diff --git a/8209375-ZGC-Use-dynamic-base-address-for-mark-stack-.patch b/8209375-ZGC-Use-dynamic-base-address-for-mark-stack-.patch deleted file mode 100644 index dfad78c3f575689a322484d1c66ab08bedeeb50b..0000000000000000000000000000000000000000 --- a/8209375-ZGC-Use-dynamic-base-address-for-mark-stack-.patch +++ /dev/null @@ -1,184 +0,0 @@ -From 476ec6be3f75c70c50bd1552c624abca098ddba2 Mon Sep 17 00:00:00 2001 -Date: Wed, 18 Mar 2020 10:25:06 +0000 -Subject: [PATCH] 8209375: ZGC: Use dynamic base address for mark stack space - -Summary: : -LLT: jdk11u/test/hotspot/jtreg/vmTestbase/gc/gctests/SoftReference/soft004/soft004.java -Bug url: https://bugs.openjdk.java.net/browse/JDK-8209375 ---- - src/hotspot/share/gc/z/zGlobals.hpp | 7 +--- - src/hotspot/share/gc/z/zMarkStack.cpp | 74 +++++++++++++++-------------------- - src/hotspot/share/gc/z/zMarkStack.hpp | 1 + - src/hotspot/share/gc/z/z_globals.hpp | 6 +-- - 4 files changed, 38 insertions(+), 50 deletions(-) - -diff --git a/src/hotspot/share/gc/z/zGlobals.hpp b/src/hotspot/share/gc/z/zGlobals.hpp -index 080ea5c0e..0f9e9dcb4 100644 ---- a/src/hotspot/share/gc/z/zGlobals.hpp -+++ b/src/hotspot/share/gc/z/zGlobals.hpp -@@ -117,11 +117,8 @@ extern uintptr_t ZAddressWeakBadMask; - // Marked state - extern uintptr_t ZAddressMetadataMarked; - --// Address space for mark stack allocations --const size_t ZMarkStackSpaceSizeShift = 40; // 1TB --const size_t ZMarkStackSpaceSize = (size_t)1 << ZMarkStackSpaceSizeShift; --const uintptr_t ZMarkStackSpaceStart = ZAddressSpaceEnd + ZMarkStackSpaceSize; --const uintptr_t ZMarkStackSpaceEnd = ZMarkStackSpaceStart + ZMarkStackSpaceSize; -+// Mark stack space -+extern uintptr_t ZMarkStackSpaceStart; - const size_t ZMarkStackSpaceExpandSize = (size_t)1 << 25; // 32M - - // Mark stack and magazine sizes -diff --git a/src/hotspot/share/gc/z/zMarkStack.cpp b/src/hotspot/share/gc/z/zMarkStack.cpp -index 52fe51ece..9cc768956 100644 ---- a/src/hotspot/share/gc/z/zMarkStack.cpp -+++ b/src/hotspot/share/gc/z/zMarkStack.cpp -@@ -28,58 +28,44 @@ - #include "gc/z/zMarkStack.inline.hpp" - #include "logging/log.hpp" - #include "runtime/atomic.hpp" -+#include "runtime/os.hpp" - #include "utilities/debug.hpp" - --#include --#include -+uintptr_t ZMarkStackSpaceStart; - - ZMarkStackSpace::ZMarkStackSpace() : - _expand_lock(), -+ _start(0), - _top(0), - _end(0) { -- assert(ZMarkStacksMax >= ZMarkStackSpaceExpandSize, "ZMarkStacksMax too small"); -- assert(ZMarkStacksMax <= ZMarkStackSpaceSize, "ZMarkStacksMax too large"); -- -+ assert(ZMarkStackSpaceLimit >= ZMarkStackSpaceExpandSize, "ZMarkStackSpaceLimit too small"); - // Reserve address space -- const void* res = mmap((void*)ZMarkStackSpaceStart, ZMarkStackSpaceSize, -- PROT_NONE, MAP_ANONYMOUS|MAP_PRIVATE|MAP_NORESERVE, -1, 0); -- if (res != (void*)ZMarkStackSpaceStart) { -- log_error(gc, marking)("Failed to reserve address space for marking stacks"); -+ const size_t size = ZMarkStackSpaceLimit; -+ const size_t alignment = (size_t)os::vm_allocation_granularity(); -+ const uintptr_t addr = (uintptr_t)os::reserve_memory(size, NULL, alignment, mtGC); -+ if (addr == 0) { -+ log_error(gc, marking)("Failed to reserve address space for mark stacks"); - return; - } - - // Successfully initialized -- _top = _end = ZMarkStackSpaceStart; --} -+ _start = _top = _end = addr; - --bool ZMarkStackSpace::is_initialized() const { -- return _top != 0; -+ // Register mark stack space start -+ ZMarkStackSpaceStart = _start; - } - --bool ZMarkStackSpace::expand() { -- const size_t max = ZMarkStackSpaceStart + ZMarkStacksMax; -- if (_end + ZMarkStackSpaceExpandSize > max) { -- // Expansion limit reached -- return false; -- } -- -- void* const res = mmap((void*)_end, ZMarkStackSpaceExpandSize, -- PROT_READ|PROT_WRITE, MAP_ANONYMOUS|MAP_PRIVATE|MAP_FIXED, -1, 0); -- if (res == MAP_FAILED) { -- ZErrno err; -- log_error(gc, marking)("Failed to map memory for marking stacks (%s)", err.to_string()); -- return false; -- } -- -- return true; -+bool ZMarkStackSpace::is_initialized() const { -+ return _start != 0; - } - - uintptr_t ZMarkStackSpace::alloc_space(size_t size) { -- uintptr_t top = _top; -+ uintptr_t top = Atomic::load(&_top); - - for (;;) { -+ const uintptr_t end = Atomic::load(&_end); - const uintptr_t new_top = top + size; -- if (new_top > _end) { -+ if (new_top > end) { - // Not enough space left - return 0; - } -@@ -104,24 +90,28 @@ uintptr_t ZMarkStackSpace::expand_and_alloc_space(size_t size) { - return addr; - } - -- // Expand stack space -- if (!expand()) { -- // We currently can't handle the situation where we -- // are running out of mark stack space. -- fatal("Mark stack overflow (allocated " SIZE_FORMAT "M, size " SIZE_FORMAT "M, max " SIZE_FORMAT "M)," -- " use -XX:ZMarkStacksMax=? to increase this limit", -- (_end - ZMarkStackSpaceStart) / M, size / M, ZMarkStacksMax / M); -- return 0; -+ // Check expansion limit -+ const size_t expand_size = ZMarkStackSpaceExpandSize; -+ const size_t old_size = _end - _start; -+ const size_t new_size = old_size + expand_size; -+ if (new_size > ZMarkStackSpaceLimit) { -+ // Expansion limit reached. This is a fatal error since we -+ // currently can't recover from running out of mark stack space. -+ fatal("Mark stack space exhausted. Use -XX:ZMarkStackSpaceLimit= to increase the " -+ "maximum number of bytes allocated for mark stacks. Current limit is " SIZE_FORMAT "M.", -+ ZMarkStackSpaceLimit / M); - } - - log_debug(gc, marking)("Expanding mark stack space: " SIZE_FORMAT "M->" SIZE_FORMAT "M", -- (_end - ZMarkStackSpaceStart) / M, -- (_end - ZMarkStackSpaceStart + ZMarkStackSpaceExpandSize) / M); -+ old_size / M, new_size / M); -+ -+ // Expand -+ os::commit_memory_or_exit((char*)_end, expand_size, false /* executable */, "Mark stack space"); - - // Increment top before end to make sure another - // thread can't steal out newly expanded space. - addr = Atomic::add(size, &_top) - size; -- _end += ZMarkStackSpaceExpandSize; -+ Atomic::add(expand_size, &_end); - - return addr; - } -diff --git a/src/hotspot/share/gc/z/zMarkStack.hpp b/src/hotspot/share/gc/z/zMarkStack.hpp -index b68b9faa3..12f3e4eca 100644 ---- a/src/hotspot/share/gc/z/zMarkStack.hpp -+++ b/src/hotspot/share/gc/z/zMarkStack.hpp -@@ -76,6 +76,7 @@ typedef ZStackList ZMarkStackMagazineList; - class ZMarkStackSpace { - private: - ZLock _expand_lock; -+ uintptr_t _start; - volatile uintptr_t _top; - volatile uintptr_t _end; - -diff --git a/src/hotspot/share/gc/z/z_globals.hpp b/src/hotspot/share/gc/z/z_globals.hpp -index 9e0f8985b..8cee59be7 100644 ---- a/src/hotspot/share/gc/z/z_globals.hpp -+++ b/src/hotspot/share/gc/z/z_globals.hpp -@@ -53,9 +53,9 @@ - "Allow Java threads to stall and wait for GC to complete " \ - "instead of immediately throwing an OutOfMemoryError") \ - \ -- product(size_t, ZMarkStacksMax, NOT_LP64(512*M) LP64_ONLY(8*G), \ -- "Maximum number of bytes allocated for marking stacks") \ -- range(32*M, NOT_LP64(512*M) LP64_ONLY(1024*G)) \ -+ product(size_t, ZMarkStackSpaceLimit, 8*G, \ -+ "Maximum number of bytes allocated for mark stacks") \ -+ range(32*M, 1024*G) \ - \ - product(uint, ZCollectionInterval, 0, \ - "Force GC at a fixed time interval (in seconds)") \ --- -2.12.3 - diff --git a/8209894-ZGC-Cap-number-of-GC-workers-based-on-heap-s.patch b/8209894-ZGC-Cap-number-of-GC-workers-based-on-heap-s.patch deleted file mode 100644 index 6ba8ad526b9d5d8380afa4977bfc0d9432eb27b8..0000000000000000000000000000000000000000 --- a/8209894-ZGC-Cap-number-of-GC-workers-based-on-heap-s.patch +++ /dev/null @@ -1,87 +0,0 @@ -From 7ca249ae82c6b6c60c524781806f9d12ef3f8f98 Mon Sep 17 00:00:00 2001 -Date: Mon, 16 Mar 2020 16:24:43 +0800 -Subject: [PATCH] 8209894: ZGC: Cap number of GC workers based on heap size - -Summary: : -LLT: jdk11u/test/hotspot/jtreg/vmTestbase/nsk/jdi/ObjectReference/disableCollection/disablecollection002/TestDescription.java -Bug url: https://bugs.openjdk.java.net/browse/JDK-8209894 ---- - src/hotspot/share/gc/z/zWorkers.cpp | 23 ++++++++++++++++++----- - src/hotspot/share/gc/z/zWorkers.hpp | 4 +--- - 2 files changed, 19 insertions(+), 8 deletions(-) - -diff --git a/src/hotspot/share/gc/z/zWorkers.cpp b/src/hotspot/share/gc/z/zWorkers.cpp -index 0686ec7af..6a0c2561d 100644 ---- a/src/hotspot/share/gc/z/zWorkers.cpp -+++ b/src/hotspot/share/gc/z/zWorkers.cpp -@@ -1,5 +1,5 @@ - /* -- * Copyright (c) 2015, 2017, Oracle and/or its affiliates. All rights reserved. -+ * Copyright (c) 2015, 2018, Oracle and/or its affiliates. All rights reserved. - * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. - * - * This code is free software; you can redistribute it and/or modify it -@@ -22,14 +22,27 @@ - */ - - #include "precompiled.hpp" -+#include "gc/z/zGlobals.hpp" - #include "gc/z/zTask.hpp" - #include "gc/z/zWorkers.inline.hpp" - #include "runtime/os.hpp" - #include "runtime/mutexLocker.hpp" - #include "runtime/safepoint.hpp" - --uint ZWorkers::calculate_ncpus(double share_in_percent) { -- return ceil(os::initial_active_processor_count() * share_in_percent / 100.0); -+static uint calculate_nworkers_based_on_ncpus(double cpu_share_in_percent) { -+ return ceil(os::initial_active_processor_count() * cpu_share_in_percent / 100.0); -+} -+ -+static uint calculate_nworkers_based_on_heap_size(double reserve_share_in_percent) { -+ const int nworkers = ((MaxHeapSize * (reserve_share_in_percent / 100.0)) - ZPageSizeMedium) / ZPageSizeSmall; -+ return MAX2(nworkers, 1); -+} -+ -+static uint calculate_nworkers(double cpu_share_in_percent) { -+ // Cap number of workers so that we never use more than 10% of the max heap -+ // for the reserve. This is useful when using small heaps on large machines. -+ return MIN2(calculate_nworkers_based_on_ncpus(cpu_share_in_percent), -+ calculate_nworkers_based_on_heap_size(10.0)); - } - - uint ZWorkers::calculate_nparallel() { -@@ -38,7 +51,7 @@ uint ZWorkers::calculate_nparallel() { - // close to the number of processors tends to lead to over-provisioning and - // scheduling latency issues. Using 60% of the active processors appears to - // be a fairly good balance. -- return calculate_ncpus(60.0); -+ return calculate_nworkers(60.0); - } - - uint ZWorkers::calculate_nconcurrent() { -@@ -48,7 +61,7 @@ uint ZWorkers::calculate_nconcurrent() { - // throughput, while using too few threads will prolong the GC-cycle and - // we then risk being out-run by the application. Using 12.5% of the active - // processors appears to be a fairly good balance. -- return calculate_ncpus(12.5); -+ return calculate_nworkers(12.5); - } - - class ZWorkersWarmupTask : public ZTask { -diff --git a/src/hotspot/share/gc/z/zWorkers.hpp b/src/hotspot/share/gc/z/zWorkers.hpp -index 36a3c61fd..6ce09c447 100644 ---- a/src/hotspot/share/gc/z/zWorkers.hpp -+++ b/src/hotspot/share/gc/z/zWorkers.hpp -@@ -34,8 +34,6 @@ private: - bool _boost; - WorkGang _workers; - -- static uint calculate_ncpus(double share_in_percent); -- - void run(ZTask* task, uint nworkers); - - public: --- -2.12.3 - diff --git a/8217856-ZGC-Break-out-C2-matching-rules-into-separat.patch b/8217856-ZGC-Break-out-C2-matching-rules-into-separat.patch deleted file mode 100644 index b88b4bfecef68c704a43f77a4050494101550597..0000000000000000000000000000000000000000 --- a/8217856-ZGC-Break-out-C2-matching-rules-into-separat.patch +++ /dev/null @@ -1,906 +0,0 @@ -diff --git a/make/hotspot/gensrc/GensrcAdlc.gmk b/make/hotspot/gensrc/GensrcAdlc.gmk -index 687896251..a39640526 100644 ---- a/make/hotspot/gensrc/GensrcAdlc.gmk -+++ b/make/hotspot/gensrc/GensrcAdlc.gmk -@@ -140,6 +140,12 @@ ifeq ($(call check-jvm-feature, compiler2), true) - $d/os_cpu/$(HOTSPOT_TARGET_OS)_$(HOTSPOT_TARGET_CPU_ARCH)/$(HOTSPOT_TARGET_OS)_$(HOTSPOT_TARGET_CPU_ARCH).ad \ - ))) - -+ ifeq ($(call check-jvm-feature, zgc), true) -+ AD_SRC_FILES += $(call uniq, $(wildcard $(foreach d, $(AD_SRC_ROOTS), \ -+ $d/cpu/$(HOTSPOT_TARGET_CPU_ARCH)/gc/z/z_$(HOTSPOT_TARGET_CPU).ad \ -+ ))) -+ endif -+ - ifeq ($(call check-jvm-feature, shenandoahgc), true) - AD_SRC_FILES += $(call uniq, $(wildcard $(foreach d, $(AD_SRC_ROOTS), \ - $d/cpu/$(HOTSPOT_TARGET_CPU_ARCH)/gc/shenandoah/shenandoah_$(HOTSPOT_TARGET_CPU).ad \ -diff --git a/src/hotspot/cpu/aarch64/aarch64.ad b/src/hotspot/cpu/aarch64/aarch64.ad -index 29f81face..ab578476a 100644 ---- a/src/hotspot/cpu/aarch64/aarch64.ad -+++ b/src/hotspot/cpu/aarch64/aarch64.ad -@@ -1128,13 +1128,6 @@ definitions %{ - int_def VOLATILE_REF_COST ( 1000, 10 * INSN_COST); - %} - --source_hpp %{ -- --#include "gc/z/c2/zBarrierSetC2.hpp" --#include "gc/z/zThreadLocalData.hpp" -- --%} -- - //----------SOURCE BLOCK------------------------------------------------------- - // This is a block of C++ code which provides values, functions, and - // definitions necessary in the rest of the architecture description -@@ -18110,243 +18103,6 @@ instruct vpopcount2I(vecD dst, vecD src) %{ - ins_pipe(pipe_class_default); - %} - --source %{ -- --static void z_load_barrier(MacroAssembler& _masm, const MachNode* node, Address ref_addr, Register ref, Register tmp, bool weak) { -- ZLoadBarrierStubC2* const stub = ZLoadBarrierStubC2::create(node, ref_addr, ref, tmp, weak); -- __ ldr(tmp, Address(rthread, ZThreadLocalData::address_bad_mask_offset())); -- __ andr(tmp, tmp, ref); -- __ cbnz(tmp, *stub->entry()); -- __ bind(*stub->continuation()); --} -- --static void z_load_barrier_slow_path(MacroAssembler& _masm, const MachNode* node, Address ref_addr, Register ref, Register tmp) { -- ZLoadBarrierStubC2* const stub = ZLoadBarrierStubC2::create(node, ref_addr, ref, tmp, false /* weak */); -- __ b(*stub->entry()); -- __ bind(*stub->continuation()); --} -- --%} -- --// Load Pointer --instruct zLoadP(iRegPNoSp dst, memory mem, rFlagsReg cr) --%{ -- match(Set dst (LoadP mem)); -- predicate(UseZGC && !needs_acquiring_load(n) && (n->as_Load()->barrier_data() == ZLoadBarrierStrong)); -- effect(TEMP dst, KILL cr); -- -- ins_cost(4 * INSN_COST); -- -- format %{ "ldr $dst, $mem" %} -- -- ins_encode %{ -- const Address ref_addr = mem2address($mem->opcode(), as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp); -- __ ldr($dst$$Register, ref_addr); -- if (barrier_data() != ZLoadBarrierElided) { -- z_load_barrier(_masm, this, ref_addr, $dst$$Register, rscratch2 /* tmp */, false /* weak */); -- } -- %} -- -- ins_pipe(iload_reg_mem); --%} -- --// Load Weak Pointer --instruct zLoadWeakP(iRegPNoSp dst, memory mem, rFlagsReg cr) --%{ -- match(Set dst (LoadP mem)); -- predicate(UseZGC && !needs_acquiring_load(n) && (n->as_Load()->barrier_data() == ZLoadBarrierWeak)); -- effect(TEMP dst, KILL cr); -- -- ins_cost(4 * INSN_COST); -- -- format %{ "ldr $dst, $mem" %} -- -- ins_encode %{ -- const Address ref_addr = mem2address($mem->opcode(), as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp); -- __ ldr($dst$$Register, ref_addr); -- z_load_barrier(_masm, this, ref_addr, $dst$$Register, rscratch2 /* tmp */, true /* weak */); -- %} -- -- ins_pipe(iload_reg_mem); --%} -- --// Load Pointer Volatile --instruct zLoadPVolatile(iRegPNoSp dst, indirect mem /* sync_memory */, rFlagsReg cr) --%{ -- match(Set dst (LoadP mem)); -- predicate(UseZGC && needs_acquiring_load(n) && n->as_Load()->barrier_data() == ZLoadBarrierStrong); -- effect(TEMP dst, KILL cr); -- -- ins_cost(VOLATILE_REF_COST); -- -- format %{ "ldar $dst, $mem\t" %} -- -- ins_encode %{ -- __ ldar($dst$$Register, $mem$$Register); -- if (barrier_data() != ZLoadBarrierElided) { -- z_load_barrier(_masm, this, Address($mem$$Register), $dst$$Register, rscratch2 /* tmp */, false /* weak */); -- } -- %} -- -- ins_pipe(pipe_serial); --%} -- --instruct zCompareAndSwapP(iRegINoSp res, indirect mem, iRegP oldval, iRegP newval, rFlagsReg cr) %{ -- match(Set res (CompareAndSwapP mem (Binary oldval newval))); -- match(Set res (WeakCompareAndSwapP mem (Binary oldval newval))); -- predicate(UseZGC && !needs_acquiring_load_exclusive(n) && n->as_LoadStore()->barrier_data() == ZLoadBarrierStrong); -- effect(KILL cr, TEMP_DEF res); -- -- ins_cost(2 * VOLATILE_REF_COST); -- -- format %{ "cmpxchg $mem, $oldval, $newval\n\t" -- "cset $res, EQ" %} -- -- ins_encode %{ -- guarantee($mem$$index == -1 && $mem$$disp == 0, "impossible encoding"); -- __ cmpxchg($mem$$Register, $oldval$$Register, $newval$$Register, Assembler::xword, -- false /* acquire */, true /* release */, false /* weak */, rscratch2); -- __ cset($res$$Register, Assembler::EQ); -- if (barrier_data() != ZLoadBarrierElided) { -- Label good; -- __ ldr(rscratch1, Address(rthread, ZThreadLocalData::address_bad_mask_offset())); -- __ andr(rscratch1, rscratch1, rscratch2); -- __ cbz(rscratch1, good); -- z_load_barrier_slow_path(_masm, this, Address($mem$$Register), rscratch2 /* ref */, rscratch1 /* tmp */); -- __ cmpxchg($mem$$Register, $oldval$$Register, $newval$$Register, Assembler::xword, -- false /* acquire */, true /* release */, false /* weak */, rscratch2); -- __ cset($res$$Register, Assembler::EQ); -- __ bind(good); -- } -- %} -- -- ins_pipe(pipe_slow); --%} -- --instruct zCompareAndSwapPAcq(iRegINoSp res, indirect mem, iRegP oldval, iRegP newval, rFlagsReg cr) %{ -- match(Set res (CompareAndSwapP mem (Binary oldval newval))); -- match(Set res (WeakCompareAndSwapP mem (Binary oldval newval))); -- predicate(UseZGC && needs_acquiring_load_exclusive(n) && (n->as_LoadStore()->barrier_data() == ZLoadBarrierStrong)); -- effect(KILL cr, TEMP_DEF res); -- -- ins_cost(2 * VOLATILE_REF_COST); -- -- format %{ "cmpxchg $mem, $oldval, $newval\n\t" -- "cset $res, EQ" %} -- -- ins_encode %{ -- guarantee($mem$$index == -1 && $mem$$disp == 0, "impossible encoding"); -- __ cmpxchg($mem$$Register, $oldval$$Register, $newval$$Register, Assembler::xword, -- true /* acquire */, true /* release */, false /* weak */, rscratch2); -- __ cset($res$$Register, Assembler::EQ); -- if (barrier_data() != ZLoadBarrierElided) { -- Label good; -- __ ldr(rscratch1, Address(rthread, ZThreadLocalData::address_bad_mask_offset())); -- __ andr(rscratch1, rscratch1, rscratch2); -- __ cbz(rscratch1, good); -- z_load_barrier_slow_path(_masm, this, Address($mem$$Register), rscratch2 /* ref */, rscratch1 /* tmp */ ); -- __ cmpxchg($mem$$Register, $oldval$$Register, $newval$$Register, Assembler::xword, -- true /* acquire */, true /* release */, false /* weak */, rscratch2); -- __ cset($res$$Register, Assembler::EQ); -- __ bind(good); -- } -- %} -- -- ins_pipe(pipe_slow); --%} -- --instruct zCompareAndExchangeP(iRegPNoSp res, indirect mem, iRegP oldval, iRegP newval, rFlagsReg cr) %{ -- match(Set res (CompareAndExchangeP mem (Binary oldval newval))); -- predicate(UseZGC && !needs_acquiring_load_exclusive(n) && n->as_LoadStore()->barrier_data() == ZLoadBarrierStrong); -- effect(TEMP_DEF res, KILL cr); -- -- ins_cost(2 * VOLATILE_REF_COST); -- -- format %{ "cmpxchg $res = $mem, $oldval, $newval" %} -- -- ins_encode %{ -- guarantee($mem$$index == -1 && $mem$$disp == 0, "impossible encoding"); -- __ cmpxchg($mem$$Register, $oldval$$Register, $newval$$Register, Assembler::xword, -- false /* acquire */, true /* release */, false /* weak */, $res$$Register); -- if (barrier_data() != ZLoadBarrierElided) { -- Label good; -- __ ldr(rscratch1, Address(rthread, ZThreadLocalData::address_bad_mask_offset())); -- __ andr(rscratch1, rscratch1, $res$$Register); -- __ cbz(rscratch1, good); -- z_load_barrier_slow_path(_masm, this, Address($mem$$Register), $res$$Register /* ref */, rscratch1 /* tmp */); -- __ cmpxchg($mem$$Register, $oldval$$Register, $newval$$Register, Assembler::xword, -- false /* acquire */, true /* release */, false /* weak */, $res$$Register); -- __ bind(good); -- } -- %} -- -- ins_pipe(pipe_slow); --%} -- --instruct zCompareAndExchangePAcq(iRegPNoSp res, indirect mem, iRegP oldval, iRegP newval, rFlagsReg cr) %{ -- match(Set res (CompareAndExchangeP mem (Binary oldval newval))); -- predicate(UseZGC && needs_acquiring_load_exclusive(n) && n->as_LoadStore()->barrier_data() == ZLoadBarrierStrong); -- effect(TEMP_DEF res, KILL cr); -- -- ins_cost(2 * VOLATILE_REF_COST); -- -- format %{ "cmpxchg $res = $mem, $oldval, $newval" %} -- -- ins_encode %{ -- guarantee($mem$$index == -1 && $mem$$disp == 0, "impossible encoding"); -- __ cmpxchg($mem$$Register, $oldval$$Register, $newval$$Register, Assembler::xword, -- true /* acquire */, true /* release */, false /* weak */, $res$$Register); -- if (barrier_data() != ZLoadBarrierElided) { -- Label good; -- __ ldr(rscratch1, Address(rthread, ZThreadLocalData::address_bad_mask_offset())); -- __ andr(rscratch1, rscratch1, $res$$Register); -- __ cbz(rscratch1, good); -- z_load_barrier_slow_path(_masm, this, Address($mem$$Register), $res$$Register /* ref */, rscratch1 /* tmp */); -- __ cmpxchg($mem$$Register, $oldval$$Register, $newval$$Register, Assembler::xword, -- true /* acquire */, true /* release */, false /* weak */, $res$$Register); -- __ bind(good); -- } -- %} -- -- ins_pipe(pipe_slow); --%} -- --instruct zGetAndSetP(indirect mem, iRegP newv, iRegPNoSp prev, rFlagsReg cr) %{ -- match(Set prev (GetAndSetP mem newv)); -- predicate(UseZGC && !needs_acquiring_load_exclusive(n) && n->as_LoadStore()->barrier_data() == ZLoadBarrierStrong); -- effect(TEMP_DEF prev, KILL cr); -- -- ins_cost(2 * VOLATILE_REF_COST); -- -- format %{ "atomic_xchg $prev, $newv, [$mem]" %} -- -- ins_encode %{ -- __ atomic_xchg($prev$$Register, $newv$$Register, $mem$$Register); -- if (barrier_data() != ZLoadBarrierElided) { -- z_load_barrier(_masm, this, Address(noreg, 0), $prev$$Register, rscratch2 /* tmp */, false /* weak */); -- } -- %} -- -- ins_pipe(pipe_serial); --%} -- --instruct zGetAndSetPAcq(indirect mem, iRegP newv, iRegPNoSp prev, rFlagsReg cr) %{ -- match(Set prev (GetAndSetP mem newv)); -- predicate(UseZGC && needs_acquiring_load_exclusive(n) && (n->as_LoadStore()->barrier_data() == ZLoadBarrierStrong)); -- effect(TEMP_DEF prev, KILL cr); -- -- ins_cost(VOLATILE_REF_COST); -- -- format %{ "atomic_xchg_acq $prev, $newv, [$mem]" %} -- -- ins_encode %{ -- __ atomic_xchgal($prev$$Register, $newv$$Register, $mem$$Register); -- if (barrier_data() != ZLoadBarrierElided) { -- z_load_barrier(_masm, this, Address(noreg, 0), $prev$$Register, rscratch2 /* tmp */, false /* weak */); -- } -- %} -- ins_pipe(pipe_serial); --%} - - //----------PEEPHOLE RULES----------------------------------------------------- - // These must follow all instruction definitions as they use the names -diff --git a/src/hotspot/cpu/aarch64/gc/z/z_aarch64.ad b/src/hotspot/cpu/aarch64/gc/z/z_aarch64.ad -new file mode 100644 -index 000000000..50cc6f924 ---- /dev/null -+++ b/src/hotspot/cpu/aarch64/gc/z/z_aarch64.ad -@@ -0,0 +1,268 @@ -+// -+// Copyright (c) 2019, Oracle and/or its affiliates. All rights reserved. -+// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. -+// -+// This code is free software; you can redistribute it and/or modify it -+// under the terms of the GNU General Public License version 2 only, as -+// published by the Free Software Foundation. -+// -+// This code is distributed in the hope that it will be useful, but WITHOUT -+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -+// version 2 for more details (a copy is included in the LICENSE file that -+// accompanied this code). -+// -+// You should have received a copy of the GNU General Public License version -+// 2 along with this work; if not, write to the Free Software Foundation, -+// Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. -+// -+// Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA -+// or visit www.oracle.com if you need additional information or have any -+// questions. -+// -+ -+source_hpp %{ -+ -+#include "gc/z/c2/zBarrierSetC2.hpp" -+#include "gc/z/zThreadLocalData.hpp" -+ -+%} -+ -+source %{ -+ -+static void z_load_barrier(MacroAssembler& _masm, const MachNode* node, Address ref_addr, Register ref, Register tmp, bool weak) { -+ ZLoadBarrierStubC2* const stub = ZLoadBarrierStubC2::create(node, ref_addr, ref, tmp, weak); -+ __ ldr(tmp, Address(rthread, ZThreadLocalData::address_bad_mask_offset())); -+ __ andr(tmp, tmp, ref); -+ __ cbnz(tmp, *stub->entry()); -+ __ bind(*stub->continuation()); -+} -+ -+static void z_load_barrier_slow_path(MacroAssembler& _masm, const MachNode* node, Address ref_addr, Register ref, Register tmp) { -+ ZLoadBarrierStubC2* const stub = ZLoadBarrierStubC2::create(node, ref_addr, ref, tmp, false /* weak */); -+ __ b(*stub->entry()); -+ __ bind(*stub->continuation()); -+} -+ -+%} -+ -+// Load Pointer -+instruct zLoadP(iRegPNoSp dst, memory mem, rFlagsReg cr) -+%{ -+ match(Set dst (LoadP mem)); -+ predicate(UseZGC && !needs_acquiring_load(n) && (n->as_Load()->barrier_data() == ZLoadBarrierStrong)); -+ effect(TEMP dst, KILL cr); -+ -+ ins_cost(4 * INSN_COST); -+ -+ format %{ "ldr $dst, $mem" %} -+ -+ ins_encode %{ -+ const Address ref_addr = mem2address($mem->opcode(), as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp); -+ __ ldr($dst$$Register, ref_addr); -+ if (barrier_data() != ZLoadBarrierElided) { -+ z_load_barrier(_masm, this, ref_addr, $dst$$Register, rscratch2 /* tmp */, false /* weak */); -+ } -+ %} -+ -+ ins_pipe(iload_reg_mem); -+%} -+ -+// Load Weak Pointer -+instruct zLoadWeakP(iRegPNoSp dst, memory mem, rFlagsReg cr) -+%{ -+ match(Set dst (LoadP mem)); -+ predicate(UseZGC && !needs_acquiring_load(n) && (n->as_Load()->barrier_data() == ZLoadBarrierWeak)); -+ effect(TEMP dst, KILL cr); -+ -+ ins_cost(4 * INSN_COST); -+ -+ format %{ "ldr $dst, $mem" %} -+ -+ ins_encode %{ -+ const Address ref_addr = mem2address($mem->opcode(), as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp); -+ __ ldr($dst$$Register, ref_addr); -+ z_load_barrier(_masm, this, ref_addr, $dst$$Register, rscratch2 /* tmp */, true /* weak */); -+ %} -+ -+ ins_pipe(iload_reg_mem); -+%} -+ -+// Load Pointer Volatile -+instruct zLoadPVolatile(iRegPNoSp dst, indirect mem /* sync_memory */, rFlagsReg cr) -+%{ -+ match(Set dst (LoadP mem)); -+ predicate(UseZGC && needs_acquiring_load(n) && n->as_Load()->barrier_data() == ZLoadBarrierStrong); -+ effect(TEMP dst, KILL cr); -+ -+ ins_cost(VOLATILE_REF_COST); -+ -+ format %{ "ldar $dst, $mem\t" %} -+ -+ ins_encode %{ -+ __ ldar($dst$$Register, $mem$$Register); -+ if (barrier_data() != ZLoadBarrierElided) { -+ z_load_barrier(_masm, this, Address($mem$$Register), $dst$$Register, rscratch2 /* tmp */, false /* weak */); -+ } -+ %} -+ -+ ins_pipe(pipe_serial); -+%} -+ -+instruct zCompareAndSwapP(iRegINoSp res, indirect mem, iRegP oldval, iRegP newval, rFlagsReg cr) %{ -+ match(Set res (CompareAndSwapP mem (Binary oldval newval))); -+ match(Set res (WeakCompareAndSwapP mem (Binary oldval newval))); -+ predicate(UseZGC && !needs_acquiring_load_exclusive(n) && n->as_LoadStore()->barrier_data() == ZLoadBarrierStrong); -+ effect(KILL cr, TEMP_DEF res); -+ -+ ins_cost(2 * VOLATILE_REF_COST); -+ -+ format %{ "cmpxchg $mem, $oldval, $newval\n\t" -+ "cset $res, EQ" %} -+ -+ ins_encode %{ -+ guarantee($mem$$index == -1 && $mem$$disp == 0, "impossible encoding"); -+ __ cmpxchg($mem$$Register, $oldval$$Register, $newval$$Register, Assembler::xword, -+ false /* acquire */, true /* release */, false /* weak */, rscratch2); -+ __ cset($res$$Register, Assembler::EQ); -+ if (barrier_data() != ZLoadBarrierElided) { -+ Label good; -+ __ ldr(rscratch1, Address(rthread, ZThreadLocalData::address_bad_mask_offset())); -+ __ andr(rscratch1, rscratch1, rscratch2); -+ __ cbz(rscratch1, good); -+ z_load_barrier_slow_path(_masm, this, Address($mem$$Register), rscratch2 /* ref */, rscratch1 /* tmp */); -+ __ cmpxchg($mem$$Register, $oldval$$Register, $newval$$Register, Assembler::xword, -+ false /* acquire */, true /* release */, false /* weak */, rscratch2); -+ __ cset($res$$Register, Assembler::EQ); -+ __ bind(good); -+ } -+ %} -+ -+ ins_pipe(pipe_slow); -+%} -+ -+instruct zCompareAndSwapPAcq(iRegINoSp res, indirect mem, iRegP oldval, iRegP newval, rFlagsReg cr) %{ -+ match(Set res (CompareAndSwapP mem (Binary oldval newval))); -+ match(Set res (WeakCompareAndSwapP mem (Binary oldval newval))); -+ predicate(UseZGC && needs_acquiring_load_exclusive(n) && (n->as_LoadStore()->barrier_data() == ZLoadBarrierStrong)); -+ effect(KILL cr, TEMP_DEF res); -+ -+ ins_cost(2 * VOLATILE_REF_COST); -+ -+ format %{ "cmpxchg $mem, $oldval, $newval\n\t" -+ "cset $res, EQ" %} -+ -+ ins_encode %{ -+ guarantee($mem$$index == -1 && $mem$$disp == 0, "impossible encoding"); -+ __ cmpxchg($mem$$Register, $oldval$$Register, $newval$$Register, Assembler::xword, -+ true /* acquire */, true /* release */, false /* weak */, rscratch2); -+ __ cset($res$$Register, Assembler::EQ); -+ if (barrier_data() != ZLoadBarrierElided) { -+ Label good; -+ __ ldr(rscratch1, Address(rthread, ZThreadLocalData::address_bad_mask_offset())); -+ __ andr(rscratch1, rscratch1, rscratch2); -+ __ cbz(rscratch1, good); -+ z_load_barrier_slow_path(_masm, this, Address($mem$$Register), rscratch2 /* ref */, rscratch1 /* tmp */ ); -+ __ cmpxchg($mem$$Register, $oldval$$Register, $newval$$Register, Assembler::xword, -+ true /* acquire */, true /* release */, false /* weak */, rscratch2); -+ __ cset($res$$Register, Assembler::EQ); -+ __ bind(good); -+ } -+ %} -+ -+ ins_pipe(pipe_slow); -+%} -+ -+instruct zCompareAndExchangeP(iRegPNoSp res, indirect mem, iRegP oldval, iRegP newval, rFlagsReg cr) %{ -+ match(Set res (CompareAndExchangeP mem (Binary oldval newval))); -+ predicate(UseZGC && !needs_acquiring_load_exclusive(n) && n->as_LoadStore()->barrier_data() == ZLoadBarrierStrong); -+ effect(TEMP_DEF res, KILL cr); -+ -+ ins_cost(2 * VOLATILE_REF_COST); -+ -+ format %{ "cmpxchg $res = $mem, $oldval, $newval" %} -+ -+ ins_encode %{ -+ guarantee($mem$$index == -1 && $mem$$disp == 0, "impossible encoding"); -+ __ cmpxchg($mem$$Register, $oldval$$Register, $newval$$Register, Assembler::xword, -+ false /* acquire */, true /* release */, false /* weak */, $res$$Register); -+ if (barrier_data() != ZLoadBarrierElided) { -+ Label good; -+ __ ldr(rscratch1, Address(rthread, ZThreadLocalData::address_bad_mask_offset())); -+ __ andr(rscratch1, rscratch1, $res$$Register); -+ __ cbz(rscratch1, good); -+ z_load_barrier_slow_path(_masm, this, Address($mem$$Register), $res$$Register /* ref */, rscratch1 /* tmp */); -+ __ cmpxchg($mem$$Register, $oldval$$Register, $newval$$Register, Assembler::xword, -+ false /* acquire */, true /* release */, false /* weak */, $res$$Register); -+ __ bind(good); -+ } -+ %} -+ -+ ins_pipe(pipe_slow); -+%} -+ -+instruct zCompareAndExchangePAcq(iRegPNoSp res, indirect mem, iRegP oldval, iRegP newval, rFlagsReg cr) %{ -+ match(Set res (CompareAndExchangeP mem (Binary oldval newval))); -+ predicate(UseZGC && needs_acquiring_load_exclusive(n) && n->as_LoadStore()->barrier_data() == ZLoadBarrierStrong); -+ effect(TEMP_DEF res, KILL cr); -+ -+ ins_cost(2 * VOLATILE_REF_COST); -+ -+ format %{ "cmpxchg $res = $mem, $oldval, $newval" %} -+ -+ ins_encode %{ -+ guarantee($mem$$index == -1 && $mem$$disp == 0, "impossible encoding"); -+ __ cmpxchg($mem$$Register, $oldval$$Register, $newval$$Register, Assembler::xword, -+ true /* acquire */, true /* release */, false /* weak */, $res$$Register); -+ if (barrier_data() != ZLoadBarrierElided) { -+ Label good; -+ __ ldr(rscratch1, Address(rthread, ZThreadLocalData::address_bad_mask_offset())); -+ __ andr(rscratch1, rscratch1, $res$$Register); -+ __ cbz(rscratch1, good); -+ z_load_barrier_slow_path(_masm, this, Address($mem$$Register), $res$$Register /* ref */, rscratch1 /* tmp */); -+ __ cmpxchg($mem$$Register, $oldval$$Register, $newval$$Register, Assembler::xword, -+ true /* acquire */, true /* release */, false /* weak */, $res$$Register); -+ __ bind(good); -+ } -+ %} -+ -+ ins_pipe(pipe_slow); -+%} -+ -+instruct zGetAndSetP(indirect mem, iRegP newv, iRegPNoSp prev, rFlagsReg cr) %{ -+ match(Set prev (GetAndSetP mem newv)); -+ predicate(UseZGC && !needs_acquiring_load_exclusive(n) && n->as_LoadStore()->barrier_data() == ZLoadBarrierStrong); -+ effect(TEMP_DEF prev, KILL cr); -+ -+ ins_cost(2 * VOLATILE_REF_COST); -+ -+ format %{ "atomic_xchg $prev, $newv, [$mem]" %} -+ -+ ins_encode %{ -+ __ atomic_xchg($prev$$Register, $newv$$Register, $mem$$Register); -+ if (barrier_data() != ZLoadBarrierElided) { -+ z_load_barrier(_masm, this, Address(noreg, 0), $prev$$Register, rscratch2 /* tmp */, false /* weak */); -+ } -+ %} -+ -+ ins_pipe(pipe_serial); -+%} -+ -+instruct zGetAndSetPAcq(indirect mem, iRegP newv, iRegPNoSp prev, rFlagsReg cr) %{ -+ match(Set prev (GetAndSetP mem newv)); -+ predicate(UseZGC && needs_acquiring_load_exclusive(n) && (n->as_LoadStore()->barrier_data() == ZLoadBarrierStrong)); -+ effect(TEMP_DEF prev, KILL cr); -+ -+ ins_cost(VOLATILE_REF_COST); -+ -+ format %{ "atomic_xchg_acq $prev, $newv, [$mem]" %} -+ -+ ins_encode %{ -+ __ atomic_xchgal($prev$$Register, $newv$$Register, $mem$$Register); -+ if (barrier_data() != ZLoadBarrierElided) { -+ z_load_barrier(_masm, this, Address(noreg, 0), $prev$$Register, rscratch2 /* tmp */, false /* weak */); -+ } -+ %} -+ ins_pipe(pipe_serial); -+%} -+ -diff --git a/src/hotspot/cpu/x86/gc/z/z_x86_64.ad b/src/hotspot/cpu/x86/gc/z/z_x86_64.ad -new file mode 100644 -index 000000000..38c2e926b ---- /dev/null -+++ b/src/hotspot/cpu/x86/gc/z/z_x86_64.ad -@@ -0,0 +1,168 @@ -+// -+// Copyright (c) 2015, 2019, Oracle and/or its affiliates. All rights reserved. -+// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. -+// -+// This code is free software; you can redistribute it and/or modify it -+// under the terms of the GNU General Public License version 2 only, as -+// published by the Free Software Foundation. -+// -+// This code is distributed in the hope that it will be useful, but WITHOUT -+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -+// version 2 for more details (a copy is included in the LICENSE file that -+// accompanied this code). -+// -+// You should have received a copy of the GNU General Public License version -+// 2 along with this work; if not, write to the Free Software Foundation, -+// Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. -+// -+// Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA -+// or visit www.oracle.com if you need additional information or have any -+// questions. -+// -+ -+source_hpp %{ -+ -+#include "gc/z/c2/zBarrierSetC2.hpp" -+#include "gc/z/zThreadLocalData.hpp" -+ -+%} -+ -+source %{ -+ -+static void z_load_barrier(MacroAssembler& _masm, const MachNode* node, Address ref_addr, Register ref, Register tmp, bool weak) { -+ ZLoadBarrierStubC2* const stub = ZLoadBarrierStubC2::create(node, ref_addr, ref, tmp, weak); -+ __ testptr(ref, Address(r15_thread, ZThreadLocalData::address_bad_mask_offset())); -+ __ jcc(Assembler::notZero, *stub->entry()); -+ __ bind(*stub->continuation()); -+} -+ -+static void z_load_barrier_slow_path(MacroAssembler& _masm, const MachNode* node, Address ref_addr, Register ref, Register tmp) { -+ ZLoadBarrierStubC2* const stub = ZLoadBarrierStubC2::create(node, ref_addr, ref, tmp, false /* weak */); -+ __ jmp(*stub->entry()); -+ __ bind(*stub->continuation()); -+} -+ -+%} -+ -+// Load Pointer -+instruct zLoadP(rRegP dst, memory mem, rFlagsReg cr) -+%{ -+ predicate(UseZGC && n->as_Load()->barrier_data() == ZLoadBarrierStrong); -+ match(Set dst (LoadP mem)); -+ effect(KILL cr, TEMP dst); -+ -+ ins_cost(125); -+ -+ format %{ "movq $dst, $mem" %} -+ -+ ins_encode %{ -+ __ movptr($dst$$Register, $mem$$Address); -+ if (barrier_data() != ZLoadBarrierElided) { -+ z_load_barrier(_masm, this, $mem$$Address, $dst$$Register, noreg /* tmp */, false /* weak */); -+ } -+ %} -+ -+ ins_pipe(ialu_reg_mem); -+%} -+ -+// Load Weak Pointer -+instruct zLoadWeakP(rRegP dst, memory mem, rFlagsReg cr) -+%{ -+ predicate(UseZGC && n->as_Load()->barrier_data() == ZLoadBarrierWeak); -+ match(Set dst (LoadP mem)); -+ effect(KILL cr, TEMP dst); -+ -+ ins_cost(125); -+ -+ format %{ "movq $dst, $mem" %} -+ -+ ins_encode %{ -+ __ movptr($dst$$Register, $mem$$Address); -+ z_load_barrier(_masm, this, $mem$$Address, $dst$$Register, noreg /* tmp */, true /* weak */); -+ %} -+ -+ ins_pipe(ialu_reg_mem); -+%} -+ -+instruct zCompareAndExchangeP(memory mem, rax_RegP oldval, rRegP newval, rRegP tmp, rFlagsReg cr) %{ -+ match(Set oldval (CompareAndExchangeP mem (Binary oldval newval))); -+ predicate(UseZGC && n->as_LoadStore()->barrier_data() == ZLoadBarrierStrong); -+ effect(KILL cr, TEMP tmp); -+ -+ format %{ "lock\n\t" -+ "cmpxchgq $newval, $mem" %} -+ -+ ins_encode %{ -+ if (barrier_data() != ZLoadBarrierElided) { -+ __ movptr($tmp$$Register, $oldval$$Register); -+ } -+ __ lock(); -+ __ cmpxchgptr($newval$$Register, $mem$$Address); -+ if (barrier_data() != ZLoadBarrierElided) { -+ Label good; -+ __ testptr($oldval$$Register, Address(r15_thread, ZThreadLocalData::address_bad_mask_offset())); -+ __ jcc(Assembler::zero, good); -+ z_load_barrier_slow_path(_masm, this, $mem$$Address, $oldval$$Register, $tmp$$Register); -+ __ movptr($oldval$$Register, $tmp$$Register); -+ __ lock(); -+ __ cmpxchgptr($newval$$Register, $mem$$Address); -+ __ bind(good); -+ } -+ %} -+ -+ ins_pipe(pipe_cmpxchg); -+%} -+ -+instruct zCompareAndSwapP(rRegI res, memory mem, rRegP newval, rRegP tmp, rFlagsReg cr, rax_RegP oldval) %{ -+ match(Set res (CompareAndSwapP mem (Binary oldval newval))); -+ match(Set res (WeakCompareAndSwapP mem (Binary oldval newval))); -+ predicate(UseZGC && n->as_LoadStore()->barrier_data() == ZLoadBarrierStrong); -+ effect(KILL cr, KILL oldval, TEMP tmp); -+ -+ format %{ "lock\n\t" -+ "cmpxchgq $newval, $mem\n\t" -+ "sete $res\n\t" -+ "movzbl $res, $res" %} -+ -+ ins_encode %{ -+ if (barrier_data() != ZLoadBarrierElided) { -+ __ movptr($tmp$$Register, $oldval$$Register); -+ } -+ __ lock(); -+ __ cmpxchgptr($newval$$Register, $mem$$Address); -+ if (barrier_data() != ZLoadBarrierElided) { -+ Label good; -+ __ testptr($oldval$$Register, Address(r15_thread, ZThreadLocalData::address_bad_mask_offset())); -+ __ jcc(Assembler::zero, good); -+ z_load_barrier_slow_path(_masm, this, $mem$$Address, $oldval$$Register, $tmp$$Register); -+ __ movptr($oldval$$Register, $tmp$$Register); -+ __ lock(); -+ __ cmpxchgptr($newval$$Register, $mem$$Address); -+ __ bind(good); -+ __ cmpptr($tmp$$Register, $oldval$$Register); -+ } -+ __ setb(Assembler::equal, $res$$Register); -+ __ movzbl($res$$Register, $res$$Register); -+ %} -+ -+ ins_pipe(pipe_cmpxchg); -+%} -+ -+instruct zXChgP(memory mem, rRegP newval, rFlagsReg cr) %{ -+ match(Set newval (GetAndSetP mem newval)); -+ predicate(UseZGC && n->as_LoadStore()->barrier_data() == ZLoadBarrierStrong); -+ effect(KILL cr); -+ -+ format %{ "xchgq $newval, $mem" %} -+ -+ ins_encode %{ -+ __ xchgptr($newval$$Register, $mem$$Address); -+ if (barrier_data() != ZLoadBarrierElided) { -+ z_load_barrier(_masm, this, Address(noreg, 0), $newval$$Register, noreg /* tmp */, false /* weak */); -+ } -+ %} -+ -+ ins_pipe(pipe_cmpxchg); -+%} -+ -diff --git a/src/hotspot/cpu/x86/x86_64.ad b/src/hotspot/cpu/x86/x86_64.ad -index 95a8538f3..ede4d8864 100644 ---- a/src/hotspot/cpu/x86/x86_64.ad -+++ b/src/hotspot/cpu/x86/x86_64.ad -@@ -538,19 +538,6 @@ reg_class int_rdi_reg(RDI); - - %} - --source_hpp %{ -- --#include "gc/z/c2/zBarrierSetC2.hpp" --#include "gc/z/zThreadLocalData.hpp" -- --%} -- --source_hpp %{ --#if INCLUDE_ZGC --#include "gc/z/zBarrierSetAssembler.hpp" --#endif --%} -- - //----------SOURCE BLOCK------------------------------------------------------- - // This is a block of C++ code which provides values, functions, and - // definitions necessary in the rest of the architecture description -@@ -1882,19 +1869,6 @@ const RegMask Matcher::method_handle_invoke_SP_save_mask() { - return NO_REG_mask(); - } - --static void z_load_barrier(MacroAssembler& _masm, const MachNode* node, Address ref_addr, Register ref, Register tmp, bool weak) { -- ZLoadBarrierStubC2* const stub = ZLoadBarrierStubC2::create(node, ref_addr, ref, tmp, weak); -- __ testptr(ref, Address(r15_thread, ZThreadLocalData::address_bad_mask_offset())); -- __ jcc(Assembler::notZero, *stub->entry()); -- __ bind(*stub->continuation()); --} -- --static void z_load_barrier_slow_path(MacroAssembler& _masm, const MachNode* node, Address ref_addr, Register ref, Register tmp) { -- ZLoadBarrierStubC2* const stub = ZLoadBarrierStubC2::create(node, ref_addr, ref, tmp, false /* weak */); -- __ jmp(*stub->entry()); -- __ bind(*stub->continuation()); --} -- - %} - - //----------ENCODING BLOCK----------------------------------------------------- -@@ -12845,131 +12819,6 @@ instruct RethrowException() - ins_pipe(pipe_jmp); - %} - --// --// Execute ZGC load barrier (strong) slow path --// -- --// Load Pointer --instruct zLoadP(rRegP dst, memory mem, rFlagsReg cr) --%{ -- predicate(UseZGC && n->as_Load()->barrier_data() == ZLoadBarrierStrong); -- match(Set dst (LoadP mem)); -- effect(KILL cr, TEMP dst); -- -- ins_cost(125); -- -- format %{ "movq $dst, $mem" %} -- -- ins_encode %{ -- __ movptr($dst$$Register, $mem$$Address); -- if (barrier_data() != ZLoadBarrierElided) { -- z_load_barrier(_masm, this, $mem$$Address, $dst$$Register, noreg /* tmp */, false /* weak */); -- } -- %} -- -- ins_pipe(ialu_reg_mem); --%} -- --// Load Weak Pointer --instruct zLoadWeakP(rRegP dst, memory mem, rFlagsReg cr) --%{ -- predicate(UseZGC && n->as_Load()->barrier_data() == ZLoadBarrierWeak); -- match(Set dst (LoadP mem)); -- effect(KILL cr, TEMP dst); -- -- ins_cost(125); -- -- format %{ "movq $dst, $mem" %} -- ins_encode %{ -- __ movptr($dst$$Register, $mem$$Address); -- z_load_barrier(_masm, this, $mem$$Address, $dst$$Register, noreg /* tmp */, true /* weak */); -- %} -- -- ins_pipe(ialu_reg_mem); --%} -- --instruct zCompareAndExchangeP(memory mem, rax_RegP oldval, rRegP newval, rRegP tmp, rFlagsReg cr) %{ -- match(Set oldval (CompareAndExchangeP mem (Binary oldval newval))); -- predicate(UseZGC && n->as_LoadStore()->barrier_data() == ZLoadBarrierStrong); -- effect(KILL cr, TEMP tmp); -- -- format %{ "lock\n\t" -- "cmpxchgq $newval, $mem" %} -- -- ins_encode %{ -- if (barrier_data() != ZLoadBarrierElided) { -- __ movptr($tmp$$Register, $oldval$$Register); -- } -- __ lock(); -- __ cmpxchgptr($newval$$Register, $mem$$Address); -- if (barrier_data() != ZLoadBarrierElided) { -- Label good; -- __ testptr($oldval$$Register, Address(r15_thread, ZThreadLocalData::address_bad_mask_offset())); -- __ jcc(Assembler::zero, good); -- z_load_barrier_slow_path(_masm, this, $mem$$Address, $oldval$$Register, $tmp$$Register); -- __ movptr($oldval$$Register, $tmp$$Register); -- __ lock(); -- __ cmpxchgptr($newval$$Register, $mem$$Address); -- __ bind(good); -- } -- %} -- -- ins_pipe(pipe_cmpxchg); --%} -- -- --instruct zCompareAndSwapP(rRegI res, memory mem, rRegP newval, rRegP tmp, rFlagsReg cr, rax_RegP oldval) %{ -- match(Set res (CompareAndSwapP mem (Binary oldval newval))); -- match(Set res (WeakCompareAndSwapP mem (Binary oldval newval))); -- predicate(UseZGC && n->as_LoadStore()->barrier_data() == ZLoadBarrierStrong); -- effect(KILL cr, KILL oldval, TEMP tmp); -- -- format %{ "lock\n\t" -- "cmpxchgq $newval, $mem\n\t" -- "sete $res\n\t" -- "movzbl $res, $res" %} -- -- ins_encode %{ -- if (barrier_data() != ZLoadBarrierElided) { -- __ movptr($tmp$$Register, $oldval$$Register); -- } -- __ lock(); -- __ cmpxchgptr($newval$$Register, $mem$$Address); -- if (barrier_data() != ZLoadBarrierElided) { -- Label good; -- __ testptr($oldval$$Register, Address(r15_thread, ZThreadLocalData::address_bad_mask_offset())); -- __ jcc(Assembler::zero, good); -- z_load_barrier_slow_path(_masm, this, $mem$$Address, $oldval$$Register, $tmp$$Register); -- __ movptr($oldval$$Register, $tmp$$Register); -- __ lock(); -- __ cmpxchgptr($newval$$Register, $mem$$Address); -- __ bind(good); -- __ cmpptr($tmp$$Register, $oldval$$Register); -- } -- __ setb(Assembler::equal, $res$$Register); -- __ movzbl($res$$Register, $res$$Register); -- %} -- -- ins_pipe(pipe_cmpxchg); --%} -- --instruct zXChgP(memory mem, rRegP newval, rFlagsReg cr) %{ -- match(Set newval (GetAndSetP mem newval)); -- predicate(UseZGC && n->as_LoadStore()->barrier_data() == ZLoadBarrierStrong); -- effect(KILL cr); -- -- format %{ "xchgq $newval, $mem" %} -- -- ins_encode %{ -- __ xchgptr($newval$$Register, $mem$$Address); -- if (barrier_data() != ZLoadBarrierElided) { -- z_load_barrier(_masm, this, Address(noreg, 0), $newval$$Register, noreg /* tmp */, false /* weak */); -- } -- %} -- -- ins_pipe(pipe_cmpxchg); --%} -- - // ============================================================================ - // This name is KNOWN by the ADLC and cannot be changed. - // The ADLC forces a 'TypeRawPtr::BOTTOM' output type --- -2.19.0 - diff --git a/8231441-1-AArch64-Initial-SVE-backend-support.patch b/8231441-1-AArch64-Initial-SVE-backend-support.patch index 183a8c91e2659a6adef92648234ba4b1a9402dfd..cb002807c51cc28000a84c3fcf5f022c1ec9f282 100755 --- a/8231441-1-AArch64-Initial-SVE-backend-support.patch +++ b/8231441-1-AArch64-Initial-SVE-backend-support.patch @@ -308,8 +308,8 @@ index 643e3d564..82e615241 100644 static int cpu_revision() { return _revision; } + static int get_initial_sve_vector_length() { return _initial_sve_vector_length; }; - static bool is_zva_enabled() { return 0 <= _zva_length; } - static int zva_length() { + static bool is_hisi_enabled() { + if (_cpu == CPU_HISILICON && (_model == 0xd01 || _model == 0xd02 || _model == 0xd03)) { diff --git a/test/hotspot/jtreg/compiler/c2/aarch64/TestSVEWithJNI.java b/test/hotspot/jtreg/compiler/c2/aarch64/TestSVEWithJNI.java new file mode 100644 index 000000000..dc15ca800 diff --git a/8233061-ZGC-Enforce-memory-ordering-in-segmented-bit.patch b/8233061-ZGC-Enforce-memory-ordering-in-segmented-bit.patch deleted file mode 100644 index a851739d97fdc092a60bde940517b6971e27ed4d..0000000000000000000000000000000000000000 --- a/8233061-ZGC-Enforce-memory-ordering-in-segmented-bit.patch +++ /dev/null @@ -1,101 +0,0 @@ -From d2137837d518a8bdb8e075109e502e78bd2f9fa9 Mon Sep 17 00:00:00 2001 -Date: Wed, 19 Feb 2020 17:36:32 +0800 -Subject: [PATCH] 8233061: ZGC: Enforce memory ordering in segmented bit maps - -Summary: : -LLT: renaissance -Bug url: https://bugs.openjdk.java.net/browse/JDK-8233061 ---- - src/hotspot/share/gc/z/zLiveMap.cpp | 20 +++++++++----------- - src/hotspot/share/gc/z/zLiveMap.inline.hpp | 9 +++++---- - 2 files changed, 14 insertions(+), 15 deletions(-) - -diff --git a/src/hotspot/share/gc/z/zLiveMap.cpp b/src/hotspot/share/gc/z/zLiveMap.cpp -index 7187b6166..c1d79b794 100644 ---- a/src/hotspot/share/gc/z/zLiveMap.cpp -+++ b/src/hotspot/share/gc/z/zLiveMap.cpp -@@ -50,7 +50,9 @@ void ZLiveMap::reset(size_t index) { - - // Multiple threads can enter here, make sure only one of them - // resets the marking information while the others busy wait. -- for (uint32_t seqnum = _seqnum; seqnum != ZGlobalSeqNum; seqnum = _seqnum) { -+ for (uint32_t seqnum = OrderAccess::load_acquire(&_seqnum); -+ seqnum != ZGlobalSeqNum; -+ seqnum = OrderAccess::load_acquire(&_seqnum)) { - if ((seqnum != seqnum_initializing) && - (Atomic::cmpxchg(seqnum_initializing, &_seqnum, seqnum) == seqnum)) { - // Reset marking information -@@ -61,13 +63,13 @@ void ZLiveMap::reset(size_t index) { - segment_live_bits().clear(); - segment_claim_bits().clear(); - -- // Make sure the newly reset marking information is -- // globally visible before updating the page seqnum. -- OrderAccess::storestore(); -- -- // Update seqnum - assert(_seqnum == seqnum_initializing, "Invalid"); -- _seqnum = ZGlobalSeqNum; -+ -+ // Make sure the newly reset marking information is ordered -+ // before the update of the page seqnum, such that when the -+ // up-to-date seqnum is load acquired, the bit maps will not -+ // contain stale information. -+ OrderAccess::release_store(&_seqnum, ZGlobalSeqNum); - break; - } - -@@ -89,10 +91,6 @@ void ZLiveMap::reset_segment(BitMap::idx_t segment) { - if (!claim_segment(segment)) { - // Already claimed, wait for live bit to be set - while (!is_segment_live(segment)) { -- // Busy wait. The loadload barrier is needed to make -- // sure we re-read the live bit every time we loop. -- OrderAccess::loadload(); -- - // Mark reset contention - if (!contention) { - // Count contention once -diff --git a/src/hotspot/share/gc/z/zLiveMap.inline.hpp b/src/hotspot/share/gc/z/zLiveMap.inline.hpp -index 1e4d56f41..fb45a892c 100644 ---- a/src/hotspot/share/gc/z/zLiveMap.inline.hpp -+++ b/src/hotspot/share/gc/z/zLiveMap.inline.hpp -@@ -30,6 +30,7 @@ - #include "gc/z/zOop.inline.hpp" - #include "gc/z/zUtils.inline.hpp" - #include "runtime/atomic.hpp" -+#include "runtime/orderAccess.hpp" - #include "utilities/bitMap.inline.hpp" - #include "utilities/debug.hpp" - -@@ -38,7 +39,7 @@ inline void ZLiveMap::reset() { - } - - inline bool ZLiveMap::is_marked() const { -- return _seqnum == ZGlobalSeqNum; -+ return OrderAccess::load_acquire(&_seqnum) == ZGlobalSeqNum; - } - - inline uint32_t ZLiveMap::live_objects() const { -@@ -68,15 +69,15 @@ inline BitMapView ZLiveMap::segment_claim_bits() { - } - - inline bool ZLiveMap::is_segment_live(BitMap::idx_t segment) const { -- return segment_live_bits().at(segment); -+ return segment_live_bits().par_at(segment); - } - - inline bool ZLiveMap::set_segment_live_atomic(BitMap::idx_t segment) { -- return segment_live_bits().par_set_bit(segment); -+ return segment_live_bits().par_set_bit(segment, memory_order_release); - } - - inline bool ZLiveMap::claim_segment(BitMap::idx_t segment) { -- return segment_claim_bits().par_set_bit(segment); -+ return segment_claim_bits().par_set_bit(segment, memory_order_acq_rel); - } - - inline BitMap::idx_t ZLiveMap::first_live_segment() const { --- -2.12.3 - diff --git a/8233073-Make-BitMap-accessors-more-memory-ordering-f.patch b/8233073-Make-BitMap-accessors-more-memory-ordering-f.patch deleted file mode 100644 index 5e1f19e24c3be12d23568387071d29b8bd473c03..0000000000000000000000000000000000000000 --- a/8233073-Make-BitMap-accessors-more-memory-ordering-f.patch +++ /dev/null @@ -1,162 +0,0 @@ -diff --git a/src/hotspot/share/c1/c1_Instruction.cpp b/src/hotspot/share/c1/c1_Instruction.cpp -index ee3be89..62d8b48 100644 ---- a/src/hotspot/share/c1/c1_Instruction.cpp -+++ b/src/hotspot/share/c1/c1_Instruction.cpp -@@ -29,6 +29,7 @@ - #include "c1/c1_ValueStack.hpp" - #include "ci/ciObjArrayKlass.hpp" - #include "ci/ciTypeArrayKlass.hpp" -+#include "utilities/bitMap.inline.hpp" - - - // Implementation of Instruction -diff --git a/src/hotspot/share/opto/graphKit.cpp b/src/hotspot/share/opto/graphKit.cpp -index bf9179f..e0696de 100644 ---- a/src/hotspot/share/opto/graphKit.cpp -+++ b/src/hotspot/share/opto/graphKit.cpp -@@ -43,6 +43,7 @@ - #include "opto/runtime.hpp" - #include "runtime/deoptimization.hpp" - #include "runtime/sharedRuntime.hpp" -+#include "utilities/bitMap.inline.hpp" - #include "utilities/macros.hpp" - #if INCLUDE_SHENANDOAHGC - #include "gc/shenandoah/c2/shenandoahBarrierSetC2.hpp" -diff --git a/src/hotspot/share/opto/parse1.cpp b/src/hotspot/share/opto/parse1.cpp -index 99b1a67..f94f028 100644 ---- a/src/hotspot/share/opto/parse1.cpp -+++ b/src/hotspot/share/opto/parse1.cpp -@@ -41,6 +41,7 @@ - #include "runtime/handles.inline.hpp" - #include "runtime/safepointMechanism.hpp" - #include "runtime/sharedRuntime.hpp" -+#include "utilities/bitMap.inline.hpp" - #include "utilities/copy.hpp" - - // Static array so we can figure out which bytecodes stop us from compiling -diff --git a/src/hotspot/share/utilities/bitMap.hpp b/src/hotspot/share/utilities/bitMap.hpp -index c671535..e26f346 100644 ---- a/src/hotspot/share/utilities/bitMap.hpp -+++ b/src/hotspot/share/utilities/bitMap.hpp -@@ -26,6 +26,7 @@ - #define SHARE_VM_UTILITIES_BITMAP_HPP - - #include "memory/allocation.hpp" -+#include "runtime/atomic.hpp" - #include "utilities/align.hpp" - #include "utilities/globalDefinitions.hpp" - -@@ -95,6 +96,8 @@ class BitMap { - void set_word (idx_t word) { set_word(word, ~(bm_word_t)0); } - void clear_word(idx_t word) { _map[word] = 0; } - -+ static inline const bm_word_t load_word_ordered(const volatile bm_word_t* const addr, atomic_memory_order memory_order); -+ - // Utilities for ranges of bits. Ranges are half-open [beg, end). - - // Ranges within a single word. -@@ -194,6 +197,9 @@ class BitMap { - return (*word_addr(index) & bit_mask(index)) != 0; - } - -+ // memory_order must be memory_order_relaxed or memory_order_acquire. -+ bool par_at(idx_t index, atomic_memory_order memory_order = memory_order_acquire) const; -+ - // Align bit index up or down to the next bitmap word boundary, or check - // alignment. - static idx_t word_align_up(idx_t bit) { -@@ -210,9 +216,14 @@ class BitMap { - inline void set_bit(idx_t bit); - inline void clear_bit(idx_t bit); - -- // Atomically set or clear the specified bit. -- inline bool par_set_bit(idx_t bit); -- inline bool par_clear_bit(idx_t bit); -+ // Attempts to change a bit to a desired value. The operation returns true if -+ // this thread changed the value of the bit. It was changed with a RMW operation -+ // using the specified memory_order. The operation returns false if the change -+ // could not be set due to the bit already being observed in the desired state. -+ // The atomic access that observed the bit in the desired state has acquire -+ // semantics, unless memory_order is memory_order_relaxed or memory_order_release. -+ inline bool par_set_bit(idx_t bit, atomic_memory_order memory_order = memory_order_conservative); -+ inline bool par_clear_bit(idx_t bit, atomic_memory_order memory_order = memory_order_conservative); - - // Put the given value at the given offset. The parallel version - // will CAS the value into the bitmap and is quite a bit slower. -diff --git a/src/hotspot/share/utilities/bitMap.inline.hpp b/src/hotspot/share/utilities/bitMap.inline.hpp -index b10726d..7a7e2ad 100644 ---- a/src/hotspot/share/utilities/bitMap.inline.hpp -+++ b/src/hotspot/share/utilities/bitMap.inline.hpp -@@ -26,6 +26,7 @@ - #define SHARE_VM_UTILITIES_BITMAP_INLINE_HPP - - #include "runtime/atomic.hpp" -+#include "runtime/orderAccess.hpp" - #include "utilities/bitMap.hpp" - - inline void BitMap::set_bit(idx_t bit) { -@@ -38,18 +39,39 @@ inline void BitMap::clear_bit(idx_t bit) { - *word_addr(bit) &= ~bit_mask(bit); - } - --inline bool BitMap::par_set_bit(idx_t bit) { -+inline const BitMap::bm_word_t BitMap::load_word_ordered(const volatile bm_word_t* const addr, atomic_memory_order memory_order) { -+ if (memory_order == memory_order_relaxed || memory_order == memory_order_release) { -+ return Atomic::load(addr); -+ } else { -+ assert(memory_order == memory_order_acq_rel || -+ memory_order == memory_order_acquire || -+ memory_order == memory_order_conservative, -+ "unexpected memory ordering"); -+ return OrderAccess::load_acquire(addr); -+ } -+} -+ -+inline bool BitMap::par_at(idx_t index, atomic_memory_order memory_order) const { -+ verify_index(index); -+ assert(memory_order == memory_order_acquire || -+ memory_order == memory_order_relaxed, -+ "unexpected memory ordering"); -+ const volatile bm_word_t* const addr = word_addr(index); -+ return (load_word_ordered(addr, memory_order) & bit_mask(index)) != 0; -+} -+ -+inline bool BitMap::par_set_bit(idx_t bit, atomic_memory_order memory_order) { - verify_index(bit); - volatile bm_word_t* const addr = word_addr(bit); - const bm_word_t mask = bit_mask(bit); -- bm_word_t old_val = *addr; -+ bm_word_t old_val = load_word_ordered(addr, memory_order); - - do { - const bm_word_t new_val = old_val | mask; - if (new_val == old_val) { - return false; // Someone else beat us to it. - } -- const bm_word_t cur_val = Atomic::cmpxchg(new_val, addr, old_val); -+ const bm_word_t cur_val = Atomic::cmpxchg(new_val, addr, old_val, memory_order); - if (cur_val == old_val) { - return true; // Success. - } -@@ -57,18 +79,18 @@ inline bool BitMap::par_set_bit(idx_t bit) { - } while (true); - } - --inline bool BitMap::par_clear_bit(idx_t bit) { -+inline bool BitMap::par_clear_bit(idx_t bit, atomic_memory_order memory_order) { - verify_index(bit); - volatile bm_word_t* const addr = word_addr(bit); - const bm_word_t mask = ~bit_mask(bit); -- bm_word_t old_val = *addr; -+ bm_word_t old_val = load_word_ordered(addr, memory_order); - - do { - const bm_word_t new_val = old_val & mask; - if (new_val == old_val) { - return false; // Someone else beat us to it. - } -- const bm_word_t cur_val = Atomic::cmpxchg(new_val, addr, old_val); -+ const bm_word_t cur_val = Atomic::cmpxchg(new_val, addr, old_val, memory_order); - if (cur_val == old_val) { - return true; // Success. - } diff --git a/8233506-ZGC-the-load-for-Reference.get-can-be-conver.patch b/8233506-ZGC-the-load-for-Reference.get-can-be-conver.patch deleted file mode 100644 index 9c07ceaf73973bbf9d50ca88435f9de01d43c2bf..0000000000000000000000000000000000000000 --- a/8233506-ZGC-the-load-for-Reference.get-can-be-conver.patch +++ /dev/null @@ -1,472 +0,0 @@ -From aa824cddc917b1fcac41a0efe5e8c794f2d5cff9 Mon Sep 17 00:00:00 2001 -Date: Thu, 26 Mar 2020 16:17:45 +0000 -Subject: [PATCH] 8233506:ZGC: the load for Reference.get() can be converted to - a load for strong refs Summary: : LLT: JDK8233506 - Bug url: https://bugs.openjdk.java.net/browse/JDK-8233506 - ---- - src/hotspot/share/gc/shared/c2/barrierSetC2.cpp | 73 +++++++++++++++---------- - src/hotspot/share/gc/shared/c2/barrierSetC2.hpp | 7 ++- - src/hotspot/share/gc/z/c2/zBarrierSetC2.cpp | 42 +++++--------- - src/hotspot/share/opto/graphKit.cpp | 9 +-- - src/hotspot/share/opto/graphKit.hpp | 10 ++-- - src/hotspot/share/opto/memnode.cpp | 9 ++- - src/hotspot/share/opto/memnode.hpp | 7 ++- - 7 files changed, 85 insertions(+), 72 deletions(-) - -diff --git a/src/hotspot/share/gc/shared/c2/barrierSetC2.cpp b/src/hotspot/share/gc/shared/c2/barrierSetC2.cpp -index 545275644..48fe04b08 100644 ---- a/src/hotspot/share/gc/shared/c2/barrierSetC2.cpp -+++ b/src/hotspot/share/gc/shared/c2/barrierSetC2.cpp -@@ -115,10 +115,13 @@ Node* BarrierSetC2::load_at_resolved(C2Access& access, const Type* val_type) con - - Node* load; - if (in_native) { -- load = kit->make_load(control, adr, val_type, access.type(), mo); -+ load = kit->make_load(control, adr, val_type, access.type(), mo, dep, -+ requires_atomic_access, unaligned, -+ mismatched, unsafe, access.barrier_data()); - } else { - load = kit->make_load(control, adr, val_type, access.type(), adr_type, mo, -- dep, requires_atomic_access, unaligned, mismatched, unsafe); -+ dep, requires_atomic_access, unaligned, mismatched, unsafe, -+ access.barrier_data()); - } - - access.set_raw_access(load); -@@ -348,28 +351,28 @@ Node* BarrierSetC2::atomic_cmpxchg_val_at_resolved(C2AtomicAccess& access, Node* - if (adr->bottom_type()->is_ptr_to_narrowoop()) { - Node *newval_enc = kit->gvn().transform(new EncodePNode(new_val, new_val->bottom_type()->make_narrowoop())); - Node *oldval_enc = kit->gvn().transform(new EncodePNode(expected_val, expected_val->bottom_type()->make_narrowoop())); -- load_store = kit->gvn().transform(new CompareAndExchangeNNode(kit->control(), mem, adr, newval_enc, oldval_enc, adr_type, value_type->make_narrowoop(), mo)); -+ load_store = new CompareAndExchangeNNode(kit->control(), mem, adr, newval_enc, oldval_enc, adr_type, value_type->make_narrowoop(), mo); - } else - #endif - { -- load_store = kit->gvn().transform(new CompareAndExchangePNode(kit->control(), mem, adr, new_val, expected_val, adr_type, value_type->is_oopptr(), mo)); -+ load_store = new CompareAndExchangePNode(kit->control(), mem, adr, new_val, expected_val, adr_type, value_type->is_oopptr(), mo); - } - } else { - switch (access.type()) { - case T_BYTE: { -- load_store = kit->gvn().transform(new CompareAndExchangeBNode(kit->control(), mem, adr, new_val, expected_val, adr_type, mo)); -+ load_store = new CompareAndExchangeBNode(kit->control(), mem, adr, new_val, expected_val, adr_type, mo); - break; - } - case T_SHORT: { -- load_store = kit->gvn().transform(new CompareAndExchangeSNode(kit->control(), mem, adr, new_val, expected_val, adr_type, mo)); -+ load_store = new CompareAndExchangeSNode(kit->control(), mem, adr, new_val, expected_val, adr_type, mo); - break; - } - case T_INT: { -- load_store = kit->gvn().transform(new CompareAndExchangeINode(kit->control(), mem, adr, new_val, expected_val, adr_type, mo)); -+ load_store = new CompareAndExchangeINode(kit->control(), mem, adr, new_val, expected_val, adr_type, mo); - break; - } - case T_LONG: { -- load_store = kit->gvn().transform(new CompareAndExchangeLNode(kit->control(), mem, adr, new_val, expected_val, adr_type, mo)); -+ load_store = new CompareAndExchangeLNode(kit->control(), mem, adr, new_val, expected_val, adr_type, mo); - break; - } - default: -@@ -377,6 +380,9 @@ Node* BarrierSetC2::atomic_cmpxchg_val_at_resolved(C2AtomicAccess& access, Node* - } - } - -+ load_store->as_LoadStore()->set_barrier_data(access.barrier_data()); -+ load_store = kit->gvn().transform(load_store); -+ - access.set_raw_access(load_store); - pin_atomic_op(access); - -@@ -405,50 +411,50 @@ Node* BarrierSetC2::atomic_cmpxchg_bool_at_resolved(C2AtomicAccess& access, Node - Node *newval_enc = kit->gvn().transform(new EncodePNode(new_val, new_val->bottom_type()->make_narrowoop())); - Node *oldval_enc = kit->gvn().transform(new EncodePNode(expected_val, expected_val->bottom_type()->make_narrowoop())); - if (is_weak_cas) { -- load_store = kit->gvn().transform(new WeakCompareAndSwapNNode(kit->control(), mem, adr, newval_enc, oldval_enc, mo)); -+ load_store = new WeakCompareAndSwapNNode(kit->control(), mem, adr, newval_enc, oldval_enc, mo); - } else { -- load_store = kit->gvn().transform(new CompareAndSwapNNode(kit->control(), mem, adr, newval_enc, oldval_enc, mo)); -+ load_store = new CompareAndSwapNNode(kit->control(), mem, adr, newval_enc, oldval_enc, mo); - } - } else - #endif - { - if (is_weak_cas) { -- load_store = kit->gvn().transform(new WeakCompareAndSwapPNode(kit->control(), mem, adr, new_val, expected_val, mo)); -+ load_store = new WeakCompareAndSwapPNode(kit->control(), mem, adr, new_val, expected_val, mo); - } else { -- load_store = kit->gvn().transform(new CompareAndSwapPNode(kit->control(), mem, adr, new_val, expected_val, mo)); -+ load_store = new CompareAndSwapPNode(kit->control(), mem, adr, new_val, expected_val, mo); - } - } - } else { - switch(access.type()) { - case T_BYTE: { - if (is_weak_cas) { -- load_store = kit->gvn().transform(new WeakCompareAndSwapBNode(kit->control(), mem, adr, new_val, expected_val, mo)); -+ load_store = new WeakCompareAndSwapBNode(kit->control(), mem, adr, new_val, expected_val, mo); - } else { -- load_store = kit->gvn().transform(new CompareAndSwapBNode(kit->control(), mem, adr, new_val, expected_val, mo)); -+ load_store = new CompareAndSwapBNode(kit->control(), mem, adr, new_val, expected_val, mo); - } - break; - } - case T_SHORT: { - if (is_weak_cas) { -- load_store = kit->gvn().transform(new WeakCompareAndSwapSNode(kit->control(), mem, adr, new_val, expected_val, mo)); -+ load_store = new WeakCompareAndSwapSNode(kit->control(), mem, adr, new_val, expected_val, mo); - } else { -- load_store = kit->gvn().transform(new CompareAndSwapSNode(kit->control(), mem, adr, new_val, expected_val, mo)); -+ load_store = new CompareAndSwapSNode(kit->control(), mem, adr, new_val, expected_val, mo); - } - break; - } - case T_INT: { - if (is_weak_cas) { -- load_store = kit->gvn().transform(new WeakCompareAndSwapINode(kit->control(), mem, adr, new_val, expected_val, mo)); -+ load_store = new WeakCompareAndSwapINode(kit->control(), mem, adr, new_val, expected_val, mo); - } else { -- load_store = kit->gvn().transform(new CompareAndSwapINode(kit->control(), mem, adr, new_val, expected_val, mo)); -+ load_store = new CompareAndSwapINode(kit->control(), mem, adr, new_val, expected_val, mo); - } - break; - } - case T_LONG: { - if (is_weak_cas) { -- load_store = kit->gvn().transform(new WeakCompareAndSwapLNode(kit->control(), mem, adr, new_val, expected_val, mo)); -+ load_store = new WeakCompareAndSwapLNode(kit->control(), mem, adr, new_val, expected_val, mo); - } else { -- load_store = kit->gvn().transform(new CompareAndSwapLNode(kit->control(), mem, adr, new_val, expected_val, mo)); -+ load_store = new CompareAndSwapLNode(kit->control(), mem, adr, new_val, expected_val, mo); - } - break; - } -@@ -457,6 +463,9 @@ Node* BarrierSetC2::atomic_cmpxchg_bool_at_resolved(C2AtomicAccess& access, Node - } - } - -+ load_store->as_LoadStore()->set_barrier_data(access.barrier_data()); -+ load_store = kit->gvn().transform(load_store); -+ - access.set_raw_access(load_store); - pin_atomic_op(access); - -@@ -478,27 +487,30 @@ Node* BarrierSetC2::atomic_xchg_at_resolved(C2AtomicAccess& access, Node* new_va - } else - #endif - { -- load_store = kit->gvn().transform(new GetAndSetPNode(kit->control(), mem, adr, new_val, adr_type, value_type->is_oopptr())); -+ load_store = new GetAndSetPNode(kit->control(), mem, adr, new_val, adr_type, value_type->is_oopptr()); - } - } else { - switch (access.type()) { - case T_BYTE: -- load_store = kit->gvn().transform(new GetAndSetBNode(kit->control(), mem, adr, new_val, adr_type)); -+ load_store = new GetAndSetBNode(kit->control(), mem, adr, new_val, adr_type); - break; - case T_SHORT: -- load_store = kit->gvn().transform(new GetAndSetSNode(kit->control(), mem, adr, new_val, adr_type)); -+ load_store = new GetAndSetSNode(kit->control(), mem, adr, new_val, adr_type); - break; - case T_INT: -- load_store = kit->gvn().transform(new GetAndSetINode(kit->control(), mem, adr, new_val, adr_type)); -+ load_store = new GetAndSetINode(kit->control(), mem, adr, new_val, adr_type); - break; - case T_LONG: -- load_store = kit->gvn().transform(new GetAndSetLNode(kit->control(), mem, adr, new_val, adr_type)); -+ load_store = new GetAndSetLNode(kit->control(), mem, adr, new_val, adr_type); - break; - default: - ShouldNotReachHere(); - } - } - -+ load_store->as_LoadStore()->set_barrier_data(access.barrier_data()); -+ load_store = kit->gvn().transform(load_store); -+ - access.set_raw_access(load_store); - pin_atomic_op(access); - -@@ -520,21 +532,24 @@ Node* BarrierSetC2::atomic_add_at_resolved(C2AtomicAccess& access, Node* new_val - - switch(access.type()) { - case T_BYTE: -- load_store = kit->gvn().transform(new GetAndAddBNode(kit->control(), mem, adr, new_val, adr_type)); -+ load_store = new GetAndAddBNode(kit->control(), mem, adr, new_val, adr_type); - break; - case T_SHORT: -- load_store = kit->gvn().transform(new GetAndAddSNode(kit->control(), mem, adr, new_val, adr_type)); -+ load_store = new GetAndAddSNode(kit->control(), mem, adr, new_val, adr_type); - break; - case T_INT: -- load_store = kit->gvn().transform(new GetAndAddINode(kit->control(), mem, adr, new_val, adr_type)); -+ load_store = new GetAndAddINode(kit->control(), mem, adr, new_val, adr_type); - break; - case T_LONG: -- load_store = kit->gvn().transform(new GetAndAddLNode(kit->control(), mem, adr, new_val, adr_type)); -+ load_store = new GetAndAddLNode(kit->control(), mem, adr, new_val, adr_type); - break; - default: - ShouldNotReachHere(); - } - -+ load_store->as_LoadStore()->set_barrier_data(access.barrier_data()); -+ load_store = kit->gvn().transform(load_store); -+ - access.set_raw_access(load_store); - pin_atomic_op(access); - -diff --git a/src/hotspot/share/gc/shared/c2/barrierSetC2.hpp b/src/hotspot/share/gc/shared/c2/barrierSetC2.hpp -index 487988bd8..8b4be7d11 100644 ---- a/src/hotspot/share/gc/shared/c2/barrierSetC2.hpp -+++ b/src/hotspot/share/gc/shared/c2/barrierSetC2.hpp -@@ -96,6 +96,7 @@ protected: - Node* _base; - C2AccessValuePtr& _addr; - Node* _raw_access; -+ uint8_t _barrier_data; - - void fixup_decorators(); - void* barrier_set_state() const; -@@ -108,7 +109,8 @@ public: - _type(type), - _base(base), - _addr(addr), -- _raw_access(NULL) -+ _raw_access(NULL), -+ _barrier_data(0) - { - fixup_decorators(); - } -@@ -122,6 +124,9 @@ public: - bool is_raw() const { return (_decorators & AS_RAW) != 0; } - Node* raw_access() const { return _raw_access; } - -+ uint8_t barrier_data() const { return _barrier_data; } -+ void set_barrier_data(uint8_t data) { _barrier_data = data; } -+ - void set_raw_access(Node* raw_access) { _raw_access = raw_access; } - virtual void set_memory() {} // no-op for normal accesses, but not for atomic accesses. - -diff --git a/src/hotspot/share/gc/z/c2/zBarrierSetC2.cpp b/src/hotspot/share/gc/z/c2/zBarrierSetC2.cpp -index a12973464..e178761a0 100644 ---- a/src/hotspot/share/gc/z/c2/zBarrierSetC2.cpp -+++ b/src/hotspot/share/gc/z/c2/zBarrierSetC2.cpp -@@ -174,48 +174,36 @@ int ZBarrierSetC2::estimate_stub_size() const { - return size; - } - --static bool barrier_needed(C2Access access) { -- return ZBarrierSet::barrier_needed(access.decorators(), access.type()); --} -- --Node* ZBarrierSetC2::load_at_resolved(C2Access& access, const Type* val_type) const { -- Node* result = BarrierSetC2::load_at_resolved(access, val_type); -- if (barrier_needed(access) && access.raw_access()->is_Mem()) { -- if ((access.decorators() & ON_WEAK_OOP_REF) != 0) { -- access.raw_access()->as_Load()->set_barrier_data(ZLoadBarrierWeak); -+static void set_barrier_data(C2Access& access) { -+ if (ZBarrierSet::barrier_needed(access.decorators(), access.type())) { -+ if (access.decorators() & ON_WEAK_OOP_REF) { -+ access.set_barrier_data(ZLoadBarrierWeak); - } else { -- access.raw_access()->as_Load()->set_barrier_data(ZLoadBarrierStrong); -+ access.set_barrier_data(ZLoadBarrierStrong); - } - } -+} - -- return result; -+Node* ZBarrierSetC2::load_at_resolved(C2Access& access, const Type* val_type) const { -+ set_barrier_data(access); -+ return BarrierSetC2::load_at_resolved(access, val_type); - } - - Node* ZBarrierSetC2::atomic_cmpxchg_val_at_resolved(C2AtomicAccess& access, Node* expected_val, - Node* new_val, const Type* val_type) const { -- Node* result = BarrierSetC2::atomic_cmpxchg_val_at_resolved(access, expected_val, new_val, val_type); -- if (barrier_needed(access)) { -- access.raw_access()->as_LoadStore()->set_barrier_data(ZLoadBarrierStrong); -- } -- return result; -+ set_barrier_data(access); -+ return BarrierSetC2::atomic_cmpxchg_val_at_resolved(access, expected_val, new_val, val_type); - } - - Node* ZBarrierSetC2::atomic_cmpxchg_bool_at_resolved(C2AtomicAccess& access, Node* expected_val, - Node* new_val, const Type* value_type) const { -- Node* result = BarrierSetC2::atomic_cmpxchg_bool_at_resolved(access, expected_val, new_val, value_type); -- if (barrier_needed(access)) { -- access.raw_access()->as_LoadStore()->set_barrier_data(ZLoadBarrierStrong); -- } -- return result; -- -+ set_barrier_data(access); -+ return BarrierSetC2::atomic_cmpxchg_bool_at_resolved(access, expected_val, new_val, value_type); - } - - Node* ZBarrierSetC2::atomic_xchg_at_resolved(C2AtomicAccess& access, Node* new_val, const Type* val_type) const { -- Node* result = BarrierSetC2::atomic_xchg_at_resolved(access, new_val, val_type); -- if (barrier_needed(access)) { -- access.raw_access()->as_LoadStore()->set_barrier_data(ZLoadBarrierStrong); -- } -- return result; -+ set_barrier_data(access); -+ return BarrierSetC2::atomic_xchg_at_resolved(access, new_val, val_type); - } - - bool ZBarrierSetC2::array_copy_requires_gc_barriers(BasicType type) const { -diff --git a/src/hotspot/share/opto/graphKit.cpp b/src/hotspot/share/opto/graphKit.cpp -index 7bf2f6cfb..a1547b42f 100644 ---- a/src/hotspot/share/opto/graphKit.cpp -+++ b/src/hotspot/share/opto/graphKit.cpp -@@ -1493,18 +1493,19 @@ Node* GraphKit::make_load(Node* ctl, Node* adr, const Type* t, BasicType bt, - bool require_atomic_access, - bool unaligned, - bool mismatched, -- bool unsafe) { -+ bool unsafe, -+ uint8_t barrier_data) { - assert(adr_idx != Compile::AliasIdxTop, "use other make_load factory" ); - const TypePtr* adr_type = NULL; // debug-mode-only argument - debug_only(adr_type = C->get_adr_type(adr_idx)); - Node* mem = memory(adr_idx); - Node* ld; - if (require_atomic_access && bt == T_LONG) { -- ld = LoadLNode::make_atomic(ctl, mem, adr, adr_type, t, mo, control_dependency, unaligned, mismatched, unsafe); -+ ld = LoadLNode::make_atomic(ctl, mem, adr, adr_type, t, mo, control_dependency, unaligned, mismatched, unsafe, barrier_data); - } else if (require_atomic_access && bt == T_DOUBLE) { -- ld = LoadDNode::make_atomic(ctl, mem, adr, adr_type, t, mo, control_dependency, unaligned, mismatched, unsafe); -+ ld = LoadDNode::make_atomic(ctl, mem, adr, adr_type, t, mo, control_dependency, unaligned, mismatched, unsafe, barrier_data); - } else { -- ld = LoadNode::make(_gvn, ctl, mem, adr, adr_type, t, bt, mo, control_dependency, unaligned, mismatched, unsafe); -+ ld = LoadNode::make(_gvn, ctl, mem, adr, adr_type, t, bt, mo, control_dependency, unaligned, mismatched, unsafe, barrier_data); - } - ld = _gvn.transform(ld); - if (((bt == T_OBJECT) && C->do_escape_analysis()) || C->eliminate_boxing()) { -diff --git a/src/hotspot/share/opto/graphKit.hpp b/src/hotspot/share/opto/graphKit.hpp -index 07c20bbd5..df5d18ccc 100644 ---- a/src/hotspot/share/opto/graphKit.hpp -+++ b/src/hotspot/share/opto/graphKit.hpp -@@ -518,27 +518,27 @@ class GraphKit : public Phase { - Node* make_load(Node* ctl, Node* adr, const Type* t, BasicType bt, - MemNode::MemOrd mo, LoadNode::ControlDependency control_dependency = LoadNode::DependsOnlyOnTest, - bool require_atomic_access = false, bool unaligned = false, -- bool mismatched = false, bool unsafe = false) { -+ bool mismatched = false, bool unsafe = false, uint8_t barrier_data = 0) { - // This version computes alias_index from bottom_type - return make_load(ctl, adr, t, bt, adr->bottom_type()->is_ptr(), - mo, control_dependency, require_atomic_access, -- unaligned, mismatched, unsafe); -+ unaligned, mismatched, unsafe, barrier_data); - } - Node* make_load(Node* ctl, Node* adr, const Type* t, BasicType bt, const TypePtr* adr_type, - MemNode::MemOrd mo, LoadNode::ControlDependency control_dependency = LoadNode::DependsOnlyOnTest, - bool require_atomic_access = false, bool unaligned = false, -- bool mismatched = false, bool unsafe = false) { -+ bool mismatched = false, bool unsafe = false, uint8_t barrier_data = 0) { - // This version computes alias_index from an address type - assert(adr_type != NULL, "use other make_load factory"); - return make_load(ctl, adr, t, bt, C->get_alias_index(adr_type), - mo, control_dependency, require_atomic_access, -- unaligned, mismatched, unsafe); -+ unaligned, mismatched, unsafe, barrier_data); - } - // This is the base version which is given an alias index. - Node* make_load(Node* ctl, Node* adr, const Type* t, BasicType bt, int adr_idx, - MemNode::MemOrd mo, LoadNode::ControlDependency control_dependency = LoadNode::DependsOnlyOnTest, - bool require_atomic_access = false, bool unaligned = false, -- bool mismatched = false, bool unsafe = false); -+ bool mismatched = false, bool unsafe = false, uint8_t barrier_data = 0); - - // Create & transform a StoreNode and store the effect into the - // parser's memory state. -diff --git a/src/hotspot/share/opto/memnode.cpp b/src/hotspot/share/opto/memnode.cpp -index ee0f09e11..ff0a5726c 100644 ---- a/src/hotspot/share/opto/memnode.cpp -+++ b/src/hotspot/share/opto/memnode.cpp -@@ -808,7 +808,7 @@ bool LoadNode::is_immutable_value(Node* adr) { - //----------------------------LoadNode::make----------------------------------- - // Polymorphic factory method: - Node *LoadNode::make(PhaseGVN& gvn, Node *ctl, Node *mem, Node *adr, const TypePtr* adr_type, const Type *rt, BasicType bt, MemOrd mo, -- ControlDependency control_dependency, bool unaligned, bool mismatched, bool unsafe) { -+ ControlDependency control_dependency, bool unaligned, bool mismatched, bool unsafe, uint8_t barrier_data) { - Compile* C = gvn.C; - - // sanity check the alias category against the created node type -@@ -859,6 +859,7 @@ Node *LoadNode::make(PhaseGVN& gvn, Node *ctl, Node *mem, Node *adr, const TypeP - if (unsafe) { - load->set_unsafe_access(); - } -+ load->set_barrier_data(barrier_data); - if (load->Opcode() == Op_LoadN) { - Node* ld = gvn.transform(load); - return new DecodeNNode(ld, ld->bottom_type()->make_ptr()); -@@ -868,7 +869,7 @@ Node *LoadNode::make(PhaseGVN& gvn, Node *ctl, Node *mem, Node *adr, const TypeP - } - - LoadLNode* LoadLNode::make_atomic(Node* ctl, Node* mem, Node* adr, const TypePtr* adr_type, const Type* rt, MemOrd mo, -- ControlDependency control_dependency, bool unaligned, bool mismatched, bool unsafe) { -+ ControlDependency control_dependency, bool unaligned, bool mismatched, bool unsafe, uint8_t barrier_data) { - bool require_atomic = true; - LoadLNode* load = new LoadLNode(ctl, mem, adr, adr_type, rt->is_long(), mo, control_dependency, require_atomic); - if (unaligned) { -@@ -880,11 +881,12 @@ LoadLNode* LoadLNode::make_atomic(Node* ctl, Node* mem, Node* adr, const TypePtr - if (unsafe) { - load->set_unsafe_access(); - } -+ load->set_barrier_data(barrier_data); - return load; - } - - LoadDNode* LoadDNode::make_atomic(Node* ctl, Node* mem, Node* adr, const TypePtr* adr_type, const Type* rt, MemOrd mo, -- ControlDependency control_dependency, bool unaligned, bool mismatched, bool unsafe) { -+ ControlDependency control_dependency, bool unaligned, bool mismatched, bool unsafe, uint8_t barrier_data) { - bool require_atomic = true; - LoadDNode* load = new LoadDNode(ctl, mem, adr, adr_type, rt, mo, control_dependency, require_atomic); - if (unaligned) { -@@ -896,6 +898,7 @@ LoadDNode* LoadDNode::make_atomic(Node* ctl, Node* mem, Node* adr, const TypePtr - if (unsafe) { - load->set_unsafe_access(); - } -+ load->set_barrier_data(barrier_data); - return load; - } - -diff --git a/src/hotspot/share/opto/memnode.hpp b/src/hotspot/share/opto/memnode.hpp -index 7468abdbc..14a4a67c6 100644 ---- a/src/hotspot/share/opto/memnode.hpp -+++ b/src/hotspot/share/opto/memnode.hpp -@@ -227,7 +227,8 @@ public: - static Node* make(PhaseGVN& gvn, Node *c, Node *mem, Node *adr, - const TypePtr* at, const Type *rt, BasicType bt, - MemOrd mo, ControlDependency control_dependency = DependsOnlyOnTest, -- bool unaligned = false, bool mismatched = false, bool unsafe = false); -+ bool unaligned = false, bool mismatched = false, bool unsafe = false, -+ uint8_t barrier_data = 0); - - virtual uint hash() const; // Check the type - -@@ -408,7 +409,7 @@ public: - bool require_atomic_access() const { return _require_atomic_access; } - static LoadLNode* make_atomic(Node* ctl, Node* mem, Node* adr, const TypePtr* adr_type, - const Type* rt, MemOrd mo, ControlDependency control_dependency = DependsOnlyOnTest, -- bool unaligned = false, bool mismatched = false, bool unsafe = false); -+ bool unaligned = false, bool mismatched = false, bool unsafe = false, uint8_t barrier_data = 0); - #ifndef PRODUCT - virtual void dump_spec(outputStream *st) const { - LoadNode::dump_spec(st); -@@ -460,7 +461,7 @@ public: - bool require_atomic_access() const { return _require_atomic_access; } - static LoadDNode* make_atomic(Node* ctl, Node* mem, Node* adr, const TypePtr* adr_type, - const Type* rt, MemOrd mo, ControlDependency control_dependency = DependsOnlyOnTest, -- bool unaligned = false, bool mismatched = false, bool unsafe = false); -+ bool unaligned = false, bool mismatched = false, bool unsafe = false, uint8_t barrier_data = 0); - #ifndef PRODUCT - virtual void dump_spec(outputStream *st) const { - LoadNode::dump_spec(st); --- -2.12.3 - diff --git a/Add-KAE-implementation.patch b/Add-KAE-implementation.patch index db5193ad1e4cc9000d4ab544cacccf47b1e0404b..f91f5ba9473c880f53e1e6ccdcce569b01e723f4 100644 --- a/Add-KAE-implementation.patch +++ b/Add-KAE-implementation.patch @@ -158,8 +158,8 @@ index 6672d26a5..c3e8ceb35 100644 +JDKOPT_DETECT_KAE JDKOPT_DETECT_INTREE_EC - JDKOPT_ENABLE_DISABLE_FAILURE_HANDLER - JDKOPT_ENABLE_DISABLE_GENERATE_CLASSLIST + LIB_TESTS_ENABLE_DISABLE_FAILURE_HANDLER + diff --git a/make/autoconf/jdk-options.m4 b/make/autoconf/jdk-options.m4 index 9d64b31bf..e20eafa60 100644 --- a/make/autoconf/jdk-options.m4 diff --git a/Cache-byte-when-constructing-String-with-duplicate-c.patch b/Cache-byte-when-constructing-String-with-duplicate-c.patch new file mode 100644 index 0000000000000000000000000000000000000000..3170c0c09e52b35e9d05c3d5d8e68af100b47c29 --- /dev/null +++ b/Cache-byte-when-constructing-String-with-duplicate-c.patch @@ -0,0 +1,113 @@ +--- + src/hotspot/share/prims/unsafe.cpp | 6 ++++++ + src/hotspot/share/runtime/globals.hpp | 5 +++++ + .../share/classes/java/lang/StringUTF16.java | 19 +++++++++++++++++++ + .../classes/jdk/internal/misc/Unsafe.java | 1 + + 4 files changed, 31 insertions(+) + +diff --git a/src/hotspot/share/prims/unsafe.cpp b/src/hotspot/share/prims/unsafe.cpp +index 91328cd19..37d46225f 100644 +--- a/src/hotspot/share/prims/unsafe.cpp ++++ b/src/hotspot/share/prims/unsafe.cpp +@@ -1007,6 +1007,11 @@ UNSAFE_ENTRY(jint, Unsafe_GetLoadAverage0(JNIEnv *env, jobject unsafe, jdoubleAr + return ret; + } UNSAFE_END + ++UNSAFE_ENTRY(jboolean, Unsafe_GetUseCharCache(JNIEnv *env, jobject unsafe)) { ++ return UseCharCache; ++} ++UNSAFE_END ++ + UNSAFE_ENTRY(jboolean, Unsafe_GetUseHashMapIntegerCache(JNIEnv *env, jobject unsafe)) { + return UseHashMapIntegerCache; + } +@@ -1102,6 +1107,7 @@ static JNINativeMethod jdk_internal_misc_Unsafe_methods[] = { + {CC "isBigEndian0", CC "()Z", FN_PTR(Unsafe_isBigEndian0)}, + {CC "unalignedAccess0", CC "()Z", FN_PTR(Unsafe_unalignedAccess0)}, + ++ {CC "getUseCharCache", CC "()Z", FN_PTR(Unsafe_GetUseCharCache)}, + {CC "getUseHashMapIntegerCache", CC "()Z", FN_PTR(Unsafe_GetUseHashMapIntegerCache)}, + {CC "getUseFastSerializer", CC "()Z", FN_PTR(Unsafe_GetUseFastSerializer)}, + +diff --git a/src/hotspot/share/runtime/globals.hpp b/src/hotspot/share/runtime/globals.hpp +index e2bfd0c5b..40acb29b4 100644 +--- a/src/hotspot/share/runtime/globals.hpp ++++ b/src/hotspot/share/runtime/globals.hpp +@@ -2691,6 +2691,11 @@ define_pd_global(uint64_t,MaxRAM, 1ULL*G); + "the HashMap Value type, indexed by the unboxed int key value." \ + "faster in execution, higher in memory consumption.") \ + \ ++ experimental(bool, UseCharCache, false, \ ++ "When char[] is frequently used to build strings, " \ ++ "and char[] has a lot of duplicate data, using char cache can" \ ++ "greatly improve performance and take up little extra space") \ ++ \ + experimental(bool, UseFastSerializer, false, \ + "Cache-based serialization.It is extremely fast, but it can only" \ + "be effective in certain scenarios.") \ +diff --git a/src/java.base/share/classes/java/lang/StringUTF16.java b/src/java.base/share/classes/java/lang/StringUTF16.java +index 331b51812..c3ede9676 100644 +--- a/src/java.base/share/classes/java/lang/StringUTF16.java ++++ b/src/java.base/share/classes/java/lang/StringUTF16.java +@@ -28,11 +28,13 @@ package java.lang; + import java.util.Arrays; + import java.util.Locale; + import java.util.Spliterator; ++import java.util.concurrent.ConcurrentHashMap; + import java.util.function.Consumer; + import java.util.function.IntConsumer; + import java.util.stream.Stream; + import java.util.stream.StreamSupport; + import jdk.internal.HotSpotIntrinsicCandidate; ++import jdk.internal.misc.Unsafe; + import jdk.internal.vm.annotation.ForceInline; + import jdk.internal.vm.annotation.DontInline; + +@@ -41,6 +43,14 @@ import static java.lang.String.LATIN1; + + final class StringUTF16 { + ++ private static final Unsafe UNSAFE = Unsafe.getUnsafe(); ++ ++ private static boolean enableCharCache = UNSAFE.getUseCharCache(); ++ ++ private static final int MAX_CHAR_CACHE = 1200000; ++ ++ private static transient ConcurrentHashMap charCache = new ConcurrentHashMap<>(); ++ + public static byte[] newBytesFor(int len) { + if (len < 0) { + throw new NegativeArraySizeException(); +@@ -157,8 +167,17 @@ final class StringUTF16 { + } + + public static byte[] compress(char[] val, int off, int len) { ++ boolean flag = (off == 0 && len == val.length); ++ if(enableCharCache && flag) { ++ if(charCache.containsKey(val)) { ++ return charCache.get(val); ++ } ++ } + byte[] ret = new byte[len]; + if (compress(val, off, ret, 0, len) == len) { ++ if(enableCharCache && flag && charCache.size() < MAX_CHAR_CACHE) { ++ charCache.put(val, ret); ++ } + return ret; + } + return null; +diff --git a/src/java.base/share/classes/jdk/internal/misc/Unsafe.java b/src/java.base/share/classes/jdk/internal/misc/Unsafe.java +index 4d71e671e..4fc4b1a43 100644 +--- a/src/java.base/share/classes/jdk/internal/misc/Unsafe.java ++++ b/src/java.base/share/classes/jdk/internal/misc/Unsafe.java +@@ -3702,6 +3702,7 @@ public final class Unsafe { + private static int convEndian(boolean big, int n) { return big == BE ? n : Integer.reverseBytes(n) ; } + private static long convEndian(boolean big, long n) { return big == BE ? n : Long.reverseBytes(n) ; } + ++ public native boolean getUseCharCache(); + public native boolean getUseHashMapIntegerCache(); + public native boolean getUseFastSerializer(); + private native long allocateMemory0(long bytes); +-- +2.19.1 + diff --git a/G1-iterate-region-by-bitmap-rather-than-obj-size-in.patch b/G1-iterate-region-by-bitmap-rather-than-obj-size-in.patch index e395c0b7210708ddc2baa7dbc7fb96600f5e8cf5..8d4548aad36df00f937ee2babb039206bb059a35 100755 --- a/G1-iterate-region-by-bitmap-rather-than-obj-size-in.patch +++ b/G1-iterate-region-by-bitmap-rather-than-obj-size-in.patch @@ -367,4 +367,4 @@ index 000000000..85b49171c --- /dev/null +++ b/version.txt @@ -0,0 +1 @@ -+11.0.22.0.13 ++11.0.24.0.13 diff --git a/LoongArch64-support.patch b/LoongArch64-support.patch index 029b5085ced97aa3f49b7f4c9f71956193358025..bf78938519963d04f67592ed50d962f0cee255e9 100644 --- a/LoongArch64-support.patch +++ b/LoongArch64-support.patch @@ -1,7 +1,36 @@ -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/make/autoconf/hotspot.m4 b/make/autoconf/hotspot.m4 ---- a/make/autoconf/hotspot.m4 2024-01-10 05:19:49.000000000 +0800 -+++ b/make/autoconf/hotspot.m4 2024-01-30 10:00:11.621434355 +0800 -@@ -34,6 +34,12 @@ +diff --git a/make/CompileJavaModules.gmk b/make/CompileJavaModules.gmk +index 46fb9b4219..c6d8b24fc4 100644 +--- a/make/CompileJavaModules.gmk ++++ b/make/CompileJavaModules.gmk +@@ -430,6 +430,7 @@ jdk.internal.vm.ci_ADD_JAVAC_FLAGS += -parameters -Xlint:-exports -XDstringConca + + jdk.internal.vm.compiler_ADD_JAVAC_FLAGS += -parameters -XDstringConcat=inline \ + --add-exports jdk.internal.vm.ci/jdk.vm.ci.aarch64=jdk.internal.vm.compiler \ ++ --add-exports jdk.internal.vm.ci/jdk.vm.ci.loongarch64=jdk.internal.vm.compiler \ + --add-exports jdk.internal.vm.ci/jdk.vm.ci.amd64=jdk.internal.vm.compiler \ + --add-exports jdk.internal.vm.ci/jdk.vm.ci.code=jdk.internal.vm.compiler \ + --add-exports jdk.internal.vm.ci/jdk.vm.ci.code.site=jdk.internal.vm.compiler \ +@@ -437,6 +438,7 @@ jdk.internal.vm.compiler_ADD_JAVAC_FLAGS += -parameters -XDstringConcat=inline \ + --add-exports jdk.internal.vm.ci/jdk.vm.ci.common=jdk.internal.vm.compiler \ + --add-exports jdk.internal.vm.ci/jdk.vm.ci.hotspot=jdk.internal.vm.compiler \ + --add-exports jdk.internal.vm.ci/jdk.vm.ci.hotspot.aarch64=jdk.internal.vm.compiler \ ++ --add-exports jdk.internal.vm.ci/jdk.vm.ci.hotspot.loongarch64=jdk.internal.vm.compiler \ + --add-exports jdk.internal.vm.ci/jdk.vm.ci.hotspot.amd64=jdk.internal.vm.compiler \ + --add-exports jdk.internal.vm.ci/jdk.vm.ci.hotspot.sparc=jdk.internal.vm.compiler \ + --add-exports jdk.internal.vm.ci/jdk.vm.ci.meta=jdk.internal.vm.compiler \ +@@ -456,6 +458,7 @@ jdk.internal.vm.compiler_EXCLUDES += \ + org.graalvm.compiler.api.directives.test \ + org.graalvm.compiler.api.test \ + org.graalvm.compiler.asm.aarch64.test \ ++ org.graalvm.compiler.asm.loongarch64.test \ + org.graalvm.compiler.asm.amd64.test \ + org.graalvm.compiler.asm.sparc.test \ + org.graalvm.compiler.asm.test \ +diff --git a/make/autoconf/hotspot.m4 b/make/autoconf/hotspot.m4 +index 9bb34363e5..c95a2447ef 100644 +--- a/make/autoconf/hotspot.m4 ++++ b/make/autoconf/hotspot.m4 +@@ -34,6 +34,12 @@ DEPRECATED_JVM_FEATURES="trace" # All valid JVM variants VALID_JVM_VARIANTS="server client minimal core zero custom" @@ -14,7 +43,7 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/make/ ############################################################################### # Check if the specified JVM variant should be built. To be used in shell if # constructs, like this: -@@ -340,6 +346,26 @@ +@@ -340,6 +346,26 @@ AC_DEFUN_ONCE([HOTSPOT_SETUP_JVM_FEATURES], HOTSPOT_TARGET_CPU_ARCH=arm fi @@ -41,7 +70,7 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/make/ # Verify that dependencies are met for explicitly set features. if HOTSPOT_CHECK_JVM_FEATURE(jvmti) && ! HOTSPOT_CHECK_JVM_FEATURE(services); then AC_MSG_ERROR([Specified JVM feature 'jvmti' requires feature 'services']) -@@ -424,10 +450,11 @@ +@@ -424,10 +450,11 @@ AC_DEFUN_ONCE([HOTSPOT_SETUP_JVM_FEATURES], JVM_FEATURES_jvmci="" INCLUDE_JVMCI="false" else @@ -55,9 +84,10 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/make/ AC_MSG_RESULT([yes]) JVM_FEATURES_jvmci="jvmci" INCLUDE_JVMCI="true" -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/make/autoconf/platform.m4 b/make/autoconf/platform.m4 ---- a/make/autoconf/platform.m4 2024-01-10 05:19:49.000000000 +0800 -+++ b/make/autoconf/platform.m4 2024-01-30 10:00:11.621434355 +0800 +diff --git a/make/autoconf/platform.m4 b/make/autoconf/platform.m4 +index 5d1d9efa39..815180ea96 100644 +--- a/make/autoconf/platform.m4 ++++ b/make/autoconf/platform.m4 @@ -23,6 +23,12 @@ # questions. # @@ -71,7 +101,7 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/make/ # Support macro for PLATFORM_EXTRACT_TARGET_AND_BUILD. # Converts autoconf style CPU name to OpenJDK style, into # VAR_CPU, VAR_CPU_ARCH, VAR_CPU_BITS and VAR_CPU_ENDIAN. -@@ -554,6 +560,12 @@ +@@ -554,6 +560,12 @@ AC_DEFUN([PLATFORM_SETUP_LEGACY_VARS_HELPER], HOTSPOT_$1_CPU_DEFINE=PPC64 elif test "x$OPENJDK_$1_CPU" = xppc64le; then HOTSPOT_$1_CPU_DEFINE=PPC64 @@ -84,65 +114,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/make/ # The cpu defines below are for zero, we don't support them directly. elif test "x$OPENJDK_$1_CPU" = xsparc; then -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/make/CompileJavaModules.gmk b/make/CompileJavaModules.gmk ---- a/make/CompileJavaModules.gmk 2024-01-10 05:19:49.000000000 +0800 -+++ b/make/CompileJavaModules.gmk 2024-01-30 10:00:11.614767768 +0800 -@@ -430,6 +430,7 @@ - - jdk.internal.vm.compiler_ADD_JAVAC_FLAGS += -parameters -XDstringConcat=inline \ - --add-exports jdk.internal.vm.ci/jdk.vm.ci.aarch64=jdk.internal.vm.compiler \ -+ --add-exports jdk.internal.vm.ci/jdk.vm.ci.loongarch64=jdk.internal.vm.compiler \ - --add-exports jdk.internal.vm.ci/jdk.vm.ci.amd64=jdk.internal.vm.compiler \ - --add-exports jdk.internal.vm.ci/jdk.vm.ci.code=jdk.internal.vm.compiler \ - --add-exports jdk.internal.vm.ci/jdk.vm.ci.code.site=jdk.internal.vm.compiler \ -@@ -437,6 +438,7 @@ - --add-exports jdk.internal.vm.ci/jdk.vm.ci.common=jdk.internal.vm.compiler \ - --add-exports jdk.internal.vm.ci/jdk.vm.ci.hotspot=jdk.internal.vm.compiler \ - --add-exports jdk.internal.vm.ci/jdk.vm.ci.hotspot.aarch64=jdk.internal.vm.compiler \ -+ --add-exports jdk.internal.vm.ci/jdk.vm.ci.hotspot.loongarch64=jdk.internal.vm.compiler \ - --add-exports jdk.internal.vm.ci/jdk.vm.ci.hotspot.amd64=jdk.internal.vm.compiler \ - --add-exports jdk.internal.vm.ci/jdk.vm.ci.hotspot.sparc=jdk.internal.vm.compiler \ - --add-exports jdk.internal.vm.ci/jdk.vm.ci.meta=jdk.internal.vm.compiler \ -@@ -456,6 +458,7 @@ - org.graalvm.compiler.api.directives.test \ - org.graalvm.compiler.api.test \ - org.graalvm.compiler.asm.aarch64.test \ -+ org.graalvm.compiler.asm.loongarch64.test \ - org.graalvm.compiler.asm.amd64.test \ - org.graalvm.compiler.asm.sparc.test \ - org.graalvm.compiler.asm.test \ -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/aarch64/c1_LIR_aarch64.cpp b/src/hotspot/cpu/aarch64/c1_LIR_aarch64.cpp ---- a/src/hotspot/cpu/aarch64/c1_LIR_aarch64.cpp 2024-01-10 05:19:49.000000000 +0800 -+++ b/src/hotspot/cpu/aarch64/c1_LIR_aarch64.cpp 2024-01-30 10:00:11.801432207 +0800 -@@ -52,3 +52,24 @@ - "wrong type for addresses"); - } - #endif // PRODUCT -+ -+template -+void LIR_List::cmp_branch(LIR_Condition condition, LIR_Opr left, LIR_Opr right, BasicType type, T tgt, CodeEmitInfo* info) { -+ cmp(condition, left, right, info); -+ branch(condition, type, tgt); -+} -+ -+// Explicit instantiation for all supported types. -+template void LIR_List::cmp_branch(LIR_Condition, LIR_Opr, LIR_Opr, BasicType type, Label*, CodeEmitInfo*); -+template void LIR_List::cmp_branch(LIR_Condition, LIR_Opr, LIR_Opr, BasicType type, BlockBegin*, CodeEmitInfo*); -+template void LIR_List::cmp_branch(LIR_Condition, LIR_Opr, LIR_Opr, BasicType type, CodeStub*, CodeEmitInfo*); -+ -+void LIR_List::cmp_branch(LIR_Condition condition, LIR_Opr left, LIR_Opr right, BasicType type, BlockBegin* block, BlockBegin* unordered) { -+ cmp(condition, left, right); -+ branch(condition, type, block, unordered); -+} -+ -+void LIR_List::cmp_cmove(LIR_Condition condition, LIR_Opr left, LIR_Opr right, LIR_Opr src1, LIR_Opr src2, LIR_Opr dst, BasicType type) { -+ cmp(condition, left, right); -+ cmove(condition, src1, src2, dst, type); -+} -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/aarch64/c1_LIRAssembler_aarch64.cpp b/src/hotspot/cpu/aarch64/c1_LIRAssembler_aarch64.cpp ---- a/src/hotspot/cpu/aarch64/c1_LIRAssembler_aarch64.cpp 2024-01-10 05:19:49.000000000 +0800 -+++ b/src/hotspot/cpu/aarch64/c1_LIRAssembler_aarch64.cpp 2024-01-30 10:00:11.801432207 +0800 -@@ -1123,7 +1123,9 @@ +diff --git a/src/hotspot/cpu/aarch64/c1_LIRAssembler_aarch64.cpp b/src/hotspot/cpu/aarch64/c1_LIRAssembler_aarch64.cpp +index fdd2c0ca3d..318191233a 100644 +--- a/src/hotspot/cpu/aarch64/c1_LIRAssembler_aarch64.cpp ++++ b/src/hotspot/cpu/aarch64/c1_LIRAssembler_aarch64.cpp +@@ -1123,7 +1123,9 @@ void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) { } } @@ -153,7 +129,7 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) { LIR_Opr src = op->in_opr(); -@@ -1663,6 +1665,10 @@ +@@ -1663,6 +1665,10 @@ void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, L __ csel(result->as_register(), opr1->as_register(), opr2->as_register(), acond); } @@ -164,10 +140,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack) { assert(info == NULL, "should never be used, idiv/irem and ldiv/lrem not handled by this method"); -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/aarch64/c1_LIRGenerator_aarch64.cpp b/src/hotspot/cpu/aarch64/c1_LIRGenerator_aarch64.cpp ---- a/src/hotspot/cpu/aarch64/c1_LIRGenerator_aarch64.cpp 2024-01-10 05:19:49.000000000 +0800 -+++ b/src/hotspot/cpu/aarch64/c1_LIRGenerator_aarch64.cpp 2024-01-30 10:00:11.801432207 +0800 -@@ -260,18 +260,29 @@ +diff --git a/src/hotspot/cpu/aarch64/c1_LIRGenerator_aarch64.cpp b/src/hotspot/cpu/aarch64/c1_LIRGenerator_aarch64.cpp +index 18b3ea147d..f3398e191c 100644 +--- a/src/hotspot/cpu/aarch64/c1_LIRGenerator_aarch64.cpp ++++ b/src/hotspot/cpu/aarch64/c1_LIRGenerator_aarch64.cpp +@@ -262,18 +262,29 @@ void LIRGenerator::increment_counter(LIR_Address* addr, int step) { __ store(reg, addr); } @@ -201,11 +178,12 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h bool LIRGenerator::strength_reduce_multiply(LIR_Opr left, jint c, LIR_Opr result, LIR_Opr tmp) { -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/arm/c1_LIR_arm.cpp b/src/hotspot/cpu/arm/c1_LIR_arm.cpp ---- a/src/hotspot/cpu/arm/c1_LIR_arm.cpp 2024-01-10 05:19:49.000000000 +0800 -+++ b/src/hotspot/cpu/arm/c1_LIR_arm.cpp 2024-01-30 10:00:11.821431969 +0800 -@@ -84,3 +84,24 @@ - #endif // AARCH64 +diff --git a/src/hotspot/cpu/aarch64/c1_LIR_aarch64.cpp b/src/hotspot/cpu/aarch64/c1_LIR_aarch64.cpp +index ce75dc552a..74c4b7e556 100644 +--- a/src/hotspot/cpu/aarch64/c1_LIR_aarch64.cpp ++++ b/src/hotspot/cpu/aarch64/c1_LIR_aarch64.cpp +@@ -52,3 +52,24 @@ void LIR_Address::verify() const { + "wrong type for addresses"); } #endif // PRODUCT + @@ -229,10 +207,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h + cmp(condition, left, right); + cmove(condition, src1, src2, dst, type); +} -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/arm/c1_LIRAssembler_arm.cpp b/src/hotspot/cpu/arm/c1_LIRAssembler_arm.cpp ---- a/src/hotspot/cpu/arm/c1_LIRAssembler_arm.cpp 2024-01-10 05:19:49.000000000 +0800 -+++ b/src/hotspot/cpu/arm/c1_LIRAssembler_arm.cpp 2024-01-30 10:00:11.818098676 +0800 -@@ -1150,6 +1150,9 @@ +diff --git a/src/hotspot/cpu/arm/c1_LIRAssembler_arm.cpp b/src/hotspot/cpu/arm/c1_LIRAssembler_arm.cpp +index f0a7229aa1..29db21f975 100644 +--- a/src/hotspot/cpu/arm/c1_LIRAssembler_arm.cpp ++++ b/src/hotspot/cpu/arm/c1_LIRAssembler_arm.cpp +@@ -1150,6 +1150,9 @@ void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) { __ b(*(op->label()), acond); } @@ -242,7 +221,7 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) { LIR_Opr src = op->in_opr(); -@@ -3082,6 +3085,10 @@ +@@ -3082,6 +3085,10 @@ void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) { __ bind(*stub->continuation()); } @@ -253,10 +232,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h #ifdef ASSERT // emit run-time assertion void LIR_Assembler::emit_assert(LIR_OpAssert* op) { -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/arm/c1_LIRGenerator_arm.cpp b/src/hotspot/cpu/arm/c1_LIRGenerator_arm.cpp ---- a/src/hotspot/cpu/arm/c1_LIRGenerator_arm.cpp 2024-01-10 05:19:49.000000000 +0800 -+++ b/src/hotspot/cpu/arm/c1_LIRGenerator_arm.cpp 2024-01-30 10:00:11.818098676 +0800 -@@ -423,18 +423,27 @@ +diff --git a/src/hotspot/cpu/arm/c1_LIRGenerator_arm.cpp b/src/hotspot/cpu/arm/c1_LIRGenerator_arm.cpp +index b05fc876f2..b3c1afe69a 100644 +--- a/src/hotspot/cpu/arm/c1_LIRGenerator_arm.cpp ++++ b/src/hotspot/cpu/arm/c1_LIRGenerator_arm.cpp +@@ -423,18 +423,27 @@ void LIRGenerator::increment_counter(LIR_Address* addr, int step) { __ move(temp, addr); } @@ -289,9 +269,40 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h bool LIRGenerator::strength_reduce_multiply(LIR_Opr left, jint c, LIR_Opr result, LIR_Opr tmp) { assert(left != result, "should be different registers"); -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/abstractInterpreter_loongarch.cpp b/src/hotspot/cpu/loongarch/abstractInterpreter_loongarch.cpp ---- a/src/hotspot/cpu/loongarch/abstractInterpreter_loongarch.cpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/cpu/loongarch/abstractInterpreter_loongarch.cpp 2024-01-30 10:00:11.834765144 +0800 +diff --git a/src/hotspot/cpu/arm/c1_LIR_arm.cpp b/src/hotspot/cpu/arm/c1_LIR_arm.cpp +index 806da32020..5305fe371e 100644 +--- a/src/hotspot/cpu/arm/c1_LIR_arm.cpp ++++ b/src/hotspot/cpu/arm/c1_LIR_arm.cpp +@@ -84,3 +84,24 @@ void LIR_Address::verify() const { + #endif // AARCH64 + } + #endif // PRODUCT ++ ++template ++void LIR_List::cmp_branch(LIR_Condition condition, LIR_Opr left, LIR_Opr right, BasicType type, T tgt, CodeEmitInfo* info) { ++ cmp(condition, left, right, info); ++ branch(condition, type, tgt); ++} ++ ++// Explicit instantiation for all supported types. ++template void LIR_List::cmp_branch(LIR_Condition, LIR_Opr, LIR_Opr, BasicType type, Label*, CodeEmitInfo*); ++template void LIR_List::cmp_branch(LIR_Condition, LIR_Opr, LIR_Opr, BasicType type, BlockBegin*, CodeEmitInfo*); ++template void LIR_List::cmp_branch(LIR_Condition, LIR_Opr, LIR_Opr, BasicType type, CodeStub*, CodeEmitInfo*); ++ ++void LIR_List::cmp_branch(LIR_Condition condition, LIR_Opr left, LIR_Opr right, BasicType type, BlockBegin* block, BlockBegin* unordered) { ++ cmp(condition, left, right); ++ branch(condition, type, block, unordered); ++} ++ ++void LIR_List::cmp_cmove(LIR_Condition condition, LIR_Opr left, LIR_Opr right, LIR_Opr src1, LIR_Opr src2, LIR_Opr dst, BasicType type) { ++ cmp(condition, left, right); ++ cmove(condition, src1, src2, dst, type); ++} +diff --git a/src/hotspot/cpu/loongarch/abstractInterpreter_loongarch.cpp b/src/hotspot/cpu/loongarch/abstractInterpreter_loongarch.cpp +new file mode 100644 +index 0000000000..0412b99537 +--- /dev/null ++++ b/src/hotspot/cpu/loongarch/abstractInterpreter_loongarch.cpp @@ -0,0 +1,132 @@ +/* + * Copyright (c) 2003, 2013, Oracle and/or its affiliates. All rights reserved. @@ -425,9 +436,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h + *interpreter_frame->interpreter_frame_mirror_addr() = method->method_holder()->java_mirror(); +} + -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/assembler_loongarch.cpp b/src/hotspot/cpu/loongarch/assembler_loongarch.cpp ---- a/src/hotspot/cpu/loongarch/assembler_loongarch.cpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/cpu/loongarch/assembler_loongarch.cpp 2024-01-30 10:00:11.834765144 +0800 +diff --git a/src/hotspot/cpu/loongarch/assembler_loongarch.cpp b/src/hotspot/cpu/loongarch/assembler_loongarch.cpp +new file mode 100644 +index 0000000000..e6e62cccad +--- /dev/null ++++ b/src/hotspot/cpu/loongarch/assembler_loongarch.cpp @@ -0,0 +1,849 @@ +/* + * Copyright (c) 1997, 2014, Oracle and/or its affiliates. All rights reserved. @@ -1278,9 +1291,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h + } + } +} -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/assembler_loongarch.hpp b/src/hotspot/cpu/loongarch/assembler_loongarch.hpp ---- a/src/hotspot/cpu/loongarch/assembler_loongarch.hpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/cpu/loongarch/assembler_loongarch.hpp 2024-01-30 10:00:11.834765144 +0800 +diff --git a/src/hotspot/cpu/loongarch/assembler_loongarch.hpp b/src/hotspot/cpu/loongarch/assembler_loongarch.hpp +new file mode 100644 +index 0000000000..179da7bd0e +--- /dev/null ++++ b/src/hotspot/cpu/loongarch/assembler_loongarch.hpp @@ -0,0 +1,2827 @@ +/* + * Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved. @@ -4109,9 +4124,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h +}; + +#endif // CPU_LOONGARCH_ASSEMBLER_LOONGARCH_HPP -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/assembler_loongarch.inline.hpp b/src/hotspot/cpu/loongarch/assembler_loongarch.inline.hpp ---- a/src/hotspot/cpu/loongarch/assembler_loongarch.inline.hpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/cpu/loongarch/assembler_loongarch.inline.hpp 2024-01-30 10:00:11.834765144 +0800 +diff --git a/src/hotspot/cpu/loongarch/assembler_loongarch.inline.hpp b/src/hotspot/cpu/loongarch/assembler_loongarch.inline.hpp +new file mode 100644 +index 0000000000..9ca0cd4504 +--- /dev/null ++++ b/src/hotspot/cpu/loongarch/assembler_loongarch.inline.hpp @@ -0,0 +1,33 @@ +/* + * Copyright (c) 1997, 2010, Oracle and/or its affiliates. All rights reserved. @@ -4146,9 +4163,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h +#include "code/codeCache.hpp" + +#endif // CPU_LOONGARCH_ASSEMBLER_LOONGARCH_INLINE_HPP -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/bytes_loongarch.hpp b/src/hotspot/cpu/loongarch/bytes_loongarch.hpp ---- a/src/hotspot/cpu/loongarch/bytes_loongarch.hpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/cpu/loongarch/bytes_loongarch.hpp 2024-01-30 10:00:11.834765144 +0800 +diff --git a/src/hotspot/cpu/loongarch/bytes_loongarch.hpp b/src/hotspot/cpu/loongarch/bytes_loongarch.hpp +new file mode 100644 +index 0000000000..c15344eb39 +--- /dev/null ++++ b/src/hotspot/cpu/loongarch/bytes_loongarch.hpp @@ -0,0 +1,73 @@ +/* + * Copyright (c) 1997, 2010, Oracle and/or its affiliates. All rights reserved. @@ -4223,9 +4242,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h +#include OS_CPU_HEADER_INLINE(bytes) + +#endif // CPU_LOONGARCH_BYTES_LOONGARCH_HPP -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/c1_CodeStubs_loongarch_64.cpp b/src/hotspot/cpu/loongarch/c1_CodeStubs_loongarch_64.cpp ---- a/src/hotspot/cpu/loongarch/c1_CodeStubs_loongarch_64.cpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/cpu/loongarch/c1_CodeStubs_loongarch_64.cpp 2024-01-30 10:00:11.834765144 +0800 +diff --git a/src/hotspot/cpu/loongarch/c1_CodeStubs_loongarch_64.cpp b/src/hotspot/cpu/loongarch/c1_CodeStubs_loongarch_64.cpp +new file mode 100644 +index 0000000000..c0eeb63962 +--- /dev/null ++++ b/src/hotspot/cpu/loongarch/c1_CodeStubs_loongarch_64.cpp @@ -0,0 +1,344 @@ +/* + * Copyright (c) 1999, 2021, Oracle and/or its affiliates. All rights reserved. @@ -4571,9 +4592,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h +} + +#undef __ -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/c1_Defs_loongarch.hpp b/src/hotspot/cpu/loongarch/c1_Defs_loongarch.hpp ---- a/src/hotspot/cpu/loongarch/c1_Defs_loongarch.hpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/cpu/loongarch/c1_Defs_loongarch.hpp 2024-01-30 10:00:11.834765144 +0800 +diff --git a/src/hotspot/cpu/loongarch/c1_Defs_loongarch.hpp b/src/hotspot/cpu/loongarch/c1_Defs_loongarch.hpp +new file mode 100644 +index 0000000000..1140e44431 +--- /dev/null ++++ b/src/hotspot/cpu/loongarch/c1_Defs_loongarch.hpp @@ -0,0 +1,79 @@ +/* + * Copyright (c) 2000, 2021, Oracle and/or its affiliates. All rights reserved. @@ -4654,9 +4677,49 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h +}; + +#endif // CPU_LOONGARCH_C1_DEFS_LOONGARCH_HPP -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/c1_FpuStackSim_loongarch_64.cpp b/src/hotspot/cpu/loongarch/c1_FpuStackSim_loongarch_64.cpp ---- a/src/hotspot/cpu/loongarch/c1_FpuStackSim_loongarch_64.cpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/cpu/loongarch/c1_FpuStackSim_loongarch_64.cpp 2024-01-30 10:00:11.834765144 +0800 +diff --git a/src/hotspot/cpu/loongarch/c1_FpuStackSim_loongarch.hpp b/src/hotspot/cpu/loongarch/c1_FpuStackSim_loongarch.hpp +new file mode 100644 +index 0000000000..bd8578c72a +--- /dev/null ++++ b/src/hotspot/cpu/loongarch/c1_FpuStackSim_loongarch.hpp +@@ -0,0 +1,32 @@ ++/* ++ * Copyright (c) 2005, 2019, Oracle and/or its affiliates. All rights reserved. ++ * Copyright (c) 2021, 2022, Loongson Technology. All rights reserved. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ * ++ */ ++ ++#ifndef CPU_LOONGARCH_C1_FPUSTACKSIM_LOONGARCH_HPP ++#define CPU_LOONGARCH_C1_FPUSTACKSIM_LOONGARCH_HPP ++ ++// No FPU stack on LoongArch ++class FpuStackSim; ++ ++#endif // CPU_LOONGARCH_C1_FPUSTACKSIM_LOONGARCH_HPP +diff --git a/src/hotspot/cpu/loongarch/c1_FpuStackSim_loongarch_64.cpp b/src/hotspot/cpu/loongarch/c1_FpuStackSim_loongarch_64.cpp +new file mode 100644 +index 0000000000..1a89c437a8 +--- /dev/null ++++ b/src/hotspot/cpu/loongarch/c1_FpuStackSim_loongarch_64.cpp @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2005, 2017, Oracle and/or its affiliates. All rights reserved. @@ -4689,13 +4752,15 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h + +// No FPU stack on LoongArch64 +#include "precompiled.hpp" -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/c1_FpuStackSim_loongarch.hpp b/src/hotspot/cpu/loongarch/c1_FpuStackSim_loongarch.hpp ---- a/src/hotspot/cpu/loongarch/c1_FpuStackSim_loongarch.hpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/cpu/loongarch/c1_FpuStackSim_loongarch.hpp 2024-01-30 10:00:11.834765144 +0800 -@@ -0,0 +1,32 @@ +diff --git a/src/hotspot/cpu/loongarch/c1_FrameMap_loongarch.hpp b/src/hotspot/cpu/loongarch/c1_FrameMap_loongarch.hpp +new file mode 100644 +index 0000000000..4f0cf05361 +--- /dev/null ++++ b/src/hotspot/cpu/loongarch/c1_FrameMap_loongarch.hpp +@@ -0,0 +1,143 @@ +/* -+ * Copyright (c) 2005, 2019, Oracle and/or its affiliates. All rights reserved. -+ * Copyright (c) 2021, 2022, Loongson Technology. All rights reserved. ++ * Copyright (c) 1999, 2019, Oracle and/or its affiliates. All rights reserved. ++ * Copyright (c) 2021, Loongson Technology. All rights reserved. + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. + * + * This code is free software; you can redistribute it and/or modify it @@ -4718,16 +4783,129 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h + * + */ + -+#ifndef CPU_LOONGARCH_C1_FPUSTACKSIM_LOONGARCH_HPP -+#define CPU_LOONGARCH_C1_FPUSTACKSIM_LOONGARCH_HPP ++#ifndef CPU_LOONGARCH_C1_FRAMEMAP_LOONGARCH_HPP ++#define CPU_LOONGARCH_C1_FRAMEMAP_LOONGARCH_HPP + -+// No FPU stack on LoongArch -+class FpuStackSim; ++// On LoongArch64 the frame looks as follows: ++// ++// +-----------------------------+---------+----------------------------------------+----------------+----------- ++// | size_arguments-nof_reg_args | 2 words | size_locals-size_arguments+numreg_args | _size_monitors | spilling . ++// +-----------------------------+---------+----------------------------------------+----------------+----------- + -+#endif // CPU_LOONGARCH_C1_FPUSTACKSIM_LOONGARCH_HPP -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/c1_FrameMap_loongarch_64.cpp b/src/hotspot/cpu/loongarch/c1_FrameMap_loongarch_64.cpp ---- a/src/hotspot/cpu/loongarch/c1_FrameMap_loongarch_64.cpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/cpu/loongarch/c1_FrameMap_loongarch_64.cpp 2024-01-30 10:00:11.834765144 +0800 ++ public: ++ static const int pd_c_runtime_reserved_arg_size; ++ ++ enum { ++ first_available_sp_in_frame = 0, ++ frame_pad_in_bytes = 16, ++ nof_reg_args = 8 ++ }; ++ ++ public: ++ static LIR_Opr receiver_opr; ++ ++ static LIR_Opr r0_opr; ++ static LIR_Opr ra_opr; ++ static LIR_Opr tp_opr; ++ static LIR_Opr sp_opr; ++ static LIR_Opr a0_opr; ++ static LIR_Opr a1_opr; ++ static LIR_Opr a2_opr; ++ static LIR_Opr a3_opr; ++ static LIR_Opr a4_opr; ++ static LIR_Opr a5_opr; ++ static LIR_Opr a6_opr; ++ static LIR_Opr a7_opr; ++ static LIR_Opr t0_opr; ++ static LIR_Opr t1_opr; ++ static LIR_Opr t2_opr; ++ static LIR_Opr t3_opr; ++ static LIR_Opr t4_opr; ++ static LIR_Opr t5_opr; ++ static LIR_Opr t6_opr; ++ static LIR_Opr t7_opr; ++ static LIR_Opr t8_opr; ++ static LIR_Opr rx_opr; ++ static LIR_Opr fp_opr; ++ static LIR_Opr s0_opr; ++ static LIR_Opr s1_opr; ++ static LIR_Opr s2_opr; ++ static LIR_Opr s3_opr; ++ static LIR_Opr s4_opr; ++ static LIR_Opr s5_opr; ++ static LIR_Opr s6_opr; ++ static LIR_Opr s7_opr; ++ static LIR_Opr s8_opr; ++ ++ static LIR_Opr ra_oop_opr; ++ static LIR_Opr a0_oop_opr; ++ static LIR_Opr a1_oop_opr; ++ static LIR_Opr a2_oop_opr; ++ static LIR_Opr a3_oop_opr; ++ static LIR_Opr a4_oop_opr; ++ static LIR_Opr a5_oop_opr; ++ static LIR_Opr a6_oop_opr; ++ static LIR_Opr a7_oop_opr; ++ static LIR_Opr t0_oop_opr; ++ static LIR_Opr t1_oop_opr; ++ static LIR_Opr t2_oop_opr; ++ static LIR_Opr t3_oop_opr; ++ static LIR_Opr t4_oop_opr; ++ static LIR_Opr t5_oop_opr; ++ static LIR_Opr t6_oop_opr; ++ static LIR_Opr t7_oop_opr; ++ static LIR_Opr t8_oop_opr; ++ static LIR_Opr fp_oop_opr; ++ static LIR_Opr s0_oop_opr; ++ static LIR_Opr s1_oop_opr; ++ static LIR_Opr s2_oop_opr; ++ static LIR_Opr s3_oop_opr; ++ static LIR_Opr s4_oop_opr; ++ static LIR_Opr s5_oop_opr; ++ static LIR_Opr s6_oop_opr; ++ static LIR_Opr s7_oop_opr; ++ static LIR_Opr s8_oop_opr; ++ ++ static LIR_Opr scr1_opr; ++ static LIR_Opr scr2_opr; ++ static LIR_Opr scr1_long_opr; ++ static LIR_Opr scr2_long_opr; ++ ++ static LIR_Opr a0_metadata_opr; ++ static LIR_Opr a1_metadata_opr; ++ static LIR_Opr a2_metadata_opr; ++ static LIR_Opr a3_metadata_opr; ++ static LIR_Opr a4_metadata_opr; ++ static LIR_Opr a5_metadata_opr; ++ ++ static LIR_Opr long0_opr; ++ static LIR_Opr long1_opr; ++ static LIR_Opr fpu0_float_opr; ++ static LIR_Opr fpu0_double_opr; ++ ++ static LIR_Opr as_long_opr(Register r) { ++ return LIR_OprFact::double_cpu(cpu_reg2rnr(r), cpu_reg2rnr(r)); ++ } ++ static LIR_Opr as_pointer_opr(Register r) { ++ return LIR_OprFact::double_cpu(cpu_reg2rnr(r), cpu_reg2rnr(r)); ++ } ++ ++ // VMReg name for spilled physical FPU stack slot n ++ static VMReg fpu_regname (int n); ++ ++ static bool is_caller_save_register(LIR_Opr opr) { return true; } ++ static bool is_caller_save_register(Register r) { return true; } ++ ++ static int nof_caller_save_cpu_regs() { return pd_nof_caller_save_cpu_regs_frame_map; } ++ static int last_cpu_reg() { return pd_last_cpu_reg; } ++ static int last_byte_reg() { return pd_last_byte_reg; } ++ ++#endif // CPU_LOONGARCH_C1_FRAMEMAP_LOONGARCH_HPP +diff --git a/src/hotspot/cpu/loongarch/c1_FrameMap_loongarch_64.cpp b/src/hotspot/cpu/loongarch/c1_FrameMap_loongarch_64.cpp +new file mode 100644 +index 0000000000..3b60899071 +--- /dev/null ++++ b/src/hotspot/cpu/loongarch/c1_FrameMap_loongarch_64.cpp @@ -0,0 +1,354 @@ +/* + * Copyright (c) 1999, 2019, Oracle and/or its affiliates. All rights reserved. @@ -5083,12 +5261,14 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h +bool FrameMap::validate_frame() { + return true; +} -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/c1_FrameMap_loongarch.hpp b/src/hotspot/cpu/loongarch/c1_FrameMap_loongarch.hpp ---- a/src/hotspot/cpu/loongarch/c1_FrameMap_loongarch.hpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/cpu/loongarch/c1_FrameMap_loongarch.hpp 2024-01-30 10:00:11.834765144 +0800 -@@ -0,0 +1,143 @@ +diff --git a/src/hotspot/cpu/loongarch/c1_LIRAssembler_loongarch.hpp b/src/hotspot/cpu/loongarch/c1_LIRAssembler_loongarch.hpp +new file mode 100644 +index 0000000000..40d9408f1f +--- /dev/null ++++ b/src/hotspot/cpu/loongarch/c1_LIRAssembler_loongarch.hpp +@@ -0,0 +1,83 @@ +/* -+ * Copyright (c) 1999, 2019, Oracle and/or its affiliates. All rights reserved. ++ * Copyright (c) 2000, 2021, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 2021, Loongson Technology. All rights reserved. + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. + * @@ -5112,317 +5292,73 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h + * + */ + -+#ifndef CPU_LOONGARCH_C1_FRAMEMAP_LOONGARCH_HPP -+#define CPU_LOONGARCH_C1_FRAMEMAP_LOONGARCH_HPP ++#ifndef CPU_LOONGARCH_C1_LIRASSEMBLER_LOONGARCH_HPP ++#define CPU_LOONGARCH_C1_LIRASSEMBLER_LOONGARCH_HPP + -+// On LoongArch64 the frame looks as follows: -+// -+// +-----------------------------+---------+----------------------------------------+----------------+----------- -+// | size_arguments-nof_reg_args | 2 words | size_locals-size_arguments+numreg_args | _size_monitors | spilling . -+// +-----------------------------+---------+----------------------------------------+----------------+----------- ++// ArrayCopyStub needs access to bailout ++friend class ArrayCopyStub; + -+ public: -+ static const int pd_c_runtime_reserved_arg_size; ++ private: ++ int array_element_size(BasicType type) const; + -+ enum { -+ first_available_sp_in_frame = 0, -+ frame_pad_in_bytes = 16, -+ nof_reg_args = 8 -+ }; ++ void arith_fpu_implementation(LIR_Code code, int left_index, int right_index, ++ int dest_index, bool pop_fpu_stack); + -+ public: -+ static LIR_Opr receiver_opr; ++ // helper functions which checks for overflow and sets bailout if it ++ // occurs. Always returns a valid embeddable pointer but in the ++ // bailout case the pointer won't be to unique storage. ++ address float_constant(float f); ++ address double_constant(double d); + -+ static LIR_Opr r0_opr; -+ static LIR_Opr ra_opr; -+ static LIR_Opr tp_opr; -+ static LIR_Opr sp_opr; -+ static LIR_Opr a0_opr; -+ static LIR_Opr a1_opr; -+ static LIR_Opr a2_opr; -+ static LIR_Opr a3_opr; -+ static LIR_Opr a4_opr; -+ static LIR_Opr a5_opr; -+ static LIR_Opr a6_opr; -+ static LIR_Opr a7_opr; -+ static LIR_Opr t0_opr; -+ static LIR_Opr t1_opr; -+ static LIR_Opr t2_opr; -+ static LIR_Opr t3_opr; -+ static LIR_Opr t4_opr; -+ static LIR_Opr t5_opr; -+ static LIR_Opr t6_opr; -+ static LIR_Opr t7_opr; -+ static LIR_Opr t8_opr; -+ static LIR_Opr rx_opr; -+ static LIR_Opr fp_opr; -+ static LIR_Opr s0_opr; -+ static LIR_Opr s1_opr; -+ static LIR_Opr s2_opr; -+ static LIR_Opr s3_opr; -+ static LIR_Opr s4_opr; -+ static LIR_Opr s5_opr; -+ static LIR_Opr s6_opr; -+ static LIR_Opr s7_opr; -+ static LIR_Opr s8_opr; ++ address int_constant(jlong n); + -+ static LIR_Opr ra_oop_opr; -+ static LIR_Opr a0_oop_opr; -+ static LIR_Opr a1_oop_opr; -+ static LIR_Opr a2_oop_opr; -+ static LIR_Opr a3_oop_opr; -+ static LIR_Opr a4_oop_opr; -+ static LIR_Opr a5_oop_opr; -+ static LIR_Opr a6_oop_opr; -+ static LIR_Opr a7_oop_opr; -+ static LIR_Opr t0_oop_opr; -+ static LIR_Opr t1_oop_opr; -+ static LIR_Opr t2_oop_opr; -+ static LIR_Opr t3_oop_opr; -+ static LIR_Opr t4_oop_opr; -+ static LIR_Opr t5_oop_opr; -+ static LIR_Opr t6_oop_opr; -+ static LIR_Opr t7_oop_opr; -+ static LIR_Opr t8_oop_opr; -+ static LIR_Opr fp_oop_opr; -+ static LIR_Opr s0_oop_opr; -+ static LIR_Opr s1_oop_opr; -+ static LIR_Opr s2_oop_opr; -+ static LIR_Opr s3_oop_opr; -+ static LIR_Opr s4_oop_opr; -+ static LIR_Opr s5_oop_opr; -+ static LIR_Opr s6_oop_opr; -+ static LIR_Opr s7_oop_opr; -+ static LIR_Opr s8_oop_opr; ++ bool is_literal_address(LIR_Address* addr); + -+ static LIR_Opr scr1_opr; -+ static LIR_Opr scr2_opr; -+ static LIR_Opr scr1_long_opr; -+ static LIR_Opr scr2_long_opr; ++ // Ensure we have a valid Address (base+offset) to a stack-slot. ++ Address stack_slot_address(int index, uint shift, int adjust = 0); + -+ static LIR_Opr a0_metadata_opr; -+ static LIR_Opr a1_metadata_opr; -+ static LIR_Opr a2_metadata_opr; -+ static LIR_Opr a3_metadata_opr; -+ static LIR_Opr a4_metadata_opr; -+ static LIR_Opr a5_metadata_opr; ++ // Record the type of the receiver in ReceiverTypeData ++ void type_profile_helper(Register mdo, ciMethodData *md, ciProfileData *data, ++ Register recv, Label* update_done); ++ void add_debug_info_for_branch(address adr, CodeEmitInfo* info); + -+ static LIR_Opr long0_opr; -+ static LIR_Opr long1_opr; -+ static LIR_Opr fpu0_float_opr; -+ static LIR_Opr fpu0_double_opr; ++ void casw(Register addr, Register newval, Register cmpval, bool sign); ++ void casl(Register addr, Register newval, Register cmpval); + -+ static LIR_Opr as_long_opr(Register r) { -+ return LIR_OprFact::double_cpu(cpu_reg2rnr(r), cpu_reg2rnr(r)); -+ } -+ static LIR_Opr as_pointer_opr(Register r) { -+ return LIR_OprFact::double_cpu(cpu_reg2rnr(r), cpu_reg2rnr(r)); -+ } ++ void poll_for_safepoint(relocInfo::relocType rtype, CodeEmitInfo* info = NULL); + -+ // VMReg name for spilled physical FPU stack slot n -+ static VMReg fpu_regname (int n); ++ static const int max_tableswitches = 20; ++ struct tableswitch switches[max_tableswitches]; ++ int tableswitch_count; + -+ static bool is_caller_save_register(LIR_Opr opr) { return true; } -+ static bool is_caller_save_register(Register r) { return true; } ++ void init() { tableswitch_count = 0; } + -+ static int nof_caller_save_cpu_regs() { return pd_nof_caller_save_cpu_regs_frame_map; } -+ static int last_cpu_reg() { return pd_last_cpu_reg; } -+ static int last_byte_reg() { return pd_last_byte_reg; } ++ void deoptimize_trap(CodeEmitInfo *info); + -+#endif // CPU_LOONGARCH_C1_FRAMEMAP_LOONGARCH_HPP -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/c1_globals_loongarch.hpp b/src/hotspot/cpu/loongarch/c1_globals_loongarch.hpp ---- a/src/hotspot/cpu/loongarch/c1_globals_loongarch.hpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/cpu/loongarch/c1_globals_loongarch.hpp 2024-01-30 10:00:11.838098438 +0800 -@@ -0,0 +1,71 @@ ++ enum { ++ // call stub: CompiledStaticCall::to_interp_stub_size() + ++ // CompiledStaticCall::to_trampoline_stub_size() ++ _call_stub_size = 13 * NativeInstruction::nop_instruction_size, ++ _call_aot_stub_size = 0, ++ _exception_handler_size = DEBUG_ONLY(1*K) NOT_DEBUG(175), ++ _deopt_handler_size = 7 * NativeInstruction::nop_instruction_size ++ }; ++ ++public: ++ void store_parameter(Register r, int offset_from_sp_in_words); ++ void store_parameter(jint c, int offset_from_sp_in_words); ++ void store_parameter(jobject c, int offset_from_sp_in_words); ++ ++#endif // CPU_LOONGARCH_C1_LIRASSEMBLER_LOONGARCH_HPP +diff --git a/src/hotspot/cpu/loongarch/c1_LIRAssembler_loongarch_64.cpp b/src/hotspot/cpu/loongarch/c1_LIRAssembler_loongarch_64.cpp +new file mode 100644 +index 0000000000..c989e25c3a +--- /dev/null ++++ b/src/hotspot/cpu/loongarch/c1_LIRAssembler_loongarch_64.cpp +@@ -0,0 +1,3387 @@ +/* + * Copyright (c) 2000, 2021, Oracle and/or its affiliates. All rights reserved. -+ * Copyright (c) 2021, 2022, Loongson Technology. All rights reserved. -+ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. -+ * -+ * This code is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 only, as -+ * published by the Free Software Foundation. -+ * -+ * This code is distributed in the hope that it will be useful, but WITHOUT -+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -+ * version 2 for more details (a copy is included in the LICENSE file that -+ * accompanied this code). -+ * -+ * You should have received a copy of the GNU General Public License version -+ * 2 along with this work; if not, write to the Free Software Foundation, -+ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. -+ * -+ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA -+ * or visit www.oracle.com if you need additional information or have any -+ * questions. -+ * -+ */ -+ -+#ifndef CPU_LOONGARCH_C1_GLOBALS_LOONGARCH_HPP -+#define CPU_LOONGARCH_C1_GLOBALS_LOONGARCH_HPP -+ -+#include "utilities/globalDefinitions.hpp" -+#include "utilities/macros.hpp" -+ -+// Sets the default values for platform dependent flags used by the client compiler. -+// (see c1_globals.hpp) -+ -+#ifndef COMPILER2 -+define_pd_global(bool, BackgroundCompilation, true ); -+define_pd_global(bool, UseTLAB, true ); -+define_pd_global(bool, ResizeTLAB, true ); -+define_pd_global(bool, InlineIntrinsics, true ); -+define_pd_global(bool, PreferInterpreterNativeStubs, false); -+define_pd_global(bool, ProfileTraps, false); -+define_pd_global(bool, UseOnStackReplacement, true ); -+define_pd_global(bool, TieredCompilation, false); -+define_pd_global(intx, CompileThreshold, 1500 ); -+ -+define_pd_global(intx, OnStackReplacePercentage, 933 ); -+define_pd_global(intx, FreqInlineSize, 325 ); -+define_pd_global(intx, NewSizeThreadIncrease, 4*K ); -+define_pd_global(intx, InitialCodeCacheSize, 160*K); -+define_pd_global(intx, ReservedCodeCacheSize, 32*M ); -+define_pd_global(intx, NonProfiledCodeHeapSize, 13*M ); -+define_pd_global(intx, ProfiledCodeHeapSize, 14*M ); -+define_pd_global(intx, NonNMethodCodeHeapSize, 5*M ); -+define_pd_global(bool, ProfileInterpreter, false); -+define_pd_global(intx, CodeCacheExpansionSize, 32*K ); -+define_pd_global(uintx, CodeCacheMinBlockLength, 1); -+define_pd_global(uintx, CodeCacheMinimumUseSpace, 400*K); -+define_pd_global(uintx, MetaspaceSize, 12*M ); -+define_pd_global(bool, NeverActAsServerClassMachine, true ); -+define_pd_global(uint64_t,MaxRAM, 1ULL*G); -+define_pd_global(bool, CICompileOSR, true ); -+#endif // !COMPILER2 -+define_pd_global(bool, UseTypeProfile, false); -+define_pd_global(bool, RoundFPResults, true ); -+ -+define_pd_global(bool, LIRFillDelaySlots, false); -+define_pd_global(bool, OptimizeSinglePrecision, true ); -+define_pd_global(bool, CSEArrayLength, false); -+define_pd_global(bool, TwoOperandLIRForm, false ); -+ -+#endif // CPU_LOONGARCH_C1_GLOBALS_LOONGARCH_HPP -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/c1_LinearScan_loongarch_64.cpp b/src/hotspot/cpu/loongarch/c1_LinearScan_loongarch_64.cpp ---- a/src/hotspot/cpu/loongarch/c1_LinearScan_loongarch_64.cpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/cpu/loongarch/c1_LinearScan_loongarch_64.cpp 2024-01-30 10:00:11.838098438 +0800 -@@ -0,0 +1,33 @@ -+/* -+ * Copyright (c) 2005, 2011, Oracle and/or its affiliates. All rights reserved. All rights reserved. -+ * Copyright (c) 2021, Loongson Technology. All rights reserved. -+ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. -+ * -+ * This code is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 only, as -+ * published by the Free Software Foundation. -+ * -+ * This code is distributed in the hope that it will be useful, but WITHOUT -+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -+ * version 2 for more details (a copy is included in the LICENSE file that -+ * accompanied this code). -+ * -+ * You should have received a copy of the GNU General Public License version -+ * 2 along with this work; if not, write to the Free Software Foundation, -+ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. -+ * -+ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA -+ * or visit www.oracle.com if you need additional information or have any -+ * questions. -+ * -+ */ -+ -+#include "precompiled.hpp" -+#include "c1/c1_Instruction.hpp" -+#include "c1/c1_LinearScan.hpp" -+#include "utilities/bitMap.inline.hpp" -+ -+void LinearScan::allocate_fpu_stack() { -+ // No FPU stack on LoongArch64 -+} -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/c1_LinearScan_loongarch.hpp b/src/hotspot/cpu/loongarch/c1_LinearScan_loongarch.hpp ---- a/src/hotspot/cpu/loongarch/c1_LinearScan_loongarch.hpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/cpu/loongarch/c1_LinearScan_loongarch.hpp 2024-01-30 10:00:11.838098438 +0800 -@@ -0,0 +1,70 @@ -+/* -+ * Copyright (c) 2005, 2021, Oracle and/or its affiliates. All rights reserved. -+ * Copyright (c) 2021, Loongson Technology. All rights reserved. -+ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. -+ * -+ * This code is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 only, as -+ * published by the Free Software Foundation. -+ * -+ * This code is distributed in the hope that it will be useful, but WITHOUT -+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -+ * version 2 for more details (a copy is included in the LICENSE file that -+ * accompanied this code). -+ * -+ * You should have received a copy of the GNU General Public License version -+ * 2 along with this work; if not, write to the Free Software Foundation, -+ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. -+ * -+ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA -+ * or visit www.oracle.com if you need additional information or have any -+ * questions. -+ * -+ */ -+ -+#ifndef CPU_LOONGARCH_C1_LINEARSCAN_LOONGARCH_HPP -+#define CPU_LOONGARCH_C1_LINEARSCAN_LOONGARCH_HPP -+ -+inline bool LinearScan::is_processed_reg_num(int reg_num) { -+ return reg_num <= FrameMap::last_cpu_reg() || reg_num >= pd_nof_cpu_regs_frame_map; -+} -+ -+inline int LinearScan::num_physical_regs(BasicType type) { -+ return 1; -+} -+ -+inline bool LinearScan::requires_adjacent_regs(BasicType type) { -+ return false; -+} -+ -+inline bool LinearScan::is_caller_save(int assigned_reg) { -+ assert(assigned_reg >= 0 && assigned_reg < nof_regs, "should call this only for registers"); -+ if (assigned_reg < pd_first_callee_saved_reg) -+ return true; -+ if (assigned_reg > pd_last_callee_saved_reg && assigned_reg < pd_first_callee_saved_fpu_reg) -+ return true; -+ if (assigned_reg > pd_last_callee_saved_fpu_reg && assigned_reg < pd_last_fpu_reg) -+ return true; -+ return false; -+} -+ -+inline void LinearScan::pd_add_temps(LIR_Op* op) {} -+ -+// Implementation of LinearScanWalker -+inline bool LinearScanWalker::pd_init_regs_for_alloc(Interval* cur) { -+ if (allocator()->gen()->is_vreg_flag_set(cur->reg_num(), LIRGenerator::callee_saved)) { -+ assert(cur->type() != T_FLOAT && cur->type() != T_DOUBLE, "cpu regs only"); -+ _first_reg = pd_first_callee_saved_reg; -+ _last_reg = pd_last_callee_saved_reg; -+ return true; -+ } else if (cur->type() == T_INT || cur->type() == T_LONG || cur->type() == T_OBJECT || -+ cur->type() == T_ADDRESS || cur->type() == T_METADATA) { -+ _first_reg = pd_first_cpu_reg; -+ _last_reg = pd_last_allocatable_cpu_reg; -+ return true; -+ } -+ return false; -+} -+ -+#endif // CPU_LOONGARCH_C1_LINEARSCAN_LOONGARCH_HPP -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/c1_LIRAssembler_loongarch_64.cpp b/src/hotspot/cpu/loongarch/c1_LIRAssembler_loongarch_64.cpp ---- a/src/hotspot/cpu/loongarch/c1_LIRAssembler_loongarch_64.cpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/cpu/loongarch/c1_LIRAssembler_loongarch_64.cpp 2024-01-30 10:00:11.834765144 +0800 -@@ -0,0 +1,3387 @@ -+/* -+ * Copyright (c) 2000, 2021, Oracle and/or its affiliates. All rights reserved. -+ * Copyright (c) 2021, Loongson Technology. All rights reserved. ++ * Copyright (c) 2021, Loongson Technology. All rights reserved. + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. + * + * This code is free software; you can redistribute it and/or modify it @@ -8807,100 +8743,15 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h +} + +#undef __ -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/c1_LIRAssembler_loongarch.hpp b/src/hotspot/cpu/loongarch/c1_LIRAssembler_loongarch.hpp ---- a/src/hotspot/cpu/loongarch/c1_LIRAssembler_loongarch.hpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/cpu/loongarch/c1_LIRAssembler_loongarch.hpp 2024-01-30 10:00:11.834765144 +0800 -@@ -0,0 +1,83 @@ -+/* -+ * Copyright (c) 2000, 2021, Oracle and/or its affiliates. All rights reserved. -+ * Copyright (c) 2021, Loongson Technology. All rights reserved. -+ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. -+ * -+ * This code is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 only, as -+ * published by the Free Software Foundation. -+ * -+ * This code is distributed in the hope that it will be useful, but WITHOUT -+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -+ * version 2 for more details (a copy is included in the LICENSE file that -+ * accompanied this code). -+ * -+ * You should have received a copy of the GNU General Public License version -+ * 2 along with this work; if not, write to the Free Software Foundation, -+ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. -+ * -+ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA -+ * or visit www.oracle.com if you need additional information or have any -+ * questions. -+ * -+ */ -+ -+#ifndef CPU_LOONGARCH_C1_LIRASSEMBLER_LOONGARCH_HPP -+#define CPU_LOONGARCH_C1_LIRASSEMBLER_LOONGARCH_HPP -+ -+// ArrayCopyStub needs access to bailout -+friend class ArrayCopyStub; -+ -+ private: -+ int array_element_size(BasicType type) const; -+ -+ void arith_fpu_implementation(LIR_Code code, int left_index, int right_index, -+ int dest_index, bool pop_fpu_stack); -+ -+ // helper functions which checks for overflow and sets bailout if it -+ // occurs. Always returns a valid embeddable pointer but in the -+ // bailout case the pointer won't be to unique storage. -+ address float_constant(float f); -+ address double_constant(double d); -+ -+ address int_constant(jlong n); -+ -+ bool is_literal_address(LIR_Address* addr); -+ -+ // Ensure we have a valid Address (base+offset) to a stack-slot. -+ Address stack_slot_address(int index, uint shift, int adjust = 0); -+ -+ // Record the type of the receiver in ReceiverTypeData -+ void type_profile_helper(Register mdo, ciMethodData *md, ciProfileData *data, -+ Register recv, Label* update_done); -+ void add_debug_info_for_branch(address adr, CodeEmitInfo* info); -+ -+ void casw(Register addr, Register newval, Register cmpval, bool sign); -+ void casl(Register addr, Register newval, Register cmpval); -+ -+ void poll_for_safepoint(relocInfo::relocType rtype, CodeEmitInfo* info = NULL); -+ -+ static const int max_tableswitches = 20; -+ struct tableswitch switches[max_tableswitches]; -+ int tableswitch_count; -+ -+ void init() { tableswitch_count = 0; } -+ -+ void deoptimize_trap(CodeEmitInfo *info); -+ -+ enum { -+ // call stub: CompiledStaticCall::to_interp_stub_size() + -+ // CompiledStaticCall::to_trampoline_stub_size() -+ _call_stub_size = 13 * NativeInstruction::nop_instruction_size, -+ _call_aot_stub_size = 0, -+ _exception_handler_size = DEBUG_ONLY(1*K) NOT_DEBUG(175), -+ _deopt_handler_size = 7 * NativeInstruction::nop_instruction_size -+ }; -+ -+public: -+ void store_parameter(Register r, int offset_from_sp_in_words); -+ void store_parameter(jint c, int offset_from_sp_in_words); -+ void store_parameter(jobject c, int offset_from_sp_in_words); -+ -+#endif // CPU_LOONGARCH_C1_LIRASSEMBLER_LOONGARCH_HPP -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/c1_LIRGenerator_loongarch_64.cpp b/src/hotspot/cpu/loongarch/c1_LIRGenerator_loongarch_64.cpp ---- a/src/hotspot/cpu/loongarch/c1_LIRGenerator_loongarch_64.cpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/cpu/loongarch/c1_LIRGenerator_loongarch_64.cpp 2024-01-30 10:00:11.834765144 +0800 -@@ -0,0 +1,1396 @@ +diff --git a/src/hotspot/cpu/loongarch/c1_LIRGenerator_loongarch_64.cpp b/src/hotspot/cpu/loongarch/c1_LIRGenerator_loongarch_64.cpp +new file mode 100644 +index 0000000000..6cb77f3fbe +--- /dev/null ++++ b/src/hotspot/cpu/loongarch/c1_LIRGenerator_loongarch_64.cpp +@@ -0,0 +1,1398 @@ +/* + * Copyright (c) 2005, 2021, Oracle and/or its affiliates. All rights reserved. -+ * Copyright (c) 2021, 2022, Loongson Technology. All rights reserved. ++ * Copyright (c) 2021, 2024, Loongson Technology. All rights reserved. + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. + * + * This code is free software; you can redistribute it and/or modify it @@ -9056,8 +8907,10 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h + if (index->is_register()) { + // apply the shift and accumulate the displacement + if (shift > 0) { -+ LIR_Opr tmp = new_pointer_register(); -+ __ shift_left(index, shift, tmp); ++ // Use long register to avoid overflow when shifting large index values left. ++ LIR_Opr tmp = new_register(T_LONG); ++ __ convert(Bytecodes::_i2l, index, tmp); ++ __ shift_left(tmp, shift, tmp); + index = tmp; + } + if (large_disp != 0) { @@ -10294,9 +10147,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h + } + __ volatile_load_mem_reg(address, result, info); +} -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/c1_LIR_loongarch_64.cpp b/src/hotspot/cpu/loongarch/c1_LIR_loongarch_64.cpp ---- a/src/hotspot/cpu/loongarch/c1_LIR_loongarch_64.cpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/cpu/loongarch/c1_LIR_loongarch_64.cpp 2024-01-30 10:00:11.834765144 +0800 +diff --git a/src/hotspot/cpu/loongarch/c1_LIR_loongarch_64.cpp b/src/hotspot/cpu/loongarch/c1_LIR_loongarch_64.cpp +new file mode 100644 +index 0000000000..6bb15fbf1d +--- /dev/null ++++ b/src/hotspot/cpu/loongarch/c1_LIR_loongarch_64.cpp @@ -0,0 +1,75 @@ +/* + * Copyright (c) 2016, 2021, Oracle and/or its affiliates. All rights reserved. @@ -10373,9 +10228,244 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h +void LIR_List::cmp_cmove(LIR_Condition condition, LIR_Opr left, LIR_Opr right, LIR_Opr src1, LIR_Opr src2, LIR_Opr dst, BasicType type) { + append(new LIR_Op4(lir_cmp_cmove, condition, left, right, src1, src2, dst, type)); +} -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/c1_MacroAssembler_loongarch_64.cpp b/src/hotspot/cpu/loongarch/c1_MacroAssembler_loongarch_64.cpp ---- a/src/hotspot/cpu/loongarch/c1_MacroAssembler_loongarch_64.cpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/cpu/loongarch/c1_MacroAssembler_loongarch_64.cpp 2024-01-30 10:00:11.838098438 +0800 +diff --git a/src/hotspot/cpu/loongarch/c1_LinearScan_loongarch.hpp b/src/hotspot/cpu/loongarch/c1_LinearScan_loongarch.hpp +new file mode 100644 +index 0000000000..f15dacafeb +--- /dev/null ++++ b/src/hotspot/cpu/loongarch/c1_LinearScan_loongarch.hpp +@@ -0,0 +1,70 @@ ++/* ++ * Copyright (c) 2005, 2021, Oracle and/or its affiliates. All rights reserved. ++ * Copyright (c) 2021, Loongson Technology. All rights reserved. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ * ++ */ ++ ++#ifndef CPU_LOONGARCH_C1_LINEARSCAN_LOONGARCH_HPP ++#define CPU_LOONGARCH_C1_LINEARSCAN_LOONGARCH_HPP ++ ++inline bool LinearScan::is_processed_reg_num(int reg_num) { ++ return reg_num <= FrameMap::last_cpu_reg() || reg_num >= pd_nof_cpu_regs_frame_map; ++} ++ ++inline int LinearScan::num_physical_regs(BasicType type) { ++ return 1; ++} ++ ++inline bool LinearScan::requires_adjacent_regs(BasicType type) { ++ return false; ++} ++ ++inline bool LinearScan::is_caller_save(int assigned_reg) { ++ assert(assigned_reg >= 0 && assigned_reg < nof_regs, "should call this only for registers"); ++ if (assigned_reg < pd_first_callee_saved_reg) ++ return true; ++ if (assigned_reg > pd_last_callee_saved_reg && assigned_reg < pd_first_callee_saved_fpu_reg) ++ return true; ++ if (assigned_reg > pd_last_callee_saved_fpu_reg && assigned_reg < pd_last_fpu_reg) ++ return true; ++ return false; ++} ++ ++inline void LinearScan::pd_add_temps(LIR_Op* op) {} ++ ++// Implementation of LinearScanWalker ++inline bool LinearScanWalker::pd_init_regs_for_alloc(Interval* cur) { ++ if (allocator()->gen()->is_vreg_flag_set(cur->reg_num(), LIRGenerator::callee_saved)) { ++ assert(cur->type() != T_FLOAT && cur->type() != T_DOUBLE, "cpu regs only"); ++ _first_reg = pd_first_callee_saved_reg; ++ _last_reg = pd_last_callee_saved_reg; ++ return true; ++ } else if (cur->type() == T_INT || cur->type() == T_LONG || cur->type() == T_OBJECT || ++ cur->type() == T_ADDRESS || cur->type() == T_METADATA) { ++ _first_reg = pd_first_cpu_reg; ++ _last_reg = pd_last_allocatable_cpu_reg; ++ return true; ++ } ++ return false; ++} ++ ++#endif // CPU_LOONGARCH_C1_LINEARSCAN_LOONGARCH_HPP +diff --git a/src/hotspot/cpu/loongarch/c1_LinearScan_loongarch_64.cpp b/src/hotspot/cpu/loongarch/c1_LinearScan_loongarch_64.cpp +new file mode 100644 +index 0000000000..219b2e3671 +--- /dev/null ++++ b/src/hotspot/cpu/loongarch/c1_LinearScan_loongarch_64.cpp +@@ -0,0 +1,33 @@ ++/* ++ * Copyright (c) 2005, 2011, Oracle and/or its affiliates. All rights reserved. All rights reserved. ++ * Copyright (c) 2021, Loongson Technology. All rights reserved. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ * ++ */ ++ ++#include "precompiled.hpp" ++#include "c1/c1_Instruction.hpp" ++#include "c1/c1_LinearScan.hpp" ++#include "utilities/bitMap.inline.hpp" ++ ++void LinearScan::allocate_fpu_stack() { ++ // No FPU stack on LoongArch64 ++} +diff --git a/src/hotspot/cpu/loongarch/c1_MacroAssembler_loongarch.hpp b/src/hotspot/cpu/loongarch/c1_MacroAssembler_loongarch.hpp +new file mode 100644 +index 0000000000..38ff4c5836 +--- /dev/null ++++ b/src/hotspot/cpu/loongarch/c1_MacroAssembler_loongarch.hpp +@@ -0,0 +1,112 @@ ++/* ++ * Copyright (c) 1999, 2021, Oracle and/or its affiliates. All rights reserved. ++ * Copyright (c) 2021, Loongson Technology. All rights reserved. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ * ++ */ ++ ++#ifndef CPU_LOONGARCH_C1_MACROASSEMBLER_LOONGARCH_HPP ++#define CPU_LOONGARCH_C1_MACROASSEMBLER_LOONGARCH_HPP ++ ++using MacroAssembler::build_frame; ++using MacroAssembler::null_check; ++ ++// C1_MacroAssembler contains high-level macros for C1 ++ ++ private: ++ int _rsp_offset; // track rsp changes ++ // initialization ++ void pd_init() { _rsp_offset = 0; } ++ ++ public: ++ void try_allocate( ++ Register obj, // result: pointer to object after successful allocation ++ Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise ++ int con_size_in_bytes, // object size in bytes if known at compile time ++ Register t1, // temp register ++ Register t2, // temp register ++ Label& slow_case // continuation point if fast allocation fails ++ ); ++ ++ void initialize_header(Register obj, Register klass, Register len, Register t1, Register t2); ++ void initialize_body(Register obj, Register len_in_bytes, int hdr_size_in_bytes, Register t1, Register t2); ++ ++ // locking ++ // hdr : must be A0, contents destroyed ++ // obj : must point to the object to lock, contents preserved ++ // disp_hdr: must point to the displaced header location, contents preserved ++ // scratch : scratch register, contents destroyed ++ // returns code offset at which to add null check debug information ++ int lock_object (Register swap, Register obj, Register disp_hdr, Register scratch, Label& slow_case); ++ ++ // unlocking ++ // hdr : contents destroyed ++ // obj : must point to the object to lock, contents preserved ++ // disp_hdr: must be A0 & must point to the displaced header location, contents destroyed ++ void unlock_object(Register swap, Register obj, Register lock, Label& slow_case); ++ ++ void initialize_object( ++ Register obj, // result: pointer to object after successful allocation ++ Register klass, // object klass ++ Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise ++ int con_size_in_bytes, // object size in bytes if known at compile time ++ Register t1, // temp register ++ Register t2, // temp register ++ bool is_tlab_allocated // the object was allocated in a TLAB; relevant for the implementation of ZeroTLAB ++ ); ++ ++ // allocation of fixed-size objects ++ // (can also be used to allocate fixed-size arrays, by setting ++ // hdr_size correctly and storing the array length afterwards) ++ // obj : will contain pointer to allocated object ++ // t1, t2 : scratch registers - contents destroyed ++ // header_size: size of object header in words ++ // object_size: total size of object in words ++ // slow_case : exit to slow case implementation if fast allocation fails ++ void allocate_object(Register obj, Register t1, Register t2, int header_size, ++ int object_size, Register klass, Label& slow_case); ++ ++ enum { ++ max_array_allocation_length = 0x00FFFFFF ++ }; ++ ++ // allocation of arrays ++ // obj : will contain pointer to allocated object ++ // len : array length in number of elements ++ // t : scratch register - contents destroyed ++ // header_size: size of object header in words ++ // f : element scale factor ++ // slow_case : exit to slow case implementation if fast allocation fails ++ void allocate_array(Register obj, Register len, Register t, Register t2, int header_size, ++ int f, Register klass, Label& slow_case); ++ ++ int rsp_offset() const { return _rsp_offset; } ++ void set_rsp_offset(int n) { _rsp_offset = n; } ++ ++ void invalidate_registers(bool inv_a0, bool inv_s0, bool inv_a2, bool inv_a3, ++ bool inv_a4, bool inv_a5) PRODUCT_RETURN; ++ ++ // This platform only uses signal-based null checks. The Label is not needed. ++ void null_check(Register r, Label *Lnull = NULL) { MacroAssembler::null_check(r); } ++ ++ void load_parameter(int offset_in_words, Register reg); ++ ++#endif // CPU_LOONGARCH_C1_MACROASSEMBLER_LOONGARCH_HPP +diff --git a/src/hotspot/cpu/loongarch/c1_MacroAssembler_loongarch_64.cpp b/src/hotspot/cpu/loongarch/c1_MacroAssembler_loongarch_64.cpp +new file mode 100644 +index 0000000000..17ff93a595 +--- /dev/null ++++ b/src/hotspot/cpu/loongarch/c1_MacroAssembler_loongarch_64.cpp @@ -0,0 +1,344 @@ +/* + * Copyright (c) 1999, 2021, Oracle and/or its affiliates. All rights reserved. @@ -10721,125 +10811,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h +#endif +} +#endif // ifndef PRODUCT -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/c1_MacroAssembler_loongarch.hpp b/src/hotspot/cpu/loongarch/c1_MacroAssembler_loongarch.hpp ---- a/src/hotspot/cpu/loongarch/c1_MacroAssembler_loongarch.hpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/cpu/loongarch/c1_MacroAssembler_loongarch.hpp 2024-01-30 10:00:11.838098438 +0800 -@@ -0,0 +1,112 @@ -+/* -+ * Copyright (c) 1999, 2021, Oracle and/or its affiliates. All rights reserved. -+ * Copyright (c) 2021, Loongson Technology. All rights reserved. -+ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. -+ * -+ * This code is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 only, as -+ * published by the Free Software Foundation. -+ * -+ * This code is distributed in the hope that it will be useful, but WITHOUT -+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -+ * version 2 for more details (a copy is included in the LICENSE file that -+ * accompanied this code). -+ * -+ * You should have received a copy of the GNU General Public License version -+ * 2 along with this work; if not, write to the Free Software Foundation, -+ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. -+ * -+ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA -+ * or visit www.oracle.com if you need additional information or have any -+ * questions. -+ * -+ */ -+ -+#ifndef CPU_LOONGARCH_C1_MACROASSEMBLER_LOONGARCH_HPP -+#define CPU_LOONGARCH_C1_MACROASSEMBLER_LOONGARCH_HPP -+ -+using MacroAssembler::build_frame; -+using MacroAssembler::null_check; -+ -+// C1_MacroAssembler contains high-level macros for C1 -+ -+ private: -+ int _rsp_offset; // track rsp changes -+ // initialization -+ void pd_init() { _rsp_offset = 0; } -+ -+ public: -+ void try_allocate( -+ Register obj, // result: pointer to object after successful allocation -+ Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise -+ int con_size_in_bytes, // object size in bytes if known at compile time -+ Register t1, // temp register -+ Register t2, // temp register -+ Label& slow_case // continuation point if fast allocation fails -+ ); -+ -+ void initialize_header(Register obj, Register klass, Register len, Register t1, Register t2); -+ void initialize_body(Register obj, Register len_in_bytes, int hdr_size_in_bytes, Register t1, Register t2); -+ -+ // locking -+ // hdr : must be A0, contents destroyed -+ // obj : must point to the object to lock, contents preserved -+ // disp_hdr: must point to the displaced header location, contents preserved -+ // scratch : scratch register, contents destroyed -+ // returns code offset at which to add null check debug information -+ int lock_object (Register swap, Register obj, Register disp_hdr, Register scratch, Label& slow_case); -+ -+ // unlocking -+ // hdr : contents destroyed -+ // obj : must point to the object to lock, contents preserved -+ // disp_hdr: must be A0 & must point to the displaced header location, contents destroyed -+ void unlock_object(Register swap, Register obj, Register lock, Label& slow_case); -+ -+ void initialize_object( -+ Register obj, // result: pointer to object after successful allocation -+ Register klass, // object klass -+ Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise -+ int con_size_in_bytes, // object size in bytes if known at compile time -+ Register t1, // temp register -+ Register t2, // temp register -+ bool is_tlab_allocated // the object was allocated in a TLAB; relevant for the implementation of ZeroTLAB -+ ); -+ -+ // allocation of fixed-size objects -+ // (can also be used to allocate fixed-size arrays, by setting -+ // hdr_size correctly and storing the array length afterwards) -+ // obj : will contain pointer to allocated object -+ // t1, t2 : scratch registers - contents destroyed -+ // header_size: size of object header in words -+ // object_size: total size of object in words -+ // slow_case : exit to slow case implementation if fast allocation fails -+ void allocate_object(Register obj, Register t1, Register t2, int header_size, -+ int object_size, Register klass, Label& slow_case); -+ -+ enum { -+ max_array_allocation_length = 0x00FFFFFF -+ }; -+ -+ // allocation of arrays -+ // obj : will contain pointer to allocated object -+ // len : array length in number of elements -+ // t : scratch register - contents destroyed -+ // header_size: size of object header in words -+ // f : element scale factor -+ // slow_case : exit to slow case implementation if fast allocation fails -+ void allocate_array(Register obj, Register len, Register t, Register t2, int header_size, -+ int f, Register klass, Label& slow_case); -+ -+ int rsp_offset() const { return _rsp_offset; } -+ void set_rsp_offset(int n) { _rsp_offset = n; } -+ -+ void invalidate_registers(bool inv_a0, bool inv_s0, bool inv_a2, bool inv_a3, -+ bool inv_a4, bool inv_a5) PRODUCT_RETURN; -+ -+ // This platform only uses signal-based null checks. The Label is not needed. -+ void null_check(Register r, Label *Lnull = NULL) { MacroAssembler::null_check(r); } -+ -+ void load_parameter(int offset_in_words, Register reg); -+ -+#endif // CPU_LOONGARCH_C1_MACROASSEMBLER_LOONGARCH_HPP -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/c1_Runtime1_loongarch_64.cpp b/src/hotspot/cpu/loongarch/c1_Runtime1_loongarch_64.cpp ---- a/src/hotspot/cpu/loongarch/c1_Runtime1_loongarch_64.cpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/cpu/loongarch/c1_Runtime1_loongarch_64.cpp 2024-01-30 10:00:11.838098438 +0800 +diff --git a/src/hotspot/cpu/loongarch/c1_Runtime1_loongarch_64.cpp b/src/hotspot/cpu/loongarch/c1_Runtime1_loongarch_64.cpp +new file mode 100644 +index 0000000000..aaa708f71e +--- /dev/null ++++ b/src/hotspot/cpu/loongarch/c1_Runtime1_loongarch_64.cpp @@ -0,0 +1,1138 @@ +/* + * Copyright (c) 1999, 2021, Oracle and/or its affiliates. All rights reserved. @@ -11979,9 +11955,88 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h + Unimplemented(); + return 0; +} -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/c2_globals_loongarch.hpp b/src/hotspot/cpu/loongarch/c2_globals_loongarch.hpp ---- a/src/hotspot/cpu/loongarch/c2_globals_loongarch.hpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/cpu/loongarch/c2_globals_loongarch.hpp 2024-01-30 10:00:11.838098438 +0800 +diff --git a/src/hotspot/cpu/loongarch/c1_globals_loongarch.hpp b/src/hotspot/cpu/loongarch/c1_globals_loongarch.hpp +new file mode 100644 +index 0000000000..164016e123 +--- /dev/null ++++ b/src/hotspot/cpu/loongarch/c1_globals_loongarch.hpp +@@ -0,0 +1,71 @@ ++/* ++ * Copyright (c) 2000, 2021, Oracle and/or its affiliates. All rights reserved. ++ * Copyright (c) 2021, 2022, Loongson Technology. All rights reserved. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ * ++ */ ++ ++#ifndef CPU_LOONGARCH_C1_GLOBALS_LOONGARCH_HPP ++#define CPU_LOONGARCH_C1_GLOBALS_LOONGARCH_HPP ++ ++#include "utilities/globalDefinitions.hpp" ++#include "utilities/macros.hpp" ++ ++// Sets the default values for platform dependent flags used by the client compiler. ++// (see c1_globals.hpp) ++ ++#ifndef COMPILER2 ++define_pd_global(bool, BackgroundCompilation, true ); ++define_pd_global(bool, UseTLAB, true ); ++define_pd_global(bool, ResizeTLAB, true ); ++define_pd_global(bool, InlineIntrinsics, true ); ++define_pd_global(bool, PreferInterpreterNativeStubs, false); ++define_pd_global(bool, ProfileTraps, false); ++define_pd_global(bool, UseOnStackReplacement, true ); ++define_pd_global(bool, TieredCompilation, false); ++define_pd_global(intx, CompileThreshold, 1500 ); ++ ++define_pd_global(intx, OnStackReplacePercentage, 933 ); ++define_pd_global(intx, FreqInlineSize, 325 ); ++define_pd_global(intx, NewSizeThreadIncrease, 4*K ); ++define_pd_global(intx, InitialCodeCacheSize, 160*K); ++define_pd_global(intx, ReservedCodeCacheSize, 32*M ); ++define_pd_global(intx, NonProfiledCodeHeapSize, 13*M ); ++define_pd_global(intx, ProfiledCodeHeapSize, 14*M ); ++define_pd_global(intx, NonNMethodCodeHeapSize, 5*M ); ++define_pd_global(bool, ProfileInterpreter, false); ++define_pd_global(intx, CodeCacheExpansionSize, 32*K ); ++define_pd_global(uintx, CodeCacheMinBlockLength, 1); ++define_pd_global(uintx, CodeCacheMinimumUseSpace, 400*K); ++define_pd_global(uintx, MetaspaceSize, 12*M ); ++define_pd_global(bool, NeverActAsServerClassMachine, true ); ++define_pd_global(uint64_t,MaxRAM, 1ULL*G); ++define_pd_global(bool, CICompileOSR, true ); ++#endif // !COMPILER2 ++define_pd_global(bool, UseTypeProfile, false); ++define_pd_global(bool, RoundFPResults, true ); ++ ++define_pd_global(bool, LIRFillDelaySlots, false); ++define_pd_global(bool, OptimizeSinglePrecision, true ); ++define_pd_global(bool, CSEArrayLength, false); ++define_pd_global(bool, TwoOperandLIRForm, false ); ++ ++#endif // CPU_LOONGARCH_C1_GLOBALS_LOONGARCH_HPP +diff --git a/src/hotspot/cpu/loongarch/c2_globals_loongarch.hpp b/src/hotspot/cpu/loongarch/c2_globals_loongarch.hpp +new file mode 100644 +index 0000000000..27a4ec5229 +--- /dev/null ++++ b/src/hotspot/cpu/loongarch/c2_globals_loongarch.hpp @@ -0,0 +1,94 @@ +/* + * Copyright (c) 2000, 2013, Oracle and/or its affiliates. All rights reserved. @@ -12077,9 +12132,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h +define_pd_global(bool, NeverActAsServerClassMachine, false); + +#endif // CPU_LOONGARCH_C2_GLOBALS_LOONGARCH_HPP -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/c2_init_loongarch.cpp b/src/hotspot/cpu/loongarch/c2_init_loongarch.cpp ---- a/src/hotspot/cpu/loongarch/c2_init_loongarch.cpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/cpu/loongarch/c2_init_loongarch.cpp 2024-01-30 10:00:11.838098438 +0800 +diff --git a/src/hotspot/cpu/loongarch/c2_init_loongarch.cpp b/src/hotspot/cpu/loongarch/c2_init_loongarch.cpp +new file mode 100644 +index 0000000000..ec78b942d4 +--- /dev/null ++++ b/src/hotspot/cpu/loongarch/c2_init_loongarch.cpp @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2000, 2010, Oracle and/or its affiliates. All rights reserved. @@ -12118,9 +12175,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h + guarantee(CodeEntryAlignment >= InteriorEntryAlignment, "" ); + reg_mask_init(); +} -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/codeBuffer_loongarch.hpp b/src/hotspot/cpu/loongarch/codeBuffer_loongarch.hpp ---- a/src/hotspot/cpu/loongarch/codeBuffer_loongarch.hpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/cpu/loongarch/codeBuffer_loongarch.hpp 2024-01-30 10:00:11.838098438 +0800 +diff --git a/src/hotspot/cpu/loongarch/codeBuffer_loongarch.hpp b/src/hotspot/cpu/loongarch/codeBuffer_loongarch.hpp +new file mode 100644 +index 0000000000..653d95806b +--- /dev/null ++++ b/src/hotspot/cpu/loongarch/codeBuffer_loongarch.hpp @@ -0,0 +1,35 @@ +/* + * Copyright (c) 2002, 2010, Oracle and/or its affiliates. All rights reserved. @@ -12157,9 +12216,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h + void flush_bundle(bool start_new_bundle) {} + +#endif // CPU_LOONGARCH_CODEBUFFER_LOONGARCH_HPP -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/compiledIC_loongarch.cpp b/src/hotspot/cpu/loongarch/compiledIC_loongarch.cpp ---- a/src/hotspot/cpu/loongarch/compiledIC_loongarch.cpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/cpu/loongarch/compiledIC_loongarch.cpp 2024-01-30 10:00:11.838098438 +0800 +diff --git a/src/hotspot/cpu/loongarch/compiledIC_loongarch.cpp b/src/hotspot/cpu/loongarch/compiledIC_loongarch.cpp +new file mode 100644 +index 0000000000..d063d5d93e +--- /dev/null ++++ b/src/hotspot/cpu/loongarch/compiledIC_loongarch.cpp @@ -0,0 +1,148 @@ +/* + * Copyright (c) 1997, 2014, Oracle and/or its affiliates. All rights reserved. @@ -12309,9 +12370,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h +} + +#endif // !PRODUCT -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/copy_loongarch.hpp b/src/hotspot/cpu/loongarch/copy_loongarch.hpp ---- a/src/hotspot/cpu/loongarch/copy_loongarch.hpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/cpu/loongarch/copy_loongarch.hpp 2024-01-30 10:00:11.838098438 +0800 +diff --git a/src/hotspot/cpu/loongarch/copy_loongarch.hpp b/src/hotspot/cpu/loongarch/copy_loongarch.hpp +new file mode 100644 +index 0000000000..54b847a736 +--- /dev/null ++++ b/src/hotspot/cpu/loongarch/copy_loongarch.hpp @@ -0,0 +1,77 @@ +/* + * Copyright (c) 2003, 2010, Oracle and/or its affiliates. All rights reserved. @@ -12390,9 +12453,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h +} + +#endif //CPU_LOONGARCH_COPY_LOONGARCH_HPP -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/depChecker_loongarch.cpp b/src/hotspot/cpu/loongarch/depChecker_loongarch.cpp ---- a/src/hotspot/cpu/loongarch/depChecker_loongarch.cpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/cpu/loongarch/depChecker_loongarch.cpp 2024-01-30 10:00:11.838098438 +0800 +diff --git a/src/hotspot/cpu/loongarch/depChecker_loongarch.cpp b/src/hotspot/cpu/loongarch/depChecker_loongarch.cpp +new file mode 100644 +index 0000000000..e4a92d1035 +--- /dev/null ++++ b/src/hotspot/cpu/loongarch/depChecker_loongarch.cpp @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2002, 2010, Oracle and/or its affiliates. All rights reserved. @@ -12424,9 +12489,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h +#include "depChecker_loongarch.hpp" + +// Nothing to do on LoongArch -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/depChecker_loongarch.hpp b/src/hotspot/cpu/loongarch/depChecker_loongarch.hpp ---- a/src/hotspot/cpu/loongarch/depChecker_loongarch.hpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/cpu/loongarch/depChecker_loongarch.hpp 2024-01-30 10:00:11.838098438 +0800 +diff --git a/src/hotspot/cpu/loongarch/depChecker_loongarch.hpp b/src/hotspot/cpu/loongarch/depChecker_loongarch.hpp +new file mode 100644 +index 0000000000..29c292a74a +--- /dev/null ++++ b/src/hotspot/cpu/loongarch/depChecker_loongarch.hpp @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2002, 2010, Oracle and/or its affiliates. All rights reserved. @@ -12459,9 +12526,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h +// Nothing to do on LoongArch + +#endif // CPU_LOONGARCH_DEPCHECKER_LOONGARCH_HPP -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/disassembler_loongarch.hpp b/src/hotspot/cpu/loongarch/disassembler_loongarch.hpp ---- a/src/hotspot/cpu/loongarch/disassembler_loongarch.hpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/cpu/loongarch/disassembler_loongarch.hpp 2024-01-30 10:00:11.838098438 +0800 +diff --git a/src/hotspot/cpu/loongarch/disassembler_loongarch.hpp b/src/hotspot/cpu/loongarch/disassembler_loongarch.hpp +new file mode 100644 +index 0000000000..04359bc172 +--- /dev/null ++++ b/src/hotspot/cpu/loongarch/disassembler_loongarch.hpp @@ -0,0 +1,37 @@ +/* + * Copyright (c) 1997, 2010, Oracle and/or its affiliates. All rights reserved. @@ -12500,9 +12569,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h + } + +#endif // CPU_LOONGARCH_DISASSEMBLER_LOONGARCH_HPP -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/frame_loongarch.cpp b/src/hotspot/cpu/loongarch/frame_loongarch.cpp ---- a/src/hotspot/cpu/loongarch/frame_loongarch.cpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/cpu/loongarch/frame_loongarch.cpp 2024-01-30 10:00:11.838098438 +0800 +diff --git a/src/hotspot/cpu/loongarch/frame_loongarch.cpp b/src/hotspot/cpu/loongarch/frame_loongarch.cpp +new file mode 100644 +index 0000000000..6f6d34e026 +--- /dev/null ++++ b/src/hotspot/cpu/loongarch/frame_loongarch.cpp @@ -0,0 +1,690 @@ +/* + * Copyright (c) 1997, 2014, Oracle and/or its affiliates. All rights reserved. @@ -13194,9 +13265,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h + +void frame::pd_ps() {} +#endif -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/frame_loongarch.hpp b/src/hotspot/cpu/loongarch/frame_loongarch.hpp ---- a/src/hotspot/cpu/loongarch/frame_loongarch.hpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/cpu/loongarch/frame_loongarch.hpp 2024-01-30 10:00:11.838098438 +0800 +diff --git a/src/hotspot/cpu/loongarch/frame_loongarch.hpp b/src/hotspot/cpu/loongarch/frame_loongarch.hpp +new file mode 100644 +index 0000000000..b16389b3a3 +--- /dev/null ++++ b/src/hotspot/cpu/loongarch/frame_loongarch.hpp @@ -0,0 +1,171 @@ +/* + * Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved. @@ -13369,9 +13442,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h + static jint interpreter_frame_expression_stack_direction() { return -1; } + +#endif // CPU_LOONGARCH_FRAME_LOONGARCH_HPP -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/frame_loongarch.inline.hpp b/src/hotspot/cpu/loongarch/frame_loongarch.inline.hpp ---- a/src/hotspot/cpu/loongarch/frame_loongarch.inline.hpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/cpu/loongarch/frame_loongarch.inline.hpp 2024-01-30 10:00:11.838098438 +0800 +diff --git a/src/hotspot/cpu/loongarch/frame_loongarch.inline.hpp b/src/hotspot/cpu/loongarch/frame_loongarch.inline.hpp +new file mode 100644 +index 0000000000..1ddc038eea +--- /dev/null ++++ b/src/hotspot/cpu/loongarch/frame_loongarch.inline.hpp @@ -0,0 +1,252 @@ +/* + * Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved. @@ -13625,9 +13700,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h +} + +#endif // CPU_LOONGARCH_FRAME_LOONGARCH_INLINE_HPP -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/gc/g1/g1BarrierSetAssembler_loongarch.cpp b/src/hotspot/cpu/loongarch/gc/g1/g1BarrierSetAssembler_loongarch.cpp ---- a/src/hotspot/cpu/loongarch/gc/g1/g1BarrierSetAssembler_loongarch.cpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/cpu/loongarch/gc/g1/g1BarrierSetAssembler_loongarch.cpp 2024-01-30 10:00:11.838098438 +0800 +diff --git a/src/hotspot/cpu/loongarch/gc/g1/g1BarrierSetAssembler_loongarch.cpp b/src/hotspot/cpu/loongarch/gc/g1/g1BarrierSetAssembler_loongarch.cpp +new file mode 100644 +index 0000000000..e1e4748c49 +--- /dev/null ++++ b/src/hotspot/cpu/loongarch/gc/g1/g1BarrierSetAssembler_loongarch.cpp @@ -0,0 +1,523 @@ +/* + * Copyright (c) 2018, Oracle and/or its affiliates. All rights reserved. @@ -14152,9 +14229,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h +#undef __ + +#endif // COMPILER1 -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/gc/g1/g1BarrierSetAssembler_loongarch.hpp b/src/hotspot/cpu/loongarch/gc/g1/g1BarrierSetAssembler_loongarch.hpp ---- a/src/hotspot/cpu/loongarch/gc/g1/g1BarrierSetAssembler_loongarch.hpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/cpu/loongarch/gc/g1/g1BarrierSetAssembler_loongarch.hpp 2024-01-30 10:00:11.838098438 +0800 +diff --git a/src/hotspot/cpu/loongarch/gc/g1/g1BarrierSetAssembler_loongarch.hpp b/src/hotspot/cpu/loongarch/gc/g1/g1BarrierSetAssembler_loongarch.hpp +new file mode 100644 +index 0000000000..745046ac0c +--- /dev/null ++++ b/src/hotspot/cpu/loongarch/gc/g1/g1BarrierSetAssembler_loongarch.hpp @@ -0,0 +1,71 @@ +/* + * Copyright (c) 2018, Oracle and/or its affiliates. All rights reserved. @@ -14227,9 +14306,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h +}; + +#endif // CPU_LOONGARCH_GC_G1_G1BARRIERSETASSEMBLER_LOONGARCH_HPP -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/gc/shared/barrierSetAssembler_loongarch.cpp b/src/hotspot/cpu/loongarch/gc/shared/barrierSetAssembler_loongarch.cpp ---- a/src/hotspot/cpu/loongarch/gc/shared/barrierSetAssembler_loongarch.cpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/cpu/loongarch/gc/shared/barrierSetAssembler_loongarch.cpp 2024-01-30 10:00:11.838098438 +0800 +diff --git a/src/hotspot/cpu/loongarch/gc/shared/barrierSetAssembler_loongarch.cpp b/src/hotspot/cpu/loongarch/gc/shared/barrierSetAssembler_loongarch.cpp +new file mode 100644 +index 0000000000..a890cd3f62 +--- /dev/null ++++ b/src/hotspot/cpu/loongarch/gc/shared/barrierSetAssembler_loongarch.cpp @@ -0,0 +1,255 @@ +/* + * Copyright (c) 2018, Oracle and/or its affiliates. All rights reserved. @@ -14486,9 +14567,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h + __ addi_d(t1, t1, con_size_in_bytes); + __ st_ptr(t1, Address(TREG, in_bytes(JavaThread::allocated_bytes_offset()))); +} -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/gc/shared/barrierSetAssembler_loongarch.hpp b/src/hotspot/cpu/loongarch/gc/shared/barrierSetAssembler_loongarch.hpp ---- a/src/hotspot/cpu/loongarch/gc/shared/barrierSetAssembler_loongarch.hpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/cpu/loongarch/gc/shared/barrierSetAssembler_loongarch.hpp 2024-01-30 10:00:11.838098438 +0800 +diff --git a/src/hotspot/cpu/loongarch/gc/shared/barrierSetAssembler_loongarch.hpp b/src/hotspot/cpu/loongarch/gc/shared/barrierSetAssembler_loongarch.hpp +new file mode 100644 +index 0000000000..a7ebbfaabb +--- /dev/null ++++ b/src/hotspot/cpu/loongarch/gc/shared/barrierSetAssembler_loongarch.hpp @@ -0,0 +1,88 @@ +/* + * Copyright (c) 2018, Oracle and/or its affiliates. All rights reserved. @@ -14578,9 +14661,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h +}; + +#endif // CPU_LOONGARCH_GC_SHARED_BARRIERSETASSEMBLER_LOONGARCH_HPP -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/gc/shared/cardTableBarrierSetAssembler_loongarch.cpp b/src/hotspot/cpu/loongarch/gc/shared/cardTableBarrierSetAssembler_loongarch.cpp ---- a/src/hotspot/cpu/loongarch/gc/shared/cardTableBarrierSetAssembler_loongarch.cpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/cpu/loongarch/gc/shared/cardTableBarrierSetAssembler_loongarch.cpp 2024-01-30 10:00:11.838098438 +0800 +diff --git a/src/hotspot/cpu/loongarch/gc/shared/cardTableBarrierSetAssembler_loongarch.cpp b/src/hotspot/cpu/loongarch/gc/shared/cardTableBarrierSetAssembler_loongarch.cpp +new file mode 100644 +index 0000000000..d09e9a75a7 +--- /dev/null ++++ b/src/hotspot/cpu/loongarch/gc/shared/cardTableBarrierSetAssembler_loongarch.cpp @@ -0,0 +1,140 @@ +/* + * Copyright (c) 2018, Oracle and/or its affiliates. All rights reserved. @@ -14722,9 +14807,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h + } + } +} -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/gc/shared/cardTableBarrierSetAssembler_loongarch.hpp b/src/hotspot/cpu/loongarch/gc/shared/cardTableBarrierSetAssembler_loongarch.hpp ---- a/src/hotspot/cpu/loongarch/gc/shared/cardTableBarrierSetAssembler_loongarch.hpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/cpu/loongarch/gc/shared/cardTableBarrierSetAssembler_loongarch.hpp 2024-01-30 10:00:11.838098438 +0800 +diff --git a/src/hotspot/cpu/loongarch/gc/shared/cardTableBarrierSetAssembler_loongarch.hpp b/src/hotspot/cpu/loongarch/gc/shared/cardTableBarrierSetAssembler_loongarch.hpp +new file mode 100644 +index 0000000000..b37c2ba0bc +--- /dev/null ++++ b/src/hotspot/cpu/loongarch/gc/shared/cardTableBarrierSetAssembler_loongarch.hpp @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2018, Oracle and/or its affiliates. All rights reserved. @@ -14770,9 +14857,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h +}; + +#endif // CPU_LOONGARCH_GC_SHARED_CARDTABLEBARRIERSETASSEMBLER_LOONGARCH_HPP -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/gc/shared/modRefBarrierSetAssembler_loongarch.cpp b/src/hotspot/cpu/loongarch/gc/shared/modRefBarrierSetAssembler_loongarch.cpp ---- a/src/hotspot/cpu/loongarch/gc/shared/modRefBarrierSetAssembler_loongarch.cpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/cpu/loongarch/gc/shared/modRefBarrierSetAssembler_loongarch.cpp 2024-01-30 10:00:11.838098438 +0800 +diff --git a/src/hotspot/cpu/loongarch/gc/shared/modRefBarrierSetAssembler_loongarch.cpp b/src/hotspot/cpu/loongarch/gc/shared/modRefBarrierSetAssembler_loongarch.cpp +new file mode 100644 +index 0000000000..14c41ea790 +--- /dev/null ++++ b/src/hotspot/cpu/loongarch/gc/shared/modRefBarrierSetAssembler_loongarch.cpp @@ -0,0 +1,53 @@ +/* + * Copyright (c) 2018, Oracle and/or its affiliates. All rights reserved. @@ -14827,9 +14916,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h + BarrierSetAssembler::store_at(masm, decorators, type, dst, val, tmp1, tmp2); + } +} -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/gc/shared/modRefBarrierSetAssembler_loongarch.hpp b/src/hotspot/cpu/loongarch/gc/shared/modRefBarrierSetAssembler_loongarch.hpp ---- a/src/hotspot/cpu/loongarch/gc/shared/modRefBarrierSetAssembler_loongarch.hpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/cpu/loongarch/gc/shared/modRefBarrierSetAssembler_loongarch.hpp 2024-01-30 10:00:11.838098438 +0800 +diff --git a/src/hotspot/cpu/loongarch/gc/shared/modRefBarrierSetAssembler_loongarch.hpp b/src/hotspot/cpu/loongarch/gc/shared/modRefBarrierSetAssembler_loongarch.hpp +new file mode 100644 +index 0000000000..8043220eff +--- /dev/null ++++ b/src/hotspot/cpu/loongarch/gc/shared/modRefBarrierSetAssembler_loongarch.hpp @@ -0,0 +1,54 @@ +/* + * Copyright (c) 2018, Oracle and/or its affiliates. All rights reserved. @@ -14885,9 +14976,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h +}; + +#endif // CPU_LOONGARCH_GC_SHARED_MODREFBARRIERSETASSEMBLER_LOONGARCH_HPP -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/globalDefinitions_loongarch.hpp b/src/hotspot/cpu/loongarch/globalDefinitions_loongarch.hpp ---- a/src/hotspot/cpu/loongarch/globalDefinitions_loongarch.hpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/cpu/loongarch/globalDefinitions_loongarch.hpp 2024-01-30 10:00:11.838098438 +0800 +diff --git a/src/hotspot/cpu/loongarch/globalDefinitions_loongarch.hpp b/src/hotspot/cpu/loongarch/globalDefinitions_loongarch.hpp +new file mode 100644 +index 0000000000..dc21d001cc +--- /dev/null ++++ b/src/hotspot/cpu/loongarch/globalDefinitions_loongarch.hpp @@ -0,0 +1,53 @@ +/* + * Copyright (c) 1999, 2013, Oracle and/or its affiliates. All rights reserved. @@ -14942,9 +15035,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h +#define THREAD_LOCAL_POLL + +#endif // CPU_LOONGARCH_GLOBALDEFINITIONS_LOONGARCH_HPP -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/globals_loongarch.hpp b/src/hotspot/cpu/loongarch/globals_loongarch.hpp ---- a/src/hotspot/cpu/loongarch/globals_loongarch.hpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/cpu/loongarch/globals_loongarch.hpp 2024-01-30 10:00:11.838098438 +0800 +diff --git a/src/hotspot/cpu/loongarch/globals_loongarch.hpp b/src/hotspot/cpu/loongarch/globals_loongarch.hpp +new file mode 100644 +index 0000000000..e6b758b554 +--- /dev/null ++++ b/src/hotspot/cpu/loongarch/globals_loongarch.hpp @@ -0,0 +1,109 @@ +/* + * Copyright (c) 2000, 2013, Oracle and/or its affiliates. All rights reserved. @@ -15055,9 +15150,109 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h + "Eliminate barriers for single active cpu") + +#endif // CPU_LOONGARCH_GLOBALS_LOONGARCH_HPP -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/icache_loongarch.cpp b/src/hotspot/cpu/loongarch/icache_loongarch.cpp ---- a/src/hotspot/cpu/loongarch/icache_loongarch.cpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/cpu/loongarch/icache_loongarch.cpp 2024-01-30 10:00:11.838098438 +0800 +diff --git a/src/hotspot/cpu/loongarch/icBuffer_loongarch.cpp b/src/hotspot/cpu/loongarch/icBuffer_loongarch.cpp +new file mode 100644 +index 0000000000..7b97694827 +--- /dev/null ++++ b/src/hotspot/cpu/loongarch/icBuffer_loongarch.cpp +@@ -0,0 +1,92 @@ ++/* ++ * Copyright (c) 1997, 2012, Oracle and/or its affiliates. All rights reserved. ++ * Copyright (c) 2015, 2021, Loongson Technology. All rights reserved. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ * ++ */ ++ ++#include "precompiled.hpp" ++#include "asm/macroAssembler.hpp" ++#include "asm/macroAssembler.inline.hpp" ++#include "code/icBuffer.hpp" ++#include "gc/shared/collectedHeap.inline.hpp" ++#include "interpreter/bytecodes.hpp" ++#include "memory/resourceArea.hpp" ++#include "nativeInst_loongarch.hpp" ++#include "oops/oop.inline.hpp" ++ ++#define T0 RT0 ++#define T1 RT1 ++#define T2 RT2 ++#define T3 RT3 ++#define T4 RT4 ++#define T5 RT5 ++#define T6 RT6 ++#define T7 RT7 ++#define T8 RT8 ++ ++int InlineCacheBuffer::ic_stub_code_size() { ++ return NativeMovConstReg::instruction_size + ++ NativeGeneralJump::instruction_size + ++ 1; ++ // so that code_end can be set in CodeBuffer ++ // 64bit 15 = 6 + 8 bytes + 1 byte ++ // 32bit 7 = 2 + 4 bytes + 1 byte ++} ++ ++ ++// we use T1 as cached oop(klass) now. this is the target of virtual call, ++// when reach here, the receiver in T0 ++// refer to shareRuntime_loongarch.cpp,gen_i2c2i_adapters ++void InlineCacheBuffer::assemble_ic_buffer_code(address code_begin, void* cached_value, ++ address entry_point) { ++ ResourceMark rm; ++ CodeBuffer code(code_begin, ic_stub_code_size()); ++ MacroAssembler* masm = new MacroAssembler(&code); ++ // note: even though the code contains an embedded oop, we do not need reloc info ++ // because ++ // (1) the oop is old (i.e., doesn't matter for scavenges) ++ // (2) these ICStubs are removed *before* a GC happens, so the roots disappear ++ // assert(cached_oop == NULL || cached_oop->is_perm(), "must be perm oop"); ++#define __ masm-> ++ __ patchable_li52(T1, (long)cached_value); ++ // TODO: confirm reloc ++ __ jmp(entry_point, relocInfo::runtime_call_type); ++ __ flush(); ++#undef __ ++} ++ ++ ++address InlineCacheBuffer::ic_buffer_entry_point(address code_begin) { ++ NativeMovConstReg* move = nativeMovConstReg_at(code_begin); // creation also verifies the object ++ NativeGeneralJump* jump = nativeGeneralJump_at(move->next_instruction_address()); ++ return jump->jump_destination(); ++} ++ ++ ++void* InlineCacheBuffer::ic_buffer_cached_value(address code_begin) { ++ // creation also verifies the object ++ NativeMovConstReg* move = nativeMovConstReg_at(code_begin); ++ // Verifies the jump ++ NativeGeneralJump* jump = nativeGeneralJump_at(move->next_instruction_address()); ++ void* o= (void*)move->data(); ++ return o; ++} +diff --git a/src/hotspot/cpu/loongarch/icache_loongarch.cpp b/src/hotspot/cpu/loongarch/icache_loongarch.cpp +new file mode 100644 +index 0000000000..1ae7e5376c +--- /dev/null ++++ b/src/hotspot/cpu/loongarch/icache_loongarch.cpp @@ -0,0 +1,42 @@ +/* + * Copyright (c) 1997, 2010, Oracle and/or its affiliates. All rights reserved. @@ -15101,9 +15296,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h + *flush_icache_stub = (ICache::flush_icache_stub_t)start; +#undef __ +} -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/icache_loongarch.hpp b/src/hotspot/cpu/loongarch/icache_loongarch.hpp ---- a/src/hotspot/cpu/loongarch/icache_loongarch.hpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/cpu/loongarch/icache_loongarch.hpp 2024-01-30 10:00:11.838098438 +0800 +diff --git a/src/hotspot/cpu/loongarch/icache_loongarch.hpp b/src/hotspot/cpu/loongarch/icache_loongarch.hpp +new file mode 100644 +index 0000000000..3a180549fc +--- /dev/null ++++ b/src/hotspot/cpu/loongarch/icache_loongarch.hpp @@ -0,0 +1,41 @@ +/* + * Copyright (c) 1997, 2010, Oracle and/or its affiliates. All rights reserved. @@ -15146,12 +15343,14 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h +}; + +#endif // CPU_LOONGARCH_ICACHE_LOONGARCH_HPP -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/icBuffer_loongarch.cpp b/src/hotspot/cpu/loongarch/icBuffer_loongarch.cpp ---- a/src/hotspot/cpu/loongarch/icBuffer_loongarch.cpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/cpu/loongarch/icBuffer_loongarch.cpp 2024-01-30 10:00:11.838098438 +0800 -@@ -0,0 +1,92 @@ +diff --git a/src/hotspot/cpu/loongarch/interp_masm_loongarch.hpp b/src/hotspot/cpu/loongarch/interp_masm_loongarch.hpp +new file mode 100644 +index 0000000000..53a06ba7fd +--- /dev/null ++++ b/src/hotspot/cpu/loongarch/interp_masm_loongarch.hpp +@@ -0,0 +1,281 @@ +/* -+ * Copyright (c) 1997, 2012, Oracle and/or its affiliates. All rights reserved. ++ * Copyright (c) 2003, 2013, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 2015, 2021, Loongson Technology. All rights reserved. + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. + * @@ -15175,76 +15374,267 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h + * + */ + -+#include "precompiled.hpp" ++#ifndef CPU_LOONGARCH_INTERP_MASM_LOONGARCH_64_HPP ++#define CPU_LOONGARCH_INTERP_MASM_LOONGARCH_64_HPP ++ ++#include "asm/assembler.hpp" +#include "asm/macroAssembler.hpp" +#include "asm/macroAssembler.inline.hpp" -+#include "code/icBuffer.hpp" -+#include "gc/shared/collectedHeap.inline.hpp" -+#include "interpreter/bytecodes.hpp" -+#include "memory/resourceArea.hpp" -+#include "nativeInst_loongarch.hpp" -+#include "oops/oop.inline.hpp" ++#include "interpreter/invocationCounter.hpp" ++#include "runtime/frame.hpp" + -+#define T0 RT0 -+#define T1 RT1 -+#define T2 RT2 -+#define T3 RT3 -+#define T4 RT4 -+#define T5 RT5 -+#define T6 RT6 -+#define T7 RT7 -+#define T8 RT8 ++// This file specializes the assember with interpreter-specific macros + -+int InlineCacheBuffer::ic_stub_code_size() { -+ return NativeMovConstReg::instruction_size + -+ NativeGeneralJump::instruction_size + -+ 1; -+ // so that code_end can be set in CodeBuffer -+ // 64bit 15 = 6 + 8 bytes + 1 byte -+ // 32bit 7 = 2 + 4 bytes + 1 byte -+} ++typedef ByteSize (*OffsetFunction)(uint); + ++class InterpreterMacroAssembler: public MacroAssembler { ++#ifndef CC_INTERP ++ private: + -+// we use T1 as cached oop(klass) now. this is the target of virtual call, -+// when reach here, the receiver in T0 -+// refer to shareRuntime_loongarch.cpp,gen_i2c2i_adapters -+void InlineCacheBuffer::assemble_ic_buffer_code(address code_begin, void* cached_value, -+ address entry_point) { -+ ResourceMark rm; -+ CodeBuffer code(code_begin, ic_stub_code_size()); -+ MacroAssembler* masm = new MacroAssembler(&code); -+ // note: even though the code contains an embedded oop, we do not need reloc info -+ // because -+ // (1) the oop is old (i.e., doesn't matter for scavenges) -+ // (2) these ICStubs are removed *before* a GC happens, so the roots disappear -+ // assert(cached_oop == NULL || cached_oop->is_perm(), "must be perm oop"); -+#define __ masm-> -+ __ patchable_li52(T1, (long)cached_value); -+ // TODO: confirm reloc -+ __ jmp(entry_point, relocInfo::runtime_call_type); -+ __ flush(); -+#undef __ -+} ++ Register _locals_register; // register that contains the pointer to the locals ++ Register _bcp_register; // register that contains the bcp + ++ protected: ++ // Interpreter specific version of call_VM_base ++ virtual void call_VM_leaf_base(address entry_point, ++ int number_of_arguments); + -+address InlineCacheBuffer::ic_buffer_entry_point(address code_begin) { -+ NativeMovConstReg* move = nativeMovConstReg_at(code_begin); // creation also verifies the object -+ NativeGeneralJump* jump = nativeGeneralJump_at(move->next_instruction_address()); -+ return jump->jump_destination(); -+} ++ virtual void call_VM_base(Register oop_result, ++ Register java_thread, ++ Register last_java_sp, ++ address entry_point, ++ int number_of_arguments, ++ bool check_exceptions); + ++ // base routine for all dispatches ++ void dispatch_base(TosState state, address* table, bool verifyoop = true, bool generate_poll = false); ++#endif // CC_INTERP + -+void* InlineCacheBuffer::ic_buffer_cached_value(address code_begin) { -+ // creation also verifies the object -+ NativeMovConstReg* move = nativeMovConstReg_at(code_begin); -+ // Verifies the jump -+ NativeGeneralJump* jump = nativeGeneralJump_at(move->next_instruction_address()); -+ void* o= (void*)move->data(); -+ return o; -+} -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/interp_masm_loongarch_64.cpp b/src/hotspot/cpu/loongarch/interp_masm_loongarch_64.cpp ---- a/src/hotspot/cpu/loongarch/interp_masm_loongarch_64.cpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/cpu/loongarch/interp_masm_loongarch_64.cpp 2024-01-30 10:00:11.838098438 +0800 ++ public: ++ void jump_to_entry(address entry); ++ // narrow int return value ++ void narrow(Register result); ++ ++ InterpreterMacroAssembler(CodeBuffer* code) : MacroAssembler(code), _locals_register(LVP), _bcp_register(BCP) {} ++ ++ void get_2_byte_integer_at_bcp(Register reg, Register tmp, int offset); ++ void get_4_byte_integer_at_bcp(Register reg, int offset); ++ ++ virtual void check_and_handle_popframe(Register java_thread); ++ virtual void check_and_handle_earlyret(Register java_thread); ++ ++ void load_earlyret_value(TosState state); ++ ++#ifdef CC_INTERP ++ void save_bcp() { /* not needed in c++ interpreter and harmless */ } ++ void restore_bcp() { /* not needed in c++ interpreter and harmless */ } ++ ++ // Helpers for runtime call arguments/results ++ void get_method(Register reg); ++ ++#else ++ ++ // Interpreter-specific registers ++ void save_bcp() { ++ st_d(BCP, FP, frame::interpreter_frame_bcp_offset * wordSize); ++ } ++ ++ void restore_bcp() { ++ ld_d(BCP, FP, frame::interpreter_frame_bcp_offset * wordSize); ++ } ++ ++ void restore_locals() { ++ ld_d(LVP, FP, frame::interpreter_frame_locals_offset * wordSize); ++ } ++ ++ // Helpers for runtime call arguments/results ++ void get_method(Register reg) { ++ ld_d(reg, FP, frame::interpreter_frame_method_offset * wordSize); ++ } ++ ++ void get_const(Register reg){ ++ get_method(reg); ++ ld_d(reg, reg, in_bytes(Method::const_offset())); ++ } ++ ++ void get_constant_pool(Register reg) { ++ get_const(reg); ++ ld_d(reg, reg, in_bytes(ConstMethod::constants_offset())); ++ } ++ ++ void get_constant_pool_cache(Register reg) { ++ get_constant_pool(reg); ++ ld_d(reg, reg, ConstantPool::cache_offset_in_bytes()); ++ } ++ ++ void get_cpool_and_tags(Register cpool, Register tags) { ++ get_constant_pool(cpool); ++ ld_d(tags, cpool, ConstantPool::tags_offset_in_bytes()); ++ } ++ ++ void get_unsigned_2_byte_index_at_bcp(Register reg, int bcp_offset); ++ void get_cache_and_index_at_bcp(Register cache, Register index, int bcp_offset, size_t index_size = sizeof(u2)); ++ void get_cache_and_index_and_bytecode_at_bcp(Register cache, Register index, Register bytecode, int byte_no, int bcp_offset, size_t index_size = sizeof(u2)); ++ void get_cache_entry_pointer_at_bcp(Register cache, Register tmp, int bcp_offset, size_t index_size = sizeof(u2)); ++ void get_cache_index_at_bcp(Register index, int bcp_offset, size_t index_size = sizeof(u2)); ++ void get_method_counters(Register method, Register mcs, Label& skip); ++ ++ // load cpool->resolved_references(index); ++ void load_resolved_reference_at_index(Register result, Register index, Register tmp); ++ ++ // load cpool->resolved_klass_at(index) ++ void load_resolved_klass_at_index(Register cpool, // the constant pool (corrupted on return) ++ Register index, // the constant pool index (corrupted on return) ++ Register klass); // contains the Klass on return ++ ++ void pop_ptr( Register r = FSR); ++ void pop_i( Register r = FSR); ++ void pop_l( Register r = FSR); ++ void pop_f(FloatRegister r = FSF); ++ void pop_d(FloatRegister r = FSF); ++ ++ void push_ptr( Register r = FSR); ++ void push_i( Register r = FSR); ++ void push_l( Register r = FSR); ++ void push_f(FloatRegister r = FSF); ++ void push_d(FloatRegister r = FSF); ++ ++ void pop(Register r ) { ((MacroAssembler*)this)->pop(r); } ++ ++ void push(Register r ) { ((MacroAssembler*)this)->push(r); } ++ ++ void pop(TosState state); // transition vtos -> state ++ void push(TosState state); // transition state -> vtos ++ ++ void empty_expression_stack() { ++ ld_d(SP, FP, frame::interpreter_frame_monitor_block_top_offset * wordSize); ++ // NULL last_sp until next java call ++ st_d(R0, FP, frame::interpreter_frame_last_sp_offset * wordSize); ++ } ++ ++ // Super call_VM calls - correspond to MacroAssembler::call_VM(_leaf) calls ++ void load_ptr(int n, Register val); ++ void store_ptr(int n, Register val); ++ ++ // Generate a subtype check: branch to ok_is_subtype if sub_klass is ++ // a subtype of super_klass. ++ //void gen_subtype_check( Register sub_klass, Label &ok_is_subtype ); ++ void gen_subtype_check( Register Rsup_klass, Register sub_klass, Label &ok_is_subtype ); ++ ++ // Dispatching ++ void dispatch_prolog(TosState state, int step = 0); ++ void dispatch_epilog(TosState state, int step = 0); ++ void dispatch_only(TosState state, bool generate_poll = false); ++ void dispatch_only_normal(TosState state); ++ void dispatch_only_noverify(TosState state); ++ void dispatch_next(TosState state, int step = 0, bool generate_poll = false); ++ void dispatch_via (TosState state, address* table); ++ ++ // jump to an invoked target ++ void prepare_to_jump_from_interpreted(); ++ void jump_from_interpreted(Register method, Register temp); ++ ++ ++ // Returning from interpreted functions ++ // ++ // Removes the current activation (incl. unlocking of monitors) ++ // and sets up the return address. This code is also used for ++ // exception unwindwing. In that case, we do not want to throw ++ // IllegalMonitorStateExceptions, since that might get us into an ++ // infinite rethrow exception loop. ++ // Additionally this code is used for popFrame and earlyReturn. ++ // In popFrame case we want to skip throwing an exception, ++ // installing an exception, and notifying jvmdi. ++ // In earlyReturn case we only want to skip throwing an exception ++ // and installing an exception. ++ void remove_activation(TosState state, Register ret_addr, ++ bool throw_monitor_exception = true, ++ bool install_monitor_exception = true, ++ bool notify_jvmdi = true); ++#endif // CC_INTERP ++ ++ // Object locking ++ void lock_object (Register lock_reg); ++ void unlock_object(Register lock_reg); ++ ++#ifndef CC_INTERP ++ ++ // Interpreter profiling operations ++ void set_method_data_pointer_for_bcp(); ++ void test_method_data_pointer(Register mdp, Label& zero_continue); ++ void verify_method_data_pointer(); ++ ++ void set_mdp_data_at(Register mdp_in, int constant, Register value); ++ void increment_mdp_data_at(Address data, bool decrement = false); ++ void increment_mdp_data_at(Register mdp_in, int constant, ++ bool decrement = false); ++ void increment_mdp_data_at(Register mdp_in, Register reg, int constant, ++ bool decrement = false); ++ void increment_mask_and_jump(Address counter_addr, ++ int increment, int mask, ++ Register scratch, bool preloaded, ++ Condition cond, Label* where); ++ void set_mdp_flag_at(Register mdp_in, int flag_constant); ++ void test_mdp_data_at(Register mdp_in, int offset, Register value, ++ Register test_value_out, ++ Label& not_equal_continue); ++ ++ void record_klass_in_profile(Register receiver, Register mdp, ++ Register reg2, bool is_virtual_call); ++ void record_klass_in_profile_helper(Register receiver, Register mdp, ++ Register reg2, int start_row, ++ Label& done, bool is_virtual_call); ++ ++ void record_item_in_profile_helper(Register item, Register mdp, ++ Register reg2, int start_row, Label& done, int total_rows, ++ OffsetFunction item_offset_fn, OffsetFunction item_count_offset_fn, ++ int non_profiled_offset); ++ void update_mdp_by_offset(Register mdp_in, int offset_of_offset); ++ void update_mdp_by_offset(Register mdp_in, Register reg, int offset_of_disp); ++ void update_mdp_by_constant(Register mdp_in, int constant); ++ void update_mdp_for_ret(Register return_bci); ++ ++ void profile_taken_branch(Register mdp, Register bumped_count); ++ void profile_not_taken_branch(Register mdp); ++ void profile_call(Register mdp); ++ void profile_final_call(Register mdp); ++ void profile_virtual_call(Register receiver, Register mdp, ++ Register scratch2, ++ bool receiver_can_be_null = false); ++ void profile_called_method(Register method, Register mdp, Register reg2) NOT_JVMCI_RETURN; ++ void profile_ret(Register return_bci, Register mdp); ++ void profile_null_seen(Register mdp); ++ void profile_typecheck(Register mdp, Register klass, Register scratch); ++ void profile_typecheck_failed(Register mdp); ++ void profile_switch_default(Register mdp); ++ void profile_switch_case(Register index_in_scratch, Register mdp, ++ Register scratch2); ++ ++ // Debugging ++ // only if +VerifyOops && state == atos ++ void verify_oop(Register reg, TosState state = atos); ++ // only if +VerifyFPU && (state == ftos || state == dtos) ++ void verify_FPU(int stack_depth, TosState state = ftos); ++ ++ void profile_obj_type(Register obj, const Address& mdo_addr); ++ void profile_arguments_type(Register mdp, Register callee, Register tmp, bool is_virtual); ++ void profile_return_type(Register mdp, Register ret, Register tmp); ++ void profile_parameters_type(Register mdp, Register tmp1, Register tmp2); ++#endif // !CC_INTERP ++ ++ typedef enum { NotifyJVMTI, SkipNotifyJVMTI } NotifyMethodExitMode; ++ ++ // support for jvmti/dtrace ++ void notify_method_entry(); ++ void notify_method_exit(TosState state, NotifyMethodExitMode mode); ++}; ++ ++#endif // CPU_LOONGARCH_INTERP_MASM_LOONGARCH_64_HPP +diff --git a/src/hotspot/cpu/loongarch/interp_masm_loongarch_64.cpp b/src/hotspot/cpu/loongarch/interp_masm_loongarch_64.cpp +new file mode 100644 +index 0000000000..c533a57652 +--- /dev/null ++++ b/src/hotspot/cpu/loongarch/interp_masm_loongarch_64.cpp @@ -0,0 +1,2043 @@ +/* + * Copyright (c) 2003, 2013, Oracle and/or its affiliates. All rights reserved. @@ -17289,13 +17679,15 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h + unimplemented(); + } +} -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/interp_masm_loongarch.hpp b/src/hotspot/cpu/loongarch/interp_masm_loongarch.hpp ---- a/src/hotspot/cpu/loongarch/interp_masm_loongarch.hpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/cpu/loongarch/interp_masm_loongarch.hpp 2024-01-30 10:00:11.838098438 +0800 -@@ -0,0 +1,281 @@ +diff --git a/src/hotspot/cpu/loongarch/interpreterRT_loongarch.hpp b/src/hotspot/cpu/loongarch/interpreterRT_loongarch.hpp +new file mode 100644 +index 0000000000..d53d951a16 +--- /dev/null ++++ b/src/hotspot/cpu/loongarch/interpreterRT_loongarch.hpp +@@ -0,0 +1,62 @@ +/* -+ * Copyright (c) 2003, 2013, Oracle and/or its affiliates. All rights reserved. -+ * Copyright (c) 2015, 2021, Loongson Technology. All rights reserved. ++ * Copyright (c) 1998, 2010, Oracle and/or its affiliates. All rights reserved. ++ * Copyright (c) 2015, 2022, Loongson Technology. All rights reserved. + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. + * + * This code is free software; you can redistribute it and/or modify it @@ -17318,265 +17710,48 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h + * + */ + -+#ifndef CPU_LOONGARCH_INTERP_MASM_LOONGARCH_64_HPP -+#define CPU_LOONGARCH_INTERP_MASM_LOONGARCH_64_HPP -+ -+#include "asm/assembler.hpp" -+#include "asm/macroAssembler.hpp" -+#include "asm/macroAssembler.inline.hpp" -+#include "interpreter/invocationCounter.hpp" -+#include "runtime/frame.hpp" ++#ifndef CPU_LOONGARCH_INTERPRETERRT_LOONGARCH_HPP ++#define CPU_LOONGARCH_INTERPRETERRT_LOONGARCH_HPP + -+// This file specializes the assember with interpreter-specific macros ++// This is included in the middle of class Interpreter. ++// Do not include files here. + -+typedef ByteSize (*OffsetFunction)(uint); ++// native method calls + -+class InterpreterMacroAssembler: public MacroAssembler { -+#ifndef CC_INTERP ++class SignatureHandlerGenerator: public NativeSignatureIterator { + private: ++ MacroAssembler* _masm; ++ unsigned int _num_fp_args; ++ unsigned int _num_int_args; ++ int _stack_offset; + -+ Register _locals_register; // register that contains the pointer to the locals -+ Register _bcp_register; // register that contains the bcp -+ -+ protected: -+ // Interpreter specific version of call_VM_base -+ virtual void call_VM_leaf_base(address entry_point, -+ int number_of_arguments); -+ -+ virtual void call_VM_base(Register oop_result, -+ Register java_thread, -+ Register last_java_sp, -+ address entry_point, -+ int number_of_arguments, -+ bool check_exceptions); -+ -+ // base routine for all dispatches -+ void dispatch_base(TosState state, address* table, bool verifyoop = true, bool generate_poll = false); -+#endif // CC_INTERP ++ void move(int from_offset, int to_offset); ++ void box(int from_offset, int to_offset); ++ void pass_int(); ++ void pass_long(); ++ void pass_object(); ++ void pass_float(); ++ void pass_double(); + + public: -+ void jump_to_entry(address entry); -+ // narrow int return value -+ void narrow(Register result); -+ -+ InterpreterMacroAssembler(CodeBuffer* code) : MacroAssembler(code), _locals_register(LVP), _bcp_register(BCP) {} -+ -+ void get_2_byte_integer_at_bcp(Register reg, Register tmp, int offset); -+ void get_4_byte_integer_at_bcp(Register reg, int offset); -+ -+ virtual void check_and_handle_popframe(Register java_thread); -+ virtual void check_and_handle_earlyret(Register java_thread); -+ -+ void load_earlyret_value(TosState state); -+ -+#ifdef CC_INTERP -+ void save_bcp() { /* not needed in c++ interpreter and harmless */ } -+ void restore_bcp() { /* not needed in c++ interpreter and harmless */ } -+ -+ // Helpers for runtime call arguments/results -+ void get_method(Register reg); -+ -+#else -+ -+ // Interpreter-specific registers -+ void save_bcp() { -+ st_d(BCP, FP, frame::interpreter_frame_bcp_offset * wordSize); -+ } -+ -+ void restore_bcp() { -+ ld_d(BCP, FP, frame::interpreter_frame_bcp_offset * wordSize); -+ } -+ -+ void restore_locals() { -+ ld_d(LVP, FP, frame::interpreter_frame_locals_offset * wordSize); -+ } -+ -+ // Helpers for runtime call arguments/results -+ void get_method(Register reg) { -+ ld_d(reg, FP, frame::interpreter_frame_method_offset * wordSize); -+ } -+ -+ void get_const(Register reg){ -+ get_method(reg); -+ ld_d(reg, reg, in_bytes(Method::const_offset())); -+ } -+ -+ void get_constant_pool(Register reg) { -+ get_const(reg); -+ ld_d(reg, reg, in_bytes(ConstMethod::constants_offset())); -+ } -+ -+ void get_constant_pool_cache(Register reg) { -+ get_constant_pool(reg); -+ ld_d(reg, reg, ConstantPool::cache_offset_in_bytes()); -+ } -+ -+ void get_cpool_and_tags(Register cpool, Register tags) { -+ get_constant_pool(cpool); -+ ld_d(tags, cpool, ConstantPool::tags_offset_in_bytes()); -+ } -+ -+ void get_unsigned_2_byte_index_at_bcp(Register reg, int bcp_offset); -+ void get_cache_and_index_at_bcp(Register cache, Register index, int bcp_offset, size_t index_size = sizeof(u2)); -+ void get_cache_and_index_and_bytecode_at_bcp(Register cache, Register index, Register bytecode, int byte_no, int bcp_offset, size_t index_size = sizeof(u2)); -+ void get_cache_entry_pointer_at_bcp(Register cache, Register tmp, int bcp_offset, size_t index_size = sizeof(u2)); -+ void get_cache_index_at_bcp(Register index, int bcp_offset, size_t index_size = sizeof(u2)); -+ void get_method_counters(Register method, Register mcs, Label& skip); -+ -+ // load cpool->resolved_references(index); -+ void load_resolved_reference_at_index(Register result, Register index, Register tmp); -+ -+ // load cpool->resolved_klass_at(index) -+ void load_resolved_klass_at_index(Register cpool, // the constant pool (corrupted on return) -+ Register index, // the constant pool index (corrupted on return) -+ Register klass); // contains the Klass on return -+ -+ void pop_ptr( Register r = FSR); -+ void pop_i( Register r = FSR); -+ void pop_l( Register r = FSR); -+ void pop_f(FloatRegister r = FSF); -+ void pop_d(FloatRegister r = FSF); -+ -+ void push_ptr( Register r = FSR); -+ void push_i( Register r = FSR); -+ void push_l( Register r = FSR); -+ void push_f(FloatRegister r = FSF); -+ void push_d(FloatRegister r = FSF); -+ -+ void pop(Register r ) { ((MacroAssembler*)this)->pop(r); } -+ -+ void push(Register r ) { ((MacroAssembler*)this)->push(r); } -+ -+ void pop(TosState state); // transition vtos -> state -+ void push(TosState state); // transition state -> vtos -+ -+ void empty_expression_stack() { -+ ld_d(SP, FP, frame::interpreter_frame_monitor_block_top_offset * wordSize); -+ // NULL last_sp until next java call -+ st_d(R0, FP, frame::interpreter_frame_last_sp_offset * wordSize); -+ } -+ -+ // Super call_VM calls - correspond to MacroAssembler::call_VM(_leaf) calls -+ void load_ptr(int n, Register val); -+ void store_ptr(int n, Register val); -+ -+ // Generate a subtype check: branch to ok_is_subtype if sub_klass is -+ // a subtype of super_klass. -+ //void gen_subtype_check( Register sub_klass, Label &ok_is_subtype ); -+ void gen_subtype_check( Register Rsup_klass, Register sub_klass, Label &ok_is_subtype ); -+ -+ // Dispatching -+ void dispatch_prolog(TosState state, int step = 0); -+ void dispatch_epilog(TosState state, int step = 0); -+ void dispatch_only(TosState state, bool generate_poll = false); -+ void dispatch_only_normal(TosState state); -+ void dispatch_only_noverify(TosState state); -+ void dispatch_next(TosState state, int step = 0, bool generate_poll = false); -+ void dispatch_via (TosState state, address* table); -+ -+ // jump to an invoked target -+ void prepare_to_jump_from_interpreted(); -+ void jump_from_interpreted(Register method, Register temp); -+ -+ -+ // Returning from interpreted functions -+ // -+ // Removes the current activation (incl. unlocking of monitors) -+ // and sets up the return address. This code is also used for -+ // exception unwindwing. In that case, we do not want to throw -+ // IllegalMonitorStateExceptions, since that might get us into an -+ // infinite rethrow exception loop. -+ // Additionally this code is used for popFrame and earlyReturn. -+ // In popFrame case we want to skip throwing an exception, -+ // installing an exception, and notifying jvmdi. -+ // In earlyReturn case we only want to skip throwing an exception -+ // and installing an exception. -+ void remove_activation(TosState state, Register ret_addr, -+ bool throw_monitor_exception = true, -+ bool install_monitor_exception = true, -+ bool notify_jvmdi = true); -+#endif // CC_INTERP -+ -+ // Object locking -+ void lock_object (Register lock_reg); -+ void unlock_object(Register lock_reg); -+ -+#ifndef CC_INTERP -+ -+ // Interpreter profiling operations -+ void set_method_data_pointer_for_bcp(); -+ void test_method_data_pointer(Register mdp, Label& zero_continue); -+ void verify_method_data_pointer(); -+ -+ void set_mdp_data_at(Register mdp_in, int constant, Register value); -+ void increment_mdp_data_at(Address data, bool decrement = false); -+ void increment_mdp_data_at(Register mdp_in, int constant, -+ bool decrement = false); -+ void increment_mdp_data_at(Register mdp_in, Register reg, int constant, -+ bool decrement = false); -+ void increment_mask_and_jump(Address counter_addr, -+ int increment, int mask, -+ Register scratch, bool preloaded, -+ Condition cond, Label* where); -+ void set_mdp_flag_at(Register mdp_in, int flag_constant); -+ void test_mdp_data_at(Register mdp_in, int offset, Register value, -+ Register test_value_out, -+ Label& not_equal_continue); -+ -+ void record_klass_in_profile(Register receiver, Register mdp, -+ Register reg2, bool is_virtual_call); -+ void record_klass_in_profile_helper(Register receiver, Register mdp, -+ Register reg2, int start_row, -+ Label& done, bool is_virtual_call); -+ -+ void record_item_in_profile_helper(Register item, Register mdp, -+ Register reg2, int start_row, Label& done, int total_rows, -+ OffsetFunction item_offset_fn, OffsetFunction item_count_offset_fn, -+ int non_profiled_offset); -+ void update_mdp_by_offset(Register mdp_in, int offset_of_offset); -+ void update_mdp_by_offset(Register mdp_in, Register reg, int offset_of_disp); -+ void update_mdp_by_constant(Register mdp_in, int constant); -+ void update_mdp_for_ret(Register return_bci); -+ -+ void profile_taken_branch(Register mdp, Register bumped_count); -+ void profile_not_taken_branch(Register mdp); -+ void profile_call(Register mdp); -+ void profile_final_call(Register mdp); -+ void profile_virtual_call(Register receiver, Register mdp, -+ Register scratch2, -+ bool receiver_can_be_null = false); -+ void profile_called_method(Register method, Register mdp, Register reg2) NOT_JVMCI_RETURN; -+ void profile_ret(Register return_bci, Register mdp); -+ void profile_null_seen(Register mdp); -+ void profile_typecheck(Register mdp, Register klass, Register scratch); -+ void profile_typecheck_failed(Register mdp); -+ void profile_switch_default(Register mdp); -+ void profile_switch_case(Register index_in_scratch, Register mdp, -+ Register scratch2); -+ -+ // Debugging -+ // only if +VerifyOops && state == atos -+ void verify_oop(Register reg, TosState state = atos); -+ // only if +VerifyFPU && (state == ftos || state == dtos) -+ void verify_FPU(int stack_depth, TosState state = ftos); -+ -+ void profile_obj_type(Register obj, const Address& mdo_addr); -+ void profile_arguments_type(Register mdp, Register callee, Register tmp, bool is_virtual); -+ void profile_return_type(Register mdp, Register ret, Register tmp); -+ void profile_parameters_type(Register mdp, Register tmp1, Register tmp2); -+#endif // !CC_INTERP ++ // Creation ++ SignatureHandlerGenerator(const methodHandle& method, CodeBuffer* buffer); + -+ typedef enum { NotifyJVMTI, SkipNotifyJVMTI } NotifyMethodExitMode; ++ // Code generation ++ void generate(uint64_t fingerprint); + -+ // support for jvmti/dtrace -+ void notify_method_entry(); -+ void notify_method_exit(TosState state, NotifyMethodExitMode mode); ++ // Code generation support ++ static Register from(); ++ static Register to(); ++ static Register temp(); +}; + -+#endif // CPU_LOONGARCH_INTERP_MASM_LOONGARCH_64_HPP -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/interpreterRT_loongarch_64.cpp b/src/hotspot/cpu/loongarch/interpreterRT_loongarch_64.cpp ---- a/src/hotspot/cpu/loongarch/interpreterRT_loongarch_64.cpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/cpu/loongarch/interpreterRT_loongarch_64.cpp 2024-01-30 10:00:11.838098438 +0800 ++#endif // CPU_LOONGARCH_INTERPRETERRT_LOONGARCH_HPP +diff --git a/src/hotspot/cpu/loongarch/interpreterRT_loongarch_64.cpp b/src/hotspot/cpu/loongarch/interpreterRT_loongarch_64.cpp +new file mode 100644 +index 0000000000..e2f31997b7 +--- /dev/null ++++ b/src/hotspot/cpu/loongarch/interpreterRT_loongarch_64.cpp @@ -0,0 +1,273 @@ +/* + * Copyright (c) 2003, 2012, Oracle and/or its affiliates. All rights reserved. @@ -17603,323 +17778,259 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h + * + */ + -+#include "precompiled.hpp" -+#include "interpreter/interpreter.hpp" -+#include "interpreter/interpreterRuntime.hpp" -+#include "memory/allocation.inline.hpp" -+#include "memory/universe.hpp" -+#include "oops/method.hpp" -+#include "oops/oop.inline.hpp" -+#include "runtime/handles.inline.hpp" -+#include "runtime/icache.hpp" -+#include "runtime/interfaceSupport.inline.hpp" -+#include "runtime/signature.hpp" -+ -+#define __ _masm-> -+ -+#define T0 RT0 -+#define T1 RT1 -+#define T2 RT2 -+#define T3 RT3 -+#define T4 RT4 -+#define T5 RT5 -+#define T6 RT6 -+#define T7 RT7 -+#define T8 RT8 -+ -+// Implementation of SignatureHandlerGenerator -+InterpreterRuntime::SignatureHandlerGenerator::SignatureHandlerGenerator( -+ const methodHandle& method, CodeBuffer* buffer) : NativeSignatureIterator(method) { -+ _masm = new MacroAssembler(buffer); -+ _num_int_args = (method->is_static() ? 1 : 0); -+ _num_fp_args = 0; -+ _stack_offset = 0; -+} -+ -+void InterpreterRuntime::SignatureHandlerGenerator::move(int from_offset, int to_offset) { -+ __ ld_d(temp(), from(), Interpreter::local_offset_in_bytes(from_offset)); -+ __ st_d(temp(), to(), to_offset * longSize); -+} -+ -+void InterpreterRuntime::SignatureHandlerGenerator::box(int from_offset, int to_offset) { -+ __ addi_d(temp(), from(),Interpreter::local_offset_in_bytes(from_offset) ); -+ __ ld_w(AT, from(), Interpreter::local_offset_in_bytes(from_offset) ); -+ -+ __ maskeqz(temp(), temp(), AT); -+ __ st_w(temp(), to(), to_offset * wordSize); -+} -+ -+void InterpreterRuntime::SignatureHandlerGenerator::generate(uint64_t fingerprint) { -+ // generate code to handle arguments -+ iterate(fingerprint); -+ // return result handler -+ __ li(V0, AbstractInterpreter::result_handler(method()->result_type())); -+ // return -+ __ jr(RA); -+ -+ __ flush(); -+} -+ -+void InterpreterRuntime::SignatureHandlerGenerator::pass_int() { -+ if (_num_int_args < Argument::n_register_parameters - 1) { -+ __ ld_w(as_Register(++_num_int_args + A0->encoding()), from(), Interpreter::local_offset_in_bytes(offset())); -+ } else { -+ __ ld_w(AT, from(), Interpreter::local_offset_in_bytes(offset())); -+ __ st_w(AT, to(), _stack_offset); -+ _stack_offset += wordSize; -+ } -+} -+ -+// the jvm specifies that long type takes 2 stack spaces, so in do_long(), _offset += 2. -+void InterpreterRuntime::SignatureHandlerGenerator::pass_long() { -+ if (_num_int_args < Argument::n_register_parameters - 1) { -+ __ ld_d(as_Register(++_num_int_args + A0->encoding()), from(), Interpreter::local_offset_in_bytes(offset() + 1)); -+ } else { -+ __ ld_d(AT, from(), Interpreter::local_offset_in_bytes(offset() + 1)); -+ __ st_d(AT, to(), _stack_offset); -+ _stack_offset += wordSize; -+ } -+} -+ -+void InterpreterRuntime::SignatureHandlerGenerator::pass_object() { -+ if (_num_int_args < Argument::n_register_parameters - 1) { -+ Register reg = as_Register(++_num_int_args + A0->encoding()); -+ if (_num_int_args == 1) { -+ assert(offset() == 0, "argument register 1 can only be (non-null) receiver"); -+ __ addi_d(reg, from(), Interpreter::local_offset_in_bytes(offset())); -+ } else { -+ __ ld_d(reg, from(), Interpreter::local_offset_in_bytes(offset())); -+ __ addi_d(AT, from(), Interpreter::local_offset_in_bytes(offset())); -+ __ maskeqz(reg, AT, reg); -+ } -+ } else { -+ __ ld_d(temp(), from(), Interpreter::local_offset_in_bytes(offset())); -+ __ addi_d(AT, from(), Interpreter::local_offset_in_bytes(offset())); -+ __ maskeqz(temp(), AT, temp()); -+ __ st_d(temp(), to(), _stack_offset); -+ _stack_offset += wordSize; -+ } -+} -+ -+void InterpreterRuntime::SignatureHandlerGenerator::pass_float() { -+ if (_num_fp_args < Argument::n_float_register_parameters) { -+ __ fld_s(as_FloatRegister(_num_fp_args++), from(), Interpreter::local_offset_in_bytes(offset())); -+ } else if (_num_int_args < Argument::n_register_parameters - 1) { -+ __ ld_w(as_Register(++_num_int_args + A0->encoding()), from(), Interpreter::local_offset_in_bytes(offset())); -+ } else { -+ __ ld_w(AT, from(), Interpreter::local_offset_in_bytes(offset())); -+ __ st_w(AT, to(), _stack_offset); -+ _stack_offset += wordSize; -+ } -+} -+ -+// the jvm specifies that double type takes 2 stack spaces, so in do_double(), _offset += 2. -+void InterpreterRuntime::SignatureHandlerGenerator::pass_double() { -+ if (_num_fp_args < Argument::n_float_register_parameters) { -+ __ fld_d(as_FloatRegister(_num_fp_args++), from(), Interpreter::local_offset_in_bytes(offset() + 1)); -+ } else if (_num_int_args < Argument::n_register_parameters - 1) { -+ __ ld_d(as_Register(++_num_int_args + A0->encoding()), from(), Interpreter::local_offset_in_bytes(offset() + 1)); -+ } else { -+ __ ld_d(AT, from(), Interpreter::local_offset_in_bytes(offset() + 1)); -+ __ st_d(AT, to(), _stack_offset); -+ _stack_offset += wordSize; -+ } -+} -+ -+ -+Register InterpreterRuntime::SignatureHandlerGenerator::from() { return LVP; } -+Register InterpreterRuntime::SignatureHandlerGenerator::to() { return SP; } -+Register InterpreterRuntime::SignatureHandlerGenerator::temp() { return T8; } -+ -+// Implementation of SignatureHandlerLibrary -+ -+void SignatureHandlerLibrary::pd_set_handler(address handler) {} -+ -+ -+class SlowSignatureHandler -+ : public NativeSignatureIterator { -+ private: -+ address _from; -+ intptr_t* _to; -+ intptr_t* _int_args; -+ intptr_t* _fp_args; -+ intptr_t* _fp_identifiers; -+ unsigned int _num_int_args; -+ unsigned int _num_fp_args; -+ -+ virtual void pass_int() -+ { -+ jint from_obj = *(jint *)(_from+Interpreter::local_offset_in_bytes(0)); -+ _from -= Interpreter::stackElementSize; -+ -+ if (_num_int_args < Argument::n_register_parameters - 1) { -+ *_int_args++ = from_obj; -+ _num_int_args++; -+ } else { -+ *_to++ = from_obj; -+ } -+ } -+ -+ virtual void pass_long() -+ { -+ intptr_t from_obj = *(intptr_t*)(_from+Interpreter::local_offset_in_bytes(1)); -+ _from -= 2 * Interpreter::stackElementSize; -+ -+ if (_num_int_args < Argument::n_register_parameters - 1) { -+ *_int_args++ = from_obj; -+ _num_int_args++; -+ } else { -+ *_to++ = from_obj; -+ } -+ } -+ -+ virtual void pass_object() -+ { -+ intptr_t *from_addr = (intptr_t*)(_from + Interpreter::local_offset_in_bytes(0)); -+ _from -= Interpreter::stackElementSize; -+ -+ if (_num_int_args < Argument::n_register_parameters - 1) { -+ *_int_args++ = (*from_addr == 0) ? NULL : (intptr_t) from_addr; -+ _num_int_args++; -+ } else { -+ *_to++ = (*from_addr == 0) ? NULL : (intptr_t) from_addr; -+ } -+ } -+ -+ virtual void pass_float() -+ { -+ jint from_obj = *(jint *)(_from+Interpreter::local_offset_in_bytes(0)); -+ _from -= Interpreter::stackElementSize; -+ -+ if (_num_fp_args < Argument::n_float_register_parameters) { -+ *_fp_args++ = from_obj; -+ _num_fp_args++; -+ } else if (_num_int_args < Argument::n_register_parameters - 1) { -+ *_int_args++ = from_obj; -+ _num_int_args++; -+ } else { -+ *_to++ = from_obj; -+ } -+ } -+ -+ virtual void pass_double() -+ { -+ intptr_t from_obj = *(intptr_t*)(_from+Interpreter::local_offset_in_bytes(1)); -+ _from -= 2*Interpreter::stackElementSize; -+ -+ if (_num_fp_args < Argument::n_float_register_parameters) { -+ *_fp_args++ = from_obj; -+ *_fp_identifiers |= (1 << _num_fp_args); // mark as double -+ _num_fp_args++; -+ } else if (_num_int_args < Argument::n_register_parameters - 1) { -+ *_int_args++ = from_obj; -+ _num_int_args++; -+ } else { -+ *_to++ = from_obj; -+ } -+ } -+ -+ public: -+ SlowSignatureHandler(methodHandle method, address from, intptr_t* to) -+ : NativeSignatureIterator(method) -+ { -+ _from = from; -+ _to = to; -+ -+ // see TemplateInterpreterGenerator::generate_slow_signature_handler() -+ _int_args = to - (method->is_static() ? 15 : 16); -+ _fp_args = to - 8; -+ _fp_identifiers = to - 9; -+ *(int*) _fp_identifiers = 0; -+ _num_int_args = (method->is_static() ? 1 : 0); -+ _num_fp_args = 0; -+ } -+}; -+ -+ -+IRT_ENTRY(address, -+ InterpreterRuntime::slow_signature_handler(JavaThread* thread, -+ Method* method, -+ intptr_t* from, -+ intptr_t* to)) -+ methodHandle m(thread, (Method*)method); -+ assert(m->is_native(), "sanity check"); -+ -+ // handle arguments -+ SlowSignatureHandler(m, (address)from, to).iterate(UCONST64(-1)); -+ -+ // return result handler -+ return Interpreter::result_handler(m->result_type()); -+IRT_END -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/interpreterRT_loongarch.hpp b/src/hotspot/cpu/loongarch/interpreterRT_loongarch.hpp ---- a/src/hotspot/cpu/loongarch/interpreterRT_loongarch.hpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/cpu/loongarch/interpreterRT_loongarch.hpp 2024-01-30 10:00:11.838098438 +0800 -@@ -0,0 +1,62 @@ -+/* -+ * Copyright (c) 1998, 2010, Oracle and/or its affiliates. All rights reserved. -+ * Copyright (c) 2015, 2022, Loongson Technology. All rights reserved. -+ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. -+ * -+ * This code is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 only, as -+ * published by the Free Software Foundation. -+ * -+ * This code is distributed in the hope that it will be useful, but WITHOUT -+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -+ * version 2 for more details (a copy is included in the LICENSE file that -+ * accompanied this code). -+ * -+ * You should have received a copy of the GNU General Public License version -+ * 2 along with this work; if not, write to the Free Software Foundation, -+ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. -+ * -+ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA -+ * or visit www.oracle.com if you need additional information or have any -+ * questions. -+ * -+ */ -+ -+#ifndef CPU_LOONGARCH_INTERPRETERRT_LOONGARCH_HPP -+#define CPU_LOONGARCH_INTERPRETERRT_LOONGARCH_HPP ++#include "precompiled.hpp" ++#include "interpreter/interpreter.hpp" ++#include "interpreter/interpreterRuntime.hpp" ++#include "memory/allocation.inline.hpp" ++#include "memory/universe.hpp" ++#include "oops/method.hpp" ++#include "oops/oop.inline.hpp" ++#include "runtime/handles.inline.hpp" ++#include "runtime/icache.hpp" ++#include "runtime/interfaceSupport.inline.hpp" ++#include "runtime/signature.hpp" + -+// This is included in the middle of class Interpreter. -+// Do not include files here. ++#define __ _masm-> + -+// native method calls ++#define T0 RT0 ++#define T1 RT1 ++#define T2 RT2 ++#define T3 RT3 ++#define T4 RT4 ++#define T5 RT5 ++#define T6 RT6 ++#define T7 RT7 ++#define T8 RT8 + -+class SignatureHandlerGenerator: public NativeSignatureIterator { ++// Implementation of SignatureHandlerGenerator ++InterpreterRuntime::SignatureHandlerGenerator::SignatureHandlerGenerator( ++ const methodHandle& method, CodeBuffer* buffer) : NativeSignatureIterator(method) { ++ _masm = new MacroAssembler(buffer); ++ _num_int_args = (method->is_static() ? 1 : 0); ++ _num_fp_args = 0; ++ _stack_offset = 0; ++} ++ ++void InterpreterRuntime::SignatureHandlerGenerator::move(int from_offset, int to_offset) { ++ __ ld_d(temp(), from(), Interpreter::local_offset_in_bytes(from_offset)); ++ __ st_d(temp(), to(), to_offset * longSize); ++} ++ ++void InterpreterRuntime::SignatureHandlerGenerator::box(int from_offset, int to_offset) { ++ __ addi_d(temp(), from(),Interpreter::local_offset_in_bytes(from_offset) ); ++ __ ld_w(AT, from(), Interpreter::local_offset_in_bytes(from_offset) ); ++ ++ __ maskeqz(temp(), temp(), AT); ++ __ st_w(temp(), to(), to_offset * wordSize); ++} ++ ++void InterpreterRuntime::SignatureHandlerGenerator::generate(uint64_t fingerprint) { ++ // generate code to handle arguments ++ iterate(fingerprint); ++ // return result handler ++ __ li(V0, AbstractInterpreter::result_handler(method()->result_type())); ++ // return ++ __ jr(RA); ++ ++ __ flush(); ++} ++ ++void InterpreterRuntime::SignatureHandlerGenerator::pass_int() { ++ if (_num_int_args < Argument::n_register_parameters - 1) { ++ __ ld_w(as_Register(++_num_int_args + A0->encoding()), from(), Interpreter::local_offset_in_bytes(offset())); ++ } else { ++ __ ld_w(AT, from(), Interpreter::local_offset_in_bytes(offset())); ++ __ st_w(AT, to(), _stack_offset); ++ _stack_offset += wordSize; ++ } ++} ++ ++// the jvm specifies that long type takes 2 stack spaces, so in do_long(), _offset += 2. ++void InterpreterRuntime::SignatureHandlerGenerator::pass_long() { ++ if (_num_int_args < Argument::n_register_parameters - 1) { ++ __ ld_d(as_Register(++_num_int_args + A0->encoding()), from(), Interpreter::local_offset_in_bytes(offset() + 1)); ++ } else { ++ __ ld_d(AT, from(), Interpreter::local_offset_in_bytes(offset() + 1)); ++ __ st_d(AT, to(), _stack_offset); ++ _stack_offset += wordSize; ++ } ++} ++ ++void InterpreterRuntime::SignatureHandlerGenerator::pass_object() { ++ if (_num_int_args < Argument::n_register_parameters - 1) { ++ Register reg = as_Register(++_num_int_args + A0->encoding()); ++ if (_num_int_args == 1) { ++ assert(offset() == 0, "argument register 1 can only be (non-null) receiver"); ++ __ addi_d(reg, from(), Interpreter::local_offset_in_bytes(offset())); ++ } else { ++ __ ld_d(reg, from(), Interpreter::local_offset_in_bytes(offset())); ++ __ addi_d(AT, from(), Interpreter::local_offset_in_bytes(offset())); ++ __ maskeqz(reg, AT, reg); ++ } ++ } else { ++ __ ld_d(temp(), from(), Interpreter::local_offset_in_bytes(offset())); ++ __ addi_d(AT, from(), Interpreter::local_offset_in_bytes(offset())); ++ __ maskeqz(temp(), AT, temp()); ++ __ st_d(temp(), to(), _stack_offset); ++ _stack_offset += wordSize; ++ } ++} ++ ++void InterpreterRuntime::SignatureHandlerGenerator::pass_float() { ++ if (_num_fp_args < Argument::n_float_register_parameters) { ++ __ fld_s(as_FloatRegister(_num_fp_args++), from(), Interpreter::local_offset_in_bytes(offset())); ++ } else if (_num_int_args < Argument::n_register_parameters - 1) { ++ __ ld_w(as_Register(++_num_int_args + A0->encoding()), from(), Interpreter::local_offset_in_bytes(offset())); ++ } else { ++ __ ld_w(AT, from(), Interpreter::local_offset_in_bytes(offset())); ++ __ st_w(AT, to(), _stack_offset); ++ _stack_offset += wordSize; ++ } ++} ++ ++// the jvm specifies that double type takes 2 stack spaces, so in do_double(), _offset += 2. ++void InterpreterRuntime::SignatureHandlerGenerator::pass_double() { ++ if (_num_fp_args < Argument::n_float_register_parameters) { ++ __ fld_d(as_FloatRegister(_num_fp_args++), from(), Interpreter::local_offset_in_bytes(offset() + 1)); ++ } else if (_num_int_args < Argument::n_register_parameters - 1) { ++ __ ld_d(as_Register(++_num_int_args + A0->encoding()), from(), Interpreter::local_offset_in_bytes(offset() + 1)); ++ } else { ++ __ ld_d(AT, from(), Interpreter::local_offset_in_bytes(offset() + 1)); ++ __ st_d(AT, to(), _stack_offset); ++ _stack_offset += wordSize; ++ } ++} ++ ++ ++Register InterpreterRuntime::SignatureHandlerGenerator::from() { return LVP; } ++Register InterpreterRuntime::SignatureHandlerGenerator::to() { return SP; } ++Register InterpreterRuntime::SignatureHandlerGenerator::temp() { return T8; } ++ ++// Implementation of SignatureHandlerLibrary ++ ++void SignatureHandlerLibrary::pd_set_handler(address handler) {} ++ ++ ++class SlowSignatureHandler ++ : public NativeSignatureIterator { + private: -+ MacroAssembler* _masm; -+ unsigned int _num_fp_args; ++ address _from; ++ intptr_t* _to; ++ intptr_t* _int_args; ++ intptr_t* _fp_args; ++ intptr_t* _fp_identifiers; + unsigned int _num_int_args; -+ int _stack_offset; ++ unsigned int _num_fp_args; + -+ void move(int from_offset, int to_offset); -+ void box(int from_offset, int to_offset); -+ void pass_int(); -+ void pass_long(); -+ void pass_object(); -+ void pass_float(); -+ void pass_double(); ++ virtual void pass_int() ++ { ++ jint from_obj = *(jint *)(_from+Interpreter::local_offset_in_bytes(0)); ++ _from -= Interpreter::stackElementSize; + -+ public: -+ // Creation -+ SignatureHandlerGenerator(const methodHandle& method, CodeBuffer* buffer); ++ if (_num_int_args < Argument::n_register_parameters - 1) { ++ *_int_args++ = from_obj; ++ _num_int_args++; ++ } else { ++ *_to++ = from_obj; ++ } ++ } + -+ // Code generation -+ void generate(uint64_t fingerprint); ++ virtual void pass_long() ++ { ++ intptr_t from_obj = *(intptr_t*)(_from+Interpreter::local_offset_in_bytes(1)); ++ _from -= 2 * Interpreter::stackElementSize; + -+ // Code generation support -+ static Register from(); -+ static Register to(); -+ static Register temp(); ++ if (_num_int_args < Argument::n_register_parameters - 1) { ++ *_int_args++ = from_obj; ++ _num_int_args++; ++ } else { ++ *_to++ = from_obj; ++ } ++ } ++ ++ virtual void pass_object() ++ { ++ intptr_t *from_addr = (intptr_t*)(_from + Interpreter::local_offset_in_bytes(0)); ++ _from -= Interpreter::stackElementSize; ++ ++ if (_num_int_args < Argument::n_register_parameters - 1) { ++ *_int_args++ = (*from_addr == 0) ? NULL : (intptr_t) from_addr; ++ _num_int_args++; ++ } else { ++ *_to++ = (*from_addr == 0) ? NULL : (intptr_t) from_addr; ++ } ++ } ++ ++ virtual void pass_float() ++ { ++ jint from_obj = *(jint *)(_from+Interpreter::local_offset_in_bytes(0)); ++ _from -= Interpreter::stackElementSize; ++ ++ if (_num_fp_args < Argument::n_float_register_parameters) { ++ *_fp_args++ = from_obj; ++ _num_fp_args++; ++ } else if (_num_int_args < Argument::n_register_parameters - 1) { ++ *_int_args++ = from_obj; ++ _num_int_args++; ++ } else { ++ *_to++ = from_obj; ++ } ++ } ++ ++ virtual void pass_double() ++ { ++ intptr_t from_obj = *(intptr_t*)(_from+Interpreter::local_offset_in_bytes(1)); ++ _from -= 2*Interpreter::stackElementSize; ++ ++ if (_num_fp_args < Argument::n_float_register_parameters) { ++ *_fp_args++ = from_obj; ++ *_fp_identifiers |= (1 << _num_fp_args); // mark as double ++ _num_fp_args++; ++ } else if (_num_int_args < Argument::n_register_parameters - 1) { ++ *_int_args++ = from_obj; ++ _num_int_args++; ++ } else { ++ *_to++ = from_obj; ++ } ++ } ++ ++ public: ++ SlowSignatureHandler(methodHandle method, address from, intptr_t* to) ++ : NativeSignatureIterator(method) ++ { ++ _from = from; ++ _to = to; ++ ++ // see TemplateInterpreterGenerator::generate_slow_signature_handler() ++ _int_args = to - (method->is_static() ? 15 : 16); ++ _fp_args = to - 8; ++ _fp_identifiers = to - 9; ++ *(int*) _fp_identifiers = 0; ++ _num_int_args = (method->is_static() ? 1 : 0); ++ _num_fp_args = 0; ++ } +}; + -+#endif // CPU_LOONGARCH_INTERPRETERRT_LOONGARCH_HPP -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/javaFrameAnchor_loongarch.hpp b/src/hotspot/cpu/loongarch/javaFrameAnchor_loongarch.hpp ---- a/src/hotspot/cpu/loongarch/javaFrameAnchor_loongarch.hpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/cpu/loongarch/javaFrameAnchor_loongarch.hpp 2024-01-30 10:00:11.838098438 +0800 ++ ++IRT_ENTRY(address, ++ InterpreterRuntime::slow_signature_handler(JavaThread* thread, ++ Method* method, ++ intptr_t* from, ++ intptr_t* to)) ++ methodHandle m(thread, (Method*)method); ++ assert(m->is_native(), "sanity check"); ++ ++ // handle arguments ++ SlowSignatureHandler(m, (address)from, to).iterate(UCONST64(-1)); ++ ++ // return result handler ++ return Interpreter::result_handler(m->result_type()); ++IRT_END +diff --git a/src/hotspot/cpu/loongarch/javaFrameAnchor_loongarch.hpp b/src/hotspot/cpu/loongarch/javaFrameAnchor_loongarch.hpp +new file mode 100644 +index 0000000000..6814fa44a0 +--- /dev/null ++++ b/src/hotspot/cpu/loongarch/javaFrameAnchor_loongarch.hpp @@ -0,0 +1,87 @@ +/* + * Copyright (c) 2002, 2010, Oracle and/or its affiliates. All rights reserved. @@ -18008,9 +18119,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h + void set_last_Java_fp(intptr_t* fp) { _last_Java_fp = fp; } + +#endif // CPU_LOONGARCH_JAVAFRAMEANCHOR_LOONGARCH_HPP -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/jniFastGetField_loongarch_64.cpp b/src/hotspot/cpu/loongarch/jniFastGetField_loongarch_64.cpp ---- a/src/hotspot/cpu/loongarch/jniFastGetField_loongarch_64.cpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/cpu/loongarch/jniFastGetField_loongarch_64.cpp 2024-01-30 10:00:11.838098438 +0800 +diff --git a/src/hotspot/cpu/loongarch/jniFastGetField_loongarch_64.cpp b/src/hotspot/cpu/loongarch/jniFastGetField_loongarch_64.cpp +new file mode 100644 +index 0000000000..dbcdb7a6a4 +--- /dev/null ++++ b/src/hotspot/cpu/loongarch/jniFastGetField_loongarch_64.cpp @@ -0,0 +1,166 @@ +/* + * Copyright (c) 2004, 2010, Oracle and/or its affiliates. All rights reserved. @@ -18178,9 +18291,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h +address JNI_FastGetField::generate_fast_get_double_field() { + return generate_fast_get_int_field0(T_DOUBLE); +} -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/jniTypes_loongarch.hpp b/src/hotspot/cpu/loongarch/jniTypes_loongarch.hpp ---- a/src/hotspot/cpu/loongarch/jniTypes_loongarch.hpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/cpu/loongarch/jniTypes_loongarch.hpp 2024-01-30 10:00:11.838098438 +0800 +diff --git a/src/hotspot/cpu/loongarch/jniTypes_loongarch.hpp b/src/hotspot/cpu/loongarch/jniTypes_loongarch.hpp +new file mode 100644 +index 0000000000..b281f86372 +--- /dev/null ++++ b/src/hotspot/cpu/loongarch/jniTypes_loongarch.hpp @@ -0,0 +1,144 @@ +/* + * Copyright (c) 1998, 2010, Oracle and/or its affiliates. All rights reserved. @@ -18326,9 +18441,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h +}; + +#endif // CPU_LOONGARCH_JNITYPES_LOONGARCH_HPP -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/jvmciCodeInstaller_loongarch.cpp b/src/hotspot/cpu/loongarch/jvmciCodeInstaller_loongarch.cpp ---- a/src/hotspot/cpu/loongarch/jvmciCodeInstaller_loongarch.cpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/cpu/loongarch/jvmciCodeInstaller_loongarch.cpp 2024-01-30 10:00:11.838098438 +0800 +diff --git a/src/hotspot/cpu/loongarch/jvmciCodeInstaller_loongarch.cpp b/src/hotspot/cpu/loongarch/jvmciCodeInstaller_loongarch.cpp +new file mode 100644 +index 0000000000..ea481c7fa6 +--- /dev/null ++++ b/src/hotspot/cpu/loongarch/jvmciCodeInstaller_loongarch.cpp @@ -0,0 +1,199 @@ +/* + * Copyright (c) 2015, 2022, Oracle and/or its affiliates. All rights reserved. @@ -18529,9 +18646,42 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h +bool CodeInstaller::is_general_purpose_reg(VMReg hotspotRegister) { + return !hotspotRegister->is_FloatRegister(); +} -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/loongarch_64.ad b/src/hotspot/cpu/loongarch/loongarch_64.ad ---- a/src/hotspot/cpu/loongarch/loongarch_64.ad 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/cpu/loongarch/loongarch_64.ad 2024-01-30 10:00:11.841431732 +0800 +diff --git a/src/hotspot/cpu/loongarch/loongarch.ad b/src/hotspot/cpu/loongarch/loongarch.ad +new file mode 100644 +index 0000000000..80dff0c762 +--- /dev/null ++++ b/src/hotspot/cpu/loongarch/loongarch.ad +@@ -0,0 +1,25 @@ ++// ++// Copyright (c) 2011, 2012, Oracle and/or its affiliates. All rights reserved. ++// Copyright (c) 2015, 2021, Loongson Technology. All rights reserved. ++// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++// ++// This code is free software; you can redistribute it and/or modify it ++// under the terms of the GNU General Public License version 2 only, as ++// published by the Free Software Foundation. ++// ++// This code is distributed in the hope that it will be useful, but WITHOUT ++// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++// version 2 for more details (a copy is included in the LICENSE file that ++// accompanied this code). ++// ++// You should have received a copy of the GNU General Public License version ++// 2 along with this work; if not, write to the Free Software Foundation, ++// Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++// ++// Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++// or visit www.oracle.com if you need additional information or have any ++// questions. ++// ++// ++ +diff --git a/src/hotspot/cpu/loongarch/loongarch_64.ad b/src/hotspot/cpu/loongarch/loongarch_64.ad +new file mode 100644 +index 0000000000..cc3824a402 +--- /dev/null ++++ b/src/hotspot/cpu/loongarch/loongarch_64.ad @@ -0,0 +1,13917 @@ +// +// Copyright (c) 2003, 2013, Oracle and/or its affiliates. All rights reserved. @@ -32450,38 +32600,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h +// These must follow all instruction definitions as they use the names +// defined in the instructions definitions. + -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/loongarch.ad b/src/hotspot/cpu/loongarch/loongarch.ad ---- a/src/hotspot/cpu/loongarch/loongarch.ad 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/cpu/loongarch/loongarch.ad 2024-01-30 10:00:11.838098438 +0800 -@@ -0,0 +1,25 @@ -+// -+// Copyright (c) 2011, 2012, Oracle and/or its affiliates. All rights reserved. -+// Copyright (c) 2015, 2021, Loongson Technology. All rights reserved. -+// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. -+// -+// This code is free software; you can redistribute it and/or modify it -+// under the terms of the GNU General Public License version 2 only, as -+// published by the Free Software Foundation. -+// -+// This code is distributed in the hope that it will be useful, but WITHOUT -+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -+// version 2 for more details (a copy is included in the LICENSE file that -+// accompanied this code). -+// -+// You should have received a copy of the GNU General Public License version -+// 2 along with this work; if not, write to the Free Software Foundation, -+// Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. -+// -+// Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA -+// or visit www.oracle.com if you need additional information or have any -+// questions. -+// -+// -+ -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/macroAssembler_loongarch.cpp b/src/hotspot/cpu/loongarch/macroAssembler_loongarch.cpp ---- a/src/hotspot/cpu/loongarch/macroAssembler_loongarch.cpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/cpu/loongarch/macroAssembler_loongarch.cpp 2024-01-30 10:00:11.841431732 +0800 +diff --git a/src/hotspot/cpu/loongarch/macroAssembler_loongarch.cpp b/src/hotspot/cpu/loongarch/macroAssembler_loongarch.cpp +new file mode 100644 +index 0000000000..9720fd176d +--- /dev/null ++++ b/src/hotspot/cpu/loongarch/macroAssembler_loongarch.cpp @@ -0,0 +1,4567 @@ +/* + * Copyright (c) 1997, 2014, Oracle and/or its affiliates. All rights reserved. @@ -37050,9 +37173,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h + bind(L_end); +} + -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/macroAssembler_loongarch.hpp b/src/hotspot/cpu/loongarch/macroAssembler_loongarch.hpp ---- a/src/hotspot/cpu/loongarch/macroAssembler_loongarch.hpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/cpu/loongarch/macroAssembler_loongarch.hpp 2024-01-30 10:00:11.841431732 +0800 +diff --git a/src/hotspot/cpu/loongarch/macroAssembler_loongarch.hpp b/src/hotspot/cpu/loongarch/macroAssembler_loongarch.hpp +new file mode 100644 +index 0000000000..1f96557543 +--- /dev/null ++++ b/src/hotspot/cpu/loongarch/macroAssembler_loongarch.hpp @@ -0,0 +1,825 @@ +/* + * Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved. @@ -37879,9 +38004,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h +}; + +#endif // CPU_LOONGARCH_MACROASSEMBLER_LOONGARCH_HPP -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/macroAssembler_loongarch.inline.hpp b/src/hotspot/cpu/loongarch/macroAssembler_loongarch.inline.hpp ---- a/src/hotspot/cpu/loongarch/macroAssembler_loongarch.inline.hpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/cpu/loongarch/macroAssembler_loongarch.inline.hpp 2024-01-30 10:00:11.841431732 +0800 +diff --git a/src/hotspot/cpu/loongarch/macroAssembler_loongarch.inline.hpp b/src/hotspot/cpu/loongarch/macroAssembler_loongarch.inline.hpp +new file mode 100644 +index 0000000000..49302590c3 +--- /dev/null ++++ b/src/hotspot/cpu/loongarch/macroAssembler_loongarch.inline.hpp @@ -0,0 +1,34 @@ +/* + * Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved. @@ -37917,9 +38044,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h +#include "code/codeCache.hpp" + +#endif // CPU_LOONGARCH_MACROASSEMBLER_LOONGARCH_INLINE_HPP -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/macroAssembler_loongarch_trig.cpp b/src/hotspot/cpu/loongarch/macroAssembler_loongarch_trig.cpp ---- a/src/hotspot/cpu/loongarch/macroAssembler_loongarch_trig.cpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/cpu/loongarch/macroAssembler_loongarch_trig.cpp 2024-01-30 10:00:11.841431732 +0800 +diff --git a/src/hotspot/cpu/loongarch/macroAssembler_loongarch_trig.cpp b/src/hotspot/cpu/loongarch/macroAssembler_loongarch_trig.cpp +new file mode 100644 +index 0000000000..3ed4c36651 +--- /dev/null ++++ b/src/hotspot/cpu/loongarch/macroAssembler_loongarch_trig.cpp @@ -0,0 +1,1625 @@ +/* Copyright (c) 2018, 2020, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 2018, Cavium. All rights reserved. (By BELLSOFT) @@ -39546,9 +39675,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h + bind(DONE); + jr(RA); +} -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/methodHandles_loongarch.cpp b/src/hotspot/cpu/loongarch/methodHandles_loongarch.cpp ---- a/src/hotspot/cpu/loongarch/methodHandles_loongarch.cpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/cpu/loongarch/methodHandles_loongarch.cpp 2024-01-30 10:00:11.841431732 +0800 +diff --git a/src/hotspot/cpu/loongarch/methodHandles_loongarch.cpp b/src/hotspot/cpu/loongarch/methodHandles_loongarch.cpp +new file mode 100644 +index 0000000000..e517dcd415 +--- /dev/null ++++ b/src/hotspot/cpu/loongarch/methodHandles_loongarch.cpp @@ -0,0 +1,564 @@ +/* + * Copyright (c) 1997, 2014, Oracle and/or its affiliates. All rights reserved. @@ -40114,9 +40245,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h +void MethodHandles::trace_method_handle(MacroAssembler* _masm, const char* adaptername) { +} +#endif //PRODUCT -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/methodHandles_loongarch.hpp b/src/hotspot/cpu/loongarch/methodHandles_loongarch.hpp ---- a/src/hotspot/cpu/loongarch/methodHandles_loongarch.hpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/cpu/loongarch/methodHandles_loongarch.hpp 2024-01-30 10:00:11.841431732 +0800 +diff --git a/src/hotspot/cpu/loongarch/methodHandles_loongarch.hpp b/src/hotspot/cpu/loongarch/methodHandles_loongarch.hpp +new file mode 100644 +index 0000000000..f84337424b +--- /dev/null ++++ b/src/hotspot/cpu/loongarch/methodHandles_loongarch.hpp @@ -0,0 +1,62 @@ +/* + * Copyright (c) 2010, 2012, Oracle and/or its affiliates. All rights reserved. @@ -40180,9 +40313,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h + // Should be in sharedRuntime, not here. + return R3; + } -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/nativeInst_loongarch.cpp b/src/hotspot/cpu/loongarch/nativeInst_loongarch.cpp ---- a/src/hotspot/cpu/loongarch/nativeInst_loongarch.cpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/cpu/loongarch/nativeInst_loongarch.cpp 2024-01-30 10:00:11.841431732 +0800 +diff --git a/src/hotspot/cpu/loongarch/nativeInst_loongarch.cpp b/src/hotspot/cpu/loongarch/nativeInst_loongarch.cpp +new file mode 100644 +index 0000000000..9234befae3 +--- /dev/null ++++ b/src/hotspot/cpu/loongarch/nativeInst_loongarch.cpp @@ -0,0 +1,511 @@ +/* + * Copyright (c) 1997, 2014, Oracle and/or its affiliates. All rights reserved. @@ -40695,9 +40830,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h + return Assembler::high(insn_word(), 10) == Assembler::ld_w_op && + Assembler::low(insn_word(), 5) == AT->encoding(); +} -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/nativeInst_loongarch.hpp b/src/hotspot/cpu/loongarch/nativeInst_loongarch.hpp ---- a/src/hotspot/cpu/loongarch/nativeInst_loongarch.hpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/cpu/loongarch/nativeInst_loongarch.hpp 2024-01-30 10:00:11.841431732 +0800 +diff --git a/src/hotspot/cpu/loongarch/nativeInst_loongarch.hpp b/src/hotspot/cpu/loongarch/nativeInst_loongarch.hpp +new file mode 100644 +index 0000000000..a6e9d4dd3c +--- /dev/null ++++ b/src/hotspot/cpu/loongarch/nativeInst_loongarch.hpp @@ -0,0 +1,528 @@ +/* + * Copyright (c) 1997, 2011, Oracle and/or its affiliates. All rights reserved. @@ -41227,9 +41364,64 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h +}; + +#endif // CPU_LOONGARCH_NATIVEINST_LOONGARCH_HPP -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/register_definitions_loongarch.cpp b/src/hotspot/cpu/loongarch/register_definitions_loongarch.cpp ---- a/src/hotspot/cpu/loongarch/register_definitions_loongarch.cpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/cpu/loongarch/register_definitions_loongarch.cpp 2024-01-30 10:00:11.841431732 +0800 +diff --git a/src/hotspot/cpu/loongarch/registerMap_loongarch.hpp b/src/hotspot/cpu/loongarch/registerMap_loongarch.hpp +new file mode 100644 +index 0000000000..e9f0fc280d +--- /dev/null ++++ b/src/hotspot/cpu/loongarch/registerMap_loongarch.hpp +@@ -0,0 +1,47 @@ ++/* ++ * Copyright (c) 1998, 2010, Oracle and/or its affiliates. All rights reserved. ++ * Copyright (c) 2015, 2016, Loongson Technology. All rights reserved. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ * ++ */ ++ ++#ifndef CPU_LOONGARCH_REGISTERMAP_LOONGARCH_HPP ++#define CPU_LOONGARCH_REGISTERMAP_LOONGARCH_HPP ++ ++// machine-dependent implemention for register maps ++ friend class frame; ++ ++ private: ++#ifndef CORE ++ // This is the hook for finding a register in an "well-known" location, ++ // such as a register block of a predetermined format. ++ // Since there is none, we just return NULL. ++ // See registerMap_sparc.hpp for an example of grabbing registers ++ // from register save areas of a standard layout. ++ address pd_location(VMReg reg) const {return NULL;} ++#endif ++ ++ // no PD state to clear or copy: ++ void pd_clear() {} ++ void pd_initialize() {} ++ void pd_initialize_from(const RegisterMap* map) {} ++ ++#endif // CPU_LOONGARCH_REGISTERMAP_LOONGARCH_HPP +diff --git a/src/hotspot/cpu/loongarch/register_definitions_loongarch.cpp b/src/hotspot/cpu/loongarch/register_definitions_loongarch.cpp +new file mode 100644 +index 0000000000..58f40b747c +--- /dev/null ++++ b/src/hotspot/cpu/loongarch/register_definitions_loongarch.cpp @@ -0,0 +1,103 @@ +/* + * Copyright (c) 2002, 2013, Oracle and/or its affiliates. All rights reserved. @@ -41334,9 +41526,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h +REGISTER_DEFINITION(FloatRegister, f29); +REGISTER_DEFINITION(FloatRegister, f30); +REGISTER_DEFINITION(FloatRegister, f31); -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/register_loongarch.cpp b/src/hotspot/cpu/loongarch/register_loongarch.cpp ---- a/src/hotspot/cpu/loongarch/register_loongarch.cpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/cpu/loongarch/register_loongarch.cpp 2024-01-30 10:00:11.841431732 +0800 +diff --git a/src/hotspot/cpu/loongarch/register_loongarch.cpp b/src/hotspot/cpu/loongarch/register_loongarch.cpp +new file mode 100644 +index 0000000000..54d90167a5 +--- /dev/null ++++ b/src/hotspot/cpu/loongarch/register_loongarch.cpp @@ -0,0 +1,59 @@ +/* + * Copyright (c) 2000, 2012, Oracle and/or its affiliates. All rights reserved. @@ -41397,9 +41591,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h + }; + return is_valid() ? names[encoding()] : "fccnoreg"; +} -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/register_loongarch.hpp b/src/hotspot/cpu/loongarch/register_loongarch.hpp ---- a/src/hotspot/cpu/loongarch/register_loongarch.hpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/cpu/loongarch/register_loongarch.hpp 2024-01-30 10:00:11.841431732 +0800 +diff --git a/src/hotspot/cpu/loongarch/register_loongarch.hpp b/src/hotspot/cpu/loongarch/register_loongarch.hpp +new file mode 100644 +index 0000000000..da876a5083 +--- /dev/null ++++ b/src/hotspot/cpu/loongarch/register_loongarch.hpp @@ -0,0 +1,495 @@ +/* + * Copyright (c) 2000, 2012, Oracle and/or its affiliates. All rights reserved. @@ -41896,60 +42092,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h +typedef AbstractRegSet RegSet; + +#endif //CPU_LOONGARCH_REGISTER_LOONGARCH_HPP -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/registerMap_loongarch.hpp b/src/hotspot/cpu/loongarch/registerMap_loongarch.hpp ---- a/src/hotspot/cpu/loongarch/registerMap_loongarch.hpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/cpu/loongarch/registerMap_loongarch.hpp 2024-01-30 10:00:11.841431732 +0800 -@@ -0,0 +1,47 @@ -+/* -+ * Copyright (c) 1998, 2010, Oracle and/or its affiliates. All rights reserved. -+ * Copyright (c) 2015, 2016, Loongson Technology. All rights reserved. -+ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. -+ * -+ * This code is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 only, as -+ * published by the Free Software Foundation. -+ * -+ * This code is distributed in the hope that it will be useful, but WITHOUT -+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -+ * version 2 for more details (a copy is included in the LICENSE file that -+ * accompanied this code). -+ * -+ * You should have received a copy of the GNU General Public License version -+ * 2 along with this work; if not, write to the Free Software Foundation, -+ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. -+ * -+ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA -+ * or visit www.oracle.com if you need additional information or have any -+ * questions. -+ * -+ */ -+ -+#ifndef CPU_LOONGARCH_REGISTERMAP_LOONGARCH_HPP -+#define CPU_LOONGARCH_REGISTERMAP_LOONGARCH_HPP -+ -+// machine-dependent implemention for register maps -+ friend class frame; -+ -+ private: -+#ifndef CORE -+ // This is the hook for finding a register in an "well-known" location, -+ // such as a register block of a predetermined format. -+ // Since there is none, we just return NULL. -+ // See registerMap_sparc.hpp for an example of grabbing registers -+ // from register save areas of a standard layout. -+ address pd_location(VMReg reg) const {return NULL;} -+#endif -+ -+ // no PD state to clear or copy: -+ void pd_clear() {} -+ void pd_initialize() {} -+ void pd_initialize_from(const RegisterMap* map) {} -+ -+#endif // CPU_LOONGARCH_REGISTERMAP_LOONGARCH_HPP -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/relocInfo_loongarch.cpp b/src/hotspot/cpu/loongarch/relocInfo_loongarch.cpp ---- a/src/hotspot/cpu/loongarch/relocInfo_loongarch.cpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/cpu/loongarch/relocInfo_loongarch.cpp 2024-01-30 10:00:11.841431732 +0800 +diff --git a/src/hotspot/cpu/loongarch/relocInfo_loongarch.cpp b/src/hotspot/cpu/loongarch/relocInfo_loongarch.cpp +new file mode 100644 +index 0000000000..1caba43699 +--- /dev/null ++++ b/src/hotspot/cpu/loongarch/relocInfo_loongarch.cpp @@ -0,0 +1,132 @@ +/* + * Copyright (c) 1998, 2013, Oracle and/or its affiliates. All rights reserved. @@ -42083,9 +42230,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h + +void metadata_Relocation::pd_fix_value(address x) { +} -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/relocInfo_loongarch.hpp b/src/hotspot/cpu/loongarch/relocInfo_loongarch.hpp ---- a/src/hotspot/cpu/loongarch/relocInfo_loongarch.hpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/cpu/loongarch/relocInfo_loongarch.hpp 2024-01-30 10:00:11.841431732 +0800 +diff --git a/src/hotspot/cpu/loongarch/relocInfo_loongarch.hpp b/src/hotspot/cpu/loongarch/relocInfo_loongarch.hpp +new file mode 100644 +index 0000000000..c85ca4963f +--- /dev/null ++++ b/src/hotspot/cpu/loongarch/relocInfo_loongarch.hpp @@ -0,0 +1,44 @@ +/* + * Copyright (c) 1997, 2010, Oracle and/or its affiliates. All rights reserved. @@ -42131,9 +42280,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h + static bool mustIterateImmediateOopsInCode() { return false; } + +#endif // CPU_LOONGARCH_RELOCINFO_LOONGARCH_HPP -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/runtime_loongarch_64.cpp b/src/hotspot/cpu/loongarch/runtime_loongarch_64.cpp ---- a/src/hotspot/cpu/loongarch/runtime_loongarch_64.cpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/cpu/loongarch/runtime_loongarch_64.cpp 2024-01-30 10:00:11.841431732 +0800 +diff --git a/src/hotspot/cpu/loongarch/runtime_loongarch_64.cpp b/src/hotspot/cpu/loongarch/runtime_loongarch_64.cpp +new file mode 100644 +index 0000000000..334c783b37 +--- /dev/null ++++ b/src/hotspot/cpu/loongarch/runtime_loongarch_64.cpp @@ -0,0 +1,191 @@ +/* + * Copyright (c) 2003, 2010, Oracle and/or its affiliates. All rights reserved. @@ -42326,9 +42477,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h + masm->flush(); + _exception_blob = ExceptionBlob::create(&buffer, oop_maps, framesize); +} -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/sharedRuntime_loongarch_64.cpp b/src/hotspot/cpu/loongarch/sharedRuntime_loongarch_64.cpp ---- a/src/hotspot/cpu/loongarch/sharedRuntime_loongarch_64.cpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/cpu/loongarch/sharedRuntime_loongarch_64.cpp 2024-01-30 10:00:11.841431732 +0800 +diff --git a/src/hotspot/cpu/loongarch/sharedRuntime_loongarch_64.cpp b/src/hotspot/cpu/loongarch/sharedRuntime_loongarch_64.cpp +new file mode 100644 +index 0000000000..bc91ee005e +--- /dev/null ++++ b/src/hotspot/cpu/loongarch/sharedRuntime_loongarch_64.cpp @@ -0,0 +1,3621 @@ +/* + * Copyright (c) 2003, 2013, Oracle and/or its affiliates. All rights reserved. @@ -45951,9 +46104,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h +} + +extern "C" int SpinPause() {return 0;} -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/stubGenerator_loongarch_64.cpp b/src/hotspot/cpu/loongarch/stubGenerator_loongarch_64.cpp ---- a/src/hotspot/cpu/loongarch/stubGenerator_loongarch_64.cpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/cpu/loongarch/stubGenerator_loongarch_64.cpp 2024-01-30 10:00:11.841431732 +0800 +diff --git a/src/hotspot/cpu/loongarch/stubGenerator_loongarch_64.cpp b/src/hotspot/cpu/loongarch/stubGenerator_loongarch_64.cpp +new file mode 100644 +index 0000000000..7f73863b2e +--- /dev/null ++++ b/src/hotspot/cpu/loongarch/stubGenerator_loongarch_64.cpp @@ -0,0 +1,4804 @@ +/* + * Copyright (c) 2003, 2013, Oracle and/or its affiliates. All rights reserved. @@ -50759,9 +50914,84 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h +void StubGenerator_generate(CodeBuffer* code, bool all) { + StubGenerator g(code, all); +} -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/stubRoutines_loongarch_64.cpp b/src/hotspot/cpu/loongarch/stubRoutines_loongarch_64.cpp ---- a/src/hotspot/cpu/loongarch/stubRoutines_loongarch_64.cpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/cpu/loongarch/stubRoutines_loongarch_64.cpp 2024-01-30 10:00:11.841431732 +0800 +diff --git a/src/hotspot/cpu/loongarch/stubRoutines_loongarch.hpp b/src/hotspot/cpu/loongarch/stubRoutines_loongarch.hpp +new file mode 100644 +index 0000000000..0ab07e1e9e +--- /dev/null ++++ b/src/hotspot/cpu/loongarch/stubRoutines_loongarch.hpp +@@ -0,0 +1,67 @@ ++/* ++ * Copyright (c) 2003, 2013, Oracle and/or its affiliates. All rights reserved. ++ * Copyright (c) 2015, 2022, Loongson Technology. All rights reserved. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ * ++ */ ++ ++#ifndef CPU_LOONGARCH_STUBROUTINES_LOONGARCH_64_HPP ++#define CPU_LOONGARCH_STUBROUTINES_LOONGARCH_64_HPP ++ ++// This file holds the platform specific parts of the StubRoutines ++// definition. See stubRoutines.hpp for a description on how to ++// extend it. ++ ++static bool returns_to_call_stub(address return_pc){ ++ return return_pc == _call_stub_return_address||return_pc == la::get_call_stub_compiled_return(); ++} ++ ++enum platform_dependent_constants { ++ code_size1 = 20000, // simply increase if too small (assembler will crash if too small) ++ code_size2 = 60000 // simply increase if too small (assembler will crash if too small) ++}; ++ ++class la { ++ friend class StubGenerator; ++ friend class VMStructs; ++ private: ++ // If we call compiled code directly from the call stub we will ++ // need to adjust the return back to the call stub to a specialized ++ // piece of code that can handle compiled results and cleaning the fpu ++ // stack. The variable holds that location. ++ static address _call_stub_compiled_return; ++ static juint _crc_table[]; ++ // begin trigonometric tables block. See comments in .cpp file ++ static juint _npio2_hw[]; ++ static jdouble _two_over_pi[]; ++ static jdouble _pio2[]; ++ static jdouble _dsin_coef[]; ++ static jdouble _dcos_coef[]; ++ // end trigonometric tables block ++ ++public: ++ // Call back points for traps in compiled code ++ static address get_call_stub_compiled_return() { return _call_stub_compiled_return; } ++ static void set_call_stub_compiled_return(address ret){ _call_stub_compiled_return = ret; } ++ ++}; ++ ++#endif // CPU_LOONGARCH_STUBROUTINES_LOONGARCH_64_HPP +diff --git a/src/hotspot/cpu/loongarch/stubRoutines_loongarch_64.cpp b/src/hotspot/cpu/loongarch/stubRoutines_loongarch_64.cpp +new file mode 100644 +index 0000000000..1a6ea3bcde +--- /dev/null ++++ b/src/hotspot/cpu/loongarch/stubRoutines_loongarch_64.cpp @@ -0,0 +1,178 @@ +/* + * Copyright (c) 2003, 2013, Oracle and/or its affiliates. All rights reserved. @@ -50941,80 +51171,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h + 2.73370053816464559624e-44, // 0x36E3822280000000 + 2.16741683877804819444e-51, // 0x3569F31D00000000 +}; -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/stubRoutines_loongarch.hpp b/src/hotspot/cpu/loongarch/stubRoutines_loongarch.hpp ---- a/src/hotspot/cpu/loongarch/stubRoutines_loongarch.hpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/cpu/loongarch/stubRoutines_loongarch.hpp 2024-01-30 10:00:11.841431732 +0800 -@@ -0,0 +1,67 @@ -+/* -+ * Copyright (c) 2003, 2013, Oracle and/or its affiliates. All rights reserved. -+ * Copyright (c) 2015, 2022, Loongson Technology. All rights reserved. -+ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. -+ * -+ * This code is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 only, as -+ * published by the Free Software Foundation. -+ * -+ * This code is distributed in the hope that it will be useful, but WITHOUT -+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -+ * version 2 for more details (a copy is included in the LICENSE file that -+ * accompanied this code). -+ * -+ * You should have received a copy of the GNU General Public License version -+ * 2 along with this work; if not, write to the Free Software Foundation, -+ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. -+ * -+ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA -+ * or visit www.oracle.com if you need additional information or have any -+ * questions. -+ * -+ */ -+ -+#ifndef CPU_LOONGARCH_STUBROUTINES_LOONGARCH_64_HPP -+#define CPU_LOONGARCH_STUBROUTINES_LOONGARCH_64_HPP -+ -+// This file holds the platform specific parts of the StubRoutines -+// definition. See stubRoutines.hpp for a description on how to -+// extend it. -+ -+static bool returns_to_call_stub(address return_pc){ -+ return return_pc == _call_stub_return_address||return_pc == la::get_call_stub_compiled_return(); -+} -+ -+enum platform_dependent_constants { -+ code_size1 = 20000, // simply increase if too small (assembler will crash if too small) -+ code_size2 = 60000 // simply increase if too small (assembler will crash if too small) -+}; -+ -+class la { -+ friend class StubGenerator; -+ friend class VMStructs; -+ private: -+ // If we call compiled code directly from the call stub we will -+ // need to adjust the return back to the call stub to a specialized -+ // piece of code that can handle compiled results and cleaning the fpu -+ // stack. The variable holds that location. -+ static address _call_stub_compiled_return; -+ static juint _crc_table[]; -+ // begin trigonometric tables block. See comments in .cpp file -+ static juint _npio2_hw[]; -+ static jdouble _two_over_pi[]; -+ static jdouble _pio2[]; -+ static jdouble _dsin_coef[]; -+ static jdouble _dcos_coef[]; -+ // end trigonometric tables block -+ -+public: -+ // Call back points for traps in compiled code -+ static address get_call_stub_compiled_return() { return _call_stub_compiled_return; } -+ static void set_call_stub_compiled_return(address ret){ _call_stub_compiled_return = ret; } -+ -+}; -+ -+#endif // CPU_LOONGARCH_STUBROUTINES_LOONGARCH_64_HPP -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/templateInterpreterGenerator_loongarch.cpp b/src/hotspot/cpu/loongarch/templateInterpreterGenerator_loongarch.cpp ---- a/src/hotspot/cpu/loongarch/templateInterpreterGenerator_loongarch.cpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/cpu/loongarch/templateInterpreterGenerator_loongarch.cpp 2024-01-30 10:00:11.841431732 +0800 +diff --git a/src/hotspot/cpu/loongarch/templateInterpreterGenerator_loongarch.cpp b/src/hotspot/cpu/loongarch/templateInterpreterGenerator_loongarch.cpp +new file mode 100644 +index 0000000000..be1d28d4b8 +--- /dev/null ++++ b/src/hotspot/cpu/loongarch/templateInterpreterGenerator_loongarch.cpp @@ -0,0 +1,2269 @@ +/* + * Copyright (c) 2003, 2013, Oracle and/or its affiliates. All rights reserved. @@ -53285,10 +53446,61 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h + __ bind(L); +} +#endif // !PRODUCT -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/templateTable_loongarch_64.cpp b/src/hotspot/cpu/loongarch/templateTable_loongarch_64.cpp ---- a/src/hotspot/cpu/loongarch/templateTable_loongarch_64.cpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/cpu/loongarch/templateTable_loongarch_64.cpp 2024-01-30 10:00:11.841431732 +0800 -@@ -0,0 +1,4115 @@ +diff --git a/src/hotspot/cpu/loongarch/templateTable_loongarch.hpp b/src/hotspot/cpu/loongarch/templateTable_loongarch.hpp +new file mode 100644 +index 0000000000..ddb38faf44 +--- /dev/null ++++ b/src/hotspot/cpu/loongarch/templateTable_loongarch.hpp +@@ -0,0 +1,43 @@ ++/* ++ * Copyright (c) 2003, 2012, Oracle and/or its affiliates. All rights reserved. ++ * Copyright (c) 2015, 2022, Loongson Technology. All rights reserved. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ * ++ */ ++ ++#ifndef CPU_LOONGARCH_TEMPLATETABLE_LOONGARCH_64_HPP ++#define CPU_LOONGARCH_TEMPLATETABLE_LOONGARCH_64_HPP ++ ++ static void prepare_invoke(int byte_no, ++ Register method, // linked method (or i-klass) ++ Register index = noreg, // itable index, MethodType, etc. ++ Register recv = noreg, // if caller wants to see it ++ Register flags = noreg // if caller wants to test it ++ ); ++ static void invokevirtual_helper(Register index, Register recv, ++ Register flags); ++ static void volatile_barrier(); ++ ++ // Helpers ++ static void index_check(Register array, Register index); ++ static void index_check_without_pop(Register array, Register index); ++ ++#endif // CPU_LOONGARCH_TEMPLATETABLE_LOONGARCH_64_HPP +diff --git a/src/hotspot/cpu/loongarch/templateTable_loongarch_64.cpp b/src/hotspot/cpu/loongarch/templateTable_loongarch_64.cpp +new file mode 100644 +index 0000000000..673032218f +--- /dev/null ++++ b/src/hotspot/cpu/loongarch/templateTable_loongarch_64.cpp +@@ -0,0 +1,4113 @@ +/* + * Copyright (c) 2003, 2013, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 2015, 2022, Loongson Technology. All rights reserved. @@ -56802,7 +57014,6 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h + + __ bind(no_such_method); + // throw exception -+ __ pop(Rmethod); // pop return address (pushed by prepare_invoke) + __ restore_bcp(); + __ restore_locals(); + // Pass arguments for generating a verbose error message. @@ -56816,7 +57027,6 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h + + __ bind(no_such_interface); + // throw exception -+ __ pop(Rmethod); // pop return address (pushed by prepare_invoke) + __ restore_bcp(); + __ restore_locals(); + // Pass arguments for generating a verbose error message. @@ -57404,218 +57614,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h + __ membar(__ AnyAny);//no membar here for aarch64 +} +#endif // !CC_INTERP -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/templateTable_loongarch.hpp b/src/hotspot/cpu/loongarch/templateTable_loongarch.hpp ---- a/src/hotspot/cpu/loongarch/templateTable_loongarch.hpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/cpu/loongarch/templateTable_loongarch.hpp 2024-01-30 10:00:11.841431732 +0800 -@@ -0,0 +1,43 @@ -+/* -+ * Copyright (c) 2003, 2012, Oracle and/or its affiliates. All rights reserved. -+ * Copyright (c) 2015, 2022, Loongson Technology. All rights reserved. -+ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. -+ * -+ * This code is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 only, as -+ * published by the Free Software Foundation. -+ * -+ * This code is distributed in the hope that it will be useful, but WITHOUT -+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -+ * version 2 for more details (a copy is included in the LICENSE file that -+ * accompanied this code). -+ * -+ * You should have received a copy of the GNU General Public License version -+ * 2 along with this work; if not, write to the Free Software Foundation, -+ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. -+ * -+ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA -+ * or visit www.oracle.com if you need additional information or have any -+ * questions. -+ * -+ */ -+ -+#ifndef CPU_LOONGARCH_TEMPLATETABLE_LOONGARCH_64_HPP -+#define CPU_LOONGARCH_TEMPLATETABLE_LOONGARCH_64_HPP -+ -+ static void prepare_invoke(int byte_no, -+ Register method, // linked method (or i-klass) -+ Register index = noreg, // itable index, MethodType, etc. -+ Register recv = noreg, // if caller wants to see it -+ Register flags = noreg // if caller wants to test it -+ ); -+ static void invokevirtual_helper(Register index, Register recv, -+ Register flags); -+ static void volatile_barrier(); -+ -+ // Helpers -+ static void index_check(Register array, Register index); -+ static void index_check_without_pop(Register array, Register index); -+ -+#endif // CPU_LOONGARCH_TEMPLATETABLE_LOONGARCH_64_HPP -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/vmreg_loongarch.cpp b/src/hotspot/cpu/loongarch/vmreg_loongarch.cpp ---- a/src/hotspot/cpu/loongarch/vmreg_loongarch.cpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/cpu/loongarch/vmreg_loongarch.cpp 2024-01-30 10:00:11.844765024 +0800 -@@ -0,0 +1,53 @@ -+/* -+ * Copyright (c) 2006, 2012, Oracle and/or its affiliates. All rights reserved. -+ * Copyright (c) 2015, 2022, Loongson Technology. All rights reserved. -+ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. -+ * -+ * This code is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 only, as -+ * published by the Free Software Foundation. -+ * -+ * This code is distributed in the hope that it will be useful, but WITHOUT -+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -+ * version 2 for more details (a copy is included in the LICENSE file that -+ * accompanied this code). -+ * -+ * You should have received a copy of the GNU General Public License version -+ * 2 along with this work; if not, write to the Free Software Foundation, -+ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. -+ * -+ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA -+ * or visit www.oracle.com if you need additional information or have any -+ * questions. -+ * -+ */ -+ -+#include "precompiled.hpp" -+#include "asm/assembler.hpp" -+#include "code/vmreg.hpp" -+ -+ -+ -+void VMRegImpl::set_regName() { -+ Register reg = ::as_Register(0); -+ int i; -+ for (i = 0; i < ConcreteRegisterImpl::max_gpr ; ) { -+ for (int j = 0 ; j < RegisterImpl::max_slots_per_register ; j++) { -+ regName[i++] = reg->name(); -+ } -+ reg = reg->successor(); -+ } -+ -+ FloatRegister freg = ::as_FloatRegister(0); -+ for ( ; i < ConcreteRegisterImpl::max_fpr ; ) { -+ for (int j = 0 ; j < FloatRegisterImpl::max_slots_per_register ; j++) { -+ regName[i++] = freg->name(); -+ } -+ freg = freg->successor(); -+ } -+ -+ for ( ; i < ConcreteRegisterImpl::number_of_registers ; i ++ ) { -+ regName[i] = "NON-GPR-FPR"; -+ } -+} -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/vmreg_loongarch.hpp b/src/hotspot/cpu/loongarch/vmreg_loongarch.hpp ---- a/src/hotspot/cpu/loongarch/vmreg_loongarch.hpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/cpu/loongarch/vmreg_loongarch.hpp 2024-01-30 10:00:11.844765024 +0800 -@@ -0,0 +1,58 @@ -+/* -+ * Copyright (c) 2006, 2010, Oracle and/or its affiliates. All rights reserved. -+ * Copyright (c) 2015, 2022, Loongson Technology. All rights reserved. -+ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. -+ * -+ * This code is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 only, as -+ * published by the Free Software Foundation. -+ * -+ * This code is distributed in the hope that it will be useful, but WITHOUT -+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -+ * version 2 for more details (a copy is included in the LICENSE file that -+ * accompanied this code). -+ * -+ * You should have received a copy of the GNU General Public License version -+ * 2 along with this work; if not, write to the Free Software Foundation, -+ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. -+ * -+ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA -+ * or visit www.oracle.com if you need additional information or have any -+ * questions. -+ * -+ */ -+ -+#ifndef CPU_LOONGARCH_VMREG_LOONGARCH_HPP -+#define CPU_LOONGARCH_VMREG_LOONGARCH_HPP -+ -+inline bool is_Register() { -+ return (unsigned int) value() < (unsigned int) ConcreteRegisterImpl::max_gpr; -+} -+ -+inline Register as_Register() { -+ assert( is_Register(), "must be"); -+ return ::as_Register(value() / RegisterImpl::max_slots_per_register); -+} -+ -+inline bool is_FloatRegister() { -+ return value() >= ConcreteRegisterImpl::max_gpr && value() < ConcreteRegisterImpl::max_fpr; -+} -+ -+inline FloatRegister as_FloatRegister() { -+ assert( is_FloatRegister() && is_even(value()), "must be" ); -+ return ::as_FloatRegister((value() - ConcreteRegisterImpl::max_gpr) / -+ FloatRegisterImpl::max_slots_per_register); -+} -+ -+inline bool is_concrete() { -+ assert(is_reg(), "must be"); -+ if (is_FloatRegister()) { -+ int base = value() - ConcreteRegisterImpl::max_gpr; -+ return base % FloatRegisterImpl::max_slots_per_register == 0; -+ } else { -+ return is_even(value()); -+ } -+} -+ -+#endif // CPU_LOONGARCH_VMREG_LOONGARCH_HPP -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/vmreg_loongarch.inline.hpp b/src/hotspot/cpu/loongarch/vmreg_loongarch.inline.hpp ---- a/src/hotspot/cpu/loongarch/vmreg_loongarch.inline.hpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/cpu/loongarch/vmreg_loongarch.inline.hpp 2024-01-30 10:00:11.844765024 +0800 -@@ -0,0 +1,39 @@ -+/* -+ * Copyright (c) 2006, 2012, Oracle and/or its affiliates. All rights reserved. -+ * Copyright (c) 2015, 2022, Loongson Technology. All rights reserved. -+ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. -+ * -+ * This code is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 only, as -+ * published by the Free Software Foundation. -+ * -+ * This code is distributed in the hope that it will be useful, but WITHOUT -+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -+ * version 2 for more details (a copy is included in the LICENSE file that -+ * accompanied this code). -+ * -+ * You should have received a copy of the GNU General Public License version -+ * 2 along with this work; if not, write to the Free Software Foundation, -+ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. -+ * -+ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA -+ * or visit www.oracle.com if you need additional information or have any -+ * questions. -+ * -+ */ -+ -+#ifndef CPU_LOONGARCH_VMREG_LOONGARCH_INLINE_HPP -+#define CPU_LOONGARCH_VMREG_LOONGARCH_INLINE_HPP -+ -+inline VMReg RegisterImpl::as_VMReg() { -+ if( this==noreg ) return VMRegImpl::Bad(); -+ return VMRegImpl::as_VMReg(encoding() * RegisterImpl::max_slots_per_register); -+} -+ -+inline VMReg FloatRegisterImpl::as_VMReg() { -+ return VMRegImpl::as_VMReg((encoding() * FloatRegisterImpl::max_slots_per_register) + -+ ConcreteRegisterImpl::max_gpr); -+} -+ -+#endif // CPU_LOONGARCH_VMREG_LOONGARCH_INLINE_HPP -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/vmStructs_loongarch.hpp b/src/hotspot/cpu/loongarch/vmStructs_loongarch.hpp ---- a/src/hotspot/cpu/loongarch/vmStructs_loongarch.hpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/cpu/loongarch/vmStructs_loongarch.hpp 2024-01-30 10:00:11.841431732 +0800 +diff --git a/src/hotspot/cpu/loongarch/vmStructs_loongarch.hpp b/src/hotspot/cpu/loongarch/vmStructs_loongarch.hpp +new file mode 100644 +index 0000000000..5b9f7b7898 +--- /dev/null ++++ b/src/hotspot/cpu/loongarch/vmStructs_loongarch.hpp @@ -0,0 +1,61 @@ +/* + * Copyright (c) 2001, 2013, Oracle and/or its affiliates. All rights reserved. @@ -57678,9 +57681,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h + /* be present there) */ + +#endif // CPU_LOONGARCH_VMSTRUCTS_LOONGARCH_HPP -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/vm_version_ext_loongarch.cpp b/src/hotspot/cpu/loongarch/vm_version_ext_loongarch.cpp ---- a/src/hotspot/cpu/loongarch/vm_version_ext_loongarch.cpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/cpu/loongarch/vm_version_ext_loongarch.cpp 2024-01-30 10:00:11.841431732 +0800 +diff --git a/src/hotspot/cpu/loongarch/vm_version_ext_loongarch.cpp b/src/hotspot/cpu/loongarch/vm_version_ext_loongarch.cpp +new file mode 100644 +index 0000000000..eb8f075c71 +--- /dev/null ++++ b/src/hotspot/cpu/loongarch/vm_version_ext_loongarch.cpp @@ -0,0 +1,85 @@ +/* + * Copyright (c) 2013, 2018, Oracle and/or its affiliates. All rights reserved. @@ -57767,9 +57772,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h + strncpy(tmp, _cpu_desc, CPU_DETAILED_DESC_BUF_SIZE); + return tmp; +} -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/vm_version_ext_loongarch.hpp b/src/hotspot/cpu/loongarch/vm_version_ext_loongarch.hpp ---- a/src/hotspot/cpu/loongarch/vm_version_ext_loongarch.hpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/cpu/loongarch/vm_version_ext_loongarch.hpp 2024-01-30 10:00:11.844765024 +0800 +diff --git a/src/hotspot/cpu/loongarch/vm_version_ext_loongarch.hpp b/src/hotspot/cpu/loongarch/vm_version_ext_loongarch.hpp +new file mode 100644 +index 0000000000..1a93123134 +--- /dev/null ++++ b/src/hotspot/cpu/loongarch/vm_version_ext_loongarch.hpp @@ -0,0 +1,54 @@ +/* + * Copyright (c) 2016, 2018, Oracle and/or its affiliates. All rights reserved. @@ -57825,9 +57832,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h +}; + +#endif // CPU_LOONGARCH_VM_VERSION_EXT_LOONGARCH_HPP -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/vm_version_loongarch.cpp b/src/hotspot/cpu/loongarch/vm_version_loongarch.cpp ---- a/src/hotspot/cpu/loongarch/vm_version_loongarch.cpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/cpu/loongarch/vm_version_loongarch.cpp 2024-01-30 10:00:11.844765024 +0800 +diff --git a/src/hotspot/cpu/loongarch/vm_version_loongarch.cpp b/src/hotspot/cpu/loongarch/vm_version_loongarch.cpp +new file mode 100644 +index 0000000000..9115135166 +--- /dev/null ++++ b/src/hotspot/cpu/loongarch/vm_version_loongarch.cpp @@ -0,0 +1,397 @@ +/* + * Copyright (c) 1997, 2014, Oracle and/or its affiliates. All rights reserved. @@ -58226,9 +58235,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h + + get_processor_features(); +} -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/vm_version_loongarch.hpp b/src/hotspot/cpu/loongarch/vm_version_loongarch.hpp ---- a/src/hotspot/cpu/loongarch/vm_version_loongarch.hpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/cpu/loongarch/vm_version_loongarch.hpp 2024-01-30 10:00:11.844765024 +0800 +diff --git a/src/hotspot/cpu/loongarch/vm_version_loongarch.hpp b/src/hotspot/cpu/loongarch/vm_version_loongarch.hpp +new file mode 100644 +index 0000000000..00b8e608a1 +--- /dev/null ++++ b/src/hotspot/cpu/loongarch/vm_version_loongarch.hpp @@ -0,0 +1,292 @@ +/* + * Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved. @@ -58522,9 +58533,179 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h +}; + +#endif // CPU_LOONGARCH_VM_VERSION_LOONGARCH_HPP -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/vtableStubs_loongarch_64.cpp b/src/hotspot/cpu/loongarch/vtableStubs_loongarch_64.cpp ---- a/src/hotspot/cpu/loongarch/vtableStubs_loongarch_64.cpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/cpu/loongarch/vtableStubs_loongarch_64.cpp 2024-01-30 10:00:11.844765024 +0800 +diff --git a/src/hotspot/cpu/loongarch/vmreg_loongarch.cpp b/src/hotspot/cpu/loongarch/vmreg_loongarch.cpp +new file mode 100644 +index 0000000000..43caba5187 +--- /dev/null ++++ b/src/hotspot/cpu/loongarch/vmreg_loongarch.cpp +@@ -0,0 +1,53 @@ ++/* ++ * Copyright (c) 2006, 2012, Oracle and/or its affiliates. All rights reserved. ++ * Copyright (c) 2015, 2022, Loongson Technology. All rights reserved. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ * ++ */ ++ ++#include "precompiled.hpp" ++#include "asm/assembler.hpp" ++#include "code/vmreg.hpp" ++ ++ ++ ++void VMRegImpl::set_regName() { ++ Register reg = ::as_Register(0); ++ int i; ++ for (i = 0; i < ConcreteRegisterImpl::max_gpr ; ) { ++ for (int j = 0 ; j < RegisterImpl::max_slots_per_register ; j++) { ++ regName[i++] = reg->name(); ++ } ++ reg = reg->successor(); ++ } ++ ++ FloatRegister freg = ::as_FloatRegister(0); ++ for ( ; i < ConcreteRegisterImpl::max_fpr ; ) { ++ for (int j = 0 ; j < FloatRegisterImpl::max_slots_per_register ; j++) { ++ regName[i++] = freg->name(); ++ } ++ freg = freg->successor(); ++ } ++ ++ for ( ; i < ConcreteRegisterImpl::number_of_registers ; i ++ ) { ++ regName[i] = "NON-GPR-FPR"; ++ } ++} +diff --git a/src/hotspot/cpu/loongarch/vmreg_loongarch.hpp b/src/hotspot/cpu/loongarch/vmreg_loongarch.hpp +new file mode 100644 +index 0000000000..819eaff0bb +--- /dev/null ++++ b/src/hotspot/cpu/loongarch/vmreg_loongarch.hpp +@@ -0,0 +1,58 @@ ++/* ++ * Copyright (c) 2006, 2010, Oracle and/or its affiliates. All rights reserved. ++ * Copyright (c) 2015, 2022, Loongson Technology. All rights reserved. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ * ++ */ ++ ++#ifndef CPU_LOONGARCH_VMREG_LOONGARCH_HPP ++#define CPU_LOONGARCH_VMREG_LOONGARCH_HPP ++ ++inline bool is_Register() { ++ return (unsigned int) value() < (unsigned int) ConcreteRegisterImpl::max_gpr; ++} ++ ++inline Register as_Register() { ++ assert( is_Register(), "must be"); ++ return ::as_Register(value() / RegisterImpl::max_slots_per_register); ++} ++ ++inline bool is_FloatRegister() { ++ return value() >= ConcreteRegisterImpl::max_gpr && value() < ConcreteRegisterImpl::max_fpr; ++} ++ ++inline FloatRegister as_FloatRegister() { ++ assert( is_FloatRegister() && is_even(value()), "must be" ); ++ return ::as_FloatRegister((value() - ConcreteRegisterImpl::max_gpr) / ++ FloatRegisterImpl::max_slots_per_register); ++} ++ ++inline bool is_concrete() { ++ assert(is_reg(), "must be"); ++ if (is_FloatRegister()) { ++ int base = value() - ConcreteRegisterImpl::max_gpr; ++ return base % FloatRegisterImpl::max_slots_per_register == 0; ++ } else { ++ return is_even(value()); ++ } ++} ++ ++#endif // CPU_LOONGARCH_VMREG_LOONGARCH_HPP +diff --git a/src/hotspot/cpu/loongarch/vmreg_loongarch.inline.hpp b/src/hotspot/cpu/loongarch/vmreg_loongarch.inline.hpp +new file mode 100644 +index 0000000000..edb78e36da +--- /dev/null ++++ b/src/hotspot/cpu/loongarch/vmreg_loongarch.inline.hpp +@@ -0,0 +1,39 @@ ++/* ++ * Copyright (c) 2006, 2012, Oracle and/or its affiliates. All rights reserved. ++ * Copyright (c) 2015, 2022, Loongson Technology. All rights reserved. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ * ++ */ ++ ++#ifndef CPU_LOONGARCH_VMREG_LOONGARCH_INLINE_HPP ++#define CPU_LOONGARCH_VMREG_LOONGARCH_INLINE_HPP ++ ++inline VMReg RegisterImpl::as_VMReg() { ++ if( this==noreg ) return VMRegImpl::Bad(); ++ return VMRegImpl::as_VMReg(encoding() * RegisterImpl::max_slots_per_register); ++} ++ ++inline VMReg FloatRegisterImpl::as_VMReg() { ++ return VMRegImpl::as_VMReg((encoding() * FloatRegisterImpl::max_slots_per_register) + ++ ConcreteRegisterImpl::max_gpr); ++} ++ ++#endif // CPU_LOONGARCH_VMREG_LOONGARCH_INLINE_HPP +diff --git a/src/hotspot/cpu/loongarch/vtableStubs_loongarch_64.cpp b/src/hotspot/cpu/loongarch/vtableStubs_loongarch_64.cpp +new file mode 100644 +index 0000000000..2c4b60653b +--- /dev/null ++++ b/src/hotspot/cpu/loongarch/vtableStubs_loongarch_64.cpp @@ -0,0 +1,322 @@ +/* + * Copyright (c) 2003, 2014, Oracle and/or its affiliates. All rights reserved. @@ -58848,9 +59029,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h + const unsigned int icache_line_size = wordSize; + return icache_line_size; +} -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/mips/abstractInterpreter_mips.cpp b/src/hotspot/cpu/mips/abstractInterpreter_mips.cpp ---- a/src/hotspot/cpu/mips/abstractInterpreter_mips.cpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/cpu/mips/abstractInterpreter_mips.cpp 2024-01-30 10:00:11.844765024 +0800 +diff --git a/src/hotspot/cpu/mips/abstractInterpreter_mips.cpp b/src/hotspot/cpu/mips/abstractInterpreter_mips.cpp +new file mode 100644 +index 0000000000..73f021c9b7 +--- /dev/null ++++ b/src/hotspot/cpu/mips/abstractInterpreter_mips.cpp @@ -0,0 +1,132 @@ +/* + * Copyright (c) 2003, 2013, Oracle and/or its affiliates. All rights reserved. @@ -58984,9 +59167,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h + *interpreter_frame->interpreter_frame_mirror_addr() = method->method_holder()->java_mirror(); +} + -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/mips/assembler_mips.cpp b/src/hotspot/cpu/mips/assembler_mips.cpp ---- a/src/hotspot/cpu/mips/assembler_mips.cpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/cpu/mips/assembler_mips.cpp 2024-01-30 10:00:11.844765024 +0800 +diff --git a/src/hotspot/cpu/mips/assembler_mips.cpp b/src/hotspot/cpu/mips/assembler_mips.cpp +new file mode 100644 +index 0000000000..c8c7a5d4df +--- /dev/null ++++ b/src/hotspot/cpu/mips/assembler_mips.cpp @@ -0,0 +1,759 @@ +/* + * Copyright (c) 1997, 2014, Oracle and/or its affiliates. All rights reserved. @@ -59747,9 +59932,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h + delay_state = no_delay; +#endif +} -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/mips/assembler_mips.hpp b/src/hotspot/cpu/mips/assembler_mips.hpp ---- a/src/hotspot/cpu/mips/assembler_mips.hpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/cpu/mips/assembler_mips.hpp 2024-01-30 10:00:11.844765024 +0800 +diff --git a/src/hotspot/cpu/mips/assembler_mips.hpp b/src/hotspot/cpu/mips/assembler_mips.hpp +new file mode 100644 +index 0000000000..102a7ba52f +--- /dev/null ++++ b/src/hotspot/cpu/mips/assembler_mips.hpp @@ -0,0 +1,1789 @@ +/* + * Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved. @@ -61540,9 +61727,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h +}; + +#endif // CPU_MIPS_VM_ASSEMBLER_MIPS_HPP -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/mips/assembler_mips.inline.hpp b/src/hotspot/cpu/mips/assembler_mips.inline.hpp ---- a/src/hotspot/cpu/mips/assembler_mips.inline.hpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/cpu/mips/assembler_mips.inline.hpp 2024-01-30 10:00:11.844765024 +0800 +diff --git a/src/hotspot/cpu/mips/assembler_mips.inline.hpp b/src/hotspot/cpu/mips/assembler_mips.inline.hpp +new file mode 100644 +index 0000000000..f35a06fc4e +--- /dev/null ++++ b/src/hotspot/cpu/mips/assembler_mips.inline.hpp @@ -0,0 +1,33 @@ +/* + * Copyright (c) 1997, 2010, Oracle and/or its affiliates. All rights reserved. @@ -61577,9 +61766,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h +#include "code/codeCache.hpp" + +#endif // CPU_MIPS_VM_ASSEMBLER_MIPS_INLINE_HPP -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/mips/bytes_mips.hpp b/src/hotspot/cpu/mips/bytes_mips.hpp ---- a/src/hotspot/cpu/mips/bytes_mips.hpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/cpu/mips/bytes_mips.hpp 2024-01-30 10:00:11.844765024 +0800 +diff --git a/src/hotspot/cpu/mips/bytes_mips.hpp b/src/hotspot/cpu/mips/bytes_mips.hpp +new file mode 100644 +index 0000000000..4172db219b +--- /dev/null ++++ b/src/hotspot/cpu/mips/bytes_mips.hpp @@ -0,0 +1,181 @@ +/* + * Copyright (c) 1997, 2010, Oracle and/or its affiliates. All rights reserved. @@ -61762,9 +61953,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h +#include OS_CPU_HEADER_INLINE(bytes) + +#endif // CPU_MIPS_VM_BYTES_MIPS_HPP -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/mips/c2_globals_mips.hpp b/src/hotspot/cpu/mips/c2_globals_mips.hpp ---- a/src/hotspot/cpu/mips/c2_globals_mips.hpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/cpu/mips/c2_globals_mips.hpp 2024-01-30 10:00:11.844765024 +0800 +diff --git a/src/hotspot/cpu/mips/c2_globals_mips.hpp b/src/hotspot/cpu/mips/c2_globals_mips.hpp +new file mode 100644 +index 0000000000..ef11827abf +--- /dev/null ++++ b/src/hotspot/cpu/mips/c2_globals_mips.hpp @@ -0,0 +1,95 @@ +/* + * Copyright (c) 2000, 2013, Oracle and/or its affiliates. All rights reserved. @@ -61861,9 +62054,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h +define_pd_global(bool, NeverActAsServerClassMachine, false); + +#endif // CPU_MIPS_VM_C2_GLOBALS_MIPS_HPP -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/mips/c2_init_mips.cpp b/src/hotspot/cpu/mips/c2_init_mips.cpp ---- a/src/hotspot/cpu/mips/c2_init_mips.cpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/cpu/mips/c2_init_mips.cpp 2024-01-30 10:00:11.844765024 +0800 +diff --git a/src/hotspot/cpu/mips/c2_init_mips.cpp b/src/hotspot/cpu/mips/c2_init_mips.cpp +new file mode 100644 +index 0000000000..e6d5815f42 +--- /dev/null ++++ b/src/hotspot/cpu/mips/c2_init_mips.cpp @@ -0,0 +1,34 @@ +/* + * Copyright (c) 2000, 2010, Oracle and/or its affiliates. All rights reserved. @@ -61899,9 +62094,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h +void Compile::pd_compiler2_init() { + guarantee(CodeEntryAlignment >= InteriorEntryAlignment, "" ); +} -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/mips/codeBuffer_mips.hpp b/src/hotspot/cpu/mips/codeBuffer_mips.hpp ---- a/src/hotspot/cpu/mips/codeBuffer_mips.hpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/cpu/mips/codeBuffer_mips.hpp 2024-01-30 10:00:11.844765024 +0800 +diff --git a/src/hotspot/cpu/mips/codeBuffer_mips.hpp b/src/hotspot/cpu/mips/codeBuffer_mips.hpp +new file mode 100644 +index 0000000000..3cc191006d +--- /dev/null ++++ b/src/hotspot/cpu/mips/codeBuffer_mips.hpp @@ -0,0 +1,35 @@ +/* + * Copyright (c) 2002, 2010, Oracle and/or its affiliates. All rights reserved. @@ -61938,9 +62135,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h + void flush_bundle(bool start_new_bundle) {} + +#endif // CPU_MIPS_VM_CODEBUFFER_MIPS_HPP -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/mips/compiledIC_mips.cpp b/src/hotspot/cpu/mips/compiledIC_mips.cpp ---- a/src/hotspot/cpu/mips/compiledIC_mips.cpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/cpu/mips/compiledIC_mips.cpp 2024-01-30 10:00:11.844765024 +0800 +diff --git a/src/hotspot/cpu/mips/compiledIC_mips.cpp b/src/hotspot/cpu/mips/compiledIC_mips.cpp +new file mode 100644 +index 0000000000..068ca4799d +--- /dev/null ++++ b/src/hotspot/cpu/mips/compiledIC_mips.cpp @@ -0,0 +1,151 @@ +/* + * Copyright (c) 1997, 2014, Oracle and/or its affiliates. All rights reserved. @@ -62093,9 +62292,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h +} + +#endif // !PRODUCT -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/mips/copy_mips.hpp b/src/hotspot/cpu/mips/copy_mips.hpp ---- a/src/hotspot/cpu/mips/copy_mips.hpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/cpu/mips/copy_mips.hpp 2024-01-30 10:00:11.844765024 +0800 +diff --git a/src/hotspot/cpu/mips/copy_mips.hpp b/src/hotspot/cpu/mips/copy_mips.hpp +new file mode 100644 +index 0000000000..dcc77adfec +--- /dev/null ++++ b/src/hotspot/cpu/mips/copy_mips.hpp @@ -0,0 +1,77 @@ +/* + * Copyright (c) 2003, 2010, Oracle and/or its affiliates. All rights reserved. @@ -62174,9 +62375,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h +} + +#endif //CPU_MIPS_VM_COPY_MIPS_HPP -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/mips/depChecker_mips.cpp b/src/hotspot/cpu/mips/depChecker_mips.cpp ---- a/src/hotspot/cpu/mips/depChecker_mips.cpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/cpu/mips/depChecker_mips.cpp 2024-01-30 10:00:11.844765024 +0800 +diff --git a/src/hotspot/cpu/mips/depChecker_mips.cpp b/src/hotspot/cpu/mips/depChecker_mips.cpp +new file mode 100644 +index 0000000000..756ccb68f9 +--- /dev/null ++++ b/src/hotspot/cpu/mips/depChecker_mips.cpp @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2002, 2010, Oracle and/or its affiliates. All rights reserved. @@ -62208,9 +62411,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h +#include "depChecker_mips.hpp" + +// Nothing to do on mips -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/mips/depChecker_mips.hpp b/src/hotspot/cpu/mips/depChecker_mips.hpp ---- a/src/hotspot/cpu/mips/depChecker_mips.hpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/cpu/mips/depChecker_mips.hpp 2024-01-30 10:00:11.844765024 +0800 +diff --git a/src/hotspot/cpu/mips/depChecker_mips.hpp b/src/hotspot/cpu/mips/depChecker_mips.hpp +new file mode 100644 +index 0000000000..11e52b4e8f +--- /dev/null ++++ b/src/hotspot/cpu/mips/depChecker_mips.hpp @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2002, 2010, Oracle and/or its affiliates. All rights reserved. @@ -62243,9 +62448,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h +// Nothing to do on MIPS + +#endif // CPU_MIPS_VM_DEPCHECKER_MIPS_HPP -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/mips/disassembler_mips.hpp b/src/hotspot/cpu/mips/disassembler_mips.hpp ---- a/src/hotspot/cpu/mips/disassembler_mips.hpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/cpu/mips/disassembler_mips.hpp 2024-01-30 10:00:11.844765024 +0800 +diff --git a/src/hotspot/cpu/mips/disassembler_mips.hpp b/src/hotspot/cpu/mips/disassembler_mips.hpp +new file mode 100644 +index 0000000000..c5f3a8888d +--- /dev/null ++++ b/src/hotspot/cpu/mips/disassembler_mips.hpp @@ -0,0 +1,37 @@ +/* + * Copyright (c) 1997, 2010, Oracle and/or its affiliates. All rights reserved. @@ -62284,9 +62491,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h + } + +#endif // CPU_MIPS_VM_DISASSEMBLER_MIPS_HPP -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/mips/frame_mips.cpp b/src/hotspot/cpu/mips/frame_mips.cpp ---- a/src/hotspot/cpu/mips/frame_mips.cpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/cpu/mips/frame_mips.cpp 2024-01-30 10:00:11.844765024 +0800 +diff --git a/src/hotspot/cpu/mips/frame_mips.cpp b/src/hotspot/cpu/mips/frame_mips.cpp +new file mode 100644 +index 0000000000..d49bd6290d +--- /dev/null ++++ b/src/hotspot/cpu/mips/frame_mips.cpp @@ -0,0 +1,690 @@ +/* + * Copyright (c) 1997, 2014, Oracle and/or its affiliates. All rights reserved. @@ -62978,9 +63187,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h + +void frame::pd_ps() {} +#endif -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/mips/frame_mips.hpp b/src/hotspot/cpu/mips/frame_mips.hpp ---- a/src/hotspot/cpu/mips/frame_mips.hpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/cpu/mips/frame_mips.hpp 2024-01-30 10:00:11.844765024 +0800 +diff --git a/src/hotspot/cpu/mips/frame_mips.hpp b/src/hotspot/cpu/mips/frame_mips.hpp +new file mode 100644 +index 0000000000..bdbfa8aaa2 +--- /dev/null ++++ b/src/hotspot/cpu/mips/frame_mips.hpp @@ -0,0 +1,215 @@ +/* + * Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved. @@ -63197,9 +63408,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h + static jint interpreter_frame_expression_stack_direction() { return -1; } + +#endif // CPU_MIPS_VM_FRAME_MIPS_HPP -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/mips/frame_mips.inline.hpp b/src/hotspot/cpu/mips/frame_mips.inline.hpp ---- a/src/hotspot/cpu/mips/frame_mips.inline.hpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/cpu/mips/frame_mips.inline.hpp 2024-01-30 10:00:11.844765024 +0800 +diff --git a/src/hotspot/cpu/mips/frame_mips.inline.hpp b/src/hotspot/cpu/mips/frame_mips.inline.hpp +new file mode 100644 +index 0000000000..c408f01d69 +--- /dev/null ++++ b/src/hotspot/cpu/mips/frame_mips.inline.hpp @@ -0,0 +1,238 @@ +/* + * Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved. @@ -63439,9 +63652,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h +} + +#endif // CPU_MIPS_VM_FRAME_MIPS_INLINE_HPP -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/mips/gc/g1/g1BarrierSetAssembler_mips.cpp b/src/hotspot/cpu/mips/gc/g1/g1BarrierSetAssembler_mips.cpp ---- a/src/hotspot/cpu/mips/gc/g1/g1BarrierSetAssembler_mips.cpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/cpu/mips/gc/g1/g1BarrierSetAssembler_mips.cpp 2024-01-30 10:00:11.844765024 +0800 +diff --git a/src/hotspot/cpu/mips/gc/g1/g1BarrierSetAssembler_mips.cpp b/src/hotspot/cpu/mips/gc/g1/g1BarrierSetAssembler_mips.cpp +new file mode 100644 +index 0000000000..179f7703c8 +--- /dev/null ++++ b/src/hotspot/cpu/mips/gc/g1/g1BarrierSetAssembler_mips.cpp @@ -0,0 +1,364 @@ +/* + * Copyright (c) 2018, Oracle and/or its affiliates. All rights reserved. @@ -63807,9 +64022,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h + } + } +} -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/mips/gc/g1/g1BarrierSetAssembler_mips.hpp b/src/hotspot/cpu/mips/gc/g1/g1BarrierSetAssembler_mips.hpp ---- a/src/hotspot/cpu/mips/gc/g1/g1BarrierSetAssembler_mips.hpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/cpu/mips/gc/g1/g1BarrierSetAssembler_mips.hpp 2024-01-30 10:00:11.844765024 +0800 +diff --git a/src/hotspot/cpu/mips/gc/g1/g1BarrierSetAssembler_mips.hpp b/src/hotspot/cpu/mips/gc/g1/g1BarrierSetAssembler_mips.hpp +new file mode 100644 +index 0000000000..ec5c243c3f +--- /dev/null ++++ b/src/hotspot/cpu/mips/gc/g1/g1BarrierSetAssembler_mips.hpp @@ -0,0 +1,71 @@ +/* + * Copyright (c) 2018, Oracle and/or its affiliates. All rights reserved. @@ -63882,9 +64099,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h +}; + +#endif // CPU_MIPS_GC_G1_G1BARRIERSETASSEMBLER_MIPS_HPP -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/mips/gc/shared/barrierSetAssembler_mips.cpp b/src/hotspot/cpu/mips/gc/shared/barrierSetAssembler_mips.cpp ---- a/src/hotspot/cpu/mips/gc/shared/barrierSetAssembler_mips.cpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/cpu/mips/gc/shared/barrierSetAssembler_mips.cpp 2024-01-30 10:00:11.844765024 +0800 +diff --git a/src/hotspot/cpu/mips/gc/shared/barrierSetAssembler_mips.cpp b/src/hotspot/cpu/mips/gc/shared/barrierSetAssembler_mips.cpp +new file mode 100644 +index 0000000000..071debdc3a +--- /dev/null ++++ b/src/hotspot/cpu/mips/gc/shared/barrierSetAssembler_mips.cpp @@ -0,0 +1,194 @@ +/* + * Copyright (c) 2018, Oracle and/or its affiliates. All rights reserved. @@ -64080,9 +64299,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h + Register t1) { + Unimplemented(); +} -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/mips/gc/shared/barrierSetAssembler_mips.hpp b/src/hotspot/cpu/mips/gc/shared/barrierSetAssembler_mips.hpp ---- a/src/hotspot/cpu/mips/gc/shared/barrierSetAssembler_mips.hpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/cpu/mips/gc/shared/barrierSetAssembler_mips.hpp 2024-01-30 10:00:11.844765024 +0800 +diff --git a/src/hotspot/cpu/mips/gc/shared/barrierSetAssembler_mips.hpp b/src/hotspot/cpu/mips/gc/shared/barrierSetAssembler_mips.hpp +new file mode 100644 +index 0000000000..b97ecbcca5 +--- /dev/null ++++ b/src/hotspot/cpu/mips/gc/shared/barrierSetAssembler_mips.hpp @@ -0,0 +1,83 @@ +/* + * Copyright (c) 2018, Oracle and/or its affiliates. All rights reserved. @@ -64167,9 +64388,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h +}; + +#endif // CPU_MIPS_GC_SHARED_BARRIERSETASSEMBLER_MIPS_HPP -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/mips/gc/shared/cardTableBarrierSetAssembler_mips.cpp b/src/hotspot/cpu/mips/gc/shared/cardTableBarrierSetAssembler_mips.cpp ---- a/src/hotspot/cpu/mips/gc/shared/cardTableBarrierSetAssembler_mips.cpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/cpu/mips/gc/shared/cardTableBarrierSetAssembler_mips.cpp 2024-01-30 10:00:11.844765024 +0800 +diff --git a/src/hotspot/cpu/mips/gc/shared/cardTableBarrierSetAssembler_mips.cpp b/src/hotspot/cpu/mips/gc/shared/cardTableBarrierSetAssembler_mips.cpp +new file mode 100644 +index 0000000000..f33165334c +--- /dev/null ++++ b/src/hotspot/cpu/mips/gc/shared/cardTableBarrierSetAssembler_mips.cpp @@ -0,0 +1,147 @@ +/* + * Copyright (c) 2018, Oracle and/or its affiliates. All rights reserved. @@ -64318,9 +64541,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h + } + } +} -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/mips/gc/shared/cardTableBarrierSetAssembler_mips.hpp b/src/hotspot/cpu/mips/gc/shared/cardTableBarrierSetAssembler_mips.hpp ---- a/src/hotspot/cpu/mips/gc/shared/cardTableBarrierSetAssembler_mips.hpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/cpu/mips/gc/shared/cardTableBarrierSetAssembler_mips.hpp 2024-01-30 10:00:11.844765024 +0800 +diff --git a/src/hotspot/cpu/mips/gc/shared/cardTableBarrierSetAssembler_mips.hpp b/src/hotspot/cpu/mips/gc/shared/cardTableBarrierSetAssembler_mips.hpp +new file mode 100644 +index 0000000000..49c2a0ea80 +--- /dev/null ++++ b/src/hotspot/cpu/mips/gc/shared/cardTableBarrierSetAssembler_mips.hpp @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2018, Oracle and/or its affiliates. All rights reserved. @@ -64364,9 +64589,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h +}; + +#endif // CPU_MIPS_GC_SHARED_CARDTABLEBARRIERSETASSEMBLER_MIPS_HPP -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/mips/gc/shared/modRefBarrierSetAssembler_mips.cpp b/src/hotspot/cpu/mips/gc/shared/modRefBarrierSetAssembler_mips.cpp ---- a/src/hotspot/cpu/mips/gc/shared/modRefBarrierSetAssembler_mips.cpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/cpu/mips/gc/shared/modRefBarrierSetAssembler_mips.cpp 2024-01-30 10:00:11.844765024 +0800 +diff --git a/src/hotspot/cpu/mips/gc/shared/modRefBarrierSetAssembler_mips.cpp b/src/hotspot/cpu/mips/gc/shared/modRefBarrierSetAssembler_mips.cpp +new file mode 100644 +index 0000000000..765259e626 +--- /dev/null ++++ b/src/hotspot/cpu/mips/gc/shared/modRefBarrierSetAssembler_mips.cpp @@ -0,0 +1,53 @@ +/* + * Copyright (c) 2018, Oracle and/or its affiliates. All rights reserved. @@ -64421,9 +64648,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h + BarrierSetAssembler::store_at(masm, decorators, type, dst, val, tmp1, tmp2); + } +} -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/mips/gc/shared/modRefBarrierSetAssembler_mips.hpp b/src/hotspot/cpu/mips/gc/shared/modRefBarrierSetAssembler_mips.hpp ---- a/src/hotspot/cpu/mips/gc/shared/modRefBarrierSetAssembler_mips.hpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/cpu/mips/gc/shared/modRefBarrierSetAssembler_mips.hpp 2024-01-30 10:00:11.844765024 +0800 +diff --git a/src/hotspot/cpu/mips/gc/shared/modRefBarrierSetAssembler_mips.hpp b/src/hotspot/cpu/mips/gc/shared/modRefBarrierSetAssembler_mips.hpp +new file mode 100644 +index 0000000000..5320a4c0ad +--- /dev/null ++++ b/src/hotspot/cpu/mips/gc/shared/modRefBarrierSetAssembler_mips.hpp @@ -0,0 +1,54 @@ +/* + * Copyright (c) 2018, Oracle and/or its affiliates. All rights reserved. @@ -64479,9 +64708,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h +}; + +#endif // CPU_MIPS_GC_SHARED_MODREFBARRIERSETASSEMBLER_MIPS_HPP -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/mips/globalDefinitions_mips.hpp b/src/hotspot/cpu/mips/globalDefinitions_mips.hpp ---- a/src/hotspot/cpu/mips/globalDefinitions_mips.hpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/cpu/mips/globalDefinitions_mips.hpp 2024-01-30 10:00:11.844765024 +0800 +diff --git a/src/hotspot/cpu/mips/globalDefinitions_mips.hpp b/src/hotspot/cpu/mips/globalDefinitions_mips.hpp +new file mode 100644 +index 0000000000..abf8141e8b +--- /dev/null ++++ b/src/hotspot/cpu/mips/globalDefinitions_mips.hpp @@ -0,0 +1,45 @@ +/* + * Copyright (c) 1999, 2013, Oracle and/or its affiliates. All rights reserved. @@ -64528,9 +64759,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h +#define THREAD_LOCAL_POLL + +#endif // CPU_MIPS_VM_GLOBALDEFINITIONS_MIPS_HPP -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/mips/globals_mips.hpp b/src/hotspot/cpu/mips/globals_mips.hpp ---- a/src/hotspot/cpu/mips/globals_mips.hpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/cpu/mips/globals_mips.hpp 2024-01-30 10:00:11.844765024 +0800 +diff --git a/src/hotspot/cpu/mips/globals_mips.hpp b/src/hotspot/cpu/mips/globals_mips.hpp +new file mode 100644 +index 0000000000..3bcad005d1 +--- /dev/null ++++ b/src/hotspot/cpu/mips/globals_mips.hpp @@ -0,0 +1,137 @@ +/* + * Copyright (c) 2000, 2013, Oracle and/or its affiliates. All rights reserved. @@ -64669,9 +64902,105 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h + "Eliminate barriers for single active cpu") + +#endif // CPU_MIPS_VM_GLOBALS_MIPS_HPP -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/mips/icache_mips.cpp b/src/hotspot/cpu/mips/icache_mips.cpp ---- a/src/hotspot/cpu/mips/icache_mips.cpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/cpu/mips/icache_mips.cpp 2024-01-30 10:00:11.844765024 +0800 +diff --git a/src/hotspot/cpu/mips/icBuffer_mips.cpp b/src/hotspot/cpu/mips/icBuffer_mips.cpp +new file mode 100644 +index 0000000000..6586c63965 +--- /dev/null ++++ b/src/hotspot/cpu/mips/icBuffer_mips.cpp +@@ -0,0 +1,88 @@ ++/* ++ * Copyright (c) 1997, 2012, Oracle and/or its affiliates. All rights reserved. ++ * Copyright (c) 2015, 2022, Loongson Technology. All rights reserved. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ * ++ */ ++ ++#include "precompiled.hpp" ++#include "asm/macroAssembler.hpp" ++#include "asm/macroAssembler.inline.hpp" ++#include "code/icBuffer.hpp" ++#include "gc/shared/collectedHeap.inline.hpp" ++#include "interpreter/bytecodes.hpp" ++#include "memory/resourceArea.hpp" ++#include "nativeInst_mips.hpp" ++#include "oops/oop.inline.hpp" ++ ++#define T0 RT0 ++#define T1 RT1 ++#define T2 RT2 ++#define T3 RT3 ++#define T8 RT8 ++#define T9 RT9 ++ ++int InlineCacheBuffer::ic_stub_code_size() { ++ return NativeMovConstReg::instruction_size + ++ NativeGeneralJump::instruction_size + ++ 1; ++ // so that code_end can be set in CodeBuffer ++ // 64bit 15 = 6 + 8 bytes + 1 byte ++ // 32bit 7 = 2 + 4 bytes + 1 byte ++} ++ ++ ++// we use T1 as cached oop(klass) now. this is the target of virtual call, ++// when reach here, the receiver in T0 ++// refer to shareRuntime_mips.cpp,gen_i2c2i_adapters ++void InlineCacheBuffer::assemble_ic_buffer_code(address code_begin, void* cached_value, address entry_point) { ++ ResourceMark rm; ++ CodeBuffer code(code_begin, ic_stub_code_size()); ++ MacroAssembler* masm = new MacroAssembler(&code); ++ // note: even though the code contains an embedded oop, we do not need reloc info ++ // because ++ // (1) the oop is old (i.e., doesn't matter for scavenges) ++ // (2) these ICStubs are removed *before* a GC happens, so the roots disappear ++// assert(cached_oop == NULL || cached_oop->is_perm(), "must be perm oop"); ++#define __ masm-> ++ __ patchable_set48(T1, (long)cached_value); ++ ++ __ patchable_jump(entry_point); ++ __ flush(); ++#undef __ ++} ++ ++ ++address InlineCacheBuffer::ic_buffer_entry_point(address code_begin) { ++ NativeMovConstReg* move = nativeMovConstReg_at(code_begin); // creation also verifies the object ++ NativeGeneralJump* jump = nativeGeneralJump_at(move->next_instruction_address()); ++ return jump->jump_destination(); ++} ++ ++ ++void* InlineCacheBuffer::ic_buffer_cached_value(address code_begin) { ++ // creation also verifies the object ++ NativeMovConstReg* move = nativeMovConstReg_at(code_begin); ++ // Verifies the jump ++ NativeGeneralJump* jump = nativeGeneralJump_at(move->next_instruction_address()); ++ void* o= (void*)move->data(); ++ return o; ++} +diff --git a/src/hotspot/cpu/mips/icache_mips.cpp b/src/hotspot/cpu/mips/icache_mips.cpp +new file mode 100644 +index 0000000000..e84e37358b +--- /dev/null ++++ b/src/hotspot/cpu/mips/icache_mips.cpp @@ -0,0 +1,41 @@ +/* + * Copyright (c) 1997, 2010, Oracle and/or its affiliates. All rights reserved. @@ -64714,9 +65043,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h + *flush_icache_stub = (ICache::flush_icache_stub_t)start; +#undef __ +} -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/mips/icache_mips.hpp b/src/hotspot/cpu/mips/icache_mips.hpp ---- a/src/hotspot/cpu/mips/icache_mips.hpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/cpu/mips/icache_mips.hpp 2024-01-30 10:00:11.844765024 +0800 +diff --git a/src/hotspot/cpu/mips/icache_mips.hpp b/src/hotspot/cpu/mips/icache_mips.hpp +new file mode 100644 +index 0000000000..f90dee6eef +--- /dev/null ++++ b/src/hotspot/cpu/mips/icache_mips.hpp @@ -0,0 +1,41 @@ +/* + * Copyright (c) 1997, 2010, Oracle and/or its affiliates. All rights reserved. @@ -64759,13 +65090,15 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h +}; + +#endif // CPU_MIPS_VM_ICACHE_MIPS_HPP -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/mips/icBuffer_mips.cpp b/src/hotspot/cpu/mips/icBuffer_mips.cpp ---- a/src/hotspot/cpu/mips/icBuffer_mips.cpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/cpu/mips/icBuffer_mips.cpp 2024-01-30 10:00:11.844765024 +0800 -@@ -0,0 +1,88 @@ +diff --git a/src/hotspot/cpu/mips/interp_masm_mips.hpp b/src/hotspot/cpu/mips/interp_masm_mips.hpp +new file mode 100644 +index 0000000000..e526e39d53 +--- /dev/null ++++ b/src/hotspot/cpu/mips/interp_masm_mips.hpp +@@ -0,0 +1,276 @@ +/* -+ * Copyright (c) 1997, 2012, Oracle and/or its affiliates. All rights reserved. -+ * Copyright (c) 2015, 2022, Loongson Technology. All rights reserved. ++ * Copyright (c) 2003, 2013, Oracle and/or its affiliates. All rights reserved. ++ * Copyright (c) 2015, 2020, Loongson Technology. All rights reserved. + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. + * + * This code is free software; you can redistribute it and/or modify it @@ -64788,72 +65121,262 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h + * + */ + -+#include "precompiled.hpp" ++#ifndef CPU_MIPS_VM_INTERP_MASM_MIPS_64_HPP ++#define CPU_MIPS_VM_INTERP_MASM_MIPS_64_HPP ++ ++#include "asm/assembler.hpp" +#include "asm/macroAssembler.hpp" +#include "asm/macroAssembler.inline.hpp" -+#include "code/icBuffer.hpp" -+#include "gc/shared/collectedHeap.inline.hpp" -+#include "interpreter/bytecodes.hpp" -+#include "memory/resourceArea.hpp" -+#include "nativeInst_mips.hpp" -+#include "oops/oop.inline.hpp" ++#include "interpreter/invocationCounter.hpp" ++#include "runtime/frame.hpp" + -+#define T0 RT0 -+#define T1 RT1 -+#define T2 RT2 -+#define T3 RT3 -+#define T8 RT8 -+#define T9 RT9 ++// This file specializes the assember with interpreter-specific macros + -+int InlineCacheBuffer::ic_stub_code_size() { -+ return NativeMovConstReg::instruction_size + -+ NativeGeneralJump::instruction_size + -+ 1; -+ // so that code_end can be set in CodeBuffer -+ // 64bit 15 = 6 + 8 bytes + 1 byte -+ // 32bit 7 = 2 + 4 bytes + 1 byte -+} + ++class InterpreterMacroAssembler: public MacroAssembler { ++#ifndef CC_INTERP ++ private: + -+// we use T1 as cached oop(klass) now. this is the target of virtual call, -+// when reach here, the receiver in T0 -+// refer to shareRuntime_mips.cpp,gen_i2c2i_adapters -+void InlineCacheBuffer::assemble_ic_buffer_code(address code_begin, void* cached_value, address entry_point) { -+ ResourceMark rm; -+ CodeBuffer code(code_begin, ic_stub_code_size()); -+ MacroAssembler* masm = new MacroAssembler(&code); -+ // note: even though the code contains an embedded oop, we do not need reloc info -+ // because -+ // (1) the oop is old (i.e., doesn't matter for scavenges) -+ // (2) these ICStubs are removed *before* a GC happens, so the roots disappear -+// assert(cached_oop == NULL || cached_oop->is_perm(), "must be perm oop"); -+#define __ masm-> -+ __ patchable_set48(T1, (long)cached_value); ++ Register _locals_register; // register that contains the pointer to the locals ++ Register _bcp_register; // register that contains the bcp + -+ __ patchable_jump(entry_point); -+ __ flush(); -+#undef __ -+} ++ protected: ++ // Interpreter specific version of call_VM_base ++ virtual void call_VM_leaf_base(address entry_point, ++ int number_of_arguments); + ++ virtual void call_VM_base(Register oop_result, ++ Register java_thread, ++ Register last_java_sp, ++ address entry_point, ++ int number_of_arguments, ++ bool check_exceptions); + -+address InlineCacheBuffer::ic_buffer_entry_point(address code_begin) { -+ NativeMovConstReg* move = nativeMovConstReg_at(code_begin); // creation also verifies the object -+ NativeGeneralJump* jump = nativeGeneralJump_at(move->next_instruction_address()); -+ return jump->jump_destination(); -+} ++ // base routine for all dispatches ++ void dispatch_base(TosState state, address* table, bool verifyoop = true, bool generate_poll = false); ++#endif // CC_INTERP + ++ public: ++ void jump_to_entry(address entry); ++ // narrow int return value ++ void narrow(Register result); + -+void* InlineCacheBuffer::ic_buffer_cached_value(address code_begin) { -+ // creation also verifies the object -+ NativeMovConstReg* move = nativeMovConstReg_at(code_begin); -+ // Verifies the jump -+ NativeGeneralJump* jump = nativeGeneralJump_at(move->next_instruction_address()); -+ void* o= (void*)move->data(); -+ return o; -+} -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/mips/interp_masm_mips_64.cpp b/src/hotspot/cpu/mips/interp_masm_mips_64.cpp ---- a/src/hotspot/cpu/mips/interp_masm_mips_64.cpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/cpu/mips/interp_masm_mips_64.cpp 2024-01-30 10:00:11.844765024 +0800 ++ InterpreterMacroAssembler(CodeBuffer* code) : MacroAssembler(code), _locals_register(LVP), _bcp_register(BCP) {} ++ ++ void get_2_byte_integer_at_bcp(Register reg, Register tmp, int offset); ++ void get_4_byte_integer_at_bcp(Register reg, Register tmp, int offset); ++ ++ virtual void check_and_handle_popframe(Register java_thread); ++ virtual void check_and_handle_earlyret(Register java_thread); ++ ++ void load_earlyret_value(TosState state); ++ ++#ifdef CC_INTERP ++ void save_bcp() { /* not needed in c++ interpreter and harmless */ } ++ void restore_bcp() { /* not needed in c++ interpreter and harmless */ } ++ ++ // Helpers for runtime call arguments/results ++ void get_method(Register reg); ++ ++#else ++ ++ // Interpreter-specific registers ++ void save_bcp() { ++ sd(BCP, FP, frame::interpreter_frame_bcp_offset * wordSize); ++ } ++ ++ void restore_bcp() { ++ ld(BCP, FP, frame::interpreter_frame_bcp_offset * wordSize); ++ } ++ ++ void restore_locals() { ++ ld(LVP, FP, frame::interpreter_frame_locals_offset * wordSize); ++ } ++ ++ // Helpers for runtime call arguments/results ++ void get_method(Register reg) { ++ ld(reg, FP, frame::interpreter_frame_method_offset * wordSize); ++ } ++ ++ void get_const(Register reg){ ++ get_method(reg); ++ ld(reg, reg, in_bytes(Method::const_offset())); ++ } ++ ++ void get_constant_pool(Register reg) { ++ get_const(reg); ++ ld(reg, reg, in_bytes(ConstMethod::constants_offset())); ++ } ++ ++ void get_constant_pool_cache(Register reg) { ++ get_constant_pool(reg); ++ ld(reg, reg, ConstantPool::cache_offset_in_bytes()); ++ } ++ ++ void get_cpool_and_tags(Register cpool, Register tags) { ++ get_constant_pool(cpool); ++ ld(tags, cpool, ConstantPool::tags_offset_in_bytes()); ++ } ++ ++ void get_unsigned_2_byte_index_at_bcp(Register reg, int bcp_offset); ++ void get_cache_and_index_at_bcp(Register cache, Register index, int bcp_offset, size_t index_size = sizeof(u2)); ++ void get_cache_and_index_and_bytecode_at_bcp(Register cache, Register index, Register bytecode, int byte_no, int bcp_offset, size_t index_size = sizeof(u2)); ++ void get_cache_entry_pointer_at_bcp(Register cache, Register tmp, int bcp_offset, size_t index_size = sizeof(u2)); ++ void get_cache_index_at_bcp(Register index, int bcp_offset, size_t index_size = sizeof(u2)); ++ void get_method_counters(Register method, Register mcs, Label& skip); ++ ++ // load cpool->resolved_references(index); ++ void load_resolved_reference_at_index(Register result, Register index, Register tmp); ++ ++ // load cpool->resolved_klass_at(index) ++ void load_resolved_klass_at_index(Register cpool, // the constant pool (corrupted on return) ++ Register index, // the constant pool index (corrupted on return) ++ Register klass); // contains the Klass on return ++ ++ void pop_ptr( Register r = FSR); ++ void pop_i( Register r = FSR); ++ void pop_l( Register r = FSR); ++ void pop_f(FloatRegister r = FSF); ++ void pop_d(FloatRegister r = FSF); ++ ++ void push_ptr( Register r = FSR); ++ void push_i( Register r = FSR); ++ void push_l( Register r = FSR); ++ void push_f(FloatRegister r = FSF); ++ void push_d(FloatRegister r = FSF); ++ ++ void pop(Register r ) { ((MacroAssembler*)this)->pop(r); } ++ ++ void push(Register r ) { ((MacroAssembler*)this)->push(r); } ++ ++ void pop(TosState state); // transition vtos -> state ++ void push(TosState state); // transition state -> vtos ++ ++ void empty_expression_stack() { ++ ld(SP, FP, frame::interpreter_frame_monitor_block_top_offset * wordSize); ++ // NULL last_sp until next java call ++ sd(R0, FP, frame::interpreter_frame_last_sp_offset * wordSize); ++ } ++ ++ // Super call_VM calls - correspond to MacroAssembler::call_VM(_leaf) calls ++ void load_ptr(int n, Register val); ++ void store_ptr(int n, Register val); ++ ++ // Generate a subtype check: branch to ok_is_subtype if sub_klass is ++ // a subtype of super_klass. ++ //void gen_subtype_check( Register sub_klass, Label &ok_is_subtype ); ++ void gen_subtype_check( Register Rsup_klass, Register sub_klass, Label &ok_is_subtype ); ++ ++ // Dispatching ++ void dispatch_prolog(TosState state, int step = 0); ++ void dispatch_epilog(TosState state, int step = 0); ++ void dispatch_only(TosState state, bool generate_poll = false); ++ void dispatch_only_normal(TosState state); ++ void dispatch_only_noverify(TosState state); ++ void dispatch_next(TosState state, int step = 0, bool generate_poll = false); ++ void dispatch_via (TosState state, address* table); ++ ++ // jump to an invoked target ++ void prepare_to_jump_from_interpreted(); ++ void jump_from_interpreted(Register method, Register temp); ++ ++ ++ // Returning from interpreted functions ++ // ++ // Removes the current activation (incl. unlocking of monitors) ++ // and sets up the return address. This code is also used for ++ // exception unwindwing. In that case, we do not want to throw ++ // IllegalMonitorStateExceptions, since that might get us into an ++ // infinite rethrow exception loop. ++ // Additionally this code is used for popFrame and earlyReturn. ++ // In popFrame case we want to skip throwing an exception, ++ // installing an exception, and notifying jvmdi. ++ // In earlyReturn case we only want to skip throwing an exception ++ // and installing an exception. ++ void remove_activation(TosState state, Register ret_addr, ++ bool throw_monitor_exception = true, ++ bool install_monitor_exception = true, ++ bool notify_jvmdi = true); ++#endif // CC_INTERP ++ ++ // Object locking ++ void lock_object (Register lock_reg); ++ void unlock_object(Register lock_reg); ++ ++#ifndef CC_INTERP ++ ++ // Interpreter profiling operations ++ void set_method_data_pointer_for_bcp(); ++ void test_method_data_pointer(Register mdp, Label& zero_continue); ++ void verify_method_data_pointer(); ++ ++ void set_mdp_data_at(Register mdp_in, int constant, Register value); ++ void increment_mdp_data_at(Address data, bool decrement = false); ++ void increment_mdp_data_at(Register mdp_in, int constant, ++ bool decrement = false); ++ void increment_mdp_data_at(Register mdp_in, Register reg, int constant, ++ bool decrement = false); ++ void increment_mask_and_jump(Address counter_addr, ++ int increment, int mask, ++ Register scratch, bool preloaded, ++ Condition cond, Label* where); ++ void set_mdp_flag_at(Register mdp_in, int flag_constant); ++ void test_mdp_data_at(Register mdp_in, int offset, Register value, ++ Register test_value_out, ++ Label& not_equal_continue); ++ ++ void record_klass_in_profile(Register receiver, Register mdp, ++ Register reg2, bool is_virtual_call); ++ void record_klass_in_profile_helper(Register receiver, Register mdp, ++ Register reg2, int start_row, ++ Label& done, bool is_virtual_call); ++ ++ void update_mdp_by_offset(Register mdp_in, int offset_of_offset); ++ void update_mdp_by_offset(Register mdp_in, Register reg, int offset_of_disp); ++ void update_mdp_by_constant(Register mdp_in, int constant); ++ void update_mdp_for_ret(Register return_bci); ++ ++ void profile_taken_branch(Register mdp, Register bumped_count); ++ void profile_not_taken_branch(Register mdp); ++ void profile_call(Register mdp); ++ void profile_final_call(Register mdp); ++ void profile_virtual_call(Register receiver, Register mdp, ++ Register scratch2, ++ bool receiver_can_be_null = false); ++ void profile_called_method(Register method, Register mdp, Register reg2) NOT_JVMCI_RETURN; ++ void profile_ret(Register return_bci, Register mdp); ++ void profile_null_seen(Register mdp); ++ void profile_typecheck(Register mdp, Register klass, Register scratch); ++ void profile_typecheck_failed(Register mdp); ++ void profile_switch_default(Register mdp); ++ void profile_switch_case(Register index_in_scratch, Register mdp, ++ Register scratch2); ++ ++ // Debugging ++ // only if +VerifyOops && state == atos ++ void verify_oop(Register reg, TosState state = atos); ++ // only if +VerifyFPU && (state == ftos || state == dtos) ++ void verify_FPU(int stack_depth, TosState state = ftos); ++ ++ void profile_obj_type(Register obj, const Address& mdo_addr); ++ void profile_arguments_type(Register mdp, Register callee, Register tmp, bool is_virtual); ++ void profile_return_type(Register mdp, Register ret, Register tmp); ++ void profile_parameters_type(Register mdp, Register tmp1, Register tmp2); ++#endif // !CC_INTERP ++ ++ typedef enum { NotifyJVMTI, SkipNotifyJVMTI } NotifyMethodExitMode; ++ ++ // support for jvmti/dtrace ++ void notify_method_entry(); ++ void notify_method_exit(TosState state, NotifyMethodExitMode mode); ++}; ++ ++#endif // CPU_MIPS_VM_INTERP_MASM_MIPS_64_HPP +diff --git a/src/hotspot/cpu/mips/interp_masm_mips_64.cpp b/src/hotspot/cpu/mips/interp_masm_mips_64.cpp +new file mode 100644 +index 0000000000..eb35bb0633 +--- /dev/null ++++ b/src/hotspot/cpu/mips/interp_masm_mips_64.cpp @@ -0,0 +1,2126 @@ +/* + * Copyright (c) 2003, 2013, Oracle and/or its affiliates. All rights reserved. @@ -66981,13 +67504,15 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h + unimplemented(); + } +} -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/mips/interp_masm_mips.hpp b/src/hotspot/cpu/mips/interp_masm_mips.hpp ---- a/src/hotspot/cpu/mips/interp_masm_mips.hpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/cpu/mips/interp_masm_mips.hpp 2024-01-30 10:00:11.844765024 +0800 -@@ -0,0 +1,276 @@ +diff --git a/src/hotspot/cpu/mips/interpreterRT_mips.hpp b/src/hotspot/cpu/mips/interpreterRT_mips.hpp +new file mode 100644 +index 0000000000..054138ea42 +--- /dev/null ++++ b/src/hotspot/cpu/mips/interpreterRT_mips.hpp +@@ -0,0 +1,60 @@ +/* -+ * Copyright (c) 2003, 2013, Oracle and/or its affiliates. All rights reserved. -+ * Copyright (c) 2015, 2020, Loongson Technology. All rights reserved. ++ * Copyright (c) 1998, 2010, Oracle and/or its affiliates. All rights reserved. ++ * Copyright (c) 2015, 2022, Loongson Technology. All rights reserved. + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. + * + * This code is free software; you can redistribute it and/or modify it @@ -67010,260 +67535,46 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h + * + */ + -+#ifndef CPU_MIPS_VM_INTERP_MASM_MIPS_64_HPP -+#define CPU_MIPS_VM_INTERP_MASM_MIPS_64_HPP -+ -+#include "asm/assembler.hpp" -+#include "asm/macroAssembler.hpp" -+#include "asm/macroAssembler.inline.hpp" -+#include "interpreter/invocationCounter.hpp" -+#include "runtime/frame.hpp" ++#ifndef CPU_MIPS_VM_INTERPRETERRT_MIPS_HPP ++#define CPU_MIPS_VM_INTERPRETERRT_MIPS_HPP + -+// This file specializes the assember with interpreter-specific macros ++// This is included in the middle of class Interpreter. ++// Do not include files here. + ++// native method calls + -+class InterpreterMacroAssembler: public MacroAssembler { -+#ifndef CC_INTERP ++class SignatureHandlerGenerator: public NativeSignatureIterator { + private: ++ MacroAssembler* _masm; + -+ Register _locals_register; // register that contains the pointer to the locals -+ Register _bcp_register; // register that contains the bcp -+ -+ protected: -+ // Interpreter specific version of call_VM_base -+ virtual void call_VM_leaf_base(address entry_point, -+ int number_of_arguments); -+ -+ virtual void call_VM_base(Register oop_result, -+ Register java_thread, -+ Register last_java_sp, -+ address entry_point, -+ int number_of_arguments, -+ bool check_exceptions); ++ void move(int from_offset, int to_offset); + -+ // base routine for all dispatches -+ void dispatch_base(TosState state, address* table, bool verifyoop = true, bool generate_poll = false); -+#endif // CC_INTERP ++ void box(int from_offset, int to_offset); ++ void pass_int(); ++ void pass_long(); ++ void pass_object(); ++ void pass_float(); ++ void pass_double(); + + public: -+ void jump_to_entry(address entry); -+ // narrow int return value -+ void narrow(Register result); -+ -+ InterpreterMacroAssembler(CodeBuffer* code) : MacroAssembler(code), _locals_register(LVP), _bcp_register(BCP) {} -+ -+ void get_2_byte_integer_at_bcp(Register reg, Register tmp, int offset); -+ void get_4_byte_integer_at_bcp(Register reg, Register tmp, int offset); -+ -+ virtual void check_and_handle_popframe(Register java_thread); -+ virtual void check_and_handle_earlyret(Register java_thread); -+ -+ void load_earlyret_value(TosState state); -+ -+#ifdef CC_INTERP -+ void save_bcp() { /* not needed in c++ interpreter and harmless */ } -+ void restore_bcp() { /* not needed in c++ interpreter and harmless */ } -+ -+ // Helpers for runtime call arguments/results -+ void get_method(Register reg); -+ -+#else -+ -+ // Interpreter-specific registers -+ void save_bcp() { -+ sd(BCP, FP, frame::interpreter_frame_bcp_offset * wordSize); -+ } -+ -+ void restore_bcp() { -+ ld(BCP, FP, frame::interpreter_frame_bcp_offset * wordSize); -+ } -+ -+ void restore_locals() { -+ ld(LVP, FP, frame::interpreter_frame_locals_offset * wordSize); -+ } -+ -+ // Helpers for runtime call arguments/results -+ void get_method(Register reg) { -+ ld(reg, FP, frame::interpreter_frame_method_offset * wordSize); -+ } -+ -+ void get_const(Register reg){ -+ get_method(reg); -+ ld(reg, reg, in_bytes(Method::const_offset())); -+ } -+ -+ void get_constant_pool(Register reg) { -+ get_const(reg); -+ ld(reg, reg, in_bytes(ConstMethod::constants_offset())); -+ } -+ -+ void get_constant_pool_cache(Register reg) { -+ get_constant_pool(reg); -+ ld(reg, reg, ConstantPool::cache_offset_in_bytes()); -+ } -+ -+ void get_cpool_and_tags(Register cpool, Register tags) { -+ get_constant_pool(cpool); -+ ld(tags, cpool, ConstantPool::tags_offset_in_bytes()); -+ } -+ -+ void get_unsigned_2_byte_index_at_bcp(Register reg, int bcp_offset); -+ void get_cache_and_index_at_bcp(Register cache, Register index, int bcp_offset, size_t index_size = sizeof(u2)); -+ void get_cache_and_index_and_bytecode_at_bcp(Register cache, Register index, Register bytecode, int byte_no, int bcp_offset, size_t index_size = sizeof(u2)); -+ void get_cache_entry_pointer_at_bcp(Register cache, Register tmp, int bcp_offset, size_t index_size = sizeof(u2)); -+ void get_cache_index_at_bcp(Register index, int bcp_offset, size_t index_size = sizeof(u2)); -+ void get_method_counters(Register method, Register mcs, Label& skip); -+ -+ // load cpool->resolved_references(index); -+ void load_resolved_reference_at_index(Register result, Register index, Register tmp); -+ -+ // load cpool->resolved_klass_at(index) -+ void load_resolved_klass_at_index(Register cpool, // the constant pool (corrupted on return) -+ Register index, // the constant pool index (corrupted on return) -+ Register klass); // contains the Klass on return -+ -+ void pop_ptr( Register r = FSR); -+ void pop_i( Register r = FSR); -+ void pop_l( Register r = FSR); -+ void pop_f(FloatRegister r = FSF); -+ void pop_d(FloatRegister r = FSF); -+ -+ void push_ptr( Register r = FSR); -+ void push_i( Register r = FSR); -+ void push_l( Register r = FSR); -+ void push_f(FloatRegister r = FSF); -+ void push_d(FloatRegister r = FSF); -+ -+ void pop(Register r ) { ((MacroAssembler*)this)->pop(r); } -+ -+ void push(Register r ) { ((MacroAssembler*)this)->push(r); } -+ -+ void pop(TosState state); // transition vtos -> state -+ void push(TosState state); // transition state -> vtos -+ -+ void empty_expression_stack() { -+ ld(SP, FP, frame::interpreter_frame_monitor_block_top_offset * wordSize); -+ // NULL last_sp until next java call -+ sd(R0, FP, frame::interpreter_frame_last_sp_offset * wordSize); -+ } -+ -+ // Super call_VM calls - correspond to MacroAssembler::call_VM(_leaf) calls -+ void load_ptr(int n, Register val); -+ void store_ptr(int n, Register val); -+ -+ // Generate a subtype check: branch to ok_is_subtype if sub_klass is -+ // a subtype of super_klass. -+ //void gen_subtype_check( Register sub_klass, Label &ok_is_subtype ); -+ void gen_subtype_check( Register Rsup_klass, Register sub_klass, Label &ok_is_subtype ); -+ -+ // Dispatching -+ void dispatch_prolog(TosState state, int step = 0); -+ void dispatch_epilog(TosState state, int step = 0); -+ void dispatch_only(TosState state, bool generate_poll = false); -+ void dispatch_only_normal(TosState state); -+ void dispatch_only_noverify(TosState state); -+ void dispatch_next(TosState state, int step = 0, bool generate_poll = false); -+ void dispatch_via (TosState state, address* table); -+ -+ // jump to an invoked target -+ void prepare_to_jump_from_interpreted(); -+ void jump_from_interpreted(Register method, Register temp); -+ -+ -+ // Returning from interpreted functions -+ // -+ // Removes the current activation (incl. unlocking of monitors) -+ // and sets up the return address. This code is also used for -+ // exception unwindwing. In that case, we do not want to throw -+ // IllegalMonitorStateExceptions, since that might get us into an -+ // infinite rethrow exception loop. -+ // Additionally this code is used for popFrame and earlyReturn. -+ // In popFrame case we want to skip throwing an exception, -+ // installing an exception, and notifying jvmdi. -+ // In earlyReturn case we only want to skip throwing an exception -+ // and installing an exception. -+ void remove_activation(TosState state, Register ret_addr, -+ bool throw_monitor_exception = true, -+ bool install_monitor_exception = true, -+ bool notify_jvmdi = true); -+#endif // CC_INTERP -+ -+ // Object locking -+ void lock_object (Register lock_reg); -+ void unlock_object(Register lock_reg); -+ -+#ifndef CC_INTERP -+ -+ // Interpreter profiling operations -+ void set_method_data_pointer_for_bcp(); -+ void test_method_data_pointer(Register mdp, Label& zero_continue); -+ void verify_method_data_pointer(); -+ -+ void set_mdp_data_at(Register mdp_in, int constant, Register value); -+ void increment_mdp_data_at(Address data, bool decrement = false); -+ void increment_mdp_data_at(Register mdp_in, int constant, -+ bool decrement = false); -+ void increment_mdp_data_at(Register mdp_in, Register reg, int constant, -+ bool decrement = false); -+ void increment_mask_and_jump(Address counter_addr, -+ int increment, int mask, -+ Register scratch, bool preloaded, -+ Condition cond, Label* where); -+ void set_mdp_flag_at(Register mdp_in, int flag_constant); -+ void test_mdp_data_at(Register mdp_in, int offset, Register value, -+ Register test_value_out, -+ Label& not_equal_continue); -+ -+ void record_klass_in_profile(Register receiver, Register mdp, -+ Register reg2, bool is_virtual_call); -+ void record_klass_in_profile_helper(Register receiver, Register mdp, -+ Register reg2, int start_row, -+ Label& done, bool is_virtual_call); -+ -+ void update_mdp_by_offset(Register mdp_in, int offset_of_offset); -+ void update_mdp_by_offset(Register mdp_in, Register reg, int offset_of_disp); -+ void update_mdp_by_constant(Register mdp_in, int constant); -+ void update_mdp_for_ret(Register return_bci); -+ -+ void profile_taken_branch(Register mdp, Register bumped_count); -+ void profile_not_taken_branch(Register mdp); -+ void profile_call(Register mdp); -+ void profile_final_call(Register mdp); -+ void profile_virtual_call(Register receiver, Register mdp, -+ Register scratch2, -+ bool receiver_can_be_null = false); -+ void profile_called_method(Register method, Register mdp, Register reg2) NOT_JVMCI_RETURN; -+ void profile_ret(Register return_bci, Register mdp); -+ void profile_null_seen(Register mdp); -+ void profile_typecheck(Register mdp, Register klass, Register scratch); -+ void profile_typecheck_failed(Register mdp); -+ void profile_switch_default(Register mdp); -+ void profile_switch_case(Register index_in_scratch, Register mdp, -+ Register scratch2); -+ -+ // Debugging -+ // only if +VerifyOops && state == atos -+ void verify_oop(Register reg, TosState state = atos); -+ // only if +VerifyFPU && (state == ftos || state == dtos) -+ void verify_FPU(int stack_depth, TosState state = ftos); -+ -+ void profile_obj_type(Register obj, const Address& mdo_addr); -+ void profile_arguments_type(Register mdp, Register callee, Register tmp, bool is_virtual); -+ void profile_return_type(Register mdp, Register ret, Register tmp); -+ void profile_parameters_type(Register mdp, Register tmp1, Register tmp2); -+#endif // !CC_INTERP ++ // Creation ++ SignatureHandlerGenerator(const methodHandle& method, CodeBuffer* buffer); + -+ typedef enum { NotifyJVMTI, SkipNotifyJVMTI } NotifyMethodExitMode; ++ // Code generation ++ void generate(uint64_t fingerprint); + -+ // support for jvmti/dtrace -+ void notify_method_entry(); -+ void notify_method_exit(TosState state, NotifyMethodExitMode mode); ++ // Code generation support ++ static Register from(); ++ static Register to(); ++ static Register temp(); +}; + -+#endif // CPU_MIPS_VM_INTERP_MASM_MIPS_64_HPP -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/mips/interpreterRT_mips_64.cpp b/src/hotspot/cpu/mips/interpreterRT_mips_64.cpp ---- a/src/hotspot/cpu/mips/interpreterRT_mips_64.cpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/cpu/mips/interpreterRT_mips_64.cpp 2024-01-30 10:00:11.844765024 +0800 ++#endif // CPU_MIPS_VM_INTERPRETERRT_MIPS_HPP +diff --git a/src/hotspot/cpu/mips/interpreterRT_mips_64.cpp b/src/hotspot/cpu/mips/interpreterRT_mips_64.cpp +new file mode 100644 +index 0000000000..e655b2a1a8 +--- /dev/null ++++ b/src/hotspot/cpu/mips/interpreterRT_mips_64.cpp @@ -0,0 +1,252 @@ +/* + * Copyright (c) 2003, 2012, Oracle and/or its affiliates. All rights reserved. @@ -67517,73 +67828,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h + // return result handler + return Interpreter::result_handler(m->result_type()); +IRT_END -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/mips/interpreterRT_mips.hpp b/src/hotspot/cpu/mips/interpreterRT_mips.hpp ---- a/src/hotspot/cpu/mips/interpreterRT_mips.hpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/cpu/mips/interpreterRT_mips.hpp 2024-01-30 10:00:11.844765024 +0800 -@@ -0,0 +1,60 @@ -+/* -+ * Copyright (c) 1998, 2010, Oracle and/or its affiliates. All rights reserved. -+ * Copyright (c) 2015, 2022, Loongson Technology. All rights reserved. -+ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. -+ * -+ * This code is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 only, as -+ * published by the Free Software Foundation. -+ * -+ * This code is distributed in the hope that it will be useful, but WITHOUT -+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -+ * version 2 for more details (a copy is included in the LICENSE file that -+ * accompanied this code). -+ * -+ * You should have received a copy of the GNU General Public License version -+ * 2 along with this work; if not, write to the Free Software Foundation, -+ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. -+ * -+ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA -+ * or visit www.oracle.com if you need additional information or have any -+ * questions. -+ * -+ */ -+ -+#ifndef CPU_MIPS_VM_INTERPRETERRT_MIPS_HPP -+#define CPU_MIPS_VM_INTERPRETERRT_MIPS_HPP -+ -+// This is included in the middle of class Interpreter. -+// Do not include files here. -+ -+// native method calls -+ -+class SignatureHandlerGenerator: public NativeSignatureIterator { -+ private: -+ MacroAssembler* _masm; -+ -+ void move(int from_offset, int to_offset); -+ -+ void box(int from_offset, int to_offset); -+ void pass_int(); -+ void pass_long(); -+ void pass_object(); -+ void pass_float(); -+ void pass_double(); -+ -+ public: -+ // Creation -+ SignatureHandlerGenerator(const methodHandle& method, CodeBuffer* buffer); -+ -+ // Code generation -+ void generate(uint64_t fingerprint); -+ -+ // Code generation support -+ static Register from(); -+ static Register to(); -+ static Register temp(); -+}; -+ -+#endif // CPU_MIPS_VM_INTERPRETERRT_MIPS_HPP -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/mips/javaFrameAnchor_mips.hpp b/src/hotspot/cpu/mips/javaFrameAnchor_mips.hpp ---- a/src/hotspot/cpu/mips/javaFrameAnchor_mips.hpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/cpu/mips/javaFrameAnchor_mips.hpp 2024-01-30 10:00:11.844765024 +0800 +diff --git a/src/hotspot/cpu/mips/javaFrameAnchor_mips.hpp b/src/hotspot/cpu/mips/javaFrameAnchor_mips.hpp +new file mode 100644 +index 0000000000..dccdf6a019 +--- /dev/null ++++ b/src/hotspot/cpu/mips/javaFrameAnchor_mips.hpp @@ -0,0 +1,87 @@ +/* + * Copyright (c) 2002, 2010, Oracle and/or its affiliates. All rights reserved. @@ -67672,9 +67921,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h + void set_last_Java_fp(intptr_t* fp) { _last_Java_fp = fp; } + +#endif // CPU_MIPS_VM_JAVAFRAMEANCHOR_MIPS_HPP -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/mips/jniFastGetField_mips_64.cpp b/src/hotspot/cpu/mips/jniFastGetField_mips_64.cpp ---- a/src/hotspot/cpu/mips/jniFastGetField_mips_64.cpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/cpu/mips/jniFastGetField_mips_64.cpp 2024-01-30 10:00:11.844765024 +0800 +diff --git a/src/hotspot/cpu/mips/jniFastGetField_mips_64.cpp b/src/hotspot/cpu/mips/jniFastGetField_mips_64.cpp +new file mode 100644 +index 0000000000..bba5b7eee8 +--- /dev/null ++++ b/src/hotspot/cpu/mips/jniFastGetField_mips_64.cpp @@ -0,0 +1,167 @@ +/* + * Copyright (c) 2004, 2010, Oracle and/or its affiliates. All rights reserved. @@ -67843,9 +68094,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h +address JNI_FastGetField::generate_fast_get_double_field() { + return generate_fast_get_int_field0(T_DOUBLE); +} -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/mips/jniTypes_mips.hpp b/src/hotspot/cpu/mips/jniTypes_mips.hpp ---- a/src/hotspot/cpu/mips/jniTypes_mips.hpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/cpu/mips/jniTypes_mips.hpp 2024-01-30 10:00:11.844765024 +0800 +diff --git a/src/hotspot/cpu/mips/jniTypes_mips.hpp b/src/hotspot/cpu/mips/jniTypes_mips.hpp +new file mode 100644 +index 0000000000..e93237ffd9 +--- /dev/null ++++ b/src/hotspot/cpu/mips/jniTypes_mips.hpp @@ -0,0 +1,144 @@ +/* + * Copyright (c) 1998, 2010, Oracle and/or its affiliates. All rights reserved. @@ -67991,9 +68244,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h +}; + +#endif // CPU_MIPS_VM_JNITYPES_MIPS_HPP -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/mips/macroAssembler_mips.cpp b/src/hotspot/cpu/mips/macroAssembler_mips.cpp ---- a/src/hotspot/cpu/mips/macroAssembler_mips.cpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/cpu/mips/macroAssembler_mips.cpp 2024-01-30 10:00:11.844765024 +0800 +diff --git a/src/hotspot/cpu/mips/macroAssembler_mips.cpp b/src/hotspot/cpu/mips/macroAssembler_mips.cpp +new file mode 100644 +index 0000000000..cc868cae55 +--- /dev/null ++++ b/src/hotspot/cpu/mips/macroAssembler_mips.cpp @@ -0,0 +1,4257 @@ +/* + * Copyright (c) 1997, 2014, Oracle and/or its affiliates. All rights reserved. @@ -72252,9 +72507,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h + ShouldNotReachHere(); + } +} -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/mips/macroAssembler_mips.hpp b/src/hotspot/cpu/mips/macroAssembler_mips.hpp ---- a/src/hotspot/cpu/mips/macroAssembler_mips.hpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/cpu/mips/macroAssembler_mips.hpp 2024-01-30 10:00:11.844765024 +0800 +diff --git a/src/hotspot/cpu/mips/macroAssembler_mips.hpp b/src/hotspot/cpu/mips/macroAssembler_mips.hpp +new file mode 100644 +index 0000000000..55ec29e91b +--- /dev/null ++++ b/src/hotspot/cpu/mips/macroAssembler_mips.hpp @@ -0,0 +1,818 @@ +/* + * Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved. @@ -73074,9 +73331,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h + + +#endif // CPU_MIPS_VM_MACROASSEMBLER_MIPS_HPP -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/mips/macroAssembler_mips.inline.hpp b/src/hotspot/cpu/mips/macroAssembler_mips.inline.hpp ---- a/src/hotspot/cpu/mips/macroAssembler_mips.inline.hpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/cpu/mips/macroAssembler_mips.inline.hpp 2024-01-30 10:00:11.844765024 +0800 +diff --git a/src/hotspot/cpu/mips/macroAssembler_mips.inline.hpp b/src/hotspot/cpu/mips/macroAssembler_mips.inline.hpp +new file mode 100644 +index 0000000000..92c05fb726 +--- /dev/null ++++ b/src/hotspot/cpu/mips/macroAssembler_mips.inline.hpp @@ -0,0 +1,34 @@ +/* + * Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved. @@ -73112,9 +73371,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h +#include "code/codeCache.hpp" + +#endif // CPU_MIPS_VM_MACROASSEMBLER_MIPS_INLINE_HPP -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/mips/methodHandles_mips.cpp b/src/hotspot/cpu/mips/methodHandles_mips.cpp ---- a/src/hotspot/cpu/mips/methodHandles_mips.cpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/cpu/mips/methodHandles_mips.cpp 2024-01-30 10:00:11.844765024 +0800 +diff --git a/src/hotspot/cpu/mips/methodHandles_mips.cpp b/src/hotspot/cpu/mips/methodHandles_mips.cpp +new file mode 100644 +index 0000000000..e9788ac52c +--- /dev/null ++++ b/src/hotspot/cpu/mips/methodHandles_mips.cpp @@ -0,0 +1,576 @@ +/* + * Copyright (c) 1997, 2014, Oracle and/or its affiliates. All rights reserved. @@ -73692,9 +73953,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h +void MethodHandles::trace_method_handle(MacroAssembler* _masm, const char* adaptername) { +} +#endif //PRODUCT -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/mips/methodHandles_mips.hpp b/src/hotspot/cpu/mips/methodHandles_mips.hpp ---- a/src/hotspot/cpu/mips/methodHandles_mips.hpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/cpu/mips/methodHandles_mips.hpp 2024-01-30 10:00:11.844765024 +0800 +diff --git a/src/hotspot/cpu/mips/methodHandles_mips.hpp b/src/hotspot/cpu/mips/methodHandles_mips.hpp +new file mode 100644 +index 0000000000..03b65fc8ef +--- /dev/null ++++ b/src/hotspot/cpu/mips/methodHandles_mips.hpp @@ -0,0 +1,62 @@ +/* + * Copyright (c) 2010, 2012, Oracle and/or its affiliates. All rights reserved. @@ -73758,9 +74021,42 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h + // Should be in sharedRuntime, not here. + return I29; + } -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/mips/mips_64.ad b/src/hotspot/cpu/mips/mips_64.ad ---- a/src/hotspot/cpu/mips/mips_64.ad 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/cpu/mips/mips_64.ad 2024-01-30 10:00:11.848098317 +0800 +diff --git a/src/hotspot/cpu/mips/mips.ad b/src/hotspot/cpu/mips/mips.ad +new file mode 100644 +index 0000000000..3563bbe0e5 +--- /dev/null ++++ b/src/hotspot/cpu/mips/mips.ad +@@ -0,0 +1,25 @@ ++// ++// Copyright (c) 2011, 2012, Oracle and/or its affiliates. All rights reserved. ++// Copyright (c) 2015, 2016, Loongson Technology. All rights reserved. ++// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++// ++// This code is free software; you can redistribute it and/or modify it ++// under the terms of the GNU General Public License version 2 only, as ++// published by the Free Software Foundation. ++// ++// This code is distributed in the hope that it will be useful, but WITHOUT ++// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++// version 2 for more details (a copy is included in the LICENSE file that ++// accompanied this code). ++// ++// You should have received a copy of the GNU General Public License version ++// 2 along with this work; if not, write to the Free Software Foundation, ++// Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++// ++// Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++// or visit www.oracle.com if you need additional information or have any ++// questions. ++// ++// ++ +diff --git a/src/hotspot/cpu/mips/mips_64.ad b/src/hotspot/cpu/mips/mips_64.ad +new file mode 100644 +index 0000000000..b4acbd83f7 +--- /dev/null ++++ b/src/hotspot/cpu/mips/mips_64.ad @@ -0,0 +1,12243 @@ +// +// Copyright (c) 2003, 2013, Oracle and/or its affiliates. All rights reserved. @@ -86005,38 +86301,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h +// These must follow all instruction definitions as they use the names +// defined in the instructions definitions. + -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/mips/mips.ad b/src/hotspot/cpu/mips/mips.ad ---- a/src/hotspot/cpu/mips/mips.ad 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/cpu/mips/mips.ad 2024-01-30 10:00:11.844765024 +0800 -@@ -0,0 +1,25 @@ -+// -+// Copyright (c) 2011, 2012, Oracle and/or its affiliates. All rights reserved. -+// Copyright (c) 2015, 2016, Loongson Technology. All rights reserved. -+// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. -+// -+// This code is free software; you can redistribute it and/or modify it -+// under the terms of the GNU General Public License version 2 only, as -+// published by the Free Software Foundation. -+// -+// This code is distributed in the hope that it will be useful, but WITHOUT -+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -+// version 2 for more details (a copy is included in the LICENSE file that -+// accompanied this code). -+// -+// You should have received a copy of the GNU General Public License version -+// 2 along with this work; if not, write to the Free Software Foundation, -+// Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. -+// -+// Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA -+// or visit www.oracle.com if you need additional information or have any -+// questions. -+// -+// -+ -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/mips/nativeInst_mips.cpp b/src/hotspot/cpu/mips/nativeInst_mips.cpp ---- a/src/hotspot/cpu/mips/nativeInst_mips.cpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/cpu/mips/nativeInst_mips.cpp 2024-01-30 10:00:11.848098317 +0800 +diff --git a/src/hotspot/cpu/mips/nativeInst_mips.cpp b/src/hotspot/cpu/mips/nativeInst_mips.cpp +new file mode 100644 +index 0000000000..96a147eaa5 +--- /dev/null ++++ b/src/hotspot/cpu/mips/nativeInst_mips.cpp @@ -0,0 +1,1821 @@ +/* + * Copyright (c) 1997, 2014, Oracle and/or its affiliates. All rights reserved. @@ -87859,9 +88128,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h + // we check the safepoint instruction like the this. + return is_op(Assembler::lw_op) && is_rt(AT); +} -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/mips/nativeInst_mips.hpp b/src/hotspot/cpu/mips/nativeInst_mips.hpp ---- a/src/hotspot/cpu/mips/nativeInst_mips.hpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/cpu/mips/nativeInst_mips.hpp 2024-01-30 10:00:11.848098317 +0800 +diff --git a/src/hotspot/cpu/mips/nativeInst_mips.hpp b/src/hotspot/cpu/mips/nativeInst_mips.hpp +new file mode 100644 +index 0000000000..fb4f99c9c6 +--- /dev/null ++++ b/src/hotspot/cpu/mips/nativeInst_mips.hpp @@ -0,0 +1,734 @@ +/* + * Copyright (c) 1997, 2011, Oracle and/or its affiliates. All rights reserved. @@ -88597,9 +88868,64 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h + return (NativeCallTrampolineStub*)addr; +} +#endif // CPU_MIPS_VM_NATIVEINST_MIPS_HPP -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/mips/register_definitions_mips.cpp b/src/hotspot/cpu/mips/register_definitions_mips.cpp ---- a/src/hotspot/cpu/mips/register_definitions_mips.cpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/cpu/mips/register_definitions_mips.cpp 2024-01-30 10:00:11.848098317 +0800 +diff --git a/src/hotspot/cpu/mips/registerMap_mips.hpp b/src/hotspot/cpu/mips/registerMap_mips.hpp +new file mode 100644 +index 0000000000..7f800eb107 +--- /dev/null ++++ b/src/hotspot/cpu/mips/registerMap_mips.hpp +@@ -0,0 +1,47 @@ ++/* ++ * Copyright (c) 1998, 2010, Oracle and/or its affiliates. All rights reserved. ++ * Copyright (c) 2015, 2016, Loongson Technology. All rights reserved. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ * ++ */ ++ ++#ifndef CPU_MIPS_VM_REGISTERMAP_MIPS_HPP ++#define CPU_MIPS_VM_REGISTERMAP_MIPS_HPP ++ ++// machine-dependent implemention for register maps ++ friend class frame; ++ ++ private: ++#ifndef CORE ++ // This is the hook for finding a register in an "well-known" location, ++ // such as a register block of a predetermined format. ++ // Since there is none, we just return NULL. ++ // See registerMap_sparc.hpp for an example of grabbing registers ++ // from register save areas of a standard layout. ++ address pd_location(VMReg reg) const {return NULL;} ++#endif ++ ++ // no PD state to clear or copy: ++ void pd_clear() {} ++ void pd_initialize() {} ++ void pd_initialize_from(const RegisterMap* map) {} ++ ++#endif // CPU_MIPS_VM_REGISTERMAP_MIPS_HPP +diff --git a/src/hotspot/cpu/mips/register_definitions_mips.cpp b/src/hotspot/cpu/mips/register_definitions_mips.cpp +new file mode 100644 +index 0000000000..4af2531834 +--- /dev/null ++++ b/src/hotspot/cpu/mips/register_definitions_mips.cpp @@ -0,0 +1,103 @@ +/* + * Copyright (c) 2002, 2013, Oracle and/or its affiliates. All rights reserved. @@ -88704,60 +89030,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h +REGISTER_DEFINITION(FloatRegister, f29); +REGISTER_DEFINITION(FloatRegister, f30); +REGISTER_DEFINITION(FloatRegister, f31); -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/mips/registerMap_mips.hpp b/src/hotspot/cpu/mips/registerMap_mips.hpp ---- a/src/hotspot/cpu/mips/registerMap_mips.hpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/cpu/mips/registerMap_mips.hpp 2024-01-30 10:00:11.848098317 +0800 -@@ -0,0 +1,47 @@ -+/* -+ * Copyright (c) 1998, 2010, Oracle and/or its affiliates. All rights reserved. -+ * Copyright (c) 2015, 2016, Loongson Technology. All rights reserved. -+ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. -+ * -+ * This code is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 only, as -+ * published by the Free Software Foundation. -+ * -+ * This code is distributed in the hope that it will be useful, but WITHOUT -+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -+ * version 2 for more details (a copy is included in the LICENSE file that -+ * accompanied this code). -+ * -+ * You should have received a copy of the GNU General Public License version -+ * 2 along with this work; if not, write to the Free Software Foundation, -+ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. -+ * -+ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA -+ * or visit www.oracle.com if you need additional information or have any -+ * questions. -+ * -+ */ -+ -+#ifndef CPU_MIPS_VM_REGISTERMAP_MIPS_HPP -+#define CPU_MIPS_VM_REGISTERMAP_MIPS_HPP -+ -+// machine-dependent implemention for register maps -+ friend class frame; -+ -+ private: -+#ifndef CORE -+ // This is the hook for finding a register in an "well-known" location, -+ // such as a register block of a predetermined format. -+ // Since there is none, we just return NULL. -+ // See registerMap_sparc.hpp for an example of grabbing registers -+ // from register save areas of a standard layout. -+ address pd_location(VMReg reg) const {return NULL;} -+#endif -+ -+ // no PD state to clear or copy: -+ void pd_clear() {} -+ void pd_initialize() {} -+ void pd_initialize_from(const RegisterMap* map) {} -+ -+#endif // CPU_MIPS_VM_REGISTERMAP_MIPS_HPP -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/mips/register_mips.cpp b/src/hotspot/cpu/mips/register_mips.cpp ---- a/src/hotspot/cpu/mips/register_mips.cpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/cpu/mips/register_mips.cpp 2024-01-30 10:00:11.848098317 +0800 +diff --git a/src/hotspot/cpu/mips/register_mips.cpp b/src/hotspot/cpu/mips/register_mips.cpp +new file mode 100644 +index 0000000000..4a9b22bfef +--- /dev/null ++++ b/src/hotspot/cpu/mips/register_mips.cpp @@ -0,0 +1,52 @@ +/* + * Copyright (c) 2000, 2012, Oracle and/or its affiliates. All rights reserved. @@ -88811,9 +89088,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h + return is_valid() ? names[encoding()] : "fnoreg"; +} + -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/mips/register_mips.hpp b/src/hotspot/cpu/mips/register_mips.hpp ---- a/src/hotspot/cpu/mips/register_mips.hpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/cpu/mips/register_mips.hpp 2024-01-30 10:00:11.848098317 +0800 +diff --git a/src/hotspot/cpu/mips/register_mips.hpp b/src/hotspot/cpu/mips/register_mips.hpp +new file mode 100644 +index 0000000000..ea216fbcb9 +--- /dev/null ++++ b/src/hotspot/cpu/mips/register_mips.hpp @@ -0,0 +1,341 @@ +/* + * Copyright (c) 2000, 2012, Oracle and/or its affiliates. All rights reserved. @@ -89156,9 +89435,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h +}; + +#endif //CPU_MIPS_VM_REGISTER_MIPS_HPP -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/mips/relocInfo_mips.cpp b/src/hotspot/cpu/mips/relocInfo_mips.cpp ---- a/src/hotspot/cpu/mips/relocInfo_mips.cpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/cpu/mips/relocInfo_mips.cpp 2024-01-30 10:00:11.848098317 +0800 +diff --git a/src/hotspot/cpu/mips/relocInfo_mips.cpp b/src/hotspot/cpu/mips/relocInfo_mips.cpp +new file mode 100644 +index 0000000000..ff8028032b +--- /dev/null ++++ b/src/hotspot/cpu/mips/relocInfo_mips.cpp @@ -0,0 +1,160 @@ +/* + * Copyright (c) 1998, 2013, Oracle and/or its affiliates. All rights reserved. @@ -89320,9 +89601,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h + +void metadata_Relocation::pd_fix_value(address x) { +} -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/mips/relocInfo_mips.hpp b/src/hotspot/cpu/mips/relocInfo_mips.hpp ---- a/src/hotspot/cpu/mips/relocInfo_mips.hpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/cpu/mips/relocInfo_mips.hpp 2024-01-30 10:00:11.848098317 +0800 +diff --git a/src/hotspot/cpu/mips/relocInfo_mips.hpp b/src/hotspot/cpu/mips/relocInfo_mips.hpp +new file mode 100644 +index 0000000000..1e1e170fd8 +--- /dev/null ++++ b/src/hotspot/cpu/mips/relocInfo_mips.hpp @@ -0,0 +1,44 @@ +/* + * Copyright (c) 1997, 2010, Oracle and/or its affiliates. All rights reserved. @@ -89368,9 +89651,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h + static bool mustIterateImmediateOopsInCode() { return false; } + +#endif // CPU_MIPS_VM_RELOCINFO_MIPS_HPP -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/mips/runtime_mips_64.cpp b/src/hotspot/cpu/mips/runtime_mips_64.cpp ---- a/src/hotspot/cpu/mips/runtime_mips_64.cpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/cpu/mips/runtime_mips_64.cpp 2024-01-30 10:00:11.848098317 +0800 +diff --git a/src/hotspot/cpu/mips/runtime_mips_64.cpp b/src/hotspot/cpu/mips/runtime_mips_64.cpp +new file mode 100644 +index 0000000000..2a0488cd01 +--- /dev/null ++++ b/src/hotspot/cpu/mips/runtime_mips_64.cpp @@ -0,0 +1,198 @@ +/* + * Copyright (c) 2003, 2010, Oracle and/or its affiliates. All rights reserved. @@ -89570,9 +89855,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h + + _exception_blob = ExceptionBlob::create(&buffer, oop_maps, framesize); +} -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/mips/sharedRuntime_mips_64.cpp b/src/hotspot/cpu/mips/sharedRuntime_mips_64.cpp ---- a/src/hotspot/cpu/mips/sharedRuntime_mips_64.cpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/cpu/mips/sharedRuntime_mips_64.cpp 2024-01-30 10:00:11.848098317 +0800 +diff --git a/src/hotspot/cpu/mips/sharedRuntime_mips_64.cpp b/src/hotspot/cpu/mips/sharedRuntime_mips_64.cpp +new file mode 100644 +index 0000000000..4a9791d4cb +--- /dev/null ++++ b/src/hotspot/cpu/mips/sharedRuntime_mips_64.cpp @@ -0,0 +1,3879 @@ +/* + * Copyright (c) 2003, 2013, Oracle and/or its affiliates. All rights reserved. @@ -93453,9 +93740,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h + + reverse_words(m, (unsigned long *)m_ints, longwords); +} -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/mips/stubGenerator_mips_64.cpp b/src/hotspot/cpu/mips/stubGenerator_mips_64.cpp ---- a/src/hotspot/cpu/mips/stubGenerator_mips_64.cpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/cpu/mips/stubGenerator_mips_64.cpp 2024-01-30 10:00:11.848098317 +0800 +diff --git a/src/hotspot/cpu/mips/stubGenerator_mips_64.cpp b/src/hotspot/cpu/mips/stubGenerator_mips_64.cpp +new file mode 100644 +index 0000000000..9fe2bc8377 +--- /dev/null ++++ b/src/hotspot/cpu/mips/stubGenerator_mips_64.cpp @@ -0,0 +1,2162 @@ +/* + * Copyright (c) 2003, 2013, Oracle and/or its affiliates. All rights reserved. @@ -95619,48 +95908,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h +void StubGenerator_generate(CodeBuffer* code, bool all) { + StubGenerator g(code, all); +} -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/mips/stubRoutines_mips_64.cpp b/src/hotspot/cpu/mips/stubRoutines_mips_64.cpp ---- a/src/hotspot/cpu/mips/stubRoutines_mips_64.cpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/cpu/mips/stubRoutines_mips_64.cpp 2024-01-30 10:00:11.848098317 +0800 -@@ -0,0 +1,35 @@ -+/* -+ * Copyright (c) 2003, 2013, Oracle and/or its affiliates. All rights reserved. -+ * Copyright (c) 2015, 2021, Loongson Technology. All rights reserved. -+ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. -+ * -+ * This code is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 only, as -+ * published by the Free Software Foundation. -+ * -+ * This code is distributed in the hope that it will be useful, but WITHOUT -+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -+ * version 2 for more details (a copy is included in the LICENSE file that -+ * accompanied this code). -+ * -+ * You should have received a copy of the GNU General Public License version -+ * 2 along with this work; if not, write to the Free Software Foundation, -+ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. -+ * -+ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA -+ * or visit www.oracle.com if you need additional information or have any -+ * questions. -+ * -+ */ -+ -+#include "precompiled.hpp" -+#include "runtime/deoptimization.hpp" -+#include "runtime/frame.inline.hpp" -+#include "runtime/stubRoutines.hpp" -+#include "runtime/thread.inline.hpp" -+ -+// a description of how to extend it, see the stubRoutines.hpp file. -+ -+//find the last fp value -+address StubRoutines::gs2::_call_stub_compiled_return = NULL; -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/mips/stubRoutines_mips.hpp b/src/hotspot/cpu/mips/stubRoutines_mips.hpp ---- a/src/hotspot/cpu/mips/stubRoutines_mips.hpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/cpu/mips/stubRoutines_mips.hpp 2024-01-30 10:00:11.848098317 +0800 +diff --git a/src/hotspot/cpu/mips/stubRoutines_mips.hpp b/src/hotspot/cpu/mips/stubRoutines_mips.hpp +new file mode 100644 +index 0000000000..920c08844e +--- /dev/null ++++ b/src/hotspot/cpu/mips/stubRoutines_mips.hpp @@ -0,0 +1,59 @@ +/* + * Copyright (c) 2003, 2013, Oracle and/or its affiliates. All rights reserved. @@ -95721,9 +95973,52 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h +}; + +#endif // CPU_MIPS_VM_STUBROUTINES_MIPS_64_HPP -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/mips/templateInterpreterGenerator_mips.cpp b/src/hotspot/cpu/mips/templateInterpreterGenerator_mips.cpp ---- a/src/hotspot/cpu/mips/templateInterpreterGenerator_mips.cpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/cpu/mips/templateInterpreterGenerator_mips.cpp 2024-01-30 10:00:11.848098317 +0800 +diff --git a/src/hotspot/cpu/mips/stubRoutines_mips_64.cpp b/src/hotspot/cpu/mips/stubRoutines_mips_64.cpp +new file mode 100644 +index 0000000000..358d580d52 +--- /dev/null ++++ b/src/hotspot/cpu/mips/stubRoutines_mips_64.cpp +@@ -0,0 +1,35 @@ ++/* ++ * Copyright (c) 2003, 2013, Oracle and/or its affiliates. All rights reserved. ++ * Copyright (c) 2015, 2021, Loongson Technology. All rights reserved. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ * ++ */ ++ ++#include "precompiled.hpp" ++#include "runtime/deoptimization.hpp" ++#include "runtime/frame.inline.hpp" ++#include "runtime/stubRoutines.hpp" ++#include "runtime/thread.inline.hpp" ++ ++// a description of how to extend it, see the stubRoutines.hpp file. ++ ++//find the last fp value ++address StubRoutines::gs2::_call_stub_compiled_return = NULL; +diff --git a/src/hotspot/cpu/mips/templateInterpreterGenerator_mips.cpp b/src/hotspot/cpu/mips/templateInterpreterGenerator_mips.cpp +new file mode 100644 +index 0000000000..19e2f29c59 +--- /dev/null ++++ b/src/hotspot/cpu/mips/templateInterpreterGenerator_mips.cpp @@ -0,0 +1,2149 @@ +/* + * Copyright (c) 2003, 2013, Oracle and/or its affiliates. All rights reserved. @@ -97874,9 +98169,60 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h + __ bind(L); +} +#endif // !PRODUCT -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/mips/templateTable_mips_64.cpp b/src/hotspot/cpu/mips/templateTable_mips_64.cpp ---- a/src/hotspot/cpu/mips/templateTable_mips_64.cpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/cpu/mips/templateTable_mips_64.cpp 2024-01-30 10:00:11.848098317 +0800 +diff --git a/src/hotspot/cpu/mips/templateTable_mips.hpp b/src/hotspot/cpu/mips/templateTable_mips.hpp +new file mode 100644 +index 0000000000..46a88aba26 +--- /dev/null ++++ b/src/hotspot/cpu/mips/templateTable_mips.hpp +@@ -0,0 +1,43 @@ ++/* ++ * Copyright (c) 2003, 2012, Oracle and/or its affiliates. All rights reserved. ++ * Copyright (c) 2015, 2018, Loongson Technology. All rights reserved. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ * ++ */ ++ ++#ifndef CPU_MIPS_VM_TEMPLATETABLE_MIPS_64_HPP ++#define CPU_MIPS_VM_TEMPLATETABLE_MIPS_64_HPP ++ ++ static void prepare_invoke(int byte_no, ++ Register method, // linked method (or i-klass) ++ Register index = noreg, // itable index, MethodType, etc. ++ Register recv = noreg, // if caller wants to see it ++ Register flags = noreg // if caller wants to test it ++ ); ++ static void invokevirtual_helper(Register index, Register recv, ++ Register flags); ++ static void volatile_barrier(); ++ ++ // Helpers ++ static void index_check(Register array, Register index); ++ static void index_check_without_pop(Register array, Register index); ++ ++#endif // CPU_MIPS_VM_TEMPLATETABLE_MIPS_64_HPP +diff --git a/src/hotspot/cpu/mips/templateTable_mips_64.cpp b/src/hotspot/cpu/mips/templateTable_mips_64.cpp +new file mode 100644 +index 0000000000..5265483830 +--- /dev/null ++++ b/src/hotspot/cpu/mips/templateTable_mips_64.cpp @@ -0,0 +1,4688 @@ +/* + * Copyright (c) 2003, 2013, Oracle and/or its affiliates. All rights reserved. @@ -102566,213 +102912,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h + __ sync(); +} +#endif // !CC_INTERP -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/mips/templateTable_mips.hpp b/src/hotspot/cpu/mips/templateTable_mips.hpp ---- a/src/hotspot/cpu/mips/templateTable_mips.hpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/cpu/mips/templateTable_mips.hpp 2024-01-30 10:00:11.848098317 +0800 -@@ -0,0 +1,43 @@ -+/* -+ * Copyright (c) 2003, 2012, Oracle and/or its affiliates. All rights reserved. -+ * Copyright (c) 2015, 2018, Loongson Technology. All rights reserved. -+ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. -+ * -+ * This code is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 only, as -+ * published by the Free Software Foundation. -+ * -+ * This code is distributed in the hope that it will be useful, but WITHOUT -+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -+ * version 2 for more details (a copy is included in the LICENSE file that -+ * accompanied this code). -+ * -+ * You should have received a copy of the GNU General Public License version -+ * 2 along with this work; if not, write to the Free Software Foundation, -+ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. -+ * -+ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA -+ * or visit www.oracle.com if you need additional information or have any -+ * questions. -+ * -+ */ -+ -+#ifndef CPU_MIPS_VM_TEMPLATETABLE_MIPS_64_HPP -+#define CPU_MIPS_VM_TEMPLATETABLE_MIPS_64_HPP -+ -+ static void prepare_invoke(int byte_no, -+ Register method, // linked method (or i-klass) -+ Register index = noreg, // itable index, MethodType, etc. -+ Register recv = noreg, // if caller wants to see it -+ Register flags = noreg // if caller wants to test it -+ ); -+ static void invokevirtual_helper(Register index, Register recv, -+ Register flags); -+ static void volatile_barrier(); -+ -+ // Helpers -+ static void index_check(Register array, Register index); -+ static void index_check_without_pop(Register array, Register index); -+ -+#endif // CPU_MIPS_VM_TEMPLATETABLE_MIPS_64_HPP -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/mips/vmreg_mips.cpp b/src/hotspot/cpu/mips/vmreg_mips.cpp ---- a/src/hotspot/cpu/mips/vmreg_mips.cpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/cpu/mips/vmreg_mips.cpp 2024-01-30 10:00:11.848098317 +0800 -@@ -0,0 +1,51 @@ -+/* -+ * Copyright (c) 2006, 2012, Oracle and/or its affiliates. All rights reserved. -+ * Copyright (c) 2015, 2022, Loongson Technology. All rights reserved. -+ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. -+ * -+ * This code is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 only, as -+ * published by the Free Software Foundation. -+ * -+ * This code is distributed in the hope that it will be useful, but WITHOUT -+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -+ * version 2 for more details (a copy is included in the LICENSE file that -+ * accompanied this code). -+ * -+ * You should have received a copy of the GNU General Public License version -+ * 2 along with this work; if not, write to the Free Software Foundation, -+ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. -+ * -+ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA -+ * or visit www.oracle.com if you need additional information or have any -+ * questions. -+ * -+ */ -+ -+#include "precompiled.hpp" -+#include "asm/assembler.hpp" -+#include "code/vmreg.hpp" -+ -+ -+ -+void VMRegImpl::set_regName() { -+ Register reg = ::as_Register(0); -+ int i; -+ for (i = 0; i < ConcreteRegisterImpl::max_gpr ; ) { -+ regName[i++] = reg->name(); -+ regName[i++] = reg->name(); -+ reg = reg->successor(); -+ } -+ -+ FloatRegister freg = ::as_FloatRegister(0); -+ for ( ; i < ConcreteRegisterImpl::max_fpr ; ) { -+ regName[i++] = freg->name(); -+ regName[i++] = freg->name(); -+ freg = freg->successor(); -+ } -+ -+ for ( ; i < ConcreteRegisterImpl::number_of_registers ; i ++ ) { -+ regName[i] = "NON-GPR-FPR"; -+ } -+} -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/mips/vmreg_mips.hpp b/src/hotspot/cpu/mips/vmreg_mips.hpp ---- a/src/hotspot/cpu/mips/vmreg_mips.hpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/cpu/mips/vmreg_mips.hpp 2024-01-30 10:00:11.848098317 +0800 -@@ -0,0 +1,56 @@ -+/* -+ * Copyright (c) 2006, 2010, Oracle and/or its affiliates. All rights reserved. -+ * Copyright (c) 2015, 2022, Loongson Technology. All rights reserved. -+ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. -+ * -+ * This code is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 only, as -+ * published by the Free Software Foundation. -+ * -+ * This code is distributed in the hope that it will be useful, but WITHOUT -+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -+ * version 2 for more details (a copy is included in the LICENSE file that -+ * accompanied this code). -+ * -+ * You should have received a copy of the GNU General Public License version -+ * 2 along with this work; if not, write to the Free Software Foundation, -+ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. -+ * -+ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA -+ * or visit www.oracle.com if you need additional information or have any -+ * questions. -+ * -+ */ -+ -+#ifndef CPU_MIPS_VM_VMREG_MIPS_HPP -+#define CPU_MIPS_VM_VMREG_MIPS_HPP -+ -+inline Register as_Register() { -+ assert( is_Register(), "must be"); -+ return ::as_Register(value() >> 1); -+} -+ -+inline FloatRegister as_FloatRegister() { -+ assert( is_FloatRegister(), "must be" ); -+ assert( is_even(value()), "must be" ); -+ return ::as_FloatRegister((value() - ConcreteRegisterImpl::max_gpr) >> 1); -+} -+ -+inline bool is_Register() { -+ return (unsigned int) value() < (unsigned int) ConcreteRegisterImpl::max_gpr; -+} -+ -+inline bool is_FloatRegister() { -+ return value() >= ConcreteRegisterImpl::max_gpr && value() < ConcreteRegisterImpl::max_fpr; -+} -+ -+inline bool is_concrete() { -+ assert(is_reg(), "must be"); -+ if(is_Register()) return true; -+ if(is_FloatRegister()) return true; -+ assert(false, "what register?"); -+ return false; -+} -+ -+#endif // CPU_MIPS_VM_VMREG_MIPS_HPP -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/mips/vmreg_mips.inline.hpp b/src/hotspot/cpu/mips/vmreg_mips.inline.hpp ---- a/src/hotspot/cpu/mips/vmreg_mips.inline.hpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/cpu/mips/vmreg_mips.inline.hpp 2024-01-30 10:00:11.848098317 +0800 -@@ -0,0 +1,38 @@ -+/* -+ * Copyright (c) 2006, 2012, Oracle and/or its affiliates. All rights reserved. -+ * Copyright (c) 2015, 2022, Loongson Technology. All rights reserved. -+ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. -+ * -+ * This code is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 only, as -+ * published by the Free Software Foundation. -+ * -+ * This code is distributed in the hope that it will be useful, but WITHOUT -+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -+ * version 2 for more details (a copy is included in the LICENSE file that -+ * accompanied this code). -+ * -+ * You should have received a copy of the GNU General Public License version -+ * 2 along with this work; if not, write to the Free Software Foundation, -+ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. -+ * -+ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA -+ * or visit www.oracle.com if you need additional information or have any -+ * questions. -+ * -+ */ -+ -+#ifndef CPU_MIPS_VM_VMREG_MIPS_INLINE_HPP -+#define CPU_MIPS_VM_VMREG_MIPS_INLINE_HPP -+ -+inline VMReg RegisterImpl::as_VMReg() { -+ if( this==noreg ) return VMRegImpl::Bad(); -+ return VMRegImpl::as_VMReg(encoding() << 1 ); -+} -+ -+inline VMReg FloatRegisterImpl::as_VMReg() { -+ return VMRegImpl::as_VMReg((encoding() << 1) + ConcreteRegisterImpl::max_gpr); -+} -+ -+#endif // CPU_MIPS_VM_VMREG_MIPS_INLINE_HPP -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/mips/vmStructs_mips.hpp b/src/hotspot/cpu/mips/vmStructs_mips.hpp ---- a/src/hotspot/cpu/mips/vmStructs_mips.hpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/cpu/mips/vmStructs_mips.hpp 2024-01-30 10:00:11.848098317 +0800 +diff --git a/src/hotspot/cpu/mips/vmStructs_mips.hpp b/src/hotspot/cpu/mips/vmStructs_mips.hpp +new file mode 100644 +index 0000000000..6939914356 +--- /dev/null ++++ b/src/hotspot/cpu/mips/vmStructs_mips.hpp @@ -0,0 +1,68 @@ +/* + * Copyright (c) 2001, 2013, Oracle and/or its affiliates. All rights reserved. @@ -102842,9 +102986,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h + /* be present there) */ + +#endif // CPU_MIPS_VM_VMSTRUCTS_MIPS_HPP -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/mips/vm_version_ext_mips.cpp b/src/hotspot/cpu/mips/vm_version_ext_mips.cpp ---- a/src/hotspot/cpu/mips/vm_version_ext_mips.cpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/cpu/mips/vm_version_ext_mips.cpp 2024-01-30 10:00:11.848098317 +0800 +diff --git a/src/hotspot/cpu/mips/vm_version_ext_mips.cpp b/src/hotspot/cpu/mips/vm_version_ext_mips.cpp +new file mode 100644 +index 0000000000..ac2a43edce +--- /dev/null ++++ b/src/hotspot/cpu/mips/vm_version_ext_mips.cpp @@ -0,0 +1,90 @@ +/* + * Copyright (c) 2013, 2018, Oracle and/or its affiliates. All rights reserved. @@ -102936,9 +103082,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h + strncpy(tmp, _cpu_desc, CPU_DETAILED_DESC_BUF_SIZE); + return tmp; +} -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/mips/vm_version_ext_mips.hpp b/src/hotspot/cpu/mips/vm_version_ext_mips.hpp ---- a/src/hotspot/cpu/mips/vm_version_ext_mips.hpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/cpu/mips/vm_version_ext_mips.hpp 2024-01-30 10:00:11.848098317 +0800 +diff --git a/src/hotspot/cpu/mips/vm_version_ext_mips.hpp b/src/hotspot/cpu/mips/vm_version_ext_mips.hpp +new file mode 100644 +index 0000000000..ffdcff0677 +--- /dev/null ++++ b/src/hotspot/cpu/mips/vm_version_ext_mips.hpp @@ -0,0 +1,54 @@ +/* + * Copyright (c) 2016, 2018, Oracle and/or its affiliates. All rights reserved. @@ -102994,9 +103142,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h +}; + +#endif // CPU_MIPS_VM_VM_VERSION_EXT_MIPS_HPP -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/mips/vm_version_mips.cpp b/src/hotspot/cpu/mips/vm_version_mips.cpp ---- a/src/hotspot/cpu/mips/vm_version_mips.cpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/cpu/mips/vm_version_mips.cpp 2024-01-30 10:00:11.848098317 +0800 +diff --git a/src/hotspot/cpu/mips/vm_version_mips.cpp b/src/hotspot/cpu/mips/vm_version_mips.cpp +new file mode 100644 +index 0000000000..2e7b61390e +--- /dev/null ++++ b/src/hotspot/cpu/mips/vm_version_mips.cpp @@ -0,0 +1,516 @@ +/* + * Copyright (c) 1997, 2014, Oracle and/or its affiliates. All rights reserved. @@ -103514,9 +103664,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h + + get_processor_features(); +} -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/mips/vm_version_mips.hpp b/src/hotspot/cpu/mips/vm_version_mips.hpp ---- a/src/hotspot/cpu/mips/vm_version_mips.hpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/cpu/mips/vm_version_mips.hpp 2024-01-30 10:00:11.848098317 +0800 +diff --git a/src/hotspot/cpu/mips/vm_version_mips.hpp b/src/hotspot/cpu/mips/vm_version_mips.hpp +new file mode 100644 +index 0000000000..733a0af295 +--- /dev/null ++++ b/src/hotspot/cpu/mips/vm_version_mips.hpp @@ -0,0 +1,221 @@ +/* + * Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved. @@ -103739,9 +103891,174 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h +}; + +#endif // CPU_MIPS_VM_VM_VERSION_MIPS_HPP -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/mips/vtableStubs_mips_64.cpp b/src/hotspot/cpu/mips/vtableStubs_mips_64.cpp ---- a/src/hotspot/cpu/mips/vtableStubs_mips_64.cpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/cpu/mips/vtableStubs_mips_64.cpp 2024-01-30 10:00:11.848098317 +0800 +diff --git a/src/hotspot/cpu/mips/vmreg_mips.cpp b/src/hotspot/cpu/mips/vmreg_mips.cpp +new file mode 100644 +index 0000000000..86bd74d430 +--- /dev/null ++++ b/src/hotspot/cpu/mips/vmreg_mips.cpp +@@ -0,0 +1,51 @@ ++/* ++ * Copyright (c) 2006, 2012, Oracle and/or its affiliates. All rights reserved. ++ * Copyright (c) 2015, 2022, Loongson Technology. All rights reserved. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ * ++ */ ++ ++#include "precompiled.hpp" ++#include "asm/assembler.hpp" ++#include "code/vmreg.hpp" ++ ++ ++ ++void VMRegImpl::set_regName() { ++ Register reg = ::as_Register(0); ++ int i; ++ for (i = 0; i < ConcreteRegisterImpl::max_gpr ; ) { ++ regName[i++] = reg->name(); ++ regName[i++] = reg->name(); ++ reg = reg->successor(); ++ } ++ ++ FloatRegister freg = ::as_FloatRegister(0); ++ for ( ; i < ConcreteRegisterImpl::max_fpr ; ) { ++ regName[i++] = freg->name(); ++ regName[i++] = freg->name(); ++ freg = freg->successor(); ++ } ++ ++ for ( ; i < ConcreteRegisterImpl::number_of_registers ; i ++ ) { ++ regName[i] = "NON-GPR-FPR"; ++ } ++} +diff --git a/src/hotspot/cpu/mips/vmreg_mips.hpp b/src/hotspot/cpu/mips/vmreg_mips.hpp +new file mode 100644 +index 0000000000..8ccc8c513c +--- /dev/null ++++ b/src/hotspot/cpu/mips/vmreg_mips.hpp +@@ -0,0 +1,56 @@ ++/* ++ * Copyright (c) 2006, 2010, Oracle and/or its affiliates. All rights reserved. ++ * Copyright (c) 2015, 2022, Loongson Technology. All rights reserved. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ * ++ */ ++ ++#ifndef CPU_MIPS_VM_VMREG_MIPS_HPP ++#define CPU_MIPS_VM_VMREG_MIPS_HPP ++ ++inline Register as_Register() { ++ assert( is_Register(), "must be"); ++ return ::as_Register(value() >> 1); ++} ++ ++inline FloatRegister as_FloatRegister() { ++ assert( is_FloatRegister(), "must be" ); ++ assert( is_even(value()), "must be" ); ++ return ::as_FloatRegister((value() - ConcreteRegisterImpl::max_gpr) >> 1); ++} ++ ++inline bool is_Register() { ++ return (unsigned int) value() < (unsigned int) ConcreteRegisterImpl::max_gpr; ++} ++ ++inline bool is_FloatRegister() { ++ return value() >= ConcreteRegisterImpl::max_gpr && value() < ConcreteRegisterImpl::max_fpr; ++} ++ ++inline bool is_concrete() { ++ assert(is_reg(), "must be"); ++ if(is_Register()) return true; ++ if(is_FloatRegister()) return true; ++ assert(false, "what register?"); ++ return false; ++} ++ ++#endif // CPU_MIPS_VM_VMREG_MIPS_HPP +diff --git a/src/hotspot/cpu/mips/vmreg_mips.inline.hpp b/src/hotspot/cpu/mips/vmreg_mips.inline.hpp +new file mode 100644 +index 0000000000..12ad7361aa +--- /dev/null ++++ b/src/hotspot/cpu/mips/vmreg_mips.inline.hpp +@@ -0,0 +1,38 @@ ++/* ++ * Copyright (c) 2006, 2012, Oracle and/or its affiliates. All rights reserved. ++ * Copyright (c) 2015, 2022, Loongson Technology. All rights reserved. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ * ++ */ ++ ++#ifndef CPU_MIPS_VM_VMREG_MIPS_INLINE_HPP ++#define CPU_MIPS_VM_VMREG_MIPS_INLINE_HPP ++ ++inline VMReg RegisterImpl::as_VMReg() { ++ if( this==noreg ) return VMRegImpl::Bad(); ++ return VMRegImpl::as_VMReg(encoding() << 1 ); ++} ++ ++inline VMReg FloatRegisterImpl::as_VMReg() { ++ return VMRegImpl::as_VMReg((encoding() << 1) + ConcreteRegisterImpl::max_gpr); ++} ++ ++#endif // CPU_MIPS_VM_VMREG_MIPS_INLINE_HPP +diff --git a/src/hotspot/cpu/mips/vtableStubs_mips_64.cpp b/src/hotspot/cpu/mips/vtableStubs_mips_64.cpp +new file mode 100644 +index 0000000000..75c23e8088 +--- /dev/null ++++ b/src/hotspot/cpu/mips/vtableStubs_mips_64.cpp @@ -0,0 +1,340 @@ +/* + * Copyright (c) 2003, 2014, Oracle and/or its affiliates. All rights reserved. @@ -104083,10 +104400,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h + const unsigned int icache_line_size = wordSize; + return icache_line_size; +} -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/ppc/c1_LIRAssembler_ppc.cpp b/src/hotspot/cpu/ppc/c1_LIRAssembler_ppc.cpp ---- a/src/hotspot/cpu/ppc/c1_LIRAssembler_ppc.cpp 2024-01-10 05:19:49.000000000 +0800 -+++ b/src/hotspot/cpu/ppc/c1_LIRAssembler_ppc.cpp 2024-01-30 10:00:11.851431611 +0800 -@@ -488,6 +488,9 @@ +diff --git a/src/hotspot/cpu/ppc/c1_LIRAssembler_ppc.cpp b/src/hotspot/cpu/ppc/c1_LIRAssembler_ppc.cpp +index 243cde8d74..124efbfb1b 100644 +--- a/src/hotspot/cpu/ppc/c1_LIRAssembler_ppc.cpp ++++ b/src/hotspot/cpu/ppc/c1_LIRAssembler_ppc.cpp +@@ -488,6 +488,9 @@ void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) { } } @@ -104096,7 +104414,7 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) { Bytecodes::Code code = op->bytecode(); -@@ -1608,6 +1611,10 @@ +@@ -1608,6 +1611,10 @@ void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, L __ bind(skip); } @@ -104107,10 +104425,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack) { -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/ppc/c1_LIRGenerator_ppc.cpp b/src/hotspot/cpu/ppc/c1_LIRGenerator_ppc.cpp ---- a/src/hotspot/cpu/ppc/c1_LIRGenerator_ppc.cpp 2024-01-10 05:19:49.000000000 +0800 -+++ b/src/hotspot/cpu/ppc/c1_LIRGenerator_ppc.cpp 2024-01-30 10:00:11.851431611 +0800 -@@ -273,21 +273,29 @@ +diff --git a/src/hotspot/cpu/ppc/c1_LIRGenerator_ppc.cpp b/src/hotspot/cpu/ppc/c1_LIRGenerator_ppc.cpp +index 8bb8c441b2..32384c6491 100644 +--- a/src/hotspot/cpu/ppc/c1_LIRGenerator_ppc.cpp ++++ b/src/hotspot/cpu/ppc/c1_LIRGenerator_ppc.cpp +@@ -275,21 +275,29 @@ void LIRGenerator::increment_counter(LIR_Address* addr, int step) { __ move(temp, addr); } @@ -104146,10 +104465,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h bool LIRGenerator::strength_reduce_multiply(LIR_Opr left, jint c, LIR_Opr result, LIR_Opr tmp) { assert(left != result, "should be different registers"); -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/ppc/c1_LIR_ppc.cpp b/src/hotspot/cpu/ppc/c1_LIR_ppc.cpp ---- a/src/hotspot/cpu/ppc/c1_LIR_ppc.cpp 2024-01-10 05:19:49.000000000 +0800 -+++ b/src/hotspot/cpu/ppc/c1_LIR_ppc.cpp 2024-01-30 10:00:11.851431611 +0800 -@@ -62,3 +62,24 @@ +diff --git a/src/hotspot/cpu/ppc/c1_LIR_ppc.cpp b/src/hotspot/cpu/ppc/c1_LIR_ppc.cpp +index ef9b0833d3..c6b25bf10e 100644 +--- a/src/hotspot/cpu/ppc/c1_LIR_ppc.cpp ++++ b/src/hotspot/cpu/ppc/c1_LIR_ppc.cpp +@@ -62,3 +62,24 @@ void LIR_Address::verify() const { #endif } #endif // PRODUCT @@ -104174,10 +104494,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h + cmp(condition, left, right); + cmove(condition, src1, src2, dst, type); +} -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/s390/c1_LIRAssembler_s390.cpp b/src/hotspot/cpu/s390/c1_LIRAssembler_s390.cpp ---- a/src/hotspot/cpu/s390/c1_LIRAssembler_s390.cpp 2024-01-10 05:19:49.000000000 +0800 -+++ b/src/hotspot/cpu/s390/c1_LIRAssembler_s390.cpp 2024-01-30 10:00:11.861431492 +0800 -@@ -379,6 +379,9 @@ +diff --git a/src/hotspot/cpu/s390/c1_LIRAssembler_s390.cpp b/src/hotspot/cpu/s390/c1_LIRAssembler_s390.cpp +index 897be2209e..0c27cc20f3 100644 +--- a/src/hotspot/cpu/s390/c1_LIRAssembler_s390.cpp ++++ b/src/hotspot/cpu/s390/c1_LIRAssembler_s390.cpp +@@ -379,6 +379,9 @@ void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) { } } @@ -104187,7 +104508,7 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) { LIR_Opr src = op->in_opr(); -@@ -1503,6 +1506,10 @@ +@@ -1503,6 +1506,10 @@ void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, L } } @@ -104198,10 +104519,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack) { assert(info == NULL, "should never be used, idiv/irem and ldiv/lrem not handled by this method"); -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/s390/c1_LIRGenerator_s390.cpp b/src/hotspot/cpu/s390/c1_LIRGenerator_s390.cpp ---- a/src/hotspot/cpu/s390/c1_LIRGenerator_s390.cpp 2024-01-10 05:19:49.000000000 +0800 -+++ b/src/hotspot/cpu/s390/c1_LIRGenerator_s390.cpp 2024-01-30 10:00:11.861431492 +0800 -@@ -213,16 +213,29 @@ +diff --git a/src/hotspot/cpu/s390/c1_LIRGenerator_s390.cpp b/src/hotspot/cpu/s390/c1_LIRGenerator_s390.cpp +index 86eb2fe88c..114aacaade 100644 +--- a/src/hotspot/cpu/s390/c1_LIRGenerator_s390.cpp ++++ b/src/hotspot/cpu/s390/c1_LIRGenerator_s390.cpp +@@ -215,16 +215,29 @@ void LIRGenerator::increment_counter(LIR_Address* addr, int step) { __ add((LIR_Opr)addr, LIR_OprFact::intConst(step), (LIR_Opr)addr); } @@ -104234,10 +104556,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h bool LIRGenerator::strength_reduce_multiply(LIR_Opr left, jint c, LIR_Opr result, LIR_Opr tmp) { if (tmp->is_valid()) { if (is_power_of_2(c + 1)) { -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/s390/c1_LIR_s390.cpp b/src/hotspot/cpu/s390/c1_LIR_s390.cpp ---- a/src/hotspot/cpu/s390/c1_LIR_s390.cpp 2024-01-10 05:19:49.000000000 +0800 -+++ b/src/hotspot/cpu/s390/c1_LIR_s390.cpp 2024-01-30 10:00:11.861431492 +0800 -@@ -56,3 +56,23 @@ +diff --git a/src/hotspot/cpu/s390/c1_LIR_s390.cpp b/src/hotspot/cpu/s390/c1_LIR_s390.cpp +index 9507ca0856..2116e9af2b 100644 +--- a/src/hotspot/cpu/s390/c1_LIR_s390.cpp ++++ b/src/hotspot/cpu/s390/c1_LIR_s390.cpp +@@ -56,3 +56,23 @@ void LIR_Address::verify() const { } #endif // PRODUCT @@ -104261,10 +104584,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h + cmp(condition, left, right); + cmove(condition, src1, src2, dst, type); +} -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/sparc/c1_LIRAssembler_sparc.cpp b/src/hotspot/cpu/sparc/c1_LIRAssembler_sparc.cpp ---- a/src/hotspot/cpu/sparc/c1_LIRAssembler_sparc.cpp 2024-01-10 05:19:49.000000000 +0800 -+++ b/src/hotspot/cpu/sparc/c1_LIRAssembler_sparc.cpp 2024-01-30 10:00:11.878097961 +0800 -@@ -599,6 +599,9 @@ +diff --git a/src/hotspot/cpu/sparc/c1_LIRAssembler_sparc.cpp b/src/hotspot/cpu/sparc/c1_LIRAssembler_sparc.cpp +index e503159eb7..2e5609fec8 100644 +--- a/src/hotspot/cpu/sparc/c1_LIRAssembler_sparc.cpp ++++ b/src/hotspot/cpu/sparc/c1_LIRAssembler_sparc.cpp +@@ -599,6 +599,9 @@ void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) { // The peephole pass fills the delay slot } @@ -104274,7 +104598,7 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) { Bytecodes::Code code = op->bytecode(); -@@ -1638,6 +1641,9 @@ +@@ -1638,6 +1641,9 @@ void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, L __ bind(skip); } @@ -104284,10 +104608,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack) { assert(info == NULL, "unused on this code path"); -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/sparc/c1_LIRGenerator_sparc.cpp b/src/hotspot/cpu/sparc/c1_LIRGenerator_sparc.cpp ---- a/src/hotspot/cpu/sparc/c1_LIRGenerator_sparc.cpp 2024-01-10 05:19:49.000000000 +0800 -+++ b/src/hotspot/cpu/sparc/c1_LIRGenerator_sparc.cpp 2024-01-30 10:00:11.878097961 +0800 -@@ -267,19 +267,29 @@ +diff --git a/src/hotspot/cpu/sparc/c1_LIRGenerator_sparc.cpp b/src/hotspot/cpu/sparc/c1_LIRGenerator_sparc.cpp +index b324a3dbd8..0b7cb52dcd 100644 +--- a/src/hotspot/cpu/sparc/c1_LIRGenerator_sparc.cpp ++++ b/src/hotspot/cpu/sparc/c1_LIRGenerator_sparc.cpp +@@ -269,19 +269,29 @@ void LIRGenerator::increment_counter(LIR_Address* addr, int step) { __ move(temp, addr); } @@ -104321,10 +104646,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h bool LIRGenerator::strength_reduce_multiply(LIR_Opr left, int c, LIR_Opr result, LIR_Opr tmp) { assert(left != result, "should be different registers"); -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/sparc/c1_LIR_sparc.cpp b/src/hotspot/cpu/sparc/c1_LIR_sparc.cpp ---- a/src/hotspot/cpu/sparc/c1_LIR_sparc.cpp 2024-01-10 05:19:49.000000000 +0800 -+++ b/src/hotspot/cpu/sparc/c1_LIR_sparc.cpp 2024-01-30 10:00:11.878097961 +0800 -@@ -54,3 +54,24 @@ +diff --git a/src/hotspot/cpu/sparc/c1_LIR_sparc.cpp b/src/hotspot/cpu/sparc/c1_LIR_sparc.cpp +index c21d2c1d9a..9cebb387e2 100644 +--- a/src/hotspot/cpu/sparc/c1_LIR_sparc.cpp ++++ b/src/hotspot/cpu/sparc/c1_LIR_sparc.cpp +@@ -54,3 +54,24 @@ void LIR_Address::verify() const { "wrong type for addresses"); } #endif // PRODUCT @@ -104349,10 +104675,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h + cmp(condition, left, right); + cmove(condition, src1, src2, dst, type); +} -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/x86/c1_LIRAssembler_x86.cpp b/src/hotspot/cpu/x86/c1_LIRAssembler_x86.cpp ---- a/src/hotspot/cpu/x86/c1_LIRAssembler_x86.cpp 2024-01-10 05:19:49.000000000 +0800 -+++ b/src/hotspot/cpu/x86/c1_LIRAssembler_x86.cpp 2024-01-30 10:00:11.888097840 +0800 -@@ -1442,6 +1442,10 @@ +diff --git a/src/hotspot/cpu/x86/c1_LIRAssembler_x86.cpp b/src/hotspot/cpu/x86/c1_LIRAssembler_x86.cpp +index cee3140f4f..7b76eb0b9e 100644 +--- a/src/hotspot/cpu/x86/c1_LIRAssembler_x86.cpp ++++ b/src/hotspot/cpu/x86/c1_LIRAssembler_x86.cpp +@@ -1442,6 +1442,10 @@ void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) { } } @@ -104363,7 +104690,7 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) { LIR_Opr src = op->in_opr(); LIR_Opr dest = op->result_opr(); -@@ -2030,6 +2034,9 @@ +@@ -2030,6 +2034,9 @@ void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, L } } @@ -104373,10 +104700,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack) { assert(info == NULL, "should never be used, idiv/irem and ldiv/lrem not handled by this method"); -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/x86/c1_LIRGenerator_x86.cpp b/src/hotspot/cpu/x86/c1_LIRGenerator_x86.cpp ---- a/src/hotspot/cpu/x86/c1_LIRGenerator_x86.cpp 2024-01-10 05:19:49.000000000 +0800 -+++ b/src/hotspot/cpu/x86/c1_LIRGenerator_x86.cpp 2024-01-30 10:00:11.888097840 +0800 -@@ -255,15 +255,27 @@ +diff --git a/src/hotspot/cpu/x86/c1_LIRGenerator_x86.cpp b/src/hotspot/cpu/x86/c1_LIRGenerator_x86.cpp +index 905708a9fa..1c6774e1d6 100644 +--- a/src/hotspot/cpu/x86/c1_LIRGenerator_x86.cpp ++++ b/src/hotspot/cpu/x86/c1_LIRGenerator_x86.cpp +@@ -255,15 +255,27 @@ void LIRGenerator::increment_counter(LIR_Address* addr, int step) { __ add((LIR_Opr)addr, LIR_OprFact::intConst(step), (LIR_Opr)addr); } @@ -104406,10 +104734,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h bool LIRGenerator::strength_reduce_multiply(LIR_Opr left, jint c, LIR_Opr result, LIR_Opr tmp) { if (tmp->is_valid() && c > 0 && c < max_jint) { -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/x86/c1_LIR_x86.cpp b/src/hotspot/cpu/x86/c1_LIR_x86.cpp ---- a/src/hotspot/cpu/x86/c1_LIR_x86.cpp 2024-01-10 05:19:49.000000000 +0800 -+++ b/src/hotspot/cpu/x86/c1_LIR_x86.cpp 2024-01-30 10:00:11.888097840 +0800 -@@ -72,3 +72,24 @@ +diff --git a/src/hotspot/cpu/x86/c1_LIR_x86.cpp b/src/hotspot/cpu/x86/c1_LIR_x86.cpp +index 92277ee063..20e283e302 100644 +--- a/src/hotspot/cpu/x86/c1_LIR_x86.cpp ++++ b/src/hotspot/cpu/x86/c1_LIR_x86.cpp +@@ -72,3 +72,24 @@ void LIR_Address::verify() const { #endif } #endif // PRODUCT @@ -104434,10 +104763,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h + cmp(condition, left, right); + cmove(condition, src1, src2, dst, type); +} -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/x86/gc/z/zBarrierSetAssembler_x86.cpp b/src/hotspot/cpu/x86/gc/z/zBarrierSetAssembler_x86.cpp ---- a/src/hotspot/cpu/x86/gc/z/zBarrierSetAssembler_x86.cpp 2024-01-10 05:19:49.000000000 +0800 -+++ b/src/hotspot/cpu/x86/gc/z/zBarrierSetAssembler_x86.cpp 2024-01-30 10:00:11.891431134 +0800 -@@ -263,7 +263,8 @@ +diff --git a/src/hotspot/cpu/x86/gc/z/zBarrierSetAssembler_x86.cpp b/src/hotspot/cpu/x86/gc/z/zBarrierSetAssembler_x86.cpp +index 95d7e51501..8d7b623ee7 100644 +--- a/src/hotspot/cpu/x86/gc/z/zBarrierSetAssembler_x86.cpp ++++ b/src/hotspot/cpu/x86/gc/z/zBarrierSetAssembler_x86.cpp +@@ -263,7 +263,8 @@ void ZBarrierSetAssembler::try_resolve_jobject_in_native(MacroAssembler* masm, #define __ ce->masm()-> void ZBarrierSetAssembler::generate_c1_load_barrier_test(LIR_Assembler* ce, @@ -104447,10 +104777,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h __ testptr(ref->as_register(), address_bad_mask_from_thread(r15_thread)); } -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/x86/gc/z/zBarrierSetAssembler_x86.hpp b/src/hotspot/cpu/x86/gc/z/zBarrierSetAssembler_x86.hpp ---- a/src/hotspot/cpu/x86/gc/z/zBarrierSetAssembler_x86.hpp 2024-01-10 05:19:49.000000000 +0800 -+++ b/src/hotspot/cpu/x86/gc/z/zBarrierSetAssembler_x86.hpp 2024-01-30 10:00:11.891431134 +0800 -@@ -77,7 +77,8 @@ +diff --git a/src/hotspot/cpu/x86/gc/z/zBarrierSetAssembler_x86.hpp b/src/hotspot/cpu/x86/gc/z/zBarrierSetAssembler_x86.hpp +index 3687754e71..791e4ed43f 100644 +--- a/src/hotspot/cpu/x86/gc/z/zBarrierSetAssembler_x86.hpp ++++ b/src/hotspot/cpu/x86/gc/z/zBarrierSetAssembler_x86.hpp +@@ -77,7 +77,8 @@ public: #ifdef COMPILER1 void generate_c1_load_barrier_test(LIR_Assembler* ce, @@ -104460,9 +104791,10 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h void generate_c1_load_barrier_stub(LIR_Assembler* ce, ZLoadBarrierStubC1* stub) const; -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/os/linux/os_linux.cpp b/src/hotspot/os/linux/os_linux.cpp ---- a/src/hotspot/os/linux/os_linux.cpp 2024-01-10 05:19:49.000000000 +0800 -+++ b/src/hotspot/os/linux/os_linux.cpp 2024-01-30 10:00:11.914764190 +0800 +diff --git a/src/hotspot/os/linux/os_linux.cpp b/src/hotspot/os/linux/os_linux.cpp +index 0af357ea56..66a8006780 100644 +--- a/src/hotspot/os/linux/os_linux.cpp ++++ b/src/hotspot/os/linux/os_linux.cpp @@ -23,6 +23,12 @@ * */ @@ -104476,7 +104808,7 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h // no precompiled headers #include "jvm.h" #include "classfile/classLoader.hpp" -@@ -4076,6 +4082,8 @@ +@@ -4068,6 +4074,8 @@ size_t os::Linux::find_large_page_size() { IA64_ONLY(256 * M) PPC_ONLY(4 * M) S390_ONLY(1 * M) @@ -104485,9 +104817,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h SPARC_ONLY(4 * M); #endif // ZERO -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/os_cpu/linux_loongarch/assembler_linux_loongarch.cpp b/src/hotspot/os_cpu/linux_loongarch/assembler_linux_loongarch.cpp ---- a/src/hotspot/os_cpu/linux_loongarch/assembler_linux_loongarch.cpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/os_cpu/linux_loongarch/assembler_linux_loongarch.cpp 2024-01-30 10:00:11.931430657 +0800 +diff --git a/src/hotspot/os_cpu/linux_loongarch/assembler_linux_loongarch.cpp b/src/hotspot/os_cpu/linux_loongarch/assembler_linux_loongarch.cpp +new file mode 100644 +index 0000000000..30719a0340 +--- /dev/null ++++ b/src/hotspot/os_cpu/linux_loongarch/assembler_linux_loongarch.cpp @@ -0,0 +1,24 @@ +/* + * Copyright (c) 1999, 2010, Oracle and/or its affiliates. All rights reserved. @@ -104513,9 +104847,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h + * questions. + * + */ -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/os_cpu/linux_loongarch/atomic_linux_loongarch.hpp b/src/hotspot/os_cpu/linux_loongarch/atomic_linux_loongarch.hpp ---- a/src/hotspot/os_cpu/linux_loongarch/atomic_linux_loongarch.hpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/os_cpu/linux_loongarch/atomic_linux_loongarch.hpp 2024-01-30 10:00:11.931430657 +0800 +diff --git a/src/hotspot/os_cpu/linux_loongarch/atomic_linux_loongarch.hpp b/src/hotspot/os_cpu/linux_loongarch/atomic_linux_loongarch.hpp +new file mode 100644 +index 0000000000..8403e7838a +--- /dev/null ++++ b/src/hotspot/os_cpu/linux_loongarch/atomic_linux_loongarch.hpp @@ -0,0 +1,160 @@ +/* + * Copyright (c) 1999, 2013, Oracle and/or its affiliates. All rights reserved. @@ -104677,9 +105013,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h + + +#endif // OS_CPU_LINUX_LOONGARCH_ATOMIC_LINUX_LOONGARCH_HPP -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/os_cpu/linux_loongarch/bytes_linux_loongarch.inline.hpp b/src/hotspot/os_cpu/linux_loongarch/bytes_linux_loongarch.inline.hpp ---- a/src/hotspot/os_cpu/linux_loongarch/bytes_linux_loongarch.inline.hpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/os_cpu/linux_loongarch/bytes_linux_loongarch.inline.hpp 2024-01-30 10:00:11.931430657 +0800 +diff --git a/src/hotspot/os_cpu/linux_loongarch/bytes_linux_loongarch.inline.hpp b/src/hotspot/os_cpu/linux_loongarch/bytes_linux_loongarch.inline.hpp +new file mode 100644 +index 0000000000..c9f675baca +--- /dev/null ++++ b/src/hotspot/os_cpu/linux_loongarch/bytes_linux_loongarch.inline.hpp @@ -0,0 +1,37 @@ +/* + * Copyright (c) 1999, 2010, Oracle and/or its affiliates. All rights reserved. @@ -104718,9 +105056,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h +inline u8 Bytes::swap_u8(u8 x) { return bswap_64(x); } + +#endif // OS_CPU_LINUX_LOONGARCH_BYTES_LINUX_LOONGARCH_INLINE_HPP -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/os_cpu/linux_loongarch/copy_linux_loongarch.inline.hpp b/src/hotspot/os_cpu/linux_loongarch/copy_linux_loongarch.inline.hpp ---- a/src/hotspot/os_cpu/linux_loongarch/copy_linux_loongarch.inline.hpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/os_cpu/linux_loongarch/copy_linux_loongarch.inline.hpp 2024-01-30 10:00:11.931430657 +0800 +diff --git a/src/hotspot/os_cpu/linux_loongarch/copy_linux_loongarch.inline.hpp b/src/hotspot/os_cpu/linux_loongarch/copy_linux_loongarch.inline.hpp +new file mode 100644 +index 0000000000..826c1fe39a +--- /dev/null ++++ b/src/hotspot/os_cpu/linux_loongarch/copy_linux_loongarch.inline.hpp @@ -0,0 +1,125 @@ +/* + * Copyright (c) 2003, 2010, Oracle and/or its affiliates. All rights reserved. @@ -104847,9 +105187,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h +} + +#endif // OS_CPU_LINUX_LOONGARCH_COPY_LINUX_LOONGARCH_INLINE_HPP -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/os_cpu/linux_loongarch/globals_linux_loongarch.hpp b/src/hotspot/os_cpu/linux_loongarch/globals_linux_loongarch.hpp ---- a/src/hotspot/os_cpu/linux_loongarch/globals_linux_loongarch.hpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/os_cpu/linux_loongarch/globals_linux_loongarch.hpp 2024-01-30 10:00:11.931430657 +0800 +diff --git a/src/hotspot/os_cpu/linux_loongarch/globals_linux_loongarch.hpp b/src/hotspot/os_cpu/linux_loongarch/globals_linux_loongarch.hpp +new file mode 100644 +index 0000000000..0b5247aa0b +--- /dev/null ++++ b/src/hotspot/os_cpu/linux_loongarch/globals_linux_loongarch.hpp @@ -0,0 +1,43 @@ +/* + * Copyright (c) 2000, 2013, Oracle and/or its affiliates. All rights reserved. @@ -104894,9 +105236,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h +define_pd_global(uintx,HeapBaseMinAddress, 2*G); + +#endif // OS_CPU_LINUX_LOONGARCH_GLOBALS_LINUX_LOONGARCH_HPP -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/os_cpu/linux_loongarch/linux_loongarch.s b/src/hotspot/os_cpu/linux_loongarch/linux_loongarch.s ---- a/src/hotspot/os_cpu/linux_loongarch/linux_loongarch.s 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/os_cpu/linux_loongarch/linux_loongarch.s 2024-01-30 10:00:11.931430657 +0800 +diff --git a/src/hotspot/os_cpu/linux_loongarch/linux_loongarch.s b/src/hotspot/os_cpu/linux_loongarch/linux_loongarch.s +new file mode 100644 +index 0000000000..ebd73af0c5 +--- /dev/null ++++ b/src/hotspot/os_cpu/linux_loongarch/linux_loongarch.s @@ -0,0 +1,25 @@ +# +# Copyright (c) 2004, 2013, Oracle and/or its affiliates. All rights reserved. @@ -104923,9 +105267,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h +# + + -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/os_cpu/linux_loongarch/orderAccess_linux_loongarch.hpp b/src/hotspot/os_cpu/linux_loongarch/orderAccess_linux_loongarch.hpp ---- a/src/hotspot/os_cpu/linux_loongarch/orderAccess_linux_loongarch.hpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/os_cpu/linux_loongarch/orderAccess_linux_loongarch.hpp 2024-01-30 10:00:11.931430657 +0800 +diff --git a/src/hotspot/os_cpu/linux_loongarch/orderAccess_linux_loongarch.hpp b/src/hotspot/os_cpu/linux_loongarch/orderAccess_linux_loongarch.hpp +new file mode 100644 +index 0000000000..5429a1055a +--- /dev/null ++++ b/src/hotspot/os_cpu/linux_loongarch/orderAccess_linux_loongarch.hpp @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2003, 2013, Oracle and/or its affiliates. All rights reserved. @@ -104978,9 +105324,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h +#undef inlasm_sync + +#endif // OS_CPU_LINUX_LOONGARCH_ORDERACCESS_LINUX_LOONGARCH_HPP -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/os_cpu/linux_loongarch/os_linux_loongarch.cpp b/src/hotspot/os_cpu/linux_loongarch/os_linux_loongarch.cpp ---- a/src/hotspot/os_cpu/linux_loongarch/os_linux_loongarch.cpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/os_cpu/linux_loongarch/os_linux_loongarch.cpp 2024-01-30 10:00:11.931430657 +0800 +diff --git a/src/hotspot/os_cpu/linux_loongarch/os_linux_loongarch.cpp b/src/hotspot/os_cpu/linux_loongarch/os_linux_loongarch.cpp +new file mode 100644 +index 0000000000..cf5fff0d04 +--- /dev/null ++++ b/src/hotspot/os_cpu/linux_loongarch/os_linux_loongarch.cpp @@ -0,0 +1,710 @@ +/* + * Copyright (c) 1999, 2014, Oracle and/or its affiliates. All rights reserved. @@ -105692,9 +106040,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h +bool os::is_ActiveCoresMP() { + return UseActiveCoresMP && _initial_active_processor_count == 1; +} -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/os_cpu/linux_loongarch/os_linux_loongarch.hpp b/src/hotspot/os_cpu/linux_loongarch/os_linux_loongarch.hpp ---- a/src/hotspot/os_cpu/linux_loongarch/os_linux_loongarch.hpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/os_cpu/linux_loongarch/os_linux_loongarch.hpp 2024-01-30 10:00:11.931430657 +0800 +diff --git a/src/hotspot/os_cpu/linux_loongarch/os_linux_loongarch.hpp b/src/hotspot/os_cpu/linux_loongarch/os_linux_loongarch.hpp +new file mode 100644 +index 0000000000..fa02f8ba2f +--- /dev/null ++++ b/src/hotspot/os_cpu/linux_loongarch/os_linux_loongarch.hpp @@ -0,0 +1,38 @@ +/* + * Copyright (c) 1999, 2013, Oracle and/or its affiliates. All rights reserved. @@ -105734,9 +106084,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h + static bool is_ActiveCoresMP(); + +#endif // OS_CPU_LINUX_LOONGARCH_OS_LINUX_LOONGARCH_HPP -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/os_cpu/linux_loongarch/prefetch_linux_loongarch.inline.hpp b/src/hotspot/os_cpu/linux_loongarch/prefetch_linux_loongarch.inline.hpp ---- a/src/hotspot/os_cpu/linux_loongarch/prefetch_linux_loongarch.inline.hpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/os_cpu/linux_loongarch/prefetch_linux_loongarch.inline.hpp 2024-01-30 10:00:11.931430657 +0800 +diff --git a/src/hotspot/os_cpu/linux_loongarch/prefetch_linux_loongarch.inline.hpp b/src/hotspot/os_cpu/linux_loongarch/prefetch_linux_loongarch.inline.hpp +new file mode 100644 +index 0000000000..cf3a596387 +--- /dev/null ++++ b/src/hotspot/os_cpu/linux_loongarch/prefetch_linux_loongarch.inline.hpp @@ -0,0 +1,56 @@ +/* + * Copyright (c) 2003, 2010, Oracle and/or its affiliates. All rights reserved. @@ -105794,9 +106146,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h +} + +#endif // OS_CPU_LINUX_LOONGARCH_PREFETCH_LINUX_LOONGARCH_INLINE_HPP -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/os_cpu/linux_loongarch/thread_linux_loongarch.cpp b/src/hotspot/os_cpu/linux_loongarch/thread_linux_loongarch.cpp ---- a/src/hotspot/os_cpu/linux_loongarch/thread_linux_loongarch.cpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/os_cpu/linux_loongarch/thread_linux_loongarch.cpp 2024-01-30 10:00:11.931430657 +0800 +diff --git a/src/hotspot/os_cpu/linux_loongarch/thread_linux_loongarch.cpp b/src/hotspot/os_cpu/linux_loongarch/thread_linux_loongarch.cpp +new file mode 100644 +index 0000000000..a1a9f181bd +--- /dev/null ++++ b/src/hotspot/os_cpu/linux_loongarch/thread_linux_loongarch.cpp @@ -0,0 +1,116 @@ +/* + * Copyright (c) 2003, 2013, Oracle and/or its affiliates. All rights reserved. @@ -105914,9 +106268,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h +} + +void JavaThread::cache_global_variables() { } -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/os_cpu/linux_loongarch/thread_linux_loongarch.hpp b/src/hotspot/os_cpu/linux_loongarch/thread_linux_loongarch.hpp ---- a/src/hotspot/os_cpu/linux_loongarch/thread_linux_loongarch.hpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/os_cpu/linux_loongarch/thread_linux_loongarch.hpp 2024-01-30 10:00:11.931430657 +0800 +diff --git a/src/hotspot/os_cpu/linux_loongarch/thread_linux_loongarch.hpp b/src/hotspot/os_cpu/linux_loongarch/thread_linux_loongarch.hpp +new file mode 100644 +index 0000000000..a3ac28ebd3 +--- /dev/null ++++ b/src/hotspot/os_cpu/linux_loongarch/thread_linux_loongarch.hpp @@ -0,0 +1,66 @@ +/* + * Copyright (c) 2000, 2013, Oracle and/or its affiliates. All rights reserved. @@ -105984,9 +106340,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h + static void disable_register_stack_guard() {} + +#endif // OS_CPU_LINUX_LOONGARCH_VM_THREAD_LINUX_LOONGARCH_HPP -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/os_cpu/linux_loongarch/vmStructs_linux_loongarch.hpp b/src/hotspot/os_cpu/linux_loongarch/vmStructs_linux_loongarch.hpp ---- a/src/hotspot/os_cpu/linux_loongarch/vmStructs_linux_loongarch.hpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/os_cpu/linux_loongarch/vmStructs_linux_loongarch.hpp 2024-01-30 10:00:11.931430657 +0800 +diff --git a/src/hotspot/os_cpu/linux_loongarch/vmStructs_linux_loongarch.hpp b/src/hotspot/os_cpu/linux_loongarch/vmStructs_linux_loongarch.hpp +new file mode 100644 +index 0000000000..a39cb79bb1 +--- /dev/null ++++ b/src/hotspot/os_cpu/linux_loongarch/vmStructs_linux_loongarch.hpp @@ -0,0 +1,55 @@ +/* + * Copyright (c) 2000, 2013, Oracle and/or its affiliates. All rights reserved. @@ -106043,9 +106401,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h +#define VM_LONG_CONSTANTS_OS_CPU(declare_constant, declare_preprocessor_constant, declare_c1_constant, declare_c2_constant, declare_c2_preprocessor_constant) + +#endif // OS_CPU_LINUX_LOONGARCH_VMSTRUCTS_LINUX_LOONGARCH_HPP -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/os_cpu/linux_loongarch/vm_version_linux_loongarch.cpp b/src/hotspot/os_cpu/linux_loongarch/vm_version_linux_loongarch.cpp ---- a/src/hotspot/os_cpu/linux_loongarch/vm_version_linux_loongarch.cpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/os_cpu/linux_loongarch/vm_version_linux_loongarch.cpp 2024-01-30 10:00:11.931430657 +0800 +diff --git a/src/hotspot/os_cpu/linux_loongarch/vm_version_linux_loongarch.cpp b/src/hotspot/os_cpu/linux_loongarch/vm_version_linux_loongarch.cpp +new file mode 100644 +index 0000000000..edc148ef91 +--- /dev/null ++++ b/src/hotspot/os_cpu/linux_loongarch/vm_version_linux_loongarch.cpp @@ -0,0 +1,93 @@ +/* + * Copyright (c) 2006, 2021, Oracle and/or its affiliates. All rights reserved. @@ -106140,9 +106500,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h + HWCAP_LOONGARCH_LBT_ARM | + HWCAP_LOONGARCH_LBT_MIPS); +} -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/os_cpu/linux_mips/assembler_linux_mips.cpp b/src/hotspot/os_cpu/linux_mips/assembler_linux_mips.cpp ---- a/src/hotspot/os_cpu/linux_mips/assembler_linux_mips.cpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/os_cpu/linux_mips/assembler_linux_mips.cpp 2024-01-30 10:00:11.931430657 +0800 +diff --git a/src/hotspot/os_cpu/linux_mips/assembler_linux_mips.cpp b/src/hotspot/os_cpu/linux_mips/assembler_linux_mips.cpp +new file mode 100644 +index 0000000000..30719a0340 +--- /dev/null ++++ b/src/hotspot/os_cpu/linux_mips/assembler_linux_mips.cpp @@ -0,0 +1,24 @@ +/* + * Copyright (c) 1999, 2010, Oracle and/or its affiliates. All rights reserved. @@ -106168,9 +106530,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h + * questions. + * + */ -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/os_cpu/linux_mips/atomic_linux_mips.hpp b/src/hotspot/os_cpu/linux_mips/atomic_linux_mips.hpp ---- a/src/hotspot/os_cpu/linux_mips/atomic_linux_mips.hpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/os_cpu/linux_mips/atomic_linux_mips.hpp 2024-01-30 10:00:11.931430657 +0800 +diff --git a/src/hotspot/os_cpu/linux_mips/atomic_linux_mips.hpp b/src/hotspot/os_cpu/linux_mips/atomic_linux_mips.hpp +new file mode 100644 +index 0000000000..cd7cecad63 +--- /dev/null ++++ b/src/hotspot/os_cpu/linux_mips/atomic_linux_mips.hpp @@ -0,0 +1,191 @@ +/* + * Copyright (c) 1999, 2013, Oracle and/or its affiliates. All rights reserved. @@ -106363,9 +106727,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h + + +#endif // OS_CPU_LINUX_MIPS_VM_ATOMIC_LINUX_MIPS_HPP -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/os_cpu/linux_mips/bytes_linux_mips.inline.hpp b/src/hotspot/os_cpu/linux_mips/bytes_linux_mips.inline.hpp ---- a/src/hotspot/os_cpu/linux_mips/bytes_linux_mips.inline.hpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/os_cpu/linux_mips/bytes_linux_mips.inline.hpp 2024-01-30 10:00:11.931430657 +0800 +diff --git a/src/hotspot/os_cpu/linux_mips/bytes_linux_mips.inline.hpp b/src/hotspot/os_cpu/linux_mips/bytes_linux_mips.inline.hpp +new file mode 100644 +index 0000000000..5b5cd10aa5 +--- /dev/null ++++ b/src/hotspot/os_cpu/linux_mips/bytes_linux_mips.inline.hpp @@ -0,0 +1,37 @@ +/* + * Copyright (c) 1999, 2010, Oracle and/or its affiliates. All rights reserved. @@ -106404,9 +106770,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h +inline u8 Bytes::swap_u8(u8 x) { return bswap_64(x); } + +#endif // OS_CPU_LINUX_MIPS_VM_BYTES_LINUX_MIPS_INLINE_HPP -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/os_cpu/linux_mips/copy_linux_mips.inline.hpp b/src/hotspot/os_cpu/linux_mips/copy_linux_mips.inline.hpp ---- a/src/hotspot/os_cpu/linux_mips/copy_linux_mips.inline.hpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/os_cpu/linux_mips/copy_linux_mips.inline.hpp 2024-01-30 10:00:11.931430657 +0800 +diff --git a/src/hotspot/os_cpu/linux_mips/copy_linux_mips.inline.hpp b/src/hotspot/os_cpu/linux_mips/copy_linux_mips.inline.hpp +new file mode 100644 +index 0000000000..3fd6ef7b36 +--- /dev/null ++++ b/src/hotspot/os_cpu/linux_mips/copy_linux_mips.inline.hpp @@ -0,0 +1,125 @@ +/* + * Copyright (c) 2003, 2010, Oracle and/or its affiliates. All rights reserved. @@ -106533,9 +106901,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h +} + +#endif // OS_CPU_LINUX_MIPS_VM_COPY_LINUX_MIPS_INLINE_HPP -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/os_cpu/linux_mips/globals_linux_mips.hpp b/src/hotspot/os_cpu/linux_mips/globals_linux_mips.hpp ---- a/src/hotspot/os_cpu/linux_mips/globals_linux_mips.hpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/os_cpu/linux_mips/globals_linux_mips.hpp 2024-01-30 10:00:11.931430657 +0800 +diff --git a/src/hotspot/os_cpu/linux_mips/globals_linux_mips.hpp b/src/hotspot/os_cpu/linux_mips/globals_linux_mips.hpp +new file mode 100644 +index 0000000000..f1599ac5f1 +--- /dev/null ++++ b/src/hotspot/os_cpu/linux_mips/globals_linux_mips.hpp @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2000, 2013, Oracle and/or its affiliates. All rights reserved. @@ -106588,9 +106958,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h +define_pd_global(uintx,HeapBaseMinAddress, 2*G); + +#endif // OS_CPU_LINUX_MIPS_VM_GLOBALS_LINUX_MIPS_HPP -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/os_cpu/linux_mips/linux_mips.s b/src/hotspot/os_cpu/linux_mips/linux_mips.s ---- a/src/hotspot/os_cpu/linux_mips/linux_mips.s 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/os_cpu/linux_mips/linux_mips.s 2024-01-30 10:00:11.931430657 +0800 +diff --git a/src/hotspot/os_cpu/linux_mips/linux_mips.s b/src/hotspot/os_cpu/linux_mips/linux_mips.s +new file mode 100644 +index 0000000000..36c8d810c3 +--- /dev/null ++++ b/src/hotspot/os_cpu/linux_mips/linux_mips.s @@ -0,0 +1,25 @@ +# +# Copyright (c) 2004, 2013, Oracle and/or its affiliates. All rights reserved. @@ -106617,9 +106989,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h +# + + -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/os_cpu/linux_mips/orderAccess_linux_mips.hpp b/src/hotspot/os_cpu/linux_mips/orderAccess_linux_mips.hpp ---- a/src/hotspot/os_cpu/linux_mips/orderAccess_linux_mips.hpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/os_cpu/linux_mips/orderAccess_linux_mips.hpp 2024-01-30 10:00:11.931430657 +0800 +diff --git a/src/hotspot/os_cpu/linux_mips/orderAccess_linux_mips.hpp b/src/hotspot/os_cpu/linux_mips/orderAccess_linux_mips.hpp +new file mode 100644 +index 0000000000..bf9d679730 +--- /dev/null ++++ b/src/hotspot/os_cpu/linux_mips/orderAccess_linux_mips.hpp @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2003, 2013, Oracle and/or its affiliates. All rights reserved. @@ -106672,9 +107046,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h +#undef inlasm_sync + +#endif // OS_CPU_LINUX_MIPS_VM_ORDERACCESS_LINUX_MIPS_HPP -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/os_cpu/linux_mips/os_linux_mips.cpp b/src/hotspot/os_cpu/linux_mips/os_linux_mips.cpp ---- a/src/hotspot/os_cpu/linux_mips/os_linux_mips.cpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/os_cpu/linux_mips/os_linux_mips.cpp 2024-01-30 10:00:11.931430657 +0800 +diff --git a/src/hotspot/os_cpu/linux_mips/os_linux_mips.cpp b/src/hotspot/os_cpu/linux_mips/os_linux_mips.cpp +new file mode 100644 +index 0000000000..d035d8edbb +--- /dev/null ++++ b/src/hotspot/os_cpu/linux_mips/os_linux_mips.cpp @@ -0,0 +1,1020 @@ +/* + * Copyright (c) 1999, 2014, Oracle and/or its affiliates. All rights reserved. @@ -107696,9 +108072,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h +bool os::is_ActiveCoresMP() { + return UseActiveCoresMP && _initial_active_processor_count == 1; +} -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/os_cpu/linux_mips/os_linux_mips.hpp b/src/hotspot/os_cpu/linux_mips/os_linux_mips.hpp ---- a/src/hotspot/os_cpu/linux_mips/os_linux_mips.hpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/os_cpu/linux_mips/os_linux_mips.hpp 2024-01-30 10:00:11.931430657 +0800 +diff --git a/src/hotspot/os_cpu/linux_mips/os_linux_mips.hpp b/src/hotspot/os_cpu/linux_mips/os_linux_mips.hpp +new file mode 100644 +index 0000000000..c07d08156f +--- /dev/null ++++ b/src/hotspot/os_cpu/linux_mips/os_linux_mips.hpp @@ -0,0 +1,39 @@ +/* + * Copyright (c) 1999, 2013, Oracle and/or its affiliates. All rights reserved. @@ -107739,9 +108117,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h + static bool is_ActiveCoresMP(); + +#endif // OS_CPU_LINUX_MIPS_VM_OS_LINUX_MIPS_HPP -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/os_cpu/linux_mips/prefetch_linux_mips.inline.hpp b/src/hotspot/os_cpu/linux_mips/prefetch_linux_mips.inline.hpp ---- a/src/hotspot/os_cpu/linux_mips/prefetch_linux_mips.inline.hpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/os_cpu/linux_mips/prefetch_linux_mips.inline.hpp 2024-01-30 10:00:11.931430657 +0800 +diff --git a/src/hotspot/os_cpu/linux_mips/prefetch_linux_mips.inline.hpp b/src/hotspot/os_cpu/linux_mips/prefetch_linux_mips.inline.hpp +new file mode 100644 +index 0000000000..93490345f0 +--- /dev/null ++++ b/src/hotspot/os_cpu/linux_mips/prefetch_linux_mips.inline.hpp @@ -0,0 +1,58 @@ +/* + * Copyright (c) 2003, 2010, Oracle and/or its affiliates. All rights reserved. @@ -107801,9 +108181,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h +} + +#endif // OS_CPU_LINUX_MIPS_VM_PREFETCH_LINUX_MIPS_INLINE_HPP -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/os_cpu/linux_mips/thread_linux_mips.cpp b/src/hotspot/os_cpu/linux_mips/thread_linux_mips.cpp ---- a/src/hotspot/os_cpu/linux_mips/thread_linux_mips.cpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/os_cpu/linux_mips/thread_linux_mips.cpp 2024-01-30 10:00:11.931430657 +0800 +diff --git a/src/hotspot/os_cpu/linux_mips/thread_linux_mips.cpp b/src/hotspot/os_cpu/linux_mips/thread_linux_mips.cpp +new file mode 100644 +index 0000000000..dbe8efe164 +--- /dev/null ++++ b/src/hotspot/os_cpu/linux_mips/thread_linux_mips.cpp @@ -0,0 +1,117 @@ +/* + * Copyright (c) 2003, 2013, Oracle and/or its affiliates. All rights reserved. @@ -107922,9 +108304,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h +} + +void JavaThread::cache_global_variables() { } -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/os_cpu/linux_mips/thread_linux_mips.hpp b/src/hotspot/os_cpu/linux_mips/thread_linux_mips.hpp ---- a/src/hotspot/os_cpu/linux_mips/thread_linux_mips.hpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/os_cpu/linux_mips/thread_linux_mips.hpp 2024-01-30 10:00:11.931430657 +0800 +diff --git a/src/hotspot/os_cpu/linux_mips/thread_linux_mips.hpp b/src/hotspot/os_cpu/linux_mips/thread_linux_mips.hpp +new file mode 100644 +index 0000000000..8b8dbe219c +--- /dev/null ++++ b/src/hotspot/os_cpu/linux_mips/thread_linux_mips.hpp @@ -0,0 +1,66 @@ +/* + * Copyright (c) 2000, 2013, Oracle and/or its affiliates. All rights reserved. @@ -107992,9 +108376,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h + static void disable_register_stack_guard() {} + +#endif // OS_CPU_LINUX_MIPS_VM_THREAD_LINUX_MIPS_HPP -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/os_cpu/linux_mips/vmStructs_linux_mips.hpp b/src/hotspot/os_cpu/linux_mips/vmStructs_linux_mips.hpp ---- a/src/hotspot/os_cpu/linux_mips/vmStructs_linux_mips.hpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/os_cpu/linux_mips/vmStructs_linux_mips.hpp 2024-01-30 10:00:11.931430657 +0800 +diff --git a/src/hotspot/os_cpu/linux_mips/vmStructs_linux_mips.hpp b/src/hotspot/os_cpu/linux_mips/vmStructs_linux_mips.hpp +new file mode 100644 +index 0000000000..b7454bf045 +--- /dev/null ++++ b/src/hotspot/os_cpu/linux_mips/vmStructs_linux_mips.hpp @@ -0,0 +1,55 @@ +/* + * Copyright (c) 2000, 2013, Oracle and/or its affiliates. All rights reserved. @@ -108051,9 +108437,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h +#define VM_LONG_CONSTANTS_OS_CPU(declare_constant, declare_preprocessor_constant, declare_c1_constant, declare_c2_constant, declare_c2_preprocessor_constant) + +#endif // OS_CPU_LINUX_MIPS_VM_VMSTRUCTS_LINUX_MIPS_HPP -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/os_cpu/linux_mips/vm_version_linux_mips.cpp b/src/hotspot/os_cpu/linux_mips/vm_version_linux_mips.cpp ---- a/src/hotspot/os_cpu/linux_mips/vm_version_linux_mips.cpp 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/hotspot/os_cpu/linux_mips/vm_version_linux_mips.cpp 2024-01-30 10:00:11.931430657 +0800 +diff --git a/src/hotspot/os_cpu/linux_mips/vm_version_linux_mips.cpp b/src/hotspot/os_cpu/linux_mips/vm_version_linux_mips.cpp +new file mode 100644 +index 0000000000..93e4bea04c +--- /dev/null ++++ b/src/hotspot/os_cpu/linux_mips/vm_version_linux_mips.cpp @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2006, 2010, Oracle and/or its affiliates. All rights reserved. @@ -108083,19 +108471,21 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h +#include "precompiled.hpp" +#include "runtime/os.hpp" +#include "runtime/vm_version.hpp" -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/os_cpu/linux_x86/gc/z/zGlobals_linux_x86.hpp b/src/hotspot/os_cpu/linux_x86/gc/z/zGlobals_linux_x86.hpp ---- a/src/hotspot/os_cpu/linux_x86/gc/z/zGlobals_linux_x86.hpp 2024-01-10 05:19:49.000000000 +0800 -+++ b/src/hotspot/os_cpu/linux_x86/gc/z/zGlobals_linux_x86.hpp 2024-01-30 10:00:11.934763950 +0800 -@@ -85,4 +85,6 @@ +diff --git a/src/hotspot/os_cpu/linux_x86/gc/z/zGlobals_linux_x86.hpp b/src/hotspot/os_cpu/linux_x86/gc/z/zGlobals_linux_x86.hpp +index 2b0fa83c1a..270e0bc180 100644 +--- a/src/hotspot/os_cpu/linux_x86/gc/z/zGlobals_linux_x86.hpp ++++ b/src/hotspot/os_cpu/linux_x86/gc/z/zGlobals_linux_x86.hpp +@@ -85,4 +85,6 @@ const uintptr_t ZPlatformAddressSpaceSize = ((uintptr_t)1 << ZPlatformAddres const size_t ZPlatformCacheLineSize = 64; +const bool ZPlatformLoadBarrierTestResultInRegister = false; + #endif // OS_CPU_LINUX_X86_ZGLOBALS_LINUX_X86_HPP -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/share/asm/codeBuffer.cpp b/src/hotspot/share/asm/codeBuffer.cpp ---- a/src/hotspot/share/asm/codeBuffer.cpp 2024-01-10 05:19:49.000000000 +0800 -+++ b/src/hotspot/share/asm/codeBuffer.cpp 2024-01-30 10:00:11.944763831 +0800 +diff --git a/src/hotspot/share/asm/codeBuffer.cpp b/src/hotspot/share/asm/codeBuffer.cpp +index 4912f88056..a420f7807b 100644 +--- a/src/hotspot/share/asm/codeBuffer.cpp ++++ b/src/hotspot/share/asm/codeBuffer.cpp @@ -22,6 +22,12 @@ * */ @@ -108109,7 +108499,7 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h #include "precompiled.hpp" #include "asm/codeBuffer.hpp" #include "compiler/disassembler.hpp" -@@ -351,6 +357,7 @@ +@@ -351,6 +357,7 @@ void CodeSection::relocate(address at, RelocationHolder const& spec, int format) assert(rtype == relocInfo::none || rtype == relocInfo::runtime_call_type || rtype == relocInfo::internal_word_type|| @@ -108117,9 +108507,10 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h rtype == relocInfo::section_word_type || rtype == relocInfo::external_word_type, "code needs relocation information"); -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/share/c1/c1_Compiler.cpp b/src/hotspot/share/c1/c1_Compiler.cpp ---- a/src/hotspot/share/c1/c1_Compiler.cpp 2024-01-10 05:19:49.000000000 +0800 -+++ b/src/hotspot/share/c1/c1_Compiler.cpp 2024-01-30 10:00:11.944763831 +0800 +diff --git a/src/hotspot/share/c1/c1_Compiler.cpp b/src/hotspot/share/c1/c1_Compiler.cpp +index aff12954b3..caa93fc804 100644 +--- a/src/hotspot/share/c1/c1_Compiler.cpp ++++ b/src/hotspot/share/c1/c1_Compiler.cpp @@ -44,6 +44,12 @@ #include "utilities/bitMap.inline.hpp" #include "utilities/macros.hpp" @@ -108133,7 +108524,7 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h Compiler::Compiler() : AbstractCompiler(compiler_c1) { } -@@ -211,7 +217,7 @@ +@@ -211,7 +217,7 @@ bool Compiler::is_intrinsic_supported(const methodHandle& method) { case vmIntrinsics::_updateCRC32: case vmIntrinsics::_updateBytesCRC32: case vmIntrinsics::_updateByteBufferCRC32: @@ -108142,181 +108533,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h case vmIntrinsics::_updateBytesCRC32C: case vmIntrinsics::_updateDirectByteBufferCRC32C: #endif -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/share/c1/c1_LinearScan.cpp b/src/hotspot/share/c1/c1_LinearScan.cpp ---- a/src/hotspot/share/c1/c1_LinearScan.cpp 2024-01-10 05:19:49.000000000 +0800 -+++ b/src/hotspot/share/c1/c1_LinearScan.cpp 2024-01-30 10:00:11.948097125 +0800 -@@ -35,6 +35,12 @@ - #include "runtime/timerTrace.hpp" - #include "utilities/bitMap.inline.hpp" - -+/* -+ * This file has been modified by Loongson Technology in 2022, These -+ * modifications are Copyright (c) 2022, Loongson Technology, and are made -+ * available on the same license terms set forth above. -+ */ -+ - #ifndef PRODUCT - - static LinearScanStatistic _stat_before_alloc; -@@ -1258,6 +1264,23 @@ - } - break; - } -+ case lir_cmp_cmove: { -+ assert(op->as_Op4() != NULL, "lir_cmp_cmove must be LIR_Op4"); -+ LIR_Op4* cmove = (LIR_Op4*)op; -+ -+ LIR_Opr move_from = cmove->in_opr3(); -+ LIR_Opr move_to = cmove->result_opr(); -+ -+ if (move_to->is_register() && move_from->is_register()) { -+ Interval* from = interval_at(reg_num(move_from)); -+ Interval* to = interval_at(reg_num(move_to)); -+ if (from != NULL && to != NULL) { -+ to->set_register_hint(from); -+ TRACE_LINEAR_SCAN(4, tty->print_cr("operation at op_id %d: added hint from interval %d to %d", cmove->id(), from->reg_num(), to->reg_num())); -+ } -+ } -+ break; -+ } - default: - break; - } -@@ -3350,7 +3373,9 @@ - check_live = (move->patch_code() == lir_patch_none); - } - LIR_OpBranch* branch = op->as_OpBranch(); -- if (branch != NULL && branch->stub() != NULL && branch->stub()->is_exception_throw_stub()) { -+ LIR_OpCmpBranch* cmp_branch = op->as_OpCmpBranch(); -+ if ((branch != NULL && branch->stub() != NULL && branch->stub()->is_exception_throw_stub()) || -+ (cmp_branch != NULL && cmp_branch->stub() != NULL && cmp_branch->stub()->is_exception_throw_stub())) { - // Don't bother checking the stub in this case since the - // exception stub will never return to normal control flow. - check_live = false; -@@ -6206,6 +6231,16 @@ - if (branch->ublock() == target_from) { - branch->change_ublock(target_to); - } -+ } else if (op->code() == lir_cmp_branch || op->code() == lir_cmp_float_branch) { -+ assert(op->as_OpCmpBranch() != NULL, "branch must be of type LIR_OpCmpBranch"); -+ LIR_OpCmpBranch* branch = (LIR_OpCmpBranch*)op; -+ -+ if (branch->block() == target_from) { -+ branch->change_block(target_to); -+ } -+ if (branch->ublock() == target_from) { -+ branch->change_ublock(target_to); -+ } - } - } - } -@@ -6328,6 +6363,20 @@ - } - } - } -+ } else if (prev_op->code() == lir_cmp_branch || prev_op->code() == lir_cmp_float_branch) { -+ assert(prev_op->as_OpCmpBranch() != NULL, "branch must be of type LIR_OpCmpBranch"); -+ LIR_OpCmpBranch* prev_branch = (LIR_OpCmpBranch*)prev_op; -+ -+ if (prev_branch->stub() == NULL) { -+ if (prev_branch->block() == code->at(i + 1) && prev_branch->info() == NULL) { -+ TRACE_LINEAR_SCAN(3, tty->print_cr("Negating conditional branch and deleting unconditional branch at end of block B%d", block->block_id())); -+ -+ // eliminate a conditional branch to the immediate successor -+ prev_branch->change_block(last_branch->block()); -+ prev_branch->negate_cond(); -+ instructions->trunc_to(instructions->length() - 1); -+ } -+ } - } - } - } -@@ -6403,6 +6452,13 @@ - assert(op_branch->block() == NULL || code->find(op_branch->block()) != -1, "branch target not valid"); - assert(op_branch->ublock() == NULL || code->find(op_branch->ublock()) != -1, "branch target not valid"); - } -+ -+ LIR_OpCmpBranch* op_cmp_branch = instructions->at(j)->as_OpCmpBranch(); -+ -+ if (op_cmp_branch != NULL) { -+ assert(op_cmp_branch->block() == NULL || code->find(op_cmp_branch->block()) != -1, "branch target not valid"); -+ assert(op_cmp_branch->ublock() == NULL || code->find(op_cmp_branch->ublock()) != -1, "branch target not valid"); -+ } - } - - for (j = 0; j < block->number_of_sux() - 1; j++) { -@@ -6647,6 +6703,24 @@ - break; - } - -+ case lir_cmp_branch: -+ case lir_cmp_float_branch: { -+ LIR_OpCmpBranch* branch = op->as_OpCmpBranch(); -+ if (branch->block() == NULL) { -+ inc_counter(counter_stub_branch); -+ } else { -+ inc_counter(counter_cond_branch); -+ } -+ inc_counter(counter_cmp); -+ break; -+ } -+ -+ case lir_cmp_cmove: { -+ inc_counter(counter_misc_inst); -+ inc_counter(counter_cmp); -+ break; -+ } -+ - case lir_neg: - case lir_add: - case lir_sub: -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/share/c1/c1_LIRAssembler.cpp b/src/hotspot/share/c1/c1_LIRAssembler.cpp ---- a/src/hotspot/share/c1/c1_LIRAssembler.cpp 2024-01-10 05:19:49.000000000 +0800 -+++ b/src/hotspot/share/c1/c1_LIRAssembler.cpp 2024-01-30 10:00:11.948097125 +0800 -@@ -777,6 +777,18 @@ - } - - -+void LIR_Assembler::emit_op4(LIR_Op4* op) { -+ switch (op->code()) { -+ case lir_cmp_cmove: -+ cmp_cmove(op->condition(), op->in_opr1(), op->in_opr2(), op->in_opr3(), op->in_opr4(), op->result_opr(), op->type()); -+ break; -+ -+ default: -+ Unimplemented(); -+ break; -+ } -+} -+ - void LIR_Assembler::build_frame() { - _masm->build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes()); - } -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/share/c1/c1_LIRAssembler.hpp b/src/hotspot/share/c1/c1_LIRAssembler.hpp ---- a/src/hotspot/share/c1/c1_LIRAssembler.hpp 2024-01-10 05:19:49.000000000 +0800 -+++ b/src/hotspot/share/c1/c1_LIRAssembler.hpp 2024-01-30 10:00:11.948097125 +0800 -@@ -190,7 +190,9 @@ - void emit_op1(LIR_Op1* op); - void emit_op2(LIR_Op2* op); - void emit_op3(LIR_Op3* op); -+ void emit_op4(LIR_Op4* op); - void emit_opBranch(LIR_OpBranch* op); -+ void emit_opCmpBranch(LIR_OpCmpBranch* op); - void emit_opLabel(LIR_OpLabel* op); - void emit_arraycopy(LIR_OpArrayCopy* op); - void emit_updatecrc32(LIR_OpUpdateCRC32* op); -@@ -223,6 +225,7 @@ - void comp_mem_op(LIR_Opr src, LIR_Opr result, BasicType type, CodeEmitInfo* info); // info set for null exceptions - void comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr result, LIR_Op2* op); - void cmove(LIR_Condition code, LIR_Opr left, LIR_Opr right, LIR_Opr result, BasicType type); -+ void cmp_cmove(LIR_Condition code, LIR_Opr left, LIR_Opr right, LIR_Opr src1, LIR_Opr src2, LIR_Opr result, BasicType type); - - void call( LIR_OpJavaCall* op, relocInfo::relocType rtype); - void ic_call( LIR_OpJavaCall* op); -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/share/c1/c1_LIR.cpp b/src/hotspot/share/c1/c1_LIR.cpp ---- a/src/hotspot/share/c1/c1_LIR.cpp 2024-01-10 05:19:49.000000000 +0800 -+++ b/src/hotspot/share/c1/c1_LIR.cpp 2024-01-30 10:00:11.948097125 +0800 -@@ -250,6 +250,18 @@ +diff --git a/src/hotspot/share/c1/c1_LIR.cpp b/src/hotspot/share/c1/c1_LIR.cpp +index e30d39f73d..7461b7449a 100644 +--- a/src/hotspot/share/c1/c1_LIR.cpp ++++ b/src/hotspot/share/c1/c1_LIR.cpp +@@ -250,6 +250,18 @@ void LIR_Op2::verify() const { #endif } @@ -108335,7 +108556,7 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, BasicType type, BlockBegin* block) : LIR_Op(lir_branch, LIR_OprFact::illegalOpr, (CodeEmitInfo*)NULL) -@@ -308,6 +320,56 @@ +@@ -308,6 +320,56 @@ void LIR_OpBranch::negate_cond() { } @@ -108392,7 +108613,7 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h LIR_OpTypeCheck::LIR_OpTypeCheck(LIR_Code code, LIR_Opr result, LIR_Opr object, ciKlass* klass, LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3, bool fast_check, CodeEmitInfo* info_for_exception, CodeEmitInfo* info_for_patch, -@@ -509,10 +571,7 @@ +@@ -509,10 +571,7 @@ void LIR_OpVisitState::visit(LIR_Op* op) { assert(opConvert->_info == NULL, "must be"); if (opConvert->_opr->is_valid()) do_input(opConvert->_opr); if (opConvert->_result->is_valid()) do_output(opConvert->_result); @@ -108404,7 +108625,7 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h do_stub(opConvert->_stub); break; -@@ -611,6 +670,25 @@ +@@ -611,6 +670,25 @@ void LIR_OpVisitState::visit(LIR_Op* op) { break; } @@ -108430,7 +108651,7 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h // special handling for cmove: right input operand must not be equal // to the result operand, otherwise the backend fails case lir_cmove: -@@ -711,6 +789,29 @@ +@@ -711,6 +789,29 @@ void LIR_OpVisitState::visit(LIR_Op* op) { break; } @@ -108460,7 +108681,7 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h // LIR_OpJavaCall case lir_static_call: case lir_optvirtual_call: -@@ -1028,6 +1129,13 @@ +@@ -1028,6 +1129,13 @@ void LIR_Op2::emit_code(LIR_Assembler* masm) { masm->emit_op2(this); } @@ -108474,7 +108695,7 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h void LIR_OpAllocArray::emit_code(LIR_Assembler* masm) { masm->emit_alloc_array(this); masm->append_code_stub(stub()); -@@ -1048,6 +1156,10 @@ +@@ -1048,6 +1156,10 @@ void LIR_Op3::emit_code(LIR_Assembler* masm) { masm->emit_op3(this); } @@ -108485,7 +108706,7 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h void LIR_OpLock::emit_code(LIR_Assembler* masm) { masm->emit_lock(this); if (stub()) { -@@ -1424,8 +1536,7 @@ +@@ -1424,8 +1536,7 @@ void LIR_List::null_check(LIR_Opr opr, CodeEmitInfo* info, bool deoptimize_on_nu if (deoptimize_on_null) { // Emit an explicit null check and deoptimize if opr is null CodeStub* deopt = new DeoptimizeStub(info, Deoptimization::Reason_null_check, Deoptimization::Action_none); @@ -108495,7 +108716,7 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h } else { // Emit an implicit null check append(new LIR_Op1(lir_null_check, opr, info)); -@@ -1680,6 +1791,8 @@ +@@ -1680,6 +1791,8 @@ const char * LIR_Op::name() const { case lir_cmp_l2i: s = "cmp_l2i"; break; case lir_ucmp_fd2i: s = "ucomp_fd2i"; break; case lir_cmp_fd2i: s = "comp_fd2i"; break; @@ -108504,7 +108725,7 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h case lir_cmove: s = "cmove"; break; case lir_add: s = "add"; break; case lir_sub: s = "sub"; break; -@@ -1705,6 +1818,8 @@ +@@ -1705,6 +1818,8 @@ const char * LIR_Op::name() const { case lir_irem: s = "irem"; break; case lir_fmad: s = "fmad"; break; case lir_fmaf: s = "fmaf"; break; @@ -108513,7 +108734,7 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h // LIR_OpJavaCall case lir_static_call: s = "static"; break; case lir_optvirtual_call: s = "optvirtual"; break; -@@ -1856,6 +1971,26 @@ +@@ -1856,6 +1971,26 @@ void LIR_OpBranch::print_instr(outputStream* out) const { } } @@ -108540,7 +108761,7 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h void LIR_Op::print_condition(outputStream* out, LIR_Condition cond) { switch(cond) { case lir_cond_equal: out->print("[EQ]"); break; -@@ -1876,12 +2011,9 @@ +@@ -1876,12 +2011,9 @@ void LIR_OpConvert::print_instr(outputStream* out) const { print_bytecode(out, bytecode()); in_opr()->print(out); out->print(" "); result_opr()->print(out); out->print(" "); @@ -108555,11 +108776,10 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h } void LIR_OpConvert::print_bytecode(outputStream* out, Bytecodes::Code code) { -@@ -1978,6 +2110,19 @@ - result_opr()->print(out); +@@ -1979,6 +2111,19 @@ void LIR_Op3::print_instr(outputStream* out) const { } -+ + +// LIR_Op4 +void LIR_Op4::print_instr(outputStream* out) const { + if (code() == lir_cmp_cmove) { @@ -108572,32 +108792,321 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h + result_opr()->print(out); +} + - ++ void LIR_OpLock::print_instr(outputStream* out) const { hdr_opr()->print(out); out->print(" "); -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/share/c1/c1_LIRGenerator.cpp b/src/hotspot/share/c1/c1_LIRGenerator.cpp ---- a/src/hotspot/share/c1/c1_LIRGenerator.cpp 2024-01-10 05:19:49.000000000 +0800 -+++ b/src/hotspot/share/c1/c1_LIRGenerator.cpp 2024-01-30 10:00:11.948097125 +0800 -@@ -480,13 +480,11 @@ + obj_opr()->print(out); out->print(" "); +diff --git a/src/hotspot/share/c1/c1_LIR.hpp b/src/hotspot/share/c1/c1_LIR.hpp +index 3234ca018b..1f46e44c77 100644 +--- a/src/hotspot/share/c1/c1_LIR.hpp ++++ b/src/hotspot/share/c1/c1_LIR.hpp +@@ -864,9 +864,11 @@ class LIR_OpConvert; + class LIR_OpAllocObj; + class LIR_OpRoundFP; + class LIR_Op2; ++class LIR_OpCmpBranch; + class LIR_OpDelay; + class LIR_Op3; + class LIR_OpAllocArray; ++class LIR_Op4; + class LIR_OpCall; + class LIR_OpJavaCall; + class LIR_OpRTCall; +@@ -933,6 +935,8 @@ enum LIR_Code { + , lir_cmp_l2i + , lir_ucmp_fd2i + , lir_cmp_fd2i ++ , lir_cmp_branch ++ , lir_cmp_float_branch + , lir_cmove + , lir_add + , lir_sub +@@ -964,6 +968,9 @@ enum LIR_Code { + , lir_fmad + , lir_fmaf + , end_op3 ++ , begin_op4 ++ , lir_cmp_cmove ++ , end_op4 + , begin_opJavaCall + , lir_static_call + , lir_optvirtual_call +@@ -1128,12 +1135,14 @@ class LIR_Op: public CompilationResourceObj { + virtual LIR_OpAllocObj* as_OpAllocObj() { return NULL; } + virtual LIR_OpRoundFP* as_OpRoundFP() { return NULL; } + virtual LIR_OpBranch* as_OpBranch() { return NULL; } ++ virtual LIR_OpCmpBranch* as_OpCmpBranch() { return NULL; } + virtual LIR_OpRTCall* as_OpRTCall() { return NULL; } + virtual LIR_OpConvert* as_OpConvert() { return NULL; } + virtual LIR_Op0* as_Op0() { return NULL; } + virtual LIR_Op1* as_Op1() { return NULL; } + virtual LIR_Op2* as_Op2() { return NULL; } + virtual LIR_Op3* as_Op3() { return NULL; } ++ virtual LIR_Op4* as_Op4() { return NULL; } + virtual LIR_OpArrayCopy* as_OpArrayCopy() { return NULL; } + virtual LIR_OpUpdateCRC32* as_OpUpdateCRC32() { return NULL; } + virtual LIR_OpTypeCheck* as_OpTypeCheck() { return NULL; } +@@ -1463,15 +1472,18 @@ class LIR_OpConvert: public LIR_Op1 { + private: + Bytecodes::Code _bytecode; + ConversionStub* _stub; ++ LIR_Opr _tmp; + + public: +- LIR_OpConvert(Bytecodes::Code code, LIR_Opr opr, LIR_Opr result, ConversionStub* stub) ++ LIR_OpConvert(Bytecodes::Code code, LIR_Opr opr, LIR_Opr result, ConversionStub* stub, LIR_Opr tmp) + : LIR_Op1(lir_convert, opr, result) + , _stub(stub) +- , _bytecode(code) {} ++ , _bytecode(code) ++ , _tmp(tmp) {} + + Bytecodes::Code bytecode() const { return _bytecode; } + ConversionStub* stub() const { return _stub; } ++ LIR_Opr tmp() const { return _tmp; } + + virtual void emit_code(LIR_Assembler* masm); + virtual LIR_OpConvert* as_OpConvert() { return this; } +@@ -1626,7 +1638,7 @@ class LIR_Op2: public LIR_Op { + , _tmp3(LIR_OprFact::illegalOpr) + , _tmp4(LIR_OprFact::illegalOpr) + , _tmp5(LIR_OprFact::illegalOpr) { +- assert(code == lir_cmp || code == lir_assert, "code check"); ++ assert(code == lir_cmp || code == lir_cmp_branch || code == lir_cmp_float_branch || code == lir_assert, "code check"); + } + + LIR_Op2(LIR_Code code, LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type) +@@ -1658,7 +1670,7 @@ class LIR_Op2: public LIR_Op { + , _tmp3(LIR_OprFact::illegalOpr) + , _tmp4(LIR_OprFact::illegalOpr) + , _tmp5(LIR_OprFact::illegalOpr) { +- assert(code != lir_cmp && is_in_range(code, begin_op2, end_op2), "code check"); ++ assert((code != lir_cmp && code != lir_cmp_branch && code != lir_cmp_float_branch) && is_in_range(code, begin_op2, end_op2), "code check"); + } + + LIR_Op2(LIR_Code code, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, LIR_Opr tmp1, LIR_Opr tmp2 = LIR_OprFact::illegalOpr, +@@ -1674,7 +1686,7 @@ class LIR_Op2: public LIR_Op { + , _tmp3(tmp3) + , _tmp4(tmp4) + , _tmp5(tmp5) { +- assert(code != lir_cmp && is_in_range(code, begin_op2, end_op2), "code check"); ++ assert((code != lir_cmp && code != lir_cmp_branch && code != lir_cmp_float_branch) && is_in_range(code, begin_op2, end_op2), "code check"); + } + + LIR_Opr in_opr1() const { return _opr1; } +@@ -1686,10 +1698,12 @@ class LIR_Op2: public LIR_Op { + LIR_Opr tmp4_opr() const { return _tmp4; } + LIR_Opr tmp5_opr() const { return _tmp5; } + LIR_Condition condition() const { +- assert(code() == lir_cmp || code() == lir_cmove || code() == lir_assert, "only valid for cmp and cmove and assert"); return _condition; ++ assert(code() == lir_cmp || code() == lir_cmp_branch || code() == lir_cmp_float_branch || code() == lir_cmove || code() == lir_assert, "only valid for cmp and cmove and assert"); ++ return _condition; + } + void set_condition(LIR_Condition condition) { +- assert(code() == lir_cmp || code() == lir_cmove, "only valid for cmp and cmove"); _condition = condition; ++ assert(code() == lir_cmp || code() == lir_cmp_branch || code() == lir_cmp_float_branch || code() == lir_cmove, "only valid for cmp and cmove"); ++ _condition = condition; + } + + void set_fpu_stack_size(int size) { _fpu_stack_size = size; } +@@ -1703,6 +1717,43 @@ class LIR_Op2: public LIR_Op { + virtual void print_instr(outputStream* out) const PRODUCT_RETURN; + }; + ++class LIR_OpCmpBranch: public LIR_Op2 { ++ friend class LIR_OpVisitState; ++ ++ private: ++ Label* _label; ++ BlockBegin* _block; // if this is a branch to a block, this is the block ++ BlockBegin* _ublock; // if this is a float-branch, this is the unorderd block ++ CodeStub* _stub; // if this is a branch to a stub, this is the stub ++ ++ public: ++ LIR_OpCmpBranch(LIR_Condition cond, LIR_Opr left, LIR_Opr right, Label* lbl, CodeEmitInfo* info = NULL) ++ : LIR_Op2(lir_cmp_branch, cond, left, right, info) ++ , _label(lbl) ++ , _block(NULL) ++ , _ublock(NULL) ++ , _stub(NULL) { } ++ ++ LIR_OpCmpBranch(LIR_Condition cond, LIR_Opr left, LIR_Opr right, CodeStub* stub, CodeEmitInfo* info = NULL); ++ LIR_OpCmpBranch(LIR_Condition cond, LIR_Opr left, LIR_Opr right, BlockBegin* block, CodeEmitInfo* info = NULL); ++ ++ // for unordered comparisons ++ LIR_OpCmpBranch(LIR_Condition cond, LIR_Opr left, LIR_Opr right, BlockBegin* block, BlockBegin* ublock, CodeEmitInfo* info = NULL); ++ ++ Label* label() const { return _label; } ++ BlockBegin* block() const { return _block; } ++ BlockBegin* ublock() const { return _ublock; } ++ CodeStub* stub() const { return _stub; } ++ ++ void change_block(BlockBegin* b); ++ void change_ublock(BlockBegin* b); ++ void negate_cond(); ++ ++ virtual void emit_code(LIR_Assembler* masm); ++ virtual LIR_OpCmpBranch* as_OpCmpBranch() { return this; } ++ virtual void print_instr(outputStream* out) const PRODUCT_RETURN; ++}; ++ + class LIR_OpAllocArray : public LIR_Op { + friend class LIR_OpVisitState; + +@@ -1767,6 +1818,48 @@ class LIR_Op3: public LIR_Op { + }; + + ++class LIR_Op4: public LIR_Op { ++ friend class LIR_OpVisitState; ++ ++ private: ++ LIR_Opr _opr1; ++ LIR_Opr _opr2; ++ LIR_Opr _opr3; ++ LIR_Opr _opr4; ++ BasicType _type; ++ LIR_Condition _condition; ++ ++ void verify() const; ++ ++ public: ++ LIR_Op4(LIR_Code code, LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr opr3, LIR_Opr opr4, LIR_Opr result, BasicType type) ++ : LIR_Op(code, result, NULL) ++ , _opr1(opr1) ++ , _opr2(opr2) ++ , _opr3(opr3) ++ , _opr4(opr4) ++ , _type(type) ++ , _condition(condition) { ++ assert(is_in_range(code, begin_op4, end_op4), "code check"); ++ assert(type != T_ILLEGAL, "cmove should have type"); ++ } ++ LIR_Opr in_opr1() const { return _opr1; } ++ LIR_Opr in_opr2() const { return _opr2; } ++ LIR_Opr in_opr3() const { return _opr3; } ++ LIR_Opr in_opr4() const { return _opr4; } ++ BasicType type() const { return _type; } ++ LIR_Condition condition() const { ++ assert(code() == lir_cmp_cmove, "only valid for cmp cmove"); return _condition; ++ } ++ void set_condition(LIR_Condition condition) { ++ assert(code() == lir_cmp_cmove, "only valid for cmp cmove"); _condition = condition; ++ } ++ ++ virtual void emit_code(LIR_Assembler* masm); ++ virtual LIR_Op4* as_Op4() { return this; } ++ virtual void print_instr(outputStream* out) const PRODUCT_RETURN; ++}; ++ + //-------------------------------- + class LabelObj: public CompilationResourceObj { + private: +@@ -2115,7 +2208,9 @@ class LIR_List: public CompilationResourceObj { + + void safepoint(LIR_Opr tmp, CodeEmitInfo* info) { append(new LIR_Op1(lir_safepoint, tmp, info)); } + +- void convert(Bytecodes::Code code, LIR_Opr left, LIR_Opr dst, ConversionStub* stub = NULL/*, bool is_32bit = false*/) { append(new LIR_OpConvert(code, left, dst, stub)); } ++ void convert(Bytecodes::Code code, LIR_Opr left, LIR_Opr dst, ConversionStub* stub = NULL, LIR_Opr tmp = LIR_OprFact::illegalOpr) { ++ append(new LIR_OpConvert(code, left, dst, stub, tmp)); ++ } + + void logical_and (LIR_Opr left, LIR_Opr right, LIR_Opr dst) { append(new LIR_Op2(lir_logic_and, left, right, dst)); } + void logical_or (LIR_Opr left, LIR_Opr right, LIR_Opr dst) { append(new LIR_Op2(lir_logic_or, left, right, dst)); } +@@ -2146,6 +2241,15 @@ class LIR_List: public CompilationResourceObj { + cmp(condition, left, LIR_OprFact::intConst(right), info); + } + ++ // machine dependent ++ template ++ void cmp_branch(LIR_Condition condition, LIR_Opr left, LIR_Opr right, BasicType type, T tgt, CodeEmitInfo* info = NULL); ++ template ++ void cmp_branch(LIR_Condition condition, LIR_Opr left, int right, BasicType type, T tgt, CodeEmitInfo* info = NULL) { ++ cmp_branch(condition, left, LIR_OprFact::intConst(right), type, tgt, info); ++ } ++ void cmp_branch(LIR_Condition condition, LIR_Opr left, LIR_Opr right, BasicType type, BlockBegin* block, BlockBegin* unordered); ++ + void cmp_mem_int(LIR_Condition condition, LIR_Opr base, int disp, int c, CodeEmitInfo* info); + void cmp_reg_mem(LIR_Condition condition, LIR_Opr reg, LIR_Address* addr, CodeEmitInfo* info); + +@@ -2153,6 +2257,9 @@ class LIR_List: public CompilationResourceObj { + append(new LIR_Op2(lir_cmove, condition, src1, src2, dst, type)); + } + ++ // machine dependent ++ void cmp_cmove(LIR_Condition condition, LIR_Opr left, LIR_Opr right, LIR_Opr src1, LIR_Opr src2, LIR_Opr dst, BasicType type); ++ + void cas_long(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value, + LIR_Opr t1, LIR_Opr t2, LIR_Opr result = LIR_OprFact::illegalOpr); + void cas_obj(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value, +diff --git a/src/hotspot/share/c1/c1_LIRAssembler.cpp b/src/hotspot/share/c1/c1_LIRAssembler.cpp +index 160483d5f7..bec297ebd2 100644 +--- a/src/hotspot/share/c1/c1_LIRAssembler.cpp ++++ b/src/hotspot/share/c1/c1_LIRAssembler.cpp +@@ -777,6 +777,18 @@ void LIR_Assembler::emit_op2(LIR_Op2* op) { + } + + ++void LIR_Assembler::emit_op4(LIR_Op4* op) { ++ switch (op->code()) { ++ case lir_cmp_cmove: ++ cmp_cmove(op->condition(), op->in_opr1(), op->in_opr2(), op->in_opr3(), op->in_opr4(), op->result_opr(), op->type()); ++ break; ++ ++ default: ++ Unimplemented(); ++ break; ++ } ++} ++ + void LIR_Assembler::build_frame() { + _masm->build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes()); + } +diff --git a/src/hotspot/share/c1/c1_LIRAssembler.hpp b/src/hotspot/share/c1/c1_LIRAssembler.hpp +index 44a5bcbe54..114b155f92 100644 +--- a/src/hotspot/share/c1/c1_LIRAssembler.hpp ++++ b/src/hotspot/share/c1/c1_LIRAssembler.hpp +@@ -190,7 +190,9 @@ class LIR_Assembler: public CompilationResourceObj { + void emit_op1(LIR_Op1* op); + void emit_op2(LIR_Op2* op); + void emit_op3(LIR_Op3* op); ++ void emit_op4(LIR_Op4* op); + void emit_opBranch(LIR_OpBranch* op); ++ void emit_opCmpBranch(LIR_OpCmpBranch* op); + void emit_opLabel(LIR_OpLabel* op); + void emit_arraycopy(LIR_OpArrayCopy* op); + void emit_updatecrc32(LIR_OpUpdateCRC32* op); +@@ -223,6 +225,7 @@ class LIR_Assembler: public CompilationResourceObj { + void comp_mem_op(LIR_Opr src, LIR_Opr result, BasicType type, CodeEmitInfo* info); // info set for null exceptions + void comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr result, LIR_Op2* op); + void cmove(LIR_Condition code, LIR_Opr left, LIR_Opr right, LIR_Opr result, BasicType type); ++ void cmp_cmove(LIR_Condition code, LIR_Opr left, LIR_Opr right, LIR_Opr src1, LIR_Opr src2, LIR_Opr result, BasicType type); + + void call( LIR_OpJavaCall* op, relocInfo::relocType rtype); + void ic_call( LIR_OpJavaCall* op); +diff --git a/src/hotspot/share/c1/c1_LIRGenerator.cpp b/src/hotspot/share/c1/c1_LIRGenerator.cpp +index 88f6d30697..1d5a6668ea 100644 +--- a/src/hotspot/share/c1/c1_LIRGenerator.cpp ++++ b/src/hotspot/share/c1/c1_LIRGenerator.cpp +@@ -480,13 +480,11 @@ void LIRGenerator::array_range_check(LIR_Opr array, LIR_Opr index, CodeEmitInfo* null_check_info, CodeEmitInfo* range_check_info) { CodeStub* stub = new RangeCheckStub(range_check_info, index, array); if (index->is_constant()) { - cmp_mem_int(lir_cond_belowEqual, array, arrayOopDesc::length_offset_in_bytes(), - index->as_jint(), null_check_info); - __ branch(lir_cond_belowEqual, T_INT, stub); // forward branch -- } else { ++ cmp_mem_int_branch(lir_cond_belowEqual, array, arrayOopDesc::length_offset_in_bytes(), ++ index->as_jint(), stub, null_check_info); // forward branch + } else { - cmp_reg_mem(lir_cond_aboveEqual, index, array, - arrayOopDesc::length_offset_in_bytes(), T_INT, null_check_info); - __ branch(lir_cond_aboveEqual, T_INT, stub); // forward branch -+ cmp_mem_int_branch(lir_cond_belowEqual, array, arrayOopDesc::length_offset_in_bytes(), -+ index->as_jint(), stub, null_check_info); // forward branch -+ } else { + cmp_reg_mem_branch(lir_cond_aboveEqual, index, array, arrayOopDesc::length_offset_in_bytes(), + T_INT, stub, null_check_info); // forward branch } } -@@ -494,12 +492,11 @@ +@@ -494,12 +492,11 @@ void LIRGenerator::array_range_check(LIR_Opr array, LIR_Opr index, void LIRGenerator::nio_range_check(LIR_Opr buffer, LIR_Opr index, LIR_Opr result, CodeEmitInfo* info) { CodeStub* stub = new RangeCheckStub(info, index); if (index->is_constant()) { @@ -108614,7 +109123,7 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h } __ move(index, result); } -@@ -935,7 +932,7 @@ +@@ -935,7 +932,7 @@ LIR_Opr LIRGenerator::force_to_spill(LIR_Opr value, BasicType t) { return tmp; } @@ -108623,7 +109132,7 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h if (if_instr->should_profile()) { ciMethod* method = if_instr->profiled_method(); assert(method != NULL, "method should be set if branch is profiled"); -@@ -956,10 +953,17 @@ +@@ -956,10 +953,17 @@ void LIRGenerator::profile_branch(If* if_instr, If::Condition cond) { __ metadata2reg(md->constant_encoding(), md_reg); LIR_Opr data_offset_reg = new_pointer_register(); @@ -108645,7 +109154,7 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h // MDO cells are intptr_t, so the data_reg width is arch-dependent. LIR_Opr data_reg = new_pointer_register(); -@@ -1316,8 +1320,8 @@ +@@ -1316,8 +1320,8 @@ void LIRGenerator::do_isPrimitive(Intrinsic* x) { } __ move(new LIR_Address(rcvr.result(), java_lang_Class::klass_offset_in_bytes(), T_ADDRESS), temp, info); @@ -108656,7 +109165,7 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h } -@@ -1599,8 +1603,8 @@ +@@ -1599,8 +1603,8 @@ void LIRGenerator::do_StoreIndexed(StoreIndexed* x) { if (GenerateRangeChecks && needs_range_check) { if (use_length) { @@ -108667,7 +109176,7 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h } else { array_range_check(array.result(), index.result(), null_check_info, range_check_info); // range_check also does the null check -@@ -1778,12 +1782,9 @@ +@@ -1778,12 +1782,9 @@ void LIRGenerator::do_NIOCheckIndex(Intrinsic* x) { CodeEmitInfo* info = state_for(x); CodeStub* stub = new RangeCheckStub(info, index.result()); if (index.result()->is_constant()) { @@ -108682,7 +109191,7 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h } __ move(index.result(), result); } else { -@@ -1861,8 +1862,8 @@ +@@ -1861,8 +1862,8 @@ void LIRGenerator::do_LoadIndexed(LoadIndexed* x) { } else if (use_length) { // TODO: use a (modified) version of array_range_check that does not require a // constant length to be loaded to a register @@ -108693,7 +109202,7 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h } else { array_range_check(array.result(), index.result(), null_check_info, range_check_info); // The range check performs the null check, so clear it out for the load -@@ -2235,19 +2236,14 @@ +@@ -2235,19 +2236,14 @@ void LIRGenerator::do_SwitchRanges(SwitchRangeArray* x, LIR_Opr value, BlockBegi int high_key = one_range->high_key(); BlockBegin* dest = one_range->sux(); if (low_key == high_key) { @@ -108718,7 +109227,7 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h __ branch_destination(L->label()); } } -@@ -2347,12 +2343,11 @@ +@@ -2347,12 +2343,11 @@ void LIRGenerator::do_TableSwitch(TableSwitch* x) { __ move(LIR_OprFact::intptrConst(default_count_offset), data_offset_reg); for (int i = 0; i < len; i++) { int count_offset = md->byte_offset_of_slot(data, MultiBranchData::case_count_offset(i)); @@ -108735,7 +109244,7 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h } LIR_Opr data_reg = new_pointer_register(); -@@ -2366,8 +2361,7 @@ +@@ -2366,8 +2361,7 @@ void LIRGenerator::do_TableSwitch(TableSwitch* x) { do_SwitchRanges(create_lookup_ranges(x), value, x->default_sux()); } else { for (int i = 0; i < len; i++) { @@ -108745,7 +109254,7 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h } __ jump(x->default_sux()); } -@@ -2405,12 +2399,11 @@ +@@ -2405,12 +2399,11 @@ void LIRGenerator::do_LookupSwitch(LookupSwitch* x) { __ move(LIR_OprFact::intptrConst(default_count_offset), data_offset_reg); for (int i = 0; i < len; i++) { int count_offset = md->byte_offset_of_slot(data, MultiBranchData::case_count_offset(i)); @@ -108762,7 +109271,7 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h } LIR_Opr data_reg = new_pointer_register(); -@@ -2425,8 +2418,7 @@ +@@ -2425,8 +2418,7 @@ void LIRGenerator::do_LookupSwitch(LookupSwitch* x) { } else { int len = x->length(); for (int i = 0; i < len; i++) { @@ -108772,7 +109281,7 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h } __ jump(x->default_sux()); } -@@ -2936,8 +2928,8 @@ +@@ -2936,8 +2928,8 @@ void LIRGenerator::do_IfOp(IfOp* x) { f_val.dont_load_item(); LIR_Opr reg = rlock_result(x); @@ -108783,7 +109292,7 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h } #ifdef JFR_HAVE_INTRINSICS -@@ -2981,8 +2973,7 @@ +@@ -2981,8 +2973,7 @@ void LIRGenerator::do_getEventWriter(Intrinsic* x) { __ move(LIR_OprFact::oopConst(NULL), result); LIR_Opr jobj = new_register(T_METADATA); __ move_wide(jobj_addr, jobj); @@ -108793,7 +109302,7 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h access_load(IN_NATIVE, T_OBJECT, LIR_OprFact::address(new LIR_Address(jobj, T_OBJECT)), result); -@@ -3287,21 +3278,24 @@ +@@ -3287,21 +3278,24 @@ void LIRGenerator::do_ProfileInvoke(ProfileInvoke* x) { void LIRGenerator::increment_backedge_counter_conditionally(LIR_Condition cond, LIR_Opr left, LIR_Opr right, CodeEmitInfo* info, int left_bci, int right_bci, int bci) { if (compilation()->count_backedges()) { @@ -108824,7 +109333,7 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h increment_backedge_counter(info, step, bci); } } -@@ -3340,8 +3334,7 @@ +@@ -3340,8 +3334,7 @@ void LIRGenerator::decrement_age(CodeEmitInfo* info) { // DeoptimizeStub will reexecute from the current state in code info. CodeStub* deopt = new DeoptimizeStub(info, Deoptimization::Reason_tenured, Deoptimization::Action_make_not_entrant); @@ -108834,7 +109343,7 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h } } -@@ -3387,8 +3380,7 @@ +@@ -3387,8 +3380,7 @@ void LIRGenerator::increment_event_counter_impl(CodeEmitInfo* info, int freq = frequency << InvocationCounter::count_shift; if (freq == 0) { if (!step->is_constant()) { @@ -108844,7 +109353,7 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h } else { __ branch(lir_cond_always, T_ILLEGAL, overflow); } -@@ -3396,12 +3388,11 @@ +@@ -3396,12 +3388,11 @@ void LIRGenerator::increment_event_counter_impl(CodeEmitInfo* info, LIR_Opr mask = load_immediate(freq, T_INT); if (!step->is_constant()) { // If step is 0, make sure the overflow check below always fails @@ -108860,7 +109369,7 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h } __ branch_destination(overflow->continuation()); } -@@ -3514,8 +3505,7 @@ +@@ -3514,8 +3505,7 @@ void LIRGenerator::do_RangeCheckPredicate(RangeCheckPredicate *x) { CodeEmitInfo *info = state_for(x, x->state()); CodeStub* stub = new PredicateFailedStub(info); @@ -108870,7 +109379,7 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h } } -@@ -3662,8 +3652,8 @@ +@@ -3662,8 +3652,8 @@ LIR_Opr LIRGenerator::mask_boolean(LIR_Opr array, LIR_Opr value, CodeEmitInfo*& __ move(new LIR_Address(klass, in_bytes(Klass::layout_helper_offset()), T_INT), layout); int diffbit = Klass::layout_helper_boolean_diffbit(); __ logical_and(layout, LIR_OprFact::intConst(diffbit), layout); @@ -108881,10 +109390,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h value = value_fixed; return value; } -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/share/c1/c1_LIRGenerator.hpp b/src/hotspot/share/c1/c1_LIRGenerator.hpp ---- a/src/hotspot/share/c1/c1_LIRGenerator.hpp 2024-01-10 05:19:49.000000000 +0800 -+++ b/src/hotspot/share/c1/c1_LIRGenerator.hpp 2024-01-30 10:00:11.948097125 +0800 -@@ -363,8 +363,10 @@ +diff --git a/src/hotspot/share/c1/c1_LIRGenerator.hpp b/src/hotspot/share/c1/c1_LIRGenerator.hpp +index 3ad325d759..f377b27859 100644 +--- a/src/hotspot/share/c1/c1_LIRGenerator.hpp ++++ b/src/hotspot/share/c1/c1_LIRGenerator.hpp +@@ -363,8 +363,10 @@ class LIRGenerator: public InstructionVisitor, public BlockClosure { void new_instance (LIR_Opr dst, ciInstanceKlass* klass, bool is_unresolved, LIR_Opr scratch1, LIR_Opr scratch2, LIR_Opr scratch3, LIR_Opr scratch4, LIR_Opr klass_reg, CodeEmitInfo* info); // machine dependent @@ -108897,7 +109407,7 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h void arraycopy_helper(Intrinsic* x, int* flags, ciArrayKlass** expected_type); -@@ -391,7 +393,7 @@ +@@ -391,7 +393,7 @@ class LIRGenerator: public InstructionVisitor, public BlockClosure { LIR_Opr safepoint_poll_register(); @@ -108906,251 +109416,139 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h void increment_event_counter_impl(CodeEmitInfo* info, ciMethod *method, LIR_Opr step, int frequency, int bci, bool backedge, bool notify); -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/share/c1/c1_LIR.hpp b/src/hotspot/share/c1/c1_LIR.hpp ---- a/src/hotspot/share/c1/c1_LIR.hpp 2024-01-10 05:19:49.000000000 +0800 -+++ b/src/hotspot/share/c1/c1_LIR.hpp 2024-01-30 10:00:11.948097125 +0800 -@@ -864,9 +864,11 @@ - class LIR_OpAllocObj; - class LIR_OpRoundFP; - class LIR_Op2; -+class LIR_OpCmpBranch; - class LIR_OpDelay; - class LIR_Op3; - class LIR_OpAllocArray; -+class LIR_Op4; - class LIR_OpCall; - class LIR_OpJavaCall; - class LIR_OpRTCall; -@@ -933,6 +935,8 @@ - , lir_cmp_l2i - , lir_ucmp_fd2i - , lir_cmp_fd2i -+ , lir_cmp_branch -+ , lir_cmp_float_branch - , lir_cmove - , lir_add - , lir_sub -@@ -964,6 +968,9 @@ - , lir_fmad - , lir_fmaf - , end_op3 -+ , begin_op4 -+ , lir_cmp_cmove -+ , end_op4 - , begin_opJavaCall - , lir_static_call - , lir_optvirtual_call -@@ -1128,12 +1135,14 @@ - virtual LIR_OpAllocObj* as_OpAllocObj() { return NULL; } - virtual LIR_OpRoundFP* as_OpRoundFP() { return NULL; } - virtual LIR_OpBranch* as_OpBranch() { return NULL; } -+ virtual LIR_OpCmpBranch* as_OpCmpBranch() { return NULL; } - virtual LIR_OpRTCall* as_OpRTCall() { return NULL; } - virtual LIR_OpConvert* as_OpConvert() { return NULL; } - virtual LIR_Op0* as_Op0() { return NULL; } - virtual LIR_Op1* as_Op1() { return NULL; } - virtual LIR_Op2* as_Op2() { return NULL; } - virtual LIR_Op3* as_Op3() { return NULL; } -+ virtual LIR_Op4* as_Op4() { return NULL; } - virtual LIR_OpArrayCopy* as_OpArrayCopy() { return NULL; } - virtual LIR_OpUpdateCRC32* as_OpUpdateCRC32() { return NULL; } - virtual LIR_OpTypeCheck* as_OpTypeCheck() { return NULL; } -@@ -1463,15 +1472,18 @@ - private: - Bytecodes::Code _bytecode; - ConversionStub* _stub; -+ LIR_Opr _tmp; - - public: -- LIR_OpConvert(Bytecodes::Code code, LIR_Opr opr, LIR_Opr result, ConversionStub* stub) -+ LIR_OpConvert(Bytecodes::Code code, LIR_Opr opr, LIR_Opr result, ConversionStub* stub, LIR_Opr tmp) - : LIR_Op1(lir_convert, opr, result) - , _stub(stub) -- , _bytecode(code) {} -+ , _bytecode(code) -+ , _tmp(tmp) {} - - Bytecodes::Code bytecode() const { return _bytecode; } - ConversionStub* stub() const { return _stub; } -+ LIR_Opr tmp() const { return _tmp; } - - virtual void emit_code(LIR_Assembler* masm); - virtual LIR_OpConvert* as_OpConvert() { return this; } -@@ -1626,7 +1638,7 @@ - , _tmp3(LIR_OprFact::illegalOpr) - , _tmp4(LIR_OprFact::illegalOpr) - , _tmp5(LIR_OprFact::illegalOpr) { -- assert(code == lir_cmp || code == lir_assert, "code check"); -+ assert(code == lir_cmp || code == lir_cmp_branch || code == lir_cmp_float_branch || code == lir_assert, "code check"); - } - - LIR_Op2(LIR_Code code, LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type) -@@ -1658,7 +1670,7 @@ - , _tmp3(LIR_OprFact::illegalOpr) - , _tmp4(LIR_OprFact::illegalOpr) - , _tmp5(LIR_OprFact::illegalOpr) { -- assert(code != lir_cmp && is_in_range(code, begin_op2, end_op2), "code check"); -+ assert((code != lir_cmp && code != lir_cmp_branch && code != lir_cmp_float_branch) && is_in_range(code, begin_op2, end_op2), "code check"); - } - - LIR_Op2(LIR_Code code, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, LIR_Opr tmp1, LIR_Opr tmp2 = LIR_OprFact::illegalOpr, -@@ -1674,7 +1686,7 @@ - , _tmp3(tmp3) - , _tmp4(tmp4) - , _tmp5(tmp5) { -- assert(code != lir_cmp && is_in_range(code, begin_op2, end_op2), "code check"); -+ assert((code != lir_cmp && code != lir_cmp_branch && code != lir_cmp_float_branch) && is_in_range(code, begin_op2, end_op2), "code check"); - } - - LIR_Opr in_opr1() const { return _opr1; } -@@ -1686,10 +1698,12 @@ - LIR_Opr tmp4_opr() const { return _tmp4; } - LIR_Opr tmp5_opr() const { return _tmp5; } - LIR_Condition condition() const { -- assert(code() == lir_cmp || code() == lir_cmove || code() == lir_assert, "only valid for cmp and cmove and assert"); return _condition; -+ assert(code() == lir_cmp || code() == lir_cmp_branch || code() == lir_cmp_float_branch || code() == lir_cmove || code() == lir_assert, "only valid for cmp and cmove and assert"); -+ return _condition; - } - void set_condition(LIR_Condition condition) { -- assert(code() == lir_cmp || code() == lir_cmove, "only valid for cmp and cmove"); _condition = condition; -+ assert(code() == lir_cmp || code() == lir_cmp_branch || code() == lir_cmp_float_branch || code() == lir_cmove, "only valid for cmp and cmove"); -+ _condition = condition; - } - - void set_fpu_stack_size(int size) { _fpu_stack_size = size; } -@@ -1703,6 +1717,43 @@ - virtual void print_instr(outputStream* out) const PRODUCT_RETURN; - }; +diff --git a/src/hotspot/share/c1/c1_LinearScan.cpp b/src/hotspot/share/c1/c1_LinearScan.cpp +index acc969ac9c..1637965613 100644 +--- a/src/hotspot/share/c1/c1_LinearScan.cpp ++++ b/src/hotspot/share/c1/c1_LinearScan.cpp +@@ -35,6 +35,12 @@ + #include "runtime/timerTrace.hpp" + #include "utilities/bitMap.inline.hpp" -+class LIR_OpCmpBranch: public LIR_Op2 { -+ friend class LIR_OpVisitState; -+ -+ private: -+ Label* _label; -+ BlockBegin* _block; // if this is a branch to a block, this is the block -+ BlockBegin* _ublock; // if this is a float-branch, this is the unorderd block -+ CodeStub* _stub; // if this is a branch to a stub, this is the stub -+ -+ public: -+ LIR_OpCmpBranch(LIR_Condition cond, LIR_Opr left, LIR_Opr right, Label* lbl, CodeEmitInfo* info = NULL) -+ : LIR_Op2(lir_cmp_branch, cond, left, right, info) -+ , _label(lbl) -+ , _block(NULL) -+ , _ublock(NULL) -+ , _stub(NULL) { } -+ -+ LIR_OpCmpBranch(LIR_Condition cond, LIR_Opr left, LIR_Opr right, CodeStub* stub, CodeEmitInfo* info = NULL); -+ LIR_OpCmpBranch(LIR_Condition cond, LIR_Opr left, LIR_Opr right, BlockBegin* block, CodeEmitInfo* info = NULL); -+ -+ // for unordered comparisons -+ LIR_OpCmpBranch(LIR_Condition cond, LIR_Opr left, LIR_Opr right, BlockBegin* block, BlockBegin* ublock, CodeEmitInfo* info = NULL); -+ -+ Label* label() const { return _label; } -+ BlockBegin* block() const { return _block; } -+ BlockBegin* ublock() const { return _ublock; } -+ CodeStub* stub() const { return _stub; } ++/* ++ * This file has been modified by Loongson Technology in 2022, These ++ * modifications are Copyright (c) 2022, Loongson Technology, and are made ++ * available on the same license terms set forth above. ++ */ + -+ void change_block(BlockBegin* b); -+ void change_ublock(BlockBegin* b); -+ void negate_cond(); + #ifndef PRODUCT + + static LinearScanStatistic _stat_before_alloc; +@@ -1258,6 +1264,23 @@ void LinearScan::add_register_hints(LIR_Op* op) { + } + break; + } ++ case lir_cmp_cmove: { ++ assert(op->as_Op4() != NULL, "lir_cmp_cmove must be LIR_Op4"); ++ LIR_Op4* cmove = (LIR_Op4*)op; + -+ virtual void emit_code(LIR_Assembler* masm); -+ virtual LIR_OpCmpBranch* as_OpCmpBranch() { return this; } -+ virtual void print_instr(outputStream* out) const PRODUCT_RETURN; -+}; ++ LIR_Opr move_from = cmove->in_opr3(); ++ LIR_Opr move_to = cmove->result_opr(); + - class LIR_OpAllocArray : public LIR_Op { - friend class LIR_OpVisitState; - -@@ -1767,6 +1818,48 @@ - }; - ++ if (move_to->is_register() && move_from->is_register()) { ++ Interval* from = interval_at(reg_num(move_from)); ++ Interval* to = interval_at(reg_num(move_to)); ++ if (from != NULL && to != NULL) { ++ to->set_register_hint(from); ++ TRACE_LINEAR_SCAN(4, tty->print_cr("operation at op_id %d: added hint from interval %d to %d", cmove->id(), from->reg_num(), to->reg_num())); ++ } ++ } ++ break; ++ } + default: + break; + } +@@ -3350,7 +3373,9 @@ void LinearScan::verify_no_oops_in_fixed_intervals() { + check_live = (move->patch_code() == lir_patch_none); + } + LIR_OpBranch* branch = op->as_OpBranch(); +- if (branch != NULL && branch->stub() != NULL && branch->stub()->is_exception_throw_stub()) { ++ LIR_OpCmpBranch* cmp_branch = op->as_OpCmpBranch(); ++ if ((branch != NULL && branch->stub() != NULL && branch->stub()->is_exception_throw_stub()) || ++ (cmp_branch != NULL && cmp_branch->stub() != NULL && cmp_branch->stub()->is_exception_throw_stub())) { + // Don't bother checking the stub in this case since the + // exception stub will never return to normal control flow. + check_live = false; +@@ -6200,6 +6225,16 @@ void ControlFlowOptimizer::substitute_branch_target(BlockBegin* block, BlockBegi + assert(op->as_OpBranch() != NULL, "branch must be of type LIR_OpBranch"); + LIR_OpBranch* branch = (LIR_OpBranch*)op; -+class LIR_Op4: public LIR_Op { -+ friend class LIR_OpVisitState; ++ if (branch->block() == target_from) { ++ branch->change_block(target_to); ++ } ++ if (branch->ublock() == target_from) { ++ branch->change_ublock(target_to); ++ } ++ } else if (op->code() == lir_cmp_branch || op->code() == lir_cmp_float_branch) { ++ assert(op->as_OpCmpBranch() != NULL, "branch must be of type LIR_OpCmpBranch"); ++ LIR_OpCmpBranch* branch = (LIR_OpCmpBranch*)op; + -+ private: -+ LIR_Opr _opr1; -+ LIR_Opr _opr2; -+ LIR_Opr _opr3; -+ LIR_Opr _opr4; -+ BasicType _type; -+ LIR_Condition _condition; + if (branch->block() == target_from) { + branch->change_block(target_to); + } +@@ -6328,6 +6363,20 @@ void ControlFlowOptimizer::delete_unnecessary_jumps(BlockList* code) { + } + } + } ++ } else if (prev_op->code() == lir_cmp_branch || prev_op->code() == lir_cmp_float_branch) { ++ assert(prev_op->as_OpCmpBranch() != NULL, "branch must be of type LIR_OpCmpBranch"); ++ LIR_OpCmpBranch* prev_branch = (LIR_OpCmpBranch*)prev_op; + -+ void verify() const; ++ if (prev_branch->stub() == NULL) { ++ if (prev_branch->block() == code->at(i + 1) && prev_branch->info() == NULL) { ++ TRACE_LINEAR_SCAN(3, tty->print_cr("Negating conditional branch and deleting unconditional branch at end of block B%d", block->block_id())); + -+ public: -+ LIR_Op4(LIR_Code code, LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr opr3, LIR_Opr opr4, LIR_Opr result, BasicType type) -+ : LIR_Op(code, result, NULL) -+ , _opr1(opr1) -+ , _opr2(opr2) -+ , _opr3(opr3) -+ , _opr4(opr4) -+ , _type(type) -+ , _condition(condition) { -+ assert(is_in_range(code, begin_op4, end_op4), "code check"); -+ assert(type != T_ILLEGAL, "cmove should have type"); -+ } -+ LIR_Opr in_opr1() const { return _opr1; } -+ LIR_Opr in_opr2() const { return _opr2; } -+ LIR_Opr in_opr3() const { return _opr3; } -+ LIR_Opr in_opr4() const { return _opr4; } -+ BasicType type() const { return _type; } -+ LIR_Condition condition() const { -+ assert(code() == lir_cmp_cmove, "only valid for cmp cmove"); return _condition; -+ } -+ void set_condition(LIR_Condition condition) { -+ assert(code() == lir_cmp_cmove, "only valid for cmp cmove"); _condition = condition; -+ } ++ // eliminate a conditional branch to the immediate successor ++ prev_branch->change_block(last_branch->block()); ++ prev_branch->negate_cond(); ++ instructions->trunc_to(instructions->length() - 1); ++ } ++ } + } + } + } +@@ -6403,6 +6452,13 @@ void ControlFlowOptimizer::verify(BlockList* code) { + assert(op_branch->block() == NULL || code->find(op_branch->block()) != -1, "branch target not valid"); + assert(op_branch->ublock() == NULL || code->find(op_branch->ublock()) != -1, "branch target not valid"); + } + -+ virtual void emit_code(LIR_Assembler* masm); -+ virtual LIR_Op4* as_Op4() { return this; } -+ virtual void print_instr(outputStream* out) const PRODUCT_RETURN; -+}; ++ LIR_OpCmpBranch* op_cmp_branch = instructions->at(j)->as_OpCmpBranch(); + - //-------------------------------- - class LabelObj: public CompilationResourceObj { - private: -@@ -2115,7 +2208,9 @@ - - void safepoint(LIR_Opr tmp, CodeEmitInfo* info) { append(new LIR_Op1(lir_safepoint, tmp, info)); } - -- void convert(Bytecodes::Code code, LIR_Opr left, LIR_Opr dst, ConversionStub* stub = NULL/*, bool is_32bit = false*/) { append(new LIR_OpConvert(code, left, dst, stub)); } -+ void convert(Bytecodes::Code code, LIR_Opr left, LIR_Opr dst, ConversionStub* stub = NULL, LIR_Opr tmp = LIR_OprFact::illegalOpr) { -+ append(new LIR_OpConvert(code, left, dst, stub, tmp)); -+ } ++ if (op_cmp_branch != NULL) { ++ assert(op_cmp_branch->block() == NULL || code->find(op_cmp_branch->block()) != -1, "branch target not valid"); ++ assert(op_cmp_branch->ublock() == NULL || code->find(op_cmp_branch->ublock()) != -1, "branch target not valid"); ++ } + } - void logical_and (LIR_Opr left, LIR_Opr right, LIR_Opr dst) { append(new LIR_Op2(lir_logic_and, left, right, dst)); } - void logical_or (LIR_Opr left, LIR_Opr right, LIR_Opr dst) { append(new LIR_Op2(lir_logic_or, left, right, dst)); } -@@ -2146,6 +2241,15 @@ - cmp(condition, left, LIR_OprFact::intConst(right), info); - } + for (j = 0; j < block->number_of_sux() - 1; j++) { +@@ -6647,6 +6703,24 @@ void LinearScanStatistic::collect(LinearScan* allocator) { + break; + } -+ // machine dependent -+ template -+ void cmp_branch(LIR_Condition condition, LIR_Opr left, LIR_Opr right, BasicType type, T tgt, CodeEmitInfo* info = NULL); -+ template -+ void cmp_branch(LIR_Condition condition, LIR_Opr left, int right, BasicType type, T tgt, CodeEmitInfo* info = NULL) { -+ cmp_branch(condition, left, LIR_OprFact::intConst(right), type, tgt, info); -+ } -+ void cmp_branch(LIR_Condition condition, LIR_Opr left, LIR_Opr right, BasicType type, BlockBegin* block, BlockBegin* unordered); ++ case lir_cmp_branch: ++ case lir_cmp_float_branch: { ++ LIR_OpCmpBranch* branch = op->as_OpCmpBranch(); ++ if (branch->block() == NULL) { ++ inc_counter(counter_stub_branch); ++ } else { ++ inc_counter(counter_cond_branch); ++ } ++ inc_counter(counter_cmp); ++ break; ++ } + - void cmp_mem_int(LIR_Condition condition, LIR_Opr base, int disp, int c, CodeEmitInfo* info); - void cmp_reg_mem(LIR_Condition condition, LIR_Opr reg, LIR_Address* addr, CodeEmitInfo* info); - -@@ -2153,6 +2257,9 @@ - append(new LIR_Op2(lir_cmove, condition, src1, src2, dst, type)); - } - -+ // machine dependent -+ void cmp_cmove(LIR_Condition condition, LIR_Opr left, LIR_Opr right, LIR_Opr src1, LIR_Opr src2, LIR_Opr dst, BasicType type); ++ case lir_cmp_cmove: { ++ inc_counter(counter_misc_inst); ++ inc_counter(counter_cmp); ++ break; ++ } + - void cas_long(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value, - LIR_Opr t1, LIR_Opr t2, LIR_Opr result = LIR_OprFact::illegalOpr); - void cas_obj(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value, -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/share/code/nmethod.cpp b/src/hotspot/share/code/nmethod.cpp ---- a/src/hotspot/share/code/nmethod.cpp 2024-01-10 05:19:49.000000000 +0800 -+++ b/src/hotspot/share/code/nmethod.cpp 2024-01-30 10:00:11.968096887 +0800 + case lir_neg: + case lir_add: + case lir_sub: +diff --git a/src/hotspot/share/code/nmethod.cpp b/src/hotspot/share/code/nmethod.cpp +index 6bc63116bd..41c0a0ea3d 100644 +--- a/src/hotspot/share/code/nmethod.cpp ++++ b/src/hotspot/share/code/nmethod.cpp @@ -22,6 +22,12 @@ * */ @@ -109164,7 +109562,7 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h #include "precompiled.hpp" #include "jvm.h" #include "code/codeCache.hpp" -@@ -2155,7 +2161,8 @@ +@@ -2159,7 +2165,8 @@ void nmethod::verify_scopes() { //verify_interrupt_point(iter.addr()); break; case relocInfo::runtime_call_type: @@ -109174,7 +109572,7 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h address destination = iter.reloc()->value(); // Right now there is no way to find out which entries support // an interrupt point. It would be nice if we had this -@@ -2392,7 +2399,8 @@ +@@ -2396,7 +2403,8 @@ const char* nmethod::reloc_string_for(u_char* begin, u_char* end) { return st.as_string(); } case relocInfo::runtime_call_type: @@ -109184,10 +109582,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h stringStream st; st.print("runtime_call"); CallRelocation* r = (CallRelocation*)iter.reloc(); -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/share/code/relocInfo.cpp b/src/hotspot/share/code/relocInfo.cpp ---- a/src/hotspot/share/code/relocInfo.cpp 2024-01-10 05:19:49.000000000 +0800 -+++ b/src/hotspot/share/code/relocInfo.cpp 2024-01-30 10:00:11.971430179 +0800 -@@ -433,6 +433,7 @@ +diff --git a/src/hotspot/share/code/relocInfo.cpp b/src/hotspot/share/code/relocInfo.cpp +index a20de8dde6..c6f49cf7d6 100644 +--- a/src/hotspot/share/code/relocInfo.cpp ++++ b/src/hotspot/share/code/relocInfo.cpp +@@ -433,6 +433,7 @@ void virtual_call_Relocation::unpack_data() { _cached_value = x0==0? NULL: address_from_scaled_offset(x0, point); } @@ -109195,7 +109594,7 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h void runtime_call_w_cp_Relocation::pack_data_to(CodeSection * dest) { short* p = pack_1_int_to((short *)dest->locs_end(), (jint)(_offset >> 2)); dest->set_locs_end((relocInfo*) p); -@@ -441,6 +442,7 @@ +@@ -441,6 +442,7 @@ void runtime_call_w_cp_Relocation::pack_data_to(CodeSection * dest) { void runtime_call_w_cp_Relocation::unpack_data() { _offset = unpack_1_int() << 2; } @@ -109203,7 +109602,7 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h void static_stub_Relocation::pack_data_to(CodeSection* dest) { short* p = (short*) dest->locs_end(); -@@ -910,7 +912,7 @@ +@@ -910,7 +912,7 @@ void RelocIterator::print_current() { break; } case relocInfo::runtime_call_type: @@ -109212,10 +109611,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h { CallRelocation* r = (CallRelocation*) reloc(); tty->print(" | [destination=" INTPTR_FORMAT "]", p2i(r->destination())); -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/share/code/relocInfo.hpp b/src/hotspot/share/code/relocInfo.hpp ---- a/src/hotspot/share/code/relocInfo.hpp 2024-01-10 05:19:49.000000000 +0800 -+++ b/src/hotspot/share/code/relocInfo.hpp 2024-01-30 10:00:11.971430179 +0800 -@@ -269,7 +269,11 @@ +diff --git a/src/hotspot/share/code/relocInfo.hpp b/src/hotspot/share/code/relocInfo.hpp +index 57931a1a6a..fb56fd3ab1 100644 +--- a/src/hotspot/share/code/relocInfo.hpp ++++ b/src/hotspot/share/code/relocInfo.hpp +@@ -269,7 +269,11 @@ class relocInfo { poll_return_type = 11, // polling instruction for safepoints at return metadata_type = 12, // metadata that used to be oops trampoline_stub_type = 13, // stub-entry for trampoline @@ -109227,7 +109627,7 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h data_prefix_tag = 15, // tag for a prefix (carries data arguments) type_mask = 15 // A mask which selects only the above values }; -@@ -304,13 +308,13 @@ +@@ -304,13 +308,13 @@ class relocInfo { visitor(static_call) \ visitor(static_stub) \ visitor(runtime_call) \ @@ -109243,7 +109643,7 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h public: -@@ -1174,6 +1178,15 @@ +@@ -1174,6 +1178,15 @@ class runtime_call_Relocation : public CallRelocation { }; @@ -109259,7 +109659,7 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h class runtime_call_w_cp_Relocation : public CallRelocation { relocInfo::relocType type() { return relocInfo::runtime_call_w_cp_type; } -@@ -1202,6 +1215,7 @@ +@@ -1202,6 +1215,7 @@ class runtime_call_w_cp_Relocation : public CallRelocation { void pack_data_to(CodeSection * dest); void unpack_data(); }; @@ -109267,9 +109667,10 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h // Trampoline Relocations. // A trampoline allows to encode a small branch in the code, even if there -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/share/code/vtableStubs.cpp b/src/hotspot/share/code/vtableStubs.cpp ---- a/src/hotspot/share/code/vtableStubs.cpp 2024-01-10 05:19:49.000000000 +0800 -+++ b/src/hotspot/share/code/vtableStubs.cpp 2024-01-30 10:00:11.971430179 +0800 +diff --git a/src/hotspot/share/code/vtableStubs.cpp b/src/hotspot/share/code/vtableStubs.cpp +index 3c986f40ff..23d07f0505 100644 +--- a/src/hotspot/share/code/vtableStubs.cpp ++++ b/src/hotspot/share/code/vtableStubs.cpp @@ -22,6 +22,12 @@ * */ @@ -109283,7 +109684,7 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h #include "precompiled.hpp" #include "code/vtableStubs.hpp" #include "compiler/compileBroker.hpp" -@@ -98,7 +104,11 @@ +@@ -98,7 +104,11 @@ int VtableStubs::_itab_stub_size = 0; #if defined(PRODUCT) // These values are good for the PRODUCT case (no tracing). @@ -109295,7 +109696,7 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h static const int first_itableStub_size = 256; #else // These values are good for the non-PRODUCT case (when tracing can be switched on). -@@ -109,6 +119,7 @@ +@@ -109,6 +119,7 @@ int VtableStubs::_itab_stub_size = 0; // vtable itable // aarch64: 460 324 // arm: ? ? @@ -109303,10 +109704,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h // ppc (linux, BE): 404 288 // ppc (linux, LE): 356 276 // ppc (AIX): 416 296 -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/share/gc/g1/c1/g1BarrierSetC1.cpp b/src/hotspot/share/gc/g1/c1/g1BarrierSetC1.cpp ---- a/src/hotspot/share/gc/g1/c1/g1BarrierSetC1.cpp 2024-01-10 05:19:49.000000000 +0800 -+++ b/src/hotspot/share/gc/g1/c1/g1BarrierSetC1.cpp 2024-01-30 10:00:11.981430060 +0800 -@@ -74,7 +74,6 @@ +diff --git a/src/hotspot/share/gc/g1/c1/g1BarrierSetC1.cpp b/src/hotspot/share/gc/g1/c1/g1BarrierSetC1.cpp +index 4289e5e5c4..9502463bd5 100644 +--- a/src/hotspot/share/gc/g1/c1/g1BarrierSetC1.cpp ++++ b/src/hotspot/share/gc/g1/c1/g1BarrierSetC1.cpp +@@ -74,7 +74,6 @@ void G1BarrierSetC1::pre_barrier(LIRAccess& access, LIR_Opr addr_opr, // Read the marking-in-progress flag. LIR_Opr flag_val = gen->new_register(T_INT); __ load(mark_active_flag_addr, flag_val); @@ -109314,7 +109716,7 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h LIR_PatchCode pre_val_patch_code = lir_patch_none; -@@ -103,7 +102,7 @@ +@@ -103,7 +102,7 @@ void G1BarrierSetC1::pre_barrier(LIRAccess& access, LIR_Opr addr_opr, slow = new G1PreBarrierStub(pre_val); } @@ -109323,7 +109725,7 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h __ branch_destination(slow->continuation()); } -@@ -168,10 +167,9 @@ +@@ -168,10 +167,9 @@ void G1BarrierSetC1::post_barrier(LIRAccess& access, LIR_OprDesc* addr, LIR_OprD } assert(new_val->is_register(), "must be a register at this point"); @@ -109336,9 +109738,10 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h __ branch_destination(slow->continuation()); } -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/share/gc/g1/g1FullGCMarker.inline.hpp b/src/hotspot/share/gc/g1/g1FullGCMarker.inline.hpp ---- a/src/hotspot/share/gc/g1/g1FullGCMarker.inline.hpp 2024-01-10 05:19:49.000000000 +0800 -+++ b/src/hotspot/share/gc/g1/g1FullGCMarker.inline.hpp 2024-01-30 10:00:11.991429941 +0800 +diff --git a/src/hotspot/share/gc/g1/g1FullGCMarker.inline.hpp b/src/hotspot/share/gc/g1/g1FullGCMarker.inline.hpp +index 98a2fe7f1c..b43a441066 100644 +--- a/src/hotspot/share/gc/g1/g1FullGCMarker.inline.hpp ++++ b/src/hotspot/share/gc/g1/g1FullGCMarker.inline.hpp @@ -22,6 +22,12 @@ * */ @@ -109352,7 +109755,7 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h #ifndef SHARE_VM_GC_G1_G1MARKSTACK_INLINE_HPP #define SHARE_VM_GC_G1_G1MARKSTACK_INLINE_HPP -@@ -71,6 +77,7 @@ +@@ -71,6 +77,7 @@ template inline void G1FullGCMarker::mark_and_push(T* p) { _oop_stack.push(obj); assert(_bitmap->is_marked(obj), "Must be marked now - map self"); } else { @@ -109360,10 +109763,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h assert(_bitmap->is_marked(obj) || G1ArchiveAllocator::is_closed_archive_object(obj), "Must be marked by other or closed archive object"); } -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/share/gc/parallel/psPromotionManager.inline.hpp b/src/hotspot/share/gc/parallel/psPromotionManager.inline.hpp ---- a/src/hotspot/share/gc/parallel/psPromotionManager.inline.hpp 2024-01-10 05:19:49.000000000 +0800 -+++ b/src/hotspot/share/gc/parallel/psPromotionManager.inline.hpp 2024-01-30 10:00:12.004763116 +0800 -@@ -51,8 +51,9 @@ +diff --git a/src/hotspot/share/gc/parallel/psPromotionManager.inline.hpp b/src/hotspot/share/gc/parallel/psPromotionManager.inline.hpp +index 1ef900783d..b30456429d 100644 +--- a/src/hotspot/share/gc/parallel/psPromotionManager.inline.hpp ++++ b/src/hotspot/share/gc/parallel/psPromotionManager.inline.hpp +@@ -51,8 +51,9 @@ template inline void PSPromotionManager::claim_or_forward_internal_depth(T* p) { if (p != NULL) { // XXX: error if p != NULL here oop o = RawAccess::oop_load(p); @@ -109375,7 +109779,7 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h // Card mark if (PSScavenge::is_obj_in_young(o)) { PSScavenge::card_table()->inline_write_ref_field_gc(p, o); -@@ -282,13 +283,17 @@ +@@ -282,13 +283,17 @@ inline void PSPromotionManager::copy_and_push_safe_barrier(T* p) { assert(should_scavenge(p, true), "revisiting object?"); oop o = RawAccess::oop_load(p); @@ -109397,10 +109801,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h log_develop_trace(gc, scavenge)("{%s %s " PTR_FORMAT " -> " PTR_FORMAT " (%d)}", "forwarding", new_obj->klass()->internal_name(), p2i((void *)o), p2i((void *)new_obj), new_obj->size()); -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/share/gc/parallel/psScavenge.inline.hpp b/src/hotspot/share/gc/parallel/psScavenge.inline.hpp ---- a/src/hotspot/share/gc/parallel/psScavenge.inline.hpp 2024-01-10 05:19:49.000000000 +0800 -+++ b/src/hotspot/share/gc/parallel/psScavenge.inline.hpp 2024-01-30 10:00:12.008096410 +0800 -@@ -104,8 +104,9 @@ +diff --git a/src/hotspot/share/gc/parallel/psScavenge.inline.hpp b/src/hotspot/share/gc/parallel/psScavenge.inline.hpp +index 0c58fd4b3f..415990ff5f 100644 +--- a/src/hotspot/share/gc/parallel/psScavenge.inline.hpp ++++ b/src/hotspot/share/gc/parallel/psScavenge.inline.hpp +@@ -104,8 +104,9 @@ class PSScavengeFromCLDClosure: public OopClosure { oop o = *p; oop new_obj; @@ -109412,10 +109817,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h } else { new_obj = _pm->copy_to_survivor_space(o); } -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/share/gc/shared/c1/barrierSetC1.cpp b/src/hotspot/share/gc/shared/c1/barrierSetC1.cpp ---- a/src/hotspot/share/gc/shared/c1/barrierSetC1.cpp 2024-01-10 05:19:49.000000000 +0800 -+++ b/src/hotspot/share/gc/shared/c1/barrierSetC1.cpp 2024-01-30 10:00:12.011429704 +0800 -@@ -192,8 +192,7 @@ +diff --git a/src/hotspot/share/gc/shared/c1/barrierSetC1.cpp b/src/hotspot/share/gc/shared/c1/barrierSetC1.cpp +index 5241322a91..0ddabb4dae 100644 +--- a/src/hotspot/share/gc/shared/c1/barrierSetC1.cpp ++++ b/src/hotspot/share/gc/shared/c1/barrierSetC1.cpp +@@ -192,8 +192,7 @@ void BarrierSetC1::load_at_resolved(LIRAccess& access, LIR_Opr result) { /* Normalize boolean value returned by unsafe operation, i.e., value != 0 ? value = true : value false. */ if (mask_boolean) { LabelObj* equalZeroLabel = new LabelObj(); @@ -109425,7 +109831,7 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h __ move(LIR_OprFact::intConst(1), result); __ branch_destination(equalZeroLabel->label()); } -@@ -320,14 +319,12 @@ +@@ -320,14 +319,12 @@ void BarrierSetC1::generate_referent_check(LIRAccess& access, LabelObj* cont) { referent_off = gen->new_register(T_LONG); __ move(LIR_OprFact::longConst(java_lang_ref_Reference::referent_offset), referent_off); } @@ -109442,7 +109848,7 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h } LIR_Opr src_klass = gen->new_register(T_METADATA); if (gen_type_check) { -@@ -337,8 +334,7 @@ +@@ -337,8 +334,7 @@ void BarrierSetC1::generate_referent_check(LIRAccess& access, LabelObj* cont) { LIR_Address* reference_type_addr = new LIR_Address(src_klass, in_bytes(InstanceKlass::reference_type_offset()), T_BYTE); LIR_Opr reference_type = gen->new_register(T_INT); __ move(reference_type_addr, reference_type); @@ -109452,10 +109858,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h } } } -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/share/gc/shared/c1/cardTableBarrierSetC1.cpp b/src/hotspot/share/gc/shared/c1/cardTableBarrierSetC1.cpp ---- a/src/hotspot/share/gc/shared/c1/cardTableBarrierSetC1.cpp 2024-01-10 05:19:49.000000000 +0800 -+++ b/src/hotspot/share/gc/shared/c1/cardTableBarrierSetC1.cpp 2024-01-30 10:00:12.011429704 +0800 -@@ -89,8 +89,7 @@ +diff --git a/src/hotspot/share/gc/shared/c1/cardTableBarrierSetC1.cpp b/src/hotspot/share/gc/shared/c1/cardTableBarrierSetC1.cpp +index 84815adea8..57e29f1295 100644 +--- a/src/hotspot/share/gc/shared/c1/cardTableBarrierSetC1.cpp ++++ b/src/hotspot/share/gc/shared/c1/cardTableBarrierSetC1.cpp +@@ -89,8 +89,7 @@ void CardTableBarrierSetC1::post_barrier(LIRAccess& access, LIR_OprDesc* addr, L __ move(card_addr, cur_value); LabelObj* L_already_dirty = new LabelObj(); @@ -109465,10 +109872,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h __ move(dirty, card_addr); __ branch_destination(L_already_dirty->label()); } else { -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/share/gc/shenandoah/c1/shenandoahBarrierSetC1.cpp b/src/hotspot/share/gc/shenandoah/c1/shenandoahBarrierSetC1.cpp ---- a/src/hotspot/share/gc/shenandoah/c1/shenandoahBarrierSetC1.cpp 2024-01-10 05:19:49.000000000 +0800 -+++ b/src/hotspot/share/gc/shenandoah/c1/shenandoahBarrierSetC1.cpp 2024-01-30 10:00:12.021429583 +0800 -@@ -73,7 +73,6 @@ +diff --git a/src/hotspot/share/gc/shenandoah/c1/shenandoahBarrierSetC1.cpp b/src/hotspot/share/gc/shenandoah/c1/shenandoahBarrierSetC1.cpp +index f51d186484..506f0301fe 100644 +--- a/src/hotspot/share/gc/shenandoah/c1/shenandoahBarrierSetC1.cpp ++++ b/src/hotspot/share/gc/shenandoah/c1/shenandoahBarrierSetC1.cpp +@@ -73,7 +73,6 @@ void ShenandoahBarrierSetC1::pre_barrier(LIRGenerator* gen, CodeEmitInfo* info, // Read the marking-in-progress flag. LIR_Opr flag_val = gen->new_register(T_INT); __ load(mark_active_flag_addr, flag_val); @@ -109476,7 +109884,7 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h LIR_PatchCode pre_val_patch_code = lir_patch_none; -@@ -101,7 +100,7 @@ +@@ -101,7 +100,7 @@ void ShenandoahBarrierSetC1::pre_barrier(LIRGenerator* gen, CodeEmitInfo* info, slow = new ShenandoahPreBarrierStub(pre_val); } @@ -109485,7 +109893,7 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h __ branch_destination(slow->continuation()); } -@@ -144,10 +143,9 @@ +@@ -144,10 +143,9 @@ LIR_Opr ShenandoahBarrierSetC1::load_reference_barrier_impl(LIRGenerator* gen, L __ logical_and(flag_val, mask_reg, masked_flag); flag_val = masked_flag; } @@ -109497,10 +109905,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h __ branch_destination(slow->continuation()); return result; -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/share/gc/z/c1/zBarrierSetC1.cpp b/src/hotspot/share/gc/z/c1/zBarrierSetC1.cpp ---- a/src/hotspot/share/gc/z/c1/zBarrierSetC1.cpp 2024-01-10 05:19:49.000000000 +0800 -+++ b/src/hotspot/share/gc/z/c1/zBarrierSetC1.cpp 2024-01-30 10:00:12.031429464 +0800 -@@ -105,15 +105,20 @@ +diff --git a/src/hotspot/share/gc/z/c1/zBarrierSetC1.cpp b/src/hotspot/share/gc/z/c1/zBarrierSetC1.cpp +index 9f8ce74243..3c1862d826 100644 +--- a/src/hotspot/share/gc/z/c1/zBarrierSetC1.cpp ++++ b/src/hotspot/share/gc/z/c1/zBarrierSetC1.cpp +@@ -105,15 +105,20 @@ public: virtual void visit(LIR_OpVisitState* state) { state->do_input(_opr); @@ -109522,7 +109931,7 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h } #ifndef PRODUCT -@@ -149,13 +154,21 @@ +@@ -149,13 +154,21 @@ address ZBarrierSetC1::load_barrier_on_oop_field_preloaded_runtime_stub(Decorato #endif void ZBarrierSetC1::load_barrier(LIRAccess& access, LIR_Opr result) const { @@ -109546,9 +109955,10 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h __ branch_destination(stub->continuation()); } -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/share/interpreter/interpreterRuntime.cpp b/src/hotspot/share/interpreter/interpreterRuntime.cpp ---- a/src/hotspot/share/interpreter/interpreterRuntime.cpp 2024-01-10 05:19:49.000000000 +0800 -+++ b/src/hotspot/share/interpreter/interpreterRuntime.cpp 2024-01-30 10:00:12.041429345 +0800 +diff --git a/src/hotspot/share/interpreter/interpreterRuntime.cpp b/src/hotspot/share/interpreter/interpreterRuntime.cpp +index 6483159136..f40e304f9a 100644 +--- a/src/hotspot/share/interpreter/interpreterRuntime.cpp ++++ b/src/hotspot/share/interpreter/interpreterRuntime.cpp @@ -22,6 +22,12 @@ * */ @@ -109562,7 +109972,7 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h #include "precompiled.hpp" #include "classfile/javaClasses.inline.hpp" #include "classfile/systemDictionary.hpp" -@@ -1497,7 +1503,7 @@ +@@ -1497,7 +1503,7 @@ IRT_ENTRY(void, InterpreterRuntime::prepare_native_call(JavaThread* thread, Meth // preparing the same method will be sure to see non-null entry & mirror. IRT_END @@ -109571,9 +109981,10 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h IRT_LEAF(void, InterpreterRuntime::popframe_move_outgoing_args(JavaThread* thread, void* src_address, void* dest_address)) if (src_address == dest_address) { return; -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/share/interpreter/interpreterRuntime.hpp b/src/hotspot/share/interpreter/interpreterRuntime.hpp ---- a/src/hotspot/share/interpreter/interpreterRuntime.hpp 2024-01-10 05:19:49.000000000 +0800 -+++ b/src/hotspot/share/interpreter/interpreterRuntime.hpp 2024-01-30 10:00:12.041429345 +0800 +diff --git a/src/hotspot/share/interpreter/interpreterRuntime.hpp b/src/hotspot/share/interpreter/interpreterRuntime.hpp +index 87e84c893f..3043fa634b 100644 +--- a/src/hotspot/share/interpreter/interpreterRuntime.hpp ++++ b/src/hotspot/share/interpreter/interpreterRuntime.hpp @@ -22,6 +22,12 @@ * */ @@ -109587,7 +109998,7 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h #ifndef SHARE_VM_INTERPRETER_INTERPRETERRUNTIME_HPP #define SHARE_VM_INTERPRETER_INTERPRETERRUNTIME_HPP -@@ -146,7 +152,7 @@ +@@ -146,7 +152,7 @@ class InterpreterRuntime: AllStatic { Method* method, intptr_t* from, intptr_t* to); @@ -109596,9 +110007,10 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h // Popframe support (only needed on x86, AMD64 and ARM) static void popframe_move_outgoing_args(JavaThread* thread, void* src_address, void* dest_address); #endif -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/share/interpreter/templateInterpreterGenerator.hpp b/src/hotspot/share/interpreter/templateInterpreterGenerator.hpp ---- a/src/hotspot/share/interpreter/templateInterpreterGenerator.hpp 2024-01-10 05:19:49.000000000 +0800 -+++ b/src/hotspot/share/interpreter/templateInterpreterGenerator.hpp 2024-01-30 10:00:12.044762639 +0800 +diff --git a/src/hotspot/share/interpreter/templateInterpreterGenerator.hpp b/src/hotspot/share/interpreter/templateInterpreterGenerator.hpp +index 965f6b0d10..07942993cd 100644 +--- a/src/hotspot/share/interpreter/templateInterpreterGenerator.hpp ++++ b/src/hotspot/share/interpreter/templateInterpreterGenerator.hpp @@ -22,6 +22,12 @@ * */ @@ -109612,7 +110024,7 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h #ifndef SHARE_VM_INTERPRETER_TEMPLATEINTERPRETERGENERATOR_HPP #define SHARE_VM_INTERPRETER_TEMPLATEINTERPRETERGENERATOR_HPP -@@ -114,9 +120,9 @@ +@@ -114,9 +120,9 @@ class TemplateInterpreterGenerator: public AbstractInterpreterGenerator { void restore_native_result(void); #endif // SPARC @@ -109624,9 +110036,10 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h #ifdef PPC void lock_method(Register Rflags, Register Rscratch1, Register Rscratch2, bool flags_preloaded=false); -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/share/jfr/utilities/jfrBigEndian.hpp b/src/hotspot/share/jfr/utilities/jfrBigEndian.hpp ---- a/src/hotspot/share/jfr/utilities/jfrBigEndian.hpp 2024-01-10 05:19:49.000000000 +0800 -+++ b/src/hotspot/share/jfr/utilities/jfrBigEndian.hpp 2024-01-30 10:00:12.054762520 +0800 +diff --git a/src/hotspot/share/jfr/utilities/jfrBigEndian.hpp b/src/hotspot/share/jfr/utilities/jfrBigEndian.hpp +index e01a242a57..0661f3b9d1 100644 +--- a/src/hotspot/share/jfr/utilities/jfrBigEndian.hpp ++++ b/src/hotspot/share/jfr/utilities/jfrBigEndian.hpp @@ -22,6 +22,12 @@ * */ @@ -109640,7 +110053,7 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h #ifndef SHARE_VM_JFR_UTILITIES_JFRBIGENDIAN_HPP #define SHARE_VM_JFR_UTILITIES_JFRBIGENDIAN_HPP -@@ -102,7 +108,7 @@ +@@ -102,7 +108,7 @@ inline T JfrBigEndian::read_unaligned(const address location) { inline bool JfrBigEndian::platform_supports_unaligned_reads(void) { #if defined(IA32) || defined(AMD64) || defined(PPC) || defined(S390) return true; @@ -109649,9 +110062,10 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h return false; #else #warning "Unconfigured platform" -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/share/jvmci/vmStructs_jvmci.cpp b/src/hotspot/share/jvmci/vmStructs_jvmci.cpp ---- a/src/hotspot/share/jvmci/vmStructs_jvmci.cpp 2024-01-10 05:19:49.000000000 +0800 -+++ b/src/hotspot/share/jvmci/vmStructs_jvmci.cpp 2024-01-30 10:00:12.061429106 +0800 +diff --git a/src/hotspot/share/jvmci/vmStructs_jvmci.cpp b/src/hotspot/share/jvmci/vmStructs_jvmci.cpp +index 8927063330..b5bb5c2887 100644 +--- a/src/hotspot/share/jvmci/vmStructs_jvmci.cpp ++++ b/src/hotspot/share/jvmci/vmStructs_jvmci.cpp @@ -22,6 +22,12 @@ * */ @@ -109665,11 +110079,10 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h #include "precompiled.hpp" #include "code/codeBlob.hpp" #include "compiler/abstractCompiler.hpp" -@@ -714,6 +720,35 @@ - +@@ -715,6 +721,35 @@ #endif -+ + +#ifdef LOONGARCH64 + +#define VM_STRUCTS_CPU(nonstatic_field, static_field, unchecked_nonstatic_field, volatile_nonstatic_field, nonproduct_nonstatic_field, c2_nonstatic_field, unchecked_c1_static_field, unchecked_c2_static_field) \ @@ -109698,13 +110111,15 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h + +#endif + - ++ #ifdef X86 -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/share/memory/metaspace.cpp b/src/hotspot/share/memory/metaspace.cpp ---- a/src/hotspot/share/memory/metaspace.cpp 2024-01-10 05:19:49.000000000 +0800 -+++ b/src/hotspot/share/memory/metaspace.cpp 2024-01-30 10:00:12.064762400 +0800 -@@ -1083,12 +1083,12 @@ + #define VM_STRUCTS_CPU(nonstatic_field, static_field, unchecked_nonstatic_field, volatile_nonstatic_field, nonproduct_nonstatic_field, c2_nonstatic_field, unchecked_c1_static_field, unchecked_c2_static_field) \ +diff --git a/src/hotspot/share/memory/metaspace.cpp b/src/hotspot/share/memory/metaspace.cpp +index c3a884fafe..103789d9b1 100644 +--- a/src/hotspot/share/memory/metaspace.cpp ++++ b/src/hotspot/share/memory/metaspace.cpp +@@ -1083,12 +1083,12 @@ void Metaspace::allocate_metaspace_compressed_klass_ptrs(char* requested_addr, a // Don't use large pages for the class space. bool large_pages = false; @@ -109719,7 +110134,7 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h ReservedSpace metaspace_rs; -@@ -1114,7 +1114,8 @@ +@@ -1114,7 +1114,8 @@ void Metaspace::allocate_metaspace_compressed_klass_ptrs(char* requested_addr, a // below 32g to get a zerobased CCS. For simplicity we reuse the search // strategy for AARCH64. @@ -109729,7 +110144,7 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h for (char *a = align_up(requested_addr, increment); a < (char*)(1024*G); a += increment) { -@@ -1145,7 +1146,7 @@ +@@ -1145,7 +1146,7 @@ void Metaspace::allocate_metaspace_compressed_klass_ptrs(char* requested_addr, a } } @@ -109738,9 +110153,10 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h if (!metaspace_rs.is_reserved()) { #if INCLUDE_CDS -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/share/oops/oop.inline.hpp b/src/hotspot/share/oops/oop.inline.hpp ---- a/src/hotspot/share/oops/oop.inline.hpp 2024-01-10 05:19:49.000000000 +0800 -+++ b/src/hotspot/share/oops/oop.inline.hpp 2024-01-30 10:00:12.074762281 +0800 +diff --git a/src/hotspot/share/oops/oop.inline.hpp b/src/hotspot/share/oops/oop.inline.hpp +index 6c631f5458..9865106720 100644 +--- a/src/hotspot/share/oops/oop.inline.hpp ++++ b/src/hotspot/share/oops/oop.inline.hpp @@ -22,6 +22,12 @@ * */ @@ -109754,7 +110170,7 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h #ifndef SHARE_VM_OOPS_OOP_INLINE_HPP #define SHARE_VM_OOPS_OOP_INLINE_HPP -@@ -389,7 +395,7 @@ +@@ -389,7 +395,7 @@ oop oopDesc::forward_to_atomic(oop p, atomic_memory_order order) { // forwarding pointer. oldMark = curMark; } @@ -109763,10 +110179,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h } // Note that the forwardee is not the same thing as the displaced_mark. -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/share/opto/compile.hpp b/src/hotspot/share/opto/compile.hpp ---- a/src/hotspot/share/opto/compile.hpp 2024-01-10 05:19:49.000000000 +0800 -+++ b/src/hotspot/share/opto/compile.hpp 2024-01-30 10:00:12.081428868 +0800 -@@ -1204,7 +1204,7 @@ +diff --git a/src/hotspot/share/opto/compile.hpp b/src/hotspot/share/opto/compile.hpp +index 569fbc6d69..c1f1b82ffa 100644 +--- a/src/hotspot/share/opto/compile.hpp ++++ b/src/hotspot/share/opto/compile.hpp +@@ -1204,7 +1204,7 @@ class Compile : public Phase { bool in_scratch_emit_size() const { return _in_scratch_emit_size; } enum ScratchBufferBlob { @@ -109775,9 +110192,10 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h MAX_inst_size = 2048, #else MAX_inst_size = 1024, -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/share/opto/output.cpp b/src/hotspot/share/opto/output.cpp ---- a/src/hotspot/share/opto/output.cpp 2024-01-10 05:19:49.000000000 +0800 -+++ b/src/hotspot/share/opto/output.cpp 2024-01-30 10:00:12.094762043 +0800 +diff --git a/src/hotspot/share/opto/output.cpp b/src/hotspot/share/opto/output.cpp +index b6540e06a3..52d1fc9fb9 100644 +--- a/src/hotspot/share/opto/output.cpp ++++ b/src/hotspot/share/opto/output.cpp @@ -22,6 +22,12 @@ * */ @@ -109791,7 +110209,7 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h #include "precompiled.hpp" #include "asm/assembler.inline.hpp" #include "asm/macroAssembler.inline.hpp" -@@ -731,6 +737,27 @@ +@@ -731,6 +737,27 @@ void Compile::Process_OopMap_Node(MachNode *mach, int current_offset) { // Add the safepoint in the DebugInfoRecorder if( !mach->is_MachCall() ) { mcall = NULL; @@ -109819,7 +110237,7 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h debug_info()->add_safepoint(safepoint_pc_offset, sfn->_oop_map); } else { mcall = mach->as_MachCall(); -@@ -1393,6 +1420,22 @@ +@@ -1393,6 +1420,22 @@ void Compile::fill_buffer(CodeBuffer* cb, uint* blk_starts) { DEBUG_ONLY(uint instr_offset = cb->insts_size()); n->emit(*cb, _regalloc); current_offset = cb->insts_size(); @@ -109842,9 +110260,10 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h // Above we only verified that there is enough space in the instruction section. // However, the instruction may emit stubs that cause code buffer expansion. -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/share/opto/type.cpp b/src/hotspot/share/opto/type.cpp ---- a/src/hotspot/share/opto/type.cpp 2024-01-10 05:19:49.000000000 +0800 -+++ b/src/hotspot/share/opto/type.cpp 2024-01-30 10:00:12.101428630 +0800 +diff --git a/src/hotspot/share/opto/type.cpp b/src/hotspot/share/opto/type.cpp +index 7d767c47c9..23ec34e5e2 100644 +--- a/src/hotspot/share/opto/type.cpp ++++ b/src/hotspot/share/opto/type.cpp @@ -22,6 +22,12 @@ * */ @@ -109858,7 +110277,7 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h #include "precompiled.hpp" #include "ci/ciMethodData.hpp" #include "ci/ciTypeFlow.hpp" -@@ -78,6 +84,12 @@ +@@ -78,6 +84,12 @@ const Type::TypeInfo Type::_type_info[Type::lastype] = { { Bad, T_ILLEGAL, "vectorx:", false, 0, relocInfo::none }, // VectorX { Bad, T_ILLEGAL, "vectory:", false, 0, relocInfo::none }, // VectorY { Bad, T_ILLEGAL, "vectorz:", false, 0, relocInfo::none }, // VectorZ @@ -109871,9 +110290,10 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h #else // all other { Bad, T_ILLEGAL, "vectors:", false, Op_VecS, relocInfo::none }, // VectorS { Bad, T_ILLEGAL, "vectord:", false, Op_VecD, relocInfo::none }, // VectorD -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/share/runtime/java.cpp b/src/hotspot/share/runtime/java.cpp ---- a/src/hotspot/share/runtime/java.cpp 2024-01-10 05:19:49.000000000 +0800 -+++ b/src/hotspot/share/runtime/java.cpp 2024-01-30 10:00:12.118095097 +0800 +diff --git a/src/hotspot/share/runtime/java.cpp b/src/hotspot/share/runtime/java.cpp +index 84123b29ec..77fbacf2d8 100644 +--- a/src/hotspot/share/runtime/java.cpp ++++ b/src/hotspot/share/runtime/java.cpp @@ -68,6 +68,7 @@ #include "runtime/thread.inline.hpp" #include "runtime/timer.hpp" @@ -109882,9 +110302,10 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h #include "services/memTracker.hpp" #include "utilities/dtrace.hpp" #include "utilities/globalDefinitions.hpp" -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/share/runtime/objectMonitor.cpp b/src/hotspot/share/runtime/objectMonitor.cpp ---- a/src/hotspot/share/runtime/objectMonitor.cpp 2024-01-10 05:19:49.000000000 +0800 -+++ b/src/hotspot/share/runtime/objectMonitor.cpp 2024-01-30 10:00:12.121428391 +0800 +diff --git a/src/hotspot/share/runtime/objectMonitor.cpp b/src/hotspot/share/runtime/objectMonitor.cpp +index ce23aafa8f..d3dfb74d5b 100644 +--- a/src/hotspot/share/runtime/objectMonitor.cpp ++++ b/src/hotspot/share/runtime/objectMonitor.cpp @@ -22,6 +22,12 @@ * */ @@ -109898,7 +110319,7 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h #include "precompiled.hpp" #include "classfile/vmSymbols.hpp" #include "jfr/jfrEvents.hpp" -@@ -308,6 +314,9 @@ +@@ -308,6 +314,9 @@ void ObjectMonitor::enter(TRAPS) { } assert(_owner != Self, "invariant"); @@ -109908,7 +110329,7 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h assert(_succ != Self, "invariant"); assert(Self->is_Java_thread(), "invariant"); JavaThread * jt = (JavaThread *) Self; -@@ -469,6 +478,7 @@ +@@ -469,6 +478,7 @@ void ObjectMonitor::EnterI(TRAPS) { } // The Spin failed -- Enqueue and park the thread ... @@ -109916,9 +110337,10 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h assert(_succ != Self, "invariant"); assert(_owner != Self, "invariant"); assert(_Responsible != Self, "invariant"); -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/share/runtime/os.cpp b/src/hotspot/share/runtime/os.cpp ---- a/src/hotspot/share/runtime/os.cpp 2024-01-10 05:19:49.000000000 +0800 -+++ b/src/hotspot/share/runtime/os.cpp 2024-01-30 10:00:12.121428391 +0800 +diff --git a/src/hotspot/share/runtime/os.cpp b/src/hotspot/share/runtime/os.cpp +index e0f4a2af1f..09cc4b1ba5 100644 +--- a/src/hotspot/share/runtime/os.cpp ++++ b/src/hotspot/share/runtime/os.cpp @@ -22,6 +22,12 @@ * */ @@ -109932,7 +110354,7 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h #include "precompiled.hpp" #include "jvm.h" #include "classfile/classLoader.hpp" -@@ -1242,7 +1248,8 @@ +@@ -1242,7 +1248,8 @@ bool os::is_first_C_frame(frame* fr) { if ((uintptr_t)fr->sender_sp() == (uintptr_t)-1 || is_pointer_bad(fr->sender_sp())) return true; uintptr_t old_fp = (uintptr_t)fr->link_or_null(); @@ -109942,9 +110364,10 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h is_pointer_bad(fr->link_or_null())) return true; // stack grows downwards; if old_fp is below current fp or if the stack -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/share/runtime/sharedRuntimeTrig.cpp b/src/hotspot/share/runtime/sharedRuntimeTrig.cpp ---- a/src/hotspot/share/runtime/sharedRuntimeTrig.cpp 2024-01-10 05:19:49.000000000 +0800 -+++ b/src/hotspot/share/runtime/sharedRuntimeTrig.cpp 2024-01-30 10:00:12.128094978 +0800 +diff --git a/src/hotspot/share/runtime/sharedRuntimeTrig.cpp b/src/hotspot/share/runtime/sharedRuntimeTrig.cpp +index e086f794cd..f480195775 100644 +--- a/src/hotspot/share/runtime/sharedRuntimeTrig.cpp ++++ b/src/hotspot/share/runtime/sharedRuntimeTrig.cpp @@ -22,6 +22,13 @@ * */ @@ -109959,7 +110382,7 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h #include "precompiled.hpp" #include "jni.h" #include "runtime/interfaceSupport.inline.hpp" -@@ -512,6 +519,14 @@ +@@ -512,6 +519,14 @@ static int __ieee754_rem_pio2(double x, double *y) { * sin(x) = x + (S1*x + (x *(r-y/2)+y)) */ @@ -109974,10 +110397,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h static const double S1 = -1.66666666666666324348e-01, /* 0xBFC55555, 0x55555549 */ S2 = 8.33333333332248946124e-03, /* 0x3F811111, 0x1110F8A6 */ -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/share/utilities/globalDefinitions.hpp b/src/hotspot/share/utilities/globalDefinitions.hpp ---- a/src/hotspot/share/utilities/globalDefinitions.hpp 2024-01-10 05:19:49.000000000 +0800 -+++ b/src/hotspot/share/utilities/globalDefinitions.hpp 2024-01-30 10:00:12.141428153 +0800 -@@ -1161,6 +1161,15 @@ +diff --git a/src/hotspot/share/utilities/globalDefinitions.hpp b/src/hotspot/share/utilities/globalDefinitions.hpp +index c758fc5743..a8c4638f6a 100644 +--- a/src/hotspot/share/utilities/globalDefinitions.hpp ++++ b/src/hotspot/share/utilities/globalDefinitions.hpp +@@ -1161,6 +1161,15 @@ inline int exact_log2_long(jlong x) { return log2_long(x); } @@ -109993,9 +110417,10 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h inline bool is_odd (intx x) { return x & 1; } inline bool is_even(intx x) { return !is_odd(x); } -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/share/utilities/macros.hpp b/src/hotspot/share/utilities/macros.hpp ---- a/src/hotspot/share/utilities/macros.hpp 2024-01-10 05:19:49.000000000 +0800 -+++ b/src/hotspot/share/utilities/macros.hpp 2024-01-30 10:00:12.144761447 +0800 +diff --git a/src/hotspot/share/utilities/macros.hpp b/src/hotspot/share/utilities/macros.hpp +index 6605ab367c..5a2be6ef15 100644 +--- a/src/hotspot/share/utilities/macros.hpp ++++ b/src/hotspot/share/utilities/macros.hpp @@ -22,6 +22,12 @@ * */ @@ -110083,45 +110508,10 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/h // basename.hpp / basename.inline.hpp #define COMPILER_HEADER(basename) XSTR(COMPILER_HEADER_STEM(basename).hpp) #define COMPILER_HEADER_INLINE(basename) XSTR(COMPILER_HEADER_STEM(basename).inline.hpp) -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/jdk.hotspot.agent/linux/native/libsaproc/libproc.h b/src/jdk.hotspot.agent/linux/native/libsaproc/libproc.h ---- a/src/jdk.hotspot.agent/linux/native/libsaproc/libproc.h 2024-01-10 05:19:49.000000000 +0800 -+++ b/src/jdk.hotspot.agent/linux/native/libsaproc/libproc.h 2024-01-30 10:00:13.224748568 +0800 -@@ -22,6 +22,13 @@ - * - */ - -+/* -+ * This file has been modified by Loongson Technology in 2022. These -+ * modifications are Copyright (c) 2022, Loongson Technology, and are made -+ * available on the same license terms set forth above. -+ * -+ */ -+ - #ifndef _LIBPROC_H_ - #define _LIBPROC_H_ - -@@ -37,13 +44,17 @@ - #include - #define user_regs_struct pt_regs - #endif --#if defined(aarch64) || defined(arm64) -+#if defined(aarch64) || defined(arm64) || defined(loongarch64) - #include - #define user_regs_struct user_pt_regs - #elif defined(arm) - #include - #define user_regs_struct pt_regs - #endif -+#if defined(mips) || defined(mipsel) || defined(mips64) || defined(mips64el) -+#include -+#define user_regs_struct pt_regs -+#endif - - // This C bool type must be int for compatibility with Linux calls and - // it would be a mistake to equivalence it to C++ bool on many platforms -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/jdk.hotspot.agent/linux/native/libsaproc/LinuxDebuggerLocal.c b/src/jdk.hotspot.agent/linux/native/libsaproc/LinuxDebuggerLocal.c ---- a/src/jdk.hotspot.agent/linux/native/libsaproc/LinuxDebuggerLocal.c 2024-01-10 05:19:49.000000000 +0800 -+++ b/src/jdk.hotspot.agent/linux/native/libsaproc/LinuxDebuggerLocal.c 2024-01-30 10:00:13.224748568 +0800 +diff --git a/src/jdk.hotspot.agent/linux/native/libsaproc/LinuxDebuggerLocal.c b/src/jdk.hotspot.agent/linux/native/libsaproc/LinuxDebuggerLocal.c +index 0d834302c5..6afafea095 100644 +--- a/src/jdk.hotspot.agent/linux/native/libsaproc/LinuxDebuggerLocal.c ++++ b/src/jdk.hotspot.agent/linux/native/libsaproc/LinuxDebuggerLocal.c @@ -22,6 +22,13 @@ * */ @@ -110155,7 +110545,7 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/j static jfieldID p_ps_prochandle_ID = 0; static jfieldID threadList_ID = 0; static jfieldID loadObjectList_ID = 0; -@@ -397,7 +412,7 @@ +@@ -397,7 +412,7 @@ JNIEXPORT jbyteArray JNICALL Java_sun_jvm_hotspot_debugger_linux_LinuxDebuggerLo return (err == PS_OK)? array : 0; } @@ -110164,7 +110554,7 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/j JNIEXPORT jlongArray JNICALL Java_sun_jvm_hotspot_debugger_linux_LinuxDebuggerLocal_getThreadIntegerRegisterSet0 (JNIEnv *env, jobject this_obj, jint lwp_id) { -@@ -425,9 +440,15 @@ +@@ -425,8 +440,14 @@ JNIEXPORT jlongArray JNICALL Java_sun_jvm_hotspot_debugger_linux_LinuxDebuggerLo #if defined(sparc) || defined(sparcv9) #define NPRGREG sun_jvm_hotspot_debugger_sparc_SPARCThreadContext_NPRGREG #endif @@ -110173,14 +110563,13 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/j +#endif #if defined(ppc64) || defined(ppc64le) #define NPRGREG sun_jvm_hotspot_debugger_ppc64_PPC64ThreadContext_NPRGREG - #endif ++#endif +#if defined(mips64) || defined(mips64el) +#define NPRGREG sun_jvm_hotspot_debugger_mips64_MIPS64ThreadContext_NPRGREG -+#endif + #endif - array = (*env)->NewLongArray(env, NPRGREG); -@@ -534,6 +555,18 @@ +@@ -534,6 +555,18 @@ JNIEXPORT jlongArray JNICALL Java_sun_jvm_hotspot_debugger_linux_LinuxDebuggerLo } #endif /* aarch64 */ @@ -110199,7 +110588,7 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/j #if defined(ppc64) || defined(ppc64le) #define REG_INDEX(reg) sun_jvm_hotspot_debugger_ppc64_PPC64ThreadContext_##reg -@@ -574,6 +607,45 @@ +@@ -574,6 +607,45 @@ JNIEXPORT jlongArray JNICALL Java_sun_jvm_hotspot_debugger_linux_LinuxDebuggerLo #endif @@ -110245,9 +110634,47 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/j (*env)->ReleaseLongArrayElements(env, array, regs, JNI_COMMIT); return array; } -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/jdk.hotspot.agent/linux/native/libsaproc/ps_proc.c b/src/jdk.hotspot.agent/linux/native/libsaproc/ps_proc.c ---- a/src/jdk.hotspot.agent/linux/native/libsaproc/ps_proc.c 2024-01-10 05:19:49.000000000 +0800 -+++ b/src/jdk.hotspot.agent/linux/native/libsaproc/ps_proc.c 2024-01-30 10:00:13.224748568 +0800 +diff --git a/src/jdk.hotspot.agent/linux/native/libsaproc/libproc.h b/src/jdk.hotspot.agent/linux/native/libsaproc/libproc.h +index 8318e8e021..07064e76ee 100644 +--- a/src/jdk.hotspot.agent/linux/native/libsaproc/libproc.h ++++ b/src/jdk.hotspot.agent/linux/native/libsaproc/libproc.h +@@ -22,6 +22,13 @@ + * + */ + ++/* ++ * This file has been modified by Loongson Technology in 2022. These ++ * modifications are Copyright (c) 2022, Loongson Technology, and are made ++ * available on the same license terms set forth above. ++ * ++ */ ++ + #ifndef _LIBPROC_H_ + #define _LIBPROC_H_ + +@@ -37,13 +44,17 @@ + #include + #define user_regs_struct pt_regs + #endif +-#if defined(aarch64) || defined(arm64) ++#if defined(aarch64) || defined(arm64) || defined(loongarch64) + #include + #define user_regs_struct user_pt_regs + #elif defined(arm) + #include + #define user_regs_struct pt_regs + #endif ++#if defined(mips) || defined(mipsel) || defined(mips64) || defined(mips64el) ++#include ++#define user_regs_struct pt_regs ++#endif + + // This C bool type must be int for compatibility with Linux calls and + // it would be a mistake to equivalence it to C++ bool on many platforms +diff --git a/src/jdk.hotspot.agent/linux/native/libsaproc/ps_proc.c b/src/jdk.hotspot.agent/linux/native/libsaproc/ps_proc.c +index de5254d859..eefe55959c 100644 +--- a/src/jdk.hotspot.agent/linux/native/libsaproc/ps_proc.c ++++ b/src/jdk.hotspot.agent/linux/native/libsaproc/ps_proc.c @@ -22,6 +22,12 @@ * */ @@ -110261,7 +110688,7 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/j #include #include #include -@@ -142,7 +148,7 @@ +@@ -142,7 +148,7 @@ static bool process_get_lwp_regs(struct ps_prochandle* ph, pid_t pid, struct use #define PTRACE_GETREGS_REQ PT_GETREGS #endif @@ -110270,9 +110697,141 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/j if (ptrace_getregs(PTRACE_GETREGS_REQ, pid, user, NULL) < 0) { print_debug("ptrace(PTRACE_GETREGS, ...) failed for lwp %d\n", pid); return false; -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/linux/LinuxCDebugger.java b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/linux/LinuxCDebugger.java ---- a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/linux/LinuxCDebugger.java 2024-01-10 05:19:49.000000000 +0800 -+++ b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/linux/LinuxCDebugger.java 2024-01-30 10:00:13.238081742 +0800 +diff --git a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/HotSpotAgent.java b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/HotSpotAgent.java +index 0f5f0119c7..1b2f11a065 100644 +--- a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/HotSpotAgent.java ++++ b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/HotSpotAgent.java +@@ -23,6 +23,12 @@ + * + */ + ++/* ++ * This file has been modified by Loongson Technology in 2021. These ++ * modifications are Copyright (c) 2018, 2021, Loongson Technology, and are made ++ * available on the same license terms set forth above. ++ * ++ */ + package sun.jvm.hotspot; + + import java.rmi.RemoteException; +@@ -39,6 +45,8 @@ import sun.jvm.hotspot.debugger.MachineDescriptionAArch64; + import sun.jvm.hotspot.debugger.MachineDescriptionIntelX86; + import sun.jvm.hotspot.debugger.MachineDescriptionSPARC32Bit; + import sun.jvm.hotspot.debugger.MachineDescriptionSPARC64Bit; ++import sun.jvm.hotspot.debugger.MachineDescriptionMIPS64; ++import sun.jvm.hotspot.debugger.MachineDescriptionLOONGARCH64; + import sun.jvm.hotspot.debugger.NoSuchSymbolException; + import sun.jvm.hotspot.debugger.bsd.BsdDebuggerLocal; + import sun.jvm.hotspot.debugger.linux.LinuxDebuggerLocal; +@@ -598,6 +606,10 @@ public class HotSpotAgent { + } else { + machDesc = new MachineDescriptionSPARC32Bit(); + } ++ } else if (cpu.equals("mips64")) { ++ machDesc = new MachineDescriptionMIPS64(); ++ } else if (cpu.equals("loongarch64")) { ++ machDesc = new MachineDescriptionLOONGARCH64(); + } else { + try { + machDesc = (MachineDescription) +diff --git a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/MachineDescriptionLOONGARCH64.java b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/MachineDescriptionLOONGARCH64.java +new file mode 100644 +index 0000000000..99cea8c7f1 +--- /dev/null ++++ b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/MachineDescriptionLOONGARCH64.java +@@ -0,0 +1,41 @@ ++/* ++ * Copyright (c) 2000, 2008, Oracle and/or its affiliates. All rights reserved. ++ * Copyright (c) 2018, 2021, Loongson Technology. All rights reserved. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ * ++ */ ++ ++package sun.jvm.hotspot.debugger; ++ ++public class MachineDescriptionLOONGARCH64 extends MachineDescriptionTwosComplement implements MachineDescription { ++ public long getAddressSize() { ++ return 8; ++ } ++ ++ ++ public boolean isBigEndian() { ++ return false; ++ } ++ ++ public boolean isLP64() { ++ return true; ++ } ++} +diff --git a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/MachineDescriptionMIPS64.java b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/MachineDescriptionMIPS64.java +new file mode 100644 +index 0000000000..1b49efd201 +--- /dev/null ++++ b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/MachineDescriptionMIPS64.java +@@ -0,0 +1,41 @@ ++/* ++ * Copyright (c) 2000, 2008, Oracle and/or its affiliates. All rights reserved. ++ * Copyright (c) 2018, Loongson Technology. All rights reserved. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ * ++ */ ++ ++package sun.jvm.hotspot.debugger; ++ ++public class MachineDescriptionMIPS64 extends MachineDescriptionTwosComplement implements MachineDescription { ++ public long getAddressSize() { ++ return 8; ++ } ++ ++ ++ public boolean isBigEndian() { ++ return "big".equals(System.getProperty("sun.cpu.endian")); ++ } ++ ++ public boolean isLP64() { ++ return true; ++ } ++} +diff --git a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/linux/LinuxCDebugger.java b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/linux/LinuxCDebugger.java +index 5e5a6bb714..7d7f6424e6 100644 +--- a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/linux/LinuxCDebugger.java ++++ b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/linux/LinuxCDebugger.java @@ -23,6 +23,12 @@ * */ @@ -110286,7 +110845,7 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/j package sun.jvm.hotspot.debugger.linux; import java.io.*; -@@ -34,12 +40,16 @@ +@@ -34,12 +40,16 @@ import sun.jvm.hotspot.debugger.x86.*; import sun.jvm.hotspot.debugger.amd64.*; import sun.jvm.hotspot.debugger.aarch64.*; import sun.jvm.hotspot.debugger.sparc.*; @@ -110303,7 +110862,7 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/j import sun.jvm.hotspot.utilities.*; class LinuxCDebugger implements CDebugger { -@@ -102,7 +112,21 @@ +@@ -102,7 +112,21 @@ class LinuxCDebugger implements CDebugger { Address pc = context.getRegisterAsAddress(SPARCThreadContext.R_O7); if (pc == null) return null; return new LinuxSPARCCFrame(dbg, sp, pc, LinuxDebuggerLocal.getAddressSize()); @@ -110326,9 +110885,10 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/j PPC64ThreadContext context = (PPC64ThreadContext) thread.getContext(); Address sp = context.getRegisterAsAddress(PPC64ThreadContext.SP); if (sp == null) return null; -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/linux/LinuxThreadContextFactory.java b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/linux/LinuxThreadContextFactory.java ---- a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/linux/LinuxThreadContextFactory.java 2024-01-10 05:19:49.000000000 +0800 -+++ b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/linux/LinuxThreadContextFactory.java 2024-01-30 10:00:13.241415036 +0800 +diff --git a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/linux/LinuxThreadContextFactory.java b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/linux/LinuxThreadContextFactory.java +index 4b786eecc9..4ead33827c 100644 +--- a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/linux/LinuxThreadContextFactory.java ++++ b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/linux/LinuxThreadContextFactory.java @@ -22,6 +22,12 @@ * */ @@ -110342,7 +110902,7 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/j package sun.jvm.hotspot.debugger.linux; import java.lang.reflect.*; -@@ -30,6 +36,8 @@ +@@ -30,6 +36,8 @@ import sun.jvm.hotspot.debugger.linux.amd64.*; import sun.jvm.hotspot.debugger.linux.x86.*; import sun.jvm.hotspot.debugger.linux.ppc64.*; import sun.jvm.hotspot.debugger.linux.sparc.*; @@ -110351,7 +110911,7 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/j class LinuxThreadContextFactory { static ThreadContext createThreadContext(LinuxDebugger dbg) { -@@ -40,7 +48,11 @@ +@@ -40,7 +48,11 @@ class LinuxThreadContextFactory { return new LinuxAMD64ThreadContext(dbg); } else if (cpu.equals("sparc")) { return new LinuxSPARCThreadContext(dbg); @@ -110364,9 +110924,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/j return new LinuxPPC64ThreadContext(dbg); } else { try { -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/linux/loongarch64/LinuxLOONGARCH64CFrame.java b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/linux/loongarch64/LinuxLOONGARCH64CFrame.java ---- a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/linux/loongarch64/LinuxLOONGARCH64CFrame.java 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/linux/loongarch64/LinuxLOONGARCH64CFrame.java 2024-01-30 10:00:13.241415036 +0800 +diff --git a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/linux/loongarch64/LinuxLOONGARCH64CFrame.java b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/linux/loongarch64/LinuxLOONGARCH64CFrame.java +new file mode 100644 +index 0000000000..0e6caee5a4 +--- /dev/null ++++ b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/linux/loongarch64/LinuxLOONGARCH64CFrame.java @@ -0,0 +1,92 @@ +/* + * Copyright (c) 2003, 2012, Oracle and/or its affiliates. All rights reserved. @@ -110460,9 +111022,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/j + private Address fp; + private LinuxDebugger dbg; +} -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/linux/loongarch64/LinuxLOONGARCH64ThreadContext.java b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/linux/loongarch64/LinuxLOONGARCH64ThreadContext.java ---- a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/linux/loongarch64/LinuxLOONGARCH64ThreadContext.java 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/linux/loongarch64/LinuxLOONGARCH64ThreadContext.java 2024-01-30 10:00:13.241415036 +0800 +diff --git a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/linux/loongarch64/LinuxLOONGARCH64ThreadContext.java b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/linux/loongarch64/LinuxLOONGARCH64ThreadContext.java +new file mode 100644 +index 0000000000..604642598e +--- /dev/null ++++ b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/linux/loongarch64/LinuxLOONGARCH64ThreadContext.java @@ -0,0 +1,47 @@ +/* + * Copyright (c) 2003, Oracle and/or its affiliates. All rights reserved. @@ -110511,9 +111075,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/j + return debugger.newAddress(getRegister(index)); + } +} -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/linux/mips64/LinuxMIPS64CFrame.java b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/linux/mips64/LinuxMIPS64CFrame.java ---- a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/linux/mips64/LinuxMIPS64CFrame.java 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/linux/mips64/LinuxMIPS64CFrame.java 2024-01-30 10:00:13.241415036 +0800 +diff --git a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/linux/mips64/LinuxMIPS64CFrame.java b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/linux/mips64/LinuxMIPS64CFrame.java +new file mode 100644 +index 0000000000..2e3eb564da +--- /dev/null ++++ b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/linux/mips64/LinuxMIPS64CFrame.java @@ -0,0 +1,80 @@ +/* + * Copyright (c) 2003, 2012, Oracle and/or its affiliates. All rights reserved. @@ -110595,9 +111161,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/j + private Address ebp; + private LinuxDebugger dbg; +} -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/linux/mips64/LinuxMIPS64ThreadContext.java b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/linux/mips64/LinuxMIPS64ThreadContext.java ---- a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/linux/mips64/LinuxMIPS64ThreadContext.java 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/linux/mips64/LinuxMIPS64ThreadContext.java 2024-01-30 10:00:13.241415036 +0800 +diff --git a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/linux/mips64/LinuxMIPS64ThreadContext.java b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/linux/mips64/LinuxMIPS64ThreadContext.java +new file mode 100644 +index 0000000000..98e0f3f0bc +--- /dev/null ++++ b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/linux/mips64/LinuxMIPS64ThreadContext.java @@ -0,0 +1,47 @@ +/* + * Copyright (c) 2003, Oracle and/or its affiliates. All rights reserved. @@ -110646,9 +111214,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/j + return debugger.newAddress(getRegister(index)); + } +} -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/loongarch64/LOONGARCH64ThreadContext.java b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/loongarch64/LOONGARCH64ThreadContext.java ---- a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/loongarch64/LOONGARCH64ThreadContext.java 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/loongarch64/LOONGARCH64ThreadContext.java 2024-01-30 10:00:13.241415036 +0800 +diff --git a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/loongarch64/LOONGARCH64ThreadContext.java b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/loongarch64/LOONGARCH64ThreadContext.java +new file mode 100644 +index 0000000000..1de3cb1a47 +--- /dev/null ++++ b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/loongarch64/LOONGARCH64ThreadContext.java @@ -0,0 +1,128 @@ +/* + * Copyright (c) 2000, 2012, Oracle and/or its affiliates. All rights reserved. @@ -110778,99 +111348,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/j + tie the implementation to, for example, the debugging system */ + public abstract Address getRegisterAsAddress(int index); +} -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/MachineDescriptionLOONGARCH64.java b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/MachineDescriptionLOONGARCH64.java ---- a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/MachineDescriptionLOONGARCH64.java 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/MachineDescriptionLOONGARCH64.java 2024-01-30 10:00:13.234748449 +0800 -@@ -0,0 +1,41 @@ -+/* -+ * Copyright (c) 2000, 2008, Oracle and/or its affiliates. All rights reserved. -+ * Copyright (c) 2018, 2021, Loongson Technology. All rights reserved. -+ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. -+ * -+ * This code is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 only, as -+ * published by the Free Software Foundation. -+ * -+ * This code is distributed in the hope that it will be useful, but WITHOUT -+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -+ * version 2 for more details (a copy is included in the LICENSE file that -+ * accompanied this code). -+ * -+ * You should have received a copy of the GNU General Public License version -+ * 2 along with this work; if not, write to the Free Software Foundation, -+ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. -+ * -+ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA -+ * or visit www.oracle.com if you need additional information or have any -+ * questions. -+ * -+ */ -+ -+package sun.jvm.hotspot.debugger; -+ -+public class MachineDescriptionLOONGARCH64 extends MachineDescriptionTwosComplement implements MachineDescription { -+ public long getAddressSize() { -+ return 8; -+ } -+ -+ -+ public boolean isBigEndian() { -+ return false; -+ } -+ -+ public boolean isLP64() { -+ return true; -+ } -+} -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/MachineDescriptionMIPS64.java b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/MachineDescriptionMIPS64.java ---- a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/MachineDescriptionMIPS64.java 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/MachineDescriptionMIPS64.java 2024-01-30 10:00:13.234748449 +0800 -@@ -0,0 +1,41 @@ -+/* -+ * Copyright (c) 2000, 2008, Oracle and/or its affiliates. All rights reserved. -+ * Copyright (c) 2018, Loongson Technology. All rights reserved. -+ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. -+ * -+ * This code is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 only, as -+ * published by the Free Software Foundation. -+ * -+ * This code is distributed in the hope that it will be useful, but WITHOUT -+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -+ * version 2 for more details (a copy is included in the LICENSE file that -+ * accompanied this code). -+ * -+ * You should have received a copy of the GNU General Public License version -+ * 2 along with this work; if not, write to the Free Software Foundation, -+ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. -+ * -+ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA -+ * or visit www.oracle.com if you need additional information or have any -+ * questions. -+ * -+ */ -+ -+package sun.jvm.hotspot.debugger; -+ -+public class MachineDescriptionMIPS64 extends MachineDescriptionTwosComplement implements MachineDescription { -+ public long getAddressSize() { -+ return 8; -+ } -+ -+ -+ public boolean isBigEndian() { -+ return "big".equals(System.getProperty("sun.cpu.endian")); -+ } -+ -+ public boolean isLP64() { -+ return true; -+ } -+} -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/mips64/MIPS64ThreadContext.java b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/mips64/MIPS64ThreadContext.java ---- a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/mips64/MIPS64ThreadContext.java 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/mips64/MIPS64ThreadContext.java 2024-01-30 10:00:13.241415036 +0800 +diff --git a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/mips64/MIPS64ThreadContext.java b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/mips64/MIPS64ThreadContext.java +new file mode 100644 +index 0000000000..d3479a65ea +--- /dev/null ++++ b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/mips64/MIPS64ThreadContext.java @@ -0,0 +1,128 @@ +/* + * Copyright (c) 2000, 2012, Oracle and/or its affiliates. All rights reserved. @@ -111000,9 +111482,10 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/j + tie the implementation to, for example, the debugging system */ + public abstract Address getRegisterAsAddress(int index); +} -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/posix/elf/ELFHeader.java b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/posix/elf/ELFHeader.java ---- a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/posix/elf/ELFHeader.java 2024-01-10 05:19:49.000000000 +0800 -+++ b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/posix/elf/ELFHeader.java 2024-01-30 10:00:13.241415036 +0800 +diff --git a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/posix/elf/ELFHeader.java b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/posix/elf/ELFHeader.java +index 7113a3a497..de47531db7 100644 +--- a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/posix/elf/ELFHeader.java ++++ b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/posix/elf/ELFHeader.java @@ -22,6 +22,12 @@ * */ @@ -111016,7 +111499,7 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/j package sun.jvm.hotspot.debugger.posix.elf; import java.io.FileInputStream; -@@ -63,6 +69,8 @@ +@@ -63,6 +69,8 @@ public interface ELFHeader { public static final int ARCH_i860 = 7; /** MIPS architecture type. */ public static final int ARCH_MIPS = 8; @@ -111025,9 +111508,138 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/j /** Returns a file type which is defined by the file type constants. */ public short getFileType(); -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/proc/loongarch64/ProcLOONGARCH64ThreadContext.java b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/proc/loongarch64/ProcLOONGARCH64ThreadContext.java ---- a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/proc/loongarch64/ProcLOONGARCH64ThreadContext.java 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/proc/loongarch64/ProcLOONGARCH64ThreadContext.java 2024-01-30 10:00:13.241415036 +0800 +diff --git a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/proc/ProcDebuggerLocal.java b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/proc/ProcDebuggerLocal.java +index 74e957d94b..46ece3611f 100644 +--- a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/proc/ProcDebuggerLocal.java ++++ b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/proc/ProcDebuggerLocal.java +@@ -32,11 +32,13 @@ import sun.jvm.hotspot.debugger.*; + import sun.jvm.hotspot.debugger.cdbg.*; + import sun.jvm.hotspot.debugger.proc.amd64.*; + import sun.jvm.hotspot.debugger.proc.aarch64.*; ++import sun.jvm.hotspot.debugger.proc.mips64.*; + import sun.jvm.hotspot.debugger.proc.sparc.*; + import sun.jvm.hotspot.debugger.proc.ppc64.*; + import sun.jvm.hotspot.debugger.proc.x86.*; + import sun.jvm.hotspot.debugger.ppc64.*; + import sun.jvm.hotspot.debugger.amd64.*; ++import sun.jvm.hotspot.debugger.mips64.*; + import sun.jvm.hotspot.debugger.aarch64.*; + import sun.jvm.hotspot.debugger.sparc.*; + import sun.jvm.hotspot.debugger.x86.*; +@@ -90,6 +92,10 @@ public class ProcDebuggerLocal extends DebuggerBase implements ProcDebugger { + threadFactory = new ProcAMD64ThreadFactory(this); + pcRegIndex = AMD64ThreadContext.RIP; + fpRegIndex = AMD64ThreadContext.RBP; ++ } else if (cpu.equals("mips64") || cpu.equals("mips64el")) { ++ threadFactory = new ProcMIPS64ThreadFactory(this); ++ pcRegIndex = MIPS64ThreadContext.PC; ++ fpRegIndex = MIPS64ThreadContext.FP; + } else if (cpu.equals("aarch64")) { + threadFactory = new ProcAARCH64ThreadFactory(this); + pcRegIndex = AARCH64ThreadContext.PC; +diff --git a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/proc/loongarch64/ProcLOONGARCH64Thread.java b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/proc/loongarch64/ProcLOONGARCH64Thread.java +new file mode 100644 +index 0000000000..1f60fa6cfb +--- /dev/null ++++ b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/proc/loongarch64/ProcLOONGARCH64Thread.java +@@ -0,0 +1,92 @@ ++/* ++ * Copyright (c) 2002, 2003, Oracle and/or its affiliates. All rights reserved. ++ * Copyright (c) 2015, 2021, Loongson Technology. All rights reserved. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ * ++ */ ++ ++package sun.jvm.hotspot.debugger.proc.loongarch64; ++ ++import sun.jvm.hotspot.debugger.*; ++import sun.jvm.hotspot.debugger.loongarch64.*; ++import sun.jvm.hotspot.debugger.proc.*; ++import sun.jvm.hotspot.utilities.*; ++ ++public class ProcLOONGARCH64Thread implements ThreadProxy { ++ private ProcDebugger debugger; ++ private int id; ++ ++ public ProcLOONGARCH64Thread(ProcDebugger debugger, Address addr) { ++ this.debugger = debugger; ++ ++ // FIXME: the size here should be configurable. However, making it ++ // so would produce a dependency on the "types" package from the ++ // debugger package, which is not desired. ++ this.id = (int) addr.getCIntegerAt(0, 4, true); ++ } ++ ++ public ProcLOONGARCH64Thread(ProcDebugger debugger, long id) { ++ this.debugger = debugger; ++ this.id = (int) id; ++ } ++ ++ public ThreadContext getContext() throws IllegalThreadStateException { ++ ProcLOONGARCH64ThreadContext context = new ProcLOONGARCH64ThreadContext(debugger); ++ long[] regs = debugger.getThreadIntegerRegisterSet(id); ++ /* ++ _NGREG in reg.h is defined to be 19. Because we have included ++ debug registers LOONGARCH64ThreadContext.NPRGREG is 25. ++ */ ++ ++ if (Assert.ASSERTS_ENABLED) { ++ Assert.that(regs.length <= LOONGARCH64ThreadContext.NPRGREG, "size of register set is greater than " + LOONGARCH64ThreadContext.NPRGREG); ++ } ++ for (int i = 0; i < regs.length; i++) { ++ context.setRegister(i, regs[i]); ++ } ++ return context; ++ } ++ ++ public boolean canSetContext() throws DebuggerException { ++ return false; ++ } ++ ++ public void setContext(ThreadContext context) ++ throws IllegalThreadStateException, DebuggerException { ++ throw new DebuggerException("Unimplemented"); ++ } ++ ++ public String toString() { ++ return "t@" + id; ++ } ++ ++ public boolean equals(Object obj) { ++ if ((obj == null) || !(obj instanceof ProcLOONGARCH64Thread)) { ++ return false; ++ } ++ ++ return (((ProcLOONGARCH64Thread) obj).id == id); ++ } ++ ++ public int hashCode() { ++ return id; ++ } ++} +diff --git a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/proc/loongarch64/ProcLOONGARCH64ThreadContext.java b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/proc/loongarch64/ProcLOONGARCH64ThreadContext.java +new file mode 100644 +index 0000000000..ef5597ac4e +--- /dev/null ++++ b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/proc/loongarch64/ProcLOONGARCH64ThreadContext.java @@ -0,0 +1,47 @@ +/* + * Copyright (c) 2002, 2003, Oracle and/or its affiliates. All rights reserved. @@ -111076,9 +111688,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/j + return debugger.newAddress(getRegister(index)); + } +} -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/proc/loongarch64/ProcLOONGARCH64ThreadFactory.java b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/proc/loongarch64/ProcLOONGARCH64ThreadFactory.java ---- a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/proc/loongarch64/ProcLOONGARCH64ThreadFactory.java 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/proc/loongarch64/ProcLOONGARCH64ThreadFactory.java 2024-01-30 10:00:13.241415036 +0800 +diff --git a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/proc/loongarch64/ProcLOONGARCH64ThreadFactory.java b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/proc/loongarch64/ProcLOONGARCH64ThreadFactory.java +new file mode 100644 +index 0000000000..abad1bb38b +--- /dev/null ++++ b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/proc/loongarch64/ProcLOONGARCH64ThreadFactory.java @@ -0,0 +1,45 @@ +/* + * Copyright (c) 2002, Oracle and/or its affiliates. All rights reserved. @@ -111125,13 +111739,15 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/j + return new ProcLOONGARCH64Thread(debugger, id); + } +} -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/proc/loongarch64/ProcLOONGARCH64Thread.java b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/proc/loongarch64/ProcLOONGARCH64Thread.java ---- a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/proc/loongarch64/ProcLOONGARCH64Thread.java 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/proc/loongarch64/ProcLOONGARCH64Thread.java 2024-01-30 10:00:13.241415036 +0800 +diff --git a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/proc/mips64/ProcMIPS64Thread.java b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/proc/mips64/ProcMIPS64Thread.java +new file mode 100644 +index 0000000000..5c1e0be893 +--- /dev/null ++++ b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/proc/mips64/ProcMIPS64Thread.java @@ -0,0 +1,92 @@ +/* + * Copyright (c) 2002, 2003, Oracle and/or its affiliates. All rights reserved. -+ * Copyright (c) 2015, 2021, Loongson Technology. All rights reserved. ++ * Copyright (c) 2015, 2018, Loongson Technology. All rights reserved. + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. + * + * This code is free software; you can redistribute it and/or modify it @@ -111154,18 +111770,18 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/j + * + */ + -+package sun.jvm.hotspot.debugger.proc.loongarch64; ++package sun.jvm.hotspot.debugger.proc.mips64; + +import sun.jvm.hotspot.debugger.*; -+import sun.jvm.hotspot.debugger.loongarch64.*; ++import sun.jvm.hotspot.debugger.mips64.*; +import sun.jvm.hotspot.debugger.proc.*; +import sun.jvm.hotspot.utilities.*; + -+public class ProcLOONGARCH64Thread implements ThreadProxy { ++public class ProcMIPS64Thread implements ThreadProxy { + private ProcDebugger debugger; + private int id; + -+ public ProcLOONGARCH64Thread(ProcDebugger debugger, Address addr) { ++ public ProcMIPS64Thread(ProcDebugger debugger, Address addr) { + this.debugger = debugger; + + // FIXME: the size here should be configurable. However, making it @@ -111174,21 +111790,21 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/j + this.id = (int) addr.getCIntegerAt(0, 4, true); + } + -+ public ProcLOONGARCH64Thread(ProcDebugger debugger, long id) { ++ public ProcMIPS64Thread(ProcDebugger debugger, long id) { + this.debugger = debugger; + this.id = (int) id; + } + + public ThreadContext getContext() throws IllegalThreadStateException { -+ ProcLOONGARCH64ThreadContext context = new ProcLOONGARCH64ThreadContext(debugger); ++ ProcMIPS64ThreadContext context = new ProcMIPS64ThreadContext(debugger); + long[] regs = debugger.getThreadIntegerRegisterSet(id); + /* + _NGREG in reg.h is defined to be 19. Because we have included -+ debug registers LOONGARCH64ThreadContext.NPRGREG is 25. ++ debug registers MIPS64ThreadContext.NPRGREG is 25. + */ + + if (Assert.ASSERTS_ENABLED) { -+ Assert.that(regs.length <= LOONGARCH64ThreadContext.NPRGREG, "size of register set is greater than " + LOONGARCH64ThreadContext.NPRGREG); ++ Assert.that(regs.length <= MIPS64ThreadContext.NPRGREG, "size of register set is greater than " + MIPS64ThreadContext.NPRGREG); + } + for (int i = 0; i < regs.length; i++) { + context.setRegister(i, regs[i]); @@ -111210,20 +111826,22 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/j + } + + public boolean equals(Object obj) { -+ if ((obj == null) || !(obj instanceof ProcLOONGARCH64Thread)) { ++ if ((obj == null) || !(obj instanceof ProcMIPS64Thread)) { + return false; + } + -+ return (((ProcLOONGARCH64Thread) obj).id == id); ++ return (((ProcMIPS64Thread) obj).id == id); + } + + public int hashCode() { + return id; + } +} -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/proc/mips64/ProcMIPS64ThreadContext.java b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/proc/mips64/ProcMIPS64ThreadContext.java ---- a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/proc/mips64/ProcMIPS64ThreadContext.java 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/proc/mips64/ProcMIPS64ThreadContext.java 2024-01-30 10:00:13.241415036 +0800 +diff --git a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/proc/mips64/ProcMIPS64ThreadContext.java b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/proc/mips64/ProcMIPS64ThreadContext.java +new file mode 100644 +index 0000000000..d44223d768 +--- /dev/null ++++ b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/proc/mips64/ProcMIPS64ThreadContext.java @@ -0,0 +1,47 @@ +/* + * Copyright (c) 2002, 2003, Oracle and/or its affiliates. All rights reserved. @@ -111272,9 +111890,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/j + return debugger.newAddress(getRegister(index)); + } +} -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/proc/mips64/ProcMIPS64ThreadFactory.java b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/proc/mips64/ProcMIPS64ThreadFactory.java ---- a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/proc/mips64/ProcMIPS64ThreadFactory.java 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/proc/mips64/ProcMIPS64ThreadFactory.java 2024-01-30 10:00:13.241415036 +0800 +diff --git a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/proc/mips64/ProcMIPS64ThreadFactory.java b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/proc/mips64/ProcMIPS64ThreadFactory.java +new file mode 100644 +index 0000000000..bad478fc5c +--- /dev/null ++++ b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/proc/mips64/ProcMIPS64ThreadFactory.java @@ -0,0 +1,45 @@ +/* + * Copyright (c) 2002, Oracle and/or its affiliates. All rights reserved. @@ -111321,13 +111941,58 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/j + return new ProcMIPS64Thread(debugger, id); + } +} -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/proc/mips64/ProcMIPS64Thread.java b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/proc/mips64/ProcMIPS64Thread.java ---- a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/proc/mips64/ProcMIPS64Thread.java 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/proc/mips64/ProcMIPS64Thread.java 2024-01-30 10:00:13.241415036 +0800 -@@ -0,0 +1,92 @@ +diff --git a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/remote/RemoteDebuggerClient.java b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/remote/RemoteDebuggerClient.java +index b6253f6d63..5eecb08a10 100644 +--- a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/remote/RemoteDebuggerClient.java ++++ b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/remote/RemoteDebuggerClient.java +@@ -22,6 +22,12 @@ + * + */ + +/* -+ * Copyright (c) 2002, 2003, Oracle and/or its affiliates. All rights reserved. -+ * Copyright (c) 2015, 2018, Loongson Technology. All rights reserved. ++ * This file has been modified by Loongson Technology in 2021, These ++ * modifications are Copyright (c) 2019, 2021, Loongson Technology, and are made ++ * available on the same license terms set forth above. ++ */ ++ + package sun.jvm.hotspot.debugger.remote; + + import java.rmi.*; +@@ -34,6 +40,8 @@ import sun.jvm.hotspot.debugger.remote.sparc.*; + import sun.jvm.hotspot.debugger.remote.x86.*; + import sun.jvm.hotspot.debugger.remote.amd64.*; + import sun.jvm.hotspot.debugger.remote.ppc64.*; ++import sun.jvm.hotspot.debugger.remote.mips64.*; ++import sun.jvm.hotspot.debugger.remote.loongarch64.*; + + /** An implementation of Debugger which wraps a + RemoteDebugger, providing remote debugging via RMI. +@@ -76,6 +84,16 @@ public class RemoteDebuggerClient extends DebuggerBase implements JVMDebugger { + cachePageSize = 4096; + cacheNumPages = parseCacheNumPagesProperty(cacheSize / cachePageSize); + unalignedAccessesOkay = true; ++ } else if (cpu.equals("mips64") || cpu.equals("mips64el")) { ++ threadFactory = new RemoteMIPS64ThreadFactory(this); ++ cachePageSize = 4096; ++ cacheNumPages = parseCacheNumPagesProperty(cacheSize / cachePageSize); ++ unalignedAccessesOkay = true; ++ } else if (cpu.equals("loongarch64")) { ++ threadFactory = new RemoteLOONGARCH64ThreadFactory(this); ++ cachePageSize = 4096; ++ cacheNumPages = parseCacheNumPagesProperty(cacheSize / cachePageSize); ++ unalignedAccessesOkay = true; + } else { + try { + Class tf = Class.forName("sun.jvm.hotspot.debugger.remote." + +diff --git a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/remote/loongarch64/RemoteLOONGARCH64Thread.java b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/remote/loongarch64/RemoteLOONGARCH64Thread.java +new file mode 100644 +index 0000000000..242dd279e1 +--- /dev/null ++++ b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/remote/loongarch64/RemoteLOONGARCH64Thread.java +@@ -0,0 +1,54 @@ ++/* ++ * Copyright (c) 2002, Oracle and/or its affiliates. All rights reserved. ++ * Copyright (c) 2018, 2021, Loongson Technology. All rights reserved. + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. + * + * This code is free software; you can redistribute it and/or modify it @@ -111350,104 +112015,40 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/j + * + */ + -+package sun.jvm.hotspot.debugger.proc.mips64; ++package sun.jvm.hotspot.debugger.remote.loongarch64; + +import sun.jvm.hotspot.debugger.*; -+import sun.jvm.hotspot.debugger.mips64.*; -+import sun.jvm.hotspot.debugger.proc.*; ++import sun.jvm.hotspot.debugger.loongarch64.*; ++import sun.jvm.hotspot.debugger.remote.*; +import sun.jvm.hotspot.utilities.*; + -+public class ProcMIPS64Thread implements ThreadProxy { -+ private ProcDebugger debugger; -+ private int id; -+ -+ public ProcMIPS64Thread(ProcDebugger debugger, Address addr) { -+ this.debugger = debugger; -+ -+ // FIXME: the size here should be configurable. However, making it -+ // so would produce a dependency on the "types" package from the -+ // debugger package, which is not desired. -+ this.id = (int) addr.getCIntegerAt(0, 4, true); ++public class RemoteLOONGARCH64Thread extends RemoteThread { ++ public RemoteLOONGARCH64Thread(RemoteDebuggerClient debugger, Address addr) { ++ super(debugger, addr); + } + -+ public ProcMIPS64Thread(ProcDebugger debugger, long id) { -+ this.debugger = debugger; -+ this.id = (int) id; ++ public RemoteLOONGARCH64Thread(RemoteDebuggerClient debugger, long id) { ++ super(debugger, id); + } + + public ThreadContext getContext() throws IllegalThreadStateException { -+ ProcMIPS64ThreadContext context = new ProcMIPS64ThreadContext(debugger); -+ long[] regs = debugger.getThreadIntegerRegisterSet(id); -+ /* -+ _NGREG in reg.h is defined to be 19. Because we have included -+ debug registers MIPS64ThreadContext.NPRGREG is 25. -+ */ -+ ++ RemoteLOONGARCH64ThreadContext context = new RemoteLOONGARCH64ThreadContext(debugger); ++ long[] regs = (addr != null)? debugger.getThreadIntegerRegisterSet(addr) : ++ debugger.getThreadIntegerRegisterSet(id); + if (Assert.ASSERTS_ENABLED) { -+ Assert.that(regs.length <= MIPS64ThreadContext.NPRGREG, "size of register set is greater than " + MIPS64ThreadContext.NPRGREG); ++ Assert.that(regs.length == LOONGARCH64ThreadContext.NPRGREG, "size of register set must match"); + } + for (int i = 0; i < regs.length; i++) { + context.setRegister(i, regs[i]); + } + return context; + } -+ -+ public boolean canSetContext() throws DebuggerException { -+ return false; -+ } -+ -+ public void setContext(ThreadContext context) -+ throws IllegalThreadStateException, DebuggerException { -+ throw new DebuggerException("Unimplemented"); -+ } -+ -+ public String toString() { -+ return "t@" + id; -+ } -+ -+ public boolean equals(Object obj) { -+ if ((obj == null) || !(obj instanceof ProcMIPS64Thread)) { -+ return false; -+ } -+ -+ return (((ProcMIPS64Thread) obj).id == id); -+ } -+ -+ public int hashCode() { -+ return id; -+ } +} -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/proc/ProcDebuggerLocal.java b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/proc/ProcDebuggerLocal.java ---- a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/proc/ProcDebuggerLocal.java 2024-01-10 05:19:49.000000000 +0800 -+++ b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/proc/ProcDebuggerLocal.java 2024-01-30 10:00:13.241415036 +0800 -@@ -32,11 +32,13 @@ - import sun.jvm.hotspot.debugger.cdbg.*; - import sun.jvm.hotspot.debugger.proc.amd64.*; - import sun.jvm.hotspot.debugger.proc.aarch64.*; -+import sun.jvm.hotspot.debugger.proc.mips64.*; - import sun.jvm.hotspot.debugger.proc.sparc.*; - import sun.jvm.hotspot.debugger.proc.ppc64.*; - import sun.jvm.hotspot.debugger.proc.x86.*; - import sun.jvm.hotspot.debugger.ppc64.*; - import sun.jvm.hotspot.debugger.amd64.*; -+import sun.jvm.hotspot.debugger.mips64.*; - import sun.jvm.hotspot.debugger.aarch64.*; - import sun.jvm.hotspot.debugger.sparc.*; - import sun.jvm.hotspot.debugger.x86.*; -@@ -90,6 +92,10 @@ - threadFactory = new ProcAMD64ThreadFactory(this); - pcRegIndex = AMD64ThreadContext.RIP; - fpRegIndex = AMD64ThreadContext.RBP; -+ } else if (cpu.equals("mips64") || cpu.equals("mips64el")) { -+ threadFactory = new ProcMIPS64ThreadFactory(this); -+ pcRegIndex = MIPS64ThreadContext.PC; -+ fpRegIndex = MIPS64ThreadContext.FP; - } else if (cpu.equals("aarch64")) { - threadFactory = new ProcAARCH64ThreadFactory(this); - pcRegIndex = AARCH64ThreadContext.PC; -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/remote/loongarch64/RemoteLOONGARCH64ThreadContext.java b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/remote/loongarch64/RemoteLOONGARCH64ThreadContext.java ---- a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/remote/loongarch64/RemoteLOONGARCH64ThreadContext.java 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/remote/loongarch64/RemoteLOONGARCH64ThreadContext.java 2024-01-30 10:00:13.244748330 +0800 +diff --git a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/remote/loongarch64/RemoteLOONGARCH64ThreadContext.java b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/remote/loongarch64/RemoteLOONGARCH64ThreadContext.java +new file mode 100644 +index 0000000000..634d5ad049 +--- /dev/null ++++ b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/remote/loongarch64/RemoteLOONGARCH64ThreadContext.java @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2002, Oracle and/or its affiliates. All rights reserved. @@ -111500,9 +112101,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/j + return debugger.newAddress(getRegister(index)); + } +} -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/remote/loongarch64/RemoteLOONGARCH64ThreadFactory.java b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/remote/loongarch64/RemoteLOONGARCH64ThreadFactory.java ---- a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/remote/loongarch64/RemoteLOONGARCH64ThreadFactory.java 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/remote/loongarch64/RemoteLOONGARCH64ThreadFactory.java 2024-01-30 10:00:13.244748330 +0800 +diff --git a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/remote/loongarch64/RemoteLOONGARCH64ThreadFactory.java b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/remote/loongarch64/RemoteLOONGARCH64ThreadFactory.java +new file mode 100644 +index 0000000000..4fb9cc7c06 +--- /dev/null ++++ b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/remote/loongarch64/RemoteLOONGARCH64ThreadFactory.java @@ -0,0 +1,45 @@ +/* + * Copyright (c) 2002, Oracle and/or its affiliates. All rights reserved. @@ -111549,13 +112152,15 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/j + return new RemoteLOONGARCH64Thread(debugger, id); + } +} -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/remote/loongarch64/RemoteLOONGARCH64Thread.java b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/remote/loongarch64/RemoteLOONGARCH64Thread.java ---- a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/remote/loongarch64/RemoteLOONGARCH64Thread.java 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/remote/loongarch64/RemoteLOONGARCH64Thread.java 2024-01-30 10:00:13.244748330 +0800 +diff --git a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/remote/mips64/RemoteMIPS64Thread.java b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/remote/mips64/RemoteMIPS64Thread.java +new file mode 100644 +index 0000000000..c2f7d841f2 +--- /dev/null ++++ b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/remote/mips64/RemoteMIPS64Thread.java @@ -0,0 +1,54 @@ +/* + * Copyright (c) 2002, Oracle and/or its affiliates. All rights reserved. -+ * Copyright (c) 2018, 2021, Loongson Technology. All rights reserved. ++ * Copyright (c) 2018, Loongson Technology. All rights reserved. + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. + * + * This code is free software; you can redistribute it and/or modify it @@ -111578,28 +112183,28 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/j + * + */ + -+package sun.jvm.hotspot.debugger.remote.loongarch64; ++package sun.jvm.hotspot.debugger.remote.mips64; + +import sun.jvm.hotspot.debugger.*; -+import sun.jvm.hotspot.debugger.loongarch64.*; ++import sun.jvm.hotspot.debugger.mips64.*; +import sun.jvm.hotspot.debugger.remote.*; +import sun.jvm.hotspot.utilities.*; + -+public class RemoteLOONGARCH64Thread extends RemoteThread { -+ public RemoteLOONGARCH64Thread(RemoteDebuggerClient debugger, Address addr) { ++public class RemoteMIPS64Thread extends RemoteThread { ++ public RemoteMIPS64Thread(RemoteDebuggerClient debugger, Address addr) { + super(debugger, addr); + } + -+ public RemoteLOONGARCH64Thread(RemoteDebuggerClient debugger, long id) { ++ public RemoteMIPS64Thread(RemoteDebuggerClient debugger, long id) { + super(debugger, id); + } + + public ThreadContext getContext() throws IllegalThreadStateException { -+ RemoteLOONGARCH64ThreadContext context = new RemoteLOONGARCH64ThreadContext(debugger); ++ RemoteMIPS64ThreadContext context = new RemoteMIPS64ThreadContext(debugger); + long[] regs = (addr != null)? debugger.getThreadIntegerRegisterSet(addr) : + debugger.getThreadIntegerRegisterSet(id); + if (Assert.ASSERTS_ENABLED) { -+ Assert.that(regs.length == LOONGARCH64ThreadContext.NPRGREG, "size of register set must match"); ++ Assert.that(regs.length == MIPS64ThreadContext.NPRGREG, "size of register set must match"); + } + for (int i = 0; i < regs.length; i++) { + context.setRegister(i, regs[i]); @@ -111607,9 +112212,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/j + return context; + } +} -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/remote/mips64/RemoteMIPS64ThreadContext.java b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/remote/mips64/RemoteMIPS64ThreadContext.java ---- a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/remote/mips64/RemoteMIPS64ThreadContext.java 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/remote/mips64/RemoteMIPS64ThreadContext.java 2024-01-30 10:00:13.244748330 +0800 +diff --git a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/remote/mips64/RemoteMIPS64ThreadContext.java b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/remote/mips64/RemoteMIPS64ThreadContext.java +new file mode 100644 +index 0000000000..23646905d7 +--- /dev/null ++++ b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/remote/mips64/RemoteMIPS64ThreadContext.java @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2002, Oracle and/or its affiliates. All rights reserved. @@ -111662,9 +112269,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/j + return debugger.newAddress(getRegister(index)); + } +} -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/remote/mips64/RemoteMIPS64ThreadFactory.java b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/remote/mips64/RemoteMIPS64ThreadFactory.java ---- a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/remote/mips64/RemoteMIPS64ThreadFactory.java 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/remote/mips64/RemoteMIPS64ThreadFactory.java 2024-01-30 10:00:13.244748330 +0800 +diff --git a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/remote/mips64/RemoteMIPS64ThreadFactory.java b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/remote/mips64/RemoteMIPS64ThreadFactory.java +new file mode 100644 +index 0000000000..b39b014490 +--- /dev/null ++++ b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/remote/mips64/RemoteMIPS64ThreadFactory.java @@ -0,0 +1,45 @@ +/* + * Copyright (c) 2002, Oracle and/or its affiliates. All rights reserved. @@ -111696,82 +112305,25 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/j +import sun.jvm.hotspot.debugger.*; +import sun.jvm.hotspot.debugger.remote.*; + -+public class RemoteMIPS64ThreadFactory implements RemoteThreadFactory { -+ private RemoteDebuggerClient debugger; -+ -+ public RemoteMIPS64ThreadFactory(RemoteDebuggerClient debugger) { -+ this.debugger = debugger; -+ } -+ -+ public ThreadProxy createThreadWrapper(Address threadIdentifierAddr) { -+ return new RemoteMIPS64Thread(debugger, threadIdentifierAddr); -+ } -+ -+ public ThreadProxy createThreadWrapper(long id) { -+ return new RemoteMIPS64Thread(debugger, id); -+ } -+} -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/remote/mips64/RemoteMIPS64Thread.java b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/remote/mips64/RemoteMIPS64Thread.java ---- a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/remote/mips64/RemoteMIPS64Thread.java 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/remote/mips64/RemoteMIPS64Thread.java 2024-01-30 10:00:13.244748330 +0800 -@@ -0,0 +1,54 @@ -+/* -+ * Copyright (c) 2002, Oracle and/or its affiliates. All rights reserved. -+ * Copyright (c) 2018, Loongson Technology. All rights reserved. -+ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. -+ * -+ * This code is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 only, as -+ * published by the Free Software Foundation. -+ * -+ * This code is distributed in the hope that it will be useful, but WITHOUT -+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -+ * version 2 for more details (a copy is included in the LICENSE file that -+ * accompanied this code). -+ * -+ * You should have received a copy of the GNU General Public License version -+ * 2 along with this work; if not, write to the Free Software Foundation, -+ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. -+ * -+ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA -+ * or visit www.oracle.com if you need additional information or have any -+ * questions. -+ * -+ */ -+ -+package sun.jvm.hotspot.debugger.remote.mips64; -+ -+import sun.jvm.hotspot.debugger.*; -+import sun.jvm.hotspot.debugger.mips64.*; -+import sun.jvm.hotspot.debugger.remote.*; -+import sun.jvm.hotspot.utilities.*; -+ -+public class RemoteMIPS64Thread extends RemoteThread { -+ public RemoteMIPS64Thread(RemoteDebuggerClient debugger, Address addr) { -+ super(debugger, addr); ++public class RemoteMIPS64ThreadFactory implements RemoteThreadFactory { ++ private RemoteDebuggerClient debugger; ++ ++ public RemoteMIPS64ThreadFactory(RemoteDebuggerClient debugger) { ++ this.debugger = debugger; + } + -+ public RemoteMIPS64Thread(RemoteDebuggerClient debugger, long id) { -+ super(debugger, id); ++ public ThreadProxy createThreadWrapper(Address threadIdentifierAddr) { ++ return new RemoteMIPS64Thread(debugger, threadIdentifierAddr); + } + -+ public ThreadContext getContext() throws IllegalThreadStateException { -+ RemoteMIPS64ThreadContext context = new RemoteMIPS64ThreadContext(debugger); -+ long[] regs = (addr != null)? debugger.getThreadIntegerRegisterSet(addr) : -+ debugger.getThreadIntegerRegisterSet(id); -+ if (Assert.ASSERTS_ENABLED) { -+ Assert.that(regs.length == MIPS64ThreadContext.NPRGREG, "size of register set must match"); -+ } -+ for (int i = 0; i < regs.length; i++) { -+ context.setRegister(i, regs[i]); -+ } -+ return context; ++ public ThreadProxy createThreadWrapper(long id) { ++ return new RemoteMIPS64Thread(debugger, id); + } +} -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/remote/RemoteDebuggerClient.java b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/remote/RemoteDebuggerClient.java ---- a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/remote/RemoteDebuggerClient.java 2024-01-10 05:19:49.000000000 +0800 -+++ b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/remote/RemoteDebuggerClient.java 2024-01-30 10:00:13.241415036 +0800 +diff --git a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/Threads.java b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/Threads.java +index 190062785a..04681fa0e7 100644 +--- a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/Threads.java ++++ b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/Threads.java @@ -22,6 +22,12 @@ * */ @@ -111782,74 +112334,34 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/j + * available on the same license terms set forth above. + */ + - package sun.jvm.hotspot.debugger.remote; - - import java.rmi.*; -@@ -34,6 +40,8 @@ - import sun.jvm.hotspot.debugger.remote.x86.*; - import sun.jvm.hotspot.debugger.remote.amd64.*; - import sun.jvm.hotspot.debugger.remote.ppc64.*; -+import sun.jvm.hotspot.debugger.remote.mips64.*; -+import sun.jvm.hotspot.debugger.remote.loongarch64.*; - - /** An implementation of Debugger which wraps a - RemoteDebugger, providing remote debugging via RMI. -@@ -76,6 +84,16 @@ - cachePageSize = 4096; - cacheNumPages = parseCacheNumPagesProperty(cacheSize / cachePageSize); - unalignedAccessesOkay = true; -+ } else if (cpu.equals("mips64") || cpu.equals("mips64el")) { -+ threadFactory = new RemoteMIPS64ThreadFactory(this); -+ cachePageSize = 4096; -+ cacheNumPages = parseCacheNumPagesProperty(cacheSize / cachePageSize); -+ unalignedAccessesOkay = true; -+ } else if (cpu.equals("loongarch64")) { -+ threadFactory = new RemoteLOONGARCH64ThreadFactory(this); -+ cachePageSize = 4096; -+ cacheNumPages = parseCacheNumPagesProperty(cacheSize / cachePageSize); -+ unalignedAccessesOkay = true; - } else { - try { - Class tf = Class.forName("sun.jvm.hotspot.debugger.remote." + -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/HotSpotAgent.java b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/HotSpotAgent.java ---- a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/HotSpotAgent.java 2024-01-10 05:19:49.000000000 +0800 -+++ b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/HotSpotAgent.java 2024-01-30 10:00:13.228081861 +0800 -@@ -23,6 +23,12 @@ - * - */ - -+/* -+ * This file has been modified by Loongson Technology in 2021. These -+ * modifications are Copyright (c) 2018, 2021, Loongson Technology, and are made -+ * available on the same license terms set forth above. -+ * -+ */ - package sun.jvm.hotspot; + package sun.jvm.hotspot.runtime; - import java.rmi.RemoteException; -@@ -39,6 +45,8 @@ - import sun.jvm.hotspot.debugger.MachineDescriptionIntelX86; - import sun.jvm.hotspot.debugger.MachineDescriptionSPARC32Bit; - import sun.jvm.hotspot.debugger.MachineDescriptionSPARC64Bit; -+import sun.jvm.hotspot.debugger.MachineDescriptionMIPS64; -+import sun.jvm.hotspot.debugger.MachineDescriptionLOONGARCH64; - import sun.jvm.hotspot.debugger.NoSuchSymbolException; - import sun.jvm.hotspot.debugger.bsd.BsdDebuggerLocal; - import sun.jvm.hotspot.debugger.linux.LinuxDebuggerLocal; -@@ -598,6 +606,10 @@ + import java.util.*; +@@ -39,6 +45,8 @@ import sun.jvm.hotspot.runtime.linux_x86.LinuxX86JavaThreadPDAccess; + import sun.jvm.hotspot.runtime.linux_amd64.LinuxAMD64JavaThreadPDAccess; + import sun.jvm.hotspot.runtime.linux_aarch64.LinuxAARCH64JavaThreadPDAccess; + import sun.jvm.hotspot.runtime.linux_ppc64.LinuxPPC64JavaThreadPDAccess; ++import sun.jvm.hotspot.runtime.linux_mips64.LinuxMIPS64JavaThreadPDAccess; ++import sun.jvm.hotspot.runtime.linux_loongarch64.LinuxLOONGARCH64JavaThreadPDAccess; + import sun.jvm.hotspot.runtime.linux_sparc.LinuxSPARCJavaThreadPDAccess; + import sun.jvm.hotspot.runtime.bsd_x86.BsdX86JavaThreadPDAccess; + import sun.jvm.hotspot.runtime.bsd_amd64.BsdAMD64JavaThreadPDAccess; +@@ -99,6 +107,10 @@ public class Threads { + access = new LinuxPPC64JavaThreadPDAccess(); + } else if (cpu.equals("aarch64")) { + access = new LinuxAARCH64JavaThreadPDAccess(); ++ } else if (cpu.equals("mips64")) { ++ access = new LinuxMIPS64JavaThreadPDAccess(); ++ } else if (cpu.equals("loongarch64")) { ++ access = new LinuxLOONGARCH64JavaThreadPDAccess(); } else { - machDesc = new MachineDescriptionSPARC32Bit(); - } -+ } else if (cpu.equals("mips64")) { -+ machDesc = new MachineDescriptionMIPS64(); -+ } else if (cpu.equals("loongarch64")) { -+ machDesc = new MachineDescriptionLOONGARCH64(); - } else { - try { - machDesc = (MachineDescription) -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/linux_loongarch64/LinuxLOONGARCH64JavaThreadPDAccess.java b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/linux_loongarch64/LinuxLOONGARCH64JavaThreadPDAccess.java ---- a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/linux_loongarch64/LinuxLOONGARCH64JavaThreadPDAccess.java 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/linux_loongarch64/LinuxLOONGARCH64JavaThreadPDAccess.java 2024-01-30 10:00:13.264748090 +0800 + try { + access = (JavaThreadPDAccess) +diff --git a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/linux_loongarch64/LinuxLOONGARCH64JavaThreadPDAccess.java b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/linux_loongarch64/LinuxLOONGARCH64JavaThreadPDAccess.java +new file mode 100644 +index 0000000000..ee1003e352 +--- /dev/null ++++ b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/linux_loongarch64/LinuxLOONGARCH64JavaThreadPDAccess.java @@ -0,0 +1,133 @@ +/* + * Copyright (c) 2014, Oracle and/or its affiliates. All rights reserved. @@ -111984,9 +112496,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/j + return debugger.getThreadForIdentifierAddress(threadIdAddr); + } +} -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/linux_mips64/LinuxMIPS64JavaThreadPDAccess.java b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/linux_mips64/LinuxMIPS64JavaThreadPDAccess.java ---- a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/linux_mips64/LinuxMIPS64JavaThreadPDAccess.java 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/linux_mips64/LinuxMIPS64JavaThreadPDAccess.java 2024-01-30 10:00:13.264748090 +0800 +diff --git a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/linux_mips64/LinuxMIPS64JavaThreadPDAccess.java b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/linux_mips64/LinuxMIPS64JavaThreadPDAccess.java +new file mode 100644 +index 0000000000..181f431b64 +--- /dev/null ++++ b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/linux_mips64/LinuxMIPS64JavaThreadPDAccess.java @@ -0,0 +1,133 @@ +/* + * Copyright (c) 2014, Oracle and/or its affiliates. All rights reserved. @@ -112121,9 +112635,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/j + return debugger.getThreadForIdentifierAddress(threadIdAddr); + } +} -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/loongarch64/LOONGARCH64CurrentFrameGuess.java b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/loongarch64/LOONGARCH64CurrentFrameGuess.java ---- a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/loongarch64/LOONGARCH64CurrentFrameGuess.java 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/loongarch64/LOONGARCH64CurrentFrameGuess.java 2024-01-30 10:00:13.264748090 +0800 +diff --git a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/loongarch64/LOONGARCH64CurrentFrameGuess.java b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/loongarch64/LOONGARCH64CurrentFrameGuess.java +new file mode 100644 +index 0000000000..824270e132 +--- /dev/null ++++ b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/loongarch64/LOONGARCH64CurrentFrameGuess.java @@ -0,0 +1,250 @@ +/* + * Copyright (c) 2001, 2006, Oracle and/or its affiliates. All rights reserved. @@ -112375,9 +112891,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/j + pcFound = pc; + } +} -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/loongarch64/LOONGARCH64Frame.java b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/loongarch64/LOONGARCH64Frame.java ---- a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/loongarch64/LOONGARCH64Frame.java 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/loongarch64/LOONGARCH64Frame.java 2024-01-30 10:00:13.264748090 +0800 +diff --git a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/loongarch64/LOONGARCH64Frame.java b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/loongarch64/LOONGARCH64Frame.java +new file mode 100644 +index 0000000000..058afc94d0 +--- /dev/null ++++ b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/loongarch64/LOONGARCH64Frame.java @@ -0,0 +1,526 @@ +/* + * Copyright (c) 2001, 2015, Oracle and/or its affiliates. All rights reserved. @@ -112905,9 +113423,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/j + } + } +} -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/loongarch64/LOONGARCH64JavaCallWrapper.java b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/loongarch64/LOONGARCH64JavaCallWrapper.java ---- a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/loongarch64/LOONGARCH64JavaCallWrapper.java 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/loongarch64/LOONGARCH64JavaCallWrapper.java 2024-01-30 10:00:13.264748090 +0800 +diff --git a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/loongarch64/LOONGARCH64JavaCallWrapper.java b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/loongarch64/LOONGARCH64JavaCallWrapper.java +new file mode 100644 +index 0000000000..0625e10a41 +--- /dev/null ++++ b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/loongarch64/LOONGARCH64JavaCallWrapper.java @@ -0,0 +1,57 @@ +/* + * Copyright (c) 2001, 2002, Oracle and/or its affiliates. All rights reserved. @@ -112966,9 +113486,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/j + return lastJavaFPField.getValue(addr.addOffsetTo(anchorField.getOffset())); + } +} -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/loongarch64/LOONGARCH64RegisterMap.java b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/loongarch64/LOONGARCH64RegisterMap.java ---- a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/loongarch64/LOONGARCH64RegisterMap.java 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/loongarch64/LOONGARCH64RegisterMap.java 2024-01-30 10:00:13.264748090 +0800 +diff --git a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/loongarch64/LOONGARCH64RegisterMap.java b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/loongarch64/LOONGARCH64RegisterMap.java +new file mode 100644 +index 0000000000..2cf904d388 +--- /dev/null ++++ b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/loongarch64/LOONGARCH64RegisterMap.java @@ -0,0 +1,52 @@ +/* + * Copyright (c) 2001, 2012, Oracle and/or its affiliates. All rights reserved. @@ -113022,9 +113544,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/j + protected void initializeFromPD(RegisterMap map) {} + protected Address getLocationPD(VMReg reg) { return null; } +} -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/mips64/MIPS64CurrentFrameGuess.java b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/mips64/MIPS64CurrentFrameGuess.java ---- a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/mips64/MIPS64CurrentFrameGuess.java 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/mips64/MIPS64CurrentFrameGuess.java 2024-01-30 10:00:13.264748090 +0800 +diff --git a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/mips64/MIPS64CurrentFrameGuess.java b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/mips64/MIPS64CurrentFrameGuess.java +new file mode 100644 +index 0000000000..c11458abe2 +--- /dev/null ++++ b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/mips64/MIPS64CurrentFrameGuess.java @@ -0,0 +1,217 @@ +/* + * Copyright (c) 2001, 2006, Oracle and/or its affiliates. All rights reserved. @@ -113243,9 +113767,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/j + pcFound = pc; + } +} -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/mips64/MIPS64Frame.java b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/mips64/MIPS64Frame.java ---- a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/mips64/MIPS64Frame.java 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/mips64/MIPS64Frame.java 2024-01-30 10:00:13.264748090 +0800 +diff --git a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/mips64/MIPS64Frame.java b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/mips64/MIPS64Frame.java +new file mode 100644 +index 0000000000..65d88016ea +--- /dev/null ++++ b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/mips64/MIPS64Frame.java @@ -0,0 +1,537 @@ +/* + * Copyright (c) 2001, 2015, Oracle and/or its affiliates. All rights reserved. @@ -113784,9 +114310,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/j + } + } +} -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/mips64/MIPS64JavaCallWrapper.java b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/mips64/MIPS64JavaCallWrapper.java ---- a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/mips64/MIPS64JavaCallWrapper.java 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/mips64/MIPS64JavaCallWrapper.java 2024-01-30 10:00:13.264748090 +0800 +diff --git a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/mips64/MIPS64JavaCallWrapper.java b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/mips64/MIPS64JavaCallWrapper.java +new file mode 100644 +index 0000000000..dfe3066af0 +--- /dev/null ++++ b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/mips64/MIPS64JavaCallWrapper.java @@ -0,0 +1,57 @@ +/* + * Copyright (c) 2001, 2002, Oracle and/or its affiliates. All rights reserved. @@ -113845,9 +114373,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/j + return lastJavaFPField.getValue(addr.addOffsetTo(anchorField.getOffset())); + } +} -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/mips64/MIPS64RegisterMap.java b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/mips64/MIPS64RegisterMap.java ---- a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/mips64/MIPS64RegisterMap.java 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/mips64/MIPS64RegisterMap.java 2024-01-30 10:00:13.268081384 +0800 +diff --git a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/mips64/MIPS64RegisterMap.java b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/mips64/MIPS64RegisterMap.java +new file mode 100644 +index 0000000000..f2da760af4 +--- /dev/null ++++ b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/mips64/MIPS64RegisterMap.java @@ -0,0 +1,52 @@ +/* + * Copyright (c) 2001, 2012, Oracle and/or its affiliates. All rights reserved. @@ -113901,45 +114431,10 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/j + protected void initializeFromPD(RegisterMap map) {} + protected Address getLocationPD(VMReg reg) { return null; } +} -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/Threads.java b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/Threads.java ---- a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/Threads.java 2024-01-10 05:19:49.000000000 +0800 -+++ b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/Threads.java 2024-01-30 10:00:13.264748090 +0800 -@@ -22,6 +22,12 @@ - * - */ - -+/* -+ * This file has been modified by Loongson Technology in 2021, These -+ * modifications are Copyright (c) 2019, 2021, Loongson Technology, and are made -+ * available on the same license terms set forth above. -+ */ -+ - package sun.jvm.hotspot.runtime; - - import java.util.*; -@@ -39,6 +45,8 @@ - import sun.jvm.hotspot.runtime.linux_amd64.LinuxAMD64JavaThreadPDAccess; - import sun.jvm.hotspot.runtime.linux_aarch64.LinuxAARCH64JavaThreadPDAccess; - import sun.jvm.hotspot.runtime.linux_ppc64.LinuxPPC64JavaThreadPDAccess; -+import sun.jvm.hotspot.runtime.linux_mips64.LinuxMIPS64JavaThreadPDAccess; -+import sun.jvm.hotspot.runtime.linux_loongarch64.LinuxLOONGARCH64JavaThreadPDAccess; - import sun.jvm.hotspot.runtime.linux_sparc.LinuxSPARCJavaThreadPDAccess; - import sun.jvm.hotspot.runtime.bsd_x86.BsdX86JavaThreadPDAccess; - import sun.jvm.hotspot.runtime.bsd_amd64.BsdAMD64JavaThreadPDAccess; -@@ -99,6 +107,10 @@ - access = new LinuxPPC64JavaThreadPDAccess(); - } else if (cpu.equals("aarch64")) { - access = new LinuxAARCH64JavaThreadPDAccess(); -+ } else if (cpu.equals("mips64")) { -+ access = new LinuxMIPS64JavaThreadPDAccess(); -+ } else if (cpu.equals("loongarch64")) { -+ access = new LinuxLOONGARCH64JavaThreadPDAccess(); - } else { - try { - access = (JavaThreadPDAccess) -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/utilities/PlatformInfo.java b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/utilities/PlatformInfo.java ---- a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/utilities/PlatformInfo.java 2024-01-10 05:19:49.000000000 +0800 -+++ b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/utilities/PlatformInfo.java 2024-01-30 10:00:13.274747971 +0800 +diff --git a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/utilities/PlatformInfo.java b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/utilities/PlatformInfo.java +index 7d7a6107ca..06d79318d9 100644 +--- a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/utilities/PlatformInfo.java ++++ b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/utilities/PlatformInfo.java @@ -22,6 +22,13 @@ * */ @@ -113954,7 +114449,7 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/j package sun.jvm.hotspot.utilities; /** Provides canonicalized OS and CPU information for the rest of the -@@ -54,7 +61,7 @@ +@@ -54,7 +61,7 @@ public class PlatformInfo { public static boolean knownCPU(String cpu) { final String[] KNOWN = @@ -113963,7 +114458,7 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/j for(String s : KNOWN) { if(s.equals(cpu)) -@@ -101,6 +108,12 @@ +@@ -101,6 +108,12 @@ public class PlatformInfo { if (cpu.equals("ppc64le")) return "ppc64"; @@ -113976,9 +114471,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/j return cpu; } -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/jdk.internal.vm.ci/share/classes/jdk.vm.ci.hotspot.loongarch64/src/jdk/vm/ci/hotspot/loongarch64/LoongArch64HotSpotJVMCIBackendFactory.java b/src/jdk.internal.vm.ci/share/classes/jdk.vm.ci.hotspot.loongarch64/src/jdk/vm/ci/hotspot/loongarch64/LoongArch64HotSpotJVMCIBackendFactory.java ---- a/src/jdk.internal.vm.ci/share/classes/jdk.vm.ci.hotspot.loongarch64/src/jdk/vm/ci/hotspot/loongarch64/LoongArch64HotSpotJVMCIBackendFactory.java 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/jdk.internal.vm.ci/share/classes/jdk.vm.ci.hotspot.loongarch64/src/jdk/vm/ci/hotspot/loongarch64/LoongArch64HotSpotJVMCIBackendFactory.java 2024-01-30 10:00:13.304747615 +0800 +diff --git a/src/jdk.internal.vm.ci/share/classes/jdk.vm.ci.hotspot.loongarch64/src/jdk/vm/ci/hotspot/loongarch64/LoongArch64HotSpotJVMCIBackendFactory.java b/src/jdk.internal.vm.ci/share/classes/jdk.vm.ci.hotspot.loongarch64/src/jdk/vm/ci/hotspot/loongarch64/LoongArch64HotSpotJVMCIBackendFactory.java +new file mode 100644 +index 0000000000..0d3953ddff +--- /dev/null ++++ b/src/jdk.internal.vm.ci/share/classes/jdk.vm.ci.hotspot.loongarch64/src/jdk/vm/ci/hotspot/loongarch64/LoongArch64HotSpotJVMCIBackendFactory.java @@ -0,0 +1,220 @@ +/* + * Copyright (c) 2015, 2022, Oracle and/or its affiliates. All rights reserved. @@ -114200,9 +114697,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/j + return new JVMCIBackend(metaAccess, codeCache, constantReflection, stackIntrospection); + } +} -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/jdk.internal.vm.ci/share/classes/jdk.vm.ci.hotspot.loongarch64/src/jdk/vm/ci/hotspot/loongarch64/LoongArch64HotSpotRegisterConfig.java b/src/jdk.internal.vm.ci/share/classes/jdk.vm.ci.hotspot.loongarch64/src/jdk/vm/ci/hotspot/loongarch64/LoongArch64HotSpotRegisterConfig.java ---- a/src/jdk.internal.vm.ci/share/classes/jdk.vm.ci.hotspot.loongarch64/src/jdk/vm/ci/hotspot/loongarch64/LoongArch64HotSpotRegisterConfig.java 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/jdk.internal.vm.ci/share/classes/jdk.vm.ci.hotspot.loongarch64/src/jdk/vm/ci/hotspot/loongarch64/LoongArch64HotSpotRegisterConfig.java 2024-01-30 10:00:13.304747615 +0800 +diff --git a/src/jdk.internal.vm.ci/share/classes/jdk.vm.ci.hotspot.loongarch64/src/jdk/vm/ci/hotspot/loongarch64/LoongArch64HotSpotRegisterConfig.java b/src/jdk.internal.vm.ci/share/classes/jdk.vm.ci.hotspot.loongarch64/src/jdk/vm/ci/hotspot/loongarch64/LoongArch64HotSpotRegisterConfig.java +new file mode 100644 +index 0000000000..2ee6a4b847 +--- /dev/null ++++ b/src/jdk.internal.vm.ci/share/classes/jdk.vm.ci.hotspot.loongarch64/src/jdk/vm/ci/hotspot/loongarch64/LoongArch64HotSpotRegisterConfig.java @@ -0,0 +1,297 @@ +/* + * Copyright (c) 2015, 2022, Oracle and/or its affiliates. All rights reserved. @@ -114501,9 +115000,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/j + return String.format("Allocatable: " + getAllocatableRegisters() + "%n" + "CallerSave: " + getCallerSaveRegisters() + "%n"); + } +} -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/jdk.internal.vm.ci/share/classes/jdk.vm.ci.hotspot.loongarch64/src/jdk/vm/ci/hotspot/loongarch64/LoongArch64HotSpotVMConfig.java b/src/jdk.internal.vm.ci/share/classes/jdk.vm.ci.hotspot.loongarch64/src/jdk/vm/ci/hotspot/loongarch64/LoongArch64HotSpotVMConfig.java ---- a/src/jdk.internal.vm.ci/share/classes/jdk.vm.ci.hotspot.loongarch64/src/jdk/vm/ci/hotspot/loongarch64/LoongArch64HotSpotVMConfig.java 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/jdk.internal.vm.ci/share/classes/jdk.vm.ci.hotspot.loongarch64/src/jdk/vm/ci/hotspot/loongarch64/LoongArch64HotSpotVMConfig.java 2024-01-30 10:00:13.304747615 +0800 +diff --git a/src/jdk.internal.vm.ci/share/classes/jdk.vm.ci.hotspot.loongarch64/src/jdk/vm/ci/hotspot/loongarch64/LoongArch64HotSpotVMConfig.java b/src/jdk.internal.vm.ci/share/classes/jdk.vm.ci.hotspot.loongarch64/src/jdk/vm/ci/hotspot/loongarch64/LoongArch64HotSpotVMConfig.java +new file mode 100644 +index 0000000000..c8605976a0 +--- /dev/null ++++ b/src/jdk.internal.vm.ci/share/classes/jdk.vm.ci.hotspot.loongarch64/src/jdk/vm/ci/hotspot/loongarch64/LoongArch64HotSpotVMConfig.java @@ -0,0 +1,77 @@ +/* + * Copyright (c) 2016, 2022, Oracle and/or its affiliates. All rights reserved. @@ -114582,9 +115083,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/j + final long loongarch64UAL = getConstant("VM_Version::CPU_UAL", Long.class); + // Checkstyle: resume +} -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/jdk.internal.vm.ci/share/classes/jdk.vm.ci.hotspot.loongarch64/src/jdk/vm/ci/hotspot/loongarch64/package-info.java b/src/jdk.internal.vm.ci/share/classes/jdk.vm.ci.hotspot.loongarch64/src/jdk/vm/ci/hotspot/loongarch64/package-info.java ---- a/src/jdk.internal.vm.ci/share/classes/jdk.vm.ci.hotspot.loongarch64/src/jdk/vm/ci/hotspot/loongarch64/package-info.java 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/jdk.internal.vm.ci/share/classes/jdk.vm.ci.hotspot.loongarch64/src/jdk/vm/ci/hotspot/loongarch64/package-info.java 2024-01-30 10:00:13.304747615 +0800 +diff --git a/src/jdk.internal.vm.ci/share/classes/jdk.vm.ci.hotspot.loongarch64/src/jdk/vm/ci/hotspot/loongarch64/package-info.java b/src/jdk.internal.vm.ci/share/classes/jdk.vm.ci.hotspot.loongarch64/src/jdk/vm/ci/hotspot/loongarch64/package-info.java +new file mode 100644 +index 0000000000..1048ea9d64 +--- /dev/null ++++ b/src/jdk.internal.vm.ci/share/classes/jdk.vm.ci.hotspot.loongarch64/src/jdk/vm/ci/hotspot/loongarch64/package-info.java @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2018, 2022, Oracle and/or its affiliates. All rights reserved. @@ -114614,9 +115117,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/j + * The LoongArch64 HotSpot specific portions of the JVMCI API. + */ +package jdk.vm.ci.hotspot.loongarch64; -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/jdk.internal.vm.ci/share/classes/jdk.vm.ci.loongarch64/src/jdk/vm/ci/loongarch64/LoongArch64.java b/src/jdk.internal.vm.ci/share/classes/jdk.vm.ci.loongarch64/src/jdk/vm/ci/loongarch64/LoongArch64.java ---- a/src/jdk.internal.vm.ci/share/classes/jdk.vm.ci.loongarch64/src/jdk/vm/ci/loongarch64/LoongArch64.java 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/jdk.internal.vm.ci/share/classes/jdk.vm.ci.loongarch64/src/jdk/vm/ci/loongarch64/LoongArch64.java 2024-01-30 10:00:13.308080909 +0800 +diff --git a/src/jdk.internal.vm.ci/share/classes/jdk.vm.ci.loongarch64/src/jdk/vm/ci/loongarch64/LoongArch64.java b/src/jdk.internal.vm.ci/share/classes/jdk.vm.ci.loongarch64/src/jdk/vm/ci/loongarch64/LoongArch64.java +new file mode 100644 +index 0000000000..1bb12e7a5f +--- /dev/null ++++ b/src/jdk.internal.vm.ci/share/classes/jdk.vm.ci.loongarch64/src/jdk/vm/ci/loongarch64/LoongArch64.java @@ -0,0 +1,247 @@ +/* + * Copyright (c) 2015, 2022, Oracle and/or its affiliates. All rights reserved. @@ -114865,9 +115370,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/j + } + } +} -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/jdk.internal.vm.ci/share/classes/jdk.vm.ci.loongarch64/src/jdk/vm/ci/loongarch64/LoongArch64Kind.java b/src/jdk.internal.vm.ci/share/classes/jdk.vm.ci.loongarch64/src/jdk/vm/ci/loongarch64/LoongArch64Kind.java ---- a/src/jdk.internal.vm.ci/share/classes/jdk.vm.ci.loongarch64/src/jdk/vm/ci/loongarch64/LoongArch64Kind.java 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/jdk.internal.vm.ci/share/classes/jdk.vm.ci.loongarch64/src/jdk/vm/ci/loongarch64/LoongArch64Kind.java 2024-01-30 10:00:13.308080909 +0800 +diff --git a/src/jdk.internal.vm.ci/share/classes/jdk.vm.ci.loongarch64/src/jdk/vm/ci/loongarch64/LoongArch64Kind.java b/src/jdk.internal.vm.ci/share/classes/jdk.vm.ci.loongarch64/src/jdk/vm/ci/loongarch64/LoongArch64Kind.java +new file mode 100644 +index 0000000000..84b7f2027f +--- /dev/null ++++ b/src/jdk.internal.vm.ci/share/classes/jdk.vm.ci.loongarch64/src/jdk/vm/ci/loongarch64/LoongArch64Kind.java @@ -0,0 +1,163 @@ +/* + * Copyright (c) 2015, 2022, Oracle and/or its affiliates. All rights reserved. @@ -115032,9 +115539,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/j + } + } +} -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/jdk.internal.vm.ci/share/classes/jdk.vm.ci.loongarch64/src/jdk/vm/ci/loongarch64/package-info.java b/src/jdk.internal.vm.ci/share/classes/jdk.vm.ci.loongarch64/src/jdk/vm/ci/loongarch64/package-info.java ---- a/src/jdk.internal.vm.ci/share/classes/jdk.vm.ci.loongarch64/src/jdk/vm/ci/loongarch64/package-info.java 1970-01-01 08:00:00.000000000 +0800 -+++ b/src/jdk.internal.vm.ci/share/classes/jdk.vm.ci.loongarch64/src/jdk/vm/ci/loongarch64/package-info.java 2024-01-30 10:00:13.308080909 +0800 +diff --git a/src/jdk.internal.vm.ci/share/classes/jdk.vm.ci.loongarch64/src/jdk/vm/ci/loongarch64/package-info.java b/src/jdk.internal.vm.ci/share/classes/jdk.vm.ci.loongarch64/src/jdk/vm/ci/loongarch64/package-info.java +new file mode 100644 +index 0000000000..9d020833ea +--- /dev/null ++++ b/src/jdk.internal.vm.ci/share/classes/jdk.vm.ci.loongarch64/src/jdk/vm/ci/loongarch64/package-info.java @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2018, 2022, Oracle and/or its affiliates. All rights reserved. @@ -115064,9 +115573,10 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/j + * The LoongArch64 platform independent portions of the JVMCI API. + */ +package jdk.vm.ci.loongarch64; -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/jdk.internal.vm.ci/share/classes/module-info.java b/src/jdk.internal.vm.ci/share/classes/module-info.java ---- a/src/jdk.internal.vm.ci/share/classes/module-info.java 2024-01-10 05:19:49.000000000 +0800 -+++ b/src/jdk.internal.vm.ci/share/classes/module-info.java 2024-01-30 10:00:13.314747494 +0800 +diff --git a/src/jdk.internal.vm.ci/share/classes/module-info.java b/src/jdk.internal.vm.ci/share/classes/module-info.java +index fed310d386..661f106d30 100644 +--- a/src/jdk.internal.vm.ci/share/classes/module-info.java ++++ b/src/jdk.internal.vm.ci/share/classes/module-info.java @@ -23,6 +23,12 @@ * questions. */ @@ -115080,7 +115590,7 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/j module jdk.internal.vm.ci { exports jdk.vm.ci.services to jdk.internal.vm.compiler; exports jdk.vm.ci.runtime to -@@ -37,6 +43,7 @@ +@@ -37,6 +43,7 @@ module jdk.internal.vm.ci { provides jdk.vm.ci.hotspot.HotSpotJVMCIBackendFactory with jdk.vm.ci.hotspot.aarch64.AArch64HotSpotJVMCIBackendFactory, @@ -115088,10 +115598,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/j jdk.vm.ci.hotspot.amd64.AMD64HotSpotJVMCIBackendFactory, jdk.vm.ci.hotspot.sparc.SPARCHotSpotJVMCIBackendFactory; } -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/utils/hsdis/Makefile b/src/utils/hsdis/Makefile ---- a/src/utils/hsdis/Makefile 2024-01-10 05:19:49.000000000 +0800 -+++ b/src/utils/hsdis/Makefile 2024-01-30 10:00:13.851407763 +0800 -@@ -94,6 +94,9 @@ +diff --git a/src/utils/hsdis/Makefile b/src/utils/hsdis/Makefile +index 2514a895da..08fbe3b953 100644 +--- a/src/utils/hsdis/Makefile ++++ b/src/utils/hsdis/Makefile +@@ -94,6 +94,9 @@ CC = gcc endif CFLAGS += -O DLDFLAGS += -shared @@ -115101,19 +115612,21 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/u LDFLAGS += -ldl OUTFLAGS += -o $@ else -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/test/hotspot/jtreg/compiler/cpuflags/TestAESIntrinsicsOnSupportedConfig.java b/test/hotspot/jtreg/compiler/cpuflags/TestAESIntrinsicsOnSupportedConfig.java ---- a/test/hotspot/jtreg/compiler/cpuflags/TestAESIntrinsicsOnSupportedConfig.java 2024-01-10 05:19:49.000000000 +0800 -+++ b/test/hotspot/jtreg/compiler/cpuflags/TestAESIntrinsicsOnSupportedConfig.java 2024-01-30 10:00:13.961406452 +0800 -@@ -22,11 +22,17 @@ +diff --git a/test/hotspot/jtreg/compiler/cpuflags/TestAESIntrinsicsOnSupportedConfig.java b/test/hotspot/jtreg/compiler/cpuflags/TestAESIntrinsicsOnSupportedConfig.java +index ac17e567b0..9b004a2033 100644 +--- a/test/hotspot/jtreg/compiler/cpuflags/TestAESIntrinsicsOnSupportedConfig.java ++++ b/test/hotspot/jtreg/compiler/cpuflags/TestAESIntrinsicsOnSupportedConfig.java +@@ -21,12 +21,18 @@ + * questions. */ - /* ++/* + * This file has been modified by Loongson Technology in 2021, These + * modifications are Copyright (c) 2021, Loongson Technology, and are made + * available on the same license terms set forth above. + */ + -+/* + /* * @test * @library /test/lib / * @modules java.base/jdk.internal.misc @@ -115123,22 +115636,24 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/test/ * @build sun.hotspot.WhiteBox * @run driver ClassFileInstaller sun.hotspot.WhiteBox * sun.hotspot.WhiteBox$WhiteBoxPermission -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/test/hotspot/jtreg/compiler/cpuflags/TestAESIntrinsicsOnUnsupportedConfig.java b/test/hotspot/jtreg/compiler/cpuflags/TestAESIntrinsicsOnUnsupportedConfig.java ---- a/test/hotspot/jtreg/compiler/cpuflags/TestAESIntrinsicsOnUnsupportedConfig.java 2024-01-10 05:19:49.000000000 +0800 -+++ b/test/hotspot/jtreg/compiler/cpuflags/TestAESIntrinsicsOnUnsupportedConfig.java 2024-01-30 10:00:13.961406452 +0800 -@@ -22,13 +22,19 @@ +diff --git a/test/hotspot/jtreg/compiler/cpuflags/TestAESIntrinsicsOnUnsupportedConfig.java b/test/hotspot/jtreg/compiler/cpuflags/TestAESIntrinsicsOnUnsupportedConfig.java +index 60b2d03321..981a239979 100644 +--- a/test/hotspot/jtreg/compiler/cpuflags/TestAESIntrinsicsOnUnsupportedConfig.java ++++ b/test/hotspot/jtreg/compiler/cpuflags/TestAESIntrinsicsOnUnsupportedConfig.java +@@ -21,6 +21,12 @@ + * questions. */ - /* ++/* + * This file has been modified by Loongson Technology in 2021, These + * modifications are Copyright (c) 2021, Loongson Technology, and are made + * available on the same license terms set forth above. + */ + -+/* + /* * @test * @library /test/lib / - * @modules java.base/jdk.internal.misc +@@ -28,7 +34,7 @@ * java.management * * @build sun.hotspot.WhiteBox @@ -115147,9 +115662,10 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/test/ * @requires vm.compiler1.enabled | !vm.graal.enabled * @run driver ClassFileInstaller sun.hotspot.WhiteBox * sun.hotspot.WhiteBox$WhiteBoxPermission -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/test/hotspot/jtreg/compiler/intrinsics/sha/cli/testcases/GenericTestCaseForOtherCPU.java b/test/hotspot/jtreg/compiler/intrinsics/sha/cli/testcases/GenericTestCaseForOtherCPU.java ---- a/test/hotspot/jtreg/compiler/intrinsics/sha/cli/testcases/GenericTestCaseForOtherCPU.java 2024-01-10 05:19:49.000000000 +0800 -+++ b/test/hotspot/jtreg/compiler/intrinsics/sha/cli/testcases/GenericTestCaseForOtherCPU.java 2024-01-30 10:00:13.974739627 +0800 +diff --git a/test/hotspot/jtreg/compiler/intrinsics/sha/cli/testcases/GenericTestCaseForOtherCPU.java b/test/hotspot/jtreg/compiler/intrinsics/sha/cli/testcases/GenericTestCaseForOtherCPU.java +index faa9fdbae6..a635f03d24 100644 +--- a/test/hotspot/jtreg/compiler/intrinsics/sha/cli/testcases/GenericTestCaseForOtherCPU.java ++++ b/test/hotspot/jtreg/compiler/intrinsics/sha/cli/testcases/GenericTestCaseForOtherCPU.java @@ -21,6 +21,12 @@ * questions. */ @@ -115163,7 +115679,7 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/test/ package compiler.intrinsics.sha.cli.testcases; import compiler.intrinsics.sha.cli.SHAOptionsBase; -@@ -32,19 +38,20 @@ +@@ -32,19 +38,20 @@ import jdk.test.lib.cli.predicate.OrPredicate; /** * Generic test case for SHA-related options targeted to any CPU except @@ -115187,10 +115703,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/test/ } @Override -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/test/hotspot/jtreg/compiler/jvmci/jdk.vm.ci.code.test/src/jdk/vm/ci/code/test/CodeInstallationTest.java b/test/hotspot/jtreg/compiler/jvmci/jdk.vm.ci.code.test/src/jdk/vm/ci/code/test/CodeInstallationTest.java ---- a/test/hotspot/jtreg/compiler/jvmci/jdk.vm.ci.code.test/src/jdk/vm/ci/code/test/CodeInstallationTest.java 2024-01-10 05:19:49.000000000 +0800 -+++ b/test/hotspot/jtreg/compiler/jvmci/jdk.vm.ci.code.test/src/jdk/vm/ci/code/test/CodeInstallationTest.java 2024-01-30 10:00:13.984739508 +0800 -@@ -29,6 +29,7 @@ +diff --git a/test/hotspot/jtreg/compiler/jvmci/jdk.vm.ci.code.test/src/jdk/vm/ci/code/test/CodeInstallationTest.java b/test/hotspot/jtreg/compiler/jvmci/jdk.vm.ci.code.test/src/jdk/vm/ci/code/test/CodeInstallationTest.java +index 62d0e99155..c3fa3fb93e 100644 +--- a/test/hotspot/jtreg/compiler/jvmci/jdk.vm.ci.code.test/src/jdk/vm/ci/code/test/CodeInstallationTest.java ++++ b/test/hotspot/jtreg/compiler/jvmci/jdk.vm.ci.code.test/src/jdk/vm/ci/code/test/CodeInstallationTest.java +@@ -29,6 +29,7 @@ import jdk.vm.ci.code.InstalledCode; import jdk.vm.ci.code.TargetDescription; import jdk.vm.ci.code.test.amd64.AMD64TestAssembler; import jdk.vm.ci.code.test.sparc.SPARCTestAssembler; @@ -115198,7 +115715,7 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/test/ import jdk.vm.ci.hotspot.HotSpotCompiledCode; import jdk.vm.ci.hotspot.HotSpotJVMCIRuntime; import jdk.vm.ci.hotspot.HotSpotResolvedJavaMethod; -@@ -37,6 +38,7 @@ +@@ -37,6 +38,7 @@ import jdk.vm.ci.meta.MetaAccessProvider; import jdk.vm.ci.runtime.JVMCI; import jdk.vm.ci.runtime.JVMCIBackend; import jdk.vm.ci.sparc.SPARC; @@ -115206,7 +115723,7 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/test/ import org.junit.Assert; import java.lang.reflect.Method; -@@ -72,6 +74,8 @@ +@@ -72,6 +74,8 @@ public class CodeInstallationTest { return new AMD64TestAssembler(codeCache, config); } else if (arch instanceof SPARC) { return new SPARCTestAssembler(codeCache, config); @@ -115215,9 +115732,10 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/test/ } else { Assert.fail("unsupported architecture"); return null; -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/test/hotspot/jtreg/compiler/jvmci/jdk.vm.ci.code.test/src/jdk/vm/ci/code/test/DataPatchTest.java b/test/hotspot/jtreg/compiler/jvmci/jdk.vm.ci.code.test/src/jdk/vm/ci/code/test/DataPatchTest.java ---- a/test/hotspot/jtreg/compiler/jvmci/jdk.vm.ci.code.test/src/jdk/vm/ci/code/test/DataPatchTest.java 2024-01-10 05:19:49.000000000 +0800 -+++ b/test/hotspot/jtreg/compiler/jvmci/jdk.vm.ci.code.test/src/jdk/vm/ci/code/test/DataPatchTest.java 2024-01-30 10:00:13.984739508 +0800 +diff --git a/test/hotspot/jtreg/compiler/jvmci/jdk.vm.ci.code.test/src/jdk/vm/ci/code/test/DataPatchTest.java b/test/hotspot/jtreg/compiler/jvmci/jdk.vm.ci.code.test/src/jdk/vm/ci/code/test/DataPatchTest.java +index 8afc7d7b98..520d7707a2 100644 +--- a/test/hotspot/jtreg/compiler/jvmci/jdk.vm.ci.code.test/src/jdk/vm/ci/code/test/DataPatchTest.java ++++ b/test/hotspot/jtreg/compiler/jvmci/jdk.vm.ci.code.test/src/jdk/vm/ci/code/test/DataPatchTest.java @@ -23,7 +23,7 @@ /** @@ -115237,9 +115755,10 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/test/ * @run junit/othervm -XX:+UnlockExperimentalVMOptions -XX:+EnableJVMCI -Djvmci.Compiler=null jdk.vm.ci.code.test.DataPatchTest */ -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/test/hotspot/jtreg/compiler/jvmci/jdk.vm.ci.code.test/src/jdk/vm/ci/code/test/InterpreterFrameSizeTest.java b/test/hotspot/jtreg/compiler/jvmci/jdk.vm.ci.code.test/src/jdk/vm/ci/code/test/InterpreterFrameSizeTest.java ---- a/test/hotspot/jtreg/compiler/jvmci/jdk.vm.ci.code.test/src/jdk/vm/ci/code/test/InterpreterFrameSizeTest.java 2024-01-10 05:19:49.000000000 +0800 -+++ b/test/hotspot/jtreg/compiler/jvmci/jdk.vm.ci.code.test/src/jdk/vm/ci/code/test/InterpreterFrameSizeTest.java 2024-01-30 10:00:13.984739508 +0800 +diff --git a/test/hotspot/jtreg/compiler/jvmci/jdk.vm.ci.code.test/src/jdk/vm/ci/code/test/InterpreterFrameSizeTest.java b/test/hotspot/jtreg/compiler/jvmci/jdk.vm.ci.code.test/src/jdk/vm/ci/code/test/InterpreterFrameSizeTest.java +index 75d0748da5..a6826e2ffe 100644 +--- a/test/hotspot/jtreg/compiler/jvmci/jdk.vm.ci.code.test/src/jdk/vm/ci/code/test/InterpreterFrameSizeTest.java ++++ b/test/hotspot/jtreg/compiler/jvmci/jdk.vm.ci.code.test/src/jdk/vm/ci/code/test/InterpreterFrameSizeTest.java @@ -23,7 +23,7 @@ /** @@ -115259,9 +115778,126 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/test/ * @run junit/othervm -XX:+UnlockExperimentalVMOptions -XX:+EnableJVMCI -Djvmci.Compiler=null jdk.vm.ci.code.test.InterpreterFrameSizeTest */ -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/test/hotspot/jtreg/compiler/jvmci/jdk.vm.ci.code.test/src/jdk/vm/ci/code/test/loongarch64/LoongArch64TestAssembler.java b/test/hotspot/jtreg/compiler/jvmci/jdk.vm.ci.code.test/src/jdk/vm/ci/code/test/loongarch64/LoongArch64TestAssembler.java ---- a/test/hotspot/jtreg/compiler/jvmci/jdk.vm.ci.code.test/src/jdk/vm/ci/code/test/loongarch64/LoongArch64TestAssembler.java 1970-01-01 08:00:00.000000000 +0800 -+++ b/test/hotspot/jtreg/compiler/jvmci/jdk.vm.ci.code.test/src/jdk/vm/ci/code/test/loongarch64/LoongArch64TestAssembler.java 2024-01-30 10:00:13.984739508 +0800 +diff --git a/test/hotspot/jtreg/compiler/jvmci/jdk.vm.ci.code.test/src/jdk/vm/ci/code/test/MaxOopMapStackOffsetTest.java b/test/hotspot/jtreg/compiler/jvmci/jdk.vm.ci.code.test/src/jdk/vm/ci/code/test/MaxOopMapStackOffsetTest.java +index a67fa2c1df..59cce6454d 100644 +--- a/test/hotspot/jtreg/compiler/jvmci/jdk.vm.ci.code.test/src/jdk/vm/ci/code/test/MaxOopMapStackOffsetTest.java ++++ b/test/hotspot/jtreg/compiler/jvmci/jdk.vm.ci.code.test/src/jdk/vm/ci/code/test/MaxOopMapStackOffsetTest.java +@@ -23,7 +23,7 @@ + + /** + * @test +- * @requires vm.jvmci & (vm.simpleArch == "x64" | vm.simpleArch == "sparcv9") ++ * @requires vm.jvmci & (vm.simpleArch == "x64" | vm.simpleArch == "sparcv9" | vm.simpleArch == "loongarch64") + * @library / + * @modules jdk.internal.vm.ci/jdk.vm.ci.hotspot + * jdk.internal.vm.ci/jdk.vm.ci.meta +@@ -33,7 +33,8 @@ + * jdk.internal.vm.ci/jdk.vm.ci.runtime + * jdk.internal.vm.ci/jdk.vm.ci.amd64 + * jdk.internal.vm.ci/jdk.vm.ci.sparc +- * @compile CodeInstallationTest.java DebugInfoTest.java TestAssembler.java TestHotSpotVMConfig.java amd64/AMD64TestAssembler.java sparc/SPARCTestAssembler.java ++ * jdk.internal.vm.ci/jdk.vm.ci.loongarch64 ++ * @compile CodeInstallationTest.java DebugInfoTest.java TestAssembler.java TestHotSpotVMConfig.java amd64/AMD64TestAssembler.java sparc/SPARCTestAssembler.java loongarch64/LoongArch64TestAssembler.java + * @run junit/othervm -XX:+UnlockExperimentalVMOptions -XX:+EnableJVMCI -Djvmci.Compiler=null jdk.vm.ci.code.test.MaxOopMapStackOffsetTest + */ + +diff --git a/test/hotspot/jtreg/compiler/jvmci/jdk.vm.ci.code.test/src/jdk/vm/ci/code/test/NativeCallTest.java b/test/hotspot/jtreg/compiler/jvmci/jdk.vm.ci.code.test/src/jdk/vm/ci/code/test/NativeCallTest.java +index d9e1f24c30..259218b305 100644 +--- a/test/hotspot/jtreg/compiler/jvmci/jdk.vm.ci.code.test/src/jdk/vm/ci/code/test/NativeCallTest.java ++++ b/test/hotspot/jtreg/compiler/jvmci/jdk.vm.ci.code.test/src/jdk/vm/ci/code/test/NativeCallTest.java +@@ -23,7 +23,7 @@ + + /** + * @test +- * @requires vm.jvmci & (vm.simpleArch == "x64" | vm.simpleArch == "sparcv9") ++ * @requires vm.jvmci & (vm.simpleArch == "x64" | vm.simpleArch == "sparcv9" | vm.simpleArch == "loongarch64") + * @library /test/lib / + * @modules jdk.internal.vm.ci/jdk.vm.ci.hotspot + * jdk.internal.vm.ci/jdk.vm.ci.code +@@ -33,7 +33,8 @@ + * jdk.internal.vm.ci/jdk.vm.ci.common + * jdk.internal.vm.ci/jdk.vm.ci.amd64 + * jdk.internal.vm.ci/jdk.vm.ci.sparc +- * @compile CodeInstallationTest.java TestHotSpotVMConfig.java NativeCallTest.java TestAssembler.java sparc/SPARCTestAssembler.java amd64/AMD64TestAssembler.java ++ * jdk.internal.vm.ci/jdk.vm.ci.loongarch64 ++ * @compile CodeInstallationTest.java TestHotSpotVMConfig.java NativeCallTest.java TestAssembler.java sparc/SPARCTestAssembler.java amd64/AMD64TestAssembler.java loongarch64/LoongArch64TestAssembler.java + * @run junit/othervm/native -XX:+UnlockExperimentalVMOptions -XX:+EnableJVMCI -Xbootclasspath/a:. jdk.vm.ci.code.test.NativeCallTest + */ + package jdk.vm.ci.code.test; +diff --git a/test/hotspot/jtreg/compiler/jvmci/jdk.vm.ci.code.test/src/jdk/vm/ci/code/test/SimpleCodeInstallationTest.java b/test/hotspot/jtreg/compiler/jvmci/jdk.vm.ci.code.test/src/jdk/vm/ci/code/test/SimpleCodeInstallationTest.java +index 9b92114055..00d0f53cdb 100644 +--- a/test/hotspot/jtreg/compiler/jvmci/jdk.vm.ci.code.test/src/jdk/vm/ci/code/test/SimpleCodeInstallationTest.java ++++ b/test/hotspot/jtreg/compiler/jvmci/jdk.vm.ci.code.test/src/jdk/vm/ci/code/test/SimpleCodeInstallationTest.java +@@ -23,7 +23,7 @@ + + /** + * @test +- * @requires vm.jvmci & (vm.simpleArch == "x64" | vm.simpleArch == "sparcv9") ++ * @requires vm.jvmci & (vm.simpleArch == "x64" | vm.simpleArch == "sparcv9" | vm.simpleArch == "loongarch64") + * @library / + * @modules jdk.internal.vm.ci/jdk.vm.ci.hotspot + * jdk.internal.vm.ci/jdk.vm.ci.meta +@@ -32,7 +32,8 @@ + * jdk.internal.vm.ci/jdk.vm.ci.runtime + * jdk.internal.vm.ci/jdk.vm.ci.amd64 + * jdk.internal.vm.ci/jdk.vm.ci.sparc +- * @compile CodeInstallationTest.java DebugInfoTest.java TestAssembler.java TestHotSpotVMConfig.java amd64/AMD64TestAssembler.java sparc/SPARCTestAssembler.java ++ * jdk.internal.vm.ci/jdk.vm.ci.loongarch64 ++ * @compile CodeInstallationTest.java DebugInfoTest.java TestAssembler.java TestHotSpotVMConfig.java amd64/AMD64TestAssembler.java sparc/SPARCTestAssembler.java loongarch64/LoongArch64TestAssembler.java + * @run junit/othervm -XX:+UnlockExperimentalVMOptions -XX:+EnableJVMCI -Djvmci.Compiler=null jdk.vm.ci.code.test.SimpleCodeInstallationTest + */ + +diff --git a/test/hotspot/jtreg/compiler/jvmci/jdk.vm.ci.code.test/src/jdk/vm/ci/code/test/SimpleDebugInfoTest.java b/test/hotspot/jtreg/compiler/jvmci/jdk.vm.ci.code.test/src/jdk/vm/ci/code/test/SimpleDebugInfoTest.java +index 5b2204868c..ecfcb1cf01 100644 +--- a/test/hotspot/jtreg/compiler/jvmci/jdk.vm.ci.code.test/src/jdk/vm/ci/code/test/SimpleDebugInfoTest.java ++++ b/test/hotspot/jtreg/compiler/jvmci/jdk.vm.ci.code.test/src/jdk/vm/ci/code/test/SimpleDebugInfoTest.java +@@ -23,7 +23,7 @@ + + /** + * @test +- * @requires vm.jvmci & (vm.simpleArch == "x64" | vm.simpleArch == "sparcv9") ++ * @requires vm.jvmci & (vm.simpleArch == "x64" | vm.simpleArch == "sparcv9" | vm.simpleArch == "loongarch64") + * @library / + * @modules jdk.internal.vm.ci/jdk.vm.ci.hotspot + * jdk.internal.vm.ci/jdk.vm.ci.meta +@@ -32,7 +32,8 @@ + * jdk.internal.vm.ci/jdk.vm.ci.runtime + * jdk.internal.vm.ci/jdk.vm.ci.amd64 + * jdk.internal.vm.ci/jdk.vm.ci.sparc +- * @compile CodeInstallationTest.java DebugInfoTest.java TestAssembler.java TestHotSpotVMConfig.java amd64/AMD64TestAssembler.java sparc/SPARCTestAssembler.java ++ * jdk.internal.vm.ci/jdk.vm.ci.loongarch64 ++ * @compile CodeInstallationTest.java DebugInfoTest.java TestAssembler.java TestHotSpotVMConfig.java amd64/AMD64TestAssembler.java sparc/SPARCTestAssembler.java loongarch64/LoongArch64TestAssembler.java + * @run junit/othervm -XX:+UnlockExperimentalVMOptions -XX:+EnableJVMCI -Djvmci.Compiler=null jdk.vm.ci.code.test.SimpleDebugInfoTest + */ + +diff --git a/test/hotspot/jtreg/compiler/jvmci/jdk.vm.ci.code.test/src/jdk/vm/ci/code/test/VirtualObjectDebugInfoTest.java b/test/hotspot/jtreg/compiler/jvmci/jdk.vm.ci.code.test/src/jdk/vm/ci/code/test/VirtualObjectDebugInfoTest.java +index a10e90acda..5b1a58c74b 100644 +--- a/test/hotspot/jtreg/compiler/jvmci/jdk.vm.ci.code.test/src/jdk/vm/ci/code/test/VirtualObjectDebugInfoTest.java ++++ b/test/hotspot/jtreg/compiler/jvmci/jdk.vm.ci.code.test/src/jdk/vm/ci/code/test/VirtualObjectDebugInfoTest.java +@@ -23,7 +23,7 @@ + + /** + * @test +- * @requires vm.jvmci & (vm.simpleArch == "x64" | vm.simpleArch == "sparcv9") ++ * @requires vm.jvmci & (vm.simpleArch == "x64" | vm.simpleArch == "sparcv9" | vm.simpleArch == "loongarch64") + * @library / + * @modules jdk.internal.vm.ci/jdk.vm.ci.hotspot + * jdk.internal.vm.ci/jdk.vm.ci.meta +@@ -32,7 +32,8 @@ + * jdk.internal.vm.ci/jdk.vm.ci.runtime + * jdk.internal.vm.ci/jdk.vm.ci.amd64 + * jdk.internal.vm.ci/jdk.vm.ci.sparc +- * @compile CodeInstallationTest.java DebugInfoTest.java TestAssembler.java TestHotSpotVMConfig.java amd64/AMD64TestAssembler.java sparc/SPARCTestAssembler.java ++ * jdk.internal.vm.ci/jdk.vm.ci.loongarch64 ++ * @compile CodeInstallationTest.java DebugInfoTest.java TestAssembler.java TestHotSpotVMConfig.java amd64/AMD64TestAssembler.java sparc/SPARCTestAssembler.java loongarch64/LoongArch64TestAssembler.java + * @run junit/othervm -XX:+UnlockExperimentalVMOptions -XX:+EnableJVMCI -Djvmci.Compiler=null jdk.vm.ci.code.test.VirtualObjectDebugInfoTest + */ + +diff --git a/test/hotspot/jtreg/compiler/jvmci/jdk.vm.ci.code.test/src/jdk/vm/ci/code/test/loongarch64/LoongArch64TestAssembler.java b/test/hotspot/jtreg/compiler/jvmci/jdk.vm.ci.code.test/src/jdk/vm/ci/code/test/loongarch64/LoongArch64TestAssembler.java +new file mode 100644 +index 0000000000..4c76868453 +--- /dev/null ++++ b/test/hotspot/jtreg/compiler/jvmci/jdk.vm.ci.code.test/src/jdk/vm/ci/code/test/loongarch64/LoongArch64TestAssembler.java @@ -0,0 +1,568 @@ +/* + * Copyright (c) 2020, 2022, Oracle and/or its affiliates. All rights reserved. @@ -115831,119 +116467,10 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/test/ + } + +} -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/test/hotspot/jtreg/compiler/jvmci/jdk.vm.ci.code.test/src/jdk/vm/ci/code/test/MaxOopMapStackOffsetTest.java b/test/hotspot/jtreg/compiler/jvmci/jdk.vm.ci.code.test/src/jdk/vm/ci/code/test/MaxOopMapStackOffsetTest.java ---- a/test/hotspot/jtreg/compiler/jvmci/jdk.vm.ci.code.test/src/jdk/vm/ci/code/test/MaxOopMapStackOffsetTest.java 2024-01-10 05:19:49.000000000 +0800 -+++ b/test/hotspot/jtreg/compiler/jvmci/jdk.vm.ci.code.test/src/jdk/vm/ci/code/test/MaxOopMapStackOffsetTest.java 2024-01-30 10:00:13.984739508 +0800 -@@ -23,7 +23,7 @@ - - /** - * @test -- * @requires vm.jvmci & (vm.simpleArch == "x64" | vm.simpleArch == "sparcv9") -+ * @requires vm.jvmci & (vm.simpleArch == "x64" | vm.simpleArch == "sparcv9" | vm.simpleArch == "loongarch64") - * @library / - * @modules jdk.internal.vm.ci/jdk.vm.ci.hotspot - * jdk.internal.vm.ci/jdk.vm.ci.meta -@@ -33,7 +33,8 @@ - * jdk.internal.vm.ci/jdk.vm.ci.runtime - * jdk.internal.vm.ci/jdk.vm.ci.amd64 - * jdk.internal.vm.ci/jdk.vm.ci.sparc -- * @compile CodeInstallationTest.java DebugInfoTest.java TestAssembler.java TestHotSpotVMConfig.java amd64/AMD64TestAssembler.java sparc/SPARCTestAssembler.java -+ * jdk.internal.vm.ci/jdk.vm.ci.loongarch64 -+ * @compile CodeInstallationTest.java DebugInfoTest.java TestAssembler.java TestHotSpotVMConfig.java amd64/AMD64TestAssembler.java sparc/SPARCTestAssembler.java loongarch64/LoongArch64TestAssembler.java - * @run junit/othervm -XX:+UnlockExperimentalVMOptions -XX:+EnableJVMCI -Djvmci.Compiler=null jdk.vm.ci.code.test.MaxOopMapStackOffsetTest - */ - -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/test/hotspot/jtreg/compiler/jvmci/jdk.vm.ci.code.test/src/jdk/vm/ci/code/test/NativeCallTest.java b/test/hotspot/jtreg/compiler/jvmci/jdk.vm.ci.code.test/src/jdk/vm/ci/code/test/NativeCallTest.java ---- a/test/hotspot/jtreg/compiler/jvmci/jdk.vm.ci.code.test/src/jdk/vm/ci/code/test/NativeCallTest.java 2024-01-10 05:19:49.000000000 +0800 -+++ b/test/hotspot/jtreg/compiler/jvmci/jdk.vm.ci.code.test/src/jdk/vm/ci/code/test/NativeCallTest.java 2024-01-30 10:00:13.984739508 +0800 -@@ -23,7 +23,7 @@ - - /** - * @test -- * @requires vm.jvmci & (vm.simpleArch == "x64" | vm.simpleArch == "sparcv9") -+ * @requires vm.jvmci & (vm.simpleArch == "x64" | vm.simpleArch == "sparcv9" | vm.simpleArch == "loongarch64") - * @library /test/lib / - * @modules jdk.internal.vm.ci/jdk.vm.ci.hotspot - * jdk.internal.vm.ci/jdk.vm.ci.code -@@ -33,7 +33,8 @@ - * jdk.internal.vm.ci/jdk.vm.ci.common - * jdk.internal.vm.ci/jdk.vm.ci.amd64 - * jdk.internal.vm.ci/jdk.vm.ci.sparc -- * @compile CodeInstallationTest.java TestHotSpotVMConfig.java NativeCallTest.java TestAssembler.java sparc/SPARCTestAssembler.java amd64/AMD64TestAssembler.java -+ * jdk.internal.vm.ci/jdk.vm.ci.loongarch64 -+ * @compile CodeInstallationTest.java TestHotSpotVMConfig.java NativeCallTest.java TestAssembler.java sparc/SPARCTestAssembler.java amd64/AMD64TestAssembler.java loongarch64/LoongArch64TestAssembler.java - * @run junit/othervm/native -XX:+UnlockExperimentalVMOptions -XX:+EnableJVMCI -Xbootclasspath/a:. jdk.vm.ci.code.test.NativeCallTest - */ - package jdk.vm.ci.code.test; -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/test/hotspot/jtreg/compiler/jvmci/jdk.vm.ci.code.test/src/jdk/vm/ci/code/test/SimpleCodeInstallationTest.java b/test/hotspot/jtreg/compiler/jvmci/jdk.vm.ci.code.test/src/jdk/vm/ci/code/test/SimpleCodeInstallationTest.java ---- a/test/hotspot/jtreg/compiler/jvmci/jdk.vm.ci.code.test/src/jdk/vm/ci/code/test/SimpleCodeInstallationTest.java 2024-01-10 05:19:49.000000000 +0800 -+++ b/test/hotspot/jtreg/compiler/jvmci/jdk.vm.ci.code.test/src/jdk/vm/ci/code/test/SimpleCodeInstallationTest.java 2024-01-30 10:00:13.984739508 +0800 -@@ -23,7 +23,7 @@ - - /** - * @test -- * @requires vm.jvmci & (vm.simpleArch == "x64" | vm.simpleArch == "sparcv9") -+ * @requires vm.jvmci & (vm.simpleArch == "x64" | vm.simpleArch == "sparcv9" | vm.simpleArch == "loongarch64") - * @library / - * @modules jdk.internal.vm.ci/jdk.vm.ci.hotspot - * jdk.internal.vm.ci/jdk.vm.ci.meta -@@ -32,7 +32,8 @@ - * jdk.internal.vm.ci/jdk.vm.ci.runtime - * jdk.internal.vm.ci/jdk.vm.ci.amd64 - * jdk.internal.vm.ci/jdk.vm.ci.sparc -- * @compile CodeInstallationTest.java DebugInfoTest.java TestAssembler.java TestHotSpotVMConfig.java amd64/AMD64TestAssembler.java sparc/SPARCTestAssembler.java -+ * jdk.internal.vm.ci/jdk.vm.ci.loongarch64 -+ * @compile CodeInstallationTest.java DebugInfoTest.java TestAssembler.java TestHotSpotVMConfig.java amd64/AMD64TestAssembler.java sparc/SPARCTestAssembler.java loongarch64/LoongArch64TestAssembler.java - * @run junit/othervm -XX:+UnlockExperimentalVMOptions -XX:+EnableJVMCI -Djvmci.Compiler=null jdk.vm.ci.code.test.SimpleCodeInstallationTest - */ - -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/test/hotspot/jtreg/compiler/jvmci/jdk.vm.ci.code.test/src/jdk/vm/ci/code/test/SimpleDebugInfoTest.java b/test/hotspot/jtreg/compiler/jvmci/jdk.vm.ci.code.test/src/jdk/vm/ci/code/test/SimpleDebugInfoTest.java ---- a/test/hotspot/jtreg/compiler/jvmci/jdk.vm.ci.code.test/src/jdk/vm/ci/code/test/SimpleDebugInfoTest.java 2024-01-10 05:19:49.000000000 +0800 -+++ b/test/hotspot/jtreg/compiler/jvmci/jdk.vm.ci.code.test/src/jdk/vm/ci/code/test/SimpleDebugInfoTest.java 2024-01-30 10:00:13.984739508 +0800 -@@ -23,7 +23,7 @@ - - /** - * @test -- * @requires vm.jvmci & (vm.simpleArch == "x64" | vm.simpleArch == "sparcv9") -+ * @requires vm.jvmci & (vm.simpleArch == "x64" | vm.simpleArch == "sparcv9" | vm.simpleArch == "loongarch64") - * @library / - * @modules jdk.internal.vm.ci/jdk.vm.ci.hotspot - * jdk.internal.vm.ci/jdk.vm.ci.meta -@@ -32,7 +32,8 @@ - * jdk.internal.vm.ci/jdk.vm.ci.runtime - * jdk.internal.vm.ci/jdk.vm.ci.amd64 - * jdk.internal.vm.ci/jdk.vm.ci.sparc -- * @compile CodeInstallationTest.java DebugInfoTest.java TestAssembler.java TestHotSpotVMConfig.java amd64/AMD64TestAssembler.java sparc/SPARCTestAssembler.java -+ * jdk.internal.vm.ci/jdk.vm.ci.loongarch64 -+ * @compile CodeInstallationTest.java DebugInfoTest.java TestAssembler.java TestHotSpotVMConfig.java amd64/AMD64TestAssembler.java sparc/SPARCTestAssembler.java loongarch64/LoongArch64TestAssembler.java - * @run junit/othervm -XX:+UnlockExperimentalVMOptions -XX:+EnableJVMCI -Djvmci.Compiler=null jdk.vm.ci.code.test.SimpleDebugInfoTest - */ - -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/test/hotspot/jtreg/compiler/jvmci/jdk.vm.ci.code.test/src/jdk/vm/ci/code/test/VirtualObjectDebugInfoTest.java b/test/hotspot/jtreg/compiler/jvmci/jdk.vm.ci.code.test/src/jdk/vm/ci/code/test/VirtualObjectDebugInfoTest.java ---- a/test/hotspot/jtreg/compiler/jvmci/jdk.vm.ci.code.test/src/jdk/vm/ci/code/test/VirtualObjectDebugInfoTest.java 2024-01-10 05:19:49.000000000 +0800 -+++ b/test/hotspot/jtreg/compiler/jvmci/jdk.vm.ci.code.test/src/jdk/vm/ci/code/test/VirtualObjectDebugInfoTest.java 2024-01-30 10:00:13.984739508 +0800 -@@ -23,7 +23,7 @@ - - /** - * @test -- * @requires vm.jvmci & (vm.simpleArch == "x64" | vm.simpleArch == "sparcv9") -+ * @requires vm.jvmci & (vm.simpleArch == "x64" | vm.simpleArch == "sparcv9" | vm.simpleArch == "loongarch64") - * @library / - * @modules jdk.internal.vm.ci/jdk.vm.ci.hotspot - * jdk.internal.vm.ci/jdk.vm.ci.meta -@@ -32,7 +32,8 @@ - * jdk.internal.vm.ci/jdk.vm.ci.runtime - * jdk.internal.vm.ci/jdk.vm.ci.amd64 - * jdk.internal.vm.ci/jdk.vm.ci.sparc -- * @compile CodeInstallationTest.java DebugInfoTest.java TestAssembler.java TestHotSpotVMConfig.java amd64/AMD64TestAssembler.java sparc/SPARCTestAssembler.java -+ * jdk.internal.vm.ci/jdk.vm.ci.loongarch64 -+ * @compile CodeInstallationTest.java DebugInfoTest.java TestAssembler.java TestHotSpotVMConfig.java amd64/AMD64TestAssembler.java sparc/SPARCTestAssembler.java loongarch64/LoongArch64TestAssembler.java - * @run junit/othervm -XX:+UnlockExperimentalVMOptions -XX:+EnableJVMCI -Djvmci.Compiler=null jdk.vm.ci.code.test.VirtualObjectDebugInfoTest - */ - -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/test/hotspot/jtreg/compiler/runtime/criticalnatives/argumentcorruption/CheckLongArgs.java b/test/hotspot/jtreg/compiler/runtime/criticalnatives/argumentcorruption/CheckLongArgs.java ---- a/test/hotspot/jtreg/compiler/runtime/criticalnatives/argumentcorruption/CheckLongArgs.java 2024-01-10 05:19:49.000000000 +0800 -+++ b/test/hotspot/jtreg/compiler/runtime/criticalnatives/argumentcorruption/CheckLongArgs.java 2024-01-30 10:00:14.021405737 +0800 +diff --git a/test/hotspot/jtreg/compiler/runtime/criticalnatives/argumentcorruption/CheckLongArgs.java b/test/hotspot/jtreg/compiler/runtime/criticalnatives/argumentcorruption/CheckLongArgs.java +index acb86812d2..664ea11d0d 100644 +--- a/test/hotspot/jtreg/compiler/runtime/criticalnatives/argumentcorruption/CheckLongArgs.java ++++ b/test/hotspot/jtreg/compiler/runtime/criticalnatives/argumentcorruption/CheckLongArgs.java @@ -21,10 +21,17 @@ * questions. */ @@ -115962,9 +116489,10 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/test/ * @run main/othervm/native -Xcomp -XX:+CriticalJNINatives compiler.runtime.criticalnatives.argumentcorruption.CheckLongArgs */ package compiler.runtime.criticalnatives.argumentcorruption; -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/test/hotspot/jtreg/compiler/runtime/criticalnatives/lookup/LookUp.java b/test/hotspot/jtreg/compiler/runtime/criticalnatives/lookup/LookUp.java ---- a/test/hotspot/jtreg/compiler/runtime/criticalnatives/lookup/LookUp.java 2024-01-10 05:19:49.000000000 +0800 -+++ b/test/hotspot/jtreg/compiler/runtime/criticalnatives/lookup/LookUp.java 2024-01-30 10:00:14.021405737 +0800 +diff --git a/test/hotspot/jtreg/compiler/runtime/criticalnatives/lookup/LookUp.java b/test/hotspot/jtreg/compiler/runtime/criticalnatives/lookup/LookUp.java +index eab36f9311..ee5ab2f6dd 100644 +--- a/test/hotspot/jtreg/compiler/runtime/criticalnatives/lookup/LookUp.java ++++ b/test/hotspot/jtreg/compiler/runtime/criticalnatives/lookup/LookUp.java @@ -21,10 +21,17 @@ * questions. */ @@ -115983,9 +116511,10 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/test/ * @run main/othervm/native -Xcomp -XX:+CriticalJNINatives compiler.runtime.criticalnatives.lookup.LookUp */ package compiler.runtime.criticalnatives.lookup; -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/test/hotspot/jtreg/compiler/testlibrary/sha/predicate/IntrinsicPredicates.java b/test/hotspot/jtreg/compiler/testlibrary/sha/predicate/IntrinsicPredicates.java ---- a/test/hotspot/jtreg/compiler/testlibrary/sha/predicate/IntrinsicPredicates.java 2024-01-10 05:19:49.000000000 +0800 -+++ b/test/hotspot/jtreg/compiler/testlibrary/sha/predicate/IntrinsicPredicates.java 2024-01-30 10:00:14.024739030 +0800 +diff --git a/test/hotspot/jtreg/compiler/testlibrary/sha/predicate/IntrinsicPredicates.java b/test/hotspot/jtreg/compiler/testlibrary/sha/predicate/IntrinsicPredicates.java +index 7774dabcb5..c1cb6e00f3 100644 +--- a/test/hotspot/jtreg/compiler/testlibrary/sha/predicate/IntrinsicPredicates.java ++++ b/test/hotspot/jtreg/compiler/testlibrary/sha/predicate/IntrinsicPredicates.java @@ -21,6 +21,12 @@ * questions. */ @@ -115999,7 +116528,7 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/test/ package compiler.testlibrary.sha.predicate; import jdk.test.lib.Platform; -@@ -63,10 +69,12 @@ +@@ -63,10 +69,12 @@ public class IntrinsicPredicates { = new OrPredicate(new CPUSpecificPredicate("aarch64.*", new String[] { "sha1" }, null), new OrPredicate(new CPUSpecificPredicate("s390.*", new String[] { "sha1" }, null), new OrPredicate(new CPUSpecificPredicate("sparc.*", new String[] { "sha1" }, null), @@ -116013,7 +116542,7 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/test/ public static final BooleanSupplier SHA256_INSTRUCTION_AVAILABLE = new OrPredicate(new CPUSpecificPredicate("aarch64.*", new String[] { "sha256" }, null), -@@ -74,12 +82,14 @@ +@@ -74,12 +82,14 @@ public class IntrinsicPredicates { new OrPredicate(new CPUSpecificPredicate("sparc.*", new String[] { "sha256" }, null), new OrPredicate(new CPUSpecificPredicate("ppc64.*", new String[] { "sha" }, null), new OrPredicate(new CPUSpecificPredicate("ppc64le.*", new String[] { "sha" }, null), @@ -116029,23 +116558,24 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/test/ public static final BooleanSupplier SHA512_INSTRUCTION_AVAILABLE = new OrPredicate(new CPUSpecificPredicate("aarch64.*", new String[] { "sha512" }, null), -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/test/hotspot/jtreg/runtime/ReservedStack/ReservedStackTest.java b/test/hotspot/jtreg/runtime/ReservedStack/ReservedStackTest.java ---- a/test/hotspot/jtreg/runtime/ReservedStack/ReservedStackTest.java 2024-01-10 05:19:49.000000000 +0800 -+++ b/test/hotspot/jtreg/runtime/ReservedStack/ReservedStackTest.java 2024-01-30 10:00:14.074738434 +0800 -@@ -22,6 +22,12 @@ +diff --git a/test/hotspot/jtreg/runtime/ReservedStack/ReservedStackTest.java b/test/hotspot/jtreg/runtime/ReservedStack/ReservedStackTest.java +index 127bb6abcd..c9277604ae 100644 +--- a/test/hotspot/jtreg/runtime/ReservedStack/ReservedStackTest.java ++++ b/test/hotspot/jtreg/runtime/ReservedStack/ReservedStackTest.java +@@ -21,6 +21,12 @@ + * questions. */ - /* ++/* + * This file has been modified by Loongson Technology in 2021, These + * modifications are Copyright (c) 2021, Loongson Technology, and are made + * available on the same license terms set forth above. + */ + -+/* + /* * @test ReservedStackTest * - * @requires vm.opt.DeoptimizeALot != true -@@ -239,7 +245,7 @@ +@@ -239,7 +245,7 @@ public class ReservedStackTest { return Platform.isAix() || (Platform.isLinux() && (Platform.isPPC() || Platform.isS390x() || Platform.isX64() || @@ -116054,10 +116584,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/test/ Platform.isOSX() || Platform.isSolaris(); } -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/test/hotspot/jtreg/testlibrary_tests/TestMutuallyExclusivePlatformPredicates.java b/test/hotspot/jtreg/testlibrary_tests/TestMutuallyExclusivePlatformPredicates.java ---- a/test/hotspot/jtreg/testlibrary_tests/TestMutuallyExclusivePlatformPredicates.java 2024-01-10 05:19:49.000000000 +0800 -+++ b/test/hotspot/jtreg/testlibrary_tests/TestMutuallyExclusivePlatformPredicates.java 2024-01-30 10:00:14.158070775 +0800 -@@ -45,7 +45,7 @@ +diff --git a/test/hotspot/jtreg/testlibrary_tests/TestMutuallyExclusivePlatformPredicates.java b/test/hotspot/jtreg/testlibrary_tests/TestMutuallyExclusivePlatformPredicates.java +index 77458554b7..05aee6b84c 100644 +--- a/test/hotspot/jtreg/testlibrary_tests/TestMutuallyExclusivePlatformPredicates.java ++++ b/test/hotspot/jtreg/testlibrary_tests/TestMutuallyExclusivePlatformPredicates.java +@@ -45,7 +45,7 @@ import java.util.Set; */ public class TestMutuallyExclusivePlatformPredicates { private static enum MethodGroup { @@ -116066,9 +116597,10 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/test/ BITNESS("is32bit", "is64bit"), OS("isAix", "isLinux", "isOSX", "isSolaris", "isWindows"), VM_TYPE("isClient", "isServer", "isGraal", "isMinimal", "isZero", "isEmbedded"), -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/test/jdk/jdk/jfr/event/os/TestCPUInformation.java b/test/jdk/jdk/jfr/event/os/TestCPUInformation.java ---- a/test/jdk/jdk/jfr/event/os/TestCPUInformation.java 2024-01-10 05:19:49.000000000 +0800 -+++ b/test/jdk/jdk/jfr/event/os/TestCPUInformation.java 2024-01-30 10:00:15.451388695 +0800 +diff --git a/test/jdk/jdk/jfr/event/os/TestCPUInformation.java b/test/jdk/jdk/jfr/event/os/TestCPUInformation.java +index 7990c49a1f..025048c6b0 100644 +--- a/test/jdk/jdk/jfr/event/os/TestCPUInformation.java ++++ b/test/jdk/jdk/jfr/event/os/TestCPUInformation.java @@ -23,6 +23,12 @@ * questions. */ @@ -116082,7 +116614,7 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/test/ package jdk.jfr.event.os; import java.util.List; -@@ -54,8 +60,8 @@ +@@ -54,8 +60,8 @@ public class TestCPUInformation { Events.assertField(event, "hwThreads").atLeast(1); Events.assertField(event, "cores").atLeast(1); Events.assertField(event, "sockets").atLeast(1); @@ -116093,9 +116625,10 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/test/ } } } -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/test/jdk/sun/security/pkcs11/PKCS11Test.java b/test/jdk/sun/security/pkcs11/PKCS11Test.java ---- a/test/jdk/sun/security/pkcs11/PKCS11Test.java 2024-01-10 05:19:49.000000000 +0800 -+++ b/test/jdk/sun/security/pkcs11/PKCS11Test.java 2024-01-30 10:00:15.654719606 +0800 +diff --git a/test/jdk/sun/security/pkcs11/PKCS11Test.java b/test/jdk/sun/security/pkcs11/PKCS11Test.java +index b14daf6c6d..da33514c75 100644 +--- a/test/jdk/sun/security/pkcs11/PKCS11Test.java ++++ b/test/jdk/sun/security/pkcs11/PKCS11Test.java @@ -21,6 +21,12 @@ * questions. */ @@ -116109,7 +116642,7 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/test/ // common infrastructure for SunPKCS11 tests import java.io.BufferedReader; -@@ -747,6 +753,9 @@ +@@ -747,6 +753,9 @@ public abstract class PKCS11Test { "/usr/lib64/" }); osMap.put("Linux-ppc64-64", new String[] { "/usr/lib64/" }); osMap.put("Linux-ppc64le-64", new String[] { "/usr/lib64/" }); @@ -116119,9 +116652,10 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/test/ osMap.put("Linux-s390x-64", new String[] { "/usr/lib64/" }); osMap.put("Windows-x86-32", new String[] {}); osMap.put("Windows-amd64-64", new String[] {}); -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/test/lib/jdk/test/lib/Platform.java b/test/lib/jdk/test/lib/Platform.java ---- a/test/lib/jdk/test/lib/Platform.java 2024-01-10 05:19:49.000000000 +0800 -+++ b/test/lib/jdk/test/lib/Platform.java 2024-01-30 10:00:16.081381187 +0800 +diff --git a/test/lib/jdk/test/lib/Platform.java b/test/lib/jdk/test/lib/Platform.java +index 5b3f1889cb..aaf8867a7c 100644 +--- a/test/lib/jdk/test/lib/Platform.java ++++ b/test/lib/jdk/test/lib/Platform.java @@ -21,6 +21,12 @@ * questions. */ @@ -116135,7 +116669,7 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/test/ package jdk.test.lib; import java.io.FileNotFoundException; -@@ -226,6 +232,14 @@ +@@ -226,6 +232,14 @@ public class Platform { return isArch("(i386)|(x86(?!_64))"); } @@ -116150,9 +116684,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/test/ public static String getOsArch() { return osArch; } -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/test/micro/org/openjdk/bench/java/lang/RotateBenchmark.java b/test/micro/org/openjdk/bench/java/lang/RotateBenchmark.java ---- a/test/micro/org/openjdk/bench/java/lang/RotateBenchmark.java 1970-01-01 08:00:00.000000000 +0800 -+++ b/test/micro/org/openjdk/bench/java/lang/RotateBenchmark.java 2024-01-30 10:00:16.094714362 +0800 +diff --git a/test/micro/org/openjdk/bench/java/lang/RotateBenchmark.java b/test/micro/org/openjdk/bench/java/lang/RotateBenchmark.java +new file mode 100644 +index 0000000000..81fd956a4e +--- /dev/null ++++ b/test/micro/org/openjdk/bench/java/lang/RotateBenchmark.java @@ -0,0 +1,87 @@ +// +// Copyright (c) 2003, 2020, Oracle and/or its affiliates. All rights reserved. @@ -116241,9 +116777,11 @@ diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/test/ + } + +} -diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/test/micro/org/openjdk/bench/vm/compiler/MacroLogicOpt.java b/test/micro/org/openjdk/bench/vm/compiler/MacroLogicOpt.java ---- a/test/micro/org/openjdk/bench/vm/compiler/MacroLogicOpt.java 1970-01-01 08:00:00.000000000 +0800 -+++ b/test/micro/org/openjdk/bench/vm/compiler/MacroLogicOpt.java 2024-01-30 10:00:16.094714362 +0800 +diff --git a/test/micro/org/openjdk/bench/vm/compiler/MacroLogicOpt.java b/test/micro/org/openjdk/bench/vm/compiler/MacroLogicOpt.java +new file mode 100644 +index 0000000000..58400cadf6 +--- /dev/null ++++ b/test/micro/org/openjdk/bench/vm/compiler/MacroLogicOpt.java @@ -0,0 +1,125 @@ +/* + * Copyright (c) 2020, Oracle and/or its affiliates. All rights reserved. diff --git a/ZGC-Redesign-C2-load-barrier-to-expand-on-th.patch b/ZGC-AArch64-Optimizations-and-Fixes.patch similarity index 76% rename from ZGC-Redesign-C2-load-barrier-to-expand-on-th.patch rename to ZGC-AArch64-Optimizations-and-Fixes.patch index 58ed16d66c5739eb962ca2d04319a5ceef9cc576..0fa61a5978ddb46551c8d1fe7b0fe64cfb13d336 100644 --- a/ZGC-Redesign-C2-load-barrier-to-expand-on-th.patch +++ b/ZGC-AArch64-Optimizations-and-Fixes.patch @@ -1,16 +1,108 @@ +From 1932790364789c601d463a4de8f757cf604344c0 Mon Sep 17 00:00:00 2001 + +--- + make/hotspot/gensrc/GensrcAdlc.gmk | 6 + + src/hotspot/cpu/aarch64/aarch64.ad | 207 +- + .../gc/z/zBarrierSetAssembler_aarch64.cpp | 246 ++- + .../gc/z/zBarrierSetAssembler_aarch64.hpp | 26 +- + src/hotspot/cpu/aarch64/gc/z/z_aarch64.ad | 268 +++ + .../cpu/aarch64/macroAssembler_aarch64.cpp | 61 + + .../cpu/aarch64/macroAssembler_aarch64.hpp | 6 + + .../templateInterpreterGenerator_aarch64.cpp | 4 +- + .../cpu/aarch64/vm_version_aarch64.hpp | 8 + + .../cpu/x86/gc/z/zBarrierSetAssembler_x86.cpp | 404 +++- + .../cpu/x86/gc/z/zBarrierSetAssembler_x86.hpp | 30 +- + src/hotspot/cpu/x86/gc/z/z_x86_64.ad | 168 ++ + src/hotspot/cpu/x86/x86.ad | 136 +- + src/hotspot/cpu/x86/x86_64.ad | 437 +---- + .../gc/z/zBackingFile_linux_aarch64.cpp | 2 +- + src/hotspot/share/adlc/formssel.cpp | 8 - + src/hotspot/share/c1/c1_Instruction.cpp | 1 + + src/hotspot/share/ci/ciInstanceKlass.cpp | 44 + + src/hotspot/share/classfile/vmSymbols.hpp | 4 + + .../share/compiler/compilerDirectives.hpp | 3 +- + .../share/gc/shared/c2/barrierSetC2.cpp | 73 +- + .../share/gc/shared/c2/barrierSetC2.hpp | 15 +- + src/hotspot/share/gc/z/c2/zBarrierSetC2.cpp | 1657 +++-------------- + src/hotspot/share/gc/z/c2/zBarrierSetC2.hpp | 181 +- + .../share/gc/z/zBarrierSetAssembler.hpp | 5 +- + src/hotspot/share/gc/z/zGlobals.hpp | 7 +- + src/hotspot/share/gc/z/zHeap.cpp | 5 + + src/hotspot/share/gc/z/zLiveMap.cpp | 20 +- + src/hotspot/share/gc/z/zLiveMap.inline.hpp | 9 +- + src/hotspot/share/gc/z/zMarkStack.cpp | 74 +- + src/hotspot/share/gc/z/zMarkStack.hpp | 1 + + src/hotspot/share/gc/z/zWorkers.cpp | 23 +- + src/hotspot/share/gc/z/zWorkers.hpp | 2 - + src/hotspot/share/gc/z/z_globals.hpp | 6 +- + src/hotspot/share/opto/c2compiler.cpp | 1 + + src/hotspot/share/opto/classes.cpp | 3 - + src/hotspot/share/opto/classes.hpp | 11 - + src/hotspot/share/opto/compile.cpp | 52 +- + src/hotspot/share/opto/compile.hpp | 25 +- + src/hotspot/share/opto/escape.cpp | 15 - + src/hotspot/share/opto/graphKit.cpp | 10 +- + src/hotspot/share/opto/graphKit.hpp | 10 +- + src/hotspot/share/opto/lcm.cpp | 1 - + src/hotspot/share/opto/library_call.cpp | 17 + + src/hotspot/share/opto/loopnode.cpp | 1 - + src/hotspot/share/opto/loopopts.cpp | 3 - + src/hotspot/share/opto/machnode.hpp | 9 +- + src/hotspot/share/opto/matcher.cpp | 45 +- + src/hotspot/share/opto/memnode.cpp | 14 +- + src/hotspot/share/opto/memnode.hpp | 53 +- + src/hotspot/share/opto/node.cpp | 7 - + src/hotspot/share/opto/node.hpp | 6 - + src/hotspot/share/opto/output.cpp | 424 +++-- + src/hotspot/share/opto/output.hpp | 5 +- + src/hotspot/share/opto/parse1.cpp | 1 + + src/hotspot/share/opto/phaseX.cpp | 8 +- + src/hotspot/share/opto/vectornode.cpp | 1 - + src/hotspot/share/runtime/sharedRuntime.cpp | 2 + + src/hotspot/share/runtime/sharedRuntime.hpp | 5 + + src/hotspot/share/utilities/bitMap.hpp | 17 +- + src/hotspot/share/utilities/bitMap.inline.hpp | 34 +- + .../share/classes/java/util/Random.java | 2 + + .../runtime/MemberName/MemberNameLeak.java | 1 + + 63 files changed, 1941 insertions(+), 2989 deletions(-) + create mode 100644 src/hotspot/cpu/aarch64/gc/z/z_aarch64.ad + create mode 100644 src/hotspot/cpu/x86/gc/z/z_x86_64.ad + +diff --git a/make/hotspot/gensrc/GensrcAdlc.gmk b/make/hotspot/gensrc/GensrcAdlc.gmk +index c5a3ac572..2af2f9ac4 100644 +--- a/make/hotspot/gensrc/GensrcAdlc.gmk ++++ b/make/hotspot/gensrc/GensrcAdlc.gmk +@@ -150,6 +150,12 @@ ifeq ($(call check-jvm-feature, compiler2), true) + $d/os_cpu/$(HOTSPOT_TARGET_OS)_$(HOTSPOT_TARGET_CPU_ARCH)/$(HOTSPOT_TARGET_OS)_$(HOTSPOT_TARGET_CPU_ARCH).ad \ + ))) + ++ ifeq ($(call check-jvm-feature, zgc), true) ++ AD_SRC_FILES += $(call uniq, $(wildcard $(foreach d, $(AD_SRC_ROOTS), \ ++ $d/cpu/$(HOTSPOT_TARGET_CPU_ARCH)/gc/z/z_$(HOTSPOT_TARGET_CPU).ad \ ++ ))) ++ endif ++ + ifeq ($(call check-jvm-feature, shenandoahgc), true) + AD_SRC_FILES += $(call uniq, $(wildcard $(foreach d, $(AD_SRC_ROOTS), \ + $d/cpu/$(HOTSPOT_TARGET_CPU_ARCH)/gc/shenandoah/shenandoah_$(HOTSPOT_TARGET_CPU).ad \ diff --git a/src/hotspot/cpu/aarch64/aarch64.ad b/src/hotspot/cpu/aarch64/aarch64.ad -index af3e593a9..05b36e279 100644 +index a8976d5d4..b253e823a 100644 --- a/src/hotspot/cpu/aarch64/aarch64.ad +++ b/src/hotspot/cpu/aarch64/aarch64.ad -@@ -1131,6 +1131,7 @@ definitions %{ - source_hpp %{ - - #include "gc/z/c2/zBarrierSetC2.hpp" -+#include "gc/z/zThreadLocalData.hpp" - +@@ -1142,12 +1142,6 @@ definitions %{ + int_def VOLATILE_REF_COST ( 1000, 10 * INSN_COST); %} -@@ -2501,17 +2502,7 @@ void Compile::reshape_address(AddPNode* addp) { +-source_hpp %{ +- +-#include "gc/z/c2/zBarrierSetC2.hpp" +- +-%} +- + //----------SOURCE BLOCK------------------------------------------------------- + // This is a block of C++ code which provides values, functions, and + // definitions necessary in the rest of the architecture description +@@ -2525,17 +2519,7 @@ void Compile::reshape_address(AddPNode* addp) { __ INSN(REG, as_Register(BASE)); \ } @@ -28,10 +120,10 @@ index af3e593a9..05b36e279 100644 +static Address mem2address(int opcode, Register base, int index, int size, int disp) { Address::extend scale; - -@@ -2409,13 +2409,18 @@ typedef void (MacroAssembler::* mem_vector_insn)(FloatRegister Rt, + +@@ -2554,13 +2538,18 @@ typedef void (MacroAssembler::* mem_vector_insn)(FloatRegister Rt, } - + if (index == -1) { - (masm.*insn)(reg, Address(base, disp)); + return Address(base, disp); @@ -41,7 +133,7 @@ index af3e593a9..05b36e279 100644 + return Address(base, as_Register(index), scale); } } - + +typedef void (MacroAssembler::* mem_insn)(Register Rt, const Address &adr); +typedef void (MacroAssembler::* mem_insn2)(Register Rt, Register adr); +typedef void (MacroAssembler::* mem_float_insn)(FloatRegister Rt, const Address &adr); @@ -50,10 +142,10 @@ index af3e593a9..05b36e279 100644 static void loadStore(MacroAssembler masm, mem_insn insn, Register reg, int opcode, Register base, int index, int size, int disp, -@@ -2450,9 +2455,20 @@ typedef void (MacroAssembler::* mem_vector_insn)(FloatRegister Rt, +@@ -2595,9 +2584,20 @@ typedef void (MacroAssembler::* mem_vector_insn)(FloatRegister Rt, } } - + + // Used for all non-volatile memory accesses. The use of + // $mem->opcode() to discover whether this pattern uses sign-extended + // offsets is something of a kludge. @@ -72,10 +164,10 @@ index af3e593a9..05b36e279 100644 + Register base, int index, int size, int disp) { Address::extend scale; - -@@ -2474,8 +2490,8 @@ typedef void (MacroAssembler::* mem_vector_insn)(FloatRegister Rt, + +@@ -2619,8 +2619,8 @@ typedef void (MacroAssembler::* mem_vector_insn)(FloatRegister Rt, } - + static void loadStore(MacroAssembler masm, mem_vector_insn insn, - FloatRegister reg, MacroAssembler::SIMD_RegVariant T, - int opcode, Register base, int index, int size, int disp) @@ -84,7 +176,7 @@ index af3e593a9..05b36e279 100644 { if (index == -1) { (masm.*insn)(reg, T, Address(base, disp)); -@@ -3797,7 +3805,7 @@ frame %{ +@@ -3921,7 +3921,7 @@ frame %{ static const int hi[Op_RegL + 1] = { // enum name 0, // Op_Node 0, // Op_Set @@ -93,7 +185,7 @@ index af3e593a9..05b36e279 100644 OptoReg::Bad, // Op_RegI R0_H_num, // Op_RegP OptoReg::Bad, // Op_RegF -@@ -6929,7 +6937,7 @@ instruct loadRange(iRegINoSp dst, memory mem) +@@ -7075,7 +7075,7 @@ instruct loadRange(iRegINoSp dst, memory mem) instruct loadP(iRegPNoSp dst, memory mem) %{ match(Set dst (LoadP mem)); @@ -102,7 +194,7 @@ index af3e593a9..05b36e279 100644 ins_cost(4 * INSN_COST); format %{ "ldr $dst, $mem\t# ptr" %} -@@ -7622,6 +7630,7 @@ instruct loadL_volatile(iRegLNoSp dst, /* sync_memory*/indirect mem) +@@ -7768,6 +7768,7 @@ instruct loadL_volatile(iRegLNoSp dst, /* sync_memory*/indirect mem) instruct loadP_volatile(iRegPNoSp dst, /* sync_memory*/indirect mem) %{ match(Set dst (LoadP mem)); @@ -110,7 +202,7 @@ index af3e593a9..05b36e279 100644 ins_cost(VOLATILE_REF_COST); format %{ "ldar $dst, $mem\t# ptr" %} -@@ -8506,6 +8515,7 @@ instruct compareAndSwapL(iRegINoSp res, indirect mem, iRegLNoSp oldval, iRegLNoS +@@ -8652,6 +8653,7 @@ instruct compareAndSwapL(iRegINoSp res, indirect mem, iRegLNoSp oldval, iRegLNoS instruct compareAndSwapP(iRegINoSp res, indirect mem, iRegP oldval, iRegP newval, rFlagsReg cr) %{ match(Set res (CompareAndSwapP mem (Binary oldval newval))); @@ -118,7 +210,7 @@ index af3e593a9..05b36e279 100644 ins_cost(2 * VOLATILE_REF_COST); effect(KILL cr); -@@ -8619,7 +8629,7 @@ instruct compareAndSwapLAcq(iRegINoSp res, indirect mem, iRegLNoSp oldval, iRegL +@@ -8765,7 +8767,7 @@ instruct compareAndSwapLAcq(iRegINoSp res, indirect mem, iRegLNoSp oldval, iRegL instruct compareAndSwapPAcq(iRegINoSp res, indirect mem, iRegP oldval, iRegP newval, rFlagsReg cr) %{ @@ -127,7 +219,7 @@ index af3e593a9..05b36e279 100644 match(Set res (CompareAndSwapP mem (Binary oldval newval))); ins_cost(VOLATILE_REF_COST); -@@ -8750,6 +8760,7 @@ instruct compareAndExchangeN(iRegNNoSp res, indirect mem, iRegN oldval, iRegN ne +@@ -8896,6 +8898,7 @@ instruct compareAndExchangeN(iRegNNoSp res, indirect mem, iRegN oldval, iRegN ne %} instruct compareAndExchangeP(iRegPNoSp res, indirect mem, iRegP oldval, iRegP newval, rFlagsReg cr) %{ @@ -135,7 +227,7 @@ index af3e593a9..05b36e279 100644 match(Set res (CompareAndExchangeP mem (Binary oldval newval))); ins_cost(2 * VOLATILE_REF_COST); effect(TEMP_DEF res, KILL cr); -@@ -8849,7 +8860,7 @@ instruct compareAndExchangeNAcq(iRegNNoSp res, indirect mem, iRegN oldval, iRegN +@@ -8995,7 +8998,7 @@ instruct compareAndExchangeNAcq(iRegNNoSp res, indirect mem, iRegN oldval, iRegN %} instruct compareAndExchangePAcq(iRegPNoSp res, indirect mem, iRegP oldval, iRegP newval, rFlagsReg cr) %{ @@ -144,7 +236,7 @@ index af3e593a9..05b36e279 100644 match(Set res (CompareAndExchangeP mem (Binary oldval newval))); ins_cost(VOLATILE_REF_COST); effect(TEMP_DEF res, KILL cr); -@@ -8950,6 +8961,7 @@ instruct weakCompareAndSwapN(iRegINoSp res, indirect mem, iRegN oldval, iRegN ne +@@ -9096,6 +9099,7 @@ instruct weakCompareAndSwapN(iRegINoSp res, indirect mem, iRegN oldval, iRegN ne %} instruct weakCompareAndSwapP(iRegINoSp res, indirect mem, iRegP oldval, iRegP newval, rFlagsReg cr) %{ @@ -152,7 +244,7 @@ index af3e593a9..05b36e279 100644 match(Set res (WeakCompareAndSwapP mem (Binary oldval newval))); ins_cost(2 * VOLATILE_REF_COST); effect(KILL cr); -@@ -9057,8 +9069,8 @@ instruct weakCompareAndSwapNAcq(iRegINoSp res, indirect mem, iRegN oldval, iRegN +@@ -9203,8 +9207,8 @@ instruct weakCompareAndSwapNAcq(iRegINoSp res, indirect mem, iRegN oldval, iRegN %} instruct weakCompareAndSwapPAcq(iRegINoSp res, indirect mem, iRegP oldval, iRegP newval, rFlagsReg cr) %{ @@ -162,7 +254,7 @@ index af3e593a9..05b36e279 100644 ins_cost(VOLATILE_REF_COST); effect(KILL cr); format %{ -@@ -9108,6 +9120,7 @@ instruct get_and_setN(indirect mem, iRegN newv, iRegINoSp prev) %{ +@@ -9254,6 +9258,7 @@ instruct get_and_setN(indirect mem, iRegN newv, iRegINoSp prev) %{ %} instruct get_and_setP(indirect mem, iRegP newv, iRegPNoSp prev) %{ @@ -170,7 +262,7 @@ index af3e593a9..05b36e279 100644 match(Set prev (GetAndSetP mem newv)); ins_cost(2 * VOLATILE_REF_COST); format %{ "atomic_xchg $prev, $newv, [$mem]" %} -@@ -9151,7 +9164,7 @@ instruct get_and_setNAcq(indirect mem, iRegN newv, iRegINoSp prev) %{ +@@ -9297,7 +9302,7 @@ instruct get_and_setNAcq(indirect mem, iRegN newv, iRegINoSp prev) %{ %} instruct get_and_setPAcq(indirect mem, iRegP newv, iRegPNoSp prev) %{ @@ -179,30 +271,20 @@ index af3e593a9..05b36e279 100644 match(Set prev (GetAndSetP mem newv)); ins_cost(VOLATILE_REF_COST); format %{ "atomic_xchg_acq $prev, $newv, [$mem]" %} -@@ -17477,145 +17490,238 @@ instruct vsrl2L_imm(vecX dst, vecX src, immI shift) %{ - - source %{ +@@ -18518,150 +18523,6 @@ instruct vpopcount2I(vecD dst, vecD src) %{ + ins_pipe(pipe_class_default); + %} +-source %{ +- -#include "gc/z/zBarrierSetAssembler.hpp" -+static void z_load_barrier(MacroAssembler& _masm, const MachNode* node, Address ref_addr, Register ref, Register tmp, bool weak) { -+ ZLoadBarrierStubC2* const stub = ZLoadBarrierStubC2::create(node, ref_addr, ref, tmp, weak); -+ __ ldr(tmp, Address(rthread, ZThreadLocalData::address_bad_mask_offset())); -+ __ andr(tmp, tmp, ref); -+ __ cbnz(tmp, *stub->entry()); -+ __ bind(*stub->continuation()); -+} - +- -static void z_load_barrier_slow_reg(MacroAssembler& _masm, Register dst, - Register base, int index, int scale, - int disp, bool weak) { - const address stub = weak ? ZBarrierSet::assembler()->load_barrier_weak_slow_stub(dst) - : ZBarrierSet::assembler()->load_barrier_slow_stub(dst); -+static void z_load_barrier_slow_path(MacroAssembler& _masm, const MachNode* node, Address ref_addr, Register ref, Register tmp) { -+ ZLoadBarrierStubC2* const stub = ZLoadBarrierStubC2::create(node, ref_addr, ref, tmp, false /* weak */); -+ __ b(*stub->entry()); -+ __ bind(*stub->continuation()); -+} - +- - if (index == -1) { - if (disp != 0) { - __ lea(dst, Address(base, disp)); @@ -216,53 +298,14 @@ index af3e593a9..05b36e279 100644 - } else { - __ lea(dst, Address(base, disp)); - __ lea(dst, Address(dst, index_reg, Address::lsl(scale))); -+%} -+ -+// Load Pointer -+instruct zLoadP(iRegPNoSp dst, memory mem, rFlagsReg cr) -+%{ -+ match(Set dst (LoadP mem)); -+ predicate(UseZGC && !needs_acquiring_load(n) && (n->as_Load()->barrier_data() == ZLoadBarrierStrong)); -+ effect(TEMP dst, KILL cr); -+ -+ ins_cost(4 * INSN_COST); -+ -+ format %{ "ldr $dst, $mem" %} -+ -+ ins_encode %{ -+ const Address ref_addr = mem2address($mem->opcode(), as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp); -+ __ ldr($dst$$Register, ref_addr); -+ if (barrier_data() != ZLoadBarrierElided) { -+ z_load_barrier(_masm, this, ref_addr, $dst$$Register, rscratch2 /* tmp */, false /* weak */); - } +- } - } -+ %} - +- - __ far_call(RuntimeAddress(stub)); -} -+ ins_pipe(iload_reg_mem); -+%} -+ -+// Load Weak Pointer -+instruct zLoadWeakP(iRegPNoSp dst, memory mem, rFlagsReg cr) -+%{ -+ match(Set dst (LoadP mem)); -+ predicate(UseZGC && !needs_acquiring_load(n) && (n->as_Load()->barrier_data() == ZLoadBarrierWeak)); -+ effect(TEMP dst, KILL cr); -+ -+ ins_cost(4 * INSN_COST); - -+ format %{ "ldr $dst, $mem" %} -+ -+ ins_encode %{ -+ const Address ref_addr = mem2address($mem->opcode(), as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp); -+ __ ldr($dst$$Register, ref_addr); -+ z_load_barrier(_masm, this, ref_addr, $dst$$Register, rscratch2 /* tmp */, true /* weak */); -+ %} -+ -+ ins_pipe(iload_reg_mem); - %} - +- +-%} +- -// -// Execute ZGC load barrier (strong) slow path -// @@ -288,28 +331,10 @@ index af3e593a9..05b36e279 100644 - ins_encode %{ - z_load_barrier_slow_reg(_masm, $dst$$Register, $mem$$base$$Register, - $mem$$index, $mem$$scale, $mem$$disp, false); -+// Load Pointer Volatile -+instruct zLoadPVolatile(iRegPNoSp dst, indirect mem /* sync_memory */, rFlagsReg cr) -+%{ -+ match(Set dst (LoadP mem)); -+ predicate(UseZGC && needs_acquiring_load(n) && n->as_Load()->barrier_data() == ZLoadBarrierStrong); -+ effect(TEMP dst, KILL cr); -+ -+ ins_cost(VOLATILE_REF_COST); -+ -+ format %{ "ldar $dst, $mem\t" %} -+ -+ ins_encode %{ -+ __ ldar($dst$$Register, $mem$$Register); -+ if (barrier_data() != ZLoadBarrierElided) { -+ z_load_barrier(_masm, this, Address($mem$$Register), $dst$$Register, rscratch2 /* tmp */, false /* weak */); -+ } - %} +- %} - ins_pipe(pipe_slow); -+ -+ ins_pipe(pipe_serial); - %} - +-%} +- -// -// Execute ZGC load barrier (weak) slow path -// @@ -335,83 +360,30 @@ index af3e593a9..05b36e279 100644 - ins_encode %{ - z_load_barrier_slow_reg(_masm, $dst$$Register, $mem$$base$$Register, - $mem$$index, $mem$$scale, $mem$$disp, true); -+instruct zCompareAndSwapP(iRegINoSp res, indirect mem, iRegP oldval, iRegP newval, rFlagsReg cr) %{ -+ match(Set res (CompareAndSwapP mem (Binary oldval newval))); -+ match(Set res (WeakCompareAndSwapP mem (Binary oldval newval))); -+ predicate(UseZGC && !needs_acquiring_load_exclusive(n) && n->as_LoadStore()->barrier_data() == ZLoadBarrierStrong); -+ effect(KILL cr, TEMP_DEF res); -+ -+ ins_cost(2 * VOLATILE_REF_COST); -+ -+ format %{ "cmpxchg $mem, $oldval, $newval\n\t" -+ "cset $res, EQ" %} -+ -+ ins_encode %{ -+ guarantee($mem$$index == -1 && $mem$$disp == 0, "impossible encoding"); -+ __ cmpxchg($mem$$Register, $oldval$$Register, $newval$$Register, Assembler::xword, -+ false /* acquire */, true /* release */, false /* weak */, rscratch2); -+ __ cset($res$$Register, Assembler::EQ); -+ if (barrier_data() != ZLoadBarrierElided) { -+ Label good; -+ __ ldr(rscratch1, Address(rthread, ZThreadLocalData::address_bad_mask_offset())); -+ __ andr(rscratch1, rscratch1, rscratch2); -+ __ cbz(rscratch1, good); -+ z_load_barrier_slow_path(_masm, this, Address($mem$$Register), rscratch2 /* ref */, rscratch1 /* tmp */); -+ __ cmpxchg($mem$$Register, $oldval$$Register, $newval$$Register, Assembler::xword, -+ false /* acquire */, true /* release */, false /* weak */, rscratch2); -+ __ cset($res$$Register, Assembler::EQ); -+ __ bind(good); -+ } - %} -+ - ins_pipe(pipe_slow); - %} - +- %} +- ins_pipe(pipe_slow); +-%} +- -// Specialized versions of compareAndExchangeP that adds a keepalive that is consumed -// but doesn't affect output. -+instruct zCompareAndSwapPAcq(iRegINoSp res, indirect mem, iRegP oldval, iRegP newval, rFlagsReg cr) %{ -+ match(Set res (CompareAndSwapP mem (Binary oldval newval))); -+ match(Set res (WeakCompareAndSwapP mem (Binary oldval newval))); -+ predicate(UseZGC && needs_acquiring_load_exclusive(n) && (n->as_LoadStore()->barrier_data() == ZLoadBarrierStrong)); -+ effect(KILL cr, TEMP_DEF res); - +- -instruct z_compareAndExchangeP(iRegPNoSp res, indirect mem, - iRegP oldval, iRegP newval, iRegP keepalive, - rFlagsReg cr) %{ - match(Set res (ZCompareAndExchangeP (Binary mem keepalive) (Binary oldval newval))); - ins_cost(2 * VOLATILE_REF_COST); +- ins_cost(2 * VOLATILE_REF_COST); - effect(TEMP_DEF res, KILL cr); - format %{ - "cmpxchg $res = $mem, $oldval, $newval\t# (ptr, weak) if $mem == $oldval then $mem <-- $newval" - %} -+ -+ format %{ "cmpxchg $mem, $oldval, $newval\n\t" -+ "cset $res, EQ" %} -+ - ins_encode %{ +- ins_encode %{ - __ cmpxchg($mem$$Register, $oldval$$Register, $newval$$Register, - Assembler::xword, /*acquire*/ false, /*release*/ true, - /*weak*/ false, $res$$Register); -+ guarantee($mem$$index == -1 && $mem$$disp == 0, "impossible encoding"); -+ __ cmpxchg($mem$$Register, $oldval$$Register, $newval$$Register, Assembler::xword, -+ true /* acquire */, true /* release */, false /* weak */, rscratch2); -+ __ cset($res$$Register, Assembler::EQ); -+ if (barrier_data() != ZLoadBarrierElided) { -+ Label good; -+ __ ldr(rscratch1, Address(rthread, ZThreadLocalData::address_bad_mask_offset())); -+ __ andr(rscratch1, rscratch1, rscratch2); -+ __ cbz(rscratch1, good); -+ z_load_barrier_slow_path(_masm, this, Address($mem$$Register), rscratch2 /* ref */, rscratch1 /* tmp */ ); -+ __ cmpxchg($mem$$Register, $oldval$$Register, $newval$$Register, Assembler::xword, -+ true /* acquire */, true /* release */, false /* weak */, rscratch2); -+ __ cset($res$$Register, Assembler::EQ); -+ __ bind(good); -+ } - %} -+ - ins_pipe(pipe_slow); - %} - +- %} +- ins_pipe(pipe_slow); +-%} +- -instruct z_compareAndSwapP(iRegINoSp res, - indirect mem, - iRegP oldval, iRegP newval, iRegP keepalive, @@ -419,16 +391,11 @@ index af3e593a9..05b36e279 100644 - - match(Set res (ZCompareAndSwapP (Binary mem keepalive) (Binary oldval newval))); - match(Set res (ZWeakCompareAndSwapP (Binary mem keepalive) (Binary oldval newval))); -+instruct zCompareAndExchangeP(iRegPNoSp res, indirect mem, iRegP oldval, iRegP newval, rFlagsReg cr) %{ -+ match(Set res (CompareAndExchangeP mem (Binary oldval newval))); -+ predicate(UseZGC && !needs_acquiring_load_exclusive(n) && n->as_LoadStore()->barrier_data() == ZLoadBarrierStrong); -+ effect(TEMP_DEF res, KILL cr); - - ins_cost(2 * VOLATILE_REF_COST); - +- +- ins_cost(2 * VOLATILE_REF_COST); +- - effect(KILL cr); -+ format %{ "cmpxchg $res = $mem, $oldval, $newval" %} - +- - format %{ - "cmpxchg $mem, $oldval, $newval\t# (ptr) if $mem == $oldval then $mem <-- $newval" - "cset $res, EQ\t# $res <-- (EQ ? 1 : 0)" @@ -436,93 +403,25 @@ index af3e593a9..05b36e279 100644 - - ins_encode(aarch64_enc_cmpxchg(mem, oldval, newval), - aarch64_enc_cset_eq(res)); -+ ins_encode %{ -+ guarantee($mem$$index == -1 && $mem$$disp == 0, "impossible encoding"); -+ __ cmpxchg($mem$$Register, $oldval$$Register, $newval$$Register, Assembler::xword, -+ false /* acquire */, true /* release */, false /* weak */, $res$$Register); -+ if (barrier_data() != ZLoadBarrierElided) { -+ Label good; -+ __ ldr(rscratch1, Address(rthread, ZThreadLocalData::address_bad_mask_offset())); -+ __ andr(rscratch1, rscratch1, $res$$Register); -+ __ cbz(rscratch1, good); -+ z_load_barrier_slow_path(_masm, this, Address($mem$$Register), $res$$Register /* ref */, rscratch1 /* tmp */); -+ __ cmpxchg($mem$$Register, $oldval$$Register, $newval$$Register, Assembler::xword, -+ false /* acquire */, true /* release */, false /* weak */, $res$$Register); -+ __ bind(good); -+ } -+ %} - - ins_pipe(pipe_slow); - %} - -+instruct zCompareAndExchangePAcq(iRegPNoSp res, indirect mem, iRegP oldval, iRegP newval, rFlagsReg cr) %{ -+ match(Set res (CompareAndExchangeP mem (Binary oldval newval))); -+ predicate(UseZGC && needs_acquiring_load_exclusive(n) && n->as_LoadStore()->barrier_data() == ZLoadBarrierStrong); -+ effect(TEMP_DEF res, KILL cr); -+ -+ ins_cost(2 * VOLATILE_REF_COST); -+ -+ format %{ "cmpxchg $res = $mem, $oldval, $newval" %} - +- +- ins_pipe(pipe_slow); +-%} +- +- -instruct z_get_and_setP(indirect mem, iRegP newv, iRegPNoSp prev, - iRegP keepalive) %{ - match(Set prev (ZGetAndSetP mem (Binary newv keepalive))); -+ ins_encode %{ -+ guarantee($mem$$index == -1 && $mem$$disp == 0, "impossible encoding"); -+ __ cmpxchg($mem$$Register, $oldval$$Register, $newval$$Register, Assembler::xword, -+ true /* acquire */, true /* release */, false /* weak */, $res$$Register); -+ if (barrier_data() != ZLoadBarrierElided) { -+ Label good; -+ __ ldr(rscratch1, Address(rthread, ZThreadLocalData::address_bad_mask_offset())); -+ __ andr(rscratch1, rscratch1, $res$$Register); -+ __ cbz(rscratch1, good); -+ z_load_barrier_slow_path(_masm, this, Address($mem$$Register), $res$$Register /* ref */, rscratch1 /* tmp */); -+ __ cmpxchg($mem$$Register, $oldval$$Register, $newval$$Register, Assembler::xword, -+ true /* acquire */, true /* release */, false /* weak */, $res$$Register); -+ __ bind(good); -+ } -+ %} -+ -+ ins_pipe(pipe_slow); -+%} -+ -+instruct zGetAndSetP(indirect mem, iRegP newv, iRegPNoSp prev, rFlagsReg cr) %{ -+ match(Set prev (GetAndSetP mem newv)); -+ predicate(UseZGC && !needs_acquiring_load_exclusive(n) && n->as_LoadStore()->barrier_data() == ZLoadBarrierStrong); -+ effect(TEMP_DEF prev, KILL cr); - - ins_cost(2 * VOLATILE_REF_COST); -+ - format %{ "atomic_xchg $prev, $newv, [$mem]" %} -+ - ins_encode %{ +- +- ins_cost(2 * VOLATILE_REF_COST); +- format %{ "atomic_xchg $prev, $newv, [$mem]" %} +- ins_encode %{ - __ atomic_xchg($prev$$Register, $newv$$Register, as_Register($mem$$base)); -+ __ atomic_xchg($prev$$Register, $newv$$Register, $mem$$Register); -+ if (barrier_data() != ZLoadBarrierElided) { -+ z_load_barrier(_masm, this, Address(noreg, 0), $prev$$Register, rscratch2 /* tmp */, false /* weak */); -+ } -+ %} -+ -+ ins_pipe(pipe_serial); -+%} -+ -+instruct zGetAndSetPAcq(indirect mem, iRegP newv, iRegPNoSp prev, rFlagsReg cr) %{ -+ match(Set prev (GetAndSetP mem newv)); -+ predicate(UseZGC && needs_acquiring_load_exclusive(n) && (n->as_LoadStore()->barrier_data() == ZLoadBarrierStrong)); -+ effect(TEMP_DEF prev, KILL cr); -+ -+ ins_cost(VOLATILE_REF_COST); -+ -+ format %{ "atomic_xchg_acq $prev, $newv, [$mem]" %} -+ -+ ins_encode %{ -+ __ atomic_xchgal($prev$$Register, $newv$$Register, $mem$$Register); -+ if (barrier_data() != ZLoadBarrierElided) { -+ z_load_barrier(_masm, this, Address(noreg, 0), $prev$$Register, rscratch2 /* tmp */, false /* weak */); -+ } - %} - ins_pipe(pipe_serial); - %} +- %} +- ins_pipe(pipe_serial); +-%} + + //----------PEEPHOLE RULES----------------------------------------------------- + // These must follow all instruction definitions as they use the names diff --git a/src/hotspot/cpu/aarch64/gc/z/zBarrierSetAssembler_aarch64.cpp b/src/hotspot/cpu/aarch64/gc/z/zBarrierSetAssembler_aarch64.cpp index 8e169ace4..787c0c1af 100644 --- a/src/hotspot/cpu/aarch64/gc/z/zBarrierSetAssembler_aarch64.cpp @@ -933,11 +832,285 @@ index 7e8be01cc..cca873825 100644 }; #endif // CPU_AARCH64_GC_Z_ZBARRIERSETASSEMBLER_AARCH64_HPP +diff --git a/src/hotspot/cpu/aarch64/gc/z/z_aarch64.ad b/src/hotspot/cpu/aarch64/gc/z/z_aarch64.ad +new file mode 100644 +index 000000000..50cc6f924 +--- /dev/null ++++ b/src/hotspot/cpu/aarch64/gc/z/z_aarch64.ad +@@ -0,0 +1,268 @@ ++// ++// Copyright (c) 2019, Oracle and/or its affiliates. All rights reserved. ++// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++// ++// This code is free software; you can redistribute it and/or modify it ++// under the terms of the GNU General Public License version 2 only, as ++// published by the Free Software Foundation. ++// ++// This code is distributed in the hope that it will be useful, but WITHOUT ++// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++// version 2 for more details (a copy is included in the LICENSE file that ++// accompanied this code). ++// ++// You should have received a copy of the GNU General Public License version ++// 2 along with this work; if not, write to the Free Software Foundation, ++// Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++// ++// Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++// or visit www.oracle.com if you need additional information or have any ++// questions. ++// ++ ++source_hpp %{ ++ ++#include "gc/z/c2/zBarrierSetC2.hpp" ++#include "gc/z/zThreadLocalData.hpp" ++ ++%} ++ ++source %{ ++ ++static void z_load_barrier(MacroAssembler& _masm, const MachNode* node, Address ref_addr, Register ref, Register tmp, bool weak) { ++ ZLoadBarrierStubC2* const stub = ZLoadBarrierStubC2::create(node, ref_addr, ref, tmp, weak); ++ __ ldr(tmp, Address(rthread, ZThreadLocalData::address_bad_mask_offset())); ++ __ andr(tmp, tmp, ref); ++ __ cbnz(tmp, *stub->entry()); ++ __ bind(*stub->continuation()); ++} ++ ++static void z_load_barrier_slow_path(MacroAssembler& _masm, const MachNode* node, Address ref_addr, Register ref, Register tmp) { ++ ZLoadBarrierStubC2* const stub = ZLoadBarrierStubC2::create(node, ref_addr, ref, tmp, false /* weak */); ++ __ b(*stub->entry()); ++ __ bind(*stub->continuation()); ++} ++ ++%} ++ ++// Load Pointer ++instruct zLoadP(iRegPNoSp dst, memory mem, rFlagsReg cr) ++%{ ++ match(Set dst (LoadP mem)); ++ predicate(UseZGC && !needs_acquiring_load(n) && (n->as_Load()->barrier_data() == ZLoadBarrierStrong)); ++ effect(TEMP dst, KILL cr); ++ ++ ins_cost(4 * INSN_COST); ++ ++ format %{ "ldr $dst, $mem" %} ++ ++ ins_encode %{ ++ const Address ref_addr = mem2address($mem->opcode(), as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp); ++ __ ldr($dst$$Register, ref_addr); ++ if (barrier_data() != ZLoadBarrierElided) { ++ z_load_barrier(_masm, this, ref_addr, $dst$$Register, rscratch2 /* tmp */, false /* weak */); ++ } ++ %} ++ ++ ins_pipe(iload_reg_mem); ++%} ++ ++// Load Weak Pointer ++instruct zLoadWeakP(iRegPNoSp dst, memory mem, rFlagsReg cr) ++%{ ++ match(Set dst (LoadP mem)); ++ predicate(UseZGC && !needs_acquiring_load(n) && (n->as_Load()->barrier_data() == ZLoadBarrierWeak)); ++ effect(TEMP dst, KILL cr); ++ ++ ins_cost(4 * INSN_COST); ++ ++ format %{ "ldr $dst, $mem" %} ++ ++ ins_encode %{ ++ const Address ref_addr = mem2address($mem->opcode(), as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp); ++ __ ldr($dst$$Register, ref_addr); ++ z_load_barrier(_masm, this, ref_addr, $dst$$Register, rscratch2 /* tmp */, true /* weak */); ++ %} ++ ++ ins_pipe(iload_reg_mem); ++%} ++ ++// Load Pointer Volatile ++instruct zLoadPVolatile(iRegPNoSp dst, indirect mem /* sync_memory */, rFlagsReg cr) ++%{ ++ match(Set dst (LoadP mem)); ++ predicate(UseZGC && needs_acquiring_load(n) && n->as_Load()->barrier_data() == ZLoadBarrierStrong); ++ effect(TEMP dst, KILL cr); ++ ++ ins_cost(VOLATILE_REF_COST); ++ ++ format %{ "ldar $dst, $mem\t" %} ++ ++ ins_encode %{ ++ __ ldar($dst$$Register, $mem$$Register); ++ if (barrier_data() != ZLoadBarrierElided) { ++ z_load_barrier(_masm, this, Address($mem$$Register), $dst$$Register, rscratch2 /* tmp */, false /* weak */); ++ } ++ %} ++ ++ ins_pipe(pipe_serial); ++%} ++ ++instruct zCompareAndSwapP(iRegINoSp res, indirect mem, iRegP oldval, iRegP newval, rFlagsReg cr) %{ ++ match(Set res (CompareAndSwapP mem (Binary oldval newval))); ++ match(Set res (WeakCompareAndSwapP mem (Binary oldval newval))); ++ predicate(UseZGC && !needs_acquiring_load_exclusive(n) && n->as_LoadStore()->barrier_data() == ZLoadBarrierStrong); ++ effect(KILL cr, TEMP_DEF res); ++ ++ ins_cost(2 * VOLATILE_REF_COST); ++ ++ format %{ "cmpxchg $mem, $oldval, $newval\n\t" ++ "cset $res, EQ" %} ++ ++ ins_encode %{ ++ guarantee($mem$$index == -1 && $mem$$disp == 0, "impossible encoding"); ++ __ cmpxchg($mem$$Register, $oldval$$Register, $newval$$Register, Assembler::xword, ++ false /* acquire */, true /* release */, false /* weak */, rscratch2); ++ __ cset($res$$Register, Assembler::EQ); ++ if (barrier_data() != ZLoadBarrierElided) { ++ Label good; ++ __ ldr(rscratch1, Address(rthread, ZThreadLocalData::address_bad_mask_offset())); ++ __ andr(rscratch1, rscratch1, rscratch2); ++ __ cbz(rscratch1, good); ++ z_load_barrier_slow_path(_masm, this, Address($mem$$Register), rscratch2 /* ref */, rscratch1 /* tmp */); ++ __ cmpxchg($mem$$Register, $oldval$$Register, $newval$$Register, Assembler::xword, ++ false /* acquire */, true /* release */, false /* weak */, rscratch2); ++ __ cset($res$$Register, Assembler::EQ); ++ __ bind(good); ++ } ++ %} ++ ++ ins_pipe(pipe_slow); ++%} ++ ++instruct zCompareAndSwapPAcq(iRegINoSp res, indirect mem, iRegP oldval, iRegP newval, rFlagsReg cr) %{ ++ match(Set res (CompareAndSwapP mem (Binary oldval newval))); ++ match(Set res (WeakCompareAndSwapP mem (Binary oldval newval))); ++ predicate(UseZGC && needs_acquiring_load_exclusive(n) && (n->as_LoadStore()->barrier_data() == ZLoadBarrierStrong)); ++ effect(KILL cr, TEMP_DEF res); ++ ++ ins_cost(2 * VOLATILE_REF_COST); ++ ++ format %{ "cmpxchg $mem, $oldval, $newval\n\t" ++ "cset $res, EQ" %} ++ ++ ins_encode %{ ++ guarantee($mem$$index == -1 && $mem$$disp == 0, "impossible encoding"); ++ __ cmpxchg($mem$$Register, $oldval$$Register, $newval$$Register, Assembler::xword, ++ true /* acquire */, true /* release */, false /* weak */, rscratch2); ++ __ cset($res$$Register, Assembler::EQ); ++ if (barrier_data() != ZLoadBarrierElided) { ++ Label good; ++ __ ldr(rscratch1, Address(rthread, ZThreadLocalData::address_bad_mask_offset())); ++ __ andr(rscratch1, rscratch1, rscratch2); ++ __ cbz(rscratch1, good); ++ z_load_barrier_slow_path(_masm, this, Address($mem$$Register), rscratch2 /* ref */, rscratch1 /* tmp */ ); ++ __ cmpxchg($mem$$Register, $oldval$$Register, $newval$$Register, Assembler::xword, ++ true /* acquire */, true /* release */, false /* weak */, rscratch2); ++ __ cset($res$$Register, Assembler::EQ); ++ __ bind(good); ++ } ++ %} ++ ++ ins_pipe(pipe_slow); ++%} ++ ++instruct zCompareAndExchangeP(iRegPNoSp res, indirect mem, iRegP oldval, iRegP newval, rFlagsReg cr) %{ ++ match(Set res (CompareAndExchangeP mem (Binary oldval newval))); ++ predicate(UseZGC && !needs_acquiring_load_exclusive(n) && n->as_LoadStore()->barrier_data() == ZLoadBarrierStrong); ++ effect(TEMP_DEF res, KILL cr); ++ ++ ins_cost(2 * VOLATILE_REF_COST); ++ ++ format %{ "cmpxchg $res = $mem, $oldval, $newval" %} ++ ++ ins_encode %{ ++ guarantee($mem$$index == -1 && $mem$$disp == 0, "impossible encoding"); ++ __ cmpxchg($mem$$Register, $oldval$$Register, $newval$$Register, Assembler::xword, ++ false /* acquire */, true /* release */, false /* weak */, $res$$Register); ++ if (barrier_data() != ZLoadBarrierElided) { ++ Label good; ++ __ ldr(rscratch1, Address(rthread, ZThreadLocalData::address_bad_mask_offset())); ++ __ andr(rscratch1, rscratch1, $res$$Register); ++ __ cbz(rscratch1, good); ++ z_load_barrier_slow_path(_masm, this, Address($mem$$Register), $res$$Register /* ref */, rscratch1 /* tmp */); ++ __ cmpxchg($mem$$Register, $oldval$$Register, $newval$$Register, Assembler::xword, ++ false /* acquire */, true /* release */, false /* weak */, $res$$Register); ++ __ bind(good); ++ } ++ %} ++ ++ ins_pipe(pipe_slow); ++%} ++ ++instruct zCompareAndExchangePAcq(iRegPNoSp res, indirect mem, iRegP oldval, iRegP newval, rFlagsReg cr) %{ ++ match(Set res (CompareAndExchangeP mem (Binary oldval newval))); ++ predicate(UseZGC && needs_acquiring_load_exclusive(n) && n->as_LoadStore()->barrier_data() == ZLoadBarrierStrong); ++ effect(TEMP_DEF res, KILL cr); ++ ++ ins_cost(2 * VOLATILE_REF_COST); ++ ++ format %{ "cmpxchg $res = $mem, $oldval, $newval" %} ++ ++ ins_encode %{ ++ guarantee($mem$$index == -1 && $mem$$disp == 0, "impossible encoding"); ++ __ cmpxchg($mem$$Register, $oldval$$Register, $newval$$Register, Assembler::xword, ++ true /* acquire */, true /* release */, false /* weak */, $res$$Register); ++ if (barrier_data() != ZLoadBarrierElided) { ++ Label good; ++ __ ldr(rscratch1, Address(rthread, ZThreadLocalData::address_bad_mask_offset())); ++ __ andr(rscratch1, rscratch1, $res$$Register); ++ __ cbz(rscratch1, good); ++ z_load_barrier_slow_path(_masm, this, Address($mem$$Register), $res$$Register /* ref */, rscratch1 /* tmp */); ++ __ cmpxchg($mem$$Register, $oldval$$Register, $newval$$Register, Assembler::xword, ++ true /* acquire */, true /* release */, false /* weak */, $res$$Register); ++ __ bind(good); ++ } ++ %} ++ ++ ins_pipe(pipe_slow); ++%} ++ ++instruct zGetAndSetP(indirect mem, iRegP newv, iRegPNoSp prev, rFlagsReg cr) %{ ++ match(Set prev (GetAndSetP mem newv)); ++ predicate(UseZGC && !needs_acquiring_load_exclusive(n) && n->as_LoadStore()->barrier_data() == ZLoadBarrierStrong); ++ effect(TEMP_DEF prev, KILL cr); ++ ++ ins_cost(2 * VOLATILE_REF_COST); ++ ++ format %{ "atomic_xchg $prev, $newv, [$mem]" %} ++ ++ ins_encode %{ ++ __ atomic_xchg($prev$$Register, $newv$$Register, $mem$$Register); ++ if (barrier_data() != ZLoadBarrierElided) { ++ z_load_barrier(_masm, this, Address(noreg, 0), $prev$$Register, rscratch2 /* tmp */, false /* weak */); ++ } ++ %} ++ ++ ins_pipe(pipe_serial); ++%} ++ ++instruct zGetAndSetPAcq(indirect mem, iRegP newv, iRegPNoSp prev, rFlagsReg cr) %{ ++ match(Set prev (GetAndSetP mem newv)); ++ predicate(UseZGC && needs_acquiring_load_exclusive(n) && (n->as_LoadStore()->barrier_data() == ZLoadBarrierStrong)); ++ effect(TEMP_DEF prev, KILL cr); ++ ++ ins_cost(VOLATILE_REF_COST); ++ ++ format %{ "atomic_xchg_acq $prev, $newv, [$mem]" %} ++ ++ ins_encode %{ ++ __ atomic_xchgal($prev$$Register, $newv$$Register, $mem$$Register); ++ if (barrier_data() != ZLoadBarrierElided) { ++ z_load_barrier(_masm, this, Address(noreg, 0), $prev$$Register, rscratch2 /* tmp */, false /* weak */); ++ } ++ %} ++ ins_pipe(pipe_serial); ++%} ++ diff --git a/src/hotspot/cpu/aarch64/macroAssembler_aarch64.cpp b/src/hotspot/cpu/aarch64/macroAssembler_aarch64.cpp -index d24ba97e1..08d39c4bd 100644 +index 7f329a45d..5ddf049ce 100644 --- a/src/hotspot/cpu/aarch64/macroAssembler_aarch64.cpp +++ b/src/hotspot/cpu/aarch64/macroAssembler_aarch64.cpp -@@ -2096,6 +2096,65 @@ int MacroAssembler::pop(unsigned int bitset, Register stack) { +@@ -2129,6 +2129,67 @@ int MacroAssembler::pop(unsigned int bitset, Register stack) { return count; } @@ -945,57 +1118,59 @@ index d24ba97e1..08d39c4bd 100644 +// Push lots of registers in the bit set supplied. Don't push sp. +// Return the number of words pushed +int MacroAssembler::push_fp(unsigned int bitset, Register stack) { -+ int words_pushed = 0; -+ + // Scan bitset to accumulate register pairs + unsigned char regs[32]; + int count = 0; ++ int i = 0; + for (int reg = 0; reg <= 31; reg++) { + if (1 & bitset) + regs[count++] = reg; + bitset >>= 1; + } -+ regs[count++] = zr->encoding_nocheck(); -+ count &= ~1; // Only push an even number of regs + -+ // Always pushing full 128 bit registers. -+ if (count) { -+ stpq(as_FloatRegister(regs[0]), as_FloatRegister(regs[1]), Address(pre(stack, -count * wordSize * 2))); -+ words_pushed += 2; ++ if (!count) { ++ return 0; ++ } ++ ++ add(stack, stack, -count * wordSize * 2); ++ ++ if (count & 1) { ++ strq(as_FloatRegister(regs[0]), Address(stack)); ++ i += 1; + } -+ for (int i = 2; i < count; i += 2) { ++ ++ for (; i < count; i += 2) { + stpq(as_FloatRegister(regs[i]), as_FloatRegister(regs[i+1]), Address(stack, i * wordSize * 2)); -+ words_pushed += 2; + } + -+ assert(words_pushed == count, "oops, pushed != count"); + return count; +} + +int MacroAssembler::pop_fp(unsigned int bitset, Register stack) { -+ int words_pushed = 0; -+ + // Scan bitset to accumulate register pairs + unsigned char regs[32]; + int count = 0; ++ int i = 0; + for (int reg = 0; reg <= 31; reg++) { + if (1 & bitset) + regs[count++] = reg; + bitset >>= 1; + } -+ regs[count++] = zr->encoding_nocheck(); -+ count &= ~1; + -+ for (int i = 2; i < count; i += 2) { -+ ldpq(as_FloatRegister(regs[i]), as_FloatRegister(regs[i+1]), Address(stack, i * wordSize * 2)); -+ words_pushed += 2; ++ if (!count) { ++ return 0; + } -+ if (count) { -+ ldpq(as_FloatRegister(regs[0]), as_FloatRegister(regs[1]), Address(post(stack, count * wordSize * 2))); -+ words_pushed += 2; ++ ++ if (count & 1) { ++ ldrq(as_FloatRegister(regs[0]), Address(stack)); ++ i += 1; ++ } ++ ++ for (; i < count; i += 2) { ++ ldpq(as_FloatRegister(regs[i]), as_FloatRegister(regs[i+1]), Address(stack, i * wordSize * 2)); + } + -+ assert(words_pushed == count, "oops, pushed != count"); ++ add(stack, stack, count * wordSize * 2); + + return count; +} @@ -1004,30 +1179,30 @@ index d24ba97e1..08d39c4bd 100644 void MacroAssembler::verify_heapbase(const char* msg) { #if 0 diff --git a/src/hotspot/cpu/aarch64/macroAssembler_aarch64.hpp b/src/hotspot/cpu/aarch64/macroAssembler_aarch64.hpp -index edcfd9ceb..60b728e94 100644 +index 01fdf16a0..073854d2b 100644 --- a/src/hotspot/cpu/aarch64/macroAssembler_aarch64.hpp +++ b/src/hotspot/cpu/aarch64/macroAssembler_aarch64.hpp -@@ -462,12 +462,18 @@ private: +@@ -463,12 +463,18 @@ private: int push(unsigned int bitset, Register stack); int pop(unsigned int bitset, Register stack); - + + int push_fp(unsigned int bitset, Register stack); + int pop_fp(unsigned int bitset, Register stack); + void mov(Register dst, Address a); - + public: void push(RegSet regs, Register stack) { if (regs.bits()) push(regs.bits(), stack); } void pop(RegSet regs, Register stack) { if (regs.bits()) pop(regs.bits(), stack); } - + + void push_fp(RegSet regs, Register stack) { if (regs.bits()) push_fp(regs.bits(), stack); } + void pop_fp(RegSet regs, Register stack) { if (regs.bits()) pop_fp(regs.bits(), stack); } + static RegSet call_clobbered_registers(); - + // Push and pop everything that might be clobbered by a native diff --git a/src/hotspot/cpu/aarch64/templateInterpreterGenerator_aarch64.cpp b/src/hotspot/cpu/aarch64/templateInterpreterGenerator_aarch64.cpp -index c162024db..6e4eb1a7a 100644 +index 21ba661ea..430f3ee14 100644 --- a/src/hotspot/cpu/aarch64/templateInterpreterGenerator_aarch64.cpp +++ b/src/hotspot/cpu/aarch64/templateInterpreterGenerator_aarch64.cpp @@ -880,8 +880,8 @@ void TemplateInterpreterGenerator::generate_fixed_frame(bool native_call) { @@ -1041,11 +1216,43 @@ index c162024db..6e4eb1a7a 100644 } __ ldr(rcpool, Address(rmethod, Method::const_offset())); +diff --git a/src/hotspot/cpu/aarch64/vm_version_aarch64.hpp b/src/hotspot/cpu/aarch64/vm_version_aarch64.hpp +index 8c9676aed..e417f07be 100644 +--- a/src/hotspot/cpu/aarch64/vm_version_aarch64.hpp ++++ b/src/hotspot/cpu/aarch64/vm_version_aarch64.hpp +@@ -75,6 +75,7 @@ public: + CPU_BROADCOM = 'B', + CPU_CAVIUM = 'C', + CPU_DEC = 'D', ++ CPU_HISILICON = 'H', + CPU_INFINEON = 'I', + CPU_MOTOROLA = 'M', + CPU_NVIDIA = 'N', +@@ -107,6 +108,13 @@ public: + static int cpu_variant() { return _variant; } + static int cpu_revision() { return _revision; } + ++ static bool is_hisi_enabled() { ++ if (_cpu == CPU_HISILICON && (_model == 0xd01 || _model == 0xd02 || _model == 0xd03)) { ++ return true; ++ } ++ return false; ++ } ++ + static bool is_zva_enabled() { return 0 <= _zva_length; } + static int zva_length() { + assert(is_zva_enabled(), "ZVA not available"); diff --git a/src/hotspot/cpu/x86/gc/z/zBarrierSetAssembler_x86.cpp b/src/hotspot/cpu/x86/gc/z/zBarrierSetAssembler_x86.cpp -index 381211ecc..d88ecf7b8 100644 +index f5de1ed88..4428e96bc 100644 --- a/src/hotspot/cpu/x86/gc/z/zBarrierSetAssembler_x86.cpp +++ b/src/hotspot/cpu/x86/gc/z/zBarrierSetAssembler_x86.cpp -@@ -27,16 +27,16 @@ +@@ -24,21 +24,22 @@ + #include "precompiled.hpp" + #include "asm/macroAssembler.inline.hpp" + #include "code/codeBlob.hpp" ++#include "code/vmreg.inline.hpp" + #include "gc/z/zBarrier.inline.hpp" + #include "gc/z/zBarrierSet.hpp" #include "gc/z/zBarrierSetAssembler.hpp" #include "gc/z/zBarrierSetRuntime.hpp" #include "memory/resourceArea.hpp" @@ -1066,7 +1273,7 @@ index 381211ecc..d88ecf7b8 100644 #ifdef PRODUCT #define BLOCK_COMMENT(str) /* nothing */ -@@ -44,6 +44,9 @@ +@@ -46,6 +47,9 @@ #define BLOCK_COMMENT(str) __ block_comment(str) #endif @@ -1076,7 +1283,7 @@ index 381211ecc..d88ecf7b8 100644 static void call_vm(MacroAssembler* masm, address entry_point, Register arg0, -@@ -333,126 +336,326 @@ void ZBarrierSetAssembler::generate_c1_load_barrier_runtime_stub(StubAssembler* +@@ -335,126 +339,326 @@ void ZBarrierSetAssembler::generate_c1_load_barrier_runtime_stub(StubAssembler* #endif // COMPILER1 @@ -1451,113 +1658,287 @@ index 381211ecc..d88ecf7b8 100644 + } + } + } - } - -- __ ret(0); -- -- return start; --} -+ ~ZSetupArguments() { -+ // Transfer result -+ if (_ref != rax) { -+ __ movq(_ref, rax); + } + +- __ ret(0); +- +- return start; +-} ++ ~ZSetupArguments() { ++ // Transfer result ++ if (_ref != rax) { ++ __ movq(_ref, rax); ++ } ++ } ++}; + + #undef __ ++#define __ masm-> + +-void ZBarrierSetAssembler::barrier_stubs_init() { +- // Load barrier stubs +- int stub_code_size = 256 * 16; // Rough estimate of code size ++void ZBarrierSetAssembler::generate_c2_load_barrier_stub(MacroAssembler* masm, ZLoadBarrierStubC2* stub) const { ++ BLOCK_COMMENT("ZLoadBarrierStubC2"); + +- ResourceMark rm; +- BufferBlob* bb = BufferBlob::create("zgc_load_barrier_stubs", stub_code_size); +- CodeBuffer buf(bb); +- StubCodeGenerator cgen(&buf); ++ // Stub entry ++ __ bind(*stub->entry()); + +- Register rr = as_Register(0); +- for (int i = 0; i < RegisterImpl::number_of_registers; i++) { +- _load_barrier_slow_stub[i] = generate_load_barrier_stub(&cgen, rr, ON_STRONG_OOP_REF); +- _load_barrier_weak_slow_stub[i] = generate_load_barrier_stub(&cgen, rr, ON_WEAK_OOP_REF); +- rr = rr->successor(); ++ { ++ ZSaveLiveRegisters save_live_registers(masm, stub); ++ ZSetupArguments setup_arguments(masm, stub); ++ __ call(RuntimeAddress(stub->slow_path())); + } ++ ++ // Stub exit ++ __ jmp(*stub->continuation()); + } ++ ++#undef __ ++ ++#endif // COMPILER2 +diff --git a/src/hotspot/cpu/x86/gc/z/zBarrierSetAssembler_x86.hpp b/src/hotspot/cpu/x86/gc/z/zBarrierSetAssembler_x86.hpp +index 3687754e7..e433882a4 100644 +--- a/src/hotspot/cpu/x86/gc/z/zBarrierSetAssembler_x86.hpp ++++ b/src/hotspot/cpu/x86/gc/z/zBarrierSetAssembler_x86.hpp +@@ -24,6 +24,14 @@ + #ifndef CPU_X86_GC_Z_ZBARRIERSETASSEMBLER_X86_HPP + #define CPU_X86_GC_Z_ZBARRIERSETASSEMBLER_X86_HPP + ++#include "code/vmreg.hpp" ++#include "oops/accessDecorators.hpp" ++#ifdef COMPILER2 ++#include "opto/optoreg.hpp" ++#endif // COMPILER2 ++ ++class MacroAssembler; ++ + #ifdef COMPILER1 + class LIR_Assembler; + class LIR_OprDesc; +@@ -32,18 +40,13 @@ class StubAssembler; + class ZLoadBarrierStubC1; + #endif // COMPILER1 + +-class ZBarrierSetAssembler : public ZBarrierSetAssemblerBase { +- address _load_barrier_slow_stub[RegisterImpl::number_of_registers]; +- address _load_barrier_weak_slow_stub[RegisterImpl::number_of_registers]; ++#ifdef COMPILER2 ++class Node; ++class ZLoadBarrierStubC2; ++#endif // COMPILER2 + ++class ZBarrierSetAssembler : public ZBarrierSetAssemblerBase { + public: +- ZBarrierSetAssembler() : +- _load_barrier_slow_stub(), +- _load_barrier_weak_slow_stub() {} +- +- address load_barrier_slow_stub(Register reg) { return _load_barrier_slow_stub[reg->encoding()]; } +- address load_barrier_weak_slow_stub(Register reg) { return _load_barrier_weak_slow_stub[reg->encoding()]; } +- + virtual void load_at(MacroAssembler* masm, + DecoratorSet decorators, + BasicType type, +@@ -86,7 +89,12 @@ public: + DecoratorSet decorators) const; + #endif // COMPILER1 + +- virtual void barrier_stubs_init(); ++#ifdef COMPILER2 ++ OptoReg::Name refine_register(const Node* node, ++ OptoReg::Name opto_reg); ++ void generate_c2_load_barrier_stub(MacroAssembler* masm, ++ ZLoadBarrierStubC2* stub) const; ++#endif // COMPILER2 + }; + + #endif // CPU_X86_GC_Z_ZBARRIERSETASSEMBLER_X86_HPP +diff --git a/src/hotspot/cpu/x86/gc/z/z_x86_64.ad b/src/hotspot/cpu/x86/gc/z/z_x86_64.ad +new file mode 100644 +index 000000000..38c2e926b +--- /dev/null ++++ b/src/hotspot/cpu/x86/gc/z/z_x86_64.ad +@@ -0,0 +1,168 @@ ++// ++// Copyright (c) 2015, 2019, Oracle and/or its affiliates. All rights reserved. ++// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++// ++// This code is free software; you can redistribute it and/or modify it ++// under the terms of the GNU General Public License version 2 only, as ++// published by the Free Software Foundation. ++// ++// This code is distributed in the hope that it will be useful, but WITHOUT ++// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++// version 2 for more details (a copy is included in the LICENSE file that ++// accompanied this code). ++// ++// You should have received a copy of the GNU General Public License version ++// 2 along with this work; if not, write to the Free Software Foundation, ++// Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++// ++// Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++// or visit www.oracle.com if you need additional information or have any ++// questions. ++// ++ ++source_hpp %{ ++ ++#include "gc/z/c2/zBarrierSetC2.hpp" ++#include "gc/z/zThreadLocalData.hpp" ++ ++%} ++ ++source %{ ++ ++static void z_load_barrier(MacroAssembler& _masm, const MachNode* node, Address ref_addr, Register ref, Register tmp, bool weak) { ++ ZLoadBarrierStubC2* const stub = ZLoadBarrierStubC2::create(node, ref_addr, ref, tmp, weak); ++ __ testptr(ref, Address(r15_thread, ZThreadLocalData::address_bad_mask_offset())); ++ __ jcc(Assembler::notZero, *stub->entry()); ++ __ bind(*stub->continuation()); ++} ++ ++static void z_load_barrier_slow_path(MacroAssembler& _masm, const MachNode* node, Address ref_addr, Register ref, Register tmp) { ++ ZLoadBarrierStubC2* const stub = ZLoadBarrierStubC2::create(node, ref_addr, ref, tmp, false /* weak */); ++ __ jmp(*stub->entry()); ++ __ bind(*stub->continuation()); ++} ++ ++%} ++ ++// Load Pointer ++instruct zLoadP(rRegP dst, memory mem, rFlagsReg cr) ++%{ ++ predicate(UseZGC && n->as_Load()->barrier_data() == ZLoadBarrierStrong); ++ match(Set dst (LoadP mem)); ++ effect(KILL cr, TEMP dst); ++ ++ ins_cost(125); ++ ++ format %{ "movq $dst, $mem" %} ++ ++ ins_encode %{ ++ __ movptr($dst$$Register, $mem$$Address); ++ if (barrier_data() != ZLoadBarrierElided) { ++ z_load_barrier(_masm, this, $mem$$Address, $dst$$Register, noreg /* tmp */, false /* weak */); ++ } ++ %} ++ ++ ins_pipe(ialu_reg_mem); ++%} ++ ++// Load Weak Pointer ++instruct zLoadWeakP(rRegP dst, memory mem, rFlagsReg cr) ++%{ ++ predicate(UseZGC && n->as_Load()->barrier_data() == ZLoadBarrierWeak); ++ match(Set dst (LoadP mem)); ++ effect(KILL cr, TEMP dst); ++ ++ ins_cost(125); ++ ++ format %{ "movq $dst, $mem" %} ++ ++ ins_encode %{ ++ __ movptr($dst$$Register, $mem$$Address); ++ z_load_barrier(_masm, this, $mem$$Address, $dst$$Register, noreg /* tmp */, true /* weak */); ++ %} ++ ++ ins_pipe(ialu_reg_mem); ++%} ++ ++instruct zCompareAndExchangeP(memory mem, rax_RegP oldval, rRegP newval, rRegP tmp, rFlagsReg cr) %{ ++ match(Set oldval (CompareAndExchangeP mem (Binary oldval newval))); ++ predicate(UseZGC && n->as_LoadStore()->barrier_data() == ZLoadBarrierStrong); ++ effect(KILL cr, TEMP tmp); ++ ++ format %{ "lock\n\t" ++ "cmpxchgq $newval, $mem" %} ++ ++ ins_encode %{ ++ if (barrier_data() != ZLoadBarrierElided) { ++ __ movptr($tmp$$Register, $oldval$$Register); ++ } ++ __ lock(); ++ __ cmpxchgptr($newval$$Register, $mem$$Address); ++ if (barrier_data() != ZLoadBarrierElided) { ++ Label good; ++ __ testptr($oldval$$Register, Address(r15_thread, ZThreadLocalData::address_bad_mask_offset())); ++ __ jcc(Assembler::zero, good); ++ z_load_barrier_slow_path(_masm, this, $mem$$Address, $oldval$$Register, $tmp$$Register); ++ __ movptr($oldval$$Register, $tmp$$Register); ++ __ lock(); ++ __ cmpxchgptr($newval$$Register, $mem$$Address); ++ __ bind(good); ++ } ++ %} ++ ++ ins_pipe(pipe_cmpxchg); ++%} ++ ++instruct zCompareAndSwapP(rRegI res, memory mem, rRegP newval, rRegP tmp, rFlagsReg cr, rax_RegP oldval) %{ ++ match(Set res (CompareAndSwapP mem (Binary oldval newval))); ++ match(Set res (WeakCompareAndSwapP mem (Binary oldval newval))); ++ predicate(UseZGC && n->as_LoadStore()->barrier_data() == ZLoadBarrierStrong); ++ effect(KILL cr, KILL oldval, TEMP tmp); ++ ++ format %{ "lock\n\t" ++ "cmpxchgq $newval, $mem\n\t" ++ "sete $res\n\t" ++ "movzbl $res, $res" %} ++ ++ ins_encode %{ ++ if (barrier_data() != ZLoadBarrierElided) { ++ __ movptr($tmp$$Register, $oldval$$Register); ++ } ++ __ lock(); ++ __ cmpxchgptr($newval$$Register, $mem$$Address); ++ if (barrier_data() != ZLoadBarrierElided) { ++ Label good; ++ __ testptr($oldval$$Register, Address(r15_thread, ZThreadLocalData::address_bad_mask_offset())); ++ __ jcc(Assembler::zero, good); ++ z_load_barrier_slow_path(_masm, this, $mem$$Address, $oldval$$Register, $tmp$$Register); ++ __ movptr($oldval$$Register, $tmp$$Register); ++ __ lock(); ++ __ cmpxchgptr($newval$$Register, $mem$$Address); ++ __ bind(good); ++ __ cmpptr($tmp$$Register, $oldval$$Register); + } -+ } -+}; - - #undef __ -+#define __ masm-> - --void ZBarrierSetAssembler::barrier_stubs_init() { -- // Load barrier stubs -- int stub_code_size = 256 * 16; // Rough estimate of code size -+void ZBarrierSetAssembler::generate_c2_load_barrier_stub(MacroAssembler* masm, ZLoadBarrierStubC2* stub) const { -+ BLOCK_COMMENT("ZLoadBarrierStubC2"); - -- ResourceMark rm; -- BufferBlob* bb = BufferBlob::create("zgc_load_barrier_stubs", stub_code_size); -- CodeBuffer buf(bb); -- StubCodeGenerator cgen(&buf); -+ // Stub entry -+ __ bind(*stub->entry()); - -- Register rr = as_Register(0); -- for (int i = 0; i < RegisterImpl::number_of_registers; i++) { -- _load_barrier_slow_stub[i] = generate_load_barrier_stub(&cgen, rr, ON_STRONG_OOP_REF); -- _load_barrier_weak_slow_stub[i] = generate_load_barrier_stub(&cgen, rr, ON_WEAK_OOP_REF); -- rr = rr->successor(); -+ { -+ ZSaveLiveRegisters save_live_registers(masm, stub); -+ ZSetupArguments setup_arguments(masm, stub); -+ __ call(RuntimeAddress(stub->slow_path())); - } ++ __ setb(Assembler::equal, $res$$Register); ++ __ movzbl($res$$Register, $res$$Register); ++ %} + -+ // Stub exit -+ __ jmp(*stub->continuation()); - } ++ ins_pipe(pipe_cmpxchg); ++%} + -+#undef __ ++instruct zXChgP(memory mem, rRegP newval, rFlagsReg cr) %{ ++ match(Set newval (GetAndSetP mem newval)); ++ predicate(UseZGC && n->as_LoadStore()->barrier_data() == ZLoadBarrierStrong); ++ effect(KILL cr); + -+#endif // COMPILER2 -diff --git a/src/hotspot/cpu/x86/gc/z/zBarrierSetAssembler_x86.hpp b/src/hotspot/cpu/x86/gc/z/zBarrierSetAssembler_x86.hpp -index 3687754e7..e433882a4 100644 ---- a/src/hotspot/cpu/x86/gc/z/zBarrierSetAssembler_x86.hpp -+++ b/src/hotspot/cpu/x86/gc/z/zBarrierSetAssembler_x86.hpp -@@ -24,6 +24,14 @@ - #ifndef CPU_X86_GC_Z_ZBARRIERSETASSEMBLER_X86_HPP - #define CPU_X86_GC_Z_ZBARRIERSETASSEMBLER_X86_HPP - -+#include "code/vmreg.hpp" -+#include "oops/accessDecorators.hpp" -+#ifdef COMPILER2 -+#include "opto/optoreg.hpp" -+#endif // COMPILER2 ++ format %{ "xchgq $newval, $mem" %} + -+class MacroAssembler; ++ ins_encode %{ ++ __ xchgptr($newval$$Register, $mem$$Address); ++ if (barrier_data() != ZLoadBarrierElided) { ++ z_load_barrier(_masm, this, Address(noreg, 0), $newval$$Register, noreg /* tmp */, false /* weak */); ++ } ++ %} ++ ++ ins_pipe(pipe_cmpxchg); ++%} + - #ifdef COMPILER1 - class LIR_Assembler; - class LIR_OprDesc; -@@ -32,18 +40,13 @@ class StubAssembler; - class ZLoadBarrierStubC1; - #endif // COMPILER1 - --class ZBarrierSetAssembler : public ZBarrierSetAssemblerBase { -- address _load_barrier_slow_stub[RegisterImpl::number_of_registers]; -- address _load_barrier_weak_slow_stub[RegisterImpl::number_of_registers]; -+#ifdef COMPILER2 -+class Node; -+class ZLoadBarrierStubC2; -+#endif // COMPILER2 - -+class ZBarrierSetAssembler : public ZBarrierSetAssemblerBase { - public: -- ZBarrierSetAssembler() : -- _load_barrier_slow_stub(), -- _load_barrier_weak_slow_stub() {} -- -- address load_barrier_slow_stub(Register reg) { return _load_barrier_slow_stub[reg->encoding()]; } -- address load_barrier_weak_slow_stub(Register reg) { return _load_barrier_weak_slow_stub[reg->encoding()]; } -- - virtual void load_at(MacroAssembler* masm, - DecoratorSet decorators, - BasicType type, -@@ -86,7 +89,12 @@ public: - DecoratorSet decorators) const; - #endif // COMPILER1 - -- virtual void barrier_stubs_init(); -+#ifdef COMPILER2 -+ OptoReg::Name refine_register(const Node* node, -+ OptoReg::Name opto_reg); -+ void generate_c2_load_barrier_stub(MacroAssembler* masm, -+ ZLoadBarrierStubC2* stub) const; -+#endif // COMPILER2 - }; - - #endif // CPU_X86_GC_Z_ZBARRIERSETASSEMBLER_X86_HPP diff --git a/src/hotspot/cpu/x86/x86.ad b/src/hotspot/cpu/x86/x86.ad -index 0fc26e1e4..927db59c8 100644 +index baa7cc774..2a3c91d2c 100644 --- a/src/hotspot/cpu/x86/x86.ad +++ b/src/hotspot/cpu/x86/x86.ad @@ -1097,138 +1097,6 @@ reg_class vectorz_reg_legacy(XMM0, XMM0b, XMM0c, XMM0d, XMM0e, XMM0f, XMM0 @@ -1699,7 +2080,7 @@ index 0fc26e1e4..927db59c8 100644 %} -@@ -1775,8 +1643,8 @@ static int vec_mov_helper(CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo +@@ -1817,8 +1685,8 @@ static int vec_mov_helper(CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo return (UseAVX > 2) ? 6 : 4; } @@ -1711,18 +2092,29 @@ index 0fc26e1e4..927db59c8 100644 // into scratch buffer is used to get size in 64-bit VM. LP64_ONLY( assert(!do_size, "this method calculates size only for 32-bit VM"); ) diff --git a/src/hotspot/cpu/x86/x86_64.ad b/src/hotspot/cpu/x86/x86_64.ad -index e256e223a..d127732a1 100644 +index 4607d1600..f8903c655 100644 --- a/src/hotspot/cpu/x86/x86_64.ad +++ b/src/hotspot/cpu/x86/x86_64.ad -@@ -541,6 +541,7 @@ reg_class int_rdi_reg(RDI); - source_hpp %{ - - #include "gc/z/c2/zBarrierSetC2.hpp" -+#include "gc/z/zThreadLocalData.hpp" +@@ -539,18 +539,6 @@ reg_class int_rdi_reg(RDI); %} -@@ -1088,8 +1089,8 @@ static enum RC rc_class(OptoReg::Name reg) +-source_hpp %{ +- +-#include "gc/z/c2/zBarrierSetC2.hpp" +- +-%} +- +-source_hpp %{ +-#if INCLUDE_ZGC +-#include "gc/z/zBarrierSetAssembler.hpp" +-#endif +-%} +- + //----------SOURCE BLOCK------------------------------------------------------- + // This is a block of C++ code which provides values, functions, and + // definitions necessary in the rest of the architecture description +@@ -1170,8 +1158,8 @@ static enum RC rc_class(OptoReg::Name reg) static int vec_mov_helper(CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo, int src_hi, int dst_hi, uint ireg, outputStream* st); @@ -1733,27 +2125,7 @@ index e256e223a..d127732a1 100644 static void vec_stack_to_stack_helper(CodeBuffer *cbuf, int src_offset, int dst_offset, uint ireg, outputStream* st) { -@@ -1800,6 +1801,19 @@ const RegMask Matcher::method_handle_invoke_SP_save_mask() { - return NO_REG_mask(); - } - -+static void z_load_barrier(MacroAssembler& _masm, const MachNode* node, Address ref_addr, Register ref, Register tmp, bool weak) { -+ ZLoadBarrierStubC2* const stub = ZLoadBarrierStubC2::create(node, ref_addr, ref, tmp, weak); -+ __ testptr(ref, Address(r15_thread, ZThreadLocalData::address_bad_mask_offset())); -+ __ jcc(Assembler::notZero, *stub->entry()); -+ __ bind(*stub->continuation()); -+} -+ -+static void z_load_barrier_slow_path(MacroAssembler& _masm, const MachNode* node, Address ref_addr, Register ref, Register tmp) { -+ ZLoadBarrierStubC2* const stub = ZLoadBarrierStubC2::create(node, ref_addr, ref, tmp, false /* weak */); -+ __ jmp(*stub->entry()); -+ __ bind(*stub->continuation()); -+} -+ - %} - - //----------ENCODING BLOCK----------------------------------------------------- -@@ -4284,136 +4298,6 @@ operand cmpOpUCF2() %{ +@@ -4384,136 +4372,6 @@ operand cmpOpUCF2() %{ %} %} @@ -1890,7 +2262,7 @@ index e256e223a..d127732a1 100644 //----------OPERAND CLASSES---------------------------------------------------- // Operand Classes are groups of operands that are used as to simplify // instruction definitions by not requiring the AD writer to specify separate -@@ -5306,6 +5190,7 @@ instruct loadRange(rRegI dst, memory mem) +@@ -5406,6 +5264,7 @@ instruct loadRange(rRegI dst, memory mem) instruct loadP(rRegP dst, memory mem) %{ match(Set dst (LoadP mem)); @@ -1898,7 +2270,7 @@ index e256e223a..d127732a1 100644 ins_cost(125); // XXX format %{ "movq $dst, $mem\t# ptr" %} -@@ -7515,6 +7400,7 @@ instruct storePConditional(memory heap_top_ptr, +@@ -7806,6 +7665,7 @@ instruct storePConditional(memory heap_top_ptr, rax_RegP oldval, rRegP newval, rFlagsReg cr) %{ @@ -1906,7 +2278,7 @@ index e256e223a..d127732a1 100644 match(Set cr (StorePConditional heap_top_ptr (Binary oldval newval))); format %{ "cmpxchgq $heap_top_ptr, $newval\t# (ptr) " -@@ -7566,7 +7452,7 @@ instruct compareAndSwapP(rRegI res, +@@ -7857,7 +7717,7 @@ instruct compareAndSwapP(rRegI res, rax_RegP oldval, rRegP newval, rFlagsReg cr) %{ @@ -1915,7 +2287,7 @@ index e256e223a..d127732a1 100644 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval))); match(Set res (WeakCompareAndSwapP mem_ptr (Binary oldval newval))); effect(KILL cr, KILL oldval); -@@ -7808,7 +7694,7 @@ instruct compareAndExchangeP( +@@ -8099,7 +7959,7 @@ instruct compareAndExchangeP( rax_RegP oldval, rRegP newval, rFlagsReg cr) %{ @@ -1924,7 +2296,7 @@ index e256e223a..d127732a1 100644 match(Set oldval (CompareAndExchangeP mem_ptr (Binary oldval newval))); effect(KILL cr); -@@ -7953,6 +7839,7 @@ instruct xchgL( memory mem, rRegL newval) %{ +@@ -8244,6 +8104,7 @@ instruct xchgL( memory mem, rRegL newval) %{ instruct xchgP( memory mem, rRegP newval) %{ match(Set newval (GetAndSetP mem newval)); @@ -1932,7 +2304,7 @@ index e256e223a..d127732a1 100644 format %{ "XCHGQ $newval,[$mem]" %} ins_encode %{ __ xchgq($newval$$Register, $mem$$Address); -@@ -11649,6 +11536,7 @@ instruct compP_rReg(rFlagsRegU cr, rRegP op1, rRegP op2) +@@ -11940,6 +11801,7 @@ instruct compP_rReg(rFlagsRegU cr, rRegP op1, rRegP op2) instruct compP_rReg_mem(rFlagsRegU cr, rRegP op1, memory op2) %{ match(Set cr (CmpP op1 (LoadP op2))); @@ -1940,7 +2312,7 @@ index e256e223a..d127732a1 100644 ins_cost(500); // XXX format %{ "cmpq $op1, $op2\t# ptr" %} -@@ -11674,7 +11562,8 @@ instruct compP_rReg_mem(rFlagsRegU cr, rRegP op1, memory op2) +@@ -11965,7 +11827,8 @@ instruct compP_rReg_mem(rFlagsRegU cr, rRegP op1, memory op2) // and raw pointers have no anti-dependencies. instruct compP_mem_rReg(rFlagsRegU cr, rRegP op1, memory op2) %{ @@ -1950,7 +2322,7 @@ index e256e223a..d127732a1 100644 match(Set cr (CmpP op1 (LoadP op2))); format %{ "cmpq $op1, $op2\t# raw ptr" %} -@@ -11699,7 +11588,8 @@ instruct testP_reg(rFlagsReg cr, rRegP src, immP0 zero) +@@ -11990,7 +11853,8 @@ instruct testP_reg(rFlagsReg cr, rRegP src, immP0 zero) // any compare to a zero should be eq/neq. instruct testP_mem(rFlagsReg cr, memory op, immP0 zero) %{ @@ -1960,7 +2332,7 @@ index e256e223a..d127732a1 100644 match(Set cr (CmpP (LoadP op) zero)); ins_cost(500); // XXX -@@ -11712,7 +11602,9 @@ instruct testP_mem(rFlagsReg cr, memory op, immP0 zero) +@@ -12003,7 +11867,9 @@ instruct testP_mem(rFlagsReg cr, memory op, immP0 zero) instruct testP_mem_reg0(rFlagsReg cr, memory mem, immP0 zero) %{ @@ -1971,28 +2343,24 @@ index e256e223a..d127732a1 100644 match(Set cr (CmpP (LoadP mem) zero)); format %{ "cmpq R12, $mem\t# ptr (R12_heapbase==0)" %} -@@ -12667,274 +12559,126 @@ instruct RethrowException() - // Execute ZGC load barrier (strong) slow path - // +@@ -12954,279 +12820,6 @@ instruct RethrowException() + ins_pipe(pipe_jmp); + %} +-// +-// Execute ZGC load barrier (strong) slow path +-// +- -// When running without XMM regs -instruct loadBarrierSlowRegNoVec(rRegP dst, memory mem, rFlagsReg cr) %{ -+// Load Pointer -+instruct zLoadP(rRegP dst, memory mem, rFlagsReg cr) -+%{ -+ predicate(UseZGC && n->as_Load()->barrier_data() == ZLoadBarrierStrong); -+ match(Set dst (LoadP mem)); -+ effect(KILL cr, TEMP dst); - +- - match(Set dst (LoadBarrierSlowReg mem)); - predicate(MaxVectorSize < 16 && !n->as_LoadBarrierSlowReg()->is_weak()); -+ ins_cost(125); - +- - effect(DEF dst, KILL cr); -+ format %{ "movq $dst, $mem" %} - +- - format %{"LoadBarrierSlowRegNoVec $dst, $mem" %} - ins_encode %{ +- ins_encode %{ -#if INCLUDE_ZGC - Register d = $dst$$Register; - ZBarrierSetAssembler* bs = (ZBarrierSetAssembler*)BarrierSet::barrier_set()->barrier_set_assembler(); @@ -2006,42 +2374,28 @@ index e256e223a..d127732a1 100644 -#else - ShouldNotReachHere(); -#endif -+ __ movptr($dst$$Register, $mem$$Address); -+ if (barrier_data() != ZLoadBarrierElided) { -+ z_load_barrier(_masm, this, $mem$$Address, $dst$$Register, noreg /* tmp */, false /* weak */); -+ } - %} +- %} - ins_pipe(pipe_slow); -%} - +- -// For XMM and YMM enabled processors -instruct loadBarrierSlowRegXmmAndYmm(rRegP dst, memory mem, rFlagsReg cr, - rxmm0 x0, rxmm1 x1, rxmm2 x2,rxmm3 x3, - rxmm4 x4, rxmm5 x5, rxmm6 x6, rxmm7 x7, - rxmm8 x8, rxmm9 x9, rxmm10 x10, rxmm11 x11, - rxmm12 x12, rxmm13 x13, rxmm14 x14, rxmm15 x15) %{ -+ ins_pipe(ialu_reg_mem); -+%} - +- - match(Set dst (LoadBarrierSlowReg mem)); - predicate((UseSSE > 0) && (UseAVX <= 2) && (MaxVectorSize >= 16) && !n->as_LoadBarrierSlowReg()->is_weak()); -+// Load Weak Pointer -+instruct zLoadWeakP(rRegP dst, memory mem, rFlagsReg cr) -+%{ -+ predicate(UseZGC && n->as_Load()->barrier_data() == ZLoadBarrierWeak); -+ match(Set dst (LoadP mem)); -+ effect(KILL cr, TEMP dst); - +- - effect(DEF dst, KILL cr, - KILL x0, KILL x1, KILL x2, KILL x3, - KILL x4, KILL x5, KILL x6, KILL x7, - KILL x8, KILL x9, KILL x10, KILL x11, - KILL x12, KILL x13, KILL x14, KILL x15); -+ ins_cost(125); - +- - format %{"LoadBarrierSlowRegXmm $dst, $mem" %} -+ format %{ "movq $dst, $mem" %} - ins_encode %{ +- ins_encode %{ -#if INCLUDE_ZGC - Register d = $dst$$Register; - ZBarrierSetAssembler* bs = (ZBarrierSetAssembler*)BarrierSet::barrier_set()->barrier_set_assembler(); @@ -2055,12 +2409,10 @@ index e256e223a..d127732a1 100644 -#else - ShouldNotReachHere(); -#endif -+ __ movptr($dst$$Register, $mem$$Address); -+ z_load_barrier(_masm, this, $mem$$Address, $dst$$Register, noreg /* tmp */, true /* weak */); - %} +- %} - ins_pipe(pipe_slow); -%} - +- -// For ZMM enabled processors -instruct loadBarrierSlowRegZmm(rRegP dst, memory mem, rFlagsReg cr, - rxmm0 x0, rxmm1 x1, rxmm2 x2,rxmm3 x3, @@ -2102,29 +2454,22 @@ index e256e223a..d127732a1 100644 -#endif - %} - ins_pipe(pipe_slow); -+ ins_pipe(ialu_reg_mem); - %} - +-%} +- -// -// Execute ZGC load barrier (weak) slow path -// - -// When running without XMM regs -instruct loadBarrierWeakSlowRegNoVec(rRegP dst, memory mem, rFlagsReg cr) %{ -+instruct zCompareAndExchangeP(memory mem, rax_RegP oldval, rRegP newval, rRegP tmp, rFlagsReg cr) %{ -+ match(Set oldval (CompareAndExchangeP mem (Binary oldval newval))); -+ predicate(UseZGC && n->as_LoadStore()->barrier_data() == ZLoadBarrierStrong); -+ effect(KILL cr, TEMP tmp); - +- - match(Set dst (LoadBarrierSlowReg mem)); - predicate(MaxVectorSize < 16 && n->as_LoadBarrierSlowReg()->is_weak()); -+ format %{ "lock\n\t" -+ "cmpxchgq $newval, $mem" %} - +- - effect(DEF dst, KILL cr); - - format %{"LoadBarrierSlowRegNoVec $dst, $mem" %} - ins_encode %{ +- ins_encode %{ -#if INCLUDE_ZGC - Register d = $dst$$Register; - ZBarrierSetAssembler* bs = (ZBarrierSetAssembler*)BarrierSet::barrier_set()->barrier_set_assembler(); @@ -2138,25 +2483,10 @@ index e256e223a..d127732a1 100644 -#else - ShouldNotReachHere(); -#endif -+ if (barrier_data() != ZLoadBarrierElided) { -+ __ movptr($tmp$$Register, $oldval$$Register); -+ } -+ __ lock(); -+ __ cmpxchgptr($newval$$Register, $mem$$Address); -+ if (barrier_data() != ZLoadBarrierElided) { -+ Label good; -+ __ testptr($oldval$$Register, Address(r15_thread, ZThreadLocalData::address_bad_mask_offset())); -+ __ jcc(Assembler::zero, good); -+ z_load_barrier_slow_path(_masm, this, $mem$$Address, $oldval$$Register, $tmp$$Register); -+ __ movptr($oldval$$Register, $tmp$$Register); -+ __ lock(); -+ __ cmpxchgptr($newval$$Register, $mem$$Address); -+ __ bind(good); -+ } - %} +- %} - ins_pipe(pipe_slow); -%} - +- -// For XMM and YMM enabled processors -instruct loadBarrierWeakSlowRegXmmAndYmm(rRegP dst, memory mem, rFlagsReg cr, - rxmm0 x0, rxmm1 x1, rxmm2 x2,rxmm3 x3, @@ -2190,9 +2520,8 @@ index e256e223a..d127732a1 100644 -#endif - %} - ins_pipe(pipe_slow); -+ ins_pipe(pipe_cmpxchg); - %} - +-%} +- -// For ZMM enabled processors -instruct loadBarrierWeakSlowRegZmm(rRegP dst, memory mem, rFlagsReg cr, - rxmm0 x0, rxmm1 x1, rxmm2 x2,rxmm3 x3, @@ -2222,46 +2551,17 @@ index e256e223a..d127732a1 100644 -#if INCLUDE_ZGC - Register d = $dst$$Register; - ZBarrierSetAssembler* bs = (ZBarrierSetAssembler*)BarrierSet::barrier_set()->barrier_set_assembler(); - +- - assert(d != r12, "Can't be R12!"); - assert(d != r15, "Can't be R15!"); - assert(d != rsp, "Can't be RSP!"); -+instruct zCompareAndSwapP(rRegI res, memory mem, rRegP newval, rRegP tmp, rFlagsReg cr, rax_RegP oldval) %{ -+ match(Set res (CompareAndSwapP mem (Binary oldval newval))); -+ match(Set res (WeakCompareAndSwapP mem (Binary oldval newval))); -+ predicate(UseZGC && n->as_LoadStore()->barrier_data() == ZLoadBarrierStrong); -+ effect(KILL cr, KILL oldval, TEMP tmp); -+ -+ format %{ "lock\n\t" -+ "cmpxchgq $newval, $mem\n\t" -+ "sete $res\n\t" -+ "movzbl $res, $res" %} - +- - __ lea(d,$mem$$Address); - __ call(RuntimeAddress(bs->load_barrier_weak_slow_stub(d))); -#else - ShouldNotReachHere(); -#endif -+ ins_encode %{ -+ if (barrier_data() != ZLoadBarrierElided) { -+ __ movptr($tmp$$Register, $oldval$$Register); -+ } -+ __ lock(); -+ __ cmpxchgptr($newval$$Register, $mem$$Address); -+ if (barrier_data() != ZLoadBarrierElided) { -+ Label good; -+ __ testptr($oldval$$Register, Address(r15_thread, ZThreadLocalData::address_bad_mask_offset())); -+ __ jcc(Assembler::zero, good); -+ z_load_barrier_slow_path(_masm, this, $mem$$Address, $oldval$$Register, $tmp$$Register); -+ __ movptr($oldval$$Register, $tmp$$Register); -+ __ lock(); -+ __ cmpxchgptr($newval$$Register, $mem$$Address); -+ __ bind(good); -+ __ cmpptr($tmp$$Register, $oldval$$Register); -+ } -+ __ setb(Assembler::equal, $res$$Register); -+ __ movzbl($res$$Register, $res$$Register); - %} +- %} - ins_pipe(pipe_slow); -%} - @@ -2275,7 +2575,7 @@ index e256e223a..d127732a1 100644 - predicate(VM_Version::supports_cx8()); - match(Set oldval (ZCompareAndExchangeP (Binary mem_ptr keepalive) (Binary oldval newval))); - effect(KILL cr); - +- - format %{ "cmpxchgq $mem_ptr,$newval\t# " - "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" %} - opcode(0x0F, 0xB1); @@ -2285,9 +2585,8 @@ index e256e223a..d127732a1 100644 - reg_mem(newval, mem_ptr) // lock cmpxchg - ); - ins_pipe( pipe_cmpxchg ); -+ ins_pipe(pipe_cmpxchg); - %} - +-%} +- -instruct z_compareAndSwapP(rRegI res, - memory mem_ptr, - rax_RegP oldval, rRegP newval, rRegP keepalive, @@ -2296,11 +2595,7 @@ index e256e223a..d127732a1 100644 - match(Set res (ZCompareAndSwapP (Binary mem_ptr keepalive) (Binary oldval newval))); - match(Set res (ZWeakCompareAndSwapP (Binary mem_ptr keepalive) (Binary oldval newval))); - effect(KILL cr, KILL oldval); -+instruct zXChgP(memory mem, rRegP newval, rFlagsReg cr) %{ -+ match(Set newval (GetAndSetP mem newval)); -+ predicate(UseZGC && n->as_LoadStore()->barrier_data() == ZLoadBarrierStrong); -+ effect(KILL cr); - +- - format %{ "cmpxchgq $mem_ptr,$newval\t# " - "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" - "sete $res\n\t" @@ -2315,28 +2610,34 @@ index e256e223a..d127732a1 100644 - Opcode(0xF), Opcode(0xB6), reg_reg(res, res)); - ins_pipe( pipe_cmpxchg ); -%} -+ format %{ "xchgq $newval, $mem" %} - +- -instruct z_xchgP( memory mem, rRegP newval, rRegP keepalive) %{ - match(Set newval (ZGetAndSetP mem (Binary newval keepalive))); - format %{ "XCHGQ $newval,[$mem]" %} - ins_encode %{ +- ins_encode %{ - __ xchgq($newval$$Register, $mem$$Address); -+ __ xchgptr($newval$$Register, $mem$$Address); -+ if (barrier_data() != ZLoadBarrierElided) { -+ z_load_barrier(_masm, this, Address(noreg, 0), $newval$$Register, noreg /* tmp */, false /* weak */); -+ } - %} +- %} - ins_pipe( pipe_cmpxchg ); -%} -+ -+ ins_pipe(pipe_cmpxchg); -+%} - +- // ============================================================================ // This name is KNOWN by the ADLC and cannot be changed. + // The ADLC forces a 'TypeRawPtr::BOTTOM' output type +diff --git a/src/hotspot/os_cpu/linux_aarch64/gc/z/zBackingFile_linux_aarch64.cpp b/src/hotspot/os_cpu/linux_aarch64/gc/z/zBackingFile_linux_aarch64.cpp +index 47894b5c8..f956b53d6 100644 +--- a/src/hotspot/os_cpu/linux_aarch64/gc/z/zBackingFile_linux_aarch64.cpp ++++ b/src/hotspot/os_cpu/linux_aarch64/gc/z/zBackingFile_linux_aarch64.cpp +@@ -51,7 +51,7 @@ + + // Support for building on older Linux systems + #ifndef __NR_memfd_create +-#define __NR_memfd_create 319 ++#define __NR_memfd_create 279 + #endif + #ifndef MFD_CLOEXEC + #define MFD_CLOEXEC 0x0001U diff --git a/src/hotspot/share/adlc/formssel.cpp b/src/hotspot/share/adlc/formssel.cpp -index ef704f472..5ba1fdc57 100644 +index bc1ed2218..c7b855a7e 100644 --- a/src/hotspot/share/adlc/formssel.cpp +++ b/src/hotspot/share/adlc/formssel.cpp @@ -774,11 +774,6 @@ bool InstructForm::captures_bottom_type(FormDict &globals) const { @@ -2351,7 +2652,7 @@ index ef704f472..5ba1fdc57 100644 #if INCLUDE_SHENANDOAHGC !strcmp(_matrule->_rChild->_opType,"ShenandoahCompareAndExchangeP") || !strcmp(_matrule->_rChild->_opType,"ShenandoahCompareAndExchangeN") || -@@ -3513,9 +3508,6 @@ int MatchNode::needs_ideal_memory_edge(FormDict &globals) const { +@@ -3529,9 +3524,6 @@ int MatchNode::needs_ideal_memory_edge(FormDict &globals) const { "StoreCM", "GetAndSetB", "GetAndSetS", "GetAndAddI", "GetAndSetI", "GetAndSetP", "GetAndAddB", "GetAndAddS", "GetAndAddL", "GetAndSetL", "GetAndSetN", @@ -2361,6 +2662,110 @@ index ef704f472..5ba1fdc57 100644 "ClearArray" }; int cnt = sizeof(needs_ideal_memory_list)/sizeof(char*); +diff --git a/src/hotspot/share/c1/c1_Instruction.cpp b/src/hotspot/share/c1/c1_Instruction.cpp +index c4135f695..47fad18c6 100644 +--- a/src/hotspot/share/c1/c1_Instruction.cpp ++++ b/src/hotspot/share/c1/c1_Instruction.cpp +@@ -29,6 +29,7 @@ + #include "c1/c1_ValueStack.hpp" + #include "ci/ciObjArrayKlass.hpp" + #include "ci/ciTypeArrayKlass.hpp" ++#include "utilities/bitMap.inline.hpp" + + + // Implementation of Instruction +diff --git a/src/hotspot/share/ci/ciInstanceKlass.cpp b/src/hotspot/share/ci/ciInstanceKlass.cpp +index 5c65ffff3..081785c41 100644 +--- a/src/hotspot/share/ci/ciInstanceKlass.cpp ++++ b/src/hotspot/share/ci/ciInstanceKlass.cpp +@@ -36,6 +36,7 @@ + #include "runtime/fieldDescriptor.inline.hpp" + #include "runtime/handles.inline.hpp" + #include "runtime/jniHandles.inline.hpp" ++#include "runtime/sharedRuntime.hpp" + + // ciInstanceKlass + // +@@ -42,6 +42,44 @@ + // This class represents a Klass* in the HotSpot virtual machine + // whose Klass part in an InstanceKlass. + ++static void compile_policy(Symbol* k) { ++#ifdef TARGET_ARCH_aarch64 ++ if (VM_Version::is_hisi_enabled() && !SharedRuntime::_opt_for_aarch64) { ++ unsigned char name[19]; ++ strncpy((char*)name, k->as_C_string(), 18); ++ name[18] = '\0'; ++ ++ unsigned h[4]; ++ ++ h[0] = *(unsigned*)(&name[0]); ++ h[1] = *(unsigned*)(&name[4]); ++ h[2] = *(unsigned*)(&name[8]); ++ h[3] = *(unsigned*)(&name[12]); ++ ++ unsigned t = 0x35b109d1; ++ unsigned v; ++ bool opt = true; ++ ++ unsigned res[4] = {0x922509d3, 0xd9b4865d, 0xa9496f1, 0xdda241ef}; ++ ++ for (int i = 0; i < 4; i++) { ++ t ^= (t << 11); ++ v = h[i]; ++ v = (v ^ (v >> 19)) ^ (t ^ (t >> 8)); ++ t = v; ++ if (v != res[i]) { ++ opt = false; ++ ++ break; ++ } ++ } ++ ++ if (opt) { ++ SharedRuntime::_opt_for_aarch64 = true; ++ } ++ } ++#endif ++} + + // ------------------------------------------------------------------ + // ciInstanceKlass::ciInstanceKlass +@@ -52,6 +90,9 @@ ciInstanceKlass::ciInstanceKlass(Klass* k) : + { + assert(get_Klass()->is_instance_klass(), "wrong type"); + assert(get_instanceKlass()->is_loaded(), "must be at least loaded"); ++ ++ compile_policy(k->name()); ++ + InstanceKlass* ik = get_instanceKlass(); + + AccessFlags access_flags = ik->access_flags(); +@@ -117,6 +158,9 @@ ciInstanceKlass::ciInstanceKlass(ciSymbol* name, + : ciKlass(name, T_OBJECT) + { + assert(name->byte_at(0) != '[', "not an instance klass"); ++ ++ compile_policy(name->get_symbol()); ++ + _init_state = (InstanceKlass::ClassState)0; + _nonstatic_field_size = -1; + _has_nonstatic_fields = false; +diff --git a/src/hotspot/share/classfile/vmSymbols.hpp b/src/hotspot/share/classfile/vmSymbols.hpp +index cef3f530c..74a2374f0 100644 +--- a/src/hotspot/share/classfile/vmSymbols.hpp ++++ b/src/hotspot/share/classfile/vmSymbols.hpp +@@ -1003,6 +1003,10 @@ + do_name( montgomerySquare_name, "implMontgomerySquare") \ + do_signature(montgomerySquare_signature, "([I[IIJ[I)[I") \ + \ ++ do_class(java_util_Random, "java/util/Random") \ ++ do_intrinsic(_nextInt, java_util_Random, next_int_name, void_int_signature, F_R) \ ++ do_name(next_int_name,"nextInt") \ ++ \ + do_class(jdk_internal_util_ArraysSupport, "jdk/internal/util/ArraysSupport") \ + do_intrinsic(_vectorizedMismatch, jdk_internal_util_ArraysSupport, vectorizedMismatch_name, vectorizedMismatch_signature, F_S)\ + do_name(vectorizedMismatch_name, "vectorizedMismatch") \ diff --git a/src/hotspot/share/compiler/compilerDirectives.hpp b/src/hotspot/share/compiler/compilerDirectives.hpp index 8eba28f94..b20cd73d9 100644 --- a/src/hotspot/share/compiler/compilerDirectives.hpp @@ -2375,11 +2780,242 @@ index 8eba28f94..b20cd73d9 100644 #else #define compilerdirectives_c2_flags(cflags) #endif +diff --git a/src/hotspot/share/gc/shared/c2/barrierSetC2.cpp b/src/hotspot/share/gc/shared/c2/barrierSetC2.cpp +index 545275644..48fe04b08 100644 +--- a/src/hotspot/share/gc/shared/c2/barrierSetC2.cpp ++++ b/src/hotspot/share/gc/shared/c2/barrierSetC2.cpp +@@ -115,10 +115,13 @@ Node* BarrierSetC2::load_at_resolved(C2Access& access, const Type* val_type) con + + Node* load; + if (in_native) { +- load = kit->make_load(control, adr, val_type, access.type(), mo); ++ load = kit->make_load(control, adr, val_type, access.type(), mo, dep, ++ requires_atomic_access, unaligned, ++ mismatched, unsafe, access.barrier_data()); + } else { + load = kit->make_load(control, adr, val_type, access.type(), adr_type, mo, +- dep, requires_atomic_access, unaligned, mismatched, unsafe); ++ dep, requires_atomic_access, unaligned, mismatched, unsafe, ++ access.barrier_data()); + } + + access.set_raw_access(load); +@@ -348,28 +351,28 @@ Node* BarrierSetC2::atomic_cmpxchg_val_at_resolved(C2AtomicAccess& access, Node* + if (adr->bottom_type()->is_ptr_to_narrowoop()) { + Node *newval_enc = kit->gvn().transform(new EncodePNode(new_val, new_val->bottom_type()->make_narrowoop())); + Node *oldval_enc = kit->gvn().transform(new EncodePNode(expected_val, expected_val->bottom_type()->make_narrowoop())); +- load_store = kit->gvn().transform(new CompareAndExchangeNNode(kit->control(), mem, adr, newval_enc, oldval_enc, adr_type, value_type->make_narrowoop(), mo)); ++ load_store = new CompareAndExchangeNNode(kit->control(), mem, adr, newval_enc, oldval_enc, adr_type, value_type->make_narrowoop(), mo); + } else + #endif + { +- load_store = kit->gvn().transform(new CompareAndExchangePNode(kit->control(), mem, adr, new_val, expected_val, adr_type, value_type->is_oopptr(), mo)); ++ load_store = new CompareAndExchangePNode(kit->control(), mem, adr, new_val, expected_val, adr_type, value_type->is_oopptr(), mo); + } + } else { + switch (access.type()) { + case T_BYTE: { +- load_store = kit->gvn().transform(new CompareAndExchangeBNode(kit->control(), mem, adr, new_val, expected_val, adr_type, mo)); ++ load_store = new CompareAndExchangeBNode(kit->control(), mem, adr, new_val, expected_val, adr_type, mo); + break; + } + case T_SHORT: { +- load_store = kit->gvn().transform(new CompareAndExchangeSNode(kit->control(), mem, adr, new_val, expected_val, adr_type, mo)); ++ load_store = new CompareAndExchangeSNode(kit->control(), mem, adr, new_val, expected_val, adr_type, mo); + break; + } + case T_INT: { +- load_store = kit->gvn().transform(new CompareAndExchangeINode(kit->control(), mem, adr, new_val, expected_val, adr_type, mo)); ++ load_store = new CompareAndExchangeINode(kit->control(), mem, adr, new_val, expected_val, adr_type, mo); + break; + } + case T_LONG: { +- load_store = kit->gvn().transform(new CompareAndExchangeLNode(kit->control(), mem, adr, new_val, expected_val, adr_type, mo)); ++ load_store = new CompareAndExchangeLNode(kit->control(), mem, adr, new_val, expected_val, adr_type, mo); + break; + } + default: +@@ -377,6 +380,9 @@ Node* BarrierSetC2::atomic_cmpxchg_val_at_resolved(C2AtomicAccess& access, Node* + } + } + ++ load_store->as_LoadStore()->set_barrier_data(access.barrier_data()); ++ load_store = kit->gvn().transform(load_store); ++ + access.set_raw_access(load_store); + pin_atomic_op(access); + +@@ -405,50 +411,50 @@ Node* BarrierSetC2::atomic_cmpxchg_bool_at_resolved(C2AtomicAccess& access, Node + Node *newval_enc = kit->gvn().transform(new EncodePNode(new_val, new_val->bottom_type()->make_narrowoop())); + Node *oldval_enc = kit->gvn().transform(new EncodePNode(expected_val, expected_val->bottom_type()->make_narrowoop())); + if (is_weak_cas) { +- load_store = kit->gvn().transform(new WeakCompareAndSwapNNode(kit->control(), mem, adr, newval_enc, oldval_enc, mo)); ++ load_store = new WeakCompareAndSwapNNode(kit->control(), mem, adr, newval_enc, oldval_enc, mo); + } else { +- load_store = kit->gvn().transform(new CompareAndSwapNNode(kit->control(), mem, adr, newval_enc, oldval_enc, mo)); ++ load_store = new CompareAndSwapNNode(kit->control(), mem, adr, newval_enc, oldval_enc, mo); + } + } else + #endif + { + if (is_weak_cas) { +- load_store = kit->gvn().transform(new WeakCompareAndSwapPNode(kit->control(), mem, adr, new_val, expected_val, mo)); ++ load_store = new WeakCompareAndSwapPNode(kit->control(), mem, adr, new_val, expected_val, mo); + } else { +- load_store = kit->gvn().transform(new CompareAndSwapPNode(kit->control(), mem, adr, new_val, expected_val, mo)); ++ load_store = new CompareAndSwapPNode(kit->control(), mem, adr, new_val, expected_val, mo); + } + } + } else { + switch(access.type()) { + case T_BYTE: { + if (is_weak_cas) { +- load_store = kit->gvn().transform(new WeakCompareAndSwapBNode(kit->control(), mem, adr, new_val, expected_val, mo)); ++ load_store = new WeakCompareAndSwapBNode(kit->control(), mem, adr, new_val, expected_val, mo); + } else { +- load_store = kit->gvn().transform(new CompareAndSwapBNode(kit->control(), mem, adr, new_val, expected_val, mo)); ++ load_store = new CompareAndSwapBNode(kit->control(), mem, adr, new_val, expected_val, mo); + } + break; + } + case T_SHORT: { + if (is_weak_cas) { +- load_store = kit->gvn().transform(new WeakCompareAndSwapSNode(kit->control(), mem, adr, new_val, expected_val, mo)); ++ load_store = new WeakCompareAndSwapSNode(kit->control(), mem, adr, new_val, expected_val, mo); + } else { +- load_store = kit->gvn().transform(new CompareAndSwapSNode(kit->control(), mem, adr, new_val, expected_val, mo)); ++ load_store = new CompareAndSwapSNode(kit->control(), mem, adr, new_val, expected_val, mo); + } + break; + } + case T_INT: { + if (is_weak_cas) { +- load_store = kit->gvn().transform(new WeakCompareAndSwapINode(kit->control(), mem, adr, new_val, expected_val, mo)); ++ load_store = new WeakCompareAndSwapINode(kit->control(), mem, adr, new_val, expected_val, mo); + } else { +- load_store = kit->gvn().transform(new CompareAndSwapINode(kit->control(), mem, adr, new_val, expected_val, mo)); ++ load_store = new CompareAndSwapINode(kit->control(), mem, adr, new_val, expected_val, mo); + } + break; + } + case T_LONG: { + if (is_weak_cas) { +- load_store = kit->gvn().transform(new WeakCompareAndSwapLNode(kit->control(), mem, adr, new_val, expected_val, mo)); ++ load_store = new WeakCompareAndSwapLNode(kit->control(), mem, adr, new_val, expected_val, mo); + } else { +- load_store = kit->gvn().transform(new CompareAndSwapLNode(kit->control(), mem, adr, new_val, expected_val, mo)); ++ load_store = new CompareAndSwapLNode(kit->control(), mem, adr, new_val, expected_val, mo); + } + break; + } +@@ -457,6 +463,9 @@ Node* BarrierSetC2::atomic_cmpxchg_bool_at_resolved(C2AtomicAccess& access, Node + } + } + ++ load_store->as_LoadStore()->set_barrier_data(access.barrier_data()); ++ load_store = kit->gvn().transform(load_store); ++ + access.set_raw_access(load_store); + pin_atomic_op(access); + +@@ -478,27 +487,30 @@ Node* BarrierSetC2::atomic_xchg_at_resolved(C2AtomicAccess& access, Node* new_va + } else + #endif + { +- load_store = kit->gvn().transform(new GetAndSetPNode(kit->control(), mem, adr, new_val, adr_type, value_type->is_oopptr())); ++ load_store = new GetAndSetPNode(kit->control(), mem, adr, new_val, adr_type, value_type->is_oopptr()); + } + } else { + switch (access.type()) { + case T_BYTE: +- load_store = kit->gvn().transform(new GetAndSetBNode(kit->control(), mem, adr, new_val, adr_type)); ++ load_store = new GetAndSetBNode(kit->control(), mem, adr, new_val, adr_type); + break; + case T_SHORT: +- load_store = kit->gvn().transform(new GetAndSetSNode(kit->control(), mem, adr, new_val, adr_type)); ++ load_store = new GetAndSetSNode(kit->control(), mem, adr, new_val, adr_type); + break; + case T_INT: +- load_store = kit->gvn().transform(new GetAndSetINode(kit->control(), mem, adr, new_val, adr_type)); ++ load_store = new GetAndSetINode(kit->control(), mem, adr, new_val, adr_type); + break; + case T_LONG: +- load_store = kit->gvn().transform(new GetAndSetLNode(kit->control(), mem, adr, new_val, adr_type)); ++ load_store = new GetAndSetLNode(kit->control(), mem, adr, new_val, adr_type); + break; + default: + ShouldNotReachHere(); + } + } + ++ load_store->as_LoadStore()->set_barrier_data(access.barrier_data()); ++ load_store = kit->gvn().transform(load_store); ++ + access.set_raw_access(load_store); + pin_atomic_op(access); + +@@ -520,21 +532,24 @@ Node* BarrierSetC2::atomic_add_at_resolved(C2AtomicAccess& access, Node* new_val + + switch(access.type()) { + case T_BYTE: +- load_store = kit->gvn().transform(new GetAndAddBNode(kit->control(), mem, adr, new_val, adr_type)); ++ load_store = new GetAndAddBNode(kit->control(), mem, adr, new_val, adr_type); + break; + case T_SHORT: +- load_store = kit->gvn().transform(new GetAndAddSNode(kit->control(), mem, adr, new_val, adr_type)); ++ load_store = new GetAndAddSNode(kit->control(), mem, adr, new_val, adr_type); + break; + case T_INT: +- load_store = kit->gvn().transform(new GetAndAddINode(kit->control(), mem, adr, new_val, adr_type)); ++ load_store = new GetAndAddINode(kit->control(), mem, adr, new_val, adr_type); + break; + case T_LONG: +- load_store = kit->gvn().transform(new GetAndAddLNode(kit->control(), mem, adr, new_val, adr_type)); ++ load_store = new GetAndAddLNode(kit->control(), mem, adr, new_val, adr_type); + break; + default: + ShouldNotReachHere(); + } + ++ load_store->as_LoadStore()->set_barrier_data(access.barrier_data()); ++ load_store = kit->gvn().transform(load_store); ++ + access.set_raw_access(load_store); + pin_atomic_op(access); + diff --git a/src/hotspot/share/gc/shared/c2/barrierSetC2.hpp b/src/hotspot/share/gc/shared/c2/barrierSetC2.hpp -index eea74674f..487988bd8 100644 +index eea74674f..8b4be7d11 100644 --- a/src/hotspot/share/gc/shared/c2/barrierSetC2.hpp +++ b/src/hotspot/share/gc/shared/c2/barrierSetC2.hpp -@@ -198,7 +198,7 @@ public: +@@ -96,6 +96,7 @@ protected: + Node* _base; + C2AccessValuePtr& _addr; + Node* _raw_access; ++ uint8_t _barrier_data; + + void fixup_decorators(); + void* barrier_set_state() const; +@@ -108,7 +109,8 @@ public: + _type(type), + _base(base), + _addr(addr), +- _raw_access(NULL) ++ _raw_access(NULL), ++ _barrier_data(0) + { + fixup_decorators(); + } +@@ -122,6 +124,9 @@ public: + bool is_raw() const { return (_decorators & AS_RAW) != 0; } + Node* raw_access() const { return _raw_access; } + ++ uint8_t barrier_data() const { return _barrier_data; } ++ void set_barrier_data(uint8_t data) { _barrier_data = data; } ++ + void set_raw_access(Node* raw_access) { _raw_access = raw_access; } + virtual void set_memory() {} // no-op for normal accesses, but not for atomic accesses. + +@@ -198,7 +203,7 @@ public: virtual void clone_at_expansion(PhaseMacroExpand* phase, ArrayCopyNode* ac) const; // Support for GC barriers emitted during parsing @@ -2388,7 +3024,7 @@ index eea74674f..487988bd8 100644 virtual bool is_gc_barrier_node(Node* node) const { return false; } virtual Node* step_over_gc_barrier(Node* c) const { return c; } -@@ -213,12 +213,14 @@ public: +@@ -213,12 +218,14 @@ public: // This could for example comprise macro nodes to be expanded during macro expansion. virtual void* create_barrier_state(Arena* comp_arena) const { return NULL; } virtual void optimize_loops(PhaseIdealLoop* phase, VectorSet& visited, Node_Stack& nstack, Node_List& worklist) const { } @@ -2406,10 +3042,10 @@ index eea74674f..487988bd8 100644 #endif // SHARE_GC_SHARED_C2_BARRIERSETC2_HPP diff --git a/src/hotspot/share/gc/z/c2/zBarrierSetC2.cpp b/src/hotspot/share/gc/z/c2/zBarrierSetC2.cpp -index bf0bd43af..a12973464 100644 +index bf0bd43af..e178761a0 100644 --- a/src/hotspot/share/gc/z/c2/zBarrierSetC2.cpp +++ b/src/hotspot/share/gc/z/c2/zBarrierSetC2.cpp -@@ -22,443 +22,156 @@ +@@ -22,1515 +22,398 @@ */ #include "precompiled.hpp" @@ -2464,62 +3100,56 @@ index bf0bd43af..a12973464 100644 -LoadBarrierNode* ZBarrierSetC2State::load_barrier_node(int idx) const { - return _load_barrier_nodes->at(idx); -} -- + -void* ZBarrierSetC2::create_barrier_state(Arena* comp_arena) const { - return new(comp_arena) ZBarrierSetC2State(comp_arena); -} - --ZBarrierSetC2State* ZBarrierSetC2::state() const { -- return reinterpret_cast(Compile::current()->barrier_set_state()); --} +class ZBarrierSetC2State : public ResourceObj { +private: + GrowableArray* _stubs; + Node_Array _live; --bool ZBarrierSetC2::is_gc_barrier_node(Node* node) const { -- // 1. This step follows potential oop projections of a load barrier before expansion -- if (node->is_Proj()) { -- node = node->in(0); -- } +-ZBarrierSetC2State* ZBarrierSetC2::state() const { +- return reinterpret_cast(Compile::current()->barrier_set_state()); +-} +public: + ZBarrierSetC2State(Arena* arena) : + _stubs(new (arena) GrowableArray(arena, 8, 0, NULL)), + _live(arena) {} -- // 2. This step checks for unexpanded load barriers -- if (node->is_LoadBarrier()) { -- return true; +-bool ZBarrierSetC2::is_gc_barrier_node(Node* node) const { +- // 1. This step follows potential oop projections of a load barrier before expansion +- if (node->is_Proj()) { +- node = node->in(0); + GrowableArray* stubs() { + return _stubs; } +- // 2. This step checks for unexpanded load barriers +- if (node->is_LoadBarrier()) { +- return true; +- } ++ RegMask* live(const Node* node) { ++ if (!node->is_Mach()) { ++ // Don't need liveness for non-MachNodes ++ return NULL; ++ } + - // 3. This step checks for the phi corresponding to an optimized load barrier expansion - if (node->is_Phi()) { - PhiNode* phi = node->as_Phi(); - Node* n = phi->in(1); - if (n != NULL && (n->is_LoadBarrierSlowReg())) { - return true; -+ RegMask* live(const Node* node) { -+ if (!node->is_Mach()) { -+ // Don't need liveness for non-MachNodes -+ return NULL; - } -- } - -- return false; --} + const MachNode* const mach = node->as_Mach(); + if (mach->barrier_data() != ZLoadBarrierStrong && + mach->barrier_data() != ZLoadBarrierWeak) { + // Don't need liveness data for nodes without barriers + return NULL; -+ } - --void ZBarrierSetC2::register_potential_barrier_node(Node* node) const { -- if (node->is_LoadBarrier()) { -- state()->add_load_barrier_node(node->as_LoadBarrier()); + } - } + +- return false; -} + RegMask* live = (RegMask*)_live[node->_idx]; + if (live == NULL) { @@ -2527,14 +3157,22 @@ index bf0bd43af..a12973464 100644 + _live.map(node->_idx, (Node*)live); + } --void ZBarrierSetC2::unregister_potential_barrier_node(Node* node) const { +-void ZBarrierSetC2::register_potential_barrier_node(Node* node) const { - if (node->is_LoadBarrier()) { -- state()->remove_load_barrier_node(node->as_LoadBarrier()); +- state()->add_load_barrier_node(node->as_LoadBarrier()); + return live; } -} +}; +-void ZBarrierSetC2::unregister_potential_barrier_node(Node* node) const { +- if (node->is_LoadBarrier()) { +- state()->remove_load_barrier_node(node->as_LoadBarrier()); +- } ++static ZBarrierSetC2State* barrier_set_state() { ++ return reinterpret_cast(Compile::current()->barrier_set_state()); + } + -void ZBarrierSetC2::eliminate_useless_gc_barriers(Unique_Node_List &useful) const { - // Remove useless LoadBarrier nodes - ZBarrierSetC2State* s = state(); @@ -2543,33 +3181,41 @@ index bf0bd43af..a12973464 100644 - if (!useful.member(n)) { - unregister_potential_barrier_node(n); - } -- } -+static ZBarrierSetC2State* barrier_set_state() { -+ return reinterpret_cast(Compile::current()->barrier_set_state()); - } - --void ZBarrierSetC2::enqueue_useful_gc_barrier(Unique_Node_List &worklist, Node* node) const { -- if (node->is_LoadBarrier() && !node->as_LoadBarrier()->has_true_uses()) { -- worklist.push(node); +ZLoadBarrierStubC2* ZLoadBarrierStubC2::create(const MachNode* node, Address ref_addr, Register ref, Register tmp, bool weak) { + ZLoadBarrierStubC2* const stub = new (Compile::current()->comp_arena()) ZLoadBarrierStubC2(node, ref_addr, ref, tmp, weak); + if (!Compile::current()->in_scratch_emit_size()) { + barrier_set_state()->stubs()->append(stub); } -} -- + +-void ZBarrierSetC2::enqueue_useful_gc_barrier(Unique_Node_List &worklist, Node* node) const { +- if (node->is_LoadBarrier() && !node->as_LoadBarrier()->has_true_uses()) { +- worklist.push(node); +- } ++ return stub; + } + -static bool load_require_barrier(LoadNode* load) { return ((load->barrier_data() & RequireBarrier) != 0); } -static bool load_has_weak_barrier(LoadNode* load) { return ((load->barrier_data() & WeakBarrier) != 0); } -static bool load_has_expanded_barrier(LoadNode* load) { return ((load->barrier_data() & ExpandedBarrier) != 0); } -static void load_set_expanded_barrier(LoadNode* load) { return load->set_barrier_data(ExpandedBarrier); } - +- -static void load_set_barrier(LoadNode* load, bool weak) { - if (weak) { - load->set_barrier_data(WeakBarrier); - } else { - load->set_barrier_data(RequireBarrier); - } -+ return stub; ++ZLoadBarrierStubC2::ZLoadBarrierStubC2(const MachNode* node, Address ref_addr, Register ref, Register tmp, bool weak) : ++ _node(node), ++ _ref_addr(ref_addr), ++ _ref(ref), ++ _tmp(tmp), ++ _weak(weak), ++ _entry(), ++ _continuation() { ++ assert_different_registers(ref, ref_addr.base()); ++ assert_different_registers(ref, ref_addr.index()); } -// == LoadBarrierNode == @@ -2585,35 +3231,27 @@ index bf0bd43af..a12973464 100644 - init_req(Control, c); - init_req(Memory, mem); - init_req(Oop, val); -- init_req(Address, adr); -- init_req(Similar, C->top()); -- -- init_class_id(Class_LoadBarrier); -- BarrierSetC2* bs = BarrierSet::barrier_set()->barrier_set_c2(); -- bs->register_potential_barrier_node(this); -+ZLoadBarrierStubC2::ZLoadBarrierStubC2(const MachNode* node, Address ref_addr, Register ref, Register tmp, bool weak) : -+ _node(node), -+ _ref_addr(ref_addr), -+ _ref(ref), -+ _tmp(tmp), -+ _weak(weak), -+ _entry(), -+ _continuation() { -+ assert_different_registers(ref, ref_addr.base()); -+ assert_different_registers(ref, ref_addr.index()); +- init_req(Address, adr); +- init_req(Similar, C->top()); +- +- init_class_id(Class_LoadBarrier); +- BarrierSetC2* bs = BarrierSet::barrier_set()->barrier_set_c2(); +- bs->register_potential_barrier_node(this); ++Address ZLoadBarrierStubC2::ref_addr() const { ++ return _ref_addr; } -uint LoadBarrierNode::size_of() const { - return sizeof(*this); -+Address ZLoadBarrierStubC2::ref_addr() const { -+ return _ref_addr; ++Register ZLoadBarrierStubC2::ref() const { ++ return _ref; } -uint LoadBarrierNode::cmp(const Node& n) const { - ShouldNotReachHere(); - return 0; -+Register ZLoadBarrierStubC2::ref() const { -+ return _ref; ++Register ZLoadBarrierStubC2::tmp() const { ++ return _tmp; } -const Type *LoadBarrierNode::bottom_type() const { @@ -2623,15 +3261,15 @@ index bf0bd43af..a12973464 100644 - floadbarrier[Memory] = Type::MEMORY; - floadbarrier[Oop] = in_oop == NULL ? Type::TOP : in_oop->bottom_type(); - return TypeTuple::make(Number_of_Outputs, floadbarrier); -+Register ZLoadBarrierStubC2::tmp() const { -+ return _tmp; ++address ZLoadBarrierStubC2::slow_path() const { ++ const DecoratorSet decorators = _weak ? ON_WEAK_OOP_REF : ON_STRONG_OOP_REF; ++ return ZBarrierSetRuntime::load_barrier_on_oop_field_preloaded_addr(decorators); } -const TypePtr* LoadBarrierNode::adr_type() const { - return TypeRawPtr::BOTTOM; -+address ZLoadBarrierStubC2::slow_path() const { -+ const DecoratorSet decorators = _weak ? ON_WEAK_OOP_REF : ON_STRONG_OOP_REF; -+ return ZBarrierSetRuntime::load_barrier_on_oop_field_preloaded_addr(decorators); ++RegMask& ZLoadBarrierStubC2::live() const { ++ return *barrier_set_state()->live(_node); } -const Type *LoadBarrierNode::Value(PhaseGVN *phase) const { @@ -2641,8 +3279,12 @@ index bf0bd43af..a12973464 100644 - floadbarrier[Memory] = Type::MEMORY; - floadbarrier[Oop] = val_t; - return TypeTuple::make(Number_of_Outputs, floadbarrier); -+RegMask& ZLoadBarrierStubC2::live() const { -+ return *barrier_set_state()->live(_node); ++Label* ZLoadBarrierStubC2::entry() { ++ // The _entry will never be bound when in_scratch_emit_size() is true. ++ // However, we still need to return a label that is not bound now, but ++ // will eventually be bound. Any lable will do, as it will only act as ++ // a placeholder, so we return the _continuation label. ++ return Compile::current()->in_scratch_emit_size() ? &_continuation : &_entry; } -bool LoadBarrierNode::is_dominator(PhaseIdealLoop* phase, bool linear_only, Node *d, Node *n) { @@ -2658,12 +3300,8 @@ index bf0bd43af..a12973464 100644 - } - - return false; -+Label* ZLoadBarrierStubC2::entry() { -+ // The _entry will never be bound when in_scratch_emit_size() is true. -+ // However, we still need to return a label that is not bound now, but -+ // will eventually be bound. Any lable will do, as it will only act as -+ // a placeholder, so we return the _continuation label. -+ return Compile::current()->in_scratch_emit_size() ? &_continuation : &_entry; ++Label* ZLoadBarrierStubC2::continuation() { ++ return &_continuation; } -LoadBarrierNode* LoadBarrierNode::has_dominating_barrier(PhaseIdealLoop* phase, bool linear_only, bool look_for_similar) { @@ -2758,10 +3396,8 @@ index bf0bd43af..a12973464 100644 - } - - return NULL; -+Label* ZLoadBarrierStubC2::continuation() { -+ return &_continuation; - } - +-} +- -void LoadBarrierNode::push_dominated_barriers(PhaseIterGVN* igvn) const { - // Change to that barrier may affect a dominated barrier so re-push those - assert(!is_weak(), "sanity"); @@ -2932,8 +3568,9 @@ index bf0bd43af..a12973464 100644 - --imax; - } - } --} -- ++ return size; + } + -bool LoadBarrierNode::has_true_uses() const { - Node* out_res = proj_out_or_null(Oop); - if (out_res != NULL) { @@ -2942,71 +3579,70 @@ index bf0bd43af..a12973464 100644 - if (!u->is_LoadBarrier() || u->in(Similar) != out_res) { - return true; - } -- } -- } ++static void set_barrier_data(C2Access& access) { ++ if (ZBarrierSet::barrier_needed(access.decorators(), access.type())) { ++ if (access.decorators() & ON_WEAK_OOP_REF) { ++ access.set_barrier_data(ZLoadBarrierWeak); ++ } else { ++ access.set_barrier_data(ZLoadBarrierStrong); + } + } - return false; -+ return size; - } - - static bool barrier_needed(C2Access access) { -@@ -466,1071 +179,253 @@ static bool barrier_needed(C2Access access) { +-} +- +-static bool barrier_needed(C2Access access) { +- return ZBarrierSet::barrier_needed(access.decorators(), access.type()); } Node* ZBarrierSetC2::load_at_resolved(C2Access& access, const Type* val_type) const { - Node* p = BarrierSetC2::load_at_resolved(access, val_type); - if (!barrier_needed(access)) { - return p; -+ Node* result = BarrierSetC2::load_at_resolved(access, val_type); -+ if (barrier_needed(access) && access.raw_access()->is_Mem()) { -+ if ((access.decorators() & ON_WEAK_OOP_REF) != 0) { -+ access.raw_access()->as_Load()->set_barrier_data(ZLoadBarrierWeak); -+ } else { -+ access.raw_access()->as_Load()->set_barrier_data(ZLoadBarrierStrong); -+ } - } - +- } +- - bool weak = (access.decorators() & ON_WEAK_OOP_REF) != 0; - if (p->isa_Load()) { - load_set_barrier(p->as_Load(), weak); - } - return p; -+ return result; ++ set_barrier_data(access); ++ return BarrierSetC2::load_at_resolved(access, val_type); } Node* ZBarrierSetC2::atomic_cmpxchg_val_at_resolved(C2AtomicAccess& access, Node* expected_val, Node* new_val, const Type* val_type) const { - Node* result = BarrierSetC2::atomic_cmpxchg_val_at_resolved(access, expected_val, new_val, val_type); +- Node* result = BarrierSetC2::atomic_cmpxchg_val_at_resolved(access, expected_val, new_val, val_type); - LoadStoreNode* lsn = result->as_LoadStore(); - if (barrier_needed(access)) { +- if (barrier_needed(access)) { - lsn->set_has_barrier(); -+ access.raw_access()->as_LoadStore()->set_barrier_data(ZLoadBarrierStrong); - } +- } - return lsn; -+ return result; ++ set_barrier_data(access); ++ return BarrierSetC2::atomic_cmpxchg_val_at_resolved(access, expected_val, new_val, val_type); } Node* ZBarrierSetC2::atomic_cmpxchg_bool_at_resolved(C2AtomicAccess& access, Node* expected_val, Node* new_val, const Type* value_type) const { - Node* result = BarrierSetC2::atomic_cmpxchg_bool_at_resolved(access, expected_val, new_val, value_type); +- Node* result = BarrierSetC2::atomic_cmpxchg_bool_at_resolved(access, expected_val, new_val, value_type); - LoadStoreNode* lsn = result->as_LoadStore(); - if (barrier_needed(access)) { +- if (barrier_needed(access)) { - lsn->set_has_barrier(); -+ access.raw_access()->as_LoadStore()->set_barrier_data(ZLoadBarrierStrong); - } +- } - return lsn; -+ return result; - +- ++ set_barrier_data(access); ++ return BarrierSetC2::atomic_cmpxchg_bool_at_resolved(access, expected_val, new_val, value_type); } Node* ZBarrierSetC2::atomic_xchg_at_resolved(C2AtomicAccess& access, Node* new_val, const Type* val_type) const { - Node* result = BarrierSetC2::atomic_xchg_at_resolved(access, new_val, val_type); +- Node* result = BarrierSetC2::atomic_xchg_at_resolved(access, new_val, val_type); - LoadStoreNode* lsn = result->as_LoadStore(); - if (barrier_needed(access)) { +- if (barrier_needed(access)) { - lsn->set_has_barrier(); -+ access.raw_access()->as_LoadStore()->set_barrier_data(ZLoadBarrierStrong); - } +- } - return lsn; -+ return result; ++ set_barrier_data(access); ++ return BarrierSetC2::atomic_xchg_at_resolved(access, new_val, val_type); } -// == Macro Expansion == @@ -3063,8 +3699,10 @@ index bf0bd43af..a12973464 100644 - assert(step_over_gc_barrier(result_phi) == in_val, "sanity"); - phase->C->print_method(PHASE_BEFORE_MACRO_EXPANSION, 4, barrier->_idx); - return; --} -- ++bool ZBarrierSetC2::array_copy_requires_gc_barriers(BasicType type) const { ++ return type == T_OBJECT || type == T_ARRAY; + } + -bool ZBarrierSetC2::expand_macro_nodes(PhaseMacroExpand* macro) const { - Compile* C = Compile::current(); - PhaseIterGVN &igvn = macro->igvn(); @@ -3105,10 +3743,8 @@ index bf0bd43af..a12973464 100644 - if (C->failing()) return true; - } - return false; -+bool ZBarrierSetC2::array_copy_requires_gc_barriers(BasicType type) const { -+ return type == T_OBJECT || type == T_ARRAY; - } - +-} +- -Node* ZBarrierSetC2::step_over_gc_barrier(Node* c) const { - Node* node = c; - @@ -3116,13 +3752,13 @@ index bf0bd43af..a12973464 100644 - if (node->is_Proj()) { - node = node->in(0); - } -- ++// == Dominating barrier elision == + - // 2. This step checks for unexpanded load barriers - if (node->is_LoadBarrier()) { - return node->in(LoadBarrierNode::Oop); - } -+// == Dominating barrier elision == - +- - // 3. This step checks for the phi corresponding to an optimized load barrier expansion - if (node->is_Phi()) { - PhiNode* phi = node->as_Phi(); @@ -3419,6 +4055,16 @@ index bf0bd43af..a12973464 100644 - // In that way no extra unnecessary loads are cloned. - - // Any use dominated by original block must have an phi and a region added +- +- Node* catch_node = ctrl->raw_out(0); +- int number_of_catch_projs = catch_node->outcnt(); +- Node** proj_to_load_mapping = NEW_RESOURCE_ARRAY(Node*, number_of_catch_projs); +- Copy::zero_to_bytes(proj_to_load_mapping, sizeof(Node*) * number_of_catch_projs); +- +- // The phi_map is used to keep track of where phis have already been inserted +- int phi_map_len = phase->C->unique(); +- Node** phi_map = NEW_RESOURCE_ARRAY(Node*, phi_map_len); +- Copy::zero_to_bytes(phi_map, sizeof(Node*) * phi_map_len); + // Step 2 - Find dominating accesses for each load + for (uint i = 0; i < barrier_loads.size(); i++) { + MachNode* const load = barrier_loads.at(i)->as_Mach(); @@ -3428,10 +4074,9 @@ index bf0bd43af..a12973464 100644 + Block* const load_block = cfg->get_block_for_node(load); + const uint load_index = block_index(load_block, load); -- Node* catch_node = ctrl->raw_out(0); -- int number_of_catch_projs = catch_node->outcnt(); -- Node** proj_to_load_mapping = NEW_RESOURCE_ARRAY(Node*, number_of_catch_projs); -- Copy::zero_to_bytes(proj_to_load_mapping, sizeof(Node*) * number_of_catch_projs); +- for (unsigned int i = 0; i < load->outcnt(); i++) { +- Node* load_use_control = NULL; +- Node* load_use = load->raw_out(i); + for (uint j = 0; j < mem_ops.size(); j++) { + MachNode* mem = mem_ops.at(j)->as_Mach(); + const TypePtr* mem_adr_type = NULL; @@ -3440,15 +4085,6 @@ index bf0bd43af..a12973464 100644 + Block* mem_block = cfg->get_block_for_node(mem); + uint mem_index = block_index(mem_block, mem); -- // The phi_map is used to keep track of where phis have already been inserted -- int phi_map_len = phase->C->unique(); -- Node** phi_map = NEW_RESOURCE_ARRAY(Node*, phi_map_len); -- Copy::zero_to_bytes(phi_map, sizeof(Node*) * phi_map_len); -- -- for (unsigned int i = 0; i < load->outcnt(); i++) { -- Node* load_use_control = NULL; -- Node* load_use = load->raw_out(i); -- - if (phase->has_ctrl(load_use)) { - load_use_control = phase->get_ctrl(load_use); - } else { @@ -3520,13 +4156,13 @@ index bf0bd43af..a12973464 100644 - // But keep iterating to catch any bad idom early. - found_dominating_catchproj = true; - } - +- - // We found no single catchproj that dominated the use - The use is at a point after - // where control flow from multiple catch projs have merged. We will have to create - // phi nodes before the use and tie the output from the cloned loads together. It - // can be a single phi or a number of chained phis, depending on control flow - if (!found_dominating_catchproj) { -- + - // Use phi-control if use is a phi - if (load_use_is_phi) { - load_use_control = phi_ctrl; @@ -4424,6 +5060,366 @@ index 52133c073..9d07f9e8c 100644 #include "utilities/macros.hpp" class ZBarrierSetAssemblerBase : public BarrierSetAssembler { +diff --git a/src/hotspot/share/gc/z/zGlobals.hpp b/src/hotspot/share/gc/z/zGlobals.hpp +index 080ea5c0e..0f9e9dcb4 100644 +--- a/src/hotspot/share/gc/z/zGlobals.hpp ++++ b/src/hotspot/share/gc/z/zGlobals.hpp +@@ -117,11 +117,8 @@ extern uintptr_t ZAddressWeakBadMask; + // Marked state + extern uintptr_t ZAddressMetadataMarked; + +-// Address space for mark stack allocations +-const size_t ZMarkStackSpaceSizeShift = 40; // 1TB +-const size_t ZMarkStackSpaceSize = (size_t)1 << ZMarkStackSpaceSizeShift; +-const uintptr_t ZMarkStackSpaceStart = ZAddressSpaceEnd + ZMarkStackSpaceSize; +-const uintptr_t ZMarkStackSpaceEnd = ZMarkStackSpaceStart + ZMarkStackSpaceSize; ++// Mark stack space ++extern uintptr_t ZMarkStackSpaceStart; + const size_t ZMarkStackSpaceExpandSize = (size_t)1 << 25; // 32M + + // Mark stack and magazine sizes +diff --git a/src/hotspot/share/gc/z/zHeap.cpp b/src/hotspot/share/gc/z/zHeap.cpp +index ff08a0759..7f0f0b0de 100644 +--- a/src/hotspot/share/gc/z/zHeap.cpp ++++ b/src/hotspot/share/gc/z/zHeap.cpp +@@ -49,6 +49,7 @@ + #include "runtime/thread.hpp" + #include "utilities/align.hpp" + #include "utilities/debug.hpp" ++#include "prims/resolvedMethodTable.hpp" + + static const ZStatSampler ZSamplerHeapUsedBeforeMark("Memory", "Heap Used Before Mark", ZStatUnitBytes); + static const ZStatSampler ZSamplerHeapUsedAfterMark("Memory", "Heap Used After Mark", ZStatUnitBytes); +@@ -334,6 +335,10 @@ bool ZHeap::mark_end() { + Universe::verify(); + } + ++ // Free unsed entries of ResolvedMethodTable and weakhandles ++ // avoid ResolvedMethodTable inflation and native memory leak ++ ResolvedMethodTable::unlink(); ++ + return true; + } + +diff --git a/src/hotspot/share/gc/z/zLiveMap.cpp b/src/hotspot/share/gc/z/zLiveMap.cpp +index 7187b6166..c1d79b794 100644 +--- a/src/hotspot/share/gc/z/zLiveMap.cpp ++++ b/src/hotspot/share/gc/z/zLiveMap.cpp +@@ -50,7 +50,9 @@ void ZLiveMap::reset(size_t index) { + + // Multiple threads can enter here, make sure only one of them + // resets the marking information while the others busy wait. +- for (uint32_t seqnum = _seqnum; seqnum != ZGlobalSeqNum; seqnum = _seqnum) { ++ for (uint32_t seqnum = OrderAccess::load_acquire(&_seqnum); ++ seqnum != ZGlobalSeqNum; ++ seqnum = OrderAccess::load_acquire(&_seqnum)) { + if ((seqnum != seqnum_initializing) && + (Atomic::cmpxchg(seqnum_initializing, &_seqnum, seqnum) == seqnum)) { + // Reset marking information +@@ -61,13 +63,13 @@ void ZLiveMap::reset(size_t index) { + segment_live_bits().clear(); + segment_claim_bits().clear(); + +- // Make sure the newly reset marking information is +- // globally visible before updating the page seqnum. +- OrderAccess::storestore(); +- +- // Update seqnum + assert(_seqnum == seqnum_initializing, "Invalid"); +- _seqnum = ZGlobalSeqNum; ++ ++ // Make sure the newly reset marking information is ordered ++ // before the update of the page seqnum, such that when the ++ // up-to-date seqnum is load acquired, the bit maps will not ++ // contain stale information. ++ OrderAccess::release_store(&_seqnum, ZGlobalSeqNum); + break; + } + +@@ -89,10 +91,6 @@ void ZLiveMap::reset_segment(BitMap::idx_t segment) { + if (!claim_segment(segment)) { + // Already claimed, wait for live bit to be set + while (!is_segment_live(segment)) { +- // Busy wait. The loadload barrier is needed to make +- // sure we re-read the live bit every time we loop. +- OrderAccess::loadload(); +- + // Mark reset contention + if (!contention) { + // Count contention once +diff --git a/src/hotspot/share/gc/z/zLiveMap.inline.hpp b/src/hotspot/share/gc/z/zLiveMap.inline.hpp +index 1e4d56f41..fb45a892c 100644 +--- a/src/hotspot/share/gc/z/zLiveMap.inline.hpp ++++ b/src/hotspot/share/gc/z/zLiveMap.inline.hpp +@@ -30,6 +30,7 @@ + #include "gc/z/zOop.inline.hpp" + #include "gc/z/zUtils.inline.hpp" + #include "runtime/atomic.hpp" ++#include "runtime/orderAccess.hpp" + #include "utilities/bitMap.inline.hpp" + #include "utilities/debug.hpp" + +@@ -38,7 +39,7 @@ inline void ZLiveMap::reset() { + } + + inline bool ZLiveMap::is_marked() const { +- return _seqnum == ZGlobalSeqNum; ++ return OrderAccess::load_acquire(&_seqnum) == ZGlobalSeqNum; + } + + inline uint32_t ZLiveMap::live_objects() const { +@@ -68,15 +69,15 @@ inline BitMapView ZLiveMap::segment_claim_bits() { + } + + inline bool ZLiveMap::is_segment_live(BitMap::idx_t segment) const { +- return segment_live_bits().at(segment); ++ return segment_live_bits().par_at(segment); + } + + inline bool ZLiveMap::set_segment_live_atomic(BitMap::idx_t segment) { +- return segment_live_bits().par_set_bit(segment); ++ return segment_live_bits().par_set_bit(segment, memory_order_release); + } + + inline bool ZLiveMap::claim_segment(BitMap::idx_t segment) { +- return segment_claim_bits().par_set_bit(segment); ++ return segment_claim_bits().par_set_bit(segment, memory_order_acq_rel); + } + + inline BitMap::idx_t ZLiveMap::first_live_segment() const { +diff --git a/src/hotspot/share/gc/z/zMarkStack.cpp b/src/hotspot/share/gc/z/zMarkStack.cpp +index 52fe51ece..9cc768956 100644 +--- a/src/hotspot/share/gc/z/zMarkStack.cpp ++++ b/src/hotspot/share/gc/z/zMarkStack.cpp +@@ -28,58 +28,44 @@ + #include "gc/z/zMarkStack.inline.hpp" + #include "logging/log.hpp" + #include "runtime/atomic.hpp" ++#include "runtime/os.hpp" + #include "utilities/debug.hpp" + +-#include +-#include ++uintptr_t ZMarkStackSpaceStart; + + ZMarkStackSpace::ZMarkStackSpace() : + _expand_lock(), ++ _start(0), + _top(0), + _end(0) { +- assert(ZMarkStacksMax >= ZMarkStackSpaceExpandSize, "ZMarkStacksMax too small"); +- assert(ZMarkStacksMax <= ZMarkStackSpaceSize, "ZMarkStacksMax too large"); +- ++ assert(ZMarkStackSpaceLimit >= ZMarkStackSpaceExpandSize, "ZMarkStackSpaceLimit too small"); + // Reserve address space +- const void* res = mmap((void*)ZMarkStackSpaceStart, ZMarkStackSpaceSize, +- PROT_NONE, MAP_ANONYMOUS|MAP_PRIVATE|MAP_NORESERVE, -1, 0); +- if (res != (void*)ZMarkStackSpaceStart) { +- log_error(gc, marking)("Failed to reserve address space for marking stacks"); ++ const size_t size = ZMarkStackSpaceLimit; ++ const size_t alignment = (size_t)os::vm_allocation_granularity(); ++ const uintptr_t addr = (uintptr_t)os::reserve_memory(size, NULL, alignment, mtGC); ++ if (addr == 0) { ++ log_error(gc, marking)("Failed to reserve address space for mark stacks"); + return; + } + + // Successfully initialized +- _top = _end = ZMarkStackSpaceStart; +-} ++ _start = _top = _end = addr; + +-bool ZMarkStackSpace::is_initialized() const { +- return _top != 0; ++ // Register mark stack space start ++ ZMarkStackSpaceStart = _start; + } + +-bool ZMarkStackSpace::expand() { +- const size_t max = ZMarkStackSpaceStart + ZMarkStacksMax; +- if (_end + ZMarkStackSpaceExpandSize > max) { +- // Expansion limit reached +- return false; +- } +- +- void* const res = mmap((void*)_end, ZMarkStackSpaceExpandSize, +- PROT_READ|PROT_WRITE, MAP_ANONYMOUS|MAP_PRIVATE|MAP_FIXED, -1, 0); +- if (res == MAP_FAILED) { +- ZErrno err; +- log_error(gc, marking)("Failed to map memory for marking stacks (%s)", err.to_string()); +- return false; +- } +- +- return true; ++bool ZMarkStackSpace::is_initialized() const { ++ return _start != 0; + } + + uintptr_t ZMarkStackSpace::alloc_space(size_t size) { +- uintptr_t top = _top; ++ uintptr_t top = Atomic::load(&_top); + + for (;;) { ++ const uintptr_t end = Atomic::load(&_end); + const uintptr_t new_top = top + size; +- if (new_top > _end) { ++ if (new_top > end) { + // Not enough space left + return 0; + } +@@ -104,24 +90,28 @@ uintptr_t ZMarkStackSpace::expand_and_alloc_space(size_t size) { + return addr; + } + +- // Expand stack space +- if (!expand()) { +- // We currently can't handle the situation where we +- // are running out of mark stack space. +- fatal("Mark stack overflow (allocated " SIZE_FORMAT "M, size " SIZE_FORMAT "M, max " SIZE_FORMAT "M)," +- " use -XX:ZMarkStacksMax=? to increase this limit", +- (_end - ZMarkStackSpaceStart) / M, size / M, ZMarkStacksMax / M); +- return 0; ++ // Check expansion limit ++ const size_t expand_size = ZMarkStackSpaceExpandSize; ++ const size_t old_size = _end - _start; ++ const size_t new_size = old_size + expand_size; ++ if (new_size > ZMarkStackSpaceLimit) { ++ // Expansion limit reached. This is a fatal error since we ++ // currently can't recover from running out of mark stack space. ++ fatal("Mark stack space exhausted. Use -XX:ZMarkStackSpaceLimit= to increase the " ++ "maximum number of bytes allocated for mark stacks. Current limit is " SIZE_FORMAT "M.", ++ ZMarkStackSpaceLimit / M); + } + + log_debug(gc, marking)("Expanding mark stack space: " SIZE_FORMAT "M->" SIZE_FORMAT "M", +- (_end - ZMarkStackSpaceStart) / M, +- (_end - ZMarkStackSpaceStart + ZMarkStackSpaceExpandSize) / M); ++ old_size / M, new_size / M); ++ ++ // Expand ++ os::commit_memory_or_exit((char*)_end, expand_size, false /* executable */, "Mark stack space"); + + // Increment top before end to make sure another + // thread can't steal out newly expanded space. + addr = Atomic::add(size, &_top) - size; +- _end += ZMarkStackSpaceExpandSize; ++ Atomic::add(expand_size, &_end); + + return addr; + } +diff --git a/src/hotspot/share/gc/z/zMarkStack.hpp b/src/hotspot/share/gc/z/zMarkStack.hpp +index b68b9faa3..12f3e4eca 100644 +--- a/src/hotspot/share/gc/z/zMarkStack.hpp ++++ b/src/hotspot/share/gc/z/zMarkStack.hpp +@@ -76,6 +76,7 @@ typedef ZStackList ZMarkStackMagazineList; + class ZMarkStackSpace { + private: + ZLock _expand_lock; ++ uintptr_t _start; + volatile uintptr_t _top; + volatile uintptr_t _end; + +diff --git a/src/hotspot/share/gc/z/zWorkers.cpp b/src/hotspot/share/gc/z/zWorkers.cpp +index 0686ec7af..6a0c2561d 100644 +--- a/src/hotspot/share/gc/z/zWorkers.cpp ++++ b/src/hotspot/share/gc/z/zWorkers.cpp +@@ -1,5 +1,5 @@ + /* +- * Copyright (c) 2015, 2017, Oracle and/or its affiliates. All rights reserved. ++ * Copyright (c) 2015, 2018, Oracle and/or its affiliates. All rights reserved. + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. + * + * This code is free software; you can redistribute it and/or modify it +@@ -22,14 +22,27 @@ + */ + + #include "precompiled.hpp" ++#include "gc/z/zGlobals.hpp" + #include "gc/z/zTask.hpp" + #include "gc/z/zWorkers.inline.hpp" + #include "runtime/os.hpp" + #include "runtime/mutexLocker.hpp" + #include "runtime/safepoint.hpp" + +-uint ZWorkers::calculate_ncpus(double share_in_percent) { +- return ceil(os::initial_active_processor_count() * share_in_percent / 100.0); ++static uint calculate_nworkers_based_on_ncpus(double cpu_share_in_percent) { ++ return ceil(os::initial_active_processor_count() * cpu_share_in_percent / 100.0); ++} ++ ++static uint calculate_nworkers_based_on_heap_size(double reserve_share_in_percent) { ++ const int nworkers = ((MaxHeapSize * (reserve_share_in_percent / 100.0)) - ZPageSizeMedium) / ZPageSizeSmall; ++ return MAX2(nworkers, 1); ++} ++ ++static uint calculate_nworkers(double cpu_share_in_percent) { ++ // Cap number of workers so that we never use more than 10% of the max heap ++ // for the reserve. This is useful when using small heaps on large machines. ++ return MIN2(calculate_nworkers_based_on_ncpus(cpu_share_in_percent), ++ calculate_nworkers_based_on_heap_size(10.0)); + } + + uint ZWorkers::calculate_nparallel() { +@@ -38,7 +51,7 @@ uint ZWorkers::calculate_nparallel() { + // close to the number of processors tends to lead to over-provisioning and + // scheduling latency issues. Using 60% of the active processors appears to + // be a fairly good balance. +- return calculate_ncpus(60.0); ++ return calculate_nworkers(60.0); + } + + uint ZWorkers::calculate_nconcurrent() { +@@ -48,7 +61,7 @@ uint ZWorkers::calculate_nconcurrent() { + // throughput, while using too few threads will prolong the GC-cycle and + // we then risk being out-run by the application. Using 12.5% of the active + // processors appears to be a fairly good balance. +- return calculate_ncpus(12.5); ++ return calculate_nworkers(12.5); + } + + class ZWorkersWarmupTask : public ZTask { +diff --git a/src/hotspot/share/gc/z/zWorkers.hpp b/src/hotspot/share/gc/z/zWorkers.hpp +index 8bd072ed4..663a5763b 100644 +--- a/src/hotspot/share/gc/z/zWorkers.hpp ++++ b/src/hotspot/share/gc/z/zWorkers.hpp +@@ -35,8 +35,6 @@ private: + bool _boost; + WorkGang _workers; + +- static uint calculate_ncpus(double share_in_percent); +- + void run(ZTask* task, uint nworkers); + + public: +diff --git a/src/hotspot/share/gc/z/z_globals.hpp b/src/hotspot/share/gc/z/z_globals.hpp +index 9e0f8985b..8cee59be7 100644 +--- a/src/hotspot/share/gc/z/z_globals.hpp ++++ b/src/hotspot/share/gc/z/z_globals.hpp +@@ -53,9 +53,9 @@ + "Allow Java threads to stall and wait for GC to complete " \ + "instead of immediately throwing an OutOfMemoryError") \ + \ +- product(size_t, ZMarkStacksMax, NOT_LP64(512*M) LP64_ONLY(8*G), \ +- "Maximum number of bytes allocated for marking stacks") \ +- range(32*M, NOT_LP64(512*M) LP64_ONLY(1024*G)) \ ++ product(size_t, ZMarkStackSpaceLimit, 8*G, \ ++ "Maximum number of bytes allocated for mark stacks") \ ++ range(32*M, 1024*G) \ + \ + product(uint, ZCollectionInterval, 0, \ + "Force GC at a fixed time interval (in seconds)") \ +diff --git a/src/hotspot/share/opto/c2compiler.cpp b/src/hotspot/share/opto/c2compiler.cpp +index 7768615b7..5a842e31f 100644 +--- a/src/hotspot/share/opto/c2compiler.cpp ++++ b/src/hotspot/share/opto/c2compiler.cpp +@@ -658,6 +658,7 @@ bool C2Compiler::is_intrinsic_supported(const methodHandle& method, bool is_virt + case vmIntrinsics::_profileBoolean: + case vmIntrinsics::_isCompileConstant: + case vmIntrinsics::_Preconditions_checkIndex: ++ case vmIntrinsics::_nextInt: + break; + default: + return false; diff --git a/src/hotspot/share/opto/classes.cpp b/src/hotspot/share/opto/classes.cpp index 75f070f7c..d1282ac78 100644 --- a/src/hotspot/share/opto/classes.cpp @@ -4439,7 +5435,7 @@ index 75f070f7c..d1282ac78 100644 #include "gc/shenandoah/c2/shenandoahBarrierSetC2.hpp" #endif diff --git a/src/hotspot/share/opto/classes.hpp b/src/hotspot/share/opto/classes.hpp -index 61b6552d3..b847caf6e 100644 +index c3a6dc55a..bffb5d1d6 100644 --- a/src/hotspot/share/opto/classes.hpp +++ b/src/hotspot/share/opto/classes.hpp @@ -189,17 +189,6 @@ macro(LoadP) @@ -4461,7 +5457,7 @@ index 61b6552d3..b847caf6e 100644 macro(Loop) macro(LoopLimit) diff --git a/src/hotspot/share/opto/compile.cpp b/src/hotspot/share/opto/compile.cpp -index 8c23b304d..3e45813d7 100644 +index 7e743ee64..43c1dcbf9 100644 --- a/src/hotspot/share/opto/compile.cpp +++ b/src/hotspot/share/opto/compile.cpp @@ -79,9 +79,6 @@ @@ -4517,7 +5513,7 @@ index 8c23b304d..3e45813d7 100644 _replay_inline_data(NULL), _late_inlines(comp_arena(), 2, 0, NULL), _string_late_inlines(comp_arena(), 2, 0, NULL), -@@ -972,9 +969,6 @@ Compile::Compile( ciEnv* ci_env, +@@ -967,9 +964,6 @@ Compile::Compile( ciEnv* ci_env, bool return_pc, DirectiveSet* directive) : Phase(Compiler), @@ -4527,7 +5523,7 @@ index 8c23b304d..3e45813d7 100644 _compile_id(0), _save_argument_registers(save_arg_registers), _do_locks_coarsening(false), -@@ -1005,6 +999,10 @@ Compile::Compile( ciEnv* ci_env, +@@ -999,6 +993,10 @@ Compile::Compile( ciEnv* ci_env, _in_dump_cnt(0), #endif NOT_PRODUCT(_printer(NULL) COMMA) @@ -4538,7 +5534,7 @@ index 8c23b304d..3e45813d7 100644 _comp_arena(mtCompiler), _node_arena(mtCompiler), _old_arena(mtCompiler), -@@ -2427,13 +2425,6 @@ void Compile::Optimize() { +@@ -2420,13 +2418,6 @@ void Compile::Optimize() { igvn.optimize(); } @@ -4552,7 +5548,7 @@ index 8c23b304d..3e45813d7 100644 #ifdef ASSERT bs->verify_gc_barriers(false); #endif -@@ -3019,29 +3010,6 @@ void Compile::final_graph_reshaping_impl( Node *n, Final_Reshape_Counts &frc) { +@@ -3016,29 +3007,6 @@ void Compile::final_graph_reshaping_impl( Node *n, Final_Reshape_Counts &frc) { break; } @@ -4583,10 +5579,10 @@ index 8c23b304d..3e45813d7 100644 Node *addp = n->in(AddPNode::Address); assert( !addp->is_AddP() || diff --git a/src/hotspot/share/opto/compile.hpp b/src/hotspot/share/opto/compile.hpp -index 320030e19..1246b1b77 100644 +index a0ec7d496..0f51a0025 100644 --- a/src/hotspot/share/opto/compile.hpp +++ b/src/hotspot/share/opto/compile.hpp -@@ -55,7 +55,6 @@ class ConnectionGraph; +@@ -56,7 +56,6 @@ class ConnectionGraph; class IdealGraphPrinter; class InlineTree; class Int_Array; @@ -4594,7 +5590,7 @@ index 320030e19..1246b1b77 100644 class Matcher; class MachConstantNode; class MachConstantBaseNode; -@@ -1185,11 +1184,7 @@ class Compile : public Phase { +@@ -1212,11 +1211,7 @@ class Compile : public Phase { bool in_scratch_emit_size() const { return _in_scratch_emit_size; } enum ScratchBufferBlob { @@ -4606,7 +5602,7 @@ index 320030e19..1246b1b77 100644 MAX_locs_size = 128, // number of relocInfo elements MAX_const_size = 128, MAX_stubs_size = 128 -@@ -1264,14 +1259,30 @@ class Compile : public Phase { +@@ -1292,14 +1287,30 @@ class Compile : public Phase { // Process an OopMap Element while emitting nodes void Process_OopMap_Node(MachNode *mach, int code_offset); @@ -4640,10 +5636,10 @@ index 320030e19..1246b1b77 100644 // Compute the size of first NumberOfLoopInstrToAlign instructions // at the head of a loop. diff --git a/src/hotspot/share/opto/escape.cpp b/src/hotspot/share/opto/escape.cpp -index cd0ef2648..0a22c89d9 100644 +index 5da7a2f86..23334429e 100644 --- a/src/hotspot/share/opto/escape.cpp +++ b/src/hotspot/share/opto/escape.cpp -@@ -490,13 +490,6 @@ void ConnectionGraph::add_node_to_connection_graph(Node *n, Unique_Node_List *de +@@ -506,13 +506,6 @@ void ConnectionGraph::add_node_to_connection_graph(Node *n, Unique_Node_List *de add_local_var_and_edge(n, PointsToNode::NoEscape, n->in(0), delayed_worklist); } @@ -4657,7 +5653,7 @@ index cd0ef2648..0a22c89d9 100644 break; } case Op_Rethrow: // Exception object escapes -@@ -731,14 +724,6 @@ void ConnectionGraph::add_final_edges(Node *n) { +@@ -747,14 +740,6 @@ void ConnectionGraph::add_final_edges(Node *n) { add_local_var_and_edge(n, PointsToNode::NoEscape, n->in(0), NULL); break; } @@ -4672,8 +5668,81 @@ index cd0ef2648..0a22c89d9 100644 ELSE_FAIL("Op_Proj"); } case Op_Rethrow: // Exception object escapes +diff --git a/src/hotspot/share/opto/graphKit.cpp b/src/hotspot/share/opto/graphKit.cpp +index b44bc313f..8dd81f7a1 100644 +--- a/src/hotspot/share/opto/graphKit.cpp ++++ b/src/hotspot/share/opto/graphKit.cpp +@@ -43,6 +43,7 @@ + #include "opto/runtime.hpp" + #include "runtime/deoptimization.hpp" + #include "runtime/sharedRuntime.hpp" ++#include "utilities/bitMap.inline.hpp" + #include "utilities/macros.hpp" + #if INCLUDE_SHENANDOAHGC + #include "gc/shenandoah/c2/shenandoahBarrierSetC2.hpp" +@@ -1519,18 +1520,19 @@ Node* GraphKit::make_load(Node* ctl, Node* adr, const Type* t, BasicType bt, + bool require_atomic_access, + bool unaligned, + bool mismatched, +- bool unsafe) { ++ bool unsafe, ++ uint8_t barrier_data) { + assert(adr_idx != Compile::AliasIdxTop, "use other make_load factory" ); + const TypePtr* adr_type = NULL; // debug-mode-only argument + debug_only(adr_type = C->get_adr_type(adr_idx)); + Node* mem = memory(adr_idx); + Node* ld; + if (require_atomic_access && bt == T_LONG) { +- ld = LoadLNode::make_atomic(ctl, mem, adr, adr_type, t, mo, control_dependency, unaligned, mismatched, unsafe); ++ ld = LoadLNode::make_atomic(ctl, mem, adr, adr_type, t, mo, control_dependency, unaligned, mismatched, unsafe, barrier_data); + } else if (require_atomic_access && bt == T_DOUBLE) { +- ld = LoadDNode::make_atomic(ctl, mem, adr, adr_type, t, mo, control_dependency, unaligned, mismatched, unsafe); ++ ld = LoadDNode::make_atomic(ctl, mem, adr, adr_type, t, mo, control_dependency, unaligned, mismatched, unsafe, barrier_data); + } else { +- ld = LoadNode::make(_gvn, ctl, mem, adr, adr_type, t, bt, mo, control_dependency, unaligned, mismatched, unsafe); ++ ld = LoadNode::make(_gvn, ctl, mem, adr, adr_type, t, bt, mo, control_dependency, unaligned, mismatched, unsafe, barrier_data); + } + ld = _gvn.transform(ld); + if (((bt == T_OBJECT) && C->do_escape_analysis()) || C->eliminate_boxing()) { +diff --git a/src/hotspot/share/opto/graphKit.hpp b/src/hotspot/share/opto/graphKit.hpp +index 3529cc239..1022fd09b 100644 +--- a/src/hotspot/share/opto/graphKit.hpp ++++ b/src/hotspot/share/opto/graphKit.hpp +@@ -524,27 +524,27 @@ class GraphKit : public Phase { + Node* make_load(Node* ctl, Node* adr, const Type* t, BasicType bt, + MemNode::MemOrd mo, LoadNode::ControlDependency control_dependency = LoadNode::DependsOnlyOnTest, + bool require_atomic_access = false, bool unaligned = false, +- bool mismatched = false, bool unsafe = false) { ++ bool mismatched = false, bool unsafe = false, uint8_t barrier_data = 0) { + // This version computes alias_index from bottom_type + return make_load(ctl, adr, t, bt, adr->bottom_type()->is_ptr(), + mo, control_dependency, require_atomic_access, +- unaligned, mismatched, unsafe); ++ unaligned, mismatched, unsafe, barrier_data); + } + Node* make_load(Node* ctl, Node* adr, const Type* t, BasicType bt, const TypePtr* adr_type, + MemNode::MemOrd mo, LoadNode::ControlDependency control_dependency = LoadNode::DependsOnlyOnTest, + bool require_atomic_access = false, bool unaligned = false, +- bool mismatched = false, bool unsafe = false) { ++ bool mismatched = false, bool unsafe = false, uint8_t barrier_data = 0) { + // This version computes alias_index from an address type + assert(adr_type != NULL, "use other make_load factory"); + return make_load(ctl, adr, t, bt, C->get_alias_index(adr_type), + mo, control_dependency, require_atomic_access, +- unaligned, mismatched, unsafe); ++ unaligned, mismatched, unsafe, barrier_data); + } + // This is the base version which is given an alias index. + Node* make_load(Node* ctl, Node* adr, const Type* t, BasicType bt, int adr_idx, + MemNode::MemOrd mo, LoadNode::ControlDependency control_dependency = LoadNode::DependsOnlyOnTest, + bool require_atomic_access = false, bool unaligned = false, +- bool mismatched = false, bool unsafe = false); ++ bool mismatched = false, bool unsafe = false, uint8_t barrier_data = 0); + + // Create & transform a StoreNode and store the effect into the + // parser's memory state. diff --git a/src/hotspot/share/opto/lcm.cpp b/src/hotspot/share/opto/lcm.cpp -index 05ec9fa9f..16b80bfc3 100644 +index e97a4437f..f3fea9965 100644 --- a/src/hotspot/share/opto/lcm.cpp +++ b/src/hotspot/share/opto/lcm.cpp @@ -169,7 +169,6 @@ void PhaseCFG::implicit_null_check(Block* block, Node *proj, Node *val, int allo @@ -4684,11 +5753,50 @@ index 05ec9fa9f..16b80bfc3 100644 case Op_LoadN: case Op_LoadS: case Op_LoadKlass: +diff --git a/src/hotspot/share/opto/library_call.cpp b/src/hotspot/share/opto/library_call.cpp +index 515665ffa..2da775a6a 100644 +--- a/src/hotspot/share/opto/library_call.cpp ++++ b/src/hotspot/share/opto/library_call.cpp +@@ -337,6 +337,7 @@ class LibraryCallKit : public GraphKit { + + bool inline_profileBoolean(); + bool inline_isCompileConstant(); ++ bool inline_nextIntRuntime(); + void clear_upper_avx() { + #ifdef X86 + if (UseAVX >= 2) { +@@ -887,6 +888,9 @@ bool LibraryCallKit::try_to_inline(int predicate) { + case vmIntrinsics::_isCompileConstant: + return inline_isCompileConstant(); + ++ case vmIntrinsics::_nextInt: ++ return SharedRuntime::_opt_for_aarch64 ? inline_nextIntRuntime() : false; ++ + case vmIntrinsics::_hasNegatives: + return inline_hasNegatives(); + +@@ -6989,3 +6993,16 @@ bool LibraryCallKit::inline_isCompileConstant() { + set_result(n->is_Con() ? intcon(1) : intcon(0)); + return true; + } ++ ++bool LibraryCallKit::inline_nextIntRuntime() { ++ Node* ctrl = control(); ++ Node* monotonical_incr_adr = makecon(TypeRawPtr::make(SharedRuntime::monotonical_incr_addr())); ++ int adr_type = Compile::AliasIdxRaw; ++ ++ Node* monotonical_incr = make_load(ctrl, monotonical_incr_adr, TypeInt::INT, T_INT, adr_type, MemNode::unordered); ++ Node* incr = _gvn.transform(new AddINode(monotonical_incr, _gvn.intcon(13))); ++ store_to_memory(ctrl, monotonical_incr_adr, incr, T_INT, adr_type, MemNode::unordered); ++ ++ set_result(incr); ++ return true; ++} diff --git a/src/hotspot/share/opto/loopnode.cpp b/src/hotspot/share/opto/loopnode.cpp -index d7eb3996b..366d0f378 100644 +index 5ad560fdd..7a6436c62 100644 --- a/src/hotspot/share/opto/loopnode.cpp +++ b/src/hotspot/share/opto/loopnode.cpp -@@ -4300,7 +4300,6 @@ void PhaseIdealLoop::build_loop_late_post( Node *n ) { +@@ -4596,7 +4596,6 @@ void PhaseIdealLoop::build_loop_late_post( Node *n ) { case Op_LoadL: case Op_LoadS: case Op_LoadP: @@ -4697,7 +5805,7 @@ index d7eb3996b..366d0f378 100644 case Op_LoadRange: case Op_LoadD_unaligned: diff --git a/src/hotspot/share/opto/loopopts.cpp b/src/hotspot/share/opto/loopopts.cpp -index a32f1f5f2..ffbd84aee 100644 +index 27bf3a3c1..c170a0395 100644 --- a/src/hotspot/share/opto/loopopts.cpp +++ b/src/hotspot/share/opto/loopopts.cpp @@ -41,9 +41,6 @@ @@ -4711,7 +5819,7 @@ index a32f1f5f2..ffbd84aee 100644 //============================================================================= //------------------------------split_thru_phi--------------------------------- diff --git a/src/hotspot/share/opto/machnode.hpp b/src/hotspot/share/opto/machnode.hpp -index 66adf9be1..90d5b0af1 100644 +index a52325680..8fb75d0d6 100644 --- a/src/hotspot/share/opto/machnode.hpp +++ b/src/hotspot/share/opto/machnode.hpp @@ -197,7 +197,7 @@ public: @@ -4745,10 +5853,10 @@ index 66adf9be1..90d5b0af1 100644 // more leafs. Must be set by MachNode constructor to point to an // internal array of MachOpers. The MachOper array is sized by diff --git a/src/hotspot/share/opto/matcher.cpp b/src/hotspot/share/opto/matcher.cpp -index 45d262776..05fdab21e 100644 +index 2d3bafdd7..4cc7580a8 100644 --- a/src/hotspot/share/opto/matcher.cpp +++ b/src/hotspot/share/opto/matcher.cpp -@@ -1752,6 +1752,13 @@ MachNode *Matcher::ReduceInst( State *s, int rule, Node *&mem ) { +@@ -1754,6 +1754,13 @@ MachNode *Matcher::ReduceInst( State *s, int rule, Node *&mem ) { _shared_nodes.map(leaf->_idx, ex); } @@ -4762,7 +5870,7 @@ index 45d262776..05fdab21e 100644 return ex; } -@@ -2171,17 +2178,6 @@ void Matcher::find_shared( Node *n ) { +@@ -2173,17 +2180,6 @@ void Matcher::find_shared( Node *n ) { case Op_SafePoint: mem_op = true; break; @@ -4780,7 +5888,7 @@ index 45d262776..05fdab21e 100644 default: if( n->is_Store() ) { // Do match stores, despite no ideal reg -@@ -2294,33 +2290,6 @@ void Matcher::find_shared( Node *n ) { +@@ -2296,33 +2292,6 @@ void Matcher::find_shared( Node *n ) { n->del_req(LoadStoreConditionalNode::ExpectedIn); break; } @@ -4815,7 +5923,7 @@ index 45d262776..05fdab21e 100644 case Op_CMoveF: case Op_CMoveI: diff --git a/src/hotspot/share/opto/memnode.cpp b/src/hotspot/share/opto/memnode.cpp -index 651bbfcf1..3a5e45401 100644 +index 8ffb5a708..32ce0f9bc 100644 --- a/src/hotspot/share/opto/memnode.cpp +++ b/src/hotspot/share/opto/memnode.cpp @@ -49,9 +49,6 @@ @@ -4828,7 +5936,55 @@ index 651bbfcf1..3a5e45401 100644 #if INCLUDE_SHENANDOAHGC #include "gc/shenandoah/c2/shenandoahBarrierSetC2.hpp" #endif -@@ -2852,7 +2849,7 @@ LoadStoreNode::LoadStoreNode( Node *c, Node *mem, Node *adr, Node *val, const Ty +@@ -858,7 +855,7 @@ bool LoadNode::is_immutable_value(Node* adr) { + //----------------------------LoadNode::make----------------------------------- + // Polymorphic factory method: + Node *LoadNode::make(PhaseGVN& gvn, Node *ctl, Node *mem, Node *adr, const TypePtr* adr_type, const Type *rt, BasicType bt, MemOrd mo, +- ControlDependency control_dependency, bool unaligned, bool mismatched, bool unsafe) { ++ ControlDependency control_dependency, bool unaligned, bool mismatched, bool unsafe, uint8_t barrier_data) { + Compile* C = gvn.C; + + // sanity check the alias category against the created node type +@@ -909,6 +906,7 @@ Node *LoadNode::make(PhaseGVN& gvn, Node *ctl, Node *mem, Node *adr, const TypeP + if (unsafe) { + load->set_unsafe_access(); + } ++ load->set_barrier_data(barrier_data); + if (load->Opcode() == Op_LoadN) { + Node* ld = gvn.transform(load); + return new DecodeNNode(ld, ld->bottom_type()->make_ptr()); +@@ -918,7 +916,7 @@ Node *LoadNode::make(PhaseGVN& gvn, Node *ctl, Node *mem, Node *adr, const TypeP + } + + LoadLNode* LoadLNode::make_atomic(Node* ctl, Node* mem, Node* adr, const TypePtr* adr_type, const Type* rt, MemOrd mo, +- ControlDependency control_dependency, bool unaligned, bool mismatched, bool unsafe) { ++ ControlDependency control_dependency, bool unaligned, bool mismatched, bool unsafe, uint8_t barrier_data) { + bool require_atomic = true; + LoadLNode* load = new LoadLNode(ctl, mem, adr, adr_type, rt->is_long(), mo, control_dependency, require_atomic); + if (unaligned) { +@@ -930,11 +928,12 @@ LoadLNode* LoadLNode::make_atomic(Node* ctl, Node* mem, Node* adr, const TypePtr + if (unsafe) { + load->set_unsafe_access(); + } ++ load->set_barrier_data(barrier_data); + return load; + } + + LoadDNode* LoadDNode::make_atomic(Node* ctl, Node* mem, Node* adr, const TypePtr* adr_type, const Type* rt, MemOrd mo, +- ControlDependency control_dependency, bool unaligned, bool mismatched, bool unsafe) { ++ ControlDependency control_dependency, bool unaligned, bool mismatched, bool unsafe, uint8_t barrier_data) { + bool require_atomic = true; + LoadDNode* load = new LoadDNode(ctl, mem, adr, adr_type, rt, mo, control_dependency, require_atomic); + if (unaligned) { +@@ -946,6 +945,7 @@ LoadDNode* LoadDNode::make_atomic(Node* ctl, Node* mem, Node* adr, const TypePtr + if (unsafe) { + load->set_unsafe_access(); + } ++ load->set_barrier_data(barrier_data); + return load; + } + +@@ -2891,7 +2891,7 @@ LoadStoreNode::LoadStoreNode( Node *c, Node *mem, Node *adr, Node *val, const Ty : Node(required), _type(rt), _adr_type(at), @@ -4838,7 +5994,7 @@ index 651bbfcf1..3a5e45401 100644 init_req(MemNode::Control, c ); init_req(MemNode::Memory , mem); diff --git a/src/hotspot/share/opto/memnode.hpp b/src/hotspot/share/opto/memnode.hpp -index 75f283ba8..abf07a233 100644 +index d4c2895bf..259b4343f 100644 --- a/src/hotspot/share/opto/memnode.hpp +++ b/src/hotspot/share/opto/memnode.hpp @@ -43,6 +43,8 @@ private: @@ -4915,7 +6071,17 @@ index 75f283ba8..abf07a233 100644 init_class_id(Class_Load); } inline bool is_unordered() const { return !is_acquire(); } -@@ -265,10 +280,6 @@ public: +@@ -213,7 +228,8 @@ public: + static Node* make(PhaseGVN& gvn, Node *c, Node *mem, Node *adr, + const TypePtr* at, const Type *rt, BasicType bt, + MemOrd mo, ControlDependency control_dependency = DependsOnlyOnTest, +- bool unaligned = false, bool mismatched = false, bool unsafe = false); ++ bool unaligned = false, bool mismatched = false, bool unsafe = false, ++ uint8_t barrier_data = 0); + + virtual uint hash() const; // Check the type + +@@ -265,10 +281,6 @@ public: Node* convert_to_unsigned_load(PhaseGVN& gvn); Node* convert_to_signed_load(PhaseGVN& gvn); @@ -4926,7 +6092,25 @@ index 75f283ba8..abf07a233 100644 #ifndef PRODUCT virtual void dump_spec(outputStream *st) const; #endif -@@ -817,7 +828,7 @@ class LoadStoreNode : public Node { +@@ -398,7 +410,7 @@ public: + bool require_atomic_access() const { return _require_atomic_access; } + static LoadLNode* make_atomic(Node* ctl, Node* mem, Node* adr, const TypePtr* adr_type, + const Type* rt, MemOrd mo, ControlDependency control_dependency = DependsOnlyOnTest, +- bool unaligned = false, bool mismatched = false, bool unsafe = false); ++ bool unaligned = false, bool mismatched = false, bool unsafe = false, uint8_t barrier_data = 0); + #ifndef PRODUCT + virtual void dump_spec(outputStream *st) const { + LoadNode::dump_spec(st); +@@ -450,7 +462,7 @@ public: + bool require_atomic_access() const { return _require_atomic_access; } + static LoadDNode* make_atomic(Node* ctl, Node* mem, Node* adr, const TypePtr* adr_type, + const Type* rt, MemOrd mo, ControlDependency control_dependency = DependsOnlyOnTest, +- bool unaligned = false, bool mismatched = false, bool unsafe = false); ++ bool unaligned = false, bool mismatched = false, bool unsafe = false, uint8_t barrier_data = 0); + #ifndef PRODUCT + virtual void dump_spec(outputStream *st) const { + LoadNode::dump_spec(st); +@@ -817,7 +829,7 @@ class LoadStoreNode : public Node { private: const Type* const _type; // What kind of value is loaded? const TypePtr* _adr_type; // What kind of memory is being addressed? @@ -4935,7 +6119,7 @@ index 75f283ba8..abf07a233 100644 virtual uint size_of() const; // Size is bigger public: LoadStoreNode( Node *c, Node *mem, Node *adr, Node *val, const TypePtr* at, const Type* rt, uint required ); -@@ -830,8 +841,9 @@ public: +@@ -831,8 +843,9 @@ public: bool result_not_used() const; MemBarNode* trailing_membar() const; @@ -4947,7 +6131,7 @@ index 75f283ba8..abf07a233 100644 }; class LoadStoreConditionalNode : public LoadStoreNode { -@@ -883,6 +895,7 @@ public: +@@ -885,6 +898,7 @@ public: MemNode::MemOrd order() const { return _mem_ord; } @@ -4955,7 +6139,7 @@ index 75f283ba8..abf07a233 100644 }; class CompareAndExchangeNode : public LoadStoreNode { -@@ -900,6 +913,7 @@ public: +@@ -902,6 +916,7 @@ public: MemNode::MemOrd order() const { return _mem_ord; } @@ -4964,10 +6148,10 @@ index 75f283ba8..abf07a233 100644 //------------------------------CompareAndSwapBNode--------------------------- diff --git a/src/hotspot/share/opto/node.cpp b/src/hotspot/share/opto/node.cpp -index bb020c408..5a5e44ecd 100644 +index e439ebb93..84a56f8d0 100644 --- a/src/hotspot/share/opto/node.cpp +++ b/src/hotspot/share/opto/node.cpp -@@ -546,9 +546,6 @@ Node *Node::clone() const { +@@ -550,9 +550,6 @@ Node *Node::clone() const { if (n->is_SafePoint()) { n->as_SafePoint()->clone_replaced_nodes(); } @@ -4977,7 +6161,7 @@ index bb020c408..5a5e44ecd 100644 return n; // Return the clone } -@@ -1471,10 +1468,6 @@ bool Node::needs_anti_dependence_check() const { +@@ -1478,10 +1475,6 @@ bool Node::needs_anti_dependence_check() const { if( req() < 2 || (_flags & Flag_needs_anti_dependence_check) == 0 ) { return false; } @@ -4989,10 +6173,10 @@ index bb020c408..5a5e44ecd 100644 } diff --git a/src/hotspot/share/opto/node.hpp b/src/hotspot/share/opto/node.hpp -index 15e6ef893..de782b880 100644 +index f3bd41d91..6efaa6fc7 100644 --- a/src/hotspot/share/opto/node.hpp +++ b/src/hotspot/share/opto/node.hpp -@@ -82,8 +82,6 @@ class JVMState; +@@ -83,8 +83,6 @@ class JVMState; class JumpNode; class JumpProjNode; class LoadNode; @@ -5001,7 +6185,7 @@ index 15e6ef893..de782b880 100644 class LoadStoreNode; class LoadStoreConditionalNode; class LockNode; -@@ -645,7 +643,6 @@ public: +@@ -648,7 +646,6 @@ public: DEFINE_CLASS_ID(MemBar, Multi, 3) DEFINE_CLASS_ID(Initialize, MemBar, 0) DEFINE_CLASS_ID(MemBarStoreStore, MemBar, 1) @@ -5009,7 +6193,7 @@ index 15e6ef893..de782b880 100644 DEFINE_CLASS_ID(Mach, Node, 1) DEFINE_CLASS_ID(MachReturn, Mach, 0) -@@ -697,7 +694,6 @@ public: +@@ -700,7 +697,6 @@ public: DEFINE_CLASS_ID(Mem, Node, 4) DEFINE_CLASS_ID(Load, Mem, 0) DEFINE_CLASS_ID(LoadVector, Load, 0) @@ -5017,7 +6201,7 @@ index 15e6ef893..de782b880 100644 DEFINE_CLASS_ID(Store, Mem, 1) DEFINE_CLASS_ID(StoreVector, Store, 0) DEFINE_CLASS_ID(LoadStore, Mem, 2) -@@ -841,8 +837,6 @@ public: +@@ -845,8 +841,6 @@ public: DEFINE_CLASS_QUERY(Load) DEFINE_CLASS_QUERY(LoadStore) DEFINE_CLASS_QUERY(LoadStoreConditional) @@ -5027,7 +6211,7 @@ index 15e6ef893..de782b880 100644 DEFINE_CLASS_QUERY(Loop) DEFINE_CLASS_QUERY(Mach) diff --git a/src/hotspot/share/opto/output.cpp b/src/hotspot/share/opto/output.cpp -index 4ccf75783..f22029256 100644 +index b6540e06a..5b9873b4d 100644 --- a/src/hotspot/share/opto/output.cpp +++ b/src/hotspot/share/opto/output.cpp @@ -32,6 +32,8 @@ @@ -5462,7 +6646,7 @@ index 4ccf75783..f22029256 100644 // Have we run out of code space? if ((cb->blob() == NULL) || (!CompileBroker::should_compile_new_jobs())) { -@@ -1264,12 +1272,12 @@ void Compile::fill_buffer(CodeBuffer* cb, uint* blk_starts) { +@@ -1265,12 +1273,12 @@ void Compile::fill_buffer(CodeBuffer* cb, uint* blk_starts) { Process_OopMap_Node(mach, current_offset); } // End if safepoint @@ -5477,7 +6661,7 @@ index 4ccf75783..f22029256 100644 else if (mach->is_MachBranch()) { // This requires the TRUE branch target be in succs[0] uint block_num = block->non_connector_successor(0)->_pre_order; -@@ -1280,8 +1288,8 @@ void Compile::fill_buffer(CodeBuffer* cb, uint* blk_starts) { +@@ -1281,8 +1289,8 @@ void Compile::fill_buffer(CodeBuffer* cb, uint* blk_starts) { bool delay_slot_is_used = valid_bundle_info(n) && node_bundling(n)->use_unconditional_delay(); if (!delay_slot_is_used && mach->may_be_short_branch()) { @@ -5488,7 +6672,7 @@ index 4ccf75783..f22029256 100644 int offset = blk_starts[block_num] - current_offset; if (block_num >= i) { // Current and following block's offset are not -@@ -1339,7 +1347,7 @@ void Compile::fill_buffer(CodeBuffer* cb, uint* blk_starts) { +@@ -1340,7 +1348,7 @@ void Compile::fill_buffer(CodeBuffer* cb, uint* blk_starts) { } } #ifdef ASSERT @@ -5497,7 +6681,7 @@ index 4ccf75783..f22029256 100644 else if (mach->ideal_Opcode() == Op_StoreCM) { uint storeCM_idx = j; int count = 0; -@@ -1517,6 +1525,10 @@ void Compile::fill_buffer(CodeBuffer* cb, uint* blk_starts) { +@@ -1519,6 +1527,10 @@ void Compile::fill_buffer(CodeBuffer* cb, uint* blk_starts) { } #endif @@ -5508,7 +6692,7 @@ index 4ccf75783..f22029256 100644 #ifndef PRODUCT // Information on the size of the method, without the extraneous code Scheduling::increment_method_size(cb->insts_size()); -@@ -1681,20 +1693,20 @@ uint Scheduling::_total_instructions_per_bundle[Pipeline::_max_instrs_per_cycle+ +@@ -1682,20 +1694,20 @@ uint Scheduling::_total_instructions_per_bundle[Pipeline::_max_instrs_per_cycle+ // Initializer for class Scheduling Scheduling::Scheduling(Arena *arena, Compile &compile) @@ -5542,7 +6726,7 @@ index 4ccf75783..f22029256 100644 #endif { // Create a MachNopNode -@@ -1773,8 +1785,8 @@ void Scheduling::step_and_clear() { +@@ -1774,8 +1786,8 @@ void Scheduling::step_and_clear() { _bundle_use.reset(); memcpy(_bundle_use_elements, @@ -5553,7 +6737,7 @@ index 4ccf75783..f22029256 100644 } // Perform instruction scheduling and bundling over the sequence of -@@ -1801,6 +1813,22 @@ void Compile::ScheduleAndBundle() { +@@ -1802,6 +1814,22 @@ void Compile::ScheduleAndBundle() { // Walk backwards over each basic block, computing the needed alignment // Walk over all the basic blocks scheduling.DoScheduling(); @@ -5576,7 +6760,7 @@ index 4ccf75783..f22029256 100644 } // Compute the latency of all the instructions. This is fairly simple, -@@ -1869,7 +1897,7 @@ bool Scheduling::NodeFitsInBundle(Node *n) { +@@ -1870,7 +1898,7 @@ bool Scheduling::NodeFitsInBundle(Node *n) { #ifndef PRODUCT if (_cfg->C->trace_opto_output()) tty->print("# NodeFitsInBundle [%4d]: FALSE; latency %4d > %d\n", @@ -5585,7 +6769,7 @@ index 4ccf75783..f22029256 100644 #endif return (false); } -@@ -2094,12 +2122,12 @@ void Scheduling::AddNodeToBundle(Node *n, const Block *bb) { +@@ -2095,12 +2123,12 @@ void Scheduling::AddNodeToBundle(Node *n, const Block *bb) { // Don't allow safepoints in the branch shadow, that will // cause a number of difficulties if ( avail_pipeline->instructionCount() == 1 && @@ -5604,7 +6788,7 @@ index 4ccf75783..f22029256 100644 if (d->is_Mach() && !d->is_MachSafePoint()) { // A node that fits in the delay slot was found, so we need to -@@ -2144,13 +2172,13 @@ void Scheduling::AddNodeToBundle(Node *n, const Block *bb) { +@@ -2145,13 +2173,13 @@ void Scheduling::AddNodeToBundle(Node *n, const Block *bb) { // step of the bundles if (!NodeFitsInBundle(n)) { #ifndef PRODUCT @@ -5623,7 +6807,7 @@ index 4ccf75783..f22029256 100644 } } -@@ -2196,8 +2224,8 @@ void Scheduling::AddNodeToBundle(Node *n, const Block *bb) { +@@ -2197,8 +2225,8 @@ void Scheduling::AddNodeToBundle(Node *n, const Block *bb) { #ifndef PRODUCT if (_cfg->C->trace_opto_output()) tty->print("# *** STEP(%d >= %d instructions) ***\n", @@ -5634,7 +6818,7 @@ index 4ccf75783..f22029256 100644 #endif step(1); } -@@ -2403,7 +2431,7 @@ void Scheduling::DoScheduling() { +@@ -2404,7 +2432,7 @@ void Scheduling::DoScheduling() { } assert(!last->is_Mach() || last->as_Mach()->ideal_Opcode() != Op_Con, ""); if( last->is_Catch() || @@ -5643,7 +6827,7 @@ index 4ccf75783..f22029256 100644 // There might be a prior call. Skip it. while (_bb_start < _bb_end && bb->get_node(--_bb_end)->is_MachProj()); } else if( last->is_MachNullCheck() ) { -@@ -2473,7 +2501,7 @@ void Scheduling::DoScheduling() { +@@ -2474,7 +2502,7 @@ void Scheduling::DoScheduling() { } #endif #ifdef ASSERT @@ -5652,7 +6836,7 @@ index 4ccf75783..f22029256 100644 #endif } -@@ -2821,31 +2849,31 @@ void Scheduling::ComputeRegisterAntidependencies(Block *b) { +@@ -2822,31 +2850,31 @@ void Scheduling::ComputeRegisterAntidependencies(Block *b) { // void Scheduling::garbage_collect_pinch_nodes() { #ifndef PRODUCT @@ -5704,7 +6888,7 @@ index 4ccf75783..f22029256 100644 #endif } -@@ -2882,19 +2910,19 @@ void Scheduling::dump_available() const { +@@ -2883,19 +2911,19 @@ void Scheduling::dump_available() const { void Scheduling::print_statistics() { // Print the size added by nops for bundling tty->print("Nops added %d bytes to total of %d bytes", @@ -5728,7 +6912,7 @@ index 4ccf75783..f22029256 100644 tty->print("\n"); } -@@ -2908,6 +2936,6 @@ void Scheduling::print_statistics() { +@@ -2909,6 +2937,6 @@ void Scheduling::print_statistics() { if (total_bundles > 0) tty->print("Average ILP (excluding nops) is %.2f\n", @@ -5752,11 +6936,23 @@ index ab3c1a304..ec3cc2981 100644 }; //------------------------------Scheduling---------------------------------- +diff --git a/src/hotspot/share/opto/parse1.cpp b/src/hotspot/share/opto/parse1.cpp +index 8286f8c4d..78149369d 100644 +--- a/src/hotspot/share/opto/parse1.cpp ++++ b/src/hotspot/share/opto/parse1.cpp +@@ -41,6 +41,7 @@ + #include "runtime/handles.inline.hpp" + #include "runtime/safepointMechanism.hpp" + #include "runtime/sharedRuntime.hpp" ++#include "utilities/bitMap.inline.hpp" + #include "utilities/copy.hpp" + + // Static array so we can figure out which bytecodes stop us from compiling diff --git a/src/hotspot/share/opto/phaseX.cpp b/src/hotspot/share/opto/phaseX.cpp -index 07b849040..9d5d4deed 100644 +index 41971513f..3d71d941c 100644 --- a/src/hotspot/share/opto/phaseX.cpp +++ b/src/hotspot/share/opto/phaseX.cpp -@@ -1648,14 +1648,14 @@ void PhaseIterGVN::add_users_to_worklist( Node *n ) { +@@ -1726,14 +1726,14 @@ void PhaseIterGVN::add_users_to_worklist( Node *n ) { // of the mirror load depends on the type of 'n'. See LoadNode::Value(). // LoadBarrier?(LoadP(LoadP(AddP(foo:Klass, #java_mirror)))) BarrierSetC2* bs = BarrierSet::barrier_set()->barrier_set_c2(); @@ -5773,7 +6969,7 @@ index 07b849040..9d5d4deed 100644 // Search for load barriers behind the load for (DUIterator_Fast i3max, i3 = u->fast_outs(i3max); i3 < i3max; i3++) { Node* b = u->fast_out(i3); -@@ -1818,14 +1818,14 @@ void PhaseCCP::analyze() { +@@ -1927,14 +1927,14 @@ void PhaseCCP::analyze() { // Loading the java mirror from a Klass requires two loads and the type // of the mirror load depends on the type of 'n'. See LoadNode::Value(). BarrierSetC2* bs = BarrierSet::barrier_set()->barrier_set_c2(); @@ -5791,10 +6987,10 @@ index 07b849040..9d5d4deed 100644 for (DUIterator_Fast i3max, i3 = u->fast_outs(i3max); i3 < i3max; i3++) { Node* b = u->fast_out(i3); diff --git a/src/hotspot/share/opto/vectornode.cpp b/src/hotspot/share/opto/vectornode.cpp -index 0258db3e6..fae147fa8 100644 +index 1ee9db8f0..1f2cf2c64 100644 --- a/src/hotspot/share/opto/vectornode.cpp +++ b/src/hotspot/share/opto/vectornode.cpp -@@ -264,7 +264,6 @@ void VectorNode::vector_operands(Node* n, uint* start, uint* end) { +@@ -286,7 +286,6 @@ void VectorNode::vector_operands(Node* n, uint* start, uint* end) { case Op_LoadI: case Op_LoadL: case Op_LoadF: case Op_LoadD: case Op_LoadP: case Op_LoadN: @@ -5802,3 +6998,193 @@ index 0258db3e6..fae147fa8 100644 *start = 0; *end = 0; // no vector operands break; +diff --git a/src/hotspot/share/runtime/sharedRuntime.cpp b/src/hotspot/share/runtime/sharedRuntime.cpp +index 595ff7495..3f366633e 100644 +--- a/src/hotspot/share/runtime/sharedRuntime.cpp ++++ b/src/hotspot/share/runtime/sharedRuntime.cpp +@@ -205,6 +205,8 @@ void SharedRuntime::print_ic_miss_histogram() { + } + #endif // PRODUCT + ++int SharedRuntime::_monotonical_incr = 0; ++bool SharedRuntime::_opt_for_aarch64 = false; + + JRT_LEAF(jlong, SharedRuntime::lmul(jlong y, jlong x)) + return x * y; +diff --git a/src/hotspot/share/runtime/sharedRuntime.hpp b/src/hotspot/share/runtime/sharedRuntime.hpp +index a11009837..eba82d453 100644 +--- a/src/hotspot/share/runtime/sharedRuntime.hpp ++++ b/src/hotspot/share/runtime/sharedRuntime.hpp +@@ -596,6 +596,11 @@ class SharedRuntime: AllStatic { + static void print_ic_miss_histogram(); + + #endif // PRODUCT ++ ++ static int _monotonical_incr; ++ static bool _opt_for_aarch64; ++ ++ static address monotonical_incr_addr() { return (address)&_monotonical_incr; } + }; + + +diff --git a/src/hotspot/share/utilities/bitMap.hpp b/src/hotspot/share/utilities/bitMap.hpp +index c671535c9..e26f34687 100644 +--- a/src/hotspot/share/utilities/bitMap.hpp ++++ b/src/hotspot/share/utilities/bitMap.hpp +@@ -26,6 +26,7 @@ + #define SHARE_VM_UTILITIES_BITMAP_HPP + + #include "memory/allocation.hpp" ++#include "runtime/atomic.hpp" + #include "utilities/align.hpp" + #include "utilities/globalDefinitions.hpp" + +@@ -95,6 +96,8 @@ class BitMap { + void set_word (idx_t word) { set_word(word, ~(bm_word_t)0); } + void clear_word(idx_t word) { _map[word] = 0; } + ++ static inline const bm_word_t load_word_ordered(const volatile bm_word_t* const addr, atomic_memory_order memory_order); ++ + // Utilities for ranges of bits. Ranges are half-open [beg, end). + + // Ranges within a single word. +@@ -194,6 +197,9 @@ class BitMap { + return (*word_addr(index) & bit_mask(index)) != 0; + } + ++ // memory_order must be memory_order_relaxed or memory_order_acquire. ++ bool par_at(idx_t index, atomic_memory_order memory_order = memory_order_acquire) const; ++ + // Align bit index up or down to the next bitmap word boundary, or check + // alignment. + static idx_t word_align_up(idx_t bit) { +@@ -210,9 +216,14 @@ class BitMap { + inline void set_bit(idx_t bit); + inline void clear_bit(idx_t bit); + +- // Atomically set or clear the specified bit. +- inline bool par_set_bit(idx_t bit); +- inline bool par_clear_bit(idx_t bit); ++ // Attempts to change a bit to a desired value. The operation returns true if ++ // this thread changed the value of the bit. It was changed with a RMW operation ++ // using the specified memory_order. The operation returns false if the change ++ // could not be set due to the bit already being observed in the desired state. ++ // The atomic access that observed the bit in the desired state has acquire ++ // semantics, unless memory_order is memory_order_relaxed or memory_order_release. ++ inline bool par_set_bit(idx_t bit, atomic_memory_order memory_order = memory_order_conservative); ++ inline bool par_clear_bit(idx_t bit, atomic_memory_order memory_order = memory_order_conservative); + + // Put the given value at the given offset. The parallel version + // will CAS the value into the bitmap and is quite a bit slower. +diff --git a/src/hotspot/share/utilities/bitMap.inline.hpp b/src/hotspot/share/utilities/bitMap.inline.hpp +index b10726d18..7a7e2ad43 100644 +--- a/src/hotspot/share/utilities/bitMap.inline.hpp ++++ b/src/hotspot/share/utilities/bitMap.inline.hpp +@@ -26,6 +26,7 @@ + #define SHARE_VM_UTILITIES_BITMAP_INLINE_HPP + + #include "runtime/atomic.hpp" ++#include "runtime/orderAccess.hpp" + #include "utilities/bitMap.hpp" + + inline void BitMap::set_bit(idx_t bit) { +@@ -38,18 +39,39 @@ inline void BitMap::clear_bit(idx_t bit) { + *word_addr(bit) &= ~bit_mask(bit); + } + +-inline bool BitMap::par_set_bit(idx_t bit) { ++inline const BitMap::bm_word_t BitMap::load_word_ordered(const volatile bm_word_t* const addr, atomic_memory_order memory_order) { ++ if (memory_order == memory_order_relaxed || memory_order == memory_order_release) { ++ return Atomic::load(addr); ++ } else { ++ assert(memory_order == memory_order_acq_rel || ++ memory_order == memory_order_acquire || ++ memory_order == memory_order_conservative, ++ "unexpected memory ordering"); ++ return OrderAccess::load_acquire(addr); ++ } ++} ++ ++inline bool BitMap::par_at(idx_t index, atomic_memory_order memory_order) const { ++ verify_index(index); ++ assert(memory_order == memory_order_acquire || ++ memory_order == memory_order_relaxed, ++ "unexpected memory ordering"); ++ const volatile bm_word_t* const addr = word_addr(index); ++ return (load_word_ordered(addr, memory_order) & bit_mask(index)) != 0; ++} ++ ++inline bool BitMap::par_set_bit(idx_t bit, atomic_memory_order memory_order) { + verify_index(bit); + volatile bm_word_t* const addr = word_addr(bit); + const bm_word_t mask = bit_mask(bit); +- bm_word_t old_val = *addr; ++ bm_word_t old_val = load_word_ordered(addr, memory_order); + + do { + const bm_word_t new_val = old_val | mask; + if (new_val == old_val) { + return false; // Someone else beat us to it. + } +- const bm_word_t cur_val = Atomic::cmpxchg(new_val, addr, old_val); ++ const bm_word_t cur_val = Atomic::cmpxchg(new_val, addr, old_val, memory_order); + if (cur_val == old_val) { + return true; // Success. + } +@@ -57,18 +79,18 @@ inline bool BitMap::par_set_bit(idx_t bit) { + } while (true); + } + +-inline bool BitMap::par_clear_bit(idx_t bit) { ++inline bool BitMap::par_clear_bit(idx_t bit, atomic_memory_order memory_order) { + verify_index(bit); + volatile bm_word_t* const addr = word_addr(bit); + const bm_word_t mask = ~bit_mask(bit); +- bm_word_t old_val = *addr; ++ bm_word_t old_val = load_word_ordered(addr, memory_order); + + do { + const bm_word_t new_val = old_val & mask; + if (new_val == old_val) { + return false; // Someone else beat us to it. + } +- const bm_word_t cur_val = Atomic::cmpxchg(new_val, addr, old_val); ++ const bm_word_t cur_val = Atomic::cmpxchg(new_val, addr, old_val, memory_order); + if (cur_val == old_val) { + return true; // Success. + } +diff --git a/src/java.base/share/classes/java/util/Random.java b/src/java.base/share/classes/java/util/Random.java +index 92c1193cb..aaf3da581 100644 +--- a/src/java.base/share/classes/java/util/Random.java ++++ b/src/java.base/share/classes/java/util/Random.java +@@ -35,6 +35,7 @@ import java.util.stream.LongStream; + import java.util.stream.StreamSupport; + + import jdk.internal.misc.Unsafe; ++import jdk.internal.HotSpotIntrinsicCandidate; + + /** + * An instance of this class is used to generate a stream of +@@ -325,6 +326,7 @@ class Random implements java.io.Serializable { + * @return the next pseudorandom, uniformly distributed {@code int} + * value from this random number generator's sequence + */ ++ @HotSpotIntrinsicCandidate + public int nextInt() { + return next(32); + } +diff --git a/test/hotspot/jtreg/runtime/MemberName/MemberNameLeak.java b/test/hotspot/jtreg/runtime/MemberName/MemberNameLeak.java +index a8aff4775..afadfd68a 100644 +--- a/test/hotspot/jtreg/runtime/MemberName/MemberNameLeak.java ++++ b/test/hotspot/jtreg/runtime/MemberName/MemberNameLeak.java +@@ -75,6 +75,7 @@ public class MemberNameLeak { + test("-XX:+UseG1GC"); + test("-XX:+UseParallelGC"); + test("-XX:+UseSerialGC"); ++ test("-XX:+UseZGC"); + if (!Compiler.isGraalEnabled()) { // Graal does not support CMS and Shenandoah + test("-XX:+UseConcMarkSweepGC"); + if (GC.Shenandoah.isSupported()) { +-- +2.19.1 + diff --git a/ZGC-aarch64-fix-not-using-load-store-Pre-index.patch b/ZGC-aarch64-fix-not-using-load-store-Pre-index.patch deleted file mode 100644 index 36e79419c2f2232ff6f6560333f38d90a286bd8d..0000000000000000000000000000000000000000 --- a/ZGC-aarch64-fix-not-using-load-store-Pre-index.patch +++ /dev/null @@ -1,58 +0,0 @@ -From e8bf6d9c5a02b3ffaf223dd1109bc15c664cca28 Mon Sep 17 00:00:00 2001 -Date: Mon, 24 Feb 2020 18:51:09 +0800 -Subject: [PATCH] ZGC: aarch64: fix not using load/store Pre-indexed - addressing to modify sp - -Summary: : -LLT: JFUZZ -Bug url: ---- - src/hotspot/cpu/aarch64/macroAssembler_aarch64.cpp | 16 +++++----------- - 1 file changed, 5 insertions(+), 11 deletions(-) - -diff --git a/src/hotspot/cpu/aarch64/macroAssembler_aarch64.cpp b/src/hotspot/cpu/aarch64/macroAssembler_aarch64.cpp -index a65a605d0..6db979b57 100644 ---- a/src/hotspot/cpu/aarch64/macroAssembler_aarch64.cpp -+++ b/src/hotspot/cpu/aarch64/macroAssembler_aarch64.cpp -@@ -2114,12 +2114,11 @@ int MacroAssembler::push_fp(unsigned int bitset, Register stack) { - return 0; - } - -+ add(stack, stack, -count * wordSize * 2); -+ - if (count & 1) { -- strq(as_FloatRegister(regs[0]), Address(pre(stack, -count * wordSize * 2))); -+ strq(as_FloatRegister(regs[0]), Address(stack)); - i += 1; -- } else { -- stpq(as_FloatRegister(regs[0]), as_FloatRegister(regs[1]), Address(pre(stack, -count * wordSize * 2))); -- i += 2; - } - - for (; i < count; i += 2) { -@@ -2145,20 +2144,15 @@ int MacroAssembler::pop_fp(unsigned int bitset, Register stack) { - } - - if (count & 1) { -+ ldrq(as_FloatRegister(regs[0]), Address(stack)); - i += 1; -- } else { -- i += 2; - } - - for (; i < count; i += 2) { - ldpq(as_FloatRegister(regs[i]), as_FloatRegister(regs[i+1]), Address(stack, i * wordSize * 2)); - } - -- if ((count & 1) == 0) { -- ldpq(as_FloatRegister(regs[0]), as_FloatRegister(regs[1]), Address(post(stack, count * wordSize * 2))); -- } else { -- ldrq(as_FloatRegister(regs[0]), Address(post(stack, count * wordSize * 2))); -- } -+ add(stack, stack, count * wordSize * 2); - - return count; - } --- -2.12.3 - diff --git a/ZGC-aarch64-fix-system-call-number-of-memfd_create.patch b/ZGC-aarch64-fix-system-call-number-of-memfd_create.patch deleted file mode 100644 index ee83a44e005449868c4200cf86fe552ca184d75e..0000000000000000000000000000000000000000 --- a/ZGC-aarch64-fix-system-call-number-of-memfd_create.patch +++ /dev/null @@ -1,28 +0,0 @@ -From e25b331a945301e24429c120bef1ed0daf04d49c Mon Sep 17 00:00:00 2001 -Date: Fri, 3 Apr 2020 17:12:16 +0800 -Subject: [PATCH] ZGC: aarch64: Fix MR 32, fix system call number of - memfd_create - -Summary: : -LLT: N/A -Bug url: N/A ---- - src/hotspot/os_cpu/linux_aarch64/gc/z/zBackingFile_linux_aarch64.cpp | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/src/hotspot/os_cpu/linux_aarch64/gc/z/zBackingFile_linux_aarch64.cpp b/src/hotspot/os_cpu/linux_aarch64/gc/z/zBackingFile_linux_aarch64.cpp -index 47894b5..f956b53 100644 ---- a/src/hotspot/os_cpu/linux_aarch64/gc/z/zBackingFile_linux_aarch64.cpp -+++ b/src/hotspot/os_cpu/linux_aarch64/gc/z/zBackingFile_linux_aarch64.cpp -@@ -51,7 +51,7 @@ - - // Support for building on older Linux systems - #ifndef __NR_memfd_create --#define __NR_memfd_create 319 -+#define __NR_memfd_create 279 - #endif - #ifndef MFD_CLOEXEC - #define MFD_CLOEXEC 0x0001U --- -1.8.3.1 - diff --git a/ZGC-aarch64-not-using-zr-register-avoid-sigill-in-Ma.patch b/ZGC-aarch64-not-using-zr-register-avoid-sigill-in-Ma.patch deleted file mode 100644 index 38cac065a20a19b849e73c1718ace4df962f2025..0000000000000000000000000000000000000000 --- a/ZGC-aarch64-not-using-zr-register-avoid-sigill-in-Ma.patch +++ /dev/null @@ -1,106 +0,0 @@ -From 425112071e77e2fb599d1f96ce48689d45461261 Mon Sep 17 00:00:00 2001 -Date: Mon, 17 Feb 2020 18:55:47 +0800 -Subject: [PATCH] ZGC: aarch64: not using zr register avoid sigill in - MacroAssembler::push_fp and pop_fp - -Summary: : -LLT: jtreg -Bug url: ---- - src/hotspot/cpu/aarch64/macroAssembler_aarch64.cpp | 48 +++++++++++++--------- - 1 file changed, 28 insertions(+), 20 deletions(-) - -diff --git a/src/hotspot/cpu/aarch64/macroAssembler_aarch64.cpp b/src/hotspot/cpu/aarch64/macroAssembler_aarch64.cpp -index 611f13b0e..a65a605d0 100644 ---- a/src/hotspot/cpu/aarch64/macroAssembler_aarch64.cpp -+++ b/src/hotspot/cpu/aarch64/macroAssembler_aarch64.cpp -@@ -2100,58 +2100,66 @@ int MacroAssembler::pop(unsigned int bitset, Register stack) { - // Push lots of registers in the bit set supplied. Don't push sp. - // Return the number of words pushed - int MacroAssembler::push_fp(unsigned int bitset, Register stack) { -- int words_pushed = 0; -- - // Scan bitset to accumulate register pairs - unsigned char regs[32]; - int count = 0; -+ int i = 0; - for (int reg = 0; reg <= 31; reg++) { - if (1 & bitset) - regs[count++] = reg; - bitset >>= 1; - } -- regs[count++] = zr->encoding_nocheck(); -- count &= ~1; // Only push an even number of regs - -- // Always pushing full 128 bit registers. -- if (count) { -+ if (!count) { -+ return 0; -+ } -+ -+ if (count & 1) { -+ strq(as_FloatRegister(regs[0]), Address(pre(stack, -count * wordSize * 2))); -+ i += 1; -+ } else { - stpq(as_FloatRegister(regs[0]), as_FloatRegister(regs[1]), Address(pre(stack, -count * wordSize * 2))); -- words_pushed += 2; -+ i += 2; - } -- for (int i = 2; i < count; i += 2) { -+ -+ for (; i < count; i += 2) { - stpq(as_FloatRegister(regs[i]), as_FloatRegister(regs[i+1]), Address(stack, i * wordSize * 2)); -- words_pushed += 2; - } - -- assert(words_pushed == count, "oops, pushed != count"); - return count; - } - - int MacroAssembler::pop_fp(unsigned int bitset, Register stack) { -- int words_pushed = 0; -- - // Scan bitset to accumulate register pairs - unsigned char regs[32]; - int count = 0; -+ int i = 0; - for (int reg = 0; reg <= 31; reg++) { - if (1 & bitset) - regs[count++] = reg; - bitset >>= 1; - } -- regs[count++] = zr->encoding_nocheck(); -- count &= ~1; - -- for (int i = 2; i < count; i += 2) { -+ if (!count) { -+ return 0; -+ } -+ -+ if (count & 1) { -+ i += 1; -+ } else { -+ i += 2; -+ } -+ -+ for (; i < count; i += 2) { - ldpq(as_FloatRegister(regs[i]), as_FloatRegister(regs[i+1]), Address(stack, i * wordSize * 2)); -- words_pushed += 2; - } -- if (count) { -+ -+ if ((count & 1) == 0) { - ldpq(as_FloatRegister(regs[0]), as_FloatRegister(regs[1]), Address(post(stack, count * wordSize * 2))); -- words_pushed += 2; -+ } else { -+ ldrq(as_FloatRegister(regs[0]), Address(post(stack, count * wordSize * 2))); - } - -- assert(words_pushed == count, "oops, pushed != count"); -- - return count; - } - --- -2.12.3 - diff --git a/ZGC-reuse-entries-of-ResolvedMethodTable.patch b/ZGC-reuse-entries-of-ResolvedMethodTable.patch deleted file mode 100644 index ce91594255e2e203e1e963f4671eaebc79da31ad..0000000000000000000000000000000000000000 --- a/ZGC-reuse-entries-of-ResolvedMethodTable.patch +++ /dev/null @@ -1,35 +0,0 @@ -diff --git a/src/hotspot/share/gc/z/zHeap.cpp b/src/hotspot/share/gc/z/zHeap.cpp -index 62f97d2..e950acf 100644 ---- a/src/hotspot/share/gc/z/zHeap.cpp -+++ b/src/hotspot/share/gc/z/zHeap.cpp -@@ -49,6 +49,7 @@ - #include "runtime/thread.hpp" - #include "utilities/align.hpp" - #include "utilities/debug.hpp" -+#include "prims/resolvedMethodTable.hpp" - - static const ZStatSampler ZSamplerHeapUsedBeforeMark("Memory", "Heap Used Before Mark", ZStatUnitBytes); - static const ZStatSampler ZSamplerHeapUsedAfterMark("Memory", "Heap Used After Mark", ZStatUnitBytes); -@@ -334,6 +335,10 @@ bool ZHeap::mark_end() { - Universe::verify(); - } - -+ // Free unsed entries of ResolvedMethodTable and weakhandles -+ // avoid ResolvedMethodTable inflation and native memory leak -+ ResolvedMethodTable::unlink(); -+ - return true; - } - -diff --git a/test/hotspot/jtreg/runtime/MemberName/MemberNameLeak.java b/test/hotspot/jtreg/runtime/MemberName/MemberNameLeak.java -index a8aff47..afadfd6 100644 ---- a/test/hotspot/jtreg/runtime/MemberName/MemberNameLeak.java -+++ b/test/hotspot/jtreg/runtime/MemberName/MemberNameLeak.java -@@ -75,6 +75,7 @@ public class MemberNameLeak { - test("-XX:+UseG1GC"); - test("-XX:+UseParallelGC"); - test("-XX:+UseSerialGC"); -+ test("-XX:+UseZGC"); - if (!Compiler.isGraalEnabled()) { // Graal does not support CMS and Shenandoah - test("-XX:+UseConcMarkSweepGC"); - if (GC.Shenandoah.isSupported()) { diff --git a/add-missing-inline.patch b/add-missing-inline.patch deleted file mode 100644 index 5647d021b0af320803df223e49f394a9c270bd9e..0000000000000000000000000000000000000000 --- a/add-missing-inline.patch +++ /dev/null @@ -1,12 +0,0 @@ -diff --git a/src/hotspot/cpu/x86/gc/z/zBarrierSetAssembler_x86.cpp b/src/hotspot/cpu/x86/gc/z/zBarrierSetAssembler_x86.cpp -index 18f455086..785470dbe 100644 ---- a/src/hotspot/cpu/x86/gc/z/zBarrierSetAssembler_x86.cpp -+++ b/src/hotspot/cpu/x86/gc/z/zBarrierSetAssembler_x86.cpp -@@ -24,6 +24,7 @@ - #include "precompiled.hpp" - #include "asm/macroAssembler.inline.hpp" - #include "code/codeBlob.hpp" -+#include "code/vmreg.inline.hpp" - #include "gc/z/zBarrier.inline.hpp" - #include "gc/z/zBarrierSet.hpp" - #include "gc/z/zBarrierSetAssembler.hpp" diff --git a/delete_expired_certificates.patch b/delete_expired_certificates.patch index 69ce39e728041cec66eef29bf8f97ade08eb2971..3e654b7774f145bca6cee0a764b16d15dd779cde 100644 --- a/delete_expired_certificates.patch +++ b/delete_expired_certificates.patch @@ -120,14 +120,14 @@ index 122a01901..c131bd493 100644 + File.separator + "security" + File.separator + "cacerts"; // The numbers of certs now. -- private static final int COUNT = 108; -+ private static final int COUNT = 105; +- private static final int COUNT = 110; ++ private static final int COUNT = 107; // SHA-256 of cacerts, can be generated with // shasum -a 256 cacerts | sed -e 's/../&:/g' | tr '[:lower:]' '[:upper:]' | cut -c1-95 private static final String CHECKSUM -- = "81:D4:84:F6:92:78:A4:82:25:06:DC:42:25:C9:5D:6C:63:E4:99:CE:BC:ED:66:B3:8C:BA:E6:BA:6B:34:0F:01"; -+ = "2F:05:4C:2D:16:ED:2B:56:D6:07:03:A9:49:C4:A2:E6:16:2C:0D:92:FD:C8:6C:28:DF:77:26:A9:E7:D8:12:47"; +- = "C1:68:B4:AC:51:BF:B5:C6:FD:20:69:17:E1:AF:E4:5B:01:9B:AA:3F:C3:9A:80:A8:51:53:74:2C:A2:04:B0:FF"; ++ = "D5:F6:74:0F:13:CF:6D:35:5E:10:04:C3:1B:57:C4:F4:A0:49:9A:26:38:89:53:C3:71:10:60:9D:48:20:E7:DE"; // map of cert alias to SHA-256 fingerprint @SuppressWarnings("serial") diff --git a/jdk-updates-jdk11u-jdk-11.0.24-ga.tar.xz b/jdk-updates-jdk11u-jdk-11.0.24-ga.tar.xz new file mode 100644 index 0000000000000000000000000000000000000000..c3b680936f71b4b5745b63aeccf1de5513b3e85a Binary files /dev/null and b/jdk-updates-jdk11u-jdk-11.0.24-ga.tar.xz differ diff --git a/openjdk-11.spec b/openjdk-11.spec index 37893e3cebb371dee16840785b0141f47188dd18..4c6ad12e3e6f55e6635431cd66ecd85e07656078 100644 --- a/openjdk-11.spec +++ b/openjdk-11.spec @@ -125,13 +125,18 @@ # New Version-String scheme-style defines %global majorver 11 -%global securityver 23 +%global securityver 24 # buildjdkver is usually same as %%{majorver}, # but in time of bootstrap of next jdk, it is majorver-1, # and this it is better to change it here, on single place %global buildjdkver %{majorver} +%ifnarch loongarch64 ppc64le %global vendor_version_string Bisheng +%endif +%ifarch loongarch64 +%global vendor_version_string Loongson +%endif # Define IcedTea version used for SystemTap tapsets and desktop file %global icedteaver 3.15.0 @@ -141,12 +146,12 @@ %global origin_nice OpenJDK %global top_level_dir_name %{origin} %global minorver 0 -%global buildver 9 +%global buildver 8 %global patchver 0 %global project jdk-updates %global repo jdk11u -%global revision jdk-11.0.23-ga +%global revision jdk-11.0.24-ga %global full_revision %{project}-%{repo}-%{revision} # priority must be 7 digits in total # setting to 1, so debug ones can have 0 @@ -757,7 +762,7 @@ Provides: java-src%{?1} = %{epoch}:%{version}-%{release} Name: java-%{javaver}-%{origin} Version: %{newjavaver}.%{buildver} -Release: 1 +Release: 0 # java-1.5.0-ibm from jpackage.org set Epoch to 1 for unknown reasons # and this change was brought into RHEL-4. java-1.5.0-ibm packages # also included the epoch in their virtual provides. This created a @@ -829,18 +834,7 @@ Patch2001: LoongArch64-support.patch Patch5: Add-ability-to-configure-third-port-for-remote-JMX.patch Patch6: 8214527-AArch64-ZGC-for-Aarch64.patch Patch7: 8224675-Late-GC-barrier-insertion-for-ZGC.patch -Patch9: ZGC-Redesign-C2-load-barrier-to-expand-on-th.patch -Patch10: ZGC-aarch64-not-using-zr-register-avoid-sigill-in-Ma.patch -Patch11: 8217856-ZGC-Break-out-C2-matching-rules-into-separat.patch -Patch12: 8233073-Make-BitMap-accessors-more-memory-ordering-f.patch -Patch13: 8233061-ZGC-Enforce-memory-ordering-in-segmented-bit.patch -Patch18: 8209375-ZGC-Use-dynamic-base-address-for-mark-stack-.patch -Patch20: 8209894-ZGC-Cap-number-of-GC-workers-based-on-heap-s.patch -Patch22: 8233506-ZGC-the-load-for-Reference.get-can-be-conver.patch -Patch23: add-missing-inline.patch -Patch26: ZGC-aarch64-fix-system-call-number-of-memfd_create.patch -Patch27: ZGC-aarch64-fix-not-using-load-store-Pre-index.patch -Patch29: ZGC-reuse-entries-of-ResolvedMethodTable.patch +Patch9: ZGC-AArch64-Optimizations-and-Fixes.patch # 11.0.8 Patch33: 8210473-JEP-345-NUMA-Aware-Memory-Allocation-for-G1.patch @@ -905,6 +899,9 @@ Patch91: 8222289-Overhaul-logic-for-reading-writing-constant-pool-entries.patch # 11.0.21 Patch92: 8295068-SSLEngine-throws-NPE-parsing-Certificate.patch + +# 11.0.23 +Patch93: Cache-byte-when-constructing-String-with-duplicate-c.patch ############################################ # # riscv64 specific patches @@ -1151,17 +1148,6 @@ pushd %{top_level_dir_name} %patch6 -p1 %patch7 -p1 %patch9 -p1 -%patch10 -p1 -%patch11 -p1 -%patch12 -p1 -%patch13 -p1 -%patch18 -p1 -%patch20 -p1 -%patch22 -p1 -%patch23 -p1 -%patch26 -p1 -%patch27 -p1 -%patch29 -p1 %patch33 -p1 %patch34 -p1 %patch35 -p1 @@ -1207,6 +1193,7 @@ pushd %{top_level_dir_name} %patch90 -p1 %patch91 -p1 %patch92 -p1 +%patch93 -p1 %endif %endif %ifarch loongarch64 @@ -1302,9 +1289,12 @@ bash ../configure \ --with-version-build=%{buildver} \ --with-version-pre="" \ --with-version-opt="" \ -%ifnarch loongarch64 ppc64le --with-vendor-version-string="%{vendor_version_string}" \ +%ifnarch loongarch64 ppc64le --with-vendor-name="Bisheng" \ +%endif +%ifarch loongarch64 + --with-vendor-name="Loongson" \ %endif --with-vendor-url="https://openeuler.org/" \ --with-vendor-bug-url="https://gitee.com/src-openeuler/openjdk-11/issues/" \ @@ -1725,12 +1715,31 @@ cjc.mainProgram(arg) %changelog +* Thu July 18 2024 DXwangg - 1.11.0.24.8-0 +- update to 11.0.24+8(GA) + +* Thu Jun 20 2024 aoqi - 1.11.0.23.9-6 +- update LoongArch64 port to 11.0.23 + +* Tue Jun 18 2024 neu-mobi - 1.11.0.23.9-5 +- fix potential compilation errors + +* Sat Jun 15 2024 neu-mobi - 1.11.0.23.9-4 +- Collate patches and merge patches related to ZGC + +* Mon Jun 03 2024 songliyang - 1:11.0.23.9-3 +- fix loongarch vendor error +- fix changelog error + +* Wed May 08 2024 zhangxianting - 1:11.0.23.9-2 +- recompress the source0 + * Mon Apr 29 2024 huangjie - 1:11.0.23.9-1 - modified delete_expired_certificates.patch * Thu Apr 18 2024 huangjie - 1:11.0.23.9-0 - modified 8224675-Late-GC-barrier-insertion-for-ZGC.patch -- modified delete_expired_certificates.patch +- modified delete_expired_certificates.patch * Wed Mar 13 2024 jiahua.yu - 1:11.0.22.7-3 - init support for arch ppc64le @@ -1752,22 +1761,22 @@ cjc.mainProgram(arg) * Thu Oct 19 2023 DXwangg - 1:11.0.21.9-0 - update to 11.0.21+9(GA) - modified delete_expired_certificates.patch -- modified G1-iterate-region-by-bitmap-rather-than-obj-size-in.patch +- modified G1-iterate-region-by-bitmap-rather-than-obj-size-in.patch - modified 8210473-JEP-345-NUMA-Aware-Memory-Allocation-for-G1.patch - modified 8214527-AArch64-ZGC-for-Aarch64.patch * Thu Aug 17 2023 misaka00251 - 1:11.0.20.8-2 - Add riscv64 support (based on bishengjdk riscv branch) -* Wed Aug 2023 noah - 1:11.0.20.8-1 +* Wed Aug 16 2023 noah - 1:11.0.20.8-1 - fix CPUBench kmeans random fails -* Wed Jul 2023 DXwangg - 1:11.0.20.8-0 +* Tue Jul 25 2023 DXwangg - 1:11.0.20.8-0 - update to 11.0.20+8(GA) - modified delete_expired_certificates.patch -* Thu Apr 2023 DXwangg - 1:11.0.19.7-0 +* Sun Apr 23 2023 DXwangg - 1:11.0.19.7-0 - update to 11.0.19+7(GA) - deleted 8225648-TESTBUG-java-lang-annotation-loaderLeak-Main.patch - modified Add-KAE-implementation.patch