diff --git a/Add-riscv64-support.patch b/Add-riscv64-support.patch index b06b0fe866fb0ae52a579323d4ef4e80effd0c9b..7e2d50c2e6427d152e7f6a395a5bcf81883b5a40 100644 --- a/Add-riscv64-support.patch +++ b/Add-riscv64-support.patch @@ -1,5 +1,5 @@ diff --git a/.github/workflows/build-cross-compile.yml b/.github/workflows/build-cross-compile.yml -index 385b097b9f..b1c333f711 100644 +index 385b097b9f..4eebe79871 100644 --- a/.github/workflows/build-cross-compile.yml +++ b/.github/workflows/build-cross-compile.yml @@ -54,28 +54,39 @@ jobs: @@ -36,7 +36,7 @@ index 385b097b9f..b1c333f711 100644 + - target-cpu: riscv64 + gnu-arch: riscv64 + debian-arch: riscv64 -+ debian-repository: https://httpredir.debian.org/debian/ ++ debian-repository: https://snapshot.debian.org/archive/debian/20240228T034848Z/ + debian-version: sid + tolerate-sysroot-errors: true @@ -85,8 +85,74 @@ index 385b097b9f..b1c333f711 100644 make-target: 'hotspot ${{ inputs.make-arguments }}' platform: linux-${{ matrix.target-cpu }} + if: steps.create-sysroot.outcome == 'success' || steps.get-cached-sysroot.outputs.cache-hit == 'true' +diff --git a/.github/workflows/build-macos.yml b/.github/workflows/build-macos.yml +index 4186c451b7..678f5a038e 100644 +--- a/.github/workflows/build-macos.yml ++++ b/.github/workflows/build-macos.yml +@@ -55,7 +55,7 @@ on: + jobs: + build-macos: + name: build +- runs-on: macos-13 ++ runs-on: macos-12 + + strategy: + fail-fast: false +diff --git a/.github/workflows/main.yml b/.github/workflows/main.yml +index 78a8e1e0d4..46cae3afbf 100644 +--- a/.github/workflows/main.yml ++++ b/.github/workflows/main.yml +@@ -223,7 +223,7 @@ jobs: + uses: ./.github/workflows/build-macos.yml + with: + platform: macos-x64 +- xcode-toolset-version: '14.3.1' ++ xcode-toolset-version: '13.4.1' + configure-arguments: ${{ github.event.inputs.configure-arguments }} + make-arguments: ${{ github.event.inputs.make-arguments }} + if: needs.select.outputs.macos-x64 == 'true' +@@ -234,7 +234,7 @@ jobs: + uses: ./.github/workflows/build-macos.yml + with: + platform: macos-aarch64 +- xcode-toolset-version: '14.3.1' ++ xcode-toolset-version: '13.4.1' + extra-conf-options: '--openjdk-target=aarch64-apple-darwin' + configure-arguments: ${{ github.event.inputs.configure-arguments }} + make-arguments: ${{ github.event.inputs.make-arguments }} +@@ -298,7 +298,7 @@ jobs: + with: + platform: macos-x64 + bootjdk-platform: macos-x64 +- runs-on: macos-13 ++ runs-on: macos-12 + + test-windows-x64: + name: windows-x64 +@@ -341,7 +341,7 @@ jobs: + -H 'Accept: application/vnd.github+json' \ + -H 'Authorization: Bearer ${{ github.token }}' \ + -H 'X-GitHub-Api-Version: 2022-11-28' \ +- '${{ github.api_url }}/repos/${{ github.repository }}/actions/runs/${{ github.run_id }}/artifacts')" ++ '${{ github.api_url }}/repos/${{ github.repository }}/actions/runs/${{ github.run_id }}/artifacts?per_page=100')" + BUNDLE_ARTIFACT_IDS="$(echo "$ALL_ARTIFACT_IDS" | jq -r -c '.artifacts | map(select(.name|startswith("bundles-"))) | .[].id')" + for id in $BUNDLE_ARTIFACT_IDS; do + echo "Removing $id" +diff --git a/.github/workflows/test.yml b/.github/workflows/test.yml +index c3560f2135..dacf8eaba1 100644 +--- a/.github/workflows/test.yml ++++ b/.github/workflows/test.yml +@@ -127,7 +127,7 @@ jobs: + run: | + # On macOS we need to install some dependencies for testing + brew install make +- sudo xcode-select --switch /Applications/Xcode_14.3.1.app/Contents/Developer ++ sudo xcode-select --switch /Applications/Xcode_13.4.1.app/Contents/Developer + # This will make GNU make available as 'make' and not only as 'gmake' + echo '/usr/local/opt/make/libexec/gnubin' >> $GITHUB_PATH + if: runner.os == 'macOS' diff --git a/.jcheck/conf b/.jcheck/conf -index be7ad6d26f..e35eb77696 100644 +index 5636278120..d13b1bf5e8 100644 --- a/.jcheck/conf +++ b/.jcheck/conf @@ -1,5 +1,5 @@ @@ -94,8 +160,17 @@ index be7ad6d26f..e35eb77696 100644 -project=jdk-updates +project=riscv-port jbs=JDK - version=11.0.24 + version=11.0.25 +diff --git a/SECURITY.md b/SECURITY.md +new file mode 100644 +index 0000000000..f4c5e7e67c +--- /dev/null ++++ b/SECURITY.md +@@ -0,0 +1,3 @@ ++# JDK Vulnerabilities ++ ++Please follow the process outlined in the [OpenJDK Vulnerability Policy](https://openjdk.org/groups/vulnerability/report) to disclose vulnerabilities in the JDK. diff --git a/make/autoconf/build-aux/config.sub b/make/autoconf/build-aux/config.sub index 3c280ac7c0..6c66c221e0 100644 --- a/make/autoconf/build-aux/config.sub @@ -156,6 +231,19 @@ index 5d1d9efa39..565ca18e20 100644 # The cpu defines below are for zero, we don't support them directly. elif test "x$OPENJDK_$1_CPU" = xsparc; then +diff --git a/make/autoconf/version-numbers b/make/autoconf/version-numbers +index fe5e0d9850..c02b769bf2 100644 +--- a/make/autoconf/version-numbers ++++ b/make/autoconf/version-numbers +@@ -37,7 +37,7 @@ DEFAULT_VERSION_DATE=2024-10-15 + DEFAULT_VERSION_CLASSFILE_MAJOR=55 # "`$EXPR $DEFAULT_VERSION_FEATURE + 44`" + DEFAULT_VERSION_CLASSFILE_MINOR=0 + DEFAULT_ACCEPTABLE_BOOT_VERSIONS="10 11" +-DEFAULT_PROMOTED_VERSION_PRE= ++DEFAULT_PROMOTED_VERSION_PRE=ea + + LAUNCHER_NAME=openjdk + PRODUCT_NAME=OpenJDK diff --git a/make/hotspot/gensrc/GensrcAdlc.gmk b/make/hotspot/gensrc/GensrcAdlc.gmk index c5a3ac5724..51137b99db 100644 --- a/make/hotspot/gensrc/GensrcAdlc.gmk @@ -180,6 +268,94 @@ index c5a3ac5724..51137b99db 100644 ifeq ($(call check-jvm-feature, shenandoahgc), true) AD_SRC_FILES += $(call uniq, $(wildcard $(foreach d, $(AD_SRC_ROOTS), \ $d/cpu/$(HOTSPOT_TARGET_CPU_ARCH)/gc/shenandoah/shenandoah_$(HOTSPOT_TARGET_CPU).ad \ +diff --git a/make/hotspot/lib/JvmFlags.gmk b/make/hotspot/lib/JvmFlags.gmk +index 3246c83155..1a91eb0079 100644 +--- a/make/hotspot/lib/JvmFlags.gmk ++++ b/make/hotspot/lib/JvmFlags.gmk +@@ -67,10 +67,12 @@ JVM_CFLAGS_TARGET_DEFINES += \ + # + + ifeq ($(DEBUG_LEVEL), release) ++ # release builds disable uses of assert macro from . ++ JVM_CFLAGS_DEBUGLEVEL := -DNDEBUG + # For hotspot, release builds differ internally between "optimized" and "product" + # in that "optimize" does not define PRODUCT. + ifneq ($(HOTSPOT_DEBUG_LEVEL), optimized) +- JVM_CFLAGS_DEBUGLEVEL := -DPRODUCT ++ JVM_CFLAGS_DEBUGLEVEL += -DPRODUCT + endif + else ifeq ($(DEBUG_LEVEL), fastdebug) + JVM_CFLAGS_DEBUGLEVEL := -DASSERT +diff --git a/make/jdk/src/classes/build/tools/tzdb/TzdbZoneRulesProvider.java b/make/jdk/src/classes/build/tools/tzdb/TzdbZoneRulesProvider.java +index f02537c305..ef94e3879c 100644 +--- a/make/jdk/src/classes/build/tools/tzdb/TzdbZoneRulesProvider.java ++++ b/make/jdk/src/classes/build/tools/tzdb/TzdbZoneRulesProvider.java +@@ -1,5 +1,5 @@ + /* +- * Copyright (c) 2014, 2019, Oracle and/or its affiliates. All rights reserved. ++ * Copyright (c) 2014, 2024, Oracle and/or its affiliates. All rights reserved. + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. + * + * This code is free software; you can redistribute it and/or modify it +@@ -363,33 +363,35 @@ class TzdbZoneRulesProvider { + } + + Month parseMonth(String mon) { +- switch (mon) { +- case "Jan": return Month.JANUARY; +- case "Feb": return Month.FEBRUARY; +- case "Mar": return Month.MARCH; +- case "Apr": return Month.APRIL; +- case "May": return Month.MAY; +- case "Jun": return Month.JUNE; +- case "Jul": return Month.JULY; +- case "Aug": return Month.AUGUST; +- case "Sep": return Month.SEPTEMBER; +- case "Oct": return Month.OCTOBER; +- case "Nov": return Month.NOVEMBER; +- case "Dec": return Month.DECEMBER; +- } ++ int len = mon.length(); ++ ++ if (mon.regionMatches(true, 0, "January", 0, len)) return Month.JANUARY; ++ if (mon.regionMatches(true, 0, "February", 0, len)) return Month.FEBRUARY; ++ if (mon.regionMatches(true, 0, "March", 0, len)) return Month.MARCH; ++ if (mon.regionMatches(true, 0, "April", 0, len)) return Month.APRIL; ++ if (mon.regionMatches(true, 0, "May", 0, len)) return Month.MAY; ++ if (mon.regionMatches(true, 0, "June", 0, len)) return Month.JUNE; ++ if (mon.regionMatches(true, 0, "July", 0, len)) return Month.JULY; ++ if (mon.regionMatches(true, 0, "August", 0, len)) return Month.AUGUST; ++ if (mon.regionMatches(true, 0, "September", 0, len)) return Month.SEPTEMBER; ++ if (mon.regionMatches(true, 0, "October", 0, len)) return Month.OCTOBER; ++ if (mon.regionMatches(true, 0, "November", 0, len)) return Month.NOVEMBER; ++ if (mon.regionMatches(true, 0, "December", 0, len)) return Month.DECEMBER; ++ + throw new IllegalArgumentException("Unknown month: " + mon); + } + + DayOfWeek parseDayOfWeek(String dow) { +- switch (dow) { +- case "Mon": return DayOfWeek.MONDAY; +- case "Tue": return DayOfWeek.TUESDAY; +- case "Wed": return DayOfWeek.WEDNESDAY; +- case "Thu": return DayOfWeek.THURSDAY; +- case "Fri": return DayOfWeek.FRIDAY; +- case "Sat": return DayOfWeek.SATURDAY; +- case "Sun": return DayOfWeek.SUNDAY; +- } ++ int len = dow.length(); ++ ++ if (dow.regionMatches(true, 0, "Monday", 0, len)) return DayOfWeek.MONDAY; ++ if (dow.regionMatches(true, 0, "Tuesday", 0, len)) return DayOfWeek.TUESDAY; ++ if (dow.regionMatches(true, 0, "Wednesday", 0, len)) return DayOfWeek.WEDNESDAY; ++ if (dow.regionMatches(true, 0, "Thursday", 0, len)) return DayOfWeek.THURSDAY; ++ if (dow.regionMatches(true, 0, "Friday", 0, len)) return DayOfWeek.FRIDAY; ++ if (dow.regionMatches(true, 0, "Saturday", 0, len)) return DayOfWeek.SATURDAY; ++ if (dow.regionMatches(true, 0, "Sunday", 0, len)) return DayOfWeek.SUNDAY; ++ + throw new IllegalArgumentException("Unknown day-of-week: " + dow); + } + diff --git a/src/hotspot/cpu/riscv/abstractInterpreter_riscv.cpp b/src/hotspot/cpu/riscv/abstractInterpreter_riscv.cpp new file mode 100644 index 0000000000..31c63abe71 @@ -365,10 +541,10 @@ index 0000000000..31c63abe71 +} diff --git a/src/hotspot/cpu/riscv/assembler_riscv.cpp b/src/hotspot/cpu/riscv/assembler_riscv.cpp new file mode 100644 -index 0000000000..a83d43a8f1 +index 0000000000..67c6f1eccb --- /dev/null +++ b/src/hotspot/cpu/riscv/assembler_riscv.cpp -@@ -0,0 +1,365 @@ +@@ -0,0 +1,337 @@ +/* + * Copyright (c) 1997, 2012, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 2014, Red Hat Inc. All rights reserved. @@ -421,7 +597,7 @@ index 0000000000..a83d43a8f1 + } +} + -+void Assembler::addw(Register Rd, Register Rn, int64_t increment, Register temp) { ++void Assembler::addw(Register Rd, Register Rn, int32_t increment, Register temp) { + if (is_imm_in_range(increment, 12, 0)) { + addiw(Rd, Rn, increment); + } else { @@ -441,7 +617,7 @@ index 0000000000..a83d43a8f1 + } +} + -+void Assembler::subw(Register Rd, Register Rn, int64_t decrement, Register temp) { ++void Assembler::subw(Register Rd, Register Rn, int32_t decrement, Register temp) { + if (is_imm_in_range(-decrement, 12, 0)) { + addiw(Rd, Rn, -decrement); + } else { @@ -487,33 +663,6 @@ index 0000000000..a83d43a8f1 + } +} + -+void Assembler::li64(Register Rd, int64_t imm) { -+ // Load upper 32 bits. upper = imm[63:32], but if imm[31] == 1 or -+ // (imm[31:28] == 0x7ff && imm[19] == 1), upper = imm[63:32] + 1. -+ int64_t lower = imm & 0xffffffff; -+ lower -= ((lower << 44) >> 44); -+ int64_t tmp_imm = ((uint64_t)(imm & 0xffffffff00000000)) + (uint64_t)lower; -+ int32_t upper = (tmp_imm - (int32_t)lower) >> 32; -+ -+ // Load upper 32 bits -+ int64_t up = upper, lo = upper; -+ lo = (lo << 52) >> 52; -+ up -= lo; -+ up = (int32_t)up; -+ lui(Rd, up); -+ addi(Rd, Rd, lo); -+ -+ // Load the rest 32 bits. -+ slli(Rd, Rd, 12); -+ addi(Rd, Rd, (int32_t)lower >> 20); -+ slli(Rd, Rd, 12); -+ lower = ((int32_t)imm << 12) >> 20; -+ addi(Rd, Rd, lower); -+ slli(Rd, Rd, 8); -+ lower = imm & 0xff; -+ addi(Rd, Rd, lower); -+} -+ +void Assembler::li32(Register Rd, int32_t imm) { + // int32_t is in range 0x8000 0000 ~ 0x7fff ffff, and imm[31] is the sign bit + int64_t upper = imm, lower = imm; @@ -522,7 +671,6 @@ index 0000000000..a83d43a8f1 + upper = (int32_t)upper; + // lui Rd, imm[31:12] + imm[11] + lui(Rd, upper); -+ // use addiw to distinguish li32 to li64 + addiw(Rd, Rd, lower); +} + @@ -586,7 +734,7 @@ index 0000000000..a83d43a8f1 + void Assembler::NAME(const Address &adr, Register temp) { \ + switch (adr.getMode()) { \ + case Address::literal: { \ -+ code_section()->relocate(pc(), adr.rspec()); \ ++ relocate(adr.rspec()); \ + NAME(adr.target(), temp); \ + break; \ + } \ @@ -644,7 +792,7 @@ index 0000000000..a83d43a8f1 +} + +void Assembler::movptr_with_offset(Register Rd, address addr, int32_t &offset) { -+ uintptr_t imm64 = (uintptr_t)addr; ++ int64_t imm64 = (int64_t)addr; +#ifndef PRODUCT + { + char buffer[64]; @@ -652,10 +800,10 @@ index 0000000000..a83d43a8f1 + block_comment(buffer); + } +#endif -+ assert(is_unsigned_imm_in_range(imm64, 47, 0) || (imm64 == (uintptr_t)-1), ++ assert(is_unsigned_imm_in_range(imm64, 47, 0) || (imm64 == (int64_t)-1), + "bit 47 overflows in address constant"); + // Load upper 31 bits -+ int32_t imm = imm64 >> 17; ++ int64_t imm = imm64 >> 17; + int64_t upper = imm, lower = imm; + lower = (lower << 52) >> 52; + upper -= lower; @@ -736,10 +884,10 @@ index 0000000000..a83d43a8f1 +} diff --git a/src/hotspot/cpu/riscv/assembler_riscv.hpp b/src/hotspot/cpu/riscv/assembler_riscv.hpp new file mode 100644 -index 0000000000..9e7d271860 +index 0000000000..9f6c477afa --- /dev/null +++ b/src/hotspot/cpu/riscv/assembler_riscv.hpp -@@ -0,0 +1,3057 @@ +@@ -0,0 +1,3056 @@ +/* + * Copyright (c) 1997, 2020, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 2014, 2020, Red Hat Inc. All rights reserved. @@ -1056,7 +1204,6 @@ index 0000000000..9e7d271860 + + void _li(Register Rd, int64_t imm); // optimized load immediate + void li32(Register Rd, int32_t imm); -+ void li64(Register Rd, int64_t imm); + void movptr(Register Rd, address addr); + void movptr_with_offset(Register Rd, address addr, int32_t &offset); + void movptr(Register Rd, uintptr_t imm64); @@ -1180,10 +1327,9 @@ index 0000000000..9e7d271860 + +#define INSN_ENTRY_RELOC(result_type, header) \ + result_type header { \ -+ InstructionMark im(this); \ + guarantee(rtype == relocInfo::internal_word_type, \ + "only internal_word_type relocs make sense here"); \ -+ code_section()->relocate(inst_mark(), InternalAddress(dest).rspec()); ++ relocate(InternalAddress(dest).rspec()); + + // Load/store register (all modes) +#define INSN(NAME, op, funct3) \ @@ -1228,7 +1374,7 @@ index 0000000000..9e7d271860 + void NAME(Register Rd, const Address &adr, Register temp = t0) { \ + switch (adr.getMode()) { \ + case Address::literal: { \ -+ code_section()->relocate(pc(), adr.rspec()); \ ++ relocate(adr.rspec()); \ + NAME(Rd, adr.target()); \ + break; \ + } \ @@ -1302,7 +1448,7 @@ index 0000000000..9e7d271860 + void NAME(FloatRegister Rd, const Address &adr, Register temp = t0) { \ + switch (adr.getMode()) { \ + case Address::literal: { \ -+ code_section()->relocate(pc(), adr.rspec()); \ ++ relocate(adr.rspec()); \ + NAME(Rd, adr.target(), temp); \ + break; \ + } \ @@ -1445,7 +1591,7 @@ index 0000000000..9e7d271860 + switch (adr.getMode()) { \ + case Address::literal: { \ + assert_different_registers(Rs, temp); \ -+ code_section()->relocate(pc(), adr.rspec()); \ ++ relocate(adr.rspec()); \ + NAME(Rs, adr.target(), temp); \ + break; \ + } \ @@ -1488,7 +1634,7 @@ index 0000000000..9e7d271860 + void NAME(FloatRegister Rs, const Address &adr, Register temp = t0) { \ + switch (adr.getMode()) { \ + case Address::literal: { \ -+ code_section()->relocate(pc(), adr.rspec()); \ ++ relocate(adr.rspec()); \ + NAME(Rs, adr.target(), temp); \ + break; \ + } \ @@ -3757,11 +3903,12 @@ index 0000000000..9e7d271860 + void wrap_label(Register r, Label &L, Register t, load_insn_by_temp insn); + void wrap_label(Register r, Label &L, jal_jalr_insn insn); + -+ // calculate pseudoinstruction ++ // Computational pseudo instructions + void add(Register Rd, Register Rn, int64_t increment, Register temp = t0); -+ void addw(Register Rd, Register Rn, int64_t increment, Register temp = t0); ++ void addw(Register Rd, Register Rn, int32_t increment, Register temp = t0); ++ + void sub(Register Rd, Register Rn, int64_t decrement, Register temp = t0); -+ void subw(Register Rd, Register Rn, int64_t decrement, Register temp = t0); ++ void subw(Register Rd, Register Rn, int32_t decrement, Register temp = t0); + + // RVB pseudo instructions + // zero extend word @@ -3852,10 +3999,10 @@ index 0000000000..7ffe880398 +#endif // CPU_RISCV_ASSEMBLER_RISCV_INLINE_HPP diff --git a/src/hotspot/cpu/riscv/bytes_riscv.hpp b/src/hotspot/cpu/riscv/bytes_riscv.hpp new file mode 100644 -index 0000000000..f60e0e38ae +index 0000000000..485a5f9355 --- /dev/null +++ b/src/hotspot/cpu/riscv/bytes_riscv.hpp -@@ -0,0 +1,165 @@ +@@ -0,0 +1,167 @@ +/* + * Copyright (c) 1997, 2019, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 2012, 2016 SAP SE. All rights reserved. @@ -3931,6 +4078,7 @@ index 0000000000..f60e0e38ae + ((u8)(((u4*)p)[0])); + + case 2: ++ case 6: + return ((u8)(((u2*)p)[3]) << 48) | + ((u8)(((u2*)p)[2]) << 32) | + ((u8)(((u2*)p)[1]) << 16) | @@ -3989,6 +4137,7 @@ index 0000000000..f60e0e38ae + break; + + case 2: ++ case 6: + ((u2*)p)[3] = x >> 48; + ((u2*)p)[2] = x >> 32; + ((u2*)p)[1] = x >> 16; @@ -4023,7 +4172,7 @@ index 0000000000..f60e0e38ae +#endif // CPU_RISCV_BYTES_RISCV_HPP diff --git a/src/hotspot/cpu/riscv/c1_CodeStubs_riscv.cpp b/src/hotspot/cpu/riscv/c1_CodeStubs_riscv.cpp new file mode 100644 -index 0000000000..12980c12de +index 0000000000..9729e16c96 --- /dev/null +++ b/src/hotspot/cpu/riscv/c1_CodeStubs_riscv.cpp @@ -0,0 +1,339 @@ @@ -4358,7 +4507,7 @@ index 0000000000..12980c12de +#ifndef PRODUCT + if (PrintC1Statistics) { + __ la(t1, ExternalAddress((address)&Runtime1::_arraycopy_slowcase_cnt)); -+ __ add_memory_int32(Address(t1), 1); ++ __ incrementw(Address(t1)); + } +#endif + @@ -5414,7 +5563,7 @@ index 0000000000..ab0a9963fc +#endif // CPU_RISCV_C1_LIRASSEMBLER_ARITH_RISCV_HPP diff --git a/src/hotspot/cpu/riscv/c1_LIRAssembler_arraycopy_riscv.cpp b/src/hotspot/cpu/riscv/c1_LIRAssembler_arraycopy_riscv.cpp new file mode 100644 -index 0000000000..b7f53e395f +index 0000000000..e6b95d3b7f --- /dev/null +++ b/src/hotspot/cpu/riscv/c1_LIRAssembler_arraycopy_riscv.cpp @@ -0,0 +1,388 @@ @@ -5477,7 +5626,7 @@ index 0000000000..b7f53e395f + __ mv(c_rarg4, j_rarg4); +#ifndef PRODUCT + if (PrintC1Statistics) { -+ __ add_memory_int32(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt), 1); ++ __ incrementw(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt)); + } +#endif + __ far_call(RuntimeAddress(copyfunc_addr)); @@ -5515,14 +5664,14 @@ index 0000000000..b7f53e395f + if (!(flags & LIR_OpArrayCopy::LIR_OpArrayCopy::dst_objarray)) { + __ load_klass(tmp, dst); + __ lw(t0, Address(tmp, in_bytes(Klass::layout_helper_offset()))); -+ __ li(t1, Klass::_lh_neutral_value); ++ __ mv(t1, Klass::_lh_neutral_value); + __ bge(t0, t1, *stub->entry(), /* is_far */ true); + } + + if (!(flags & LIR_OpArrayCopy::LIR_OpArrayCopy::src_objarray)) { + __ load_klass(tmp, src); + __ lw(t0, Address(tmp, in_bytes(Klass::layout_helper_offset()))); -+ __ li(t1, Klass::_lh_neutral_value); ++ __ mv(t1, Klass::_lh_neutral_value); + __ bge(t0, t1, *stub->entry(), /* is_far */ true); + } + } @@ -5584,7 +5733,7 @@ index 0000000000..b7f53e395f + if (PrintC1Statistics) { + Label failed; + __ bnez(x10, failed); -+ __ add_memory_int32(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_cnt), 1); ++ __ incrementw(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_cnt)); + __ bind(failed); + } +#endif @@ -5593,7 +5742,7 @@ index 0000000000..b7f53e395f + +#ifndef PRODUCT + if (PrintC1Statistics) { -+ __ add_memory_int32(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_attempt_cnt), 1); ++ __ incrementw(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_attempt_cnt)); + } +#endif + assert_different_registers(dst, dst_pos, length, src_pos, src, x10, t0); @@ -5744,7 +5893,7 @@ index 0000000000..b7f53e395f + +#ifndef PRODUCT + if (PrintC1Statistics) { -+ __ add_memory_int32(ExternalAddress(Runtime1::arraycopy_count_address(basic_type)), 1); ++ __ incrementw(ExternalAddress(Runtime1::arraycopy_count_address(basic_type))); + } +#endif + arraycopy_prepare_params(src, src_pos, length, dst, dst_pos, basic_type); @@ -5866,10 +6015,10 @@ index 0000000000..06a0f248ca +#endif // CPU_RISCV_C1_LIRASSEMBLER_ARRAYCOPY_RISCV_HPP diff --git a/src/hotspot/cpu/riscv/c1_LIRAssembler_riscv.cpp b/src/hotspot/cpu/riscv/c1_LIRAssembler_riscv.cpp new file mode 100644 -index 0000000000..1e482d7cc2 +index 0000000000..fb6a60fb49 --- /dev/null +++ b/src/hotspot/cpu/riscv/c1_LIRAssembler_riscv.cpp -@@ -0,0 +1,2268 @@ +@@ -0,0 +1,2258 @@ +/* + * Copyright (c) 2000, 2020, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 2014, 2020, Red Hat Inc. All rights reserved. @@ -6937,7 +7086,7 @@ index 0000000000..1e482d7cc2 + __ ld(t1, Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)))); + __ bne(recv, t1, next_test); + Address data_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i))); -+ __ add_memory_int64(data_addr, DataLayout::counter_increment); ++ __ increment(data_addr, DataLayout::counter_increment); + __ j(*update_done); + __ bind(next_test); + } @@ -6949,7 +7098,7 @@ index 0000000000..1e482d7cc2 + __ ld(t1, recv_addr); + __ bnez(t1, next_test); + __ sd(recv, recv_addr); -+ __ li(t1, DataLayout::counter_increment); ++ __ mv(t1, DataLayout::counter_increment); + __ sd(t1, Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)))); + __ j(*update_done); + __ bind(next_test); @@ -7229,7 +7378,7 @@ index 0000000000..1e482d7cc2 + // With RVC a call instruction may get 2-byte aligned. + // The address of the call instruction needs to be 4-byte aligned to + // ensure that it does not span a cache line so that it can be patched. -+ __ align(4); ++ __ align(NativeInstruction::instruction_size); +} + +void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) { @@ -7257,7 +7406,7 @@ index 0000000000..1e482d7cc2 + +void LIR_Assembler::emit_static_call_stub() { + address call_pc = __ pc(); -+ assert((__ offset() % 4) == 0, "bad alignment"); ++ MacroAssembler::assert_alignment(call_pc); + address stub = __ start_a_stub(call_stub_size()); + if (stub == NULL) { + bailout("static call stub overflow"); @@ -7435,7 +7584,7 @@ index 0000000000..1e482d7cc2 + ciKlass* receiver = vc_data->receiver(i); + if (known_klass->equals(receiver)) { + Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i))); -+ __ add_memory_int64(data_addr, DataLayout::counter_increment); ++ __ increment(data_addr, DataLayout::counter_increment); + return; + } + } @@ -7451,7 +7600,7 @@ index 0000000000..1e482d7cc2 + __ mov_metadata(t1, known_klass->constant_encoding()); + __ sd(t1, recv_addr); + Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i))); -+ __ add_memory_int64(data_addr, DataLayout::counter_increment); ++ __ increment(data_addr, DataLayout::counter_increment); + return; + } + } @@ -7461,13 +7610,13 @@ index 0000000000..1e482d7cc2 + type_profile_helper(mdo, md, data, recv, &update_done); + // Receiver did not match any saved receiver and there is no empty row for it. + // Increment total counter to indicate polymorphic case. -+ __ add_memory_int64(counter_addr, DataLayout::counter_increment); ++ __ increment(counter_addr, DataLayout::counter_increment); + + __ bind(update_done); + } + } else { + // Static call -+ __ add_memory_int64(counter_addr, DataLayout::counter_increment); ++ __ increment(counter_addr, DataLayout::counter_increment); + } +} + @@ -7502,7 +7651,7 @@ index 0000000000..1e482d7cc2 + + if (TypeEntries::is_type_none(current_klass)) { + __ beqz(t1, none); -+ __ li(t0, (u1)TypeEntries::null_seen); ++ __ mv(t0, (u1)TypeEntries::null_seen); + __ beq(t0, t1, none); + // There is a chance that the checks above (re-reading profiling + // data from memory) fail if another thread has just set the @@ -7552,7 +7701,7 @@ index 0000000000..1e482d7cc2 + Label ok; + __ ld(t0, mdo_addr); + __ beqz(t0, ok); -+ __ li(t1, (u1)TypeEntries::null_seen); ++ __ mv(t1, (u1)TypeEntries::null_seen); + __ beq(t0, t1, ok); + // may have been set by another thread + __ membar(MacroAssembler::LoadLoad); @@ -8027,16 +8176,6 @@ index 0000000000..1e482d7cc2 + __ bind(done); +} + -+void LIR_Assembler::add_debug_info_for_branch(address adr, CodeEmitInfo* info) { -+ _masm->code_section()->relocate(adr, relocInfo::poll_type); -+ int pc_offset = code_offset(); -+ flush_debug_info(pc_offset); -+ info->record_debug_info(compilation()->debug_info_recorder(), pc_offset); -+ if (info->exception_handlers() != NULL) { -+ compilation()->add_exception_handlers_for_pco(pc_offset, info->exception_handlers()); -+ } -+} -+ +void LIR_Assembler::type_profile(Register obj, ciMethodData* md, Register klass_RInfo, Register k_RInfo, + ciProfileData* data, Label* success, Label* failure, + Label& profile_cast_success, Label& profile_cast_failure) { @@ -8133,17 +8272,17 @@ index 0000000000..1e482d7cc2 + assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp"); + int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord; + assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset"); -+ __ li(t0, c); ++ __ mv(t0, c); + __ sd(t0, Address(sp, offset_from_rsp_in_bytes)); +} + +#undef __ diff --git a/src/hotspot/cpu/riscv/c1_LIRAssembler_riscv.hpp b/src/hotspot/cpu/riscv/c1_LIRAssembler_riscv.hpp new file mode 100644 -index 0000000000..5c81f1c704 +index 0000000000..2afd61a3db --- /dev/null +++ b/src/hotspot/cpu/riscv/c1_LIRAssembler_riscv.hpp -@@ -0,0 +1,133 @@ +@@ -0,0 +1,131 @@ +/* + * Copyright (c) 2000, 2019, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 2014, Red Hat Inc. All rights reserved. @@ -8204,8 +8343,6 @@ index 0000000000..5c81f1c704 + ciMethodData *md, ciProfileData *data, + Register recv, Label* update_done); + -+ void add_debug_info_for_branch(address adr, CodeEmitInfo* info); -+ + void casw(Register addr, Register newval, Register cmpval); + void caswu(Register addr, Register newval, Register cmpval); + void casl(Register addr, Register newval, Register cmpval); @@ -9568,10 +9705,10 @@ index 0000000000..d7ca7b0fd0 +#endif // CPU_RISCV_C1_LINEARSCAN_RISCV_HPP diff --git a/src/hotspot/cpu/riscv/c1_MacroAssembler_riscv.cpp b/src/hotspot/cpu/riscv/c1_MacroAssembler_riscv.cpp new file mode 100644 -index 0000000000..99d981f97f +index 0000000000..957bfa1127 --- /dev/null +++ b/src/hotspot/cpu/riscv/c1_MacroAssembler_riscv.cpp -@@ -0,0 +1,443 @@ +@@ -0,0 +1,444 @@ +/* + * Copyright (c) 1999, 2020, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 2014, Red Hat Inc. All rights reserved. @@ -9669,7 +9806,7 @@ index 0000000000..99d981f97f + // assuming both the stack pointer and page_size have their least + // significant 2 bits cleared and page_size is a power of 2 + sub(hdr, hdr, sp); -+ li(t0, aligned_mask - os::vm_page_size()); ++ mv(t0, aligned_mask - os::vm_page_size()); + andr(hdr, hdr, t0); + // for recursive locking, the result is zero => save it in the displaced header + // location (NULL in the displaced hdr location indicates recursive locking) @@ -9679,7 +9816,7 @@ index 0000000000..99d981f97f + bind(done); + if (PrintBiasedLockingStatistics) { + la(t1, ExternalAddress((address)BiasedLocking::fast_path_entry_count_addr())); -+ add_memory_int32(Address(t1, 0), 1); ++ incrementw(Address(t1, 0)); + } + return null_check_offset; +} @@ -9910,6 +10047,7 @@ index 0000000000..99d981f97f + + +void C1_MacroAssembler::verified_entry() { ++ assert_alignment(pc()); +} + +void C1_MacroAssembler::load_parameter(int offset_in_words, Register reg) { @@ -10144,7 +10282,7 @@ index 0000000000..1950cee5dd +#endif // CPU_RISCV_C1_MACROASSEMBLER_RISCV_HPP diff --git a/src/hotspot/cpu/riscv/c1_Runtime1_riscv.cpp b/src/hotspot/cpu/riscv/c1_Runtime1_riscv.cpp new file mode 100644 -index 0000000000..329df2e1ca +index 0000000000..ffcca64e0b --- /dev/null +++ b/src/hotspot/cpu/riscv/c1_Runtime1_riscv.cpp @@ -0,0 +1,1210 @@ @@ -11155,7 +11293,7 @@ index 0000000000..329df2e1ca + __ check_klass_subtype_slow_path(x14, x10, x12, x15, NULL, &miss); + + // fallthrough on success: -+ __ li(t0, 1); ++ __ mv(t0, 1); + __ sd(t0, Address(sp, (result_off) * VMRegImpl::stack_slot_size)); // result + __ pop_reg(RegSet::of(x10, x12, x14, x15), sp); + __ ret(); @@ -11345,7 +11483,7 @@ index 0000000000..329df2e1ca + default: + { + StubFrame f(sasm, "unimplemented entry", dont_gc_arguments); -+ __ li(x10, (int) id); ++ __ mv(x10, (int)id); + __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, unimplemented_entry), x10); + __ should_not_reach_here(); + } @@ -13077,13 +13215,13 @@ index 0000000000..abd5bda7e4 +#endif // CPU_RISCV_FRAME_RISCV_INLINE_HPP diff --git a/src/hotspot/cpu/riscv/gc/g1/g1BarrierSetAssembler_riscv.cpp b/src/hotspot/cpu/riscv/gc/g1/g1BarrierSetAssembler_riscv.cpp new file mode 100644 -index 0000000000..e191cbcee2 +index 0000000000..c5ccf040c7 --- /dev/null +++ b/src/hotspot/cpu/riscv/gc/g1/g1BarrierSetAssembler_riscv.cpp -@@ -0,0 +1,481 @@ +@@ -0,0 +1,475 @@ +/* + * Copyright (c) 2018, 2020, Oracle and/or its affiliates. All rights reserved. -+ * Copyright (c) 2020, 2021, Huawei Technologies Co., Ltd. All rights reserved. ++ * Copyright (c) 2020, 2022, Huawei Technologies Co., Ltd. All rights reserved. + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. + * + * This code is free software; you can redistribute it and/or modify it @@ -13128,7 +13266,6 @@ index 0000000000..e191cbcee2 + +void G1BarrierSetAssembler::gen_write_ref_array_pre_barrier(MacroAssembler* masm, DecoratorSet decorators, + Register addr, Register count, RegSet saved_regs) { -+ assert_cond(masm != NULL); + bool dest_uninitialized = (decorators & IS_DEST_UNINITIALIZED) != 0; + if (!dest_uninitialized) { + Label done; @@ -13171,7 +13308,6 @@ index 0000000000..e191cbcee2 + +void G1BarrierSetAssembler::gen_write_ref_array_post_barrier(MacroAssembler* masm, DecoratorSet decorators, + Register start, Register count, Register tmp, RegSet saved_regs) { -+ assert_cond(masm != NULL); + __ push_reg(saved_regs, sp); + assert_different_registers(start, count, tmp); + assert_different_registers(c_rarg0, count); @@ -13192,7 +13328,6 @@ index 0000000000..e191cbcee2 + // directly to skip generating the check by + // InterpreterMacroAssembler::call_VM_leaf_base that checks _last_sp. + -+ assert_cond(masm != NULL); + assert(thread == xthread, "must be"); + + Label done; @@ -13260,7 +13395,6 @@ index 0000000000..e191cbcee2 + Register thread, + Register tmp, + Register tmp2) { -+ assert_cond(masm != NULL); + assert(thread == xthread, "must be"); + assert_different_registers(store_addr, new_val, thread, tmp, tmp2, + t0); @@ -13337,7 +13471,6 @@ index 0000000000..e191cbcee2 + +void G1BarrierSetAssembler::load_at(MacroAssembler* masm, DecoratorSet decorators, BasicType type, + Register dst, Address src, Register tmp1, Register tmp_thread) { -+ assert_cond(masm != NULL); + bool on_oop = is_reference_type(type); + bool on_weak = (decorators & ON_WEAK_OOP_REF) != 0; + bool on_phantom = (decorators & ON_PHANTOM_OOP_REF) != 0; @@ -13361,7 +13494,6 @@ index 0000000000..e191cbcee2 + +void G1BarrierSetAssembler::oop_store_at(MacroAssembler* masm, DecoratorSet decorators, BasicType type, + Address dst, Register val, Register tmp1, Register tmp2) { -+ assert_cond(masm != NULL); + // flatten object address if needed + if (dst.offset() == 0) { + if (dst.base() != x13) { @@ -13685,10 +13817,10 @@ index 0000000000..8735fd014f +#endif // CPU_RISCV_GC_G1_G1GLOBALS_RISCV_HPP diff --git a/src/hotspot/cpu/riscv/gc/shared/barrierSetAssembler_riscv.cpp b/src/hotspot/cpu/riscv/gc/shared/barrierSetAssembler_riscv.cpp new file mode 100644 -index 0000000000..2b556b95d7 +index 0000000000..2b439280fa --- /dev/null +++ b/src/hotspot/cpu/riscv/gc/shared/barrierSetAssembler_riscv.cpp -@@ -0,0 +1,231 @@ +@@ -0,0 +1,225 @@ +/* + * Copyright (c) 2018, 2020, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 2020, 2022, Huawei Technologies Co., Ltd. All rights reserved. @@ -13730,8 +13862,6 @@ index 0000000000..2b556b95d7 + +void BarrierSetAssembler::load_at(MacroAssembler* masm, DecoratorSet decorators, BasicType type, + Register dst, Address src, Register tmp1, Register tmp_thread) { -+ assert_cond(masm != NULL); -+ + // RA is live. It must be saved around calls. + + bool in_heap = (decorators & IN_HEAP) != 0; @@ -13772,7 +13902,6 @@ index 0000000000..2b556b95d7 + +void BarrierSetAssembler::store_at(MacroAssembler* masm, DecoratorSet decorators, BasicType type, + Address dst, Register val, Register tmp1, Register tmp2) { -+ assert_cond(masm != NULL); + bool in_heap = (decorators & IN_HEAP) != 0; + bool in_native = (decorators & IN_NATIVE) != 0; + switch (type) { @@ -13814,7 +13943,6 @@ index 0000000000..2b556b95d7 + +void BarrierSetAssembler::try_resolve_jobject_in_native(MacroAssembler* masm, Register jni_env, + Register obj, Register tmp, Label& slowpath) { -+ assert_cond(masm != NULL); + // If mask changes we need to ensure that the inverse is still encodable as an immediate + STATIC_ASSERT(JNIHandles::weak_tag_mask == 1); + __ andi(obj, obj, ~JNIHandles::weak_tag_mask); @@ -13829,7 +13957,6 @@ index 0000000000..2b556b95d7 + Register tmp2, + Label& slow_case, + bool is_far) { -+ assert_cond(masm != NULL); + assert_different_registers(obj, tmp2); + assert_different_registers(obj, var_size_in_bytes); + Register end = tmp2; @@ -13909,7 +14036,6 @@ index 0000000000..2b556b95d7 + Register var_size_in_bytes, + int con_size_in_bytes, + Register tmp1) { -+ assert_cond(masm != NULL); + assert(tmp1->is_valid(), "need temp reg"); + + __ ld(tmp1, Address(xthread, in_bytes(JavaThread::allocated_bytes_offset()))); @@ -14004,10 +14130,10 @@ index 0000000000..984d94f4c3 +#endif // CPU_RISCV_GC_SHARED_BARRIERSETASSEMBLER_RISCV_HPP diff --git a/src/hotspot/cpu/riscv/gc/shared/cardTableBarrierSetAssembler_riscv.cpp b/src/hotspot/cpu/riscv/gc/shared/cardTableBarrierSetAssembler_riscv.cpp new file mode 100644 -index 0000000000..81d47d61d4 +index 0000000000..671cad68b2 --- /dev/null +++ b/src/hotspot/cpu/riscv/gc/shared/cardTableBarrierSetAssembler_riscv.cpp -@@ -0,0 +1,125 @@ +@@ -0,0 +1,122 @@ +/* + * Copyright (c) 2018, 2019, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 2020, 2022, Huawei Technologies Co., Ltd. All rights reserved. @@ -14046,7 +14172,6 @@ index 0000000000..81d47d61d4 + + +void CardTableBarrierSetAssembler::store_check(MacroAssembler* masm, Register obj, Register tmp) { -+ assert_cond(masm != NULL); + assert_different_registers(obj, tmp); + BarrierSet* bs = BarrierSet::barrier_set(); + assert(bs->kind() == BarrierSet::CardTableBarrierSet, "Wrong barrier set kind"); @@ -14079,7 +14204,6 @@ index 0000000000..81d47d61d4 + +void CardTableBarrierSetAssembler::gen_write_ref_array_post_barrier(MacroAssembler* masm, DecoratorSet decorators, + Register start, Register count, Register tmp, RegSet saved_regs) { -+ assert_cond(masm != NULL); + assert_different_registers(start, tmp); + assert_different_registers(count, tmp); + @@ -14127,7 +14251,6 @@ index 0000000000..81d47d61d4 + if (!precise || dst.offset() == 0) { + store_check(masm, dst.base(), x13); + } else { -+ assert_cond(masm != NULL); + __ la(x13, dst); + store_check(masm, x13, t0); + } @@ -14183,13 +14306,13 @@ index 0000000000..686fe8fa47 +#endif // #ifndef CPU_RISCV_GC_SHARED_CARDTABLEBARRIERSETASSEMBLER_RISCV_HPP diff --git a/src/hotspot/cpu/riscv/gc/shared/modRefBarrierSetAssembler_riscv.cpp b/src/hotspot/cpu/riscv/gc/shared/modRefBarrierSetAssembler_riscv.cpp new file mode 100644 -index 0000000000..7aa2015f9e +index 0000000000..4b7982eb21 --- /dev/null +++ b/src/hotspot/cpu/riscv/gc/shared/modRefBarrierSetAssembler_riscv.cpp -@@ -0,0 +1,55 @@ +@@ -0,0 +1,54 @@ +/* + * Copyright (c) 2018, 2019, Oracle and/or its affiliates. All rights reserved. -+ * Copyright (c) 2020, 2021, Huawei Technologies Co., Ltd. All rights reserved. ++ * Copyright (c) 2020, 2022, Huawei Technologies Co., Ltd. All rights reserved. + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. + * + * This code is free software; you can redistribute it and/or modify it @@ -14220,7 +14343,6 @@ index 0000000000..7aa2015f9e + +void ModRefBarrierSetAssembler::arraycopy_prologue(MacroAssembler* masm, DecoratorSet decorators, bool is_oop, + Register src, Register dst, Register count, RegSet saved_regs) { -+ + if (is_oop) { + gen_write_ref_array_pre_barrier(masm, decorators, dst, count, saved_regs); + } @@ -14428,7 +14550,7 @@ index 0000000000..d19f5b859c +} diff --git a/src/hotspot/cpu/riscv/gc/shenandoah/shenandoahBarrierSetAssembler_riscv.cpp b/src/hotspot/cpu/riscv/gc/shenandoah/shenandoahBarrierSetAssembler_riscv.cpp new file mode 100644 -index 0000000000..b8534c52e7 +index 0000000000..d73ea36b24 --- /dev/null +++ b/src/hotspot/cpu/riscv/gc/shenandoah/shenandoahBarrierSetAssembler_riscv.cpp @@ -0,0 +1,715 @@ @@ -14920,7 +15042,7 @@ index 0000000000..b8534c52e7 + if (is_cae) { + __ mv(result, expected); + } else { -+ __ addi(result, zr, 1); ++ __ mv(result, 1); + } + __ j(done); + @@ -15831,7 +15953,7 @@ index 0000000000..5bf40ca820 +#endif // CPU_RISCV_ICACHE_RISCV_HPP diff --git a/src/hotspot/cpu/riscv/interp_masm_riscv.cpp b/src/hotspot/cpu/riscv/interp_masm_riscv.cpp new file mode 100644 -index 0000000000..b50be7e726 +index 0000000000..fa5ddc34b2 --- /dev/null +++ b/src/hotspot/cpu/riscv/interp_masm_riscv.cpp @@ -0,0 +1,1931 @@ @@ -16349,7 +16471,7 @@ index 0000000000..b50be7e726 + bnez(t1, safepoint); + } + if (table == Interpreter::dispatch_table(state)) { -+ li(t1, Interpreter::distance_from_dispatch_table(state)); ++ mv(t1, Interpreter::distance_from_dispatch_table(state)); + add(t1, Rs, t1); + shadd(t1, t1, xdispatch, t1, 3); + } else { @@ -16642,7 +16764,7 @@ index 0000000000..b50be7e726 + // least significant 3 bits clear. + // NOTE: the oopMark is in swap_reg x10 as the result of cmpxchg + sub(swap_reg, swap_reg, sp); -+ li(t0, (int64_t)(7 - os::vm_page_size())); ++ mv(t0, (int64_t)(7 - os::vm_page_size())); + andr(swap_reg, swap_reg, t0); + + // Save the test result, for recursive case, the result is zero @@ -16743,7 +16865,7 @@ index 0000000000..b50be7e726 +void InterpreterMacroAssembler::set_method_data_pointer_for_bcp() { + assert(ProfileInterpreter, "must be profiling interpreter"); + Label set_mdp; -+ push_reg(0xc00, sp); // save x10, x11 ++ push_reg(RegSet::of(x10, x11), sp); // save x10, x11 + + // Test MDO to avoid the call if it is NULL. + ld(x10, Address(xmethod, in_bytes(Method::method_data_offset()))); @@ -16756,7 +16878,7 @@ index 0000000000..b50be7e726 + add(x10, x11, x10); + sd(x10, Address(fp, frame::interpreter_frame_mdp_offset * wordSize)); + bind(set_mdp); -+ pop_reg(0xc00, sp); ++ pop_reg(RegSet::of(x10, x11), sp); +} + +void InterpreterMacroAssembler::verify_method_data_pointer() { @@ -17494,7 +17616,7 @@ index 0000000000..b50be7e726 + + ld(t0, mdo_addr); + beqz(t0, none); -+ li(tmp, (u1)TypeEntries::null_seen); ++ mv(tmp, (u1)TypeEntries::null_seen); + beq(t0, tmp, none); + // There is a chance that the checks above (re-reading profiling + // data from memory) fail if another thread has just set the @@ -17529,10 +17651,10 @@ index 0000000000..b50be7e726 + + lbu(t0, Address(mdp, in_bytes(DataLayout::tag_offset()) - off_to_start)); + if (is_virtual) { -+ li(tmp, (u1)DataLayout::virtual_call_type_data_tag); ++ mv(tmp, (u1)DataLayout::virtual_call_type_data_tag); + bne(t0, tmp, profile_continue); + } else { -+ li(tmp, (u1)DataLayout::call_type_data_tag); ++ mv(tmp, (u1)DataLayout::call_type_data_tag); + bne(t0, tmp, profile_continue); + } + @@ -17562,7 +17684,7 @@ index 0000000000..b50be7e726 + mv(index, zr); // index < TypeProfileArgsLimit + bind(loop); + bgtz(index, profileReturnType); -+ li(t0, (int)MethodData::profile_return()); ++ mv(t0, (int)MethodData::profile_return()); + beqz(t0, profileArgument); // (index > 0 || MethodData::profile_return()) == false + bind(profileReturnType); + // If return value type is profiled we may have no argument to profile @@ -17570,7 +17692,7 @@ index 0000000000..b50be7e726 + mv(t1, - TypeStackSlotEntries::per_arg_count()); + mul(t1, index, t1); + add(tmp, tmp, t1); -+ li(t1, TypeStackSlotEntries::per_arg_count()); ++ mv(t1, TypeStackSlotEntries::per_arg_count()); + add(t0, mdp, off_to_args); + blt(tmp, t1, done); + @@ -17581,8 +17703,8 @@ index 0000000000..b50be7e726 + // stack offset o (zero based) from the start of the argument + // list, for n arguments translates into offset n - o - 1 from + // the end of the argument list -+ li(t0, stack_slot_offset0); -+ li(t1, slot_step); ++ mv(t0, stack_slot_offset0); ++ mv(t1, slot_step); + mul(t1, index, t1); + add(t0, t0, t1); + add(t0, mdp, t0); @@ -17592,8 +17714,8 @@ index 0000000000..b50be7e726 + Address arg_addr = argument_address(tmp); + ld(tmp, arg_addr); + -+ li(t0, argument_type_offset0); -+ li(t1, type_step); ++ mv(t0, argument_type_offset0); ++ mv(t1, type_step); + mul(t1, index, t1); + add(t0, t0, t1); + add(mdo_addr, mdp, t0); @@ -17605,7 +17727,7 @@ index 0000000000..b50be7e726 + + // increment index by 1 + addi(index, index, 1); -+ li(t1, TypeProfileArgsLimit); ++ mv(t1, TypeProfileArgsLimit); + blt(index, t1, loop); + bind(loopEnd); + @@ -17660,13 +17782,13 @@ index 0000000000..b50be7e726 + // length + Label do_profile; + lbu(t0, Address(xbcp, 0)); -+ li(tmp, (u1)Bytecodes::_invokedynamic); ++ mv(tmp, (u1)Bytecodes::_invokedynamic); + beq(t0, tmp, do_profile); -+ li(tmp, (u1)Bytecodes::_invokehandle); ++ mv(tmp, (u1)Bytecodes::_invokehandle); + beq(t0, tmp, do_profile); + get_method(tmp); + lhu(t0, Address(tmp, Method::intrinsic_id_offset_in_bytes())); -+ li(t1, vmIntrinsics::_compiledLambdaForm); ++ mv(t1, vmIntrinsics::_compiledLambdaForm); + bne(t0, t1, profile_continue); + bind(do_profile); + } @@ -18057,10 +18179,10 @@ index 0000000000..4126e8ee70 +#endif // CPU_RISCV_INTERP_MASM_RISCV_HPP diff --git a/src/hotspot/cpu/riscv/interpreterRT_riscv.cpp b/src/hotspot/cpu/riscv/interpreterRT_riscv.cpp new file mode 100644 -index 0000000000..776b078723 +index 0000000000..b5e6b8c512 --- /dev/null +++ b/src/hotspot/cpu/riscv/interpreterRT_riscv.cpp -@@ -0,0 +1,295 @@ +@@ -0,0 +1,305 @@ +/* + * Copyright (c) 2003, 2019, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 2014, 2020, Red Hat Inc. All rights reserved. @@ -18137,6 +18259,16 @@ index 0000000000..776b078723 + _stack_offset = 0; +} + ++// The C ABI specifies: ++// "integer scalars narrower than XLEN bits are widened according to the sign ++// of their type up to 32 bits, then sign-extended to XLEN bits." ++// Applies for both passed in register and stack. ++// ++// Java uses 32-bit stack slots; jint, jshort, jchar, jbyte uses one slot. ++// Native uses 64-bit stack slots for all integer scalar types. ++// ++// lw loads the Java stack slot, sign-extends and ++// sd store this widened integer into a 64 bit native stack slot. +void InterpreterRuntime::SignatureHandlerGenerator::pass_int() { + const Address src(from(), Interpreter::local_offset_in_bytes(offset())); + @@ -18145,7 +18277,7 @@ index 0000000000..776b078723 + __ lw(reg, src); + } else { + __ lw(x10, src); -+ __ sw(x10, Address(to(), next_stack_offset())); ++ __ sd(x10, Address(to(), next_stack_offset())); + } +} + @@ -18839,10 +18971,10 @@ index 0000000000..df3c0267ee +#endif // CPU_RISCV_JNITYPES_RISCV_HPP diff --git a/src/hotspot/cpu/riscv/macroAssembler_riscv.cpp b/src/hotspot/cpu/riscv/macroAssembler_riscv.cpp new file mode 100644 -index 0000000000..e18bd3d8e2 +index 0000000000..14e07036ac --- /dev/null +++ b/src/hotspot/cpu/riscv/macroAssembler_riscv.cpp -@@ -0,0 +1,5410 @@ +@@ -0,0 +1,5390 @@ +/* + * Copyright (c) 1997, 2020, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 2014, 2020, Red Hat Inc. All rights reserved. @@ -18908,28 +19040,24 @@ index 0000000000..e18bd3d8e2 + +static void pass_arg0(MacroAssembler* masm, Register arg) { + if (c_rarg0 != arg) { -+ assert_cond(masm != NULL); + masm->mv(c_rarg0, arg); + } +} + +static void pass_arg1(MacroAssembler* masm, Register arg) { + if (c_rarg1 != arg) { -+ assert_cond(masm != NULL); + masm->mv(c_rarg1, arg); + } +} + +static void pass_arg2(MacroAssembler* masm, Register arg) { + if (c_rarg2 != arg) { -+ assert_cond(masm != NULL); + masm->mv(c_rarg2, arg); + } +} + +static void pass_arg3(MacroAssembler* masm, Register arg) { + if (c_rarg3 != arg) { -+ assert_cond(masm != NULL); + masm->mv(c_rarg3, arg); + } +} @@ -19104,7 +19232,6 @@ index 0000000000..e18bd3d8e2 + if (L.is_bound()) { + set_last_Java_frame(last_java_sp, last_java_fp, target(L), tmp); + } else { -+ InstructionMark im(this); + L.add_patch_at(code(), locator()); + set_last_Java_frame(last_java_sp, last_java_fp, pc() /* Patched later */, tmp); + } @@ -19237,7 +19364,7 @@ index 0000000000..e18bd3d8e2 + // The length of the instruction sequence emitted should be independent + // of the values of the local char buffer address so that the size of mach + // nodes for scratch emit and normal emit matches. -+ mv(t0, (address)b); ++ movptr(t0, (address)b); + + // call indirectly to solve generation ordering problem + int32_t offset = 0; @@ -19276,7 +19403,7 @@ index 0000000000..e18bd3d8e2 + // The length of the instruction sequence emitted should be independent + // of the values of the local char buffer address so that the size of mach + // nodes for scratch emit and normal emit matches. -+ mv(t0, (address)b); ++ movptr(t0, (address)b); + + // call indirectly to solve generation ordering problem + int32_t offset = 0; @@ -19597,15 +19724,13 @@ index 0000000000..e18bd3d8e2 +} + +void MacroAssembler::la(Register Rd, const Address &adr) { -+ InstructionMark im(this); -+ code_section()->relocate(inst_mark(), adr.rspec()); -+ relocInfo::relocType rtype = adr.rspec().reloc()->type(); -+ + switch (adr.getMode()) { + case Address::literal: { ++ relocInfo::relocType rtype = adr.rspec().reloc()->type(); + if (rtype == relocInfo::none) { -+ li(Rd, (intptr_t)(adr.target())); ++ mv(Rd, (intptr_t)(adr.target())); + } else { ++ relocate(adr.rspec()); + movptr(Rd, adr.target()); + } + break; @@ -19812,7 +19937,7 @@ index 0000000000..e18bd3d8e2 + return count; +} + -+// Push lots of registers in the bit set supplied. Don't push sp. ++// Push integer registers in the bitset supplied. Don't push sp. +// Return the number of words pushed +int MacroAssembler::push_reg(unsigned int bitset, Register stack) { + DEBUG_ONLY(int words_pushed = 0;) @@ -19824,11 +19949,11 @@ index 0000000000..e18bd3d8e2 + int offset = is_even(count) ? 0 : wordSize; + + if (count) { -+ addi(stack, stack, - count * wordSize - offset); ++ addi(stack, stack, -count * wordSize - offset); + } + for (int i = count - 1; i >= 0; i--) { + sd(as_Register(regs[i]), Address(stack, (count - 1 - i) * wordSize + offset)); -+ DEBUG_ONLY(words_pushed ++;) ++ DEBUG_ONLY(words_pushed++;) + } + + assert(words_pushed == count, "oops, pushed != count"); @@ -19847,7 +19972,7 @@ index 0000000000..e18bd3d8e2 + + for (int i = count - 1; i >= 0; i--) { + ld(as_Register(regs[i]), Address(stack, (count - 1 - i) * wordSize + offset)); -+ DEBUG_ONLY(words_popped ++;) ++ DEBUG_ONLY(words_popped++;) + } + + if (count) { @@ -19858,11 +19983,11 @@ index 0000000000..e18bd3d8e2 + return count; +} + -+// Push float registers in the bitset, except sp. -+// Return the number of heapwords pushed. ++// Push floating-point registers in the bitset supplied. ++// Return the number of words pushed +int MacroAssembler::push_fp(unsigned int bitset, Register stack) { + CompressibleRegion cr(this); -+ int words_pushed = 0; ++ DEBUG_ONLY(int words_pushed = 0;) + unsigned char regs[32]; + int count = bitset_to_regs(bitset, regs); + int push_slots = count + (count & 1); @@ -19873,23 +19998,24 @@ index 0000000000..e18bd3d8e2 + + for (int i = count - 1; i >= 0; i--) { + fsd(as_FloatRegister(regs[i]), Address(stack, (push_slots - 1 - i) * wordSize)); -+ words_pushed++; ++ DEBUG_ONLY(words_pushed++;) + } + + assert(words_pushed == count, "oops, pushed(%d) != count(%d)", words_pushed, count); ++ + return count; +} + +int MacroAssembler::pop_fp(unsigned int bitset, Register stack) { + CompressibleRegion cr(this); -+ int words_popped = 0; ++ DEBUG_ONLY(int words_popped = 0;) + unsigned char regs[32]; + int count = bitset_to_regs(bitset, regs); + int pop_slots = count + (count & 1); + + for (int i = count - 1; i >= 0; i--) { + fld(as_FloatRegister(regs[i]), Address(stack, (pop_slots - 1 - i) * wordSize)); -+ words_popped++; ++ DEBUG_ONLY(words_popped++;) + } + + if (count) { @@ -19897,6 +20023,7 @@ index 0000000000..e18bd3d8e2 + } + + assert(words_popped == count, "oops, popped(%d) != count(%d)", words_popped, count); ++ + return count; +} + @@ -19910,7 +20037,7 @@ index 0000000000..e18bd3d8e2 + int offset = 0; + for (int i = 0; i < 32; i++) { + if (i <= f7->encoding() || i >= f28->encoding() || (i >= f10->encoding() && i <= f17->encoding())) { -+ fsd(as_FloatRegister(i), Address(sp, wordSize * (offset ++))); ++ fsd(as_FloatRegister(i), Address(sp, wordSize * (offset++))); + } + } +} @@ -19920,7 +20047,7 @@ index 0000000000..e18bd3d8e2 + int offset = 0; + for (int i = 0; i < 32; i++) { + if (i <= f7->encoding() || i >= f28->encoding() || (i >= f10->encoding() && i <= f17->encoding())) { -+ fld(as_FloatRegister(i), Address(sp, wordSize * (offset ++))); ++ fld(as_FloatRegister(i), Address(sp, wordSize * (offset++))); + } + } + addi(sp, sp, wordSize * 20); @@ -19931,19 +20058,19 @@ index 0000000000..e18bd3d8e2 +// Push all the integer registers, except zr(x0) & sp(x2) & gp(x3) & tp(x4). +void MacroAssembler::pusha() { + CompressibleRegion cr(this); -+ push_reg(0xffffffe2, sp); ++ push_reg(RegSet::of(x1) + RegSet::range(x5, x31), sp); +} + +// Pop all the integer registers, except zr(x0) & sp(x2) & gp(x3) & tp(x4). +void MacroAssembler::popa() { + CompressibleRegion cr(this); -+ pop_reg(0xffffffe2, sp); ++ pop_reg(RegSet::of(x1) + RegSet::range(x5, x31), sp); +} + +void MacroAssembler::push_CPU_state() { + CompressibleRegion cr(this); + // integer registers, except zr(x0) & ra(x1) & sp(x2) & gp(x3) & tp(x4) -+ push_reg(0xffffffe0, sp); ++ push_reg(RegSet::range(x5, x31), sp); + + // float registers + addi(sp, sp, - 32 * wordSize); @@ -19962,7 +20089,7 @@ index 0000000000..e18bd3d8e2 + addi(sp, sp, 32 * wordSize); + + // integer registers, except zr(x0) & ra(x1) & sp(x2) & gp(x3) & tp(x4) -+ pop_reg(0xffffffe0, sp); ++ pop_reg(RegSet::range(x5, x31), sp); +} + +static int patch_offset_in_jal(address branch, int64_t offset) { @@ -20001,27 +20128,6 @@ index 0000000000..e18bd3d8e2 + return MOVPTR_INSTRUCTIONS_NUM * NativeInstruction::instruction_size; +} + -+static int patch_imm_in_li64(address branch, address target) { -+ const int LI64_INSTRUCTIONS_NUM = 8; // lui + addi + slli + addi + slli + addi + slli + addi -+ int64_t lower = (intptr_t)target & 0xffffffff; -+ lower = lower - ((lower << 44) >> 44); -+ int64_t tmp_imm = ((uint64_t)((intptr_t)target & 0xffffffff00000000)) + (uint64_t)lower; -+ int32_t upper = (tmp_imm - (int32_t)lower) >> 32; -+ int64_t tmp_upper = upper, tmp_lower = upper; -+ tmp_lower = (tmp_lower << 52) >> 52; -+ tmp_upper -= tmp_lower; -+ tmp_upper >>= 12; -+ // Load upper 32 bits. Upper = target[63:32], but if target[31] = 1 or (target[31:28] == 0x7ff && target[19] == 1), -+ // upper = target[63:32] + 1. -+ Assembler::patch(branch + 0, 31, 12, tmp_upper & 0xfffff); // Lui. -+ Assembler::patch(branch + 4, 31, 20, tmp_lower & 0xfff); // Addi. -+ // Load the rest 32 bits. -+ Assembler::patch(branch + 12, 31, 20, ((int32_t)lower >> 20) & 0xfff); // Addi. -+ Assembler::patch(branch + 20, 31, 20, (((intptr_t)target << 44) >> 52) & 0xfff); // Addi. -+ Assembler::patch(branch + 28, 31, 20, (intptr_t)target & 0xff); // Addi. -+ return LI64_INSTRUCTIONS_NUM * NativeInstruction::instruction_size; -+} -+ +static int patch_imm_in_li32(address branch, int32_t target) { + const int LI32_INSTRUCTIONS_NUM = 2; // lui + addiw + int64_t upper = (intptr_t)target; @@ -20076,16 +20182,6 @@ index 0000000000..e18bd3d8e2 + return (address) target_address; +} + -+static address get_target_of_li64(address insn_addr) { -+ assert_cond(insn_addr != NULL); -+ intptr_t target_address = (((int64_t)Assembler::sextract(((unsigned*)insn_addr)[0], 31, 12)) & 0xfffff) << 44; // Lui. -+ target_address += ((int64_t)Assembler::sextract(((unsigned*)insn_addr)[1], 31, 20)) << 32; // Addi. -+ target_address += ((int64_t)Assembler::sextract(((unsigned*)insn_addr)[3], 31, 20)) << 20; // Addi. -+ target_address += ((int64_t)Assembler::sextract(((unsigned*)insn_addr)[5], 31, 20)) << 8; // Addi. -+ target_address += ((int64_t)Assembler::sextract(((unsigned*)insn_addr)[7], 31, 20)); // Addi. -+ return (address)target_address; -+} -+ +static address get_target_of_li32(address insn_addr) { + assert_cond(insn_addr != NULL); + intptr_t target_address = (((int64_t)Assembler::sextract(((unsigned*)insn_addr)[0], 31, 12)) & 0xfffff) << 12; // Lui. @@ -20106,8 +20202,6 @@ index 0000000000..e18bd3d8e2 + return patch_offset_in_pc_relative(branch, offset); + } else if (NativeInstruction::is_movptr_at(branch)) { // movptr + return patch_addr_in_movptr(branch, target); -+ } else if (NativeInstruction::is_li64_at(branch)) { // li64 -+ return patch_imm_in_li64(branch, target); + } else if (NativeInstruction::is_li32_at(branch)) { // li32 + int64_t imm = (intptr_t)target; + return patch_imm_in_li32(branch, (int32_t)imm); @@ -20133,8 +20227,6 @@ index 0000000000..e18bd3d8e2 + offset = get_offset_of_pc_relative(insn_addr); + } else if (NativeInstruction::is_movptr_at(insn_addr)) { // movptr + return get_target_of_movptr(insn_addr); -+ } else if (NativeInstruction::is_li64_at(insn_addr)) { // li64 -+ return get_target_of_li64(insn_addr); + } else if (NativeInstruction::is_li32_at(insn_addr)) { // li32 + return get_target_of_li32(insn_addr); + } else { @@ -20173,16 +20265,10 @@ index 0000000000..e18bd3d8e2 + +void MacroAssembler::mv(Register Rd, Address dest) { + assert(dest.getMode() == Address::literal, "Address mode should be Address::literal"); -+ code_section()->relocate(pc(), dest.rspec()); ++ relocate(dest.rspec()); + movptr(Rd, dest.target()); +} + -+void MacroAssembler::mv(Register Rd, address addr) { -+ // Here in case of use with relocation, use fix length instruction -+ // movptr instead of li -+ movptr(Rd, addr); -+} -+ +void MacroAssembler::mv(Register Rd, RegisterOrConstant src) { + if (src.is_register()) { + mv(Rd, src.as_register()); @@ -20422,7 +20508,7 @@ index 0000000000..e18bd3d8e2 + and_imm12(Rd, Rn, imm); + } else { + assert_different_registers(Rn, tmp); -+ li(tmp, imm); ++ mv(tmp, imm); + andr(Rd, Rn, tmp); + } +} @@ -20436,7 +20522,7 @@ index 0000000000..e18bd3d8e2 + ori(tmp1, tmp1, src.as_constant()); + } else { + assert_different_registers(tmp1, tmp2); -+ li(tmp2, src.as_constant()); ++ mv(tmp2, src.as_constant()); + orr(tmp1, tmp1, tmp2); + } + } @@ -20525,7 +20611,6 @@ index 0000000000..e18bd3d8e2 +} + +SkipIfEqual::SkipIfEqual(MacroAssembler* masm, const bool* flag_addr, bool value) { -+ assert_cond(masm != NULL); + int32_t offset = 0; + _masm = masm; + _masm->la_patchable(t0, ExternalAddress((address)flag_addr), offset); @@ -20534,7 +20619,6 @@ index 0000000000..e18bd3d8e2 +} + +SkipIfEqual::~SkipIfEqual() { -+ assert_cond(_masm != NULL); + _masm->bind(_label); + _masm = NULL; +} @@ -20665,7 +20749,7 @@ index 0000000000..e18bd3d8e2 + } + + assert_different_registers(src, xbase); -+ li(xbase, (uintptr_t)Universe::narrow_klass_base()); ++ mv(xbase, (uintptr_t)Universe::narrow_klass_base()); + + if (Universe::narrow_klass_shift() != 0) { + assert(LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong"); @@ -20707,7 +20791,7 @@ index 0000000000..e18bd3d8e2 + } + + assert_different_registers(src, xbase); -+ li(xbase, (intptr_t)Universe::narrow_klass_base()); ++ mv(xbase, (intptr_t)Universe::narrow_klass_base()); + sub(dst, src, xbase); + if (Universe::narrow_klass_shift() != 0) { + assert(LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong"); @@ -20860,7 +20944,7 @@ index 0000000000..e18bd3d8e2 + if (itable_index.is_register()) { + slli(t0, itable_index.as_register(), 3); + } else { -+ li(t0, itable_index.as_constant() << 3); ++ mv(t0, itable_index.as_constant() << 3); + } + add(recv_klass, recv_klass, t0); + if (itentry_off) { @@ -21051,10 +21135,10 @@ index 0000000000..e18bd3d8e2 + andi(aligned_addr, addr, ~3); + + if (size == int8) { -+ addi(mask, zr, 0xff); ++ mv(mask, 0xff); + } else { + // size == int16 case -+ addi(mask, zr, -1); ++ mv(mask, -1); + zero_extend(mask, mask, 16); + } + sll(mask, mask, shift); @@ -21094,7 +21178,7 @@ index 0000000000..e18bd3d8e2 + bnez(tmp, retry); + + if (result_as_bool) { -+ addi(result, zr, 1); ++ mv(result, 1); + j(done); + + bind(fail); @@ -21129,7 +21213,7 @@ index 0000000000..e18bd3d8e2 + assert_different_registers(addr, old, mask, not_mask, new_val, expected, shift, tmp); + cmpxchg_narrow_value_helper(addr, expected, new_val, size, tmp1, tmp2, tmp3); + -+ Label succ, fail, done; ++ Label fail, done; + + lr_w(old, aligned_addr, acquire); + andr(tmp, old, mask); @@ -21138,13 +21222,14 @@ index 0000000000..e18bd3d8e2 + andr(tmp, old, not_mask); + orr(tmp, tmp, new_val); + sc_w(tmp, tmp, aligned_addr, release); -+ beqz(tmp, succ); ++ bnez(tmp, fail); + -+ bind(fail); -+ addi(result, zr, 1); ++ // Success ++ mv(result, 1); + j(done); + -+ bind(succ); ++ // Fail ++ bind(fail); + mv(result, zr); + + bind(done); @@ -21166,7 +21251,7 @@ index 0000000000..e18bd3d8e2 + + // equal, succeed + if (result_as_bool) { -+ li(result, 1); ++ mv(result, 1); + } else { + mv(result, expected); + } @@ -21188,20 +21273,20 @@ index 0000000000..e18bd3d8e2 + enum operand_size size, + Assembler::Aqrl acquire, Assembler::Aqrl release, + Register result) { -+ Label fail, done, sc_done; ++ Label fail, done; + load_reserved(addr, size, acquire); + bne(t0, expected, fail); + store_conditional(addr, new_val, size, release); -+ beqz(t0, sc_done); ++ bnez(t0, fail); + -+ // fail -+ bind(fail); -+ li(result, 1); ++ // Success ++ mv(result, 1); + j(done); + -+ // sc_done -+ bind(sc_done); -+ mv(result, 0); ++ // Fail ++ bind(fail); ++ mv(result, zr); ++ + bind(done); +} + @@ -21443,7 +21528,7 @@ index 0000000000..e18bd3d8e2 + add(x15, x15, Array::base_offset_in_bytes()); + + // Set t0 to an obvious invalid value, falling through by default -+ li(t0, -1); ++ mv(t0, -1); + // Scan X12 words at [X15] for an occurrence of X10. + repne_scan(x15, x10, x12, t0); + @@ -21500,11 +21585,10 @@ index 0000000000..e18bd3d8e2 + RegSet::range(x28, x31) + ra - thread; + push_reg(saved_regs, sp); + -+ int32_t offset = 0; -+ movptr_with_offset(ra, CAST_FROM_FN_PTR(address, Thread::current), offset); -+ jalr(ra, ra, offset); -+ if (thread != x10) { -+ mv(thread, x10); ++ mv(ra, CAST_FROM_FN_PTR(address, Thread::current)); ++ jalr(ra); ++ if (thread != c_rarg0) { ++ mv(thread, c_rarg0); + } + + // restore pushed registers @@ -21514,7 +21598,7 @@ index 0000000000..e18bd3d8e2 +void MacroAssembler::load_byte_map_base(Register reg) { + jbyte *byte_map_base = + ((CardTableBarrierSet*)(BarrierSet::barrier_set()))->card_table()->byte_map_base(); -+ li(reg, (uint64_t)byte_map_base); ++ mv(reg, (uint64_t)byte_map_base); +} + +void MacroAssembler::la_patchable(Register reg1, const Address &dest, int32_t &offset) { @@ -21528,8 +21612,7 @@ index 0000000000..e18bd3d8e2 + assert(is_valid_riscv64_address(dest.target()), "bad address"); + assert(dest.getMode() == Address::literal, "la_patchable must be applied to a literal address"); + -+ InstructionMark im(this); -+ code_section()->relocate(inst_mark(), dest.rspec()); ++ relocate(dest.rspec()); + // RISC-V doesn't compute a page-aligned address, in order to partially + // compensate for the use of *signed* offsets in its base+disp12 + // addressing mode (RISC-V's PC-relative reach remains asymmetric @@ -21823,7 +21906,7 @@ index 0000000000..e18bd3d8e2 +// Read the polling page. The address of the polling page must +// already be in r. +void MacroAssembler::read_polling_page(Register dest, int32_t offset, relocInfo::relocType rtype) { -+ code_section()->relocate(pc(), rtype); ++ relocate(rtype); + lwu(zr, Address(dest, offset)); +} + @@ -21838,9 +21921,7 @@ index 0000000000..e18bd3d8e2 + } +#endif + int oop_index = oop_recorder()->find_index(obj); -+ InstructionMark im(this); -+ RelocationHolder rspec = oop_Relocation::spec(oop_index); -+ code_section()->relocate(inst_mark(), rspec); ++ relocate(oop_Relocation::spec(oop_index)); + li32(dst, 0xDEADBEEF); + zero_extend(dst, dst, 32); +} @@ -21851,10 +21932,8 @@ index 0000000000..e18bd3d8e2 + int index = oop_recorder()->find_index(k); + assert(!Universe::heap()->is_in_reserved(k), "should not be an oop"); + -+ InstructionMark im(this); -+ RelocationHolder rspec = metadata_Relocation::spec(index); -+ code_section()->relocate(inst_mark(), rspec); + narrowKlass nk = Klass::encode_klass(k); ++ relocate(metadata_Relocation::spec(index)); + li32(dst, nk); + zero_extend(dst, dst, 32); +} @@ -21889,6 +21968,11 @@ index 0000000000..e18bd3d8e2 + } + + if (cbuf != NULL) { cbuf->set_insts_mark(); } ++#ifdef ASSERT ++ if (entry.rspec().type() != relocInfo::runtime_call_type) { ++ assert_alignment(pc()); ++ } ++#endif + relocate(entry.rspec()); + if (!far_branches()) { + jal(entry.target()); @@ -21971,19 +22055,47 @@ index 0000000000..e18bd3d8e2 + } +} + -+void MacroAssembler::add_memory_int64(const Address dst, int64_t imm) { ++void MacroAssembler::increment(const Address dst, int64_t value) { ++ assert(((dst.getMode() == Address::base_plus_offset && ++ is_offset_in_range(dst.offset(), 12)) || is_imm_in_range(value, 12, 0)), ++ "invalid value and address mode combination"); + Address adr = add_memory_helper(dst); -+ assert_different_registers(adr.base(), t0); ++ assert(!adr.uses(t0), "invalid dst for address increment"); + ld(t0, adr); -+ addi(t0, t0, imm); ++ add(t0, t0, value, t1); + sd(t0, adr); +} + -+void MacroAssembler::add_memory_int32(const Address dst, int32_t imm) { ++void MacroAssembler::incrementw(const Address dst, int32_t value) { ++ assert(((dst.getMode() == Address::base_plus_offset && ++ is_offset_in_range(dst.offset(), 12)) || is_imm_in_range(value, 12, 0)), ++ "invalid value and address mode combination"); + Address adr = add_memory_helper(dst); -+ assert_different_registers(adr.base(), t0); ++ assert(!adr.uses(t0), "invalid dst for address increment"); + lwu(t0, adr); -+ addiw(t0, t0, imm); ++ addw(t0, t0, value, t1); ++ sw(t0, adr); ++} ++ ++void MacroAssembler::decrement(const Address dst, int64_t value) { ++ assert(((dst.getMode() == Address::base_plus_offset && ++ is_offset_in_range(dst.offset(), 12)) || is_imm_in_range(value, 12, 0)), ++ "invalid value and address mode combination"); ++ Address adr = add_memory_helper(dst); ++ assert(!adr.uses(t0), "invalid dst for address decrement"); ++ ld(t0, adr); ++ sub(t0, t0, value, t1); ++ sd(t0, adr); ++} ++ ++void MacroAssembler::decrementw(const Address dst, int32_t value) { ++ assert(((dst.getMode() == Address::base_plus_offset && ++ is_offset_in_range(dst.offset(), 12)) || is_imm_in_range(value, 12, 0)), ++ "invalid value and address mode combination"); ++ Address adr = add_memory_helper(dst); ++ assert(!adr.uses(t0), "invalid dst for address decrement"); ++ lwu(t0, adr); ++ subw(t0, t0, value, t1); + sw(t0, adr); +} + @@ -22063,7 +22175,7 @@ index 0000000000..e18bd3d8e2 + add(in, in, t0); + + const int unroll = 8; -+ li(tmp, unroll); ++ mv(tmp, unroll); + blt(len, tmp, L_tail_loop); + bind(L_unroll); + for (int i = 0; i < unroll; i++) { @@ -22553,7 +22665,7 @@ index 0000000000..e18bd3d8e2 + assert_different_registers(Rd, Rs, tmp1, tmp2); + Label Loop; + int step = isLL ? 8 : 16; -+ li(Rd, -step); ++ mv(Rd, -step); + mv(tmp2, Rs); + + bind(Loop); @@ -22570,7 +22682,7 @@ index 0000000000..e18bd3d8e2 +void MacroAssembler::inflate_lo32(Register Rd, Register Rs, Register tmp1, Register tmp2) +{ + assert_different_registers(Rd, Rs, tmp1, tmp2); -+ li(tmp1, 0xFF); ++ mv(tmp1, 0xFF); + mv(Rd, zr); + for (int i = 0; i <= 3; i++) + { @@ -22592,7 +22704,7 @@ index 0000000000..e18bd3d8e2 +void MacroAssembler::inflate_hi32(Register Rd, Register Rs, Register tmp1, Register tmp2) +{ + assert_different_registers(Rd, Rs, tmp1, tmp2); -+ li(tmp1, 0xFF00000000); ++ mv(tmp1, 0xFF00000000); + mv(Rd, zr); + for (int i = 0; i <= 3; i++) + { @@ -22690,7 +22802,7 @@ index 0000000000..e18bd3d8e2 + Register cnt_reg = t0; + Register loop_base = t1; + cnt = cnt - remainder; -+ li(cnt_reg, cnt); ++ mv(cnt_reg, cnt); + add(loop_base, base, remainder * wordSize); + bind(loop); + sub(cnt_reg, cnt_reg, unroll); @@ -23746,7 +23858,7 @@ index 0000000000..e18bd3d8e2 + bind(L); + + // A very short string -+ li(t0, minCharsInWord); ++ mv(t0, minCharsInWord); + ble(cnt2, t0, SHORT_STRING); + + // Compare longwords @@ -23757,7 +23869,7 @@ index 0000000000..e18bd3d8e2 + ld(tmp1, Address(str1)); + beq(str1, str2, DONE); + ld(tmp2, Address(str2)); -+ li(t0, STUB_THRESHOLD); ++ mv(t0, STUB_THRESHOLD); + bge(cnt2, t0, STUB); + sub(cnt2, cnt2, minCharsInWord); + beqz(cnt2, TAIL_CHECK); @@ -23771,7 +23883,7 @@ index 0000000000..e18bd3d8e2 + } else if (isLU) { // LU case + lwu(tmp1, Address(str1)); + ld(tmp2, Address(str2)); -+ li(t0, STUB_THRESHOLD); ++ mv(t0, STUB_THRESHOLD); + bge(cnt2, t0, STUB); + addi(cnt2, cnt2, -4); + add(str1, str1, cnt2); @@ -23785,7 +23897,7 @@ index 0000000000..e18bd3d8e2 + } else { // UL case + ld(tmp1, Address(str1)); + lwu(tmp2, Address(str2)); -+ li(t0, STUB_THRESHOLD); ++ mv(t0, STUB_THRESHOLD); + bge(cnt2, t0, STUB); + addi(cnt2, cnt2, -4); + slli(t0, cnt2, 1); @@ -23961,7 +24073,7 @@ index 0000000000..e18bd3d8e2 + + assert(elem_size == 1 || elem_size == 2, "must be char or byte"); + assert_different_registers(a1, a2, result, cnt1, t0, t1, tmp3, tmp4, tmp5, tmp6); -+ li(elem_per_word, wordSize / elem_size); ++ mv(elem_per_word, wordSize / elem_size); + + BLOCK_COMMENT("arrays_equals {"); + @@ -24255,10 +24367,10 @@ index 0000000000..e18bd3d8e2 + diff --git a/src/hotspot/cpu/riscv/macroAssembler_riscv.hpp b/src/hotspot/cpu/riscv/macroAssembler_riscv.hpp new file mode 100644 -index 0000000000..c660bce437 +index 0000000000..eca18b51f3 --- /dev/null +++ b/src/hotspot/cpu/riscv/macroAssembler_riscv.hpp -@@ -0,0 +1,966 @@ +@@ -0,0 +1,984 @@ +/* + * Copyright (c) 1997, 2020, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 2014, 2020, Red Hat Inc. All rights reserved. @@ -24290,6 +24402,7 @@ index 0000000000..c660bce437 + +#include "asm/assembler.hpp" +#include "metaprogramming/enableIf.hpp" ++#include "nativeInst_riscv.hpp" + +// MacroAssembler extends Assembler by frequently used macros. +// @@ -24334,6 +24447,9 @@ index 0000000000..c660bce437 + + // Alignment + void align(int modulus, int extra_offset = 0); ++ static inline void assert_alignment(address pc, int alignment = NativeInstruction::instruction_size) { ++ assert(is_aligned(pc, alignment), "bad alignment"); ++ } + + // Stack frame creation/removal + // Note that SP must be updated to the right place before saving/restoring RA and FP @@ -24755,12 +24871,17 @@ index 0000000000..c660bce437 + void double_blt(FloatRegister Rs1, FloatRegister Rs2, Label &l, bool is_far = false, bool is_unordered = false); + void double_bgt(FloatRegister Rs1, FloatRegister Rs2, Label &l, bool is_far = false, bool is_unordered = false); + -+ void push_reg(RegSet regs, Register stack) { if (regs.bits()) { push_reg(regs.bits(), stack); } } -+ void pop_reg(RegSet regs, Register stack) { if (regs.bits()) { pop_reg(regs.bits(), stack); } } ++private: ++ int push_reg(unsigned int bitset, Register stack); ++ int pop_reg(unsigned int bitset, Register stack); ++ int push_fp(unsigned int bitset, Register stack); ++ int pop_fp(unsigned int bitset, Register stack); ++ ++public: + void push_reg(Register Rs); + void pop_reg(Register Rd); -+ int push_reg(unsigned int bitset, Register stack); -+ int pop_reg(unsigned int bitset, Register stack); ++ void push_reg(RegSet regs, Register stack) { if (regs.bits()) push_reg(regs.bits(), stack); } ++ void pop_reg(RegSet regs, Register stack) { if (regs.bits()) pop_reg(regs.bits(), stack); } + + // Push and pop everything that might be clobbered by a native + // runtime call except t0 and t1. (They are always @@ -24791,6 +24912,8 @@ index 0000000000..c660bce437 + } + + // mv ++ void mv(Register Rd, address addr) { li(Rd, (int64_t)addr); } ++ + inline void mv(Register Rd, int imm64) { li(Rd, (int64_t)imm64); } + inline void mv(Register Rd, long imm64) { li(Rd, (int64_t)imm64); } + inline void mv(Register Rd, long long imm64) { li(Rd, (int64_t)imm64); } @@ -24801,7 +24924,6 @@ index 0000000000..c660bce437 + inline void mvw(Register Rd, int32_t imm32) { mv(Rd, imm32); } + + void mv(Register Rd, Address dest); -+ void mv(Register Rd, address dest); + void mv(Register Rd, RegisterOrConstant src); + + // logic @@ -24915,8 +25037,19 @@ index 0000000000..c660bce437 + address trampoline_call(Address entry, CodeBuffer* cbuf = NULL); + address ic_call(address entry, jint method_index = 0); + -+ void add_memory_int64(const Address dst, int64_t imm); -+ void add_memory_int32(const Address dst, int32_t imm); ++ // Support for memory inc/dec ++ // n.b. increment/decrement calls with an Address destination will ++ // need to use a scratch register to load the value to be ++ // incremented. increment/decrement calls which add or subtract a ++ // constant value other than sign-extended 12-bit immediate will need ++ // to use a 2nd scratch register to hold the constant. so, an address ++ // increment/decrement may trash both t0 and t1. ++ ++ void increment(const Address dst, int64_t value = 1); ++ void incrementw(const Address dst, int32_t value = 1); ++ ++ void decrement(const Address dst, int64_t value = 1); ++ void decrementw(const Address dst, int32_t value = 1); + + void cmpptr(Register src1, Address src2, Label& equal); + @@ -25054,9 +25187,6 @@ index 0000000000..c660bce437 + // if [src1 < src2], dst = -1; + void cmp_l2i(Register dst, Register src1, Register src2, Register tmp = t0); + -+ int push_fp(unsigned int bitset, Register stack); -+ int pop_fp(unsigned int bitset, Register stack); -+ + // vext + void vmnot_m(VectorRegister vd, VectorRegister vs); + void vncvt_x_x_w(VectorRegister vd, VectorRegister vs, VectorMask vm = unmasked); @@ -25264,10 +25394,10 @@ index 0000000000..ef968ccd96 +#endif // CPU_RISCV_MACROASSEMBLER_RISCV_INLINE_HPP diff --git a/src/hotspot/cpu/riscv/methodHandles_riscv.cpp b/src/hotspot/cpu/riscv/methodHandles_riscv.cpp new file mode 100644 -index 0000000000..fd907f77af +index 0000000000..3c4e8847ce --- /dev/null +++ b/src/hotspot/cpu/riscv/methodHandles_riscv.cpp -@@ -0,0 +1,450 @@ +@@ -0,0 +1,444 @@ +/* + * Copyright (c) 1997, 2020, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 2014, Red Hat Inc. All rights reserved. @@ -25317,7 +25447,6 @@ index 0000000000..fd907f77af +#define BIND(label) bind(label); BLOCK_COMMENT(#label ":") + +void MethodHandles::load_klass_from_Class(MacroAssembler* _masm, Register klass_reg) { -+ assert_cond(_masm != NULL); + if (VerifyMethodHandles) { + verify_klass(_masm, klass_reg, SystemDictionary::WK_KLASS_ENUM_NAME(java_lang_Class), + "MH argument is a Class"); @@ -25339,7 +25468,6 @@ index 0000000000..fd907f77af +void MethodHandles::verify_klass(MacroAssembler* _masm, + Register obj, SystemDictionary::WKID klass_id, + const char* error_message) { -+ assert_cond(_masm != NULL); + InstanceKlass** klass_addr = SystemDictionary::well_known_klass_addr(klass_id); + Klass* klass = SystemDictionary::well_known_klass(klass_id); + Register temp = t1; @@ -25368,7 +25496,6 @@ index 0000000000..fd907f77af + +void MethodHandles::jump_from_method_handle(MacroAssembler* _masm, Register method, Register temp, + bool for_compiler_entry) { -+ assert_cond(_masm != NULL); + assert(method == xmethod, "interpreter calling convention"); + Label L_no_such_method; + __ beqz(xmethod, L_no_such_method); @@ -25399,7 +25526,6 @@ index 0000000000..fd907f77af + Register recv, Register method_temp, + Register temp2, + bool for_compiler_entry) { -+ assert_cond(_masm != NULL); + BLOCK_COMMENT("jump_to_lambda_form {"); + // This is the initial entry point of a lazy method handle. + // After type checking, it picks up the invoker from the LambdaForm. @@ -25438,7 +25564,6 @@ index 0000000000..fd907f77af +// Code generation +address MethodHandles::generate_method_handle_interpreter_entry(MacroAssembler* _masm, + vmIntrinsics::ID iid) { -+ assert_cond(_masm != NULL); + const bool not_for_compiler_entry = false; // this is the interpreter entry + assert(is_signature_polymorphic(iid), "expected invoke iid"); + if (iid == vmIntrinsics::_invokeGeneric || @@ -25526,7 +25651,6 @@ index 0000000000..fd907f77af + Register receiver_reg, + Register member_reg, + bool for_compiler_entry) { -+ assert_cond(_masm != NULL); + assert(is_signature_polymorphic(iid), "expected invoke iid"); + // temps used in this code are not used in *either* compiled or interpreted calling sequences + Register temp1 = x7; @@ -25783,10 +25907,10 @@ index 0000000000..65493eba76 + bool for_compiler_entry); diff --git a/src/hotspot/cpu/riscv/nativeInst_riscv.cpp b/src/hotspot/cpu/riscv/nativeInst_riscv.cpp new file mode 100644 -index 0000000000..27011ad128 +index 0000000000..ecce8eb021 --- /dev/null +++ b/src/hotspot/cpu/riscv/nativeInst_riscv.cpp -@@ -0,0 +1,417 @@ +@@ -0,0 +1,414 @@ +/* + * Copyright (c) 1997, 2020, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 2014, 2020, Red Hat Inc. All rights reserved. @@ -25891,18 +26015,6 @@ index 0000000000..27011ad128 + check_li32_data_dependency(instr); +} + -+bool NativeInstruction::is_li64_at(address instr) { -+ return is_lui_at(instr) && // lui -+ is_addi_at(instr + instruction_size) && // addi -+ is_slli_shift_at(instr + instruction_size * 2, 12) && // Slli Rd, Rs, 12 -+ is_addi_at(instr + instruction_size * 3) && // addi -+ is_slli_shift_at(instr + instruction_size * 4, 12) && // Slli Rd, Rs, 12 -+ is_addi_at(instr + instruction_size * 5) && // addi -+ is_slli_shift_at(instr + instruction_size * 6, 8) && // Slli Rd, Rs, 8 -+ is_addi_at(instr + instruction_size * 7) && // addi -+ check_li64_data_dependency(instr); -+} -+ +void NativeCall::verify() { + assert(NativeCall::is_call_at((address)this), "unexpected code at call site"); +} @@ -26053,6 +26165,13 @@ index 0000000000..27011ad128 + + +void NativeJump::check_verified_entry_alignment(address entry, address verified_entry) { ++ // Patching to not_entrant can happen while activations of the method are ++ // in use. The patching in that instance must happen only when certain ++ // alignment restrictions are true. These guarantees check those ++ // conditions. ++ ++ // Must be 4 bytes aligned ++ MacroAssembler::assert_alignment(verified_entry); +} + + @@ -26132,6 +26251,8 @@ index 0000000000..27011ad128 + nativeInstruction_at(verified_entry)->is_sigill_zombie_not_entrant(), + "riscv cannot replace non-jump with jump"); + ++ check_verified_entry_alignment(entry, verified_entry); ++ + // Patch this nmethod atomically. + if (Assembler::reachable_from_branch_at(verified_entry, dest)) { + ptrdiff_t offset = dest - verified_entry; @@ -26206,10 +26327,10 @@ index 0000000000..27011ad128 +} diff --git a/src/hotspot/cpu/riscv/nativeInst_riscv.hpp b/src/hotspot/cpu/riscv/nativeInst_riscv.hpp new file mode 100644 -index 0000000000..2e5c84ee3b +index 0000000000..183ab85fc9 --- /dev/null +++ b/src/hotspot/cpu/riscv/nativeInst_riscv.hpp -@@ -0,0 +1,555 @@ +@@ -0,0 +1,520 @@ +/* + * Copyright (c) 1997, 2020, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 2014, 2018, Red Hat Inc. All rights reserved. @@ -26326,40 +26447,6 @@ index 0000000000..2e5c84ee3b + extract_rs1(last_instr) == extract_rd(slli2); + } + -+ // the instruction sequence of li64 is as below: -+ // lui -+ // addi -+ // slli -+ // addi -+ // slli -+ // addi -+ // slli -+ // addi -+ static bool check_li64_data_dependency(address instr) { -+ address lui = instr; -+ address addi1 = lui + instruction_size; -+ address slli1 = addi1 + instruction_size; -+ address addi2 = slli1 + instruction_size; -+ address slli2 = addi2 + instruction_size; -+ address addi3 = slli2 + instruction_size; -+ address slli3 = addi3 + instruction_size; -+ address addi4 = slli3 + instruction_size; -+ return extract_rs1(addi1) == extract_rd(lui) && -+ extract_rs1(addi1) == extract_rd(addi1) && -+ extract_rs1(slli1) == extract_rd(addi1) && -+ extract_rs1(slli1) == extract_rd(slli1) && -+ extract_rs1(addi2) == extract_rd(slli1) && -+ extract_rs1(addi2) == extract_rd(addi2) && -+ extract_rs1(slli2) == extract_rd(addi2) && -+ extract_rs1(slli2) == extract_rd(slli2) && -+ extract_rs1(addi3) == extract_rd(slli2) && -+ extract_rs1(addi3) == extract_rd(addi3) && -+ extract_rs1(slli3) == extract_rd(addi3) && -+ extract_rs1(slli3) == extract_rd(slli3) && -+ extract_rs1(addi4) == extract_rd(slli3) && -+ extract_rs1(addi4) == extract_rd(addi4); -+ } -+ + // the instruction sequence of li32 is as below: + // lui + // addiw @@ -26394,7 +26481,6 @@ index 0000000000..2e5c84ee3b + + static bool is_movptr_at(address instr); + static bool is_li32_at(address instr); -+ static bool is_li64_at(address instr); + static bool is_pc_relative_at(address branch); + static bool is_load_pc_relative_at(address branch); + @@ -27638,10 +27724,10 @@ index 0000000000..840ed935d8 +#endif // CPU_RISCV_RELOCINFO_RISCV_HPP diff --git a/src/hotspot/cpu/riscv/riscv.ad b/src/hotspot/cpu/riscv/riscv.ad new file mode 100644 -index 0000000000..02d6167629 +index 0000000000..d54ae97200 --- /dev/null +++ b/src/hotspot/cpu/riscv/riscv.ad -@@ -0,0 +1,10280 @@ +@@ -0,0 +1,10273 @@ +// +// Copyright (c) 2003, 2020, Oracle and/or its affiliates. All rights reserved. +// Copyright (c) 2014, 2020, Red Hat Inc. All rights reserved. @@ -27728,8 +27814,8 @@ index 0000000000..02d6167629 +reg_def R0_H ( NS, NS, Op_RegI, 0, x0->as_VMReg()->next() ); +reg_def R1 ( NS, SOC, Op_RegI, 1, x1->as_VMReg() ); // ra +reg_def R1_H ( NS, SOC, Op_RegI, 1, x1->as_VMReg()->next() ); -+reg_def R2 ( NS, SOE, Op_RegI, 2, x2->as_VMReg() ); // sp -+reg_def R2_H ( NS, SOE, Op_RegI, 2, x2->as_VMReg()->next() ); ++reg_def R2 ( NS, NS, Op_RegI, 2, x2->as_VMReg() ); // sp ++reg_def R2_H ( NS, NS, Op_RegI, 2, x2->as_VMReg()->next() ); +reg_def R3 ( NS, NS, Op_RegI, 3, x3->as_VMReg() ); // gp +reg_def R3_H ( NS, NS, Op_RegI, 3, x3->as_VMReg()->next() ); +reg_def R4 ( NS, NS, Op_RegI, 4, x4->as_VMReg() ); // tp @@ -28707,6 +28793,7 @@ index 0000000000..02d6167629 + + // insert a nop at the start of the prolog so we can patch in a + // branch if we need to invalidate the method later ++ MacroAssembler::assert_alignment(__ pc()); + __ nop(); + + assert_cond(C != NULL); @@ -29054,6 +29141,10 @@ index 0000000000..02d6167629 + __ cmp_klass(j_rarg0, t1, t0, skip); + __ far_jump(RuntimeAddress(SharedRuntime::get_ic_miss_stub())); + __ bind(skip); ++ ++ // These NOPs are critical so that verified entry point is properly ++ // 4 bytes aligned for patching by NativeJump::patch_verified_entry() ++ __ align(NativeInstruction::instruction_size); +} + +uint MachUEPNode::size(PhaseRegAlloc* ra_) const @@ -29431,7 +29522,7 @@ index 0000000000..02d6167629 + Assembler::CompressibleRegion cr(&_masm); + int64_t con = (int64_t)$src$$constant; + Register dst_reg = as_Register($dst$$reg); -+ __ li(dst_reg, con); ++ __ mv(dst_reg, con); + %} + + enc_class riscv_enc_mov_p(iRegP dst, immP src) %{ @@ -29448,7 +29539,7 @@ index 0000000000..02d6167629 + __ mov_metadata(dst_reg, (Metadata*)con); + } else { + assert(rtype == relocInfo::none, "unexpected reloc type"); -+ __ li(dst_reg, $src$$constant); ++ __ mv(dst_reg, $src$$constant); + } + } + %} @@ -29457,7 +29548,7 @@ index 0000000000..02d6167629 + MacroAssembler _masm(&cbuf); + Assembler::CompressibleRegion cr(&_masm); + Register dst_reg = as_Register($dst$$reg); -+ __ li(dst_reg, 1); ++ __ mv(dst_reg, 1); + %} + + enc_class riscv_enc_mov_poll_page(iRegP dst, immPollPage src) %{ @@ -29595,7 +29686,7 @@ index 0000000000..02d6167629 + + __ bind(miss); + if (!$primary) { -+ __ li(cr_reg, 1); ++ __ mv(cr_reg, 1); + } + + __ bind(done); @@ -29734,7 +29825,7 @@ index 0000000000..02d6167629 + // Check if the owner is self by comparing the value in the + // markWord of object (disp_hdr) with the stack pointer. + __ sub(disp_hdr, disp_hdr, sp); -+ __ li(tmp, (intptr_t) (~(os::vm_page_size()-1) | (uintptr_t)markOopDesc::lock_mask_in_place)); ++ __ mv(tmp, (intptr_t) (~(os::vm_page_size()-1) | (uintptr_t)markOopDesc::lock_mask_in_place)); + // If (mark & lock_mask) == 0 and mark - sp < page_size, we are stack-locking and goto cont, + // hence we can store 0 as the displaced header in the box, which indicates that it is a + // recursive lock. @@ -33108,14 +33199,13 @@ index 0000000000..02d6167629 + + format %{ + "cmpxchg_weak $mem, $oldval, $newval\t# (byte, weak) if $mem == $oldval then $mem <-- $newval\n\t" -+ "xori $res, $res, 1\t# $res == 1 when success, #@weakCompareAndSwapB" ++ "# $res == 1 when success, #@weakCompareAndSwapB" + %} + + ins_encode %{ + __ weak_cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8, + /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register, + $tmp1$$Register, $tmp2$$Register, $tmp3$$Register); -+ __ xori($res$$Register, $res$$Register, 1); + %} + + ins_pipe(pipe_slow); @@ -33132,14 +33222,13 @@ index 0000000000..02d6167629 + + format %{ + "cmpxchg_weak $mem, $oldval, $newval\t# (short, weak) if $mem == $oldval then $mem <-- $newval\n\t" -+ "xori $res, $res, 1\t# $res == 1 when success, #@weakCompareAndSwapS" ++ "# $res == 1 when success, #@weakCompareAndSwapS" + %} + + ins_encode %{ + __ weak_cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16, + /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register, + $tmp1$$Register, $tmp2$$Register, $tmp3$$Register); -+ __ xori($res$$Register, $res$$Register, 1); + %} + + ins_pipe(pipe_slow); @@ -33153,13 +33242,12 @@ index 0000000000..02d6167629 + + format %{ + "cmpxchg_weak $mem, $oldval, $newval\t# (int, weak) if $mem == $oldval then $mem <-- $newval\n\t" -+ "xori $res, $res, 1\t# $res == 1 when success, #@weakCompareAndSwapI" ++ "# $res == 1 when success, #@weakCompareAndSwapI" + %} + + ins_encode %{ + __ cmpxchg_weak(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int32, + /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register); -+ __ xori($res$$Register, $res$$Register, 1); + %} + + ins_pipe(pipe_slow); @@ -33173,13 +33261,12 @@ index 0000000000..02d6167629 + + format %{ + "cmpxchg_weak $mem, $oldval, $newval\t# (long, weak) if $mem == $oldval then $mem <-- $newval\n\t" -+ "xori $res, $res, 1\t# $res == 1 when success, #@weakCompareAndSwapL" ++ "# $res == 1 when success, #@weakCompareAndSwapL" + %} + + ins_encode %{ + __ cmpxchg_weak(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64, + /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register); -+ __ xori($res$$Register, $res$$Register, 1); + %} + + ins_pipe(pipe_slow); @@ -33193,13 +33280,12 @@ index 0000000000..02d6167629 + + format %{ + "cmpxchg_weak $mem, $oldval, $newval\t# (narrow oop, weak) if $mem == $oldval then $mem <-- $newval\n\t" -+ "xori $res, $res, 1\t# $res == 1 when success, #@weakCompareAndSwapN" ++ "# $res == 1 when success, #@weakCompareAndSwapN" + %} + + ins_encode %{ + __ cmpxchg_weak(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::uint32, + /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register); -+ __ xori($res$$Register, $res$$Register, 1); + %} + + ins_pipe(pipe_slow); @@ -33213,13 +33299,12 @@ index 0000000000..02d6167629 + + format %{ + "cmpxchg_weak $mem, $oldval, $newval\t# (ptr, weak) if $mem == $oldval then $mem <-- $newval\n\t" -+ "xori $res, $res, 1\t# $res == 1 when success, #@weakCompareAndSwapP" ++ "# $res == 1 when success, #@weakCompareAndSwapP" + %} + + ins_encode %{ + __ cmpxchg_weak(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64, + /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register); -+ __ xori($res$$Register, $res$$Register, 1); + %} + + ins_pipe(pipe_slow); @@ -33238,14 +33323,13 @@ index 0000000000..02d6167629 + + format %{ + "cmpxchg_weak_acq $mem, $oldval, $newval\t# (byte, weak) if $mem == $oldval then $mem <-- $newval\n\t" -+ "xori $res, $res, 1\t# $res == 1 when success, #@weakCompareAndSwapBAcq" ++ "# $res == 1 when success, #@weakCompareAndSwapBAcq" + %} + + ins_encode %{ + __ weak_cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8, + /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register, + $tmp1$$Register, $tmp2$$Register, $tmp3$$Register); -+ __ xori($res$$Register, $res$$Register, 1); + %} + + ins_pipe(pipe_slow); @@ -33264,14 +33348,13 @@ index 0000000000..02d6167629 + + format %{ + "cmpxchg_weak_acq $mem, $oldval, $newval\t# (short, weak) if $mem == $oldval then $mem <-- $newval\n\t" -+ "xori $res, $res, 1\t# $res == 1 when success, #@weakCompareAndSwapSAcq" ++ "# $res == 1 when success, #@weakCompareAndSwapSAcq" + %} + + ins_encode %{ + __ weak_cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16, + /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register, + $tmp1$$Register, $tmp2$$Register, $tmp3$$Register); -+ __ xori($res$$Register, $res$$Register, 1); + %} + + ins_pipe(pipe_slow); @@ -33287,13 +33370,12 @@ index 0000000000..02d6167629 + + format %{ + "cmpxchg_weak_acq $mem, $oldval, $newval\t# (int, weak) if $mem == $oldval then $mem <-- $newval\n\t" -+ "xori $res, $res, 1\t# $res == 1 when success, #@weakCompareAndSwapIAcq" ++ "# $res == 1 when success, #@weakCompareAndSwapIAcq" + %} + + ins_encode %{ + __ cmpxchg_weak(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int32, + /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register); -+ __ xori($res$$Register, $res$$Register, 1); + %} + + ins_pipe(pipe_slow); @@ -33309,13 +33391,12 @@ index 0000000000..02d6167629 + + format %{ + "cmpxchg_weak_acq $mem, $oldval, $newval\t# (long, weak) if $mem == $oldval then $mem <-- $newval\n\t" -+ "xori $res, $res, 1\t# $res == 1 when success, #@weakCompareAndSwapLAcq" ++ "# $res == 1 when success, #@weakCompareAndSwapLAcq" + %} + + ins_encode %{ + __ cmpxchg_weak(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64, + /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register); -+ __ xori($res$$Register, $res$$Register, 1); + %} + + ins_pipe(pipe_slow); @@ -33331,13 +33412,12 @@ index 0000000000..02d6167629 + + format %{ + "cmpxchg_weak_acq $mem, $oldval, $newval\t# (narrow oop, weak) if $mem == $oldval then $mem <-- $newval\n\t" -+ "xori $res, $res, 1\t# $res == 1 when success, #@weakCompareAndSwapNAcq" ++ "# $res == 1 when success, #@weakCompareAndSwapNAcq" + %} + + ins_encode %{ + __ cmpxchg_weak(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::uint32, + /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register); -+ __ xori($res$$Register, $res$$Register, 1); + %} + + ins_pipe(pipe_slow); @@ -33353,13 +33433,12 @@ index 0000000000..02d6167629 + + format %{ + "cmpxchg_weak_acq $mem, $oldval, $newval\t# (ptr, weak) if $mem == $oldval then $mem <-- $newval\n\t" -+ "xori $res, $res, 1\t# $res == 1 when success, #@weakCompareAndSwapPAcq" ++ "\t# $res == 1 when success, #@weakCompareAndSwapPAcq" + %} + + ins_encode %{ + __ cmpxchg_weak(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64, + /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register); -+ __ xori($res$$Register, $res$$Register, 1); + %} + + ins_pipe(pipe_slow); @@ -38397,10 +38476,10 @@ index 0000000000..7dda004cd3 \ No newline at end of file diff --git a/src/hotspot/cpu/riscv/sharedRuntime_riscv.cpp b/src/hotspot/cpu/riscv/sharedRuntime_riscv.cpp new file mode 100644 -index 0000000000..f41a496093 +index 0000000000..7b1112b388 --- /dev/null +++ b/src/hotspot/cpu/riscv/sharedRuntime_riscv.cpp -@@ -0,0 +1,2666 @@ +@@ -0,0 +1,2661 @@ +/* + * Copyright (c) 2003, 2020, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 2014, 2020, Red Hat Inc. All rights reserved. @@ -38532,7 +38611,6 @@ index 0000000000..f41a496093 +}; + +OopMap* RegisterSaver::save_live_registers(MacroAssembler* masm, int additional_frame_words, int* total_frame_words) { -+ assert_cond(masm != NULL && total_frame_words != NULL); + int frame_size_in_bytes = align_up(additional_frame_words * wordSize + ra_offset_in_bytes() + wordSize, 16); + // OopMap frame size is in compiler stack slots (jint's) not bytes or words + int frame_size_in_slots = frame_size_in_bytes / BytesPerInt; @@ -38580,7 +38658,6 @@ index 0000000000..f41a496093 +} + +void RegisterSaver::restore_live_registers(MacroAssembler* masm) { -+ assert_cond(masm != NULL); + __ pop_CPU_state(); + __ leave(); +} @@ -38711,7 +38788,6 @@ index 0000000000..f41a496093 + +// Patch the callers callsite with entry to compiled code if it exists. +static void patch_callers_callsite(MacroAssembler *masm) { -+ assert_cond(masm != NULL); + Label L; + __ ld(t0, Address(xmethod, in_bytes(Method::code_offset()))); + __ beqz(t0, L); @@ -38820,7 +38896,7 @@ index 0000000000..f41a496093 + __ sd(t0, Address(sp, next_off), /*temp register*/esp); +#ifdef ASSERT + // Overwrite the unused slot with known junk -+ __ li(t0, 0xdeadffffdeadaaaaul); ++ __ mv(t0, 0xdeadffffdeadaaaaul); + __ sd(t0, Address(sp, st_off), /*temp register*/esp); +#endif /* ASSERT */ + } else { @@ -38839,7 +38915,7 @@ index 0000000000..f41a496093 + // long/double in gpr +#ifdef ASSERT + // Overwrite the unused slot with known junk -+ __ li(t0, 0xdeadffffdeadaaabul); ++ __ mv(t0, 0xdeadffffdeadaaabul); + __ sd(t0, Address(sp, st_off), /*temp register*/esp); +#endif /* ASSERT */ + __ sd(r, Address(sp, next_off)); @@ -38855,7 +38931,7 @@ index 0000000000..f41a496093 + } else { +#ifdef ASSERT + // Overwrite the unused slot with known junk -+ __ li(t0, 0xdeadffffdeadaaacul); ++ __ mv(t0, 0xdeadffffdeadaaacul); + __ sd(t0, Address(sp, st_off), /*temp register*/esp); +#endif /* ASSERT */ + __ fsd(r_1->as_FloatRegister(), Address(sp, next_off)); @@ -39110,16 +39186,21 @@ index 0000000000..f41a496093 + return stk_args; +} + -+// On 64 bit we will store integer like items to the stack as -+// 64 bits items (riscv64 abi) even though java would only store -+// 32bits for a parameter. On 32bit it will simply be 32 bits -+// So this routine will do 32->32 on 32bit and 32->64 on 64bit ++// The C ABI specifies: ++// "integer scalars narrower than XLEN bits are widened according to the sign ++// of their type up to 32 bits, then sign-extended to XLEN bits." ++// Applies for both passed in register and stack. ++// ++// Java uses 32-bit stack slots; jint, jshort, jchar, jbyte uses one slot. ++// Native uses 64-bit stack slots for all integer scalar types. ++// ++// lw loads the Java stack slot, sign-extends and ++// sd store this widened integer into a 64 bit native stack slot. +static void move32_64(MacroAssembler* masm, VMRegPair src, VMRegPair dst) { -+ assert_cond(masm != NULL); + if (src.first()->is_stack()) { + if (dst.first()->is_stack()) { + // stack to stack -+ __ ld(t0, Address(fp, reg2offset_in(src.first()))); ++ __ lw(t0, Address(fp, reg2offset_in(src.first()))); + __ sd(t0, Address(sp, reg2offset_out(dst.first()))); + } else { + // stack to reg @@ -39145,7 +39226,6 @@ index 0000000000..f41a496093 + VMRegPair dst, + bool is_receiver, + int* receiver_offset) { -+ assert_cond(masm != NULL && map != NULL && receiver_offset != NULL); + // must pass a handle. First figure out the location we use as a handle + Register rHandle = dst.first()->is_stack() ? t1 : dst.first()->as_Register(); + @@ -39228,7 +39308,6 @@ index 0000000000..f41a496093 +static void float_move(MacroAssembler* masm, VMRegPair src, VMRegPair dst) { + assert(src.first()->is_stack() && dst.first()->is_stack() || + src.first()->is_reg() && dst.first()->is_reg() || src.first()->is_stack() && dst.first()->is_reg(), "Unexpected error"); -+ assert_cond(masm != NULL); + if (src.first()->is_stack()) { + if (dst.first()->is_stack()) { + __ lwu(t0, Address(fp, reg2offset_in(src.first()))); @@ -39249,7 +39328,6 @@ index 0000000000..f41a496093 + +// A long move +static void long_move(MacroAssembler* masm, VMRegPair src, VMRegPair dst) { -+ assert_cond(masm != NULL); + if (src.first()->is_stack()) { + if (dst.first()->is_stack()) { + // stack to stack @@ -39273,7 +39351,6 @@ index 0000000000..f41a496093 +static void double_move(MacroAssembler* masm, VMRegPair src, VMRegPair dst) { + assert(src.first()->is_stack() && dst.first()->is_stack() || + src.first()->is_reg() && dst.first()->is_reg() || src.first()->is_stack() && dst.first()->is_reg(), "Unexpected error"); -+ assert_cond(masm != NULL); + if (src.first()->is_stack()) { + if (dst.first()->is_stack()) { + __ ld(t0, Address(fp, reg2offset_in(src.first()))); @@ -39293,7 +39370,6 @@ index 0000000000..f41a496093 +} + +void SharedRuntime::save_native_result(MacroAssembler *masm, BasicType ret_type, int frame_slots) { -+ assert_cond(masm != NULL); + // We always ignore the frame_slots arg and just use the space just below frame pointer + // which by this time is free to use + switch (ret_type) { @@ -39311,7 +39387,6 @@ index 0000000000..f41a496093 +} + +void SharedRuntime::restore_native_result(MacroAssembler *masm, BasicType ret_type, int frame_slots) { -+ assert_cond(masm != NULL); + // We always ignore the frame_slots arg and just use the space just below frame pointer + // which by this time is free to use + switch (ret_type) { @@ -39329,7 +39404,6 @@ index 0000000000..f41a496093 +} + +static void save_args(MacroAssembler *masm, int arg_count, int first_arg, VMRegPair *args) { -+ assert_cond(masm != NULL && args != NULL); + RegSet x; + for ( int i = first_arg ; i < arg_count ; i++ ) { + if (args[i].first()->is_Register()) { @@ -39343,7 +39417,6 @@ index 0000000000..f41a496093 +} + +static void restore_args(MacroAssembler *masm, int arg_count, int first_arg, VMRegPair *args) { -+ assert_cond(masm != NULL && args != NULL); + RegSet x; + for ( int i = first_arg ; i < arg_count ; i++ ) { + if (args[i].first()->is_Register()) { @@ -39364,7 +39437,6 @@ index 0000000000..f41a496093 +} + +static void rt_call(MacroAssembler* masm, address dest) { -+ assert_cond(masm != NULL); + CodeBlob *cb = CodeCache::find_blob(dest); + if (cb) { + __ far_call(RuntimeAddress(dest)); @@ -39497,6 +39569,7 @@ index 0000000000..f41a496093 + int vep_offset = ((intptr_t)__ pc()) - start; + + // First instruction must be a nop as it may need to be patched on deoptimisation ++ MacroAssembler::assert_alignment(__ pc()); + __ nop(); + gen_special_dispatch(masm, + method, @@ -39648,6 +39721,7 @@ index 0000000000..f41a496093 + + // If we have to make this method not-entrant we'll overwrite its + // first instruction with a jump. ++ MacroAssembler::assert_alignment(__ pc()); + __ nop(); + + // Generate stack overflow check @@ -40307,7 +40381,7 @@ index 0000000000..f41a496093 + // Now it is safe to overwrite any register + + // Deopt during an exception. Save exec mode for unpack_frames. -+ __ li(xcpool, Deoptimization::Unpack_exception); // callee-saved ++ __ mv(xcpool, Deoptimization::Unpack_exception); // callee-saved + + // load throwing pc from JavaThread and patch it as the return address + // of the current frame. Then clear the field in JavaThread @@ -40368,7 +40442,7 @@ index 0000000000..f41a496093 + + __ lwu(xcpool, Address(x15, Deoptimization::UnrollBlock::unpack_kind_offset_in_bytes())); + Label noException; -+ __ li(t0, Deoptimization::Unpack_exception); ++ __ mv(t0, Deoptimization::Unpack_exception); + __ bne(xcpool, t0, noException); // Was exception pending? + __ ld(x10, Address(xthread, JavaThread::exception_oop_offset())); + __ ld(x13, Address(xthread, JavaThread::exception_pc_offset())); @@ -40447,7 +40521,7 @@ index 0000000000..f41a496093 + __ sub(sp, sp, x9); + + // Push interpreter frames in a loop -+ __ li(t0, 0xDEADDEAD); // Make a recognizable pattern ++ __ mv(t0, 0xDEADDEAD); // Make a recognizable pattern + __ mv(t1, t0); + Label loop; + __ bind(loop); @@ -40848,7 +40922,7 @@ index 0000000000..f41a496093 +// must do any gc of the args. +// +RuntimeStub* SharedRuntime::generate_resolve_blob(address destination, const char* name) { -+ assert (StubRoutines::forward_exception_entry() != NULL, "must be generated before"); ++ assert(StubRoutines::forward_exception_entry() != NULL, "must be generated before"); + + // allocate space for the code + ResourceMark rm; @@ -41069,7 +41143,7 @@ index 0000000000..f41a496093 +#endif // COMPILER2 diff --git a/src/hotspot/cpu/riscv/stubGenerator_riscv.cpp b/src/hotspot/cpu/riscv/stubGenerator_riscv.cpp new file mode 100644 -index 0000000000..9970229c5c +index 0000000000..272dd9aeb3 --- /dev/null +++ b/src/hotspot/cpu/riscv/stubGenerator_riscv.cpp @@ -0,0 +1,3743 @@ @@ -41429,13 +41503,13 @@ index 0000000000..9970229c5c + __ ld(j_rarg2, result); + Label is_long, is_float, is_double, exit; + __ ld(j_rarg1, result_type); -+ __ li(t0, (u1)T_OBJECT); ++ __ mv(t0, (u1)T_OBJECT); + __ beq(j_rarg1, t0, is_long); -+ __ li(t0, (u1)T_LONG); ++ __ mv(t0, (u1)T_LONG); + __ beq(j_rarg1, t0, is_long); -+ __ li(t0, (u1)T_FLOAT); ++ __ mv(t0, (u1)T_FLOAT); + __ beq(j_rarg1, t0, is_float); -+ __ li(t0, (u1)T_DOUBLE); ++ __ mv(t0, (u1)T_DOUBLE); + __ beq(j_rarg1, t0, is_double); + + // handle T_INT case @@ -41673,7 +41747,7 @@ index 0000000000..9970229c5c + + Label exit, error; + -+ __ push_reg(0x3000, sp); // save c_rarg2 and c_rarg3 ++ __ push_reg(RegSet::of(c_rarg2, c_rarg3), sp); // save c_rarg2 and c_rarg3 + + __ la(c_rarg2, ExternalAddress((address) StubRoutines::verify_oop_count_addr())); + __ ld(c_rarg3, Address(c_rarg2)); @@ -41699,12 +41773,12 @@ index 0000000000..9970229c5c + // return if everything seems ok + __ bind(exit); + -+ __ pop_reg(0x3000, sp); // pop c_rarg2 and c_rarg3 ++ __ pop_reg(RegSet::of(c_rarg2, c_rarg3), sp); // pop c_rarg2 and c_rarg3 + __ ret(); + + // handle errors + __ bind(error); -+ __ pop_reg(0x3000, sp); // pop c_rarg2 and c_rarg3 ++ __ pop_reg(RegSet::of(c_rarg2, c_rarg3), sp); // pop c_rarg2 and c_rarg3 + + __ pusha(); + // debug(char* msg, int64_t pc, int64_t regs[]) @@ -41817,7 +41891,7 @@ index 0000000000..9970229c5c + { + Label L; + -+ __ li(t0, 8); ++ __ mv(t0, 8); + __ bge(count, t0, L); + __ stop("genrate_copy_longs called with < 8 words"); + __ bind(L); @@ -43018,7 +43092,7 @@ index 0000000000..9970229c5c + } + + __ BIND(L_failed); -+ __ li(x10, -1); ++ __ mv(x10, -1); + __ leave(); // required for proper stackwalking of RuntimeStub frame + __ ret(); + @@ -44206,7 +44280,7 @@ index 0000000000..9970229c5c + ld(Rm, Address(Rm)); + add(Rn, Pn_base, Rn); + ld(Rn, Address(Rn)); -+ li(t0, 1); // set carry flag, i.e. no borrow ++ mv(t0, 1); // set carry flag, i.e. no borrow + align(16); + bind(loop); { + notr(Rn, Rn); @@ -44371,7 +44445,7 @@ index 0000000000..9970229c5c + enter(); + + // Make room. -+ li(Ra, 512); ++ mv(Ra, 512); + bgt(Rlen, Ra, argh); + slli(Ra, Rlen, exact_log2(4 * sizeof(jint))); + sub(Ra, sp, Ra); @@ -44397,7 +44471,7 @@ index 0000000000..9970229c5c + { + ld(Rn, Address(Pn_base)); + mul(Rlo_mn, Rn, inv); -+ li(t0, -1); ++ mv(t0, -1); + Label ok; + beq(Rlo_mn, t0, ok); + stop("broken inverse in Montgomery multiply"); @@ -44493,7 +44567,7 @@ index 0000000000..9970229c5c + enter(); + + // Make room. -+ li(Ra, 512); ++ mv(Ra, 512); + bgt(Rlen, Ra, argh); + slli(Ra, Rlen, exact_log2(4 * sizeof(jint))); + sub(Ra, sp, Ra); @@ -45042,7 +45116,7 @@ index 0000000000..0c9445e18a +#endif // CPU_RISCV_STUBROUTINES_RISCV_HPP diff --git a/src/hotspot/cpu/riscv/templateInterpreterGenerator_riscv.cpp b/src/hotspot/cpu/riscv/templateInterpreterGenerator_riscv.cpp new file mode 100644 -index 0000000000..e639fa7e12 +index 0000000000..34c85e8145 --- /dev/null +++ b/src/hotspot/cpu/riscv/templateInterpreterGenerator_riscv.cpp @@ -0,0 +1,1833 @@ @@ -45588,7 +45662,7 @@ index 0000000000..e639fa7e12 + address entry = __ pc(); + __ push(state); + __ call_VM(noreg, runtime_entry); -+ __ fence(0xf, 0xf); ++ __ membar(MacroAssembler::AnyAny); + __ dispatch_via(vtos, Interpreter::_normal_table.table_for(vtos)); + return entry; +} @@ -46703,7 +46777,7 @@ index 0000000000..e639fa7e12 + Label L_done; + + __ lbu(t0, Address(xbcp, 0)); -+ __ li(t1, Bytecodes::_invokestatic); ++ __ mv(t1, Bytecodes::_invokestatic); + __ bne(t1, t0, L_done); + + // The member name argument must be restored if _invokestatic is re-executed after a PopFrame call. @@ -46846,7 +46920,7 @@ index 0000000000..e639fa7e12 + __ push_reg(t0); + __ push_reg(x10); + __ mv(x10, (address) &BytecodeCounter::_counter_value); -+ __ li(t0, 1); ++ __ mv(t0, 1); + __ amoadd_d(zr, x10, t0, Assembler::aqrl); + __ pop_reg(x10); + __ pop_reg(t0); @@ -46881,10 +46955,10 @@ index 0000000000..e639fa7e12 +#endif // !PRODUCT diff --git a/src/hotspot/cpu/riscv/templateTable_riscv.cpp b/src/hotspot/cpu/riscv/templateTable_riscv.cpp new file mode 100644 -index 0000000000..84b1afc7dc +index 0000000000..c22fd3bfcd --- /dev/null +++ b/src/hotspot/cpu/riscv/templateTable_riscv.cpp -@@ -0,0 +1,4006 @@ +@@ -0,0 +1,4000 @@ +/* + * Copyright (c) 2003, 2020, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 2014, Red Hat Inc. All rights reserved. @@ -46961,15 +47035,12 @@ index 0000000000..84b1afc7dc + return iaddress(n); +} + -+static inline Address iaddress(Register r, Register temp, InterpreterMacroAssembler* _masm) { -+ assert_cond(_masm != NULL); ++static inline Address iaddress(Register r, Register temp, InterpreterMacroAssembler* _masm) { + _masm->shadd(temp, r, xlocals, temp, 3); + return Address(temp, 0); +} + -+static inline Address laddress(Register r, Register temp, -+ InterpreterMacroAssembler* _masm) { -+ assert_cond(_masm != NULL); ++static inline Address laddress(Register r, Register temp, InterpreterMacroAssembler* _masm) { + _masm->shadd(temp, r, xlocals, temp, 3); + return Address(temp, Interpreter::local_offset_in_bytes(1));; +} @@ -46978,8 +47049,7 @@ index 0000000000..84b1afc7dc + return iaddress(r, temp, _masm); +} + -+static inline Address daddress(Register r, Register temp, -+ InterpreterMacroAssembler* _masm) { ++static inline Address daddress(Register r, Register temp, InterpreterMacroAssembler* _masm) { + return laddress(r, temp, _masm); +} + @@ -47025,7 +47095,6 @@ index 0000000000..84b1afc7dc + Register val, + DecoratorSet decorators) { + assert(val == noreg || val == x10, "parameter is just for looks"); -+ assert_cond(_masm != NULL); + __ store_heap_oop(dst, val, x29, x11, decorators); +} + @@ -47033,7 +47102,6 @@ index 0000000000..84b1afc7dc + Address src, + Register dst, + DecoratorSet decorators) { -+ assert_cond(_masm != NULL); + __ load_heap_oop(dst, src, x7, x11, decorators); +} + @@ -47127,13 +47195,13 @@ index 0000000000..84b1afc7dc +void TemplateTable::iconst(int value) +{ + transition(vtos, itos); -+ __ li(x10, value); ++ __ mv(x10, value); +} + +void TemplateTable::lconst(int value) +{ + transition(vtos, ltos); -+ __ li(x10, value); ++ __ mv(x10, value); +} + +void TemplateTable::fconst(int value) @@ -50655,7 +50723,7 @@ index 0000000000..84b1afc7dc + __ j(done); + // Come here on success + __ bind(ok_is_subtype); -+ __ li(x10, 1); ++ __ mv(x10, 1); + + // Collect counts on whether this test sees NULLs a lot or not. + if (ProfileInterpreter) { @@ -51612,7 +51680,7 @@ index 0000000000..06b70020b4 +#endif // CPU_RISCV_VM_VMREG_RISCV_INLINE_HPP diff --git a/src/hotspot/cpu/riscv/vtableStubs_riscv.cpp b/src/hotspot/cpu/riscv/vtableStubs_riscv.cpp new file mode 100644 -index 0000000000..0d205240a5 +index 0000000000..448bb09ba7 --- /dev/null +++ b/src/hotspot/cpu/riscv/vtableStubs_riscv.cpp @@ -0,0 +1,260 @@ @@ -51690,7 +51758,7 @@ index 0000000000..0d205240a5 +#if (!defined(PRODUCT) && defined(COMPILER2)) + if (CountCompiledCalls) { + __ la(t2, ExternalAddress((address) SharedRuntime::nof_megamorphic_calls_addr())); -+ __ add_memory_int64(Address(t2), 1); ++ __ increment(Address(t2)); + } +#endif + @@ -51781,7 +51849,7 @@ index 0000000000..0d205240a5 +#if (!defined(PRODUCT) && defined(COMPILER2)) + if (CountCompiledCalls) { + __ la(x18, ExternalAddress((address) SharedRuntime::nof_megamorphic_calls_addr())); -+ __ add_memory_int64(Address(x18), 1); ++ __ increment(Address(x18)); + } +#endif + @@ -54503,10 +54571,10 @@ index a383297611..5e9228e705 100644 #endif // !CPU diff --git a/src/hotspot/share/runtime/thread.hpp b/src/hotspot/share/runtime/thread.hpp -index 34c8d98362..7cf95058fe 100644 +index 8ac6d63586..6bb38c40cc 100644 --- a/src/hotspot/share/runtime/thread.hpp +++ b/src/hotspot/share/runtime/thread.hpp -@@ -1259,7 +1259,7 @@ class JavaThread: public Thread { +@@ -1261,7 +1261,7 @@ class JavaThread: public Thread { address last_Java_pc(void) { return _anchor.last_Java_pc(); } // Safepoint support @@ -54572,6 +54640,99 @@ index 6605ab367c..7f1bcff6b3 100644 #ifdef VM_LITTLE_ENDIAN #define LITTLE_ENDIAN_ONLY(code) code #define BIG_ENDIAN_ONLY(code) +diff --git a/src/hotspot/share/utilities/vmassert_reinstall.hpp b/src/hotspot/share/utilities/vmassert_reinstall.hpp +new file mode 100644 +index 0000000000..32d31ac0c4 +--- /dev/null ++++ b/src/hotspot/share/utilities/vmassert_reinstall.hpp +@@ -0,0 +1,36 @@ ++/* ++ * Copyright (c) 2022, Oracle and/or its affiliates. All rights reserved. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ * ++ */ ++ ++// Intentionally no #include guard. May be included multiple times for effect. ++ ++// See vmassert_uninstall.hpp for usage. ++ ++// Remove possible stdlib assert macro (or any others, for that matter). ++#undef assert ++ ++// Reinstall HotSpot's assert macro, if previously defined. ++#ifdef vmassert ++#define assert(p, ...) vmassert(p, __VA_ARGS__) ++#endif ++ +diff --git a/src/hotspot/share/utilities/vmassert_uninstall.hpp b/src/hotspot/share/utilities/vmassert_uninstall.hpp +new file mode 100644 +index 0000000000..dd6d51633d +--- /dev/null ++++ b/src/hotspot/share/utilities/vmassert_uninstall.hpp +@@ -0,0 +1,45 @@ ++/* ++ * Copyright (c) 2022, Oracle and/or its affiliates. All rights reserved. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ * ++ */ ++ ++// Intentionally no #include guard. May be included multiple times for effect. ++ ++// The files vmassert_uninstall.hpp and vmassert_reinstall.hpp provide a ++// workaround for the name collision between HotSpot's assert macro and the ++// Standard Library's assert macro. When including a 3rd-party header that ++// uses (and so includes) the standard assert macro, wrap that inclusion with ++// includes of these two files, e.g. ++// ++// #include "utilities/vmassert_uninstall.hpp" ++// #include
++// #include "utilities/vmassert_reinstall.hpp" ++// ++// This removes the HotSpot macro definition while pre-processing the ++// 3rd-party header, then reinstates the HotSpot macro (if previously defined) ++// for following code. ++ ++// Remove HotSpot's assert macro, if present. ++#ifdef vmassert ++#undef assert ++#endif // vmassert ++ diff --git a/src/jdk.hotspot.agent/linux/native/libsaproc/LinuxDebuggerLocal.c b/src/jdk.hotspot.agent/linux/native/libsaproc/LinuxDebuggerLocal.c index 0d834302c5..45a927fb5e 100644 --- a/src/jdk.hotspot.agent/linux/native/libsaproc/LinuxDebuggerLocal.c @@ -56581,6 +56742,86 @@ index 7d7a6107ca..6552ce255f 100644 for(String s : KNOWN) { if(s.equals(cpu)) +diff --git a/test/hotspot/gtest/gc/shared/test_memset_with_concurrent_readers.cpp b/test/hotspot/gtest/gc/shared/test_memset_with_concurrent_readers.cpp +index 24f25b87af..7a3845e336 100644 +--- a/test/hotspot/gtest/gc/shared/test_memset_with_concurrent_readers.cpp ++++ b/test/hotspot/gtest/gc/shared/test_memset_with_concurrent_readers.cpp +@@ -1,5 +1,5 @@ + /* +- * Copyright (c) 2016, Oracle and/or its affiliates. All rights reserved. ++ * Copyright (c) 2016, 2022, Oracle and/or its affiliates. All rights reserved. + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. + * + * This code is free software; you can redistribute it and/or modify it +@@ -24,10 +24,13 @@ + #include "precompiled.hpp" + #include "gc/shared/memset_with_concurrent_readers.hpp" + #include "utilities/globalDefinitions.hpp" +-#include "unittest.hpp" + ++#include "utilities/vmassert_uninstall.hpp" + #include + #include ++#include "utilities/vmassert_reinstall.hpp" ++ ++#include "unittest.hpp" + + static unsigned line_byte(const char* line, size_t i) { + return unsigned(line[i]) & 0xFF; +diff --git a/test/hotspot/gtest/jfr/test_networkUtilization.cpp b/test/hotspot/gtest/jfr/test_networkUtilization.cpp +index 19d6a6e2c2..42cd18356b 100644 +--- a/test/hotspot/gtest/jfr/test_networkUtilization.cpp ++++ b/test/hotspot/gtest/jfr/test_networkUtilization.cpp +@@ -1,5 +1,5 @@ + /* +- * Copyright (c) 2018, Oracle and/or its affiliates. All rights reserved. ++ * Copyright (c) 2018, 2022, Oracle and/or its affiliates. All rights reserved. + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. + * + * This code is free software; you can redistribute it and/or modify it +@@ -42,11 +42,13 @@ + #include "utilities/globalDefinitions.hpp" + #include "utilities/growableArray.hpp" + +-#include "unittest.hpp" +- ++#include "utilities/vmassert_uninstall.hpp" + #include + #include + #include ++#include "utilities/vmassert_reinstall.hpp" ++ ++#include "unittest.hpp" + + namespace { + +diff --git a/test/hotspot/gtest/unittest.hpp b/test/hotspot/gtest/unittest.hpp +index 0494a0e240..91edf6adba 100644 +--- a/test/hotspot/gtest/unittest.hpp ++++ b/test/hotspot/gtest/unittest.hpp +@@ -28,19 +28,10 @@ + #include + + #define GTEST_DONT_DEFINE_TEST 1 +-#include "gtest/gtest.h" + +-// gtest/gtest.h includes assert.h which will define the assert macro, but hotspot has its +-// own standards incompatible assert macro that takes two parameters. +-// The workaround is to undef assert and then re-define it. The re-definition +-// must unfortunately be copied since debug.hpp might already have been +-// included and a second include wouldn't work due to the header guards in debug.hpp. +-#ifdef assert +- #undef assert +- #ifdef vmassert +- #define assert(p, ...) vmassert(p, __VA_ARGS__) +- #endif +-#endif ++#include "utilities/vmassert_uninstall.hpp" ++#include "gtest/gtest.h" ++#include "utilities/vmassert_reinstall.hpp" + + #define CONCAT(a, b) a ## b + diff --git a/test/hotspot/jtreg/compiler/c2/TestBit.java b/test/hotspot/jtreg/compiler/c2/TestBit.java index 7805918c28..823b9f39db 100644 --- a/test/hotspot/jtreg/compiler/c2/TestBit.java @@ -56611,6 +56852,152 @@ index 7805918c28..823b9f39db 100644 if (expectedTestBitInstruction != null) { output.shouldContain(expectedTestBitInstruction); +diff --git a/test/hotspot/jtreg/compiler/calls/TestManyArgs.java b/test/hotspot/jtreg/compiler/calls/TestManyArgs.java +new file mode 100644 +index 0000000000..fbd9c13d7c +--- /dev/null ++++ b/test/hotspot/jtreg/compiler/calls/TestManyArgs.java +@@ -0,0 +1,65 @@ ++/* ++ * Copyright (c) 2024, Oracle and/or its affiliates. All rights reserved. ++ * Copyright (c) 2024, Rivos Inc. All rights reserved. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ */ ++ ++/* @test ++ * @summary Pass values on stack. ++ * @requires os.arch == "riscv64" ++ * @run main/native compiler.calls.TestManyArgs ++ */ ++ ++package compiler.calls; ++ ++public class TestManyArgs { ++ static { ++ System.loadLibrary("TestManyArgs"); ++ } ++ ++ native static void scramblestack(); ++ ++ native static int checkargs(int arg0, short arg1, byte arg2, ++ int arg3, short arg4, byte arg5, ++ int arg6, short arg7, byte arg8, ++ int arg9, short arg10, byte arg11); ++ ++ static int compiledbridge(int arg0, short arg1, byte arg2, ++ int arg3, short arg4, byte arg5, ++ int arg6, short arg7, byte arg8, ++ int arg9, short arg10, byte arg11) { ++ return checkargs(arg0, arg1, arg2, arg3, arg4, arg5, ++ arg6, arg7, arg8, arg9, arg10, arg11); ++ } ++ ++ static public void main(String[] args) { ++ scramblestack(); ++ for (int i = 0; i < 20000; i++) { ++ int res = compiledbridge((int)0xf, (short)0xf, (byte)0xf, ++ (int)0xf, (short)0xf, (byte)0xf, ++ (int)0xf, (short)0xf, (byte)0xf, ++ (int)0xf, (short)0xf, (byte)0xf); ++ if (res != 0) { ++ throw new RuntimeException("Test failed"); ++ } ++ } ++ } ++} +diff --git a/test/hotspot/jtreg/compiler/calls/libTestManyArgs.c b/test/hotspot/jtreg/compiler/calls/libTestManyArgs.c +new file mode 100644 +index 0000000000..8836c79e43 +--- /dev/null ++++ b/test/hotspot/jtreg/compiler/calls/libTestManyArgs.c +@@ -0,0 +1,69 @@ ++/* ++ * Copyright (c) 2024, Oracle and/or its affiliates. All rights reserved. ++ * Copyright (c) 2024, Rivos Inc. All rights reserved. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ */ ++ ++#include "jni.h" ++ ++#ifdef riscv64 ++/* RV64 ABI pass all integers as 64-bit, in registers or on stack ++ * As compiler may choose to load smaller width than 64-bit if passed on stack, ++ * this test may not find any bugs. ++ * Therefore we trick the compiler todo 64-bit loads, ++ * by saying these args are jlongs. ++ */ ++JNIEXPORT jint JNICALL Java_compiler_calls_TestManyArgs_checkargs(JNIEnv* env, jclass jclazz, ++ jlong arg0, jlong arg1, jlong arg2, ++ jlong arg3, jlong arg4, jlong arg5, ++ jlong arg6, jlong arg7, jlong arg8, ++ jlong arg9, jlong arg10, jlong arg11) ++#else ++JNIEXPORT jint JNICALL Java_compiler_calls_TestManyArgs_checkargs(JNIEnv* env, jclass jclazz, ++ jint arg0, jshort arg1, jbyte arg2, ++ jint arg3, jshort arg4, jbyte arg5, ++ jint arg6, jshort arg7, jbyte arg8, ++ jint arg9, jshort arg10, jbyte arg11) ++#endif ++{ ++ if (arg0 != 0xf) return 1; ++ if (arg1 != 0xf) return 1; ++ if (arg2 != 0xf) return 1; ++ if (arg3 != 0xf) return 1; ++ if (arg4 != 0xf) return 1; ++ if (arg5 != 0xf) return 1; ++ if (arg6 != 0xf) return 1; ++ if (arg7 != 0xf) return 1; ++ if (arg8 != 0xf) return 1; ++ if (arg9 != 0xf) return 1; ++ if (arg10 != 0xf) return 1; ++ if (arg11 != 0xf) return 1; ++ return 0; ++} ++ ++JNIEXPORT ++void JNICALL Java_compiler_calls_TestManyArgs_scramblestack(JNIEnv* env, jclass jclazz) ++{ ++ volatile char stack[12*8]; ++ for (unsigned int i = 0; i < sizeof(stack); i++) { ++ stack[i] = (char)0xff; ++ } ++} diff --git a/test/hotspot/jtreg/compiler/floatingpoint/TestLibmIntrinsics.java b/test/hotspot/jtreg/compiler/floatingpoint/TestLibmIntrinsics.java new file mode 100644 index 0000000000..5a1b659bbe @@ -57251,6 +57638,82 @@ index 7774dabcb5..7afe3560f3 100644 public static final BooleanSupplier ANY_SHA_INSTRUCTION_AVAILABLE = new OrPredicate(IntrinsicPredicates.SHA1_INSTRUCTION_AVAILABLE, +diff --git a/test/hotspot/jtreg/gc/stress/TestStressG1Humongous.java b/test/hotspot/jtreg/gc/stress/TestStressG1Humongous.java +index 5aea51a24f..da63e02555 100644 +--- a/test/hotspot/jtreg/gc/stress/TestStressG1Humongous.java ++++ b/test/hotspot/jtreg/gc/stress/TestStressG1Humongous.java +@@ -24,14 +24,41 @@ + package gc.stress; + + /* +- * @test TestStressG1Humongous ++ * @test + * @key gc stress + * @summary Stress G1 by humongous allocations in situation near OOM + * @requires vm.gc.G1 + * @requires !vm.flightRecorder + * @library /test/lib + * @modules java.base/jdk.internal.misc +- * @run driver/timeout=1300 gc.stress.TestStressG1Humongous ++ * @run driver/timeout=180 gc.stress.TestStressG1Humongous 4 3 1.1 120 ++ */ ++ ++/* ++ * @test ++ * @requires vm.gc.G1 ++ * @requires !vm.flightRecorder ++ * @library /test/lib ++ * @modules java.base/jdk.internal.misc ++ * @run driver/timeout=180 gc.stress.TestStressG1Humongous 16 5 2.1 120 ++ */ ++ ++/* ++ * @test ++ * @requires vm.gc.G1 ++ * @requires !vm.flightRecorder ++ * @library /test/lib ++ * @modules java.base/jdk.internal.misc ++ * @run driver/timeout=180 gc.stress.TestStressG1Humongous 32 4 0.6 120 ++ */ ++ ++/* ++ * @test ++ * @requires vm.gc.G1 ++ * @requires !vm.flightRecorder ++ * @library /test/lib ++ * @modules java.base/jdk.internal.misc ++ * @run driver/timeout=900 gc.stress.TestStressG1Humongous 1 7 0.6 600 + */ + + import java.util.ArrayList; +@@ -48,17 +75,19 @@ import jdk.test.lib.process.OutputAnalyzer; + public class TestStressG1Humongous{ + + public static void main(String[] args) throws Exception { ++ if (args.length != 4) { ++ throw new IllegalArgumentException("Test expects 4 arguments"); ++ } ++ + // Limit heap size on 32-bit platforms + int heapSize = Platform.is32bit() ? 512 : 1024; +- // Heap size, region size, threads, humongous size, timeout +- run(heapSize, 4, 3, 1.1, 120); +- run(heapSize, 16, 5, 2.1, 120); +- run(heapSize, 32, 4, 0.6, 120); +- run(heapSize, 1, 7, 0.6, 600); +- } + +- private static void run(int heapSize, int regionSize, int threads, double humongousSize, int timeout) +- throws Exception { ++ // Region size, threads, humongous size, and timeout passed as @run arguments ++ int regionSize = Integer.parseInt(args[0]); ++ int threads = Integer.parseInt(args[1]); ++ double humongousSize = Double.parseDouble(args[2]); ++ int timeout = Integer.parseInt(args[3]); ++ + ArrayList options = new ArrayList<>(); + Collections.addAll(options, Utils.getTestJavaOpts()); + Collections.addAll(options, diff --git a/test/hotspot/jtreg/runtime/NMT/CheckForProperDetailStackTrace.java b/test/hotspot/jtreg/runtime/NMT/CheckForProperDetailStackTrace.java index 57256aa5a3..d4d43b01ae 100644 --- a/test/hotspot/jtreg/runtime/NMT/CheckForProperDetailStackTrace.java @@ -57304,6 +57767,620 @@ index 126a43a900..feb4de5388 100644 BITNESS("is32bit", "is64bit"), OS("isAix", "isLinux", "isOSX", "isSolaris", "isWindows"), VM_TYPE("isClient", "isServer", "isGraal", "isMinimal", "isZero", "isEmbedded"), +diff --git a/test/jdk/java/awt/List/MouseDraggedOutCauseScrollingTest/MouseDraggedOutCauseScrollingTest.html b/test/jdk/java/awt/List/MouseDraggedOutCauseScrollingTest/MouseDraggedOutCauseScrollingTest.html +deleted file mode 100644 +index 7049e82703..0000000000 +--- a/test/jdk/java/awt/List/MouseDraggedOutCauseScrollingTest/MouseDraggedOutCauseScrollingTest.html ++++ /dev/null +@@ -1,43 +0,0 @@ +- +- +- +- +- +- ManualYesNoTest +- +- +- +-

ManualYesNoTest
Bug ID:

+- +-

See the dialog box (usually in upper left corner) for instructions

+- +- +- +- +diff --git a/test/jdk/java/awt/List/MouseDraggedOutCauseScrollingTest/MouseDraggedOutCauseScrollingTest.java b/test/jdk/java/awt/List/MouseDraggedOutCauseScrollingTest/MouseDraggedOutCauseScrollingTest.java +index 8b509a1231..446b7a3a93 100644 +--- a/test/jdk/java/awt/List/MouseDraggedOutCauseScrollingTest/MouseDraggedOutCauseScrollingTest.java ++++ b/test/jdk/java/awt/List/MouseDraggedOutCauseScrollingTest/MouseDraggedOutCauseScrollingTest.java +@@ -1,5 +1,5 @@ + /* +- * Copyright (c) 2013, Oracle and/or its affiliates. All rights reserved. ++ * Copyright (c) 2013, 2024, Oracle and/or its affiliates. All rights reserved. + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. + * + * This code is free software; you can redistribute it and/or modify it +@@ -22,29 +22,29 @@ + */ + + /* +- test ++ @test + @bug 6243382 8006070 + @summary Dragging of mouse outside of a List and Choice area don't work properly on XAWT +- @author Dmitry.Cherepanov@SUN.COM area=awt.list +- @run applet/manual=yesno MouseDraggedOutCauseScrollingTest.html ++ @requires (os.family == "linux") ++ @library /java/awt/regtesthelpers ++ @run main/manual MouseDraggedOutCauseScrollingTest + */ + +-import java.applet.Applet; +-import java.awt.*; ++import java.awt.Choice; ++import java.awt.Frame; ++import java.awt.GridLayout; ++import java.awt.List; ++import java.awt.Toolkit; + +-public class MouseDraggedOutCauseScrollingTest extends Applet +-{ +- Choice choice; +- List singleList; +- List multipleList; ++public class MouseDraggedOutCauseScrollingTest { + +- public void init() +- { +- this.setLayout (new GridLayout (1, 3)); ++ static Frame createUI() { ++ Frame frame = new Frame("MouseDraggedOutCausesScrollingTest"); ++ frame.setLayout(new GridLayout(1, 3)); + +- choice = new Choice(); +- singleList = new List(3, false); +- multipleList = new List(3, true); ++ Choice choice = new Choice(); ++ List singleList = new List(3, false); ++ List multipleList = new List(3, true); + + choice.add("Choice"); + for (int i = 1; i < 100; i++){ +@@ -59,188 +59,66 @@ public class MouseDraggedOutCauseScrollingTest extends Applet + for (int i = 1; i < 100; i++) + multipleList.add(""+i); + +- this.add(choice); +- this.add(singleList); +- this.add(multipleList); ++ frame.add(choice); ++ frame.add(singleList); ++ frame.add(multipleList); ++ frame.setSize(400, 100); ++ return frame; ++ } + ++ public static void main(String[] args) throws Exception { + String toolkitName = Toolkit.getDefaultToolkit().getClass().getName(); ++ + if (!toolkitName.equals("sun.awt.X11.XToolkit")) { +- String[] instructions = +- { +- "This test is not applicable to the current platform. Press PASS" +- }; +- Sysout.createDialogWithInstructions( instructions ); +- } else { +- String[] instructions = +- { +- "0) Please note, that this is only Motif/XAWT test. At first, make the applet active", +- "1.1) Click on the choice", +- "1.2) Press the left button of the mouse and keep on any item of the choice, for example 5", +- "1.3) Drag mouse out of the area of the unfurled list, at the same time hold the X coordinate of the mouse position about the same", +- "1.4) To make sure, that when the Y coordinate of the mouse position higher of the upper bound of the list then scrolling UP of the list and selected item changes on the upper. If not, the test failed", +- "1.5) To make sure, that when the Y coordinate of the mouse position under of the lower bound of the list then scrolling DOWN of the list and selected item changes on the lower. If not, the test failed", +- "-----------------------------------", +- "2.1) Click on the single list", +- "2.2) Press the left button of the mouse and keep on any item of the list, for example 5", +- "2.3) Drag mouse out of the area of the unfurled list, at the same time hold the X coordinate of the mouse position about the same", +- "2.4) To make sure, that when the Y coordinate of the mouse position higher of the upper bound of the list then scrolling UP of the list and selected item changes on the upper. If not, the test failed", +- "2.5) To make sure, that when the Y coordinate of the mouse position under of the lower bound of the list then scrolling DOWN of the list and selected item changes on the lower. If not, the test failed", +- "-----------------------------------", +- "3.1) Click on the multiple list", +- "3.2) Press the left button of the mouse and keep on any item of the list, for example 5", +- "3.3) Drag mouse out of the area of the unfurled list, at the same time hold the X coordinate of the mouse position about the same", +- "3.4) To make sure, that when the Y coordinate of the mouse position higher of the upper bound of the list then scrolling of the list NO OCCURED and selected item NO CHANGES on the upper. If not, the test failed", +- "3.5) To make sure, that when the Y coordinate of the mouse position under of the lower bound of the list then scrolling of the list NO OCCURED and selected item NO CHANGES on the lower. If not, the test failed", +- "4) Test passed." +- }; +- Sysout.createDialogWithInstructions( instructions ); ++ System.out.println(INAPPLICABLE); ++ return; + } + +- }//End init() +- +- public void start () +- { +- setSize (400,100); +- setVisible(true); +- validate(); +- +- }// start() +- +-}// class ManualYesNoTest +- +-/**************************************************** +- Standard Test Machinery +- DO NOT modify anything below -- it's a standard +- chunk of code whose purpose is to make user +- interaction uniform, and thereby make it simpler +- to read and understand someone else's test. +- ****************************************************/ +- +-/** +- This is part of the standard test machinery. +- It creates a dialog (with the instructions), and is the interface +- for sending text messages to the user. +- To print the instructions, send an array of strings to Sysout.createDialog +- WithInstructions method. Put one line of instructions per array entry. +- To display a message for the tester to see, simply call Sysout.println +- with the string to be displayed. +- This mimics System.out.println but works within the test harness as well +- as standalone. +- */ +- +-class Sysout +-{ +- private static TestDialog dialog; +- +- public static void createDialogWithInstructions( String[] instructions ) +- { +- dialog = new TestDialog( new Frame(), "Instructions" ); +- dialog.printInstructions( instructions ); +- dialog.setVisible(true); +- println( "Any messages for the tester will display here." ); +- } +- +- public static void createDialog( ) +- { +- dialog = new TestDialog( new Frame(), "Instructions" ); +- String[] defInstr = { "Instructions will appear here. ", "" } ; +- dialog.printInstructions( defInstr ); +- dialog.setVisible(true); +- println( "Any messages for the tester will display here." ); +- } +- +- +- public static void printInstructions( String[] instructions ) +- { +- dialog.printInstructions( instructions ); +- } +- +- +- public static void println( String messageIn ) +- { +- dialog.displayMessage( messageIn ); +- } +- +-}// Sysout class +- +-/** +- This is part of the standard test machinery. It provides a place for the +- test instructions to be displayed, and a place for interactive messages +- to the user to be displayed. +- To have the test instructions displayed, see Sysout. +- To have a message to the user be displayed, see Sysout. +- Do not call anything in this dialog directly. +- */ +-class TestDialog extends Dialog +-{ +- +- TextArea instructionsText; +- TextArea messageText; +- int maxStringLength = 80; +- +- //DO NOT call this directly, go through Sysout +- public TestDialog( Frame frame, String name ) +- { +- super( frame, name ); +- int scrollBoth = TextArea.SCROLLBARS_BOTH; +- instructionsText = new TextArea( "", 15, maxStringLength, scrollBoth ); +- add( "North", instructionsText ); +- +- messageText = new TextArea( "", 5, maxStringLength, scrollBoth ); +- add("Center", messageText); +- +- pack(); +- +- setVisible(true); +- }// TestDialog() +- +- //DO NOT call this directly, go through Sysout +- public void printInstructions( String[] instructions ) +- { +- //Clear out any current instructions +- instructionsText.setText( "" ); +- +- //Go down array of instruction strings +- +- String printStr, remainingStr; +- for( int i=0; i < instructions.length; i++ ) +- { +- //chop up each into pieces maxSringLength long +- remainingStr = instructions[ i ]; +- while( remainingStr.length() > 0 ) +- { +- //if longer than max then chop off first max chars to print +- if( remainingStr.length() >= maxStringLength ) +- { +- //Try to chop on a word boundary +- int posOfSpace = remainingStr. +- lastIndexOf( ' ', maxStringLength - 1 ); +- +- if( posOfSpace <= 0 ) posOfSpace = maxStringLength - 1; +- +- printStr = remainingStr.substring( 0, posOfSpace + 1 ); +- remainingStr = remainingStr.substring( posOfSpace + 1 ); +- } +- //else just print +- else +- { +- printStr = remainingStr; +- remainingStr = ""; +- } +- +- instructionsText.append( printStr + "\n" ); +- +- }// while +- +- }// for +- +- }//printInstructions() +- +- //DO NOT call this directly, go through Sysout +- public void displayMessage( String messageIn ) +- { +- messageText.append( messageIn + "\n" ); +- System.out.println(messageIn); ++ PassFailJFrame ++ .builder() ++ .instructions(INSTRUCTIONS) ++ .rows(40) ++ .columns(70) ++ .testUI(MouseDraggedOutCauseScrollingTest::createUI) ++ .build() ++ .awaitAndCheck(); + } + +-}// TestDialog class ++ static final String INAPPLICABLE = "The test is not applicable to the current platform. Test PASSES."; ++ static final String INSTRUCTIONS = "0) Please note, that this is an XAWT/Linux only test. First, make the test window is active.\n" + ++ "-----------------------------------\n" + ++ "1.1) Click on the Choice.\n" + ++ "1.2) Press and hold down the left button of the mouse to select (eg) item 5 in the choice.\n" + ++ "1.3) Drag the mouse vertically out of the area of the open list,\n" + ++ " keeping the X coordinate of the mouse position about the same.\n" + ++ "1.4) Check that when the Y coordinate of the mouse position is higher than the upper bound of the list\n" + ++ " then the list continues to scrolls UP and the selected item changes at the top until you reach the topmost item.\n" + ++ " If not, the test failed. Press FAIL.\n" + ++ "1.5) Check that when the Y coordinate of the mouse position is lower than the lower bound of the list\n" + ++ " then the list continues to scroll DOWN and the selected item changes at the bottom until you reach the bottommost item.\n" + ++ " If not, the test failed. Press FAIL.\n" + ++ "-----------------------------------\n" + ++ "2.1) Click on the Single List.\n" + ++ "2.2) Press and hold down the left button of the mouse to select (eg) item 5 in the list.\n" + ++ "2.3) Drag the mouse vertically out of the area of the open list,\n" + ++ " keeping the X coordinate of the mouse position about the same.\n" + ++ "2.4) Check that when the Y coordinate of the mouse position is higher than the upper bound of the list\n" + ++ " then the list continues to scrolls UP and the selected item changes at the top until you reach the topmost item.\n" + ++ " If not, the test failed. Press FAIL.\n" + ++ "2.5) Check that when the Y coordinate of the mouse position is lower than the lower bound of the list\n" + ++ " then the list continues to scroll DOWN and the selected item changes at the bottom until you reach the bottommost item.\n" + ++ " If not, the test failed. Press FAIL.\n" + ++ "-----------------------------------\n" + ++ "3.1) Click on the Multiple List.\n" + ++ "3.2) Press and hold down the left button of the mouse to select (eg) item 5 in the list.\n" + ++ "3.3) Drag the mouse vertically out of the area of the open list,\n" + ++ " keeping the X coordinate of the mouse position about the same.\n" + ++ "3.4) Check that when the Y coordinate of the mouse is higher than the upper bound of the list\n" + ++ " that scrolling of the list DOES NOT OCCUR and the selected item IS UNCHANGED at the top.\n" + ++ " If not, the test failed. Press FAIL.\n" + ++ "3.5) Check that when the Y coordinate of the mouse is below the lower bound of the list\n" + ++ " that scrolling of the list DOES NOT OCCUR and the selected item IS UNCHANGED at the bottom.\n" + ++ " If not, the test failed. Press FAIL.\n" + ++ "-----------------------------------\n" + ++ "4) The test has now passed. Press PASS."; ++} +diff --git a/test/jdk/java/awt/Modal/PrintDialogsTest/PrintDialogsTest.html b/test/jdk/java/awt/Modal/PrintDialogsTest/PrintDialogsTest.html +index a562b886ab..e69de29bb2 100644 +--- a/test/jdk/java/awt/Modal/PrintDialogsTest/PrintDialogsTest.html ++++ b/test/jdk/java/awt/Modal/PrintDialogsTest/PrintDialogsTest.html +@@ -1,44 +0,0 @@ +- +- +- +- +- PrintDialogsTest +- +- +- +- +-Please select dialog modality type and parent; also select +-the print auxiliary dialog to be displayed (Page Setup or Print dialog). +-Then click "Start test" button. +- +-When the windows will appear check if modal blocking for Dialog works as expected. +-Then push "Open" button on the Dialog to show the auxiliary dialog and check +-if it blocks the rest of the application. Then close it and check correctness +-of modal blocking behavior for the Dialog again. To close all the test +-windows please push "Finish" button. +- +-To finish the overall test push "Pass" or "Fail" button depending on result. +- +- +- +diff --git a/test/jdk/java/awt/Modal/PrintDialogsTest/PrintDialogsTest.java b/test/jdk/java/awt/Modal/PrintDialogsTest/PrintDialogsTest.java +index 989c48295b..8a07d284a9 100644 +--- a/test/jdk/java/awt/Modal/PrintDialogsTest/PrintDialogsTest.java ++++ b/test/jdk/java/awt/Modal/PrintDialogsTest/PrintDialogsTest.java +@@ -1,5 +1,5 @@ + /* +- * Copyright (c) 2007, 2014, Oracle and/or its affiliates. All rights reserved. ++ * Copyright (c) 2007, 2024, Oracle and/or its affiliates. All rights reserved. + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. + * + * This code is free software; you can redistribute it and/or modify it +@@ -25,21 +25,75 @@ + /* + * @test + * @bug 8055836 8057694 8055752 +- * @summary Check if Print and Page Setup dialogs lock other windows; ++ * @summary Check if Print and Page Setup dialogs block other windows; + * check also correctness of modal behavior for other dialogs. +- * +- * @run applet/manual=yesno PrintDialogsTest.html ++ * @library /java/awt/regtesthelpers ++ * @run main/manual PrintDialogsTest + */ + + +-import java.applet.Applet; +-import java.awt.*; ++import java.awt.BorderLayout; ++import java.awt.Button; ++import java.awt.Checkbox; ++import java.awt.CheckboxGroup; ++import java.awt.Dialog; ++import java.awt.Frame; ++import java.awt.EventQueue; ++import java.awt.GridLayout; ++import java.awt.Label; ++import java.awt.Panel; + + import java.awt.event.ActionEvent; + import java.awt.event.ActionListener; + + +-public class PrintDialogsTest extends Applet implements ActionListener { ++public class PrintDialogsTest extends Panel implements ActionListener { ++ ++ static final String INSTRUCTIONS = ++ "This test is free format, which means there is no enforced or guided sequence." + "\n" + ++ ++ "Please select each of " + "\n" + ++ "(a) The dialog parent type." + "\n" + ++ "(b) The dialog modality type" + "\n" + ++ "(c) The print dialog type (Print dialog or Page Setup dialog)" + "\n" + ++ ++ "Once the choices have been made click the \"Start test\" button." + "\n" + ++ ++ "Three windows will appear" + "\n" + ++ "(1) A Frame or a Dialog - in the case you selected \"Dialog\" as the parent type" + "\n" + ++ "(2) a Window (ie an undecorated top-level)" + "\n" + ++ "(3) A dialog with two buttons \"Open\" and \"Finish\"" + "\n" + ++ ++ "Now check as follows whether modal blocking works as expected." + "\n" + ++ "Windows (1) and (2) contain a button which you should be able to press" + "\n" + ++ "ONLY if you selected \"Non-modal\", or \"Modeless\" for modality type." + "\n" + ++ "In other cases window (3) will block input to (1) and (2)" + "\n" + ++ ++ "Then push the \"Open\" button on the Dialog to show the printing dialog and check" + "\n" + ++ "if it blocks the rest of the application - ie all of windows (1), (2) and (3)" + "\n" + ++ "should ALWAYS be blocked when the print dialog is showing." + "\n" + ++ "Now cancel the printing dialog and check the correctness of modal blocking" + "\n" + ++ "behavior for the Dialog again." + "\n" + ++ "To close all the 3 test windows please push the \"Finish\" button." + "\n" + ++ ++ "Repeat all the above for different combinations, which should include" + "\n" + ++ "using all of the Dialog parent choices and all of the Dialog Modality types." + "\n" + ++ ++ "If any behave incorrectly, note the combination of choices and press Fail." + "\n" + ++ ++ "If all behave correctly, press Pass."; ++ ++ public static void main(String[] args) throws Exception { ++ ++ PassFailJFrame.builder() ++ .instructions(INSTRUCTIONS) ++ .rows(35) ++ .columns(60) ++ .testUI(PrintDialogsTest::createUI) ++ .testTimeOut(10) ++ .build() ++ .awaitAndCheck(); ++ } + + private Button btnTest; + private Checkbox cbPage, cbPrint, +@@ -48,6 +102,14 @@ public class PrintDialogsTest extends Applet implements ActionListener { + + private CheckboxGroup groupDialog, groupParent, groupModType; + ++ private static Frame createUI() { ++ Frame frame = new Frame("Dialog Modality Testing"); ++ PrintDialogsTest test = new PrintDialogsTest(); ++ test.createGUI(); ++ frame.add(test); ++ frame.pack(); ++ return frame; ++ } + + public void actionPerformed(ActionEvent e) { + +@@ -99,13 +161,13 @@ public class PrintDialogsTest extends Applet implements ActionListener { + + setLayout(new BorderLayout()); + +- setSize(350, 200); + Panel panel = new Panel(); +- panel.setLayout(new GridLayout(18, 1)); ++ panel.setLayout(new GridLayout(21, 1)); + + btnTest = new Button("Start test"); + btnTest.addActionListener(this); + panel.add(btnTest); ++ panel.add(new Label(" ")); // spacing + + + panel.add(new Label("Dialog parent:")); +@@ -123,6 +185,7 @@ public class PrintDialogsTest extends Applet implements ActionListener { + panel.add(cbHiddFrm); + panel.add(cbDlg); + panel.add(cbFrm); ++ panel.add(new Label(" ")); // spacing + + panel.add(new Label("Dialog modality type:")); + groupModType = new CheckboxGroup(); +@@ -139,7 +202,7 @@ public class PrintDialogsTest extends Applet implements ActionListener { + panel.add(cbDocModal); + panel.add(cbTKModal); + panel.add(cbModeless); +- add(panel); ++ panel.add(new Label(" ")); // spacing + + panel.add(new Label("Print dialog type:")); + groupDialog = new CheckboxGroup(); +@@ -148,13 +211,6 @@ public class PrintDialogsTest extends Applet implements ActionListener { + panel.add(cbPage); + panel.add(cbPrint); + +- validate(); +- setVisible(true); +- } +- +- public void start() { +- try { +- EventQueue.invokeAndWait(this::createGUI); +- } catch (Exception e) {} ++ add(panel); + } + } +diff --git a/test/jdk/javax/naming/module/RunBasic.java b/test/jdk/javax/naming/module/RunBasic.java +index 512062de40..f9d259d620 100644 +--- a/test/jdk/javax/naming/module/RunBasic.java ++++ b/test/jdk/javax/naming/module/RunBasic.java +@@ -134,7 +134,15 @@ public class RunBasic { + opts.add("test/" + clsName); + opts.add("ldap://" + HOST_NAME + "/dc=ie,dc=oracle,dc=com"); + System.out.println("Running with the '" + desc + "' module..."); ++<<<<<<< HEAD ++ runJava("-Dtest.src=" + TEST_SRC, "-p", "mods", "-m", "test/" + clsName, ++ "ldap://" + HOST_NAME + "/dc=ie,dc=oracle,dc=com"); ++||||||| 82c330b464 ++ runJava("-Dtest.src=" + TEST_SRC, "-p", "mods", "-m", "test/" + clsName, ++ "ldap://localhost/dc=ie,dc=oracle,dc=com"); ++======= + runJava(opts.toArray(String[]::new)); ++>>>>>>> cee8535a9d3de8558b4b5028d68e397e508bef71 + } + + private static void runJava(String... opts) throws Throwable { +diff --git a/test/jdk/jdk/jfr/event/oldobject/TestListenerLeak.java b/test/jdk/jdk/jfr/event/oldobject/TestListenerLeak.java +index a275eda517..2cb092e60b 100644 +--- a/test/jdk/jdk/jfr/event/oldobject/TestListenerLeak.java ++++ b/test/jdk/jdk/jfr/event/oldobject/TestListenerLeak.java +@@ -1,5 +1,5 @@ + /* +- * Copyright (c) 2018, Oracle and/or its affiliates. All rights reserved. ++ * Copyright (c) 2018, 2023, Oracle and/or its affiliates. All rights reserved. + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. + * + * This code is free software; you can redistribute it and/or modify it +@@ -74,15 +74,17 @@ public class TestListenerLeak { + + public static void main(String[] args) throws Exception { + WhiteBox.setWriteAllObjectSamples(true); +- +- try (Recording r = new Recording()) { +- r.enable(EventNames.OldObjectSample).withStackTrace().with("cutoff", "infinity"); +- r.start(); +- listenerLeak(); +- r.stop(); +- List events = Events.fromRecording(r); +- if (OldObjects.countMatchingEvents(events, Stuff[].class, null, null, -1, "listenerLeak") == 0) { +- throw new Exception("Could not find leak with " + Stuff[].class); ++ while (true) { ++ try (Recording r = new Recording()) { ++ r.enable(EventNames.OldObjectSample).withStackTrace().with("cutoff", "infinity"); ++ r.start(); ++ listenerLeak(); ++ r.stop(); ++ List events = Events.fromRecording(r); ++ if (OldObjects.countMatchingEvents(events, Stuff[].class, null, null, -1, "listenerLeak") != 0) { ++ return; // Success ++ } ++ System.out.println("Could not find leak with " + Stuff[].class + ". Retrying."); + } + } + } diff --git a/test/jdk/jdk/jfr/event/os/TestCPUInformation.java b/test/jdk/jdk/jfr/event/os/TestCPUInformation.java index 7990c49a1f..abeff80e5e 100644 --- a/test/jdk/jdk/jfr/event/os/TestCPUInformation.java @@ -57326,6 +58403,137 @@ index 7990c49a1f..abeff80e5e 100644 } } } +diff --git a/test/jdk/sun/util/calendar/zi/Month.java b/test/jdk/sun/util/calendar/zi/Month.java +index cb60b8d441..bab909f763 100644 +--- a/test/jdk/sun/util/calendar/zi/Month.java ++++ b/test/jdk/sun/util/calendar/zi/Month.java +@@ -1,5 +1,5 @@ + /* +- * Copyright (c) 2000, 2018, Oracle and/or its affiliates. All rights reserved. ++ * Copyright (c) 2000, 2024, Oracle and/or its affiliates. All rights reserved. + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. + * + * This code is free software; you can redistribute it and/or modify it +@@ -21,11 +21,6 @@ + * questions. + */ + +-import java.util.ArrayList; +-import java.util.HashMap; +-import java.util.List; +-import java.util.Map; +- + /** + * Month enum handles month related manipulation. + * +@@ -47,15 +42,6 @@ enum Month { + + private final String abbr; + +- private static final Map abbreviations +- = new HashMap(12); +- +- static { +- for (Month m : Month.values()) { +- abbreviations.put(m.abbr, m); +- } +- } +- + private Month(String abbr) { + this.abbr = abbr; + } +@@ -70,11 +56,22 @@ enum Month { + * @return the Month value + */ + static Month parse(String name) { +- Month m = abbreviations.get(name); +- if (m != null) { +- return m; +- } +- return null; ++ int len = name.length(); ++ ++ if (name.regionMatches(true, 0, "January", 0, len)) return Month.JANUARY; ++ if (name.regionMatches(true, 0, "February", 0, len)) return Month.FEBRUARY; ++ if (name.regionMatches(true, 0, "March", 0, len)) return Month.MARCH; ++ if (name.regionMatches(true, 0, "April", 0, len)) return Month.APRIL; ++ if (name.regionMatches(true, 0, "May", 0, len)) return Month.MAY; ++ if (name.regionMatches(true, 0, "June", 0, len)) return Month.JUNE; ++ if (name.regionMatches(true, 0, "July", 0, len)) return Month.JULY; ++ if (name.regionMatches(true, 0, "August", 0, len)) return Month.AUGUST; ++ if (name.regionMatches(true, 0, "September", 0, len)) return Month.SEPTEMBER; ++ if (name.regionMatches(true, 0, "October", 0, len)) return Month.OCTOBER; ++ if (name.regionMatches(true, 0, "November", 0, len)) return Month.NOVEMBER; ++ if (name.regionMatches(true, 0, "December", 0, len)) return Month.DECEMBER; ++ ++ throw new IllegalArgumentException("Unknown month: " + name); + } + + /** +diff --git a/test/jdk/sun/util/calendar/zi/RuleDay.java b/test/jdk/sun/util/calendar/zi/RuleDay.java +index bc730944b4..9cd81c1e52 100644 +--- a/test/jdk/sun/util/calendar/zi/RuleDay.java ++++ b/test/jdk/sun/util/calendar/zi/RuleDay.java +@@ -1,5 +1,5 @@ + /* +- * Copyright (c) 2000, 2018, Oracle and/or its affiliates. All rights reserved. ++ * Copyright (c) 2000, 2024, Oracle and/or its affiliates. All rights reserved. + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. + * + * This code is free software; you can redistribute it and/or modify it +@@ -21,11 +21,6 @@ + * questions. + */ + +-import java.util.ArrayList; +-import java.util.HashMap; +-import java.util.List; +-import java.util.Map; +- + /** + * RuleDay class represents the value of the "ON" field. The day of + * week values start from 1 following the {@link java.util.Calendar} +@@ -34,13 +29,6 @@ import java.util.Map; + * @since 1.4 + */ + class RuleDay { +- private static final Map abbreviations = new HashMap(7); +- static { +- for (DayOfWeek day : DayOfWeek.values()) { +- abbreviations.put(day.getAbbr(), day); +- } +- } +- + private String dayName = null; + private DayOfWeek dow; + private boolean lastOne = false; +@@ -166,13 +154,23 @@ class RuleDay { + return sign + toString(d); + } + +- private static DayOfWeek getDOW(String abbr) { +- return abbreviations.get(abbr); ++ private static DayOfWeek getDOW(String name) { ++ int len = name.length(); ++ ++ if (name.regionMatches(true, 0, "Monday", 0, len)) return DayOfWeek.MONDAY; ++ if (name.regionMatches(true, 0, "Tuesday", 0, len)) return DayOfWeek.TUESDAY; ++ if (name.regionMatches(true, 0, "Wednesday", 0, len)) return DayOfWeek.WEDNESDAY; ++ if (name.regionMatches(true, 0, "Thursday", 0, len)) return DayOfWeek.THURSDAY; ++ if (name.regionMatches(true, 0, "Friday", 0, len)) return DayOfWeek.FRIDAY; ++ if (name.regionMatches(true, 0, "Saturday", 0, len)) return DayOfWeek.SATURDAY; ++ if (name.regionMatches(true, 0, "Sunday", 0, len)) return DayOfWeek.SUNDAY; ++ ++ throw new IllegalArgumentException("Unknown day-of-week: " + name); + } + + /** + * Converts the specified day of week value to the day-of-week +- * name defined in {@link java.util.Calenda}. ++ * name defined in {@link java.util.Calendar}. + * @param dow 1-based day of week value + * @return the Calendar day of week name with "Calendar." prefix. + * @throws IllegalArgumentException if the specified dow value is out of range. diff --git a/test/lib/jdk/test/lib/Platform.java b/test/lib/jdk/test/lib/Platform.java index 6269373c2b..e1511772e7 100644 --- a/test/lib/jdk/test/lib/Platform.java diff --git a/G1-iterate-region-by-bitmap-rather-than-obj-size-in.patch b/G1-iterate-region-by-bitmap-rather-than-obj-size-in.patch index 8d4548aad36df00f937ee2babb039206bb059a35..fc0fb3465ddce315670454a0d7996372dcc0eaaa 100755 --- a/G1-iterate-region-by-bitmap-rather-than-obj-size-in.patch +++ b/G1-iterate-region-by-bitmap-rather-than-obj-size-in.patch @@ -367,4 +367,4 @@ index 000000000..85b49171c --- /dev/null +++ b/version.txt @@ -0,0 +1 @@ -+11.0.24.0.13 ++11.0.25.0.13 diff --git a/LoongArch64-support.patch b/LoongArch64-support.patch index bf78938519963d04f67592ed50d962f0cee255e9..8446b94c018c66bc75aa7fa9597bdb569f3bf8a4 100644 --- a/LoongArch64-support.patch +++ b/LoongArch64-support.patch @@ -18679,10 +18679,10 @@ index 0000000000..80dff0c762 + diff --git a/src/hotspot/cpu/loongarch/loongarch_64.ad b/src/hotspot/cpu/loongarch/loongarch_64.ad new file mode 100644 -index 0000000000..cc3824a402 +index 0000000000..c10f0b70cf --- /dev/null +++ b/src/hotspot/cpu/loongarch/loongarch_64.ad -@@ -0,0 +1,13917 @@ +@@ -0,0 +1,13928 @@ +// +// Copyright (c) 2003, 2013, Oracle and/or its affiliates. All rights reserved. +// Copyright (c) 2015, 2023, Loongson Technology. All rights reserved. @@ -25123,6 +25123,17 @@ index 0000000000..cc3824a402 + ins_pipe(empty); +%} + ++instruct same_addr_load_fence() %{ ++ match(SameAddrLoadFence); ++ ins_cost(400); ++ ++ format %{ "MEMBAR @ same_addr_load_fence" %} ++ ins_encode %{ ++ __ dbar(0x700); ++ %} ++ ins_pipe(pipe_slow); ++%} ++ +//----------Move Instructions-------------------------------------------------- +instruct castX2P(mRegP dst, mRegL src) %{ + match(Set dst (CastX2P src)); @@ -38046,13 +38057,13 @@ index 0000000000..49302590c3 +#endif // CPU_LOONGARCH_MACROASSEMBLER_LOONGARCH_INLINE_HPP diff --git a/src/hotspot/cpu/loongarch/macroAssembler_loongarch_trig.cpp b/src/hotspot/cpu/loongarch/macroAssembler_loongarch_trig.cpp new file mode 100644 -index 0000000000..3ed4c36651 +index 0000000000..6e27a69747 --- /dev/null +++ b/src/hotspot/cpu/loongarch/macroAssembler_loongarch_trig.cpp -@@ -0,0 +1,1625 @@ +@@ -0,0 +1,1626 @@ +/* Copyright (c) 2018, 2020, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 2018, Cavium. All rights reserved. (By BELLSOFT) -+ * Copyright (c) 2022, Loongson Technology. All rights reserved. ++ * Copyright (c) 2022, 2024, Loongson Technology. All rights reserved. + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. + * + * This code is free software; you can redistribute it and/or modify it @@ -38951,7 +38962,7 @@ index 0000000000..3ed4c36651 + b(Q_DONE); + bind(JX_IS_0); + if (UseLASX) { -+ xvfmul_d(v28, v18, v6); // f[0,1] * x[0] ++ xvfmul_d(v28, v18, v6); // f[0,3] * x[0] + fmul_d(v30, v19, v6); // f[4] * x[0] + } else { + vfmul_d(v28, v18, v6); // f[0,1] * x[0] @@ -39180,6 +39191,7 @@ index 0000000000..3ed4c36651 + st_w(tmp2, SCR2, 0); + addi_w(SCR1, SCR1, 24); + addi_w(jz, jz, 1); ++ alsl_d(SCR2, jz, iqBase, 2 - 1); + st_w(tmp3, SCR2, 0); // iq[jz] = (int) fw + b(Z_ZERO_CHECK_DONE); + bind(Z_IS_LESS_THAN_TWO24B); @@ -104792,7 +104804,7 @@ index 3687754e71..791e4ed43f 100644 void generate_c1_load_barrier_stub(LIR_Assembler* ce, ZLoadBarrierStubC1* stub) const; diff --git a/src/hotspot/os/linux/os_linux.cpp b/src/hotspot/os/linux/os_linux.cpp -index 0af357ea56..66a8006780 100644 +index 2842a11f92..4f58ec4be3 100644 --- a/src/hotspot/os/linux/os_linux.cpp +++ b/src/hotspot/os/linux/os_linux.cpp @@ -23,6 +23,12 @@ @@ -104808,7 +104820,7 @@ index 0af357ea56..66a8006780 100644 // no precompiled headers #include "jvm.h" #include "classfile/classLoader.hpp" -@@ -4068,6 +4074,8 @@ size_t os::Linux::find_large_page_size() { +@@ -4060,6 +4066,8 @@ size_t os::Linux::find_large_page_size() { IA64_ONLY(256 * M) PPC_ONLY(4 * M) S390_ONLY(1 * M) @@ -108482,6 +108494,31 @@ index 2b0fa83c1a..270e0bc180 100644 +const bool ZPlatformLoadBarrierTestResultInRegister = false; + #endif // OS_CPU_LINUX_X86_ZGLOBALS_LINUX_X86_HPP +diff --git a/src/hotspot/share/adlc/formssel.cpp b/src/hotspot/share/adlc/formssel.cpp +index f810fde767..90f733cdf9 100644 +--- a/src/hotspot/share/adlc/formssel.cpp ++++ b/src/hotspot/share/adlc/formssel.cpp +@@ -22,6 +22,12 @@ + * + */ + ++/* ++ * This file has been modified by Loongson Technology in 2023, These ++ * modifications are Copyright (c) 2023, Loongson Technology, and are made ++ * available on the same license terms set forth above. ++ */ ++ + // FORMS.CPP - Definitions for ADL Parser Forms Classes + #include "adlc.hpp" + +@@ -4109,6 +4115,7 @@ bool MatchRule::is_ideal_membar() const { + !strcmp(_opType,"MemBarVolatile") || + !strcmp(_opType,"MemBarCPUOrder") || + !strcmp(_opType,"MemBarStoreStore") || ++ !strcmp(_opType,"SameAddrLoadFence" ) || + !strcmp(_opType,"OnSpinWait"); + } + diff --git a/src/hotspot/share/asm/codeBuffer.cpp b/src/hotspot/share/asm/codeBuffer.cpp index 4912f88056..a420f7807b 100644 --- a/src/hotspot/share/asm/codeBuffer.cpp @@ -109872,6 +109909,46 @@ index 84815adea8..57e29f1295 100644 __ move(dirty, card_addr); __ branch_destination(L_already_dirty->label()); } else { +diff --git a/src/hotspot/share/gc/shared/c2/barrierSetC2.cpp b/src/hotspot/share/gc/shared/c2/barrierSetC2.cpp +index 5452756444..62adf9971e 100644 +--- a/src/hotspot/share/gc/shared/c2/barrierSetC2.cpp ++++ b/src/hotspot/share/gc/shared/c2/barrierSetC2.cpp +@@ -22,6 +22,12 @@ + * + */ + ++/* ++ * This file has been modified by Loongson Technology in 2023, These ++ * modifications are Copyright (c) 2023, Loongson Technology, and are made ++ * available on the same license terms set forth above. ++ */ ++ + #include "precompiled.hpp" + #include "gc/shared/c2/barrierSetC2.hpp" + #include "opto/arraycopynode.hpp" +@@ -197,6 +203,8 @@ public: + + bool is_volatile = (decorators & MO_SEQ_CST) != 0; + bool is_acquire = (decorators & MO_ACQUIRE) != 0; ++ bool is_relaxed = (decorators & MO_RELAXED) != 0; ++ bool is_unsafe = (decorators & C2_UNSAFE_ACCESS) != 0; + + // If reference is volatile, prevent following volatiles ops from + // floating up before the volatile access. +@@ -227,6 +235,13 @@ public: + assert(_leading_membar == NULL || support_IRIW_for_not_multiple_copy_atomic_cpu, "no leading membar expected"); + Node* mb = kit->insert_mem_bar(Op_MemBarAcquire, n); + mb->as_MemBar()->set_trailing_load(); ++ } else if (is_relaxed && is_unsafe) { ++#ifdef LOONGARCH64 ++ assert(kit != NULL, "unsupported at optimization time"); ++ Node* n = _access.raw_access(); ++ Node* mb = kit->insert_mem_bar(Op_SameAddrLoadFence, n); ++ mb->as_MemBar()->set_trailing_load(); ++#endif + } + } + } diff --git a/src/hotspot/share/gc/shenandoah/c1/shenandoahBarrierSetC1.cpp b/src/hotspot/share/gc/shenandoah/c1/shenandoahBarrierSetC1.cpp index f51d186484..506f0301fe 100644 --- a/src/hotspot/share/gc/shenandoah/c1/shenandoahBarrierSetC1.cpp @@ -110179,6 +110256,56 @@ index 6c631f5458..9865106720 100644 } // Note that the forwardee is not the same thing as the displaced_mark. +diff --git a/src/hotspot/share/opto/classes.hpp b/src/hotspot/share/opto/classes.hpp +index 7a9bd91117..b46e9bcf5b 100644 +--- a/src/hotspot/share/opto/classes.hpp ++++ b/src/hotspot/share/opto/classes.hpp +@@ -22,6 +22,12 @@ + * + */ + ++/* ++ * This file has been modified by Loongson Technology in 2023, These ++ * modifications are Copyright (c) 2023, Loongson Technology, and are made ++ * available on the same license terms set forth above. ++ */ ++ + #include "utilities/macros.hpp" + + // The giant table of Node classes. +@@ -217,6 +223,7 @@ macro(StoreFence) + macro(MemBarReleaseLock) + macro(MemBarVolatile) + macro(MemBarStoreStore) ++macro(SameAddrLoadFence) + macro(MergeMem) + macro(MinD) + macro(MinF) +diff --git a/src/hotspot/share/opto/compile.cpp b/src/hotspot/share/opto/compile.cpp +index da06b47400..510438d675 100644 +--- a/src/hotspot/share/opto/compile.cpp ++++ b/src/hotspot/share/opto/compile.cpp +@@ -22,6 +22,12 @@ + * + */ + ++/* ++ * This file has been modified by Loongson Technology in 2023, These ++ * modifications are Copyright (c) 2023, Loongson Technology, and are made ++ * available on the same license terms set forth above. ++ */ ++ + #include "precompiled.hpp" + #include "asm/macroAssembler.hpp" + #include "asm/macroAssembler.inline.hpp" +@@ -3448,6 +3454,7 @@ void Compile::final_graph_reshaping_impl( Node *n, Final_Reshape_Counts &frc) { + n->set_req(MemBarNode::Precedent, top()); + } + break; ++ case Op_SameAddrLoadFence: + case Op_MemBarAcquire: { + if (n->as_MemBar()->trailing_load() && n->req() > MemBarNode::Precedent) { + // At parse time, the trailing MemBarAcquire for a volatile load diff --git a/src/hotspot/share/opto/compile.hpp b/src/hotspot/share/opto/compile.hpp index 569fbc6d69..c1f1b82ffa 100644 --- a/src/hotspot/share/opto/compile.hpp @@ -110192,6 +110319,63 @@ index 569fbc6d69..c1f1b82ffa 100644 MAX_inst_size = 2048, #else MAX_inst_size = 1024, +diff --git a/src/hotspot/share/opto/memnode.cpp b/src/hotspot/share/opto/memnode.cpp +index e194386b56..d5e6dd71a7 100644 +--- a/src/hotspot/share/opto/memnode.cpp ++++ b/src/hotspot/share/opto/memnode.cpp +@@ -22,6 +22,12 @@ + * + */ + ++/* ++ * This file has been modified by Loongson Technology in 2023, These ++ * modifications are Copyright (c) 2023, Loongson Technology, and are made ++ * available on the same license terms set forth above. ++ */ ++ + #include "precompiled.hpp" + #include "classfile/systemDictionary.hpp" + #include "compiler/compileLog.hpp" +@@ -3190,6 +3196,7 @@ MemBarNode* MemBarNode::make(Compile* C, int opcode, int atp, Node* pn) { + case Op_MemBarReleaseLock: return new MemBarReleaseLockNode(C, atp, pn); + case Op_MemBarVolatile: return new MemBarVolatileNode(C, atp, pn); + case Op_MemBarCPUOrder: return new MemBarCPUOrderNode(C, atp, pn); ++ case Op_SameAddrLoadFence: return new SameAddrLoadFenceNode(C, atp, pn); + case Op_OnSpinWait: return new OnSpinWaitNode(C, atp, pn); + case Op_Initialize: return new InitializeNode(C, atp, pn); + case Op_MemBarStoreStore: return new MemBarStoreStoreNode(C, atp, pn); +diff --git a/src/hotspot/share/opto/memnode.hpp b/src/hotspot/share/opto/memnode.hpp +index e4676977e1..bf1efbf835 100644 +--- a/src/hotspot/share/opto/memnode.hpp ++++ b/src/hotspot/share/opto/memnode.hpp +@@ -22,6 +22,12 @@ + * + */ + ++/* ++ * This file has been modified by Loongson Technology in 2023, These ++ * modifications are Copyright (c) 2023, Loongson Technology, and are made ++ * available on the same license terms set forth above. ++ */ ++ + #ifndef SHARE_VM_OPTO_MEMNODE_HPP + #define SHARE_VM_OPTO_MEMNODE_HPP + +@@ -1293,6 +1299,14 @@ public: + virtual uint ideal_reg() const { return 0; } // not matched in the AD file + }; + ++// Used to prevent LoadLoad reorder for same address. ++class SameAddrLoadFenceNode: public MemBarNode { ++public: ++ SameAddrLoadFenceNode(Compile* C, int alias_idx, Node* precedent) ++ : MemBarNode(C, alias_idx, precedent) {} ++ virtual int Opcode() const; ++}; ++ + class OnSpinWaitNode: public MemBarNode { + public: + OnSpinWaitNode(Compile* C, int alias_idx, Node* precedent) diff --git a/src/hotspot/share/opto/output.cpp b/src/hotspot/share/opto/output.cpp index b6540e06a3..52d1fc9fb9 100644 --- a/src/hotspot/share/opto/output.cpp @@ -110338,7 +110522,7 @@ index ce23aafa8f..d3dfb74d5b 100644 assert(_owner != Self, "invariant"); assert(_Responsible != Self, "invariant"); diff --git a/src/hotspot/share/runtime/os.cpp b/src/hotspot/share/runtime/os.cpp -index e0f4a2af1f..09cc4b1ba5 100644 +index 1c540bb621..0e44240d40 100644 --- a/src/hotspot/share/runtime/os.cpp +++ b/src/hotspot/share/runtime/os.cpp @@ -22,6 +22,12 @@ @@ -110397,6 +110581,31 @@ index e086f794cd..f480195775 100644 static const double S1 = -1.66666666666666324348e-01, /* 0xBFC55555, 0x55555549 */ S2 = 8.33333333332248946124e-03, /* 0x3F811111, 0x1110F8A6 */ +diff --git a/src/hotspot/share/runtime/vmStructs.cpp b/src/hotspot/share/runtime/vmStructs.cpp +index adce6da6a3..db099a2985 100644 +--- a/src/hotspot/share/runtime/vmStructs.cpp ++++ b/src/hotspot/share/runtime/vmStructs.cpp +@@ -22,6 +22,12 @@ + * + */ + ++/* ++ * This file has been modified by Loongson Technology in 2023, These ++ * modifications are Copyright (c) 2023, Loongson Technology, and are made ++ * available on the same license terms set forth above. ++ */ ++ + #include "precompiled.hpp" + #include "ci/ciField.hpp" + #include "ci/ciInstance.hpp" +@@ -1642,6 +1648,7 @@ typedef PaddedEnd PaddedObjectMonitor; + declare_c2_type(StoreFenceNode, MemBarNode) \ + declare_c2_type(MemBarVolatileNode, MemBarNode) \ + declare_c2_type(MemBarCPUOrderNode, MemBarNode) \ ++ declare_c2_type(SameAddrLoadFenceNode, MemBarNode) \ + declare_c2_type(OnSpinWaitNode, MemBarNode) \ + declare_c2_type(InitializeNode, MemBarNode) \ + declare_c2_type(ThreadLocalNode, Node) \ diff --git a/src/hotspot/share/utilities/globalDefinitions.hpp b/src/hotspot/share/utilities/globalDefinitions.hpp index c758fc5743..a8c4638f6a 100644 --- a/src/hotspot/share/utilities/globalDefinitions.hpp @@ -110672,7 +110881,7 @@ index 8318e8e021..07064e76ee 100644 // This C bool type must be int for compatibility with Linux calls and // it would be a mistake to equivalence it to C++ bool on many platforms diff --git a/src/jdk.hotspot.agent/linux/native/libsaproc/ps_proc.c b/src/jdk.hotspot.agent/linux/native/libsaproc/ps_proc.c -index de5254d859..eefe55959c 100644 +index c22b5d1cb3..36d6343960 100644 --- a/src/jdk.hotspot.agent/linux/native/libsaproc/ps_proc.c +++ b/src/jdk.hotspot.agent/linux/native/libsaproc/ps_proc.c @@ -22,6 +22,12 @@ @@ -110688,12 +110897,12 @@ index de5254d859..eefe55959c 100644 #include #include #include -@@ -142,7 +148,7 @@ static bool process_get_lwp_regs(struct ps_prochandle* ph, pid_t pid, struct use - #define PTRACE_GETREGS_REQ PT_GETREGS - #endif - --#ifdef PTRACE_GETREGS_REQ -+#if defined(PTRACE_GETREGS_REQ) && !defined(loongarch64) +@@ -151,7 +157,7 @@ static bool process_get_lwp_regs(struct ps_prochandle* ph, pid_t pid, struct use + return false; + } + return true; +-#elif defined(PTRACE_GETREGS_REQ) ++#elif defined(PTRACE_GETREGS_REQ) && !defined(loongarch64) if (ptrace_getregs(PTRACE_GETREGS_REQ, pid, user, NULL) < 0) { print_debug("ptrace(PTRACE_GETREGS, ...) failed for lwp %d\n", pid); return false; @@ -116585,7 +116794,7 @@ index 127bb6abcd..c9277604ae 100644 Platform.isSolaris(); } diff --git a/test/hotspot/jtreg/testlibrary_tests/TestMutuallyExclusivePlatformPredicates.java b/test/hotspot/jtreg/testlibrary_tests/TestMutuallyExclusivePlatformPredicates.java -index 77458554b7..05aee6b84c 100644 +index 126a43a900..55bd135f6e 100644 --- a/test/hotspot/jtreg/testlibrary_tests/TestMutuallyExclusivePlatformPredicates.java +++ b/test/hotspot/jtreg/testlibrary_tests/TestMutuallyExclusivePlatformPredicates.java @@ -45,7 +45,7 @@ import java.util.Set; @@ -116625,35 +116834,8 @@ index 7990c49a1f..025048c6b0 100644 } } } -diff --git a/test/jdk/sun/security/pkcs11/PKCS11Test.java b/test/jdk/sun/security/pkcs11/PKCS11Test.java -index b14daf6c6d..da33514c75 100644 ---- a/test/jdk/sun/security/pkcs11/PKCS11Test.java -+++ b/test/jdk/sun/security/pkcs11/PKCS11Test.java -@@ -21,6 +21,12 @@ - * questions. - */ - -+/* -+ * This file has been modified by Loongson Technology in 2022, These -+ * modifications are Copyright (c) 2021, 2022, Loongson Technology, and are made -+ * available on the same license terms set forth above. -+ */ -+ - // common infrastructure for SunPKCS11 tests - - import java.io.BufferedReader; -@@ -747,6 +753,9 @@ public abstract class PKCS11Test { - "/usr/lib64/" }); - osMap.put("Linux-ppc64-64", new String[] { "/usr/lib64/" }); - osMap.put("Linux-ppc64le-64", new String[] { "/usr/lib64/" }); -+ osMap.put("Linux-mips64el-64", new String[]{"/usr/lib64/"}); -+ osMap.put("Linux-loongarch64-64", new String[]{"/usr/lib/loongarch64-linux-gnu/", -+ "/usr/lib64/" }); - osMap.put("Linux-s390x-64", new String[] { "/usr/lib64/" }); - osMap.put("Windows-x86-32", new String[] {}); - osMap.put("Windows-amd64-64", new String[] {}); diff --git a/test/lib/jdk/test/lib/Platform.java b/test/lib/jdk/test/lib/Platform.java -index 5b3f1889cb..aaf8867a7c 100644 +index 6269373c2b..440ec4664f 100644 --- a/test/lib/jdk/test/lib/Platform.java +++ b/test/lib/jdk/test/lib/Platform.java @@ -21,6 +21,12 @@ @@ -116668,8 +116850,8 @@ index 5b3f1889cb..aaf8867a7c 100644 + package jdk.test.lib; - import java.io.FileNotFoundException; -@@ -226,6 +232,14 @@ public class Platform { + import java.io.BufferedReader; +@@ -229,6 +235,14 @@ public class Platform { return isArch("(i386)|(x86(?!_64))"); } diff --git a/change-ActivePrcoessorCount-only-for-HBase.patch b/change-ActivePrcoessorCount-only-for-HBase.patch new file mode 100644 index 0000000000000000000000000000000000000000..3d604e544365aea7793dd6e3212c8369c4c269ff --- /dev/null +++ b/change-ActivePrcoessorCount-only-for-HBase.patch @@ -0,0 +1,232 @@ +diff --git a/src/hotspot/cpu/aarch64/vm_version_aarch64.hpp b/src/hotspot/cpu/aarch64/vm_version_aarch64.hpp +index faf109ab1..ab83d2a6b 100644 +--- a/src/hotspot/cpu/aarch64/vm_version_aarch64.hpp ++++ b/src/hotspot/cpu/aarch64/vm_version_aarch64.hpp +@@ -121,7 +121,8 @@ public: + static int get_initial_sve_vector_length() { return _initial_sve_vector_length; }; + + static bool is_hisi_enabled() { +- if (_cpu == CPU_HISILICON && (_model == 0xd01 || _model == 0xd02 || _model == 0xd03)) { ++ if (_cpu == CPU_HISILICON && (_model == 0xd01 || _model == 0xd02 || _model == 0xd03 || ++ _model == 0xd22 || _model == 0xd45)) { + return true; + } + return false; +diff --git a/make/hotspot/symbols/symbols-shared b/make/hotspot/symbols/symbols-shared +index 5d26d1028..d955c25f2 100644 +--- a/make/hotspot/symbols/symbols-shared ++++ b/make/hotspot/symbols/symbols-shared +@@ -28,6 +28,7 @@ jio_snprintf + jio_vfprintf + jio_vsnprintf + JNI_CreateJavaVM ++JNI_SetCParam + JNI_GetCreatedJavaVMs + JNI_GetDefaultJavaVMInitArgs + JVM_FindClassFromBootLoader +diff --git a/src/hotspot/cpu/aarch64/vm_version_aarch64.cpp b/src/hotspot/cpu/aarch64/vm_version_aarch64.cpp +index 9c2bdbbad..552267b0f 100644 +--- a/src/hotspot/cpu/aarch64/vm_version_aarch64.cpp ++++ b/src/hotspot/cpu/aarch64/vm_version_aarch64.cpp +@@ -413,3 +413,28 @@ void VM_Version::initialize() { + + UNSUPPORTED_OPTION(CriticalJNINatives); + } ++ ++int VM_Version::get_cpu_model() { ++ int cpu_lines = 0; ++ if (FILE *f = fopen("/proc/cpuinfo", "r")) { ++ char buf[128], *p; ++ while (fgets(buf, sizeof (buf), f) != NULL) { ++ if ((p = strchr(buf, ':')) != NULL) { ++ long v = strtol(p+1, NULL, 0); ++ if (strncmp(buf, "CPU implementer", sizeof "CPU implementer" - 1) == 0) { ++ _cpu = v; ++ cpu_lines++; ++ } else if (strncmp(buf, "CPU variant", sizeof "CPU variant" - 1) == 0) { ++ _variant = v; ++ } else if (strncmp(buf, "CPU part", sizeof "CPU part" - 1) == 0) { ++ if (_model != v) _model2 = _model; ++ _model = v; ++ } else if (strncmp(buf, "CPU revision", sizeof "CPU revision" - 1) == 0) { ++ _revision = v; ++ } ++ } ++ } ++ fclose(f); ++ } ++ return cpu_lines; ++} +\ No newline at end of file +diff --git a/src/hotspot/cpu/aarch64/vm_version_aarch64.hpp b/src/hotspot/cpu/aarch64/vm_version_aarch64.hpp +index f03da8710..faf109ab1 100644 +--- a/src/hotspot/cpu/aarch64/vm_version_aarch64.hpp ++++ b/src/hotspot/cpu/aarch64/vm_version_aarch64.hpp +@@ -112,6 +112,7 @@ public: + CPU_DMB_ATOMICS = (1 << 31), + }; + ++ static int get_cpu_model(); + static int cpu_family() { return _cpu; } + static int cpu_model() { return _model; } + static int cpu_model2() { return _model2; } +diff --git a/src/hotspot/os_cpu/linux_aarch64/thread_linux_aarch64.cpp b/src/hotspot/os_cpu/linux_aarch64/thread_linux_aarch64.cpp +index 9084daeaa..0d7e03cd8 100644 +--- a/src/hotspot/os_cpu/linux_aarch64/thread_linux_aarch64.cpp ++++ b/src/hotspot/os_cpu/linux_aarch64/thread_linux_aarch64.cpp +@@ -46,6 +46,35 @@ bool JavaThread::pd_get_top_frame_for_profiling(frame* fr_addr, void* ucontext, + return pd_get_top_frame(fr_addr, ucontext, isInJava); + } + ++inline unsigned int stringHash(const char* str) { ++ unsigned int seed = 13; ++ unsigned int hash = 0; ++ while(*str) { ++ hash = hash * seed + (*str++); ++ } ++ ++ return (hash & 0x7fffffff); ++} ++ ++void JavaThread::os_linux_aarch64_options(int apc, char **name) { ++ if (name == NULL) { ++ return; ++ } ++ VM_Version::get_cpu_model(); ++ if (VM_Version::is_hisi_enabled()) { ++ int i = 0; ++ int step = 0; ++ while (name[i] != NULL) { ++ if (stringHash(name[i]) == 1396789436) { ++ if (FLAG_IS_DEFAULT(ActiveProcessorCount) && (UseG1GC || UseParallelGC || UseZGC) && apc > 8) ++ FLAG_SET_DEFAULT(ActiveProcessorCount, 8); ++ break; ++ } ++ i++; ++ } ++ } ++} ++ + bool JavaThread::pd_get_top_frame(frame* fr_addr, void* ucontext, bool isInJava) { + assert(this->is_Java_thread(), "must be JavaThread"); + JavaThread* jt = (JavaThread *)this; +diff --git a/src/hotspot/os_cpu/linux_aarch64/thread_linux_aarch64.hpp b/src/hotspot/os_cpu/linux_aarch64/thread_linux_aarch64.hpp +index 985b664aa..521ac0dcc 100644 +--- a/src/hotspot/os_cpu/linux_aarch64/thread_linux_aarch64.hpp ++++ b/src/hotspot/os_cpu/linux_aarch64/thread_linux_aarch64.hpp +@@ -55,6 +55,8 @@ + bool pd_get_top_frame_for_signal_handler(frame* fr_addr, void* ucontext, + bool isInJava); + ++ static void os_linux_aarch64_options(int apc, char **name); ++ + bool pd_get_top_frame_for_profiling(frame* fr_addr, void* ucontext, bool isInJava); + private: + bool pd_get_top_frame(frame* fr_addr, void* ucontext, bool isInJava); +diff --git a/src/hotspot/share/prims/jni.cpp b/src/hotspot/share/prims/jni.cpp +index 289283dca..0b2138d98 100644 +--- a/src/hotspot/share/prims/jni.cpp ++++ b/src/hotspot/share/prims/jni.cpp +@@ -3951,6 +3951,11 @@ _JNI_IMPORT_OR_EXPORT_ jint JNICALL JNI_GetDefaultJavaVMInitArgs(void *args_) { + DT_RETURN_MARK_DECL(CreateJavaVM, jint + , HOTSPOT_JNI_CREATEJAVAVM_RETURN(_ret_ref)); + ++const char** argv_for_execvp; ++_JNI_IMPORT_OR_EXPORT_ void JNICALL JNI_SetCParam(char** raw_argv) { ++ argv_for_execvp = (const char**)raw_argv; ++} ++ + static jint JNI_CreateJavaVM_inner(JavaVM **vm, void **penv, void *args) { + HOTSPOT_JNI_CREATEJAVAVM_ENTRY((void **) vm, penv, args); + +diff --git a/src/hotspot/share/runtime/os.cpp b/src/hotspot/share/runtime/os.cpp +index 1c540bb62..214bb21f9 100644 +--- a/src/hotspot/share/runtime/os.cpp ++++ b/src/hotspot/share/runtime/os.cpp +@@ -447,6 +447,11 @@ static void signal_thread_entry(JavaThread* thread, TRAPS) { + } + + void os::init_before_ergo() { ++#ifdef AARCH64 ++ // global variables ++ extern char** argv_for_execvp; ++ JavaThread::os_linux_aarch64_options(active_processor_count(), argv_for_execvp); ++#endif + initialize_initial_active_processor_count(); + // We need to initialize large page support here because ergonomics takes some + // decisions depending on large page support and the calculated large page size. +diff --git a/src/java.base/share/native/include/jni.h b/src/java.base/share/native/include/jni.h +index e15503f4d..4aaa75685 100644 +--- a/src/java.base/share/native/include/jni.h ++++ b/src/java.base/share/native/include/jni.h +@@ -1948,6 +1948,9 @@ JNI_GetDefaultJavaVMInitArgs(void *args); + _JNI_IMPORT_OR_EXPORT_ jint JNICALL + JNI_CreateJavaVM(JavaVM **pvm, void **penv, void *args); + ++_JNI_IMPORT_OR_EXPORT_ void JNICALL ++JNI_SetCParam(char** raw_argv); ++ + _JNI_IMPORT_OR_EXPORT_ jint JNICALL + JNI_GetCreatedJavaVMs(JavaVM **, jsize, jsize *); + +diff --git a/src/java.base/share/native/libjli/java.c b/src/java.base/share/native/libjli/java.c +index a38ddae63..120d8f33b 100644 +--- a/src/java.base/share/native/libjli/java.c ++++ b/src/java.base/share/native/libjli/java.c +@@ -284,6 +284,7 @@ JLI_Launch(int argc, char ** argv, /* main argc, argv */ + + ifn.CreateJavaVM = 0; + ifn.GetDefaultJavaVMInitArgs = 0; ++ ifn.raw_argv = argv; + + if (JLI_IsTraceLauncher()) { + start = CounterGet(); +@@ -1524,6 +1525,7 @@ InitializeJVM(JavaVM **pvm, JNIEnv **penv, InvocationFunctions *ifn) + i, args.options[i].optionString); + } + ++ ifn->SetCParam(ifn->raw_argv); + r = ifn->CreateJavaVM(pvm, (void **)penv, &args); + JLI_MemFree(options); + return r == JNI_OK; +diff --git a/src/java.base/share/native/libjli/java.h b/src/java.base/share/native/libjli/java.h +index 45acece27..43ca5cf39 100644 +--- a/src/java.base/share/native/libjli/java.h ++++ b/src/java.base/share/native/libjli/java.h +@@ -77,13 +77,16 @@ + * Pointers to the needed JNI invocation API, initialized by LoadJavaVM. + */ + typedef jint (JNICALL *CreateJavaVM_t)(JavaVM **pvm, void **env, void *args); ++typedef void (JNICALL *SetCParam_t)(char** raw_argv); + typedef jint (JNICALL *GetDefaultJavaVMInitArgs_t)(void *args); + typedef jint (JNICALL *GetCreatedJavaVMs_t)(JavaVM **vmBuf, jsize bufLen, jsize *nVMs); + + typedef struct { + CreateJavaVM_t CreateJavaVM; ++ SetCParam_t SetCParam; + GetDefaultJavaVMInitArgs_t GetDefaultJavaVMInitArgs; + GetCreatedJavaVMs_t GetCreatedJavaVMs; ++ char** raw_argv; + } InvocationFunctions; + + JNIEXPORT int JNICALL +diff --git a/src/java.base/unix/native/libjli/java_md_solinux.c b/src/java.base/unix/native/libjli/java_md_solinux.c +index 160f91975..7526c0d9f 100644 +--- a/src/java.base/unix/native/libjli/java_md_solinux.c ++++ b/src/java.base/unix/native/libjli/java_md_solinux.c +@@ -615,6 +615,13 @@ LoadJavaVM(const char *jvmpath, InvocationFunctions *ifn) + return JNI_FALSE; + } + ++ ifn->SetCParam = (SetCParam_t) ++ dlsym(libjvm, "JNI_SetCParam"); ++ if (ifn->SetCParam == NULL) { ++ JLI_ReportErrorMessage(DLL_ERROR2, jvmpath, dlerror()); ++ return JNI_FALSE; ++ } ++ + ifn->GetDefaultJavaVMInitArgs = (GetDefaultJavaVMInitArgs_t) + dlsym(libjvm, "JNI_GetDefaultJavaVMInitArgs"); + if (ifn->GetDefaultJavaVMInitArgs == NULL) { +-- +2.21.0.windows.1 diff --git a/delete_expired_certificates.patch b/delete_expired_certificates.patch index 3e654b7774f145bca6cee0a764b16d15dd779cde..19a0e1562473a34aaec8579fb4f75bd14d52c163 100644 --- a/delete_expired_certificates.patch +++ b/delete_expired_certificates.patch @@ -120,19 +120,18 @@ index 122a01901..c131bd493 100644 + File.separator + "security" + File.separator + "cacerts"; // The numbers of certs now. -- private static final int COUNT = 110; -+ private static final int COUNT = 107; +- private static final int COUNT = 112; ++ private static final int COUNT = 109; // SHA-256 of cacerts, can be generated with // shasum -a 256 cacerts | sed -e 's/../&:/g' | tr '[:lower:]' '[:upper:]' | cut -c1-95 private static final String CHECKSUM -- = "C1:68:B4:AC:51:BF:B5:C6:FD:20:69:17:E1:AF:E4:5B:01:9B:AA:3F:C3:9A:80:A8:51:53:74:2C:A2:04:B0:FF"; -+ = "D5:F6:74:0F:13:CF:6D:35:5E:10:04:C3:1B:57:C4:F4:A0:49:9A:26:38:89:53:C3:71:10:60:9D:48:20:E7:DE"; +- = "8F:E0:6F:7F:21:59:33:A6:43:F3:48:FD:A3:4A:8E:28:35:AA:DD:6E:A5:43:56:F1:28:34:48:DF:5C:D2:7C:72"; ++ = "20:83:CF:5E:F7:A9:E6:C6:06:ED:2C:28:3E:CE:AF:B9:BF:9D:26:CB:29:0C:E2:CF:B8:4F:DF:E9:59:5F:A6:3C"; // map of cert alias to SHA-256 fingerprint @SuppressWarnings("serial") - private static final Map FINGERPRINT_MAP = new HashMap<>() { -@@ -109,8 +109,6 @@ public class VerifyCACerts { +@@ -110,8 +110,6 @@ public class VerifyCACerts { "7E:37:CB:8B:4C:47:09:0C:AB:36:55:1B:A6:F4:5D:B8:40:68:0F:BA:16:6A:95:2D:B1:00:71:7F:43:05:3F:C2"); put("digicerthighassuranceevrootca [jdk]", "74:31:E5:F4:C3:C1:CE:46:90:77:4F:0B:61:E0:54:40:88:3B:A9:A0:1E:D0:0B:A6:AB:D7:80:6E:D3:B1:18:CF"); @@ -141,7 +140,7 @@ index 122a01901..c131bd493 100644 put("geotrustprimaryca [jdk]", "37:D5:10:06:C5:12:EA:AB:62:64:21:F1:EC:8C:92:01:3F:C5:F8:2A:E9:8E:E5:33:EB:46:19:B8:DE:B4:D0:6C"); put("geotrustprimarycag2 [jdk]", -@@ -145,10 +143,6 @@ public class VerifyCACerts { +@@ -146,10 +144,6 @@ public class VerifyCACerts { "96:BC:EC:06:26:49:76:F3:74:60:77:9A:CF:28:C5:A7:CF:E8:A3:C0:AA:E1:1A:8F:FC:EE:05:C0:BD:DF:08:C6"); put("letsencryptisrgx2 [jdk]", "69:72:9B:8E:15:A8:6E:FC:17:7A:57:AF:B7:17:1D:FC:64:AD:D2:8C:2F:CA:8C:F1:50:7E:34:45:3C:CB:14:70"); @@ -152,7 +151,7 @@ index 122a01901..c131bd493 100644 put("quovadisrootca1g3 [jdk]", "8A:86:6F:D1:B2:76:B5:7E:57:8E:92:1C:65:82:8A:2B:ED:58:E9:F2:F2:88:05:41:34:B7:F1:F4:BF:C9:CC:74"); put("quovadisrootca2 [jdk]", -@@ -282,12 +276,6 @@ public class VerifyCACerts { +@@ -291,12 +285,6 @@ public class VerifyCACerts { add("addtrustexternalca [jdk]"); // Valid until: Sat May 30 10:44:50 GMT 2020 add("addtrustqualifiedca [jdk]"); diff --git a/jdk-updates-jdk11u-jdk-11.0.23-ga.tar.xz b/jdk-updates-jdk11u-jdk-11.0.23-ga.tar.xz deleted file mode 100644 index 921bdb22895680fb23af8e04daff21e532027915..0000000000000000000000000000000000000000 Binary files a/jdk-updates-jdk11u-jdk-11.0.23-ga.tar.xz and /dev/null differ diff --git a/jdk-updates-jdk11u-jdk-11.0.24-ga.tar.xz b/jdk-updates-jdk11u-jdk-11.0.25-ga.tar.xz similarity index 82% rename from jdk-updates-jdk11u-jdk-11.0.24-ga.tar.xz rename to jdk-updates-jdk11u-jdk-11.0.25-ga.tar.xz index c3b680936f71b4b5745b63aeccf1de5513b3e85a..0a86b9fd29777e296b596675ea94439254bc3b22 100644 Binary files a/jdk-updates-jdk11u-jdk-11.0.24-ga.tar.xz and b/jdk-updates-jdk11u-jdk-11.0.25-ga.tar.xz differ diff --git a/openjdk-11.spec b/openjdk-11.spec index 32b9df0f5a013c3dfc5ced3a00a154aa64dffdc1..4bbba2155c9e050f61b48a1f0f0c1ff7a7553748 100644 --- a/openjdk-11.spec +++ b/openjdk-11.spec @@ -22,6 +22,9 @@ # Enable release builds by default on relevant arches. %bcond_without release +# Disable global LTO +%define _lto_cflags %{nil} + # The -g flag says to use strip -g instead of full strip on DSOs or EXEs. # This fixes detailed NMT and other tools which need minimal debug info. # See: https://bugzilla.redhat.com/show_bug.cgi?id=1520879 @@ -125,14 +128,14 @@ # New Version-String scheme-style defines %global majorver 11 -%global securityver 24 +%global securityver 25 # buildjdkver is usually same as %%{majorver}, # but in time of bootstrap of next jdk, it is majorver-1, # and this it is better to change it here, on single place %global buildjdkver %{majorver} %ifnarch loongarch64 ppc64le -%global vendor_version_string Bisheng +%global vendor_version_string BiSheng %endif %ifarch loongarch64 %global vendor_version_string Loongson @@ -146,12 +149,12 @@ %global origin_nice OpenJDK %global top_level_dir_name %{origin} %global minorver 0 -%global buildver 8 +%global buildver 9 %global patchver 0 %global project jdk-updates %global repo jdk11u -%global revision jdk-11.0.24-ga +%global revision jdk-11.0.25-ga %global full_revision %{project}-%{repo}-%{revision} # priority must be 7 digits in total # setting to 1, so debug ones can have 0 @@ -695,6 +698,9 @@ Provides: java-%{origin}-headless%{?1} = %{epoch}:%{version}-%{release} Provides: jre-%{origin}-headless%{?1} = %{epoch}:%{version}-%{release} Provides: java-headless%{?1} = %{epoch}:%{version}-%{release} Provides: jre-headless%{?1} = %{epoch}:%{version}-%{release} + +# To fix /usr/bin/jjs not provided +Provides: /usr/bin/jjs } %define java_devel_rpo() %{expand: @@ -762,7 +768,7 @@ Provides: java-src%{?1} = %{epoch}:%{version}-%{release} Name: java-%{javaver}-%{origin} Version: %{newjavaver}.%{buildver} -Release: 1 +Release: 3 # java-1.5.0-ibm from jpackage.org set Epoch to 1 for unknown reasons # and this change was brought into RHEL-4. java-1.5.0-ibm packages # also included the epoch in their virtual provides. This created a @@ -791,7 +797,7 @@ Group: Development/Languages # The test code includes copies of NSS under the Mozilla Public License v2.0 # The PCSClite headers are under a BSD with advertising license # The elliptic curve cryptography (ECC) source code is licensed under the LGPLv2.1 or any later version -License: ASL 1.1 and ASL 2.0 and BSD and BSD with advertising and GPL+ and GPLv2 and GPLv2 with exceptions and IJG and LGPLv2+ and MIT and MPLv2.0 and Public Domain and W3C and zlib and ISC and FTL and RSA +License: ASL 1.1 and ASL 2.0 and BSD and BSD with advertising and GPL+ and GPLv2 and GPLv2 with exceptions and IJG and LGPLv2+ and MIT and MPLv2.0 and Public Domain and W3C and zlib and ISC and FTL and RSA-MD URL: http://openjdk.java.net/ @@ -808,15 +814,6 @@ Source9: jconsole.desktop.in # nss configuration file Source11: nss.cfg.in -############################################ -# -# RPM/distribution specific patches -# -############################################ -# NSS via SunPKCS11 Provider (disabled comment -# due to memory leak). -Patch1000: rh1648249-add_commented_out_nss_cfg_provider_to_java_security.patch - ############################################ # # LoongArch64 specific patches @@ -902,6 +899,9 @@ Patch92: 8295068-SSLEngine-throws-NPE-parsing-Certificate.patch # 11.0.23 Patch93: Cache-byte-when-constructing-String-with-duplicate-c.patch + +# 11.0.25 +Patch94: change-ActivePrcoessorCount-only-for-HBase.patch ############################################ # # riscv64 specific patches @@ -1194,6 +1194,7 @@ pushd %{top_level_dir_name} %patch91 -p1 %patch92 -p1 %patch93 -p1 +%patch94 -p1 %endif %endif %ifarch loongarch64 @@ -1201,8 +1202,6 @@ pushd %{top_level_dir_name} %endif popd # openjdk -# %patch1000 - # Extract systemtap tapsets %if %{with_systemtap} tar --strip-components=1 -x -I xz -f %{SOURCE8} @@ -1291,7 +1290,7 @@ bash ../configure \ --with-version-opt="" \ --with-vendor-version-string="%{vendor_version_string}" \ %ifnarch loongarch64 ppc64le - --with-vendor-name="Bisheng" \ + --with-vendor-name="BiSheng" \ %endif %ifarch loongarch64 --with-vendor-name="Loongson" \ @@ -1588,9 +1587,10 @@ else end end -- run content of included file with fake args +arg = nil; -- it is better to null the arg up, no meter if they exists or not, and use cjc as module in unified way, instead of relaying on "main" method during require "copy_jdk_configs.lua" cjc = require "copy_jdk_configs.lua" -arg = {"--currentjvm", "%{uniquesuffix %{nil}}", "--jvmdir", "%{_jvmdir %{nil}}", "--origname", "%{name}", "--origjavaver", "%{javaver}", "--arch", "%{_arch}", "--temp", "%{rpm_state_dir}/%{name}.%{_arch}"} -cjc.mainProgram(arg) +args = {"--currentjvm", "%{uniquesuffix %{nil}}", "--jvmdir", "%{_jvmdir %{nil}}", "--origname", "%{name}", "--origjavaver", "%{javaver}", "--arch", "%{_arch}", "--temp", "%{rpm_state_dir}/%{name}.%{_arch}"} +cjc.mainProgram(args) -- the returns from copy_jdk_configs.lua should not affect this 'main', so it should run under all circumstances, except fatal error %post %{post_script %{nil}} @@ -1715,10 +1715,40 @@ cjc.mainProgram(arg) %changelog -* Thu July 18 2024 Dingli Zhang - 1.11.0.24.8-1 +* Wed Nov 6 2024 Pan Xuefeng - 1:11.0.25.9-3 +- update LoongArch64 port to 11.0.25 + +* Wed Oct 23 2024 Dingli Zhang - 1:11.0.25.9-2 +- update riscv64 port to 11.0.25 + +* Mon Oct 21 2024 wuyafang - 1:11.0.25.9-1 +- disable lto in spec +- add Provides: /usr/bin/jjs +- update license + +* Wed Oct 16 2024 wuyafang - 1:11.0.25.9-0 +- upgrade to 11.0.25+9(GA) +- change default ActiveProcessorCount only for HBase + +* Fri Aug 30 2024 songliyang - 1.11.0.24.8-6 +- update License + +* Thu Aug 1 2024 aoqi - 1.11.0.24.8-5 +- update LoongArch64 port to 11.0.24 + +* Thu Jul 29 2024 DXwangg - 1.11.0.24.8-4 +- modified delete_expired_certificates.patch + +* Thu Jul 25 2024 songliyang - 1.11.0.24.8-3 +- update Loongarch support patch to fix the error while applying in prep stage + +* Tue Jul 23 2024 songliyang - 1.11.0.24.8-2 +- null the arg to solve openjdk-headless install error + +* Thu Jul 18 2024 Dingli Zhang - 1.11.0.24.8-1 - update riscv64 port to 11.0.24 -* Thu July 18 2024 DXwangg - 1.11.0.24.8-0 +* Thu Jul 18 2024 DXwangg - 1.11.0.24.8-0 - update to 11.0.24+8(GA) * Thu Jun 20 2024 aoqi - 1.11.0.23.9-6 @@ -1742,7 +1772,7 @@ cjc.mainProgram(arg) * Thu Apr 18 2024 huangjie - 1:11.0.23.9-0 - modified 8224675-Late-GC-barrier-insertion-for-ZGC.patch -- modified delete_expired_certificates.patch +- modified delete_expired_certificates.patch * Wed Mar 13 2024 jiahua.yu - 1:11.0.22.7-3 - init support for arch ppc64le @@ -1764,7 +1794,7 @@ cjc.mainProgram(arg) * Thu Oct 19 2023 DXwangg - 1:11.0.21.9-0 - update to 11.0.21+9(GA) - modified delete_expired_certificates.patch -- modified G1-iterate-region-by-bitmap-rather-than-obj-size-in.patch +- modified G1-iterate-region-by-bitmap-rather-than-obj-size-in.patch - modified 8210473-JEP-345-NUMA-Aware-Memory-Allocation-for-G1.patch - modified 8214527-AArch64-ZGC-for-Aarch64.patch diff --git a/rh1648249-add_commented_out_nss_cfg_provider_to_java_security.patch b/rh1648249-add_commented_out_nss_cfg_provider_to_java_security.patch deleted file mode 100644 index 1b92ddcb1154713c534b003a1d9b1d6985c5e549..0000000000000000000000000000000000000000 --- a/rh1648249-add_commented_out_nss_cfg_provider_to_java_security.patch +++ /dev/null @@ -1,11 +0,0 @@ -diff -r 5b86f66575b7 src/share/lib/security/java.security-linux ---- openjdk/src/java.base/share/conf/security/java.security Tue May 16 13:29:05 2017 -0700 -+++ openjdk/src/java.base/share/conf/security/java.security Tue Jun 06 14:05:12 2017 +0200 -@@ -83,6 +83,7 @@ - #ifndef solaris - security.provider.tbd=SunPKCS11 - #endif -+#security.provider.tbd=SunPKCS11 ${java.home}/lib/security/nss.cfg - - # - # A list of preferred providers for specific algorithms. These providers will