diff --git a/LoongArch64-support.patch b/LoongArch64-support.patch index 09663e8ec14f3fb60bbfe3d45e5c72acb4faa557..7045115e0d6f1fe31f75d91579231910382c0377 100644 --- a/LoongArch64-support.patch +++ b/LoongArch64-support.patch @@ -1,7 +1,6 @@ -diff --git a/make/autoconf/jvm-features.m4 b/make/autoconf/jvm-features.m4 -index 906a2857877..20d35c2a9e2 100644 ---- a/make/autoconf/jvm-features.m4 -+++ b/make/autoconf/jvm-features.m4 +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/make/autoconf/jvm-features.m4 b/make/autoconf/jvm-features.m4 +--- a/make/autoconf/jvm-features.m4 2024-01-10 05:18:15.000000000 +0800 ++++ b/make/autoconf/jvm-features.m4 2024-01-31 14:01:10.934089173 +0800 @@ -23,6 +23,12 @@ # questions. # @@ -15,11 +14,10 @@ index 906a2857877..20d35c2a9e2 100644 ############################################################################### # Terminology used in this file: # -@@ -242,6 +248,23 @@ AC_DEFUN_ONCE([JVM_FEATURES_CHECK_CDS], - ]) +@@ -243,6 +249,23 @@ ]) -+############################################################################### + ############################################################################### +# Check if the feature 'compiler1' is available on this platform. +# +AC_DEFUN_ONCE([JVM_FEATURES_CHECK_COMPILER1], @@ -36,10 +34,11 @@ index 906a2857877..20d35c2a9e2 100644 + ]) +]) + - ############################################################################### ++############################################################################### # Check if the feature 'dtrace' is available on this platform. # -@@ -292,6 +315,8 @@ AC_DEFUN_ONCE([JVM_FEATURES_CHECK_JVMCI], + AC_DEFUN_ONCE([JVM_FEATURES_CHECK_DTRACE], +@@ -295,6 +318,8 @@ AC_MSG_RESULT([yes]) elif test "x$OPENJDK_TARGET_CPU" = "xaarch64"; then AC_MSG_RESULT([yes]) @@ -48,17 +47,17 @@ index 906a2857877..20d35c2a9e2 100644 else AC_MSG_RESULT([no, $OPENJDK_TARGET_CPU]) AVAILABLE=false -@@ -308,7 +333,8 @@ AC_DEFUN_ONCE([JVM_FEATURES_CHECK_SHENANDOAHGC], - AC_MSG_CHECKING([if platform is supported by Shenandoah]) +@@ -312,7 +337,8 @@ if test "x$OPENJDK_TARGET_CPU_ARCH" = "xx86" || \ test "x$OPENJDK_TARGET_CPU" = "xaarch64" || \ -- test "x$OPENJDK_TARGET_CPU" = "xppc64le"; then -+ test "x$OPENJDK_TARGET_CPU" = "xppc64le" || \ + test "x$OPENJDK_TARGET_CPU" = "xppc64le" || \ +- test "x$OPENJDK_TARGET_CPU" = "xriscv64"; then ++ test "x$OPENJDK_TARGET_CPU" = "xriscv64" || \ + test "x$OPENJDK_TARGET_CPU" = "xloongarch64"; then AC_MSG_RESULT([yes]) else AC_MSG_RESULT([no, $OPENJDK_TARGET_CPU]) -@@ -365,6 +391,13 @@ AC_DEFUN_ONCE([JVM_FEATURES_CHECK_ZGC], +@@ -370,6 +396,13 @@ AC_MSG_RESULT([no, $OPENJDK_TARGET_OS-$OPENJDK_TARGET_CPU]) AVAILABLE=false fi @@ -72,7 +71,7 @@ index 906a2857877..20d35c2a9e2 100644 else AC_MSG_RESULT([no, $OPENJDK_TARGET_OS-$OPENJDK_TARGET_CPU]) AVAILABLE=false -@@ -399,6 +432,7 @@ AC_DEFUN_ONCE([JVM_FEATURES_PREPARE_PLATFORM], +@@ -404,6 +437,7 @@ # JVM_FEATURES_PLATFORM_UNAVAILABLE. JVM_FEATURES_CHECK_CDS @@ -80,10 +79,9 @@ index 906a2857877..20d35c2a9e2 100644 JVM_FEATURES_CHECK_DTRACE JVM_FEATURES_CHECK_JFR JVM_FEATURES_CHECK_JVMCI -diff --git a/make/autoconf/platform.m4 b/make/autoconf/platform.m4 -index 9e9e9454f0e..9058b736007 100644 ---- a/make/autoconf/platform.m4 -+++ b/make/autoconf/platform.m4 +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/make/autoconf/platform.m4 b/make/autoconf/platform.m4 +--- a/make/autoconf/platform.m4 2024-01-10 05:18:15.000000000 +0800 ++++ b/make/autoconf/platform.m4 2024-01-31 14:01:10.934089173 +0800 @@ -23,6 +23,12 @@ # questions. # @@ -97,7 +95,7 @@ index 9e9e9454f0e..9058b736007 100644 # Support macro for PLATFORM_EXTRACT_TARGET_AND_BUILD. # Converts autoconf style CPU name to OpenJDK style, into # VAR_CPU, VAR_CPU_ARCH, VAR_CPU_BITS and VAR_CPU_ENDIAN. -@@ -539,11 +545,26 @@ AC_DEFUN([PLATFORM_SETUP_LEGACY_VARS_HELPER], +@@ -539,11 +545,26 @@ HOTSPOT_$1_CPU=ppc_64 elif test "x$OPENJDK_$1_CPU" = xppc64le; then HOTSPOT_$1_CPU=ppc_64 @@ -124,10 +122,10 @@ index 9e9e9454f0e..9058b736007 100644 AC_SUBST(HOTSPOT_$1_CPU_ARCH) # Setup HOTSPOT_$1_CPU_DEFINE -@@ -561,6 +582,12 @@ AC_DEFUN([PLATFORM_SETUP_LEGACY_VARS_HELPER], - HOTSPOT_$1_CPU_DEFINE=PPC64 - elif test "x$OPENJDK_$1_CPU" = xppc64le; then +@@ -563,6 +584,12 @@ HOTSPOT_$1_CPU_DEFINE=PPC64 + elif test "x$OPENJDK_$1_CPU" = xriscv64; then + HOTSPOT_$1_CPU_DEFINE=RISCV64 + elif test "x$OPENJDK_$1_CPU" = xmips64; then + HOTSPOT_$1_CPU_DEFINE=MIPS64 + elif test "x$OPENJDK_$1_CPU" = xmips64el; then @@ -137,236 +135,9 @@ index 9e9e9454f0e..9058b736007 100644 # The cpu defines below are for zero, we don't support them directly. elif test "x$OPENJDK_$1_CPU" = xsparc; then -diff --git a/src/hotspot/cpu/aarch64/c1_LIRAssembler_aarch64.cpp b/src/hotspot/cpu/aarch64/c1_LIRAssembler_aarch64.cpp -index 5ce3ecf9e7a..2a43b3a3411 100644 ---- a/src/hotspot/cpu/aarch64/c1_LIRAssembler_aarch64.cpp -+++ b/src/hotspot/cpu/aarch64/c1_LIRAssembler_aarch64.cpp -@@ -1119,7 +1119,9 @@ void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) { - } - } - -- -+void LIR_Assembler::emit_opCmpBranch(LIR_OpCmpBranch* op) { -+ ShouldNotReachHere(); -+} - - void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) { - LIR_Opr src = op->in_opr(); -@@ -1658,6 +1660,10 @@ void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, L - __ csel(result->as_register(), opr1->as_register(), opr2->as_register(), acond); - } - -+void LIR_Assembler::cmp_cmove(LIR_Condition condition, LIR_Opr left, LIR_Opr right, LIR_Opr src1, LIR_Opr src2, LIR_Opr result, BasicType type) { -+ ShouldNotReachHere(); -+} -+ - void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack) { - assert(info == NULL, "should never be used, idiv/irem and ldiv/lrem not handled by this method"); - -diff --git a/src/hotspot/cpu/aarch64/c1_LIRGenerator_aarch64.cpp b/src/hotspot/cpu/aarch64/c1_LIRGenerator_aarch64.cpp -index d2cbdbdba26..6220d90dfec 100644 ---- a/src/hotspot/cpu/aarch64/c1_LIRGenerator_aarch64.cpp -+++ b/src/hotspot/cpu/aarch64/c1_LIRGenerator_aarch64.cpp -@@ -261,18 +261,29 @@ void LIRGenerator::increment_counter(LIR_Address* addr, int step) { - __ store(reg, addr); - } - --void LIRGenerator::cmp_mem_int(LIR_Condition condition, LIR_Opr base, int disp, int c, CodeEmitInfo* info) { -+template -+void LIRGenerator::cmp_mem_int_branch(LIR_Condition condition, LIR_Opr base, int disp, int c, T tgt, CodeEmitInfo* info) { - LIR_Opr reg = new_register(T_INT); - __ load(generate_address(base, disp, T_INT), reg, info); -- __ cmp(condition, reg, LIR_OprFact::intConst(c)); -+ __ cmp_branch(condition, reg, LIR_OprFact::intConst(c), tgt); - } - --void LIRGenerator::cmp_reg_mem(LIR_Condition condition, LIR_Opr reg, LIR_Opr base, int disp, BasicType type, CodeEmitInfo* info) { -+// Explicit instantiation for all supported types. -+template void LIRGenerator::cmp_mem_int_branch(LIR_Condition, LIR_Opr, int, int, Label*, CodeEmitInfo*); -+template void LIRGenerator::cmp_mem_int_branch(LIR_Condition, LIR_Opr, int, int, BlockBegin*, CodeEmitInfo*); -+template void LIRGenerator::cmp_mem_int_branch(LIR_Condition, LIR_Opr, int, int, CodeStub*, CodeEmitInfo*); -+ -+template -+void LIRGenerator::cmp_reg_mem_branch(LIR_Condition condition, LIR_Opr reg, LIR_Opr base, int disp, BasicType type, T tgt, CodeEmitInfo* info) { - LIR_Opr reg1 = new_register(T_INT); - __ load(generate_address(base, disp, type), reg1, info); -- __ cmp(condition, reg, reg1); -+ __ cmp_branch(condition, reg, reg1, tgt); - } - -+// Explicit instantiation for all supported types. -+template void LIRGenerator::cmp_reg_mem_branch(LIR_Condition, LIR_Opr, LIR_Opr, int, BasicType, Label*, CodeEmitInfo*); -+template void LIRGenerator::cmp_reg_mem_branch(LIR_Condition, LIR_Opr, LIR_Opr, int, BasicType, BlockBegin*, CodeEmitInfo*); -+template void LIRGenerator::cmp_reg_mem_branch(LIR_Condition, LIR_Opr, LIR_Opr, int, BasicType, CodeStub*, CodeEmitInfo*); - - bool LIRGenerator::strength_reduce_multiply(LIR_Opr left, jint c, LIR_Opr result, LIR_Opr tmp) { - -diff --git a/src/hotspot/cpu/aarch64/c1_LIR_aarch64.cpp b/src/hotspot/cpu/aarch64/c1_LIR_aarch64.cpp -index 58e1cf5ae63..8f67e6f4f67 100644 ---- a/src/hotspot/cpu/aarch64/c1_LIR_aarch64.cpp -+++ b/src/hotspot/cpu/aarch64/c1_LIR_aarch64.cpp -@@ -52,3 +52,24 @@ void LIR_Address::verify() const { - "wrong type for addresses"); - } - #endif // PRODUCT -+ -+template -+void LIR_List::cmp_branch(LIR_Condition condition, LIR_Opr left, LIR_Opr right, T tgt, CodeEmitInfo* info) { -+ cmp(condition, left, right, info); -+ branch(condition, tgt); -+} -+ -+// Explicit instantiation for all supported types. -+template void LIR_List::cmp_branch(LIR_Condition, LIR_Opr, LIR_Opr, Label*, CodeEmitInfo*); -+template void LIR_List::cmp_branch(LIR_Condition, LIR_Opr, LIR_Opr, BlockBegin*, CodeEmitInfo*); -+template void LIR_List::cmp_branch(LIR_Condition, LIR_Opr, LIR_Opr, CodeStub*, CodeEmitInfo*); -+ -+void LIR_List::cmp_branch(LIR_Condition condition, LIR_Opr left, LIR_Opr right, BlockBegin* block, BlockBegin* unordered) { -+ cmp(condition, left, right); -+ branch(condition, block, unordered); -+} -+ -+void LIR_List::cmp_cmove(LIR_Condition condition, LIR_Opr left, LIR_Opr right, LIR_Opr src1, LIR_Opr src2, LIR_Opr dst, BasicType type) { -+ cmp(condition, left, right); -+ cmove(condition, src1, src2, dst, type); -+} -diff --git a/src/hotspot/cpu/aarch64/gc/z/zBarrierSetAssembler_aarch64.cpp b/src/hotspot/cpu/aarch64/gc/z/zBarrierSetAssembler_aarch64.cpp -index 6b42982ed90..e39e6e8ab48 100644 ---- a/src/hotspot/cpu/aarch64/gc/z/zBarrierSetAssembler_aarch64.cpp -+++ b/src/hotspot/cpu/aarch64/gc/z/zBarrierSetAssembler_aarch64.cpp -@@ -209,7 +209,8 @@ void ZBarrierSetAssembler::try_resolve_jobject_in_native(MacroAssembler* masm, - #define __ ce->masm()-> - - void ZBarrierSetAssembler::generate_c1_load_barrier_test(LIR_Assembler* ce, -- LIR_Opr ref) const { -+ LIR_Opr ref, -+ LIR_Opr res) const { - assert_different_registers(rscratch1, rthread, ref->as_register()); - - __ ldr(rscratch1, address_bad_mask_from_thread(rthread)); -diff --git a/src/hotspot/cpu/aarch64/gc/z/zBarrierSetAssembler_aarch64.hpp b/src/hotspot/cpu/aarch64/gc/z/zBarrierSetAssembler_aarch64.hpp -index cca87382560..de7bda178d3 100644 ---- a/src/hotspot/cpu/aarch64/gc/z/zBarrierSetAssembler_aarch64.hpp -+++ b/src/hotspot/cpu/aarch64/gc/z/zBarrierSetAssembler_aarch64.hpp -@@ -79,7 +79,8 @@ public: - - #ifdef COMPILER1 - void generate_c1_load_barrier_test(LIR_Assembler* ce, -- LIR_Opr ref) const; -+ LIR_Opr ref, -+ LIR_Opr res) const; - - void generate_c1_load_barrier_stub(LIR_Assembler* ce, - ZLoadBarrierStubC1* stub) const; -diff --git a/src/hotspot/cpu/aarch64/gc/z/zGlobals_aarch64.hpp b/src/hotspot/cpu/aarch64/gc/z/zGlobals_aarch64.hpp -index 3187808b65a..bf18d48814f 100644 ---- a/src/hotspot/cpu/aarch64/gc/z/zGlobals_aarch64.hpp -+++ b/src/hotspot/cpu/aarch64/gc/z/zGlobals_aarch64.hpp -@@ -28,6 +28,8 @@ const size_t ZPlatformGranuleSizeShift = 21; // 2MB - const size_t ZPlatformHeapViews = 3; - const size_t ZPlatformCacheLineSize = 64; - -+const bool ZPlatformLoadBarrierTestResultInRegister = false; -+ - size_t ZPlatformAddressOffsetBits(); - size_t ZPlatformAddressMetadataShift(); - -diff --git a/src/hotspot/cpu/arm/c1_LIRAssembler_arm.cpp b/src/hotspot/cpu/arm/c1_LIRAssembler_arm.cpp -index 1c21f835f75..9a3d3b6eabd 100644 ---- a/src/hotspot/cpu/arm/c1_LIRAssembler_arm.cpp -+++ b/src/hotspot/cpu/arm/c1_LIRAssembler_arm.cpp -@@ -899,6 +899,9 @@ void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) { - __ b(*(op->label()), acond); - } - -+void LIR_Assembler::emit_opCmpBranch(LIR_OpCmpBranch* op) { -+ ShouldNotReachHere(); -+} - - void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) { - LIR_Opr src = op->in_opr(); -@@ -1498,6 +1501,10 @@ void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, L - } - } - -+void LIR_Assembler::cmp_cmove(LIR_Condition condition, LIR_Opr left, LIR_Opr right, LIR_Opr src1, LIR_Opr src2, LIR_Opr result, BasicType type) { -+ ShouldNotReachHere(); -+} -+ - #ifdef ASSERT - static int reg_size(LIR_Opr op) { - switch (op->type()) { -diff --git a/src/hotspot/cpu/arm/c1_LIRGenerator_arm.cpp b/src/hotspot/cpu/arm/c1_LIRGenerator_arm.cpp -index b16986ee2a2..46904771218 100644 ---- a/src/hotspot/cpu/arm/c1_LIRGenerator_arm.cpp -+++ b/src/hotspot/cpu/arm/c1_LIRGenerator_arm.cpp -@@ -313,18 +313,27 @@ void LIRGenerator::increment_counter(LIR_Address* addr, int step) { - __ move(temp, addr); - } - -- --void LIRGenerator::cmp_mem_int(LIR_Condition condition, LIR_Opr base, int disp, int c, CodeEmitInfo* info) { -+template -+void LIRGenerator::cmp_mem_int_branch(LIR_Condition condition, LIR_Opr base, int disp, int c, T tgt, CodeEmitInfo* info) { - __ load(new LIR_Address(base, disp, T_INT), FrameMap::LR_opr, info); -- __ cmp(condition, FrameMap::LR_opr, c); -+ __ cmp_branch(condition, FrameMap::LR_opr, c, tgt); - } - -+// Explicit instantiation for all supported types. -+template void LIRGenerator::cmp_mem_int_branch(LIR_Condition, LIR_Opr, int, int, Label*, CodeEmitInfo*); -+template void LIRGenerator::cmp_mem_int_branch(LIR_Condition, LIR_Opr, int, int, BlockBegin*, CodeEmitInfo*); -+template void LIRGenerator::cmp_mem_int_branch(LIR_Condition, LIR_Opr, int, int, CodeStub*, CodeEmitInfo*); - --void LIRGenerator::cmp_reg_mem(LIR_Condition condition, LIR_Opr reg, LIR_Opr base, int disp, BasicType type, CodeEmitInfo* info) { -+template -+void LIRGenerator::cmp_reg_mem_branch(LIR_Condition condition, LIR_Opr reg, LIR_Opr base, int disp, BasicType type, T tgt, CodeEmitInfo* info) { - __ load(new LIR_Address(base, disp, type), FrameMap::LR_opr, info); -- __ cmp(condition, reg, FrameMap::LR_opr); -+ __ cmp_branch(condition, reg, FrameMap::LR_opr, tgt); - } - -+// Explicit instantiation for all supported types. -+template void LIRGenerator::cmp_reg_mem_branch(LIR_Condition, LIR_Opr, LIR_Opr, int, BasicType, Label*, CodeEmitInfo*); -+template void LIRGenerator::cmp_reg_mem_branch(LIR_Condition, LIR_Opr, LIR_Opr, int, BasicType, BlockBegin*, CodeEmitInfo*); -+template void LIRGenerator::cmp_reg_mem_branch(LIR_Condition, LIR_Opr, LIR_Opr, int, BasicType, CodeStub*, CodeEmitInfo*); - - bool LIRGenerator::strength_reduce_multiply(LIR_Opr left, jint c, LIR_Opr result, LIR_Opr tmp) { - assert(left != result, "should be different registers"); -diff --git a/src/hotspot/cpu/arm/c1_LIR_arm.cpp b/src/hotspot/cpu/arm/c1_LIR_arm.cpp -index 60bd5265bfb..11df12754cd 100644 ---- a/src/hotspot/cpu/arm/c1_LIR_arm.cpp -+++ b/src/hotspot/cpu/arm/c1_LIR_arm.cpp -@@ -62,3 +62,24 @@ void LIR_Address::verify() const { - #endif - } - #endif // PRODUCT -+ -+template -+void LIR_List::cmp_branch(LIR_Condition condition, LIR_Opr left, LIR_Opr right, T tgt, CodeEmitInfo* info) { -+ cmp(condition, left, right, info); -+ branch(condition, tgt); -+} -+ -+// Explicit instantiation for all supported types. -+template void LIR_List::cmp_branch(LIR_Condition, LIR_Opr, LIR_Opr, Label*, CodeEmitInfo*); -+template void LIR_List::cmp_branch(LIR_Condition, LIR_Opr, LIR_Opr, BlockBegin*, CodeEmitInfo*); -+template void LIR_List::cmp_branch(LIR_Condition, LIR_Opr, LIR_Opr, CodeStub*, CodeEmitInfo*); -+ -+void LIR_List::cmp_branch(LIR_Condition condition, LIR_Opr left, LIR_Opr right, BlockBegin* block, BlockBegin* unordered) { -+ cmp(condition, left, right); -+ branch(condition, block, unordered); -+} -+ -+void LIR_List::cmp_cmove(LIR_Condition condition, LIR_Opr left, LIR_Opr right, LIR_Opr src1, LIR_Opr src2, LIR_Opr dst, BasicType type) { -+ cmp(condition, left, right); -+ cmove(condition, src1, src2, dst, type); -+} -diff --git a/src/hotspot/cpu/loongarch/abstractInterpreter_loongarch.cpp b/src/hotspot/cpu/loongarch/abstractInterpreter_loongarch.cpp -new file mode 100644 -index 00000000000..fbcd4050b64 ---- /dev/null -+++ b/src/hotspot/cpu/loongarch/abstractInterpreter_loongarch.cpp +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/abstractInterpreter_loongarch.cpp b/src/hotspot/cpu/loongarch/abstractInterpreter_loongarch.cpp +--- a/src/hotspot/cpu/loongarch/abstractInterpreter_loongarch.cpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/loongarch/abstractInterpreter_loongarch.cpp 2024-01-31 14:01:11.594095468 +0800 @@ -0,0 +1,133 @@ +/* + * Copyright (c) 2003, 2013, Oracle and/or its affiliates. All rights reserved. @@ -501,11 +272,9 @@ index 00000000000..fbcd4050b64 + *interpreter_frame->interpreter_frame_mirror_addr() = method->method_holder()->java_mirror(); +} + -diff --git a/src/hotspot/cpu/loongarch/assembler_loongarch.cpp b/src/hotspot/cpu/loongarch/assembler_loongarch.cpp -new file mode 100644 -index 00000000000..e6e62cccad0 ---- /dev/null -+++ b/src/hotspot/cpu/loongarch/assembler_loongarch.cpp +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/assembler_loongarch.cpp b/src/hotspot/cpu/loongarch/assembler_loongarch.cpp +--- a/src/hotspot/cpu/loongarch/assembler_loongarch.cpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/loongarch/assembler_loongarch.cpp 2024-01-31 14:01:11.594095468 +0800 @@ -0,0 +1,849 @@ +/* + * Copyright (c) 1997, 2014, Oracle and/or its affiliates. All rights reserved. @@ -1356,12 +1125,10 @@ index 00000000000..e6e62cccad0 + } + } +} -diff --git a/src/hotspot/cpu/loongarch/assembler_loongarch.hpp b/src/hotspot/cpu/loongarch/assembler_loongarch.hpp -new file mode 100644 -index 00000000000..40a3aea36f8 ---- /dev/null -+++ b/src/hotspot/cpu/loongarch/assembler_loongarch.hpp -@@ -0,0 +1,2812 @@ +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/assembler_loongarch.hpp b/src/hotspot/cpu/loongarch/assembler_loongarch.hpp +--- a/src/hotspot/cpu/loongarch/assembler_loongarch.hpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/loongarch/assembler_loongarch.hpp 2024-01-31 14:01:11.597428831 +0800 +@@ -0,0 +1,2831 @@ +/* + * Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 2015, 2021, Loongson Technology. All rights reserved. @@ -2560,6 +2327,7 @@ index 00000000000..40a3aea36f8 + stptr_w_op = 0b00100101, + ldptr_d_op = 0b00100110, + stptr_d_op = 0b00100111, ++ csr_op = 0b00000100, + + unknow_ops8 = 0b11111111 + }; @@ -2656,6 +2424,15 @@ index 00000000000..40a3aea36f8 + static int high6 (int x) { return high(x, 6); } + + ++ static ALWAYSINLINE void patch(address a, int length, uint32_t val) { ++ guarantee(val < (1ULL << length), "Field too big for insn"); ++ guarantee(length > 0, "length > 0"); ++ unsigned target = *(unsigned *)a; ++ target = (target >> length) << length; ++ target |= val; ++ *(unsigned *)a = target; ++ } ++ + protected: + // help methods for instruction ejection + @@ -3219,6 +2996,8 @@ index 00000000000..40a3aea36f8 + void stptr_w (Register rd, Register rj, int si16) { assert(is_simm(si16, 16) && ((si16 & 0x3) == 0), "not a signed 16-bit int"); emit_int32(insn_I14RR(stptr_w_op, si16>>2, (int)rj->encoding(), (int)rd->encoding())); } + void ldptr_d (Register rd, Register rj, int si16) { assert(is_simm(si16, 16) && ((si16 & 0x3) == 0), "not a signed 16-bit int"); emit_int32(insn_I14RR(ldptr_d_op, si16>>2, (int)rj->encoding(), (int)rd->encoding())); } + void stptr_d (Register rd, Register rj, int si16) { assert(is_simm(si16, 16) && ((si16 & 0x3) == 0), "not a signed 16-bit int"); emit_int32(insn_I14RR(stptr_d_op, si16>>2, (int)rj->encoding(), (int)rd->encoding())); } ++ void csrrd (Register rd, int csr) { emit_int32(insn_I14RR(csr_op, csr, 0, (int)rd->encoding())); } ++ void csrwr (Register rd, int csr) { emit_int32(insn_I14RR(csr_op, csr, 1, (int)rd->encoding())); } + + void ld_b (Register rd, Register rj, int si12) { assert(is_simm(si12, 12), "not a signed 12-bit int"); emit_int32(insn_I12RR(ld_b_op, si12, (int)rj->encoding(), (int)rd->encoding())); } + void ld_h (Register rd, Register rj, int si12) { assert(is_simm(si12, 12), "not a signed 12-bit int"); emit_int32(insn_I12RR(ld_h_op, si12, (int)rj->encoding(), (int)rd->encoding())); } @@ -3392,18 +3171,25 @@ index 00000000000..40a3aea36f8 + void bceqz(ConditionalFlagRegister cj, Label& L) { bceqz(cj, target(L)); } + void bcnez(ConditionalFlagRegister cj, Label& L) { bcnez(cj, target(L)); } + -+ // Now Membar_mask_bits is 0,Need to fix it after LA6000 + typedef enum { -+ StoreStore = 0, -+ LoadStore = 0, -+ StoreLoad = 0, -+ LoadLoad = 0, -+ AnyAny = 0 ++ // hint[4] ++ Completion = 0, ++ Ordering = (1 << 4), ++ ++ // The bitwise-not of the below constants is corresponding to the hint. This is convenient for OR operation. ++ // hint[3:2] and hint[1:0] ++ LoadLoad = ((1 << 3) | (1 << 1)), ++ LoadStore = ((1 << 3) | (1 << 0)), ++ StoreLoad = ((1 << 2) | (1 << 1)), ++ StoreStore = ((1 << 2) | (1 << 0)), ++ AnyAny = ((3 << 2) | (3 << 0)), + } Membar_mask_bits; + + // Serializes memory and blows flags + void membar(Membar_mask_bits hint) { -+ dbar(hint); ++ assert((hint & (3 << 0)) != 0, "membar mask unsupported!"); ++ assert((hint & (3 << 2)) != 0, "membar mask unsupported!"); ++ dbar(Ordering | (~hint & 0xf)); + } + + // LSX and LASX @@ -4174,11 +3960,9 @@ index 00000000000..40a3aea36f8 +}; + +#endif // CPU_LOONGARCH_ASSEMBLER_LOONGARCH_HPP -diff --git a/src/hotspot/cpu/loongarch/assembler_loongarch.inline.hpp b/src/hotspot/cpu/loongarch/assembler_loongarch.inline.hpp -new file mode 100644 -index 00000000000..9ca0cd45047 ---- /dev/null -+++ b/src/hotspot/cpu/loongarch/assembler_loongarch.inline.hpp +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/assembler_loongarch.inline.hpp b/src/hotspot/cpu/loongarch/assembler_loongarch.inline.hpp +--- a/src/hotspot/cpu/loongarch/assembler_loongarch.inline.hpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/loongarch/assembler_loongarch.inline.hpp 2024-01-31 14:01:11.597428831 +0800 @@ -0,0 +1,33 @@ +/* + * Copyright (c) 1997, 2010, Oracle and/or its affiliates. All rights reserved. @@ -4213,11 +3997,9 @@ index 00000000000..9ca0cd45047 +#include "code/codeCache.hpp" + +#endif // CPU_LOONGARCH_ASSEMBLER_LOONGARCH_INLINE_HPP -diff --git a/src/hotspot/cpu/loongarch/bytes_loongarch.hpp b/src/hotspot/cpu/loongarch/bytes_loongarch.hpp -new file mode 100644 -index 00000000000..c15344eb390 ---- /dev/null -+++ b/src/hotspot/cpu/loongarch/bytes_loongarch.hpp +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/bytes_loongarch.hpp b/src/hotspot/cpu/loongarch/bytes_loongarch.hpp +--- a/src/hotspot/cpu/loongarch/bytes_loongarch.hpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/loongarch/bytes_loongarch.hpp 2024-01-31 14:01:11.597428831 +0800 @@ -0,0 +1,73 @@ +/* + * Copyright (c) 1997, 2010, Oracle and/or its affiliates. All rights reserved. @@ -4292,11 +4074,9 @@ index 00000000000..c15344eb390 +#include OS_CPU_HEADER_INLINE(bytes) + +#endif // CPU_LOONGARCH_BYTES_LOONGARCH_HPP -diff --git a/src/hotspot/cpu/loongarch/c1_CodeStubs_loongarch_64.cpp b/src/hotspot/cpu/loongarch/c1_CodeStubs_loongarch_64.cpp -new file mode 100644 -index 00000000000..663a9aec2a9 ---- /dev/null -+++ b/src/hotspot/cpu/loongarch/c1_CodeStubs_loongarch_64.cpp +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/c1_CodeStubs_loongarch_64.cpp b/src/hotspot/cpu/loongarch/c1_CodeStubs_loongarch_64.cpp +--- a/src/hotspot/cpu/loongarch/c1_CodeStubs_loongarch_64.cpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/loongarch/c1_CodeStubs_loongarch_64.cpp 2024-01-31 14:01:11.597428831 +0800 @@ -0,0 +1,360 @@ +/* + * Copyright (c) 1999, 2021, Oracle and/or its affiliates. All rights reserved. @@ -4658,11 +4438,9 @@ index 00000000000..663a9aec2a9 +} + +#undef __ -diff --git a/src/hotspot/cpu/loongarch/c1_Defs_loongarch.hpp b/src/hotspot/cpu/loongarch/c1_Defs_loongarch.hpp -new file mode 100644 -index 00000000000..1140e44431d ---- /dev/null -+++ b/src/hotspot/cpu/loongarch/c1_Defs_loongarch.hpp +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/c1_Defs_loongarch.hpp b/src/hotspot/cpu/loongarch/c1_Defs_loongarch.hpp +--- a/src/hotspot/cpu/loongarch/c1_Defs_loongarch.hpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/loongarch/c1_Defs_loongarch.hpp 2024-01-31 14:01:11.597428831 +0800 @@ -0,0 +1,79 @@ +/* + * Copyright (c) 2000, 2021, Oracle and/or its affiliates. All rights reserved. @@ -4743,49 +4521,9 @@ index 00000000000..1140e44431d +}; + +#endif // CPU_LOONGARCH_C1_DEFS_LOONGARCH_HPP -diff --git a/src/hotspot/cpu/loongarch/c1_FpuStackSim_loongarch.hpp b/src/hotspot/cpu/loongarch/c1_FpuStackSim_loongarch.hpp -new file mode 100644 -index 00000000000..047412d036a ---- /dev/null -+++ b/src/hotspot/cpu/loongarch/c1_FpuStackSim_loongarch.hpp -@@ -0,0 +1,32 @@ -+/* -+ * Copyright (c) 2005, 2019, Oracle and/or its affiliates. All rights reserved. -+ * Copyright (c) 2021, Loongson Technology. All rights reserved. -+ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. -+ * -+ * This code is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 only, as -+ * published by the Free Software Foundation. -+ * -+ * This code is distributed in the hope that it will be useful, but WITHOUT -+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -+ * version 2 for more details (a copy is included in the LICENSE file that -+ * accompanied this code). -+ * -+ * You should have received a copy of the GNU General Public License version -+ * 2 along with this work; if not, write to the Free Software Foundation, -+ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. -+ * -+ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA -+ * or visit www.oracle.com if you need additional information or have any -+ * questions. -+ * -+ */ -+ -+#ifndef CPU_LOONGARCH_C1_FPUSTACKSIM_LOONGARCH_HPP -+#define CPU_LOONGARCH_C1_FPUSTACKSIM_LOONGARCH_HPP -+ -+// No FPU stack on LoongArch -+class FpuStackSim; -+ -+#endif // CPU_LOONGARCH_C1_FPUSTACKSIM_LOONGARCH_HPP -diff --git a/src/hotspot/cpu/loongarch/c1_FpuStackSim_loongarch_64.cpp b/src/hotspot/cpu/loongarch/c1_FpuStackSim_loongarch_64.cpp -new file mode 100644 -index 00000000000..1a89c437a83 ---- /dev/null -+++ b/src/hotspot/cpu/loongarch/c1_FpuStackSim_loongarch_64.cpp +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/c1_FpuStackSim_loongarch_64.cpp b/src/hotspot/cpu/loongarch/c1_FpuStackSim_loongarch_64.cpp +--- a/src/hotspot/cpu/loongarch/c1_FpuStackSim_loongarch_64.cpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/loongarch/c1_FpuStackSim_loongarch_64.cpp 2024-01-31 14:01:11.597428831 +0800 @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2005, 2017, Oracle and/or its affiliates. All rights reserved. @@ -4818,14 +4556,12 @@ index 00000000000..1a89c437a83 + +// No FPU stack on LoongArch64 +#include "precompiled.hpp" -diff --git a/src/hotspot/cpu/loongarch/c1_FrameMap_loongarch.hpp b/src/hotspot/cpu/loongarch/c1_FrameMap_loongarch.hpp -new file mode 100644 -index 00000000000..4f0cf053617 ---- /dev/null -+++ b/src/hotspot/cpu/loongarch/c1_FrameMap_loongarch.hpp -@@ -0,0 +1,143 @@ +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/c1_FpuStackSim_loongarch.hpp b/src/hotspot/cpu/loongarch/c1_FpuStackSim_loongarch.hpp +--- a/src/hotspot/cpu/loongarch/c1_FpuStackSim_loongarch.hpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/loongarch/c1_FpuStackSim_loongarch.hpp 2024-01-31 14:01:11.597428831 +0800 +@@ -0,0 +1,32 @@ +/* -+ * Copyright (c) 1999, 2019, Oracle and/or its affiliates. All rights reserved. ++ * Copyright (c) 2005, 2019, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 2021, Loongson Technology. All rights reserved. + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. + * @@ -4849,129 +4585,16 @@ index 00000000000..4f0cf053617 + * + */ + -+#ifndef CPU_LOONGARCH_C1_FRAMEMAP_LOONGARCH_HPP -+#define CPU_LOONGARCH_C1_FRAMEMAP_LOONGARCH_HPP -+ -+// On LoongArch64 the frame looks as follows: -+// -+// +-----------------------------+---------+----------------------------------------+----------------+----------- -+// | size_arguments-nof_reg_args | 2 words | size_locals-size_arguments+numreg_args | _size_monitors | spilling . -+// +-----------------------------+---------+----------------------------------------+----------------+----------- -+ -+ public: -+ static const int pd_c_runtime_reserved_arg_size; -+ -+ enum { -+ first_available_sp_in_frame = 0, -+ frame_pad_in_bytes = 16, -+ nof_reg_args = 8 -+ }; -+ -+ public: -+ static LIR_Opr receiver_opr; -+ -+ static LIR_Opr r0_opr; -+ static LIR_Opr ra_opr; -+ static LIR_Opr tp_opr; -+ static LIR_Opr sp_opr; -+ static LIR_Opr a0_opr; -+ static LIR_Opr a1_opr; -+ static LIR_Opr a2_opr; -+ static LIR_Opr a3_opr; -+ static LIR_Opr a4_opr; -+ static LIR_Opr a5_opr; -+ static LIR_Opr a6_opr; -+ static LIR_Opr a7_opr; -+ static LIR_Opr t0_opr; -+ static LIR_Opr t1_opr; -+ static LIR_Opr t2_opr; -+ static LIR_Opr t3_opr; -+ static LIR_Opr t4_opr; -+ static LIR_Opr t5_opr; -+ static LIR_Opr t6_opr; -+ static LIR_Opr t7_opr; -+ static LIR_Opr t8_opr; -+ static LIR_Opr rx_opr; -+ static LIR_Opr fp_opr; -+ static LIR_Opr s0_opr; -+ static LIR_Opr s1_opr; -+ static LIR_Opr s2_opr; -+ static LIR_Opr s3_opr; -+ static LIR_Opr s4_opr; -+ static LIR_Opr s5_opr; -+ static LIR_Opr s6_opr; -+ static LIR_Opr s7_opr; -+ static LIR_Opr s8_opr; -+ -+ static LIR_Opr ra_oop_opr; -+ static LIR_Opr a0_oop_opr; -+ static LIR_Opr a1_oop_opr; -+ static LIR_Opr a2_oop_opr; -+ static LIR_Opr a3_oop_opr; -+ static LIR_Opr a4_oop_opr; -+ static LIR_Opr a5_oop_opr; -+ static LIR_Opr a6_oop_opr; -+ static LIR_Opr a7_oop_opr; -+ static LIR_Opr t0_oop_opr; -+ static LIR_Opr t1_oop_opr; -+ static LIR_Opr t2_oop_opr; -+ static LIR_Opr t3_oop_opr; -+ static LIR_Opr t4_oop_opr; -+ static LIR_Opr t5_oop_opr; -+ static LIR_Opr t6_oop_opr; -+ static LIR_Opr t7_oop_opr; -+ static LIR_Opr t8_oop_opr; -+ static LIR_Opr fp_oop_opr; -+ static LIR_Opr s0_oop_opr; -+ static LIR_Opr s1_oop_opr; -+ static LIR_Opr s2_oop_opr; -+ static LIR_Opr s3_oop_opr; -+ static LIR_Opr s4_oop_opr; -+ static LIR_Opr s5_oop_opr; -+ static LIR_Opr s6_oop_opr; -+ static LIR_Opr s7_oop_opr; -+ static LIR_Opr s8_oop_opr; -+ -+ static LIR_Opr scr1_opr; -+ static LIR_Opr scr2_opr; -+ static LIR_Opr scr1_long_opr; -+ static LIR_Opr scr2_long_opr; -+ -+ static LIR_Opr a0_metadata_opr; -+ static LIR_Opr a1_metadata_opr; -+ static LIR_Opr a2_metadata_opr; -+ static LIR_Opr a3_metadata_opr; -+ static LIR_Opr a4_metadata_opr; -+ static LIR_Opr a5_metadata_opr; -+ -+ static LIR_Opr long0_opr; -+ static LIR_Opr long1_opr; -+ static LIR_Opr fpu0_float_opr; -+ static LIR_Opr fpu0_double_opr; -+ -+ static LIR_Opr as_long_opr(Register r) { -+ return LIR_OprFact::double_cpu(cpu_reg2rnr(r), cpu_reg2rnr(r)); -+ } -+ static LIR_Opr as_pointer_opr(Register r) { -+ return LIR_OprFact::double_cpu(cpu_reg2rnr(r), cpu_reg2rnr(r)); -+ } -+ -+ // VMReg name for spilled physical FPU stack slot n -+ static VMReg fpu_regname (int n); -+ -+ static bool is_caller_save_register(LIR_Opr opr) { return true; } -+ static bool is_caller_save_register(Register r) { return true; } ++#ifndef CPU_LOONGARCH_C1_FPUSTACKSIM_LOONGARCH_HPP ++#define CPU_LOONGARCH_C1_FPUSTACKSIM_LOONGARCH_HPP + -+ static int nof_caller_save_cpu_regs() { return pd_nof_caller_save_cpu_regs_frame_map; } -+ static int last_cpu_reg() { return pd_last_cpu_reg; } -+ static int last_byte_reg() { return pd_last_byte_reg; } ++// No FPU stack on LoongArch ++class FpuStackSim; + -+#endif // CPU_LOONGARCH_C1_FRAMEMAP_LOONGARCH_HPP -diff --git a/src/hotspot/cpu/loongarch/c1_FrameMap_loongarch_64.cpp b/src/hotspot/cpu/loongarch/c1_FrameMap_loongarch_64.cpp -new file mode 100644 -index 00000000000..8d439fda060 ---- /dev/null -+++ b/src/hotspot/cpu/loongarch/c1_FrameMap_loongarch_64.cpp ++#endif // CPU_LOONGARCH_C1_FPUSTACKSIM_LOONGARCH_HPP +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/c1_FrameMap_loongarch_64.cpp b/src/hotspot/cpu/loongarch/c1_FrameMap_loongarch_64.cpp +--- a/src/hotspot/cpu/loongarch/c1_FrameMap_loongarch_64.cpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/loongarch/c1_FrameMap_loongarch_64.cpp 2024-01-31 14:01:11.597428831 +0800 @@ -0,0 +1,362 @@ +/* + * Copyright (c) 1999, 2019, Oracle and/or its affiliates. All rights reserved. @@ -5335,12 +4958,157 @@ index 00000000000..8d439fda060 +bool FrameMap::validate_frame() { + return true; +} -diff --git a/src/hotspot/cpu/loongarch/c1_LIRAssembler_loongarch.hpp b/src/hotspot/cpu/loongarch/c1_LIRAssembler_loongarch.hpp -new file mode 100644 -index 00000000000..486592903ce ---- /dev/null -+++ b/src/hotspot/cpu/loongarch/c1_LIRAssembler_loongarch.hpp -@@ -0,0 +1,82 @@ +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/c1_FrameMap_loongarch.hpp b/src/hotspot/cpu/loongarch/c1_FrameMap_loongarch.hpp +--- a/src/hotspot/cpu/loongarch/c1_FrameMap_loongarch.hpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/loongarch/c1_FrameMap_loongarch.hpp 2024-01-31 14:01:11.597428831 +0800 +@@ -0,0 +1,143 @@ ++/* ++ * Copyright (c) 1999, 2019, Oracle and/or its affiliates. All rights reserved. ++ * Copyright (c) 2021, Loongson Technology. All rights reserved. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ * ++ */ ++ ++#ifndef CPU_LOONGARCH_C1_FRAMEMAP_LOONGARCH_HPP ++#define CPU_LOONGARCH_C1_FRAMEMAP_LOONGARCH_HPP ++ ++// On LoongArch64 the frame looks as follows: ++// ++// +-----------------------------+---------+----------------------------------------+----------------+----------- ++// | size_arguments-nof_reg_args | 2 words | size_locals-size_arguments+numreg_args | _size_monitors | spilling . ++// +-----------------------------+---------+----------------------------------------+----------------+----------- ++ ++ public: ++ static const int pd_c_runtime_reserved_arg_size; ++ ++ enum { ++ first_available_sp_in_frame = 0, ++ frame_pad_in_bytes = 16, ++ nof_reg_args = 8 ++ }; ++ ++ public: ++ static LIR_Opr receiver_opr; ++ ++ static LIR_Opr r0_opr; ++ static LIR_Opr ra_opr; ++ static LIR_Opr tp_opr; ++ static LIR_Opr sp_opr; ++ static LIR_Opr a0_opr; ++ static LIR_Opr a1_opr; ++ static LIR_Opr a2_opr; ++ static LIR_Opr a3_opr; ++ static LIR_Opr a4_opr; ++ static LIR_Opr a5_opr; ++ static LIR_Opr a6_opr; ++ static LIR_Opr a7_opr; ++ static LIR_Opr t0_opr; ++ static LIR_Opr t1_opr; ++ static LIR_Opr t2_opr; ++ static LIR_Opr t3_opr; ++ static LIR_Opr t4_opr; ++ static LIR_Opr t5_opr; ++ static LIR_Opr t6_opr; ++ static LIR_Opr t7_opr; ++ static LIR_Opr t8_opr; ++ static LIR_Opr rx_opr; ++ static LIR_Opr fp_opr; ++ static LIR_Opr s0_opr; ++ static LIR_Opr s1_opr; ++ static LIR_Opr s2_opr; ++ static LIR_Opr s3_opr; ++ static LIR_Opr s4_opr; ++ static LIR_Opr s5_opr; ++ static LIR_Opr s6_opr; ++ static LIR_Opr s7_opr; ++ static LIR_Opr s8_opr; ++ ++ static LIR_Opr ra_oop_opr; ++ static LIR_Opr a0_oop_opr; ++ static LIR_Opr a1_oop_opr; ++ static LIR_Opr a2_oop_opr; ++ static LIR_Opr a3_oop_opr; ++ static LIR_Opr a4_oop_opr; ++ static LIR_Opr a5_oop_opr; ++ static LIR_Opr a6_oop_opr; ++ static LIR_Opr a7_oop_opr; ++ static LIR_Opr t0_oop_opr; ++ static LIR_Opr t1_oop_opr; ++ static LIR_Opr t2_oop_opr; ++ static LIR_Opr t3_oop_opr; ++ static LIR_Opr t4_oop_opr; ++ static LIR_Opr t5_oop_opr; ++ static LIR_Opr t6_oop_opr; ++ static LIR_Opr t7_oop_opr; ++ static LIR_Opr t8_oop_opr; ++ static LIR_Opr fp_oop_opr; ++ static LIR_Opr s0_oop_opr; ++ static LIR_Opr s1_oop_opr; ++ static LIR_Opr s2_oop_opr; ++ static LIR_Opr s3_oop_opr; ++ static LIR_Opr s4_oop_opr; ++ static LIR_Opr s5_oop_opr; ++ static LIR_Opr s6_oop_opr; ++ static LIR_Opr s7_oop_opr; ++ static LIR_Opr s8_oop_opr; ++ ++ static LIR_Opr scr1_opr; ++ static LIR_Opr scr2_opr; ++ static LIR_Opr scr1_long_opr; ++ static LIR_Opr scr2_long_opr; ++ ++ static LIR_Opr a0_metadata_opr; ++ static LIR_Opr a1_metadata_opr; ++ static LIR_Opr a2_metadata_opr; ++ static LIR_Opr a3_metadata_opr; ++ static LIR_Opr a4_metadata_opr; ++ static LIR_Opr a5_metadata_opr; ++ ++ static LIR_Opr long0_opr; ++ static LIR_Opr long1_opr; ++ static LIR_Opr fpu0_float_opr; ++ static LIR_Opr fpu0_double_opr; ++ ++ static LIR_Opr as_long_opr(Register r) { ++ return LIR_OprFact::double_cpu(cpu_reg2rnr(r), cpu_reg2rnr(r)); ++ } ++ static LIR_Opr as_pointer_opr(Register r) { ++ return LIR_OprFact::double_cpu(cpu_reg2rnr(r), cpu_reg2rnr(r)); ++ } ++ ++ // VMReg name for spilled physical FPU stack slot n ++ static VMReg fpu_regname (int n); ++ ++ static bool is_caller_save_register(LIR_Opr opr) { return true; } ++ static bool is_caller_save_register(Register r) { return true; } ++ ++ static int nof_caller_save_cpu_regs() { return pd_nof_caller_save_cpu_regs_frame_map; } ++ static int last_cpu_reg() { return pd_last_cpu_reg; } ++ static int last_byte_reg() { return pd_last_byte_reg; } ++ ++#endif // CPU_LOONGARCH_C1_FRAMEMAP_LOONGARCH_HPP +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/c1_globals_loongarch.hpp b/src/hotspot/cpu/loongarch/c1_globals_loongarch.hpp +--- a/src/hotspot/cpu/loongarch/c1_globals_loongarch.hpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/loongarch/c1_globals_loongarch.hpp 2024-01-31 14:01:11.597428831 +0800 +@@ -0,0 +1,65 @@ +/* + * Copyright (c) 2000, 2021, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 2021, Loongson Technology. All rights reserved. @@ -5366,69 +5134,161 @@ index 00000000000..486592903ce + * + */ + -+#ifndef CPU_LOONGARCH_C1_LIRASSEMBLER_LOONGARCH_HPP -+#define CPU_LOONGARCH_C1_LIRASSEMBLER_LOONGARCH_HPP ++#ifndef CPU_LOONGARCH_C1_GLOBALS_LOONGARCH_HPP ++#define CPU_LOONGARCH_C1_GLOBALS_LOONGARCH_HPP + -+// ArrayCopyStub needs access to bailout -+friend class ArrayCopyStub; ++#include "utilities/globalDefinitions.hpp" ++#include "utilities/macros.hpp" + -+ private: -+ int array_element_size(BasicType type) const; ++// Sets the default values for platform dependent flags used by the client compiler. ++// (see c1_globals.hpp) + -+ void arith_fpu_implementation(LIR_Code code, int left_index, int right_index, -+ int dest_index, bool pop_fpu_stack); ++#ifndef COMPILER2 ++define_pd_global(bool, BackgroundCompilation, true ); ++define_pd_global(bool, InlineIntrinsics, true ); ++define_pd_global(bool, PreferInterpreterNativeStubs, false); ++define_pd_global(bool, ProfileTraps, false); ++define_pd_global(bool, UseOnStackReplacement, true ); ++define_pd_global(bool, TieredCompilation, false); ++define_pd_global(intx, CompileThreshold, 1500 ); + -+ // helper functions which checks for overflow and sets bailout if it -+ // occurs. Always returns a valid embeddable pointer but in the -+ // bailout case the pointer won't be to unique storage. -+ address float_constant(float f); -+ address double_constant(double d); ++define_pd_global(intx, OnStackReplacePercentage, 933 ); ++define_pd_global(intx, NewSizeThreadIncrease, 4*K ); ++define_pd_global(intx, InitialCodeCacheSize, 160*K); ++define_pd_global(intx, ReservedCodeCacheSize, 32*M ); ++define_pd_global(intx, NonProfiledCodeHeapSize, 13*M ); ++define_pd_global(intx, ProfiledCodeHeapSize, 14*M ); ++define_pd_global(intx, NonNMethodCodeHeapSize, 5*M ); ++define_pd_global(bool, ProfileInterpreter, false); ++define_pd_global(intx, CodeCacheExpansionSize, 32*K ); ++define_pd_global(uintx, CodeCacheMinBlockLength, 1); ++define_pd_global(uintx, CodeCacheMinimumUseSpace, 400*K); ++define_pd_global(bool, NeverActAsServerClassMachine, true ); ++define_pd_global(uint64_t,MaxRAM, 1ULL*G); ++define_pd_global(bool, CICompileOSR, true ); ++#endif // !COMPILER2 ++define_pd_global(bool, UseTypeProfile, false); + -+ address int_constant(jlong n); ++define_pd_global(bool, OptimizeSinglePrecision, true ); ++define_pd_global(bool, CSEArrayLength, false); ++define_pd_global(bool, TwoOperandLIRForm, false ); + -+ bool is_literal_address(LIR_Address* addr); ++#endif // CPU_LOONGARCH_C1_GLOBALS_LOONGARCH_HPP +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/c1_LinearScan_loongarch_64.cpp b/src/hotspot/cpu/loongarch/c1_LinearScan_loongarch_64.cpp +--- a/src/hotspot/cpu/loongarch/c1_LinearScan_loongarch_64.cpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/loongarch/c1_LinearScan_loongarch_64.cpp 2024-01-31 14:01:11.597428831 +0800 +@@ -0,0 +1,33 @@ ++/* ++ * Copyright (c) 2005, 2011, Oracle and/or its affiliates. All rights reserved. All rights reserved. ++ * Copyright (c) 2021, Loongson Technology. All rights reserved. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ * ++ */ + -+ // Ensure we have a valid Address (base+offset) to a stack-slot. -+ Address stack_slot_address(int index, uint shift, int adjust = 0); ++#include "precompiled.hpp" ++#include "c1/c1_Instruction.hpp" ++#include "c1/c1_LinearScan.hpp" ++#include "utilities/bitMap.inline.hpp" + -+ // Record the type of the receiver in ReceiverTypeData -+ void type_profile_helper(Register mdo, ciMethodData *md, ciProfileData *data, -+ Register recv, Label* update_done); -+ void add_debug_info_for_branch(address adr, CodeEmitInfo* info); ++void LinearScan::allocate_fpu_stack() { ++ // No FPU stack on LoongArch64 ++} +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/c1_LinearScan_loongarch.hpp b/src/hotspot/cpu/loongarch/c1_LinearScan_loongarch.hpp +--- a/src/hotspot/cpu/loongarch/c1_LinearScan_loongarch.hpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/loongarch/c1_LinearScan_loongarch.hpp 2024-01-31 14:01:11.597428831 +0800 +@@ -0,0 +1,70 @@ ++/* ++ * Copyright (c) 2005, 2021, Oracle and/or its affiliates. All rights reserved. ++ * Copyright (c) 2021, Loongson Technology. All rights reserved. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ * ++ */ + -+ void casw(Register addr, Register newval, Register cmpval, bool sign); -+ void casl(Register addr, Register newval, Register cmpval); ++#ifndef CPU_LOONGARCH_C1_LINEARSCAN_LOONGARCH_HPP ++#define CPU_LOONGARCH_C1_LINEARSCAN_LOONGARCH_HPP + -+ void poll_for_safepoint(relocInfo::relocType rtype, CodeEmitInfo* info = NULL); ++inline bool LinearScan::is_processed_reg_num(int reg_num) { ++ return reg_num <= FrameMap::last_cpu_reg() || reg_num >= pd_nof_cpu_regs_frame_map; ++} + -+ static const int max_tableswitches = 20; -+ struct tableswitch switches[max_tableswitches]; -+ int tableswitch_count; ++inline int LinearScan::num_physical_regs(BasicType type) { ++ return 1; ++} + -+ void init() { tableswitch_count = 0; } ++inline bool LinearScan::requires_adjacent_regs(BasicType type) { ++ return false; ++} + -+ void deoptimize_trap(CodeEmitInfo *info); ++inline bool LinearScan::is_caller_save(int assigned_reg) { ++ assert(assigned_reg >= 0 && assigned_reg < nof_regs, "should call this only for registers"); ++ if (assigned_reg < pd_first_callee_saved_reg) ++ return true; ++ if (assigned_reg > pd_last_callee_saved_reg && assigned_reg < pd_first_callee_saved_fpu_reg) ++ return true; ++ if (assigned_reg > pd_last_callee_saved_fpu_reg && assigned_reg < pd_last_fpu_reg) ++ return true; ++ return false; ++} + -+ enum { -+ // call stub: CompiledStaticCall::to_interp_stub_size() + -+ // CompiledStaticCall::to_trampoline_stub_size() -+ _call_stub_size = 13 * NativeInstruction::nop_instruction_size, -+ _exception_handler_size = DEBUG_ONLY(1*K) NOT_DEBUG(175), -+ _deopt_handler_size = 7 * NativeInstruction::nop_instruction_size -+ }; ++inline void LinearScan::pd_add_temps(LIR_Op* op) {} + -+public: -+ void store_parameter(Register r, int offset_from_sp_in_words); -+ void store_parameter(jint c, int offset_from_sp_in_words); -+ void store_parameter(jobject c, int offset_from_sp_in_words); ++// Implementation of LinearScanWalker ++inline bool LinearScanWalker::pd_init_regs_for_alloc(Interval* cur) { ++ if (allocator()->gen()->is_vreg_flag_set(cur->reg_num(), LIRGenerator::callee_saved)) { ++ assert(cur->type() != T_FLOAT && cur->type() != T_DOUBLE, "cpu regs only"); ++ _first_reg = pd_first_callee_saved_reg; ++ _last_reg = pd_last_callee_saved_reg; ++ return true; ++ } else if (cur->type() == T_INT || cur->type() == T_LONG || cur->type() == T_OBJECT || ++ cur->type() == T_ADDRESS || cur->type() == T_METADATA) { ++ _first_reg = pd_first_cpu_reg; ++ _last_reg = pd_last_allocatable_cpu_reg; ++ return true; ++ } ++ return false; ++} + -+#endif // CPU_LOONGARCH_C1_LIRASSEMBLER_LOONGARCH_HPP -diff --git a/src/hotspot/cpu/loongarch/c1_LIRAssembler_loongarch_64.cpp b/src/hotspot/cpu/loongarch/c1_LIRAssembler_loongarch_64.cpp -new file mode 100644 -index 00000000000..2e4fbc1ecc0 ---- /dev/null -+++ b/src/hotspot/cpu/loongarch/c1_LIRAssembler_loongarch_64.cpp -@@ -0,0 +1,3382 @@ ++#endif // CPU_LOONGARCH_C1_LINEARSCAN_LOONGARCH_HPP +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/c1_LIRAssembler_loongarch_64.cpp b/src/hotspot/cpu/loongarch/c1_LIRAssembler_loongarch_64.cpp +--- a/src/hotspot/cpu/loongarch/c1_LIRAssembler_loongarch_64.cpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/loongarch/c1_LIRAssembler_loongarch_64.cpp 2024-01-31 14:01:11.597428831 +0800 +@@ -0,0 +1,3388 @@ +/* + * Copyright (c) 2000, 2021, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 2021, Loongson Technology. All rights reserved. @@ -6321,14 +6181,7 @@ index 00000000000..2e4fbc1ecc0 + __ ld_ptr(dest->as_register(), as_Address(from_addr)); + break; + case T_ADDRESS: -+ // FIXME: OMG this is a horrible kludge. Any offset from an -+ // address that matches klass_offset_in_bytes() will be loaded -+ // as a word, not a long. -+ if (UseCompressedClassPointers && addr->disp() == oopDesc::klass_offset_in_bytes()) { -+ __ ld_wu(dest->as_register(), as_Address(from_addr)); -+ } else { -+ __ ld_ptr(dest->as_register(), as_Address(from_addr)); -+ } ++ __ ld_ptr(dest->as_register(), as_Address(from_addr)); + break; + case T_INT: + __ ld_w(dest->as_register(), as_Address(from_addr)); @@ -6361,10 +6214,6 @@ index 00000000000..2e4fbc1ecc0 + // Load barrier has not yet been applied, so ZGC can't verify the oop here + __ verify_oop(dest->as_register()); + } -+ } else if (type == T_ADDRESS && addr->disp() == oopDesc::klass_offset_in_bytes()) { -+ if (UseCompressedClassPointers) { -+ __ decode_klass_not_null(dest->as_register()); -+ } + } +} + @@ -6398,19 +6247,20 @@ index 00000000000..2e4fbc1ecc0 +#ifdef ASSERT + assert(op->block() == NULL || op->block()->label() == op->label(), "wrong label"); + if (op->block() != NULL) _branch_target_blocks.append(op->block()); -+ assert(op->cond() == lir_cond_always, "must be"); +#endif + -+ if (op->info() != NULL) -+ add_debug_info_for_branch(op->info()); ++ if (op->cond() == lir_cond_always) { ++ if (op->info() != NULL) ++ add_debug_info_for_branch(op->info()); + -+ __ b_far(*(op->label())); ++ __ b_far(*(op->label())); ++ } else { ++ emit_cmp_branch(op); ++ } +} + -+void LIR_Assembler::emit_opCmpBranch(LIR_OpCmpBranch* op) { ++void LIR_Assembler::emit_cmp_branch(LIR_OpBranch* op) { +#ifdef ASSERT -+ assert(op->block() == NULL || op->block()->label() == op->label(), "wrong label"); -+ if (op->block() != NULL) _branch_target_blocks.append(op->block()); + if (op->ublock() != NULL) _branch_target_blocks.append(op->ublock()); +#endif + @@ -6426,7 +6276,7 @@ index 00000000000..2e4fbc1ecc0 + LIR_Opr opr2 = op->in_opr2(); + assert(op->condition() != lir_cond_always, "must be"); + -+ if (op->code() == lir_cmp_float_branch) { ++ if (op->code() == lir_cond_float_branch) { + bool is_unordered = (op->ublock() == op->block()); + if (opr1->is_single_fpu()) { + FloatRegister reg1 = opr1->as_float_reg(); @@ -6982,12 +6832,16 @@ index 00000000000..2e4fbc1ecc0 + +void LIR_Assembler::casw(Register addr, Register newval, Register cmpval, bool sign) { + __ cmpxchg32(Address(addr, 0), cmpval, newval, SCR1, sign, -+ /* retold */ false, /* barrier */ true, /* weak */ false, /* exchage */ false); ++ /* retold */ false, /* acquire */ true, /* weak */ false, /* exchange */ false); ++ // LA SC equals store-conditional dbar, so no need AnyAny after CAS. ++ //__ membar(__ AnyAny); +} + +void LIR_Assembler::casl(Register addr, Register newval, Register cmpval) { + __ cmpxchg(Address(addr, 0), cmpval, newval, SCR1, -+ /* retold */ false, /* barrier */ true, /* weak */ false, /* exchage */ false); ++ /* retold */ false, /* acquire */ true, /* weak */ false, /* exchange */ false); ++ // LA SC equals store-conditional dbar, so no need AnyAny after CAS. ++ //__ membar(__ AnyAny); +} + +void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) { @@ -7024,13 +6878,8 @@ index 00000000000..2e4fbc1ecc0 + } +} + -+void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, -+ LIR_Opr result, BasicType type) { -+ Unimplemented(); -+} -+ -+void LIR_Assembler::cmp_cmove(LIR_Condition condition, LIR_Opr left, LIR_Opr right, -+ LIR_Opr src1, LIR_Opr src2, LIR_Opr result, BasicType type) { ++void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr src1, LIR_Opr src2, LIR_Opr result, BasicType type, ++ LIR_Opr left, LIR_Opr right) { + assert(result->is_single_cpu() || result->is_double_cpu(), "expect single register for result"); + assert(left->is_single_cpu() || left->is_double_cpu(), "must be"); + Register regd = (result->type() == T_LONG) ? result->as_register_lo() : result->as_register(); @@ -8311,6 +8160,23 @@ index 00000000000..2e4fbc1ecc0 + __ bind(*op->stub()->continuation()); +} + ++void LIR_Assembler::emit_load_klass(LIR_OpLoadKlass* op) { ++ Register obj = op->obj()->as_pointer_register(); ++ Register result = op->result_opr()->as_pointer_register(); ++ ++ CodeEmitInfo* info = op->info(); ++ if (info != NULL) { ++ add_debug_info_for_null_check_here(info); ++ } ++ ++ if (UseCompressedClassPointers) { ++ __ ld_wu(result, obj, oopDesc::klass_offset_in_bytes()); ++ __ decode_klass_not_null(result); ++ } else { ++ __ ld_ptr(result, obj, oopDesc::klass_offset_in_bytes()); ++ } ++} ++ +void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) { + ciMethod* method = op->profiled_method(); + ciMethod* callee = op->profiled_callee(); @@ -8811,12 +8677,98 @@ index 00000000000..2e4fbc1ecc0 +} + +#undef __ -diff --git a/src/hotspot/cpu/loongarch/c1_LIRGenerator_loongarch_64.cpp b/src/hotspot/cpu/loongarch/c1_LIRGenerator_loongarch_64.cpp -new file mode 100644 -index 00000000000..a346700ed36 ---- /dev/null -+++ b/src/hotspot/cpu/loongarch/c1_LIRGenerator_loongarch_64.cpp -@@ -0,0 +1,1397 @@ +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/c1_LIRAssembler_loongarch.hpp b/src/hotspot/cpu/loongarch/c1_LIRAssembler_loongarch.hpp +--- a/src/hotspot/cpu/loongarch/c1_LIRAssembler_loongarch.hpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/loongarch/c1_LIRAssembler_loongarch.hpp 2024-01-31 14:01:11.597428831 +0800 +@@ -0,0 +1,84 @@ ++/* ++ * Copyright (c) 2000, 2021, Oracle and/or its affiliates. All rights reserved. ++ * Copyright (c) 2021, Loongson Technology. All rights reserved. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ * ++ */ ++ ++#ifndef CPU_LOONGARCH_C1_LIRASSEMBLER_LOONGARCH_HPP ++#define CPU_LOONGARCH_C1_LIRASSEMBLER_LOONGARCH_HPP ++ ++// ArrayCopyStub needs access to bailout ++friend class ArrayCopyStub; ++ ++ private: ++ int array_element_size(BasicType type) const; ++ ++ void arith_fpu_implementation(LIR_Code code, int left_index, int right_index, ++ int dest_index, bool pop_fpu_stack); ++ ++ // helper functions which checks for overflow and sets bailout if it ++ // occurs. Always returns a valid embeddable pointer but in the ++ // bailout case the pointer won't be to unique storage. ++ address float_constant(float f); ++ address double_constant(double d); ++ ++ address int_constant(jlong n); ++ ++ bool is_literal_address(LIR_Address* addr); ++ ++ // Ensure we have a valid Address (base+offset) to a stack-slot. ++ Address stack_slot_address(int index, uint shift, int adjust = 0); ++ ++ // Record the type of the receiver in ReceiverTypeData ++ void type_profile_helper(Register mdo, ciMethodData *md, ciProfileData *data, ++ Register recv, Label* update_done); ++ void add_debug_info_for_branch(address adr, CodeEmitInfo* info); ++ ++ void casw(Register addr, Register newval, Register cmpval, bool sign); ++ void casl(Register addr, Register newval, Register cmpval); ++ ++ void poll_for_safepoint(relocInfo::relocType rtype, CodeEmitInfo* info = NULL); ++ ++ static const int max_tableswitches = 20; ++ struct tableswitch switches[max_tableswitches]; ++ int tableswitch_count; ++ ++ void init() { tableswitch_count = 0; } ++ ++ void deoptimize_trap(CodeEmitInfo *info); ++ ++ void emit_cmp_branch(LIR_OpBranch* op); ++ ++ enum { ++ // call stub: CompiledStaticCall::to_interp_stub_size() + ++ // CompiledStaticCall::to_trampoline_stub_size() ++ _call_stub_size = 13 * NativeInstruction::nop_instruction_size, ++ _exception_handler_size = DEBUG_ONLY(1*K) NOT_DEBUG(175), ++ _deopt_handler_size = 7 * NativeInstruction::nop_instruction_size ++ }; ++ ++public: ++ void store_parameter(Register r, int offset_from_sp_in_words); ++ void store_parameter(jint c, int offset_from_sp_in_words); ++ void store_parameter(jobject c, int offset_from_sp_in_words); ++ ++#endif // CPU_LOONGARCH_C1_LIRASSEMBLER_LOONGARCH_HPP +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/c1_LIRGenerator_loongarch_64.cpp b/src/hotspot/cpu/loongarch/c1_LIRGenerator_loongarch_64.cpp +--- a/src/hotspot/cpu/loongarch/c1_LIRGenerator_loongarch_64.cpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/loongarch/c1_LIRGenerator_loongarch_64.cpp 2024-01-31 14:01:11.597428831 +0800 +@@ -0,0 +1,1384 @@ +/* + * Copyright (c) 2005, 2021, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 2021, 2022, Loongson Technology. All rights reserved. @@ -9079,32 +9031,18 @@ index 00000000000..a346700ed36 + __ store(reg, addr); +} + -+template -+void LIRGenerator::cmp_mem_int_branch(LIR_Condition condition, LIR_Opr base, -+ int disp, int c, T tgt, CodeEmitInfo* info) { ++void LIRGenerator::cmp_mem_int(LIR_Condition condition, LIR_Opr base, int disp, int c, CodeEmitInfo* info) { + LIR_Opr reg = new_register(T_INT); + __ load(generate_address(base, disp, T_INT), reg, info); -+ __ cmp_branch(condition, reg, LIR_OprFact::intConst(c), tgt); ++ __ cmp(condition, reg, LIR_OprFact::intConst(c)); +} + -+// Explicit instantiation for all supported types. -+template void LIRGenerator::cmp_mem_int_branch(LIR_Condition, LIR_Opr, int, int, Label*, CodeEmitInfo*); -+template void LIRGenerator::cmp_mem_int_branch(LIR_Condition, LIR_Opr, int, int, BlockBegin*, CodeEmitInfo*); -+template void LIRGenerator::cmp_mem_int_branch(LIR_Condition, LIR_Opr, int, int, CodeStub*, CodeEmitInfo*); -+ -+template -+void LIRGenerator::cmp_reg_mem_branch(LIR_Condition condition, LIR_Opr reg, LIR_Opr base, -+ int disp, BasicType type, T tgt, CodeEmitInfo* info) { ++void LIRGenerator::cmp_reg_mem(LIR_Condition condition, LIR_Opr reg, LIR_Opr base, int disp, BasicType type, CodeEmitInfo* info) { + LIR_Opr reg1 = new_register(T_INT); + __ load(generate_address(base, disp, type), reg1, info); -+ __ cmp_branch(condition, reg, reg1, tgt); ++ __ cmp(condition, reg, reg1); +} + -+// Explicit instantiation for all supported types. -+template void LIRGenerator::cmp_reg_mem_branch(LIR_Condition, LIR_Opr, LIR_Opr, int, BasicType, Label*, CodeEmitInfo*); -+template void LIRGenerator::cmp_reg_mem_branch(LIR_Condition, LIR_Opr, LIR_Opr, int, BasicType, BlockBegin*, CodeEmitInfo*); -+template void LIRGenerator::cmp_reg_mem_branch(LIR_Condition, LIR_Opr, LIR_Opr, int, BasicType, CodeStub*, CodeEmitInfo*); -+ +bool LIRGenerator::strength_reduce_multiply(LIR_Opr left, jint c, LIR_Opr result, LIR_Opr tmp) { + if (is_power_of_2(c - 1)) { + __ shift_left(left, exact_log2(c - 1), tmp); @@ -9260,8 +9198,8 @@ index 00000000000..a346700ed36 + } + if (need_zero_check) { + CodeEmitInfo* info = state_for(x); -+ CodeStub* stub = new DivByZeroStub(info); -+ __ cmp_branch(lir_cond_equal, right.result(), LIR_OprFact::longConst(0), stub); ++ __ cmp(lir_cond_equal, right.result(), LIR_OprFact::longConst(0)); ++ __ branch(lir_cond_equal, new DivByZeroStub(info)); + } + + rlock_result(x); @@ -9331,8 +9269,8 @@ index 00000000000..a346700ed36 + } + if (need_zero_check) { + CodeEmitInfo* info = state_for(x); -+ CodeStub* stub = new DivByZeroStub(info); -+ __ cmp_branch(lir_cond_equal, right_arg->result(), LIR_OprFact::longConst(0), stub); ++ __ cmp(lir_cond_equal, right_arg->result(), LIR_OprFact::longConst(0)); ++ __ branch(lir_cond_equal, new DivByZeroStub(info)); + } + + LIR_Opr ill = LIR_OprFact::illegalOpr; @@ -10178,13 +10116,14 @@ index 00000000000..a346700ed36 + __ safepoint(LIR_OprFact::illegalOpr, state_for(x, x->state_before())); + } + ++ __ cmp(lir_cond(cond), left, right); + // Generate branch profiling. Profiling code doesn't kill flags. -+ profile_branch(x, cond, left, right); ++ profile_branch(x, cond); + move_to_phi(x->state()); + if (x->x()->type()->is_float_kind()) { -+ __ cmp_branch(lir_cond(cond), left, right, x->tsux(), x->usux()); ++ __ branch(lir_cond(cond), x->tsux(), x->usux()); + } else { -+ __ cmp_branch(lir_cond(cond), left, right, x->tsux()); ++ __ branch(lir_cond(cond), x->tsux()); + } + assert(x->default_sux() == x->fsux(), "wrong destination above"); + __ jump(x->default_sux()); @@ -10214,12 +10153,10 @@ index 00000000000..a346700ed36 + } + __ volatile_load_mem_reg(address, result, info); +} -diff --git a/src/hotspot/cpu/loongarch/c1_LIR_loongarch_64.cpp b/src/hotspot/cpu/loongarch/c1_LIR_loongarch_64.cpp -new file mode 100644 -index 00000000000..127be89865e ---- /dev/null -+++ b/src/hotspot/cpu/loongarch/c1_LIR_loongarch_64.cpp -@@ -0,0 +1,75 @@ +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/c1_LIR_loongarch_64.cpp b/src/hotspot/cpu/loongarch/c1_LIR_loongarch_64.cpp +--- a/src/hotspot/cpu/loongarch/c1_LIR_loongarch_64.cpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/loongarch/c1_LIR_loongarch_64.cpp 2024-01-31 14:01:11.597428831 +0800 +@@ -0,0 +1,57 @@ +/* + * Copyright (c) 2016, 2021, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 2021, Loongson Technology. All rights reserved. @@ -10277,262 +10214,9 @@ index 00000000000..127be89865e + "wrong type for addresses"); +} +#endif // PRODUCT -+ -+template -+void LIR_List::cmp_branch(LIR_Condition condition, LIR_Opr left, LIR_Opr right, T tgt, CodeEmitInfo* info) { -+ append(new LIR_OpCmpBranch(condition, left, right, tgt, info)); -+} -+ -+// Explicit instantiation for all supported types. -+template void LIR_List::cmp_branch(LIR_Condition, LIR_Opr, LIR_Opr, Label*, CodeEmitInfo*); -+template void LIR_List::cmp_branch(LIR_Condition, LIR_Opr, LIR_Opr, BlockBegin*, CodeEmitInfo*); -+template void LIR_List::cmp_branch(LIR_Condition, LIR_Opr, LIR_Opr, CodeStub*, CodeEmitInfo*); -+ -+void LIR_List::cmp_branch(LIR_Condition condition, LIR_Opr left, LIR_Opr right, BlockBegin* block, BlockBegin* unordered) { -+ append(new LIR_OpCmpBranch(condition, left, right, block, unordered)); -+} -+ -+void LIR_List::cmp_cmove(LIR_Condition condition, LIR_Opr left, LIR_Opr right, LIR_Opr src1, LIR_Opr src2, LIR_Opr dst, BasicType type) { -+ append(new LIR_Op4(lir_cmp_cmove, condition, left, right, src1, src2, dst, type)); -+} -diff --git a/src/hotspot/cpu/loongarch/c1_LinearScan_loongarch.hpp b/src/hotspot/cpu/loongarch/c1_LinearScan_loongarch.hpp -new file mode 100644 -index 00000000000..f15dacafeba ---- /dev/null -+++ b/src/hotspot/cpu/loongarch/c1_LinearScan_loongarch.hpp -@@ -0,0 +1,70 @@ -+/* -+ * Copyright (c) 2005, 2021, Oracle and/or its affiliates. All rights reserved. -+ * Copyright (c) 2021, Loongson Technology. All rights reserved. -+ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. -+ * -+ * This code is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 only, as -+ * published by the Free Software Foundation. -+ * -+ * This code is distributed in the hope that it will be useful, but WITHOUT -+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -+ * version 2 for more details (a copy is included in the LICENSE file that -+ * accompanied this code). -+ * -+ * You should have received a copy of the GNU General Public License version -+ * 2 along with this work; if not, write to the Free Software Foundation, -+ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. -+ * -+ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA -+ * or visit www.oracle.com if you need additional information or have any -+ * questions. -+ * -+ */ -+ -+#ifndef CPU_LOONGARCH_C1_LINEARSCAN_LOONGARCH_HPP -+#define CPU_LOONGARCH_C1_LINEARSCAN_LOONGARCH_HPP -+ -+inline bool LinearScan::is_processed_reg_num(int reg_num) { -+ return reg_num <= FrameMap::last_cpu_reg() || reg_num >= pd_nof_cpu_regs_frame_map; -+} -+ -+inline int LinearScan::num_physical_regs(BasicType type) { -+ return 1; -+} -+ -+inline bool LinearScan::requires_adjacent_regs(BasicType type) { -+ return false; -+} -+ -+inline bool LinearScan::is_caller_save(int assigned_reg) { -+ assert(assigned_reg >= 0 && assigned_reg < nof_regs, "should call this only for registers"); -+ if (assigned_reg < pd_first_callee_saved_reg) -+ return true; -+ if (assigned_reg > pd_last_callee_saved_reg && assigned_reg < pd_first_callee_saved_fpu_reg) -+ return true; -+ if (assigned_reg > pd_last_callee_saved_fpu_reg && assigned_reg < pd_last_fpu_reg) -+ return true; -+ return false; -+} -+ -+inline void LinearScan::pd_add_temps(LIR_Op* op) {} -+ -+// Implementation of LinearScanWalker -+inline bool LinearScanWalker::pd_init_regs_for_alloc(Interval* cur) { -+ if (allocator()->gen()->is_vreg_flag_set(cur->reg_num(), LIRGenerator::callee_saved)) { -+ assert(cur->type() != T_FLOAT && cur->type() != T_DOUBLE, "cpu regs only"); -+ _first_reg = pd_first_callee_saved_reg; -+ _last_reg = pd_last_callee_saved_reg; -+ return true; -+ } else if (cur->type() == T_INT || cur->type() == T_LONG || cur->type() == T_OBJECT || -+ cur->type() == T_ADDRESS || cur->type() == T_METADATA) { -+ _first_reg = pd_first_cpu_reg; -+ _last_reg = pd_last_allocatable_cpu_reg; -+ return true; -+ } -+ return false; -+} -+ -+#endif // CPU_LOONGARCH_C1_LINEARSCAN_LOONGARCH_HPP -diff --git a/src/hotspot/cpu/loongarch/c1_LinearScan_loongarch_64.cpp b/src/hotspot/cpu/loongarch/c1_LinearScan_loongarch_64.cpp -new file mode 100644 -index 00000000000..219b2e3671c ---- /dev/null -+++ b/src/hotspot/cpu/loongarch/c1_LinearScan_loongarch_64.cpp -@@ -0,0 +1,33 @@ -+/* -+ * Copyright (c) 2005, 2011, Oracle and/or its affiliates. All rights reserved. All rights reserved. -+ * Copyright (c) 2021, Loongson Technology. All rights reserved. -+ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. -+ * -+ * This code is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 only, as -+ * published by the Free Software Foundation. -+ * -+ * This code is distributed in the hope that it will be useful, but WITHOUT -+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -+ * version 2 for more details (a copy is included in the LICENSE file that -+ * accompanied this code). -+ * -+ * You should have received a copy of the GNU General Public License version -+ * 2 along with this work; if not, write to the Free Software Foundation, -+ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. -+ * -+ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA -+ * or visit www.oracle.com if you need additional information or have any -+ * questions. -+ * -+ */ -+ -+#include "precompiled.hpp" -+#include "c1/c1_Instruction.hpp" -+#include "c1/c1_LinearScan.hpp" -+#include "utilities/bitMap.inline.hpp" -+ -+void LinearScan::allocate_fpu_stack() { -+ // No FPU stack on LoongArch64 -+} -diff --git a/src/hotspot/cpu/loongarch/c1_MacroAssembler_loongarch.hpp b/src/hotspot/cpu/loongarch/c1_MacroAssembler_loongarch.hpp -new file mode 100644 -index 00000000000..38ff4c58369 ---- /dev/null -+++ b/src/hotspot/cpu/loongarch/c1_MacroAssembler_loongarch.hpp -@@ -0,0 +1,112 @@ -+/* -+ * Copyright (c) 1999, 2021, Oracle and/or its affiliates. All rights reserved. -+ * Copyright (c) 2021, Loongson Technology. All rights reserved. -+ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. -+ * -+ * This code is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 only, as -+ * published by the Free Software Foundation. -+ * -+ * This code is distributed in the hope that it will be useful, but WITHOUT -+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -+ * version 2 for more details (a copy is included in the LICENSE file that -+ * accompanied this code). -+ * -+ * You should have received a copy of the GNU General Public License version -+ * 2 along with this work; if not, write to the Free Software Foundation, -+ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. -+ * -+ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA -+ * or visit www.oracle.com if you need additional information or have any -+ * questions. -+ * -+ */ -+ -+#ifndef CPU_LOONGARCH_C1_MACROASSEMBLER_LOONGARCH_HPP -+#define CPU_LOONGARCH_C1_MACROASSEMBLER_LOONGARCH_HPP -+ -+using MacroAssembler::build_frame; -+using MacroAssembler::null_check; -+ -+// C1_MacroAssembler contains high-level macros for C1 -+ -+ private: -+ int _rsp_offset; // track rsp changes -+ // initialization -+ void pd_init() { _rsp_offset = 0; } -+ -+ public: -+ void try_allocate( -+ Register obj, // result: pointer to object after successful allocation -+ Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise -+ int con_size_in_bytes, // object size in bytes if known at compile time -+ Register t1, // temp register -+ Register t2, // temp register -+ Label& slow_case // continuation point if fast allocation fails -+ ); -+ -+ void initialize_header(Register obj, Register klass, Register len, Register t1, Register t2); -+ void initialize_body(Register obj, Register len_in_bytes, int hdr_size_in_bytes, Register t1, Register t2); -+ -+ // locking -+ // hdr : must be A0, contents destroyed -+ // obj : must point to the object to lock, contents preserved -+ // disp_hdr: must point to the displaced header location, contents preserved -+ // scratch : scratch register, contents destroyed -+ // returns code offset at which to add null check debug information -+ int lock_object (Register swap, Register obj, Register disp_hdr, Register scratch, Label& slow_case); -+ -+ // unlocking -+ // hdr : contents destroyed -+ // obj : must point to the object to lock, contents preserved -+ // disp_hdr: must be A0 & must point to the displaced header location, contents destroyed -+ void unlock_object(Register swap, Register obj, Register lock, Label& slow_case); -+ -+ void initialize_object( -+ Register obj, // result: pointer to object after successful allocation -+ Register klass, // object klass -+ Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise -+ int con_size_in_bytes, // object size in bytes if known at compile time -+ Register t1, // temp register -+ Register t2, // temp register -+ bool is_tlab_allocated // the object was allocated in a TLAB; relevant for the implementation of ZeroTLAB -+ ); -+ -+ // allocation of fixed-size objects -+ // (can also be used to allocate fixed-size arrays, by setting -+ // hdr_size correctly and storing the array length afterwards) -+ // obj : will contain pointer to allocated object -+ // t1, t2 : scratch registers - contents destroyed -+ // header_size: size of object header in words -+ // object_size: total size of object in words -+ // slow_case : exit to slow case implementation if fast allocation fails -+ void allocate_object(Register obj, Register t1, Register t2, int header_size, -+ int object_size, Register klass, Label& slow_case); -+ -+ enum { -+ max_array_allocation_length = 0x00FFFFFF -+ }; -+ -+ // allocation of arrays -+ // obj : will contain pointer to allocated object -+ // len : array length in number of elements -+ // t : scratch register - contents destroyed -+ // header_size: size of object header in words -+ // f : element scale factor -+ // slow_case : exit to slow case implementation if fast allocation fails -+ void allocate_array(Register obj, Register len, Register t, Register t2, int header_size, -+ int f, Register klass, Label& slow_case); -+ -+ int rsp_offset() const { return _rsp_offset; } -+ void set_rsp_offset(int n) { _rsp_offset = n; } -+ -+ void invalidate_registers(bool inv_a0, bool inv_s0, bool inv_a2, bool inv_a3, -+ bool inv_a4, bool inv_a5) PRODUCT_RETURN; -+ -+ // This platform only uses signal-based null checks. The Label is not needed. -+ void null_check(Register r, Label *Lnull = NULL) { MacroAssembler::null_check(r); } -+ -+ void load_parameter(int offset_in_words, Register reg); -+ -+#endif // CPU_LOONGARCH_C1_MACROASSEMBLER_LOONGARCH_HPP -diff --git a/src/hotspot/cpu/loongarch/c1_MacroAssembler_loongarch_64.cpp b/src/hotspot/cpu/loongarch/c1_MacroAssembler_loongarch_64.cpp -new file mode 100644 -index 00000000000..56c6281d415 ---- /dev/null -+++ b/src/hotspot/cpu/loongarch/c1_MacroAssembler_loongarch_64.cpp +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/c1_MacroAssembler_loongarch_64.cpp b/src/hotspot/cpu/loongarch/c1_MacroAssembler_loongarch_64.cpp +--- a/src/hotspot/cpu/loongarch/c1_MacroAssembler_loongarch_64.cpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/loongarch/c1_MacroAssembler_loongarch_64.cpp 2024-01-31 14:01:11.597428831 +0800 @@ -0,0 +1,365 @@ +/* + * Copyright (c) 1999, 2021, Oracle and/or its affiliates. All rights reserved. @@ -10622,7 +10306,7 @@ index 00000000000..56c6281d415 + // displaced header address in the object header - if it is not the same, get the + // object header instead + lea(SCR2, Address(obj, hdr_offset)); -+ cmpxchg(Address(SCR2, 0), hdr, disp_hdr, SCR1, true, false, done); ++ cmpxchg(Address(SCR2, 0), hdr, disp_hdr, SCR1, true, true /* acquire */, done); + // if the object header was the same, we're done + // if the object header was not the same, it is now in the hdr register + // => test if it is a stack pointer into the same stack (recursive locking), i.e.: @@ -10682,9 +10366,9 @@ index 00000000000..56c6281d415 + // we do unlocking via runtime call + if (hdr_offset) { + lea(SCR1, Address(obj, hdr_offset)); -+ cmpxchg(Address(SCR1, 0), disp_hdr, hdr, SCR2, false, false, done, &slow_case); ++ cmpxchg(Address(SCR1, 0), disp_hdr, hdr, SCR2, false, true /* acquire */, done, &slow_case); + } else { -+ cmpxchg(Address(obj, 0), disp_hdr, hdr, SCR2, false, false, done, &slow_case); ++ cmpxchg(Address(obj, 0), disp_hdr, hdr, SCR2, false, true /* acquire */, done, &slow_case); + } + // done + bind(done); @@ -10899,11 +10583,125 @@ index 00000000000..56c6281d415 +#endif +} +#endif // ifndef PRODUCT -diff --git a/src/hotspot/cpu/loongarch/c1_Runtime1_loongarch_64.cpp b/src/hotspot/cpu/loongarch/c1_Runtime1_loongarch_64.cpp -new file mode 100644 -index 00000000000..87da18e294a ---- /dev/null -+++ b/src/hotspot/cpu/loongarch/c1_Runtime1_loongarch_64.cpp +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/c1_MacroAssembler_loongarch.hpp b/src/hotspot/cpu/loongarch/c1_MacroAssembler_loongarch.hpp +--- a/src/hotspot/cpu/loongarch/c1_MacroAssembler_loongarch.hpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/loongarch/c1_MacroAssembler_loongarch.hpp 2024-01-31 14:01:11.597428831 +0800 +@@ -0,0 +1,112 @@ ++/* ++ * Copyright (c) 1999, 2021, Oracle and/or its affiliates. All rights reserved. ++ * Copyright (c) 2021, Loongson Technology. All rights reserved. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ * ++ */ ++ ++#ifndef CPU_LOONGARCH_C1_MACROASSEMBLER_LOONGARCH_HPP ++#define CPU_LOONGARCH_C1_MACROASSEMBLER_LOONGARCH_HPP ++ ++using MacroAssembler::build_frame; ++using MacroAssembler::null_check; ++ ++// C1_MacroAssembler contains high-level macros for C1 ++ ++ private: ++ int _rsp_offset; // track rsp changes ++ // initialization ++ void pd_init() { _rsp_offset = 0; } ++ ++ public: ++ void try_allocate( ++ Register obj, // result: pointer to object after successful allocation ++ Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise ++ int con_size_in_bytes, // object size in bytes if known at compile time ++ Register t1, // temp register ++ Register t2, // temp register ++ Label& slow_case // continuation point if fast allocation fails ++ ); ++ ++ void initialize_header(Register obj, Register klass, Register len, Register t1, Register t2); ++ void initialize_body(Register obj, Register len_in_bytes, int hdr_size_in_bytes, Register t1, Register t2); ++ ++ // locking ++ // hdr : must be A0, contents destroyed ++ // obj : must point to the object to lock, contents preserved ++ // disp_hdr: must point to the displaced header location, contents preserved ++ // scratch : scratch register, contents destroyed ++ // returns code offset at which to add null check debug information ++ int lock_object (Register swap, Register obj, Register disp_hdr, Register scratch, Label& slow_case); ++ ++ // unlocking ++ // hdr : contents destroyed ++ // obj : must point to the object to lock, contents preserved ++ // disp_hdr: must be A0 & must point to the displaced header location, contents destroyed ++ void unlock_object(Register swap, Register obj, Register lock, Label& slow_case); ++ ++ void initialize_object( ++ Register obj, // result: pointer to object after successful allocation ++ Register klass, // object klass ++ Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise ++ int con_size_in_bytes, // object size in bytes if known at compile time ++ Register t1, // temp register ++ Register t2, // temp register ++ bool is_tlab_allocated // the object was allocated in a TLAB; relevant for the implementation of ZeroTLAB ++ ); ++ ++ // allocation of fixed-size objects ++ // (can also be used to allocate fixed-size arrays, by setting ++ // hdr_size correctly and storing the array length afterwards) ++ // obj : will contain pointer to allocated object ++ // t1, t2 : scratch registers - contents destroyed ++ // header_size: size of object header in words ++ // object_size: total size of object in words ++ // slow_case : exit to slow case implementation if fast allocation fails ++ void allocate_object(Register obj, Register t1, Register t2, int header_size, ++ int object_size, Register klass, Label& slow_case); ++ ++ enum { ++ max_array_allocation_length = 0x00FFFFFF ++ }; ++ ++ // allocation of arrays ++ // obj : will contain pointer to allocated object ++ // len : array length in number of elements ++ // t : scratch register - contents destroyed ++ // header_size: size of object header in words ++ // f : element scale factor ++ // slow_case : exit to slow case implementation if fast allocation fails ++ void allocate_array(Register obj, Register len, Register t, Register t2, int header_size, ++ int f, Register klass, Label& slow_case); ++ ++ int rsp_offset() const { return _rsp_offset; } ++ void set_rsp_offset(int n) { _rsp_offset = n; } ++ ++ void invalidate_registers(bool inv_a0, bool inv_s0, bool inv_a2, bool inv_a3, ++ bool inv_a4, bool inv_a5) PRODUCT_RETURN; ++ ++ // This platform only uses signal-based null checks. The Label is not needed. ++ void null_check(Register r, Label *Lnull = NULL) { MacroAssembler::null_check(r); } ++ ++ void load_parameter(int offset_in_words, Register reg); ++ ++#endif // CPU_LOONGARCH_C1_MACROASSEMBLER_LOONGARCH_HPP +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/c1_Runtime1_loongarch_64.cpp b/src/hotspot/cpu/loongarch/c1_Runtime1_loongarch_64.cpp +--- a/src/hotspot/cpu/loongarch/c1_Runtime1_loongarch_64.cpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/loongarch/c1_Runtime1_loongarch_64.cpp 2024-01-31 14:01:11.597428831 +0800 @@ -0,0 +1,1148 @@ +/* + * Copyright (c) 1999, 2021, Oracle and/or its affiliates. All rights reserved. @@ -12053,15 +11851,13 @@ index 00000000000..87da18e294a + Unimplemented(); + return 0; +} -diff --git a/src/hotspot/cpu/loongarch/c1_globals_loongarch.hpp b/src/hotspot/cpu/loongarch/c1_globals_loongarch.hpp -new file mode 100644 -index 00000000000..ce84af28c9b ---- /dev/null -+++ b/src/hotspot/cpu/loongarch/c1_globals_loongarch.hpp -@@ -0,0 +1,65 @@ +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/c2_globals_loongarch.hpp b/src/hotspot/cpu/loongarch/c2_globals_loongarch.hpp +--- a/src/hotspot/cpu/loongarch/c2_globals_loongarch.hpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/loongarch/c2_globals_loongarch.hpp 2024-01-31 14:01:11.597428831 +0800 +@@ -0,0 +1,90 @@ +/* -+ * Copyright (c) 2000, 2021, Oracle and/or its affiliates. All rights reserved. -+ * Copyright (c) 2021, Loongson Technology. All rights reserved. ++ * Copyright (c) 2000, 2013, Oracle and/or its affiliates. All rights reserved. ++ * Copyright (c) 2015, 2022, Loongson Technology. All rights reserved. + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. + * + * This code is free software; you can redistribute it and/or modify it @@ -12084,55 +11880,119 @@ index 00000000000..ce84af28c9b + * + */ + -+#ifndef CPU_LOONGARCH_C1_GLOBALS_LOONGARCH_HPP -+#define CPU_LOONGARCH_C1_GLOBALS_LOONGARCH_HPP ++#ifndef CPU_LOONGARCH_C2_GLOBALS_LOONGARCH_HPP ++#define CPU_LOONGARCH_C2_GLOBALS_LOONGARCH_HPP + +#include "utilities/globalDefinitions.hpp" +#include "utilities/macros.hpp" + -+// Sets the default values for platform dependent flags used by the client compiler. -+// (see c1_globals.hpp) -+ -+#ifndef COMPILER2 -+define_pd_global(bool, BackgroundCompilation, true ); -+define_pd_global(bool, InlineIntrinsics, true ); ++// Sets the default values for platform dependent flags used by the server compiler. ++// (see c2_globals.hpp). Alpha-sorted. ++define_pd_global(bool, BackgroundCompilation, true); ++define_pd_global(bool, UseTLAB, true); ++define_pd_global(bool, ResizeTLAB, true); ++define_pd_global(bool, CICompileOSR, true); ++define_pd_global(bool, InlineIntrinsics, true); +define_pd_global(bool, PreferInterpreterNativeStubs, false); -+define_pd_global(bool, ProfileTraps, false); -+define_pd_global(bool, UseOnStackReplacement, true ); -+define_pd_global(bool, TieredCompilation, false); -+define_pd_global(intx, CompileThreshold, 1500 ); ++define_pd_global(bool, ProfileTraps, true); ++define_pd_global(bool, UseOnStackReplacement, true); ++define_pd_global(bool, ProfileInterpreter, true); ++define_pd_global(bool, TieredCompilation, true); ++define_pd_global(intx, CompileThreshold, 10000); ++define_pd_global(intx, BackEdgeThreshold, 100000); + -+define_pd_global(intx, OnStackReplacePercentage, 933 ); -+define_pd_global(intx, NewSizeThreadIncrease, 4*K ); -+define_pd_global(intx, InitialCodeCacheSize, 160*K); -+define_pd_global(intx, ReservedCodeCacheSize, 32*M ); -+define_pd_global(intx, NonProfiledCodeHeapSize, 13*M ); -+define_pd_global(intx, ProfiledCodeHeapSize, 14*M ); -+define_pd_global(intx, NonNMethodCodeHeapSize, 5*M ); -+define_pd_global(bool, ProfileInterpreter, false); -+define_pd_global(intx, CodeCacheExpansionSize, 32*K ); -+define_pd_global(uintx, CodeCacheMinBlockLength, 1); ++define_pd_global(intx, OnStackReplacePercentage, 140); ++define_pd_global(intx, ConditionalMoveLimit, 3); ++define_pd_global(intx, FLOATPRESSURE, 31); ++define_pd_global(intx, FreqInlineSize, 325); ++define_pd_global(intx, MinJumpTableSize, 10); ++define_pd_global(intx, INTPRESSURE, 23); ++define_pd_global(intx, InteriorEntryAlignment, 16); ++define_pd_global(intx, NewSizeThreadIncrease, ScaleForWordSize(4*K)); ++define_pd_global(intx, LoopUnrollLimit, 60); ++define_pd_global(intx, LoopPercentProfileLimit, 10); ++// InitialCodeCacheSize derived from specjbb2000 run. ++define_pd_global(intx, InitialCodeCacheSize, 2496*K); // Integral multiple of CodeCacheExpansionSize ++define_pd_global(intx, CodeCacheExpansionSize, 64*K); ++ ++// Ergonomics related flags ++define_pd_global(uint64_t,MaxRAM, 128ULL*G); ++define_pd_global(intx, RegisterCostAreaRatio, 16000); ++ ++// Peephole and CISC spilling both break the graph, and so makes the ++// scheduler sick. ++define_pd_global(bool, OptoPeephole, false); ++define_pd_global(bool, UseCISCSpill, false); ++define_pd_global(bool, OptoScheduling, false); ++define_pd_global(bool, OptoBundling, false); ++define_pd_global(bool, OptoRegScheduling, false); ++define_pd_global(bool, SuperWordLoopUnrollAnalysis, true); ++define_pd_global(bool, IdealizeClearArrayNode, true); ++ ++define_pd_global(intx, ReservedCodeCacheSize, 48*M); ++define_pd_global(intx, NonProfiledCodeHeapSize, 21*M); ++define_pd_global(intx, ProfiledCodeHeapSize, 22*M); ++define_pd_global(intx, NonNMethodCodeHeapSize, 5*M ); ++define_pd_global(uintx, CodeCacheMinBlockLength, 4); +define_pd_global(uintx, CodeCacheMinimumUseSpace, 400*K); -+define_pd_global(bool, NeverActAsServerClassMachine, true ); -+define_pd_global(uint64_t,MaxRAM, 1ULL*G); -+define_pd_global(bool, CICompileOSR, true ); -+#endif // !COMPILER2 -+define_pd_global(bool, UseTypeProfile, false); + -+define_pd_global(bool, OptimizeSinglePrecision, true ); -+define_pd_global(bool, CSEArrayLength, false); -+define_pd_global(bool, TwoOperandLIRForm, false ); ++define_pd_global(bool, TrapBasedRangeChecks, false); + -+#endif // CPU_LOONGARCH_C1_GLOBALS_LOONGARCH_HPP -diff --git a/src/hotspot/cpu/loongarch/c2_MacroAssembler_loongarch.cpp b/src/hotspot/cpu/loongarch/c2_MacroAssembler_loongarch.cpp -new file mode 100644 -index 00000000000..e3a01f1f25d ---- /dev/null -+++ b/src/hotspot/cpu/loongarch/c2_MacroAssembler_loongarch.cpp ++// Heap related flags ++define_pd_global(uintx,MetaspaceSize, ScaleForWordSize(16*M)); ++ ++// Ergonomics related flags ++define_pd_global(bool, NeverActAsServerClassMachine, false); ++ ++#endif // CPU_LOONGARCH_C2_GLOBALS_LOONGARCH_HPP +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/c2_init_loongarch.cpp b/src/hotspot/cpu/loongarch/c2_init_loongarch.cpp +--- a/src/hotspot/cpu/loongarch/c2_init_loongarch.cpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/loongarch/c2_init_loongarch.cpp 2024-01-31 14:01:11.597428831 +0800 +@@ -0,0 +1,37 @@ ++/* ++ * Copyright (c) 2000, 2010, Oracle and/or its affiliates. All rights reserved. ++ * Copyright (c) 2015, 2022, Loongson Technology. All rights reserved. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ * ++ */ ++ ++#include "precompiled.hpp" ++#include "opto/compile.hpp" ++#include "opto/node.hpp" ++ ++// processor dependent initialization for LoongArch ++ ++extern void reg_mask_init(); ++ ++void Compile::pd_compiler2_init() { ++ guarantee(CodeEntryAlignment >= InteriorEntryAlignment, "" ); ++ reg_mask_init(); ++} +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/c2_MacroAssembler_loongarch.cpp b/src/hotspot/cpu/loongarch/c2_MacroAssembler_loongarch.cpp +--- a/src/hotspot/cpu/loongarch/c2_MacroAssembler_loongarch.cpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/loongarch/c2_MacroAssembler_loongarch.cpp 2024-01-31 14:01:11.597428831 +0800 @@ -0,0 +1,1872 @@ +/* + * Copyright (c) 2020, Oracle and/or its affiliates. All rights reserved. -+ * Copyright (c) 2021, 2022, Loongson Technology. All rights reserved. ++ * Copyright (c) 2021, 2023, Loongson Technology. All rights reserved. + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. + * + * This code is free software; you can redistribute it and/or modify it @@ -12327,7 +12187,7 @@ index 00000000000..e3a01f1f25d + + if (PrintBiasedLockingStatistics) { + Label SUCC, FAIL; -+ cmpxchg(Address(objReg, 0), tmpReg, boxReg, scrReg, true, false, SUCC, &FAIL); // Updates tmpReg ++ cmpxchg(Address(objReg, 0), tmpReg, boxReg, scrReg, true, true /* acquire */, SUCC, &FAIL); // Updates tmpReg + bind(SUCC); + atomic_inc32((address)BiasedLocking::fast_path_entry_count_addr(), 1, AT, scrReg); + li(resReg, 1); @@ -12335,7 +12195,7 @@ index 00000000000..e3a01f1f25d + bind(FAIL); + } else { + // If cmpxchg is succ, then scrReg = 1 -+ cmpxchg(Address(objReg, 0), tmpReg, boxReg, scrReg, true, false, DONE_SET); // Updates tmpReg ++ cmpxchg(Address(objReg, 0), tmpReg, boxReg, scrReg, true, true /* acquire */, DONE_SET); // Updates tmpReg + } + + // Recursive locking @@ -12380,7 +12240,7 @@ index 00000000000..e3a01f1f25d +#endif + // It's inflated and appears unlocked + addi_d(tmpReg, tmpReg, ObjectMonitor::owner_offset_in_bytes() - 2); -+ cmpxchg(Address(tmpReg, 0), R0, TREG, scrReg, false, false); ++ cmpxchg(Address(tmpReg, 0), R0, TREG, scrReg, false, true /* acquire */); + // Intentional fall-through into DONE ... + + bind(DONE_SET); @@ -12499,14 +12359,14 @@ index 00000000000..e3a01f1f25d + move(AT, R0); + bnez(scrReg, DONE_SET); + -+ dbar(0); ++ membar(Assembler::Membar_mask_bits(LoadStore|StoreStore)); + st_d(R0, Address(tmpReg, ObjectMonitor::owner_offset_in_bytes() - 2)); + li(resReg, 1); + b(DONE); + + bind(Stacked); + ld_d(tmpReg, Address(boxReg, 0)); -+ cmpxchg(Address(objReg, 0), boxReg, tmpReg, AT, false, false); ++ cmpxchg(Address(objReg, 0), boxReg, tmpReg, AT, false, true /* acquire */); + + bind(DONE_SET); + move(resReg, AT); @@ -14002,11 +13862,9 @@ index 00000000000..e3a01f1f25d + Unimplemented(); + } +} -diff --git a/src/hotspot/cpu/loongarch/c2_MacroAssembler_loongarch.hpp b/src/hotspot/cpu/loongarch/c2_MacroAssembler_loongarch.hpp -new file mode 100644 -index 00000000000..2babade2e22 ---- /dev/null -+++ b/src/hotspot/cpu/loongarch/c2_MacroAssembler_loongarch.hpp +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/c2_MacroAssembler_loongarch.hpp b/src/hotspot/cpu/loongarch/c2_MacroAssembler_loongarch.hpp +--- a/src/hotspot/cpu/loongarch/c2_MacroAssembler_loongarch.hpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/loongarch/c2_MacroAssembler_loongarch.hpp 2024-01-31 14:01:11.597428831 +0800 @@ -0,0 +1,144 @@ +/* + * Copyright (c) 2020, Oracle and/or its affiliates. All rights reserved. @@ -14152,15 +14010,13 @@ index 00000000000..2babade2e22 + void reduce_ins_r(Register reg1, Register reg2, Register reg3, BasicType type, int opcode); + void reduce_ins_f(FloatRegister reg1, FloatRegister reg2, FloatRegister reg3, BasicType type, int opcode); +#endif // CPU_LOONGARCH_C2_MACROASSEMBLER_LOONGARCH_HPP -diff --git a/src/hotspot/cpu/loongarch/c2_globals_loongarch.hpp b/src/hotspot/cpu/loongarch/c2_globals_loongarch.hpp -new file mode 100644 -index 00000000000..0e40e2ca7cf ---- /dev/null -+++ b/src/hotspot/cpu/loongarch/c2_globals_loongarch.hpp -@@ -0,0 +1,90 @@ +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/c2_safepointPollStubTable_loongarch.cpp b/src/hotspot/cpu/loongarch/c2_safepointPollStubTable_loongarch.cpp +--- a/src/hotspot/cpu/loongarch/c2_safepointPollStubTable_loongarch.cpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/loongarch/c2_safepointPollStubTable_loongarch.cpp 2024-01-31 14:01:11.597428831 +0800 +@@ -0,0 +1,50 @@ +/* -+ * Copyright (c) 2000, 2013, Oracle and/or its affiliates. All rights reserved. -+ * Copyright (c) 2015, 2022, Loongson Technology. All rights reserved. ++ * Copyright (c) 2020, 2021, Oracle and/or its affiliates. All rights reserved. ++ * Copyright (c) 2021, Loongson Technology. All rights reserved. + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. + * + * This code is free software; you can redistribute it and/or modify it @@ -14183,219 +14039,76 @@ index 00000000000..0e40e2ca7cf + * + */ + -+#ifndef CPU_LOONGARCH_C2_GLOBALS_LOONGARCH_HPP -+#define CPU_LOONGARCH_C2_GLOBALS_LOONGARCH_HPP -+ -+#include "utilities/globalDefinitions.hpp" -+#include "utilities/macros.hpp" -+ -+// Sets the default values for platform dependent flags used by the server compiler. -+// (see c2_globals.hpp). Alpha-sorted. -+define_pd_global(bool, BackgroundCompilation, true); -+define_pd_global(bool, UseTLAB, true); -+define_pd_global(bool, ResizeTLAB, true); -+define_pd_global(bool, CICompileOSR, true); -+define_pd_global(bool, InlineIntrinsics, true); -+define_pd_global(bool, PreferInterpreterNativeStubs, false); -+define_pd_global(bool, ProfileTraps, true); -+define_pd_global(bool, UseOnStackReplacement, true); -+define_pd_global(bool, ProfileInterpreter, true); -+define_pd_global(bool, TieredCompilation, true); -+define_pd_global(intx, CompileThreshold, 10000); -+define_pd_global(intx, BackEdgeThreshold, 100000); -+ -+define_pd_global(intx, OnStackReplacePercentage, 140); -+define_pd_global(intx, ConditionalMoveLimit, 3); -+define_pd_global(intx, FLOATPRESSURE, 31); -+define_pd_global(intx, FreqInlineSize, 325); -+define_pd_global(intx, MinJumpTableSize, 10); -+define_pd_global(intx, INTPRESSURE, 23); -+define_pd_global(intx, InteriorEntryAlignment, 16); -+define_pd_global(intx, NewSizeThreadIncrease, ScaleForWordSize(4*K)); -+define_pd_global(intx, LoopUnrollLimit, 60); -+define_pd_global(intx, LoopPercentProfileLimit, 10); -+// InitialCodeCacheSize derived from specjbb2000 run. -+define_pd_global(intx, InitialCodeCacheSize, 2496*K); // Integral multiple of CodeCacheExpansionSize -+define_pd_global(intx, CodeCacheExpansionSize, 64*K); ++#include "precompiled.hpp" ++#include "asm/macroAssembler.hpp" ++#include "opto/compile.hpp" ++#include "opto/node.hpp" ++#include "opto/output.hpp" ++#include "runtime/sharedRuntime.hpp" + -+// Ergonomics related flags -+define_pd_global(uint64_t,MaxRAM, 128ULL*G); -+define_pd_global(intx, RegisterCostAreaRatio, 16000); ++#define __ masm. ++void C2SafepointPollStubTable::emit_stub_impl(MacroAssembler& masm, C2SafepointPollStub* entry) const { ++ assert(SharedRuntime::polling_page_return_handler_blob() != NULL, ++ "polling page return stub not created yet"); ++ address stub = SharedRuntime::polling_page_return_handler_blob()->entry_point(); + -+// Peephole and CISC spilling both break the graph, and so makes the -+// scheduler sick. -+define_pd_global(bool, OptoPeephole, false); -+define_pd_global(bool, UseCISCSpill, false); -+define_pd_global(bool, OptoScheduling, false); -+define_pd_global(bool, OptoBundling, false); -+define_pd_global(bool, OptoRegScheduling, false); -+define_pd_global(bool, SuperWordLoopUnrollAnalysis, true); -+define_pd_global(bool, IdealizeClearArrayNode, true); ++ Register thread = TREG; ++#ifndef OPT_THREAD ++ get_thread(thread); ++#endif + -+define_pd_global(intx, ReservedCodeCacheSize, 48*M); -+define_pd_global(intx, NonProfiledCodeHeapSize, 21*M); -+define_pd_global(intx, ProfiledCodeHeapSize, 22*M); -+define_pd_global(intx, NonNMethodCodeHeapSize, 5*M ); -+define_pd_global(uintx, CodeCacheMinBlockLength, 4); -+define_pd_global(uintx, CodeCacheMinimumUseSpace, 400*K); ++ __ bind(entry->_stub_label); ++ InternalAddress safepoint_pc(masm.pc() - masm.offset() + entry->_safepoint_offset); ++ __ lea(AT, safepoint_pc); ++ __ st_d(AT, Address(thread, JavaThread::saved_exception_pc_offset())); ++ __ jmp(stub, relocInfo::runtime_call_type); ++} ++#undef __ +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/codeBuffer_loongarch.hpp b/src/hotspot/cpu/loongarch/codeBuffer_loongarch.hpp +--- a/src/hotspot/cpu/loongarch/codeBuffer_loongarch.hpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/loongarch/codeBuffer_loongarch.hpp 2024-01-31 14:01:11.597428831 +0800 +@@ -0,0 +1,35 @@ ++/* ++ * Copyright (c) 2002, 2010, Oracle and/or its affiliates. All rights reserved. ++ * Copyright (c) 2015, 2021, Loongson Technology. All rights reserved. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ * ++ */ + -+define_pd_global(bool, TrapBasedRangeChecks, false); ++#ifndef CPU_LOONGARCH_CODEBUFFER_LOONGARCH_HPP ++#define CPU_LOONGARCH_CODEBUFFER_LOONGARCH_HPP + -+// Heap related flags -+define_pd_global(uintx,MetaspaceSize, ScaleForWordSize(16*M)); ++private: ++ void pd_initialize() {} + -+// Ergonomics related flags -+define_pd_global(bool, NeverActAsServerClassMachine, false); ++public: ++ void flush_bundle(bool start_new_bundle) {} + -+#endif // CPU_LOONGARCH_C2_GLOBALS_LOONGARCH_HPP -diff --git a/src/hotspot/cpu/loongarch/c2_init_loongarch.cpp b/src/hotspot/cpu/loongarch/c2_init_loongarch.cpp -new file mode 100644 -index 00000000000..ec78b942d40 ---- /dev/null -+++ b/src/hotspot/cpu/loongarch/c2_init_loongarch.cpp -@@ -0,0 +1,37 @@ ++#endif // CPU_LOONGARCH_CODEBUFFER_LOONGARCH_HPP +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/compiledIC_loongarch.cpp b/src/hotspot/cpu/loongarch/compiledIC_loongarch.cpp +--- a/src/hotspot/cpu/loongarch/compiledIC_loongarch.cpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/loongarch/compiledIC_loongarch.cpp 2024-01-31 14:01:11.597428831 +0800 +@@ -0,0 +1,144 @@ +/* -+ * Copyright (c) 2000, 2010, Oracle and/or its affiliates. All rights reserved. -+ * Copyright (c) 2015, 2022, Loongson Technology. All rights reserved. -+ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. -+ * -+ * This code is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 only, as -+ * published by the Free Software Foundation. -+ * -+ * This code is distributed in the hope that it will be useful, but WITHOUT -+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -+ * version 2 for more details (a copy is included in the LICENSE file that -+ * accompanied this code). -+ * -+ * You should have received a copy of the GNU General Public License version -+ * 2 along with this work; if not, write to the Free Software Foundation, -+ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. -+ * -+ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA -+ * or visit www.oracle.com if you need additional information or have any -+ * questions. -+ * -+ */ -+ -+#include "precompiled.hpp" -+#include "opto/compile.hpp" -+#include "opto/node.hpp" -+ -+// processor dependent initialization for LoongArch -+ -+extern void reg_mask_init(); -+ -+void Compile::pd_compiler2_init() { -+ guarantee(CodeEntryAlignment >= InteriorEntryAlignment, "" ); -+ reg_mask_init(); -+} -diff --git a/src/hotspot/cpu/loongarch/c2_safepointPollStubTable_loongarch.cpp b/src/hotspot/cpu/loongarch/c2_safepointPollStubTable_loongarch.cpp -new file mode 100644 -index 00000000000..866858b26b8 ---- /dev/null -+++ b/src/hotspot/cpu/loongarch/c2_safepointPollStubTable_loongarch.cpp -@@ -0,0 +1,50 @@ -+/* -+ * Copyright (c) 2020, 2021, Oracle and/or its affiliates. All rights reserved. -+ * Copyright (c) 2021, Loongson Technology. All rights reserved. -+ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. -+ * -+ * This code is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 only, as -+ * published by the Free Software Foundation. -+ * -+ * This code is distributed in the hope that it will be useful, but WITHOUT -+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -+ * version 2 for more details (a copy is included in the LICENSE file that -+ * accompanied this code). -+ * -+ * You should have received a copy of the GNU General Public License version -+ * 2 along with this work; if not, write to the Free Software Foundation, -+ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. -+ * -+ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA -+ * or visit www.oracle.com if you need additional information or have any -+ * questions. -+ * -+ */ -+ -+#include "precompiled.hpp" -+#include "asm/macroAssembler.hpp" -+#include "opto/compile.hpp" -+#include "opto/node.hpp" -+#include "opto/output.hpp" -+#include "runtime/sharedRuntime.hpp" -+ -+#define __ masm. -+void C2SafepointPollStubTable::emit_stub_impl(MacroAssembler& masm, C2SafepointPollStub* entry) const { -+ assert(SharedRuntime::polling_page_return_handler_blob() != NULL, -+ "polling page return stub not created yet"); -+ address stub = SharedRuntime::polling_page_return_handler_blob()->entry_point(); -+ -+ Register thread = TREG; -+#ifndef OPT_THREAD -+ get_thread(thread); -+#endif -+ -+ __ bind(entry->_stub_label); -+ InternalAddress safepoint_pc(masm.pc() - masm.offset() + entry->_safepoint_offset); -+ __ lea(AT, safepoint_pc); -+ __ st_d(AT, Address(thread, JavaThread::saved_exception_pc_offset())); -+ __ jmp(stub, relocInfo::runtime_call_type); -+} -+#undef __ -diff --git a/src/hotspot/cpu/loongarch/codeBuffer_loongarch.hpp b/src/hotspot/cpu/loongarch/codeBuffer_loongarch.hpp -new file mode 100644 -index 00000000000..653d95806bf ---- /dev/null -+++ b/src/hotspot/cpu/loongarch/codeBuffer_loongarch.hpp -@@ -0,0 +1,35 @@ -+/* -+ * Copyright (c) 2002, 2010, Oracle and/or its affiliates. All rights reserved. -+ * Copyright (c) 2015, 2021, Loongson Technology. All rights reserved. -+ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. -+ * -+ * This code is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 only, as -+ * published by the Free Software Foundation. -+ * -+ * This code is distributed in the hope that it will be useful, but WITHOUT -+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -+ * version 2 for more details (a copy is included in the LICENSE file that -+ * accompanied this code). -+ * -+ * You should have received a copy of the GNU General Public License version -+ * 2 along with this work; if not, write to the Free Software Foundation, -+ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. -+ * -+ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA -+ * or visit www.oracle.com if you need additional information or have any -+ * questions. -+ * -+ */ -+ -+#ifndef CPU_LOONGARCH_CODEBUFFER_LOONGARCH_HPP -+#define CPU_LOONGARCH_CODEBUFFER_LOONGARCH_HPP -+ -+private: -+ void pd_initialize() {} -+ -+public: -+ void flush_bundle(bool start_new_bundle) {} -+ -+#endif // CPU_LOONGARCH_CODEBUFFER_LOONGARCH_HPP -diff --git a/src/hotspot/cpu/loongarch/compiledIC_loongarch.cpp b/src/hotspot/cpu/loongarch/compiledIC_loongarch.cpp -new file mode 100644 -index 00000000000..b3f70a1665b ---- /dev/null -+++ b/src/hotspot/cpu/loongarch/compiledIC_loongarch.cpp -@@ -0,0 +1,144 @@ -+/* -+ * Copyright (c) 1997, 2014, Oracle and/or its affiliates. All rights reserved. ++ * Copyright (c) 1997, 2014, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 2015, 2022, Loongson Technology. All rights reserved. + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. + * @@ -14538,11 +14251,9 @@ index 00000000000..b3f70a1665b +} + +#endif // !PRODUCT -diff --git a/src/hotspot/cpu/loongarch/copy_loongarch.hpp b/src/hotspot/cpu/loongarch/copy_loongarch.hpp -new file mode 100644 -index 00000000000..54b847a7369 ---- /dev/null -+++ b/src/hotspot/cpu/loongarch/copy_loongarch.hpp +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/copy_loongarch.hpp b/src/hotspot/cpu/loongarch/copy_loongarch.hpp +--- a/src/hotspot/cpu/loongarch/copy_loongarch.hpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/loongarch/copy_loongarch.hpp 2024-01-31 14:01:11.597428831 +0800 @@ -0,0 +1,77 @@ +/* + * Copyright (c) 2003, 2010, Oracle and/or its affiliates. All rights reserved. @@ -14621,11 +14332,9 @@ index 00000000000..54b847a7369 +} + +#endif //CPU_LOONGARCH_COPY_LOONGARCH_HPP -diff --git a/src/hotspot/cpu/loongarch/disassembler_loongarch.hpp b/src/hotspot/cpu/loongarch/disassembler_loongarch.hpp -new file mode 100644 -index 00000000000..fd176c8f056 ---- /dev/null -+++ b/src/hotspot/cpu/loongarch/disassembler_loongarch.hpp +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/disassembler_loongarch.hpp b/src/hotspot/cpu/loongarch/disassembler_loongarch.hpp +--- a/src/hotspot/cpu/loongarch/disassembler_loongarch.hpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/loongarch/disassembler_loongarch.hpp 2024-01-31 14:01:11.597428831 +0800 @@ -0,0 +1,57 @@ +/* + * Copyright (c) 1997, 2010, Oracle and/or its affiliates. All rights reserved. @@ -14684,11 +14393,9 @@ index 00000000000..fd176c8f056 + static void annotate(address pc, outputStream* st) { }; + +#endif // CPU_LOONGARCH_DISASSEMBLER_LOONGARCH_HPP -diff --git a/src/hotspot/cpu/loongarch/foreign_globals_loongarch.cpp b/src/hotspot/cpu/loongarch/foreign_globals_loongarch.cpp -new file mode 100644 -index 00000000000..fb4647c2723 ---- /dev/null -+++ b/src/hotspot/cpu/loongarch/foreign_globals_loongarch.cpp +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/foreign_globals_loongarch.cpp b/src/hotspot/cpu/loongarch/foreign_globals_loongarch.cpp +--- a/src/hotspot/cpu/loongarch/foreign_globals_loongarch.cpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/loongarch/foreign_globals_loongarch.cpp 2024-01-31 14:01:11.597428831 +0800 @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2020, Red Hat, Inc. All rights reserved. @@ -14732,11 +14439,9 @@ index 00000000000..fb4647c2723 + ShouldNotCallThis(); + return {}; +} -diff --git a/src/hotspot/cpu/loongarch/foreign_globals_loongarch.hpp b/src/hotspot/cpu/loongarch/foreign_globals_loongarch.hpp -new file mode 100644 -index 00000000000..680a27363ec ---- /dev/null -+++ b/src/hotspot/cpu/loongarch/foreign_globals_loongarch.hpp +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/foreign_globals_loongarch.hpp b/src/hotspot/cpu/loongarch/foreign_globals_loongarch.hpp +--- a/src/hotspot/cpu/loongarch/foreign_globals_loongarch.hpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/loongarch/foreign_globals_loongarch.hpp 2024-01-31 14:01:11.597428831 +0800 @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2020, Red Hat, Inc. All rights reserved. @@ -14769,11 +14474,9 @@ index 00000000000..680a27363ec +class ABIDescriptor {}; + +#endif // CPU_LOONGARCH_FOREIGN_GLOBALS_LOONGARCH_HPP -diff --git a/src/hotspot/cpu/loongarch/frame_loongarch.cpp b/src/hotspot/cpu/loongarch/frame_loongarch.cpp -new file mode 100644 -index 00000000000..23a63a77d98 ---- /dev/null -+++ b/src/hotspot/cpu/loongarch/frame_loongarch.cpp +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/frame_loongarch.cpp b/src/hotspot/cpu/loongarch/frame_loongarch.cpp +--- a/src/hotspot/cpu/loongarch/frame_loongarch.cpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/loongarch/frame_loongarch.cpp 2024-01-31 14:01:11.597428831 +0800 @@ -0,0 +1,668 @@ +/* + * Copyright (c) 1997, 2014, Oracle and/or its affiliates. All rights reserved. @@ -15315,7 +15018,7 @@ index 00000000000..23a63a77d98 + + // first the method + -+ Method* m = *interpreter_frame_method_addr(); ++ Method* m = safe_interpreter_frame_method(); + + // validate the method we'd find in this potential sender + if (!Method::is_valid_method(m)) return false; @@ -15443,11 +15146,9 @@ index 00000000000..23a63a77d98 + +void frame::pd_ps() {} +#endif -diff --git a/src/hotspot/cpu/loongarch/frame_loongarch.hpp b/src/hotspot/cpu/loongarch/frame_loongarch.hpp -new file mode 100644 -index 00000000000..738b5306366 ---- /dev/null -+++ b/src/hotspot/cpu/loongarch/frame_loongarch.hpp +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/frame_loongarch.hpp b/src/hotspot/cpu/loongarch/frame_loongarch.hpp +--- a/src/hotspot/cpu/loongarch/frame_loongarch.hpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/loongarch/frame_loongarch.hpp 2024-01-31 14:01:11.597428831 +0800 @@ -0,0 +1,162 @@ +/* + * Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved. @@ -15611,11 +15312,9 @@ index 00000000000..738b5306366 + frame sender_raw(RegisterMap* map) const; + +#endif // CPU_LOONGARCH_FRAME_LOONGARCH_HPP -diff --git a/src/hotspot/cpu/loongarch/frame_loongarch.inline.hpp b/src/hotspot/cpu/loongarch/frame_loongarch.inline.hpp -new file mode 100644 -index 00000000000..8b0e0502701 ---- /dev/null -+++ b/src/hotspot/cpu/loongarch/frame_loongarch.inline.hpp +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/frame_loongarch.inline.hpp b/src/hotspot/cpu/loongarch/frame_loongarch.inline.hpp +--- a/src/hotspot/cpu/loongarch/frame_loongarch.inline.hpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/loongarch/frame_loongarch.inline.hpp 2024-01-31 14:01:11.597428831 +0800 @@ -0,0 +1,245 @@ +/* + * Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved. @@ -15862,11 +15561,9 @@ index 00000000000..8b0e0502701 +} + +#endif // CPU_LOONGARCH_FRAME_LOONGARCH_INLINE_HPP -diff --git a/src/hotspot/cpu/loongarch/gc/g1/g1BarrierSetAssembler_loongarch.cpp b/src/hotspot/cpu/loongarch/gc/g1/g1BarrierSetAssembler_loongarch.cpp -new file mode 100644 -index 00000000000..e129264506b ---- /dev/null -+++ b/src/hotspot/cpu/loongarch/gc/g1/g1BarrierSetAssembler_loongarch.cpp +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/gc/g1/g1BarrierSetAssembler_loongarch.cpp b/src/hotspot/cpu/loongarch/gc/g1/g1BarrierSetAssembler_loongarch.cpp +--- a/src/hotspot/cpu/loongarch/gc/g1/g1BarrierSetAssembler_loongarch.cpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/loongarch/gc/g1/g1BarrierSetAssembler_loongarch.cpp 2024-01-31 14:01:11.597428831 +0800 @@ -0,0 +1,532 @@ +/* + * Copyright (c) 2018, Oracle and/or its affiliates. All rights reserved. @@ -16400,11 +16097,9 @@ index 00000000000..e129264506b +#undef __ + +#endif // COMPILER1 -diff --git a/src/hotspot/cpu/loongarch/gc/g1/g1BarrierSetAssembler_loongarch.hpp b/src/hotspot/cpu/loongarch/gc/g1/g1BarrierSetAssembler_loongarch.hpp -new file mode 100644 -index 00000000000..745046ac0cc ---- /dev/null -+++ b/src/hotspot/cpu/loongarch/gc/g1/g1BarrierSetAssembler_loongarch.hpp +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/gc/g1/g1BarrierSetAssembler_loongarch.hpp b/src/hotspot/cpu/loongarch/gc/g1/g1BarrierSetAssembler_loongarch.hpp +--- a/src/hotspot/cpu/loongarch/gc/g1/g1BarrierSetAssembler_loongarch.hpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/loongarch/gc/g1/g1BarrierSetAssembler_loongarch.hpp 2024-01-31 14:01:11.597428831 +0800 @@ -0,0 +1,71 @@ +/* + * Copyright (c) 2018, Oracle and/or its affiliates. All rights reserved. @@ -16477,11 +16172,9 @@ index 00000000000..745046ac0cc +}; + +#endif // CPU_LOONGARCH_GC_G1_G1BARRIERSETASSEMBLER_LOONGARCH_HPP -diff --git a/src/hotspot/cpu/loongarch/gc/g1/g1Globals_loongarch.hpp b/src/hotspot/cpu/loongarch/gc/g1/g1Globals_loongarch.hpp -new file mode 100644 -index 00000000000..44b7ff1485f ---- /dev/null -+++ b/src/hotspot/cpu/loongarch/gc/g1/g1Globals_loongarch.hpp +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/gc/g1/g1Globals_loongarch.hpp b/src/hotspot/cpu/loongarch/gc/g1/g1Globals_loongarch.hpp +--- a/src/hotspot/cpu/loongarch/gc/g1/g1Globals_loongarch.hpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/loongarch/gc/g1/g1Globals_loongarch.hpp 2024-01-31 14:01:11.597428831 +0800 @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2021, Oracle and/or its affiliates. All rights reserved. @@ -16513,11 +16206,9 @@ index 00000000000..44b7ff1485f +const size_t G1MergeHeapRootsPrefetchCacheSize = 8; + +#endif // CPU_LOONGARCH_GC_G1_G1GLOBALS_LOONGARCH_HPP -diff --git a/src/hotspot/cpu/loongarch/gc/shared/barrierSetAssembler_loongarch.cpp b/src/hotspot/cpu/loongarch/gc/shared/barrierSetAssembler_loongarch.cpp -new file mode 100644 -index 00000000000..4706559a837 ---- /dev/null -+++ b/src/hotspot/cpu/loongarch/gc/shared/barrierSetAssembler_loongarch.cpp +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/gc/shared/barrierSetAssembler_loongarch.cpp b/src/hotspot/cpu/loongarch/gc/shared/barrierSetAssembler_loongarch.cpp +--- a/src/hotspot/cpu/loongarch/gc/shared/barrierSetAssembler_loongarch.cpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/loongarch/gc/shared/barrierSetAssembler_loongarch.cpp 2024-01-31 14:01:11.600762198 +0800 @@ -0,0 +1,320 @@ +/* + * Copyright (c) 2018, Oracle and/or its affiliates. All rights reserved. @@ -16839,11 +16530,9 @@ index 00000000000..4706559a837 + __ bind(method_live); +} + -diff --git a/src/hotspot/cpu/loongarch/gc/shared/barrierSetAssembler_loongarch.hpp b/src/hotspot/cpu/loongarch/gc/shared/barrierSetAssembler_loongarch.hpp -new file mode 100644 -index 00000000000..f87c2061132 ---- /dev/null -+++ b/src/hotspot/cpu/loongarch/gc/shared/barrierSetAssembler_loongarch.hpp +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/gc/shared/barrierSetAssembler_loongarch.hpp b/src/hotspot/cpu/loongarch/gc/shared/barrierSetAssembler_loongarch.hpp +--- a/src/hotspot/cpu/loongarch/gc/shared/barrierSetAssembler_loongarch.hpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/loongarch/gc/shared/barrierSetAssembler_loongarch.hpp 2024-01-31 14:01:11.600762198 +0800 @@ -0,0 +1,93 @@ +/* + * Copyright (c) 2018, Oracle and/or its affiliates. All rights reserved. @@ -16938,11 +16627,9 @@ index 00000000000..f87c2061132 +}; + +#endif // CPU_LOONGARCH_GC_SHARED_BARRIERSETASSEMBLER_LOONGARCH_HPP -diff --git a/src/hotspot/cpu/loongarch/gc/shared/barrierSetNMethod_loongarch.cpp b/src/hotspot/cpu/loongarch/gc/shared/barrierSetNMethod_loongarch.cpp -new file mode 100644 -index 00000000000..65cee60f69d ---- /dev/null -+++ b/src/hotspot/cpu/loongarch/gc/shared/barrierSetNMethod_loongarch.cpp +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/gc/shared/barrierSetNMethod_loongarch.cpp b/src/hotspot/cpu/loongarch/gc/shared/barrierSetNMethod_loongarch.cpp +--- a/src/hotspot/cpu/loongarch/gc/shared/barrierSetNMethod_loongarch.cpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/loongarch/gc/shared/barrierSetNMethod_loongarch.cpp 2024-01-31 14:01:11.600762198 +0800 @@ -0,0 +1,157 @@ +/* + * Copyright (c) 2018, Oracle and/or its affiliates. All rights reserved. @@ -17101,11 +16788,9 @@ index 00000000000..65cee60f69d + NativeNMethodBarrier* barrier = native_nmethod_barrier(nm); + return barrier->get_value() != disarmed_value(); +} -diff --git a/src/hotspot/cpu/loongarch/gc/shared/cardTableBarrierSetAssembler_loongarch.cpp b/src/hotspot/cpu/loongarch/gc/shared/cardTableBarrierSetAssembler_loongarch.cpp -new file mode 100644 -index 00000000000..96dc9562a02 ---- /dev/null -+++ b/src/hotspot/cpu/loongarch/gc/shared/cardTableBarrierSetAssembler_loongarch.cpp +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/gc/shared/cardTableBarrierSetAssembler_loongarch.cpp b/src/hotspot/cpu/loongarch/gc/shared/cardTableBarrierSetAssembler_loongarch.cpp +--- a/src/hotspot/cpu/loongarch/gc/shared/cardTableBarrierSetAssembler_loongarch.cpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/loongarch/gc/shared/cardTableBarrierSetAssembler_loongarch.cpp 2024-01-31 14:01:11.600762198 +0800 @@ -0,0 +1,119 @@ +/* + * Copyright (c) 2018, Oracle and/or its affiliates. All rights reserved. @@ -17226,11 +16911,9 @@ index 00000000000..96dc9562a02 + } + } +} -diff --git a/src/hotspot/cpu/loongarch/gc/shared/cardTableBarrierSetAssembler_loongarch.hpp b/src/hotspot/cpu/loongarch/gc/shared/cardTableBarrierSetAssembler_loongarch.hpp -new file mode 100644 -index 00000000000..7d628ca6a85 ---- /dev/null -+++ b/src/hotspot/cpu/loongarch/gc/shared/cardTableBarrierSetAssembler_loongarch.hpp +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/gc/shared/cardTableBarrierSetAssembler_loongarch.hpp b/src/hotspot/cpu/loongarch/gc/shared/cardTableBarrierSetAssembler_loongarch.hpp +--- a/src/hotspot/cpu/loongarch/gc/shared/cardTableBarrierSetAssembler_loongarch.hpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/loongarch/gc/shared/cardTableBarrierSetAssembler_loongarch.hpp 2024-01-31 14:01:11.600762198 +0800 @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2018, Oracle and/or its affiliates. All rights reserved. @@ -17276,11 +16959,9 @@ index 00000000000..7d628ca6a85 +}; + +#endif // CPU_LOONGARCH_GC_SHARED_CARDTABLEBARRIERSETASSEMBLER_LOONGARCH_HPP -diff --git a/src/hotspot/cpu/loongarch/gc/shared/modRefBarrierSetAssembler_loongarch.cpp b/src/hotspot/cpu/loongarch/gc/shared/modRefBarrierSetAssembler_loongarch.cpp -new file mode 100644 -index 00000000000..71c3cb49386 ---- /dev/null -+++ b/src/hotspot/cpu/loongarch/gc/shared/modRefBarrierSetAssembler_loongarch.cpp +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/gc/shared/modRefBarrierSetAssembler_loongarch.cpp b/src/hotspot/cpu/loongarch/gc/shared/modRefBarrierSetAssembler_loongarch.cpp +--- a/src/hotspot/cpu/loongarch/gc/shared/modRefBarrierSetAssembler_loongarch.cpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/loongarch/gc/shared/modRefBarrierSetAssembler_loongarch.cpp 2024-01-31 14:01:11.600762198 +0800 @@ -0,0 +1,53 @@ +/* + * Copyright (c) 2018, Oracle and/or its affiliates. All rights reserved. @@ -17335,11 +17016,9 @@ index 00000000000..71c3cb49386 + BarrierSetAssembler::store_at(masm, decorators, type, dst, val, tmp1, tmp2); + } +} -diff --git a/src/hotspot/cpu/loongarch/gc/shared/modRefBarrierSetAssembler_loongarch.hpp b/src/hotspot/cpu/loongarch/gc/shared/modRefBarrierSetAssembler_loongarch.hpp -new file mode 100644 -index 00000000000..086bdebb506 ---- /dev/null -+++ b/src/hotspot/cpu/loongarch/gc/shared/modRefBarrierSetAssembler_loongarch.hpp +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/gc/shared/modRefBarrierSetAssembler_loongarch.hpp b/src/hotspot/cpu/loongarch/gc/shared/modRefBarrierSetAssembler_loongarch.hpp +--- a/src/hotspot/cpu/loongarch/gc/shared/modRefBarrierSetAssembler_loongarch.hpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/loongarch/gc/shared/modRefBarrierSetAssembler_loongarch.hpp 2024-01-31 14:01:11.600762198 +0800 @@ -0,0 +1,54 @@ +/* + * Copyright (c) 2018, Oracle and/or its affiliates. All rights reserved. @@ -17395,11 +17074,9 @@ index 00000000000..086bdebb506 +}; + +#endif // CPU_LOONGARCH_GC_SHARED_MODREFBARRIERSETASSEMBLER_LOONGARCH_HPP -diff --git a/src/hotspot/cpu/loongarch/gc/shenandoah/c1/shenandoahBarrierSetC1_loongarch.cpp b/src/hotspot/cpu/loongarch/gc/shenandoah/c1/shenandoahBarrierSetC1_loongarch.cpp -new file mode 100644 -index 00000000000..f82a2500d41 ---- /dev/null -+++ b/src/hotspot/cpu/loongarch/gc/shenandoah/c1/shenandoahBarrierSetC1_loongarch.cpp +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/gc/shenandoah/c1/shenandoahBarrierSetC1_loongarch.cpp b/src/hotspot/cpu/loongarch/gc/shenandoah/c1/shenandoahBarrierSetC1_loongarch.cpp +--- a/src/hotspot/cpu/loongarch/gc/shenandoah/c1/shenandoahBarrierSetC1_loongarch.cpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/loongarch/gc/shenandoah/c1/shenandoahBarrierSetC1_loongarch.cpp 2024-01-31 14:01:11.600762198 +0800 @@ -0,0 +1,130 @@ +/* + * Copyright (c) 2018, 2021, Red Hat, Inc. All rights reserved. @@ -17531,11 +17208,9 @@ index 00000000000..f82a2500d41 + + return result; +} -diff --git a/src/hotspot/cpu/loongarch/gc/shenandoah/shenandoahBarrierSetAssembler_loongarch.cpp b/src/hotspot/cpu/loongarch/gc/shenandoah/shenandoahBarrierSetAssembler_loongarch.cpp -new file mode 100644 -index 00000000000..7cf552e283a ---- /dev/null -+++ b/src/hotspot/cpu/loongarch/gc/shenandoah/shenandoahBarrierSetAssembler_loongarch.cpp +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/gc/shenandoah/shenandoahBarrierSetAssembler_loongarch.cpp b/src/hotspot/cpu/loongarch/gc/shenandoah/shenandoahBarrierSetAssembler_loongarch.cpp +--- a/src/hotspot/cpu/loongarch/gc/shenandoah/shenandoahBarrierSetAssembler_loongarch.cpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/loongarch/gc/shenandoah/shenandoahBarrierSetAssembler_loongarch.cpp 2024-01-31 14:01:11.600762198 +0800 @@ -0,0 +1,784 @@ +/* + * Copyright (c) 2018, 2021, Red Hat, Inc. All rights reserved. @@ -18054,9 +17729,9 @@ index 00000000000..7cf552e283a + + if (is_narrow) { + __ cmpxchg32(addr, expected, new_val, tmp2, false /* sign */, false /* retold */, -+ acquire /* barrier */, false /* weak */, true /* exchange */); ++ acquire /* acquire */, false /* weak */, true /* exchange */); + } else { -+ __ cmpxchg(addr, expected, new_val, tmp2, false /* retold */, acquire /* barrier */, ++ __ cmpxchg(addr, expected, new_val, tmp2, false /* retold */, acquire /* acquire */, + false /* weak */, true /* exchange */); + } + // tmp2 holds value fetched. @@ -18120,9 +17795,9 @@ index 00000000000..7cf552e283a + // compares result with expected. + if (is_narrow) { + __ cmpxchg32(addr, tmp2, new_val, tmp1, false /* sign */, false /* retold */, -+ acquire /* barrier */, false /* weak */, false /* exchange */); ++ acquire /* acquire */, false /* weak */, false /* exchange */); + } else { -+ __ cmpxchg(addr, tmp2, new_val, tmp1, false /* retold */, acquire /* barrier */, ++ __ cmpxchg(addr, tmp2, new_val, tmp1, false /* retold */, acquire /* acquire */, + false /* weak */, false /* exchange */); + } + // tmp1 set iff success, tmp2 holds value fetched. @@ -18321,11 +17996,9 @@ index 00000000000..7cf552e283a +#undef __ + +#endif // COMPILER1 -diff --git a/src/hotspot/cpu/loongarch/gc/shenandoah/shenandoahBarrierSetAssembler_loongarch.hpp b/src/hotspot/cpu/loongarch/gc/shenandoah/shenandoahBarrierSetAssembler_loongarch.hpp -new file mode 100644 -index 00000000000..e2c862f6c5c ---- /dev/null -+++ b/src/hotspot/cpu/loongarch/gc/shenandoah/shenandoahBarrierSetAssembler_loongarch.hpp +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/gc/shenandoah/shenandoahBarrierSetAssembler_loongarch.hpp b/src/hotspot/cpu/loongarch/gc/shenandoah/shenandoahBarrierSetAssembler_loongarch.hpp +--- a/src/hotspot/cpu/loongarch/gc/shenandoah/shenandoahBarrierSetAssembler_loongarch.hpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/loongarch/gc/shenandoah/shenandoahBarrierSetAssembler_loongarch.hpp 2024-01-31 14:01:11.600762198 +0800 @@ -0,0 +1,85 @@ +/* + * Copyright (c) 2018, 2021, Red Hat, Inc. All rights reserved. @@ -18412,11 +18085,9 @@ index 00000000000..e2c862f6c5c +}; + +#endif // CPU_LOONGARCH_GC_SHENANDOAH_SHENANDOAHBARRIERSETASSEMBLER_LOONGARCH_HPP -diff --git a/src/hotspot/cpu/loongarch/gc/shenandoah/shenandoah_loongarch_64.ad b/src/hotspot/cpu/loongarch/gc/shenandoah/shenandoah_loongarch_64.ad -new file mode 100644 -index 00000000000..04f67d23157 ---- /dev/null -+++ b/src/hotspot/cpu/loongarch/gc/shenandoah/shenandoah_loongarch_64.ad +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/gc/shenandoah/shenandoah_loongarch_64.ad b/src/hotspot/cpu/loongarch/gc/shenandoah/shenandoah_loongarch_64.ad +--- a/src/hotspot/cpu/loongarch/gc/shenandoah/shenandoah_loongarch_64.ad 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/loongarch/gc/shenandoah/shenandoah_loongarch_64.ad 2024-01-31 14:01:11.600762198 +0800 @@ -0,0 +1,222 @@ +// +// Copyright (c) 2018, Red Hat, Inc. All rights reserved. @@ -18640,12 +18311,10 @@ index 00000000000..04f67d23157 + + ins_pipe(pipe_slow); +%} -diff --git a/src/hotspot/cpu/loongarch/gc/z/zBarrierSetAssembler_loongarch.cpp b/src/hotspot/cpu/loongarch/gc/z/zBarrierSetAssembler_loongarch.cpp -new file mode 100644 -index 00000000000..3ef43daa725 ---- /dev/null -+++ b/src/hotspot/cpu/loongarch/gc/z/zBarrierSetAssembler_loongarch.cpp -@@ -0,0 +1,466 @@ +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/gc/z/zBarrierSetAssembler_loongarch.cpp b/src/hotspot/cpu/loongarch/gc/z/zBarrierSetAssembler_loongarch.cpp +--- a/src/hotspot/cpu/loongarch/gc/z/zBarrierSetAssembler_loongarch.cpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/loongarch/gc/z/zBarrierSetAssembler_loongarch.cpp 2024-01-31 14:01:11.600762198 +0800 +@@ -0,0 +1,462 @@ +/* + * Copyright (c) 2019, 2021, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 2021, 2022, Loongson Technology. All rights reserved. @@ -18870,14 +18539,10 @@ index 00000000000..3ef43daa725 +#define __ ce->masm()-> + +void ZBarrierSetAssembler::generate_c1_load_barrier_test(LIR_Assembler* ce, -+ LIR_Opr ref, -+ LIR_Opr res) const { -+ Register rscratch1 = AT; -+ Register rthread = TREG; -+ assert_different_registers(rscratch1, rthread, ref->as_register()); -+ -+ __ ld_d(rscratch1, address_bad_mask_from_thread(rthread)); -+ __ andr(res->as_register(), ref->as_register(), rscratch1); ++ LIR_Opr ref) const { ++ assert_different_registers(SCR1, TREG, ref->as_register()); ++ __ ld_d(SCR1, address_bad_mask_from_thread(TREG)); ++ __ andr(SCR1, SCR1, ref->as_register()); +} + +void ZBarrierSetAssembler::generate_c1_load_barrier_stub(LIR_Assembler* ce, @@ -19112,12 +18777,10 @@ index 00000000000..3ef43daa725 +#undef __ + +#endif // COMPILER2 -diff --git a/src/hotspot/cpu/loongarch/gc/z/zBarrierSetAssembler_loongarch.hpp b/src/hotspot/cpu/loongarch/gc/z/zBarrierSetAssembler_loongarch.hpp -new file mode 100644 -index 00000000000..8d032c34995 ---- /dev/null -+++ b/src/hotspot/cpu/loongarch/gc/z/zBarrierSetAssembler_loongarch.hpp -@@ -0,0 +1,102 @@ +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/gc/z/zBarrierSetAssembler_loongarch.hpp b/src/hotspot/cpu/loongarch/gc/z/zBarrierSetAssembler_loongarch.hpp +--- a/src/hotspot/cpu/loongarch/gc/z/zBarrierSetAssembler_loongarch.hpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/loongarch/gc/z/zBarrierSetAssembler_loongarch.hpp 2024-01-31 14:01:11.600762198 +0800 +@@ -0,0 +1,101 @@ +/* + * Copyright (c) 2019, 2021, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 2021, Loongson Technology. All rights reserved. @@ -19200,8 +18863,7 @@ index 00000000000..8d032c34995 + +#ifdef COMPILER1 + void generate_c1_load_barrier_test(LIR_Assembler* ce, -+ LIR_Opr ref, -+ LIR_Opr res) const; ++ LIR_Opr ref) const; + + void generate_c1_load_barrier_stub(LIR_Assembler* ce, + ZLoadBarrierStubC1* stub) const; @@ -19220,11 +18882,9 @@ index 00000000000..8d032c34995 +}; + +#endif // CPU_LOONGARCH_GC_Z_ZBARRIERSETASSEMBLER_LOONGARCH_HPP -diff --git a/src/hotspot/cpu/loongarch/gc/z/zGlobals_loongarch.cpp b/src/hotspot/cpu/loongarch/gc/z/zGlobals_loongarch.cpp -new file mode 100644 -index 00000000000..85db1cf1854 ---- /dev/null -+++ b/src/hotspot/cpu/loongarch/gc/z/zGlobals_loongarch.cpp +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/gc/z/zGlobals_loongarch.cpp b/src/hotspot/cpu/loongarch/gc/z/zGlobals_loongarch.cpp +--- a/src/hotspot/cpu/loongarch/gc/z/zGlobals_loongarch.cpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/loongarch/gc/z/zGlobals_loongarch.cpp 2024-01-31 14:01:11.600762198 +0800 @@ -0,0 +1,211 @@ +/* + * Copyright (c) 2017, 2021, Oracle and/or its affiliates. All rights reserved. @@ -19437,12 +19097,10 @@ index 00000000000..85db1cf1854 +size_t ZPlatformAddressMetadataShift() { + return ZPlatformAddressOffsetBits(); +} -diff --git a/src/hotspot/cpu/loongarch/gc/z/zGlobals_loongarch.hpp b/src/hotspot/cpu/loongarch/gc/z/zGlobals_loongarch.hpp -new file mode 100644 -index 00000000000..7d20899d949 ---- /dev/null -+++ b/src/hotspot/cpu/loongarch/gc/z/zGlobals_loongarch.hpp -@@ -0,0 +1,37 @@ +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/gc/z/zGlobals_loongarch.hpp b/src/hotspot/cpu/loongarch/gc/z/zGlobals_loongarch.hpp +--- a/src/hotspot/cpu/loongarch/gc/z/zGlobals_loongarch.hpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/loongarch/gc/z/zGlobals_loongarch.hpp 2024-01-31 14:01:11.600762198 +0800 +@@ -0,0 +1,35 @@ +/* + * Copyright (c) 2015, 2021, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 2021, Loongson Technology. All rights reserved. @@ -19474,17 +19132,13 @@ index 00000000000..7d20899d949 +const size_t ZPlatformHeapViews = 3; +const size_t ZPlatformCacheLineSize = 64; + -+const bool ZPlatformLoadBarrierTestResultInRegister = true; -+ +size_t ZPlatformAddressOffsetBits(); +size_t ZPlatformAddressMetadataShift(); + +#endif // CPU_LOONGARCH_GC_Z_ZGLOBALS_LOONGARCH_HPP -diff --git a/src/hotspot/cpu/loongarch/gc/z/z_loongarch_64.ad b/src/hotspot/cpu/loongarch/gc/z/z_loongarch_64.ad -new file mode 100644 -index 00000000000..59656e75376 ---- /dev/null -+++ b/src/hotspot/cpu/loongarch/gc/z/z_loongarch_64.ad +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/gc/z/z_loongarch_64.ad b/src/hotspot/cpu/loongarch/gc/z/z_loongarch_64.ad +--- a/src/hotspot/cpu/loongarch/gc/z/z_loongarch_64.ad 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/loongarch/gc/z/z_loongarch_64.ad 2024-01-31 14:01:11.600762198 +0800 @@ -0,0 +1,273 @@ +// +// Copyright (c) 2019, 2021, Oracle and/or its affiliates. All rights reserved. @@ -19552,12 +19206,12 @@ index 00000000000..59656e75376 +#endif + Address addr(mem); + if (node->barrier_data() == ZLoadBarrierElided) { -+ __ cmpxchg(addr, oldval, newval, tmp, false /* retold */, acquire /* barrier */, ++ __ cmpxchg(addr, oldval, newval, tmp, false /* retold */, acquire /* acquire */, + weak /* weak */, false /* exchange */); + __ move(res, tmp); + } else { + __ move(tmp, oldval); -+ __ cmpxchg(addr, tmp, newval, AT, true /* retold */, acquire /* barrier */, ++ __ cmpxchg(addr, tmp, newval, AT, true /* retold */, acquire /* acquire */, + false /* weak */, false /* exchange */); + __ move(res, AT); + @@ -19566,7 +19220,7 @@ index 00000000000..59656e75376 + __ andr(AT, AT, tmp); + __ beqz(AT, good); + z_load_barrier_slow_path(_masm, node, addr, tmp, res /* used as tmp */); -+ __ cmpxchg(addr, oldval, newval, tmp, false /* retold */, acquire /* barrier */, weak /* weak */, false /* exchange */); ++ __ cmpxchg(addr, oldval, newval, tmp, false /* retold */, acquire /* acquire */, weak /* weak */, false /* exchange */); + __ move(res, tmp); + __ bind(good); + } @@ -19759,11 +19413,9 @@ index 00000000000..59656e75376 + + ins_pipe(pipe_slow); +%} -diff --git a/src/hotspot/cpu/loongarch/globalDefinitions_loongarch.hpp b/src/hotspot/cpu/loongarch/globalDefinitions_loongarch.hpp -new file mode 100644 -index 00000000000..363cd6e2092 ---- /dev/null -+++ b/src/hotspot/cpu/loongarch/globalDefinitions_loongarch.hpp +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/globalDefinitions_loongarch.hpp b/src/hotspot/cpu/loongarch/globalDefinitions_loongarch.hpp +--- a/src/hotspot/cpu/loongarch/globalDefinitions_loongarch.hpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/loongarch/globalDefinitions_loongarch.hpp 2024-01-31 14:01:11.600762198 +0800 @@ -0,0 +1,55 @@ +/* + * Copyright (c) 1999, 2013, Oracle and/or its affiliates. All rights reserved. @@ -19820,12 +19472,10 @@ index 00000000000..363cd6e2092 +#define COMPRESSED_CLASS_POINTERS_DEPENDS_ON_COMPRESSED_OOPS false + +#endif // CPU_LOONGARCH_GLOBALDEFINITIONS_LOONGARCH_HPP -diff --git a/src/hotspot/cpu/loongarch/globals_loongarch.hpp b/src/hotspot/cpu/loongarch/globals_loongarch.hpp -new file mode 100644 -index 00000000000..e31a3d02555 ---- /dev/null -+++ b/src/hotspot/cpu/loongarch/globals_loongarch.hpp -@@ -0,0 +1,104 @@ +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/globals_loongarch.hpp b/src/hotspot/cpu/loongarch/globals_loongarch.hpp +--- a/src/hotspot/cpu/loongarch/globals_loongarch.hpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/loongarch/globals_loongarch.hpp 2024-01-31 14:01:11.600762198 +0800 +@@ -0,0 +1,106 @@ +/* + * Copyright (c) 2000, 2013, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 2015, 2022, Loongson Technology. All rights reserved. @@ -19925,16 +19575,107 @@ index 00000000000..e31a3d02555 + "Use CRC32 instructions for CRC32 computation") \ + \ + product(bool, UseActiveCoresMP, false, \ -+ "Eliminate barriers for single active cpu") ++ "Eliminate barriers for single active cpu") \ ++ \ ++ product(bool, TraceTraps, false, "Trace all traps the signal handler") + +// end of ARCH_FLAGS + +#endif // CPU_LOONGARCH_GLOBALS_LOONGARCH_HPP -diff --git a/src/hotspot/cpu/loongarch/icBuffer_loongarch.cpp b/src/hotspot/cpu/loongarch/icBuffer_loongarch.cpp -new file mode 100644 -index 00000000000..a8f08bbf422 ---- /dev/null -+++ b/src/hotspot/cpu/loongarch/icBuffer_loongarch.cpp +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/icache_loongarch.cpp b/src/hotspot/cpu/loongarch/icache_loongarch.cpp +--- a/src/hotspot/cpu/loongarch/icache_loongarch.cpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/loongarch/icache_loongarch.cpp 2024-01-31 14:01:11.600762198 +0800 +@@ -0,0 +1,42 @@ ++/* ++ * Copyright (c) 1997, 2010, Oracle and/or its affiliates. All rights reserved. ++ * Copyright (c) 2015, 2021, Loongson Technology. All rights reserved. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ * ++ */ ++ ++#include "precompiled.hpp" ++#include "asm/macroAssembler.hpp" ++#include "runtime/icache.hpp" ++ ++void ICacheStubGenerator::generate_icache_flush(ICache::flush_icache_stub_t* flush_icache_stub) ++{ ++#define __ _masm-> ++ StubCodeMark mark(this, "ICache", "flush_icache_stub"); ++ address start = __ pc(); ++ ++ __ ibar(0); ++ __ ori(V0, RA2, 0); ++ __ jr(RA); ++ ++ *flush_icache_stub = (ICache::flush_icache_stub_t)start; ++#undef __ ++} +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/icache_loongarch.hpp b/src/hotspot/cpu/loongarch/icache_loongarch.hpp +--- a/src/hotspot/cpu/loongarch/icache_loongarch.hpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/loongarch/icache_loongarch.hpp 2024-01-31 14:01:11.600762198 +0800 +@@ -0,0 +1,41 @@ ++/* ++ * Copyright (c) 1997, 2010, Oracle and/or its affiliates. All rights reserved. ++ * Copyright (c) 2015, 2022, Loongson Technology. All rights reserved. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ * ++ */ ++ ++#ifndef CPU_LOONGARCH_ICACHE_LOONGARCH_HPP ++#define CPU_LOONGARCH_ICACHE_LOONGARCH_HPP ++ ++// Interface for updating the instruction cache. Whenever the VM modifies ++// code, part of the processor instruction cache potentially has to be flushed. ++ ++class ICache : public AbstractICache { ++ public: ++ enum { ++ stub_size = 3 * BytesPerInstWord, // Size of the icache flush stub in bytes ++ line_size = 32, // flush instruction affects a dword ++ log2_line_size = 5 // log2(line_size) ++ }; ++}; ++ ++#endif // CPU_LOONGARCH_ICACHE_LOONGARCH_HPP +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/icBuffer_loongarch.cpp b/src/hotspot/cpu/loongarch/icBuffer_loongarch.cpp +--- a/src/hotspot/cpu/loongarch/icBuffer_loongarch.cpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/loongarch/icBuffer_loongarch.cpp 2024-01-31 14:01:11.600762198 +0800 @@ -0,0 +1,100 @@ +/* + * Copyright (c) 1997, 2012, Oracle and/or its affiliates. All rights reserved. @@ -20036,383 +19777,10 @@ index 00000000000..a8f08bbf422 + void* o= (void*)move->data(); + return o; +} -diff --git a/src/hotspot/cpu/loongarch/icache_loongarch.cpp b/src/hotspot/cpu/loongarch/icache_loongarch.cpp -new file mode 100644 -index 00000000000..d577e41f59c ---- /dev/null -+++ b/src/hotspot/cpu/loongarch/icache_loongarch.cpp -@@ -0,0 +1,42 @@ -+/* -+ * Copyright (c) 1997, 2010, Oracle and/or its affiliates. All rights reserved. -+ * Copyright (c) 2015, 2021, Loongson Technology. All rights reserved. -+ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. -+ * -+ * This code is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 only, as -+ * published by the Free Software Foundation. -+ * -+ * This code is distributed in the hope that it will be useful, but WITHOUT -+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -+ * version 2 for more details (a copy is included in the LICENSE file that -+ * accompanied this code). -+ * -+ * You should have received a copy of the GNU General Public License version -+ * 2 along with this work; if not, write to the Free Software Foundation, -+ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. -+ * -+ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA -+ * or visit www.oracle.com if you need additional information or have any -+ * questions. -+ * -+ */ -+ -+#include "precompiled.hpp" -+#include "asm/macroAssembler.hpp" -+#include "runtime/icache.hpp" -+ -+void ICacheStubGenerator::generate_icache_flush(ICache::flush_icache_stub_t* flush_icache_stub) -+{ -+#define __ _masm-> -+ StubCodeMark mark(this, "ICache", "flush_icache_stub"); -+ address start = __ pc(); -+ -+ __ ibar(0); -+ __ ori(V0, RA2, 0); -+ __ jr(RA); -+ -+ *flush_icache_stub = (ICache::flush_icache_stub_t)start; -+#undef __ -+} -diff --git a/src/hotspot/cpu/loongarch/icache_loongarch.hpp b/src/hotspot/cpu/loongarch/icache_loongarch.hpp -new file mode 100644 -index 00000000000..3a180549fc6 ---- /dev/null -+++ b/src/hotspot/cpu/loongarch/icache_loongarch.hpp -@@ -0,0 +1,41 @@ -+/* -+ * Copyright (c) 1997, 2010, Oracle and/or its affiliates. All rights reserved. -+ * Copyright (c) 2015, 2022, Loongson Technology. All rights reserved. -+ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. -+ * -+ * This code is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 only, as -+ * published by the Free Software Foundation. -+ * -+ * This code is distributed in the hope that it will be useful, but WITHOUT -+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -+ * version 2 for more details (a copy is included in the LICENSE file that -+ * accompanied this code). -+ * -+ * You should have received a copy of the GNU General Public License version -+ * 2 along with this work; if not, write to the Free Software Foundation, -+ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. -+ * -+ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA -+ * or visit www.oracle.com if you need additional information or have any -+ * questions. -+ * -+ */ -+ -+#ifndef CPU_LOONGARCH_ICACHE_LOONGARCH_HPP -+#define CPU_LOONGARCH_ICACHE_LOONGARCH_HPP -+ -+// Interface for updating the instruction cache. Whenever the VM modifies -+// code, part of the processor instruction cache potentially has to be flushed. -+ -+class ICache : public AbstractICache { -+ public: -+ enum { -+ stub_size = 3 * BytesPerInstWord, // Size of the icache flush stub in bytes -+ line_size = 32, // flush instruction affects a dword -+ log2_line_size = 5 // log2(line_size) -+ }; -+}; -+ -+#endif // CPU_LOONGARCH_ICACHE_LOONGARCH_HPP -diff --git a/src/hotspot/cpu/loongarch/interp_masm_loongarch.hpp b/src/hotspot/cpu/loongarch/interp_masm_loongarch.hpp -new file mode 100644 -index 00000000000..7dea5deb183 ---- /dev/null -+++ b/src/hotspot/cpu/loongarch/interp_masm_loongarch.hpp -@@ -0,0 +1,270 @@ -+/* -+ * Copyright (c) 2003, 2013, Oracle and/or its affiliates. All rights reserved. -+ * Copyright (c) 2015, 2021, Loongson Technology. All rights reserved. -+ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. -+ * -+ * This code is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 only, as -+ * published by the Free Software Foundation. -+ * -+ * This code is distributed in the hope that it will be useful, but WITHOUT -+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -+ * version 2 for more details (a copy is included in the LICENSE file that -+ * accompanied this code). -+ * -+ * You should have received a copy of the GNU General Public License version -+ * 2 along with this work; if not, write to the Free Software Foundation, -+ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. -+ * -+ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA -+ * or visit www.oracle.com if you need additional information or have any -+ * questions. -+ * -+ */ -+ -+#ifndef CPU_LOONGARCH_INTERP_MASM_LOONGARCH_64_HPP -+#define CPU_LOONGARCH_INTERP_MASM_LOONGARCH_64_HPP -+ -+#include "asm/assembler.hpp" -+#include "asm/macroAssembler.hpp" -+#include "asm/macroAssembler.inline.hpp" -+#include "interpreter/invocationCounter.hpp" -+#include "runtime/frame.hpp" -+ -+// This file specializes the assember with interpreter-specific macros -+ -+typedef ByteSize (*OffsetFunction)(uint); -+ -+class InterpreterMacroAssembler: public MacroAssembler { -+ private: -+ -+ Register _locals_register; // register that contains the pointer to the locals -+ Register _bcp_register; // register that contains the bcp -+ -+ protected: -+ // Interpreter specific version of call_VM_base -+ virtual void call_VM_leaf_base(address entry_point, -+ int number_of_arguments); -+ -+ virtual void call_VM_base(Register oop_result, -+ Register java_thread, -+ Register last_java_sp, -+ address entry_point, -+ int number_of_arguments, -+ bool check_exceptions); -+ -+ // base routine for all dispatches -+ void dispatch_base(TosState state, address* table, bool verifyoop = true, bool generate_poll = false); -+ -+ public: -+ void jump_to_entry(address entry); -+ // narrow int return value -+ void narrow(Register result); -+ -+ InterpreterMacroAssembler(CodeBuffer* code) : MacroAssembler(code), _locals_register(LVP), _bcp_register(BCP) {} -+ -+ void get_2_byte_integer_at_bcp(Register reg, Register tmp, int offset); -+ void get_4_byte_integer_at_bcp(Register reg, int offset); -+ -+ virtual void check_and_handle_popframe(Register java_thread); -+ virtual void check_and_handle_earlyret(Register java_thread); -+ -+ void load_earlyret_value(TosState state); -+ -+ // Interpreter-specific registers -+ void save_bcp() { -+ st_d(BCP, FP, frame::interpreter_frame_bcp_offset * wordSize); -+ } -+ -+ void restore_bcp() { -+ ld_d(BCP, FP, frame::interpreter_frame_bcp_offset * wordSize); -+ } -+ -+ void restore_locals() { -+ ld_d(LVP, FP, frame::interpreter_frame_locals_offset * wordSize); -+ } -+ -+ // Helpers for runtime call arguments/results -+ void get_method(Register reg) { -+ ld_d(reg, FP, frame::interpreter_frame_method_offset * wordSize); -+ } -+ -+ void get_const(Register reg){ -+ get_method(reg); -+ ld_d(reg, reg, in_bytes(Method::const_offset())); -+ } -+ -+ void get_constant_pool(Register reg) { -+ get_const(reg); -+ ld_d(reg, reg, in_bytes(ConstMethod::constants_offset())); -+ } -+ -+ void get_constant_pool_cache(Register reg) { -+ get_constant_pool(reg); -+ ld_d(reg, reg, ConstantPool::cache_offset_in_bytes()); -+ } -+ -+ void get_cpool_and_tags(Register cpool, Register tags) { -+ get_constant_pool(cpool); -+ ld_d(tags, cpool, ConstantPool::tags_offset_in_bytes()); -+ } -+ -+ void get_unsigned_2_byte_index_at_bcp(Register reg, int bcp_offset); -+ void get_cache_and_index_at_bcp(Register cache, Register index, int bcp_offset, size_t index_size = sizeof(u2)); -+ void get_cache_and_index_and_bytecode_at_bcp(Register cache, Register index, Register bytecode, int byte_no, int bcp_offset, size_t index_size = sizeof(u2)); -+ void get_cache_entry_pointer_at_bcp(Register cache, Register tmp, int bcp_offset, size_t index_size = sizeof(u2)); -+ void get_cache_index_at_bcp(Register index, int bcp_offset, size_t index_size = sizeof(u2)); -+ void get_method_counters(Register method, Register mcs, Label& skip); -+ -+ // load cpool->resolved_references(index); -+ void load_resolved_reference_at_index(Register result, Register index, Register tmp); -+ -+ // load cpool->resolved_klass_at(index) -+ void load_resolved_klass_at_index(Register cpool, // the constant pool (corrupted on return) -+ Register index, // the constant pool index (corrupted on return) -+ Register klass); // contains the Klass on return -+ -+ void load_resolved_method_at_index(int byte_no, -+ Register method, -+ Register cache, -+ Register index); -+ -+ void pop_ptr( Register r = FSR); -+ void pop_i( Register r = FSR); -+ void pop_l( Register r = FSR); -+ void pop_f(FloatRegister r = FSF); -+ void pop_d(FloatRegister r = FSF); -+ -+ void push_ptr( Register r = FSR); -+ void push_i( Register r = FSR); -+ void push_l( Register r = FSR); -+ void push_f(FloatRegister r = FSF); -+ void push_d(FloatRegister r = FSF); -+ -+ void pop(Register r ) { ((MacroAssembler*)this)->pop(r); } -+ -+ void push(Register r ) { ((MacroAssembler*)this)->push(r); } -+ -+ void pop(TosState state); // transition vtos -> state -+ void push(TosState state); // transition state -> vtos -+ -+ void empty_expression_stack() { -+ ld_d(SP, FP, frame::interpreter_frame_monitor_block_top_offset * wordSize); -+ // NULL last_sp until next java call -+ st_d(R0, FP, frame::interpreter_frame_last_sp_offset * wordSize); -+ } -+ -+ // Super call_VM calls - correspond to MacroAssembler::call_VM(_leaf) calls -+ void load_ptr(int n, Register val); -+ void store_ptr(int n, Register val); -+ -+ // Generate a subtype check: branch to ok_is_subtype if sub_klass is -+ // a subtype of super_klass. -+ //void gen_subtype_check( Register sub_klass, Label &ok_is_subtype ); -+ void gen_subtype_check( Register Rsup_klass, Register sub_klass, Label &ok_is_subtype ); -+ -+ // Dispatching -+ void dispatch_prolog(TosState state, int step = 0); -+ void dispatch_epilog(TosState state, int step = 0); -+ void dispatch_only(TosState state, bool generate_poll = false); -+ void dispatch_only_normal(TosState state); -+ void dispatch_only_noverify(TosState state); -+ void dispatch_next(TosState state, int step = 0, bool generate_poll = false); -+ void dispatch_via (TosState state, address* table); -+ -+ // jump to an invoked target -+ void prepare_to_jump_from_interpreted(); -+ void jump_from_interpreted(Register method, Register temp); -+ -+ -+ // Returning from interpreted functions -+ // -+ // Removes the current activation (incl. unlocking of monitors) -+ // and sets up the return address. This code is also used for -+ // exception unwindwing. In that case, we do not want to throw -+ // IllegalMonitorStateExceptions, since that might get us into an -+ // infinite rethrow exception loop. -+ // Additionally this code is used for popFrame and earlyReturn. -+ // In popFrame case we want to skip throwing an exception, -+ // installing an exception, and notifying jvmdi. -+ // In earlyReturn case we only want to skip throwing an exception -+ // and installing an exception. -+ void remove_activation(TosState state, Register ret_addr, -+ bool throw_monitor_exception = true, -+ bool install_monitor_exception = true, -+ bool notify_jvmdi = true); -+ -+ // Object locking -+ void lock_object (Register lock_reg); -+ void unlock_object(Register lock_reg); -+ -+ // Interpreter profiling operations -+ void set_method_data_pointer_for_bcp(); -+ void test_method_data_pointer(Register mdp, Label& zero_continue); -+ void verify_method_data_pointer(); -+ -+ void set_mdp_data_at(Register mdp_in, int constant, Register value); -+ void increment_mdp_data_at(Address data, bool decrement = false); -+ void increment_mdp_data_at(Register mdp_in, int constant, -+ bool decrement = false); -+ void increment_mdp_data_at(Register mdp_in, Register reg, int constant, -+ bool decrement = false); -+ void increment_mask_and_jump(Address counter_addr, -+ int increment, Address mask, -+ Register scratch, bool preloaded, -+ Condition cond, Label* where); -+ void set_mdp_flag_at(Register mdp_in, int flag_constant); -+ void test_mdp_data_at(Register mdp_in, int offset, Register value, -+ Register test_value_out, -+ Label& not_equal_continue); -+ -+ void record_klass_in_profile(Register receiver, Register mdp, -+ Register reg2, bool is_virtual_call); -+ void record_klass_in_profile_helper(Register receiver, Register mdp, -+ Register reg2, int start_row, -+ Label& done, bool is_virtual_call); -+ -+ void record_item_in_profile_helper(Register item, Register mdp, -+ Register reg2, int start_row, Label& done, int total_rows, -+ OffsetFunction item_offset_fn, OffsetFunction item_count_offset_fn, -+ int non_profiled_offset); -+ void update_mdp_by_offset(Register mdp_in, int offset_of_offset); -+ void update_mdp_by_offset(Register mdp_in, Register reg, int offset_of_disp); -+ void update_mdp_by_constant(Register mdp_in, int constant); -+ void update_mdp_for_ret(Register return_bci); -+ -+ void profile_taken_branch(Register mdp, Register bumped_count); -+ void profile_not_taken_branch(Register mdp); -+ void profile_call(Register mdp); -+ void profile_final_call(Register mdp); -+ void profile_virtual_call(Register receiver, Register mdp, -+ Register scratch2, -+ bool receiver_can_be_null = false); -+ void profile_ret(Register return_bci, Register mdp); -+ void profile_null_seen(Register mdp); -+ void profile_typecheck(Register mdp, Register klass, Register scratch); -+ void profile_typecheck_failed(Register mdp); -+ void profile_switch_default(Register mdp); -+ void profile_switch_case(Register index_in_scratch, Register mdp, -+ Register scratch2); -+ -+ // Debugging -+ // only if +VerifyOops && state == atos -+ void verify_oop(Register reg, TosState state = atos); -+ // only if +VerifyFPU && (state == ftos || state == dtos) -+ void verify_FPU(int stack_depth, TosState state = ftos); -+ -+ void profile_obj_type(Register obj, const Address& mdo_addr); -+ void profile_arguments_type(Register mdp, Register callee, Register tmp, bool is_virtual); -+ void profile_return_type(Register mdp, Register ret, Register tmp); -+ void profile_parameters_type(Register mdp, Register tmp1, Register tmp2); -+ -+ typedef enum { NotifyJVMTI, SkipNotifyJVMTI } NotifyMethodExitMode; -+ -+ // support for jvmti/dtrace -+ void notify_method_entry(); -+ void notify_method_exit(TosState state, NotifyMethodExitMode mode); -+}; -+ -+#endif // CPU_LOONGARCH_INTERP_MASM_LOONGARCH_64_HPP -diff --git a/src/hotspot/cpu/loongarch/interp_masm_loongarch_64.cpp b/src/hotspot/cpu/loongarch/interp_masm_loongarch_64.cpp -new file mode 100644 -index 00000000000..fa65d10765c ---- /dev/null -+++ b/src/hotspot/cpu/loongarch/interp_masm_loongarch_64.cpp -@@ -0,0 +1,2040 @@ +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/interp_masm_loongarch_64.cpp b/src/hotspot/cpu/loongarch/interp_masm_loongarch_64.cpp +--- a/src/hotspot/cpu/loongarch/interp_masm_loongarch_64.cpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/loongarch/interp_masm_loongarch_64.cpp 2024-01-31 14:01:11.600762198 +0800 +@@ -0,0 +1,2040 @@ +/* + * Copyright (c) 2003, 2013, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 2015, 2021, Loongson Technology. All rights reserved. @@ -21294,13 +20662,13 @@ index 00000000000..fa65d10765c + + if (PrintBiasedLockingStatistics) { + Label succ, fail; -+ cmpxchg(Address(scr_reg, 0), tmp_reg, lock_reg, AT, true, false, succ, &fail); ++ cmpxchg(Address(scr_reg, 0), tmp_reg, lock_reg, AT, true, true /* acquire */, succ, &fail); + bind(succ); + atomic_inc32((address)BiasedLocking::fast_path_entry_count_addr(), 1, AT, scr_reg); + b(done); + bind(fail); + } else { -+ cmpxchg(Address(scr_reg, 0), tmp_reg, lock_reg, AT, true, false, done); ++ cmpxchg(Address(scr_reg, 0), tmp_reg, lock_reg, AT, true, true /* acquire */, done); + } + + // Test if the oopMark is an obvious stack pointer, i.e., @@ -21374,7 +20742,7 @@ index 00000000000..fa65d10765c + beqz(hdr_reg, done); + + // Atomic swap back the old header -+ cmpxchg(Address(scr_reg, 0), tmp_reg, hdr_reg, AT, false, false, done); ++ cmpxchg(Address(scr_reg, 0), tmp_reg, hdr_reg, AT, false, true /* acquire */, done); + + // Call the runtime routine for slow case. + st_d(scr_reg, lock_reg, BasicObjectLock::obj_offset_in_bytes()); // restore obj @@ -22453,15 +21821,13 @@ index 00000000000..fa65d10765c + unimplemented(); + } +} -diff --git a/src/hotspot/cpu/loongarch/interpreterRT_loongarch.hpp b/src/hotspot/cpu/loongarch/interpreterRT_loongarch.hpp -new file mode 100644 -index 00000000000..d53d951a160 ---- /dev/null -+++ b/src/hotspot/cpu/loongarch/interpreterRT_loongarch.hpp -@@ -0,0 +1,62 @@ +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/interp_masm_loongarch.hpp b/src/hotspot/cpu/loongarch/interp_masm_loongarch.hpp +--- a/src/hotspot/cpu/loongarch/interp_masm_loongarch.hpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/loongarch/interp_masm_loongarch.hpp 2024-01-31 14:01:11.600762198 +0800 +@@ -0,0 +1,270 @@ +/* -+ * Copyright (c) 1998, 2010, Oracle and/or its affiliates. All rights reserved. -+ * Copyright (c) 2015, 2022, Loongson Technology. All rights reserved. ++ * Copyright (c) 2003, 2013, Oracle and/or its affiliates. All rights reserved. ++ * Copyright (c) 2015, 2021, Loongson Technology. All rights reserved. + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. + * + * This code is free software; you can redistribute it and/or modify it @@ -22484,48 +21850,254 @@ index 00000000000..d53d951a160 + * + */ + -+#ifndef CPU_LOONGARCH_INTERPRETERRT_LOONGARCH_HPP -+#define CPU_LOONGARCH_INTERPRETERRT_LOONGARCH_HPP ++#ifndef CPU_LOONGARCH_INTERP_MASM_LOONGARCH_64_HPP ++#define CPU_LOONGARCH_INTERP_MASM_LOONGARCH_64_HPP + -+// This is included in the middle of class Interpreter. -+// Do not include files here. ++#include "asm/assembler.hpp" ++#include "asm/macroAssembler.hpp" ++#include "asm/macroAssembler.inline.hpp" ++#include "interpreter/invocationCounter.hpp" ++#include "runtime/frame.hpp" + -+// native method calls ++// This file specializes the assember with interpreter-specific macros + -+class SignatureHandlerGenerator: public NativeSignatureIterator { ++typedef ByteSize (*OffsetFunction)(uint); ++ ++class InterpreterMacroAssembler: public MacroAssembler { + private: -+ MacroAssembler* _masm; -+ unsigned int _num_fp_args; -+ unsigned int _num_int_args; -+ int _stack_offset; + -+ void move(int from_offset, int to_offset); -+ void box(int from_offset, int to_offset); -+ void pass_int(); -+ void pass_long(); -+ void pass_object(); -+ void pass_float(); -+ void pass_double(); ++ Register _locals_register; // register that contains the pointer to the locals ++ Register _bcp_register; // register that contains the bcp ++ ++ protected: ++ // Interpreter specific version of call_VM_base ++ virtual void call_VM_leaf_base(address entry_point, ++ int number_of_arguments); ++ ++ virtual void call_VM_base(Register oop_result, ++ Register java_thread, ++ Register last_java_sp, ++ address entry_point, ++ int number_of_arguments, ++ bool check_exceptions); ++ ++ // base routine for all dispatches ++ void dispatch_base(TosState state, address* table, bool verifyoop = true, bool generate_poll = false); + + public: -+ // Creation -+ SignatureHandlerGenerator(const methodHandle& method, CodeBuffer* buffer); ++ void jump_to_entry(address entry); ++ // narrow int return value ++ void narrow(Register result); + -+ // Code generation -+ void generate(uint64_t fingerprint); ++ InterpreterMacroAssembler(CodeBuffer* code) : MacroAssembler(code), _locals_register(LVP), _bcp_register(BCP) {} + -+ // Code generation support -+ static Register from(); -+ static Register to(); -+ static Register temp(); ++ void get_2_byte_integer_at_bcp(Register reg, Register tmp, int offset); ++ void get_4_byte_integer_at_bcp(Register reg, int offset); ++ ++ virtual void check_and_handle_popframe(Register java_thread); ++ virtual void check_and_handle_earlyret(Register java_thread); ++ ++ void load_earlyret_value(TosState state); ++ ++ // Interpreter-specific registers ++ void save_bcp() { ++ st_d(BCP, FP, frame::interpreter_frame_bcp_offset * wordSize); ++ } ++ ++ void restore_bcp() { ++ ld_d(BCP, FP, frame::interpreter_frame_bcp_offset * wordSize); ++ } ++ ++ void restore_locals() { ++ ld_d(LVP, FP, frame::interpreter_frame_locals_offset * wordSize); ++ } ++ ++ // Helpers for runtime call arguments/results ++ void get_method(Register reg) { ++ ld_d(reg, FP, frame::interpreter_frame_method_offset * wordSize); ++ } ++ ++ void get_const(Register reg){ ++ get_method(reg); ++ ld_d(reg, reg, in_bytes(Method::const_offset())); ++ } ++ ++ void get_constant_pool(Register reg) { ++ get_const(reg); ++ ld_d(reg, reg, in_bytes(ConstMethod::constants_offset())); ++ } ++ ++ void get_constant_pool_cache(Register reg) { ++ get_constant_pool(reg); ++ ld_d(reg, reg, ConstantPool::cache_offset_in_bytes()); ++ } ++ ++ void get_cpool_and_tags(Register cpool, Register tags) { ++ get_constant_pool(cpool); ++ ld_d(tags, cpool, ConstantPool::tags_offset_in_bytes()); ++ } ++ ++ void get_unsigned_2_byte_index_at_bcp(Register reg, int bcp_offset); ++ void get_cache_and_index_at_bcp(Register cache, Register index, int bcp_offset, size_t index_size = sizeof(u2)); ++ void get_cache_and_index_and_bytecode_at_bcp(Register cache, Register index, Register bytecode, int byte_no, int bcp_offset, size_t index_size = sizeof(u2)); ++ void get_cache_entry_pointer_at_bcp(Register cache, Register tmp, int bcp_offset, size_t index_size = sizeof(u2)); ++ void get_cache_index_at_bcp(Register index, int bcp_offset, size_t index_size = sizeof(u2)); ++ void get_method_counters(Register method, Register mcs, Label& skip); ++ ++ // load cpool->resolved_references(index); ++ void load_resolved_reference_at_index(Register result, Register index, Register tmp); ++ ++ // load cpool->resolved_klass_at(index) ++ void load_resolved_klass_at_index(Register cpool, // the constant pool (corrupted on return) ++ Register index, // the constant pool index (corrupted on return) ++ Register klass); // contains the Klass on return ++ ++ void load_resolved_method_at_index(int byte_no, ++ Register method, ++ Register cache, ++ Register index); ++ ++ void pop_ptr( Register r = FSR); ++ void pop_i( Register r = FSR); ++ void pop_l( Register r = FSR); ++ void pop_f(FloatRegister r = FSF); ++ void pop_d(FloatRegister r = FSF); ++ ++ void push_ptr( Register r = FSR); ++ void push_i( Register r = FSR); ++ void push_l( Register r = FSR); ++ void push_f(FloatRegister r = FSF); ++ void push_d(FloatRegister r = FSF); ++ ++ void pop(Register r ) { ((MacroAssembler*)this)->pop(r); } ++ ++ void push(Register r ) { ((MacroAssembler*)this)->push(r); } ++ ++ void pop(TosState state); // transition vtos -> state ++ void push(TosState state); // transition state -> vtos ++ ++ void empty_expression_stack() { ++ ld_d(SP, FP, frame::interpreter_frame_monitor_block_top_offset * wordSize); ++ // NULL last_sp until next java call ++ st_d(R0, FP, frame::interpreter_frame_last_sp_offset * wordSize); ++ } ++ ++ // Super call_VM calls - correspond to MacroAssembler::call_VM(_leaf) calls ++ void load_ptr(int n, Register val); ++ void store_ptr(int n, Register val); ++ ++ // Generate a subtype check: branch to ok_is_subtype if sub_klass is ++ // a subtype of super_klass. ++ //void gen_subtype_check( Register sub_klass, Label &ok_is_subtype ); ++ void gen_subtype_check( Register Rsup_klass, Register sub_klass, Label &ok_is_subtype ); ++ ++ // Dispatching ++ void dispatch_prolog(TosState state, int step = 0); ++ void dispatch_epilog(TosState state, int step = 0); ++ void dispatch_only(TosState state, bool generate_poll = false); ++ void dispatch_only_normal(TosState state); ++ void dispatch_only_noverify(TosState state); ++ void dispatch_next(TosState state, int step = 0, bool generate_poll = false); ++ void dispatch_via (TosState state, address* table); ++ ++ // jump to an invoked target ++ void prepare_to_jump_from_interpreted(); ++ void jump_from_interpreted(Register method, Register temp); ++ ++ ++ // Returning from interpreted functions ++ // ++ // Removes the current activation (incl. unlocking of monitors) ++ // and sets up the return address. This code is also used for ++ // exception unwindwing. In that case, we do not want to throw ++ // IllegalMonitorStateExceptions, since that might get us into an ++ // infinite rethrow exception loop. ++ // Additionally this code is used for popFrame and earlyReturn. ++ // In popFrame case we want to skip throwing an exception, ++ // installing an exception, and notifying jvmdi. ++ // In earlyReturn case we only want to skip throwing an exception ++ // and installing an exception. ++ void remove_activation(TosState state, Register ret_addr, ++ bool throw_monitor_exception = true, ++ bool install_monitor_exception = true, ++ bool notify_jvmdi = true); ++ ++ // Object locking ++ void lock_object (Register lock_reg); ++ void unlock_object(Register lock_reg); ++ ++ // Interpreter profiling operations ++ void set_method_data_pointer_for_bcp(); ++ void test_method_data_pointer(Register mdp, Label& zero_continue); ++ void verify_method_data_pointer(); ++ ++ void set_mdp_data_at(Register mdp_in, int constant, Register value); ++ void increment_mdp_data_at(Address data, bool decrement = false); ++ void increment_mdp_data_at(Register mdp_in, int constant, ++ bool decrement = false); ++ void increment_mdp_data_at(Register mdp_in, Register reg, int constant, ++ bool decrement = false); ++ void increment_mask_and_jump(Address counter_addr, ++ int increment, Address mask, ++ Register scratch, bool preloaded, ++ Condition cond, Label* where); ++ void set_mdp_flag_at(Register mdp_in, int flag_constant); ++ void test_mdp_data_at(Register mdp_in, int offset, Register value, ++ Register test_value_out, ++ Label& not_equal_continue); ++ ++ void record_klass_in_profile(Register receiver, Register mdp, ++ Register reg2, bool is_virtual_call); ++ void record_klass_in_profile_helper(Register receiver, Register mdp, ++ Register reg2, int start_row, ++ Label& done, bool is_virtual_call); ++ ++ void record_item_in_profile_helper(Register item, Register mdp, ++ Register reg2, int start_row, Label& done, int total_rows, ++ OffsetFunction item_offset_fn, OffsetFunction item_count_offset_fn, ++ int non_profiled_offset); ++ void update_mdp_by_offset(Register mdp_in, int offset_of_offset); ++ void update_mdp_by_offset(Register mdp_in, Register reg, int offset_of_disp); ++ void update_mdp_by_constant(Register mdp_in, int constant); ++ void update_mdp_for_ret(Register return_bci); ++ ++ void profile_taken_branch(Register mdp, Register bumped_count); ++ void profile_not_taken_branch(Register mdp); ++ void profile_call(Register mdp); ++ void profile_final_call(Register mdp); ++ void profile_virtual_call(Register receiver, Register mdp, ++ Register scratch2, ++ bool receiver_can_be_null = false); ++ void profile_ret(Register return_bci, Register mdp); ++ void profile_null_seen(Register mdp); ++ void profile_typecheck(Register mdp, Register klass, Register scratch); ++ void profile_typecheck_failed(Register mdp); ++ void profile_switch_default(Register mdp); ++ void profile_switch_case(Register index_in_scratch, Register mdp, ++ Register scratch2); ++ ++ // Debugging ++ // only if +VerifyOops && state == atos ++ void verify_oop(Register reg, TosState state = atos); ++ // only if +VerifyFPU && (state == ftos || state == dtos) ++ void verify_FPU(int stack_depth, TosState state = ftos); ++ ++ void profile_obj_type(Register obj, const Address& mdo_addr); ++ void profile_arguments_type(Register mdp, Register callee, Register tmp, bool is_virtual); ++ void profile_return_type(Register mdp, Register ret, Register tmp); ++ void profile_parameters_type(Register mdp, Register tmp1, Register tmp2); ++ ++ typedef enum { NotifyJVMTI, SkipNotifyJVMTI } NotifyMethodExitMode; ++ ++ // support for jvmti/dtrace ++ void notify_method_entry(); ++ void notify_method_exit(TosState state, NotifyMethodExitMode mode); +}; + -+#endif // CPU_LOONGARCH_INTERPRETERRT_LOONGARCH_HPP -diff --git a/src/hotspot/cpu/loongarch/interpreterRT_loongarch_64.cpp b/src/hotspot/cpu/loongarch/interpreterRT_loongarch_64.cpp -new file mode 100644 -index 00000000000..85a199e760d ---- /dev/null -+++ b/src/hotspot/cpu/loongarch/interpreterRT_loongarch_64.cpp ++#endif // CPU_LOONGARCH_INTERP_MASM_LOONGARCH_64_HPP +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/interpreterRT_loongarch_64.cpp b/src/hotspot/cpu/loongarch/interpreterRT_loongarch_64.cpp +--- a/src/hotspot/cpu/loongarch/interpreterRT_loongarch_64.cpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/loongarch/interpreterRT_loongarch_64.cpp 2024-01-31 14:01:11.600762198 +0800 @@ -0,0 +1,282 @@ +/* + * Copyright (c) 2003, 2012, Oracle and/or its affiliates. All rights reserved. @@ -22809,11 +22381,75 @@ index 00000000000..85a199e760d + // return result handler + return Interpreter::result_handler(m->result_type()); +JRT_END -diff --git a/src/hotspot/cpu/loongarch/javaFrameAnchor_loongarch.hpp b/src/hotspot/cpu/loongarch/javaFrameAnchor_loongarch.hpp -new file mode 100644 -index 00000000000..048107c2425 ---- /dev/null -+++ b/src/hotspot/cpu/loongarch/javaFrameAnchor_loongarch.hpp +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/interpreterRT_loongarch.hpp b/src/hotspot/cpu/loongarch/interpreterRT_loongarch.hpp +--- a/src/hotspot/cpu/loongarch/interpreterRT_loongarch.hpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/loongarch/interpreterRT_loongarch.hpp 2024-01-31 14:01:11.600762198 +0800 +@@ -0,0 +1,62 @@ ++/* ++ * Copyright (c) 1998, 2010, Oracle and/or its affiliates. All rights reserved. ++ * Copyright (c) 2015, 2022, Loongson Technology. All rights reserved. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ * ++ */ ++ ++#ifndef CPU_LOONGARCH_INTERPRETERRT_LOONGARCH_HPP ++#define CPU_LOONGARCH_INTERPRETERRT_LOONGARCH_HPP ++ ++// This is included in the middle of class Interpreter. ++// Do not include files here. ++ ++// native method calls ++ ++class SignatureHandlerGenerator: public NativeSignatureIterator { ++ private: ++ MacroAssembler* _masm; ++ unsigned int _num_fp_args; ++ unsigned int _num_int_args; ++ int _stack_offset; ++ ++ void move(int from_offset, int to_offset); ++ void box(int from_offset, int to_offset); ++ void pass_int(); ++ void pass_long(); ++ void pass_object(); ++ void pass_float(); ++ void pass_double(); ++ ++ public: ++ // Creation ++ SignatureHandlerGenerator(const methodHandle& method, CodeBuffer* buffer); ++ ++ // Code generation ++ void generate(uint64_t fingerprint); ++ ++ // Code generation support ++ static Register from(); ++ static Register to(); ++ static Register temp(); ++}; ++ ++#endif // CPU_LOONGARCH_INTERPRETERRT_LOONGARCH_HPP +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/javaFrameAnchor_loongarch.hpp b/src/hotspot/cpu/loongarch/javaFrameAnchor_loongarch.hpp +--- a/src/hotspot/cpu/loongarch/javaFrameAnchor_loongarch.hpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/loongarch/javaFrameAnchor_loongarch.hpp 2024-01-31 14:01:11.600762198 +0800 @@ -0,0 +1,87 @@ +/* + * Copyright (c) 2002, 2010, Oracle and/or its affiliates. All rights reserved. @@ -22902,11 +22538,9 @@ index 00000000000..048107c2425 + void set_last_Java_fp(intptr_t* fp) { _last_Java_fp = fp; } + +#endif // CPU_LOONGARCH_JAVAFRAMEANCHOR_LOONGARCH_HPP -diff --git a/src/hotspot/cpu/loongarch/jniFastGetField_loongarch_64.cpp b/src/hotspot/cpu/loongarch/jniFastGetField_loongarch_64.cpp -new file mode 100644 -index 00000000000..5b08280921c ---- /dev/null -+++ b/src/hotspot/cpu/loongarch/jniFastGetField_loongarch_64.cpp +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/jniFastGetField_loongarch_64.cpp b/src/hotspot/cpu/loongarch/jniFastGetField_loongarch_64.cpp +--- a/src/hotspot/cpu/loongarch/jniFastGetField_loongarch_64.cpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/loongarch/jniFastGetField_loongarch_64.cpp 2024-01-31 14:01:11.600762198 +0800 @@ -0,0 +1,197 @@ +/* + * Copyright (c) 2004, 2010, Oracle and/or its affiliates. All rights reserved. @@ -23105,11 +22739,9 @@ index 00000000000..5b08280921c +address JNI_FastGetField::generate_fast_get_double_field() { + return generate_fast_get_int_field0(T_DOUBLE); +} -diff --git a/src/hotspot/cpu/loongarch/jniTypes_loongarch.hpp b/src/hotspot/cpu/loongarch/jniTypes_loongarch.hpp -new file mode 100644 -index 00000000000..0ee04e042b5 ---- /dev/null -+++ b/src/hotspot/cpu/loongarch/jniTypes_loongarch.hpp +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/jniTypes_loongarch.hpp b/src/hotspot/cpu/loongarch/jniTypes_loongarch.hpp +--- a/src/hotspot/cpu/loongarch/jniTypes_loongarch.hpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/loongarch/jniTypes_loongarch.hpp 2024-01-31 14:01:11.600762198 +0800 @@ -0,0 +1,143 @@ +/* + * Copyright (c) 1998, 2010, Oracle and/or its affiliates. All rights reserved. @@ -23254,11 +22886,9 @@ index 00000000000..0ee04e042b5 +}; + +#endif // CPU_LOONGARCH_JNITYPES_LOONGARCH_HPP -diff --git a/src/hotspot/cpu/loongarch/jvmciCodeInstaller_loongarch.cpp b/src/hotspot/cpu/loongarch/jvmciCodeInstaller_loongarch.cpp -new file mode 100644 -index 00000000000..eb75830ec9c ---- /dev/null -+++ b/src/hotspot/cpu/loongarch/jvmciCodeInstaller_loongarch.cpp +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/jvmciCodeInstaller_loongarch.cpp b/src/hotspot/cpu/loongarch/jvmciCodeInstaller_loongarch.cpp +--- a/src/hotspot/cpu/loongarch/jvmciCodeInstaller_loongarch.cpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/loongarch/jvmciCodeInstaller_loongarch.cpp 2024-01-31 14:01:11.600762198 +0800 @@ -0,0 +1,202 @@ +/* + * Copyright (c) 2015, 2022, Oracle and/or its affiliates. All rights reserved. @@ -23462,43 +23092,10 @@ index 00000000000..eb75830ec9c +bool CodeInstaller::is_general_purpose_reg(VMReg hotspotRegister) { + return !hotspotRegister->is_FloatRegister(); +} -diff --git a/src/hotspot/cpu/loongarch/loongarch.ad b/src/hotspot/cpu/loongarch/loongarch.ad -new file mode 100644 -index 00000000000..80dff0c7626 ---- /dev/null -+++ b/src/hotspot/cpu/loongarch/loongarch.ad -@@ -0,0 +1,25 @@ -+// -+// Copyright (c) 2011, 2012, Oracle and/or its affiliates. All rights reserved. -+// Copyright (c) 2015, 2021, Loongson Technology. All rights reserved. -+// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. -+// -+// This code is free software; you can redistribute it and/or modify it -+// under the terms of the GNU General Public License version 2 only, as -+// published by the Free Software Foundation. -+// -+// This code is distributed in the hope that it will be useful, but WITHOUT -+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -+// version 2 for more details (a copy is included in the LICENSE file that -+// accompanied this code). -+// -+// You should have received a copy of the GNU General Public License version -+// 2 along with this work; if not, write to the Free Software Foundation, -+// Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. -+// -+// Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA -+// or visit www.oracle.com if you need additional information or have any -+// questions. -+// -+// -+ -diff --git a/src/hotspot/cpu/loongarch/loongarch_64.ad b/src/hotspot/cpu/loongarch/loongarch_64.ad -new file mode 100644 -index 00000000000..703aeafc855 ---- /dev/null -+++ b/src/hotspot/cpu/loongarch/loongarch_64.ad -@@ -0,0 +1,15672 @@ +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/loongarch_64.ad b/src/hotspot/cpu/loongarch/loongarch_64.ad +--- a/src/hotspot/cpu/loongarch/loongarch_64.ad 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/loongarch/loongarch_64.ad 2024-01-31 14:01:11.600762198 +0800 +@@ -0,0 +1,15678 @@ +// +// Copyright (c) 2003, 2013, Oracle and/or its affiliates. All rights reserved. +// Copyright (c) 2015, 2022, Loongson Technology. All rights reserved. @@ -25615,7 +25212,7 @@ index 00000000000..703aeafc855 + if (C->stub_function() == NULL && BarrierSet::barrier_set()->barrier_set_nmethod() != NULL) { + st->print("\n\t"); + st->print("ld_d T1, guard, 0\n\t"); -+ st->print("dbar 0\n\t"); ++ st->print("membar LoadLoad\n\t"); + st->print("ld_d T2, TREG, thread_disarmed_offset\n\t"); + st->print("beq T1, T2, skip\n\t"); + st->print("\n\t"); @@ -29935,6 +29532,7 @@ index 00000000000..703aeafc855 + +instruct membar_storestore() %{ + match(MemBarStoreStore); ++ match(StoreStoreFence); + + ins_cost(400); + format %{ "MEMBAR-storestore @ membar_storestore" %} @@ -33895,13 +33493,13 @@ index 00000000000..703aeafc855 + ins_cost(300); + + // Use the following format syntax -+ format %{ "ILLTRAP ;#@ShouldNotReachHere" %} ++ format %{ "stop; #@ShouldNotReachHere" %} + ins_encode %{ + if (is_reachable()) { -+ // Here we should emit illtrap! -+ __ stop("ShouldNotReachHere"); ++ __ stop(_halt_reason); + } + %} ++ + ins_pipe( pipe_jump ); +%} + @@ -34085,9 +33683,9 @@ index 00000000000..703aeafc855 + Address addr($mem_ptr$$Register, 0); + + if (res != addr.base() && res != oldval && res != newval) { -+ __ cmpxchg32(addr, oldval, newval, res, true, false, true); ++ __ cmpxchg32(addr, oldval, newval, res, true, false, true /* acquire */); + } else { -+ __ cmpxchg32(addr, oldval, newval, AT, true, false, true); ++ __ cmpxchg32(addr, oldval, newval, AT, true, false, true /* acquire */); + __ move(res, AT); + } + %} @@ -34106,9 +33704,9 @@ index 00000000000..703aeafc855 + Address addr($mem_ptr$$Register, 0); + + if (res != addr.base() && res != oldval && res != newval) { -+ __ cmpxchg(addr, oldval, newval, res, false, true); ++ __ cmpxchg(addr, oldval, newval, res, false, true /* acquire */); + } else { -+ __ cmpxchg(addr, oldval, newval, AT, false, true); ++ __ cmpxchg(addr, oldval, newval, AT, false, true /* acquire */); + __ move(res, AT); + } + %} @@ -34127,9 +33725,9 @@ index 00000000000..703aeafc855 + Address addr($mem_ptr$$Register, 0); + + if (res != addr.base() && res != oldval && res != newval) { -+ __ cmpxchg(addr, oldval, newval, res, false, true); ++ __ cmpxchg(addr, oldval, newval, res, false, true /* acquire */); + } else { -+ __ cmpxchg(addr, oldval, newval, AT, false, true); ++ __ cmpxchg(addr, oldval, newval, AT, false, true /* acquire */); + __ move(res, AT); + } + %} @@ -34147,9 +33745,9 @@ index 00000000000..703aeafc855 + Address addr($mem_ptr$$Register, 0); + + if (res != addr.base() && res != oldval && res != newval) { -+ __ cmpxchg32(addr, oldval, newval, res, false, false, true); ++ __ cmpxchg32(addr, oldval, newval, res, false, false, true /* acquire */); + } else { -+ __ cmpxchg32(addr, oldval, newval, AT, false, false, true); ++ __ cmpxchg32(addr, oldval, newval, AT, false, false, true /* acquire */); + __ move(res, AT); + } + %} @@ -34288,14 +33886,14 @@ index 00000000000..703aeafc855 + ins_cost(2 * MEMORY_REF_COST); + effect(TEMP_DEF res); + format %{ -+ "cmpxchg32 $res = $mem, $oldval, $newval\t# if $mem == $oldval then $mem <-- $newval @compareAndExchangeI" ++ "CMPXCHG $res = $mem, $oldval, $newval\t# if $mem == $oldval then $mem <-- $newval @compareAndExchangeI" + %} + ins_encode %{ + Register newval = $newval$$Register; + Register oldval = $oldval$$Register; + Register res = $res$$Register; + Address addr(as_Register($mem$$base)); -+ __ cmpxchg32(addr, oldval, newval, res, true /* sign */, false /* retold */, true /* barrier */, false /* weak */, true /* exchange */); ++ __ cmpxchg32(addr, oldval, newval, res, true /* sign */, false /* retold */, true /* acquire */, false /* weak */, true /* exchange */); + %} + ins_pipe(pipe_slow); +%} @@ -34306,14 +33904,14 @@ index 00000000000..703aeafc855 + ins_cost(2 * MEMORY_REF_COST); + effect(TEMP_DEF res); + format %{ -+ "cmpxchg $res = $mem, $oldval, $newval\t# if $mem == $oldval then $mem <-- $newval @compareAndExchangeL" ++ "CMPXCHG $res = $mem, $oldval, $newval\t# if $mem == $oldval then $mem <-- $newval @compareAndExchangeL" + %} + ins_encode %{ + Register newval = $newval$$Register; + Register oldval = $oldval$$Register; + Register res = $res$$Register; + Address addr(as_Register($mem$$base)); -+ __ cmpxchg(addr, oldval, newval, res, false /* retold */, true /* barrier */, false /* weak */, true /* exchange */); ++ __ cmpxchg(addr, oldval, newval, res, false /* retold */, true /* acquire */, false /* weak */, true /* exchange */); + %} + ins_pipe(pipe_slow); +%} @@ -34324,7 +33922,7 @@ index 00000000000..703aeafc855 + ins_cost(2 * MEMORY_REF_COST); + effect(TEMP_DEF res); + format %{ -+ "cmpxchg $res = $mem, $oldval, $newval\t# if $mem == $oldval then $mem <-- $newval @compareAndExchangeP" ++ "CMPXCHG $res = $mem, $oldval, $newval\t# if $mem == $oldval then $mem <-- $newval @compareAndExchangeP" + %} + ins_encode %{ + Register newval = $newval$$Register; @@ -34342,14 +33940,14 @@ index 00000000000..703aeafc855 + ins_cost(2 * MEMORY_REF_COST); + effect(TEMP_DEF res); + format %{ -+ "cmpxchg32 $res = $mem, $oldval, $newval\t# if $mem == $oldval then $mem <-- $newval @compareAndExchangeN" ++ "CMPXCHG $res = $mem, $oldval, $newval\t# if $mem == $oldval then $mem <-- $newval @compareAndExchangeN" + %} + ins_encode %{ + Register newval = $newval$$Register; + Register oldval = $oldval$$Register; + Register res = $res$$Register; + Address addr(as_Register($mem$$base)); -+ __ cmpxchg32(addr, oldval, newval, res, false /* sign */, false /* retold */, true /* barrier */, false /* weak */, true /* exchange */); ++ __ cmpxchg32(addr, oldval, newval, res, false /* sign */, false /* retold */, true /* acquire */, false /* weak */, true /* exchange */); + %} + ins_pipe(pipe_slow); +%} @@ -34367,9 +33965,9 @@ index 00000000000..703aeafc855 + Register res = $res$$Register; + Address addr(as_Register($mem$$base)); + if (res != addr.base() && res != oldval && res != newval) { -+ __ cmpxchg32(addr, oldval, newval, res, true /* sign */, false /* retold */, true /* barrier */, true /* weak */, false /* exchange */); ++ __ cmpxchg32(addr, oldval, newval, res, true /* sign */, false /* retold */, true /* acquire */, true /* weak */, false /* exchange */); + } else { -+ __ cmpxchg32(addr, oldval, newval, AT, true /* sign */, false /* retold */, true /* barrier */, true /* weak */, false /* exchange */); ++ __ cmpxchg32(addr, oldval, newval, AT, true /* sign */, false /* retold */, true /* acquire */, true /* weak */, false /* exchange */); + __ move(res, AT); + } + %} @@ -34381,7 +33979,7 @@ index 00000000000..703aeafc855 + match(Set res (WeakCompareAndSwapL mem (Binary oldval newval))); + ins_cost(2 * MEMORY_REF_COST); + format %{ -+ "cmpxchg $res = $mem, $oldval, $newval\t# if $mem == $oldval then $mem <-- $newval @WeakCompareAndSwapL" ++ "CMPXCHG $res = $mem, $oldval, $newval\t# if $mem == $oldval then $mem <-- $newval @WeakCompareAndSwapL" + %} + ins_encode %{ + Register newval = $newval$$Register; @@ -34389,9 +33987,9 @@ index 00000000000..703aeafc855 + Register res = $res$$Register; + Address addr(as_Register($mem$$base)); + if (res != addr.base() && res != oldval && res != newval) { -+ __ cmpxchg(addr, oldval, newval, res, false /* retold */, true /* barrier */, true /* weak */, false /* exchange */); ++ __ cmpxchg(addr, oldval, newval, res, false /* retold */, true /* acquire */, true /* weak */, false /* exchange */); + } else { -+ __ cmpxchg(addr, oldval, newval, AT, false /* retold */, true /* barrier */, true /* weak */, false /* exchange */); ++ __ cmpxchg(addr, oldval, newval, AT, false /* retold */, true /* acquire */, true /* weak */, false /* exchange */); + __ move(res, AT); + } + %} @@ -34403,7 +34001,7 @@ index 00000000000..703aeafc855 + match(Set res (WeakCompareAndSwapP mem (Binary oldval newval))); + ins_cost(MEMORY_REF_COST); + format %{ -+ "cmpxchg $res = $mem, $oldval, $newval\t# if $mem == $oldval then $mem <-- $newval @weakCompareAndSwapP" ++ "CMPXCHG $res = $mem, $oldval, $newval\t# if $mem == $oldval then $mem <-- $newval @weakCompareAndSwapP" + %} + ins_encode %{ + Register newval = $newval$$Register; @@ -34411,9 +34009,9 @@ index 00000000000..703aeafc855 + Register res = $res$$Register; + Address addr(as_Register($mem$$base)); + if (res != addr.base() && res != oldval && res != newval) { -+ __ cmpxchg(addr, oldval, newval, res, false /* retold */, false /* barrier */, true /* weak */, false /* exchange */); ++ __ cmpxchg(addr, oldval, newval, res, false /* retold */, false /* acquire */, true /* weak */, false /* exchange */); + } else { -+ __ cmpxchg(addr, oldval, newval, AT, false /* retold */, false /* barrier */, true /* weak */, false /* exchange */); ++ __ cmpxchg(addr, oldval, newval, AT, false /* retold */, false /* acquire */, true /* weak */, false /* exchange */); + __ move(res, AT); + } + %} @@ -34425,7 +34023,7 @@ index 00000000000..703aeafc855 + match(Set res (WeakCompareAndSwapP mem (Binary oldval newval))); + ins_cost(2 * MEMORY_REF_COST); + format %{ -+ "cmpxchg $res = $mem, $oldval, $newval\t# if $mem == $oldval then $mem <-- $newval @weakCompareAndSwapP" ++ "CMPXCHG $res = $mem, $oldval, $newval\t# if $mem == $oldval then $mem <-- $newval @weakCompareAndSwapP" + %} + ins_encode %{ + Register newval = $newval$$Register; @@ -34433,9 +34031,9 @@ index 00000000000..703aeafc855 + Register res = $res$$Register; + Address addr(as_Register($mem$$base)); + if (res != addr.base() && res != oldval && res != newval) { -+ __ cmpxchg(addr, oldval, newval, res, false /* retold */, true /* barrier */, true /* weak */, false /* exchange */); ++ __ cmpxchg(addr, oldval, newval, res, false /* retold */, true /* acquire */, true /* weak */, false /* exchange */); + } else { -+ __ cmpxchg(addr, oldval, newval, AT, false /* retold */, true /* barrier */, true /* weak */, false /* exchange */); ++ __ cmpxchg(addr, oldval, newval, AT, false /* retold */, true /* acquire */, true /* weak */, false /* exchange */); + __ move(res, AT); + } + %} @@ -34447,7 +34045,7 @@ index 00000000000..703aeafc855 + match(Set res (WeakCompareAndSwapN mem (Binary oldval newval))); + ins_cost(2 * MEMORY_REF_COST); + format %{ -+ "cmpxchg32 $res = $mem, $oldval, $newval\t# if $mem == $oldval then $mem <-- $newval @weakCompareAndSwapN" ++ "CMPXCHG $res = $mem, $oldval, $newval\t# if $mem == $oldval then $mem <-- $newval @weakCompareAndSwapN" + %} + ins_encode %{ + Register newval = $newval$$Register; @@ -34455,9 +34053,9 @@ index 00000000000..703aeafc855 + Register res = $res$$Register; + Address addr(as_Register($mem$$base)); + if (res != addr.base() && res != oldval && res != newval) { -+ __ cmpxchg32(addr, oldval, newval, res, false /* sign */, false /* retold */, true /* barrier */, true /* weak */, false /* exchange */); ++ __ cmpxchg32(addr, oldval, newval, res, false /* sign */, false /* retold */, true /* acquire */, true /* weak */, false /* exchange */); + } else { -+ __ cmpxchg32(addr, oldval, newval, AT, false /* sign */, false /* retold */, true /* barrier */, true /* weak */, false /* exchange */); ++ __ cmpxchg32(addr, oldval, newval, AT, false /* sign */, false /* retold */, true /* acquire */, true /* weak */, false /* exchange */); + __ move(res, AT); + } + %} @@ -38696,13 +38294,19 @@ index 00000000000..703aeafc855 + match(Set dst (VectorInsert (Binary dst val) idx)); + format %{ "xvinsert $dst, $val, $idx\t# @insert32B" %} + ins_encode %{ -+ if ($idx$$constant < 16) { -+ __ vinsgr2vr_b($dst$$FloatRegister, $val$$Register, $idx$$constant); -+ } else { -+ __ xvpermi_d($dst$$FloatRegister, $dst$$FloatRegister, 0b01001110); -+ __ vinsgr2vr_b($dst$$FloatRegister, $val$$Register, $idx$$constant-16); -+ __ xvpermi_d($dst$$FloatRegister, $dst$$FloatRegister, 0b01001110); ++ int idx = $idx$$constant; ++ int msbw, lsbw; ++ switch (idx % 4) { ++ case 0: msbw = 7, lsbw = 0; break; ++ case 1: msbw = 15, lsbw = 8; break; ++ case 2: msbw = 23, lsbw = 16; break; ++ case 3: msbw = 31, lsbw = 24; break; ++ default: ++ ShouldNotReachHere(); + } ++ __ xvpickve2gr_w(SCR1, $dst$$FloatRegister, idx >> 2); ++ __ bstrins_w(SCR1, $val$$Register, msbw, lsbw); ++ __ xvinsgr2vr_w($dst$$FloatRegister, SCR1, idx >> 2); + %} + ins_pipe( pipe_slow ); +%} @@ -38712,13 +38316,12 @@ index 00000000000..703aeafc855 + match(Set dst (VectorInsert (Binary dst val) idx)); + format %{ "xvinsert $dst, $val, $idx\t# @insert16S" %} + ins_encode %{ -+ if ($idx$$constant < 8) { -+ __ vinsgr2vr_h($dst$$FloatRegister, $val$$Register, $idx$$constant); -+ } else { -+ __ xvpermi_d($dst$$FloatRegister, $dst$$FloatRegister, 0b01001110); -+ __ vinsgr2vr_h($dst$$FloatRegister, $val$$Register, $idx$$constant-8); -+ __ xvpermi_d($dst$$FloatRegister, $dst$$FloatRegister, 0b01001110); -+ } ++ int idx = $idx$$constant; ++ int msbw = (idx % 2) ? 31 : 15; ++ int lsbw = (idx % 2) ? 16 : 0; ++ __ xvpickve2gr_w(SCR1, $dst$$FloatRegister, idx >> 1); ++ __ bstrins_w(SCR1, $val$$Register, msbw, lsbw); ++ __ xvinsgr2vr_w($dst$$FloatRegister, SCR1, idx >> 1); + %} + ins_pipe( pipe_slow ); +%} @@ -39171,12 +38774,39 @@ index 00000000000..703aeafc855 +// These must follow all instruction definitions as they use the names +// defined in the instructions definitions. + -diff --git a/src/hotspot/cpu/loongarch/macroAssembler_loongarch.cpp b/src/hotspot/cpu/loongarch/macroAssembler_loongarch.cpp -new file mode 100644 -index 00000000000..882c43bf592 ---- /dev/null -+++ b/src/hotspot/cpu/loongarch/macroAssembler_loongarch.cpp -@@ -0,0 +1,3834 @@ +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/loongarch.ad b/src/hotspot/cpu/loongarch/loongarch.ad +--- a/src/hotspot/cpu/loongarch/loongarch.ad 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/loongarch/loongarch.ad 2024-01-31 14:01:11.600762198 +0800 +@@ -0,0 +1,25 @@ ++// ++// Copyright (c) 2011, 2012, Oracle and/or its affiliates. All rights reserved. ++// Copyright (c) 2015, 2021, Loongson Technology. All rights reserved. ++// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++// ++// This code is free software; you can redistribute it and/or modify it ++// under the terms of the GNU General Public License version 2 only, as ++// published by the Free Software Foundation. ++// ++// This code is distributed in the hope that it will be useful, but WITHOUT ++// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++// version 2 for more details (a copy is included in the LICENSE file that ++// accompanied this code). ++// ++// You should have received a copy of the GNU General Public License version ++// 2 along with this work; if not, write to the Free Software Foundation, ++// Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++// ++// Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++// or visit www.oracle.com if you need additional information or have any ++// questions. ++// ++// ++ +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/macroAssembler_loongarch.cpp b/src/hotspot/cpu/loongarch/macroAssembler_loongarch.cpp +--- a/src/hotspot/cpu/loongarch/macroAssembler_loongarch.cpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/loongarch/macroAssembler_loongarch.cpp 2024-01-31 14:01:11.600762198 +0800 +@@ -0,0 +1,3839 @@ +/* + * Copyright (c) 1997, 2014, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 2017, 2022, Loongson Technology. All rights reserved. @@ -39835,7 +39465,7 @@ index 00000000000..882c43bf592 +#else + orr(tmp_reg, TREG, swap_reg); +#endif -+ cmpxchg(Address(obj_reg, 0), swap_reg, tmp_reg, AT, false, false); ++ cmpxchg(Address(obj_reg, 0), swap_reg, tmp_reg, AT, false, true /* acquire */); + if (need_tmp_reg) { + pop(tmp_reg); + } @@ -39880,7 +39510,7 @@ index 00000000000..882c43bf592 +#endif + ld_ptr(swap_reg, saved_mark_addr); + -+ cmpxchg(Address(obj_reg, 0), swap_reg, tmp_reg, AT, false, false); ++ cmpxchg(Address(obj_reg, 0), swap_reg, tmp_reg, AT, false, true /* acquire */); + if (need_tmp_reg) { + pop(tmp_reg); + } @@ -39920,7 +39550,7 @@ index 00000000000..882c43bf592 + push(tmp_reg); + } + load_prototype_header(tmp_reg, obj_reg); -+ cmpxchg(Address(obj_reg, 0), swap_reg, tmp_reg, AT, false, false); ++ cmpxchg(Address(obj_reg, 0), swap_reg, tmp_reg, AT, false, true /* acquire */); + if (need_tmp_reg) { + pop(tmp_reg); + } @@ -40157,22 +39787,11 @@ index 00000000000..882c43bf592 + + +void MacroAssembler::stop(const char* msg) { -+ li(A0, (long)msg); -+ call(CAST_FROM_FN_PTR(address, MacroAssembler::debug), relocInfo::runtime_call_type); -+ brk(17); -+} -+ -+void MacroAssembler::warn(const char* msg) { -+ push_call_clobbered_registers(); -+ li(A0, (long)msg); -+ push(S2); -+ move(S2, SP); // use S2 as a sender SP holder -+ assert(StackAlignmentInBytes == 16, "must be"); -+ bstrins_d(SP, R0, 3, 0); // align stack as required by ABI -+ call(CAST_FROM_FN_PTR(address, MacroAssembler::debug), relocInfo::runtime_call_type); -+ move(SP, S2); // use S2 as a sender SP holder -+ pop(S2); -+ pop_call_clobbered_registers(); ++#ifndef PRODUCT ++ block_comment(msg); ++#endif ++ csrrd(R0, 0); ++ emit_int64((uintptr_t)msg); +} + +void MacroAssembler::increment(Register reg, int imm) { @@ -41012,7 +40631,7 @@ index 00000000000..882c43bf592 +} + +void MacroAssembler::cmpxchg(Address addr, Register oldval, Register newval, -+ Register resflag, bool retold, bool barrier, ++ Register resflag, bool retold, bool acquire, + bool weak, bool exchange) { + assert(oldval != resflag, "oldval != resflag"); + assert(newval != resflag, "newval != resflag"); @@ -41035,8 +40654,11 @@ index 00000000000..882c43bf592 + b(succ); + + bind(fail); -+ if (barrier) -+ membar(LoadLoad); ++ if (acquire) { ++ membar(Assembler::Membar_mask_bits(LoadLoad|LoadStore)); ++ } else { ++ dbar(0x700); ++ } + if (retold && oldval != R0) + move(oldval, resflag); + if (!exchange) { @@ -41046,7 +40668,7 @@ index 00000000000..882c43bf592 +} + +void MacroAssembler::cmpxchg(Address addr, Register oldval, Register newval, -+ Register tmp, bool retold, bool barrier, Label& succ, Label* fail) { ++ Register tmp, bool retold, bool acquire, Label& succ, Label* fail) { + assert(oldval != tmp, "oldval != tmp"); + assert(newval != tmp, "newval != tmp"); + Label again, neq; @@ -41060,8 +40682,11 @@ index 00000000000..882c43bf592 + b(succ); + + bind(neq); -+ if (barrier) -+ membar(LoadLoad); ++ if (acquire) { ++ membar(Assembler::Membar_mask_bits(LoadLoad|LoadStore)); ++ } else { ++ dbar(0x700); ++ } + if (retold && oldval != R0) + move(oldval, tmp); + if (fail) @@ -41069,7 +40694,7 @@ index 00000000000..882c43bf592 +} + +void MacroAssembler::cmpxchg32(Address addr, Register oldval, Register newval, -+ Register resflag, bool sign, bool retold, bool barrier, ++ Register resflag, bool sign, bool retold, bool acquire, + bool weak, bool exchange) { + assert(oldval != resflag, "oldval != resflag"); + assert(newval != resflag, "newval != resflag"); @@ -41094,8 +40719,11 @@ index 00000000000..882c43bf592 + b(succ); + + bind(fail); -+ if (barrier) -+ membar(LoadLoad); ++ if (acquire) { ++ membar(Assembler::Membar_mask_bits(LoadLoad|LoadStore)); ++ } else { ++ dbar(0x700); ++ } + if (retold && oldval != R0) + move(oldval, resflag); + if (!exchange) { @@ -41105,7 +40733,7 @@ index 00000000000..882c43bf592 +} + +void MacroAssembler::cmpxchg32(Address addr, Register oldval, Register newval, Register tmp, -+ bool sign, bool retold, bool barrier, Label& succ, Label* fail) { ++ bool sign, bool retold, bool acquire, Label& succ, Label* fail) { + assert(oldval != tmp, "oldval != tmp"); + assert(newval != tmp, "newval != tmp"); + Label again, neq; @@ -41121,8 +40749,11 @@ index 00000000000..882c43bf592 + b(succ); + + bind(neq); -+ if (barrier) -+ membar(LoadLoad); ++ if (acquire) { ++ membar(Assembler::Membar_mask_bits(LoadLoad|LoadStore)); ++ } else { ++ dbar(0x700); ++ } + if (retold && oldval != R0) + move(oldval, tmp); + if (fail) @@ -42569,10 +42200,14 @@ index 00000000000..882c43bf592 + address last = code()->last_insn(); + if (last != NULL && ((NativeInstruction*)last)->is_sync() && prev == last) { + code()->set_last_insn(NULL); ++ NativeMembar *membar = (NativeMembar*)prev; ++ // merged membar ++ // e.g. LoadLoad and LoadLoad|LoadStore to LoadLoad|LoadStore ++ membar->set_hint(membar->get_hint() & (~hint & 0xF)); + block_comment("merged membar"); + } else { + code()->set_last_insn(pc()); -+ dbar(hint); ++ Assembler::membar(hint); + } +} + @@ -43011,12 +42646,10 @@ index 00000000000..882c43bf592 + } +} +#endif -diff --git a/src/hotspot/cpu/loongarch/macroAssembler_loongarch.hpp b/src/hotspot/cpu/loongarch/macroAssembler_loongarch.hpp -new file mode 100644 -index 00000000000..07c33b80151 ---- /dev/null -+++ b/src/hotspot/cpu/loongarch/macroAssembler_loongarch.hpp -@@ -0,0 +1,757 @@ +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/macroAssembler_loongarch.hpp b/src/hotspot/cpu/loongarch/macroAssembler_loongarch.hpp +--- a/src/hotspot/cpu/loongarch/macroAssembler_loongarch.hpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/loongarch/macroAssembler_loongarch.hpp 2024-01-31 14:01:11.600762198 +0800 +@@ -0,0 +1,754 @@ +/* + * Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 2015, 2022, Loongson Technology. All rights reserved. @@ -43406,9 +43039,6 @@ index 00000000000..07c33b80151 + // prints msg, dumps registers and stops execution + void stop(const char* msg); + -+ // prints msg and continues -+ void warn(const char* msg); -+ + static void debug(char* msg/*, RegistersForDebugging* regs*/); + static void debug64(char* msg, int64_t pc, int64_t regs[]); + @@ -43572,13 +43202,13 @@ index 00000000000..07c33b80151 + void bswap_w(Register dst, Register src); + + void cmpxchg(Address addr, Register oldval, Register newval, Register resflag, -+ bool retold, bool barrier, bool weak = false, bool exchange = false); ++ bool retold, bool acquire, bool weak = false, bool exchange = false); + void cmpxchg(Address addr, Register oldval, Register newval, Register tmp, -+ bool retold, bool barrier, Label& succ, Label* fail = nullptr); ++ bool retold, bool acquire, Label& succ, Label* fail = nullptr); + void cmpxchg32(Address addr, Register oldval, Register newval, Register resflag, -+ bool sign, bool retold, bool barrier, bool weak = false, bool exchange = false); ++ bool sign, bool retold, bool acquire, bool weak = false, bool exchange = false); + void cmpxchg32(Address addr, Register oldval, Register newval, Register tmp, -+ bool sign, bool retold, bool barrier, Label& succ, Label* fail = nullptr); ++ bool sign, bool retold, bool acquire, Label& succ, Label* fail = nullptr); + + void extend_sign(Register rh, Register rl) { /*stop("extend_sign");*/ guarantee(0, "LA not implemented yet");} + void neg(Register reg) { /*dsubu(reg, R0, reg);*/ guarantee(0, "LA not implemented yet");} @@ -43774,11 +43404,9 @@ index 00000000000..07c33b80151 +}; + +#endif // CPU_LOONGARCH_MACROASSEMBLER_LOONGARCH_HPP -diff --git a/src/hotspot/cpu/loongarch/macroAssembler_loongarch.inline.hpp b/src/hotspot/cpu/loongarch/macroAssembler_loongarch.inline.hpp -new file mode 100644 -index 00000000000..49302590c37 ---- /dev/null -+++ b/src/hotspot/cpu/loongarch/macroAssembler_loongarch.inline.hpp +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/macroAssembler_loongarch.inline.hpp b/src/hotspot/cpu/loongarch/macroAssembler_loongarch.inline.hpp +--- a/src/hotspot/cpu/loongarch/macroAssembler_loongarch.inline.hpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/loongarch/macroAssembler_loongarch.inline.hpp 2024-01-31 14:01:11.604095562 +0800 @@ -0,0 +1,34 @@ +/* + * Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved. @@ -43814,11 +43442,9 @@ index 00000000000..49302590c37 +#include "code/codeCache.hpp" + +#endif // CPU_LOONGARCH_MACROASSEMBLER_LOONGARCH_INLINE_HPP -diff --git a/src/hotspot/cpu/loongarch/macroAssembler_loongarch_trig.cpp b/src/hotspot/cpu/loongarch/macroAssembler_loongarch_trig.cpp -new file mode 100644 -index 00000000000..63b5b0da7e7 ---- /dev/null -+++ b/src/hotspot/cpu/loongarch/macroAssembler_loongarch_trig.cpp +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/macroAssembler_loongarch_trig.cpp b/src/hotspot/cpu/loongarch/macroAssembler_loongarch_trig.cpp +--- a/src/hotspot/cpu/loongarch/macroAssembler_loongarch_trig.cpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/loongarch/macroAssembler_loongarch_trig.cpp 2024-01-31 14:01:11.604095562 +0800 @@ -0,0 +1,1633 @@ +/* Copyright (c) 2018, 2020, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 2018, Cavium. All rights reserved. (By BELLSOFT) @@ -45453,11 +45079,9 @@ index 00000000000..63b5b0da7e7 + bind(DONE); + jr(RA); +} -diff --git a/src/hotspot/cpu/loongarch/matcher_loongarch.hpp b/src/hotspot/cpu/loongarch/matcher_loongarch.hpp -new file mode 100644 -index 00000000000..21a691b1faa ---- /dev/null -+++ b/src/hotspot/cpu/loongarch/matcher_loongarch.hpp +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/matcher_loongarch.hpp b/src/hotspot/cpu/loongarch/matcher_loongarch.hpp +--- a/src/hotspot/cpu/loongarch/matcher_loongarch.hpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/loongarch/matcher_loongarch.hpp 2024-01-31 14:01:11.604095562 +0800 @@ -0,0 +1,145 @@ +/* + * Copyright (c) 2021, Oracle and/or its affiliates. All rights reserved. @@ -45604,11 +45228,9 @@ index 00000000000..21a691b1faa + static const bool supports_encode_ascii_array = true; + +#endif // CPU_LOONGARCH_MATCHER_LOONGARCH_HPP -diff --git a/src/hotspot/cpu/loongarch/methodHandles_loongarch.cpp b/src/hotspot/cpu/loongarch/methodHandles_loongarch.cpp -new file mode 100644 -index 00000000000..31b3040c3a5 ---- /dev/null -+++ b/src/hotspot/cpu/loongarch/methodHandles_loongarch.cpp +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/methodHandles_loongarch.cpp b/src/hotspot/cpu/loongarch/methodHandles_loongarch.cpp +--- a/src/hotspot/cpu/loongarch/methodHandles_loongarch.cpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/loongarch/methodHandles_loongarch.cpp 2024-01-31 14:01:11.604095562 +0800 @@ -0,0 +1,585 @@ +/* + * Copyright (c) 1997, 2014, Oracle and/or its affiliates. All rights reserved. @@ -46195,11 +45817,9 @@ index 00000000000..31b3040c3a5 +void MethodHandles::trace_method_handle(MacroAssembler* _masm, const char* adaptername) { +} +#endif //PRODUCT -diff --git a/src/hotspot/cpu/loongarch/methodHandles_loongarch.hpp b/src/hotspot/cpu/loongarch/methodHandles_loongarch.hpp -new file mode 100644 -index 00000000000..a97520ea768 ---- /dev/null -+++ b/src/hotspot/cpu/loongarch/methodHandles_loongarch.hpp +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/methodHandles_loongarch.hpp b/src/hotspot/cpu/loongarch/methodHandles_loongarch.hpp +--- a/src/hotspot/cpu/loongarch/methodHandles_loongarch.hpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/loongarch/methodHandles_loongarch.hpp 2024-01-31 14:01:11.604095562 +0800 @@ -0,0 +1,62 @@ +/* + * Copyright (c) 2010, 2012, Oracle and/or its affiliates. All rights reserved. @@ -46263,12 +45883,10 @@ index 00000000000..a97520ea768 + // Should be in sharedRuntime, not here. + return R3; + } -diff --git a/src/hotspot/cpu/loongarch/nativeInst_loongarch.cpp b/src/hotspot/cpu/loongarch/nativeInst_loongarch.cpp -new file mode 100644 -index 00000000000..407f539e8d7 ---- /dev/null -+++ b/src/hotspot/cpu/loongarch/nativeInst_loongarch.cpp -@@ -0,0 +1,525 @@ +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/nativeInst_loongarch.cpp b/src/hotspot/cpu/loongarch/nativeInst_loongarch.cpp +--- a/src/hotspot/cpu/loongarch/nativeInst_loongarch.cpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/loongarch/nativeInst_loongarch.cpp 2024-01-31 14:01:11.604095562 +0800 +@@ -0,0 +1,529 @@ +/* + * Copyright (c) 1997, 2014, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 2015, 2021, Loongson Technology. All rights reserved. @@ -46693,6 +46311,10 @@ index 00000000000..407f539e8d7 + return uint_at(0) == NativeIllegalInstruction::instruction_code; +} + ++bool NativeInstruction::is_stop() { ++ return uint_at(0) == 0x04000000; // csrrd R0 0 ++} ++ +void NativeIllegalInstruction::insert(address code_pos) { + *(juint*)code_pos = instruction_code; + ICache::invalidate_range(code_pos, instruction_size); @@ -46794,12 +46416,10 @@ index 00000000000..407f539e8d7 + return Assembler::high(insn_word(), 10) == Assembler::ld_w_op && + Assembler::low(insn_word(), 5) == AT->encoding(); +} -diff --git a/src/hotspot/cpu/loongarch/nativeInst_loongarch.hpp b/src/hotspot/cpu/loongarch/nativeInst_loongarch.hpp -new file mode 100644 -index 00000000000..2f126991338 ---- /dev/null -+++ b/src/hotspot/cpu/loongarch/nativeInst_loongarch.hpp -@@ -0,0 +1,523 @@ +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/nativeInst_loongarch.hpp b/src/hotspot/cpu/loongarch/nativeInst_loongarch.hpp +--- a/src/hotspot/cpu/loongarch/nativeInst_loongarch.hpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/loongarch/nativeInst_loongarch.hpp 2024-01-31 14:01:11.604095562 +0800 +@@ -0,0 +1,531 @@ +/* + * Copyright (c) 1997, 2011, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 2015, 2021, Loongson Technology. All rights reserved. @@ -46882,6 +46502,7 @@ index 00000000000..2f126991338 + inline bool is_NativeCallTrampolineStub_at(); + //We use an illegal instruction for marking a method as not_entrant or zombie. + bool is_sigill_zombie_not_entrant(); ++ bool is_stop(); + + protected: + address addr_at(int offset) const { return address(this) + offset; } @@ -47322,79 +46943,17 @@ index 00000000000..2f126991338 + assert(ni->is_NativeCallTrampolineStub_at(), "no call trampoline found"); + return (NativeCallTrampolineStub*)addr; +} -+#endif // CPU_LOONGARCH_NATIVEINST_LOONGARCH_HPP -diff --git a/src/hotspot/cpu/loongarch/registerMap_loongarch.hpp b/src/hotspot/cpu/loongarch/registerMap_loongarch.hpp -new file mode 100644 -index 00000000000..07aa5b22817 ---- /dev/null -+++ b/src/hotspot/cpu/loongarch/registerMap_loongarch.hpp -@@ -0,0 +1,61 @@ -+/* -+ * Copyright (c) 1998, 2010, Oracle and/or its affiliates. All rights reserved. -+ * Copyright (c) 2015, 2022, Loongson Technology. All rights reserved. -+ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. -+ * -+ * This code is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 only, as -+ * published by the Free Software Foundation. -+ * -+ * This code is distributed in the hope that it will be useful, but WITHOUT -+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -+ * version 2 for more details (a copy is included in the LICENSE file that -+ * accompanied this code). -+ * -+ * You should have received a copy of the GNU General Public License version -+ * 2 along with this work; if not, write to the Free Software Foundation, -+ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. -+ * -+ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA -+ * or visit www.oracle.com if you need additional information or have any -+ * questions. -+ * -+ */ -+ -+#ifndef CPU_LOONGARCH_REGISTERMAP_LOONGARCH_HPP -+#define CPU_LOONGARCH_REGISTERMAP_LOONGARCH_HPP -+ -+// machine-dependent implemention for register maps -+ friend class frame; + -+ private: -+#ifndef CORE -+ // This is the hook for finding a register in an "well-known" location, -+ // such as a register block of a predetermined format. -+ // Since there is none, we just return NULL. -+ // See registerMap_sparc.hpp for an example of grabbing registers -+ // from register save areas of a standard layout. -+ address pd_location(VMReg reg) const {return NULL;} -+ address pd_location(VMReg base_reg, int slot_idx) const { -+ if (base_reg->is_FloatRegister()) { -+ assert(base_reg->is_concrete(), "must pass base reg"); -+ intptr_t offset_in_bytes = slot_idx * VMRegImpl::stack_slot_size; -+ address base_location = location(base_reg); -+ if (base_location != NULL) { -+ return base_location + offset_in_bytes; -+ } else { -+ return NULL; -+ } -+ } else { -+ return location(base_reg->next(slot_idx)); -+ } -+ } -+#endif -+ -+ // no PD state to clear or copy: -+ void pd_clear() {} -+ void pd_initialize() {} -+ void pd_initialize_from(const RegisterMap* map) {} ++class NativeMembar : public NativeInstruction { ++public: ++ unsigned int get_hint() { return Assembler::low(insn_word(), 4); } ++ void set_hint(int hint) { Assembler::patch(addr_at(0), 4, hint); } ++}; + -+#endif // CPU_LOONGARCH_REGISTERMAP_LOONGARCH_HPP -diff --git a/src/hotspot/cpu/loongarch/register_definitions_loongarch.cpp b/src/hotspot/cpu/loongarch/register_definitions_loongarch.cpp -new file mode 100644 -index 00000000000..58f40b747c2 ---- /dev/null -+++ b/src/hotspot/cpu/loongarch/register_definitions_loongarch.cpp ++#endif // CPU_LOONGARCH_NATIVEINST_LOONGARCH_HPP +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/register_definitions_loongarch.cpp b/src/hotspot/cpu/loongarch/register_definitions_loongarch.cpp +--- a/src/hotspot/cpu/loongarch/register_definitions_loongarch.cpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/loongarch/register_definitions_loongarch.cpp 2024-01-31 14:01:11.604095562 +0800 @@ -0,0 +1,103 @@ +/* + * Copyright (c) 2002, 2013, Oracle and/or its affiliates. All rights reserved. @@ -47499,11 +47058,9 @@ index 00000000000..58f40b747c2 +REGISTER_DEFINITION(FloatRegister, f29); +REGISTER_DEFINITION(FloatRegister, f30); +REGISTER_DEFINITION(FloatRegister, f31); -diff --git a/src/hotspot/cpu/loongarch/register_loongarch.cpp b/src/hotspot/cpu/loongarch/register_loongarch.cpp -new file mode 100644 -index 00000000000..54d90167a52 ---- /dev/null -+++ b/src/hotspot/cpu/loongarch/register_loongarch.cpp +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/register_loongarch.cpp b/src/hotspot/cpu/loongarch/register_loongarch.cpp +--- a/src/hotspot/cpu/loongarch/register_loongarch.cpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/loongarch/register_loongarch.cpp 2024-01-31 14:01:11.604095562 +0800 @@ -0,0 +1,59 @@ +/* + * Copyright (c) 2000, 2012, Oracle and/or its affiliates. All rights reserved. @@ -47564,11 +47121,9 @@ index 00000000000..54d90167a52 + }; + return is_valid() ? names[encoding()] : "fccnoreg"; +} -diff --git a/src/hotspot/cpu/loongarch/register_loongarch.hpp b/src/hotspot/cpu/loongarch/register_loongarch.hpp -new file mode 100644 -index 00000000000..85669f435c7 ---- /dev/null -+++ b/src/hotspot/cpu/loongarch/register_loongarch.hpp +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/register_loongarch.hpp b/src/hotspot/cpu/loongarch/register_loongarch.hpp +--- a/src/hotspot/cpu/loongarch/register_loongarch.hpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/loongarch/register_loongarch.hpp 2024-01-31 14:01:11.604095562 +0800 @@ -0,0 +1,499 @@ +/* + * Copyright (c) 2000, 2012, Oracle and/or its affiliates. All rights reserved. @@ -48069,11 +47624,74 @@ index 00000000000..85669f435c7 +typedef AbstractRegSet FloatRegSet; + +#endif //CPU_LOONGARCH_REGISTER_LOONGARCH_HPP -diff --git a/src/hotspot/cpu/loongarch/relocInfo_loongarch.cpp b/src/hotspot/cpu/loongarch/relocInfo_loongarch.cpp -new file mode 100644 -index 00000000000..079d581c91f ---- /dev/null -+++ b/src/hotspot/cpu/loongarch/relocInfo_loongarch.cpp +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/registerMap_loongarch.hpp b/src/hotspot/cpu/loongarch/registerMap_loongarch.hpp +--- a/src/hotspot/cpu/loongarch/registerMap_loongarch.hpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/loongarch/registerMap_loongarch.hpp 2024-01-31 14:01:11.604095562 +0800 +@@ -0,0 +1,61 @@ ++/* ++ * Copyright (c) 1998, 2010, Oracle and/or its affiliates. All rights reserved. ++ * Copyright (c) 2015, 2022, Loongson Technology. All rights reserved. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ * ++ */ ++ ++#ifndef CPU_LOONGARCH_REGISTERMAP_LOONGARCH_HPP ++#define CPU_LOONGARCH_REGISTERMAP_LOONGARCH_HPP ++ ++// machine-dependent implemention for register maps ++ friend class frame; ++ ++ private: ++#ifndef CORE ++ // This is the hook for finding a register in an "well-known" location, ++ // such as a register block of a predetermined format. ++ // Since there is none, we just return NULL. ++ // See registerMap_sparc.hpp for an example of grabbing registers ++ // from register save areas of a standard layout. ++ address pd_location(VMReg reg) const {return NULL;} ++ address pd_location(VMReg base_reg, int slot_idx) const { ++ if (base_reg->is_FloatRegister()) { ++ assert(base_reg->is_concrete(), "must pass base reg"); ++ intptr_t offset_in_bytes = slot_idx * VMRegImpl::stack_slot_size; ++ address base_location = location(base_reg); ++ if (base_location != NULL) { ++ return base_location + offset_in_bytes; ++ } else { ++ return NULL; ++ } ++ } else { ++ return location(base_reg->next(slot_idx)); ++ } ++ } ++#endif ++ ++ // no PD state to clear or copy: ++ void pd_clear() {} ++ void pd_initialize() {} ++ void pd_initialize_from(const RegisterMap* map) {} ++ ++#endif // CPU_LOONGARCH_REGISTERMAP_LOONGARCH_HPP +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/relocInfo_loongarch.cpp b/src/hotspot/cpu/loongarch/relocInfo_loongarch.cpp +--- a/src/hotspot/cpu/loongarch/relocInfo_loongarch.cpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/loongarch/relocInfo_loongarch.cpp 2024-01-31 14:01:11.604095562 +0800 @@ -0,0 +1,132 @@ +/* + * Copyright (c) 1998, 2013, Oracle and/or its affiliates. All rights reserved. @@ -48207,11 +47825,9 @@ index 00000000000..079d581c91f + +void metadata_Relocation::pd_fix_value(address x) { +} -diff --git a/src/hotspot/cpu/loongarch/relocInfo_loongarch.hpp b/src/hotspot/cpu/loongarch/relocInfo_loongarch.hpp -new file mode 100644 -index 00000000000..c85ca4963f3 ---- /dev/null -+++ b/src/hotspot/cpu/loongarch/relocInfo_loongarch.hpp +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/relocInfo_loongarch.hpp b/src/hotspot/cpu/loongarch/relocInfo_loongarch.hpp +--- a/src/hotspot/cpu/loongarch/relocInfo_loongarch.hpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/loongarch/relocInfo_loongarch.hpp 2024-01-31 14:01:11.604095562 +0800 @@ -0,0 +1,44 @@ +/* + * Copyright (c) 1997, 2010, Oracle and/or its affiliates. All rights reserved. @@ -48257,11 +47873,9 @@ index 00000000000..c85ca4963f3 + static bool mustIterateImmediateOopsInCode() { return false; } + +#endif // CPU_LOONGARCH_RELOCINFO_LOONGARCH_HPP -diff --git a/src/hotspot/cpu/loongarch/runtime_loongarch_64.cpp b/src/hotspot/cpu/loongarch/runtime_loongarch_64.cpp -new file mode 100644 -index 00000000000..fae11f47e62 ---- /dev/null -+++ b/src/hotspot/cpu/loongarch/runtime_loongarch_64.cpp +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/runtime_loongarch_64.cpp b/src/hotspot/cpu/loongarch/runtime_loongarch_64.cpp +--- a/src/hotspot/cpu/loongarch/runtime_loongarch_64.cpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/loongarch/runtime_loongarch_64.cpp 2024-01-31 14:01:11.604095562 +0800 @@ -0,0 +1,199 @@ +/* + * Copyright (c) 2003, 2010, Oracle and/or its affiliates. All rights reserved. @@ -48462,15 +48076,13 @@ index 00000000000..fae11f47e62 + masm->flush(); + _exception_blob = ExceptionBlob::create(&buffer, oop_maps, framesize); +} -diff --git a/src/hotspot/cpu/loongarch/sharedRuntime_loongarch_64.cpp b/src/hotspot/cpu/loongarch/sharedRuntime_loongarch_64.cpp -new file mode 100644 -index 00000000000..0fe2f8f0d36 ---- /dev/null -+++ b/src/hotspot/cpu/loongarch/sharedRuntime_loongarch_64.cpp -@@ -0,0 +1,3114 @@ +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/sharedRuntime_loongarch_64.cpp b/src/hotspot/cpu/loongarch/sharedRuntime_loongarch_64.cpp +--- a/src/hotspot/cpu/loongarch/sharedRuntime_loongarch_64.cpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/loongarch/sharedRuntime_loongarch_64.cpp 2024-01-31 14:01:11.604095562 +0800 +@@ -0,0 +1,3113 @@ +/* + * Copyright (c) 2003, 2013, Oracle and/or its affiliates. All rights reserved. -+ * Copyright (c) 2015, 2021, Loongson Technology. All rights reserved. ++ * Copyright (c) 2015, 2023, Loongson Technology. All rights reserved. + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. + * + * This code is free software; you can redistribute it and/or modify it @@ -48797,9 +48409,9 @@ index 00000000000..0fe2f8f0d36 +} + +// Is vector's size (in bytes) bigger than a size saved by default? -+// 16 bytes XMM registers are saved by default using fxsave/fxrstor instructions. ++// 8 bytes registers are saved by default using fld/fst instructions. +bool SharedRuntime::is_wide_vector(int size) { -+ return size > 16; ++ return size > 8; +} + +// The java_calling_convention describes stack locations as ideal slots on @@ -49363,7 +48975,6 @@ index 00000000000..0fe2f8f0d36 + + gen_c2i_adapter(masm, total_args_passed, comp_args_on_stack, sig_bt, regs, skip_fixup); + -+ __ flush(); + return AdapterHandlerLibrary::new_entry(fingerprint, i2c_entry, c2i_entry, c2i_unverified_entry, c2i_no_clinit_check_entry); +} + @@ -50399,7 +50010,7 @@ index 00000000000..0fe2f8f0d36 + __ orr(swap_reg, swap_reg, AT); + + __ st_d(swap_reg, lock_reg, mark_word_offset); -+ __ cmpxchg(Address(obj_reg, 0), swap_reg, lock_reg, AT, true, false, lock_done); ++ __ cmpxchg(Address(obj_reg, 0), swap_reg, lock_reg, AT, true, true /* acquire */, lock_done); + // Test if the oopMark is an obvious stack pointer, i.e., + // 1) (mark & 3) == 0, and + // 2) sp <= mark < mark + os::pagesize() @@ -50434,8 +50045,8 @@ index 00000000000..0fe2f8f0d36 + + // Now set thread in native + __ addi_d(AT, R0, _thread_in_native); -+ if(os::is_MP()) { -+ __ dbar(0); // store release ++ if (os::is_MP()) { ++ __ membar(Assembler::Membar_mask_bits(__ LoadStore|__ StoreStore)); + } + __ st_w(AT, thread, in_bytes(JavaThread::thread_state_offset())); + } @@ -50490,8 +50101,8 @@ index 00000000000..0fe2f8f0d36 + // Thread A is resumed to finish this native method, but doesn't block here since it + // didn't see any synchronization is progress, and escapes. + __ addi_d(AT, R0, _thread_in_native_trans); -+ if(os::is_MP()) { -+ __ dbar(0); // store release ++ if (os::is_MP()) { ++ __ membar(Assembler::Membar_mask_bits(__ LoadStore|__ StoreStore)); + } + __ st_w(AT, thread, in_bytes(JavaThread::thread_state_offset())); + @@ -50538,8 +50149,8 @@ index 00000000000..0fe2f8f0d36 + + // change thread state + __ addi_d(AT, R0, _thread_in_Java); -+ if(os::is_MP()) { -+ __ dbar(0); // store release ++ if (os::is_MP()) { ++ __ membar(Assembler::Membar_mask_bits(__ LoadStore|__ StoreStore)); + } + __ st_w(AT, thread, in_bytes(JavaThread::thread_state_offset())); + __ bind(after_transition); @@ -50583,7 +50194,7 @@ index 00000000000..0fe2f8f0d36 + // get address of the stack lock + __ addi_d (c_rarg0, FP, lock_slot_fp_offset); + // Atomic swap old header if oop still contains the stack lock -+ __ cmpxchg(Address(obj_reg, 0), c_rarg0, T8, AT, false, false, unlock_done, &slow_path_unlock); ++ __ cmpxchg(Address(obj_reg, 0), c_rarg0, T8, AT, false, true /* acquire */, unlock_done, &slow_path_unlock); + + // slow path re-enters here + __ bind(unlock_done); @@ -51582,12 +51193,10 @@ index 00000000000..0fe2f8f0d36 + return nullptr; +} +#endif -diff --git a/src/hotspot/cpu/loongarch/stubGenerator_loongarch_64.cpp b/src/hotspot/cpu/loongarch/stubGenerator_loongarch_64.cpp -new file mode 100644 -index 00000000000..fbdc96f10f5 ---- /dev/null -+++ b/src/hotspot/cpu/loongarch/stubGenerator_loongarch_64.cpp -@@ -0,0 +1,5296 @@ +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/stubGenerator_loongarch_64.cpp b/src/hotspot/cpu/loongarch/stubGenerator_loongarch_64.cpp +--- a/src/hotspot/cpu/loongarch/stubGenerator_loongarch_64.cpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/loongarch/stubGenerator_loongarch_64.cpp 2024-01-31 14:01:11.604095562 +0800 +@@ -0,0 +1,5176 @@ +/* + * Copyright (c) 2003, 2013, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 2015, 2022, Loongson Technology. All rights reserved. @@ -52318,8 +51927,8 @@ index 00000000000..fbdc96f10f5 + + // disjoint large copy + void generate_disjoint_large_copy(Label &entry, const char *name) { -+ StubCodeMark mark(this, "StubRoutines", name); + __ align(CodeEntryAlignment); ++ StubCodeMark mark(this, "StubRoutines", name); + + { + UnsafeCopyMemoryMark ucmm(this, true, true); @@ -52331,7 +51940,7 @@ index 00000000000..fbdc96f10f5 + __ ld_d(A6, A0, 0); + __ ld_d(A7, A2, -8); + -+ __ andi(T1, A0, 7); ++ __ andi(T1, A1, 7); + __ sub_d(T0, R0, T1); + __ addi_d(T0, T0, 8); + @@ -52403,8 +52012,8 @@ index 00000000000..fbdc96f10f5 + + // disjoint large copy lsx + void generate_disjoint_large_copy_lsx(Label &entry, const char *name) { -+ StubCodeMark mark(this, "StubRoutines", name); + __ align(CodeEntryAlignment); ++ StubCodeMark mark(this, "StubRoutines", name); + + { + UnsafeCopyMemoryMark ucmm(this, true, true); @@ -52416,7 +52025,7 @@ index 00000000000..fbdc96f10f5 + __ vld(F0, A0, 0); + __ vld(F1, A2, -16); + -+ __ andi(T1, A0, 15); ++ __ andi(T1, A1, 15); + __ sub_d(T0, R0, T1); + __ addi_d(T0, T0, 16); + @@ -52488,8 +52097,8 @@ index 00000000000..fbdc96f10f5 + + // disjoint large copy lasx + void generate_disjoint_large_copy_lasx(Label &entry, const char *name) { -+ StubCodeMark mark(this, "StubRoutines", name); + __ align(CodeEntryAlignment); ++ StubCodeMark mark(this, "StubRoutines", name); + + { + UnsafeCopyMemoryMark ucmm(this, true, true); @@ -52501,7 +52110,7 @@ index 00000000000..fbdc96f10f5 + __ xvld(F0, A0, 0); + __ xvld(F1, A2, -32); + -+ __ andi(T1, A0, 31); ++ __ andi(T1, A1, 31); + __ sub_d(T0, R0, T1); + __ addi_d(T0, T0, 32); + @@ -52573,8 +52182,8 @@ index 00000000000..fbdc96f10f5 + + // conjoint large copy + void generate_conjoint_large_copy(Label &entry, const char *name) { -+ StubCodeMark mark(this, "StubRoutines", name); + __ align(CodeEntryAlignment); ++ StubCodeMark mark(this, "StubRoutines", name); + + { + UnsafeCopyMemoryMark ucmm(this, true, true); @@ -52586,7 +52195,7 @@ index 00000000000..fbdc96f10f5 + __ ld_d(A6, A0, 0); + __ ld_d(A7, A2, -8); + -+ __ andi(T1, A2, 7); ++ __ andi(T1, A3, 7); + __ sub_d(A2, A2, T1); + __ sub_d(A5, A3, T1); + @@ -52655,8 +52264,8 @@ index 00000000000..fbdc96f10f5 + + // conjoint large copy lsx + void generate_conjoint_large_copy_lsx(Label &entry, const char *name) { -+ StubCodeMark mark(this, "StubRoutines", name); + __ align(CodeEntryAlignment); ++ StubCodeMark mark(this, "StubRoutines", name); + + { + UnsafeCopyMemoryMark ucmm(this, true, true); @@ -52668,7 +52277,7 @@ index 00000000000..fbdc96f10f5 + __ vld(F0, A0, 0); + __ vld(F1, A2, -16); + -+ __ andi(T1, A2, 15); ++ __ andi(T1, A3, 15); + __ sub_d(A2, A2, T1); + __ sub_d(A5, A3, T1); + @@ -52737,8 +52346,8 @@ index 00000000000..fbdc96f10f5 + + // conjoint large copy lasx + void generate_conjoint_large_copy_lasx(Label &entry, const char *name) { -+ StubCodeMark mark(this, "StubRoutines", name); + __ align(CodeEntryAlignment); ++ StubCodeMark mark(this, "StubRoutines", name); + + { + UnsafeCopyMemoryMark ucmm(this, true, true); @@ -52750,7 +52359,7 @@ index 00000000000..fbdc96f10f5 + __ xvld(F0, A0, 0); + __ xvld(F1, A2, -32); + -+ __ andi(T1, A2, 31); ++ __ andi(T1, A3, 31); + __ sub_d(A2, A2, T1); + __ sub_d(A5, A3, T1); + @@ -52819,8 +52428,8 @@ index 00000000000..fbdc96f10f5 + + // Byte small copy: less than { int:9, lsx:17, lasx:33 } elements. + void generate_byte_small_copy(Label &entry, const char *name) { -+ StubCodeMark mark(this, "StubRoutines", name); + __ align(CodeEntryAlignment); ++ StubCodeMark mark(this, "StubRoutines", name); + + Label L; + __ bind(entry); @@ -53184,9 +52793,9 @@ index 00000000000..fbdc96f10f5 + // used by generate_conjoint_byte_copy(). + // + address generate_disjoint_byte_copy(bool aligned, Label &small, Label &large, -+ Label &large_aligned, const char * name) { -+ StubCodeMark mark(this, "StubRoutines", name); ++ const char * name) { + __ align(CodeEntryAlignment); ++ StubCodeMark mark(this, "StubRoutines", name); + address start = __ pc(); + + if (UseLASX) @@ -53197,12 +52806,6 @@ index 00000000000..fbdc96f10f5 + __ sltui(T0, A2, 9); + __ bnez(T0, small); + -+ if (large_aligned.is_bound()) { -+ __ orr(T0, A0, A1); -+ __ andi(T0, T0, 7); -+ __ beqz(T0, large_aligned); -+ } -+ + __ b(large); + + return start; @@ -53224,9 +52827,9 @@ index 00000000000..fbdc96f10f5 + // and stored atomically. + // + address generate_conjoint_byte_copy(bool aligned, Label &small, Label &large, -+ Label &large_aligned, const char *name) { -+ StubCodeMark mark(this, "StubRoutines", name); ++ const char *name) { + __ align(CodeEntryAlignment); ++ StubCodeMark mark(this, "StubRoutines", name); + address start = __ pc(); + + array_overlap_test(StubRoutines::jbyte_disjoint_arraycopy(), 0); @@ -53239,12 +52842,6 @@ index 00000000000..fbdc96f10f5 + __ sltui(T0, A2, 9); + __ bnez(T0, small); + -+ if (large_aligned.is_bound()) { -+ __ orr(T0, A0, A1); -+ __ andi(T0, T0, 7); -+ __ beqz(T0, large_aligned); -+ } -+ + __ b(large); + + return start; @@ -53252,8 +52849,8 @@ index 00000000000..fbdc96f10f5 + + // Short small copy: less than { int:9, lsx:9, lasx:17 } elements. + void generate_short_small_copy(Label &entry, const char *name) { -+ StubCodeMark mark(this, "StubRoutines", name); + __ align(CodeEntryAlignment); ++ StubCodeMark mark(this, "StubRoutines", name); + + Label L; + __ bind(entry); @@ -53463,9 +53060,9 @@ index 00000000000..fbdc96f10f5 + // used by generate_conjoint_short_copy(). + // + address generate_disjoint_short_copy(bool aligned, Label &small, Label &large, -+ Label &large_aligned, const char * name) { -+ StubCodeMark mark(this, "StubRoutines", name); ++ const char * name) { + __ align(CodeEntryAlignment); ++ StubCodeMark mark(this, "StubRoutines", name); + address start = __ pc(); + + if (UseLASX) @@ -53476,12 +53073,6 @@ index 00000000000..fbdc96f10f5 + + __ slli_d(A2, A2, 1); + -+ if (large_aligned.is_bound()) { -+ __ orr(T0, A0, A1); -+ __ andi(T0, T0, 7); -+ __ beqz(T0, large_aligned); -+ } -+ + __ b(large); + + return start; @@ -53503,9 +53094,9 @@ index 00000000000..fbdc96f10f5 + // and stored atomically. + // + address generate_conjoint_short_copy(bool aligned, Label &small, Label &large, -+ Label &large_aligned, const char *name) { -+ StubCodeMark mark(this, "StubRoutines", name); ++ const char *name) { + __ align(CodeEntryAlignment); ++ StubCodeMark mark(this, "StubRoutines", name); + address start = __ pc(); + + array_overlap_test(StubRoutines::jshort_disjoint_arraycopy(), 1); @@ -53518,12 +53109,6 @@ index 00000000000..fbdc96f10f5 + + __ slli_d(A2, A2, 1); + -+ if (large_aligned.is_bound()) { -+ __ orr(T0, A0, A1); -+ __ andi(T0, T0, 7); -+ __ beqz(T0, large_aligned); -+ } -+ + __ b(large); + + return start; @@ -53531,8 +53116,8 @@ index 00000000000..fbdc96f10f5 + + // Int small copy: less than { int:7, lsx:7, lasx:9 } elements. + void generate_int_small_copy(Label &entry, const char *name) { -+ StubCodeMark mark(this, "StubRoutines", name); + __ align(CodeEntryAlignment); ++ StubCodeMark mark(this, "StubRoutines", name); + + Label L; + __ bind(entry); @@ -53665,8 +53250,8 @@ index 00000000000..fbdc96f10f5 + + // Generate maybe oop copy + void gen_maybe_oop_copy(bool is_oop, bool disjoint, bool aligned, Label &small, -+ Label &large, Label &large_aligned, const char *name, -+ int small_limit, int log2_elem_size, bool dest_uninitialized = false) { ++ Label &large, const char *name, int small_limit, ++ int log2_elem_size, bool dest_uninitialized = false) { + Label post, _large; + DecoratorSet decorators = DECORATORS_NONE; + BarrierSetAssembler *bs = nullptr; @@ -53712,20 +53297,6 @@ index 00000000000..fbdc96f10f5 + __ bind(_large); + __ slli_d(A2, A2, log2_elem_size); + -+ if (large_aligned.is_bound()) { -+ __ orr(T0, A0, A1); -+ __ andi(T0, T0, (1 << (log2_elem_size + 1)) - 1); -+ if (is_oop) { -+ Label skip; -+ __ bnez(T0, skip); -+ __ bl(large_aligned); -+ __ b(post); -+ __ bind(skip); -+ } else { -+ __ beqz(T0, large_aligned); -+ } -+ } -+ + if (is_oop) { + __ bl(large); + } else { @@ -53766,14 +53337,14 @@ index 00000000000..fbdc96f10f5 + // used by generate_conjoint_int_oop_copy(). + // + address generate_disjoint_int_oop_copy(bool aligned, bool is_oop, Label &small, -+ Label &large, Label &large_aligned, const char *name, -+ int small_limit, bool dest_uninitialized = false) { -+ StubCodeMark mark(this, "StubRoutines", name); ++ Label &large, const char *name, int small_limit, ++ bool dest_uninitialized = false) { + __ align(CodeEntryAlignment); ++ StubCodeMark mark(this, "StubRoutines", name); + address start = __ pc(); + -+ gen_maybe_oop_copy(is_oop, true, aligned, small, large, large_aligned, -+ name, small_limit, 2, dest_uninitialized); ++ gen_maybe_oop_copy(is_oop, true, aligned, small, large, name, ++ small_limit, 2, dest_uninitialized); + + return start; + } @@ -53794,10 +53365,10 @@ index 00000000000..fbdc96f10f5 + // cache line boundaries will still be loaded and stored atomicly. + // + address generate_conjoint_int_oop_copy(bool aligned, bool is_oop, Label &small, -+ Label &large, Label &large_aligned, const char *name, -+ int small_limit, bool dest_uninitialized = false) { -+ StubCodeMark mark(this, "StubRoutines", name); ++ Label &large, const char *name, int small_limit, ++ bool dest_uninitialized = false) { + __ align(CodeEntryAlignment); ++ StubCodeMark mark(this, "StubRoutines", name); + address start = __ pc(); + + if (is_oop) { @@ -53806,16 +53377,16 @@ index 00000000000..fbdc96f10f5 + array_overlap_test(StubRoutines::jint_disjoint_arraycopy(), 2); + } + -+ gen_maybe_oop_copy(is_oop, false, aligned, small, large, large_aligned, -+ name, small_limit, 2, dest_uninitialized); ++ gen_maybe_oop_copy(is_oop, false, aligned, small, large, name, ++ small_limit, 2, dest_uninitialized); + + return start; + } + + // Long small copy: less than { int:4, lsx:4, lasx:5 } elements. + void generate_long_small_copy(Label &entry, const char *name) { -+ StubCodeMark mark(this, "StubRoutines", name); + __ align(CodeEntryAlignment); ++ StubCodeMark mark(this, "StubRoutines", name); + + Label L; + __ bind(entry); @@ -53918,14 +53489,14 @@ index 00000000000..fbdc96f10f5 + // used by generate_conjoint_int_oop_copy(). + // + address generate_disjoint_long_oop_copy(bool aligned, bool is_oop, Label &small, -+ Label &large, Label &large_aligned, const char *name, -+ int small_limit, bool dest_uninitialized = false) { -+ StubCodeMark mark(this, "StubRoutines", name); ++ Label &large, const char *name, int small_limit, ++ bool dest_uninitialized = false) { + __ align(CodeEntryAlignment); ++ StubCodeMark mark(this, "StubRoutines", name); + address start = __ pc(); + -+ gen_maybe_oop_copy(is_oop, true, aligned, small, large, large_aligned, -+ name, small_limit, 3, dest_uninitialized); ++ gen_maybe_oop_copy(is_oop, true, aligned, small, large, name, ++ small_limit, 3, dest_uninitialized); + + return start; + } @@ -53946,10 +53517,10 @@ index 00000000000..fbdc96f10f5 + // cache line boundaries will still be loaded and stored atomicly. + // + address generate_conjoint_long_oop_copy(bool aligned, bool is_oop, Label &small, -+ Label &large, Label &large_aligned, const char *name, -+ int small_limit, bool dest_uninitialized = false) { -+ StubCodeMark mark(this, "StubRoutines", name); ++ Label &large, const char *name, int small_limit, ++ bool dest_uninitialized = false) { + __ align(CodeEntryAlignment); ++ StubCodeMark mark(this, "StubRoutines", name); + address start = __ pc(); + + if (is_oop) { @@ -53958,8 +53529,8 @@ index 00000000000..fbdc96f10f5 + array_overlap_test(StubRoutines::jlong_disjoint_arraycopy(), 3); + } + -+ gen_maybe_oop_copy(is_oop, false, aligned, small, large, large_aligned, -+ name, small_limit, 3, dest_uninitialized); ++ gen_maybe_oop_copy(is_oop, false, aligned, small, large, name, ++ small_limit, 3, dest_uninitialized); + + return start; + } @@ -54479,20 +54050,24 @@ index 00000000000..fbdc96f10f5 + + void generate_arraycopy_stubs() { + Label disjoint_large_copy, conjoint_large_copy; -+ Label disjoint_large_copy_lsx, conjoint_large_copy_lsx; -+ Label disjoint_large_copy_lasx, conjoint_large_copy_lasx; + Label byte_small_copy, short_small_copy, int_small_copy, long_small_copy; -+ Label none; ++ int int_oop_small_limit, long_oop_small_limit; + -+ generate_disjoint_large_copy(disjoint_large_copy, "disjoint_large_copy"); -+ generate_conjoint_large_copy(conjoint_large_copy, "conjoint_large_copy"); -+ if (UseLSX) { -+ generate_disjoint_large_copy_lsx(disjoint_large_copy_lsx, "disjoint_large_copy_lsx"); -+ generate_conjoint_large_copy_lsx(conjoint_large_copy_lsx, "conjoint_large_copy_lsx"); -+ } + if (UseLASX) { -+ generate_disjoint_large_copy_lasx(disjoint_large_copy_lasx, "disjoint_large_copy_lasx"); -+ generate_conjoint_large_copy_lasx(conjoint_large_copy_lasx, "conjoint_large_copy_lasx"); ++ int_oop_small_limit = 9; ++ long_oop_small_limit = 5; ++ generate_disjoint_large_copy_lasx(disjoint_large_copy, "disjoint_large_copy_lasx"); ++ generate_conjoint_large_copy_lasx(conjoint_large_copy, "conjoint_large_copy_lasx"); ++ } else if (UseLSX) { ++ int_oop_small_limit = 7; ++ long_oop_small_limit = 4; ++ generate_disjoint_large_copy_lsx(disjoint_large_copy, "disjoint_large_copy_lsx"); ++ generate_conjoint_large_copy_lsx(conjoint_large_copy, "conjoint_large_copy_lsx"); ++ } else { ++ int_oop_small_limit = 7; ++ long_oop_small_limit = 4; ++ generate_disjoint_large_copy(disjoint_large_copy, "disjoint_large_copy_int"); ++ generate_conjoint_large_copy(conjoint_large_copy, "conjoint_large_copy_int"); + } + generate_byte_small_copy(byte_small_copy, "jbyte_small_copy"); + generate_short_small_copy(short_small_copy, "jshort_small_copy"); @@ -54500,78 +54075,39 @@ index 00000000000..fbdc96f10f5 + generate_long_small_copy(long_small_copy, "jlong_small_copy"); + + if (UseCompressedOops) { -+ if (UseLSX) { -+ StubRoutines::_oop_disjoint_arraycopy = generate_disjoint_int_oop_copy(false, true, int_small_copy, disjoint_large_copy_lsx, disjoint_large_copy, "oop_disjoint_arraycopy", 7); -+ StubRoutines::_oop_disjoint_arraycopy_uninit = generate_disjoint_int_oop_copy(false, true, int_small_copy, disjoint_large_copy_lsx, disjoint_large_copy, "oop_disjoint_arraycopy_uninit", 7, true); -+ } else { -+ StubRoutines::_oop_disjoint_arraycopy = generate_disjoint_int_oop_copy(false, true, int_small_copy, disjoint_large_copy, none, "oop_disjoint_arraycopy", 7); -+ StubRoutines::_oop_disjoint_arraycopy_uninit = generate_disjoint_int_oop_copy(false, true, int_small_copy, disjoint_large_copy, none, "oop_disjoint_arraycopy_uninit", 7, true); -+ } -+ if (UseLASX) { -+ StubRoutines::_oop_arraycopy = generate_conjoint_int_oop_copy(false, true, int_small_copy, conjoint_large_copy_lasx, conjoint_large_copy, "oop_arraycopy", 9); -+ StubRoutines::_oop_arraycopy_uninit = generate_conjoint_int_oop_copy(false, true, int_small_copy, conjoint_large_copy_lasx, conjoint_large_copy, "oop_arraycopy_uninit", 9, true); -+ } else if (UseLSX) { -+ StubRoutines::_oop_arraycopy = generate_conjoint_int_oop_copy(false, true, int_small_copy, conjoint_large_copy_lsx, conjoint_large_copy, "oop_arraycopy", 7); -+ StubRoutines::_oop_arraycopy_uninit = generate_conjoint_int_oop_copy(false, true, int_small_copy, conjoint_large_copy_lsx, conjoint_large_copy, "oop_arraycopy_uninit", 7, true); -+ } else { -+ StubRoutines::_oop_arraycopy = generate_conjoint_int_oop_copy(false, true, int_small_copy, conjoint_large_copy, none, "oop_arraycopy", 7); -+ StubRoutines::_oop_arraycopy_uninit = generate_conjoint_int_oop_copy(false, true, int_small_copy, conjoint_large_copy, none, "oop_arraycopy_uninit", 7, true); -+ } ++ StubRoutines::_oop_disjoint_arraycopy = generate_disjoint_int_oop_copy(false, true, int_small_copy, disjoint_large_copy, ++ "oop_disjoint_arraycopy", int_oop_small_limit); ++ StubRoutines::_oop_disjoint_arraycopy_uninit = generate_disjoint_int_oop_copy(false, true, int_small_copy, disjoint_large_copy, ++ "oop_disjoint_arraycopy_uninit", int_oop_small_limit, true); ++ StubRoutines::_oop_arraycopy = generate_conjoint_int_oop_copy(false, true, int_small_copy, conjoint_large_copy, ++ "oop_arraycopy", int_oop_small_limit); ++ StubRoutines::_oop_arraycopy_uninit = generate_conjoint_int_oop_copy(false, true, int_small_copy, conjoint_large_copy, ++ "oop_arraycopy_uninit", int_oop_small_limit, true); + } else { -+ if (UseLASX) { -+ StubRoutines::_oop_disjoint_arraycopy = generate_disjoint_long_oop_copy(false, true, long_small_copy, disjoint_large_copy, disjoint_large_copy_lasx, "oop_disjoint_arraycopy", 5); -+ StubRoutines::_oop_disjoint_arraycopy_uninit = generate_disjoint_long_oop_copy(false, true, long_small_copy, disjoint_large_copy, disjoint_large_copy_lasx, "oop_disjoint_arraycopy_uninit", 5, true); -+ StubRoutines::_oop_arraycopy = generate_conjoint_long_oop_copy(false, true, long_small_copy, conjoint_large_copy, conjoint_large_copy_lasx, "oop_arraycopy", 5); -+ StubRoutines::_oop_arraycopy_uninit = generate_conjoint_long_oop_copy(false, true, long_small_copy, conjoint_large_copy, conjoint_large_copy_lasx, "oop_arraycopy_uninit", 5, true); -+ } else if (UseLSX) { -+ StubRoutines::_oop_disjoint_arraycopy = generate_disjoint_long_oop_copy(false, true, long_small_copy, disjoint_large_copy, disjoint_large_copy_lsx, "oop_disjoint_arraycopy", 4); -+ StubRoutines::_oop_disjoint_arraycopy_uninit = generate_disjoint_long_oop_copy(false, true, long_small_copy, disjoint_large_copy, disjoint_large_copy_lsx, "oop_disjoint_arraycopy_uninit", 4, true); -+ StubRoutines::_oop_arraycopy = generate_conjoint_long_oop_copy(false, true, long_small_copy, conjoint_large_copy, conjoint_large_copy_lsx, "oop_arraycopy", 4); -+ StubRoutines::_oop_arraycopy_uninit = generate_conjoint_long_oop_copy(false, true, long_small_copy, conjoint_large_copy, conjoint_large_copy_lsx, "oop_arraycopy_uninit", 4, true); -+ } else { -+ StubRoutines::_oop_disjoint_arraycopy = generate_disjoint_long_oop_copy(false, true, long_small_copy, disjoint_large_copy, none, "oop_disjoint_arraycopy", 4); -+ StubRoutines::_oop_disjoint_arraycopy_uninit = generate_disjoint_long_oop_copy(false, true, long_small_copy, disjoint_large_copy, none, "oop_disjoint_arraycopy_uninit", 4, true); -+ StubRoutines::_oop_arraycopy = generate_conjoint_long_oop_copy(false, true, long_small_copy, conjoint_large_copy, none, "oop_arraycopy", 4); -+ StubRoutines::_oop_arraycopy_uninit = generate_conjoint_long_oop_copy(false, true, long_small_copy, conjoint_large_copy, conjoint_large_copy_lsx, "oop_arraycopy_uninit", 4, true); -+ } -+ } -+ -+ if (UseLASX) { -+ StubRoutines::_jbyte_disjoint_arraycopy = generate_disjoint_byte_copy(false, byte_small_copy, disjoint_large_copy_lasx, disjoint_large_copy_lsx, "jbyte_disjoint_arraycopy"); -+ StubRoutines::_jshort_disjoint_arraycopy = generate_disjoint_short_copy(false, short_small_copy, disjoint_large_copy_lasx, disjoint_large_copy, "jshort_disjoint_arraycopy"); -+ StubRoutines::_jint_disjoint_arraycopy = generate_disjoint_int_oop_copy(false, false, int_small_copy, disjoint_large_copy_lasx, disjoint_large_copy, "jint_disjoint_arraycopy", 9); -+ -+ StubRoutines::_jbyte_arraycopy = generate_conjoint_byte_copy(false, byte_small_copy, conjoint_large_copy_lasx, conjoint_large_copy_lsx, "jbyte_arraycopy"); -+ StubRoutines::_jshort_arraycopy = generate_conjoint_short_copy(false, short_small_copy, conjoint_large_copy_lasx, conjoint_large_copy, "jshort_arraycopy"); -+ StubRoutines::_jint_arraycopy = generate_conjoint_int_oop_copy(false, false, int_small_copy, conjoint_large_copy_lasx, conjoint_large_copy, "jint_arraycopy", 9); -+ } else if (UseLSX) { -+ StubRoutines::_jbyte_disjoint_arraycopy = generate_disjoint_byte_copy(false, byte_small_copy, disjoint_large_copy_lsx, none, "jbyte_disjoint_arraycopy"); -+ StubRoutines::_jshort_disjoint_arraycopy = generate_disjoint_short_copy(false, short_small_copy, disjoint_large_copy_lsx, disjoint_large_copy, "jshort_disjoint_arraycopy"); -+ StubRoutines::_jint_disjoint_arraycopy = generate_disjoint_int_oop_copy(false, false, int_small_copy, disjoint_large_copy_lsx, disjoint_large_copy, "jint_disjoint_arraycopy", 7); -+ -+ StubRoutines::_jbyte_arraycopy = generate_conjoint_byte_copy(false, byte_small_copy, conjoint_large_copy_lsx, none, "jbyte_arraycopy"); -+ StubRoutines::_jshort_arraycopy = generate_conjoint_short_copy(false, short_small_copy, conjoint_large_copy_lsx, conjoint_large_copy, "jshort_arraycopy"); -+ StubRoutines::_jint_arraycopy = generate_conjoint_int_oop_copy(false, false, int_small_copy, conjoint_large_copy_lsx, conjoint_large_copy, "jint_arraycopy", 7); -+ } else { -+ StubRoutines::_jbyte_disjoint_arraycopy = generate_disjoint_byte_copy(false, byte_small_copy, disjoint_large_copy, none, "jbyte_disjoint_arraycopy"); -+ StubRoutines::_jshort_disjoint_arraycopy = generate_disjoint_short_copy(false, short_small_copy, disjoint_large_copy, none, "jshort_disjoint_arraycopy"); -+ StubRoutines::_jint_disjoint_arraycopy = generate_disjoint_int_oop_copy(false, false, int_small_copy, disjoint_large_copy, none, "jint_disjoint_arraycopy", 7); -+ -+ StubRoutines::_jbyte_arraycopy = generate_conjoint_byte_copy(false, byte_small_copy, conjoint_large_copy, none, "jbyte_arraycopy"); -+ StubRoutines::_jshort_arraycopy = generate_conjoint_short_copy(false, short_small_copy, conjoint_large_copy, none, "jshort_arraycopy"); -+ StubRoutines::_jint_arraycopy = generate_conjoint_int_oop_copy(false, false, int_small_copy, conjoint_large_copy, none, "jint_arraycopy", 7); -+ } -+ -+ if (UseLASX) { -+ StubRoutines::_jlong_disjoint_arraycopy = generate_disjoint_long_oop_copy(false, false, long_small_copy, disjoint_large_copy, disjoint_large_copy_lasx, "jlong_disjoint_arraycopy", 5); -+ StubRoutines::_jlong_arraycopy = generate_conjoint_long_oop_copy(false, false, long_small_copy, conjoint_large_copy, conjoint_large_copy_lasx, "jlong_arraycopy", 5); -+ } else if (UseLSX) { -+ StubRoutines::_jlong_disjoint_arraycopy = generate_disjoint_long_oop_copy(false, false, long_small_copy, disjoint_large_copy, disjoint_large_copy_lsx, "jlong_disjoint_arraycopy", 4); -+ StubRoutines::_jlong_arraycopy = generate_conjoint_long_oop_copy(false, false, long_small_copy, conjoint_large_copy, conjoint_large_copy_lsx, "jlong_arraycopy", 4); -+ } else { -+ StubRoutines::_jlong_disjoint_arraycopy = generate_disjoint_long_oop_copy(false, false, long_small_copy, disjoint_large_copy, none, "jlong_disjoint_arraycopy", 4); -+ StubRoutines::_jlong_arraycopy = generate_conjoint_long_oop_copy(false, false, long_small_copy, conjoint_large_copy, none, "jlong_arraycopy", 4); -+ } ++ StubRoutines::_oop_disjoint_arraycopy = generate_disjoint_long_oop_copy(false, true, long_small_copy, disjoint_large_copy, ++ "oop_disjoint_arraycopy", long_oop_small_limit); ++ StubRoutines::_oop_disjoint_arraycopy_uninit = generate_disjoint_long_oop_copy(false, true, long_small_copy, disjoint_large_copy, ++ "oop_disjoint_arraycopy_uninit", long_oop_small_limit, true); ++ StubRoutines::_oop_arraycopy = generate_conjoint_long_oop_copy(false, true, long_small_copy, conjoint_large_copy, ++ "oop_arraycopy", long_oop_small_limit); ++ StubRoutines::_oop_arraycopy_uninit = generate_conjoint_long_oop_copy(false, true, long_small_copy, conjoint_large_copy, ++ "oop_arraycopy_uninit", long_oop_small_limit, true); ++ } ++ ++ StubRoutines::_jbyte_disjoint_arraycopy = generate_disjoint_byte_copy(false, byte_small_copy, disjoint_large_copy, "jbyte_disjoint_arraycopy"); ++ StubRoutines::_jshort_disjoint_arraycopy = generate_disjoint_short_copy(false, short_small_copy, disjoint_large_copy, "jshort_disjoint_arraycopy"); ++ StubRoutines::_jint_disjoint_arraycopy = generate_disjoint_int_oop_copy(false, false, int_small_copy, disjoint_large_copy, ++ "jint_disjoint_arraycopy", int_oop_small_limit); ++ ++ StubRoutines::_jbyte_arraycopy = generate_conjoint_byte_copy(false, byte_small_copy, conjoint_large_copy, "jbyte_arraycopy"); ++ StubRoutines::_jshort_arraycopy = generate_conjoint_short_copy(false, short_small_copy, conjoint_large_copy, "jshort_arraycopy"); ++ StubRoutines::_jint_arraycopy = generate_conjoint_int_oop_copy(false, false, int_small_copy, conjoint_large_copy, ++ "jint_arraycopy", int_oop_small_limit); ++ ++ StubRoutines::_jlong_disjoint_arraycopy = generate_disjoint_long_oop_copy(false, false, long_small_copy, disjoint_large_copy, ++ "jlong_disjoint_arraycopy", long_oop_small_limit); ++ StubRoutines::_jlong_arraycopy = generate_conjoint_long_oop_copy(false, false, long_small_copy, conjoint_large_copy, ++ "jlong_arraycopy", long_oop_small_limit); + + // We don't generate specialized code for HeapWord-aligned source + // arrays, so just use the code we've already generated @@ -56020,45 +55556,6 @@ index 00000000000..fbdc96f10f5 + return start; + } + -+ // add a function to implement SafeFetch32 and SafeFetchN -+ void generate_safefetch(const char* name, int size, address* entry, -+ address* fault_pc, address* continuation_pc) { -+ // safefetch signatures: -+ // int SafeFetch32(int* adr, int errValue); -+ // intptr_t SafeFetchN (intptr_t* adr, intptr_t errValue); -+ // -+ // arguments: -+ // A0 = adr -+ // A1 = errValue -+ // -+ // result: -+ // PPC_RET = *adr or errValue -+ StubCodeMark mark(this, "StubRoutines", name); -+ -+ // Entry point, pc or function descriptor. -+ *entry = __ pc(); -+ -+ // Load *adr into A1, may fault. -+ *fault_pc = __ pc(); -+ switch (size) { -+ case 4: -+ // int32_t -+ __ ld_w(A1, A0, 0); -+ break; -+ case 8: -+ // int64_t -+ __ ld_d(A1, A0, 0); -+ break; -+ default: -+ ShouldNotReachHere(); -+ } -+ -+ // return errValue or *adr -+ *continuation_pc = __ pc(); -+ __ add_d(V0, A1, R0); -+ __ jr(RA); -+ } -+ + +#undef __ +#define __ masm-> @@ -56812,14 +56309,6 @@ index 00000000000..fbdc96f10f5 + StubRoutines::_dcos = generate_dsin_dcos(/* isCos = */ true); + } + -+ // Safefetch stubs. -+ generate_safefetch("SafeFetch32", sizeof(int), &StubRoutines::_safefetch32_entry, -+ &StubRoutines::_safefetch32_fault_pc, -+ &StubRoutines::_safefetch32_continuation_pc); -+ generate_safefetch("SafeFetchN", sizeof(intptr_t), &StubRoutines::_safefetchN_entry, -+ &StubRoutines::_safefetchN_fault_pc, -+ &StubRoutines::_safefetchN_continuation_pc); -+ +#ifdef COMPILER2 + if (UseMulAddIntrinsic) { + StubRoutines::_mulAdd = generate_mulAdd(); @@ -56884,106 +56373,9 @@ index 00000000000..fbdc96f10f5 + } + StubGenerator g(code, all); +} -diff --git a/src/hotspot/cpu/loongarch/stubRoutines_loongarch.hpp b/src/hotspot/cpu/loongarch/stubRoutines_loongarch.hpp -new file mode 100644 -index 00000000000..20f2a14afcd ---- /dev/null -+++ b/src/hotspot/cpu/loongarch/stubRoutines_loongarch.hpp -@@ -0,0 +1,89 @@ -+/* -+ * Copyright (c) 2003, 2013, Oracle and/or its affiliates. All rights reserved. -+ * Copyright (c) 2015, 2022, Loongson Technology. All rights reserved. -+ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. -+ * -+ * This code is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 only, as -+ * published by the Free Software Foundation. -+ * -+ * This code is distributed in the hope that it will be useful, but WITHOUT -+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -+ * version 2 for more details (a copy is included in the LICENSE file that -+ * accompanied this code). -+ * -+ * You should have received a copy of the GNU General Public License version -+ * 2 along with this work; if not, write to the Free Software Foundation, -+ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. -+ * -+ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA -+ * or visit www.oracle.com if you need additional information or have any -+ * questions. -+ * -+ */ -+ -+#ifndef CPU_LOONGARCH_STUBROUTINES_LOONGARCH_64_HPP -+#define CPU_LOONGARCH_STUBROUTINES_LOONGARCH_64_HPP -+ -+// This file holds the platform specific parts of the StubRoutines -+// definition. See stubRoutines.hpp for a description on how to -+// extend it. -+ -+static bool returns_to_call_stub(address return_pc){ -+ return return_pc == _call_stub_return_address||return_pc == la::get_call_stub_compiled_return(); -+} -+ -+enum platform_dependent_constants { -+ code_size1 = 20000, // simply increase if too small (assembler will crash if too small) -+ code_size2 = 60000 // simply increase if too small (assembler will crash if too small) -+}; -+ -+class la { -+ friend class StubGenerator; -+ friend class VMStructs; -+ private: -+ // If we call compiled code directly from the call stub we will -+ // need to adjust the return back to the call stub to a specialized -+ // piece of code that can handle compiled results and cleaning the fpu -+ // stack. The variable holds that location. -+ static address _call_stub_compiled_return; -+ static address _vector_iota_indices; -+ static juint _crc_table[]; -+ static address _method_entry_barrier; -+ // begin trigonometric tables block. See comments in .cpp file -+ static juint _npio2_hw[]; -+ static jdouble _two_over_pi[]; -+ static jdouble _pio2[]; -+ static jdouble _dsin_coef[]; -+ static jdouble _dcos_coef[]; -+ // end trigonometric tables block -+ -+ static address _string_indexof_linear_ll; -+ static address _string_indexof_linear_uu; -+ static address _string_indexof_linear_ul; -+ -+public: -+ // Call back points for traps in compiled code -+ static address get_call_stub_compiled_return() { return _call_stub_compiled_return; } -+ static void set_call_stub_compiled_return(address ret){ _call_stub_compiled_return = ret; } -+ static address vector_iota_indices() { return _vector_iota_indices; } -+ -+ static address method_entry_barrier() { -+ return _method_entry_barrier; -+ } -+ -+ static address string_indexof_linear_ul() { -+ return _string_indexof_linear_ul; -+ } -+ -+ static address string_indexof_linear_ll() { -+ return _string_indexof_linear_ll; -+ } -+ -+ static address string_indexof_linear_uu() { -+ return _string_indexof_linear_uu; -+ } -+}; -+ -+#endif // CPU_LOONGARCH_STUBROUTINES_LOONGARCH_64_HPP -diff --git a/src/hotspot/cpu/loongarch/stubRoutines_loongarch_64.cpp b/src/hotspot/cpu/loongarch/stubRoutines_loongarch_64.cpp -new file mode 100644 -index 00000000000..53ded54ae6c ---- /dev/null -+++ b/src/hotspot/cpu/loongarch/stubRoutines_loongarch_64.cpp +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/stubRoutines_loongarch_64.cpp b/src/hotspot/cpu/loongarch/stubRoutines_loongarch_64.cpp +--- a/src/hotspot/cpu/loongarch/stubRoutines_loongarch_64.cpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/loongarch/stubRoutines_loongarch_64.cpp 2024-01-31 14:01:11.604095562 +0800 @@ -0,0 +1,183 @@ +/* + * Copyright (c) 2003, 2013, Oracle and/or its affiliates. All rights reserved. @@ -57168,12 +56560,10 @@ index 00000000000..53ded54ae6c + 2.73370053816464559624e-44, // 0x36E3822280000000 + 2.16741683877804819444e-51, // 0x3569F31D00000000 +}; -diff --git a/src/hotspot/cpu/loongarch/templateInterpreterGenerator_loongarch.cpp b/src/hotspot/cpu/loongarch/templateInterpreterGenerator_loongarch.cpp -new file mode 100644 -index 00000000000..88b938103bc ---- /dev/null -+++ b/src/hotspot/cpu/loongarch/templateInterpreterGenerator_loongarch.cpp -@@ -0,0 +1,2197 @@ +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/stubRoutines_loongarch.hpp b/src/hotspot/cpu/loongarch/stubRoutines_loongarch.hpp +--- a/src/hotspot/cpu/loongarch/stubRoutines_loongarch.hpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/loongarch/stubRoutines_loongarch.hpp 2024-01-31 14:01:11.604095562 +0800 +@@ -0,0 +1,89 @@ +/* + * Copyright (c) 2003, 2013, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 2015, 2022, Loongson Technology. All rights reserved. @@ -57199,6 +56589,99 @@ index 00000000000..88b938103bc + * + */ + ++#ifndef CPU_LOONGARCH_STUBROUTINES_LOONGARCH_64_HPP ++#define CPU_LOONGARCH_STUBROUTINES_LOONGARCH_64_HPP ++ ++// This file holds the platform specific parts of the StubRoutines ++// definition. See stubRoutines.hpp for a description on how to ++// extend it. ++ ++static bool returns_to_call_stub(address return_pc){ ++ return return_pc == _call_stub_return_address||return_pc == la::get_call_stub_compiled_return(); ++} ++ ++enum platform_dependent_constants { ++ code_size1 = 20000, // simply increase if too small (assembler will crash if too small) ++ code_size2 = 60000 // simply increase if too small (assembler will crash if too small) ++}; ++ ++class la { ++ friend class StubGenerator; ++ friend class VMStructs; ++ private: ++ // If we call compiled code directly from the call stub we will ++ // need to adjust the return back to the call stub to a specialized ++ // piece of code that can handle compiled results and cleaning the fpu ++ // stack. The variable holds that location. ++ static address _call_stub_compiled_return; ++ static address _vector_iota_indices; ++ static juint _crc_table[]; ++ static address _method_entry_barrier; ++ // begin trigonometric tables block. See comments in .cpp file ++ static juint _npio2_hw[]; ++ static jdouble _two_over_pi[]; ++ static jdouble _pio2[]; ++ static jdouble _dsin_coef[]; ++ static jdouble _dcos_coef[]; ++ // end trigonometric tables block ++ ++ static address _string_indexof_linear_ll; ++ static address _string_indexof_linear_uu; ++ static address _string_indexof_linear_ul; ++ ++public: ++ // Call back points for traps in compiled code ++ static address get_call_stub_compiled_return() { return _call_stub_compiled_return; } ++ static void set_call_stub_compiled_return(address ret){ _call_stub_compiled_return = ret; } ++ static address vector_iota_indices() { return _vector_iota_indices; } ++ ++ static address method_entry_barrier() { ++ return _method_entry_barrier; ++ } ++ ++ static address string_indexof_linear_ul() { ++ return _string_indexof_linear_ul; ++ } ++ ++ static address string_indexof_linear_ll() { ++ return _string_indexof_linear_ll; ++ } ++ ++ static address string_indexof_linear_uu() { ++ return _string_indexof_linear_uu; ++ } ++}; ++ ++#endif // CPU_LOONGARCH_STUBROUTINES_LOONGARCH_64_HPP +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/templateInterpreterGenerator_loongarch.cpp b/src/hotspot/cpu/loongarch/templateInterpreterGenerator_loongarch.cpp +--- a/src/hotspot/cpu/loongarch/templateInterpreterGenerator_loongarch.cpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/loongarch/templateInterpreterGenerator_loongarch.cpp 2024-01-31 14:01:11.604095562 +0800 +@@ -0,0 +1,2197 @@ ++/* ++ * Copyright (c) 2003, 2013, Oracle and/or its affiliates. All rights reserved. ++ * Copyright (c) 2015, 2023, Loongson Technology. All rights reserved. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ * ++ */ ++ +#include "precompiled.hpp" +#include "asm/macroAssembler.hpp" +#include "classfile/javaClasses.hpp" @@ -58554,8 +58037,8 @@ index 00000000000..88b938103bc +#endif + + __ li(t, _thread_in_native); -+ if(os::is_MP()) { -+ __ dbar(0); // store release ++ if (os::is_MP()) { ++ __ membar(Assembler::Membar_mask_bits(__ LoadStore|__ StoreStore)); + } + __ st_w(t, thread, in_bytes(JavaThread::thread_state_offset())); + @@ -58579,8 +58062,8 @@ index 00000000000..88b938103bc + __ get_thread(thread); +#endif + __ li(t, _thread_in_native_trans); -+ if(os::is_MP()) { -+ __ dbar(0); // store release ++ if (os::is_MP()) { ++ __ membar(Assembler::Membar_mask_bits(__ LoadStore|__ StoreStore)); + } + __ st_w(t, thread, in_bytes(JavaThread::thread_state_offset())); + @@ -58623,8 +58106,8 @@ index 00000000000..88b938103bc + + // change thread state + __ li(t, _thread_in_Java); -+ if(os::is_MP()) { -+ __ dbar(0); // store release ++ if (os::is_MP()) { ++ __ membar(Assembler::Membar_mask_bits(__ LoadStore|__ StoreStore)); + } + __ st_w(t, thread, in_bytes(JavaThread::thread_state_offset())); + __ reset_last_Java_frame(thread, true); @@ -59371,61 +58854,10 @@ index 00000000000..88b938103bc + __ bind(L); +} +#endif // !PRODUCT -diff --git a/src/hotspot/cpu/loongarch/templateTable_loongarch.hpp b/src/hotspot/cpu/loongarch/templateTable_loongarch.hpp -new file mode 100644 -index 00000000000..ddb38faf446 ---- /dev/null -+++ b/src/hotspot/cpu/loongarch/templateTable_loongarch.hpp -@@ -0,0 +1,43 @@ -+/* -+ * Copyright (c) 2003, 2012, Oracle and/or its affiliates. All rights reserved. -+ * Copyright (c) 2015, 2022, Loongson Technology. All rights reserved. -+ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. -+ * -+ * This code is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 only, as -+ * published by the Free Software Foundation. -+ * -+ * This code is distributed in the hope that it will be useful, but WITHOUT -+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -+ * version 2 for more details (a copy is included in the LICENSE file that -+ * accompanied this code). -+ * -+ * You should have received a copy of the GNU General Public License version -+ * 2 along with this work; if not, write to the Free Software Foundation, -+ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. -+ * -+ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA -+ * or visit www.oracle.com if you need additional information or have any -+ * questions. -+ * -+ */ -+ -+#ifndef CPU_LOONGARCH_TEMPLATETABLE_LOONGARCH_64_HPP -+#define CPU_LOONGARCH_TEMPLATETABLE_LOONGARCH_64_HPP -+ -+ static void prepare_invoke(int byte_no, -+ Register method, // linked method (or i-klass) -+ Register index = noreg, // itable index, MethodType, etc. -+ Register recv = noreg, // if caller wants to see it -+ Register flags = noreg // if caller wants to test it -+ ); -+ static void invokevirtual_helper(Register index, Register recv, -+ Register flags); -+ static void volatile_barrier(); -+ -+ // Helpers -+ static void index_check(Register array, Register index); -+ static void index_check_without_pop(Register array, Register index); -+ -+#endif // CPU_LOONGARCH_TEMPLATETABLE_LOONGARCH_64_HPP -diff --git a/src/hotspot/cpu/loongarch/templateTable_loongarch_64.cpp b/src/hotspot/cpu/loongarch/templateTable_loongarch_64.cpp -new file mode 100644 -index 00000000000..138bf701bf8 ---- /dev/null -+++ b/src/hotspot/cpu/loongarch/templateTable_loongarch_64.cpp -@@ -0,0 +1,4077 @@ +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/templateTable_loongarch_64.cpp b/src/hotspot/cpu/loongarch/templateTable_loongarch_64.cpp +--- a/src/hotspot/cpu/loongarch/templateTable_loongarch_64.cpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/loongarch/templateTable_loongarch_64.cpp 2024-01-31 14:01:11.604095562 +0800 +@@ -0,0 +1,4043 @@ +/* + * Copyright (c) 2003, 2013, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 2015, 2021, Loongson Technology. All rights reserved. @@ -61604,38 +61036,6 @@ index 00000000000..138bf701bf8 + __ jr(T4); +} + -+// ---------------------------------------------------------------------------- -+// Volatile variables demand their effects be made known to all CPU's -+// in order. Store buffers on most chips allow reads & writes to -+// reorder; the JMM's ReadAfterWrite.java test fails in -Xint mode -+// without some kind of memory barrier (i.e., it's not sufficient that -+// the interpreter does not reorder volatile references, the hardware -+// also must not reorder them). -+// -+// According to the new Java Memory Model (JMM): -+// (1) All volatiles are serialized wrt to each other. ALSO reads & -+// writes act as aquire & release, so: -+// (2) A read cannot let unrelated NON-volatile memory refs that -+// happen after the read float up to before the read. It's OK for -+// non-volatile memory refs that happen before the volatile read to -+// float down below it. -+// (3) Similar a volatile write cannot let unrelated NON-volatile -+// memory refs that happen BEFORE the write float down to after the -+// write. It's OK for non-volatile memory refs that happen after the -+// volatile write to float up before it. -+// -+// We only put in barriers around volatile refs (they are expensive), -+// not _between_ memory refs (that would require us to track the -+// flavor of the previous memory refs). Requirements (2) and (3) -+// require some barriers before volatile stores and after volatile -+// loads. These nearly cover requirement (1) but miss the -+// volatile-store-volatile-load case. This final case is placed after -+// volatile-stores although it could just as well go before -+// volatile-loads. -+void TemplateTable::volatile_barrier() { -+ if(os::is_MP()) __ membar(__ StoreLoad); -+} -+ +// we dont shift left 2 bits in get_cache_and_index_at_bcp +// for we always need shift the index we use it. the ConstantPoolCacheEntry +// is 16-byte long, index is the index in @@ -61840,7 +61240,7 @@ index 00000000000..138bf701bf8 + + Label notVolatile; + __ beq(scratch, R0, notVolatile); -+ volatile_barrier(); ++ __ membar(MacroAssembler::AnyAny); + __ bind(notVolatile); + } + @@ -61986,7 +61386,7 @@ index 00000000000..138bf701bf8 + { + Label notVolatile; + __ beq(scratch, R0, notVolatile); -+ volatile_barrier(); ++ __ membar(Assembler::Membar_mask_bits(__ LoadLoad | __ LoadStore)); + __ bind(notVolatile); + } +} @@ -62102,7 +61502,7 @@ index 00000000000..138bf701bf8 + + Label notVolatile; + __ beq(scratch, R0, notVolatile); -+ volatile_barrier(); ++ __ membar(Assembler::Membar_mask_bits(__ StoreStore | __ LoadStore)); + __ bind(notVolatile); + } + @@ -62274,7 +61674,7 @@ index 00000000000..138bf701bf8 + { + Label notVolatile; + __ beq(scratch, R0, notVolatile); -+ volatile_barrier(); ++ __ membar(Assembler::Membar_mask_bits(__ StoreLoad | __ StoreStore)); + __ bind(notVolatile); + } +} @@ -62384,7 +61784,7 @@ index 00000000000..138bf701bf8 + + Label notVolatile; + __ beq(scratch, R0, notVolatile); -+ volatile_barrier(); ++ __ membar(Assembler::Membar_mask_bits(__ StoreStore | __ LoadStore)); + __ bind(notVolatile); + } + @@ -62433,7 +61833,7 @@ index 00000000000..138bf701bf8 + { + Label notVolatile; + __ beq(scratch, R0, notVolatile); -+ volatile_barrier(); ++ __ membar(Assembler::Membar_mask_bits(__ StoreLoad | __ StoreStore)); + __ bind(notVolatile); + } +} @@ -62484,7 +61884,7 @@ index 00000000000..138bf701bf8 + + Label notVolatile; + __ beq(scratch, R0, notVolatile); -+ volatile_barrier(); ++ __ membar(MacroAssembler::AnyAny); + __ bind(notVolatile); + } + @@ -62528,7 +61928,7 @@ index 00000000000..138bf701bf8 + { + Label notVolatile; + __ beq(scratch, R0, notVolatile); -+ volatile_barrier(); ++ __ membar(Assembler::Membar_mask_bits(__ LoadLoad | __ LoadStore)); + __ bind(notVolatile); + } +} @@ -62558,7 +61958,7 @@ index 00000000000..138bf701bf8 + + Label notVolatile; + __ beq(scratch, R0, notVolatile); -+ volatile_barrier(); ++ __ membar(MacroAssembler::AnyAny); + __ bind(notVolatile); + } + @@ -62583,7 +61983,7 @@ index 00000000000..138bf701bf8 + { + Label notVolatile; + __ beq(scratch, R0, notVolatile); -+ volatile_barrier(); ++ __ membar(Assembler::Membar_mask_bits(__ LoadLoad | __ LoadStore)); + __ bind(notVolatile); + } +} @@ -62906,7 +62306,6 @@ index 00000000000..138bf701bf8 + + __ bind(no_such_method); + // throw exception -+ __ pop(Rmethod); // pop return address (pushed by prepare_invoke) + __ restore_bcp(); + __ restore_locals(); + // Pass arguments for generating a verbose error message. @@ -62920,7 +62319,6 @@ index 00000000000..138bf701bf8 + + __ bind(no_such_interface); + // throw exception -+ __ pop(Rmethod); // pop return address (pushed by prepare_invoke) + __ restore_bcp(); + __ restore_locals(); + // Pass arguments for generating a verbose error message. @@ -63503,99 +62901,307 @@ index 00000000000..138bf701bf8 + __ alsl_d(SP, AT, SP, Address::times_8 - 1); + __ membar(__ AnyAny);//no membar here for aarch64 +} -diff --git a/src/hotspot/cpu/loongarch/universalNativeInvoker_loongarch_64.cpp b/src/hotspot/cpu/loongarch/universalNativeInvoker_loongarch_64.cpp -new file mode 100644 -index 00000000000..87f6a113268 ---- /dev/null -+++ b/src/hotspot/cpu/loongarch/universalNativeInvoker_loongarch_64.cpp -@@ -0,0 +1,32 @@ -+/* -+ * Copyright (c) 2020, Red Hat, Inc. All rights reserved. -+ * Copyright (c) 2021, Loongson Technology. All rights reserved. -+ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. -+ * -+ * This code is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 only, as -+ * published by the Free Software Foundation. -+ * -+ * This code is distributed in the hope that it will be useful, but WITHOUT -+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -+ * version 2 for more details (a copy is included in the LICENSE file that -+ * accompanied this code). -+ * -+ * You should have received a copy of the GNU General Public License version -+ * 2 along with this work; if not, write to the Free Software Foundation, -+ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. -+ * -+ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA -+ * or visit www.oracle.com if you need additional information or have any -+ * questions. -+ */ -+ -+#include "precompiled.hpp" -+#include "prims/universalNativeInvoker.hpp" -+#include "utilities/debug.hpp" -+ -+address ProgrammableInvoker::generate_adapter(jobject jabi, jobject jlayout) { -+ Unimplemented(); -+ return nullptr; -+} -diff --git a/src/hotspot/cpu/loongarch/universalUpcallHandler_loongarch_64.cpp b/src/hotspot/cpu/loongarch/universalUpcallHandler_loongarch_64.cpp -new file mode 100644 -index 00000000000..7586b084868 ---- /dev/null -+++ b/src/hotspot/cpu/loongarch/universalUpcallHandler_loongarch_64.cpp -@@ -0,0 +1,41 @@ -+/* -+ * Copyright (c) 2020, Red Hat, Inc. All rights reserved. -+ * Copyright (c) 2021, Loongson Technology. All rights reserved. -+ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. -+ * -+ * This code is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 only, as -+ * published by the Free Software Foundation. -+ * -+ * This code is distributed in the hope that it will be useful, but WITHOUT -+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -+ * version 2 for more details (a copy is included in the LICENSE file that -+ * accompanied this code). -+ * -+ * You should have received a copy of the GNU General Public License version -+ * 2 along with this work; if not, write to the Free Software Foundation, -+ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. -+ * -+ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA -+ * or visit www.oracle.com if you need additional information or have any -+ * questions. -+ */ -+ -+#include "precompiled.hpp" -+#include "prims/universalUpcallHandler.hpp" -+#include "utilities/debug.hpp" -+ -+address ProgrammableUpcallHandler::generate_upcall_stub(jobject rec, jobject jabi, jobject jlayout) { -+ Unimplemented(); -+ return nullptr; -+} -+ -+address ProgrammableUpcallHandler::generate_optimized_upcall_stub(jobject mh, Method* entry, jobject jabi, jobject jconv) { -+ ShouldNotCallThis(); -+ return nullptr; -+} -+ -+bool ProgrammableUpcallHandler::supports_optimized_upcalls() { -+ return false; -+} -diff --git a/src/hotspot/cpu/loongarch/vmStructs_loongarch.hpp b/src/hotspot/cpu/loongarch/vmStructs_loongarch.hpp -new file mode 100644 -index 00000000000..5b9f7b78981 ---- /dev/null -+++ b/src/hotspot/cpu/loongarch/vmStructs_loongarch.hpp -@@ -0,0 +1,61 @@ +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/templateTable_loongarch.hpp b/src/hotspot/cpu/loongarch/templateTable_loongarch.hpp +--- a/src/hotspot/cpu/loongarch/templateTable_loongarch.hpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/loongarch/templateTable_loongarch.hpp 2024-01-31 14:01:11.604095562 +0800 +@@ -0,0 +1,43 @@ +/* -+ * Copyright (c) 2001, 2013, Oracle and/or its affiliates. All rights reserved. ++ * Copyright (c) 2003, 2012, Oracle and/or its affiliates. All rights reserved. ++ * Copyright (c) 2015, 2022, Loongson Technology. All rights reserved. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ * ++ */ ++ ++#ifndef CPU_LOONGARCH_TEMPLATETABLE_LOONGARCH_64_HPP ++#define CPU_LOONGARCH_TEMPLATETABLE_LOONGARCH_64_HPP ++ ++ static void prepare_invoke(int byte_no, ++ Register method, // linked method (or i-klass) ++ Register index = noreg, // itable index, MethodType, etc. ++ Register recv = noreg, // if caller wants to see it ++ Register flags = noreg // if caller wants to test it ++ ); ++ static void invokevirtual_helper(Register index, Register recv, ++ Register flags); ++ static void volatile_barrier(); ++ ++ // Helpers ++ static void index_check(Register array, Register index); ++ static void index_check_without_pop(Register array, Register index); ++ ++#endif // CPU_LOONGARCH_TEMPLATETABLE_LOONGARCH_64_HPP +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/universalNativeInvoker_loongarch_64.cpp b/src/hotspot/cpu/loongarch/universalNativeInvoker_loongarch_64.cpp +--- a/src/hotspot/cpu/loongarch/universalNativeInvoker_loongarch_64.cpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/loongarch/universalNativeInvoker_loongarch_64.cpp 2024-01-31 14:01:11.604095562 +0800 +@@ -0,0 +1,32 @@ ++/* ++ * Copyright (c) 2020, Red Hat, Inc. All rights reserved. ++ * Copyright (c) 2021, Loongson Technology. All rights reserved. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ */ ++ ++#include "precompiled.hpp" ++#include "prims/universalNativeInvoker.hpp" ++#include "utilities/debug.hpp" ++ ++address ProgrammableInvoker::generate_adapter(jobject jabi, jobject jlayout) { ++ Unimplemented(); ++ return nullptr; ++} +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/universalUpcallHandler_loongarch_64.cpp b/src/hotspot/cpu/loongarch/universalUpcallHandler_loongarch_64.cpp +--- a/src/hotspot/cpu/loongarch/universalUpcallHandler_loongarch_64.cpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/loongarch/universalUpcallHandler_loongarch_64.cpp 2024-01-31 14:01:11.604095562 +0800 +@@ -0,0 +1,41 @@ ++/* ++ * Copyright (c) 2020, Red Hat, Inc. All rights reserved. ++ * Copyright (c) 2021, Loongson Technology. All rights reserved. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ */ ++ ++#include "precompiled.hpp" ++#include "prims/universalUpcallHandler.hpp" ++#include "utilities/debug.hpp" ++ ++address ProgrammableUpcallHandler::generate_upcall_stub(jobject rec, jobject jabi, jobject jlayout) { ++ Unimplemented(); ++ return nullptr; ++} ++ ++address ProgrammableUpcallHandler::generate_optimized_upcall_stub(jobject mh, Method* entry, jobject jabi, jobject jconv) { ++ ShouldNotCallThis(); ++ return nullptr; ++} ++ ++bool ProgrammableUpcallHandler::supports_optimized_upcalls() { ++ return false; ++} +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/vmreg_loongarch.cpp b/src/hotspot/cpu/loongarch/vmreg_loongarch.cpp +--- a/src/hotspot/cpu/loongarch/vmreg_loongarch.cpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/loongarch/vmreg_loongarch.cpp 2024-01-31 14:01:11.604095562 +0800 +@@ -0,0 +1,58 @@ ++/* ++ * Copyright (c) 2006, 2012, Oracle and/or its affiliates. All rights reserved. ++ * Copyright (c) 2015, 2022, Loongson Technology. All rights reserved. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ * ++ */ ++ ++#include "precompiled.hpp" ++#include "asm/assembler.hpp" ++#include "code/vmreg.hpp" ++ ++ ++ ++void VMRegImpl::set_regName() { ++ Register reg = ::as_Register(0); ++ int i; ++ for (i = 0; i < ConcreteRegisterImpl::max_gpr ; ) { ++ for (int j = 0 ; j < RegisterImpl::max_slots_per_register ; j++) { ++ regName[i++] = reg->name(); ++ } ++ reg = reg->successor(); ++ } ++ ++ FloatRegister freg = ::as_FloatRegister(0); ++ for ( ; i < ConcreteRegisterImpl::max_fpr ; ) { ++ for (int j = 0 ; j < FloatRegisterImpl::max_slots_per_register ; j++) { ++ regName[i++] = freg->name(); ++ } ++ freg = freg->successor(); ++ } ++ ++ for ( ; i < ConcreteRegisterImpl::number_of_registers ; i ++ ) { ++ regName[i] = "NON-GPR-FPR"; ++ } ++} ++ ++VMReg VMRegImpl::vmStorageToVMReg(int type, int index) { ++ Unimplemented(); ++ return VMRegImpl::Bad(); ++} +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/vmreg_loongarch.hpp b/src/hotspot/cpu/loongarch/vmreg_loongarch.hpp +--- a/src/hotspot/cpu/loongarch/vmreg_loongarch.hpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/loongarch/vmreg_loongarch.hpp 2024-01-31 14:01:11.604095562 +0800 +@@ -0,0 +1,58 @@ ++/* ++ * Copyright (c) 2006, 2010, Oracle and/or its affiliates. All rights reserved. ++ * Copyright (c) 2015, 2022, Loongson Technology. All rights reserved. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ * ++ */ ++ ++#ifndef CPU_LOONGARCH_VMREG_LOONGARCH_HPP ++#define CPU_LOONGARCH_VMREG_LOONGARCH_HPP ++ ++inline bool is_Register() { ++ return (unsigned int) value() < (unsigned int) ConcreteRegisterImpl::max_gpr; ++} ++ ++inline Register as_Register() { ++ assert( is_Register(), "must be"); ++ return ::as_Register(value() / RegisterImpl::max_slots_per_register); ++} ++ ++inline bool is_FloatRegister() { ++ return value() >= ConcreteRegisterImpl::max_gpr && value() < ConcreteRegisterImpl::max_fpr; ++} ++ ++inline FloatRegister as_FloatRegister() { ++ assert( is_FloatRegister() && is_even(value()), "must be" ); ++ return ::as_FloatRegister((value() - ConcreteRegisterImpl::max_gpr) / ++ FloatRegisterImpl::max_slots_per_register); ++} ++ ++inline bool is_concrete() { ++ assert(is_reg(), "must be"); ++ if (is_FloatRegister()) { ++ int base = value() - ConcreteRegisterImpl::max_gpr; ++ return base % FloatRegisterImpl::max_slots_per_register == 0; ++ } else { ++ return is_even(value()); ++ } ++} ++ ++#endif // CPU_LOONGARCH_VMREG_LOONGARCH_HPP +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/vmreg_loongarch.inline.hpp b/src/hotspot/cpu/loongarch/vmreg_loongarch.inline.hpp +--- a/src/hotspot/cpu/loongarch/vmreg_loongarch.inline.hpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/loongarch/vmreg_loongarch.inline.hpp 2024-01-31 14:01:11.604095562 +0800 +@@ -0,0 +1,39 @@ ++/* ++ * Copyright (c) 2006, 2012, Oracle and/or its affiliates. All rights reserved. ++ * Copyright (c) 2015, 2022, Loongson Technology. All rights reserved. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ * ++ */ ++ ++#ifndef CPU_LOONGARCH_VMREG_LOONGARCH_INLINE_HPP ++#define CPU_LOONGARCH_VMREG_LOONGARCH_INLINE_HPP ++ ++inline VMReg RegisterImpl::as_VMReg() { ++ if( this==noreg ) return VMRegImpl::Bad(); ++ return VMRegImpl::as_VMReg(encoding() * RegisterImpl::max_slots_per_register); ++} ++ ++inline VMReg FloatRegisterImpl::as_VMReg() { ++ return VMRegImpl::as_VMReg((encoding() * FloatRegisterImpl::max_slots_per_register) + ++ ConcreteRegisterImpl::max_gpr); ++} ++ ++#endif // CPU_LOONGARCH_VMREG_LOONGARCH_INLINE_HPP +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/vmStructs_loongarch.hpp b/src/hotspot/cpu/loongarch/vmStructs_loongarch.hpp +--- a/src/hotspot/cpu/loongarch/vmStructs_loongarch.hpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/loongarch/vmStructs_loongarch.hpp 2024-01-31 14:01:11.604095562 +0800 +@@ -0,0 +1,61 @@ ++/* ++ * Copyright (c) 2001, 2013, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 2015, 2022, Loongson Technology. All rights reserved. + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. + * @@ -63655,11 +63261,9 @@ index 00000000000..5b9f7b78981 + /* be present there) */ + +#endif // CPU_LOONGARCH_VMSTRUCTS_LOONGARCH_HPP -diff --git a/src/hotspot/cpu/loongarch/vm_version_ext_loongarch.cpp b/src/hotspot/cpu/loongarch/vm_version_ext_loongarch.cpp -new file mode 100644 -index 00000000000..31da20e6f39 ---- /dev/null -+++ b/src/hotspot/cpu/loongarch/vm_version_ext_loongarch.cpp +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/vm_version_ext_loongarch.cpp b/src/hotspot/cpu/loongarch/vm_version_ext_loongarch.cpp +--- a/src/hotspot/cpu/loongarch/vm_version_ext_loongarch.cpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/loongarch/vm_version_ext_loongarch.cpp 2024-01-31 14:01:11.604095562 +0800 @@ -0,0 +1,85 @@ +/* + * Copyright (c) 2013, 2018, Oracle and/or its affiliates. All rights reserved. @@ -63746,11 +63350,9 @@ index 00000000000..31da20e6f39 + strncpy(tmp, _cpu_desc, CPU_DETAILED_DESC_BUF_SIZE); + return tmp; +} -diff --git a/src/hotspot/cpu/loongarch/vm_version_ext_loongarch.hpp b/src/hotspot/cpu/loongarch/vm_version_ext_loongarch.hpp -new file mode 100644 -index 00000000000..1a93123134c ---- /dev/null -+++ b/src/hotspot/cpu/loongarch/vm_version_ext_loongarch.hpp +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/vm_version_ext_loongarch.hpp b/src/hotspot/cpu/loongarch/vm_version_ext_loongarch.hpp +--- a/src/hotspot/cpu/loongarch/vm_version_ext_loongarch.hpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/loongarch/vm_version_ext_loongarch.hpp 2024-01-31 14:01:11.604095562 +0800 @@ -0,0 +1,54 @@ +/* + * Copyright (c) 2016, 2018, Oracle and/or its affiliates. All rights reserved. @@ -63806,11 +63408,9 @@ index 00000000000..1a93123134c +}; + +#endif // CPU_LOONGARCH_VM_VERSION_EXT_LOONGARCH_HPP -diff --git a/src/hotspot/cpu/loongarch/vm_version_loongarch.cpp b/src/hotspot/cpu/loongarch/vm_version_loongarch.cpp -new file mode 100644 -index 00000000000..c9a19b379b7 ---- /dev/null -+++ b/src/hotspot/cpu/loongarch/vm_version_loongarch.cpp +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/vm_version_loongarch.cpp b/src/hotspot/cpu/loongarch/vm_version_loongarch.cpp +--- a/src/hotspot/cpu/loongarch/vm_version_loongarch.cpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/loongarch/vm_version_loongarch.cpp 2024-01-31 14:01:11.604095562 +0800 @@ -0,0 +1,432 @@ +/* + * Copyright (c) 1997, 2014, Oracle and/or its affiliates. All rights reserved. @@ -63989,7 +63589,7 @@ index 00000000000..c9a19b379b7 + _supports_cx8 = true; + + if (UseG1GC && FLAG_IS_DEFAULT(MaxGCPauseMillis)) { -+ FLAG_SET_CMDLINE(MaxGCPauseMillis, 650); ++ FLAG_SET_DEFAULT(MaxGCPauseMillis, 150); + } + + if (supports_lsx()) { @@ -64244,11 +63844,9 @@ index 00000000000..c9a19b379b7 + + get_processor_features(); +} -diff --git a/src/hotspot/cpu/loongarch/vm_version_loongarch.hpp b/src/hotspot/cpu/loongarch/vm_version_loongarch.hpp -new file mode 100644 -index 00000000000..cae9f863c30 ---- /dev/null -+++ b/src/hotspot/cpu/loongarch/vm_version_loongarch.hpp +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/vm_version_loongarch.hpp b/src/hotspot/cpu/loongarch/vm_version_loongarch.hpp +--- a/src/hotspot/cpu/loongarch/vm_version_loongarch.hpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/loongarch/vm_version_loongarch.hpp 2024-01-31 14:01:11.604095562 +0800 @@ -0,0 +1,295 @@ +/* + * Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved. @@ -64545,184 +64143,9 @@ index 00000000000..cae9f863c30 +}; + +#endif // CPU_LOONGARCH_VM_VERSION_LOONGARCH_HPP -diff --git a/src/hotspot/cpu/loongarch/vmreg_loongarch.cpp b/src/hotspot/cpu/loongarch/vmreg_loongarch.cpp -new file mode 100644 -index 00000000000..79d2560f494 ---- /dev/null -+++ b/src/hotspot/cpu/loongarch/vmreg_loongarch.cpp -@@ -0,0 +1,58 @@ -+/* -+ * Copyright (c) 2006, 2012, Oracle and/or its affiliates. All rights reserved. -+ * Copyright (c) 2015, 2022, Loongson Technology. All rights reserved. -+ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. -+ * -+ * This code is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 only, as -+ * published by the Free Software Foundation. -+ * -+ * This code is distributed in the hope that it will be useful, but WITHOUT -+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -+ * version 2 for more details (a copy is included in the LICENSE file that -+ * accompanied this code). -+ * -+ * You should have received a copy of the GNU General Public License version -+ * 2 along with this work; if not, write to the Free Software Foundation, -+ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. -+ * -+ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA -+ * or visit www.oracle.com if you need additional information or have any -+ * questions. -+ * -+ */ -+ -+#include "precompiled.hpp" -+#include "asm/assembler.hpp" -+#include "code/vmreg.hpp" -+ -+ -+ -+void VMRegImpl::set_regName() { -+ Register reg = ::as_Register(0); -+ int i; -+ for (i = 0; i < ConcreteRegisterImpl::max_gpr ; ) { -+ for (int j = 0 ; j < RegisterImpl::max_slots_per_register ; j++) { -+ regName[i++] = reg->name(); -+ } -+ reg = reg->successor(); -+ } -+ -+ FloatRegister freg = ::as_FloatRegister(0); -+ for ( ; i < ConcreteRegisterImpl::max_fpr ; ) { -+ for (int j = 0 ; j < FloatRegisterImpl::max_slots_per_register ; j++) { -+ regName[i++] = freg->name(); -+ } -+ freg = freg->successor(); -+ } -+ -+ for ( ; i < ConcreteRegisterImpl::number_of_registers ; i ++ ) { -+ regName[i] = "NON-GPR-FPR"; -+ } -+} -+ -+VMReg VMRegImpl::vmStorageToVMReg(int type, int index) { -+ Unimplemented(); -+ return VMRegImpl::Bad(); -+} -diff --git a/src/hotspot/cpu/loongarch/vmreg_loongarch.hpp b/src/hotspot/cpu/loongarch/vmreg_loongarch.hpp -new file mode 100644 -index 00000000000..819eaff0bb3 ---- /dev/null -+++ b/src/hotspot/cpu/loongarch/vmreg_loongarch.hpp -@@ -0,0 +1,58 @@ -+/* -+ * Copyright (c) 2006, 2010, Oracle and/or its affiliates. All rights reserved. -+ * Copyright (c) 2015, 2022, Loongson Technology. All rights reserved. -+ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. -+ * -+ * This code is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 only, as -+ * published by the Free Software Foundation. -+ * -+ * This code is distributed in the hope that it will be useful, but WITHOUT -+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -+ * version 2 for more details (a copy is included in the LICENSE file that -+ * accompanied this code). -+ * -+ * You should have received a copy of the GNU General Public License version -+ * 2 along with this work; if not, write to the Free Software Foundation, -+ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. -+ * -+ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA -+ * or visit www.oracle.com if you need additional information or have any -+ * questions. -+ * -+ */ -+ -+#ifndef CPU_LOONGARCH_VMREG_LOONGARCH_HPP -+#define CPU_LOONGARCH_VMREG_LOONGARCH_HPP -+ -+inline bool is_Register() { -+ return (unsigned int) value() < (unsigned int) ConcreteRegisterImpl::max_gpr; -+} -+ -+inline Register as_Register() { -+ assert( is_Register(), "must be"); -+ return ::as_Register(value() / RegisterImpl::max_slots_per_register); -+} -+ -+inline bool is_FloatRegister() { -+ return value() >= ConcreteRegisterImpl::max_gpr && value() < ConcreteRegisterImpl::max_fpr; -+} -+ -+inline FloatRegister as_FloatRegister() { -+ assert( is_FloatRegister() && is_even(value()), "must be" ); -+ return ::as_FloatRegister((value() - ConcreteRegisterImpl::max_gpr) / -+ FloatRegisterImpl::max_slots_per_register); -+} -+ -+inline bool is_concrete() { -+ assert(is_reg(), "must be"); -+ if (is_FloatRegister()) { -+ int base = value() - ConcreteRegisterImpl::max_gpr; -+ return base % FloatRegisterImpl::max_slots_per_register == 0; -+ } else { -+ return is_even(value()); -+ } -+} -+ -+#endif // CPU_LOONGARCH_VMREG_LOONGARCH_HPP -diff --git a/src/hotspot/cpu/loongarch/vmreg_loongarch.inline.hpp b/src/hotspot/cpu/loongarch/vmreg_loongarch.inline.hpp -new file mode 100644 -index 00000000000..edb78e36daa ---- /dev/null -+++ b/src/hotspot/cpu/loongarch/vmreg_loongarch.inline.hpp -@@ -0,0 +1,39 @@ -+/* -+ * Copyright (c) 2006, 2012, Oracle and/or its affiliates. All rights reserved. -+ * Copyright (c) 2015, 2022, Loongson Technology. All rights reserved. -+ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. -+ * -+ * This code is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 only, as -+ * published by the Free Software Foundation. -+ * -+ * This code is distributed in the hope that it will be useful, but WITHOUT -+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -+ * version 2 for more details (a copy is included in the LICENSE file that -+ * accompanied this code). -+ * -+ * You should have received a copy of the GNU General Public License version -+ * 2 along with this work; if not, write to the Free Software Foundation, -+ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. -+ * -+ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA -+ * or visit www.oracle.com if you need additional information or have any -+ * questions. -+ * -+ */ -+ -+#ifndef CPU_LOONGARCH_VMREG_LOONGARCH_INLINE_HPP -+#define CPU_LOONGARCH_VMREG_LOONGARCH_INLINE_HPP -+ -+inline VMReg RegisterImpl::as_VMReg() { -+ if( this==noreg ) return VMRegImpl::Bad(); -+ return VMRegImpl::as_VMReg(encoding() * RegisterImpl::max_slots_per_register); -+} -+ -+inline VMReg FloatRegisterImpl::as_VMReg() { -+ return VMRegImpl::as_VMReg((encoding() * FloatRegisterImpl::max_slots_per_register) + -+ ConcreteRegisterImpl::max_gpr); -+} -+ -+#endif // CPU_LOONGARCH_VMREG_LOONGARCH_INLINE_HPP -diff --git a/src/hotspot/cpu/loongarch/vtableStubs_loongarch_64.cpp b/src/hotspot/cpu/loongarch/vtableStubs_loongarch_64.cpp -new file mode 100644 -index 00000000000..6a190529b64 ---- /dev/null -+++ b/src/hotspot/cpu/loongarch/vtableStubs_loongarch_64.cpp +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/loongarch/vtableStubs_loongarch_64.cpp b/src/hotspot/cpu/loongarch/vtableStubs_loongarch_64.cpp +--- a/src/hotspot/cpu/loongarch/vtableStubs_loongarch_64.cpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/loongarch/vtableStubs_loongarch_64.cpp 2024-01-31 14:01:11.604095562 +0800 @@ -0,0 +1,331 @@ +/* + * Copyright (c) 2003, 2014, Oracle and/or its affiliates. All rights reserved. @@ -65055,11 +64478,9 @@ index 00000000000..6a190529b64 + const unsigned int icache_line_size = wordSize; + return icache_line_size; +} -diff --git a/src/hotspot/cpu/mips/abstractInterpreter_mips.cpp b/src/hotspot/cpu/mips/abstractInterpreter_mips.cpp -new file mode 100644 -index 00000000000..c34334ec4c7 ---- /dev/null -+++ b/src/hotspot/cpu/mips/abstractInterpreter_mips.cpp +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/mips/abstractInterpreter_mips.cpp b/src/hotspot/cpu/mips/abstractInterpreter_mips.cpp +--- a/src/hotspot/cpu/mips/abstractInterpreter_mips.cpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/mips/abstractInterpreter_mips.cpp 2024-01-31 14:01:11.604095562 +0800 @@ -0,0 +1,133 @@ +/* + * Copyright (c) 2003, 2013, Oracle and/or its affiliates. All rights reserved. @@ -65194,11 +64615,9 @@ index 00000000000..c34334ec4c7 + *interpreter_frame->interpreter_frame_mirror_addr() = method->method_holder()->java_mirror(); +} + -diff --git a/src/hotspot/cpu/mips/assembler_mips.cpp b/src/hotspot/cpu/mips/assembler_mips.cpp -new file mode 100644 -index 00000000000..2205ef1a42c ---- /dev/null -+++ b/src/hotspot/cpu/mips/assembler_mips.cpp +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/mips/assembler_mips.cpp b/src/hotspot/cpu/mips/assembler_mips.cpp +--- a/src/hotspot/cpu/mips/assembler_mips.cpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/mips/assembler_mips.cpp 2024-01-31 14:01:11.604095562 +0800 @@ -0,0 +1,764 @@ +/* + * Copyright (c) 1997, 2014, Oracle and/or its affiliates. All rights reserved. @@ -65964,11 +65383,9 @@ index 00000000000..2205ef1a42c + delay_state = no_delay; +#endif +} -diff --git a/src/hotspot/cpu/mips/assembler_mips.hpp b/src/hotspot/cpu/mips/assembler_mips.hpp -new file mode 100644 -index 00000000000..8d0d9e0eb21 ---- /dev/null -+++ b/src/hotspot/cpu/mips/assembler_mips.hpp +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/mips/assembler_mips.hpp b/src/hotspot/cpu/mips/assembler_mips.hpp +--- a/src/hotspot/cpu/mips/assembler_mips.hpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/mips/assembler_mips.hpp 2024-01-31 14:01:11.604095562 +0800 @@ -0,0 +1,1777 @@ +/* + * Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved. @@ -67747,11 +67164,9 @@ index 00000000000..8d0d9e0eb21 +}; + +#endif // CPU_MIPS_VM_ASSEMBLER_MIPS_HPP -diff --git a/src/hotspot/cpu/mips/assembler_mips.inline.hpp b/src/hotspot/cpu/mips/assembler_mips.inline.hpp -new file mode 100644 -index 00000000000..39aeb5509a7 ---- /dev/null -+++ b/src/hotspot/cpu/mips/assembler_mips.inline.hpp +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/mips/assembler_mips.inline.hpp b/src/hotspot/cpu/mips/assembler_mips.inline.hpp +--- a/src/hotspot/cpu/mips/assembler_mips.inline.hpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/mips/assembler_mips.inline.hpp 2024-01-31 14:01:11.604095562 +0800 @@ -0,0 +1,33 @@ +/* + * Copyright (c) 1997, 2010, Oracle and/or its affiliates. All rights reserved. @@ -67786,11 +67201,9 @@ index 00000000000..39aeb5509a7 +#include "code/codeCache.hpp" + +#endif // CPU_MIPS_VM_ASSEMBLER_MIPS_INLINE_HPP -diff --git a/src/hotspot/cpu/mips/bytes_mips.hpp b/src/hotspot/cpu/mips/bytes_mips.hpp -new file mode 100644 -index 00000000000..4172db219b1 ---- /dev/null -+++ b/src/hotspot/cpu/mips/bytes_mips.hpp +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/mips/bytes_mips.hpp b/src/hotspot/cpu/mips/bytes_mips.hpp +--- a/src/hotspot/cpu/mips/bytes_mips.hpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/mips/bytes_mips.hpp 2024-01-31 14:01:11.604095562 +0800 @@ -0,0 +1,181 @@ +/* + * Copyright (c) 1997, 2010, Oracle and/or its affiliates. All rights reserved. @@ -67973,11 +67386,142 @@ index 00000000000..4172db219b1 +#include OS_CPU_HEADER_INLINE(bytes) + +#endif // CPU_MIPS_VM_BYTES_MIPS_HPP -diff --git a/src/hotspot/cpu/mips/c2_MacroAssembler_mips.cpp b/src/hotspot/cpu/mips/c2_MacroAssembler_mips.cpp -new file mode 100644 -index 00000000000..3d98ec11f6b ---- /dev/null -+++ b/src/hotspot/cpu/mips/c2_MacroAssembler_mips.cpp +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/mips/c2_globals_mips.hpp b/src/hotspot/cpu/mips/c2_globals_mips.hpp +--- a/src/hotspot/cpu/mips/c2_globals_mips.hpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/mips/c2_globals_mips.hpp 2024-01-31 14:01:11.607428929 +0800 +@@ -0,0 +1,91 @@ ++/* ++ * Copyright (c) 2000, 2013, Oracle and/or its affiliates. All rights reserved. ++ * Copyright (c) 2015, 2022, Loongson Technology. All rights reserved. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ * ++ */ ++ ++#ifndef CPU_MIPS_VM_C2_GLOBALS_MIPS_HPP ++#define CPU_MIPS_VM_C2_GLOBALS_MIPS_HPP ++ ++#include "utilities/globalDefinitions.hpp" ++#include "utilities/macros.hpp" ++ ++// Sets the default values for platform dependent flags used by the server compiler. ++// (see c2_globals.hpp). Alpha-sorted. ++define_pd_global(bool, BackgroundCompilation, true); ++define_pd_global(bool, UseTLAB, true); ++define_pd_global(bool, ResizeTLAB, true); ++define_pd_global(bool, CICompileOSR, true); ++define_pd_global(bool, InlineIntrinsics, true); ++define_pd_global(bool, PreferInterpreterNativeStubs, false); ++define_pd_global(bool, ProfileTraps, true); ++define_pd_global(bool, UseOnStackReplacement, true); ++define_pd_global(bool, ProfileInterpreter, true); ++// Disable C1 in server JIT ++define_pd_global(bool, TieredCompilation, false); ++define_pd_global(intx, CompileThreshold, 10000); ++define_pd_global(intx, BackEdgeThreshold, 100000); ++ ++define_pd_global(intx, OnStackReplacePercentage, 140); ++define_pd_global(intx, ConditionalMoveLimit, 3); ++define_pd_global(intx, FLOATPRESSURE, 31); ++define_pd_global(intx, FreqInlineSize, 325); ++define_pd_global(intx, MinJumpTableSize, 10); ++define_pd_global(intx, INTPRESSURE, 21); ++define_pd_global(intx, InteriorEntryAlignment, 16); ++define_pd_global(intx, NewSizeThreadIncrease, ScaleForWordSize(4*K)); ++define_pd_global(intx, LoopUnrollLimit, 60); ++define_pd_global(intx, LoopPercentProfileLimit, 10); ++// InitialCodeCacheSize derived from specjbb2000 run. ++define_pd_global(intx, InitialCodeCacheSize, 2496*K); // Integral multiple of CodeCacheExpansionSize ++define_pd_global(intx, CodeCacheExpansionSize, 64*K); ++ ++// Ergonomics related flags ++define_pd_global(uint64_t,MaxRAM, 128ULL*G); ++define_pd_global(intx, RegisterCostAreaRatio, 16000); ++ ++// Peephole and CISC spilling both break the graph, and so makes the ++// scheduler sick. ++define_pd_global(bool, OptoPeephole, false); ++define_pd_global(bool, UseCISCSpill, false); ++define_pd_global(bool, OptoScheduling, false); ++define_pd_global(bool, OptoBundling, false); ++define_pd_global(bool, OptoRegScheduling, false); ++define_pd_global(bool, SuperWordLoopUnrollAnalysis, true); ++define_pd_global(bool, IdealizeClearArrayNode, true); ++ ++define_pd_global(intx, ReservedCodeCacheSize, 120*M); ++define_pd_global(intx, NonProfiledCodeHeapSize, 57*M); ++define_pd_global(intx, ProfiledCodeHeapSize, 58*M); ++define_pd_global(intx, NonNMethodCodeHeapSize, 5*M ); ++define_pd_global(uintx, CodeCacheMinBlockLength, 4); ++define_pd_global(uintx, CodeCacheMinimumUseSpace, 400*K); ++ ++define_pd_global(bool, TrapBasedRangeChecks, false); ++ ++// Heap related flags ++define_pd_global(uintx,MetaspaceSize, ScaleForWordSize(16*M)); ++ ++// Ergonomics related flags ++define_pd_global(bool, NeverActAsServerClassMachine, false); ++ ++#endif // CPU_MIPS_VM_C2_GLOBALS_MIPS_HPP +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/mips/c2_init_mips.cpp b/src/hotspot/cpu/mips/c2_init_mips.cpp +--- a/src/hotspot/cpu/mips/c2_init_mips.cpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/mips/c2_init_mips.cpp 2024-01-31 14:01:11.607428929 +0800 +@@ -0,0 +1,34 @@ ++/* ++ * Copyright (c) 2000, 2010, Oracle and/or its affiliates. All rights reserved. ++ * Copyright (c) 2015, 2019, Loongson Technology. All rights reserved. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ * ++ */ ++ ++#include "precompiled.hpp" ++#include "opto/compile.hpp" ++#include "opto/node.hpp" ++ ++// processor dependent initialization for mips ++ ++void Compile::pd_compiler2_init() { ++ guarantee(CodeEntryAlignment >= InteriorEntryAlignment, "" ); ++} +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/mips/c2_MacroAssembler_mips.cpp b/src/hotspot/cpu/mips/c2_MacroAssembler_mips.cpp +--- a/src/hotspot/cpu/mips/c2_MacroAssembler_mips.cpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/mips/c2_MacroAssembler_mips.cpp 2024-01-31 14:01:11.604095562 +0800 @@ -0,0 +1,614 @@ +/* + * Copyright (c) 2020, Oracle and/or its affiliates. All rights reserved. @@ -68593,11 +68137,9 @@ index 00000000000..3d98ec11f6b + ShouldNotReachHere(); + } +} -diff --git a/src/hotspot/cpu/mips/c2_MacroAssembler_mips.hpp b/src/hotspot/cpu/mips/c2_MacroAssembler_mips.hpp -new file mode 100644 -index 00000000000..7bdf6e52126 ---- /dev/null -+++ b/src/hotspot/cpu/mips/c2_MacroAssembler_mips.hpp +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/mips/c2_MacroAssembler_mips.hpp b/src/hotspot/cpu/mips/c2_MacroAssembler_mips.hpp +--- a/src/hotspot/cpu/mips/c2_MacroAssembler_mips.hpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/mips/c2_MacroAssembler_mips.hpp 2024-01-31 14:01:11.607428929 +0800 @@ -0,0 +1,162 @@ +/* + * Copyright (c) 2020, Oracle and/or its affiliates. All rights reserved. @@ -68761,148 +68303,9 @@ index 00000000000..7bdf6e52126 + void gs_loadstore(FloatRegister reg, Register base, Register index, int disp, int type); + +#endif // CPU_MIPS_VM_C2_MACROASSEMBLER_MIPS_HPP -diff --git a/src/hotspot/cpu/mips/c2_globals_mips.hpp b/src/hotspot/cpu/mips/c2_globals_mips.hpp -new file mode 100644 -index 00000000000..f452cebf549 ---- /dev/null -+++ b/src/hotspot/cpu/mips/c2_globals_mips.hpp -@@ -0,0 +1,91 @@ -+/* -+ * Copyright (c) 2000, 2013, Oracle and/or its affiliates. All rights reserved. -+ * Copyright (c) 2015, 2022, Loongson Technology. All rights reserved. -+ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. -+ * -+ * This code is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 only, as -+ * published by the Free Software Foundation. -+ * -+ * This code is distributed in the hope that it will be useful, but WITHOUT -+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -+ * version 2 for more details (a copy is included in the LICENSE file that -+ * accompanied this code). -+ * -+ * You should have received a copy of the GNU General Public License version -+ * 2 along with this work; if not, write to the Free Software Foundation, -+ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. -+ * -+ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA -+ * or visit www.oracle.com if you need additional information or have any -+ * questions. -+ * -+ */ -+ -+#ifndef CPU_MIPS_VM_C2_GLOBALS_MIPS_HPP -+#define CPU_MIPS_VM_C2_GLOBALS_MIPS_HPP -+ -+#include "utilities/globalDefinitions.hpp" -+#include "utilities/macros.hpp" -+ -+// Sets the default values for platform dependent flags used by the server compiler. -+// (see c2_globals.hpp). Alpha-sorted. -+define_pd_global(bool, BackgroundCompilation, true); -+define_pd_global(bool, UseTLAB, true); -+define_pd_global(bool, ResizeTLAB, true); -+define_pd_global(bool, CICompileOSR, true); -+define_pd_global(bool, InlineIntrinsics, true); -+define_pd_global(bool, PreferInterpreterNativeStubs, false); -+define_pd_global(bool, ProfileTraps, true); -+define_pd_global(bool, UseOnStackReplacement, true); -+define_pd_global(bool, ProfileInterpreter, true); -+// Disable C1 in server JIT -+define_pd_global(bool, TieredCompilation, false); -+define_pd_global(intx, CompileThreshold, 10000); -+define_pd_global(intx, BackEdgeThreshold, 100000); -+ -+define_pd_global(intx, OnStackReplacePercentage, 140); -+define_pd_global(intx, ConditionalMoveLimit, 3); -+define_pd_global(intx, FLOATPRESSURE, 31); -+define_pd_global(intx, FreqInlineSize, 325); -+define_pd_global(intx, MinJumpTableSize, 10); -+define_pd_global(intx, INTPRESSURE, 21); -+define_pd_global(intx, InteriorEntryAlignment, 16); -+define_pd_global(intx, NewSizeThreadIncrease, ScaleForWordSize(4*K)); -+define_pd_global(intx, LoopUnrollLimit, 60); -+define_pd_global(intx, LoopPercentProfileLimit, 10); -+// InitialCodeCacheSize derived from specjbb2000 run. -+define_pd_global(intx, InitialCodeCacheSize, 2496*K); // Integral multiple of CodeCacheExpansionSize -+define_pd_global(intx, CodeCacheExpansionSize, 64*K); -+ -+// Ergonomics related flags -+define_pd_global(uint64_t,MaxRAM, 128ULL*G); -+define_pd_global(intx, RegisterCostAreaRatio, 16000); -+ -+// Peephole and CISC spilling both break the graph, and so makes the -+// scheduler sick. -+define_pd_global(bool, OptoPeephole, false); -+define_pd_global(bool, UseCISCSpill, false); -+define_pd_global(bool, OptoScheduling, false); -+define_pd_global(bool, OptoBundling, false); -+define_pd_global(bool, OptoRegScheduling, false); -+define_pd_global(bool, SuperWordLoopUnrollAnalysis, true); -+define_pd_global(bool, IdealizeClearArrayNode, true); -+ -+define_pd_global(intx, ReservedCodeCacheSize, 120*M); -+define_pd_global(intx, NonProfiledCodeHeapSize, 57*M); -+define_pd_global(intx, ProfiledCodeHeapSize, 58*M); -+define_pd_global(intx, NonNMethodCodeHeapSize, 5*M ); -+define_pd_global(uintx, CodeCacheMinBlockLength, 4); -+define_pd_global(uintx, CodeCacheMinimumUseSpace, 400*K); -+ -+define_pd_global(bool, TrapBasedRangeChecks, false); -+ -+// Heap related flags -+define_pd_global(uintx,MetaspaceSize, ScaleForWordSize(16*M)); -+ -+// Ergonomics related flags -+define_pd_global(bool, NeverActAsServerClassMachine, false); -+ -+#endif // CPU_MIPS_VM_C2_GLOBALS_MIPS_HPP -diff --git a/src/hotspot/cpu/mips/c2_init_mips.cpp b/src/hotspot/cpu/mips/c2_init_mips.cpp -new file mode 100644 -index 00000000000..e6d5815f424 ---- /dev/null -+++ b/src/hotspot/cpu/mips/c2_init_mips.cpp -@@ -0,0 +1,34 @@ -+/* -+ * Copyright (c) 2000, 2010, Oracle and/or its affiliates. All rights reserved. -+ * Copyright (c) 2015, 2019, Loongson Technology. All rights reserved. -+ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. -+ * -+ * This code is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 only, as -+ * published by the Free Software Foundation. -+ * -+ * This code is distributed in the hope that it will be useful, but WITHOUT -+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -+ * version 2 for more details (a copy is included in the LICENSE file that -+ * accompanied this code). -+ * -+ * You should have received a copy of the GNU General Public License version -+ * 2 along with this work; if not, write to the Free Software Foundation, -+ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. -+ * -+ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA -+ * or visit www.oracle.com if you need additional information or have any -+ * questions. -+ * -+ */ -+ -+#include "precompiled.hpp" -+#include "opto/compile.hpp" -+#include "opto/node.hpp" -+ -+// processor dependent initialization for mips -+ -+void Compile::pd_compiler2_init() { -+ guarantee(CodeEntryAlignment >= InteriorEntryAlignment, "" ); -+} -diff --git a/src/hotspot/cpu/mips/codeBuffer_mips.hpp b/src/hotspot/cpu/mips/codeBuffer_mips.hpp -new file mode 100644 -index 00000000000..3cc191006d4 ---- /dev/null -+++ b/src/hotspot/cpu/mips/codeBuffer_mips.hpp +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/mips/codeBuffer_mips.hpp b/src/hotspot/cpu/mips/codeBuffer_mips.hpp +--- a/src/hotspot/cpu/mips/codeBuffer_mips.hpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/mips/codeBuffer_mips.hpp 2024-01-31 14:01:11.607428929 +0800 @@ -0,0 +1,35 @@ +/* + * Copyright (c) 2002, 2010, Oracle and/or its affiliates. All rights reserved. @@ -68939,11 +68342,9 @@ index 00000000000..3cc191006d4 + void flush_bundle(bool start_new_bundle) {} + +#endif // CPU_MIPS_VM_CODEBUFFER_MIPS_HPP -diff --git a/src/hotspot/cpu/mips/compiledIC_mips.cpp b/src/hotspot/cpu/mips/compiledIC_mips.cpp -new file mode 100644 -index 00000000000..81f67a92a78 ---- /dev/null -+++ b/src/hotspot/cpu/mips/compiledIC_mips.cpp +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/mips/compiledIC_mips.cpp b/src/hotspot/cpu/mips/compiledIC_mips.cpp +--- a/src/hotspot/cpu/mips/compiledIC_mips.cpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/mips/compiledIC_mips.cpp 2024-01-31 14:01:11.607428929 +0800 @@ -0,0 +1,147 @@ +/* + * Copyright (c) 1997, 2014, Oracle and/or its affiliates. All rights reserved. @@ -69092,11 +68493,9 @@ index 00000000000..81f67a92a78 +} + +#endif // !PRODUCT -diff --git a/src/hotspot/cpu/mips/copy_mips.hpp b/src/hotspot/cpu/mips/copy_mips.hpp -new file mode 100644 -index 00000000000..dcc77adfec1 ---- /dev/null -+++ b/src/hotspot/cpu/mips/copy_mips.hpp +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/mips/copy_mips.hpp b/src/hotspot/cpu/mips/copy_mips.hpp +--- a/src/hotspot/cpu/mips/copy_mips.hpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/mips/copy_mips.hpp 2024-01-31 14:01:11.607428929 +0800 @@ -0,0 +1,77 @@ +/* + * Copyright (c) 2003, 2010, Oracle and/or its affiliates. All rights reserved. @@ -69175,11 +68574,9 @@ index 00000000000..dcc77adfec1 +} + +#endif //CPU_MIPS_VM_COPY_MIPS_HPP -diff --git a/src/hotspot/cpu/mips/depChecker_mips.cpp b/src/hotspot/cpu/mips/depChecker_mips.cpp -new file mode 100644 -index 00000000000..756ccb68f9c ---- /dev/null -+++ b/src/hotspot/cpu/mips/depChecker_mips.cpp +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/mips/depChecker_mips.cpp b/src/hotspot/cpu/mips/depChecker_mips.cpp +--- a/src/hotspot/cpu/mips/depChecker_mips.cpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/mips/depChecker_mips.cpp 2024-01-31 14:01:11.607428929 +0800 @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2002, 2010, Oracle and/or its affiliates. All rights reserved. @@ -69211,11 +68608,9 @@ index 00000000000..756ccb68f9c +#include "depChecker_mips.hpp" + +// Nothing to do on mips -diff --git a/src/hotspot/cpu/mips/depChecker_mips.hpp b/src/hotspot/cpu/mips/depChecker_mips.hpp -new file mode 100644 -index 00000000000..11e52b4e8f8 ---- /dev/null -+++ b/src/hotspot/cpu/mips/depChecker_mips.hpp +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/mips/depChecker_mips.hpp b/src/hotspot/cpu/mips/depChecker_mips.hpp +--- a/src/hotspot/cpu/mips/depChecker_mips.hpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/mips/depChecker_mips.hpp 2024-01-31 14:01:11.607428929 +0800 @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2002, 2010, Oracle and/or its affiliates. All rights reserved. @@ -69248,11 +68643,9 @@ index 00000000000..11e52b4e8f8 +// Nothing to do on MIPS + +#endif // CPU_MIPS_VM_DEPCHECKER_MIPS_HPP -diff --git a/src/hotspot/cpu/mips/disassembler_mips.hpp b/src/hotspot/cpu/mips/disassembler_mips.hpp -new file mode 100644 -index 00000000000..1ca0053b923 ---- /dev/null -+++ b/src/hotspot/cpu/mips/disassembler_mips.hpp +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/mips/disassembler_mips.hpp b/src/hotspot/cpu/mips/disassembler_mips.hpp +--- a/src/hotspot/cpu/mips/disassembler_mips.hpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/mips/disassembler_mips.hpp 2024-01-31 14:01:11.607428929 +0800 @@ -0,0 +1,57 @@ +/* + * Copyright (c) 1997, 2010, Oracle and/or its affiliates. All rights reserved. @@ -69311,11 +68704,9 @@ index 00000000000..1ca0053b923 + static void annotate(address pc, outputStream* st) { }; + +#endif // CPU_MIPS_VM_DISASSEMBLER_MIPS_HPP -diff --git a/src/hotspot/cpu/mips/foreign_globals_mips.cpp b/src/hotspot/cpu/mips/foreign_globals_mips.cpp -new file mode 100644 -index 00000000000..fb4647c2723 ---- /dev/null -+++ b/src/hotspot/cpu/mips/foreign_globals_mips.cpp +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/mips/foreign_globals_mips.cpp b/src/hotspot/cpu/mips/foreign_globals_mips.cpp +--- a/src/hotspot/cpu/mips/foreign_globals_mips.cpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/mips/foreign_globals_mips.cpp 2024-01-31 14:01:11.607428929 +0800 @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2020, Red Hat, Inc. All rights reserved. @@ -69359,11 +68750,9 @@ index 00000000000..fb4647c2723 + ShouldNotCallThis(); + return {}; +} -diff --git a/src/hotspot/cpu/mips/foreign_globals_mips.hpp b/src/hotspot/cpu/mips/foreign_globals_mips.hpp -new file mode 100644 -index 00000000000..3c00688168a ---- /dev/null -+++ b/src/hotspot/cpu/mips/foreign_globals_mips.hpp +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/mips/foreign_globals_mips.hpp b/src/hotspot/cpu/mips/foreign_globals_mips.hpp +--- a/src/hotspot/cpu/mips/foreign_globals_mips.hpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/mips/foreign_globals_mips.hpp 2024-01-31 14:01:11.607428929 +0800 @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2020, Red Hat, Inc. All rights reserved. @@ -69396,11 +68785,9 @@ index 00000000000..3c00688168a +class ABIDescriptor {}; + +#endif // CPU_MIPS_VM_FOREIGN_GLOBALS_MIPS_HPP -diff --git a/src/hotspot/cpu/mips/frame_mips.cpp b/src/hotspot/cpu/mips/frame_mips.cpp -new file mode 100644 -index 00000000000..bf2b87b24cc ---- /dev/null -+++ b/src/hotspot/cpu/mips/frame_mips.cpp +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/mips/frame_mips.cpp b/src/hotspot/cpu/mips/frame_mips.cpp +--- a/src/hotspot/cpu/mips/frame_mips.cpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/mips/frame_mips.cpp 2024-01-31 14:01:11.607428929 +0800 @@ -0,0 +1,665 @@ +/* + * Copyright (c) 1997, 2014, Oracle and/or its affiliates. All rights reserved. @@ -70067,11 +69454,9 @@ index 00000000000..bf2b87b24cc + +void frame::pd_ps() {} +#endif -diff --git a/src/hotspot/cpu/mips/frame_mips.hpp b/src/hotspot/cpu/mips/frame_mips.hpp -new file mode 100644 -index 00000000000..ac706e71f9a ---- /dev/null -+++ b/src/hotspot/cpu/mips/frame_mips.hpp +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/mips/frame_mips.hpp b/src/hotspot/cpu/mips/frame_mips.hpp +--- a/src/hotspot/cpu/mips/frame_mips.hpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/mips/frame_mips.hpp 2024-01-31 14:01:11.607428929 +0800 @@ -0,0 +1,215 @@ +/* + * Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved. @@ -70288,11 +69673,9 @@ index 00000000000..ac706e71f9a + static jint interpreter_frame_expression_stack_direction() { return -1; } + +#endif // CPU_MIPS_VM_FRAME_MIPS_HPP -diff --git a/src/hotspot/cpu/mips/frame_mips.inline.hpp b/src/hotspot/cpu/mips/frame_mips.inline.hpp -new file mode 100644 -index 00000000000..c408f01d69a ---- /dev/null -+++ b/src/hotspot/cpu/mips/frame_mips.inline.hpp +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/mips/frame_mips.inline.hpp b/src/hotspot/cpu/mips/frame_mips.inline.hpp +--- a/src/hotspot/cpu/mips/frame_mips.inline.hpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/mips/frame_mips.inline.hpp 2024-01-31 14:01:11.607428929 +0800 @@ -0,0 +1,238 @@ +/* + * Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved. @@ -70532,11 +69915,9 @@ index 00000000000..c408f01d69a +} + +#endif // CPU_MIPS_VM_FRAME_MIPS_INLINE_HPP -diff --git a/src/hotspot/cpu/mips/gc/g1/g1BarrierSetAssembler_mips.cpp b/src/hotspot/cpu/mips/gc/g1/g1BarrierSetAssembler_mips.cpp -new file mode 100644 -index 00000000000..196ff1582a1 ---- /dev/null -+++ b/src/hotspot/cpu/mips/gc/g1/g1BarrierSetAssembler_mips.cpp +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/mips/gc/g1/g1BarrierSetAssembler_mips.cpp b/src/hotspot/cpu/mips/gc/g1/g1BarrierSetAssembler_mips.cpp +--- a/src/hotspot/cpu/mips/gc/g1/g1BarrierSetAssembler_mips.cpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/mips/gc/g1/g1BarrierSetAssembler_mips.cpp 2024-01-31 14:01:11.607428929 +0800 @@ -0,0 +1,373 @@ +/* + * Copyright (c) 2018, Oracle and/or its affiliates. All rights reserved. @@ -70911,11 +70292,9 @@ index 00000000000..196ff1582a1 + } + } +} -diff --git a/src/hotspot/cpu/mips/gc/g1/g1BarrierSetAssembler_mips.hpp b/src/hotspot/cpu/mips/gc/g1/g1BarrierSetAssembler_mips.hpp -new file mode 100644 -index 00000000000..ec5c243c3f1 ---- /dev/null -+++ b/src/hotspot/cpu/mips/gc/g1/g1BarrierSetAssembler_mips.hpp +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/mips/gc/g1/g1BarrierSetAssembler_mips.hpp b/src/hotspot/cpu/mips/gc/g1/g1BarrierSetAssembler_mips.hpp +--- a/src/hotspot/cpu/mips/gc/g1/g1BarrierSetAssembler_mips.hpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/mips/gc/g1/g1BarrierSetAssembler_mips.hpp 2024-01-31 14:01:11.607428929 +0800 @@ -0,0 +1,71 @@ +/* + * Copyright (c) 2018, Oracle and/or its affiliates. All rights reserved. @@ -70988,11 +70367,9 @@ index 00000000000..ec5c243c3f1 +}; + +#endif // CPU_MIPS_GC_G1_G1BARRIERSETASSEMBLER_MIPS_HPP -diff --git a/src/hotspot/cpu/mips/gc/g1/g1Globals_mips.hpp b/src/hotspot/cpu/mips/gc/g1/g1Globals_mips.hpp -new file mode 100644 -index 00000000000..f0c7badaac7 ---- /dev/null -+++ b/src/hotspot/cpu/mips/gc/g1/g1Globals_mips.hpp +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/mips/gc/g1/g1Globals_mips.hpp b/src/hotspot/cpu/mips/gc/g1/g1Globals_mips.hpp +--- a/src/hotspot/cpu/mips/gc/g1/g1Globals_mips.hpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/mips/gc/g1/g1Globals_mips.hpp 2024-01-31 14:01:11.607428929 +0800 @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2021, Oracle and/or its affiliates. All rights reserved. @@ -71024,11 +70401,9 @@ index 00000000000..f0c7badaac7 +const size_t G1MergeHeapRootsPrefetchCacheSize = 8; + +#endif // CPU_MIPS_GC_G1_G1GLOBALS_MIPS_HPP -diff --git a/src/hotspot/cpu/mips/gc/shared/barrierSetAssembler_mips.cpp b/src/hotspot/cpu/mips/gc/shared/barrierSetAssembler_mips.cpp -new file mode 100644 -index 00000000000..071debdc3a3 ---- /dev/null -+++ b/src/hotspot/cpu/mips/gc/shared/barrierSetAssembler_mips.cpp +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/mips/gc/shared/barrierSetAssembler_mips.cpp b/src/hotspot/cpu/mips/gc/shared/barrierSetAssembler_mips.cpp +--- a/src/hotspot/cpu/mips/gc/shared/barrierSetAssembler_mips.cpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/mips/gc/shared/barrierSetAssembler_mips.cpp 2024-01-31 14:01:11.607428929 +0800 @@ -0,0 +1,194 @@ +/* + * Copyright (c) 2018, Oracle and/or its affiliates. All rights reserved. @@ -71224,11 +70599,9 @@ index 00000000000..071debdc3a3 + Register t1) { + Unimplemented(); +} -diff --git a/src/hotspot/cpu/mips/gc/shared/barrierSetAssembler_mips.hpp b/src/hotspot/cpu/mips/gc/shared/barrierSetAssembler_mips.hpp -new file mode 100644 -index 00000000000..bc68de604d2 ---- /dev/null -+++ b/src/hotspot/cpu/mips/gc/shared/barrierSetAssembler_mips.hpp +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/mips/gc/shared/barrierSetAssembler_mips.hpp b/src/hotspot/cpu/mips/gc/shared/barrierSetAssembler_mips.hpp +--- a/src/hotspot/cpu/mips/gc/shared/barrierSetAssembler_mips.hpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/mips/gc/shared/barrierSetAssembler_mips.hpp 2024-01-31 14:01:11.607428929 +0800 @@ -0,0 +1,84 @@ +/* + * Copyright (c) 2018, Oracle and/or its affiliates. All rights reserved. @@ -71314,11 +70687,9 @@ index 00000000000..bc68de604d2 +}; + +#endif // CPU_MIPS_GC_SHARED_BARRIERSETASSEMBLER_MIPS_HPP -diff --git a/src/hotspot/cpu/mips/gc/shared/barrierSetNMethod_mips.cpp b/src/hotspot/cpu/mips/gc/shared/barrierSetNMethod_mips.cpp -new file mode 100644 -index 00000000000..3d4e69333b0 ---- /dev/null -+++ b/src/hotspot/cpu/mips/gc/shared/barrierSetNMethod_mips.cpp +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/mips/gc/shared/barrierSetNMethod_mips.cpp b/src/hotspot/cpu/mips/gc/shared/barrierSetNMethod_mips.cpp +--- a/src/hotspot/cpu/mips/gc/shared/barrierSetNMethod_mips.cpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/mips/gc/shared/barrierSetNMethod_mips.cpp 2024-01-31 14:01:11.607428929 +0800 @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2018, Oracle and/or its affiliates. All rights reserved. @@ -71361,11 +70732,9 @@ index 00000000000..3d4e69333b0 + ShouldNotReachHere(); + return false; +} -diff --git a/src/hotspot/cpu/mips/gc/shared/cardTableBarrierSetAssembler_mips.cpp b/src/hotspot/cpu/mips/gc/shared/cardTableBarrierSetAssembler_mips.cpp -new file mode 100644 -index 00000000000..1b2002fd040 ---- /dev/null -+++ b/src/hotspot/cpu/mips/gc/shared/cardTableBarrierSetAssembler_mips.cpp +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/mips/gc/shared/cardTableBarrierSetAssembler_mips.cpp b/src/hotspot/cpu/mips/gc/shared/cardTableBarrierSetAssembler_mips.cpp +--- a/src/hotspot/cpu/mips/gc/shared/cardTableBarrierSetAssembler_mips.cpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/mips/gc/shared/cardTableBarrierSetAssembler_mips.cpp 2024-01-31 14:01:11.607428929 +0800 @@ -0,0 +1,144 @@ +/* + * Copyright (c) 2018, Oracle and/or its affiliates. All rights reserved. @@ -71511,11 +70880,9 @@ index 00000000000..1b2002fd040 + } + } +} -diff --git a/src/hotspot/cpu/mips/gc/shared/cardTableBarrierSetAssembler_mips.hpp b/src/hotspot/cpu/mips/gc/shared/cardTableBarrierSetAssembler_mips.hpp -new file mode 100644 -index 00000000000..49c2a0ea80e ---- /dev/null -+++ b/src/hotspot/cpu/mips/gc/shared/cardTableBarrierSetAssembler_mips.hpp +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/mips/gc/shared/cardTableBarrierSetAssembler_mips.hpp b/src/hotspot/cpu/mips/gc/shared/cardTableBarrierSetAssembler_mips.hpp +--- a/src/hotspot/cpu/mips/gc/shared/cardTableBarrierSetAssembler_mips.hpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/mips/gc/shared/cardTableBarrierSetAssembler_mips.hpp 2024-01-31 14:01:11.607428929 +0800 @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2018, Oracle and/or its affiliates. All rights reserved. @@ -71559,11 +70926,9 @@ index 00000000000..49c2a0ea80e +}; + +#endif // CPU_MIPS_GC_SHARED_CARDTABLEBARRIERSETASSEMBLER_MIPS_HPP -diff --git a/src/hotspot/cpu/mips/gc/shared/modRefBarrierSetAssembler_mips.cpp b/src/hotspot/cpu/mips/gc/shared/modRefBarrierSetAssembler_mips.cpp -new file mode 100644 -index 00000000000..765259e6266 ---- /dev/null -+++ b/src/hotspot/cpu/mips/gc/shared/modRefBarrierSetAssembler_mips.cpp +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/mips/gc/shared/modRefBarrierSetAssembler_mips.cpp b/src/hotspot/cpu/mips/gc/shared/modRefBarrierSetAssembler_mips.cpp +--- a/src/hotspot/cpu/mips/gc/shared/modRefBarrierSetAssembler_mips.cpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/mips/gc/shared/modRefBarrierSetAssembler_mips.cpp 2024-01-31 14:01:11.607428929 +0800 @@ -0,0 +1,53 @@ +/* + * Copyright (c) 2018, Oracle and/or its affiliates. All rights reserved. @@ -71618,11 +70983,9 @@ index 00000000000..765259e6266 + BarrierSetAssembler::store_at(masm, decorators, type, dst, val, tmp1, tmp2); + } +} -diff --git a/src/hotspot/cpu/mips/gc/shared/modRefBarrierSetAssembler_mips.hpp b/src/hotspot/cpu/mips/gc/shared/modRefBarrierSetAssembler_mips.hpp -new file mode 100644 -index 00000000000..5320a4c0add ---- /dev/null -+++ b/src/hotspot/cpu/mips/gc/shared/modRefBarrierSetAssembler_mips.hpp +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/mips/gc/shared/modRefBarrierSetAssembler_mips.hpp b/src/hotspot/cpu/mips/gc/shared/modRefBarrierSetAssembler_mips.hpp +--- a/src/hotspot/cpu/mips/gc/shared/modRefBarrierSetAssembler_mips.hpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/mips/gc/shared/modRefBarrierSetAssembler_mips.hpp 2024-01-31 14:01:11.607428929 +0800 @@ -0,0 +1,54 @@ +/* + * Copyright (c) 2018, Oracle and/or its affiliates. All rights reserved. @@ -71678,11 +71041,9 @@ index 00000000000..5320a4c0add +}; + +#endif // CPU_MIPS_GC_SHARED_MODREFBARRIERSETASSEMBLER_MIPS_HPP -diff --git a/src/hotspot/cpu/mips/globalDefinitions_mips.hpp b/src/hotspot/cpu/mips/globalDefinitions_mips.hpp -new file mode 100644 -index 00000000000..2b50d15ffd7 ---- /dev/null -+++ b/src/hotspot/cpu/mips/globalDefinitions_mips.hpp +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/mips/globalDefinitions_mips.hpp b/src/hotspot/cpu/mips/globalDefinitions_mips.hpp +--- a/src/hotspot/cpu/mips/globalDefinitions_mips.hpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/mips/globalDefinitions_mips.hpp 2024-01-31 14:01:11.607428929 +0800 @@ -0,0 +1,47 @@ +/* + * Copyright (c) 1999, 2013, Oracle and/or its affiliates. All rights reserved. @@ -71731,11 +71092,9 @@ index 00000000000..2b50d15ffd7 +#define COMPRESSED_CLASS_POINTERS_DEPENDS_ON_COMPRESSED_OOPS false + +#endif // CPU_MIPS_VM_GLOBALDEFINITIONS_MIPS_HPP -diff --git a/src/hotspot/cpu/mips/globals_mips.hpp b/src/hotspot/cpu/mips/globals_mips.hpp -new file mode 100644 -index 00000000000..2d88d370c94 ---- /dev/null -+++ b/src/hotspot/cpu/mips/globals_mips.hpp +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/mips/globals_mips.hpp b/src/hotspot/cpu/mips/globals_mips.hpp +--- a/src/hotspot/cpu/mips/globals_mips.hpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/mips/globals_mips.hpp 2024-01-31 14:01:11.607428929 +0800 @@ -0,0 +1,132 @@ +/* + * Copyright (c) 2000, 2013, Oracle and/or its affiliates. All rights reserved. @@ -71869,11 +71228,99 @@ index 00000000000..2d88d370c94 +// end of ARCH_FLAGS + +#endif // CPU_MIPS_VM_GLOBALS_MIPS_HPP -diff --git a/src/hotspot/cpu/mips/icBuffer_mips.cpp b/src/hotspot/cpu/mips/icBuffer_mips.cpp -new file mode 100644 -index 00000000000..604e951a9bf ---- /dev/null -+++ b/src/hotspot/cpu/mips/icBuffer_mips.cpp +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/mips/icache_mips.cpp b/src/hotspot/cpu/mips/icache_mips.cpp +--- a/src/hotspot/cpu/mips/icache_mips.cpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/mips/icache_mips.cpp 2024-01-31 14:01:11.607428929 +0800 +@@ -0,0 +1,41 @@ ++/* ++ * Copyright (c) 1997, 2010, Oracle and/or its affiliates. All rights reserved. ++ * Copyright (c) 2015, 2021, Loongson Technology. All rights reserved. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ * ++ */ ++ ++#include "precompiled.hpp" ++#include "asm/macroAssembler.hpp" ++#include "runtime/icache.hpp" ++ ++void ICacheStubGenerator::generate_icache_flush(ICache::flush_icache_stub_t* flush_icache_stub) ++{ ++#define __ _masm-> ++ StubCodeMark mark(this, "ICache", "flush_icache_stub"); ++ address start = __ pc(); ++ ++ __ jr_hb(RA); ++ __ delayed()->ori(V0, RA2, 0); ++ ++ *flush_icache_stub = (ICache::flush_icache_stub_t)start; ++#undef __ ++} +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/mips/icache_mips.hpp b/src/hotspot/cpu/mips/icache_mips.hpp +--- a/src/hotspot/cpu/mips/icache_mips.hpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/mips/icache_mips.hpp 2024-01-31 14:01:11.607428929 +0800 +@@ -0,0 +1,41 @@ ++/* ++ * Copyright (c) 1997, 2010, Oracle and/or its affiliates. All rights reserved. ++ * Copyright (c) 2015, 2021, Loongson Technology. All rights reserved. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ * ++ */ ++ ++#ifndef CPU_MIPS_VM_ICACHE_MIPS_HPP ++#define CPU_MIPS_VM_ICACHE_MIPS_HPP ++ ++// Interface for updating the instruction cache. Whenever the VM modifies ++// code, part of the processor instruction cache potentially has to be flushed. ++ ++class ICache : public AbstractICache { ++ public: ++ enum { ++ stub_size = 2 * BytesPerInstWord, // Size of the icache flush stub in bytes ++ line_size = 32, // flush instruction affects a dword ++ log2_line_size = 5 // log2(line_size) ++ }; ++}; ++ ++#endif // CPU_MIPS_VM_ICACHE_MIPS_HPP +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/mips/icBuffer_mips.cpp b/src/hotspot/cpu/mips/icBuffer_mips.cpp +--- a/src/hotspot/cpu/mips/icBuffer_mips.cpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/mips/icBuffer_mips.cpp 2024-01-31 14:01:11.607428929 +0800 @@ -0,0 +1,96 @@ +/* + * Copyright (c) 1997, 2012, Oracle and/or its affiliates. All rights reserved. @@ -71971,381 +71418,13 @@ index 00000000000..604e951a9bf + void* o= (void*)move->data(); + return o; +} -diff --git a/src/hotspot/cpu/mips/icache_mips.cpp b/src/hotspot/cpu/mips/icache_mips.cpp -new file mode 100644 -index 00000000000..848964b63f6 ---- /dev/null -+++ b/src/hotspot/cpu/mips/icache_mips.cpp -@@ -0,0 +1,41 @@ -+/* -+ * Copyright (c) 1997, 2010, Oracle and/or its affiliates. All rights reserved. -+ * Copyright (c) 2015, 2021, Loongson Technology. All rights reserved. -+ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. -+ * -+ * This code is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 only, as -+ * published by the Free Software Foundation. -+ * -+ * This code is distributed in the hope that it will be useful, but WITHOUT -+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -+ * version 2 for more details (a copy is included in the LICENSE file that -+ * accompanied this code). -+ * -+ * You should have received a copy of the GNU General Public License version -+ * 2 along with this work; if not, write to the Free Software Foundation, -+ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. -+ * -+ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA -+ * or visit www.oracle.com if you need additional information or have any -+ * questions. -+ * -+ */ -+ -+#include "precompiled.hpp" -+#include "asm/macroAssembler.hpp" -+#include "runtime/icache.hpp" -+ -+void ICacheStubGenerator::generate_icache_flush(ICache::flush_icache_stub_t* flush_icache_stub) -+{ -+#define __ _masm-> -+ StubCodeMark mark(this, "ICache", "flush_icache_stub"); -+ address start = __ pc(); -+ -+ __ jr_hb(RA); -+ __ delayed()->ori(V0, RA2, 0); -+ -+ *flush_icache_stub = (ICache::flush_icache_stub_t)start; -+#undef __ -+} -diff --git a/src/hotspot/cpu/mips/icache_mips.hpp b/src/hotspot/cpu/mips/icache_mips.hpp -new file mode 100644 -index 00000000000..f90dee6eef7 ---- /dev/null -+++ b/src/hotspot/cpu/mips/icache_mips.hpp -@@ -0,0 +1,41 @@ -+/* -+ * Copyright (c) 1997, 2010, Oracle and/or its affiliates. All rights reserved. -+ * Copyright (c) 2015, 2021, Loongson Technology. All rights reserved. -+ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. -+ * -+ * This code is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 only, as -+ * published by the Free Software Foundation. -+ * -+ * This code is distributed in the hope that it will be useful, but WITHOUT -+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -+ * version 2 for more details (a copy is included in the LICENSE file that -+ * accompanied this code). -+ * -+ * You should have received a copy of the GNU General Public License version -+ * 2 along with this work; if not, write to the Free Software Foundation, -+ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. -+ * -+ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA -+ * or visit www.oracle.com if you need additional information or have any -+ * questions. -+ * -+ */ -+ -+#ifndef CPU_MIPS_VM_ICACHE_MIPS_HPP -+#define CPU_MIPS_VM_ICACHE_MIPS_HPP -+ -+// Interface for updating the instruction cache. Whenever the VM modifies -+// code, part of the processor instruction cache potentially has to be flushed. -+ -+class ICache : public AbstractICache { -+ public: -+ enum { -+ stub_size = 2 * BytesPerInstWord, // Size of the icache flush stub in bytes -+ line_size = 32, // flush instruction affects a dword -+ log2_line_size = 5 // log2(line_size) -+ }; -+}; -+ -+#endif // CPU_MIPS_VM_ICACHE_MIPS_HPP -diff --git a/src/hotspot/cpu/mips/interp_masm_mips.hpp b/src/hotspot/cpu/mips/interp_masm_mips.hpp -new file mode 100644 -index 00000000000..1b9aa653fd4 ---- /dev/null -+++ b/src/hotspot/cpu/mips/interp_masm_mips.hpp -@@ -0,0 +1,266 @@ +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/mips/interp_masm_mips_64.cpp b/src/hotspot/cpu/mips/interp_masm_mips_64.cpp +--- a/src/hotspot/cpu/mips/interp_masm_mips_64.cpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/mips/interp_masm_mips_64.cpp 2024-01-31 14:01:11.607428929 +0800 +@@ -0,0 +1,2140 @@ +/* + * Copyright (c) 2003, 2013, Oracle and/or its affiliates. All rights reserved. -+ * Copyright (c) 2015, 2021, Loongson Technology. All rights reserved. -+ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. -+ * -+ * This code is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 only, as -+ * published by the Free Software Foundation. -+ * -+ * This code is distributed in the hope that it will be useful, but WITHOUT -+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -+ * version 2 for more details (a copy is included in the LICENSE file that -+ * accompanied this code). -+ * -+ * You should have received a copy of the GNU General Public License version -+ * 2 along with this work; if not, write to the Free Software Foundation, -+ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. -+ * -+ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA -+ * or visit www.oracle.com if you need additional information or have any -+ * questions. -+ * -+ */ -+ -+#ifndef CPU_MIPS_VM_INTERP_MASM_MIPS_64_HPP -+#define CPU_MIPS_VM_INTERP_MASM_MIPS_64_HPP -+ -+#include "asm/assembler.hpp" -+#include "asm/macroAssembler.hpp" -+#include "asm/macroAssembler.inline.hpp" -+#include "interpreter/invocationCounter.hpp" -+#include "runtime/frame.hpp" -+ -+// This file specializes the assember with interpreter-specific macros -+ -+ -+class InterpreterMacroAssembler: public MacroAssembler { -+ private: -+ -+ Register _locals_register; // register that contains the pointer to the locals -+ Register _bcp_register; // register that contains the bcp -+ -+ protected: -+ // Interpreter specific version of call_VM_base -+ virtual void call_VM_leaf_base(address entry_point, -+ int number_of_arguments); -+ -+ virtual void call_VM_base(Register oop_result, -+ Register java_thread, -+ Register last_java_sp, -+ address entry_point, -+ int number_of_arguments, -+ bool check_exceptions); -+ -+ // base routine for all dispatches -+ void dispatch_base(TosState state, address* table, bool verifyoop = true, bool generate_poll = false); -+ -+ public: -+ void jump_to_entry(address entry); -+ // narrow int return value -+ void narrow(Register result); -+ -+ InterpreterMacroAssembler(CodeBuffer* code) : MacroAssembler(code), _locals_register(LVP), _bcp_register(BCP) {} -+ -+ void get_2_byte_integer_at_bcp(Register reg, Register tmp, int offset); -+ void get_4_byte_integer_at_bcp(Register reg, Register tmp, int offset); -+ -+ virtual void check_and_handle_popframe(Register java_thread); -+ virtual void check_and_handle_earlyret(Register java_thread); -+ -+ void load_earlyret_value(TosState state); -+ -+ // Interpreter-specific registers -+ void save_bcp() { -+ sd(BCP, FP, frame::interpreter_frame_bcp_offset * wordSize); -+ } -+ -+ void restore_bcp() { -+ ld(BCP, FP, frame::interpreter_frame_bcp_offset * wordSize); -+ } -+ -+ void restore_locals() { -+ ld(LVP, FP, frame::interpreter_frame_locals_offset * wordSize); -+ } -+ -+ // Helpers for runtime call arguments/results -+ void get_method(Register reg) { -+ ld(reg, FP, frame::interpreter_frame_method_offset * wordSize); -+ } -+ -+ void get_const(Register reg){ -+ get_method(reg); -+ ld(reg, reg, in_bytes(Method::const_offset())); -+ } -+ -+ void get_constant_pool(Register reg) { -+ get_const(reg); -+ ld(reg, reg, in_bytes(ConstMethod::constants_offset())); -+ } -+ -+ void get_constant_pool_cache(Register reg) { -+ get_constant_pool(reg); -+ ld(reg, reg, ConstantPool::cache_offset_in_bytes()); -+ } -+ -+ void get_cpool_and_tags(Register cpool, Register tags) { -+ get_constant_pool(cpool); -+ ld(tags, cpool, ConstantPool::tags_offset_in_bytes()); -+ } -+ -+ void get_unsigned_2_byte_index_at_bcp(Register reg, int bcp_offset); -+ void get_cache_and_index_at_bcp(Register cache, Register index, int bcp_offset, size_t index_size = sizeof(u2)); -+ void get_cache_and_index_and_bytecode_at_bcp(Register cache, Register index, Register bytecode, int byte_no, int bcp_offset, size_t index_size = sizeof(u2)); -+ void get_cache_entry_pointer_at_bcp(Register cache, Register tmp, int bcp_offset, size_t index_size = sizeof(u2)); -+ void get_cache_index_at_bcp(Register index, int bcp_offset, size_t index_size = sizeof(u2)); -+ void get_method_counters(Register method, Register mcs, Label& skip); -+ -+ // load cpool->resolved_references(index); -+ void load_resolved_reference_at_index(Register result, Register index, Register tmp); -+ -+ // load cpool->resolved_klass_at(index) -+ void load_resolved_klass_at_index(Register cpool, // the constant pool (corrupted on return) -+ Register index, // the constant pool index (corrupted on return) -+ Register klass); // contains the Klass on return -+ -+ void load_resolved_method_at_index(int byte_no, -+ Register method, -+ Register cache, -+ Register index); -+ -+ void pop_ptr( Register r = FSR); -+ void pop_i( Register r = FSR); -+ void pop_l( Register r = FSR); -+ void pop_f(FloatRegister r = FSF); -+ void pop_d(FloatRegister r = FSF); -+ -+ void push_ptr( Register r = FSR); -+ void push_i( Register r = FSR); -+ void push_l( Register r = FSR); -+ void push_f(FloatRegister r = FSF); -+ void push_d(FloatRegister r = FSF); -+ -+ void pop(Register r ) { ((MacroAssembler*)this)->pop(r); } -+ -+ void push(Register r ) { ((MacroAssembler*)this)->push(r); } -+ -+ void pop(TosState state); // transition vtos -> state -+ void push(TosState state); // transition state -> vtos -+ -+ void empty_expression_stack() { -+ ld(SP, FP, frame::interpreter_frame_monitor_block_top_offset * wordSize); -+ // NULL last_sp until next java call -+ sd(R0, FP, frame::interpreter_frame_last_sp_offset * wordSize); -+ } -+ -+ // Super call_VM calls - correspond to MacroAssembler::call_VM(_leaf) calls -+ void load_ptr(int n, Register val); -+ void store_ptr(int n, Register val); -+ -+ // Generate a subtype check: branch to ok_is_subtype if sub_klass is -+ // a subtype of super_klass. -+ //void gen_subtype_check( Register sub_klass, Label &ok_is_subtype ); -+ void gen_subtype_check( Register Rsup_klass, Register sub_klass, Label &ok_is_subtype ); -+ -+ // Dispatching -+ void dispatch_prolog(TosState state, int step = 0); -+ void dispatch_epilog(TosState state, int step = 0); -+ void dispatch_only(TosState state, bool generate_poll = false); -+ void dispatch_only_normal(TosState state); -+ void dispatch_only_noverify(TosState state); -+ void dispatch_next(TosState state, int step = 0, bool generate_poll = false); -+ void dispatch_via (TosState state, address* table); -+ -+ // jump to an invoked target -+ void prepare_to_jump_from_interpreted(); -+ void jump_from_interpreted(Register method, Register temp); -+ -+ -+ // Returning from interpreted functions -+ // -+ // Removes the current activation (incl. unlocking of monitors) -+ // and sets up the return address. This code is also used for -+ // exception unwindwing. In that case, we do not want to throw -+ // IllegalMonitorStateExceptions, since that might get us into an -+ // infinite rethrow exception loop. -+ // Additionally this code is used for popFrame and earlyReturn. -+ // In popFrame case we want to skip throwing an exception, -+ // installing an exception, and notifying jvmdi. -+ // In earlyReturn case we only want to skip throwing an exception -+ // and installing an exception. -+ void remove_activation(TosState state, Register ret_addr, -+ bool throw_monitor_exception = true, -+ bool install_monitor_exception = true, -+ bool notify_jvmdi = true); -+ -+ // Object locking -+ void lock_object (Register lock_reg); -+ void unlock_object(Register lock_reg); -+ -+ // Interpreter profiling operations -+ void set_method_data_pointer_for_bcp(); -+ void test_method_data_pointer(Register mdp, Label& zero_continue); -+ void verify_method_data_pointer(); -+ -+ void set_mdp_data_at(Register mdp_in, int constant, Register value); -+ void increment_mdp_data_at(Address data, bool decrement = false); -+ void increment_mdp_data_at(Register mdp_in, int constant, -+ bool decrement = false); -+ void increment_mdp_data_at(Register mdp_in, Register reg, int constant, -+ bool decrement = false); -+ void increment_mask_and_jump(Address counter_addr, -+ int increment, Address mask, -+ Register scratch, bool preloaded, -+ Condition cond, Label* where); -+ void set_mdp_flag_at(Register mdp_in, int flag_constant); -+ void test_mdp_data_at(Register mdp_in, int offset, Register value, -+ Register test_value_out, -+ Label& not_equal_continue); -+ -+ void record_klass_in_profile(Register receiver, Register mdp, -+ Register reg2, bool is_virtual_call); -+ void record_klass_in_profile_helper(Register receiver, Register mdp, -+ Register reg2, int start_row, -+ Label& done, bool is_virtual_call); -+ -+ void update_mdp_by_offset(Register mdp_in, int offset_of_offset); -+ void update_mdp_by_offset(Register mdp_in, Register reg, int offset_of_disp); -+ void update_mdp_by_constant(Register mdp_in, int constant); -+ void update_mdp_for_ret(Register return_bci); -+ -+ void profile_taken_branch(Register mdp, Register bumped_count); -+ void profile_not_taken_branch(Register mdp); -+ void profile_call(Register mdp); -+ void profile_final_call(Register mdp); -+ void profile_virtual_call(Register receiver, Register mdp, -+ Register scratch2, -+ bool receiver_can_be_null = false); -+ void profile_called_method(Register method, Register mdp, Register reg2) NOT_JVMCI_RETURN; -+ void profile_ret(Register return_bci, Register mdp); -+ void profile_null_seen(Register mdp); -+ void profile_typecheck(Register mdp, Register klass, Register scratch); -+ void profile_typecheck_failed(Register mdp); -+ void profile_switch_default(Register mdp); -+ void profile_switch_case(Register index_in_scratch, Register mdp, -+ Register scratch2); -+ -+ // Debugging -+ // only if +VerifyOops && state == atos -+ void verify_oop(Register reg, TosState state = atos); -+ // only if +VerifyFPU && (state == ftos || state == dtos) -+ void verify_FPU(int stack_depth, TosState state = ftos); -+ -+ void profile_obj_type(Register obj, const Address& mdo_addr); -+ void profile_arguments_type(Register mdp, Register callee, Register tmp, bool is_virtual); -+ void profile_return_type(Register mdp, Register ret, Register tmp); -+ void profile_parameters_type(Register mdp, Register tmp1, Register tmp2); -+ -+ typedef enum { NotifyJVMTI, SkipNotifyJVMTI } NotifyMethodExitMode; -+ -+ // support for jvmti/dtrace -+ void notify_method_entry(); -+ void notify_method_exit(TosState state, NotifyMethodExitMode mode); -+}; -+ -+#endif // CPU_MIPS_VM_INTERP_MASM_MIPS_64_HPP -diff --git a/src/hotspot/cpu/mips/interp_masm_mips_64.cpp b/src/hotspot/cpu/mips/interp_masm_mips_64.cpp -new file mode 100644 -index 00000000000..732325fdbd4 ---- /dev/null -+++ b/src/hotspot/cpu/mips/interp_masm_mips_64.cpp -@@ -0,0 +1,2140 @@ -+/* -+ * Copyright (c) 2003, 2013, Oracle and/or its affiliates. All rights reserved. -+ * Copyright (c) 2015, 2022, Loongson Technology. All rights reserved. ++ * Copyright (c) 2015, 2022, Loongson Technology. All rights reserved. + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. + * + * This code is free software; you can redistribute it and/or modify it @@ -74483,15 +73562,13 @@ index 00000000000..732325fdbd4 + unimplemented(); + } +} -diff --git a/src/hotspot/cpu/mips/interpreterRT_mips.hpp b/src/hotspot/cpu/mips/interpreterRT_mips.hpp -new file mode 100644 -index 00000000000..054138ea42b ---- /dev/null -+++ b/src/hotspot/cpu/mips/interpreterRT_mips.hpp -@@ -0,0 +1,60 @@ +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/mips/interp_masm_mips.hpp b/src/hotspot/cpu/mips/interp_masm_mips.hpp +--- a/src/hotspot/cpu/mips/interp_masm_mips.hpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/mips/interp_masm_mips.hpp 2024-01-31 14:01:11.607428929 +0800 +@@ -0,0 +1,266 @@ +/* -+ * Copyright (c) 1998, 2010, Oracle and/or its affiliates. All rights reserved. -+ * Copyright (c) 2015, 2022, Loongson Technology. All rights reserved. ++ * Copyright (c) 2003, 2013, Oracle and/or its affiliates. All rights reserved. ++ * Copyright (c) 2015, 2021, Loongson Technology. All rights reserved. + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. + * + * This code is free software; you can redistribute it and/or modify it @@ -74514,46 +73591,250 @@ index 00000000000..054138ea42b + * + */ + -+#ifndef CPU_MIPS_VM_INTERPRETERRT_MIPS_HPP -+#define CPU_MIPS_VM_INTERPRETERRT_MIPS_HPP ++#ifndef CPU_MIPS_VM_INTERP_MASM_MIPS_64_HPP ++#define CPU_MIPS_VM_INTERP_MASM_MIPS_64_HPP + -+// This is included in the middle of class Interpreter. -+// Do not include files here. ++#include "asm/assembler.hpp" ++#include "asm/macroAssembler.hpp" ++#include "asm/macroAssembler.inline.hpp" ++#include "interpreter/invocationCounter.hpp" ++#include "runtime/frame.hpp" + -+// native method calls ++// This file specializes the assember with interpreter-specific macros + -+class SignatureHandlerGenerator: public NativeSignatureIterator { ++ ++class InterpreterMacroAssembler: public MacroAssembler { + private: -+ MacroAssembler* _masm; + -+ void move(int from_offset, int to_offset); ++ Register _locals_register; // register that contains the pointer to the locals ++ Register _bcp_register; // register that contains the bcp + -+ void box(int from_offset, int to_offset); -+ void pass_int(); -+ void pass_long(); -+ void pass_object(); -+ void pass_float(); -+ void pass_double(); ++ protected: ++ // Interpreter specific version of call_VM_base ++ virtual void call_VM_leaf_base(address entry_point, ++ int number_of_arguments); ++ ++ virtual void call_VM_base(Register oop_result, ++ Register java_thread, ++ Register last_java_sp, ++ address entry_point, ++ int number_of_arguments, ++ bool check_exceptions); ++ ++ // base routine for all dispatches ++ void dispatch_base(TosState state, address* table, bool verifyoop = true, bool generate_poll = false); + + public: -+ // Creation -+ SignatureHandlerGenerator(const methodHandle& method, CodeBuffer* buffer); ++ void jump_to_entry(address entry); ++ // narrow int return value ++ void narrow(Register result); + -+ // Code generation -+ void generate(uint64_t fingerprint); ++ InterpreterMacroAssembler(CodeBuffer* code) : MacroAssembler(code), _locals_register(LVP), _bcp_register(BCP) {} + -+ // Code generation support -+ static Register from(); -+ static Register to(); -+ static Register temp(); ++ void get_2_byte_integer_at_bcp(Register reg, Register tmp, int offset); ++ void get_4_byte_integer_at_bcp(Register reg, Register tmp, int offset); ++ ++ virtual void check_and_handle_popframe(Register java_thread); ++ virtual void check_and_handle_earlyret(Register java_thread); ++ ++ void load_earlyret_value(TosState state); ++ ++ // Interpreter-specific registers ++ void save_bcp() { ++ sd(BCP, FP, frame::interpreter_frame_bcp_offset * wordSize); ++ } ++ ++ void restore_bcp() { ++ ld(BCP, FP, frame::interpreter_frame_bcp_offset * wordSize); ++ } ++ ++ void restore_locals() { ++ ld(LVP, FP, frame::interpreter_frame_locals_offset * wordSize); ++ } ++ ++ // Helpers for runtime call arguments/results ++ void get_method(Register reg) { ++ ld(reg, FP, frame::interpreter_frame_method_offset * wordSize); ++ } ++ ++ void get_const(Register reg){ ++ get_method(reg); ++ ld(reg, reg, in_bytes(Method::const_offset())); ++ } ++ ++ void get_constant_pool(Register reg) { ++ get_const(reg); ++ ld(reg, reg, in_bytes(ConstMethod::constants_offset())); ++ } ++ ++ void get_constant_pool_cache(Register reg) { ++ get_constant_pool(reg); ++ ld(reg, reg, ConstantPool::cache_offset_in_bytes()); ++ } ++ ++ void get_cpool_and_tags(Register cpool, Register tags) { ++ get_constant_pool(cpool); ++ ld(tags, cpool, ConstantPool::tags_offset_in_bytes()); ++ } ++ ++ void get_unsigned_2_byte_index_at_bcp(Register reg, int bcp_offset); ++ void get_cache_and_index_at_bcp(Register cache, Register index, int bcp_offset, size_t index_size = sizeof(u2)); ++ void get_cache_and_index_and_bytecode_at_bcp(Register cache, Register index, Register bytecode, int byte_no, int bcp_offset, size_t index_size = sizeof(u2)); ++ void get_cache_entry_pointer_at_bcp(Register cache, Register tmp, int bcp_offset, size_t index_size = sizeof(u2)); ++ void get_cache_index_at_bcp(Register index, int bcp_offset, size_t index_size = sizeof(u2)); ++ void get_method_counters(Register method, Register mcs, Label& skip); ++ ++ // load cpool->resolved_references(index); ++ void load_resolved_reference_at_index(Register result, Register index, Register tmp); ++ ++ // load cpool->resolved_klass_at(index) ++ void load_resolved_klass_at_index(Register cpool, // the constant pool (corrupted on return) ++ Register index, // the constant pool index (corrupted on return) ++ Register klass); // contains the Klass on return ++ ++ void load_resolved_method_at_index(int byte_no, ++ Register method, ++ Register cache, ++ Register index); ++ ++ void pop_ptr( Register r = FSR); ++ void pop_i( Register r = FSR); ++ void pop_l( Register r = FSR); ++ void pop_f(FloatRegister r = FSF); ++ void pop_d(FloatRegister r = FSF); ++ ++ void push_ptr( Register r = FSR); ++ void push_i( Register r = FSR); ++ void push_l( Register r = FSR); ++ void push_f(FloatRegister r = FSF); ++ void push_d(FloatRegister r = FSF); ++ ++ void pop(Register r ) { ((MacroAssembler*)this)->pop(r); } ++ ++ void push(Register r ) { ((MacroAssembler*)this)->push(r); } ++ ++ void pop(TosState state); // transition vtos -> state ++ void push(TosState state); // transition state -> vtos ++ ++ void empty_expression_stack() { ++ ld(SP, FP, frame::interpreter_frame_monitor_block_top_offset * wordSize); ++ // NULL last_sp until next java call ++ sd(R0, FP, frame::interpreter_frame_last_sp_offset * wordSize); ++ } ++ ++ // Super call_VM calls - correspond to MacroAssembler::call_VM(_leaf) calls ++ void load_ptr(int n, Register val); ++ void store_ptr(int n, Register val); ++ ++ // Generate a subtype check: branch to ok_is_subtype if sub_klass is ++ // a subtype of super_klass. ++ //void gen_subtype_check( Register sub_klass, Label &ok_is_subtype ); ++ void gen_subtype_check( Register Rsup_klass, Register sub_klass, Label &ok_is_subtype ); ++ ++ // Dispatching ++ void dispatch_prolog(TosState state, int step = 0); ++ void dispatch_epilog(TosState state, int step = 0); ++ void dispatch_only(TosState state, bool generate_poll = false); ++ void dispatch_only_normal(TosState state); ++ void dispatch_only_noverify(TosState state); ++ void dispatch_next(TosState state, int step = 0, bool generate_poll = false); ++ void dispatch_via (TosState state, address* table); ++ ++ // jump to an invoked target ++ void prepare_to_jump_from_interpreted(); ++ void jump_from_interpreted(Register method, Register temp); ++ ++ ++ // Returning from interpreted functions ++ // ++ // Removes the current activation (incl. unlocking of monitors) ++ // and sets up the return address. This code is also used for ++ // exception unwindwing. In that case, we do not want to throw ++ // IllegalMonitorStateExceptions, since that might get us into an ++ // infinite rethrow exception loop. ++ // Additionally this code is used for popFrame and earlyReturn. ++ // In popFrame case we want to skip throwing an exception, ++ // installing an exception, and notifying jvmdi. ++ // In earlyReturn case we only want to skip throwing an exception ++ // and installing an exception. ++ void remove_activation(TosState state, Register ret_addr, ++ bool throw_monitor_exception = true, ++ bool install_monitor_exception = true, ++ bool notify_jvmdi = true); ++ ++ // Object locking ++ void lock_object (Register lock_reg); ++ void unlock_object(Register lock_reg); ++ ++ // Interpreter profiling operations ++ void set_method_data_pointer_for_bcp(); ++ void test_method_data_pointer(Register mdp, Label& zero_continue); ++ void verify_method_data_pointer(); ++ ++ void set_mdp_data_at(Register mdp_in, int constant, Register value); ++ void increment_mdp_data_at(Address data, bool decrement = false); ++ void increment_mdp_data_at(Register mdp_in, int constant, ++ bool decrement = false); ++ void increment_mdp_data_at(Register mdp_in, Register reg, int constant, ++ bool decrement = false); ++ void increment_mask_and_jump(Address counter_addr, ++ int increment, Address mask, ++ Register scratch, bool preloaded, ++ Condition cond, Label* where); ++ void set_mdp_flag_at(Register mdp_in, int flag_constant); ++ void test_mdp_data_at(Register mdp_in, int offset, Register value, ++ Register test_value_out, ++ Label& not_equal_continue); ++ ++ void record_klass_in_profile(Register receiver, Register mdp, ++ Register reg2, bool is_virtual_call); ++ void record_klass_in_profile_helper(Register receiver, Register mdp, ++ Register reg2, int start_row, ++ Label& done, bool is_virtual_call); ++ ++ void update_mdp_by_offset(Register mdp_in, int offset_of_offset); ++ void update_mdp_by_offset(Register mdp_in, Register reg, int offset_of_disp); ++ void update_mdp_by_constant(Register mdp_in, int constant); ++ void update_mdp_for_ret(Register return_bci); ++ ++ void profile_taken_branch(Register mdp, Register bumped_count); ++ void profile_not_taken_branch(Register mdp); ++ void profile_call(Register mdp); ++ void profile_final_call(Register mdp); ++ void profile_virtual_call(Register receiver, Register mdp, ++ Register scratch2, ++ bool receiver_can_be_null = false); ++ void profile_called_method(Register method, Register mdp, Register reg2) NOT_JVMCI_RETURN; ++ void profile_ret(Register return_bci, Register mdp); ++ void profile_null_seen(Register mdp); ++ void profile_typecheck(Register mdp, Register klass, Register scratch); ++ void profile_typecheck_failed(Register mdp); ++ void profile_switch_default(Register mdp); ++ void profile_switch_case(Register index_in_scratch, Register mdp, ++ Register scratch2); ++ ++ // Debugging ++ // only if +VerifyOops && state == atos ++ void verify_oop(Register reg, TosState state = atos); ++ // only if +VerifyFPU && (state == ftos || state == dtos) ++ void verify_FPU(int stack_depth, TosState state = ftos); ++ ++ void profile_obj_type(Register obj, const Address& mdo_addr); ++ void profile_arguments_type(Register mdp, Register callee, Register tmp, bool is_virtual); ++ void profile_return_type(Register mdp, Register ret, Register tmp); ++ void profile_parameters_type(Register mdp, Register tmp1, Register tmp2); ++ ++ typedef enum { NotifyJVMTI, SkipNotifyJVMTI } NotifyMethodExitMode; ++ ++ // support for jvmti/dtrace ++ void notify_method_entry(); ++ void notify_method_exit(TosState state, NotifyMethodExitMode mode); +}; + -+#endif // CPU_MIPS_VM_INTERPRETERRT_MIPS_HPP -diff --git a/src/hotspot/cpu/mips/interpreterRT_mips_64.cpp b/src/hotspot/cpu/mips/interpreterRT_mips_64.cpp -new file mode 100644 -index 00000000000..3e8ae9fb5a5 ---- /dev/null -+++ b/src/hotspot/cpu/mips/interpreterRT_mips_64.cpp ++#endif // CPU_MIPS_VM_INTERP_MASM_MIPS_64_HPP +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/mips/interpreterRT_mips_64.cpp b/src/hotspot/cpu/mips/interpreterRT_mips_64.cpp +--- a/src/hotspot/cpu/mips/interpreterRT_mips_64.cpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/mips/interpreterRT_mips_64.cpp 2024-01-31 14:01:11.607428929 +0800 @@ -0,0 +1,260 @@ +/* + * Copyright (c) 2003, 2012, Oracle and/or its affiliates. All rights reserved. @@ -74815,11 +74096,73 @@ index 00000000000..3e8ae9fb5a5 + // return result handler + return Interpreter::result_handler(m->result_type()); +JRT_END -diff --git a/src/hotspot/cpu/mips/javaFrameAnchor_mips.hpp b/src/hotspot/cpu/mips/javaFrameAnchor_mips.hpp -new file mode 100644 -index 00000000000..f5f3735e7cb ---- /dev/null -+++ b/src/hotspot/cpu/mips/javaFrameAnchor_mips.hpp +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/mips/interpreterRT_mips.hpp b/src/hotspot/cpu/mips/interpreterRT_mips.hpp +--- a/src/hotspot/cpu/mips/interpreterRT_mips.hpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/mips/interpreterRT_mips.hpp 2024-01-31 14:01:11.607428929 +0800 +@@ -0,0 +1,60 @@ ++/* ++ * Copyright (c) 1998, 2010, Oracle and/or its affiliates. All rights reserved. ++ * Copyright (c) 2015, 2022, Loongson Technology. All rights reserved. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ * ++ */ ++ ++#ifndef CPU_MIPS_VM_INTERPRETERRT_MIPS_HPP ++#define CPU_MIPS_VM_INTERPRETERRT_MIPS_HPP ++ ++// This is included in the middle of class Interpreter. ++// Do not include files here. ++ ++// native method calls ++ ++class SignatureHandlerGenerator: public NativeSignatureIterator { ++ private: ++ MacroAssembler* _masm; ++ ++ void move(int from_offset, int to_offset); ++ ++ void box(int from_offset, int to_offset); ++ void pass_int(); ++ void pass_long(); ++ void pass_object(); ++ void pass_float(); ++ void pass_double(); ++ ++ public: ++ // Creation ++ SignatureHandlerGenerator(const methodHandle& method, CodeBuffer* buffer); ++ ++ // Code generation ++ void generate(uint64_t fingerprint); ++ ++ // Code generation support ++ static Register from(); ++ static Register to(); ++ static Register temp(); ++}; ++ ++#endif // CPU_MIPS_VM_INTERPRETERRT_MIPS_HPP +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/mips/javaFrameAnchor_mips.hpp b/src/hotspot/cpu/mips/javaFrameAnchor_mips.hpp +--- a/src/hotspot/cpu/mips/javaFrameAnchor_mips.hpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/mips/javaFrameAnchor_mips.hpp 2024-01-31 14:01:11.607428929 +0800 @@ -0,0 +1,87 @@ +/* + * Copyright (c) 2002, 2010, Oracle and/or its affiliates. All rights reserved. @@ -74908,11 +74251,9 @@ index 00000000000..f5f3735e7cb + void set_last_Java_fp(intptr_t* fp) { _last_Java_fp = fp; } + +#endif // CPU_MIPS_VM_JAVAFRAMEANCHOR_MIPS_HPP -diff --git a/src/hotspot/cpu/mips/jniFastGetField_mips_64.cpp b/src/hotspot/cpu/mips/jniFastGetField_mips_64.cpp -new file mode 100644 -index 00000000000..547414f7ef3 ---- /dev/null -+++ b/src/hotspot/cpu/mips/jniFastGetField_mips_64.cpp +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/mips/jniFastGetField_mips_64.cpp b/src/hotspot/cpu/mips/jniFastGetField_mips_64.cpp +--- a/src/hotspot/cpu/mips/jniFastGetField_mips_64.cpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/mips/jniFastGetField_mips_64.cpp 2024-01-31 14:01:11.607428929 +0800 @@ -0,0 +1,203 @@ +/* + * Copyright (c) 2004, 2010, Oracle and/or its affiliates. All rights reserved. @@ -75117,11 +74458,9 @@ index 00000000000..547414f7ef3 +address JNI_FastGetField::generate_fast_get_double_field() { + return generate_fast_get_int_field0(T_DOUBLE); +} -diff --git a/src/hotspot/cpu/mips/jniTypes_mips.hpp b/src/hotspot/cpu/mips/jniTypes_mips.hpp -new file mode 100644 -index 00000000000..08ac565aa53 ---- /dev/null -+++ b/src/hotspot/cpu/mips/jniTypes_mips.hpp +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/mips/jniTypes_mips.hpp b/src/hotspot/cpu/mips/jniTypes_mips.hpp +--- a/src/hotspot/cpu/mips/jniTypes_mips.hpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/mips/jniTypes_mips.hpp 2024-01-31 14:01:11.607428929 +0800 @@ -0,0 +1,143 @@ +/* + * Copyright (c) 1998, 2010, Oracle and/or its affiliates. All rights reserved. @@ -75266,11 +74605,9 @@ index 00000000000..08ac565aa53 +}; + +#endif // CPU_MIPS_VM_JNITYPES_MIPS_HPP -diff --git a/src/hotspot/cpu/mips/macroAssembler_mips.cpp b/src/hotspot/cpu/mips/macroAssembler_mips.cpp -new file mode 100644 -index 00000000000..1256e957970 ---- /dev/null -+++ b/src/hotspot/cpu/mips/macroAssembler_mips.cpp +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/mips/macroAssembler_mips.cpp b/src/hotspot/cpu/mips/macroAssembler_mips.cpp +--- a/src/hotspot/cpu/mips/macroAssembler_mips.cpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/mips/macroAssembler_mips.cpp 2024-01-31 14:01:11.607428929 +0800 @@ -0,0 +1,3686 @@ +/* + * Copyright (c) 1997, 2014, Oracle and/or its affiliates. All rights reserved. @@ -78958,11 +78295,9 @@ index 00000000000..1256e957970 + Unimplemented(); + } +} -diff --git a/src/hotspot/cpu/mips/macroAssembler_mips.hpp b/src/hotspot/cpu/mips/macroAssembler_mips.hpp -new file mode 100644 -index 00000000000..daec23fcf9c ---- /dev/null -+++ b/src/hotspot/cpu/mips/macroAssembler_mips.hpp +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/mips/macroAssembler_mips.hpp b/src/hotspot/cpu/mips/macroAssembler_mips.hpp +--- a/src/hotspot/cpu/mips/macroAssembler_mips.hpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/mips/macroAssembler_mips.hpp 2024-01-31 14:01:11.607428929 +0800 @@ -0,0 +1,704 @@ +/* + * Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved. @@ -79668,11 +79003,9 @@ index 00000000000..daec23fcf9c + + +#endif // CPU_MIPS_VM_MACROASSEMBLER_MIPS_HPP -diff --git a/src/hotspot/cpu/mips/macroAssembler_mips.inline.hpp b/src/hotspot/cpu/mips/macroAssembler_mips.inline.hpp -new file mode 100644 -index 00000000000..92c05fb726a ---- /dev/null -+++ b/src/hotspot/cpu/mips/macroAssembler_mips.inline.hpp +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/mips/macroAssembler_mips.inline.hpp b/src/hotspot/cpu/mips/macroAssembler_mips.inline.hpp +--- a/src/hotspot/cpu/mips/macroAssembler_mips.inline.hpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/mips/macroAssembler_mips.inline.hpp 2024-01-31 14:01:11.607428929 +0800 @@ -0,0 +1,34 @@ +/* + * Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved. @@ -79708,11 +79041,9 @@ index 00000000000..92c05fb726a +#include "code/codeCache.hpp" + +#endif // CPU_MIPS_VM_MACROASSEMBLER_MIPS_INLINE_HPP -diff --git a/src/hotspot/cpu/mips/matcher_mips.hpp b/src/hotspot/cpu/mips/matcher_mips.hpp -new file mode 100644 -index 00000000000..94f58720ffe ---- /dev/null -+++ b/src/hotspot/cpu/mips/matcher_mips.hpp +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/mips/matcher_mips.hpp b/src/hotspot/cpu/mips/matcher_mips.hpp +--- a/src/hotspot/cpu/mips/matcher_mips.hpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/mips/matcher_mips.hpp 2024-01-31 14:01:11.607428929 +0800 @@ -0,0 +1,145 @@ +/* + * Copyright (c) 2021, Oracle and/or its affiliates. All rights reserved. @@ -79859,11 +79190,9 @@ index 00000000000..94f58720ffe + static const bool supports_encode_ascii_array = false; + +#endif // CPU_MIPS_MATCHER_MIPS_HPP -diff --git a/src/hotspot/cpu/mips/methodHandles_mips.cpp b/src/hotspot/cpu/mips/methodHandles_mips.cpp -new file mode 100644 -index 00000000000..c4279705062 ---- /dev/null -+++ b/src/hotspot/cpu/mips/methodHandles_mips.cpp +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/mips/methodHandles_mips.cpp b/src/hotspot/cpu/mips/methodHandles_mips.cpp +--- a/src/hotspot/cpu/mips/methodHandles_mips.cpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/mips/methodHandles_mips.cpp 2024-01-31 14:01:11.607428929 +0800 @@ -0,0 +1,597 @@ +/* + * Copyright (c) 1997, 2014, Oracle and/or its affiliates. All rights reserved. @@ -80462,11 +79791,9 @@ index 00000000000..c4279705062 +void MethodHandles::trace_method_handle(MacroAssembler* _masm, const char* adaptername) { +} +#endif //PRODUCT -diff --git a/src/hotspot/cpu/mips/methodHandles_mips.hpp b/src/hotspot/cpu/mips/methodHandles_mips.hpp -new file mode 100644 -index 00000000000..a95f8e40596 ---- /dev/null -+++ b/src/hotspot/cpu/mips/methodHandles_mips.hpp +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/mips/methodHandles_mips.hpp b/src/hotspot/cpu/mips/methodHandles_mips.hpp +--- a/src/hotspot/cpu/mips/methodHandles_mips.hpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/mips/methodHandles_mips.hpp 2024-01-31 14:01:11.607428929 +0800 @@ -0,0 +1,62 @@ +/* + * Copyright (c) 2010, 2012, Oracle and/or its affiliates. All rights reserved. @@ -80530,43 +79857,10 @@ index 00000000000..a95f8e40596 + // Should be in sharedRuntime, not here. + return I29; + } -diff --git a/src/hotspot/cpu/mips/mips.ad b/src/hotspot/cpu/mips/mips.ad -new file mode 100644 -index 00000000000..3563bbe0e59 ---- /dev/null -+++ b/src/hotspot/cpu/mips/mips.ad -@@ -0,0 +1,25 @@ -+// -+// Copyright (c) 2011, 2012, Oracle and/or its affiliates. All rights reserved. -+// Copyright (c) 2015, 2016, Loongson Technology. All rights reserved. -+// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. -+// -+// This code is free software; you can redistribute it and/or modify it -+// under the terms of the GNU General Public License version 2 only, as -+// published by the Free Software Foundation. -+// -+// This code is distributed in the hope that it will be useful, but WITHOUT -+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -+// version 2 for more details (a copy is included in the LICENSE file that -+// accompanied this code). -+// -+// You should have received a copy of the GNU General Public License version -+// 2 along with this work; if not, write to the Free Software Foundation, -+// Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. -+// -+// Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA -+// or visit www.oracle.com if you need additional information or have any -+// questions. -+// -+// -+ -diff --git a/src/hotspot/cpu/mips/mips_64.ad b/src/hotspot/cpu/mips/mips_64.ad -new file mode 100644 -index 00000000000..ec85f64244c ---- /dev/null -+++ b/src/hotspot/cpu/mips/mips_64.ad -@@ -0,0 +1,12316 @@ +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/mips/mips_64.ad b/src/hotspot/cpu/mips/mips_64.ad +--- a/src/hotspot/cpu/mips/mips_64.ad 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/mips/mips_64.ad 2024-01-31 14:01:11.607428929 +0800 +@@ -0,0 +1,12317 @@ +// +// Copyright (c) 2003, 2013, Oracle and/or its affiliates. All rights reserved. +// Copyright (c) 2015, 2022, Loongson Technology. All rights reserved. @@ -87696,6 +86990,7 @@ index 00000000000..ec85f64244c + +instruct membar_storestore() %{ + match(MemBarStoreStore); ++ match(StoreStoreFence); + + ins_cost(400); + format %{ "MEMBAR-storestore @ membar_storestore" %} @@ -92883,11 +92178,38 @@ index 00000000000..ec85f64244c +// These must follow all instruction definitions as they use the names +// defined in the instructions definitions. + -diff --git a/src/hotspot/cpu/mips/nativeInst_mips.cpp b/src/hotspot/cpu/mips/nativeInst_mips.cpp -new file mode 100644 -index 00000000000..05c525f35ef ---- /dev/null -+++ b/src/hotspot/cpu/mips/nativeInst_mips.cpp +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/mips/mips.ad b/src/hotspot/cpu/mips/mips.ad +--- a/src/hotspot/cpu/mips/mips.ad 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/mips/mips.ad 2024-01-31 14:01:11.607428929 +0800 +@@ -0,0 +1,25 @@ ++// ++// Copyright (c) 2011, 2012, Oracle and/or its affiliates. All rights reserved. ++// Copyright (c) 2015, 2016, Loongson Technology. All rights reserved. ++// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++// ++// This code is free software; you can redistribute it and/or modify it ++// under the terms of the GNU General Public License version 2 only, as ++// published by the Free Software Foundation. ++// ++// This code is distributed in the hope that it will be useful, but WITHOUT ++// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++// version 2 for more details (a copy is included in the LICENSE file that ++// accompanied this code). ++// ++// You should have received a copy of the GNU General Public License version ++// 2 along with this work; if not, write to the Free Software Foundation, ++// Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++// ++// Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++// or visit www.oracle.com if you need additional information or have any ++// questions. ++// ++// ++ +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/mips/nativeInst_mips.cpp b/src/hotspot/cpu/mips/nativeInst_mips.cpp +--- a/src/hotspot/cpu/mips/nativeInst_mips.cpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/mips/nativeInst_mips.cpp 2024-01-31 14:01:11.610762293 +0800 @@ -0,0 +1,1825 @@ +/* + * Copyright (c) 1997, 2014, Oracle and/or its affiliates. All rights reserved. @@ -94714,11 +94036,9 @@ index 00000000000..05c525f35ef + // we check the safepoint instruction like the this. + return is_op(Assembler::lw_op) && is_rt(AT); +} -diff --git a/src/hotspot/cpu/mips/nativeInst_mips.hpp b/src/hotspot/cpu/mips/nativeInst_mips.hpp -new file mode 100644 -index 00000000000..9f0f24cc34b ---- /dev/null -+++ b/src/hotspot/cpu/mips/nativeInst_mips.hpp +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/mips/nativeInst_mips.hpp b/src/hotspot/cpu/mips/nativeInst_mips.hpp +--- a/src/hotspot/cpu/mips/nativeInst_mips.hpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/mips/nativeInst_mips.hpp 2024-01-31 14:01:11.610762293 +0800 @@ -0,0 +1,734 @@ +/* + * Copyright (c) 1997, 2011, Oracle and/or its affiliates. All rights reserved. @@ -95454,67 +94774,9 @@ index 00000000000..9f0f24cc34b + return (NativeCallTrampolineStub*)addr; +} +#endif // CPU_MIPS_VM_NATIVEINST_MIPS_HPP -diff --git a/src/hotspot/cpu/mips/registerMap_mips.hpp b/src/hotspot/cpu/mips/registerMap_mips.hpp -new file mode 100644 -index 00000000000..3f3558f79d4 ---- /dev/null -+++ b/src/hotspot/cpu/mips/registerMap_mips.hpp -@@ -0,0 +1,50 @@ -+/* -+ * Copyright (c) 1998, 2010, Oracle and/or its affiliates. All rights reserved. -+ * Copyright (c) 2015, 2021, Loongson Technology. All rights reserved. -+ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. -+ * -+ * This code is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 only, as -+ * published by the Free Software Foundation. -+ * -+ * This code is distributed in the hope that it will be useful, but WITHOUT -+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -+ * version 2 for more details (a copy is included in the LICENSE file that -+ * accompanied this code). -+ * -+ * You should have received a copy of the GNU General Public License version -+ * 2 along with this work; if not, write to the Free Software Foundation, -+ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. -+ * -+ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA -+ * or visit www.oracle.com if you need additional information or have any -+ * questions. -+ * -+ */ -+ -+#ifndef CPU_MIPS_VM_REGISTERMAP_MIPS_HPP -+#define CPU_MIPS_VM_REGISTERMAP_MIPS_HPP -+ -+// machine-dependent implemention for register maps -+ friend class frame; -+ -+ private: -+#ifndef CORE -+ // This is the hook for finding a register in an "well-known" location, -+ // such as a register block of a predetermined format. -+ // Since there is none, we just return NULL. -+ // See registerMap_sparc.hpp for an example of grabbing registers -+ // from register save areas of a standard layout. -+ address pd_location(VMReg reg) const {return NULL;} -+ address pd_location(VMReg base_reg, int slot_idx) const { -+ return location(base_reg->next(slot_idx)); -+ } -+#endif -+ -+ // no PD state to clear or copy: -+ void pd_clear() {} -+ void pd_initialize() {} -+ void pd_initialize_from(const RegisterMap* map) {} -+ -+#endif // CPU_MIPS_VM_REGISTERMAP_MIPS_HPP -diff --git a/src/hotspot/cpu/mips/register_definitions_mips.cpp b/src/hotspot/cpu/mips/register_definitions_mips.cpp -new file mode 100644 -index 00000000000..4af25318346 ---- /dev/null -+++ b/src/hotspot/cpu/mips/register_definitions_mips.cpp +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/mips/register_definitions_mips.cpp b/src/hotspot/cpu/mips/register_definitions_mips.cpp +--- a/src/hotspot/cpu/mips/register_definitions_mips.cpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/mips/register_definitions_mips.cpp 2024-01-31 14:01:11.610762293 +0800 @@ -0,0 +1,103 @@ +/* + * Copyright (c) 2002, 2013, Oracle and/or its affiliates. All rights reserved. @@ -95619,11 +94881,63 @@ index 00000000000..4af25318346 +REGISTER_DEFINITION(FloatRegister, f29); +REGISTER_DEFINITION(FloatRegister, f30); +REGISTER_DEFINITION(FloatRegister, f31); -diff --git a/src/hotspot/cpu/mips/register_mips.cpp b/src/hotspot/cpu/mips/register_mips.cpp -new file mode 100644 -index 00000000000..4a9b22bfef2 ---- /dev/null -+++ b/src/hotspot/cpu/mips/register_mips.cpp +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/mips/registerMap_mips.hpp b/src/hotspot/cpu/mips/registerMap_mips.hpp +--- a/src/hotspot/cpu/mips/registerMap_mips.hpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/mips/registerMap_mips.hpp 2024-01-31 14:01:11.610762293 +0800 +@@ -0,0 +1,50 @@ ++/* ++ * Copyright (c) 1998, 2010, Oracle and/or its affiliates. All rights reserved. ++ * Copyright (c) 2015, 2021, Loongson Technology. All rights reserved. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ * ++ */ ++ ++#ifndef CPU_MIPS_VM_REGISTERMAP_MIPS_HPP ++#define CPU_MIPS_VM_REGISTERMAP_MIPS_HPP ++ ++// machine-dependent implemention for register maps ++ friend class frame; ++ ++ private: ++#ifndef CORE ++ // This is the hook for finding a register in an "well-known" location, ++ // such as a register block of a predetermined format. ++ // Since there is none, we just return NULL. ++ // See registerMap_sparc.hpp for an example of grabbing registers ++ // from register save areas of a standard layout. ++ address pd_location(VMReg reg) const {return NULL;} ++ address pd_location(VMReg base_reg, int slot_idx) const { ++ return location(base_reg->next(slot_idx)); ++ } ++#endif ++ ++ // no PD state to clear or copy: ++ void pd_clear() {} ++ void pd_initialize() {} ++ void pd_initialize_from(const RegisterMap* map) {} ++ ++#endif // CPU_MIPS_VM_REGISTERMAP_MIPS_HPP +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/mips/register_mips.cpp b/src/hotspot/cpu/mips/register_mips.cpp +--- a/src/hotspot/cpu/mips/register_mips.cpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/mips/register_mips.cpp 2024-01-31 14:01:11.610762293 +0800 @@ -0,0 +1,52 @@ +/* + * Copyright (c) 2000, 2012, Oracle and/or its affiliates. All rights reserved. @@ -95677,11 +94991,9 @@ index 00000000000..4a9b22bfef2 + return is_valid() ? names[encoding()] : "fnoreg"; +} + -diff --git a/src/hotspot/cpu/mips/register_mips.hpp b/src/hotspot/cpu/mips/register_mips.hpp -new file mode 100644 -index 00000000000..4f74717c24f ---- /dev/null -+++ b/src/hotspot/cpu/mips/register_mips.hpp +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/mips/register_mips.hpp b/src/hotspot/cpu/mips/register_mips.hpp +--- a/src/hotspot/cpu/mips/register_mips.hpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/mips/register_mips.hpp 2024-01-31 14:01:11.610762293 +0800 @@ -0,0 +1,344 @@ +/* + * Copyright (c) 2000, 2012, Oracle and/or its affiliates. All rights reserved. @@ -96027,11 +95339,9 @@ index 00000000000..4f74717c24f +}; + +#endif //CPU_MIPS_VM_REGISTER_MIPS_HPP -diff --git a/src/hotspot/cpu/mips/relocInfo_mips.cpp b/src/hotspot/cpu/mips/relocInfo_mips.cpp -new file mode 100644 -index 00000000000..7d8d072b51b ---- /dev/null -+++ b/src/hotspot/cpu/mips/relocInfo_mips.cpp +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/mips/relocInfo_mips.cpp b/src/hotspot/cpu/mips/relocInfo_mips.cpp +--- a/src/hotspot/cpu/mips/relocInfo_mips.cpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/mips/relocInfo_mips.cpp 2024-01-31 14:01:11.610762293 +0800 @@ -0,0 +1,160 @@ +/* + * Copyright (c) 1998, 2013, Oracle and/or its affiliates. All rights reserved. @@ -96193,11 +95503,9 @@ index 00000000000..7d8d072b51b + +void metadata_Relocation::pd_fix_value(address x) { +} -diff --git a/src/hotspot/cpu/mips/relocInfo_mips.hpp b/src/hotspot/cpu/mips/relocInfo_mips.hpp -new file mode 100644 -index 00000000000..1e1e170fd87 ---- /dev/null -+++ b/src/hotspot/cpu/mips/relocInfo_mips.hpp +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/mips/relocInfo_mips.hpp b/src/hotspot/cpu/mips/relocInfo_mips.hpp +--- a/src/hotspot/cpu/mips/relocInfo_mips.hpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/mips/relocInfo_mips.hpp 2024-01-31 14:01:11.610762293 +0800 @@ -0,0 +1,44 @@ +/* + * Copyright (c) 1997, 2010, Oracle and/or its affiliates. All rights reserved. @@ -96243,11 +95551,9 @@ index 00000000000..1e1e170fd87 + static bool mustIterateImmediateOopsInCode() { return false; } + +#endif // CPU_MIPS_VM_RELOCINFO_MIPS_HPP -diff --git a/src/hotspot/cpu/mips/runtime_mips_64.cpp b/src/hotspot/cpu/mips/runtime_mips_64.cpp -new file mode 100644 -index 00000000000..36ab413f0b3 ---- /dev/null -+++ b/src/hotspot/cpu/mips/runtime_mips_64.cpp +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/mips/runtime_mips_64.cpp b/src/hotspot/cpu/mips/runtime_mips_64.cpp +--- a/src/hotspot/cpu/mips/runtime_mips_64.cpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/mips/runtime_mips_64.cpp 2024-01-31 14:01:11.610762293 +0800 @@ -0,0 +1,206 @@ +/* + * Copyright (c) 2003, 2010, Oracle and/or its affiliates. All rights reserved. @@ -96455,11 +95761,9 @@ index 00000000000..36ab413f0b3 + + _exception_blob = ExceptionBlob::create(&buffer, oop_maps, framesize); +} -diff --git a/src/hotspot/cpu/mips/sharedRuntime_mips_64.cpp b/src/hotspot/cpu/mips/sharedRuntime_mips_64.cpp -new file mode 100644 -index 00000000000..48cc424a54e ---- /dev/null -+++ b/src/hotspot/cpu/mips/sharedRuntime_mips_64.cpp +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/mips/sharedRuntime_mips_64.cpp b/src/hotspot/cpu/mips/sharedRuntime_mips_64.cpp +--- a/src/hotspot/cpu/mips/sharedRuntime_mips_64.cpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/mips/sharedRuntime_mips_64.cpp 2024-01-31 14:01:11.610762293 +0800 @@ -0,0 +1,3384 @@ +/* + * Copyright (c) 2003, 2013, Oracle and/or its affiliates. All rights reserved. @@ -99845,15 +99149,13 @@ index 00000000000..48cc424a54e + return nullptr; +} +#endif -diff --git a/src/hotspot/cpu/mips/stubGenerator_mips_64.cpp b/src/hotspot/cpu/mips/stubGenerator_mips_64.cpp -new file mode 100644 -index 00000000000..ad44d23c531 ---- /dev/null -+++ b/src/hotspot/cpu/mips/stubGenerator_mips_64.cpp -@@ -0,0 +1,2774 @@ +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/mips/stubGenerator_mips_64.cpp b/src/hotspot/cpu/mips/stubGenerator_mips_64.cpp +--- a/src/hotspot/cpu/mips/stubGenerator_mips_64.cpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/mips/stubGenerator_mips_64.cpp 2024-01-31 14:01:11.610762293 +0800 +@@ -0,0 +1,2725 @@ +/* + * Copyright (c) 2003, 2013, Oracle and/or its affiliates. All rights reserved. -+ * Copyright (c) 2015, 2022, Loongson Technology. All rights reserved. ++ * Copyright (c) 2015, 2023, Loongson Technology. All rights reserved. + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. + * + * This code is free software; you can redistribute it and/or modify it @@ -101758,47 +101060,6 @@ index 00000000000..ad44d23c531 + StubRoutines::_arrayof_jint_fill = generate_fill(T_INT, true, "arrayof_jint_fill"); + } + -+ // add a function to implement SafeFetch32 and SafeFetchN -+ void generate_safefetch(const char* name, int size, address* entry, -+ address* fault_pc, address* continuation_pc) { -+ // safefetch signatures: -+ // int SafeFetch32(int* adr, int errValue); -+ // intptr_t SafeFetchN (intptr_t* adr, intptr_t errValue); -+ // -+ // arguments: -+ // A0 = adr -+ // A1 = errValue -+ // -+ // result: -+ // PPC_RET = *adr or errValue -+ -+ StubCodeMark mark(this, "StubRoutines", name); -+ -+ // Entry point, pc or function descriptor. -+ *entry = __ pc(); -+ -+ // Load *adr into A1, may fault. -+ *fault_pc = __ pc(); -+ switch (size) { -+ case 4: -+ // int32_t -+ __ lw(A1, A0, 0); -+ break; -+ case 8: -+ // int64_t -+ __ ld(A1, A0, 0); -+ break; -+ default: -+ ShouldNotReachHere(); -+ } -+ -+ // return errValue or *adr -+ *continuation_pc = __ pc(); -+ __ addu(V0,A1,R0); -+ __ jr(RA); -+ __ delayed()->nop(); -+ } -+ + +#undef __ +#define __ masm-> @@ -102574,14 +101835,6 @@ index 00000000000..ad44d23c531 + generate_arraycopy_stubs(); +#endif + -+ // Safefetch stubs. -+ generate_safefetch("SafeFetch32", sizeof(int), &StubRoutines::_safefetch32_entry, -+ &StubRoutines::_safefetch32_fault_pc, -+ &StubRoutines::_safefetch32_continuation_pc); -+ generate_safefetch("SafeFetchN", sizeof(intptr_t), &StubRoutines::_safefetchN_entry, -+ &StubRoutines::_safefetchN_fault_pc, -+ &StubRoutines::_safefetchN_continuation_pc); -+ +#ifdef COMPILER2 + if (UseMontgomeryMultiplyIntrinsic) { + if (UseLEXT1) { @@ -102625,11 +101878,48 @@ index 00000000000..ad44d23c531 + } + StubGenerator g(code, all); +} -diff --git a/src/hotspot/cpu/mips/stubRoutines_mips.hpp b/src/hotspot/cpu/mips/stubRoutines_mips.hpp -new file mode 100644 -index 00000000000..920c08844e1 ---- /dev/null -+++ b/src/hotspot/cpu/mips/stubRoutines_mips.hpp +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/mips/stubRoutines_mips_64.cpp b/src/hotspot/cpu/mips/stubRoutines_mips_64.cpp +--- a/src/hotspot/cpu/mips/stubRoutines_mips_64.cpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/mips/stubRoutines_mips_64.cpp 2024-01-31 14:01:11.610762293 +0800 +@@ -0,0 +1,35 @@ ++/* ++ * Copyright (c) 2003, 2013, Oracle and/or its affiliates. All rights reserved. ++ * Copyright (c) 2015, 2021, Loongson Technology. All rights reserved. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ * ++ */ ++ ++#include "precompiled.hpp" ++#include "runtime/deoptimization.hpp" ++#include "runtime/frame.inline.hpp" ++#include "runtime/stubRoutines.hpp" ++#include "runtime/thread.inline.hpp" ++ ++// a description of how to extend it, see the stubRoutines.hpp file. ++ ++//find the last fp value ++address StubRoutines::gs2::_call_stub_compiled_return = NULL; +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/mips/stubRoutines_mips.hpp b/src/hotspot/cpu/mips/stubRoutines_mips.hpp +--- a/src/hotspot/cpu/mips/stubRoutines_mips.hpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/mips/stubRoutines_mips.hpp 2024-01-31 14:01:11.610762293 +0800 @@ -0,0 +1,59 @@ +/* + * Copyright (c) 2003, 2013, Oracle and/or its affiliates. All rights reserved. @@ -102690,52 +101980,9 @@ index 00000000000..920c08844e1 +}; + +#endif // CPU_MIPS_VM_STUBROUTINES_MIPS_64_HPP -diff --git a/src/hotspot/cpu/mips/stubRoutines_mips_64.cpp b/src/hotspot/cpu/mips/stubRoutines_mips_64.cpp -new file mode 100644 -index 00000000000..358d580d527 ---- /dev/null -+++ b/src/hotspot/cpu/mips/stubRoutines_mips_64.cpp -@@ -0,0 +1,35 @@ -+/* -+ * Copyright (c) 2003, 2013, Oracle and/or its affiliates. All rights reserved. -+ * Copyright (c) 2015, 2021, Loongson Technology. All rights reserved. -+ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. -+ * -+ * This code is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 only, as -+ * published by the Free Software Foundation. -+ * -+ * This code is distributed in the hope that it will be useful, but WITHOUT -+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -+ * version 2 for more details (a copy is included in the LICENSE file that -+ * accompanied this code). -+ * -+ * You should have received a copy of the GNU General Public License version -+ * 2 along with this work; if not, write to the Free Software Foundation, -+ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. -+ * -+ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA -+ * or visit www.oracle.com if you need additional information or have any -+ * questions. -+ * -+ */ -+ -+#include "precompiled.hpp" -+#include "runtime/deoptimization.hpp" -+#include "runtime/frame.inline.hpp" -+#include "runtime/stubRoutines.hpp" -+#include "runtime/thread.inline.hpp" -+ -+// a description of how to extend it, see the stubRoutines.hpp file. -+ -+//find the last fp value -+address StubRoutines::gs2::_call_stub_compiled_return = NULL; -diff --git a/src/hotspot/cpu/mips/templateInterpreterGenerator_mips.cpp b/src/hotspot/cpu/mips/templateInterpreterGenerator_mips.cpp -new file mode 100644 -index 00000000000..b723add6dfc ---- /dev/null -+++ b/src/hotspot/cpu/mips/templateInterpreterGenerator_mips.cpp +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/mips/templateInterpreterGenerator_mips.cpp b/src/hotspot/cpu/mips/templateInterpreterGenerator_mips.cpp +--- a/src/hotspot/cpu/mips/templateInterpreterGenerator_mips.cpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/mips/templateInterpreterGenerator_mips.cpp 2024-01-31 14:01:11.610762293 +0800 @@ -0,0 +1,2094 @@ +/* + * Copyright (c) 2003, 2013, Oracle and/or its affiliates. All rights reserved. @@ -104831,60 +104078,9 @@ index 00000000000..b723add6dfc + __ bind(L); +} +#endif // !PRODUCT -diff --git a/src/hotspot/cpu/mips/templateTable_mips.hpp b/src/hotspot/cpu/mips/templateTable_mips.hpp -new file mode 100644 -index 00000000000..46a88aba261 ---- /dev/null -+++ b/src/hotspot/cpu/mips/templateTable_mips.hpp -@@ -0,0 +1,43 @@ -+/* -+ * Copyright (c) 2003, 2012, Oracle and/or its affiliates. All rights reserved. -+ * Copyright (c) 2015, 2018, Loongson Technology. All rights reserved. -+ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. -+ * -+ * This code is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 only, as -+ * published by the Free Software Foundation. -+ * -+ * This code is distributed in the hope that it will be useful, but WITHOUT -+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -+ * version 2 for more details (a copy is included in the LICENSE file that -+ * accompanied this code). -+ * -+ * You should have received a copy of the GNU General Public License version -+ * 2 along with this work; if not, write to the Free Software Foundation, -+ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. -+ * -+ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA -+ * or visit www.oracle.com if you need additional information or have any -+ * questions. -+ * -+ */ -+ -+#ifndef CPU_MIPS_VM_TEMPLATETABLE_MIPS_64_HPP -+#define CPU_MIPS_VM_TEMPLATETABLE_MIPS_64_HPP -+ -+ static void prepare_invoke(int byte_no, -+ Register method, // linked method (or i-klass) -+ Register index = noreg, // itable index, MethodType, etc. -+ Register recv = noreg, // if caller wants to see it -+ Register flags = noreg // if caller wants to test it -+ ); -+ static void invokevirtual_helper(Register index, Register recv, -+ Register flags); -+ static void volatile_barrier(); -+ -+ // Helpers -+ static void index_check(Register array, Register index); -+ static void index_check_without_pop(Register array, Register index); -+ -+#endif // CPU_MIPS_VM_TEMPLATETABLE_MIPS_64_HPP -diff --git a/src/hotspot/cpu/mips/templateTable_mips_64.cpp b/src/hotspot/cpu/mips/templateTable_mips_64.cpp -new file mode 100644 -index 00000000000..bbf95f45225 ---- /dev/null -+++ b/src/hotspot/cpu/mips/templateTable_mips_64.cpp +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/mips/templateTable_mips_64.cpp b/src/hotspot/cpu/mips/templateTable_mips_64.cpp +--- a/src/hotspot/cpu/mips/templateTable_mips_64.cpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/mips/templateTable_mips_64.cpp 2024-01-31 14:01:11.610762293 +0800 @@ -0,0 +1,4613 @@ +/* + * Copyright (c) 2003, 2013, Oracle and/or its affiliates. All rights reserved. @@ -109499,11 +108695,56 @@ index 00000000000..bbf95f45225 + __ daddu(SP, SP, AT); + __ sync(); +} -diff --git a/src/hotspot/cpu/mips/universalNativeInvoker_mips_64.cpp b/src/hotspot/cpu/mips/universalNativeInvoker_mips_64.cpp -new file mode 100644 -index 00000000000..87f6a113268 ---- /dev/null -+++ b/src/hotspot/cpu/mips/universalNativeInvoker_mips_64.cpp +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/mips/templateTable_mips.hpp b/src/hotspot/cpu/mips/templateTable_mips.hpp +--- a/src/hotspot/cpu/mips/templateTable_mips.hpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/mips/templateTable_mips.hpp 2024-01-31 14:01:11.610762293 +0800 +@@ -0,0 +1,43 @@ ++/* ++ * Copyright (c) 2003, 2012, Oracle and/or its affiliates. All rights reserved. ++ * Copyright (c) 2015, 2018, Loongson Technology. All rights reserved. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ * ++ */ ++ ++#ifndef CPU_MIPS_VM_TEMPLATETABLE_MIPS_64_HPP ++#define CPU_MIPS_VM_TEMPLATETABLE_MIPS_64_HPP ++ ++ static void prepare_invoke(int byte_no, ++ Register method, // linked method (or i-klass) ++ Register index = noreg, // itable index, MethodType, etc. ++ Register recv = noreg, // if caller wants to see it ++ Register flags = noreg // if caller wants to test it ++ ); ++ static void invokevirtual_helper(Register index, Register recv, ++ Register flags); ++ static void volatile_barrier(); ++ ++ // Helpers ++ static void index_check(Register array, Register index); ++ static void index_check_without_pop(Register array, Register index); ++ ++#endif // CPU_MIPS_VM_TEMPLATETABLE_MIPS_64_HPP +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/mips/universalNativeInvoker_mips_64.cpp b/src/hotspot/cpu/mips/universalNativeInvoker_mips_64.cpp +--- a/src/hotspot/cpu/mips/universalNativeInvoker_mips_64.cpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/mips/universalNativeInvoker_mips_64.cpp 2024-01-31 14:01:11.610762293 +0800 @@ -0,0 +1,32 @@ +/* + * Copyright (c) 2020, Red Hat, Inc. All rights reserved. @@ -109537,11 +108778,9 @@ index 00000000000..87f6a113268 + Unimplemented(); + return nullptr; +} -diff --git a/src/hotspot/cpu/mips/universalUpcallHandler_mips_64.cpp b/src/hotspot/cpu/mips/universalUpcallHandler_mips_64.cpp -new file mode 100644 -index 00000000000..7586b084868 ---- /dev/null -+++ b/src/hotspot/cpu/mips/universalUpcallHandler_mips_64.cpp +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/mips/universalUpcallHandler_mips_64.cpp b/src/hotspot/cpu/mips/universalUpcallHandler_mips_64.cpp +--- a/src/hotspot/cpu/mips/universalUpcallHandler_mips_64.cpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/mips/universalUpcallHandler_mips_64.cpp 2024-01-31 14:01:11.610762293 +0800 @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2020, Red Hat, Inc. All rights reserved. @@ -109584,11 +108823,171 @@ index 00000000000..7586b084868 +bool ProgrammableUpcallHandler::supports_optimized_upcalls() { + return false; +} -diff --git a/src/hotspot/cpu/mips/vmStructs_mips.hpp b/src/hotspot/cpu/mips/vmStructs_mips.hpp -new file mode 100644 -index 00000000000..6939914356d ---- /dev/null -+++ b/src/hotspot/cpu/mips/vmStructs_mips.hpp +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/mips/vmreg_mips.cpp b/src/hotspot/cpu/mips/vmreg_mips.cpp +--- a/src/hotspot/cpu/mips/vmreg_mips.cpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/mips/vmreg_mips.cpp 2024-01-31 14:01:11.610762293 +0800 +@@ -0,0 +1,56 @@ ++/* ++ * Copyright (c) 2006, 2012, Oracle and/or its affiliates. All rights reserved. ++ * Copyright (c) 2015, 2022, Loongson Technology. All rights reserved. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ * ++ */ ++ ++#include "precompiled.hpp" ++#include "asm/assembler.hpp" ++#include "code/vmreg.hpp" ++ ++ ++ ++void VMRegImpl::set_regName() { ++ Register reg = ::as_Register(0); ++ int i; ++ for (i = 0; i < ConcreteRegisterImpl::max_gpr ; ) { ++ regName[i++] = reg->name(); ++ regName[i++] = reg->name(); ++ reg = reg->successor(); ++ } ++ ++ FloatRegister freg = ::as_FloatRegister(0); ++ for ( ; i < ConcreteRegisterImpl::max_fpr ; ) { ++ regName[i++] = freg->name(); ++ regName[i++] = freg->name(); ++ freg = freg->successor(); ++ } ++ ++ for ( ; i < ConcreteRegisterImpl::number_of_registers ; i ++ ) { ++ regName[i] = "NON-GPR-FPR"; ++ } ++} ++ ++VMReg VMRegImpl::vmStorageToVMReg(int type, int index) { ++ Unimplemented(); ++ return VMRegImpl::Bad(); ++} +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/mips/vmreg_mips.hpp b/src/hotspot/cpu/mips/vmreg_mips.hpp +--- a/src/hotspot/cpu/mips/vmreg_mips.hpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/mips/vmreg_mips.hpp 2024-01-31 14:01:11.610762293 +0800 +@@ -0,0 +1,56 @@ ++/* ++ * Copyright (c) 2006, 2010, Oracle and/or its affiliates. All rights reserved. ++ * Copyright (c) 2015, 2022, Loongson Technology. All rights reserved. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ * ++ */ ++ ++#ifndef CPU_MIPS_VM_VMREG_MIPS_HPP ++#define CPU_MIPS_VM_VMREG_MIPS_HPP ++ ++inline Register as_Register() { ++ assert( is_Register(), "must be"); ++ return ::as_Register(value() >> 1); ++} ++ ++inline FloatRegister as_FloatRegister() { ++ assert( is_FloatRegister(), "must be" ); ++ assert( is_even(value()), "must be" ); ++ return ::as_FloatRegister((value() - ConcreteRegisterImpl::max_gpr) >> 1); ++} ++ ++inline bool is_Register() { ++ return (unsigned int) value() < (unsigned int) ConcreteRegisterImpl::max_gpr; ++} ++ ++inline bool is_FloatRegister() { ++ return value() >= ConcreteRegisterImpl::max_gpr && value() < ConcreteRegisterImpl::max_fpr; ++} ++ ++inline bool is_concrete() { ++ assert(is_reg(), "must be"); ++ if(is_Register()) return true; ++ if(is_FloatRegister()) return true; ++ assert(false, "what register?"); ++ return false; ++} ++ ++#endif // CPU_MIPS_VM_VMREG_MIPS_HPP +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/mips/vmreg_mips.inline.hpp b/src/hotspot/cpu/mips/vmreg_mips.inline.hpp +--- a/src/hotspot/cpu/mips/vmreg_mips.inline.hpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/mips/vmreg_mips.inline.hpp 2024-01-31 14:01:11.610762293 +0800 +@@ -0,0 +1,38 @@ ++/* ++ * Copyright (c) 2006, 2012, Oracle and/or its affiliates. All rights reserved. ++ * Copyright (c) 2015, 2022, Loongson Technology. All rights reserved. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ * ++ */ ++ ++#ifndef CPU_MIPS_VM_VMREG_MIPS_INLINE_HPP ++#define CPU_MIPS_VM_VMREG_MIPS_INLINE_HPP ++ ++inline VMReg RegisterImpl::as_VMReg() { ++ if( this==noreg ) return VMRegImpl::Bad(); ++ return VMRegImpl::as_VMReg(encoding() << 1 ); ++} ++ ++inline VMReg FloatRegisterImpl::as_VMReg() { ++ return VMRegImpl::as_VMReg((encoding() << 1) + ConcreteRegisterImpl::max_gpr); ++} ++ ++#endif // CPU_MIPS_VM_VMREG_MIPS_INLINE_HPP +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/mips/vmStructs_mips.hpp b/src/hotspot/cpu/mips/vmStructs_mips.hpp +--- a/src/hotspot/cpu/mips/vmStructs_mips.hpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/mips/vmStructs_mips.hpp 2024-01-31 14:01:11.610762293 +0800 @@ -0,0 +1,68 @@ +/* + * Copyright (c) 2001, 2013, Oracle and/or its affiliates. All rights reserved. @@ -109658,11 +109057,9 @@ index 00000000000..6939914356d + /* be present there) */ + +#endif // CPU_MIPS_VM_VMSTRUCTS_MIPS_HPP -diff --git a/src/hotspot/cpu/mips/vm_version_ext_mips.cpp b/src/hotspot/cpu/mips/vm_version_ext_mips.cpp -new file mode 100644 -index 00000000000..d3f07078570 ---- /dev/null -+++ b/src/hotspot/cpu/mips/vm_version_ext_mips.cpp +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/mips/vm_version_ext_mips.cpp b/src/hotspot/cpu/mips/vm_version_ext_mips.cpp +--- a/src/hotspot/cpu/mips/vm_version_ext_mips.cpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/mips/vm_version_ext_mips.cpp 2024-01-31 14:01:11.610762293 +0800 @@ -0,0 +1,90 @@ +/* + * Copyright (c) 2013, 2018, Oracle and/or its affiliates. All rights reserved. @@ -109754,11 +109151,9 @@ index 00000000000..d3f07078570 + strncpy(tmp, _cpu_desc, CPU_DETAILED_DESC_BUF_SIZE); + return tmp; +} -diff --git a/src/hotspot/cpu/mips/vm_version_ext_mips.hpp b/src/hotspot/cpu/mips/vm_version_ext_mips.hpp -new file mode 100644 -index 00000000000..ffdcff06777 ---- /dev/null -+++ b/src/hotspot/cpu/mips/vm_version_ext_mips.hpp +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/mips/vm_version_ext_mips.hpp b/src/hotspot/cpu/mips/vm_version_ext_mips.hpp +--- a/src/hotspot/cpu/mips/vm_version_ext_mips.hpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/mips/vm_version_ext_mips.hpp 2024-01-31 14:01:11.610762293 +0800 @@ -0,0 +1,54 @@ +/* + * Copyright (c) 2016, 2018, Oracle and/or its affiliates. All rights reserved. @@ -109814,11 +109209,9 @@ index 00000000000..ffdcff06777 +}; + +#endif // CPU_MIPS_VM_VM_VERSION_EXT_MIPS_HPP -diff --git a/src/hotspot/cpu/mips/vm_version_mips.cpp b/src/hotspot/cpu/mips/vm_version_mips.cpp -new file mode 100644 -index 00000000000..8625bc70075 ---- /dev/null -+++ b/src/hotspot/cpu/mips/vm_version_mips.cpp +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/mips/vm_version_mips.cpp b/src/hotspot/cpu/mips/vm_version_mips.cpp +--- a/src/hotspot/cpu/mips/vm_version_mips.cpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/mips/vm_version_mips.cpp 2024-01-31 14:01:11.610762293 +0800 @@ -0,0 +1,523 @@ +/* + * Copyright (c) 1997, 2014, Oracle and/or its affiliates. All rights reserved. @@ -110343,11 +109736,9 @@ index 00000000000..8625bc70075 + + get_processor_features(); +} -diff --git a/src/hotspot/cpu/mips/vm_version_mips.hpp b/src/hotspot/cpu/mips/vm_version_mips.hpp -new file mode 100644 -index 00000000000..30c7b5a934d ---- /dev/null -+++ b/src/hotspot/cpu/mips/vm_version_mips.hpp +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/mips/vm_version_mips.hpp b/src/hotspot/cpu/mips/vm_version_mips.hpp +--- a/src/hotspot/cpu/mips/vm_version_mips.hpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/mips/vm_version_mips.hpp 2024-01-31 14:01:11.610762293 +0800 @@ -0,0 +1,218 @@ +/* + * Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved. @@ -110567,179 +109958,9 @@ index 00000000000..30c7b5a934d +}; + +#endif // CPU_MIPS_VM_VM_VERSION_MIPS_HPP -diff --git a/src/hotspot/cpu/mips/vmreg_mips.cpp b/src/hotspot/cpu/mips/vmreg_mips.cpp -new file mode 100644 -index 00000000000..95dbd17f1a8 ---- /dev/null -+++ b/src/hotspot/cpu/mips/vmreg_mips.cpp -@@ -0,0 +1,56 @@ -+/* -+ * Copyright (c) 2006, 2012, Oracle and/or its affiliates. All rights reserved. -+ * Copyright (c) 2015, 2022, Loongson Technology. All rights reserved. -+ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. -+ * -+ * This code is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 only, as -+ * published by the Free Software Foundation. -+ * -+ * This code is distributed in the hope that it will be useful, but WITHOUT -+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -+ * version 2 for more details (a copy is included in the LICENSE file that -+ * accompanied this code). -+ * -+ * You should have received a copy of the GNU General Public License version -+ * 2 along with this work; if not, write to the Free Software Foundation, -+ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. -+ * -+ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA -+ * or visit www.oracle.com if you need additional information or have any -+ * questions. -+ * -+ */ -+ -+#include "precompiled.hpp" -+#include "asm/assembler.hpp" -+#include "code/vmreg.hpp" -+ -+ -+ -+void VMRegImpl::set_regName() { -+ Register reg = ::as_Register(0); -+ int i; -+ for (i = 0; i < ConcreteRegisterImpl::max_gpr ; ) { -+ regName[i++] = reg->name(); -+ regName[i++] = reg->name(); -+ reg = reg->successor(); -+ } -+ -+ FloatRegister freg = ::as_FloatRegister(0); -+ for ( ; i < ConcreteRegisterImpl::max_fpr ; ) { -+ regName[i++] = freg->name(); -+ regName[i++] = freg->name(); -+ freg = freg->successor(); -+ } -+ -+ for ( ; i < ConcreteRegisterImpl::number_of_registers ; i ++ ) { -+ regName[i] = "NON-GPR-FPR"; -+ } -+} -+ -+VMReg VMRegImpl::vmStorageToVMReg(int type, int index) { -+ Unimplemented(); -+ return VMRegImpl::Bad(); -+} -diff --git a/src/hotspot/cpu/mips/vmreg_mips.hpp b/src/hotspot/cpu/mips/vmreg_mips.hpp -new file mode 100644 -index 00000000000..8ccc8c513c8 ---- /dev/null -+++ b/src/hotspot/cpu/mips/vmreg_mips.hpp -@@ -0,0 +1,56 @@ -+/* -+ * Copyright (c) 2006, 2010, Oracle and/or its affiliates. All rights reserved. -+ * Copyright (c) 2015, 2022, Loongson Technology. All rights reserved. -+ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. -+ * -+ * This code is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 only, as -+ * published by the Free Software Foundation. -+ * -+ * This code is distributed in the hope that it will be useful, but WITHOUT -+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -+ * version 2 for more details (a copy is included in the LICENSE file that -+ * accompanied this code). -+ * -+ * You should have received a copy of the GNU General Public License version -+ * 2 along with this work; if not, write to the Free Software Foundation, -+ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. -+ * -+ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA -+ * or visit www.oracle.com if you need additional information or have any -+ * questions. -+ * -+ */ -+ -+#ifndef CPU_MIPS_VM_VMREG_MIPS_HPP -+#define CPU_MIPS_VM_VMREG_MIPS_HPP -+ -+inline Register as_Register() { -+ assert( is_Register(), "must be"); -+ return ::as_Register(value() >> 1); -+} -+ -+inline FloatRegister as_FloatRegister() { -+ assert( is_FloatRegister(), "must be" ); -+ assert( is_even(value()), "must be" ); -+ return ::as_FloatRegister((value() - ConcreteRegisterImpl::max_gpr) >> 1); -+} -+ -+inline bool is_Register() { -+ return (unsigned int) value() < (unsigned int) ConcreteRegisterImpl::max_gpr; -+} -+ -+inline bool is_FloatRegister() { -+ return value() >= ConcreteRegisterImpl::max_gpr && value() < ConcreteRegisterImpl::max_fpr; -+} -+ -+inline bool is_concrete() { -+ assert(is_reg(), "must be"); -+ if(is_Register()) return true; -+ if(is_FloatRegister()) return true; -+ assert(false, "what register?"); -+ return false; -+} -+ -+#endif // CPU_MIPS_VM_VMREG_MIPS_HPP -diff --git a/src/hotspot/cpu/mips/vmreg_mips.inline.hpp b/src/hotspot/cpu/mips/vmreg_mips.inline.hpp -new file mode 100644 -index 00000000000..12ad7361aa5 ---- /dev/null -+++ b/src/hotspot/cpu/mips/vmreg_mips.inline.hpp -@@ -0,0 +1,38 @@ -+/* -+ * Copyright (c) 2006, 2012, Oracle and/or its affiliates. All rights reserved. -+ * Copyright (c) 2015, 2022, Loongson Technology. All rights reserved. -+ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. -+ * -+ * This code is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 only, as -+ * published by the Free Software Foundation. -+ * -+ * This code is distributed in the hope that it will be useful, but WITHOUT -+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -+ * version 2 for more details (a copy is included in the LICENSE file that -+ * accompanied this code). -+ * -+ * You should have received a copy of the GNU General Public License version -+ * 2 along with this work; if not, write to the Free Software Foundation, -+ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. -+ * -+ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA -+ * or visit www.oracle.com if you need additional information or have any -+ * questions. -+ * -+ */ -+ -+#ifndef CPU_MIPS_VM_VMREG_MIPS_INLINE_HPP -+#define CPU_MIPS_VM_VMREG_MIPS_INLINE_HPP -+ -+inline VMReg RegisterImpl::as_VMReg() { -+ if( this==noreg ) return VMRegImpl::Bad(); -+ return VMRegImpl::as_VMReg(encoding() << 1 ); -+} -+ -+inline VMReg FloatRegisterImpl::as_VMReg() { -+ return VMRegImpl::as_VMReg((encoding() << 1) + ConcreteRegisterImpl::max_gpr); -+} -+ -+#endif // CPU_MIPS_VM_VMREG_MIPS_INLINE_HPP -diff --git a/src/hotspot/cpu/mips/vtableStubs_mips_64.cpp b/src/hotspot/cpu/mips/vtableStubs_mips_64.cpp -new file mode 100644 -index 00000000000..f373aac45c2 ---- /dev/null -+++ b/src/hotspot/cpu/mips/vtableStubs_mips_64.cpp +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/mips/vtableStubs_mips_64.cpp b/src/hotspot/cpu/mips/vtableStubs_mips_64.cpp +--- a/src/hotspot/cpu/mips/vtableStubs_mips_64.cpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/cpu/mips/vtableStubs_mips_64.cpp 2024-01-31 14:01:11.610762293 +0800 @@ -0,0 +1,348 @@ +/* + * Copyright (c) 2003, 2014, Oracle and/or its affiliates. All rights reserved. @@ -111089,133 +110310,10 @@ index 00000000000..f373aac45c2 + const unsigned int icache_line_size = wordSize; + return icache_line_size; +} -diff --git a/src/hotspot/cpu/ppc/c1_LIRAssembler_ppc.cpp b/src/hotspot/cpu/ppc/c1_LIRAssembler_ppc.cpp -index af9a856ae08..dc2acbe8b15 100644 ---- a/src/hotspot/cpu/ppc/c1_LIRAssembler_ppc.cpp -+++ b/src/hotspot/cpu/ppc/c1_LIRAssembler_ppc.cpp -@@ -506,6 +506,9 @@ void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) { - } - } - -+void LIR_Assembler::emit_opCmpBranch(LIR_OpCmpBranch* op) { -+ ShouldNotReachHere(); -+} - - void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) { - Bytecodes::Code code = op->bytecode(); -@@ -1609,6 +1612,10 @@ void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, L - __ bind(skip); - } - -+void LIR_Assembler::cmp_cmove(LIR_Condition condition, LIR_Opr left, LIR_Opr right, LIR_Opr src1, LIR_Opr src2, LIR_Opr result, BasicType type) { -+ ShouldNotReachHere(); -+} -+ - - void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, - CodeEmitInfo* info, bool pop_fpu_stack) { -diff --git a/src/hotspot/cpu/ppc/c1_LIRGenerator_ppc.cpp b/src/hotspot/cpu/ppc/c1_LIRGenerator_ppc.cpp -index 2c685920367..c0def81ce44 100644 ---- a/src/hotspot/cpu/ppc/c1_LIRGenerator_ppc.cpp -+++ b/src/hotspot/cpu/ppc/c1_LIRGenerator_ppc.cpp -@@ -275,21 +275,29 @@ void LIRGenerator::increment_counter(LIR_Address* addr, int step) { - __ move(temp, addr); - } - -- --void LIRGenerator::cmp_mem_int(LIR_Condition condition, LIR_Opr base, int disp, int c, CodeEmitInfo* info) { -+template -+void LIRGenerator::cmp_mem_int_branch(LIR_Condition condition, LIR_Opr base, int disp, int c, T tgt, CodeEmitInfo* info) { - LIR_Opr tmp = FrameMap::R0_opr; - __ load(new LIR_Address(base, disp, T_INT), tmp, info); -- __ cmp(condition, tmp, c); -+ __ cmp_branch(condition, tmp, c, tgt); - } - -+// Explicit instantiation for all supported types. -+template void LIRGenerator::cmp_mem_int_branch(LIR_Condition, LIR_Opr, int, int, Label*, CodeEmitInfo*); -+template void LIRGenerator::cmp_mem_int_branch(LIR_Condition, LIR_Opr, int, int, BlockBegin*, CodeEmitInfo*); -+template void LIRGenerator::cmp_mem_int_branch(LIR_Condition, LIR_Opr, int, int, CodeStub*, CodeEmitInfo*); - --void LIRGenerator::cmp_reg_mem(LIR_Condition condition, LIR_Opr reg, LIR_Opr base, -- int disp, BasicType type, CodeEmitInfo* info) { -+template -+void LIRGenerator::cmp_reg_mem_branch(LIR_Condition condition, LIR_Opr reg, LIR_Opr base, int disp, BasicType type, T tgt, CodeEmitInfo* info) { - LIR_Opr tmp = FrameMap::R0_opr; - __ load(new LIR_Address(base, disp, type), tmp, info); -- __ cmp(condition, reg, tmp); -+ __ cmp_branch(condition, reg, tmp, tgt); - } - -+// Explicit instantiation for all supported types. -+template void LIRGenerator::cmp_reg_mem_branch(LIR_Condition, LIR_Opr, LIR_Opr, int, BasicType, Label*, CodeEmitInfo*); -+template void LIRGenerator::cmp_reg_mem_branch(LIR_Condition, LIR_Opr, LIR_Opr, int, BasicType, BlockBegin*, CodeEmitInfo*); -+template void LIRGenerator::cmp_reg_mem_branch(LIR_Condition, LIR_Opr, LIR_Opr, int, BasicType, CodeStub*, CodeEmitInfo*); - - bool LIRGenerator::strength_reduce_multiply(LIR_Opr left, jint c, LIR_Opr result, LIR_Opr tmp) { - assert(left != result, "should be different registers"); -diff --git a/src/hotspot/cpu/ppc/c1_LIR_ppc.cpp b/src/hotspot/cpu/ppc/c1_LIR_ppc.cpp -index fb234e82985..8f77a103edb 100644 ---- a/src/hotspot/cpu/ppc/c1_LIR_ppc.cpp -+++ b/src/hotspot/cpu/ppc/c1_LIR_ppc.cpp -@@ -62,3 +62,24 @@ void LIR_Address::verify() const { - #endif - } - #endif // PRODUCT -+ -+template -+void LIR_List::cmp_branch(LIR_Condition condition, LIR_Opr left, LIR_Opr right, T tgt, CodeEmitInfo* info) { -+ cmp(condition, left, right, info); -+ branch(condition, tgt); -+} -+ -+// Explicit instantiation for all supported types. -+template void LIR_List::cmp_branch(LIR_Condition, LIR_Opr, LIR_Opr, Label*, CodeEmitInfo*); -+template void LIR_List::cmp_branch(LIR_Condition, LIR_Opr, LIR_Opr, BlockBegin*, CodeEmitInfo*); -+template void LIR_List::cmp_branch(LIR_Condition, LIR_Opr, LIR_Opr, CodeStub*, CodeEmitInfo*); -+ -+void LIR_List::cmp_branch(LIR_Condition condition, LIR_Opr left, LIR_Opr right, BlockBegin* block, BlockBegin* unordered) { -+ cmp(condition, left, right); -+ branch(condition, block, unordered); -+} -+ -+void LIR_List::cmp_cmove(LIR_Condition condition, LIR_Opr left, LIR_Opr right, LIR_Opr src1, LIR_Opr src2, LIR_Opr dst, BasicType type) { -+ cmp(condition, left, right); -+ cmove(condition, src1, src2, dst, type); -+} -diff --git a/src/hotspot/cpu/ppc/gc/z/zBarrierSetAssembler_ppc.cpp b/src/hotspot/cpu/ppc/gc/z/zBarrierSetAssembler_ppc.cpp -index 17fc8e5078e..27e431c2c61 100644 ---- a/src/hotspot/cpu/ppc/gc/z/zBarrierSetAssembler_ppc.cpp -+++ b/src/hotspot/cpu/ppc/gc/z/zBarrierSetAssembler_ppc.cpp -@@ -292,7 +292,8 @@ void ZBarrierSetAssembler::try_resolve_jobject_in_native(MacroAssembler* masm, R - // Code emitted by LIR node "LIR_OpZLoadBarrierTest" which in turn is emitted by ZBarrierSetC1::load_barrier. - // The actual compare and branch instructions are represented as stand-alone LIR nodes. - void ZBarrierSetAssembler::generate_c1_load_barrier_test(LIR_Assembler* ce, -- LIR_Opr ref) const { -+ LIR_Opr ref, -+ LIR_Opr res) const { - __ block_comment("load_barrier_test (zgc) {"); - - __ ld(R0, in_bytes(ZThreadLocalData::address_bad_mask_offset()), R16_thread); -diff --git a/src/hotspot/cpu/ppc/gc/z/zBarrierSetAssembler_ppc.hpp b/src/hotspot/cpu/ppc/gc/z/zBarrierSetAssembler_ppc.hpp -index e2ff1bf53ae..4957e73ae22 100644 ---- a/src/hotspot/cpu/ppc/gc/z/zBarrierSetAssembler_ppc.hpp -+++ b/src/hotspot/cpu/ppc/gc/z/zBarrierSetAssembler_ppc.hpp -@@ -67,7 +67,8 @@ public: - - #ifdef COMPILER1 - void generate_c1_load_barrier_test(LIR_Assembler* ce, -- LIR_Opr ref) const; -+ LIR_Opr ref, -+ LIR_Opr res) const; - - void generate_c1_load_barrier_stub(LIR_Assembler* ce, - ZLoadBarrierStubC1* stub) const; -diff --git a/src/hotspot/cpu/ppc/gc/z/zGlobals_ppc.hpp b/src/hotspot/cpu/ppc/gc/z/zGlobals_ppc.hpp -index 3657b16fc1a..a2aab225743 100644 ---- a/src/hotspot/cpu/ppc/gc/z/zGlobals_ppc.hpp -+++ b/src/hotspot/cpu/ppc/gc/z/zGlobals_ppc.hpp -@@ -30,6 +30,8 @@ const size_t ZPlatformGranuleSizeShift = 21; // 2MB +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/cpu/ppc/gc/z/zGlobals_ppc.hpp b/src/hotspot/cpu/ppc/gc/z/zGlobals_ppc.hpp +--- a/src/hotspot/cpu/ppc/gc/z/zGlobals_ppc.hpp 2024-01-10 05:18:15.000000000 +0800 ++++ b/src/hotspot/cpu/ppc/gc/z/zGlobals_ppc.hpp 2024-01-31 14:01:11.617429024 +0800 +@@ -30,6 +30,8 @@ const size_t ZPlatformHeapViews = 3; const size_t ZPlatformCacheLineSize = DEFAULT_CACHE_LINE_SIZE; @@ -111224,229 +110322,9 @@ index 3657b16fc1a..a2aab225743 100644 size_t ZPlatformAddressOffsetBits(); size_t ZPlatformAddressMetadataShift(); -diff --git a/src/hotspot/cpu/s390/c1_LIRAssembler_s390.cpp b/src/hotspot/cpu/s390/c1_LIRAssembler_s390.cpp -index a7d5a4a1c42..d9a3c4ae5ee 100644 ---- a/src/hotspot/cpu/s390/c1_LIRAssembler_s390.cpp -+++ b/src/hotspot/cpu/s390/c1_LIRAssembler_s390.cpp -@@ -395,6 +395,9 @@ void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) { - } - } - -+void LIR_Assembler::emit_opCmpBranch(LIR_OpCmpBranch* op) { -+ ShouldNotReachHere(); -+} - - void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) { - LIR_Opr src = op->in_opr(); -@@ -1501,6 +1504,10 @@ void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, L - } - } - -+void LIR_Assembler::cmp_cmove(LIR_Condition condition, LIR_Opr left, LIR_Opr right, LIR_Opr src1, LIR_Opr src2, LIR_Opr result, BasicType type) { -+ ShouldNotReachHere(); -+} -+ - void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, - CodeEmitInfo* info, bool pop_fpu_stack) { - assert(info == NULL, "should never be used, idiv/irem and ldiv/lrem not handled by this method"); -diff --git a/src/hotspot/cpu/s390/c1_LIRGenerator_s390.cpp b/src/hotspot/cpu/s390/c1_LIRGenerator_s390.cpp -index c6d5085079f..755b3738b3f 100644 ---- a/src/hotspot/cpu/s390/c1_LIRGenerator_s390.cpp -+++ b/src/hotspot/cpu/s390/c1_LIRGenerator_s390.cpp -@@ -214,16 +214,29 @@ void LIRGenerator::increment_counter(LIR_Address* addr, int step) { - __ add((LIR_Opr)addr, LIR_OprFact::intConst(step), (LIR_Opr)addr); - } - --void LIRGenerator::cmp_mem_int(LIR_Condition condition, LIR_Opr base, int disp, int c, CodeEmitInfo* info) { -+template -+void LIRGenerator::cmp_mem_int_branch(LIR_Condition condition, LIR_Opr base, int disp, int c, T tgt, CodeEmitInfo* info) { - LIR_Opr scratch = FrameMap::Z_R1_opr; - __ load(new LIR_Address(base, disp, T_INT), scratch, info); -- __ cmp(condition, scratch, c); -+ __ cmp_branch(condition, scratch, c, tgt); - } - --void LIRGenerator::cmp_reg_mem(LIR_Condition condition, LIR_Opr reg, LIR_Opr base, int disp, BasicType type, CodeEmitInfo* info) { -+// Explicit instantiation for all supported types. -+template void LIRGenerator::cmp_mem_int_branch(LIR_Condition, LIR_Opr, int, int, Label*, CodeEmitInfo*); -+template void LIRGenerator::cmp_mem_int_branch(LIR_Condition, LIR_Opr, int, int, BlockBegin*, CodeEmitInfo*); -+template void LIRGenerator::cmp_mem_int_branch(LIR_Condition, LIR_Opr, int, int, CodeStub*, CodeEmitInfo*); -+ -+template -+void LIRGenerator::cmp_reg_mem_branch(LIR_Condition condition, LIR_Opr reg, LIR_Opr base, int disp, BasicType type, T tgt, CodeEmitInfo* info) { - __ cmp_reg_mem(condition, reg, new LIR_Address(base, disp, type), info); -+ __ branch(condition, tgt); - } - -+// Explicit instantiation for all supported types. -+template void LIRGenerator::cmp_reg_mem_branch(LIR_Condition, LIR_Opr, LIR_Opr, int, BasicType, Label*, CodeEmitInfo*); -+template void LIRGenerator::cmp_reg_mem_branch(LIR_Condition, LIR_Opr, LIR_Opr, int, BasicType, BlockBegin*, CodeEmitInfo*); -+template void LIRGenerator::cmp_reg_mem_branch(LIR_Condition, LIR_Opr, LIR_Opr, int, BasicType, CodeStub*, CodeEmitInfo*); -+ - bool LIRGenerator::strength_reduce_multiply(LIR_Opr left, jint c, LIR_Opr result, LIR_Opr tmp) { - if (tmp->is_valid()) { - if (is_power_of_2(c + 1)) { -diff --git a/src/hotspot/cpu/s390/c1_LIR_s390.cpp b/src/hotspot/cpu/s390/c1_LIR_s390.cpp -index 3c46915e475..9fcc1a8aedb 100644 ---- a/src/hotspot/cpu/s390/c1_LIR_s390.cpp -+++ b/src/hotspot/cpu/s390/c1_LIR_s390.cpp -@@ -56,3 +56,23 @@ void LIR_Address::verify() const { - } - #endif // PRODUCT - -+template -+void LIR_List::cmp_branch(LIR_Condition condition, LIR_Opr left, LIR_Opr right, T tgt, CodeEmitInfo* info) { -+ cmp(condition, left, right, info); -+ branch(condition, tgt); -+} -+ -+// Explicit instantiation for all supported types. -+template void LIR_List::cmp_branch(LIR_Condition, LIR_Opr, LIR_Opr, Label*, CodeEmitInfo*); -+template void LIR_List::cmp_branch(LIR_Condition, LIR_Opr, LIR_Opr, BlockBegin*, CodeEmitInfo*); -+template void LIR_List::cmp_branch(LIR_Condition, LIR_Opr, LIR_Opr, CodeStub*, CodeEmitInfo*); -+ -+void LIR_List::cmp_branch(LIR_Condition condition, LIR_Opr left, LIR_Opr right, BlockBegin* block, BlockBegin* unordered) { -+ cmp(condition, left, right); -+ branch(condition, block, unordered); -+} -+ -+void LIR_List::cmp_cmove(LIR_Condition condition, LIR_Opr left, LIR_Opr right, LIR_Opr src1, LIR_Opr src2, LIR_Opr dst, BasicType type) { -+ cmp(condition, left, right); -+ cmove(condition, src1, src2, dst, type); -+} -diff --git a/src/hotspot/cpu/x86/c1_LIRAssembler_x86.cpp b/src/hotspot/cpu/x86/c1_LIRAssembler_x86.cpp -index e2454f32481..ee89adfd72e 100644 ---- a/src/hotspot/cpu/x86/c1_LIRAssembler_x86.cpp -+++ b/src/hotspot/cpu/x86/c1_LIRAssembler_x86.cpp -@@ -1459,6 +1459,10 @@ void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) { - } - } - -+void LIR_Assembler::emit_opCmpBranch(LIR_OpCmpBranch* op) { -+ ShouldNotReachHere(); -+} -+ - void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) { - LIR_Opr src = op->in_opr(); - LIR_Opr dest = op->result_opr(); -@@ -2077,6 +2081,9 @@ void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, L - } - } - -+void LIR_Assembler::cmp_cmove(LIR_Condition condition, LIR_Opr left, LIR_Opr right, LIR_Opr src1, LIR_Opr src2, LIR_Opr result, BasicType type) { -+ ShouldNotReachHere(); -+} - - void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack) { - assert(info == NULL, "should never be used, idiv/irem and ldiv/lrem not handled by this method"); -diff --git a/src/hotspot/cpu/x86/c1_LIRGenerator_x86.cpp b/src/hotspot/cpu/x86/c1_LIRGenerator_x86.cpp -index b99f16fea05..08d28f4f368 100644 ---- a/src/hotspot/cpu/x86/c1_LIRGenerator_x86.cpp -+++ b/src/hotspot/cpu/x86/c1_LIRGenerator_x86.cpp -@@ -259,15 +259,27 @@ void LIRGenerator::increment_counter(LIR_Address* addr, int step) { - __ add((LIR_Opr)addr, LIR_OprFact::intConst(step), (LIR_Opr)addr); - } - --void LIRGenerator::cmp_mem_int(LIR_Condition condition, LIR_Opr base, int disp, int c, CodeEmitInfo* info) { -+template -+void LIRGenerator::cmp_mem_int_branch(LIR_Condition condition, LIR_Opr base, int disp, int c, T tgt, CodeEmitInfo* info) { - __ cmp_mem_int(condition, base, disp, c, info); -+ __ branch(condition, tgt); - } - -+// Explicit instantiation for all supported types. -+template void LIRGenerator::cmp_mem_int_branch(LIR_Condition, LIR_Opr, int, int, Label*, CodeEmitInfo*); -+template void LIRGenerator::cmp_mem_int_branch(LIR_Condition, LIR_Opr, int, int, BlockBegin*, CodeEmitInfo*); -+template void LIRGenerator::cmp_mem_int_branch(LIR_Condition, LIR_Opr, int, int, CodeStub*, CodeEmitInfo*); - --void LIRGenerator::cmp_reg_mem(LIR_Condition condition, LIR_Opr reg, LIR_Opr base, int disp, BasicType type, CodeEmitInfo* info) { -+template -+void LIRGenerator::cmp_reg_mem_branch(LIR_Condition condition, LIR_Opr reg, LIR_Opr base, int disp, BasicType type, T tgt, CodeEmitInfo* info) { - __ cmp_reg_mem(condition, reg, new LIR_Address(base, disp, type), info); -+ __ branch(condition, tgt); - } - -+// Explicit instantiation for all supported types. -+template void LIRGenerator::cmp_reg_mem_branch(LIR_Condition, LIR_Opr, LIR_Opr, int, BasicType, Label*, CodeEmitInfo*); -+template void LIRGenerator::cmp_reg_mem_branch(LIR_Condition, LIR_Opr, LIR_Opr, int, BasicType, BlockBegin*, CodeEmitInfo*); -+template void LIRGenerator::cmp_reg_mem_branch(LIR_Condition, LIR_Opr, LIR_Opr, int, BasicType, CodeStub*, CodeEmitInfo*); - - bool LIRGenerator::strength_reduce_multiply(LIR_Opr left, jint c, LIR_Opr result, LIR_Opr tmp) { - if (tmp->is_valid() && c > 0 && c < max_jint) { -diff --git a/src/hotspot/cpu/x86/c1_LIR_x86.cpp b/src/hotspot/cpu/x86/c1_LIR_x86.cpp -index f7e3392d2e5..31cf9da42a0 100644 ---- a/src/hotspot/cpu/x86/c1_LIR_x86.cpp -+++ b/src/hotspot/cpu/x86/c1_LIR_x86.cpp -@@ -72,3 +72,24 @@ void LIR_Address::verify() const { - #endif - } - #endif // PRODUCT -+ -+template -+void LIR_List::cmp_branch(LIR_Condition condition, LIR_Opr left, LIR_Opr right, T tgt, CodeEmitInfo* info) { -+ cmp(condition, left, right, info); -+ branch(condition, tgt); -+} -+ -+// Explicit instantiation for all supported types. -+template void LIR_List::cmp_branch(LIR_Condition, LIR_Opr, LIR_Opr, Label*, CodeEmitInfo*); -+template void LIR_List::cmp_branch(LIR_Condition, LIR_Opr, LIR_Opr, BlockBegin*, CodeEmitInfo*); -+template void LIR_List::cmp_branch(LIR_Condition, LIR_Opr, LIR_Opr, CodeStub*, CodeEmitInfo*); -+ -+void LIR_List::cmp_branch(LIR_Condition condition, LIR_Opr left, LIR_Opr right, BlockBegin* block, BlockBegin* unordered) { -+ cmp(condition, left, right); -+ branch(condition, block, unordered); -+} -+ -+void LIR_List::cmp_cmove(LIR_Condition condition, LIR_Opr left, LIR_Opr right, LIR_Opr src1, LIR_Opr src2, LIR_Opr dst, BasicType type) { -+ cmp(condition, left, right); -+ cmove(condition, src1, src2, dst, type); -+} -diff --git a/src/hotspot/cpu/x86/gc/z/zBarrierSetAssembler_x86.cpp b/src/hotspot/cpu/x86/gc/z/zBarrierSetAssembler_x86.cpp -index 6fc8833f7f1..4e9d6aad41e 100644 ---- a/src/hotspot/cpu/x86/gc/z/zBarrierSetAssembler_x86.cpp -+++ b/src/hotspot/cpu/x86/gc/z/zBarrierSetAssembler_x86.cpp -@@ -266,7 +266,8 @@ void ZBarrierSetAssembler::try_resolve_jobject_in_native(MacroAssembler* masm, - #define __ ce->masm()-> - - void ZBarrierSetAssembler::generate_c1_load_barrier_test(LIR_Assembler* ce, -- LIR_Opr ref) const { -+ LIR_Opr ref, -+ LIR_Opr res) const { - __ testptr(ref->as_register(), address_bad_mask_from_thread(r15_thread)); - } - -diff --git a/src/hotspot/cpu/x86/gc/z/zBarrierSetAssembler_x86.hpp b/src/hotspot/cpu/x86/gc/z/zBarrierSetAssembler_x86.hpp -index c83783d3e3f..1fa546cfaf4 100644 ---- a/src/hotspot/cpu/x86/gc/z/zBarrierSetAssembler_x86.hpp -+++ b/src/hotspot/cpu/x86/gc/z/zBarrierSetAssembler_x86.hpp -@@ -80,7 +80,8 @@ public: - - #ifdef COMPILER1 - void generate_c1_load_barrier_test(LIR_Assembler* ce, -- LIR_Opr ref) const; -+ LIR_Opr ref, -+ LIR_Opr res) const; - - void generate_c1_load_barrier_stub(LIR_Assembler* ce, - ZLoadBarrierStubC1* stub) const; -diff --git a/src/hotspot/cpu/x86/gc/z/zGlobals_x86.hpp b/src/hotspot/cpu/x86/gc/z/zGlobals_x86.hpp -index db558d8cb2a..94f27399309 100644 ---- a/src/hotspot/cpu/x86/gc/z/zGlobals_x86.hpp -+++ b/src/hotspot/cpu/x86/gc/z/zGlobals_x86.hpp -@@ -28,6 +28,8 @@ const size_t ZPlatformGranuleSizeShift = 21; // 2MB - const size_t ZPlatformHeapViews = 3; - const size_t ZPlatformCacheLineSize = 64; - -+const bool ZPlatformLoadBarrierTestResultInRegister = false; -+ - size_t ZPlatformAddressOffsetBits(); - size_t ZPlatformAddressMetadataShift(); - -diff --git a/src/hotspot/os/linux/os_linux.cpp b/src/hotspot/os/linux/os_linux.cpp -index ba139a3f320..b0cd9816757 100644 ---- a/src/hotspot/os/linux/os_linux.cpp -+++ b/src/hotspot/os/linux/os_linux.cpp +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/os/linux/os_linux.cpp b/src/hotspot/os/linux/os_linux.cpp +--- a/src/hotspot/os/linux/os_linux.cpp 2024-01-10 05:18:15.000000000 +0800 ++++ b/src/hotspot/os/linux/os_linux.cpp 2024-01-31 14:01:11.664096134 +0800 @@ -23,6 +23,12 @@ * */ @@ -111460,7 +110338,7 @@ index ba139a3f320..b0cd9816757 100644 // no precompiled headers #include "jvm.h" #include "classfile/vmSymbols.hpp" -@@ -2410,7 +2416,7 @@ void os::print_memory_info(outputStream* st) { +@@ -2463,7 +2469,7 @@ // before "flags" so if we find a second "model name", then the // "flags" field is considered missing. static bool print_model_name_and_flags(outputStream* st, char* buf, size_t buflen) { @@ -111469,7 +110347,7 @@ index ba139a3f320..b0cd9816757 100644 // Other platforms have less repetitive cpuinfo files FILE *fp = fopen("/proc/cpuinfo", "r"); if (fp) { -@@ -2500,7 +2506,7 @@ void os::pd_print_cpu_info(outputStream* st, char* buf, size_t buflen) { +@@ -2553,7 +2559,7 @@ print_sys_devices_cpu_info(st, buf, buflen); } @@ -111478,11 +110356,9 @@ index ba139a3f320..b0cd9816757 100644 const char* search_string = "model name"; #elif defined(M68K) const char* search_string = "CPU"; -diff --git a/src/hotspot/os_cpu/linux_loongarch/assembler_linux_loongarch.cpp b/src/hotspot/os_cpu/linux_loongarch/assembler_linux_loongarch.cpp -new file mode 100644 -index 00000000000..30719a0340b ---- /dev/null -+++ b/src/hotspot/os_cpu/linux_loongarch/assembler_linux_loongarch.cpp +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/os_cpu/linux_loongarch/assembler_linux_loongarch.cpp b/src/hotspot/os_cpu/linux_loongarch/assembler_linux_loongarch.cpp +--- a/src/hotspot/os_cpu/linux_loongarch/assembler_linux_loongarch.cpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/os_cpu/linux_loongarch/assembler_linux_loongarch.cpp 2024-01-31 14:01:11.674096231 +0800 @@ -0,0 +1,24 @@ +/* + * Copyright (c) 1999, 2010, Oracle and/or its affiliates. All rights reserved. @@ -111508,15 +110384,13 @@ index 00000000000..30719a0340b + * questions. + * + */ -diff --git a/src/hotspot/os_cpu/linux_loongarch/atomic_linux_loongarch.hpp b/src/hotspot/os_cpu/linux_loongarch/atomic_linux_loongarch.hpp -new file mode 100644 -index 00000000000..4fab36f92b4 ---- /dev/null -+++ b/src/hotspot/os_cpu/linux_loongarch/atomic_linux_loongarch.hpp -@@ -0,0 +1,269 @@ +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/os_cpu/linux_loongarch/atomic_linux_loongarch.hpp b/src/hotspot/os_cpu/linux_loongarch/atomic_linux_loongarch.hpp +--- a/src/hotspot/os_cpu/linux_loongarch/atomic_linux_loongarch.hpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/os_cpu/linux_loongarch/atomic_linux_loongarch.hpp 2024-01-31 14:01:11.674096231 +0800 +@@ -0,0 +1,275 @@ +/* + * Copyright (c) 1999, 2013, Oracle and/or its affiliates. All rights reserved. -+ * Copyright (c) 2015, 2021, Loongson Technology. All rights reserved. ++ * Copyright (c) 2015, 2023, Loongson Technology. All rights reserved. + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. + * + * This code is free software; you can redistribute it and/or modify it @@ -111683,13 +110557,16 @@ index 00000000000..4fab36f92b4 + + switch (order) { + case memory_order_relaxed: ++ case memory_order_release: + asm volatile ( + "1: ll.w %[prev], %[dest] \n\t" + " bne %[prev], %[_old], 2f \n\t" + " move %[temp], %[_new] \n\t" + " sc.w %[temp], %[dest] \n\t" + " beqz %[temp], 1b \n\t" -+ "2: \n\t" ++ " b 3f \n\t" ++ "2: dbar 0x700 \n\t" ++ "3: \n\t" + : [prev] "=&r" (prev), [temp] "=&r" (temp) + : [_old] "r" (compare_value), [_new] "r" (exchange_value), [dest] "ZC" (*dest) + : "memory"); @@ -111702,7 +110579,7 @@ index 00000000000..4fab36f92b4 + " sc.w %[temp], %[dest] \n\t" + " beqz %[temp], 1b \n\t" + " b 3f \n\t" -+ "2: dbar 0 \n\t" ++ "2: dbar 0x14 \n\t" + "3: \n\t" + : [prev] "=&r" (prev), [temp] "=&r" (temp) + : [_old] "r" (compare_value), [_new] "r" (exchange_value), [dest] "ZC" (*dest) @@ -111724,13 +110601,16 @@ index 00000000000..4fab36f92b4 + + switch (order) { + case memory_order_relaxed: ++ case memory_order_release: + asm volatile ( + "1: ll.d %[prev], %[dest] \n\t" + " bne %[prev], %[_old], 2f \n\t" + " move %[temp], %[_new] \n\t" + " sc.d %[temp], %[dest] \n\t" + " beqz %[temp], 1b \n\t" -+ "2: \n\t" ++ " b 3f \n\t" ++ "2: dbar 0x700 \n\t" ++ "3: \n\t" + : [prev] "=&r" (prev), [temp] "=&r" (temp) + : [_old] "r" (compare_value), [_new] "r" (exchange_value), [dest] "ZC" (*dest) + : "memory"); @@ -111743,7 +110623,7 @@ index 00000000000..4fab36f92b4 + " sc.d %[temp], %[dest] \n\t" + " beqz %[temp], 1b \n\t" + " b 3f \n\t" -+ "2: dbar 0 \n\t" ++ "2: dbar 0x14 \n\t" + "3: \n\t" + : [prev] "=&r" (prev), [temp] "=&r" (temp) + : [_old] "r" (compare_value), [_new] "r" (exchange_value), [dest] "ZC" (*dest) @@ -111783,11 +110663,9 @@ index 00000000000..4fab36f92b4 +}; + +#endif // OS_CPU_LINUX_LOONGARCH_ATOMIC_LINUX_LOONGARCH_HPP -diff --git a/src/hotspot/os_cpu/linux_loongarch/bytes_linux_loongarch.inline.hpp b/src/hotspot/os_cpu/linux_loongarch/bytes_linux_loongarch.inline.hpp -new file mode 100644 -index 00000000000..c9f675baca4 ---- /dev/null -+++ b/src/hotspot/os_cpu/linux_loongarch/bytes_linux_loongarch.inline.hpp +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/os_cpu/linux_loongarch/bytes_linux_loongarch.inline.hpp b/src/hotspot/os_cpu/linux_loongarch/bytes_linux_loongarch.inline.hpp +--- a/src/hotspot/os_cpu/linux_loongarch/bytes_linux_loongarch.inline.hpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/os_cpu/linux_loongarch/bytes_linux_loongarch.inline.hpp 2024-01-31 14:01:11.674096231 +0800 @@ -0,0 +1,37 @@ +/* + * Copyright (c) 1999, 2010, Oracle and/or its affiliates. All rights reserved. @@ -111826,11 +110704,9 @@ index 00000000000..c9f675baca4 +inline u8 Bytes::swap_u8(u8 x) { return bswap_64(x); } + +#endif // OS_CPU_LINUX_LOONGARCH_BYTES_LINUX_LOONGARCH_INLINE_HPP -diff --git a/src/hotspot/os_cpu/linux_loongarch/copy_linux_loongarch.inline.hpp b/src/hotspot/os_cpu/linux_loongarch/copy_linux_loongarch.inline.hpp -new file mode 100644 -index 00000000000..826c1fe39ac ---- /dev/null -+++ b/src/hotspot/os_cpu/linux_loongarch/copy_linux_loongarch.inline.hpp +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/os_cpu/linux_loongarch/copy_linux_loongarch.inline.hpp b/src/hotspot/os_cpu/linux_loongarch/copy_linux_loongarch.inline.hpp +--- a/src/hotspot/os_cpu/linux_loongarch/copy_linux_loongarch.inline.hpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/os_cpu/linux_loongarch/copy_linux_loongarch.inline.hpp 2024-01-31 14:01:11.674096231 +0800 @@ -0,0 +1,125 @@ +/* + * Copyright (c) 2003, 2010, Oracle and/or its affiliates. All rights reserved. @@ -111957,11 +110833,9 @@ index 00000000000..826c1fe39ac +} + +#endif // OS_CPU_LINUX_LOONGARCH_COPY_LINUX_LOONGARCH_INLINE_HPP -diff --git a/src/hotspot/os_cpu/linux_loongarch/gc/z/zSyscall_linux_loongarch.hpp b/src/hotspot/os_cpu/linux_loongarch/gc/z/zSyscall_linux_loongarch.hpp -new file mode 100644 -index 00000000000..46d5d5a268b ---- /dev/null -+++ b/src/hotspot/os_cpu/linux_loongarch/gc/z/zSyscall_linux_loongarch.hpp +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/os_cpu/linux_loongarch/gc/z/zSyscall_linux_loongarch.hpp b/src/hotspot/os_cpu/linux_loongarch/gc/z/zSyscall_linux_loongarch.hpp +--- a/src/hotspot/os_cpu/linux_loongarch/gc/z/zSyscall_linux_loongarch.hpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/os_cpu/linux_loongarch/gc/z/zSyscall_linux_loongarch.hpp 2024-01-31 14:01:11.674096231 +0800 @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2019, 2021, Oracle and/or its affiliates. All rights reserved. @@ -112004,11 +110878,9 @@ index 00000000000..46d5d5a268b +#endif + +#endif // OS_CPU_LINUX_LOONGARCH_GC_Z_ZSYSCALL_LINUX_LOONGARCH_HPP -diff --git a/src/hotspot/os_cpu/linux_loongarch/globals_linux_loongarch.hpp b/src/hotspot/os_cpu/linux_loongarch/globals_linux_loongarch.hpp -new file mode 100644 -index 00000000000..0b5247aa0b6 ---- /dev/null -+++ b/src/hotspot/os_cpu/linux_loongarch/globals_linux_loongarch.hpp +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/os_cpu/linux_loongarch/globals_linux_loongarch.hpp b/src/hotspot/os_cpu/linux_loongarch/globals_linux_loongarch.hpp +--- a/src/hotspot/os_cpu/linux_loongarch/globals_linux_loongarch.hpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/os_cpu/linux_loongarch/globals_linux_loongarch.hpp 2024-01-31 14:01:11.674096231 +0800 @@ -0,0 +1,43 @@ +/* + * Copyright (c) 2000, 2013, Oracle and/or its affiliates. All rights reserved. @@ -112053,11 +110925,9 @@ index 00000000000..0b5247aa0b6 +define_pd_global(uintx,HeapBaseMinAddress, 2*G); + +#endif // OS_CPU_LINUX_LOONGARCH_GLOBALS_LINUX_LOONGARCH_HPP -diff --git a/src/hotspot/os_cpu/linux_loongarch/linux_loongarch.s b/src/hotspot/os_cpu/linux_loongarch/linux_loongarch.s -new file mode 100644 -index 00000000000..ebd73af0c53 ---- /dev/null -+++ b/src/hotspot/os_cpu/linux_loongarch/linux_loongarch.s +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/os_cpu/linux_loongarch/linux_loongarch.s b/src/hotspot/os_cpu/linux_loongarch/linux_loongarch.s +--- a/src/hotspot/os_cpu/linux_loongarch/linux_loongarch.s 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/os_cpu/linux_loongarch/linux_loongarch.s 2024-01-31 14:01:11.674096231 +0800 @@ -0,0 +1,25 @@ +# +# Copyright (c) 2004, 2013, Oracle and/or its affiliates. All rights reserved. @@ -112084,11 +110954,9 @@ index 00000000000..ebd73af0c53 +# + + -diff --git a/src/hotspot/os_cpu/linux_loongarch/orderAccess_linux_loongarch.hpp b/src/hotspot/os_cpu/linux_loongarch/orderAccess_linux_loongarch.hpp -new file mode 100644 -index 00000000000..23a9d27b0f4 ---- /dev/null -+++ b/src/hotspot/os_cpu/linux_loongarch/orderAccess_linux_loongarch.hpp +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/os_cpu/linux_loongarch/orderAccess_linux_loongarch.hpp b/src/hotspot/os_cpu/linux_loongarch/orderAccess_linux_loongarch.hpp +--- a/src/hotspot/os_cpu/linux_loongarch/orderAccess_linux_loongarch.hpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/os_cpu/linux_loongarch/orderAccess_linux_loongarch.hpp 2024-01-31 14:01:11.674096231 +0800 @@ -0,0 +1,52 @@ +/* + * Copyright (c) 2003, 2013, Oracle and/or its affiliates. All rights reserved. @@ -112123,31 +110991,29 @@ index 00000000000..23a9d27b0f4 +// Included in orderAccess.hpp header file. + +// Implementation of class OrderAccess. -+#define inlasm_sync() if (os::is_ActiveCoresMP()) \ ++#define inlasm_sync(v) if (os::is_ActiveCoresMP()) \ + __asm__ __volatile__ ("nop" : : : "memory"); \ + else \ -+ __asm__ __volatile__ ("dbar 0" : : : "memory"); ++ __asm__ __volatile__ ("dbar %0" : :"K"(v) : "memory"); ++#define inlasm_synci() __asm__ __volatile__ ("ibar 0" : : : "memory"); + -+inline void OrderAccess::loadload() { inlasm_sync(); } -+inline void OrderAccess::storestore() { inlasm_sync(); } -+inline void OrderAccess::loadstore() { inlasm_sync(); } -+inline void OrderAccess::storeload() { inlasm_sync(); } -+ -+inline void OrderAccess::acquire() { inlasm_sync(); } -+inline void OrderAccess::release() { inlasm_sync(); } -+inline void OrderAccess::fence() { inlasm_sync(); } -+inline void OrderAccess::cross_modify_fence_impl() { inlasm_sync(); } ++inline void OrderAccess::loadload() { inlasm_sync(0x15); } ++inline void OrderAccess::storestore() { inlasm_sync(0x1a); } ++inline void OrderAccess::loadstore() { inlasm_sync(0x16); } ++inline void OrderAccess::storeload() { inlasm_sync(0x19); } + ++inline void OrderAccess::acquire() { inlasm_sync(0x14); } ++inline void OrderAccess::release() { inlasm_sync(0x12); } ++inline void OrderAccess::fence() { inlasm_sync(0x10); } ++inline void OrderAccess::cross_modify_fence_impl() { inlasm_synci(); } + +#undef inlasm_sync + +#endif // OS_CPU_LINUX_LOONGARCH_ORDERACCESS_LINUX_LOONGARCH_HPP -diff --git a/src/hotspot/os_cpu/linux_loongarch/os_linux_loongarch.cpp b/src/hotspot/os_cpu/linux_loongarch/os_linux_loongarch.cpp -new file mode 100644 -index 00000000000..a2e4fea109c ---- /dev/null -+++ b/src/hotspot/os_cpu/linux_loongarch/os_linux_loongarch.cpp -@@ -0,0 +1,500 @@ +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/os_cpu/linux_loongarch/os_linux_loongarch.cpp b/src/hotspot/os_cpu/linux_loongarch/os_linux_loongarch.cpp +--- a/src/hotspot/os_cpu/linux_loongarch/os_linux_loongarch.cpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/os_cpu/linux_loongarch/os_linux_loongarch.cpp 2024-01-31 14:01:11.674096231 +0800 +@@ -0,0 +1,529 @@ +/* + * Copyright (c) 1999, 2014, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 2015, 2021, Loongson Technology. All rights reserved. @@ -112279,6 +111145,12 @@ index 00000000000..a2e4fea109c + intptr_t* sp; + intptr_t* fp; + address epc = fetch_frame_from_context(ucVoid, &sp, &fp); ++ if (!is_readable_pointer(epc)) { ++ // Try to recover from calling into bad memory ++ // Assume new frame has not been set up, the same as ++ // compiled frame stack bang ++ return fetch_compiled_frame_from_context(ucVoid); ++ } + return frame(sp, fp, epc); +} + @@ -112426,6 +111298,24 @@ index 00000000000..a2e4fea109c +#ifdef PRINT_SIGNAL_HANDLE + tty->print_cr("continuation_for_implicit_exception stub: %lx", stub); +#endif ++ } else if (sig == SIGILL && nativeInstruction_at(pc)->is_stop()) { ++ // Pull a pointer to the error message out of the instruction ++ // stream. ++ const uint64_t *detail_msg_ptr ++ = (uint64_t*)(pc + 4/*NativeInstruction::instruction_size*/); ++ const char *detail_msg = (const char *)*detail_msg_ptr; ++ const char *msg = "stop"; ++ if (TraceTraps) { ++ tty->print_cr("trap: %s: (SIGILL)", msg); ++ } ++ ++ // End life with a fatal error, message and detail message and the context. ++ // Note: no need to do any post-processing here (e.g. signal chaining) ++ va_list va_dummy; ++ VMError::report_and_die(thread, uc, nullptr, 0, msg, detail_msg, va_dummy); ++ va_end(va_dummy); ++ ++ ShouldNotReachHere(); + } + } else if ((thread->thread_state() == _thread_in_vm || + thread->thread_state() == _thread_in_native) && @@ -112573,6 +111463,7 @@ index 00000000000..a2e4fea109c + if (context == NULL) return; + + const ucontext_t *uc = (const ucontext_t*)context; ++ + st->print_cr("Registers:"); + st->print( "ZERO=" INTPTR_FORMAT, (intptr_t)uc->uc_mcontext.__gregs[0]); + st->print(", RA=" INTPTR_FORMAT, (intptr_t)uc->uc_mcontext.__gregs[1]); @@ -112615,19 +111506,23 @@ index 00000000000..a2e4fea109c + st->print(", S8=" INTPTR_FORMAT, (intptr_t)uc->uc_mcontext.__gregs[31]); + st->cr(); + st->cr(); ++} + -+ intptr_t *sp = (intptr_t *)os::Linux::ucontext_get_sp(uc); -+ st->print_cr("Top of Stack: (sp=" PTR_FORMAT ")", p2i(sp)); -+ print_hex_dump(st, (address)(sp - 32), (address)(sp + 32), sizeof(intptr_t)); ++void os::print_tos_pc(outputStream *st, const void *context) { ++ if (context == NULL) return; ++ ++ const ucontext_t* uc = (const ucontext_t*)context; ++ ++ address sp = (address)os::Linux::ucontext_get_sp(uc); ++ print_tos(st, sp); + st->cr(); + + // Note: it may be unsafe to inspect memory near pc. For example, pc may + // point to garbage if entry point in an nmethod is corrupted. Leave + // this at the end, and hope for the best. -+ address pc = os::Posix::ucontext_get_pc(uc); -+ st->print_cr("Instructions: (pc=" PTR_FORMAT ")", p2i(pc)); -+ print_hex_dump(st, pc - 64, pc + 64, sizeof(char)); -+ Disassembler::decode(pc - 80, pc + 80, st); ++ address pc = os::fetch_frame_from_context(uc).pc(); ++ print_instructions(st, pc); ++ st->cr(); +} + +void os::setup_fpu() { @@ -112648,11 +111543,9 @@ index 00000000000..a2e4fea109c +bool os::is_ActiveCoresMP() { + return UseActiveCoresMP && _initial_active_processor_count == 1; +} -diff --git a/src/hotspot/os_cpu/linux_loongarch/os_linux_loongarch.hpp b/src/hotspot/os_cpu/linux_loongarch/os_linux_loongarch.hpp -new file mode 100644 -index 00000000000..fa02f8ba2f9 ---- /dev/null -+++ b/src/hotspot/os_cpu/linux_loongarch/os_linux_loongarch.hpp +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/os_cpu/linux_loongarch/os_linux_loongarch.hpp b/src/hotspot/os_cpu/linux_loongarch/os_linux_loongarch.hpp +--- a/src/hotspot/os_cpu/linux_loongarch/os_linux_loongarch.hpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/os_cpu/linux_loongarch/os_linux_loongarch.hpp 2024-01-31 14:01:11.674096231 +0800 @@ -0,0 +1,38 @@ +/* + * Copyright (c) 1999, 2013, Oracle and/or its affiliates. All rights reserved. @@ -112692,11 +111585,9 @@ index 00000000000..fa02f8ba2f9 + static bool is_ActiveCoresMP(); + +#endif // OS_CPU_LINUX_LOONGARCH_OS_LINUX_LOONGARCH_HPP -diff --git a/src/hotspot/os_cpu/linux_loongarch/prefetch_linux_loongarch.inline.hpp b/src/hotspot/os_cpu/linux_loongarch/prefetch_linux_loongarch.inline.hpp -new file mode 100644 -index 00000000000..cf3a596387c ---- /dev/null -+++ b/src/hotspot/os_cpu/linux_loongarch/prefetch_linux_loongarch.inline.hpp +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/os_cpu/linux_loongarch/prefetch_linux_loongarch.inline.hpp b/src/hotspot/os_cpu/linux_loongarch/prefetch_linux_loongarch.inline.hpp +--- a/src/hotspot/os_cpu/linux_loongarch/prefetch_linux_loongarch.inline.hpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/os_cpu/linux_loongarch/prefetch_linux_loongarch.inline.hpp 2024-01-31 14:01:11.674096231 +0800 @@ -0,0 +1,56 @@ +/* + * Copyright (c) 2003, 2010, Oracle and/or its affiliates. All rights reserved. @@ -112754,11 +111645,69 @@ index 00000000000..cf3a596387c +} + +#endif // OS_CPU_LINUX_LOONGARCH_PREFETCH_LINUX_LOONGARCH_INLINE_HPP -diff --git a/src/hotspot/os_cpu/linux_loongarch/thread_linux_loongarch.cpp b/src/hotspot/os_cpu/linux_loongarch/thread_linux_loongarch.cpp -new file mode 100644 -index 00000000000..9204302bca8 ---- /dev/null -+++ b/src/hotspot/os_cpu/linux_loongarch/thread_linux_loongarch.cpp +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/os_cpu/linux_loongarch/safefetch_linux_loongarch64.S b/src/hotspot/os_cpu/linux_loongarch/safefetch_linux_loongarch64.S +--- a/src/hotspot/os_cpu/linux_loongarch/safefetch_linux_loongarch64.S 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/os_cpu/linux_loongarch/safefetch_linux_loongarch64.S 2024-01-31 14:01:11.674096231 +0800 +@@ -0,0 +1,56 @@ ++/* ++ * Copyright (c) 2022 SAP SE. All rights reserved. ++ * Copyright (c) 2022, Oracle and/or its affiliates. All rights reserved. ++ * Copyright (c) 2022, Loongson Technology. All rights reserved. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ * ++ */ ++ ++ .globl SafeFetchN_impl ++ .globl _SafeFetchN_fault ++ .globl _SafeFetchN_continuation ++ .globl SafeFetch32_impl ++ .globl _SafeFetch32_fault ++ .globl _SafeFetch32_continuation ++ ++ # Support for int SafeFetch32(int* address, int defaultval); ++ # ++ # a0 : address ++ # a1 : defaultval ++SafeFetch32_impl: ++_SafeFetch32_fault: ++ ld.w $r4, $r4, 0 ++ jr $r1 ++_SafeFetch32_continuation: ++ or $r4, $r5, $r0 ++ jr $r1 ++ ++ # Support for intptr_t SafeFetchN(intptr_t* address, intptr_t defaultval); ++ # ++ # a0 : address ++ # a1 : defaultval ++SafeFetchN_impl: ++_SafeFetchN_fault: ++ ld.d $r4, $r4, 0 ++ jr $r1 ++_SafeFetchN_continuation: ++ or $r4, $r5, $r0 ++ jr $r1 +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/os_cpu/linux_loongarch/thread_linux_loongarch.cpp b/src/hotspot/os_cpu/linux_loongarch/thread_linux_loongarch.cpp +--- a/src/hotspot/os_cpu/linux_loongarch/thread_linux_loongarch.cpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/os_cpu/linux_loongarch/thread_linux_loongarch.cpp 2024-01-31 14:01:11.674096231 +0800 @@ -0,0 +1,105 @@ +/* + * Copyright (c) 2003, 2013, Oracle and/or its affiliates. All rights reserved. @@ -112865,11 +111814,9 @@ index 00000000000..9204302bca8 +} + +void JavaThread::cache_global_variables() { } -diff --git a/src/hotspot/os_cpu/linux_loongarch/thread_linux_loongarch.hpp b/src/hotspot/os_cpu/linux_loongarch/thread_linux_loongarch.hpp -new file mode 100644 -index 00000000000..82fc6fb659f ---- /dev/null -+++ b/src/hotspot/os_cpu/linux_loongarch/thread_linux_loongarch.hpp +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/os_cpu/linux_loongarch/thread_linux_loongarch.hpp b/src/hotspot/os_cpu/linux_loongarch/thread_linux_loongarch.hpp +--- a/src/hotspot/os_cpu/linux_loongarch/thread_linux_loongarch.hpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/os_cpu/linux_loongarch/thread_linux_loongarch.hpp 2024-01-31 14:01:11.674096231 +0800 @@ -0,0 +1,66 @@ +/* + * Copyright (c) 2000, 2013, Oracle and/or its affiliates. All rights reserved. @@ -112937,11 +111884,9 @@ index 00000000000..82fc6fb659f + static void disable_register_stack_guard() {} + +#endif // OS_CPU_LINUX_LOONGARCH_VM_THREAD_LINUX_LOONGARCH_HPP -diff --git a/src/hotspot/os_cpu/linux_loongarch/vmStructs_linux_loongarch.hpp b/src/hotspot/os_cpu/linux_loongarch/vmStructs_linux_loongarch.hpp -new file mode 100644 -index 00000000000..a39cb79bb1e ---- /dev/null -+++ b/src/hotspot/os_cpu/linux_loongarch/vmStructs_linux_loongarch.hpp +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/os_cpu/linux_loongarch/vmStructs_linux_loongarch.hpp b/src/hotspot/os_cpu/linux_loongarch/vmStructs_linux_loongarch.hpp +--- a/src/hotspot/os_cpu/linux_loongarch/vmStructs_linux_loongarch.hpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/os_cpu/linux_loongarch/vmStructs_linux_loongarch.hpp 2024-01-31 14:01:11.674096231 +0800 @@ -0,0 +1,55 @@ +/* + * Copyright (c) 2000, 2013, Oracle and/or its affiliates. All rights reserved. @@ -112998,11 +111943,9 @@ index 00000000000..a39cb79bb1e +#define VM_LONG_CONSTANTS_OS_CPU(declare_constant, declare_preprocessor_constant, declare_c1_constant, declare_c2_constant, declare_c2_preprocessor_constant) + +#endif // OS_CPU_LINUX_LOONGARCH_VMSTRUCTS_LINUX_LOONGARCH_HPP -diff --git a/src/hotspot/os_cpu/linux_loongarch/vm_version_linux_loongarch.cpp b/src/hotspot/os_cpu/linux_loongarch/vm_version_linux_loongarch.cpp -new file mode 100644 -index 00000000000..3711a7036a1 ---- /dev/null -+++ b/src/hotspot/os_cpu/linux_loongarch/vm_version_linux_loongarch.cpp +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/os_cpu/linux_loongarch/vm_version_linux_loongarch.cpp b/src/hotspot/os_cpu/linux_loongarch/vm_version_linux_loongarch.cpp +--- a/src/hotspot/os_cpu/linux_loongarch/vm_version_linux_loongarch.cpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/os_cpu/linux_loongarch/vm_version_linux_loongarch.cpp 2024-01-31 14:01:11.674096231 +0800 @@ -0,0 +1,95 @@ +/* + * Copyright (c) 2006, 2021, Oracle and/or its affiliates. All rights reserved. @@ -113099,11 +112042,9 @@ index 00000000000..3711a7036a1 + HWCAP_LOONGARCH_LBT_ARM | + HWCAP_LOONGARCH_LBT_MIPS); +} -diff --git a/src/hotspot/os_cpu/linux_mips/assembler_linux_mips.cpp b/src/hotspot/os_cpu/linux_mips/assembler_linux_mips.cpp -new file mode 100644 -index 00000000000..30719a0340b ---- /dev/null -+++ b/src/hotspot/os_cpu/linux_mips/assembler_linux_mips.cpp +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/os_cpu/linux_mips/assembler_linux_mips.cpp b/src/hotspot/os_cpu/linux_mips/assembler_linux_mips.cpp +--- a/src/hotspot/os_cpu/linux_mips/assembler_linux_mips.cpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/os_cpu/linux_mips/assembler_linux_mips.cpp 2024-01-31 14:01:11.674096231 +0800 @@ -0,0 +1,24 @@ +/* + * Copyright (c) 1999, 2010, Oracle and/or its affiliates. All rights reserved. @@ -113129,11 +112070,9 @@ index 00000000000..30719a0340b + * questions. + * + */ -diff --git a/src/hotspot/os_cpu/linux_mips/atomic_linux_mips.hpp b/src/hotspot/os_cpu/linux_mips/atomic_linux_mips.hpp -new file mode 100644 -index 00000000000..c82e3ce1ecf ---- /dev/null -+++ b/src/hotspot/os_cpu/linux_mips/atomic_linux_mips.hpp +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/os_cpu/linux_mips/atomic_linux_mips.hpp b/src/hotspot/os_cpu/linux_mips/atomic_linux_mips.hpp +--- a/src/hotspot/os_cpu/linux_mips/atomic_linux_mips.hpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/os_cpu/linux_mips/atomic_linux_mips.hpp 2024-01-31 14:01:11.674096231 +0800 @@ -0,0 +1,194 @@ +/* + * Copyright (c) 1999, 2013, Oracle and/or its affiliates. All rights reserved. @@ -113329,11 +112268,9 @@ index 00000000000..c82e3ce1ecf + + +#endif // OS_CPU_LINUX_MIPS_VM_ATOMIC_LINUX_MIPS_HPP -diff --git a/src/hotspot/os_cpu/linux_mips/bytes_linux_mips.inline.hpp b/src/hotspot/os_cpu/linux_mips/bytes_linux_mips.inline.hpp -new file mode 100644 -index 00000000000..5b5cd10aa55 ---- /dev/null -+++ b/src/hotspot/os_cpu/linux_mips/bytes_linux_mips.inline.hpp +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/os_cpu/linux_mips/bytes_linux_mips.inline.hpp b/src/hotspot/os_cpu/linux_mips/bytes_linux_mips.inline.hpp +--- a/src/hotspot/os_cpu/linux_mips/bytes_linux_mips.inline.hpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/os_cpu/linux_mips/bytes_linux_mips.inline.hpp 2024-01-31 14:01:11.674096231 +0800 @@ -0,0 +1,37 @@ +/* + * Copyright (c) 1999, 2010, Oracle and/or its affiliates. All rights reserved. @@ -113372,11 +112309,9 @@ index 00000000000..5b5cd10aa55 +inline u8 Bytes::swap_u8(u8 x) { return bswap_64(x); } + +#endif // OS_CPU_LINUX_MIPS_VM_BYTES_LINUX_MIPS_INLINE_HPP -diff --git a/src/hotspot/os_cpu/linux_mips/copy_linux_mips.inline.hpp b/src/hotspot/os_cpu/linux_mips/copy_linux_mips.inline.hpp -new file mode 100644 -index 00000000000..3fd6ef7b36c ---- /dev/null -+++ b/src/hotspot/os_cpu/linux_mips/copy_linux_mips.inline.hpp +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/os_cpu/linux_mips/copy_linux_mips.inline.hpp b/src/hotspot/os_cpu/linux_mips/copy_linux_mips.inline.hpp +--- a/src/hotspot/os_cpu/linux_mips/copy_linux_mips.inline.hpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/os_cpu/linux_mips/copy_linux_mips.inline.hpp 2024-01-31 14:01:11.674096231 +0800 @@ -0,0 +1,125 @@ +/* + * Copyright (c) 2003, 2010, Oracle and/or its affiliates. All rights reserved. @@ -113503,11 +112438,9 @@ index 00000000000..3fd6ef7b36c +} + +#endif // OS_CPU_LINUX_MIPS_VM_COPY_LINUX_MIPS_INLINE_HPP -diff --git a/src/hotspot/os_cpu/linux_mips/globals_linux_mips.hpp b/src/hotspot/os_cpu/linux_mips/globals_linux_mips.hpp -new file mode 100644 -index 00000000000..f1599ac5f17 ---- /dev/null -+++ b/src/hotspot/os_cpu/linux_mips/globals_linux_mips.hpp +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/os_cpu/linux_mips/globals_linux_mips.hpp b/src/hotspot/os_cpu/linux_mips/globals_linux_mips.hpp +--- a/src/hotspot/os_cpu/linux_mips/globals_linux_mips.hpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/os_cpu/linux_mips/globals_linux_mips.hpp 2024-01-31 14:01:11.674096231 +0800 @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2000, 2013, Oracle and/or its affiliates. All rights reserved. @@ -113560,11 +112493,9 @@ index 00000000000..f1599ac5f17 +define_pd_global(uintx,HeapBaseMinAddress, 2*G); + +#endif // OS_CPU_LINUX_MIPS_VM_GLOBALS_LINUX_MIPS_HPP -diff --git a/src/hotspot/os_cpu/linux_mips/linux_mips.s b/src/hotspot/os_cpu/linux_mips/linux_mips.s -new file mode 100644 -index 00000000000..36c8d810c3c ---- /dev/null -+++ b/src/hotspot/os_cpu/linux_mips/linux_mips.s +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/os_cpu/linux_mips/linux_mips.s b/src/hotspot/os_cpu/linux_mips/linux_mips.s +--- a/src/hotspot/os_cpu/linux_mips/linux_mips.s 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/os_cpu/linux_mips/linux_mips.s 2024-01-31 14:01:11.674096231 +0800 @@ -0,0 +1,25 @@ +# +# Copyright (c) 2004, 2013, Oracle and/or its affiliates. All rights reserved. @@ -113591,11 +112522,9 @@ index 00000000000..36c8d810c3c +# + + -diff --git a/src/hotspot/os_cpu/linux_mips/orderAccess_linux_mips.hpp b/src/hotspot/os_cpu/linux_mips/orderAccess_linux_mips.hpp -new file mode 100644 -index 00000000000..460d118c869 ---- /dev/null -+++ b/src/hotspot/os_cpu/linux_mips/orderAccess_linux_mips.hpp +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/os_cpu/linux_mips/orderAccess_linux_mips.hpp b/src/hotspot/os_cpu/linux_mips/orderAccess_linux_mips.hpp +--- a/src/hotspot/os_cpu/linux_mips/orderAccess_linux_mips.hpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/os_cpu/linux_mips/orderAccess_linux_mips.hpp 2024-01-31 14:01:11.674096231 +0800 @@ -0,0 +1,52 @@ +/* + * Copyright (c) 2003, 2013, Oracle and/or its affiliates. All rights reserved. @@ -113634,6 +112563,7 @@ index 00000000000..460d118c869 + __asm__ __volatile__ ("nop" : : : "memory"); \ + else \ + __asm__ __volatile__ ("sync" : : : "memory"); ++#define inlasm_synci() __asm__ __volatile__ ("synci 0($0)" : : : "memory"); + +inline void OrderAccess::loadload() { inlasm_sync(); } +inline void OrderAccess::storestore() { inlasm_sync(); } @@ -113643,18 +112573,15 @@ index 00000000000..460d118c869 +inline void OrderAccess::acquire() { inlasm_sync(); } +inline void OrderAccess::release() { inlasm_sync(); } +inline void OrderAccess::fence() { inlasm_sync(); } -+inline void OrderAccess::cross_modify_fence_impl() { inlasm_sync(); } -+ ++inline void OrderAccess::cross_modify_fence_impl() { inlasm_synci(); } + +#undef inlasm_sync + +#endif // OS_CPU_LINUX_MIPS_VM_ORDERACCESS_LINUX_MIPS_HPP -diff --git a/src/hotspot/os_cpu/linux_mips/os_linux_mips.cpp b/src/hotspot/os_cpu/linux_mips/os_linux_mips.cpp -new file mode 100644 -index 00000000000..8344945ff79 ---- /dev/null -+++ b/src/hotspot/os_cpu/linux_mips/os_linux_mips.cpp -@@ -0,0 +1,810 @@ +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/os_cpu/linux_mips/os_linux_mips.cpp b/src/hotspot/os_cpu/linux_mips/os_linux_mips.cpp +--- a/src/hotspot/os_cpu/linux_mips/os_linux_mips.cpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/os_cpu/linux_mips/os_linux_mips.cpp 2024-01-31 14:01:11.677429596 +0800 +@@ -0,0 +1,817 @@ +/* + * Copyright (c) 1999, 2014, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 2015, 2023, Loongson Technology. All rights reserved. @@ -114377,6 +113304,7 @@ index 00000000000..8344945ff79 + if (context == NULL) return; + + const ucontext_t *uc = (const ucontext_t*)context; ++ + st->print_cr("Registers:"); + st->print( "R0=" INTPTR_FORMAT, (intptr_t)uc->uc_mcontext.gregs[0]); + st->print(", AT=" INTPTR_FORMAT, (intptr_t)uc->uc_mcontext.gregs[1]); @@ -114419,6 +113347,12 @@ index 00000000000..8344945ff79 + st->print(", RA=" INTPTR_FORMAT, (intptr_t)uc->uc_mcontext.gregs[31]); + st->cr(); + st->cr(); ++} ++ ++void os::print_tos_pc(outputStream *st, const void *context) { ++ if (context == NULL) return; ++ ++ const ucontext_t* uc = (const ucontext_t*)context; + + intptr_t *sp = (intptr_t *)os::Linux::ucontext_get_sp(uc); + st->print_cr("Top of Stack: (sp=" PTR_FORMAT ")", p2i(sp)); @@ -114465,11 +113399,9 @@ index 00000000000..8344945ff79 +bool os::is_ActiveCoresMP() { + return UseActiveCoresMP && _initial_active_processor_count == 1; +} -diff --git a/src/hotspot/os_cpu/linux_mips/os_linux_mips.hpp b/src/hotspot/os_cpu/linux_mips/os_linux_mips.hpp -new file mode 100644 -index 00000000000..c07d08156f2 ---- /dev/null -+++ b/src/hotspot/os_cpu/linux_mips/os_linux_mips.hpp +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/os_cpu/linux_mips/os_linux_mips.hpp b/src/hotspot/os_cpu/linux_mips/os_linux_mips.hpp +--- a/src/hotspot/os_cpu/linux_mips/os_linux_mips.hpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/os_cpu/linux_mips/os_linux_mips.hpp 2024-01-31 14:01:11.677429596 +0800 @@ -0,0 +1,39 @@ +/* + * Copyright (c) 1999, 2013, Oracle and/or its affiliates. All rights reserved. @@ -114510,11 +113442,9 @@ index 00000000000..c07d08156f2 + static bool is_ActiveCoresMP(); + +#endif // OS_CPU_LINUX_MIPS_VM_OS_LINUX_MIPS_HPP -diff --git a/src/hotspot/os_cpu/linux_mips/prefetch_linux_mips.inline.hpp b/src/hotspot/os_cpu/linux_mips/prefetch_linux_mips.inline.hpp -new file mode 100644 -index 00000000000..93490345f0b ---- /dev/null -+++ b/src/hotspot/os_cpu/linux_mips/prefetch_linux_mips.inline.hpp +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/os_cpu/linux_mips/prefetch_linux_mips.inline.hpp b/src/hotspot/os_cpu/linux_mips/prefetch_linux_mips.inline.hpp +--- a/src/hotspot/os_cpu/linux_mips/prefetch_linux_mips.inline.hpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/os_cpu/linux_mips/prefetch_linux_mips.inline.hpp 2024-01-31 14:01:11.677429596 +0800 @@ -0,0 +1,58 @@ +/* + * Copyright (c) 2003, 2010, Oracle and/or its affiliates. All rights reserved. @@ -114574,15 +113504,14 @@ index 00000000000..93490345f0b +} + +#endif // OS_CPU_LINUX_MIPS_VM_PREFETCH_LINUX_MIPS_INLINE_HPP -diff --git a/src/hotspot/os_cpu/linux_mips/thread_linux_mips.cpp b/src/hotspot/os_cpu/linux_mips/thread_linux_mips.cpp -new file mode 100644 -index 00000000000..4372eb41e9c ---- /dev/null -+++ b/src/hotspot/os_cpu/linux_mips/thread_linux_mips.cpp -@@ -0,0 +1,108 @@ +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/os_cpu/linux_mips/safefetch_linux_mips64.S b/src/hotspot/os_cpu/linux_mips/safefetch_linux_mips64.S +--- a/src/hotspot/os_cpu/linux_mips/safefetch_linux_mips64.S 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/os_cpu/linux_mips/safefetch_linux_mips64.S 2024-01-31 14:01:11.677429596 +0800 +@@ -0,0 +1,60 @@ +/* -+ * Copyright (c) 2003, 2013, Oracle and/or its affiliates. All rights reserved. -+ * Copyright (c) 2015, 2022, Loongson Technology. All rights reserved. ++ * Copyright (c) 2022 SAP SE. All rights reserved. ++ * Copyright (c) 2022, Oracle and/or its affiliates. All rights reserved. ++ * Copyright (c) 2023, Loongson Technology. All rights reserved. + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. + * + * This code is free software; you can redistribute it and/or modify it @@ -114605,98 +113534,159 @@ index 00000000000..4372eb41e9c + * + */ + -+#include "precompiled.hpp" -+#include "compiler/compileBroker.hpp" -+#include "runtime/frame.inline.hpp" -+#include "runtime/thread.inline.hpp" -+#include "runtime/sharedRuntime.hpp" -+ -+void JavaThread::pd_initialize() -+{ -+ _anchor.clear(); -+} -+ -+frame JavaThread::pd_last_frame() { -+ assert(has_last_Java_frame(), "must have last_Java_sp() when suspended"); -+ if (_anchor.last_Java_pc() != NULL) { -+ return frame(_anchor.last_Java_sp(), _anchor.last_Java_fp(), _anchor.last_Java_pc()); -+ } else { -+ // This will pick up pc from sp -+ return frame(_anchor.last_Java_sp(), _anchor.last_Java_fp()); -+ } -+} -+ -+// For Forte Analyzer AsyncGetCallTrace profiling support - thread is -+// currently interrupted by SIGPROF -+bool JavaThread::pd_get_top_frame_for_signal_handler(frame* fr_addr, -+ void* ucontext, bool isInJava) { -+ -+ assert(Thread::current() == this, "caller must be current thread"); -+ return pd_get_top_frame(fr_addr, ucontext, isInJava); -+} -+ -+bool JavaThread::pd_get_top_frame_for_profiling(frame* fr_addr, void* ucontext, bool isInJava) { -+ return pd_get_top_frame(fr_addr, ucontext, isInJava); -+} -+ -+bool JavaThread::pd_get_top_frame(frame* fr_addr, void* ucontext, bool isInJava) { -+ assert(this->is_Java_thread(), "must be JavaThread"); -+ JavaThread* jt = (JavaThread *)this; -+ -+ // If we have a last_Java_frame, then we should use it even if -+ // isInJava == true. It should be more reliable than ucontext info. -+ if (jt->has_last_Java_frame() && jt->frame_anchor()->walkable()) { -+ *fr_addr = jt->pd_last_frame(); -+ return true; -+ } -+ -+ // At this point, we don't have a last_Java_frame, so -+ // we try to glean some information out of the ucontext -+ // if we were running Java code when SIGPROF came in. -+ if (isInJava) { -+ ucontext_t* uc = (ucontext_t*) ucontext; -+ -+ intptr_t* ret_fp; -+ intptr_t* ret_sp; -+ address addr = os::fetch_frame_from_context(uc, &ret_sp, &ret_fp); -+ if (addr == NULL || ret_sp == NULL) { -+ // ucontext wasn't useful -+ return false; -+ } -+ -+ frame ret_frame(ret_sp, ret_fp, addr); -+ if (!ret_frame.safe_for_sender(jt)) { -+#ifdef COMPILER2 -+ // C2 and JVMCI use ebp as a general register see if NULL fp helps -+ frame ret_frame2(ret_sp, NULL, addr); -+ if (!ret_frame2.safe_for_sender(jt)) { -+ // nothing else to try if the frame isn't good -+ return false; -+ } -+ ret_frame = ret_frame2; -+#else -+ // nothing else to try if the frame isn't good -+ return false; -+#endif // COMPILER2_OR_JVMCI -+ } -+ *fr_addr = ret_frame; -+ return true; -+ } -+ -+ // nothing else to try -+ return false; -+} -+ -+void JavaThread::cache_global_variables() { } -diff --git a/src/hotspot/os_cpu/linux_mips/thread_linux_mips.hpp b/src/hotspot/os_cpu/linux_mips/thread_linux_mips.hpp -new file mode 100644 -index 00000000000..c38f6950fd0 ---- /dev/null -+++ b/src/hotspot/os_cpu/linux_mips/thread_linux_mips.hpp -@@ -0,0 +1,66 @@ ++ .globl SafeFetchN_impl ++ .globl _SafeFetchN_fault ++ .globl _SafeFetchN_continuation ++ .globl SafeFetch32_impl ++ .globl _SafeFetch32_fault ++ .globl _SafeFetch32_continuation ++ ++ # Support for int SafeFetch32(int* address, int defaultval); ++ # ++ # a0 : address ++ # a1 : defaultval ++SafeFetch32_impl: ++_SafeFetch32_fault: ++ lw $2, 0($4) ++ j $31 ++ nop ++_SafeFetch32_continuation: ++ or $2, $5, $0 ++ j $31 ++ nop ++ ++ # Support for intptr_t SafeFetchN(intptr_t* address, intptr_t defaultval); ++ # ++ # a0 : address ++ # a1 : defaultval ++SafeFetchN_impl: ++_SafeFetchN_fault: ++ ld $2, 0($4) ++ j $31 ++ nop ++_SafeFetchN_continuation: ++ or $2, $5, $0 ++ j $31 ++ nop +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/os_cpu/linux_mips/thread_linux_mips.cpp b/src/hotspot/os_cpu/linux_mips/thread_linux_mips.cpp +--- a/src/hotspot/os_cpu/linux_mips/thread_linux_mips.cpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/os_cpu/linux_mips/thread_linux_mips.cpp 2024-01-31 14:01:11.677429596 +0800 +@@ -0,0 +1,108 @@ +/* -+ * Copyright (c) 2000, 2013, Oracle and/or its affiliates. All rights reserved. -+ * Copyright (c) 2015, 2021, Loongson Technology. All rights reserved. ++ * Copyright (c) 2003, 2013, Oracle and/or its affiliates. All rights reserved. ++ * Copyright (c) 2015, 2022, Loongson Technology. All rights reserved. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ * ++ */ ++ ++#include "precompiled.hpp" ++#include "compiler/compileBroker.hpp" ++#include "runtime/frame.inline.hpp" ++#include "runtime/thread.inline.hpp" ++#include "runtime/sharedRuntime.hpp" ++ ++void JavaThread::pd_initialize() ++{ ++ _anchor.clear(); ++} ++ ++frame JavaThread::pd_last_frame() { ++ assert(has_last_Java_frame(), "must have last_Java_sp() when suspended"); ++ if (_anchor.last_Java_pc() != NULL) { ++ return frame(_anchor.last_Java_sp(), _anchor.last_Java_fp(), _anchor.last_Java_pc()); ++ } else { ++ // This will pick up pc from sp ++ return frame(_anchor.last_Java_sp(), _anchor.last_Java_fp()); ++ } ++} ++ ++// For Forte Analyzer AsyncGetCallTrace profiling support - thread is ++// currently interrupted by SIGPROF ++bool JavaThread::pd_get_top_frame_for_signal_handler(frame* fr_addr, ++ void* ucontext, bool isInJava) { ++ ++ assert(Thread::current() == this, "caller must be current thread"); ++ return pd_get_top_frame(fr_addr, ucontext, isInJava); ++} ++ ++bool JavaThread::pd_get_top_frame_for_profiling(frame* fr_addr, void* ucontext, bool isInJava) { ++ return pd_get_top_frame(fr_addr, ucontext, isInJava); ++} ++ ++bool JavaThread::pd_get_top_frame(frame* fr_addr, void* ucontext, bool isInJava) { ++ assert(this->is_Java_thread(), "must be JavaThread"); ++ JavaThread* jt = (JavaThread *)this; ++ ++ // If we have a last_Java_frame, then we should use it even if ++ // isInJava == true. It should be more reliable than ucontext info. ++ if (jt->has_last_Java_frame() && jt->frame_anchor()->walkable()) { ++ *fr_addr = jt->pd_last_frame(); ++ return true; ++ } ++ ++ // At this point, we don't have a last_Java_frame, so ++ // we try to glean some information out of the ucontext ++ // if we were running Java code when SIGPROF came in. ++ if (isInJava) { ++ ucontext_t* uc = (ucontext_t*) ucontext; ++ ++ intptr_t* ret_fp; ++ intptr_t* ret_sp; ++ address addr = os::fetch_frame_from_context(uc, &ret_sp, &ret_fp); ++ if (addr == NULL || ret_sp == NULL) { ++ // ucontext wasn't useful ++ return false; ++ } ++ ++ frame ret_frame(ret_sp, ret_fp, addr); ++ if (!ret_frame.safe_for_sender(jt)) { ++#ifdef COMPILER2 ++ // C2 and JVMCI use ebp as a general register see if NULL fp helps ++ frame ret_frame2(ret_sp, NULL, addr); ++ if (!ret_frame2.safe_for_sender(jt)) { ++ // nothing else to try if the frame isn't good ++ return false; ++ } ++ ret_frame = ret_frame2; ++#else ++ // nothing else to try if the frame isn't good ++ return false; ++#endif // COMPILER2_OR_JVMCI ++ } ++ *fr_addr = ret_frame; ++ return true; ++ } ++ ++ // nothing else to try ++ return false; ++} ++ ++void JavaThread::cache_global_variables() { } +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/os_cpu/linux_mips/thread_linux_mips.hpp b/src/hotspot/os_cpu/linux_mips/thread_linux_mips.hpp +--- a/src/hotspot/os_cpu/linux_mips/thread_linux_mips.hpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/os_cpu/linux_mips/thread_linux_mips.hpp 2024-01-31 14:01:11.677429596 +0800 +@@ -0,0 +1,66 @@ ++/* ++ * Copyright (c) 2000, 2013, Oracle and/or its affiliates. All rights reserved. ++ * Copyright (c) 2015, 2021, Loongson Technology. All rights reserved. + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. + * + * This code is free software; you can redistribute it and/or modify it @@ -114760,11 +113750,9 @@ index 00000000000..c38f6950fd0 + static void disable_register_stack_guard() {} + +#endif // OS_CPU_LINUX_MIPS_VM_THREAD_LINUX_MIPS_HPP -diff --git a/src/hotspot/os_cpu/linux_mips/vmStructs_linux_mips.hpp b/src/hotspot/os_cpu/linux_mips/vmStructs_linux_mips.hpp -new file mode 100644 -index 00000000000..b7454bf045a ---- /dev/null -+++ b/src/hotspot/os_cpu/linux_mips/vmStructs_linux_mips.hpp +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/os_cpu/linux_mips/vmStructs_linux_mips.hpp b/src/hotspot/os_cpu/linux_mips/vmStructs_linux_mips.hpp +--- a/src/hotspot/os_cpu/linux_mips/vmStructs_linux_mips.hpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/os_cpu/linux_mips/vmStructs_linux_mips.hpp 2024-01-31 14:01:11.677429596 +0800 @@ -0,0 +1,55 @@ +/* + * Copyright (c) 2000, 2013, Oracle and/or its affiliates. All rights reserved. @@ -114821,11 +113809,9 @@ index 00000000000..b7454bf045a +#define VM_LONG_CONSTANTS_OS_CPU(declare_constant, declare_preprocessor_constant, declare_c1_constant, declare_c2_constant, declare_c2_preprocessor_constant) + +#endif // OS_CPU_LINUX_MIPS_VM_VMSTRUCTS_LINUX_MIPS_HPP -diff --git a/src/hotspot/os_cpu/linux_mips/vm_version_linux_mips.cpp b/src/hotspot/os_cpu/linux_mips/vm_version_linux_mips.cpp -new file mode 100644 -index 00000000000..93e4bea04c6 ---- /dev/null -+++ b/src/hotspot/os_cpu/linux_mips/vm_version_linux_mips.cpp +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/os_cpu/linux_mips/vm_version_linux_mips.cpp b/src/hotspot/os_cpu/linux_mips/vm_version_linux_mips.cpp +--- a/src/hotspot/os_cpu/linux_mips/vm_version_linux_mips.cpp 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/hotspot/os_cpu/linux_mips/vm_version_linux_mips.cpp 2024-01-31 14:01:11.677429596 +0800 @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2006, 2010, Oracle and/or its affiliates. All rights reserved. @@ -114855,10 +113841,9 @@ index 00000000000..93e4bea04c6 +#include "precompiled.hpp" +#include "runtime/os.hpp" +#include "runtime/vm_version.hpp" -diff --git a/src/hotspot/share/asm/codeBuffer.cpp b/src/hotspot/share/asm/codeBuffer.cpp -index 0012152d48d..e3660cab271 100644 ---- a/src/hotspot/share/asm/codeBuffer.cpp -+++ b/src/hotspot/share/asm/codeBuffer.cpp +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/share/asm/codeBuffer.cpp b/src/hotspot/share/asm/codeBuffer.cpp +--- a/src/hotspot/share/asm/codeBuffer.cpp 2024-01-10 05:18:15.000000000 +0800 ++++ b/src/hotspot/share/asm/codeBuffer.cpp 2024-01-31 14:01:11.684096327 +0800 @@ -22,6 +22,12 @@ * */ @@ -114872,7 +113857,7 @@ index 0012152d48d..e3660cab271 100644 #include "precompiled.hpp" #include "asm/codeBuffer.hpp" #include "code/oopRecorder.inline.hpp" -@@ -330,6 +336,7 @@ void CodeSection::relocate(address at, RelocationHolder const& spec, int format) +@@ -330,6 +336,7 @@ assert(rtype == relocInfo::none || rtype == relocInfo::runtime_call_type || rtype == relocInfo::internal_word_type|| @@ -114880,10 +113865,9 @@ index 0012152d48d..e3660cab271 100644 rtype == relocInfo::section_word_type || rtype == relocInfo::external_word_type, "code needs relocation information"); -diff --git a/src/hotspot/share/c1/c1_Compiler.cpp b/src/hotspot/share/c1/c1_Compiler.cpp -index 3795b4e0192..9830cd9c27c 100644 ---- a/src/hotspot/share/c1/c1_Compiler.cpp -+++ b/src/hotspot/share/c1/c1_Compiler.cpp +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/share/c1/c1_Compiler.cpp b/src/hotspot/share/c1/c1_Compiler.cpp +--- a/src/hotspot/share/c1/c1_Compiler.cpp 2024-01-10 05:18:15.000000000 +0800 ++++ b/src/hotspot/share/c1/c1_Compiler.cpp 2024-01-31 14:01:11.684096327 +0800 @@ -43,6 +43,12 @@ #include "utilities/bitMap.inline.hpp" #include "utilities/macros.hpp" @@ -114897,7 +113881,7 @@ index 3795b4e0192..9830cd9c27c 100644 Compiler::Compiler() : AbstractCompiler(compiler_c1) { } -@@ -211,7 +217,7 @@ bool Compiler::is_intrinsic_supported(const methodHandle& method) { +@@ -212,7 +218,7 @@ case vmIntrinsics::_updateCRC32: case vmIntrinsics::_updateBytesCRC32: case vmIntrinsics::_updateByteBufferCRC32: @@ -114906,321 +113890,357 @@ index 3795b4e0192..9830cd9c27c 100644 case vmIntrinsics::_updateBytesCRC32C: case vmIntrinsics::_updateDirectByteBufferCRC32C: #endif -diff --git a/src/hotspot/share/c1/c1_LIR.cpp b/src/hotspot/share/c1/c1_LIR.cpp -index 62cff4c7505..f1af08d5df0 100644 ---- a/src/hotspot/share/c1/c1_LIR.cpp -+++ b/src/hotspot/share/c1/c1_LIR.cpp -@@ -236,6 +236,18 @@ void LIR_Op2::verify() const { - #endif +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/share/c1/c1_LinearScan.cpp b/src/hotspot/share/c1/c1_LinearScan.cpp +--- a/src/hotspot/share/c1/c1_LinearScan.cpp 2024-01-10 05:18:15.000000000 +0800 ++++ b/src/hotspot/share/c1/c1_LinearScan.cpp 2024-01-31 14:01:11.687429690 +0800 +@@ -35,6 +35,12 @@ + #include "runtime/timerTrace.hpp" + #include "utilities/bitMap.inline.hpp" + ++/* ++ * This file has been modified by Loongson Technology in 2023, These ++ * modifications are Copyright (c) 2022, 2023, Loongson Technology, and are made ++ * available on the same license terms set forth above. ++ */ ++ + #ifndef PRODUCT + + static LinearScanStatistic _stat_before_alloc; +@@ -1240,7 +1246,7 @@ + break; + } + case lir_cmove: { +-#ifdef RISCV ++#if defined(RISCV) || defined(LOONGARCH) + assert(op->as_Op4() != NULL, "lir_cmove must be LIR_Op4"); + LIR_Op4* cmove = (LIR_Op4*)op; + #else +@@ -3151,7 +3157,7 @@ + } + } + +-#ifndef RISCV ++#if !defined(RISCV) && !defined(LOONGARCH) + // Disable these optimizations on riscv temporarily, because it does not + // work when the comparison operands are bound to branches or cmoves. + { TIME_LINEAR_SCAN(timer_optimize_lir); +@@ -6385,7 +6391,7 @@ + // There might be a cmove inserted for profiling which depends on the same + // compare. If we change the condition of the respective compare, we have + // to take care of this cmove as well. +-#ifdef RISCV ++#if defined(RISCV) || defined(LOONGARCH) + LIR_Op4* prev_cmove = NULL; + #else + LIR_Op2* prev_cmove = NULL; +@@ -6395,7 +6401,7 @@ + prev_op = instructions->at(j); + // check for the cmove + if (prev_op->code() == lir_cmove) { +-#ifdef RISCV ++#if defined(RISCV) || defined(LOONGARCH) + assert(prev_op->as_Op4() != NULL, "cmove must be of type LIR_Op4"); + prev_cmove = (LIR_Op4*)prev_op; + #else +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/share/c1/c1_LIRAssembler.cpp b/src/hotspot/share/c1/c1_LIRAssembler.cpp +--- a/src/hotspot/share/c1/c1_LIRAssembler.cpp 2024-01-10 05:18:15.000000000 +0800 ++++ b/src/hotspot/share/c1/c1_LIRAssembler.cpp 2024-01-31 14:01:11.687429690 +0800 +@@ -22,6 +22,12 @@ + * + */ + ++/* ++ * This file has been modified by Loongson Technology in 2023, These ++ * modifications are Copyright (c) 2022, 2023, Loongson Technology, and are made ++ * available on the same license terms set forth above. ++ */ ++ + #include "precompiled.hpp" + #include "asm/assembler.inline.hpp" + #include "c1/c1_Compilation.hpp" +@@ -691,7 +697,7 @@ + comp_fl2i(op->code(), op->in_opr1(), op->in_opr2(), op->result_opr(), op); + break; + +-#ifndef RISCV ++#if !defined(RISCV) && !defined(LOONGARCH) + case lir_cmove: + cmove(op->condition(), op->in_opr1(), op->in_opr2(), op->result_opr(), op->type()); + break; +@@ -758,7 +764,7 @@ + } } -+void LIR_Op4::verify() const { -+#ifdef ASSERT -+ switch (code()) { -+ case lir_cmp_cmove: -+ break; +-#ifdef RISCV ++#if defined(RISCV) || defined(LOONGARCH) + void LIR_Assembler::emit_op4(LIR_Op4* op) { + switch(op->code()) { + case lir_cmove: +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/share/c1/c1_LIRAssembler.hpp b/src/hotspot/share/c1/c1_LIRAssembler.hpp +--- a/src/hotspot/share/c1/c1_LIRAssembler.hpp 2024-01-10 05:18:15.000000000 +0800 ++++ b/src/hotspot/share/c1/c1_LIRAssembler.hpp 2024-01-31 14:01:11.687429690 +0800 +@@ -22,6 +22,12 @@ + * + */ + ++/* ++ * This file has been modified by Loongson Technology in 2023, These ++ * modifications are Copyright (c) 2022, 2023, Loongson Technology, and are made ++ * available on the same license terms set forth above. ++ */ + -+ default: -+ assert(!result_opr()->is_register() || !result_opr()->is_oop_register(), -+ "can't produce oops from arith"); -+ } -+#endif -+} + #ifndef SHARE_C1_C1_LIRASSEMBLER_HPP + #define SHARE_C1_C1_LIRASSEMBLER_HPP + +@@ -186,7 +192,7 @@ + void emit_op1(LIR_Op1* op); + void emit_op2(LIR_Op2* op); + void emit_op3(LIR_Op3* op); +-#ifdef RISCV ++#if defined(RISCV) || defined(LOONGARCH) + void emit_op4(LIR_Op4* op); + #endif + void emit_opBranch(LIR_OpBranch* op); +@@ -222,7 +228,7 @@ + void volatile_move_op(LIR_Opr src, LIR_Opr result, BasicType type, CodeEmitInfo* info); + void comp_mem_op(LIR_Opr src, LIR_Opr result, BasicType type, CodeEmitInfo* info); // info set for null exceptions + void comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr result, LIR_Op2* op); +-#ifdef RISCV ++#if defined(RISCV) || defined(LOONGARCH) + void cmove(LIR_Condition code, LIR_Opr left, LIR_Opr right, LIR_Opr result, BasicType type, + LIR_Opr cmp_opr1 = LIR_OprFact::illegalOpr, LIR_Opr cmp_opr2 = LIR_OprFact::illegalOpr); + #else +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/share/c1/c1_LIR.cpp b/src/hotspot/share/c1/c1_LIR.cpp +--- a/src/hotspot/share/c1/c1_LIR.cpp 2024-01-10 05:18:15.000000000 +0800 ++++ b/src/hotspot/share/c1/c1_LIR.cpp 2024-01-31 14:01:11.687429690 +0800 +@@ -22,6 +22,12 @@ + * + */ + ++/* ++ * This file has been modified by Loongson Technology in 2023, These ++ * modifications are Copyright (c) 2022, 2023, Loongson Technology, and are made ++ * available on the same license terms set forth above. ++ */ ++ + #include "precompiled.hpp" + #include "c1/c1_CodeStubs.hpp" + #include "c1/c1_InstructionPrinter.hpp" +@@ -190,6 +196,8 @@ + case lir_cmove: + #ifdef RISCV + assert(false, "lir_cmove is LIR_Op4 on RISCV"); ++#elif defined(LOONGARCH) ++ assert(false, "lir_cmove is LIR_Op4 on LoongArch"); + #endif + case lir_xchg: + break; +@@ -241,7 +249,7 @@ + LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, BlockBegin* block) +-#ifdef RISCV ++#if defined(RISCV) || defined(LOONGARCH) + : LIR_Op2(lir_branch, cond, LIR_OprFact::illegalOpr, LIR_OprFact::illegalOpr, (CodeEmitInfo*)NULL) + #else : LIR_Op(lir_branch, LIR_OprFact::illegalOpr, (CodeEmitInfo*)NULL) -@@ -291,6 +303,56 @@ void LIR_OpBranch::negate_cond() { +@@ -254,7 +262,7 @@ } + LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, CodeStub* stub) : +-#ifdef RISCV ++#if defined(RISCV) || defined(LOONGARCH) + LIR_Op2(lir_branch, cond, LIR_OprFact::illegalOpr, LIR_OprFact::illegalOpr, (CodeEmitInfo*)NULL) + #else + LIR_Op(lir_branch, LIR_OprFact::illegalOpr, (CodeEmitInfo*)NULL) +@@ -267,7 +275,7 @@ + } -+LIR_OpCmpBranch::LIR_OpCmpBranch(LIR_Condition cond, LIR_Opr left, LIR_Opr right, CodeStub* stub, CodeEmitInfo* info) -+ : LIR_Op2(lir_cmp_branch, cond, left, right, info) -+ , _label(stub->entry()) -+ , _block(NULL) -+ , _ublock(NULL) -+ , _stub(stub) { -+} -+ -+LIR_OpCmpBranch::LIR_OpCmpBranch(LIR_Condition cond, LIR_Opr left, LIR_Opr right, BlockBegin* block, CodeEmitInfo* info) -+ : LIR_Op2(lir_cmp_branch, cond, left, right, info) -+ , _label(block->label()) -+ , _block(block) -+ , _ublock(NULL) -+ , _stub(NULL) { -+} -+ -+LIR_OpCmpBranch::LIR_OpCmpBranch(LIR_Condition cond, LIR_Opr left, LIR_Opr right, BlockBegin* block, BlockBegin* ublock, CodeEmitInfo* info) -+ : LIR_Op2(lir_cmp_float_branch, cond, left, right, info) -+ , _label(block->label()) -+ , _block(block) -+ , _ublock(ublock) -+ , _stub(NULL) { -+} -+ -+void LIR_OpCmpBranch::change_block(BlockBegin* b) { -+ assert(_block != NULL, "must have old block"); -+ assert(_block->label() == label(), "must be equal"); -+ -+ _block = b; -+ _label = b->label(); -+} -+ -+void LIR_OpCmpBranch::change_ublock(BlockBegin* b) { -+ assert(_ublock != NULL, "must have old block"); -+ -+ _ublock = b; -+} -+ -+void LIR_OpCmpBranch::negate_cond() { -+ switch (condition()) { -+ case lir_cond_equal: set_condition(lir_cond_notEqual); break; -+ case lir_cond_notEqual: set_condition(lir_cond_equal); break; -+ case lir_cond_less: set_condition(lir_cond_greaterEqual); break; -+ case lir_cond_lessEqual: set_condition(lir_cond_greater); break; -+ case lir_cond_greaterEqual: set_condition(lir_cond_less); break; -+ case lir_cond_greater: set_condition(lir_cond_lessEqual); break; -+ default: ShouldNotReachHere(); -+ } -+} -+ - LIR_OpTypeCheck::LIR_OpTypeCheck(LIR_Code code, LIR_Opr result, LIR_Opr object, ciKlass* klass, - LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3, - bool fast_check, CodeEmitInfo* info_for_exception, CodeEmitInfo* info_for_patch, -@@ -497,10 +559,7 @@ void LIR_OpVisitState::visit(LIR_Op* op) { + LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, BlockBegin* block, BlockBegin* ublock) +-#ifdef RISCV ++#if defined(RISCV) || defined(LOONGARCH) + : LIR_Op2(lir_cond_float_branch, cond, LIR_OprFact::illegalOpr, LIR_OprFact::illegalOpr, (CodeEmitInfo*)NULL) + #else + : LIR_Op(lir_cond_float_branch, LIR_OprFact::illegalOpr, (CodeEmitInfo*)NULL) +@@ -512,6 +520,7 @@ assert(opConvert->_info == NULL, "must be"); if (opConvert->_opr->is_valid()) do_input(opConvert->_opr); if (opConvert->_result->is_valid()) do_output(opConvert->_result); --#ifdef PPC32 -- if (opConvert->_tmp1->is_valid()) do_temp(opConvert->_tmp1); -- if (opConvert->_tmp2->is_valid()) do_temp(opConvert->_tmp2); --#endif + if (opConvert->_tmp->is_valid()) do_temp(opConvert->_tmp); - do_stub(opConvert->_stub); - - break; -@@ -597,6 +656,25 @@ void LIR_OpVisitState::visit(LIR_Op* op) { - break; - } + #ifdef PPC32 + if (opConvert->_tmp1->is_valid()) do_temp(opConvert->_tmp1); + if (opConvert->_tmp2->is_valid()) do_temp(opConvert->_tmp2); +@@ -528,7 +537,7 @@ + assert(op->as_OpBranch() != NULL, "must be"); + LIR_OpBranch* opBranch = (LIR_OpBranch*)op; -+// LIR_OpCmpBranch; -+ case lir_cmp_branch: // may have info, input and result register always invalid -+ case lir_cmp_float_branch: // may have info, input and result register always invalid -+ { -+ assert(op->as_OpCmpBranch() != NULL, "must be"); -+ LIR_OpCmpBranch* opCmpBranch = (LIR_OpCmpBranch*)op; -+ assert(opCmpBranch->_tmp2->is_illegal() && opCmpBranch->_tmp3->is_illegal() && -+ opCmpBranch->_tmp4->is_illegal() && opCmpBranch->_tmp5->is_illegal(), "not used"); -+ -+ if (opCmpBranch->_info) do_info(opCmpBranch->_info); -+ if (opCmpBranch->_opr1->is_valid()) do_input(opCmpBranch->_opr1); -+ if (opCmpBranch->_opr2->is_valid()) do_input(opCmpBranch->_opr2); -+ if (opCmpBranch->_tmp1->is_valid()) do_temp(opCmpBranch->_tmp1); -+ if (opCmpBranch->_stub != NULL) opCmpBranch->stub()->visit(this); -+ assert(opCmpBranch->_result->is_illegal(), "not used"); -+ -+ break; -+ } -+ - // special handling for cmove: right input operand must not be equal +-#ifdef RISCV ++#if defined(RISCV) || defined(LOONGARCH) + assert(opBranch->_tmp1->is_illegal() && opBranch->_tmp2->is_illegal() && + opBranch->_tmp3->is_illegal() && opBranch->_tmp4->is_illegal() && + opBranch->_tmp5->is_illegal(), "not used"); +@@ -625,7 +634,7 @@ // to the result operand, otherwise the backend fails case lir_cmove: -@@ -697,6 +775,29 @@ void LIR_OpVisitState::visit(LIR_Op* op) { - break; - } - -+// LIR_Op4 -+ // special handling for cmp cmove: src2(opr4) operand must not be equal -+ // to the result operand, otherwise the backend fails -+ case lir_cmp_cmove: -+ { -+ assert(op->as_Op4() != NULL, "must be"); -+ LIR_Op4* op4 = (LIR_Op4*)op; -+ -+ assert(op4->_info == NULL, "not used"); -+ assert(op4->_opr1->is_valid() && op4->_opr2->is_valid() && -+ op4->_opr3->is_valid() && op4->_opr4->is_valid() && -+ op4->_result->is_valid(), "used"); -+ -+ do_input(op4->_opr1); -+ do_input(op4->_opr2); -+ do_input(op4->_opr3); -+ do_input(op4->_opr4); -+ do_temp(op4->_opr4); -+ do_output(op4->_result); -+ -+ break; -+ } -+ - // LIR_OpJavaCall - case lir_static_call: - case lir_optvirtual_call: -@@ -1022,6 +1123,13 @@ void LIR_Op2::emit_code(LIR_Assembler* masm) { - masm->emit_op2(this); - } + { +-#ifdef RISCV ++#if defined(RISCV) || defined(LOONGARCH) + assert(op->as_Op4() != NULL, "must be"); + LIR_Op4* op4 = (LIR_Op4*)op; -+void LIR_OpCmpBranch::emit_code(LIR_Assembler* masm) { -+ masm->emit_opCmpBranch(this); -+ if (stub()) { -+ masm->append_code_stub(stub()); -+ } -+} -+ - void LIR_OpAllocArray::emit_code(LIR_Assembler* masm) { - masm->emit_alloc_array(this); - masm->append_code_stub(stub()); -@@ -1042,6 +1150,10 @@ void LIR_Op3::emit_code(LIR_Assembler* masm) { +@@ -1095,7 +1104,7 @@ masm->emit_op3(this); } -+void LIR_Op4::emit_code(LIR_Assembler* masm) { -+ masm->emit_op4(this); -+} -+ - void LIR_OpLock::emit_code(LIR_Assembler* masm) { - masm->emit_lock(this); - if (stub()) { -@@ -1418,8 +1530,7 @@ void LIR_List::null_check(LIR_Opr opr, CodeEmitInfo* info, bool deoptimize_on_nu - if (deoptimize_on_null) { - // Emit an explicit null check and deoptimize if opr is null - CodeStub* deopt = new DeoptimizeStub(info, Deoptimization::Reason_null_check, Deoptimization::Action_none); -- cmp(lir_cond_equal, opr, LIR_OprFact::oopConst(NULL)); -- branch(lir_cond_equal, deopt); -+ cmp_branch(lir_cond_equal, opr, LIR_OprFact::oopConst(NULL), deopt); - } else { - // Emit an implicit null check - append(new LIR_Op1(lir_null_check, opr, info)); -@@ -1667,6 +1778,8 @@ const char * LIR_Op::name() const { - case lir_cmp_l2i: s = "cmp_l2i"; break; - case lir_ucmp_fd2i: s = "ucomp_fd2i"; break; - case lir_cmp_fd2i: s = "comp_fd2i"; break; -+ case lir_cmp_branch: s = "cmp_branch"; break; -+ case lir_cmp_float_branch: s = "cmp_fbranch"; break; - case lir_cmove: s = "cmove"; break; - case lir_add: s = "add"; break; - case lir_sub: s = "sub"; break; -@@ -1690,6 +1803,8 @@ const char * LIR_Op::name() const { - case lir_irem: s = "irem"; break; - case lir_fmad: s = "fmad"; break; - case lir_fmaf: s = "fmaf"; break; -+ // LIR_Op4 -+ case lir_cmp_cmove: s = "cmp_cmove"; break; - // LIR_OpJavaCall - case lir_static_call: s = "static"; break; - case lir_optvirtual_call: s = "optvirtual"; break; -@@ -1840,6 +1955,26 @@ void LIR_OpBranch::print_instr(outputStream* out) const { - } +-#ifdef RISCV ++#if defined(RISCV) || defined(LOONGARCH) + void LIR_Op4::emit_code(LIR_Assembler* masm) { + masm->emit_op4(this); + } +@@ -1141,7 +1150,7 @@ + , _file(NULL) + , _line(0) + #endif +-#ifdef RISCV ++#if defined(RISCV) || defined(LOONGARCH) + , _cmp_opr1(LIR_OprFact::illegalOpr) + , _cmp_opr2(LIR_OprFact::illegalOpr) + #endif +@@ -1162,7 +1171,7 @@ } + #endif -+// LIR_OpCmpBranch -+void LIR_OpCmpBranch::print_instr(outputStream* out) const { -+ print_condition(out, condition()); out->print(" "); -+ in_opr1()->print(out); out->print(" "); -+ in_opr2()->print(out); out->print(" "); -+ if (block() != NULL) { -+ out->print("[B%d] ", block()->block_id()); -+ } else if (stub() != NULL) { -+ out->print("["); -+ stub()->print_name(out); -+ out->print(": " INTPTR_FORMAT "]", p2i(stub())); -+ if (stub()->info() != NULL) out->print(" [bci:%d]", stub()->info()->stack()->bci()); -+ } else { -+ out->print("[label:" INTPTR_FORMAT "] ", p2i(label())); -+ } -+ if (ublock() != NULL) { -+ out->print("unordered: [B%d] ", ublock()->block_id()); -+ } -+} -+ - void LIR_Op::print_condition(outputStream* out, LIR_Condition cond) { - switch(cond) { - case lir_cond_equal: out->print("[EQ]"); break; -@@ -1860,12 +1995,9 @@ void LIR_OpConvert::print_instr(outputStream* out) const { +-#ifdef RISCV ++#if defined(RISCV) || defined(LOONGARCH) + void LIR_List::set_cmp_oprs(LIR_Op* op) { + switch (op->code()) { + case lir_cmp: +@@ -1185,7 +1194,7 @@ + break; + #if INCLUDE_ZGC + case lir_zloadbarrier_test: +- _cmp_opr1 = FrameMap::as_opr(t1); ++ _cmp_opr1 = FrameMap::as_opr(RISCV_ONLY(t1) LOONGARCH64_ONLY(SCR1)); + _cmp_opr2 = LIR_OprFact::intConst(0); + break; + #endif +@@ -1924,7 +1933,7 @@ + // LIR_OpBranch + void LIR_OpBranch::print_instr(outputStream* out) const { + print_condition(out, cond()); out->print(" "); +-#ifdef RISCV ++#if defined(RISCV) || defined(LOONGARCH) + in_opr1()->print(out); out->print(" "); + in_opr2()->print(out); out->print(" "); + #endif +@@ -1963,6 +1972,9 @@ print_bytecode(out, bytecode()); in_opr()->print(out); out->print(" "); result_opr()->print(out); out->print(" "); --#ifdef PPC32 -- if(tmp1()->is_valid()) { -- tmp1()->print(out); out->print(" "); -- tmp2()->print(out); out->print(" "); + if(tmp()->is_valid()) { + tmp()->print(out); out->print(" "); - } --#endif - } ++ } + #ifdef PPC32 + if(tmp1()->is_valid()) { + tmp1()->print(out); out->print(" "); +@@ -2014,7 +2026,7 @@ - void LIR_OpConvert::print_bytecode(outputStream* out, Bytecodes::Code code) { -@@ -1963,6 +2095,19 @@ void LIR_Op3::print_instr(outputStream* out) const { + // LIR_Op2 + void LIR_Op2::print_instr(outputStream* out) const { +-#ifdef RISCV ++#if defined(RISCV) || defined(LOONGARCH) + if (code() == lir_cmp || code() == lir_branch || code() == lir_cond_float_branch) { + #else + if (code() == lir_cmove || code() == lir_cmp) { +@@ -2069,7 +2081,7 @@ + result_opr()->print(out); } +-#ifdef RISCV ++#if defined(RISCV) || defined(LOONGARCH) + // LIR_Op4 + void LIR_Op4::print_instr(outputStream* out) const { + print_condition(out, condition()); out->print(" "); +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/share/c1/c1_LIR.hpp b/src/hotspot/share/c1/c1_LIR.hpp +--- a/src/hotspot/share/c1/c1_LIR.hpp 2024-01-10 05:18:15.000000000 +0800 ++++ b/src/hotspot/share/c1/c1_LIR.hpp 2024-01-31 14:01:11.687429690 +0800 +@@ -22,6 +22,12 @@ + * + */ + ++/* ++ * This file has been modified by Loongson Technology in 2023, These ++ * modifications are Copyright (c) 2022, 2023, Loongson Technology, and are made ++ * available on the same license terms set forth above. ++ */ ++ + #ifndef SHARE_C1_C1_LIR_HPP + #define SHARE_C1_C1_LIR_HPP -+// LIR_Op4 -+void LIR_Op4::print_instr(outputStream* out) const { -+ if (code() == lir_cmp_cmove) { -+ print_condition(out, condition()); out->print(" "); -+ } -+ in_opr1()->print(out); out->print(" "); -+ in_opr2()->print(out); out->print(" "); -+ in_opr3()->print(out); out->print(" "); -+ in_opr4()->print(out); out->print(" "); -+ result_opr()->print(out); -+} -+ -+ - void LIR_OpLock::print_instr(outputStream* out) const { - hdr_opr()->print(out); out->print(" "); - obj_opr()->print(out); out->print(" "); -diff --git a/src/hotspot/share/c1/c1_LIR.hpp b/src/hotspot/share/c1/c1_LIR.hpp -index 2342e6117eb..00c3f938e11 100644 ---- a/src/hotspot/share/c1/c1_LIR.hpp -+++ b/src/hotspot/share/c1/c1_LIR.hpp -@@ -866,9 +866,11 @@ class LIR_OpAllocObj; - class LIR_OpReturn; - class LIR_OpRoundFP; - class LIR_Op2; -+class LIR_OpCmpBranch; +@@ -869,7 +875,7 @@ class LIR_OpDelay; class LIR_Op3; class LIR_OpAllocArray; -+class LIR_Op4; +-#ifdef RISCV ++#if defined(RISCV) || defined(LOONGARCH) + class LIR_Op4; + #endif class LIR_OpCall; - class LIR_OpJavaCall; - class LIR_OpRTCall; -@@ -928,6 +930,8 @@ enum LIR_Code { +@@ -917,7 +923,7 @@ + , lir_null_check + , lir_return + , lir_leal +-#ifndef RISCV ++#if !defined(RISCV) && !defined(LOONGARCH) + , lir_branch + , lir_cond_float_branch + #endif +@@ -931,7 +937,7 @@ + , lir_load_klass + , end_op1 + , begin_op2 +-#ifdef RISCV ++#if defined(RISCV) || defined(LOONGARCH) + , lir_branch + , lir_cond_float_branch + #endif +@@ -939,7 +945,7 @@ , lir_cmp_l2i , lir_ucmp_fd2i , lir_cmp_fd2i -+ , lir_cmp_branch -+ , lir_cmp_float_branch +-#ifndef RISCV ++#if !defined(RISCV) && !defined(LOONGARCH) , lir_cmove + #endif , lir_add - , lir_sub -@@ -956,6 +960,9 @@ enum LIR_Code { +@@ -969,7 +975,7 @@ , lir_fmad , lir_fmaf , end_op3 -+ , begin_op4 -+ , lir_cmp_cmove -+ , end_op4 - , begin_opJavaCall - , lir_static_call - , lir_optvirtual_call -@@ -1121,6 +1128,7 @@ class LIR_Op: public CompilationResourceObj { - virtual LIR_OpAllocObj* as_OpAllocObj() { return NULL; } - virtual LIR_OpRoundFP* as_OpRoundFP() { return NULL; } - virtual LIR_OpBranch* as_OpBranch() { return NULL; } -+ virtual LIR_OpCmpBranch* as_OpCmpBranch() { return NULL; } - virtual LIR_OpReturn* as_OpReturn() { return NULL; } - virtual LIR_OpRTCall* as_OpRTCall() { return NULL; } - virtual LIR_OpConvert* as_OpConvert() { return NULL; } -@@ -1128,6 +1136,7 @@ class LIR_Op: public CompilationResourceObj { +-#ifdef RISCV ++#if defined(RISCV) || defined(LOONGARCH) + , begin_op4 + , lir_cmove + , end_op4 +@@ -1010,7 +1016,7 @@ + , begin_opAssert + , lir_assert + , end_opAssert +-#if defined(RISCV) && defined(INCLUDE_ZGC) ++#if (defined(RISCV) || defined(LOONGARCH)) && defined(INCLUDE_ZGC) + , begin_opZLoadBarrierTest + , lir_zloadbarrier_test + , end_opZLoadBarrierTest +@@ -1151,7 +1157,7 @@ virtual LIR_Op1* as_Op1() { return NULL; } virtual LIR_Op2* as_Op2() { return NULL; } virtual LIR_Op3* as_Op3() { return NULL; } -+ virtual LIR_Op4* as_Op4() { return NULL; } +-#ifdef RISCV ++#if defined(RISCV) || defined(LOONGARCH) + virtual LIR_Op4* as_Op4() { return NULL; } + #endif virtual LIR_OpArrayCopy* as_OpArrayCopy() { return NULL; } - virtual LIR_OpUpdateCRC32* as_OpUpdateCRC32() { return NULL; } - virtual LIR_OpTypeCheck* as_OpTypeCheck() { return NULL; } -@@ -1461,15 +1470,18 @@ class LIR_OpConvert: public LIR_Op1 { +@@ -1447,15 +1453,18 @@ private: Bytecodes::Code _bytecode; ConversionStub* _stub; @@ -115241,142 +114261,123 @@ index 2342e6117eb..00c3f938e11 100644 virtual void emit_code(LIR_Assembler* masm); virtual LIR_OpConvert* as_OpConvert() { return this; } -@@ -1624,7 +1636,7 @@ class LIR_Op2: public LIR_Op { +@@ -1610,7 +1619,7 @@ , _tmp4(LIR_OprFact::illegalOpr) , _tmp5(LIR_OprFact::illegalOpr) , _condition(condition) { -- assert(code == lir_cmp || code == lir_assert, "code check"); -+ assert(code == lir_cmp || code == lir_cmp_branch || code == lir_cmp_float_branch || code == lir_assert, "code check"); +- assert(code == lir_cmp || code == lir_assert RISCV_ONLY(|| code == lir_branch || code == lir_cond_float_branch), "code check"); ++ assert(code == lir_cmp || code == lir_assert RISCV_ONLY(|| code == lir_branch || code == lir_cond_float_branch)LOONGARCH64_ONLY(|| code == lir_branch || code == lir_cond_float_branch), "code check"); } LIR_Op2(LIR_Code code, LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type) -@@ -1656,7 +1668,7 @@ class LIR_Op2: public LIR_Op { +@@ -1642,7 +1651,7 @@ , _tmp4(LIR_OprFact::illegalOpr) , _tmp5(LIR_OprFact::illegalOpr) , _condition(lir_cond_unknown) { -- assert(code != lir_cmp && is_in_range(code, begin_op2, end_op2), "code check"); -+ assert((code != lir_cmp && code != lir_cmp_branch && code != lir_cmp_float_branch) && is_in_range(code, begin_op2, end_op2), "code check"); +- assert(code != lir_cmp && RISCV_ONLY(code != lir_branch && code != lir_cond_float_branch &&) is_in_range(code, begin_op2, end_op2), "code check"); ++ assert(code != lir_cmp && RISCV_ONLY(code != lir_branch && code != lir_cond_float_branch &&)LOONGARCH64_ONLY(code != lir_branch && code != lir_cond_float_branch &&) is_in_range(code, begin_op2, end_op2), "code check"); } LIR_Op2(LIR_Code code, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, LIR_Opr tmp1, LIR_Opr tmp2 = LIR_OprFact::illegalOpr, -@@ -1672,7 +1684,7 @@ class LIR_Op2: public LIR_Op { +@@ -1658,7 +1667,7 @@ , _tmp4(tmp4) , _tmp5(tmp5) , _condition(lir_cond_unknown) { -- assert(code != lir_cmp && is_in_range(code, begin_op2, end_op2), "code check"); -+ assert((code != lir_cmp && code != lir_cmp_branch && code != lir_cmp_float_branch) && is_in_range(code, begin_op2, end_op2), "code check"); +- assert(code != lir_cmp && RISCV_ONLY(code != lir_branch && code != lir_cond_float_branch &&) is_in_range(code, begin_op2, end_op2), "code check"); ++ assert(code != lir_cmp && RISCV_ONLY(code != lir_branch && code != lir_cond_float_branch &&)LOONGARCH64_ONLY(code != lir_branch && code != lir_cond_float_branch &&) is_in_range(code, begin_op2, end_op2), "code check"); } LIR_Opr in_opr1() const { return _opr1; } -@@ -1684,10 +1696,12 @@ class LIR_Op2: public LIR_Op { +@@ -1670,14 +1679,14 @@ LIR_Opr tmp4_opr() const { return _tmp4; } LIR_Opr tmp5_opr() const { return _tmp5; } LIR_Condition condition() const { -- assert(code() == lir_cmp || code() == lir_cmove || code() == lir_assert, "only valid for cmp and cmove and assert"); return _condition; -+ assert(code() == lir_cmp || code() == lir_cmp_branch || code() == lir_cmp_float_branch || code() == lir_cmove || code() == lir_assert, "only valid for cmp and cmove and assert"); -+ return _condition; +-#ifdef RISCV ++#if defined(RISCV) || defined(LOONGARCH) + assert(code() == lir_cmp || code() == lir_branch || code() == lir_cond_float_branch || code() == lir_assert, "only valid for branch and assert"); return _condition; + #else + assert(code() == lir_cmp || code() == lir_cmove || code() == lir_assert, "only valid for cmp and cmove and assert"); return _condition; + #endif } void set_condition(LIR_Condition condition) { -- assert(code() == lir_cmp || code() == lir_cmove, "only valid for cmp and cmove"); _condition = condition; -+ assert(code() == lir_cmp || code() == lir_cmp_branch || code() == lir_cmp_float_branch || code() == lir_cmove, "only valid for cmp and cmove"); -+ _condition = condition; - } - - void set_fpu_stack_size(int size) { _fpu_stack_size = size; } -@@ -1701,6 +1715,43 @@ class LIR_Op2: public LIR_Op { +-#ifdef RISCV ++#if defined(RISCV) || defined(LOONGARCH) + assert(code() == lir_cmp || code() == lir_branch || code() == lir_cond_float_branch, "only valid for branch"); _condition = condition; + #else + assert(code() == lir_cmp || code() == lir_cmove, "only valid for cmp and cmove"); _condition = condition; +@@ -1695,7 +1704,7 @@ virtual void print_instr(outputStream* out) const PRODUCT_RETURN; }; -+class LIR_OpCmpBranch: public LIR_Op2 { -+ friend class LIR_OpVisitState; -+ -+ private: -+ Label* _label; -+ BlockBegin* _block; // if this is a branch to a block, this is the block -+ BlockBegin* _ublock; // if this is a float-branch, this is the unorderd block -+ CodeStub* _stub; // if this is a branch to a stub, this is the stub -+ -+ public: -+ LIR_OpCmpBranch(LIR_Condition cond, LIR_Opr left, LIR_Opr right, Label* lbl, CodeEmitInfo* info = NULL) -+ : LIR_Op2(lir_cmp_branch, cond, left, right, info) -+ , _label(lbl) -+ , _block(NULL) -+ , _ublock(NULL) -+ , _stub(NULL) { } -+ -+ LIR_OpCmpBranch(LIR_Condition cond, LIR_Opr left, LIR_Opr right, CodeStub* stub, CodeEmitInfo* info = NULL); -+ LIR_OpCmpBranch(LIR_Condition cond, LIR_Opr left, LIR_Opr right, BlockBegin* block, CodeEmitInfo* info = NULL); -+ -+ // for unordered comparisons -+ LIR_OpCmpBranch(LIR_Condition cond, LIR_Opr left, LIR_Opr right, BlockBegin* block, BlockBegin* ublock, CodeEmitInfo* info = NULL); -+ -+ Label* label() const { return _label; } -+ BlockBegin* block() const { return _block; } -+ BlockBegin* ublock() const { return _ublock; } -+ CodeStub* stub() const { return _stub; } -+ -+ void change_block(BlockBegin* b); -+ void change_ublock(BlockBegin* b); -+ void negate_cond(); -+ -+ virtual void emit_code(LIR_Assembler* masm); -+ virtual LIR_OpCmpBranch* as_OpCmpBranch() { return this; } -+ virtual void print_instr(outputStream* out) const PRODUCT_RETURN; -+}; -+ - class LIR_OpAllocArray : public LIR_Op { +-#ifdef RISCV ++#if defined(RISCV) || defined(LOONGARCH) + class LIR_OpBranch: public LIR_Op2 { + #else + class LIR_OpBranch: public LIR_Op { +@@ -1703,7 +1712,7 @@ friend class LIR_OpVisitState; -@@ -1765,6 +1816,48 @@ class LIR_Op3: public LIR_Op { + private: +-#ifndef RISCV ++#if !defined(RISCV) && !defined(LOONGARCH) + LIR_Condition _cond; + #endif + Label* _label; +@@ -1713,7 +1722,7 @@ + + public: + LIR_OpBranch(LIR_Condition cond, Label* lbl) +-#ifdef RISCV ++#if defined(RISCV) || defined(LOONGARCH) + : LIR_Op2(lir_branch, cond, LIR_OprFact::illegalOpr, LIR_OprFact::illegalOpr, (CodeEmitInfo*) NULL) + #else + : LIR_Op(lir_branch, LIR_OprFact::illegalOpr, (CodeEmitInfo*) NULL) +@@ -1730,7 +1739,7 @@ + // for unordered comparisons + LIR_OpBranch(LIR_Condition cond, BlockBegin* block, BlockBegin* ublock); + +-#ifdef RISCV ++#if defined(RISCV) || defined(LOONGARCH) + LIR_Condition cond() const { return condition(); } + void set_cond(LIR_Condition cond) { set_condition(cond); } + #else +@@ -1814,7 +1823,7 @@ + virtual void print_instr(outputStream* out) const PRODUCT_RETURN; }; +-#ifdef RISCV ++#if defined(RISCV) || defined(LOONGARCH) + class LIR_Op4: public LIR_Op { + friend class LIR_OpVisitState; + protected: +@@ -2112,7 +2121,7 @@ + const char * _file; + int _line; + #endif +-#ifdef RISCV ++#if defined(RISCV) || defined(LOONGARCH) + LIR_Opr _cmp_opr1; + LIR_Opr _cmp_opr2; + #endif +@@ -2128,7 +2137,7 @@ + } + #endif // PRODUCT -+class LIR_Op4: public LIR_Op { -+ friend class LIR_OpVisitState; -+ -+ private: -+ LIR_Opr _opr1; -+ LIR_Opr _opr2; -+ LIR_Opr _opr3; -+ LIR_Opr _opr4; -+ BasicType _type; -+ LIR_Condition _condition; -+ -+ void verify() const; -+ -+ public: -+ LIR_Op4(LIR_Code code, LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr opr3, LIR_Opr opr4, LIR_Opr result, BasicType type) -+ : LIR_Op(code, result, NULL) -+ , _opr1(opr1) -+ , _opr2(opr2) -+ , _opr3(opr3) -+ , _opr4(opr4) -+ , _type(type) -+ , _condition(condition) { -+ assert(is_in_range(code, begin_op4, end_op4), "code check"); -+ assert(type != T_ILLEGAL, "cmove should have type"); -+ } -+ LIR_Opr in_opr1() const { return _opr1; } -+ LIR_Opr in_opr2() const { return _opr2; } -+ LIR_Opr in_opr3() const { return _opr3; } -+ LIR_Opr in_opr4() const { return _opr4; } -+ BasicType type() const { return _type; } -+ LIR_Condition condition() const { -+ assert(code() == lir_cmp_cmove, "only valid for cmp cmove"); return _condition; -+ } -+ void set_condition(LIR_Condition condition) { -+ assert(code() == lir_cmp_cmove, "only valid for cmp cmove"); _condition = condition; -+ } -+ -+ virtual void emit_code(LIR_Assembler* masm); -+ virtual LIR_Op4* as_Op4() { return this; } -+ virtual void print_instr(outputStream* out) const PRODUCT_RETURN; -+}; -+ - //-------------------------------- - class LabelObj: public CompilationResourceObj { - private: -@@ -2106,7 +2199,9 @@ class LIR_List: public CompilationResourceObj { +-#ifdef RISCV ++#if defined(RISCV) || defined(LOONGARCH) + set_cmp_oprs(op); + // lir_cmp set cmp oprs only on riscv + if (op->code() == lir_cmp) return; +@@ -2150,7 +2159,7 @@ + void set_file_and_line(const char * file, int line); + #endif + +-#ifdef RISCV ++#if defined(RISCV) || defined(LOONGARCH) + void set_cmp_oprs(LIR_Op* op); + #endif + +@@ -2246,7 +2255,9 @@ void safepoint(LIR_Opr tmp, CodeEmitInfo* info) { append(new LIR_Op1(lir_safepoint, tmp, info)); } void return_op(LIR_Opr result) { append(new LIR_OpReturn(result)); } @@ -115387,575 +114388,18 @@ index 2342e6117eb..00c3f938e11 100644 void logical_and (LIR_Opr left, LIR_Opr right, LIR_Opr dst) { append(new LIR_Op2(lir_logic_and, left, right, dst)); } void logical_or (LIR_Opr left, LIR_Opr right, LIR_Opr dst) { append(new LIR_Op2(lir_logic_or, left, right, dst)); } -@@ -2130,6 +2225,15 @@ class LIR_List: public CompilationResourceObj { - cmp(condition, left, LIR_OprFact::intConst(right), info); - } - -+ // machine dependent -+ template -+ void cmp_branch(LIR_Condition condition, LIR_Opr left, LIR_Opr right, T tgt, CodeEmitInfo* info = NULL); -+ template -+ void cmp_branch(LIR_Condition condition, LIR_Opr left, int right, T tgt, CodeEmitInfo* info = NULL) { -+ cmp_branch(condition, left, LIR_OprFact::intConst(right), tgt, info); -+ } -+ void cmp_branch(LIR_Condition condition, LIR_Opr left, LIR_Opr right, BlockBegin* block, BlockBegin* unordered); -+ +@@ -2273,7 +2284,7 @@ void cmp_mem_int(LIR_Condition condition, LIR_Opr base, int disp, int c, CodeEmitInfo* info); void cmp_reg_mem(LIR_Condition condition, LIR_Opr reg, LIR_Address* addr, CodeEmitInfo* info); -@@ -2137,6 +2241,9 @@ class LIR_List: public CompilationResourceObj { - append(new LIR_Op2(lir_cmove, condition, src1, src2, dst, type)); - } - -+ // machine dependent -+ void cmp_cmove(LIR_Condition condition, LIR_Opr left, LIR_Opr right, LIR_Opr src1, LIR_Opr src2, LIR_Opr dst, BasicType type); -+ - void cas_long(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value, - LIR_Opr t1, LIR_Opr t2, LIR_Opr result = LIR_OprFact::illegalOpr); - void cas_obj(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value, -diff --git a/src/hotspot/share/c1/c1_LIRAssembler.cpp b/src/hotspot/share/c1/c1_LIRAssembler.cpp -index 37ce476253d..09053d94b51 100644 ---- a/src/hotspot/share/c1/c1_LIRAssembler.cpp -+++ b/src/hotspot/share/c1/c1_LIRAssembler.cpp -@@ -757,6 +757,18 @@ void LIR_Assembler::emit_op2(LIR_Op2* op) { - } - - -+void LIR_Assembler::emit_op4(LIR_Op4* op) { -+ switch (op->code()) { -+ case lir_cmp_cmove: -+ cmp_cmove(op->condition(), op->in_opr1(), op->in_opr2(), op->in_opr3(), op->in_opr4(), op->result_opr(), op->type()); -+ break; -+ -+ default: -+ Unimplemented(); -+ break; -+ } -+} -+ - void LIR_Assembler::build_frame() { - _masm->build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes()); - } -diff --git a/src/hotspot/share/c1/c1_LIRAssembler.hpp b/src/hotspot/share/c1/c1_LIRAssembler.hpp -index 02c79160d04..d0cceefdda1 100644 ---- a/src/hotspot/share/c1/c1_LIRAssembler.hpp -+++ b/src/hotspot/share/c1/c1_LIRAssembler.hpp -@@ -186,7 +186,9 @@ class LIR_Assembler: public CompilationResourceObj { - void emit_op1(LIR_Op1* op); - void emit_op2(LIR_Op2* op); - void emit_op3(LIR_Op3* op); -+ void emit_op4(LIR_Op4* op); - void emit_opBranch(LIR_OpBranch* op); -+ void emit_opCmpBranch(LIR_OpCmpBranch* op); - void emit_opLabel(LIR_OpLabel* op); - void emit_arraycopy(LIR_OpArrayCopy* op); - void emit_updatecrc32(LIR_OpUpdateCRC32* op); -@@ -219,6 +221,7 @@ class LIR_Assembler: public CompilationResourceObj { - void comp_mem_op(LIR_Opr src, LIR_Opr result, BasicType type, CodeEmitInfo* info); // info set for null exceptions - void comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr result, LIR_Op2* op); - void cmove(LIR_Condition code, LIR_Opr left, LIR_Opr right, LIR_Opr result, BasicType type); -+ void cmp_cmove(LIR_Condition code, LIR_Opr left, LIR_Opr right, LIR_Opr src1, LIR_Opr src2, LIR_Opr result, BasicType type); - - void call( LIR_OpJavaCall* op, relocInfo::relocType rtype); - void ic_call( LIR_OpJavaCall* op); -diff --git a/src/hotspot/share/c1/c1_LIRGenerator.cpp b/src/hotspot/share/c1/c1_LIRGenerator.cpp -index e5e71fab8c1..227ea093a68 100644 ---- a/src/hotspot/share/c1/c1_LIRGenerator.cpp -+++ b/src/hotspot/share/c1/c1_LIRGenerator.cpp -@@ -475,13 +475,11 @@ void LIRGenerator::array_range_check(LIR_Opr array, LIR_Opr index, - CodeEmitInfo* null_check_info, CodeEmitInfo* range_check_info) { - CodeStub* stub = new RangeCheckStub(range_check_info, index, array); - if (index->is_constant()) { -- cmp_mem_int(lir_cond_belowEqual, array, arrayOopDesc::length_offset_in_bytes(), -- index->as_jint(), null_check_info); -- __ branch(lir_cond_belowEqual, stub); // forward branch -+ cmp_mem_int_branch(lir_cond_belowEqual, array, arrayOopDesc::length_offset_in_bytes(), -+ index->as_jint(), stub, null_check_info); // forward branch - } else { -- cmp_reg_mem(lir_cond_aboveEqual, index, array, -- arrayOopDesc::length_offset_in_bytes(), T_INT, null_check_info); -- __ branch(lir_cond_aboveEqual, stub); // forward branch -+ cmp_reg_mem_branch(lir_cond_aboveEqual, index, array, arrayOopDesc::length_offset_in_bytes(), -+ T_INT, stub, null_check_info); // forward branch - } - } - -@@ -489,12 +487,11 @@ void LIRGenerator::array_range_check(LIR_Opr array, LIR_Opr index, - void LIRGenerator::nio_range_check(LIR_Opr buffer, LIR_Opr index, LIR_Opr result, CodeEmitInfo* info) { - CodeStub* stub = new RangeCheckStub(info, index); - if (index->is_constant()) { -- cmp_mem_int(lir_cond_belowEqual, buffer, java_nio_Buffer::limit_offset(), index->as_jint(), info); -- __ branch(lir_cond_belowEqual, stub); // forward branch -+ cmp_mem_int_branch(lir_cond_belowEqual, buffer, java_nio_Buffer::limit_offset(), -+ index->as_jint(), stub, info); // forward branch - } else { -- cmp_reg_mem(lir_cond_aboveEqual, index, buffer, -- java_nio_Buffer::limit_offset(), T_INT, info); -- __ branch(lir_cond_aboveEqual, stub); // forward branch -+ cmp_reg_mem_branch(lir_cond_aboveEqual, index, buffer, -+ java_nio_Buffer::limit_offset(), T_INT, stub, info); // forward branch - } - __ move(index, result); - } -@@ -920,7 +917,7 @@ LIR_Opr LIRGenerator::force_to_spill(LIR_Opr value, BasicType t) { - return tmp; - } - --void LIRGenerator::profile_branch(If* if_instr, If::Condition cond) { -+void LIRGenerator::profile_branch(If* if_instr, If::Condition cond, LIR_Opr left, LIR_Opr right) { - if (if_instr->should_profile()) { - ciMethod* method = if_instr->profiled_method(); - assert(method != NULL, "method should be set if branch is profiled"); -@@ -941,10 +938,17 @@ void LIRGenerator::profile_branch(If* if_instr, If::Condition cond) { - __ metadata2reg(md->constant_encoding(), md_reg); - - LIR_Opr data_offset_reg = new_pointer_register(); -- __ cmove(lir_cond(cond), -- LIR_OprFact::intptrConst(taken_count_offset), -- LIR_OprFact::intptrConst(not_taken_count_offset), -- data_offset_reg, as_BasicType(if_instr->x()->type())); -+ if (left == LIR_OprFact::illegalOpr && right == LIR_OprFact::illegalOpr) { -+ __ cmove(lir_cond(cond), -+ LIR_OprFact::intptrConst(taken_count_offset), -+ LIR_OprFact::intptrConst(not_taken_count_offset), -+ data_offset_reg, as_BasicType(if_instr->x()->type())); -+ } else { -+ __ cmp_cmove(lir_cond(cond), left, right, -+ LIR_OprFact::intptrConst(taken_count_offset), -+ LIR_OprFact::intptrConst(not_taken_count_offset), -+ data_offset_reg, as_BasicType(if_instr->x()->type())); -+ } - - // MDO cells are intptr_t, so the data_reg width is arch-dependent. - LIR_Opr data_reg = new_pointer_register(); -@@ -1294,8 +1298,8 @@ void LIRGenerator::do_isPrimitive(Intrinsic* x) { - } - - __ move(new LIR_Address(rcvr.result(), java_lang_Class::klass_offset(), T_ADDRESS), temp, info); -- __ cmp(lir_cond_notEqual, temp, LIR_OprFact::metadataConst(0)); -- __ cmove(lir_cond_notEqual, LIR_OprFact::intConst(0), LIR_OprFact::intConst(1), result, T_BOOLEAN); -+ __ cmp_cmove(lir_cond_notEqual, temp, LIR_OprFact::metadataConst(0), -+ LIR_OprFact::intConst(0), LIR_OprFact::intConst(1), result, T_BOOLEAN); - } - - // Example: Foo.class.getModifiers() -@@ -1327,8 +1331,8 @@ void LIRGenerator::do_getModifiers(Intrinsic* x) { - - // Check if this is a Java mirror of primitive type, and select the appropriate klass. - LIR_Opr klass = new_register(T_METADATA); -- __ cmp(lir_cond_equal, recv_klass, LIR_OprFact::metadataConst(0)); -- __ cmove(lir_cond_equal, prim_klass, recv_klass, klass, T_ADDRESS); -+ __ cmp_cmove(lir_cond_equal, recv_klass, LIR_OprFact::metadataConst(0), -+ prim_klass, recv_klass, klass, T_ADDRESS); - - // Get the answer. - __ move(new LIR_Address(klass, in_bytes(Klass::modifier_flags_offset()), T_INT), result); -@@ -1360,8 +1364,7 @@ void LIRGenerator::do_getObjectSize(Intrinsic* x) { - LabelObj* L_done = new LabelObj(); - LabelObj* L_array = new LabelObj(); - -- __ cmp(lir_cond_lessEqual, layout, 0); -- __ branch(lir_cond_lessEqual, L_array->label()); -+ __ cmp_branch(lir_cond_lessEqual, layout, 0, L_array->label()); - - // Instance case: the layout helper gives us instance size almost directly, - // but we need to mask out the _lh_instance_slow_path_bit. -@@ -1414,8 +1417,7 @@ void LIRGenerator::do_getObjectSize(Intrinsic* x) { - LabelObj* L_shift_exit = new LabelObj(); - - __ branch_destination(L_shift_loop->label()); -- __ cmp(lir_cond_equal, layout, 0); -- __ branch(lir_cond_equal, L_shift_exit->label()); -+ __ cmp_branch(lir_cond_equal, layout, 0, L_shift_exit->label()); - - #ifdef _LP64 - __ shift_left(length, 1, length); -@@ -1714,8 +1716,8 @@ void LIRGenerator::do_StoreIndexed(StoreIndexed* x) { - - if (GenerateRangeChecks && needs_range_check) { - if (use_length) { -- __ cmp(lir_cond_belowEqual, length.result(), index.result()); -- __ branch(lir_cond_belowEqual, new RangeCheckStub(range_check_info, index.result(), array.result())); -+ CodeStub* stub = new RangeCheckStub(range_check_info, index.result(), array.result()); -+ __ cmp_branch(lir_cond_belowEqual, length.result(), index.result(), stub); - } else { - array_range_check(array.result(), index.result(), null_check_info, range_check_info); - // range_check also does the null check -@@ -1893,12 +1895,11 @@ void LIRGenerator::do_NIOCheckIndex(Intrinsic* x) { - CodeEmitInfo* info = state_for(x); - CodeStub* stub = new RangeCheckStub(info, index.result()); - if (index.result()->is_constant()) { -- cmp_mem_int(lir_cond_belowEqual, buf.result(), java_nio_Buffer::limit_offset(), index.result()->as_jint(), info); -- __ branch(lir_cond_belowEqual, stub); -+ cmp_mem_int_branch(lir_cond_belowEqual, buf.result(), java_nio_Buffer::limit_offset(), -+ index.result()->as_jint(), stub, info); - } else { -- cmp_reg_mem(lir_cond_aboveEqual, index.result(), buf.result(), -- java_nio_Buffer::limit_offset(), T_INT, info); -- __ branch(lir_cond_aboveEqual, stub); -+ cmp_reg_mem_branch(lir_cond_aboveEqual, index.result(), buf.result(), -+ java_nio_Buffer::limit_offset(), T_INT, stub, info); - } - __ move(index.result(), result); - } else { -@@ -1976,8 +1977,8 @@ void LIRGenerator::do_LoadIndexed(LoadIndexed* x) { - } else if (use_length) { - // TODO: use a (modified) version of array_range_check that does not require a - // constant length to be loaded to a register -- __ cmp(lir_cond_belowEqual, length.result(), index.result()); -- __ branch(lir_cond_belowEqual, new RangeCheckStub(range_check_info, index.result(), array.result())); -+ CodeStub* stub = new RangeCheckStub(range_check_info, index.result(), array.result()); -+ __ cmp_branch(lir_cond_belowEqual, length.result(), index.result(), stub); - } else { - array_range_check(array.result(), index.result(), null_check_info, range_check_info); - // The range check performs the null check, so clear it out for the load -@@ -2352,19 +2353,14 @@ void LIRGenerator::do_SwitchRanges(SwitchRangeArray* x, LIR_Opr value, BlockBegi - int high_key = one_range->high_key(); - BlockBegin* dest = one_range->sux(); - if (low_key == high_key) { -- __ cmp(lir_cond_equal, value, low_key); -- __ branch(lir_cond_equal, dest); -+ __ cmp_branch(lir_cond_equal, value, low_key, dest); - } else if (high_key - low_key == 1) { -- __ cmp(lir_cond_equal, value, low_key); -- __ branch(lir_cond_equal, dest); -- __ cmp(lir_cond_equal, value, high_key); -- __ branch(lir_cond_equal, dest); -+ __ cmp_branch(lir_cond_equal, value, low_key, dest); -+ __ cmp_branch(lir_cond_equal, value, high_key, dest); - } else { - LabelObj* L = new LabelObj(); -- __ cmp(lir_cond_less, value, low_key); -- __ branch(lir_cond_less, L->label()); -- __ cmp(lir_cond_lessEqual, value, high_key); -- __ branch(lir_cond_lessEqual, dest); -+ __ cmp_branch(lir_cond_less, value, low_key, L->label()); -+ __ cmp_branch(lir_cond_lessEqual, value, high_key, dest); - __ branch_destination(L->label()); - } - } -@@ -2464,12 +2460,11 @@ void LIRGenerator::do_TableSwitch(TableSwitch* x) { - __ move(LIR_OprFact::intptrConst(default_count_offset), data_offset_reg); - for (int i = 0; i < len; i++) { - int count_offset = md->byte_offset_of_slot(data, MultiBranchData::case_count_offset(i)); -- __ cmp(lir_cond_equal, value, i + lo_key); - __ move(data_offset_reg, tmp_reg); -- __ cmove(lir_cond_equal, -- LIR_OprFact::intptrConst(count_offset), -- tmp_reg, -- data_offset_reg, T_INT); -+ __ cmp_cmove(lir_cond_equal, value, LIR_OprFact::intConst(i + lo_key), -+ LIR_OprFact::intptrConst(count_offset), -+ tmp_reg, -+ data_offset_reg, T_INT); - } - - LIR_Opr data_reg = new_pointer_register(); -@@ -2483,8 +2478,7 @@ void LIRGenerator::do_TableSwitch(TableSwitch* x) { - do_SwitchRanges(create_lookup_ranges(x), value, x->default_sux()); - } else { - for (int i = 0; i < len; i++) { -- __ cmp(lir_cond_equal, value, i + lo_key); -- __ branch(lir_cond_equal, x->sux_at(i)); -+ __ cmp_branch(lir_cond_equal, value, i + lo_key, x->sux_at(i)); - } - __ jump(x->default_sux()); - } -@@ -2522,12 +2516,11 @@ void LIRGenerator::do_LookupSwitch(LookupSwitch* x) { - __ move(LIR_OprFact::intptrConst(default_count_offset), data_offset_reg); - for (int i = 0; i < len; i++) { - int count_offset = md->byte_offset_of_slot(data, MultiBranchData::case_count_offset(i)); -- __ cmp(lir_cond_equal, value, x->key_at(i)); - __ move(data_offset_reg, tmp_reg); -- __ cmove(lir_cond_equal, -- LIR_OprFact::intptrConst(count_offset), -- tmp_reg, -- data_offset_reg, T_INT); -+ __ cmp_cmove(lir_cond_equal, value, LIR_OprFact::intConst(x->key_at(i)), -+ LIR_OprFact::intptrConst(count_offset), -+ tmp_reg, -+ data_offset_reg, T_INT); - } - - LIR_Opr data_reg = new_pointer_register(); -@@ -2542,8 +2535,7 @@ void LIRGenerator::do_LookupSwitch(LookupSwitch* x) { - } else { - int len = x->length(); - for (int i = 0; i < len; i++) { -- __ cmp(lir_cond_equal, value, x->key_at(i)); -- __ branch(lir_cond_equal, x->sux_at(i)); -+ __ cmp_branch(lir_cond_equal, value, x->key_at(i), x->sux_at(i)); - } - __ jump(x->default_sux()); - } -@@ -3038,8 +3030,8 @@ void LIRGenerator::do_IfOp(IfOp* x) { - f_val.dont_load_item(); - LIR_Opr reg = rlock_result(x); - -- __ cmp(lir_cond(x->cond()), left.result(), right.result()); -- __ cmove(lir_cond(x->cond()), t_val.result(), f_val.result(), reg, as_BasicType(x->x()->type())); -+ __ cmp_cmove(lir_cond(x->cond()), left.result(), right.result(), -+ t_val.result(), f_val.result(), reg, as_BasicType(x->x()->type())); - } - - #ifdef JFR_HAVE_INTRINSICS -@@ -3056,8 +3048,7 @@ void LIRGenerator::do_getEventWriter(Intrinsic* x) { - __ move(LIR_OprFact::oopConst(NULL), result); - LIR_Opr jobj = new_register(T_METADATA); - __ move_wide(jobj_addr, jobj); -- __ cmp(lir_cond_equal, jobj, LIR_OprFact::metadataConst(0)); -- __ branch(lir_cond_equal, L_end->label()); -+ __ cmp_branch(lir_cond_equal, jobj, LIR_OprFact::metadataConst(0), L_end->label()); - - access_load(IN_NATIVE, T_OBJECT, LIR_OprFact::address(new LIR_Address(jobj, T_OBJECT)), result); - -@@ -3365,21 +3356,24 @@ void LIRGenerator::do_ProfileInvoke(ProfileInvoke* x) { - - void LIRGenerator::increment_backedge_counter_conditionally(LIR_Condition cond, LIR_Opr left, LIR_Opr right, CodeEmitInfo* info, int left_bci, int right_bci, int bci) { - if (compilation()->count_backedges()) { -+ LIR_Opr step = new_register(T_INT); -+ LIR_Opr plus_one = LIR_OprFact::intConst(InvocationCounter::count_increment); -+ LIR_Opr zero = LIR_OprFact::intConst(0); - #if defined(X86) && !defined(_LP64) - // BEWARE! On 32-bit x86 cmp clobbers its left argument so we need a temp copy. - LIR_Opr left_copy = new_register(left->type()); - __ move(left, left_copy); - __ cmp(cond, left_copy, right); --#else -- __ cmp(cond, left, right); --#endif -- LIR_Opr step = new_register(T_INT); -- LIR_Opr plus_one = LIR_OprFact::intConst(InvocationCounter::count_increment); -- LIR_Opr zero = LIR_OprFact::intConst(0); - __ cmove(cond, - (left_bci < bci) ? plus_one : zero, - (right_bci < bci) ? plus_one : zero, - step, left->type()); -+#else -+ __ cmp_cmove(cond, left, right, -+ (left_bci < bci) ? plus_one : zero, -+ (right_bci < bci) ? plus_one : zero, -+ step, left->type()); -+#endif - increment_backedge_counter(info, step, bci); - } - } -@@ -3418,8 +3412,7 @@ void LIRGenerator::decrement_age(CodeEmitInfo* info) { - // DeoptimizeStub will reexecute from the current state in code info. - CodeStub* deopt = new DeoptimizeStub(info, Deoptimization::Reason_tenured, - Deoptimization::Action_make_not_entrant); -- __ cmp(lir_cond_lessEqual, result, LIR_OprFact::intConst(0)); -- __ branch(lir_cond_lessEqual, deopt); -+ __ cmp_branch(lir_cond_lessEqual, result, LIR_OprFact::intConst(0), deopt); - } - } - -@@ -3465,8 +3458,7 @@ void LIRGenerator::increment_event_counter_impl(CodeEmitInfo* info, - int freq = frequency << InvocationCounter::count_shift; - if (freq == 0) { - if (!step->is_constant()) { -- __ cmp(lir_cond_notEqual, step, LIR_OprFact::intConst(0)); -- __ branch(lir_cond_notEqual, overflow); -+ __ cmp_branch(lir_cond_notEqual, step, LIR_OprFact::intConst(0), overflow); - } else { - __ branch(lir_cond_always, overflow); - } -@@ -3474,12 +3466,11 @@ void LIRGenerator::increment_event_counter_impl(CodeEmitInfo* info, - LIR_Opr mask = load_immediate(freq, T_INT); - if (!step->is_constant()) { - // If step is 0, make sure the overflow check below always fails -- __ cmp(lir_cond_notEqual, step, LIR_OprFact::intConst(0)); -- __ cmove(lir_cond_notEqual, result, LIR_OprFact::intConst(InvocationCounter::count_increment), result, T_INT); -+ __ cmp_cmove(lir_cond_notEqual, step, LIR_OprFact::intConst(0), -+ result, LIR_OprFact::intConst(InvocationCounter::count_increment), result, T_INT); - } - __ logical_and(result, mask, result); -- __ cmp(lir_cond_equal, result, LIR_OprFact::intConst(0)); -- __ branch(lir_cond_equal, overflow); -+ __ cmp_branch(lir_cond_equal, result, LIR_OprFact::intConst(0), overflow); - } - __ branch_destination(overflow->continuation()); - } -@@ -3592,8 +3583,7 @@ void LIRGenerator::do_RangeCheckPredicate(RangeCheckPredicate *x) { - CodeEmitInfo *info = state_for(x, x->state()); - CodeStub* stub = new PredicateFailedStub(info); - -- __ cmp(lir_cond(cond), left, right); -- __ branch(lir_cond(cond), stub); -+ __ cmp_branch(lir_cond(cond), left, right, stub); - } - } - -@@ -3747,8 +3737,8 @@ LIR_Opr LIRGenerator::mask_boolean(LIR_Opr array, LIR_Opr value, CodeEmitInfo*& - __ move(new LIR_Address(klass, in_bytes(Klass::layout_helper_offset()), T_INT), layout); - int diffbit = Klass::layout_helper_boolean_diffbit(); - __ logical_and(layout, LIR_OprFact::intConst(diffbit), layout); -- __ cmp(lir_cond_notEqual, layout, LIR_OprFact::intConst(0)); -- __ cmove(lir_cond_notEqual, value_fixed, value, value_fixed, T_BYTE); -+ __ cmp_cmove(lir_cond_notEqual, layout, LIR_OprFact::intConst(0), -+ value_fixed, value, value_fixed, T_BYTE); - value = value_fixed; - return value; - } -diff --git a/src/hotspot/share/c1/c1_LIRGenerator.hpp b/src/hotspot/share/c1/c1_LIRGenerator.hpp -index 67c986cb4e7..cdd97fc386d 100644 ---- a/src/hotspot/share/c1/c1_LIRGenerator.hpp -+++ b/src/hotspot/share/c1/c1_LIRGenerator.hpp -@@ -365,8 +365,10 @@ class LIRGenerator: public InstructionVisitor, public BlockClosure { - void new_instance (LIR_Opr dst, ciInstanceKlass* klass, bool is_unresolved, LIR_Opr scratch1, LIR_Opr scratch2, LIR_Opr scratch3, LIR_Opr scratch4, LIR_Opr klass_reg, CodeEmitInfo* info); - - // machine dependent -- void cmp_mem_int(LIR_Condition condition, LIR_Opr base, int disp, int c, CodeEmitInfo* info); -- void cmp_reg_mem(LIR_Condition condition, LIR_Opr reg, LIR_Opr base, int disp, BasicType type, CodeEmitInfo* info); -+ template -+ void cmp_mem_int_branch(LIR_Condition condition, LIR_Opr base, int disp, int c, T tgt, CodeEmitInfo* info); -+ template -+ void cmp_reg_mem_branch(LIR_Condition condition, LIR_Opr reg, LIR_Opr base, int disp, BasicType type, T tgt, CodeEmitInfo* info); - - void arraycopy_helper(Intrinsic* x, int* flags, ciArrayKlass** expected_type); - -@@ -393,7 +395,7 @@ class LIRGenerator: public InstructionVisitor, public BlockClosure { - - LIR_Opr safepoint_poll_register(); - -- void profile_branch(If* if_instr, If::Condition cond); -+ void profile_branch(If* if_instr, If::Condition cond, LIR_Opr left = LIR_OprFact::illegalOpr, LIR_Opr right = LIR_OprFact::illegalOpr); - void increment_event_counter_impl(CodeEmitInfo* info, - ciMethod *method, LIR_Opr step, int frequency, - int bci, bool backedge, bool notify); -diff --git a/src/hotspot/share/c1/c1_LinearScan.cpp b/src/hotspot/share/c1/c1_LinearScan.cpp -index 84846e8e43d..f81a440d237 100644 ---- a/src/hotspot/share/c1/c1_LinearScan.cpp -+++ b/src/hotspot/share/c1/c1_LinearScan.cpp -@@ -35,6 +35,12 @@ - #include "runtime/timerTrace.hpp" - #include "utilities/bitMap.inline.hpp" - -+/* -+ * This file has been modified by Loongson Technology in 2022, These -+ * modifications are Copyright (c) 2022, Loongson Technology, and are made -+ * available on the same license terms set forth above. -+ */ -+ - #ifndef PRODUCT - - static LinearScanStatistic _stat_before_alloc; -@@ -1256,6 +1262,23 @@ void LinearScan::add_register_hints(LIR_Op* op) { - } - break; - } -+ case lir_cmp_cmove: { -+ assert(op->as_Op4() != NULL, "lir_cmp_cmove must be LIR_Op4"); -+ LIR_Op4* cmove = (LIR_Op4*)op; -+ -+ LIR_Opr move_from = cmove->in_opr3(); -+ LIR_Opr move_to = cmove->result_opr(); -+ -+ if (move_to->is_register() && move_from->is_register()) { -+ Interval* from = interval_at(reg_num(move_from)); -+ Interval* to = interval_at(reg_num(move_to)); -+ if (from != NULL && to != NULL) { -+ to->set_register_hint(from); -+ TRACE_LINEAR_SCAN(4, tty->print_cr("operation at op_id %d: added hint from interval %d to %d", cmove->id(), from->reg_num(), to->reg_num())); -+ } -+ } -+ break; -+ } - default: - break; - } -@@ -3386,7 +3409,9 @@ void LinearScan::verify_no_oops_in_fixed_intervals() { - check_live = (move->patch_code() == lir_patch_none); - } - LIR_OpBranch* branch = op->as_OpBranch(); -- if (branch != NULL && branch->stub() != NULL && branch->stub()->is_exception_throw_stub()) { -+ LIR_OpCmpBranch* cmp_branch = op->as_OpCmpBranch(); -+ if ((branch != NULL && branch->stub() != NULL && branch->stub()->is_exception_throw_stub()) || -+ (cmp_branch != NULL && cmp_branch->stub() != NULL && cmp_branch->stub()->is_exception_throw_stub())) { - // Don't bother checking the stub in this case since the - // exception stub will never return to normal control flow. - check_live = false; -@@ -6276,6 +6301,16 @@ void ControlFlowOptimizer::substitute_branch_target(BlockBegin* block, BlockBegi - assert(op->as_OpBranch() != NULL, "branch must be of type LIR_OpBranch"); - LIR_OpBranch* branch = (LIR_OpBranch*)op; - -+ if (branch->block() == target_from) { -+ branch->change_block(target_to); -+ } -+ if (branch->ublock() == target_from) { -+ branch->change_ublock(target_to); -+ } -+ } else if (op->code() == lir_cmp_branch || op->code() == lir_cmp_float_branch) { -+ assert(op->as_OpCmpBranch() != NULL, "branch must be of type LIR_OpCmpBranch"); -+ LIR_OpCmpBranch* branch = (LIR_OpCmpBranch*)op; -+ - if (branch->block() == target_from) { - branch->change_block(target_to); - } -@@ -6404,6 +6439,20 @@ void ControlFlowOptimizer::delete_unnecessary_jumps(BlockList* code) { - } - } - } -+ } else if (prev_op->code() == lir_cmp_branch || prev_op->code() == lir_cmp_float_branch) { -+ assert(prev_op->as_OpCmpBranch() != NULL, "branch must be of type LIR_OpCmpBranch"); -+ LIR_OpCmpBranch* prev_branch = (LIR_OpCmpBranch*)prev_op; -+ -+ if (prev_branch->stub() == NULL) { -+ if (prev_branch->block() == code->at(i + 1) && prev_branch->info() == NULL) { -+ TRACE_LINEAR_SCAN(3, tty->print_cr("Negating conditional branch and deleting unconditional branch at end of block B%d", block->block_id())); -+ -+ // eliminate a conditional branch to the immediate successor -+ prev_branch->change_block(last_branch->block()); -+ prev_branch->negate_cond(); -+ instructions->trunc_to(instructions->length() - 1); -+ } -+ } - } - } - } -@@ -6479,6 +6528,13 @@ void ControlFlowOptimizer::verify(BlockList* code) { - assert(op_branch->block() == NULL || code->find(op_branch->block()) != -1, "branch target not valid"); - assert(op_branch->ublock() == NULL || code->find(op_branch->ublock()) != -1, "branch target not valid"); - } -+ -+ LIR_OpCmpBranch* op_cmp_branch = instructions->at(j)->as_OpCmpBranch(); -+ -+ if (op_cmp_branch != NULL) { -+ assert(op_cmp_branch->block() == NULL || code->find(op_cmp_branch->block()) != -1, "branch target not valid"); -+ assert(op_cmp_branch->ublock() == NULL || code->find(op_cmp_branch->ublock()) != -1, "branch target not valid"); -+ } - } - - for (j = 0; j < block->number_of_sux() - 1; j++) { -@@ -6722,6 +6778,24 @@ void LinearScanStatistic::collect(LinearScan* allocator) { - break; - } - -+ case lir_cmp_branch: -+ case lir_cmp_float_branch: { -+ LIR_OpCmpBranch* branch = op->as_OpCmpBranch(); -+ if (branch->block() == NULL) { -+ inc_counter(counter_stub_branch); -+ } else { -+ inc_counter(counter_cond_branch); -+ } -+ inc_counter(counter_cmp); -+ break; -+ } -+ -+ case lir_cmp_cmove: { -+ inc_counter(counter_misc_inst); -+ inc_counter(counter_cmp); -+ break; -+ } -+ - case lir_neg: - case lir_add: - case lir_sub: -diff --git a/src/hotspot/share/code/nmethod.cpp b/src/hotspot/share/code/nmethod.cpp -index 7fe1d05ff1c..4156c029bc1 100644 ---- a/src/hotspot/share/code/nmethod.cpp -+++ b/src/hotspot/share/code/nmethod.cpp +-#ifdef RISCV ++#if defined(RISCV) || defined(LOONGARCH) + void cmove(LIR_Condition condition, LIR_Opr src1, LIR_Opr src2, LIR_Opr dst, BasicType type, + LIR_Opr cmp_opr1 = LIR_OprFact::illegalOpr, LIR_Opr cmp_opr2 = LIR_OprFact::illegalOpr) { + append(new LIR_Op4(lir_cmove, condition, src1, src2, cmp_opr1, cmp_opr2, dst, type)); +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/share/code/nmethod.cpp b/src/hotspot/share/code/nmethod.cpp +--- a/src/hotspot/share/code/nmethod.cpp 2024-01-10 05:18:15.000000000 +0800 ++++ b/src/hotspot/share/code/nmethod.cpp 2024-01-31 14:01:11.714096611 +0800 @@ -22,6 +22,12 @@ * */ @@ -115969,7 +114413,7 @@ index 7fe1d05ff1c..4156c029bc1 100644 #include "precompiled.hpp" #include "jvm.h" #include "asm/assembler.inline.hpp" -@@ -2532,7 +2538,8 @@ void nmethod::verify_scopes() { +@@ -2540,7 +2546,8 @@ //verify_interrupt_point(iter.addr()); break; case relocInfo::runtime_call_type: @@ -115979,7 +114423,7 @@ index 7fe1d05ff1c..4156c029bc1 100644 address destination = iter.reloc()->value(); // Right now there is no way to find out which entries support // an interrupt point. It would be nice if we had this -@@ -3094,7 +3101,8 @@ const char* nmethod::reloc_string_for(u_char* begin, u_char* end) { +@@ -3108,7 +3115,8 @@ return st.as_string(); } case relocInfo::runtime_call_type: @@ -115989,11 +114433,10 @@ index 7fe1d05ff1c..4156c029bc1 100644 stringStream st; st.print("runtime_call"); CallRelocation* r = (CallRelocation*)iter.reloc(); -diff --git a/src/hotspot/share/code/relocInfo.cpp b/src/hotspot/share/code/relocInfo.cpp -index 47769c53a5b..ed69d18d759 100644 ---- a/src/hotspot/share/code/relocInfo.cpp -+++ b/src/hotspot/share/code/relocInfo.cpp -@@ -402,6 +402,7 @@ void virtual_call_Relocation::unpack_data() { +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/share/code/relocInfo.cpp b/src/hotspot/share/code/relocInfo.cpp +--- a/src/hotspot/share/code/relocInfo.cpp 2024-01-10 05:18:15.000000000 +0800 ++++ b/src/hotspot/share/code/relocInfo.cpp 2024-01-31 14:01:11.714096611 +0800 +@@ -402,6 +402,7 @@ _cached_value = x0==0? NULL: address_from_scaled_offset(x0, point); } @@ -116001,7 +114444,7 @@ index 47769c53a5b..ed69d18d759 100644 void runtime_call_w_cp_Relocation::pack_data_to(CodeSection * dest) { short* p = pack_1_int_to((short *)dest->locs_end(), (jint)(_offset >> 2)); dest->set_locs_end((relocInfo*) p); -@@ -410,6 +411,7 @@ void runtime_call_w_cp_Relocation::pack_data_to(CodeSection * dest) { +@@ -410,6 +411,7 @@ void runtime_call_w_cp_Relocation::unpack_data() { _offset = unpack_1_int() << 2; } @@ -116009,7 +114452,7 @@ index 47769c53a5b..ed69d18d759 100644 void static_stub_Relocation::pack_data_to(CodeSection* dest) { short* p = (short*) dest->locs_end(); -@@ -874,7 +876,7 @@ void RelocIterator::print_current() { +@@ -874,7 +876,7 @@ break; } case relocInfo::runtime_call_type: @@ -116018,11 +114461,10 @@ index 47769c53a5b..ed69d18d759 100644 { CallRelocation* r = (CallRelocation*) reloc(); tty->print(" | [destination=" INTPTR_FORMAT "]", p2i(r->destination())); -diff --git a/src/hotspot/share/code/relocInfo.hpp b/src/hotspot/share/code/relocInfo.hpp -index 55d4ac7c62d..b1c34733021 100644 ---- a/src/hotspot/share/code/relocInfo.hpp -+++ b/src/hotspot/share/code/relocInfo.hpp -@@ -266,7 +266,11 @@ class relocInfo { +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/share/code/relocInfo.hpp b/src/hotspot/share/code/relocInfo.hpp +--- a/src/hotspot/share/code/relocInfo.hpp 2024-01-10 05:18:15.000000000 +0800 ++++ b/src/hotspot/share/code/relocInfo.hpp 2024-01-31 14:01:11.714096611 +0800 +@@ -266,7 +266,11 @@ poll_return_type = 11, // polling instruction for safepoints at return metadata_type = 12, // metadata that used to be oops trampoline_stub_type = 13, // stub-entry for trampoline @@ -116034,7 +114476,7 @@ index 55d4ac7c62d..b1c34733021 100644 data_prefix_tag = 15, // tag for a prefix (carries data arguments) type_mask = 15 // A mask which selects only the above values }; -@@ -300,13 +304,13 @@ class relocInfo { +@@ -300,13 +304,13 @@ visitor(static_call) \ visitor(static_stub) \ visitor(runtime_call) \ @@ -116050,7 +114492,7 @@ index 55d4ac7c62d..b1c34733021 100644 public: -@@ -1146,6 +1150,16 @@ class runtime_call_Relocation : public CallRelocation { +@@ -1146,6 +1150,16 @@ }; @@ -116067,7 +114509,7 @@ index 55d4ac7c62d..b1c34733021 100644 class runtime_call_w_cp_Relocation : public CallRelocation { public: static RelocationHolder spec() { -@@ -1175,6 +1189,7 @@ class runtime_call_w_cp_Relocation : public CallRelocation { +@@ -1175,6 +1189,7 @@ void pack_data_to(CodeSection * dest); void unpack_data(); }; @@ -116075,10 +114517,9 @@ index 55d4ac7c62d..b1c34733021 100644 // Trampoline Relocations. // A trampoline allows to encode a small branch in the code, even if there -diff --git a/src/hotspot/share/code/vtableStubs.cpp b/src/hotspot/share/code/vtableStubs.cpp -index d490adb3eef..0b1d7dc0a27 100644 ---- a/src/hotspot/share/code/vtableStubs.cpp -+++ b/src/hotspot/share/code/vtableStubs.cpp +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/share/code/vtableStubs.cpp b/src/hotspot/share/code/vtableStubs.cpp +--- a/src/hotspot/share/code/vtableStubs.cpp 2024-01-10 05:18:15.000000000 +0800 ++++ b/src/hotspot/share/code/vtableStubs.cpp 2024-01-31 14:01:11.714096611 +0800 @@ -22,6 +22,12 @@ * */ @@ -116092,7 +114533,7 @@ index d490adb3eef..0b1d7dc0a27 100644 #include "precompiled.hpp" #include "code/vtableStubs.hpp" #include "compiler/compileBroker.hpp" -@@ -102,7 +108,11 @@ int VtableStubs::_itab_stub_size = 0; +@@ -102,7 +108,11 @@ #if defined(PRODUCT) // These values are good for the PRODUCT case (no tracing). @@ -116104,7 +114545,7 @@ index d490adb3eef..0b1d7dc0a27 100644 static const int first_itableStub_size = 256; #else // These values are good for the non-PRODUCT case (when tracing can be switched on). -@@ -113,6 +123,7 @@ int VtableStubs::_itab_stub_size = 0; +@@ -113,6 +123,7 @@ // vtable itable // aarch64: 460 324 // arm: ? ? @@ -116112,43 +114553,9 @@ index d490adb3eef..0b1d7dc0a27 100644 // ppc (linux, BE): 404 288 // ppc (linux, LE): 356 276 // ppc (AIX): 416 296 -diff --git a/src/hotspot/share/gc/g1/c1/g1BarrierSetC1.cpp b/src/hotspot/share/gc/g1/c1/g1BarrierSetC1.cpp -index 60a213aec77..4970790b873 100644 ---- a/src/hotspot/share/gc/g1/c1/g1BarrierSetC1.cpp -+++ b/src/hotspot/share/gc/g1/c1/g1BarrierSetC1.cpp -@@ -74,7 +74,6 @@ void G1BarrierSetC1::pre_barrier(LIRAccess& access, LIR_Opr addr_opr, - // Read the marking-in-progress flag. - LIR_Opr flag_val = gen->new_register(T_INT); - __ load(mark_active_flag_addr, flag_val); -- __ cmp(lir_cond_notEqual, flag_val, LIR_OprFact::intConst(0)); - - LIR_PatchCode pre_val_patch_code = lir_patch_none; - -@@ -103,7 +102,7 @@ void G1BarrierSetC1::pre_barrier(LIRAccess& access, LIR_Opr addr_opr, - slow = new G1PreBarrierStub(pre_val); - } - -- __ branch(lir_cond_notEqual, slow); -+ __ cmp_branch(lir_cond_notEqual, flag_val, LIR_OprFact::intConst(0), slow); - __ branch_destination(slow->continuation()); - } - -@@ -168,10 +167,8 @@ void G1BarrierSetC1::post_barrier(LIRAccess& access, LIR_OprDesc* addr, LIR_OprD - } - assert(new_val->is_register(), "must be a register at this point"); - -- __ cmp(lir_cond_notEqual, xor_shift_res, LIR_OprFact::intptrConst(NULL_WORD)); -- - CodeStub* slow = new G1PostBarrierStub(addr, new_val); -- __ branch(lir_cond_notEqual, slow); -+ __ cmp_branch(lir_cond_notEqual, xor_shift_res, LIR_OprFact::intptrConst(NULL_WORD), slow); - __ branch_destination(slow->continuation()); - } - -diff --git a/src/hotspot/share/gc/g1/g1ParScanThreadState.inline.hpp b/src/hotspot/share/gc/g1/g1ParScanThreadState.inline.hpp -index f0944108810..a8c1f97a80e 100644 ---- a/src/hotspot/share/gc/g1/g1ParScanThreadState.inline.hpp -+++ b/src/hotspot/share/gc/g1/g1ParScanThreadState.inline.hpp +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/share/gc/g1/g1ParScanThreadState.inline.hpp b/src/hotspot/share/gc/g1/g1ParScanThreadState.inline.hpp +--- a/src/hotspot/share/gc/g1/g1ParScanThreadState.inline.hpp 2024-01-10 05:18:15.000000000 +0800 ++++ b/src/hotspot/share/gc/g1/g1ParScanThreadState.inline.hpp 2024-01-31 14:01:11.730763436 +0800 @@ -22,6 +22,12 @@ * */ @@ -116162,7 +114569,7 @@ index f0944108810..a8c1f97a80e 100644 #ifndef SHARE_GC_G1_G1PARSCANTHREADSTATE_INLINE_HPP #define SHARE_GC_G1_G1PARSCANTHREADSTATE_INLINE_HPP -@@ -58,6 +64,9 @@ void G1ParScanThreadState::trim_queue_partially() { +@@ -58,6 +64,9 @@ void G1ParScanThreadState::trim_queue() { trim_queue_to_threshold(0); assert(_task_queue->overflow_empty(), "invariant"); @@ -116172,98 +114579,9 @@ index f0944108810..a8c1f97a80e 100644 assert(_task_queue->taskqueue_empty(), "invariant"); } -diff --git a/src/hotspot/share/gc/shared/c1/barrierSetC1.cpp b/src/hotspot/share/gc/shared/c1/barrierSetC1.cpp -index 663ff91372b..7447fd5b1dd 100644 ---- a/src/hotspot/share/gc/shared/c1/barrierSetC1.cpp -+++ b/src/hotspot/share/gc/shared/c1/barrierSetC1.cpp -@@ -193,8 +193,7 @@ void BarrierSetC1::load_at_resolved(LIRAccess& access, LIR_Opr result) { - /* Normalize boolean value returned by unsafe operation, i.e., value != 0 ? value = true : value false. */ - if (mask_boolean) { - LabelObj* equalZeroLabel = new LabelObj(); -- __ cmp(lir_cond_equal, result, 0); -- __ branch(lir_cond_equal, equalZeroLabel->label()); -+ __ cmp_branch(lir_cond_equal, result, 0, equalZeroLabel->label()); - __ move(LIR_OprFact::intConst(1), result); - __ branch_destination(equalZeroLabel->label()); - } -@@ -321,14 +320,12 @@ void BarrierSetC1::generate_referent_check(LIRAccess& access, LabelObj* cont) { - referent_off = gen->new_register(T_LONG); - __ move(LIR_OprFact::longConst(java_lang_ref_Reference::referent_offset()), referent_off); - } -- __ cmp(lir_cond_notEqual, offset, referent_off); -- __ branch(lir_cond_notEqual, cont->label()); -+ __ cmp_branch(lir_cond_notEqual, offset, referent_off, cont->label()); - } - if (gen_source_check) { - // offset is a const and equals referent offset - // if (source == null) -> continue -- __ cmp(lir_cond_equal, base_reg, LIR_OprFact::oopConst(NULL)); -- __ branch(lir_cond_equal, cont->label()); -+ __ cmp_branch(lir_cond_equal, base_reg, LIR_OprFact::oopConst(NULL), cont->label()); - } - LIR_Opr src_klass = gen->new_register(T_METADATA); - if (gen_type_check) { -@@ -338,8 +335,7 @@ void BarrierSetC1::generate_referent_check(LIRAccess& access, LabelObj* cont) { - LIR_Address* reference_type_addr = new LIR_Address(src_klass, in_bytes(InstanceKlass::reference_type_offset()), T_BYTE); - LIR_Opr reference_type = gen->new_register(T_INT); - __ move(reference_type_addr, reference_type); -- __ cmp(lir_cond_equal, reference_type, LIR_OprFact::intConst(REF_NONE)); -- __ branch(lir_cond_equal, cont->label()); -+ __ cmp_branch(lir_cond_equal, reference_type, LIR_OprFact::intConst(REF_NONE), cont->label()); - } - } - } -diff --git a/src/hotspot/share/gc/shared/c1/cardTableBarrierSetC1.cpp b/src/hotspot/share/gc/shared/c1/cardTableBarrierSetC1.cpp -index a89b57d8e45..f89cb3b2dcc 100644 ---- a/src/hotspot/share/gc/shared/c1/cardTableBarrierSetC1.cpp -+++ b/src/hotspot/share/gc/shared/c1/cardTableBarrierSetC1.cpp -@@ -86,8 +86,7 @@ void CardTableBarrierSetC1::post_barrier(LIRAccess& access, LIR_OprDesc* addr, L - __ move(card_addr, cur_value); - - LabelObj* L_already_dirty = new LabelObj(); -- __ cmp(lir_cond_equal, cur_value, dirty); -- __ branch(lir_cond_equal, L_already_dirty->label()); -+ __ cmp_branch(lir_cond_equal, cur_value, dirty, L_already_dirty->label()); - __ move(dirty, card_addr); - __ branch_destination(L_already_dirty->label()); - } else { -diff --git a/src/hotspot/share/gc/shenandoah/c1/shenandoahBarrierSetC1.cpp b/src/hotspot/share/gc/shenandoah/c1/shenandoahBarrierSetC1.cpp -index 97041ee1743..efdb92bbaaa 100644 ---- a/src/hotspot/share/gc/shenandoah/c1/shenandoahBarrierSetC1.cpp -+++ b/src/hotspot/share/gc/shenandoah/c1/shenandoahBarrierSetC1.cpp -@@ -78,7 +78,6 @@ void ShenandoahBarrierSetC1::pre_barrier(LIRGenerator* gen, CodeEmitInfo* info, - // Read the marking-in-progress flag. - LIR_Opr flag_val = gen->new_register(T_INT); - __ load(mark_active_flag_addr, flag_val); -- __ cmp(lir_cond_notEqual, flag_val, LIR_OprFact::intConst(0)); - - LIR_PatchCode pre_val_patch_code = lir_patch_none; - -@@ -106,7 +105,7 @@ void ShenandoahBarrierSetC1::pre_barrier(LIRGenerator* gen, CodeEmitInfo* info, - slow = new ShenandoahPreBarrierStub(pre_val); - } - -- __ branch(lir_cond_notEqual, slow); -+ __ cmp_branch(lir_cond_notEqual, flag_val, LIR_OprFact::intConst(0), slow); - __ branch_destination(slow->continuation()); - } - -@@ -153,10 +152,9 @@ LIR_Opr ShenandoahBarrierSetC1::load_reference_barrier_impl(LIRGenerator* gen, L - __ logical_and(flag_val, mask_reg, masked_flag); - flag_val = masked_flag; - } -- __ cmp(lir_cond_notEqual, flag_val, LIR_OprFact::intConst(0)); - - CodeStub* slow = new ShenandoahLoadReferenceBarrierStub(obj, addr, result, tmp1, tmp2, decorators); -- __ branch(lir_cond_notEqual, slow); -+ __ cmp_branch(lir_cond_notEqual, flag_val, LIR_OprFact::intConst(0), slow); - __ branch_destination(slow->continuation()); - - return result; -diff --git a/src/hotspot/share/gc/shenandoah/shenandoahArguments.cpp b/src/hotspot/share/gc/shenandoah/shenandoahArguments.cpp -index c7e0c9b0cd9..c6717bb76af 100644 ---- a/src/hotspot/share/gc/shenandoah/shenandoahArguments.cpp -+++ b/src/hotspot/share/gc/shenandoah/shenandoahArguments.cpp +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/share/gc/shenandoah/shenandoahArguments.cpp b/src/hotspot/share/gc/shenandoah/shenandoahArguments.cpp +--- a/src/hotspot/share/gc/shenandoah/shenandoahArguments.cpp 2024-01-10 05:18:15.000000000 +0800 ++++ b/src/hotspot/share/gc/shenandoah/shenandoahArguments.cpp 2024-01-31 14:01:11.757430357 +0800 @@ -22,6 +22,12 @@ * */ @@ -116281,65 +114599,39 @@ index c7e0c9b0cd9..c6717bb76af 100644 #include "utilities/defaultStream.hpp" void ShenandoahArguments::initialize() { --#if !(defined AARCH64 || defined AMD64 || defined IA32 || defined PPC64) -+#if !(defined AARCH64 || defined AMD64 || defined IA32 || defined PPC64 || defined LOONGARCH64) +-#if !(defined AARCH64 || defined AMD64 || defined IA32 || defined PPC64 || defined RISCV64) ++#if !(defined AARCH64 || defined AMD64 || defined IA32 || defined PPC64 || defined RISCV64 || defined LOONGARCH64) vm_exit_during_initialization("Shenandoah GC is not supported on this platform."); #endif -diff --git a/src/hotspot/share/gc/z/c1/zBarrierSetC1.cpp b/src/hotspot/share/gc/z/c1/zBarrierSetC1.cpp -index 4f2e36a8304..b145a63363a 100644 ---- a/src/hotspot/share/gc/z/c1/zBarrierSetC1.cpp -+++ b/src/hotspot/share/gc/z/c1/zBarrierSetC1.cpp -@@ -99,15 +99,20 @@ public: - - virtual void visit(LIR_OpVisitState* state) { - state->do_input(_opr); -+ if (_result->is_valid()) { -+ state->do_temp(_opr); -+ state->do_output(_result); -+ } - } - - virtual void emit_code(LIR_Assembler* ce) { -- ZBarrierSet::assembler()->generate_c1_load_barrier_test(ce, _opr); -+ ZBarrierSet::assembler()->generate_c1_load_barrier_test(ce, _opr, result_opr()); - } - - virtual void print_instr(outputStream* out) const { - _opr->print(out); - out->print(" "); -+ result_opr()->print(out); - } - - #ifndef PRODUCT -@@ -143,13 +148,21 @@ address ZBarrierSetC1::load_barrier_on_oop_field_preloaded_runtime_stub(Decorato - #endif +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/share/gc/z/c1/zBarrierSetC1.cpp b/src/hotspot/share/gc/z/c1/zBarrierSetC1.cpp +--- a/src/hotspot/share/gc/z/c1/zBarrierSetC1.cpp 2024-01-10 05:18:15.000000000 +0800 ++++ b/src/hotspot/share/gc/z/c1/zBarrierSetC1.cpp 2024-01-31 14:01:11.764097088 +0800 +@@ -21,6 +21,12 @@ + * questions. + */ - void ZBarrierSetC1::load_barrier(LIRAccess& access, LIR_Opr result) const { -+ LIR_Op* op = new LIR_OpZLoadBarrierTest(result); ++/* ++ * This file has been modified by Loongson Technology in 2023, These ++ * modifications are Copyright (c) 2022, 2023, Loongson Technology, and are made ++ * available on the same license terms set forth above. ++ */ + - // Fast path -- __ append(new LIR_OpZLoadBarrierTest(result)); -+ __ append(op); - - // Slow path - const address runtime_stub = load_barrier_on_oop_field_preloaded_runtime_stub(access.decorators()); - CodeStub* const stub = new ZLoadBarrierStubC1(access, result, runtime_stub); -- __ branch(lir_cond_notEqual, stub); -+ if (ZPlatformLoadBarrierTestResultInRegister) { -+ LIR_Opr res = access.gen()->new_register(result->type()); -+ op->set_result_opr(res); -+ __ cmp_branch(lir_cond_notEqual, res, LIR_OprFact::intptrConst(NULL_WORD), stub); -+ } else { -+ __ branch(lir_cond_notEqual, stub); -+ } - __ branch_destination(stub->continuation()); - } + #include "precompiled.hpp" + #include "c1/c1_LIR.hpp" + #include "c1/c1_LIRGenerator.hpp" +@@ -94,7 +100,7 @@ -diff --git a/src/hotspot/share/interpreter/interpreterRuntime.cpp b/src/hotspot/share/interpreter/interpreterRuntime.cpp -index d66ed24d862..b682bb9d62a 100644 ---- a/src/hotspot/share/interpreter/interpreterRuntime.cpp -+++ b/src/hotspot/share/interpreter/interpreterRuntime.cpp + public: + LIR_OpZLoadBarrierTest(LIR_Opr opr) : +-#ifdef RISCV ++#if defined(RISCV) || defined(LOONGARCH) + LIR_Op(lir_zloadbarrier_test, LIR_OprFact::illegalOpr, NULL), + #else + LIR_Op(), +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/share/interpreter/interpreterRuntime.cpp b/src/hotspot/share/interpreter/interpreterRuntime.cpp +--- a/src/hotspot/share/interpreter/interpreterRuntime.cpp 2024-01-10 05:18:15.000000000 +0800 ++++ b/src/hotspot/share/interpreter/interpreterRuntime.cpp 2024-01-31 14:01:11.800764107 +0800 @@ -22,6 +22,12 @@ * */ @@ -116353,7 +114645,7 @@ index d66ed24d862..b682bb9d62a 100644 #include "precompiled.hpp" #include "jvm_io.h" #include "classfile/javaClasses.inline.hpp" -@@ -1459,7 +1465,7 @@ JRT_ENTRY(void, InterpreterRuntime::prepare_native_call(JavaThread* current, Met +@@ -1459,7 +1465,7 @@ // preparing the same method will be sure to see non-null entry & mirror. JRT_END @@ -116362,10 +114654,9 @@ index d66ed24d862..b682bb9d62a 100644 JRT_LEAF(void, InterpreterRuntime::popframe_move_outgoing_args(JavaThread* current, void* src_address, void* dest_address)) if (src_address == dest_address) { return; -diff --git a/src/hotspot/share/interpreter/interpreterRuntime.hpp b/src/hotspot/share/interpreter/interpreterRuntime.hpp -index c32431784aa..8209c42a1c4 100644 ---- a/src/hotspot/share/interpreter/interpreterRuntime.hpp -+++ b/src/hotspot/share/interpreter/interpreterRuntime.hpp +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/share/interpreter/interpreterRuntime.hpp b/src/hotspot/share/interpreter/interpreterRuntime.hpp +--- a/src/hotspot/share/interpreter/interpreterRuntime.hpp 2024-01-10 05:18:15.000000000 +0800 ++++ b/src/hotspot/share/interpreter/interpreterRuntime.hpp 2024-01-31 14:01:11.800764107 +0800 @@ -22,6 +22,12 @@ * */ @@ -116379,7 +114670,7 @@ index c32431784aa..8209c42a1c4 100644 #ifndef SHARE_INTERPRETER_INTERPRETERRUNTIME_HPP #define SHARE_INTERPRETER_INTERPRETERRUNTIME_HPP -@@ -135,7 +141,7 @@ class InterpreterRuntime: AllStatic { +@@ -135,7 +141,7 @@ Method* method, intptr_t* from, intptr_t* to); @@ -116388,10 +114679,9 @@ index c32431784aa..8209c42a1c4 100644 // Popframe support (only needed on x86, AMD64 and ARM) static void popframe_move_outgoing_args(JavaThread* current, void* src_address, void* dest_address); #endif -diff --git a/src/hotspot/share/interpreter/templateInterpreterGenerator.hpp b/src/hotspot/share/interpreter/templateInterpreterGenerator.hpp -index 4e167ff451a..9441bae96c1 100644 ---- a/src/hotspot/share/interpreter/templateInterpreterGenerator.hpp -+++ b/src/hotspot/share/interpreter/templateInterpreterGenerator.hpp +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/share/interpreter/templateInterpreterGenerator.hpp b/src/hotspot/share/interpreter/templateInterpreterGenerator.hpp +--- a/src/hotspot/share/interpreter/templateInterpreterGenerator.hpp 2024-01-10 05:18:15.000000000 +0800 ++++ b/src/hotspot/share/interpreter/templateInterpreterGenerator.hpp 2024-01-31 14:01:11.804097472 +0800 @@ -22,6 +22,12 @@ * */ @@ -116405,7 +114695,7 @@ index 4e167ff451a..9441bae96c1 100644 #ifndef SHARE_INTERPRETER_TEMPLATEINTERPRETERGENERATOR_HPP #define SHARE_INTERPRETER_TEMPLATEINTERPRETERGENERATOR_HPP -@@ -110,9 +116,9 @@ class TemplateInterpreterGenerator: public AbstractInterpreterGenerator { +@@ -110,9 +116,9 @@ void generate_fixed_frame(bool native_call); @@ -116417,10 +114707,9 @@ index 4e167ff451a..9441bae96c1 100644 #ifdef PPC void lock_method(Register Rflags, Register Rscratch1, Register Rscratch2, bool flags_preloaded=false); -diff --git a/src/hotspot/share/jfr/utilities/jfrBigEndian.hpp b/src/hotspot/share/jfr/utilities/jfrBigEndian.hpp -index db2e7ebaad2..c381aa11475 100644 ---- a/src/hotspot/share/jfr/utilities/jfrBigEndian.hpp -+++ b/src/hotspot/share/jfr/utilities/jfrBigEndian.hpp +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/share/jfr/utilities/jfrBigEndian.hpp b/src/hotspot/share/jfr/utilities/jfrBigEndian.hpp +--- a/src/hotspot/share/jfr/utilities/jfrBigEndian.hpp 2024-01-10 05:18:15.000000000 +0800 ++++ b/src/hotspot/share/jfr/utilities/jfrBigEndian.hpp 2024-01-31 14:01:11.817430931 +0800 @@ -22,6 +22,12 @@ * */ @@ -116434,19 +114723,18 @@ index db2e7ebaad2..c381aa11475 100644 #ifndef SHARE_JFR_UTILITIES_JFRBIGENDIAN_HPP #define SHARE_JFR_UTILITIES_JFRBIGENDIAN_HPP -@@ -102,7 +108,7 @@ inline T JfrBigEndian::read_unaligned(const address location) { +@@ -102,7 +108,7 @@ inline bool JfrBigEndian::platform_supports_unaligned_reads(void) { #if defined(IA32) || defined(AMD64) || defined(PPC) || defined(S390) return true; --#elif defined(ARM) || defined(AARCH64) -+#elif defined(ARM) || defined(AARCH64) || defined(MIPS) || defined(LOONGARCH) +-#elif defined(ARM) || defined(AARCH64) || defined(RISCV) ++#elif defined(ARM) || defined(AARCH64) || defined(RISCV) || defined(MIPS) || defined(LOONGARCH) return false; #else #warning "Unconfigured platform" -diff --git a/src/hotspot/share/jvmci/vmStructs_jvmci.cpp b/src/hotspot/share/jvmci/vmStructs_jvmci.cpp -index 3f57d487bae..3b49daaf96e 100644 ---- a/src/hotspot/share/jvmci/vmStructs_jvmci.cpp -+++ b/src/hotspot/share/jvmci/vmStructs_jvmci.cpp +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/share/jvmci/vmStructs_jvmci.cpp b/src/hotspot/share/jvmci/vmStructs_jvmci.cpp +--- a/src/hotspot/share/jvmci/vmStructs_jvmci.cpp 2024-01-10 05:18:15.000000000 +0800 ++++ b/src/hotspot/share/jvmci/vmStructs_jvmci.cpp 2024-01-31 14:01:11.824097659 +0800 @@ -22,6 +22,12 @@ * */ @@ -116478,10 +114766,9 @@ index 3f57d487bae..3b49daaf96e 100644 #ifdef X86 #define VM_STRUCTS_CPU(nonstatic_field, static_field, unchecked_nonstatic_field, volatile_nonstatic_field, nonproduct_nonstatic_field, c2_nonstatic_field, unchecked_c1_static_field, unchecked_c2_static_field) \ -diff --git a/src/hotspot/share/memory/metaspace.cpp b/src/hotspot/share/memory/metaspace.cpp -index 2c42c013560..2bfb3d71634 100644 ---- a/src/hotspot/share/memory/metaspace.cpp -+++ b/src/hotspot/share/memory/metaspace.cpp +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/share/memory/metaspace.cpp b/src/hotspot/share/memory/metaspace.cpp +--- a/src/hotspot/share/memory/metaspace.cpp 2024-01-10 05:18:15.000000000 +0800 ++++ b/src/hotspot/share/memory/metaspace.cpp 2024-01-31 14:01:11.827431026 +0800 @@ -23,6 +23,12 @@ * */ @@ -116495,7 +114782,7 @@ index 2c42c013560..2bfb3d71634 100644 #include "precompiled.hpp" #include "cds/metaspaceShared.hpp" #include "classfile/classLoaderData.hpp" -@@ -587,12 +593,15 @@ bool Metaspace::class_space_is_initialized() { +@@ -587,12 +593,15 @@ // On error, returns an unreserved space. ReservedSpace Metaspace::reserve_address_space_for_compressed_classes(size_t size) { @@ -116503,8 +114790,8 @@ index 2c42c013560..2bfb3d71634 100644 +#if defined(AARCH64) || defined(PPC64) || defined(MIPS64) || defined(LOONGARCH64) const size_t alignment = Metaspace::reserve_alignment(); - // AArch64: Try to align metaspace so that we can decode a compressed - // klass with a single MOVK instruction. We can do this iff the + // AArch64: Try to align metaspace class space so that we can decode a + // compressed klass with a single MOVK instruction. We can do this iff the // compressed class base is a multiple of 4G. + + // MIPS: Cannot mmap for 1G space at 4G position, and prepare for future optimization. @@ -116512,8 +114799,8 @@ index 2c42c013560..2bfb3d71634 100644 // Additionally, above 32G, ensure the lower LogKlassAlignmentInBytes bits // of the upper 32-bits of the address are zero so we can handle a shift // when decoding. -@@ -627,16 +636,16 @@ ReservedSpace Metaspace::reserve_address_space_for_compressed_classes(size_t siz - a += search_ranges[i].increment; +@@ -649,16 +658,16 @@ + return rs; } } -#endif // defined(AARCH64) || defined(PPC64) @@ -116532,10 +114819,9 @@ index 2c42c013560..2bfb3d71634 100644 } #endif // _LP64 -diff --git a/src/hotspot/share/opto/output.cpp b/src/hotspot/share/opto/output.cpp -index 57d2fe05481..79c2b223588 100644 ---- a/src/hotspot/share/opto/output.cpp -+++ b/src/hotspot/share/opto/output.cpp +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/share/opto/output.cpp b/src/hotspot/share/opto/output.cpp +--- a/src/hotspot/share/opto/output.cpp 2024-01-10 05:18:15.000000000 +0800 ++++ b/src/hotspot/share/opto/output.cpp 2024-01-31 14:01:11.857431311 +0800 @@ -22,6 +22,12 @@ * */ @@ -116549,10 +114835,10 @@ index 57d2fe05481..79c2b223588 100644 #include "precompiled.hpp" #include "asm/assembler.inline.hpp" #include "asm/macroAssembler.inline.hpp" -@@ -1011,6 +1017,27 @@ void PhaseOutput::Process_OopMap_Node(MachNode *mach, int current_offset) { +@@ -1011,6 +1017,27 @@ // Add the safepoint in the DebugInfoRecorder if( !mach->is_MachCall() ) { - mcall = NULL; + mcall = nullptr; +#if defined(MIPS) || defined(LOONGARCH) + // safepoint_pc_offset should point to tha last instruction in safePoint. + // In X86 and sparc, their safePoints only contain one instruction. @@ -116577,7 +114863,7 @@ index 57d2fe05481..79c2b223588 100644 C->debug_info()->add_safepoint(safepoint_pc_offset, sfn->_oop_map); } else { mcall = mach->as_MachCall(); -@@ -1686,6 +1713,22 @@ void PhaseOutput::fill_buffer(CodeBuffer* cb, uint* blk_starts) { +@@ -1686,6 +1713,22 @@ DEBUG_ONLY(uint instr_offset = cb->insts_size()); n->emit(*cb, C->regalloc()); current_offset = cb->insts_size(); @@ -116600,10 +114886,9 @@ index 57d2fe05481..79c2b223588 100644 // Above we only verified that there is enough space in the instruction section. // However, the instruction may emit stubs that cause code buffer expansion. -diff --git a/src/hotspot/share/opto/type.cpp b/src/hotspot/share/opto/type.cpp -index 4c6fe91aee9..9a204facf42 100644 ---- a/src/hotspot/share/opto/type.cpp -+++ b/src/hotspot/share/opto/type.cpp +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/share/opto/type.cpp b/src/hotspot/share/opto/type.cpp +--- a/src/hotspot/share/opto/type.cpp 2024-01-10 05:18:15.000000000 +0800 ++++ b/src/hotspot/share/opto/type.cpp 2024-01-31 14:01:11.864098041 +0800 @@ -22,6 +22,12 @@ * */ @@ -116617,7 +114902,7 @@ index 4c6fe91aee9..9a204facf42 100644 #include "precompiled.hpp" #include "ci/ciMethodData.hpp" #include "ci/ciTypeFlow.hpp" -@@ -78,6 +84,14 @@ const Type::TypeInfo Type::_type_info[Type::lastype] = { +@@ -78,6 +84,14 @@ { Bad, T_ILLEGAL, "vectorx:", false, 0, relocInfo::none }, // VectorX { Bad, T_ILLEGAL, "vectory:", false, 0, relocInfo::none }, // VectorY { Bad, T_ILLEGAL, "vectorz:", false, 0, relocInfo::none }, // VectorZ @@ -116632,10 +114917,43 @@ index 4c6fe91aee9..9a204facf42 100644 #else // all other { Bad, T_ILLEGAL, "vectormask:", false, Op_RegVectMask, relocInfo::none }, // VectorMask. { Bad, T_ILLEGAL, "vectora:", false, Op_VecA, relocInfo::none }, // VectorA. -diff --git a/src/hotspot/share/runtime/os.cpp b/src/hotspot/share/runtime/os.cpp -index ef43c317040..1b82cef1619 100644 ---- a/src/hotspot/share/runtime/os.cpp -+++ b/src/hotspot/share/runtime/os.cpp +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/share/runtime/objectMonitor.cpp b/src/hotspot/share/runtime/objectMonitor.cpp +--- a/src/hotspot/share/runtime/objectMonitor.cpp 2024-01-10 05:18:15.000000000 +0800 ++++ b/src/hotspot/share/runtime/objectMonitor.cpp 2024-01-31 14:01:11.884098234 +0800 +@@ -22,6 +22,12 @@ + * + */ + ++/* ++ * This file has been modified by Loongson Technology in 2023, These ++ * modifications are Copyright (c) 2023, Loongson Technology, and are made ++ * available on the same license terms set forth above. ++ */ ++ + #include "precompiled.hpp" + #include "classfile/vmSymbols.hpp" + #include "gc/shared/oopStorage.hpp" +@@ -362,6 +368,9 @@ + } + + assert(owner_raw() != current, "invariant"); ++ // Thread _succ != current assertion load reording before Thread if (_succ == current) _succ = nullptr. ++ // But expect order is firstly if (_succ == current) _succ = nullptr then _succ != current assertion. ++ DEBUG_ONLY(LOONGARCH64_ONLY(__asm__ __volatile__ ("dbar 0x700\n");)MIPS64_ONLY(OrderAccess::loadload();)) + assert(_succ != current, "invariant"); + assert(!SafepointSynchronize::is_at_safepoint(), "invariant"); + assert(current->thread_state() != _thread_blocked, "invariant"); +@@ -723,6 +732,7 @@ + } + + // The Spin failed -- Enqueue and park the thread ... ++ DEBUG_ONLY(LOONGARCH64_ONLY(__asm__ __volatile__ ("dbar 0x700\n");)MIPS64_ONLY(OrderAccess::loadload();)) + assert(_succ != current, "invariant"); + assert(owner_raw() != current, "invariant"); + assert(_Responsible != current, "invariant"); +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/share/runtime/os.cpp b/src/hotspot/share/runtime/os.cpp +--- a/src/hotspot/share/runtime/os.cpp 2024-01-10 05:18:15.000000000 +0800 ++++ b/src/hotspot/share/runtime/os.cpp 2024-01-31 14:01:11.884098234 +0800 @@ -22,6 +22,12 @@ * */ @@ -116649,7 +114967,7 @@ index ef43c317040..1b82cef1619 100644 #include "precompiled.hpp" #include "jvm.h" #include "classfile/javaClasses.hpp" -@@ -1250,7 +1256,8 @@ bool os::is_first_C_frame(frame* fr) { +@@ -1228,7 +1234,8 @@ if ((uintptr_t)fr->sender_sp() == (uintptr_t)-1 || is_pointer_bad(fr->sender_sp())) return true; uintptr_t old_fp = (uintptr_t)fr->link_or_null(); @@ -116659,10 +114977,9 @@ index ef43c317040..1b82cef1619 100644 is_pointer_bad(fr->link_or_null())) return true; // stack grows downwards; if old_fp is below current fp or if the stack -diff --git a/src/hotspot/share/runtime/sharedRuntime.cpp b/src/hotspot/share/runtime/sharedRuntime.cpp -index 66613e5d8c6..6f789b7e55f 100644 ---- a/src/hotspot/share/runtime/sharedRuntime.cpp -+++ b/src/hotspot/share/runtime/sharedRuntime.cpp +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/share/runtime/sharedRuntime.cpp b/src/hotspot/share/runtime/sharedRuntime.cpp +--- a/src/hotspot/share/runtime/sharedRuntime.cpp 2024-01-10 05:18:15.000000000 +0800 ++++ b/src/hotspot/share/runtime/sharedRuntime.cpp 2024-01-31 14:01:11.887431599 +0800 @@ -22,6 +22,12 @@ * */ @@ -116676,7 +114993,7 @@ index 66613e5d8c6..6f789b7e55f 100644 #include "precompiled.hpp" #include "classfile/javaClasses.hpp" #include "jvm.h" -@@ -3048,7 +3054,7 @@ void AdapterHandlerLibrary::create_native_wrapper(const methodHandle& method) { +@@ -3054,7 +3060,7 @@ CodeBuffer buffer(buf); struct { double data[20]; } locs_buf; buffer.insts()->initialize_shared_locs((relocInfo*)&locs_buf, sizeof(locs_buf) / sizeof(relocInfo)); @@ -116685,10 +115002,9 @@ index 66613e5d8c6..6f789b7e55f 100644 // On AArch64 with ZGC and nmethod entry barriers, we need all oops to be // in the constant pool to ensure ordering between the barrier and oops // accesses. For native_wrappers we need a constant. -diff --git a/src/hotspot/share/runtime/sharedRuntimeTrig.cpp b/src/hotspot/share/runtime/sharedRuntimeTrig.cpp -index 6e3aa30b0b9..8f1d486f5cb 100644 ---- a/src/hotspot/share/runtime/sharedRuntimeTrig.cpp -+++ b/src/hotspot/share/runtime/sharedRuntimeTrig.cpp +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/share/runtime/sharedRuntimeTrig.cpp b/src/hotspot/share/runtime/sharedRuntimeTrig.cpp +--- a/src/hotspot/share/runtime/sharedRuntimeTrig.cpp 2024-01-10 05:18:15.000000000 +0800 ++++ b/src/hotspot/share/runtime/sharedRuntimeTrig.cpp 2024-01-31 14:01:11.887431599 +0800 @@ -22,6 +22,13 @@ * */ @@ -116703,7 +115019,7 @@ index 6e3aa30b0b9..8f1d486f5cb 100644 #include "precompiled.hpp" #include "jni.h" #include "runtime/interfaceSupport.inline.hpp" -@@ -507,6 +514,14 @@ static int __ieee754_rem_pio2(double x, double *y) { +@@ -507,6 +514,14 @@ * sin(x) = x + (S1*x + (x *(r-y/2)+y)) */ @@ -116718,10 +115034,43 @@ index 6e3aa30b0b9..8f1d486f5cb 100644 static const double S1 = -1.66666666666666324348e-01, /* 0xBFC55555, 0x55555549 */ S2 = 8.33333333332248946124e-03, /* 0x3F811111, 0x1110F8A6 */ -diff --git a/src/hotspot/share/utilities/macros.hpp b/src/hotspot/share/utilities/macros.hpp -index 501ba0dbabc..8783e6dca2f 100644 ---- a/src/hotspot/share/utilities/macros.hpp -+++ b/src/hotspot/share/utilities/macros.hpp +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/share/runtime/thread.inline.hpp b/src/hotspot/share/runtime/thread.inline.hpp +--- a/src/hotspot/share/runtime/thread.inline.hpp 2024-01-10 05:18:15.000000000 +0800 ++++ b/src/hotspot/share/runtime/thread.inline.hpp 2024-01-31 14:01:11.890764962 +0800 +@@ -23,6 +23,12 @@ + * + */ + ++/* ++ * This file has been modified by Loongson Technology in 2023, These ++ * modifications are Copyright (c) 2018, 2023, Loongson Technology, and are made ++ * available on the same license terms set forth above. ++ */ ++ + #ifndef SHARE_RUNTIME_THREAD_INLINE_HPP + #define SHARE_RUNTIME_THREAD_INLINE_HPP + +@@ -132,7 +138,7 @@ + } + + inline JavaThreadState JavaThread::thread_state() const { +-#if defined(PPC64) || defined (AARCH64) || defined(RISCV64) ++#if defined(PPC64) || defined (AARCH64) || defined(RISCV64) || defined(LOONGARCH64) + // Use membars when accessing volatile _thread_state. See + // Threads::create_vm() for size checks. + return (JavaThreadState) Atomic::load_acquire((volatile jint*)&_thread_state); +@@ -144,7 +150,7 @@ + inline void JavaThread::set_thread_state(JavaThreadState s) { + assert(current_or_null() == NULL || current_or_null() == this, + "state change should only be called by the current thread"); +-#if defined(PPC64) || defined (AARCH64) || defined(RISCV64) ++#if defined(PPC64) || defined (AARCH64) || defined(RISCV64) || defined(LOONGARCH64) + // Use membars when accessing volatile _thread_state. See + // Threads::create_vm() for size checks. + Atomic::release_store((volatile jint*)&_thread_state, (jint)s); +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/hotspot/share/utilities/macros.hpp b/src/hotspot/share/utilities/macros.hpp +--- a/src/hotspot/share/utilities/macros.hpp 2024-01-10 05:18:15.000000000 +0800 ++++ b/src/hotspot/share/utilities/macros.hpp 2024-01-31 14:01:11.904098424 +0800 @@ -22,6 +22,12 @@ * */ @@ -116774,7 +115123,7 @@ index 501ba0dbabc..8783e6dca2f 100644 #if defined(PPC32) || defined(PPC64) #ifndef PPC #define PPC -@@ -579,16 +617,34 @@ +@@ -605,16 +643,34 @@ // OS_CPU_HEADER(vmStructs) --> vmStructs_linux_x86.hpp // // basename.hpp / basename.inline.hpp @@ -116809,10 +115158,46 @@ index 501ba0dbabc..8783e6dca2f 100644 // basename.hpp / basename.inline.hpp #define COMPILER_HEADER(basename) XSTR(COMPILER_HEADER_STEM(basename).hpp) #define COMPILER_HEADER_INLINE(basename) XSTR(COMPILER_HEADER_STEM(basename).inline.hpp) -diff --git a/src/jdk.hotspot.agent/linux/native/libsaproc/LinuxDebuggerLocal.cpp b/src/jdk.hotspot.agent/linux/native/libsaproc/LinuxDebuggerLocal.cpp -index b7a2c6dde8f..c2a144f49b8 100644 ---- a/src/jdk.hotspot.agent/linux/native/libsaproc/LinuxDebuggerLocal.cpp -+++ b/src/jdk.hotspot.agent/linux/native/libsaproc/LinuxDebuggerLocal.cpp +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/jdk.hotspot.agent/linux/native/libsaproc/libproc.h b/src/jdk.hotspot.agent/linux/native/libsaproc/libproc.h +--- a/src/jdk.hotspot.agent/linux/native/libsaproc/libproc.h 2024-01-10 05:18:15.000000000 +0800 ++++ b/src/jdk.hotspot.agent/linux/native/libsaproc/libproc.h 2024-01-31 14:01:12.934108220 +0800 +@@ -22,6 +22,13 @@ + * + */ + ++/* ++ * This file has been modified by Loongson Technology in 2022. These ++ * modifications are Copyright (c) 2022, Loongson Technology, and are made ++ * available on the same license terms set forth above. ++ * ++ */ ++ + #ifndef _LIBPROC_H_ + #define _LIBPROC_H_ + +@@ -37,7 +44,7 @@ + #include + #define user_regs_struct pt_regs + #endif +-#if defined(aarch64) || defined(arm64) ++#if defined(aarch64) || defined(arm64) || defined(loongarch64) + #include + #define user_regs_struct user_pt_regs + #elif defined(arm) +@@ -46,6 +53,10 @@ + #elif defined(riscv64) + #include + #endif ++#if defined(mips) || defined(mipsel) || defined(mips64) || defined(mips64el) ++#include ++#define user_regs_struct pt_regs ++#endif + + // This C bool type must be int for compatibility with Linux calls and + // it would be a mistake to equivalence it to C++ bool on many platforms +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/jdk.hotspot.agent/linux/native/libsaproc/LinuxDebuggerLocal.cpp b/src/jdk.hotspot.agent/linux/native/libsaproc/LinuxDebuggerLocal.cpp +--- a/src/jdk.hotspot.agent/linux/native/libsaproc/LinuxDebuggerLocal.cpp 2024-01-10 05:18:15.000000000 +0800 ++++ b/src/jdk.hotspot.agent/linux/native/libsaproc/LinuxDebuggerLocal.cpp 2024-01-31 14:01:12.934108220 +0800 @@ -23,6 +23,13 @@ * */ @@ -116827,8 +115212,8 @@ index b7a2c6dde8f..c2a144f49b8 100644 #include #include "libproc.h" #include "proc_service.h" -@@ -60,6 +67,10 @@ - #include "sun_jvm_hotspot_debugger_aarch64_AARCH64ThreadContext.h" +@@ -64,6 +71,10 @@ + #include "sun_jvm_hotspot_debugger_riscv64_RISCV64ThreadContext.h" #endif +#ifdef loongarch64 @@ -116838,18 +115223,18 @@ index b7a2c6dde8f..c2a144f49b8 100644 class AutoJavaString { JNIEnv* m_env; jstring m_str; -@@ -408,7 +419,7 @@ JNIEXPORT jbyteArray JNICALL Java_sun_jvm_hotspot_debugger_linux_LinuxDebuggerLo +@@ -412,7 +423,7 @@ return (err == PS_OK)? array : 0; } --#if defined(i586) || defined(amd64) || defined(ppc64) || defined(ppc64le) || defined(aarch64) -+#if defined(i586) || defined(amd64) || defined(ppc64) || defined(ppc64le) || defined(aarch64) || defined(loongarch64) +-#if defined(i586) || defined(amd64) || defined(ppc64) || defined(ppc64le) || defined(aarch64) || defined(riscv64) ++#if defined(i586) || defined(amd64) || defined(ppc64) || defined(ppc64le) || defined(aarch64) || defined(riscv64) || defined(loongarch64) extern "C" JNIEXPORT jlongArray JNICALL Java_sun_jvm_hotspot_debugger_linux_LinuxDebuggerLocal_getThreadIntegerRegisterSet0 (JNIEnv *env, jobject this_obj, jint lwp_id) { -@@ -440,6 +451,9 @@ JNIEXPORT jlongArray JNICALL Java_sun_jvm_hotspot_debugger_linux_LinuxDebuggerLo - #ifdef aarch64 - #define NPRGREG sun_jvm_hotspot_debugger_aarch64_AARCH64ThreadContext_NPRGREG +@@ -447,6 +458,9 @@ + #ifdef riscv64 + #define NPRGREG sun_jvm_hotspot_debugger_riscv64_RISCV64ThreadContext_NPRGREG #endif +#ifdef loongarch64 +#define NPRGREG sun_jvm_hotspot_debugger_loongarch64_LOONGARCH64ThreadContext_NPRGREG @@ -116857,9 +115242,9 @@ index b7a2c6dde8f..c2a144f49b8 100644 #if defined(ppc64) || defined(ppc64le) #define NPRGREG sun_jvm_hotspot_debugger_ppc64_PPC64ThreadContext_NPRGREG #endif -@@ -516,6 +530,18 @@ JNIEXPORT jlongArray JNICALL Java_sun_jvm_hotspot_debugger_linux_LinuxDebuggerLo - } - #endif /* aarch64 */ +@@ -561,6 +575,18 @@ + + #endif /* riscv64 */ +#if defined(loongarch64) + @@ -116876,47 +115261,9 @@ index b7a2c6dde8f..c2a144f49b8 100644 #if defined(ppc64) || defined(ppc64le) #define REG_INDEX(reg) sun_jvm_hotspot_debugger_ppc64_PPC64ThreadContext_##reg -diff --git a/src/jdk.hotspot.agent/linux/native/libsaproc/libproc.h b/src/jdk.hotspot.agent/linux/native/libsaproc/libproc.h -index b0fcfb1e4d5..17920fafec9 100644 ---- a/src/jdk.hotspot.agent/linux/native/libsaproc/libproc.h -+++ b/src/jdk.hotspot.agent/linux/native/libsaproc/libproc.h -@@ -22,6 +22,13 @@ - * - */ - -+/* -+ * This file has been modified by Loongson Technology in 2022. These -+ * modifications are Copyright (c) 2022, Loongson Technology, and are made -+ * available on the same license terms set forth above. -+ * -+ */ -+ - #ifndef _LIBPROC_H_ - #define _LIBPROC_H_ - -@@ -37,13 +44,17 @@ - #include - #define user_regs_struct pt_regs - #endif --#if defined(aarch64) || defined(arm64) -+#if defined(aarch64) || defined(arm64) || defined(loongarch64) - #include - #define user_regs_struct user_pt_regs - #elif defined(arm) - #include - #define user_regs_struct pt_regs - #endif -+#if defined(mips) || defined(mipsel) || defined(mips64) || defined(mips64el) -+#include -+#define user_regs_struct pt_regs -+#endif - - // This C bool type must be int for compatibility with Linux calls and - // it would be a mistake to equivalence it to C++ bool on many platforms -diff --git a/src/jdk.hotspot.agent/linux/native/libsaproc/ps_proc.c b/src/jdk.hotspot.agent/linux/native/libsaproc/ps_proc.c -index b5fec835a98..d991f29cbb1 100644 ---- a/src/jdk.hotspot.agent/linux/native/libsaproc/ps_proc.c -+++ b/src/jdk.hotspot.agent/linux/native/libsaproc/ps_proc.c +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/jdk.hotspot.agent/linux/native/libsaproc/ps_proc.c b/src/jdk.hotspot.agent/linux/native/libsaproc/ps_proc.c +--- a/src/jdk.hotspot.agent/linux/native/libsaproc/ps_proc.c 2024-01-10 05:18:15.000000000 +0800 ++++ b/src/jdk.hotspot.agent/linux/native/libsaproc/ps_proc.c 2024-01-31 14:01:12.934108220 +0800 @@ -22,6 +22,12 @@ * */ @@ -116930,7 +115277,7 @@ index b5fec835a98..d991f29cbb1 100644 #include #include #include -@@ -138,7 +144,7 @@ static bool process_get_lwp_regs(struct ps_prochandle* ph, pid_t pid, struct use +@@ -138,7 +144,7 @@ #define PTRACE_GETREGS_REQ PT_GETREGS #endif @@ -116939,141 +115286,9 @@ index b5fec835a98..d991f29cbb1 100644 if (ptrace_getregs(PTRACE_GETREGS_REQ, pid, user, NULL) < 0) { print_debug("ptrace(PTRACE_GETREGS, ...) failed for lwp(%d) errno(%d) \"%s\"\n", pid, errno, strerror(errno)); -diff --git a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/HotSpotAgent.java b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/HotSpotAgent.java -index aa021510567..021ba6f2820 100644 ---- a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/HotSpotAgent.java -+++ b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/HotSpotAgent.java -@@ -23,6 +23,12 @@ - * - */ - -+/* -+ * This file has been modified by Loongson Technology in 2021. These -+ * modifications are Copyright (c) 2018, 2021, Loongson Technology, and are made -+ * available on the same license terms set forth above. -+ * -+ */ - package sun.jvm.hotspot; - - import java.rmi.RemoteException; -@@ -37,6 +43,8 @@ import sun.jvm.hotspot.debugger.MachineDescriptionAMD64; - import sun.jvm.hotspot.debugger.MachineDescriptionPPC64; - import sun.jvm.hotspot.debugger.MachineDescriptionAArch64; - import sun.jvm.hotspot.debugger.MachineDescriptionIntelX86; -+import sun.jvm.hotspot.debugger.MachineDescriptionMIPS64; -+import sun.jvm.hotspot.debugger.MachineDescriptionLOONGARCH64; - import sun.jvm.hotspot.debugger.NoSuchSymbolException; - import sun.jvm.hotspot.debugger.bsd.BsdDebuggerLocal; - import sun.jvm.hotspot.debugger.linux.LinuxDebuggerLocal; -@@ -569,6 +577,10 @@ public class HotSpotAgent { - machDesc = new MachineDescriptionPPC64(); - } else if (cpu.equals("aarch64")) { - machDesc = new MachineDescriptionAArch64(); -+ } else if (cpu.equals("mips64")) { -+ machDesc = new MachineDescriptionMIPS64(); -+ } else if (cpu.equals("loongarch64")) { -+ machDesc = new MachineDescriptionLOONGARCH64(); - } else { - try { - machDesc = (MachineDescription) -diff --git a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/MachineDescriptionLOONGARCH64.java b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/MachineDescriptionLOONGARCH64.java -new file mode 100644 -index 00000000000..99cea8c7f14 ---- /dev/null -+++ b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/MachineDescriptionLOONGARCH64.java -@@ -0,0 +1,41 @@ -+/* -+ * Copyright (c) 2000, 2008, Oracle and/or its affiliates. All rights reserved. -+ * Copyright (c) 2018, 2021, Loongson Technology. All rights reserved. -+ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. -+ * -+ * This code is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 only, as -+ * published by the Free Software Foundation. -+ * -+ * This code is distributed in the hope that it will be useful, but WITHOUT -+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -+ * version 2 for more details (a copy is included in the LICENSE file that -+ * accompanied this code). -+ * -+ * You should have received a copy of the GNU General Public License version -+ * 2 along with this work; if not, write to the Free Software Foundation, -+ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. -+ * -+ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA -+ * or visit www.oracle.com if you need additional information or have any -+ * questions. -+ * -+ */ -+ -+package sun.jvm.hotspot.debugger; -+ -+public class MachineDescriptionLOONGARCH64 extends MachineDescriptionTwosComplement implements MachineDescription { -+ public long getAddressSize() { -+ return 8; -+ } -+ -+ -+ public boolean isBigEndian() { -+ return false; -+ } -+ -+ public boolean isLP64() { -+ return true; -+ } -+} -diff --git a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/MachineDescriptionMIPS64.java b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/MachineDescriptionMIPS64.java -new file mode 100644 -index 00000000000..1b49efd2017 ---- /dev/null -+++ b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/MachineDescriptionMIPS64.java -@@ -0,0 +1,41 @@ -+/* -+ * Copyright (c) 2000, 2008, Oracle and/or its affiliates. All rights reserved. -+ * Copyright (c) 2018, Loongson Technology. All rights reserved. -+ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. -+ * -+ * This code is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 only, as -+ * published by the Free Software Foundation. -+ * -+ * This code is distributed in the hope that it will be useful, but WITHOUT -+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -+ * version 2 for more details (a copy is included in the LICENSE file that -+ * accompanied this code). -+ * -+ * You should have received a copy of the GNU General Public License version -+ * 2 along with this work; if not, write to the Free Software Foundation, -+ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. -+ * -+ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA -+ * or visit www.oracle.com if you need additional information or have any -+ * questions. -+ * -+ */ -+ -+package sun.jvm.hotspot.debugger; -+ -+public class MachineDescriptionMIPS64 extends MachineDescriptionTwosComplement implements MachineDescription { -+ public long getAddressSize() { -+ return 8; -+ } -+ -+ -+ public boolean isBigEndian() { -+ return "big".equals(System.getProperty("sun.cpu.endian")); -+ } -+ -+ public boolean isLP64() { -+ return true; -+ } -+} -diff --git a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/linux/LinuxCDebugger.java b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/linux/LinuxCDebugger.java -index 491e3d5dc2c..db3b1cc20ee 100644 ---- a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/linux/LinuxCDebugger.java -+++ b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/linux/LinuxCDebugger.java +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/linux/LinuxCDebugger.java b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/linux/LinuxCDebugger.java +--- a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/linux/LinuxCDebugger.java 2024-01-10 05:18:15.000000000 +0800 ++++ b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/linux/LinuxCDebugger.java 2024-01-31 14:01:12.947441682 +0800 @@ -23,6 +23,12 @@ * */ @@ -117087,10 +115302,10 @@ index 491e3d5dc2c..db3b1cc20ee 100644 package sun.jvm.hotspot.debugger.linux; import java.io.*; -@@ -33,11 +39,15 @@ import sun.jvm.hotspot.debugger.cdbg.*; - import sun.jvm.hotspot.debugger.x86.*; +@@ -34,12 +40,16 @@ import sun.jvm.hotspot.debugger.amd64.*; import sun.jvm.hotspot.debugger.aarch64.*; + import sun.jvm.hotspot.debugger.riscv64.*; +import sun.jvm.hotspot.debugger.mips64.*; +import sun.jvm.hotspot.debugger.loongarch64.*; import sun.jvm.hotspot.debugger.ppc64.*; @@ -117098,12 +115313,13 @@ index 491e3d5dc2c..db3b1cc20ee 100644 import sun.jvm.hotspot.debugger.linux.amd64.*; import sun.jvm.hotspot.debugger.linux.ppc64.*; import sun.jvm.hotspot.debugger.linux.aarch64.*; + import sun.jvm.hotspot.debugger.linux.riscv64.*; +import sun.jvm.hotspot.debugger.linux.mips64.*; +import sun.jvm.hotspot.debugger.linux.loongarch64.*; import sun.jvm.hotspot.utilities.*; class LinuxCDebugger implements CDebugger { -@@ -91,7 +101,21 @@ class LinuxCDebugger implements CDebugger { +@@ -93,7 +103,21 @@ Address pc = context.getRegisterAsAddress(AMD64ThreadContext.RIP); if (pc == null) return null; return LinuxAMD64CFrame.getTopFrame(dbg, pc, context); @@ -117126,10 +115342,9 @@ index 491e3d5dc2c..db3b1cc20ee 100644 PPC64ThreadContext context = (PPC64ThreadContext) thread.getContext(); Address sp = context.getRegisterAsAddress(PPC64ThreadContext.SP); if (sp == null) return null; -diff --git a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/linux/LinuxThreadContextFactory.java b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/linux/LinuxThreadContextFactory.java -index 69a34fe2afa..c21e0d6a611 100644 ---- a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/linux/LinuxThreadContextFactory.java -+++ b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/linux/LinuxThreadContextFactory.java +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/linux/LinuxThreadContextFactory.java b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/linux/LinuxThreadContextFactory.java +--- a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/linux/LinuxThreadContextFactory.java 2024-01-10 05:18:15.000000000 +0800 ++++ b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/linux/LinuxThreadContextFactory.java 2024-01-31 14:01:12.950775047 +0800 @@ -22,6 +22,12 @@ * */ @@ -117143,7 +115358,7 @@ index 69a34fe2afa..c21e0d6a611 100644 package sun.jvm.hotspot.debugger.linux; import java.lang.reflect.*; -@@ -29,6 +35,8 @@ import sun.jvm.hotspot.debugger.*; +@@ -29,6 +35,8 @@ import sun.jvm.hotspot.debugger.linux.amd64.*; import sun.jvm.hotspot.debugger.linux.x86.*; import sun.jvm.hotspot.debugger.linux.ppc64.*; @@ -117152,7 +115367,7 @@ index 69a34fe2afa..c21e0d6a611 100644 class LinuxThreadContextFactory { static ThreadContext createThreadContext(LinuxDebugger dbg) { -@@ -37,7 +45,11 @@ class LinuxThreadContextFactory { +@@ -37,7 +45,11 @@ return new LinuxX86ThreadContext(dbg); } else if (cpu.equals("amd64")) { return new LinuxAMD64ThreadContext(dbg); @@ -117165,11 +115380,9 @@ index 69a34fe2afa..c21e0d6a611 100644 return new LinuxPPC64ThreadContext(dbg); } else { try { -diff --git a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/linux/loongarch64/LinuxLOONGARCH64CFrame.java b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/linux/loongarch64/LinuxLOONGARCH64CFrame.java -new file mode 100644 -index 00000000000..0e6caee5a49 ---- /dev/null -+++ b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/linux/loongarch64/LinuxLOONGARCH64CFrame.java +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/linux/loongarch64/LinuxLOONGARCH64CFrame.java b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/linux/loongarch64/LinuxLOONGARCH64CFrame.java +--- a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/linux/loongarch64/LinuxLOONGARCH64CFrame.java 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/linux/loongarch64/LinuxLOONGARCH64CFrame.java 2024-01-31 14:01:12.950775047 +0800 @@ -0,0 +1,92 @@ +/* + * Copyright (c) 2003, 2012, Oracle and/or its affiliates. All rights reserved. @@ -117263,11 +115476,9 @@ index 00000000000..0e6caee5a49 + private Address fp; + private LinuxDebugger dbg; +} -diff --git a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/linux/loongarch64/LinuxLOONGARCH64ThreadContext.java b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/linux/loongarch64/LinuxLOONGARCH64ThreadContext.java -new file mode 100644 -index 00000000000..604642598e0 ---- /dev/null -+++ b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/linux/loongarch64/LinuxLOONGARCH64ThreadContext.java +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/linux/loongarch64/LinuxLOONGARCH64ThreadContext.java b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/linux/loongarch64/LinuxLOONGARCH64ThreadContext.java +--- a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/linux/loongarch64/LinuxLOONGARCH64ThreadContext.java 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/linux/loongarch64/LinuxLOONGARCH64ThreadContext.java 2024-01-31 14:01:12.950775047 +0800 @@ -0,0 +1,47 @@ +/* + * Copyright (c) 2003, Oracle and/or its affiliates. All rights reserved. @@ -117316,11 +115527,9 @@ index 00000000000..604642598e0 + return debugger.newAddress(getRegister(index)); + } +} -diff --git a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/linux/mips64/LinuxMIPS64CFrame.java b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/linux/mips64/LinuxMIPS64CFrame.java -new file mode 100644 -index 00000000000..2e3eb564da2 ---- /dev/null -+++ b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/linux/mips64/LinuxMIPS64CFrame.java +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/linux/mips64/LinuxMIPS64CFrame.java b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/linux/mips64/LinuxMIPS64CFrame.java +--- a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/linux/mips64/LinuxMIPS64CFrame.java 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/linux/mips64/LinuxMIPS64CFrame.java 2024-01-31 14:01:12.950775047 +0800 @@ -0,0 +1,80 @@ +/* + * Copyright (c) 2003, 2012, Oracle and/or its affiliates. All rights reserved. @@ -117402,11 +115611,9 @@ index 00000000000..2e3eb564da2 + private Address ebp; + private LinuxDebugger dbg; +} -diff --git a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/linux/mips64/LinuxMIPS64ThreadContext.java b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/linux/mips64/LinuxMIPS64ThreadContext.java -new file mode 100644 -index 00000000000..98e0f3f0bcf ---- /dev/null -+++ b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/linux/mips64/LinuxMIPS64ThreadContext.java +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/linux/mips64/LinuxMIPS64ThreadContext.java b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/linux/mips64/LinuxMIPS64ThreadContext.java +--- a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/linux/mips64/LinuxMIPS64ThreadContext.java 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/linux/mips64/LinuxMIPS64ThreadContext.java 2024-01-31 14:01:12.950775047 +0800 @@ -0,0 +1,47 @@ +/* + * Copyright (c) 2003, Oracle and/or its affiliates. All rights reserved. @@ -117455,11 +115662,9 @@ index 00000000000..98e0f3f0bcf + return debugger.newAddress(getRegister(index)); + } +} -diff --git a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/loongarch64/LOONGARCH64ThreadContext.java b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/loongarch64/LOONGARCH64ThreadContext.java -new file mode 100644 -index 00000000000..1de3cb1a472 ---- /dev/null -+++ b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/loongarch64/LOONGARCH64ThreadContext.java +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/loongarch64/LOONGARCH64ThreadContext.java b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/loongarch64/LOONGARCH64ThreadContext.java +--- a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/loongarch64/LOONGARCH64ThreadContext.java 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/loongarch64/LOONGARCH64ThreadContext.java 2024-01-31 14:01:12.950775047 +0800 @@ -0,0 +1,128 @@ +/* + * Copyright (c) 2000, 2012, Oracle and/or its affiliates. All rights reserved. @@ -117589,11 +115794,99 @@ index 00000000000..1de3cb1a472 + tie the implementation to, for example, the debugging system */ + public abstract Address getRegisterAsAddress(int index); +} -diff --git a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/mips64/MIPS64ThreadContext.java b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/mips64/MIPS64ThreadContext.java -new file mode 100644 -index 00000000000..d3479a65ea0 ---- /dev/null -+++ b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/mips64/MIPS64ThreadContext.java +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/MachineDescriptionLOONGARCH64.java b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/MachineDescriptionLOONGARCH64.java +--- a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/MachineDescriptionLOONGARCH64.java 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/MachineDescriptionLOONGARCH64.java 2024-01-31 14:01:12.944108315 +0800 +@@ -0,0 +1,41 @@ ++/* ++ * Copyright (c) 2000, 2008, Oracle and/or its affiliates. All rights reserved. ++ * Copyright (c) 2018, 2021, Loongson Technology. All rights reserved. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ * ++ */ ++ ++package sun.jvm.hotspot.debugger; ++ ++public class MachineDescriptionLOONGARCH64 extends MachineDescriptionTwosComplement implements MachineDescription { ++ public long getAddressSize() { ++ return 8; ++ } ++ ++ ++ public boolean isBigEndian() { ++ return false; ++ } ++ ++ public boolean isLP64() { ++ return true; ++ } ++} +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/MachineDescriptionMIPS64.java b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/MachineDescriptionMIPS64.java +--- a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/MachineDescriptionMIPS64.java 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/MachineDescriptionMIPS64.java 2024-01-31 14:01:12.944108315 +0800 +@@ -0,0 +1,41 @@ ++/* ++ * Copyright (c) 2000, 2008, Oracle and/or its affiliates. All rights reserved. ++ * Copyright (c) 2018, Loongson Technology. All rights reserved. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ * ++ */ ++ ++package sun.jvm.hotspot.debugger; ++ ++public class MachineDescriptionMIPS64 extends MachineDescriptionTwosComplement implements MachineDescription { ++ public long getAddressSize() { ++ return 8; ++ } ++ ++ ++ public boolean isBigEndian() { ++ return "big".equals(System.getProperty("sun.cpu.endian")); ++ } ++ ++ public boolean isLP64() { ++ return true; ++ } ++} +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/mips64/MIPS64ThreadContext.java b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/mips64/MIPS64ThreadContext.java +--- a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/mips64/MIPS64ThreadContext.java 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/mips64/MIPS64ThreadContext.java 2024-01-31 14:01:12.950775047 +0800 @@ -0,0 +1,128 @@ +/* + * Copyright (c) 2000, 2012, Oracle and/or its affiliates. All rights reserved. @@ -117723,10 +116016,9 @@ index 00000000000..d3479a65ea0 + tie the implementation to, for example, the debugging system */ + public abstract Address getRegisterAsAddress(int index); +} -diff --git a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/posix/elf/ELFHeader.java b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/posix/elf/ELFHeader.java -index 7113a3a497b..de47531db7c 100644 ---- a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/posix/elf/ELFHeader.java -+++ b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/posix/elf/ELFHeader.java +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/posix/elf/ELFHeader.java b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/posix/elf/ELFHeader.java +--- a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/posix/elf/ELFHeader.java 2024-01-10 05:18:15.000000000 +0800 ++++ b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/posix/elf/ELFHeader.java 2024-01-31 14:01:12.950775047 +0800 @@ -22,6 +22,12 @@ * */ @@ -117740,7 +116032,7 @@ index 7113a3a497b..de47531db7c 100644 package sun.jvm.hotspot.debugger.posix.elf; import java.io.FileInputStream; -@@ -63,6 +69,8 @@ public interface ELFHeader { +@@ -63,6 +69,8 @@ public static final int ARCH_i860 = 7; /** MIPS architecture type. */ public static final int ARCH_MIPS = 8; @@ -117749,109 +116041,9 @@ index 7113a3a497b..de47531db7c 100644 /** Returns a file type which is defined by the file type constants. */ public short getFileType(); -diff --git a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/proc/loongarch64/ProcLOONGARCH64Thread.java b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/proc/loongarch64/ProcLOONGARCH64Thread.java -new file mode 100644 -index 00000000000..1f60fa6cfb2 ---- /dev/null -+++ b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/proc/loongarch64/ProcLOONGARCH64Thread.java -@@ -0,0 +1,92 @@ -+/* -+ * Copyright (c) 2002, 2003, Oracle and/or its affiliates. All rights reserved. -+ * Copyright (c) 2015, 2021, Loongson Technology. All rights reserved. -+ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. -+ * -+ * This code is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 only, as -+ * published by the Free Software Foundation. -+ * -+ * This code is distributed in the hope that it will be useful, but WITHOUT -+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -+ * version 2 for more details (a copy is included in the LICENSE file that -+ * accompanied this code). -+ * -+ * You should have received a copy of the GNU General Public License version -+ * 2 along with this work; if not, write to the Free Software Foundation, -+ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. -+ * -+ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA -+ * or visit www.oracle.com if you need additional information or have any -+ * questions. -+ * -+ */ -+ -+package sun.jvm.hotspot.debugger.proc.loongarch64; -+ -+import sun.jvm.hotspot.debugger.*; -+import sun.jvm.hotspot.debugger.loongarch64.*; -+import sun.jvm.hotspot.debugger.proc.*; -+import sun.jvm.hotspot.utilities.*; -+ -+public class ProcLOONGARCH64Thread implements ThreadProxy { -+ private ProcDebugger debugger; -+ private int id; -+ -+ public ProcLOONGARCH64Thread(ProcDebugger debugger, Address addr) { -+ this.debugger = debugger; -+ -+ // FIXME: the size here should be configurable. However, making it -+ // so would produce a dependency on the "types" package from the -+ // debugger package, which is not desired. -+ this.id = (int) addr.getCIntegerAt(0, 4, true); -+ } -+ -+ public ProcLOONGARCH64Thread(ProcDebugger debugger, long id) { -+ this.debugger = debugger; -+ this.id = (int) id; -+ } -+ -+ public ThreadContext getContext() throws IllegalThreadStateException { -+ ProcLOONGARCH64ThreadContext context = new ProcLOONGARCH64ThreadContext(debugger); -+ long[] regs = debugger.getThreadIntegerRegisterSet(id); -+ /* -+ _NGREG in reg.h is defined to be 19. Because we have included -+ debug registers LOONGARCH64ThreadContext.NPRGREG is 25. -+ */ -+ -+ if (Assert.ASSERTS_ENABLED) { -+ Assert.that(regs.length <= LOONGARCH64ThreadContext.NPRGREG, "size of register set is greater than " + LOONGARCH64ThreadContext.NPRGREG); -+ } -+ for (int i = 0; i < regs.length; i++) { -+ context.setRegister(i, regs[i]); -+ } -+ return context; -+ } -+ -+ public boolean canSetContext() throws DebuggerException { -+ return false; -+ } -+ -+ public void setContext(ThreadContext context) -+ throws IllegalThreadStateException, DebuggerException { -+ throw new DebuggerException("Unimplemented"); -+ } -+ -+ public String toString() { -+ return "t@" + id; -+ } -+ -+ public boolean equals(Object obj) { -+ if ((obj == null) || !(obj instanceof ProcLOONGARCH64Thread)) { -+ return false; -+ } -+ -+ return (((ProcLOONGARCH64Thread) obj).id == id); -+ } -+ -+ public int hashCode() { -+ return id; -+ } -+} -diff --git a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/proc/loongarch64/ProcLOONGARCH64ThreadContext.java b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/proc/loongarch64/ProcLOONGARCH64ThreadContext.java -new file mode 100644 -index 00000000000..ef5597ac4e9 ---- /dev/null -+++ b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/proc/loongarch64/ProcLOONGARCH64ThreadContext.java +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/proc/loongarch64/ProcLOONGARCH64ThreadContext.java b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/proc/loongarch64/ProcLOONGARCH64ThreadContext.java +--- a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/proc/loongarch64/ProcLOONGARCH64ThreadContext.java 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/proc/loongarch64/ProcLOONGARCH64ThreadContext.java 2024-01-31 14:01:12.950775047 +0800 @@ -0,0 +1,47 @@ +/* + * Copyright (c) 2002, 2003, Oracle and/or its affiliates. All rights reserved. @@ -117900,11 +116092,9 @@ index 00000000000..ef5597ac4e9 + return debugger.newAddress(getRegister(index)); + } +} -diff --git a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/proc/loongarch64/ProcLOONGARCH64ThreadFactory.java b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/proc/loongarch64/ProcLOONGARCH64ThreadFactory.java -new file mode 100644 -index 00000000000..abad1bb38b7 ---- /dev/null -+++ b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/proc/loongarch64/ProcLOONGARCH64ThreadFactory.java +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/proc/loongarch64/ProcLOONGARCH64ThreadFactory.java b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/proc/loongarch64/ProcLOONGARCH64ThreadFactory.java +--- a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/proc/loongarch64/ProcLOONGARCH64ThreadFactory.java 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/proc/loongarch64/ProcLOONGARCH64ThreadFactory.java 2024-01-31 14:01:12.950775047 +0800 @@ -0,0 +1,45 @@ +/* + * Copyright (c) 2002, Oracle and/or its affiliates. All rights reserved. @@ -117951,15 +116141,13 @@ index 00000000000..abad1bb38b7 + return new ProcLOONGARCH64Thread(debugger, id); + } +} -diff --git a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/proc/mips64/ProcMIPS64Thread.java b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/proc/mips64/ProcMIPS64Thread.java -new file mode 100644 -index 00000000000..5c1e0be8932 ---- /dev/null -+++ b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/proc/mips64/ProcMIPS64Thread.java +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/proc/loongarch64/ProcLOONGARCH64Thread.java b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/proc/loongarch64/ProcLOONGARCH64Thread.java +--- a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/proc/loongarch64/ProcLOONGARCH64Thread.java 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/proc/loongarch64/ProcLOONGARCH64Thread.java 2024-01-31 14:01:12.950775047 +0800 @@ -0,0 +1,92 @@ +/* + * Copyright (c) 2002, 2003, Oracle and/or its affiliates. All rights reserved. -+ * Copyright (c) 2015, 2018, Loongson Technology. All rights reserved. ++ * Copyright (c) 2015, 2021, Loongson Technology. All rights reserved. + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. + * + * This code is free software; you can redistribute it and/or modify it @@ -117982,18 +116170,18 @@ index 00000000000..5c1e0be8932 + * + */ + -+package sun.jvm.hotspot.debugger.proc.mips64; ++package sun.jvm.hotspot.debugger.proc.loongarch64; + +import sun.jvm.hotspot.debugger.*; -+import sun.jvm.hotspot.debugger.mips64.*; ++import sun.jvm.hotspot.debugger.loongarch64.*; +import sun.jvm.hotspot.debugger.proc.*; +import sun.jvm.hotspot.utilities.*; + -+public class ProcMIPS64Thread implements ThreadProxy { ++public class ProcLOONGARCH64Thread implements ThreadProxy { + private ProcDebugger debugger; + private int id; + -+ public ProcMIPS64Thread(ProcDebugger debugger, Address addr) { ++ public ProcLOONGARCH64Thread(ProcDebugger debugger, Address addr) { + this.debugger = debugger; + + // FIXME: the size here should be configurable. However, making it @@ -118002,21 +116190,21 @@ index 00000000000..5c1e0be8932 + this.id = (int) addr.getCIntegerAt(0, 4, true); + } + -+ public ProcMIPS64Thread(ProcDebugger debugger, long id) { ++ public ProcLOONGARCH64Thread(ProcDebugger debugger, long id) { + this.debugger = debugger; + this.id = (int) id; + } + + public ThreadContext getContext() throws IllegalThreadStateException { -+ ProcMIPS64ThreadContext context = new ProcMIPS64ThreadContext(debugger); ++ ProcLOONGARCH64ThreadContext context = new ProcLOONGARCH64ThreadContext(debugger); + long[] regs = debugger.getThreadIntegerRegisterSet(id); + /* + _NGREG in reg.h is defined to be 19. Because we have included -+ debug registers MIPS64ThreadContext.NPRGREG is 25. ++ debug registers LOONGARCH64ThreadContext.NPRGREG is 25. + */ + + if (Assert.ASSERTS_ENABLED) { -+ Assert.that(regs.length <= MIPS64ThreadContext.NPRGREG, "size of register set is greater than " + MIPS64ThreadContext.NPRGREG); ++ Assert.that(regs.length <= LOONGARCH64ThreadContext.NPRGREG, "size of register set is greater than " + LOONGARCH64ThreadContext.NPRGREG); + } + for (int i = 0; i < regs.length; i++) { + context.setRegister(i, regs[i]); @@ -118038,22 +116226,20 @@ index 00000000000..5c1e0be8932 + } + + public boolean equals(Object obj) { -+ if ((obj == null) || !(obj instanceof ProcMIPS64Thread)) { ++ if ((obj == null) || !(obj instanceof ProcLOONGARCH64Thread)) { + return false; + } + -+ return (((ProcMIPS64Thread) obj).id == id); ++ return (((ProcLOONGARCH64Thread) obj).id == id); + } + + public int hashCode() { + return id; + } +} -diff --git a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/proc/mips64/ProcMIPS64ThreadContext.java b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/proc/mips64/ProcMIPS64ThreadContext.java -new file mode 100644 -index 00000000000..d44223d768a ---- /dev/null -+++ b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/proc/mips64/ProcMIPS64ThreadContext.java +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/proc/mips64/ProcMIPS64ThreadContext.java b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/proc/mips64/ProcMIPS64ThreadContext.java +--- a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/proc/mips64/ProcMIPS64ThreadContext.java 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/proc/mips64/ProcMIPS64ThreadContext.java 2024-01-31 14:01:12.950775047 +0800 @@ -0,0 +1,47 @@ +/* + * Copyright (c) 2002, 2003, Oracle and/or its affiliates. All rights reserved. @@ -118102,11 +116288,9 @@ index 00000000000..d44223d768a + return debugger.newAddress(getRegister(index)); + } +} -diff --git a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/proc/mips64/ProcMIPS64ThreadFactory.java b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/proc/mips64/ProcMIPS64ThreadFactory.java -new file mode 100644 -index 00000000000..bad478fc5ca ---- /dev/null -+++ b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/proc/mips64/ProcMIPS64ThreadFactory.java +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/proc/mips64/ProcMIPS64ThreadFactory.java b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/proc/mips64/ProcMIPS64ThreadFactory.java +--- a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/proc/mips64/ProcMIPS64ThreadFactory.java 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/proc/mips64/ProcMIPS64ThreadFactory.java 2024-01-31 14:01:12.950775047 +0800 @@ -0,0 +1,45 @@ +/* + * Copyright (c) 2002, Oracle and/or its affiliates. All rights reserved. @@ -118153,58 +116337,13 @@ index 00000000000..bad478fc5ca + return new ProcMIPS64Thread(debugger, id); + } +} -diff --git a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/remote/RemoteDebuggerClient.java b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/remote/RemoteDebuggerClient.java -index 2bd396c8f4f..da89480f72c 100644 ---- a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/remote/RemoteDebuggerClient.java -+++ b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/remote/RemoteDebuggerClient.java -@@ -22,6 +22,12 @@ - * - */ - -+/* -+ * This file has been modified by Loongson Technology in 2021, These -+ * modifications are Copyright (c) 2019, 2021, Loongson Technology, and are made -+ * available on the same license terms set forth above. -+ */ -+ - package sun.jvm.hotspot.debugger.remote; - - import java.rmi.*; -@@ -33,6 +39,8 @@ import sun.jvm.hotspot.debugger.cdbg.*; - import sun.jvm.hotspot.debugger.remote.x86.*; - import sun.jvm.hotspot.debugger.remote.amd64.*; - import sun.jvm.hotspot.debugger.remote.ppc64.*; -+import sun.jvm.hotspot.debugger.remote.mips64.*; -+import sun.jvm.hotspot.debugger.remote.loongarch64.*; - - /** An implementation of Debugger which wraps a - RemoteDebugger, providing remote debugging via RMI. -@@ -71,6 +79,16 @@ public class RemoteDebuggerClient extends DebuggerBase implements JVMDebugger { - cachePageSize = 4096; - cacheNumPages = parseCacheNumPagesProperty(cacheSize / cachePageSize); - unalignedAccessesOkay = true; -+ } else if (cpu.equals("mips64") || cpu.equals("mips64el")) { -+ threadFactory = new RemoteMIPS64ThreadFactory(this); -+ cachePageSize = 4096; -+ cacheNumPages = parseCacheNumPagesProperty(cacheSize / cachePageSize); -+ unalignedAccessesOkay = true; -+ } else if (cpu.equals("loongarch64")) { -+ threadFactory = new RemoteLOONGARCH64ThreadFactory(this); -+ cachePageSize = 4096; -+ cacheNumPages = parseCacheNumPagesProperty(cacheSize / cachePageSize); -+ unalignedAccessesOkay = true; - } else { - try { - Class tf = Class.forName("sun.jvm.hotspot.debugger.remote." + -diff --git a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/remote/loongarch64/RemoteLOONGARCH64Thread.java b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/remote/loongarch64/RemoteLOONGARCH64Thread.java -new file mode 100644 -index 00000000000..242dd279e1a ---- /dev/null -+++ b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/remote/loongarch64/RemoteLOONGARCH64Thread.java -@@ -0,0 +1,54 @@ +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/proc/mips64/ProcMIPS64Thread.java b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/proc/mips64/ProcMIPS64Thread.java +--- a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/proc/mips64/ProcMIPS64Thread.java 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/proc/mips64/ProcMIPS64Thread.java 2024-01-31 14:01:12.950775047 +0800 +@@ -0,0 +1,92 @@ +/* -+ * Copyright (c) 2002, Oracle and/or its affiliates. All rights reserved. -+ * Copyright (c) 2018, 2021, Loongson Technology. All rights reserved. ++ * Copyright (c) 2002, 2003, Oracle and/or its affiliates. All rights reserved. ++ * Copyright (c) 2015, 2018, Loongson Technology. All rights reserved. + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. + * + * This code is free software; you can redistribute it and/or modify it @@ -118227,40 +116366,76 @@ index 00000000000..242dd279e1a + * + */ + -+package sun.jvm.hotspot.debugger.remote.loongarch64; ++package sun.jvm.hotspot.debugger.proc.mips64; + +import sun.jvm.hotspot.debugger.*; -+import sun.jvm.hotspot.debugger.loongarch64.*; -+import sun.jvm.hotspot.debugger.remote.*; ++import sun.jvm.hotspot.debugger.mips64.*; ++import sun.jvm.hotspot.debugger.proc.*; +import sun.jvm.hotspot.utilities.*; + -+public class RemoteLOONGARCH64Thread extends RemoteThread { -+ public RemoteLOONGARCH64Thread(RemoteDebuggerClient debugger, Address addr) { -+ super(debugger, addr); ++public class ProcMIPS64Thread implements ThreadProxy { ++ private ProcDebugger debugger; ++ private int id; ++ ++ public ProcMIPS64Thread(ProcDebugger debugger, Address addr) { ++ this.debugger = debugger; ++ ++ // FIXME: the size here should be configurable. However, making it ++ // so would produce a dependency on the "types" package from the ++ // debugger package, which is not desired. ++ this.id = (int) addr.getCIntegerAt(0, 4, true); + } + -+ public RemoteLOONGARCH64Thread(RemoteDebuggerClient debugger, long id) { -+ super(debugger, id); ++ public ProcMIPS64Thread(ProcDebugger debugger, long id) { ++ this.debugger = debugger; ++ this.id = (int) id; + } + + public ThreadContext getContext() throws IllegalThreadStateException { -+ RemoteLOONGARCH64ThreadContext context = new RemoteLOONGARCH64ThreadContext(debugger); -+ long[] regs = (addr != null)? debugger.getThreadIntegerRegisterSet(addr) : -+ debugger.getThreadIntegerRegisterSet(id); ++ ProcMIPS64ThreadContext context = new ProcMIPS64ThreadContext(debugger); ++ long[] regs = debugger.getThreadIntegerRegisterSet(id); ++ /* ++ _NGREG in reg.h is defined to be 19. Because we have included ++ debug registers MIPS64ThreadContext.NPRGREG is 25. ++ */ ++ + if (Assert.ASSERTS_ENABLED) { -+ Assert.that(regs.length == LOONGARCH64ThreadContext.NPRGREG, "size of register set must match"); ++ Assert.that(regs.length <= MIPS64ThreadContext.NPRGREG, "size of register set is greater than " + MIPS64ThreadContext.NPRGREG); + } + for (int i = 0; i < regs.length; i++) { + context.setRegister(i, regs[i]); + } + return context; + } ++ ++ public boolean canSetContext() throws DebuggerException { ++ return false; ++ } ++ ++ public void setContext(ThreadContext context) ++ throws IllegalThreadStateException, DebuggerException { ++ throw new DebuggerException("Unimplemented"); ++ } ++ ++ public String toString() { ++ return "t@" + id; ++ } ++ ++ public boolean equals(Object obj) { ++ if ((obj == null) || !(obj instanceof ProcMIPS64Thread)) { ++ return false; ++ } ++ ++ return (((ProcMIPS64Thread) obj).id == id); ++ } ++ ++ public int hashCode() { ++ return id; ++ } +} -diff --git a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/remote/loongarch64/RemoteLOONGARCH64ThreadContext.java b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/remote/loongarch64/RemoteLOONGARCH64ThreadContext.java -new file mode 100644 -index 00000000000..634d5ad049f ---- /dev/null -+++ b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/remote/loongarch64/RemoteLOONGARCH64ThreadContext.java +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/remote/loongarch64/RemoteLOONGARCH64ThreadContext.java b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/remote/loongarch64/RemoteLOONGARCH64ThreadContext.java +--- a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/remote/loongarch64/RemoteLOONGARCH64ThreadContext.java 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/remote/loongarch64/RemoteLOONGARCH64ThreadContext.java 2024-01-31 14:01:12.950775047 +0800 @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2002, Oracle and/or its affiliates. All rights reserved. @@ -118313,11 +116488,9 @@ index 00000000000..634d5ad049f + return debugger.newAddress(getRegister(index)); + } +} -diff --git a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/remote/loongarch64/RemoteLOONGARCH64ThreadFactory.java b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/remote/loongarch64/RemoteLOONGARCH64ThreadFactory.java -new file mode 100644 -index 00000000000..4fb9cc7c069 ---- /dev/null -+++ b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/remote/loongarch64/RemoteLOONGARCH64ThreadFactory.java +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/remote/loongarch64/RemoteLOONGARCH64ThreadFactory.java b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/remote/loongarch64/RemoteLOONGARCH64ThreadFactory.java +--- a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/remote/loongarch64/RemoteLOONGARCH64ThreadFactory.java 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/remote/loongarch64/RemoteLOONGARCH64ThreadFactory.java 2024-01-31 14:01:12.950775047 +0800 @@ -0,0 +1,45 @@ +/* + * Copyright (c) 2002, Oracle and/or its affiliates. All rights reserved. @@ -118364,15 +116537,13 @@ index 00000000000..4fb9cc7c069 + return new RemoteLOONGARCH64Thread(debugger, id); + } +} -diff --git a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/remote/mips64/RemoteMIPS64Thread.java b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/remote/mips64/RemoteMIPS64Thread.java -new file mode 100644 -index 00000000000..c2f7d841f20 ---- /dev/null -+++ b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/remote/mips64/RemoteMIPS64Thread.java +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/remote/loongarch64/RemoteLOONGARCH64Thread.java b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/remote/loongarch64/RemoteLOONGARCH64Thread.java +--- a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/remote/loongarch64/RemoteLOONGARCH64Thread.java 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/remote/loongarch64/RemoteLOONGARCH64Thread.java 2024-01-31 14:01:12.950775047 +0800 @@ -0,0 +1,54 @@ +/* + * Copyright (c) 2002, Oracle and/or its affiliates. All rights reserved. -+ * Copyright (c) 2018, Loongson Technology. All rights reserved. ++ * Copyright (c) 2018, 2021, Loongson Technology. All rights reserved. + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. + * + * This code is free software; you can redistribute it and/or modify it @@ -118395,28 +116566,28 @@ index 00000000000..c2f7d841f20 + * + */ + -+package sun.jvm.hotspot.debugger.remote.mips64; ++package sun.jvm.hotspot.debugger.remote.loongarch64; + +import sun.jvm.hotspot.debugger.*; -+import sun.jvm.hotspot.debugger.mips64.*; ++import sun.jvm.hotspot.debugger.loongarch64.*; +import sun.jvm.hotspot.debugger.remote.*; +import sun.jvm.hotspot.utilities.*; + -+public class RemoteMIPS64Thread extends RemoteThread { -+ public RemoteMIPS64Thread(RemoteDebuggerClient debugger, Address addr) { ++public class RemoteLOONGARCH64Thread extends RemoteThread { ++ public RemoteLOONGARCH64Thread(RemoteDebuggerClient debugger, Address addr) { + super(debugger, addr); + } + -+ public RemoteMIPS64Thread(RemoteDebuggerClient debugger, long id) { ++ public RemoteLOONGARCH64Thread(RemoteDebuggerClient debugger, long id) { + super(debugger, id); + } + + public ThreadContext getContext() throws IllegalThreadStateException { -+ RemoteMIPS64ThreadContext context = new RemoteMIPS64ThreadContext(debugger); ++ RemoteLOONGARCH64ThreadContext context = new RemoteLOONGARCH64ThreadContext(debugger); + long[] regs = (addr != null)? debugger.getThreadIntegerRegisterSet(addr) : + debugger.getThreadIntegerRegisterSet(id); + if (Assert.ASSERTS_ENABLED) { -+ Assert.that(regs.length == MIPS64ThreadContext.NPRGREG, "size of register set must match"); ++ Assert.that(regs.length == LOONGARCH64ThreadContext.NPRGREG, "size of register set must match"); + } + for (int i = 0; i < regs.length; i++) { + context.setRegister(i, regs[i]); @@ -118424,11 +116595,9 @@ index 00000000000..c2f7d841f20 + return context; + } +} -diff --git a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/remote/mips64/RemoteMIPS64ThreadContext.java b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/remote/mips64/RemoteMIPS64ThreadContext.java -new file mode 100644 -index 00000000000..23646905d74 ---- /dev/null -+++ b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/remote/mips64/RemoteMIPS64ThreadContext.java +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/remote/mips64/RemoteMIPS64ThreadContext.java b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/remote/mips64/RemoteMIPS64ThreadContext.java +--- a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/remote/mips64/RemoteMIPS64ThreadContext.java 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/remote/mips64/RemoteMIPS64ThreadContext.java 2024-01-31 14:01:12.954108410 +0800 @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2002, Oracle and/or its affiliates. All rights reserved. @@ -118481,11 +116650,9 @@ index 00000000000..23646905d74 + return debugger.newAddress(getRegister(index)); + } +} -diff --git a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/remote/mips64/RemoteMIPS64ThreadFactory.java b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/remote/mips64/RemoteMIPS64ThreadFactory.java -new file mode 100644 -index 00000000000..b39b0144901 ---- /dev/null -+++ b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/remote/mips64/RemoteMIPS64ThreadFactory.java +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/remote/mips64/RemoteMIPS64ThreadFactory.java b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/remote/mips64/RemoteMIPS64ThreadFactory.java +--- a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/remote/mips64/RemoteMIPS64ThreadFactory.java 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/remote/mips64/RemoteMIPS64ThreadFactory.java 2024-01-31 14:01:12.954108410 +0800 @@ -0,0 +1,45 @@ +/* + * Copyright (c) 2002, Oracle and/or its affiliates. All rights reserved. @@ -118517,25 +116684,82 @@ index 00000000000..b39b0144901 +import sun.jvm.hotspot.debugger.*; +import sun.jvm.hotspot.debugger.remote.*; + -+public class RemoteMIPS64ThreadFactory implements RemoteThreadFactory { -+ private RemoteDebuggerClient debugger; -+ -+ public RemoteMIPS64ThreadFactory(RemoteDebuggerClient debugger) { -+ this.debugger = debugger; ++public class RemoteMIPS64ThreadFactory implements RemoteThreadFactory { ++ private RemoteDebuggerClient debugger; ++ ++ public RemoteMIPS64ThreadFactory(RemoteDebuggerClient debugger) { ++ this.debugger = debugger; ++ } ++ ++ public ThreadProxy createThreadWrapper(Address threadIdentifierAddr) { ++ return new RemoteMIPS64Thread(debugger, threadIdentifierAddr); ++ } ++ ++ public ThreadProxy createThreadWrapper(long id) { ++ return new RemoteMIPS64Thread(debugger, id); ++ } ++} +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/remote/mips64/RemoteMIPS64Thread.java b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/remote/mips64/RemoteMIPS64Thread.java +--- a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/remote/mips64/RemoteMIPS64Thread.java 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/remote/mips64/RemoteMIPS64Thread.java 2024-01-31 14:01:12.950775047 +0800 +@@ -0,0 +1,54 @@ ++/* ++ * Copyright (c) 2002, Oracle and/or its affiliates. All rights reserved. ++ * Copyright (c) 2018, Loongson Technology. All rights reserved. ++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. ++ * ++ * This code is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 only, as ++ * published by the Free Software Foundation. ++ * ++ * This code is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * version 2 for more details (a copy is included in the LICENSE file that ++ * accompanied this code). ++ * ++ * You should have received a copy of the GNU General Public License version ++ * 2 along with this work; if not, write to the Free Software Foundation, ++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. ++ * ++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA ++ * or visit www.oracle.com if you need additional information or have any ++ * questions. ++ * ++ */ ++ ++package sun.jvm.hotspot.debugger.remote.mips64; ++ ++import sun.jvm.hotspot.debugger.*; ++import sun.jvm.hotspot.debugger.mips64.*; ++import sun.jvm.hotspot.debugger.remote.*; ++import sun.jvm.hotspot.utilities.*; ++ ++public class RemoteMIPS64Thread extends RemoteThread { ++ public RemoteMIPS64Thread(RemoteDebuggerClient debugger, Address addr) { ++ super(debugger, addr); + } + -+ public ThreadProxy createThreadWrapper(Address threadIdentifierAddr) { -+ return new RemoteMIPS64Thread(debugger, threadIdentifierAddr); ++ public RemoteMIPS64Thread(RemoteDebuggerClient debugger, long id) { ++ super(debugger, id); + } + -+ public ThreadProxy createThreadWrapper(long id) { -+ return new RemoteMIPS64Thread(debugger, id); ++ public ThreadContext getContext() throws IllegalThreadStateException { ++ RemoteMIPS64ThreadContext context = new RemoteMIPS64ThreadContext(debugger); ++ long[] regs = (addr != null)? debugger.getThreadIntegerRegisterSet(addr) : ++ debugger.getThreadIntegerRegisterSet(id); ++ if (Assert.ASSERTS_ENABLED) { ++ Assert.that(regs.length == MIPS64ThreadContext.NPRGREG, "size of register set must match"); ++ } ++ for (int i = 0; i < regs.length; i++) { ++ context.setRegister(i, regs[i]); ++ } ++ return context; + } +} -diff --git a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/Threads.java b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/Threads.java -index 4a2fa691d3f..59e4a3aca46 100644 ---- a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/Threads.java -+++ b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/Threads.java +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/remote/RemoteDebuggerClient.java b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/remote/RemoteDebuggerClient.java +--- a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/remote/RemoteDebuggerClient.java 2024-01-10 05:18:15.000000000 +0800 ++++ b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/remote/RemoteDebuggerClient.java 2024-01-31 14:01:12.950775047 +0800 @@ -22,6 +22,12 @@ * */ @@ -118546,34 +116770,74 @@ index 4a2fa691d3f..59e4a3aca46 100644 + * available on the same license terms set forth above. + */ + - package sun.jvm.hotspot.runtime; + package sun.jvm.hotspot.debugger.remote; - import java.util.*; -@@ -35,6 +41,8 @@ import sun.jvm.hotspot.runtime.linux_x86.LinuxX86JavaThreadPDAccess; - import sun.jvm.hotspot.runtime.linux_amd64.LinuxAMD64JavaThreadPDAccess; - import sun.jvm.hotspot.runtime.linux_aarch64.LinuxAARCH64JavaThreadPDAccess; - import sun.jvm.hotspot.runtime.linux_ppc64.LinuxPPC64JavaThreadPDAccess; -+import sun.jvm.hotspot.runtime.linux_mips64.LinuxMIPS64JavaThreadPDAccess; -+import sun.jvm.hotspot.runtime.linux_loongarch64.LinuxLOONGARCH64JavaThreadPDAccess; - import sun.jvm.hotspot.runtime.bsd_x86.BsdX86JavaThreadPDAccess; - import sun.jvm.hotspot.runtime.bsd_amd64.BsdAMD64JavaThreadPDAccess; - import sun.jvm.hotspot.runtime.bsd_aarch64.BsdAARCH64JavaThreadPDAccess; -@@ -113,6 +121,10 @@ public class Threads { - access = new LinuxPPC64JavaThreadPDAccess(); - } else if (cpu.equals("aarch64")) { - access = new LinuxAARCH64JavaThreadPDAccess(); -+ } else if (cpu.equals("mips64")) { -+ access = new LinuxMIPS64JavaThreadPDAccess(); -+ } else if (cpu.equals("loongarch64")) { -+ access = new LinuxLOONGARCH64JavaThreadPDAccess(); - } else { - try { - access = (JavaThreadPDAccess) -diff --git a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/linux_loongarch64/LinuxLOONGARCH64JavaThreadPDAccess.java b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/linux_loongarch64/LinuxLOONGARCH64JavaThreadPDAccess.java -new file mode 100644 -index 00000000000..75d6bf2c642 ---- /dev/null -+++ b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/linux_loongarch64/LinuxLOONGARCH64JavaThreadPDAccess.java + import java.rmi.*; +@@ -33,6 +39,8 @@ + import sun.jvm.hotspot.debugger.remote.x86.*; + import sun.jvm.hotspot.debugger.remote.amd64.*; + import sun.jvm.hotspot.debugger.remote.ppc64.*; ++import sun.jvm.hotspot.debugger.remote.mips64.*; ++import sun.jvm.hotspot.debugger.remote.loongarch64.*; + + /** An implementation of Debugger which wraps a + RemoteDebugger, providing remote debugging via RMI. +@@ -71,6 +79,16 @@ + cachePageSize = 4096; + cacheNumPages = parseCacheNumPagesProperty(cacheSize / cachePageSize); + unalignedAccessesOkay = true; ++ } else if (cpu.equals("mips64") || cpu.equals("mips64el")) { ++ threadFactory = new RemoteMIPS64ThreadFactory(this); ++ cachePageSize = 4096; ++ cacheNumPages = parseCacheNumPagesProperty(cacheSize / cachePageSize); ++ unalignedAccessesOkay = true; ++ } else if (cpu.equals("loongarch64")) { ++ threadFactory = new RemoteLOONGARCH64ThreadFactory(this); ++ cachePageSize = 4096; ++ cacheNumPages = parseCacheNumPagesProperty(cacheSize / cachePageSize); ++ unalignedAccessesOkay = true; + } else { + try { + Class tf = Class.forName("sun.jvm.hotspot.debugger.remote." + +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/HotSpotAgent.java b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/HotSpotAgent.java +--- a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/HotSpotAgent.java 2024-01-10 05:18:15.000000000 +0800 ++++ b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/HotSpotAgent.java 2024-01-31 14:01:12.940774951 +0800 +@@ -23,6 +23,12 @@ + * + */ + ++/* ++ * This file has been modified by Loongson Technology in 2021. These ++ * modifications are Copyright (c) 2018, 2021, Loongson Technology, and are made ++ * available on the same license terms set forth above. ++ * ++ */ + package sun.jvm.hotspot; + + import java.rmi.RemoteException; +@@ -38,6 +44,8 @@ + import sun.jvm.hotspot.debugger.MachineDescriptionAArch64; + import sun.jvm.hotspot.debugger.MachineDescriptionRISCV64; + import sun.jvm.hotspot.debugger.MachineDescriptionIntelX86; ++import sun.jvm.hotspot.debugger.MachineDescriptionMIPS64; ++import sun.jvm.hotspot.debugger.MachineDescriptionLOONGARCH64; + import sun.jvm.hotspot.debugger.NoSuchSymbolException; + import sun.jvm.hotspot.debugger.bsd.BsdDebuggerLocal; + import sun.jvm.hotspot.debugger.linux.LinuxDebuggerLocal; +@@ -572,6 +580,10 @@ + machDesc = new MachineDescriptionAArch64(); + } else if (cpu.equals("riscv64")) { + machDesc = new MachineDescriptionRISCV64(); ++ } else if (cpu.equals("mips64")) { ++ machDesc = new MachineDescriptionMIPS64(); ++ } else if (cpu.equals("loongarch64")) { ++ machDesc = new MachineDescriptionLOONGARCH64(); + } else { + try { + machDesc = (MachineDescription) +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/linux_loongarch64/LinuxLOONGARCH64JavaThreadPDAccess.java b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/linux_loongarch64/LinuxLOONGARCH64JavaThreadPDAccess.java +--- a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/linux_loongarch64/LinuxLOONGARCH64JavaThreadPDAccess.java 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/linux_loongarch64/LinuxLOONGARCH64JavaThreadPDAccess.java 2024-01-31 14:01:12.974108600 +0800 @@ -0,0 +1,135 @@ +/* + * Copyright (c) 2014, Oracle and/or its affiliates. All rights reserved. @@ -118710,11 +116974,9 @@ index 00000000000..75d6bf2c642 + return debugger.getThreadForIdentifierAddress(threadIdAddr); + } +} -diff --git a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/linux_mips64/LinuxMIPS64JavaThreadPDAccess.java b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/linux_mips64/LinuxMIPS64JavaThreadPDAccess.java -new file mode 100644 -index 00000000000..88223744932 ---- /dev/null -+++ b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/linux_mips64/LinuxMIPS64JavaThreadPDAccess.java +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/linux_mips64/LinuxMIPS64JavaThreadPDAccess.java b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/linux_mips64/LinuxMIPS64JavaThreadPDAccess.java +--- a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/linux_mips64/LinuxMIPS64JavaThreadPDAccess.java 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/linux_mips64/LinuxMIPS64JavaThreadPDAccess.java 2024-01-31 14:01:12.974108600 +0800 @@ -0,0 +1,135 @@ +/* + * Copyright (c) 2014, Oracle and/or its affiliates. All rights reserved. @@ -118851,11 +117113,9 @@ index 00000000000..88223744932 + return debugger.getThreadForIdentifierAddress(threadIdAddr); + } +} -diff --git a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/loongarch64/LOONGARCH64CurrentFrameGuess.java b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/loongarch64/LOONGARCH64CurrentFrameGuess.java -new file mode 100644 -index 00000000000..824270e1329 ---- /dev/null -+++ b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/loongarch64/LOONGARCH64CurrentFrameGuess.java +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/loongarch64/LOONGARCH64CurrentFrameGuess.java b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/loongarch64/LOONGARCH64CurrentFrameGuess.java +--- a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/loongarch64/LOONGARCH64CurrentFrameGuess.java 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/loongarch64/LOONGARCH64CurrentFrameGuess.java 2024-01-31 14:01:12.974108600 +0800 @@ -0,0 +1,250 @@ +/* + * Copyright (c) 2001, 2006, Oracle and/or its affiliates. All rights reserved. @@ -119107,11 +117367,9 @@ index 00000000000..824270e1329 + pcFound = pc; + } +} -diff --git a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/loongarch64/LOONGARCH64Frame.java b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/loongarch64/LOONGARCH64Frame.java -new file mode 100644 -index 00000000000..576654594d8 ---- /dev/null -+++ b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/loongarch64/LOONGARCH64Frame.java +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/loongarch64/LOONGARCH64Frame.java b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/loongarch64/LOONGARCH64Frame.java +--- a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/loongarch64/LOONGARCH64Frame.java 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/loongarch64/LOONGARCH64Frame.java 2024-01-31 14:01:12.974108600 +0800 @@ -0,0 +1,519 @@ +/* + * Copyright (c) 2001, 2015, Oracle and/or its affiliates. All rights reserved. @@ -119632,11 +117890,9 @@ index 00000000000..576654594d8 + } + } +} -diff --git a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/loongarch64/LOONGARCH64JavaCallWrapper.java b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/loongarch64/LOONGARCH64JavaCallWrapper.java -new file mode 100644 -index 00000000000..0ad9573a42d ---- /dev/null -+++ b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/loongarch64/LOONGARCH64JavaCallWrapper.java +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/loongarch64/LOONGARCH64JavaCallWrapper.java b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/loongarch64/LOONGARCH64JavaCallWrapper.java +--- a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/loongarch64/LOONGARCH64JavaCallWrapper.java 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/loongarch64/LOONGARCH64JavaCallWrapper.java 2024-01-31 14:01:12.974108600 +0800 @@ -0,0 +1,59 @@ +/* + * Copyright (c) 2001, 2002, Oracle and/or its affiliates. All rights reserved. @@ -119697,11 +117953,9 @@ index 00000000000..0ad9573a42d + return lastJavaFPField.getValue(addr.addOffsetTo(anchorField.getOffset())); + } +} -diff --git a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/loongarch64/LOONGARCH64RegisterMap.java b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/loongarch64/LOONGARCH64RegisterMap.java -new file mode 100644 -index 00000000000..2cf904d3885 ---- /dev/null -+++ b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/loongarch64/LOONGARCH64RegisterMap.java +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/loongarch64/LOONGARCH64RegisterMap.java b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/loongarch64/LOONGARCH64RegisterMap.java +--- a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/loongarch64/LOONGARCH64RegisterMap.java 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/loongarch64/LOONGARCH64RegisterMap.java 2024-01-31 14:01:12.974108600 +0800 @@ -0,0 +1,52 @@ +/* + * Copyright (c) 2001, 2012, Oracle and/or its affiliates. All rights reserved. @@ -119755,11 +118009,9 @@ index 00000000000..2cf904d3885 + protected void initializeFromPD(RegisterMap map) {} + protected Address getLocationPD(VMReg reg) { return null; } +} -diff --git a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/mips64/MIPS64CurrentFrameGuess.java b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/mips64/MIPS64CurrentFrameGuess.java -new file mode 100644 -index 00000000000..c11458abe2c ---- /dev/null -+++ b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/mips64/MIPS64CurrentFrameGuess.java +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/mips64/MIPS64CurrentFrameGuess.java b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/mips64/MIPS64CurrentFrameGuess.java +--- a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/mips64/MIPS64CurrentFrameGuess.java 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/mips64/MIPS64CurrentFrameGuess.java 2024-01-31 14:01:12.974108600 +0800 @@ -0,0 +1,217 @@ +/* + * Copyright (c) 2001, 2006, Oracle and/or its affiliates. All rights reserved. @@ -119978,11 +118230,9 @@ index 00000000000..c11458abe2c + pcFound = pc; + } +} -diff --git a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/mips64/MIPS64Frame.java b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/mips64/MIPS64Frame.java -new file mode 100644 -index 00000000000..e11d64737dd ---- /dev/null -+++ b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/mips64/MIPS64Frame.java +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/mips64/MIPS64Frame.java b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/mips64/MIPS64Frame.java +--- a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/mips64/MIPS64Frame.java 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/mips64/MIPS64Frame.java 2024-01-31 14:01:12.974108600 +0800 @@ -0,0 +1,539 @@ +/* + * Copyright (c) 2001, 2015, Oracle and/or its affiliates. All rights reserved. @@ -120523,11 +118773,9 @@ index 00000000000..e11d64737dd + } + } +} -diff --git a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/mips64/MIPS64JavaCallWrapper.java b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/mips64/MIPS64JavaCallWrapper.java -new file mode 100644 -index 00000000000..8a4a28a6055 ---- /dev/null -+++ b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/mips64/MIPS64JavaCallWrapper.java +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/mips64/MIPS64JavaCallWrapper.java b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/mips64/MIPS64JavaCallWrapper.java +--- a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/mips64/MIPS64JavaCallWrapper.java 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/mips64/MIPS64JavaCallWrapper.java 2024-01-31 14:01:12.974108600 +0800 @@ -0,0 +1,59 @@ +/* + * Copyright (c) 2001, 2002, Oracle and/or its affiliates. All rights reserved. @@ -120588,11 +118836,9 @@ index 00000000000..8a4a28a6055 + return lastJavaFPField.getValue(addr.addOffsetTo(anchorField.getOffset())); + } +} -diff --git a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/mips64/MIPS64RegisterMap.java b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/mips64/MIPS64RegisterMap.java -new file mode 100644 -index 00000000000..f2da760af4a ---- /dev/null -+++ b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/mips64/MIPS64RegisterMap.java +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/mips64/MIPS64RegisterMap.java b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/mips64/MIPS64RegisterMap.java +--- a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/mips64/MIPS64RegisterMap.java 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/mips64/MIPS64RegisterMap.java 2024-01-31 14:01:12.974108600 +0800 @@ -0,0 +1,52 @@ +/* + * Copyright (c) 2001, 2012, Oracle and/or its affiliates. All rights reserved. @@ -120646,10 +118892,45 @@ index 00000000000..f2da760af4a + protected void initializeFromPD(RegisterMap map) {} + protected Address getLocationPD(VMReg reg) { return null; } +} -diff --git a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/utilities/PlatformInfo.java b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/utilities/PlatformInfo.java -index 3e66e24700b..f894792f912 100644 ---- a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/utilities/PlatformInfo.java -+++ b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/utilities/PlatformInfo.java +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/Threads.java b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/Threads.java +--- a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/Threads.java 2024-01-10 05:18:15.000000000 +0800 ++++ b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/Threads.java 2024-01-31 14:01:12.970775237 +0800 +@@ -22,6 +22,12 @@ + * + */ + ++/* ++ * This file has been modified by Loongson Technology in 2021, These ++ * modifications are Copyright (c) 2019, 2021, Loongson Technology, and are made ++ * available on the same license terms set forth above. ++ */ ++ + package sun.jvm.hotspot.runtime; + + import java.util.*; +@@ -36,6 +42,8 @@ + import sun.jvm.hotspot.runtime.linux_aarch64.LinuxAARCH64JavaThreadPDAccess; + import sun.jvm.hotspot.runtime.linux_riscv64.LinuxRISCV64JavaThreadPDAccess; + import sun.jvm.hotspot.runtime.linux_ppc64.LinuxPPC64JavaThreadPDAccess; ++import sun.jvm.hotspot.runtime.linux_mips64.LinuxMIPS64JavaThreadPDAccess; ++import sun.jvm.hotspot.runtime.linux_loongarch64.LinuxLOONGARCH64JavaThreadPDAccess; + import sun.jvm.hotspot.runtime.bsd_x86.BsdX86JavaThreadPDAccess; + import sun.jvm.hotspot.runtime.bsd_amd64.BsdAMD64JavaThreadPDAccess; + import sun.jvm.hotspot.runtime.bsd_aarch64.BsdAARCH64JavaThreadPDAccess; +@@ -116,6 +124,10 @@ + access = new LinuxAARCH64JavaThreadPDAccess(); + } else if (cpu.equals("riscv64")) { + access = new LinuxRISCV64JavaThreadPDAccess(); ++ } else if (cpu.equals("mips64")) { ++ access = new LinuxMIPS64JavaThreadPDAccess(); ++ } else if (cpu.equals("loongarch64")) { ++ access = new LinuxLOONGARCH64JavaThreadPDAccess(); + } else { + try { + access = (JavaThreadPDAccess) +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/utilities/PlatformInfo.java b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/utilities/PlatformInfo.java +--- a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/utilities/PlatformInfo.java 2024-01-10 05:18:15.000000000 +0800 ++++ b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/utilities/PlatformInfo.java 2024-01-31 14:01:12.980775332 +0800 @@ -22,6 +22,13 @@ * */ @@ -120664,16 +118945,16 @@ index 3e66e24700b..f894792f912 100644 package sun.jvm.hotspot.utilities; /** Provides canonicalized OS and CPU information for the rest of the -@@ -50,7 +57,7 @@ public class PlatformInfo { +@@ -50,7 +57,7 @@ public static boolean knownCPU(String cpu) { final String[] KNOWN = -- new String[] {"i386", "x86", "x86_64", "amd64", "ppc64", "ppc64le", "aarch64"}; -+ new String[] {"i386", "x86", "x86_64", "amd64", "ppc64", "ppc64le", "aarch64", "mips64", "mips64el", "loongarch64"}; +- new String[] {"i386", "x86", "x86_64", "amd64", "ppc64", "ppc64le", "aarch64", "riscv64"}; ++ new String[] {"i386", "x86", "x86_64", "amd64", "ppc64", "ppc64le", "aarch64", "riscv64", "mips64", "mips64el", "loongarch64"}; for(String s : KNOWN) { if(s.equals(cpu)) -@@ -83,6 +90,12 @@ public class PlatformInfo { +@@ -83,6 +90,12 @@ if (cpu.equals("ppc64le")) return "ppc64"; @@ -120686,15 +118967,13 @@ index 3e66e24700b..f894792f912 100644 return cpu; } -diff --git a/src/jdk.internal.vm.ci/share/classes/jdk.vm.ci.hotspot.loongarch64/src/jdk/vm/ci/hotspot/loongarch64/LoongArch64HotSpotJVMCIBackendFactory.java b/src/jdk.internal.vm.ci/share/classes/jdk.vm.ci.hotspot.loongarch64/src/jdk/vm/ci/hotspot/loongarch64/LoongArch64HotSpotJVMCIBackendFactory.java -new file mode 100644 -index 00000000000..e3a7daa1983 ---- /dev/null -+++ b/src/jdk.internal.vm.ci/share/classes/jdk.vm.ci.hotspot.loongarch64/src/jdk/vm/ci/hotspot/loongarch64/LoongArch64HotSpotJVMCIBackendFactory.java +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/jdk.internal.vm.ci/share/classes/jdk/vm/ci/hotspot/loongarch64/LoongArch64HotSpotJVMCIBackendFactory.java b/src/jdk.internal.vm.ci/share/classes/jdk/vm/ci/hotspot/loongarch64/LoongArch64HotSpotJVMCIBackendFactory.java +--- a/src/jdk.internal.vm.ci/share/classes/jdk/vm/ci/hotspot/loongarch64/LoongArch64HotSpotJVMCIBackendFactory.java 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/jdk.internal.vm.ci/share/classes/jdk/vm/ci/hotspot/loongarch64/LoongArch64HotSpotJVMCIBackendFactory.java 2024-01-31 14:01:13.054109362 +0800 @@ -0,0 +1,142 @@ +/* + * Copyright (c) 2015, 2022, Oracle and/or its affiliates. All rights reserved. -+ * Copyright (c) 2022, Loongson Technology. All rights reserved. ++ * Copyright (c) 2022, 2023, Loongson Technology. All rights reserved. + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. + * + * This code is free software; you can redistribute it and/or modify it @@ -120834,15 +119113,13 @@ index 00000000000..e3a7daa1983 + return new JVMCIBackend(metaAccess, codeCache, constantReflection, stackIntrospection); + } +} -diff --git a/src/jdk.internal.vm.ci/share/classes/jdk.vm.ci.hotspot.loongarch64/src/jdk/vm/ci/hotspot/loongarch64/LoongArch64HotSpotRegisterConfig.java b/src/jdk.internal.vm.ci/share/classes/jdk.vm.ci.hotspot.loongarch64/src/jdk/vm/ci/hotspot/loongarch64/LoongArch64HotSpotRegisterConfig.java -new file mode 100644 -index 00000000000..2ee6a4b8472 ---- /dev/null -+++ b/src/jdk.internal.vm.ci/share/classes/jdk.vm.ci.hotspot.loongarch64/src/jdk/vm/ci/hotspot/loongarch64/LoongArch64HotSpotRegisterConfig.java +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/jdk.internal.vm.ci/share/classes/jdk/vm/ci/hotspot/loongarch64/LoongArch64HotSpotRegisterConfig.java b/src/jdk.internal.vm.ci/share/classes/jdk/vm/ci/hotspot/loongarch64/LoongArch64HotSpotRegisterConfig.java +--- a/src/jdk.internal.vm.ci/share/classes/jdk/vm/ci/hotspot/loongarch64/LoongArch64HotSpotRegisterConfig.java 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/jdk.internal.vm.ci/share/classes/jdk/vm/ci/hotspot/loongarch64/LoongArch64HotSpotRegisterConfig.java 2024-01-31 14:01:13.054109362 +0800 @@ -0,0 +1,297 @@ +/* + * Copyright (c) 2015, 2022, Oracle and/or its affiliates. All rights reserved. -+ * Copyright (c) 2022, Loongson Technology. All rights reserved. ++ * Copyright (c) 2022, 2023, Loongson Technology. All rights reserved. + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. + * + * This code is free software; you can redistribute it and/or modify it @@ -121137,15 +119414,13 @@ index 00000000000..2ee6a4b8472 + return String.format("Allocatable: " + getAllocatableRegisters() + "%n" + "CallerSave: " + getCallerSaveRegisters() + "%n"); + } +} -diff --git a/src/jdk.internal.vm.ci/share/classes/jdk.vm.ci.hotspot.loongarch64/src/jdk/vm/ci/hotspot/loongarch64/LoongArch64HotSpotVMConfig.java b/src/jdk.internal.vm.ci/share/classes/jdk.vm.ci.hotspot.loongarch64/src/jdk/vm/ci/hotspot/loongarch64/LoongArch64HotSpotVMConfig.java -new file mode 100644 -index 00000000000..c8605976a0d ---- /dev/null -+++ b/src/jdk.internal.vm.ci/share/classes/jdk.vm.ci.hotspot.loongarch64/src/jdk/vm/ci/hotspot/loongarch64/LoongArch64HotSpotVMConfig.java +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/jdk.internal.vm.ci/share/classes/jdk/vm/ci/hotspot/loongarch64/LoongArch64HotSpotVMConfig.java b/src/jdk.internal.vm.ci/share/classes/jdk/vm/ci/hotspot/loongarch64/LoongArch64HotSpotVMConfig.java +--- a/src/jdk.internal.vm.ci/share/classes/jdk/vm/ci/hotspot/loongarch64/LoongArch64HotSpotVMConfig.java 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/jdk.internal.vm.ci/share/classes/jdk/vm/ci/hotspot/loongarch64/LoongArch64HotSpotVMConfig.java 2024-01-31 14:01:13.054109362 +0800 @@ -0,0 +1,77 @@ +/* + * Copyright (c) 2016, 2022, Oracle and/or its affiliates. All rights reserved. -+ * Copyright (c) 2022, Loongson Technology. All rights reserved. ++ * Copyright (c) 2022, 2023, Loongson Technology. All rights reserved. + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. + * + * This code is free software; you can redistribute it and/or modify it @@ -121220,15 +119495,13 @@ index 00000000000..c8605976a0d + final long loongarch64UAL = getConstant("VM_Version::CPU_UAL", Long.class); + // Checkstyle: resume +} -diff --git a/src/jdk.internal.vm.ci/share/classes/jdk.vm.ci.hotspot.loongarch64/src/jdk/vm/ci/hotspot/loongarch64/package-info.java b/src/jdk.internal.vm.ci/share/classes/jdk.vm.ci.hotspot.loongarch64/src/jdk/vm/ci/hotspot/loongarch64/package-info.java -new file mode 100644 -index 00000000000..1048ea9d64b ---- /dev/null -+++ b/src/jdk.internal.vm.ci/share/classes/jdk.vm.ci.hotspot.loongarch64/src/jdk/vm/ci/hotspot/loongarch64/package-info.java +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/jdk.internal.vm.ci/share/classes/jdk/vm/ci/hotspot/loongarch64/package-info.java b/src/jdk.internal.vm.ci/share/classes/jdk/vm/ci/hotspot/loongarch64/package-info.java +--- a/src/jdk.internal.vm.ci/share/classes/jdk/vm/ci/hotspot/loongarch64/package-info.java 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/jdk.internal.vm.ci/share/classes/jdk/vm/ci/hotspot/loongarch64/package-info.java 2024-01-31 14:01:13.054109362 +0800 @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2018, 2022, Oracle and/or its affiliates. All rights reserved. -+ * Copyright (c) 2022, Loongson Technology. All rights reserved. ++ * Copyright (c) 2022, 2023, Loongson Technology. All rights reserved. + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. + * + * This code is free software; you can redistribute it and/or modify it @@ -121254,15 +119527,13 @@ index 00000000000..1048ea9d64b + * The LoongArch64 HotSpot specific portions of the JVMCI API. + */ +package jdk.vm.ci.hotspot.loongarch64; -diff --git a/src/jdk.internal.vm.ci/share/classes/jdk.vm.ci.loongarch64/src/jdk/vm/ci/loongarch64/LoongArch64.java b/src/jdk.internal.vm.ci/share/classes/jdk.vm.ci.loongarch64/src/jdk/vm/ci/loongarch64/LoongArch64.java -new file mode 100644 -index 00000000000..99201889b84 ---- /dev/null -+++ b/src/jdk.internal.vm.ci/share/classes/jdk.vm.ci.loongarch64/src/jdk/vm/ci/loongarch64/LoongArch64.java +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/jdk.internal.vm.ci/share/classes/jdk/vm/ci/loongarch64/LoongArch64.java b/src/jdk.internal.vm.ci/share/classes/jdk/vm/ci/loongarch64/LoongArch64.java +--- a/src/jdk.internal.vm.ci/share/classes/jdk/vm/ci/loongarch64/LoongArch64.java 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/jdk.internal.vm.ci/share/classes/jdk/vm/ci/loongarch64/LoongArch64.java 2024-01-31 14:01:13.054109362 +0800 @@ -0,0 +1,249 @@ +/* + * Copyright (c) 2015, 2022, Oracle and/or its affiliates. All rights reserved. -+ * Copyright (c) 2022, Loongson Technology. All rights reserved. ++ * Copyright (c) 2022, 2023, Loongson Technology. All rights reserved. + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. + * + * This code is free software; you can redistribute it and/or modify it @@ -121509,15 +119780,13 @@ index 00000000000..99201889b84 + } + } +} -diff --git a/src/jdk.internal.vm.ci/share/classes/jdk.vm.ci.loongarch64/src/jdk/vm/ci/loongarch64/LoongArch64Kind.java b/src/jdk.internal.vm.ci/share/classes/jdk.vm.ci.loongarch64/src/jdk/vm/ci/loongarch64/LoongArch64Kind.java -new file mode 100644 -index 00000000000..84b7f2027f1 ---- /dev/null -+++ b/src/jdk.internal.vm.ci/share/classes/jdk.vm.ci.loongarch64/src/jdk/vm/ci/loongarch64/LoongArch64Kind.java +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/jdk.internal.vm.ci/share/classes/jdk/vm/ci/loongarch64/LoongArch64Kind.java b/src/jdk.internal.vm.ci/share/classes/jdk/vm/ci/loongarch64/LoongArch64Kind.java +--- a/src/jdk.internal.vm.ci/share/classes/jdk/vm/ci/loongarch64/LoongArch64Kind.java 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/jdk.internal.vm.ci/share/classes/jdk/vm/ci/loongarch64/LoongArch64Kind.java 2024-01-31 14:01:13.054109362 +0800 @@ -0,0 +1,163 @@ +/* + * Copyright (c) 2015, 2022, Oracle and/or its affiliates. All rights reserved. -+ * Copyright (c) 2022, Loongson Technology. All rights reserved. ++ * Copyright (c) 2022, 2023, Loongson Technology. All rights reserved. + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. + * + * This code is free software; you can redistribute it and/or modify it @@ -121678,15 +119947,13 @@ index 00000000000..84b7f2027f1 + } + } +} -diff --git a/src/jdk.internal.vm.ci/share/classes/jdk.vm.ci.loongarch64/src/jdk/vm/ci/loongarch64/package-info.java b/src/jdk.internal.vm.ci/share/classes/jdk.vm.ci.loongarch64/src/jdk/vm/ci/loongarch64/package-info.java -new file mode 100644 -index 00000000000..9d020833eaf ---- /dev/null -+++ b/src/jdk.internal.vm.ci/share/classes/jdk.vm.ci.loongarch64/src/jdk/vm/ci/loongarch64/package-info.java +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/jdk.internal.vm.ci/share/classes/jdk/vm/ci/loongarch64/package-info.java b/src/jdk.internal.vm.ci/share/classes/jdk/vm/ci/loongarch64/package-info.java +--- a/src/jdk.internal.vm.ci/share/classes/jdk/vm/ci/loongarch64/package-info.java 1970-01-01 08:00:00.000000000 +0800 ++++ b/src/jdk.internal.vm.ci/share/classes/jdk/vm/ci/loongarch64/package-info.java 2024-01-31 14:01:13.054109362 +0800 @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2018, 2022, Oracle and/or its affiliates. All rights reserved. -+ * Copyright (c) 2022, Loongson Technology. All rights reserved. ++ * Copyright (c) 2022, 2023, Loongson Technology. All rights reserved. + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. + * + * This code is free software; you can redistribute it and/or modify it @@ -121712,10 +119979,9 @@ index 00000000000..9d020833eaf + * The LoongArch64 platform independent portions of the JVMCI API. + */ +package jdk.vm.ci.loongarch64; -diff --git a/src/jdk.internal.vm.ci/share/classes/module-info.java b/src/jdk.internal.vm.ci/share/classes/module-info.java -index ed197695720..62a4ff4be0f 100644 ---- a/src/jdk.internal.vm.ci/share/classes/module-info.java -+++ b/src/jdk.internal.vm.ci/share/classes/module-info.java +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/jdk.internal.vm.ci/share/classes/module-info.java b/src/jdk.internal.vm.ci/share/classes/module-info.java +--- a/src/jdk.internal.vm.ci/share/classes/module-info.java 2024-01-10 05:18:15.000000000 +0800 ++++ b/src/jdk.internal.vm.ci/share/classes/module-info.java 2024-01-31 14:01:13.057442726 +0800 @@ -23,6 +23,12 @@ * questions. */ @@ -121729,18 +119995,17 @@ index ed197695720..62a4ff4be0f 100644 module jdk.internal.vm.ci { exports jdk.vm.ci.services to jdk.internal.vm.compiler, -@@ -39,5 +45,6 @@ module jdk.internal.vm.ci { +@@ -39,5 +45,6 @@ provides jdk.vm.ci.hotspot.HotSpotJVMCIBackendFactory with jdk.vm.ci.hotspot.aarch64.AArch64HotSpotJVMCIBackendFactory, + jdk.vm.ci.hotspot.loongarch64.LoongArch64HotSpotJVMCIBackendFactory, jdk.vm.ci.hotspot.amd64.AMD64HotSpotJVMCIBackendFactory; } -diff --git a/src/utils/hsdis/Makefile b/src/utils/hsdis/Makefile -index 66dac7130bd..dd2ccd340f2 100644 ---- a/src/utils/hsdis/Makefile -+++ b/src/utils/hsdis/Makefile -@@ -89,6 +89,9 @@ CC = gcc +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/src/utils/hsdis/Makefile b/src/utils/hsdis/Makefile +--- a/src/utils/hsdis/Makefile 2024-01-10 05:18:15.000000000 +0800 ++++ b/src/utils/hsdis/Makefile 2024-01-31 14:01:13.247444526 +0800 +@@ -89,6 +89,9 @@ endif CFLAGS += -O DLDFLAGS += -shared @@ -121750,60 +120015,55 @@ index 66dac7130bd..dd2ccd340f2 100644 LDFLAGS += -ldl OUTFLAGS += -o $@ else -diff --git a/test/hotspot/jtreg/compiler/cpuflags/TestAESIntrinsicsOnSupportedConfig.java b/test/hotspot/jtreg/compiler/cpuflags/TestAESIntrinsicsOnSupportedConfig.java -index 273da8ce7f2..3c81fc96949 100644 ---- a/test/hotspot/jtreg/compiler/cpuflags/TestAESIntrinsicsOnSupportedConfig.java -+++ b/test/hotspot/jtreg/compiler/cpuflags/TestAESIntrinsicsOnSupportedConfig.java -@@ -21,12 +21,18 @@ - * questions. +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/test/hotspot/jtreg/compiler/cpuflags/TestAESIntrinsicsOnSupportedConfig.java b/test/hotspot/jtreg/compiler/cpuflags/TestAESIntrinsicsOnSupportedConfig.java +--- a/test/hotspot/jtreg/compiler/cpuflags/TestAESIntrinsicsOnSupportedConfig.java 2024-01-10 05:18:15.000000000 +0800 ++++ b/test/hotspot/jtreg/compiler/cpuflags/TestAESIntrinsicsOnSupportedConfig.java 2024-01-31 14:01:13.304111732 +0800 +@@ -22,11 +22,17 @@ */ -+/* + /* + * This file has been modified by Loongson Technology in 2021, These + * modifications are Copyright (c) 2021, Loongson Technology, and are made + * available on the same license terms set forth above. + */ + - /* ++/* * @test * @library /test/lib / * @modules java.base/jdk.internal.misc * java.management - * @requires vm.cpu.features ~= ".*aes.*" & !vm.graal.enabled + * @requires (vm.cpu.features ~= ".*aes.*" | os.arch == "loongarch64") & !vm.graal.enabled - * @build sun.hotspot.WhiteBox - * @run driver jdk.test.lib.helpers.ClassFileInstaller sun.hotspot.WhiteBox + * @build jdk.test.whitebox.WhiteBox + * @run driver jdk.test.lib.helpers.ClassFileInstaller jdk.test.whitebox.WhiteBox * @run main/othervm/timeout=600 -Xbootclasspath/a:. -diff --git a/test/hotspot/jtreg/compiler/cpuflags/TestAESIntrinsicsOnUnsupportedConfig.java b/test/hotspot/jtreg/compiler/cpuflags/TestAESIntrinsicsOnUnsupportedConfig.java -index f13c5dd2b89..460a3dafe38 100644 ---- a/test/hotspot/jtreg/compiler/cpuflags/TestAESIntrinsicsOnUnsupportedConfig.java -+++ b/test/hotspot/jtreg/compiler/cpuflags/TestAESIntrinsicsOnUnsupportedConfig.java -@@ -21,6 +21,12 @@ - * questions. +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/test/hotspot/jtreg/compiler/cpuflags/TestAESIntrinsicsOnUnsupportedConfig.java b/test/hotspot/jtreg/compiler/cpuflags/TestAESIntrinsicsOnUnsupportedConfig.java +--- a/test/hotspot/jtreg/compiler/cpuflags/TestAESIntrinsicsOnUnsupportedConfig.java 2024-01-10 05:18:15.000000000 +0800 ++++ b/test/hotspot/jtreg/compiler/cpuflags/TestAESIntrinsicsOnUnsupportedConfig.java 2024-01-31 14:01:13.304111732 +0800 +@@ -22,13 +22,19 @@ */ -+/* + /* + * This file has been modified by Loongson Technology in 2021, These + * modifications are Copyright (c) 2021, Loongson Technology, and are made + * available on the same license terms set forth above. + */ + - /* ++/* * @test * @library /test/lib / -@@ -28,7 +34,7 @@ + * @modules java.base/jdk.internal.misc * java.management * - * @build sun.hotspot.WhiteBox + * @build jdk.test.whitebox.WhiteBox - * @requires !(vm.cpu.features ~= ".*aes.*") + * @requires !(vm.cpu.features ~= ".*aes.*" | os.arch == "loongarch64") * @requires vm.compiler1.enabled | !vm.graal.enabled - * @run driver jdk.test.lib.helpers.ClassFileInstaller sun.hotspot.WhiteBox + * @run driver jdk.test.lib.helpers.ClassFileInstaller jdk.test.whitebox.WhiteBox * @run main/othervm -Xbootclasspath/a:. -XX:+UnlockDiagnosticVMOptions -diff --git a/test/hotspot/jtreg/compiler/intrinsics/sha/cli/testcases/GenericTestCaseForOtherCPU.java b/test/hotspot/jtreg/compiler/intrinsics/sha/cli/testcases/GenericTestCaseForOtherCPU.java -index 2b8d143dd68..0209ea644ef 100644 ---- a/test/hotspot/jtreg/compiler/intrinsics/sha/cli/testcases/GenericTestCaseForOtherCPU.java -+++ b/test/hotspot/jtreg/compiler/intrinsics/sha/cli/testcases/GenericTestCaseForOtherCPU.java +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/test/hotspot/jtreg/compiler/intrinsics/sha/cli/testcases/GenericTestCaseForOtherCPU.java b/test/hotspot/jtreg/compiler/intrinsics/sha/cli/testcases/GenericTestCaseForOtherCPU.java +--- a/test/hotspot/jtreg/compiler/intrinsics/sha/cli/testcases/GenericTestCaseForOtherCPU.java 2024-01-10 05:18:15.000000000 +0800 ++++ b/test/hotspot/jtreg/compiler/intrinsics/sha/cli/testcases/GenericTestCaseForOtherCPU.java 2024-01-31 14:01:13.317445191 +0800 @@ -21,6 +21,12 @@ * questions. */ @@ -121817,61 +120077,63 @@ index 2b8d143dd68..0209ea644ef 100644 package compiler.intrinsics.sha.cli.testcases; import compiler.intrinsics.sha.cli.DigestOptionsBase; -@@ -32,7 +38,7 @@ import jdk.test.lib.cli.predicate.OrPredicate; +@@ -32,7 +38,7 @@ /** * Generic test case for SHA-related options targeted to any CPU except -- * AArch64, PPC, S390x, and X86. -+ * AArch64, PPC, S390x, LoongArch64, and X86. +- * AArch64, RISCV64, PPC, S390x, and X86. ++ * AArch64, RISCV64, PPC, S390x, LoongArch64, and X86. */ public class GenericTestCaseForOtherCPU extends DigestOptionsBase.TestCase { -@@ -44,13 +50,14 @@ public class GenericTestCaseForOtherCPU extends +@@ -44,14 +50,15 @@ } public GenericTestCaseForOtherCPU(String optionName, boolean checkUseSHA) { -- // Execute the test case on any CPU except AArch64, PPC, S390x, and X86. -+ // Execute the test case on any CPU except AArch64, PPC, S390x, LoongArch64, and X86. +- // Execute the test case on any CPU except AArch64, RISCV64, PPC, S390x, and X86. ++ // Execute the test case on any CPU except AArch64, RISCV64, PPC, S390x, LoongArch64, and X86. super(optionName, new NotPredicate( new OrPredicate(Platform::isAArch64, + new OrPredicate(Platform::isRISCV64, new OrPredicate(Platform::isS390x, new OrPredicate(Platform::isPPC, + new OrPredicate(Platform::isLoongArch64, new OrPredicate(Platform::isX64, -- Platform::isX86)))))); -+ Platform::isX86))))))); +- Platform::isX86))))))); ++ Platform::isX86)))))))); this.checkUseSHA = checkUseSHA; } -diff --git a/test/hotspot/jtreg/compiler/jvmci/jdk.vm.ci.code.test/src/jdk/vm/ci/code/test/CodeInstallationTest.java b/test/hotspot/jtreg/compiler/jvmci/jdk.vm.ci.code.test/src/jdk/vm/ci/code/test/CodeInstallationTest.java -index d7ecc7c04ef..4095202ea30 100644 ---- a/test/hotspot/jtreg/compiler/jvmci/jdk.vm.ci.code.test/src/jdk/vm/ci/code/test/CodeInstallationTest.java -+++ b/test/hotspot/jtreg/compiler/jvmci/jdk.vm.ci.code.test/src/jdk/vm/ci/code/test/CodeInstallationTest.java -@@ -20,14 +20,23 @@ +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/test/hotspot/jtreg/compiler/jvmci/jdk.vm.ci.code.test/src/jdk/vm/ci/code/test/CodeInstallationTest.java b/test/hotspot/jtreg/compiler/jvmci/jdk.vm.ci.code.test/src/jdk/vm/ci/code/test/CodeInstallationTest.java +--- a/test/hotspot/jtreg/compiler/jvmci/jdk.vm.ci.code.test/src/jdk/vm/ci/code/test/CodeInstallationTest.java 2024-01-10 05:18:15.000000000 +0800 ++++ b/test/hotspot/jtreg/compiler/jvmci/jdk.vm.ci.code.test/src/jdk/vm/ci/code/test/CodeInstallationTest.java 2024-01-31 14:01:13.327445286 +0800 +@@ -20,16 +20,25 @@ * or visit www.oracle.com if you need additional information or have any * questions. */ + +/* -+ * This file has been modified by Loongson Technology in 2022, These -+ * modifications are Copyright (c) 2022, Loongson Technology, and are made ++ * This file has been modified by Loongson Technology in 2023, These ++ * modifications are Copyright (c) 2022, 2023, Loongson Technology, and are made + * available on the same license terms set forth above. + */ + package jdk.vm.ci.code.test; import jdk.vm.ci.aarch64.AArch64; -+import jdk.vm.ci.loongarch64.LoongArch64; import jdk.vm.ci.amd64.AMD64; ++import jdk.vm.ci.loongarch64.LoongArch64; import jdk.vm.ci.code.Architecture; import jdk.vm.ci.code.CodeCacheProvider; import jdk.vm.ci.code.InstalledCode; import jdk.vm.ci.code.TargetDescription; -+import jdk.vm.ci.code.test.loongarch64.LoongArch64TestAssembler; import jdk.vm.ci.code.test.aarch64.AArch64TestAssembler; import jdk.vm.ci.code.test.amd64.AMD64TestAssembler; ++import jdk.vm.ci.code.test.loongarch64.LoongArch64TestAssembler; import jdk.vm.ci.hotspot.HotSpotCodeCacheProvider; -@@ -75,6 +84,8 @@ public class CodeInstallationTest { + import jdk.vm.ci.hotspot.HotSpotCompiledCode; + import jdk.vm.ci.hotspot.HotSpotJVMCIRuntime; +@@ -75,6 +84,8 @@ return new AMD64TestAssembler(codeCache, config); } else if (arch instanceof AArch64) { return new AArch64TestAssembler(codeCache, config); @@ -121880,10 +120142,9 @@ index d7ecc7c04ef..4095202ea30 100644 } else { Assert.fail("unsupported architecture"); return null; -diff --git a/test/hotspot/jtreg/compiler/jvmci/jdk.vm.ci.code.test/src/jdk/vm/ci/code/test/DataPatchTest.java b/test/hotspot/jtreg/compiler/jvmci/jdk.vm.ci.code.test/src/jdk/vm/ci/code/test/DataPatchTest.java -index 2e3f90368b1..a07fcc8af94 100644 ---- a/test/hotspot/jtreg/compiler/jvmci/jdk.vm.ci.code.test/src/jdk/vm/ci/code/test/DataPatchTest.java -+++ b/test/hotspot/jtreg/compiler/jvmci/jdk.vm.ci.code.test/src/jdk/vm/ci/code/test/DataPatchTest.java +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/test/hotspot/jtreg/compiler/jvmci/jdk.vm.ci.code.test/src/jdk/vm/ci/code/test/DataPatchTest.java b/test/hotspot/jtreg/compiler/jvmci/jdk.vm.ci.code.test/src/jdk/vm/ci/code/test/DataPatchTest.java +--- a/test/hotspot/jtreg/compiler/jvmci/jdk.vm.ci.code.test/src/jdk/vm/ci/code/test/DataPatchTest.java 2024-01-10 05:18:15.000000000 +0800 ++++ b/test/hotspot/jtreg/compiler/jvmci/jdk.vm.ci.code.test/src/jdk/vm/ci/code/test/DataPatchTest.java 2024-01-31 14:01:13.327445286 +0800 @@ -21,10 +21,16 @@ * questions. */ @@ -121913,10 +120174,9 @@ index 2e3f90368b1..a07fcc8af94 100644 * @run junit/othervm -XX:+UnlockExperimentalVMOptions -XX:+EnableJVMCI -XX:-UseJVMCICompiler jdk.vm.ci.code.test.DataPatchTest */ -diff --git a/test/hotspot/jtreg/compiler/jvmci/jdk.vm.ci.code.test/src/jdk/vm/ci/code/test/InterpreterFrameSizeTest.java b/test/hotspot/jtreg/compiler/jvmci/jdk.vm.ci.code.test/src/jdk/vm/ci/code/test/InterpreterFrameSizeTest.java -index b88832677eb..00860c8a66a 100644 ---- a/test/hotspot/jtreg/compiler/jvmci/jdk.vm.ci.code.test/src/jdk/vm/ci/code/test/InterpreterFrameSizeTest.java -+++ b/test/hotspot/jtreg/compiler/jvmci/jdk.vm.ci.code.test/src/jdk/vm/ci/code/test/InterpreterFrameSizeTest.java +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/test/hotspot/jtreg/compiler/jvmci/jdk.vm.ci.code.test/src/jdk/vm/ci/code/test/InterpreterFrameSizeTest.java b/test/hotspot/jtreg/compiler/jvmci/jdk.vm.ci.code.test/src/jdk/vm/ci/code/test/InterpreterFrameSizeTest.java +--- a/test/hotspot/jtreg/compiler/jvmci/jdk.vm.ci.code.test/src/jdk/vm/ci/code/test/InterpreterFrameSizeTest.java 2024-01-10 05:18:15.000000000 +0800 ++++ b/test/hotspot/jtreg/compiler/jvmci/jdk.vm.ci.code.test/src/jdk/vm/ci/code/test/InterpreterFrameSizeTest.java 2024-01-31 14:01:13.327445286 +0800 @@ -21,10 +21,16 @@ * questions. */ @@ -121946,176 +120206,9 @@ index b88832677eb..00860c8a66a 100644 * @run junit/othervm -XX:+UnlockExperimentalVMOptions -XX:+EnableJVMCI -XX:-UseJVMCICompiler jdk.vm.ci.code.test.InterpreterFrameSizeTest */ -diff --git a/test/hotspot/jtreg/compiler/jvmci/jdk.vm.ci.code.test/src/jdk/vm/ci/code/test/MaxOopMapStackOffsetTest.java b/test/hotspot/jtreg/compiler/jvmci/jdk.vm.ci.code.test/src/jdk/vm/ci/code/test/MaxOopMapStackOffsetTest.java -index f473d089a54..6ca7b76f1e7 100644 ---- a/test/hotspot/jtreg/compiler/jvmci/jdk.vm.ci.code.test/src/jdk/vm/ci/code/test/MaxOopMapStackOffsetTest.java -+++ b/test/hotspot/jtreg/compiler/jvmci/jdk.vm.ci.code.test/src/jdk/vm/ci/code/test/MaxOopMapStackOffsetTest.java -@@ -21,10 +21,16 @@ - * questions. - */ - -+/* -+ * This file has been modified by Loongson Technology in 2022, These -+ * modifications are Copyright (c) 2022, Loongson Technology, and are made -+ * available on the same license terms set forth above. -+ */ -+ - /** - * @test - * @requires vm.jvmci -- * @requires vm.simpleArch == "x64" | vm.simpleArch == "aarch64" -+ * @requires vm.simpleArch == "x64" | vm.simpleArch == "aarch64" | vm.simpleArch == "loongarch64" - * @library / - * @modules jdk.internal.vm.ci/jdk.vm.ci.hotspot - * jdk.internal.vm.ci/jdk.vm.ci.meta -@@ -33,8 +39,9 @@ - * jdk.internal.vm.ci/jdk.vm.ci.common - * jdk.internal.vm.ci/jdk.vm.ci.runtime - * jdk.internal.vm.ci/jdk.vm.ci.aarch64 -+ * jdk.internal.vm.ci/jdk.vm.ci.loongarch64 - * jdk.internal.vm.ci/jdk.vm.ci.amd64 -- * @compile CodeInstallationTest.java DebugInfoTest.java TestAssembler.java TestHotSpotVMConfig.java amd64/AMD64TestAssembler.java aarch64/AArch64TestAssembler.java -+ * @compile CodeInstallationTest.java DebugInfoTest.java TestAssembler.java TestHotSpotVMConfig.java amd64/AMD64TestAssembler.java aarch64/AArch64TestAssembler.java loongarch64/LoongArch64TestAssembler.java - * @run junit/othervm -XX:+UnlockExperimentalVMOptions -XX:+EnableJVMCI -XX:-UseJVMCICompiler jdk.vm.ci.code.test.MaxOopMapStackOffsetTest - */ - -diff --git a/test/hotspot/jtreg/compiler/jvmci/jdk.vm.ci.code.test/src/jdk/vm/ci/code/test/NativeCallTest.java b/test/hotspot/jtreg/compiler/jvmci/jdk.vm.ci.code.test/src/jdk/vm/ci/code/test/NativeCallTest.java -index dce107095d5..d8c855dfb3a 100644 ---- a/test/hotspot/jtreg/compiler/jvmci/jdk.vm.ci.code.test/src/jdk/vm/ci/code/test/NativeCallTest.java -+++ b/test/hotspot/jtreg/compiler/jvmci/jdk.vm.ci.code.test/src/jdk/vm/ci/code/test/NativeCallTest.java -@@ -21,10 +21,16 @@ - * questions. - */ - -+/* -+ * This file has been modified by Loongson Technology in 2022, These -+ * modifications are Copyright (c) 2022, Loongson Technology, and are made -+ * available on the same license terms set forth above. -+ */ -+ - /** - * @test - * @requires vm.jvmci -- * @requires vm.simpleArch == "x64" | vm.simpleArch == "aarch64" -+ * @requires vm.simpleArch == "x64" | vm.simpleArch == "aarch64" | vm.simpleArch == "loongarch64" - * @library /test/lib / - * @modules jdk.internal.vm.ci/jdk.vm.ci.hotspot - * jdk.internal.vm.ci/jdk.vm.ci.code -@@ -33,8 +39,9 @@ - * jdk.internal.vm.ci/jdk.vm.ci.runtime - * jdk.internal.vm.ci/jdk.vm.ci.common - * jdk.internal.vm.ci/jdk.vm.ci.aarch64 -+ * jdk.internal.vm.ci/jdk.vm.ci.loongarch64 - * jdk.internal.vm.ci/jdk.vm.ci.amd64 -- * @compile CodeInstallationTest.java TestHotSpotVMConfig.java NativeCallTest.java TestAssembler.java amd64/AMD64TestAssembler.java aarch64/AArch64TestAssembler.java -+ * @compile CodeInstallationTest.java TestHotSpotVMConfig.java NativeCallTest.java TestAssembler.java amd64/AMD64TestAssembler.java aarch64/AArch64TestAssembler.java loongarch64/LoongArch64TestAssembler.java - * @run junit/othervm/native -XX:+UnlockExperimentalVMOptions -XX:+EnableJVMCI -Xbootclasspath/a:. jdk.vm.ci.code.test.NativeCallTest - */ - package jdk.vm.ci.code.test; -diff --git a/test/hotspot/jtreg/compiler/jvmci/jdk.vm.ci.code.test/src/jdk/vm/ci/code/test/SimpleCodeInstallationTest.java b/test/hotspot/jtreg/compiler/jvmci/jdk.vm.ci.code.test/src/jdk/vm/ci/code/test/SimpleCodeInstallationTest.java -index e5fc53e8013..75494d5ccf1 100644 ---- a/test/hotspot/jtreg/compiler/jvmci/jdk.vm.ci.code.test/src/jdk/vm/ci/code/test/SimpleCodeInstallationTest.java -+++ b/test/hotspot/jtreg/compiler/jvmci/jdk.vm.ci.code.test/src/jdk/vm/ci/code/test/SimpleCodeInstallationTest.java -@@ -21,10 +21,16 @@ - * questions. - */ - -+/* -+ * This file has been modified by Loongson Technology in 2022, These -+ * modifications are Copyright (c) 2022, Loongson Technology, and are made -+ * available on the same license terms set forth above. -+ */ -+ - /** - * @test - * @requires vm.jvmci -- * @requires vm.simpleArch == "x64" | vm.simpleArch == "aarch64" -+ * @requires vm.simpleArch == "x64" | vm.simpleArch == "aarch64" | vm.simpleArch == "loongarch64" - * @library / - * @modules jdk.internal.vm.ci/jdk.vm.ci.hotspot - * jdk.internal.vm.ci/jdk.vm.ci.meta -@@ -32,8 +38,9 @@ - * jdk.internal.vm.ci/jdk.vm.ci.code.site - * jdk.internal.vm.ci/jdk.vm.ci.runtime - * jdk.internal.vm.ci/jdk.vm.ci.aarch64 -+ * jdk.internal.vm.ci/jdk.vm.ci.loongarch64 - * jdk.internal.vm.ci/jdk.vm.ci.amd64 -- * @compile CodeInstallationTest.java DebugInfoTest.java TestAssembler.java TestHotSpotVMConfig.java amd64/AMD64TestAssembler.java aarch64/AArch64TestAssembler.java -+ * @compile CodeInstallationTest.java DebugInfoTest.java TestAssembler.java TestHotSpotVMConfig.java amd64/AMD64TestAssembler.java aarch64/AArch64TestAssembler.java loongarch64/LoongArch64TestAssembler.java - * @run junit/othervm -XX:+UnlockExperimentalVMOptions -XX:+EnableJVMCI -XX:-UseJVMCICompiler jdk.vm.ci.code.test.SimpleCodeInstallationTest - */ - -diff --git a/test/hotspot/jtreg/compiler/jvmci/jdk.vm.ci.code.test/src/jdk/vm/ci/code/test/SimpleDebugInfoTest.java b/test/hotspot/jtreg/compiler/jvmci/jdk.vm.ci.code.test/src/jdk/vm/ci/code/test/SimpleDebugInfoTest.java -index bfd611312a2..08be94ac132 100644 ---- a/test/hotspot/jtreg/compiler/jvmci/jdk.vm.ci.code.test/src/jdk/vm/ci/code/test/SimpleDebugInfoTest.java -+++ b/test/hotspot/jtreg/compiler/jvmci/jdk.vm.ci.code.test/src/jdk/vm/ci/code/test/SimpleDebugInfoTest.java -@@ -21,10 +21,16 @@ - * questions. - */ - -+/* -+ * This file has been modified by Loongson Technology in 2022, These -+ * modifications are Copyright (c) 2022, Loongson Technology, and are made -+ * available on the same license terms set forth above. -+ */ -+ - /** - * @test - * @requires vm.jvmci -- * @requires vm.simpleArch == "x64" | vm.simpleArch == "aarch64" -+ * @requires vm.simpleArch == "x64" | vm.simpleArch == "aarch64" | vm.simpleArch == "loongarch64" - * @library / - * @modules jdk.internal.vm.ci/jdk.vm.ci.hotspot - * jdk.internal.vm.ci/jdk.vm.ci.meta -@@ -32,8 +38,9 @@ - * jdk.internal.vm.ci/jdk.vm.ci.code.site - * jdk.internal.vm.ci/jdk.vm.ci.runtime - * jdk.internal.vm.ci/jdk.vm.ci.aarch64 -+ * jdk.internal.vm.ci/jdk.vm.ci.loongarch64 - * jdk.internal.vm.ci/jdk.vm.ci.amd64 -- * @compile CodeInstallationTest.java DebugInfoTest.java TestAssembler.java TestHotSpotVMConfig.java amd64/AMD64TestAssembler.java aarch64/AArch64TestAssembler.java -+ * @compile CodeInstallationTest.java DebugInfoTest.java TestAssembler.java TestHotSpotVMConfig.java amd64/AMD64TestAssembler.java aarch64/AArch64TestAssembler.java loongarch64/LoongArch64TestAssembler.java - * @run junit/othervm -XX:+UnlockExperimentalVMOptions -XX:+EnableJVMCI -XX:-UseJVMCICompiler jdk.vm.ci.code.test.SimpleDebugInfoTest - */ - -diff --git a/test/hotspot/jtreg/compiler/jvmci/jdk.vm.ci.code.test/src/jdk/vm/ci/code/test/VirtualObjectDebugInfoTest.java b/test/hotspot/jtreg/compiler/jvmci/jdk.vm.ci.code.test/src/jdk/vm/ci/code/test/VirtualObjectDebugInfoTest.java -index 1fb0d77eb73..b2d40f70a80 100644 ---- a/test/hotspot/jtreg/compiler/jvmci/jdk.vm.ci.code.test/src/jdk/vm/ci/code/test/VirtualObjectDebugInfoTest.java -+++ b/test/hotspot/jtreg/compiler/jvmci/jdk.vm.ci.code.test/src/jdk/vm/ci/code/test/VirtualObjectDebugInfoTest.java -@@ -21,10 +21,16 @@ - * questions. - */ - -+/* -+ * This file has been modified by Loongson Technology in 2022, These -+ * modifications are Copyright (c) 2022, Loongson Technology, and are made -+ * available on the same license terms set forth above. -+ */ -+ - /** - * @test - * @requires vm.jvmci -- * @requires vm.simpleArch == "x64" | vm.simpleArch == "aarch64" -+ * @requires vm.simpleArch == "x64" | vm.simpleArch == "aarch64" | vm.simpleArch == "loongarch64" - * @library / - * @modules jdk.internal.vm.ci/jdk.vm.ci.hotspot - * jdk.internal.vm.ci/jdk.vm.ci.meta -@@ -32,8 +38,9 @@ - * jdk.internal.vm.ci/jdk.vm.ci.code.site - * jdk.internal.vm.ci/jdk.vm.ci.runtime - * jdk.internal.vm.ci/jdk.vm.ci.aarch64 -+ * jdk.internal.vm.ci/jdk.vm.ci.loongarch64 - * jdk.internal.vm.ci/jdk.vm.ci.amd64 -- * @compile CodeInstallationTest.java DebugInfoTest.java TestAssembler.java TestHotSpotVMConfig.java amd64/AMD64TestAssembler.java aarch64/AArch64TestAssembler.java -+ * @compile CodeInstallationTest.java DebugInfoTest.java TestAssembler.java TestHotSpotVMConfig.java amd64/AMD64TestAssembler.java aarch64/AArch64TestAssembler.java loongarch64/LoongArch64TestAssembler.java - * @run junit/othervm -XX:+UnlockExperimentalVMOptions -XX:+EnableJVMCI -XX:-UseJVMCICompiler jdk.vm.ci.code.test.VirtualObjectDebugInfoTest - */ - -diff --git a/test/hotspot/jtreg/compiler/jvmci/jdk.vm.ci.code.test/src/jdk/vm/ci/code/test/loongarch64/LoongArch64TestAssembler.java b/test/hotspot/jtreg/compiler/jvmci/jdk.vm.ci.code.test/src/jdk/vm/ci/code/test/loongarch64/LoongArch64TestAssembler.java -new file mode 100644 -index 00000000000..4c76868453a ---- /dev/null -+++ b/test/hotspot/jtreg/compiler/jvmci/jdk.vm.ci.code.test/src/jdk/vm/ci/code/test/loongarch64/LoongArch64TestAssembler.java +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/test/hotspot/jtreg/compiler/jvmci/jdk.vm.ci.code.test/src/jdk/vm/ci/code/test/loongarch64/LoongArch64TestAssembler.java b/test/hotspot/jtreg/compiler/jvmci/jdk.vm.ci.code.test/src/jdk/vm/ci/code/test/loongarch64/LoongArch64TestAssembler.java +--- a/test/hotspot/jtreg/compiler/jvmci/jdk.vm.ci.code.test/src/jdk/vm/ci/code/test/loongarch64/LoongArch64TestAssembler.java 1970-01-01 08:00:00.000000000 +0800 ++++ b/test/hotspot/jtreg/compiler/jvmci/jdk.vm.ci.code.test/src/jdk/vm/ci/code/test/loongarch64/LoongArch64TestAssembler.java 2024-01-31 14:01:13.327445286 +0800 @@ -0,0 +1,568 @@ +/* + * Copyright (c) 2020, 2022, Oracle and/or its affiliates. All rights reserved. @@ -122685,11 +120778,10 @@ index 00000000000..4c76868453a + } + +} -diff --git a/test/hotspot/jtreg/compiler/lib/ir_framework/IRNode.java b/test/hotspot/jtreg/compiler/lib/ir_framework/IRNode.java -index bbbec26406d..5989d3fd6c2 100644 ---- a/test/hotspot/jtreg/compiler/lib/ir_framework/IRNode.java -+++ b/test/hotspot/jtreg/compiler/lib/ir_framework/IRNode.java -@@ -21,6 +21,12 @@ +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/test/hotspot/jtreg/compiler/jvmci/jdk.vm.ci.code.test/src/jdk/vm/ci/code/test/MaxOopMapStackOffsetTest.java b/test/hotspot/jtreg/compiler/jvmci/jdk.vm.ci.code.test/src/jdk/vm/ci/code/test/MaxOopMapStackOffsetTest.java +--- a/test/hotspot/jtreg/compiler/jvmci/jdk.vm.ci.code.test/src/jdk/vm/ci/code/test/MaxOopMapStackOffsetTest.java 2024-01-10 05:18:15.000000000 +0800 ++++ b/test/hotspot/jtreg/compiler/jvmci/jdk.vm.ci.code.test/src/jdk/vm/ci/code/test/MaxOopMapStackOffsetTest.java 2024-01-31 14:01:13.327445286 +0800 +@@ -21,10 +21,16 @@ * questions. */ @@ -122699,68 +120791,183 @@ index bbbec26406d..5989d3fd6c2 100644 + * available on the same license terms set forth above. + */ + - package compiler.lib.ir_framework; + /** + * @test + * @requires vm.jvmci +- * @requires vm.simpleArch == "x64" | vm.simpleArch == "aarch64" ++ * @requires vm.simpleArch == "x64" | vm.simpleArch == "aarch64" | vm.simpleArch == "loongarch64" + * @library / + * @modules jdk.internal.vm.ci/jdk.vm.ci.hotspot + * jdk.internal.vm.ci/jdk.vm.ci.meta +@@ -33,8 +39,9 @@ + * jdk.internal.vm.ci/jdk.vm.ci.common + * jdk.internal.vm.ci/jdk.vm.ci.runtime + * jdk.internal.vm.ci/jdk.vm.ci.aarch64 ++ * jdk.internal.vm.ci/jdk.vm.ci.loongarch64 + * jdk.internal.vm.ci/jdk.vm.ci.amd64 +- * @compile CodeInstallationTest.java DebugInfoTest.java TestAssembler.java TestHotSpotVMConfig.java amd64/AMD64TestAssembler.java aarch64/AArch64TestAssembler.java ++ * @compile CodeInstallationTest.java DebugInfoTest.java TestAssembler.java TestHotSpotVMConfig.java amd64/AMD64TestAssembler.java aarch64/AArch64TestAssembler.java loongarch64/LoongArch64TestAssembler.java + * @run junit/othervm -XX:+UnlockExperimentalVMOptions -XX:+EnableJVMCI -XX:-UseJVMCICompiler jdk.vm.ci.code.test.MaxOopMapStackOffsetTest + */ - import compiler.lib.ir_framework.driver.irmatching.IRMatcher; -@@ -58,8 +64,8 @@ public class IRNode { - public static final String ALLOC_ARRAY = "(.*precise klass \\[L.*\\R((.*(?i:mov|xor|nop|spill).*|\\s*|.*LGHI.*)\\R)*.*(?i:call,static).*wrapper for: _new_array_Java" + END; - public static final String ALLOC_ARRAY_OF = COMPOSITE_PREFIX + "(.*precise klass \\[L.*" + IS_REPLACED + ";:.*\\R((.*(?i:mov|xorl|nop|spill).*|\\s*|.*LGHI.*)\\R)*.*(?i:call,static).*wrapper for: _new_array_Java" + END; +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/test/hotspot/jtreg/compiler/jvmci/jdk.vm.ci.code.test/src/jdk/vm/ci/code/test/NativeCallTest.java b/test/hotspot/jtreg/compiler/jvmci/jdk.vm.ci.code.test/src/jdk/vm/ci/code/test/NativeCallTest.java +--- a/test/hotspot/jtreg/compiler/jvmci/jdk.vm.ci.code.test/src/jdk/vm/ci/code/test/NativeCallTest.java 2024-01-10 05:18:15.000000000 +0800 ++++ b/test/hotspot/jtreg/compiler/jvmci/jdk.vm.ci.code.test/src/jdk/vm/ci/code/test/NativeCallTest.java 2024-01-31 14:01:13.327445286 +0800 +@@ -21,10 +21,16 @@ + * questions. + */ -- public static final String CHECKCAST_ARRAY = "(((?i:cmp|CLFI|CLR).*precise klass \\[.*;:|.*(?i:mov|or).*precise klass \\[.*;:.*\\R.*(cmp|CMP|CLR))" + END; -- public static final String CHECKCAST_ARRAY_OF = COMPOSITE_PREFIX + "(((?i:cmp|CLFI|CLR).*precise klass \\[.*" + IS_REPLACED + ";:|.*(?i:mov|or).*precise klass \\[.*" + IS_REPLACED + ";:.*\\R.*(cmp|CMP|CLR))" + END; -+ public static final String CHECKCAST_ARRAY = "(((?i:cmp|CLFI|CLR).*precise klass \\[.*;:|.*(?i:mov|or|li).*precise klass \\[.*;:.*\\R.*(cmp|CMP|CLR))" + END; -+ public static final String CHECKCAST_ARRAY_OF = COMPOSITE_PREFIX + "(((?i:cmp|CLFI|CLR).*precise klass \\[.*" + IS_REPLACED + ";:|.*(?i:mov|or|li).*precise klass \\[.*" + IS_REPLACED + ";:.*\\R.*(cmp|CMP|CLR))" + END; - // Does not work on s390 (a rule containing this regex will be skipped on s390). - public static final String CHECKCAST_ARRAYCOPY = "(.*((?i:call_leaf_nofp,runtime)|CALL,\\s?runtime leaf nofp|BCTRL.*.leaf call).*checkcast_arraycopy.*" + END; ++/* ++ * This file has been modified by Loongson Technology in 2022, These ++ * modifications are Copyright (c) 2022, Loongson Technology, and are made ++ * available on the same license terms set forth above. ++ */ ++ + /** + * @test + * @requires vm.jvmci +- * @requires vm.simpleArch == "x64" | vm.simpleArch == "aarch64" ++ * @requires vm.simpleArch == "x64" | vm.simpleArch == "aarch64" | vm.simpleArch == "loongarch64" + * @library /test/lib / + * @modules jdk.internal.vm.ci/jdk.vm.ci.hotspot + * jdk.internal.vm.ci/jdk.vm.ci.code +@@ -33,8 +39,9 @@ + * jdk.internal.vm.ci/jdk.vm.ci.runtime + * jdk.internal.vm.ci/jdk.vm.ci.common + * jdk.internal.vm.ci/jdk.vm.ci.aarch64 ++ * jdk.internal.vm.ci/jdk.vm.ci.loongarch64 + * jdk.internal.vm.ci/jdk.vm.ci.amd64 +- * @compile CodeInstallationTest.java TestHotSpotVMConfig.java NativeCallTest.java TestAssembler.java amd64/AMD64TestAssembler.java aarch64/AArch64TestAssembler.java ++ * @compile CodeInstallationTest.java TestHotSpotVMConfig.java NativeCallTest.java TestAssembler.java amd64/AMD64TestAssembler.java aarch64/AArch64TestAssembler.java loongarch64/LoongArch64TestAssembler.java + * @run junit/othervm/native -XX:+UnlockExperimentalVMOptions -XX:+EnableJVMCI -Xbootclasspath/a:. jdk.vm.ci.code.test.NativeCallTest + */ + package jdk.vm.ci.code.test; +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/test/hotspot/jtreg/compiler/jvmci/jdk.vm.ci.code.test/src/jdk/vm/ci/code/test/SimpleCodeInstallationTest.java b/test/hotspot/jtreg/compiler/jvmci/jdk.vm.ci.code.test/src/jdk/vm/ci/code/test/SimpleCodeInstallationTest.java +--- a/test/hotspot/jtreg/compiler/jvmci/jdk.vm.ci.code.test/src/jdk/vm/ci/code/test/SimpleCodeInstallationTest.java 2024-01-10 05:18:15.000000000 +0800 ++++ b/test/hotspot/jtreg/compiler/jvmci/jdk.vm.ci.code.test/src/jdk/vm/ci/code/test/SimpleCodeInstallationTest.java 2024-01-31 14:01:13.327445286 +0800 +@@ -21,10 +21,16 @@ + * questions. + */ -diff --git a/test/hotspot/jtreg/compiler/runtime/TestConstantsInError.java b/test/hotspot/jtreg/compiler/runtime/TestConstantsInError.java -index 2f9189cd9bc..eb9db789f91 100644 ---- a/test/hotspot/jtreg/compiler/runtime/TestConstantsInError.java -+++ b/test/hotspot/jtreg/compiler/runtime/TestConstantsInError.java -@@ -21,6 +21,12 @@ ++/* ++ * This file has been modified by Loongson Technology in 2022, These ++ * modifications are Copyright (c) 2022, Loongson Technology, and are made ++ * available on the same license terms set forth above. ++ */ ++ + /** + * @test + * @requires vm.jvmci +- * @requires vm.simpleArch == "x64" | vm.simpleArch == "aarch64" ++ * @requires vm.simpleArch == "x64" | vm.simpleArch == "aarch64" | vm.simpleArch == "loongarch64" + * @library / + * @modules jdk.internal.vm.ci/jdk.vm.ci.hotspot + * jdk.internal.vm.ci/jdk.vm.ci.meta +@@ -32,8 +38,9 @@ + * jdk.internal.vm.ci/jdk.vm.ci.code.site + * jdk.internal.vm.ci/jdk.vm.ci.runtime + * jdk.internal.vm.ci/jdk.vm.ci.aarch64 ++ * jdk.internal.vm.ci/jdk.vm.ci.loongarch64 + * jdk.internal.vm.ci/jdk.vm.ci.amd64 +- * @compile CodeInstallationTest.java DebugInfoTest.java TestAssembler.java TestHotSpotVMConfig.java amd64/AMD64TestAssembler.java aarch64/AArch64TestAssembler.java ++ * @compile CodeInstallationTest.java DebugInfoTest.java TestAssembler.java TestHotSpotVMConfig.java amd64/AMD64TestAssembler.java aarch64/AArch64TestAssembler.java loongarch64/LoongArch64TestAssembler.java + * @run junit/othervm -XX:+UnlockExperimentalVMOptions -XX:+EnableJVMCI -XX:-UseJVMCICompiler jdk.vm.ci.code.test.SimpleCodeInstallationTest + */ + +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/test/hotspot/jtreg/compiler/jvmci/jdk.vm.ci.code.test/src/jdk/vm/ci/code/test/SimpleDebugInfoTest.java b/test/hotspot/jtreg/compiler/jvmci/jdk.vm.ci.code.test/src/jdk/vm/ci/code/test/SimpleDebugInfoTest.java +--- a/test/hotspot/jtreg/compiler/jvmci/jdk.vm.ci.code.test/src/jdk/vm/ci/code/test/SimpleDebugInfoTest.java 2024-01-10 05:18:15.000000000 +0800 ++++ b/test/hotspot/jtreg/compiler/jvmci/jdk.vm.ci.code.test/src/jdk/vm/ci/code/test/SimpleDebugInfoTest.java 2024-01-31 14:01:13.327445286 +0800 +@@ -21,10 +21,16 @@ * questions. */ +/* -+ * This file has been modified by Loongson Technology in 2022. These -+ * modifications are Copyright (c) 2022 Loongson Technology, and are made ++ * This file has been modified by Loongson Technology in 2022, These ++ * modifications are Copyright (c) 2022, Loongson Technology, and are made + * available on the same license terms set forth above. + */ + - /* + /** * @test - * @bug 8279822 -@@ -130,7 +136,7 @@ public abstract class TestConstantsInError implements OutputProcessor { - results.shouldMatch("Test_C1/.*::test \\(3 bytes\\)$") - .shouldMatch("Test_C2/.*::test \\(3 bytes\\)$"); + * @requires vm.jvmci +- * @requires vm.simpleArch == "x64" | vm.simpleArch == "aarch64" ++ * @requires vm.simpleArch == "x64" | vm.simpleArch == "aarch64" | vm.simpleArch == "loongarch64" + * @library / + * @modules jdk.internal.vm.ci/jdk.vm.ci.hotspot + * jdk.internal.vm.ci/jdk.vm.ci.meta +@@ -32,8 +38,9 @@ + * jdk.internal.vm.ci/jdk.vm.ci.code.site + * jdk.internal.vm.ci/jdk.vm.ci.runtime + * jdk.internal.vm.ci/jdk.vm.ci.aarch64 ++ * jdk.internal.vm.ci/jdk.vm.ci.loongarch64 + * jdk.internal.vm.ci/jdk.vm.ci.amd64 +- * @compile CodeInstallationTest.java DebugInfoTest.java TestAssembler.java TestHotSpotVMConfig.java amd64/AMD64TestAssembler.java aarch64/AArch64TestAssembler.java ++ * @compile CodeInstallationTest.java DebugInfoTest.java TestAssembler.java TestHotSpotVMConfig.java amd64/AMD64TestAssembler.java aarch64/AArch64TestAssembler.java loongarch64/LoongArch64TestAssembler.java + * @run junit/othervm -XX:+UnlockExperimentalVMOptions -XX:+EnableJVMCI -XX:-UseJVMCICompiler jdk.vm.ci.code.test.SimpleDebugInfoTest + */ -- if (isC1 && Platform.isAArch64()) { // no code patching -+ if (isC1 && (Platform.isAArch64() || Platform.isLoongArch64())) { // no code patching - results.shouldMatch("Test_C1/.*::test \\(3 bytes\\) made not entrant") - .shouldMatch("Test_C2/.*::test \\(3 bytes\\) made not entrant"); - } else { -@@ -168,7 +174,7 @@ public abstract class TestConstantsInError implements OutputProcessor { - .shouldMatch("Test_MH3/.*::test \\(3 bytes\\)$") - .shouldMatch("Test_MH4/.*::test \\(3 bytes\\)$"); +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/test/hotspot/jtreg/compiler/jvmci/jdk.vm.ci.code.test/src/jdk/vm/ci/code/test/VirtualObjectDebugInfoTest.java b/test/hotspot/jtreg/compiler/jvmci/jdk.vm.ci.code.test/src/jdk/vm/ci/code/test/VirtualObjectDebugInfoTest.java +--- a/test/hotspot/jtreg/compiler/jvmci/jdk.vm.ci.code.test/src/jdk/vm/ci/code/test/VirtualObjectDebugInfoTest.java 2024-01-10 05:18:15.000000000 +0800 ++++ b/test/hotspot/jtreg/compiler/jvmci/jdk.vm.ci.code.test/src/jdk/vm/ci/code/test/VirtualObjectDebugInfoTest.java 2024-01-31 14:01:13.327445286 +0800 +@@ -21,10 +21,16 @@ + * questions. + */ -- if (isC1 && Platform.isAArch64()) { // no code patching -+ if (isC1 && (Platform.isAArch64() || Platform.isLoongArch64())) { // no code patching - results.shouldMatch("Test_MH1/.*::test \\(3 bytes\\) made not entrant") - .shouldMatch("Test_MH2/.*::test \\(3 bytes\\) made not entrant") - .shouldMatch("Test_MH3/.*::test \\(3 bytes\\) made not entrant") -@@ -191,7 +197,7 @@ public abstract class TestConstantsInError implements OutputProcessor { - results.shouldMatch("Test_MT1/.*::test \\(3 bytes\\)$") - .shouldMatch("Test_MT2/.*::test \\(3 bytes\\)$"); ++/* ++ * This file has been modified by Loongson Technology in 2022, These ++ * modifications are Copyright (c) 2022, Loongson Technology, and are made ++ * available on the same license terms set forth above. ++ */ ++ + /** + * @test + * @requires vm.jvmci +- * @requires vm.simpleArch == "x64" | vm.simpleArch == "aarch64" ++ * @requires vm.simpleArch == "x64" | vm.simpleArch == "aarch64" | vm.simpleArch == "loongarch64" + * @library / + * @modules jdk.internal.vm.ci/jdk.vm.ci.hotspot + * jdk.internal.vm.ci/jdk.vm.ci.meta +@@ -32,8 +38,9 @@ + * jdk.internal.vm.ci/jdk.vm.ci.code.site + * jdk.internal.vm.ci/jdk.vm.ci.runtime + * jdk.internal.vm.ci/jdk.vm.ci.aarch64 ++ * jdk.internal.vm.ci/jdk.vm.ci.loongarch64 + * jdk.internal.vm.ci/jdk.vm.ci.amd64 +- * @compile CodeInstallationTest.java DebugInfoTest.java TestAssembler.java TestHotSpotVMConfig.java amd64/AMD64TestAssembler.java aarch64/AArch64TestAssembler.java ++ * @compile CodeInstallationTest.java DebugInfoTest.java TestAssembler.java TestHotSpotVMConfig.java amd64/AMD64TestAssembler.java aarch64/AArch64TestAssembler.java loongarch64/LoongArch64TestAssembler.java + * @run junit/othervm -XX:+UnlockExperimentalVMOptions -XX:+EnableJVMCI -XX:-UseJVMCICompiler jdk.vm.ci.code.test.VirtualObjectDebugInfoTest + */ -- if (isC1 && Platform.isAArch64()) { // no code patching -+ if (isC1 && (Platform.isAArch64() || Platform.isLoongArch64())) { // no code patching - results.shouldMatch("Test_MT1/.*::test \\(3 bytes\\) made not entrant") - .shouldMatch("Test_MT2/.*::test \\(3 bytes\\) made not entrant"); - } else { -diff --git a/test/hotspot/jtreg/compiler/runtime/criticalnatives/argumentcorruption/CheckLongArgs.java b/test/hotspot/jtreg/compiler/runtime/criticalnatives/argumentcorruption/CheckLongArgs.java -index d38d76443f0..119acb520da 100644 ---- a/test/hotspot/jtreg/compiler/runtime/criticalnatives/argumentcorruption/CheckLongArgs.java -+++ b/test/hotspot/jtreg/compiler/runtime/criticalnatives/argumentcorruption/CheckLongArgs.java +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/test/hotspot/jtreg/compiler/lib/ir_framework/IRNode.java b/test/hotspot/jtreg/compiler/lib/ir_framework/IRNode.java +--- a/test/hotspot/jtreg/compiler/lib/ir_framework/IRNode.java 2024-01-10 05:18:15.000000000 +0800 ++++ b/test/hotspot/jtreg/compiler/lib/ir_framework/IRNode.java 2024-01-31 14:01:13.330778650 +0800 +@@ -21,6 +21,12 @@ + * questions. + */ + ++/* ++ * This file has been modified by Loongson Technology in 2022, These ++ * modifications are Copyright (c) 2022, Loongson Technology, and are made ++ * available on the same license terms set forth above. ++ */ ++ + package compiler.lib.ir_framework; + + import compiler.lib.ir_framework.driver.irmatching.IRMatcher; +@@ -58,8 +64,8 @@ + public static final String ALLOC_ARRAY = "(.*precise klass \\[L.*\\R((.*(?i:mov|mv|xor|nop|spill).*|\\s*|.*LGHI.*)\\R)*.*(?i:call,static).*wrapper for: _new_array_Java" + END; + public static final String ALLOC_ARRAY_OF = COMPOSITE_PREFIX + "(.*precise klass \\[L.*" + IS_REPLACED + ";:.*\\R((.*(?i:mov|mv|xorl|nop|spill).*|\\s*|.*LGHI.*)\\R)*.*(?i:call,static).*wrapper for: _new_array_Java" + END; + +- public static final String CHECKCAST_ARRAY = "(((?i:cmp|CLFI|CLR).*precise klass \\[.*;:|.*(?i:mov|mv|or).*precise klass \\[.*;:.*\\R.*(cmp|CMP|CLR))" + END; +- public static final String CHECKCAST_ARRAY_OF = COMPOSITE_PREFIX + "(((?i:cmp|CLFI|CLR).*precise klass \\[.*" + IS_REPLACED + ";:|.*(?i:mov|mv|or).*precise klass \\[.*" + IS_REPLACED + ";:.*\\R.*(cmp|CMP|CLR))" + END; ++ public static final String CHECKCAST_ARRAY = "(((?i:cmp|CLFI|CLR).*precise klass \\[.*;:|.*(?i:mov|mv|or|li).*precise klass \\[.*;:.*\\R.*(cmp|CMP|CLR))" + END; ++ public static final String CHECKCAST_ARRAY_OF = COMPOSITE_PREFIX + "(((?i:cmp|CLFI|CLR).*precise klass \\[.*" + IS_REPLACED + ";:|.*(?i:mov|mv|or|li).*precise klass \\[.*" + IS_REPLACED + ";:.*\\R.*(cmp|CMP|CLR))" + END; + // Does not work on s390 (a rule containing this regex will be skipped on s390). + public static final String CHECKCAST_ARRAYCOPY = "(.*((?i:call_leaf_nofp,runtime)|CALL,\\s?runtime leaf nofp|BCTRL.*.leaf call).*checkcast_arraycopy.*" + END; + +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/test/hotspot/jtreg/compiler/runtime/criticalnatives/argumentcorruption/CheckLongArgs.java b/test/hotspot/jtreg/compiler/runtime/criticalnatives/argumentcorruption/CheckLongArgs.java +--- a/test/hotspot/jtreg/compiler/runtime/criticalnatives/argumentcorruption/CheckLongArgs.java 2024-01-10 05:18:15.000000000 +0800 ++++ b/test/hotspot/jtreg/compiler/runtime/criticalnatives/argumentcorruption/CheckLongArgs.java 2024-01-31 14:01:13.350778841 +0800 @@ -21,10 +21,17 @@ * questions. */ @@ -122774,15 +120981,14 @@ index d38d76443f0..119acb520da 100644 /* @test * @bug 8167409 - * @requires (os.arch != "aarch64") & (os.arch != "arm") & (vm.flavor != "zero") + * @requires (os.arch != "aarch64") & (os.arch != "arm") & (os.arch != "riscv64") & (vm.flavor != "zero") + * @requires (os.arch != "mips64el") & (os.arch != "loongarch64") & (vm.flavor != "zero") * @run main/othervm/native -Xcomp -XX:+CriticalJNINatives compiler.runtime.criticalnatives.argumentcorruption.CheckLongArgs */ package compiler.runtime.criticalnatives.argumentcorruption; -diff --git a/test/hotspot/jtreg/compiler/runtime/criticalnatives/lookup/LookUp.java b/test/hotspot/jtreg/compiler/runtime/criticalnatives/lookup/LookUp.java -index 37c42c9c336..d3e73158a25 100644 ---- a/test/hotspot/jtreg/compiler/runtime/criticalnatives/lookup/LookUp.java -+++ b/test/hotspot/jtreg/compiler/runtime/criticalnatives/lookup/LookUp.java +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/test/hotspot/jtreg/compiler/runtime/criticalnatives/lookup/LookUp.java b/test/hotspot/jtreg/compiler/runtime/criticalnatives/lookup/LookUp.java +--- a/test/hotspot/jtreg/compiler/runtime/criticalnatives/lookup/LookUp.java 2024-01-10 05:18:15.000000000 +0800 ++++ b/test/hotspot/jtreg/compiler/runtime/criticalnatives/lookup/LookUp.java 2024-01-31 14:01:13.350778841 +0800 @@ -21,10 +21,17 @@ * questions. */ @@ -122796,15 +121002,57 @@ index 37c42c9c336..d3e73158a25 100644 /* @test * @bug 8167408 - * @requires (os.arch != "aarch64") & (os.arch != "arm") & (vm.flavor != "zero") + * @requires (os.arch != "aarch64") & (os.arch != "arm") & (os.arch != "riscv64") & (vm.flavor != "zero") + * @requires (os.arch != "mips64el") & (os.arch != "loongarch64") & (vm.flavor != "zero") * @run main/othervm/native -Xcomp -XX:+CriticalJNINatives compiler.runtime.criticalnatives.lookup.LookUp */ package compiler.runtime.criticalnatives.lookup; -diff --git a/test/hotspot/jtreg/compiler/testlibrary/sha/predicate/IntrinsicPredicates.java b/test/hotspot/jtreg/compiler/testlibrary/sha/predicate/IntrinsicPredicates.java -index 782ab6b9b46..8b859a92d8a 100644 ---- a/test/hotspot/jtreg/compiler/testlibrary/sha/predicate/IntrinsicPredicates.java -+++ b/test/hotspot/jtreg/compiler/testlibrary/sha/predicate/IntrinsicPredicates.java +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/test/hotspot/jtreg/compiler/runtime/TestConstantsInError.java b/test/hotspot/jtreg/compiler/runtime/TestConstantsInError.java +--- a/test/hotspot/jtreg/compiler/runtime/TestConstantsInError.java 2024-01-10 05:18:15.000000000 +0800 ++++ b/test/hotspot/jtreg/compiler/runtime/TestConstantsInError.java 2024-01-31 14:01:13.350778841 +0800 +@@ -22,6 +22,12 @@ + */ + + /* ++ * This file has been modified by Loongson Technology in 2022. These ++ * modifications are Copyright (c) 2022 Loongson Technology, and are made ++ * available on the same license terms set forth above. ++ */ ++ ++/* + * @test + * @bug 8279822 + * @requires vm.flagless +@@ -130,7 +136,7 @@ + results.shouldMatch("Test_C1/.*::test \\(3 bytes\\)$") + .shouldMatch("Test_C2/.*::test \\(3 bytes\\)$"); + +- if (isC1 && (Platform.isAArch64() || Platform.isRISCV64())) { // no code patching ++ if (isC1 && (Platform.isAArch64() || Platform.isRISCV64() || Platform.isLoongArch64())) { // no code patching + results.shouldMatch("Test_C1/.*::test \\(3 bytes\\) made not entrant") + .shouldMatch("Test_C2/.*::test \\(3 bytes\\) made not entrant"); + } else { +@@ -168,7 +174,7 @@ + .shouldMatch("Test_MH3/.*::test \\(3 bytes\\)$") + .shouldMatch("Test_MH4/.*::test \\(3 bytes\\)$"); + +- if (isC1 && (Platform.isAArch64() || Platform.isRISCV64())) { // no code patching ++ if (isC1 && (Platform.isAArch64() || Platform.isRISCV64() || Platform.isLoongArch64())) { // no code patching + results.shouldMatch("Test_MH1/.*::test \\(3 bytes\\) made not entrant") + .shouldMatch("Test_MH2/.*::test \\(3 bytes\\) made not entrant") + .shouldMatch("Test_MH3/.*::test \\(3 bytes\\) made not entrant") +@@ -191,7 +197,7 @@ + results.shouldMatch("Test_MT1/.*::test \\(3 bytes\\)$") + .shouldMatch("Test_MT2/.*::test \\(3 bytes\\)$"); + +- if (isC1 && (Platform.isAArch64() || Platform.isRISCV64())) { // no code patching ++ if (isC1 && (Platform.isAArch64() || Platform.isRISCV64() || Platform.isLoongArch64())) { // no code patching + results.shouldMatch("Test_MT1/.*::test \\(3 bytes\\) made not entrant") + .shouldMatch("Test_MT2/.*::test \\(3 bytes\\) made not entrant"); + } else { +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/test/hotspot/jtreg/compiler/testlibrary/sha/predicate/IntrinsicPredicates.java b/test/hotspot/jtreg/compiler/testlibrary/sha/predicate/IntrinsicPredicates.java +--- a/test/hotspot/jtreg/compiler/testlibrary/sha/predicate/IntrinsicPredicates.java 2024-01-10 05:18:15.000000000 +0800 ++++ b/test/hotspot/jtreg/compiler/testlibrary/sha/predicate/IntrinsicPredicates.java 2024-01-31 14:01:13.354112205 +0800 @@ -21,6 +21,12 @@ * questions. */ @@ -122818,7 +121066,7 @@ index 782ab6b9b46..8b859a92d8a 100644 package compiler.testlibrary.sha.predicate; import jdk.test.lib.Platform; -@@ -61,30 +67,35 @@ public class IntrinsicPredicates { +@@ -61,19 +67,22 @@ public static final BooleanSupplier MD5_INSTRUCTION_AVAILABLE = new OrPredicate(new CPUSpecificPredicate("aarch64.*", null, null), @@ -122831,17 +121079,19 @@ index 782ab6b9b46..8b859a92d8a 100644 public static final BooleanSupplier SHA1_INSTRUCTION_AVAILABLE = new OrPredicate(new CPUSpecificPredicate("aarch64.*", new String[] { "sha1" }, null), + new OrPredicate(new CPUSpecificPredicate("riscv64.*", new String[] { "sha1" }, null), new OrPredicate(new CPUSpecificPredicate("s390.*", new String[] { "sha1" }, null), + // Basic instructions are used to implement SHA1 Intrinsics on LA, so "sha1" feature is not needed. + new OrPredicate(new CPUSpecificPredicate("loongarch64.*", null, null), // x86 variants new OrPredicate(new CPUSpecificPredicate("amd64.*", new String[] { "sha" }, null), new OrPredicate(new CPUSpecificPredicate("i386.*", new String[] { "sha" }, null), -- new CPUSpecificPredicate("x86.*", new String[] { "sha" }, null))))); -+ new CPUSpecificPredicate("x86.*", new String[] { "sha" }, null)))))); +- new CPUSpecificPredicate("x86.*", new String[] { "sha" }, null)))))); ++ new CPUSpecificPredicate("x86.*", new String[] { "sha" }, null))))))); public static final BooleanSupplier SHA256_INSTRUCTION_AVAILABLE = new OrPredicate(new CPUSpecificPredicate("aarch64.*", new String[] { "sha256" }, null), +@@ -81,12 +90,14 @@ new OrPredicate(new CPUSpecificPredicate("s390.*", new String[] { "sha256" }, null), new OrPredicate(new CPUSpecificPredicate("ppc64.*", new String[] { "sha" }, null), new OrPredicate(new CPUSpecificPredicate("ppc64le.*", new String[] { "sha" }, null), @@ -122852,41 +121102,40 @@ index 782ab6b9b46..8b859a92d8a 100644 new OrPredicate(new CPUSpecificPredicate("i386.*", new String[] { "sha" }, null), new OrPredicate(new CPUSpecificPredicate("x86.*", new String[] { "sha" }, null), new OrPredicate(new CPUSpecificPredicate("amd64.*", new String[] { "avx2", "bmi2" }, null), -- new CPUSpecificPredicate("x86_64", new String[] { "avx2", "bmi2" }, null))))))))); -+ new CPUSpecificPredicate("x86_64", new String[] { "avx2", "bmi2" }, null)))))))))); +- new CPUSpecificPredicate("x86_64", new String[] { "avx2", "bmi2" }, null)))))))))); ++ new CPUSpecificPredicate("x86_64", new String[] { "avx2", "bmi2" }, null))))))))))); public static final BooleanSupplier SHA512_INSTRUCTION_AVAILABLE = new OrPredicate(new CPUSpecificPredicate("aarch64.*", new String[] { "sha512" }, null), -diff --git a/test/hotspot/jtreg/runtime/ReservedStack/ReservedStackTest.java b/test/hotspot/jtreg/runtime/ReservedStack/ReservedStackTest.java -index c11472a0918..bf933f04957 100644 ---- a/test/hotspot/jtreg/runtime/ReservedStack/ReservedStackTest.java -+++ b/test/hotspot/jtreg/runtime/ReservedStack/ReservedStackTest.java -@@ -21,6 +21,12 @@ - * questions. +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/test/hotspot/jtreg/runtime/ReservedStack/ReservedStackTest.java b/test/hotspot/jtreg/runtime/ReservedStack/ReservedStackTest.java +--- a/test/hotspot/jtreg/runtime/ReservedStack/ReservedStackTest.java 2024-01-10 05:18:15.000000000 +0800 ++++ b/test/hotspot/jtreg/runtime/ReservedStack/ReservedStackTest.java 2024-01-31 14:01:13.407446045 +0800 +@@ -22,6 +22,12 @@ */ -+/* + /* + * This file has been modified by Loongson Technology in 2021, These + * modifications are Copyright (c) 2021, Loongson Technology, and are made + * available on the same license terms set forth above. + */ + - /* ++/* * @test ReservedStackTest * -@@ -240,7 +246,7 @@ public class ReservedStackTest { + * @requires vm.opt.DeoptimizeALot != true +@@ -240,7 +246,8 @@ return Platform.isAix() || (Platform.isLinux() && (Platform.isPPC() || Platform.isS390x() || Platform.isX64() || -- Platform.isX86() || Platform.isAArch64())) || -+ Platform.isX86() || Platform.isAArch64() || Platform.isMIPS() || Platform.isLoongArch64())) || +- Platform.isX86() || Platform.isAArch64() || Platform.isRISCV64())) || ++ Platform.isX86() || Platform.isAArch64() || Platform.isRISCV64() || ++ Platform.isMIPS() || Platform.isLoongArch64())) || Platform.isOSX(); } -diff --git a/test/hotspot/jtreg/testlibrary_tests/ir_framework/tests/TestIRMatching.java b/test/hotspot/jtreg/testlibrary_tests/ir_framework/tests/TestIRMatching.java -index 7e2ef559559..fee901db2ff 100644 ---- a/test/hotspot/jtreg/testlibrary_tests/ir_framework/tests/TestIRMatching.java -+++ b/test/hotspot/jtreg/testlibrary_tests/ir_framework/tests/TestIRMatching.java +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/test/hotspot/jtreg/testlibrary_tests/ir_framework/tests/TestIRMatching.java b/test/hotspot/jtreg/testlibrary_tests/ir_framework/tests/TestIRMatching.java +--- a/test/hotspot/jtreg/testlibrary_tests/ir_framework/tests/TestIRMatching.java 2024-01-10 05:18:15.000000000 +0800 ++++ b/test/hotspot/jtreg/testlibrary_tests/ir_framework/tests/TestIRMatching.java 2024-01-31 14:01:13.490780166 +0800 @@ -21,6 +21,12 @@ * questions. */ @@ -122900,7 +121149,7 @@ index 7e2ef559559..fee901db2ff 100644 package ir_framework.tests; import compiler.lib.ir_framework.*; -@@ -215,7 +221,7 @@ public class TestIRMatching { +@@ -215,7 +221,7 @@ runCheck(BadFailOnConstraint.create(Membar.class, "membar()", 1, "MemBar")); String cmp; @@ -122909,10 +121158,237 @@ index 7e2ef559559..fee901db2ff 100644 cmp = "CMP"; } else if (Platform.isS390x()){ cmp = "CLFI"; -diff --git a/test/jdk/jdk/jfr/event/os/TestCPUInformation.java b/test/jdk/jdk/jfr/event/os/TestCPUInformation.java -index a4b5169ca4a..ae739a92f28 100644 ---- a/test/jdk/jdk/jfr/event/os/TestCPUInformation.java -+++ b/test/jdk/jdk/jfr/event/os/TestCPUInformation.java +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/test/hotspot/jtreg/vmTestbase/nsk/share/jdi/ArgumentHandler.java b/test/hotspot/jtreg/vmTestbase/nsk/share/jdi/ArgumentHandler.java +--- a/test/hotspot/jtreg/vmTestbase/nsk/share/jdi/ArgumentHandler.java 2024-01-10 05:18:15.000000000 +0800 ++++ b/test/hotspot/jtreg/vmTestbase/nsk/share/jdi/ArgumentHandler.java 2024-01-31 14:01:14.454122624 +0800 +@@ -21,6 +21,12 @@ + * questions. + */ + ++/* ++ * This file has been modified by Loongson Technology in 2022, These ++ * modifications are Copyright (c) 2022, Loongson Technology, and are made ++ * available on the same license terms set forth above. ++ */ ++ + package nsk.share.jdi; + + import nsk.share.*; +@@ -520,21 +526,22 @@ + * available only on the Microsoft Windows platform. + * " + */ +- {"linux-i586", "com.sun.jdi.SharedMemoryAttach"}, +- {"linux-ia64", "com.sun.jdi.SharedMemoryAttach"}, +- {"linux-amd64", "com.sun.jdi.SharedMemoryAttach"}, +- {"linux-x64", "com.sun.jdi.SharedMemoryAttach"}, +- {"linux-aarch64", "com.sun.jdi.SharedMemoryAttach"}, +- {"linux-arm", "com.sun.jdi.SharedMemoryAttach"}, +- {"linux-ppc64", "com.sun.jdi.SharedMemoryAttach"}, +- {"linux-ppc64le", "com.sun.jdi.SharedMemoryAttach"}, +- {"linux-s390x", "com.sun.jdi.SharedMemoryAttach"}, +- {"linux-riscv64", "com.sun.jdi.SharedMemoryAttach"}, +- {"macosx-amd64", "com.sun.jdi.SharedMemoryAttach"}, +- {"mac-x64", "com.sun.jdi.SharedMemoryAttach"}, +- {"macosx-aarch64", "com.sun.jdi.SharedMemoryAttach"}, +- {"mac-aarch64", "com.sun.jdi.SharedMemoryAttach"}, +- {"aix-ppc64", "com.sun.jdi.SharedMemoryAttach"}, ++ {"linux-i586", "com.sun.jdi.SharedMemoryAttach"}, ++ {"linux-ia64", "com.sun.jdi.SharedMemoryAttach"}, ++ {"linux-amd64", "com.sun.jdi.SharedMemoryAttach"}, ++ {"linux-x64", "com.sun.jdi.SharedMemoryAttach"}, ++ {"linux-aarch64", "com.sun.jdi.SharedMemoryAttach"}, ++ {"linux-arm", "com.sun.jdi.SharedMemoryAttach"}, ++ {"linux-ppc64", "com.sun.jdi.SharedMemoryAttach"}, ++ {"linux-ppc64le", "com.sun.jdi.SharedMemoryAttach"}, ++ {"linux-s390x", "com.sun.jdi.SharedMemoryAttach"}, ++ {"linux-riscv64", "com.sun.jdi.SharedMemoryAttach"}, ++ {"linux-loongarch64", "com.sun.jdi.SharedMemoryAttach"}, ++ {"macosx-amd64", "com.sun.jdi.SharedMemoryAttach"}, ++ {"mac-x64", "com.sun.jdi.SharedMemoryAttach"}, ++ {"macosx-aarch64", "com.sun.jdi.SharedMemoryAttach"}, ++ {"mac-aarch64", "com.sun.jdi.SharedMemoryAttach"}, ++ {"aix-ppc64", "com.sun.jdi.SharedMemoryAttach"}, + + // listening connectors + /* +@@ -546,21 +553,22 @@ + * It is available only on the Microsoft Windows platform. + * " + */ +- {"linux-i586", "com.sun.jdi.SharedMemoryListen"}, +- {"linux-ia64", "com.sun.jdi.SharedMemoryListen"}, +- {"linux-amd64", "com.sun.jdi.SharedMemoryListen"}, +- {"linux-x64", "com.sun.jdi.SharedMemoryListen"}, +- {"linux-aarch64", "com.sun.jdi.SharedMemoryListen"}, +- {"linux-arm", "com.sun.jdi.SharedMemoryListen"}, +- {"linux-ppc64", "com.sun.jdi.SharedMemoryListen"}, +- {"linux-ppc64le", "com.sun.jdi.SharedMemoryListen"}, +- {"linux-s390x", "com.sun.jdi.SharedMemoryListen"}, +- {"linux-riscv64", "com.sun.jdi.SharedMemoryListen"}, +- {"macosx-amd64", "com.sun.jdi.SharedMemoryListen"}, +- {"mac-x64", "com.sun.jdi.SharedMemoryListen"}, +- {"macosx-aarch64", "com.sun.jdi.SharedMemoryListen"}, +- {"mac-aarch64", "com.sun.jdi.SharedMemoryListen"}, +- {"aix-ppc64", "com.sun.jdi.SharedMemoryListen"}, ++ {"linux-i586", "com.sun.jdi.SharedMemoryListen"}, ++ {"linux-ia64", "com.sun.jdi.SharedMemoryListen"}, ++ {"linux-amd64", "com.sun.jdi.SharedMemoryListen"}, ++ {"linux-x64", "com.sun.jdi.SharedMemoryListen"}, ++ {"linux-aarch64", "com.sun.jdi.SharedMemoryListen"}, ++ {"linux-arm", "com.sun.jdi.SharedMemoryListen"}, ++ {"linux-ppc64", "com.sun.jdi.SharedMemoryListen"}, ++ {"linux-ppc64le", "com.sun.jdi.SharedMemoryListen"}, ++ {"linux-s390x", "com.sun.jdi.SharedMemoryListen"}, ++ {"linux-riscv64", "com.sun.jdi.SharedMemoryListen"}, ++ {"linux-loongarch64", "com.sun.jdi.SharedMemoryListen"}, ++ {"macosx-amd64", "com.sun.jdi.SharedMemoryListen"}, ++ {"mac-x64", "com.sun.jdi.SharedMemoryListen"}, ++ {"macosx-aarch64", "com.sun.jdi.SharedMemoryListen"}, ++ {"mac-aarch64", "com.sun.jdi.SharedMemoryListen"}, ++ {"aix-ppc64", "com.sun.jdi.SharedMemoryListen"}, + + // launching connectors + /* +@@ -575,78 +583,82 @@ + * Windows, the shared memory transport is used. On Linux the socket transport is used. + * " + */ +- {"linux-i586", "com.sun.jdi.CommandLineLaunch", "dt_shmem"}, +- {"linux-i586", "com.sun.jdi.RawCommandLineLaunch", "dt_shmem"}, ++ {"linux-i586", "com.sun.jdi.CommandLineLaunch", "dt_shmem"}, ++ {"linux-i586", "com.sun.jdi.RawCommandLineLaunch", "dt_shmem"}, ++ ++ {"linux-ia64", "com.sun.jdi.CommandLineLaunch", "dt_shmem"}, ++ {"linux-ia64", "com.sun.jdi.RawCommandLineLaunch", "dt_shmem"}, + +- {"linux-ia64", "com.sun.jdi.CommandLineLaunch", "dt_shmem"}, +- {"linux-ia64", "com.sun.jdi.RawCommandLineLaunch", "dt_shmem"}, ++ {"linux-amd64", "com.sun.jdi.CommandLineLaunch", "dt_shmem"}, ++ {"linux-amd64", "com.sun.jdi.RawCommandLineLaunch", "dt_shmem"}, + +- {"linux-amd64", "com.sun.jdi.CommandLineLaunch", "dt_shmem"}, +- {"linux-amd64", "com.sun.jdi.RawCommandLineLaunch", "dt_shmem"}, ++ {"linux-x64", "com.sun.jdi.CommandLineLaunch", "dt_shmem"}, ++ {"linux-x64", "com.sun.jdi.RawCommandLineLaunch", "dt_shmem"}, + +- {"linux-x64", "com.sun.jdi.CommandLineLaunch", "dt_shmem"}, +- {"linux-x64", "com.sun.jdi.RawCommandLineLaunch", "dt_shmem"}, ++ {"linux-aarch64", "com.sun.jdi.CommandLineLaunch", "dt_shmem"}, ++ {"linux-aarch64", "com.sun.jdi.RawCommandLineLaunch", "dt_shmem"}, + +- {"linux-aarch64", "com.sun.jdi.CommandLineLaunch", "dt_shmem"}, +- {"linux-aarch64", "com.sun.jdi.RawCommandLineLaunch", "dt_shmem"}, ++ {"linux-arm", "com.sun.jdi.CommandLineLaunch", "dt_shmem"}, ++ {"linux-arm", "com.sun.jdi.RawCommandLineLaunch", "dt_shmem"}, + +- {"linux-arm", "com.sun.jdi.CommandLineLaunch", "dt_shmem"}, +- {"linux-arm", "com.sun.jdi.RawCommandLineLaunch", "dt_shmem"}, ++ {"linux-ppc64", "com.sun.jdi.CommandLineLaunch", "dt_shmem"}, ++ {"linux-ppc64", "com.sun.jdi.RawCommandLineLaunch", "dt_shmem"}, + +- {"linux-ppc64", "com.sun.jdi.CommandLineLaunch", "dt_shmem"}, +- {"linux-ppc64", "com.sun.jdi.RawCommandLineLaunch", "dt_shmem"}, ++ {"linux-ppc64le", "com.sun.jdi.CommandLineLaunch", "dt_shmem"}, ++ {"linux-ppc64le", "com.sun.jdi.RawCommandLineLaunch", "dt_shmem"}, + +- {"linux-ppc64le", "com.sun.jdi.CommandLineLaunch", "dt_shmem"}, +- {"linux-ppc64le", "com.sun.jdi.RawCommandLineLaunch", "dt_shmem"}, ++ {"linux-s390x", "com.sun.jdi.CommandLineLaunch", "dt_shmem"}, ++ {"linux-s390x", "com.sun.jdi.RawCommandLineLaunch", "dt_shmem"}, + +- {"linux-s390x", "com.sun.jdi.CommandLineLaunch", "dt_shmem"}, +- {"linux-s390x", "com.sun.jdi.RawCommandLineLaunch", "dt_shmem"}, ++ {"linux-riscv64", "com.sun.jdi.CommandLineLaunch", "dt_shmem"}, ++ {"linux-riscv64", "com.sun.jdi.RawCommandLineLaunch", "dt_shmem"}, + +- {"linux-riscv64", "com.sun.jdi.CommandLineLaunch", "dt_shmem"}, +- {"linux-riscv64", "com.sun.jdi.RawCommandLineLaunch", "dt_shmem"}, ++ {"linux-loongarch64", "com.sun.jdi.CommandLineLaunch", "dt_shmem"}, ++ {"linux-loongarch64", "com.sun.jdi.RawCommandLineLaunch", "dt_shmem"}, + +- {"windows-i586", "com.sun.jdi.CommandLineLaunch", "dt_socket"}, +- {"windows-i586", "com.sun.jdi.RawCommandLineLaunch", "dt_socket"}, ++ {"windows-i586", "com.sun.jdi.CommandLineLaunch", "dt_socket"}, ++ {"windows-i586", "com.sun.jdi.RawCommandLineLaunch", "dt_socket"}, + +- {"windows-ia64", "com.sun.jdi.CommandLineLaunch", "dt_socket"}, +- {"windows-ia64", "com.sun.jdi.RawCommandLineLaunch", "dt_socket"}, ++ {"windows-ia64", "com.sun.jdi.CommandLineLaunch", "dt_socket"}, ++ {"windows-ia64", "com.sun.jdi.RawCommandLineLaunch", "dt_socket"}, + +- {"windows-amd64", "com.sun.jdi.CommandLineLaunch", "dt_socket"}, +- {"windows-amd64", "com.sun.jdi.RawCommandLineLaunch", "dt_socket"}, ++ {"windows-amd64", "com.sun.jdi.CommandLineLaunch", "dt_socket"}, ++ {"windows-amd64", "com.sun.jdi.RawCommandLineLaunch", "dt_socket"}, + +- {"windows-x64", "com.sun.jdi.CommandLineLaunch", "dt_socket"}, +- {"windows-x64", "com.sun.jdi.RawCommandLineLaunch", "dt_socket"}, ++ {"windows-x64", "com.sun.jdi.CommandLineLaunch", "dt_socket"}, ++ {"windows-x64", "com.sun.jdi.RawCommandLineLaunch", "dt_socket"}, + +- {"macosx-amd64", "com.sun.jdi.CommandLineLaunch", "dt_shmem"}, +- {"macosx-amd64", "com.sun.jdi.RawCommandLineLaunch", "dt_shmem"}, ++ {"macosx-amd64", "com.sun.jdi.CommandLineLaunch", "dt_shmem"}, ++ {"macosx-amd64", "com.sun.jdi.RawCommandLineLaunch", "dt_shmem"}, + +- {"mac-x64", "com.sun.jdi.CommandLineLaunch", "dt_shmem"}, +- {"mac-x64", "com.sun.jdi.RawCommandLineLaunch", "dt_shmem"}, ++ {"mac-x64", "com.sun.jdi.CommandLineLaunch", "dt_shmem"}, ++ {"mac-x64", "com.sun.jdi.RawCommandLineLaunch", "dt_shmem"}, + +- {"macosx-aarch64", "com.sun.jdi.CommandLineLaunch", "dt_shmem"}, +- {"macosx-aarch64", "com.sun.jdi.RawCommandLineLaunch", "dt_shmem"}, ++ {"macosx-aarch64", "com.sun.jdi.CommandLineLaunch", "dt_shmem"}, ++ {"macosx-aarch64", "com.sun.jdi.RawCommandLineLaunch", "dt_shmem"}, + +- {"mac-aarch64", "com.sun.jdi.CommandLineLaunch", "dt_shmem"}, +- {"mac-aarch64", "com.sun.jdi.RawCommandLineLaunch", "dt_shmem"}, ++ {"mac-aarch64", "com.sun.jdi.CommandLineLaunch", "dt_shmem"}, ++ {"mac-aarch64", "com.sun.jdi.RawCommandLineLaunch", "dt_shmem"}, + +- {"aix-ppc64", "com.sun.jdi.CommandLineLaunch", "dt_shmem"}, +- {"aix-ppc64", "com.sun.jdi.RawCommandLineLaunch", "dt_shmem"}, ++ {"aix-ppc64", "com.sun.jdi.CommandLineLaunch", "dt_shmem"}, ++ {"aix-ppc64", "com.sun.jdi.RawCommandLineLaunch", "dt_shmem"}, + + // shared memory transport is implemented only on windows platform +- {"linux-i586", "dt_shmem"}, +- {"linux-ia64", "dt_shmem"}, +- {"linux-amd64", "dt_shmem"}, +- {"linux-x64", "dt_shmem"}, +- {"linux-aarch64", "dt_shmem"}, +- {"linux-arm", "dt_shmem"}, +- {"linux-ppc64", "dt_shmem"}, +- {"linux-ppc64le", "dt_shmem"}, +- {"linux-s390x", "dt_shmem"}, +- {"linux-riscv64", "dt_shmem"}, +- {"macosx-amd64", "dt_shmem"}, +- {"mac-x64", "dt_shmem"}, +- {"macosx-aarch64", "dt_shmem"}, +- {"mac-aarch64", "dt_shmem"}, +- {"aix-ppc64", "dt_shmem"}, ++ {"linux-i586", "dt_shmem"}, ++ {"linux-ia64", "dt_shmem"}, ++ {"linux-amd64", "dt_shmem"}, ++ {"linux-x64", "dt_shmem"}, ++ {"linux-aarch64", "dt_shmem"}, ++ {"linux-arm", "dt_shmem"}, ++ {"linux-ppc64", "dt_shmem"}, ++ {"linux-ppc64le", "dt_shmem"}, ++ {"linux-s390x", "dt_shmem"}, ++ {"linux-riscv64", "dt_shmem"}, ++ {"linux-loongarch64", "dt_shmem"}, ++ {"macosx-amd64", "dt_shmem"}, ++ {"mac-x64", "dt_shmem"}, ++ {"macosx-aarch64", "dt_shmem"}, ++ {"mac-aarch64", "dt_shmem"}, ++ {"aix-ppc64", "dt_shmem"}, + }; + } +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/test/jdk/jdk/jfr/event/os/TestCPUInformation.java b/test/jdk/jdk/jfr/event/os/TestCPUInformation.java +--- a/test/jdk/jdk/jfr/event/os/TestCPUInformation.java 2024-01-10 05:18:15.000000000 +0800 ++++ b/test/jdk/jdk/jfr/event/os/TestCPUInformation.java 2024-01-31 14:01:15.310797381 +0800 @@ -21,6 +21,12 @@ * questions. */ @@ -122926,21 +121402,20 @@ index a4b5169ca4a..ae739a92f28 100644 package jdk.jfr.event.os; import java.util.List; -@@ -52,8 +58,8 @@ public class TestCPUInformation { +@@ -52,8 +58,8 @@ Events.assertField(event, "hwThreads").atLeast(1); Events.assertField(event, "cores").atLeast(1); Events.assertField(event, "sockets").atLeast(1); -- Events.assertField(event, "cpu").containsAny("Intel", "AMD", "Unknown x86", "ARM", "PPC", "PowerPC", "AArch64", "s390"); -- Events.assertField(event, "description").containsAny("Intel", "AMD", "Unknown x86", "ARM", "PPC", "PowerPC", "AArch64", "s390"); -+ Events.assertField(event, "cpu").containsAny("Intel", "AMD", "Unknown x86", "ARM", "PPC", "PowerPC", "AArch64", "s390", "MIPS", "LoongArch"); -+ Events.assertField(event, "description").containsAny("Intel", "AMD", "Unknown x86", "ARM", "PPC", "PowerPC", "AArch64", "s390", "MIPS", "LoongArch"); +- Events.assertField(event, "cpu").containsAny("Intel", "AMD", "Unknown x86", "ARM", "PPC", "PowerPC", "AArch64", "RISCV64", "s390"); +- Events.assertField(event, "description").containsAny("Intel", "AMD", "Unknown x86", "ARM", "PPC", "PowerPC", "AArch64", "RISCV64", "s390"); ++ Events.assertField(event, "cpu").containsAny("Intel", "AMD", "Unknown x86", "ARM", "PPC", "PowerPC", "AArch64", "RISCV64", "s390", "MIPS", "LoongArch"); ++ Events.assertField(event, "description").containsAny("Intel", "AMD", "Unknown x86", "ARM", "PPC", "PowerPC", "AArch64", "RISCV64", "s390", "MIPS", "LoongArch"); } } } -diff --git a/test/jdk/sun/security/pkcs11/PKCS11Test.java b/test/jdk/sun/security/pkcs11/PKCS11Test.java -index a9a8a8178ee..99295d779c5 100644 ---- a/test/jdk/sun/security/pkcs11/PKCS11Test.java -+++ b/test/jdk/sun/security/pkcs11/PKCS11Test.java +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/test/jdk/sun/security/pkcs11/PKCS11Test.java b/test/jdk/sun/security/pkcs11/PKCS11Test.java +--- a/test/jdk/sun/security/pkcs11/PKCS11Test.java 2024-01-10 05:18:15.000000000 +0800 ++++ b/test/jdk/sun/security/pkcs11/PKCS11Test.java 2024-01-31 14:01:15.500799172 +0800 @@ -21,6 +21,12 @@ * questions. */ @@ -122954,7 +121429,7 @@ index a9a8a8178ee..99295d779c5 100644 // common infrastructure for SunPKCS11 tests import java.io.ByteArrayOutputStream; -@@ -693,6 +699,9 @@ public abstract class PKCS11Test { +@@ -693,6 +699,9 @@ "/usr/lib64/" }); osMap.put("Linux-ppc64-64", new String[] { "/usr/lib64/" }); osMap.put("Linux-ppc64le-64", new String[] { "/usr/lib64/" }); @@ -122964,36 +121439,9 @@ index a9a8a8178ee..99295d779c5 100644 osMap.put("Linux-s390x-64", new String[] { "/usr/lib64/" }); osMap.put("Windows-x86-32", new String[] {}); osMap.put("Windows-amd64-64", new String[] {}); -diff --git a/test/lib-test/jdk/test/lib/TestMutuallyExclusivePlatformPredicates.java b/test/lib-test/jdk/test/lib/TestMutuallyExclusivePlatformPredicates.java -index 4be69a6566c..d5b5b3adfa4 100644 ---- a/test/lib-test/jdk/test/lib/TestMutuallyExclusivePlatformPredicates.java -+++ b/test/lib-test/jdk/test/lib/TestMutuallyExclusivePlatformPredicates.java -@@ -33,6 +33,12 @@ import java.util.HashSet; - import java.util.List; - import java.util.Set; - -+/* -+ * This file has been modified by Loongson Technology in 2021, These -+ * modifications are Copyright (c) 2021, Loongson Technology, and are made -+ * available on the same license terms set forth above. -+ */ -+ - /** - * @test - * @summary Verify that for each group of mutually exclusive predicates defined -@@ -45,7 +51,7 @@ import java.util.Set; - */ - public class TestMutuallyExclusivePlatformPredicates { - private static enum MethodGroup { -- ARCH("isAArch64", "isARM", "isPPC", "isS390x", "isX64", "isX86"), -+ ARCH("isAArch64", "isARM", "isPPC", "isS390x", "isX64", "isX86", "isMIPS", "isLoongArch64"), - BITNESS("is32bit", "is64bit"), - OS("isAix", "isLinux", "isOSX", "isWindows"), - VM_TYPE("isClient", "isServer", "isMinimal", "isZero", "isEmbedded"), -diff --git a/test/lib/jdk/test/lib/Platform.java b/test/lib/jdk/test/lib/Platform.java -index 952c02270e5..ef98ee74a48 100644 ---- a/test/lib/jdk/test/lib/Platform.java -+++ b/test/lib/jdk/test/lib/Platform.java +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/test/lib/jdk/test/lib/Platform.java b/test/lib/jdk/test/lib/Platform.java +--- a/test/lib/jdk/test/lib/Platform.java 2024-01-10 05:18:15.000000000 +0800 ++++ b/test/lib/jdk/test/lib/Platform.java 2024-01-31 14:01:16.430807926 +0800 @@ -21,6 +21,12 @@ * questions. */ @@ -123006,8 +121454,8 @@ index 952c02270e5..ef98ee74a48 100644 + package jdk.test.lib; - import java.io.FileNotFoundException; -@@ -214,6 +220,14 @@ public class Platform { + import java.io.BufferedReader; +@@ -233,6 +239,14 @@ return isArch("(i386)|(x86(?!_64))"); } @@ -123022,3 +121470,28 @@ index 952c02270e5..ef98ee74a48 100644 public static String getOsArch() { return osArch; } +diff -Naur -x .git -x .github -x .gitattributes -x .gitignore -x .jcheck a/test/lib-test/jdk/test/lib/TestMutuallyExclusivePlatformPredicates.java b/test/lib-test/jdk/test/lib/TestMutuallyExclusivePlatformPredicates.java +--- a/test/lib-test/jdk/test/lib/TestMutuallyExclusivePlatformPredicates.java 2024-01-10 05:18:15.000000000 +0800 ++++ b/test/lib-test/jdk/test/lib/TestMutuallyExclusivePlatformPredicates.java 2024-01-31 14:01:16.427474562 +0800 +@@ -33,6 +33,12 @@ + import java.util.List; + import java.util.Set; + ++/* ++ * This file has been modified by Loongson Technology in 2021, These ++ * modifications are Copyright (c) 2021, Loongson Technology, and are made ++ * available on the same license terms set forth above. ++ */ ++ + /** + * @test + * @summary Verify that for each group of mutually exclusive predicates defined +@@ -45,7 +51,7 @@ + */ + public class TestMutuallyExclusivePlatformPredicates { + private static enum MethodGroup { +- ARCH("isAArch64", "isARM", "isRISCV64", "isPPC", "isS390x", "isX64", "isX86"), ++ ARCH("isAArch64", "isARM", "isRISCV64", "isPPC", "isS390x", "isX64", "isX86", "isMIPS", "isLoongArch64"), + BITNESS("is32bit", "is64bit"), + OS("isAix", "isLinux", "isOSX", "isWindows"), + VM_TYPE("isClient", "isServer", "isMinimal", "isZero", "isEmbedded"), diff --git a/openjdk-17.spec b/openjdk-17.spec index 6672c588e7ed0bff8ebf9d2539cdc939bbb2d23c..110327948547e71a7648d4491955341ae45d9813 100644 --- a/openjdk-17.spec +++ b/openjdk-17.spec @@ -893,7 +893,7 @@ Provides: java-src%{?1} = %{epoch}:%{version}-%{release} Name: java-%{javaver}-%{origin} Version: %{newjavaver}.%{buildver} -Release: 0 +Release: 1 # java-1.5.0-ibm from jpackage.org set Epoch to 1 for unknown reasons # and this change was brought into RHEL-4. java-1.5.0-ibm packages @@ -1831,6 +1831,9 @@ cjc.mainProgram(arg) %changelog +* Mon Feb 19 2024 Leslie Zhai - 1:17.0.10.9-1 +- Rebase LoongArch64 patch + * Thu Jan 18 2024 neu-mobi - 1:17.0.10.9-0.rolling - del 8168469-Memory-leak-in-JceSecurity.patch - del 8275509-ModuleDescriptor.hashCode-isn-t-rep.patch