diff --git a/Backport-JDK-8347981-RISC-V-implement-Add-Zfa-zli-imm-loads.patch b/Backport-JDK-8347981-RISC-V-implement-Add-Zfa-zli-imm-loads.patch new file mode 100644 index 0000000000000000000000000000000000000000..cc46f5362c5ee3b0132bcec3c6cdbea20dbf6eb1 --- /dev/null +++ b/Backport-JDK-8347981-RISC-V-implement-Add-Zfa-zli-imm-loads.patch @@ -0,0 +1,312 @@ +commit b41700856257905ccc95ae04ea874346ef3905fb +Author: 张泽建10053720 +Date: Thu Oct 16 15:00:52 2025 +0800 + + Backport 8347981: RISC-V: Add Zfa zli imm loads + +diff --git a/src/hotspot/cpu/riscv/assembler_riscv.hpp b/src/hotspot/cpu/riscv/assembler_riscv.hpp +index 24de7c15f..334044770 100644 +--- a/src/hotspot/cpu/riscv/assembler_riscv.hpp ++++ b/src/hotspot/cpu/riscv/assembler_riscv.hpp +@@ -323,7 +323,101 @@ class InternalAddress: public Address { + }; + + class Assembler : public AbstractAssembler { ++protected: ++ static int zfa_zli_lookup_double(uint64_t value) { ++ switch(value) { ++ case 0xbff0000000000000 : return 0; ++ case 0x0010000000000000 : return 1; ++ case 0x3ef0000000000000 : return 2; ++ case 0x3f00000000000000 : return 3; ++ case 0x3f70000000000000 : return 4; ++ case 0x3f80000000000000 : return 5; ++ case 0x3fb0000000000000 : return 6; ++ case 0x3fc0000000000000 : return 7; ++ case 0x3fd0000000000000 : return 8; ++ case 0x3fd4000000000000 : return 9; ++ case 0x3fd8000000000000 : return 10; ++ case 0x3fdc000000000000 : return 11; ++ case 0x3fe0000000000000 : return 12; ++ case 0x3fe4000000000000 : return 13; ++ case 0x3fe8000000000000 : return 14; ++ case 0x3fec000000000000 : return 15; ++ case 0x3ff0000000000000 : return 16; ++ case 0x3ff4000000000000 : return 17; ++ case 0x3ff8000000000000 : return 18; ++ case 0x3ffc000000000000 : return 19; ++ case 0x4000000000000000 : return 20; ++ case 0x4004000000000000 : return 21; ++ case 0x4008000000000000 : return 22; ++ case 0x4010000000000000 : return 23; ++ case 0x4020000000000000 : return 24; ++ case 0x4030000000000000 : return 25; ++ case 0x4060000000000000 : return 26; ++ case 0x4070000000000000 : return 27; ++ case 0x40e0000000000000 : return 28; ++ case 0x40f0000000000000 : return 29; ++ case 0x7ff0000000000000 : return 30; ++ case 0x7ff8000000000000 : return 31; ++ default: break; ++ } ++ return -1; ++ } ++ ++ static int zfa_zli_lookup_float(uint32_t value) { ++ switch(value) { ++ case 0xbf800000 : return 0; ++ case 0x00800000 : return 1; ++ case 0x37800000 : return 2; ++ case 0x38000000 : return 3; ++ case 0x3b800000 : return 4; ++ case 0x3c000000 : return 5; ++ case 0x3d800000 : return 6; ++ case 0x3e000000 : return 7; ++ case 0x3e800000 : return 8; ++ case 0x3ea00000 : return 9; ++ case 0x3ec00000 : return 10; ++ case 0x3ee00000 : return 11; ++ case 0x3f000000 : return 12; ++ case 0x3f200000 : return 13; ++ case 0x3f400000 : return 14; ++ case 0x3f600000 : return 15; ++ case 0x3f800000 : return 16; ++ case 0x3fa00000 : return 17; ++ case 0x3fc00000 : return 18; ++ case 0x3fe00000 : return 19; ++ case 0x40000000 : return 20; ++ case 0x40200000 : return 21; ++ case 0x40400000 : return 22; ++ case 0x40800000 : return 23; ++ case 0x41000000 : return 24; ++ case 0x41800000 : return 25; ++ case 0x43000000 : return 26; ++ case 0x43800000 : return 27; ++ case 0x47000000 : return 28; ++ case 0x47800000 : return 29; ++ case 0x7f800000 : return 30; ++ case 0x7fc00000 : return 31; ++ default: break; ++ } ++ return -1; ++ } ++ + public: ++ static bool can_zfa_zli_float(jfloat f) { ++ if (!UseZfa) { ++ return false; ++ } ++ uint32_t f_bits = (uint32_t)jint_cast(f); ++ return zfa_zli_lookup_float(f_bits) != -1; ++ } ++ ++ static bool can_zfa_zli_double(jdouble d) { ++ if (!UseZfa) { ++ return false; ++ } ++ uint64_t d_bits = (uint64_t)julong_cast(d); ++ return zfa_zli_lookup_double(d_bits) != -1; ++ } + + enum { + instruction_size = 4, +@@ -1093,6 +1187,25 @@ enum operand_size { int8, int16, int32, uint32, int64 }; + + #undef INSN + ++// Zfa Instruction Definitions Floating-point Load Immediate ++#define INSN(NAME, op, funct5, funct7) \ ++ void NAME(FloatRegister Rd, uint8_t imm) { \ ++ guarantee(is_uimm5(imm), "Immediate is out of validity"); \ ++ unsigned insn = 0; \ ++ patch((address)&insn, 6, 0, op); \ ++ patch((address)&insn, 14, 12, 0b000); \ ++ patch((address)&insn, 24, 20, funct5); \ ++ patch((address)&insn, 31, 25, funct7); \ ++ patch_reg((address)&insn, 7, Rd); \ ++ patch((address)&insn, 19, 15, imm); \ ++ emit(insn); \ ++ } ++ ++ INSN(_fli_s, 0b1010011, 0b00001, 0b1111000); ++ INSN(_fli_d, 0b1010011, 0b00001, 0b1111001); ++ ++#undef INSN ++ + // ========================== + // RISC-V Vector Extension + // ========================== +diff --git a/src/hotspot/cpu/riscv/c1_LIRAssembler_riscv.cpp b/src/hotspot/cpu/riscv/c1_LIRAssembler_riscv.cpp +index 8e52a6775..df7e2a15a 100644 +--- a/src/hotspot/cpu/riscv/c1_LIRAssembler_riscv.cpp ++++ b/src/hotspot/cpu/riscv/c1_LIRAssembler_riscv.cpp +@@ -446,6 +446,8 @@ void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_cod + assert(dest->is_register(), "should not call otherwise"); + LIR_Const* c = src->as_constant_ptr(); + address const_addr = nullptr; ++ jfloat fconst; ++ jdouble dconst; + + switch (c->type()) { + case T_INT: +@@ -481,15 +483,25 @@ void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_cod + break; + + case T_FLOAT: +- const_addr = float_constant(c->as_jfloat()); +- assert(const_addr != nullptr, "must create float constant in the constant table"); +- __ flw(dest->as_float_reg(), InternalAddress(const_addr)); ++ fconst = c->as_jfloat(); ++ if (MacroAssembler::can_fp_imm_load(fconst)) { ++ __ fli_s(dest->as_float_reg(), fconst); ++ } else { ++ const_addr = float_constant(fconst); ++ assert(const_addr != nullptr, "must create float constant in the constant table"); ++ __ flw(dest->as_float_reg(), InternalAddress(const_addr)); ++ } + break; + + case T_DOUBLE: +- const_addr = double_constant(c->as_jdouble()); +- assert(const_addr != nullptr, "must create double constant in the constant table"); +- __ fld(dest->as_double_reg(), InternalAddress(const_addr)); ++ dconst = c->as_jdouble(); ++ if (MacroAssembler::can_dp_imm_load(dconst)) { ++ __ fli_d(dest->as_double_reg(), dconst); ++ } else { ++ const_addr = double_constant(c->as_jdouble()); ++ assert(const_addr != nullptr, "must create double constant in the constant table"); ++ __ fld(dest->as_double_reg(), InternalAddress(const_addr)); ++ } + break; + + default: +diff --git a/src/hotspot/cpu/riscv/globals_riscv.hpp b/src/hotspot/cpu/riscv/globals_riscv.hpp +index 2ee0b4b94..d22379d0d 100644 +--- a/src/hotspot/cpu/riscv/globals_riscv.hpp ++++ b/src/hotspot/cpu/riscv/globals_riscv.hpp +@@ -106,6 +106,7 @@ define_pd_global(intx, InlineSmallCode, 1000); + product(bool, UseZba, false, DIAGNOSTIC, "Use Zba instructions") \ + product(bool, UseZbb, false, DIAGNOSTIC, "Use Zbb instructions") \ + product(bool, UseZbs, false, DIAGNOSTIC, "Use Zbs instructions") \ ++ product(bool, UseZfa, false, EXPERIMENTAL, "Use Zfa instructions") \ + product(bool, UseZic64b, false, EXPERIMENTAL, "Use Zic64b instructions") \ + product(bool, UseZicbom, false, EXPERIMENTAL, "Use Zicbom instructions") \ + product(bool, UseZicbop, false, EXPERIMENTAL, "Use Zicbop instructions") \ +diff --git a/src/hotspot/cpu/riscv/macroAssembler_riscv.cpp b/src/hotspot/cpu/riscv/macroAssembler_riscv.cpp +index e398d353a..64b0bc1ef 100644 +--- a/src/hotspot/cpu/riscv/macroAssembler_riscv.cpp ++++ b/src/hotspot/cpu/riscv/macroAssembler_riscv.cpp +@@ -1537,6 +1537,45 @@ void MacroAssembler::movptr(Register Rd, address addr, int32_t &offset) { + offset = imm64 & 0x3f; + } + ++// floating point imm move ++bool MacroAssembler::can_fp_imm_load(float imm) { ++ jint f_bits = jint_cast(imm); ++ if (f_bits == 0) { ++ return true; ++ } ++ return can_zfa_zli_float(imm); ++} ++ ++bool MacroAssembler::can_dp_imm_load(double imm) { ++ julong d_bits = julong_cast(imm); ++ if (d_bits == 0) { ++ return true; ++ } ++ return can_zfa_zli_double(imm); ++} ++ ++void MacroAssembler::fli_s(FloatRegister Rd, float imm) { ++ jint f_bits = jint_cast(imm); ++ if (f_bits == 0) { ++ fmv_w_x(Rd, zr); ++ return; ++ } ++ int Rs = zfa_zli_lookup_float(f_bits); ++ assert(Rs != -1, "Must be"); ++ _fli_s(Rd, Rs); ++} ++ ++void MacroAssembler::fli_d(FloatRegister Rd, double imm) { ++ uint64_t d_bits = (uint64_t)julong_cast(imm); ++ if (d_bits == 0) { ++ fmv_d_x(Rd, zr); ++ return; ++ } ++ int Rs = zfa_zli_lookup_double(d_bits); ++ assert(Rs != -1, "Must be"); ++ _fli_d(Rd, Rs); ++} ++ + void MacroAssembler::add(Register Rd, Register Rn, int64_t increment, Register temp) { + if (is_simm12(increment)) { + addi(Rd, Rn, increment); +diff --git a/src/hotspot/cpu/riscv/macroAssembler_riscv.hpp b/src/hotspot/cpu/riscv/macroAssembler_riscv.hpp +index 08c953b2c..752479fa7 100644 +--- a/src/hotspot/cpu/riscv/macroAssembler_riscv.hpp ++++ b/src/hotspot/cpu/riscv/macroAssembler_riscv.hpp +@@ -747,6 +747,12 @@ public: + movptr(Rd, (address)imm64); + } + ++ // float imm move ++ static bool can_fp_imm_load(float imm); ++ static bool can_dp_imm_load(double imm); ++ void fli_s(FloatRegister Rd, float imm); ++ void fli_d(FloatRegister Rd, double imm); ++ + // arith + void add (Register Rd, Register Rn, int64_t increment, Register temp = t0); + void addw(Register Rd, Register Rn, int32_t increment, Register temp = t0); +diff --git a/src/hotspot/cpu/riscv/riscv.ad b/src/hotspot/cpu/riscv/riscv.ad +index d47b3a050..53d3eefb1 100644 +--- a/src/hotspot/cpu/riscv/riscv.ad ++++ b/src/hotspot/cpu/riscv/riscv.ad +@@ -4901,7 +4901,11 @@ instruct loadConF(fRegF dst, immF con) %{ + %} + + ins_encode %{ +- __ flw(as_FloatRegister($dst$$reg), $constantaddress($con)); ++ if (MacroAssembler::can_fp_imm_load($con$$constant)) { ++ __ fli_s(as_FloatRegister($dst$$reg), $con$$constant); ++ } else { ++ __ flw(as_FloatRegister($dst$$reg), $constantaddress($con)); ++ } + %} + + ins_pipe(fp_load_constant_s); +@@ -4931,7 +4935,11 @@ instruct loadConD(fRegD dst, immD con) %{ + %} + + ins_encode %{ +- __ fld(as_FloatRegister($dst$$reg), $constantaddress($con)); ++ if (MacroAssembler::can_dp_imm_load($con$$constant)) { ++ __ fli_d(as_FloatRegister($dst$$reg), $con$$constant); ++ } else { ++ __ fld(as_FloatRegister($dst$$reg), $constantaddress($con)); ++ } + %} + + ins_pipe(fp_load_constant_d); +diff --git a/src/hotspot/cpu/riscv/vm_version_riscv.hpp b/src/hotspot/cpu/riscv/vm_version_riscv.hpp +index 01c5cf0c6..caeae40bd 100644 +--- a/src/hotspot/cpu/riscv/vm_version_riscv.hpp ++++ b/src/hotspot/cpu/riscv/vm_version_riscv.hpp +@@ -140,6 +140,7 @@ class VM_Version : public Abstract_VM_Version { + decl(ext_Zbb , "Zbb" , RV_NO_FLAG_BIT, true , UPDATE_DEFAULT(UseZbb)) \ + decl(ext_Zbc , "Zbc" , RV_NO_FLAG_BIT, true , NO_UPDATE_DEFAULT) \ + decl(ext_Zbs , "Zbs" , RV_NO_FLAG_BIT, true , UPDATE_DEFAULT(UseZbs)) \ ++ decl(ext_Zfa , "Zfa" , RV_NO_FLAG_BIT, true , UPDATE_DEFAULT(UseZfa)) \ + decl(ext_Zicsr , "Zicsr" , RV_NO_FLAG_BIT, true , NO_UPDATE_DEFAULT) \ + decl(ext_Zifencei , "Zifencei" , RV_NO_FLAG_BIT, true , NO_UPDATE_DEFAULT) \ + decl(ext_Zic64b , "Zic64b" , RV_NO_FLAG_BIT, true , UPDATE_DEFAULT(UseZic64b)) \ +@@ -198,6 +199,7 @@ class VM_Version : public Abstract_VM_Version { + RV_ENABLE_EXTENSION(UseZba) \ + RV_ENABLE_EXTENSION(UseZbb) \ + RV_ENABLE_EXTENSION(UseZbs) \ ++ RV_ENABLE_EXTENSION(UseZfa) \ + RV_ENABLE_EXTENSION(UseZic64b) \ + RV_ENABLE_EXTENSION(UseZicbom) \ + RV_ENABLE_EXTENSION(UseZicbop) \ diff --git a/openjdk-21.spec b/openjdk-21.spec index d2261300d3e7e3985efac245381781d5396148cc..3f6d080fbd64d7fcbee1a9f4f49256d133f21b4a 100644 --- a/openjdk-21.spec +++ b/openjdk-21.spec @@ -905,7 +905,7 @@ Name: java-21-%{origin} Version: %{newjavaver}.%{buildver} # This package needs `.rolling` as part of Release so as to not conflict on install with # java-X-openjdk. I.e. when latest rolling release is also an LTS release packaged as -Release: 6 +Release: 7 # java-1.5.0-ibm from jpackage.org set Epoch to 1 for unknown reasons # and this change was brought into RHEL-4. java-1.5.0-ibm packages @@ -1066,6 +1066,7 @@ Patch3011: Backport-JDK-8334999-RISC-V-AES-single-block-cryption-intrinsics.patc Patch3012: Backport-JDK-8315716-RISC-V-implement-ChaCha20-intrinsic.patch Patch3013: Backport-JDK-8316592-RISC-V-implement-poly1305-intrinsic.patch Patch3014: Backport-JDK-8317721-RISC-V-Implement-CRC32-intrinsic.patch +Patch3015: Backport-JDK-8347981-RISC-V-implement-Add-Zfa-zli-imm-loads.patch BuildRequires: autoconf BuildRequires: automake @@ -1375,6 +1376,7 @@ pushd %{top_level_dir_name} %patch3012 -p1 %patch3013 -p1 %patch3014 -p1 +%patch3015 -p1 popd %endif @@ -1932,6 +1934,9 @@ cjc.mainProgram(args) -- the returns from copy_jdk_configs.lua should not affect %changelog +* Fri Oct 17 2025 zhangzejian - 1:21.0.8.9-7 +- RISC-V Add Zfa zli imm loads + * Wed Oct 15 2025 zhangshihui - 1:21.0.8.9-6 - RISC-V add CRC32