From c8fce76668c5f5d001c2fcea9b4ed0deb4b0306d Mon Sep 17 00:00:00 2001 From: panxuefeng Date: Mon, 9 Dec 2024 15:16:20 +0800 Subject: [PATCH] LoongArch update to jdk23.0.1+11 --- LoongArch64-support.patch | 1302 ++++++++++++++++++------------------- openjdk-latest.spec | 5 +- 2 files changed, 626 insertions(+), 681 deletions(-) diff --git a/LoongArch64-support.patch b/LoongArch64-support.patch index 80a93bd..4762839 100644 --- a/LoongArch64-support.patch +++ b/LoongArch64-support.patch @@ -1093,13 +1093,13 @@ index 00000000000..f9528680cf0 +} diff --git a/src/hotspot/cpu/loongarch/assembler_loongarch.hpp b/src/hotspot/cpu/loongarch/assembler_loongarch.hpp new file mode 100644 -index 00000000000..a4ee680663d +index 00000000000..f57ce474bed --- /dev/null +++ b/src/hotspot/cpu/loongarch/assembler_loongarch.hpp @@ -0,0 +1,3213 @@ +/* + * Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved. -+ * Copyright (c) 2015, 2023, Loongson Technology. All rights reserved. ++ * Copyright (c) 2015, 2024, Loongson Technology. All rights reserved. + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. + * + * This code is free software; you can redistribute it and/or modify it @@ -2852,15 +2852,15 @@ index 00000000000..a4ee680663d + // Test if x is within signed immediate range for nbits. + static bool is_simm (int x, unsigned int nbits) { + assert(0 < nbits && nbits < 32, "out of bounds"); -+ const int min = -( ((int)1) << nbits-1 ); -+ const int maxplus1 = ( ((int)1) << nbits-1 ); ++ const int min = -( ((int)1) << (nbits-1) ); ++ const int maxplus1 = ( ((int)1) << (nbits-1) ); + return min <= x && x < maxplus1; + } + + static bool is_simm(jlong x, unsigned int nbits) { + assert(0 < nbits && nbits < 64, "out of bounds"); -+ const jlong min = -( ((jlong)1) << nbits-1 ); -+ const jlong maxplus1 = ( ((jlong)1) << nbits-1 ); ++ const jlong min = -( ((jlong)1) << (nbits-1) ); ++ const jlong maxplus1 = ( ((jlong)1) << (nbits-1) ); + return min <= x && x < maxplus1; + } + @@ -5434,13 +5434,13 @@ index 00000000000..f157536797b +} diff --git a/src/hotspot/cpu/loongarch/c1_LIRAssembler_loongarch.hpp b/src/hotspot/cpu/loongarch/c1_LIRAssembler_loongarch.hpp new file mode 100644 -index 00000000000..2d489e691b9 +index 00000000000..6efa280b970 --- /dev/null +++ b/src/hotspot/cpu/loongarch/c1_LIRAssembler_loongarch.hpp @@ -0,0 +1,84 @@ +/* + * Copyright (c) 2000, 2021, Oracle and/or its affiliates. All rights reserved. -+ * Copyright (c) 2021, 2023, Loongson Technology. All rights reserved. ++ * Copyright (c) 2021, 2024, Loongson Technology. All rights reserved. + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. + * + * This code is free software; you can redistribute it and/or modify it @@ -5509,8 +5509,8 @@ index 00000000000..2d489e691b9 + void emit_cmp_branch(LIR_OpBranch* op); + + enum { -+ // call stub: CompiledStaticCall::to_interp_stub_size() + -+ // CompiledStaticCall::to_trampoline_stub_size() ++ // call stub: CompiledDirectCall::to_interp_stub_size() + ++ // CompiledDirectCall::to_trampoline_stub_size() + _call_stub_size = 13 * NativeInstruction::nop_instruction_size, + _exception_handler_size = DEBUG_ONLY(1*K) NOT_DEBUG(175), + _deopt_handler_size = 7 * NativeInstruction::nop_instruction_size @@ -5524,13 +5524,13 @@ index 00000000000..2d489e691b9 +#endif // CPU_LOONGARCH_C1_LIRASSEMBLER_LOONGARCH_HPP diff --git a/src/hotspot/cpu/loongarch/c1_LIRAssembler_loongarch_64.cpp b/src/hotspot/cpu/loongarch/c1_LIRAssembler_loongarch_64.cpp new file mode 100644 -index 00000000000..1cea5b84c0f +index 00000000000..61332a25b5d --- /dev/null +++ b/src/hotspot/cpu/loongarch/c1_LIRAssembler_loongarch_64.cpp -@@ -0,0 +1,3365 @@ +@@ -0,0 +1,3337 @@ +/* + * Copyright (c) 2000, 2021, Oracle and/or its affiliates. All rights reserved. -+ * Copyright (c) 2021, 2023, Loongson Technology. All rights reserved. ++ * Copyright (c) 2021, 2024, Loongson Technology. All rights reserved. + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. + * + * This code is free software; you can redistribute it and/or modify it @@ -5781,35 +5781,7 @@ index 00000000000..1cea5b84c0f + +// inline cache check; done before the frame is built. +int LIR_Assembler::check_icache() { -+ Register receiver = FrameMap::receiver_opr->as_register(); -+ Register ic_klass = IC_Klass; -+ int start_offset = __ offset(); -+ Label dont; -+ -+ __ verify_oop(receiver); -+ -+ // explicit null check not needed since load from [klass_offset] causes a trap -+ // check against inline cache -+ assert(!MacroAssembler::needs_explicit_null_check(oopDesc::klass_offset_in_bytes()), -+ "must add explicit null check"); -+ -+ __ load_klass(SCR2, receiver); -+ __ beq(SCR2, ic_klass, dont); -+ -+ // if icache check fails, then jump to runtime routine -+ // Note: RECEIVER must still contain the receiver! -+ __ jmp(SharedRuntime::get_ic_miss_stub(), relocInfo::runtime_call_type); -+ -+ // We align the verified entry point unless the method body -+ // (including its inline cache check) will fit in a single 64-byte -+ // icache line. -+ if (!method()->is_accessor() || __ offset() - start_offset > 4 * 4) { -+ // force alignment after the cache check. -+ __ align(CodeEntryAlignment); -+ } -+ -+ __ bind(dont); -+ return start_offset; ++ return __ ic_check(CodeEntryAlignment); +} + +void LIR_Assembler::clinit_barrier(ciMethod* method) { @@ -7864,7 +7836,7 @@ index 00000000000..1cea5b84c0f + // This is recognized as unresolved by relocs/nativeInst/ic code + __ patchable_jump(__ pc()); + -+ assert(__ offset() - start + CompiledStaticCall::to_trampoline_stub_size() <= call_stub_size(), ++ assert(__ offset() - start + CompiledDirectCall::to_trampoline_stub_size() <= call_stub_size(), + "stub too big"); + __ end_a_stub(); +} @@ -8561,7 +8533,7 @@ index 00000000000..1cea5b84c0f + // set already but no need to check. + __ beqz(SCR1, next); + -+ __ andi(SCR1, tmp, TypeEntries::type_unknown); ++ __ test_bit(SCR1, tmp, exact_log2(TypeEntries::type_unknown)); + __ bnez(SCR1, next); // already unknown. Nothing to do anymore. + + if (TypeEntries::is_type_none(current_klass)) { @@ -8584,7 +8556,7 @@ index 00000000000..1cea5b84c0f + ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "conflict only"); + + __ ld_d(tmp, mdo_addr); -+ __ andi(SCR2, tmp, TypeEntries::type_unknown); ++ __ test_bit(SCR1, tmp, exact_log2(TypeEntries::type_unknown)); + __ bnez(SCR2, next); // already unknown. Nothing to do anymore. + } + @@ -8647,7 +8619,7 @@ index 00000000000..1cea5b84c0f + ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "inconsistent"); + + __ ld_d(tmp, mdo_addr); -+ __ andi(SCR1, tmp, TypeEntries::type_unknown); ++ __ test_bit(SCR1, tmp, exact_log2(TypeEntries::type_unknown)); + __ bnez(SCR1, next); // already unknown. Nothing to do anymore. + + __ ori(tmp, tmp, TypeEntries::type_unknown); @@ -8895,13 +8867,13 @@ index 00000000000..1cea5b84c0f +#undef __ diff --git a/src/hotspot/cpu/loongarch/c1_LIRGenerator_loongarch_64.cpp b/src/hotspot/cpu/loongarch/c1_LIRGenerator_loongarch_64.cpp new file mode 100644 -index 00000000000..bf5fba7a100 +index 00000000000..c11f0318415 --- /dev/null +++ b/src/hotspot/cpu/loongarch/c1_LIRGenerator_loongarch_64.cpp -@@ -0,0 +1,1393 @@ +@@ -0,0 +1,1391 @@ +/* + * Copyright (c) 2005, 2021, Oracle and/or its affiliates. All rights reserved. -+ * Copyright (c) 2021, 2024, Loongson Technology. All rights reserved. ++ * Copyright (c) 2021, 2023, Loongson Technology. All rights reserved. + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. + * + * This code is free software; you can redistribute it and/or modify it @@ -9058,10 +9030,8 @@ index 00000000000..bf5fba7a100 + if (index->is_register()) { + // apply the shift and accumulate the displacement + if (shift > 0) { -+ // Use long register to avoid overflow when shifting large index values left. -+ LIR_Opr tmp = new_register(T_LONG); -+ __ convert(Bytecodes::_i2l, index, tmp); -+ __ shift_left(tmp, shift, tmp); ++ LIR_Opr tmp = new_pointer_register(); ++ __ shift_left(index, shift, tmp); + index = tmp; + } + if (large_disp != 0) { @@ -10589,13 +10559,13 @@ index 00000000000..d1c63b13896 +#endif // CPU_LOONGARCH_C1_MACROASSEMBLER_LOONGARCH_HPP diff --git a/src/hotspot/cpu/loongarch/c1_MacroAssembler_loongarch_64.cpp b/src/hotspot/cpu/loongarch/c1_MacroAssembler_loongarch_64.cpp new file mode 100644 -index 00000000000..eaaaf464fe6 +index 00000000000..12fde2bc0a9 --- /dev/null +++ b/src/hotspot/cpu/loongarch/c1_MacroAssembler_loongarch_64.cpp -@@ -0,0 +1,350 @@ +@@ -0,0 +1,347 @@ +/* + * Copyright (c) 1999, 2021, Oracle and/or its affiliates. All rights reserved. -+ * Copyright (c) 2021, 2023, Loongson Technology. All rights reserved. ++ * Copyright (c) 2021, 2024, Loongson Technology. All rights reserved. + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. + * + * This code is free software; you can redistribute it and/or modify it @@ -10648,8 +10618,7 @@ index 00000000000..eaaaf464fe6 + if (DiagnoseSyncOnValueBasedClasses != 0) { + load_klass(hdr, obj); + ld_w(hdr, Address(hdr, Klass::access_flags_offset())); -+ li(SCR1, JVM_ACC_IS_VALUE_BASED_CLASS); -+ andr(SCR1, hdr, SCR1); ++ test_bit(SCR1, hdr, exact_log2(JVM_ACC_IS_VALUE_BASED_CLASS)); + bnez(SCR1, slow_case); + } + @@ -10716,9 +10685,7 @@ index 00000000000..eaaaf464fe6 + verify_oop(obj); + if (LockingMode == LM_LIGHTWEIGHT) { + ld_d(hdr, Address(obj, oopDesc::mark_offset_in_bytes())); -+ // We cannot use tbnz here, the target might be too far away and cannot -+ // be encoded. -+ andi(AT, hdr, markWord::monitor_value); ++ test_bit(AT, hdr, exact_log2(markWord::monitor_value)); + bnez(AT, slow_case); + lightweight_unlock(obj, hdr, SCR1, SCR2, slow_case); + } else if (LockingMode == LM_LEGACY) { @@ -10945,13 +10912,13 @@ index 00000000000..eaaaf464fe6 +#endif // ifndef PRODUCT diff --git a/src/hotspot/cpu/loongarch/c1_Runtime1_loongarch_64.cpp b/src/hotspot/cpu/loongarch/c1_Runtime1_loongarch_64.cpp new file mode 100644 -index 00000000000..21f7c6f2d00 +index 00000000000..f587ae722df --- /dev/null +++ b/src/hotspot/cpu/loongarch/c1_Runtime1_loongarch_64.cpp -@@ -0,0 +1,1049 @@ +@@ -0,0 +1,1047 @@ +/* + * Copyright (c) 1999, 2021, Oracle and/or its affiliates. All rights reserved. -+ * Copyright (c) 2021, 2023, Loongson Technology. All rights reserved. ++ * Copyright (c) 2021, 2024, Loongson Technology. All rights reserved. + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. + * + * This code is free software; you can redistribute it and/or modify it @@ -10989,7 +10956,6 @@ index 00000000000..21f7c6f2d00 +#include "interpreter/interpreter.hpp" +#include "memory/universe.hpp" +#include "nativeInst_loongarch.hpp" -+#include "oops/compiledICHolder.hpp" +#include "oops/oop.inline.hpp" +#include "prims/jvmtiExport.hpp" +#include "register_loongarch.hpp" @@ -11723,8 +11689,7 @@ index 00000000000..21f7c6f2d00 + Register t = A5; + __ load_klass(t, A0); + __ ld_w(t, Address(t, Klass::access_flags_offset())); -+ __ li(SCR1, JVM_ACC_HAS_FINALIZER); -+ __ andr(SCR1, t, SCR1); ++ __ test_bit(SCR1, t, exact_log2(JVM_ACC_HAS_FINALIZER)); + __ bnez(SCR1, register_finalizer); + __ jr(RA); + @@ -12167,13 +12132,13 @@ index 00000000000..37b74d4ac16 +#undef __ diff --git a/src/hotspot/cpu/loongarch/c2_MacroAssembler_loongarch.cpp b/src/hotspot/cpu/loongarch/c2_MacroAssembler_loongarch.cpp new file mode 100644 -index 00000000000..d83d08e9549 +index 00000000000..62939a8441a --- /dev/null +++ b/src/hotspot/cpu/loongarch/c2_MacroAssembler_loongarch.cpp -@@ -0,0 +1,1903 @@ +@@ -0,0 +1,2011 @@ +/* + * Copyright (c) 2020, Oracle and/or its affiliates. All rights reserved. -+ * Copyright (c) 2021, 2023, Loongson Technology. All rights reserved. ++ * Copyright (c) 2021, 2024, Loongson Technology. All rights reserved. + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. + * + * This code is free software; you can redistribute it and/or modify it @@ -12207,6 +12172,11 @@ index 00000000000..d83d08e9549 +#include "runtime/objectMonitor.hpp" +#include "runtime/stubRoutines.hpp" + ++#ifdef PRODUCT ++#define BLOCK_COMMENT(str) /* nothing */ ++#else ++#define BLOCK_COMMENT(str) block_comment(str) ++#endif + +// using the cr register as the bool result: 0 for failed; others success. +void C2_MacroAssembler::fast_lock_c2(Register oop, Register box, Register flag, @@ -12224,14 +12194,13 @@ index 00000000000..d83d08e9549 + if (DiagnoseSyncOnValueBasedClasses != 0) { + load_klass(flag, oop); + ld_wu(flag, Address(flag, Klass::access_flags_offset())); -+ li(AT, JVM_ACC_IS_VALUE_BASED_CLASS); -+ andr(AT, flag, AT); ++ test_bit(AT, flag, exact_log2(JVM_ACC_IS_VALUE_BASED_CLASS)); + move(flag, R0); + bnez(AT, cont); + } + + // Check for existing monitor -+ andi(AT, disp_hdr, markWord::monitor_value); ++ test_bit(AT, disp_hdr, exact_log2(markWord::monitor_value)); + bnez(AT, object_has_monitor); // inflated vs stack-locked|neutral|bias + + if (LockingMode == LM_MONITOR) { @@ -12329,7 +12298,7 @@ index 00000000000..d83d08e9549 + + // Handle existing monitor. + ld_d(tmp, oop, oopDesc::mark_offset_in_bytes()); -+ andi(AT, tmp, markWord::monitor_value); ++ test_bit(AT, tmp, exact_log2(markWord::monitor_value)); + bnez(AT, object_has_monitor); + + if (LockingMode == LM_MONITOR) { @@ -12356,11 +12325,8 @@ index 00000000000..d83d08e9549 + // If the owner is anonymous, we need to fix it -- in an outline stub. + Register tmp2 = disp_hdr; + ld_d(tmp2, Address(tmp, ObjectMonitor::owner_offset())); -+ // We cannot use tbnz here, the target might be too far away and cannot -+ // be encoded. + assert_different_registers(tmp2, AT); -+ li(AT, (uint64_t)ObjectMonitor::ANONYMOUS_OWNER); -+ andr(AT, tmp2, AT); ++ test_bit(AT, tmp2, exact_log2(ObjectMonitor::ANONYMOUS_OWNER)); + C2HandleAnonOMOwnerStub* stub = new (Compile::current()->comp_arena()) C2HandleAnonOMOwnerStub(tmp, tmp2); + Compile::current()->output()->add_stub(stub); + bnez(AT, stub->entry()); @@ -14074,15 +14040,122 @@ index 00000000000..d83d08e9549 + } + return MacroAssembler::in_scratch_emit_size(); +} ++ ++// jdk.internal.util.ArraysSupport.vectorizedHashCode ++void C2_MacroAssembler::arrays_hashcode(Register ary, Register cnt, Register result, ++ Register tmp1, Register tmp2, Register tmp3, ++ Register tmp4, Register tmp5, Register tmp6, ++ Register tmp7, BasicType eltype) ++{ ++ assert_different_registers(ary, cnt, result, tmp1, tmp2, tmp3, tmp4, tmp5, tmp6, tmp7, SCR1); ++ ++ const int elsize = arrays_hashcode_elsize(eltype); ++ const int chunks_end_shift = exact_log2(elsize); ++ ++ switch (eltype) { ++ case T_BOOLEAN: BLOCK_COMMENT("arrays_hashcode(unsigned byte) {"); break; ++ case T_CHAR: BLOCK_COMMENT("arrays_hashcode(char) {"); break; ++ case T_BYTE: BLOCK_COMMENT("arrays_hashcode(byte) {"); break; ++ case T_SHORT: BLOCK_COMMENT("arrays_hashcode(short) {"); break; ++ case T_INT: BLOCK_COMMENT("arrays_hashcode(int) {"); break; ++ default: ++ ShouldNotReachHere(); ++ } ++ ++ const int stride = 4; ++ const Register pow31_4 = tmp1; ++ const Register pow31_3 = tmp2; ++ const Register pow31_2 = tmp3; ++ const Register chunks = tmp4; ++ const Register chunks_end = chunks; ++ ++ Label DONE, TAIL, TAIL_LOOP, WIDE_LOOP; ++ ++ // result has a value initially ++ ++ beqz(cnt, DONE); ++ ++ srli_d(chunks, cnt, stride>>1); ++ slli_d(chunks, chunks, stride>>1); ++ beqz(chunks, TAIL); ++ ++ li(pow31_4, 923521); // [31^^4] ++ li(pow31_3, 29791); // [31^^3] ++ li(pow31_2, 961); // [31^^2] ++ ++ slli_d(chunks_end, chunks, chunks_end_shift); ++ add_d(chunks_end, ary, chunks_end); ++ andi(cnt, cnt, stride-1); // don't forget about tail! ++ ++ bind(WIDE_LOOP); ++ mul_w(result, result, pow31_4); // 31^^4 * h ++ arrays_hashcode_elload(SCR1, Address(ary, 0 * elsize), eltype); ++ arrays_hashcode_elload(tmp7, Address(ary, 1 * elsize), eltype); ++ arrays_hashcode_elload(tmp5, Address(ary, 2 * elsize), eltype); ++ arrays_hashcode_elload(tmp6, Address(ary, 3 * elsize), eltype); ++ mul_w(SCR1, SCR1, pow31_3); // 31^^3 * ary[i+0] ++ add_w(result, result, SCR1); ++ mul_w(tmp7, tmp7, pow31_2); // 31^^2 * ary[i+1] ++ add_w(result, result, tmp7); ++ slli_w(SCR1, tmp5, 5); // optimize 31^^1 * ary[i+2] ++ sub_w(tmp5, SCR1, tmp5); // with ary[i+2]<<5 - ary[i+2] ++ add_w(result, result, tmp5); ++ add_w(result, result, tmp6); // 31^^4 * h + 31^^3 * ary[i+0] + 31^^2 * ary[i+1] ++ // + 31^^1 * ary[i+2] + 31^^0 * ary[i+3] ++ addi_d(ary, ary, elsize * stride); ++ bne(ary, chunks_end, WIDE_LOOP); ++ beqz(cnt, DONE); ++ ++ bind(TAIL); ++ slli_d(chunks_end, cnt, chunks_end_shift); ++ add_d(chunks_end, ary, chunks_end); ++ ++ bind(TAIL_LOOP); ++ arrays_hashcode_elload(SCR1, Address(ary), eltype); ++ slli_w(tmp7, result, 5); // optimize 31 * result ++ sub_w(result, tmp7, result); // with result<<5 - result ++ add_w(result, result, SCR1); ++ addi_d(ary, ary, elsize); ++ bne(ary, chunks_end, TAIL_LOOP); ++ ++ bind(DONE); ++ BLOCK_COMMENT("} // arrays_hashcode"); ++} ++ ++int C2_MacroAssembler::arrays_hashcode_elsize(BasicType eltype) { ++ switch (eltype) { ++ case T_BOOLEAN: return sizeof(jboolean); ++ case T_BYTE: return sizeof(jbyte); ++ case T_SHORT: return sizeof(jshort); ++ case T_CHAR: return sizeof(jchar); ++ case T_INT: return sizeof(jint); ++ default: ++ ShouldNotReachHere(); ++ return -1; ++ } ++} ++ ++void C2_MacroAssembler::arrays_hashcode_elload(Register dst, Address src, BasicType eltype) { ++ switch (eltype) { ++ // T_BOOLEAN used as surrogate for unsigned byte ++ case T_BOOLEAN: ld_bu(dst, src); break; ++ case T_BYTE: ld_b(dst, src); break; ++ case T_SHORT: ld_h(dst, src); break; ++ case T_CHAR: ld_hu(dst, src); break; ++ case T_INT: ld_w(dst, src); break; ++ default: ++ ShouldNotReachHere(); ++ } ++} diff --git a/src/hotspot/cpu/loongarch/c2_MacroAssembler_loongarch.hpp b/src/hotspot/cpu/loongarch/c2_MacroAssembler_loongarch.hpp new file mode 100644 -index 00000000000..804e060f195 +index 00000000000..a4fef55b68e --- /dev/null +++ b/src/hotspot/cpu/loongarch/c2_MacroAssembler_loongarch.hpp -@@ -0,0 +1,141 @@ +@@ -0,0 +1,150 @@ +/* + * Copyright (c) 2020, Oracle and/or its affiliates. All rights reserved. -+ * Copyright (c) 2021, 2023, Loongson Technology. All rights reserved. ++ * Copyright (c) 2021, 2024, Loongson Technology. All rights reserved. + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. + * + * This code is free software; you can redistribute it and/or modify it @@ -14151,6 +14224,15 @@ index 00000000000..804e060f195 + Register cnt, Register tmp1, Register tmp2, Register result, + bool is_char, bool is_array); + ++ void arrays_hashcode(Register ary, Register cnt, Register result, ++ Register tmp1, Register tmp2, ++ Register tmp3, Register tmp4, ++ Register tmp5, Register tmp6, ++ Register tmp7, BasicType eltype); ++ // helper function for arrays_hashcode ++ int arrays_hashcode_elsize(BasicType eltype); ++ void arrays_hashcode_elload(Register dst, Address src, BasicType eltype); ++ + // Memory Data Type + #define INT_TYPE 0x100 + #define FLOAT_TYPE 0x200 @@ -14438,13 +14520,13 @@ index 00000000000..c8041a57f96 +#endif // CPU_LOONGARCH_CODEBUFFER_LOONGARCH_HPP diff --git a/src/hotspot/cpu/loongarch/compiledIC_loongarch.cpp b/src/hotspot/cpu/loongarch/compiledIC_loongarch.cpp new file mode 100644 -index 00000000000..17ee4b75f72 +index 00000000000..d1806472335 --- /dev/null +++ b/src/hotspot/cpu/loongarch/compiledIC_loongarch.cpp -@@ -0,0 +1,138 @@ +@@ -0,0 +1,131 @@ +/* + * Copyright (c) 1997, 2014, Oracle and/or its affiliates. All rights reserved. -+ * Copyright (c) 2015, 2023, Loongson Technology. All rights reserved. ++ * Copyright (c) 2015, 2024, Loongson Technology. All rights reserved. + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. + * + * This code is free software; you can redistribute it and/or modify it @@ -14470,8 +14552,8 @@ index 00000000000..17ee4b75f72 +#include "precompiled.hpp" +#include "asm/macroAssembler.inline.hpp" +#include "code/compiledIC.hpp" -+#include "code/icBuffer.hpp" +#include "code/nmethod.hpp" ++#include "logging/log.hpp" +#include "memory/resourceArea.hpp" +#include "runtime/mutexLocker.hpp" +#include "runtime/safepoint.hpp" @@ -14479,7 +14561,7 @@ index 00000000000..17ee4b75f72 +// ---------------------------------------------------------------------------- + +#define __ _masm. -+address CompiledStaticCall::emit_to_interp_stub(CodeBuffer &cbuf, address mark) { ++address CompiledDirectCall::emit_to_interp_stub(CodeBuffer &cbuf, address mark) { + precond(cbuf.stubs()->start() != badAddress); + precond(cbuf.stubs()->end() != badAddress); + @@ -14491,7 +14573,7 @@ index 00000000000..17ee4b75f72 + // That's why we must use the macroassembler to generate a stub. + MacroAssembler _masm(&cbuf); + -+ address base = __ start_a_stub(CompiledStaticCall::to_interp_stub_size()); ++ address base = __ start_a_stub(CompiledDirectCall::to_interp_stub_size()); + if (base == nullptr) return nullptr; // CodeBuffer::expand failed + // static stub relocation stores the instruction address of the call + @@ -14507,30 +14589,23 @@ index 00000000000..17ee4b75f72 +} +#undef __ + -+int CompiledStaticCall::to_interp_stub_size() { ++int CompiledDirectCall::to_interp_stub_size() { + return NativeInstruction::nop_instruction_size + NativeMovConstReg::instruction_size + NativeGeneralJump::instruction_size; +} + -+int CompiledStaticCall::to_trampoline_stub_size() { ++int CompiledDirectCall::to_trampoline_stub_size() { + return NativeInstruction::nop_instruction_size + NativeCallTrampolineStub::instruction_size; +} + +// Relocation entries for call stub, compiled java to interpreter. -+int CompiledStaticCall::reloc_to_interp_stub() { ++int CompiledDirectCall::reloc_to_interp_stub() { + return 16; +} + -+void CompiledDirectStaticCall::set_to_interpreted(const methodHandle& callee, address entry) { ++void CompiledDirectCall::set_to_interpreted(const methodHandle& callee, address entry) { + address stub = find_stub(); + guarantee(stub != nullptr, "stub not found"); + -+ if (TraceICs) { -+ ResourceMark rm; -+ tty->print_cr("CompiledDirectStaticCall@" INTPTR_FORMAT ": set_to_interpreted %s", -+ p2i(instruction_address()), -+ callee->name_and_sig_as_C_string()); -+ } -+ + // Creation also verifies the object. + NativeMovConstReg* method_holder = nativeMovConstReg_at(stub + NativeInstruction::nop_instruction_size); + NativeGeneralJump* jump = nativeGeneralJump_at(method_holder->next_instruction_address()); @@ -14544,7 +14619,7 @@ index 00000000000..17ee4b75f72 + set_destination_mt_safe(stub); +} + -+void CompiledDirectStaticCall::set_stub_to_clean(static_stub_Relocation* static_stub) { ++void CompiledDirectCall::set_stub_to_clean(static_stub_Relocation* static_stub) { + assert (CompiledIC_lock->is_locked() || SafepointSynchronize::is_at_safepoint(), "mt unsafe call"); + // Reset stub. + address stub = static_stub->addr(); @@ -14560,7 +14635,7 @@ index 00000000000..17ee4b75f72 +// Non-product mode code +#ifndef PRODUCT + -+void CompiledDirectStaticCall::verify() { ++void CompiledDirectCall::verify() { + // Verify call. + _call->verify(); + if (os::is_MP()) { @@ -16729,13 +16804,13 @@ index 00000000000..09703c9d7c4 +} diff --git a/src/hotspot/cpu/loongarch/frame_loongarch.hpp b/src/hotspot/cpu/loongarch/frame_loongarch.hpp new file mode 100644 -index 00000000000..36dd89ff08f +index 00000000000..4e2c8cec35e --- /dev/null +++ b/src/hotspot/cpu/loongarch/frame_loongarch.hpp -@@ -0,0 +1,200 @@ +@@ -0,0 +1,198 @@ +/* + * Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved. -+ * Copyright (c) 2015, 2023, Loongson Technology. All rights reserved. ++ * Copyright (c) 2015, 2024, Loongson Technology. All rights reserved. + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. + * + * This code is free software; you can redistribute it and/or modify it @@ -16890,8 +16965,6 @@ index 00000000000..36dd89ff08f + static void verify_deopt_original_pc(CompiledMethod* nm, intptr_t* unextended_sp); +#endif + -+ const ImmutableOopMap* get_oop_map() const; -+ + public: + // Constructors + @@ -16935,13 +17008,13 @@ index 00000000000..36dd89ff08f +#endif // CPU_LOONGARCH_FRAME_LOONGARCH_HPP diff --git a/src/hotspot/cpu/loongarch/frame_loongarch.inline.hpp b/src/hotspot/cpu/loongarch/frame_loongarch.inline.hpp new file mode 100644 -index 00000000000..8eac47d6ef9 +index 00000000000..d0f11d26f4b --- /dev/null +++ b/src/hotspot/cpu/loongarch/frame_loongarch.inline.hpp -@@ -0,0 +1,473 @@ +@@ -0,0 +1,459 @@ +/* + * Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved. -+ * Copyright (c) 2015, 2023, Loongson Technology. All rights reserved. ++ * Copyright (c) 2015, 2024, Loongson Technology. All rights reserved. + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. + * + * This code is free software; you can redistribute it and/or modify it @@ -17124,7 +17197,7 @@ index 00000000000..8eac47d6ef9 + unextended_sp() == other.unextended_sp() && + fp() == other.fp() && + pc() == other.pc(); -+ assert(!ret || ret && cb() == other.cb() && _deopt_state == other._deopt_state, "inconsistent construction"); ++ assert(!ret || (cb() == other.cb() && _deopt_state == other._deopt_state), "inconsistent construction"); + return ret; +} + @@ -17283,20 +17356,6 @@ index 00000000000..8eac47d6ef9 + return frame::sender_sp_offset - frame::return_addr_offset; +} + -+inline const ImmutableOopMap* frame::get_oop_map() const { -+ if (_cb == nullptr) return nullptr; -+ if (_cb->oop_maps() != nullptr) { -+ NativePostCallNop* nop = nativePostCallNop_at(_pc); -+ if (nop != nullptr && nop->displacement() != 0) { -+ int slot = ((nop->displacement() >> 24) & 0xff); -+ return _cb->oop_map_for_slot(slot, _pc); -+ } -+ const ImmutableOopMap* oop_map = OopMapSet::find_map(this); -+ return oop_map; -+ } -+ return nullptr; -+} -+ +//------------------------------------------------------------------------------ +// frame::sender +frame frame::sender(RegisterMap* map) const { @@ -23443,13 +23502,13 @@ index 00000000000..7a50810acda +%} diff --git a/src/hotspot/cpu/loongarch/globalDefinitions_loongarch.hpp b/src/hotspot/cpu/loongarch/globalDefinitions_loongarch.hpp new file mode 100644 -index 00000000000..2306c5bc6d1 +index 00000000000..65e81626fdc --- /dev/null +++ b/src/hotspot/cpu/loongarch/globalDefinitions_loongarch.hpp -@@ -0,0 +1,58 @@ +@@ -0,0 +1,62 @@ +/* + * Copyright (c) 1999, 2013, Oracle and/or its affiliates. All rights reserved. -+ * Copyright (c) 2015, 2023, Loongson Technology. All rights reserved. ++ * Copyright (c) 2015, 2024, Loongson Technology. All rights reserved. + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. + * + * This code is free software; you can redistribute it and/or modify it @@ -23502,8 +23561,12 @@ index 00000000000..2306c5bc6d1 + +#define USE_POINTERS_TO_REGISTER_IMPL_ARRAY + ++// The expected size in bytes of a cache line. +#define DEFAULT_CACHE_LINE_SIZE 64 + ++// The default padding size for data structures to avoid false sharing. ++#define DEFAULT_PADDING_SIZE DEFAULT_CACHE_LINE_SIZE ++ +#endif // CPU_LOONGARCH_GLOBALDEFINITIONS_LOONGARCH_HPP diff --git a/src/hotspot/cpu/loongarch/globals_loongarch.hpp b/src/hotspot/cpu/loongarch/globals_loongarch.hpp new file mode 100644 @@ -23636,94 +23699,6 @@ index 00000000000..e38b0401bee +// end of ARCH_FLAGS + +#endif // CPU_LOONGARCH_GLOBALS_LOONGARCH_HPP -diff --git a/src/hotspot/cpu/loongarch/icBuffer_loongarch.cpp b/src/hotspot/cpu/loongarch/icBuffer_loongarch.cpp -new file mode 100644 -index 00000000000..c53d50d78f6 ---- /dev/null -+++ b/src/hotspot/cpu/loongarch/icBuffer_loongarch.cpp -@@ -0,0 +1,82 @@ -+/* -+ * Copyright (c) 1997, 2012, Oracle and/or its affiliates. All rights reserved. -+ * Copyright (c) 2015, 2022, Loongson Technology. All rights reserved. -+ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. -+ * -+ * This code is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 only, as -+ * published by the Free Software Foundation. -+ * -+ * This code is distributed in the hope that it will be useful, but WITHOUT -+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -+ * version 2 for more details (a copy is included in the LICENSE file that -+ * accompanied this code). -+ * -+ * You should have received a copy of the GNU General Public License version -+ * 2 along with this work; if not, write to the Free Software Foundation, -+ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. -+ * -+ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA -+ * or visit www.oracle.com if you need additional information or have any -+ * questions. -+ * -+ */ -+ -+#include "precompiled.hpp" -+#include "asm/macroAssembler.hpp" -+#include "asm/macroAssembler.inline.hpp" -+#include "code/icBuffer.hpp" -+#include "gc/shared/collectedHeap.inline.hpp" -+#include "interpreter/bytecodes.hpp" -+#include "memory/resourceArea.hpp" -+#include "nativeInst_loongarch.hpp" -+#include "oops/oop.inline.hpp" -+ -+ -+int InlineCacheBuffer::ic_stub_code_size() { -+ return NativeMovConstReg::instruction_size + // patchable_li52() == 3 ins -+ NativeGeneralJump::instruction_size; // patchable_jump() == 2 ins -+} -+ -+ -+// The use IC_Klass refer to SharedRuntime::gen_i2c2i_adapters -+void InlineCacheBuffer::assemble_ic_buffer_code(address code_begin, -+ void* cached_value, -+ address entry_point) { -+ ResourceMark rm; -+ CodeBuffer code(code_begin, ic_stub_code_size()); -+ MacroAssembler* masm = new MacroAssembler(&code); -+ // Note: even though the code contains an embedded value, we do not need reloc info -+ // because -+ // (1) the value is old (i.e., doesn't matter for scavenges) -+ // (2) these ICStubs are removed *before* a GC happens, so the roots disappear -+ -+#define __ masm-> -+ address start = __ pc(); -+ __ patchable_li52(IC_Klass, (long)cached_value); -+ __ jmp(entry_point, relocInfo::runtime_call_type); -+ -+ ICache::invalidate_range(code_begin, InlineCacheBuffer::ic_stub_code_size()); -+ assert(__ pc() - start == ic_stub_code_size(), "must be"); -+#undef __ -+} -+ -+ -+address InlineCacheBuffer::ic_buffer_entry_point(address code_begin) { -+ // move -> jump -> entry -+ NativeMovConstReg* move = nativeMovConstReg_at(code_begin); -+ NativeGeneralJump* jump = nativeGeneralJump_at(move->next_instruction_address()); -+ return jump->jump_destination(); -+} -+ -+ -+void* InlineCacheBuffer::ic_buffer_cached_value(address code_begin) { -+ // double check the instructions flow -+ NativeMovConstReg* move = nativeMovConstReg_at(code_begin); -+ NativeGeneralJump* jump = nativeGeneralJump_at(move->next_instruction_address()); -+ -+ // cached value is the data arg of NativeMovConstReg -+ void* cached_value = (void*)move->data(); -+ return cached_value; -+} diff --git a/src/hotspot/cpu/loongarch/icache_loongarch.cpp b/src/hotspot/cpu/loongarch/icache_loongarch.cpp new file mode 100644 index 00000000000..59906711428 @@ -24098,13 +24073,13 @@ index 00000000000..85bed067c49 +#endif // CPU_LOONGARCH_INTERP_MASM_LOONGARCH_64_HPP diff --git a/src/hotspot/cpu/loongarch/interp_masm_loongarch_64.cpp b/src/hotspot/cpu/loongarch/interp_masm_loongarch_64.cpp new file mode 100644 -index 00000000000..0e9e66940b4 +index 00000000000..9950ded9eb3 --- /dev/null +++ b/src/hotspot/cpu/loongarch/interp_masm_loongarch_64.cpp -@@ -0,0 +1,1884 @@ +@@ -0,0 +1,1881 @@ +/* + * Copyright (c) 2003, 2013, Oracle and/or its affiliates. All rights reserved. -+ * Copyright (c) 2015, 2023, Loongson Technology. All rights reserved. ++ * Copyright (c) 2015, 2024, Loongson Technology. All rights reserved. + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. + * + * This code is free software; you can redistribute it and/or modify it @@ -24238,25 +24213,23 @@ index 00000000000..0e9e66940b4 + restore_locals(); +} + -+ +void InterpreterMacroAssembler::check_and_handle_popframe(Register java_thread) { + if (JvmtiExport::can_pop_frame()) { + Label L; + // Initiate popframe handling only if it is not already being -+ // processed. If the flag has the popframe_processing bit set, it -+ // means that this code is called *during* popframe handling - we ++ // processed. If the flag has the popframe_processing bit set, ++ // it means that this code is called *during* popframe handling - we + // don't want to reenter. + // This method is only called just after the call into the vm in + // call_VM_base, so the arg registers are available. -+ // Not clear if any other register is available, so load AT twice + assert(AT != java_thread, "check"); -+ ld_w(AT, java_thread, in_bytes(JavaThread::popframe_condition_offset())); -+ andi(AT, AT, JavaThread::popframe_pending_bit); -+ beq(AT, R0, L); -+ -+ ld_w(AT, java_thread, in_bytes(JavaThread::popframe_condition_offset())); -+ andi(AT, AT, JavaThread::popframe_processing_bit); -+ bne(AT, R0, L); ++ ld_w(AT, Address(java_thread, JavaThread::popframe_condition_offset())); ++ test_bit(T8, AT, exact_log2(JavaThread::popframe_pending_bit)); ++ beqz(T8, L); ++ test_bit(T8, AT, exact_log2(JavaThread::popframe_processing_bit)); ++ bnez(T8, L); ++ // Call Interpreter::remove_activation_preserving_args_entry() to get the ++ // address of the same-named entrypoint in the generated interpreter code. + call_VM_leaf(CAST_FROM_FN_PTR(address, Interpreter::remove_activation_preserving_args_entry)); + jr(V0); + bind(L); @@ -24624,7 +24597,7 @@ index 00000000000..0e9e66940b4 + if (needs_thread_local_poll) { + NOT_PRODUCT(block_comment("Thread-local Safepoint poll")); + ld_d(SCR1, TREG, in_bytes(JavaThread::polling_word_offset())); -+ andi(SCR1, SCR1, SafepointMechanism::poll_bit()); ++ test_bit(SCR1, SCR1, exact_log2(SafepointMechanism::poll_bit())); + bnez(SCR1, safepoint); + } + @@ -24722,7 +24695,7 @@ index 00000000000..0e9e66940b4 + // get method access flags + ld_d(AT, FP, frame::interpreter_frame_method_offset * wordSize); + ld_wu(AT, AT, in_bytes(Method::access_flags_offset())); -+ andi(AT, AT, JVM_ACC_SYNCHRONIZED); ++ test_bit(AT, AT, exact_log2(JVM_ACC_SYNCHRONIZED)); + beqz(AT, unlocked); + + // Don't unlock anything if the _do_not_unlock_if_synchronized flag is set. @@ -24887,9 +24860,8 @@ index 00000000000..0e9e66940b4 + if (DiagnoseSyncOnValueBasedClasses != 0) { + load_klass(tmp_reg, scr_reg); + ld_w(tmp_reg, Address(tmp_reg, Klass::access_flags_offset())); -+ li(AT, JVM_ACC_IS_VALUE_BASED_CLASS); -+ andr(AT, AT, tmp_reg); -+ bnez(AT, slow_case); ++ test_bit(tmp_reg, tmp_reg, exact_log2(JVM_ACC_IS_VALUE_BASED_CLASS)); ++ bnez(tmp_reg, slow_case); + } + + if (LockingMode == LM_LIGHTWEIGHT) { @@ -24993,7 +24965,7 @@ index 00000000000..0e9e66940b4 + bne(scr_reg, tmp, slow_case); + + ld_d(hdr_reg, Address(scr_reg, oopDesc::mark_offset_in_bytes())); -+ andi(AT, hdr_reg, markWord::monitor_value); ++ test_bit(AT, hdr_reg, exact_log2(markWord::monitor_value)); + bnez(AT, slow_case); + lightweight_unlock(scr_reg, hdr_reg, tmp_reg, SCR1, slow_case); + b(count); @@ -25581,19 +25553,19 @@ index 00000000000..0e9e66940b4 + addi_d(AT, T4, -T_BOOLEAN); + bne(AT, R0, notBool); + andi(result, result, 0x1); -+ beq(R0, R0, done); ++ b(done); + + bind(notBool); + addi_d(AT, T4, -T_BYTE); + bne(AT, R0, notByte); + ext_w_b(result, result); -+ beq(R0, R0, done); ++ b(done); + + bind(notByte); + addi_d(AT, T4, -T_CHAR); + bne(AT, R0, notChar); + bstrpick_d(result, result, 15, 0); -+ beq(R0, R0, done); ++ b(done); + + bind(notChar); + ext_w_h(result, result); @@ -25646,7 +25618,7 @@ index 00000000000..0e9e66940b4 + bstrpick_d(T5, obj, 63, 2); + beqz(T5, next); + -+ andi(T5, obj, TypeEntries::type_unknown); ++ test_bit(T5, obj, exact_log2(TypeEntries::type_unknown)); + bnez(T5, next); + + beqz(AT, none); @@ -26418,13 +26390,13 @@ index 00000000000..79a65cd5be1 +#endif // CPU_LOONGARCH_JAVAFRAMEANCHOR_LOONGARCH_HPP diff --git a/src/hotspot/cpu/loongarch/jniFastGetField_loongarch_64.cpp b/src/hotspot/cpu/loongarch/jniFastGetField_loongarch_64.cpp new file mode 100644 -index 00000000000..8e8e548e610 +index 00000000000..eb697ec6793 --- /dev/null +++ b/src/hotspot/cpu/loongarch/jniFastGetField_loongarch_64.cpp @@ -0,0 +1,179 @@ +/* + * Copyright (c) 2004, 2010, Oracle and/or its affiliates. All rights reserved. -+ * Copyright (c) 2015, 2023, Loongson Technology. All rights reserved. ++ * Copyright (c) 2015, 2024, Loongson Technology. All rights reserved. + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. + * + * This code is free software; you can redistribute it and/or modify it @@ -26498,9 +26470,9 @@ index 00000000000..8e8e548e610 + + __ li(counter_addr, SafepointSynchronize::safepoint_counter_addr()); + __ ld_w(counter_prev_val, counter_addr, 0); -+ + // Parameters(A0~A3) should not be modified, since they will be used in slow path -+ __ andi(tmp1, counter_prev_val, 1); ++ __ test_bit(tmp1, counter_prev_val, exact_log2(1)); ++ // An even value means there are no ongoing safepoint operations + __ bnez(tmp1, slow); + + if (JvmtiExport::can_post_field_access()) { @@ -26984,13 +26956,13 @@ index 00000000000..80dff0c7626 + diff --git a/src/hotspot/cpu/loongarch/loongarch_64.ad b/src/hotspot/cpu/loongarch/loongarch_64.ad new file mode 100644 -index 00000000000..c725468b09f +index 00000000000..ac51e3eaf7d --- /dev/null +++ b/src/hotspot/cpu/loongarch/loongarch_64.ad -@@ -0,0 +1,15964 @@ +@@ -0,0 +1,16015 @@ +// +// Copyright (c) 2003, 2013, Oracle and/or its affiliates. All rights reserved. -+// Copyright (c) 2015, 2023, Loongson Technology. All rights reserved. ++// Copyright (c) 2015, 2024, Loongson Technology. All rights reserved. +// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. +// +// This code is free software; you can redistribute it and/or modify it @@ -28005,7 +27977,7 @@ index 00000000000..c725468b09f + return true; // Per default match rules are supported. +} + -+bool Matcher::match_rule_supported_superword(int opcode, int vlen, BasicType bt) { ++bool Matcher::match_rule_supported_auto_vectorization(int opcode, int vlen, BasicType bt) { + return match_rule_supported_vector(opcode, vlen, bt); +} + @@ -28137,7 +28109,7 @@ index 00000000000..c725468b09f + return -1; +} + -+int Matcher::superword_max_vector_size(const BasicType bt) { ++int Matcher::max_vector_size_auto_vectorization(const BasicType bt) { + return Matcher::max_vector_size(bt); +} + @@ -29040,25 +29012,24 @@ index 00000000000..c725468b09f +//============================================================================= +#ifndef PRODUCT +void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream* st ) const { -+ st->print_cr("load_klass(T4, T0)"); -+ st->print_cr("\tbeq(T4, iCache, L)"); ++ st->print_cr("# MachUEPNode"); ++ if (UseCompressedClassPointers) { ++ st->print_cr("\tld_wu AT, T0, oopDesc::klass_offset_in_bytes()"); ++ st->print_cr("\tld_wu T4, T1, CompiledICData::speculated_klass_offset()"); ++ } else { ++ st->print_cr("\tld_d AT, T0, oopDesc::klass_offset_in_bytes()"); ++ st->print_cr("\tld_d T4, T1, CompiledICData::speculated_klass_offset()"); ++ } ++ st->print_cr("\tbeq(AT, T4, ic_hit)"); + st->print_cr("\tjmp(SharedRuntime::get_ic_miss_stub(), relocInfo::runtime_call_type)"); -+ st->print_cr(" L:"); ++ st->print_cr(" ic_hit:"); +} +#endif + + +void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { + C2_MacroAssembler _masm(&cbuf); -+ int ic_reg = Matcher::inline_cache_reg_encode(); -+ Label L; -+ Register receiver = T0; -+ Register iCache = as_Register(ic_reg); -+ -+ __ load_klass(T4, receiver); -+ __ beq(T4, iCache, L); -+ __ jmp((address)SharedRuntime::get_ic_miss_stub(), relocInfo::runtime_call_type); -+ __ bind(L); ++ __ ic_check(InteriorEntryAlignment); +} + +uint MachUEPNode::size(PhaseRegAlloc *ra_) const { @@ -29447,7 +29418,7 @@ index 00000000000..c725468b09f + cbuf.shared_stub_to_interp_for(_method, cbuf.insts()->mark_off()); + } else { + // Emit stub for static call -+ address stub = CompiledStaticCall::emit_to_interp_stub(cbuf); ++ address stub = CompiledDirectCall::emit_to_interp_stub(cbuf); + if (stub == nullptr) { + ciEnv::current()->record_failure("CodeCache is full"); + return; @@ -35983,6 +35954,25 @@ index 00000000000..c725468b09f + ins_pipe( pipe_slow ); +%} + ++// fast ArraysSupport.vectorizedHashCode ++instruct arrays_hashcode(a1_RegP ary, mA2RegI cnt, mA0RegI result, immI basic_type, ++ mRegL tmp1, mRegL tmp2, mRegL tmp3, mRegL tmp4, ++ mRegL tmp5, mRegL tmp6, mRegL tmp7) ++%{ ++ match(Set result (VectorizedHashCode (Binary ary cnt) (Binary result basic_type))); ++ effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5, TEMP tmp6, TEMP tmp7, ++ USE_KILL ary, USE_KILL cnt, USE basic_type); ++ ++ format %{ "Array HashCode array[] $ary,$cnt,$result,$basic_type -> $result @ arrays_hashcode" %} ++ ins_encode %{ ++ __ arrays_hashcode($ary$$Register, $cnt$$Register, $result$$Register, ++ $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, ++ $tmp4$$Register, $tmp5$$Register, $tmp6$$Register, ++ $tmp7$$Register, (BasicType)$basic_type$$constant); ++ %} ++ ins_pipe( pipe_slow ); ++%} ++ +//----------Arithmetic Instructions------------------------------------------- +//----------Addition Instructions--------------------------------------------- +instruct addI_Reg_Reg(mRegI dst, mRegIorL2I src1, mRegIorL2I src2) %{ @@ -42850,6 +42840,39 @@ index 00000000000..c725468b09f + ins_pipe(pipe_slow); +%} + ++// ------------------------------ ReverseBytesV -------------------------------- ++ ++instruct reverseBytesV(vReg dst, vReg src) %{ ++ match(Set dst (ReverseBytesV src)); ++ format %{ "(x)vreverse_byte $dst, $src\t# @reverseBytesV" %} ++ ins_encode %{ ++ if (Matcher::vector_length_in_bytes(this) > 16) { ++ switch (Matcher::vector_element_basic_type(this)) { ++ case T_BYTE : if ($dst$$FloatRegister != $src$$FloatRegister) ++ __ xvori_b($dst$$FloatRegister, $src$$FloatRegister, 0); break; ++ case T_SHORT : __ xvshuf4i_b($dst$$FloatRegister, $src$$FloatRegister, 0b10110001); break; ++ case T_INT : __ xvshuf4i_b($dst$$FloatRegister, $src$$FloatRegister, 0b00011011); break; ++ case T_LONG : __ xvshuf4i_w($dst$$FloatRegister, $src$$FloatRegister, 0b10110001); ++ __ xvshuf4i_b($dst$$FloatRegister, $dst$$FloatRegister, 0b00011011); break; ++ default: ++ ShouldNotReachHere(); ++ } ++ } else { ++ switch (Matcher::vector_element_basic_type(this)) { ++ case T_BYTE : if ($dst$$FloatRegister != $src$$FloatRegister) ++ __ vori_b($dst$$FloatRegister, $src$$FloatRegister, 0); break; ++ case T_SHORT : __ vshuf4i_b($dst$$FloatRegister, $src$$FloatRegister, 0b10110001); break; ++ case T_INT : __ vshuf4i_b($dst$$FloatRegister, $src$$FloatRegister, 0b00011011); break; ++ case T_LONG : __ vshuf4i_w($dst$$FloatRegister, $src$$FloatRegister, 0b10110001); ++ __ vshuf4i_b($dst$$FloatRegister, $dst$$FloatRegister, 0b00011011); break; ++ default: ++ ShouldNotReachHere(); ++ } ++ } ++ %} ++ ins_pipe(pipe_slow); ++%} ++ + +//----------PEEPHOLE RULES----------------------------------------------------- +// These must follow all instruction definitions as they use the names @@ -42954,13 +42977,13 @@ index 00000000000..c725468b09f + diff --git a/src/hotspot/cpu/loongarch/macroAssembler_loongarch.cpp b/src/hotspot/cpu/loongarch/macroAssembler_loongarch.cpp new file mode 100644 -index 00000000000..1e23abc76f8 +index 00000000000..adcf1c8ac3b --- /dev/null +++ b/src/hotspot/cpu/loongarch/macroAssembler_loongarch.cpp -@@ -0,0 +1,4279 @@ +@@ -0,0 +1,4326 @@ +/* + * Copyright (c) 1997, 2014, Oracle and/or its affiliates. All rights reserved. -+ * Copyright (c) 2017, 2023, Loongson Technology. All rights reserved. ++ * Copyright (c) 2017, 2024, Loongson Technology. All rights reserved. + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. + * + * This code is free software; you can redistribute it and/or modify it @@ -42987,6 +43010,7 @@ index 00000000000..1e23abc76f8 +#include "asm/assembler.hpp" +#include "asm/assembler.inline.hpp" +#include "asm/macroAssembler.inline.hpp" ++#include "code/compiledIC.hpp" +#include "compiler/disassembler.hpp" +#include "compiler/oopMap.hpp" +#include "gc/shared/barrierSet.hpp" @@ -43558,6 +43582,41 @@ index 00000000000..1e23abc76f8 + return trampoline_call(AddressLiteral(entry, rh)); +} + ++int MacroAssembler::ic_check_size() { ++ return 4 * 5; ++} ++ ++int MacroAssembler::ic_check(int end_alignment) { ++ Register receiver = j_rarg0; ++ Register data = IC_Klass; ++ Register tmp1 = SCR1; ++ Register tmp2 = SCR2; ++ ++ // The UEP of a code blob ensures that the VEP is padded. However, the padding of the UEP is placed ++ // before the inline cache check, so we don't have to execute any nop instructions when dispatching ++ // through the UEP, yet we can ensure that the VEP is aligned appropriately. That's why we align ++ // before the inline cache check here, and not after ++ align(end_alignment, offset() + ic_check_size()); ++ int uep_offset = offset(); ++ ++ if (UseCompressedClassPointers) { ++ ld_wu(tmp1, Address(receiver, oopDesc::klass_offset_in_bytes())); ++ ld_wu(tmp2, Address(data, CompiledICData::speculated_klass_offset())); ++ } else { ++ ld_d(tmp1, Address(receiver, oopDesc::klass_offset_in_bytes())); ++ ld_d(tmp2, Address(data, CompiledICData::speculated_klass_offset())); ++ } ++ ++ Label ic_hit; ++ beq(tmp1, tmp2, ic_hit); ++ relocate(relocInfo::runtime_call_type); ++ patchable_jump(SharedRuntime::get_ic_miss_stub(), true /* force patchable */); ++ bind(ic_hit); ++ ++ assert((offset() % end_alignment) == 0, "Misaligned verified entry point."); ++ return uep_offset; ++} ++ +void MacroAssembler::emit_static_call_stub() { + // Code stream for loading method may be changed. + ibar(0); @@ -43980,7 +44039,7 @@ index 00000000000..1e23abc76f8 + // we may safely use the sp instead to perform the stack watermark check. + blt_far(AT, in_nmethod ? SP : FP, slow_path, false /* signed */); + } else { -+ andi(AT, AT, SafepointMechanism::poll_bit()); ++ test_bit(AT, AT, exact_log2(SafepointMechanism::poll_bit())); + bnez(AT, slow_path); + } +} @@ -44305,6 +44364,10 @@ index 00000000000..1e23abc76f8 + slli_w(dst, dst, 0); // keep sign, clear upper bits +} + ++void MacroAssembler::test_bit(Register dst, Register src, uint32_t bit_pos) { ++ bstrpick_d(dst, src, bit_pos, bit_pos); ++} ++ +void MacroAssembler::cmpxchg(Address addr, Register oldval, Register newval, + Register resflag, bool retold, bool acquire, + bool weak, bool exchange) { @@ -44734,7 +44797,14 @@ index 00000000000..1e23abc76f8 +} + +void MacroAssembler::align(int modulus) { -+ while (offset() % modulus != 0) nop(); ++ align(modulus, offset()); ++} ++ ++// Ensure that the code at target bytes offset from the current offset() is aligned ++// according to modulus. ++void MacroAssembler::align(int modulus, int target) { ++ int delta = target - offset(); ++ while ((offset() + delta) % modulus != 0) nop(); +} + +void MacroAssembler::post_call_nop() { @@ -45703,7 +45773,7 @@ index 00000000000..1e23abc76f8 + + bind(tagged); + // Test for jweak tag. -+ andi(AT, value, JNIHandles::TypeTag::weak_global); ++ test_bit(AT, value, exact_log2(JNIHandles::TypeTag::weak_global)); + bnez(AT, weak_tagged); + + // Resolve global handle @@ -45729,7 +45799,7 @@ index 00000000000..1e23abc76f8 +#ifdef ASSERT + { + Label valid_global_tag; -+ andi(AT, value, JNIHandles::TypeTag::global); // Test for global tag. ++ test_bit(AT, value, exact_log2(JNIHandles::TypeTag::global)); + bnez(AT, valid_global_tag); + stop("non global jobject using resolve_global_jobject"); + bind(valid_global_tag); @@ -47239,13 +47309,13 @@ index 00000000000..1e23abc76f8 +#endif diff --git a/src/hotspot/cpu/loongarch/macroAssembler_loongarch.hpp b/src/hotspot/cpu/loongarch/macroAssembler_loongarch.hpp new file mode 100644 -index 00000000000..dbed82cd653 +index 00000000000..9f23fd2b26e --- /dev/null +++ b/src/hotspot/cpu/loongarch/macroAssembler_loongarch.hpp -@@ -0,0 +1,815 @@ +@@ -0,0 +1,821 @@ +/* + * Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved. -+ * Copyright (c) 2015, 2023, Loongson Technology. All rights reserved. ++ * Copyright (c) 2015, 2024, Loongson Technology. All rights reserved. + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. + * + * This code is free software; you can redistribute it and/or modify it @@ -47387,6 +47457,7 @@ index 00000000000..dbed82cd653 + + // Alignment + void align(int modulus); ++ void align(int modulus, int target); + + void post_call_nop(); + @@ -47737,6 +47808,8 @@ index 00000000000..dbed82cd653 + + // Emit the CompiledIC call idiom + address ic_call(address entry, jint method_index = 0); ++ static int ic_check_size(); ++ int ic_check(int end_alignment); + + void emit_static_call_stub(); + @@ -47789,6 +47862,9 @@ index 00000000000..dbed82cd653 + // convert big endian integer to little endian integer + void bswap_w(Register dst, Register src); + ++ // test single bit in src, result is set to dst ++ void test_bit(Register dst, Register src, uint32_t bit_pos); ++ + void cmpxchg(Address addr, Register oldval, Register newval, Register resflag, + bool retold, bool acquire, bool weak = false, bool exchange = false); + void cmpxchg(Address addr, Register oldval, Register newval, Register tmp, @@ -50726,10 +50802,10 @@ index 00000000000..b4a1b09b375 +} diff --git a/src/hotspot/cpu/loongarch/matcher_loongarch.hpp b/src/hotspot/cpu/loongarch/matcher_loongarch.hpp new file mode 100644 -index 00000000000..012e781dba8 +index 00000000000..9ee20e0b3d0 --- /dev/null +++ b/src/hotspot/cpu/loongarch/matcher_loongarch.hpp -@@ -0,0 +1,181 @@ +@@ -0,0 +1,186 @@ +/* + * Copyright (c) 2021, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 2021, 2023, Loongson Technology. All rights reserved. @@ -50910,6 +50986,11 @@ index 00000000000..012e781dba8 + } + } + ++ // Is SIMD sort supported for this CPU? ++ static bool supports_simd_sort(BasicType bt) { ++ return false; ++ } ++ +#endif // CPU_LOONGARCH_MATCHER_LOONGARCH_HPP diff --git a/src/hotspot/cpu/loongarch/methodHandles_loongarch.cpp b/src/hotspot/cpu/loongarch/methodHandles_loongarch.cpp new file mode 100644 @@ -51558,13 +51639,13 @@ index 00000000000..8e129225509 + } diff --git a/src/hotspot/cpu/loongarch/nativeInst_loongarch.cpp b/src/hotspot/cpu/loongarch/nativeInst_loongarch.cpp new file mode 100644 -index 00000000000..c298cda5de7 +index 00000000000..cc64142a178 --- /dev/null +++ b/src/hotspot/cpu/loongarch/nativeInst_loongarch.cpp -@@ -0,0 +1,537 @@ +@@ -0,0 +1,542 @@ +/* + * Copyright (c) 1997, 2014, Oracle and/or its affiliates. All rights reserved. -+ * Copyright (c) 2015, 2023, Loongson Technology. All rights reserved. ++ * Copyright (c) 2015, 2024, Loongson Technology. All rights reserved. + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. + * + * This code is free software; you can redistribute it and/or modify it @@ -52075,12 +52156,16 @@ index 00000000000..c298cda5de7 + NativeDeoptInstruction::insert(addr_at(0)); +} + -+void NativePostCallNop::patch(jint diff) { -+ assert(diff != 0, "must be"); ++bool NativePostCallNop::patch(int32_t oopmap_slot, int32_t cb_offset) { ++ if (((oopmap_slot & 0xff) != oopmap_slot) || ((cb_offset & 0xffffff) != cb_offset)) { ++ return false; // cannot encode ++ } ++ uint32_t data = ((uint32_t)oopmap_slot << 24) | cb_offset; ++ assert(data != 0, "must be"); + assert(check(), "must be"); + -+ int lo = (diff & 0xffff); -+ int hi = ((diff >> 16) & 0xffff); ++ int lo = (data & 0xffff); ++ int hi = ((data >> 16) & 0xffff); + + uint32_t *code_pos_first = (uint32_t *) addr_at(4); + uint32_t *code_pos_second = (uint32_t *) addr_at(8); @@ -52089,6 +52174,7 @@ index 00000000000..c298cda5de7 + + *((uint32_t *)(code_pos_first)) = (uint32_t) ((opcode | lo) << 5); + *((uint32_t *)(code_pos_second)) = (uint32_t) ((opcode | hi) << 5); ++ return true; // successfully encoded +} + +void NativeDeoptInstruction::verify() { @@ -52101,13 +52187,13 @@ index 00000000000..c298cda5de7 +} diff --git a/src/hotspot/cpu/loongarch/nativeInst_loongarch.hpp b/src/hotspot/cpu/loongarch/nativeInst_loongarch.hpp new file mode 100644 -index 00000000000..3a322a218a3 +index 00000000000..1246c7c0aa5 --- /dev/null +++ b/src/hotspot/cpu/loongarch/nativeInst_loongarch.hpp -@@ -0,0 +1,595 @@ +@@ -0,0 +1,601 @@ +/* + * Copyright (c) 1997, 2011, Oracle and/or its affiliates. All rights reserved. -+ * Copyright (c) 2015, 2023, Loongson Technology. All rights reserved. ++ * Copyright (c) 2015, 2024, Loongson Technology. All rights reserved. + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. + * + * This code is free software; you can redistribute it and/or modify it @@ -52643,15 +52729,21 @@ index 00000000000..3a322a218a3 + return is_nop() && ((uint_at(4) & 0xffc0001f) == 0x03800000); + } + -+ jint displacement() const { ++ bool decode(int32_t& oopmap_slot, int32_t& cb_offset) const { + uint32_t first_ori = uint_at(4); + uint32_t second_ori = uint_at(8); + int lo = ((first_ori >> 5) & 0xffff); + int hi = ((second_ori >> 5) & 0xffff); -+ return (jint) ((hi << 16) | lo); ++ uint32_t data = (hi << 16) | lo; ++ if (data == 0) { ++ return false; // no information encoded ++ } ++ cb_offset = (data & 0xffffff); ++ oopmap_slot = (data >> 24) & 0xff; ++ return true; // decoding succeeded + } + -+ void patch(jint diff); ++ bool patch(int32_t oopmap_slot, int32_t cb_offset); + void make_deopt(); +}; + @@ -53508,10 +53600,10 @@ index 00000000000..c85ca4963f3 +#endif // CPU_LOONGARCH_RELOCINFO_LOONGARCH_HPP diff --git a/src/hotspot/cpu/loongarch/sharedRuntime_loongarch_64.cpp b/src/hotspot/cpu/loongarch/sharedRuntime_loongarch_64.cpp new file mode 100644 -index 00000000000..23763cc6c78 +index 00000000000..bd984c1e9f8 --- /dev/null +++ b/src/hotspot/cpu/loongarch/sharedRuntime_loongarch_64.cpp -@@ -0,0 +1,2977 @@ +@@ -0,0 +1,2961 @@ +/* + * Copyright (c) 2003, 2013, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 2015, 2024, Loongson Technology. All rights reserved. @@ -53542,13 +53634,11 @@ index 00000000000..23763cc6c78 +#include "asm/macroAssembler.inline.hpp" +#include "code/compiledIC.hpp" +#include "code/debugInfoRec.hpp" -+#include "code/icBuffer.hpp" +#include "code/nativeInst.hpp" +#include "code/vtableStubs.hpp" +#include "compiler/oopMap.hpp" +#include "gc/shared/barrierSetAssembler.hpp" +#include "interpreter/interpreter.hpp" -+#include "oops/compiledICHolder.hpp" +#include "oops/klass.inline.hpp" +#include "oops/method.inline.hpp" +#include "prims/methodHandles.hpp" @@ -54206,25 +54296,18 @@ index 00000000000..23763cc6c78 + Label skip_fixup; + { + __ block_comment("c2i_unverified_entry {"); -+ Register holder = IC_Klass; ++ Register data = IC_Klass; + Register receiver = T0; + Register temp = T8; + address ic_miss = SharedRuntime::get_ic_miss_stub(); + -+ Label missed; -+ -+ //add for compressedoops -+ __ load_klass(temp, receiver); -+ -+ __ ld_d(AT, Address(holder, CompiledICHolder::holder_klass_offset())); -+ __ ld_d(Rmethod, Address(holder, CompiledICHolder::holder_metadata_offset())); -+ __ bne(AT, temp, missed); + // Method might have been compiled since the call site was patched to + // interpreted if that is the case treat it as a miss so we can get + // the call site corrected. ++ __ ic_check(1 /* end_alignment */); ++ __ ld_d(Rmethod, Address(data, CompiledICData::speculated_method_offset())); + __ ld_d(AT, Address(Rmethod, Method::code_offset())); + __ beq(AT, R0, skip_fixup); -+ __ bind(missed); + + __ jmp(ic_miss, relocInfo::runtime_call_type); + __ block_comment("} c2i_unverified_entry"); @@ -54239,7 +54322,7 @@ index 00000000000..23763cc6c78 + + { // Bypass the barrier for non-static methods + __ ld_w(AT, Address(Rmethod, Method::access_flags_offset())); -+ __ andi(AT, AT, JVM_ACC_STATIC); ++ __ test_bit(AT, AT, exact_log2(JVM_ACC_STATIC)); + __ beqz(AT, L_skip_barrier); // non-static + } + @@ -54586,7 +54669,7 @@ index 00000000000..23763cc6c78 + __ b(exit); + + CodeBuffer* cbuf = masm->code_section()->outer(); -+ CompiledStaticCall::emit_to_interp_stub(*cbuf, mark); ++ CompiledDirectCall::emit_to_interp_stub(*cbuf, mark); + } + + // compiled entry @@ -54651,7 +54734,7 @@ index 00000000000..23763cc6c78 + } + + CodeBuffer* cbuf = masm->code_section()->outer(); -+ CompiledStaticCall::emit_to_interp_stub(*cbuf, mark); ++ CompiledDirectCall::emit_to_interp_stub(*cbuf, mark); +} + +static void gen_continuation_yield(MacroAssembler* masm, @@ -54838,6 +54921,7 @@ index 00000000000..23763cc6c78 + in_ByteSize(-1), + oop_maps, + exception_offset); ++ if (nm == nullptr) return nm; + if (method->is_continuation_enter_intrinsic()) { + ContinuationEntry::set_enter_code(nm, interpreted_entry_offset); + } else if (method->is_continuation_yield_intrinsic()) { @@ -54998,24 +55082,17 @@ index 00000000000..23763cc6c78 + + + // First thing make an ic check to see if we should even be here -+ address ic_miss = SharedRuntime::get_ic_miss_stub(); + + // We are free to use all registers as temps without saving them and + // restoring them except fp. fp is the only callee save register + // as far as the interpreter and the compiler(s) are concerned. + -+ const Register ic_reg = IC_Klass; + const Register receiver = T0; + -+ Label hit; + Label exception_pending; + + __ verify_oop(receiver); -+ //add for compressedoops -+ __ load_klass(T4, receiver); -+ __ beq(T4, ic_reg, hit); -+ __ jmp(ic_miss, relocInfo::runtime_call_type); -+ __ bind(hit); ++ __ ic_check(8 /* end_alignment */); + + int vep_offset = ((intptr_t)__ pc()) - start; + @@ -55439,7 +55516,7 @@ index 00000000000..23763cc6c78 + } else { + assert(LockingMode == LM_LIGHTWEIGHT, ""); + __ ld_d(lock_reg, Address(obj_reg, oopDesc::mark_offset_in_bytes())); -+ __ andi(AT, lock_reg, markWord::monitor_value); ++ __ test_bit(AT, lock_reg, exact_log2(markWord::monitor_value)); + __ bnez(AT, slow_path_unlock); + __ lightweight_unlock(obj_reg, lock_reg, swap_reg, SCR1, slow_path_unlock); + __ decrement(Address(TREG, JavaThread::held_monitor_count_offset())); @@ -55988,15 +56065,12 @@ index 00000000000..23763cc6c78 +} + +#ifdef COMPILER2 -+ +//------------------------------generate_uncommon_trap_blob-------------------- -+// Ought to generate an ideal graph & compile, but here's some SPARC ASM -+// instead. +void SharedRuntime::generate_uncommon_trap_blob() { -+ // allocate space for the code ++ // Allocate space for the code + ResourceMark rm; -+ // setup code generation tools -+ CodeBuffer buffer ("uncommon_trap_blob", 512*80 , 512*40 ); ++ // Setup code generation tools ++ CodeBuffer buffer("uncommon_trap_blob", 2048, 1024); + MacroAssembler* masm = new MacroAssembler(&buffer); + + enum frame_layout { @@ -56005,40 +56079,51 @@ index 00000000000..23763cc6c78 + framesize + }; + assert(framesize % 4 == 0, "sp not 16-byte aligned"); ++ + address start = __ pc(); + + // Push self-frame. + __ addi_d(SP, SP, -framesize * BytesPerInt); -+ + __ st_d(RA, SP, return_off * BytesPerInt); + __ st_d(FP, SP, fp_off * BytesPerInt); ++ // we don't expect an arg reg save area ++#ifndef PRODUCT ++ assert(frame::arg_reg_save_area_bytes == 0, "not expecting frame reg save area"); ++#endif ++ // compiler left unloaded_class_index in j_rarg0 move to where the ++ // runtime expects it. ++ __ addi_w(c_rarg1, j_rarg0, 0); + -+ __ addi_d(FP, SP, framesize * BytesPerInt); -+ -+ // set last_Java_sp ++ // we need to set the past SP to the stack pointer of the stub frame ++ // and the pc to the address where this runtime call will return ++ // although actually any pc in this code blob will do). + Label retaddr; -+ __ set_last_Java_frame(NOREG, FP, retaddr); -+ // Call C code. Need thread but NOT official VM entry -+ // crud. We cannot block on this call, no GC can happen. Call should -+ // capture callee-saved registers as well as return values. -+ __ move(A0, TREG); -+ // argument already in T0 -+ __ move(A1, T0); -+ __ addi_d(A2, R0, Deoptimization::Unpack_uncommon_trap); -+ __ call((address)Deoptimization::uncommon_trap, relocInfo::runtime_call_type); ++ __ set_last_Java_frame(noreg, noreg, retaddr); ++ ++ // Call C code. We cannot block on this call, no GC can happen. ++ // Call should capture callee-saved registers as well as return values. ++ // ++ // UnrollBlock* uncommon_trap(JavaThread* thread, jint unloaded_class_index, jint exec_mode) ++ // ++ __ move(c_rarg0, TREG); ++ __ addi_w(c_rarg2, R0, (unsigned)Deoptimization::Unpack_uncommon_trap); ++ __ call(CAST_FROM_FN_PTR(address, Deoptimization::uncommon_trap), ++ relocInfo::runtime_call_type); + __ bind(retaddr); + + // Set an oopmap for the call site + OopMapSet *oop_maps = new OopMapSet(); -+ OopMap* map = new OopMap( framesize, 0 ); + -+ oop_maps->add_gc_map(__ pc() - start, map); ++ oop_maps->add_gc_map(__ pc() - start, new OopMap(framesize, 0)); + + __ reset_last_Java_frame(false); + -+ // Load UnrollBlock into S7 -+ Register unroll = S7; -+ __ move(unroll, V0); ++ Register unroll = T8; ++ Register pcs = T6; ++ Register sizes = T5; ++ Register count = T4; ++ ++ __ move(unroll, c_rarg0); // move call return value to unroll + +#ifdef ASSERT + { Label L; @@ -56055,107 +56140,98 @@ index 00000000000..23763cc6c78 + // Frame picture (youngest to oldest) + // 1: self-frame (no frame link) + // 2: deopting frame (no frame link) -+ // 3: possible-i2c-adapter-frame -+ // 4: caller of deopting frame (could be compiled/interpreted. If interpreted we will create an -+ // and c2i here) ++ // 3: caller of deopting frame (could be compiled/interpreted). + -+ __ addi_d(SP, SP, framesize * BytesPerInt); ++ __ addi_d(SP, SP, framesize << LogBytesPerInt); + -+ // Pop deoptimized frame -+ __ ld_w(T8, Address(unroll, Deoptimization::UnrollBlock::size_of_deoptimized_frame_offset())); -+ __ add_d(SP, SP, T8); ++ // Pop deoptimized frame (int) ++ __ ld_wu(AT, Address(unroll, Deoptimization::UnrollBlock::size_of_deoptimized_frame_offset())); ++ __ add_d(SP, SP, AT); ++ // LoongArch do not need to restore RA and FP here, since: ++ // 1: The RA shall be loaded by frame PC array (frame_pcs) later ++ // 2: The FP is protected via frame::initial_deoptimization_info() + +#ifdef ASSERT + // Compilers generate code that bang the stack by as much as the + // interpreter would need. So this stack banging should never + // trigger a fault. Verify that it does not on non product builds. -+ __ ld_w(TSR, Address(unroll, Deoptimization::UnrollBlock::total_frame_sizes_offset())); -+ __ bang_stack_size(TSR, T8); ++ __ ld_wu(sizes, Address(unroll, Deoptimization::UnrollBlock::total_frame_sizes_offset())); ++ __ bang_stack_size(sizes, pcs /* tmp */); +#endif + -+ // register for frame pcs -+ Register pcs = T8; -+ // register for frame sizes -+ Register sizes = T4; -+ // register for frame count -+ Register count = T3; -+ // register for the sender's sp -+ Register sender_sp = T1; -+ -+ // sp should be pointing at the return address to the caller (4) -+ // Load array of frame pcs + __ ld_d(pcs, Address(unroll, Deoptimization::UnrollBlock::frame_pcs_offset())); -+ -+ // Load array of frame sizes + __ ld_d(sizes, Address(unroll, Deoptimization::UnrollBlock::frame_sizes_offset())); + __ ld_wu(count, Address(unroll, Deoptimization::UnrollBlock::number_of_frames_offset())); + + // Pick up the initial fp we should save + __ ld_d(FP, Address(unroll, Deoptimization::UnrollBlock::initial_info_offset())); + -+ // Now adjust the caller's stack to make up for the extra locals -+ // but record the original sp so that we can save it in the skeletal interpreter -+ // frame and the stack walking of interpreter_sender will get the unextended sp -+ // value and not the "real" sp value. -+ __ move(sender_sp, SP); -+ __ ld_w(AT, Address(unroll, Deoptimization::UnrollBlock::caller_adjustment_offset())); ++ // Now adjust the caller's stack to make up for the extra locals but ++ // record the original sp so that we can save it in the skeletal ++ // interpreter frame and the stack walking of interpreter_sender ++ // will get the unextended sp value and not the "real" sp value. ++ ++ __ move(Rsender, SP); ++ __ ld_wu(AT, Address(unroll, Deoptimization::UnrollBlock::caller_adjustment_offset())); + __ sub_d(SP, SP, AT); + + // Push interpreter frames in a loop + Label loop; + __ bind(loop); -+ __ ld_d(T2, sizes, 0); // Load frame size -+ __ ld_d(RA, pcs, 0); // save return address -+ __ addi_d(T2, T2, -2*wordSize); // we'll push pc and fp, by hand ++ __ ld_d(AT, sizes, 0); // load frame size ++ __ ld_d(RA, pcs, 0); // save return address ++ __ addi_d(AT, AT, -2 * wordSize); // we'll push RA and FP, by hand + __ enter(); -+ __ sub_d(SP, SP, T2); // Prolog! ++ __ sub_d(SP, SP, AT); ++ // Save Rsender to make it walkable, and then pass it to next frame. ++ __ st_d(Rsender, FP, frame::interpreter_frame_sender_sp_offset * wordSize); ++ __ move(Rsender, SP); + // This value is corrected by layout_activation_impl + __ st_d(R0, FP, frame::interpreter_frame_last_sp_offset * wordSize); -+ __ st_d(sender_sp, FP, frame::interpreter_frame_sender_sp_offset * wordSize);// Make it walkable -+ __ move(sender_sp, SP); // pass to next frame -+ __ addi_d(count, count, -1); // decrement counter -+ __ addi_d(sizes, sizes, wordSize); // Bump array pointer (sizes) -+ __ addi_d(pcs, pcs, wordSize); // Bump array pointer (pcs) -+ __ bne(count, R0, loop); ++ __ addi_d(count, count, -1); ++ __ addi_d(sizes, sizes, wordSize); ++ __ addi_d(pcs, pcs, wordSize); ++ __ blt(R0, count, loop); + -+ __ ld_d(RA, pcs, 0); ++ __ ld_d(RA, pcs, 0); // save final return address + -+ // Re-push self-frame -+ // save old & set new FP -+ // save final return address + __ enter(); + -+ // Use FP because the frames look interpreted now -+ // Save "the_pc" since it cannot easily be retrieved using the last_java_SP after we aligned SP. -+ // Don't need the precise return PC here, just precise enough to point into this code blob. ++ // Use FP because the frames look interpreted now. Save "the_pc" since it ++ // cannot easily be retrieved using the last_java_SP after we aligned SP. ++ // Do not need the precise return PC address here, just precise enough to ++ // point into this code blob. + Label L; + address the_pc = __ pc(); + __ bind(L); -+ __ set_last_Java_frame(NOREG, FP, L); ++ __ set_last_Java_frame(SP, FP, L); + + assert(StackAlignmentInBytes == 16, "must be"); -+ __ bstrins_d(SP, R0, 3, 0); // Fix stack alignment as required by ABI ++ __ bstrins_d(SP, R0, 3, 0); ++ ++ // Call C code. We cannot block on this call, no GC can happen. ++ // Call should capture callee-saved registers as well as return values. ++ // ++ // BasicType unpack_frames(JavaThread* thread, int exec_mode) ++ // ++ __ move(c_rarg0, TREG); ++ __ addi_w(c_rarg1, R0, (unsigned)Deoptimization::Unpack_uncommon_trap); ++ __ call(CAST_FROM_FN_PTR(address, Deoptimization::unpack_frames), ++ relocInfo::runtime_call_type); + -+ // Call C code. Need thread but NOT official VM entry -+ // crud. We cannot block on this call, no GC can happen. Call should -+ // restore return values to their stack-slots with the new SP. -+ __ move(A0, TREG); -+ __ li(A1, Deoptimization::Unpack_uncommon_trap); -+ __ call((address)Deoptimization::unpack_frames, relocInfo::runtime_call_type); + // Set an oopmap for the call site ++ // Use the same PC we used for the last java frame + oop_maps->add_gc_map(the_pc - start, new OopMap(framesize, 0)); + + __ reset_last_Java_frame(true); + -+ // Pop self-frame. -+ __ leave(); // Epilog! -+ -+ // Jump to interpreter ++ __ leave(); + __ jr(RA); -+ // ------------- ++ + // make sure all code is generated + masm->flush(); -+ _uncommon_trap_blob = UncommonTrapBlob::create(&buffer, oop_maps, framesize / 2); ++ ++ _uncommon_trap_blob = UncommonTrapBlob::create(&buffer, oop_maps, framesize >> 1); +} + +#endif // COMPILER2 @@ -63064,13 +63140,13 @@ index 00000000000..3cef08cb261 +}; diff --git a/src/hotspot/cpu/loongarch/templateInterpreterGenerator_loongarch.cpp b/src/hotspot/cpu/loongarch/templateInterpreterGenerator_loongarch.cpp new file mode 100644 -index 00000000000..1d487c4e978 +index 00000000000..0311a343810 --- /dev/null +++ b/src/hotspot/cpu/loongarch/templateInterpreterGenerator_loongarch.cpp @@ -0,0 +1,2118 @@ +/* + * Copyright (c) 2003, 2013, Oracle and/or its affiliates. All rights reserved. -+ * Copyright (c) 2015, 2023, Loongson Technology. All rights reserved. ++ * Copyright (c) 2015, 2024, Loongson Technology. All rights reserved. + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. + * + * This code is free software; you can redistribute it and/or modify it @@ -63169,7 +63245,7 @@ index 00000000000..1d487c4e978 + FloatRegister floatreg = as_FloatRegister(i + FA0->encoding()); + Label isdouble, done; + -+ __ andi(AT, A3, 1 << i); ++ __ test_bit(AT, A3, i); + __ bnez(AT, isdouble); + __ fld_s(floatreg, SP, (10 + i) * wordSize); + __ b(done); @@ -63921,7 +63997,7 @@ index 00000000000..1d487c4e978 +#ifdef ASSERT + { Label L; + __ ld_w(T0, Rmethod, in_bytes(Method::access_flags_offset())); -+ __ andi(T0, T0, JVM_ACC_SYNCHRONIZED); ++ __ test_bit(T0, T0, exact_log2(JVM_ACC_SYNCHRONIZED)); + __ bne(T0, R0, L); + __ stop("method doesn't need synchronization"); + __ bind(L); @@ -63931,7 +64007,7 @@ index 00000000000..1d487c4e978 + { + Label done; + __ ld_w(T0, Rmethod, in_bytes(Method::access_flags_offset())); -+ __ andi(T2, T0, JVM_ACC_STATIC); ++ __ test_bit(T2, T0, exact_log2(JVM_ACC_STATIC)); + __ ld_d(T0, LVP, Interpreter::local_offset_in_bytes(0)); + __ beq(T2, R0, done); + __ load_mirror(T0, Rmethod, SCR2, SCR1); @@ -64144,14 +64220,14 @@ index 00000000000..1d487c4e978 + __ ld_w(T0, Rmethod, in_bytes(Method::access_flags_offset())); + { + Label L; -+ __ andi(AT, T0, JVM_ACC_NATIVE); ++ __ test_bit(AT, T0, exact_log2(JVM_ACC_NATIVE)); + __ bne(AT, R0, L); + __ stop("tried to execute native method as non-native"); + __ bind(L); + } + { + Label L; -+ __ andi(AT, T0, JVM_ACC_ABSTRACT); ++ __ test_bit(AT, T0, exact_log2(JVM_ACC_ABSTRACT)); + __ beq(AT, R0, L); + __ stop("tried to execute abstract method in interpreter"); + __ bind(L); @@ -64192,7 +64268,7 @@ index 00000000000..1d487c4e978 + { + Label L; + __ ld_w(T0, Rmethod, in_bytes(Method::access_flags_offset())); -+ __ andi(AT, T0, JVM_ACC_SYNCHRONIZED); ++ __ test_bit(AT, T0, exact_log2(JVM_ACC_SYNCHRONIZED)); + __ beq(AT, R0, L); + __ stop("method needs synchronization"); + __ bind(L); @@ -64247,7 +64323,7 @@ index 00000000000..1d487c4e978 + // LoongArch ABI: caller does not reserve space for the register auguments. + // A0 and A1(if needed) + __ ld_w(AT, Rmethod, in_bytes(Method::access_flags_offset())); -+ __ andi(AT, AT, JVM_ACC_STATIC); ++ __ test_bit(AT, AT, exact_log2(JVM_ACC_STATIC)); + __ beq(AT, R0, Lstatic); + __ addi_d(t, t, 1); + __ bind(Lstatic); @@ -64327,7 +64403,7 @@ index 00000000000..1d487c4e978 + { + Label L; + __ ld_w(t, method, in_bytes(Method::access_flags_offset())); -+ __ andi(AT, t, JVM_ACC_STATIC); ++ __ test_bit(AT, t, exact_log2(JVM_ACC_STATIC)); + __ beq(AT, R0, L); + + // get mirror @@ -64559,7 +64635,7 @@ index 00000000000..1d487c4e978 + const Register monitor_reg = T0; + Label L; + __ ld_w(t, method, in_bytes(Method::access_flags_offset())); -+ __ andi(t, t, JVM_ACC_SYNCHRONIZED); ++ __ test_bit(t, t, exact_log2(JVM_ACC_SYNCHRONIZED)); + __ addi_d(monitor_reg, FP, frame::interpreter_frame_initial_sp_offset * wordSize - (int)sizeof(BasicObjectLock)); + __ beq(t, R0, L); + // the code below should be shared with interpreter macro assembler implementation @@ -64733,14 +64809,14 @@ index 00000000000..1d487c4e978 + __ ld_d(AT, Rmethod, in_bytes(Method::access_flags_offset())); + { + Label L; -+ __ andi(T2, AT, JVM_ACC_NATIVE); ++ __ test_bit(T2, AT, exact_log2(JVM_ACC_NATIVE)); + __ beq(T2, R0, L); + __ stop("tried to execute native method as non-native"); + __ bind(L); + } + { + Label L; -+ __ andi(T2, AT, JVM_ACC_ABSTRACT); ++ __ test_bit(T2, AT, exact_log2(JVM_ACC_ABSTRACT)); + __ beq(T2, R0, L); + __ stop("tried to execute abstract method in interpreter"); + __ bind(L); @@ -64787,8 +64863,8 @@ index 00000000000..1d487c4e978 +#ifdef ASSERT + { Label L; + __ ld_w(AT, Rmethod, in_bytes(Method::access_flags_offset())); -+ __ andi(T2, AT, JVM_ACC_SYNCHRONIZED); -+ __ beq(T2, R0, L); ++ __ test_bit(AT, AT, exact_log2(JVM_ACC_SYNCHRONIZED)); ++ __ beqz(AT, L); + __ stop("method needs synchronization"); + __ bind(L); + } @@ -65232,13 +65308,13 @@ index 00000000000..9278dcfafc3 +#endif // CPU_LOONGARCH_TEMPLATETABLE_LOONGARCH_64_HPP diff --git a/src/hotspot/cpu/loongarch/templateTable_loongarch_64.cpp b/src/hotspot/cpu/loongarch/templateTable_loongarch_64.cpp new file mode 100644 -index 00000000000..74115edea62 +index 00000000000..515a9ec813d --- /dev/null +++ b/src/hotspot/cpu/loongarch/templateTable_loongarch_64.cpp -@@ -0,0 +1,4077 @@ +@@ -0,0 +1,4061 @@ +/* + * Copyright (c) 2003, 2013, Oracle and/or its affiliates. All rights reserved. -+ * Copyright (c) 2015, 2023, Loongson Technology. All rights reserved. ++ * Copyright (c) 2015, 2024, Loongson Technology. All rights reserved. + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. + * + * This code is free software; you can redistribute it and/or modify it @@ -66295,12 +66371,8 @@ index 00000000000..74115edea62 + // since both types share the bastore bytecode. + __ load_klass(T4, A1); + __ ld_w(T4, T4, in_bytes(Klass::layout_helper_offset())); -+ -+ int diffbit = Klass::layout_helper_boolean_diffbit(); -+ __ li(AT, diffbit); -+ + Label L_skip; -+ __ andr(AT, T4, AT); ++ __ test_bit(AT, T4, exact_log2(Klass::layout_helper_boolean_diffbit())); + __ beq(AT, R0, L_skip); + __ andi(FSR, FSR, 0x1); + __ bind(L_skip); @@ -66923,7 +66995,7 @@ index 00000000000..74115edea62 + __ increment_mask_and_jump(mdo_backedge_counter, increment, mask, + T1, false, Assembler::zero, + UseOnStackReplacement ? &backedge_counter_overflow : &dispatch); -+ __ beq(R0, R0, dispatch); ++ __ b(dispatch); + } + __ bind(no_mdo); + // Increment backedge counter in MethodCounters* @@ -67365,9 +67437,8 @@ index 00000000000..74115edea62 + __ ld_d(c_rarg1, aaddress(0)); + __ load_klass(LVP, c_rarg1); + __ ld_w(LVP, Address(LVP, Klass::access_flags_offset())); -+ __ li(AT, JVM_ACC_HAS_FINALIZER); -+ __ andr(AT, AT, LVP); + Label skip_register_finalizer; ++ __ test_bit(AT, LVP, exact_log2(JVM_ACC_HAS_FINALIZER)); + __ beqz(AT, skip_register_finalizer); + + __ call_VM(noreg, CAST_FROM_FN_PTR(address, @@ -67386,7 +67457,7 @@ index 00000000000..74115edea62 + if (_desc->bytecode() != Bytecodes::_return_register_finalizer) { + Label no_safepoint; + __ ld_d(AT, Address(TREG, JavaThread::polling_word_offset())); -+ __ andi(AT, AT, 1 << exact_log2(SafepointMechanism::poll_bit())); ++ __ test_bit(AT, AT, exact_log2(SafepointMechanism::poll_bit())); + __ beqz(AT, no_safepoint); + __ push(state); + __ push_cont_fastpath(TREG); @@ -67557,7 +67628,7 @@ index 00000000000..74115edea62 + + // maybe push appendix to arguments (just before return address) + Label L_no_push; -+ __ andi(AT, flags, 1 << ResolvedMethodEntry::has_appendix_shift); ++ __ test_bit(AT, flags, ResolvedMethodEntry::has_appendix_shift); + __ beqz(AT, L_no_push); + // invokehandle uses an index into the resolved references array + __ ld_hu(ref_index, Address(cache, in_bytes(ResolvedMethodEntry::resolved_references_index_offset()))); @@ -67591,9 +67662,9 @@ index 00000000000..74115edea62 + // Otherwise, the registers will be populated with the klass and method. + + Label NotVirtual; Label NotVFinal; Label Done; -+ __ andi(AT, flags, 1 << ResolvedMethodEntry::is_forced_virtual_shift); ++ __ test_bit(AT, flags, ResolvedMethodEntry::is_forced_virtual_shift); + __ beqz(AT, NotVirtual); -+ __ andi(AT, flags, 1 << ResolvedMethodEntry::is_vfinal_shift); ++ __ test_bit(AT, flags, ResolvedMethodEntry::is_vfinal_shift); + __ beqz(AT, NotVFinal); + __ ld_d(method_or_table_index, Address(cache, in_bytes(ResolvedMethodEntry::method_offset()))); + __ b(Done); @@ -67621,7 +67692,7 @@ index 00000000000..74115edea62 + + // method_or_table_index can either be an itable index or a method depending on the virtual final flag + Label NotVFinal; Label Done; -+ __ andi(AT, flags, 1 << ResolvedMethodEntry::is_vfinal_shift); ++ __ test_bit(AT, flags, ResolvedMethodEntry::is_vfinal_shift); + __ beqz(AT, NotVFinal); + __ ld_d(method_or_table_index, Address(cache, in_bytes(ResolvedMethodEntry::method_offset()))); + __ b(Done); @@ -67672,7 +67743,7 @@ index 00000000000..74115edea62 + Label L_no_push; + // Check if there is an appendix + __ ld_bu(index, Address(cache, in_bytes(ResolvedIndyEntry::flags_offset()))); -+ __ andi(AT, index, 1UL << ResolvedIndyEntry::has_appendix_shift); ++ __ test_bit(AT, index, ResolvedIndyEntry::has_appendix_shift); + __ beqz(AT, L_no_push); + + // Get appendix @@ -67777,10 +67848,8 @@ index 00000000000..74115edea62 + load_resolved_field_entry(obj, cache, tos_state, off, flags, is_static); + + { -+ __ li(scratch, 1 << ResolvedFieldEntry::is_volatile_shift); -+ __ andr(scratch, scratch, flags); -+ + Label notVolatile; ++ __ test_bit(scratch, flags, ResolvedFieldEntry::is_volatile_shift); + __ beq(scratch, R0, notVolatile); + __ membar(MacroAssembler::AnyAny); + __ bind(notVolatile); @@ -68025,16 +68094,13 @@ index 00000000000..74115edea62 + + Label Done; + { -+ __ li(scratch, 1 << ResolvedFieldEntry::is_volatile_shift); -+ __ andr(scratch, scratch, flags); -+ + Label notVolatile; ++ __ test_bit(scratch, flags, ResolvedFieldEntry::is_volatile_shift); + __ beq(scratch, R0, notVolatile); + __ membar(Assembler::Membar_mask_bits(__ StoreStore | __ LoadStore)); + __ bind(notVolatile); + } + -+ + Label notByte, notBool, notInt, notShort, notChar, notLong, notFloat, notObj, notDouble; + + assert(btos == 0, "change code, btos != 0"); @@ -68292,20 +68358,18 @@ index 00000000000..74115edea62 + + // access constant pool cache + __ load_field_entry(T3, T2); -+ -+ // Must prevent reordering of the following cp cache loads with bytecode load -+ __ membar(__ LoadLoad); + __ push(T0); + // T2: field offset, T0: TOS, T1: flags + load_resolved_field_entry(T3, T3, T0, T2, T1); + __ pop(T0); + ++ // Must prevent reordering of the following cp cache loads with bytecode load ++ __ membar(__ LoadLoad); ++ + Label Done; + { -+ __ li(scratch, 1 << ResolvedFieldEntry::is_volatile_shift); -+ __ andr(scratch, scratch, T1); -+ + Label notVolatile; ++ __ test_bit(scratch, T1, ResolvedFieldEntry::is_volatile_shift); + __ beq(scratch, R0, notVolatile); + __ membar(Assembler::Membar_mask_bits(__ StoreStore | __ LoadStore)); + __ bind(notVolatile); @@ -68401,10 +68465,8 @@ index 00000000000..74115edea62 + __ ld_bu(T1, Address(T3, in_bytes(ResolvedFieldEntry::flags_offset()))); + + { -+ __ li(scratch, 1 << ResolvedFieldEntry::is_volatile_shift); -+ __ andr(scratch, scratch, T1); -+ + Label notVolatile; ++ __ test_bit(scratch, T1, ResolvedFieldEntry::is_volatile_shift); + __ beqz(scratch, notVolatile); + __ membar(MacroAssembler::AnyAny); + __ bind(notVolatile); @@ -68474,8 +68536,7 @@ index 00000000000..74115edea62 + + { + __ ld_bu(AT, Address(T3, in_bytes(ResolvedFieldEntry::flags_offset()))); -+ __ li(scratch, 1 << ResolvedFieldEntry::is_volatile_shift); -+ __ andr(scratch, scratch, AT); ++ __ test_bit(scratch, AT, ResolvedFieldEntry::is_volatile_shift); + + Label notVolatile; + __ beq(scratch, R0, notVolatile); @@ -68554,7 +68615,7 @@ index 00000000000..74115edea62 + + // Test for an invoke of a final method + Label notFinal; -+ __ andi(AT, flags, 1 << ResolvedMethodEntry::is_vfinal_shift); ++ __ test_bit(AT, flags, ResolvedMethodEntry::is_vfinal_shift); + __ beq(AT, R0, notFinal); + + Register method = index; // method must be Rmethod @@ -68683,7 +68744,7 @@ index 00000000000..74115edea62 + // Special case of invokeinterface called for virtual method of + // java.lang.Object. See cpCache.cpp for details. + Label notObjectMethod; -+ __ andi(AT, T1, 1 << ResolvedMethodEntry::is_forced_virtual_shift); ++ __ test_bit(AT, T1, ResolvedMethodEntry::is_forced_virtual_shift); + __ beqz(AT, notObjectMethod); + + invokevirtual_helper(Rmethod, T3, T1); @@ -68695,7 +68756,7 @@ index 00000000000..74115edea62 + + // Check for private method invocation - indicated by vfinal + Label notVFinal; -+ __ andi(AT, T1, 1 << ResolvedMethodEntry::is_vfinal_shift); ++ __ test_bit(AT, T1, ResolvedMethodEntry::is_vfinal_shift); + __ beqz(AT, notVFinal); + + // Get receiver klass into FSR @@ -68891,15 +68952,14 @@ index 00000000000..74115edea62 + // get InstanceKlass + __ load_resolved_klass_at_index(A1, A2, T3); + -+ // make sure klass is initialized & doesn't have finalizer -+ // make sure klass is fully initialized -+ __ ld_hu(T1, T3, in_bytes(InstanceKlass::init_state_offset())); -+ __ addi_d(AT, T1, - (int)InstanceKlass::fully_initialized); -+ __ bnez(AT, slow_case); ++ // make sure klass is initialized ++ assert(VM_Version::supports_fast_class_init_checks(), "Optimization requires support for fast class initialization checks"); ++ __ clinit_barrier(T3, T1, nullptr /*L_fast_path*/, &slow_case); + -+ // has_finalizer ++ // get instance_size in InstanceKlass (scaled to a count of bytes) + __ ld_w(T0, T3, in_bytes(Klass::layout_helper_offset()) ); -+ __ andi(AT, T0, Klass::_lh_instance_slow_path_bit); ++ // test to see if it has a finalizer or is malformed in some way ++ __ test_bit(AT, T0, exact_log2(Klass::_lh_instance_slow_path_bit)); + __ bnez(AT, slow_case); + + // Allocate the instance: @@ -69101,7 +69161,7 @@ index 00000000000..74115edea62 + + // Collect counts on whether this test sees nulls a lot or not. + if (ProfileInterpreter) { -+ __ beq(R0, R0, done); ++ __ b(done); + __ bind(is_null); + __ profile_null_seen(T3); + } else { @@ -69729,13 +69789,13 @@ index 00000000000..5b9f7b78981 +#endif // CPU_LOONGARCH_VMSTRUCTS_LOONGARCH_HPP diff --git a/src/hotspot/cpu/loongarch/vm_version_loongarch.cpp b/src/hotspot/cpu/loongarch/vm_version_loongarch.cpp new file mode 100644 -index 00000000000..c30bf3bf416 +index 00000000000..4c5fb862661 --- /dev/null +++ b/src/hotspot/cpu/loongarch/vm_version_loongarch.cpp -@@ -0,0 +1,514 @@ +@@ -0,0 +1,517 @@ +/* + * Copyright (c) 1997, 2014, Oracle and/or its affiliates. All rights reserved. -+ * Copyright (c) 2015, 2023, Loongson Technology. All rights reserved. ++ * Copyright (c) 2015, 2024, Loongson Technology. All rights reserved. + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. + * + * This code is free software; you can redistribute it and/or modify it @@ -70149,6 +70209,9 @@ index 00000000000..c30bf3bf416 + FLAG_SET_DEFAULT(UsePoly1305Intrinsics, true); + } + ++ if (FLAG_IS_DEFAULT(UseVectorizedHashCodeIntrinsic)) { ++ FLAG_SET_DEFAULT(UseVectorizedHashCodeIntrinsic, true); ++ } +#endif + + // This machine allows unaligned memory accesses @@ -70249,13 +70312,13 @@ index 00000000000..c30bf3bf416 +} diff --git a/src/hotspot/cpu/loongarch/vm_version_loongarch.hpp b/src/hotspot/cpu/loongarch/vm_version_loongarch.hpp new file mode 100644 -index 00000000000..04bd6942dc2 +index 00000000000..9f4d46472ab --- /dev/null +++ b/src/hotspot/cpu/loongarch/vm_version_loongarch.hpp -@@ -0,0 +1,308 @@ +@@ -0,0 +1,309 @@ +/* + * Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved. -+ * Copyright (c) 2015, 2023, Loongson Technology. All rights reserved. ++ * Copyright (c) 2015, 2024, Loongson Technology. All rights reserved. + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. + * + * This code is free software; you can redistribute it and/or modify it @@ -70550,6 +70613,7 @@ index 00000000000..04bd6942dc2 + static bool supports_lam_bh() { return _features & CPU_LAM_BH; } + static bool supports_lamcas() { return _features & CPU_LAMCAS; } + ++ // LoongArch64 supports fast class initialization checks + static bool supports_fast_class_init_checks() { return true; } + static bool supports_float16() { return UseLSX; } + constexpr static bool supports_stack_watermark_barrier() { return true; } @@ -70824,13 +70888,13 @@ index 00000000000..03b53dc81f8 +#endif // CPU_LOONGARCH_VMSTORAGE_LOONGARCH_INLINE_HPP diff --git a/src/hotspot/cpu/loongarch/vtableStubs_loongarch_64.cpp b/src/hotspot/cpu/loongarch/vtableStubs_loongarch_64.cpp new file mode 100644 -index 00000000000..ab12021832d +index 00000000000..772e5c02c9c --- /dev/null +++ b/src/hotspot/cpu/loongarch/vtableStubs_loongarch_64.cpp @@ -0,0 +1,312 @@ +/* + * Copyright (c) 2003, 2014, Oracle and/or its affiliates. All rights reserved. -+ * Copyright (c) 2015, 2023, Loongson Technology. All rights reserved. ++ * Copyright (c) 2015, 2024, Loongson Technology. All rights reserved. + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. + * + * This code is free software; you can redistribute it and/or modify it @@ -70855,10 +70919,10 @@ index 00000000000..ab12021832d + +#include "precompiled.hpp" +#include "asm/macroAssembler.hpp" ++#include "code/compiledIC.hpp" +#include "code/vtableStubs.hpp" +#include "interp_masm_loongarch.hpp" +#include "memory/resourceArea.hpp" -+#include "oops/compiledICHolder.hpp" +#include "oops/klass.inline.hpp" +#include "oops/klassVtable.hpp" +#include "runtime/sharedRuntime.hpp" @@ -71023,14 +71087,14 @@ index 00000000000..ab12021832d + } +#endif // PRODUCT + -+ const Register holder_klass_reg = T1; // declaring interface klass (DECC) ++ const Register holder_klass_reg = T1; // declaring interface klass (DEFC) + const Register resolved_klass_reg = Rmethod; // resolved interface klass (REFC) -+ const Register icholder_reg = T1; ++ const Register icdata_reg = T1; + + Label L_no_such_interface; + -+ __ ld_d(resolved_klass_reg, Address(icholder_reg, CompiledICHolder::holder_klass_offset())); -+ __ ld_d(holder_klass_reg, Address(icholder_reg, CompiledICHolder::holder_metadata_offset())); ++ __ ld_d(resolved_klass_reg, Address(icdata_reg, CompiledICData::itable_refc_klass_offset())); ++ __ ld_d(holder_klass_reg, Address(icdata_reg, CompiledICData::itable_defc_klass_offset())); + + // get receiver klass (also an implicit null-check) + address npe_addr = __ pc(); @@ -71141,7 +71205,7 @@ index 00000000000..ab12021832d + return icache_line_size; +} diff --git a/src/hotspot/os/linux/os_linux.cpp b/src/hotspot/os/linux/os_linux.cpp -index 3fc025e5100..3e421c369d7 100644 +index c51aeb0ae17..dbd6a2d96a8 100644 --- a/src/hotspot/os/linux/os_linux.cpp +++ b/src/hotspot/os/linux/os_linux.cpp @@ -23,6 +23,12 @@ @@ -71156,8 +71220,8 @@ index 3fc025e5100..3e421c369d7 100644 + // no precompiled headers #include "classfile/vmSymbols.hpp" - #include "code/icBuffer.hpp" -@@ -2249,6 +2255,12 @@ bool os::Linux::query_process_memory_info(os::Linux::meminfo_t* info) { + #include "code/vtableStubs.hpp" +@@ -2318,6 +2324,12 @@ bool os::Linux::query_process_memory_info(os::Linux::meminfo_t* info) { return false; } @@ -71170,7 +71234,7 @@ index 3fc025e5100..3e421c369d7 100644 #ifdef __GLIBC__ // For Glibc, print a one-liner with the malloc tunables. // Most important and popular is MALLOC_ARENA_MAX, but we are -@@ -2465,7 +2477,7 @@ void os::print_memory_info(outputStream* st) { +@@ -2536,7 +2548,7 @@ void os::print_memory_info(outputStream* st) { // before "flags" so if we find a second "model name", then the // "flags" field is considered missing. static bool print_model_name_and_flags(outputStream* st, char* buf, size_t buflen) { @@ -71179,7 +71243,7 @@ index 3fc025e5100..3e421c369d7 100644 // Other platforms have less repetitive cpuinfo files FILE *fp = os::fopen("/proc/cpuinfo", "r"); if (fp) { -@@ -2577,7 +2589,7 @@ void os::jfr_report_memory_info() { +@@ -2648,7 +2660,7 @@ void os::jfr_report_memory_info() { #endif // INCLUDE_JFR @@ -71188,7 +71252,7 @@ index 3fc025e5100..3e421c369d7 100644 const char* search_string = "model name"; #elif defined(M68K) const char* search_string = "CPU"; -@@ -4401,6 +4413,44 @@ void os::Linux::numa_init() { +@@ -4511,6 +4523,44 @@ void os::Linux::numa_init() { // If there's only one node (they start from 0) or if the process // is bound explicitly to a single node using membind, disable NUMA UseNUMA = false; @@ -71234,7 +71298,7 @@ index 3fc025e5100..3e421c369d7 100644 LogTarget(Info,os) log; LogStream ls(log); diff --git a/src/hotspot/os/linux/os_linux.hpp b/src/hotspot/os/linux/os_linux.hpp -index 4b2ccf8e370..5eaa98414ca 100644 +index 6b902e82802..0f43a32ea44 100644 --- a/src/hotspot/os/linux/os_linux.hpp +++ b/src/hotspot/os/linux/os_linux.hpp @@ -22,6 +22,12 @@ @@ -71250,7 +71314,7 @@ index 4b2ccf8e370..5eaa98414ca 100644 #ifndef OS_LINUX_OS_LINUX_HPP #define OS_LINUX_OS_LINUX_HPP -@@ -190,6 +196,8 @@ class os::Linux { +@@ -192,6 +198,8 @@ class os::Linux { // none present @@ -71260,7 +71324,7 @@ index 4b2ccf8e370..5eaa98414ca 100644 static void numa_init(); diff --git a/src/hotspot/os/linux/systemMemoryBarrier_linux.cpp b/src/hotspot/os/linux/systemMemoryBarrier_linux.cpp -index 446449a40e0..0f70070713f 100644 +index 892d825b40c..a9130b3399a 100644 --- a/src/hotspot/os/linux/systemMemoryBarrier_linux.cpp +++ b/src/hotspot/os/linux/systemMemoryBarrier_linux.cpp @@ -22,6 +22,12 @@ @@ -71275,7 +71339,7 @@ index 446449a40e0..0f70070713f 100644 + #include "precompiled.hpp" #include "logging/log.hpp" - #include "runtime/os.hpp" + #include "os_linux.hpp" @@ -43,6 +49,8 @@ #define SYS_membarrier 283 #elif defined(ALPHA) @@ -72421,13 +72485,13 @@ index 00000000000..2d096943ae8 +#endif // OS_CPU_LINUX_LOONGARCH_ORDERACCESS_LINUX_LOONGARCH_HPP diff --git a/src/hotspot/os_cpu/linux_loongarch/os_linux_loongarch.cpp b/src/hotspot/os_cpu/linux_loongarch/os_linux_loongarch.cpp new file mode 100644 -index 00000000000..31bfcba8db6 +index 00000000000..cae2e474aac --- /dev/null +++ b/src/hotspot/os_cpu/linux_loongarch/os_linux_loongarch.cpp -@@ -0,0 +1,491 @@ +@@ -0,0 +1,490 @@ +/* + * Copyright (c) 1999, 2014, Oracle and/or its affiliates. All rights reserved. -+ * Copyright (c) 2015, 2023, Loongson Technology. All rights reserved. ++ * Copyright (c) 2015, 2024, Loongson Technology. All rights reserved. + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. + * + * This code is free software; you can redistribute it and/or modify it @@ -72455,7 +72519,6 @@ index 00000000000..31bfcba8db6 +#include "classfile/classLoader.hpp" +#include "classfile/systemDictionary.hpp" +#include "classfile/vmSymbols.hpp" -+#include "code/icBuffer.hpp" +#include "code/vtableStubs.hpp" +#include "interpreter/interpreter.hpp" +#include "memory/allocation.inline.hpp" @@ -73238,7 +73301,7 @@ index 00000000000..3711a7036a1 + HWCAP_LOONGARCH_LBT_MIPS); +} diff --git a/src/hotspot/share/adlc/formssel.cpp b/src/hotspot/share/adlc/formssel.cpp -index 8e2366e5d09..38e5fd7b2c6 100644 +index ecbf472c59e..8e18d82d45e 100644 --- a/src/hotspot/share/adlc/formssel.cpp +++ b/src/hotspot/share/adlc/formssel.cpp @@ -22,6 +22,12 @@ @@ -73254,7 +73317,7 @@ index 8e2366e5d09..38e5fd7b2c6 100644 // FORMS.CPP - Definitions for ADL Parser Forms Classes #include "adlc.hpp" -@@ -4174,6 +4180,7 @@ bool MatchRule::is_ideal_membar() const { +@@ -4175,6 +4181,7 @@ bool MatchRule::is_ideal_membar() const { !strcmp(_opType,"MemBarVolatile") || !strcmp(_opType,"MemBarCPUOrder") || !strcmp(_opType,"MemBarStoreStore") || @@ -73451,7 +73514,7 @@ index 6f527135fbe..2e2910bdb5c 100644 void call_runtime_leaf(address routine, LIR_Opr tmp, LIR_Opr result, LIR_OprList* arguments) { append(new LIR_OpRTCall(routine, tmp, result, arguments)); diff --git a/src/hotspot/share/c1/c1_LinearScan.cpp b/src/hotspot/share/c1/c1_LinearScan.cpp -index 7e46f9d5603..97f98d5a5e0 100644 +index a4d955e52a0..79d0d03e961 100644 --- a/src/hotspot/share/c1/c1_LinearScan.cpp +++ b/src/hotspot/share/c1/c1_LinearScan.cpp @@ -22,6 +22,12 @@ @@ -73538,7 +73601,7 @@ index 7e46f9d5603..97f98d5a5e0 100644 } } diff --git a/src/hotspot/share/code/vtableStubs.cpp b/src/hotspot/share/code/vtableStubs.cpp -index eed3dc8e787..c8b58dd459c 100644 +index 5a54426d6a4..d23c220b3e0 100644 --- a/src/hotspot/share/code/vtableStubs.cpp +++ b/src/hotspot/share/code/vtableStubs.cpp @@ -22,6 +22,12 @@ @@ -73567,7 +73630,7 @@ index eed3dc8e787..c8b58dd459c 100644 #else // These values are good for the non-PRODUCT case (when tracing can be switched on). diff --git a/src/hotspot/share/gc/g1/g1Arguments.cpp b/src/hotspot/share/gc/g1/g1Arguments.cpp -index b8a7c677f7f..e02033a1ff5 100644 +index 5f022bfdc3c..2fed0abbc93 100644 --- a/src/hotspot/share/gc/g1/g1Arguments.cpp +++ b/src/hotspot/share/gc/g1/g1Arguments.cpp @@ -23,6 +23,12 @@ @@ -73583,7 +73646,7 @@ index b8a7c677f7f..e02033a1ff5 100644 #include "precompiled.hpp" #include "cds/cdsConfig.hpp" #include "gc/g1/g1Arguments.hpp" -@@ -168,6 +174,20 @@ void G1Arguments::initialize_card_set_configuration() { +@@ -162,6 +168,20 @@ void G1Arguments::initialize_card_set_configuration() { void G1Arguments::initialize() { GCArguments::initialize(); assert(UseG1GC, "Error"); @@ -73830,7 +73893,7 @@ index f917a6c3e7b..a851a673f98 100644 ZStoreBarrierEntry _buffer[_buffer_length]; diff --git a/src/hotspot/share/interpreter/interpreterRuntime.cpp b/src/hotspot/share/interpreter/interpreterRuntime.cpp -index 70439459d35..a9ebc001900 100644 +index ff7c453e01e..952fbc80705 100644 --- a/src/hotspot/share/interpreter/interpreterRuntime.cpp +++ b/src/hotspot/share/interpreter/interpreterRuntime.cpp @@ -22,6 +22,12 @@ @@ -73846,7 +73909,7 @@ index 70439459d35..a9ebc001900 100644 #include "precompiled.hpp" #include "classfile/javaClasses.inline.hpp" #include "classfile/symbolTable.hpp" -@@ -1461,7 +1467,7 @@ JRT_ENTRY(void, InterpreterRuntime::prepare_native_call(JavaThread* current, Met +@@ -1466,7 +1472,7 @@ JRT_ENTRY(void, InterpreterRuntime::prepare_native_call(JavaThread* current, Met // preparing the same method will be sure to see non-null entry & mirror. JRT_END @@ -73910,28 +73973,6 @@ index bcccff2fe82..5c836ab5114 100644 #ifdef ARM32 void generate_math_runtime_call(AbstractInterpreter::MethodKind kind); -diff --git a/src/hotspot/share/jfr/support/jfrNativeLibraryLoadEvent.cpp b/src/hotspot/share/jfr/support/jfrNativeLibraryLoadEvent.cpp -index c26592763d4..da669ee4354 100644 ---- a/src/hotspot/share/jfr/support/jfrNativeLibraryLoadEvent.cpp -+++ b/src/hotspot/share/jfr/support/jfrNativeLibraryLoadEvent.cpp -@@ -105,13 +105,15 @@ static void commit(HelperType& helper) { - assert(thread != nullptr, "invariant"); - if (thread->is_Java_thread()) { - JavaThread* jt = JavaThread::cast(thread); -- if (jt->thread_state() != _thread_in_vm) { -- assert(jt->thread_state() == _thread_in_native, "invariant"); -+ if (jt->thread_state() == _thread_in_native) { - // For a JavaThread to take a JFR stacktrace, it must be in _thread_in_vm. Can safepoint here. - ThreadInVMfromNative transition(jt); - event.commit(); - return; - } -+ // If a thread comes here still _thread_in_Java, which can happen for example -+ // when loading the disassembler library in response to traps in JIT code - all is ok. -+ // Since there is no ljf, an event will be committed without a stacktrace. - } - event.commit(); - } diff --git a/src/hotspot/share/jfr/utilities/jfrBigEndian.hpp b/src/hotspot/share/jfr/utilities/jfrBigEndian.hpp index 7661b35863c..ad281cad645 100644 --- a/src/hotspot/share/jfr/utilities/jfrBigEndian.hpp @@ -73959,7 +74000,7 @@ index 7661b35863c..ad281cad645 100644 #else #warning "Unconfigured platform" diff --git a/src/hotspot/share/jvmci/vmStructs_jvmci.cpp b/src/hotspot/share/jvmci/vmStructs_jvmci.cpp -index bac9a786fd9..0bb983e6246 100644 +index f47c4cdd940..991c81b7999 100644 --- a/src/hotspot/share/jvmci/vmStructs_jvmci.cpp +++ b/src/hotspot/share/jvmci/vmStructs_jvmci.cpp @@ -22,6 +22,12 @@ @@ -73974,8 +74015,8 @@ index bac9a786fd9..0bb983e6246 100644 + #include "precompiled.hpp" #include "code/codeCache.hpp" - #include "compiler/compileBroker.hpp" -@@ -871,6 +877,17 @@ + #include "code/compiledIC.hpp" +@@ -880,6 +886,17 @@ #endif @@ -74029,7 +74070,7 @@ index c7590861032..c192d19e849 100644 // that stub out arch-specific methods. Some compilers are smart enough // to figure out the argument is always null and then warn about it. diff --git a/src/hotspot/share/opto/classes.hpp b/src/hotspot/share/opto/classes.hpp -index 7d1a2cd1db0..f936dd8e748 100644 +index f1da18f464e..b9582858cdb 100644 --- a/src/hotspot/share/opto/classes.hpp +++ b/src/hotspot/share/opto/classes.hpp @@ -22,6 +22,12 @@ @@ -74054,7 +74095,7 @@ index 7d1a2cd1db0..f936dd8e748 100644 macro(MinI) macro(MinL) diff --git a/src/hotspot/share/opto/compile.cpp b/src/hotspot/share/opto/compile.cpp -index 8a5e98eda92..a572e02bb9a 100644 +index 83b922492b3..7c27e3d62b8 100644 --- a/src/hotspot/share/opto/compile.cpp +++ b/src/hotspot/share/opto/compile.cpp @@ -22,6 +22,12 @@ @@ -74070,7 +74111,7 @@ index 8a5e98eda92..a572e02bb9a 100644 #include "precompiled.hpp" #include "asm/macroAssembler.hpp" #include "asm/macroAssembler.inline.hpp" -@@ -3772,6 +3778,7 @@ void Compile::final_graph_reshaping_main_switch(Node* n, Final_Reshape_Counts& f +@@ -3818,6 +3824,7 @@ void Compile::final_graph_reshaping_main_switch(Node* n, Final_Reshape_Counts& f n->set_req(MemBarNode::Precedent, top()); } break; @@ -74079,7 +74120,7 @@ index 8a5e98eda92..a572e02bb9a 100644 if (n->as_MemBar()->trailing_load() && n->req() > MemBarNode::Precedent) { // At parse time, the trailing MemBarAcquire for a volatile load diff --git a/src/hotspot/share/opto/memnode.cpp b/src/hotspot/share/opto/memnode.cpp -index c402a240acb..de8f6835ae6 100644 +index 010a13a07ba..09ff523d5fd 100644 --- a/src/hotspot/share/opto/memnode.cpp +++ b/src/hotspot/share/opto/memnode.cpp @@ -22,6 +22,12 @@ @@ -74095,7 +74136,7 @@ index c402a240acb..de8f6835ae6 100644 #include "precompiled.hpp" #include "classfile/javaClasses.hpp" #include "compiler/compileLog.hpp" -@@ -3327,6 +3333,7 @@ MemBarNode* MemBarNode::make(Compile* C, int opcode, int atp, Node* pn) { +@@ -3353,6 +3359,7 @@ MemBarNode* MemBarNode::make(Compile* C, int opcode, int atp, Node* pn) { case Op_MemBarReleaseLock: return new MemBarReleaseLockNode(C, atp, pn); case Op_MemBarVolatile: return new MemBarVolatileNode(C, atp, pn); case Op_MemBarCPUOrder: return new MemBarCPUOrderNode(C, atp, pn); @@ -74104,7 +74145,7 @@ index c402a240acb..de8f6835ae6 100644 case Op_Initialize: return new InitializeNode(C, atp, pn); default: ShouldNotReachHere(); return nullptr; diff --git a/src/hotspot/share/opto/memnode.hpp b/src/hotspot/share/opto/memnode.hpp -index 85f4380188d..0ca6096e59f 100644 +index e0f5a437413..65241574207 100644 --- a/src/hotspot/share/opto/memnode.hpp +++ b/src/hotspot/share/opto/memnode.hpp @@ -22,6 +22,12 @@ @@ -74120,7 +74161,7 @@ index 85f4380188d..0ca6096e59f 100644 #ifndef SHARE_OPTO_MEMNODE_HPP #define SHARE_OPTO_MEMNODE_HPP -@@ -1292,6 +1298,14 @@ class MemBarCPUOrderNode: public MemBarNode { +@@ -1299,6 +1305,14 @@ class MemBarCPUOrderNode: public MemBarNode { virtual uint ideal_reg() const { return 0; } // not matched in the AD file }; @@ -74136,7 +74177,7 @@ index 85f4380188d..0ca6096e59f 100644 public: OnSpinWaitNode(Compile* C, int alias_idx, Node* precedent) diff --git a/src/hotspot/share/opto/output.cpp b/src/hotspot/share/opto/output.cpp -index 9481b91ce39..e6fe6a706cc 100644 +index 640a24693de..6e6820beb2e 100644 --- a/src/hotspot/share/opto/output.cpp +++ b/src/hotspot/share/opto/output.cpp @@ -22,6 +22,12 @@ @@ -74176,7 +74217,7 @@ index 9481b91ce39..e6fe6a706cc 100644 // Above we only verified that there is enough space in the instruction section. // However, the instruction may emit stubs that cause code buffer expansion. diff --git a/src/hotspot/share/runtime/arguments.cpp b/src/hotspot/share/runtime/arguments.cpp -index 250bef15869..1360e72dbbd 100644 +index dfd5eec6b4f..f9109506b93 100644 --- a/src/hotspot/share/runtime/arguments.cpp +++ b/src/hotspot/share/runtime/arguments.cpp @@ -22,6 +22,12 @@ @@ -74192,7 +74233,7 @@ index 250bef15869..1360e72dbbd 100644 #include "precompiled.hpp" #include "cds/cds_globals.hpp" #include "cds/cdsConfig.hpp" -@@ -1844,14 +1850,14 @@ bool Arguments::check_vm_args_consistency() { +@@ -1819,14 +1825,14 @@ bool Arguments::check_vm_args_consistency() { } #endif @@ -74236,7 +74277,7 @@ index 03c0af1a572..7e468def61d 100644 #else frame sender = frame(); diff --git a/src/hotspot/share/runtime/continuationFreezeThaw.cpp b/src/hotspot/share/runtime/continuationFreezeThaw.cpp -index 47906e81f11..3e9ac7a8502 100644 +index c9ddfa900dd..6593a279db7 100644 --- a/src/hotspot/share/runtime/continuationFreezeThaw.cpp +++ b/src/hotspot/share/runtime/continuationFreezeThaw.cpp @@ -22,6 +22,12 @@ @@ -74326,7 +74367,7 @@ index 7b1ad7e17e1..c7a0246e375 100644 // Threads::create_vm() for size checks. Atomic::release_store(&_thread_state, s); diff --git a/src/hotspot/share/runtime/objectMonitor.cpp b/src/hotspot/share/runtime/objectMonitor.cpp -index 2214713aa4b..462e3e8031b 100644 +index 8efd4e5b0c1..85e29eba6e3 100644 --- a/src/hotspot/share/runtime/objectMonitor.cpp +++ b/src/hotspot/share/runtime/objectMonitor.cpp @@ -22,6 +22,12 @@ @@ -74342,7 +74383,7 @@ index 2214713aa4b..462e3e8031b 100644 #include "precompiled.hpp" #include "classfile/vmSymbols.hpp" #include "gc/shared/oopStorage.hpp" -@@ -356,6 +362,9 @@ bool ObjectMonitor::enter(JavaThread* current) { +@@ -421,6 +427,9 @@ bool ObjectMonitor::enter(JavaThread* current) { } assert(owner_raw() != current, "invariant"); @@ -74352,7 +74393,7 @@ index 2214713aa4b..462e3e8031b 100644 assert(_succ != current, "invariant"); assert(!SafepointSynchronize::is_at_safepoint(), "invariant"); assert(current->thread_state() != _thread_blocked, "invariant"); -@@ -706,6 +715,7 @@ void ObjectMonitor::EnterI(JavaThread* current) { +@@ -771,6 +780,7 @@ void ObjectMonitor::EnterI(JavaThread* current) { } // The Spin failed -- Enqueue and park the thread ... @@ -74361,7 +74402,7 @@ index 2214713aa4b..462e3e8031b 100644 assert(owner_raw() != current, "invariant"); assert(_Responsible != current, "invariant"); diff --git a/src/hotspot/share/runtime/os.cpp b/src/hotspot/share/runtime/os.cpp -index 0eb4015a246..9aa9d7ef86f 100644 +index 5d6c1fa69ca..808423499d8 100644 --- a/src/hotspot/share/runtime/os.cpp +++ b/src/hotspot/share/runtime/os.cpp @@ -22,6 +22,12 @@ @@ -74377,7 +74418,7 @@ index 0eb4015a246..9aa9d7ef86f 100644 #include "precompiled.hpp" #include "cds/cdsConfig.hpp" #include "classfile/javaClasses.hpp" -@@ -1308,7 +1314,8 @@ bool os::is_first_C_frame(frame* fr) { +@@ -1314,7 +1320,8 @@ bool os::is_first_C_frame(frame* fr) { if ((uintptr_t)fr->sender_sp() == (uintptr_t)-1 || is_pointer_bad(fr->sender_sp())) return true; uintptr_t old_fp = (uintptr_t)fr->link_or_null(); @@ -74429,7 +74470,7 @@ index fac76262f3c..f41cf843d31 100644 static double __kernel_sin(double x, double y, int iy) { diff --git a/src/hotspot/share/runtime/synchronizer.cpp b/src/hotspot/share/runtime/synchronizer.cpp -index 34eafb01c6d..c663e01e221 100644 +index 6498330b190..55e53ecb219 100644 --- a/src/hotspot/share/runtime/synchronizer.cpp +++ b/src/hotspot/share/runtime/synchronizer.cpp @@ -22,6 +22,12 @@ @@ -74445,7 +74486,7 @@ index 34eafb01c6d..c663e01e221 100644 #include "precompiled.hpp" #include "classfile/vmSymbols.hpp" #include "gc/shared/collectedHeap.hpp" -@@ -493,7 +499,7 @@ void ObjectSynchronizer::handle_sync_on_value_based_class(Handle obj, JavaThread +@@ -509,7 +515,7 @@ void ObjectSynchronizer::handle_sync_on_value_based_class(Handle obj, JavaThread } static bool useHeavyMonitors() { @@ -74455,7 +74496,7 @@ index 34eafb01c6d..c663e01e221 100644 #else return false; diff --git a/src/hotspot/share/runtime/vmStructs.cpp b/src/hotspot/share/runtime/vmStructs.cpp -index 54d591ff141..425daacb947 100644 +index 3ddb9619d72..48c207d3b91 100644 --- a/src/hotspot/share/runtime/vmStructs.cpp +++ b/src/hotspot/share/runtime/vmStructs.cpp @@ -22,6 +22,12 @@ @@ -74471,7 +74512,7 @@ index 54d591ff141..425daacb947 100644 #include "precompiled.hpp" #include "cds/filemap.hpp" #include "ci/ciField.hpp" -@@ -1512,6 +1518,7 @@ +@@ -1509,6 +1515,7 @@ declare_c2_type(StoreFenceNode, MemBarNode) \ declare_c2_type(MemBarVolatileNode, MemBarNode) \ declare_c2_type(MemBarCPUOrderNode, MemBarNode) \ @@ -74554,7 +74595,7 @@ index 500e312b2f3..7fe68049d17 100644 return FALLBACK; // fallback linker } diff --git a/src/java.base/share/classes/jdk/internal/foreign/abi/AbstractLinker.java b/src/java.base/share/classes/jdk/internal/foreign/abi/AbstractLinker.java -index d90e5acd259..10c77f1de73 100644 +index 12c9a2dfaa2..81fef13d543 100644 --- a/src/java.base/share/classes/jdk/internal/foreign/abi/AbstractLinker.java +++ b/src/java.base/share/classes/jdk/internal/foreign/abi/AbstractLinker.java @@ -22,6 +22,12 @@ @@ -74587,7 +74628,7 @@ index d90e5acd259..10c77f1de73 100644 public interface UpcallStubFactory { diff --git a/src/java.base/share/classes/jdk/internal/foreign/abi/SharedUtils.java b/src/java.base/share/classes/jdk/internal/foreign/abi/SharedUtils.java -index 5f625242182..df1b9a65a53 100644 +index 83698398eda..a8e88da3676 100644 --- a/src/java.base/share/classes/jdk/internal/foreign/abi/SharedUtils.java +++ b/src/java.base/share/classes/jdk/internal/foreign/abi/SharedUtils.java @@ -22,6 +22,12 @@ @@ -74611,7 +74652,7 @@ index 5f625242182..df1b9a65a53 100644 import jdk.internal.foreign.abi.ppc64.aix.AixPPC64Linker; import jdk.internal.foreign.abi.ppc64.linux.LinuxPPC64Linker; import jdk.internal.foreign.abi.ppc64.linux.LinuxPPC64leLinker; -@@ -250,6 +257,7 @@ public static Linker getSystemLinker() { +@@ -251,6 +258,7 @@ public static Linker getSystemLinker() { case LINUX_PPC_64_LE -> LinuxPPC64leLinker.getInstance(); case LINUX_RISCV_64 -> LinuxRISCV64Linker.getInstance(); case LINUX_S390 -> LinuxS390Linker.getInstance(); @@ -78832,7 +78873,7 @@ index 5968b7221c7..6bcdf4d189d 100644 * @library /test/lib / * @run driver compiler.c2.irTests.TestVectorizationNotRun diff --git a/test/hotspot/jtreg/compiler/c2/irTests/TestVectorizeTypeConversion.java b/test/hotspot/jtreg/compiler/c2/irTests/TestVectorizeTypeConversion.java -index 67c26ecbddf..ba69c910ce6 100644 +index 899be4bbc9c..3aefead5d13 100644 --- a/test/hotspot/jtreg/compiler/c2/irTests/TestVectorizeTypeConversion.java +++ b/test/hotspot/jtreg/compiler/c2/irTests/TestVectorizeTypeConversion.java @@ -21,6 +21,12 @@ @@ -78884,7 +78925,7 @@ index ebe3fe63ccf..04ea3cccdef 100644 * @run driver compiler.c2.irTests.TestVectorizeURShiftSubword */ diff --git a/test/hotspot/jtreg/compiler/cpuflags/TestAESIntrinsicsOnSupportedConfig.java b/test/hotspot/jtreg/compiler/cpuflags/TestAESIntrinsicsOnSupportedConfig.java -index 4c56daebfb8..92836130408 100644 +index ac3a6d9a8c6..c17598902ff 100644 --- a/test/hotspot/jtreg/compiler/cpuflags/TestAESIntrinsicsOnSupportedConfig.java +++ b/test/hotspot/jtreg/compiler/cpuflags/TestAESIntrinsicsOnSupportedConfig.java @@ -21,12 +21,18 @@ @@ -78908,7 +78949,7 @@ index 4c56daebfb8..92836130408 100644 * @run driver jdk.test.lib.helpers.ClassFileInstaller jdk.test.whitebox.WhiteBox * @run main/othervm/timeout=600 -Xbootclasspath/a:. diff --git a/test/hotspot/jtreg/compiler/cpuflags/TestAESIntrinsicsOnUnsupportedConfig.java b/test/hotspot/jtreg/compiler/cpuflags/TestAESIntrinsicsOnUnsupportedConfig.java -index 03016ea3dd6..62ce6c1a7a5 100644 +index fdc8f63f9e0..993cf68d011 100644 --- a/test/hotspot/jtreg/compiler/cpuflags/TestAESIntrinsicsOnUnsupportedConfig.java +++ b/test/hotspot/jtreg/compiler/cpuflags/TestAESIntrinsicsOnUnsupportedConfig.java @@ -21,6 +21,12 @@ @@ -78933,33 +78974,6 @@ index 03016ea3dd6..62ce6c1a7a5 100644 * @requires vm.compiler1.enabled | !vm.graal.enabled * @run driver jdk.test.lib.helpers.ClassFileInstaller jdk.test.whitebox.WhiteBox * @run main/othervm -Xbootclasspath/a:. -XX:+UnlockDiagnosticVMOptions -diff --git a/test/hotspot/jtreg/compiler/intrinsics/TestBitShuffleOpers.java b/test/hotspot/jtreg/compiler/intrinsics/TestBitShuffleOpers.java -index 9a7e0c6b9f2..847ed1e7b51 100644 ---- a/test/hotspot/jtreg/compiler/intrinsics/TestBitShuffleOpers.java -+++ b/test/hotspot/jtreg/compiler/intrinsics/TestBitShuffleOpers.java -@@ -21,6 +21,12 @@ - * questions. - */ - -+/* -+ * This file has been modified by Loongson Technology in 2023, These -+ * modifications are Copyright (c) 2023, Loongson Technology, and are made -+ * available on the same license terms set forth above. -+ */ -+ - /** - * @test - * @bug 8283894 -@@ -31,7 +37,8 @@ - * (vm.cpu.features ~= ".*bmi2.*" & vm.cpu.features ~= ".*bmi1.*" & - * vm.cpu.features ~= ".*sse2.*")) | - * (os.arch=="aarch64" & vm.cpu.features ~= ".*svebitperm.*") | -- * (os.arch=="riscv64" & vm.cpu.features ~= ".*v,.*")) -+ * (os.arch=="riscv64" & vm.cpu.features ~= ".*v,.*") | -+ * (os.arch=="loongarch64")) - * @library /test/lib / - * @run driver compiler.intrinsics.TestBitShuffleOpers - */ diff --git a/test/hotspot/jtreg/compiler/intrinsics/TestCompareUnsigned.java b/test/hotspot/jtreg/compiler/intrinsics/TestCompareUnsigned.java index 99a594ade69..61fa03381c5 100644 --- a/test/hotspot/jtreg/compiler/intrinsics/TestCompareUnsigned.java @@ -79163,10 +79177,10 @@ index 55f8375332d..ff5d931ec51 100644 // the ChaCha20 known answer tests in // com/sun/crypto/provider/Cipher are sufficient. diff --git a/test/hotspot/jtreg/compiler/intrinsics/float16/Binary16Conversion.java b/test/hotspot/jtreg/compiler/intrinsics/float16/Binary16Conversion.java -index 0541121c127..d9fe8c91dc4 100644 +index ab4d8ff8bb7..9184cd8c005 100644 --- a/test/hotspot/jtreg/compiler/intrinsics/float16/Binary16Conversion.java +++ b/test/hotspot/jtreg/compiler/intrinsics/float16/Binary16Conversion.java -@@ -21,11 +21,17 @@ +@@ -21,12 +21,18 @@ * questions. */ @@ -79180,16 +79194,17 @@ index 0541121c127..d9fe8c91dc4 100644 * @test * @bug 8289551 8302976 * @summary Verify conversion between float and the binary16 format -- * @requires (vm.cpu.features ~= ".*avx512vl.*" | vm.cpu.features ~= ".*f16c.*") | os.arch=="aarch64" -+ * @requires (vm.cpu.features ~= ".*avx512vl.*" | vm.cpu.features ~= ".*f16c.*") | os.arch=="aarch64" | os.arch=="loongarch64" + * @requires (vm.cpu.features ~= ".*avx512vl.*" | vm.cpu.features ~= ".*f16c.*") | os.arch=="aarch64" +- * | (os.arch == "riscv64" & vm.cpu.features ~= ".*zfh,.*") ++ * | (os.arch == "riscv64" & vm.cpu.features ~= ".*zfh,.*") | os.arch=="loongarch64" * @requires vm.compiler1.enabled & vm.compiler2.enabled * @requires vm.compMode != "Xcomp" * @comment default run diff --git a/test/hotspot/jtreg/compiler/intrinsics/float16/Binary16ConversionNaN.java b/test/hotspot/jtreg/compiler/intrinsics/float16/Binary16ConversionNaN.java -index 38060dfb504..151caa94346 100644 +index f549c1ae670..7046f8ac771 100644 --- a/test/hotspot/jtreg/compiler/intrinsics/float16/Binary16ConversionNaN.java +++ b/test/hotspot/jtreg/compiler/intrinsics/float16/Binary16ConversionNaN.java -@@ -21,11 +21,17 @@ +@@ -21,12 +21,18 @@ * questions. */ @@ -79203,16 +79218,17 @@ index 38060dfb504..151caa94346 100644 * @test * @bug 8289551 8302976 * @summary Verify NaN sign and significand bits are preserved across conversions -- * @requires (vm.cpu.features ~= ".*avx512vl.*" | vm.cpu.features ~= ".*f16c.*") | os.arch=="aarch64" -+ * @requires (vm.cpu.features ~= ".*avx512vl.*" | vm.cpu.features ~= ".*f16c.*") | os.arch=="aarch64" | os.arch=="loongarch64" + * @requires (vm.cpu.features ~= ".*avx512vl.*" | vm.cpu.features ~= ".*f16c.*") | os.arch=="aarch64" +- * | (os.arch == "riscv64" & vm.cpu.features ~= ".*zfh,.*") ++ * | (os.arch == "riscv64" & vm.cpu.features ~= ".*zfh,.*") | os.arch=="loongarch64" * @requires vm.compiler1.enabled & vm.compiler2.enabled * @requires vm.compMode != "Xcomp" * @library /test/lib / diff --git a/test/hotspot/jtreg/compiler/intrinsics/float16/TestAllFloat16ToFloat.java b/test/hotspot/jtreg/compiler/intrinsics/float16/TestAllFloat16ToFloat.java -index 492901f0046..e95554fa944 100644 +index 937e17f8fca..f3eb1de4182 100644 --- a/test/hotspot/jtreg/compiler/intrinsics/float16/TestAllFloat16ToFloat.java +++ b/test/hotspot/jtreg/compiler/intrinsics/float16/TestAllFloat16ToFloat.java -@@ -21,11 +21,17 @@ +@@ -21,12 +21,18 @@ * questions. */ @@ -79226,16 +79242,17 @@ index 492901f0046..e95554fa944 100644 * @test * @bug 8302976 * @summary Verify conversion between float and the binary16 format -- * @requires (vm.cpu.features ~= ".*avx512vl.*" | vm.cpu.features ~= ".*f16c.*") | os.arch == "aarch64" -+ * @requires (vm.cpu.features ~= ".*avx512vl.*" | vm.cpu.features ~= ".*f16c.*") | os.arch == "aarch64" | os.arch == "loongarch64" + * @requires (vm.cpu.features ~= ".*avx512vl.*" | vm.cpu.features ~= ".*f16c.*") | os.arch == "aarch64" +- * | (os.arch == "riscv64" & vm.cpu.features ~= ".*zfh,.*") ++ * | (os.arch == "riscv64" & vm.cpu.features ~= ".*zfh,.*") | os.arch == "loongarch64" * @requires vm.compiler1.enabled & vm.compiler2.enabled * @requires vm.compMode != "Xcomp" * @comment default run: diff --git a/test/hotspot/jtreg/compiler/intrinsics/float16/TestConstFloat16ToFloat.java b/test/hotspot/jtreg/compiler/intrinsics/float16/TestConstFloat16ToFloat.java -index b4ba578c9f2..27e6b86abe2 100644 +index f58cf618c1c..bdb3a27f857 100644 --- a/test/hotspot/jtreg/compiler/intrinsics/float16/TestConstFloat16ToFloat.java +++ b/test/hotspot/jtreg/compiler/intrinsics/float16/TestConstFloat16ToFloat.java -@@ -21,11 +21,17 @@ +@@ -21,12 +21,18 @@ * questions. */ @@ -79249,8 +79266,9 @@ index b4ba578c9f2..27e6b86abe2 100644 * @test * @bug 8302976 * @summary Verify conversion cons between float and the binary16 format -- * @requires (vm.cpu.features ~= ".*avx512vl.*" | vm.cpu.features ~= ".*f16c.*") | os.arch=="aarch64" -+ * @requires (vm.cpu.features ~= ".*avx512vl.*" | vm.cpu.features ~= ".*f16c.*") | os.arch=="aarch64" | os.arch == "loongarch64" + * @requires (vm.cpu.features ~= ".*avx512vl.*" | vm.cpu.features ~= ".*f16c.*") | os.arch=="aarch64" +- * | (os.arch == "riscv64" & vm.cpu.features ~= ".*zfh,.*") ++ * | (os.arch == "riscv64" & vm.cpu.features ~= ".*zfh,.*") | os.arch == "loongarch64" * @requires vm.compiler1.enabled & vm.compiler2.enabled * @requires vm.compMode != "Xcomp" * @comment default run: @@ -80206,7 +80224,7 @@ index 00000000000..4c76868453a + +} diff --git a/test/hotspot/jtreg/compiler/lib/ir_framework/IRNode.java b/test/hotspot/jtreg/compiler/lib/ir_framework/IRNode.java -index 9e91268edff..2b25abb24c5 100644 +index 3fd0455da1d..6234ad125c5 100644 --- a/test/hotspot/jtreg/compiler/lib/ir_framework/IRNode.java +++ b/test/hotspot/jtreg/compiler/lib/ir_framework/IRNode.java @@ -21,6 +21,12 @@ @@ -80222,7 +80240,7 @@ index 9e91268edff..2b25abb24c5 100644 package compiler.lib.ir_framework; import compiler.lib.ir_framework.driver.irmatching.mapping.*; -@@ -375,13 +381,13 @@ +@@ -380,13 +386,13 @@ public static final String CHECKCAST_ARRAY = PREFIX + "CHECKCAST_ARRAY" + POSTFIX; static { @@ -80288,7 +80306,7 @@ index b9a3028978f..36efb0b63ba 100644 * @run main/othervm compiler.rangechecks.TestRangeCheckHoistingScaledIV */ diff --git a/test/hotspot/jtreg/compiler/runtime/TestConstantsInError.java b/test/hotspot/jtreg/compiler/runtime/TestConstantsInError.java -index df221959bb5..a15ac48e3fa 100644 +index 3daf12df879..31018941a9c 100644 --- a/test/hotspot/jtreg/compiler/runtime/TestConstantsInError.java +++ b/test/hotspot/jtreg/compiler/runtime/TestConstantsInError.java @@ -21,6 +21,12 @@ @@ -80367,7 +80385,7 @@ index 5dd938442cc..2ec4cab8f62 100644 * @run driver compiler.sharedstubs.SharedStubToInterpTest -XX:-TieredCompilation * diff --git a/test/hotspot/jtreg/compiler/testlibrary/sha/predicate/IntrinsicPredicates.java b/test/hotspot/jtreg/compiler/testlibrary/sha/predicate/IntrinsicPredicates.java -index 689c7c8cc2f..f734c1baa3f 100644 +index d5bf13e8fc2..9becbf7f92e 100644 --- a/test/hotspot/jtreg/compiler/testlibrary/sha/predicate/IntrinsicPredicates.java +++ b/test/hotspot/jtreg/compiler/testlibrary/sha/predicate/IntrinsicPredicates.java @@ -21,6 +21,12 @@ @@ -80383,16 +80401,16 @@ index 689c7c8cc2f..f734c1baa3f 100644 package compiler.testlibrary.sha.predicate; import jdk.test.lib.Platform; -@@ -61,19 +67,22 @@ - +@@ -62,19 +68,22 @@ public static final BooleanSupplier MD5_INSTRUCTION_AVAILABLE = new OrPredicate(new CPUSpecificPredicate("aarch64.*", null, null), + new OrPredicate(new CPUSpecificPredicate("riscv64.*", null, null), + new OrPredicate(new CPUSpecificPredicate("loongarch64.*", null, null), // x86 variants new OrPredicate(new CPUSpecificPredicate("amd64.*", null, null), new OrPredicate(new CPUSpecificPredicate("i386.*", null, null), -- new CPUSpecificPredicate("x86.*", null, null)))); -+ new CPUSpecificPredicate("x86.*", null, null))))); +- new CPUSpecificPredicate("x86.*", null, null))))); ++ new CPUSpecificPredicate("x86.*", null, null)))))); public static final BooleanSupplier SHA1_INSTRUCTION_AVAILABLE = new OrPredicate(new CPUSpecificPredicate("aarch64.*", new String[] { "sha1" }, null), @@ -80408,7 +80426,7 @@ index 689c7c8cc2f..f734c1baa3f 100644 public static final BooleanSupplier SHA256_INSTRUCTION_AVAILABLE = new OrPredicate(new CPUSpecificPredicate("aarch64.*", new String[] { "sha256" }, null), -@@ -81,12 +90,14 @@ +@@ -82,12 +91,14 @@ new OrPredicate(new CPUSpecificPredicate("s390.*", new String[] { "sha256" }, null), new OrPredicate(new CPUSpecificPredicate("ppc64.*", new String[] { "sha" }, null), new OrPredicate(new CPUSpecificPredicate("ppc64le.*", new String[] { "sha" }, null), @@ -80666,32 +80684,6 @@ index e3baed37804..18b9333b1d1 100644 * @run driver compiler.c2.irTests.TestAutoVecIntMinMax */ -diff --git a/test/hotspot/jtreg/compiler/vectorization/TestBufferVectorization.java b/test/hotspot/jtreg/compiler/vectorization/TestBufferVectorization.java -index 889cc68f876..a9e769ef99c 100644 ---- a/test/hotspot/jtreg/compiler/vectorization/TestBufferVectorization.java -+++ b/test/hotspot/jtreg/compiler/vectorization/TestBufferVectorization.java -@@ -21,6 +21,12 @@ - * questions. - */ - -+/* -+ * This file has been modified by Loongson Technology in 2023, These -+ * modifications are Copyright (c) 2023, Loongson Technology, and are made -+ * available on the same license terms set forth above. -+ */ -+ - /** - * @test - * @bug 8257531 -@@ -29,7 +35,7 @@ - * - * @requires vm.flagless - * @requires vm.compiler2.enabled & vm.debug == true -- * @requires os.arch=="x86" | os.arch=="i386" | os.arch=="amd64" | os.arch=="x86_64" | os.arch=="aarch64" -+ * @requires os.arch=="x86" | os.arch=="i386" | os.arch=="amd64" | os.arch=="x86_64" | os.arch=="aarch64" | os.arch=="loongarch64" - * - * @run driver compiler.vectorization.TestBufferVectorization array - * @run driver compiler.vectorization.TestBufferVectorization arrayOffset diff --git a/test/hotspot/jtreg/compiler/vectorization/TestFloatConversionsVector.java b/test/hotspot/jtreg/compiler/vectorization/TestFloatConversionsVector.java index 49035332fa4..8a1f3aa6882 100644 --- a/test/hotspot/jtreg/compiler/vectorization/TestFloatConversionsVector.java @@ -80716,32 +80708,6 @@ index 49035332fa4..8a1f3aa6882 100644 * @library /test/lib / * @run driver compiler.vectorization.TestFloatConversionsVector */ -diff --git a/test/hotspot/jtreg/compiler/vectorization/TestNumberOfContinuousZeros.java b/test/hotspot/jtreg/compiler/vectorization/TestNumberOfContinuousZeros.java -index abbabca0f2a..b7bde7068b5 100644 ---- a/test/hotspot/jtreg/compiler/vectorization/TestNumberOfContinuousZeros.java -+++ b/test/hotspot/jtreg/compiler/vectorization/TestNumberOfContinuousZeros.java -@@ -21,13 +21,20 @@ - * questions. - */ - -+/* -+ * This file has been modified by Loongson Technology in 2023, These -+ * modifications are Copyright (c) 2023, Loongson Technology, and are made -+ * available on the same license terms set forth above. -+ */ -+ - /** - * @test - * @key randomness - * @summary Test vectorization of numberOfTrailingZeros/numberOfLeadingZeros for Long - * @requires vm.compiler2.enabled - * @requires (os.simpleArch == "x64" & vm.cpu.features ~= ".*avx2.*") | --* (os.simpleArch == "aarch64" & vm.cpu.features ~= ".*sve.*") -+* (os.simpleArch == "aarch64" & vm.cpu.features ~= ".*sve.*") | -+* (os.simpleArch == "loongarch64") - * @library /test/lib / - * @run driver compiler.vectorization.TestNumberOfContinuousZeros - */ diff --git a/test/hotspot/jtreg/compiler/vectorization/TestPopulateIndex.java b/test/hotspot/jtreg/compiler/vectorization/TestPopulateIndex.java index e23accd27b0..e5b7682a7d1 100644 --- a/test/hotspot/jtreg/compiler/vectorization/TestPopulateIndex.java @@ -80768,31 +80734,6 @@ index e23accd27b0..e5b7682a7d1 100644 * @library /test/lib / * @run driver compiler.vectorization.TestPopulateIndex */ -diff --git a/test/hotspot/jtreg/compiler/vectorization/TestReverseBitsVector.java b/test/hotspot/jtreg/compiler/vectorization/TestReverseBitsVector.java -index 1144186d8e5..f36bb209a6b 100644 ---- a/test/hotspot/jtreg/compiler/vectorization/TestReverseBitsVector.java -+++ b/test/hotspot/jtreg/compiler/vectorization/TestReverseBitsVector.java -@@ -20,12 +20,19 @@ - * or visit www.oracle.com if you need additional information or have any - * questions. - */ -+ -+/* -+ * This file has been modified by Loongson Technology in 2023, These -+ * modifications are Copyright (c) 2023, Loongson Technology, and are made -+ * available on the same license terms set forth above. -+ */ -+ - /** - * @test - * @bug 8290034 - * @summary Auto-vectorization of Reverse bit operation. - * @requires vm.compiler2.enabled -- * @requires (os.simpleArch == "x64" & vm.cpu.features ~= ".*avx2.*") | os.arch == "aarch64" -+ * @requires (os.simpleArch == "x64" & vm.cpu.features ~= ".*avx2.*") | os.arch == "aarch64" | os.arch=="loongarch64" - * @library /test/lib / - * @run driver compiler.vectorization.TestReverseBitsVector - */ diff --git a/test/hotspot/jtreg/compiler/vectorization/TestReverseBytes.java b/test/hotspot/jtreg/compiler/vectorization/TestReverseBytes.java index 47813e2790e..d30f2d3d177 100644 --- a/test/hotspot/jtreg/compiler/vectorization/TestReverseBytes.java @@ -81079,10 +81020,10 @@ index 8004d34f5ce..1001f48afe6 100644 * @run main/othervm --enable-native-access=ALL-UNNAMED -XX:+UnlockDiagnosticVMOptions diff --git a/test/hotspot/jtreg/loongson/25064/NUMAHelper.java b/test/hotspot/jtreg/loongson/25064/NUMAHelper.java new file mode 100644 -index 00000000000..40443449bf3 +index 00000000000..ee0c4387eb3 --- /dev/null +++ b/test/hotspot/jtreg/loongson/25064/NUMAHelper.java -@@ -0,0 +1,99 @@ +@@ -0,0 +1,100 @@ +/* + * Copyright (c) 2023, Loongson Technology. All rights reserved. + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. @@ -81141,7 +81082,8 @@ index 00000000000..40443449bf3 + } + + static OutputAnalyzer invokeJvm(String... args) throws Exception { -+ return new OutputAnalyzer(ProcessTools.createTestJvm(args).start()); ++ ProcessBuilder pb = ProcessTools.createTestJavaProcessBuilder(args); ++ return new OutputAnalyzer(pb.start()); + } + + static int getNUMANodes() throws Exception { @@ -82328,7 +82270,7 @@ index 00000000000..9cfabdea488 +maxOutputSize = 2500000 diff --git a/test/hotspot/jtreg/loongson/30358/TestLoadLoad.java b/test/hotspot/jtreg/loongson/30358/TestLoadLoad.java new file mode 100644 -index 00000000000..29c3cebfece +index 00000000000..92a4f00c247 --- /dev/null +++ b/test/hotspot/jtreg/loongson/30358/TestLoadLoad.java @@ -0,0 +1,129 @@ @@ -82381,7 +82323,7 @@ index 00000000000..29c3cebfece + command.add("-XX:+PrintInterpreter"); + command.add("-version"); + -+ ProcessBuilder pb = ProcessTools.createJavaProcessBuilder(command); ++ ProcessBuilder pb = ProcessTools.createLimitedTestJavaProcessBuilder(command); + OutputAnalyzer analyzer = new OutputAnalyzer(pb.start()); + + analyzer.shouldHaveExitValue(0); @@ -82463,7 +82405,7 @@ index 00000000000..29c3cebfece +} diff --git a/test/hotspot/jtreg/loongson/30358/TestNewObjectWithFinal.java b/test/hotspot/jtreg/loongson/30358/TestNewObjectWithFinal.java new file mode 100644 -index 00000000000..a9a8cb39dca +index 00000000000..2bc9ada7ce8 --- /dev/null +++ b/test/hotspot/jtreg/loongson/30358/TestNewObjectWithFinal.java @@ -0,0 +1,247 @@ @@ -82539,7 +82481,7 @@ index 00000000000..a9a8cb39dca + command.add("-XX:CompileCommand=compileonly," + Launcher.class.getName() + "::" + "test"); + command.add(Launcher.class.getName()); + -+ ProcessBuilder pb = ProcessTools.createJavaProcessBuilder(command); ++ ProcessBuilder pb = ProcessTools.createLimitedTestJavaProcessBuilder(command); + OutputAnalyzer analyzer = new OutputAnalyzer(pb.start()); + + analyzer.shouldHaveExitValue(0); @@ -82716,7 +82658,7 @@ index 00000000000..a9a8cb39dca +} diff --git a/test/hotspot/jtreg/loongson/30358/TestVolatile.java b/test/hotspot/jtreg/loongson/30358/TestVolatile.java new file mode 100644 -index 00000000000..ebe7ed7329a +index 00000000000..9fefa381c38 --- /dev/null +++ b/test/hotspot/jtreg/loongson/30358/TestVolatile.java @@ -0,0 +1,358 @@ @@ -82796,7 +82738,7 @@ index 00000000000..ebe7ed7329a + command.add("-XX:CompileCommand=dontinline," + Launcher.class.getName() + "::" + "*"); + command.add(Launcher.class.getName()); + -+ ProcessBuilder pb = ProcessTools.createJavaProcessBuilder(command); ++ ProcessBuilder pb = ProcessTools.createLimitedTestJavaProcessBuilder(command); + + OutputAnalyzer analyzer = new OutputAnalyzer(pb.start()); + @@ -83313,7 +83255,7 @@ index 5d9c3982fb6..f346e763db5 100644 * @requires vm.flagless * @library /test/lib diff --git a/test/hotspot/jtreg/testlibrary_tests/ir_framework/tests/TestIRMatching.java b/test/hotspot/jtreg/testlibrary_tests/ir_framework/tests/TestIRMatching.java -index 6ad3f377706..cefd4e94811 100644 +index f77be989421..b4b050f00b7 100644 --- a/test/hotspot/jtreg/testlibrary_tests/ir_framework/tests/TestIRMatching.java +++ b/test/hotspot/jtreg/testlibrary_tests/ir_framework/tests/TestIRMatching.java @@ -21,6 +21,12 @@ diff --git a/openjdk-latest.spec b/openjdk-latest.spec index af25bde..2674b9c 100644 --- a/openjdk-latest.spec +++ b/openjdk-latest.spec @@ -179,7 +179,7 @@ %global top_level_dir_name %{origin} %global minorver 0 %global buildver 11 -%global rpmrelease 2 +%global rpmrelease 3 # priority must be 8 digits in total; up to openjdk 1.8, we were using 18..... so when we moved to 11, we had to add another digit %if %is_system_jdk %global priority %( printf '%02d%02d%02d%02d' %{majorver} %{minorver} %{securityver} %{buildver} ) @@ -1795,6 +1795,9 @@ cjc.mainProgram(args) -- the returns from copy_jdk_configs.lua should not affect %changelog +* Mon Dec 9 2024 Pan xuefeng - 1:23.0.1.11-3.rolling +- LoongArch update to jdk23.0.1+11 + * Thu Nov 28 2024 Dingli Zhang - 1:23.0.1.11-2.rolling - Adopt suitable buildjdkver to build by itself - Modify release and rpmrelease in spec -- Gitee