diff --git a/0008-Get-CPU-MHz-on-RISC-V.patch b/0008-Get-CPU-MHz-on-RISC-V.patch new file mode 100644 index 0000000000000000000000000000000000000000..6cfeea4690a0a6ab94473681dfc0c2eab977984a --- /dev/null +++ b/0008-Get-CPU-MHz-on-RISC-V.patch @@ -0,0 +1,40 @@ +From 08d1c895359c89ff16e85bc86dbe66fe47c90274 Mon Sep 17 00:00:00 2001 +From: "v.v.mitrofanov" +Date: Mon, 31 Jan 2022 13:09:57 +0300 +Subject: [PATCH 1/2] Get CPU MHz on RISC-V + +This test needs to know current CPU MHz value to output test results correctly. +This patch set a CPU MHz value in case of using RISC-V arch. + +get_cpu_mhz() tries to acquire CPU MHz value from /proc/cpuinfo for +some arches. It is not possible to get CPU MHz value from +/proc/cpuinfo on RISC-V. It returns always 0. But it is possible to +get this value calculated on cpu cycles. Use CPU cycles value calculated +in sample_get_cpu_mhz(); + +This patch is tested on SiFive HiFive Unmatched board. + +Signed-off-by: v.v.mitrofanov +--- + src/get_clock.c | 5 +++++ + 1 file changed, 5 insertions(+) + +diff --git a/src/get_clock.c b/src/get_clock.c +index acdc6f1..78ad865 100755 +--- a/src/get_clock.c ++++ b/src/get_clock.c +@@ -222,6 +222,11 @@ double get_cpu_mhz(int no_cpu_freq_warn) + if (proc < 1) + proc = sample; + #endif ++ #ifdef __riscv ++ if (proc <= 0) ++ proc = sample; ++ #endif ++ + if (!proc || !sample) + return 0; + +-- +2.40.1 + diff --git a/0009-Get-CPU-cycles-on-RISC-V.patch b/0009-Get-CPU-cycles-on-RISC-V.patch new file mode 100644 index 0000000000000000000000000000000000000000..1137b45a84f03000be5c6ab4525efca6cfbf9438 --- /dev/null +++ b/0009-Get-CPU-cycles-on-RISC-V.patch @@ -0,0 +1,116 @@ +From df20eb17a10aa4c930887c92a4d5a3832402a096 Mon Sep 17 00:00:00 2001 +From: "v.v.mitrofanov" +Date: Mon, 31 Jan 2022 13:41:30 +0300 +Subject: [PATCH 2/2] Get CPU cycles on RISC-V + +This test acquires CPU cycles to perform output calculations +and get timestamps. There is no cpu_cycles() implementation on RISC-V arch. + +This patch gets cycles using perf events. +One of the most notable reasons to use perf event instead of +reading counter registers is to avoid modifying MUCOUNTEREN +register. Due to the RISC-V ISA specification (riscv-privileged-v1.9) +before getting any access to counter registers it is necessary to enable it in MUCOUNTEREN in a privileged mode. On the other hand, +perf events are free to use. + +This patch is tested on the SiFive HiFive Unmatched board. + +Signed-off-by: v.v.mitrofanov +--- + src/get_clock.c | 62 +++++++++++++++++++++++++++++++++++++++++++++++++ + src/get_clock.h | 9 +++++++ + 2 files changed, 71 insertions(+) + +diff --git a/src/get_clock.c b/src/get_clock.c +index 78ad865..c6adbdc 100755 +--- a/src/get_clock.c ++++ b/src/get_clock.c +@@ -237,3 +237,65 @@ double get_cpu_mhz(int no_cpu_freq_warn) + return proc; + #endif + } ++ ++#if defined(__riscv) ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++static long perf_event_open(struct perf_event_attr *hw_event, ++ pid_t pid, int cpu, int group_fd, ++ unsigned long flags) ++{ ++ return syscall(__NR_perf_event_open, hw_event, pid, ++ cpu, group_fd, flags); ++} ++ ++cycles_t perf_get_cycles() ++{ ++ cycles_t cycles = 0; ++ struct perf_event_attr pe; ++ const pid_t pid = 0; // Current task ++ const int cpu = -1; // On any CPU ++ const int group_fd = -1; // Use leader group ++ const unsigned long flags = 0; ++ /* Use this variable just to open perf event here and once. ++ It is appropriate because it touches only this function and ++ not fix other code */ ++ static int is_open = 0; ++ /* Make file discriptor static just to keep it valid during ++ programm execution. It will be closed automatically when ++ test finishes. It is a hack just not to fix other part of test */ ++ static int fd = -1; ++ ++ if (!is_open) { ++ memset(&pe, 0, sizeof(pe)); ++ ++ pe.type = PERF_TYPE_HARDWARE; ++ pe.size = sizeof(pe); ++ pe.config = PERF_COUNT_HW_CPU_CYCLES; ++ pe.disabled = 0; ++ pe.exclude_kernel = 0; ++ pe.exclude_hv = 0; ++ ++ fd = perf_event_open(&pe, pid, cpu, group_fd, flags); ++ if (fd == -1) { ++ fprintf(stderr, "Error opening perf event (%llx)\n", pe.config); ++ exit(EXIT_FAILURE); ++ } ++ ++ is_open = 1; ++ } ++ ++ if(read(fd, &cycles, sizeof(cycles)) < 0) { ++ fprintf(stderr, "Error reading perf event (%llx)\n", pe.config); ++ exit(EXIT_FAILURE); ++ } ++ ++ return cycles; ++} ++#endif +diff --git a/src/get_clock.h b/src/get_clock.h +index dacbcd0..97c3500 100755 +--- a/src/get_clock.h ++++ b/src/get_clock.h +@@ -104,6 +104,15 @@ static inline cycles_t get_cycles() + asm volatile("mrs %0, cntvct_el0" : "=r" (cval)); + return cval; + } ++#elif defined(__riscv) ++typedef unsigned long cycles_t; ++ ++cycles_t perf_get_cycles(); ++ ++static inline cycles_t get_cycles() ++{ ++ return perf_get_cycles(); ++} + + #elif defined(__loongarch64) + typedef unsigned long cycles_t; +-- +2.40.1 + diff --git a/perftest.spec b/perftest.spec index 5429ea867f431c974407dfa27297a19085393735..0d2037fd15d7a1dc3d2fdc100fde4bea24fa00c4 100644 --- a/perftest.spec +++ b/perftest.spec @@ -1,6 +1,6 @@ Name: perftest Version: 4.5 -Release: 4 +Release: 5 License: GPLv2 or BSD Summary: RDMA Performance Testing Tools Url: https://github.com/linux-rdma/perftest @@ -13,6 +13,8 @@ Patch4: 0004-Perftest-Increase-max-inline-size-to-support-larger-.patch Patch5: 0005-Perftest-Add-support-for-HNS.patch Patch6: 0006-Perftest-Add-new-HNS-roce-device-ROH-to-support-new_.patch Patch7: 0007-add-loongarch-support-for-perftest.patch +Patch8: 0008-Get-CPU-MHz-on-RISC-V.patch +Patch9: 0009-Get-CPU-cycles-on-RISC-V.patch BuildRequires: automake gcc libibverbs-devel >= 1.2.0 librdmacm-devel >= 1.0.21 libibumad-devel >= 1.3.10.2 BuildRequires: pciutils-devel @@ -39,6 +41,12 @@ done %_bindir/* %changelog +* Mon Jul 03 2023 Xiaoqian Lv - 4.5-5 +- Type: enhancement +- ID: NA +- SUG: NA +- DESC: backport upstream 4.5-0.20 patches to support riscv64 + * Fri Jan 6 2023 Wenlong Zhang - 4.5-4 - Type: bugfix - ID: NA