From 401984bbd127ded259c03a5758ea18824090e197 Mon Sep 17 00:00:00 2001 From: AlexChen Date: Wed, 25 Dec 2024 18:30:17 +0800 Subject: [PATCH] QEMU update to version 6.2.0-105: - target/i386: Add EPYC-Genoa model to support Zen 4 processor series - target/i386: Add VNMI and automatic IBRS feature bits - target/i386: Add missing feature bits in EPYC-Milan model - target/i386: Add feature bits for CPUID_Fn80000021_EAX - target/i386: Add a couple of feature bits in 8000_0008_EBX - target/i386: Add new EPYC CPU versions with updated cache_info - target/i386: allow versioned CPUs to specify new cache_info Signed-off-by: AlexChen (cherry picked from commit 941be8259b4a01d66f0c9c9d16c7acf8933688eb) --- qemu.spec | 19 +- ...EPYC-Genoa-model-to-support-Zen-4-pr.patch | 195 ++++++++++++++++++ ...VNMI-and-automatic-IBRS-feature-bits.patch | 98 +++++++++ ...a-couple-of-feature-bits-in-8000_000.patch | 85 ++++++++ ...feature-bits-for-CPUID_Fn80000021_EA.patch | 118 +++++++++++ ...missing-feature-bits-in-EPYC-Milan-m.patch | 144 +++++++++++++ ...new-EPYC-CPU-versions-with-updated-c.patch | 184 +++++++++++++++++ ...w-versioned-CPUs-to-specify-new-cach.patch | 107 ++++++++++ 8 files changed, 948 insertions(+), 2 deletions(-) create mode 100644 target-i386-Add-EPYC-Genoa-model-to-support-Zen-4-pr.patch create mode 100644 target-i386-Add-VNMI-and-automatic-IBRS-feature-bits.patch create mode 100644 target-i386-Add-a-couple-of-feature-bits-in-8000_000.patch create mode 100644 target-i386-Add-feature-bits-for-CPUID_Fn80000021_EA.patch create mode 100644 target-i386-Add-missing-feature-bits-in-EPYC-Milan-m.patch create mode 100644 target-i386-Add-new-EPYC-CPU-versions-with-updated-c.patch create mode 100644 target-i386-allow-versioned-CPUs-to-specify-new-cach.patch diff --git a/qemu.spec b/qemu.spec index 30b4f436..9d101563 100644 --- a/qemu.spec +++ b/qemu.spec @@ -3,7 +3,7 @@ Name: qemu Version: 6.2.0 -Release: 104 +Release: 105 Epoch: 10 Summary: QEMU is a generic and open source machine emulator and virtualizer License: GPLv2 and BSD and MIT and CC-BY-SA-4.0 @@ -1126,7 +1126,13 @@ Patch1111: s390x-ap-fix-missing-subsystem-reset-registration.patch Patch1112: qemu-bswap-Undefine-CPU_CONVERT-once-done.patch Patch1113: linux-user-Add-missing-signals-in-strace-output.patch Patch1114: linux-user-Add-missing-clock_gettime64-syscall-strac.patch - +Patch1115: target-i386-allow-versioned-CPUs-to-specify-new-cach.patch +Patch1116: target-i386-Add-new-EPYC-CPU-versions-with-updated-c.patch +Patch1117: target-i386-Add-a-couple-of-feature-bits-in-8000_000.patch +Patch1118: target-i386-Add-feature-bits-for-CPUID_Fn80000021_EA.patch +Patch1119: target-i386-Add-missing-feature-bits-in-EPYC-Milan-m.patch +Patch1120: target-i386-Add-VNMI-and-automatic-IBRS-feature-bits.patch +Patch1121: target-i386-Add-EPYC-Genoa-model-to-support-Zen-4-pr.patch BuildRequires: flex BuildRequires: gcc @@ -1725,6 +1731,15 @@ getent passwd qemu >/dev/null || \ %endif %changelog +* Wed Dec 25 2024 - 10:6.2.0-105 +- target/i386: Add EPYC-Genoa model to support Zen 4 processor series +- target/i386: Add VNMI and automatic IBRS feature bits +- target/i386: Add missing feature bits in EPYC-Milan model +- target/i386: Add feature bits for CPUID_Fn80000021_EAX +- target/i386: Add a couple of feature bits in 8000_0008_EBX +- target/i386: Add new EPYC CPU versions with updated cache_info +- target/i386: allow versioned CPUs to specify new cache_info + * Tue Dec 17 2024 - 10:6.2.0-104 - intel_iommu: Add missed reserved bit check for IEC descriptor - 9pfs: fix crash on 'Treaddir' request diff --git a/target-i386-Add-EPYC-Genoa-model-to-support-Zen-4-pr.patch b/target-i386-Add-EPYC-Genoa-model-to-support-Zen-4-pr.patch new file mode 100644 index 00000000..4c182174 --- /dev/null +++ b/target-i386-Add-EPYC-Genoa-model-to-support-Zen-4-pr.patch @@ -0,0 +1,195 @@ +From 85e2eee5a5f8b8146203c05f43caf1d988bc0d7d Mon Sep 17 00:00:00 2001 +From: Babu Moger +Date: Thu, 4 May 2023 15:53:12 -0500 +Subject: [PATCH] target/i386: Add EPYC-Genoa model to support Zen 4 processor + series + +mainline inclusion +from mainline-8.1.0 +commit 166b1741884dd4fd7090b753cd7333868457a29b +category: feature +bugzilla: https://gitee.com/openeuler/qemu/issues/IAUSKJ +Reference: https://gitlab.com/qemu-project/qemu/-/commit/166b1741884dd4fd7090b753cd7333868457a29b + +commit 166b1741884dd4fd7090b753cd7333868457a29b upstream + +Adds the support for AMD EPYC Genoa generation processors. The model +display for the new processor will be EPYC-Genoa. + +Adds the following new feature bits on top of the feature bits from +the previous generation EPYC models. + +avx512f : AVX-512 Foundation instruction +avx512dq : AVX-512 Doubleword & Quadword Instruction +avx512ifma : AVX-512 Integer Fused Multiply Add instruction +avx512cd : AVX-512 Conflict Detection instruction +avx512bw : AVX-512 Byte and Word Instructions +avx512vl : AVX-512 Vector Length Extension Instructions +avx512vbmi : AVX-512 Vector Byte Manipulation Instruction +avx512_vbmi2 : AVX-512 Additional Vector Byte Manipulation Instruction +gfni : AVX-512 Galois Field New Instructions +avx512_vnni : AVX-512 Vector Neural Network Instructions +avx512_bitalg : AVX-512 Bit Algorithms, add bit algorithms Instructions +avx512_vpopcntdq: AVX-512 AVX-512 Vector Population Count Doubleword and + Quadword Instructions +avx512_bf16 : AVX-512 BFLOAT16 instructions +la57 : 57-bit virtual address support (5-level Page Tables) +vnmi : Virtual NMI (VNMI) allows the hypervisor to inject the NMI + into the guest without using Event Injection mechanism + meaning not required to track the guest NMI and intercepting + the IRET. +auto-ibrs : The AMD Zen4 core supports a new feature called Automatic IBRS. + It is a "set-and-forget" feature that means that, unlike e.g., + s/w-toggled SPEC_CTRL.IBRS, h/w manages its IBRS mitigation + resources automatically across CPL transitions. + +Signed-off-by: Babu Moger +Message-Id: <20230504205313.225073-8-babu.moger@amd.com> +Signed-off-by: Paolo Bonzini +--- + target/i386/cpu.c | 122 ++++++++++++++++++++++++++++++++++++++++++++++ + 1 file changed, 122 insertions(+) + +diff --git a/target/i386/cpu.c b/target/i386/cpu.c +index 59b585b0d0..016a62a809 100644 +--- a/target/i386/cpu.c ++++ b/target/i386/cpu.c +@@ -1999,6 +1999,56 @@ static const CPUCaches epyc_milan_v2_cache_info = { + }, + }; + ++static const CPUCaches epyc_genoa_cache_info = { ++ .l1d_cache = &(CPUCacheInfo) { ++ .type = DATA_CACHE, ++ .level = 1, ++ .size = 32 * KiB, ++ .line_size = 64, ++ .associativity = 8, ++ .partitions = 1, ++ .sets = 64, ++ .lines_per_tag = 1, ++ .self_init = 1, ++ .no_invd_sharing = true, ++ }, ++ .l1i_cache = &(CPUCacheInfo) { ++ .type = INSTRUCTION_CACHE, ++ .level = 1, ++ .size = 32 * KiB, ++ .line_size = 64, ++ .associativity = 8, ++ .partitions = 1, ++ .sets = 64, ++ .lines_per_tag = 1, ++ .self_init = 1, ++ .no_invd_sharing = true, ++ }, ++ .l2_cache = &(CPUCacheInfo) { ++ .type = UNIFIED_CACHE, ++ .level = 2, ++ .size = 1 * MiB, ++ .line_size = 64, ++ .associativity = 8, ++ .partitions = 1, ++ .sets = 2048, ++ .lines_per_tag = 1, ++ }, ++ .l3_cache = &(CPUCacheInfo) { ++ .type = UNIFIED_CACHE, ++ .level = 3, ++ .size = 32 * MiB, ++ .line_size = 64, ++ .associativity = 16, ++ .partitions = 1, ++ .sets = 32768, ++ .lines_per_tag = 1, ++ .self_init = true, ++ .inclusive = true, ++ .complex_indexing = false, ++ }, ++}; ++ + /* The following VMX features are not supported by KVM and are left out in the + * CPU definitions: + * +@@ -4904,6 +4954,78 @@ static const X86CPUDefinition builtin_x86_defs[] = { + { /* end of list */ } + } + }, ++ { ++ .name = "EPYC-Genoa", ++ .level = 0xd, ++ .vendor = CPUID_VENDOR_AMD, ++ .family = 25, ++ .model = 17, ++ .stepping = 0, ++ .features[FEAT_1_EDX] = ++ CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | ++ CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | ++ CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | ++ CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | ++ CPUID_VME | CPUID_FP87, ++ .features[FEAT_1_ECX] = ++ CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | ++ CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT | ++ CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | ++ CPUID_EXT_PCID | CPUID_EXT_CX16 | CPUID_EXT_FMA | ++ CPUID_EXT_SSSE3 | CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | ++ CPUID_EXT_SSE3, ++ .features[FEAT_8000_0001_EDX] = ++ CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | ++ CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | ++ CPUID_EXT2_SYSCALL, ++ .features[FEAT_8000_0001_ECX] = ++ CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | ++ CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | ++ CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | ++ CPUID_EXT3_TOPOEXT | CPUID_EXT3_PERFCORE, ++ .features[FEAT_8000_0008_EBX] = ++ CPUID_8000_0008_EBX_CLZERO | CPUID_8000_0008_EBX_XSAVEERPTR | ++ CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_IBPB | ++ CPUID_8000_0008_EBX_IBRS | CPUID_8000_0008_EBX_STIBP | ++ CPUID_8000_0008_EBX_STIBP_ALWAYS_ON | ++ CPUID_8000_0008_EBX_AMD_SSBD | CPUID_8000_0008_EBX_AMD_PSFD, ++ .features[FEAT_8000_0021_EAX] = ++ CPUID_8000_0021_EAX_No_NESTED_DATA_BP | ++ CPUID_8000_0021_EAX_LFENCE_ALWAYS_SERIALIZING | ++ CPUID_8000_0021_EAX_NULL_SEL_CLR_BASE | ++ CPUID_8000_0021_EAX_AUTO_IBRS, ++ .features[FEAT_7_0_EBX] = ++ CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | ++ CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | ++ CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_AVX512F | ++ CPUID_7_0_EBX_AVX512DQ | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | ++ CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_AVX512IFMA | ++ CPUID_7_0_EBX_CLFLUSHOPT | CPUID_7_0_EBX_CLWB | ++ CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_SHA_NI | ++ CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512VL, ++ .features[FEAT_7_0_ECX] = ++ CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | ++ CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI | ++ CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | ++ CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG | ++ CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57 | ++ CPUID_7_0_ECX_RDPID, ++ .features[FEAT_7_0_EDX] = ++ CPUID_7_0_EDX_FSRM, ++ .features[FEAT_7_1_EAX] = ++ CPUID_7_1_EAX_AVX512_BF16, ++ .features[FEAT_XSAVE] = ++ CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | ++ CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES, ++ .features[FEAT_6_EAX] = ++ CPUID_6_EAX_ARAT, ++ .features[FEAT_SVM] = ++ CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE | CPUID_SVM_VNMI | ++ CPUID_SVM_SVME_ADDR_CHK, ++ .xlevel = 0x80000022, ++ .model_id = "AMD EPYC-Genoa Processor", ++ .cache_info = &epyc_genoa_cache_info, ++ }, + }; + + /* +-- +2.45.1.windows.1 + diff --git a/target-i386-Add-VNMI-and-automatic-IBRS-feature-bits.patch b/target-i386-Add-VNMI-and-automatic-IBRS-feature-bits.patch new file mode 100644 index 00000000..6564eee6 --- /dev/null +++ b/target-i386-Add-VNMI-and-automatic-IBRS-feature-bits.patch @@ -0,0 +1,98 @@ +From bb5ec050bb8144c464cfe1b0954230ea2d5b4803 Mon Sep 17 00:00:00 2001 +From: Babu Moger +Date: Thu, 4 May 2023 15:53:11 -0500 +Subject: [PATCH] target/i386: Add VNMI and automatic IBRS feature bits +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +mainline inclusion +from mainline-8.1.0 +commit 62a798d4bc2c3e767d94670776c77a7df274d7c5 +category: feature +bugzilla: https://gitee.com/openeuler/qemu/issues/IAUSKJ +Reference: https://gitlab.com/qemu-project/qemu/-/commit/62a798d4bc2c3e767d94670776c77a7df274d7c5 + +commit 62a798d4bc2c3e767d94670776c77a7df274d7c5 upstream + +Add the following featute bits. + +vnmi: Virtual NMI (VNMI) allows the hypervisor to inject the NMI into the + guest without using Event Injection mechanism meaning not required to + track the guest NMI and intercepting the IRET. + The presence of this feature is indicated via the CPUID function + 0x8000000A_EDX[25]. + +automatic-ibrs : + The AMD Zen4 core supports a new feature called Automatic IBRS. + It is a "set-and-forget" feature that means that, unlike e.g., + s/w-toggled SPEC_CTRL.IBRS, h/w manages its IBRS mitigation + resources automatically across CPL transitions. + The presence of this feature is indicated via the CPUID function + 0x80000021_EAX[8]. + +The documention for the features are available in the links below. +a. Processor Programming Reference (PPR) for AMD Family 19h Model 01h, + Revision B1 Processors +b. AMD64 Architecture Programmer’s Manual Volumes 1–5 Publication No. Revision + 40332 4.05 Date October 2022 + +Signed-off-by: Santosh Shukla +Signed-off-by: Kim Phillips +Signed-off-by: Babu Moger +Link: https://www.amd.com/system/files/TechDocs/55898_B1_pub_0.50.zip +Link: https://www.amd.com/system/files/TechDocs/40332_4.05.pdf +Message-Id: <20230504205313.225073-7-babu.moger@amd.com> +Signed-off-by: Paolo Bonzini +(cherry picked from commit 62a798d4bc2c3e767d94670776c77a7df274d7c5) +--- + target/i386/cpu.c | 4 ++-- + target/i386/cpu.h | 3 +++ + 2 files changed, 5 insertions(+), 2 deletions(-) + +diff --git a/target/i386/cpu.c b/target/i386/cpu.c +index 4d7f948eb1..59b585b0d0 100644 +--- a/target/i386/cpu.c ++++ b/target/i386/cpu.c +@@ -806,7 +806,7 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = { + "pfthreshold", "avic", NULL, "v-vmsave-vmload", + "vgif", NULL, NULL, NULL, + NULL, NULL, NULL, NULL, +- NULL, NULL, NULL, NULL, ++ NULL, "vnmi", NULL, NULL, + "svme-addr-chk", NULL, NULL, NULL, + }, + .cpuid = { .eax = 0x8000000A, .reg = R_EDX, }, +@@ -963,7 +963,7 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = { + .feat_names = { + "no-nested-data-bp", NULL, "lfence-always-serializing", NULL, + NULL, NULL, "null-sel-clr-base", NULL, +- NULL, NULL, NULL, NULL, ++ "auto-ibrs", NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, +diff --git a/target/i386/cpu.h b/target/i386/cpu.h +index 7b1190c3f2..84910db8bb 100644 +--- a/target/i386/cpu.h ++++ b/target/i386/cpu.h +@@ -760,6 +760,7 @@ uint64_t x86_cpu_get_supported_feature_word(FeatureWord w, + #define CPUID_SVM_AVIC (1U << 13) + #define CPUID_SVM_V_VMSAVE_VMLOAD (1U << 15) + #define CPUID_SVM_VGIF (1U << 16) ++#define CPUID_SVM_VNMI (1U << 25) + #define CPUID_SVM_SVME_ADDR_CHK (1U << 28) + + /* Support RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE */ +@@ -948,6 +949,8 @@ uint64_t x86_cpu_get_supported_feature_word(FeatureWord w, + #define CPUID_8000_0021_EAX_LFENCE_ALWAYS_SERIALIZING (1U << 2) + /* Null Selector Clears Base */ + #define CPUID_8000_0021_EAX_NULL_SEL_CLR_BASE (1U << 6) ++/* Automatic IBRS */ ++#define CPUID_8000_0021_EAX_AUTO_IBRS (1U << 8) + + #define CPUID_XSAVE_XSAVEOPT (1U << 0) + #define CPUID_XSAVE_XSAVEC (1U << 1) +-- +2.45.1.windows.1 + diff --git a/target-i386-Add-a-couple-of-feature-bits-in-8000_000.patch b/target-i386-Add-a-couple-of-feature-bits-in-8000_000.patch new file mode 100644 index 00000000..c8f851a2 --- /dev/null +++ b/target-i386-Add-a-couple-of-feature-bits-in-8000_000.patch @@ -0,0 +1,85 @@ +From ee4a95c635cf3add270ed195cbf3de2af087fd69 Mon Sep 17 00:00:00 2001 +From: Babu Moger +Date: Thu, 4 May 2023 15:53:08 -0500 +Subject: [PATCH] target/i386: Add a couple of feature bits in 8000_0008_EBX + +mainline inclusion +from mainline-8.1.0 +commit bb039a230e6a7920d71d21fa9afee2653a678c48 +category: feature +bugzilla: https://gitee.com/openeuler/qemu/issues/IAUSKJ +Reference: https://gitlab.com/qemu-project/qemu/-/commit/bb039a230e6a7920d71d21fa9afee2653a678c48 + +commit bb039a230e6a7920d71d21fa9afee2653a678c48 upstream + +Add the following feature bits. + +amd-psfd : Predictive Store Forwarding Disable: + PSF is a hardware-based micro-architectural optimization + designed to improve the performance of code execution by + predicting address dependencies between loads and stores. + While SSBD (Speculative Store Bypass Disable) disables both + PSF and speculative store bypass, PSFD only disables PSF. + PSFD may be desirable for the software which is concerned + with the speculative behavior of PSF but desires a smaller + performance impact than setting SSBD. + Depends on the following kernel commit: + b73a54321ad8 ("KVM: x86: Expose Predictive Store Forwarding Disable") + +stibp-always-on : + Single Thread Indirect Branch Prediction mode has enhanced + performance and may be left always on. + +The documentation for the features are available in the links below. +a. Processor Programming Reference (PPR) for AMD Family 19h Model 01h, + Revision B1 Processors +b. SECURITY ANALYSIS OF AMD PREDICTIVE STORE FORWARDING + +Signed-off-by: Babu Moger +Acked-by: Michael S. Tsirkin +Link: https://www.amd.com/system/files/documents/security-analysis-predictive-store-forwarding.pdf +Link: https://www.amd.com/system/files/TechDocs/55898_B1_pub_0.50.zip +Message-Id: <20230504205313.225073-4-babu.moger@amd.com> +Signed-off-by: Paolo Bonzini +--- + target/i386/cpu.c | 4 ++-- + target/i386/cpu.h | 4 ++++ + 2 files changed, 6 insertions(+), 2 deletions(-) + +diff --git a/target/i386/cpu.c b/target/i386/cpu.c +index 940aec42cf..02d19c2b4e 100644 +--- a/target/i386/cpu.c ++++ b/target/i386/cpu.c +@@ -949,10 +949,10 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = { + NULL, NULL, NULL, NULL, + NULL, "wbnoinvd", NULL, NULL, + "ibpb", NULL, "ibrs", "amd-stibp", +- NULL, NULL, NULL, NULL, ++ NULL, "stibp-always-on", NULL, NULL, + NULL, NULL, NULL, NULL, + "amd-ssbd", "virt-ssbd", "amd-no-ssb", NULL, +- NULL, NULL, NULL, NULL, ++ "amd-psfd", NULL, NULL, NULL, + }, + .cpuid = { .eax = 0x80000008, .reg = R_EBX, }, + .tcg_features = 0, +diff --git a/target/i386/cpu.h b/target/i386/cpu.h +index e8322a928b..623bd0e4d6 100644 +--- a/target/i386/cpu.h ++++ b/target/i386/cpu.h +@@ -934,8 +934,12 @@ uint64_t x86_cpu_get_supported_feature_word(FeatureWord w, + #define CPUID_8000_0008_EBX_IBRS (1U << 14) + /* Single Thread Indirect Branch Predictors */ + #define CPUID_8000_0008_EBX_STIBP (1U << 15) ++/* STIBP mode has enhanced performance and may be left always on */ ++#define CPUID_8000_0008_EBX_STIBP_ALWAYS_ON (1U << 17) + /* Speculative Store Bypass Disable */ + #define CPUID_8000_0008_EBX_AMD_SSBD (1U << 24) ++/* Predictive Store Forwarding Disable */ ++#define CPUID_8000_0008_EBX_AMD_PSFD (1U << 28) + + #define CPUID_XSAVE_XSAVEOPT (1U << 0) + #define CPUID_XSAVE_XSAVEC (1U << 1) +-- +2.45.1.windows.1 + diff --git a/target-i386-Add-feature-bits-for-CPUID_Fn80000021_EA.patch b/target-i386-Add-feature-bits-for-CPUID_Fn80000021_EA.patch new file mode 100644 index 00000000..e4c74b43 --- /dev/null +++ b/target-i386-Add-feature-bits-for-CPUID_Fn80000021_EA.patch @@ -0,0 +1,118 @@ +From c006e700cf6f1925dc9400d37e2e6c9c53b7bc92 Mon Sep 17 00:00:00 2001 +From: Babu Moger +Date: Thu, 4 May 2023 15:53:09 -0500 +Subject: [PATCH] target/i386: Add feature bits for CPUID_Fn80000021_EAX +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +mainline inclusion +from mainline-8.1.0 +commit b70eec312b185197d639bff689007727e596afd1 +category: feature +bugzilla: https://gitee.com/openeuler/qemu/issues/IAUSKJ +Reference: https://gitlab.com/qemu-project/qemu/-/commit/b70eec312b185197d639bff689007727e596afd1 + +commit b70eec312b185197d639bff689007727e596afd1 upstream + +Add the following feature bits. +no-nested-data-bp : Processor ignores nested data breakpoints. +lfence-always-serializing : LFENCE instruction is always serializing. +null-sel-cls-base : Null Selector Clears Base. When this bit is + set, a null segment load clears the segment base. + +The documentation for the features are available in the links below. +a. Processor Programming Reference (PPR) for AMD Family 19h Model 01h, + Revision B1 Processors +b. AMD64 Architecture Programmer’s Manual Volumes 1–5 Publication No. Revision + 40332 4.05 Date October 2022 + +Signed-off-by: Babu Moger +Acked-by: Michael S. Tsirkin +Link: https://www.amd.com/system/files/TechDocs/55898_B1_pub_0.50.zip +Link: https://www.amd.com/system/files/TechDocs/40332_4.05.pdf +Message-Id: <20230504205313.225073-5-babu.moger@amd.com> +Signed-off-by: Paolo Bonzini +--- + target/i386/cpu.c | 24 ++++++++++++++++++++++++ + target/i386/cpu.h | 8 ++++++++ + 2 files changed, 32 insertions(+) + +diff --git a/target/i386/cpu.c b/target/i386/cpu.c +index 02d19c2b4e..527135ca9d 100644 +--- a/target/i386/cpu.c ++++ b/target/i386/cpu.c +@@ -958,6 +958,22 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = { + .tcg_features = 0, + .unmigratable_flags = 0, + }, ++ [FEAT_8000_0021_EAX] = { ++ .type = CPUID_FEATURE_WORD, ++ .feat_names = { ++ "no-nested-data-bp", NULL, "lfence-always-serializing", NULL, ++ NULL, NULL, "null-sel-clr-base", NULL, ++ NULL, NULL, NULL, NULL, ++ NULL, NULL, NULL, NULL, ++ NULL, NULL, NULL, NULL, ++ NULL, NULL, NULL, NULL, ++ NULL, NULL, NULL, NULL, ++ NULL, NULL, NULL, NULL, ++ }, ++ .cpuid = { .eax = 0x80000021, .reg = R_EAX, }, ++ .tcg_features = 0, ++ .unmigratable_flags = 0, ++ }, + [FEAT_XSAVE] = { + .type = CPUID_FEATURE_WORD, + .feat_names = { +@@ -6542,6 +6558,10 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, + *ebx |= sev_get_reduced_phys_bits() << 6; + } + break; ++ case 0x80000021: ++ *eax = env->features[FEAT_8000_0021_EAX]; ++ *ebx = *ecx = *edx = 0; ++ break; + default: + /* reserved values: zero */ + *eax = 0; +@@ -6949,6 +6969,10 @@ void x86_cpu_expand_features(X86CPU *cpu, Error **errp) + x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000001F); + } + ++ if (env->features[FEAT_8000_0021_EAX]) { ++ x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x80000021); ++ } ++ + /* SGX requires CPUID[0x12] for EPC enumeration */ + if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_SGX) { + x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x12); +diff --git a/target/i386/cpu.h b/target/i386/cpu.h +index 623bd0e4d6..7b1190c3f2 100644 +--- a/target/i386/cpu.h ++++ b/target/i386/cpu.h +@@ -585,6 +585,7 @@ typedef enum FeatureWord { + FEAT_8000_0001_ECX, /* CPUID[8000_0001].ECX */ + FEAT_8000_0007_EDX, /* CPUID[8000_0007].EDX */ + FEAT_8000_0008_EBX, /* CPUID[8000_0008].EBX */ ++ FEAT_8000_0021_EAX, /* CPUID[8000_0021].EAX */ + FEAT_C000_0001_EDX, /* CPUID[C000_0001].EDX */ + FEAT_KVM, /* CPUID[4000_0001].EAX (KVM_CPUID_FEATURES) */ + FEAT_KVM_HINTS, /* CPUID[4000_0001].EDX */ +@@ -941,6 +942,13 @@ uint64_t x86_cpu_get_supported_feature_word(FeatureWord w, + /* Predictive Store Forwarding Disable */ + #define CPUID_8000_0008_EBX_AMD_PSFD (1U << 28) + ++/* Processor ignores nested data breakpoints */ ++#define CPUID_8000_0021_EAX_No_NESTED_DATA_BP (1U << 0) ++/* LFENCE is always serializing */ ++#define CPUID_8000_0021_EAX_LFENCE_ALWAYS_SERIALIZING (1U << 2) ++/* Null Selector Clears Base */ ++#define CPUID_8000_0021_EAX_NULL_SEL_CLR_BASE (1U << 6) ++ + #define CPUID_XSAVE_XSAVEOPT (1U << 0) + #define CPUID_XSAVE_XSAVEC (1U << 1) + #define CPUID_XSAVE_XGETBV1 (1U << 2) +-- +2.45.1.windows.1 + diff --git a/target-i386-Add-missing-feature-bits-in-EPYC-Milan-m.patch b/target-i386-Add-missing-feature-bits-in-EPYC-Milan-m.patch new file mode 100644 index 00000000..ccc58012 --- /dev/null +++ b/target-i386-Add-missing-feature-bits-in-EPYC-Milan-m.patch @@ -0,0 +1,144 @@ +From e5e589d3b9023861474e53428e721482614cee6d Mon Sep 17 00:00:00 2001 +From: Babu Moger +Date: Thu, 4 May 2023 15:53:10 -0500 +Subject: [PATCH] target/i386: Add missing feature bits in EPYC-Milan model +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +mainline inclusion +from mainline-8.1.0 +commit 27f03be6f59d04bd5673ba1e1628b2b490f9a9ff +category: feature +bugzilla: https://gitee.com/openeuler/qemu/issues/IAUSKJ +Reference: https://gitlab.com/qemu-project/qemu/-/commit/27f03be6f59d04bd5673ba1e1628b2b490f9a9ff + +commit 27f03be6f59d04bd5673ba1e1628b2b490f9a9ff upstream + +Add the following feature bits for EPYC-Milan model and bump the version. +vaes : Vector VAES(ENC|DEC), VAES(ENC|DEC)LAST instruction support +vpclmulqdq : Vector VPCLMULQDQ instruction support +stibp-always-on : Single Thread Indirect Branch Prediction Mode has enhanced + performance and may be left Always on +amd-psfd : Predictive Store Forward Disable +no-nested-data-bp : Processor ignores nested data breakpoints +lfence-always-serializing : LFENCE instruction is always serializing +null-sel-clr-base : Null Selector Clears Base. When this bit is + set, a null segment load clears the segment base + +These new features will be added in EPYC-Milan-v2. The "-cpu help" output +after the change will be. + + x86 EPYC-Milan (alias configured by machine type) + x86 EPYC-Milan-v1 AMD EPYC-Milan Processor + x86 EPYC-Milan-v2 AMD EPYC-Milan Processor + +The documentation for the features are available in the links below. +a. Processor Programming Reference (PPR) for AMD Family 19h Model 01h, + Revision B1 Processors +b. SECURITY ANALYSIS OF AMD PREDICTIVE STORE FORWARDING +c. AMD64 Architecture Programmer’s Manual Volumes 1–5 Publication No. Revision + 40332 4.05 Date October 2022 + +Signed-off-by: Babu Moger +Acked-by: Michael S. Tsirkin +Link: https://www.amd.com/system/files/TechDocs/55898_B1_pub_0.50.zip +Link: https://www.amd.com/system/files/documents/security-analysis-predictive-store-forwarding.pdf +Link: https://www.amd.com/system/files/TechDocs/40332_4.05.pdf +Message-Id: <20230504205313.225073-6-babu.moger@amd.com> +Signed-off-by: Paolo Bonzini +--- + target/i386/cpu.c | 70 +++++++++++++++++++++++++++++++++++++++++++++++ + 1 file changed, 70 insertions(+) + +diff --git a/target/i386/cpu.c b/target/i386/cpu.c +index 527135ca9d..4d7f948eb1 100644 +--- a/target/i386/cpu.c ++++ b/target/i386/cpu.c +@@ -1949,6 +1949,56 @@ static const CPUCaches epyc_milan_cache_info = { + }, + }; + ++static const CPUCaches epyc_milan_v2_cache_info = { ++ .l1d_cache = &(CPUCacheInfo) { ++ .type = DATA_CACHE, ++ .level = 1, ++ .size = 32 * KiB, ++ .line_size = 64, ++ .associativity = 8, ++ .partitions = 1, ++ .sets = 64, ++ .lines_per_tag = 1, ++ .self_init = 1, ++ .no_invd_sharing = true, ++ }, ++ .l1i_cache = &(CPUCacheInfo) { ++ .type = INSTRUCTION_CACHE, ++ .level = 1, ++ .size = 32 * KiB, ++ .line_size = 64, ++ .associativity = 8, ++ .partitions = 1, ++ .sets = 64, ++ .lines_per_tag = 1, ++ .self_init = 1, ++ .no_invd_sharing = true, ++ }, ++ .l2_cache = &(CPUCacheInfo) { ++ .type = UNIFIED_CACHE, ++ .level = 2, ++ .size = 512 * KiB, ++ .line_size = 64, ++ .associativity = 8, ++ .partitions = 1, ++ .sets = 1024, ++ .lines_per_tag = 1, ++ }, ++ .l3_cache = &(CPUCacheInfo) { ++ .type = UNIFIED_CACHE, ++ .level = 3, ++ .size = 32 * MiB, ++ .line_size = 64, ++ .associativity = 16, ++ .partitions = 1, ++ .sets = 32768, ++ .lines_per_tag = 1, ++ .self_init = true, ++ .inclusive = true, ++ .complex_indexing = false, ++ }, ++}; ++ + /* The following VMX features are not supported by KVM and are left out in the + * CPU definitions: + * +@@ -4833,6 +4883,26 @@ static const X86CPUDefinition builtin_x86_defs[] = { + .xlevel = 0x8000001E, + .model_id = "AMD EPYC-Milan Processor", + .cache_info = &epyc_milan_cache_info, ++ .versions = (X86CPUVersionDefinition[]) { ++ { .version = 1 }, ++ { ++ .version = 2, ++ .props = (PropValue[]) { ++ { "model-id", ++ "AMD EPYC-Milan-v2 Processor" }, ++ { "vaes", "on" }, ++ { "vpclmulqdq", "on" }, ++ { "stibp-always-on", "on" }, ++ { "amd-psfd", "on" }, ++ { "no-nested-data-bp", "on" }, ++ { "lfence-always-serializing", "on" }, ++ { "null-sel-clr-base", "on" }, ++ { /* end of list */ } ++ }, ++ .cache_info = &epyc_milan_v2_cache_info ++ }, ++ { /* end of list */ } ++ } + }, + }; + +-- +2.45.1.windows.1 + diff --git a/target-i386-Add-new-EPYC-CPU-versions-with-updated-c.patch b/target-i386-Add-new-EPYC-CPU-versions-with-updated-c.patch new file mode 100644 index 00000000..711c7428 --- /dev/null +++ b/target-i386-Add-new-EPYC-CPU-versions-with-updated-c.patch @@ -0,0 +1,184 @@ +From 2f5f0f03e92489bf17edd686d48a22201b5ff081 Mon Sep 17 00:00:00 2001 +From: Michael Roth +Date: Thu, 4 May 2023 15:53:07 -0500 +Subject: [PATCH] target/i386: Add new EPYC CPU versions with updated + cache_info + +mainline inclusion +from mainline-8.1.0 +commit d7c72735f618a7ee27ee109d8b1468193734606a +category: feature +bugzilla: https://gitee.com/openeuler/qemu/issues/IAUSKJ +Reference: https://gitlab.com/qemu-project/qemu/-/commit/d7c72735f618a7ee27ee109d8b1468193734606a + +commit d7c72735f618a7ee27ee109d8b1468193734606a upstream + +Introduce new EPYC cpu versions: EPYC-v4 and EPYC-Rome-v3. +The only difference vs. older models is an updated cache_info with +the 'complex_indexing' bit unset, since this bit is not currently +defined for AMD and may cause problems should it be used for +something else in the future. Setting this bit will also cause +CPUID validation failures when running SEV-SNP guests. + +Signed-off-by: Michael Roth +Signed-off-by: Babu Moger +Acked-by: Michael S. Tsirkin +Message-Id: <20230504205313.225073-3-babu.moger@amd.com> +Signed-off-by: Paolo Bonzini +--- + target/i386/cpu.c | 118 ++++++++++++++++++++++++++++++++++++++++++++++ + 1 file changed, 118 insertions(+) + +diff --git a/target/i386/cpu.c b/target/i386/cpu.c +index 60df10c954..940aec42cf 100644 +--- a/target/i386/cpu.c ++++ b/target/i386/cpu.c +@@ -1733,6 +1733,56 @@ static const CPUCaches epyc_cache_info = { + }, + }; + ++static CPUCaches epyc_v4_cache_info = { ++ .l1d_cache = &(CPUCacheInfo) { ++ .type = DATA_CACHE, ++ .level = 1, ++ .size = 32 * KiB, ++ .line_size = 64, ++ .associativity = 8, ++ .partitions = 1, ++ .sets = 64, ++ .lines_per_tag = 1, ++ .self_init = 1, ++ .no_invd_sharing = true, ++ }, ++ .l1i_cache = &(CPUCacheInfo) { ++ .type = INSTRUCTION_CACHE, ++ .level = 1, ++ .size = 64 * KiB, ++ .line_size = 64, ++ .associativity = 4, ++ .partitions = 1, ++ .sets = 256, ++ .lines_per_tag = 1, ++ .self_init = 1, ++ .no_invd_sharing = true, ++ }, ++ .l2_cache = &(CPUCacheInfo) { ++ .type = UNIFIED_CACHE, ++ .level = 2, ++ .size = 512 * KiB, ++ .line_size = 64, ++ .associativity = 8, ++ .partitions = 1, ++ .sets = 1024, ++ .lines_per_tag = 1, ++ }, ++ .l3_cache = &(CPUCacheInfo) { ++ .type = UNIFIED_CACHE, ++ .level = 3, ++ .size = 8 * MiB, ++ .line_size = 64, ++ .associativity = 16, ++ .partitions = 1, ++ .sets = 8192, ++ .lines_per_tag = 1, ++ .self_init = true, ++ .inclusive = true, ++ .complex_indexing = false, ++ }, ++}; ++ + static const CPUCaches epyc_rome_cache_info = { + .l1d_cache = &(CPUCacheInfo) { + .type = DATA_CACHE, +@@ -1783,6 +1833,56 @@ static const CPUCaches epyc_rome_cache_info = { + }, + }; + ++static const CPUCaches epyc_rome_v3_cache_info = { ++ .l1d_cache = &(CPUCacheInfo) { ++ .type = DATA_CACHE, ++ .level = 1, ++ .size = 32 * KiB, ++ .line_size = 64, ++ .associativity = 8, ++ .partitions = 1, ++ .sets = 64, ++ .lines_per_tag = 1, ++ .self_init = 1, ++ .no_invd_sharing = true, ++ }, ++ .l1i_cache = &(CPUCacheInfo) { ++ .type = INSTRUCTION_CACHE, ++ .level = 1, ++ .size = 32 * KiB, ++ .line_size = 64, ++ .associativity = 8, ++ .partitions = 1, ++ .sets = 64, ++ .lines_per_tag = 1, ++ .self_init = 1, ++ .no_invd_sharing = true, ++ }, ++ .l2_cache = &(CPUCacheInfo) { ++ .type = UNIFIED_CACHE, ++ .level = 2, ++ .size = 512 * KiB, ++ .line_size = 64, ++ .associativity = 8, ++ .partitions = 1, ++ .sets = 1024, ++ .lines_per_tag = 1, ++ }, ++ .l3_cache = &(CPUCacheInfo) { ++ .type = UNIFIED_CACHE, ++ .level = 3, ++ .size = 16 * MiB, ++ .line_size = 64, ++ .associativity = 16, ++ .partitions = 1, ++ .sets = 16384, ++ .lines_per_tag = 1, ++ .self_init = true, ++ .inclusive = true, ++ .complex_indexing = false, ++ }, ++}; ++ + static const CPUCaches epyc_milan_cache_info = { + .l1d_cache = &(CPUCacheInfo) { + .type = DATA_CACHE, +@@ -4523,6 +4623,15 @@ static const X86CPUDefinition builtin_x86_defs[] = { + { /* end of list */ } + } + }, ++ { ++ .version = 4, ++ .props = (PropValue[]) { ++ { "model-id", ++ "AMD EPYC-v4 Processor" }, ++ { /* end of list */ } ++ }, ++ .cache_info = &epyc_v4_cache_info ++ }, + { /* end of list */ } + } + }, +@@ -4642,6 +4751,15 @@ static const X86CPUDefinition builtin_x86_defs[] = { + { /* end of list */ } + } + }, ++ { ++ .version = 3, ++ .props = (PropValue[]) { ++ { "model-id", ++ "AMD EPYC-Rome-v3 Processor" }, ++ { /* end of list */ } ++ }, ++ .cache_info = &epyc_rome_v3_cache_info ++ }, + { /* end of list */ } + } + }, +-- +2.45.1.windows.1 + diff --git a/target-i386-allow-versioned-CPUs-to-specify-new-cach.patch b/target-i386-allow-versioned-CPUs-to-specify-new-cach.patch new file mode 100644 index 00000000..4aec2f7e --- /dev/null +++ b/target-i386-allow-versioned-CPUs-to-specify-new-cach.patch @@ -0,0 +1,107 @@ +From e06155ba57d41604c66d849ed2032e66f35215ac Mon Sep 17 00:00:00 2001 +From: Michael Roth +Date: Thu, 4 May 2023 15:53:06 -0500 +Subject: [PATCH] target/i386: allow versioned CPUs to specify new cache_info + +mainline inclusion +from mainline-8.1.0 +commit cca0a000d06f897411a8af4402e5d0522bbe450b +category: feature +bugzilla: https://gitee.com/openeuler/qemu/issues/IAUSKJ +Reference: https://gitlab.com/qemu-project/qemu/-/commit/cca0a000d06f897411a8af4402e5d0522bbe450b + +commit cca0a000d06f897411a8af4402e5d0522bbe450b upstream + +New EPYC CPUs versions require small changes to their cache_info's. +Because current QEMU x86 CPU definition does not support versioned +cach_info, we would have to declare a new CPU type for each such case. +To avoid the dup work, add "cache_info" in X86CPUVersionDefinition", +to allow new cache_info pointers to be specified for a new CPU version. + +Co-developed-by: Wei Huang +Signed-off-by: Wei Huang +Signed-off-by: Michael Roth +Signed-off-by: Babu Moger +Acked-by: Michael S. Tsirkin +Message-Id: <20230504205313.225073-2-babu.moger@amd.com> +Signed-off-by: Paolo Bonzini +--- + target/i386/cpu.c | 35 ++++++++++++++++++++++++++++++++--- + 1 file changed, 32 insertions(+), 3 deletions(-) + +diff --git a/target/i386/cpu.c b/target/i386/cpu.c +index 4473e0923e..60df10c954 100644 +--- a/target/i386/cpu.c ++++ b/target/i386/cpu.c +@@ -1624,6 +1624,7 @@ typedef struct X86CPUVersionDefinition { + const char *alias; + const char *note; + PropValue *props; ++ const CPUCaches *const cache_info; + } X86CPUVersionDefinition; + + /* Base definition for a CPU model */ +@@ -5570,6 +5571,31 @@ static void x86_cpu_apply_version_props(X86CPU *cpu, X86CPUModel *model) + assert(vdef->version == version); + } + ++static const CPUCaches *x86_cpu_get_versioned_cache_info(X86CPU *cpu, ++ X86CPUModel *model) ++{ ++ const X86CPUVersionDefinition *vdef; ++ X86CPUVersion version = x86_cpu_model_resolve_version(model); ++ const CPUCaches *cache_info = model->cpudef->cache_info; ++ ++ if (version == CPU_VERSION_LEGACY) { ++ return cache_info; ++ } ++ ++ for (vdef = x86_cpu_def_get_versions(model->cpudef); vdef->version; vdef++) { ++ if (vdef->cache_info) { ++ cache_info = vdef->cache_info; ++ } ++ ++ if (vdef->version == version) { ++ break; ++ } ++ } ++ ++ assert(vdef->version == version); ++ return cache_info; ++} ++ + /* + * Load data from X86CPUDefinition into a X86CPU object. + * Only for builtin_x86_defs models initialized with x86_register_cpudef_types. +@@ -5602,7 +5628,7 @@ static void x86_cpu_load_model(X86CPU *cpu, X86CPUModel *model) + } + + /* legacy-cache defaults to 'off' if CPU model provides cache info */ +- cpu->legacy_cache = !def->cache_info; ++ cpu->legacy_cache = !x86_cpu_get_versioned_cache_info(cpu, model); + + env->features[FEAT_1_ECX] |= CPUID_EXT_HYPERVISOR; + +@@ -7046,14 +7072,17 @@ static void x86_cpu_realizefn(DeviceState *dev, Error **errp) + + /* Cache information initialization */ + if (!cpu->legacy_cache) { +- if (!xcc->model || !xcc->model->cpudef->cache_info) { ++ const CPUCaches *cache_info = ++ x86_cpu_get_versioned_cache_info(cpu, xcc->model); ++ ++ if (!xcc->model || !cache_info) { + g_autofree char *name = x86_cpu_class_get_model_name(xcc); + error_setg(errp, + "CPU model '%s' doesn't support legacy-cache=off", name); + return; + } + env->cache_info_cpuid2 = env->cache_info_cpuid4 = env->cache_info_amd = +- *xcc->model->cpudef->cache_info; ++ *cache_info; + } else { + /* Build legacy cache information */ + env->cache_info_cpuid2.l1d_cache = &legacy_l1d_cache; +-- +2.45.1.windows.1 + -- Gitee