From 441db31dd9d35bd07a71b5ac753989b0611b64d1 Mon Sep 17 00:00:00 2001 From: zhangpengrui Date: Fri, 5 Sep 2025 10:51:31 +0800 Subject: [PATCH] QEMU update to version 8.2.0-41 Signed-off-by: zhangpengrui --- ...-set-vms-bootinfo.confidential-in-vi.patch | 33 ++++ ...-build.c-Migrate-fw_cfg-creation-to-.patch | 180 ++++++++++++++++++ ...-build.c-Migrate-virtio-creation-to-.patch | 158 +++++++++++++++ ...rovm.c-Use-common-function-to-add-vi.patch | 57 ++++++ ...ex-Define-properties-for-MMIO-ranges.patch | 128 +++++++++++++ ...ke-few-IMSIC-macros-and-functions-pu.patch | 117 ++++++++++++ ...-Update-GPEX-MMIO-related-properties.patch | 117 ++++++++++++ ...cpi-build.c-Add-AIA-support-in-RINTC.patch | 114 +++++++++++ ...t-acpi-build.c-Add-APLIC-in-the-MADT.patch | 76 ++++++++ ...pi-build.c-Add-CMO-information-in-RH.patch | 131 +++++++++++++ ...t-acpi-build.c-Add-IMSIC-in-the-MADT.patch | 76 ++++++++ ...pi-build.c-Add-IO-controllers-and-de.patch | 160 ++++++++++++++++ ...rt-acpi-build.c-Add-MMU-node-in-RHCT.patch | 102 ++++++++++ ...v-virt-acpi-build.c-Add-PLIC-in-MADT.patch | 72 +++++++ ...pi-build.c-Add-SRAT-and-SLIT-ACPI-ta.patch | 112 +++++++++++ ...pi-build.c-Add-namespace-devices-for.patch | 78 ++++++++ ...irt-acpi-build.c-Generate-SPCR-table.patch | 78 ++++++++ ...pi-build.c-Update-the-HID-of-RISC-V-.patch | 41 ++++ ...fix-the-interrupts-extended-property.patch | 92 +++++++++ ...ix-deadlock-when-resetting-uninstall.patch | 39 ++++ qemu.spec | 48 ++++- ...uffer-overrun-when-using-path-option.patch | 42 ++++ ...Refine-VMX-controls-setting-for-back.patch | 68 +++++++ 23 files changed, 2118 insertions(+), 1 deletion(-) create mode 100644 Bugfix-Correctly-set-vms-bootinfo.confidential-in-vi.patch create mode 100644 hw-arm-virt-acpi-build.c-Migrate-fw_cfg-creation-to-.patch create mode 100644 hw-arm-virt-acpi-build.c-Migrate-virtio-creation-to-.patch create mode 100644 hw-i386-acpi-microvm.c-Use-common-function-to-add-vi.patch create mode 100644 hw-pci-host-gpex-Define-properties-for-MMIO-ranges.patch create mode 100644 hw-riscv-virt-Make-few-IMSIC-macros-and-functions-pu.patch create mode 100644 hw-riscv-virt-Update-GPEX-MMIO-related-properties.patch create mode 100644 hw-riscv-virt-acpi-build.c-Add-AIA-support-in-RINTC.patch create mode 100644 hw-riscv-virt-acpi-build.c-Add-APLIC-in-the-MADT.patch create mode 100644 hw-riscv-virt-acpi-build.c-Add-CMO-information-in-RH.patch create mode 100644 hw-riscv-virt-acpi-build.c-Add-IMSIC-in-the-MADT.patch create mode 100644 hw-riscv-virt-acpi-build.c-Add-IO-controllers-and-de.patch create mode 100644 hw-riscv-virt-acpi-build.c-Add-MMU-node-in-RHCT.patch create mode 100644 hw-riscv-virt-acpi-build.c-Add-PLIC-in-MADT.patch create mode 100644 hw-riscv-virt-acpi-build.c-Add-SRAT-and-SLIT-ACPI-ta.patch create mode 100644 hw-riscv-virt-acpi-build.c-Add-namespace-devices-for.patch create mode 100644 hw-riscv-virt-acpi-build.c-Generate-SPCR-table.patch create mode 100644 hw-riscv-virt-acpi-build.c-Update-the-HID-of-RISC-V-.patch create mode 100644 hw-riscv-virt.c-fix-the-interrupts-extended-property.patch create mode 100644 plugins-loader-fix-deadlock-when-resetting-uninstall.patch create mode 100644 smbios-Fix-buffer-overrun-when-using-path-option.patch create mode 100644 target-i386-kvm-Refine-VMX-controls-setting-for-back.patch diff --git a/Bugfix-Correctly-set-vms-bootinfo.confidential-in-vi.patch b/Bugfix-Correctly-set-vms-bootinfo.confidential-in-vi.patch new file mode 100644 index 0000000..8a2af28 --- /dev/null +++ b/Bugfix-Correctly-set-vms-bootinfo.confidential-in-vi.patch @@ -0,0 +1,33 @@ +From 07e397a40e7f33ca980b29ba6c8b6de0c7419991 Mon Sep 17 00:00:00 2001 +From: yxk +Date: Wed, 20 Aug 2025 03:22:03 +0800 +Subject: [PATCH] Bugfix: Correctly set vms->bootinfo.confidential in virtCCA + senarios. + +Both CCA and virtCCA senarios can set vms->bootinfo.confidential in +hw/arm/virt.c. + +Signed-off-by: yxk +--- + hw/arm/virt.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/hw/arm/virt.c b/hw/arm/virt.c +index f12bc645d2..cf4156ed49 100644 +--- a/hw/arm/virt.c ++++ b/hw/arm/virt.c +@@ -2930,9 +2930,9 @@ static void machvirt_init(MachineState *machine) + vms->bootinfo.firmware_loaded = firmware_loaded; + vms->bootinfo.firmware_base = vms->memmap[VIRT_FLASH].base; + vms->bootinfo.firmware_max_size = vms->memmap[VIRT_FLASH].size; +- vms->bootinfo.confidential = virtcca_cvm_enabled(); + vms->bootinfo.psci_conduit = vms->psci_conduit; +- vms->bootinfo.confidential = virt_machine_is_confidential(vms); ++ vms->bootinfo.confidential = virt_machine_is_confidential(vms) || ++ virtcca_cvm_enabled(); + vms->bootinfo.skip_bootloader = vms->bootinfo.confidential; + arm_load_kernel(ARM_CPU(first_cpu), machine, &vms->bootinfo); + +-- +2.33.0 + diff --git a/hw-arm-virt-acpi-build.c-Migrate-fw_cfg-creation-to-.patch b/hw-arm-virt-acpi-build.c-Migrate-fw_cfg-creation-to-.patch new file mode 100644 index 0000000..10b2a1d --- /dev/null +++ b/hw-arm-virt-acpi-build.c-Migrate-fw_cfg-creation-to-.patch @@ -0,0 +1,180 @@ +From 948c605badb09d87eb439a711940d932d07cdd1e Mon Sep 17 00:00:00 2001 +From: yechao-w +Date: Mon, 4 Aug 2025 20:59:24 +0800 +Subject: [PATCH 01/18] hw/arm/virt-acpi-build.c: Migrate fw_cfg creation to + common location + +commit 4c7f4f4f0516ad1bad45b011235202f5be6899de upstream + +RISC-V also needs to use the same code to create fw_cfg in DSDT. So, +avoid code duplication by moving the code in arm and riscv to a device +specific file. + +Suggested-by: Igor Mammedov +Signed-off-by: Sunil V L +Reviewed-by: Daniel Henrique Barboza +Reviewed-by: Alistair Francis +Reviewed-by: Andrew Jones +Acked-by: Michael S. Tsirkin +Message-ID: <20231218150247.466427-2-sunilvl@ventanamicro.com> +Signed-off-by: Alistair Francis +--- + hw/arm/virt-acpi-build.c | 19 ++----------------- + hw/nvram/fw_cfg-acpi.c | 23 +++++++++++++++++++++++ + hw/nvram/meson.build | 1 + + hw/riscv/virt-acpi-build.c | 19 ++----------------- + include/hw/nvram/fw_cfg_acpi.h | 15 +++++++++++++++ + 5 files changed, 43 insertions(+), 34 deletions(-) + create mode 100644 hw/nvram/fw_cfg-acpi.c + create mode 100644 include/hw/nvram/fw_cfg_acpi.h + +diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c +index 5e949671a1..81ca26c052 100644 +--- a/hw/arm/virt-acpi-build.c ++++ b/hw/arm/virt-acpi-build.c +@@ -35,7 +35,7 @@ + #include "target/arm/cpu.h" + #include "hw/acpi/acpi-defs.h" + #include "hw/acpi/acpi.h" +-#include "hw/nvram/fw_cfg.h" ++#include "hw/nvram/fw_cfg_acpi.h" + #include "hw/acpi/bios-linker-loader.h" + #include "hw/acpi/aml-build.h" + #include "hw/acpi/utils.h" +@@ -341,21 +341,6 @@ static void acpi_dsdt_add_uart(Aml *scope, const MemMapEntry *uart_memmap, + aml_append(scope, dev); + } + +-static void acpi_dsdt_add_fw_cfg(Aml *scope, const MemMapEntry *fw_cfg_memmap) +-{ +- Aml *dev = aml_device("FWCF"); +- aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0002"))); +- /* device present, functioning, decoding, not shown in UI */ +- aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); +- aml_append(dev, aml_name_decl("_CCA", aml_int(1))); +- +- Aml *crs = aml_resource_template(); +- aml_append(crs, aml_memory32_fixed(fw_cfg_memmap->base, +- fw_cfg_memmap->size, AML_READ_WRITE)); +- aml_append(dev, aml_name_decl("_CRS", crs)); +- aml_append(scope, dev); +-} +- + static void acpi_dsdt_add_flash(Aml *scope, const MemMapEntry *flash_memmap) + { + Aml *dev, *crs; +@@ -1318,7 +1303,7 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) + if (vmc->acpi_expose_flash) { + acpi_dsdt_add_flash(scope, &memmap[VIRT_FLASH]); + } +- acpi_dsdt_add_fw_cfg(scope, &memmap[VIRT_FW_CFG]); ++ fw_cfg_acpi_dsdt_add(scope, &memmap[VIRT_FW_CFG]); + acpi_dsdt_add_virtio(scope, &memmap[VIRT_MMIO], + (irqmap[VIRT_MMIO] + ARM_SPI_BASE), NUM_VIRTIO_TRANSPORTS); + acpi_dsdt_add_pci(scope, memmap, irqmap[VIRT_PCIE] + ARM_SPI_BASE, vms); +diff --git a/hw/nvram/fw_cfg-acpi.c b/hw/nvram/fw_cfg-acpi.c +new file mode 100644 +index 0000000000..4e48baeaa0 +--- /dev/null ++++ b/hw/nvram/fw_cfg-acpi.c +@@ -0,0 +1,23 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * Add fw_cfg device in DSDT ++ * ++ */ ++ ++#include "hw/nvram/fw_cfg_acpi.h" ++#include "hw/acpi/aml-build.h" ++ ++void fw_cfg_acpi_dsdt_add(Aml *scope, const MemMapEntry *fw_cfg_memmap) ++{ ++ Aml *dev = aml_device("FWCF"); ++ aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0002"))); ++ /* device present, functioning, decoding, not shown in UI */ ++ aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); ++ aml_append(dev, aml_name_decl("_CCA", aml_int(1))); ++ ++ Aml *crs = aml_resource_template(); ++ aml_append(crs, aml_memory32_fixed(fw_cfg_memmap->base, ++ fw_cfg_memmap->size, AML_READ_WRITE)); ++ aml_append(dev, aml_name_decl("_CRS", crs)); ++ aml_append(scope, dev); ++} +diff --git a/hw/nvram/meson.build b/hw/nvram/meson.build +index 75e415b1a0..4996c72456 100644 +--- a/hw/nvram/meson.build ++++ b/hw/nvram/meson.build +@@ -17,3 +17,4 @@ system_ss.add(when: 'CONFIG_XLNX_EFUSE_ZYNQMP', if_true: files( + system_ss.add(when: 'CONFIG_XLNX_BBRAM', if_true: files('xlnx-bbram.c')) + + specific_ss.add(when: 'CONFIG_PSERIES', if_true: files('spapr_nvram.c')) ++specific_ss.add(when: 'CONFIG_ACPI', if_true: files('fw_cfg-acpi.c')) +diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c +index 7331248f59..d8772c2821 100644 +--- a/hw/riscv/virt-acpi-build.c ++++ b/hw/riscv/virt-acpi-build.c +@@ -28,6 +28,7 @@ + #include "hw/acpi/acpi.h" + #include "hw/acpi/aml-build.h" + #include "hw/acpi/utils.h" ++#include "hw/nvram/fw_cfg_acpi.h" + #include "qapi/error.h" + #include "qemu/error-report.h" + #include "sysemu/reset.h" +@@ -97,22 +98,6 @@ static void acpi_dsdt_add_cpus(Aml *scope, RISCVVirtState *s) + } + } + +-static void acpi_dsdt_add_fw_cfg(Aml *scope, const MemMapEntry *fw_cfg_memmap) +-{ +- Aml *dev = aml_device("FWCF"); +- aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0002"))); +- +- /* device present, functioning, decoding, not shown in UI */ +- aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); +- aml_append(dev, aml_name_decl("_CCA", aml_int(1))); +- +- Aml *crs = aml_resource_template(); +- aml_append(crs, aml_memory32_fixed(fw_cfg_memmap->base, +- fw_cfg_memmap->size, AML_READ_WRITE)); +- aml_append(dev, aml_name_decl("_CRS", crs)); +- aml_append(scope, dev); +-} +- + /* RHCT Node[N] starts at offset 56 */ + #define RHCT_NODE_ARRAY_OFFSET 56 + +@@ -226,7 +211,7 @@ static void build_dsdt(GArray *table_data, + scope = aml_scope("\\_SB"); + acpi_dsdt_add_cpus(scope, s); + +- acpi_dsdt_add_fw_cfg(scope, &memmap[VIRT_FW_CFG]); ++ fw_cfg_acpi_dsdt_add(scope, &memmap[VIRT_FW_CFG]); + + aml_append(dsdt, scope); + +diff --git a/include/hw/nvram/fw_cfg_acpi.h b/include/hw/nvram/fw_cfg_acpi.h +new file mode 100644 +index 0000000000..b6553d86fc +--- /dev/null ++++ b/include/hw/nvram/fw_cfg_acpi.h +@@ -0,0 +1,15 @@ ++/* SPDX-License-Identifier: GPL-2.0+ */ ++/* ++ * ACPI support for fw_cfg ++ * ++ */ ++ ++#ifndef FW_CFG_ACPI_H ++#define FW_CFG_ACPI_H ++ ++#include "qemu/osdep.h" ++#include "exec/hwaddr.h" ++ ++void fw_cfg_acpi_dsdt_add(Aml *scope, const MemMapEntry *fw_cfg_memmap); ++ ++#endif +-- +2.33.0 + diff --git a/hw-arm-virt-acpi-build.c-Migrate-virtio-creation-to-.patch b/hw-arm-virt-acpi-build.c-Migrate-virtio-creation-to-.patch new file mode 100644 index 0000000..da6031d --- /dev/null +++ b/hw-arm-virt-acpi-build.c-Migrate-virtio-creation-to-.patch @@ -0,0 +1,158 @@ +From 4339104293871dba77a50502357ed96962edae2c Mon Sep 17 00:00:00 2001 +From: yechao-w +Date: Mon, 4 Aug 2025 20:59:25 +0800 +Subject: [PATCH 02/18] hw/arm/virt-acpi-build.c: Migrate virtio creation to + common location + +commit 57ba8436282940b59d9a069cc01a601bbc8036c5 upstream + +RISC-V also needs to create the virtio in DSDT in the same way as ARM. +So, instead of duplicating the code, move this function to the device +specific file which is common across architectures. + +Suggested-by: Igor Mammedov +Signed-off-by: Sunil V L +Reviewed-by: Alistair Francis +Reviewed-by: Andrew Jones +Acked-by: Michael S. Tsirkin +Message-ID: <20231218150247.466427-3-sunilvl@ventanamicro.com> +Signed-off-by: Alistair Francis +--- + hw/arm/virt-acpi-build.c | 32 ++++---------------------------- + hw/virtio/meson.build | 1 + + hw/virtio/virtio-acpi.c | 33 +++++++++++++++++++++++++++++++++ + include/hw/virtio/virtio-acpi.h | 16 ++++++++++++++++ + 4 files changed, 54 insertions(+), 28 deletions(-) + create mode 100644 hw/virtio/virtio-acpi.c + create mode 100644 include/hw/virtio/virtio-acpi.h + +diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c +index 81ca26c052..b389ef7622 100644 +--- a/hw/arm/virt-acpi-build.c ++++ b/hw/arm/virt-acpi-build.c +@@ -59,6 +59,7 @@ + #include "hw/acpi/ghes.h" + #include "hw/acpi/viot.h" + #include "kvm_arm.h" ++#include "hw/virtio/virtio-acpi.h" + + #define ARM_SPI_BASE 32 + +@@ -365,32 +366,6 @@ static void acpi_dsdt_add_flash(Aml *scope, const MemMapEntry *flash_memmap) + aml_append(scope, dev); + } + +-static void acpi_dsdt_add_virtio(Aml *scope, +- const MemMapEntry *virtio_mmio_memmap, +- uint32_t mmio_irq, int num) +-{ +- hwaddr base = virtio_mmio_memmap->base; +- hwaddr size = virtio_mmio_memmap->size; +- int i; +- +- for (i = 0; i < num; i++) { +- uint32_t irq = mmio_irq + i; +- Aml *dev = aml_device("VR%02u", i); +- aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0005"))); +- aml_append(dev, aml_name_decl("_UID", aml_int(i))); +- aml_append(dev, aml_name_decl("_CCA", aml_int(1))); +- +- Aml *crs = aml_resource_template(); +- aml_append(crs, aml_memory32_fixed(base, size, AML_READ_WRITE)); +- aml_append(crs, +- aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, +- AML_EXCLUSIVE, &irq, 1)); +- aml_append(dev, aml_name_decl("_CRS", crs)); +- aml_append(scope, dev); +- base += size; +- } +-} +- + static void acpi_dsdt_add_hisi_sec(Aml *scope, + const MemMapEntry *virtio_mmio_memmap, + int dev_id) +@@ -1304,8 +1279,9 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) + acpi_dsdt_add_flash(scope, &memmap[VIRT_FLASH]); + } + fw_cfg_acpi_dsdt_add(scope, &memmap[VIRT_FW_CFG]); +- acpi_dsdt_add_virtio(scope, &memmap[VIRT_MMIO], +- (irqmap[VIRT_MMIO] + ARM_SPI_BASE), NUM_VIRTIO_TRANSPORTS); ++ virtio_acpi_dsdt_add(scope, memmap[VIRT_MMIO].base, memmap[VIRT_MMIO].size, ++ (irqmap[VIRT_MMIO] + ARM_SPI_BASE), ++ 0, NUM_VIRTIO_TRANSPORTS); + acpi_dsdt_add_pci(scope, memmap, irqmap[VIRT_PCIE] + ARM_SPI_BASE, vms); + + if (virtcca_cvm_enabled()) { +diff --git a/hw/virtio/meson.build b/hw/virtio/meson.build +index 67291563d3..7f29622099 100644 +--- a/hw/virtio/meson.build ++++ b/hw/virtio/meson.build +@@ -79,3 +79,4 @@ system_ss.add(when: 'CONFIG_ALL', if_true: files('virtio-stub.c')) + system_ss.add(files('virtio-hmp-cmds.c')) + + specific_ss.add_all(when: 'CONFIG_VIRTIO', if_true: specific_virtio_ss) ++system_ss.add(when: 'CONFIG_ACPI', if_true: files('virtio-acpi.c')) +diff --git a/hw/virtio/virtio-acpi.c b/hw/virtio/virtio-acpi.c +new file mode 100644 +index 0000000000..e18cb38bdb +--- /dev/null ++++ b/hw/virtio/virtio-acpi.c +@@ -0,0 +1,33 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * virtio ACPI Support ++ * ++ */ ++ ++#include "hw/virtio/virtio-acpi.h" ++#include "hw/acpi/aml-build.h" ++ ++void virtio_acpi_dsdt_add(Aml *scope, const hwaddr base, const hwaddr size, ++ uint32_t mmio_irq, long int start_index, int num) ++{ ++ hwaddr virtio_base = base; ++ uint32_t irq = mmio_irq; ++ long int i; ++ ++ for (i = start_index; i < start_index + num; i++) { ++ Aml *dev = aml_device("VR%02u", (unsigned)i); ++ aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0005"))); ++ aml_append(dev, aml_name_decl("_UID", aml_int(i))); ++ aml_append(dev, aml_name_decl("_CCA", aml_int(1))); ++ ++ Aml *crs = aml_resource_template(); ++ aml_append(crs, aml_memory32_fixed(virtio_base, size, AML_READ_WRITE)); ++ aml_append(crs, ++ aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, ++ AML_EXCLUSIVE, &irq, 1)); ++ aml_append(dev, aml_name_decl("_CRS", crs)); ++ aml_append(scope, dev); ++ virtio_base += size; ++ irq++; ++ } ++} +diff --git a/include/hw/virtio/virtio-acpi.h b/include/hw/virtio/virtio-acpi.h +new file mode 100644 +index 0000000000..844e102569 +--- /dev/null ++++ b/include/hw/virtio/virtio-acpi.h +@@ -0,0 +1,16 @@ ++/* SPDX-License-Identifier: GPL-2.0+ */ ++/* ++ * ACPI support for virtio ++ */ ++ ++#ifndef VIRTIO_ACPI_H ++#define VIRTIO_ACPI_H ++ ++#include "qemu/osdep.h" ++#include "exec/hwaddr.h" ++ ++void virtio_acpi_dsdt_add(Aml *scope, const hwaddr virtio_mmio_base, ++ const hwaddr virtio_mmio_size, uint32_t mmio_irq, ++ long int start_index, int num); ++ ++#endif +-- +2.33.0 + diff --git a/hw-i386-acpi-microvm.c-Use-common-function-to-add-vi.patch b/hw-i386-acpi-microvm.c-Use-common-function-to-add-vi.patch new file mode 100644 index 0000000..ea0ba79 --- /dev/null +++ b/hw-i386-acpi-microvm.c-Use-common-function-to-add-vi.patch @@ -0,0 +1,57 @@ +From be7b030b8ae20a284aee2ab41f49337db3ebe48d Mon Sep 17 00:00:00 2001 +From: yechao-w +Date: Mon, 4 Aug 2025 20:59:26 +0800 +Subject: [PATCH 03/18] hw/i386/acpi-microvm.c: Use common function to add + virtio in DSDT + +commit 8199bf48ea1fdb8e491311a0dc28cea30af18c95 uptream + +With common function to add virtio in DSDT created now, update microvm +code also to use it instead of duplicate code. + +Suggested-by: Andrew Jones +Signed-off-by: Sunil V L +Acked-by: Alistair Francis +Acked-by: Michael S. Tsirkin +Message-ID: <20231218150247.466427-4-sunilvl@ventanamicro.com> +Signed-off-by: Alistair Francis +--- + hw/i386/acpi-microvm.c | 15 ++------------- + 1 file changed, 2 insertions(+), 13 deletions(-) + +diff --git a/hw/i386/acpi-microvm.c b/hw/i386/acpi-microvm.c +index 2909a73933..279da6b4aa 100644 +--- a/hw/i386/acpi-microvm.c ++++ b/hw/i386/acpi-microvm.c +@@ -37,6 +37,7 @@ + #include "hw/pci/pci.h" + #include "hw/pci/pcie_host.h" + #include "hw/usb/xhci.h" ++#include "hw/virtio/virtio-acpi.h" + #include "hw/virtio/virtio-mmio.h" + #include "hw/input/i8042.h" + +@@ -77,19 +78,7 @@ static void acpi_dsdt_add_virtio(Aml *scope, + uint32_t irq = mms->virtio_irq_base + index; + hwaddr base = VIRTIO_MMIO_BASE + index * 512; + hwaddr size = 512; +- +- Aml *dev = aml_device("VR%02u", (unsigned)index); +- aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0005"))); +- aml_append(dev, aml_name_decl("_UID", aml_int(index))); +- aml_append(dev, aml_name_decl("_CCA", aml_int(1))); +- +- Aml *crs = aml_resource_template(); +- aml_append(crs, aml_memory32_fixed(base, size, AML_READ_WRITE)); +- aml_append(crs, +- aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, +- AML_EXCLUSIVE, &irq, 1)); +- aml_append(dev, aml_name_decl("_CRS", crs)); +- aml_append(scope, dev); ++ virtio_acpi_dsdt_add(scope, base, size, irq, index, 1); + } + } + } +-- +2.33.0 + diff --git a/hw-pci-host-gpex-Define-properties-for-MMIO-ranges.patch b/hw-pci-host-gpex-Define-properties-for-MMIO-ranges.patch new file mode 100644 index 0000000..787bd0e --- /dev/null +++ b/hw-pci-host-gpex-Define-properties-for-MMIO-ranges.patch @@ -0,0 +1,128 @@ +From 7ec434a0f9935a7a6a14896140f33c7e1436111e Mon Sep 17 00:00:00 2001 +From: yechao-w +Date: Mon, 4 Aug 2025 20:59:34 +0800 +Subject: [PATCH 10/18] hw/pci-host/gpex: Define properties for MMIO ranges + +commit 8f6a4874887c226b0df35f5b78fa77f197507d96 upstream + +ACPI DSDT generator needs information like ECAM range, PIO range, 32-bit +and 64-bit PCI MMIO range etc related to the PCI host bridge. Instead of +making these values machine specific, create properties for the GPEX +host bridge with default value 0. During initialization, the firmware +can initialize these properties with correct values for the platform. +This basically allows DSDT generator code independent of the machine +specific memory map accesses. + +Suggested-by: Igor Mammedov +Signed-off-by: Sunil V L +Acked-by: Alistair Francis +Acked-by: Michael S. Tsirkin +Reviewed-by: Daniel Henrique Barboza +Message-ID: <20231218150247.466427-11-sunilvl@ventanamicro.com> +Signed-off-by: Alistair Francis +--- + hw/pci-host/gpex-acpi.c | 13 +++++++++++++ + hw/pci-host/gpex.c | 12 ++++++++++++ + include/hw/pci-host/gpex.h | 30 +++++++++++++++++++++--------- + 3 files changed, 46 insertions(+), 9 deletions(-) + +diff --git a/hw/pci-host/gpex-acpi.c b/hw/pci-host/gpex-acpi.c +index 162f6221ab..020ded0ff6 100644 +--- a/hw/pci-host/gpex-acpi.c ++++ b/hw/pci-host/gpex-acpi.c +@@ -296,3 +296,16 @@ void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig *cfg) + + crs_range_set_free(&crs_range_set); + } ++ ++void acpi_dsdt_add_gpex_host(Aml *scope, uint32_t irq) ++{ ++ bool ambig; ++ Object *obj = object_resolve_path_type("", TYPE_GPEX_HOST, &ambig); ++ ++ if (!obj || ambig) { ++ return; ++ } ++ ++ GPEX_HOST(obj)->gpex_cfg.irq = irq; ++ acpi_dsdt_add_gpex(scope, &GPEX_HOST(obj)->gpex_cfg); ++} +diff --git a/hw/pci-host/gpex.c b/hw/pci-host/gpex.c +index a6752fac5e..41f4e73f6e 100644 +--- a/hw/pci-host/gpex.c ++++ b/hw/pci-host/gpex.c +@@ -154,6 +154,18 @@ static Property gpex_host_properties[] = { + */ + DEFINE_PROP_BOOL("allow-unmapped-accesses", GPEXHost, + allow_unmapped_accesses, true), ++ DEFINE_PROP_UINT64(PCI_HOST_ECAM_BASE, GPEXHost, gpex_cfg.ecam.base, 0), ++ DEFINE_PROP_SIZE(PCI_HOST_ECAM_SIZE, GPEXHost, gpex_cfg.ecam.size, 0), ++ DEFINE_PROP_UINT64(PCI_HOST_PIO_BASE, GPEXHost, gpex_cfg.pio.base, 0), ++ DEFINE_PROP_SIZE(PCI_HOST_PIO_SIZE, GPEXHost, gpex_cfg.pio.size, 0), ++ DEFINE_PROP_UINT64(PCI_HOST_BELOW_4G_MMIO_BASE, GPEXHost, ++ gpex_cfg.mmio32.base, 0), ++ DEFINE_PROP_SIZE(PCI_HOST_BELOW_4G_MMIO_SIZE, GPEXHost, ++ gpex_cfg.mmio32.size, 0), ++ DEFINE_PROP_UINT64(PCI_HOST_ABOVE_4G_MMIO_BASE, GPEXHost, ++ gpex_cfg.mmio64.base, 0), ++ DEFINE_PROP_SIZE(PCI_HOST_ABOVE_4G_MMIO_SIZE, GPEXHost, ++ gpex_cfg.mmio64.size, 0), + DEFINE_PROP_END_OF_LIST(), + }; + +diff --git a/include/hw/pci-host/gpex.h b/include/hw/pci-host/gpex.h +index 65475f7f9d..c414ae5190 100644 +--- a/include/hw/pci-host/gpex.h ++++ b/include/hw/pci-host/gpex.h +@@ -40,6 +40,16 @@ struct GPEXRootState { + /*< public >*/ + }; + ++struct GPEXConfig { ++ MemMapEntry ecam; ++ MemMapEntry mmio32; ++ MemMapEntry mmio64; ++ MemMapEntry pio; ++ int irq; ++ PCIBus *bus; ++ bool preserve_config; ++}; ++ + struct GPEXHost { + /*< private >*/ + PCIExpressHost parent_obj; +@@ -55,20 +65,22 @@ struct GPEXHost { + int irq_num[GPEX_NUM_IRQS]; + + bool allow_unmapped_accesses; +-}; + +-struct GPEXConfig { +- MemMapEntry ecam; +- MemMapEntry mmio32; +- MemMapEntry mmio64; +- MemMapEntry pio; +- int irq; +- PCIBus *bus; +- bool preserve_config; ++ struct GPEXConfig gpex_cfg; + }; + + int gpex_set_irq_num(GPEXHost *s, int index, int gsi); + + void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig *cfg); ++void acpi_dsdt_add_gpex_host(Aml *scope, uint32_t irq); ++ ++#define PCI_HOST_PIO_BASE "x-pio-base" ++#define PCI_HOST_PIO_SIZE "x-pio-size" ++#define PCI_HOST_ECAM_BASE "x-ecam-base" ++#define PCI_HOST_ECAM_SIZE "x-ecam-size" ++#define PCI_HOST_BELOW_4G_MMIO_BASE "x-below-4g-mmio-base" ++#define PCI_HOST_BELOW_4G_MMIO_SIZE "x-below-4g-mmio-size" ++#define PCI_HOST_ABOVE_4G_MMIO_BASE "x-above-4g-mmio-base" ++#define PCI_HOST_ABOVE_4G_MMIO_SIZE "x-above-4g-mmio-size" + + #endif /* HW_GPEX_H */ +-- +2.33.0 + diff --git a/hw-riscv-virt-Make-few-IMSIC-macros-and-functions-pu.patch b/hw-riscv-virt-Make-few-IMSIC-macros-and-functions-pu.patch new file mode 100644 index 0000000..d894084 --- /dev/null +++ b/hw-riscv-virt-Make-few-IMSIC-macros-and-functions-pu.patch @@ -0,0 +1,117 @@ +From 2ce3c25215a931f183ad530baba7a07ddd55cfe6 Mon Sep 17 00:00:00 2001 +From: yechao-w +Date: Mon, 4 Aug 2025 20:59:27 +0800 +Subject: [PATCH 04/18] hw/riscv: virt: Make few IMSIC macros and functions + public + +commit 68c8b403c78b8f20acbebba3cdc46320853fe5ca upstream + +Some macros and static function related to IMSIC are defined in virt.c. +They are required in virt-acpi-build.c. So, make them public. + +Signed-off-by: Sunil V L +Reviewed-by: Daniel Henrique Barboza +Reviewed-by: Alistair Francis +Reviewed-by: Andrew Jones +Acked-by: Michael S. Tsirkin +Message-ID: <20231218150247.466427-5-sunilvl@ventanamicro.com> +Signed-off-by: Alistair Francis +--- + hw/riscv/virt.c | 25 +------------------------ + include/hw/riscv/virt.h | 25 +++++++++++++++++++++++++ + 2 files changed, 26 insertions(+), 24 deletions(-) + +diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c +index 9b29ed1108..30b9f8cab6 100644 +--- a/hw/riscv/virt.c ++++ b/hw/riscv/virt.c +@@ -39,7 +39,6 @@ + #include "hw/firmware/smbios.h" + #include "hw/intc/riscv_aclint.h" + #include "hw/intc/riscv_aplic.h" +-#include "hw/intc/riscv_imsic.h" + #include "hw/intc/sifive_plic.h" + #include "hw/misc/sifive_test.h" + #include "hw/platform-bus.h" +@@ -55,28 +54,6 @@ + #include "hw/acpi/aml-build.h" + #include "qapi/qapi-visit-common.h" + +-/* +- * The virt machine physical address space used by some of the devices +- * namely ACLINT, PLIC, APLIC, and IMSIC depend on number of Sockets, +- * number of CPUs, and number of IMSIC guest files. +- * +- * Various limits defined by VIRT_SOCKETS_MAX_BITS, VIRT_CPUS_MAX_BITS, +- * and VIRT_IRQCHIP_MAX_GUESTS_BITS are tuned for maximum utilization +- * of virt machine physical address space. +- */ +- +-#define VIRT_IMSIC_GROUP_MAX_SIZE (1U << IMSIC_MMIO_GROUP_MIN_SHIFT) +-#if VIRT_IMSIC_GROUP_MAX_SIZE < \ +- IMSIC_GROUP_SIZE(VIRT_CPUS_MAX_BITS, VIRT_IRQCHIP_MAX_GUESTS_BITS) +-#error "Can't accommodate single IMSIC group in address space" +-#endif +- +-#define VIRT_IMSIC_MAX_SIZE (VIRT_SOCKETS_MAX * \ +- VIRT_IMSIC_GROUP_MAX_SIZE) +-#if 0x4000000 < VIRT_IMSIC_MAX_SIZE +-#error "Can't accommodate all IMSIC groups in address space" +-#endif +- + /* KVM AIA only supports APLIC MSI. APLIC Wired is always emulated by QEMU. */ + static bool virt_use_kvm_aia(RISCVVirtState *s) + { +@@ -513,7 +490,7 @@ static void create_fdt_socket_plic(RISCVVirtState *s, + g_free(plic_cells); + } + +-static uint32_t imsic_num_bits(uint32_t count) ++uint32_t imsic_num_bits(uint32_t count) + { + uint32_t ret = 0; + +diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h +index e5c474b26e..5b03575ed3 100644 +--- a/include/hw/riscv/virt.h ++++ b/include/hw/riscv/virt.h +@@ -23,6 +23,7 @@ + #include "hw/riscv/riscv_hart.h" + #include "hw/sysbus.h" + #include "hw/block/flash.h" ++#include "hw/intc/riscv_imsic.h" + + #define VIRT_CPUS_MAX_BITS 9 + #define VIRT_CPUS_MAX (1 << VIRT_CPUS_MAX_BITS) +@@ -127,4 +128,28 @@ enum { + + bool virt_is_acpi_enabled(RISCVVirtState *s); + void virt_acpi_setup(RISCVVirtState *vms); ++uint32_t imsic_num_bits(uint32_t count); ++ ++/* ++ * The virt machine physical address space used by some of the devices ++ * namely ACLINT, PLIC, APLIC, and IMSIC depend on number of Sockets, ++ * number of CPUs, and number of IMSIC guest files. ++ * ++ * Various limits defined by VIRT_SOCKETS_MAX_BITS, VIRT_CPUS_MAX_BITS, ++ * and VIRT_IRQCHIP_MAX_GUESTS_BITS are tuned for maximum utilization ++ * of virt machine physical address space. ++ */ ++ ++#define VIRT_IMSIC_GROUP_MAX_SIZE (1U << IMSIC_MMIO_GROUP_MIN_SHIFT) ++#if VIRT_IMSIC_GROUP_MAX_SIZE < \ ++ IMSIC_GROUP_SIZE(VIRT_CPUS_MAX_BITS, VIRT_IRQCHIP_MAX_GUESTS_BITS) ++#error "Can't accomodate single IMSIC group in address space" ++#endif ++ ++#define VIRT_IMSIC_MAX_SIZE (VIRT_SOCKETS_MAX * \ ++ VIRT_IMSIC_GROUP_MAX_SIZE) ++#if 0x4000000 < VIRT_IMSIC_MAX_SIZE ++#error "Can't accomodate all IMSIC groups in address space" ++#endif ++ + #endif +-- +2.33.0 + diff --git a/hw-riscv-virt-Update-GPEX-MMIO-related-properties.patch b/hw-riscv-virt-Update-GPEX-MMIO-related-properties.patch new file mode 100644 index 0000000..818ec89 --- /dev/null +++ b/hw-riscv-virt-Update-GPEX-MMIO-related-properties.patch @@ -0,0 +1,117 @@ +From 9367132cdc0340ebc17d434527818fe87f1f0fa4 Mon Sep 17 00:00:00 2001 +From: yechao-w +Date: Mon, 4 Aug 2025 20:59:35 +0800 +Subject: [PATCH 11/18] hw/riscv/virt: Update GPEX MMIO related properties + +commit e86e95270e2b10e57c69852778452b54b31e1c19 upstream + +Update the GPEX host bridge properties related to MMIO ranges with +values set for the virt machine. + +Suggested-by: Igor Mammedov +Signed-off-by: Sunil V L +Reviewed-by: Alistair Francis +Acked-by: Michael S. Tsirkin +Message-ID: <20231218150247.466427-12-sunilvl@ventanamicro.com> +Signed-off-by: Alistair Francis +--- + hw/riscv/virt.c | 47 ++++++++++++++++++++++++++++------------- + include/hw/riscv/virt.h | 1 + + 2 files changed, 33 insertions(+), 15 deletions(-) + +diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c +index 30b9f8cab6..c47df46bfc 100644 +--- a/hw/riscv/virt.c ++++ b/hw/riscv/virt.c +@@ -1055,21 +1055,45 @@ static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap) + } + + static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem, +- hwaddr ecam_base, hwaddr ecam_size, +- hwaddr mmio_base, hwaddr mmio_size, +- hwaddr high_mmio_base, +- hwaddr high_mmio_size, +- hwaddr pio_base, +- DeviceState *irqchip) ++ DeviceState *irqchip, ++ RISCVVirtState *s) + { + DeviceState *dev; + MemoryRegion *ecam_alias, *ecam_reg; + MemoryRegion *mmio_alias, *high_mmio_alias, *mmio_reg; ++ hwaddr ecam_base = s->memmap[VIRT_PCIE_ECAM].base; ++ hwaddr ecam_size = s->memmap[VIRT_PCIE_ECAM].size; ++ hwaddr mmio_base = s->memmap[VIRT_PCIE_MMIO].base; ++ hwaddr mmio_size = s->memmap[VIRT_PCIE_MMIO].size; ++ hwaddr high_mmio_base = virt_high_pcie_memmap.base; ++ hwaddr high_mmio_size = virt_high_pcie_memmap.size; ++ hwaddr pio_base = s->memmap[VIRT_PCIE_PIO].base; ++ hwaddr pio_size = s->memmap[VIRT_PCIE_PIO].size; + qemu_irq irq; + int i; + + dev = qdev_new(TYPE_GPEX_HOST); + ++ /* Set GPEX object properties for the virt machine */ ++ object_property_set_uint(OBJECT(GPEX_HOST(dev)), PCI_HOST_ECAM_BASE, ++ ecam_base, NULL); ++ object_property_set_int(OBJECT(GPEX_HOST(dev)), PCI_HOST_ECAM_SIZE, ++ ecam_size, NULL); ++ object_property_set_uint(OBJECT(GPEX_HOST(dev)), ++ PCI_HOST_BELOW_4G_MMIO_BASE, ++ mmio_base, NULL); ++ object_property_set_int(OBJECT(GPEX_HOST(dev)), PCI_HOST_BELOW_4G_MMIO_SIZE, ++ mmio_size, NULL); ++ object_property_set_uint(OBJECT(GPEX_HOST(dev)), ++ PCI_HOST_ABOVE_4G_MMIO_BASE, ++ high_mmio_base, NULL); ++ object_property_set_int(OBJECT(GPEX_HOST(dev)), PCI_HOST_ABOVE_4G_MMIO_SIZE, ++ high_mmio_size, NULL); ++ object_property_set_uint(OBJECT(GPEX_HOST(dev)), PCI_HOST_PIO_BASE, ++ pio_base, NULL); ++ object_property_set_int(OBJECT(GPEX_HOST(dev)), PCI_HOST_PIO_SIZE, ++ pio_size, NULL); ++ + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); + + ecam_alias = g_new0(MemoryRegion, 1); +@@ -1100,6 +1124,7 @@ static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem, + gpex_set_irq_num(GPEX_HOST(dev), i, PCIE_IRQ + i); + } + ++ GPEX_HOST(dev)->gpex_cfg.bus = PCI_HOST_BRIDGE(GPEX_HOST(dev))->bus; + return dev; + } + +@@ -1536,15 +1561,7 @@ static void virt_machine_init(MachineState *machine) + qdev_get_gpio_in(virtio_irqchip, VIRTIO_IRQ + i)); + } + +- gpex_pcie_init(system_memory, +- memmap[VIRT_PCIE_ECAM].base, +- memmap[VIRT_PCIE_ECAM].size, +- memmap[VIRT_PCIE_MMIO].base, +- memmap[VIRT_PCIE_MMIO].size, +- virt_high_pcie_memmap.base, +- virt_high_pcie_memmap.size, +- memmap[VIRT_PCIE_PIO].base, +- pcie_irqchip); ++ gpex_pcie_init(system_memory, pcie_irqchip, s); + + create_platform_bus(s, mmio_irqchip); + +diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h +index 5b03575ed3..f89790fd58 100644 +--- a/include/hw/riscv/virt.h ++++ b/include/hw/riscv/virt.h +@@ -61,6 +61,7 @@ struct RISCVVirtState { + char *oem_table_id; + OnOffAuto acpi; + const MemMapEntry *memmap; ++ struct GPEXHost *gpex_host; + }; + + enum { +-- +2.33.0 + diff --git a/hw-riscv-virt-acpi-build.c-Add-AIA-support-in-RINTC.patch b/hw-riscv-virt-acpi-build.c-Add-AIA-support-in-RINTC.patch new file mode 100644 index 0000000..14d6e29 --- /dev/null +++ b/hw-riscv-virt-acpi-build.c-Add-AIA-support-in-RINTC.patch @@ -0,0 +1,114 @@ +From bd3c5ec667493e193db4a2fdf165b96f45af8262 Mon Sep 17 00:00:00 2001 +From: yechao-w +Date: Mon, 4 Aug 2025 20:59:28 +0800 +Subject: [PATCH 05/18] hw/riscv/virt-acpi-build.c: Add AIA support in RINTC + +commit 0efb12b713338e2be713b689d1c9743f7163f85d upstream + +Update the RINTC structure in MADT with AIA related fields. + +Signed-off-by: Sunil V L +Reviewed-by: Daniel Henrique Barboza +Acked-by: Alistair Francis +Reviewed-by: Andrew Jones +Acked-by: Michael S. Tsirkin +Message-ID: <20231218150247.466427-6-sunilvl@ventanamicro.com> +Signed-off-by: Alistair Francis +--- + hw/riscv/virt-acpi-build.c | 43 ++++++++++++++++++++++++++++++++++---- + 1 file changed, 39 insertions(+), 4 deletions(-) + +diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c +index d8772c2821..3f9536356e 100644 +--- a/hw/riscv/virt-acpi-build.c ++++ b/hw/riscv/virt-acpi-build.c +@@ -38,6 +38,7 @@ + #include "hw/intc/riscv_aclint.h" + + #define ACPI_BUILD_TABLE_SIZE 0x20000 ++#define ACPI_BUILD_INTC_ID(socket, index) ((socket << 24) | (index)) + + typedef struct AcpiBuildState { + /* Copy of table in RAM (for patching) */ +@@ -59,17 +60,50 @@ static void acpi_align_size(GArray *blob, unsigned align) + + static void riscv_acpi_madt_add_rintc(uint32_t uid, + const CPUArchIdList *arch_ids, +- GArray *entry) ++ GArray *entry, ++ RISCVVirtState *s) + { ++ uint8_t guest_index_bits = imsic_num_bits(s->aia_guests + 1); + uint64_t hart_id = arch_ids->cpus[uid].arch_id; ++ uint32_t imsic_size, local_cpu_id, socket_id; ++ uint64_t imsic_socket_addr, imsic_addr; ++ MachineState *ms = MACHINE(s); + ++ socket_id = arch_ids->cpus[uid].props.node_id; ++ local_cpu_id = (arch_ids->cpus[uid].arch_id - ++ riscv_socket_first_hartid(ms, socket_id)) % ++ riscv_socket_hart_count(ms, socket_id); ++ imsic_socket_addr = s->memmap[VIRT_IMSIC_S].base + ++ (socket_id * VIRT_IMSIC_GROUP_MAX_SIZE); ++ imsic_size = IMSIC_HART_SIZE(guest_index_bits); ++ imsic_addr = imsic_socket_addr + local_cpu_id * imsic_size; + build_append_int_noprefix(entry, 0x18, 1); /* Type */ +- build_append_int_noprefix(entry, 20, 1); /* Length */ ++ build_append_int_noprefix(entry, 36, 1); /* Length */ + build_append_int_noprefix(entry, 1, 1); /* Version */ + build_append_int_noprefix(entry, 0, 1); /* Reserved */ + build_append_int_noprefix(entry, 0x1, 4); /* Flags */ + build_append_int_noprefix(entry, hart_id, 8); /* Hart ID */ + build_append_int_noprefix(entry, uid, 4); /* ACPI Processor UID */ ++ /* External Interrupt Controller ID */ ++ if (s->aia_type == VIRT_AIA_TYPE_APLIC) { ++ build_append_int_noprefix(entry, ++ ACPI_BUILD_INTC_ID( ++ arch_ids->cpus[uid].props.node_id, ++ local_cpu_id), ++ 4); ++ } else { ++ build_append_int_noprefix(entry, 0, 4); ++ } ++ ++ if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) { ++ /* IMSIC Base address */ ++ build_append_int_noprefix(entry, imsic_addr, 8); ++ /* IMSIC Size */ ++ build_append_int_noprefix(entry, imsic_size, 4); ++ } else { ++ build_append_int_noprefix(entry, 0, 8); ++ build_append_int_noprefix(entry, 0, 4); ++ } + } + + static void acpi_dsdt_add_cpus(Aml *scope, RISCVVirtState *s) +@@ -88,7 +122,7 @@ static void acpi_dsdt_add_cpus(Aml *scope, RISCVVirtState *s) + aml_int(arch_ids->cpus[i].arch_id))); + + /* build _MAT object */ +- riscv_acpi_madt_add_rintc(i, arch_ids, madt_buf); ++ riscv_acpi_madt_add_rintc(i, arch_ids, madt_buf, s); + aml_append(dev, aml_name_decl("_MAT", + aml_buffer(madt_buf->len, + (uint8_t *)madt_buf->data))); +@@ -227,6 +261,7 @@ static void build_dsdt(GArray *table_data, + * 5.2.12 Multiple APIC Description Table (MADT) + * REF: https://github.com/riscv-non-isa/riscv-acpi/issues/15 + * https://drive.google.com/file/d/1R6k4MshhN3WTT-hwqAquu5nX6xSEqK2l/view ++ * https://drive.google.com/file/d/1oMGPyOD58JaPgMl1pKasT-VKsIKia7zR/view + */ + static void build_madt(GArray *table_data, + BIOSLinker *linker, +@@ -246,7 +281,7 @@ static void build_madt(GArray *table_data, + + /* RISC-V Local INTC structures per HART */ + for (int i = 0; i < arch_ids->len; i++) { +- riscv_acpi_madt_add_rintc(i, arch_ids, table_data); ++ riscv_acpi_madt_add_rintc(i, arch_ids, table_data, s); + } + + acpi_table_end(linker, &table); +-- +2.33.0 + diff --git a/hw-riscv-virt-acpi-build.c-Add-APLIC-in-the-MADT.patch b/hw-riscv-virt-acpi-build.c-Add-APLIC-in-the-MADT.patch new file mode 100644 index 0000000..92cad72 --- /dev/null +++ b/hw-riscv-virt-acpi-build.c-Add-APLIC-in-the-MADT.patch @@ -0,0 +1,76 @@ +From d9f8fe22148991711170825346b61ff3f8adfb0f Mon Sep 17 00:00:00 2001 +From: yechao-w +Date: Mon, 4 Aug 2025 20:59:30 +0800 +Subject: [PATCH 07/18] hw/riscv/virt-acpi-build.c: Add APLIC in the MADT + +commit 7d189186f68b2b249c0bd6c84984f3aad2bcd1ca upstream + +Add APLIC structures for each socket in the MADT when system is configured +with APLIC as the external wired interrupt controller. + +Signed-off-by: Sunil V L +Reviewed-by: Daniel Henrique Barboza +Reviewed-by: Andrew Jones +Acked-by: Alistair Francis +Acked-by: Michael S. Tsirkin +Message-ID: <20231218150247.466427-8-sunilvl@ventanamicro.com> +Signed-off-by: Alistair Francis +--- + hw/riscv/virt-acpi-build.c | 34 ++++++++++++++++++++++++++++++++++ + 1 file changed, 34 insertions(+) + +diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c +index 6bb21014fd..ec49c8804b 100644 +--- a/hw/riscv/virt-acpi-build.c ++++ b/hw/riscv/virt-acpi-build.c +@@ -274,6 +274,8 @@ static void build_madt(GArray *table_data, + uint8_t guest_index_bits = imsic_num_bits(s->aia_guests + 1); + uint16_t imsic_max_hart_per_socket = 0; + uint8_t hart_index_bits; ++ uint64_t aplic_addr; ++ uint32_t gsi_base; + uint8_t socket; + + for (socket = 0; socket < riscv_socket_count(ms); socket++) { +@@ -319,6 +321,38 @@ static void build_madt(GArray *table_data, + build_append_int_noprefix(table_data, IMSIC_MMIO_GROUP_MIN_SHIFT, 1); + } + ++ if (s->aia_type != VIRT_AIA_TYPE_NONE) { ++ /* APLICs */ ++ for (socket = 0; socket < riscv_socket_count(ms); socket++) { ++ aplic_addr = s->memmap[VIRT_APLIC_S].base + ++ s->memmap[VIRT_APLIC_S].size * socket; ++ gsi_base = VIRT_IRQCHIP_NUM_SOURCES * socket; ++ build_append_int_noprefix(table_data, 0x1A, 1); /* Type */ ++ build_append_int_noprefix(table_data, 36, 1); /* Length */ ++ build_append_int_noprefix(table_data, 1, 1); /* Version */ ++ build_append_int_noprefix(table_data, socket, 1); /* APLIC ID */ ++ build_append_int_noprefix(table_data, 0, 4); /* Flags */ ++ build_append_int_noprefix(table_data, 0, 8); /* Hardware ID */ ++ /* Number of IDCs */ ++ if (s->aia_type == VIRT_AIA_TYPE_APLIC) { ++ build_append_int_noprefix(table_data, ++ s->soc[socket].num_harts, ++ 2); ++ } else { ++ build_append_int_noprefix(table_data, 0, 2); ++ } ++ /* Total External Interrupt Sources Supported */ ++ build_append_int_noprefix(table_data, VIRT_IRQCHIP_NUM_SOURCES, 2); ++ /* Global System Interrupt Base */ ++ build_append_int_noprefix(table_data, gsi_base, 4); ++ /* APLIC Address */ ++ build_append_int_noprefix(table_data, aplic_addr, 8); ++ /* APLIC size */ ++ build_append_int_noprefix(table_data, ++ s->memmap[VIRT_APLIC_S].size, 4); ++ } ++ } ++ + acpi_table_end(linker, &table); + } + +-- +2.33.0 + diff --git a/hw-riscv-virt-acpi-build.c-Add-CMO-information-in-RH.patch b/hw-riscv-virt-acpi-build.c-Add-CMO-information-in-RH.patch new file mode 100644 index 0000000..02b0129 --- /dev/null +++ b/hw-riscv-virt-acpi-build.c-Add-CMO-information-in-RH.patch @@ -0,0 +1,131 @@ +From 99684e0a5700edb5d7ca51f255f23a54749efd1a Mon Sep 17 00:00:00 2001 +From: yechao-w +Date: Mon, 4 Aug 2025 20:59:31 +0800 +Subject: [PATCH 08/18] hw/riscv/virt-acpi-build.c: Add CMO information in RHCT + +commit e810a5177c44509e17293d4c7e6cffab8ce197c9 stream + +When CMO related extensions like Zicboz, Zicbom and Zicbop are enabled, the +block size for those extensions need to be communicated via CMO node in +RHCT. Add CMO node in RHCT if any of those CMO extensions are detected. + +Signed-off-by: Sunil V L +Reviewed-by: Daniel Henrique Barboza +Reviewed-by: Andrew Jones +Acked-by: Alistair Francis +Acked-by: Michael S. Tsirkin +Message-ID: <20231218150247.466427-9-sunilvl@ventanamicro.com> +Signed-off-by: Alistair Francis +--- + hw/riscv/virt-acpi-build.c | 64 +++++++++++++++++++++++++++++++++----- + 1 file changed, 56 insertions(+), 8 deletions(-) + +diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c +index ec49c8804b..506d487ede 100644 +--- a/hw/riscv/virt-acpi-build.c ++++ b/hw/riscv/virt-acpi-build.c +@@ -140,6 +140,7 @@ static void acpi_dsdt_add_cpus(Aml *scope, RISCVVirtState *s) + * 5.2.36 RISC-V Hart Capabilities Table (RHCT) + * REF: https://github.com/riscv-non-isa/riscv-acpi/issues/16 + * https://drive.google.com/file/d/1nP3nFiH4jkPMp6COOxP6123DCZKR-tia/view ++ * https://drive.google.com/file/d/1sKbOa8m1UZw1JkquZYe3F1zQBN1xXsaf/view + */ + static void build_rhct(GArray *table_data, + BIOSLinker *linker, +@@ -149,8 +150,8 @@ static void build_rhct(GArray *table_data, + MachineState *ms = MACHINE(s); + const CPUArchIdList *arch_ids = mc->possible_cpu_arch_ids(ms); + size_t len, aligned_len; +- uint32_t isa_offset, num_rhct_nodes; +- RISCVCPU *cpu; ++ uint32_t isa_offset, num_rhct_nodes, cmo_offset = 0; ++ RISCVCPU *cpu = &s->soc[0].harts[0]; + char *isa; + + AcpiTable table = { .sig = "RHCT", .rev = 1, .oem_id = s->oem_id, +@@ -166,6 +167,9 @@ static void build_rhct(GArray *table_data, + + /* ISA + N hart info */ + num_rhct_nodes = 1 + ms->smp.cpus; ++ if (cpu->cfg.ext_zicbom || cpu->cfg.ext_zicboz) { ++ num_rhct_nodes++; ++ } + + /* Number of RHCT nodes*/ + build_append_int_noprefix(table_data, num_rhct_nodes, 4); +@@ -177,7 +181,6 @@ static void build_rhct(GArray *table_data, + isa_offset = table_data->len - table.table_offset; + build_append_int_noprefix(table_data, 0, 2); /* Type 0 */ + +- cpu = &s->soc[0].harts[0]; + isa = riscv_isa_string(cpu); + len = 8 + strlen(isa) + 1; + aligned_len = (len % 2) ? (len + 1) : len; +@@ -193,14 +196,59 @@ static void build_rhct(GArray *table_data, + build_append_int_noprefix(table_data, 0x0, 1); /* Optional Padding */ + } + ++ /* CMO node */ ++ if (cpu->cfg.ext_zicbom || cpu->cfg.ext_zicboz) { ++ cmo_offset = table_data->len - table.table_offset; ++ build_append_int_noprefix(table_data, 1, 2); /* Type */ ++ build_append_int_noprefix(table_data, 10, 2); /* Length */ ++ build_append_int_noprefix(table_data, 0x1, 2); /* Revision */ ++ build_append_int_noprefix(table_data, 0, 1); /* Reserved */ ++ ++ /* CBOM block size */ ++ if (cpu->cfg.cbom_blocksize) { ++ build_append_int_noprefix(table_data, ++ __builtin_ctz(cpu->cfg.cbom_blocksize), ++ 1); ++ } else { ++ build_append_int_noprefix(table_data, 0, 1); ++ } ++ ++ /* CBOP block size */ ++ build_append_int_noprefix(table_data, 0, 1); ++ ++ /* CBOZ block size */ ++ if (cpu->cfg.cboz_blocksize) { ++ build_append_int_noprefix(table_data, ++ __builtin_ctz(cpu->cfg.cboz_blocksize), ++ 1); ++ } else { ++ build_append_int_noprefix(table_data, 0, 1); ++ } ++ } ++ + /* Hart Info Node */ + for (int i = 0; i < arch_ids->len; i++) { ++ len = 16; ++ int num_offsets = 1; + build_append_int_noprefix(table_data, 0xFFFF, 2); /* Type */ +- build_append_int_noprefix(table_data, 16, 2); /* Length */ +- build_append_int_noprefix(table_data, 0x1, 2); /* Revision */ +- build_append_int_noprefix(table_data, 1, 2); /* Number of offsets */ +- build_append_int_noprefix(table_data, i, 4); /* ACPI Processor UID */ +- build_append_int_noprefix(table_data, isa_offset, 4); /* Offsets[0] */ ++ ++ /* Length */ ++ if (cmo_offset) { ++ len += 4; ++ num_offsets++; ++ } ++ ++ build_append_int_noprefix(table_data, len, 2); ++ build_append_int_noprefix(table_data, 0x1, 2); /* Revision */ ++ /* Number of offsets */ ++ build_append_int_noprefix(table_data, num_offsets, 2); ++ build_append_int_noprefix(table_data, i, 4); /* ACPI Processor UID */ ++ ++ /* Offsets */ ++ build_append_int_noprefix(table_data, isa_offset, 4); ++ if (cmo_offset) { ++ build_append_int_noprefix(table_data, cmo_offset, 4); ++ } + } + + acpi_table_end(linker, &table); +-- +2.33.0 + diff --git a/hw-riscv-virt-acpi-build.c-Add-IMSIC-in-the-MADT.patch b/hw-riscv-virt-acpi-build.c-Add-IMSIC-in-the-MADT.patch new file mode 100644 index 0000000..adfac94 --- /dev/null +++ b/hw-riscv-virt-acpi-build.c-Add-IMSIC-in-the-MADT.patch @@ -0,0 +1,76 @@ +From ff2e662b539eb2cf9a754f1c5fb2e055e67ac3f7 Mon Sep 17 00:00:00 2001 +From: yechao-w +Date: Mon, 4 Aug 2025 20:59:29 +0800 +Subject: [PATCH 06/18] hw/riscv/virt-acpi-build.c: Add IMSIC in the MADT + +commit 66ac45b75975a64aa3fbcaa038aecfbc11ac8547 upstream + +Add IMSIC structure in MADT when IMSIC is configured. + +Signed-off-by: Sunil V L +Reviewed-by: Daniel Henrique Barboza +Reviewed-by: Andrew Jones +Acked-by: Alistair Francis +Acked-by: Michael S. Tsirkin +Message-ID: <20231218150247.466427-7-sunilvl@ventanamicro.com> +Signed-off-by: Alistair Francis +--- + hw/riscv/virt-acpi-build.c | 35 +++++++++++++++++++++++++++++++++++ + 1 file changed, 35 insertions(+) + +diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c +index 3f9536356e..6bb21014fd 100644 +--- a/hw/riscv/virt-acpi-build.c ++++ b/hw/riscv/virt-acpi-build.c +@@ -270,6 +270,19 @@ static void build_madt(GArray *table_data, + MachineClass *mc = MACHINE_GET_CLASS(s); + MachineState *ms = MACHINE(s); + const CPUArchIdList *arch_ids = mc->possible_cpu_arch_ids(ms); ++ uint8_t group_index_bits = imsic_num_bits(riscv_socket_count(ms)); ++ uint8_t guest_index_bits = imsic_num_bits(s->aia_guests + 1); ++ uint16_t imsic_max_hart_per_socket = 0; ++ uint8_t hart_index_bits; ++ uint8_t socket; ++ ++ for (socket = 0; socket < riscv_socket_count(ms); socket++) { ++ if (imsic_max_hart_per_socket < s->soc[socket].num_harts) { ++ imsic_max_hart_per_socket = s->soc[socket].num_harts; ++ } ++ } ++ ++ hart_index_bits = imsic_num_bits(imsic_max_hart_per_socket); + + AcpiTable table = { .sig = "APIC", .rev = 6, .oem_id = s->oem_id, + .oem_table_id = s->oem_table_id }; +@@ -284,6 +297,28 @@ static void build_madt(GArray *table_data, + riscv_acpi_madt_add_rintc(i, arch_ids, table_data, s); + } + ++ /* IMSIC */ ++ if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) { ++ /* IMSIC */ ++ build_append_int_noprefix(table_data, 0x19, 1); /* Type */ ++ build_append_int_noprefix(table_data, 16, 1); /* Length */ ++ build_append_int_noprefix(table_data, 1, 1); /* Version */ ++ build_append_int_noprefix(table_data, 0, 1); /* Reserved */ ++ build_append_int_noprefix(table_data, 0, 4); /* Flags */ ++ /* Number of supervisor mode Interrupt Identities */ ++ build_append_int_noprefix(table_data, VIRT_IRQCHIP_NUM_MSIS, 2); ++ /* Number of guest mode Interrupt Identities */ ++ build_append_int_noprefix(table_data, VIRT_IRQCHIP_NUM_MSIS, 2); ++ /* Guest Index Bits */ ++ build_append_int_noprefix(table_data, guest_index_bits, 1); ++ /* Hart Index Bits */ ++ build_append_int_noprefix(table_data, hart_index_bits, 1); ++ /* Group Index Bits */ ++ build_append_int_noprefix(table_data, group_index_bits, 1); ++ /* Group Index Shift */ ++ build_append_int_noprefix(table_data, IMSIC_MMIO_GROUP_MIN_SHIFT, 1); ++ } ++ + acpi_table_end(linker, &table); + } + +-- +2.33.0 + diff --git a/hw-riscv-virt-acpi-build.c-Add-IO-controllers-and-de.patch b/hw-riscv-virt-acpi-build.c-Add-IO-controllers-and-de.patch new file mode 100644 index 0000000..b37a4ce --- /dev/null +++ b/hw-riscv-virt-acpi-build.c-Add-IO-controllers-and-de.patch @@ -0,0 +1,160 @@ +From 58d2550602ca8ccf9cc4b80bb7ddd1580052eeab Mon Sep 17 00:00:00 2001 +From: yechao-w +Date: Mon, 4 Aug 2025 20:59:36 +0800 +Subject: [PATCH 12/18] hw/riscv/virt-acpi-build.c: Add IO controllers and + devices + +commit 55ecd83b3697d0e4002c1dfde3265ebe6fa887cc upstream + +Add basic IO controllers and devices like PCI, VirtIO and UART in the +ACPI namespace. + +Signed-off-by: Sunil V L +Reviewed-by: Daniel Henrique Barboza +Acked-by: Alistair Francis +Acked-by: Michael S. Tsirkin +Message-ID: <20231218150247.466427-13-sunilvl@ventanamicro.com> +Signed-off-by: Alistair Francis +--- + hw/riscv/Kconfig | 1 + + hw/riscv/virt-acpi-build.c | 79 ++++++++++++++++++++++++++++++++++++-- + 2 files changed, 76 insertions(+), 4 deletions(-) + +diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig +index 1e11ac9432..5d644eb7b1 100644 +--- a/hw/riscv/Kconfig ++++ b/hw/riscv/Kconfig +@@ -46,6 +46,7 @@ config RISCV_VIRT + select FW_CFG_DMA + select PLATFORM_BUS + select ACPI ++ select ACPI_PCI + + config SHAKTI_C + bool +diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c +index 86c38f7c2b..4d03a27efd 100644 +--- a/hw/riscv/virt-acpi-build.c ++++ b/hw/riscv/virt-acpi-build.c +@@ -27,15 +27,18 @@ + #include "hw/acpi/acpi-defs.h" + #include "hw/acpi/acpi.h" + #include "hw/acpi/aml-build.h" ++#include "hw/acpi/pci.h" + #include "hw/acpi/utils.h" ++#include "hw/intc/riscv_aclint.h" + #include "hw/nvram/fw_cfg_acpi.h" ++#include "hw/pci-host/gpex.h" ++#include "hw/riscv/virt.h" ++#include "hw/riscv/numa.h" ++#include "hw/virtio/virtio-acpi.h" ++#include "migration/vmstate.h" + #include "qapi/error.h" + #include "qemu/error-report.h" + #include "sysemu/reset.h" +-#include "migration/vmstate.h" +-#include "hw/riscv/virt.h" +-#include "hw/riscv/numa.h" +-#include "hw/intc/riscv_aclint.h" + + #define ACPI_BUILD_TABLE_SIZE 0x20000 + #define ACPI_BUILD_INTC_ID(socket, index) ((socket << 24) | (index)) +@@ -132,6 +135,39 @@ static void acpi_dsdt_add_cpus(Aml *scope, RISCVVirtState *s) + } + } + ++static void ++acpi_dsdt_add_uart(Aml *scope, const MemMapEntry *uart_memmap, ++ uint32_t uart_irq) ++{ ++ Aml *dev = aml_device("COM0"); ++ aml_append(dev, aml_name_decl("_HID", aml_string("PNP0501"))); ++ aml_append(dev, aml_name_decl("_UID", aml_int(0))); ++ ++ Aml *crs = aml_resource_template(); ++ aml_append(crs, aml_memory32_fixed(uart_memmap->base, ++ uart_memmap->size, AML_READ_WRITE)); ++ aml_append(crs, ++ aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, ++ AML_EXCLUSIVE, &uart_irq, 1)); ++ aml_append(dev, aml_name_decl("_CRS", crs)); ++ ++ Aml *pkg = aml_package(2); ++ aml_append(pkg, aml_string("clock-frequency")); ++ aml_append(pkg, aml_int(3686400)); ++ ++ Aml *UUID = aml_touuid("DAFFD814-6EBA-4D8C-8A91-BC9BBF4AA301"); ++ ++ Aml *pkg1 = aml_package(1); ++ aml_append(pkg1, pkg); ++ ++ Aml *package = aml_package(2); ++ aml_append(package, UUID); ++ aml_append(package, pkg1); ++ ++ aml_append(dev, aml_name_decl("_DSD", package)); ++ aml_append(scope, dev); ++} ++ + /* RHCT Node[N] starts at offset 56 */ + #define RHCT_NODE_ARRAY_OFFSET 56 + +@@ -310,6 +346,8 @@ static void build_dsdt(GArray *table_data, + RISCVVirtState *s) + { + Aml *scope, *dsdt; ++ MachineState *ms = MACHINE(s); ++ uint8_t socket_count; + const MemMapEntry *memmap = s->memmap; + AcpiTable table = { .sig = "DSDT", .rev = 2, .oem_id = s->oem_id, + .oem_table_id = s->oem_table_id }; +@@ -329,6 +367,29 @@ static void build_dsdt(GArray *table_data, + + fw_cfg_acpi_dsdt_add(scope, &memmap[VIRT_FW_CFG]); + ++ socket_count = riscv_socket_count(ms); ++ ++ acpi_dsdt_add_uart(scope, &memmap[VIRT_UART0], UART0_IRQ); ++ ++ if (socket_count == 1) { ++ virtio_acpi_dsdt_add(scope, memmap[VIRT_VIRTIO].base, ++ memmap[VIRT_VIRTIO].size, ++ VIRTIO_IRQ, 0, VIRTIO_COUNT); ++ acpi_dsdt_add_gpex_host(scope, PCIE_IRQ); ++ } else if (socket_count == 2) { ++ virtio_acpi_dsdt_add(scope, memmap[VIRT_VIRTIO].base, ++ memmap[VIRT_VIRTIO].size, ++ VIRTIO_IRQ + VIRT_IRQCHIP_NUM_SOURCES, 0, ++ VIRTIO_COUNT); ++ acpi_dsdt_add_gpex_host(scope, PCIE_IRQ + VIRT_IRQCHIP_NUM_SOURCES); ++ } else { ++ virtio_acpi_dsdt_add(scope, memmap[VIRT_VIRTIO].base, ++ memmap[VIRT_VIRTIO].size, ++ VIRTIO_IRQ + VIRT_IRQCHIP_NUM_SOURCES, 0, ++ VIRTIO_COUNT); ++ acpi_dsdt_add_gpex_host(scope, PCIE_IRQ + VIRT_IRQCHIP_NUM_SOURCES * 2); ++ } ++ + aml_append(dsdt, scope); + + /* copy AML table into ACPI tables blob and patch header there */ +@@ -465,6 +526,16 @@ static void virt_acpi_build(RISCVVirtState *s, AcpiBuildTables *tables) + acpi_add_table(table_offsets, tables_blob); + build_rhct(tables_blob, tables->linker, s); + ++ acpi_add_table(table_offsets, tables_blob); ++ { ++ AcpiMcfgInfo mcfg = { ++ .base = s->memmap[VIRT_PCIE_MMIO].base, ++ .size = s->memmap[VIRT_PCIE_MMIO].size, ++ }; ++ build_mcfg(tables_blob, tables->linker, &mcfg, s->oem_id, ++ s->oem_table_id); ++ } ++ + /* XSDT is pointed to by RSDP */ + xsdt = tables_blob->len; + build_xsdt(tables_blob, tables->linker, table_offsets, s->oem_id, +-- +2.33.0 + diff --git a/hw-riscv-virt-acpi-build.c-Add-MMU-node-in-RHCT.patch b/hw-riscv-virt-acpi-build.c-Add-MMU-node-in-RHCT.patch new file mode 100644 index 0000000..24a1c29 --- /dev/null +++ b/hw-riscv-virt-acpi-build.c-Add-MMU-node-in-RHCT.patch @@ -0,0 +1,102 @@ +From 7310f0bc6612ced123be51af2fd720e84955759a Mon Sep 17 00:00:00 2001 +From: yechao-w +Date: Mon, 4 Aug 2025 20:59:33 +0800 +Subject: [PATCH 09/18] hw/riscv/virt-acpi-build.c: Add MMU node in RHCT + +commit a52aea263e0f25993e368ee682d96f32aff52499 upstream + +MMU type information is available via MMU node in RHCT. Add this node in +RHCT. + +Signed-off-by: Sunil V L +Reviewed-by: Daniel Henrique Barboza +Reviewed-by: Andrew Jones +Acked-by: Alistair Francis +Acked-by: Michael S. Tsirkin +Message-ID: <20231218150247.466427-10-sunilvl@ventanamicro.com> +Signed-off-by: Alistair Francis +--- + hw/riscv/virt-acpi-build.c | 36 +++++++++++++++++++++++++++++++++++- + 1 file changed, 35 insertions(+), 1 deletion(-) + +diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c +index 506d487ede..86c38f7c2b 100644 +--- a/hw/riscv/virt-acpi-build.c ++++ b/hw/riscv/virt-acpi-build.c +@@ -152,6 +152,8 @@ static void build_rhct(GArray *table_data, + size_t len, aligned_len; + uint32_t isa_offset, num_rhct_nodes, cmo_offset = 0; + RISCVCPU *cpu = &s->soc[0].harts[0]; ++ uint32_t mmu_offset = 0; ++ uint8_t satp_mode_max; + char *isa; + + AcpiTable table = { .sig = "RHCT", .rev = 1, .oem_id = s->oem_id, +@@ -171,6 +173,10 @@ static void build_rhct(GArray *table_data, + num_rhct_nodes++; + } + ++ if (cpu->cfg.satp_mode.supported != 0) { ++ num_rhct_nodes++; ++ } ++ + /* Number of RHCT nodes*/ + build_append_int_noprefix(table_data, num_rhct_nodes, 4); + +@@ -226,6 +232,26 @@ static void build_rhct(GArray *table_data, + } + } + ++ /* MMU node structure */ ++ if (cpu->cfg.satp_mode.supported != 0) { ++ satp_mode_max = satp_mode_max_from_map(cpu->cfg.satp_mode.map); ++ mmu_offset = table_data->len - table.table_offset; ++ build_append_int_noprefix(table_data, 2, 2); /* Type */ ++ build_append_int_noprefix(table_data, 8, 2); /* Length */ ++ build_append_int_noprefix(table_data, 0x1, 2); /* Revision */ ++ build_append_int_noprefix(table_data, 0, 1); /* Reserved */ ++ /* MMU Type */ ++ if (satp_mode_max == VM_1_10_SV57) { ++ build_append_int_noprefix(table_data, 2, 1); /* Sv57 */ ++ } else if (satp_mode_max == VM_1_10_SV48) { ++ build_append_int_noprefix(table_data, 1, 1); /* Sv48 */ ++ } else if (satp_mode_max == VM_1_10_SV39) { ++ build_append_int_noprefix(table_data, 0, 1); /* Sv39 */ ++ } else { ++ assert(1); ++ } ++ } ++ + /* Hart Info Node */ + for (int i = 0; i < arch_ids->len; i++) { + len = 16; +@@ -238,17 +264,25 @@ static void build_rhct(GArray *table_data, + num_offsets++; + } + ++ if (mmu_offset) { ++ len += 4; ++ num_offsets++; ++ } ++ + build_append_int_noprefix(table_data, len, 2); + build_append_int_noprefix(table_data, 0x1, 2); /* Revision */ + /* Number of offsets */ + build_append_int_noprefix(table_data, num_offsets, 2); + build_append_int_noprefix(table_data, i, 4); /* ACPI Processor UID */ +- + /* Offsets */ + build_append_int_noprefix(table_data, isa_offset, 4); + if (cmo_offset) { + build_append_int_noprefix(table_data, cmo_offset, 4); + } ++ ++ if (mmu_offset) { ++ build_append_int_noprefix(table_data, mmu_offset, 4); ++ } + } + + acpi_table_end(linker, &table); +-- +2.33.0 + diff --git a/hw-riscv-virt-acpi-build.c-Add-PLIC-in-MADT.patch b/hw-riscv-virt-acpi-build.c-Add-PLIC-in-MADT.patch new file mode 100644 index 0000000..5c89086 --- /dev/null +++ b/hw-riscv-virt-acpi-build.c-Add-PLIC-in-MADT.patch @@ -0,0 +1,72 @@ +From 37a9be92a26b78341aa2ab03126590b9d9fa18b6 Mon Sep 17 00:00:00 2001 +From: yechao-w +Date: Mon, 4 Aug 2025 20:59:37 +0800 +Subject: [PATCH 13/18] hw/riscv/virt-acpi-build.c: Add PLIC in MADT + +commit d641da6ed431f497b763a6e6bf30e0b4dc00e0d9 upstream + +Add PLIC structures for each socket in the MADT when system is +configured with PLIC as the external interrupt controller. + +Signed-off-by: Haibo Xu +Signed-off-by: Sunil V L +Reviewed-by: Daniel Henrique Barboza +Reviewed-by: Andrew Jones +Acked-by: Alistair Francis +Acked-by: Michael S. Tsirkin +Message-ID: <20231218150247.466427-14-sunilvl@ventanamicro.com> +Signed-off-by: Alistair Francis +--- + hw/riscv/virt-acpi-build.c | 29 +++++++++++++++++++++++++++++ + 1 file changed, 29 insertions(+) + +diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c +index 4d03a27efd..d4a02579d6 100644 +--- a/hw/riscv/virt-acpi-build.c ++++ b/hw/riscv/virt-acpi-build.c +@@ -94,6 +94,12 @@ static void riscv_acpi_madt_add_rintc(uint32_t uid, + arch_ids->cpus[uid].props.node_id, + local_cpu_id), + 4); ++ } else if (s->aia_type == VIRT_AIA_TYPE_NONE) { ++ build_append_int_noprefix(entry, ++ ACPI_BUILD_INTC_ID( ++ arch_ids->cpus[uid].props.node_id, ++ 2 * local_cpu_id + 1), ++ 4); + } else { + build_append_int_noprefix(entry, 0, 4); + } +@@ -494,6 +500,29 @@ static void build_madt(GArray *table_data, + build_append_int_noprefix(table_data, + s->memmap[VIRT_APLIC_S].size, 4); + } ++ } else { ++ /* PLICs */ ++ for (socket = 0; socket < riscv_socket_count(ms); socket++) { ++ aplic_addr = s->memmap[VIRT_PLIC].base + ++ s->memmap[VIRT_PLIC].size * socket; ++ gsi_base = VIRT_IRQCHIP_NUM_SOURCES * socket; ++ build_append_int_noprefix(table_data, 0x1B, 1); /* Type */ ++ build_append_int_noprefix(table_data, 36, 1); /* Length */ ++ build_append_int_noprefix(table_data, 1, 1); /* Version */ ++ build_append_int_noprefix(table_data, socket, 1); /* PLIC ID */ ++ build_append_int_noprefix(table_data, 0, 8); /* Hardware ID */ ++ /* Total External Interrupt Sources Supported */ ++ build_append_int_noprefix(table_data, ++ VIRT_IRQCHIP_NUM_SOURCES - 1, 2); ++ build_append_int_noprefix(table_data, 0, 2); /* Max Priority */ ++ build_append_int_noprefix(table_data, 0, 4); /* Flags */ ++ /* PLIC Size */ ++ build_append_int_noprefix(table_data, s->memmap[VIRT_PLIC].size, 4); ++ /* PLIC Address */ ++ build_append_int_noprefix(table_data, aplic_addr, 8); ++ /* Global System Interrupt Vector Base */ ++ build_append_int_noprefix(table_data, gsi_base, 4); ++ } + } + + acpi_table_end(linker, &table); +-- +2.33.0 + diff --git a/hw-riscv-virt-acpi-build.c-Add-SRAT-and-SLIT-ACPI-ta.patch b/hw-riscv-virt-acpi-build.c-Add-SRAT-and-SLIT-ACPI-ta.patch new file mode 100644 index 0000000..bec635f --- /dev/null +++ b/hw-riscv-virt-acpi-build.c-Add-SRAT-and-SLIT-ACPI-ta.patch @@ -0,0 +1,112 @@ +From 6d52123c9c8a0c6e9d7560f9c4e4b641e568e0c6 Mon Sep 17 00:00:00 2001 +From: yechao-w +Date: Mon, 4 Aug 2025 20:59:42 +0800 +Subject: [PATCH 18/18] hw/riscv/virt-acpi-build.c: Add SRAT and SLIT ACPI + tables + +commit a29f5b957644dd0f14a43c8719b18c134875195c upstream + +Enable ACPI NUMA support by adding the following 2 ACPI tables: +SRAT: provides the association for memory/Harts and Proximity Domains +SLIT: provides the relative distance between Proximity Domains + +The SRAT RINTC Affinity Structure definition[1] was based on the recently +approved ACPI CodeFirst ECR[2]. + +[1] https://github.com/riscv-non-isa/riscv-acpi/issues/25 +[2] https://mantis.uefi.org/mantis/view.php?id=2433 + +Signed-off-by: Haibo Xu +Reviewed-by: Andrew Jones +Message-ID: <20240129094200.3581037-1-haibo1.xu@intel.com> +Signed-off-by: Alistair Francis +--- + hw/riscv/virt-acpi-build.c | 60 ++++++++++++++++++++++++++++++++++++++ + 1 file changed, 60 insertions(+) + +diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c +index d69c25d2c9..69e9646683 100644 +--- a/hw/riscv/virt-acpi-build.c ++++ b/hw/riscv/virt-acpi-build.c +@@ -596,11 +596,61 @@ static void build_madt(GArray *table_data, + acpi_table_end(linker, &table); + } + ++/* ++ * ACPI spec, Revision 6.5+ ++ * 5.2.16 System Resource Affinity Table (SRAT) ++ * REF: https://github.com/riscv-non-isa/riscv-acpi/issues/25 ++ * https://drive.google.com/file/d/1YTdDx2IPm5IeZjAW932EYU-tUtgS08tX/view ++ */ ++static void ++build_srat(GArray *table_data, BIOSLinker *linker, RISCVVirtState *vms) ++{ ++ int i; ++ uint64_t mem_base; ++ MachineClass *mc = MACHINE_GET_CLASS(vms); ++ MachineState *ms = MACHINE(vms); ++ const CPUArchIdList *cpu_list = mc->possible_cpu_arch_ids(ms); ++ AcpiTable table = { .sig = "SRAT", .rev = 3, .oem_id = vms->oem_id, ++ .oem_table_id = vms->oem_table_id }; ++ ++ acpi_table_begin(&table, table_data); ++ build_append_int_noprefix(table_data, 1, 4); /* Reserved */ ++ build_append_int_noprefix(table_data, 0, 8); /* Reserved */ ++ ++ for (i = 0; i < cpu_list->len; ++i) { ++ uint32_t nodeid = cpu_list->cpus[i].props.node_id; ++ /* ++ * 5.2.16.8 RINTC Affinity Structure ++ */ ++ build_append_int_noprefix(table_data, 7, 1); /* Type */ ++ build_append_int_noprefix(table_data, 20, 1); /* Length */ ++ build_append_int_noprefix(table_data, 0, 2); /* Reserved */ ++ build_append_int_noprefix(table_data, nodeid, 4); /* Proximity Domain */ ++ build_append_int_noprefix(table_data, i, 4); /* ACPI Processor UID */ ++ /* Flags, Table 5-70 */ ++ build_append_int_noprefix(table_data, 1 /* Flags: Enabled */, 4); ++ build_append_int_noprefix(table_data, 0, 4); /* Clock Domain */ ++ } ++ ++ mem_base = vms->memmap[VIRT_DRAM].base; ++ for (i = 0; i < ms->numa_state->num_nodes; ++i) { ++ if (ms->numa_state->nodes[i].node_mem > 0) { ++ build_srat_memory(table_data, mem_base, ++ ms->numa_state->nodes[i].node_mem, i, ++ MEM_AFFINITY_ENABLED); ++ mem_base += ms->numa_state->nodes[i].node_mem; ++ } ++ } ++ ++ acpi_table_end(linker, &table); ++} ++ + static void virt_acpi_build(RISCVVirtState *s, AcpiBuildTables *tables) + { + GArray *table_offsets; + unsigned dsdt, xsdt; + GArray *tables_blob = tables->table_data; ++ MachineState *ms = MACHINE(s); + + table_offsets = g_array_new(false, true, + sizeof(uint32_t)); +@@ -636,6 +686,16 @@ static void virt_acpi_build(RISCVVirtState *s, AcpiBuildTables *tables) + s->oem_table_id); + } + ++ if (ms->numa_state->num_nodes > 0) { ++ acpi_add_table(table_offsets, tables_blob); ++ build_srat(tables_blob, tables->linker, s); ++ if (ms->numa_state->have_numa_distance) { ++ acpi_add_table(table_offsets, tables_blob); ++ build_slit(tables_blob, tables->linker, ms, s->oem_id, ++ s->oem_table_id); ++ } ++ } ++ + /* XSDT is pointed to by RSDP */ + xsdt = tables_blob->len; + build_xsdt(tables_blob, tables->linker, table_offsets, s->oem_id, +-- +2.33.0 + diff --git a/hw-riscv-virt-acpi-build.c-Add-namespace-devices-for.patch b/hw-riscv-virt-acpi-build.c-Add-namespace-devices-for.patch new file mode 100644 index 0000000..231a6ae --- /dev/null +++ b/hw-riscv-virt-acpi-build.c-Add-namespace-devices-for.patch @@ -0,0 +1,78 @@ +From 27190f7b6b48ba4684e9f352d0adda63bca814fe Mon Sep 17 00:00:00 2001 +From: yechao-w +Date: Mon, 4 Aug 2025 20:59:39 +0800 +Subject: [PATCH 15/18] hw/riscv/virt-acpi-build.c: Add namespace devices for + PLIC and APLIC + +commit a54dd0cd6b9119c44d52547f51a529122f0ec1f1 upstream + +As per the requirement ACPI_080 in the RISC-V Boot and Runtime Services +(BRS) specification [1], PLIC and APLIC should be in namespace as well. +So, add them using the defined HID. + +[1] - https://github.com/riscv-non-isa/riscv-brs/releases/download/v0.0.2/riscv-brs-spec.pdf + (Chapter 6) + +Signed-off-by: Sunil V L +Acked-by: Alistair Francis +Acked-by: Igor Mammedov +Message-Id: <20240716144306.2432257-2-sunilvl@ventanamicro.com> +Reviewed-by: Michael S. Tsirkin +Signed-off-by: Michael S. Tsirkin +--- + hw/riscv/virt-acpi-build.c | 32 ++++++++++++++++++++++++++++++++ + 1 file changed, 32 insertions(+) + +diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c +index d4a02579d6..2189579d53 100644 +--- a/hw/riscv/virt-acpi-build.c ++++ b/hw/riscv/virt-acpi-build.c +@@ -141,6 +141,30 @@ static void acpi_dsdt_add_cpus(Aml *scope, RISCVVirtState *s) + } + } + ++static void acpi_dsdt_add_plic_aplic(Aml *scope, uint8_t socket_count, ++ uint64_t mmio_base, uint64_t mmio_size, ++ const char *hid) ++{ ++ uint64_t plic_aplic_addr; ++ uint32_t gsi_base; ++ uint8_t socket; ++ ++ for (socket = 0; socket < socket_count; socket++) { ++ plic_aplic_addr = mmio_base + mmio_size * socket; ++ gsi_base = VIRT_IRQCHIP_NUM_SOURCES * socket; ++ Aml *dev = aml_device("IC%.02X", socket); ++ aml_append(dev, aml_name_decl("_HID", aml_string("%s", hid))); ++ aml_append(dev, aml_name_decl("_UID", aml_int(socket))); ++ aml_append(dev, aml_name_decl("_GSB", aml_int(gsi_base))); ++ ++ Aml *crs = aml_resource_template(); ++ aml_append(crs, aml_memory32_fixed(plic_aplic_addr, mmio_size, ++ AML_READ_WRITE)); ++ aml_append(dev, aml_name_decl("_CRS", crs)); ++ aml_append(scope, dev); ++ } ++} ++ + static void + acpi_dsdt_add_uart(Aml *scope, const MemMapEntry *uart_memmap, + uint32_t uart_irq) +@@ -375,6 +399,14 @@ static void build_dsdt(GArray *table_data, + + socket_count = riscv_socket_count(ms); + ++ if (s->aia_type == VIRT_AIA_TYPE_NONE) { ++ acpi_dsdt_add_plic_aplic(scope, socket_count, memmap[VIRT_PLIC].base, ++ memmap[VIRT_PLIC].size, "RSCV0001"); ++ } else { ++ acpi_dsdt_add_plic_aplic(scope, socket_count, memmap[VIRT_APLIC_S].base, ++ memmap[VIRT_APLIC_S].size, "RSCV0002"); ++ } ++ + acpi_dsdt_add_uart(scope, &memmap[VIRT_UART0], UART0_IRQ); + + if (socket_count == 1) { +-- +2.33.0 + diff --git a/hw-riscv-virt-acpi-build.c-Generate-SPCR-table.patch b/hw-riscv-virt-acpi-build.c-Generate-SPCR-table.patch new file mode 100644 index 0000000..d29531b --- /dev/null +++ b/hw-riscv-virt-acpi-build.c-Generate-SPCR-table.patch @@ -0,0 +1,78 @@ +From 612c2ba1c1b0377318bf9a8ed421a505bafc3311 Mon Sep 17 00:00:00 2001 +From: yechao-w +Date: Mon, 4 Aug 2025 20:59:41 +0800 +Subject: [PATCH 17/18] hw/riscv/virt-acpi-build.c: Generate SPCR table + +commit 3e6f1e61b4bc0facd13967580feed47d96a2c28c upstream + +Generate Serial Port Console Redirection Table (SPCR) for RISC-V +virtual machine. + +Signed-off-by: Sia Jee Heng +Reviewed-by: Daniel Henrique Barboza +Message-ID: <20240129021440.17640-3-jeeheng.sia@starfivetech.com> +Signed-off-by: Alistair Francis +--- + hw/riscv/virt-acpi-build.c | 39 ++++++++++++++++++++++++++++++++++++++ + 1 file changed, 39 insertions(+) + +diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c +index 6230ab02c6..d69c25d2c9 100644 +--- a/hw/riscv/virt-acpi-build.c ++++ b/hw/riscv/virt-acpi-build.c +@@ -198,6 +198,42 @@ acpi_dsdt_add_uart(Aml *scope, const MemMapEntry *uart_memmap, + aml_append(scope, dev); + } + ++/* ++ * Serial Port Console Redirection Table (SPCR) ++ * Rev: 1.07 ++ */ ++ ++static void ++spcr_setup(GArray *table_data, BIOSLinker *linker, RISCVVirtState *s) ++{ ++ AcpiSpcrData serial = { ++ .interface_type = 0, /* 16550 compatible */ ++ .base_addr.id = AML_AS_SYSTEM_MEMORY, ++ .base_addr.width = 32, ++ .base_addr.offset = 0, ++ .base_addr.size = 1, ++ .base_addr.addr = s->memmap[VIRT_UART0].base, ++ .interrupt_type = (1 << 4),/* Bit[4] RISC-V PLIC/APLIC */ ++ .pc_interrupt = 0, ++ .interrupt = UART0_IRQ, ++ .baud_rate = 7, /* 15200 */ ++ .parity = 0, ++ .stop_bits = 1, ++ .flow_control = 0, ++ .terminal_type = 3, /* ANSI */ ++ .language = 0, /* Language */ ++ .pci_device_id = 0xffff, /* not a PCI device*/ ++ .pci_vendor_id = 0xffff, /* not a PCI device*/ ++ .pci_bus = 0, ++ .pci_device = 0, ++ .pci_function = 0, ++ .pci_flags = 0, ++ .pci_segment = 0, ++ }; ++ ++ build_spcr(table_data, linker, &serial, 2, s->oem_id, s->oem_table_id); ++} ++ + /* RHCT Node[N] starts at offset 56 */ + #define RHCT_NODE_ARRAY_OFFSET 56 + +@@ -587,6 +623,9 @@ static void virt_acpi_build(RISCVVirtState *s, AcpiBuildTables *tables) + acpi_add_table(table_offsets, tables_blob); + build_rhct(tables_blob, tables->linker, s); + ++ acpi_add_table(table_offsets, tables_blob); ++ spcr_setup(tables_blob, tables->linker, s); ++ + acpi_add_table(table_offsets, tables_blob); + { + AcpiMcfgInfo mcfg = { +-- +2.33.0 + diff --git a/hw-riscv-virt-acpi-build.c-Update-the-HID-of-RISC-V-.patch b/hw-riscv-virt-acpi-build.c-Update-the-HID-of-RISC-V-.patch new file mode 100644 index 0000000..460d7fc --- /dev/null +++ b/hw-riscv-virt-acpi-build.c-Update-the-HID-of-RISC-V-.patch @@ -0,0 +1,41 @@ +From 0fb0bf77d7a956e36975c8cfcac83c2e972a5fe3 Mon Sep 17 00:00:00 2001 +From: yechao-w +Date: Mon, 4 Aug 2025 20:59:40 +0800 +Subject: [PATCH 16/18] hw/riscv/virt-acpi-build.c: Update the HID of RISC-V + UART + +commit faacd2e6b6a85a5eee2472e5a7f50bf69c4ad44a upstream + +The requirement ACPI_060 in the RISC-V BRS specification [1], requires +NS16550 compatible UART to have the HID RSCV0003. So, update the HID for +the UART. + +[1] - https://github.com/riscv-non-isa/riscv-brs/releases/download/v0.0.2/riscv-brs-spec.pdf + (Chapter 6) + +Signed-off-by: Sunil V L +Acked-by: Alistair Francis +Reviewed-by: Igor Mammedov +Message-Id: <20240716144306.2432257-3-sunilvl@ventanamicro.com> +Reviewed-by: Michael S. Tsirkin +Signed-off-by: Michael S. Tsirkin +--- + hw/riscv/virt-acpi-build.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c +index 2189579d53..6230ab02c6 100644 +--- a/hw/riscv/virt-acpi-build.c ++++ b/hw/riscv/virt-acpi-build.c +@@ -170,7 +170,7 @@ acpi_dsdt_add_uart(Aml *scope, const MemMapEntry *uart_memmap, + uint32_t uart_irq) + { + Aml *dev = aml_device("COM0"); +- aml_append(dev, aml_name_decl("_HID", aml_string("PNP0501"))); ++ aml_append(dev, aml_name_decl("_HID", aml_string("RSCV0003"))); + aml_append(dev, aml_name_decl("_UID", aml_int(0))); + + Aml *crs = aml_resource_template(); +-- +2.33.0 + diff --git a/hw-riscv-virt.c-fix-the-interrupts-extended-property.patch b/hw-riscv-virt.c-fix-the-interrupts-extended-property.patch new file mode 100644 index 0000000..5102015 --- /dev/null +++ b/hw-riscv-virt.c-fix-the-interrupts-extended-property.patch @@ -0,0 +1,92 @@ +From 127e3dfe8ed67aa0f763e03c5424e6f23b8aafb3 Mon Sep 17 00:00:00 2001 +From: yechao-w +Date: Mon, 4 Aug 2025 20:59:38 +0800 +Subject: [PATCH 14/18] hw/riscv/virt.c: fix the interrupts-extended property + format of PLIC + +commit ca334e10dcd1f0f3a3c08f8dc3f9945d574d0e6b upstream + +The interrupts-extended property of PLIC only has 2 * hart number +fields when KVM enabled, copy 4 * hart number fields to fdt will +expose some uninitialized value. + +In this patch, I also refactor the code about the setting of +interrupts-extended property of PLIC for improved readability. + +Signed-off-by: Yong-Xuan Wang +Reviewed-by: Jim Shu +Reviewed-by: Daniel Henrique Barboza +Message-ID: <20231218090543.22353-1-yongxuan.wang@sifive.com> +Signed-off-by: Alistair Francis +--- + hw/riscv/virt.c | 47 +++++++++++++++++++++++++++-------------------- + 1 file changed, 27 insertions(+), 20 deletions(-) + +diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c +index c47df46bfc..8f01ec7f61 100644 +--- a/hw/riscv/virt.c ++++ b/hw/riscv/virt.c +@@ -438,24 +438,6 @@ static void create_fdt_socket_plic(RISCVVirtState *s, + "sifive,plic-1.0.0", "riscv,plic0" + }; + +- if (kvm_enabled()) { +- plic_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2); +- } else { +- plic_cells = g_new0(uint32_t, s->soc[socket].num_harts * 4); +- } +- +- for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) { +- if (kvm_enabled()) { +- plic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); +- plic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_S_EXT); +- } else { +- plic_cells[cpu * 4 + 0] = cpu_to_be32(intc_phandles[cpu]); +- plic_cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_EXT); +- plic_cells[cpu * 4 + 2] = cpu_to_be32(intc_phandles[cpu]); +- plic_cells[cpu * 4 + 3] = cpu_to_be32(IRQ_S_EXT); +- } +- } +- + plic_phandles[socket] = (*phandle)++; + plic_addr = memmap[VIRT_PLIC].base + (memmap[VIRT_PLIC].size * socket); + plic_name = g_strdup_printf("/soc/plic@%lx", plic_addr); +@@ -468,8 +450,33 @@ static void create_fdt_socket_plic(RISCVVirtState *s, + (char **)&plic_compat, + ARRAY_SIZE(plic_compat)); + qemu_fdt_setprop(ms->fdt, plic_name, "interrupt-controller", NULL, 0); +- qemu_fdt_setprop(ms->fdt, plic_name, "interrupts-extended", +- plic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4); ++ ++ if (kvm_enabled()) { ++ plic_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2); ++ ++ for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) { ++ plic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); ++ plic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_S_EXT); ++ } ++ ++ qemu_fdt_setprop(ms->fdt, plic_name, "interrupts-extended", ++ plic_cells, ++ s->soc[socket].num_harts * sizeof(uint32_t) * 2); ++ } else { ++ plic_cells = g_new0(uint32_t, s->soc[socket].num_harts * 4); ++ ++ for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) { ++ plic_cells[cpu * 4 + 0] = cpu_to_be32(intc_phandles[cpu]); ++ plic_cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_EXT); ++ plic_cells[cpu * 4 + 2] = cpu_to_be32(intc_phandles[cpu]); ++ plic_cells[cpu * 4 + 3] = cpu_to_be32(IRQ_S_EXT); ++ } ++ ++ qemu_fdt_setprop(ms->fdt, plic_name, "interrupts-extended", ++ plic_cells, ++ s->soc[socket].num_harts * sizeof(uint32_t) * 4); ++ } ++ + qemu_fdt_setprop_cells(ms->fdt, plic_name, "reg", + 0x0, plic_addr, 0x0, memmap[VIRT_PLIC].size); + qemu_fdt_setprop_cell(ms->fdt, plic_name, "riscv,ndev", +-- +2.33.0 + diff --git a/plugins-loader-fix-deadlock-when-resetting-uninstall.patch b/plugins-loader-fix-deadlock-when-resetting-uninstall.patch new file mode 100644 index 0000000..433a141 --- /dev/null +++ b/plugins-loader-fix-deadlock-when-resetting-uninstall.patch @@ -0,0 +1,39 @@ +From 105b30f3406bb968b1eb87a6127a988cfb0a3022 Mon Sep 17 00:00:00 2001 +From: songjie +Date: Wed, 13 Aug 2025 14:46:12 +0800 +Subject: [PATCH] plugins/loader: fix deadlock when resetting/uninstalling a + plugin +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Reported and fixed by Dmitry Kurakin. + +Fixes: #2901 + +Signed-off-by: default avatarPierrick Bouvier +Message-Id: <20250404032027.430575-2-pierrick.bouvier@linaro.org> +Signed-off-by: default avatarAlex Bennée +Reviewed-by: default avatarPhilippe Mathieu-Daudé +(cherry picked from commit c07cd110) +Signed-off-by: default avatarMichael Tokarev +--- + plugins/loader.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/plugins/loader.c b/plugins/loader.c +index 734c11cae0..1f06dfa970 100644 +--- a/plugins/loader.c ++++ b/plugins/loader.c +@@ -374,7 +374,7 @@ static void plugin_reset_destroy(struct qemu_plugin_reset_data *data) + { + qemu_rec_mutex_lock(&plugin.lock); + plugin_reset_destroy__locked(data); +- qemu_rec_mutex_lock(&plugin.lock); ++ qemu_rec_mutex_unlock(&plugin.lock); + } + + static void plugin_flush_destroy(CPUState *cpu, run_on_cpu_data arg) +-- +2.33.0 + diff --git a/qemu.spec b/qemu.spec index 56d3023..9b5a4b4 100644 --- a/qemu.spec +++ b/qemu.spec @@ -3,7 +3,7 @@ Name: qemu Version: 8.2.0 -Release: 40 +Release: 41 Epoch: 11 Summary: QEMU is a generic and open source machine emulator and virtualizer License: GPLv2 and BSD and MIT and CC-BY-SA-4.0 @@ -997,6 +997,28 @@ Patch0980: target-arm-kvm-rme-Add-measurement-log.patch Patch0981: hw-arm-virt-Add-measurement-log-for-confidential-boo.patch Patch0982: On-the-Adaptation-of-CCA-and-virtCCA.patch Patch0983: Bugfix-Fix-compile-error-in-aarch32.patch +Patch0984: target-i386-kvm-Refine-VMX-controls-setting-for-back.patch +Patch0985: Bugfix-Correctly-set-vms-bootinfo.confidential-in-vi.patch +Patch0986: hw-arm-virt-acpi-build.c-Migrate-fw_cfg-creation-to-.patch +Patch0987: hw-arm-virt-acpi-build.c-Migrate-virtio-creation-to-.patch +Patch0988: hw-i386-acpi-microvm.c-Use-common-function-to-add-vi.patch +Patch0989: hw-riscv-virt-Make-few-IMSIC-macros-and-functions-pu.patch +Patch0990: hw-riscv-virt-acpi-build.c-Add-AIA-support-in-RINTC.patch +Patch0991: hw-riscv-virt-acpi-build.c-Add-IMSIC-in-the-MADT.patch +Patch0992: hw-riscv-virt-acpi-build.c-Add-APLIC-in-the-MADT.patch +Patch0993: hw-riscv-virt-acpi-build.c-Add-CMO-information-in-RH.patch +Patch0994: hw-riscv-virt-acpi-build.c-Add-MMU-node-in-RHCT.patch +Patch0995: hw-pci-host-gpex-Define-properties-for-MMIO-ranges.patch +Patch0996: hw-riscv-virt-Update-GPEX-MMIO-related-properties.patch +Patch0997: hw-riscv-virt-acpi-build.c-Add-IO-controllers-and-de.patch +Patch0998: hw-riscv-virt-acpi-build.c-Add-PLIC-in-MADT.patch +Patch0999: hw-riscv-virt.c-fix-the-interrupts-extended-property.patch +Patch1000: hw-riscv-virt-acpi-build.c-Add-namespace-devices-for.patch +Patch1001: hw-riscv-virt-acpi-build.c-Update-the-HID-of-RISC-V-.patch +Patch1002: hw-riscv-virt-acpi-build.c-Generate-SPCR-table.patch +Patch1003: hw-riscv-virt-acpi-build.c-Add-SRAT-and-SLIT-ACPI-ta.patch +Patch1004: plugins-loader-fix-deadlock-when-resetting-uninstall.patch +Patch1005: smbios-Fix-buffer-overrun-when-using-path-option.patch BuildRequires: flex BuildRequires: gcc @@ -1599,6 +1621,30 @@ getent passwd qemu >/dev/null || \ %endif %changelog +* Tue Aug 26 2025 Pengrui Zhang - 11:8.2.0-41 +- target/i386/kvm: Refine VMX controls setting for backward compatibility +- Bugfix: Correctly set vms->bootinfo.confidential in virtCCA senarios. +- hw/arm/virt-acpi-build.c: Migrate fw_cfg creation to common location +- hw/arm/virt-acpi-build.c: Migrate virtio creation to common location +- hw/i386/acpi-microvm.c: Use common function to add virtio in DSDT +- hw/riscv: virt: Make few IMSIC macros and functions public +- hw/riscv/virt-acpi-build.c: Add AIA support in RINTC +- hw/riscv/virt-acpi-build.c: Add IMSIC in the MADT +- hw/riscv/virt-acpi-build.c: Add APLIC in the MADT +- hw/riscv/virt-acpi-build.c: Add CMO information in RHCT +- hw/riscv/virt-acpi-build.c: Add MMU node in RHCT +- hw/pci-host/gpex: Define properties for MMIO ranges +- hw/riscv/virt: Update GPEX MMIO related properties +- hw/riscv/virt-acpi-build.c: Add IO controllers and devices +- hw/riscv/virt-acpi-build.c: Add PLIC in MADT +- hw/riscv/virt.c: fix the interrupts-extended property format of PLIC +- hw/riscv/virt-acpi-build.c: Add namespace devices for PLIC and APLIC +- hw/riscv/virt-acpi-build.c: Update the HID of RISC-V UART +- hw/riscv/virt-acpi-build.c: Generate SPCR table +- hw/riscv/virt-acpi-build.c: Add SRAT and SLIT ACPI tables +- plugins/loader: fix deadlock when resetting/uninstalling a plugin +- smbios: Fix buffer overrun when using path= option + * Wed Aug 13 2025 Pengrui Zhang - 11:8.2.0-40 - hw/acpi: Fix the memory leak issue - virtio-net: Fix num_buffers for version 1 diff --git a/smbios-Fix-buffer-overrun-when-using-path-option.patch b/smbios-Fix-buffer-overrun-when-using-path-option.patch new file mode 100644 index 0000000..b96a186 --- /dev/null +++ b/smbios-Fix-buffer-overrun-when-using-path-option.patch @@ -0,0 +1,42 @@ +From 7c76516fee790add2ba308b38999e5cebbd24523 Mon Sep 17 00:00:00 2001 +From: jiesong +Date: Wed, 13 Aug 2025 23:11:18 +0800 +Subject: [PATCH] smbios: Fix buffer overrun when using path= option +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +We have to make sure the array of bytes read from the path= file +is null-terminated, otherwise we run into a buffer overrun later on. + +Fixes: bb99f477 ("hw/smbios: support loading OEM strings values from a file") +Resolves: #2879 + +Signed-off-by: default avatarDaan De Meyer +Reviewed-by: default avatarDaniel P. Berrangé +Tested-by: default avatarValentin David +Message-ID: <20250323213622.2581013-1-daan.j.demeyer@gmail.com> +Signed-off-by: default avatarPhilippe Mathieu-Daudé +(cherry picked from commit a7a05f5f) +Signed-off-by: default avatarMichael Tokarev +--- + hw/smbios/smbios.c | 3 +++ + 1 file changed, 3 insertions(+) + +diff --git a/hw/smbios/smbios.c b/hw/smbios/smbios.c +index c0c5a81e66..be726ce4ac 100644 +--- a/hw/smbios/smbios.c ++++ b/hw/smbios/smbios.c +@@ -1223,6 +1223,9 @@ static int save_opt_one(void *opaque, + g_byte_array_append(data, (guint8 *)buf, ret); + } + ++ buf[0] = '\0'; ++ g_byte_array_append(data, (guint8 *)buf, 1); ++ + qemu_close(fd); + + *opt->dest = g_renew(char *, *opt->dest, (*opt->ndest) + 1); +-- +2.33.0 + diff --git a/target-i386-kvm-Refine-VMX-controls-setting-for-back.patch b/target-i386-kvm-Refine-VMX-controls-setting-for-back.patch new file mode 100644 index 0000000..47b7268 --- /dev/null +++ b/target-i386-kvm-Refine-VMX-controls-setting-for-back.patch @@ -0,0 +1,68 @@ +From ef76ea9ce99c8158a09f243a9a7f5c9819a2b97b Mon Sep 17 00:00:00 2001 +From: EwanHai +Date: Thu, 5 Jun 2025 03:44:26 -0400 +Subject: [PATCH] target/i386/kvm: Refine VMX controls setting for backward + compatibility + +Upstream qemu commit 4a910e1 ("target/i386: do not set unsupported VMX secondary +execution controls") implemented a workaround for hosts that have +specific CPUID features but do not support the corresponding VMX +controls, e.g., hosts support RDSEED but do not support RDSEED-Exiting. + +In detail, commit 4a910e1 introduced a flag `has_msr_vmx_procbased_clts2`. +If KVM has `MSR_IA32_VMX_PROCBASED_CTLS2` in its msr list, QEMU would +use KVM's settings, avoiding any modifications to this MSR. + +However, this commit (4a910e1) didn't account for cases in older Linux +kernels(4.17~5.2) where `MSR_IA32_VMX_PROCBASED_CTLS2` is in +`kvm_feature_msrs`-obtained by ioctl(KVM_GET_MSR_FEATURE_INDEX_LIST), +but not in `kvm_msr_list`-obtained by ioctl(KVM_GET_MSR_INDEX_LIST). +As a result,it did not set the `has_msr_vmx_procbased_clts2` flag based +on `kvm_msr_list` alone, even though KVM does maintain the value of +this MSR. + +This patch supplements the above logic, ensuring that +`has_msr_vmx_procbased_clts2` is correctly set by checking both MSR +lists, thus maintaining compatibility with older kernels. + +Signed-off-by: EwanHai +--- + target/i386/kvm/kvm.c | 15 +++++++++++++++ + 1 file changed, 15 insertions(+) + +diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c +index 3a88e65635..2f379876e6 100644 +--- a/target/i386/kvm/kvm.c ++++ b/target/i386/kvm/kvm.c +@@ -2314,6 +2314,7 @@ void kvm_arch_do_init_vcpu(X86CPU *cpu) + static int kvm_get_supported_feature_msrs(KVMState *s) + { + int ret = 0; ++ int i; + + if (kvm_feature_msrs != NULL) { + return 0; +@@ -2348,6 +2349,20 @@ static int kvm_get_supported_feature_msrs(KVMState *s) + return ret; + } + ++ /* ++ * Compatibility fix: ++ * Older Linux kernels (4.17~5.2) report MSR_IA32_VMX_PROCBASED_CTLS2 ++ * in KVM_GET_MSR_FEATURE_INDEX_LIST but not in KVM_GET_MSR_INDEX_LIST. ++ * This leads to an issue in older kernel versions where QEMU, ++ * through the KVM_GET_MSR_INDEX_LIST check, assumes the kernel ++ * doesn't maintain MSR_IA32_VMX_PROCBASED_CTLS2, resulting in ++ * incorrect settings by QEMU for this MSR. ++ */ ++ for (i = 0; i < kvm_feature_msrs->nmsrs; i++) { ++ if (kvm_feature_msrs->indices[i] == MSR_IA32_VMX_PROCBASED_CTLS2) { ++ has_msr_vmx_procbased_ctls2 = true; ++ } ++ } + return 0; + } + +-- +2.33.0 + -- Gitee