From 6eb346e60c94a35468fbfb66caabb07c770eebfa Mon Sep 17 00:00:00 2001 From: Peng Liang Date: Wed, 16 Sep 2020 19:40:28 +0800 Subject: [PATCH 1/6] target/arm: only set ID_PFR1_EL1.GIC for AArch32 guest Some AArch64 CPU doesn't support AArch32 mode, and the values of AArch32 registers are all 0. Hence, We'd better not to modify AArch32 registers in AArch64 mode. Signed-off-by: zhanghailiang Signed-off-by: Peng Liang --- ...set-ID_PFR1_EL1.GIC-for-AArch32-gues.patch | 31 +++++++++++++++++++ 1 file changed, 31 insertions(+) create mode 100644 target-arm-only-set-ID_PFR1_EL1.GIC-for-AArch32-gues.patch diff --git a/target-arm-only-set-ID_PFR1_EL1.GIC-for-AArch32-gues.patch b/target-arm-only-set-ID_PFR1_EL1.GIC-for-AArch32-gues.patch new file mode 100644 index 0000000..91702db --- /dev/null +++ b/target-arm-only-set-ID_PFR1_EL1.GIC-for-AArch32-gues.patch @@ -0,0 +1,31 @@ +From 88e3146118230de8b99280db219a6a6c47bebce1 Mon Sep 17 00:00:00 2001 +From: Peng Liang +Date: Wed, 16 Sep 2020 19:40:28 +0800 +Subject: [PATCH] target/arm: only set ID_PFR1_EL1.GIC for AArch32 guest + +Some AArch64 CPU doesn't support AArch32 mode, and the values of AArch32 +registers are all 0. Hence, We'd better not to modify AArch32 registers +in AArch64 mode. + +Signed-off-by: zhanghailiang +Signed-off-by: Peng Liang +--- + target/arm/helper.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/target/arm/helper.c b/target/arm/helper.c +index 97b6b86197..b262f5d6c5 100644 +--- a/target/arm/helper.c ++++ b/target/arm/helper.c +@@ -5672,7 +5672,7 @@ static uint64_t id_pfr1_read(CPUARMState *env, const ARMCPRegInfo *ri) + ARMCPU *cpu = env_archcpu(env); + uint64_t pfr1 = cpu->id_pfr1; + +- if (env->gicv3state) { ++ if (!arm_feature(&cpu->env, ARM_FEATURE_AARCH64) && env->gicv3state) { + pfr1 |= 1 << 28; + } + return pfr1; +-- +2.23.0 + -- Gitee From 9733f4067aaa68a6090ca6e7a8164e8d52a2fab6 Mon Sep 17 00:00:00 2001 From: Peng Liang Date: Mon, 21 Sep 2020 22:14:20 +0800 Subject: [PATCH 2/6] target/arm: clear EL2 and EL3 only when kvm is not enabled When has_el2 and has_el3 are disabled, which is the default value for virt machine, QEMU will clear the corresponding field in ID_PFR1_EL1 and ID_AA64PFR0_EL1 to not expose EL3 and EL2 to guest. Because KVM doesn't support to emulate ID registers in AArch64 before, it will not take effect. Hence, clear EL2 and EL3 only when kvm is not enabled for backwards compatibility. Signed-off-by: Peng Liang --- ...-EL2-and-EL3-only-when-kvm-is-not-en.patch | 42 +++++++++++++++++++ 1 file changed, 42 insertions(+) create mode 100644 target-arm-clear-EL2-and-EL3-only-when-kvm-is-not-en.patch diff --git a/target-arm-clear-EL2-and-EL3-only-when-kvm-is-not-en.patch b/target-arm-clear-EL2-and-EL3-only-when-kvm-is-not-en.patch new file mode 100644 index 0000000..455dc84 --- /dev/null +++ b/target-arm-clear-EL2-and-EL3-only-when-kvm-is-not-en.patch @@ -0,0 +1,42 @@ +From ad6ce039cab07b6a99ccaa36fbb0043ae85a74c9 Mon Sep 17 00:00:00 2001 +From: Peng Liang +Date: Mon, 21 Sep 2020 22:14:20 +0800 +Subject: [PATCH] target/arm: clear EL2 and EL3 only when kvm is not enabled + +When has_el2 and has_el3 are disabled, which is the default value for +virt machine, QEMU will clear the corresponding field in ID_PFR1_EL1 and +ID_AA64PFR0_EL1 to not expose EL3 and EL2 to guest. Because KVM doesn't +support to emulate ID registers in AArch64 before, it will not take +effect. Hence, clear EL2 and EL3 only when kvm is not enabled for +backwards compatibility. + +Signed-off-by: Peng Liang +--- + target/arm/cpu.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/target/arm/cpu.c b/target/arm/cpu.c +index 7ae2d3da56..3f62336acf 100644 +--- a/target/arm/cpu.c ++++ b/target/arm/cpu.c +@@ -1996,7 +1996,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) + } + } + +- if (!cpu->has_el3) { ++ if (!cpu->has_el3 && !kvm_enabled()) { + /* If the has_el3 CPU property is disabled then we need to disable the + * feature. + */ +@@ -2037,7 +2037,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) + cpu->pmceid1 = 0; + } + +- if (!arm_feature(env, ARM_FEATURE_EL2)) { ++ if (!arm_feature(env, ARM_FEATURE_EL2) && !kvm_enabled()) { + /* Disable the hypervisor feature bits in the processor feature + * registers if we don't have EL2. These are id_pfr1[15:12] and + * id_aa64pfr0_el1[11:8]. +-- +2.23.0 + -- Gitee From 7f6f8a6db9094643cc0d8d8a6c65aea1626fc92b Mon Sep 17 00:00:00 2001 From: Euler Robot Date: Tue, 22 Sep 2020 14:38:21 +0800 Subject: [PATCH 3/6] spec: Update patch and changelog with !11 target/arm: only set ID_PFR1_EL1.GIC for AArch32 guest target/arm: clear EL2 and EL3 only when kvm is not enabled Signed-off-by: Peng Liang Signed-off-by: zhanghailiang --- qemu.spec | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/qemu.spec b/qemu.spec index 3d4287d..08cad26 100644 --- a/qemu.spec +++ b/qemu.spec @@ -291,6 +291,8 @@ Patch0278: migration-savevm-release-gslist-after-dump_vmstate_j.patch Patch0279: virtio-input-fix-memory-leak-on-unrealize.patch Patch0280: hw-sd-sdhci-Fix-DMA-Transfer-Block-Size-field.patch Patch0281: hw-xhci-check-return-value-of-usb_packet_map.patch +Patch0282: target-arm-only-set-ID_PFR1_EL1.GIC-for-AArch32-gues.patch +Patch0283: target-arm-clear-EL2-and-EL3-only-when-kvm-is-not-en.patch BuildRequires: flex BuildRequires: bison @@ -637,6 +639,10 @@ getent passwd qemu >/dev/null || \ %endif %changelog +* Mon Sep 21 2020 Peng Liang +- target/arm: only set ID_PFR1_EL1.GIC for AArch32 guest +- target/arm: clear EL2 and EL3 only when kvm is not enabled + * Fri Sep 18 2020 Huawei Technologies Co., Ltd - hw-sd-sdhci-Fix-DMA-Transfer-Block-Size-field.patch - hw-xhci-check-return-value-of-usb_packet_map.patch -- Gitee From 0db2b0adb4b8edb33046a3d451ae97feb45d77fa Mon Sep 17 00:00:00 2001 From: Peng Liang Date: Sat, 19 Sep 2020 09:04:45 +0800 Subject: [PATCH 4/6] target/arm: Update the ID registers of Kunpeng-920 The values of some ID registers in Kunpeng-920 are not exactly correct. Let's update them. The values are read from Kunpeng-920 by calling read_sysreg_s. Signed-off-by: Peng Liang --- ...date-the-ID-registers-of-Kunpeng-920.patch | 57 +++++++++++++++++++ 1 file changed, 57 insertions(+) create mode 100644 target-arm-Update-the-ID-registers-of-Kunpeng-920.patch diff --git a/target-arm-Update-the-ID-registers-of-Kunpeng-920.patch b/target-arm-Update-the-ID-registers-of-Kunpeng-920.patch new file mode 100644 index 0000000..586dcbb --- /dev/null +++ b/target-arm-Update-the-ID-registers-of-Kunpeng-920.patch @@ -0,0 +1,57 @@ +From b54ca94f19a9b22537712638ae05d2095258eb80 Mon Sep 17 00:00:00 2001 +From: Peng Liang +Date: Sat, 19 Sep 2020 09:04:45 +0800 +Subject: [PATCH] target/arm: Update the ID registers of Kunpeng-920 + +The values of some ID registers in Kunpeng-920 are not exactly correct. +Let's update them. The values are read from Kunpeng-920 by calling +read_sysreg_s. + +Signed-off-by: Peng Liang +--- + target/arm/cpu64.c | 27 +++++++++++++++++++++++++-- + 1 file changed, 25 insertions(+), 2 deletions(-) + +diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c +index 726d123d8e..a1649f8844 100644 +--- a/target/arm/cpu64.c ++++ b/target/arm/cpu64.c +@@ -275,10 +275,33 @@ static void aarch64_kunpeng_920_initfn(Object *obj) + + cpu->midr = 0x480fd010; + cpu->ctr = 0x84448004; +- cpu->isar.regs[ID_AA64PFR0] = 0x11001111; ++ cpu->isar.regs[ID_ISAR0] = 0; ++ cpu->isar.regs[ID_ISAR1] = 0; ++ cpu->isar.regs[ID_ISAR2] = 0; ++ cpu->isar.regs[ID_ISAR3] = 0; ++ cpu->isar.regs[ID_ISAR4] = 0; ++ cpu->isar.regs[ID_ISAR5] = 0; ++ cpu->isar.regs[ID_MMFR0] = 0; ++ cpu->isar.regs[ID_MMFR1] = 0; ++ cpu->isar.regs[ID_MMFR2] = 0; ++ cpu->isar.regs[ID_MMFR3] = 0; ++ cpu->isar.regs[ID_MMFR4] = 0; ++ cpu->isar.regs[MVFR0] = 0; ++ cpu->isar.regs[MVFR1] = 0; ++ cpu->isar.regs[MVFR2] = 0; ++ cpu->isar.regs[ID_DFR0] = 0; ++ cpu->isar.regs[MVFR2] = 0; ++ cpu->isar.regs[MVFR2] = 0; ++ cpu->isar.regs[MVFR2] = 0; ++ cpu->id_pfr0 = 0; ++ cpu->id_pfr1 = 0; ++ cpu->isar.regs[ID_AA64PFR0] = 0x0000010011111111; + cpu->isar.regs[ID_AA64DFR0] = 0x110305408; +- cpu->isar.regs[ID_AA64ISAR0] = 0x10211120; ++ cpu->isar.regs[ID_AA64ISAR0] = 0x0001100010211120; ++ cpu->isar.regs[ID_AA64ISAR1] = 0x00011001; + cpu->isar.regs[ID_AA64MMFR0] = 0x101125; ++ cpu->isar.regs[ID_AA64MMFR1] = 0x10211122; ++ cpu->isar.regs[ID_AA64MMFR2] = 0x00001011; + } + + static void cpu_max_get_sve_vq(Object *obj, Visitor *v, const char *name, +-- +2.23.0 + -- Gitee From 28c8927a8b795cd463e7d0f55ed13f023361a3c5 Mon Sep 17 00:00:00 2001 From: Euler Robot Date: Tue, 22 Sep 2020 14:38:22 +0800 Subject: [PATCH 5/6] spec: Update patch and changelog with !12 target/arm: Update the ID registers of Kunpeng-920 Signed-off-by: Peng Liang --- qemu.spec | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/qemu.spec b/qemu.spec index 08cad26..8a2e4cc 100644 --- a/qemu.spec +++ b/qemu.spec @@ -293,6 +293,7 @@ Patch0280: hw-sd-sdhci-Fix-DMA-Transfer-Block-Size-field.patch Patch0281: hw-xhci-check-return-value-of-usb_packet_map.patch Patch0282: target-arm-only-set-ID_PFR1_EL1.GIC-for-AArch32-gues.patch Patch0283: target-arm-clear-EL2-and-EL3-only-when-kvm-is-not-en.patch +Patch0284: target-arm-Update-the-ID-registers-of-Kunpeng-920.patch BuildRequires: flex BuildRequires: bison @@ -639,6 +640,9 @@ getent passwd qemu >/dev/null || \ %endif %changelog +* Sat Sep 19 2020 Peng Liang +- target/arm: Update the ID registers of Kunpeng-920 + * Mon Sep 21 2020 Peng Liang - target/arm: only set ID_PFR1_EL1.GIC for AArch32 guest - target/arm: clear EL2 and EL3 only when kvm is not enabled -- Gitee From 60f7f23c5a46e52fa320f883bf34dcddc824557a Mon Sep 17 00:00:00 2001 From: Euler Robot Date: Tue, 22 Sep 2020 14:38:22 +0800 Subject: [PATCH 6/6] spec: Update release version with !11 !12 increase release verison by one Signed-off-by: Euler Robot --- qemu.spec | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qemu.spec b/qemu.spec index 8a2e4cc..3ad6f7e 100644 --- a/qemu.spec +++ b/qemu.spec @@ -1,6 +1,6 @@ Name: qemu Version: 4.1.0 -Release: 30 +Release: 31 Epoch: 2 Summary: QEMU is a generic and open source machine emulator and virtualizer License: GPLv2 and BSD and MIT and CC-BY -- Gitee