From 3265d8ae1df6666aab6aa75c18eee8e53b779dab Mon Sep 17 00:00:00 2001 From: Chen Qun Date: Thu, 18 Jul 2019 15:34:05 +0800 Subject: [PATCH 1/5] target/i386: Introduce Denverton CPU model Denverton is the Atom Processor of Intel Harrisonville platform. For more information: https://ark.intel.com/content/www/us/en/ark/products/\ codename/63508/denverton.html Signed-off-by: Tao Xu Message-Id: <20190718073405.28301-1-tao3.xu@intel.com> Signed-off-by: Eduardo Habkost --- ...t-i386-Introduce-Denverton-CPU-model.patch | 79 +++++++++++++++++++ 1 file changed, 79 insertions(+) create mode 100644 target-i386-Introduce-Denverton-CPU-model.patch diff --git a/target-i386-Introduce-Denverton-CPU-model.patch b/target-i386-Introduce-Denverton-CPU-model.patch new file mode 100644 index 0000000..3e9debe --- /dev/null +++ b/target-i386-Introduce-Denverton-CPU-model.patch @@ -0,0 +1,79 @@ +From 7d602cefa04f4992d913683c1a5826abc4806e41 Mon Sep 17 00:00:00 2001 +From: Tao Xu +Date: Thu, 18 Jul 2019 15:34:05 +0800 +Subject: [PATCH] target/i386: Introduce Denverton CPU model + +Denverton is the Atom Processor of Intel Harrisonville platform. + +For more information: +https://ark.intel.com/content/www/us/en/ark/products/\ +codename/63508/denverton.html + +Signed-off-by: Tao Xu +Message-Id: <20190718073405.28301-1-tao3.xu@intel.com> +Signed-off-by: Eduardo Habkost +--- + target/i386/cpu.c | 47 +++++++++++++++++++++++++++++++++++++++++++++++ + 1 file changed, 47 insertions(+) + +diff --git a/target/i386/cpu.c b/target/i386/cpu.c +index 5af4fca350..d3742ef4ac 100644 +--- a/target/i386/cpu.c ++++ b/target/i386/cpu.c +@@ -2552,6 +2552,53 @@ static X86CPUDefinition builtin_x86_defs[] = { + .xlevel = 0x80000008, + .model_id = "Intel Xeon Processor (Icelake)", + }, ++ { ++ .name = "Denverton", ++ .level = 21, ++ .vendor = CPUID_VENDOR_INTEL, ++ .family = 6, ++ .model = 95, ++ .stepping = 1, ++ .features[FEAT_1_EDX] = ++ CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC | ++ CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | ++ CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | ++ CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR | ++ CPUID_SSE | CPUID_SSE2, ++ .features[FEAT_1_ECX] = ++ CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_MONITOR | ++ CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | CPUID_EXT_SSE41 | ++ CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | ++ CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER | ++ CPUID_EXT_AES | CPUID_EXT_XSAVE | CPUID_EXT_RDRAND, ++ .features[FEAT_8000_0001_EDX] = ++ CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB | ++ CPUID_EXT2_RDTSCP | CPUID_EXT2_LM, ++ .features[FEAT_8000_0001_ECX] = ++ CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, ++ .features[FEAT_7_0_EBX] = ++ CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_ERMS | ++ CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_SMAP | ++ CPUID_7_0_EBX_CLFLUSHOPT | CPUID_7_0_EBX_SHA_NI, ++ .features[FEAT_7_0_EDX] = ++ CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_ARCH_CAPABILITIES | ++ CPUID_7_0_EDX_SPEC_CTRL_SSBD, ++ /* ++ * Missing: XSAVES (not supported by some Linux versions, ++ * including v4.1 to v4.12). ++ * KVM doesn't yet expose any XSAVES state save component, ++ * and the only one defined in Skylake (processor tracing) ++ * probably will block migration anyway. ++ */ ++ .features[FEAT_XSAVE] = ++ CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | CPUID_XSAVE_XGETBV1, ++ .features[FEAT_6_EAX] = ++ CPUID_6_EAX_ARAT, ++ .features[FEAT_ARCH_CAPABILITIES] = ++ MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY, ++ .xlevel = 0x80000008, ++ .model_id = "Intel Atom Processor (Denverton)", ++ }, + { + .name = "Snowridge", + .level = 27, +-- +2.27.0 + -- Gitee From f8b061efaa85eb86d82dcced72473468d2b8dd59 Mon Sep 17 00:00:00 2001 From: Chen Qun Date: Sat, 12 Oct 2019 10:47:48 +0800 Subject: [PATCH 2/5] target/i386: Add Snowridge-v2 (no MPX) CPU model Add new version of Snowridge CPU model that removes MPX feature. MPX support is being phased out by Intel. GCC has dropped it, Linux kernel and KVM are also going to do that in the future. Signed-off-by: Xiaoyao Li Message-Id: <20191012024748.127135-1-xiaoyao.li@intel.com> Signed-off-by: Eduardo Habkost --- ...86-Add-Snowridge-v2-no-MPX-CPU-model.patch | 43 +++++++++++++++++++ 1 file changed, 43 insertions(+) create mode 100644 target-i386-Add-Snowridge-v2-no-MPX-CPU-model.patch diff --git a/target-i386-Add-Snowridge-v2-no-MPX-CPU-model.patch b/target-i386-Add-Snowridge-v2-no-MPX-CPU-model.patch new file mode 100644 index 0000000..eedd335 --- /dev/null +++ b/target-i386-Add-Snowridge-v2-no-MPX-CPU-model.patch @@ -0,0 +1,43 @@ +From ce4bb30a650773833cd1e86afcaa30e47259085c Mon Sep 17 00:00:00 2001 +From: Xiaoyao Li +Date: Sat, 12 Oct 2019 10:47:48 +0800 +Subject: [PATCH] target/i386: Add Snowridge-v2 (no MPX) CPU model + +Add new version of Snowridge CPU model that removes MPX feature. + +MPX support is being phased out by Intel. GCC has dropped it, Linux kernel +and KVM are also going to do that in the future. + +Signed-off-by: Xiaoyao Li +Message-Id: <20191012024748.127135-1-xiaoyao.li@intel.com> +Signed-off-by: Eduardo Habkost +--- + target/i386/cpu.c | 12 ++++++++++++ + 1 file changed, 12 insertions(+) + +diff --git a/target/i386/cpu.c b/target/i386/cpu.c +index d3742ef4ac..f09612f9da 100644 +--- a/target/i386/cpu.c ++++ b/target/i386/cpu.c +@@ -2668,6 +2668,18 @@ static X86CPUDefinition builtin_x86_defs[] = { + CPUID_6_EAX_ARAT, + .xlevel = 0x80000008, + .model_id = "Intel Atom Processor (SnowRidge)", ++ .versions = (X86CPUVersionDefinition[]) { ++ { .version = 1 }, ++ { ++ .version = 2, ++ .props = (PropValue[]) { ++ { "mpx", "off" }, ++ { "model-id", "Intel Atom Processor (Snowridge, no MPX)" }, ++ { /* end of list */ }, ++ }, ++ }, ++ { /* end of list */ }, ++ }, + }, + { + .name = "KnightsMill", +-- +2.27.0 + -- Gitee From 0b329b7ce36360c6e00313ba281d79b7c66a7c5f Mon Sep 17 00:00:00 2001 From: Chen Qun Date: Wed, 25 Sep 2019 23:49:48 +0200 Subject: [PATCH 3/5] i386: Add CPUID bit for CLZERO and XSAVEERPTR The CPUID bits CLZERO and XSAVEERPTR are availble on AMD's ZEN platform and could be passed to the guest. Signed-off-by: Sebastian Andrzej Siewior Signed-off-by: Paolo Bonzini --- ...-CPUID-bit-for-CLZERO-and-XSAVEERPTR.patch | 44 +++++++++++++++++++ 1 file changed, 44 insertions(+) create mode 100644 i386-Add-CPUID-bit-for-CLZERO-and-XSAVEERPTR.patch diff --git a/i386-Add-CPUID-bit-for-CLZERO-and-XSAVEERPTR.patch b/i386-Add-CPUID-bit-for-CLZERO-and-XSAVEERPTR.patch new file mode 100644 index 0000000..dfa4a70 --- /dev/null +++ b/i386-Add-CPUID-bit-for-CLZERO-and-XSAVEERPTR.patch @@ -0,0 +1,44 @@ +From a6206163d42156cb9de290f914c6883c77b012b9 Mon Sep 17 00:00:00 2001 +From: Sebastian Andrzej Siewior +Date: Wed, 25 Sep 2019 23:49:48 +0200 +Subject: [PATCH] i386: Add CPUID bit for CLZERO and XSAVEERPTR + +The CPUID bits CLZERO and XSAVEERPTR are availble on AMD's ZEN platform +and could be passed to the guest. + +Signed-off-by: Sebastian Andrzej Siewior +Signed-off-by: Paolo Bonzini +--- + target/i386/cpu.c | 2 +- + target/i386/cpu.h | 2 ++ + 2 files changed, 3 insertions(+), 1 deletion(-) + +diff --git a/target/i386/cpu.c b/target/i386/cpu.c +index f09612f9da..e65f372f25 100644 +--- a/target/i386/cpu.c ++++ b/target/i386/cpu.c +@@ -1134,7 +1134,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = { + [FEAT_8000_0008_EBX] = { + .type = CPUID_FEATURE_WORD, + .feat_names = { +- NULL, NULL, NULL, NULL, ++ "clzero", NULL, "xsaveerptr", NULL, + NULL, NULL, NULL, NULL, + NULL, "wbnoinvd", NULL, NULL, + "ibpb", NULL, NULL, NULL, +diff --git a/target/i386/cpu.h b/target/i386/cpu.h +index 7ff8ddd464..24d489db0f 100644 +--- a/target/i386/cpu.h ++++ b/target/i386/cpu.h +@@ -696,6 +696,8 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS]; + + #define CPUID_7_1_EAX_AVX512_BF16 (1U << 5) /* AVX512 BFloat16 Instruction */ + ++#define CPUID_8000_0008_EBX_CLZERO (1U << 0) /* CLZERO instruction */ ++#define CPUID_8000_0008_EBX_XSAVEERPTR (1U << 2) /* Always save/restore FP error pointers */ + #define CPUID_8000_0008_EBX_WBNOINVD (1U << 9) /* Write back and + do not invalidate cache */ + #define CPUID_8000_0008_EBX_IBPB (1U << 12) /* Indirect Branch Prediction Barrier */ +-- +2.27.0 + -- Gitee From dadccf364631b178ba926934a372735bafadd9c8 Mon Sep 17 00:00:00 2001 From: Chen Qun Date: Tue, 20 Jul 2021 16:27:34 +0800 Subject: [PATCH 4/5] spec: Update patch and changelog with !161 x86: new CPU models for Denverton (server-class Atom-based SoC), Snowridge, and Dhyana !161 target/i386: Introduce Denverton CPU model target/i386: Add Snowridge-v2 (no MPX) CPU model i386: Add CPUID bit for CLZERO and XSAVEERPTR Signed-off-by: Chen Qun --- qemu.spec | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/qemu.spec b/qemu.spec index 23a9ced..ca424ab 100644 --- a/qemu.spec +++ b/qemu.spec @@ -346,6 +346,9 @@ Patch0333: target-i386-Add-new-bit-definitions-of-MSR_IA32_ARCH.patch Patch0334: target-i386-Add-missed-security-features-to-Cooperla.patch Patch0335: target-i386-add-PSCHANGE_NO-bit-for-the-ARCH_CAPABIL.patch Patch0336: target-i386-Export-TAA_NO-bit-to-guests.patch +Patch0337: target-i386-Introduce-Denverton-CPU-model.patch +Patch0338: target-i386-Add-Snowridge-v2-no-MPX-CPU-model.patch +Patch0339: i386-Add-CPUID-bit-for-CLZERO-and-XSAVEERPTR.patch BuildRequires: flex BuildRequires: gcc @@ -740,6 +743,11 @@ getent passwd qemu >/dev/null || \ %endif %changelog +* Tue Jul 20 2021 Chen Qun +- target/i386: Introduce Denverton CPU model +- target/i386: Add Snowridge-v2 (no MPX) CPU model +- i386: Add CPUID bit for CLZERO and XSAVEERPTR + * Mon Jul 19 2021 Chen Qun - x86: Intel AVX512_BF16 feature enabling - i386: Add MSR feature bit for MDS-NO -- Gitee From b43563c752e08311fc78470c8ee240581b1ccbf0 Mon Sep 17 00:00:00 2001 From: Chen Qun Date: Tue, 20 Jul 2021 16:27:34 +0800 Subject: [PATCH 5/5] spec: Update release version with !161 increase release verison by one Signed-off-by: Chen Qun --- qemu.spec | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qemu.spec b/qemu.spec index ca424ab..2d8081e 100644 --- a/qemu.spec +++ b/qemu.spec @@ -1,6 +1,6 @@ Name: qemu Version: 4.1.0 -Release: 62 +Release: 63 Epoch: 2 Summary: QEMU is a generic and open source machine emulator and virtualizer License: GPLv2 and BSD and MIT and CC-BY-SA-4.0 -- Gitee