From 24c97e9e43e6f18d003d26ff1d303088c79299d0 Mon Sep 17 00:00:00 2001 From: imxcc Date: Fri, 11 Feb 2022 15:35:27 +0800 Subject: [PATCH] Update with openEuler !230 Signed-off-by: imxcc --- ...tex-A72-processor-kvm-target-support.patch | 59 ++++++++++++++++ ...ortex-A72-processor-kvm-target-suppo.patch | 49 ++++++++++++++ ...t-cpu-parse-feature-to-avoid-failure.patch | 67 +++++++++++++++++++ qemu.spec | 12 +++- 4 files changed, 184 insertions(+), 3 deletions(-) create mode 100644 0003-cpu-add-Cortex-A72-processor-kvm-target-support.patch create mode 100644 Revert-cpu-add-Cortex-A72-processor-kvm-target-suppo.patch create mode 100644 Revert-cpu-parse-feature-to-avoid-failure.patch diff --git a/0003-cpu-add-Cortex-A72-processor-kvm-target-support.patch b/0003-cpu-add-Cortex-A72-processor-kvm-target-support.patch new file mode 100644 index 00000000..a9819897 --- /dev/null +++ b/0003-cpu-add-Cortex-A72-processor-kvm-target-support.patch @@ -0,0 +1,59 @@ +From 8ddc2bcb196a34cc641d50b057550e4b11dc8700 Mon Sep 17 00:00:00 2001 +From: Xu Yandong +Date: Wed, 9 Feb 2022 17:39:34 +0800 +Subject: [PATCH 3/3] cpu: add Cortex-A72 processor kvm target support + +The ARM Cortex-A72 is ARMv8-A micro-architecture, +add kvm target to ARM Cortex-A72 processor definition. + +Signed-off-by: Xu Yandong +Signed-off-by: Mingwang Li +--- + target/arm/cpu64.c | 2 +- + target/arm/kvm-consts.h | 3 +++ + 2 files changed, 4 insertions(+), 1 deletion(-) + +diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c +index 26419fe994..1b56261964 100644 +--- a/target/arm/cpu64.c ++++ b/target/arm/cpu64.c +@@ -202,6 +202,7 @@ static void aarch64_a72_initfn(Object *obj) + ARMCPU *cpu = ARM_CPU(obj); + + cpu->dtb_compatible = "arm,cortex-a72"; ++ cpu->kvm_target = QEMU_KVM_ARM_TARGET_GENERIC_V8; + set_feature(&cpu->env, ARM_FEATURE_V8); + set_feature(&cpu->env, ARM_FEATURE_NEON); + set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); +@@ -265,7 +266,6 @@ static void aarch64_kunpeng_920_initfn(Object *obj) + cpu->isar.id_aa64dfr0 = 0x110305408; + cpu->isar.id_aa64isar0 = 0x10211120; + cpu->isar.id_aa64mmfr0 = 0x101125; +- cpu->kvm_target = KVM_ARM_TARGET_GENERIC_V8; + } + + void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) +diff --git a/target/arm/kvm-consts.h b/target/arm/kvm-consts.h +index 580f1c1fee..5f1311ade7 100644 +--- a/target/arm/kvm-consts.h ++++ b/target/arm/kvm-consts.h +@@ -130,6 +130,8 @@ MISMATCH_CHECK(QEMU_PSCI_RET_DISABLED, PSCI_RET_DISABLED); + #define QEMU_KVM_ARM_TARGET_CORTEX_A57 2 + #define QEMU_KVM_ARM_TARGET_XGENE_POTENZA 3 + #define QEMU_KVM_ARM_TARGET_CORTEX_A53 4 ++/* Generic ARM v8 target */ ++#define QEMU_KVM_ARM_TARGET_GENERIC_V8 5 + + /* There's no kernel define for this: sentinel value which + * matches no KVM target value for either 64 or 32 bit +@@ -141,6 +143,7 @@ MISMATCH_CHECK(QEMU_KVM_ARM_TARGET_FOUNDATION_V8, KVM_ARM_TARGET_FOUNDATION_V8); + MISMATCH_CHECK(QEMU_KVM_ARM_TARGET_CORTEX_A57, KVM_ARM_TARGET_CORTEX_A57); + MISMATCH_CHECK(QEMU_KVM_ARM_TARGET_XGENE_POTENZA, KVM_ARM_TARGET_XGENE_POTENZA); + MISMATCH_CHECK(QEMU_KVM_ARM_TARGET_CORTEX_A53, KVM_ARM_TARGET_CORTEX_A53); ++MISMATCH_CHECK(QEMU_KVM_ARM_TARGET_GENERIC_V8, KVM_ARM_TARGET_GENERIC_V8); + + #define CP_REG_ARM64 0x6000000000000000ULL + #define CP_REG_ARM_COPROC_MASK 0x000000000FFF0000 +-- +2.27.0 + diff --git a/Revert-cpu-add-Cortex-A72-processor-kvm-target-suppo.patch b/Revert-cpu-add-Cortex-A72-processor-kvm-target-suppo.patch new file mode 100644 index 00000000..684893c9 --- /dev/null +++ b/Revert-cpu-add-Cortex-A72-processor-kvm-target-suppo.patch @@ -0,0 +1,49 @@ +From 7474971c6fd6c6f77e66ded125e5f2521c7e12a2 Mon Sep 17 00:00:00 2001 +From: Mingwang Li +Date: Wed, 9 Feb 2022 17:35:52 +0800 +Subject: [PATCH 2/3] Revert "cpu: add Cortex-A72 processor kvm target support" + +This reverts commit f0da7fa5230b5f771570b2c12288e4a56a20dd97. + +Signed-off-by: Mingwang Li +--- + target/arm/cpu64.c | 1 - + target/arm/kvm-consts.h | 3 --- + 2 files changed, 4 deletions(-) + +diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c +index bd8e5b5676..26419fe994 100644 +--- a/target/arm/cpu64.c ++++ b/target/arm/cpu64.c +@@ -202,7 +202,6 @@ static void aarch64_a72_initfn(Object *obj) + ARMCPU *cpu = ARM_CPU(obj); + + cpu->dtb_compatible = "arm,cortex-a72"; +- cpu->kvm_target = QEMU_KVM_ARM_TARGET_GENERIC_V8; + set_feature(&cpu->env, ARM_FEATURE_V8); + set_feature(&cpu->env, ARM_FEATURE_NEON); + set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); +diff --git a/target/arm/kvm-consts.h b/target/arm/kvm-consts.h +index 5f1311ade7..580f1c1fee 100644 +--- a/target/arm/kvm-consts.h ++++ b/target/arm/kvm-consts.h +@@ -130,8 +130,6 @@ MISMATCH_CHECK(QEMU_PSCI_RET_DISABLED, PSCI_RET_DISABLED); + #define QEMU_KVM_ARM_TARGET_CORTEX_A57 2 + #define QEMU_KVM_ARM_TARGET_XGENE_POTENZA 3 + #define QEMU_KVM_ARM_TARGET_CORTEX_A53 4 +-/* Generic ARM v8 target */ +-#define QEMU_KVM_ARM_TARGET_GENERIC_V8 5 + + /* There's no kernel define for this: sentinel value which + * matches no KVM target value for either 64 or 32 bit +@@ -143,7 +141,6 @@ MISMATCH_CHECK(QEMU_KVM_ARM_TARGET_FOUNDATION_V8, KVM_ARM_TARGET_FOUNDATION_V8); + MISMATCH_CHECK(QEMU_KVM_ARM_TARGET_CORTEX_A57, KVM_ARM_TARGET_CORTEX_A57); + MISMATCH_CHECK(QEMU_KVM_ARM_TARGET_XGENE_POTENZA, KVM_ARM_TARGET_XGENE_POTENZA); + MISMATCH_CHECK(QEMU_KVM_ARM_TARGET_CORTEX_A53, KVM_ARM_TARGET_CORTEX_A53); +-MISMATCH_CHECK(QEMU_KVM_ARM_TARGET_GENERIC_V8, KVM_ARM_TARGET_GENERIC_V8); + + #define CP_REG_ARM64 0x6000000000000000ULL + #define CP_REG_ARM_COPROC_MASK 0x000000000FFF0000 +-- +2.27.0 + diff --git a/Revert-cpu-parse-feature-to-avoid-failure.patch b/Revert-cpu-parse-feature-to-avoid-failure.patch new file mode 100644 index 00000000..038edb89 --- /dev/null +++ b/Revert-cpu-parse-feature-to-avoid-failure.patch @@ -0,0 +1,67 @@ +From cae52ca5b1dd4a295eaabc9649481f3d6a684f06 Mon Sep 17 00:00:00 2001 +From: Mingwang Li +Date: Wed, 9 Feb 2022 17:33:26 +0800 +Subject: [PATCH 1/3] Revert "cpu: parse +/- feature to avoid failure" + +This reverts commit ef83cde8dd2c9b404527354489b14d2bd238733d. + +Signed-off-by: Mingwang Li +--- + target/arm/cpu64.c | 37 ------------------------------------- + 1 file changed, 37 deletions(-) + +diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c +index 08d886de7b..bd8e5b5676 100644 +--- a/target/arm/cpu64.c ++++ b/target/arm/cpu64.c +@@ -983,47 +983,10 @@ static gchar *aarch64_gdb_arch_name(CPUState *cs) + return g_strdup("aarch64"); + } + +-/* Parse "+feature,-feature,feature=foo" CPU feature string +- */ +-static void arm_cpu_parse_featurestr(const char *typename, char *features, +- Error **errp ) +-{ +- char *featurestr; +- char *val; +- static bool cpu_globals_initialized; +- +- if (cpu_globals_initialized) { +- return; +- } +- cpu_globals_initialized = true; +- +- featurestr = features ? strtok(features, ",") : NULL; +- while (featurestr) { +- val = strchr(featurestr, '='); +- if (val) { +- GlobalProperty *prop = g_new0(typeof(*prop), 1); +- *val = 0; +- val++; +- prop->driver = typename; +- prop->property = g_strdup(featurestr); +- prop->value = g_strdup(val); +- qdev_prop_register_global(prop); +- } else if (featurestr[0] == '+' || featurestr[0] == '-') { +- warn_report("Ignore %s feature\n", featurestr); +- } else { +- error_setg(errp, "Expected key=value format, found %s.", +- featurestr); +- return; +- } +- featurestr = strtok(NULL, ","); +- } +-} +- + static void aarch64_cpu_class_init(ObjectClass *oc, void *data) + { + CPUClass *cc = CPU_CLASS(oc); + +- cc->parse_features = arm_cpu_parse_featurestr; + cc->gdb_read_register = aarch64_cpu_gdb_read_register; + cc->gdb_write_register = aarch64_cpu_gdb_write_register; + cc->gdb_num_core_regs = 34; +-- +2.27.0 + diff --git a/qemu.spec b/qemu.spec index 9cb9e1e1..396811d7 100644 --- a/qemu.spec +++ b/qemu.spec @@ -1,6 +1,6 @@ Name: qemu Version: 6.2.0 -Release: 4 +Release: 5 Epoch: 2 Summary: QEMU is a generic and open source machine emulator and virtualizer License: GPLv2 and BSD and MIT and CC-BY-SA-4.0 @@ -29,8 +29,9 @@ Patch0016: migration-Add-multi-thread-compress-ops.patch Patch0017: migration-Add-zstd-support-in-multi-thread-compressi.patch Patch0018: migration-Add-compress_level-sanity-check.patch Patch0019: doc-Update-multi-thread-compression-doc.patch - - +Patch0020: Revert-cpu-parse-feature-to-avoid-failure.patch +Patch0021: Revert-cpu-add-Cortex-A72-processor-kvm-target-suppo.patch +Patch0022: 0003-cpu-add-Cortex-A72-processor-kvm-target-support.patch BuildRequires: flex BuildRequires: gcc @@ -473,6 +474,11 @@ getent passwd qemu >/dev/null || \ %endif %changelog +* Fri Feb 11 2022 imxcc +- Revert "cpu: parse +/- feature to avoid failure" +- Revert "cpu: add Cortex-A72 processor kvm target support" +- cpu: add Cortex-A72 processor kvm target support + * Thu Feb 10 2022 imxcc - qapi/block-core: Add retry option for error action - qapi/block-core: Add retry option for error action -- Gitee