From 1670f7256407121d83f24ebff0edf6c1fd4f3cf7 Mon Sep 17 00:00:00 2001 From: Yanjing Zhou Date: Wed, 15 May 2024 14:10:06 +0800 Subject: [PATCH] target/i386: Add Hygon Dhyana-v3 and Dharma CPU model Add the following feature bits for Dhyana-v3 CPU model: perfctr-core, clzero, xsaveerptr, aes, pclmulqdq, sha-ni Disable xsaves feature bit for Erratum 1386 Add the following feature bits for Dharma CPU model compare to Dhyana: stibp, ibrs, umip, ssbd Signed-off-by: Yanjing Zhou --- qemu.spec | 8 +- ...t-i386-Add-Hygon-Dhyana-v3-CPU-model.patch | 43 ++++++ ...-i386-Add-new-Hygon-Dharma-CPU-model.patch | 133 ++++++++++++++++++ 3 files changed, 183 insertions(+), 1 deletion(-) create mode 100644 target-i386-Add-Hygon-Dhyana-v3-CPU-model.patch create mode 100644 target-i386-Add-new-Hygon-Dharma-CPU-model.patch diff --git a/qemu.spec b/qemu.spec index cec3ffcc..84851662 100644 --- a/qemu.spec +++ b/qemu.spec @@ -3,7 +3,7 @@ Name: qemu Version: 8.2.0 -Release: 12 +Release: 13 Epoch: 11 Summary: QEMU is a generic and open source machine emulator and virtualizer License: GPLv2 and BSD and MIT and CC-BY-SA-4.0 @@ -259,6 +259,8 @@ Patch0242: hw-isa-vt82c686-Keep-track-of-PIRQ-PINT-pins-separat.patch Patch0243: target-i386-Introduce-Icelake-Server-v7-to-enable-TS.patch Patch0244: target-i386-Add-new-CPU-model-SierraForest.patch Patch0245: target-i386-Export-RFDS-bit-to-guests.patch +Patch0246: target-i386-Add-Hygon-Dhyana-v3-CPU-model.patch +Patch0247: target-i386-Add-new-Hygon-Dharma-CPU-model.patch BuildRequires: flex BuildRequires: gcc @@ -856,6 +858,10 @@ getent passwd qemu >/dev/null || \ %endif %changelog +* Wed May 15 2024 Yanjing Zhou - 11:8.2.0-13 +- target/i386: Add Hygon Dhyana-v3 CPU model +- target/i386: Add new Hygon 'Dharma' CPU model + * Thu May 10 2024 zhangxianting - 11:8.2.0-12 - target/i386: Export RFDS bit to guests - target/i386: Add new CPU model SierraForest diff --git a/target-i386-Add-Hygon-Dhyana-v3-CPU-model.patch b/target-i386-Add-Hygon-Dhyana-v3-CPU-model.patch new file mode 100644 index 00000000..3d08b291 --- /dev/null +++ b/target-i386-Add-Hygon-Dhyana-v3-CPU-model.patch @@ -0,0 +1,43 @@ +From 418c2d2dcdeed16ca33c8ad35882e9f02f9f74bf Mon Sep 17 00:00:00 2001 +From: Yanjing Zhou +Date: Wed, 15 May 2024 13:49:19 +0800 +Subject: [PATCH 1/2] target/i386: Add Hygon Dhyana-v3 CPU model + +Add the following feature bits for Dhyana CPU model: +perfctr-core, clzero, xsaveerptr, aes, pclmulqdq, sha-ni + +Disable xsaves feature bit for Erratum 1386 + +Signed-off-by: Yanjing Zhou +--- + target/i386/cpu.c | 14 ++++++++++++++ + 1 file changed, 14 insertions(+) + +diff --git a/target/i386/cpu.c b/target/i386/cpu.c +index fd32c64f9..f4c22f32c 100644 +--- a/target/i386/cpu.c ++++ b/target/i386/cpu.c +@@ -4793,6 +4793,20 @@ static const X86CPUDefinition builtin_x86_defs[] = { + { /* end of list */ } + }, + }, ++ { .version = 3, ++ .props = (PropValue[]) { ++ { "xsaves", "off" }, ++ { "perfctr-core", "on" }, ++ { "clzero", "on" }, ++ { "xsaveerptr", "on" }, ++ { "aes", "on" }, ++ { "pclmulqdq", "on" }, ++ { "sha-ni", "on" }, ++ { "model-id", ++ "Hygon Dhyana-v3 processor" }, ++ { /* end of list */ } ++ }, ++ }, + { /* end of list */ } + } + }, +-- +2.43.0 + diff --git a/target-i386-Add-new-Hygon-Dharma-CPU-model.patch b/target-i386-Add-new-Hygon-Dharma-CPU-model.patch new file mode 100644 index 00000000..d77fec27 --- /dev/null +++ b/target-i386-Add-new-Hygon-Dharma-CPU-model.patch @@ -0,0 +1,133 @@ +From 6a187808fbb91a3dcedd684a7718a349751e421f Mon Sep 17 00:00:00 2001 +From: Yanjing Zhou +Date: Wed, 15 May 2024 13:50:17 +0800 +Subject: [PATCH 2/2] target/i386: Add new Hygon 'Dharma' CPU model + +Add the following feature bits compare to Dhyana CPU model: +stibp, ibrs, umip, ssbd + +Signed-off-by: Yanjing Zhou +--- + target/i386/cpu.c | 99 +++++++++++++++++++++++++++++++++++++++++++++++ + 1 file changed, 99 insertions(+) + +diff --git a/target/i386/cpu.c b/target/i386/cpu.c +index f4c22f32c..711370d9b 100644 +--- a/target/i386/cpu.c ++++ b/target/i386/cpu.c +@@ -2162,6 +2162,56 @@ static const CPUCaches epyc_genoa_cache_info = { + }, + }; + ++static const CPUCaches dharma_cache_info = { ++ .l1d_cache = &(CPUCacheInfo) { ++ .type = DATA_CACHE, ++ .level = 1, ++ .size = 32 * KiB, ++ .line_size = 64, ++ .associativity = 8, ++ .partitions = 1, ++ .sets = 64, ++ .lines_per_tag = 1, ++ .self_init = 1, ++ .no_invd_sharing = true, ++ }, ++ .l1i_cache = &(CPUCacheInfo) { ++ .type = INSTRUCTION_CACHE, ++ .level = 1, ++ .size = 32 * KiB, ++ .line_size = 64, ++ .associativity = 8, ++ .partitions = 1, ++ .sets = 64, ++ .lines_per_tag = 1, ++ .self_init = 1, ++ .no_invd_sharing = true, ++ }, ++ .l2_cache = &(CPUCacheInfo) { ++ .type = UNIFIED_CACHE, ++ .level = 2, ++ .size = 512 * KiB, ++ .line_size = 64, ++ .associativity = 8, ++ .partitions = 1, ++ .sets = 1024, ++ .lines_per_tag = 1, ++ }, ++ .l3_cache = &(CPUCacheInfo) { ++ .type = UNIFIED_CACHE, ++ .level = 3, ++ .size = 16 * MiB, ++ .line_size = 64, ++ .associativity = 16, ++ .partitions = 1, ++ .sets = 16384, ++ .lines_per_tag = 1, ++ .self_init = true, ++ .inclusive = true, ++ .complex_indexing = true, ++ }, ++}; ++ + /* The following VMX features are not supported by KVM and are left out in the + * CPU definitions: + * +@@ -5038,6 +5088,55 @@ static const X86CPUDefinition builtin_x86_defs[] = { + .model_id = "AMD EPYC-Genoa Processor", + .cache_info = &epyc_genoa_cache_info, + }, ++ { ++ .name = "Dharma", ++ .level = 0xd, ++ .vendor = CPUID_VENDOR_HYGON, ++ .family = 24, ++ .model = 4, ++ .stepping = 0, ++ .features[FEAT_1_EDX] = ++ CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | ++ CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | ++ CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | ++ CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | ++ CPUID_VME | CPUID_FP87, ++ .features[FEAT_1_ECX] = ++ CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | ++ CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT | ++ CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | ++ CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | ++ CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, ++ .features[FEAT_8000_0001_EDX] = ++ CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | ++ CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | ++ CPUID_EXT2_SYSCALL, ++ .features[FEAT_8000_0001_ECX] = ++ CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | ++ CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | ++ CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | ++ CPUID_EXT3_TOPOEXT | CPUID_EXT3_PERFCORE, ++ .features[FEAT_8000_0008_EBX] = ++ CPUID_8000_0008_EBX_CLZERO | CPUID_8000_0008_EBX_XSAVEERPTR | ++ CPUID_8000_0008_EBX_IBPB | CPUID_8000_0008_EBX_IBRS | ++ CPUID_8000_0008_EBX_STIBP | CPUID_8000_0008_EBX_AMD_SSBD, ++ .features[FEAT_7_0_EBX] = ++ CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | ++ CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED | ++ CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | ++ CPUID_7_0_EBX_SHA_NI, ++ .features[FEAT_7_0_ECX] = CPUID_7_0_ECX_UMIP, ++ .features[FEAT_XSAVE] = ++ CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | ++ CPUID_XSAVE_XGETBV1, ++ .features[FEAT_6_EAX] = ++ CPUID_6_EAX_ARAT, ++ .features[FEAT_SVM] = ++ CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, ++ .xlevel = 0x8000001E, ++ .model_id = "Hygon Dharma Processor", ++ .cache_info = &dharma_cache_info, ++ }, + }; + + /* +-- +2.43.0 + -- Gitee