From d7e98f6592f442b1785a60a0c776d0c7005e0192 Mon Sep 17 00:00:00 2001 From: Jiabo Feng Date: Sat, 15 Jun 2024 08:53:45 +0800 Subject: [PATCH] =?UTF-8?q?QEMU=20update=20to=20version=208.2.0-14?= =?UTF-8?q?=EF=BC=9B=20-=20target/riscv/cpu.c:=20fix=20Zvkb=20extension=20?= =?UTF-8?q?config=20-=20target/i386:=20Add=20new=20Hygon=20'Dharma'=20CPU?= =?UTF-8?q?=20model=20-=20target/i386:=20Add=20Hygon=20Dhyana-v3=20CPU=20m?= =?UTF-8?q?odel=20-=20ui/gtk:=20Fix=20mouse/motion=20event=20scaling=20iss?= =?UTF-8?q?ue=20with=20GTK=20display=20backend=20-=20hw/ufs:=20Fix=20buffe?= =?UTF-8?q?r=20overflow=20bug=20-=20arm/virt:=20Set=20vcpus=5Fcount=20of?= =?UTF-8?q?=20CPU=20as=201=20to=20compatible=20with=20libvirt=20-=20ppc/pn?= =?UTF-8?q?v:=20I2C=20controller=20is=20not=20user=20creatablei?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Jiabo Feng (cherry picked from commit 0121fec7e16a335753b628b3aba13c64bc7aa593) --- ...us_count-of-CPU-as-1-to-compatible-w.patch | 38 +++++ hw-ufs-Fix-buffer-overflow-bug.patch | 63 +++++++++ ...2C-controller-is-not-user-creatablei.patch | 46 ++++++ qemu.spec | 18 ++- ...t-i386-Add-Hygon-Dhyana-v3-CPU-model.patch | 43 ++++++ ...-i386-Add-new-Hygon-Dharma-CPU-model.patch | 133 ++++++++++++++++++ ...iscv-cpu.c-fix-Zvkb-extension-config.patch | 43 ++++++ ...-motion-event-scaling-issue-with-GTK.patch | 82 +++++++++++ 8 files changed, 465 insertions(+), 1 deletion(-) create mode 100644 arm-virt-Set-vcpus_count-of-CPU-as-1-to-compatible-w.patch create mode 100644 hw-ufs-Fix-buffer-overflow-bug.patch create mode 100644 ppc-pnv-I2C-controller-is-not-user-creatablei.patch create mode 100644 target-i386-Add-Hygon-Dhyana-v3-CPU-model.patch create mode 100644 target-i386-Add-new-Hygon-Dharma-CPU-model.patch create mode 100644 target-riscv-cpu.c-fix-Zvkb-extension-config.patch create mode 100644 ui-gtk-Fix-mouse-motion-event-scaling-issue-with-GTK.patch diff --git a/arm-virt-Set-vcpus_count-of-CPU-as-1-to-compatible-w.patch b/arm-virt-Set-vcpus_count-of-CPU-as-1-to-compatible-w.patch new file mode 100644 index 00000000..76e00a1d --- /dev/null +++ b/arm-virt-Set-vcpus_count-of-CPU-as-1-to-compatible-w.patch @@ -0,0 +1,38 @@ +From 85d1711807bc1ec0118cdc9f7cbf9a6e6b96db76 Mon Sep 17 00:00:00 2001 +From: Keqian Zhu +Date: Thu, 23 May 2024 15:51:35 +0800 +Subject: [PATCH] arm/virt: Set vcpus_count of CPU as 1 to compatible with + libvirt + +If vcpus_count is greater than 1, use libvirt to hotplug vcpu +will fail: "An error occurred, but the cause is unknown". + +Signed-off-by: Keqian Zhu +--- + hw/arm/virt.c | 3 +-- + 1 file changed, 1 insertion(+), 2 deletions(-) + +diff --git a/hw/arm/virt.c b/hw/arm/virt.c +index dfe4d9e129..a6e324c6f8 100644 +--- a/hw/arm/virt.c ++++ b/hw/arm/virt.c +@@ -3064,7 +3064,6 @@ static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms) + { + int n; + unsigned int max_cpus = ms->smp.max_cpus; +- unsigned int smp_threads = ms->smp.threads; + VirtMachineState *vms = VIRT_MACHINE(ms); + MachineClass *mc = MACHINE_GET_CLASS(vms); + +@@ -3078,7 +3077,7 @@ static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms) + ms->possible_cpus->len = max_cpus; + for (n = 0; n < ms->possible_cpus->len; n++) { + ms->possible_cpus->cpus[n].type = ms->cpu_type; +- ms->possible_cpus->cpus[n].vcpus_count = smp_threads; ++ ms->possible_cpus->cpus[n].vcpus_count = 1; + ms->possible_cpus->cpus[n].arch_id = + virt_cpu_mp_affinity(vms, n); + +-- +2.41.0.windows.1 + diff --git a/hw-ufs-Fix-buffer-overflow-bug.patch b/hw-ufs-Fix-buffer-overflow-bug.patch new file mode 100644 index 00000000..b5541170 --- /dev/null +++ b/hw-ufs-Fix-buffer-overflow-bug.patch @@ -0,0 +1,63 @@ +From 73fecb1c0fab9a1e0593b769c36bdc795c9316ae Mon Sep 17 00:00:00 2001 +From: qihao +Date: Wed, 15 May 2024 15:52:28 +0800 +Subject: [PATCH] hw/ufs: Fix buffer overflow bug + +cheery-pick from f2c8aeb1afefcda92054c448b21fc59cdd99db30 + +It fixes the buffer overflow vulnerability in the ufs device. +The bug was detected by sanitizers. + +You can reproduce it by: + +cat << EOF |\ +qemu-system-x86_64 \ +-display none -machine accel=qtest -m 512M -M q35 -nodefaults -drive \ +file=null-co://,if=none,id=disk0 -device ufs,id=ufs_bus -device \ +ufs-lu,drive=disk0,bus=ufs_bus -qtest stdio +outl 0xcf8 0x80000810 +outl 0xcfc 0xe0000000 +outl 0xcf8 0x80000804 +outw 0xcfc 0x06 +write 0xe0000058 0x1 0xa7 +write 0xa 0x1 0x50 +EOF + +Resolves: #2299 +Fixes: 329f16624499 ("hw/ufs: Support for Query Transfer Requests") +Reported-by: Zheyu Ma +Signed-off-by: Jeuk Kim +Signed-off-by: qihao_yewu +--- + hw/ufs/ufs.c | 8 ++++++++ + 1 file changed, 8 insertions(+) + +diff --git a/hw/ufs/ufs.c b/hw/ufs/ufs.c +index eccdb852a0..bac78a32bb 100644 +--- a/hw/ufs/ufs.c ++++ b/hw/ufs/ufs.c +@@ -126,6 +126,10 @@ static MemTxResult ufs_dma_read_req_upiu(UfsRequest *req) + copy_size = sizeof(UtpUpiuHeader) + UFS_TRANSACTION_SPECIFIC_FIELD_SIZE + + data_segment_length; + ++ if (copy_size > sizeof(req->req_upiu)) { ++ copy_size = sizeof(req->req_upiu); ++ } ++ + ret = ufs_addr_read(u, req_upiu_base_addr, &req->req_upiu, copy_size); + if (ret) { + trace_ufs_err_dma_read_req_upiu(req->slot, req_upiu_base_addr); +@@ -225,6 +229,10 @@ static MemTxResult ufs_dma_write_rsp_upiu(UfsRequest *req) + copy_size = rsp_upiu_byte_len; + } + ++ if (copy_size > sizeof(req->rsp_upiu)) { ++ copy_size = sizeof(req->rsp_upiu); ++ } ++ + ret = ufs_addr_write(u, rsp_upiu_base_addr, &req->rsp_upiu, copy_size); + if (ret) { + trace_ufs_err_dma_write_rsp_upiu(req->slot, rsp_upiu_base_addr); +-- +2.41.0.windows.1 + diff --git a/ppc-pnv-I2C-controller-is-not-user-creatablei.patch b/ppc-pnv-I2C-controller-is-not-user-creatablei.patch new file mode 100644 index 00000000..254ef7dc --- /dev/null +++ b/ppc-pnv-I2C-controller-is-not-user-creatablei.patch @@ -0,0 +1,46 @@ +From e2a4aed3ef07b05302ab4d15017b720fec97905f Mon Sep 17 00:00:00 2001 +From: gaojiazhen +Date: Mon, 25 Mar 2024 18:04:40 +0800 +Subject: [PATCH] ppc/pnv: I2C controller is not user creatablei +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +cherry picked from commit 5b2b9450a2f83668bedd092b43233ad35f0d40bd + +The I2C controller is a subunit of the processor. Make it so and avoid +QEMU crashes. + + $ build/qemu-system-ppc64 -S -machine powernv9 -device pnv-i2c + qemu-system-ppc64: ../hw/ppc/pnv_i2c.c:521: pnv_i2c_realize: Assertion `i2c->chip' failed. + Aborted (core dumped) + +Fixes: 263b81e ("ppc/pnv: Add an I2C controller model") +Cc: Glenn Miles +Reported-by: Thomas Huth +Reviewed-by: Thomas Huth +Reviewed-by: Philippe Mathieu-Daudé +Reviewed-by: Glenn Miles +Signed-off-by: Cédric Le Goater +Signed-off-by: Gao Jiazhen +--- + hw/ppc/pnv_i2c.c | 3 +++ + 1 file changed, 3 insertions(+) + +diff --git a/hw/ppc/pnv_i2c.c b/hw/ppc/pnv_i2c.c +index 656a48eebe..0ac6aa5c06 100644 +--- a/hw/ppc/pnv_i2c.c ++++ b/hw/ppc/pnv_i2c.c +@@ -673,6 +673,9 @@ static void pnv_i2c_class_init(ObjectClass *klass, void *data) + + xscomc->dt_xscom = pnv_i2c_dt_xscom; + ++ /* Reason: This device is part of the CPU and cannot be used separately */ ++ dc->user_creatable = false; ++ + dc->desc = "PowerNV I2C"; + dc->realize = pnv_i2c_realize; + device_class_set_props(dc, pnv_i2c_properties); +-- +2.41.0.windows.1 + diff --git a/qemu.spec b/qemu.spec index e1b8fbed..af89b3ad 100644 --- a/qemu.spec +++ b/qemu.spec @@ -3,7 +3,7 @@ Name: qemu Version: 8.2.0 -Release: 13 +Release: 14 Epoch: 11 Summary: QEMU is a generic and open source machine emulator and virtualizer License: GPLv2 and BSD and MIT and CC-BY-SA-4.0 @@ -269,6 +269,13 @@ Patch0252: target-loongarch-kvm-Add-pmu-support.patch Patch0253: target-loongarch-kvm-Fix-vm-restore-failed.patch Patch0254: target-loongarch-kvm-Add-pv-steal-time-support.patch Patch0255: target-loongarch-kvm-fpu-save-the-vreg-registers-hig.patch +Patch0256: ppc-pnv-I2C-controller-is-not-user-creatablei.patch +Patch0257: arm-virt-Set-vcpus_count-of-CPU-as-1-to-compatible-w.patch +Patch0258: hw-ufs-Fix-buffer-overflow-bug.patch +Patch0259: ui-gtk-Fix-mouse-motion-event-scaling-issue-with-GTK.patch +Patch0260: target-i386-Add-Hygon-Dhyana-v3-CPU-model.patch +Patch0261: target-i386-Add-new-Hygon-Dharma-CPU-model.patch +Patch0262: target-riscv-cpu.c-fix-Zvkb-extension-config.patch BuildRequires: flex BuildRequires: gcc @@ -866,6 +873,15 @@ getent passwd qemu >/dev/null || \ %endif %changelog +* Sat Jun 15 2024 Jiabo Feng - 11:8.2.0-14 +- target/riscv/cpu.c: fix Zvkb extension config +- target/i386: Add new Hygon 'Dharma' CPU model +- target/i386: Add Hygon Dhyana-v3 CPU model +- ui/gtk: Fix mouse/motion event scaling issue with GTK display backend +- hw/ufs: Fix buffer overflow bug +- arm/virt: Set vcpus_count of CPU as 1 to compatible with libvirt +- ppc/pnv: I2C controller is not user creatablei + * Mon May 20 2024 Song Gao - 11:8.2.0-13 - target/loongarch: Fix qemu-system-loongarch64 assert - target/loongarch: Fix qemu-loongarch64 hang when executing 'll.d $t0, $t0, 0' diff --git a/target-i386-Add-Hygon-Dhyana-v3-CPU-model.patch b/target-i386-Add-Hygon-Dhyana-v3-CPU-model.patch new file mode 100644 index 00000000..03db2220 --- /dev/null +++ b/target-i386-Add-Hygon-Dhyana-v3-CPU-model.patch @@ -0,0 +1,43 @@ +From 7d4bc795419a69457ee5f2e32674183dc009d48f Mon Sep 17 00:00:00 2001 +From: Yanjing Zhou +Date: Wed, 15 May 2024 13:49:19 +0800 +Subject: [PATCH] target/i386: Add Hygon Dhyana-v3 CPU model + +Add the following feature bits for Dhyana CPU model: +perfctr-core, clzero, xsaveerptr, aes, pclmulqdq, sha-ni + +Disable xsaves feature bit for Erratum 1386 + +Signed-off-by: Yanjing Zhou +--- + target/i386/cpu.c | 14 ++++++++++++++ + 1 file changed, 14 insertions(+) + +diff --git a/target/i386/cpu.c b/target/i386/cpu.c +index fd32c64f99..f4c22f32c6 100644 +--- a/target/i386/cpu.c ++++ b/target/i386/cpu.c +@@ -4793,6 +4793,20 @@ static const X86CPUDefinition builtin_x86_defs[] = { + { /* end of list */ } + }, + }, ++ { .version = 3, ++ .props = (PropValue[]) { ++ { "xsaves", "off" }, ++ { "perfctr-core", "on" }, ++ { "clzero", "on" }, ++ { "xsaveerptr", "on" }, ++ { "aes", "on" }, ++ { "pclmulqdq", "on" }, ++ { "sha-ni", "on" }, ++ { "model-id", ++ "Hygon Dhyana-v3 processor" }, ++ { /* end of list */ } ++ }, ++ }, + { /* end of list */ } + } + }, +-- +2.41.0.windows.1 + diff --git a/target-i386-Add-new-Hygon-Dharma-CPU-model.patch b/target-i386-Add-new-Hygon-Dharma-CPU-model.patch new file mode 100644 index 00000000..b05c4a53 --- /dev/null +++ b/target-i386-Add-new-Hygon-Dharma-CPU-model.patch @@ -0,0 +1,133 @@ +From f4d31d640491c66bb1277e12d3c1d0e7ebc7cae5 Mon Sep 17 00:00:00 2001 +From: Yanjing Zhou +Date: Wed, 15 May 2024 13:50:17 +0800 +Subject: [PATCH] target/i386: Add new Hygon 'Dharma' CPU model + +Add the following feature bits compare to Dhyana CPU model: +stibp, ibrs, umip, ssbd + +Signed-off-by: Yanjing Zhou +--- + target/i386/cpu.c | 99 +++++++++++++++++++++++++++++++++++++++++++++++ + 1 file changed, 99 insertions(+) + +diff --git a/target/i386/cpu.c b/target/i386/cpu.c +index f4c22f32c6..711370d9b8 100644 +--- a/target/i386/cpu.c ++++ b/target/i386/cpu.c +@@ -2162,6 +2162,56 @@ static const CPUCaches epyc_genoa_cache_info = { + }, + }; + ++static const CPUCaches dharma_cache_info = { ++ .l1d_cache = &(CPUCacheInfo) { ++ .type = DATA_CACHE, ++ .level = 1, ++ .size = 32 * KiB, ++ .line_size = 64, ++ .associativity = 8, ++ .partitions = 1, ++ .sets = 64, ++ .lines_per_tag = 1, ++ .self_init = 1, ++ .no_invd_sharing = true, ++ }, ++ .l1i_cache = &(CPUCacheInfo) { ++ .type = INSTRUCTION_CACHE, ++ .level = 1, ++ .size = 32 * KiB, ++ .line_size = 64, ++ .associativity = 8, ++ .partitions = 1, ++ .sets = 64, ++ .lines_per_tag = 1, ++ .self_init = 1, ++ .no_invd_sharing = true, ++ }, ++ .l2_cache = &(CPUCacheInfo) { ++ .type = UNIFIED_CACHE, ++ .level = 2, ++ .size = 512 * KiB, ++ .line_size = 64, ++ .associativity = 8, ++ .partitions = 1, ++ .sets = 1024, ++ .lines_per_tag = 1, ++ }, ++ .l3_cache = &(CPUCacheInfo) { ++ .type = UNIFIED_CACHE, ++ .level = 3, ++ .size = 16 * MiB, ++ .line_size = 64, ++ .associativity = 16, ++ .partitions = 1, ++ .sets = 16384, ++ .lines_per_tag = 1, ++ .self_init = true, ++ .inclusive = true, ++ .complex_indexing = true, ++ }, ++}; ++ + /* The following VMX features are not supported by KVM and are left out in the + * CPU definitions: + * +@@ -5038,6 +5088,55 @@ static const X86CPUDefinition builtin_x86_defs[] = { + .model_id = "AMD EPYC-Genoa Processor", + .cache_info = &epyc_genoa_cache_info, + }, ++ { ++ .name = "Dharma", ++ .level = 0xd, ++ .vendor = CPUID_VENDOR_HYGON, ++ .family = 24, ++ .model = 4, ++ .stepping = 0, ++ .features[FEAT_1_EDX] = ++ CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | ++ CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | ++ CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | ++ CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | ++ CPUID_VME | CPUID_FP87, ++ .features[FEAT_1_ECX] = ++ CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | ++ CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT | ++ CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | ++ CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | ++ CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, ++ .features[FEAT_8000_0001_EDX] = ++ CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | ++ CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | ++ CPUID_EXT2_SYSCALL, ++ .features[FEAT_8000_0001_ECX] = ++ CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | ++ CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | ++ CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | ++ CPUID_EXT3_TOPOEXT | CPUID_EXT3_PERFCORE, ++ .features[FEAT_8000_0008_EBX] = ++ CPUID_8000_0008_EBX_CLZERO | CPUID_8000_0008_EBX_XSAVEERPTR | ++ CPUID_8000_0008_EBX_IBPB | CPUID_8000_0008_EBX_IBRS | ++ CPUID_8000_0008_EBX_STIBP | CPUID_8000_0008_EBX_AMD_SSBD, ++ .features[FEAT_7_0_EBX] = ++ CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | ++ CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED | ++ CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | ++ CPUID_7_0_EBX_SHA_NI, ++ .features[FEAT_7_0_ECX] = CPUID_7_0_ECX_UMIP, ++ .features[FEAT_XSAVE] = ++ CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | ++ CPUID_XSAVE_XGETBV1, ++ .features[FEAT_6_EAX] = ++ CPUID_6_EAX_ARAT, ++ .features[FEAT_SVM] = ++ CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, ++ .xlevel = 0x8000001E, ++ .model_id = "Hygon Dharma Processor", ++ .cache_info = &dharma_cache_info, ++ }, + }; + + /* +-- +2.41.0.windows.1 + diff --git a/target-riscv-cpu.c-fix-Zvkb-extension-config.patch b/target-riscv-cpu.c-fix-Zvkb-extension-config.patch new file mode 100644 index 00000000..3043991c --- /dev/null +++ b/target-riscv-cpu.c-fix-Zvkb-extension-config.patch @@ -0,0 +1,43 @@ +From c7c526af0bb4de631e2e5f1d38518beb8fa5a8a4 Mon Sep 17 00:00:00 2001 +From: qihao +Date: Wed, 5 Jun 2024 15:21:06 +0800 +Subject: [PATCH] target/riscv/cpu.c: fix Zvkb extension config +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +cheery-pick from ff33b7a9699e977a050a1014c617a89da1bf8295 + +This code has a typo that writes zvkb to zvkg, causing users can't +enable zvkb through the config. This patch gets this fixed. + +Signed-off-by: Yangyu Chen +Fixes: ea61ef7097d0 ("target/riscv: Move vector crypto extensions to riscv_cpu_extensions") +Reviewed-by: LIU Zhiwei +Reviewed-by: Alistair Francis +Reviewed-by: Max Chou +Reviewed-by:  Weiwei Li +Message-ID: +Cc: qemu-stable +Signed-off-by: Alistair Francis +Signed-off-by: qihao_yewu +--- + target/riscv/cpu.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c +index 83c7c0cf07..77cb59b8a1 100644 +--- a/target/riscv/cpu.c ++++ b/target/riscv/cpu.c +@@ -1359,7 +1359,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = { + /* Vector cryptography extensions */ + MULTI_EXT_CFG_BOOL("zvbb", ext_zvbb, false), + MULTI_EXT_CFG_BOOL("zvbc", ext_zvbc, false), +- MULTI_EXT_CFG_BOOL("zvkb", ext_zvkg, false), ++ MULTI_EXT_CFG_BOOL("zvkb", ext_zvkb, false), + MULTI_EXT_CFG_BOOL("zvkg", ext_zvkg, false), + MULTI_EXT_CFG_BOOL("zvkned", ext_zvkned, false), + MULTI_EXT_CFG_BOOL("zvknha", ext_zvknha, false), +-- +2.41.0.windows.1 + diff --git a/ui-gtk-Fix-mouse-motion-event-scaling-issue-with-GTK.patch b/ui-gtk-Fix-mouse-motion-event-scaling-issue-with-GTK.patch new file mode 100644 index 00000000..fda092ea --- /dev/null +++ b/ui-gtk-Fix-mouse-motion-event-scaling-issue-with-GTK.patch @@ -0,0 +1,82 @@ +From 2e5fd7f2e6027899e84984bc31f52d4dda3b89ed Mon Sep 17 00:00:00 2001 +From: qihao +Date: Tue, 21 May 2024 14:35:19 +0800 +Subject: [PATCH] ui/gtk: Fix mouse/motion event scaling issue with GTK display + backend +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +cheery-pick from 37e91415018db3656b46cdea8f9e4d47b3ff130d + +Remove gtk_widget_get_scale_factor() usage from the calculation of +the motion events in the GTK backend to make it work correctly on +environments that have `gtk_widget_get_scale_factor() != 1`. + +This scale factor usage had been introduced in the commit f14aab420c and +at that time the window size was used for calculating the things and it +was working correctly. However, in the commit 2f31663ed4 the logic +switched to use the widget size instead of window size and because of +the change the usage of scale factor becomes invalid (since widgets use +`vc->gfx.scale_{x, y}` for scaling). + +Tested on Crostini on ChromeOS (15823.51.0) with an external display. + +Fixes: 2f31663ed4 ("ui/gtk: use widget size for cursor motion event") +Fixes: f14aab420c ("ui: fix incorrect pointer position on highdpi with +gtk") + +Signed-off-by: hikalium +Acked-by: Marc-André Lureau +Message-Id: <20240512111435.30121-3-hikalium@hikalium.com> +Signed-off-by: qihao_yewu +--- + ui/gtk.c | 17 +++++++++++++---- + 1 file changed, 13 insertions(+), 4 deletions(-) + +diff --git a/ui/gtk.c b/ui/gtk.c +index 810d7fc796..1a69f6fc37 100644 +--- a/ui/gtk.c ++++ b/ui/gtk.c +@@ -887,7 +887,7 @@ static gboolean gd_motion_event(GtkWidget *widget, GdkEventMotion *motion, + int x, y; + int mx, my; + int fbh, fbw; +- int ww, wh, ws; ++ int ww, wh; + + if (!vc->gfx.ds) { + return TRUE; +@@ -898,8 +898,13 @@ static gboolean gd_motion_event(GtkWidget *widget, GdkEventMotion *motion, + + ww = gtk_widget_get_allocated_width(widget); + wh = gtk_widget_get_allocated_height(widget); +- ws = gtk_widget_get_scale_factor(widget); + ++ /* ++ * `widget` may not have the same size with the frame buffer. ++ * In such cases, some paddings are needed around the `vc`. ++ * To achieve that, `vc` will be displayed at (mx, my) ++ * so that it is displayed at the center of the widget. ++ */ + mx = my = 0; + if (ww > fbw) { + mx = (ww - fbw) / 2; +@@ -908,8 +913,12 @@ static gboolean gd_motion_event(GtkWidget *widget, GdkEventMotion *motion, + my = (wh - fbh) / 2; + } + +- x = (motion->x - mx) / vc->gfx.scale_x * ws; +- y = (motion->y - my) / vc->gfx.scale_y * ws; ++ /* ++ * `motion` is reported in `widget` coordinates ++ * so translating it to the coordinates in `vc`. ++ */ ++ x = (motion->x - mx) / vc->gfx.scale_x; ++ y = (motion->y - my) / vc->gfx.scale_y; + + if (qemu_input_is_absolute(vc->gfx.dcl.con)) { + if (x < 0 || y < 0 || +-- +2.41.0.windows.1 + -- Gitee