diff --git a/articles/20240828-riscv-plic-spec.md b/articles/20240828-riscv-plic-spec.md new file mode 100644 index 0000000000000000000000000000000000000000..a5429feea8b7e3f6b9f14eafead534cc4f3c7346 --- /dev/null +++ b/articles/20240828-riscv-plic-spec.md @@ -0,0 +1,423 @@ +> Corrector: [TinyCorrect](https://gitee.com/tinylab/tinycorrect) v0.2-rc2 - [autocorrect epw]
+> Title: [RISC-V Platform-Level Interrupt Controller Specification](https://github.com/riscv/riscv-plic-spec/blob/master/riscv-plic.adoc)
+> Author: Abner Chang@**March 12, 2023**
+> Translator: Sunts
+> Date: 2024/08/28
+> Revisor: Falcon
+> Project: [RISC-V Linux 内核剖析](https://gitee.com/tinylab/riscv-linux)
+> Sponsor: PLCT Lab, ISCAS + +# RISC-V 平台级中断控制器规范 + +目录 + +[1. 中断目标和核心上下文](#jump1) + +[2. 中断网关](#jump2) + +[3. 中断通知](#jump3) + +[3. 中断标识符](#jump4) + +[4. 中断流](#jump5) + +[5. RISCV PLIC 运行参数](#jump6) + +## 前言 + +PLIC(Platform-Level Interrupt Controller) 平台级中断控制器主要用于 RISCV 架构下外部中断的控制和处理。PLIC 将各种设备中断复用到 Hart 上下文的外部中断线上，并通过硬件支持中断优先级。PLIC 支持最多 1023 个中断（0 被保留）和 15872 个上下文，但实际的中断和上下文数量取决于 PLIC 的实现。 + + + +## 中断目标和 HART 上下文 + +> We use the term hart to unambiguously and concisely describe a hardware thread as opposed to software-managed thread contexts. + +hart 用于描述硬件线程，与软件管理的线程上下文相对。 + +> Interrupt targets are usually hart contexts, where a hart context is a given privilege mode on a given hart (though there are other possible interrupt targets, such as DMA engines). For example, in an 4-core system with 2-way SMT, you have 8 harts and probably at least two privilege modes per hart: machine mode and supervisor mode (Ref). +> Not all hart contexts need be interrupt targets, in particular, if a processor core does not support delegating external interrupts to lower-privilege modes, then the lower-privilege hart contexts will not be interrupt targets. Interrupt notifications generated by the PLIC appear in the meip/seip bits of the mip/sip registers for M/S modes respectively. + +中断目标通常是 hart 上下文（中断目标还可以是 DMA 引擎等不在本文考虑内），其中 hart 上下文是在给定 hart 上的给定特权模式。例如，在一个 4 核 8 线程计算机中，你有 8 个 hart，每个 hart 可能至少有两种特权模式：机器模式和特权级模式。并非所有 hart 上下文都需要成为中断目标，特别是如果处理器核心不支持将外部中断委托给较低特权模式，则较低特权的 hart 上下文将不会成为中断目标。由 PLIC 生成的中断通知将出现在 M/S 模式的 mip/sip 寄存器的 meip/seip 位中。 + +> Note: Previous versions of this specification indicated that the PLIC supports U-mode interrupts. This text was removed because the privileged architecture does not define U-mode interrupts. If a future privileged architecture specifies U-mode interrupts, this PLIC specification can be straightforwardly extended to support them. + +注：规范目前移除了用户模式中断，因为特权架构并未定义用户模式中断。如果未来的特权架构规定了用户模式中断，那么 PLIC 规范可以很直接地进行扩展以支持这些中断。 + +> The notification only appear in lower-privilege xip registers if external interrupts have been delegated to the lower-privilege modes. +> Each processor core must define a policy on how simultaneous active interrupts are taken by multiple hart contexts on the core. For the simple case of a single stack of hart contexts, one for each supported privileged mode, interrupts for higher-privilege contexts can preempt execution of interrupt handlers for lower-privilege contexts. A multithreaded processor core could run multiple independent interrupt handlers on different hart contexts at the same time. A processor core could also provide hart contexts that are only used for interrupt handling to reduce interrupt service latency, and these might preempt interrupt handlers for other harts on the same core. + +如果外部中断已经被委派给较低特权模式，那么这些中断的通知只会出现在较低特权的扩展中断寄存器（XIP）中。每个处理器核心都必须定义一个策略，说明如何处理核心上多个 hart 上下文同时发生的活动中断。对于简单的单个 hart 上下文堆栈的情况，即为每种支持的特权模式提供一个 hart 上下文，在这种情况下，较高特权模式下的中断可以抢占较低特权模式下中断处理程序的执行。一个多线程的处理器核心可以在不同的 hart 上下文上同时运行多个独立的中断处理程序。处理器核心还可以提供专门用于中断处理的 hart 上下文以降低中断服务延迟，并且这些上下文可能抢占同一核心上其他 hart 的中断处理程序。 + +> The PLIC treats each interrupt target independently and does not take into account any interrupt prioritization scheme used by a component that contains multiple interrupt targets. As a result, the PLIC provides no concept of interrupt preemption or nesting so this must be handled by the cores hosting multiple interrupt target contexts. + +PLIC 独立处理每个中断目标，不会考虑包含多个中断目标的组件所使用的任何中断优先级方案。因此，PLIC 不提供中断抢占或嵌套的概念，因此必须由托管多个中断目标上下文的内核来处理。 + +下图为 RISCV PLIC 中断架构图 + +![RISC-V PLIC 中断架构图](images/riscv_plic_spec/plic.jpg) + + + +## 中断网关 + +> The interrupt gateways are responsible for converting global interrupt signals into a common interrupt request format, and for controlling the flow of interrupt requests to the PLIC core. At most one interrupt request per interrupt source can be pending in the PLIC core at any time, indicated by setting the source’s IP bit. The gateway only forwards a new interrupt request to the PLIC core after receiving notification that the interrupt handler servicing the previous interrupt request from the same source has completed. + +中断网关负责将全局中断信号转换为通用的中断请求格式，并控制流向 PLIC 内核的中断请求。在任何时候，PLIC 内核中的每个中断源最多只能有一个中断请求待处理，通过设置中断源的 IP(Interrupt Pending) 位来显示。网关只有在收到来自同一中断源的上一个中断请求的中断处理程序处理完毕的通知后，才会向 PLIC 内核转发新的中断请求。 + +> If the global interrupt source uses level-sensitive interrupts, the gateway will convert the first assertion of the interrupt level into an interrupt request, but thereafter the gateway will not forward an additional interrupt request until it receives an interrupt completion message. On receiving an interrupt completion message, if the interrupt is level-triggered and the interrupt is still asserted, a new interrupt request will be forwarded to the PLIC core. The gateway does not have the facility to retract an interrupt request once forwarded to the PLIC core. If a level-sensitive interrupt source deasserts the interrupt after the PLIC core accepts the request and before the interrupt is serviced, the interrupt request remains present in the IP bit of the PLIC core and will be serviced by a handler, which will then have to determine that the interrupt device no longer requires service. + +如果全局中断源的中断为水平触发，中断网关会将首次中断电平的激活转换为一个中断请求；但之后，网关不会转发额外的中断请求，直到它接收到一个中断完成消息。在接收到中断完成消息后，如果该中断是水平触发并且中断仍然处于激活状态，则一个新的中断请求会被转发到 PLIC 核心。网关不具备一旦转发至 PLIC 核心后撤销中断请求的功能。如果一个水平触发的中断源在 PLIC 核心接受请求后但在中断被服务前取消了中断信号，那么中断请求仍会存在于 PLIC 核心的 IP 位中，并将由处理程序进行服务，此时处理程序需要确定中断设备实际上不再需要服务。 + +> If the global interrupt source was edge-triggered, the gateway will convert the first matching signal edge into an interrupt request. Depending on the design of the device and the interrupt handler, in between sending an interrupt request and receiving notice of its handler’s completion, the gateway might either ignore additional matching edges or increment a counter of pending interrupts. In either case, the next interrupt request will not be forwarded to the PLIC core until the previous completion message has been received. If the gateway has a pending interrupt counter, the counter will be decremented when the interrupt request is accepted by the PLIC core. Unlike dedicated-wire interrupt signals, message-signalled interrupts (MSIs) are sent over the system interconnect via a message packet that describes which interrupt is being asserted. The message is decoded to select an interrupt gateway, and the relevant gateway then handles the MSI similar to an edge-triggered interrupt. + +如果全局中断源是边沿触发的，网关会将首次匹配的信号边沿转换为一个中断请求。根据设备的设计以及中断处理程序的不同，在发送一个中断请求与接收其处理程序完成的通知之间，网关可能会忽略额外的匹配边沿或者递增一个待处理中断的计数器。在这两种情况下，下一个中断请求都不会被转发到 PLIC 核心，直到先前的完成消息已被接收。如果网关具有一个待处理中断计数器，当中断请求被 PLIC 核心接受时，计数器将会递减。与专用线中断信号不同，消息指示中断（MSIs）是通过系统互联经由一个描述哪个中断正在被激活的消息包发送的。该消息被解码以选择一个中断网关，相关的网关然后像处理边沿触发的中断一样处理 MSI(Message Signaled Interrupt)。 + + +## 中断通知 + +> Each interrupt target has an external interrupt pending (EIP) bit in the PLIC core that indicates that the corresponding target has a pending interrupt waiting for service. The value in EIP can change as a result of changes to state in the PLIC core, brought on by interrupt sources, interrupt targets, or other agents manipulating register values in the PLIC. The value in EIP is communicated to the destination target as an interrupt notification. If the target is a RISC-V hart context, the interrupt notifications arrive on the meip/seip bits depending on the privilege level of the hart context. + +在 PLIC 内核中，每个中断目标都有一个外部中断待处理（EIP）位，该位表示相应目标有一个等待服务的待处理中断。EIP 中的值会因 PLIC 内核中的状态变化而改变，这些变化是由中断源、中断目标或操纵 PLIC 中寄存器值的其他代理引起的。EIP 中的值将作为中断通知传递给目标目标。如果目标是 RISC-V hart 上下文，中断通知会根据 hart 上下文所处的不同模式到达机器模式的 meip 或特权级/监管者模式的 seip 位。 + +> (In simple systems, the interrupt notifications will be simple wires connected to the processor implementing a hart. In more complex platforms, the notifications might be routed as messages across a system interconnect.) + +（在简单的系统中，中断通知将是连接到实现 hart 的处理器的简单线路。而在更复杂的平台上，这些通知可能会作为消息通过系统互联进行路由。） + +> The PLIC hardware only supports multicasting of interrupts, such that all enabled targets will receive interrupt notifications for a given active interrupt. + +PLIC 硬件仅支持中断的多播功能，这意味着所有已启用的目标都会接收到给定活动中断的中断通知。 + +> (Multicasting provides rapid response since the fastest responder claims the interrupt, but can be wasteful in high-interrupt-rate scenarios if multiple harts take a trap for an interrupt that only one can successfully claim. Software can modulate the PLIC IE bits as part of each interrupt handler to provide alternate policies, such as interrupt affinity or round-robin unicasting.) + +多播提供了快速响应的能力，因为最快的响应者可以响应中断，但在高中断率的情况下，如果多个 hart 为一个只能被其中一个成功响应的中断采取陷阱操作，这可能会造成资源浪费。软件可以通过在每个中断处理程序中调节 PLIC 的 IE 位来提供替代策略，比如中断亲和性或轮询单播。 + +> Depending on the platform architecture and the method used to transport interrupt notifications, these might take some time to be received at the targets. The PLIC is guaranteed to eventually deliver all state changes in EIP to all targets, provided there is no intervening activity in the PLIC core. + +根据平台架构和用于传输中断通知的方法，这些通知可能需要一段时间才能被目标接收。只要在 PLIC 核心中没有干预行为，PLIC 保证最终会将 EIP 中的所有状态变化传递给所有目标。 + +> (The value in an interrupt notification is only guaranteed to hold an EIP value that was valid at some point in the past. In particular, a second target can respond and claim an interrupt while a notification to the first target is still in flight, such that when the first target tries to claim the interrupt it finds it has no active interrupts in the PLIC core.) + +（中断通知中的值仅保证持有过去某个时刻有效的 EIP 值。特别是，当第一个目标的中断通知仍在传输途中时，第二个目标可以回复并响应中断，这样当第一个目标尝试响应中断时，它可能会发现 PLIC 核心中没有活动的中断。） + + + +## 中断标识符 + +> Global interrupt sources are assigned small unsigned integer identifiers, beginning at the value 1. An interrupt ID of 0 is reserved to mean “no interrupt”. + +全局中断源被分配了从小整数标识符开始的小的无符号整数，起始值为 1。中断 ID 为 0 被保留，表示“无中断”。 + +> Interrupt identifiers are also used to break ties when two or more interrupt sources have the same assigned priority. Smaller values of interrupt ID take precedence over larger values of interrupt ID. + +中断标识符也被用来解决两个或多个中断源具有相同分配优先级的情况。较小的中断 ID 值比较大的中断 ID 值具有更高的优先级。 + + +## 中断流 + +下图展示了通过 PLIC 处理中断时，各代理之间流动的消息。 +![RISC-V PLIC 中断流](images/riscv_plic_spec/interrupt_flow.jpg) + +> * Global interrupts are sent from their source to an interrupt gateway that processes the interrupt signal from each source + +> * Interrupt gateway then sends a single interrupt request to the PLIC core, which latches these in the core interrupt pending bits (IP). + +> * The PLIC core forwards an interrupt notification to one or more targets if the targets have any pending interrupts enabled, and the priority of the pending interrupts exceeds a per-target threshold. + +> * When the target takes the external interrupt, it sends an interrupt claim request to retrieve the identifier of the highest priority global interrupt source pending for that target from the PLIC core. + +> * PLIC core then clears the corresponding interrupt source pending bit. + +> * After the target has serviced the interrupt, it sends the associated interrupt gateway an interrupt completion message + +> * The interrupt gateway can now forward another interrupt request for the same source to the PLIC. + +* 全局中断从中断源发送到中断网关，由网关处理来自各中断源的中断信号 + +* 然后，中断网关向 PLIC 核发送单个中断请求，PLIC 核将这些请求锁存在内核中断待处理位（IP）中。 + +* 如果一个或多个目标使能了待处理中断，且待处理中断的优先级超过了每个目标的阈值，PLIC 内核就会向这些目标转发中断通知。 + +* 当目标接收到外部中断时，它会发送中断响应请求，以从 PLIC 内核获取该目标待处理的最高优先级全局中断源的标识符。 + +* 然后，PLIC 核清除相应的中断源的中断挂起位。 + +* 目标处理完中断后，会向相关中断网关发送中断完成信息 + +* 现在，中断网关可将同一中断源的另一个中断请求转发给 PLIC。 + + + +## RISCV PLIC 运行参数 + +规范定义了一般 PLIC 运行参数寄存器块，它们分别是 + +> * Interrupt Priorities registers: The interrupt priority for each interrupt source. + +> * Interrupt Pending Bits registers: The interrupt pending status of each interrupt source. + +> * Interrupt Enables registers: The enablement of interrupt source of each context. + +> * Priority Thresholds registers: The interrupt priority threshold of each context. + +> * Interrupt Claim registers: The register to acquire interrupt source ID of each context. + +> * Interrupt Completion registers: The register to send interrupt completion message to the associated gateway. + +* 中断优先级寄存器：记录各中断源的中断优先级 + +* 中断挂起位寄存器：记录各中断源的中断挂起状态 + +* 中断使能寄存器：记录各上下文对各中断源的使能情况 + +* 中断阈值寄存器：记录各上下文使能中断的优先级阈值 + +* 中断响应寄存器：用于各上下文获取中断源的 ID + +* 中断完成寄存器：用于发送中断完成信号到对应中断网关 + +下图为 PLIC 运行参数图 + +![RISC-V PLIC 运行参数](images/riscv_plic_spec/plic_operation_parameter.jpg) + +### 内存映射 + +> The `base address of PLIC Memory Map` is platform implementation-specific. The memory-mapped registers specified in this chapter have a width of 32-bits. The bits are accessed atomically with LW and SW instructions. + +PLIC 内存映射的基地址因具体平台而异。内存映射寄存器的宽度都为 32bit。使用 LW 和 SW 指令可以原子方式访问这些位。 + +#### plic 内存映射 + +> ```c +>base + 0x000000: Reserved (interrupt source 0 does not exist) +>base + 0x000004: Interrupt source 1 priority +>base + 0x000008: Interrupt source 2 priority +>... +>base + 0x000FFC: Interrupt source 1023 priority +>base + 0x001000: Interrupt Pending bit 0-31 +>base + 0x00107C: Interrupt Pending bit 992-1023 +>... +>base + 0x002000: Enable bits for sources 0-31 on context 0 +>base + 0x002004: Enable bits for sources 32-63 on context 0 +>... +>base + 0x00207C: Enable bits for sources 992-1023 on context 0 +>base + 0x002080: Enable bits for sources 0-31 on context 1 +>base + 0x002084: Enable bits for sources 32-63 on context 1 +>... +>base + 0x0020FC: Enable bits for sources 992-1023 on context 1 +>base + 0x002100: Enable bits for sources 0-31 on context 2 +>base + 0x002104: Enable bits for sources 32-63 on context 2 +>... +>base + 0x00217C: Enable bits for sources 992-1023 on context 2 +>... +>base + 0x1F1F80: Enable bits for sources 0-31 on context 15871 +>base + 0x1F1F84: Enable bits for sources 32-63 on context 15871 +>base + 0x1F1FFC: Enable bits for sources 992-1023 on context 15871 +>... +>base + 0x1FFFFC: Reserved +>base + 0x200000: Priority threshold for context 0 +>base + 0x200004: Claim/complete for context 0 +>base + 0x200008: Reserved +>... +>base + 0x200FFC: Reserved +>base + 0x201000: Priority threshold for context 1 +>base + 0x201004: Claim/complete for context 1 +>... +>base + 0x3FFF000: Priority threshold for context 15871 +>base + 0x3FFF004: Claim/complete for context 15871 +>base + 0x3FFF008: Reserved +>... +>base + 0x3FFFFFC: Reserved +> ``` + +### 中断优先级 + +> Interrupt priorities are small unsigned integers, with a platform-specific maximum number of supported levels. The priority value 0 is reserved to mean "never interrupt", and interrupt priority increases with increasing integer values. Each global interrupt source has an associated interrupt priority held in a memory-mapped register. Different interrupt sources need not support the same set of priority values. A valid implementation can hardwire all input priority levels. Interrupt source priority registers should be WARL fields to allow software to determine the number and position of read-write bits in each priority specification, if any. To simplify discovery of supported priority values, each priority register must support any combination of values in the bits that are variable within the register, i.e., if there are two variable bits in the register, all four combinations of values in those bits must operate as valid priority levels. + +中断优先级是小的无符号整数，支持的最大优先级取决于特定平台。优先级值 0 表示 “从不中断”，中断优先级随整数值的增加而增加。每个全局中断源都有一个相关的中断优先级，保存在内存映射寄存器中。不同的中断源无需支持同一组优先级值。硬连线所有输入优先级是一种合法的实现。中断源优先级寄存器应为 WARL 字段，以便软件确定每个优先级规范中读写位的数量和位置。为了简化对支持的优先级值的查找，每个优先级寄存器必须支持寄存器内可变位的任意组合值，即如果寄存器中有两个可变位，则这些位中的所有四个组合值都必须作为有效的优先级级别运行。 + +> If PLIC supports Interrupt Priorities, then each PLIC interrupt source can be assigned a priority by writing to its 32-bit memory-mapped `priority` register. A priority value of 0 is reserved to mean "never interrupt" and effectively disables the interrupt. Priority 1 is the lowest active priority while the maximum level of priority depends on PLIC implementation. Ties between global interrupts of the same priority are broken by the Interrupt ID; interrupts with the lowest ID have the highest effective priority. + +如果 PLIC 支持中断优先级，那么每个 PLIC 中断源都可以通过写入其 32 位内存映射优先级寄存器来分配优先级。优先级值为 0 表示 “从不中断”，并有效禁用中断。优先级 1 是最低的活动优先级，而最高优先级则取决于 PLIC 的实现。具有相同优先级的全局中断之间的联系通过中断 ID 来打破；ID 最低的中断具有最高的有效优先级。 + +> The base address of Interrupt Source Priority block within PLIC Memory Map region is fixed at 0x000000. + +PLIC 内存映射区域内中断源优先级块的基地址固定为 0x000000。 + +| PLIC 寄存器组名 | 功能 | 寄存器组大小 |描述| +|:---:|:---: |:---: |:---:| +| 中断源优先级 | 中断源 #0 - #1023 的优先级 | 1024 * 4 = 4096(0x1000) bytes | 这是一个包含 PLIC 中断源优先级的连续内存块。该内存块共有 1024 个中断源优先级。中断源优先级 #0 被保留，表示不存在。 + +#### PLIC 中断优先级内存映射 + +>``` +>0x000000: Reserved (interrupt source 0 does not exist) +>0x000004: Interrupt source 1 priority +>0x000008: Interrupt source 2 priority +>... +>0x000FFC: Interrupt source 1023 priority +>``` + +### 中断挂起位 + +> The current status of the interrupt source pending bits in the PLIC core can be read from the pending array, organized as 32-bit register. The pending bit for interrupt ID N is stored in bit (N mod 32) of word (N/32). Bit 0 of word 0, which represents the non-existent interrupt source 0, is hardwired to zero. + +PLIC 内核中中断源挂起位的当前状态可从以 32 位寄存器形式组织的待处理数组中读取。中断 ID N 的挂起位存储在字（N/32）的位（N 模 32）中。字 0 的第 0 位代表不存在的中断源 0，被硬连为 0。 + +> A pending bit in the PLIC core can be cleared by setting the associated enable bit then performing a claim. + +PLIC 核中的中断挂起位可通过设置相关的中断使能位然后通过中断响应来清除。 + +> The base address of Interrupt Pending Bits block within PLIC Memory Map region is fixed at 0x001000. + +PLIC 内存映射区域内中断挂起块的基地址固定为 0x001000。 + +| PLIC 寄存器组名 | 功能 | 寄存器组大小 |描述| +|:---:|:---: |:---: |:---:| +| 中断挂起位 | 中断源 #0 - #N 的中断挂起位 | 1024 / 8 = 128 (0x80) bytes | 这是一个包含 PLIC 中断挂起位的连续存储块。每个中断挂起位占用该寄存器块的 1 位。 + +#### PLIC 中断挂起位内存映射 + +>``` +>0x001000: Interrupt Source #0 to #31 Pending Bits +>... +>0x00107C: Interrupt Source #992 to #1023 Pending Bits +>``` + +### 中断使能 + +> Each global interrupt can be enabled by setting the corresponding bit in the `enables` register. The `enables` registers are accessed as a contiguous array of 32-bit registers, packed the same way as the `pending` bits. Bit 0 of enable register 0 represents the non-existent interrupt ID 0 and is hardwired to 0. PLIC has 15872 Interrupt Enable blocks for the contexts. + +可通过设置使能寄存器中的相应位来使能每个全局中断。使能寄存器作为 32 位寄存器的连续数组访问，其组织方式与挂起位相同。使能寄存器 0 的第 0 位代表不存在的中断 ID 0，并硬连接为 0。 + +> How PLIC organizes interrupts for the contexts (Hart and privilege mode) is out of RISC-V PLIC specification scope, however it must be spec-out in vendor’s PLIC specification. + +PLIC 如何为上下文（Hart 和特权模式）组织中断不属于 RISC-V PLIC 规范的范围，但必须在供应商的 PLIC 规范中加以说明。 + +> (A large number of potential IE bits might be hardwired to zero in cases where some interrupt sources can only be routed to a subset of targets. A larger number of bits might be wired to 1 for an embedded device with fixed interrupt routing. Interrupt priorities, thresholds, and hart-internal interrupt masking provide considerable flexibility in ignoring external interrupts even if a global interrupt source is always enabled.) + +（在某些中断源只能路由到部分中断目标，大量潜在的 IE 位可能被硬连线为 0。对于具有固定中断路由的嵌入式设备，可能会有更多位被连接为 1。即使全局中断源始终处于启用状态，中断优先级、阈值和 hart 内部中断屏蔽在忽略外部中断方面也提供了相当大的灵活性）。 + +PLIC 内存映射区域内中断使能块的基地址固定为 0x002000。 + +| PLIC 寄存器组名 | 功能 | 寄存器组大小 |描述| +|:---:|:---: |:---: |:---:| +| 中断使能位 | 15872 个上下文的中断源 #0 - #1023 的中断挂起位 | (1024 / 8) * 15872 = 2031616 (0x1f0000) bytes | 这是一个连续的内存块，包含了 15872 个上下文的 PLIC 中断使能位。每个中断使能位占用该寄存器块中的 1 位，总共包含 15872 个中断使能位块。 + +#### PLIC 中断使能位内存映射 + +>``` +>0x002000: Interrupt Source #0 to #31 Enable Bits on context 0 +>... +>0x00207C: Interrupt Source #992 to #1023 Enable Bits on context 0 +>0x002080: Interrupt Source #0 to #31 Enable Bits on context 1 +>... +>0x0020FC: Interrupt Source #992 to #1023 Enable Bits on context 1 +>0x002100: Interrupt Source #0 to #31 Enable Bits on context 2 +>... +>0x00217C: Interrupt Source #992 to #1023 Enable Bits on context 2 +>0x002180: Interrupt Source #0 to #31 Enable Bits on context 3 +>... +>0x0021FC: Interrupt Source #992 to #1023 Enable Bits on context 3 +>... +>... +>... +>0x1F1F80: Interrupt Source #0 to #31 on context 15871 +>... +>0x1F1FFC: Interrupt Source #992 to #1023 on context 15871 +>``` + +### 中断阈值 + +> PLIC provides context based `threshold register` for the settings of a interrupt priority threshold of each context. The `threshold register` is a WARL field. The PLIC will mask all PLIC interrupts of a priority less than or equal to `threshold`. For example, a `threshold` value of zero permits all interrupts with non-zero priority. + +PLIC 提供基于上下文的阈值寄存器，用于设置每个上下文的中断优先级阈值。阈值寄存器是一个 WARL 字段。PLIC 将屏蔽优先级小于或等于阈值的所有 PLIC 中断。例如，阈值为 0 时，将允许所有优先级不为 0 的中断。 + +优先级阈值寄存器块的基地址位于 4K 对齐位置，起始于偏移量 0x200000 位置。 + +| PLIC 寄存器组名 | 功能 | 寄存器组大小 |描述| +|:---:|:---: |:---: |:---:| +| 优先级阈值 | 15872 个上下文的优先级阈值 | 4096 * 15872 = 65011712 (0x3e00000) bytes | 用于设置每个上下文的中断优先级寄存器 + +#### PLIC 中断优先级阈值内存映射 + +>``` +>0x200000: Priority threshold for context 0 +>0x201000: Priority threshold for context 1 +>0x202000: Priority threshold for context 2 +>0x203000: Priority threshold for context 3 +>... +>... +>... +>0x3FFF000: Priority threshold for context 15871 +>``` + +### 中断响应处理 + +> Sometime after a target receives an interrupt notification, it might decide to service the interrupt. The target sends an interrupt claim message to the PLIC core, which will usually be implemented as a non-idempotent memory-mapped I/O control register read. On receiving a claim message, the PLIC core will atomically determine the ID of the highest-priority pending interrupt for the target and then clear down the corresponding source’s IP bit. The PLIC core will then return the ID to the target. The PLIC core will return an ID of zero, if there were no pending interrupts for the target when the claim was serviced. + +中断目标收到中断通知后，可能会决定为中断提供服务。中断目标向 PLIC 核发送中断响应信息，通常是通过读取非幂等内存映射 I/O 控制寄存器来实现的。收到请求消息后，PLIC 核将以原子方式确定中断目标最高优先级待处理中断的 ID，然后清除相应源的 IP 位。然后，PLIC 核会将 ID 返回给目标。如果在服务请求时目标没有待处理中断，PLIC 内核将返回一个 0 的 ID。 + +> After the highest-priority pending interrupt is claimed by a target and the corresponding IP bit is cleared, other lower-priority pending interrupts might then become visible to the target, and so the PLIC EIP bit might not be cleared after a claim. The interrupt handler can check the local meip/seip/ueip bits before exiting the handler, to allow more efficient service of other interrupts without first restoring the interrupted context and taking another interrupt trap. + +当优先级最高的挂起中断被目标响应并清除相应的 IP 位后，此时其他优先级较低的挂起中断可能对中断目标可见，因此 PLIC EIP 位可能不会在中断响应后被清除。中断处理程序可在退出处理程序前检查本地的 meip/seip/ueip 位，以便更有效地处理其他中断，而无需恢复中断上下文并重新通过中断处理程序陷入另一个中断。 + +> It is always legal for a hart to perform a claim even if the EIP is not set. In particular, a hart could set the threshold value to maximum to disable interrupt notifications and instead poll for active interrupts using periodic claim requests, though a simpler approach to implement polling would be to clear the external interrupt enable in the corresponding xie register for privilege mode x. + +hart 在 EIP 未设置时执行中断响应是合法行为。特别地，hart 可以将中断阈值设置为最大值，以禁用中断通知，进而使用周期性的中断响应请求对活动的有效中断进行轮询。此外，实现轮询的更简单方法是清除特权模式 x 的相应 xie 寄存器中的外部中断使能。 + +> The PLIC can perform an interrupt claim by reading the `claim/complete` register, which returns the ID of the highest priority pending interrupt or zero if there is no pending interrupt. A successful claim will also atomically clear the corresponding pending bit on the interrupt source. The PLIC can perform a claim at any time and the claim operation is not affected by the setting of the priority threshold register. + +PLIC 可通过读取中断响应/完成寄存器来执行中断响应，该寄存器会返回优先级最高的挂起中断的 ID，如果没有挂起中断，则返回 0。成功的中断响应也会原子式地清除中断源上相应的挂起位。PLIC 可在任何时间执行中断响应，且中断响应操作不受优先级阈值寄存器设置的影响。 + +> The Interrupt Claim Process register is context based and is located at (4K alignment + 4) starts from offset 0x200000. + +一个中断响应/完成寄存器作用于一个上下文，位于（4K + 4）对齐地址处，起始于偏移量 0x200000 位置。 + +| PLIC 寄存器组名 | 功能 | 寄存器组大小 |描述| +|:---:|:---: |:---: |:---:| +| 中断响应寄存器 | 15872 个上下文的中断响应过程 | 4096 * 15872 = 65011712 (0x3e00000) bytes | 用于每个上下文读取待服务的中断 ID + +#### PLIC 中断响应处理内存映射 + +>``` +>0x200004: Interrupt Claim Process for context 0 +>0x201004: Interrupt Claim Process for context 1 +>0x202004: Interrupt Claim Process for context 2 +>0x203004: Interrupt Claim Process for context 3 +>... +>... +>... +>0x3FFF004: Interrupt Claim Process for context 15871 +>``` + +### 中断完成 + +> The PLIC signals it has completed executing an interrupt handler by writing the interrupt ID it received from the claim to the claim/complete register. The PLIC does not check whether the completion ID is the same as the last claim ID for that target. If the completion ID does not match an interrupt source that is currently enabled for the target, the completion is silently ignored. + +PLIC 将从响应中接收到的中断 ID 写入中断响应/完成寄存器，以表示已完成中断处理程序的执行。PLIC 不会检查完成 ID 是否与该目标的上一次请求 ID 相同。如果完成 ID 与中断目标当前使能的中断源不匹配，则完成将被静默忽略。 + +> After a handler has completed service of an interrupt, the associated gateway must be sent an interrupt completion message, usually as a write to a non-idempotent memory-mapped I/O control register. The gateway will only forward additional interrupts to the PLIC core after receiving the completion message. + +处理程序完成中断服务后，必须向相关网关发送中断完成信息，通常是写入非幂等内存映射 I/O 控制寄存器。网关只有在收到完成信息后，才会向 PLIC 内核转发其他中断。 + +> The Interrupt Completion registers are context based and located at the same address with Interrupt Claim Process register, which is at (4K alignment + 4) starts from offset 0x200000. + +一个中断完成寄存器作用域一个上下文，与中断响应处理寄存器位于同一地址，即从偏移量 0x200000 开始的（4K + 4）对齐地址。 + +| PLIC 寄存器组名 | 功能 | 寄存器组大小 |描述| +|:---:|:---: |:---: |:---:| +| 中断完成寄存器 | 15872 个上下文的中断完成 | 4096 * 15872 = 65011712 (0x3e00000) bytes | 用于每个上下文写入已经完成的中断 ID + +#### PLIC 中断完成寄存器内存映射 + +>``` +>0x200004: Interrupt Completion for context 0 +>0x201004: Interrupt Completion for context 1 +>0x202004: Interrupt Completion for context 2 +>0x203004: Interrupt Completion for context 3 +>... +>... +>... +>0x3FFF004: Interrupt Completion for context 15871 +>``` diff --git a/articles/images/riscv_plic_spec/interrupt_flow.jpg b/articles/images/riscv_plic_spec/interrupt_flow.jpg new file mode 100644 index 0000000000000000000000000000000000000000..57d070f3bb5818e3a773887854efd9ba8899ff24 Binary files /dev/null and b/articles/images/riscv_plic_spec/interrupt_flow.jpg differ diff --git a/articles/images/riscv_plic_spec/plic.jpg b/articles/images/riscv_plic_spec/plic.jpg new file mode 100644 index 0000000000000000000000000000000000000000..82894df5dc50c7be6fccc735f8cdd1439093331a Binary files /dev/null and b/articles/images/riscv_plic_spec/plic.jpg differ diff --git a/articles/images/riscv_plic_spec/plic_operation_parameter.jpg b/articles/images/riscv_plic_spec/plic_operation_parameter.jpg new file mode 100644 index 0000000000000000000000000000000000000000..545d0d82c5300cbfcc1a82b32ba4712d620289f0 Binary files /dev/null and b/articles/images/riscv_plic_spec/plic_operation_parameter.jpg differ