# FudanVerilogHomework

**Repository Path**: trs3/fudan-verilog-homework

## Basic Information

- **Project Name**: FudanVerilogHomework
- **Description**: Homework of Fudan Programmable Logic Device and HDL Courses
- **Primary Language**: Verilog
- **License**: Not specified
- **Default Branch**: master
- **Homepage**: None
- **GVP Project**: No

## Statistics

- **Stars**: 0
- **Forks**: 0
- **Created**: 2021-11-20
- **Last Updated**: 2021-11-24

## Categories & Tags

**Categories**: Uncategorized

**Tags**: Verilog

## README

No README documentation available for this project.