diff --git a/base_code/bare_metal/download-tool/download_tool.tar.bz2 b/base_code/bare_metal/download-tool/download_tool.tar.bz2
new file mode 100644
index 0000000000000000000000000000000000000000..78ecc63c9a54cc7f81f5be83596a6c7e0010c9e8
Binary files /dev/null and b/base_code/bare_metal/download-tool/download_tool.tar.bz2 differ
diff --git a/base_code/bare_metal/download-tool/tool.tar.bz2 b/base_code/bare_metal/download-tool/tool.tar.bz2
deleted file mode 100644
index 88ea0dae841f39db1bc1021ab402bdbf3166af5a..0000000000000000000000000000000000000000
Binary files a/base_code/bare_metal/download-tool/tool.tar.bz2 and /dev/null differ
diff --git a/base_code/linux_app/beep/c/Makefile b/base_code/linux_app/beep/c/Makefile
index 984a9a3e4c4346d3632a15ac52cc0b52ac0d3e48..cfae174169423b9f4d4ab5fc108879cd36aa211b 100644
--- a/base_code/linux_app/beep/c/Makefile
+++ b/base_code/linux_app/beep/c/Makefile
@@ -51,7 +51,7 @@ clean:
 cleanall:
 	rm -rf build_x86 build_arm
 
-#命令前带“@”,表示不在终端上输出执行的命令
+#命令前带"@",表示不在终端上输出执行的命令
 #这个目标主要是用来调试Makefile时输出一些内容
 check:
 	@echo $(CFLAGS)
diff --git a/base_code/linux_app/beep/c_shell/Makefile b/base_code/linux_app/beep/c_shell/Makefile
index 984a9a3e4c4346d3632a15ac52cc0b52ac0d3e48..cfae174169423b9f4d4ab5fc108879cd36aa211b 100644
--- a/base_code/linux_app/beep/c_shell/Makefile
+++ b/base_code/linux_app/beep/c_shell/Makefile
@@ -51,7 +51,7 @@ clean:
 cleanall:
 	rm -rf build_x86 build_arm
 
-#命令前带“@”,表示不在终端上输出执行的命令
+#命令前带"@",表示不在终端上输出执行的命令
 #这个目标主要是用来调试Makefile时输出一些内容
 check:
 	@echo $(CFLAGS)
diff --git a/base_code/linux_app/file_io/stdio/Makefile b/base_code/linux_app/file_io/stdio/Makefile
index e29cdbad9cb3af27b8e35d1b90e6dd4b8cc9856c..1c43431b9b752b31b7d4027974afdedce7bc66e7 100644
--- a/base_code/linux_app/file_io/stdio/Makefile
+++ b/base_code/linux_app/file_io/stdio/Makefile
@@ -51,7 +51,7 @@ clean:
 cleanall:
 	rm -rf build_x86 build_arm
 
-#命令前带“@”,表示不在终端上输出执行的命令
+#命令前带"@",表示不在终端上输出执行的命令
 #这个目标主要是用来调试Makefile时输出一些内容
 check:
 	@echo $(CFLAGS)
diff --git a/base_code/linux_app/file_io/systemcall/Makefile b/base_code/linux_app/file_io/systemcall/Makefile
index e29cdbad9cb3af27b8e35d1b90e6dd4b8cc9856c..1c43431b9b752b31b7d4027974afdedce7bc66e7 100644
--- a/base_code/linux_app/file_io/systemcall/Makefile
+++ b/base_code/linux_app/file_io/systemcall/Makefile
@@ -51,7 +51,7 @@ clean:
 cleanall:
 	rm -rf build_x86 build_arm
 
-#命令前带“@”,表示不在终端上输出执行的命令
+#命令前带"@",表示不在终端上输出执行的命令
 #这个目标主要是用来调试Makefile时输出一些内容
 check:
 	@echo $(CFLAGS)
diff --git a/base_code/linux_app/i2c/gtxx_detect/Makefile b/base_code/linux_app/i2c/gtxx_detect/Makefile
index e4a7989f3a18ea4eff8ace69621212aa656bc919..d6f203422c1f059d5d4b0641dbb07ecbff6baa92 100644
--- a/base_code/linux_app/i2c/gtxx_detect/Makefile
+++ b/base_code/linux_app/i2c/gtxx_detect/Makefile
@@ -51,7 +51,7 @@ clean:
 cleanall:
 	rm -rf build_x86 build_arm
 
-#命令前带“@”,表示不在终端上输出执行的命令
+#命令前带"@",表示不在终端上输出执行的命令
 #这个目标主要是用来调试Makefile时输出一些内容
 check:
 	@echo $(CFLAGS)
diff --git a/base_code/linux_app/i2c/mpu6050/Makefile b/base_code/linux_app/i2c/mpu6050/Makefile
index 01340e74dd22a4d53ac31ab601625d2bcc9e2e76..636d8e12e703c379f0d0b69c4103f3881f89c530 100644
--- a/base_code/linux_app/i2c/mpu6050/Makefile
+++ b/base_code/linux_app/i2c/mpu6050/Makefile
@@ -51,7 +51,7 @@ clean:
 cleanall:
 	rm -rf build_x86 build_arm
 
-#命令前带“@”,表示不在终端上输出执行的命令
+#命令前带"@",表示不在终端上输出执行的命令
 #这个目标主要是用来调试Makefile时输出一些内容
 check:
 	@echo $(CFLAGS)
diff --git a/base_code/linux_app/i2c/oled/Makefile b/base_code/linux_app/i2c/oled/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..d2fac9a2d26a69711d2011ff0d63c48c8e9a627a
--- /dev/null
+++ b/base_code/linux_app/i2c/oled/Makefile
@@ -0,0 +1,66 @@
+
+#生成可执行文件的名称
+Target = oled_demo
+ARCH ?= x86
+#编译器CC
+#根据传入的参数ARCH，确定使用的编译器
+#默认使用gcc编译器
+#make ARCH=arm 时使用ARM-GCC编译器
+ifeq ($(ARCH), x86)
+	CC = gcc
+else
+	CC = arm-linux-gnueabihf-gcc
+endif
+#存放中间文件的路径
+build_dir = build_$(ARCH)
+#存放源文件的文件夹
+src_dir =  sources
+#存放头文件的文件夹
+inc_dir = includes .
+
+#源文件
+sources = $(foreach dir,$(src_dir),$(wildcard $(dir)/*.c))
+#目标文件（*.o）
+objects = $(patsubst %.c,$(build_dir)/%.o,$(notdir $(sources)))
+#头文件
+includes = $(foreach dir,$(inc_dir),$(wildcard $(dir)/*.h))
+#编译参数
+#指定头文件的路径
+CFLAGS = $(patsubst %, -I%, $(inc_dir))
+
+#链接过程
+#开发板上无法使用动态库，因此使用静态链接的方式
+$(build_dir)/$(Target) : $(objects)  | create_build
+	$(CC) $^ -o $@ 
+
+#编译工程
+#编译src文件夹中的源文件，并将生成的目标文件放在objs文件夹中
+$(build_dir)/%.o : $(src_dir)/%.c $(includes) | create_build
+	$(CC) -c $(CFLAGS) $< -o $@ 
+
+
+#以下为伪目标，调用方式：make 伪目标
+#clean：用于Clean Project
+#check：用于检查某个变量的值
+.PHONY:clean cleanall check create_build
+#按架构删除
+clean:
+	rm -rf $(build_dir)
+
+#全部删除
+cleanall:
+	rm -rf build_x86 build_arm
+
+#命令前带"@",表示不在终端上输出执行的命令
+#这个目标主要是用来调试Makefile时输出一些内容
+check:
+	@echo $(CFLAGS)
+	@echo $(CURDIR)
+	@echo $(src_dir)
+	@echo $(sources)
+	@echo $(objects)
+	
+#创建一个新目录create，用于存放过程文件
+create_build:
+	@mkdir -p $(build_dir)
+
diff --git a/base_code/linux_app/i2c/oled/includes/oled_app.h b/base_code/linux_app/i2c/oled/includes/oled_app.h
new file mode 100644
index 0000000000000000000000000000000000000000..f74a2bd03a7dbdcbf1e1dd3233503df5a3b44c2c
--- /dev/null
+++ b/base_code/linux_app/i2c/oled/includes/oled_app.h
@@ -0,0 +1,30 @@
+
+#ifndef __OLED_APP_H
+#define	__OLED_APP_H
+
+
+
+
+#define I2C_RETRIES                                 0x0701
+#define I2C_TIMEOUT                                 0x0702
+#define I2C_SLAVE                                   0x0703       //IIC从器件的地址设置
+#define I2C_BUS_MODE                                0x0780
+
+#define OLED_COMMEND_ADDR 0x00
+#define OLED_DATA_ADDR 0x40
+#define OLED_ADDRESS 0x3C   //通过调整0R电阻,屏可以0x78和0x7A两个地址 -- 默认0x78  3C  
+
+typedef unsigned char uint8;
+
+
+
+static uint8 oled_i2c_write(int fd, uint8 reg, uint8 val);
+void OLED_Init(void);
+void OLED_Fill(unsigned char fill_Data); //全屏填充
+void OLED_CLS(void);//清屏
+void oled_set_Pos(unsigned char x, unsigned char y); //设置起始点坐标
+void OLED_ShowStr(unsigned char x, unsigned char y, unsigned char ch[], unsigned char TextSize);
+void OLED_ShowCN(unsigned char x, unsigned char y, unsigned char N);
+void OLED_DrawBMP(unsigned char x0,unsigned char y0,unsigned char x1,unsigned char y1,unsigned char BMP[]);
+
+#endif
\ No newline at end of file
diff --git a/base_code/linux_app/i2c/oled/sources/main.c b/base_code/linux_app/i2c/oled/sources/main.c
new file mode 100644
index 0000000000000000000000000000000000000000..0bd58a2f197fdb8f29efd34e64d45799cac86c6e
--- /dev/null
+++ b/base_code/linux_app/i2c/oled/sources/main.c
@@ -0,0 +1,65 @@
+
+/************************************************************/
+//文件名：mpu6050.c
+//功能:测试linux下iic驱动oled显示程序
+//使用说明: (1)
+//          (2)
+//          (3)
+//          (4)
+//作者:pengjie
+//日期:2019-07-03
+
+/************************************************************/
+//包含头文件
+#include <stdio.h>
+#include <stdlib.h>
+#include <unistd.h>
+#include <sys/ioctl.h>
+#include <sys/types.h>
+#include <sys/stat.h>
+#include <fcntl.h>
+#include <sys/select.h>
+#include <sys/time.h>
+#include <errno.h>
+
+#include "oled_app.h"
+
+extern int fd;
+extern const unsigned char BMP1[];
+
+/* 主函数  */
+int main(int argc, char *argv[])
+{
+    int i = 0; //用于循环
+
+    OLED_Init(); //初始化oled
+    usleep(1000 * 100);
+    OLED_Fill(0xff); //全屏填充
+
+    while (1)
+    {
+        OLED_Fill(0xff); //全屏填充
+        sleep(1);
+
+        OLED_CLS(); //清屏
+        sleep(1);
+
+        OLED_ShowStr(0, 3, (unsigned char *)"Wildfire Tech", 1);  //测试6*8字符
+        OLED_ShowStr(0, 4, (unsigned char *)"Hello wildfire", 2); //测试8*16字符
+        sleep(1);
+        OLED_CLS(); //清屏
+
+        for (i = 0; i < 4; i++)
+        {
+            OLED_ShowCN(22 + i * 16, 0, i); //测试显示中文
+        }
+        sleep(1);
+        OLED_CLS(); //清屏
+
+        OLED_DrawBMP(0, 0, 128, 8, (unsigned char *)BMP1); //测试BMP位图显示
+        sleep(1);
+        OLED_CLS(); //清屏
+    }
+
+    close(fd);
+}
diff --git a/base_code/linux_app/i2c/oled/sources/oled_app.c b/base_code/linux_app/i2c/oled/sources/oled_app.c
new file mode 100644
index 0000000000000000000000000000000000000000..333e9b6ebc88914e0f20c4cd888a0dfcf1642c4c
--- /dev/null
+++ b/base_code/linux_app/i2c/oled/sources/oled_app.c
@@ -0,0 +1,322 @@
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <unistd.h>
+#include <sys/ioctl.h>
+#include <sys/types.h>
+#include <sys/stat.h>
+#include <fcntl.h>
+
+
+
+#include "oled_app.h"
+
+
+
+int fd = -1;
+
+/*程序中使用到的点阵 字库*/
+extern const unsigned char F16x16[];
+extern const unsigned char F6x8[][6];
+extern const unsigned char F8X16[];
+extern const unsigned char BMP1[];
+
+
+/* IIC 写函数
+*   参数说明：fd，打开的设备文件句柄。 rg, 命令值。 val，要写入的数据
+*   返回值：  成功，返回0. 失败，返回 -1
+*/
+static uint8 oled_i2c_write(int fd, uint8 reg, uint8 val)
+{
+    int retries;
+    uint8 data[2];
+    int write_error = 0;
+
+    data[0] = reg;
+    data[1] = val;
+    
+    ioctl(fd, I2C_SLAVE, OLED_ADDRESS);
+
+    for (retries = 5; retries; retries--)
+    {
+        if (write(fd, data, 2) == 2)
+        {
+            return 0;
+        }
+        usleep(1000);
+    }
+    return -1;
+}
+
+
+// /* IIC 写函数
+// *   参数说明：fd，打开的设备文件句柄。 rg, 命令值。 val，要写入的数据
+// *   返回值：  成功，返回0. 失败，返回 -1
+// */
+// static uint8 oled_oled_i2c_write_command(int fd, uint8 reg, uint8 val)
+// {
+//     int retries;
+//     uint8 data[2];
+//     int write_error = 0;
+
+//     data[0] = reg;
+//     data[1] = val;
+    
+//     ioctl(fd, I2C_SLAVE, OLED_ADDRESS);
+
+//     for (retries = 5; retries; retries--)
+//     {
+//         if (write(fd, data, 2) == 2)
+//         {
+//             return 0;
+//         }
+//         usleep(1000);
+//     }
+//     return -1;
+// }
+
+
+
+
+
+
+
+
+
+/*  初始化 OLED 
+*   参数说明：fd，打开的设备文件句柄。 rg, 命令值。 val，要写入的数据
+*   返回值：  成功，返回0. 失败，返回 -1
+*/
+
+void OLED_Init(void)
+{
+    fd = open("/dev/i2c-0", O_RDWR); // open file and enable read and  write
+
+    if (fd < 0)
+    {
+        perror("Can't open /dev/i2c-0 \n"); // open i2c dev file fail
+        exit(1);
+    }
+    
+    /*发送 从设备地址， 这里就是 oled的地址*/
+    if (ioctl(fd, I2C_SLAVE, OLED_ADDRESS) < 0)
+    { //set i2c address
+        printf("fail to set i2c device slave address!\n");
+        close(fd);
+    }
+
+
+    oled_i2c_write(fd, OLED_COMMEND_ADDR, 0xAE); //display off
+    oled_i2c_write(fd, OLED_COMMEND_ADDR, 0x20); //Set Memory Addressing Mode
+    oled_i2c_write(fd, OLED_COMMEND_ADDR, 0x10); //00,Horizontal Addressing Mode;01,Vertical Addressing Mode;10,Page Addressing Mode (RESET);11,Invalid
+    oled_i2c_write(fd, OLED_COMMEND_ADDR, 0xb0); //Set Page Start Address for Page Addressing Mode,0-7
+    oled_i2c_write(fd, OLED_COMMEND_ADDR, 0xc8); //Set COM Output Scan Direction
+    oled_i2c_write(fd, OLED_COMMEND_ADDR, 0x00); //---set low column address
+    oled_i2c_write(fd, OLED_COMMEND_ADDR, 0x10); //---set high column address
+    oled_i2c_write(fd, OLED_COMMEND_ADDR, 0x40); //--set start line address
+    oled_i2c_write(fd, OLED_COMMEND_ADDR, 0x81); //--set contrast control register
+    oled_i2c_write(fd, OLED_COMMEND_ADDR, 0xf);  //亮度调节 0x00~0xff
+    oled_i2c_write(fd, OLED_COMMEND_ADDR, 0xa1); //--set segment re-map 0 to 127
+    oled_i2c_write(fd, OLED_COMMEND_ADDR, 0xa6); //--set normal display
+    oled_i2c_write(fd, OLED_COMMEND_ADDR, 0xa8); //--set multiplex ratio(1 to 64)
+    oled_i2c_write(fd, OLED_COMMEND_ADDR, 0x3F); //
+    oled_i2c_write(fd, OLED_COMMEND_ADDR, 0xa4); //0xa4,Output follows RAM content;0xa5,Output ignores RAM content
+    oled_i2c_write(fd, OLED_COMMEND_ADDR, 0xd3); //-set display offset
+    oled_i2c_write(fd, OLED_COMMEND_ADDR, 0x00); //-not offset
+    oled_i2c_write(fd, OLED_COMMEND_ADDR, 0xd5); //--set display clock divide ratio/oscillator frequency
+    oled_i2c_write(fd, OLED_COMMEND_ADDR, 0xf0); //--set divide ratio
+    oled_i2c_write(fd, OLED_COMMEND_ADDR, 0xd9); //--set pre-charge period
+    oled_i2c_write(fd, OLED_COMMEND_ADDR, 0x22); //
+    oled_i2c_write(fd, OLED_COMMEND_ADDR, 0xda); //--set com pins hardware configuration
+    oled_i2c_write(fd, OLED_COMMEND_ADDR, 0x12);
+    oled_i2c_write(fd, OLED_COMMEND_ADDR, 0xdb); //--set vcomh
+    oled_i2c_write(fd, OLED_COMMEND_ADDR, 0x20); //0x20,0.77xVcc
+    oled_i2c_write(fd, OLED_COMMEND_ADDR, 0x8d); //--set DC-DC enable
+    oled_i2c_write(fd, OLED_COMMEND_ADDR, 0x14); //
+    oled_i2c_write(fd, OLED_COMMEND_ADDR, 0xaf); //--turn on oled panel
+}
+
+
+
+/**
+  * @brief  OLED_Fill，填充整个屏幕
+  * @param  fill_Data:要填充的数据
+	* @retval 无
+  */
+void OLED_Fill(unsigned char fill_Data) //全屏填充
+{
+    unsigned char m, n;
+    for (m = 0; m < 8; m++)
+    {
+        oled_i2c_write(fd, OLED_COMMEND_ADDR, 0xb0 + m); //page0-page1
+        oled_i2c_write(fd, OLED_COMMEND_ADDR, 0x00);     //low column start address
+        oled_i2c_write(fd, OLED_COMMEND_ADDR, 0x10);     //high column start address
+
+        for (n = 0; n < 128; n++)
+        {
+            // WriteDat(fill_Data);
+            oled_i2c_write(fd, OLED_DATA_ADDR, fill_Data); //high column start address
+        }
+    }
+}
+
+
+ /**
+  * @brief  OLED_SetPos，设置光标
+  * @param  x,光标x位置  y，光标y位置
+  *					
+  * @retval 无
+  */
+void oled_set_Pos(unsigned char x, unsigned char y) //设置起始点坐标
+{ 
+	oled_i2c_write(fd, OLED_COMMEND_ADDR,0xb0+y);
+	oled_i2c_write(fd, OLED_COMMEND_ADDR,((x&0xf0)>>4)|0x10);
+	oled_i2c_write(fd, OLED_COMMEND_ADDR,(x&0x0f)|0x01);
+}
+
+
+
+ /**
+  * @brief  OLED_CLS，清屏
+  * @param  无
+	* @retval 无
+  */
+void OLED_CLS(void)//清屏
+{
+	OLED_Fill(0x00);
+}
+
+
+ /**
+  * @brief  OLED_ON，将OLED从休眠中唤醒
+  * @param  无
+	* @retval 无
+  */
+void OLED_ON(void)
+{
+	oled_i2c_write(fd, OLED_COMMEND_ADDR,0X8D);  //设置电荷泵
+	oled_i2c_write(fd, OLED_COMMEND_ADDR,0X14);  //开启电荷泵
+	oled_i2c_write(fd, OLED_COMMEND_ADDR,0XAF);  //OLED唤醒
+}
+
+
+ /**
+  * @brief  OLED_OFF，让OLED休眠 -- 休眠模式下,OLED功耗不到10uA
+  * @param  无
+	* @retval 无
+  */
+void OLED_OFF(void)
+{
+	oled_i2c_write(fd, OLED_COMMEND_ADDR,0X8D);  //设置电荷泵
+	oled_i2c_write(fd, OLED_COMMEND_ADDR,0X10);  //关闭电荷泵
+	oled_i2c_write(fd, OLED_COMMEND_ADDR,0XAE);  //OLED休眠
+}
+
+
+
+ /**
+  * @brief  OLED_ShowStr，显示codetab.h中的ASCII字符,有6*8和8*16可选择
+  * @param  x,y : 起始点坐标(x:0~127, y:0~7);
+	*					ch[] :- 要显示的字符串; 
+	*					TextSize : 字符大小(1:6*8 ; 2:8*16)
+	* @retval 无
+  */
+void OLED_ShowStr(unsigned char x, unsigned char y, unsigned char ch[], unsigned char TextSize)
+{
+	unsigned char c = 0,i = 0,j = 0;
+	switch(TextSize)
+	{
+		case 1:
+		{
+			while(ch[j] != '\0')
+			{
+				c = ch[j] - 32;
+				if(x > 126)
+				{
+					x = 0;
+					y++;
+				}
+				oled_set_Pos(x,y);
+				for(i=0;i<6;i++)
+					oled_i2c_write(fd, OLED_DATA_ADDR,F6x8[c][i]);
+				x += 6;
+				j++;
+			}
+		}break;
+		case 2:
+		{
+			while(ch[j] != '\0')
+			{
+				c = ch[j] - 32;
+				if(x > 120)
+				{
+					x = 0;
+					y++;
+				}  
+				oled_set_Pos(x,y);
+				for(i=0;i<8;i++)
+					oled_i2c_write(fd, OLED_DATA_ADDR,F8X16[c*16+i]);
+				oled_set_Pos(x,y+1);
+				for(i=0;i<8;i++)
+					oled_i2c_write(fd, OLED_DATA_ADDR,F8X16[c*16+i+8]);
+				x += 8;
+				j++;
+			}
+		}break;
+	}
+}
+
+
+
+ /**
+  * @brief  OLED_ShowCN，显示codetab.h中的汉字,16*16点阵
+  * @param  x,y: 起始点坐标(x:0~127, y:0~7); 
+	*					N:汉字在codetab.h中的索引
+	* @retval 无
+  */
+void OLED_ShowCN(unsigned char x, unsigned char y, unsigned char N)
+{
+	unsigned char wm=0;
+	unsigned int  adder=32*N;
+	oled_set_Pos(x , y);
+	for(wm = 0;wm < 16;wm++)
+	{
+		oled_i2c_write(fd, OLED_DATA_ADDR,F16x16[adder]);
+		adder += 1;
+	}
+	oled_set_Pos(x,y + 1);
+	for(wm = 0;wm < 16;wm++)
+	{
+	  oled_i2c_write(fd, OLED_DATA_ADDR,F16x16[adder]);
+		adder += 1;
+	}
+}
+
+
+
+
+ /**
+  * @brief  OLED_DrawBMP，显示BMP位图
+  * @param  x0,y0 :起始点坐标(x0:0~127, y0:0~7);
+	*					x1,y1 : 起点对角线(结束点)的坐标(x1:1~128,y1:1~8)
+	* @retval 无
+  */
+void OLED_DrawBMP(unsigned char x0,unsigned char y0,unsigned char x1,unsigned char y1,unsigned char BMP[])
+{
+	unsigned int j=0;
+	unsigned char x,y;
+
+  if(y1%8==0)
+		y = y1/8;
+  else
+		y = y1/8 + 1;
+	for(y=y0;y<y1;y++)
+	{
+		oled_set_Pos(x0,y);
+    for(x=x0;x<x1;x++)
+		{
+			oled_i2c_write(fd, OLED_DATA_ADDR,BMP[j++]);
+		}
+	}
+}
+
diff --git a/base_code/linux_app/i2c/oled/sources/oled_code_table.c b/base_code/linux_app/i2c/oled/sources/oled_code_table.c
new file mode 100644
index 0000000000000000000000000000000000000000..410aa96885ed989564185bb096d06b7634b59517
--- /dev/null
+++ b/base_code/linux_app/i2c/oled/sources/oled_code_table.c
@@ -0,0 +1,304 @@
+/**
+  ******************************************************************************
+
+  * @brief   128*64点阵的OLED显示测试工程，仅适用于SD1306驱动IIC通信方式显示屏
+  ******************************************************************************
+  * @attention  *
+	* 
+	* 1. 128*64点整OLED模块功能演示程序的字表，仅适用heltec.taobao.com所售产品;
+	* 2. 字表由打包资料中的"取字软件"计算得出;
+	* 3. 取字方式 -- 共阴、列行式、逆向输出
+	*
+  *
+  ******************************************************************************
+  */ 
+
+extern const unsigned char F16x16[];
+extern const unsigned char F6x8[][6];
+extern const unsigned char F8X16[];
+extern const unsigned char BMP1[];
+
+/***************************16*16的点阵字体取模方式：共阴——列行式——逆向输出*********/
+const unsigned char F16x16[] =
+
+{	
+	0x00,0xFE,0x92,0x92,0xFE,0x92,0x92,0xFE,0x00,0x42,0x4A,0xD2,0x6A,0x46,0xC0,0x00,
+	0x40,0xC4,0x44,0x44,0x3F,0x24,0x24,0x24,0x00,0x40,0x80,0x7F,0x00,0x01,0x00,0x00,/*"野",0*/
+
+	0x00,0x00,0xC0,0x38,0x00,0x00,0x00,0xFF,0x00,0x00,0x40,0x20,0x18,0x00,0x00,0x00,
+	0x80,0x81,0x40,0x20,0x10,0x0C,0x03,0x00,0x03,0x0C,0x10,0x20,0x40,0x80,0x80,0x00,/*"火",1*/
+
+	0x24,0x24,0xA4,0xFE,0xA3,0x22,0x00,0x22,0xCC,0x00,0x00,0xFF,0x00,0x00,0x00,0x00,
+	0x08,0x06,0x01,0xFF,0x00,0x01,0x04,0x04,0x04,0x04,0x04,0xFF,0x02,0x02,0x02,0x00,/*"科",2*/
+
+	0x10,0x10,0x10,0xFF,0x10,0x90,0x08,0x88,0x88,0x88,0xFF,0x88,0x88,0x88,0x08,0x00,
+	0x04,0x44,0x82,0x7F,0x01,0x80,0x80,0x40,0x43,0x2C,0x10,0x28,0x46,0x81,0x80,0x00/*"技",3*/
+	
+		
+};
+
+
+/************************************6*8的点阵************************************/
+const unsigned char F6x8[][6] =
+{
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00,// sp
+	0x00, 0x00, 0x00, 0x2f, 0x00, 0x00,// !
+	0x00, 0x00, 0x07, 0x00, 0x07, 0x00,// "
+	0x00, 0x14, 0x7f, 0x14, 0x7f, 0x14,// #
+	0x00, 0x24, 0x2a, 0x7f, 0x2a, 0x12,// $
+	0x00, 0x62, 0x64, 0x08, 0x13, 0x23,// %
+	0x00, 0x36, 0x49, 0x55, 0x22, 0x50,// &
+	0x00, 0x00, 0x05, 0x03, 0x00, 0x00,// '
+	0x00, 0x00, 0x1c, 0x22, 0x41, 0x00,// (
+	0x00, 0x00, 0x41, 0x22, 0x1c, 0x00,// )
+	0x00, 0x14, 0x08, 0x3E, 0x08, 0x14,// *
+	0x00, 0x08, 0x08, 0x3E, 0x08, 0x08,// +
+	0x00, 0x00, 0x00, 0xA0, 0x60, 0x00,// ,
+	0x00, 0x08, 0x08, 0x08, 0x08, 0x08,// -
+	0x00, 0x00, 0x60, 0x60, 0x00, 0x00,// .
+	0x00, 0x20, 0x10, 0x08, 0x04, 0x02,// /
+	0x00, 0x3E, 0x51, 0x49, 0x45, 0x3E,// 0
+	0x00, 0x00, 0x42, 0x7F, 0x40, 0x00,// 1
+	0x00, 0x42, 0x61, 0x51, 0x49, 0x46,// 2
+	0x00, 0x21, 0x41, 0x45, 0x4B, 0x31,// 3
+	0x00, 0x18, 0x14, 0x12, 0x7F, 0x10,// 4
+	0x00, 0x27, 0x45, 0x45, 0x45, 0x39,// 5
+	0x00, 0x3C, 0x4A, 0x49, 0x49, 0x30,// 6
+	0x00, 0x01, 0x71, 0x09, 0x05, 0x03,// 7
+	0x00, 0x36, 0x49, 0x49, 0x49, 0x36,// 8
+	0x00, 0x06, 0x49, 0x49, 0x29, 0x1E,// 9
+	0x00, 0x00, 0x36, 0x36, 0x00, 0x00,// :
+	0x00, 0x00, 0x56, 0x36, 0x00, 0x00,// ;
+	0x00, 0x08, 0x14, 0x22, 0x41, 0x00,// <
+	0x00, 0x14, 0x14, 0x14, 0x14, 0x14,// =
+	0x00, 0x00, 0x41, 0x22, 0x14, 0x08,// >
+	0x00, 0x02, 0x01, 0x51, 0x09, 0x06,// ?
+	0x00, 0x32, 0x49, 0x59, 0x51, 0x3E,// @
+	0x00, 0x7C, 0x12, 0x11, 0x12, 0x7C,// A
+	0x00, 0x7F, 0x49, 0x49, 0x49, 0x36,// B
+	0x00, 0x3E, 0x41, 0x41, 0x41, 0x22,// C
+	0x00, 0x7F, 0x41, 0x41, 0x22, 0x1C,// D
+	0x00, 0x7F, 0x49, 0x49, 0x49, 0x41,// E
+	0x00, 0x7F, 0x09, 0x09, 0x09, 0x01,// F
+	0x00, 0x3E, 0x41, 0x49, 0x49, 0x7A,// G
+	0x00, 0x7F, 0x08, 0x08, 0x08, 0x7F,// H
+	0x00, 0x00, 0x41, 0x7F, 0x41, 0x00,// I
+	0x00, 0x20, 0x40, 0x41, 0x3F, 0x01,// J
+	0x00, 0x7F, 0x08, 0x14, 0x22, 0x41,// K
+	0x00, 0x7F, 0x40, 0x40, 0x40, 0x40,// L
+	0x00, 0x7F, 0x02, 0x0C, 0x02, 0x7F,// M
+	0x00, 0x7F, 0x04, 0x08, 0x10, 0x7F,// N
+	0x00, 0x3E, 0x41, 0x41, 0x41, 0x3E,// O
+	0x00, 0x7F, 0x09, 0x09, 0x09, 0x06,// P
+	0x00, 0x3E, 0x41, 0x51, 0x21, 0x5E,// Q
+	0x00, 0x7F, 0x09, 0x19, 0x29, 0x46,// R
+	0x00, 0x46, 0x49, 0x49, 0x49, 0x31,// S
+	0x00, 0x01, 0x01, 0x7F, 0x01, 0x01,// T
+	0x00, 0x3F, 0x40, 0x40, 0x40, 0x3F,// U
+	0x00, 0x1F, 0x20, 0x40, 0x20, 0x1F,// V
+	0x00, 0x3F, 0x40, 0x38, 0x40, 0x3F,// W
+	0x00, 0x63, 0x14, 0x08, 0x14, 0x63,// X
+	0x00, 0x07, 0x08, 0x70, 0x08, 0x07,// Y
+	0x00, 0x61, 0x51, 0x49, 0x45, 0x43,// Z
+	0x00, 0x00, 0x7F, 0x41, 0x41, 0x00,// [
+	0x00, 0x55, 0x2A, 0x55, 0x2A, 0x55,// 55
+	0x00, 0x00, 0x41, 0x41, 0x7F, 0x00,// ]
+	0x00, 0x04, 0x02, 0x01, 0x02, 0x04,// ^
+	0x00, 0x40, 0x40, 0x40, 0x40, 0x40,// _
+	0x00, 0x00, 0x01, 0x02, 0x04, 0x00,// '
+	0x00, 0x20, 0x54, 0x54, 0x54, 0x78,// a
+	0x00, 0x7F, 0x48, 0x44, 0x44, 0x38,// b
+	0x00, 0x38, 0x44, 0x44, 0x44, 0x20,// c
+	0x00, 0x38, 0x44, 0x44, 0x48, 0x7F,// d
+	0x00, 0x38, 0x54, 0x54, 0x54, 0x18,// e
+	0x00, 0x08, 0x7E, 0x09, 0x01, 0x02,// f
+	0x00, 0x18, 0xA4, 0xA4, 0xA4, 0x7C,// g
+	0x00, 0x7F, 0x08, 0x04, 0x04, 0x78,// h
+	0x00, 0x00, 0x44, 0x7D, 0x40, 0x00,// i
+	0x00, 0x40, 0x80, 0x84, 0x7D, 0x00,// j
+	0x00, 0x7F, 0x10, 0x28, 0x44, 0x00,// k
+	0x00, 0x00, 0x41, 0x7F, 0x40, 0x00,// l
+	0x00, 0x7C, 0x04, 0x18, 0x04, 0x78,// m
+	0x00, 0x7C, 0x08, 0x04, 0x04, 0x78,// n
+	0x00, 0x38, 0x44, 0x44, 0x44, 0x38,// o
+	0x00, 0xFC, 0x24, 0x24, 0x24, 0x18,// p
+	0x00, 0x18, 0x24, 0x24, 0x18, 0xFC,// q
+	0x00, 0x7C, 0x08, 0x04, 0x04, 0x08,// r
+	0x00, 0x48, 0x54, 0x54, 0x54, 0x20,// s
+	0x00, 0x04, 0x3F, 0x44, 0x40, 0x20,// t
+	0x00, 0x3C, 0x40, 0x40, 0x20, 0x7C,// u
+	0x00, 0x1C, 0x20, 0x40, 0x20, 0x1C,// v
+	0x00, 0x3C, 0x40, 0x30, 0x40, 0x3C,// w
+	0x00, 0x44, 0x28, 0x10, 0x28, 0x44,// x
+	0x00, 0x1C, 0xA0, 0xA0, 0xA0, 0x7C,// y
+	0x00, 0x44, 0x64, 0x54, 0x4C, 0x44,// z
+	0x14, 0x14, 0x14, 0x14, 0x14, 0x14,// horiz lines
+};
+/****************************************8*16的点阵************************************/
+const unsigned char F8X16[]=	  
+{
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,// 0
+  0x00,0x00,0x00,0xF8,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x33,0x30,0x00,0x00,0x00,//! 1
+  0x00,0x10,0x0C,0x06,0x10,0x0C,0x06,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,//" 2
+  0x40,0xC0,0x78,0x40,0xC0,0x78,0x40,0x00,0x04,0x3F,0x04,0x04,0x3F,0x04,0x04,0x00,//# 3
+  0x00,0x70,0x88,0xFC,0x08,0x30,0x00,0x00,0x00,0x18,0x20,0xFF,0x21,0x1E,0x00,0x00,//$ 4
+  0xF0,0x08,0xF0,0x00,0xE0,0x18,0x00,0x00,0x00,0x21,0x1C,0x03,0x1E,0x21,0x1E,0x00,//% 5
+  0x00,0xF0,0x08,0x88,0x70,0x00,0x00,0x00,0x1E,0x21,0x23,0x24,0x19,0x27,0x21,0x10,//& 6
+  0x10,0x16,0x0E,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,//' 7
+  0x00,0x00,0x00,0xE0,0x18,0x04,0x02,0x00,0x00,0x00,0x00,0x07,0x18,0x20,0x40,0x00,//( 8
+  0x00,0x02,0x04,0x18,0xE0,0x00,0x00,0x00,0x00,0x40,0x20,0x18,0x07,0x00,0x00,0x00,//) 9
+  0x40,0x40,0x80,0xF0,0x80,0x40,0x40,0x00,0x02,0x02,0x01,0x0F,0x01,0x02,0x02,0x00,//* 10
+  0x00,0x00,0x00,0xF0,0x00,0x00,0x00,0x00,0x01,0x01,0x01,0x1F,0x01,0x01,0x01,0x00,//+ 11
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0xB0,0x70,0x00,0x00,0x00,0x00,0x00,//, 12
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x01,0x01,0x01,0x01,0x01,0x01,//- 13
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x30,0x30,0x00,0x00,0x00,0x00,0x00,//. 14
+  0x00,0x00,0x00,0x00,0x80,0x60,0x18,0x04,0x00,0x60,0x18,0x06,0x01,0x00,0x00,0x00,/// 15
+  0x00,0xE0,0x10,0x08,0x08,0x10,0xE0,0x00,0x00,0x0F,0x10,0x20,0x20,0x10,0x0F,0x00,//0 16
+  0x00,0x10,0x10,0xF8,0x00,0x00,0x00,0x00,0x00,0x20,0x20,0x3F,0x20,0x20,0x00,0x00,//1 17
+  0x00,0x70,0x08,0x08,0x08,0x88,0x70,0x00,0x00,0x30,0x28,0x24,0x22,0x21,0x30,0x00,//2 18
+  0x00,0x30,0x08,0x88,0x88,0x48,0x30,0x00,0x00,0x18,0x20,0x20,0x20,0x11,0x0E,0x00,//3 19
+  0x00,0x00,0xC0,0x20,0x10,0xF8,0x00,0x00,0x00,0x07,0x04,0x24,0x24,0x3F,0x24,0x00,//4 20
+  0x00,0xF8,0x08,0x88,0x88,0x08,0x08,0x00,0x00,0x19,0x21,0x20,0x20,0x11,0x0E,0x00,//5 21
+  0x00,0xE0,0x10,0x88,0x88,0x18,0x00,0x00,0x00,0x0F,0x11,0x20,0x20,0x11,0x0E,0x00,//6 22
+  0x00,0x38,0x08,0x08,0xC8,0x38,0x08,0x00,0x00,0x00,0x00,0x3F,0x00,0x00,0x00,0x00,//7 23
+  0x00,0x70,0x88,0x08,0x08,0x88,0x70,0x00,0x00,0x1C,0x22,0x21,0x21,0x22,0x1C,0x00,//8 24
+  0x00,0xE0,0x10,0x08,0x08,0x10,0xE0,0x00,0x00,0x00,0x31,0x22,0x22,0x11,0x0F,0x00,//9 25
+  0x00,0x00,0x00,0xC0,0xC0,0x00,0x00,0x00,0x00,0x00,0x00,0x30,0x30,0x00,0x00,0x00,//: 26
+  0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x60,0x00,0x00,0x00,0x00,//; 27
+  0x00,0x00,0x80,0x40,0x20,0x10,0x08,0x00,0x00,0x01,0x02,0x04,0x08,0x10,0x20,0x00,//< 28
+  0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x00,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x00,//= 29
+  0x00,0x08,0x10,0x20,0x40,0x80,0x00,0x00,0x00,0x20,0x10,0x08,0x04,0x02,0x01,0x00,//> 30
+  0x00,0x70,0x48,0x08,0x08,0x08,0xF0,0x00,0x00,0x00,0x00,0x30,0x36,0x01,0x00,0x00,//? 31
+  0xC0,0x30,0xC8,0x28,0xE8,0x10,0xE0,0x00,0x07,0x18,0x27,0x24,0x23,0x14,0x0B,0x00,//@ 32
+  0x00,0x00,0xC0,0x38,0xE0,0x00,0x00,0x00,0x20,0x3C,0x23,0x02,0x02,0x27,0x38,0x20,//A 33
+  0x08,0xF8,0x88,0x88,0x88,0x70,0x00,0x00,0x20,0x3F,0x20,0x20,0x20,0x11,0x0E,0x00,//B 34
+  0xC0,0x30,0x08,0x08,0x08,0x08,0x38,0x00,0x07,0x18,0x20,0x20,0x20,0x10,0x08,0x00,//C 35
+  0x08,0xF8,0x08,0x08,0x08,0x10,0xE0,0x00,0x20,0x3F,0x20,0x20,0x20,0x10,0x0F,0x00,//D 36
+  0x08,0xF8,0x88,0x88,0xE8,0x08,0x10,0x00,0x20,0x3F,0x20,0x20,0x23,0x20,0x18,0x00,//E 37
+  0x08,0xF8,0x88,0x88,0xE8,0x08,0x10,0x00,0x20,0x3F,0x20,0x00,0x03,0x00,0x00,0x00,//F 38
+  0xC0,0x30,0x08,0x08,0x08,0x38,0x00,0x00,0x07,0x18,0x20,0x20,0x22,0x1E,0x02,0x00,//G 39
+  0x08,0xF8,0x08,0x00,0x00,0x08,0xF8,0x08,0x20,0x3F,0x21,0x01,0x01,0x21,0x3F,0x20,//H 40
+  0x00,0x08,0x08,0xF8,0x08,0x08,0x00,0x00,0x00,0x20,0x20,0x3F,0x20,0x20,0x00,0x00,//I 41
+  0x00,0x00,0x08,0x08,0xF8,0x08,0x08,0x00,0xC0,0x80,0x80,0x80,0x7F,0x00,0x00,0x00,//J 42
+  0x08,0xF8,0x88,0xC0,0x28,0x18,0x08,0x00,0x20,0x3F,0x20,0x01,0x26,0x38,0x20,0x00,//K 43
+  0x08,0xF8,0x08,0x00,0x00,0x00,0x00,0x00,0x20,0x3F,0x20,0x20,0x20,0x20,0x30,0x00,//L 44
+  0x08,0xF8,0xF8,0x00,0xF8,0xF8,0x08,0x00,0x20,0x3F,0x00,0x3F,0x00,0x3F,0x20,0x00,//M 45
+  0x08,0xF8,0x30,0xC0,0x00,0x08,0xF8,0x08,0x20,0x3F,0x20,0x00,0x07,0x18,0x3F,0x00,//N 46
+  0xE0,0x10,0x08,0x08,0x08,0x10,0xE0,0x00,0x0F,0x10,0x20,0x20,0x20,0x10,0x0F,0x00,//O 47
+  0x08,0xF8,0x08,0x08,0x08,0x08,0xF0,0x00,0x20,0x3F,0x21,0x01,0x01,0x01,0x00,0x00,//P 48
+  0xE0,0x10,0x08,0x08,0x08,0x10,0xE0,0x00,0x0F,0x18,0x24,0x24,0x38,0x50,0x4F,0x00,//Q 49
+  0x08,0xF8,0x88,0x88,0x88,0x88,0x70,0x00,0x20,0x3F,0x20,0x00,0x03,0x0C,0x30,0x20,//R 50
+  0x00,0x70,0x88,0x08,0x08,0x08,0x38,0x00,0x00,0x38,0x20,0x21,0x21,0x22,0x1C,0x00,//S 51
+  0x18,0x08,0x08,0xF8,0x08,0x08,0x18,0x00,0x00,0x00,0x20,0x3F,0x20,0x00,0x00,0x00,//T 52
+  0x08,0xF8,0x08,0x00,0x00,0x08,0xF8,0x08,0x00,0x1F,0x20,0x20,0x20,0x20,0x1F,0x00,//U 53
+  0x08,0x78,0x88,0x00,0x00,0xC8,0x38,0x08,0x00,0x00,0x07,0x38,0x0E,0x01,0x00,0x00,//V 54
+  0xF8,0x08,0x00,0xF8,0x00,0x08,0xF8,0x00,0x03,0x3C,0x07,0x00,0x07,0x3C,0x03,0x00,//W 55
+  0x08,0x18,0x68,0x80,0x80,0x68,0x18,0x08,0x20,0x30,0x2C,0x03,0x03,0x2C,0x30,0x20,//X 56
+  0x08,0x38,0xC8,0x00,0xC8,0x38,0x08,0x00,0x00,0x00,0x20,0x3F,0x20,0x00,0x00,0x00,//Y 57
+  0x10,0x08,0x08,0x08,0xC8,0x38,0x08,0x00,0x20,0x38,0x26,0x21,0x20,0x20,0x18,0x00,//Z 58
+  0x00,0x00,0x00,0xFE,0x02,0x02,0x02,0x00,0x00,0x00,0x00,0x7F,0x40,0x40,0x40,0x00,//[ 59
+  0x00,0x0C,0x30,0xC0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x06,0x38,0xC0,0x00,//\ 60
+  0x00,0x02,0x02,0x02,0xFE,0x00,0x00,0x00,0x00,0x40,0x40,0x40,0x7F,0x00,0x00,0x00,//] 61
+  0x00,0x00,0x04,0x02,0x02,0x02,0x04,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,//^ 62
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,//_ 63
+  0x00,0x02,0x02,0x04,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,//` 64
+  0x00,0x00,0x80,0x80,0x80,0x80,0x00,0x00,0x00,0x19,0x24,0x22,0x22,0x22,0x3F,0x20,//a 65
+  0x08,0xF8,0x00,0x80,0x80,0x00,0x00,0x00,0x00,0x3F,0x11,0x20,0x20,0x11,0x0E,0x00,//b 66
+  0x00,0x00,0x00,0x80,0x80,0x80,0x00,0x00,0x00,0x0E,0x11,0x20,0x20,0x20,0x11,0x00,//c 67
+  0x00,0x00,0x00,0x80,0x80,0x88,0xF8,0x00,0x00,0x0E,0x11,0x20,0x20,0x10,0x3F,0x20,//d 68
+  0x00,0x00,0x80,0x80,0x80,0x80,0x00,0x00,0x00,0x1F,0x22,0x22,0x22,0x22,0x13,0x00,//e 69
+  0x00,0x80,0x80,0xF0,0x88,0x88,0x88,0x18,0x00,0x20,0x20,0x3F,0x20,0x20,0x00,0x00,//f 70
+  0x00,0x00,0x80,0x80,0x80,0x80,0x80,0x00,0x00,0x6B,0x94,0x94,0x94,0x93,0x60,0x00,//g 71
+  0x08,0xF8,0x00,0x80,0x80,0x80,0x00,0x00,0x20,0x3F,0x21,0x00,0x00,0x20,0x3F,0x20,//h 72
+  0x00,0x80,0x98,0x98,0x00,0x00,0x00,0x00,0x00,0x20,0x20,0x3F,0x20,0x20,0x00,0x00,//i 73
+  0x00,0x00,0x00,0x80,0x98,0x98,0x00,0x00,0x00,0xC0,0x80,0x80,0x80,0x7F,0x00,0x00,//j 74
+  0x08,0xF8,0x00,0x00,0x80,0x80,0x80,0x00,0x20,0x3F,0x24,0x02,0x2D,0x30,0x20,0x00,//k 75
+  0x00,0x08,0x08,0xF8,0x00,0x00,0x00,0x00,0x00,0x20,0x20,0x3F,0x20,0x20,0x00,0x00,//l 76
+  0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x00,0x20,0x3F,0x20,0x00,0x3F,0x20,0x00,0x3F,//m 77
+  0x80,0x80,0x00,0x80,0x80,0x80,0x00,0x00,0x20,0x3F,0x21,0x00,0x00,0x20,0x3F,0x20,//n 78
+  0x00,0x00,0x80,0x80,0x80,0x80,0x00,0x00,0x00,0x1F,0x20,0x20,0x20,0x20,0x1F,0x00,//o 79
+  0x80,0x80,0x00,0x80,0x80,0x00,0x00,0x00,0x80,0xFF,0xA1,0x20,0x20,0x11,0x0E,0x00,//p 80
+  0x00,0x00,0x00,0x80,0x80,0x80,0x80,0x00,0x00,0x0E,0x11,0x20,0x20,0xA0,0xFF,0x80,//q 81
+  0x80,0x80,0x80,0x00,0x80,0x80,0x80,0x00,0x20,0x20,0x3F,0x21,0x20,0x00,0x01,0x00,//r 82
+  0x00,0x00,0x80,0x80,0x80,0x80,0x80,0x00,0x00,0x33,0x24,0x24,0x24,0x24,0x19,0x00,//s 83
+  0x00,0x80,0x80,0xE0,0x80,0x80,0x00,0x00,0x00,0x00,0x00,0x1F,0x20,0x20,0x00,0x00,//t 84
+  0x80,0x80,0x00,0x00,0x00,0x80,0x80,0x00,0x00,0x1F,0x20,0x20,0x20,0x10,0x3F,0x20,//u 85
+  0x80,0x80,0x80,0x00,0x00,0x80,0x80,0x80,0x00,0x01,0x0E,0x30,0x08,0x06,0x01,0x00,//v 86
+  0x80,0x80,0x00,0x80,0x00,0x80,0x80,0x80,0x0F,0x30,0x0C,0x03,0x0C,0x30,0x0F,0x00,//w 87
+  0x00,0x80,0x80,0x00,0x80,0x80,0x80,0x00,0x00,0x20,0x31,0x2E,0x0E,0x31,0x20,0x00,//x 88
+  0x80,0x80,0x80,0x00,0x00,0x80,0x80,0x80,0x80,0x81,0x8E,0x70,0x18,0x06,0x01,0x00,//y 89
+  0x00,0x80,0x80,0x80,0x80,0x80,0x80,0x00,0x00,0x21,0x30,0x2C,0x22,0x21,0x30,0x00,//z 90
+  0x00,0x00,0x00,0x00,0x80,0x7C,0x02,0x02,0x00,0x00,0x00,0x00,0x00,0x3F,0x40,0x40,//{ 91
+  0x00,0x00,0x00,0x00,0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0x00,0x00,0x00,//| 92
+  0x00,0x02,0x02,0x7C,0x80,0x00,0x00,0x00,0x00,0x40,0x40,0x3F,0x00,0x00,0x00,0x00,//} 93
+  0x00,0x06,0x01,0x01,0x02,0x02,0x04,0x04,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,//~ 94
+};
+
+const unsigned char BMP1[] =
+{
+	0x00,0x03,0x05,0x09,0x11,0xFF,0x11,0x89,0x05,0xC3,0x00,0xE0,0x00,0xF0,0x00,0xF8,
+	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x44,0x28,0xFF,0x11,0xAA,0x44,0x00,0x00,0x00,
+	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x83,0x01,0x38,0x44,0x82,0x92,
+	0x92,0x74,0x01,0x83,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x7C,0x44,0xC7,0x01,0x7D,
+	0x7D,0x7D,0x7D,0x01,0x7D,0x7D,0x7D,0x7D,0x01,0x7D,0x7D,0x7D,0x7D,0x01,0xFF,0x00,
+	0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x01,0x00,0x01,0x00,0x01,0x00,0x01,0x00,0x01,
+	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x01,0x00,0x00,0x00,0x00,0x00,
+	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x01,0x00,0x00,0x00,0x00,
+	0x00,0x00,0x01,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x01,0x01,
+	0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x00,
+	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x40,0x40,0x40,0x40,0x00,0x00,
+	0x6D,0x6D,0x6D,0x6D,0x6D,0x00,0x00,0x60,0x60,0x60,0x60,0x60,0x00,0x00,0x40,0x40,
+	0x40,0x40,0x40,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xDB,0xDB,0xDB,0xDB,0xDB,0x00,0x00,
+	0xDB,0xDB,0xDB,0xDB,0xDB,0x00,0x00,0xDB,0xDB,0xDB,0xDB,0xDB,0x00,0x00,0xDB,0xDB,
+	0xDB,0xDB,0xDB,0x00,0x00,0xDA,0xDA,0xDA,0xDA,0xDA,0x00,0x00,0xD8,0xD8,0xD8,0xD8,
+	0xD8,0x00,0x00,0xC0,0xC0,0xC0,0xC0,0xC0,0x00,0x00,0xC0,0xC0,0xC0,0xC0,0xC0,0x00,
+	0x00,0xC0,0xC0,0xC0,0xC0,0xC0,0x00,0x00,0xC0,0xC0,0xC0,0xC0,0xC0,0x00,0x00,0x80,
+	0x80,0x80,0x80,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x06,0x06,0x06,0x06,0x06,0x00,0x00,
+	0x06,0x06,0x06,0x06,0x06,0x00,0x00,0x06,0x06,0x06,0x06,0x06,0x00,0x00,0x06,0x06,
+	0x06,0x06,0x06,0x00,0x00,0x06,0x06,0x06,0xE6,0x66,0x20,0x00,0x06,0x06,0x86,0x06,
+	0x06,0x00,0x00,0x06,0x06,0x06,0x06,0x86,0x00,0x00,0x06,0x06,0x06,0x06,0x06,0x00,
+	0x00,0x86,0x86,0x86,0x86,0x86,0x80,0x80,0x86,0x86,0x06,0x86,0x86,0xC0,0xC0,0x86,
+	0x86,0x86,0x06,0x06,0xD0,0x30,0x76,0x06,0x06,0x06,0x06,0x00,0x00,0x06,0x06,0x06,
+	0x06,0x06,0x00,0x00,0x06,0x06,0x06,0x06,0x06,0x00,0x00,0x06,0x06,0x06,0x06,0x06,
+	0x00,0x00,0x06,0x06,0x06,0x06,0x06,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x60,0x1C,0x00,0xFE,0x00,0x01,
+	0x02,0x00,0xC4,0x18,0x20,0x02,0x9E,0x63,0xB2,0x0E,0x00,0xFF,0x81,0x81,0xFF,0x00,
+	0x00,0x80,0x40,0x30,0x0F,0x00,0x00,0x00,0x00,0xFF,0x00,0x23,0xEA,0xAA,0xBF,0xAA,
+	0xEA,0x03,0x3F,0x00,0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x00,0x00,0x00,0x80,0x80,0x80,0x00,0x00,0x00,0x00,0x00,0x80,0x80,0x80,0x00,0x00,
+	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x0E,0x0C,0x08,0x00,0x00,0x01,0x01,0x01,
+	0x01,0x01,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x01,0x00,0x81,0x80,0x80,0x81,0x80,
+	0x81,0x80,0x80,0x80,0x80,0x01,0x01,0x01,0x01,0x00,0x00,0x00,0x01,0x00,0x00,0x00,
+	0x01,0x00,0x01,0x01,0x09,0x0C,0x0E,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xC0,0xC0,0xC0,0xC0,0xC0,0xC0,0xC0,0xC0,
+	0xC0,0xC0,0xC0,0xC0,0xC0,0xC0,0xC0,0xC0,0xC0,0xC0,0xC0,0xC0,0xC0,0xC0,0xC0,0x00,
+	0x00,0x1E,0x21,0x40,0x40,0x50,0x21,0x5E,0x00,0x1E,0x21,0x40,0x40,0x50,0x21,0x5E,
+	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0xFF,0xC1,0xC1,0xFF,
+	0xFF,0xC1,0xC1,0xFF,0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0xFF,0x80,0xFC,0xF3,0xEF,0xF3,0xFC,
+	0x80,0xFF,0x80,0xEE,0xEE,0xEE,0xF5,0xFB,0xFF,0x9C,0xBE,0xB6,0xB6,0x88,0xFF,0x00,/*"D:\DreamSpark\OLED\MP3_UI.bmp",0*/
+};
+
diff --git a/base_code/linux_app/input/README.md b/base_code/linux_app/input/README.md
index 770d7433f23e979bb06158e9797d8ed2967b2e35..ac07141c099c842cb1eba244048560c35800bf72 100644
--- a/base_code/linux_app/input/README.md
+++ b/base_code/linux_app/input/README.md
@@ -48,8 +48,8 @@ sudo evtest
 #/dev/input/event5:	VirtualBox USB Tablet
 #/dev/input/event6:	VirtualBox mouse integration
 
-#示例中的“VirtualBox mouse integration”为鼠标设备，它的路径为“/dev/input/event6”,
-#把“/dev/input/event6”作为本程序的输入参数运行即可，运行后移动鼠标即会有输出。
+#示例中的"VirtualBox mouse integration"为鼠标设备，它的路径为"/dev/input/event6",
+#把"/dev/input/event6"作为本程序的输入参数运行即可，运行后移动鼠标即会有输出。
 
 #如：  sudo ./build_x86/input_demo  /dev/input/event6
 ```
diff --git a/base_code/linux_app/input/c/Makefile b/base_code/linux_app/input/c/Makefile
index 691948a320e3904d54af3eda0505262b5af3001a..932b0257adaa80c55345a6105fb02c1de30168b5 100644
--- a/base_code/linux_app/input/c/Makefile
+++ b/base_code/linux_app/input/c/Makefile
@@ -51,7 +51,7 @@ clean:
 cleanall:
 	rm -rf build_x86 build_arm
 
-#命令前带“@”,表示不在终端上输出执行的命令
+#命令前带"@",表示不在终端上输出执行的命令
 #这个目标主要是用来调试Makefile时输出一些内容
 check:
 	@echo $(CFLAGS)
diff --git a/base_code/linux_app/input/c/sources/main.c b/base_code/linux_app/input/c/sources/main.c
index e925b3dd8337058b1a368266b2c92b31e03b0814..7916359d8d2a084615e1db67b8f8ebaaece00cbb 100644
--- a/base_code/linux_app/input/c/sources/main.c
+++ b/base_code/linux_app/input/c/sources/main.c
@@ -12,7 +12,7 @@
 const char default_path[] = "/dev/input/by-path/platform-gpio-keys-event";
 
 //开发板上的ON_OFF按键，请根据实际情况修改
-//const char default_path[] = "/dev/input/by-path/platform-20cc000.snvs:snvs-powerkey-event";
+//const char default_path[] = "/dev/input/by-path/platform-ci_hdrc.1-usb-0:1.1:1.0-event-mouse";
 
 
 int main(int argc, char *argv[])
diff --git a/base_code/linux_app/led/sys_class_gpio_export/c_systemcall/Makefile b/base_code/linux_app/led/sys_class_gpio_export/c_systemcall/Makefile
index 8ac0f2d95ed3a053ddbf99ca86b4b7721a20983a..c6f75a4c03b2d7ee97a742c73d4c9190caf5f5ca 100644
--- a/base_code/linux_app/led/sys_class_gpio_export/c_systemcall/Makefile
+++ b/base_code/linux_app/led/sys_class_gpio_export/c_systemcall/Makefile
@@ -51,7 +51,7 @@ clean:
 cleanall:
 	rm -rf build_x86 build_arm
 
-#命令前带“@”,表示不在终端上输出执行的命令
+#命令前带"@",表示不在终端上输出执行的命令
 #这个目标主要是用来调试Makefile时输出一些内容
 check:
 	@echo $(CFLAGS)
diff --git a/base_code/linux_app/led/sys_class_gpio_export/c_systemcall/README.md b/base_code/linux_app/led/sys_class_gpio_export/c_systemcall/README.md
index a99a6bd0d569d8c560a6bd95f4e1b0e3fc645d8b..cee63806ddea13089d6a1193cf17a48b96dbcf36 100644
--- a/base_code/linux_app/led/sys_class_gpio_export/c_systemcall/README.md
+++ b/base_code/linux_app/led/sys_class_gpio_export/c_systemcall/README.md
@@ -29,7 +29,7 @@
     <span>cp led_demo ***</span>
     + 确保板子已经挂载上了nfs文件系统，切换到挂载的目录，执行以下命令<br>
     <span>./led_demo</span><br>
-3. 若操作无误的话，我们可以看到板子的LED灯，轮流显示 “红绿蓝黄紫青白” 的颜色
+3. 若操作无误的话，我们可以看到板子的LED灯，轮流显示 "红绿蓝黄紫青白" 的颜色
 ---
 # 补充说明
 若想要执行Clean Project的操作，可以使用以下命令：<span>./run.sh clc</span>
\ No newline at end of file
diff --git a/base_code/linux_app/led/sys_class_leds/c_shell/Makefile b/base_code/linux_app/led/sys_class_leds/c_shell/Makefile
index 7b6f35d9f77c10f61060128272147f39c7fc56a0..6525ff7d72172df9c5e656e4503b0b0788e17a8b 100644
--- a/base_code/linux_app/led/sys_class_leds/c_shell/Makefile
+++ b/base_code/linux_app/led/sys_class_leds/c_shell/Makefile
@@ -51,7 +51,7 @@ clean:
 cleanall:
 	rm -rf build_x86 build_arm
 
-#命令前带“@”,表示不在终端上输出执行的命令
+#命令前带"@",表示不在终端上输出执行的命令
 #这个目标主要是用来调试Makefile时输出一些内容
 check:
 	@echo $(CFLAGS)
diff --git a/base_code/linux_app/led/sys_class_leds/c_stdio/Makefile b/base_code/linux_app/led/sys_class_leds/c_stdio/Makefile
index 7b6f35d9f77c10f61060128272147f39c7fc56a0..6525ff7d72172df9c5e656e4503b0b0788e17a8b 100644
--- a/base_code/linux_app/led/sys_class_leds/c_stdio/Makefile
+++ b/base_code/linux_app/led/sys_class_leds/c_stdio/Makefile
@@ -51,7 +51,7 @@ clean:
 cleanall:
 	rm -rf build_x86 build_arm
 
-#命令前带“@”,表示不在终端上输出执行的命令
+#命令前带"@",表示不在终端上输出执行的命令
 #这个目标主要是用来调试Makefile时输出一些内容
 check:
 	@echo $(CFLAGS)
diff --git a/base_code/linux_app/led/sys_class_leds/c_systemcall/Makefile b/base_code/linux_app/led/sys_class_leds/c_systemcall/Makefile
index 7b6f35d9f77c10f61060128272147f39c7fc56a0..6525ff7d72172df9c5e656e4503b0b0788e17a8b 100644
--- a/base_code/linux_app/led/sys_class_leds/c_systemcall/Makefile
+++ b/base_code/linux_app/led/sys_class_leds/c_systemcall/Makefile
@@ -51,7 +51,7 @@ clean:
 cleanall:
 	rm -rf build_x86 build_arm
 
-#命令前带“@”,表示不在终端上输出执行的命令
+#命令前带"@",表示不在终端上输出执行的命令
 #这个目标主要是用来调试Makefile时输出一些内容
 check:
 	@echo $(CFLAGS)
diff --git a/base_code/linux_app/makefile_step/README.md b/base_code/linux_app/makefile_step/README.md
index b81b20d7581aba41e0f3471a8db519b2eb991462..f3ca85b212460f252d8613dd3f01267ceaa903ca 100644
--- a/base_code/linux_app/makefile_step/README.md
+++ b/base_code/linux_app/makefile_step/README.md
@@ -14,7 +14,7 @@
 #在主机上Makefile所在的目录执行如下命令
 #查看当前目录的内容
 ls
-#执行make命令，make会在当前目录下搜索“Makefile”或“makefile”，并执行
+#执行make命令，make会在当前目录下搜索"Makefile"或"makefile"，并执行
 make
 #可看到make命令后的输出，它执行了Makefile中编写的命令
 #查看执行make命令后的目录内容，多了test.txt文件
diff --git a/base_code/linux_app/makefile_step/step5/Makefile b/base_code/linux_app/makefile_step/step5/Makefile
index bfdc16061c08274dd25bff9fe50068ac7b1c3252..37873313020da7a9600b934b30d39ec3fb247ce2 100644
--- a/base_code/linux_app/makefile_step/step5/Makefile
+++ b/base_code/linux_app/makefile_step/step5/Makefile
@@ -43,7 +43,7 @@ $(BUILD_DIR)/$(TARGET): $(OBJS)
 #*.o文件的生成规则
 $(BUILD_DIR)/%.o: $(SRC_DIR)/%.c $(DEPS)
 #创建一个编译目录，用于存放过程文件
-#命令前带“@”,表示不在终端上输出
+#命令前带"@",表示不在终端上输出
 	@mkdir -p $(BUILD_DIR)
 	$(CC) -c -o $@ $< $(CFLAGS)
 
diff --git a/base_code/linux_app/nfs_config/README.md b/base_code/linux_app/nfs_config/README.md
index 926c8b5b2950e5b0262160d789263868af13c352..3cdbb5314d754ace48a7264be355b95aa7f0f775 100644
--- a/base_code/linux_app/nfs_config/README.md
+++ b/base_code/linux_app/nfs_config/README.md
@@ -105,5 +105,5 @@ showmount   -e
     #以下命令在开发板上运行
     umount  /home/root/mountnfs
     ```
-    使用该命令时以要取消挂载的目录作为参数即可，没有输出表示执行正常。如果在当前挂载的目录进行umount操作，会提示“device is busy”。建议取消挂载时，先切换到家目录”~”，在进行umount操作。
+    使用该命令时以要取消挂载的目录作为参数即可，没有输出表示执行正常。如果在当前挂载的目录进行umount操作，会提示"device is busy"。建议取消挂载时，先切换到家目录"~"，在进行umount操作。
 
diff --git a/base_code/linux_app/spi/spi_oled/Makefile b/base_code/linux_app/spi/spi_oled/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..54a26b85c5bf7be3cf1ae64b67d8791e36a0ac43
--- /dev/null
+++ b/base_code/linux_app/spi/spi_oled/Makefile
@@ -0,0 +1,66 @@
+
+#生成可执行文件的名称
+Target = spi_oled_demo
+ARCH ?= x86
+#编译器CC
+#根据传入的参数ARCH，确定使用的编译器
+#默认使用gcc编译器
+#make ARCH=arm 时使用ARM-GCC编译器
+ifeq ($(ARCH), x86)
+	CC = gcc
+else
+	CC = arm-linux-gnueabihf-gcc
+endif
+#存放中间文件的路径
+build_dir = build_$(ARCH)
+#存放源文件的文件夹
+src_dir =  sources
+#存放头文件的文件夹
+inc_dir = includes .
+
+#源文件
+sources = $(foreach dir,$(src_dir),$(wildcard $(dir)/*.c))
+#目标文件（*.o）
+objects = $(patsubst %.c,$(build_dir)/%.o,$(notdir $(sources)))
+#头文件
+includes = $(foreach dir,$(inc_dir),$(wildcard $(dir)/*.h))
+#编译参数
+#指定头文件的路径
+CFLAGS = $(patsubst %, -I%, $(inc_dir))
+
+#链接过程
+#开发板上无法使用动态库，因此使用静态链接的方式
+$(build_dir)/$(Target) : $(objects)  | create_build
+	$(CC) $^ -o $@ 
+
+#编译工程
+#编译src文件夹中的源文件，并将生成的目标文件放在objs文件夹中
+$(build_dir)/%.o : $(src_dir)/%.c $(includes) | create_build
+	$(CC) -c $(CFLAGS) $< -o $@ 
+
+
+#以下为伪目标，调用方式：make 伪目标
+#clean：用于Clean Project
+#check：用于检查某个变量的值
+.PHONY:clean cleanall check create_build
+#按架构删除
+clean:
+	rm -rf $(build_dir)
+
+#全部删除
+cleanall:
+	rm -rf build_x86 build_arm
+
+#命令前带"@",表示不在终端上输出执行的命令
+#这个目标主要是用来调试Makefile时输出一些内容
+check:
+	@echo $(CFLAGS)
+	@echo $(CURDIR)
+	@echo $(src_dir)
+	@echo $(sources)
+	@echo $(objects)
+	
+#创建一个新目录create，用于存放过程文件
+create_build:
+	@mkdir -p $(build_dir)
+
diff --git a/base_code/linux_app/spi/spi_oled/includes/spi_oled_app.h b/base_code/linux_app/spi/spi_oled/includes/spi_oled_app.h
new file mode 100644
index 0000000000000000000000000000000000000000..d9429edee6e24147c29f1f3650cd687c64760580
--- /dev/null
+++ b/base_code/linux_app/spi/spi_oled/includes/spi_oled_app.h
@@ -0,0 +1,49 @@
+#ifndef __SPI_OLED_APP_H
+#define	__SPI_OLED_APP_H
+
+
+#include <stdint.h>
+#include <stdio.h>
+#include <stdlib.h>
+
+
+
+#define XLevelL			0x00
+#define XLevelH			0x10
+#define XLevel	    ((XLevelH&0x0F)*16+XLevelL)
+#define Max_Column	128
+#define Max_Row			64
+#define	Brightness	0xCF 
+#define X_WIDTH 		128  //oled显示屏列数
+#define Y_WIDTH 		64   //oled显示屏行数
+
+
+
+/*led 灯设备文件路径，用作SPI OLED的 D/C 引脚*/
+#define data_or_command_DEV_path "/sys/class/leds/green/brightness"
+/* SPI3 总线设备文件路径*/
+#define spi3_oled_DEV_path        "/dev/spidev2.0"
+
+
+
+
+
+
+
+
+void spi_and_gpio_init(void);
+void oled_init(void);
+void OLED_SetPos(unsigned char x, unsigned char y);//设置起始点坐标
+void OLED_Fill(unsigned char bmp_dat);//全屏填充
+void OLED_ON(void);
+void OLED_OFF(void);
+void OLED_ShowStr(unsigned char x, unsigned char y, unsigned char ch[], unsigned char TextSize);
+void OLED_ShowCN(unsigned char x, unsigned char y, unsigned char N);
+void OLED_DrawBMP(unsigned char x0, unsigned char y0, unsigned char x1, unsigned char y1, unsigned char BMP[]);
+
+
+void spi_oled_send_commend(unsigned char cmd);
+void spi_oled_send_data(unsigned char dat);
+void transfer(int fd, uint8_t const *tx, uint8_t const *rx, size_t len);
+
+#endif
\ No newline at end of file
diff --git a/base_code/linux_app/spi/spi_oled/sources/main.c b/base_code/linux_app/spi/spi_oled/sources/main.c
new file mode 100644
index 0000000000000000000000000000000000000000..07f2019331ac7b0c3312fd1070aae6fdcd084761
--- /dev/null
+++ b/base_code/linux_app/spi/spi_oled/sources/main.c
@@ -0,0 +1,84 @@
+/************************************************************/
+//功能:测试linux下spi读写OLED显示屏程序
+//使用说明: (1)
+//          (2)
+//          (3)
+//          (4)
+//日期:2019-07-03
+
+/************************************************************/
+
+
+
+/*SPI OLED 接线说明
+* OLED D/C   引脚， CSI_HSYNC   CN5 IO4.20 34    0 指令，1 数据
+* OLED MOSI  引脚， UART2_CTS   CN4 IO1.22 50
+* OLED CLOCK 引脚， UART2_RXD   CN4 IO1.21 52
+* OLED CS    引脚， GND
+* OLED GND   引脚， GND
+* OLED VCC   引脚， 3.3V  OLED不兼容5V
+*/
+
+
+#include <stdint.h>
+#include <unistd.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <getopt.h>
+#include <fcntl.h>
+#include <time.h>
+#include <sys/ioctl.h>
+#include <linux/ioctl.h>
+#include <sys/stat.h>
+#include <linux/types.h>
+#include <linux/spi/spidev.h>
+
+#include "spi_oled_app.h"
+
+
+
+/* 设备文件描述符 */
+extern int data_or_command; // 命令 、 数据 控制引脚的设备文件描述符
+extern int fd;				// SPI 控制引脚的设备文件描述符
+
+/*程序中使用到的点阵 字库*/
+extern const unsigned char BMP1[];
+
+
+int main(int argc, char *argv[])
+{
+	int i = 0; //用于循环
+	oled_init();
+	OLED_Fill(0xFF);
+
+
+	while (1)
+	{
+		sleep(1);
+
+		OLED_Fill(0x00); //清屏
+		sleep(1);
+
+		OLED_ShowStr(0, 3, (unsigned char *)"Wildfire Tech", 1);  //测试6*8字符
+		OLED_ShowStr(0, 4, (unsigned char *)"Hello wildfire", 2); //测试8*16字符
+		sleep(1);
+		OLED_Fill(0x00); //清屏
+
+		for (i = 0; i < 4; i++)
+		{
+			OLED_ShowCN(22 + i * 16, 0, i); //测试显示中文
+		}
+		sleep(1);
+		OLED_Fill(0x00); //清屏
+
+		OLED_DrawBMP(0, 0, 128, 8, (unsigned char *)BMP1); //测试BMP位图显示
+		sleep(1);
+		OLED_Fill(0x00); //清屏
+	}
+
+	close(fd);
+
+	return 0;
+}
+
diff --git a/base_code/linux_app/spi/spi_oled/sources/oled_code_table.c b/base_code/linux_app/spi/spi_oled/sources/oled_code_table.c
new file mode 100644
index 0000000000000000000000000000000000000000..410aa96885ed989564185bb096d06b7634b59517
--- /dev/null
+++ b/base_code/linux_app/spi/spi_oled/sources/oled_code_table.c
@@ -0,0 +1,304 @@
+/**
+  ******************************************************************************
+
+  * @brief   128*64点阵的OLED显示测试工程，仅适用于SD1306驱动IIC通信方式显示屏
+  ******************************************************************************
+  * @attention  *
+	* 
+	* 1. 128*64点整OLED模块功能演示程序的字表，仅适用heltec.taobao.com所售产品;
+	* 2. 字表由打包资料中的"取字软件"计算得出;
+	* 3. 取字方式 -- 共阴、列行式、逆向输出
+	*
+  *
+  ******************************************************************************
+  */ 
+
+extern const unsigned char F16x16[];
+extern const unsigned char F6x8[][6];
+extern const unsigned char F8X16[];
+extern const unsigned char BMP1[];
+
+/***************************16*16的点阵字体取模方式：共阴——列行式——逆向输出*********/
+const unsigned char F16x16[] =
+
+{	
+	0x00,0xFE,0x92,0x92,0xFE,0x92,0x92,0xFE,0x00,0x42,0x4A,0xD2,0x6A,0x46,0xC0,0x00,
+	0x40,0xC4,0x44,0x44,0x3F,0x24,0x24,0x24,0x00,0x40,0x80,0x7F,0x00,0x01,0x00,0x00,/*"野",0*/
+
+	0x00,0x00,0xC0,0x38,0x00,0x00,0x00,0xFF,0x00,0x00,0x40,0x20,0x18,0x00,0x00,0x00,
+	0x80,0x81,0x40,0x20,0x10,0x0C,0x03,0x00,0x03,0x0C,0x10,0x20,0x40,0x80,0x80,0x00,/*"火",1*/
+
+	0x24,0x24,0xA4,0xFE,0xA3,0x22,0x00,0x22,0xCC,0x00,0x00,0xFF,0x00,0x00,0x00,0x00,
+	0x08,0x06,0x01,0xFF,0x00,0x01,0x04,0x04,0x04,0x04,0x04,0xFF,0x02,0x02,0x02,0x00,/*"科",2*/
+
+	0x10,0x10,0x10,0xFF,0x10,0x90,0x08,0x88,0x88,0x88,0xFF,0x88,0x88,0x88,0x08,0x00,
+	0x04,0x44,0x82,0x7F,0x01,0x80,0x80,0x40,0x43,0x2C,0x10,0x28,0x46,0x81,0x80,0x00/*"技",3*/
+	
+		
+};
+
+
+/************************************6*8的点阵************************************/
+const unsigned char F6x8[][6] =
+{
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00,// sp
+	0x00, 0x00, 0x00, 0x2f, 0x00, 0x00,// !
+	0x00, 0x00, 0x07, 0x00, 0x07, 0x00,// "
+	0x00, 0x14, 0x7f, 0x14, 0x7f, 0x14,// #
+	0x00, 0x24, 0x2a, 0x7f, 0x2a, 0x12,// $
+	0x00, 0x62, 0x64, 0x08, 0x13, 0x23,// %
+	0x00, 0x36, 0x49, 0x55, 0x22, 0x50,// &
+	0x00, 0x00, 0x05, 0x03, 0x00, 0x00,// '
+	0x00, 0x00, 0x1c, 0x22, 0x41, 0x00,// (
+	0x00, 0x00, 0x41, 0x22, 0x1c, 0x00,// )
+	0x00, 0x14, 0x08, 0x3E, 0x08, 0x14,// *
+	0x00, 0x08, 0x08, 0x3E, 0x08, 0x08,// +
+	0x00, 0x00, 0x00, 0xA0, 0x60, 0x00,// ,
+	0x00, 0x08, 0x08, 0x08, 0x08, 0x08,// -
+	0x00, 0x00, 0x60, 0x60, 0x00, 0x00,// .
+	0x00, 0x20, 0x10, 0x08, 0x04, 0x02,// /
+	0x00, 0x3E, 0x51, 0x49, 0x45, 0x3E,// 0
+	0x00, 0x00, 0x42, 0x7F, 0x40, 0x00,// 1
+	0x00, 0x42, 0x61, 0x51, 0x49, 0x46,// 2
+	0x00, 0x21, 0x41, 0x45, 0x4B, 0x31,// 3
+	0x00, 0x18, 0x14, 0x12, 0x7F, 0x10,// 4
+	0x00, 0x27, 0x45, 0x45, 0x45, 0x39,// 5
+	0x00, 0x3C, 0x4A, 0x49, 0x49, 0x30,// 6
+	0x00, 0x01, 0x71, 0x09, 0x05, 0x03,// 7
+	0x00, 0x36, 0x49, 0x49, 0x49, 0x36,// 8
+	0x00, 0x06, 0x49, 0x49, 0x29, 0x1E,// 9
+	0x00, 0x00, 0x36, 0x36, 0x00, 0x00,// :
+	0x00, 0x00, 0x56, 0x36, 0x00, 0x00,// ;
+	0x00, 0x08, 0x14, 0x22, 0x41, 0x00,// <
+	0x00, 0x14, 0x14, 0x14, 0x14, 0x14,// =
+	0x00, 0x00, 0x41, 0x22, 0x14, 0x08,// >
+	0x00, 0x02, 0x01, 0x51, 0x09, 0x06,// ?
+	0x00, 0x32, 0x49, 0x59, 0x51, 0x3E,// @
+	0x00, 0x7C, 0x12, 0x11, 0x12, 0x7C,// A
+	0x00, 0x7F, 0x49, 0x49, 0x49, 0x36,// B
+	0x00, 0x3E, 0x41, 0x41, 0x41, 0x22,// C
+	0x00, 0x7F, 0x41, 0x41, 0x22, 0x1C,// D
+	0x00, 0x7F, 0x49, 0x49, 0x49, 0x41,// E
+	0x00, 0x7F, 0x09, 0x09, 0x09, 0x01,// F
+	0x00, 0x3E, 0x41, 0x49, 0x49, 0x7A,// G
+	0x00, 0x7F, 0x08, 0x08, 0x08, 0x7F,// H
+	0x00, 0x00, 0x41, 0x7F, 0x41, 0x00,// I
+	0x00, 0x20, 0x40, 0x41, 0x3F, 0x01,// J
+	0x00, 0x7F, 0x08, 0x14, 0x22, 0x41,// K
+	0x00, 0x7F, 0x40, 0x40, 0x40, 0x40,// L
+	0x00, 0x7F, 0x02, 0x0C, 0x02, 0x7F,// M
+	0x00, 0x7F, 0x04, 0x08, 0x10, 0x7F,// N
+	0x00, 0x3E, 0x41, 0x41, 0x41, 0x3E,// O
+	0x00, 0x7F, 0x09, 0x09, 0x09, 0x06,// P
+	0x00, 0x3E, 0x41, 0x51, 0x21, 0x5E,// Q
+	0x00, 0x7F, 0x09, 0x19, 0x29, 0x46,// R
+	0x00, 0x46, 0x49, 0x49, 0x49, 0x31,// S
+	0x00, 0x01, 0x01, 0x7F, 0x01, 0x01,// T
+	0x00, 0x3F, 0x40, 0x40, 0x40, 0x3F,// U
+	0x00, 0x1F, 0x20, 0x40, 0x20, 0x1F,// V
+	0x00, 0x3F, 0x40, 0x38, 0x40, 0x3F,// W
+	0x00, 0x63, 0x14, 0x08, 0x14, 0x63,// X
+	0x00, 0x07, 0x08, 0x70, 0x08, 0x07,// Y
+	0x00, 0x61, 0x51, 0x49, 0x45, 0x43,// Z
+	0x00, 0x00, 0x7F, 0x41, 0x41, 0x00,// [
+	0x00, 0x55, 0x2A, 0x55, 0x2A, 0x55,// 55
+	0x00, 0x00, 0x41, 0x41, 0x7F, 0x00,// ]
+	0x00, 0x04, 0x02, 0x01, 0x02, 0x04,// ^
+	0x00, 0x40, 0x40, 0x40, 0x40, 0x40,// _
+	0x00, 0x00, 0x01, 0x02, 0x04, 0x00,// '
+	0x00, 0x20, 0x54, 0x54, 0x54, 0x78,// a
+	0x00, 0x7F, 0x48, 0x44, 0x44, 0x38,// b
+	0x00, 0x38, 0x44, 0x44, 0x44, 0x20,// c
+	0x00, 0x38, 0x44, 0x44, 0x48, 0x7F,// d
+	0x00, 0x38, 0x54, 0x54, 0x54, 0x18,// e
+	0x00, 0x08, 0x7E, 0x09, 0x01, 0x02,// f
+	0x00, 0x18, 0xA4, 0xA4, 0xA4, 0x7C,// g
+	0x00, 0x7F, 0x08, 0x04, 0x04, 0x78,// h
+	0x00, 0x00, 0x44, 0x7D, 0x40, 0x00,// i
+	0x00, 0x40, 0x80, 0x84, 0x7D, 0x00,// j
+	0x00, 0x7F, 0x10, 0x28, 0x44, 0x00,// k
+	0x00, 0x00, 0x41, 0x7F, 0x40, 0x00,// l
+	0x00, 0x7C, 0x04, 0x18, 0x04, 0x78,// m
+	0x00, 0x7C, 0x08, 0x04, 0x04, 0x78,// n
+	0x00, 0x38, 0x44, 0x44, 0x44, 0x38,// o
+	0x00, 0xFC, 0x24, 0x24, 0x24, 0x18,// p
+	0x00, 0x18, 0x24, 0x24, 0x18, 0xFC,// q
+	0x00, 0x7C, 0x08, 0x04, 0x04, 0x08,// r
+	0x00, 0x48, 0x54, 0x54, 0x54, 0x20,// s
+	0x00, 0x04, 0x3F, 0x44, 0x40, 0x20,// t
+	0x00, 0x3C, 0x40, 0x40, 0x20, 0x7C,// u
+	0x00, 0x1C, 0x20, 0x40, 0x20, 0x1C,// v
+	0x00, 0x3C, 0x40, 0x30, 0x40, 0x3C,// w
+	0x00, 0x44, 0x28, 0x10, 0x28, 0x44,// x
+	0x00, 0x1C, 0xA0, 0xA0, 0xA0, 0x7C,// y
+	0x00, 0x44, 0x64, 0x54, 0x4C, 0x44,// z
+	0x14, 0x14, 0x14, 0x14, 0x14, 0x14,// horiz lines
+};
+/****************************************8*16的点阵************************************/
+const unsigned char F8X16[]=	  
+{
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,// 0
+  0x00,0x00,0x00,0xF8,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x33,0x30,0x00,0x00,0x00,//! 1
+  0x00,0x10,0x0C,0x06,0x10,0x0C,0x06,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,//" 2
+  0x40,0xC0,0x78,0x40,0xC0,0x78,0x40,0x00,0x04,0x3F,0x04,0x04,0x3F,0x04,0x04,0x00,//# 3
+  0x00,0x70,0x88,0xFC,0x08,0x30,0x00,0x00,0x00,0x18,0x20,0xFF,0x21,0x1E,0x00,0x00,//$ 4
+  0xF0,0x08,0xF0,0x00,0xE0,0x18,0x00,0x00,0x00,0x21,0x1C,0x03,0x1E,0x21,0x1E,0x00,//% 5
+  0x00,0xF0,0x08,0x88,0x70,0x00,0x00,0x00,0x1E,0x21,0x23,0x24,0x19,0x27,0x21,0x10,//& 6
+  0x10,0x16,0x0E,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,//' 7
+  0x00,0x00,0x00,0xE0,0x18,0x04,0x02,0x00,0x00,0x00,0x00,0x07,0x18,0x20,0x40,0x00,//( 8
+  0x00,0x02,0x04,0x18,0xE0,0x00,0x00,0x00,0x00,0x40,0x20,0x18,0x07,0x00,0x00,0x00,//) 9
+  0x40,0x40,0x80,0xF0,0x80,0x40,0x40,0x00,0x02,0x02,0x01,0x0F,0x01,0x02,0x02,0x00,//* 10
+  0x00,0x00,0x00,0xF0,0x00,0x00,0x00,0x00,0x01,0x01,0x01,0x1F,0x01,0x01,0x01,0x00,//+ 11
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0xB0,0x70,0x00,0x00,0x00,0x00,0x00,//, 12
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x01,0x01,0x01,0x01,0x01,0x01,//- 13
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x30,0x30,0x00,0x00,0x00,0x00,0x00,//. 14
+  0x00,0x00,0x00,0x00,0x80,0x60,0x18,0x04,0x00,0x60,0x18,0x06,0x01,0x00,0x00,0x00,/// 15
+  0x00,0xE0,0x10,0x08,0x08,0x10,0xE0,0x00,0x00,0x0F,0x10,0x20,0x20,0x10,0x0F,0x00,//0 16
+  0x00,0x10,0x10,0xF8,0x00,0x00,0x00,0x00,0x00,0x20,0x20,0x3F,0x20,0x20,0x00,0x00,//1 17
+  0x00,0x70,0x08,0x08,0x08,0x88,0x70,0x00,0x00,0x30,0x28,0x24,0x22,0x21,0x30,0x00,//2 18
+  0x00,0x30,0x08,0x88,0x88,0x48,0x30,0x00,0x00,0x18,0x20,0x20,0x20,0x11,0x0E,0x00,//3 19
+  0x00,0x00,0xC0,0x20,0x10,0xF8,0x00,0x00,0x00,0x07,0x04,0x24,0x24,0x3F,0x24,0x00,//4 20
+  0x00,0xF8,0x08,0x88,0x88,0x08,0x08,0x00,0x00,0x19,0x21,0x20,0x20,0x11,0x0E,0x00,//5 21
+  0x00,0xE0,0x10,0x88,0x88,0x18,0x00,0x00,0x00,0x0F,0x11,0x20,0x20,0x11,0x0E,0x00,//6 22
+  0x00,0x38,0x08,0x08,0xC8,0x38,0x08,0x00,0x00,0x00,0x00,0x3F,0x00,0x00,0x00,0x00,//7 23
+  0x00,0x70,0x88,0x08,0x08,0x88,0x70,0x00,0x00,0x1C,0x22,0x21,0x21,0x22,0x1C,0x00,//8 24
+  0x00,0xE0,0x10,0x08,0x08,0x10,0xE0,0x00,0x00,0x00,0x31,0x22,0x22,0x11,0x0F,0x00,//9 25
+  0x00,0x00,0x00,0xC0,0xC0,0x00,0x00,0x00,0x00,0x00,0x00,0x30,0x30,0x00,0x00,0x00,//: 26
+  0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x60,0x00,0x00,0x00,0x00,//; 27
+  0x00,0x00,0x80,0x40,0x20,0x10,0x08,0x00,0x00,0x01,0x02,0x04,0x08,0x10,0x20,0x00,//< 28
+  0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x00,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x00,//= 29
+  0x00,0x08,0x10,0x20,0x40,0x80,0x00,0x00,0x00,0x20,0x10,0x08,0x04,0x02,0x01,0x00,//> 30
+  0x00,0x70,0x48,0x08,0x08,0x08,0xF0,0x00,0x00,0x00,0x00,0x30,0x36,0x01,0x00,0x00,//? 31
+  0xC0,0x30,0xC8,0x28,0xE8,0x10,0xE0,0x00,0x07,0x18,0x27,0x24,0x23,0x14,0x0B,0x00,//@ 32
+  0x00,0x00,0xC0,0x38,0xE0,0x00,0x00,0x00,0x20,0x3C,0x23,0x02,0x02,0x27,0x38,0x20,//A 33
+  0x08,0xF8,0x88,0x88,0x88,0x70,0x00,0x00,0x20,0x3F,0x20,0x20,0x20,0x11,0x0E,0x00,//B 34
+  0xC0,0x30,0x08,0x08,0x08,0x08,0x38,0x00,0x07,0x18,0x20,0x20,0x20,0x10,0x08,0x00,//C 35
+  0x08,0xF8,0x08,0x08,0x08,0x10,0xE0,0x00,0x20,0x3F,0x20,0x20,0x20,0x10,0x0F,0x00,//D 36
+  0x08,0xF8,0x88,0x88,0xE8,0x08,0x10,0x00,0x20,0x3F,0x20,0x20,0x23,0x20,0x18,0x00,//E 37
+  0x08,0xF8,0x88,0x88,0xE8,0x08,0x10,0x00,0x20,0x3F,0x20,0x00,0x03,0x00,0x00,0x00,//F 38
+  0xC0,0x30,0x08,0x08,0x08,0x38,0x00,0x00,0x07,0x18,0x20,0x20,0x22,0x1E,0x02,0x00,//G 39
+  0x08,0xF8,0x08,0x00,0x00,0x08,0xF8,0x08,0x20,0x3F,0x21,0x01,0x01,0x21,0x3F,0x20,//H 40
+  0x00,0x08,0x08,0xF8,0x08,0x08,0x00,0x00,0x00,0x20,0x20,0x3F,0x20,0x20,0x00,0x00,//I 41
+  0x00,0x00,0x08,0x08,0xF8,0x08,0x08,0x00,0xC0,0x80,0x80,0x80,0x7F,0x00,0x00,0x00,//J 42
+  0x08,0xF8,0x88,0xC0,0x28,0x18,0x08,0x00,0x20,0x3F,0x20,0x01,0x26,0x38,0x20,0x00,//K 43
+  0x08,0xF8,0x08,0x00,0x00,0x00,0x00,0x00,0x20,0x3F,0x20,0x20,0x20,0x20,0x30,0x00,//L 44
+  0x08,0xF8,0xF8,0x00,0xF8,0xF8,0x08,0x00,0x20,0x3F,0x00,0x3F,0x00,0x3F,0x20,0x00,//M 45
+  0x08,0xF8,0x30,0xC0,0x00,0x08,0xF8,0x08,0x20,0x3F,0x20,0x00,0x07,0x18,0x3F,0x00,//N 46
+  0xE0,0x10,0x08,0x08,0x08,0x10,0xE0,0x00,0x0F,0x10,0x20,0x20,0x20,0x10,0x0F,0x00,//O 47
+  0x08,0xF8,0x08,0x08,0x08,0x08,0xF0,0x00,0x20,0x3F,0x21,0x01,0x01,0x01,0x00,0x00,//P 48
+  0xE0,0x10,0x08,0x08,0x08,0x10,0xE0,0x00,0x0F,0x18,0x24,0x24,0x38,0x50,0x4F,0x00,//Q 49
+  0x08,0xF8,0x88,0x88,0x88,0x88,0x70,0x00,0x20,0x3F,0x20,0x00,0x03,0x0C,0x30,0x20,//R 50
+  0x00,0x70,0x88,0x08,0x08,0x08,0x38,0x00,0x00,0x38,0x20,0x21,0x21,0x22,0x1C,0x00,//S 51
+  0x18,0x08,0x08,0xF8,0x08,0x08,0x18,0x00,0x00,0x00,0x20,0x3F,0x20,0x00,0x00,0x00,//T 52
+  0x08,0xF8,0x08,0x00,0x00,0x08,0xF8,0x08,0x00,0x1F,0x20,0x20,0x20,0x20,0x1F,0x00,//U 53
+  0x08,0x78,0x88,0x00,0x00,0xC8,0x38,0x08,0x00,0x00,0x07,0x38,0x0E,0x01,0x00,0x00,//V 54
+  0xF8,0x08,0x00,0xF8,0x00,0x08,0xF8,0x00,0x03,0x3C,0x07,0x00,0x07,0x3C,0x03,0x00,//W 55
+  0x08,0x18,0x68,0x80,0x80,0x68,0x18,0x08,0x20,0x30,0x2C,0x03,0x03,0x2C,0x30,0x20,//X 56
+  0x08,0x38,0xC8,0x00,0xC8,0x38,0x08,0x00,0x00,0x00,0x20,0x3F,0x20,0x00,0x00,0x00,//Y 57
+  0x10,0x08,0x08,0x08,0xC8,0x38,0x08,0x00,0x20,0x38,0x26,0x21,0x20,0x20,0x18,0x00,//Z 58
+  0x00,0x00,0x00,0xFE,0x02,0x02,0x02,0x00,0x00,0x00,0x00,0x7F,0x40,0x40,0x40,0x00,//[ 59
+  0x00,0x0C,0x30,0xC0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x06,0x38,0xC0,0x00,//\ 60
+  0x00,0x02,0x02,0x02,0xFE,0x00,0x00,0x00,0x00,0x40,0x40,0x40,0x7F,0x00,0x00,0x00,//] 61
+  0x00,0x00,0x04,0x02,0x02,0x02,0x04,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,//^ 62
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,//_ 63
+  0x00,0x02,0x02,0x04,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,//` 64
+  0x00,0x00,0x80,0x80,0x80,0x80,0x00,0x00,0x00,0x19,0x24,0x22,0x22,0x22,0x3F,0x20,//a 65
+  0x08,0xF8,0x00,0x80,0x80,0x00,0x00,0x00,0x00,0x3F,0x11,0x20,0x20,0x11,0x0E,0x00,//b 66
+  0x00,0x00,0x00,0x80,0x80,0x80,0x00,0x00,0x00,0x0E,0x11,0x20,0x20,0x20,0x11,0x00,//c 67
+  0x00,0x00,0x00,0x80,0x80,0x88,0xF8,0x00,0x00,0x0E,0x11,0x20,0x20,0x10,0x3F,0x20,//d 68
+  0x00,0x00,0x80,0x80,0x80,0x80,0x00,0x00,0x00,0x1F,0x22,0x22,0x22,0x22,0x13,0x00,//e 69
+  0x00,0x80,0x80,0xF0,0x88,0x88,0x88,0x18,0x00,0x20,0x20,0x3F,0x20,0x20,0x00,0x00,//f 70
+  0x00,0x00,0x80,0x80,0x80,0x80,0x80,0x00,0x00,0x6B,0x94,0x94,0x94,0x93,0x60,0x00,//g 71
+  0x08,0xF8,0x00,0x80,0x80,0x80,0x00,0x00,0x20,0x3F,0x21,0x00,0x00,0x20,0x3F,0x20,//h 72
+  0x00,0x80,0x98,0x98,0x00,0x00,0x00,0x00,0x00,0x20,0x20,0x3F,0x20,0x20,0x00,0x00,//i 73
+  0x00,0x00,0x00,0x80,0x98,0x98,0x00,0x00,0x00,0xC0,0x80,0x80,0x80,0x7F,0x00,0x00,//j 74
+  0x08,0xF8,0x00,0x00,0x80,0x80,0x80,0x00,0x20,0x3F,0x24,0x02,0x2D,0x30,0x20,0x00,//k 75
+  0x00,0x08,0x08,0xF8,0x00,0x00,0x00,0x00,0x00,0x20,0x20,0x3F,0x20,0x20,0x00,0x00,//l 76
+  0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x00,0x20,0x3F,0x20,0x00,0x3F,0x20,0x00,0x3F,//m 77
+  0x80,0x80,0x00,0x80,0x80,0x80,0x00,0x00,0x20,0x3F,0x21,0x00,0x00,0x20,0x3F,0x20,//n 78
+  0x00,0x00,0x80,0x80,0x80,0x80,0x00,0x00,0x00,0x1F,0x20,0x20,0x20,0x20,0x1F,0x00,//o 79
+  0x80,0x80,0x00,0x80,0x80,0x00,0x00,0x00,0x80,0xFF,0xA1,0x20,0x20,0x11,0x0E,0x00,//p 80
+  0x00,0x00,0x00,0x80,0x80,0x80,0x80,0x00,0x00,0x0E,0x11,0x20,0x20,0xA0,0xFF,0x80,//q 81
+  0x80,0x80,0x80,0x00,0x80,0x80,0x80,0x00,0x20,0x20,0x3F,0x21,0x20,0x00,0x01,0x00,//r 82
+  0x00,0x00,0x80,0x80,0x80,0x80,0x80,0x00,0x00,0x33,0x24,0x24,0x24,0x24,0x19,0x00,//s 83
+  0x00,0x80,0x80,0xE0,0x80,0x80,0x00,0x00,0x00,0x00,0x00,0x1F,0x20,0x20,0x00,0x00,//t 84
+  0x80,0x80,0x00,0x00,0x00,0x80,0x80,0x00,0x00,0x1F,0x20,0x20,0x20,0x10,0x3F,0x20,//u 85
+  0x80,0x80,0x80,0x00,0x00,0x80,0x80,0x80,0x00,0x01,0x0E,0x30,0x08,0x06,0x01,0x00,//v 86
+  0x80,0x80,0x00,0x80,0x00,0x80,0x80,0x80,0x0F,0x30,0x0C,0x03,0x0C,0x30,0x0F,0x00,//w 87
+  0x00,0x80,0x80,0x00,0x80,0x80,0x80,0x00,0x00,0x20,0x31,0x2E,0x0E,0x31,0x20,0x00,//x 88
+  0x80,0x80,0x80,0x00,0x00,0x80,0x80,0x80,0x80,0x81,0x8E,0x70,0x18,0x06,0x01,0x00,//y 89
+  0x00,0x80,0x80,0x80,0x80,0x80,0x80,0x00,0x00,0x21,0x30,0x2C,0x22,0x21,0x30,0x00,//z 90
+  0x00,0x00,0x00,0x00,0x80,0x7C,0x02,0x02,0x00,0x00,0x00,0x00,0x00,0x3F,0x40,0x40,//{ 91
+  0x00,0x00,0x00,0x00,0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0x00,0x00,0x00,//| 92
+  0x00,0x02,0x02,0x7C,0x80,0x00,0x00,0x00,0x00,0x40,0x40,0x3F,0x00,0x00,0x00,0x00,//} 93
+  0x00,0x06,0x01,0x01,0x02,0x02,0x04,0x04,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,//~ 94
+};
+
+const unsigned char BMP1[] =
+{
+	0x00,0x03,0x05,0x09,0x11,0xFF,0x11,0x89,0x05,0xC3,0x00,0xE0,0x00,0xF0,0x00,0xF8,
+	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x44,0x28,0xFF,0x11,0xAA,0x44,0x00,0x00,0x00,
+	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x83,0x01,0x38,0x44,0x82,0x92,
+	0x92,0x74,0x01,0x83,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x7C,0x44,0xC7,0x01,0x7D,
+	0x7D,0x7D,0x7D,0x01,0x7D,0x7D,0x7D,0x7D,0x01,0x7D,0x7D,0x7D,0x7D,0x01,0xFF,0x00,
+	0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x01,0x00,0x01,0x00,0x01,0x00,0x01,0x00,0x01,
+	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x01,0x00,0x00,0x00,0x00,0x00,
+	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x01,0x00,0x00,0x00,0x00,
+	0x00,0x00,0x01,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x01,0x01,
+	0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x00,
+	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x40,0x40,0x40,0x40,0x00,0x00,
+	0x6D,0x6D,0x6D,0x6D,0x6D,0x00,0x00,0x60,0x60,0x60,0x60,0x60,0x00,0x00,0x40,0x40,
+	0x40,0x40,0x40,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xDB,0xDB,0xDB,0xDB,0xDB,0x00,0x00,
+	0xDB,0xDB,0xDB,0xDB,0xDB,0x00,0x00,0xDB,0xDB,0xDB,0xDB,0xDB,0x00,0x00,0xDB,0xDB,
+	0xDB,0xDB,0xDB,0x00,0x00,0xDA,0xDA,0xDA,0xDA,0xDA,0x00,0x00,0xD8,0xD8,0xD8,0xD8,
+	0xD8,0x00,0x00,0xC0,0xC0,0xC0,0xC0,0xC0,0x00,0x00,0xC0,0xC0,0xC0,0xC0,0xC0,0x00,
+	0x00,0xC0,0xC0,0xC0,0xC0,0xC0,0x00,0x00,0xC0,0xC0,0xC0,0xC0,0xC0,0x00,0x00,0x80,
+	0x80,0x80,0x80,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x06,0x06,0x06,0x06,0x06,0x00,0x00,
+	0x06,0x06,0x06,0x06,0x06,0x00,0x00,0x06,0x06,0x06,0x06,0x06,0x00,0x00,0x06,0x06,
+	0x06,0x06,0x06,0x00,0x00,0x06,0x06,0x06,0xE6,0x66,0x20,0x00,0x06,0x06,0x86,0x06,
+	0x06,0x00,0x00,0x06,0x06,0x06,0x06,0x86,0x00,0x00,0x06,0x06,0x06,0x06,0x06,0x00,
+	0x00,0x86,0x86,0x86,0x86,0x86,0x80,0x80,0x86,0x86,0x06,0x86,0x86,0xC0,0xC0,0x86,
+	0x86,0x86,0x06,0x06,0xD0,0x30,0x76,0x06,0x06,0x06,0x06,0x00,0x00,0x06,0x06,0x06,
+	0x06,0x06,0x00,0x00,0x06,0x06,0x06,0x06,0x06,0x00,0x00,0x06,0x06,0x06,0x06,0x06,
+	0x00,0x00,0x06,0x06,0x06,0x06,0x06,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x60,0x1C,0x00,0xFE,0x00,0x01,
+	0x02,0x00,0xC4,0x18,0x20,0x02,0x9E,0x63,0xB2,0x0E,0x00,0xFF,0x81,0x81,0xFF,0x00,
+	0x00,0x80,0x40,0x30,0x0F,0x00,0x00,0x00,0x00,0xFF,0x00,0x23,0xEA,0xAA,0xBF,0xAA,
+	0xEA,0x03,0x3F,0x00,0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x00,0x00,0x00,0x80,0x80,0x80,0x00,0x00,0x00,0x00,0x00,0x80,0x80,0x80,0x00,0x00,
+	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x0E,0x0C,0x08,0x00,0x00,0x01,0x01,0x01,
+	0x01,0x01,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x01,0x00,0x81,0x80,0x80,0x81,0x80,
+	0x81,0x80,0x80,0x80,0x80,0x01,0x01,0x01,0x01,0x00,0x00,0x00,0x01,0x00,0x00,0x00,
+	0x01,0x00,0x01,0x01,0x09,0x0C,0x0E,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xC0,0xC0,0xC0,0xC0,0xC0,0xC0,0xC0,0xC0,
+	0xC0,0xC0,0xC0,0xC0,0xC0,0xC0,0xC0,0xC0,0xC0,0xC0,0xC0,0xC0,0xC0,0xC0,0xC0,0x00,
+	0x00,0x1E,0x21,0x40,0x40,0x50,0x21,0x5E,0x00,0x1E,0x21,0x40,0x40,0x50,0x21,0x5E,
+	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0xFF,0xC1,0xC1,0xFF,
+	0xFF,0xC1,0xC1,0xFF,0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0xFF,0x80,0xFC,0xF3,0xEF,0xF3,0xFC,
+	0x80,0xFF,0x80,0xEE,0xEE,0xEE,0xF5,0xFB,0xFF,0x9C,0xBE,0xB6,0xB6,0x88,0xFF,0x00,/*"D:\DreamSpark\OLED\MP3_UI.bmp",0*/
+};
+
diff --git a/base_code/linux_app/spi/spi_oled/sources/spi_oled_app.c b/base_code/linux_app/spi/spi_oled/sources/spi_oled_app.c
new file mode 100644
index 0000000000000000000000000000000000000000..8fcc90879faa352f71087fd4f201dd40bdc1cb46
--- /dev/null
+++ b/base_code/linux_app/spi/spi_oled/sources/spi_oled_app.c
@@ -0,0 +1,358 @@
+#include <sys/ioctl.h>
+#include <sys/types.h>
+#include <sys/stat.h>
+#include <fcntl.h>
+
+#include <linux/spi/spidev.h>
+#include "spi_oled_app.h"
+
+static uint32_t mode = SPI_MODE_0;           //用于保存 SPI 工作模式
+static uint8_t bits = 8;        // 接收、发送数据位数
+static uint32_t speed = 500000; // 发送速度
+static uint16_t delay;          //保存延时时间
+
+/* 设备文件描述符 */
+int data_or_command = 0; // 命令 、 数据 控制引脚的设备文件描述符
+int fd;                  // SPI 控制引脚的设备文件描述符
+
+int fd = -1;
+
+/*程序中使用到的点阵 字库*/
+extern const unsigned char F16x16[];
+extern const unsigned char F6x8[][6];
+extern const unsigned char F8X16[];
+
+/*
+* 错误处理函数。
+*/
+void pabort(const char *s)
+{
+  perror(s);
+  abort();
+}
+
+
+
+
+/*
+* 执行SPI 发送函数
+* fd， SPI设备描述符。 tx, 要发送的数据，rx，接收到的数据首地址， 发送数据长度(单位，字节)
+*/
+
+
+void transfer(int fd, uint8_t const *tx, uint8_t const *rx, size_t len)
+{
+  int ret;
+  /*------------------第一部分--------------------*/
+  struct spi_ioc_transfer tr = {
+      .tx_buf = (unsigned long)tx,
+      .rx_buf = (unsigned long)rx,
+      .len = len,
+      .delay_usecs = delay,
+      .speed_hz = speed,
+      .bits_per_word = bits,
+      .tx_nbits = 1,
+      .rx_nbits = 1
+  };
+
+  /*------------------第二部分--------------------*/
+  ret = ioctl(fd, SPI_IOC_MESSAGE(1), &tr);
+  if (ret < 1)
+  {
+    pabort("can't send spi message");
+  }
+}
+
+
+
+/*
+* 向 SPI_OLED 发送控制命令
+* cmd， 要发送的命令。 
+*/
+void spi_oled_send_commend(unsigned char cmd)
+{
+  uint8_t tx = cmd;
+  uint8_t rx;
+
+  write(data_or_command, "255", 3); //设置 SPI_OLED 的 D/C 为低电平
+  transfer(fd, &tx, &rx, 1);        //发送控制命令
+}
+
+/*
+* 向 SPI_OLED 发送数据
+* cmd， 要发送的数据。 
+*/
+void spi_oled_send_data(unsigned char dat)
+{
+  uint8_t tx = dat;
+  uint8_t rx;
+
+  write(data_or_command, "0", 1); //设置 SPI_OLED 的 D/C 为高电平
+  transfer(fd, &tx, &rx, 1);      //发送数据
+}
+
+/*
+* 填充整个OLED 显示屏
+* bmp_dat， 填充的值 
+*/
+void OLED_Fill(unsigned char bmp_dat) //全屏填充
+{
+  unsigned char y, x;
+  for (y = 0; y < 8; y++)
+  {
+    spi_oled_send_commend(0xb0 + y);
+    spi_oled_send_commend(0x01);
+    spi_oled_send_commend(0x10);
+    for (x = 0; x < X_WIDTH; x++)
+    {
+      spi_oled_send_data(bmp_dat);
+    }
+  }
+}
+
+/*
+* 设置光标位置
+* 参数： x, 目标位置的x轴坐标(取值范围 0到7 )。y， 目标位置的y轴坐标（取值范围 0到 X_WIDTH - 1）
+*/
+void OLED_SetPos(unsigned char x, unsigned char y) //设置起始点坐标
+{
+  spi_oled_send_commend(0xb0 + y);
+  spi_oled_send_commend(((x & 0xf0) >> 4) | 0x10);
+  spi_oled_send_commend((x & 0x0f) | 0x01);
+}
+
+/**
+  * @brief  OLED_ON，将OLED从休眠中唤醒
+  * @param  无
+	* @retval 无
+  */
+void OLED_ON(void)
+{
+  spi_oled_send_commend(0X8D); //设置电荷泵
+  spi_oled_send_commend(0X14); //开启电荷泵
+  spi_oled_send_commend(0XAF); //OLED唤醒
+}
+
+/**
+  * @brief  OLED_OFF，让OLED休眠 -- 休眠模式下,OLED功耗不到10uA
+  * @param  无
+	* @retval 无
+  */
+void OLED_OFF(void)
+{
+  spi_oled_send_commend(0X8D); //设置电荷泵
+  spi_oled_send_commend(0X10); //关闭电荷泵
+  spi_oled_send_commend(0XAE); //OLED休眠
+}
+
+/*
+* oled 初始化函数
+*/
+void oled_init(void)
+{
+  spi_and_gpio_init();
+
+  spi_oled_send_commend(0xae);
+  spi_oled_send_commend(0xae); //--turn off oled panel
+  spi_oled_send_commend(0x00); //---set low column address
+  spi_oled_send_commend(0x10); //---set high column address
+  spi_oled_send_commend(0x40); //--set start line address  Set Mapping RAM Display Start Line (0x00~0x3F)
+  spi_oled_send_commend(0x81); //--set contrast control register
+  spi_oled_send_commend(0xcf); // Set SEG Output Current Brightness
+  spi_oled_send_commend(0xa1); //--Set SEG/Column Mapping     0xa0,0xa1
+  spi_oled_send_commend(0xc8); //Set COM/Row Scan Direction   0xc0,0xc8
+  spi_oled_send_commend(0xa6); //--set normal display
+  spi_oled_send_commend(0xa8); //--set multiplex ratio(1 to 64)
+  spi_oled_send_commend(0x3f); //--1/64 duty
+  spi_oled_send_commend(0xd3); //-set display offset	Shift Mapping RAM Counter (0x00~0x3F)
+  spi_oled_send_commend(0x00); //-not offset
+  spi_oled_send_commend(0xd5); //--set display clock divide ratio/oscillator frequency
+  spi_oled_send_commend(0x80); //--set divide ratio, Set Clock as 100 Frames/Sec
+  spi_oled_send_commend(0xd9); //--set pre-charge period
+  spi_oled_send_commend(0xf1); //Set Pre-Charge as 15 Clocks & Discharge as 1 Clock
+  spi_oled_send_commend(0xda); //--set com pins hardware configuration
+  spi_oled_send_commend(0x12);
+  spi_oled_send_commend(0xdb); //--set vcomh
+  spi_oled_send_commend(0x40); //Set VCOM Deselect Level
+  spi_oled_send_commend(0x20); //-Set Page Addressing Mode (0x00/0x01/0x02)
+  spi_oled_send_commend(0x02); //
+  spi_oled_send_commend(0x8d); //--set Charge Pump enable/disable
+  spi_oled_send_commend(0x14); //--set(0x10) disable
+  spi_oled_send_commend(0xa4); // Disable Entire Display On (0xa4/0xa5)
+  spi_oled_send_commend(0xa6); // Disable Inverse Display On (0xa6/a7)
+  spi_oled_send_commend(0xaf); //--turn on oled panel
+
+  OLED_Fill(0x00);
+  OLED_SetPos(0, 0);
+}
+
+
+
+/*
+* 初始化SPI ,初始化OLED 使用到的命令、数据控制引脚
+*/
+void spi_and_gpio_init(void)
+{
+  int ret = 0;
+
+  /*打开 SPI 设备*/
+  fd = open("/dev/spidev2.0", O_RDWR);
+  if (fd < 0)
+  {
+    pabort("can't open /dev/spidev2.0 ");
+  }
+
+  /*打开 LED 设备*/
+  data_or_command = open(data_or_command_DEV_path, O_RDWR);
+  if (fd < 0)
+  {
+    pabort("can't open /sys/class/leds/green/brightness");
+  }
+
+  /*
+	 * spi mode 设置SPI 工作模式
+	 */
+  ret = ioctl(fd, SPI_IOC_WR_MODE32, &mode);
+  if (ret == -1)
+    pabort("can't set spi mode");
+
+  ret = ioctl(fd, SPI_IOC_RD_MODE32, &mode);
+  if (ret == -1)
+    pabort("can't get spi mode");
+
+  /*
+	 * bits per word  设置一个字节的位数
+	 */
+  ret = ioctl(fd, SPI_IOC_WR_BITS_PER_WORD, &bits);
+  if (ret == -1)
+    pabort("can't set bits per word");
+
+  ret = ioctl(fd, SPI_IOC_RD_BITS_PER_WORD, &bits);
+  if (ret == -1)
+    pabort("can't get bits per word");
+
+  /*
+	 * max speed hz  设置SPI 最高工作频率
+	 */
+  ret = ioctl(fd, SPI_IOC_WR_MAX_SPEED_HZ, &speed);
+  if (ret == -1)
+    pabort("can't set max speed hz");
+
+  ret = ioctl(fd, SPI_IOC_RD_MAX_SPEED_HZ, &speed);
+  if (ret == -1)
+    pabort("can't get max speed hz");
+
+  printf("spi mode: 0x%x\n", mode);
+  printf("bits per word: %d\n", bits);
+  printf("max speed: %d Hz (%d KHz)\n", speed, speed / 1000);
+}
+
+
+
+
+
+/**
+  * @brief  OLED_ShowStr，显示codetab.h中的ASCII字符,有6*8和8*16可选择
+  * @param  x,y : 起始点坐标(x:0~127, y:0~7);
+	*					ch[] :- 要显示的字符串; 
+	*					TextSize : 字符大小(1:6*8 ; 2:8*16)
+	* @retval 无
+  */
+void OLED_ShowStr(unsigned char x, unsigned char y, unsigned char ch[], unsigned char TextSize)
+{
+  unsigned char c = 0, i = 0, j = 0;
+  switch (TextSize)
+  {
+  case 1:
+  {
+    while (ch[j] != '\0')
+    {
+      c = ch[j] - 32;
+      if (x > 126)
+      {
+        x = 0;
+        y++;
+      }
+      OLED_SetPos(x, y);
+      for (i = 0; i < 6; i++)
+        spi_oled_send_data(F6x8[c][i]);
+      x += 6;
+      j++;
+    }
+  }
+  break;
+  case 2:
+  {
+    while (ch[j] != '\0')
+    {
+      c = ch[j] - 32;
+      if (x > 120)
+      {
+        x = 0;
+        y++;
+      }
+      OLED_SetPos(x, y);
+      for (i = 0; i < 8; i++)
+        spi_oled_send_data(F8X16[c * 16 + i]);
+      OLED_SetPos(x, y + 1);
+      for (i = 0; i < 8; i++)
+        spi_oled_send_data(F8X16[c * 16 + i + 8]);
+      x += 8;
+      j++;
+    }
+  }
+  break;
+  }
+}
+
+
+/**
+  * @brief  OLED_ShowCN，显示codetab.h中的汉字,16*16点阵
+  * @param  x,y: 起始点坐标(x:0~127, y:0~7); 
+	*					N:汉字在codetab.h中的索引
+	* @retval 无
+  */
+void OLED_ShowCN(unsigned char x, unsigned char y, unsigned char N)
+{
+  unsigned char wm = 0;
+  unsigned int adder = 32 * N;
+  OLED_SetPos(x, y);
+  for (wm = 0; wm < 16; wm++)
+  {
+    spi_oled_send_data(F16x16[adder]);
+    adder += 1;
+  }
+  OLED_SetPos(x, y + 1);
+  for (wm = 0; wm < 16; wm++)
+  {
+    spi_oled_send_data(F16x16[adder]);
+    adder += 1;
+  }
+}
+
+
+
+/**
+  * @brief  OLED_DrawBMP，显示BMP位图
+  * @param  x0,y0 :起始点坐标(x0:0~127, y0:0~7);
+	*					x1,y1 : 起点对角线(结束点)的坐标(x1:1~128,y1:1~8)
+	* @retval 无
+  */
+void OLED_DrawBMP(unsigned char x0, unsigned char y0, unsigned char x1, unsigned char y1, unsigned char BMP[])
+{
+  unsigned int j = 0;
+  unsigned char x, y;
+
+  if (y1 % 8 == 0)
+    y = y1 / 8;
+  else
+    y = y1 / 8 + 1;
+  for (y = y0; y < y1; y++)
+  {
+    OLED_SetPos(x0, y);
+    for (x = x0; x < x1; x++)
+    {
+      spi_oled_send_data(BMP[j++]);
+    }
+  }
+}
diff --git a/base_code/linux_app/spi/spi_test/Makefile b/base_code/linux_app/spi/spi_test/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..8062600524c4da4af2b1d1064f371ea2c32cdbd3
--- /dev/null
+++ b/base_code/linux_app/spi/spi_test/Makefile
@@ -0,0 +1,66 @@
+
+#生成可执行文件的名称
+Target = spi_test_demo
+ARCH ?= x86
+#编译器CC
+#根据传入的参数ARCH，确定使用的编译器
+#默认使用gcc编译器
+#make ARCH=arm 时使用ARM-GCC编译器
+ifeq ($(ARCH), x86)
+	CC = gcc
+else
+	CC = arm-linux-gnueabihf-gcc
+endif
+#存放中间文件的路径
+build_dir = build_$(ARCH)
+#存放源文件的文件夹
+src_dir =  sources
+#存放头文件的文件夹
+inc_dir = includes .
+
+#源文件
+sources = $(foreach dir,$(src_dir),$(wildcard $(dir)/*.c))
+#目标文件（*.o）
+objects = $(patsubst %.c,$(build_dir)/%.o,$(notdir $(sources)))
+#头文件
+includes = $(foreach dir,$(inc_dir),$(wildcard $(dir)/*.h))
+#编译参数
+#指定头文件的路径
+CFLAGS = $(patsubst %, -I%, $(inc_dir))
+
+#链接过程
+#开发板上无法使用动态库，因此使用静态链接的方式
+$(build_dir)/$(Target) : $(objects)  | create_build
+	$(CC) $^ -o $@ 
+
+#编译工程
+#编译src文件夹中的源文件，并将生成的目标文件放在objs文件夹中
+$(build_dir)/%.o : $(src_dir)/%.c $(includes) | create_build
+	$(CC) -c $(CFLAGS) $< -o $@ 
+
+
+#以下为伪目标，调用方式：make 伪目标
+#clean：用于Clean Project
+#check：用于检查某个变量的值
+.PHONY:clean cleanall check create_build
+#按架构删除
+clean:
+	rm -rf $(build_dir)
+
+#全部删除
+cleanall:
+	rm -rf build_x86 build_arm
+
+#命令前带"@",表示不在终端上输出执行的命令
+#这个目标主要是用来调试Makefile时输出一些内容
+check:
+	@echo $(CFLAGS)
+	@echo $(CURDIR)
+	@echo $(src_dir)
+	@echo $(sources)
+	@echo $(objects)
+	
+#创建一个新目录create，用于存放过程文件
+create_build:
+	@mkdir -p $(build_dir)
+
diff --git a/base_code/linux_app/spi/spi_test/includes/spi_oled_app.h b/base_code/linux_app/spi/spi_test/includes/spi_oled_app.h
new file mode 100644
index 0000000000000000000000000000000000000000..969d9512ea34df00be82ab2d07f8aad8a8ded870
--- /dev/null
+++ b/base_code/linux_app/spi/spi_test/includes/spi_oled_app.h
@@ -0,0 +1,19 @@
+#ifndef __SPI_OLED_APP_H
+#define	__SPI_OLED_APP_H
+
+#include <stdint.h>
+#include <stdio.h>
+#include <stdlib.h>
+
+
+
+/* SPI3 总线设备文件路径*/
+#define spi3_oled_DEV_path        "/dev/spidev2.0"
+
+
+
+
+void spi_init(void);
+void transfer(int fd, uint8_t const *tx, uint8_t const *rx, size_t len);
+
+#endif
\ No newline at end of file
diff --git a/base_code/linux_app/spi/spi_test/sources/main.c b/base_code/linux_app/spi/spi_test/sources/main.c
new file mode 100644
index 0000000000000000000000000000000000000000..a7687834a366bcc3450658e8dc64cc860f0c3799
--- /dev/null
+++ b/base_code/linux_app/spi/spi_test/sources/main.c
@@ -0,0 +1,61 @@
+/************************************************************/
+//功能:测试linux下spi读写OLED显示屏程序
+//使用说明: (1)
+//          (2)
+//          (3)
+//          (4)
+//日期:2019-07-03
+
+/************************************************************/
+
+/*SPI OLED 接线说明
+* OLED D/C   引脚， CSI_HSYNC   CN5 IO4.20 34    0 指令，1 数据
+* OLED MOSI  引脚， UART2_CTS   CN4 IO1.22 50
+* OLED CLOCK 引脚， UART2_RXD   CN4 IO1.21 52
+* OLED CS    引脚， GND
+* OLED GND   引脚， GND
+* OLED VCC   引脚， 3.3V  OLED不兼容5V
+*/
+
+#include <stdint.h>
+#include <unistd.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <getopt.h>
+#include <fcntl.h>
+#include <time.h>
+#include <sys/ioctl.h>
+#include <linux/ioctl.h>
+#include <sys/stat.h>
+#include <linux/types.h>
+#include <linux/spi/spidev.h>
+
+#include "spi_oled_app.h"
+
+
+/*SPI 接收 、发送 缓冲区*/
+unsigned char tx_buffer[100] = "hello the world !";
+unsigned char rx_buffer[100];
+
+
+extern int fd;                  // SPI 控制引脚的设备文件描述符
+
+
+
+int main(int argc, char *argv[])
+{
+	/*初始化SPI */
+	spi_init();
+
+	/*执行发送*/
+	transfer(fd, tx_buffer, rx_buffer, sizeof(tx_buffer));
+
+	/*打印 tx_buffer 和 rx_buffer*/
+	printf("tx_buffer: \n %s\n ", tx_buffer);
+	printf("rx_buffer: \n %s\n ", rx_buffer);
+
+	close(fd);
+
+	return 0;
+}
diff --git a/base_code/linux_app/spi/spi_test/sources/oled_code_table.c b/base_code/linux_app/spi/spi_test/sources/oled_code_table.c
new file mode 100644
index 0000000000000000000000000000000000000000..410aa96885ed989564185bb096d06b7634b59517
--- /dev/null
+++ b/base_code/linux_app/spi/spi_test/sources/oled_code_table.c
@@ -0,0 +1,304 @@
+/**
+  ******************************************************************************
+
+  * @brief   128*64点阵的OLED显示测试工程，仅适用于SD1306驱动IIC通信方式显示屏
+  ******************************************************************************
+  * @attention  *
+	* 
+	* 1. 128*64点整OLED模块功能演示程序的字表，仅适用heltec.taobao.com所售产品;
+	* 2. 字表由打包资料中的"取字软件"计算得出;
+	* 3. 取字方式 -- 共阴、列行式、逆向输出
+	*
+  *
+  ******************************************************************************
+  */ 
+
+extern const unsigned char F16x16[];
+extern const unsigned char F6x8[][6];
+extern const unsigned char F8X16[];
+extern const unsigned char BMP1[];
+
+/***************************16*16的点阵字体取模方式：共阴——列行式——逆向输出*********/
+const unsigned char F16x16[] =
+
+{	
+	0x00,0xFE,0x92,0x92,0xFE,0x92,0x92,0xFE,0x00,0x42,0x4A,0xD2,0x6A,0x46,0xC0,0x00,
+	0x40,0xC4,0x44,0x44,0x3F,0x24,0x24,0x24,0x00,0x40,0x80,0x7F,0x00,0x01,0x00,0x00,/*"野",0*/
+
+	0x00,0x00,0xC0,0x38,0x00,0x00,0x00,0xFF,0x00,0x00,0x40,0x20,0x18,0x00,0x00,0x00,
+	0x80,0x81,0x40,0x20,0x10,0x0C,0x03,0x00,0x03,0x0C,0x10,0x20,0x40,0x80,0x80,0x00,/*"火",1*/
+
+	0x24,0x24,0xA4,0xFE,0xA3,0x22,0x00,0x22,0xCC,0x00,0x00,0xFF,0x00,0x00,0x00,0x00,
+	0x08,0x06,0x01,0xFF,0x00,0x01,0x04,0x04,0x04,0x04,0x04,0xFF,0x02,0x02,0x02,0x00,/*"科",2*/
+
+	0x10,0x10,0x10,0xFF,0x10,0x90,0x08,0x88,0x88,0x88,0xFF,0x88,0x88,0x88,0x08,0x00,
+	0x04,0x44,0x82,0x7F,0x01,0x80,0x80,0x40,0x43,0x2C,0x10,0x28,0x46,0x81,0x80,0x00/*"技",3*/
+	
+		
+};
+
+
+/************************************6*8的点阵************************************/
+const unsigned char F6x8[][6] =
+{
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00,// sp
+	0x00, 0x00, 0x00, 0x2f, 0x00, 0x00,// !
+	0x00, 0x00, 0x07, 0x00, 0x07, 0x00,// "
+	0x00, 0x14, 0x7f, 0x14, 0x7f, 0x14,// #
+	0x00, 0x24, 0x2a, 0x7f, 0x2a, 0x12,// $
+	0x00, 0x62, 0x64, 0x08, 0x13, 0x23,// %
+	0x00, 0x36, 0x49, 0x55, 0x22, 0x50,// &
+	0x00, 0x00, 0x05, 0x03, 0x00, 0x00,// '
+	0x00, 0x00, 0x1c, 0x22, 0x41, 0x00,// (
+	0x00, 0x00, 0x41, 0x22, 0x1c, 0x00,// )
+	0x00, 0x14, 0x08, 0x3E, 0x08, 0x14,// *
+	0x00, 0x08, 0x08, 0x3E, 0x08, 0x08,// +
+	0x00, 0x00, 0x00, 0xA0, 0x60, 0x00,// ,
+	0x00, 0x08, 0x08, 0x08, 0x08, 0x08,// -
+	0x00, 0x00, 0x60, 0x60, 0x00, 0x00,// .
+	0x00, 0x20, 0x10, 0x08, 0x04, 0x02,// /
+	0x00, 0x3E, 0x51, 0x49, 0x45, 0x3E,// 0
+	0x00, 0x00, 0x42, 0x7F, 0x40, 0x00,// 1
+	0x00, 0x42, 0x61, 0x51, 0x49, 0x46,// 2
+	0x00, 0x21, 0x41, 0x45, 0x4B, 0x31,// 3
+	0x00, 0x18, 0x14, 0x12, 0x7F, 0x10,// 4
+	0x00, 0x27, 0x45, 0x45, 0x45, 0x39,// 5
+	0x00, 0x3C, 0x4A, 0x49, 0x49, 0x30,// 6
+	0x00, 0x01, 0x71, 0x09, 0x05, 0x03,// 7
+	0x00, 0x36, 0x49, 0x49, 0x49, 0x36,// 8
+	0x00, 0x06, 0x49, 0x49, 0x29, 0x1E,// 9
+	0x00, 0x00, 0x36, 0x36, 0x00, 0x00,// :
+	0x00, 0x00, 0x56, 0x36, 0x00, 0x00,// ;
+	0x00, 0x08, 0x14, 0x22, 0x41, 0x00,// <
+	0x00, 0x14, 0x14, 0x14, 0x14, 0x14,// =
+	0x00, 0x00, 0x41, 0x22, 0x14, 0x08,// >
+	0x00, 0x02, 0x01, 0x51, 0x09, 0x06,// ?
+	0x00, 0x32, 0x49, 0x59, 0x51, 0x3E,// @
+	0x00, 0x7C, 0x12, 0x11, 0x12, 0x7C,// A
+	0x00, 0x7F, 0x49, 0x49, 0x49, 0x36,// B
+	0x00, 0x3E, 0x41, 0x41, 0x41, 0x22,// C
+	0x00, 0x7F, 0x41, 0x41, 0x22, 0x1C,// D
+	0x00, 0x7F, 0x49, 0x49, 0x49, 0x41,// E
+	0x00, 0x7F, 0x09, 0x09, 0x09, 0x01,// F
+	0x00, 0x3E, 0x41, 0x49, 0x49, 0x7A,// G
+	0x00, 0x7F, 0x08, 0x08, 0x08, 0x7F,// H
+	0x00, 0x00, 0x41, 0x7F, 0x41, 0x00,// I
+	0x00, 0x20, 0x40, 0x41, 0x3F, 0x01,// J
+	0x00, 0x7F, 0x08, 0x14, 0x22, 0x41,// K
+	0x00, 0x7F, 0x40, 0x40, 0x40, 0x40,// L
+	0x00, 0x7F, 0x02, 0x0C, 0x02, 0x7F,// M
+	0x00, 0x7F, 0x04, 0x08, 0x10, 0x7F,// N
+	0x00, 0x3E, 0x41, 0x41, 0x41, 0x3E,// O
+	0x00, 0x7F, 0x09, 0x09, 0x09, 0x06,// P
+	0x00, 0x3E, 0x41, 0x51, 0x21, 0x5E,// Q
+	0x00, 0x7F, 0x09, 0x19, 0x29, 0x46,// R
+	0x00, 0x46, 0x49, 0x49, 0x49, 0x31,// S
+	0x00, 0x01, 0x01, 0x7F, 0x01, 0x01,// T
+	0x00, 0x3F, 0x40, 0x40, 0x40, 0x3F,// U
+	0x00, 0x1F, 0x20, 0x40, 0x20, 0x1F,// V
+	0x00, 0x3F, 0x40, 0x38, 0x40, 0x3F,// W
+	0x00, 0x63, 0x14, 0x08, 0x14, 0x63,// X
+	0x00, 0x07, 0x08, 0x70, 0x08, 0x07,// Y
+	0x00, 0x61, 0x51, 0x49, 0x45, 0x43,// Z
+	0x00, 0x00, 0x7F, 0x41, 0x41, 0x00,// [
+	0x00, 0x55, 0x2A, 0x55, 0x2A, 0x55,// 55
+	0x00, 0x00, 0x41, 0x41, 0x7F, 0x00,// ]
+	0x00, 0x04, 0x02, 0x01, 0x02, 0x04,// ^
+	0x00, 0x40, 0x40, 0x40, 0x40, 0x40,// _
+	0x00, 0x00, 0x01, 0x02, 0x04, 0x00,// '
+	0x00, 0x20, 0x54, 0x54, 0x54, 0x78,// a
+	0x00, 0x7F, 0x48, 0x44, 0x44, 0x38,// b
+	0x00, 0x38, 0x44, 0x44, 0x44, 0x20,// c
+	0x00, 0x38, 0x44, 0x44, 0x48, 0x7F,// d
+	0x00, 0x38, 0x54, 0x54, 0x54, 0x18,// e
+	0x00, 0x08, 0x7E, 0x09, 0x01, 0x02,// f
+	0x00, 0x18, 0xA4, 0xA4, 0xA4, 0x7C,// g
+	0x00, 0x7F, 0x08, 0x04, 0x04, 0x78,// h
+	0x00, 0x00, 0x44, 0x7D, 0x40, 0x00,// i
+	0x00, 0x40, 0x80, 0x84, 0x7D, 0x00,// j
+	0x00, 0x7F, 0x10, 0x28, 0x44, 0x00,// k
+	0x00, 0x00, 0x41, 0x7F, 0x40, 0x00,// l
+	0x00, 0x7C, 0x04, 0x18, 0x04, 0x78,// m
+	0x00, 0x7C, 0x08, 0x04, 0x04, 0x78,// n
+	0x00, 0x38, 0x44, 0x44, 0x44, 0x38,// o
+	0x00, 0xFC, 0x24, 0x24, 0x24, 0x18,// p
+	0x00, 0x18, 0x24, 0x24, 0x18, 0xFC,// q
+	0x00, 0x7C, 0x08, 0x04, 0x04, 0x08,// r
+	0x00, 0x48, 0x54, 0x54, 0x54, 0x20,// s
+	0x00, 0x04, 0x3F, 0x44, 0x40, 0x20,// t
+	0x00, 0x3C, 0x40, 0x40, 0x20, 0x7C,// u
+	0x00, 0x1C, 0x20, 0x40, 0x20, 0x1C,// v
+	0x00, 0x3C, 0x40, 0x30, 0x40, 0x3C,// w
+	0x00, 0x44, 0x28, 0x10, 0x28, 0x44,// x
+	0x00, 0x1C, 0xA0, 0xA0, 0xA0, 0x7C,// y
+	0x00, 0x44, 0x64, 0x54, 0x4C, 0x44,// z
+	0x14, 0x14, 0x14, 0x14, 0x14, 0x14,// horiz lines
+};
+/****************************************8*16的点阵************************************/
+const unsigned char F8X16[]=	  
+{
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,// 0
+  0x00,0x00,0x00,0xF8,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x33,0x30,0x00,0x00,0x00,//! 1
+  0x00,0x10,0x0C,0x06,0x10,0x0C,0x06,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,//" 2
+  0x40,0xC0,0x78,0x40,0xC0,0x78,0x40,0x00,0x04,0x3F,0x04,0x04,0x3F,0x04,0x04,0x00,//# 3
+  0x00,0x70,0x88,0xFC,0x08,0x30,0x00,0x00,0x00,0x18,0x20,0xFF,0x21,0x1E,0x00,0x00,//$ 4
+  0xF0,0x08,0xF0,0x00,0xE0,0x18,0x00,0x00,0x00,0x21,0x1C,0x03,0x1E,0x21,0x1E,0x00,//% 5
+  0x00,0xF0,0x08,0x88,0x70,0x00,0x00,0x00,0x1E,0x21,0x23,0x24,0x19,0x27,0x21,0x10,//& 6
+  0x10,0x16,0x0E,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,//' 7
+  0x00,0x00,0x00,0xE0,0x18,0x04,0x02,0x00,0x00,0x00,0x00,0x07,0x18,0x20,0x40,0x00,//( 8
+  0x00,0x02,0x04,0x18,0xE0,0x00,0x00,0x00,0x00,0x40,0x20,0x18,0x07,0x00,0x00,0x00,//) 9
+  0x40,0x40,0x80,0xF0,0x80,0x40,0x40,0x00,0x02,0x02,0x01,0x0F,0x01,0x02,0x02,0x00,//* 10
+  0x00,0x00,0x00,0xF0,0x00,0x00,0x00,0x00,0x01,0x01,0x01,0x1F,0x01,0x01,0x01,0x00,//+ 11
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0xB0,0x70,0x00,0x00,0x00,0x00,0x00,//, 12
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x01,0x01,0x01,0x01,0x01,0x01,//- 13
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x30,0x30,0x00,0x00,0x00,0x00,0x00,//. 14
+  0x00,0x00,0x00,0x00,0x80,0x60,0x18,0x04,0x00,0x60,0x18,0x06,0x01,0x00,0x00,0x00,/// 15
+  0x00,0xE0,0x10,0x08,0x08,0x10,0xE0,0x00,0x00,0x0F,0x10,0x20,0x20,0x10,0x0F,0x00,//0 16
+  0x00,0x10,0x10,0xF8,0x00,0x00,0x00,0x00,0x00,0x20,0x20,0x3F,0x20,0x20,0x00,0x00,//1 17
+  0x00,0x70,0x08,0x08,0x08,0x88,0x70,0x00,0x00,0x30,0x28,0x24,0x22,0x21,0x30,0x00,//2 18
+  0x00,0x30,0x08,0x88,0x88,0x48,0x30,0x00,0x00,0x18,0x20,0x20,0x20,0x11,0x0E,0x00,//3 19
+  0x00,0x00,0xC0,0x20,0x10,0xF8,0x00,0x00,0x00,0x07,0x04,0x24,0x24,0x3F,0x24,0x00,//4 20
+  0x00,0xF8,0x08,0x88,0x88,0x08,0x08,0x00,0x00,0x19,0x21,0x20,0x20,0x11,0x0E,0x00,//5 21
+  0x00,0xE0,0x10,0x88,0x88,0x18,0x00,0x00,0x00,0x0F,0x11,0x20,0x20,0x11,0x0E,0x00,//6 22
+  0x00,0x38,0x08,0x08,0xC8,0x38,0x08,0x00,0x00,0x00,0x00,0x3F,0x00,0x00,0x00,0x00,//7 23
+  0x00,0x70,0x88,0x08,0x08,0x88,0x70,0x00,0x00,0x1C,0x22,0x21,0x21,0x22,0x1C,0x00,//8 24
+  0x00,0xE0,0x10,0x08,0x08,0x10,0xE0,0x00,0x00,0x00,0x31,0x22,0x22,0x11,0x0F,0x00,//9 25
+  0x00,0x00,0x00,0xC0,0xC0,0x00,0x00,0x00,0x00,0x00,0x00,0x30,0x30,0x00,0x00,0x00,//: 26
+  0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x60,0x00,0x00,0x00,0x00,//; 27
+  0x00,0x00,0x80,0x40,0x20,0x10,0x08,0x00,0x00,0x01,0x02,0x04,0x08,0x10,0x20,0x00,//< 28
+  0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x00,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x00,//= 29
+  0x00,0x08,0x10,0x20,0x40,0x80,0x00,0x00,0x00,0x20,0x10,0x08,0x04,0x02,0x01,0x00,//> 30
+  0x00,0x70,0x48,0x08,0x08,0x08,0xF0,0x00,0x00,0x00,0x00,0x30,0x36,0x01,0x00,0x00,//? 31
+  0xC0,0x30,0xC8,0x28,0xE8,0x10,0xE0,0x00,0x07,0x18,0x27,0x24,0x23,0x14,0x0B,0x00,//@ 32
+  0x00,0x00,0xC0,0x38,0xE0,0x00,0x00,0x00,0x20,0x3C,0x23,0x02,0x02,0x27,0x38,0x20,//A 33
+  0x08,0xF8,0x88,0x88,0x88,0x70,0x00,0x00,0x20,0x3F,0x20,0x20,0x20,0x11,0x0E,0x00,//B 34
+  0xC0,0x30,0x08,0x08,0x08,0x08,0x38,0x00,0x07,0x18,0x20,0x20,0x20,0x10,0x08,0x00,//C 35
+  0x08,0xF8,0x08,0x08,0x08,0x10,0xE0,0x00,0x20,0x3F,0x20,0x20,0x20,0x10,0x0F,0x00,//D 36
+  0x08,0xF8,0x88,0x88,0xE8,0x08,0x10,0x00,0x20,0x3F,0x20,0x20,0x23,0x20,0x18,0x00,//E 37
+  0x08,0xF8,0x88,0x88,0xE8,0x08,0x10,0x00,0x20,0x3F,0x20,0x00,0x03,0x00,0x00,0x00,//F 38
+  0xC0,0x30,0x08,0x08,0x08,0x38,0x00,0x00,0x07,0x18,0x20,0x20,0x22,0x1E,0x02,0x00,//G 39
+  0x08,0xF8,0x08,0x00,0x00,0x08,0xF8,0x08,0x20,0x3F,0x21,0x01,0x01,0x21,0x3F,0x20,//H 40
+  0x00,0x08,0x08,0xF8,0x08,0x08,0x00,0x00,0x00,0x20,0x20,0x3F,0x20,0x20,0x00,0x00,//I 41
+  0x00,0x00,0x08,0x08,0xF8,0x08,0x08,0x00,0xC0,0x80,0x80,0x80,0x7F,0x00,0x00,0x00,//J 42
+  0x08,0xF8,0x88,0xC0,0x28,0x18,0x08,0x00,0x20,0x3F,0x20,0x01,0x26,0x38,0x20,0x00,//K 43
+  0x08,0xF8,0x08,0x00,0x00,0x00,0x00,0x00,0x20,0x3F,0x20,0x20,0x20,0x20,0x30,0x00,//L 44
+  0x08,0xF8,0xF8,0x00,0xF8,0xF8,0x08,0x00,0x20,0x3F,0x00,0x3F,0x00,0x3F,0x20,0x00,//M 45
+  0x08,0xF8,0x30,0xC0,0x00,0x08,0xF8,0x08,0x20,0x3F,0x20,0x00,0x07,0x18,0x3F,0x00,//N 46
+  0xE0,0x10,0x08,0x08,0x08,0x10,0xE0,0x00,0x0F,0x10,0x20,0x20,0x20,0x10,0x0F,0x00,//O 47
+  0x08,0xF8,0x08,0x08,0x08,0x08,0xF0,0x00,0x20,0x3F,0x21,0x01,0x01,0x01,0x00,0x00,//P 48
+  0xE0,0x10,0x08,0x08,0x08,0x10,0xE0,0x00,0x0F,0x18,0x24,0x24,0x38,0x50,0x4F,0x00,//Q 49
+  0x08,0xF8,0x88,0x88,0x88,0x88,0x70,0x00,0x20,0x3F,0x20,0x00,0x03,0x0C,0x30,0x20,//R 50
+  0x00,0x70,0x88,0x08,0x08,0x08,0x38,0x00,0x00,0x38,0x20,0x21,0x21,0x22,0x1C,0x00,//S 51
+  0x18,0x08,0x08,0xF8,0x08,0x08,0x18,0x00,0x00,0x00,0x20,0x3F,0x20,0x00,0x00,0x00,//T 52
+  0x08,0xF8,0x08,0x00,0x00,0x08,0xF8,0x08,0x00,0x1F,0x20,0x20,0x20,0x20,0x1F,0x00,//U 53
+  0x08,0x78,0x88,0x00,0x00,0xC8,0x38,0x08,0x00,0x00,0x07,0x38,0x0E,0x01,0x00,0x00,//V 54
+  0xF8,0x08,0x00,0xF8,0x00,0x08,0xF8,0x00,0x03,0x3C,0x07,0x00,0x07,0x3C,0x03,0x00,//W 55
+  0x08,0x18,0x68,0x80,0x80,0x68,0x18,0x08,0x20,0x30,0x2C,0x03,0x03,0x2C,0x30,0x20,//X 56
+  0x08,0x38,0xC8,0x00,0xC8,0x38,0x08,0x00,0x00,0x00,0x20,0x3F,0x20,0x00,0x00,0x00,//Y 57
+  0x10,0x08,0x08,0x08,0xC8,0x38,0x08,0x00,0x20,0x38,0x26,0x21,0x20,0x20,0x18,0x00,//Z 58
+  0x00,0x00,0x00,0xFE,0x02,0x02,0x02,0x00,0x00,0x00,0x00,0x7F,0x40,0x40,0x40,0x00,//[ 59
+  0x00,0x0C,0x30,0xC0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x06,0x38,0xC0,0x00,//\ 60
+  0x00,0x02,0x02,0x02,0xFE,0x00,0x00,0x00,0x00,0x40,0x40,0x40,0x7F,0x00,0x00,0x00,//] 61
+  0x00,0x00,0x04,0x02,0x02,0x02,0x04,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,//^ 62
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,//_ 63
+  0x00,0x02,0x02,0x04,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,//` 64
+  0x00,0x00,0x80,0x80,0x80,0x80,0x00,0x00,0x00,0x19,0x24,0x22,0x22,0x22,0x3F,0x20,//a 65
+  0x08,0xF8,0x00,0x80,0x80,0x00,0x00,0x00,0x00,0x3F,0x11,0x20,0x20,0x11,0x0E,0x00,//b 66
+  0x00,0x00,0x00,0x80,0x80,0x80,0x00,0x00,0x00,0x0E,0x11,0x20,0x20,0x20,0x11,0x00,//c 67
+  0x00,0x00,0x00,0x80,0x80,0x88,0xF8,0x00,0x00,0x0E,0x11,0x20,0x20,0x10,0x3F,0x20,//d 68
+  0x00,0x00,0x80,0x80,0x80,0x80,0x00,0x00,0x00,0x1F,0x22,0x22,0x22,0x22,0x13,0x00,//e 69
+  0x00,0x80,0x80,0xF0,0x88,0x88,0x88,0x18,0x00,0x20,0x20,0x3F,0x20,0x20,0x00,0x00,//f 70
+  0x00,0x00,0x80,0x80,0x80,0x80,0x80,0x00,0x00,0x6B,0x94,0x94,0x94,0x93,0x60,0x00,//g 71
+  0x08,0xF8,0x00,0x80,0x80,0x80,0x00,0x00,0x20,0x3F,0x21,0x00,0x00,0x20,0x3F,0x20,//h 72
+  0x00,0x80,0x98,0x98,0x00,0x00,0x00,0x00,0x00,0x20,0x20,0x3F,0x20,0x20,0x00,0x00,//i 73
+  0x00,0x00,0x00,0x80,0x98,0x98,0x00,0x00,0x00,0xC0,0x80,0x80,0x80,0x7F,0x00,0x00,//j 74
+  0x08,0xF8,0x00,0x00,0x80,0x80,0x80,0x00,0x20,0x3F,0x24,0x02,0x2D,0x30,0x20,0x00,//k 75
+  0x00,0x08,0x08,0xF8,0x00,0x00,0x00,0x00,0x00,0x20,0x20,0x3F,0x20,0x20,0x00,0x00,//l 76
+  0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x00,0x20,0x3F,0x20,0x00,0x3F,0x20,0x00,0x3F,//m 77
+  0x80,0x80,0x00,0x80,0x80,0x80,0x00,0x00,0x20,0x3F,0x21,0x00,0x00,0x20,0x3F,0x20,//n 78
+  0x00,0x00,0x80,0x80,0x80,0x80,0x00,0x00,0x00,0x1F,0x20,0x20,0x20,0x20,0x1F,0x00,//o 79
+  0x80,0x80,0x00,0x80,0x80,0x00,0x00,0x00,0x80,0xFF,0xA1,0x20,0x20,0x11,0x0E,0x00,//p 80
+  0x00,0x00,0x00,0x80,0x80,0x80,0x80,0x00,0x00,0x0E,0x11,0x20,0x20,0xA0,0xFF,0x80,//q 81
+  0x80,0x80,0x80,0x00,0x80,0x80,0x80,0x00,0x20,0x20,0x3F,0x21,0x20,0x00,0x01,0x00,//r 82
+  0x00,0x00,0x80,0x80,0x80,0x80,0x80,0x00,0x00,0x33,0x24,0x24,0x24,0x24,0x19,0x00,//s 83
+  0x00,0x80,0x80,0xE0,0x80,0x80,0x00,0x00,0x00,0x00,0x00,0x1F,0x20,0x20,0x00,0x00,//t 84
+  0x80,0x80,0x00,0x00,0x00,0x80,0x80,0x00,0x00,0x1F,0x20,0x20,0x20,0x10,0x3F,0x20,//u 85
+  0x80,0x80,0x80,0x00,0x00,0x80,0x80,0x80,0x00,0x01,0x0E,0x30,0x08,0x06,0x01,0x00,//v 86
+  0x80,0x80,0x00,0x80,0x00,0x80,0x80,0x80,0x0F,0x30,0x0C,0x03,0x0C,0x30,0x0F,0x00,//w 87
+  0x00,0x80,0x80,0x00,0x80,0x80,0x80,0x00,0x00,0x20,0x31,0x2E,0x0E,0x31,0x20,0x00,//x 88
+  0x80,0x80,0x80,0x00,0x00,0x80,0x80,0x80,0x80,0x81,0x8E,0x70,0x18,0x06,0x01,0x00,//y 89
+  0x00,0x80,0x80,0x80,0x80,0x80,0x80,0x00,0x00,0x21,0x30,0x2C,0x22,0x21,0x30,0x00,//z 90
+  0x00,0x00,0x00,0x00,0x80,0x7C,0x02,0x02,0x00,0x00,0x00,0x00,0x00,0x3F,0x40,0x40,//{ 91
+  0x00,0x00,0x00,0x00,0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0x00,0x00,0x00,//| 92
+  0x00,0x02,0x02,0x7C,0x80,0x00,0x00,0x00,0x00,0x40,0x40,0x3F,0x00,0x00,0x00,0x00,//} 93
+  0x00,0x06,0x01,0x01,0x02,0x02,0x04,0x04,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,//~ 94
+};
+
+const unsigned char BMP1[] =
+{
+	0x00,0x03,0x05,0x09,0x11,0xFF,0x11,0x89,0x05,0xC3,0x00,0xE0,0x00,0xF0,0x00,0xF8,
+	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x44,0x28,0xFF,0x11,0xAA,0x44,0x00,0x00,0x00,
+	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x83,0x01,0x38,0x44,0x82,0x92,
+	0x92,0x74,0x01,0x83,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x7C,0x44,0xC7,0x01,0x7D,
+	0x7D,0x7D,0x7D,0x01,0x7D,0x7D,0x7D,0x7D,0x01,0x7D,0x7D,0x7D,0x7D,0x01,0xFF,0x00,
+	0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x01,0x00,0x01,0x00,0x01,0x00,0x01,0x00,0x01,
+	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x01,0x00,0x00,0x00,0x00,0x00,
+	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x01,0x00,0x00,0x00,0x00,
+	0x00,0x00,0x01,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x01,0x01,
+	0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x00,
+	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x40,0x40,0x40,0x40,0x00,0x00,
+	0x6D,0x6D,0x6D,0x6D,0x6D,0x00,0x00,0x60,0x60,0x60,0x60,0x60,0x00,0x00,0x40,0x40,
+	0x40,0x40,0x40,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xDB,0xDB,0xDB,0xDB,0xDB,0x00,0x00,
+	0xDB,0xDB,0xDB,0xDB,0xDB,0x00,0x00,0xDB,0xDB,0xDB,0xDB,0xDB,0x00,0x00,0xDB,0xDB,
+	0xDB,0xDB,0xDB,0x00,0x00,0xDA,0xDA,0xDA,0xDA,0xDA,0x00,0x00,0xD8,0xD8,0xD8,0xD8,
+	0xD8,0x00,0x00,0xC0,0xC0,0xC0,0xC0,0xC0,0x00,0x00,0xC0,0xC0,0xC0,0xC0,0xC0,0x00,
+	0x00,0xC0,0xC0,0xC0,0xC0,0xC0,0x00,0x00,0xC0,0xC0,0xC0,0xC0,0xC0,0x00,0x00,0x80,
+	0x80,0x80,0x80,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x06,0x06,0x06,0x06,0x06,0x00,0x00,
+	0x06,0x06,0x06,0x06,0x06,0x00,0x00,0x06,0x06,0x06,0x06,0x06,0x00,0x00,0x06,0x06,
+	0x06,0x06,0x06,0x00,0x00,0x06,0x06,0x06,0xE6,0x66,0x20,0x00,0x06,0x06,0x86,0x06,
+	0x06,0x00,0x00,0x06,0x06,0x06,0x06,0x86,0x00,0x00,0x06,0x06,0x06,0x06,0x06,0x00,
+	0x00,0x86,0x86,0x86,0x86,0x86,0x80,0x80,0x86,0x86,0x06,0x86,0x86,0xC0,0xC0,0x86,
+	0x86,0x86,0x06,0x06,0xD0,0x30,0x76,0x06,0x06,0x06,0x06,0x00,0x00,0x06,0x06,0x06,
+	0x06,0x06,0x00,0x00,0x06,0x06,0x06,0x06,0x06,0x00,0x00,0x06,0x06,0x06,0x06,0x06,
+	0x00,0x00,0x06,0x06,0x06,0x06,0x06,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x60,0x1C,0x00,0xFE,0x00,0x01,
+	0x02,0x00,0xC4,0x18,0x20,0x02,0x9E,0x63,0xB2,0x0E,0x00,0xFF,0x81,0x81,0xFF,0x00,
+	0x00,0x80,0x40,0x30,0x0F,0x00,0x00,0x00,0x00,0xFF,0x00,0x23,0xEA,0xAA,0xBF,0xAA,
+	0xEA,0x03,0x3F,0x00,0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x00,0x00,0x00,0x80,0x80,0x80,0x00,0x00,0x00,0x00,0x00,0x80,0x80,0x80,0x00,0x00,
+	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x0E,0x0C,0x08,0x00,0x00,0x01,0x01,0x01,
+	0x01,0x01,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x01,0x00,0x81,0x80,0x80,0x81,0x80,
+	0x81,0x80,0x80,0x80,0x80,0x01,0x01,0x01,0x01,0x00,0x00,0x00,0x01,0x00,0x00,0x00,
+	0x01,0x00,0x01,0x01,0x09,0x0C,0x0E,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xC0,0xC0,0xC0,0xC0,0xC0,0xC0,0xC0,0xC0,
+	0xC0,0xC0,0xC0,0xC0,0xC0,0xC0,0xC0,0xC0,0xC0,0xC0,0xC0,0xC0,0xC0,0xC0,0xC0,0x00,
+	0x00,0x1E,0x21,0x40,0x40,0x50,0x21,0x5E,0x00,0x1E,0x21,0x40,0x40,0x50,0x21,0x5E,
+	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0xFF,0xC1,0xC1,0xFF,
+	0xFF,0xC1,0xC1,0xFF,0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0xFF,0x80,0xFC,0xF3,0xEF,0xF3,0xFC,
+	0x80,0xFF,0x80,0xEE,0xEE,0xEE,0xF5,0xFB,0xFF,0x9C,0xBE,0xB6,0xB6,0x88,0xFF,0x00,/*"D:\DreamSpark\OLED\MP3_UI.bmp",0*/
+};
+
diff --git a/base_code/linux_app/spi/spi_test/sources/spi_oled_app.c b/base_code/linux_app/spi/spi_test/sources/spi_oled_app.c
new file mode 100644
index 0000000000000000000000000000000000000000..7c8dcad51f4ab77aba4079429a42ec2a2ad1660f
--- /dev/null
+++ b/base_code/linux_app/spi/spi_test/sources/spi_oled_app.c
@@ -0,0 +1,116 @@
+#include <sys/ioctl.h>
+#include <sys/types.h>
+#include <sys/stat.h>
+#include <fcntl.h>
+
+#include <linux/spi/spidev.h>
+#include "spi_oled_app.h"
+
+static  uint32_t mode;           //用于保存 SPI 工作模式
+static  uint8_t bits = 8;        // 接收、发送数据位数
+static  uint32_t speed = 500000; // 发送速度
+static  uint16_t delay;          //保存延时时间
+
+/* 设备文件描述符 */
+int fd;                  // SPI 控制引脚的设备文件描述符
+
+
+
+/*
+* 错误处理函数。
+*/
+void pabort(const char *s)
+{
+  perror(s);
+  abort();
+}
+
+/*
+* 执行SPI 发送函数
+* fd， SPI设备描述符。 tx, 要发送的数据，rx，接收到的数据首地址， 发送数据长度(单位，字节)
+*/
+void transfer(int fd, uint8_t const *tx, uint8_t const *rx, size_t len)
+{
+  int ret;
+  int out_fd;
+  struct spi_ioc_transfer tr = {
+      .tx_buf = (unsigned long)tx,
+      .rx_buf = (unsigned long)rx,
+      .len = len,
+      .delay_usecs = delay,
+      .speed_hz = speed,
+      .bits_per_word = bits,
+  };
+
+
+
+  ret = ioctl(fd, SPI_IOC_MESSAGE(1), &tr);
+  if (ret < 1)
+  {
+    pabort("can't send spi message");
+  }
+}
+
+
+
+/*
+* 初始化SPI ,初始化OLED 使用到的命令、数据控制引脚
+*/
+void spi_init(void)
+{
+  int ret = 0;
+
+  /*打开 SPI 设备*/
+  fd = open("/dev/spidev2.0", O_RDWR);
+  if (fd < 0)
+  {
+    pabort("can't open /dev/spidev2.0 ");
+  }
+
+  /*
+	 * spi mode 设置SPI 工作模式
+	 */
+  ret = ioctl(fd, SPI_IOC_WR_MODE32, &mode);
+  if (ret == -1)
+    pabort("can't set spi mode");
+
+  ret = ioctl(fd, SPI_IOC_RD_MODE32, &mode);
+  if (ret == -1)
+    pabort("can't get spi mode");
+
+  /*
+	 * bits per word  设置一个字节的位数
+	 */
+  ret = ioctl(fd, SPI_IOC_WR_BITS_PER_WORD, &bits);
+  if (ret == -1)
+    pabort("can't set bits per word");
+
+  ret = ioctl(fd, SPI_IOC_RD_BITS_PER_WORD, &bits);
+  if (ret == -1)
+    pabort("can't get bits per word");
+
+  /*
+	 * max speed hz  设置SPI 最高工作频率
+	 */
+  ret = ioctl(fd, SPI_IOC_WR_MAX_SPEED_HZ, &speed);
+  if (ret == -1)
+    pabort("can't set max speed hz");
+
+  ret = ioctl(fd, SPI_IOC_RD_MAX_SPEED_HZ, &speed);
+  if (ret == -1)
+    pabort("can't get max speed hz");
+
+  printf("spi mode: 0x%x\n", mode);
+  printf("bits per word: %d\n", bits);
+  printf("max speed: %d Hz (%d KHz)\n", speed, speed / 1000);
+}
+
+
+
+
+
+
+
+
+
+
diff --git a/base_code/linux_app/tty/README.md b/base_code/linux_app/tty/README.md
index fdfdd66180956fac37ee0d70be6ad47ddee238e8..468030238afaaedc9c79279e9593da7753e1507f 100644
--- a/base_code/linux_app/tty/README.md
+++ b/base_code/linux_app/tty/README.md
@@ -4,8 +4,8 @@
 
 - /dev/ttymxc0用于串口1，默认用于控制开发板的命令行终端。
 - /dev/ttymxc2用于串口3，是开发板上UART3的DB9接口，使用是必须要连接跳线帽：
-    * “UART3_TXD<---->T2IN”
-    * “UART3_RXD<---->R2OUT”
+    * "UART3_TXD<---->T2IN"
+    * "UART3_RXD<---->R2OUT"
 
 
 各个目录的演示说明如下：
diff --git a/base_code/linux_app/tty/c/Makefile b/base_code/linux_app/tty/c/Makefile
index 09ab31b769448abf6f9f9043c47f2b218d433c33..71d6e029ce484270044f55419db436a4e8fbde40 100644
--- a/base_code/linux_app/tty/c/Makefile
+++ b/base_code/linux_app/tty/c/Makefile
@@ -51,7 +51,7 @@ clean:
 cleanall:
 	rm -rf build_x86 build_arm
 
-#命令前带“@”,表示不在终端上输出执行的命令
+#命令前带"@",表示不在终端上输出执行的命令
 #这个目标主要是用来调试Makefile时输出一些内容
 check:
 	@echo $(CFLAGS)
diff --git a/base_code/linux_app/tty/c_full/Makefile b/base_code/linux_app/tty/c_full/Makefile
index 09ab31b769448abf6f9f9043c47f2b218d433c33..71d6e029ce484270044f55419db436a4e8fbde40 100644
--- a/base_code/linux_app/tty/c_full/Makefile
+++ b/base_code/linux_app/tty/c_full/Makefile
@@ -51,7 +51,7 @@ clean:
 cleanall:
 	rm -rf build_x86 build_arm
 
-#命令前带“@”,表示不在终端上输出执行的命令
+#命令前带"@",表示不在终端上输出执行的命令
 #这个目标主要是用来调试Makefile时输出一些内容
 check:
 	@echo $(CFLAGS)
diff --git a/base_code/linux_app/tty/c_ioctl/Makefile b/base_code/linux_app/tty/c_ioctl/Makefile
index 09ab31b769448abf6f9f9043c47f2b218d433c33..71d6e029ce484270044f55419db436a4e8fbde40 100644
--- a/base_code/linux_app/tty/c_ioctl/Makefile
+++ b/base_code/linux_app/tty/c_ioctl/Makefile
@@ -51,7 +51,7 @@ clean:
 cleanall:
 	rm -rf build_x86 build_arm
 
-#命令前带“@”,表示不在终端上输出执行的命令
+#命令前带"@",表示不在终端上输出执行的命令
 #这个目标主要是用来调试Makefile时输出一些内容
 check:
 	@echo $(CFLAGS)
diff --git a/base_code/linux_app/tty/shell/uart.sh b/base_code/linux_app/tty/shell/uart.sh
index a1ed64ce5b45aacbdb445a3abb341d4362da5f58..578e723d240d5cb3d93c6fd1d21e71579333b249 100644
--- a/base_code/linux_app/tty/shell/uart.sh
+++ b/base_code/linux_app/tty/shell/uart.sh
@@ -2,7 +2,7 @@
 # 串口(uart3)发送接受实验
 # echo用于向串口发送数据
 # cat用于接收数据
-# 按“Ctrl+C”可退出
+# 按"Ctrl+C"可退出
 # 注意：用户往UART3发送数据时，需要在发送内容后加上换行符
 echo "embedfire imx6ull uart demo" > /dev/ttymxc2
 
diff --git a/base_code/linux_debug/backtrace/Makefile b/base_code/linux_debug/backtrace/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..dcc912463f7940fabd799586c863ce87f87c981e
--- /dev/null
+++ b/base_code/linux_debug/backtrace/Makefile
@@ -0,0 +1,62 @@
+# 解释一下： 
+# 　　（1）第1行指定编译器为 gcc，可以根据需要修改为 g++ 或者 arm-linux-gcc 等交叉编译工具链。 
+# 　　（2）第2行是为了获取匹配模式的文件名，*.c 表示当前工程目录的 c 文件，*/*.c 表示所有下一级目录的 .c 文件。 
+# 　　（3）第3行是将 $(SRC) 中的 .c 文件替换成 .o 文件。 	SRC=$(wildcard *.c */*.c)
+# 　　（4）第4行用于指定编译选项，根据需要添加，比如 -g、-ml、-Wall、-O2 等等。 
+# 　　（5）第5、6行，同样使用了 wildcard 和 patsubst 函数来处理，目的是为了指定最终生成的可执行文件名。 
+# 　　（6）第8行 $(TARGET):$(OBJS) 表示由 .o 文件链接成可执行文件。 
+# 　　（7）注意第9行前面是一个 <tab> 键，而 $@ 表示目标，也就是 $(TARGET)，$^ 表示依赖列表，也就是 $(OBJS) 。 
+# 　　（9）第12行中的 $< 表示搜索到的第一个匹配的文件。 
+# 　　（10）第14行的 clean 是伪目标（.PHONY），它不需要依赖，执行 make 命令时是不会执行的，当执行 make clean 时才会执行。 
+# 　　（11）.PHONY:clean 防止当前目录下有clean文件导致无法清除
+# 　　另外，Makefile 的赋值除了使用等号（=），还可以使用 := 、+= 、?= 符号。具体含义如下：
+
+# := 即使变量   表示简单赋值（注意右边的 $ 值只会向上寻找）
+# = 延时变量
+# += 表示追加赋值
+# ?= 表示判断赋值（判断左边是否已经定义过，如果是则忽略本次赋值）
+
+# CC=gcc
+# SRCS=$(wildcard *.c */*.c)
+# OBJS=$(patsubst %.c, %.o, $(SRCS))
+# FLAG=-g
+# NAME=$(wildcard *.c)
+# TARGET=$(patsubst %.c, %, $(NAME))
+
+# $(TARGET):$(OBJS)
+# 	$(CC) -o $@ $^ $(FLAG)
+
+# %.o:%.c
+# 	$(CC) -o $@ -c $< -g
+
+# clean:
+# 	rm -rf $(TARGET) $(OBJS)
+
+# .PHONY:clean
+
+# CC = arm-linux-gnueabihf-gcc
+CC=gcc
+SRC = $(wildcard *.c */*.c)
+OBJS = $(patsubst %.c, %.o, $(SRC))
+DEP_FILES := $(patsubst %, .%.d,$(OBJS))
+DEP_FILES := $(wildcard $(DEP_FILES))
+FLAG = -g -Werror -I. -Iinclude -static
+TARGET = targets
+
+$(TARGET):$(OBJS)
+	$(CC) -o $@ $^ $(FLAG)
+
+ifneq ($(DEP_FILES),)
+include $(DEP_FILES)
+endif
+
+%.o:%.c
+	$(CC) -o $@ -c $(FLAG) $< -g -MD -MF .$@.d
+
+clean:
+	rm -rf $(TARGET) $(OBJS)
+
+distclean:
+	rm -rf $(DEP_FILES)
+
+.PHONY:clean
diff --git a/base_code/linux_debug/backtrace/backtrace.c b/base_code/linux_debug/backtrace/backtrace.c
new file mode 100644
index 0000000000000000000000000000000000000000..cf6df8438c054cc29afac2041ad5fcf4492c7fbd
--- /dev/null
+++ b/base_code/linux_debug/backtrace/backtrace.c
@@ -0,0 +1,71 @@
+#include <sys/types.h>
+#include <unistd.h>
+#include <stdio.h>
+#include <stdlib.h>
+
+void test1(int arg)
+{
+    int num;
+    num = arg;
+
+    printf("\t\t---我是 test%d 函数\n", num);
+}
+
+void test2(int arg)
+{
+    int num;
+    num = arg;
+
+    printf("\t--我是 test%d 函数\n", num);
+
+    printf("\t-- test%d 开始调用 test1 \n", num);
+    test1(1);
+    printf("\t-- test%d 结束调用 test1 \n", num);
+
+    printf("\t--结束调用 test%d \n", num);
+}
+
+void test3(int arg)
+{
+    int num;
+    num = arg;
+
+    printf("-我是 test%d 函数\n", num);
+
+    printf("- test%d 开始调用 test2 \n", num);
+    test2(2);
+    printf("- test%d 结束调用 test1 \n", num);
+
+    printf("-结束调用 test%d \n", num);
+}
+
+int main(void)
+{
+    test3(3);
+
+    sleep(1);     // 防止进程过快退出
+
+    return 0;
+}
+
+
+// int fibonacci(int n)
+// {       
+//     if (n == 1 || n == 2) {   
+//         return 1;
+//     }   
+
+//     return fibonacci(n - 1) + fibonacci(n - 2);                                                                                                            
+// }       
+        
+// int main()
+// {       
+//     int n = 10; 
+//     int ret = 0;
+
+//     ret = fibonacci(n);
+
+//     printf("fibonacci(%d)=%d\n", n, ret);
+
+//     return 0;
+// }
diff --git a/base_code/linux_debug/core_dump/Makefile b/base_code/linux_debug/core_dump/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..dcc912463f7940fabd799586c863ce87f87c981e
--- /dev/null
+++ b/base_code/linux_debug/core_dump/Makefile
@@ -0,0 +1,62 @@
+# 解释一下： 
+# 　　（1）第1行指定编译器为 gcc，可以根据需要修改为 g++ 或者 arm-linux-gcc 等交叉编译工具链。 
+# 　　（2）第2行是为了获取匹配模式的文件名，*.c 表示当前工程目录的 c 文件，*/*.c 表示所有下一级目录的 .c 文件。 
+# 　　（3）第3行是将 $(SRC) 中的 .c 文件替换成 .o 文件。 	SRC=$(wildcard *.c */*.c)
+# 　　（4）第4行用于指定编译选项，根据需要添加，比如 -g、-ml、-Wall、-O2 等等。 
+# 　　（5）第5、6行，同样使用了 wildcard 和 patsubst 函数来处理，目的是为了指定最终生成的可执行文件名。 
+# 　　（6）第8行 $(TARGET):$(OBJS) 表示由 .o 文件链接成可执行文件。 
+# 　　（7）注意第9行前面是一个 <tab> 键，而 $@ 表示目标，也就是 $(TARGET)，$^ 表示依赖列表，也就是 $(OBJS) 。 
+# 　　（9）第12行中的 $< 表示搜索到的第一个匹配的文件。 
+# 　　（10）第14行的 clean 是伪目标（.PHONY），它不需要依赖，执行 make 命令时是不会执行的，当执行 make clean 时才会执行。 
+# 　　（11）.PHONY:clean 防止当前目录下有clean文件导致无法清除
+# 　　另外，Makefile 的赋值除了使用等号（=），还可以使用 := 、+= 、?= 符号。具体含义如下：
+
+# := 即使变量   表示简单赋值（注意右边的 $ 值只会向上寻找）
+# = 延时变量
+# += 表示追加赋值
+# ?= 表示判断赋值（判断左边是否已经定义过，如果是则忽略本次赋值）
+
+# CC=gcc
+# SRCS=$(wildcard *.c */*.c)
+# OBJS=$(patsubst %.c, %.o, $(SRCS))
+# FLAG=-g
+# NAME=$(wildcard *.c)
+# TARGET=$(patsubst %.c, %, $(NAME))
+
+# $(TARGET):$(OBJS)
+# 	$(CC) -o $@ $^ $(FLAG)
+
+# %.o:%.c
+# 	$(CC) -o $@ -c $< -g
+
+# clean:
+# 	rm -rf $(TARGET) $(OBJS)
+
+# .PHONY:clean
+
+# CC = arm-linux-gnueabihf-gcc
+CC=gcc
+SRC = $(wildcard *.c */*.c)
+OBJS = $(patsubst %.c, %.o, $(SRC))
+DEP_FILES := $(patsubst %, .%.d,$(OBJS))
+DEP_FILES := $(wildcard $(DEP_FILES))
+FLAG = -g -Werror -I. -Iinclude -static
+TARGET = targets
+
+$(TARGET):$(OBJS)
+	$(CC) -o $@ $^ $(FLAG)
+
+ifneq ($(DEP_FILES),)
+include $(DEP_FILES)
+endif
+
+%.o:%.c
+	$(CC) -o $@ -c $(FLAG) $< -g -MD -MF .$@.d
+
+clean:
+	rm -rf $(TARGET) $(OBJS)
+
+distclean:
+	rm -rf $(DEP_FILES)
+
+.PHONY:clean
diff --git a/base_code/linux_debug/core_dump/core_dump.c b/base_code/linux_debug/core_dump/core_dump.c
new file mode 100644
index 0000000000000000000000000000000000000000..8747020ba191bc47c412064a62ed8addb6fbeff7
--- /dev/null
+++ b/base_code/linux_debug/core_dump/core_dump.c
@@ -0,0 +1,21 @@
+#include <sys/types.h>
+#include <unistd.h>
+#include <stdio.h>
+#include <stdlib.h>
+
+int main(void)
+{
+    int *a = NULL;
+
+    printf("这是一个错误\n");
+
+    // abort();
+    *a = 0x1;
+
+    printf("看看我是否能打印出来\n");
+
+    sleep(1);       // 防止进程过快退出
+
+    return 0;
+}
+
diff --git a/base_code/linux_debug/gdb_use/hello.c b/base_code/linux_debug/gdb_use/hello.c
new file mode 100644
index 0000000000000000000000000000000000000000..56eeee82fba57bbb4018873be960d3fdd6bc4360
--- /dev/null
+++ b/base_code/linux_debug/gdb_use/hello.c
@@ -0,0 +1,14 @@
+/* $begin hello */
+#include <stdio.h>
+
+int main() 
+{
+	printf("hello, world! This is a C program.\n");
+	for(int i=0;i<10;i++ ){
+		printf("output i=%d\n",i);
+	}
+
+	return 0;
+}
+/* $end hello */
+
diff --git a/base_code/linux_driver/1_SupportMoreDev/Makefile b/base_code/linux_driver/1_SupportMoreDev/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..409daf5259b498a65b9b30a8f201aac73ecfb988
--- /dev/null
+++ b/base_code/linux_driver/1_SupportMoreDev/Makefile
@@ -0,0 +1,10 @@
+KERNEL_DIR=/home/embedfire/module/linux-imx
+
+obj-m := chrdev.o
+
+all:
+	$(MAKE) -C $(KERNEL_DIR) M=$(CURDIR) modules
+	
+.PHONY:clean
+clean:
+	$(MAKE) -C $(KERNEL_DIR) M=$(CURDIR) clean
\ No newline at end of file
diff --git a/base_code/linux_driver/1_SupportMoreDev/chrdev.c b/base_code/linux_driver/1_SupportMoreDev/chrdev.c
new file mode 100644
index 0000000000000000000000000000000000000000..899c6b7d2cb518f6a2dc3e306cc2cb5cca589b94
--- /dev/null
+++ b/base_code/linux_driver/1_SupportMoreDev/chrdev.c
@@ -0,0 +1,128 @@
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/fs.h>
+#include <linux/cdev.h>
+#include <linux/uaccess.h>
+#define DEV_NAME            "EmbedCharDev"
+#define DEV_CNT                 (2)
+#define BUFF_SIZE               128
+//定义字符设备的设备号
+static dev_t devno;
+//定义字符设备结构体chr_dev
+static struct cdev chr_dev;
+//数据缓冲区
+static char vbuf1[BUFF_SIZE];
+static char vbuf2[BUFF_SIZE];
+static int chr_dev_open(struct inode *inode, struct file *filp);
+static int chr_dev_release(struct inode *inode, struct file *filp);
+static ssize_t chr_dev_write(struct file *filp, const char __user * buf, size_t count, loff_t *ppos);
+static ssize_t chr_dev_read(struct file *filp, char __user * buf, size_t count, loff_t *ppos);
+static struct file_operations  chr_dev_fops = 
+{
+    .owner = THIS_MODULE,
+    .open = chr_dev_open,
+    .release = chr_dev_release,
+    .write = chr_dev_write,
+    .read = chr_dev_read,
+};
+
+static int chr_dev_open(struct inode *inode, struct file *filp)
+{
+    printk("\nopen\n ");
+    switch(MINOR(inode->i_rdev))
+    {
+        case 0 :
+        {
+            filp->private_data = vbuf1;
+            break;
+        }
+        case 1 :
+        {
+            filp->private_data = vbuf2;
+            break;
+        }
+    }
+    return 0;
+}
+
+static int chr_dev_release(struct inode *inode, struct file *filp)
+{
+    printk("\nrelease\n");
+    return 0;
+}
+
+static ssize_t chr_dev_write(struct file *filp, const char __user * buf, size_t count, loff_t *ppos)
+{
+    unsigned long p = *ppos;
+    int ret;
+    char *vbuf = filp->private_data;
+    int tmp = count ;
+    if(p > BUFF_SIZE)
+        return 0;
+    if(tmp > BUFF_SIZE - p)
+        tmp = BUFF_SIZE - p;
+    ret = copy_from_user(vbuf, buf, tmp);
+    *ppos += tmp;
+    return tmp;
+}
+
+static ssize_t chr_dev_read(struct file *filp, char __user * buf, size_t count, loff_t *ppos)
+{
+    unsigned long p = *ppos;
+    int ret;
+    int tmp = count ;
+    char *vbuf = filp->private_data;
+    if(p >= BUFF_SIZE)
+        return 0;
+    if(tmp > BUFF_SIZE - p)
+        tmp = BUFF_SIZE - p;
+    ret = copy_to_user(buf, vbuf+p, tmp);
+    *ppos +=tmp;
+    return tmp;
+}
+
+static int __init chrdev_init(void)
+{
+    int ret = 0;
+    printk("chrdev init\n");
+    //第一步
+    //采用动态分配的方式，获取设备编号，次设备号为0，
+    //设备名称为EmbedCharDev，可通过命令cat  /proc/devices查看
+    //DEV_CNT为1，当前只申请一个设备编号
+    ret = alloc_chrdev_region(&devno, 0, DEV_CNT, DEV_NAME);
+    if(ret < 0){
+        printk("fail to alloc devno\n");
+        goto alloc_err;
+    }
+    //第二步
+    //关联字符设备结构体cdev与文件操作结构体file_operations
+    cdev_init(&chr_dev, &chr_dev_fops);
+    //第三步
+    //添加设备至cdev_map散列表中
+    ret = cdev_add(&chr_dev, devno, DEV_CNT);
+    if(ret < 0)
+    {
+        printk("fail to add cdev\n");
+        goto add_err;
+    }
+    return 0;
+
+add_err:
+    //添加设备失败时，需要注销设备号
+    unregister_chrdev_region(devno, DEV_CNT);
+alloc_err:
+    return ret;
+}
+module_init(chrdev_init);
+
+static void __exit chrdev_exit(void)
+{
+    printk("chrdev exit\n");
+    unregister_chrdev_region(devno, DEV_CNT);
+
+    cdev_del(&chr_dev);
+}
+module_exit(chrdev_exit);
+
+MODULE_LICENSE("GPL");
+
diff --git a/base_code/linux_driver/1_SupportMoreDev/main.c b/base_code/linux_driver/1_SupportMoreDev/main.c
new file mode 100644
index 0000000000000000000000000000000000000000..6159e18f3562bb9fb267d75fdd967db0c3e26b21
--- /dev/null
+++ b/base_code/linux_driver/1_SupportMoreDev/main.c
@@ -0,0 +1,25 @@
+#include <stdio.h>
+#include <unistd.h>
+#include <fcntl.h>
+#include <string.h>
+char *wbuf = "Hello World\n";
+char rbuf[128];
+int main(void)
+{
+    printf("EmbedCharDev test\n");
+    //打开文件
+    int fd = open("/dev/chrdev", O_RDWR);
+    //写入数据
+    write(fd, wbuf, strlen(wbuf));
+    //写入完毕，关闭文件
+    close(fd);
+    //打开文件
+     fd = open("/dev/chrdev", O_RDWR);
+    //读取文件内容
+    read(fd, rbuf, 128);
+    //打印读取的内容
+    printf("The content : %s", rbuf);
+    //读取完毕，关闭文件
+    close(fd);
+    return 0;
+}
\ No newline at end of file
diff --git a/base_code/linux_driver/2_SupportMoreDev/Makefile b/base_code/linux_driver/2_SupportMoreDev/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..409daf5259b498a65b9b30a8f201aac73ecfb988
--- /dev/null
+++ b/base_code/linux_driver/2_SupportMoreDev/Makefile
@@ -0,0 +1,10 @@
+KERNEL_DIR=/home/embedfire/module/linux-imx
+
+obj-m := chrdev.o
+
+all:
+	$(MAKE) -C $(KERNEL_DIR) M=$(CURDIR) modules
+	
+.PHONY:clean
+clean:
+	$(MAKE) -C $(KERNEL_DIR) M=$(CURDIR) clean
\ No newline at end of file
diff --git a/base_code/linux_driver/2_SupportMoreDev/chrdev.c b/base_code/linux_driver/2_SupportMoreDev/chrdev.c
new file mode 100644
index 0000000000000000000000000000000000000000..16254646e505081ff4242ddce77fd17f7931ace0
--- /dev/null
+++ b/base_code/linux_driver/2_SupportMoreDev/chrdev.c
@@ -0,0 +1,130 @@
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/cdev.h>
+#include <linux/fs.h>
+#include <linux/uaccess.h>
+
+#define DEV_NAME            "EmbedCharDev"
+#define DEV_CNT                 (2)
+#define BUFF_SIZE               128
+//定义字符设备的设备号
+static dev_t devno;
+
+//虚拟字符设备
+struct chr_dev{
+    struct cdev dev;
+    char vbuf[BUFF_SIZE];
+};
+//字符设备1
+static struct chr_dev vcdev1;
+//字符设备2
+static struct chr_dev vcdev2;
+
+static int chr_dev_open(struct inode *inode, struct file *filp);
+static int chr_dev_release(struct inode *inode, struct file *filp);
+static ssize_t chr_dev_write(struct file *filp, const char __user * buf, size_t count, loff_t *ppos);
+static ssize_t chr_dev_read(struct file *filp, char __user * buf, size_t count, loff_t *ppos);
+
+static struct file_operations chr_dev_fops = {
+    .owner = THIS_MODULE,
+    .open = chr_dev_open,
+    .release = chr_dev_release,
+    .write = chr_dev_write,
+    .read = chr_dev_read,
+};
+static int chr_dev_open(struct inode *inode, struct file *filp)
+{
+    printk("open\n");
+    filp->private_data = container_of(inode->i_cdev, struct chr_dev, dev);
+    return 0;
+}
+
+static int chr_dev_release(struct inode *inode, struct file *filp)
+{
+    printk("\nrelease\n");
+    return 0;
+}
+
+static ssize_t chr_dev_write(struct file *filp, const char __user * buf, size_t count, loff_t *ppos)
+{
+    unsigned long p = *ppos;
+    int ret;
+    //获取文件的私有数据
+    struct chr_dev *dev = filp->private_data;
+    char *vbuf = dev->vbuf;
+
+    int tmp = count ;
+    if(p > BUFF_SIZE)
+        return 0;
+    if(tmp > BUFF_SIZE - p)
+        tmp = BUFF_SIZE - p;
+    ret = copy_from_user(vbuf, buf, tmp);
+    *ppos += tmp;
+    return tmp;
+}
+
+static ssize_t chr_dev_read(struct file *filp, char __user * buf, size_t count, loff_t *ppos)
+{
+    unsigned long p = *ppos;
+    int ret;
+    int tmp = count ;
+    //获取文件的私有数据
+    struct chr_dev *dev = filp->private_data;
+    char *vbuf = dev->vbuf;
+    if(p >= BUFF_SIZE)
+        return 0;
+    if(tmp > BUFF_SIZE - p)
+        tmp = BUFF_SIZE - p;
+    ret = copy_to_user(buf, vbuf+p, tmp);
+    *ppos +=tmp;
+    return tmp;
+}
+
+
+static int __init chrdev_init(void)
+{
+    int ret;
+    printk("chrdev init\n");
+    ret = alloc_chrdev_region(&devno, 0, DEV_CNT,  DEV_NAME);
+    if(ret < 0)
+        goto alloc_err;
+
+    //关联第一个设备：vdev1
+    cdev_init(&vcdev1.dev, &chr_dev_fops);
+    ret = cdev_add(&vcdev1.dev, devno+0, 1);
+    if(ret < 0){
+        printk("fail to add vcdev1 ");
+        goto add_err1;
+    }
+    //关联第二个设备：vdev2
+    cdev_init(&vcdev2.dev, &chr_dev_fops);
+    ret = cdev_add(&vcdev2.dev, devno+1, 1);
+    if(ret < 0){
+        printk("fail to add vcdev2 ");
+        goto add_err2;
+    }
+    return 0;
+add_err2:
+    cdev_del(&(vcdev1.dev));
+add_err1:
+    unregister_chrdev_region(devno, DEV_CNT);
+alloc_err:
+    return ret;
+
+}
+
+module_init(chrdev_init);
+
+
+
+static void __exit chrdev_exit(void)
+{
+    printk("chrdev exit\n");
+    unregister_chrdev_region(devno, DEV_CNT);
+    cdev_del(&(vcdev1.dev));
+    cdev_del(&(vcdev2.dev));
+}
+module_exit(chrdev_exit);
+
+
+MODULE_LICENSE("GPL");
diff --git a/base_code/linux_driver/EmbedCharDev/Makefile b/base_code/linux_driver/EmbedCharDev/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..409daf5259b498a65b9b30a8f201aac73ecfb988
--- /dev/null
+++ b/base_code/linux_driver/EmbedCharDev/Makefile
@@ -0,0 +1,10 @@
+KERNEL_DIR=/home/embedfire/module/linux-imx
+
+obj-m := chrdev.o
+
+all:
+	$(MAKE) -C $(KERNEL_DIR) M=$(CURDIR) modules
+	
+.PHONY:clean
+clean:
+	$(MAKE) -C $(KERNEL_DIR) M=$(CURDIR) clean
\ No newline at end of file
diff --git a/base_code/linux_driver/EmbedCharDev/chrdev.c b/base_code/linux_driver/EmbedCharDev/chrdev.c
new file mode 100644
index 0000000000000000000000000000000000000000..c3f398183dcb5d42a8b2cb1c71359943922ec95e
--- /dev/null
+++ b/base_code/linux_driver/EmbedCharDev/chrdev.c
@@ -0,0 +1,114 @@
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/fs.h>
+#include <linux/cdev.h>
+#include <linux/uaccess.h>
+#define DEV_NAME            "EmbedCharDev"
+#define DEV_CNT                 (1)
+#define BUFF_SIZE               128
+//定义字符设备的设备号
+static dev_t devno;
+//定义字符设备结构体chr_dev
+static struct cdev chr_dev;
+//数据缓冲区
+static char vbuf[BUFF_SIZE];
+static int chr_dev_open(struct inode *inode, struct file *filp);
+static int chr_dev_release(struct inode *inode, struct file *filp);
+static ssize_t chr_dev_write(struct file *filp, const char __user * buf, size_t count, loff_t *ppos);
+static ssize_t chr_dev_read(struct file *filp, char __user * buf, size_t count, loff_t *ppos);
+static struct file_operations  chr_dev_fops = 
+{
+    .owner = THIS_MODULE,
+    .open = chr_dev_open,
+    .release = chr_dev_release,
+    .write = chr_dev_write,
+    .read = chr_dev_read,
+};
+
+static int chr_dev_open(struct inode *inode, struct file *filp)
+{
+    printk("\nopen\n");
+    return 0;
+}
+
+static int chr_dev_release(struct inode *inode, struct file *filp)
+{
+    printk("\nrelease\n");
+    return 0;
+}
+
+static ssize_t chr_dev_write(struct file *filp, const char __user * buf, size_t count, loff_t *ppos)
+{
+    unsigned long p = *ppos;
+    int ret;
+    int tmp = count ;
+    if(p > BUFF_SIZE)
+        return 0;
+    if(tmp > BUFF_SIZE - p)
+        tmp = BUFF_SIZE - p;
+    ret = copy_from_user(vbuf, buf, tmp);
+    *ppos += tmp;
+    return tmp;
+}
+
+static ssize_t chr_dev_read(struct file *filp, char __user * buf, size_t count, loff_t *ppos)
+{
+    unsigned long p = *ppos;
+    int ret;
+    int tmp = count ;
+    static int i = 0;
+    i++;
+    if(p >= BUFF_SIZE)
+        return 0;
+    if(tmp > BUFF_SIZE - p)
+        tmp = BUFF_SIZE - p;
+    ret = copy_to_user(buf, vbuf+p, tmp);
+    *ppos +=tmp;
+    return tmp;
+}
+
+static int __init chrdev_init(void)
+{
+    int ret = 0;
+    printk("chrdev init\n");
+    //第一步
+    //采用动态分配的方式，获取设备编号，次设备号为0，
+    //设备名称为EmbedCharDev，可通过命令cat  /proc/devices查看
+    //DEV_CNT为1，当前只申请一个设备编号
+    ret = alloc_chrdev_region(&devno, 0, DEV_CNT, DEV_NAME);
+    if(ret < 0){
+        printk("fail to alloc devno\n");
+        goto alloc_err;
+    }
+    //第二步
+    //关联字符设备结构体cdev与文件操作结构体file_operations
+    cdev_init(&chr_dev, &chr_dev_fops);
+    //第三步
+    //添加设备至cdev_map散列表中
+    ret = cdev_add(&chr_dev, devno, DEV_CNT);
+    if(ret < 0)
+    {
+        printk("fail to add cdev\n");
+        goto add_err;
+    }
+    return 0;
+
+add_err:
+    //添加设备失败时，需要注销设备号
+    unregister_chrdev_region(devno, DEV_CNT);
+alloc_err:
+    return ret;
+}
+module_init(chrdev_init);
+
+static void __exit chrdev_exit(void)
+{
+    printk("chrdev exit\n");
+    unregister_chrdev_region(devno, DEV_CNT);
+
+    cdev_del(&chr_dev);
+}
+module_exit(chrdev_exit);
+
+MODULE_LICENSE("GPL");
+
diff --git a/base_code/linux_driver/EmbedCharDev/main.c b/base_code/linux_driver/EmbedCharDev/main.c
new file mode 100644
index 0000000000000000000000000000000000000000..6159e18f3562bb9fb267d75fdd967db0c3e26b21
--- /dev/null
+++ b/base_code/linux_driver/EmbedCharDev/main.c
@@ -0,0 +1,25 @@
+#include <stdio.h>
+#include <unistd.h>
+#include <fcntl.h>
+#include <string.h>
+char *wbuf = "Hello World\n";
+char rbuf[128];
+int main(void)
+{
+    printf("EmbedCharDev test\n");
+    //打开文件
+    int fd = open("/dev/chrdev", O_RDWR);
+    //写入数据
+    write(fd, wbuf, strlen(wbuf));
+    //写入完毕，关闭文件
+    close(fd);
+    //打开文件
+     fd = open("/dev/chrdev", O_RDWR);
+    //读取文件内容
+    read(fd, rbuf, 128);
+    //打印读取的内容
+    printf("The content : %s", rbuf);
+    //读取完毕，关闭文件
+    close(fd);
+    return 0;
+}
\ No newline at end of file
diff --git a/base_code/linux_driver/I2c_MPU6050/Makefile b/base_code/linux_driver/I2c_MPU6050/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..8ab0912f8bbe23ea3248846f23cbe2ad2f3c416b
--- /dev/null
+++ b/base_code/linux_driver/I2c_MPU6050/Makefile
@@ -0,0 +1,11 @@
+#KERNEL_DIR = /home/new_kernel2/ebf-buster-linux
+KERNEL_DIR = /home/gulun/fire/kernel/ebf-buster-linux
+
+obj-m := i2c_mpu6050.o
+
+all:
+	$(MAKE) EXTRA_CFLAGS=-fno-pic -C $(KERNEL_DIR) M=$(CURDIR) modules
+	
+.PHONY:clean
+clean:
+	$(MAKE)  -C $(KERNEL_DIR) M=$(CURDIR) clean
diff --git a/base_code/linux_driver/I2c_MPU6050/i2c_mpu6050.c b/base_code/linux_driver/I2c_MPU6050/i2c_mpu6050.c
new file mode 100644
index 0000000000000000000000000000000000000000..216b69919b80b40d3a29d795d97817629ef25a0d
--- /dev/null
+++ b/base_code/linux_driver/I2c_MPU6050/i2c_mpu6050.c
@@ -0,0 +1,315 @@
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/fs.h>
+#include <linux/cdev.h>
+#include <linux/uaccess.h>
+#include <linux/i2c.h>
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/delay.h>
+#include <linux/ide.h>
+#include <linux/errno.h>
+#include <linux/gpio.h>
+#include <asm/mach/map.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_gpio.h>
+#include <asm/io.h>
+#include <linux/device.h>
+
+#include <linux/platform_device.h>
+
+#include "i2c_mpu6050.h"
+
+/*------------------字符设备内容----------------------*/
+#define DEV_NAME "I2C1_mpu6050"
+#define DEV_CNT (1)
+
+/*定义 led 资源结构体，保存获取得到的节点信息以及转换后的虚拟寄存器地址*/
+static dev_t mpu6050_devno;				 //定义字符设备的设备号
+static struct cdev mpu6050_chr_dev;		 //定义字符设备结构体chr_dev
+struct class *class_mpu6050;			 //保存创建的类
+struct device *device_mpu6050;			 // 保存创建的设备
+struct device_node *mpu6050_device_node; //rgb_led的设备树节点结构体
+
+/*------------------IIC设备内容----------------------*/
+struct i2c_client *mpu6050_client = NULL; //保存mpu6050设备对应的i2c_client结构体，匹配成功后由.prob函数带回。
+
+/*通过i2c 向mpu6050写入数据
+*mpu6050_client：mpu6050的i2c_client结构体。
+*address, 数据要写入的地址，
+*data, 要写入的数据
+*返回值，错误，-1。成功，0  
+*/
+static int i2c_write_mpu6050(struct i2c_client *mpu6050_client, u8 address, u8 data)
+{
+	int error = 0;
+	u8 write_data[2];
+	struct i2c_msg send_msg; //要发送的数据结构体
+
+	/*设置要发送的数据*/
+	write_data[0] = address;
+	write_data[1] = data;
+
+	/*发送 iic要写入的地址 reg*/
+	send_msg.addr = mpu6050_client->addr; //mpu6050在 iic 总线上的地址
+	send_msg.flags = 0;					  //标记为发送数据
+	send_msg.buf = write_data;			  //写入的首地址
+	send_msg.len = 2;					  //reg长度
+
+	/*执行发送*/
+	error = i2c_transfer(mpu6050_client->adapter, &send_msg, 1);
+	if (error != 1)
+	{
+		printk(KERN_DEBUG "\n i2c_transfer error \n");
+		return -1;
+	}
+	return 0;
+}
+
+/*通过i2c 向mpu6050写入数据
+*mpu6050_client：mpu6050的i2c_client结构体。
+*address, 要读取的地址，
+*data，保存读取得到的数据
+*length，读长度
+*返回值，错误，-1。成功，0
+*/
+static int i2c_read_mpu6050(struct i2c_client *mpu6050_client, u8 address, void *data, u32 length)
+{
+	int error = 0;
+	u8 address_data = address;
+	struct i2c_msg mpu6050_msg[2];
+	/*设置读取位置msg*/
+	mpu6050_msg[0].addr = mpu6050_client->addr; //mpu6050在 iic 总线上的地址
+	mpu6050_msg[0].flags = 0;					//标记为发送数据
+	mpu6050_msg[0].buf = &address_data;			//写入的首地址
+	mpu6050_msg[0].len = 1;						//写入长度
+
+	/*设置读取位置msg*/
+	mpu6050_msg[1].addr = mpu6050_client->addr; //mpu6050在 iic 总线上的地址
+	mpu6050_msg[1].flags = I2C_M_RD;			//标记为读取数据
+	mpu6050_msg[1].buf = data;					//读取得到的数据保存位置
+	mpu6050_msg[1].len = length;				//读取长度
+
+	error = i2c_transfer(mpu6050_client->adapter, mpu6050_msg, 2);
+
+	if (error != 2)
+	{
+		printk(KERN_DEBUG "\n i2c_read_mpu6050 error \n");
+		return -1;
+	}
+	return 0;
+}
+
+/*初始化i2c
+*返回值，成功，返回0。失败，返回 -1
+*/
+static int mpu6050_init(void)
+{
+	int error = 0;
+	/*配置mpu6050*/
+	error += i2c_write_mpu6050(mpu6050_client, PWR_MGMT_1, 0X00);
+	error += i2c_write_mpu6050(mpu6050_client, SMPLRT_DIV, 0X07);
+	error += i2c_write_mpu6050(mpu6050_client, CONFIG, 0X06);
+	error += i2c_write_mpu6050(mpu6050_client, ACCEL_CONFIG, 0X01);
+
+	if (error < 0)
+	{
+		/*初始化错误*/
+		printk(KERN_DEBUG "\n mpu6050_init error \n");
+		return -1;
+	}
+	return 0;
+}
+
+/*字符设备操作函数集，open函数实现*/
+static int mpu6050_open(struct inode *inode, struct file *filp)
+{
+	// printk("\n mpu6050_open \n");
+
+	/*向 mpu6050 发送配置数据，让mpu6050处于正常工作状态*/
+	mpu6050_init();
+	return 0;
+}
+
+/*字符设备操作函数集，.read函数实现*/
+static ssize_t mpu6050_read(struct file *filp, char __user *buf, size_t cnt, loff_t *off)
+{
+	char data_H;
+	char data_L;
+	int error;
+	short mpu6050_result[6]; //保存mpu6050转换得到的原始数据
+
+	// printk("\n mpu6050_read \n");
+	
+	i2c_read_mpu6050(mpu6050_client, ACCEL_XOUT_H, &data_H, 1);
+	i2c_read_mpu6050(mpu6050_client, ACCEL_XOUT_L, &data_L, 1);
+	mpu6050_result[0] = data_H << 8;
+	mpu6050_result[0] += data_L;
+
+	i2c_read_mpu6050(mpu6050_client, ACCEL_YOUT_H, &data_H, 1);
+	i2c_read_mpu6050(mpu6050_client, ACCEL_YOUT_L, &data_L, 1);
+	mpu6050_result[1] = data_H << 8;
+    mpu6050_result[1] += data_L;
+
+	i2c_read_mpu6050(mpu6050_client, ACCEL_ZOUT_H, &data_H, 1);
+	i2c_read_mpu6050(mpu6050_client, ACCEL_ZOUT_L, &data_L, 1);
+	mpu6050_result[2] = data_H << 8;
+	mpu6050_result[2] += data_L;
+
+	i2c_read_mpu6050(mpu6050_client, GYRO_XOUT_H, &data_H, 1);
+	i2c_read_mpu6050(mpu6050_client, GYRO_XOUT_L, &data_L, 1);
+	mpu6050_result[3] = data_H << 8;
+	mpu6050_result[3] += data_L;
+
+	i2c_read_mpu6050(mpu6050_client, GYRO_YOUT_H, &data_H, 1);
+	i2c_read_mpu6050(mpu6050_client, GYRO_YOUT_L, &data_L, 1);
+	mpu6050_result[4] = data_H << 8;
+	mpu6050_result[4] += data_L;
+
+	i2c_read_mpu6050(mpu6050_client, GYRO_ZOUT_H, &data_H, 1);
+	i2c_read_mpu6050(mpu6050_client, GYRO_ZOUT_L, &data_L, 1);
+	mpu6050_result[5] = data_H << 8;
+	mpu6050_result[5] += data_L;
+
+
+	// printk("AX=%d, AY=%d, AZ=%d \n",(int)mpu6050_result[0],(int)mpu6050_result[1],(int)mpu6050_result[2]);
+	// printk("GX=%d, GY=%d, GZ=%d \n \n",(int)mpu6050_result[3],(int)mpu6050_result[4],(int)mpu6050_result[5]);
+
+	/*将读取得到的数据拷贝到用户空间*/
+	error = copy_to_user(buf, mpu6050_result, cnt);
+
+	if(error != 0)
+	{
+		printk("copy_to_user error!");
+		return -1;
+	}
+	return 0;
+}
+
+/*字符设备操作函数集，.release函数实现*/
+static int mpu6050_release(struct inode *inode, struct file *filp)
+{
+	// printk("\n mpu6050_release \n");
+	
+	/*向mpu6050发送命令，使mpu6050进入关机状态*/
+	return 0;
+}
+
+/*字符设备操作函数集*/
+static struct file_operations mpu6050_chr_dev_fops =
+	{
+		.owner = THIS_MODULE,
+		.open = mpu6050_open,
+		.read = mpu6050_read,
+		.release = mpu6050_release,
+};
+
+/*----------------平台驱动函数集-----------------*/
+static int mpu6050_probe(struct i2c_client *client, const struct i2c_device_id *id)
+{
+
+	int ret = -1; //保存错误状态码
+
+	printk(KERN_EMERG "\t  match successed  \n");
+	/*---------------------注册 字符设备部分-----------------*/
+
+	//采用动态分配的方式，获取设备编号，次设备号为0，
+	//设备名称为rgb-leds，可通过命令cat  /proc/devices查看
+	//DEV_CNT为1，当前只申请一个设备编号
+	ret = alloc_chrdev_region(&mpu6050_devno, 0, DEV_CNT, DEV_NAME);
+	if (ret < 0)
+	{
+		printk("fail to alloc mpu6050_devno\n");
+		goto alloc_err;
+	}
+
+	//关联字符设备结构体cdev与文件操作结构体file_operations
+	mpu6050_chr_dev.owner = THIS_MODULE;
+	cdev_init(&mpu6050_chr_dev, &mpu6050_chr_dev_fops);
+
+	// 添加设备至cdev_map散列表中
+	ret = cdev_add(&mpu6050_chr_dev, mpu6050_devno, DEV_CNT);
+	if (ret < 0)
+	{
+		printk("fail to add cdev\n");
+		goto add_err;
+	}
+
+	/*创建类 */
+	class_mpu6050 = class_create(THIS_MODULE, DEV_NAME);
+
+	/*创建设备 DEV_NAME 指定设备名，*/
+	device_mpu6050 = device_create(class_mpu6050, NULL, mpu6050_devno, NULL, DEV_NAME);
+	mpu6050_client = client;
+	return 0;
+
+add_err:
+	// 添加设备失败时，需要注销设备号
+	unregister_chrdev_region(mpu6050_devno, DEV_CNT);
+	printk("\n error! \n");
+alloc_err:
+
+	return -1;
+}
+
+
+static int mpu6050_remove(struct i2c_client *client)
+{
+	/*删除设备*/
+	device_destroy(class_mpu6050, mpu6050_devno);	  //清除设备
+	class_destroy(class_mpu6050);					  //清除类
+	cdev_del(&mpu6050_chr_dev);						  //清除设备号
+	unregister_chrdev_region(mpu6050_devno, DEV_CNT); //取消注册字符设备
+	return 0;
+}
+
+
+
+/*定义ID 匹配表*/
+static const struct i2c_device_id gtp_device_id[] = {
+	{"fire,i2c_mpu6050", 0},
+	{}};
+
+/*定义设备树匹配表*/
+static const struct of_device_id mpu6050_of_match_table[] = {
+	{.compatible = "fire,i2c_mpu6050"},
+	{/* sentinel */}};
+
+/*定义i2c总线设备结构体*/
+struct i2c_driver mpu6050_driver = {
+	.probe = mpu6050_probe,
+	.remove = mpu6050_remove,
+	.id_table = gtp_device_id,
+	.driver = {
+		.name = "fire,i2c_mpu6050",
+		.owner = THIS_MODULE,
+		.of_match_table = mpu6050_of_match_table,
+	},
+};
+
+/*
+*驱动初始化函数
+*/
+static int __init mpu6050_driver_init(void)
+{
+	int ret;
+	pr_info("mpu6050_driver_init\n");
+	ret = i2c_add_driver(&mpu6050_driver);
+	return ret;
+}
+
+/*
+*驱动注销函数
+*/
+static void __exit mpu6050_driver_exit(void)
+{
+	pr_info("mpu6050_driver_exit\n");
+	i2c_del_driver(&mpu6050_driver);
+}
+
+module_init(mpu6050_driver_init);
+module_exit(mpu6050_driver_exit);
+
+MODULE_LICENSE("GPL");
diff --git a/base_code/linux_driver/I2c_MPU6050/i2c_mpu6050.h b/base_code/linux_driver/I2c_MPU6050/i2c_mpu6050.h
new file mode 100644
index 0000000000000000000000000000000000000000..f8f5d75f725cccc2f73badc0c26bdaa2e09d3262
--- /dev/null
+++ b/base_code/linux_driver/I2c_MPU6050/i2c_mpu6050.h
@@ -0,0 +1,35 @@
+
+#ifndef I2C_MPU6050_H
+#define I2C_MPU6050_H
+
+
+//宏定义
+#define SMPLRT_DIV                                  0x19
+#define CONFIG                                      0x1A
+#define GYRO_CONFIG                                 0x1B
+#define ACCEL_CONFIG                                0x1C
+#define ACCEL_XOUT_H                                0x3B
+#define ACCEL_XOUT_L                                0x3C
+#define ACCEL_YOUT_H                                0x3D
+#define ACCEL_YOUT_L                                0x3E
+#define ACCEL_ZOUT_H                                0x3F
+#define ACCEL_ZOUT_L                                0x40
+#define TEMP_OUT_H                                  0x41
+#define TEMP_OUT_L                                  0x42
+#define GYRO_XOUT_H                                 0x43
+#define GYRO_XOUT_L                                 0x44
+#define GYRO_YOUT_H                                 0x45
+#define GYRO_YOUT_L                                 0x46
+#define GYRO_ZOUT_H                                 0x47
+#define GYRO_ZOUT_L                                 0x48
+#define PWR_MGMT_1                                  0x6B
+#define WHO_AM_I                                    0x75
+#define SlaveAddress                                0xD0
+#define Address                                     0x68                  //MPU6050地址
+#define I2C_RETRIES                                 0x0701
+#define I2C_TIMEOUT                                 0x0702
+#define I2C_SLAVE                                   0x0703       //IIC从器件的地址设置
+#define I2C_BUS_MODE                                0x0780
+
+
+#endif
\ No newline at end of file
diff --git a/base_code/linux_driver/I2c_MPU6050/imx-fire-mpu6050-overlay.dts b/base_code/linux_driver/I2c_MPU6050/imx-fire-mpu6050-overlay.dts
new file mode 100644
index 0000000000000000000000000000000000000000..9355e70343adab2a4dafaa9b72fdc516af66208f
--- /dev/null
+++ b/base_code/linux_driver/I2c_MPU6050/imx-fire-mpu6050-overlay.dts
@@ -0,0 +1,43 @@
+/*
+ * Copyright (C) 2019 - All Rights Reserved by 
+ * filename : imx-fire-mpu6050-overlay.dts
+ * brief : Device Tree overlay for EBF6ull Pro mpu6050 device
+ * author : embedfire
+ * date : 2019-11-26
+ * version : A001
+ */
+
+ /dts-v1/;
+ /plugin/;
+#include "imx6ul-pinfunc.h"
+
+ / {
+     fragment@0 {
+         target = <&i2c1>;
+         __overlay__ { 
+            clock-frequency = <100000>;
+	        pinctrl-names = "default";
+	        pinctrl-0 = <&pinctrl_i2c1>;
+	        status = "okay";
+
+	        i2c_mpu6050@68 {
+	        	compatible = "fire,i2c_mpu6050";
+	        	reg = <0x68>;
+	        	status = "okay";
+	        };        
+         };
+     };
+
+     fragment@1 {
+         target = <&iomuxc>;
+         __overlay__ { 
+        pinctrl_i2c1: i2c1grp {
+        		fsl,pins = <
+        			MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0
+        			MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0
+        		>;
+        	};     
+         };
+     };
+
+ };
diff --git a/base_code/linux_driver/I2c_MPU6050/test_app.c b/base_code/linux_driver/I2c_MPU6050/test_app.c
new file mode 100644
index 0000000000000000000000000000000000000000..790a388cff11bb6cc542ed678cd0f171dcbce36b
--- /dev/null
+++ b/base_code/linux_driver/I2c_MPU6050/test_app.c
@@ -0,0 +1,41 @@
+#include <stdio.h>
+#include <unistd.h>
+#include <fcntl.h>
+#include <string.h>
+#include <stdlib.h>
+int main(int argc, char *argv[])
+{
+
+    short resive_data[6];  //保存收到的 mpu6050转换结果数据，依次为 AX(x轴角度), AY, AZ 。GX(x轴加速度), GY ,GZ
+
+    /*打开文件*/
+    int fd = open("/dev/I2C1_mpu6050", O_RDWR);
+    if(fd < 0)
+    {
+		printf("open file : %s failed !\n", argv[0]);
+		return -1;
+	}
+
+    /*读取数据*/
+    int error = read(fd,resive_data,12);
+    if(error < 0)
+    {
+        printf("write file error! \n");
+        close(fd);
+        /*判断是否关闭成功*/
+    }
+
+    /*打印数据*/
+    printf("AX=%d, AY=%d, AZ=%d ",(int)resive_data[0],(int)resive_data[1],(int)resive_data[2]);
+	printf("    GX=%d, GY=%d, GZ=%d \n \n",(int)resive_data[3],(int)resive_data[4],(int)resive_data[5]);
+
+
+    /*关闭文件*/
+    error = close(fd);
+    if(error < 0)
+    {
+        printf("close file error! \n");
+    }
+    
+    return 0;
+}
\ No newline at end of file
diff --git a/base_code/linux_driver/concurrency/atomic/Makefile b/base_code/linux_driver/concurrency/atomic/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..b900ab9f19f700fc83bd46c8379f7fe4ad7e811b
--- /dev/null
+++ b/base_code/linux_driver/concurrency/atomic/Makefile
@@ -0,0 +1,12 @@
+KERNEL_DIR = /home/fire2/ebf-buster-linux
+
+obj-m := led_cdev.o
+
+all:
+	$(MAKE) -C $(KERNEL_DIR) M=$(CURDIR) modules
+	
+.PHONY:clean
+clean:
+	$(MAKE) -C $(KERNEL_DIR) M=$(CURDIR) clean
+
+	echo 1 >/dev/led_chrdev0
diff --git a/base_code/linux_driver/concurrency/atomic/led_cdev.c b/base_code/linux_driver/concurrency/atomic/led_cdev.c
new file mode 100644
index 0000000000000000000000000000000000000000..ef589786cc7457089195d616e70f89ec85784d5c
--- /dev/null
+++ b/base_code/linux_driver/concurrency/atomic/led_cdev.c
@@ -0,0 +1,217 @@
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/cdev.h>
+#include <linux/fs.h>
+#include <linux/uaccess.h>
+#include <linux/io.h>
+
+#define DEV_NAME            "led_chrdev"
+#define DEV_CNT                 (3)
+
+static dev_t devno;
+struct class *led_chrdev_class;
+
+/*自定义led_chrdev结构体，保存有字符设备结构体cdev
+ *和led 相关寄存器地址。
+*/
+struct led_chrdev {
+	struct cdev dev;
+	unsigned int __iomem *va_dr;
+	unsigned int __iomem *va_gdir;
+	unsigned int __iomem *va_iomuxc_mux;
+	unsigned int __iomem *va_ccm_ccgrx;
+	unsigned int __iomem *va_iomux_pad;
+
+	unsigned long pa_dr;
+	unsigned long pa_gdir;
+	unsigned long pa_iomuxc_mux;
+	unsigned long pa_ccm_ccgrx;
+	unsigned long pa_iomux_pad;
+
+	unsigned int led_pin;
+	unsigned int clock_offset;
+};
+
+
+static atomic_t test_atomic = ATOMIC_INIT(1);
+
+static int led_chrdev_open(struct inode *inode, struct file *filp)
+{
+
+	unsigned int val = 0;
+	struct led_chrdev *led_cdev =
+	    (struct led_chrdev *)container_of(inode->i_cdev, struct led_chrdev,
+					      dev);
+	filp->private_data =
+	    container_of(inode->i_cdev, struct led_chrdev, dev);
+
+
+	if(atomic_read(&test_atomic))
+	{
+		atomic_set(&test_atomic,0);
+	}
+    else
+    {
+		printk("\n driver on using!  open failed !!!\n");
+		return - EBUSY;
+    }
+	
+	printk("open\n");
+
+	led_cdev->va_dr = ioremap(led_cdev->pa_dr, 4);
+	led_cdev->va_gdir = ioremap(led_cdev->pa_gdir, 4);
+	led_cdev->va_iomuxc_mux = ioremap(led_cdev->pa_iomuxc_mux, 4);
+	led_cdev->va_ccm_ccgrx = ioremap(led_cdev->pa_ccm_ccgrx, 4);
+	led_cdev->va_iomux_pad = ioremap(led_cdev->pa_iomux_pad, 4);
+
+	val = ioread32(led_cdev->va_ccm_ccgrx);
+	val &= ~(3 << led_cdev->clock_offset);
+	val |= (3 << led_cdev->clock_offset);
+	iowrite32(val, led_cdev->va_ccm_ccgrx);
+
+	iowrite32(5, led_cdev->va_iomuxc_mux);
+
+	iowrite32(0x1F838, led_cdev->va_iomux_pad);
+
+	val = ioread32(led_cdev->va_gdir);
+	val &= ~(1 << led_cdev->led_pin);
+	val |= (1 << led_cdev->led_pin);
+	iowrite32(val, led_cdev->va_gdir);
+
+	val = ioread32(led_cdev->va_dr);
+	val |= (0x01 << led_cdev->led_pin);
+	iowrite32(val, led_cdev->va_dr);
+
+	return 0;
+}
+
+static int led_chrdev_release(struct inode *inode, struct file *filp)
+{
+	struct led_chrdev *led_cdev =
+	    (struct led_chrdev *)container_of(inode->i_cdev, struct led_chrdev,
+					      dev);
+
+	iounmap(led_cdev->va_dr);
+	iounmap(led_cdev->va_gdir);
+	iounmap(led_cdev->va_iomuxc_mux);
+	iounmap(led_cdev->va_ccm_ccgrx);
+	iounmap(led_cdev->va_iomux_pad);
+
+    atomic_set(&test_atomic,1);
+	printk(" \n finished  !!!\n");
+
+	return 0;
+}
+
+
+
+
+static ssize_t led_chrdev_write(struct file *filp, const char __user * buf,
+				size_t count, loff_t * ppos)
+{
+	unsigned long val = 0;
+	unsigned long ret = 0;
+
+	int tmp = count;
+
+	kstrtoul_from_user(buf, tmp, 10, &ret);
+	struct led_chrdev *led_cdev = (struct led_chrdev *)filp->private_data;
+
+	val = ioread32(led_cdev->va_dr);
+	if (ret == 0)
+	{
+		val &= ~(0x01 << led_cdev->led_pin);
+		printk("red led on\n");
+	}
+	else
+	{
+		val |= (0x01 << led_cdev->led_pin);
+		printk("red led off\n");
+	}
+		
+
+	iowrite32(val, led_cdev->va_dr);
+	*ppos += tmp;
+	return tmp;
+}
+
+static struct file_operations led_chrdev_fops = {
+	.owner = THIS_MODULE,
+	.open = led_chrdev_open,
+	.release = led_chrdev_release,
+	.write = led_chrdev_write,
+};
+
+static struct led_chrdev led_cdev[DEV_CNT] = {
+	{.pa_dr = 0x0209C000,.pa_gdir = 0x0209C004,.pa_iomuxc_mux =
+	 0x20E006C,.pa_ccm_ccgrx = 0x20C406C,.pa_iomux_pad =
+	 0x20E02F8,.led_pin = 4,.clock_offset = 26},
+	{.pa_dr = 0x20A8000,.pa_gdir = 0x20A8004,.pa_iomuxc_mux =
+	 0x20E01E0,.pa_ccm_ccgrx = 0x20C4074,.pa_iomux_pad =
+	 0x20E046C,.led_pin = 20,.clock_offset = 12},
+	{.pa_dr = 0x20A8000,.pa_gdir = 0x20A8004,.pa_iomuxc_mux =
+	 0x20E01DC,.pa_ccm_ccgrx = 0x20C4074,.pa_iomux_pad =
+	 0x20E0468,.led_pin = 19,.clock_offset = 12},
+};
+
+
+/*驱动入口*/
+static __init int led_chrdev_init(void)
+{
+	int i = 0;
+	dev_t cur_dev;
+	printk("led chrdev init\n");
+
+	/*动态申请设备号*/
+	alloc_chrdev_region(&devno, 0, DEV_CNT, DEV_NAME);
+
+	/*创建“字符设备”类*/
+	led_chrdev_class = class_create(THIS_MODULE, "led_chrdev");
+
+	for (; i < DEV_CNT; i++) {
+		/*初始化字符设备结构体 cdev(指定操作函数集)*/
+		cdev_init(&led_cdev[i].dev, &led_chrdev_fops);
+		led_cdev[i].dev.owner = THIS_MODULE;
+
+		/*由主设备号和次设备号合成设备号*/
+		cur_dev = MKDEV(MAJOR(devno), MINOR(devno) + i);
+
+		/*注册字符设备*/
+		cdev_add(&led_cdev[i].dev, cur_dev, 1);
+
+		/*创建字符设备节点*/
+		device_create(led_chrdev_class, NULL, cur_dev, NULL,
+			      DEV_NAME "%d", i);
+	}
+
+	return 0;
+}
+module_init(led_chrdev_init);
+
+
+/*驱动出口*/
+static __exit void led_chrdev_exit(void)
+{
+	int i;
+	dev_t cur_dev;
+	printk("led chrdev exit\n");
+
+	for (i = 0; i < DEV_CNT; i++) {
+		/*由主设备号和次设备号拼接成设备号*/
+		cur_dev = MKDEV(MAJOR(devno), MINOR(devno) + i);
+
+		/*移除字符设备节点*/
+		device_destroy(led_chrdev_class, cur_dev);
+
+		cdev_del(&led_cdev[i].dev);
+
+	}
+	unregister_chrdev_region(devno, DEV_CNT);
+	class_destroy(led_chrdev_class);
+
+}
+
+module_exit(led_chrdev_exit);
+
+MODULE_AUTHOR("embedfire");
+MODULE_LICENSE("GPL");
diff --git a/base_code/linux_driver/concurrency/atomic/main.c b/base_code/linux_driver/concurrency/atomic/main.c
new file mode 100644
index 0000000000000000000000000000000000000000..7faeb6796135bbf30d28ed6059972a61c53ae574
--- /dev/null
+++ b/base_code/linux_driver/concurrency/atomic/main.c
@@ -0,0 +1,42 @@
+#include <stdio.h>
+#include <unistd.h>
+#include <fcntl.h>
+#include <string.h>
+int main(int argc, char *argv[])
+{
+    /*判断输入的命令是否合法*/
+    if(argc != 2)
+    {
+        printf(" commend error ! \n");
+        return -1;
+    }
+
+    /*打开文件*/
+    int fd = open("/dev/led_chrdev0", O_RDWR);
+    if(fd < 0)
+    {
+		printf("\n open file : /dev/led_chrdev0 failed !!!\n");
+		return -1;
+	}
+
+    /*判断命令的有效性*/
+    /*写入命令*/
+    int error = write(fd,argv[1],sizeof(argv[1]));
+    if(error < 0)
+    {
+        printf("write file error! \n");
+        close(fd);
+        /*判断是否关闭成功*/
+    }
+
+
+    sleep(15);  //休眠5秒
+
+    /*关闭文件*/
+    error = close(fd);
+    if(error < 0)
+    {
+        printf("close file error! \n");
+    }
+    return 0;
+}
\ No newline at end of file
diff --git a/base_code/linux_driver/concurrency/mutex/Makefile b/base_code/linux_driver/concurrency/mutex/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..5cd69b3e813881fa0d76b81a6edb46e840741b93
--- /dev/null
+++ b/base_code/linux_driver/concurrency/mutex/Makefile
@@ -0,0 +1,12 @@
+KERNEL_DIR = /home/fire2/ebf-buster-linux
+
+obj-m := mutex.o
+
+all:
+	$(MAKE) -C $(KERNEL_DIR) M=$(CURDIR) modules
+	
+.PHONY:clean
+clean:
+	$(MAKE) -C $(KERNEL_DIR) M=$(CURDIR) clean
+
+	echo 1 >/dev/led_chrdev0
diff --git a/base_code/linux_driver/concurrency/mutex/mutex.c b/base_code/linux_driver/concurrency/mutex/mutex.c
new file mode 100644
index 0000000000000000000000000000000000000000..f5d0134d8b3f65537177d8a0cff9546c6c9f599e
--- /dev/null
+++ b/base_code/linux_driver/concurrency/mutex/mutex.c
@@ -0,0 +1,215 @@
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/cdev.h>
+#include <linux/fs.h>
+#include <linux/uaccess.h>
+#include <linux/io.h>
+#include <linux/delay.h>
+
+#define DEV_NAME "led_chrdev"
+#define DEV_CNT (3)
+
+static dev_t devno;
+struct class *led_chrdev_class;
+
+/*定义一个自旋锁*/
+// spinlock_t s_lock;
+// struct semaphore sema_lock;
+struct mutex mu_lock;
+
+/*自定义led_chrdev结构体，保存有字符设备结构体cdev
+ *和led 相关寄存器地址。
+*/
+struct led_chrdev
+{
+	struct cdev dev;
+	unsigned int __iomem *va_dr;
+	unsigned int __iomem *va_gdir;
+	unsigned int __iomem *va_iomuxc_mux;
+	unsigned int __iomem *va_ccm_ccgrx;
+	unsigned int __iomem *va_iomux_pad;
+
+	unsigned long pa_dr;
+	unsigned long pa_gdir;
+	unsigned long pa_iomuxc_mux;
+	unsigned long pa_ccm_ccgrx;
+	unsigned long pa_iomux_pad;
+
+	unsigned int led_pin;
+	unsigned int clock_offset;
+};
+
+
+
+static int led_chrdev_open(struct inode *inode, struct file *filp)
+{
+
+	unsigned int val = 0;
+
+	struct led_chrdev *led_cdev =
+		(struct led_chrdev *)container_of(inode->i_cdev, struct led_chrdev,
+										  dev);
+	filp->private_data =
+		container_of(inode->i_cdev, struct led_chrdev, dev);
+
+	printk("open\n");
+
+	led_cdev->va_dr = ioremap(led_cdev->pa_dr, 4);
+	led_cdev->va_gdir = ioremap(led_cdev->pa_gdir, 4);
+	led_cdev->va_iomuxc_mux = ioremap(led_cdev->pa_iomuxc_mux, 4);
+	led_cdev->va_ccm_ccgrx = ioremap(led_cdev->pa_ccm_ccgrx, 4);
+	led_cdev->va_iomux_pad = ioremap(led_cdev->pa_iomux_pad, 4);
+
+	val = ioread32(led_cdev->va_ccm_ccgrx);
+	val &= ~(3 << led_cdev->clock_offset);
+	val |= (3 << led_cdev->clock_offset);
+	iowrite32(val, led_cdev->va_ccm_ccgrx);
+
+	iowrite32(5, led_cdev->va_iomuxc_mux);
+
+	iowrite32(0x1F838, led_cdev->va_iomux_pad);
+
+	val = ioread32(led_cdev->va_gdir);
+	val &= ~(1 << led_cdev->led_pin);
+	val |= (1 << led_cdev->led_pin);
+	iowrite32(val, led_cdev->va_gdir);
+
+	val = ioread32(led_cdev->va_dr);
+	val |= (0x01 << led_cdev->led_pin);
+	iowrite32(val, led_cdev->va_dr);
+
+	return 0;
+}
+
+static int led_chrdev_release(struct inode *inode, struct file *filp)
+{
+	struct led_chrdev *led_cdev =
+		(struct led_chrdev *)container_of(inode->i_cdev, struct led_chrdev,
+										  dev);
+
+	iounmap(led_cdev->va_dr);
+	iounmap(led_cdev->va_gdir);
+	iounmap(led_cdev->va_iomuxc_mux);
+	iounmap(led_cdev->va_ccm_ccgrx);
+	iounmap(led_cdev->va_iomux_pad);
+
+	printk(" \n finished  !!!\n");
+
+	return 0;
+}
+
+static ssize_t led_chrdev_write(struct file *filp, const char __user *buf,
+								size_t count, loff_t *ppos)
+{
+	unsigned long val = 0;
+	unsigned long ret = 0;
+	unsigned long i;
+
+	int tmp = count;
+
+	kstrtoul_from_user(buf, tmp, 10, &ret);
+	struct led_chrdev *led_cdev = (struct led_chrdev *)filp->private_data;
+
+	// spin_lock(&s_lock);
+	// down(&sema_lock);
+	mutex_lock(&mu_lock);
+
+	for (i = ret; i > 0; i--)
+	{
+		printk("the data is %ld \n", i);
+
+		/*点亮led 灯*/
+		val &= ~(0x01 << led_cdev->led_pin);
+		iowrite32(val, led_cdev->va_dr);
+		mdelay(100);
+
+		/*熄灭led 灯*/
+		val |= (0x01 << led_cdev->led_pin); 
+		iowrite32(val, led_cdev->va_dr);
+		mdelay(100);
+	}
+	// spin_unlock(&s_lock);
+	// up(&sema_lock);
+	mutex_unlock(&mu_lock);
+
+	*ppos += tmp;
+	return tmp;
+}
+
+static struct file_operations led_chrdev_fops = {
+	.owner = THIS_MODULE,
+	.open = led_chrdev_open,
+	.release = led_chrdev_release,
+	.write = led_chrdev_write,
+};
+
+static struct led_chrdev led_cdev[DEV_CNT] = {
+	{.pa_dr = 0x0209C000, .pa_gdir = 0x0209C004, .pa_iomuxc_mux = 0x20E006C, .pa_ccm_ccgrx = 0x20C406C, .pa_iomux_pad = 0x20E02F8, .led_pin = 4, .clock_offset = 26},
+	{.pa_dr = 0x20A8000, .pa_gdir = 0x20A8004, .pa_iomuxc_mux = 0x20E01E0, .pa_ccm_ccgrx = 0x20C4074, .pa_iomux_pad = 0x20E046C, .led_pin = 20, .clock_offset = 12},
+	{.pa_dr = 0x20A8000, .pa_gdir = 0x20A8004, .pa_iomuxc_mux = 0x20E01DC, .pa_ccm_ccgrx = 0x20C4074, .pa_iomux_pad = 0x20E0468, .led_pin = 19, .clock_offset = 12},
+};
+
+/*驱动入口*/
+static __init int led_chrdev_init(void)
+{
+	int i = 0;
+	dev_t cur_dev;
+
+	printk("led chrdev init\n");
+
+	/*动态申请设备号*/
+	alloc_chrdev_region(&devno, 0, DEV_CNT, DEV_NAME);
+
+	/*创建“字符设备”类*/
+	led_chrdev_class = class_create(THIS_MODULE, "led_chrdev");
+
+	for (; i < DEV_CNT; i++)
+	{
+		/*初始化字符设备结构体 cdev(指定操作函数集)*/
+		cdev_init(&led_cdev[i].dev, &led_chrdev_fops);
+		led_cdev[i].dev.owner = THIS_MODULE;
+
+		/*由主设备号和次设备号合成设备号*/
+		cur_dev = MKDEV(MAJOR(devno), MINOR(devno) + i);
+
+		/*注册字符设备*/
+		cdev_add(&led_cdev[i].dev, cur_dev, 1);
+
+		/*创建字符设备节点*/
+		device_create(led_chrdev_class, NULL, cur_dev, NULL,
+					  DEV_NAME "%d", i);
+	}
+
+
+	// spin_lock_init(&s_lock);
+	// sema_init(&sema_lock, 1);
+	mutex_init(&mu_lock);
+	return 0;
+}
+module_init(led_chrdev_init);
+
+/*驱动出口*/
+static __exit void led_chrdev_exit(void)
+{
+	int i;
+	dev_t cur_dev;
+	printk("led chrdev exit\n");
+
+	for (i = 0; i < DEV_CNT; i++)
+	{
+		/*由主设备号和次设备号拼接成设备号*/
+		cur_dev = MKDEV(MAJOR(devno), MINOR(devno) + i);
+
+		/*移除字符设备节点*/
+		device_destroy(led_chrdev_class, cur_dev);
+
+		cdev_del(&led_cdev[i].dev);
+	}
+	unregister_chrdev_region(devno, DEV_CNT);
+	class_destroy(led_chrdev_class);
+}
+
+module_exit(led_chrdev_exit);
+
+MODULE_AUTHOR("embedfire");
+MODULE_LICENSE("GPL");
diff --git a/base_code/linux_driver/concurrency/mutex/test_app.c b/base_code/linux_driver/concurrency/mutex/test_app.c
new file mode 100644
index 0000000000000000000000000000000000000000..238d5c87f0240ac8f77829707116ab7fa85906a8
--- /dev/null
+++ b/base_code/linux_driver/concurrency/mutex/test_app.c
@@ -0,0 +1,87 @@
+#include <stdio.h>
+#include <unistd.h>
+#include <fcntl.h>
+#include <string.h>
+
+/*多线程需要用到的头文件*/
+#include <sys/types.h>
+#include <unistd.h>
+
+int main(int argc, char *argv[])
+{
+
+    pid_t pid; //用于保存 fork 函数返回的父、子线程的PID
+    int fd;
+
+    /*判断输入的命令是否合法*/
+    if (argc != 2)
+    {
+        printf(" commend error ! \n");
+        return -1;
+    }
+
+    pid = fork();
+    if (pid < 0)
+    {
+        /*fork 函数执行错误*/
+        printf("\n fork error ！！\n");
+        return -1;
+    }
+
+    if (0 == pid)
+    {
+        printf("\n child! \n");
+        /*这里是子线程*/
+        fd = open("/dev/led_chrdev0", O_RDWR); //打开设 "led_chrdev0"
+        if (fd < 0)
+        {
+            printf("\n open file : /dev/led_chrdev0 failed !!!\n");
+            return -1;
+        }
+
+        /*写入命令*/
+        int error = write(fd, argv[1], sizeof(argv[1]));
+        if (error < 0)
+        {
+            printf("write file error! \n");
+            close(fd);
+            /*判断是否关闭成功*/
+        }
+
+        /*关闭文件*/
+        error = close(fd);
+        if (error < 0)
+        {
+            printf("close file error! \n");
+        }
+    }
+    else
+    {
+        printf("\n parent! \n");
+        /*这里是父进程*/
+        fd = open("/dev/led_chrdev1", O_RDWR); //打开设 "led_chrdev1"
+        if (fd < 0)
+        {
+            printf("\n open file : /dev/led_chrdev1 failed !!!\n");
+            return -1;
+        }
+
+        /*写入命令*/
+        int error = write(fd, argv[1], sizeof(argv[1]));
+        if (error < 0)
+        {
+            printf("write file error! \n");
+            close(fd);
+            /*判断是否关闭成功*/
+        }
+
+        /*关闭文件*/
+        error = close(fd);
+        if (error < 0)
+        {
+            printf("close file error! \n");
+        }
+    }
+
+    return 0;
+}
\ No newline at end of file
diff --git a/base_code/linux_driver/concurrency/semaphore/Makefile b/base_code/linux_driver/concurrency/semaphore/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..779f63e89b090ad26b02f27f2a1987cdc90035d3
--- /dev/null
+++ b/base_code/linux_driver/concurrency/semaphore/Makefile
@@ -0,0 +1,12 @@
+KERNEL_DIR = /home/fire2/ebf-buster-linux
+
+obj-m := semaphore.o
+
+all:
+	$(MAKE) -C $(KERNEL_DIR) M=$(CURDIR) modules
+	
+.PHONY:clean
+clean:
+	$(MAKE) -C $(KERNEL_DIR) M=$(CURDIR) clean
+
+	echo 1 >/dev/led_chrdev0
diff --git a/base_code/linux_driver/concurrency/semaphore/semaphore.c b/base_code/linux_driver/concurrency/semaphore/semaphore.c
new file mode 100644
index 0000000000000000000000000000000000000000..10be32d2dc060be0b9d7d1e183d6c486bf514fe6
--- /dev/null
+++ b/base_code/linux_driver/concurrency/semaphore/semaphore.c
@@ -0,0 +1,211 @@
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/cdev.h>
+#include <linux/fs.h>
+#include <linux/uaccess.h>
+#include <linux/io.h>
+#include <linux/delay.h>
+
+#define DEV_NAME "led_chrdev"
+#define DEV_CNT (3)
+
+static dev_t devno;
+struct class *led_chrdev_class;
+
+/*定义一个自旋锁*/
+// spinlock_t s_lock;
+struct semaphore sema_lock;
+
+/*自定义led_chrdev结构体，保存有字符设备结构体cdev
+ *和led 相关寄存器地址。
+*/
+struct led_chrdev
+{
+	struct cdev dev;
+	unsigned int __iomem *va_dr;
+	unsigned int __iomem *va_gdir;
+	unsigned int __iomem *va_iomuxc_mux;
+	unsigned int __iomem *va_ccm_ccgrx;
+	unsigned int __iomem *va_iomux_pad;
+
+	unsigned long pa_dr;
+	unsigned long pa_gdir;
+	unsigned long pa_iomuxc_mux;
+	unsigned long pa_ccm_ccgrx;
+	unsigned long pa_iomux_pad;
+
+	unsigned int led_pin;
+	unsigned int clock_offset;
+};
+
+
+
+static int led_chrdev_open(struct inode *inode, struct file *filp)
+{
+
+	unsigned int val = 0;
+
+	struct led_chrdev *led_cdev =
+		(struct led_chrdev *)container_of(inode->i_cdev, struct led_chrdev,
+										  dev);
+	filp->private_data =
+		container_of(inode->i_cdev, struct led_chrdev, dev);
+
+	printk("open\n");
+
+	led_cdev->va_dr = ioremap(led_cdev->pa_dr, 4);
+	led_cdev->va_gdir = ioremap(led_cdev->pa_gdir, 4);
+	led_cdev->va_iomuxc_mux = ioremap(led_cdev->pa_iomuxc_mux, 4);
+	led_cdev->va_ccm_ccgrx = ioremap(led_cdev->pa_ccm_ccgrx, 4);
+	led_cdev->va_iomux_pad = ioremap(led_cdev->pa_iomux_pad, 4);
+
+	val = ioread32(led_cdev->va_ccm_ccgrx);
+	val &= ~(3 << led_cdev->clock_offset);
+	val |= (3 << led_cdev->clock_offset);
+	iowrite32(val, led_cdev->va_ccm_ccgrx);
+
+	iowrite32(5, led_cdev->va_iomuxc_mux);
+
+	iowrite32(0x1F838, led_cdev->va_iomux_pad);
+
+	val = ioread32(led_cdev->va_gdir);
+	val &= ~(1 << led_cdev->led_pin);
+	val |= (1 << led_cdev->led_pin);
+	iowrite32(val, led_cdev->va_gdir);
+
+	val = ioread32(led_cdev->va_dr);
+	val |= (0x01 << led_cdev->led_pin);
+	iowrite32(val, led_cdev->va_dr);
+
+	return 0;
+}
+
+static int led_chrdev_release(struct inode *inode, struct file *filp)
+{
+	struct led_chrdev *led_cdev =
+		(struct led_chrdev *)container_of(inode->i_cdev, struct led_chrdev,
+										  dev);
+
+	iounmap(led_cdev->va_dr);
+	iounmap(led_cdev->va_gdir);
+	iounmap(led_cdev->va_iomuxc_mux);
+	iounmap(led_cdev->va_ccm_ccgrx);
+	iounmap(led_cdev->va_iomux_pad);
+
+	printk(" \n finished  !!!\n");
+
+	return 0;
+}
+
+static ssize_t led_chrdev_write(struct file *filp, const char __user *buf,
+								size_t count, loff_t *ppos)
+{
+	unsigned long val = 0;
+	unsigned long ret = 0;
+	unsigned long i;
+
+	int tmp = count;
+
+	kstrtoul_from_user(buf, tmp, 10, &ret);
+	struct led_chrdev *led_cdev = (struct led_chrdev *)filp->private_data;
+
+	// spin_lock(&s_lock);
+	down(&sema_lock);
+	for (i = ret; i > 0; i--)
+	{
+		printk("the data is %ld \n", i);
+
+		/*点亮led 灯*/
+		val &= ~(0x01 << led_cdev->led_pin);
+		iowrite32(val, led_cdev->va_dr);
+		mdelay(100);
+
+		/*熄灭led 灯*/
+		val |= (0x01 << led_cdev->led_pin); 
+		iowrite32(val, led_cdev->va_dr);
+		mdelay(100);
+	}
+	// spin_unlock(&s_lock);
+	up(&sema_lock);
+
+
+	*ppos += tmp;
+	return tmp;
+}
+
+static struct file_operations led_chrdev_fops = {
+	.owner = THIS_MODULE,
+	.open = led_chrdev_open,
+	.release = led_chrdev_release,
+	.write = led_chrdev_write,
+};
+
+static struct led_chrdev led_cdev[DEV_CNT] = {
+	{.pa_dr = 0x0209C000, .pa_gdir = 0x0209C004, .pa_iomuxc_mux = 0x20E006C, .pa_ccm_ccgrx = 0x20C406C, .pa_iomux_pad = 0x20E02F8, .led_pin = 4, .clock_offset = 26},
+	{.pa_dr = 0x20A8000, .pa_gdir = 0x20A8004, .pa_iomuxc_mux = 0x20E01E0, .pa_ccm_ccgrx = 0x20C4074, .pa_iomux_pad = 0x20E046C, .led_pin = 20, .clock_offset = 12},
+	{.pa_dr = 0x20A8000, .pa_gdir = 0x20A8004, .pa_iomuxc_mux = 0x20E01DC, .pa_ccm_ccgrx = 0x20C4074, .pa_iomux_pad = 0x20E0468, .led_pin = 19, .clock_offset = 12},
+};
+
+/*驱动入口*/
+static __init int led_chrdev_init(void)
+{
+	int i = 0;
+	dev_t cur_dev;
+
+	printk("led chrdev init\n");
+
+	/*动态申请设备号*/
+	alloc_chrdev_region(&devno, 0, DEV_CNT, DEV_NAME);
+
+	/*创建“字符设备”类*/
+	led_chrdev_class = class_create(THIS_MODULE, "led_chrdev");
+
+	for (; i < DEV_CNT; i++)
+	{
+		/*初始化字符设备结构体 cdev(指定操作函数集)*/
+		cdev_init(&led_cdev[i].dev, &led_chrdev_fops);
+		led_cdev[i].dev.owner = THIS_MODULE;
+
+		/*由主设备号和次设备号合成设备号*/
+		cur_dev = MKDEV(MAJOR(devno), MINOR(devno) + i);
+
+		/*注册字符设备*/
+		cdev_add(&led_cdev[i].dev, cur_dev, 1);
+
+		/*创建字符设备节点*/
+		device_create(led_chrdev_class, NULL, cur_dev, NULL,
+					  DEV_NAME "%d", i);
+	}
+
+
+	// spin_lock_init(&s_lock);
+	sema_init(&sema_lock, 1);
+	return 0;
+}
+module_init(led_chrdev_init);
+
+/*驱动出口*/
+static __exit void led_chrdev_exit(void)
+{
+	int i;
+	dev_t cur_dev;
+	printk("led chrdev exit\n");
+
+	for (i = 0; i < DEV_CNT; i++)
+	{
+		/*由主设备号和次设备号拼接成设备号*/
+		cur_dev = MKDEV(MAJOR(devno), MINOR(devno) + i);
+
+		/*移除字符设备节点*/
+		device_destroy(led_chrdev_class, cur_dev);
+
+		cdev_del(&led_cdev[i].dev);
+	}
+	unregister_chrdev_region(devno, DEV_CNT);
+	class_destroy(led_chrdev_class);
+}
+
+module_exit(led_chrdev_exit);
+
+MODULE_AUTHOR("embedfire");
+MODULE_LICENSE("GPL");
diff --git a/base_code/linux_driver/concurrency/semaphore/test_app.c b/base_code/linux_driver/concurrency/semaphore/test_app.c
new file mode 100644
index 0000000000000000000000000000000000000000..238d5c87f0240ac8f77829707116ab7fa85906a8
--- /dev/null
+++ b/base_code/linux_driver/concurrency/semaphore/test_app.c
@@ -0,0 +1,87 @@
+#include <stdio.h>
+#include <unistd.h>
+#include <fcntl.h>
+#include <string.h>
+
+/*多线程需要用到的头文件*/
+#include <sys/types.h>
+#include <unistd.h>
+
+int main(int argc, char *argv[])
+{
+
+    pid_t pid; //用于保存 fork 函数返回的父、子线程的PID
+    int fd;
+
+    /*判断输入的命令是否合法*/
+    if (argc != 2)
+    {
+        printf(" commend error ! \n");
+        return -1;
+    }
+
+    pid = fork();
+    if (pid < 0)
+    {
+        /*fork 函数执行错误*/
+        printf("\n fork error ！！\n");
+        return -1;
+    }
+
+    if (0 == pid)
+    {
+        printf("\n child! \n");
+        /*这里是子线程*/
+        fd = open("/dev/led_chrdev0", O_RDWR); //打开设 "led_chrdev0"
+        if (fd < 0)
+        {
+            printf("\n open file : /dev/led_chrdev0 failed !!!\n");
+            return -1;
+        }
+
+        /*写入命令*/
+        int error = write(fd, argv[1], sizeof(argv[1]));
+        if (error < 0)
+        {
+            printf("write file error! \n");
+            close(fd);
+            /*判断是否关闭成功*/
+        }
+
+        /*关闭文件*/
+        error = close(fd);
+        if (error < 0)
+        {
+            printf("close file error! \n");
+        }
+    }
+    else
+    {
+        printf("\n parent! \n");
+        /*这里是父进程*/
+        fd = open("/dev/led_chrdev1", O_RDWR); //打开设 "led_chrdev1"
+        if (fd < 0)
+        {
+            printf("\n open file : /dev/led_chrdev1 failed !!!\n");
+            return -1;
+        }
+
+        /*写入命令*/
+        int error = write(fd, argv[1], sizeof(argv[1]));
+        if (error < 0)
+        {
+            printf("write file error! \n");
+            close(fd);
+            /*判断是否关闭成功*/
+        }
+
+        /*关闭文件*/
+        error = close(fd);
+        if (error < 0)
+        {
+            printf("close file error! \n");
+        }
+    }
+
+    return 0;
+}
\ No newline at end of file
diff --git a/base_code/linux_driver/concurrency/spinlock/Makefile b/base_code/linux_driver/concurrency/spinlock/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..d1ed067c8a3bd7f1017aabeb1d5d0ddc657fbc33
--- /dev/null
+++ b/base_code/linux_driver/concurrency/spinlock/Makefile
@@ -0,0 +1,12 @@
+KERNEL_DIR = /home/fire2/ebf-buster-linux
+
+obj-m := spinlock.o
+
+all:
+	$(MAKE) -C $(KERNEL_DIR) M=$(CURDIR) modules
+	
+.PHONY:clean
+clean:
+	$(MAKE) -C $(KERNEL_DIR) M=$(CURDIR) clean
+
+	echo 1 >/dev/led_chrdev0
diff --git a/base_code/linux_driver/concurrency/spinlock/spinlock.c b/base_code/linux_driver/concurrency/spinlock/spinlock.c
new file mode 100644
index 0000000000000000000000000000000000000000..9ce1122694958d076f2e9b90c8c835df8ac00e3c
--- /dev/null
+++ b/base_code/linux_driver/concurrency/spinlock/spinlock.c
@@ -0,0 +1,205 @@
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/cdev.h>
+#include <linux/fs.h>
+#include <linux/uaccess.h>
+#include <linux/io.h>
+#include <linux/delay.h>
+
+#define DEV_NAME "led_chrdev"
+#define DEV_CNT (3)
+
+static dev_t devno;
+struct class *led_chrdev_class;
+
+/*定义一个自旋锁*/
+spinlock_t s_lock;
+
+/*自定义led_chrdev结构体，保存有字符设备结构体cdev
+ *和led 相关寄存器地址。
+*/
+struct led_chrdev
+{
+	struct cdev dev;
+	unsigned int __iomem *va_dr;
+	unsigned int __iomem *va_gdir;
+	unsigned int __iomem *va_iomuxc_mux;
+	unsigned int __iomem *va_ccm_ccgrx;
+	unsigned int __iomem *va_iomux_pad;
+
+	unsigned long pa_dr;
+	unsigned long pa_gdir;
+	unsigned long pa_iomuxc_mux;
+	unsigned long pa_ccm_ccgrx;
+	unsigned long pa_iomux_pad;
+
+	unsigned int led_pin;
+	unsigned int clock_offset;
+};
+
+
+
+static int led_chrdev_open(struct inode *inode, struct file *filp)
+{
+
+	unsigned int val = 0;
+
+	struct led_chrdev *led_cdev =
+		(struct led_chrdev *)container_of(inode->i_cdev, struct led_chrdev,
+										  dev);
+	filp->private_data =
+		container_of(inode->i_cdev, struct led_chrdev, dev);
+
+	printk("open\n");
+
+	led_cdev->va_dr = ioremap(led_cdev->pa_dr, 4);
+	led_cdev->va_gdir = ioremap(led_cdev->pa_gdir, 4);
+	led_cdev->va_iomuxc_mux = ioremap(led_cdev->pa_iomuxc_mux, 4);
+	led_cdev->va_ccm_ccgrx = ioremap(led_cdev->pa_ccm_ccgrx, 4);
+	led_cdev->va_iomux_pad = ioremap(led_cdev->pa_iomux_pad, 4);
+
+	val = ioread32(led_cdev->va_ccm_ccgrx);
+	val &= ~(3 << led_cdev->clock_offset);
+	val |= (3 << led_cdev->clock_offset);
+	iowrite32(val, led_cdev->va_ccm_ccgrx);
+
+	iowrite32(5, led_cdev->va_iomuxc_mux);
+
+	iowrite32(0x1F838, led_cdev->va_iomux_pad);
+
+	val = ioread32(led_cdev->va_gdir);
+	val &= ~(1 << led_cdev->led_pin);
+	val |= (1 << led_cdev->led_pin);
+	iowrite32(val, led_cdev->va_gdir);
+
+	val = ioread32(led_cdev->va_dr);
+	val |= (0x01 << led_cdev->led_pin);
+	iowrite32(val, led_cdev->va_dr);
+
+	return 0;
+}
+
+static int led_chrdev_release(struct inode *inode, struct file *filp)
+{
+	struct led_chrdev *led_cdev =
+		(struct led_chrdev *)container_of(inode->i_cdev, struct led_chrdev,
+										  dev);
+
+	iounmap(led_cdev->va_dr);
+	iounmap(led_cdev->va_gdir);
+	iounmap(led_cdev->va_iomuxc_mux);
+	iounmap(led_cdev->va_ccm_ccgrx);
+	iounmap(led_cdev->va_iomux_pad);
+
+	printk(" \n finished  !!!\n");
+
+	return 0;
+}
+
+static ssize_t led_chrdev_write(struct file *filp, const char __user *buf,
+								size_t count, loff_t *ppos)
+{
+	unsigned long val = 0;
+	unsigned long ret = 0;
+	unsigned long i;
+
+	int tmp = count;
+
+	kstrtoul_from_user(buf, tmp, 10, &ret);
+	struct led_chrdev *led_cdev = (struct led_chrdev *)filp->private_data;
+
+	// spin_lock(&s_lock);
+	for (i = ret; i > 0; i--)
+	{
+		printk("the data is %ld \n", i);
+
+		/*点亮led 灯*/
+		val &= ~(0x01 << led_cdev->led_pin);
+		iowrite32(val, led_cdev->va_dr);
+		mdelay(100);
+
+		/*熄灭led 灯*/
+		val |= (0x01 << led_cdev->led_pin); 
+		iowrite32(val, led_cdev->va_dr);
+		mdelay(100);
+	}
+	// spin_unlock(&s_lock);
+
+
+	*ppos += tmp;
+	return tmp;
+}
+
+static struct file_operations led_chrdev_fops = {
+	.owner = THIS_MODULE,
+	.open = led_chrdev_open,
+	.release = led_chrdev_release,
+	.write = led_chrdev_write,
+};
+
+static struct led_chrdev led_cdev[DEV_CNT] = {
+	{.pa_dr = 0x0209C000, .pa_gdir = 0x0209C004, .pa_iomuxc_mux = 0x20E006C, .pa_ccm_ccgrx = 0x20C406C, .pa_iomux_pad = 0x20E02F8, .led_pin = 4, .clock_offset = 26},
+	{.pa_dr = 0x20A8000, .pa_gdir = 0x20A8004, .pa_iomuxc_mux = 0x20E01E0, .pa_ccm_ccgrx = 0x20C4074, .pa_iomux_pad = 0x20E046C, .led_pin = 20, .clock_offset = 12},
+	{.pa_dr = 0x20A8000, .pa_gdir = 0x20A8004, .pa_iomuxc_mux = 0x20E01DC, .pa_ccm_ccgrx = 0x20C4074, .pa_iomux_pad = 0x20E0468, .led_pin = 19, .clock_offset = 12},
+};
+
+/*驱动入口*/
+static __init int led_chrdev_init(void)
+{
+	int i = 0;
+	dev_t cur_dev;
+
+	printk("led chrdev init\n");
+
+	/*动态申请设备号*/
+	alloc_chrdev_region(&devno, 0, DEV_CNT, DEV_NAME);
+
+	/*创建“字符设备”类*/
+	led_chrdev_class = class_create(THIS_MODULE, "led_chrdev");
+
+	for (; i < DEV_CNT; i++)
+	{
+		/*初始化字符设备结构体 cdev(指定操作函数集)*/
+		cdev_init(&led_cdev[i].dev, &led_chrdev_fops);
+		led_cdev[i].dev.owner = THIS_MODULE;
+
+		/*由主设备号和次设备号合成设备号*/
+		cur_dev = MKDEV(MAJOR(devno), MINOR(devno) + i);
+
+		/*注册字符设备*/
+		cdev_add(&led_cdev[i].dev, cur_dev, 1);
+
+		/*创建字符设备节点*/
+		device_create(led_chrdev_class, NULL, cur_dev, NULL,
+					  DEV_NAME "%d", i);
+	}
+	spin_lock_init(&s_lock);
+	return 0;
+}
+module_init(led_chrdev_init);
+
+/*驱动出口*/
+static __exit void led_chrdev_exit(void)
+{
+	int i;
+	dev_t cur_dev;
+	printk("led chrdev exit\n");
+
+	for (i = 0; i < DEV_CNT; i++)
+	{
+		/*由主设备号和次设备号拼接成设备号*/
+		cur_dev = MKDEV(MAJOR(devno), MINOR(devno) + i);
+
+		/*移除字符设备节点*/
+		device_destroy(led_chrdev_class, cur_dev);
+
+		cdev_del(&led_cdev[i].dev);
+	}
+	unregister_chrdev_region(devno, DEV_CNT);
+	class_destroy(led_chrdev_class);
+}
+
+module_exit(led_chrdev_exit);
+
+MODULE_AUTHOR("embedfire");
+MODULE_LICENSE("GPL");
diff --git a/base_code/linux_driver/concurrency/spinlock/test_app.c b/base_code/linux_driver/concurrency/spinlock/test_app.c
new file mode 100644
index 0000000000000000000000000000000000000000..238d5c87f0240ac8f77829707116ab7fa85906a8
--- /dev/null
+++ b/base_code/linux_driver/concurrency/spinlock/test_app.c
@@ -0,0 +1,87 @@
+#include <stdio.h>
+#include <unistd.h>
+#include <fcntl.h>
+#include <string.h>
+
+/*多线程需要用到的头文件*/
+#include <sys/types.h>
+#include <unistd.h>
+
+int main(int argc, char *argv[])
+{
+
+    pid_t pid; //用于保存 fork 函数返回的父、子线程的PID
+    int fd;
+
+    /*判断输入的命令是否合法*/
+    if (argc != 2)
+    {
+        printf(" commend error ! \n");
+        return -1;
+    }
+
+    pid = fork();
+    if (pid < 0)
+    {
+        /*fork 函数执行错误*/
+        printf("\n fork error ！！\n");
+        return -1;
+    }
+
+    if (0 == pid)
+    {
+        printf("\n child! \n");
+        /*这里是子线程*/
+        fd = open("/dev/led_chrdev0", O_RDWR); //打开设 "led_chrdev0"
+        if (fd < 0)
+        {
+            printf("\n open file : /dev/led_chrdev0 failed !!!\n");
+            return -1;
+        }
+
+        /*写入命令*/
+        int error = write(fd, argv[1], sizeof(argv[1]));
+        if (error < 0)
+        {
+            printf("write file error! \n");
+            close(fd);
+            /*判断是否关闭成功*/
+        }
+
+        /*关闭文件*/
+        error = close(fd);
+        if (error < 0)
+        {
+            printf("close file error! \n");
+        }
+    }
+    else
+    {
+        printf("\n parent! \n");
+        /*这里是父进程*/
+        fd = open("/dev/led_chrdev1", O_RDWR); //打开设 "led_chrdev1"
+        if (fd < 0)
+        {
+            printf("\n open file : /dev/led_chrdev1 failed !!!\n");
+            return -1;
+        }
+
+        /*写入命令*/
+        int error = write(fd, argv[1], sizeof(argv[1]));
+        if (error < 0)
+        {
+            printf("write file error! \n");
+            close(fd);
+            /*判断是否关闭成功*/
+        }
+
+        /*关闭文件*/
+        error = close(fd);
+        if (error < 0)
+        {
+            printf("close file error! \n");
+        }
+    }
+
+    return 0;
+}
\ No newline at end of file
diff --git a/base_code/linux_driver/device_tree_rgb_led/Makefile b/base_code/linux_driver/device_tree_rgb_led/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..c153d05f30b4b56d7288a681a8df38c0a81ea9c7
--- /dev/null
+++ b/base_code/linux_driver/device_tree_rgb_led/Makefile
@@ -0,0 +1,10 @@
+KERNEL_DIR = /home/fire2/ebf-buster-linux
+
+obj-m := rgb_led.o
+
+all:
+	$(MAKE) -C $(KERNEL_DIR) M=$(CURDIR) modules
+	
+.PHONY:clean
+clean:
+	$(MAKE) -C $(KERNEL_DIR) M=$(CURDIR) clean
diff --git a/base_code/linux_driver/device_tree_rgb_led/imx6ull-seeed-npi.dts b/base_code/linux_driver/device_tree_rgb_led/imx6ull-seeed-npi.dts
new file mode 100644
index 0000000000000000000000000000000000000000..072a609a7abee3f09a216f97f6b88b537e9cc4c8
--- /dev/null
+++ b/base_code/linux_driver/device_tree_rgb_led/imx6ull-seeed-npi.dts
@@ -0,0 +1,475 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/input/input.h>
+#include "imx6ull.dtsi"
+
+/ {
+	model = "Seeed i.MX6 ULL NPi Board";
+	compatible = "fsl,imx6ull-14x14-evk", "fsl,imx6ull";
+
+	aliases {
+		pwm0 = &pwm1;
+		pwm1 = &pwm2;
+		pwm2 = &pwm3;
+		pwm3 = &pwm4;
+	};
+
+	chosen {
+		stdout-path = &uart1;
+	};
+
+	memory {
+		reg = <0x80000000 0x20000000>;
+	};
+
+	reserved-memory {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		linux,cma {
+			compatible = "shared-dma-pool";
+			reusable;
+			size = <0x14000000>;
+			linux,cma-default;
+		};
+	};
+
+	regulators {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+
+		reg_sd1_vmmc: regulator@1 {
+			compatible = "regulator-fixed";
+			regulator-name = "VSD_3V3";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+			gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
+			off-on-delay = <20000>;
+			enable-active-high;
+		};
+
+		reg_gpio_dvfs: regulator-gpio {
+			compatible = "regulator-gpio";
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_dvfs>;
+			regulator-min-microvolt = <1300000>;
+			regulator-max-microvolt = <1400000>;
+			regulator-name = "gpio_dvfs";
+			regulator-type = "voltage";
+			gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>;
+			states = <1300000 0x1 1400000 0x0>;
+		};
+	};
+
+    /* External sound card */
+    sound: sound {
+        status = "disabled";
+    };
+
+
+/*
+*CCM_CCGR1                         0x020C406C
+*IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO04  0x020E006C
+*IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO04  0x020E02F8
+*GPIO1_GD                          0x0209C000
+*GPIO1_GDIR                        0x0209C004
+*/
+
+
+/*
+*CCM_CCGR3                         0x020C4074
+*IOMUXC_SW_MUX_CTL_PAD_CSI_HSYNC   0x020E01E0
+*IOMUXC_SW_PAD_CTL_PAD_CSI_HSYNC   0x020E046C
+*GPIO4_GD                          0x020A8000
+*GPIO4_GDIR                        0x020A8004
+*/
+
+
+/*
+*CCM_CCGR3                         0x020C4074
+*IOMUXC_SW_MUX_CTL_PAD_CSI_VSYNC   0x020E01DC
+*IOMUXC_SW_PAD_CTL_PAD_CSI_VSYNC   0x020E0468
+*GPIO4_GD                          0x020A8000
+*GPIO4_GDIR                        0x020A8004
+*/
+	/*添加led节点*/
+	rgb_led{
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "fire,rgb_led";
+
+		/*红灯节点*/
+		ranges;
+		rgb_led_red@0x020C406C{
+			compatible = "fire,rgb_led_red";
+			reg = <0x020C406C 0x00000004
+			       0x020E006C 0x00000004
+			       0x020E02F8 0x00000004
+				   0x0209C000 0x00000004
+			       0x0209C004 0x00000004>;
+			status = "okay";
+		};
+
+		/*绿灯节点*/
+		rgb_led_green@0x020C4074{
+			compatible = "fire,rgb_led_green";
+			reg = <0x020C4074 0x00000004
+			       0x020E01E0 0x00000004
+			       0x020E046C 0x00000004
+				   0x020A8000 0x00000004
+			       0x020A8004 0x00000004>;
+			status = "okay";
+		};
+
+		/*蓝灯节点*/
+		rgb_led_blue@0x020C4074{
+			compatible = "fire,rgb_led_blue";
+			reg = <0x020C4074 0x00000004
+			       0x020E01DC 0x00000004
+			       0x020E0468 0x00000004
+				   0x020A8000 0x00000004
+			       0x020A8004 0x00000004>;
+			status = "okay";
+		};
+	};
+};
+
+
+
+
+&cpu0 {
+	dc-supply = <&reg_gpio_dvfs>;
+	clock-frequency = <800000000>;
+};
+
+&clks {
+	assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
+	assigned-clock-rates = <786432000>;
+};
+
+
+&fec1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_enet1>;
+	phy-mode = "rmii";
+	phy-handle = <&ethphy0>;
+	status = "okay";
+};
+
+&fec2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_enet2>;
+	phy-mode = "rmii";
+	phy-handle = <&ethphy1>;
+	status = "okay";
+
+	mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ethphy0: ethernet-phy@2 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <2>;
+			micrel,led-mode = <1>;
+			clocks = <&clks IMX6UL_CLK_ENET_REF>;
+			clock-names = "rmii-ref";
+		};
+
+		ethphy1: ethernet-phy@1 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <1>;
+			micrel,led-mode = <1>;
+			clocks = <&clks IMX6UL_CLK_ENET2_REF>;
+			clock-names = "rmii-ref";
+		};
+	};
+};
+
+
+&gpc {
+	fsl,cpu_pupscr_sw2iso = <0xf>;
+	fsl,cpu_pupscr_sw = <0x0>;
+	fsl,cpu_pdnscr_iso2sw = <0x1>;
+	fsl,cpu_pdnscr_iso = <0x1>;
+	fsl,ldo-bypass = <0>; /* DCDC, ldo-enable */
+};
+
+
+&iomuxc {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_hog_1>;
+
+	pinctrl_rgb_led:rgb_led{
+			fsl,pins = <
+				MX6UL_PAD_GPIO1_IO04__GPIO1_IO04	0x000010B1 /* remote control   add by pan  20200307*/
+				MX6UL_PAD_CSI_HSYNC__GPIO4_IO20	    0x000010B1 /* remote control   add by pan  20200307*/
+				MX6UL_PAD_CSI_VSYNC__GPIO4_IO19	    0x000010B1 /* remote control   add by pan  20200307*/
+			>;
+		};
+
+	pinctrl_gpmi_nand: gpmi-nand {
+			fsl,pins = <
+				MX6UL_PAD_NAND_CLE__RAWNAND_CLE         0xb0b1
+				MX6UL_PAD_NAND_ALE__RAWNAND_ALE         0xb0b1
+				MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B       0xb0b1
+				MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0xb000
+				MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B     0xb0b1
+				MX6UL_PAD_NAND_CE1_B__RAWNAND_CE1_B     0xb0b1
+				MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B       0xb0b1
+				MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B       0xb0b1
+				MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00   0xb0b1
+				MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01   0xb0b1
+				MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02   0xb0b1
+				MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03   0xb0b1
+				MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04   0xb0b1
+				MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05   0xb0b1
+				MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06   0xb0b1
+				MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07   0xb0b1
+			>;
+		};
+
+	pinctrl_hog_1: hoggrp-1 {
+		fsl,pins = <
+			MX6UL_PAD_UART1_RTS_B__GPIO1_IO19	0x17059 /* SD1 CD */
+			MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT	0x17059 /* SD1 VSELECT */
+			MX6UL_PAD_GPIO1_IO09__GPIO1_IO09        0x17059 /* SD1 RESET */
+		>;
+	};
+
+	pinctrl_enet1: enet1grp {
+		fsl,pins = <
+			MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN	0x1b0b0
+			MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER	0x1b0b0
+			MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00	0x1b0b0
+			MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01	0x1b0b0
+			MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN	0x1b0b0
+			MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00	0x1b0b0
+			MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01	0x1b0b0
+			MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1	0x4001b031
+		>;
+	};
+
+	pinctrl_enet2: enet2grp {
+		fsl,pins = <
+			MX6UL_PAD_GPIO1_IO07__ENET2_MDC		0x1b0b0
+			MX6UL_PAD_GPIO1_IO06__ENET2_MDIO	0x1b0b0
+			MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN	0x1b0b0
+			MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER	0x1b0b0
+			MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00	0x1b0b0
+			MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01	0x1b0b0
+			MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN	0x1b0b0
+			MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00	0x1b0b0
+			MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01	0x1b0b0
+			MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2	0x4001b031
+		>;
+	};
+
+	pinctrl_uart1: uart1grp {
+		fsl,pins = <
+			MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
+			MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
+		>;
+	};
+
+
+	pinctrl_usb_otg1_id: usbotg1idgrp {
+		fsl,pins = <
+			MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID	0x17059
+		>;
+	};
+
+        pinctrl_dvfs: dvfsgrp {
+                fsl,pins = <
+                        MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03      0x79
+                >;
+        };
+
+	pinctrl_usdhc1: usdhc1grp {
+		fsl,pins = <
+			MX6UL_PAD_SD1_CMD__USDHC1_CMD     0x17059
+			MX6UL_PAD_SD1_CLK__USDHC1_CLK     0x10071
+			MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
+			MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
+			MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
+			MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
+		>;
+	};
+
+	pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
+		fsl,pins = <
+			MX6UL_PAD_SD1_CMD__USDHC1_CMD     0x170b9
+			MX6UL_PAD_SD1_CLK__USDHC1_CLK     0x100b9
+			MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
+			MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
+			MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
+			MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9
+		>;
+	};
+
+	pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
+		fsl,pins = <
+			MX6UL_PAD_SD1_CMD__USDHC1_CMD     0x170f9
+			MX6UL_PAD_SD1_CLK__USDHC1_CLK     0x100f9
+			MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9
+			MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9
+			MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9
+			MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9
+		>;
+	};
+
+	pinctrl_usdhc2: usdhc2grp {
+		fsl,pins = <
+			MX6UL_PAD_NAND_RE_B__USDHC2_CLK     0x10069
+			MX6UL_PAD_NAND_WE_B__USDHC2_CMD     0x17059
+			MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
+			MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
+			MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
+			MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
+		>;
+	};
+
+	pinctrl_usdhc2_8bit: usdhc2grp_8bit {
+		fsl,pins = <
+			MX6UL_PAD_NAND_RE_B__USDHC2_CLK     0x10069
+			MX6UL_PAD_NAND_WE_B__USDHC2_CMD     0x17059
+			MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
+			MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
+			MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
+			MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
+			MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17059
+			MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17059
+			MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17059
+			MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17059
+		>;
+	};
+
+	pinctrl_usdhc2_8bit_100mhz: usdhc2grp_8bit_100mhz {
+		fsl,pins = <
+			MX6UL_PAD_NAND_RE_B__USDHC2_CLK     0x100b9
+			MX6UL_PAD_NAND_WE_B__USDHC2_CMD     0x170b9
+			MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170b9
+			MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170b9
+			MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170b9
+			MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170b9
+			MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170b9
+			MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170b9
+			MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170b9
+			MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170b9
+		>;
+	};
+
+	pinctrl_usdhc2_8bit_200mhz: usdhc2grp_8bit_200mhz {
+		fsl,pins = <
+			MX6UL_PAD_NAND_RE_B__USDHC2_CLK     0x100f9
+			MX6UL_PAD_NAND_WE_B__USDHC2_CMD     0x170f9
+			MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9
+			MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9
+			MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9
+			MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9
+			MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170f9
+			MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170f9
+			MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170f9
+			MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170f9
+		>;
+	};
+
+};
+
+&iomuxc_snvs {
+	pinctrl-names = "default_snvs";
+	pinctrl-0 = <&pinctrl_hog_2>;
+	pinctrl_hog_2: hoggrp-2 {
+		fsl,pins = <
+			MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00      0x80000000
+		>;
+	};
+};
+
+
+&snvs_pwrkey {
+	status = "disabled";
+};
+
+&pxp {
+	status = "okay";
+};
+
+
+&uart1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart1>;
+	status = "okay";
+};
+
+
+&usbotg1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usb_otg1_id>;
+	dr_mode = "otg";
+	srp-disable;
+	hnp-disable;
+	adp-disable;
+	status = "okay";
+};
+
+&usbotg2 {
+	dr_mode = "host";
+	disable-over-current;
+	status = "okay";
+};
+
+&usbphy1 {
+	fsl,tx-d-cal = <106>;
+};
+
+&usbphy2 {
+	fsl,tx-d-cal = <106>;
+};
+
+&usdhc1 {
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc1>;
+	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
+	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
+	no-1-8-v;
+	/*cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;*/
+	keep-power-in-suspend;
+	/*non-removable;*/
+	enable-sdio-wakeup;
+	vmmc-supply = <&reg_sd1_vmmc>;
+	status = "okay";
+};
+
+&usdhc2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usdhc2_8bit>;
+	non-removable;
+	status = "okay";
+};
+
+&gpmi {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_gpmi_nand>;
+	status = "okay";
+	//nand-on-flash-bbt;
+
+	partition@0 {
+			label = "uboot";
+			reg = <0x00000000 0x00800000>;
+		};
+		partition@1 {
+			label = "rootfs";
+			reg = <0x00800000 0x1F800000>;
+		};
+};
diff --git a/base_code/linux_driver/device_tree_rgb_led/rgb_led.c b/base_code/linux_driver/device_tree_rgb_led/rgb_led.c
new file mode 100644
index 0000000000000000000000000000000000000000..86832ccaaeec7b5238f9b5650e924b77c596a26c
--- /dev/null
+++ b/base_code/linux_driver/device_tree_rgb_led/rgb_led.c
@@ -0,0 +1,375 @@
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/fs.h>
+#include <linux/cdev.h>
+#include <linux/uaccess.h>
+
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/delay.h>
+#include <linux/ide.h>
+#include <linux/errno.h>
+#include <linux/gpio.h>
+#include <asm/mach/map.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_gpio.h>
+#include <asm/io.h>
+#include <linux/device.h>
+
+#include <linux/platform_device.h>
+
+/*------------------字符设备内容----------------------*/
+#define DEV_NAME "rgb_led"
+#define DEV_CNT (1)
+
+/*定义 led 资源结构体，保存获取得到的节点信息以及转换后的虚拟寄存器地址*/
+struct led_resource
+{
+	struct device_node *device_node; //rgb_led_red的设备树节点
+	void __iomem *virtual_CCM_CCGR;
+	void __iomem *virtual_IOMUXC_SW_MUX_CTL_PAD;
+	void __iomem *virtual_IOMUXC_SW_PAD_CTL_PAD;
+	void __iomem *virtual_DR;
+	void __iomem *virtual_GDIR;
+};
+
+static dev_t led_devno;					 //定义字符设备的设备号
+static struct cdev led_chr_dev;			 //定义字符设备结构体chr_dev
+struct class *class_led;				 //保存创建的类
+struct device *device;					 // 保存创建的设备
+struct device_node *rgb_led_device_node; //rgb_led的设备树节点结构体
+
+/*定义 R G B 三个灯的led_resource 结构体，保存获取得到的节点信息*/
+struct led_resource led_red;
+struct led_resource led_green;
+struct led_resource led_blue;
+
+/*字符设备操作函数集，open函数*/
+static int led_chr_dev_open(struct inode *inode, struct file *filp)
+{
+	printk("\n open form driver \n");
+	return 0;
+}
+
+/*字符设备操作函数集，write函数*/
+static ssize_t led_chr_dev_write(struct file *filp, const char __user *buf, size_t cnt, loff_t *offt)
+{
+
+	unsigned int register_data = 0; //暂存读取得到的寄存器数据
+	unsigned char write_data; //用于保存接收到的数据
+
+	int error = copy_from_user(&write_data, buf, cnt);
+	if (error < 0)
+	{
+		return -1;
+	}
+
+	/*设置 GPIO1_04 输出电平*/
+	if (write_data & 0x04)
+	{
+		register_data = readl(led_red.virtual_DR);
+		register_data &= ~(0x01 << 4);
+		writel(register_data, led_red.virtual_DR); // GPIO1_04引脚输出低电平，红灯亮
+	}
+	else
+	{
+		register_data = readl(led_red.virtual_DR);
+		register_data |= (0x01 << 4);
+		writel(register_data, led_red.virtual_DR); // GPIO1_04引脚输出高电平，红灯灭
+	}
+
+	/*设置 GPIO4_20 输出电平*/
+	if (write_data & 0x02)
+	{
+		register_data = readl(led_green.virtual_DR);
+		register_data &= ~(0x01 << 20);
+		writel(register_data, led_green.virtual_DR); // GPIO4_20引脚输出低电平，绿灯亮
+	}
+	else
+	{
+		register_data = readl(led_green.virtual_DR);
+		register_data |= (0x01 << 20);
+		writel(register_data, led_green.virtual_DR); // GPIO4_20引脚输出高电平，绿灯灭
+	}
+
+	/*设置 GPIO4_19 输出电平*/
+	if (write_data & 0x01)
+	{
+		register_data = readl(led_blue.virtual_DR);
+		register_data &= ~(0x01 << 19);
+		writel(register_data, led_blue.virtual_DR); //GPIO4_19引脚输出低电平，蓝灯亮
+	}
+	else
+	{
+		register_data = readl(led_blue.virtual_DR);
+		register_data |= (0x01 << 19);
+		writel(register_data, led_blue.virtual_DR); //GPIO4_19引脚输出高电平，蓝灯灭
+	}
+
+	return 0;
+}
+
+/*字符设备操作函数集*/
+static struct file_operations led_chr_dev_fops =
+	{
+		.owner = THIS_MODULE,
+		.open = led_chr_dev_open,
+		.write = led_chr_dev_write,
+};
+
+/*----------------平台驱动函数集-----------------*/
+static int led_probe(struct platform_device *pdv)
+{
+
+	int ret = -1; //保存错误状态码
+	unsigned int register_data = 0;
+
+	printk(KERN_EMERG "\t  match successed  \n");
+
+	/*获取rgb_led的设备树节点*/
+	rgb_led_device_node = of_find_node_by_path("/rgb_led");
+	if (rgb_led_device_node == NULL)
+	{
+		printk(KERN_ERR "\t  get rgb_led failed!  \n");
+		return -1;
+	}
+
+	/*获取rgb_led节点的红灯子节点*/
+	led_red.device_node = of_find_node_by_name(rgb_led_device_node,"rgb_led_red");
+	if (led_red.device_node == NULL)
+	{
+		printk(KERN_ERR "\n get rgb_led_red_device_node failed ! \n");
+		return -1;
+	}
+
+
+	/*获取 reg 属性并转化为虚拟地址*/
+	led_red.virtual_CCM_CCGR = of_iomap(led_red.device_node, 0);
+	led_red.virtual_IOMUXC_SW_MUX_CTL_PAD = of_iomap(led_red.device_node, 1);
+	led_red.virtual_IOMUXC_SW_PAD_CTL_PAD = of_iomap(led_red.device_node, 2);
+	led_red.virtual_DR = of_iomap(led_red.device_node, 3);
+	led_red.virtual_GDIR = of_iomap(led_red.device_node, 4);
+
+	/*初始化红灯*/
+	register_data = readl(led_red.virtual_CCM_CCGR);
+	register_data |= (0x03 << 26);
+	writel(register_data, led_red.virtual_CCM_CCGR); //开启时钟
+
+	register_data = readl(led_red.virtual_IOMUXC_SW_MUX_CTL_PAD);
+	register_data &= ~(0xf << 0);
+	register_data |= (0x05 << 0);
+	writel(register_data, led_red.virtual_IOMUXC_SW_MUX_CTL_PAD); //设置复用功能
+
+	register_data = readl(led_red.virtual_IOMUXC_SW_PAD_CTL_PAD);
+	register_data = (0x10B0);
+	writel(register_data, led_red.virtual_IOMUXC_SW_PAD_CTL_PAD); //设置PAD 属性
+
+	register_data = readl(led_red.virtual_GDIR);
+	register_data |= (0x01 << 4);
+	writel(register_data, led_red.virtual_GDIR); //设置GPIO1_04 为输出模式
+
+	register_data = readl(led_red.virtual_DR);
+	register_data |= (0x01 << 4);
+	writel(register_data, led_red.virtual_DR); //设置 GPIO1_04 默认输出高电平
+
+
+
+
+
+
+	/*获取rgb_led节点的绿灯子节点*/
+	led_green.device_node = of_find_node_by_name(rgb_led_device_node,"rgb_led_green");
+	if (led_green.device_node == NULL)
+	{
+		printk(KERN_ERR "\n get rgb_led_green_device_node failed ! \n");
+		return -1;
+	}
+
+	/*获取 reg 属性并转化为虚拟地址*/
+	led_green.virtual_CCM_CCGR = of_iomap(led_green.device_node, 0);
+	led_green.virtual_IOMUXC_SW_MUX_CTL_PAD = of_iomap(led_green.device_node, 1);
+	led_green.virtual_IOMUXC_SW_PAD_CTL_PAD = of_iomap(led_green.device_node, 2);
+	led_green.virtual_DR = of_iomap(led_green.device_node, 3);
+	led_green.virtual_GDIR = of_iomap(led_green.device_node, 4);
+
+	/*初始化绿灯*/
+	register_data = readl(led_green.virtual_CCM_CCGR);
+	register_data |= (0x03 << 12);
+	writel(register_data, led_green.virtual_CCM_CCGR); //开启时钟
+
+	register_data = readl(led_green.virtual_IOMUXC_SW_MUX_CTL_PAD);
+	register_data &= ~(0xf << 0);
+	register_data |= (0x05 << 0);
+	writel(register_data, led_green.virtual_IOMUXC_SW_MUX_CTL_PAD); //设置复用功能
+
+	register_data = readl(led_green.virtual_IOMUXC_SW_PAD_CTL_PAD);
+	register_data = (0x10B0);
+	writel(register_data, led_green.virtual_IOMUXC_SW_PAD_CTL_PAD); //设置PAD 属性
+
+	register_data = readl(led_green.virtual_GDIR);
+	register_data |= (0x01 << 20);
+	writel(register_data, led_green.virtual_GDIR); //设置GPIO4_IO20 为输出模式
+
+	register_data = readl(led_green.virtual_DR);
+	register_data |= (0x01 << 20);
+	writel(register_data, led_green.virtual_DR); //设置 GPIO4_IO20 默认输出高电平
+
+
+
+
+
+
+	/*获取rgb_led节点的蓝灯子节点*/
+	led_blue.device_node = of_find_node_by_name(rgb_led_device_node,"rgb_led_blue");
+	if (led_blue.device_node == NULL)
+	{
+		printk(KERN_ERR "\n get rgb_led_blue_device_node failed ! \n");
+		return -1;
+	}
+
+	/*获取 reg 属性并转化为虚拟地址*/
+	led_blue.virtual_CCM_CCGR = of_iomap(led_blue.device_node, 0);
+	led_blue.virtual_IOMUXC_SW_MUX_CTL_PAD = of_iomap(led_blue.device_node, 1);
+	led_blue.virtual_IOMUXC_SW_PAD_CTL_PAD = of_iomap(led_blue.device_node, 2);
+	led_blue.virtual_DR = of_iomap(led_blue.device_node, 3);
+	led_blue.virtual_GDIR = of_iomap(led_blue.device_node, 4);
+
+	/*初始化蓝灯*/
+	register_data = readl(led_blue.virtual_CCM_CCGR);
+	register_data |= (0x03 << 12);
+	writel(register_data, led_blue.virtual_CCM_CCGR); //开启时钟
+
+	register_data = readl(led_blue.virtual_IOMUXC_SW_MUX_CTL_PAD);
+	register_data &= ~(0xf << 0);
+	register_data |= (0x05 << 0);
+	writel(register_data, led_blue.virtual_IOMUXC_SW_MUX_CTL_PAD); //设置复用功能
+
+	register_data = readl(led_blue.virtual_IOMUXC_SW_PAD_CTL_PAD);
+	register_data = (0x10B0);
+	writel(register_data, led_blue.virtual_IOMUXC_SW_PAD_CTL_PAD); //设置PAD 属性
+
+	register_data = readl(led_blue.virtual_GDIR);
+	register_data |= (0x01 << 19);
+	writel(register_data, led_blue.virtual_GDIR); //设置GPIO4_IO19 为输出模式
+
+	register_data = readl(led_blue.virtual_DR);
+	register_data |= (0x01 << 19);
+	writel(register_data, led_blue.virtual_DR); //设置 GPIO4_IO19 默认输出高电平
+
+
+
+
+
+
+
+
+	/*---------------------注册 字符设备部分-----------------*/
+
+	//第一步
+	//采用动态分配的方式，获取设备编号，次设备号为0，
+	//设备名称为rgb-leds，可通过命令cat  /proc/devices查看
+	//DEV_CNT为1，当前只申请一个设备编号
+	ret = alloc_chrdev_region(&led_devno, 0, DEV_CNT, DEV_NAME);
+	if (ret < 0)
+	{
+		printk("fail to alloc led_devno\n");
+		goto alloc_err;
+	}
+	//第二步
+	//关联字符设备结构体cdev与文件操作结构体file_operations
+	led_chr_dev.owner = THIS_MODULE;
+	cdev_init(&led_chr_dev, &led_chr_dev_fops);
+	//第三步
+	//添加设备至cdev_map散列表中
+	ret = cdev_add(&led_chr_dev, led_devno, DEV_CNT);
+	if (ret < 0)
+	{
+		printk("fail to add cdev\n");
+		goto add_err;
+	}
+
+	//第四步
+	/*创建类 */
+	class_led = class_create(THIS_MODULE, DEV_NAME);
+
+	/*创建设备*/
+	device = device_create(class_led, NULL, led_devno, NULL, DEV_NAME);
+
+	return 0;
+
+add_err:
+	//添加设备失败时，需要注销设备号
+	unregister_chrdev_region(led_devno, DEV_CNT);
+	printk("\n error! \n");
+alloc_err:
+
+	return -1;
+}
+
+static const struct of_device_id rgb_led[] = {
+	{.compatible = "fire,rgb_led"},
+	{/* sentinel */}};
+
+/*定义平台设备结构体*/
+struct platform_driver led_platform_driver = {
+	.probe = led_probe,
+	.driver = {
+		.name = "rgb-leds-platform",
+		.owner = THIS_MODULE,
+		.of_match_table = rgb_led,
+	}};
+
+/*
+*驱动初始化函数
+*/
+static int __init led_platform_driver_init(void)
+{
+	int DriverState;
+	DriverState = platform_driver_register(&led_platform_driver);
+	printk(KERN_EMERG "\tDriverState is %d\n", DriverState);
+	return 0;
+}
+
+/*
+*驱动注销函数
+*/
+static void __exit led_platform_driver_exit(void)
+{
+	/*取消物理地址映射到虚拟地址*/
+	iounmap(led_green.virtual_CCM_CCGR);
+	iounmap(led_green.virtual_IOMUXC_SW_MUX_CTL_PAD);
+	iounmap(led_green.virtual_IOMUXC_SW_PAD_CTL_PAD);
+	iounmap(led_green.virtual_DR);
+	iounmap(led_green.virtual_GDIR);
+
+	iounmap(led_red.virtual_CCM_CCGR);
+	iounmap(led_red.virtual_IOMUXC_SW_MUX_CTL_PAD);
+	iounmap(led_red.virtual_IOMUXC_SW_PAD_CTL_PAD);
+	iounmap(led_red.virtual_DR);
+	iounmap(led_red.virtual_GDIR);
+
+	iounmap(led_blue.virtual_CCM_CCGR);
+	iounmap(led_blue.virtual_IOMUXC_SW_MUX_CTL_PAD);
+	iounmap(led_blue.virtual_IOMUXC_SW_PAD_CTL_PAD);
+	iounmap(led_blue.virtual_DR);
+	iounmap(led_blue.virtual_GDIR);
+
+	/*删除设备*/
+	device_destroy(class_led, led_devno);		  //清除设备
+	class_destroy(class_led);					  //清除类
+	cdev_del(&led_chr_dev);						  //清除设备号
+	unregister_chrdev_region(led_devno, DEV_CNT); //取消注册字符设备
+
+	/*注销字符设备*/
+	platform_driver_unregister(&led_platform_driver);
+
+	printk(KERN_EMERG "HELLO WORLD exit!\n");
+}
+
+module_init(led_platform_driver_init);
+module_exit(led_platform_driver_exit);
+
+MODULE_LICENSE("GPL");
+
+/**/
diff --git a/base_code/linux_driver/device_tree_rgb_led/test_app.c b/base_code/linux_driver/device_tree_rgb_led/test_app.c
new file mode 100644
index 0000000000000000000000000000000000000000..89bea9f4ac505ef804e0f25cbbf5c0acf1f079d2
--- /dev/null
+++ b/base_code/linux_driver/device_tree_rgb_led/test_app.c
@@ -0,0 +1,44 @@
+#include <stdio.h>
+#include <unistd.h>
+#include <fcntl.h>
+#include <string.h>
+int main(int argc, char *argv[])
+{
+    printf("led_tiny test\n");
+    /*判断输入的命令是否合法*/
+    if(argc != 2)
+    {
+        printf(" commend error ! \n");
+        return -1;
+    }
+
+
+    /*打开文件*/
+    int fd = open("/dev/rgb_led", O_RDWR);
+    if(fd < 0)
+    {
+		printf("open file : %s failed !\n", argv[0]);
+		return -1;
+	}
+
+    unsigned char commend = atoi(argv[1]);  //将受到的命令值转化为数字;
+
+
+    /*写入命令*/
+    int error = write(fd,&commend,sizeof(commend));
+    if(error < 0)
+    {
+        printf("write file error! \n");
+        close(fd);
+        /*判断是否关闭成功*/
+    }
+
+    /*关闭文件*/
+    error = close(fd);
+    if(error < 0)
+    {
+        printf("close file error! \n");
+    }
+    
+    return 0;
+}
\ No newline at end of file
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/.gitignore b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/.gitignore
new file mode 100644
index 0000000000000000000000000000000000000000..15411c94778a59d7cdca3348164497208ed8a0e9
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/.gitignore
@@ -0,0 +1,3 @@
+*.cmd
+*.tmp
+config-pin
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/Makefile b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..f8f965ab3a92d5f6dccd37a5d0ceb9940b3c1a3f
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/Makefile
@@ -0,0 +1,245 @@
+
+DTC ?= dtc
+CPP ?= cpp
+DESTDIR ?=
+
+DTCVERSION ?= $(shell $(DTC) --version | grep ^Version | sed 's/^.* //g')
+
+MAKEFLAGS += -rR --no-print-directory
+
+ALL_PLATFORMES := $(patsubst overlays/%,%,$(wildcard overlays/*))
+
+PHONY += all
+all: $(foreach i,$(ALL_PLATFORMES),all_$(i))
+
+PHONY += clean
+clean: $(foreach i,$(ALL_PLATFORMES),clean_$(i))
+
+PHONY += install
+install: $(foreach i,$(ALL_PLATFORMES),install_$(i))
+
+# Do not:
+# o  use make's built-in rules and variables
+#    (this increases performance and avoids hard-to-debug behaviour);
+# o  print "Entering directory ...";
+MAKEFLAGS += -rR --no-print-directory
+
+# To put more focus on warnings, be less verbose as default
+# Use 'make V=1' to see the full commands
+
+ifeq ("$(origin V)", "command line")
+  KBUILD_VERBOSE = $(V)
+endif
+ifndef KBUILD_VERBOSE
+  KBUILD_VERBOSE = 0
+endif
+
+DTC_FLAGS += -Wno-unit_address_vs_reg
+#http://snapshot.debian.org/binary/device-tree-compiler/
+#http://snapshot.debian.org/package/device-tree-compiler/1.4.4-1/#device-tree-compiler_1.4.4-1
+#http://snapshot.debian.org/archive/debian/20170925T220404Z/pool/main/d/device-tree-compiler/device-tree-compiler_1.4.4-1_amd64.deb
+
+ifeq "$(DTCVERSION)" "1.4.5"
+	#GIT BROKEN!!!! Ubuntu Bionic has patches..
+	DTC_FLAGS += -Wno-dmas_property
+	DTC_FLAGS += -Wno-gpios_property
+	DTC_FLAGS += -Wno-pwms_property
+	DTC_FLAGS += -Wno-interrupts_property
+endif
+
+ifeq "$(DTCVERSION)" "1.4.6"
+	#http://snapshot.debian.org/package/device-tree-compiler/1.4.6-1/#device-tree-compiler_1.4.6-1
+	#http://snapshot.debian.org/archive/debian/20180426T224735Z/pool/main/d/device-tree-compiler/device-tree-compiler_1.4.6-1_amd64.deb
+	#Debian: 1.4.6
+	DTC_FLAGS += -Wno-chosen_node_is_root
+	DTC_FLAGS += -Wno-alias_paths
+	DTC_FLAGS += -Wno-avoid_unnecessary_addr_size
+endif
+
+ifeq "$(DTCVERSION)" "1.4.7"
+	#http://snapshot.debian.org/package/device-tree-compiler/1.4.7-3/#device-tree-compiler_1.4.7-3
+	#http://snapshot.debian.org/archive/debian/20180911T215003Z/pool/main/d/device-tree-compiler/device-tree-compiler_1.4.7-3_amd64.deb
+	#Debian: 1.4.6
+	DTC_FLAGS += -Wno-chosen_node_is_root
+	DTC_FLAGS += -Wno-alias_paths
+	DTC_FLAGS += -Wno-avoid_unnecessary_addr_size
+endif
+
+ifeq "$(DTCVERSION)" "1.5.0"
+	#http://snapshot.debian.org/package/device-tree-compiler/1.5.0-1/#device-tree-compiler_1.5.0-1
+	#http://snapshot.debian.org/archive/debian/20190313T032949Z/pool/main/d/device-tree-compiler/device-tree-compiler_1.5.0-1_amd64.deb
+	#Debian: 1.4.6
+	DTC_FLAGS += -Wno-chosen_node_is_root
+	DTC_FLAGS += -Wno-alias_paths
+	DTC_FLAGS += -Wno-avoid_unnecessary_addr_size
+endif
+
+ifeq "$(DTCVERSION)" "2.0.0"
+	#BUILDBOT...http://gfnd.rcn-ee.org:8080/job/beagleboard_overlays/job/master/
+	DTC_FLAGS += -Wno-chosen_node_is_root
+	DTC_FLAGS += -Wno-alias_paths
+endif
+
+# Beautify output
+# ---------------------------------------------------------------------------
+#
+# Normally, we echo the whole command before executing it. By making
+# that echo $($(quiet)$(cmd)), we now have the possibility to set
+# $(quiet) to choose other forms of output instead, e.g.
+#
+#         quiet_cmd_cc_o_c = Compiling $(RELDIR)/$@
+#         cmd_cc_o_c       = $(CC) $(c_flags) -c -o $@ $<
+#
+# If $(quiet) is empty, the whole command will be printed.
+# If it is set to "quiet_", only the short version will be printed. 
+# If it is set to "silent_", nothing will be printed at all, since
+# the variable $(silent_cmd_cc_o_c) doesn't exist.
+#
+# A simple variant is to prefix commands with $(Q) - that's useful
+# for commands that shall be hidden in non-verbose mode.
+#
+#       $(Q)ln $@ :<
+#
+# If KBUILD_VERBOSE equals 0 then the above command will be hidden.
+# If KBUILD_VERBOSE equals 1 then the above command is displayed.
+
+ifeq ($(KBUILD_VERBOSE),1)
+  quiet =
+  Q =
+else
+  quiet=quiet_
+  Q = @
+endif
+
+# If the user is running make -s (silent mode), suppress echoing of
+# commands
+
+ifneq ($(filter 4.%,$(MAKE_VERSION)),)	# make-4
+ifneq ($(filter %s ,$(firstword x$(MAKEFLAGS))),)
+  quiet=silent_
+endif
+else					# make-3.8x
+ifneq ($(filter s% -s%,$(MAKEFLAGS)),)
+  quiet=silent_
+endif
+endif
+
+export quiet Q KBUILD_VERBOSE
+
+all_%:
+	$(Q)$(MAKE) PLATFORM=$* all_arch
+	gcc -o config-pin ./tools/pmunts_muntsos/config-pin.c
+
+clean_%:
+	$(Q)$(MAKE) PLATFORM=$* clean_arch
+	rm config-pin || true
+	rm -rf output
+
+install_%:
+	$(Q)$(MAKE) PLATFORM=$* install_arch
+
+ifeq ($(PLATFORM),)
+
+ALL_DTS		:= $(shell find overlays/* -name \*.dts)
+
+ALL_DTB		:= $(patsubst %.dts,%.dtbo,$(ALL_DTS))
+
+$(ALL_DTB): PLATFORM=$(word 2,$(subst /, ,$@))
+$(ALL_DTB): FORCE
+	$(Q)$(MAKE) PLATFORM=$(PLATFORM) $@
+
+else
+
+PLATFORM_DTS	:= $(shell find overlays/$(PLATFORM) -name \*.dts)
+
+PLATFORM_DTB	:= $(patsubst %.dts,%.dtbo,$(PLATFORM_DTS))
+
+src	:= overlays/$(PLATFORM)
+obj	:= overlays/$(PLATFORM)
+
+include scripts/Kbuild.include
+
+cmd_files := $(wildcard $(foreach f,$(PLATFORM_DTB),$(dir $(f)).$(notdir $(f)).cmd))
+
+ifneq ($(cmd_files),)
+  include $(cmd_files)
+endif
+
+quiet_cmd_clean    = CLEAN   $(obj)
+      cmd_clean    = rm -f $(__clean-files)
+
+dtc-tmp = $(subst $(comma),_,$(dot-target).dts.tmp)
+
+dtc_cpp_flags  = -Wp,-MD,$(depfile).pre.tmp -nostdinc		\
+                 -Iinclude -I$(src) -Ioverlays -Itestcase-data	\
+                 -undef -D__DTS__
+
+quiet_cmd_dtc = DTC     $@
+cmd_dtc = $(CPP) $(dtc_cpp_flags) -x assembler-with-cpp -o $(dtc-tmp) $< ; \
+        $(DTC) -O dtb -o $@ -b 0 -@ \
+                -i $(src) $(DTC_FLAGS) \
+                -d $(depfile).dtc.tmp $(dtc-tmp) ; \
+        cat $(depfile).pre.tmp $(depfile).dtc.tmp > $(depfile)
+
+$(obj)/%.dtbo: $(src)/%.dts FORCE | create_output
+	$(call if_changed_dep,dtc)
+	@mv $@ output
+
+create_output: 
+	@mkdir -p output
+
+PHONY += all_arch
+all_arch: $(PLATFORM_DTB)
+	@:
+
+PHONY += install_arch
+install_arch: $(PLATFORM_DTBO)
+	mkdir -p $(DESTDIR)/lib/firmware/
+	cp -v $(obj)/*.dtbo $(DESTDIR)/lib/firmware/
+	mkdir -p $(DESTDIR)/usr/bin/
+	cp -v config-pin $(DESTDIR)/usr/bin/
+
+RCS_FIND_IGNORE := \( -name SCCS -o -name BitKeeper -o -name .svn -o -name CVS \
+                   -o -name .pc -o -name .hg -o -name .git \) -prune -o
+
+PHONY += clean_arch
+clean_arch: __clean-files = $(PLATFORM_DTB)
+clean_arch: FORCE
+	$(call cmd,clean)
+	@find . $(RCS_FIND_IGNORE) \
+		\( -name '.*.cmd' \
+		-o -name '.*.d' \
+		-o -name '.*.tmp' \
+		\) -type f -print | xargs rm -f
+
+endif
+
+help:
+	@echo "Targets:"
+	@echo "  all:                   Build all device tree binaries for all architectures"
+	@echo "  clean:                 Clean all generated files"
+	@echo "  install:               Install all generated files (sudo)"
+	@echo ""
+	@echo "  all_<PLATFORM>:            Build all device tree binaries for <PLATFORM>"
+	@echo "  clean_<PLATFORM>:          Clean all generated files for <PLATFORM>"
+	@echo "  install_<PLATFORM>:        Install all generated files for <PLATFORM> (sudo)"
+	@echo ""
+	@echo "  overlays/<PLATFORM>/<DTS>.dtbo   Build a single device tree binary"
+	@echo ""
+	@echo "Architectures: $(ALL_PLATFORMES)"
+
+PHONY += FORCE
+FORCE:
+
+.PHONY: $(PHONY)
+
+
+builddeb:
+	# build the source package in the parent directory
+	# then rename it to project_version.orig.tar.gz
+	#$(PYTHON) setup.py sdist $(COMPILE) --dist-dir=../
+	#rename -f 's/$(PROJECT)-(.*)\.tar\.gz/$(PROJECT)_$$1\.orig\.tar\.gz/' ../*
+	# build the package
+	./install.sh
+	dpkg-buildpackage -i -I -rfakeroot
+
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/README.md b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/README.md
new file mode 100644
index 0000000000000000000000000000000000000000..b671a80be67d926d6edef0d8acb59c7eb6adbf24
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/README.md
@@ -0,0 +1,39 @@
+# 内核配置
+
+## dth11/dsb18b20——单总线设备驱动
+ ->Device Drivers
+->Dallas's 1-wire support<*>
+
+
+
+## WM8960
+-> Device Drivers 
+  -> Sound card support 
+    -> Advanced Linux Sound Architecture
+        -> ALSA for SoC audio support 
+            -> CODEC drivers
+                -> Wolfson Microelectronics WM8960 CODEC< >
+
+PS：使用声卡驱动是需要配置声卡
+
+## 摄像头
+  ->Device Drivers 
+   -> Multimedia support 
+    -> V4L platform devices-
+      -> MXC Camera/V4L2 PRP Features support
+        -> OmniVision ov5640 camera support<M> 
+        ->OmniVision ov5640 camera support < > 
+
+
+## AP6236
+  -> Device Drivers               
+    -> Network device support                                         
+       -> Wireless LAN
+        <*>   Broadcom FullMAC wireless cards support                        
+                (/lib/firmware/bcm/AP6236/Wi-Fi/fw_bcm43436b0.bin) Firmware path     
+                (/lib/firmware/bcm/AP6236/Wi-Fi/nvram_ap6236.txt) NVRAM path   
+
+需要修改net/wireless/文件夹下的Kconfig和Makefile，并且需要把wifi固件放到对应的文件夹
+
+
+
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/board/am335x-bbw-bbb-base.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/board/am335x-bbw-bbb-base.h
new file mode 100644
index 0000000000000000000000000000000000000000..ad745f042c7056c5d8618d95d4194dea97f183e7
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/board/am335x-bbw-bbb-base.h
@@ -0,0 +1,108 @@
+/*
+ * This header provides constants for bbw/bbb pinctrl bindings.
+ *
+ * Copyright (C) 2014 Robert Nelson <robertcnelson@gmail.com>
+ *
+ * Numbers Based on: https://github.com/derekmolloy/boneDeviceTree/tree/master/docs
+ */
+
+#ifndef _DT_BINDINGS_BOARD_AM335X_BBW_BBB_BASE_H
+#define _DT_BINDINGS_BOARD_AM335X_BBW_BBB_BASE_H
+
+#define BONE_P8_03 0x018
+#define BONE_P8_04 0x01C
+
+#define BONE_P8_05 0x008
+#define BONE_P8_06 0x00C
+#define BONE_P8_07 0x090
+#define BONE_P8_08 0x094
+
+#define BONE_P8_09 0x09C
+#define BONE_P8_10 0x098
+#define BONE_P8_11 0x034
+#define BONE_P8_12 0x030
+
+#define BONE_P8_13 0x024
+#define BONE_P8_14 0x028
+#define BONE_P8_15 0x03C
+#define BONE_P8_16 0x038
+
+#define BONE_P8_17 0x02C
+#define BONE_P8_18 0x08C
+#define BONE_P8_19 0x020
+#define BONE_P8_20 0x084
+
+#define BONE_P8_21 0x080
+#define BONE_P8_22 0x014
+#define BONE_P8_23 0x010
+#define BONE_P8_24 0x004
+
+#define BONE_P8_25 0x000
+#define BONE_P8_26 0x07C
+#define BONE_P8_27 0x0E0
+#define BONE_P8_28 0x0E8
+
+#define BONE_P8_29 0x0E4
+#define BONE_P8_30 0x0EC
+#define BONE_P8_31 0x0D8
+#define BONE_P8_32 0x0DC
+
+#define BONE_P8_33 0x0D4
+#define BONE_P8_34 0x0CC
+#define BONE_P8_35 0x0D0
+#define BONE_P8_36 0x0C8
+
+#define BONE_P8_37 0x0C0
+#define BONE_P8_38 0x0C4
+#define BONE_P8_39 0x0B8
+#define BONE_P8_40 0x0BC
+
+#define BONE_P8_41 0x0B0
+#define BONE_P8_42 0x0B4
+#define BONE_P8_43 0x0A8
+#define BONE_P8_44 0x0AC
+
+#define BONE_P8_45 0x0A0
+#define BONE_P8_46 0x0A4
+
+#define BONE_P9_11 0x070
+#define BONE_P9_12 0x078
+
+#define BONE_P9_13 0x074
+#define BONE_P9_14 0x048
+#define BONE_P9_15 0x040
+#define BONE_P9_16 0x04C
+
+#define BONE_P9_17 0x15C
+#define BONE_P9_18 0x158
+#define BONE_P9_19 0x17C
+#define BONE_P9_20 0x178
+
+#define BONE_P9_21 0x154
+#define BONE_P9_22 0x150
+#define BONE_P9_23 0x044
+#define BONE_P9_24 0x184
+
+#define BONE_P9_25 0x1AC
+#define BONE_P9_26 0x180
+#define BONE_P9_27 0x1A4
+#define BONE_P9_28 0x19C
+
+#define BONE_P9_29 0x194
+#define BONE_P9_30 0x198
+#define BONE_P9_31 0x190
+
+/* Shared P21 of P11 */
+#define BONE_P9_41 0x1B4
+#define BONE_P9_41A 0x1B4
+#define BONE_P9_41B 0x1A8
+#define BONE_P9_91 0x1A8
+
+/* Shared P22 of P11 */
+#define BONE_P9_42 0x164
+#define BONE_P9_42A 0x164
+#define BONE_P9_42B 0x1A0
+#define BONE_P9_92 0x1A0
+
+#endif
+
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/board/am335x-pb-base.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/board/am335x-pb-base.h
new file mode 100644
index 0000000000000000000000000000000000000000..ea5f17704aa5247ec38b6153a16f4435de173bf9
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/board/am335x-pb-base.h
@@ -0,0 +1,207 @@
+/*
+ * This header provides constants for PocketBeagle pinctrl bindings.
+ *
+ * Copyright (C) 2019 Jason Kridner <jdk@ti.com>
+ */
+
+#ifndef _DT_BINDINGS_BOARD_AM335X_PB_BASE_H
+#define _DT_BINDINGS_BOARD_AM335X_PB_BASE_H
+
+
+/************************/
+/* P1 Header */
+/************************/
+
+/* P1_01                VIN-AC */
+
+/* P1_02 (ZCZ ball R5) gpio2_23 */
+#define PB_P1_02 0x08e4
+
+/* P1_03 (ZCZ ball F15)  usb1_vbus_out         */
+
+/* P1_04 (ZCZ ball R6) gpio2_25 */
+
+#define PB_P1_04 0x08ec
+/* P1_05 (ZCZ ball T18)  usb1_vbus_in         */
+
+/* P1_06 (ZCZ ball A16) spi0_cs0 */
+#define PB_P1_06 0x095c
+
+/* P1_07                VIN-USB */
+
+/* P1_08 (ZCZ ball A17) spi0_sclk */
+
+#define PB_P1_08 0x0950
+/* P1_09 (ZCZ ball R18)  USB1-DN         */
+
+/* P1_10 (ZCZ ball B17) spi0_d0 */
+#define PB_P1_10 0x0954
+
+/* P1_11 (ZCZ ball R17)  USB1-DP         */
+
+/* P1_12 (ZCZ ball B16) spi0_d1 */
+#define PB_P1_12 0x0958
+
+/* P1_13 (ZCZ ball P17)  USB1-ID         */
+
+/* P1_14                VOUT-3.3V */
+
+/* P1_15                GND */
+
+/* P1_16                GND */
+
+/* P1_17 (ZCZ ball A9)  VREFN         */
+
+/* P1_18 (ZCZ ball B9)  VREFP         */
+
+/* P1_19 (ZCZ ball B6)  AIN0         */
+
+/* P1_20 (ZCZ ball D14) gpio0_20 */
+#define PB_P1_20 0x09b4
+
+/* P1_21 (ZCZ ball C7)  AIN1         */
+
+/* P1_22                GND */
+
+/* P1_23 (ZCZ ball B7)  AIN2         */
+
+/* P1_24                VOUT-5V */
+
+/* P1_25 (ZCZ ball A7)  AIN3         */
+
+/* P1_26 (ZCZ ball D18) i2c2_sda */
+#define PB_P1_26 0x0978
+
+/* P1_27 (ZCZ ball C8)  AIN4         */
+
+/* P1_28 (ZCZ ball D17) i2c2_scl */
+#define PB_P1_28 0x097c
+
+/* P1_29 (ZCZ ball A14) pru0_in7 */
+#define PB_P1_29 0x09ac
+
+/* P1_30 (ZCZ ball E16) uart0_txd */
+#define PB_P1_30 0x0974
+
+/* P1_31 (ZCZ ball B12) pru0_in4 */
+#define PB_P1_31 0x09a0
+
+/* P1_32 (ZCZ ball E15) uart0_rxd */
+#define PB_P1_32 0x0970
+
+/* P1_33 (ZCZ ball B13) pru0_in1 */
+#define PB_P1_33 0x0994
+
+/* P1_34 (ZCZ ball T11) gpio0_26 */
+#define PB_P1_34 0x0828
+
+/* P1_35 (ZCZ ball V5) pru1_in10 */
+#define PB_P1_35 0x08e8
+
+/* P1_36 (ZCZ ball A13) ehrpwm0a */
+#define PB_P1_36 0x0990
+
+
+/************************/
+/* P2 Header */
+/************************/
+
+/* P2_01 (ZCZ ball U14) ehrpwm1a */
+#define PB_P2_01 0x0848
+
+/* P2_02 (ZCZ ball V17) gpio1_27 */
+#define PB_P2_02 0x086c
+
+/* P2_03 (ZCZ ball T10) gpio0_23 */
+#define PB_P2_03 0x0824
+
+/* P2_04 (ZCZ ball T16) gpio1_26 */
+#define PB_P2_04 0x0868
+
+/* P2_05 (ZCZ ball T17) uart4_rxd */
+#define PB_P2_05 0x0870
+
+/* P2_06 (ZCZ ball U16) gpio1_25 */
+#define PB_P2_06 0x0864
+
+/* P2_07 (ZCZ ball U17) uart4_txd */
+#define PB_P2_07 0x0874
+
+/* P2_08 (ZCZ ball U18) gpio1_28 */
+#define PB_P2_08 0x0878
+
+/* P2_09 (ZCZ ball D15) i2c1_scl */
+#define PB_P2_09 0x0984
+
+/* P2_10 (ZCZ ball R14) gpio1_20 */
+#define PB_P2_10 0x0850
+
+/* P2_11 (ZCZ ball D16) i2c1_sda */
+#define PB_P2_11 0x0980
+
+/* P2_12                POWER_BUTTON */
+
+/* P2_13                VOUT-5V */
+
+/* P2_14                BAT-VIN */
+
+/* P2_15                GND */
+
+/* P2_16                BAT-TEMP */
+
+/* P2_17 (ZCZ ball V12) gpio2_1 */
+#define PB_P2_17 0x088c
+
+/* P2_18 (ZCZ ball U13) gpio1_15 */
+#define PB_P2_18 0x083c
+
+/* P2_19 (ZCZ ball U12) gpio0_27 */
+#define PB_P2_19 0x082c
+
+/* P2_20 (ZCZ ball T13) gpio2_0 */
+#define PB_P2_20 0x0888
+
+/* P2_21                GND */
+
+/* P2_22 (ZCZ ball V13) gpio1_14 */
+#define PB_P2_22 0x0838
+
+/* P2_23                VOUT-3.3V */
+
+/* P2_24 (ZCZ ball T12) gpio1_12 */
+#define PB_P2_24 0x0830
+
+/* P2_25 (ZCZ ball E17) spi1_d1 */
+#define PB_P2_25 0x096c
+
+/* P2_26                RESET# */
+
+/* P2_27 (ZCZ ball E18) spi1_d0 */
+#define PB_P2_27 0x0968
+
+/* P2_28 (ZCZ ball D13) pru0_in6 */
+#define PB_P2_28 0x09a8
+
+/* P2_29 (ZCZ ball C18) spi1_sclk */
+#define PB_P2_29 0x0964
+
+/* P2_30 (ZCZ ball C12) pru0_in3 */
+#define PB_P2_30 0x099c
+
+/* P2_31 (ZCZ ball A15) spi1_cs1 */
+#define PB_P2_31 0x09b0
+
+/* P2_32 (ZCZ ball D12) pru0_in2 */
+#define PB_P2_32 0x0998
+
+/* P2_33 (ZCZ ball R12) gpio1_13 */
+#define PB_P2_33 0x0834
+
+/* P2_34 (ZCZ ball C13) pru0_in5 */
+#define PB_P2_34 0x09a4
+
+/* P2_35 (ZCZ ball U5) gpio2_22 */
+#define PB_P2_35 0x08e0
+
+/* P2_36 (ZCZ ball C9)  AIN7         */
+#endif
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/actions,s700-cmu.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/actions,s700-cmu.h
new file mode 100644
index 0000000000000000000000000000000000000000..3e19429967241961d85ad006d62319314a227a88
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/actions,s700-cmu.h
@@ -0,0 +1,118 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Device Tree binding constants for Actions Semi S700 Clock Management Unit
+ *
+ * Copyright (c) 2014 Actions Semi Inc.
+ * Author: David Liu <liuwei@actions-semi.com>
+ *
+ * Author: Pathiban Nallathambi <pn@denx.de>
+ * Author: Saravanan Sekar <sravanhome@gmail.com>
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_S700_H
+#define __DT_BINDINGS_CLOCK_S700_H
+
+#define CLK_NONE			0
+
+/* pll clocks */
+#define CLK_CORE_PLL			1
+#define CLK_DEV_PLL			2
+#define CLK_DDR_PLL			3
+#define CLK_NAND_PLL			4
+#define CLK_DISPLAY_PLL			5
+#define CLK_TVOUT_PLL			6
+#define CLK_CVBS_PLL			7
+#define CLK_AUDIO_PLL			8
+#define CLK_ETHERNET_PLL		9
+
+/* system clock */
+#define CLK_CPU				10
+#define CLK_DEV				11
+#define CLK_AHB				12
+#define CLK_APB				13
+#define CLK_DMAC			14
+#define CLK_NOC0_CLK_MUX		15
+#define CLK_NOC1_CLK_MUX		16
+#define CLK_HP_CLK_MUX			17
+#define CLK_HP_CLK_DIV			18
+#define CLK_NOC1_CLK_DIV		19
+#define CLK_NOC0			20
+#define CLK_NOC1			21
+#define CLK_SENOR_SRC			22
+
+/* peripheral device clock */
+#define CLK_GPIO			23
+#define CLK_TIMER			24
+#define CLK_DSI				25
+#define CLK_CSI				26
+#define CLK_SI				27
+#define CLK_DE				28
+#define CLK_HDE				29
+#define CLK_VDE				30
+#define CLK_VCE				31
+#define CLK_NAND			32
+#define CLK_SD0				33
+#define CLK_SD1				34
+#define CLK_SD2				35
+
+#define CLK_UART0			36
+#define CLK_UART1			37
+#define CLK_UART2			38
+#define CLK_UART3			39
+#define CLK_UART4			40
+#define CLK_UART5			41
+#define CLK_UART6			42
+
+#define CLK_PWM0			43
+#define CLK_PWM1			44
+#define CLK_PWM2			45
+#define CLK_PWM3			46
+#define CLK_PWM4			47
+#define CLK_PWM5			48
+#define CLK_GPU3D			49
+
+#define CLK_I2C0			50
+#define CLK_I2C1			51
+#define CLK_I2C2			52
+#define CLK_I2C3			53
+
+#define CLK_SPI0			54
+#define CLK_SPI1			55
+#define CLK_SPI2			56
+#define CLK_SPI3			57
+
+#define CLK_USB3_480MPLL0		58
+#define CLK_USB3_480MPHY0		59
+#define CLK_USB3_5GPHY			60
+#define CLK_USB3_CCE			61
+#define CLK_USB3_MAC			62
+
+#define CLK_LCD				63
+#define CLK_HDMI_AUDIO			64
+#define CLK_I2SRX			65
+#define CLK_I2STX			66
+
+#define CLK_SENSOR0			67
+#define CLK_SENSOR1			68
+
+#define CLK_HDMI_DEV			69
+
+#define CLK_ETHERNET			70
+#define CLK_RMII_REF			71
+
+#define CLK_USB2H0_PLLEN		72
+#define CLK_USB2H0_PHY			73
+#define CLK_USB2H0_CCE			74
+#define CLK_USB2H1_PLLEN		75
+#define CLK_USB2H1_PHY			76
+#define CLK_USB2H1_CCE			77
+
+#define CLK_TVOUT			78
+
+#define CLK_THERMAL_SENSOR		79
+
+#define CLK_IRC_SWITCH			80
+#define CLK_PCM1			81
+#define CLK_NR_CLKS			(CLK_PCM1 + 1)
+
+#endif /* __DT_BINDINGS_CLOCK_S700_H */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/actions,s900-cmu.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/actions,s900-cmu.h
new file mode 100644
index 0000000000000000000000000000000000000000..7c1251565f43921dc69b0074c9f7732069df26a1
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/actions,s900-cmu.h
@@ -0,0 +1,129 @@
+// SPDX-License-Identifier: GPL-2.0+
+//
+// Device Tree binding constants for Actions Semi S900 Clock Management Unit
+//
+// Copyright (c) 2014 Actions Semi Inc.
+// Copyright (c) 2018 Linaro Ltd.
+
+#ifndef __DT_BINDINGS_CLOCK_S900_CMU_H
+#define __DT_BINDINGS_CLOCK_S900_CMU_H
+
+#define CLK_NONE			0
+
+/* fixed rate clocks */
+#define CLK_LOSC			1
+#define CLK_HOSC			2
+
+/* pll clocks */
+#define CLK_CORE_PLL			3
+#define CLK_DEV_PLL			4
+#define CLK_DDR_PLL			5
+#define CLK_NAND_PLL			6
+#define CLK_DISPLAY_PLL			7
+#define CLK_DSI_PLL			8
+#define CLK_ASSIST_PLL			9
+#define CLK_AUDIO_PLL			10
+
+/* system clock */
+#define CLK_CPU				15
+#define CLK_DEV				16
+#define CLK_NOC				17
+#define CLK_NOC_MUX			18
+#define CLK_NOC_DIV			19
+#define CLK_AHB				20
+#define CLK_APB				21
+#define CLK_DMAC			22
+
+/* peripheral device clock */
+#define CLK_GPIO			23
+
+#define CLK_BISP			24
+#define CLK_CSI0			25
+#define CLK_CSI1			26
+
+#define CLK_DE0				27
+#define CLK_DE1				28
+#define CLK_DE2				29
+#define CLK_DE3				30
+#define CLK_DSI				32
+
+#define CLK_GPU				33
+#define CLK_GPU_CORE			34
+#define CLK_GPU_MEM			35
+#define CLK_GPU_SYS			36
+
+#define CLK_HDE				37
+#define CLK_I2C0			38
+#define CLK_I2C1			39
+#define CLK_I2C2			40
+#define CLK_I2C3			41
+#define CLK_I2C4			42
+#define CLK_I2C5			43
+#define CLK_I2SRX			44
+#define CLK_I2STX			45
+#define CLK_IMX				46
+#define CLK_LCD				47
+#define CLK_NAND0			48
+#define CLK_NAND1			49
+#define CLK_PWM0			50
+#define CLK_PWM1			51
+#define CLK_PWM2			52
+#define CLK_PWM3			53
+#define CLK_PWM4			54
+#define CLK_PWM5			55
+#define CLK_SD0				56
+#define CLK_SD1				57
+#define CLK_SD2				58
+#define CLK_SD3				59
+#define CLK_SENSOR			60
+#define CLK_SPEED_SENSOR		61
+#define CLK_SPI0			62
+#define CLK_SPI1			63
+#define CLK_SPI2			64
+#define CLK_SPI3			65
+#define CLK_THERMAL_SENSOR		66
+#define CLK_UART0			67
+#define CLK_UART1			68
+#define CLK_UART2			69
+#define CLK_UART3			70
+#define CLK_UART4			71
+#define CLK_UART5			72
+#define CLK_UART6			73
+#define CLK_VCE				74
+#define CLK_VDE				75
+
+#define CLK_USB3_480MPLL0		76
+#define CLK_USB3_480MPHY0		77
+#define CLK_USB3_5GPHY			78
+#define CLK_USB3_CCE			79
+#define CLK_USB3_MAC			80
+
+#define CLK_TIMER			83
+
+#define CLK_HDMI_AUDIO			84
+
+#define CLK_24M				85
+
+#define CLK_EDP				86
+
+#define CLK_24M_EDP			87
+#define CLK_EDP_PLL			88
+#define CLK_EDP_LINK			89
+
+#define CLK_USB2H0_PLLEN		90
+#define CLK_USB2H0_PHY			91
+#define CLK_USB2H0_CCE			92
+#define CLK_USB2H1_PLLEN		93
+#define CLK_USB2H1_PHY			94
+#define CLK_USB2H1_CCE			95
+
+#define CLK_DDR0			96
+#define CLK_DDR1			97
+#define CLK_DMM				98
+
+#define CLK_ETH_MAC			99
+#define CLK_RMII_REF			100
+
+#define CLK_NR_CLKS			(CLK_RMII_REF + 1)
+
+#endif /* __DT_BINDINGS_CLOCK_S900_CMU_H */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/alphascale,asm9260.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/alphascale,asm9260.h
new file mode 100644
index 0000000000000000000000000000000000000000..04e8db27daf02d7851de13bce40fce1dfec1c41c
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/alphascale,asm9260.h
@@ -0,0 +1,97 @@
+/*
+ * Copyright 2014 Oleksij Rempel <linux@rempel-privat.de>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_CLK_ASM9260_H
+#define _DT_BINDINGS_CLK_ASM9260_H
+
+/* ahb gate */
+#define CLKID_AHB_ROM		0
+#define CLKID_AHB_RAM		1
+#define CLKID_AHB_GPIO		2
+#define CLKID_AHB_MAC		3
+#define CLKID_AHB_EMI		4
+#define CLKID_AHB_USB0		5
+#define CLKID_AHB_USB1		6
+#define CLKID_AHB_DMA0		7
+#define CLKID_AHB_DMA1		8
+#define CLKID_AHB_UART0		9
+#define CLKID_AHB_UART1		10
+#define CLKID_AHB_UART2		11
+#define CLKID_AHB_UART3		12
+#define CLKID_AHB_UART4		13
+#define CLKID_AHB_UART5		14
+#define CLKID_AHB_UART6		15
+#define CLKID_AHB_UART7		16
+#define CLKID_AHB_UART8		17
+#define CLKID_AHB_UART9		18
+#define CLKID_AHB_I2S0		19
+#define CLKID_AHB_I2C0		20
+#define CLKID_AHB_I2C1		21
+#define CLKID_AHB_SSP0		22
+#define CLKID_AHB_IOCONFIG	23
+#define CLKID_AHB_WDT		24
+#define CLKID_AHB_CAN0		25
+#define CLKID_AHB_CAN1		26
+#define CLKID_AHB_MPWM		27
+#define CLKID_AHB_SPI0		28
+#define CLKID_AHB_SPI1		29
+#define CLKID_AHB_QEI		30
+#define CLKID_AHB_QUADSPI0	31
+#define CLKID_AHB_CAMIF		32
+#define CLKID_AHB_LCDIF		33
+#define CLKID_AHB_TIMER0	34
+#define CLKID_AHB_TIMER1	35
+#define CLKID_AHB_TIMER2	36
+#define CLKID_AHB_TIMER3	37
+#define CLKID_AHB_IRQ		38
+#define CLKID_AHB_RTC		39
+#define CLKID_AHB_NAND		40
+#define CLKID_AHB_ADC0		41
+#define CLKID_AHB_LED		42
+#define CLKID_AHB_DAC0		43
+#define CLKID_AHB_LCD		44
+#define CLKID_AHB_I2S1		45
+#define CLKID_AHB_MAC1		46
+
+/* devider */
+#define CLKID_SYS_CPU		47
+#define CLKID_SYS_AHB		48
+#define CLKID_SYS_I2S0M		49
+#define CLKID_SYS_I2S0S		50
+#define CLKID_SYS_I2S1M		51
+#define CLKID_SYS_I2S1S		52
+#define CLKID_SYS_UART0		53
+#define CLKID_SYS_UART1		54
+#define CLKID_SYS_UART2		55
+#define CLKID_SYS_UART3		56
+#define CLKID_SYS_UART4		56
+#define CLKID_SYS_UART5		57
+#define CLKID_SYS_UART6		58
+#define CLKID_SYS_UART7		59
+#define CLKID_SYS_UART8		60
+#define CLKID_SYS_UART9		61
+#define CLKID_SYS_SPI0		62
+#define CLKID_SYS_SPI1		63
+#define CLKID_SYS_QUADSPI	64
+#define CLKID_SYS_SSP0		65
+#define CLKID_SYS_NAND		66
+#define CLKID_SYS_TRACE		67
+#define CLKID_SYS_CAMM		68
+#define CLKID_SYS_WDT		69
+#define CLKID_SYS_CLKOUT	70
+#define CLKID_SYS_MAC		71
+#define CLKID_SYS_LCD		72
+#define CLKID_SYS_ADCANA	73
+
+#define MAX_CLKS		74
+#endif
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/am3.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/am3.h
new file mode 100644
index 0000000000000000000000000000000000000000..b396f00e481db9d4858856c05cc9454677395f7e
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/am3.h
@@ -0,0 +1,108 @@
+/*
+ * Copyright 2017 Texas Instruments, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#ifndef __DT_BINDINGS_CLK_AM3_H
+#define __DT_BINDINGS_CLK_AM3_H
+
+#define AM3_CLKCTRL_OFFSET	0x0
+#define AM3_CLKCTRL_INDEX(offset)	((offset) - AM3_CLKCTRL_OFFSET)
+
+/* l4_per clocks */
+#define AM3_L4_PER_CLKCTRL_OFFSET	0x14
+#define AM3_L4_PER_CLKCTRL_INDEX(offset)	((offset) - AM3_L4_PER_CLKCTRL_OFFSET)
+#define AM3_CPGMAC0_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x14)
+#define AM3_LCDC_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x18)
+#define AM3_USB_OTG_HS_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x1c)
+#define AM3_TPTC0_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x24)
+#define AM3_EMIF_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x28)
+#define AM3_OCMCRAM_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x2c)
+#define AM3_GPMC_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x30)
+#define AM3_MCASP0_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x34)
+#define AM3_UART6_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x38)
+#define AM3_MMC1_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x3c)
+#define AM3_ELM_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x40)
+#define AM3_I2C3_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x44)
+#define AM3_I2C2_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x48)
+#define AM3_SPI0_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x4c)
+#define AM3_SPI1_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x50)
+#define AM3_L4_LS_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x60)
+#define AM3_MCASP1_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x68)
+#define AM3_UART2_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x6c)
+#define AM3_UART3_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x70)
+#define AM3_UART4_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x74)
+#define AM3_UART5_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x78)
+#define AM3_TIMER7_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x7c)
+#define AM3_TIMER2_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x80)
+#define AM3_TIMER3_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x84)
+#define AM3_TIMER4_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x88)
+#define AM3_RNG_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x90)
+#define AM3_AES_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x94)
+#define AM3_SHAM_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0xa0)
+#define AM3_GPIO2_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0xac)
+#define AM3_GPIO3_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0xb0)
+#define AM3_GPIO4_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0xb4)
+#define AM3_TPCC_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0xbc)
+#define AM3_D_CAN0_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0xc0)
+#define AM3_D_CAN1_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0xc4)
+#define AM3_EPWMSS1_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0xcc)
+#define AM3_EPWMSS0_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0xd4)
+#define AM3_EPWMSS2_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0xd8)
+#define AM3_L3_INSTR_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0xdc)
+#define AM3_L3_MAIN_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0xe0)
+#define AM3_PRUSS_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0xe8)
+#define AM3_TIMER5_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0xec)
+#define AM3_TIMER6_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0xf0)
+#define AM3_MMC2_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0xf4)
+#define AM3_MMC3_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0xf8)
+#define AM3_TPTC1_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0xfc)
+#define AM3_TPTC2_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x100)
+#define AM3_SPINLOCK_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x10c)
+#define AM3_MAILBOX_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x110)
+#define AM3_L4_HS_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x120)
+#define AM3_OCPWP_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x130)
+#define AM3_CLKDIV32K_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x14c)
+
+/* l4_wkup clocks */
+#define AM3_L4_WKUP_CLKCTRL_OFFSET	0x4
+#define AM3_L4_WKUP_CLKCTRL_INDEX(offset)	((offset) - AM3_L4_WKUP_CLKCTRL_OFFSET)
+#define AM3_CONTROL_CLKCTRL	AM3_L4_WKUP_CLKCTRL_INDEX(0x4)
+#define AM3_GPIO1_CLKCTRL	AM3_L4_WKUP_CLKCTRL_INDEX(0x8)
+#define AM3_L4_WKUP_CLKCTRL	AM3_L4_WKUP_CLKCTRL_INDEX(0xc)
+#define AM3_DEBUGSS_CLKCTRL	AM3_L4_WKUP_CLKCTRL_INDEX(0x14)
+#define AM3_WKUP_M3_CLKCTRL	AM3_L4_WKUP_CLKCTRL_INDEX(0xb0)
+#define AM3_UART1_CLKCTRL	AM3_L4_WKUP_CLKCTRL_INDEX(0xb4)
+#define AM3_I2C1_CLKCTRL	AM3_L4_WKUP_CLKCTRL_INDEX(0xb8)
+#define AM3_ADC_TSC_CLKCTRL	AM3_L4_WKUP_CLKCTRL_INDEX(0xbc)
+#define AM3_SMARTREFLEX0_CLKCTRL	AM3_L4_WKUP_CLKCTRL_INDEX(0xc0)
+#define AM3_TIMER1_CLKCTRL	AM3_L4_WKUP_CLKCTRL_INDEX(0xc4)
+#define AM3_SMARTREFLEX1_CLKCTRL	AM3_L4_WKUP_CLKCTRL_INDEX(0xc8)
+#define AM3_WD_TIMER2_CLKCTRL	AM3_L4_WKUP_CLKCTRL_INDEX(0xd4)
+
+/* mpu clocks */
+#define AM3_MPU_CLKCTRL_OFFSET	0x4
+#define AM3_MPU_CLKCTRL_INDEX(offset)	((offset) - AM3_MPU_CLKCTRL_OFFSET)
+#define AM3_MPU_CLKCTRL	AM3_MPU_CLKCTRL_INDEX(0x4)
+
+/* l4_rtc clocks */
+#define AM3_RTC_CLKCTRL	AM3_CLKCTRL_INDEX(0x0)
+
+/* gfx_l3 clocks */
+#define AM3_GFX_L3_CLKCTRL_OFFSET	0x4
+#define AM3_GFX_L3_CLKCTRL_INDEX(offset)	((offset) - AM3_GFX_L3_CLKCTRL_OFFSET)
+#define AM3_GFX_CLKCTRL	AM3_GFX_L3_CLKCTRL_INDEX(0x4)
+
+/* l4_cefuse clocks */
+#define AM3_L4_CEFUSE_CLKCTRL_OFFSET	0x20
+#define AM3_L4_CEFUSE_CLKCTRL_INDEX(offset)	((offset) - AM3_L4_CEFUSE_CLKCTRL_OFFSET)
+#define AM3_CEFUSE_CLKCTRL	AM3_L4_CEFUSE_CLKCTRL_INDEX(0x20)
+
+#endif
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/am4.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/am4.h
new file mode 100644
index 0000000000000000000000000000000000000000..d21df00b32701593a4624eb6b8869a398067a291
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/am4.h
@@ -0,0 +1,113 @@
+/*
+ * Copyright 2017 Texas Instruments, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#ifndef __DT_BINDINGS_CLK_AM4_H
+#define __DT_BINDINGS_CLK_AM4_H
+
+#define AM4_CLKCTRL_OFFSET	0x20
+#define AM4_CLKCTRL_INDEX(offset)	((offset) - AM4_CLKCTRL_OFFSET)
+
+/* l4_wkup clocks */
+#define AM4_ADC_TSC_CLKCTRL	AM4_CLKCTRL_INDEX(0x120)
+#define AM4_L4_WKUP_CLKCTRL	AM4_CLKCTRL_INDEX(0x220)
+#define AM4_WKUP_M3_CLKCTRL	AM4_CLKCTRL_INDEX(0x228)
+#define AM4_COUNTER_32K_CLKCTRL	AM4_CLKCTRL_INDEX(0x230)
+#define AM4_TIMER1_CLKCTRL	AM4_CLKCTRL_INDEX(0x328)
+#define AM4_WD_TIMER2_CLKCTRL	AM4_CLKCTRL_INDEX(0x338)
+#define AM4_I2C1_CLKCTRL	AM4_CLKCTRL_INDEX(0x340)
+#define AM4_UART1_CLKCTRL	AM4_CLKCTRL_INDEX(0x348)
+#define AM4_SMARTREFLEX0_CLKCTRL	AM4_CLKCTRL_INDEX(0x350)
+#define AM4_SMARTREFLEX1_CLKCTRL	AM4_CLKCTRL_INDEX(0x358)
+#define AM4_CONTROL_CLKCTRL	AM4_CLKCTRL_INDEX(0x360)
+#define AM4_GPIO1_CLKCTRL	AM4_CLKCTRL_INDEX(0x368)
+
+/* mpu clocks */
+#define AM4_MPU_CLKCTRL	AM4_CLKCTRL_INDEX(0x20)
+
+/* gfx_l3 clocks */
+#define AM4_GFX_CLKCTRL	AM4_CLKCTRL_INDEX(0x20)
+
+/* l4_rtc clocks */
+#define AM4_RTC_CLKCTRL	AM4_CLKCTRL_INDEX(0x20)
+
+/* l4_per clocks */
+#define AM4_L3_MAIN_CLKCTRL	AM4_CLKCTRL_INDEX(0x20)
+#define AM4_AES_CLKCTRL	AM4_CLKCTRL_INDEX(0x28)
+#define AM4_DES_CLKCTRL	AM4_CLKCTRL_INDEX(0x30)
+#define AM4_L3_INSTR_CLKCTRL	AM4_CLKCTRL_INDEX(0x40)
+#define AM4_OCMCRAM_CLKCTRL	AM4_CLKCTRL_INDEX(0x50)
+#define AM4_SHAM_CLKCTRL	AM4_CLKCTRL_INDEX(0x58)
+#define AM4_VPFE0_CLKCTRL	AM4_CLKCTRL_INDEX(0x68)
+#define AM4_VPFE1_CLKCTRL	AM4_CLKCTRL_INDEX(0x70)
+#define AM4_TPCC_CLKCTRL	AM4_CLKCTRL_INDEX(0x78)
+#define AM4_TPTC0_CLKCTRL	AM4_CLKCTRL_INDEX(0x80)
+#define AM4_TPTC1_CLKCTRL	AM4_CLKCTRL_INDEX(0x88)
+#define AM4_TPTC2_CLKCTRL	AM4_CLKCTRL_INDEX(0x90)
+#define AM4_L4_HS_CLKCTRL	AM4_CLKCTRL_INDEX(0xa0)
+#define AM4_GPMC_CLKCTRL	AM4_CLKCTRL_INDEX(0x220)
+#define AM4_MCASP0_CLKCTRL	AM4_CLKCTRL_INDEX(0x238)
+#define AM4_MCASP1_CLKCTRL	AM4_CLKCTRL_INDEX(0x240)
+#define AM4_MMC3_CLKCTRL	AM4_CLKCTRL_INDEX(0x248)
+#define AM4_QSPI_CLKCTRL	AM4_CLKCTRL_INDEX(0x258)
+#define AM4_USB_OTG_SS0_CLKCTRL	AM4_CLKCTRL_INDEX(0x260)
+#define AM4_USB_OTG_SS1_CLKCTRL	AM4_CLKCTRL_INDEX(0x268)
+#define AM4_PRUSS_CLKCTRL	AM4_CLKCTRL_INDEX(0x320)
+#define AM4_L4_LS_CLKCTRL	AM4_CLKCTRL_INDEX(0x420)
+#define AM4_D_CAN0_CLKCTRL	AM4_CLKCTRL_INDEX(0x428)
+#define AM4_D_CAN1_CLKCTRL	AM4_CLKCTRL_INDEX(0x430)
+#define AM4_EPWMSS0_CLKCTRL	AM4_CLKCTRL_INDEX(0x438)
+#define AM4_EPWMSS1_CLKCTRL	AM4_CLKCTRL_INDEX(0x440)
+#define AM4_EPWMSS2_CLKCTRL	AM4_CLKCTRL_INDEX(0x448)
+#define AM4_EPWMSS3_CLKCTRL	AM4_CLKCTRL_INDEX(0x450)
+#define AM4_EPWMSS4_CLKCTRL	AM4_CLKCTRL_INDEX(0x458)
+#define AM4_EPWMSS5_CLKCTRL	AM4_CLKCTRL_INDEX(0x460)
+#define AM4_ELM_CLKCTRL	AM4_CLKCTRL_INDEX(0x468)
+#define AM4_GPIO2_CLKCTRL	AM4_CLKCTRL_INDEX(0x478)
+#define AM4_GPIO3_CLKCTRL	AM4_CLKCTRL_INDEX(0x480)
+#define AM4_GPIO4_CLKCTRL	AM4_CLKCTRL_INDEX(0x488)
+#define AM4_GPIO5_CLKCTRL	AM4_CLKCTRL_INDEX(0x490)
+#define AM4_GPIO6_CLKCTRL	AM4_CLKCTRL_INDEX(0x498)
+#define AM4_HDQ1W_CLKCTRL	AM4_CLKCTRL_INDEX(0x4a0)
+#define AM4_I2C2_CLKCTRL	AM4_CLKCTRL_INDEX(0x4a8)
+#define AM4_I2C3_CLKCTRL	AM4_CLKCTRL_INDEX(0x4b0)
+#define AM4_MAILBOX_CLKCTRL	AM4_CLKCTRL_INDEX(0x4b8)
+#define AM4_MMC1_CLKCTRL	AM4_CLKCTRL_INDEX(0x4c0)
+#define AM4_MMC2_CLKCTRL	AM4_CLKCTRL_INDEX(0x4c8)
+#define AM4_RNG_CLKCTRL	AM4_CLKCTRL_INDEX(0x4e0)
+#define AM4_SPI0_CLKCTRL	AM4_CLKCTRL_INDEX(0x500)
+#define AM4_SPI1_CLKCTRL	AM4_CLKCTRL_INDEX(0x508)
+#define AM4_SPI2_CLKCTRL	AM4_CLKCTRL_INDEX(0x510)
+#define AM4_SPI3_CLKCTRL	AM4_CLKCTRL_INDEX(0x518)
+#define AM4_SPI4_CLKCTRL	AM4_CLKCTRL_INDEX(0x520)
+#define AM4_SPINLOCK_CLKCTRL	AM4_CLKCTRL_INDEX(0x528)
+#define AM4_TIMER2_CLKCTRL	AM4_CLKCTRL_INDEX(0x530)
+#define AM4_TIMER3_CLKCTRL	AM4_CLKCTRL_INDEX(0x538)
+#define AM4_TIMER4_CLKCTRL	AM4_CLKCTRL_INDEX(0x540)
+#define AM4_TIMER5_CLKCTRL	AM4_CLKCTRL_INDEX(0x548)
+#define AM4_TIMER6_CLKCTRL	AM4_CLKCTRL_INDEX(0x550)
+#define AM4_TIMER7_CLKCTRL	AM4_CLKCTRL_INDEX(0x558)
+#define AM4_TIMER8_CLKCTRL	AM4_CLKCTRL_INDEX(0x560)
+#define AM4_TIMER9_CLKCTRL	AM4_CLKCTRL_INDEX(0x568)
+#define AM4_TIMER10_CLKCTRL	AM4_CLKCTRL_INDEX(0x570)
+#define AM4_TIMER11_CLKCTRL	AM4_CLKCTRL_INDEX(0x578)
+#define AM4_UART2_CLKCTRL	AM4_CLKCTRL_INDEX(0x580)
+#define AM4_UART3_CLKCTRL	AM4_CLKCTRL_INDEX(0x588)
+#define AM4_UART4_CLKCTRL	AM4_CLKCTRL_INDEX(0x590)
+#define AM4_UART5_CLKCTRL	AM4_CLKCTRL_INDEX(0x598)
+#define AM4_UART6_CLKCTRL	AM4_CLKCTRL_INDEX(0x5a0)
+#define AM4_OCP2SCP0_CLKCTRL	AM4_CLKCTRL_INDEX(0x5b8)
+#define AM4_OCP2SCP1_CLKCTRL	AM4_CLKCTRL_INDEX(0x5c0)
+#define AM4_EMIF_CLKCTRL	AM4_CLKCTRL_INDEX(0x720)
+#define AM4_DSS_CORE_CLKCTRL	AM4_CLKCTRL_INDEX(0xa20)
+#define AM4_CPGMAC0_CLKCTRL	AM4_CLKCTRL_INDEX(0xb20)
+
+#endif
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/aspeed-clock.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/aspeed-clock.h
new file mode 100644
index 0000000000000000000000000000000000000000..f43738607d771d4f4996cf0f1523113db4ca1ed1
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/aspeed-clock.h
@@ -0,0 +1,54 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+
+#ifndef DT_BINDINGS_ASPEED_CLOCK_H
+#define DT_BINDINGS_ASPEED_CLOCK_H
+
+#define ASPEED_CLK_GATE_ECLK		0
+#define ASPEED_CLK_GATE_GCLK		1
+#define ASPEED_CLK_GATE_MCLK		2
+#define ASPEED_CLK_GATE_VCLK		3
+#define ASPEED_CLK_GATE_BCLK		4
+#define ASPEED_CLK_GATE_DCLK		5
+#define ASPEED_CLK_GATE_REFCLK		6
+#define ASPEED_CLK_GATE_USBPORT2CLK	7
+#define ASPEED_CLK_GATE_LCLK		8
+#define ASPEED_CLK_GATE_USBUHCICLK	9
+#define ASPEED_CLK_GATE_D1CLK		10
+#define ASPEED_CLK_GATE_YCLK		11
+#define ASPEED_CLK_GATE_USBPORT1CLK	12
+#define ASPEED_CLK_GATE_UART1CLK	13
+#define ASPEED_CLK_GATE_UART2CLK	14
+#define ASPEED_CLK_GATE_UART5CLK	15
+#define ASPEED_CLK_GATE_ESPICLK		16
+#define ASPEED_CLK_GATE_MAC1CLK		17
+#define ASPEED_CLK_GATE_MAC2CLK		18
+#define ASPEED_CLK_GATE_RSACLK		19
+#define ASPEED_CLK_GATE_UART3CLK	20
+#define ASPEED_CLK_GATE_UART4CLK	21
+#define ASPEED_CLK_GATE_SDCLK		22
+#define ASPEED_CLK_GATE_LHCCLK		23
+#define ASPEED_CLK_HPLL			24
+#define ASPEED_CLK_AHB			25
+#define ASPEED_CLK_APB			26
+#define ASPEED_CLK_UART			27
+#define ASPEED_CLK_SDIO			28
+#define ASPEED_CLK_ECLK			29
+#define ASPEED_CLK_ECLK_MUX		30
+#define ASPEED_CLK_LHCLK		31
+#define ASPEED_CLK_MAC			32
+#define ASPEED_CLK_BCLK			33
+#define ASPEED_CLK_MPLL			34
+#define ASPEED_CLK_24M			35
+
+#define ASPEED_RESET_XDMA		0
+#define ASPEED_RESET_MCTP		1
+#define ASPEED_RESET_ADC		2
+#define ASPEED_RESET_JTAG_MASTER	3
+#define ASPEED_RESET_MIC		4
+#define ASPEED_RESET_PWM		5
+#define ASPEED_RESET_PECI		6
+#define ASPEED_RESET_I2C		7
+#define ASPEED_RESET_AHB		8
+#define ASPEED_RESET_CRT1		9
+
+#endif
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/at91.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/at91.h
new file mode 100644
index 0000000000000000000000000000000000000000..ab3ee241d10c50577694ab5eeacabf8c8cabcb39
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/at91.h
@@ -0,0 +1,23 @@
+/*
+ * This header provides constants for AT91 pmc status.
+ *
+ * The constants defined in this header are being used in dts.
+ *
+ * Licensed under GPLv2 or later.
+ */
+
+#ifndef _DT_BINDINGS_CLK_AT91_H
+#define _DT_BINDINGS_CLK_AT91_H
+
+#define AT91_PMC_MOSCS		0		/* MOSCS Flag */
+#define AT91_PMC_LOCKA		1		/* PLLA Lock */
+#define AT91_PMC_LOCKB		2		/* PLLB Lock */
+#define AT91_PMC_MCKRDY		3		/* Master Clock */
+#define AT91_PMC_LOCKU		6		/* UPLL Lock */
+#define AT91_PMC_PCKRDY(id)	(8 + (id))	/* Programmable Clock */
+#define AT91_PMC_MOSCSELS	16		/* Main Oscillator Selection */
+#define AT91_PMC_MOSCRCS	17		/* Main On-Chip RC */
+#define AT91_PMC_CFDEV		18		/* Clock Failure Detector Event */
+#define AT91_PMC_GCKRDY		24		/* Generated Clocks */
+
+#endif
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/ath79-clk.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/ath79-clk.h
new file mode 100644
index 0000000000000000000000000000000000000000..27359ad8390431a6ed01b073ef09a4ac6d4cc8ca
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/ath79-clk.h
@@ -0,0 +1,19 @@
+/*
+ * Copyright (C) 2014, 2016 Antony Pavlov <antonynpavlov@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __DT_BINDINGS_ATH79_CLK_H
+#define __DT_BINDINGS_ATH79_CLK_H
+
+#define ATH79_CLK_CPU		0
+#define ATH79_CLK_DDR		1
+#define ATH79_CLK_AHB		2
+
+#define ATH79_CLK_END		3
+
+#endif /* __DT_BINDINGS_ATH79_CLK_H */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/axg-aoclkc.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/axg-aoclkc.h
new file mode 100644
index 0000000000000000000000000000000000000000..61955016a55b3fe9f76a1b8ffeda97cf054a6a33
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/axg-aoclkc.h
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
+/*
+ * Copyright (c) 2016 BayLibre, SAS
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ *
+ * Copyright (c) 2018 Amlogic, inc.
+ * Author: Qiufang Dai <qiufang.dai@amlogic.com>
+ */
+
+#ifndef DT_BINDINGS_CLOCK_AMLOGIC_MESON_AXG_AOCLK
+#define DT_BINDINGS_CLOCK_AMLOGIC_MESON_AXG_AOCLK
+
+#define CLKID_AO_REMOTE		0
+#define CLKID_AO_I2C_MASTER	1
+#define CLKID_AO_I2C_SLAVE	2
+#define CLKID_AO_UART1		3
+#define CLKID_AO_UART2		4
+#define CLKID_AO_IR_BLASTER	5
+#define CLKID_AO_SAR_ADC	6
+#define CLKID_AO_CLK81		7
+#define CLKID_AO_SAR_ADC_SEL	8
+#define CLKID_AO_SAR_ADC_DIV	9
+#define CLKID_AO_SAR_ADC_CLK	10
+#define CLKID_AO_ALT_XTAL	11
+
+#endif
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/axg-audio-clkc.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/axg-audio-clkc.h
new file mode 100644
index 0000000000000000000000000000000000000000..fd9c362099d9bea3d3132ad203aa785f7a4314de
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/axg-audio-clkc.h
@@ -0,0 +1,94 @@
+/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
+/*
+ * Copyright (c) 2018 Baylibre SAS.
+ * Author: Jerome Brunet <jbrunet@baylibre.com>
+ */
+
+#ifndef __AXG_AUDIO_CLKC_BINDINGS_H
+#define __AXG_AUDIO_CLKC_BINDINGS_H
+
+#define AUD_CLKID_SLV_SCLK0		9
+#define AUD_CLKID_SLV_SCLK1		10
+#define AUD_CLKID_SLV_SCLK2		11
+#define AUD_CLKID_SLV_SCLK3		12
+#define AUD_CLKID_SLV_SCLK4		13
+#define AUD_CLKID_SLV_SCLK5		14
+#define AUD_CLKID_SLV_SCLK6		15
+#define AUD_CLKID_SLV_SCLK7		16
+#define AUD_CLKID_SLV_SCLK8		17
+#define AUD_CLKID_SLV_SCLK9		18
+#define AUD_CLKID_SLV_LRCLK0		19
+#define AUD_CLKID_SLV_LRCLK1		20
+#define AUD_CLKID_SLV_LRCLK2		21
+#define AUD_CLKID_SLV_LRCLK3		22
+#define AUD_CLKID_SLV_LRCLK4		23
+#define AUD_CLKID_SLV_LRCLK5		24
+#define AUD_CLKID_SLV_LRCLK6		25
+#define AUD_CLKID_SLV_LRCLK7		26
+#define AUD_CLKID_SLV_LRCLK8		27
+#define AUD_CLKID_SLV_LRCLK9		28
+#define AUD_CLKID_DDR_ARB		29
+#define AUD_CLKID_PDM			30
+#define AUD_CLKID_TDMIN_A		31
+#define AUD_CLKID_TDMIN_B		32
+#define AUD_CLKID_TDMIN_C		33
+#define AUD_CLKID_TDMIN_LB		34
+#define AUD_CLKID_TDMOUT_A		35
+#define AUD_CLKID_TDMOUT_B		36
+#define AUD_CLKID_TDMOUT_C		37
+#define AUD_CLKID_FRDDR_A		38
+#define AUD_CLKID_FRDDR_B		39
+#define AUD_CLKID_FRDDR_C		40
+#define AUD_CLKID_TODDR_A		41
+#define AUD_CLKID_TODDR_B		42
+#define AUD_CLKID_TODDR_C		43
+#define AUD_CLKID_LOOPBACK		44
+#define AUD_CLKID_SPDIFIN		45
+#define AUD_CLKID_SPDIFOUT		46
+#define AUD_CLKID_RESAMPLE		47
+#define AUD_CLKID_POWER_DETECT		48
+#define AUD_CLKID_MST_A_MCLK		49
+#define AUD_CLKID_MST_B_MCLK		50
+#define AUD_CLKID_MST_C_MCLK		51
+#define AUD_CLKID_MST_D_MCLK		52
+#define AUD_CLKID_MST_E_MCLK		53
+#define AUD_CLKID_MST_F_MCLK		54
+#define AUD_CLKID_SPDIFOUT_CLK		55
+#define AUD_CLKID_SPDIFIN_CLK		56
+#define AUD_CLKID_PDM_DCLK		57
+#define AUD_CLKID_PDM_SYSCLK		58
+#define AUD_CLKID_MST_A_SCLK		79
+#define AUD_CLKID_MST_B_SCLK		80
+#define AUD_CLKID_MST_C_SCLK		81
+#define AUD_CLKID_MST_D_SCLK		82
+#define AUD_CLKID_MST_E_SCLK		83
+#define AUD_CLKID_MST_F_SCLK		84
+#define AUD_CLKID_MST_A_LRCLK		86
+#define AUD_CLKID_MST_B_LRCLK		87
+#define AUD_CLKID_MST_C_LRCLK		88
+#define AUD_CLKID_MST_D_LRCLK		89
+#define AUD_CLKID_MST_E_LRCLK		90
+#define AUD_CLKID_MST_F_LRCLK		91
+#define AUD_CLKID_TDMIN_A_SCLK_SEL	116
+#define AUD_CLKID_TDMIN_B_SCLK_SEL	117
+#define AUD_CLKID_TDMIN_C_SCLK_SEL	118
+#define AUD_CLKID_TDMIN_LB_SCLK_SEL	119
+#define AUD_CLKID_TDMOUT_A_SCLK_SEL	120
+#define AUD_CLKID_TDMOUT_B_SCLK_SEL	121
+#define AUD_CLKID_TDMOUT_C_SCLK_SEL	122
+#define AUD_CLKID_TDMIN_A_SCLK		123
+#define AUD_CLKID_TDMIN_B_SCLK		124
+#define AUD_CLKID_TDMIN_C_SCLK		125
+#define AUD_CLKID_TDMIN_LB_SCLK		126
+#define AUD_CLKID_TDMOUT_A_SCLK		127
+#define AUD_CLKID_TDMOUT_B_SCLK		128
+#define AUD_CLKID_TDMOUT_C_SCLK		129
+#define AUD_CLKID_TDMIN_A_LRCLK		130
+#define AUD_CLKID_TDMIN_B_LRCLK		131
+#define AUD_CLKID_TDMIN_C_LRCLK		132
+#define AUD_CLKID_TDMIN_LB_LRCLK	133
+#define AUD_CLKID_TDMOUT_A_LRCLK	134
+#define AUD_CLKID_TDMOUT_B_LRCLK	135
+#define AUD_CLKID_TDMOUT_C_LRCLK	136
+
+#endif /* __AXG_AUDIO_CLKC_BINDINGS_H */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/axg-clkc.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/axg-clkc.h
new file mode 100644
index 0000000000000000000000000000000000000000..fd1f938c38d191b9c56fcc9004a981936a69c476
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/axg-clkc.h
@@ -0,0 +1,76 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Meson-AXG clock tree IDs
+ *
+ * Copyright (c) 2017 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __AXG_CLKC_H
+#define __AXG_CLKC_H
+
+#define CLKID_SYS_PLL				0
+#define CLKID_FIXED_PLL				1
+#define CLKID_FCLK_DIV2				2
+#define CLKID_FCLK_DIV3				3
+#define CLKID_FCLK_DIV4				4
+#define CLKID_FCLK_DIV5				5
+#define CLKID_FCLK_DIV7				6
+#define CLKID_GP0_PLL				7
+#define CLKID_CLK81				10
+#define CLKID_MPLL0				11
+#define CLKID_MPLL1				12
+#define CLKID_MPLL2				13
+#define CLKID_MPLL3				14
+#define CLKID_DDR				15
+#define CLKID_AUDIO_LOCKER			16
+#define CLKID_MIPI_DSI_HOST			17
+#define CLKID_ISA				18
+#define CLKID_PL301				19
+#define CLKID_PERIPHS				20
+#define CLKID_SPICC0				21
+#define CLKID_I2C				22
+#define CLKID_RNG0				23
+#define CLKID_UART0				24
+#define CLKID_MIPI_DSI_PHY			25
+#define CLKID_SPICC1				26
+#define CLKID_PCIE_A				27
+#define CLKID_PCIE_B				28
+#define CLKID_HIU_IFACE				29
+#define CLKID_ASSIST_MISC			30
+#define CLKID_SD_EMMC_B				31
+#define CLKID_SD_EMMC_C				32
+#define CLKID_DMA				33
+#define CLKID_SPI				34
+#define CLKID_AUDIO				35
+#define CLKID_ETH				36
+#define CLKID_UART1				37
+#define CLKID_G2D				38
+#define CLKID_USB0				39
+#define CLKID_USB1				40
+#define CLKID_RESET				41
+#define CLKID_USB				42
+#define CLKID_AHB_ARB0				43
+#define CLKID_EFUSE				44
+#define CLKID_BOOT_ROM				45
+#define CLKID_AHB_DATA_BUS			46
+#define CLKID_AHB_CTRL_BUS			47
+#define CLKID_USB1_DDR_BRIDGE			48
+#define CLKID_USB0_DDR_BRIDGE			49
+#define CLKID_MMC_PCLK				50
+#define CLKID_VPU_INTR				51
+#define CLKID_SEC_AHB_AHB3_BRIDGE		52
+#define CLKID_GIC				53
+#define CLKID_AO_MEDIA_CPU			54
+#define CLKID_AO_AHB_SRAM			55
+#define CLKID_AO_AHB_BUS			56
+#define CLKID_AO_IFACE				57
+#define CLKID_AO_I2C				58
+#define CLKID_SD_EMMC_B_CLK0			59
+#define CLKID_SD_EMMC_C_CLK0			60
+#define CLKID_HIFI_PLL				69
+#define CLKID_PCIE_CML_EN0			79
+#define CLKID_PCIE_CML_EN1			80
+#define CLKID_MIPI_ENABLE			81
+#define CLKID_GEN_CLK				84
+
+#endif /* __AXG_CLKC_H */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/axis,artpec6-clkctrl.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/axis,artpec6-clkctrl.h
new file mode 100644
index 0000000000000000000000000000000000000000..f9f04dccc99660d1a0d1a82d5cd540155ad8b8f1
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/axis,artpec6-clkctrl.h
@@ -0,0 +1,38 @@
+/*
+ * ARTPEC-6 clock controller indexes
+ *
+ * Copyright 2016 Axis Comunications AB.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef DT_BINDINGS_CLK_ARTPEC6_CLKCTRL_H
+#define DT_BINDINGS_CLK_ARTPEC6_CLKCTRL_H
+
+#define ARTPEC6_CLK_CPU			0
+#define ARTPEC6_CLK_CPU_PERIPH		1
+#define ARTPEC6_CLK_NAND_CLKA		2
+#define ARTPEC6_CLK_NAND_CLKB		3
+#define ARTPEC6_CLK_ETH_ACLK		4
+#define ARTPEC6_CLK_DMA_ACLK		5
+#define ARTPEC6_CLK_PTP_REF		6
+#define ARTPEC6_CLK_SD_PCLK		7
+#define ARTPEC6_CLK_SD_IMCLK		8
+#define ARTPEC6_CLK_I2S_HST		9
+#define ARTPEC6_CLK_I2S0_CLK		10
+#define ARTPEC6_CLK_I2S1_CLK		11
+#define ARTPEC6_CLK_UART_PCLK		12
+#define ARTPEC6_CLK_UART_REFCLK		13
+#define ARTPEC6_CLK_I2C			14
+#define ARTPEC6_CLK_SPI_PCLK		15
+#define ARTPEC6_CLK_SPI_SSPCLK		16
+#define ARTPEC6_CLK_SYS_TIMER		17
+#define ARTPEC6_CLK_FRACDIV_IN		18
+#define ARTPEC6_CLK_DBG_PCLK		19
+
+/* This must be the highest clock index plus one. */
+#define ARTPEC6_CLK_NUMCLOCKS		20
+
+#endif
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/bcm-cygnus.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/bcm-cygnus.h
new file mode 100644
index 0000000000000000000000000000000000000000..62ac5d782a000305aa23bc24cc3560771793fae9
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/bcm-cygnus.h
@@ -0,0 +1,74 @@
+/*
+ *  BSD LICENSE
+ *
+ *  Copyright(c) 2014 Broadcom Corporation.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    * Redistributions of source code must retain the above copyright
+ *      notice, this list of conditions and the following disclaimer.
+ *    * Redistributions in binary form must reproduce the above copyright
+ *      notice, this list of conditions and the following disclaimer in
+ *      the documentation and/or other materials provided with the
+ *      distribution.
+ *    * Neither the name of Broadcom Corporation nor the names of its
+ *      contributors may be used to endorse or promote products derived
+ *      from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _CLOCK_BCM_CYGNUS_H
+#define _CLOCK_BCM_CYGNUS_H
+
+/* GENPLL clock ID */
+#define BCM_CYGNUS_GENPLL                     0
+#define BCM_CYGNUS_GENPLL_AXI21_CLK           1
+#define BCM_CYGNUS_GENPLL_250MHZ_CLK          2
+#define BCM_CYGNUS_GENPLL_IHOST_SYS_CLK       3
+#define BCM_CYGNUS_GENPLL_ENET_SW_CLK         4
+#define BCM_CYGNUS_GENPLL_AUDIO_125_CLK       5
+#define BCM_CYGNUS_GENPLL_CAN_CLK             6
+
+/* LCPLL0 clock ID */
+#define BCM_CYGNUS_LCPLL0                     0
+#define BCM_CYGNUS_LCPLL0_PCIE_PHY_REF_CLK    1
+#define BCM_CYGNUS_LCPLL0_DDR_PHY_CLK         2
+#define BCM_CYGNUS_LCPLL0_SDIO_CLK            3
+#define BCM_CYGNUS_LCPLL0_USB_PHY_REF_CLK     4
+#define BCM_CYGNUS_LCPLL0_SMART_CARD_CLK      5
+#define BCM_CYGNUS_LCPLL0_CH5_UNUSED          6
+
+/* MIPI PLL clock ID */
+#define BCM_CYGNUS_MIPIPLL                    0
+#define BCM_CYGNUS_MIPIPLL_CH0_UNUSED         1
+#define BCM_CYGNUS_MIPIPLL_CH1_LCD            2
+#define BCM_CYGNUS_MIPIPLL_CH2_V3D            3
+#define BCM_CYGNUS_MIPIPLL_CH3_UNUSED         4
+#define BCM_CYGNUS_MIPIPLL_CH4_UNUSED         5
+#define BCM_CYGNUS_MIPIPLL_CH5_UNUSED         6
+
+/* ASIU clock ID */
+#define BCM_CYGNUS_ASIU_KEYPAD_CLK    0
+#define BCM_CYGNUS_ASIU_ADC_CLK       1
+#define BCM_CYGNUS_ASIU_PWM_CLK       2
+
+/* AUDIO clock ID */
+#define BCM_CYGNUS_AUDIOPLL           0
+#define BCM_CYGNUS_AUDIOPLL_CH0       1
+#define BCM_CYGNUS_AUDIOPLL_CH1       2
+#define BCM_CYGNUS_AUDIOPLL_CH2       3
+
+#endif /* _CLOCK_BCM_CYGNUS_H */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/bcm-ns2.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/bcm-ns2.h
new file mode 100644
index 0000000000000000000000000000000000000000..d99c7a2e70cbe492098a5d1410e433a7dde24aa9
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/bcm-ns2.h
@@ -0,0 +1,72 @@
+/*
+ *  BSD LICENSE
+ *
+ *  Copyright(c) 2015 Broadcom Corporation.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    * Redistributions of source code must retain the above copyright
+ *      notice, this list of conditions and the following disclaimer.
+ *    * Redistributions in binary form must reproduce the above copyright
+ *      notice, this list of conditions and the following disclaimer in
+ *      the documentation and/or other materials provided with the
+ *      distribution.
+ *    * Neither the name of Broadcom Corporation nor the names of its
+ *      contributors may be used to endorse or promote products derived
+ *      from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _CLOCK_BCM_NS2_H
+#define _CLOCK_BCM_NS2_H
+
+/* GENPLL SCR clock channel ID */
+#define BCM_NS2_GENPLL_SCR		0
+#define BCM_NS2_GENPLL_SCR_SCR_CLK	1
+#define BCM_NS2_GENPLL_SCR_FS_CLK	2
+#define BCM_NS2_GENPLL_SCR_AUDIO_CLK	3
+#define BCM_NS2_GENPLL_SCR_CH3_UNUSED	4
+#define BCM_NS2_GENPLL_SCR_CH4_UNUSED	5
+#define BCM_NS2_GENPLL_SCR_CH5_UNUSED	6
+
+/* GENPLL SW clock channel ID */
+#define BCM_NS2_GENPLL_SW		0
+#define BCM_NS2_GENPLL_SW_RPE_CLK	1
+#define BCM_NS2_GENPLL_SW_250_CLK	2
+#define BCM_NS2_GENPLL_SW_NIC_CLK	3
+#define BCM_NS2_GENPLL_SW_CHIMP_CLK	4
+#define BCM_NS2_GENPLL_SW_PORT_CLK	5
+#define BCM_NS2_GENPLL_SW_SDIO_CLK	6
+
+/* LCPLL DDR clock channel ID */
+#define BCM_NS2_LCPLL_DDR		0
+#define BCM_NS2_LCPLL_DDR_PCIE_SATA_USB_CLK	1
+#define BCM_NS2_LCPLL_DDR_DDR_CLK	2
+#define BCM_NS2_LCPLL_DDR_CH2_UNUSED	3
+#define BCM_NS2_LCPLL_DDR_CH3_UNUSED	4
+#define BCM_NS2_LCPLL_DDR_CH4_UNUSED	5
+#define BCM_NS2_LCPLL_DDR_CH5_UNUSED	6
+
+/* LCPLL PORTS clock channel ID */
+#define BCM_NS2_LCPLL_PORTS		0
+#define BCM_NS2_LCPLL_PORTS_WAN_CLK	1
+#define BCM_NS2_LCPLL_PORTS_RGMII_CLK	2
+#define BCM_NS2_LCPLL_PORTS_CH2_UNUSED	3
+#define BCM_NS2_LCPLL_PORTS_CH3_UNUSED	4
+#define BCM_NS2_LCPLL_PORTS_CH4_UNUSED	5
+#define BCM_NS2_LCPLL_PORTS_CH5_UNUSED	6
+
+#endif /* _CLOCK_BCM_NS2_H */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/bcm-nsp.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/bcm-nsp.h
new file mode 100644
index 0000000000000000000000000000000000000000..ad5827cde7828c5639ae1402370607040bdc1183
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/bcm-nsp.h
@@ -0,0 +1,51 @@
+/*
+ *  BSD LICENSE
+ *
+ *  Copyright(c) 2015 Broadcom Corporation.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *	* Redistributions of source code must retain the above copyright
+ *	  notice, this list of conditions and the following disclaimer.
+ *	* Redistributions in binary form must reproduce the above copyright
+ *	  notice, this list of conditions and the following disclaimer in
+ *	  the documentation and/or other materials provided with the
+ *	  distribution.
+ *	* Neither the name of Broadcom Corporation nor the names of its
+ *	  contributors may be used to endorse or promote products derived
+ *	  from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _CLOCK_BCM_NSP_H
+#define _CLOCK_BCM_NSP_H
+
+/* GENPLL clock channel ID */
+#define BCM_NSP_GENPLL			0
+#define BCM_NSP_GENPLL_PHY_CLK		1
+#define BCM_NSP_GENPLL_ENET_SW_CLK	2
+#define BCM_NSP_GENPLL_USB_PHY_REF_CLK	3
+#define BCM_NSP_GENPLL_IPROCFAST_CLK	4
+#define BCM_NSP_GENPLL_SATA1_CLK	5
+#define BCM_NSP_GENPLL_SATA2_CLK	6
+
+/* LCPLL0 clock channel ID */
+#define BCM_NSP_LCPLL0			0
+#define BCM_NSP_LCPLL0_PCIE_PHY_REF_CLK	1
+#define BCM_NSP_LCPLL0_SDIO_CLK		2
+#define BCM_NSP_LCPLL0_DDR_PHY_CLK	3
+
+#endif /* _CLOCK_BCM_NSP_H */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/bcm-sr.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/bcm-sr.h
new file mode 100644
index 0000000000000000000000000000000000000000..419011ba1a9480d1e61f81c69f6feb9439feebee
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/bcm-sr.h
@@ -0,0 +1,111 @@
+/*
+ *  BSD LICENSE
+ *
+ *  Copyright(c) 2017 Broadcom. All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    * Redistributions of source code must retain the above copyright
+ *      notice, this list of conditions and the following disclaimer.
+ *    * Redistributions in binary form must reproduce the above copyright
+ *      notice, this list of conditions and the following disclaimer in
+ *      the documentation and/or other materials provided with the
+ *      distribution.
+ *    * Neither the name of Broadcom Corporation nor the names of its
+ *      contributors may be used to endorse or promote products derived
+ *      from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _CLOCK_BCM_SR_H
+#define _CLOCK_BCM_SR_H
+
+/* GENPLL 0 clock channel ID SCR HSLS FS PCIE */
+#define BCM_SR_GENPLL0			0
+#define BCM_SR_GENPLL0_125M_CLK		1
+#define BCM_SR_GENPLL0_SCR_CLK		2
+#define BCM_SR_GENPLL0_250M_CLK		3
+#define BCM_SR_GENPLL0_PCIE_AXI_CLK	4
+#define BCM_SR_GENPLL0_PAXC_AXI_X2_CLK	5
+#define BCM_SR_GENPLL0_PAXC_AXI_CLK	6
+
+/* GENPLL 1 clock channel ID MHB PCIE NITRO */
+#define BCM_SR_GENPLL1			0
+#define BCM_SR_GENPLL1_PCIE_TL_CLK	1
+#define BCM_SR_GENPLL1_MHB_APB_CLK	2
+
+/* GENPLL 2 clock channel ID NITRO MHB*/
+#define BCM_SR_GENPLL2			0
+#define BCM_SR_GENPLL2_NIC_CLK		1
+#define BCM_SR_GENPLL2_TS_500_CLK	2
+#define BCM_SR_GENPLL2_125_NITRO_CLK	3
+#define BCM_SR_GENPLL2_CHIMP_CLK	4
+#define BCM_SR_GENPLL2_NIC_FLASH_CLK	5
+#define BCM_SR_GENPLL2_FS4_CLK		6
+
+/* GENPLL 3 HSLS clock channel ID */
+#define BCM_SR_GENPLL3			0
+#define BCM_SR_GENPLL3_HSLS_CLK		1
+#define BCM_SR_GENPLL3_SDIO_CLK		2
+
+/* GENPLL 4 SCR clock channel ID */
+#define BCM_SR_GENPLL4			0
+#define BCM_SR_GENPLL4_CCN_CLK		1
+#define BCM_SR_GENPLL4_TPIU_PLL_CLK	2
+#define BCM_SR_GENPLL4_NOC_CLK		3
+#define BCM_SR_GENPLL4_CHCLK_FS4_CLK	4
+#define BCM_SR_GENPLL4_BRIDGE_FSCPU_CLK	5
+
+/* GENPLL 5 FS4 clock channel ID */
+#define BCM_SR_GENPLL5			0
+#define BCM_SR_GENPLL5_FS4_HF_CLK	1
+#define BCM_SR_GENPLL5_CRYPTO_AE_CLK	2
+#define BCM_SR_GENPLL5_RAID_AE_CLK	3
+
+/* GENPLL 6 NITRO clock channel ID */
+#define BCM_SR_GENPLL6			0
+#define BCM_SR_GENPLL6_48_USB_CLK	1
+
+/* LCPLL0  clock channel ID */
+#define BCM_SR_LCPLL0			0
+#define BCM_SR_LCPLL0_SATA_REFP_CLK	1
+#define BCM_SR_LCPLL0_SATA_REFN_CLK	2
+#define BCM_SR_LCPLL0_SATA_350_CLK	3
+#define BCM_SR_LCPLL0_SATA_500_CLK	4
+
+/* LCPLL1  clock channel ID */
+#define BCM_SR_LCPLL1			0
+#define BCM_SR_LCPLL1_WAN_CLK		1
+#define BCM_SR_LCPLL1_USB_REF_CLK	2
+#define BCM_SR_LCPLL1_CRMU_TS_CLK	3
+
+/* LCPLL PCIE  clock channel ID */
+#define BCM_SR_LCPLL_PCIE		0
+#define BCM_SR_LCPLL_PCIE_PHY_REF_CLK	1
+
+/* GENPLL EMEM0 clock channel ID */
+#define BCM_SR_EMEMPLL0			0
+#define BCM_SR_EMEMPLL0_EMEM_CLK	1
+
+/* GENPLL EMEM0 clock channel ID */
+#define BCM_SR_EMEMPLL1			0
+#define BCM_SR_EMEMPLL1_EMEM_CLK	1
+
+/* GENPLL EMEM0 clock channel ID */
+#define BCM_SR_EMEMPLL2			0
+#define BCM_SR_EMEMPLL2_EMEM_CLK	1
+
+#endif /* _CLOCK_BCM_SR_H */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/bcm21664.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/bcm21664.h
new file mode 100644
index 0000000000000000000000000000000000000000..5a7f0e4750a844a5297361a001a8017f3a699db5
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/bcm21664.h
@@ -0,0 +1,62 @@
+/*
+ * Copyright (C) 2013 Broadcom Corporation
+ * Copyright 2013 Linaro Limited
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _CLOCK_BCM21664_H
+#define _CLOCK_BCM21664_H
+
+/*
+ * This file defines the values used to specify clocks provided by
+ * the clock control units (CCUs) on Broadcom BCM21664 family SoCs.
+ */
+
+/* bcm21664 CCU device tree "compatible" strings */
+#define BCM21664_DT_ROOT_CCU_COMPAT	"brcm,bcm21664-root-ccu"
+#define BCM21664_DT_AON_CCU_COMPAT	"brcm,bcm21664-aon-ccu"
+#define BCM21664_DT_MASTER_CCU_COMPAT	"brcm,bcm21664-master-ccu"
+#define BCM21664_DT_SLAVE_CCU_COMPAT	"brcm,bcm21664-slave-ccu"
+
+/* root CCU clock ids */
+
+#define BCM21664_ROOT_CCU_FRAC_1M		0
+#define BCM21664_ROOT_CCU_CLOCK_COUNT		1
+
+/* aon CCU clock ids */
+
+#define BCM21664_AON_CCU_HUB_TIMER		0
+#define BCM21664_AON_CCU_CLOCK_COUNT		1
+
+/* master CCU clock ids */
+
+#define BCM21664_MASTER_CCU_SDIO1		0
+#define BCM21664_MASTER_CCU_SDIO2		1
+#define BCM21664_MASTER_CCU_SDIO3		2
+#define BCM21664_MASTER_CCU_SDIO4		3
+#define BCM21664_MASTER_CCU_SDIO1_SLEEP		4
+#define BCM21664_MASTER_CCU_SDIO2_SLEEP		5
+#define BCM21664_MASTER_CCU_SDIO3_SLEEP		6
+#define BCM21664_MASTER_CCU_SDIO4_SLEEP		7
+#define BCM21664_MASTER_CCU_CLOCK_COUNT		8
+
+/* slave CCU clock ids */
+
+#define BCM21664_SLAVE_CCU_UARTB		0
+#define BCM21664_SLAVE_CCU_UARTB2		1
+#define BCM21664_SLAVE_CCU_UARTB3		2
+#define BCM21664_SLAVE_CCU_BSC1			3
+#define BCM21664_SLAVE_CCU_BSC2			4
+#define BCM21664_SLAVE_CCU_BSC3			5
+#define BCM21664_SLAVE_CCU_BSC4			6
+#define BCM21664_SLAVE_CCU_CLOCK_COUNT		7
+
+#endif /* _CLOCK_BCM21664_H */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/bcm281xx.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/bcm281xx.h
new file mode 100644
index 0000000000000000000000000000000000000000..a763460cf1afcc9d9f8b98a9508f3d851b319805
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/bcm281xx.h
@@ -0,0 +1,77 @@
+/*
+ * Copyright (C) 2013 Broadcom Corporation
+ * Copyright 2013 Linaro Limited
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _CLOCK_BCM281XX_H
+#define _CLOCK_BCM281XX_H
+
+/*
+ * This file defines the values used to specify clocks provided by
+ * the clock control units (CCUs) on Broadcom BCM281XX family SoCs.
+ */
+
+/*
+ * These are the bcm281xx CCU device tree "compatible" strings.
+ * We're stuck with using "bcm11351" in the string because wild
+ * cards aren't allowed, and that name was the first one defined
+ * in this family of devices.
+ */
+#define BCM281XX_DT_ROOT_CCU_COMPAT	"brcm,bcm11351-root-ccu"
+#define BCM281XX_DT_AON_CCU_COMPAT	"brcm,bcm11351-aon-ccu"
+#define BCM281XX_DT_HUB_CCU_COMPAT	"brcm,bcm11351-hub-ccu"
+#define BCM281XX_DT_MASTER_CCU_COMPAT	"brcm,bcm11351-master-ccu"
+#define BCM281XX_DT_SLAVE_CCU_COMPAT	"brcm,bcm11351-slave-ccu"
+
+/* root CCU clock ids */
+
+#define BCM281XX_ROOT_CCU_FRAC_1M		0
+#define BCM281XX_ROOT_CCU_CLOCK_COUNT		1
+
+/* aon CCU clock ids */
+
+#define BCM281XX_AON_CCU_HUB_TIMER		0
+#define BCM281XX_AON_CCU_PMU_BSC		1
+#define BCM281XX_AON_CCU_PMU_BSC_VAR		2
+#define BCM281XX_AON_CCU_CLOCK_COUNT		3
+
+/* hub CCU clock ids */
+
+#define BCM281XX_HUB_CCU_TMON_1M		0
+#define BCM281XX_HUB_CCU_CLOCK_COUNT		1
+
+/* master CCU clock ids */
+
+#define BCM281XX_MASTER_CCU_SDIO1		0
+#define BCM281XX_MASTER_CCU_SDIO2		1
+#define BCM281XX_MASTER_CCU_SDIO3		2
+#define BCM281XX_MASTER_CCU_SDIO4		3
+#define BCM281XX_MASTER_CCU_USB_IC		4
+#define BCM281XX_MASTER_CCU_HSIC2_48M		5
+#define BCM281XX_MASTER_CCU_HSIC2_12M		6
+#define BCM281XX_MASTER_CCU_CLOCK_COUNT		7
+
+/* slave CCU clock ids */
+
+#define BCM281XX_SLAVE_CCU_UARTB		0
+#define BCM281XX_SLAVE_CCU_UARTB2		1
+#define BCM281XX_SLAVE_CCU_UARTB3		2
+#define BCM281XX_SLAVE_CCU_UARTB4		3
+#define BCM281XX_SLAVE_CCU_SSP0			4
+#define BCM281XX_SLAVE_CCU_SSP2			5
+#define BCM281XX_SLAVE_CCU_BSC1			6
+#define BCM281XX_SLAVE_CCU_BSC2			7
+#define BCM281XX_SLAVE_CCU_BSC3			8
+#define BCM281XX_SLAVE_CCU_PWM			9
+#define BCM281XX_SLAVE_CCU_CLOCK_COUNT		10
+
+#endif /* _CLOCK_BCM281XX_H */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/bcm2835-aux.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/bcm2835-aux.h
new file mode 100644
index 0000000000000000000000000000000000000000..d91156e2658dabeaaa8624921c322646d3d18dda
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/bcm2835-aux.h
@@ -0,0 +1,17 @@
+/*
+ * Copyright (C) 2015 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#define BCM2835_AUX_CLOCK_UART		0
+#define BCM2835_AUX_CLOCK_SPI1		1
+#define BCM2835_AUX_CLOCK_SPI2		2
+#define BCM2835_AUX_CLOCK_COUNT		3
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/bcm2835.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/bcm2835.h
new file mode 100644
index 0000000000000000000000000000000000000000..a0c812b0fa391d149b4f546db39bdc4bef207960
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/bcm2835.h
@@ -0,0 +1,68 @@
+/*
+ * Copyright (C) 2015 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#define BCM2835_PLLA			0
+#define BCM2835_PLLB			1
+#define BCM2835_PLLC			2
+#define BCM2835_PLLD			3
+#define BCM2835_PLLH			4
+
+#define BCM2835_PLLA_CORE		5
+#define BCM2835_PLLA_PER		6
+#define BCM2835_PLLB_ARM		7
+#define BCM2835_PLLC_CORE0		8
+#define BCM2835_PLLC_CORE1		9
+#define BCM2835_PLLC_CORE2		10
+#define BCM2835_PLLC_PER		11
+#define BCM2835_PLLD_CORE		12
+#define BCM2835_PLLD_PER		13
+#define BCM2835_PLLH_RCAL		14
+#define BCM2835_PLLH_AUX		15
+#define BCM2835_PLLH_PIX		16
+
+#define BCM2835_CLOCK_TIMER		17
+#define BCM2835_CLOCK_OTP		18
+#define BCM2835_CLOCK_UART		19
+#define BCM2835_CLOCK_VPU		20
+#define BCM2835_CLOCK_V3D		21
+#define BCM2835_CLOCK_ISP		22
+#define BCM2835_CLOCK_H264		23
+#define BCM2835_CLOCK_VEC		24
+#define BCM2835_CLOCK_HSM		25
+#define BCM2835_CLOCK_SDRAM		26
+#define BCM2835_CLOCK_TSENS		27
+#define BCM2835_CLOCK_EMMC		28
+#define BCM2835_CLOCK_PERI_IMAGE	29
+#define BCM2835_CLOCK_PWM		30
+#define BCM2835_CLOCK_PCM		31
+
+#define BCM2835_PLLA_DSI0		32
+#define BCM2835_PLLA_CCP2		33
+#define BCM2835_PLLD_DSI0		34
+#define BCM2835_PLLD_DSI1		35
+
+#define BCM2835_CLOCK_AVEO		36
+#define BCM2835_CLOCK_DFT		37
+#define BCM2835_CLOCK_GP0		38
+#define BCM2835_CLOCK_GP1		39
+#define BCM2835_CLOCK_GP2		40
+#define BCM2835_CLOCK_SLIM		41
+#define BCM2835_CLOCK_SMI		42
+#define BCM2835_CLOCK_TEC		43
+#define BCM2835_CLOCK_DPI		44
+#define BCM2835_CLOCK_CAM0		45
+#define BCM2835_CLOCK_CAM1		46
+#define BCM2835_CLOCK_DSI0E		47
+#define BCM2835_CLOCK_DSI1E		48
+#define BCM2835_CLOCK_DSI0P		49
+#define BCM2835_CLOCK_DSI1P		50
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/berlin2.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/berlin2.h
new file mode 100644
index 0000000000000000000000000000000000000000..b07b8efab075453e003d76137607aff173164819
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/berlin2.h
@@ -0,0 +1,46 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Berlin2 BG2/BG2CD clock tree IDs
+ */
+
+#define CLKID_SYS		0
+#define CLKID_CPU		1
+#define CLKID_DRMFIGO		2
+#define CLKID_CFG		3
+#define CLKID_GFX		4
+#define CLKID_ZSP		5
+#define CLKID_PERIF		6
+#define CLKID_PCUBE		7
+#define CLKID_VSCOPE		8
+#define CLKID_NFC_ECC		9
+#define CLKID_VPP		10
+#define CLKID_APP		11
+#define CLKID_AUDIO0		12
+#define CLKID_AUDIO2		13
+#define CLKID_AUDIO3		14
+#define CLKID_AUDIO1		15
+#define CLKID_GFX3D_CORE	16
+#define CLKID_GFX3D_SYS		17
+#define CLKID_ARC		18
+#define CLKID_VIP		19
+#define CLKID_SDIO0XIN		20
+#define CLKID_SDIO1XIN		21
+#define CLKID_GFX3D_EXTRA	22
+#define CLKID_GC360		23
+#define CLKID_SDIO_DLLMST	24
+#define CLKID_GETH0		25
+#define CLKID_GETH1		26
+#define CLKID_SATA		27
+#define CLKID_AHBAPB		28
+#define CLKID_USB0		29
+#define CLKID_USB1		30
+#define CLKID_PBRIDGE		31
+#define CLKID_SDIO0		32
+#define CLKID_SDIO1		33
+#define CLKID_NFC		34
+#define CLKID_SMEMC		35
+#define CLKID_AUDIOHD		36
+#define CLKID_VIDEO0		37
+#define CLKID_VIDEO1		38
+#define CLKID_VIDEO2		39
+#define CLKID_TWD		40
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/berlin2q.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/berlin2q.h
new file mode 100644
index 0000000000000000000000000000000000000000..44b4ac3828508fc0641b69674901ea0dfe5c1564
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/berlin2q.h
@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Berlin2 BG2Q clock tree IDs
+ */
+
+#define CLKID_SYS		0
+#define CLKID_DRMFIGO		1
+#define CLKID_CFG		2
+#define CLKID_GFX2D		3
+#define CLKID_ZSP		4
+#define CLKID_PERIF		5
+#define CLKID_PCUBE		6
+#define CLKID_VSCOPE		7
+#define CLKID_NFC_ECC		8
+#define CLKID_VPP		9
+#define CLKID_APP		10
+#define CLKID_SDIO0XIN		11
+#define CLKID_SDIO1XIN		12
+#define CLKID_GFX2DAXI		13
+#define CLKID_GETH0		14
+#define CLKID_SATA		15
+#define CLKID_AHBAPB		16
+#define CLKID_USB0		17
+#define CLKID_USB1		18
+#define CLKID_USB2		19
+#define CLKID_USB3		20
+#define CLKID_PBRIDGE		21
+#define CLKID_SDIO		22
+#define CLKID_NFC		23
+#define CLKID_SMEMC		24
+#define CLKID_PCIE		25
+#define CLKID_TWD		26
+#define CLKID_CPU		27
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/boston-clock.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/boston-clock.h
new file mode 100644
index 0000000000000000000000000000000000000000..a6f0098211378654cc8321860b88da4ba972a850
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/boston-clock.h
@@ -0,0 +1,14 @@
+/*
+ * Copyright (C) 2016 Imagination Technologies
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_BOSTON_CLOCK_H__
+#define __DT_BINDINGS_CLOCK_BOSTON_CLOCK_H__
+
+#define BOSTON_CLK_INPUT 0
+#define BOSTON_CLK_SYS 1
+#define BOSTON_CLK_CPU 2
+
+#endif /* __DT_BINDINGS_CLOCK_BOSTON_CLOCK_H__ */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/clps711x-clock.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/clps711x-clock.h
new file mode 100644
index 0000000000000000000000000000000000000000..0c4c80b632426f810865ef794b8d2a534913cbb7
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/clps711x-clock.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_CLPS711X_H
+#define __DT_BINDINGS_CLOCK_CLPS711X_H
+
+#define CLPS711X_CLK_DUMMY	0
+#define CLPS711X_CLK_CPU	1
+#define CLPS711X_CLK_BUS	2
+#define CLPS711X_CLK_PLL	3
+#define CLPS711X_CLK_TIMERREF	4
+#define CLPS711X_CLK_TIMER1	5
+#define CLPS711X_CLK_TIMER2	6
+#define CLPS711X_CLK_PWM	7
+#define CLPS711X_CLK_SPIREF	8
+#define CLPS711X_CLK_SPI	9
+#define CLPS711X_CLK_UART	10
+#define CLPS711X_CLK_TICK	11
+#define CLPS711X_CLK_MAX	12
+
+#endif
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/cortina,gemini-clock.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/cortina,gemini-clock.h
new file mode 100644
index 0000000000000000000000000000000000000000..04c3404b2d335a16ef8f19fe7df86cc4488b6831
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/cortina,gemini-clock.h
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef DT_BINDINGS_CORTINA_GEMINI_CLOCK_H
+#define DT_BINDINGS_CORTINA_GEMINI_CLOCK_H
+
+/* RTC, AHB, APB, CPU, PCI, TVC, UART clocks and 13 gates */
+#define GEMINI_NUM_CLKS 20
+
+#define GEMINI_CLK_RTC 0
+#define GEMINI_CLK_AHB 1
+#define GEMINI_CLK_APB 2
+#define GEMINI_CLK_CPU 3
+#define GEMINI_CLK_PCI 4
+#define GEMINI_CLK_TVC 5
+#define GEMINI_CLK_UART 6
+#define GEMINI_CLK_GATES 7
+#define GEMINI_CLK_GATE_SECURITY 7
+#define GEMINI_CLK_GATE_GMAC0 8
+#define GEMINI_CLK_GATE_GMAC1 9
+#define GEMINI_CLK_GATE_SATA0 10
+#define GEMINI_CLK_GATE_SATA1 11
+#define GEMINI_CLK_GATE_USB0 12
+#define GEMINI_CLK_GATE_USB1 13
+#define GEMINI_CLK_GATE_IDE 14
+#define GEMINI_CLK_GATE_PCI 15
+#define GEMINI_CLK_GATE_DDR 16
+#define GEMINI_CLK_GATE_FLASH 17
+#define GEMINI_CLK_GATE_TVC 18
+#define GEMINI_CLK_GATE_BOOT 19
+
+#endif /* DT_BINDINGS_CORTINA_GEMINI_CLOCK_H */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/dm814.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/dm814.h
new file mode 100644
index 0000000000000000000000000000000000000000..0e7099a344e1f2ae572a19862bc5c4d0175e3d8b
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/dm814.h
@@ -0,0 +1,45 @@
+/*
+ * Copyright 2017 Texas Instruments, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#ifndef __DT_BINDINGS_CLK_DM814_H
+#define __DT_BINDINGS_CLK_DM814_H
+
+#define DM814_CLKCTRL_OFFSET	0x0
+#define DM814_CLKCTRL_INDEX(offset)	((offset) - DM814_CLKCTRL_OFFSET)
+
+/* default clocks */
+#define DM814_USB_OTG_HS_CLKCTRL	DM814_CLKCTRL_INDEX(0x58)
+
+/* alwon clocks */
+#define DM814_UART1_CLKCTRL	DM814_CLKCTRL_INDEX(0x150)
+#define DM814_UART2_CLKCTRL	DM814_CLKCTRL_INDEX(0x154)
+#define DM814_UART3_CLKCTRL	DM814_CLKCTRL_INDEX(0x158)
+#define DM814_GPIO1_CLKCTRL	DM814_CLKCTRL_INDEX(0x15c)
+#define DM814_GPIO2_CLKCTRL	DM814_CLKCTRL_INDEX(0x160)
+#define DM814_I2C1_CLKCTRL	DM814_CLKCTRL_INDEX(0x164)
+#define DM814_I2C2_CLKCTRL	DM814_CLKCTRL_INDEX(0x168)
+#define DM814_WD_TIMER_CLKCTRL	DM814_CLKCTRL_INDEX(0x18c)
+#define DM814_MCSPI1_CLKCTRL	DM814_CLKCTRL_INDEX(0x190)
+#define DM814_GPMC_CLKCTRL	DM814_CLKCTRL_INDEX(0x1d0)
+#define DM814_CPGMAC0_CLKCTRL	DM814_CLKCTRL_INDEX(0x1d4)
+#define DM814_MPU_CLKCTRL	DM814_CLKCTRL_INDEX(0x1dc)
+#define DM814_RTC_CLKCTRL	DM814_CLKCTRL_INDEX(0x1f0)
+#define DM814_TPCC_CLKCTRL	DM814_CLKCTRL_INDEX(0x1f4)
+#define DM814_TPTC0_CLKCTRL	DM814_CLKCTRL_INDEX(0x1f8)
+#define DM814_TPTC1_CLKCTRL	DM814_CLKCTRL_INDEX(0x1fc)
+#define DM814_TPTC2_CLKCTRL	DM814_CLKCTRL_INDEX(0x200)
+#define DM814_TPTC3_CLKCTRL	DM814_CLKCTRL_INDEX(0x204)
+#define DM814_MMC1_CLKCTRL	DM814_CLKCTRL_INDEX(0x21c)
+#define DM814_MMC2_CLKCTRL	DM814_CLKCTRL_INDEX(0x220)
+#define DM814_MMC3_CLKCTRL	DM814_CLKCTRL_INDEX(0x224)
+
+#endif
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/dm816.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/dm816.h
new file mode 100644
index 0000000000000000000000000000000000000000..69e8a36d783ea121b90541213d33a42de0c80e33
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/dm816.h
@@ -0,0 +1,53 @@
+/*
+ * Copyright 2017 Texas Instruments, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#ifndef __DT_BINDINGS_CLK_DM816_H
+#define __DT_BINDINGS_CLK_DM816_H
+
+#define DM816_CLKCTRL_OFFSET	0x0
+#define DM816_CLKCTRL_INDEX(offset)	((offset) - DM816_CLKCTRL_OFFSET)
+
+/* default clocks */
+#define DM816_USB_OTG_HS_CLKCTRL	DM816_CLKCTRL_INDEX(0x58)
+
+/* alwon clocks */
+#define DM816_UART1_CLKCTRL	DM816_CLKCTRL_INDEX(0x150)
+#define DM816_UART2_CLKCTRL	DM816_CLKCTRL_INDEX(0x154)
+#define DM816_UART3_CLKCTRL	DM816_CLKCTRL_INDEX(0x158)
+#define DM816_GPIO1_CLKCTRL	DM816_CLKCTRL_INDEX(0x15c)
+#define DM816_GPIO2_CLKCTRL	DM816_CLKCTRL_INDEX(0x160)
+#define DM816_I2C1_CLKCTRL	DM816_CLKCTRL_INDEX(0x164)
+#define DM816_I2C2_CLKCTRL	DM816_CLKCTRL_INDEX(0x168)
+#define DM816_TIMER1_CLKCTRL	DM816_CLKCTRL_INDEX(0x170)
+#define DM816_TIMER2_CLKCTRL	DM816_CLKCTRL_INDEX(0x174)
+#define DM816_TIMER3_CLKCTRL	DM816_CLKCTRL_INDEX(0x178)
+#define DM816_TIMER4_CLKCTRL	DM816_CLKCTRL_INDEX(0x17c)
+#define DM816_TIMER5_CLKCTRL	DM816_CLKCTRL_INDEX(0x180)
+#define DM816_TIMER6_CLKCTRL	DM816_CLKCTRL_INDEX(0x184)
+#define DM816_TIMER7_CLKCTRL	DM816_CLKCTRL_INDEX(0x188)
+#define DM816_WD_TIMER_CLKCTRL	DM816_CLKCTRL_INDEX(0x18c)
+#define DM816_MCSPI1_CLKCTRL	DM816_CLKCTRL_INDEX(0x190)
+#define DM816_MAILBOX_CLKCTRL	DM816_CLKCTRL_INDEX(0x194)
+#define DM816_SPINBOX_CLKCTRL	DM816_CLKCTRL_INDEX(0x198)
+#define DM816_MMC1_CLKCTRL	DM816_CLKCTRL_INDEX(0x1b0)
+#define DM816_GPMC_CLKCTRL	DM816_CLKCTRL_INDEX(0x1d0)
+#define DM816_DAVINCI_MDIO_CLKCTRL	DM816_CLKCTRL_INDEX(0x1d4)
+#define DM816_EMAC1_CLKCTRL	DM816_CLKCTRL_INDEX(0x1d8)
+#define DM816_MPU_CLKCTRL	DM816_CLKCTRL_INDEX(0x1dc)
+#define DM816_RTC_CLKCTRL	DM816_CLKCTRL_INDEX(0x1f0)
+#define DM816_TPCC_CLKCTRL	DM816_CLKCTRL_INDEX(0x1f4)
+#define DM816_TPTC0_CLKCTRL	DM816_CLKCTRL_INDEX(0x1f8)
+#define DM816_TPTC1_CLKCTRL	DM816_CLKCTRL_INDEX(0x1fc)
+#define DM816_TPTC2_CLKCTRL	DM816_CLKCTRL_INDEX(0x200)
+#define DM816_TPTC3_CLKCTRL	DM816_CLKCTRL_INDEX(0x204)
+
+#endif
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/dra7.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/dra7.h
new file mode 100644
index 0000000000000000000000000000000000000000..d7549c57cac36c66bae2373eef4e517acb022f7b
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/dra7.h
@@ -0,0 +1,173 @@
+/*
+ * Copyright 2017 Texas Instruments, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#ifndef __DT_BINDINGS_CLK_DRA7_H
+#define __DT_BINDINGS_CLK_DRA7_H
+
+#define DRA7_CLKCTRL_OFFSET	0x20
+#define DRA7_CLKCTRL_INDEX(offset)	((offset) - DRA7_CLKCTRL_OFFSET)
+
+/* mpu clocks */
+#define DRA7_MPU_CLKCTRL	DRA7_CLKCTRL_INDEX(0x20)
+
+/* ipu clocks */
+#define DRA7_IPU_CLKCTRL_OFFSET	0x40
+#define DRA7_IPU_CLKCTRL_INDEX(offset)	((offset) - DRA7_IPU_CLKCTRL_OFFSET)
+#define DRA7_MCASP1_CLKCTRL	DRA7_IPU_CLKCTRL_INDEX(0x50)
+#define DRA7_TIMER5_CLKCTRL	DRA7_IPU_CLKCTRL_INDEX(0x58)
+#define DRA7_TIMER6_CLKCTRL	DRA7_IPU_CLKCTRL_INDEX(0x60)
+#define DRA7_TIMER7_CLKCTRL	DRA7_IPU_CLKCTRL_INDEX(0x68)
+#define DRA7_TIMER8_CLKCTRL	DRA7_IPU_CLKCTRL_INDEX(0x70)
+#define DRA7_I2C5_CLKCTRL	DRA7_IPU_CLKCTRL_INDEX(0x78)
+#define DRA7_UART6_CLKCTRL	DRA7_IPU_CLKCTRL_INDEX(0x80)
+
+/* rtc clocks */
+#define DRA7_RTC_CLKCTRL_OFFSET	0x40
+#define DRA7_RTC_CLKCTRL_INDEX(offset)	((offset) - DRA7_RTC_CLKCTRL_OFFSET)
+#define DRA7_RTCSS_CLKCTRL	DRA7_RTC_CLKCTRL_INDEX(0x44)
+
+/* coreaon clocks */
+#define DRA7_SMARTREFLEX_MPU_CLKCTRL	DRA7_CLKCTRL_INDEX(0x28)
+#define DRA7_SMARTREFLEX_CORE_CLKCTRL	DRA7_CLKCTRL_INDEX(0x38)
+
+/* l3main1 clocks */
+#define DRA7_L3_MAIN_1_CLKCTRL	DRA7_CLKCTRL_INDEX(0x20)
+#define DRA7_GPMC_CLKCTRL	DRA7_CLKCTRL_INDEX(0x28)
+#define DRA7_TPCC_CLKCTRL	DRA7_CLKCTRL_INDEX(0x70)
+#define DRA7_TPTC0_CLKCTRL	DRA7_CLKCTRL_INDEX(0x78)
+#define DRA7_TPTC1_CLKCTRL	DRA7_CLKCTRL_INDEX(0x80)
+#define DRA7_VCP1_CLKCTRL	DRA7_CLKCTRL_INDEX(0x88)
+#define DRA7_VCP2_CLKCTRL	DRA7_CLKCTRL_INDEX(0x90)
+
+/* dma clocks */
+#define DRA7_DMA_SYSTEM_CLKCTRL	DRA7_CLKCTRL_INDEX(0x20)
+
+/* emif clocks */
+#define DRA7_DMM_CLKCTRL	DRA7_CLKCTRL_INDEX(0x20)
+
+/* atl clocks */
+#define DRA7_ATL_CLKCTRL_OFFSET	0x0
+#define DRA7_ATL_CLKCTRL_INDEX(offset)	((offset) - DRA7_ATL_CLKCTRL_OFFSET)
+#define DRA7_ATL_CLKCTRL	DRA7_ATL_CLKCTRL_INDEX(0x0)
+
+/* l4cfg clocks */
+#define DRA7_L4_CFG_CLKCTRL	DRA7_CLKCTRL_INDEX(0x20)
+#define DRA7_SPINLOCK_CLKCTRL	DRA7_CLKCTRL_INDEX(0x28)
+#define DRA7_MAILBOX1_CLKCTRL	DRA7_CLKCTRL_INDEX(0x30)
+#define DRA7_MAILBOX2_CLKCTRL	DRA7_CLKCTRL_INDEX(0x48)
+#define DRA7_MAILBOX3_CLKCTRL	DRA7_CLKCTRL_INDEX(0x50)
+#define DRA7_MAILBOX4_CLKCTRL	DRA7_CLKCTRL_INDEX(0x58)
+#define DRA7_MAILBOX5_CLKCTRL	DRA7_CLKCTRL_INDEX(0x60)
+#define DRA7_MAILBOX6_CLKCTRL	DRA7_CLKCTRL_INDEX(0x68)
+#define DRA7_MAILBOX7_CLKCTRL	DRA7_CLKCTRL_INDEX(0x70)
+#define DRA7_MAILBOX8_CLKCTRL	DRA7_CLKCTRL_INDEX(0x78)
+#define DRA7_MAILBOX9_CLKCTRL	DRA7_CLKCTRL_INDEX(0x80)
+#define DRA7_MAILBOX10_CLKCTRL	DRA7_CLKCTRL_INDEX(0x88)
+#define DRA7_MAILBOX11_CLKCTRL	DRA7_CLKCTRL_INDEX(0x90)
+#define DRA7_MAILBOX12_CLKCTRL	DRA7_CLKCTRL_INDEX(0x98)
+#define DRA7_MAILBOX13_CLKCTRL	DRA7_CLKCTRL_INDEX(0xa0)
+
+/* l3instr clocks */
+#define DRA7_L3_MAIN_2_CLKCTRL	DRA7_CLKCTRL_INDEX(0x20)
+#define DRA7_L3_INSTR_CLKCTRL	DRA7_CLKCTRL_INDEX(0x28)
+
+/* dss clocks */
+#define DRA7_DSS_CORE_CLKCTRL	DRA7_CLKCTRL_INDEX(0x20)
+#define DRA7_BB2D_CLKCTRL	DRA7_CLKCTRL_INDEX(0x30)
+
+/* l3init clocks */
+#define DRA7_MMC1_CLKCTRL	DRA7_CLKCTRL_INDEX(0x28)
+#define DRA7_MMC2_CLKCTRL	DRA7_CLKCTRL_INDEX(0x30)
+#define DRA7_USB_OTG_SS2_CLKCTRL	DRA7_CLKCTRL_INDEX(0x40)
+#define DRA7_USB_OTG_SS3_CLKCTRL	DRA7_CLKCTRL_INDEX(0x48)
+#define DRA7_USB_OTG_SS4_CLKCTRL	DRA7_CLKCTRL_INDEX(0x50)
+#define DRA7_SATA_CLKCTRL	DRA7_CLKCTRL_INDEX(0x88)
+#define DRA7_PCIE1_CLKCTRL	DRA7_CLKCTRL_INDEX(0xb0)
+#define DRA7_PCIE2_CLKCTRL	DRA7_CLKCTRL_INDEX(0xb8)
+#define DRA7_GMAC_CLKCTRL	DRA7_CLKCTRL_INDEX(0xd0)
+#define DRA7_OCP2SCP1_CLKCTRL	DRA7_CLKCTRL_INDEX(0xe0)
+#define DRA7_OCP2SCP3_CLKCTRL	DRA7_CLKCTRL_INDEX(0xe8)
+#define DRA7_USB_OTG_SS1_CLKCTRL	DRA7_CLKCTRL_INDEX(0xf0)
+
+/* l4per clocks */
+#define DRA7_L4PER_CLKCTRL_OFFSET	0x0
+#define DRA7_L4PER_CLKCTRL_INDEX(offset)	((offset) - DRA7_L4PER_CLKCTRL_OFFSET)
+#define DRA7_L4_PER2_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0xc)
+#define DRA7_L4_PER3_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0x14)
+#define DRA7_TIMER10_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0x28)
+#define DRA7_TIMER11_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0x30)
+#define DRA7_TIMER2_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0x38)
+#define DRA7_TIMER3_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0x40)
+#define DRA7_TIMER4_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0x48)
+#define DRA7_TIMER9_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0x50)
+#define DRA7_ELM_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0x58)
+#define DRA7_GPIO2_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0x60)
+#define DRA7_GPIO3_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0x68)
+#define DRA7_GPIO4_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0x70)
+#define DRA7_GPIO5_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0x78)
+#define DRA7_GPIO6_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0x80)
+#define DRA7_HDQ1W_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0x88)
+#define DRA7_EPWMSS1_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0x90)
+#define DRA7_EPWMSS2_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0x98)
+#define DRA7_I2C1_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0xa0)
+#define DRA7_I2C2_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0xa8)
+#define DRA7_I2C3_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0xb0)
+#define DRA7_I2C4_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0xb8)
+#define DRA7_L4_PER1_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0xc0)
+#define DRA7_EPWMSS0_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0xc4)
+#define DRA7_TIMER13_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0xc8)
+#define DRA7_TIMER14_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0xd0)
+#define DRA7_TIMER15_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0xd8)
+#define DRA7_MCSPI1_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0xf0)
+#define DRA7_MCSPI2_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0xf8)
+#define DRA7_MCSPI3_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0x100)
+#define DRA7_MCSPI4_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0x108)
+#define DRA7_GPIO7_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0x110)
+#define DRA7_GPIO8_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0x118)
+#define DRA7_MMC3_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0x120)
+#define DRA7_MMC4_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0x128)
+#define DRA7_TIMER16_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0x130)
+#define DRA7_QSPI_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0x138)
+#define DRA7_UART1_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0x140)
+#define DRA7_UART2_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0x148)
+#define DRA7_UART3_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0x150)
+#define DRA7_UART4_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0x158)
+#define DRA7_MCASP2_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0x160)
+#define DRA7_MCASP3_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0x168)
+#define DRA7_UART5_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0x170)
+#define DRA7_MCASP5_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0x178)
+#define DRA7_MCASP8_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0x190)
+#define DRA7_MCASP4_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0x198)
+#define DRA7_AES1_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0x1a0)
+#define DRA7_AES2_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0x1a8)
+#define DRA7_DES_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0x1b0)
+#define DRA7_RNG_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0x1c0)
+#define DRA7_SHAM_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0x1c8)
+#define DRA7_UART7_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0x1d0)
+#define DRA7_UART8_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0x1e0)
+#define DRA7_UART9_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0x1e8)
+#define DRA7_DCAN2_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0x1f0)
+#define DRA7_MCASP6_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0x204)
+#define DRA7_MCASP7_CLKCTRL	DRA7_L4PER_CLKCTRL_INDEX(0x208)
+
+/* wkupaon clocks */
+#define DRA7_L4_WKUP_CLKCTRL	DRA7_CLKCTRL_INDEX(0x20)
+#define DRA7_WD_TIMER2_CLKCTRL	DRA7_CLKCTRL_INDEX(0x30)
+#define DRA7_GPIO1_CLKCTRL	DRA7_CLKCTRL_INDEX(0x38)
+#define DRA7_TIMER1_CLKCTRL	DRA7_CLKCTRL_INDEX(0x40)
+#define DRA7_TIMER12_CLKCTRL	DRA7_CLKCTRL_INDEX(0x48)
+#define DRA7_COUNTER_32K_CLKCTRL	DRA7_CLKCTRL_INDEX(0x50)
+#define DRA7_UART10_CLKCTRL	DRA7_CLKCTRL_INDEX(0x80)
+#define DRA7_DCAN1_CLKCTRL	DRA7_CLKCTRL_INDEX(0x88)
+#define DRA7_ADC_CLKCTRL	DRA7_CLKCTRL_INDEX(0xa0)
+
+#endif
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/efm32-cmu.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/efm32-cmu.h
new file mode 100644
index 0000000000000000000000000000000000000000..4b48d15fe194fb2708ce9cf9b6bd23346d942304
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/efm32-cmu.h
@@ -0,0 +1,43 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __DT_BINDINGS_CLOCK_EFM32_CMU_H
+#define __DT_BINDINGS_CLOCK_EFM32_CMU_H
+
+#define clk_HFXO		0
+#define clk_HFRCO		1
+#define clk_LFXO		2
+#define clk_LFRCO		3
+#define clk_ULFRCO		4
+#define clk_AUXHFRCO		5
+#define clk_HFCLKNODIV		6
+#define clk_HFCLK		7
+#define clk_HFPERCLK		8
+#define clk_HFCORECLK		9
+#define clk_LFACLK		10
+#define clk_LFBCLK		11
+#define clk_WDOGCLK		12
+#define clk_HFCORECLKDMA	13
+#define clk_HFCORECLKAES	14
+#define clk_HFCORECLKUSBC	15
+#define clk_HFCORECLKUSB	16
+#define clk_HFCORECLKLE		17
+#define clk_HFCORECLKEBI	18
+#define clk_HFPERCLKUSART0	19
+#define clk_HFPERCLKUSART1	20
+#define clk_HFPERCLKUSART2	21
+#define clk_HFPERCLKUART0	22
+#define clk_HFPERCLKUART1	23
+#define clk_HFPERCLKTIMER0	24
+#define clk_HFPERCLKTIMER1	25
+#define clk_HFPERCLKTIMER2	26
+#define clk_HFPERCLKTIMER3	27
+#define clk_HFPERCLKACMP0	28
+#define clk_HFPERCLKACMP1	29
+#define clk_HFPERCLKI2C0	30
+#define clk_HFPERCLKI2C1	31
+#define clk_HFPERCLKGPIO	32
+#define clk_HFPERCLKVCMP	33
+#define clk_HFPERCLKPRS		34
+#define clk_HFPERCLKADC0	35
+#define clk_HFPERCLKDAC0	36
+
+#endif /* __DT_BINDINGS_CLOCK_EFM32_CMU_H */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/exynos-audss-clk.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/exynos-audss-clk.h
new file mode 100644
index 0000000000000000000000000000000000000000..eee9fcc6e6af2006b8c55d073bbe9683ffa40d06
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/exynos-audss-clk.h
@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * This header provides constants for Samsung audio subsystem
+ * clock controller.
+ *
+ * The constants defined in this header are being used in dts
+ * and exynos audss driver.
+ */
+
+#ifndef _DT_BINDINGS_CLK_EXYNOS_AUDSS_H
+#define _DT_BINDINGS_CLK_EXYNOS_AUDSS_H
+
+#define EXYNOS_MOUT_AUDSS	0
+#define EXYNOS_MOUT_I2S	1
+#define EXYNOS_DOUT_SRP	2
+#define EXYNOS_DOUT_AUD_BUS	3
+#define EXYNOS_DOUT_I2S	4
+#define EXYNOS_SRP_CLK		5
+#define EXYNOS_I2S_BUS		6
+#define EXYNOS_SCLK_I2S	7
+#define EXYNOS_PCM_BUS		8
+#define EXYNOS_SCLK_PCM	9
+#define EXYNOS_ADMA		10
+
+#define EXYNOS_AUDSS_MAX_CLKS	11
+
+#endif
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/exynos3250.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/exynos3250.h
new file mode 100644
index 0000000000000000000000000000000000000000..c796ff02ceeb10829a70680adb4f585a0dee1752
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/exynos3250.h
@@ -0,0 +1,356 @@
+/*
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * 	Author: Tomasz Figa <t.figa@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Device Tree binding constants for Samsung Exynos3250 clock controllers.
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_SAMSUNG_EXYNOS3250_CLOCK_H
+#define _DT_BINDINGS_CLOCK_SAMSUNG_EXYNOS3250_CLOCK_H
+
+/*
+ * Let each exported clock get a unique index, which is used on DT-enabled
+ * platforms to lookup the clock from a clock specifier. These indices are
+ * therefore considered an ABI and so must not be changed. This implies
+ * that new clocks should be added either in free spaces between clock groups
+ * or at the end.
+ */
+
+
+/*
+ * Main CMU
+ */
+
+#define CLK_OSCSEL			1
+#define CLK_FIN_PLL			2
+#define CLK_FOUT_APLL			3
+#define CLK_FOUT_VPLL			4
+#define CLK_FOUT_UPLL			5
+#define CLK_FOUT_MPLL			6
+#define CLK_ARM_CLK			7
+
+/* Muxes */
+#define CLK_MOUT_MPLL_USER_L		16
+#define CLK_MOUT_GDL			17
+#define CLK_MOUT_MPLL_USER_R		18
+#define CLK_MOUT_GDR			19
+#define CLK_MOUT_EBI			20
+#define CLK_MOUT_ACLK_200		21
+#define CLK_MOUT_ACLK_160		22
+#define CLK_MOUT_ACLK_100		23
+#define CLK_MOUT_ACLK_266_1		24
+#define CLK_MOUT_ACLK_266_0		25
+#define CLK_MOUT_ACLK_266		26
+#define CLK_MOUT_VPLL			27
+#define CLK_MOUT_EPLL_USER		28
+#define CLK_MOUT_EBI_1			29
+#define CLK_MOUT_UPLL			30
+#define CLK_MOUT_ACLK_400_MCUISP_SUB	31
+#define CLK_MOUT_MPLL			32
+#define CLK_MOUT_ACLK_400_MCUISP	33
+#define CLK_MOUT_VPLLSRC		34
+#define CLK_MOUT_CAM1			35
+#define CLK_MOUT_CAM_BLK		36
+#define CLK_MOUT_MFC			37
+#define CLK_MOUT_MFC_1			38
+#define CLK_MOUT_MFC_0			39
+#define CLK_MOUT_G3D			40
+#define CLK_MOUT_G3D_1			41
+#define CLK_MOUT_G3D_0			42
+#define CLK_MOUT_MIPI0			43
+#define CLK_MOUT_FIMD0			44
+#define CLK_MOUT_UART_ISP		45
+#define CLK_MOUT_SPI1_ISP		46
+#define CLK_MOUT_SPI0_ISP		47
+#define CLK_MOUT_TSADC			48
+#define CLK_MOUT_MMC1			49
+#define CLK_MOUT_MMC0			50
+#define CLK_MOUT_UART1			51
+#define CLK_MOUT_UART0			52
+#define CLK_MOUT_SPI1			53
+#define CLK_MOUT_SPI0			54
+#define CLK_MOUT_AUDIO			55
+#define CLK_MOUT_MPLL_USER_C		56
+#define CLK_MOUT_HPM			57
+#define CLK_MOUT_CORE			58
+#define CLK_MOUT_APLL			59
+#define CLK_MOUT_ACLK_266_SUB		60
+#define CLK_MOUT_UART2			61
+#define CLK_MOUT_MMC2			62
+
+/* Dividers */
+#define CLK_DIV_GPL			64
+#define CLK_DIV_GDL			65
+#define CLK_DIV_GPR			66
+#define CLK_DIV_GDR			67
+#define CLK_DIV_MPLL_PRE		68
+#define CLK_DIV_ACLK_400_MCUISP		69
+#define CLK_DIV_EBI			70
+#define CLK_DIV_ACLK_200		71
+#define CLK_DIV_ACLK_160		72
+#define CLK_DIV_ACLK_100		73
+#define CLK_DIV_ACLK_266		74
+#define CLK_DIV_CAM1			75
+#define CLK_DIV_CAM_BLK			76
+#define CLK_DIV_MFC			77
+#define CLK_DIV_G3D			78
+#define CLK_DIV_MIPI0_PRE		79
+#define CLK_DIV_MIPI0			80
+#define CLK_DIV_FIMD0			81
+#define CLK_DIV_UART_ISP		82
+#define CLK_DIV_SPI1_ISP_PRE		83
+#define CLK_DIV_SPI1_ISP		84
+#define CLK_DIV_SPI0_ISP_PRE		85
+#define CLK_DIV_SPI0_ISP		86
+#define CLK_DIV_TSADC_PRE		87
+#define CLK_DIV_TSADC			88
+#define CLK_DIV_MMC1_PRE		89
+#define CLK_DIV_MMC1			90
+#define CLK_DIV_MMC0_PRE		91
+#define CLK_DIV_MMC0			92
+#define CLK_DIV_UART1			93
+#define CLK_DIV_UART0			94
+#define CLK_DIV_SPI1_PRE		95
+#define CLK_DIV_SPI1			96
+#define CLK_DIV_SPI0_PRE		97
+#define CLK_DIV_SPI0			98
+#define CLK_DIV_PCM			99
+#define CLK_DIV_AUDIO			100
+#define CLK_DIV_I2S			101
+#define CLK_DIV_CORE2			102
+#define CLK_DIV_APLL			103
+#define CLK_DIV_PCLK_DBG		104
+#define CLK_DIV_ATB			105
+#define CLK_DIV_COREM			106
+#define CLK_DIV_CORE			107
+#define CLK_DIV_HPM			108
+#define CLK_DIV_COPY			109
+#define CLK_DIV_UART2			110
+#define CLK_DIV_MMC2_PRE		111
+#define CLK_DIV_MMC2			112
+
+/* Gates */
+#define CLK_ASYNC_G3D			128
+#define CLK_ASYNC_MFCL			129
+#define CLK_PPMULEFT			130
+#define CLK_GPIO_LEFT			131
+#define CLK_ASYNC_ISPMX			132
+#define CLK_ASYNC_FSYSD			133
+#define CLK_ASYNC_LCD0X			134
+#define CLK_ASYNC_CAMX			135
+#define CLK_PPMURIGHT			136
+#define CLK_GPIO_RIGHT			137
+#define CLK_MONOCNT			138
+#define CLK_TZPC6			139
+#define CLK_PROVISIONKEY1		140
+#define CLK_PROVISIONKEY0		141
+#define CLK_CMU_ISPPART			142
+#define CLK_TMU_APBIF			143
+#define CLK_KEYIF			144
+#define CLK_RTC				145
+#define CLK_WDT				146
+#define CLK_MCT				147
+#define CLK_SECKEY			148
+#define CLK_TZPC5			149
+#define CLK_TZPC4			150
+#define CLK_TZPC3			151
+#define CLK_TZPC2			152
+#define CLK_TZPC1			153
+#define CLK_TZPC0			154
+#define CLK_CMU_COREPART		155
+#define CLK_CMU_TOPPART			156
+#define CLK_PMU_APBIF			157
+#define CLK_SYSREG			158
+#define CLK_CHIP_ID			159
+#define CLK_QEJPEG			160
+#define CLK_PIXELASYNCM1		161
+#define CLK_PIXELASYNCM0		162
+#define CLK_PPMUCAMIF			163
+#define CLK_QEM2MSCALER			164
+#define CLK_QEGSCALER1			165
+#define CLK_QEGSCALER0			166
+#define CLK_SMMUJPEG			167
+#define CLK_SMMUM2M2SCALER		168
+#define CLK_SMMUGSCALER1		169
+#define CLK_SMMUGSCALER0		170
+#define CLK_JPEG			171
+#define CLK_M2MSCALER			172
+#define CLK_GSCALER1			173
+#define CLK_GSCALER0			174
+#define CLK_QEMFC			175
+#define CLK_PPMUMFC_L			176
+#define CLK_SMMUMFC_L			177
+#define CLK_MFC				178
+#define CLK_SMMUG3D			179
+#define CLK_QEG3D			180
+#define CLK_PPMUG3D			181
+#define CLK_G3D				182
+#define CLK_QE_CH1_LCD			183
+#define CLK_QE_CH0_LCD			184
+#define CLK_PPMULCD0			185
+#define CLK_SMMUFIMD0			186
+#define CLK_DSIM0			187
+#define CLK_FIMD0			188
+#define CLK_CAM1			189
+#define CLK_UART_ISP_TOP		190
+#define CLK_SPI1_ISP_TOP		191
+#define CLK_SPI0_ISP_TOP		192
+#define CLK_TSADC			193
+#define CLK_PPMUFILE			194
+#define CLK_USBOTG			195
+#define CLK_USBHOST			196
+#define CLK_SROMC			197
+#define CLK_SDMMC1			198
+#define CLK_SDMMC0			199
+#define CLK_PDMA1			200
+#define CLK_PDMA0			201
+#define CLK_PWM				202
+#define CLK_PCM				203
+#define CLK_I2S				204
+#define CLK_SPI1			205
+#define CLK_SPI0			206
+#define CLK_I2C7			207
+#define CLK_I2C6			208
+#define CLK_I2C5			209
+#define CLK_I2C4			210
+#define CLK_I2C3			211
+#define CLK_I2C2			212
+#define CLK_I2C1			213
+#define CLK_I2C0			214
+#define CLK_UART1			215
+#define CLK_UART0			216
+#define CLK_BLOCK_LCD			217
+#define CLK_BLOCK_G3D			218
+#define CLK_BLOCK_MFC			219
+#define CLK_BLOCK_CAM			220
+#define CLK_SMIES			221
+#define CLK_UART2			222
+#define CLK_SDMMC2			223
+
+/* Special clocks */
+#define CLK_SCLK_JPEG			224
+#define CLK_SCLK_M2MSCALER		225
+#define CLK_SCLK_GSCALER1		226
+#define CLK_SCLK_GSCALER0		227
+#define CLK_SCLK_MFC			228
+#define CLK_SCLK_G3D			229
+#define CLK_SCLK_MIPIDPHY2L		230
+#define CLK_SCLK_MIPI0			231
+#define CLK_SCLK_FIMD0			232
+#define CLK_SCLK_CAM1			233
+#define CLK_SCLK_UART_ISP		234
+#define CLK_SCLK_SPI1_ISP		235
+#define CLK_SCLK_SPI0_ISP		236
+#define CLK_SCLK_UPLL			237
+#define CLK_SCLK_TSADC			238
+#define CLK_SCLK_EBI			239
+#define CLK_SCLK_MMC1			240
+#define CLK_SCLK_MMC0			241
+#define CLK_SCLK_I2S			242
+#define CLK_SCLK_PCM			243
+#define CLK_SCLK_SPI1			244
+#define CLK_SCLK_SPI0			245
+#define CLK_SCLK_UART1			246
+#define CLK_SCLK_UART0			247
+#define CLK_SCLK_UART2			248
+#define CLK_SCLK_MMC2			249
+
+/*
+ * Total number of clocks of main CMU.
+ * NOTE: Must be equal to last clock ID increased by one.
+ */
+#define CLK_NR_CLKS			250
+
+/*
+ * CMU DMC
+ */
+
+#define CLK_FOUT_BPLL			1
+#define CLK_FOUT_EPLL			2
+
+/* Muxes */
+#define CLK_MOUT_MPLL_MIF		8
+#define CLK_MOUT_BPLL			9
+#define CLK_MOUT_DPHY			10
+#define CLK_MOUT_DMC_BUS		11
+#define CLK_MOUT_EPLL			12
+
+/* Dividers */
+#define CLK_DIV_DMC			16
+#define CLK_DIV_DPHY			17
+#define CLK_DIV_DMC_PRE			18
+#define CLK_DIV_DMCP			19
+#define CLK_DIV_DMCD			20
+
+/*
+ * Total number of clocks of main CMU.
+ * NOTE: Must be equal to last clock ID increased by one.
+ */
+#define NR_CLKS_DMC			21
+
+/*
+ * CMU ISP
+ */
+
+/* Dividers */
+
+#define CLK_DIV_ISP1			1
+#define CLK_DIV_ISP0			2
+#define CLK_DIV_MCUISP1			3
+#define CLK_DIV_MCUISP0			4
+#define CLK_DIV_MPWM			5
+
+/* Gates */
+
+#define CLK_UART_ISP			8
+#define CLK_WDT_ISP			9
+#define CLK_PWM_ISP			10
+#define CLK_I2C1_ISP			11
+#define CLK_I2C0_ISP			12
+#define CLK_MPWM_ISP			13
+#define CLK_MCUCTL_ISP			14
+#define CLK_PPMUISPX			15
+#define CLK_PPMUISPMX			16
+#define CLK_QE_LITE1			17
+#define CLK_QE_LITE0			18
+#define CLK_QE_FD			19
+#define CLK_QE_DRC			20
+#define CLK_QE_ISP			21
+#define CLK_CSIS1			22
+#define CLK_SMMU_LITE1			23
+#define CLK_SMMU_LITE0			24
+#define CLK_SMMU_FD			25
+#define CLK_SMMU_DRC			26
+#define CLK_SMMU_ISP			27
+#define CLK_GICISP			28
+#define CLK_CSIS0			29
+#define CLK_MCUISP			30
+#define CLK_LITE1			31
+#define CLK_LITE0			32
+#define CLK_FD				33
+#define CLK_DRC				34
+#define CLK_ISP				35
+#define CLK_QE_ISPCX			36
+#define CLK_QE_SCALERP			37
+#define CLK_QE_SCALERC			38
+#define CLK_SMMU_SCALERP		39
+#define CLK_SMMU_SCALERC		40
+#define CLK_SCALERP			41
+#define CLK_SCALERC			42
+#define CLK_SPI1_ISP			43
+#define CLK_SPI0_ISP			44
+#define CLK_SMMU_ISPCX			45
+#define CLK_ASYNCAXIM			46
+#define CLK_SCLK_MPWM_ISP		47
+
+/*
+ * Total number of clocks of CMU_ISP.
+ * NOTE: Must be equal to last clock ID increased by one.
+ */
+#define NR_CLKS_ISP			48
+
+#endif /* _DT_BINDINGS_CLOCK_SAMSUNG_EXYNOS3250_CLOCK_H */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/exynos4.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/exynos4.h
new file mode 100644
index 0000000000000000000000000000000000000000..e9f9d400c322f10f04417d69456de75a4d3be17e
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/exynos4.h
@@ -0,0 +1,310 @@
+/*
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * Author: Andrzej Hajda <a.hajda@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Device Tree binding constants for Exynos4 clock controller.
+*/
+
+#ifndef _DT_BINDINGS_CLOCK_EXYNOS_4_H
+#define _DT_BINDINGS_CLOCK_EXYNOS_4_H
+
+/* core clocks */
+#define CLK_XXTI		1
+#define CLK_XUSBXTI		2
+#define CLK_FIN_PLL		3
+#define CLK_FOUT_APLL		4
+#define CLK_FOUT_MPLL		5
+#define CLK_FOUT_EPLL		6
+#define CLK_FOUT_VPLL		7
+#define CLK_SCLK_APLL		8
+#define CLK_SCLK_MPLL		9
+#define CLK_SCLK_EPLL		10
+#define CLK_SCLK_VPLL		11
+#define CLK_ARM_CLK		12
+#define CLK_ACLK200		13
+#define CLK_ACLK100		14
+#define CLK_ACLK160		15
+#define CLK_ACLK133		16
+#define CLK_MOUT_MPLL_USER_T	17 /* Exynos4x12 only */
+#define CLK_MOUT_MPLL_USER_C	18 /* Exynos4x12 only */
+#define CLK_MOUT_CORE		19
+#define CLK_MOUT_APLL		20
+#define CLK_SCLK_HDMIPHY	22
+#define CLK_OUT_DMC		23
+#define CLK_OUT_TOP		24
+#define CLK_OUT_LEFTBUS		25
+#define CLK_OUT_RIGHTBUS	26
+#define CLK_OUT_CPU		27
+
+/* gate for special clocks (sclk) */
+#define CLK_SCLK_FIMC0		128
+#define CLK_SCLK_FIMC1		129
+#define CLK_SCLK_FIMC2		130
+#define CLK_SCLK_FIMC3		131
+#define CLK_SCLK_CAM0		132
+#define CLK_SCLK_CAM1		133
+#define CLK_SCLK_CSIS0		134
+#define CLK_SCLK_CSIS1		135
+#define CLK_SCLK_HDMI		136
+#define CLK_SCLK_MIXER		137
+#define CLK_SCLK_DAC		138
+#define CLK_SCLK_PIXEL		139
+#define CLK_SCLK_FIMD0		140
+#define CLK_SCLK_MDNIE0		141 /* Exynos4412 only */
+#define CLK_SCLK_MDNIE_PWM0	142
+#define CLK_SCLK_MIPI0		143
+#define CLK_SCLK_AUDIO0		144
+#define CLK_SCLK_MMC0		145
+#define CLK_SCLK_MMC1		146
+#define CLK_SCLK_MMC2		147
+#define CLK_SCLK_MMC3		148
+#define CLK_SCLK_MMC4		149
+#define CLK_SCLK_SATA		150 /* Exynos4210 only */
+#define CLK_SCLK_UART0		151
+#define CLK_SCLK_UART1		152
+#define CLK_SCLK_UART2		153
+#define CLK_SCLK_UART3		154
+#define CLK_SCLK_UART4		155
+#define CLK_SCLK_AUDIO1		156
+#define CLK_SCLK_AUDIO2		157
+#define CLK_SCLK_SPDIF		158
+#define CLK_SCLK_SPI0		159
+#define CLK_SCLK_SPI1		160
+#define CLK_SCLK_SPI2		161
+#define CLK_SCLK_SLIMBUS	162
+#define CLK_SCLK_FIMD1		163 /* Exynos4210 only */
+#define CLK_SCLK_MIPI1		164 /* Exynos4210 only */
+#define CLK_SCLK_PCM1		165
+#define CLK_SCLK_PCM2		166
+#define CLK_SCLK_I2S1		167
+#define CLK_SCLK_I2S2		168
+#define CLK_SCLK_MIPIHSI	169 /* Exynos4412 only */
+#define CLK_SCLK_MFC		170
+#define CLK_SCLK_PCM0		171
+#define CLK_SCLK_G3D		172
+#define CLK_SCLK_PWM_ISP	173 /* Exynos4x12 only */
+#define CLK_SCLK_SPI0_ISP	174 /* Exynos4x12 only */
+#define CLK_SCLK_SPI1_ISP	175 /* Exynos4x12 only */
+#define CLK_SCLK_UART_ISP	176 /* Exynos4x12 only */
+#define CLK_SCLK_FIMG2D		177
+
+/* gate clocks */
+#define CLK_SSS			255
+#define CLK_FIMC0		256
+#define CLK_FIMC1		257
+#define CLK_FIMC2		258
+#define CLK_FIMC3		259
+#define CLK_CSIS0		260
+#define CLK_CSIS1		261
+#define CLK_JPEG		262
+#define CLK_SMMU_FIMC0		263
+#define CLK_SMMU_FIMC1		264
+#define CLK_SMMU_FIMC2		265
+#define CLK_SMMU_FIMC3		266
+#define CLK_SMMU_JPEG		267
+#define CLK_VP			268
+#define CLK_MIXER		269
+#define CLK_TVENC		270 /* Exynos4210 only */
+#define CLK_HDMI		271
+#define CLK_SMMU_TV		272
+#define CLK_MFC			273
+#define CLK_SMMU_MFCL		274
+#define CLK_SMMU_MFCR		275
+#define CLK_G3D			276
+#define CLK_G2D			277
+#define CLK_ROTATOR		278
+#define CLK_MDMA		279
+#define CLK_SMMU_G2D		280
+#define CLK_SMMU_ROTATOR	281
+#define CLK_SMMU_MDMA		282
+#define CLK_FIMD0		283
+#define CLK_MIE0		284
+#define CLK_MDNIE0		285 /* Exynos4412 only */
+#define CLK_DSIM0		286
+#define CLK_SMMU_FIMD0		287
+#define CLK_FIMD1		288 /* Exynos4210 only */
+#define CLK_MIE1		289 /* Exynos4210 only */
+#define CLK_DSIM1		290 /* Exynos4210 only */
+#define CLK_SMMU_FIMD1		291 /* Exynos4210 only */
+#define CLK_PDMA0		292
+#define CLK_PDMA1		293
+#define CLK_PCIE_PHY		294
+#define CLK_SATA_PHY		295 /* Exynos4210 only */
+#define CLK_TSI			296
+#define CLK_SDMMC0		297
+#define CLK_SDMMC1		298
+#define CLK_SDMMC2		299
+#define CLK_SDMMC3		300
+#define CLK_SDMMC4		301
+#define CLK_SATA		302 /* Exynos4210 only */
+#define CLK_SROMC		303
+#define CLK_USB_HOST		304
+#define CLK_USB_DEVICE		305
+#define CLK_PCIE		306
+#define CLK_ONENAND		307
+#define CLK_NFCON		308
+#define CLK_SMMU_PCIE		309
+#define CLK_GPS			310
+#define CLK_SMMU_GPS		311
+#define CLK_UART0		312
+#define CLK_UART1		313
+#define CLK_UART2		314
+#define CLK_UART3		315
+#define CLK_UART4		316
+#define CLK_I2C0		317
+#define CLK_I2C1		318
+#define CLK_I2C2		319
+#define CLK_I2C3		320
+#define CLK_I2C4		321
+#define CLK_I2C5		322
+#define CLK_I2C6		323
+#define CLK_I2C7		324
+#define CLK_I2C_HDMI		325
+#define CLK_TSADC		326
+#define CLK_SPI0		327
+#define CLK_SPI1		328
+#define CLK_SPI2		329
+#define CLK_I2S1		330
+#define CLK_I2S2		331
+#define CLK_PCM0		332
+#define CLK_I2S0		333
+#define CLK_PCM1		334
+#define CLK_PCM2		335
+#define CLK_PWM			336
+#define CLK_SLIMBUS		337
+#define CLK_SPDIF		338
+#define CLK_AC97		339
+#define CLK_MODEMIF		340
+#define CLK_CHIPID		341
+#define CLK_SYSREG		342
+#define CLK_HDMI_CEC		343
+#define CLK_MCT			344
+#define CLK_WDT			345
+#define CLK_RTC			346
+#define CLK_KEYIF		347
+#define CLK_AUDSS		348
+#define CLK_MIPI_HSI		349 /* Exynos4210 only */
+#define CLK_PIXELASYNCM0	351
+#define CLK_PIXELASYNCM1	352
+#define CLK_FIMC_LITE0		353 /* Exynos4x12 only */
+#define CLK_FIMC_LITE1		354 /* Exynos4x12 only */
+#define CLK_PPMUISPX		355 /* Exynos4x12 only */
+#define CLK_PPMUISPMX		356 /* Exynos4x12 only */
+#define CLK_FIMC_ISP		357 /* Exynos4x12 only */
+#define CLK_FIMC_DRC		358 /* Exynos4x12 only */
+#define CLK_FIMC_FD		359 /* Exynos4x12 only */
+#define CLK_MCUISP		360 /* Exynos4x12 only */
+#define CLK_GICISP		361 /* Exynos4x12 only */
+#define CLK_SMMU_ISP		362 /* Exynos4x12 only */
+#define CLK_SMMU_DRC		363 /* Exynos4x12 only */
+#define CLK_SMMU_FD		364 /* Exynos4x12 only */
+#define CLK_SMMU_LITE0		365 /* Exynos4x12 only */
+#define CLK_SMMU_LITE1		366 /* Exynos4x12 only */
+#define CLK_MCUCTL_ISP		367 /* Exynos4x12 only */
+#define CLK_MPWM_ISP		368 /* Exynos4x12 only */
+#define CLK_I2C0_ISP		369 /* Exynos4x12 only */
+#define CLK_I2C1_ISP		370 /* Exynos4x12 only */
+#define CLK_MTCADC_ISP		371 /* Exynos4x12 only */
+#define CLK_PWM_ISP		372 /* Exynos4x12 only */
+#define CLK_WDT_ISP		373 /* Exynos4x12 only */
+#define CLK_UART_ISP		374 /* Exynos4x12 only */
+#define CLK_ASYNCAXIM		375 /* Exynos4x12 only */
+#define CLK_SMMU_ISPCX		376 /* Exynos4x12 only */
+#define CLK_SPI0_ISP		377 /* Exynos4x12 only */
+#define CLK_SPI1_ISP		378 /* Exynos4x12 only */
+#define CLK_PWM_ISP_SCLK	379 /* Exynos4x12 only */
+#define CLK_SPI0_ISP_SCLK	380 /* Exynos4x12 only */
+#define CLK_SPI1_ISP_SCLK	381 /* Exynos4x12 only */
+#define CLK_UART_ISP_SCLK	382 /* Exynos4x12 only */
+#define CLK_TMU_APBIF		383
+
+/* mux clocks */
+#define CLK_MOUT_FIMC0		384
+#define CLK_MOUT_FIMC1		385
+#define CLK_MOUT_FIMC2		386
+#define CLK_MOUT_FIMC3		387
+#define CLK_MOUT_CAM0		388
+#define CLK_MOUT_CAM1		389
+#define CLK_MOUT_CSIS0		390
+#define CLK_MOUT_CSIS1		391
+#define CLK_MOUT_G3D0		392
+#define CLK_MOUT_G3D1		393
+#define CLK_MOUT_G3D		394
+#define CLK_ACLK400_MCUISP	395 /* Exynos4x12 only */
+#define CLK_MOUT_HDMI		396
+#define CLK_MOUT_MIXER		397
+
+/* gate clocks - ppmu */
+#define CLK_PPMULEFT		400
+#define CLK_PPMURIGHT		401
+#define CLK_PPMUCAMIF		402
+#define CLK_PPMUTV		403
+#define CLK_PPMUMFC_L		404
+#define CLK_PPMUMFC_R		405
+#define CLK_PPMUG3D		406
+#define CLK_PPMUIMAGE		407
+#define CLK_PPMULCD0		408
+#define CLK_PPMULCD1		409 /* Exynos4210 only */
+#define CLK_PPMUFILE		410
+#define CLK_PPMUGPS		411
+#define CLK_PPMUDMC0		412
+#define CLK_PPMUDMC1		413
+#define CLK_PPMUCPU		414
+#define CLK_PPMUACP		415
+
+/* div clocks */
+#define CLK_DIV_ISP0		450 /* Exynos4x12 only */
+#define CLK_DIV_ISP1		451 /* Exynos4x12 only */
+#define CLK_DIV_MCUISP0		452 /* Exynos4x12 only */
+#define CLK_DIV_MCUISP1		453 /* Exynos4x12 only */
+#define CLK_DIV_ACLK200		454 /* Exynos4x12 only */
+#define CLK_DIV_ACLK400_MCUISP	455 /* Exynos4x12 only */
+#define CLK_DIV_ACP		456
+#define CLK_DIV_DMC		457
+#define CLK_DIV_C2C		458 /* Exynos4x12 only */
+#define CLK_DIV_GDL		459
+#define CLK_DIV_GDR		460
+
+/* must be greater than maximal clock id */
+#define CLK_NR_CLKS		461
+
+/* Exynos4x12 ISP clocks */
+#define CLK_ISP_FIMC_ISP		 1
+#define CLK_ISP_FIMC_DRC		 2
+#define CLK_ISP_FIMC_FD			 3
+#define CLK_ISP_FIMC_LITE0		 4
+#define CLK_ISP_FIMC_LITE1		 5
+#define CLK_ISP_MCUISP			 6
+#define CLK_ISP_GICISP			 7
+#define CLK_ISP_SMMU_ISP		 8
+#define CLK_ISP_SMMU_DRC		 9
+#define CLK_ISP_SMMU_FD			10
+#define CLK_ISP_SMMU_LITE0		11
+#define CLK_ISP_SMMU_LITE1		12
+#define CLK_ISP_PPMUISPMX		13
+#define CLK_ISP_PPMUISPX		14
+#define CLK_ISP_MCUCTL_ISP		15
+#define CLK_ISP_MPWM_ISP		16
+#define CLK_ISP_I2C0_ISP		17
+#define CLK_ISP_I2C1_ISP		18
+#define CLK_ISP_MTCADC_ISP		19
+#define CLK_ISP_PWM_ISP			20
+#define CLK_ISP_WDT_ISP			21
+#define CLK_ISP_UART_ISP		22
+#define CLK_ISP_ASYNCAXIM		23
+#define CLK_ISP_SMMU_ISPCX		24
+#define CLK_ISP_SPI0_ISP		25
+#define CLK_ISP_SPI1_ISP		26
+
+#define CLK_ISP_DIV_ISP0		27
+#define CLK_ISP_DIV_ISP1		28
+#define CLK_ISP_DIV_MCUISP0		29
+#define CLK_ISP_DIV_MCUISP1		30
+
+#define CLK_NR_ISP_CLKS			31
+
+#endif /* _DT_BINDINGS_CLOCK_EXYNOS_4_H */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/exynos5250.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/exynos5250.h
new file mode 100644
index 0000000000000000000000000000000000000000..15508adcdfde5451a8d8a230bf0f2e3c29cbd7a4
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/exynos5250.h
@@ -0,0 +1,182 @@
+/*
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * Author: Andrzej Hajda <a.hajda@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Device Tree binding constants for Exynos5250 clock controller.
+*/
+
+#ifndef _DT_BINDINGS_CLOCK_EXYNOS_5250_H
+#define _DT_BINDINGS_CLOCK_EXYNOS_5250_H
+
+/* core clocks */
+#define CLK_FIN_PLL		1
+#define CLK_FOUT_APLL		2
+#define CLK_FOUT_MPLL		3
+#define CLK_FOUT_BPLL		4
+#define CLK_FOUT_GPLL		5
+#define CLK_FOUT_CPLL		6
+#define CLK_FOUT_EPLL		7
+#define CLK_FOUT_VPLL		8
+#define CLK_ARM_CLK		9
+
+/* gate for special clocks (sclk) */
+#define CLK_SCLK_CAM_BAYER	128
+#define CLK_SCLK_CAM0		129
+#define CLK_SCLK_CAM1		130
+#define CLK_SCLK_GSCL_WA	131
+#define CLK_SCLK_GSCL_WB	132
+#define CLK_SCLK_FIMD1		133
+#define CLK_SCLK_MIPI1		134
+#define CLK_SCLK_DP		135
+#define CLK_SCLK_HDMI		136
+#define CLK_SCLK_PIXEL		137
+#define CLK_SCLK_AUDIO0		138
+#define CLK_SCLK_MMC0		139
+#define CLK_SCLK_MMC1		140
+#define CLK_SCLK_MMC2		141
+#define CLK_SCLK_MMC3		142
+#define CLK_SCLK_SATA		143
+#define CLK_SCLK_USB3		144
+#define CLK_SCLK_JPEG		145
+#define CLK_SCLK_UART0		146
+#define CLK_SCLK_UART1		147
+#define CLK_SCLK_UART2		148
+#define CLK_SCLK_UART3		149
+#define CLK_SCLK_PWM		150
+#define CLK_SCLK_AUDIO1		151
+#define CLK_SCLK_AUDIO2		152
+#define CLK_SCLK_SPDIF		153
+#define CLK_SCLK_SPI0		154
+#define CLK_SCLK_SPI1		155
+#define CLK_SCLK_SPI2		156
+#define CLK_DIV_I2S1		157
+#define CLK_DIV_I2S2		158
+#define CLK_SCLK_HDMIPHY	159
+#define CLK_DIV_PCM0		160
+
+/* gate clocks */
+#define CLK_GSCL0		256
+#define CLK_GSCL1		257
+#define CLK_GSCL2		258
+#define CLK_GSCL3		259
+#define CLK_GSCL_WA		260
+#define CLK_GSCL_WB		261
+#define CLK_SMMU_GSCL0		262
+#define CLK_SMMU_GSCL1		263
+#define CLK_SMMU_GSCL2		264
+#define CLK_SMMU_GSCL3		265
+#define CLK_MFC			266
+#define CLK_SMMU_MFCL		267
+#define CLK_SMMU_MFCR		268
+#define CLK_ROTATOR		269
+#define CLK_JPEG		270
+#define CLK_MDMA1		271
+#define CLK_SMMU_ROTATOR	272
+#define CLK_SMMU_JPEG		273
+#define CLK_SMMU_MDMA1		274
+#define CLK_PDMA0		275
+#define CLK_PDMA1		276
+#define CLK_SATA		277
+#define CLK_USBOTG		278
+#define CLK_MIPI_HSI		279
+#define CLK_SDMMC0		280
+#define CLK_SDMMC1		281
+#define CLK_SDMMC2		282
+#define CLK_SDMMC3		283
+#define CLK_SROMC		284
+#define CLK_USB2		285
+#define CLK_USB3		286
+#define CLK_SATA_PHYCTRL	287
+#define CLK_SATA_PHYI2C		288
+#define CLK_UART0		289
+#define CLK_UART1		290
+#define CLK_UART2		291
+#define CLK_UART3		292
+#define CLK_UART4		293
+#define CLK_I2C0		294
+#define CLK_I2C1		295
+#define CLK_I2C2		296
+#define CLK_I2C3		297
+#define CLK_I2C4		298
+#define CLK_I2C5		299
+#define CLK_I2C6		300
+#define CLK_I2C7		301
+#define CLK_I2C_HDMI		302
+#define CLK_ADC			303
+#define CLK_SPI0		304
+#define CLK_SPI1		305
+#define CLK_SPI2		306
+#define CLK_I2S1		307
+#define CLK_I2S2		308
+#define CLK_PCM1		309
+#define CLK_PCM2		310
+#define CLK_PWM			311
+#define CLK_SPDIF		312
+#define CLK_AC97		313
+#define CLK_HSI2C0		314
+#define CLK_HSI2C1		315
+#define CLK_HSI2C2		316
+#define CLK_HSI2C3		317
+#define CLK_CHIPID		318
+#define CLK_SYSREG		319
+#define CLK_PMU			320
+#define CLK_CMU_TOP		321
+#define CLK_CMU_CORE		322
+#define CLK_CMU_MEM		323
+#define CLK_TZPC0		324
+#define CLK_TZPC1		325
+#define CLK_TZPC2		326
+#define CLK_TZPC3		327
+#define CLK_TZPC4		328
+#define CLK_TZPC5		329
+#define CLK_TZPC6		330
+#define CLK_TZPC7		331
+#define CLK_TZPC8		332
+#define CLK_TZPC9		333
+#define CLK_HDMI_CEC		334
+#define CLK_MCT			335
+#define CLK_WDT			336
+#define CLK_RTC			337
+#define CLK_TMU			338
+#define CLK_FIMD1		339
+#define CLK_MIE1		340
+#define CLK_DSIM0		341
+#define CLK_DP			342
+#define CLK_MIXER		343
+#define CLK_HDMI		344
+#define CLK_G2D			345
+#define CLK_MDMA0		346
+#define CLK_SMMU_MDMA0		347
+#define CLK_SSS			348
+#define CLK_G3D			349
+#define CLK_SMMU_TV		350
+#define CLK_SMMU_FIMD1		351
+#define CLK_SMMU_2D		352
+#define CLK_SMMU_FIMC_ISP	353
+#define CLK_SMMU_FIMC_DRC	354
+#define CLK_SMMU_FIMC_SCC	355
+#define CLK_SMMU_FIMC_SCP	356
+#define CLK_SMMU_FIMC_FD	357
+#define CLK_SMMU_FIMC_MCU	358
+#define CLK_SMMU_FIMC_ODC	359
+#define CLK_SMMU_FIMC_DIS0	360
+#define CLK_SMMU_FIMC_DIS1	361
+#define CLK_SMMU_FIMC_3DNR	362
+#define CLK_SMMU_FIMC_LITE0	363
+#define CLK_SMMU_FIMC_LITE1	364
+#define CLK_CAMIF_TOP		365
+
+/* mux clocks */
+#define CLK_MOUT_HDMI		1024
+#define CLK_MOUT_GPLL		1025
+#define CLK_MOUT_ACLK200_DISP1_SUB	1026
+#define CLK_MOUT_ACLK300_DISP1_SUB	1027
+
+/* must be greater than maximal clock id */
+#define CLK_NR_CLKS		1028
+
+#endif /* _DT_BINDINGS_CLOCK_EXYNOS_5250_H */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/exynos5260-clk.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/exynos5260-clk.h
new file mode 100644
index 0000000000000000000000000000000000000000..a4bac9a1764fc1cde39aa52dbd51f1a22f13b16e
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/exynos5260-clk.h
@@ -0,0 +1,469 @@
+/*
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * Author: Rahul Sharma <rahul.sharma@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Provides Constants for Exynos5260 clocks.
+*/
+
+#ifndef _DT_BINDINGS_CLK_EXYNOS5260_H
+#define _DT_BINDINGS_CLK_EXYNOS5260_H
+
+/* Clock names: <cmu><type><IP> */
+
+/* List Of Clocks For CMU_TOP */
+
+#define TOP_FOUT_DISP_PLL				1
+#define TOP_FOUT_AUD_PLL				2
+#define TOP_MOUT_AUDTOP_PLL_USER			3
+#define TOP_MOUT_AUD_PLL				4
+#define TOP_MOUT_DISP_PLL				5
+#define TOP_MOUT_BUSTOP_PLL_USER			6
+#define TOP_MOUT_MEMTOP_PLL_USER			7
+#define TOP_MOUT_MEDIATOP_PLL_USER			8
+#define TOP_MOUT_DISP_DISP_333				9
+#define TOP_MOUT_ACLK_DISP_333				10
+#define TOP_MOUT_DISP_DISP_222				11
+#define TOP_MOUT_ACLK_DISP_222				12
+#define TOP_MOUT_DISP_MEDIA_PIXEL			13
+#define TOP_MOUT_FIMD1					14
+#define TOP_MOUT_SCLK_PERI_SPI0_CLK			15
+#define TOP_MOUT_SCLK_PERI_SPI1_CLK			16
+#define TOP_MOUT_SCLK_PERI_SPI2_CLK			17
+#define TOP_MOUT_SCLK_PERI_UART0_UCLK			18
+#define TOP_MOUT_SCLK_PERI_UART2_UCLK			19
+#define TOP_MOUT_SCLK_PERI_UART1_UCLK			20
+#define TOP_MOUT_BUS4_BUSTOP_100			21
+#define TOP_MOUT_BUS4_BUSTOP_400			22
+#define TOP_MOUT_BUS3_BUSTOP_100			23
+#define TOP_MOUT_BUS3_BUSTOP_400			24
+#define TOP_MOUT_BUS2_BUSTOP_400			25
+#define TOP_MOUT_BUS2_BUSTOP_100			26
+#define TOP_MOUT_BUS1_BUSTOP_100			27
+#define TOP_MOUT_BUS1_BUSTOP_400			28
+#define TOP_MOUT_SCLK_FSYS_USB				29
+#define TOP_MOUT_SCLK_FSYS_MMC0_SDCLKIN_A		30
+#define TOP_MOUT_SCLK_FSYS_MMC1_SDCLKIN_A		31
+#define TOP_MOUT_SCLK_FSYS_MMC2_SDCLKIN_A		32
+#define TOP_MOUT_SCLK_FSYS_MMC0_SDCLKIN_B		33
+#define TOP_MOUT_SCLK_FSYS_MMC1_SDCLKIN_B		34
+#define TOP_MOUT_SCLK_FSYS_MMC2_SDCLKIN_B		35
+#define TOP_MOUT_ACLK_ISP1_266				36
+#define TOP_MOUT_ISP1_MEDIA_266				37
+#define TOP_MOUT_ACLK_ISP1_400				38
+#define TOP_MOUT_ISP1_MEDIA_400				39
+#define TOP_MOUT_SCLK_ISP1_SPI0				40
+#define TOP_MOUT_SCLK_ISP1_SPI1				41
+#define TOP_MOUT_SCLK_ISP1_UART				42
+#define TOP_MOUT_SCLK_ISP1_SENSOR2			43
+#define TOP_MOUT_SCLK_ISP1_SENSOR1			44
+#define TOP_MOUT_SCLK_ISP1_SENSOR0			45
+#define TOP_MOUT_ACLK_MFC_333				46
+#define TOP_MOUT_MFC_BUSTOP_333				47
+#define TOP_MOUT_ACLK_G2D_333				48
+#define TOP_MOUT_G2D_BUSTOP_333				49
+#define TOP_MOUT_ACLK_GSCL_FIMC				50
+#define TOP_MOUT_GSCL_BUSTOP_FIMC			51
+#define TOP_MOUT_ACLK_GSCL_333				52
+#define TOP_MOUT_GSCL_BUSTOP_333			53
+#define TOP_MOUT_ACLK_GSCL_400				54
+#define TOP_MOUT_M2M_MEDIATOP_400			55
+#define TOP_DOUT_ACLK_MFC_333				56
+#define TOP_DOUT_ACLK_G2D_333				57
+#define TOP_DOUT_SCLK_ISP1_SENSOR2_A			58
+#define TOP_DOUT_SCLK_ISP1_SENSOR1_A			59
+#define TOP_DOUT_SCLK_ISP1_SENSOR0_A			60
+#define TOP_DOUT_ACLK_GSCL_FIMC				61
+#define TOP_DOUT_ACLK_GSCL_400				62
+#define TOP_DOUT_ACLK_GSCL_333				63
+#define TOP_DOUT_SCLK_ISP1_SPI0_B			64
+#define TOP_DOUT_SCLK_ISP1_SPI0_A			65
+#define TOP_DOUT_ACLK_ISP1_400				66
+#define TOP_DOUT_ACLK_ISP1_266				67
+#define TOP_DOUT_SCLK_ISP1_UART				68
+#define TOP_DOUT_SCLK_ISP1_SPI1_B			69
+#define TOP_DOUT_SCLK_ISP1_SPI1_A			70
+#define TOP_DOUT_SCLK_ISP1_SENSOR2_B			71
+#define TOP_DOUT_SCLK_ISP1_SENSOR1_B			72
+#define TOP_DOUT_SCLK_ISP1_SENSOR0_B			73
+#define TOP_DOUTTOP__SCLK_HPM_TARGETCLK			74
+#define TOP_DOUT_SCLK_DISP_PIXEL			75
+#define TOP_DOUT_ACLK_DISP_222				76
+#define TOP_DOUT_ACLK_DISP_333				77
+#define TOP_DOUT_ACLK_BUS4_100				78
+#define TOP_DOUT_ACLK_BUS4_400				79
+#define TOP_DOUT_ACLK_BUS3_100				80
+#define TOP_DOUT_ACLK_BUS3_400				81
+#define TOP_DOUT_ACLK_BUS2_100				82
+#define TOP_DOUT_ACLK_BUS2_400				83
+#define TOP_DOUT_ACLK_BUS1_100				84
+#define TOP_DOUT_ACLK_BUS1_400				85
+#define TOP_DOUT_SCLK_PERI_SPI1_B			86
+#define TOP_DOUT_SCLK_PERI_SPI1_A			87
+#define TOP_DOUT_SCLK_PERI_SPI0_B			88
+#define TOP_DOUT_SCLK_PERI_SPI0_A			89
+#define TOP_DOUT_SCLK_PERI_UART0			90
+#define TOP_DOUT_SCLK_PERI_UART2			91
+#define TOP_DOUT_SCLK_PERI_UART1			92
+#define TOP_DOUT_SCLK_PERI_SPI2_B			93
+#define TOP_DOUT_SCLK_PERI_SPI2_A			94
+#define TOP_DOUT_ACLK_PERI_AUD				95
+#define TOP_DOUT_ACLK_PERI_66				96
+#define TOP_DOUT_SCLK_FSYS_MMC0_SDCLKIN_B		97
+#define TOP_DOUT_SCLK_FSYS_MMC0_SDCLKIN_A		98
+#define TOP_DOUT_SCLK_FSYS_USBDRD30_SUSPEND_CLK		99
+#define TOP_DOUT_ACLK_FSYS_200				100
+#define TOP_DOUT_SCLK_FSYS_MMC2_SDCLKIN_B		101
+#define TOP_DOUT_SCLK_FSYS_MMC2_SDCLKIN_A		102
+#define TOP_DOUT_SCLK_FSYS_MMC1_SDCLKIN_B		103
+#define TOP_DOUT_SCLK_FSYS_MMC1_SDCLKIN_A		104
+#define TOP_SCLK_FIMD1					105
+#define TOP_SCLK_MMC2					106
+#define TOP_SCLK_MMC1					107
+#define TOP_SCLK_MMC0					108
+#define PHYCLK_DPTX_PHY_CH3_TXD_CLK			109
+#define PHYCLK_DPTX_PHY_CH2_TXD_CLK			110
+#define PHYCLK_DPTX_PHY_CH1_TXD_CLK			111
+#define PHYCLK_DPTX_PHY_CH0_TXD_CLK			112
+#define phyclk_hdmi_phy_tmds_clko			113
+#define PHYCLK_HDMI_PHY_PIXEL_CLKO			114
+#define PHYCLK_HDMI_LINK_O_TMDS_CLKHI			115
+#define PHYCLK_MIPI_DPHY_4L_M_TXBYTECLKHS		116
+#define PHYCLK_DPTX_PHY_O_REF_CLK_24M			117
+#define PHYCLK_DPTX_PHY_CLK_DIV2			118
+#define PHYCLK_MIPI_DPHY_4L_M_RXCLKESC0			119
+#define PHYCLK_USBHOST20_PHY_PHYCLOCK			120
+#define PHYCLK_USBHOST20_PHY_FREECLK			121
+#define PHYCLK_USBHOST20_PHY_CLK48MOHCI			122
+#define PHYCLK_USBDRD30_UDRD30_PIPE_PCLK		123
+#define PHYCLK_USBDRD30_UDRD30_PHYCLOCK			124
+#define TOP_NR_CLK					125
+
+
+/* List Of Clocks For CMU_EGL */
+
+#define EGL_FOUT_EGL_PLL				1
+#define EGL_FOUT_EGL_DPLL				2
+#define EGL_MOUT_EGL_B					3
+#define EGL_MOUT_EGL_PLL				4
+#define EGL_DOUT_EGL_PLL				5
+#define EGL_DOUT_EGL_PCLK_DBG				6
+#define EGL_DOUT_EGL_ATCLK				7
+#define EGL_DOUT_PCLK_EGL				8
+#define EGL_DOUT_ACLK_EGL				9
+#define EGL_DOUT_EGL2					10
+#define EGL_DOUT_EGL1					11
+#define EGL_NR_CLK					12
+
+
+/* List Of Clocks For CMU_KFC */
+
+#define KFC_FOUT_KFC_PLL				1
+#define KFC_MOUT_KFC_PLL				2
+#define KFC_MOUT_KFC					3
+#define KFC_DOUT_KFC_PLL				4
+#define KFC_DOUT_PCLK_KFC				5
+#define KFC_DOUT_ACLK_KFC				6
+#define KFC_DOUT_KFC_PCLK_DBG				7
+#define KFC_DOUT_KFC_ATCLK				8
+#define KFC_DOUT_KFC2					9
+#define KFC_DOUT_KFC1					10
+#define KFC_NR_CLK					11
+
+
+/* List Of Clocks For CMU_MIF */
+
+#define MIF_FOUT_MEM_PLL				1
+#define MIF_FOUT_MEDIA_PLL				2
+#define MIF_FOUT_BUS_PLL				3
+#define MIF_MOUT_CLK2X_PHY				4
+#define MIF_MOUT_MIF_DREX2X				5
+#define MIF_MOUT_CLKM_PHY				6
+#define MIF_MOUT_MIF_DREX				7
+#define MIF_MOUT_MEDIA_PLL				8
+#define MIF_MOUT_BUS_PLL				9
+#define MIF_MOUT_MEM_PLL				10
+#define MIF_DOUT_ACLK_BUS_100				11
+#define MIF_DOUT_ACLK_BUS_200				12
+#define MIF_DOUT_ACLK_MIF_466				13
+#define MIF_DOUT_CLK2X_PHY				14
+#define MIF_DOUT_CLKM_PHY				15
+#define MIF_DOUT_BUS_PLL				16
+#define MIF_DOUT_MEM_PLL				17
+#define MIF_DOUT_MEDIA_PLL				18
+#define MIF_CLK_LPDDR3PHY_WRAP1				19
+#define MIF_CLK_LPDDR3PHY_WRAP0				20
+#define MIF_CLK_MONOCNT					21
+#define MIF_CLK_MIF_RTC					22
+#define MIF_CLK_DREX1					23
+#define MIF_CLK_DREX0					24
+#define MIF_CLK_INTMEM					25
+#define MIF_SCLK_LPDDR3PHY_WRAP_U1			26
+#define MIF_SCLK_LPDDR3PHY_WRAP_U0			27
+#define MIF_NR_CLK					28
+
+
+/* List Of Clocks For CMU_G3D */
+
+#define G3D_FOUT_G3D_PLL				1
+#define G3D_MOUT_G3D_PLL				2
+#define G3D_DOUT_PCLK_G3D				3
+#define G3D_DOUT_ACLK_G3D				4
+#define G3D_CLK_G3D_HPM					5
+#define G3D_CLK_G3D					6
+#define G3D_NR_CLK					7
+
+
+/* List Of Clocks For CMU_AUD */
+
+#define AUD_MOUT_SCLK_AUD_PCM				1
+#define AUD_MOUT_SCLK_AUD_I2S				2
+#define AUD_MOUT_AUD_PLL_USER				3
+#define AUD_DOUT_ACLK_AUD_131				4
+#define AUD_DOUT_SCLK_AUD_UART				5
+#define AUD_DOUT_SCLK_AUD_PCM				6
+#define AUD_DOUT_SCLK_AUD_I2S				7
+#define AUD_CLK_AUD_UART				8
+#define AUD_CLK_PCM					9
+#define AUD_CLK_I2S					10
+#define AUD_CLK_DMAC					11
+#define AUD_CLK_SRAMC					12
+#define AUD_SCLK_AUD_UART				13
+#define AUD_SCLK_PCM					14
+#define AUD_SCLK_I2S					15
+#define AUD_NR_CLK					16
+
+
+/* List Of Clocks For CMU_MFC */
+
+#define MFC_MOUT_ACLK_MFC_333_USER			1
+#define MFC_DOUT_PCLK_MFC_83				2
+#define MFC_CLK_MFC					3
+#define MFC_CLK_SMMU2_MFCM1				4
+#define MFC_CLK_SMMU2_MFCM0				5
+#define MFC_NR_CLK					6
+
+
+/* List Of Clocks For CMU_GSCL */
+
+#define GSCL_MOUT_ACLK_CSIS				1
+#define GSCL_MOUT_ACLK_GSCL_FIMC_USER			2
+#define GSCL_MOUT_ACLK_M2M_400_USER			3
+#define GSCL_MOUT_ACLK_GSCL_333_USER			4
+#define GSCL_DOUT_ACLK_CSIS_200				5
+#define GSCL_DOUT_PCLK_M2M_100				6
+#define GSCL_CLK_PIXEL_GSCL1				7
+#define GSCL_CLK_PIXEL_GSCL0				8
+#define GSCL_CLK_MSCL1					9
+#define GSCL_CLK_MSCL0					10
+#define GSCL_CLK_GSCL1					11
+#define GSCL_CLK_GSCL0					12
+#define GSCL_CLK_FIMC_LITE_D				13
+#define GSCL_CLK_FIMC_LITE_B				14
+#define GSCL_CLK_FIMC_LITE_A				15
+#define GSCL_CLK_CSIS1					16
+#define GSCL_CLK_CSIS0					17
+#define GSCL_CLK_SMMU3_LITE_D				18
+#define GSCL_CLK_SMMU3_LITE_B				19
+#define GSCL_CLK_SMMU3_LITE_A				20
+#define GSCL_CLK_SMMU3_GSCL0				21
+#define GSCL_CLK_SMMU3_GSCL1				22
+#define GSCL_CLK_SMMU3_MSCL0				23
+#define GSCL_CLK_SMMU3_MSCL1				24
+#define GSCL_SCLK_CSIS1_WRAP				25
+#define GSCL_SCLK_CSIS0_WRAP				26
+#define GSCL_NR_CLK					27
+
+
+/* List Of Clocks For CMU_FSYS */
+
+#define FSYS_MOUT_PHYCLK_USBHOST20_PHYCLK_USER		1
+#define FSYS_MOUT_PHYCLK_USBHOST20_FREECLK_USER		2
+#define FSYS_MOUT_PHYCLK_USBHOST20_CLK48MOHCI_USER	3
+#define FSYS_MOUT_PHYCLK_USBDRD30_PIPE_PCLK_USER	4
+#define FSYS_MOUT_PHYCLK_USBDRD30_PHYCLOCK_USER		5
+#define FSYS_CLK_TSI					6
+#define FSYS_CLK_USBLINK				7
+#define FSYS_CLK_USBHOST20				8
+#define FSYS_CLK_USBDRD30				9
+#define FSYS_CLK_SROMC					10
+#define FSYS_CLK_PDMA					11
+#define FSYS_CLK_MMC2					12
+#define FSYS_CLK_MMC1					13
+#define FSYS_CLK_MMC0					14
+#define FSYS_CLK_RTIC					15
+#define FSYS_CLK_SMMU_RTIC				16
+#define FSYS_PHYCLK_USBDRD30				17
+#define FSYS_PHYCLK_USBHOST20				18
+#define FSYS_NR_CLK					19
+
+
+/* List Of Clocks For CMU_PERI */
+
+#define PERI_MOUT_SCLK_SPDIF				1
+#define PERI_MOUT_SCLK_I2SCOD				2
+#define PERI_MOUT_SCLK_PCM				3
+#define PERI_DOUT_I2S					4
+#define PERI_DOUT_PCM					5
+#define PERI_CLK_WDT_KFC				6
+#define PERI_CLK_WDT_EGL				7
+#define PERI_CLK_HSIC3					8
+#define PERI_CLK_HSIC2					9
+#define PERI_CLK_HSIC1					10
+#define PERI_CLK_HSIC0					11
+#define PERI_CLK_PCM					12
+#define PERI_CLK_MCT					13
+#define PERI_CLK_I2S					14
+#define PERI_CLK_I2CHDMI				15
+#define PERI_CLK_I2C7					16
+#define PERI_CLK_I2C6					17
+#define PERI_CLK_I2C5					18
+#define PERI_CLK_I2C4					19
+#define PERI_CLK_I2C9					20
+#define PERI_CLK_I2C8					21
+#define PERI_CLK_I2C11					22
+#define PERI_CLK_I2C10					23
+#define PERI_CLK_HDMICEC				24
+#define PERI_CLK_EFUSE_WRITER				25
+#define PERI_CLK_ABB					26
+#define PERI_CLK_UART2					27
+#define PERI_CLK_UART1					28
+#define PERI_CLK_UART0					29
+#define PERI_CLK_ADC					30
+#define PERI_CLK_TMU4					31
+#define PERI_CLK_TMU3					32
+#define PERI_CLK_TMU2					33
+#define PERI_CLK_TMU1					34
+#define PERI_CLK_TMU0					35
+#define PERI_CLK_SPI2					36
+#define PERI_CLK_SPI1					37
+#define PERI_CLK_SPI0					38
+#define PERI_CLK_SPDIF					39
+#define PERI_CLK_PWM					40
+#define PERI_CLK_UART4					41
+#define PERI_CLK_CHIPID					42
+#define PERI_CLK_PROVKEY0				43
+#define PERI_CLK_PROVKEY1				44
+#define PERI_CLK_SECKEY					45
+#define PERI_CLK_TOP_RTC				46
+#define PERI_CLK_TZPC10					47
+#define PERI_CLK_TZPC9					48
+#define PERI_CLK_TZPC8					49
+#define PERI_CLK_TZPC7					50
+#define PERI_CLK_TZPC6					51
+#define PERI_CLK_TZPC5					52
+#define PERI_CLK_TZPC4					53
+#define PERI_CLK_TZPC3					54
+#define PERI_CLK_TZPC2					55
+#define PERI_CLK_TZPC1					56
+#define PERI_CLK_TZPC0					57
+#define PERI_SCLK_UART2					58
+#define PERI_SCLK_UART1					59
+#define PERI_SCLK_UART0					60
+#define PERI_SCLK_SPI2					61
+#define PERI_SCLK_SPI1					62
+#define PERI_SCLK_SPI0					63
+#define PERI_SCLK_SPDIF					64
+#define PERI_SCLK_I2S					65
+#define PERI_SCLK_PCM1					66
+#define PERI_NR_CLK					67
+
+
+/* List Of Clocks For CMU_DISP */
+
+#define DISP_MOUT_SCLK_HDMI_SPDIF			1
+#define DISP_MOUT_SCLK_HDMI_PIXEL			2
+#define DISP_MOUT_PHYCLK_MIPI_DPHY_4LMRXCLK_ESC0_USER	3
+#define DISP_MOUT_PHYCLK_HDMI_PHY_TMDS_CLKO_USER	4
+#define DISP_MOUT_PHYCLK_HDMI_PHY_REF_CLKO_USER		5
+#define DISP_MOUT_HDMI_PHY_PIXEL			6
+#define DISP_MOUT_PHYCLK_HDMI_LINK_O_TMDS_CLKHI_USER	7
+#define DISP_MOUT_PHYCLK_MIPI_DPHY_4L_M_TXBYTE_CLKHS	8
+#define DISP_MOUT_PHYCLK_DPTX_PHY_O_REF_CLK_24M_USER	9
+#define DISP_MOUT_PHYCLK_DPTX_PHY_CLK_DIV2_USER		10
+#define DISP_MOUT_PHYCLK_DPTX_PHY_CH3_TXD_CLK_USER	11
+#define DISP_MOUT_PHYCLK_DPTX_PHY_CH2_TXD_CLK_USER	12
+#define DISP_MOUT_PHYCLK_DPTX_PHY_CH1_TXD_CLK_USER	13
+#define DISP_MOUT_PHYCLK_DPTX_PHY_CH0_TXD_CLK_USER	14
+#define DISP_MOUT_ACLK_DISP_222_USER			15
+#define DISP_MOUT_SCLK_DISP_PIXEL_USER			16
+#define DISP_MOUT_ACLK_DISP_333_USER			17
+#define DISP_DOUT_SCLK_HDMI_PHY_PIXEL_CLKI		18
+#define DISP_DOUT_SCLK_FIMD1_EXTCLKPLL			19
+#define DISP_DOUT_PCLK_DISP_111				20
+#define DISP_CLK_SMMU_TV				21
+#define DISP_CLK_SMMU_FIMD1M1				22
+#define DISP_CLK_SMMU_FIMD1M0				23
+#define DISP_CLK_PIXEL_MIXER				24
+#define DISP_CLK_PIXEL_DISP				25
+#define DISP_CLK_MIXER					26
+#define DISP_CLK_MIPIPHY				27
+#define DISP_CLK_HDMIPHY				28
+#define DISP_CLK_HDMI					29
+#define DISP_CLK_FIMD1					30
+#define DISP_CLK_DSIM1					31
+#define DISP_CLK_DPPHY					32
+#define DISP_CLK_DP					33
+#define DISP_SCLK_PIXEL					34
+#define DISP_MOUT_HDMI_PHY_PIXEL_USER			35
+#define DISP_NR_CLK					36
+
+
+/* List Of Clocks For CMU_G2D */
+
+#define G2D_MOUT_ACLK_G2D_333_USER			1
+#define G2D_DOUT_PCLK_G2D_83				2
+#define G2D_CLK_SMMU3_JPEG				3
+#define G2D_CLK_MDMA					4
+#define G2D_CLK_JPEG					5
+#define G2D_CLK_G2D					6
+#define G2D_CLK_SSS					7
+#define G2D_CLK_SLIM_SSS				8
+#define G2D_CLK_SMMU_SLIM_SSS				9
+#define G2D_CLK_SMMU_SSS				10
+#define G2D_CLK_SMMU_MDMA				11
+#define G2D_CLK_SMMU3_G2D				12
+#define G2D_NR_CLK					13
+
+
+/* List Of Clocks For CMU_ISP */
+
+#define ISP_MOUT_ISP_400_USER				1
+#define ISP_MOUT_ISP_266_USER				2
+#define ISP_DOUT_SCLK_MPWM				3
+#define ISP_DOUT_CA5_PCLKDBG				4
+#define ISP_DOUT_CA5_ATCLKIN				5
+#define ISP_DOUT_PCLK_ISP_133				6
+#define ISP_DOUT_PCLK_ISP_66				7
+#define ISP_CLK_GIC					8
+#define ISP_CLK_WDT					9
+#define ISP_CLK_UART					10
+#define ISP_CLK_SPI1					11
+#define ISP_CLK_SPI0					12
+#define ISP_CLK_SMMU_SCALERP				13
+#define ISP_CLK_SMMU_SCALERC				14
+#define ISP_CLK_SMMU_ISPCX				15
+#define ISP_CLK_SMMU_ISP				16
+#define ISP_CLK_SMMU_FD					17
+#define ISP_CLK_SMMU_DRC				18
+#define ISP_CLK_PWM					19
+#define ISP_CLK_MTCADC					20
+#define ISP_CLK_MPWM					21
+#define ISP_CLK_MCUCTL					22
+#define ISP_CLK_I2C1					23
+#define ISP_CLK_I2C0					24
+#define ISP_CLK_FIMC_SCALERP				25
+#define ISP_CLK_FIMC_SCALERC				26
+#define ISP_CLK_FIMC					27
+#define ISP_CLK_FIMC_FD					28
+#define ISP_CLK_FIMC_DRC				29
+#define ISP_CLK_CA5					30
+#define ISP_SCLK_SPI0_EXT				31
+#define ISP_SCLK_SPI1_EXT				32
+#define ISP_SCLK_UART_EXT				33
+#define ISP_NR_CLK					34
+
+#endif
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/exynos5410.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/exynos5410.h
new file mode 100644
index 0000000000000000000000000000000000000000..6cb4e90f81fc33628d23f353cbbd6cba00815945
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/exynos5410.h
@@ -0,0 +1,68 @@
+/*
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * Copyright (c) 2016 Krzysztof Kozlowski
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Device Tree binding constants for Exynos5421 clock controller.
+*/
+
+#ifndef _DT_BINDINGS_CLOCK_EXYNOS_5410_H
+#define _DT_BINDINGS_CLOCK_EXYNOS_5410_H
+
+/* core clocks */
+#define CLK_FIN_PLL		1
+#define CLK_FOUT_APLL		2
+#define CLK_FOUT_CPLL		3
+#define CLK_FOUT_MPLL		4
+#define CLK_FOUT_BPLL		5
+#define CLK_FOUT_KPLL		6
+#define CLK_FOUT_EPLL		7
+
+/* gate for special clocks (sclk) */
+#define CLK_SCLK_UART0		128
+#define CLK_SCLK_UART1		129
+#define CLK_SCLK_UART2		130
+#define CLK_SCLK_UART3		131
+#define CLK_SCLK_MMC0		132
+#define CLK_SCLK_MMC1		133
+#define CLK_SCLK_MMC2		134
+#define CLK_SCLK_USBD300	150
+#define CLK_SCLK_USBD301	151
+#define CLK_SCLK_USBPHY300	152
+#define CLK_SCLK_USBPHY301	153
+#define CLK_SCLK_PWM		155
+
+/* gate clocks */
+#define CLK_UART0		257
+#define CLK_UART1		258
+#define CLK_UART2		259
+#define CLK_I2C0		261
+#define CLK_I2C1		262
+#define CLK_I2C2		263
+#define CLK_I2C3		264
+#define CLK_USI0		265
+#define CLK_USI1		266
+#define CLK_USI2		267
+#define CLK_USI3		268
+#define CLK_UART3		260
+#define CLK_PWM			279
+#define CLK_MCT			315
+#define CLK_WDT			316
+#define CLK_RTC			317
+#define CLK_TMU			318
+#define CLK_MMC0		351
+#define CLK_MMC1		352
+#define CLK_MMC2		353
+#define CLK_PDMA0		362
+#define CLK_PDMA1		363
+#define CLK_USBH20		365
+#define CLK_USBD300		366
+#define CLK_USBD301		367
+#define CLK_SSS			471
+
+#define CLK_NR_CLKS		512
+
+#endif /* _DT_BINDINGS_CLOCK_EXYNOS_5410_H */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/exynos5420.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/exynos5420.h
new file mode 100644
index 0000000000000000000000000000000000000000..2740ae0424a97836cc3212f773fea13f4e91a53d
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/exynos5420.h
@@ -0,0 +1,258 @@
+/*
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * Author: Andrzej Hajda <a.hajda@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Device Tree binding constants for Exynos5420 clock controller.
+*/
+
+#ifndef _DT_BINDINGS_CLOCK_EXYNOS_5420_H
+#define _DT_BINDINGS_CLOCK_EXYNOS_5420_H
+
+/* core clocks */
+#define CLK_FIN_PLL		1
+#define CLK_FOUT_APLL		2
+#define CLK_FOUT_CPLL		3
+#define CLK_FOUT_DPLL		4
+#define CLK_FOUT_EPLL		5
+#define CLK_FOUT_RPLL		6
+#define CLK_FOUT_IPLL		7
+#define CLK_FOUT_SPLL		8
+#define CLK_FOUT_VPLL		9
+#define CLK_FOUT_MPLL		10
+#define CLK_FOUT_BPLL		11
+#define CLK_FOUT_KPLL		12
+#define CLK_ARM_CLK		13
+#define CLK_KFC_CLK		14
+
+/* gate for special clocks (sclk) */
+#define CLK_SCLK_UART0		128
+#define CLK_SCLK_UART1		129
+#define CLK_SCLK_UART2		130
+#define CLK_SCLK_UART3		131
+#define CLK_SCLK_MMC0		132
+#define CLK_SCLK_MMC1		133
+#define CLK_SCLK_MMC2		134
+#define CLK_SCLK_SPI0		135
+#define CLK_SCLK_SPI1		136
+#define CLK_SCLK_SPI2		137
+#define CLK_SCLK_I2S1		138
+#define CLK_SCLK_I2S2		139
+#define CLK_SCLK_PCM1		140
+#define CLK_SCLK_PCM2		141
+#define CLK_SCLK_SPDIF		142
+#define CLK_SCLK_HDMI		143
+#define CLK_SCLK_PIXEL		144
+#define CLK_SCLK_DP1		145
+#define CLK_SCLK_MIPI1		146
+#define CLK_SCLK_FIMD1		147
+#define CLK_SCLK_MAUDIO0	148
+#define CLK_SCLK_MAUPCM0	149
+#define CLK_SCLK_USBD300	150
+#define CLK_SCLK_USBD301	151
+#define CLK_SCLK_USBPHY300	152
+#define CLK_SCLK_USBPHY301	153
+#define CLK_SCLK_UNIPRO		154
+#define CLK_SCLK_PWM		155
+#define CLK_SCLK_GSCL_WA	156
+#define CLK_SCLK_GSCL_WB	157
+#define CLK_SCLK_HDMIPHY	158
+#define CLK_MAU_EPLL		159
+#define CLK_SCLK_HSIC_12M	160
+#define CLK_SCLK_MPHY_IXTAL24	161
+
+/* gate clocks */
+#define CLK_UART0		257
+#define CLK_UART1		258
+#define CLK_UART2		259
+#define CLK_UART3		260
+#define CLK_I2C0		261
+#define CLK_I2C1		262
+#define CLK_I2C2		263
+#define CLK_I2C3		264
+#define CLK_USI0		265
+#define CLK_USI1		266
+#define CLK_USI2		267
+#define CLK_USI3		268
+#define CLK_I2C_HDMI		269
+#define CLK_TSADC		270
+#define CLK_SPI0		271
+#define CLK_SPI1		272
+#define CLK_SPI2		273
+#define CLK_KEYIF		274
+#define CLK_I2S1		275
+#define CLK_I2S2		276
+#define CLK_PCM1		277
+#define CLK_PCM2		278
+#define CLK_PWM			279
+#define CLK_SPDIF		280
+#define CLK_USI4		281
+#define CLK_USI5		282
+#define CLK_USI6		283
+#define CLK_ACLK66_PSGEN	300
+#define CLK_CHIPID		301
+#define CLK_SYSREG		302
+#define CLK_TZPC0		303
+#define CLK_TZPC1		304
+#define CLK_TZPC2		305
+#define CLK_TZPC3		306
+#define CLK_TZPC4		307
+#define CLK_TZPC5		308
+#define CLK_TZPC6		309
+#define CLK_TZPC7		310
+#define CLK_TZPC8		311
+#define CLK_TZPC9		312
+#define CLK_HDMI_CEC		313
+#define CLK_SECKEY		314
+#define CLK_MCT			315
+#define CLK_WDT			316
+#define CLK_RTC			317
+#define CLK_TMU			318
+#define CLK_TMU_GPU		319
+#define CLK_PCLK66_GPIO		330
+#define CLK_ACLK200_FSYS2	350
+#define CLK_MMC0		351
+#define CLK_MMC1		352
+#define CLK_MMC2		353
+#define CLK_SROMC		354
+#define CLK_UFS			355
+#define CLK_ACLK200_FSYS	360
+#define CLK_TSI			361
+#define CLK_PDMA0		362
+#define CLK_PDMA1		363
+#define CLK_RTIC		364
+#define CLK_USBH20		365
+#define CLK_USBD300		366
+#define CLK_USBD301		367
+#define CLK_ACLK400_MSCL	380
+#define CLK_MSCL0		381
+#define CLK_MSCL1		382
+#define CLK_MSCL2		383
+#define CLK_SMMU_MSCL0		384
+#define CLK_SMMU_MSCL1		385
+#define CLK_SMMU_MSCL2		386
+#define CLK_ACLK333		400
+#define CLK_MFC			401
+#define CLK_SMMU_MFCL		402
+#define CLK_SMMU_MFCR		403
+#define CLK_ACLK200_DISP1	410
+#define CLK_DSIM1		411
+#define CLK_DP1			412
+#define CLK_HDMI		413
+#define CLK_ACLK300_DISP1	420
+#define CLK_FIMD1		421
+#define CLK_SMMU_FIMD1M0	422
+#define CLK_SMMU_FIMD1M1	423
+#define CLK_ACLK166		430
+#define CLK_MIXER		431
+#define CLK_ACLK266		440
+#define CLK_ROTATOR		441
+#define CLK_MDMA1		442
+#define CLK_SMMU_ROTATOR	443
+#define CLK_SMMU_MDMA1		444
+#define CLK_ACLK300_JPEG	450
+#define CLK_JPEG		451
+#define CLK_JPEG2		452
+#define CLK_SMMU_JPEG		453
+#define CLK_SMMU_JPEG2		454
+#define CLK_ACLK300_GSCL	460
+#define CLK_SMMU_GSCL0		461
+#define CLK_SMMU_GSCL1		462
+#define CLK_GSCL_WA		463
+#define CLK_GSCL_WB		464
+#define CLK_GSCL0		465
+#define CLK_GSCL1		466
+#define CLK_FIMC_3AA		467
+#define CLK_ACLK266_G2D		470
+#define CLK_SSS			471
+#define CLK_SLIM_SSS		472
+#define CLK_MDMA0		473
+#define CLK_ACLK333_G2D		480
+#define CLK_G2D			481
+#define CLK_ACLK333_432_GSCL	490
+#define CLK_SMMU_3AA		491
+#define CLK_SMMU_FIMCL0		492
+#define CLK_SMMU_FIMCL1		493
+#define CLK_SMMU_FIMCL3		494
+#define CLK_FIMC_LITE3		495
+#define CLK_FIMC_LITE0		496
+#define CLK_FIMC_LITE1		497
+#define CLK_ACLK_G3D		500
+#define CLK_G3D			501
+#define CLK_SMMU_MIXER		502
+#define CLK_SMMU_G2D		503
+#define CLK_SMMU_MDMA0		504
+#define CLK_MC			505
+#define CLK_TOP_RTC		506
+#define CLK_SCLK_UART_ISP	510
+#define CLK_SCLK_SPI0_ISP	511
+#define CLK_SCLK_SPI1_ISP	512
+#define CLK_SCLK_PWM_ISP	513
+#define CLK_SCLK_ISP_SENSOR0	514
+#define CLK_SCLK_ISP_SENSOR1	515
+#define CLK_SCLK_ISP_SENSOR2	516
+#define CLK_ACLK432_SCALER	517
+#define CLK_ACLK432_CAM		518
+#define CLK_ACLK_FL1550_CAM	519
+#define CLK_ACLK550_CAM		520
+
+/* mux clocks */
+#define CLK_MOUT_HDMI		640
+#define CLK_MOUT_G3D		641
+#define CLK_MOUT_VPLL		642
+#define CLK_MOUT_MAUDIO0	643
+#define CLK_MOUT_USER_ACLK333	644
+#define CLK_MOUT_SW_ACLK333	645
+#define CLK_MOUT_USER_ACLK200_DISP1	646
+#define CLK_MOUT_SW_ACLK200	647
+#define CLK_MOUT_USER_ACLK300_DISP1     648
+#define CLK_MOUT_SW_ACLK300     649
+#define CLK_MOUT_USER_ACLK400_DISP1     650
+#define CLK_MOUT_SW_ACLK400     651
+#define CLK_MOUT_USER_ACLK300_GSCL	652
+#define CLK_MOUT_SW_ACLK300_GSCL	653
+#define CLK_MOUT_MCLK_CDREX	654
+#define CLK_MOUT_BPLL		655
+#define CLK_MOUT_MX_MSPLL_CCORE	656
+#define CLK_MOUT_EPLL		657
+#define CLK_MOUT_MAU_EPLL	658
+#define CLK_MOUT_USER_MAU_EPLL	659
+
+/* divider clocks */
+#define CLK_DOUT_PIXEL		768
+#define CLK_DOUT_ACLK400_WCORE	769
+#define CLK_DOUT_ACLK400_ISP	770
+#define CLK_DOUT_ACLK400_MSCL	771
+#define CLK_DOUT_ACLK200	772
+#define CLK_DOUT_ACLK200_FSYS2	773
+#define CLK_DOUT_ACLK100_NOC	774
+#define CLK_DOUT_PCLK200_FSYS	775
+#define CLK_DOUT_ACLK200_FSYS	776
+#define CLK_DOUT_ACLK333_432_GSCL	777
+#define CLK_DOUT_ACLK333_432_ISP	778
+#define CLK_DOUT_ACLK66		779
+#define CLK_DOUT_ACLK333_432_ISP0	780
+#define CLK_DOUT_ACLK266	781
+#define CLK_DOUT_ACLK166	782
+#define CLK_DOUT_ACLK333	783
+#define CLK_DOUT_ACLK333_G2D	784
+#define CLK_DOUT_ACLK266_G2D	785
+#define CLK_DOUT_ACLK_G3D	786
+#define CLK_DOUT_ACLK300_JPEG	787
+#define CLK_DOUT_ACLK300_DISP1	788
+#define CLK_DOUT_ACLK300_GSCL	789
+#define CLK_DOUT_ACLK400_DISP1	790
+#define CLK_DOUT_PCLK_CDREX	791
+#define CLK_DOUT_SCLK_CDREX	792
+#define CLK_DOUT_ACLK_CDREX1	793
+#define CLK_DOUT_CCLK_DREX0	794
+#define CLK_DOUT_CLK2X_PHY0	795
+#define CLK_DOUT_PCLK_CORE_MEM	796
+
+/* must be greater than maximal clock id */
+#define CLK_NR_CLKS		797
+
+#endif /* _DT_BINDINGS_CLOCK_EXYNOS_5420_H */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/exynos5433.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/exynos5433.h
new file mode 100644
index 0000000000000000000000000000000000000000..be39d23e6a32ecf3e4fa24343ea518352db75f8e
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/exynos5433.h
@@ -0,0 +1,1412 @@
+/*
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * Author: Chanwoo Choi <cw00.choi@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_EXYNOS5433_H
+#define _DT_BINDINGS_CLOCK_EXYNOS5433_H
+
+/* CMU_TOP */
+#define CLK_FOUT_ISP_PLL		1
+#define CLK_FOUT_AUD_PLL		2
+
+#define CLK_MOUT_AUD_PLL		10
+#define CLK_MOUT_ISP_PLL		11
+#define CLK_MOUT_AUD_PLL_USER_T		12
+#define CLK_MOUT_MPHY_PLL_USER		13
+#define CLK_MOUT_MFC_PLL_USER		14
+#define CLK_MOUT_BUS_PLL_USER		15
+#define CLK_MOUT_ACLK_HEVC_400		16
+#define CLK_MOUT_ACLK_CAM1_333		17
+#define CLK_MOUT_ACLK_CAM1_552_B	18
+#define CLK_MOUT_ACLK_CAM1_552_A	19
+#define CLK_MOUT_ACLK_ISP_DIS_400	20
+#define CLK_MOUT_ACLK_ISP_400		21
+#define CLK_MOUT_ACLK_BUS0_400		22
+#define CLK_MOUT_ACLK_MSCL_400_B	23
+#define CLK_MOUT_ACLK_MSCL_400_A	24
+#define CLK_MOUT_ACLK_GSCL_333		25
+#define CLK_MOUT_ACLK_G2D_400_B		26
+#define CLK_MOUT_ACLK_G2D_400_A		27
+#define CLK_MOUT_SCLK_JPEG_C		28
+#define CLK_MOUT_SCLK_JPEG_B		29
+#define CLK_MOUT_SCLK_JPEG_A		30
+#define CLK_MOUT_SCLK_MMC2_B		31
+#define CLK_MOUT_SCLK_MMC2_A		32
+#define CLK_MOUT_SCLK_MMC1_B		33
+#define CLK_MOUT_SCLK_MMC1_A		34
+#define CLK_MOUT_SCLK_MMC0_D		35
+#define CLK_MOUT_SCLK_MMC0_C		36
+#define CLK_MOUT_SCLK_MMC0_B		37
+#define CLK_MOUT_SCLK_MMC0_A		38
+#define CLK_MOUT_SCLK_SPI4		39
+#define CLK_MOUT_SCLK_SPI3		40
+#define CLK_MOUT_SCLK_UART2		41
+#define CLK_MOUT_SCLK_UART1		42
+#define CLK_MOUT_SCLK_UART0		43
+#define CLK_MOUT_SCLK_SPI2		44
+#define CLK_MOUT_SCLK_SPI1		45
+#define CLK_MOUT_SCLK_SPI0		46
+#define CLK_MOUT_ACLK_MFC_400_C		47
+#define CLK_MOUT_ACLK_MFC_400_B		48
+#define CLK_MOUT_ACLK_MFC_400_A		49
+#define CLK_MOUT_SCLK_ISP_SENSOR2	50
+#define CLK_MOUT_SCLK_ISP_SENSOR1	51
+#define CLK_MOUT_SCLK_ISP_SENSOR0	52
+#define CLK_MOUT_SCLK_ISP_UART		53
+#define CLK_MOUT_SCLK_ISP_SPI1		54
+#define CLK_MOUT_SCLK_ISP_SPI0		55
+#define CLK_MOUT_SCLK_PCIE_100		56
+#define CLK_MOUT_SCLK_UFSUNIPRO		57
+#define CLK_MOUT_SCLK_USBHOST30		58
+#define CLK_MOUT_SCLK_USBDRD30		59
+#define CLK_MOUT_SCLK_SLIMBUS		60
+#define CLK_MOUT_SCLK_SPDIF		61
+#define CLK_MOUT_SCLK_AUDIO1		62
+#define CLK_MOUT_SCLK_AUDIO0		63
+#define CLK_MOUT_SCLK_HDMI_SPDIF	64
+
+#define CLK_DIV_ACLK_FSYS_200		100
+#define CLK_DIV_ACLK_IMEM_SSSX_266	101
+#define CLK_DIV_ACLK_IMEM_200		102
+#define CLK_DIV_ACLK_IMEM_266		103
+#define CLK_DIV_ACLK_PERIC_66_B		104
+#define CLK_DIV_ACLK_PERIC_66_A		105
+#define CLK_DIV_ACLK_PERIS_66_B		106
+#define CLK_DIV_ACLK_PERIS_66_A		107
+#define CLK_DIV_SCLK_MMC1_B		108
+#define CLK_DIV_SCLK_MMC1_A		109
+#define CLK_DIV_SCLK_MMC0_B		110
+#define CLK_DIV_SCLK_MMC0_A		111
+#define CLK_DIV_SCLK_MMC2_B		112
+#define CLK_DIV_SCLK_MMC2_A		113
+#define CLK_DIV_SCLK_SPI1_B		114
+#define CLK_DIV_SCLK_SPI1_A		115
+#define CLK_DIV_SCLK_SPI0_B		116
+#define CLK_DIV_SCLK_SPI0_A		117
+#define CLK_DIV_SCLK_SPI2_B		118
+#define CLK_DIV_SCLK_SPI2_A		119
+#define CLK_DIV_SCLK_UART2		120
+#define CLK_DIV_SCLK_UART1		121
+#define CLK_DIV_SCLK_UART0		122
+#define CLK_DIV_SCLK_SPI4_B		123
+#define CLK_DIV_SCLK_SPI4_A		124
+#define CLK_DIV_SCLK_SPI3_B		125
+#define CLK_DIV_SCLK_SPI3_A		126
+#define CLK_DIV_SCLK_I2S1		127
+#define CLK_DIV_SCLK_PCM1		128
+#define CLK_DIV_SCLK_AUDIO1		129
+#define CLK_DIV_SCLK_AUDIO0		130
+#define CLK_DIV_ACLK_GSCL_111		131
+#define CLK_DIV_ACLK_GSCL_333		132
+#define CLK_DIV_ACLK_HEVC_400		133
+#define CLK_DIV_ACLK_MFC_400		134
+#define CLK_DIV_ACLK_G2D_266		135
+#define CLK_DIV_ACLK_G2D_400		136
+#define CLK_DIV_ACLK_G3D_400		137
+#define CLK_DIV_ACLK_BUS0_400		138
+#define CLK_DIV_ACLK_BUS1_400		139
+#define CLK_DIV_SCLK_PCIE_100		140
+#define CLK_DIV_SCLK_USBHOST30		141
+#define CLK_DIV_SCLK_UFSUNIPRO		142
+#define CLK_DIV_SCLK_USBDRD30		143
+#define CLK_DIV_SCLK_JPEG		144
+#define CLK_DIV_ACLK_MSCL_400		145
+#define CLK_DIV_ACLK_ISP_DIS_400	146
+#define CLK_DIV_ACLK_ISP_400		147
+#define CLK_DIV_ACLK_CAM0_333		148
+#define CLK_DIV_ACLK_CAM0_400		149
+#define CLK_DIV_ACLK_CAM0_552		150
+#define CLK_DIV_ACLK_CAM1_333		151
+#define CLK_DIV_ACLK_CAM1_400		152
+#define CLK_DIV_ACLK_CAM1_552		153
+#define CLK_DIV_SCLK_ISP_UART		154
+#define CLK_DIV_SCLK_ISP_SPI1_B		155
+#define CLK_DIV_SCLK_ISP_SPI1_A		156
+#define CLK_DIV_SCLK_ISP_SPI0_B		157
+#define CLK_DIV_SCLK_ISP_SPI0_A		158
+#define CLK_DIV_SCLK_ISP_SENSOR2_B	159
+#define CLK_DIV_SCLK_ISP_SENSOR2_A	160
+#define CLK_DIV_SCLK_ISP_SENSOR1_B	161
+#define CLK_DIV_SCLK_ISP_SENSOR1_A	162
+#define CLK_DIV_SCLK_ISP_SENSOR0_B	163
+#define CLK_DIV_SCLK_ISP_SENSOR0_A	164
+
+#define CLK_ACLK_PERIC_66		200
+#define CLK_ACLK_PERIS_66		201
+#define CLK_ACLK_FSYS_200		202
+#define CLK_SCLK_MMC2_FSYS		203
+#define CLK_SCLK_MMC1_FSYS		204
+#define CLK_SCLK_MMC0_FSYS		205
+#define CLK_SCLK_SPI4_PERIC		206
+#define CLK_SCLK_SPI3_PERIC		207
+#define CLK_SCLK_UART2_PERIC		208
+#define CLK_SCLK_UART1_PERIC		209
+#define CLK_SCLK_UART0_PERIC		210
+#define CLK_SCLK_SPI2_PERIC		211
+#define CLK_SCLK_SPI1_PERIC		212
+#define CLK_SCLK_SPI0_PERIC		213
+#define CLK_SCLK_SPDIF_PERIC		214
+#define CLK_SCLK_I2S1_PERIC		215
+#define CLK_SCLK_PCM1_PERIC		216
+#define CLK_SCLK_SLIMBUS		217
+#define CLK_SCLK_AUDIO1			218
+#define CLK_SCLK_AUDIO0			219
+#define CLK_ACLK_G2D_266		220
+#define CLK_ACLK_G2D_400		221
+#define CLK_ACLK_G3D_400		222
+#define CLK_ACLK_IMEM_SSX_266		223
+#define CLK_ACLK_BUS0_400		224
+#define CLK_ACLK_BUS1_400		225
+#define CLK_ACLK_IMEM_200		226
+#define CLK_ACLK_IMEM_266		227
+#define CLK_SCLK_PCIE_100_FSYS		228
+#define CLK_SCLK_UFSUNIPRO_FSYS		229
+#define CLK_SCLK_USBHOST30_FSYS		230
+#define CLK_SCLK_USBDRD30_FSYS		231
+#define CLK_ACLK_GSCL_111		232
+#define CLK_ACLK_GSCL_333		233
+#define CLK_SCLK_JPEG_MSCL		234
+#define CLK_ACLK_MSCL_400		235
+#define CLK_ACLK_MFC_400		236
+#define CLK_ACLK_HEVC_400		237
+#define CLK_ACLK_ISP_DIS_400		238
+#define CLK_ACLK_ISP_400		239
+#define CLK_ACLK_CAM0_333		240
+#define CLK_ACLK_CAM0_400		241
+#define CLK_ACLK_CAM0_552		242
+#define CLK_ACLK_CAM1_333		243
+#define CLK_ACLK_CAM1_400		244
+#define CLK_ACLK_CAM1_552		245
+#define CLK_SCLK_ISP_SENSOR2		246
+#define CLK_SCLK_ISP_SENSOR1		247
+#define CLK_SCLK_ISP_SENSOR0		248
+#define CLK_SCLK_ISP_MCTADC_CAM1	249
+#define CLK_SCLK_ISP_UART_CAM1		250
+#define CLK_SCLK_ISP_SPI1_CAM1		251
+#define CLK_SCLK_ISP_SPI0_CAM1		252
+#define CLK_SCLK_HDMI_SPDIF_DISP	253
+
+#define TOP_NR_CLK			254
+
+/* CMU_CPIF */
+#define CLK_FOUT_MPHY_PLL		1
+
+#define CLK_MOUT_MPHY_PLL		2
+
+#define CLK_DIV_SCLK_MPHY		10
+
+#define CLK_SCLK_MPHY_PLL		11
+#define CLK_SCLK_UFS_MPHY		11
+
+#define CPIF_NR_CLK			12
+
+/* CMU_MIF */
+#define CLK_FOUT_MEM0_PLL		1
+#define CLK_FOUT_MEM1_PLL		2
+#define CLK_FOUT_BUS_PLL		3
+#define CLK_FOUT_MFC_PLL		4
+#define CLK_DOUT_MFC_PLL		5
+#define CLK_DOUT_BUS_PLL		6
+#define CLK_DOUT_MEM1_PLL		7
+#define CLK_DOUT_MEM0_PLL		8
+
+#define CLK_MOUT_MFC_PLL_DIV2		10
+#define CLK_MOUT_BUS_PLL_DIV2		11
+#define CLK_MOUT_MEM1_PLL_DIV2		12
+#define CLK_MOUT_MEM0_PLL_DIV2		13
+#define CLK_MOUT_MFC_PLL		14
+#define CLK_MOUT_BUS_PLL		15
+#define CLK_MOUT_MEM1_PLL		16
+#define CLK_MOUT_MEM0_PLL		17
+#define CLK_MOUT_CLK2X_PHY_C		18
+#define CLK_MOUT_CLK2X_PHY_B		19
+#define CLK_MOUT_CLK2X_PHY_A		20
+#define CLK_MOUT_CLKM_PHY_C		21
+#define CLK_MOUT_CLKM_PHY_B		22
+#define CLK_MOUT_CLKM_PHY_A		23
+#define CLK_MOUT_ACLK_MIFNM_200		24
+#define CLK_MOUT_ACLK_MIFNM_400		25
+#define CLK_MOUT_ACLK_DISP_333_B	26
+#define CLK_MOUT_ACLK_DISP_333_A	27
+#define CLK_MOUT_SCLK_DECON_VCLK_C	28
+#define CLK_MOUT_SCLK_DECON_VCLK_B	29
+#define CLK_MOUT_SCLK_DECON_VCLK_A	30
+#define CLK_MOUT_SCLK_DECON_ECLK_C	31
+#define CLK_MOUT_SCLK_DECON_ECLK_B	32
+#define CLK_MOUT_SCLK_DECON_ECLK_A	33
+#define CLK_MOUT_SCLK_DECON_TV_ECLK_C	34
+#define CLK_MOUT_SCLK_DECON_TV_ECLK_B	35
+#define CLK_MOUT_SCLK_DECON_TV_ECLK_A	36
+#define CLK_MOUT_SCLK_DSD_C		37
+#define CLK_MOUT_SCLK_DSD_B		38
+#define CLK_MOUT_SCLK_DSD_A		39
+#define CLK_MOUT_SCLK_DSIM0_C		40
+#define CLK_MOUT_SCLK_DSIM0_B		41
+#define CLK_MOUT_SCLK_DSIM0_A		42
+#define CLK_MOUT_SCLK_DECON_TV_VCLK_C	46
+#define CLK_MOUT_SCLK_DECON_TV_VCLK_B	47
+#define CLK_MOUT_SCLK_DECON_TV_VCLK_A	48
+#define CLK_MOUT_SCLK_DSIM1_C		49
+#define CLK_MOUT_SCLK_DSIM1_B		50
+#define CLK_MOUT_SCLK_DSIM1_A		51
+
+#define CLK_DIV_SCLK_HPM_MIF		55
+#define CLK_DIV_ACLK_DREX1		56
+#define CLK_DIV_ACLK_DREX0		57
+#define CLK_DIV_CLK2XPHY		58
+#define CLK_DIV_ACLK_MIF_266		59
+#define CLK_DIV_ACLK_MIFND_133		60
+#define CLK_DIV_ACLK_MIF_133		61
+#define CLK_DIV_ACLK_MIFNM_200		62
+#define CLK_DIV_ACLK_MIF_200		63
+#define CLK_DIV_ACLK_MIF_400		64
+#define CLK_DIV_ACLK_BUS2_400		65
+#define CLK_DIV_ACLK_DISP_333		66
+#define CLK_DIV_ACLK_CPIF_200		67
+#define CLK_DIV_SCLK_DSIM1		68
+#define CLK_DIV_SCLK_DECON_TV_VCLK	69
+#define CLK_DIV_SCLK_DSIM0		70
+#define CLK_DIV_SCLK_DSD		71
+#define CLK_DIV_SCLK_DECON_TV_ECLK	72
+#define CLK_DIV_SCLK_DECON_VCLK		73
+#define CLK_DIV_SCLK_DECON_ECLK		74
+#define CLK_DIV_MIF_PRE			75
+
+#define CLK_CLK2X_PHY1			80
+#define CLK_CLK2X_PHY0			81
+#define CLK_CLKM_PHY1			82
+#define CLK_CLKM_PHY0			83
+#define CLK_RCLK_DREX1			84
+#define CLK_RCLK_DREX0			85
+#define CLK_ACLK_DREX1_TZ		86
+#define CLK_ACLK_DREX0_TZ		87
+#define CLK_ACLK_DREX1_PEREV		88
+#define CLK_ACLK_DREX0_PEREV		89
+#define CLK_ACLK_DREX1_MEMIF		90
+#define CLK_ACLK_DREX0_MEMIF		91
+#define CLK_ACLK_DREX1_SCH		92
+#define CLK_ACLK_DREX0_SCH		93
+#define CLK_ACLK_DREX1_BUSIF		94
+#define CLK_ACLK_DREX0_BUSIF		95
+#define CLK_ACLK_DREX1_BUSIF_RD		96
+#define CLK_ACLK_DREX0_BUSIF_RD		97
+#define CLK_ACLK_DREX1			98
+#define CLK_ACLK_DREX0			99
+#define CLK_ACLK_ASYNCAXIM_ATLAS_CCIX	100
+#define CLK_ACLK_ASYNCAXIS_ATLAS_MIF	101
+#define CLK_ACLK_ASYNCAXIM_ATLAS_MIF	102
+#define CLK_ACLK_ASYNCAXIS_MIF_IMEM	103
+#define CLK_ACLK_ASYNCAXIS_NOC_P_CCI	104
+#define CLK_ACLK_ASYNCAXIM_NOC_P_CCI	105
+#define CLK_ACLK_ASYNCAXIS_CP1		106
+#define CLK_ACLK_ASYNCAXIM_CP1		107
+#define CLK_ACLK_ASYNCAXIS_CP0		108
+#define CLK_ACLK_ASYNCAXIM_CP0		109
+#define CLK_ACLK_ASYNCAXIS_DREX1_3	110
+#define CLK_ACLK_ASYNCAXIM_DREX1_3	111
+#define CLK_ACLK_ASYNCAXIS_DREX1_1	112
+#define CLK_ACLK_ASYNCAXIM_DREX1_1	113
+#define CLK_ACLK_ASYNCAXIS_DREX1_0	114
+#define CLK_ACLK_ASYNCAXIM_DREX1_0	115
+#define CLK_ACLK_ASYNCAXIS_DREX0_3	116
+#define CLK_ACLK_ASYNCAXIM_DREX0_3	117
+#define CLK_ACLK_ASYNCAXIS_DREX0_1	118
+#define CLK_ACLK_ASYNCAXIM_DREX0_1	119
+#define CLK_ACLK_ASYNCAXIS_DREX0_0	120
+#define CLK_ACLK_ASYNCAXIM_DREX0_0	121
+#define CLK_ACLK_AHB2APB_MIF2P		122
+#define CLK_ACLK_AHB2APB_MIF1P		123
+#define CLK_ACLK_AHB2APB_MIF0P		124
+#define CLK_ACLK_IXIU_CCI		125
+#define CLK_ACLK_XIU_MIFSFRX		126
+#define CLK_ACLK_MIFNP_133		127
+#define CLK_ACLK_MIFNM_200		128
+#define CLK_ACLK_MIFND_133		129
+#define CLK_ACLK_MIFND_400		130
+#define CLK_ACLK_CCI			131
+#define CLK_ACLK_MIFND_266		132
+#define CLK_ACLK_PPMU_DREX1S3		133
+#define CLK_ACLK_PPMU_DREX1S1		134
+#define CLK_ACLK_PPMU_DREX1S0		135
+#define CLK_ACLK_PPMU_DREX0S3		136
+#define CLK_ACLK_PPMU_DREX0S1		137
+#define CLK_ACLK_PPMU_DREX0S0		138
+#define CLK_ACLK_BTS_APOLLO		139
+#define CLK_ACLK_BTS_ATLAS		140
+#define CLK_ACLK_ACE_SEL_APOLL		141
+#define CLK_ACLK_ACE_SEL_ATLAS		142
+#define CLK_ACLK_AXIDS_CCI_MIFSFRX	143
+#define CLK_ACLK_AXIUS_ATLAS_CCI	144
+#define CLK_ACLK_AXISYNCDNS_CCI		145
+#define CLK_ACLK_AXISYNCDN_CCI		146
+#define CLK_ACLK_AXISYNCDN_NOC_D	147
+#define CLK_ACLK_ASYNCACEM_APOLLO_CCI	148
+#define CLK_ACLK_ASYNCACEM_ATLAS_CCI	149
+#define CLK_ACLK_ASYNCAPBS_MIF_CSSYS	150
+#define CLK_ACLK_BUS2_400		151
+#define CLK_ACLK_DISP_333		152
+#define CLK_ACLK_CPIF_200		153
+#define CLK_PCLK_PPMU_DREX1S3		154
+#define CLK_PCLK_PPMU_DREX1S1		155
+#define CLK_PCLK_PPMU_DREX1S0		156
+#define CLK_PCLK_PPMU_DREX0S3		157
+#define CLK_PCLK_PPMU_DREX0S1		158
+#define CLK_PCLK_PPMU_DREX0S0		159
+#define CLK_PCLK_BTS_APOLLO		160
+#define CLK_PCLK_BTS_ATLAS		161
+#define CLK_PCLK_ASYNCAXI_NOC_P_CCI	162
+#define CLK_PCLK_ASYNCAXI_CP1		163
+#define CLK_PCLK_ASYNCAXI_CP0		164
+#define CLK_PCLK_ASYNCAXI_DREX1_3	165
+#define CLK_PCLK_ASYNCAXI_DREX1_1	166
+#define CLK_PCLK_ASYNCAXI_DREX1_0	167
+#define CLK_PCLK_ASYNCAXI_DREX0_3	168
+#define CLK_PCLK_ASYNCAXI_DREX0_1	169
+#define CLK_PCLK_ASYNCAXI_DREX0_0	170
+#define CLK_PCLK_MIFSRVND_133		171
+#define CLK_PCLK_PMU_MIF		172
+#define CLK_PCLK_SYSREG_MIF		173
+#define CLK_PCLK_GPIO_ALIVE		174
+#define CLK_PCLK_ABB			175
+#define CLK_PCLK_PMU_APBIF		176
+#define CLK_PCLK_DDR_PHY1		177
+#define CLK_PCLK_DREX1			178
+#define CLK_PCLK_DDR_PHY0		179
+#define CLK_PCLK_DREX0			180
+#define CLK_PCLK_DREX0_TZ		181
+#define CLK_PCLK_DREX1_TZ		182
+#define CLK_PCLK_MONOTONIC_CNT		183
+#define CLK_PCLK_RTC			184
+#define CLK_SCLK_DSIM1_DISP		185
+#define CLK_SCLK_DECON_TV_VCLK_DISP	186
+#define CLK_SCLK_FREQ_DET_BUS_PLL	187
+#define CLK_SCLK_FREQ_DET_MFC_PLL	188
+#define CLK_SCLK_FREQ_DET_MEM0_PLL	189
+#define CLK_SCLK_FREQ_DET_MEM1_PLL	190
+#define CLK_SCLK_DSIM0_DISP		191
+#define CLK_SCLK_DSD_DISP		192
+#define CLK_SCLK_DECON_TV_ECLK_DISP	193
+#define CLK_SCLK_DECON_VCLK_DISP	194
+#define CLK_SCLK_DECON_ECLK_DISP	195
+#define CLK_SCLK_HPM_MIF		196
+#define CLK_SCLK_MFC_PLL		197
+#define CLK_SCLK_BUS_PLL		198
+#define CLK_SCLK_BUS_PLL_APOLLO		199
+#define CLK_SCLK_BUS_PLL_ATLAS		200
+
+#define MIF_NR_CLK			201
+
+/* CMU_PERIC */
+#define CLK_PCLK_SPI2			1
+#define CLK_PCLK_SPI1			2
+#define CLK_PCLK_SPI0			3
+#define CLK_PCLK_UART2			4
+#define CLK_PCLK_UART1			5
+#define CLK_PCLK_UART0			6
+#define CLK_PCLK_HSI2C3			7
+#define CLK_PCLK_HSI2C2			8
+#define CLK_PCLK_HSI2C1			9
+#define CLK_PCLK_HSI2C0			10
+#define CLK_PCLK_I2C7			11
+#define CLK_PCLK_I2C6			12
+#define CLK_PCLK_I2C5			13
+#define CLK_PCLK_I2C4			14
+#define CLK_PCLK_I2C3			15
+#define CLK_PCLK_I2C2			16
+#define CLK_PCLK_I2C1			17
+#define CLK_PCLK_I2C0			18
+#define CLK_PCLK_SPI4			19
+#define CLK_PCLK_SPI3			20
+#define CLK_PCLK_HSI2C11		21
+#define CLK_PCLK_HSI2C10		22
+#define CLK_PCLK_HSI2C9			23
+#define CLK_PCLK_HSI2C8			24
+#define CLK_PCLK_HSI2C7			25
+#define CLK_PCLK_HSI2C6			26
+#define CLK_PCLK_HSI2C5			27
+#define CLK_PCLK_HSI2C4			28
+#define CLK_SCLK_SPI4			29
+#define CLK_SCLK_SPI3			30
+#define CLK_SCLK_SPI2			31
+#define CLK_SCLK_SPI1			32
+#define CLK_SCLK_SPI0			33
+#define CLK_SCLK_UART2			34
+#define CLK_SCLK_UART1			35
+#define CLK_SCLK_UART0			36
+#define CLK_ACLK_AHB2APB_PERIC2P	37
+#define CLK_ACLK_AHB2APB_PERIC1P	38
+#define CLK_ACLK_AHB2APB_PERIC0P	39
+#define CLK_ACLK_PERICNP_66		40
+#define CLK_PCLK_SCI			41
+#define CLK_PCLK_GPIO_FINGER		42
+#define CLK_PCLK_GPIO_ESE		43
+#define CLK_PCLK_PWM			44
+#define CLK_PCLK_SPDIF			45
+#define CLK_PCLK_PCM1			46
+#define CLK_PCLK_I2S1			47
+#define CLK_PCLK_ADCIF			48
+#define CLK_PCLK_GPIO_TOUCH		49
+#define CLK_PCLK_GPIO_NFC		50
+#define CLK_PCLK_GPIO_PERIC		51
+#define CLK_PCLK_PMU_PERIC		52
+#define CLK_PCLK_SYSREG_PERIC		53
+#define CLK_SCLK_IOCLK_SPI4		54
+#define CLK_SCLK_IOCLK_SPI3		55
+#define CLK_SCLK_SCI			56
+#define CLK_SCLK_SC_IN			57
+#define CLK_SCLK_PWM			58
+#define CLK_SCLK_IOCLK_SPI2		59
+#define CLK_SCLK_IOCLK_SPI1		60
+#define CLK_SCLK_IOCLK_SPI0		61
+#define CLK_SCLK_IOCLK_I2S1_BCLK	62
+#define CLK_SCLK_SPDIF			63
+#define CLK_SCLK_PCM1			64
+#define CLK_SCLK_I2S1			65
+
+#define CLK_DIV_SCLK_SCI		70
+#define CLK_DIV_SCLK_SC_IN		71
+
+#define PERIC_NR_CLK			72
+
+/* CMU_PERIS */
+#define CLK_PCLK_HPM_APBIF		1
+#define CLK_PCLK_TMU1_APBIF		2
+#define CLK_PCLK_TMU0_APBIF		3
+#define CLK_PCLK_PMU_PERIS		4
+#define CLK_PCLK_SYSREG_PERIS		5
+#define CLK_PCLK_CMU_TOP_APBIF		6
+#define CLK_PCLK_WDT_APOLLO		7
+#define CLK_PCLK_WDT_ATLAS		8
+#define CLK_PCLK_MCT			9
+#define CLK_PCLK_HDMI_CEC		10
+#define CLK_ACLK_AHB2APB_PERIS1P	11
+#define CLK_ACLK_AHB2APB_PERIS0P	12
+#define CLK_ACLK_PERISNP_66		13
+#define CLK_PCLK_TZPC12			14
+#define CLK_PCLK_TZPC11			15
+#define CLK_PCLK_TZPC10			16
+#define CLK_PCLK_TZPC9			17
+#define CLK_PCLK_TZPC8			18
+#define CLK_PCLK_TZPC7			19
+#define CLK_PCLK_TZPC6			20
+#define CLK_PCLK_TZPC5			21
+#define CLK_PCLK_TZPC4			22
+#define CLK_PCLK_TZPC3			23
+#define CLK_PCLK_TZPC2			24
+#define CLK_PCLK_TZPC1			25
+#define CLK_PCLK_TZPC0			26
+#define CLK_PCLK_SECKEY_APBIF		27
+#define CLK_PCLK_CHIPID_APBIF		28
+#define CLK_PCLK_TOPRTC			29
+#define CLK_PCLK_CUSTOM_EFUSE_APBIF	30
+#define CLK_PCLK_ANTIRBK_CNT_APBIF	31
+#define CLK_PCLK_OTP_CON_APBIF		32
+#define CLK_SCLK_ASV_TB			33
+#define CLK_SCLK_TMU1			34
+#define CLK_SCLK_TMU0			35
+#define CLK_SCLK_SECKEY			36
+#define CLK_SCLK_CHIPID			37
+#define CLK_SCLK_TOPRTC			38
+#define CLK_SCLK_CUSTOM_EFUSE		39
+#define CLK_SCLK_ANTIRBK_CNT		40
+#define CLK_SCLK_OTP_CON		41
+
+#define PERIS_NR_CLK			42
+
+/* CMU_FSYS */
+#define CLK_MOUT_ACLK_FSYS_200_USER	1
+#define CLK_MOUT_SCLK_MMC2_USER		2
+#define CLK_MOUT_SCLK_MMC1_USER		3
+#define CLK_MOUT_SCLK_MMC0_USER		4
+#define CLK_MOUT_SCLK_UFS_MPHY_USER	5
+#define CLK_MOUT_SCLK_PCIE_100_USER	6
+#define CLK_MOUT_SCLK_UFSUNIPRO_USER	7
+#define CLK_MOUT_SCLK_USBHOST30_USER	8
+#define CLK_MOUT_SCLK_USBDRD30_USER	9
+#define CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_USER	10
+#define CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_USER		11
+#define CLK_MOUT_PHYCLK_USBHOST20_PHY_HSIC1_USER		12
+#define CLK_MOUT_PHYCLK_USBHOST20_PHY_CLK48MOHCI_USER		13
+#define CLK_MOUT_PHYCLK_USBHOST20_PHY_PHYCLOCK_USER		14
+#define CLK_MOUT_PHYCLK_USBHOST20_PHY_PHY_FREECLK_USER		15
+#define CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_USER		16
+#define CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_USER		17
+#define CLK_MOUT_PHYCLK_UFS_RX1_SYMBOL_USER			18
+#define CLK_MOUT_PHYCLK_UFS_RX0_SYMBOL_USER			19
+#define CLK_MOUT_PHYCLK_UFS_TX1_SYMBOL_USER			20
+#define CLK_MOUT_PHYCLK_UFS_TX0_SYMBOL_USER			21
+#define CLK_MOUT_PHYCLK_LLI_MPHY_TO_UFS_USER			22
+#define CLK_MOUT_SCLK_MPHY					23
+
+#define CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_PHY			25
+#define CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_PHY		26
+#define CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_PHY		27
+#define CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_PHY		28
+#define CLK_PHYCLK_USBHOST20_PHY_FREECLK_PHY			29
+#define CLK_PHYCLK_USBHOST20_PHY_PHYCLOCK_PHY			30
+#define CLK_PHYCLK_USBHOST20_PHY_CLK48MOHCI_PHY			31
+#define CLK_PHYCLK_USBHOST20_PHY_HSIC1_PHY			32
+#define CLK_PHYCLK_UFS_TX0_SYMBOL_PHY				33
+#define CLK_PHYCLK_UFS_RX0_SYMBOL_PHY				34
+#define CLK_PHYCLK_UFS_TX1_SYMBOL_PHY				35
+#define CLK_PHYCLK_UFS_RX1_SYMBOL_PHY				36
+#define CLK_PHYCLK_LLI_MPHY_TO_UFS_PHY				37
+
+#define CLK_ACLK_PCIE			50
+#define CLK_ACLK_PDMA1			51
+#define CLK_ACLK_TSI			52
+#define CLK_ACLK_MMC2			53
+#define CLK_ACLK_MMC1			54
+#define CLK_ACLK_MMC0			55
+#define CLK_ACLK_UFS			56
+#define CLK_ACLK_USBHOST20		57
+#define CLK_ACLK_USBHOST30		58
+#define CLK_ACLK_USBDRD30		59
+#define CLK_ACLK_PDMA0			60
+#define CLK_SCLK_MMC2			61
+#define CLK_SCLK_MMC1			62
+#define CLK_SCLK_MMC0			63
+#define CLK_PDMA1			64
+#define CLK_PDMA0			65
+#define CLK_ACLK_XIU_FSYSPX		66
+#define CLK_ACLK_AHB_USBLINKH1		67
+#define CLK_ACLK_SMMU_PDMA1		68
+#define CLK_ACLK_BTS_PCIE		69
+#define CLK_ACLK_AXIUS_PDMA1		70
+#define CLK_ACLK_SMMU_PDMA0		71
+#define CLK_ACLK_BTS_UFS		72
+#define CLK_ACLK_BTS_USBHOST30		73
+#define CLK_ACLK_BTS_USBDRD30		74
+#define CLK_ACLK_AXIUS_PDMA0		75
+#define CLK_ACLK_AXIUS_USBHS		76
+#define CLK_ACLK_AXIUS_FSYSSX		77
+#define CLK_ACLK_AHB2APB_FSYSP		78
+#define CLK_ACLK_AHB2AXI_USBHS		79
+#define CLK_ACLK_AHB_USBLINKH0		80
+#define CLK_ACLK_AHB_USBHS		81
+#define CLK_ACLK_AHB_FSYSH		82
+#define CLK_ACLK_XIU_FSYSX		83
+#define CLK_ACLK_XIU_FSYSSX		84
+#define CLK_ACLK_FSYSNP_200		85
+#define CLK_ACLK_FSYSND_200		86
+#define CLK_PCLK_PCIE_CTRL		87
+#define CLK_PCLK_SMMU_PDMA1		88
+#define CLK_PCLK_PCIE_PHY		89
+#define CLK_PCLK_BTS_PCIE		90
+#define CLK_PCLK_SMMU_PDMA0		91
+#define CLK_PCLK_BTS_UFS		92
+#define CLK_PCLK_BTS_USBHOST30		93
+#define CLK_PCLK_BTS_USBDRD30		94
+#define CLK_PCLK_GPIO_FSYS		95
+#define CLK_PCLK_PMU_FSYS		96
+#define CLK_PCLK_SYSREG_FSYS		97
+#define CLK_SCLK_PCIE_100		98
+#define CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK	99
+#define CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK	100
+#define CLK_PHYCLK_UFS_RX1_SYMBOL		101
+#define CLK_PHYCLK_UFS_RX0_SYMBOL		102
+#define CLK_PHYCLK_UFS_TX1_SYMBOL		103
+#define CLK_PHYCLK_UFS_TX0_SYMBOL		104
+#define CLK_PHYCLK_USBHOST20_PHY_HSIC1		105
+#define CLK_PHYCLK_USBHOST20_PHY_CLK48MOHCI	106
+#define CLK_PHYCLK_USBHOST20_PHY_PHYCLOCK	107
+#define CLK_PHYCLK_USBHOST20_PHY_FREECLK	108
+#define CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK	109
+#define CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK	110
+#define CLK_SCLK_MPHY			111
+#define CLK_SCLK_UFSUNIPRO		112
+#define CLK_SCLK_USBHOST30		113
+#define CLK_SCLK_USBDRD30		114
+#define CLK_PCIE			115
+
+#define FSYS_NR_CLK			116
+
+/* CMU_G2D */
+#define CLK_MUX_ACLK_G2D_266_USER	1
+#define CLK_MUX_ACLK_G2D_400_USER	2
+
+#define CLK_DIV_PCLK_G2D		3
+
+#define CLK_ACLK_SMMU_MDMA1		4
+#define CLK_ACLK_BTS_MDMA1		5
+#define CLK_ACLK_BTS_G2D		6
+#define CLK_ACLK_ALB_G2D		7
+#define CLK_ACLK_AXIUS_G2DX		8
+#define CLK_ACLK_ASYNCAXI_SYSX		9
+#define CLK_ACLK_AHB2APB_G2D1P		10
+#define CLK_ACLK_AHB2APB_G2D0P		11
+#define CLK_ACLK_XIU_G2DX		12
+#define CLK_ACLK_G2DNP_133		13
+#define CLK_ACLK_G2DND_400		14
+#define CLK_ACLK_MDMA1			15
+#define CLK_ACLK_G2D			16
+#define CLK_ACLK_SMMU_G2D		17
+#define CLK_PCLK_SMMU_MDMA1		18
+#define CLK_PCLK_BTS_MDMA1		19
+#define CLK_PCLK_BTS_G2D		20
+#define CLK_PCLK_ALB_G2D		21
+#define CLK_PCLK_ASYNCAXI_SYSX		22
+#define CLK_PCLK_PMU_G2D		23
+#define CLK_PCLK_SYSREG_G2D		24
+#define CLK_PCLK_G2D			25
+#define CLK_PCLK_SMMU_G2D		26
+
+#define G2D_NR_CLK			27
+
+/* CMU_DISP */
+#define CLK_FOUT_DISP_PLL				1
+
+#define CLK_MOUT_DISP_PLL				2
+#define CLK_MOUT_SCLK_DSIM1_USER			3
+#define CLK_MOUT_SCLK_DSIM0_USER			4
+#define CLK_MOUT_SCLK_DSD_USER				5
+#define CLK_MOUT_SCLK_DECON_TV_ECLK_USER		6
+#define CLK_MOUT_SCLK_DECON_VCLK_USER			7
+#define CLK_MOUT_SCLK_DECON_ECLK_USER			8
+#define CLK_MOUT_SCLK_DECON_TV_VCLK_USER		9
+#define CLK_MOUT_ACLK_DISP_333_USER			10
+#define CLK_MOUT_PHYCLK_MIPIDPHY1_BITCLKDIV8_USER	11
+#define CLK_MOUT_PHYCLK_MIPIDPHY1_RXCLKESC0_USER	12
+#define CLK_MOUT_PHYCLK_MIPIDPHY0_BITCLKDIV8_USER	13
+#define CLK_MOUT_PHYCLK_MIPIDPHY0_RXCLKESC0_USER	14
+#define CLK_MOUT_PHYCLK_HDMIPHY_TMDS_CLKO_USER		15
+#define CLK_MOUT_PHYCLK_HDMIPHY_PIXEL_CLKO_USER		16
+#define CLK_MOUT_SCLK_DSIM0				17
+#define CLK_MOUT_SCLK_DECON_TV_ECLK			18
+#define CLK_MOUT_SCLK_DECON_VCLK			19
+#define CLK_MOUT_SCLK_DECON_ECLK			20
+#define CLK_MOUT_SCLK_DSIM1_B_DISP			21
+#define CLK_MOUT_SCLK_DSIM1_A_DISP			22
+#define CLK_MOUT_SCLK_DECON_TV_VCLK_C_DISP		23
+#define CLK_MOUT_SCLK_DECON_TV_VCLK_B_DISP		24
+#define CLK_MOUT_SCLK_DECON_TV_VCLK_A_DISP		25
+
+#define CLK_DIV_SCLK_DSIM1_DISP				30
+#define CLK_DIV_SCLK_DECON_TV_VCLK_DISP			31
+#define CLK_DIV_SCLK_DSIM0_DISP				32
+#define CLK_DIV_SCLK_DECON_TV_ECLK_DISP			33
+#define CLK_DIV_SCLK_DECON_VCLK_DISP			34
+#define CLK_DIV_SCLK_DECON_ECLK_DISP			35
+#define CLK_DIV_PCLK_DISP				36
+
+#define CLK_ACLK_DECON_TV				40
+#define CLK_ACLK_DECON					41
+#define CLK_ACLK_SMMU_TV1X				42
+#define CLK_ACLK_SMMU_TV0X				43
+#define CLK_ACLK_SMMU_DECON1X				44
+#define CLK_ACLK_SMMU_DECON0X				45
+#define CLK_ACLK_BTS_DECON_TV_M3			46
+#define CLK_ACLK_BTS_DECON_TV_M2			47
+#define CLK_ACLK_BTS_DECON_TV_M1			48
+#define CLK_ACLK_BTS_DECON_TV_M0			49
+#define CLK_ACLK_BTS_DECON_NM4				50
+#define CLK_ACLK_BTS_DECON_NM3				51
+#define CLK_ACLK_BTS_DECON_NM2				52
+#define CLK_ACLK_BTS_DECON_NM1				53
+#define CLK_ACLK_BTS_DECON_NM0				54
+#define CLK_ACLK_AHB2APB_DISPSFR2P			55
+#define CLK_ACLK_AHB2APB_DISPSFR1P			56
+#define CLK_ACLK_AHB2APB_DISPSFR0P			57
+#define CLK_ACLK_AHB_DISPH				58
+#define CLK_ACLK_XIU_TV1X				59
+#define CLK_ACLK_XIU_TV0X				60
+#define CLK_ACLK_XIU_DECON1X				61
+#define CLK_ACLK_XIU_DECON0X				62
+#define CLK_ACLK_XIU_DISP1X				63
+#define CLK_ACLK_XIU_DISPNP_100				64
+#define CLK_ACLK_DISP1ND_333				65
+#define CLK_ACLK_DISP0ND_333				66
+#define CLK_PCLK_SMMU_TV1X				67
+#define CLK_PCLK_SMMU_TV0X				68
+#define CLK_PCLK_SMMU_DECON1X				69
+#define CLK_PCLK_SMMU_DECON0X				70
+#define CLK_PCLK_BTS_DECON_TV_M3			71
+#define CLK_PCLK_BTS_DECON_TV_M2			72
+#define CLK_PCLK_BTS_DECON_TV_M1			73
+#define CLK_PCLK_BTS_DECON_TV_M0			74
+#define CLK_PCLK_BTS_DECONM4				75
+#define CLK_PCLK_BTS_DECONM3				76
+#define CLK_PCLK_BTS_DECONM2				77
+#define CLK_PCLK_BTS_DECONM1				78
+#define CLK_PCLK_BTS_DECONM0				79
+#define CLK_PCLK_MIC1					80
+#define CLK_PCLK_PMU_DISP				81
+#define CLK_PCLK_SYSREG_DISP				82
+#define CLK_PCLK_HDMIPHY				83
+#define CLK_PCLK_HDMI					84
+#define CLK_PCLK_MIC0					85
+#define CLK_PCLK_DSIM1					86
+#define CLK_PCLK_DSIM0					87
+#define CLK_PCLK_DECON_TV				88
+#define CLK_PHYCLK_MIPIDPHY1_BITCLKDIV8			89
+#define CLK_PHYCLK_MIPIDPHY1_RXCLKESC0			90
+#define CLK_SCLK_RGB_TV_VCLK_TO_DSIM1			91
+#define CLK_SCLK_RGB_TV_VCLK_TO_MIC1			92
+#define CLK_SCLK_DSIM1					93
+#define CLK_SCLK_DECON_TV_VCLK				94
+#define CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8			95
+#define CLK_PHYCLK_MIPIDPHY0_RXCLKESC0			96
+#define CLK_PHYCLK_HDMIPHY_TMDS_CLKO			97
+#define CLK_PHYCLK_HDMI_PIXEL				98
+#define CLK_SCLK_RGB_VCLK_TO_SMIES			99
+#define CLK_SCLK_FREQ_DET_DISP_PLL			100
+#define CLK_SCLK_RGB_VCLK_TO_DSIM0			101
+#define CLK_SCLK_RGB_VCLK_TO_MIC0			102
+#define CLK_SCLK_DSD					103
+#define CLK_SCLK_HDMI_SPDIF				104
+#define CLK_SCLK_DSIM0					105
+#define CLK_SCLK_DECON_TV_ECLK				106
+#define CLK_SCLK_DECON_VCLK				107
+#define CLK_SCLK_DECON_ECLK				108
+#define CLK_SCLK_RGB_VCLK				109
+#define CLK_SCLK_RGB_TV_VCLK				110
+
+#define CLK_PHYCLK_HDMIPHY_PIXEL_CLKO_PHY		111
+#define CLK_PHYCLK_HDMIPHY_TMDS_CLKO_PHY		112
+
+#define CLK_PCLK_DECON					113
+
+#define CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8_PHY		114
+#define CLK_PHYCLK_MIPIDPHY0_RXCLKESC0_PHY		115
+
+#define DISP_NR_CLK					116
+
+/* CMU_AUD */
+#define CLK_MOUT_AUD_PLL_USER				1
+#define CLK_MOUT_SCLK_AUD_PCM				2
+#define CLK_MOUT_SCLK_AUD_I2S				3
+
+#define CLK_DIV_ATCLK_AUD				4
+#define CLK_DIV_PCLK_DBG_AUD				5
+#define CLK_DIV_ACLK_AUD				6
+#define CLK_DIV_AUD_CA5					7
+#define CLK_DIV_SCLK_AUD_SLIMBUS			8
+#define CLK_DIV_SCLK_AUD_UART				9
+#define CLK_DIV_SCLK_AUD_PCM				10
+#define CLK_DIV_SCLK_AUD_I2S				11
+
+#define CLK_ACLK_INTR_CTRL				12
+#define CLK_ACLK_AXIDS2_LPASSP				13
+#define CLK_ACLK_AXIDS1_LPASSP				14
+#define CLK_ACLK_AXI2APB1_LPASSP			15
+#define CLK_ACLK_AXI2APH_LPASSP				16
+#define CLK_ACLK_SMMU_LPASSX				17
+#define CLK_ACLK_AXIDS0_LPASSP				18
+#define CLK_ACLK_AXI2APB0_LPASSP			19
+#define CLK_ACLK_XIU_LPASSX				20
+#define CLK_ACLK_AUDNP_133				21
+#define CLK_ACLK_AUDND_133				22
+#define CLK_ACLK_SRAMC					23
+#define CLK_ACLK_DMAC					24
+#define CLK_PCLK_WDT1					25
+#define CLK_PCLK_WDT0					26
+#define CLK_PCLK_SFR1					27
+#define CLK_PCLK_SMMU_LPASSX				28
+#define CLK_PCLK_GPIO_AUD				29
+#define CLK_PCLK_PMU_AUD				30
+#define CLK_PCLK_SYSREG_AUD				31
+#define CLK_PCLK_AUD_SLIMBUS				32
+#define CLK_PCLK_AUD_UART				33
+#define CLK_PCLK_AUD_PCM				34
+#define CLK_PCLK_AUD_I2S				35
+#define CLK_PCLK_TIMER					36
+#define CLK_PCLK_SFR0_CTRL				37
+#define CLK_ATCLK_AUD					38
+#define CLK_PCLK_DBG_AUD				39
+#define CLK_SCLK_AUD_CA5				40
+#define CLK_SCLK_JTAG_TCK				41
+#define CLK_SCLK_SLIMBUS_CLKIN				42
+#define CLK_SCLK_AUD_SLIMBUS				43
+#define CLK_SCLK_AUD_UART				44
+#define CLK_SCLK_AUD_PCM				45
+#define CLK_SCLK_I2S_BCLK				46
+#define CLK_SCLK_AUD_I2S				47
+
+#define AUD_NR_CLK					48
+
+/* CMU_BUS{0|1|2} */
+#define CLK_DIV_PCLK_BUS_133				1
+
+#define CLK_ACLK_AHB2APB_BUSP				2
+#define CLK_ACLK_BUSNP_133				3
+#define CLK_ACLK_BUSND_400				4
+#define CLK_PCLK_BUSSRVND_133				5
+#define CLK_PCLK_PMU_BUS				6
+#define CLK_PCLK_SYSREG_BUS				7
+
+#define CLK_MOUT_ACLK_BUS2_400_USER			8  /* Only CMU_BUS2 */
+#define CLK_ACLK_BUS2BEND_400				9  /* Only CMU_BUS2 */
+#define CLK_ACLK_BUS2RTND_400				10 /* Only CMU_BUS2 */
+
+#define BUSx_NR_CLK					11
+
+/* CMU_G3D */
+#define CLK_FOUT_G3D_PLL				1
+
+#define CLK_MOUT_ACLK_G3D_400				2
+#define CLK_MOUT_G3D_PLL				3
+
+#define CLK_DIV_SCLK_HPM_G3D				4
+#define CLK_DIV_PCLK_G3D				5
+#define CLK_DIV_ACLK_G3D				6
+#define CLK_ACLK_BTS_G3D1				7
+#define CLK_ACLK_BTS_G3D0				8
+#define CLK_ACLK_ASYNCAPBS_G3D				9
+#define CLK_ACLK_ASYNCAPBM_G3D				10
+#define CLK_ACLK_AHB2APB_G3DP				11
+#define CLK_ACLK_G3DNP_150				12
+#define CLK_ACLK_G3DND_600				13
+#define CLK_ACLK_G3D					14
+#define CLK_PCLK_BTS_G3D1				15
+#define CLK_PCLK_BTS_G3D0				16
+#define CLK_PCLK_PMU_G3D				17
+#define CLK_PCLK_SYSREG_G3D				18
+#define CLK_SCLK_HPM_G3D				19
+
+#define G3D_NR_CLK					20
+
+/* CMU_GSCL */
+#define CLK_MOUT_ACLK_GSCL_111_USER			1
+#define CLK_MOUT_ACLK_GSCL_333_USER			2
+
+#define CLK_ACLK_BTS_GSCL2				3
+#define CLK_ACLK_BTS_GSCL1				4
+#define CLK_ACLK_BTS_GSCL0				5
+#define CLK_ACLK_AHB2APB_GSCLP				6
+#define CLK_ACLK_XIU_GSCLX				7
+#define CLK_ACLK_GSCLNP_111				8
+#define CLK_ACLK_GSCLRTND_333				9
+#define CLK_ACLK_GSCLBEND_333				10
+#define CLK_ACLK_GSD					11
+#define CLK_ACLK_GSCL2					12
+#define CLK_ACLK_GSCL1					13
+#define CLK_ACLK_GSCL0					14
+#define CLK_ACLK_SMMU_GSCL0				15
+#define CLK_ACLK_SMMU_GSCL1				16
+#define CLK_ACLK_SMMU_GSCL2				17
+#define CLK_PCLK_BTS_GSCL2				18
+#define CLK_PCLK_BTS_GSCL1				19
+#define CLK_PCLK_BTS_GSCL0				20
+#define CLK_PCLK_PMU_GSCL				21
+#define CLK_PCLK_SYSREG_GSCL				22
+#define CLK_PCLK_GSCL2					23
+#define CLK_PCLK_GSCL1					24
+#define CLK_PCLK_GSCL0					25
+#define CLK_PCLK_SMMU_GSCL0				26
+#define CLK_PCLK_SMMU_GSCL1				27
+#define CLK_PCLK_SMMU_GSCL2				28
+
+#define GSCL_NR_CLK					29
+
+/* CMU_APOLLO */
+#define CLK_FOUT_APOLLO_PLL				1
+
+#define CLK_MOUT_APOLLO_PLL				2
+#define CLK_MOUT_BUS_PLL_APOLLO_USER			3
+#define CLK_MOUT_APOLLO					4
+
+#define CLK_DIV_CNTCLK_APOLLO				5
+#define CLK_DIV_PCLK_DBG_APOLLO				6
+#define CLK_DIV_ATCLK_APOLLO				7
+#define CLK_DIV_PCLK_APOLLO				8
+#define CLK_DIV_ACLK_APOLLO				9
+#define CLK_DIV_APOLLO2					10
+#define CLK_DIV_APOLLO1					11
+#define CLK_DIV_SCLK_HPM_APOLLO				12
+#define CLK_DIV_APOLLO_PLL				13
+
+#define CLK_ACLK_ATBDS_APOLLO_3				14
+#define CLK_ACLK_ATBDS_APOLLO_2				15
+#define CLK_ACLK_ATBDS_APOLLO_1				16
+#define CLK_ACLK_ATBDS_APOLLO_0				17
+#define CLK_ACLK_ASATBSLV_APOLLO_3_CSSYS		18
+#define CLK_ACLK_ASATBSLV_APOLLO_2_CSSYS		19
+#define CLK_ACLK_ASATBSLV_APOLLO_1_CSSYS		20
+#define CLK_ACLK_ASATBSLV_APOLLO_0_CSSYS		21
+#define CLK_ACLK_ASYNCACES_APOLLO_CCI			22
+#define CLK_ACLK_AHB2APB_APOLLOP			23
+#define CLK_ACLK_APOLLONP_200				24
+#define CLK_PCLK_ASAPBMST_CSSYS_APOLLO			25
+#define CLK_PCLK_PMU_APOLLO				26
+#define CLK_PCLK_SYSREG_APOLLO				27
+#define CLK_CNTCLK_APOLLO				28
+#define CLK_SCLK_HPM_APOLLO				29
+#define CLK_SCLK_APOLLO					30
+
+#define APOLLO_NR_CLK					31
+
+/* CMU_ATLAS */
+#define CLK_FOUT_ATLAS_PLL				1
+
+#define CLK_MOUT_ATLAS_PLL				2
+#define CLK_MOUT_BUS_PLL_ATLAS_USER			3
+#define CLK_MOUT_ATLAS					4
+
+#define CLK_DIV_CNTCLK_ATLAS				5
+#define CLK_DIV_PCLK_DBG_ATLAS				6
+#define CLK_DIV_ATCLK_ATLASO				7
+#define CLK_DIV_PCLK_ATLAS				8
+#define CLK_DIV_ACLK_ATLAS				9
+#define CLK_DIV_ATLAS2					10
+#define CLK_DIV_ATLAS1					11
+#define CLK_DIV_SCLK_HPM_ATLAS				12
+#define CLK_DIV_ATLAS_PLL				13
+
+#define CLK_ACLK_ATB_AUD_CSSYS				14
+#define CLK_ACLK_ATB_APOLLO3_CSSYS			15
+#define CLK_ACLK_ATB_APOLLO2_CSSYS			16
+#define CLK_ACLK_ATB_APOLLO1_CSSYS			17
+#define CLK_ACLK_ATB_APOLLO0_CSSYS			18
+#define CLK_ACLK_ASYNCAHBS_CSSYS_SSS			19
+#define CLK_ACLK_ASYNCAXIS_CSSYS_CCIX			20
+#define CLK_ACLK_ASYNCACES_ATLAS_CCI			21
+#define CLK_ACLK_AHB2APB_ATLASP				22
+#define CLK_ACLK_ATLASNP_200				23
+#define CLK_PCLK_ASYNCAPB_AUD_CSSYS			24
+#define CLK_PCLK_ASYNCAPB_ISP_CSSYS			25
+#define CLK_PCLK_ASYNCAPB_APOLLO_CSSYS			26
+#define CLK_PCLK_PMU_ATLAS				27
+#define CLK_PCLK_SYSREG_ATLAS				28
+#define CLK_PCLK_SECJTAG				29
+#define CLK_CNTCLK_ATLAS				30
+#define CLK_SCLK_FREQ_DET_ATLAS_PLL			31
+#define CLK_SCLK_HPM_ATLAS				32
+#define CLK_TRACECLK					33
+#define CLK_CTMCLK					34
+#define CLK_HCLK_CSSYS					35
+#define CLK_PCLK_DBG_CSSYS				36
+#define CLK_PCLK_DBG					37
+#define CLK_ATCLK					38
+#define CLK_SCLK_ATLAS					39
+
+#define ATLAS_NR_CLK					40
+
+/* CMU_MSCL */
+#define CLK_MOUT_SCLK_JPEG_USER				1
+#define CLK_MOUT_ACLK_MSCL_400_USER			2
+#define CLK_MOUT_SCLK_JPEG				3
+
+#define CLK_DIV_PCLK_MSCL				4
+
+#define CLK_ACLK_BTS_JPEG				5
+#define CLK_ACLK_BTS_M2MSCALER1				6
+#define CLK_ACLK_BTS_M2MSCALER0				7
+#define CLK_ACLK_AHB2APB_MSCL0P				8
+#define CLK_ACLK_XIU_MSCLX				9
+#define CLK_ACLK_MSCLNP_100				10
+#define CLK_ACLK_MSCLND_400				11
+#define CLK_ACLK_JPEG					12
+#define CLK_ACLK_M2MSCALER1				13
+#define CLK_ACLK_M2MSCALER0				14
+#define CLK_ACLK_SMMU_M2MSCALER0			15
+#define CLK_ACLK_SMMU_M2MSCALER1			16
+#define CLK_ACLK_SMMU_JPEG				17
+#define CLK_PCLK_BTS_JPEG				18
+#define CLK_PCLK_BTS_M2MSCALER1				19
+#define CLK_PCLK_BTS_M2MSCALER0				20
+#define CLK_PCLK_PMU_MSCL				21
+#define CLK_PCLK_SYSREG_MSCL				22
+#define CLK_PCLK_JPEG					23
+#define CLK_PCLK_M2MSCALER1				24
+#define CLK_PCLK_M2MSCALER0				25
+#define CLK_PCLK_SMMU_M2MSCALER0			26
+#define CLK_PCLK_SMMU_M2MSCALER1			27
+#define CLK_PCLK_SMMU_JPEG				28
+#define CLK_SCLK_JPEG					29
+
+#define MSCL_NR_CLK					30
+
+/* CMU_MFC */
+#define CLK_MOUT_ACLK_MFC_400_USER			1
+
+#define CLK_DIV_PCLK_MFC				2
+
+#define CLK_ACLK_BTS_MFC_1				3
+#define CLK_ACLK_BTS_MFC_0				4
+#define CLK_ACLK_AHB2APB_MFCP				5
+#define CLK_ACLK_XIU_MFCX				6
+#define CLK_ACLK_MFCNP_100				7
+#define CLK_ACLK_MFCND_400				8
+#define CLK_ACLK_MFC					9
+#define CLK_ACLK_SMMU_MFC_1				10
+#define CLK_ACLK_SMMU_MFC_0				11
+#define CLK_PCLK_BTS_MFC_1				12
+#define CLK_PCLK_BTS_MFC_0				13
+#define CLK_PCLK_PMU_MFC				14
+#define CLK_PCLK_SYSREG_MFC				15
+#define CLK_PCLK_MFC					16
+#define CLK_PCLK_SMMU_MFC_1				17
+#define CLK_PCLK_SMMU_MFC_0				18
+
+#define MFC_NR_CLK					19
+
+/* CMU_HEVC */
+#define CLK_MOUT_ACLK_HEVC_400_USER			1
+
+#define CLK_DIV_PCLK_HEVC				2
+
+#define CLK_ACLK_BTS_HEVC_1				3
+#define CLK_ACLK_BTS_HEVC_0				4
+#define CLK_ACLK_AHB2APB_HEVCP				5
+#define CLK_ACLK_XIU_HEVCX				6
+#define CLK_ACLK_HEVCNP_100				7
+#define CLK_ACLK_HEVCND_400				8
+#define CLK_ACLK_HEVC					9
+#define CLK_ACLK_SMMU_HEVC_1				10
+#define CLK_ACLK_SMMU_HEVC_0				11
+#define CLK_PCLK_BTS_HEVC_1				12
+#define CLK_PCLK_BTS_HEVC_0				13
+#define CLK_PCLK_PMU_HEVC				14
+#define CLK_PCLK_SYSREG_HEVC				15
+#define CLK_PCLK_HEVC					16
+#define CLK_PCLK_SMMU_HEVC_1				17
+#define CLK_PCLK_SMMU_HEVC_0				18
+
+#define HEVC_NR_CLK					19
+
+/* CMU_ISP */
+#define CLK_MOUT_ACLK_ISP_DIS_400_USER			1
+#define CLK_MOUT_ACLK_ISP_400_USER			2
+
+#define CLK_DIV_PCLK_ISP_DIS				3
+#define CLK_DIV_PCLK_ISP				4
+#define CLK_DIV_ACLK_ISP_D_200				5
+#define CLK_DIV_ACLK_ISP_C_200				6
+
+#define CLK_ACLK_ISP_D_GLUE				7
+#define CLK_ACLK_SCALERP				8
+#define CLK_ACLK_3DNR					9
+#define CLK_ACLK_DIS					10
+#define CLK_ACLK_SCALERC				11
+#define CLK_ACLK_DRC					12
+#define CLK_ACLK_ISP					13
+#define CLK_ACLK_AXIUS_SCALERP				14
+#define CLK_ACLK_AXIUS_SCALERC				15
+#define CLK_ACLK_AXIUS_DRC				16
+#define CLK_ACLK_ASYNCAHBM_ISP2P			17
+#define CLK_ACLK_ASYNCAHBM_ISP1P			18
+#define CLK_ACLK_ASYNCAXIS_DIS1				19
+#define CLK_ACLK_ASYNCAXIS_DIS0				20
+#define CLK_ACLK_ASYNCAXIM_DIS1				21
+#define CLK_ACLK_ASYNCAXIM_DIS0				22
+#define CLK_ACLK_ASYNCAXIM_ISP2P			23
+#define CLK_ACLK_ASYNCAXIM_ISP1P			24
+#define CLK_ACLK_AHB2APB_ISP2P				25
+#define CLK_ACLK_AHB2APB_ISP1P				26
+#define CLK_ACLK_AXI2APB_ISP2P				27
+#define CLK_ACLK_AXI2APB_ISP1P				28
+#define CLK_ACLK_XIU_ISPEX1				29
+#define CLK_ACLK_XIU_ISPEX0				30
+#define CLK_ACLK_ISPND_400				31
+#define CLK_ACLK_SMMU_SCALERP				32
+#define CLK_ACLK_SMMU_3DNR				33
+#define CLK_ACLK_SMMU_DIS1				34
+#define CLK_ACLK_SMMU_DIS0				35
+#define CLK_ACLK_SMMU_SCALERC				36
+#define CLK_ACLK_SMMU_DRC				37
+#define CLK_ACLK_SMMU_ISP				38
+#define CLK_ACLK_BTS_SCALERP				39
+#define CLK_ACLK_BTS_3DR				40
+#define CLK_ACLK_BTS_DIS1				41
+#define CLK_ACLK_BTS_DIS0				42
+#define CLK_ACLK_BTS_SCALERC				43
+#define CLK_ACLK_BTS_DRC				44
+#define CLK_ACLK_BTS_ISP				45
+#define CLK_PCLK_SMMU_SCALERP				46
+#define CLK_PCLK_SMMU_3DNR				47
+#define CLK_PCLK_SMMU_DIS1				48
+#define CLK_PCLK_SMMU_DIS0				49
+#define CLK_PCLK_SMMU_SCALERC				50
+#define CLK_PCLK_SMMU_DRC				51
+#define CLK_PCLK_SMMU_ISP				52
+#define CLK_PCLK_BTS_SCALERP				53
+#define CLK_PCLK_BTS_3DNR				54
+#define CLK_PCLK_BTS_DIS1				55
+#define CLK_PCLK_BTS_DIS0				56
+#define CLK_PCLK_BTS_SCALERC				57
+#define CLK_PCLK_BTS_DRC				58
+#define CLK_PCLK_BTS_ISP				59
+#define CLK_PCLK_ASYNCAXI_DIS1				60
+#define CLK_PCLK_ASYNCAXI_DIS0				61
+#define CLK_PCLK_PMU_ISP				62
+#define CLK_PCLK_SYSREG_ISP				63
+#define CLK_PCLK_CMU_ISP_LOCAL				64
+#define CLK_PCLK_SCALERP				65
+#define CLK_PCLK_3DNR					66
+#define CLK_PCLK_DIS_CORE				67
+#define CLK_PCLK_DIS					68
+#define CLK_PCLK_SCALERC				69
+#define CLK_PCLK_DRC					70
+#define CLK_PCLK_ISP					71
+#define CLK_SCLK_PIXELASYNCS_DIS			72
+#define CLK_SCLK_PIXELASYNCM_DIS			73
+#define CLK_SCLK_PIXELASYNCS_SCALERP			74
+#define CLK_SCLK_PIXELASYNCM_ISPD			75
+#define CLK_SCLK_PIXELASYNCS_ISPC			76
+#define CLK_SCLK_PIXELASYNCM_ISPC			77
+
+#define ISP_NR_CLK					78
+
+/* CMU_CAM0 */
+#define CLK_PHYCLK_RXBYTEECLKHS0_S4_PHY			1
+#define CLK_PHYCLK_RXBYTEECLKHS0_S2A_PHY		2
+
+#define CLK_MOUT_ACLK_CAM0_333_USER			3
+#define CLK_MOUT_ACLK_CAM0_400_USER			4
+#define CLK_MOUT_ACLK_CAM0_552_USER			5
+#define CLK_MOUT_PHYCLK_RXBYTECLKHS0_S4_USER		6
+#define CLK_MOUT_PHYCLK_RXBYTECLKHS0_S2A_USER		7
+#define CLK_MOUT_ACLK_LITE_D_B				8
+#define CLK_MOUT_ACLK_LITE_D_A				9
+#define CLK_MOUT_ACLK_LITE_B_B				10
+#define CLK_MOUT_ACLK_LITE_B_A				11
+#define CLK_MOUT_ACLK_LITE_A_B				12
+#define CLK_MOUT_ACLK_LITE_A_A				13
+#define CLK_MOUT_ACLK_CAM0_400				14
+#define CLK_MOUT_ACLK_CSIS1_B				15
+#define CLK_MOUT_ACLK_CSIS1_A				16
+#define CLK_MOUT_ACLK_CSIS0_B				17
+#define CLK_MOUT_ACLK_CSIS0_A				18
+#define CLK_MOUT_ACLK_3AA1_B				19
+#define CLK_MOUT_ACLK_3AA1_A				20
+#define CLK_MOUT_ACLK_3AA0_B				21
+#define CLK_MOUT_ACLK_3AA0_A				22
+#define CLK_MOUT_SCLK_LITE_FREECNT_C			23
+#define CLK_MOUT_SCLK_LITE_FREECNT_B			24
+#define CLK_MOUT_SCLK_LITE_FREECNT_A			25
+#define CLK_MOUT_SCLK_PIXELASYNC_LITE_C_B		26
+#define CLK_MOUT_SCLK_PIXELASYNC_LITE_C_A		27
+#define CLK_MOUT_SCLK_PIXELASYNC_LITE_C_INIT_B		28
+#define CLK_MOUT_SCLK_PIXELASYNC_LITE_C_INIT_A		29
+
+#define CLK_DIV_PCLK_CAM0_50				30
+#define CLK_DIV_ACLK_CAM0_200				31
+#define CLK_DIV_ACLK_CAM0_BUS_400			32
+#define CLK_DIV_PCLK_LITE_D				33
+#define CLK_DIV_ACLK_LITE_D				34
+#define CLK_DIV_PCLK_LITE_B				35
+#define CLK_DIV_ACLK_LITE_B				36
+#define CLK_DIV_PCLK_LITE_A				37
+#define CLK_DIV_ACLK_LITE_A				38
+#define CLK_DIV_ACLK_CSIS1				39
+#define CLK_DIV_ACLK_CSIS0				40
+#define CLK_DIV_PCLK_3AA1				41
+#define CLK_DIV_ACLK_3AA1				42
+#define CLK_DIV_PCLK_3AA0				43
+#define CLK_DIV_ACLK_3AA0				44
+#define CLK_DIV_SCLK_PIXELASYNC_LITE_C			45
+#define CLK_DIV_PCLK_PIXELASYNC_LITE_C			46
+#define CLK_DIV_SCLK_PIXELASYNC_LITE_C_INIT		47
+
+#define CLK_ACLK_CSIS1					50
+#define CLK_ACLK_CSIS0					51
+#define CLK_ACLK_3AA1					52
+#define CLK_ACLK_3AA0					53
+#define CLK_ACLK_LITE_D					54
+#define CLK_ACLK_LITE_B					55
+#define CLK_ACLK_LITE_A					56
+#define CLK_ACLK_AHBSYNCDN				57
+#define CLK_ACLK_AXIUS_LITE_D				58
+#define CLK_ACLK_AXIUS_LITE_B				59
+#define CLK_ACLK_AXIUS_LITE_A				60
+#define CLK_ACLK_ASYNCAPBM_3AA1				61
+#define CLK_ACLK_ASYNCAPBS_3AA1				62
+#define CLK_ACLK_ASYNCAPBM_3AA0				63
+#define CLK_ACLK_ASYNCAPBS_3AA0				64
+#define CLK_ACLK_ASYNCAPBM_LITE_D			65
+#define CLK_ACLK_ASYNCAPBS_LITE_D			66
+#define CLK_ACLK_ASYNCAPBM_LITE_B			67
+#define CLK_ACLK_ASYNCAPBS_LITE_B			68
+#define CLK_ACLK_ASYNCAPBM_LITE_A			69
+#define CLK_ACLK_ASYNCAPBS_LITE_A			70
+#define CLK_ACLK_ASYNCAXIM_ISP0P			71
+#define CLK_ACLK_ASYNCAXIM_3AA1				72
+#define CLK_ACLK_ASYNCAXIS_3AA1				73
+#define CLK_ACLK_ASYNCAXIM_3AA0				74
+#define CLK_ACLK_ASYNCAXIS_3AA0				75
+#define CLK_ACLK_ASYNCAXIM_LITE_D			76
+#define CLK_ACLK_ASYNCAXIS_LITE_D			77
+#define CLK_ACLK_ASYNCAXIM_LITE_B			78
+#define CLK_ACLK_ASYNCAXIS_LITE_B			79
+#define CLK_ACLK_ASYNCAXIM_LITE_A			80
+#define CLK_ACLK_ASYNCAXIS_LITE_A			81
+#define CLK_ACLK_AHB2APB_ISPSFRP			82
+#define CLK_ACLK_AXI2APB_ISP0P				83
+#define CLK_ACLK_AXI2AHB_ISP0P				84
+#define CLK_ACLK_XIU_IS0X				85
+#define CLK_ACLK_XIU_ISP0EX				86
+#define CLK_ACLK_CAM0NP_276				87
+#define CLK_ACLK_CAM0ND_400				88
+#define CLK_ACLK_SMMU_3AA1				89
+#define CLK_ACLK_SMMU_3AA0				90
+#define CLK_ACLK_SMMU_LITE_D				91
+#define CLK_ACLK_SMMU_LITE_B				92
+#define CLK_ACLK_SMMU_LITE_A				93
+#define CLK_ACLK_BTS_3AA1				94
+#define CLK_ACLK_BTS_3AA0				95
+#define CLK_ACLK_BTS_LITE_D				96
+#define CLK_ACLK_BTS_LITE_B				97
+#define CLK_ACLK_BTS_LITE_A				98
+#define CLK_PCLK_SMMU_3AA1				99
+#define CLK_PCLK_SMMU_3AA0				100
+#define CLK_PCLK_SMMU_LITE_D				101
+#define CLK_PCLK_SMMU_LITE_B				102
+#define CLK_PCLK_SMMU_LITE_A				103
+#define CLK_PCLK_BTS_3AA1				104
+#define CLK_PCLK_BTS_3AA0				105
+#define CLK_PCLK_BTS_LITE_D				106
+#define CLK_PCLK_BTS_LITE_B				107
+#define CLK_PCLK_BTS_LITE_A				108
+#define CLK_PCLK_ASYNCAXI_CAM1				109
+#define CLK_PCLK_ASYNCAXI_3AA1				110
+#define CLK_PCLK_ASYNCAXI_3AA0				111
+#define CLK_PCLK_ASYNCAXI_LITE_D			112
+#define CLK_PCLK_ASYNCAXI_LITE_B			113
+#define CLK_PCLK_ASYNCAXI_LITE_A			114
+#define CLK_PCLK_PMU_CAM0				115
+#define CLK_PCLK_SYSREG_CAM0				116
+#define CLK_PCLK_CMU_CAM0_LOCAL				117
+#define CLK_PCLK_CSIS1					118
+#define CLK_PCLK_CSIS0					119
+#define CLK_PCLK_3AA1					120
+#define CLK_PCLK_3AA0					121
+#define CLK_PCLK_LITE_D					122
+#define CLK_PCLK_LITE_B					123
+#define CLK_PCLK_LITE_A					124
+#define CLK_PHYCLK_RXBYTECLKHS0_S4			125
+#define CLK_PHYCLK_RXBYTECLKHS0_S2A			126
+#define CLK_SCLK_LITE_FREECNT				127
+#define CLK_SCLK_PIXELASYNCM_3AA1			128
+#define CLK_SCLK_PIXELASYNCM_3AA0			129
+#define CLK_SCLK_PIXELASYNCS_3AA0			130
+#define CLK_SCLK_PIXELASYNCM_LITE_C			131
+#define CLK_SCLK_PIXELASYNCM_LITE_C_INIT		132
+#define CLK_SCLK_PIXELASYNCS_LITE_C_INIT		133
+
+#define CAM0_NR_CLK					134
+
+/* CMU_CAM1 */
+#define CLK_PHYCLK_RXBYTEECLKHS0_S2B			1
+
+#define CLK_MOUT_SCLK_ISP_UART_USER			2
+#define CLK_MOUT_SCLK_ISP_SPI1_USER			3
+#define CLK_MOUT_SCLK_ISP_SPI0_USER			4
+#define CLK_MOUT_ACLK_CAM1_333_USER			5
+#define CLK_MOUT_ACLK_CAM1_400_USER			6
+#define CLK_MOUT_ACLK_CAM1_552_USER			7
+#define CLK_MOUT_PHYCLK_RXBYTECLKHS0_S2B_USER		8
+#define CLK_MOUT_ACLK_CSIS2_B				9
+#define CLK_MOUT_ACLK_CSIS2_A				10
+#define CLK_MOUT_ACLK_FD_B				11
+#define CLK_MOUT_ACLK_FD_A				12
+#define CLK_MOUT_ACLK_LITE_C_B				13
+#define CLK_MOUT_ACLK_LITE_C_A				14
+
+#define CLK_DIV_SCLK_ISP_MPWM				15
+#define CLK_DIV_PCLK_CAM1_83				16
+#define CLK_DIV_PCLK_CAM1_166				17
+#define CLK_DIV_PCLK_DBG_CAM1				18
+#define CLK_DIV_ATCLK_CAM1				19
+#define CLK_DIV_ACLK_CSIS2				20
+#define CLK_DIV_PCLK_FD					21
+#define CLK_DIV_ACLK_FD					22
+#define CLK_DIV_PCLK_LITE_C				23
+#define CLK_DIV_ACLK_LITE_C				24
+
+#define CLK_ACLK_ISP_GIC				25
+#define CLK_ACLK_FD					26
+#define CLK_ACLK_LITE_C					27
+#define CLK_ACLK_CSIS2					28
+#define CLK_ACLK_ASYNCAPBM_FD				29
+#define CLK_ACLK_ASYNCAPBS_FD				30
+#define CLK_ACLK_ASYNCAPBM_LITE_C			31
+#define CLK_ACLK_ASYNCAPBS_LITE_C			32
+#define CLK_ACLK_ASYNCAHBS_SFRISP2H2			33
+#define CLK_ACLK_ASYNCAHBS_SFRISP2H1			34
+#define CLK_ACLK_ASYNCAXIM_CA5				35
+#define CLK_ACLK_ASYNCAXIS_CA5				36
+#define CLK_ACLK_ASYNCAXIS_ISPX2			37
+#define CLK_ACLK_ASYNCAXIS_ISPX1			38
+#define CLK_ACLK_ASYNCAXIS_ISPX0			39
+#define CLK_ACLK_ASYNCAXIM_ISPEX			40
+#define CLK_ACLK_ASYNCAXIM_ISP3P			41
+#define CLK_ACLK_ASYNCAXIS_ISP3P			42
+#define CLK_ACLK_ASYNCAXIM_FD				43
+#define CLK_ACLK_ASYNCAXIS_FD				44
+#define CLK_ACLK_ASYNCAXIM_LITE_C			45
+#define CLK_ACLK_ASYNCAXIS_LITE_C			46
+#define CLK_ACLK_AHB2APB_ISP5P				47
+#define CLK_ACLK_AHB2APB_ISP3P				48
+#define CLK_ACLK_AXI2APB_ISP3P				49
+#define CLK_ACLK_AHB_SFRISP2H				50
+#define CLK_ACLK_AXI_ISP_HX_R				51
+#define CLK_ACLK_AXI_ISP_CX_R				52
+#define CLK_ACLK_AXI_ISP_HX				53
+#define CLK_ACLK_AXI_ISP_CX				54
+#define CLK_ACLK_XIU_ISPX				55
+#define CLK_ACLK_XIU_ISPEX				56
+#define CLK_ACLK_CAM1NP_333				57
+#define CLK_ACLK_CAM1ND_400				58
+#define CLK_ACLK_SMMU_ISPCPU				59
+#define CLK_ACLK_SMMU_FD				60
+#define CLK_ACLK_SMMU_LITE_C				61
+#define CLK_ACLK_BTS_ISP3P				62
+#define CLK_ACLK_BTS_FD					63
+#define CLK_ACLK_BTS_LITE_C				64
+#define CLK_ACLK_AHBDN_SFRISP2H				65
+#define CLK_ACLK_AHBDN_ISP5P				66
+#define CLK_ACLK_AXIUS_ISP3P				67
+#define CLK_ACLK_AXIUS_FD				68
+#define CLK_ACLK_AXIUS_LITE_C				69
+#define CLK_PCLK_SMMU_ISPCPU				70
+#define CLK_PCLK_SMMU_FD				71
+#define CLK_PCLK_SMMU_LITE_C				72
+#define CLK_PCLK_BTS_ISP3P				73
+#define CLK_PCLK_BTS_FD					74
+#define CLK_PCLK_BTS_LITE_C				75
+#define CLK_PCLK_ASYNCAXIM_CA5				76
+#define CLK_PCLK_ASYNCAXIM_ISPEX			77
+#define CLK_PCLK_ASYNCAXIM_ISP3P			78
+#define CLK_PCLK_ASYNCAXIM_FD				79
+#define CLK_PCLK_ASYNCAXIM_LITE_C			80
+#define CLK_PCLK_PMU_CAM1				81
+#define CLK_PCLK_SYSREG_CAM1				82
+#define CLK_PCLK_CMU_CAM1_LOCAL				83
+#define CLK_PCLK_ISP_MCTADC				84
+#define CLK_PCLK_ISP_WDT				85
+#define CLK_PCLK_ISP_PWM				86
+#define CLK_PCLK_ISP_UART				87
+#define CLK_PCLK_ISP_MCUCTL				88
+#define CLK_PCLK_ISP_SPI1				89
+#define CLK_PCLK_ISP_SPI0				90
+#define CLK_PCLK_ISP_I2C2				91
+#define CLK_PCLK_ISP_I2C1				92
+#define CLK_PCLK_ISP_I2C0				93
+#define CLK_PCLK_ISP_MPWM				94
+#define CLK_PCLK_FD					95
+#define CLK_PCLK_LITE_C					96
+#define CLK_PCLK_CSIS2					97
+#define CLK_SCLK_ISP_I2C2				98
+#define CLK_SCLK_ISP_I2C1				99
+#define CLK_SCLK_ISP_I2C0				100
+#define CLK_SCLK_ISP_PWM				101
+#define CLK_PHYCLK_RXBYTECLKHS0_S2B			102
+#define CLK_SCLK_LITE_C_FREECNT				103
+#define CLK_SCLK_PIXELASYNCM_FD				104
+#define CLK_SCLK_ISP_MCTADC				105
+#define CLK_SCLK_ISP_UART				106
+#define CLK_SCLK_ISP_SPI1				107
+#define CLK_SCLK_ISP_SPI0				108
+#define CLK_SCLK_ISP_MPWM				109
+#define CLK_PCLK_DBG_ISP				110
+#define CLK_ATCLK_ISP					111
+#define CLK_SCLK_ISP_CA5				112
+
+#define CAM1_NR_CLK					113
+
+#endif /* _DT_BINDINGS_CLOCK_EXYNOS5433_H */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/exynos7-clk.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/exynos7-clk.h
new file mode 100644
index 0000000000000000000000000000000000000000..10c558611085df705e982623a1934031015de461
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/exynos7-clk.h
@@ -0,0 +1,207 @@
+/*
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * Author: Naveen Krishna Ch <naveenkrishna.ch@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef _DT_BINDINGS_CLOCK_EXYNOS7_H
+#define _DT_BINDINGS_CLOCK_EXYNOS7_H
+
+/* TOPC */
+#define DOUT_ACLK_PERIS			1
+#define DOUT_SCLK_BUS0_PLL		2
+#define DOUT_SCLK_BUS1_PLL		3
+#define DOUT_SCLK_CC_PLL		4
+#define DOUT_SCLK_MFC_PLL		5
+#define DOUT_ACLK_CCORE_133		6
+#define DOUT_ACLK_MSCL_532		7
+#define ACLK_MSCL_532			8
+#define DOUT_SCLK_AUD_PLL		9
+#define FOUT_AUD_PLL			10
+#define SCLK_AUD_PLL			11
+#define SCLK_MFC_PLL_B			12
+#define SCLK_MFC_PLL_A			13
+#define SCLK_BUS1_PLL_B			14
+#define SCLK_BUS1_PLL_A			15
+#define SCLK_BUS0_PLL_B			16
+#define SCLK_BUS0_PLL_A			17
+#define SCLK_CC_PLL_B			18
+#define SCLK_CC_PLL_A			19
+#define ACLK_CCORE_133			20
+#define ACLK_PERIS_66			21
+#define TOPC_NR_CLK			22
+
+/* TOP0 */
+#define DOUT_ACLK_PERIC1		1
+#define DOUT_ACLK_PERIC0		2
+#define CLK_SCLK_UART0			3
+#define CLK_SCLK_UART1			4
+#define CLK_SCLK_UART2			5
+#define CLK_SCLK_UART3			6
+#define CLK_SCLK_SPI0			7
+#define CLK_SCLK_SPI1			8
+#define CLK_SCLK_SPI2			9
+#define CLK_SCLK_SPI3			10
+#define CLK_SCLK_SPI4			11
+#define CLK_SCLK_SPDIF			12
+#define CLK_SCLK_PCM1			13
+#define CLK_SCLK_I2S1			14
+#define CLK_ACLK_PERIC0_66		15
+#define CLK_ACLK_PERIC1_66		16
+#define TOP0_NR_CLK			17
+
+/* TOP1 */
+#define DOUT_ACLK_FSYS1_200		1
+#define DOUT_ACLK_FSYS0_200		2
+#define DOUT_SCLK_MMC2			3
+#define DOUT_SCLK_MMC1			4
+#define DOUT_SCLK_MMC0			5
+#define CLK_SCLK_MMC2			6
+#define CLK_SCLK_MMC1			7
+#define CLK_SCLK_MMC0			8
+#define CLK_ACLK_FSYS0_200		9
+#define CLK_ACLK_FSYS1_200		10
+#define CLK_SCLK_PHY_FSYS1		11
+#define CLK_SCLK_PHY_FSYS1_26M		12
+#define MOUT_SCLK_UFSUNIPRO20		13
+#define DOUT_SCLK_UFSUNIPRO20		14
+#define CLK_SCLK_UFSUNIPRO20		15
+#define DOUT_SCLK_PHY_FSYS1		16
+#define DOUT_SCLK_PHY_FSYS1_26M		17
+#define TOP1_NR_CLK			18
+
+/* CCORE */
+#define PCLK_RTC			1
+#define CCORE_NR_CLK			2
+
+/* PERIC0 */
+#define PCLK_UART0			1
+#define SCLK_UART0			2
+#define PCLK_HSI2C0			3
+#define PCLK_HSI2C1			4
+#define PCLK_HSI2C4			5
+#define PCLK_HSI2C5			6
+#define PCLK_HSI2C9			7
+#define PCLK_HSI2C10			8
+#define PCLK_HSI2C11			9
+#define PCLK_PWM			10
+#define SCLK_PWM			11
+#define PCLK_ADCIF			12
+#define PERIC0_NR_CLK			13
+
+/* PERIC1 */
+#define PCLK_UART1			1
+#define PCLK_UART2			2
+#define PCLK_UART3			3
+#define SCLK_UART1			4
+#define SCLK_UART2			5
+#define SCLK_UART3			6
+#define PCLK_HSI2C2			7
+#define PCLK_HSI2C3			8
+#define PCLK_HSI2C6			9
+#define PCLK_HSI2C7			10
+#define PCLK_HSI2C8			11
+#define PCLK_SPI0			12
+#define PCLK_SPI1			13
+#define PCLK_SPI2			14
+#define PCLK_SPI3			15
+#define PCLK_SPI4			16
+#define SCLK_SPI0			17
+#define SCLK_SPI1			18
+#define SCLK_SPI2			19
+#define SCLK_SPI3			20
+#define SCLK_SPI4			21
+#define PCLK_I2S1			22
+#define PCLK_PCM1			23
+#define PCLK_SPDIF			24
+#define SCLK_I2S1			25
+#define SCLK_PCM1			26
+#define SCLK_SPDIF			27
+#define PERIC1_NR_CLK			28
+
+/* PERIS */
+#define PCLK_CHIPID			1
+#define SCLK_CHIPID			2
+#define PCLK_WDT			3
+#define PCLK_TMU			4
+#define SCLK_TMU			5
+#define PERIS_NR_CLK			6
+
+/* FSYS0 */
+#define ACLK_MMC2			1
+#define ACLK_AXIUS_USBDRD30X_FSYS0X	2
+#define ACLK_USBDRD300			3
+#define SCLK_USBDRD300_SUSPENDCLK	4
+#define SCLK_USBDRD300_REFCLK		5
+#define PHYCLK_USBDRD300_UDRD30_PIPE_PCLK_USER		6
+#define PHYCLK_USBDRD300_UDRD30_PHYCLK_USER		7
+#define OSCCLK_PHY_CLKOUT_USB30_PHY		8
+#define ACLK_PDMA0			9
+#define ACLK_PDMA1			10
+#define FSYS0_NR_CLK			11
+
+/* FSYS1 */
+#define ACLK_MMC1			1
+#define ACLK_MMC0			2
+#define PHYCLK_UFS20_TX0_SYMBOL		3
+#define PHYCLK_UFS20_RX0_SYMBOL		4
+#define PHYCLK_UFS20_RX1_SYMBOL		5
+#define ACLK_UFS20_LINK			6
+#define SCLK_UFSUNIPRO20_USER		7
+#define PHYCLK_UFS20_RX1_SYMBOL_USER	8
+#define PHYCLK_UFS20_RX0_SYMBOL_USER	9
+#define PHYCLK_UFS20_TX0_SYMBOL_USER	10
+#define OSCCLK_PHY_CLKOUT_EMBEDDED_COMBO_PHY	11
+#define SCLK_COMBO_PHY_EMBEDDED_26M	12
+#define DOUT_PCLK_FSYS1			13
+#define PCLK_GPIO_FSYS1			14
+#define MOUT_FSYS1_PHYCLK_SEL1		15
+#define FSYS1_NR_CLK			16
+
+/* MSCL */
+#define USERMUX_ACLK_MSCL_532		1
+#define DOUT_PCLK_MSCL			2
+#define ACLK_MSCL_0			3
+#define ACLK_MSCL_1			4
+#define ACLK_JPEG			5
+#define ACLK_G2D			6
+#define ACLK_LH_ASYNC_SI_MSCL_0		7
+#define ACLK_LH_ASYNC_SI_MSCL_1		8
+#define ACLK_AXI2ACEL_BRIDGE		9
+#define ACLK_XIU_MSCLX_0		10
+#define ACLK_XIU_MSCLX_1		11
+#define ACLK_QE_MSCL_0			12
+#define ACLK_QE_MSCL_1			13
+#define ACLK_QE_JPEG			14
+#define ACLK_QE_G2D			15
+#define ACLK_PPMU_MSCL_0		16
+#define ACLK_PPMU_MSCL_1		17
+#define ACLK_MSCLNP_133			18
+#define ACLK_AHB2APB_MSCL0P		19
+#define ACLK_AHB2APB_MSCL1P		20
+
+#define PCLK_MSCL_0			21
+#define PCLK_MSCL_1			22
+#define PCLK_JPEG			23
+#define PCLK_G2D			24
+#define PCLK_QE_MSCL_0			25
+#define PCLK_QE_MSCL_1			26
+#define PCLK_QE_JPEG			27
+#define PCLK_QE_G2D			28
+#define PCLK_PPMU_MSCL_0		29
+#define PCLK_PPMU_MSCL_1		30
+#define PCLK_AXI2ACEL_BRIDGE		31
+#define PCLK_PMU_MSCL			32
+#define MSCL_NR_CLK			33
+
+/* AUD */
+#define SCLK_I2S			1
+#define SCLK_PCM			2
+#define PCLK_I2S			3
+#define PCLK_PCM			4
+#define ACLK_ADMA			5
+#define AUD_NR_CLK			6
+#endif /* _DT_BINDINGS_CLOCK_EXYNOS7_H */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/gxbb-aoclkc.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/gxbb-aoclkc.h
new file mode 100644
index 0000000000000000000000000000000000000000..9d15e2221fdb7fd5f732eaa5a800f7b66112f8a5
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/gxbb-aoclkc.h
@@ -0,0 +1,67 @@
+/*
+ * This file is provided under a dual BSD/GPLv2 license.  When using or
+ * redistributing this file, you may do so under either license.
+ *
+ * GPL LICENSE SUMMARY
+ *
+ * Copyright (c) 2016 BayLibre, SAS.
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see <http://www.gnu.org/licenses/>.
+ * The full GNU General Public License is included in this distribution
+ * in the file called COPYING.
+ *
+ * BSD LICENSE
+ *
+ * Copyright (c) 2016 BayLibre, SAS.
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *   * Redistributions in binary form must reproduce the above copyright
+ *     notice, this list of conditions and the following disclaimer in
+ *     the documentation and/or other materials provided with the
+ *     distribution.
+ *   * Neither the name of Intel Corporation nor the names of its
+ *     contributors may be used to endorse or promote products derived
+ *     from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef DT_BINDINGS_CLOCK_AMLOGIC_MESON_GXBB_AOCLK
+#define DT_BINDINGS_CLOCK_AMLOGIC_MESON_GXBB_AOCLK
+
+#define CLKID_AO_REMOTE		0
+#define CLKID_AO_I2C_MASTER	1
+#define CLKID_AO_I2C_SLAVE	2
+#define CLKID_AO_UART1		3
+#define CLKID_AO_UART2		4
+#define CLKID_AO_IR_BLASTER	5
+#define CLKID_AO_CEC_32K	6
+
+#endif
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/gxbb-clkc.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/gxbb-clkc.h
new file mode 100644
index 0000000000000000000000000000000000000000..3979d48c025f6e563dd97fda90eebb12fbe848b7
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/gxbb-clkc.h
@@ -0,0 +1,132 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * GXBB clock tree IDs
+ */
+
+#ifndef __GXBB_CLKC_H
+#define __GXBB_CLKC_H
+
+#define CLKID_SYS_PLL		0
+#define CLKID_HDMI_PLL		2
+#define CLKID_FIXED_PLL		3
+#define CLKID_FCLK_DIV2		4
+#define CLKID_FCLK_DIV3		5
+#define CLKID_FCLK_DIV4		6
+#define CLKID_FCLK_DIV5		7
+#define CLKID_FCLK_DIV7		8
+#define CLKID_GP0_PLL		9
+#define CLKID_CLK81		12
+#define CLKID_MPLL0		13
+#define CLKID_MPLL1		14
+#define CLKID_MPLL2		15
+#define CLKID_DDR		16
+#define CLKID_DOS		17
+#define CLKID_ISA		18
+#define CLKID_PL301		19
+#define CLKID_PERIPHS		20
+#define CLKID_SPICC		21
+#define CLKID_I2C		22
+#define CLKID_SAR_ADC		23
+#define CLKID_SMART_CARD	24
+#define CLKID_RNG0		25
+#define CLKID_UART0		26
+#define CLKID_SDHC		27
+#define CLKID_STREAM		28
+#define CLKID_ASYNC_FIFO	29
+#define CLKID_SDIO		30
+#define CLKID_ABUF		31
+#define CLKID_HIU_IFACE		32
+#define CLKID_ASSIST_MISC	33
+#define CLKID_SPI		34
+#define CLKID_ETH		36
+#define CLKID_I2S_SPDIF		35
+#define CLKID_DEMUX		37
+#define CLKID_AIU_GLUE		38
+#define CLKID_IEC958		39
+#define CLKID_I2S_OUT		40
+#define CLKID_AMCLK		41
+#define CLKID_AIFIFO2		42
+#define CLKID_MIXER		43
+#define CLKID_MIXER_IFACE	44
+#define CLKID_ADC		45
+#define CLKID_BLKMV		46
+#define CLKID_AIU		47
+#define CLKID_UART1		48
+#define CLKID_G2D		49
+#define CLKID_USB0		50
+#define CLKID_USB1		51
+#define CLKID_RESET		52
+#define CLKID_NAND		53
+#define CLKID_DOS_PARSER	54
+#define CLKID_USB		55
+#define CLKID_VDIN1		56
+#define CLKID_AHB_ARB0		57
+#define CLKID_EFUSE		58
+#define CLKID_BOOT_ROM		59
+#define CLKID_AHB_DATA_BUS	60
+#define CLKID_AHB_CTRL_BUS	61
+#define CLKID_HDMI_INTR_SYNC	62
+#define CLKID_HDMI_PCLK		63
+#define CLKID_USB1_DDR_BRIDGE	64
+#define CLKID_USB0_DDR_BRIDGE	65
+#define CLKID_MMC_PCLK		66
+#define CLKID_DVIN		67
+#define CLKID_UART2		68
+#define CLKID_SANA		69
+#define CLKID_VPU_INTR		70
+#define CLKID_SEC_AHB_AHB3_BRIDGE 71
+#define CLKID_CLK81_A53		72
+#define CLKID_VCLK2_VENCI0	73
+#define CLKID_VCLK2_VENCI1	74
+#define CLKID_VCLK2_VENCP0	75
+#define CLKID_VCLK2_VENCP1	76
+#define CLKID_GCLK_VENCI_INT0	77
+#define CLKID_GCLK_VENCI_INT	78
+#define CLKID_DAC_CLK		79
+#define CLKID_AOCLK_GATE	80
+#define CLKID_IEC958_GATE	81
+#define CLKID_ENC480P		82
+#define CLKID_RNG1		83
+#define CLKID_GCLK_VENCI_INT1	84
+#define CLKID_VCLK2_VENCLMCC	85
+#define CLKID_VCLK2_VENCL	86
+#define CLKID_VCLK_OTHER	87
+#define CLKID_EDP		88
+#define CLKID_AO_MEDIA_CPU	89
+#define CLKID_AO_AHB_SRAM	90
+#define CLKID_AO_AHB_BUS	91
+#define CLKID_AO_IFACE		92
+#define CLKID_AO_I2C		93
+#define CLKID_SD_EMMC_A		94
+#define CLKID_SD_EMMC_B		95
+#define CLKID_SD_EMMC_C		96
+#define CLKID_SAR_ADC_CLK	97
+#define CLKID_SAR_ADC_SEL	98
+#define CLKID_MALI_0_SEL	100
+#define CLKID_MALI_0		102
+#define CLKID_MALI_1_SEL	103
+#define CLKID_MALI_1		105
+#define CLKID_MALI		106
+#define CLKID_CTS_AMCLK		107
+#define CLKID_CTS_MCLK_I958	110
+#define CLKID_CTS_I958		113
+#define CLKID_32K_CLK		114
+#define CLKID_SD_EMMC_A_CLK0	119
+#define CLKID_SD_EMMC_B_CLK0	122
+#define CLKID_SD_EMMC_C_CLK0	125
+#define CLKID_VPU_0_SEL		126
+#define CLKID_VPU_0		128
+#define CLKID_VPU_1_SEL		129
+#define CLKID_VPU_1		131
+#define CLKID_VPU		132
+#define CLKID_VAPB_0_SEL	133
+#define CLKID_VAPB_0		135
+#define CLKID_VAPB_1_SEL	136
+#define CLKID_VAPB_1		138
+#define CLKID_VAPB_SEL		139
+#define CLKID_VAPB		140
+#define CLKID_VDEC_1		153
+#define CLKID_VDEC_HEVC		156
+#define CLKID_GEN_CLK		159
+
+#endif /* __GXBB_CLKC_H */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/hi3516cv300-clock.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/hi3516cv300-clock.h
new file mode 100644
index 0000000000000000000000000000000000000000..5ba51b8388fc1f864e90844906629a980c2b3b37
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/hi3516cv300-clock.h
@@ -0,0 +1,48 @@
+/*
+ * Copyright (c) 2016 HiSilicon Technologies Co., Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __DTS_HI3516CV300_CLOCK_H
+#define __DTS_HI3516CV300_CLOCK_H
+
+/* hi3516CV300 core CRG */
+#define HI3516CV300_APB_CLK		0
+#define HI3516CV300_UART0_CLK		1
+#define HI3516CV300_UART1_CLK		2
+#define HI3516CV300_UART2_CLK		3
+#define HI3516CV300_SPI0_CLK		4
+#define HI3516CV300_SPI1_CLK		5
+#define HI3516CV300_FMC_CLK		6
+#define HI3516CV300_MMC0_CLK		7
+#define HI3516CV300_MMC1_CLK		8
+#define HI3516CV300_MMC2_CLK		9
+#define HI3516CV300_MMC3_CLK		10
+#define HI3516CV300_ETH_CLK		11
+#define HI3516CV300_ETH_MACIF_CLK	12
+#define HI3516CV300_DMAC_CLK		13
+#define HI3516CV300_PWM_CLK		14
+#define HI3516CV300_USB2_BUS_CLK	15
+#define HI3516CV300_USB2_OHCI48M_CLK	16
+#define HI3516CV300_USB2_OHCI12M_CLK	17
+#define HI3516CV300_USB2_OTG_UTMI_CLK	18
+#define HI3516CV300_USB2_HST_PHY_CLK	19
+#define HI3516CV300_USB2_UTMI0_CLK	20
+#define HI3516CV300_USB2_PHY_CLK	21
+
+/* hi3516CV300 sysctrl CRG */
+#define HI3516CV300_WDT_CLK		1
+
+#endif	/* __DTS_HI3516CV300_CLOCK_H */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/hi3519-clock.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/hi3519-clock.h
new file mode 100644
index 0000000000000000000000000000000000000000..14f4d2184e5a3a202a6db7c65e778a6489435dc4
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/hi3519-clock.h
@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2015 HiSilicon Technologies Co., Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __DTS_HI3519_CLOCK_H
+#define __DTS_HI3519_CLOCK_H
+
+#define HI3519_FMC_CLK			1
+#define HI3519_SPI0_CLK			2
+#define HI3519_SPI1_CLK			3
+#define HI3519_SPI2_CLK			4
+#define HI3519_UART0_CLK		5
+#define HI3519_UART1_CLK		6
+#define HI3519_UART2_CLK		7
+#define HI3519_UART3_CLK		8
+#define HI3519_UART4_CLK		9
+#define HI3519_PWM_CLK			10
+#define HI3519_DMA_CLK			11
+#define HI3519_IR_CLK			12
+#define HI3519_ETH_PHY_CLK		13
+#define HI3519_ETH_MAC_CLK		14
+#define HI3519_ETH_MACIF_CLK		15
+#define HI3519_USB2_BUS_CLK		16
+#define HI3519_USB2_PORT_CLK		17
+#define HI3519_USB3_CLK			18
+
+#endif	/* __DTS_HI3519_CLOCK_H */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/hi3620-clock.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/hi3620-clock.h
new file mode 100644
index 0000000000000000000000000000000000000000..21b9d0e2eb0cd0e018d9cb531e768ed6e849ccc3
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/hi3620-clock.h
@@ -0,0 +1,157 @@
+/*
+ * Copyright (c) 2012-2013 Hisilicon Limited.
+ * Copyright (c) 2012-2013 Linaro Limited.
+ *
+ * Author: Haojian Zhuang <haojian.zhuang@linaro.org>
+ *	   Xin Li <li.xin@linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ */
+
+#ifndef __DTS_HI3620_CLOCK_H
+#define __DTS_HI3620_CLOCK_H
+
+#define HI3620_NONE_CLOCK	0
+
+/* fixed rate & fixed factor clocks */
+#define HI3620_OSC32K		1
+#define HI3620_OSC26M		2
+#define HI3620_PCLK		3
+#define HI3620_PLL_ARM0		4
+#define HI3620_PLL_ARM1		5
+#define HI3620_PLL_PERI		6
+#define HI3620_PLL_USB		7
+#define HI3620_PLL_HDMI		8
+#define HI3620_PLL_GPU		9
+#define HI3620_RCLK_TCXO	10
+#define HI3620_RCLK_CFGAXI	11
+#define HI3620_RCLK_PICO	12
+
+/* mux clocks */
+#define HI3620_TIMER0_MUX	32
+#define HI3620_TIMER1_MUX	33
+#define HI3620_TIMER2_MUX	34
+#define HI3620_TIMER3_MUX	35
+#define HI3620_TIMER4_MUX	36
+#define HI3620_TIMER5_MUX	37
+#define HI3620_TIMER6_MUX	38
+#define HI3620_TIMER7_MUX	39
+#define HI3620_TIMER8_MUX	40
+#define HI3620_TIMER9_MUX	41
+#define HI3620_UART0_MUX	42
+#define HI3620_UART1_MUX	43
+#define HI3620_UART2_MUX	44
+#define HI3620_UART3_MUX	45
+#define HI3620_UART4_MUX	46
+#define HI3620_SPI0_MUX		47
+#define HI3620_SPI1_MUX		48
+#define HI3620_SPI2_MUX		49
+#define HI3620_SAXI_MUX		50
+#define HI3620_PWM0_MUX		51
+#define HI3620_PWM1_MUX		52
+#define HI3620_SD_MUX		53
+#define HI3620_MMC1_MUX		54
+#define HI3620_MMC1_MUX2	55
+#define HI3620_G2D_MUX		56
+#define HI3620_VENC_MUX		57
+#define HI3620_VDEC_MUX		58
+#define HI3620_VPP_MUX		59
+#define HI3620_EDC0_MUX		60
+#define HI3620_LDI0_MUX		61
+#define HI3620_EDC1_MUX		62
+#define HI3620_LDI1_MUX		63
+#define HI3620_RCLK_HSIC	64
+#define HI3620_MMC2_MUX		65
+#define HI3620_MMC3_MUX		66
+
+/* divider clocks */
+#define HI3620_SHAREAXI_DIV	128
+#define HI3620_CFGAXI_DIV	129
+#define HI3620_SD_DIV		130
+#define HI3620_MMC1_DIV		131
+#define HI3620_HSIC_DIV		132
+#define HI3620_MMC2_DIV		133
+#define HI3620_MMC3_DIV		134
+
+/* gate clocks */
+#define HI3620_TIMERCLK01	160
+#define HI3620_TIMER_RCLK01	161
+#define HI3620_TIMERCLK23	162
+#define HI3620_TIMER_RCLK23	163
+#define HI3620_TIMERCLK45	164
+#define HI3620_TIMERCLK67	165
+#define HI3620_TIMERCLK89	166
+#define HI3620_RTCCLK		167
+#define HI3620_KPC_CLK		168
+#define HI3620_GPIOCLK0		169
+#define HI3620_GPIOCLK1		170
+#define HI3620_GPIOCLK2		171
+#define HI3620_GPIOCLK3		172
+#define HI3620_GPIOCLK4		173
+#define HI3620_GPIOCLK5		174
+#define HI3620_GPIOCLK6		175
+#define HI3620_GPIOCLK7		176
+#define HI3620_GPIOCLK8		177
+#define HI3620_GPIOCLK9		178
+#define HI3620_GPIOCLK10	179
+#define HI3620_GPIOCLK11	180
+#define HI3620_GPIOCLK12	181
+#define HI3620_GPIOCLK13	182
+#define HI3620_GPIOCLK14	183
+#define HI3620_GPIOCLK15	184
+#define HI3620_GPIOCLK16	185
+#define HI3620_GPIOCLK17	186
+#define HI3620_GPIOCLK18	187
+#define HI3620_GPIOCLK19	188
+#define HI3620_GPIOCLK20	189
+#define HI3620_GPIOCLK21	190
+#define HI3620_DPHY0_CLK	191
+#define HI3620_DPHY1_CLK	192
+#define HI3620_DPHY2_CLK	193
+#define HI3620_USBPHY_CLK	194
+#define HI3620_ACP_CLK		195
+#define HI3620_PWMCLK0		196
+#define HI3620_PWMCLK1		197
+#define HI3620_UARTCLK0		198
+#define HI3620_UARTCLK1		199
+#define HI3620_UARTCLK2		200
+#define HI3620_UARTCLK3		201
+#define HI3620_UARTCLK4		202
+#define HI3620_SPICLK0		203
+#define HI3620_SPICLK1		204
+#define HI3620_SPICLK2		205
+#define HI3620_I2CCLK0		206
+#define HI3620_I2CCLK1		207
+#define HI3620_I2CCLK2		208
+#define HI3620_I2CCLK3		209
+#define HI3620_SCI_CLK		210
+#define HI3620_DDRC_PER_CLK	211
+#define HI3620_DMAC_CLK		212
+#define HI3620_USB2DVC_CLK	213
+#define HI3620_SD_CLK		214
+#define HI3620_MMC_CLK1		215
+#define HI3620_MMC_CLK2		216
+#define HI3620_MMC_CLK3		217
+#define HI3620_MCU_CLK		218
+
+#define HI3620_SD_CIUCLK	0
+#define HI3620_MMC_CIUCLK1	1
+#define HI3620_MMC_CIUCLK2	2
+#define HI3620_MMC_CIUCLK3	3
+
+#define HI3620_NR_CLKS		219
+
+#endif	/* __DTS_HI3620_CLOCK_H */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/hi3660-clock.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/hi3660-clock.h
new file mode 100644
index 0000000000000000000000000000000000000000..75d583eb84ddada92cc5078bbeb6c3a5b676a53c
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/hi3660-clock.h
@@ -0,0 +1,218 @@
+/*
+ * Copyright (c) 2016-2017 Linaro Ltd.
+ * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __DTS_HI3660_CLOCK_H
+#define __DTS_HI3660_CLOCK_H
+
+/* fixed rate clocks */
+#define HI3660_CLKIN_SYS		0
+#define HI3660_CLKIN_REF		1
+#define HI3660_CLK_FLL_SRC		2
+#define HI3660_CLK_PPLL0		3
+#define HI3660_CLK_PPLL1		4
+#define HI3660_CLK_PPLL2		5
+#define HI3660_CLK_PPLL3		6
+#define HI3660_CLK_SCPLL		7
+#define HI3660_PCLK			8
+#define HI3660_CLK_UART0_DBG		9
+#define HI3660_CLK_UART6		10
+#define HI3660_OSC32K			11
+#define HI3660_OSC19M			12
+#define HI3660_CLK_480M			13
+#define HI3660_CLK_INV			14
+
+/* clk in crgctrl */
+#define HI3660_FACTOR_UART3		15
+#define HI3660_CLK_FACTOR_MMC		16
+#define HI3660_CLK_GATE_I2C0		17
+#define HI3660_CLK_GATE_I2C1		18
+#define HI3660_CLK_GATE_I2C2		19
+#define HI3660_CLK_GATE_I2C6		20
+#define HI3660_CLK_DIV_SYSBUS		21
+#define HI3660_CLK_DIV_320M		22
+#define HI3660_CLK_DIV_A53		23
+#define HI3660_CLK_GATE_SPI0		24
+#define HI3660_CLK_GATE_SPI2		25
+#define HI3660_PCIEPHY_REF		26
+#define HI3660_CLK_ABB_USB		27
+#define HI3660_HCLK_GATE_SDIO0		28
+#define HI3660_HCLK_GATE_SD		29
+#define HI3660_CLK_GATE_AOMM		30
+#define HI3660_PCLK_GPIO0		31
+#define HI3660_PCLK_GPIO1		32
+#define HI3660_PCLK_GPIO2		33
+#define HI3660_PCLK_GPIO3		34
+#define HI3660_PCLK_GPIO4		35
+#define HI3660_PCLK_GPIO5		36
+#define HI3660_PCLK_GPIO6		37
+#define HI3660_PCLK_GPIO7		38
+#define HI3660_PCLK_GPIO8		39
+#define HI3660_PCLK_GPIO9		40
+#define HI3660_PCLK_GPIO10		41
+#define HI3660_PCLK_GPIO11		42
+#define HI3660_PCLK_GPIO12		43
+#define HI3660_PCLK_GPIO13		44
+#define HI3660_PCLK_GPIO14		45
+#define HI3660_PCLK_GPIO15		46
+#define HI3660_PCLK_GPIO16		47
+#define HI3660_PCLK_GPIO17		48
+#define HI3660_PCLK_GPIO18		49
+#define HI3660_PCLK_GPIO19		50
+#define HI3660_PCLK_GPIO20		51
+#define HI3660_PCLK_GPIO21		52
+#define HI3660_CLK_GATE_SPI3		53
+#define HI3660_CLK_GATE_I2C7		54
+#define HI3660_CLK_GATE_I2C3		55
+#define HI3660_CLK_GATE_SPI1		56
+#define HI3660_CLK_GATE_UART1		57
+#define HI3660_CLK_GATE_UART2		58
+#define HI3660_CLK_GATE_UART4		59
+#define HI3660_CLK_GATE_UART5		60
+#define HI3660_CLK_GATE_I2C4		61
+#define HI3660_CLK_GATE_DMAC		62
+#define HI3660_PCLK_GATE_DSS		63
+#define HI3660_ACLK_GATE_DSS		64
+#define HI3660_CLK_GATE_LDI1		65
+#define HI3660_CLK_GATE_LDI0		66
+#define HI3660_CLK_GATE_VIVOBUS		67
+#define HI3660_CLK_GATE_EDC0		68
+#define HI3660_CLK_GATE_TXDPHY0_CFG	69
+#define HI3660_CLK_GATE_TXDPHY0_REF	70
+#define HI3660_CLK_GATE_TXDPHY1_CFG	71
+#define HI3660_CLK_GATE_TXDPHY1_REF	72
+#define HI3660_ACLK_GATE_USB3OTG	73
+#define HI3660_CLK_GATE_SPI4		74
+#define HI3660_CLK_GATE_SD		75
+#define HI3660_CLK_GATE_SDIO0		76
+#define HI3660_CLK_GATE_UFS_SUBSYS	77
+#define HI3660_PCLK_GATE_DSI0		78
+#define HI3660_PCLK_GATE_DSI1		79
+#define HI3660_ACLK_GATE_PCIE		80
+#define HI3660_PCLK_GATE_PCIE_SYS       81
+#define HI3660_CLK_GATE_PCIEAUX		82
+#define HI3660_PCLK_GATE_PCIE_PHY	83
+#define HI3660_CLK_ANDGT_LDI0		84
+#define HI3660_CLK_ANDGT_LDI1		85
+#define HI3660_CLK_ANDGT_EDC0		86
+#define HI3660_CLK_GATE_UFSPHY_GT	87
+#define HI3660_CLK_ANDGT_MMC		88
+#define HI3660_CLK_ANDGT_SD		89
+#define HI3660_CLK_A53HPM_ANDGT		90
+#define HI3660_CLK_ANDGT_SDIO		91
+#define HI3660_CLK_ANDGT_UART0		92
+#define HI3660_CLK_ANDGT_UART1		93
+#define HI3660_CLK_ANDGT_UARTH		94
+#define HI3660_CLK_ANDGT_SPI		95
+#define HI3660_CLK_VIVOBUS_ANDGT	96
+#define HI3660_CLK_AOMM_ANDGT		97
+#define HI3660_CLK_320M_PLL_GT		98
+#define HI3660_AUTODIV_EMMC0BUS		99
+#define HI3660_AUTODIV_SYSBUS		100
+#define HI3660_CLK_GATE_UFSPHY_CFG	101
+#define HI3660_CLK_GATE_UFSIO_REF	102
+#define HI3660_CLK_MUX_SYSBUS		103
+#define HI3660_CLK_MUX_UART0		104
+#define HI3660_CLK_MUX_UART1		105
+#define HI3660_CLK_MUX_UARTH		106
+#define HI3660_CLK_MUX_SPI		107
+#define HI3660_CLK_MUX_I2C		108
+#define HI3660_CLK_MUX_MMC_PLL		109
+#define HI3660_CLK_MUX_LDI1		110
+#define HI3660_CLK_MUX_LDI0		111
+#define HI3660_CLK_MUX_SD_PLL		112
+#define HI3660_CLK_MUX_SD_SYS		113
+#define HI3660_CLK_MUX_EDC0		114
+#define HI3660_CLK_MUX_SDIO_SYS		115
+#define HI3660_CLK_MUX_SDIO_PLL		116
+#define HI3660_CLK_MUX_VIVOBUS		117
+#define HI3660_CLK_MUX_A53HPM		118
+#define HI3660_CLK_MUX_320M		119
+#define HI3660_CLK_MUX_IOPERI		120
+#define HI3660_CLK_DIV_UART0		121
+#define HI3660_CLK_DIV_UART1		122
+#define HI3660_CLK_DIV_UARTH		123
+#define HI3660_CLK_DIV_MMC		124
+#define HI3660_CLK_DIV_SD		125
+#define HI3660_CLK_DIV_EDC0		126
+#define HI3660_CLK_DIV_LDI0		127
+#define HI3660_CLK_DIV_SDIO		128
+#define HI3660_CLK_DIV_LDI1		129
+#define HI3660_CLK_DIV_SPI		130
+#define HI3660_CLK_DIV_VIVOBUS		131
+#define HI3660_CLK_DIV_I2C		132
+#define HI3660_CLK_DIV_UFSPHY		133
+#define HI3660_CLK_DIV_CFGBUS		134
+#define HI3660_CLK_DIV_MMC0BUS		135
+#define HI3660_CLK_DIV_MMC1BUS		136
+#define HI3660_CLK_DIV_UFSPERI		137
+#define HI3660_CLK_DIV_AOMM		138
+#define HI3660_CLK_DIV_IOPERI		139
+#define HI3660_VENC_VOLT_HOLD		140
+#define HI3660_PERI_VOLT_HOLD		141
+#define HI3660_CLK_GATE_VENC		142
+#define HI3660_CLK_GATE_VDEC		143
+#define HI3660_CLK_ANDGT_VENC		144
+#define HI3660_CLK_ANDGT_VDEC		145
+#define HI3660_CLK_MUX_VENC		146
+#define HI3660_CLK_MUX_VDEC		147
+#define HI3660_CLK_DIV_VENC		148
+#define HI3660_CLK_DIV_VDEC		149
+#define HI3660_CLK_FAC_ISP_SNCLK	150
+#define HI3660_CLK_GATE_ISP_SNCLK0	151
+#define HI3660_CLK_GATE_ISP_SNCLK1	152
+#define HI3660_CLK_GATE_ISP_SNCLK2	153
+#define HI3660_CLK_ANGT_ISP_SNCLK	154
+#define HI3660_CLK_MUX_ISP_SNCLK	155
+#define HI3660_CLK_DIV_ISP_SNCLK	156
+
+/* clk in pmuctrl */
+#define HI3660_GATE_ABB_192		0
+
+/* clk in pctrl */
+#define HI3660_GATE_UFS_TCXO_EN		0
+#define HI3660_GATE_USB_TCXO_EN		1
+
+/* clk in sctrl */
+#define HI3660_PCLK_AO_GPIO0		0
+#define HI3660_PCLK_AO_GPIO1		1
+#define HI3660_PCLK_AO_GPIO2		2
+#define HI3660_PCLK_AO_GPIO3		3
+#define HI3660_PCLK_AO_GPIO4		4
+#define HI3660_PCLK_AO_GPIO5		5
+#define HI3660_PCLK_AO_GPIO6		6
+#define HI3660_PCLK_GATE_MMBUF		7
+#define HI3660_CLK_GATE_DSS_AXI_MM	8
+#define HI3660_PCLK_MMBUF_ANDGT		9
+#define HI3660_CLK_MMBUF_PLL_ANDGT	10
+#define HI3660_CLK_FLL_MMBUF_ANDGT	11
+#define HI3660_CLK_SYS_MMBUF_ANDGT	12
+#define HI3660_CLK_GATE_PCIEPHY_GT	13
+#define HI3660_ACLK_MUX_MMBUF		14
+#define HI3660_CLK_SW_MMBUF		15
+#define HI3660_CLK_DIV_AOBUS		16
+#define HI3660_PCLK_DIV_MMBUF		17
+#define HI3660_ACLK_DIV_MMBUF		18
+#define HI3660_CLK_DIV_PCIEPHY		19
+
+/* clk in iomcu */
+#define HI3660_CLK_I2C0_IOMCU		0
+#define HI3660_CLK_I2C1_IOMCU		1
+#define HI3660_CLK_I2C2_IOMCU		2
+#define HI3660_CLK_I2C6_IOMCU		3
+#define HI3660_CLK_IOMCU_PERI0		4
+
+/* clk in stub clock */
+#define HI3660_CLK_STUB_CLUSTER0	0
+#define HI3660_CLK_STUB_CLUSTER1	1
+#define HI3660_CLK_STUB_GPU		2
+#define HI3660_CLK_STUB_DDR		3
+#define HI3660_CLK_STUB_NUM		4
+
+#endif	/* __DTS_HI3660_CLOCK_H */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/hi6220-clock.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/hi6220-clock.h
new file mode 100644
index 0000000000000000000000000000000000000000..409cc02cd844c5f4760164795671ba61e6ef5e13
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/hi6220-clock.h
@@ -0,0 +1,181 @@
+/*
+ * Copyright (c) 2015 Hisilicon Limited.
+ *
+ * Author: Bintian Wang <bintian.wang@huawei.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_HI6220_H
+#define __DT_BINDINGS_CLOCK_HI6220_H
+
+/* clk in Hi6220 AO (always on) controller */
+#define HI6220_NONE_CLOCK	0
+
+/* fixed rate clocks */
+#define HI6220_REF32K		1
+#define HI6220_CLK_TCXO		2
+#define HI6220_MMC1_PAD		3
+#define HI6220_MMC2_PAD		4
+#define HI6220_MMC0_PAD		5
+#define HI6220_PLL_BBP		6
+#define HI6220_PLL_GPU		7
+#define HI6220_PLL1_DDR		8
+#define HI6220_PLL_SYS		9
+#define HI6220_PLL_SYS_MEDIA	10
+#define HI6220_DDR_SRC		11
+#define HI6220_PLL_MEDIA	12
+#define HI6220_PLL_DDR		13
+
+/* fixed factor clocks */
+#define HI6220_300M		14
+#define HI6220_150M		15
+#define HI6220_PICOPHY_SRC	16
+#define HI6220_MMC0_SRC_SEL	17
+#define HI6220_MMC1_SRC_SEL	18
+#define HI6220_MMC2_SRC_SEL	19
+#define HI6220_VPU_CODEC	20
+#define HI6220_MMC0_SMP		21
+#define HI6220_MMC1_SMP		22
+#define HI6220_MMC2_SMP		23
+
+/* gate clocks */
+#define HI6220_WDT0_PCLK	24
+#define HI6220_WDT1_PCLK	25
+#define HI6220_WDT2_PCLK	26
+#define HI6220_TIMER0_PCLK	27
+#define HI6220_TIMER1_PCLK	28
+#define HI6220_TIMER2_PCLK	29
+#define HI6220_TIMER3_PCLK	30
+#define HI6220_TIMER4_PCLK	31
+#define HI6220_TIMER5_PCLK	32
+#define HI6220_TIMER6_PCLK	33
+#define HI6220_TIMER7_PCLK	34
+#define HI6220_TIMER8_PCLK	35
+#define HI6220_UART0_PCLK	36
+#define HI6220_RTC0_PCLK	37
+#define HI6220_RTC1_PCLK	38
+#define HI6220_AO_NR_CLKS	39
+
+/* clk in Hi6220 systrl */
+/* gate clock */
+#define HI6220_MMC0_CLK		1
+#define HI6220_MMC0_CIUCLK	2
+#define HI6220_MMC1_CLK		3
+#define HI6220_MMC1_CIUCLK	4
+#define HI6220_MMC2_CLK		5
+#define HI6220_MMC2_CIUCLK	6
+#define HI6220_USBOTG_HCLK	7
+#define HI6220_CLK_PICOPHY	8
+#define HI6220_HIFI		9
+#define HI6220_DACODEC_PCLK	10
+#define HI6220_EDMAC_ACLK	11
+#define HI6220_CS_ATB		12
+#define HI6220_I2C0_CLK		13
+#define HI6220_I2C1_CLK		14
+#define HI6220_I2C2_CLK		15
+#define HI6220_I2C3_CLK		16
+#define HI6220_UART1_PCLK	17
+#define HI6220_UART2_PCLK	18
+#define HI6220_UART3_PCLK	19
+#define HI6220_UART4_PCLK	20
+#define HI6220_SPI_CLK		21
+#define HI6220_TSENSOR_CLK	22
+#define HI6220_MMU_CLK		23
+#define HI6220_HIFI_SEL		24
+#define HI6220_MMC0_SYSPLL	25
+#define HI6220_MMC1_SYSPLL	26
+#define HI6220_MMC2_SYSPLL	27
+#define HI6220_MMC0_SEL		28
+#define HI6220_MMC1_SEL		29
+#define HI6220_BBPPLL_SEL	30
+#define HI6220_MEDIA_PLL_SRC	31
+#define HI6220_MMC2_SEL		32
+#define HI6220_CS_ATB_SYSPLL	33
+
+/* mux clocks */
+#define HI6220_MMC0_SRC		34
+#define HI6220_MMC0_SMP_IN	35
+#define HI6220_MMC1_SRC		36
+#define HI6220_MMC1_SMP_IN	37
+#define HI6220_MMC2_SRC		38
+#define HI6220_MMC2_SMP_IN	39
+#define HI6220_HIFI_SRC		40
+#define HI6220_UART1_SRC	41
+#define HI6220_UART2_SRC	42
+#define HI6220_UART3_SRC	43
+#define HI6220_UART4_SRC	44
+#define HI6220_MMC0_MUX0	45
+#define HI6220_MMC1_MUX0	46
+#define HI6220_MMC2_MUX0	47
+#define HI6220_MMC0_MUX1	48
+#define HI6220_MMC1_MUX1	49
+#define HI6220_MMC2_MUX1	50
+
+/* divider clocks */
+#define HI6220_CLK_BUS		51
+#define HI6220_MMC0_DIV		52
+#define HI6220_MMC1_DIV		53
+#define HI6220_MMC2_DIV		54
+#define HI6220_HIFI_DIV		55
+#define HI6220_BBPPLL0_DIV	56
+#define HI6220_CS_DAPB		57
+#define HI6220_CS_ATB_DIV	58
+
+/* gate clock */
+#define HI6220_DAPB_CLK		59
+
+#define HI6220_SYS_NR_CLKS	60
+
+/* clk in Hi6220 media controller */
+/* gate clocks */
+#define HI6220_DSI_PCLK		1
+#define HI6220_G3D_PCLK		2
+#define HI6220_ACLK_CODEC_VPU	3
+#define HI6220_ISP_SCLK		4
+#define HI6220_ADE_CORE		5
+#define HI6220_MED_MMU		6
+#define HI6220_CFG_CSI4PHY	7
+#define HI6220_CFG_CSI2PHY	8
+#define HI6220_ISP_SCLK_GATE	9
+#define HI6220_ISP_SCLK_GATE1	10
+#define HI6220_ADE_CORE_GATE	11
+#define HI6220_CODEC_VPU_GATE	12
+#define HI6220_MED_SYSPLL	13
+
+/* mux clocks */
+#define HI6220_1440_1200	14
+#define HI6220_1000_1200	15
+#define HI6220_1000_1440	16
+
+/* divider clocks */
+#define HI6220_CODEC_JPEG	17
+#define HI6220_ISP_SCLK_SRC	18
+#define HI6220_ISP_SCLK1	19
+#define HI6220_ADE_CORE_SRC	20
+#define HI6220_ADE_PIX_SRC	21
+#define HI6220_G3D_CLK		22
+#define HI6220_CODEC_VPU_SRC	23
+
+#define HI6220_MEDIA_NR_CLKS	24
+
+/* clk in Hi6220 power controller */
+/* gate clocks */
+#define HI6220_PLL_GPU_GATE	1
+#define HI6220_PLL1_DDR_GATE	2
+#define HI6220_PLL_DDR_GATE	3
+#define HI6220_PLL_MEDIA_GATE	4
+#define HI6220_PLL0_BBP_GATE	5
+
+/* divider clocks */
+#define HI6220_DDRC_SRC		6
+#define HI6220_DDRC_AXI1	7
+
+#define HI6220_POWER_NR_CLKS	8
+
+/* clk in Hi6220 acpu sctrl */
+#define HI6220_ACPU_SFT_AT_S		0
+
+#endif
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/hip04-clock.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/hip04-clock.h
new file mode 100644
index 0000000000000000000000000000000000000000..695e61cd152380a0c3c3e9d27a0705e1f5107d66
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/hip04-clock.h
@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2013-2014 Hisilicon Limited.
+ * Copyright (c) 2013-2014 Linaro Limited.
+ *
+ * Author: Haojian Zhuang <haojian.zhuang@linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ */
+
+#ifndef __DTS_HIP04_CLOCK_H
+#define __DTS_HIP04_CLOCK_H
+
+#define HIP04_NONE_CLOCK	0
+
+/* fixed rate & fixed factor clocks */
+#define HIP04_OSC50M		1
+#define HIP04_CLK_50M		2
+#define HIP04_CLK_168M		3
+
+#define HIP04_NR_CLKS		64
+
+#endif	/* __DTS_HIP04_CLOCK_H */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/histb-clock.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/histb-clock.h
new file mode 100644
index 0000000000000000000000000000000000000000..136de24733bea37fe1cbce30740a804acbf884b3
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/histb-clock.h
@@ -0,0 +1,82 @@
+/*
+ * Copyright (c) 2016 HiSilicon Technologies Co., Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __DTS_HISTB_CLOCK_H
+#define __DTS_HISTB_CLOCK_H
+
+/* clocks provided by core CRG */
+#define HISTB_OSC_CLK			0
+#define HISTB_APB_CLK			1
+#define HISTB_AHB_CLK			2
+#define HISTB_UART1_CLK			3
+#define HISTB_UART2_CLK			4
+#define HISTB_UART3_CLK			5
+#define HISTB_I2C0_CLK			6
+#define HISTB_I2C1_CLK			7
+#define HISTB_I2C2_CLK			8
+#define HISTB_I2C3_CLK			9
+#define HISTB_I2C4_CLK			10
+#define HISTB_I2C5_CLK			11
+#define HISTB_SPI0_CLK			12
+#define HISTB_SPI1_CLK			13
+#define HISTB_SPI2_CLK			14
+#define HISTB_SCI_CLK			15
+#define HISTB_FMC_CLK			16
+#define HISTB_MMC_BIU_CLK		17
+#define HISTB_MMC_CIU_CLK		18
+#define HISTB_MMC_DRV_CLK		19
+#define HISTB_MMC_SAMPLE_CLK		20
+#define HISTB_SDIO0_BIU_CLK		21
+#define HISTB_SDIO0_CIU_CLK		22
+#define HISTB_SDIO0_DRV_CLK		23
+#define HISTB_SDIO0_SAMPLE_CLK		24
+#define HISTB_PCIE_AUX_CLK		25
+#define HISTB_PCIE_PIPE_CLK		26
+#define HISTB_PCIE_SYS_CLK		27
+#define HISTB_PCIE_BUS_CLK		28
+#define HISTB_ETH0_MAC_CLK		29
+#define HISTB_ETH0_MACIF_CLK		30
+#define HISTB_ETH1_MAC_CLK		31
+#define HISTB_ETH1_MACIF_CLK		32
+#define HISTB_COMBPHY1_CLK		33
+#define HISTB_USB2_BUS_CLK		34
+#define HISTB_USB2_PHY_CLK		35
+#define HISTB_USB2_UTMI_CLK		36
+#define HISTB_USB2_12M_CLK		37
+#define HISTB_USB2_48M_CLK		38
+#define HISTB_USB2_OTG_UTMI_CLK		39
+#define HISTB_USB2_PHY1_REF_CLK		40
+#define HISTB_USB2_PHY2_REF_CLK		41
+#define HISTB_COMBPHY0_CLK		42
+#define HISTB_USB3_BUS_CLK		43
+#define HISTB_USB3_UTMI_CLK		44
+#define HISTB_USB3_PIPE_CLK		45
+#define HISTB_USB3_SUSPEND_CLK		46
+#define HISTB_USB3_BUS_CLK1		47
+#define HISTB_USB3_UTMI_CLK1		48
+#define HISTB_USB3_PIPE_CLK1		49
+#define HISTB_USB3_SUSPEND_CLK1		50
+
+/* clocks provided by mcu CRG */
+#define HISTB_MCE_CLK			1
+#define HISTB_IR_CLK			2
+#define HISTB_TIMER01_CLK		3
+#define HISTB_LEDC_CLK			4
+#define HISTB_UART0_CLK			5
+#define HISTB_LSADC_CLK			6
+
+#endif	/* __DTS_HISTB_CLOCK_H */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/hix5hd2-clock.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/hix5hd2-clock.h
new file mode 100644
index 0000000000000000000000000000000000000000..fd29c174ba632114ff720a4a885d5b3beb403139
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/hix5hd2-clock.h
@@ -0,0 +1,85 @@
+/*
+ * Copyright (c) 2014 Linaro Ltd.
+ * Copyright (c) 2014 Hisilicon Limited.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ */
+
+#ifndef __DTS_HIX5HD2_CLOCK_H
+#define __DTS_HIX5HD2_CLOCK_H
+
+/* fixed rate */
+#define HIX5HD2_FIXED_1200M		1
+#define HIX5HD2_FIXED_400M		2
+#define HIX5HD2_FIXED_48M		3
+#define HIX5HD2_FIXED_24M		4
+#define HIX5HD2_FIXED_600M		5
+#define HIX5HD2_FIXED_300M		6
+#define HIX5HD2_FIXED_75M		7
+#define HIX5HD2_FIXED_200M		8
+#define HIX5HD2_FIXED_100M		9
+#define HIX5HD2_FIXED_40M		10
+#define HIX5HD2_FIXED_150M		11
+#define HIX5HD2_FIXED_1728M		12
+#define HIX5HD2_FIXED_28P8M		13
+#define HIX5HD2_FIXED_432M		14
+#define HIX5HD2_FIXED_345P6M		15
+#define HIX5HD2_FIXED_288M		16
+#define HIX5HD2_FIXED_60M		17
+#define HIX5HD2_FIXED_750M		18
+#define HIX5HD2_FIXED_500M		19
+#define HIX5HD2_FIXED_54M		20
+#define HIX5HD2_FIXED_27M		21
+#define HIX5HD2_FIXED_1500M		22
+#define HIX5HD2_FIXED_375M		23
+#define HIX5HD2_FIXED_187M		24
+#define HIX5HD2_FIXED_250M		25
+#define HIX5HD2_FIXED_125M		26
+#define HIX5HD2_FIXED_2P02M		27
+#define HIX5HD2_FIXED_50M		28
+#define HIX5HD2_FIXED_25M		29
+#define HIX5HD2_FIXED_83M		30
+
+/* mux clocks */
+#define HIX5HD2_SFC_MUX			64
+#define HIX5HD2_MMC_MUX			65
+#define HIX5HD2_FEPHY_MUX		66
+#define HIX5HD2_SD_MUX			67
+
+/* gate clocks */
+#define HIX5HD2_SFC_RST			128
+#define HIX5HD2_SFC_CLK			129
+#define HIX5HD2_MMC_CIU_CLK		130
+#define HIX5HD2_MMC_BIU_CLK		131
+#define HIX5HD2_MMC_CIU_RST		132
+#define HIX5HD2_FWD_BUS_CLK		133
+#define HIX5HD2_FWD_SYS_CLK		134
+#define HIX5HD2_MAC0_PHY_CLK		135
+#define HIX5HD2_SD_CIU_CLK		136
+#define HIX5HD2_SD_BIU_CLK		137
+#define HIX5HD2_SD_CIU_RST		138
+#define HIX5HD2_WDG0_CLK		139
+#define HIX5HD2_WDG0_RST		140
+#define HIX5HD2_I2C0_CLK		141
+#define HIX5HD2_I2C0_RST		142
+#define HIX5HD2_I2C1_CLK		143
+#define HIX5HD2_I2C1_RST		144
+#define HIX5HD2_I2C2_CLK		145
+#define HIX5HD2_I2C2_RST		146
+#define HIX5HD2_I2C3_CLK		147
+#define HIX5HD2_I2C3_RST		148
+#define HIX5HD2_I2C4_CLK		149
+#define HIX5HD2_I2C4_RST		150
+#define HIX5HD2_I2C5_CLK		151
+#define HIX5HD2_I2C5_RST		152
+
+/* complex */
+#define HIX5HD2_MAC0_CLK		192
+#define HIX5HD2_MAC1_CLK		193
+#define HIX5HD2_SATA_CLK		194
+#define HIX5HD2_USB_CLK			195
+
+#define HIX5HD2_NR_CLKS			256
+#endif	/* __DTS_HIX5HD2_CLOCK_H */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/imx1-clock.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/imx1-clock.h
new file mode 100644
index 0000000000000000000000000000000000000000..607bf01a31dd52ca09e6e379cf2b286b42b6a0a0
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/imx1-clock.h
@@ -0,0 +1,40 @@
+/*
+ * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_IMX1_H
+#define __DT_BINDINGS_CLOCK_IMX1_H
+
+#define IMX1_CLK_DUMMY		0
+#define IMX1_CLK_CLK32		1
+#define IMX1_CLK_CLK16M_EXT	2
+#define IMX1_CLK_CLK16M		3
+#define IMX1_CLK_CLK32_PREMULT	4
+#define IMX1_CLK_PREM		5
+#define IMX1_CLK_MPLL		6
+#define IMX1_CLK_MPLL_GATE	7
+#define IMX1_CLK_SPLL		8
+#define IMX1_CLK_SPLL_GATE	9
+#define IMX1_CLK_MCU		10
+#define IMX1_CLK_FCLK		11
+#define IMX1_CLK_HCLK		12
+#define IMX1_CLK_CLK48M		13
+#define IMX1_CLK_PER1		14
+#define IMX1_CLK_PER2		15
+#define IMX1_CLK_PER3		16
+#define IMX1_CLK_CLKO		17
+#define IMX1_CLK_UART3_GATE	18
+#define IMX1_CLK_SSI2_GATE	19
+#define IMX1_CLK_BROM_GATE	20
+#define IMX1_CLK_DMA_GATE	21
+#define IMX1_CLK_CSI_GATE	22
+#define IMX1_CLK_MMA_GATE	23
+#define IMX1_CLK_USBD_GATE	24
+#define IMX1_CLK_MAX		25
+
+#endif
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/imx21-clock.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/imx21-clock.h
new file mode 100644
index 0000000000000000000000000000000000000000..b13596cf51b22b49d090dd98a01654fdb4b4f671
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/imx21-clock.h
@@ -0,0 +1,80 @@
+/*
+ * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_IMX21_H
+#define __DT_BINDINGS_CLOCK_IMX21_H
+
+#define IMX21_CLK_DUMMY			0
+#define IMX21_CLK_CKIL			1
+#define IMX21_CLK_CKIH			2
+#define IMX21_CLK_FPM			3
+#define IMX21_CLK_CKIH_DIV1P5		4
+#define IMX21_CLK_MPLL_GATE		5
+#define IMX21_CLK_SPLL_GATE		6
+#define IMX21_CLK_FPM_GATE		7
+#define IMX21_CLK_CKIH_GATE		8
+#define IMX21_CLK_MPLL_OSC_SEL		9
+#define IMX21_CLK_IPG			10
+#define IMX21_CLK_HCLK			11
+#define IMX21_CLK_MPLL_SEL		12
+#define IMX21_CLK_SPLL_SEL		13
+#define IMX21_CLK_SSI1_SEL		14
+#define IMX21_CLK_SSI2_SEL		15
+#define IMX21_CLK_USB_DIV		16
+#define IMX21_CLK_FCLK			17
+#define IMX21_CLK_MPLL			18
+#define IMX21_CLK_SPLL			19
+#define IMX21_CLK_NFC_DIV		20
+#define IMX21_CLK_SSI1_DIV		21
+#define IMX21_CLK_SSI2_DIV		22
+#define IMX21_CLK_PER1			23
+#define IMX21_CLK_PER2			24
+#define IMX21_CLK_PER3			25
+#define IMX21_CLK_PER4			26
+#define IMX21_CLK_UART1_IPG_GATE	27
+#define IMX21_CLK_UART2_IPG_GATE	28
+#define IMX21_CLK_UART3_IPG_GATE	29
+#define IMX21_CLK_UART4_IPG_GATE	30
+#define IMX21_CLK_CSPI1_IPG_GATE	31
+#define IMX21_CLK_CSPI2_IPG_GATE	32
+#define IMX21_CLK_SSI1_GATE		33
+#define IMX21_CLK_SSI2_GATE		34
+#define IMX21_CLK_SDHC1_IPG_GATE	35
+#define IMX21_CLK_SDHC2_IPG_GATE	36
+#define IMX21_CLK_GPIO_GATE		37
+#define IMX21_CLK_I2C_GATE		38
+#define IMX21_CLK_DMA_GATE		39
+#define IMX21_CLK_USB_GATE		40
+#define IMX21_CLK_EMMA_GATE		41
+#define IMX21_CLK_SSI2_BAUD_GATE	42
+#define IMX21_CLK_SSI1_BAUD_GATE	43
+#define IMX21_CLK_LCDC_IPG_GATE		44
+#define IMX21_CLK_NFC_GATE		45
+#define IMX21_CLK_LCDC_HCLK_GATE	46
+#define IMX21_CLK_PER4_GATE		47
+#define IMX21_CLK_BMI_GATE		48
+#define IMX21_CLK_USB_HCLK_GATE		49
+#define IMX21_CLK_SLCDC_GATE		50
+#define IMX21_CLK_SLCDC_HCLK_GATE	51
+#define IMX21_CLK_EMMA_HCLK_GATE	52
+#define IMX21_CLK_BROM_GATE		53
+#define IMX21_CLK_DMA_HCLK_GATE		54
+#define IMX21_CLK_CSI_HCLK_GATE		55
+#define IMX21_CLK_CSPI3_IPG_GATE	56
+#define IMX21_CLK_WDOG_GATE		57
+#define IMX21_CLK_GPT1_IPG_GATE		58
+#define IMX21_CLK_GPT2_IPG_GATE		59
+#define IMX21_CLK_GPT3_IPG_GATE		60
+#define IMX21_CLK_PWM_IPG_GATE		61
+#define IMX21_CLK_RTC_GATE		62
+#define IMX21_CLK_KPP_GATE		63
+#define IMX21_CLK_OWIRE_GATE		64
+#define IMX21_CLK_MAX			65
+
+#endif
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/imx27-clock.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/imx27-clock.h
new file mode 100644
index 0000000000000000000000000000000000000000..148b053e54ec7c90a6b6d321a2805d417f18010d
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/imx27-clock.h
@@ -0,0 +1,108 @@
+/*
+ * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_IMX27_H
+#define __DT_BINDINGS_CLOCK_IMX27_H
+
+#define IMX27_CLK_DUMMY			0
+#define IMX27_CLK_CKIH			1
+#define IMX27_CLK_CKIL			2
+#define IMX27_CLK_MPLL			3
+#define IMX27_CLK_SPLL			4
+#define IMX27_CLK_MPLL_MAIN2		5
+#define IMX27_CLK_AHB			6
+#define IMX27_CLK_IPG			7
+#define IMX27_CLK_NFC_DIV		8
+#define IMX27_CLK_PER1_DIV		9
+#define IMX27_CLK_PER2_DIV		10
+#define IMX27_CLK_PER3_DIV		11
+#define IMX27_CLK_PER4_DIV		12
+#define IMX27_CLK_VPU_SEL		13
+#define IMX27_CLK_VPU_DIV		14
+#define IMX27_CLK_USB_DIV		15
+#define IMX27_CLK_CPU_SEL		16
+#define IMX27_CLK_CLKO_SEL		17
+#define IMX27_CLK_CPU_DIV		18
+#define IMX27_CLK_CLKO_DIV		19
+#define IMX27_CLK_SSI1_SEL		20
+#define IMX27_CLK_SSI2_SEL		21
+#define IMX27_CLK_SSI1_DIV		22
+#define IMX27_CLK_SSI2_DIV		23
+#define IMX27_CLK_CLKO_EN		24
+#define IMX27_CLK_SSI2_IPG_GATE		25
+#define IMX27_CLK_SSI1_IPG_GATE		26
+#define IMX27_CLK_SLCDC_IPG_GATE	27
+#define IMX27_CLK_SDHC3_IPG_GATE	28
+#define IMX27_CLK_SDHC2_IPG_GATE	29
+#define IMX27_CLK_SDHC1_IPG_GATE	30
+#define IMX27_CLK_SCC_IPG_GATE		31
+#define IMX27_CLK_SAHARA_IPG_GATE	32
+#define IMX27_CLK_RTC_IPG_GATE		33
+#define IMX27_CLK_PWM_IPG_GATE		34
+#define IMX27_CLK_OWIRE_IPG_GATE	35
+#define IMX27_CLK_LCDC_IPG_GATE		36
+#define IMX27_CLK_KPP_IPG_GATE		37
+#define IMX27_CLK_IIM_IPG_GATE		38
+#define IMX27_CLK_I2C2_IPG_GATE		39
+#define IMX27_CLK_I2C1_IPG_GATE		40
+#define IMX27_CLK_GPT6_IPG_GATE		41
+#define IMX27_CLK_GPT5_IPG_GATE		42
+#define IMX27_CLK_GPT4_IPG_GATE		43
+#define IMX27_CLK_GPT3_IPG_GATE		44
+#define IMX27_CLK_GPT2_IPG_GATE		45
+#define IMX27_CLK_GPT1_IPG_GATE		46
+#define IMX27_CLK_GPIO_IPG_GATE		47
+#define IMX27_CLK_FEC_IPG_GATE		48
+#define IMX27_CLK_EMMA_IPG_GATE		49
+#define IMX27_CLK_DMA_IPG_GATE		50
+#define IMX27_CLK_CSPI3_IPG_GATE	51
+#define IMX27_CLK_CSPI2_IPG_GATE	52
+#define IMX27_CLK_CSPI1_IPG_GATE	53
+#define IMX27_CLK_NFC_BAUD_GATE		54
+#define IMX27_CLK_SSI2_BAUD_GATE	55
+#define IMX27_CLK_SSI1_BAUD_GATE	56
+#define IMX27_CLK_VPU_BAUD_GATE		57
+#define IMX27_CLK_PER4_GATE		58
+#define IMX27_CLK_PER3_GATE		59
+#define IMX27_CLK_PER2_GATE		60
+#define IMX27_CLK_PER1_GATE		61
+#define IMX27_CLK_USB_AHB_GATE		62
+#define IMX27_CLK_SLCDC_AHB_GATE	63
+#define IMX27_CLK_SAHARA_AHB_GATE	64
+#define IMX27_CLK_LCDC_AHB_GATE		65
+#define IMX27_CLK_VPU_AHB_GATE		66
+#define IMX27_CLK_FEC_AHB_GATE		67
+#define IMX27_CLK_EMMA_AHB_GATE		68
+#define IMX27_CLK_EMI_AHB_GATE		69
+#define IMX27_CLK_DMA_AHB_GATE		70
+#define IMX27_CLK_CSI_AHB_GATE		71
+#define IMX27_CLK_BROM_AHB_GATE		72
+#define IMX27_CLK_ATA_AHB_GATE		73
+#define IMX27_CLK_WDOG_IPG_GATE		74
+#define IMX27_CLK_USB_IPG_GATE		75
+#define IMX27_CLK_UART6_IPG_GATE	76
+#define IMX27_CLK_UART5_IPG_GATE	77
+#define IMX27_CLK_UART4_IPG_GATE	78
+#define IMX27_CLK_UART3_IPG_GATE	79
+#define IMX27_CLK_UART2_IPG_GATE	80
+#define IMX27_CLK_UART1_IPG_GATE	81
+#define IMX27_CLK_CKIH_DIV1P5		82
+#define IMX27_CLK_FPM			83
+#define IMX27_CLK_MPLL_OSC_SEL		84
+#define IMX27_CLK_MPLL_SEL		85
+#define IMX27_CLK_SPLL_GATE		86
+#define IMX27_CLK_MSHC_DIV		87
+#define IMX27_CLK_RTIC_IPG_GATE		88
+#define IMX27_CLK_MSHC_IPG_GATE		89
+#define IMX27_CLK_RTIC_AHB_GATE		90
+#define IMX27_CLK_MSHC_BAUD_GATE	91
+#define IMX27_CLK_CKIH_GATE		92
+#define IMX27_CLK_MAX			93
+
+#endif
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/imx5-clock.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/imx5-clock.h
new file mode 100644
index 0000000000000000000000000000000000000000..d382fc71aa837a72da9381519e13dcce4a4f6f0f
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/imx5-clock.h
@@ -0,0 +1,219 @@
+/*
+ * Copyright 2013 Lucas Stach, Pengutronix <l.stach@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_IMX5_H
+#define __DT_BINDINGS_CLOCK_IMX5_H
+
+#define IMX5_CLK_DUMMY			0
+#define IMX5_CLK_CKIL			1
+#define IMX5_CLK_OSC			2
+#define IMX5_CLK_CKIH1			3
+#define IMX5_CLK_CKIH2			4
+#define IMX5_CLK_AHB			5
+#define IMX5_CLK_IPG			6
+#define IMX5_CLK_AXI_A			7
+#define IMX5_CLK_AXI_B			8
+#define IMX5_CLK_UART_PRED		9
+#define IMX5_CLK_UART_ROOT		10
+#define IMX5_CLK_ESDHC_A_PRED		11
+#define IMX5_CLK_ESDHC_B_PRED		12
+#define IMX5_CLK_ESDHC_C_SEL		13
+#define IMX5_CLK_ESDHC_D_SEL		14
+#define IMX5_CLK_EMI_SEL		15
+#define IMX5_CLK_EMI_SLOW_PODF		16
+#define IMX5_CLK_NFC_PODF		17
+#define IMX5_CLK_ECSPI_PRED		18
+#define IMX5_CLK_ECSPI_PODF		19
+#define IMX5_CLK_USBOH3_PRED		20
+#define IMX5_CLK_USBOH3_PODF		21
+#define IMX5_CLK_USB_PHY_PRED		22
+#define IMX5_CLK_USB_PHY_PODF		23
+#define IMX5_CLK_CPU_PODF		24
+#define IMX5_CLK_DI_PRED		25
+#define IMX5_CLK_TVE_SEL		27
+#define IMX5_CLK_UART1_IPG_GATE		28
+#define IMX5_CLK_UART1_PER_GATE		29
+#define IMX5_CLK_UART2_IPG_GATE		30
+#define IMX5_CLK_UART2_PER_GATE		31
+#define IMX5_CLK_UART3_IPG_GATE		32
+#define IMX5_CLK_UART3_PER_GATE		33
+#define IMX5_CLK_I2C1_GATE		34
+#define IMX5_CLK_I2C2_GATE		35
+#define IMX5_CLK_GPT_IPG_GATE		36
+#define IMX5_CLK_PWM1_IPG_GATE		37
+#define IMX5_CLK_PWM1_HF_GATE		38
+#define IMX5_CLK_PWM2_IPG_GATE		39
+#define IMX5_CLK_PWM2_HF_GATE		40
+#define IMX5_CLK_GPT_HF_GATE		41
+#define IMX5_CLK_FEC_GATE		42
+#define IMX5_CLK_USBOH3_PER_GATE	43
+#define IMX5_CLK_ESDHC1_IPG_GATE	44
+#define IMX5_CLK_ESDHC2_IPG_GATE	45
+#define IMX5_CLK_ESDHC3_IPG_GATE	46
+#define IMX5_CLK_ESDHC4_IPG_GATE	47
+#define IMX5_CLK_SSI1_IPG_GATE		48
+#define IMX5_CLK_SSI2_IPG_GATE		49
+#define IMX5_CLK_SSI3_IPG_GATE		50
+#define IMX5_CLK_ECSPI1_IPG_GATE	51
+#define IMX5_CLK_ECSPI1_PER_GATE	52
+#define IMX5_CLK_ECSPI2_IPG_GATE	53
+#define IMX5_CLK_ECSPI2_PER_GATE	54
+#define IMX5_CLK_CSPI_IPG_GATE		55
+#define IMX5_CLK_SDMA_GATE		56
+#define IMX5_CLK_EMI_SLOW_GATE		57
+#define IMX5_CLK_IPU_SEL		58
+#define IMX5_CLK_IPU_GATE		59
+#define IMX5_CLK_NFC_GATE		60
+#define IMX5_CLK_IPU_DI1_GATE		61
+#define IMX5_CLK_VPU_SEL		62
+#define IMX5_CLK_VPU_GATE		63
+#define IMX5_CLK_VPU_REFERENCE_GATE	64
+#define IMX5_CLK_UART4_IPG_GATE		65
+#define IMX5_CLK_UART4_PER_GATE		66
+#define IMX5_CLK_UART5_IPG_GATE		67
+#define IMX5_CLK_UART5_PER_GATE		68
+#define IMX5_CLK_TVE_GATE		69
+#define IMX5_CLK_TVE_PRED		70
+#define IMX5_CLK_ESDHC1_PER_GATE	71
+#define IMX5_CLK_ESDHC2_PER_GATE	72
+#define IMX5_CLK_ESDHC3_PER_GATE	73
+#define IMX5_CLK_ESDHC4_PER_GATE	74
+#define IMX5_CLK_USB_PHY_GATE		75
+#define IMX5_CLK_HSI2C_GATE		76
+#define IMX5_CLK_MIPI_HSC1_GATE		77
+#define IMX5_CLK_MIPI_HSC2_GATE		78
+#define IMX5_CLK_MIPI_ESC_GATE		79
+#define IMX5_CLK_MIPI_HSP_GATE		80
+#define IMX5_CLK_LDB_DI1_DIV_3_5	81
+#define IMX5_CLK_LDB_DI1_DIV		82
+#define IMX5_CLK_LDB_DI0_DIV_3_5	83
+#define IMX5_CLK_LDB_DI0_DIV		84
+#define IMX5_CLK_LDB_DI1_GATE		85
+#define IMX5_CLK_CAN2_SERIAL_GATE	86
+#define IMX5_CLK_CAN2_IPG_GATE		87
+#define IMX5_CLK_I2C3_GATE		88
+#define IMX5_CLK_LP_APM			89
+#define IMX5_CLK_PERIPH_APM		90
+#define IMX5_CLK_MAIN_BUS		91
+#define IMX5_CLK_AHB_MAX		92
+#define IMX5_CLK_AIPS_TZ1		93
+#define IMX5_CLK_AIPS_TZ2		94
+#define IMX5_CLK_TMAX1			95
+#define IMX5_CLK_TMAX2			96
+#define IMX5_CLK_TMAX3			97
+#define IMX5_CLK_SPBA			98
+#define IMX5_CLK_UART_SEL		99
+#define IMX5_CLK_ESDHC_A_SEL		100
+#define IMX5_CLK_ESDHC_B_SEL		101
+#define IMX5_CLK_ESDHC_A_PODF		102
+#define IMX5_CLK_ESDHC_B_PODF		103
+#define IMX5_CLK_ECSPI_SEL		104
+#define IMX5_CLK_USBOH3_SEL		105
+#define IMX5_CLK_USB_PHY_SEL		106
+#define IMX5_CLK_IIM_GATE		107
+#define IMX5_CLK_USBOH3_GATE		108
+#define IMX5_CLK_EMI_FAST_GATE		109
+#define IMX5_CLK_IPU_DI0_GATE		110
+#define IMX5_CLK_GPC_DVFS		111
+#define IMX5_CLK_PLL1_SW		112
+#define IMX5_CLK_PLL2_SW		113
+#define IMX5_CLK_PLL3_SW		114
+#define IMX5_CLK_IPU_DI0_SEL		115
+#define IMX5_CLK_IPU_DI1_SEL		116
+#define IMX5_CLK_TVE_EXT_SEL		117
+#define IMX5_CLK_MX51_MIPI		118
+#define IMX5_CLK_PLL4_SW		119
+#define IMX5_CLK_LDB_DI1_SEL		120
+#define IMX5_CLK_DI_PLL4_PODF		121
+#define IMX5_CLK_LDB_DI0_SEL		122
+#define IMX5_CLK_LDB_DI0_GATE		123
+#define IMX5_CLK_USB_PHY1_GATE		124
+#define IMX5_CLK_USB_PHY2_GATE		125
+#define IMX5_CLK_PER_LP_APM		126
+#define IMX5_CLK_PER_PRED1		127
+#define IMX5_CLK_PER_PRED2		128
+#define IMX5_CLK_PER_PODF		129
+#define IMX5_CLK_PER_ROOT		130
+#define IMX5_CLK_SSI_APM		131
+#define IMX5_CLK_SSI1_ROOT_SEL		132
+#define IMX5_CLK_SSI2_ROOT_SEL		133
+#define IMX5_CLK_SSI3_ROOT_SEL		134
+#define IMX5_CLK_SSI_EXT1_SEL		135
+#define IMX5_CLK_SSI_EXT2_SEL		136
+#define IMX5_CLK_SSI_EXT1_COM_SEL	137
+#define IMX5_CLK_SSI_EXT2_COM_SEL	138
+#define IMX5_CLK_SSI1_ROOT_PRED		139
+#define IMX5_CLK_SSI1_ROOT_PODF		140
+#define IMX5_CLK_SSI2_ROOT_PRED		141
+#define IMX5_CLK_SSI2_ROOT_PODF		142
+#define IMX5_CLK_SSI_EXT1_PRED		143
+#define IMX5_CLK_SSI_EXT1_PODF		144
+#define IMX5_CLK_SSI_EXT2_PRED		145
+#define IMX5_CLK_SSI_EXT2_PODF		146
+#define IMX5_CLK_SSI1_ROOT_GATE		147
+#define IMX5_CLK_SSI2_ROOT_GATE		148
+#define IMX5_CLK_SSI3_ROOT_GATE		149
+#define IMX5_CLK_SSI_EXT1_GATE		150
+#define IMX5_CLK_SSI_EXT2_GATE		151
+#define IMX5_CLK_EPIT1_IPG_GATE		152
+#define IMX5_CLK_EPIT1_HF_GATE		153
+#define IMX5_CLK_EPIT2_IPG_GATE		154
+#define IMX5_CLK_EPIT2_HF_GATE		155
+#define IMX5_CLK_CAN_SEL		156
+#define IMX5_CLK_CAN1_SERIAL_GATE	157
+#define IMX5_CLK_CAN1_IPG_GATE		158
+#define IMX5_CLK_OWIRE_GATE		159
+#define IMX5_CLK_GPU3D_SEL		160
+#define IMX5_CLK_GPU2D_SEL		161
+#define IMX5_CLK_GPU3D_GATE		162
+#define IMX5_CLK_GPU2D_GATE		163
+#define IMX5_CLK_GARB_GATE		164
+#define IMX5_CLK_CKO1_SEL		165
+#define IMX5_CLK_CKO1_PODF		166
+#define IMX5_CLK_CKO1			167
+#define IMX5_CLK_CKO2_SEL		168
+#define IMX5_CLK_CKO2_PODF		169
+#define IMX5_CLK_CKO2			170
+#define IMX5_CLK_SRTC_GATE		171
+#define IMX5_CLK_PATA_GATE		172
+#define IMX5_CLK_SATA_GATE		173
+#define IMX5_CLK_SPDIF_XTAL_SEL		174
+#define IMX5_CLK_SPDIF0_SEL		175
+#define IMX5_CLK_SPDIF1_SEL		176
+#define IMX5_CLK_SPDIF0_PRED		177
+#define IMX5_CLK_SPDIF0_PODF		178
+#define IMX5_CLK_SPDIF1_PRED		179
+#define IMX5_CLK_SPDIF1_PODF		180
+#define IMX5_CLK_SPDIF0_COM_SEL		181
+#define IMX5_CLK_SPDIF1_COM_SEL		182
+#define IMX5_CLK_SPDIF0_GATE		183
+#define IMX5_CLK_SPDIF1_GATE		184
+#define IMX5_CLK_SPDIF_IPG_GATE		185
+#define IMX5_CLK_OCRAM			186
+#define IMX5_CLK_SAHARA_IPG_GATE	187
+#define IMX5_CLK_SATA_REF		188
+#define IMX5_CLK_STEP_SEL		189
+#define IMX5_CLK_CPU_PODF_SEL		190
+#define IMX5_CLK_ARM			191
+#define IMX5_CLK_FIRI_PRED		192
+#define IMX5_CLK_FIRI_SEL		193
+#define IMX5_CLK_FIRI_PODF		194
+#define IMX5_CLK_FIRI_SERIAL_GATE	195
+#define IMX5_CLK_FIRI_IPG_GATE		196
+#define IMX5_CLK_CSI0_MCLK1_PRED	197
+#define IMX5_CLK_CSI0_MCLK1_SEL		198
+#define IMX5_CLK_CSI0_MCLK1_PODF	199
+#define IMX5_CLK_CSI0_MCLK1_GATE	200
+#define IMX5_CLK_IEEE1588_PRED		201
+#define IMX5_CLK_IEEE1588_SEL		202
+#define IMX5_CLK_IEEE1588_PODF		203
+#define IMX5_CLK_IEEE1588_GATE		204
+#define IMX5_CLK_END			205
+
+#endif /* __DT_BINDINGS_CLOCK_IMX5_H */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/imx6qdl-clock.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/imx6qdl-clock.h
new file mode 100644
index 0000000000000000000000000000000000000000..1f3772cde688ad11be3a40b1ce6bf413dee74ae1
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/imx6qdl-clock.h
@@ -0,0 +1,285 @@
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_IMX6QDL_H
+#define __DT_BINDINGS_CLOCK_IMX6QDL_H
+
+#define IMX6QDL_CLK_DUMMY			0
+#define IMX6QDL_CLK_CKIL			1
+#define IMX6QDL_CLK_CKIH			2
+#define IMX6QDL_CLK_OSC				3
+#define IMX6QDL_CLK_PLL2_PFD0_352M		4
+#define IMX6QDL_CLK_PLL2_PFD1_594M		5
+#define IMX6QDL_CLK_PLL2_PFD2_396M		6
+#define IMX6QDL_CLK_PLL3_PFD0_720M		7
+#define IMX6QDL_CLK_PLL3_PFD1_540M		8
+#define IMX6QDL_CLK_PLL3_PFD2_508M		9
+#define IMX6QDL_CLK_PLL3_PFD3_454M		10
+#define IMX6QDL_CLK_PLL2_198M			11
+#define IMX6QDL_CLK_PLL3_120M			12
+#define IMX6QDL_CLK_PLL3_80M			13
+#define IMX6QDL_CLK_PLL3_60M			14
+#define IMX6QDL_CLK_TWD				15
+#define IMX6QDL_CLK_STEP			16
+#define IMX6QDL_CLK_PLL1_SW			17
+#define IMX6QDL_CLK_PERIPH_PRE			18
+#define IMX6QDL_CLK_PERIPH2_PRE			19
+#define IMX6QDL_CLK_PERIPH_CLK2_SEL		20
+#define IMX6QDL_CLK_PERIPH2_CLK2_SEL		21
+#define IMX6QDL_CLK_AXI_SEL			22
+#define IMX6QDL_CLK_ESAI_SEL			23
+#define IMX6QDL_CLK_ASRC_SEL			24
+#define IMX6QDL_CLK_SPDIF_SEL			25
+#define IMX6QDL_CLK_GPU2D_AXI			26
+#define IMX6QDL_CLK_GPU3D_AXI			27
+#define IMX6QDL_CLK_GPU2D_CORE_SEL		28
+#define IMX6QDL_CLK_GPU3D_CORE_SEL		29
+#define IMX6QDL_CLK_GPU3D_SHADER_SEL		30
+#define IMX6QDL_CLK_IPU1_SEL			31
+#define IMX6QDL_CLK_IPU2_SEL			32
+#define IMX6QDL_CLK_LDB_DI0_SEL			33
+#define IMX6QDL_CLK_LDB_DI1_SEL			34
+#define IMX6QDL_CLK_IPU1_DI0_PRE_SEL		35
+#define IMX6QDL_CLK_IPU1_DI1_PRE_SEL		36
+#define IMX6QDL_CLK_IPU2_DI0_PRE_SEL		37
+#define IMX6QDL_CLK_IPU2_DI1_PRE_SEL		38
+#define IMX6QDL_CLK_IPU1_DI0_SEL		39
+#define IMX6QDL_CLK_IPU1_DI1_SEL		40
+#define IMX6QDL_CLK_IPU2_DI0_SEL		41
+#define IMX6QDL_CLK_IPU2_DI1_SEL		42
+#define IMX6QDL_CLK_HSI_TX_SEL			43
+#define IMX6QDL_CLK_PCIE_AXI_SEL		44
+#define IMX6QDL_CLK_SSI1_SEL			45
+#define IMX6QDL_CLK_SSI2_SEL			46
+#define IMX6QDL_CLK_SSI3_SEL			47
+#define IMX6QDL_CLK_USDHC1_SEL			48
+#define IMX6QDL_CLK_USDHC2_SEL			49
+#define IMX6QDL_CLK_USDHC3_SEL			50
+#define IMX6QDL_CLK_USDHC4_SEL			51
+#define IMX6QDL_CLK_ENFC_SEL			52
+#define IMX6QDL_CLK_EIM_SEL			53
+#define IMX6QDL_CLK_EIM_SLOW_SEL		54
+#define IMX6QDL_CLK_VDO_AXI_SEL			55
+#define IMX6QDL_CLK_VPU_AXI_SEL			56
+#define IMX6QDL_CLK_CKO1_SEL			57
+#define IMX6QDL_CLK_PERIPH			58
+#define IMX6QDL_CLK_PERIPH2			59
+#define IMX6QDL_CLK_PERIPH_CLK2			60
+#define IMX6QDL_CLK_PERIPH2_CLK2		61
+#define IMX6QDL_CLK_IPG				62
+#define IMX6QDL_CLK_IPG_PER			63
+#define IMX6QDL_CLK_ESAI_PRED			64
+#define IMX6QDL_CLK_ESAI_PODF			65
+#define IMX6QDL_CLK_ASRC_PRED			66
+#define IMX6QDL_CLK_ASRC_PODF			67
+#define IMX6QDL_CLK_SPDIF_PRED			68
+#define IMX6QDL_CLK_SPDIF_PODF			69
+#define IMX6QDL_CLK_CAN_ROOT			70
+#define IMX6QDL_CLK_ECSPI_ROOT			71
+#define IMX6QDL_CLK_GPU2D_CORE_PODF		72
+#define IMX6QDL_CLK_GPU3D_CORE_PODF		73
+#define IMX6QDL_CLK_GPU3D_SHADER		74
+#define IMX6QDL_CLK_IPU1_PODF			75
+#define IMX6QDL_CLK_IPU2_PODF			76
+#define IMX6QDL_CLK_LDB_DI0_PODF		77
+#define IMX6QDL_CLK_LDB_DI1_PODF		78
+#define IMX6QDL_CLK_IPU1_DI0_PRE		79
+#define IMX6QDL_CLK_IPU1_DI1_PRE		80
+#define IMX6QDL_CLK_IPU2_DI0_PRE		81
+#define IMX6QDL_CLK_IPU2_DI1_PRE		82
+#define IMX6QDL_CLK_HSI_TX_PODF			83
+#define IMX6QDL_CLK_SSI1_PRED			84
+#define IMX6QDL_CLK_SSI1_PODF			85
+#define IMX6QDL_CLK_SSI2_PRED			86
+#define IMX6QDL_CLK_SSI2_PODF			87
+#define IMX6QDL_CLK_SSI3_PRED			88
+#define IMX6QDL_CLK_SSI3_PODF			89
+#define IMX6QDL_CLK_UART_SERIAL_PODF		90
+#define IMX6QDL_CLK_USDHC1_PODF			91
+#define IMX6QDL_CLK_USDHC2_PODF			92
+#define IMX6QDL_CLK_USDHC3_PODF			93
+#define IMX6QDL_CLK_USDHC4_PODF			94
+#define IMX6QDL_CLK_ENFC_PRED			95
+#define IMX6QDL_CLK_ENFC_PODF			96
+#define IMX6QDL_CLK_EIM_PODF			97
+#define IMX6QDL_CLK_EIM_SLOW_PODF		98
+#define IMX6QDL_CLK_VPU_AXI_PODF		99
+#define IMX6QDL_CLK_CKO1_PODF			100
+#define IMX6QDL_CLK_AXI				101
+#define IMX6QDL_CLK_MMDC_CH0_AXI_PODF		102
+#define IMX6QDL_CLK_MMDC_CH1_AXI_PODF		103
+#define IMX6QDL_CLK_ARM				104
+#define IMX6QDL_CLK_AHB				105
+#define IMX6QDL_CLK_APBH_DMA			106
+#define IMX6QDL_CLK_ASRC			107
+#define IMX6QDL_CLK_CAN1_IPG			108
+#define IMX6QDL_CLK_CAN1_SERIAL			109
+#define IMX6QDL_CLK_CAN2_IPG			110
+#define IMX6QDL_CLK_CAN2_SERIAL			111
+#define IMX6QDL_CLK_ECSPI1			112
+#define IMX6QDL_CLK_ECSPI2			113
+#define IMX6QDL_CLK_ECSPI3			114
+#define IMX6QDL_CLK_ECSPI4			115
+#define IMX6Q_CLK_ECSPI5			116
+#define IMX6DL_CLK_I2C4				116
+#define IMX6QDL_CLK_ENET			117
+#define IMX6QDL_CLK_ESAI_EXTAL			118
+#define IMX6QDL_CLK_GPT_IPG			119
+#define IMX6QDL_CLK_GPT_IPG_PER			120
+#define IMX6QDL_CLK_GPU2D_CORE			121
+#define IMX6QDL_CLK_GPU3D_CORE			122
+#define IMX6QDL_CLK_HDMI_IAHB			123
+#define IMX6QDL_CLK_HDMI_ISFR			124
+#define IMX6QDL_CLK_I2C1			125
+#define IMX6QDL_CLK_I2C2			126
+#define IMX6QDL_CLK_I2C3			127
+#define IMX6QDL_CLK_IIM				128
+#define IMX6QDL_CLK_ENFC			129
+#define IMX6QDL_CLK_IPU1			130
+#define IMX6QDL_CLK_IPU1_DI0			131
+#define IMX6QDL_CLK_IPU1_DI1			132
+#define IMX6QDL_CLK_IPU2			133
+#define IMX6QDL_CLK_IPU2_DI0			134
+#define IMX6QDL_CLK_LDB_DI0			135
+#define IMX6QDL_CLK_LDB_DI1			136
+#define IMX6QDL_CLK_IPU2_DI1			137
+#define IMX6QDL_CLK_HSI_TX			138
+#define IMX6QDL_CLK_MLB				139
+#define IMX6QDL_CLK_MMDC_CH0_AXI		140
+#define IMX6QDL_CLK_MMDC_CH1_AXI		141
+#define IMX6QDL_CLK_OCRAM			142
+#define IMX6QDL_CLK_OPENVG_AXI			143
+#define IMX6QDL_CLK_PCIE_AXI			144
+#define IMX6QDL_CLK_PWM1			145
+#define IMX6QDL_CLK_PWM2			146
+#define IMX6QDL_CLK_PWM3			147
+#define IMX6QDL_CLK_PWM4			148
+#define IMX6QDL_CLK_PER1_BCH			149
+#define IMX6QDL_CLK_GPMI_BCH_APB		150
+#define IMX6QDL_CLK_GPMI_BCH			151
+#define IMX6QDL_CLK_GPMI_IO			152
+#define IMX6QDL_CLK_GPMI_APB			153
+#define IMX6QDL_CLK_SATA			154
+#define IMX6QDL_CLK_SDMA			155
+#define IMX6QDL_CLK_SPBA			156
+#define IMX6QDL_CLK_SSI1			157
+#define IMX6QDL_CLK_SSI2			158
+#define IMX6QDL_CLK_SSI3			159
+#define IMX6QDL_CLK_UART_IPG			160
+#define IMX6QDL_CLK_UART_SERIAL			161
+#define IMX6QDL_CLK_USBOH3			162
+#define IMX6QDL_CLK_USDHC1			163
+#define IMX6QDL_CLK_USDHC2			164
+#define IMX6QDL_CLK_USDHC3			165
+#define IMX6QDL_CLK_USDHC4			166
+#define IMX6QDL_CLK_VDO_AXI			167
+#define IMX6QDL_CLK_VPU_AXI			168
+#define IMX6QDL_CLK_CKO1			169
+#define IMX6QDL_CLK_PLL1_SYS			170
+#define IMX6QDL_CLK_PLL2_BUS			171
+#define IMX6QDL_CLK_PLL3_USB_OTG		172
+#define IMX6QDL_CLK_PLL4_AUDIO			173
+#define IMX6QDL_CLK_PLL5_VIDEO			174
+#define IMX6QDL_CLK_PLL8_MLB			175
+#define IMX6QDL_CLK_PLL7_USB_HOST		176
+#define IMX6QDL_CLK_PLL6_ENET			177
+#define IMX6QDL_CLK_SSI1_IPG			178
+#define IMX6QDL_CLK_SSI2_IPG			179
+#define IMX6QDL_CLK_SSI3_IPG			180
+#define IMX6QDL_CLK_ROM				181
+#define IMX6QDL_CLK_USBPHY1			182
+#define IMX6QDL_CLK_USBPHY2			183
+#define IMX6QDL_CLK_LDB_DI0_DIV_3_5		184
+#define IMX6QDL_CLK_LDB_DI1_DIV_3_5		185
+#define IMX6QDL_CLK_SATA_REF			186
+#define IMX6QDL_CLK_SATA_REF_100M		187
+#define IMX6QDL_CLK_PCIE_REF			188
+#define IMX6QDL_CLK_PCIE_REF_125M		189
+#define IMX6QDL_CLK_ENET_REF			190
+#define IMX6QDL_CLK_USBPHY1_GATE		191
+#define IMX6QDL_CLK_USBPHY2_GATE		192
+#define IMX6QDL_CLK_PLL4_POST_DIV		193
+#define IMX6QDL_CLK_PLL5_POST_DIV		194
+#define IMX6QDL_CLK_PLL5_VIDEO_DIV		195
+#define IMX6QDL_CLK_EIM_SLOW			196
+#define IMX6QDL_CLK_SPDIF			197
+#define IMX6QDL_CLK_CKO2_SEL			198
+#define IMX6QDL_CLK_CKO2_PODF			199
+#define IMX6QDL_CLK_CKO2			200
+#define IMX6QDL_CLK_CKO				201
+#define IMX6QDL_CLK_VDOA			202
+#define IMX6QDL_CLK_PLL4_AUDIO_DIV		203
+#define IMX6QDL_CLK_LVDS1_SEL			204
+#define IMX6QDL_CLK_LVDS2_SEL			205
+#define IMX6QDL_CLK_LVDS1_GATE			206
+#define IMX6QDL_CLK_LVDS2_GATE			207
+#define IMX6QDL_CLK_ESAI_IPG			208
+#define IMX6QDL_CLK_ESAI_MEM			209
+#define IMX6QDL_CLK_ASRC_IPG			210
+#define IMX6QDL_CLK_ASRC_MEM			211
+#define IMX6QDL_CLK_LVDS1_IN			212
+#define IMX6QDL_CLK_LVDS2_IN			213
+#define IMX6QDL_CLK_ANACLK1			214
+#define IMX6QDL_CLK_ANACLK2			215
+#define IMX6QDL_PLL1_BYPASS_SRC			216
+#define IMX6QDL_PLL2_BYPASS_SRC			217
+#define IMX6QDL_PLL3_BYPASS_SRC			218
+#define IMX6QDL_PLL4_BYPASS_SRC			219
+#define IMX6QDL_PLL5_BYPASS_SRC			220
+#define IMX6QDL_PLL6_BYPASS_SRC			221
+#define IMX6QDL_PLL7_BYPASS_SRC			222
+#define IMX6QDL_CLK_PLL1			223
+#define IMX6QDL_CLK_PLL2			224
+#define IMX6QDL_CLK_PLL3			225
+#define IMX6QDL_CLK_PLL4			226
+#define IMX6QDL_CLK_PLL5			227
+#define IMX6QDL_CLK_PLL6			228
+#define IMX6QDL_CLK_PLL7			229
+#define IMX6QDL_PLL1_BYPASS			230
+#define IMX6QDL_PLL2_BYPASS			231
+#define IMX6QDL_PLL3_BYPASS			232
+#define IMX6QDL_PLL4_BYPASS			233
+#define IMX6QDL_PLL5_BYPASS			234
+#define IMX6QDL_PLL6_BYPASS			235
+#define IMX6QDL_PLL7_BYPASS			236
+#define IMX6QDL_CLK_GPT_3M			237
+#define IMX6QDL_CLK_VIDEO_27M			238
+#define IMX6QDL_CLK_MIPI_CORE_CFG		239
+#define IMX6QDL_CLK_MIPI_IPG			240
+#define IMX6QDL_CLK_CAAM_MEM			241
+#define IMX6QDL_CLK_CAAM_ACLK			242
+#define IMX6QDL_CLK_CAAM_IPG			243
+#define IMX6QDL_CLK_SPDIF_GCLK			244
+#define IMX6QDL_CLK_UART_SEL			245
+#define IMX6QDL_CLK_IPG_PER_SEL			246
+#define IMX6QDL_CLK_ECSPI_SEL			247
+#define IMX6QDL_CLK_CAN_SEL			248
+#define IMX6QDL_CLK_MMDC_CH1_AXI_CG		249
+#define IMX6QDL_CLK_PRE0			250
+#define IMX6QDL_CLK_PRE1			251
+#define IMX6QDL_CLK_PRE2			252
+#define IMX6QDL_CLK_PRE3			253
+#define IMX6QDL_CLK_PRG0_AXI			254
+#define IMX6QDL_CLK_PRG1_AXI			255
+#define IMX6QDL_CLK_PRG0_APB			256
+#define IMX6QDL_CLK_PRG1_APB			257
+#define IMX6QDL_CLK_PRE_AXI			258
+#define IMX6QDL_CLK_MLB_SEL			259
+#define IMX6QDL_CLK_MLB_PODF			260
+#define IMX6QDL_CLK_EPIT1			261
+#define IMX6QDL_CLK_EPIT2			262
+#define IMX6QDL_CLK_AXI_ALT_SEL			263
+#define IMX6QDL_CLK_LDB_DI0_DIV_7		264
+#define IMX6QDL_CLK_LDB_DI1_DIV_7		265
+#define IMX6QDL_CLK_LDB_DI0_DIV_SEL		266
+#define IMX6QDL_CLK_LDB_DI1_DIV_SEL		267
+#define IMX6QDL_CLK_DCIC1			268
+#define IMX6QDL_CLK_DCIC2			269
+#define IMX6QDL_CLK_END				270
+
+#endif /* __DT_BINDINGS_CLOCK_IMX6QDL_H */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/imx6sl-clock.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/imx6sl-clock.h
new file mode 100644
index 0000000000000000000000000000000000000000..6bc731e00a898e30eb8171f063a30a890df9b5bd
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/imx6sl-clock.h
@@ -0,0 +1,181 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_IMX6SL_H
+#define __DT_BINDINGS_CLOCK_IMX6SL_H
+
+#define IMX6SL_CLK_DUMMY		0
+#define IMX6SL_CLK_CKIL			1
+#define IMX6SL_CLK_OSC			2
+#define IMX6SL_CLK_PLL1_SYS		3
+#define IMX6SL_CLK_PLL2_BUS		4
+#define IMX6SL_CLK_PLL3_USB_OTG		5
+#define IMX6SL_CLK_PLL4_AUDIO		6
+#define IMX6SL_CLK_PLL5_VIDEO		7
+#define IMX6SL_CLK_PLL6_ENET		8
+#define IMX6SL_CLK_PLL7_USB_HOST	9
+#define IMX6SL_CLK_USBPHY1		10
+#define IMX6SL_CLK_USBPHY2		11
+#define IMX6SL_CLK_USBPHY1_GATE		12
+#define IMX6SL_CLK_USBPHY2_GATE		13
+#define IMX6SL_CLK_PLL4_POST_DIV	14
+#define IMX6SL_CLK_PLL5_POST_DIV	15
+#define IMX6SL_CLK_PLL5_VIDEO_DIV	16
+#define IMX6SL_CLK_ENET_REF		17
+#define IMX6SL_CLK_PLL2_PFD0		18
+#define IMX6SL_CLK_PLL2_PFD1		19
+#define IMX6SL_CLK_PLL2_PFD2		20
+#define IMX6SL_CLK_PLL3_PFD0		21
+#define IMX6SL_CLK_PLL3_PFD1		22
+#define IMX6SL_CLK_PLL3_PFD2		23
+#define IMX6SL_CLK_PLL3_PFD3		24
+#define IMX6SL_CLK_PLL2_198M		25
+#define IMX6SL_CLK_PLL3_120M		26
+#define IMX6SL_CLK_PLL3_80M		27
+#define IMX6SL_CLK_PLL3_60M		28
+#define IMX6SL_CLK_STEP			29
+#define IMX6SL_CLK_PLL1_SW		30
+#define IMX6SL_CLK_OCRAM_ALT_SEL	31
+#define IMX6SL_CLK_OCRAM_SEL		32
+#define IMX6SL_CLK_PRE_PERIPH2_SEL	33
+#define IMX6SL_CLK_PRE_PERIPH_SEL	34
+#define IMX6SL_CLK_PERIPH2_CLK2_SEL	35
+#define IMX6SL_CLK_PERIPH_CLK2_SEL	36
+#define IMX6SL_CLK_CSI_SEL		37
+#define IMX6SL_CLK_LCDIF_AXI_SEL	38
+#define IMX6SL_CLK_USDHC1_SEL		39
+#define IMX6SL_CLK_USDHC2_SEL		40
+#define IMX6SL_CLK_USDHC3_SEL		41
+#define IMX6SL_CLK_USDHC4_SEL		42
+#define IMX6SL_CLK_SSI1_SEL		43
+#define IMX6SL_CLK_SSI2_SEL		44
+#define IMX6SL_CLK_SSI3_SEL		45
+#define IMX6SL_CLK_PERCLK_SEL		46
+#define IMX6SL_CLK_PXP_AXI_SEL		47
+#define IMX6SL_CLK_EPDC_AXI_SEL		48
+#define IMX6SL_CLK_GPU2D_OVG_SEL	49
+#define IMX6SL_CLK_GPU2D_SEL		50
+#define IMX6SL_CLK_LCDIF_PIX_SEL	51
+#define IMX6SL_CLK_EPDC_PIX_SEL		52
+#define IMX6SL_CLK_SPDIF0_SEL		53
+#define IMX6SL_CLK_SPDIF1_SEL		54
+#define IMX6SL_CLK_EXTERN_AUDIO_SEL	55
+#define IMX6SL_CLK_ECSPI_SEL		56
+#define IMX6SL_CLK_UART_SEL		57
+#define IMX6SL_CLK_PERIPH		58
+#define IMX6SL_CLK_PERIPH2		59
+#define IMX6SL_CLK_OCRAM_PODF		60
+#define IMX6SL_CLK_PERIPH_CLK2_PODF	61
+#define IMX6SL_CLK_PERIPH2_CLK2_PODF	62
+#define IMX6SL_CLK_IPG			63
+#define IMX6SL_CLK_CSI_PODF		64
+#define IMX6SL_CLK_LCDIF_AXI_PODF	65
+#define IMX6SL_CLK_USDHC1_PODF		66
+#define IMX6SL_CLK_USDHC2_PODF		67
+#define IMX6SL_CLK_USDHC3_PODF		68
+#define IMX6SL_CLK_USDHC4_PODF		69
+#define IMX6SL_CLK_SSI1_PRED		70
+#define IMX6SL_CLK_SSI1_PODF		71
+#define IMX6SL_CLK_SSI2_PRED		72
+#define IMX6SL_CLK_SSI2_PODF		73
+#define IMX6SL_CLK_SSI3_PRED		74
+#define IMX6SL_CLK_SSI3_PODF		75
+#define IMX6SL_CLK_PERCLK		76
+#define IMX6SL_CLK_PXP_AXI_PODF		77
+#define IMX6SL_CLK_EPDC_AXI_PODF	78
+#define IMX6SL_CLK_GPU2D_OVG_PODF	79
+#define IMX6SL_CLK_GPU2D_PODF		80
+#define IMX6SL_CLK_LCDIF_PIX_PRED	81
+#define IMX6SL_CLK_EPDC_PIX_PRED	82
+#define IMX6SL_CLK_LCDIF_PIX_PODF	83
+#define IMX6SL_CLK_EPDC_PIX_PODF	84
+#define IMX6SL_CLK_SPDIF0_PRED		85
+#define IMX6SL_CLK_SPDIF0_PODF		86
+#define IMX6SL_CLK_SPDIF1_PRED		87
+#define IMX6SL_CLK_SPDIF1_PODF		88
+#define IMX6SL_CLK_EXTERN_AUDIO_PRED	89
+#define IMX6SL_CLK_EXTERN_AUDIO_PODF	90
+#define IMX6SL_CLK_ECSPI_ROOT		91
+#define IMX6SL_CLK_UART_ROOT		92
+#define IMX6SL_CLK_AHB			93
+#define IMX6SL_CLK_MMDC_ROOT		94
+#define IMX6SL_CLK_ARM			95
+#define IMX6SL_CLK_ECSPI1		96
+#define IMX6SL_CLK_ECSPI2		97
+#define IMX6SL_CLK_ECSPI3		98
+#define IMX6SL_CLK_ECSPI4		99
+#define IMX6SL_CLK_EPIT1		100
+#define IMX6SL_CLK_EPIT2		101
+#define IMX6SL_CLK_EXTERN_AUDIO		102
+#define IMX6SL_CLK_GPT			103
+#define IMX6SL_CLK_GPT_SERIAL		104
+#define IMX6SL_CLK_GPU2D_OVG		105
+#define IMX6SL_CLK_I2C1			106
+#define IMX6SL_CLK_I2C2			107
+#define IMX6SL_CLK_I2C3			108
+#define IMX6SL_CLK_OCOTP		109
+#define IMX6SL_CLK_CSI			110
+#define IMX6SL_CLK_PXP_AXI		111
+#define IMX6SL_CLK_EPDC_AXI		112
+#define IMX6SL_CLK_LCDIF_AXI		113
+#define IMX6SL_CLK_LCDIF_PIX		114
+#define IMX6SL_CLK_EPDC_PIX		115
+#define IMX6SL_CLK_OCRAM		116
+#define IMX6SL_CLK_PWM1			117
+#define IMX6SL_CLK_PWM2			118
+#define IMX6SL_CLK_PWM3			119
+#define IMX6SL_CLK_PWM4			120
+#define IMX6SL_CLK_SDMA			121
+#define IMX6SL_CLK_SPDIF		122
+#define IMX6SL_CLK_SSI1			123
+#define IMX6SL_CLK_SSI2			124
+#define IMX6SL_CLK_SSI3			125
+#define IMX6SL_CLK_UART			126
+#define IMX6SL_CLK_UART_SERIAL		127
+#define IMX6SL_CLK_USBOH3		128
+#define IMX6SL_CLK_USDHC1		129
+#define IMX6SL_CLK_USDHC2		130
+#define IMX6SL_CLK_USDHC3		131
+#define IMX6SL_CLK_USDHC4		132
+#define IMX6SL_CLK_PLL4_AUDIO_DIV	133
+#define IMX6SL_CLK_SPBA			134
+#define IMX6SL_CLK_ENET			135
+#define IMX6SL_CLK_LVDS1_SEL		136
+#define IMX6SL_CLK_LVDS1_OUT		137
+#define IMX6SL_CLK_LVDS1_IN		138
+#define IMX6SL_CLK_ANACLK1		139
+#define IMX6SL_PLL1_BYPASS_SRC		140
+#define IMX6SL_PLL2_BYPASS_SRC		141
+#define IMX6SL_PLL3_BYPASS_SRC		142
+#define IMX6SL_PLL4_BYPASS_SRC		143
+#define IMX6SL_PLL5_BYPASS_SRC		144
+#define IMX6SL_PLL6_BYPASS_SRC		145
+#define IMX6SL_PLL7_BYPASS_SRC		146
+#define IMX6SL_CLK_PLL1			147
+#define IMX6SL_CLK_PLL2			148
+#define IMX6SL_CLK_PLL3			149
+#define IMX6SL_CLK_PLL4			150
+#define IMX6SL_CLK_PLL5			151
+#define IMX6SL_CLK_PLL6			152
+#define IMX6SL_CLK_PLL7			153
+#define IMX6SL_PLL1_BYPASS		154
+#define IMX6SL_PLL2_BYPASS		155
+#define IMX6SL_PLL3_BYPASS		156
+#define IMX6SL_PLL4_BYPASS		157
+#define IMX6SL_PLL5_BYPASS		158
+#define IMX6SL_PLL6_BYPASS		159
+#define IMX6SL_PLL7_BYPASS		160
+#define IMX6SL_CLK_SSI1_IPG		161
+#define IMX6SL_CLK_SSI2_IPG		162
+#define IMX6SL_CLK_SSI3_IPG		163
+#define IMX6SL_CLK_SPDIF_GCLK		164
+#define IMX6SL_CLK_UART_OSC_4M		165
+#define IMX6SL_CLK_END			166
+
+#endif /* __DT_BINDINGS_CLOCK_IMX6SL_H */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/imx6sll-clock.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/imx6sll-clock.h
new file mode 100644
index 0000000000000000000000000000000000000000..c603667235fe80e694d1a4e436f2abf53fe16a79
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/imx6sll-clock.h
@@ -0,0 +1,209 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017-2018 NXP.
+ *
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_IMX6SLL_H
+#define __DT_BINDINGS_CLOCK_IMX6SLL_H
+
+#define IMX6SLL_CLK_DUMMY		0
+#define IMX6SLL_CLK_CKIL		1
+#define IMX6SLL_CLK_OSC			2
+#define IMX6SLL_PLL1_BYPASS_SRC		3
+#define IMX6SLL_PLL2_BYPASS_SRC		4
+#define IMX6SLL_PLL3_BYPASS_SRC		5
+#define IMX6SLL_PLL4_BYPASS_SRC		6
+#define IMX6SLL_PLL5_BYPASS_SRC		7
+#define IMX6SLL_PLL6_BYPASS_SRC		8
+#define IMX6SLL_PLL7_BYPASS_SRC		9
+#define IMX6SLL_CLK_PLL1		10
+#define IMX6SLL_CLK_PLL2		11
+#define IMX6SLL_CLK_PLL3		12
+#define IMX6SLL_CLK_PLL4		13
+#define IMX6SLL_CLK_PLL5		14
+#define IMX6SLL_CLK_PLL6		15
+#define IMX6SLL_CLK_PLL7		16
+#define IMX6SLL_PLL1_BYPASS		17
+#define IMX6SLL_PLL2_BYPASS		18
+#define IMX6SLL_PLL3_BYPASS		19
+#define IMX6SLL_PLL4_BYPASS		20
+#define IMX6SLL_PLL5_BYPASS		21
+#define IMX6SLL_PLL6_BYPASS		22
+#define IMX6SLL_PLL7_BYPASS		23
+#define IMX6SLL_CLK_PLL1_SYS		24
+#define IMX6SLL_CLK_PLL2_BUS		25
+#define IMX6SLL_CLK_PLL3_USB_OTG	26
+#define IMX6SLL_CLK_PLL4_AUDIO		27
+#define IMX6SLL_CLK_PLL5_VIDEO		28
+#define IMX6SLL_CLK_PLL6_ENET		29
+#define IMX6SLL_CLK_PLL7_USB_HOST	30
+#define IMX6SLL_CLK_USBPHY1		31
+#define IMX6SLL_CLK_USBPHY2		32
+#define IMX6SLL_CLK_USBPHY1_GATE	33
+#define IMX6SLL_CLK_USBPHY2_GATE	34
+#define IMX6SLL_CLK_PLL2_PFD0		35
+#define IMX6SLL_CLK_PLL2_PFD1		36
+#define IMX6SLL_CLK_PLL2_PFD2		37
+#define IMX6SLL_CLK_PLL2_PFD3		38
+#define IMX6SLL_CLK_PLL3_PFD0		39
+#define IMX6SLL_CLK_PLL3_PFD1		40
+#define IMX6SLL_CLK_PLL3_PFD2		41
+#define IMX6SLL_CLK_PLL3_PFD3		42
+#define IMX6SLL_CLK_PLL4_POST_DIV	43
+#define IMX6SLL_CLK_PLL4_AUDIO_DIV	44
+#define IMX6SLL_CLK_PLL5_POST_DIV	45
+#define IMX6SLL_CLK_PLL5_VIDEO_DIV	46
+#define IMX6SLL_CLK_PLL2_198M		47
+#define IMX6SLL_CLK_PLL3_120M		48
+#define IMX6SLL_CLK_PLL3_80M		49
+#define IMX6SLL_CLK_PLL3_60M		50
+#define IMX6SLL_CLK_STEP		51
+#define IMX6SLL_CLK_PLL1_SW		52
+#define IMX6SLL_CLK_AXI_ALT_SEL		53
+#define IMX6SLL_CLK_AXI_SEL		54
+#define IMX6SLL_CLK_PERIPH_PRE		55
+#define IMX6SLL_CLK_PERIPH2_PRE		56
+#define IMX6SLL_CLK_PERIPH_CLK2_SEL	57
+#define IMX6SLL_CLK_PERIPH2_CLK2_SEL	58
+#define IMX6SLL_CLK_PERCLK_SEL		59
+#define IMX6SLL_CLK_USDHC1_SEL		60
+#define IMX6SLL_CLK_USDHC2_SEL		61
+#define IMX6SLL_CLK_USDHC3_SEL		62
+#define IMX6SLL_CLK_SSI1_SEL		63
+#define IMX6SLL_CLK_SSI2_SEL		64
+#define IMX6SLL_CLK_SSI3_SEL		65
+#define IMX6SLL_CLK_PXP_SEL		66
+#define IMX6SLL_CLK_LCDIF_PRE_SEL	67
+#define IMX6SLL_CLK_LCDIF_SEL		68
+#define IMX6SLL_CLK_EPDC_PRE_SEL	69
+#define IMX6SLL_CLK_SPDIF_SEL		70
+#define IMX6SLL_CLK_ECSPI_SEL		71
+#define IMX6SLL_CLK_UART_SEL		72
+#define IMX6SLL_CLK_ARM			73
+#define IMX6SLL_CLK_PERIPH		74
+#define IMX6SLL_CLK_PERIPH2		75
+#define IMX6SLL_CLK_PERIPH2_CLK2	76
+#define IMX6SLL_CLK_PERIPH_CLK2		77
+#define IMX6SLL_CLK_MMDC_PODF		78
+#define IMX6SLL_CLK_AXI_PODF		79
+#define IMX6SLL_CLK_AHB			80
+#define IMX6SLL_CLK_IPG			81
+#define IMX6SLL_CLK_PERCLK		82
+#define IMX6SLL_CLK_USDHC1_PODF		83
+#define IMX6SLL_CLK_USDHC2_PODF		84
+#define IMX6SLL_CLK_USDHC3_PODF		85
+#define IMX6SLL_CLK_SSI1_PRED		86
+#define IMX6SLL_CLK_SSI2_PRED		87
+#define IMX6SLL_CLK_SSI3_PRED		88
+#define IMX6SLL_CLK_SSI1_PODF		89
+#define IMX6SLL_CLK_SSI2_PODF		90
+#define IMX6SLL_CLK_SSI3_PODF		91
+#define IMX6SLL_CLK_PXP_PODF		92
+#define IMX6SLL_CLK_LCDIF_PRED		93
+#define IMX6SLL_CLK_LCDIF_PODF		94
+#define IMX6SLL_CLK_EPDC_SEL		95
+#define IMX6SLL_CLK_EPDC_PODF		96
+#define IMX6SLL_CLK_SPDIF_PRED		97
+#define IMX6SLL_CLK_SPDIF_PODF		98
+#define IMX6SLL_CLK_ECSPI_PODF		99
+#define IMX6SLL_CLK_UART_PODF		100
+
+/* CCGR 0 */
+#define IMX6SLL_CLK_AIPSTZ1		101
+#define IMX6SLL_CLK_AIPSTZ2		102
+#define IMX6SLL_CLK_DCP			103
+#define IMX6SLL_CLK_UART2_IPG		104
+#define IMX6SLL_CLK_UART2_SERIAL	105
+
+/* CCGR 1 */
+#define IMX6SLL_CLK_ECSPI1		106
+#define IMX6SLL_CLK_ECSPI2		107
+#define IMX6SLL_CLK_ECSPI3		108
+#define IMX6SLL_CLK_ECSPI4		109
+#define IMX6SLL_CLK_UART3_IPG		110
+#define IMX6SLL_CLK_UART3_SERIAL	111
+#define IMX6SLL_CLK_UART4_IPG		112
+#define IMX6SLL_CLK_UART4_SERIAL	113
+#define IMX6SLL_CLK_EPIT1		114
+#define IMX6SLL_CLK_EPIT2		115
+#define IMX6SLL_CLK_GPT_BUS		116
+#define IMX6SLL_CLK_GPT_SERIAL		117
+
+/* CCGR2 */
+#define IMX6SLL_CLK_CSI			118
+#define IMX6SLL_CLK_I2C1		119
+#define IMX6SLL_CLK_I2C2		120
+#define IMX6SLL_CLK_I2C3		121
+#define IMX6SLL_CLK_OCOTP		122
+#define IMX6SLL_CLK_LCDIF_APB		123
+#define IMX6SLL_CLK_PXP			124
+
+/* CCGR3 */
+#define IMX6SLL_CLK_UART5_IPG		125
+#define IMX6SLL_CLK_UART5_SERIAL	126
+#define IMX6SLL_CLK_EPDC_AXI		127
+#define IMX6SLL_CLK_EPDC_PIX		128
+#define IMX6SLL_CLK_LCDIF_PIX		129
+#define IMX6SLL_CLK_WDOG1		130
+#define IMX6SLL_CLK_MMDC_P0_FAST	131
+#define IMX6SLL_CLK_MMDC_P0_IPG		132
+#define IMX6SLL_CLK_OCRAM		133
+
+/* CCGR4 */
+#define IMX6SLL_CLK_PWM1		134
+#define IMX6SLL_CLK_PWM2		135
+#define IMX6SLL_CLK_PWM3		136
+#define IMX6SLL_CLK_PWM4		137
+
+/* CCGR 5 */
+#define IMX6SLL_CLK_ROM			138
+#define IMX6SLL_CLK_SDMA		139
+#define IMX6SLL_CLK_KPP			140
+#define IMX6SLL_CLK_WDOG2		141
+#define IMX6SLL_CLK_SPBA		142
+#define IMX6SLL_CLK_SPDIF		143
+#define IMX6SLL_CLK_SPDIF_GCLK		144
+#define IMX6SLL_CLK_SSI1		145
+#define IMX6SLL_CLK_SSI1_IPG		146
+#define IMX6SLL_CLK_SSI2		147
+#define IMX6SLL_CLK_SSI2_IPG		148
+#define IMX6SLL_CLK_SSI3		149
+#define IMX6SLL_CLK_SSI3_IPG		150
+#define IMX6SLL_CLK_UART1_IPG		151
+#define IMX6SLL_CLK_UART1_SERIAL	152
+
+/* CCGR 6 */
+#define IMX6SLL_CLK_USBOH3		153
+#define IMX6SLL_CLK_USDHC1		154
+#define IMX6SLL_CLK_USDHC2		155
+#define IMX6SLL_CLK_USDHC3		156
+
+#define IMX6SLL_CLK_IPP_DI0		157
+#define IMX6SLL_CLK_IPP_DI1		158
+#define IMX6SLL_CLK_LDB_DI0_SEL		159
+#define IMX6SLL_CLK_LDB_DI0_DIV_3_5	160
+#define IMX6SLL_CLK_LDB_DI0_DIV_7	161
+#define IMX6SLL_CLK_LDB_DI0_DIV_SEL	162
+#define IMX6SLL_CLK_LDB_DI0		163
+#define IMX6SLL_CLK_LDB_DI1_SEL		164
+#define IMX6SLL_CLK_LDB_DI1_DIV_3_5	165
+#define IMX6SLL_CLK_LDB_DI1_DIV_7	166
+#define IMX6SLL_CLK_LDB_DI1_DIV_SEL	167
+#define IMX6SLL_CLK_LDB_DI1		168
+#define IMX6SLL_CLK_EXTERN_AUDIO_SEL    169
+#define IMX6SLL_CLK_EXTERN_AUDIO_PRED   170
+#define IMX6SLL_CLK_EXTERN_AUDIO_PODF   171
+#define IMX6SLL_CLK_EXTERN_AUDIO        172
+#define IMX6SLL_CLK_GPIO1               173
+#define IMX6SLL_CLK_GPIO2               174
+#define IMX6SLL_CLK_GPIO3               175
+#define IMX6SLL_CLK_GPIO4               176
+#define IMX6SLL_CLK_GPIO5               177
+#define IMX6SLL_CLK_GPIO6               178
+#define IMX6SLL_CLK_GPT_3M		179
+
+#define IMX6SLL_CLK_END			180
+
+#endif /* __DT_BINDINGS_CLOCK_IMX6SLL_H */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/imx6sx-clock.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/imx6sx-clock.h
new file mode 100644
index 0000000000000000000000000000000000000000..a248f928a30ab58740665edd7fdae4a64d36075b
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/imx6sx-clock.h
@@ -0,0 +1,284 @@
+/*
+ * Copyright (C) 2014-2015 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_IMX6SX_H
+#define __DT_BINDINGS_CLOCK_IMX6SX_H
+
+#define IMX6SX_CLK_DUMMY		0
+#define IMX6SX_CLK_CKIL			1
+#define IMX6SX_CLK_CKIH			2
+#define IMX6SX_CLK_OSC			3
+#define IMX6SX_CLK_PLL1_SYS		4
+#define IMX6SX_CLK_PLL2_BUS		5
+#define IMX6SX_CLK_PLL3_USB_OTG		6
+#define IMX6SX_CLK_PLL4_AUDIO		7
+#define IMX6SX_CLK_PLL5_VIDEO		8
+#define IMX6SX_CLK_PLL6_ENET		9
+#define IMX6SX_CLK_PLL7_USB_HOST	10
+#define IMX6SX_CLK_USBPHY1		11
+#define IMX6SX_CLK_USBPHY2		12
+#define IMX6SX_CLK_USBPHY1_GATE		13
+#define IMX6SX_CLK_USBPHY2_GATE		14
+#define IMX6SX_CLK_PCIE_REF		15
+#define IMX6SX_CLK_PCIE_REF_125M	16
+#define IMX6SX_CLK_ENET_REF		17
+#define IMX6SX_CLK_PLL2_PFD0		18
+#define IMX6SX_CLK_PLL2_PFD1		19
+#define IMX6SX_CLK_PLL2_PFD2		20
+#define IMX6SX_CLK_PLL2_PFD3		21
+#define IMX6SX_CLK_PLL3_PFD0		22
+#define IMX6SX_CLK_PLL3_PFD1		23
+#define IMX6SX_CLK_PLL3_PFD2		24
+#define IMX6SX_CLK_PLL3_PFD3		25
+#define IMX6SX_CLK_PLL2_198M		26
+#define IMX6SX_CLK_PLL3_120M		27
+#define IMX6SX_CLK_PLL3_80M		28
+#define IMX6SX_CLK_PLL3_60M		29
+#define IMX6SX_CLK_TWD			30
+#define IMX6SX_CLK_PLL4_POST_DIV	31
+#define IMX6SX_CLK_PLL4_AUDIO_DIV	32
+#define IMX6SX_CLK_PLL5_POST_DIV	33
+#define IMX6SX_CLK_PLL5_VIDEO_DIV	34
+#define IMX6SX_CLK_STEP			35
+#define IMX6SX_CLK_PLL1_SW		36
+#define IMX6SX_CLK_OCRAM_SEL		37
+#define IMX6SX_CLK_PERIPH_PRE		38
+#define IMX6SX_CLK_PERIPH2_PRE		39
+#define IMX6SX_CLK_PERIPH_CLK2_SEL	40
+#define IMX6SX_CLK_PERIPH2_CLK2_SEL	41
+#define IMX6SX_CLK_PCIE_AXI_SEL		42
+#define IMX6SX_CLK_GPU_AXI_SEL		43
+#define IMX6SX_CLK_GPU_CORE_SEL		44
+#define IMX6SX_CLK_EIM_SLOW_SEL		45
+#define IMX6SX_CLK_USDHC1_SEL		46
+#define IMX6SX_CLK_USDHC2_SEL		47
+#define IMX6SX_CLK_USDHC3_SEL		48
+#define IMX6SX_CLK_USDHC4_SEL		49
+#define IMX6SX_CLK_SSI1_SEL		50
+#define IMX6SX_CLK_SSI2_SEL		51
+#define IMX6SX_CLK_SSI3_SEL		52
+#define IMX6SX_CLK_QSPI1_SEL		53
+#define IMX6SX_CLK_PERCLK_SEL		54
+#define IMX6SX_CLK_VID_SEL		55
+#define IMX6SX_CLK_ESAI_SEL		56
+#define IMX6SX_CLK_LDB_DI0_DIV_SEL	57
+#define IMX6SX_CLK_LDB_DI1_DIV_SEL	58
+#define IMX6SX_CLK_CAN_SEL		59
+#define IMX6SX_CLK_UART_SEL		60
+#define IMX6SX_CLK_QSPI2_SEL		61
+#define IMX6SX_CLK_LDB_DI1_SEL		62
+#define IMX6SX_CLK_LDB_DI0_SEL		63
+#define IMX6SX_CLK_SPDIF_SEL		64
+#define IMX6SX_CLK_AUDIO_SEL		65
+#define IMX6SX_CLK_ENET_PRE_SEL		66
+#define IMX6SX_CLK_ENET_SEL		67
+#define IMX6SX_CLK_M4_PRE_SEL		68
+#define IMX6SX_CLK_M4_SEL		69
+#define IMX6SX_CLK_ECSPI_SEL		70
+#define IMX6SX_CLK_LCDIF1_PRE_SEL	71
+#define IMX6SX_CLK_LCDIF2_PRE_SEL	72
+#define IMX6SX_CLK_LCDIF1_SEL		73
+#define IMX6SX_CLK_LCDIF2_SEL		74
+#define IMX6SX_CLK_DISPLAY_SEL		75
+#define IMX6SX_CLK_CSI_SEL		76
+#define IMX6SX_CLK_CKO1_SEL		77
+#define IMX6SX_CLK_CKO2_SEL		78
+#define IMX6SX_CLK_CKO			79
+#define IMX6SX_CLK_PERIPH_CLK2		80
+#define IMX6SX_CLK_PERIPH2_CLK2		81
+#define IMX6SX_CLK_IPG			82
+#define IMX6SX_CLK_GPU_CORE_PODF	83
+#define IMX6SX_CLK_GPU_AXI_PODF		84
+#define IMX6SX_CLK_LCDIF1_PODF		85
+#define IMX6SX_CLK_QSPI1_PODF		86
+#define IMX6SX_CLK_EIM_SLOW_PODF	87
+#define IMX6SX_CLK_LCDIF2_PODF		88
+#define IMX6SX_CLK_PERCLK		89
+#define IMX6SX_CLK_VID_PODF		90
+#define IMX6SX_CLK_CAN_PODF		91
+#define IMX6SX_CLK_USDHC1_PODF		92
+#define IMX6SX_CLK_USDHC2_PODF		93
+#define IMX6SX_CLK_USDHC3_PODF		94
+#define IMX6SX_CLK_USDHC4_PODF		95
+#define IMX6SX_CLK_UART_PODF		96
+#define IMX6SX_CLK_ESAI_PRED		97
+#define IMX6SX_CLK_ESAI_PODF		98
+#define IMX6SX_CLK_SSI3_PRED		99
+#define IMX6SX_CLK_SSI3_PODF		100
+#define IMX6SX_CLK_SSI1_PRED		101
+#define IMX6SX_CLK_SSI1_PODF		102
+#define IMX6SX_CLK_QSPI2_PRED		103
+#define IMX6SX_CLK_QSPI2_PODF		104
+#define IMX6SX_CLK_SSI2_PRED		105
+#define IMX6SX_CLK_SSI2_PODF		106
+#define IMX6SX_CLK_SPDIF_PRED		107
+#define IMX6SX_CLK_SPDIF_PODF		108
+#define IMX6SX_CLK_AUDIO_PRED		109
+#define IMX6SX_CLK_AUDIO_PODF		110
+#define IMX6SX_CLK_ENET_PODF		111
+#define IMX6SX_CLK_M4_PODF		112
+#define IMX6SX_CLK_ECSPI_PODF		113
+#define IMX6SX_CLK_LCDIF1_PRED		114
+#define IMX6SX_CLK_LCDIF2_PRED		115
+#define IMX6SX_CLK_DISPLAY_PODF		116
+#define IMX6SX_CLK_CSI_PODF		117
+#define IMX6SX_CLK_LDB_DI0_DIV_3_5	118
+#define IMX6SX_CLK_LDB_DI0_DIV_7	119
+#define IMX6SX_CLK_LDB_DI1_DIV_3_5	120
+#define IMX6SX_CLK_LDB_DI1_DIV_7	121
+#define IMX6SX_CLK_CKO1_PODF		122
+#define IMX6SX_CLK_CKO2_PODF		123
+#define IMX6SX_CLK_PERIPH		124
+#define IMX6SX_CLK_PERIPH2		125
+#define IMX6SX_CLK_OCRAM		126
+#define IMX6SX_CLK_AHB			127
+#define IMX6SX_CLK_MMDC_PODF		128
+#define IMX6SX_CLK_ARM			129
+#define IMX6SX_CLK_AIPS_TZ1		130
+#define IMX6SX_CLK_AIPS_TZ2		131
+#define IMX6SX_CLK_APBH_DMA		132
+#define IMX6SX_CLK_ASRC_GATE		133
+#define IMX6SX_CLK_CAAM_MEM		134
+#define IMX6SX_CLK_CAAM_ACLK		135
+#define IMX6SX_CLK_CAAM_IPG		136
+#define IMX6SX_CLK_CAN1_IPG		137
+#define IMX6SX_CLK_CAN1_SERIAL		138
+#define IMX6SX_CLK_CAN2_IPG		139
+#define IMX6SX_CLK_CAN2_SERIAL		140
+#define IMX6SX_CLK_CPU_DEBUG		141
+#define IMX6SX_CLK_DCIC1		142
+#define IMX6SX_CLK_DCIC2		143
+#define IMX6SX_CLK_AIPS_TZ3		144
+#define IMX6SX_CLK_ECSPI1		145
+#define IMX6SX_CLK_ECSPI2		146
+#define IMX6SX_CLK_ECSPI3		147
+#define IMX6SX_CLK_ECSPI4		148
+#define IMX6SX_CLK_ECSPI5		149
+#define IMX6SX_CLK_EPIT1		150
+#define IMX6SX_CLK_EPIT2		151
+#define IMX6SX_CLK_ESAI_EXTAL		152
+#define IMX6SX_CLK_WAKEUP		153
+#define IMX6SX_CLK_GPT_BUS		154
+#define IMX6SX_CLK_GPT_SERIAL		155
+#define IMX6SX_CLK_GPU			156
+#define IMX6SX_CLK_OCRAM_S		157
+#define IMX6SX_CLK_CANFD		158
+#define IMX6SX_CLK_CSI			159
+#define IMX6SX_CLK_I2C1			160
+#define IMX6SX_CLK_I2C2			161
+#define IMX6SX_CLK_I2C3			162
+#define IMX6SX_CLK_OCOTP		163
+#define IMX6SX_CLK_IOMUXC		164
+#define IMX6SX_CLK_IPMUX1		165
+#define IMX6SX_CLK_IPMUX2		166
+#define IMX6SX_CLK_IPMUX3		167
+#define IMX6SX_CLK_TZASC1		168
+#define IMX6SX_CLK_LCDIF_APB		169
+#define IMX6SX_CLK_PXP_AXI		170
+#define IMX6SX_CLK_M4			171
+#define IMX6SX_CLK_ENET			172
+#define IMX6SX_CLK_DISPLAY_AXI		173
+#define IMX6SX_CLK_LCDIF2_PIX		174
+#define IMX6SX_CLK_LCDIF1_PIX		175
+#define IMX6SX_CLK_LDB_DI0		176
+#define IMX6SX_CLK_QSPI1		177
+#define IMX6SX_CLK_MLB			178
+#define IMX6SX_CLK_MMDC_P0_FAST		179
+#define IMX6SX_CLK_MMDC_P0_IPG		180
+#define IMX6SX_CLK_AXI			181
+#define IMX6SX_CLK_PCIE_AXI		182
+#define IMX6SX_CLK_QSPI2		183
+#define IMX6SX_CLK_PER1_BCH		184
+#define IMX6SX_CLK_PER2_MAIN		185
+#define IMX6SX_CLK_PWM1			186
+#define IMX6SX_CLK_PWM2			187
+#define IMX6SX_CLK_PWM3			188
+#define IMX6SX_CLK_PWM4			189
+#define IMX6SX_CLK_GPMI_BCH_APB		190
+#define IMX6SX_CLK_GPMI_BCH		191
+#define IMX6SX_CLK_GPMI_IO		192
+#define IMX6SX_CLK_GPMI_APB		193
+#define IMX6SX_CLK_ROM			194
+#define IMX6SX_CLK_SDMA			195
+#define IMX6SX_CLK_SPBA			196
+#define IMX6SX_CLK_SPDIF		197
+#define IMX6SX_CLK_SSI1_IPG		198
+#define IMX6SX_CLK_SSI2_IPG		199
+#define IMX6SX_CLK_SSI3_IPG		200
+#define IMX6SX_CLK_SSI1			201
+#define IMX6SX_CLK_SSI2			202
+#define IMX6SX_CLK_SSI3			203
+#define IMX6SX_CLK_UART_IPG		204
+#define IMX6SX_CLK_UART_SERIAL		205
+#define IMX6SX_CLK_SAI1			206
+#define IMX6SX_CLK_SAI2			207
+#define IMX6SX_CLK_USBOH3		208
+#define IMX6SX_CLK_USDHC1		209
+#define IMX6SX_CLK_USDHC2		210
+#define IMX6SX_CLK_USDHC3		211
+#define IMX6SX_CLK_USDHC4		212
+#define IMX6SX_CLK_EIM_SLOW		213
+#define IMX6SX_CLK_PWM8			214
+#define IMX6SX_CLK_VADC			215
+#define IMX6SX_CLK_GIS			216
+#define IMX6SX_CLK_I2C4			217
+#define IMX6SX_CLK_PWM5			218
+#define IMX6SX_CLK_PWM6			219
+#define IMX6SX_CLK_PWM7			220
+#define IMX6SX_CLK_CKO1			221
+#define IMX6SX_CLK_CKO2			222
+#define IMX6SX_CLK_IPP_DI0		223
+#define IMX6SX_CLK_IPP_DI1		224
+#define IMX6SX_CLK_ENET_AHB		225
+#define IMX6SX_CLK_OCRAM_PODF		226
+#define IMX6SX_CLK_GPT_3M		227
+#define IMX6SX_CLK_ENET_PTP		228
+#define IMX6SX_CLK_ENET_PTP_REF		229
+#define IMX6SX_CLK_ENET2_REF		230
+#define IMX6SX_CLK_ENET2_REF_125M	231
+#define IMX6SX_CLK_AUDIO		232
+#define IMX6SX_CLK_LVDS1_SEL		233
+#define IMX6SX_CLK_LVDS1_OUT		234
+#define IMX6SX_CLK_ASRC_IPG		235
+#define IMX6SX_CLK_ASRC_MEM		236
+#define IMX6SX_CLK_SAI1_IPG		237
+#define IMX6SX_CLK_SAI2_IPG		238
+#define IMX6SX_CLK_ESAI_IPG		239
+#define IMX6SX_CLK_ESAI_MEM		240
+#define IMX6SX_CLK_LVDS1_IN		241
+#define IMX6SX_CLK_ANACLK1		242
+#define IMX6SX_PLL1_BYPASS_SRC		243
+#define IMX6SX_PLL2_BYPASS_SRC		244
+#define IMX6SX_PLL3_BYPASS_SRC		245
+#define IMX6SX_PLL4_BYPASS_SRC		246
+#define IMX6SX_PLL5_BYPASS_SRC		247
+#define IMX6SX_PLL6_BYPASS_SRC		248
+#define IMX6SX_PLL7_BYPASS_SRC		249
+#define IMX6SX_CLK_PLL1			250
+#define IMX6SX_CLK_PLL2			251
+#define IMX6SX_CLK_PLL3			252
+#define IMX6SX_CLK_PLL4			253
+#define IMX6SX_CLK_PLL5			254
+#define IMX6SX_CLK_PLL6			255
+#define IMX6SX_CLK_PLL7			256
+#define IMX6SX_PLL1_BYPASS		257
+#define IMX6SX_PLL2_BYPASS		258
+#define IMX6SX_PLL3_BYPASS		259
+#define IMX6SX_PLL4_BYPASS		260
+#define IMX6SX_PLL5_BYPASS		261
+#define IMX6SX_PLL6_BYPASS		262
+#define IMX6SX_PLL7_BYPASS		263
+#define IMX6SX_CLK_SPDIF_GCLK		264
+#define IMX6SX_CLK_LVDS2_SEL		265
+#define IMX6SX_CLK_LVDS2_OUT		266
+#define IMX6SX_CLK_LVDS2_IN		267
+#define IMX6SX_CLK_ANACLK2		268
+#define IMX6SX_CLK_CLK_END		269
+
+#endif /* __DT_BINDINGS_CLOCK_IMX6SX_H */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/imx6ul-clock.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/imx6ul-clock.h
new file mode 100644
index 0000000000000000000000000000000000000000..f8e0476a3a0eb00189b102b06f7566738d929184
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/imx6ul-clock.h
@@ -0,0 +1,265 @@
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_IMX6UL_H
+#define __DT_BINDINGS_CLOCK_IMX6UL_H
+
+#define IMX6UL_CLK_DUMMY		0
+#define IMX6UL_CLK_CKIL			1
+#define IMX6UL_CLK_CKIH			2
+#define IMX6UL_CLK_OSC			3
+#define IMX6UL_PLL1_BYPASS_SRC		4
+#define IMX6UL_PLL2_BYPASS_SRC		5
+#define IMX6UL_PLL3_BYPASS_SRC		6
+#define IMX6UL_PLL4_BYPASS_SRC		7
+#define IMX6UL_PLL5_BYPASS_SRC		8
+#define IMX6UL_PLL6_BYPASS_SRC		9
+#define IMX6UL_PLL7_BYPASS_SRC		10
+#define IMX6UL_CLK_PLL1			11
+#define IMX6UL_CLK_PLL2			12
+#define IMX6UL_CLK_PLL3			13
+#define IMX6UL_CLK_PLL4			14
+#define IMX6UL_CLK_PLL5			15
+#define IMX6UL_CLK_PLL6			16
+#define IMX6UL_CLK_PLL7			17
+#define IMX6UL_PLL1_BYPASS		18
+#define IMX6UL_PLL2_BYPASS		19
+#define IMX6UL_PLL3_BYPASS		20
+#define IMX6UL_PLL4_BYPASS		21
+#define IMX6UL_PLL5_BYPASS		22
+#define IMX6UL_PLL6_BYPASS		23
+#define IMX6UL_PLL7_BYPASS		24
+#define IMX6UL_CLK_PLL1_SYS		25
+#define IMX6UL_CLK_PLL2_BUS		26
+#define IMX6UL_CLK_PLL3_USB_OTG		27
+#define IMX6UL_CLK_PLL4_AUDIO		28
+#define IMX6UL_CLK_PLL5_VIDEO		29
+#define IMX6UL_CLK_PLL6_ENET		30
+#define IMX6UL_CLK_PLL7_USB_HOST	31
+#define IMX6UL_CLK_USBPHY1		32
+#define IMX6UL_CLK_USBPHY2		33
+#define IMX6UL_CLK_USBPHY1_GATE		34
+#define IMX6UL_CLK_USBPHY2_GATE		35
+#define IMX6UL_CLK_PLL2_PFD0		36
+#define IMX6UL_CLK_PLL2_PFD1		37
+#define IMX6UL_CLK_PLL2_PFD2		38
+#define IMX6UL_CLK_PLL2_PFD3		39
+#define IMX6UL_CLK_PLL3_PFD0		40
+#define IMX6UL_CLK_PLL3_PFD1		41
+#define IMX6UL_CLK_PLL3_PFD2		42
+#define IMX6UL_CLK_PLL3_PFD3		43
+#define IMX6UL_CLK_ENET_REF		44
+#define IMX6UL_CLK_ENET2_REF		45
+#define IMX6UL_CLK_ENET2_REF_125M	46
+#define IMX6UL_CLK_ENET_PTP_REF		47
+#define IMX6UL_CLK_ENET_PTP		48
+#define IMX6UL_CLK_PLL4_POST_DIV	49
+#define IMX6UL_CLK_PLL4_AUDIO_DIV	50
+#define IMX6UL_CLK_PLL5_POST_DIV	51
+#define IMX6UL_CLK_PLL5_VIDEO_DIV	52
+#define IMX6UL_CLK_PLL2_198M		53
+#define IMX6UL_CLK_PLL3_80M		54
+#define IMX6UL_CLK_PLL3_60M		55
+#define IMX6UL_CLK_STEP			56
+#define IMX6UL_CLK_PLL1_SW		57
+#define IMX6UL_CLK_AXI_ALT_SEL		58
+#define IMX6UL_CLK_AXI_SEL		59
+#define IMX6UL_CLK_PERIPH_PRE		60
+#define IMX6UL_CLK_PERIPH2_PRE		61
+#define IMX6UL_CLK_PERIPH_CLK2_SEL	62
+#define IMX6UL_CLK_PERIPH2_CLK2_SEL	63
+#define IMX6UL_CLK_USDHC1_SEL		64
+#define IMX6UL_CLK_USDHC2_SEL		65
+#define IMX6UL_CLK_BCH_SEL		66
+#define IMX6UL_CLK_GPMI_SEL		67
+#define IMX6UL_CLK_EIM_SLOW_SEL		68
+#define IMX6UL_CLK_SPDIF_SEL		69
+#define IMX6UL_CLK_SAI1_SEL		70
+#define IMX6UL_CLK_SAI2_SEL		71
+#define IMX6UL_CLK_SAI3_SEL		72
+#define IMX6UL_CLK_LCDIF_PRE_SEL	73
+#define IMX6UL_CLK_SIM_PRE_SEL		74
+#define IMX6UL_CLK_LDB_DI0_SEL		75
+#define IMX6UL_CLK_LDB_DI1_SEL		76
+#define IMX6UL_CLK_ENFC_SEL		77
+#define IMX6UL_CLK_CAN_SEL		78
+#define IMX6UL_CLK_ECSPI_SEL		79
+#define IMX6UL_CLK_UART_SEL		80
+#define IMX6UL_CLK_QSPI1_SEL		81
+#define IMX6UL_CLK_PERCLK_SEL		82
+#define IMX6UL_CLK_LCDIF_SEL		83
+#define IMX6UL_CLK_SIM_SEL		84
+#define IMX6UL_CLK_PERIPH		85
+#define IMX6UL_CLK_PERIPH2		86
+#define IMX6UL_CLK_LDB_DI0_DIV_3_5	87
+#define IMX6UL_CLK_LDB_DI0_DIV_7	88
+#define IMX6UL_CLK_LDB_DI1_DIV_3_5	89
+#define IMX6UL_CLK_LDB_DI1_DIV_7	90
+#define IMX6UL_CLK_LDB_DI0_DIV_SEL	91
+#define IMX6UL_CLK_LDB_DI1_DIV_SEL	92
+#define IMX6UL_CLK_ARM			93
+#define IMX6UL_CLK_PERIPH_CLK2		94
+#define IMX6UL_CLK_PERIPH2_CLK2		95
+#define IMX6UL_CLK_AHB			96
+#define IMX6UL_CLK_MMDC_PODF		97
+#define IMX6UL_CLK_AXI_PODF		98
+#define IMX6UL_CLK_PERCLK		99
+#define IMX6UL_CLK_IPG			100
+#define IMX6UL_CLK_USDHC1_PODF		101
+#define IMX6UL_CLK_USDHC2_PODF		102
+#define IMX6UL_CLK_BCH_PODF		103
+#define IMX6UL_CLK_GPMI_PODF		104
+#define IMX6UL_CLK_EIM_SLOW_PODF	105
+#define IMX6UL_CLK_SPDIF_PRED		106
+#define IMX6UL_CLK_SPDIF_PODF		107
+#define IMX6UL_CLK_SAI1_PRED		108
+#define IMX6UL_CLK_SAI1_PODF		109
+#define IMX6UL_CLK_SAI2_PRED		110
+#define IMX6UL_CLK_SAI2_PODF		111
+#define IMX6UL_CLK_SAI3_PRED		112
+#define IMX6UL_CLK_SAI3_PODF		113
+#define IMX6UL_CLK_LCDIF_PRED		114
+#define IMX6UL_CLK_LCDIF_PODF		115
+#define IMX6UL_CLK_SIM_PODF		116
+#define IMX6UL_CLK_QSPI1_PDOF		117
+#define IMX6UL_CLK_ENFC_PRED		118
+#define IMX6UL_CLK_ENFC_PODF		119
+#define IMX6UL_CLK_CAN_PODF		120
+#define IMX6UL_CLK_ECSPI_PODF		121
+#define IMX6UL_CLK_UART_PODF		122
+#define IMX6UL_CLK_ADC1			123
+#define IMX6UL_CLK_ADC2			124
+#define IMX6UL_CLK_AIPSTZ1		125
+#define IMX6UL_CLK_AIPSTZ2		126
+#define IMX6UL_CLK_AIPSTZ3		127
+#define IMX6UL_CLK_APBHDMA		128
+#define IMX6UL_CLK_ASRC_IPG		129
+#define IMX6UL_CLK_ASRC_MEM		130
+#define IMX6UL_CLK_GPMI_BCH_APB		131
+#define IMX6UL_CLK_GPMI_BCH		132
+#define IMX6UL_CLK_GPMI_IO		133
+#define IMX6UL_CLK_GPMI_APB		134
+#define IMX6UL_CLK_CAAM_MEM		135
+#define IMX6UL_CLK_CAAM_ACLK		136
+#define IMX6UL_CLK_CAAM_IPG		137
+#define IMX6UL_CLK_CSI			138
+#define IMX6UL_CLK_ECSPI1		139
+#define IMX6UL_CLK_ECSPI2		140
+#define IMX6UL_CLK_ECSPI3		141
+#define IMX6UL_CLK_ECSPI4		142
+#define IMX6UL_CLK_EIM			143
+#define IMX6UL_CLK_ENET			144
+#define IMX6UL_CLK_ENET_AHB		145
+#define IMX6UL_CLK_EPIT1		146
+#define IMX6UL_CLK_EPIT2		147
+#define IMX6UL_CLK_CAN1_IPG		148
+#define IMX6UL_CLK_CAN1_SERIAL		149
+#define IMX6UL_CLK_CAN2_IPG		150
+#define IMX6UL_CLK_CAN2_SERIAL		151
+#define IMX6UL_CLK_GPT1_BUS		152
+#define IMX6UL_CLK_GPT1_SERIAL		153
+#define IMX6UL_CLK_GPT2_BUS		154
+#define IMX6UL_CLK_GPT2_SERIAL		155
+#define IMX6UL_CLK_I2C1			156
+#define IMX6UL_CLK_I2C2			157
+#define IMX6UL_CLK_I2C3			158
+#define IMX6UL_CLK_I2C4			159
+#define IMX6UL_CLK_IOMUXC		160
+#define IMX6UL_CLK_LCDIF_APB		161
+#define IMX6UL_CLK_LCDIF_PIX		162
+#define IMX6UL_CLK_MMDC_P0_FAST		163
+#define IMX6UL_CLK_MMDC_P0_IPG		164
+#define IMX6UL_CLK_OCOTP		165
+#define IMX6UL_CLK_OCRAM		166
+#define IMX6UL_CLK_PWM1			167
+#define IMX6UL_CLK_PWM2			168
+#define IMX6UL_CLK_PWM3			169
+#define IMX6UL_CLK_PWM4			170
+#define IMX6UL_CLK_PWM5			171
+#define IMX6UL_CLK_PWM6			172
+#define IMX6UL_CLK_PWM7			173
+#define IMX6UL_CLK_PWM8			174
+#define IMX6UL_CLK_PXP			175
+#define IMX6UL_CLK_QSPI			176
+#define IMX6UL_CLK_ROM			177
+#define IMX6UL_CLK_SAI1			178
+#define IMX6UL_CLK_SAI1_IPG		179
+#define IMX6UL_CLK_SAI2			180
+#define IMX6UL_CLK_SAI2_IPG		181
+#define IMX6UL_CLK_SAI3			182
+#define IMX6UL_CLK_SAI3_IPG		183
+#define IMX6UL_CLK_SDMA			184
+#define IMX6UL_CLK_SIM			185
+#define IMX6UL_CLK_SIM_S		186
+#define IMX6UL_CLK_SPBA			187
+#define IMX6UL_CLK_SPDIF		188
+#define IMX6UL_CLK_UART1_IPG		189
+#define IMX6UL_CLK_UART1_SERIAL		190
+#define IMX6UL_CLK_UART2_IPG		191
+#define IMX6UL_CLK_UART2_SERIAL		192
+#define IMX6UL_CLK_UART3_IPG		193
+#define IMX6UL_CLK_UART3_SERIAL		194
+#define IMX6UL_CLK_UART4_IPG		195
+#define IMX6UL_CLK_UART4_SERIAL		196
+#define IMX6UL_CLK_UART5_IPG		197
+#define IMX6UL_CLK_UART5_SERIAL		198
+#define IMX6UL_CLK_UART6_IPG		199
+#define IMX6UL_CLK_UART6_SERIAL		200
+#define IMX6UL_CLK_UART7_IPG		201
+#define IMX6UL_CLK_UART7_SERIAL		202
+#define IMX6UL_CLK_UART8_IPG		203
+#define IMX6UL_CLK_UART8_SERIAL		204
+#define IMX6UL_CLK_USBOH3		205
+#define IMX6UL_CLK_USDHC1		206
+#define IMX6UL_CLK_USDHC2		207
+#define IMX6UL_CLK_WDOG1		208
+#define IMX6UL_CLK_WDOG2		209
+#define IMX6UL_CLK_WDOG3		210
+#define IMX6UL_CLK_LDB_DI0		211
+#define IMX6UL_CLK_AXI			212
+#define IMX6UL_CLK_SPDIF_GCLK		213
+#define IMX6UL_CLK_GPT_3M		214
+#define IMX6UL_CLK_SIM2			215
+#define IMX6UL_CLK_SIM1			216
+#define IMX6UL_CLK_IPP_DI0		217
+#define IMX6UL_CLK_IPP_DI1		218
+#define IMX6UL_CA7_SECONDARY_SEL	219
+#define IMX6UL_CLK_PER_BCH		220
+#define IMX6UL_CLK_CSI_SEL		221
+#define IMX6UL_CLK_CSI_PODF		222
+#define IMX6UL_CLK_PLL3_120M		223
+#define IMX6UL_CLK_KPP			224
+#define IMX6ULL_CLK_ESAI_PRED		225
+#define IMX6ULL_CLK_ESAI_PODF		226
+#define IMX6ULL_CLK_ESAI_EXTAL		227
+#define IMX6ULL_CLK_ESAI_MEM		228
+#define IMX6ULL_CLK_ESAI_IPG		229
+#define IMX6ULL_CLK_DCP_CLK		230
+#define IMX6ULL_CLK_EPDC_PRE_SEL	231
+#define IMX6ULL_CLK_EPDC_SEL		232
+#define IMX6ULL_CLK_EPDC_PODF		233
+#define IMX6ULL_CLK_EPDC_ACLK		234
+#define IMX6ULL_CLK_EPDC_PIX		235
+#define IMX6ULL_CLK_ESAI_SEL		236
+#define IMX6UL_CLK_CKO1_SEL		237
+#define IMX6UL_CLK_CKO1_PODF		238
+#define IMX6UL_CLK_CKO1			239
+#define IMX6UL_CLK_CKO2_SEL		240
+#define IMX6UL_CLK_CKO2_PODF		241
+#define IMX6UL_CLK_CKO2			242
+#define IMX6UL_CLK_CKO			243
+#define IMX6UL_CLK_GPIO1		244
+#define IMX6UL_CLK_GPIO2		245
+#define IMX6UL_CLK_GPIO3		246
+#define IMX6UL_CLK_GPIO4		247
+#define IMX6UL_CLK_GPIO5		248
+
+#define IMX6UL_CLK_END			249
+
+#endif /* __DT_BINDINGS_CLOCK_IMX6UL_H */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/imx7d-clock.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/imx7d-clock.h
new file mode 100644
index 0000000000000000000000000000000000000000..89eadb96da2ebfd5669902c9383e68b020daae1d
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/imx7d-clock.h
@@ -0,0 +1,463 @@
+/*
+ * Copyright (C) 2014-2015 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_IMX7D_H
+#define __DT_BINDINGS_CLOCK_IMX7D_H
+
+#define IMX7D_OSC_24M_CLK		0
+#define IMX7D_PLL_ARM_MAIN		1
+#define IMX7D_PLL_ARM_MAIN_CLK		2
+#define IMX7D_PLL_ARM_MAIN_SRC		3
+#define IMX7D_PLL_ARM_MAIN_BYPASS	4
+#define IMX7D_PLL_SYS_MAIN		5
+#define IMX7D_PLL_SYS_MAIN_CLK		6
+#define IMX7D_PLL_SYS_MAIN_SRC		7
+#define IMX7D_PLL_SYS_MAIN_BYPASS	8
+#define IMX7D_PLL_SYS_MAIN_480M		9
+#define IMX7D_PLL_SYS_MAIN_240M		10
+#define IMX7D_PLL_SYS_MAIN_120M		11
+#define IMX7D_PLL_SYS_MAIN_480M_CLK	12
+#define IMX7D_PLL_SYS_MAIN_240M_CLK	13
+#define IMX7D_PLL_SYS_MAIN_120M_CLK	14
+#define IMX7D_PLL_SYS_PFD0_392M_CLK	15
+#define IMX7D_PLL_SYS_PFD0_196M		16
+#define IMX7D_PLL_SYS_PFD0_196M_CLK	17
+#define IMX7D_PLL_SYS_PFD1_332M_CLK	18
+#define IMX7D_PLL_SYS_PFD1_166M		19
+#define IMX7D_PLL_SYS_PFD1_166M_CLK	20
+#define IMX7D_PLL_SYS_PFD2_270M_CLK	21
+#define IMX7D_PLL_SYS_PFD2_135M		22
+#define IMX7D_PLL_SYS_PFD2_135M_CLK	23
+#define IMX7D_PLL_SYS_PFD3_CLK		24
+#define IMX7D_PLL_SYS_PFD4_CLK		25
+#define IMX7D_PLL_SYS_PFD5_CLK		26
+#define IMX7D_PLL_SYS_PFD6_CLK		27
+#define IMX7D_PLL_SYS_PFD7_CLK		28
+#define IMX7D_PLL_ENET_MAIN		29
+#define IMX7D_PLL_ENET_MAIN_CLK		30
+#define IMX7D_PLL_ENET_MAIN_SRC		31
+#define IMX7D_PLL_ENET_MAIN_BYPASS	32
+#define IMX7D_PLL_ENET_MAIN_500M	33
+#define IMX7D_PLL_ENET_MAIN_250M	34
+#define IMX7D_PLL_ENET_MAIN_125M	35
+#define IMX7D_PLL_ENET_MAIN_100M	36
+#define IMX7D_PLL_ENET_MAIN_50M		37
+#define IMX7D_PLL_ENET_MAIN_40M		38
+#define IMX7D_PLL_ENET_MAIN_25M		39
+#define IMX7D_PLL_ENET_MAIN_500M_CLK	40
+#define IMX7D_PLL_ENET_MAIN_250M_CLK	41
+#define IMX7D_PLL_ENET_MAIN_125M_CLK	42
+#define IMX7D_PLL_ENET_MAIN_100M_CLK	43
+#define IMX7D_PLL_ENET_MAIN_50M_CLK	44
+#define IMX7D_PLL_ENET_MAIN_40M_CLK	45
+#define IMX7D_PLL_ENET_MAIN_25M_CLK	46
+#define IMX7D_PLL_DRAM_MAIN		47
+#define IMX7D_PLL_DRAM_MAIN_CLK		48
+#define IMX7D_PLL_DRAM_MAIN_SRC		49
+#define IMX7D_PLL_DRAM_MAIN_BYPASS	50
+#define IMX7D_PLL_DRAM_MAIN_533M	51
+#define IMX7D_PLL_DRAM_MAIN_533M_CLK	52
+#define IMX7D_PLL_AUDIO_MAIN		53
+#define IMX7D_PLL_AUDIO_MAIN_CLK	54
+#define IMX7D_PLL_AUDIO_MAIN_SRC	55
+#define IMX7D_PLL_AUDIO_MAIN_BYPASS	56
+#define IMX7D_PLL_VIDEO_MAIN_CLK	57
+#define IMX7D_PLL_VIDEO_MAIN		58
+#define IMX7D_PLL_VIDEO_MAIN_SRC	59
+#define IMX7D_PLL_VIDEO_MAIN_BYPASS	60
+#define IMX7D_USB_MAIN_480M_CLK		61
+#define IMX7D_ARM_A7_ROOT_CLK		62
+#define IMX7D_ARM_A7_ROOT_SRC		63
+#define IMX7D_ARM_A7_ROOT_CG		64
+#define IMX7D_ARM_A7_ROOT_DIV		65
+#define IMX7D_ARM_M4_ROOT_CLK		66
+#define IMX7D_ARM_M4_ROOT_SRC		67
+#define IMX7D_ARM_M4_ROOT_CG		68
+#define IMX7D_ARM_M4_ROOT_DIV		69
+#define IMX7D_ARM_M0_ROOT_CLK		70	/* unused */
+#define IMX7D_ARM_M0_ROOT_SRC		71	/* unused */
+#define IMX7D_ARM_M0_ROOT_CG		72	/* unused */
+#define IMX7D_ARM_M0_ROOT_DIV		73	/* unused */
+#define IMX7D_MAIN_AXI_ROOT_CLK		74
+#define IMX7D_MAIN_AXI_ROOT_SRC		75
+#define IMX7D_MAIN_AXI_ROOT_CG		76
+#define IMX7D_MAIN_AXI_ROOT_DIV		77
+#define IMX7D_DISP_AXI_ROOT_CLK		78
+#define IMX7D_DISP_AXI_ROOT_SRC		79
+#define IMX7D_DISP_AXI_ROOT_CG		80
+#define IMX7D_DISP_AXI_ROOT_DIV		81
+#define IMX7D_ENET_AXI_ROOT_CLK		82
+#define IMX7D_ENET_AXI_ROOT_SRC		83
+#define IMX7D_ENET_AXI_ROOT_CG		84
+#define IMX7D_ENET_AXI_ROOT_DIV		85
+#define IMX7D_NAND_USDHC_BUS_ROOT_CLK	86
+#define IMX7D_NAND_USDHC_BUS_ROOT_SRC	87
+#define IMX7D_NAND_USDHC_BUS_ROOT_CG	88
+#define IMX7D_NAND_USDHC_BUS_ROOT_DIV	89
+#define IMX7D_AHB_CHANNEL_ROOT_CLK	90
+#define IMX7D_AHB_CHANNEL_ROOT_SRC	91
+#define IMX7D_AHB_CHANNEL_ROOT_CG	92
+#define IMX7D_AHB_CHANNEL_ROOT_DIV	93
+#define IMX7D_DRAM_PHYM_ROOT_CLK	94
+#define IMX7D_DRAM_PHYM_ROOT_SRC	95
+#define IMX7D_DRAM_PHYM_ROOT_CG		96
+#define IMX7D_DRAM_PHYM_ROOT_DIV	97
+#define IMX7D_DRAM_ROOT_CLK		98
+#define IMX7D_DRAM_ROOT_SRC		99
+#define IMX7D_DRAM_ROOT_CG		100
+#define IMX7D_DRAM_ROOT_DIV		101
+#define IMX7D_DRAM_PHYM_ALT_ROOT_CLK	102
+#define IMX7D_DRAM_PHYM_ALT_ROOT_SRC	103
+#define IMX7D_DRAM_PHYM_ALT_ROOT_CG	104
+#define IMX7D_DRAM_PHYM_ALT_ROOT_DIV	105
+#define IMX7D_DRAM_ALT_ROOT_CLK		106
+#define IMX7D_DRAM_ALT_ROOT_SRC		107
+#define IMX7D_DRAM_ALT_ROOT_CG		108
+#define IMX7D_DRAM_ALT_ROOT_DIV		109
+#define IMX7D_USB_HSIC_ROOT_CLK		110
+#define IMX7D_USB_HSIC_ROOT_SRC		111
+#define IMX7D_USB_HSIC_ROOT_CG		112
+#define IMX7D_USB_HSIC_ROOT_DIV		113
+#define IMX7D_PCIE_CTRL_ROOT_CLK	114
+#define IMX7D_PCIE_CTRL_ROOT_SRC	115
+#define IMX7D_PCIE_CTRL_ROOT_CG		116
+#define IMX7D_PCIE_CTRL_ROOT_DIV	117
+#define IMX7D_PCIE_PHY_ROOT_CLK		118
+#define IMX7D_PCIE_PHY_ROOT_SRC		119
+#define IMX7D_PCIE_PHY_ROOT_CG		120
+#define IMX7D_PCIE_PHY_ROOT_DIV		121
+#define IMX7D_EPDC_PIXEL_ROOT_CLK	122
+#define IMX7D_EPDC_PIXEL_ROOT_SRC	123
+#define IMX7D_EPDC_PIXEL_ROOT_CG	124
+#define IMX7D_EPDC_PIXEL_ROOT_DIV	125
+#define IMX7D_LCDIF_PIXEL_ROOT_CLK	126
+#define IMX7D_LCDIF_PIXEL_ROOT_SRC	127
+#define IMX7D_LCDIF_PIXEL_ROOT_CG	128
+#define IMX7D_LCDIF_PIXEL_ROOT_DIV	129
+#define IMX7D_MIPI_DSI_ROOT_CLK		130
+#define IMX7D_MIPI_DSI_ROOT_SRC		131
+#define IMX7D_MIPI_DSI_ROOT_CG		132
+#define IMX7D_MIPI_DSI_ROOT_DIV		133
+#define IMX7D_MIPI_CSI_ROOT_CLK		134
+#define IMX7D_MIPI_CSI_ROOT_SRC		135
+#define IMX7D_MIPI_CSI_ROOT_CG		136
+#define IMX7D_MIPI_CSI_ROOT_DIV		137
+#define IMX7D_MIPI_DPHY_ROOT_CLK	138
+#define IMX7D_MIPI_DPHY_ROOT_SRC	139
+#define IMX7D_MIPI_DPHY_ROOT_CG		140
+#define IMX7D_MIPI_DPHY_ROOT_DIV	141
+#define IMX7D_SAI1_ROOT_CLK		142
+#define IMX7D_SAI1_ROOT_SRC		143
+#define IMX7D_SAI1_ROOT_CG		144
+#define IMX7D_SAI1_ROOT_DIV		145
+#define IMX7D_SAI2_ROOT_CLK		146
+#define IMX7D_SAI2_ROOT_SRC		147
+#define IMX7D_SAI2_ROOT_CG		148
+#define IMX7D_SAI2_ROOT_DIV		149
+#define IMX7D_SAI3_ROOT_CLK		150
+#define IMX7D_SAI3_ROOT_SRC		151
+#define IMX7D_SAI3_ROOT_CG		152
+#define IMX7D_SAI3_ROOT_DIV		153
+#define IMX7D_SPDIF_ROOT_CLK		154
+#define IMX7D_SPDIF_ROOT_SRC		155
+#define IMX7D_SPDIF_ROOT_CG		156
+#define IMX7D_SPDIF_ROOT_DIV		157
+#define IMX7D_ENET1_IPG_ROOT_CLK        158
+#define IMX7D_ENET1_REF_ROOT_SRC	159
+#define IMX7D_ENET1_REF_ROOT_CG		160
+#define IMX7D_ENET1_REF_ROOT_DIV	161
+#define IMX7D_ENET1_TIME_ROOT_CLK	162
+#define IMX7D_ENET1_TIME_ROOT_SRC	163
+#define IMX7D_ENET1_TIME_ROOT_CG	164
+#define IMX7D_ENET1_TIME_ROOT_DIV	165
+#define IMX7D_ENET2_IPG_ROOT_CLK        166
+#define IMX7D_ENET2_REF_ROOT_SRC	167
+#define IMX7D_ENET2_REF_ROOT_CG		168
+#define IMX7D_ENET2_REF_ROOT_DIV	169
+#define IMX7D_ENET2_TIME_ROOT_CLK	170
+#define IMX7D_ENET2_TIME_ROOT_SRC	171
+#define IMX7D_ENET2_TIME_ROOT_CG	172
+#define IMX7D_ENET2_TIME_ROOT_DIV	173
+#define IMX7D_ENET_PHY_REF_ROOT_CLK	174
+#define IMX7D_ENET_PHY_REF_ROOT_SRC	175
+#define IMX7D_ENET_PHY_REF_ROOT_CG	176
+#define IMX7D_ENET_PHY_REF_ROOT_DIV	177
+#define IMX7D_EIM_ROOT_CLK		178
+#define IMX7D_EIM_ROOT_SRC		179
+#define IMX7D_EIM_ROOT_CG		180
+#define IMX7D_EIM_ROOT_DIV		181
+#define IMX7D_NAND_ROOT_CLK		182
+#define IMX7D_NAND_ROOT_SRC		183
+#define IMX7D_NAND_ROOT_CG		184
+#define IMX7D_NAND_ROOT_DIV		185
+#define IMX7D_QSPI_ROOT_CLK		186
+#define IMX7D_QSPI_ROOT_SRC		187
+#define IMX7D_QSPI_ROOT_CG		188
+#define IMX7D_QSPI_ROOT_DIV		189
+#define IMX7D_USDHC1_ROOT_CLK		190
+#define IMX7D_USDHC1_ROOT_SRC		191
+#define IMX7D_USDHC1_ROOT_CG		192
+#define IMX7D_USDHC1_ROOT_DIV		193
+#define IMX7D_USDHC2_ROOT_CLK		194
+#define IMX7D_USDHC2_ROOT_SRC		195
+#define IMX7D_USDHC2_ROOT_CG		196
+#define IMX7D_USDHC2_ROOT_DIV		197
+#define IMX7D_USDHC3_ROOT_CLK		198
+#define IMX7D_USDHC3_ROOT_SRC		199
+#define IMX7D_USDHC3_ROOT_CG		200
+#define IMX7D_USDHC3_ROOT_DIV		201
+#define IMX7D_CAN1_ROOT_CLK		202
+#define IMX7D_CAN1_ROOT_SRC		203
+#define IMX7D_CAN1_ROOT_CG		204
+#define IMX7D_CAN1_ROOT_DIV		205
+#define IMX7D_CAN2_ROOT_CLK		206
+#define IMX7D_CAN2_ROOT_SRC		207
+#define IMX7D_CAN2_ROOT_CG		208
+#define IMX7D_CAN2_ROOT_DIV		209
+#define IMX7D_I2C1_ROOT_CLK		210
+#define IMX7D_I2C1_ROOT_SRC		211
+#define IMX7D_I2C1_ROOT_CG		212
+#define IMX7D_I2C1_ROOT_DIV		213
+#define IMX7D_I2C2_ROOT_CLK		214
+#define IMX7D_I2C2_ROOT_SRC		215
+#define IMX7D_I2C2_ROOT_CG		216
+#define IMX7D_I2C2_ROOT_DIV		217
+#define IMX7D_I2C3_ROOT_CLK		218
+#define IMX7D_I2C3_ROOT_SRC		219
+#define IMX7D_I2C3_ROOT_CG		220
+#define IMX7D_I2C3_ROOT_DIV		221
+#define IMX7D_I2C4_ROOT_CLK		222
+#define IMX7D_I2C4_ROOT_SRC		223
+#define IMX7D_I2C4_ROOT_CG		224
+#define IMX7D_I2C4_ROOT_DIV		225
+#define IMX7D_UART1_ROOT_CLK		226
+#define IMX7D_UART1_ROOT_SRC		227
+#define IMX7D_UART1_ROOT_CG		228
+#define IMX7D_UART1_ROOT_DIV		229
+#define IMX7D_UART2_ROOT_CLK		230
+#define IMX7D_UART2_ROOT_SRC		231
+#define IMX7D_UART2_ROOT_CG		232
+#define IMX7D_UART2_ROOT_DIV		233
+#define IMX7D_UART3_ROOT_CLK		234
+#define IMX7D_UART3_ROOT_SRC		235
+#define IMX7D_UART3_ROOT_CG		236
+#define IMX7D_UART3_ROOT_DIV		237
+#define IMX7D_UART4_ROOT_CLK		238
+#define IMX7D_UART4_ROOT_SRC		239
+#define IMX7D_UART4_ROOT_CG		240
+#define IMX7D_UART4_ROOT_DIV		241
+#define IMX7D_UART5_ROOT_CLK		242
+#define IMX7D_UART5_ROOT_SRC		243
+#define IMX7D_UART5_ROOT_CG		244
+#define IMX7D_UART5_ROOT_DIV		245
+#define IMX7D_UART6_ROOT_CLK		246
+#define IMX7D_UART6_ROOT_SRC		247
+#define IMX7D_UART6_ROOT_CG		248
+#define IMX7D_UART6_ROOT_DIV		249
+#define IMX7D_UART7_ROOT_CLK		250
+#define IMX7D_UART7_ROOT_SRC		251
+#define IMX7D_UART7_ROOT_CG		252
+#define IMX7D_UART7_ROOT_DIV		253
+#define IMX7D_ECSPI1_ROOT_CLK		254
+#define IMX7D_ECSPI1_ROOT_SRC		255
+#define IMX7D_ECSPI1_ROOT_CG		256
+#define IMX7D_ECSPI1_ROOT_DIV		257
+#define IMX7D_ECSPI2_ROOT_CLK		258
+#define IMX7D_ECSPI2_ROOT_SRC		259
+#define IMX7D_ECSPI2_ROOT_CG		260
+#define IMX7D_ECSPI2_ROOT_DIV		261
+#define IMX7D_ECSPI3_ROOT_CLK		262
+#define IMX7D_ECSPI3_ROOT_SRC		263
+#define IMX7D_ECSPI3_ROOT_CG		264
+#define IMX7D_ECSPI3_ROOT_DIV		265
+#define IMX7D_ECSPI4_ROOT_CLK		266
+#define IMX7D_ECSPI4_ROOT_SRC		267
+#define IMX7D_ECSPI4_ROOT_CG		268
+#define IMX7D_ECSPI4_ROOT_DIV		269
+#define IMX7D_PWM1_ROOT_CLK		270
+#define IMX7D_PWM1_ROOT_SRC		271
+#define IMX7D_PWM1_ROOT_CG		272
+#define IMX7D_PWM1_ROOT_DIV		273
+#define IMX7D_PWM2_ROOT_CLK		274
+#define IMX7D_PWM2_ROOT_SRC		275
+#define IMX7D_PWM2_ROOT_CG		276
+#define IMX7D_PWM2_ROOT_DIV		277
+#define IMX7D_PWM3_ROOT_CLK		278
+#define IMX7D_PWM3_ROOT_SRC		279
+#define IMX7D_PWM3_ROOT_CG		280
+#define IMX7D_PWM3_ROOT_DIV		281
+#define IMX7D_PWM4_ROOT_CLK		282
+#define IMX7D_PWM4_ROOT_SRC		283
+#define IMX7D_PWM4_ROOT_CG		284
+#define IMX7D_PWM4_ROOT_DIV		285
+#define IMX7D_FLEXTIMER1_ROOT_CLK	286
+#define IMX7D_FLEXTIMER1_ROOT_SRC	287
+#define IMX7D_FLEXTIMER1_ROOT_CG	288
+#define IMX7D_FLEXTIMER1_ROOT_DIV	289
+#define IMX7D_FLEXTIMER2_ROOT_CLK	290
+#define IMX7D_FLEXTIMER2_ROOT_SRC	291
+#define IMX7D_FLEXTIMER2_ROOT_CG	292
+#define IMX7D_FLEXTIMER2_ROOT_DIV	293
+#define IMX7D_SIM1_ROOT_CLK		294
+#define IMX7D_SIM1_ROOT_SRC		295
+#define IMX7D_SIM1_ROOT_CG		296
+#define IMX7D_SIM1_ROOT_DIV		297
+#define IMX7D_SIM2_ROOT_CLK		298
+#define IMX7D_SIM2_ROOT_SRC		299
+#define IMX7D_SIM2_ROOT_CG		300
+#define IMX7D_SIM2_ROOT_DIV		301
+#define IMX7D_GPT1_ROOT_CLK		302
+#define IMX7D_GPT1_ROOT_SRC		303
+#define IMX7D_GPT1_ROOT_CG		304
+#define IMX7D_GPT1_ROOT_DIV		305
+#define IMX7D_GPT2_ROOT_CLK		306
+#define IMX7D_GPT2_ROOT_SRC		307
+#define IMX7D_GPT2_ROOT_CG		308
+#define IMX7D_GPT2_ROOT_DIV		309
+#define IMX7D_GPT3_ROOT_CLK		310
+#define IMX7D_GPT3_ROOT_SRC		311
+#define IMX7D_GPT3_ROOT_CG		312
+#define IMX7D_GPT3_ROOT_DIV		313
+#define IMX7D_GPT4_ROOT_CLK		314
+#define IMX7D_GPT4_ROOT_SRC		315
+#define IMX7D_GPT4_ROOT_CG		316
+#define IMX7D_GPT4_ROOT_DIV		317
+#define IMX7D_TRACE_ROOT_CLK		318
+#define IMX7D_TRACE_ROOT_SRC		319
+#define IMX7D_TRACE_ROOT_CG		320
+#define IMX7D_TRACE_ROOT_DIV		321
+#define IMX7D_WDOG1_ROOT_CLK		322
+#define IMX7D_WDOG_ROOT_SRC		323
+#define IMX7D_WDOG_ROOT_CG		324
+#define IMX7D_WDOG_ROOT_DIV		325
+#define IMX7D_CSI_MCLK_ROOT_CLK		326
+#define IMX7D_CSI_MCLK_ROOT_SRC		327
+#define IMX7D_CSI_MCLK_ROOT_CG		328
+#define IMX7D_CSI_MCLK_ROOT_DIV		329
+#define IMX7D_AUDIO_MCLK_ROOT_CLK	330
+#define IMX7D_AUDIO_MCLK_ROOT_SRC	331
+#define IMX7D_AUDIO_MCLK_ROOT_CG	332
+#define IMX7D_AUDIO_MCLK_ROOT_DIV	333
+#define IMX7D_WRCLK_ROOT_CLK		334
+#define IMX7D_WRCLK_ROOT_SRC		335
+#define IMX7D_WRCLK_ROOT_CG		336
+#define IMX7D_WRCLK_ROOT_DIV		337
+#define IMX7D_CLKO1_ROOT_SRC		338
+#define IMX7D_CLKO1_ROOT_CG		339
+#define IMX7D_CLKO1_ROOT_DIV		340
+#define IMX7D_CLKO2_ROOT_SRC		341
+#define IMX7D_CLKO2_ROOT_CG		342
+#define IMX7D_CLKO2_ROOT_DIV		343
+#define IMX7D_MAIN_AXI_ROOT_PRE_DIV	344
+#define IMX7D_DISP_AXI_ROOT_PRE_DIV	345
+#define IMX7D_ENET_AXI_ROOT_PRE_DIV	346
+#define IMX7D_NAND_USDHC_BUS_ROOT_PRE_DIV 347
+#define IMX7D_AHB_CHANNEL_ROOT_PRE_DIV	348
+#define IMX7D_USB_HSIC_ROOT_PRE_DIV	349
+#define IMX7D_PCIE_CTRL_ROOT_PRE_DIV	350
+#define IMX7D_PCIE_PHY_ROOT_PRE_DIV	351
+#define IMX7D_EPDC_PIXEL_ROOT_PRE_DIV	352
+#define IMX7D_LCDIF_PIXEL_ROOT_PRE_DIV	353
+#define IMX7D_MIPI_DSI_ROOT_PRE_DIV	354
+#define IMX7D_MIPI_CSI_ROOT_PRE_DIV	355
+#define IMX7D_MIPI_DPHY_ROOT_PRE_DIV	356
+#define IMX7D_SAI1_ROOT_PRE_DIV		357
+#define IMX7D_SAI2_ROOT_PRE_DIV		358
+#define IMX7D_SAI3_ROOT_PRE_DIV		359
+#define IMX7D_SPDIF_ROOT_PRE_DIV	360
+#define IMX7D_ENET1_REF_ROOT_PRE_DIV	361
+#define IMX7D_ENET1_TIME_ROOT_PRE_DIV	362
+#define IMX7D_ENET2_REF_ROOT_PRE_DIV	363
+#define IMX7D_ENET2_TIME_ROOT_PRE_DIV	364
+#define IMX7D_ENET_PHY_REF_ROOT_PRE_DIV 365
+#define IMX7D_EIM_ROOT_PRE_DIV		366
+#define IMX7D_NAND_ROOT_PRE_DIV		367
+#define IMX7D_QSPI_ROOT_PRE_DIV		368
+#define IMX7D_USDHC1_ROOT_PRE_DIV	369
+#define IMX7D_USDHC2_ROOT_PRE_DIV	370
+#define IMX7D_USDHC3_ROOT_PRE_DIV	371
+#define IMX7D_CAN1_ROOT_PRE_DIV		372
+#define IMX7D_CAN2_ROOT_PRE_DIV		373
+#define IMX7D_I2C1_ROOT_PRE_DIV		374
+#define IMX7D_I2C2_ROOT_PRE_DIV		375
+#define IMX7D_I2C3_ROOT_PRE_DIV		376
+#define IMX7D_I2C4_ROOT_PRE_DIV		377
+#define IMX7D_UART1_ROOT_PRE_DIV	378
+#define IMX7D_UART2_ROOT_PRE_DIV	379
+#define IMX7D_UART3_ROOT_PRE_DIV	380
+#define IMX7D_UART4_ROOT_PRE_DIV	381
+#define IMX7D_UART5_ROOT_PRE_DIV	382
+#define IMX7D_UART6_ROOT_PRE_DIV	383
+#define IMX7D_UART7_ROOT_PRE_DIV	384
+#define IMX7D_ECSPI1_ROOT_PRE_DIV	385
+#define IMX7D_ECSPI2_ROOT_PRE_DIV	386
+#define IMX7D_ECSPI3_ROOT_PRE_DIV	387
+#define IMX7D_ECSPI4_ROOT_PRE_DIV	388
+#define IMX7D_PWM1_ROOT_PRE_DIV		389
+#define IMX7D_PWM2_ROOT_PRE_DIV		390
+#define IMX7D_PWM3_ROOT_PRE_DIV		391
+#define IMX7D_PWM4_ROOT_PRE_DIV		392
+#define IMX7D_FLEXTIMER1_ROOT_PRE_DIV	393
+#define IMX7D_FLEXTIMER2_ROOT_PRE_DIV	394
+#define IMX7D_SIM1_ROOT_PRE_DIV		395
+#define IMX7D_SIM2_ROOT_PRE_DIV		396
+#define IMX7D_GPT1_ROOT_PRE_DIV		397
+#define IMX7D_GPT2_ROOT_PRE_DIV		398
+#define IMX7D_GPT3_ROOT_PRE_DIV		399
+#define IMX7D_GPT4_ROOT_PRE_DIV		400
+#define IMX7D_TRACE_ROOT_PRE_DIV	401
+#define IMX7D_WDOG_ROOT_PRE_DIV		402
+#define IMX7D_CSI_MCLK_ROOT_PRE_DIV	403
+#define IMX7D_AUDIO_MCLK_ROOT_PRE_DIV	404
+#define IMX7D_WRCLK_ROOT_PRE_DIV	405
+#define IMX7D_CLKO1_ROOT_PRE_DIV	406
+#define IMX7D_CLKO2_ROOT_PRE_DIV	407
+#define IMX7D_DRAM_PHYM_ALT_ROOT_PRE_DIV 408
+#define IMX7D_DRAM_ALT_ROOT_PRE_DIV	409
+#define IMX7D_LVDS1_IN_CLK		410
+#define IMX7D_LVDS1_OUT_SEL		411
+#define IMX7D_LVDS1_OUT_CLK		412
+#define IMX7D_CLK_DUMMY			413
+#define IMX7D_GPT_3M_CLK		414
+#define IMX7D_OCRAM_CLK			415
+#define IMX7D_OCRAM_S_CLK		416
+#define IMX7D_WDOG2_ROOT_CLK		417
+#define IMX7D_WDOG3_ROOT_CLK		418
+#define IMX7D_WDOG4_ROOT_CLK		419
+#define IMX7D_SDMA_CORE_CLK		420
+#define IMX7D_USB1_MAIN_480M_CLK	421
+#define IMX7D_USB_CTRL_CLK		422
+#define IMX7D_USB_PHY1_CLK		423
+#define IMX7D_USB_PHY2_CLK		424
+#define IMX7D_IPG_ROOT_CLK		425
+#define IMX7D_SAI1_IPG_CLK		426
+#define IMX7D_SAI2_IPG_CLK		427
+#define IMX7D_SAI3_IPG_CLK		428
+#define IMX7D_PLL_AUDIO_TEST_DIV	429
+#define IMX7D_PLL_AUDIO_POST_DIV	430
+#define IMX7D_PLL_VIDEO_TEST_DIV	431
+#define IMX7D_PLL_VIDEO_POST_DIV	432
+#define IMX7D_MU_ROOT_CLK		433
+#define IMX7D_SEMA4_HS_ROOT_CLK		434
+#define IMX7D_PLL_DRAM_TEST_DIV		435
+#define IMX7D_ADC_ROOT_CLK		436
+#define IMX7D_CLK_ARM			437
+#define IMX7D_CKIL			438
+#define IMX7D_OCOTP_CLK			439
+#define IMX7D_NAND_RAWNAND_CLK		440
+#define IMX7D_NAND_USDHC_BUS_RAWNAND_CLK 441
+#define IMX7D_SNVS_CLK			442
+#define IMX7D_CAAM_CLK			443
+#define IMX7D_KPP_ROOT_CLK		444
+#define IMX7D_PXP_IPG_CLK		445
+#define IMX7D_PXP_AXI_CLK		446
+#define IMX7D_CLK_END			447
+
+#endif /* __DT_BINDINGS_CLOCK_IMX7D_H */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/imx7ulp-clock.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/imx7ulp-clock.h
new file mode 100644
index 0000000000000000000000000000000000000000..28413e25bc67c54e69334b693bbb5e7774c12c1e
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/imx7ulp-clock.h
@@ -0,0 +1,169 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_IMX7ULP_H
+#define __DT_BINDINGS_CLOCK_IMX7ULP_H
+
+#define IMX7ULP_CLK_DUMMY		0
+#define IMX7ULP_CLK_ROSC		1
+#define IMX7ULP_CLK_SOSC		2
+#define IMX7ULP_CLK_FIRC		3
+
+/* SCG1 */
+#define IMX7ULP_CLK_SPLL_PRE_SEL	4
+#define IMX7ULP_CLK_SPLL_PRE_DIV	5
+#define IMX7ULP_CLK_SPLL		6
+#define IMX7ULP_CLK_SPLL_POST_DIV1	7
+#define IMX7ULP_CLK_SPLL_POST_DIV2	8
+#define IMX7ULP_CLK_SPLL_PFD0		9
+#define IMX7ULP_CLK_SPLL_PFD1		10
+#define IMX7ULP_CLK_SPLL_PFD2		11
+#define IMX7ULP_CLK_SPLL_PFD3		12
+#define IMX7ULP_CLK_SPLL_PFD_SEL	13
+#define IMX7ULP_CLK_SPLL_SEL		14
+#define IMX7ULP_CLK_APLL_PRE_SEL	15
+#define IMX7ULP_CLK_APLL_PRE_DIV	16
+#define IMX7ULP_CLK_APLL		17
+#define IMX7ULP_CLK_APLL_POST_DIV1	18
+#define IMX7ULP_CLK_APLL_POST_DIV2	19
+#define IMX7ULP_CLK_APLL_PFD0		20
+#define IMX7ULP_CLK_APLL_PFD1		21
+#define IMX7ULP_CLK_APLL_PFD2		22
+#define IMX7ULP_CLK_APLL_PFD3		23
+#define IMX7ULP_CLK_APLL_PFD_SEL	24
+#define IMX7ULP_CLK_APLL_SEL		25
+#define IMX7ULP_CLK_UPLL		26
+#define IMX7ULP_CLK_SYS_SEL		27
+#define IMX7ULP_CLK_CORE_DIV		28
+#define IMX7ULP_CLK_BUS_DIV		29
+#define IMX7ULP_CLK_PLAT_DIV		30
+#define IMX7ULP_CLK_DDR_SEL		31
+#define IMX7ULP_CLK_DDR_DIV		32
+#define IMX7ULP_CLK_NIC_SEL		33
+#define IMX7ULP_CLK_NIC0_DIV		34
+#define IMX7ULP_CLK_GPU_DIV		35
+#define IMX7ULP_CLK_NIC1_DIV		36
+#define IMX7ULP_CLK_NIC1_BUS_DIV	37
+#define IMX7ULP_CLK_NIC1_EXT_DIV	38
+
+/* PCG2 */
+#define IMX7ULP_CLK_DMA1		39
+#define IMX7ULP_CLK_RGPIO2P1		40
+#define IMX7ULP_CLK_FLEXBUS		41
+#define IMX7ULP_CLK_SEMA42_1		42
+#define IMX7ULP_CLK_DMA_MUX1		43
+#define IMX7ULP_CLK_SNVS		44
+#define IMX7ULP_CLK_CAAM		45
+#define IMX7ULP_CLK_LPTPM4		46
+#define IMX7ULP_CLK_LPTPM5		47
+#define IMX7ULP_CLK_LPIT1		48
+#define IMX7ULP_CLK_LPSPI2		49
+#define IMX7ULP_CLK_LPSPI3		50
+#define IMX7ULP_CLK_LPI2C4		51
+#define IMX7ULP_CLK_LPI2C5		52
+#define IMX7ULP_CLK_LPUART4		53
+#define IMX7ULP_CLK_LPUART5		54
+#define IMX7ULP_CLK_FLEXIO1		55
+#define IMX7ULP_CLK_USB0		56
+#define IMX7ULP_CLK_USB1		57
+#define IMX7ULP_CLK_USB_PHY		58
+#define IMX7ULP_CLK_USB_PL301		59
+#define IMX7ULP_CLK_USDHC0		60
+#define IMX7ULP_CLK_USDHC1		61
+#define IMX7ULP_CLK_WDG1		62
+#define IMX7ULP_CLK_WDG2		63
+
+/* PCG3 */
+#define IMX7ULP_CLK_LPTPM6		64
+#define IMX7ULP_CLK_LPTPM7		65
+#define IMX7ULP_CLK_LPI2C6		66
+#define IMX7ULP_CLK_LPI2C7		67
+#define IMX7ULP_CLK_LPUART6		68
+#define IMX7ULP_CLK_LPUART7		69
+#define IMX7ULP_CLK_VIU			70
+#define IMX7ULP_CLK_DSI			71
+#define IMX7ULP_CLK_LCDIF		72
+#define IMX7ULP_CLK_MMDC		73
+#define IMX7ULP_CLK_PCTLC		74
+#define IMX7ULP_CLK_PCTLD		75
+#define IMX7ULP_CLK_PCTLE		76
+#define IMX7ULP_CLK_PCTLF		77
+#define IMX7ULP_CLK_GPU3D		78
+#define IMX7ULP_CLK_GPU2D		79
+
+#define IMX7ULP_CLK_MIPI_PLL		80
+#define IMX7ULP_CLK_SIRC		81
+
+#define IMX7ULP_CLK_SCG1_CLKOUT		82
+#define IMX7ULP_CLK_HSRUN_SYS_SEL	83
+#define IMX7ULP_CLK_HSRUN_CORE		84
+#define IMX7ULP_CLK_ARM			85
+
+#define IMX7ULP_CLK_SOSC_BUS_CLK        86
+#define IMX7ULP_CLK_FIRC_BUS_CLK        87
+#define IMX7ULP_CLK_SPLL_BUS_CLK        88
+
+#define IMX7ULP_CLK_END			89
+
+/*cm4 clocks*/
+#define IMX7ULP_CM4_CLK_DUMMY		0
+#define IMX7ULP_CM4_CLK_ROSC		1
+#define IMX7ULP_CM4_CLK_SOSC		2
+#define IMX7ULP_CM4_CLK_FIRC		3
+#define IMX7ULP_CM4_CLK_SIRC		4
+
+/* SCG0 */
+#define IMX7ULP_CM4_CLK_SPLL_VCO_PRE_SEL	5
+#define IMX7ULP_CM4_CLK_SPLL_VCO_PRE_DIV	6
+#define IMX7ULP_CM4_CLK_SPLL		7
+#define IMX7ULP_CM4_CLK_SPLL_VCO	8
+#define IMX7ULP_CM4_CLK_SPLL_VCO_POST_DIV1	9
+#define IMX7ULP_CM4_CLK_SPLL_VCO_POST_DIV2	10
+#define IMX7ULP_CM4_CLK_SPLL_PFD0	11
+#define IMX7ULP_CM4_CLK_SPLL_PFD1	12
+#define IMX7ULP_CM4_CLK_SPLL_PFD2	13
+#define IMX7ULP_CM4_CLK_SPLL_PFD3	14
+#define IMX7ULP_CM4_CLK_SPLL_PFD_SEL	15
+#define IMX7ULP_CM4_CLK_SPLL_PFD	16
+#define IMX7ULP_CM4_CLK_SPLL_SEL	17
+#define IMX7ULP_CM4_CLK_APLL_VCO_PRE_SEL	18
+#define IMX7ULP_CM4_CLK_APLL_VCO_PRE_DIV	19
+#define IMX7ULP_CM4_CLK_APLL		20
+#define IMX7ULP_CM4_CLK_APLL_VCO	21
+#define IMX7ULP_CM4_CLK_APLL_VCO_POST_DIV1	22
+#define IMX7ULP_CM4_CLK_APLL_VCO_POST_DIV2	23
+#define IMX7ULP_CM4_CLK_APLL_PFD0	24
+#define IMX7ULP_CM4_CLK_APLL_PFD1	25
+#define IMX7ULP_CM4_CLK_APLL_PFD2	26
+#define IMX7ULP_CM4_CLK_APLL_PFD3	27
+#define IMX7ULP_CM4_CLK_APLL_PFD_SEL	28
+#define IMX7ULP_CM4_CLK_APLL_PFD	29
+#define IMX7ULP_CM4_CLK_APLL_SEL	30
+#define IMX7ULP_CM4_CLK_APLL_PFD0_PRE_DIV	31
+#define IMX7ULP_CM4_CLK_SYS_SEL		32
+#define IMX7ULP_CM4_CLK_CORE_DIV	33
+#define IMX7ULP_CM4_CLK_BUS_DIV		34
+#define IMX7ULP_CM4_CLK_PLAT_DIV	35
+#define IMX7ULP_CM4_CLK_SLOW_DIV	36
+
+#define IMX7ULP_CM4_CLK_SAI0_SEL	37
+#define IMX7ULP_CM4_CLK_SAI0_DIV	38
+#define IMX7ULP_CM4_CLK_SAI0_ROOT	39
+#define IMX7ULP_CM4_CLK_SAI0_IPG	40
+#define IMX7ULP_CM4_CLK_SAI1_SEL	41
+#define IMX7ULP_CM4_CLK_SAI1_DIV	42
+#define IMX7ULP_CM4_CLK_SAI1_ROOT	43
+#define IMX7ULP_CM4_CLK_SAI1_IPG	44
+
+#define IMX7ULP_CLK_SCG0_CLKOUT		45
+
+#define IMX7ULP_CM4_CLK_END		46
+
+#endif /* __DT_BINDINGS_CLOCK_IMX7ULP_H */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/imx8mm-clock.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/imx8mm-clock.h
new file mode 100644
index 0000000000000000000000000000000000000000..45fcb1e9ba22efca3b38ffdd2f51a79b49c55883
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/imx8mm-clock.h
@@ -0,0 +1,246 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright 2017-2018 NXP
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_IMX8MM_H
+#define __DT_BINDINGS_CLOCK_IMX8MM_H
+
+#define IMX8MM_CLK_DUMMY			0
+#define IMX8MM_CLK_32K				1
+#define IMX8MM_CLK_24M				2
+#define IMX8MM_OSC_HDMI_CLK			3
+#define IMX8MM_CLK_EXT1				4
+#define IMX8MM_CLK_EXT2				5
+#define IMX8MM_CLK_EXT3				6
+#define IMX8MM_CLK_EXT4				7
+#define IMX8MM_AUDIO_PLL1_REF_SEL		8
+#define IMX8MM_AUDIO_PLL2_REF_SEL		9
+#define IMX8MM_VIDEO_PLL1_REF_SEL		10
+#define IMX8MM_DRAM_PLL_REF_SEL			11
+#define IMX8MM_GPU_PLL_REF_SEL			12
+#define IMX8MM_VPU_PLL_REF_SEL			13
+#define IMX8MM_ARM_PLL_REF_SEL			14
+#define IMX8MM_SYS_PLL1_REF_SEL			15
+#define IMX8MM_SYS_PLL2_REF_SEL			16
+#define IMX8MM_SYS_PLL3_REF_SEL			17
+#define IMX8MM_AUDIO_PLL1			18
+#define IMX8MM_AUDIO_PLL2			19
+#define IMX8MM_VIDEO_PLL1			20
+#define IMX8MM_DRAM_PLL				21
+#define IMX8MM_GPU_PLL				22
+#define IMX8MM_VPU_PLL				23
+#define IMX8MM_ARM_PLL				24
+#define IMX8MM_SYS_PLL1				25
+#define IMX8MM_SYS_PLL2				26
+#define IMX8MM_SYS_PLL3				27
+#define IMX8MM_AUDIO_PLL1_BYPASS		28
+#define IMX8MM_AUDIO_PLL2_BYPASS		29
+#define IMX8MM_VIDEO_PLL1_BYPASS		30
+#define IMX8MM_DRAM_PLL_BYPASS			31
+#define IMX8MM_GPU_PLL_BYPASS			32
+#define IMX8MM_VPU_PLL_BYPASS			33
+#define IMX8MM_ARM_PLL_BYPASS			34
+#define IMX8MM_SYS_PLL1_BYPASS			35
+#define IMX8MM_SYS_PLL2_BYPASS			36
+#define IMX8MM_SYS_PLL3_BYPASS			37
+#define IMX8MM_AUDIO_PLL1_OUT			38
+#define IMX8MM_AUDIO_PLL2_OUT			39
+#define IMX8MM_VIDEO_PLL1_OUT			40
+#define IMX8MM_DRAM_PLL_OUT			41
+#define IMX8MM_GPU_PLL_OUT			42
+#define IMX8MM_VPU_PLL_OUT			43
+#define IMX8MM_ARM_PLL_OUT			44
+#define IMX8MM_SYS_PLL1_OUT			45
+#define IMX8MM_SYS_PLL2_OUT			46
+#define IMX8MM_SYS_PLL3_OUT			47
+#define IMX8MM_SYS_PLL1_40M			48
+#define IMX8MM_SYS_PLL1_80M			49
+#define IMX8MM_SYS_PLL1_100M			50
+#define IMX8MM_SYS_PLL1_133M			51
+#define IMX8MM_SYS_PLL1_160M			52
+#define IMX8MM_SYS_PLL1_200M			53
+#define IMX8MM_SYS_PLL1_266M			54
+#define IMX8MM_SYS_PLL1_400M			55
+#define IMX8MM_SYS_PLL1_800M			56
+#define IMX8MM_SYS_PLL2_50M			57
+#define IMX8MM_SYS_PLL2_100M			58
+#define IMX8MM_SYS_PLL2_125M			59
+#define IMX8MM_SYS_PLL2_166M			60
+#define IMX8MM_SYS_PLL2_200M			61
+#define IMX8MM_SYS_PLL2_250M			62
+#define IMX8MM_SYS_PLL2_333M			63
+#define IMX8MM_SYS_PLL2_500M			64
+#define IMX8MM_SYS_PLL2_1000M			65
+
+/* core */
+#define IMX8MM_CLK_A53_SRC			66
+#define IMX8MM_CLK_M4_SRC			67
+#define IMX8MM_CLK_VPU_SRC			68
+#define IMX8MM_CLK_GPU3D_SRC			69
+#define IMX8MM_CLK_GPU2D_SRC			70
+#define IMX8MM_CLK_A53_CG			71
+#define IMX8MM_CLK_M4_CG			72
+#define IMX8MM_CLK_VPU_CG			73
+#define IMX8MM_CLK_GPU3D_CG			74
+#define IMX8MM_CLK_GPU2D_CG			75
+#define IMX8MM_CLK_A53_DIV			76
+#define IMX8MM_CLK_M4_DIV			77
+#define IMX8MM_CLK_VPU_DIV			78
+#define IMX8MM_CLK_GPU3D_DIV			79
+#define IMX8MM_CLK_GPU2D_DIV			80
+
+/* bus */
+#define IMX8MM_CLK_MAIN_AXI			81
+#define IMX8MM_CLK_ENET_AXI			82
+#define IMX8MM_CLK_NAND_USDHC_BUS		83
+#define IMX8MM_CLK_VPU_BUS			84
+#define IMX8MM_CLK_DISP_AXI			85
+#define IMX8MM_CLK_DISP_APB			86
+#define IMX8MM_CLK_DISP_RTRM			87
+#define IMX8MM_CLK_USB_BUS			88
+#define IMX8MM_CLK_GPU_AXI			89
+#define IMX8MM_CLK_GPU_AHB			90
+#define IMX8MM_CLK_NOC				91
+#define IMX8MM_CLK_NOC_APB			92
+
+#define IMX8MM_CLK_AHB				93
+#define IMX8MM_CLK_AUDIO_AHB			94
+#define IMX8MM_CLK_IPG_ROOT			95
+#define IMX8MM_CLK_IPG_AUDIO_ROOT		96
+
+#define IMX8MM_CLK_DRAM_ALT			97
+#define IMX8MM_CLK_DRAM_APB			98
+#define IMX8MM_CLK_VPU_G1			99
+#define IMX8MM_CLK_VPU_G2			100
+#define IMX8MM_CLK_DISP_DTRC			101
+#define IMX8MM_CLK_DISP_DC8000			102
+#define IMX8MM_CLK_PCIE1_CTRL			103
+#define IMX8MM_CLK_PCIE1_PHY			104
+#define IMX8MM_CLK_PCIE1_AUX			105
+#define IMX8MM_CLK_DC_PIXEL			106
+#define IMX8MM_CLK_LCDIF_PIXEL			107
+#define IMX8MM_CLK_SAI1				108
+#define IMX8MM_CLK_SAI2				109
+#define IMX8MM_CLK_SAI3				110
+#define IMX8MM_CLK_SAI4				111
+#define IMX8MM_CLK_SAI5				112
+#define IMX8MM_CLK_SAI6				113
+#define IMX8MM_CLK_SPDIF1			114
+#define IMX8MM_CLK_SPDIF2			115
+#define IMX8MM_CLK_ENET_REF			116
+#define IMX8MM_CLK_ENET_TIMER			117
+#define IMX8MM_CLK_ENET_PHY_REF			118
+#define IMX8MM_CLK_NAND				119
+#define IMX8MM_CLK_QSPI				120
+#define IMX8MM_CLK_USDHC1			121
+#define IMX8MM_CLK_USDHC2			122
+#define IMX8MM_CLK_I2C1				123
+#define IMX8MM_CLK_I2C2				124
+#define IMX8MM_CLK_I2C3				125
+#define IMX8MM_CLK_I2C4				126
+#define IMX8MM_CLK_UART1			127
+#define IMX8MM_CLK_UART2			128
+#define IMX8MM_CLK_UART3			129
+#define IMX8MM_CLK_UART4			130
+#define IMX8MM_CLK_USB_CORE_REF			131
+#define IMX8MM_CLK_USB_PHY_REF			132
+#define IMX8MM_CLK_ECSPI1			133
+#define IMX8MM_CLK_ECSPI2			134
+#define IMX8MM_CLK_PWM1				135
+#define IMX8MM_CLK_PWM2				136
+#define IMX8MM_CLK_PWM3				137
+#define IMX8MM_CLK_PWM4				138
+#define IMX8MM_CLK_GPT1				139
+#define IMX8MM_CLK_WDOG				140
+#define IMX8MM_CLK_WRCLK			141
+#define IMX8MM_CLK_DSI_CORE			142
+#define IMX8MM_CLK_DSI_PHY_REF			143
+#define IMX8MM_CLK_DSI_DBI			144
+#define IMX8MM_CLK_USDHC3			145
+#define IMX8MM_CLK_CSI1_CORE			146
+#define IMX8MM_CLK_CSI1_PHY_REF			147
+#define IMX8MM_CLK_CSI1_ESC			148
+#define IMX8MM_CLK_CSI2_CORE			149
+#define IMX8MM_CLK_CSI2_PHY_REF			150
+#define IMX8MM_CLK_CSI2_ESC			151
+#define IMX8MM_CLK_PCIE2_CTRL			152
+#define IMX8MM_CLK_PCIE2_PHY			153
+#define IMX8MM_CLK_PCIE2_AUX			154
+#define IMX8MM_CLK_ECSPI3			155
+#define IMX8MM_CLK_PDM				156
+#define IMX8MM_CLK_VPU_H1			157
+#define IMX8MM_CLK_CLKO1			158
+
+#define IMX8MM_CLK_ECSPI1_ROOT			159
+#define IMX8MM_CLK_ECSPI2_ROOT			160
+#define IMX8MM_CLK_ECSPI3_ROOT			161
+#define IMX8MM_CLK_ENET1_ROOT			162
+#define IMX8MM_CLK_GPT1_ROOT			163
+#define IMX8MM_CLK_I2C1_ROOT			164
+#define IMX8MM_CLK_I2C2_ROOT			165
+#define IMX8MM_CLK_I2C3_ROOT			166
+#define IMX8MM_CLK_I2C4_ROOT			167
+#define IMX8MM_CLK_OCOTP_ROOT			168
+#define IMX8MM_CLK_PCIE1_ROOT			169
+#define IMX8MM_CLK_PWM1_ROOT			170
+#define IMX8MM_CLK_PWM2_ROOT			171
+#define IMX8MM_CLK_PWM3_ROOT			172
+#define IMX8MM_CLK_PWM4_ROOT			173
+#define IMX8MM_CLK_QSPI_ROOT			174
+#define IMX8MM_CLK_NAND_ROOT			175
+#define IMX8MM_CLK_SAI1_ROOT			176
+#define IMX8MM_CLK_SAI1_IPG			177
+#define IMX8MM_CLK_SAI2_ROOT			178
+#define IMX8MM_CLK_SAI2_IPG			179
+#define IMX8MM_CLK_SAI3_ROOT			180
+#define IMX8MM_CLK_SAI3_IPG			181
+#define IMX8MM_CLK_SAI4_ROOT			182
+#define IMX8MM_CLK_SAI4_IPG			183
+#define IMX8MM_CLK_SAI5_ROOT			184
+#define IMX8MM_CLK_SAI5_IPG			185
+#define IMX8MM_CLK_SAI6_ROOT			186
+#define IMX8MM_CLK_SAI6_IPG			187
+#define IMX8MM_CLK_UART1_ROOT			188
+#define IMX8MM_CLK_UART2_ROOT			189
+#define IMX8MM_CLK_UART3_ROOT			190
+#define IMX8MM_CLK_UART4_ROOT			191
+#define IMX8MM_CLK_USB1_CTRL_ROOT		192
+#define IMX8MM_CLK_GPU3D_ROOT			193
+#define IMX8MM_CLK_USDHC1_ROOT			194
+#define IMX8MM_CLK_USDHC2_ROOT			195
+#define IMX8MM_CLK_WDOG1_ROOT			196
+#define IMX8MM_CLK_WDOG2_ROOT			197
+#define IMX8MM_CLK_WDOG3_ROOT			198
+#define IMX8MM_CLK_VPU_G1_ROOT			199
+#define IMX8MM_CLK_GPU_BUS_ROOT			200
+#define IMX8MM_CLK_VPU_H1_ROOT			201
+#define IMX8MM_CLK_VPU_G2_ROOT			202
+#define IMX8MM_CLK_PDM_ROOT			203
+#define IMX8MM_CLK_DISP_ROOT			204
+#define IMX8MM_CLK_DISP_AXI_ROOT		205
+#define IMX8MM_CLK_DISP_APB_ROOT		206
+#define IMX8MM_CLK_DISP_RTRM_ROOT		207
+#define IMX8MM_CLK_USDHC3_ROOT			208
+#define IMX8MM_CLK_TMU_ROOT			209
+#define IMX8MM_CLK_VPU_DEC_ROOT			210
+#define IMX8MM_CLK_SDMA1_ROOT			211
+#define IMX8MM_CLK_SDMA2_ROOT			212
+#define IMX8MM_CLK_SDMA3_ROOT			213
+#define IMX8MM_CLK_GPT_3M			214
+#define IMX8MM_CLK_ARM				215
+#define IMX8MM_CLK_PDM_IPG			216
+#define IMX8MM_CLK_GPU2D_ROOT			217
+#define IMX8MM_CLK_MU_ROOT			218
+#define IMX8MM_CLK_CSI1_ROOT			219
+
+#define IMX8MM_CLK_DRAM_CORE			220
+#define IMX8MM_CLK_DRAM_ALT_ROOT		221
+
+#define IMX8MM_CLK_NAND_USDHC_BUS_RAWNAND_CLK	222
+
+#define IMX8MM_CLK_SIM_HSIO			223
+
+#define IMX8MM_CLK_END				224
+
+#endif
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/imx8mq-clock.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/imx8mq-clock.h
new file mode 100644
index 0000000000000000000000000000000000000000..e05eea7ce1e72c0fa7dfbb5bcecfac4ae92a3646
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/imx8mq-clock.h
@@ -0,0 +1,410 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_IMX8MQ_H
+#define __DT_BINDINGS_CLOCK_IMX8MQ_H
+
+#define IMX8MQ_CLK_DUMMY		0
+#define IMX8MQ_CLK_32K			1
+#define IMX8MQ_CLK_25M			2
+#define IMX8MQ_CLK_27M			3
+#define IMX8MQ_CLK_EXT1			4
+#define IMX8MQ_CLK_EXT2			5
+#define IMX8MQ_CLK_EXT3			6
+#define IMX8MQ_CLK_EXT4			7
+
+/* ANAMIX PLL clocks */
+/* FRAC PLLs */
+/* ARM PLL */
+#define IMX8MQ_ARM_PLL_REF_SEL		8
+#define IMX8MQ_ARM_PLL_REF_DIV		9
+#define IMX8MQ_ARM_PLL			10
+#define IMX8MQ_ARM_PLL_BYPASS		11
+#define IMX8MQ_ARM_PLL_OUT		12
+
+/* GPU PLL */
+#define IMX8MQ_GPU_PLL_REF_SEL		13
+#define IMX8MQ_GPU_PLL_REF_DIV		14
+#define IMX8MQ_GPU_PLL			15
+#define IMX8MQ_GPU_PLL_BYPASS		16
+#define IMX8MQ_GPU_PLL_OUT		17
+
+/* VPU PLL */
+#define IMX8MQ_VPU_PLL_REF_SEL		18
+#define IMX8MQ_VPU_PLL_REF_DIV		19
+#define IMX8MQ_VPU_PLL			20
+#define IMX8MQ_VPU_PLL_BYPASS		21
+#define IMX8MQ_VPU_PLL_OUT		22
+
+/* AUDIO PLL1 */
+#define IMX8MQ_AUDIO_PLL1_REF_SEL	23
+#define IMX8MQ_AUDIO_PLL1_REF_DIV	24
+#define IMX8MQ_AUDIO_PLL1		25
+#define IMX8MQ_AUDIO_PLL1_BYPASS	26
+#define IMX8MQ_AUDIO_PLL1_OUT		27
+
+/* AUDIO PLL2 */
+#define IMX8MQ_AUDIO_PLL2_REF_SEL	28
+#define IMX8MQ_AUDIO_PLL2_REF_DIV	29
+#define IMX8MQ_AUDIO_PLL2		30
+#define IMX8MQ_AUDIO_PLL2_BYPASS	31
+#define IMX8MQ_AUDIO_PLL2_OUT		32
+
+/* VIDEO PLL1 */
+#define IMX8MQ_VIDEO_PLL1_REF_SEL	33
+#define IMX8MQ_VIDEO_PLL1_REF_DIV	34
+#define IMX8MQ_VIDEO_PLL1		35
+#define IMX8MQ_VIDEO_PLL1_BYPASS	36
+#define IMX8MQ_VIDEO_PLL1_OUT		37
+
+/* SYS1 PLL */
+#define IMX8MQ_SYS1_PLL1_REF_SEL	38
+#define IMX8MQ_SYS1_PLL1_REF_DIV	39
+#define IMX8MQ_SYS1_PLL1		40
+#define IMX8MQ_SYS1_PLL1_OUT		41
+#define IMX8MQ_SYS1_PLL1_OUT_DIV	42
+#define IMX8MQ_SYS1_PLL2		43
+#define IMX8MQ_SYS1_PLL2_DIV		44
+#define IMX8MQ_SYS1_PLL2_OUT		45
+
+/* SYS2 PLL */
+#define IMX8MQ_SYS2_PLL1_REF_SEL	46
+#define IMX8MQ_SYS2_PLL1_REF_DIV	47
+#define IMX8MQ_SYS2_PLL1		48
+#define IMX8MQ_SYS2_PLL1_OUT		49
+#define IMX8MQ_SYS2_PLL1_OUT_DIV	50
+#define IMX8MQ_SYS2_PLL2		51
+#define IMX8MQ_SYS2_PLL2_DIV		52
+#define IMX8MQ_SYS2_PLL2_OUT		53
+
+/* SYS3 PLL */
+#define IMX8MQ_SYS3_PLL1_REF_SEL	54
+#define IMX8MQ_SYS3_PLL1_REF_DIV	55
+#define IMX8MQ_SYS3_PLL1		56
+#define IMX8MQ_SYS3_PLL1_OUT		57
+#define IMX8MQ_SYS3_PLL1_OUT_DIV	58
+#define IMX8MQ_SYS3_PLL2		59
+#define IMX8MQ_SYS3_PLL2_DIV		60
+#define IMX8MQ_SYS3_PLL2_OUT		61
+
+/* DRAM PLL */
+#define IMX8MQ_DRAM_PLL1_REF_SEL	62
+#define IMX8MQ_DRAM_PLL1_REF_DIV	63
+#define IMX8MQ_DRAM_PLL1		64
+#define IMX8MQ_DRAM_PLL1_OUT		65
+#define IMX8MQ_DRAM_PLL1_OUT_DIV	66
+#define IMX8MQ_DRAM_PLL2		67
+#define IMX8MQ_DRAM_PLL2_DIV		68
+#define IMX8MQ_DRAM_PLL2_OUT		69
+
+/* SYS PLL DIV */
+#define IMX8MQ_SYS1_PLL_40M		70
+#define IMX8MQ_SYS1_PLL_80M		71
+#define IMX8MQ_SYS1_PLL_100M		72
+#define IMX8MQ_SYS1_PLL_133M		73
+#define IMX8MQ_SYS1_PLL_160M		74
+#define IMX8MQ_SYS1_PLL_200M		75
+#define IMX8MQ_SYS1_PLL_266M		76
+#define IMX8MQ_SYS1_PLL_400M		77
+#define IMX8MQ_SYS1_PLL_800M		78
+
+#define IMX8MQ_SYS2_PLL_50M		79
+#define IMX8MQ_SYS2_PLL_100M		80
+#define IMX8MQ_SYS2_PLL_125M		81
+#define IMX8MQ_SYS2_PLL_166M		82
+#define IMX8MQ_SYS2_PLL_200M		83
+#define IMX8MQ_SYS2_PLL_250M		84
+#define IMX8MQ_SYS2_PLL_333M		85
+#define IMX8MQ_SYS2_PLL_500M		86
+#define IMX8MQ_SYS2_PLL_1000M		87
+
+/* CCM ROOT clocks */
+/* A53 */
+#define IMX8MQ_CLK_A53_SRC		88
+#define IMX8MQ_CLK_A53_CG		89
+#define IMX8MQ_CLK_A53_DIV		90
+/* M4 */
+#define IMX8MQ_CLK_M4_SRC		91
+#define IMX8MQ_CLK_M4_CG		92
+#define IMX8MQ_CLK_M4_DIV		93
+/* VPU */
+#define IMX8MQ_CLK_VPU_SRC		94
+#define IMX8MQ_CLK_VPU_CG		95
+#define IMX8MQ_CLK_VPU_DIV		96
+/* GPU CORE */
+#define IMX8MQ_CLK_GPU_CORE_SRC		97
+#define IMX8MQ_CLK_GPU_CORE_CG		98
+#define IMX8MQ_CLK_GPU_CORE_DIV		99
+/* GPU SHADER */
+#define IMX8MQ_CLK_GPU_SHADER_SRC	100
+#define IMX8MQ_CLK_GPU_SHADER_CG	101
+#define IMX8MQ_CLK_GPU_SHADER_DIV	102
+
+/* BUS TYPE */
+/* MAIN AXI */
+#define IMX8MQ_CLK_MAIN_AXI		103
+/* ENET AXI */
+#define IMX8MQ_CLK_ENET_AXI		104
+/* NAND_USDHC_BUS */
+#define IMX8MQ_CLK_NAND_USDHC_BUS	105
+/* VPU BUS */
+#define IMX8MQ_CLK_VPU_BUS		106
+/* DISP_AXI */
+#define IMX8MQ_CLK_DISP_AXI		107
+/* DISP APB */
+#define IMX8MQ_CLK_DISP_APB		108
+/* DISP RTRM */
+#define IMX8MQ_CLK_DISP_RTRM		109
+/* USB_BUS */
+#define IMX8MQ_CLK_USB_BUS		110
+/* GPU_AXI */
+#define IMX8MQ_CLK_GPU_AXI		111
+/* GPU_AHB */
+#define IMX8MQ_CLK_GPU_AHB		112
+/* NOC */
+#define IMX8MQ_CLK_NOC			113
+/* NOC_APB */
+#define IMX8MQ_CLK_NOC_APB		114
+
+/* AHB */
+#define IMX8MQ_CLK_AHB			115
+/* AUDIO AHB */
+#define IMX8MQ_CLK_AUDIO_AHB		116
+
+/* DRAM_ALT */
+#define IMX8MQ_CLK_DRAM_ALT		117
+/* DRAM APB */
+#define IMX8MQ_CLK_DRAM_APB		118
+/* VPU_G1 */
+#define IMX8MQ_CLK_VPU_G1		119
+/* VPU_G2 */
+#define IMX8MQ_CLK_VPU_G2		120
+/* DISP_DTRC */
+#define IMX8MQ_CLK_DISP_DTRC		121
+/* DISP_DC8000 */
+#define IMX8MQ_CLK_DISP_DC8000		122
+/* PCIE_CTRL */
+#define IMX8MQ_CLK_PCIE1_CTRL		123
+/* PCIE_PHY */
+#define IMX8MQ_CLK_PCIE1_PHY		124
+/* PCIE_AUX */
+#define IMX8MQ_CLK_PCIE1_AUX		125
+/* DC_PIXEL */
+#define IMX8MQ_CLK_DC_PIXEL		126
+/* LCDIF_PIXEL */
+#define IMX8MQ_CLK_LCDIF_PIXEL		127
+/* SAI1~6 */
+#define IMX8MQ_CLK_SAI1			128
+
+#define IMX8MQ_CLK_SAI2			129
+
+#define IMX8MQ_CLK_SAI3			130
+
+#define IMX8MQ_CLK_SAI4			131
+
+#define IMX8MQ_CLK_SAI5			132
+
+#define IMX8MQ_CLK_SAI6			133
+/* SPDIF1 */
+#define IMX8MQ_CLK_SPDIF1		134
+/* SPDIF2 */
+#define IMX8MQ_CLK_SPDIF2		135
+/* ENET_REF */
+#define IMX8MQ_CLK_ENET_REF		136
+/* ENET_TIMER */
+#define IMX8MQ_CLK_ENET_TIMER		137
+/* ENET_PHY */
+#define IMX8MQ_CLK_ENET_PHY_REF		138
+/* NAND */
+#define IMX8MQ_CLK_NAND			139
+/* QSPI */
+#define IMX8MQ_CLK_QSPI			140
+/* USDHC1 */
+#define IMX8MQ_CLK_USDHC1		141
+/* USDHC2 */
+#define IMX8MQ_CLK_USDHC2		142
+/* I2C1 */
+#define IMX8MQ_CLK_I2C1			143
+/* I2C2 */
+#define IMX8MQ_CLK_I2C2			144
+/* I2C3 */
+#define IMX8MQ_CLK_I2C3			145
+/* I2C4 */
+#define IMX8MQ_CLK_I2C4			146
+/* UART1 */
+#define IMX8MQ_CLK_UART1		148
+/* UART2 */
+#define IMX8MQ_CLK_UART2		149
+/* UART3 */
+#define IMX8MQ_CLK_UART3		150
+/* UART4 */
+#define IMX8MQ_CLK_UART4		151
+/* USB_CORE_REF */
+#define IMX8MQ_CLK_USB_CORE_REF		152
+/* USB_PHY_REF */
+#define IMX8MQ_CLK_USB_PHY_REF		153
+/* ECSPI1 */
+#define IMX8MQ_CLK_ECSPI1		154
+/* ECSPI2 */
+#define IMX8MQ_CLK_ECSPI2		155
+/* PWM1 */
+#define IMX8MQ_CLK_PWM1			156
+/* PWM2 */
+#define IMX8MQ_CLK_PWM2			157
+/* PWM3 */
+#define IMX8MQ_CLK_PWM3			158
+/* PWM4 */
+#define IMX8MQ_CLK_PWM4			159
+/* GPT1 */
+#define IMX8MQ_CLK_GPT1			160
+/* WDOG */
+#define IMX8MQ_CLK_WDOG			161
+/* WRCLK */
+#define IMX8MQ_CLK_WRCLK		162
+/* DSI_CORE */
+#define IMX8MQ_CLK_DSI_CORE		163
+/* DSI_PHY */
+#define IMX8MQ_CLK_DSI_PHY_REF		164
+/* DSI_DBI */
+#define IMX8MQ_CLK_DSI_DBI		165
+/*DSI_ESC */
+#define IMX8MQ_CLK_DSI_ESC		166
+/* CSI1_CORE */
+#define IMX8MQ_CLK_CSI1_CORE		167
+/* CSI1_PHY */
+#define IMX8MQ_CLK_CSI1_PHY_REF		168
+/* CSI_ESC */
+#define IMX8MQ_CLK_CSI1_ESC		169
+/* CSI2_CORE */
+#define IMX8MQ_CLK_CSI2_CORE		170
+/* CSI2_PHY */
+#define IMX8MQ_CLK_CSI2_PHY_REF		171
+/* CSI2_ESC */
+#define IMX8MQ_CLK_CSI2_ESC		172
+/* PCIE2_CTRL */
+#define IMX8MQ_CLK_PCIE2_CTRL		173
+/* PCIE2_PHY */
+#define IMX8MQ_CLK_PCIE2_PHY		174
+/* PCIE2_AUX */
+#define IMX8MQ_CLK_PCIE2_AUX		175
+/* ECSPI3 */
+#define IMX8MQ_CLK_ECSPI3			176
+
+/* CCGR clocks */
+#define IMX8MQ_CLK_A53_ROOT			191
+#define IMX8MQ_CLK_DRAM_ROOT			192
+#define IMX8MQ_CLK_ECSPI1_ROOT			193
+#define IMX8MQ_CLK_ECSPI2_ROOT			194
+#define IMX8MQ_CLK_ECSPI3_ROOT			195
+#define IMX8MQ_CLK_ENET1_ROOT			196
+#define IMX8MQ_CLK_GPT1_ROOT			197
+#define IMX8MQ_CLK_I2C1_ROOT			198
+#define IMX8MQ_CLK_I2C2_ROOT			199
+#define IMX8MQ_CLK_I2C3_ROOT			200
+#define IMX8MQ_CLK_I2C4_ROOT			201
+#define IMX8MQ_CLK_M4_ROOT			202
+#define IMX8MQ_CLK_PCIE1_ROOT			203
+#define IMX8MQ_CLK_PCIE2_ROOT			204
+#define IMX8MQ_CLK_PWM1_ROOT			205
+#define IMX8MQ_CLK_PWM2_ROOT			206
+#define IMX8MQ_CLK_PWM3_ROOT			207
+#define IMX8MQ_CLK_PWM4_ROOT			208
+#define IMX8MQ_CLK_QSPI_ROOT			209
+#define IMX8MQ_CLK_SAI1_ROOT			210
+#define IMX8MQ_CLK_SAI2_ROOT			211
+#define IMX8MQ_CLK_SAI3_ROOT			212
+#define IMX8MQ_CLK_SAI4_ROOT			213
+#define IMX8MQ_CLK_SAI5_ROOT			214
+#define IMX8MQ_CLK_SAI6_ROOT			215
+#define IMX8MQ_CLK_UART1_ROOT			216
+#define IMX8MQ_CLK_UART2_ROOT			217
+#define IMX8MQ_CLK_UART3_ROOT			218
+#define IMX8MQ_CLK_UART4_ROOT			219
+#define IMX8MQ_CLK_USB1_CTRL_ROOT		220
+#define IMX8MQ_CLK_USB2_CTRL_ROOT		221
+#define IMX8MQ_CLK_USB1_PHY_ROOT		222
+#define IMX8MQ_CLK_USB2_PHY_ROOT		223
+#define IMX8MQ_CLK_USDHC1_ROOT			224
+#define IMX8MQ_CLK_USDHC2_ROOT			225
+#define IMX8MQ_CLK_WDOG1_ROOT			226
+#define IMX8MQ_CLK_WDOG2_ROOT			227
+#define IMX8MQ_CLK_WDOG3_ROOT			228
+#define IMX8MQ_CLK_GPU_ROOT			229
+#define IMX8MQ_CLK_HEVC_ROOT			230
+#define IMX8MQ_CLK_AVC_ROOT			231
+#define IMX8MQ_CLK_VP9_ROOT			232
+#define IMX8MQ_CLK_HEVC_INTER_ROOT		233
+#define IMX8MQ_CLK_DISP_ROOT			234
+#define IMX8MQ_CLK_HDMI_ROOT			235
+#define IMX8MQ_CLK_HDMI_PHY_ROOT		236
+#define IMX8MQ_CLK_VPU_DEC_ROOT			237
+#define IMX8MQ_CLK_CSI1_ROOT			238
+#define IMX8MQ_CLK_CSI2_ROOT			239
+#define IMX8MQ_CLK_RAWNAND_ROOT			240
+#define IMX8MQ_CLK_SDMA1_ROOT			241
+#define IMX8MQ_CLK_SDMA2_ROOT			242
+#define IMX8MQ_CLK_VPU_G1_ROOT			243
+#define IMX8MQ_CLK_VPU_G2_ROOT			244
+
+/* SCCG PLL GATE */
+#define IMX8MQ_SYS1_PLL_OUT			245
+#define IMX8MQ_SYS2_PLL_OUT			246
+#define IMX8MQ_SYS3_PLL_OUT			247
+#define IMX8MQ_DRAM_PLL_OUT			248
+
+#define IMX8MQ_GPT_3M_CLK			249
+
+#define IMX8MQ_CLK_IPG_ROOT			250
+#define IMX8MQ_CLK_IPG_AUDIO_ROOT		251
+#define IMX8MQ_CLK_SAI1_IPG			252
+#define IMX8MQ_CLK_SAI2_IPG			253
+#define IMX8MQ_CLK_SAI3_IPG			254
+#define IMX8MQ_CLK_SAI4_IPG			255
+#define IMX8MQ_CLK_SAI5_IPG			256
+#define IMX8MQ_CLK_SAI6_IPG			257
+
+/* DSI AHB/IPG clocks */
+/* rxesc clock */
+#define IMX8MQ_CLK_DSI_AHB                  258
+/* txesc clock */
+#define IMX8MQ_CLK_DSI_IPG_DIV                  259
+
+/* VIDEO2 PLL */
+#define IMX8MQ_VIDEO2_PLL1_REF_SEL		260
+#define IMX8MQ_VIDEO2_PLL1_REF_DIV		261
+#define IMX8MQ_VIDEO2_PLL1			262
+#define IMX8MQ_VIDEO2_PLL1_OUT			263
+#define IMX8MQ_VIDEO2_PLL1_OUT_DIV		264
+#define IMX8MQ_VIDEO2_PLL2			265
+#define IMX8MQ_VIDEO2_PLL2_DIV			266
+#define IMX8MQ_VIDEO2_PLL2_OUT			267
+#define IMX8MQ_CLK_TMU_ROOT			268
+
+/* Display root clocks */
+#define IMX8MQ_CLK_DISP_AXI_ROOT		269
+#define IMX8MQ_CLK_DISP_APB_ROOT		270
+#define IMX8MQ_CLK_DISP_RTRM_ROOT		271
+
+#define IMX8MQ_CLK_OCOTP_ROOT			272
+
+#define IMX8MQ_CLK_DRAM_ALT_ROOT		273
+#define IMX8MQ_CLK_DRAM_CORE			274
+
+#define IMX8MQ_CLK_MU_ROOT			275
+#define IMX8MQ_VIDEO2_PLL_OUT			276
+
+#define IMX8MQ_CLK_CLKO2			277
+
+#define IMX8MQ_CLK_NAND_USDHC_BUS_RAWNAND_CLK	278
+
+#define IMX8MQ_CLK_PHY_27MHZ			279
+
+#define IMX8MQ_CLK_END                         280
+
+#endif /* __DT_BINDINGS_CLOCK_IMX8MQ_H */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/imx8qm-clock.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/imx8qm-clock.h
new file mode 100644
index 0000000000000000000000000000000000000000..820ea0dcc3d5ea291ce4a9c160ea03e12a91cea6
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/imx8qm-clock.h
@@ -0,0 +1,866 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_IMX8QM_H
+#define __DT_BINDINGS_CLOCK_IMX8QM_H
+
+#define IMX8QM_CLK_DUMMY					0
+
+#define IMX8QM_A53_DIV						1
+#define IMX8QM_A53_CLK						2
+#define IMX8QM_A72_DIV						3
+#define IMX8QM_A72_CLK						4
+
+/* SC Clocks. */
+#define IMX8QM_SC_I2C_DIV					5
+#define IMX8QM_SC_I2C_CLK					6
+#define IMX8QM_SC_PID0_DIV					7
+#define IMX8QM_SC_PID0_CLK					8
+#define IMX8QM_SC_PIT_DIV					9
+#define IMX8QM_SC_PIT_CLK					10
+#define IMX8QM_SC_TPM_DIV					11
+#define IMX8QM_SC_TPM_CLK					12
+#define IMX8QM_SC_UART_DIV					13
+#define IMX8QM_SC_UART_CLK					14
+
+/* LSIO */
+#define IMX8QM_PWM0_DIV						15
+#define IMX8QM_PWM0_CLK						16
+#define IMX8QM_PWM1_DIV						17
+#define IMX8QM_PWM1_CLK						18
+#define IMX8QM_PWM2_DIV						19
+#define IMX8QM_PWM2_CLK						20
+#define IMX8QM_PWM3_DIV						21
+#define IMX8QM_PWM3_CLK						22
+#define IMX8QM_PWM4_DIV						23
+#define IMX8QM_PWM4_CLK						24
+#define IMX8QM_PWM5_DIV						26
+#define IMX8QM_PWM5_CLK						27
+#define IMX8QM_PWM6_DIV						28
+#define IMX8QM_PWM6_CLK						29
+#define IMX8QM_PWM7_DIV						30
+#define IMX8QM_PWM7_CLK						31
+#define IMX8QM_FSPI0_DIV					32
+#define IMX8QM_FSPI0_CLK					33
+#define IMX8QM_FSPI1_DIV					34
+#define IMX8QM_FSPI1_CLK					35
+#define IMX8QM_GPT0_DIV						36
+#define IMX8QM_GPT0_CLK						37
+#define IMX8QM_GPT1_DIV						38
+#define IMX8QM_GPT1_CLK						39
+#define IMX8QM_GPT2_DIV						40
+#define IMX8QM_GPT2_CLK						41
+#define IMX8QM_GPT3_DIV						42
+#define IMX8QM_GPT3_CLK						43
+#define IMX8QM_GPT4_DIV						44
+#define IMX8QM_GPT4_CLK						45
+
+/* Connectivity */
+#define IMX8QM_APBHDMA_CLK					46
+#define IMX8QM_GPMI_APB_CLK					47
+#define IMX8QM_GPMI_APB_BCH_CLK				48
+#define IMX8QM_GPMI_BCH_IO_DIV				49
+#define IMX8QM_GPMI_BCH_IO_CLK				50
+#define IMX8QM_GPMI_BCH_DIV					51
+#define IMX8QM_GPMI_BCH_CLK					52
+#define IMX8QM_SDHC0_IPG_CLK				53
+#define IMX8QM_SDHC0_DIV					54
+#define IMX8QM_SDHC0_CLK					55
+#define IMX8QM_SDHC1_IPG_CLK				56
+#define IMX8QM_SDHC1_DIV					57
+#define IMX8QM_SDHC1_CLK					58
+#define IMX8QM_SDHC2_IPG_CLK				59
+#define IMX8QM_SDHC2_DIV					60
+#define IMX8QM_SDHC2_CLK					61
+#define IMX8QM_USB2_OH_AHB_CLK				62
+#define IMX8QM_USB2_OH_IPG_S_CLK			63
+#define IMX8QM_USB2_OH_IPG_S_PL301_CLK		64
+#define IMX8QM_USB2_PHY_IPG_CLK				65
+#define IMX8QM_USB3_IPG_CLK					66
+#define IMX8QM_USB3_CORE_PCLK				67
+#define IMX8QM_USB3_PHY_CLK					68
+#define IMX8QM_USB3_ACLK_DIV				69
+#define IMX8QM_USB3_ACLK					70
+#define IMX8QM_USB3_BUS_DIV					71
+#define IMX8QM_USB3_BUS_CLK					72
+#define IMX8QM_USB3_LPM_DIV					73
+#define IMX8QM_USB3_LPM_CLK					74
+#define IMX8QM_ENET0_AHB_CLK				75
+#define IMX8QM_ENET0_IPG_S_CLK				76
+#define IMX8QM_ENET0_IPG_CLK				77
+#define IMX8QM_ENET0_RGMII_DIV				78
+#define IMX8QM_ENET0_RGMII_TX_CLK			79
+#define IMX8QM_ENET0_ROOT_DIV				80
+#define IMX8QM_ENET0_TX_CLK					81
+#define IMX8QM_ENET0_ROOT_CLK				82
+#define IMX8QM_ENET0_PTP_CLK				83
+#define IMX8QM_ENET0_BYPASS_DIV				84
+#define IMX8QM_ENET1_AHB_CLK				85
+#define IMX8QM_ENET1_IPG_S_CLK				86
+#define IMX8QM_ENET1_IPG_CLK				87
+#define IMX8QM_ENET1_RGMII_DIV				88
+#define IMX8QM_ENET1_RGMII_TX_CLK			89
+#define IMX8QM_ENET1_ROOT_DIV				90
+#define IMX8QM_ENET1_TX_CLK					91
+#define IMX8QM_ENET1_ROOT_CLK				92
+#define IMX8QM_ENET1_PTP_CLK				93
+#define IMX8QM_ENET1_BYPASS_DIV				94
+#define IMX8QM_MLB_CLK						95
+#define IMX8QM_MLB_HCLK						96
+#define IMX8QM_MLB_IPG_CLK					97
+#define IMX8QM_EDMA_CLK						98
+#define IMX8QM_EDMA_IPG_CLK					99
+
+/* DMA */
+#define IMX8QM_SPI0_IPG_CLK					100
+#define IMX8QM_SPI0_DIV						101
+#define IMX8QM_SPI0_CLK					102
+#define IMX8QM_SPI1_IPG_CLK					103
+#define IMX8QM_SPI1_DIV						104
+#define IMX8QM_SPI1_CLK						105
+#define IMX8QM_SPI2_IPG_CLK					106
+#define IMX8QM_SPI2_DIV						107
+#define IMX8QM_SPI2_CLK						108
+#define IMX8QM_SPI3_IPG_CLK					109
+#define IMX8QM_SPI3_DIV						110
+#define IMX8QM_SPI3_CLK						111
+#define IMX8QM_UART0_IPG_CLK				112
+#define IMX8QM_UART0_DIV					113
+#define IMX8QM_UART0_CLK					114
+#define IMX8QM_UART1_IPG_CLK				115
+#define IMX8QM_UART1_DIV					116
+#define IMX8QM_UART1_CLK					117
+#define IMX8QM_UART2_IPG_CLK				118
+#define IMX8QM_UART2_DIV					119
+#define IMX8QM_UART2_CLK					120
+#define IMX8QM_UART3_IPG_CLK				121
+#define IMX8QM_UART3_DIV					122
+#define IMX8QM_UART3_CLK					123
+#define IMX8QM_UART4_IPG_CLK				124
+#define IMX8QM_UART4_DIV					125
+#define IMX8QM_EMVSIM0_IPG_CLK				126
+#define IMX8QM_UART4_CLK					127
+#define IMX8QM_EMVSIM0_DIV					128
+#define IMX8QM_EMVSIM0_CLK					129
+#define IMX8QM_EMVSIM1_IPG_CLK				130
+#define IMX8QM_EMVSIM1_DIV					131
+#define IMX8QM_EMVSIM1_CLK					132
+#define IMX8QM_CAN0_IPG_CHI_CLK				133
+#define IMX8QM_CAN0_IPG_CLK					134
+#define IMX8QM_CAN0_DIV						135
+#define IMX8QM_CAN0_CLK						136
+#define IMX8QM_CAN1_IPG_CHI_CLK				137
+#define IMX8QM_CAN1_IPG_CLK					138
+#define IMX8QM_CAN1_DIV						139
+#define IMX8QM_CAN1_CLK						140
+#define IMX8QM_CAN2_IPG_CHI_CLK				141
+#define IMX8QM_CAN2_IPG_CLK					142
+#define IMX8QM_CAN2_DIV						143
+#define IMX8QM_CAN2_CLK						144
+#define IMX8QM_I2C0_IPG_CLK					145
+#define IMX8QM_I2C0_DIV						146
+#define IMX8QM_I2C0_CLK						147
+#define IMX8QM_I2C1_IPG_CLK					148
+#define IMX8QM_I2C1_DIV						149
+#define IMX8QM_I2C1_CLK						150
+#define IMX8QM_I2C2_IPG_CLK					151
+#define IMX8QM_I2C2_DIV						152
+#define IMX8QM_I2C2_CLK						153
+#define IMX8QM_I2C3_IPG_CLK					154
+#define IMX8QM_I2C3_DIV						155
+#define IMX8QM_I2C3_CLK						156
+#define IMX8QM_I2C4_IPG_CLK					157
+#define IMX8QM_I2C4_DIV						158
+#define IMX8QM_I2C4_CLK						159
+#define IMX8QM_FTM0_IPG_CLK					160
+#define IMX8QM_FTM0_DIV						161
+#define IMX8QM_FTM0_CLK						162
+#define IMX8QM_FTM1_IPG_CLK					163
+#define IMX8QM_FTM1_DIV						164
+#define IMX8QM_FTM1_CLK						165
+#define IMX8QM_ADC0_IPG_CLK					166
+#define IMX8QM_ADC0_DIV						167
+#define IMX8QM_ADC0_CLK						168
+#define IMX8QM_ADC1_IPG_CLK					169
+#define IMX8QM_ADC1_DIV						170
+#define IMX8QM_ADC1_CLK						171
+
+/* Audio */
+#define IMX8QM_AUD_PLL0_DIV					172
+#define IMX8QM_AUD_PLL0						173
+#define IMX8QM_AUD_PLL1_DIV					174
+#define IMX8QM_AUD_PLL1						175
+#define IMX8QM_AUD_AMIX_IPG					182
+#define IMX8QM_AUD_ESAI_0_IPG				183
+#define IMX8QM_AUD_ESAI_1_IPG				184
+#define IMX8QM_AUD_ESAI_0_EXTAL_IPG			185
+#define IMX8QM_AUD_ESAI_1_EXTAL_IPG			186
+#define IMX8QM_AUD_SAI_0_IPG				187
+#define IMX8QM_AUD_SAI_0_IPG_S				188
+#define IMX8QM_AUD_SAI_0_MCLK				189
+#define IMX8QM_AUD_SAI_1_IPG				190
+#define IMX8QM_AUD_SAI_1_IPG_S				191
+#define IMX8QM_AUD_SAI_1_MCLK				192
+#define IMX8QM_AUD_SAI_2_IPG				193
+#define IMX8QM_AUD_SAI_2_IPG_S				194
+#define IMX8QM_AUD_SAI_2_MCLK				195
+#define IMX8QM_AUD_SAI_3_IPG				196
+#define IMX8QM_AUD_SAI_3_IPG_S				197
+#define IMX8QM_AUD_SAI_3_MCLK				198
+#define IMX8QM_AUD_SAI_6_IPG				199
+#define IMX8QM_AUD_SAI_6_IPG_S				200
+#define IMX8QM_AUD_SAI_6_MCLK				201
+#define IMX8QM_AUD_SAI_7_IPG				202
+#define IMX8QM_AUD_SAI_7_IPG_S				203
+#define IMX8QM_AUD_SAI_7_MCLK				204
+#define IMX8QM_AUD_SAI_HDMIRX0_IPG			205
+#define IMX8QM_AUD_SAI_HDMIRX0_IPG_S		206
+#define IMX8QM_AUD_SAI_HDMIRX0_MCLK			207
+#define IMX8QM_AUD_SAI_HDMITX0_IPG			208
+#define IMX8QM_AUD_SAI_HDMITX0_IPG_S		209
+#define IMX8QM_AUD_SAI_HDMITX0_MCLK			210
+#define IMX8QM_AUD_MQS_IPG					211
+#define IMX8QM_AUD_MQS_HMCLK				212
+#define IMX8QM_AUD_GPT5_IPG_S				213
+#define IMX8QM_AUD_GPT5_CLKIN				214
+#define IMX8QM_AUD_GPT5_24M_CLK				215
+#define IMX8QM_AUD_GPT6_IPG_S				216
+#define IMX8QM_AUD_GPT6_CLKIN				217
+#define IMX8QM_AUD_GPT6_24M_CLK				218
+#define IMX8QM_AUD_GPT7_IPG_S				219
+#define IMX8QM_AUD_GPT7_CLKIN				220
+#define IMX8QM_AUD_GPT7_24M_CLK				221
+#define IMX8QM_AUD_GPT8_IPG_S				222
+#define IMX8QM_AUD_GPT8_CLKIN				223
+#define IMX8QM_AUD_GPT8_24M_CLK				224
+#define IMX8QM_AUD_GPT9_IPG_S				225
+#define IMX8QM_AUD_GPT9_CLKIN				226
+#define IMX8QM_AUD_GPT9_24M_CLK				227
+#define IMX8QM_AUD_GPT10_IPG_S				228
+#define IMX8QM_AUD_GPT10_CLKIN				229
+#define IMX8QM_AUD_GPT10_24M_CLK			230
+#define IMX8QM_AUD_ACM_AUD_PLL_CLK0_DIV		232
+#define IMX8QM_AUD_ACM_AUD_PLL_CLK0_CLK		233
+#define IMX8QM_AUD_ACM_AUD_PLL_CLK1_DIV		234
+#define IMX8QM_AUD_ACM_AUD_PLL_CLK1_CLK		235
+#define IMX8QM_AUD_ACM_AUD_REC_CLK0_DIV		236
+#define IMX8QM_AUD_ACM_AUD_REC_CLK0_CLK		237
+#define IMX8QM_AUD_ACM_AUD_REC_CLK1_DIV		238
+#define IMX8QM_AUD_ACM_AUD_REC_CLK1_CLK		239
+#define IMX8QM_AUD_MCLKOUT0					240
+#define IMX8QM_AUD_MCLKOUT1					241
+#define IMX8QM_AUD_SPDIF_0_TX_CLK			242
+#define IMX8QM_AUD_SPDIF_0_GCLKW			243
+#define IMX8QM_AUD_SPDIF_0_IPG_S			244
+#define IMX8QM_AUD_SPDIF_1_TX_CLK			245
+#define IMX8QM_AUD_SPDIF_1_GCLKW			246
+#define IMX8QM_AUD_SPDIF_1_IPG_S			247
+#define IMX8QM_AUD_ASRC_0_IPG				248
+#define IMX8QM_AUD_ASRC_0_MEM				249
+#define IMX8QM_AUD_ASRC_1_IPG				250
+#define IMX8QM_AUD_ASRC_1_MEM				251
+
+
+/* VPU */
+#define IMX8QM_VPU_CORE_DIV					252
+#define IMX8QM_VPU_CORE_CLK					253
+#define IMX8QM_VPU_UART_DIV					254
+#define IMX8QM_VPU_UART_CLK					255
+#define IMX8QM_VPU_DDR_DIV					256
+#define IMX8QM_VPU_DDR_CLK					257
+#define IMX8QM_VPU_SYS_DIV				258
+#define IMX8QM_VPU_SYS_CLK				259
+#define IMX8QM_VPU_XUVI_DIV					260
+#define IMX8QM_VPU_XUVI_CLK					261
+
+/* GPU Clocks. */
+#define IMX8QM_GPU0_CORE_DIV				262
+#define IMX8QM_GPU0_CORE_CLK				263
+#define IMX8QM_GPU0_SHADER_DIV				264
+#define IMX8QM_GPU0_SHADER_CLK				265
+#define IMX8QM_GPU1_CORE_DIV				266
+#define IMX8QM_GPU1_CORE_CLK				267
+#define IMX8QM_GPU1_SHADER_DIV				268
+#define IMX8QM_GPU1_SHADER_CLK				269
+
+
+/* MIPI CSI */
+#define IMX8QM_CSI0_IPG_CLK_S				270
+#define IMX8QM_CSI0_LIS_IPG_CLK				271
+#define IMX8QM_CSI0_APB_CLK					272
+#define IMX8QM_CSI0_I2C0_DIV				273
+#define IMX8QM_CSI0_I2C0_CLK				274
+#define IMX8QM_CSI0_PWM0_DIV				275
+#define IMX8QM_CSI0_PWM0_CLK				276
+#define IMX8QM_CSI0_CORE_DIV				277
+#define IMX8QM_CSI0_CORE_CLK				278
+#define IMX8QM_CSI0_ESC_DIV					279
+#define IMX8QM_CSI0_ESC_CLK					280
+#define IMX8QM_CSI1_IPG_CLK_S				281
+#define IMX8QM_CSI1_LIS_IPG_CLK				282
+#define IMX8QM_CSI1_APB_CLK					283
+#define IMX8QM_CSI1_I2C0_DIV				284
+#define IMX8QM_CSI1_I2C0_CLK				285
+#define IMX8QM_CSI1_PWM0_DIV				286
+#define IMX8QM_CSI1_PWM0_CLK				287
+#define IMX8QM_CSI1_CORE_DIV				288
+#define IMX8QM_CSI1_CORE_CLK				289
+#define IMX8QM_CSI1_ESC_DIV					290
+#define IMX8QM_CSI1_ESC_CLK					291
+
+
+/* Display */
+#define IMX8QM_DC0_PLL0_DIV					292
+#define IMX8QM_DC0_PLL0_CLK					293
+#define IMX8QM_DC0_PLL1_DIV					294
+#define IMX8QM_DC0_PLL1_CLK					295
+#define IMX8QM_DC0_DISP0_DIV				296
+#define IMX8QM_DC0_DISP0_CLK				297
+#define IMX8QM_DC0_DISP1_DIV				298
+#define IMX8QM_DC0_DISP1_CLK				299
+#define IMX8QM_DC0_BYPASS_0_DIV				300
+#define IMX8QM_DC0_BYPASS_1_DIV				301
+#define IMX8QM_DC0_IRIS_AXI_CLK				302
+#define IMX8AM_DC0_IRIS_MVPL_CLK			303
+#define IMX8QM_DC0_DISP0_MSI_CLK			304
+#define IMX8QM_DC0_LIS_IPG_CLK				305
+#define IMX8QM_DC0_PXL_CMB_APB_CLK			306
+#define IMX8QM_DC0_PRG0_RTRAM_CLK			307
+#define IMX8QM_DC0_PRG1_RTRAM_CLK			308
+#define IMX8QM_DC0_PRG2_RTRAM_CLK			309
+#define IMX8QM_DC0_PRG3_RTRAM_CLK			310
+#define IMX8QM_DC0_PRG4_RTRAM_CLK			311
+#define IMX8QM_DC0_PRG5_RTRAM_CLK			312
+#define IMX8QM_DC0_PRG6_RTRAM_CLK			313
+#define IMX8QM_DC0_PRG7_RTRAM_CLK			314
+#define IMX8QM_DC0_PRG8_RTRAM_CLK			315
+#define IMX8QM_DC0_PRG0_APB_CLK				316
+#define IMX8QM_DC0_PRG1_APB_CLK				317
+#define IMX8QM_DC0_PRG2_APB_CLK				318
+#define IMX8QM_DC0_PRG3_APB_CLK				319
+#define IMX8QM_DC0_PRG4_APB_CLK				320
+#define IMX8QM_DC0_PRG5_APB_CLK				321
+#define IMX8QM_DC0_PRG6_APB_CLK				322
+#define IMX8QM_DC0_PRG7_APB_CLK				323
+#define IMX8QM_DC0_PRG8_APB_CLK				324
+#define IMX8QM_DC0_DPR0_APB_CLK				325
+#define IMX8QM_DC0_DPR1_APB_CLK				326
+#define IMX8QM_DC0_RTRAM0_CLK				327
+#define IMX8QM_DC0_RTRAM1_CLK				328
+#define IMX8QM_DC1_PLL0_DIV					329
+#define IMX8QM_DC1_PLL0_CLK					330
+#define IMX8QM_DC1_PLL1_DIV					331
+#define IMX8QM_DC1_PLL1_CLK					332
+#define IMX8QM_DC1_DISP0_DIV				333
+#define IMX8QM_DC1_DISP0_CLK				334
+#define IMX8QM_DC1_BYPASS_0_DIV				335
+#define IMX8QM_DC1_BYPASS_1_DIV				336
+#define IMX8QM_DC1_DISP1_DIV				337
+#define IMX8QM_DC1_DISP1_CLK				338
+#define IMX8QM_DC1_IRIS_AXI_CLK				339
+#define IMX8AM_DC1_IRIS_MVPL_CLK			340
+#define IMX8QM_DC1_DISP0_MSI_CLK			341
+#define IMX8QM_DC1_LIS_IPG_CLK				342
+#define IMX8QM_DC1_PXL_CMB_APB_CLK			343
+#define IMX8QM_DC1_PRG0_RTRAM_CLK			344
+#define IMX8QM_DC1_PRG1_RTRAM_CLK			345
+#define IMX8QM_DC1_PRG2_RTRAM_CLK			346
+#define IMX8QM_DC1_PRG3_RTRAM_CLK			347
+#define IMX8QM_DC1_PRG4_RTRAM_CLK			348
+#define IMX8QM_DC1_PRG5_RTRAM_CLK			349
+#define IMX8QM_DC1_PRG6_RTRAM_CLK			350
+#define IMX8QM_DC1_PRG7_RTRAM_CLK			351
+#define IMX8QM_DC1_PRG8_RTRAM_CLK			352
+#define IMX8QM_DC1_PRG0_APB_CLK				353
+#define IMX8QM_DC1_PRG1_APB_CLK				354
+#define IMX8QM_DC1_PRG2_APB_CLK				355
+#define IMX8QM_DC1_PRG3_APB_CLK				356
+#define IMX8QM_DC1_PRG4_APB_CLK				357
+#define IMX8QM_DC1_PRG5_APB_CLK				358
+#define IMX8QM_DC1_PRG6_APB_CLK				359
+#define IMX8QM_DC1_PRG7_APB_CLK				360
+#define IMX8QM_DC1_PRG8_APB_CLK				361
+#define IMX8QM_DC1_DPR0_APB_CLK				362
+#define IMX8QM_DC1_DPR1_APB_CLK				363
+#define IMX8QM_DC1_RTRAM0_CLK				364
+#define IMX8QM_DC1_RTRAM1_CLK				365
+
+/* DRC */
+#define IMX8QM_DRC0_PLL0_DIV				366
+#define IMX8QM_DRC0_PLL0_CLK				367
+#define IMX8QM_DRC0_DIV						368
+#define IMX8QM_DRC0_CLK						369
+#define IMX8QM_DRC1_PLL0_DIV				370
+#define IMX8QM_DRC1_PLL0_CLK				371
+#define IMX8QM_DRC1_DIV						372
+#define IMX8QM_DRC1_CLK						373
+
+/* HDMI */
+#define IMX8QM_HDMI_AV_PLL_DIV				374
+#define IMX8QM_HDMI_AV_PLL_CLK				375
+#define IMX8QM_HDMI_I2S_BYPASS_CLK			376
+#define IMX8QM_HDMI_I2C0_DIV				377
+#define IMX8QM_HDMI_I2C0_CLK				378
+#define IMX8QM_HDMI_PXL_DIV					379
+#define IMX8QM_HDMI_PXL_CLK					380
+#define IMX8QM_HDMI_PXL_LINK_DIV			381
+#define IMX8QM_HDMI_PXL_LINK_CLK			382
+#define IMX8QM_HDMI_PXL_MUX_DIV				383
+#define IMX8QM_HDMI_PXL_MUX_CLK				384
+#define IMX8QM_HDMI_I2S_DIV					385
+#define IMX8QM_HDMI_I2S_CLK					386
+#define IMX8QM_HDMI_HDP_CORE_DIV			387
+#define IMX8QM_HDMI_HDP_CORE_CLK			388
+#define IMX8QM_HDMI_I2C_IPG_S_CLK			389
+#define IMX8QM_HDMI_I2C_IPG_CLK				390
+#define IMX8QM_HDMI_PWM_IPG_S_CLK			391
+#define IMX8QM_HDMI_PWM_IPG_CLK				392
+#define IMX8QM_HDMI_PWM_32K_CLK				393
+#define IMX8QM_HDMI_GPIO_IPG_CLK			394
+#define IMX8QM_HDMI_PXL_LINK_SLV_ODD_CLK	395
+#define IMX8QM_HDMI_PXL_LINK_SLV_EVEN_CLK	396
+#define IMX8QM_HDMI_LIS_IPG_CLK				397
+#define IMX8QM_HDMI_MSI_HCLK				398
+#define IMX8QM_HDMI_PXL_EVEN_CLK			399
+#define IMX8QM_HDMI_HDP_CLK					400
+#define IMX8QM_HDMI_PXL_DBL_CLK				401
+#define IMX8QM_HDMI_APB_CLK					402
+#define IMX8QM_HDMI_PXL_LPCG_CLK			403
+#define IMX8QM_HDMI_HDP_PHY_CLK				404
+#define IMX8QM_HDMI_IPG_DIV					405
+#define IMX8QM_HDMI_VIF_CLK					406
+#define IMX8QM_HDMI_DIG_PLL_DIV				407
+#define IMX8QM_HDMI_DIG_PLL_CLK				408
+#define IMX8QM_HDMI_APB_MUX_CSR_CLK			409
+#define IMX8QM_HDMI_APB_MUX_CTRL_CLK		410
+
+/* RX-HDMI */
+#define IMX8QM_HDMI_RX_I2S_BYPASS_CLK		411
+#define IMX8QM_HDMI_RX_BYPASS_CLK			412
+#define IMX8QM_HDMI_RX_SPDIF_BYPASS_CLK		413
+#define IMX8QM_HDMI_RX_I2C0_DIV				414
+#define IMX8QM_HDMI_RX_I2C0_CLK				415
+#define IMX8QM_HDMI_RX_SPDIF_DIV			416
+#define IMX8QM_HDMI_RX_SPDIF_CLK			417
+#define IMX8QM_HDMI_RX_HD_REF_DIV			418
+#define IMX8QM_HDMI_RX_HD_REF_CLK			419
+#define IMX8QM_HDMI_RX_HD_CORE_DIV			420
+#define IMX8QM_HDMI_RX_HD_CORE_CLK			421
+#define IMX8QM_HDMI_RX_PXL_DIV				422
+#define IMX8QM_HDMI_RX_PXL_CLK				423
+#define IMX8QM_HDMI_RX_I2S_DIV				424
+#define IMX8QM_HDMI_RX_I2S_CLK				425
+#define IMX8QM_HDMI_RX_PWM_DIV				426
+#define IMX8QM_HDMI_RX_PWM_CLK				427
+
+/* LVDS */
+#define IMX8QM_LVDS0_BYPASS_CLK				428
+#define IMX8QM_LVDS0_PIXEL_DIV				429
+#define IMX8QM_LVDS0_PIXEL_CLK				430
+#define IMX8QM_LVDS0_PHY_DIV				431
+#define IMX8QM_LVDS0_PHY_CLK				432
+#define IMX8QM_LVDS0_I2C0_IPG_CLK			433
+#define IMX8QM_LVDS0_I2C0_DIV				434
+#define IMX8QM_LVDS0_I2C0_CLK				435
+#define IMX8QM_LVDS0_I2C1_IPG_CLK			436
+#define IMX8QM_LVDS0_I2C1_DIV				437
+#define IMX8QM_LVDS0_I2C1_CLK				438
+#define IMX8QM_LVDS0_PWM0_IPG_CLK			439
+#define IMX8QM_LVDS0_PWM0_DIV				440
+#define IMX8QM_LVDS0_PWM0_CLK				441
+#define IMX8QM_LVDS0_GPIO_IPG_CLK			444
+#define IMX8QM_LVDS1_BYPASS_DIV				445
+#define IMX8QM_LVDS1_BYPASS_CLK				446
+#define IMX8QM_LVDS1_PIXEL_DIV				447
+#define IMX8QM_LVDS1_PIXEL_CLK				448
+#define IMX8QM_LVDS1_PHY_DIV				449
+#define IMX8QM_LVDS1_PHY_CLK				450
+#define IMX8QM_LVDS1_I2C0_IPG_CLK			451
+#define IMX8QM_LVDS1_I2C0_DIV				452
+#define IMX8QM_LVDS1_I2C0_CLK				453
+#define IMX8QM_LVDS1_I2C1_IPG_CLK			454
+#define IMX8QM_LVDS1_I2C1_DIV				455
+#define IMX8QM_LVDS1_I2C1_CLK				456
+#define IMX8QM_LVDS1_PWM0_IPG_CLK			457
+#define IMX8QM_LVDS1_PWM0_DIV				458
+#define IMX8QM_LVDS1_PWM0_CLK				459
+#define IMX8QM_LVDS1_GPIO_IPG_CLK			462
+
+/* MIPI */
+#define IMX8QM_MIPI0_BYPASS_CLK				465
+#define IMX8QM_MIPI0_I2C0_DIV				466
+#define IMX8QM_MIPI0_I2C0_CLK				467
+#define IMX8QM_MIPI0_I2C1_DIV				468
+#define IMX8QM_MIPI0_I2C1_CLK				469
+#define IMX8QM_MIPI0_PWM0_DIV				470
+#define IMX8QM_MIPI0_PWM0_CLK				471
+#define IMX8QM_MIPI0_DSI_TX_ESC_DIV			472
+#define IMX8QM_MIPI0_DSI_TX_ESC_CLK			473
+#define IMX8QM_MIPI0_DSI_RX_ESC_DIV			474
+#define IMX8QM_MIPI0_DSI_RX_ESC_CLK			475
+#define IMX8QM_MIPI0_PXL_DIV				476
+#define IMX8QM_MIPI0_PXL_CLK				477
+#define IMX8QM_MIPI1_BYPASS_CLK				479
+#define IMX8QM_MIPI1_I2C0_DIV				480
+#define IMX8QM_MIPI1_I2C0_CLK				481
+#define IMX8QM_MIPI1_I2C1_DIV				482
+#define IMX8QM_MIPI1_I2C1_CLK				483
+#define IMX8QM_MIPI1_PWM0_DIV				484
+#define IMX8QM_MIPI1_PWM0_CLK				485
+#define IMX8QM_MIPI1_DSI_TX_ESC_DIV			486
+#define IMX8QM_MIPI1_DSI_TX_ESC_CLK			487
+#define IMX8QM_MIPI1_DSI_RX_ESC_DIV			488
+#define IMX8QM_MIPI1_DSI_RX_ESC_CLK			489
+#define IMX8QM_MIPI1_PXL_DIV				490
+#define IMX8QM_MIPI1_PXL_CLK				491
+
+/* Imaging */
+#define IMX8QM_IMG_JPEG_ENC_IPG_CLK			492
+#define IMX8QM_IMG_JPEG_ENC_CLK				493
+#define IMX8QM_IMG_JPEG_DEC_IPG_CLK			494
+#define IMX8QM_IMG_JPEG_DEC_CLK				495
+#define IMX8QM_IMG_PXL_LINK_DC0_CLK			496
+#define IMX8QM_IMG_PXL_LINK_DC1_CLK			497
+#define IMX8QM_IMG_PXL_LINK_CSI0_CLK		498
+#define IMX8QM_IMG_PXL_LINK_CSI1_CLK		499
+#define IMX8QM_IMG_PXL_LINK_HDMI_IN_CLK		500
+#define IMX8QM_IMG_PDMA_0_CLK				501
+#define IMX8QM_IMG_PDMA_1_CLK				502
+#define IMX8QM_IMG_PDMA_2_CLK				503
+#define IMX8QM_IMG_PDMA_3_CLK				504
+#define IMX8QM_IMG_PDMA_4_CLK				505
+#define IMX8QM_IMG_PDMA_5_CLK				506
+#define IMX8QM_IMG_PDMA_6_CLK				507
+#define IMX8QM_IMG_PDMA_7_CLK				508
+
+/* HSIO */
+#define IMX8QM_HSIO_PCIE_A_MSTR_AXI_CLK		509
+#define IMX8QM_HSIO_PCIE_A_SLV_AXI_CLK		510
+#define IMX8QM_HSIO_PCIE_A_DBI_AXI_CLK		511
+#define IMX8QM_HSIO_PCIE_B_MSTR_AXI_CLK		512
+#define IMX8QM_HSIO_PCIE_B_SLV_AXI_CLK		513
+#define IMX8QM_HSIO_PCIE_B_DBI_AXI_CLK		514
+#define IMX8QM_HSIO_PCIE_X1_PER_CLK			515
+#define IMX8QM_HSIO_PCIE_X2_PER_CLK			516
+#define IMX8QM_HSIO_SATA_PER_CLK			517
+#define IMX8QM_HSIO_PHY_X1_PER_CLK			518
+#define IMX8QM_HSIO_PHY_X2_PER_CLK			519
+#define IMX8QM_HSIO_MISC_PER_CLK			520
+#define IMX8QM_HSIO_PHY_X1_APB_CLK			521
+#define IMX8QM_HSIO_PHY_X2_APB_0_CLK		522
+#define IMX8QM_HSIO_PHY_X2_APB_1_CLK		523
+#define IMX8QM_HSIO_SATA_CLK				524
+#define IMX8QM_HSIO_GPIO_CLK				525
+#define IMX8QM_HSIO_PHY_X1_PCLK				526
+#define IMX8QM_HSIO_PHY_X2_PCLK_0			527
+#define IMX8QM_HSIO_PHY_X2_PCLK_1			528
+#define IMX8QM_HSIO_SATA_EPCS_RX_CLK		529
+#define IMX8QM_HSIO_SATA_EPCS_TX_CLK		530
+
+
+/* M4 */
+#define IMX8QM_M4_0_CORE_DIV				531
+#define IMX8QM_M4_0_CORE_CLK				532
+#define IMX8QM_M4_0_I2C_DIV					533
+#define IMX8QM_M4_0_I2C_CLK					534
+#define IMX8QM_M4_0_PIT_DIV					535
+#define IMX8QM_M4_0_PIT_CLK					536
+#define IMX8QM_M4_0_TPM_DIV					537
+#define IMX8QM_M4_0_TPM_CLK					538
+#define IMX8QM_M4_0_UART_DIV				539
+#define IMX8QM_M4_0_UART_CLK				540
+#define IMX8QM_M4_0_WDOG_DIV				541
+#define IMX8QM_M4_0_WDOG_CLK				542
+#define IMX8QM_M4_1_CORE_DIV				543
+#define IMX8QM_M4_1_CORE_CLK				544
+#define IMX8QM_M4_1_I2C_DIV					545
+#define IMX8QM_M4_1_I2C_CLK					546
+#define IMX8QM_M4_1_PIT_DIV					547
+#define IMX8QM_M4_1_PIT_CLK					548
+#define IMX8QM_M4_1_TPM_DIV					549
+#define IMX8QM_M4_1_TPM_CLK					550
+#define IMX8QM_M4_1_UART_DIV				551
+#define IMX8QM_M4_1_UART_CLK				552
+#define IMX8QM_M4_1_WDOG_DIV				553
+#define IMX8QM_M4_1_WDOG_CLK				554
+
+/* IPG clocks */
+#define IMX8QM_24MHZ						555
+#define IMX8QM_GPT_3M						556
+#define IMX8QM_IPG_DMA_CLK_ROOT				557
+#define IMX8QM_IPG_AUD_CLK_ROOT				558
+#define IMX8QM_IPG_CONN_CLK_ROOT			559
+#define IMX8QM_AHB_CONN_CLK_ROOT			560
+#define IMX8QM_AXI_CONN_CLK_ROOT			561
+#define IMX8QM_IPG_MIPI_CSI_CLK_ROOT		562
+#define IMX8QM_DC_AXI_EXT_CLK				563
+#define IMX8QM_DC_AXI_INT_CLK				564
+#define IMX8QM_DC_CFG_CLK					565
+#define IMX8QM_HDMI_IPG_CLK					566
+#define IMX8QM_LVDS_IPG_CLK					567
+#define IMX8QM_IMG_AXI_CLK					568
+#define IMX8QM_IMG_IPG_CLK					569
+#define IMX8QM_IMG_PXL_CLK					570
+#define IMX8QM_CSI0_I2C0_IPG_CLK			571
+#define IMX8QM_CSI0_PWM0_IPG_CLK			572
+#define IMX8QM_CSI1_I2C0_IPG_CLK			573
+#define IMX8QM_CSI1_PWM0_IPG_CLK			574
+#define IMX8QM_DC0_DPR0_B_CLK				575
+#define IMX8QM_DC0_DPR1_B_CLK				576
+#define IMX8QM_DC1_DPR0_B_CLK				577
+#define IMX8QM_DC1_DPR1_B_CLK				578
+#define IMX8QM_32KHZ						579
+#define IMX8QM_HSIO_AXI_CLK					580
+#define IMX8QM_HSIO_PER_CLK					581
+#define IMX8QM_HDMI_RX_GPIO_IPG_S_CLK		582
+#define IMX8QM_HDMI_RX_PWM_IPG_S_CLK		583
+#define IMX8QM_HDMI_RX_PWM_IPG_CLK			584
+#define IMX8QM_HDMI_RX_I2C_DIV_CLK			585
+#define IMX8QM_HDMI_RX_I2C_IPG_S_CLK		586
+#define IMX8QM_HDMI_RX_I2C_IPG_CLK			587
+#define IMX8QM_HDMI_RX_SINK_PCLK			588
+#define IMX8QM_HDMI_RX_SINK_SCLK			589
+#define IMX8QM_HDMI_RX_PXL_ENC_CLK			590
+#define IMX8QM_HDMI_RX_IPG_CLK				591
+
+/* ACM */
+#define IMX8QM_HDMI_RX_MCLK			592
+#define IMX8QM_EXT_AUD_MCLK0			593
+#define IMX8QM_EXT_AUD_MCLK1			594
+#define IMX8QM_ESAI0_RX_CLK			595
+#define IMX8QM_ESAI0_RX_HF_CLK			596
+#define IMX8QM_ESAI0_TX_CLK			597
+#define IMX8QM_ESAI0_TX_HF_CLK			598
+#define IMX8QM_ESAI1_RX_CLK			599
+#define IMX8QM_ESAI1_RX_HF_CLK			600
+#define IMX8QM_ESAI1_TX_CLK			601
+#define IMX8QM_ESAI1_TX_HF_CLK			602
+#define IMX8QM_SPDIF0_RX			603
+#define IMX8QM_SPDIF1_RX			604
+#define IMX8QM_SAI0_RX_BCLK			605
+#define IMX8QM_SAI0_TX_BCLK			606
+#define IMX8QM_SAI1_RX_BCLK			607
+#define IMX8QM_SAI1_TX_BCLK			608
+#define IMX8QM_SAI2_RX_BCLK			609
+#define IMX8QM_SAI3_RX_BCLK			610
+#define IMX8QM_HDMI_RX_SAI0_RX_BCLK		611
+#define IMX8QM_SAI6_RX_BCLK			612
+#define IMX8QM_HDMI_TX_SAI0_TX_BCLK		613
+
+#define IMX8QM_ACM_AUD_CLK0_SEL		614
+#define IMX8QM_ACM_AUD_CLK0_CLK		615
+#define IMX8QM_ACM_AUD_CLK1_SEL		616
+#define IMX8QM_ACM_AUD_CLK1_CLK		617
+#define IMX8QM_ACM_MCLKOUT0_SEL		618
+#define IMX8QM_ACM_MCLKOUT0_CLK		619
+#define IMX8QM_ACM_MCLKOUT1_SEL		620
+#define IMX8QM_ACM_MCLKOUT1_CLK		621
+#define IMX8QM_ACM_ASRC0_MUX_CLK_SEL		622
+#define IMX8QM_ACM_ASRC0_MUX_CLK_CLK		623
+#define IMX8QM_ACM_ASRC1_MUX_CLK_SEL		624
+#define IMX8QM_ACM_ASRC1_MUX_CLK_CLK		625
+#define IMX8QM_ACM_ESAI0_MCLK_SEL		626
+#define IMX8QM_ACM_ESAI0_MCLK_CLK		627
+#define IMX8QM_ACM_ESAI1_MCLK_SEL		628
+#define IMX8QM_ACM_ESAI1_MCLK_CLK		629
+#define IMX8QM_ACM_GPT0_MUX_CLK_SEL		630
+#define IMX8QM_ACM_GPT0_MUX_CLK_CLK		631
+#define IMX8QM_ACM_GPT1_MUX_CLK_SEL		632
+#define IMX8QM_ACM_GPT1_MUX_CLK_CLK		633
+#define IMX8QM_ACM_GPT2_MUX_CLK_SEL		634
+#define IMX8QM_ACM_GPT2_MUX_CLK_CLK		635
+#define IMX8QM_ACM_GPT3_MUX_CLK_SEL		636
+#define IMX8QM_ACM_GPT3_MUX_CLK_CLK		637
+#define IMX8QM_ACM_GPT4_MUX_CLK_SEL		638
+#define IMX8QM_ACM_GPT4_MUX_CLK_CLK		639
+#define IMX8QM_ACM_GPT5_MUX_CLK_SEL		640
+#define IMX8QM_ACM_GPT5_MUX_CLK_CLK		641
+#define IMX8QM_ACM_SAI0_MCLK_SEL		642
+#define IMX8QM_ACM_SAI0_MCLK_CLK		643
+#define IMX8QM_ACM_SAI1_MCLK_SEL		644
+#define IMX8QM_ACM_SAI1_MCLK_CLK		645
+#define IMX8QM_ACM_SAI2_MCLK_SEL		646
+#define IMX8QM_ACM_SAI2_MCLK_CLK		647
+#define IMX8QM_ACM_SAI3_MCLK_SEL		648
+#define IMX8QM_ACM_SAI3_MCLK_CLK		649
+#define IMX8QM_ACM_HDMI_RX_SAI0_MCLK_SEL	650
+#define IMX8QM_ACM_HDMI_RX_SAI0_MCLK_CLK	651
+#define IMX8QM_ACM_HDMI_TX_SAI0_MCLK_SEL	652
+#define IMX8QM_ACM_HDMI_TX_SAI0_MCLK_CLK	653
+#define IMX8QM_ACM_SAI6_MCLK_SEL		654
+#define IMX8QM_ACM_SAI6_MCLK_CLK		655
+#define IMX8QM_ACM_SAI7_MCLK_SEL		656
+#define IMX8QM_ACM_SAI7_MCLK_CLK		657
+#define IMX8QM_ACM_SPDIF0_TX_CLK_SEL		658
+#define IMX8QM_ACM_SPDIF0_TX_CLK_CLK		659
+#define IMX8QM_ACM_SPDIF1_TX_CLK_SEL		660
+#define IMX8QM_ACM_SPDIF1_TX_CLK_CLK		661
+#define IMX8QM_ACM_MQS_TX_CLK_SEL		662
+#define IMX8QM_ACM_MQS_TX_CLK_CLK		663
+
+#define IMX8QM_ENET0_REF_25MHZ_125MHZ_SEL	664
+#define IMX8QM_ENET0_REF_25MHZ_125MHZ_CLK	665
+#define IMX8QM_ENET1_REF_25MHZ_125MHZ_SEL	666
+#define IMX8QM_ENET1_REF_25MHZ_125MHZ_CLK	667
+#define IMX8QM_ENET0_REF_50MHZ_CLK			668
+#define IMX8QM_ENET1_REF_50MHZ_CLK			669
+#define IMX8QM_ENET_25MHZ_CLK				670
+#define IMX8QM_ENET_125MHZ_CLK				671
+#define IMX8QM_ENET0_REF_DIV				672
+#define IMX8QM_ENET0_REF_CLK				673
+#define IMX8QM_ENET1_REF_DIV				674
+#define IMX8QM_ENET1_REF_CLK				675
+#define IMX8QM_ENET0_RMII_TX_CLK			676
+#define IMX8QM_ENET1_RMII_TX_CLK			677
+#define IMX8QM_ENET0_RMII_TX_SEL			678
+#define IMX8QM_ENET1_RMII_TX_SEL			679
+#define IMX8QM_ENET0_RMII_RX_CLK			680
+#define IMX8QM_ENET1_RMII_RX_CLK			681
+
+#define IMX8QM_KPP_CLK						683
+#define IMX8QM_GPT0_HF_CLK					684
+#define IMX8QM_GPT0_IPG_S_CLK				685
+#define IMX8QM_GPT0_IPG_SLV_CLK				686
+#define IMX8QM_GPT0_IPG_MSTR_CLK			687
+#define IMX8QM_GPT1_HF_CLK					688
+#define IMX8QM_GPT1_IPG_S_CLK				689
+#define IMX8QM_GPT1_IPG_SLV_CLK				690
+#define IMX8QM_GPT1_IPG_MSTR_CLK			691
+#define IMX8QM_GPT2_HF_CLK					692
+#define IMX8QM_GPT2_IPG_S_CLK				693
+#define IMX8QM_GPT2_IPG_SLV_CLK				694
+#define IMX8QM_GPT2_IPG_MSTR_CLK			695
+#define IMX8QM_GPT3_HF_CLK					696
+#define IMX8QM_GPT3_IPG_S_CLK				697
+#define IMX8QM_GPT3_IPG_SLV_CLK				698
+#define IMX8QM_GPT3_IPG_MSTR_CLK			699
+#define IMX8QM_GPT4_HF_CLK					700
+#define IMX8QM_GPT4_IPG_S_CLK				701
+#define IMX8QM_GPT4_IPG_SLV_CLK				702
+#define IMX8QM_GPT4_IPG_MSTR_CLK			703
+#define IMX8QM_PWM0_HF_CLK					704
+#define IMX8QM_PWM0_IPG_S_CLK				705
+#define IMX8QM_PWM0_IPG_SLV_CLK				706
+#define IMX8QM_PWM0_IPG_MSTR_CLK			707
+#define IMX8QM_PWM1_HF_CLK					708
+#define IMX8QM_PWM1_IPG_S_CLK				709
+#define IMX8QM_PWM1_IPG_SLV_CLK				710
+#define IMX8QM_PWM1_IPG_MSTR_CLK			711
+#define IMX8QM_PWM2_HF_CLK					712
+#define IMX8QM_PWM2_IPG_S_CLK				713
+#define IMX8QM_PWM2_IPG_SLV_CLK				714
+#define IMX8QM_PWM2_IPG_MSTR_CLK			715
+#define IMX8QM_PWM3_HF_CLK					716
+#define IMX8QM_PWM3_IPG_S_CLK				717
+#define IMX8QM_PWM3_IPG_SLV_CLK				718
+#define IMX8QM_PWM3_IPG_MSTR_CLK			719
+#define IMX8QM_PWM4_HF_CLK					720
+#define IMX8QM_PWM4_IPG_S_CLK				721
+#define IMX8QM_PWM4_IPG_SLV_CLK				722
+#define IMX8QM_PWM4_IPG_MSTR_CLK			723
+#define IMX8QM_PWM5_HF_CLK					724
+#define IMX8QM_PWM5_IPG_S_CLK				725
+#define IMX8QM_PWM5_IPG_SLV_CLK				726
+#define IMX8QM_PWM5_IPG_MSTR_CLK			727
+#define IMX8QM_PWM6_HF_CLK					728
+#define IMX8QM_PWM6_IPG_S_CLK				729
+#define IMX8QM_PWM6_IPG_SLV_CLK				730
+#define IMX8QM_PWM6_IPG_MSTR_CLK			731
+#define IMX8QM_PWM7_HF_CLK					732
+#define IMX8QM_PWM7_IPG_S_CLK				733
+#define IMX8QM_PWM7_IPG_SLV_CLK				734
+#define IMX8QM_PWM7_IPG_MSTR_CLK			735
+#define IMX8QM_FSPI0_HCLK					736
+#define IMX8QM_FSPI0_IPG_CLK				737
+#define IMX8QM_FSPI0_IPG_S_CLK				738
+#define IMX8QM_FSPI1_HCLK					736
+#define IMX8QM_FSPI1_IPG_CLK				737
+#define IMX8QM_FSPI1_IPG_S_CLK				738
+#define IMX8QM_GPIO0_IPG_S_CLK				739
+#define IMX8QM_GPIO1_IPG_S_CLK				740
+#define IMX8QM_GPIO2_IPG_S_CLK				741
+#define IMX8QM_GPIO3_IPG_S_CLK				742
+#define IMX8QM_GPIO4_IPG_S_CLK				743
+#define IMX8QM_GPIO5_IPG_S_CLK				744
+#define IMX8QM_GPIO6_IPG_S_CLK				745
+#define IMX8QM_GPIO7_IPG_S_CLK				746
+#define IMX8QM_ROMCP_CLK					747
+#define IMX8QM_ROMCP_REG_CLK				748
+#define IMX8QM_96KROM_CLK					749
+#define IMX8QM_OCRAM_MEM_CLK				750
+#define IMX8QM_OCRAM_CTRL_CLK				751
+#define IMX8QM_LSIO_BUS_CLK					752
+#define IMX8QM_LSIO_MEM_CLK					753
+#define IMX8QM_LVDS0_LIS_IPG_CLK			754
+#define IMX8QM_LVDS1_LIS_IPG_CLK			755
+#define IMX8QM_MIPI0_LIS_IPG_CLK			756
+#define IMX8QM_MIPI0_I2C0_IPG_S_CLK			757
+#define IMX8QM_MIPI0_I2C0_IPG_CLK			758
+#define IMX8QM_MIPI0_I2C1_IPG_S_CLK			759
+#define IMX8QM_MIPI0_I2C1_IPG_CLK			760
+#define IMX8QM_MIPI0_CLK_ROOT				761
+#define IMX8QM_MIPI1_LIS_IPG_CLK			762
+#define IMX8QM_MIPI1_I2C0_IPG_S_CLK			763
+#define IMX8QM_MIPI1_I2C0_IPG_CLK			764
+#define IMX8QM_MIPI1_I2C1_IPG_S_CLK			765
+#define IMX8QM_MIPI1_I2C1_IPG_CLK			766
+#define IMX8QM_MIPI1_CLK_ROOT				767
+#define IMX8QM_DC0_DISP0_SEL				768
+#define IMX8QM_DC0_DISP1_SEL				769
+#define IMX8QM_DC1_DISP0_SEL				770
+#define IMX8QM_DC1_DISP1_SEL				771
+
+/* CM40 */
+#define IMX8QM_CM40_IPG_CLK				772
+#define IMX8QM_CM40_I2C_DIV				773
+#define IMX8QM_CM40_I2C_CLK				774
+#define IMX8QM_CM40_I2C_IPG_CLK				775
+
+/* CM41 */
+#define IMX8QM_CM41_IPG_CLK				776
+#define IMX8QM_CM41_I2C_DIV				777
+#define IMX8QM_CM41_I2C_CLK				778
+#define IMX8QM_CM41_I2C_IPG_CLK				779
+
+#define IMX8QM_HDMI_PXL_SEL					780
+#define IMX8QM_HDMI_PXL_LINK_SEL			781
+#define IMX8QM_HDMI_PXL_MUX_SEL 			782
+#define IMX8QM_HDMI_AV_PLL_BYPASS_CLK		783
+
+#define IMX8QM_HDMI_RX_PXL_SEL				784
+#define IMX8QM_HDMI_RX_HD_REF_SEL			785
+#define IMX8QM_HDMI_RX_HD_CORE_SEL			786
+#define IMX8QM_HDMI_RX_DIG_PLL_CLK			787
+
+#define IMX8QM_LSIO_MU5A_IPG_S_CLK			788
+#define IMX8QM_LSIO_MU5A_IPG_CLK			789
+#define IMX8QM_LSIO_MU6A_IPG_S_CLK			790
+#define IMX8QM_LSIO_MU6A_IPG_CLK			791
+
+/* DSP */
+#define IMX8QM_AUD_DSP_ADB_ACLK		792
+#define IMX8QM_AUD_DSP_IPG		793
+#define IMX8QM_AUD_DSP_CORE_CLK		794
+#define IMX8QM_AUD_OCRAM_IPG		795
+
+/* MIPI DSI */
+#define IMX8QM_MIPI0_DSI_PHY_DIV			796
+#define IMX8QM_MIPI0_DSI_PHY_CLK			797
+#define IMX8QM_MIPI1_DSI_PHY_DIV			798
+#define IMX8QM_MIPI1_DSI_PHY_CLK			799
+
+#define IMX8QM_CLK_END					800
+
+#endif /* __DT_BINDINGS_CLOCK_IMX8QM_H */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/imx8qxp-clock.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/imx8qxp-clock.h
new file mode 100644
index 0000000000000000000000000000000000000000..6316d5a717804c297207cd613cd19da110d01c76
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/imx8qxp-clock.h
@@ -0,0 +1,597 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017-2018 NXP
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_IMX8QXP_H
+#define __DT_BINDINGS_CLOCK_IMX8QXP_H
+
+#define IMX8QXP_CLK_DUMMY					0
+
+#define IMX8QXP_UART0_IPG_CLK					1
+#define IMX8QXP_UART0_DIV					2
+#define IMX8QXP_UART0_CLK					3
+
+#define IMX8QXP_IPG_DMA_CLK_ROOT				4
+
+/* GPU Clocks. */
+#define IMX8QXP_GPU0_CORE_DIV					5
+#define IMX8QXP_GPU0_CORE_CLK					6
+#define IMX8QXP_GPU0_SHADER_DIV					7
+#define IMX8QXP_GPU0_SHADER_CLK					8
+
+#define IMX8QXP_24MHZ						9
+#define IMX8QXP_GPT_3M						10
+#define IMX8QXP_32KHZ						11
+
+/* LSIO SS */
+#define IMX8QXP_LSIO_MEM_CLK					12
+#define IMX8QXP_LSIO_BUS_CLK					13
+#define IMX8QXP_LSIO_PWM0_DIV					14
+#define IMX8QXP_LSIO_PWM0_IPG_S_CLK				15
+#define IMX8QXP_LSIO_PWM0_IPG_SLV_CLK				16
+#define IMX8QXP_LSIO_PWM0_IPG_MSTR_CLK				17
+#define IMX8QXP_LSIO_PWM0_HF_CLK				18
+#define IMX8QXP_LSIO_PWM0_CLK					19
+#define IMX8QXP_LSIO_PWM1_DIV					20
+#define IMX8QXP_LSIO_PWM1_IPG_S_CLK				21
+#define IMX8QXP_LSIO_PWM1_IPG_SLV_CLK				22
+#define IMX8QXP_LSIO_PWM1_IPG_MSTR_CLK				23
+#define IMX8QXP_LSIO_PWM1_HF_CLK				24
+#define IMX8QXP_LSIO_PWM1_CLK					25
+#define IMX8QXP_LSIO_PWM2_DIV					26
+#define IMX8QXP_LSIO_PWM2_IPG_S_CLK				27
+#define IMX8QXP_LSIO_PWM2_IPG_SLV_CLK				28
+#define IMX8QXP_LSIO_PWM2_IPG_MSTR_CLK				29
+#define IMX8QXP_LSIO_PWM2_HF_CLK				30
+#define IMX8QXP_LSIO_PWM2_CLK					31
+#define IMX8QXP_LSIO_PWM3_DIV					32
+#define IMX8QXP_LSIO_PWM3_IPG_S_CLK				33
+#define IMX8QXP_LSIO_PWM3_IPG_SLV_CLK				34
+#define IMX8QXP_LSIO_PWM3_IPG_MSTR_CLK				35
+#define IMX8QXP_LSIO_PWM3_HF_CLK				36
+#define IMX8QXP_LSIO_PWM3_CLK					37
+#define IMX8QXP_LSIO_PWM4_DIV					38
+#define IMX8QXP_LSIO_PWM4_IPG_S_CLK				39
+#define IMX8QXP_LSIO_PWM4_IPG_SLV_CLK				40
+#define IMX8QXP_LSIO_PWM4_IPG_MSTR_CLK				42
+#define IMX8QXP_LSIO_PWM4_HF_CLK				43
+#define IMX8QXP_LSIO_PWM4_CLK					44
+#define IMX8QXP_LSIO_PWM5_DIV					45
+#define IMX8QXP_LSIO_PWM5_IPG_S_CLK				46
+#define IMX8QXP_LSIO_PWM5_IPG_SLV_CLK				47
+#define IMX8QXP_LSIO_PWM5_IPG_MSTR_CLK				48
+#define IMX8QXP_LSIO_PWM5_HF_CLK				49
+#define IMX8QXP_LSIO_PWM5_CLK					50
+#define IMX8QXP_LSIO_PWM6_DIV					51
+#define IMX8QXP_LSIO_PWM6_IPG_S_CLK				52
+#define IMX8QXP_LSIO_PWM6_IPG_SLV_CLK				53
+#define IMX8QXP_LSIO_PWM6_IPG_MSTR_CLK				54
+#define IMX8QXP_LSIO_PWM6_HF_CLK				55
+#define IMX8QXP_LSIO_PWM6_CLK					56
+#define IMX8QXP_LSIO_PWM7_DIV					57
+#define IMX8QXP_LSIO_PWM7_IPG_S_CLK				58
+#define IMX8QXP_LSIO_PWM7_IPG_SLV_CLK				59
+#define IMX8QXP_LSIO_PWM7_IPG_MSTR_CLK				60
+#define IMX8QXP_LSIO_PWM7_HF_CLK				61
+#define IMX8QXP_LSIO_PWM7_CLK					62
+#define IMX8QXP_LSIO_GPT0_DIV					63
+#define IMX8QXP_LSIO_GPT0_IPG_S_CLK				64
+#define IMX8QXP_LSIO_GPT0_IPG_SLV_CLK				65
+#define IMX8QXP_LSIO_GPT0_IPG_MSTR_CLK				66
+#define IMX8QXP_LSIO_GPT0_HF_CLK				67
+#define IMX8QXP_LSIO_GPT0_CLK					68
+#define IMX8QXP_LSIO_GPT1_DIV					69
+#define IMX8QXP_LSIO_GPT1_IPG_S_CLK				70
+#define IMX8QXP_LSIO_GPT1_IPG_SLV_CLK				71
+#define IMX8QXP_LSIO_GPT1_IPG_MSTR_CLK				72
+#define IMX8QXP_LSIO_GPT1_HF_CLK				73
+#define IMX8QXP_LSIO_GPT1_CLK					74
+#define IMX8QXP_LSIO_GPT2_DIV					75
+#define IMX8QXP_LSIO_GPT2_IPG_S_CLK				76
+#define IMX8QXP_LSIO_GPT2_IPG_SLV_CLK				77
+#define IMX8QXP_LSIO_GPT2_IPG_MSTR_CLK				78
+#define IMX8QXP_LSIO_GPT2_HF_CLK				79
+#define IMX8QXP_LSIO_GPT2_CLK					80
+#define IMX8QXP_LSIO_GPT3_DIV					81
+#define IMX8QXP_LSIO_GPT3_IPG_S_CLK				82
+#define IMX8QXP_LSIO_GPT3_IPG_SLV_CLK				83
+#define IMX8QXP_LSIO_GPT3_IPG_MSTR_CLK				84
+#define IMX8QXP_LSIO_GPT3_HF_CLK				85
+#define IMX8QXP_LSIO_GPT3_CLK					86
+#define IMX8QXP_LSIO_GPT4_DIV					87
+#define IMX8QXP_LSIO_GPT4_IPG_S_CLK				88
+#define IMX8QXP_LSIO_GPT4_IPG_SLV_CLK				89
+#define IMX8QXP_LSIO_GPT4_IPG_MSTR_CLK				90
+#define IMX8QXP_LSIO_GPT4_HF_CLK				91
+#define IMX8QXP_LSIO_GPT4_CLK					92
+#define IMX8QXP_LSIO_FSPI0_DIV					93
+#define IMX8QXP_LSIO_FSPI0_HCLK					94
+#define IMX8QXP_LSIO_FSPI0_IPG_S_CLK				95
+#define IMX8QXP_LSIO_FSPI0_IPG_CLK				96
+#define IMX8QXP_LSIO_FSPI0_CLK					97
+#define IMX8QXP_LSIO_FSPI1_DIV					98
+#define IMX8QXP_LSIO_FSPI1_HCLK					99
+#define IMX8QXP_LSIO_FSPI1_IPG_S_CLK				100
+#define IMX8QXP_LSIO_FSPI1_IPG_CLK				101
+#define IMX8QXP_LSIO_FSPI1_CLK					102
+#define IMX8QXP_LSIO_GPIO0_IPG_S_CLK				103
+#define IMX8QXP_LSIO_GPIO1_IPG_S_CLK				104
+#define IMX8QXP_LSIO_GPIO2_IPG_S_CLK				105
+#define IMX8QXP_LSIO_GPIO3_IPG_S_CLK				106
+#define IMX8QXP_LSIO_GPIO4_IPG_S_CLK				107
+#define IMX8QXP_LSIO_GPIO5_IPG_S_CLK				108
+#define IMX8QXP_LSIO_GPIO6_IPG_S_CLK				109
+#define IMX8QXP_LSIO_GPIO7_IPG_S_CLK				110
+#define IMX8QXP_LSIO_ROMCP_REG_CLK				111
+#define IMX8QXP_LSIO_ROMCP_CLK					112
+#define IMX8QXP_LSIO_96KROM_CLK					113
+#define IMX8QXP_LSIO_OCRAM_MEM_CLK				114
+#define IMX8QXP_LSIO_OCRAM_CTRL_CLK				115
+
+/* ADMA SS */
+#define IMX8QXP_UART1_IPG_CLK					116
+#define IMX8QXP_UART2_IPG_CLK					117
+#define IMX8QXP_UART3_IPG_CLK					118
+#define IMX8QXP_UART1_DIV					119
+#define IMX8QXP_UART2_DIV					120
+#define IMX8QXP_UART3_DIV					121
+#define IMX8QXP_UART1_CLK					122
+#define IMX8QXP_UART2_CLK					123
+#define IMX8QXP_UART3_CLK					124
+#define IMX8QXP_SPI0_IPG_CLK					125
+#define IMX8QXP_SPI1_IPG_CLK					126
+#define IMX8QXP_SPI2_IPG_CLK					127
+#define IMX8QXP_SPI3_IPG_CLK					128
+#define IMX8QXP_SPI0_DIV					129
+#define IMX8QXP_SPI1_DIV					130
+#define IMX8QXP_SPI2_DIV					131
+#define IMX8QXP_SPI3_DIV					132
+#define IMX8QXP_SPI0_CLK					133
+#define IMX8QXP_SPI1_CLK					134
+#define IMX8QXP_SPI2_CLK					135
+#define IMX8QXP_SPI3_CLK					136
+#define IMX8QXP_CAN0_IPG_CHI_CLK				137
+#define IMX8QXP_CAN1_IPG_CHI_CLK				138
+#define IMX8QXP_CAN2_IPG_CHI_CLK				139
+#define IMX8QXP_CAN0_IPG_CLK					140
+#define IMX8QXP_CAN1_IPG_CLK					141
+#define IMX8QXP_CAN2_IPG_CLK					142
+#define IMX8QXP_CAN0_DIV					143
+#define IMX8QXP_CAN1_DIV					144
+#define IMX8QXP_CAN2_DIV					145
+#define IMX8QXP_CAN0_CLK					146
+#define IMX8QXP_CAN1_CLK					147
+#define IMX8QXP_CAN2_CLK					148
+#define IMX8QXP_I2C0_IPG_CLK					149
+#define IMX8QXP_I2C1_IPG_CLK					150
+#define IMX8QXP_I2C2_IPG_CLK					151
+#define IMX8QXP_I2C3_IPG_CLK					152
+#define IMX8QXP_I2C0_DIV					153
+#define IMX8QXP_I2C1_DIV					154
+#define IMX8QXP_I2C2_DIV					155
+#define IMX8QXP_I2C3_DIV					156
+#define IMX8QXP_I2C0_CLK					157
+#define IMX8QXP_I2C1_CLK					158
+#define IMX8QXP_I2C2_CLK					159
+#define IMX8QXP_I2C3_CLK					160
+#define IMX8QXP_FTM0_IPG_CLK					161
+#define IMX8QXP_FTM1_IPG_CLK					162
+#define IMX8QXP_FTM0_DIV					163
+#define IMX8QXP_FTM1_DIV					164
+#define IMX8QXP_FTM0_CLK					165
+#define IMX8QXP_FTM1_CLK					166
+#define IMX8QXP_ADC0_IPG_CLK					167
+#define IMX8QXP_ADC0_DIV					168
+#define IMX8QXP_ADC0_CLK					169
+#define IMX8QXP_PWM_IPG_CLK					170
+#define IMX8QXP_PWM_DIV						171
+#define IMX8QXP_PWM_CLK						172
+#define IMX8QXP_LCD_IPG_CLK					173
+#define IMX8QXP_LCD_DIV						174
+#define IMX8QXP_LCD_CLK						175
+
+/* Connectivity SS */
+#define IMX8QXP_AXI_CONN_CLK_ROOT				176
+#define IMX8QXP_AHB_CONN_CLK_ROOT				177
+#define IMX8QXP_IPG_CONN_CLK_ROOT				178
+#define IMX8QXP_SDHC0_IPG_CLK					179
+#define IMX8QXP_SDHC1_IPG_CLK					180
+#define IMX8QXP_SDHC2_IPG_CLK					181
+#define IMX8QXP_SDHC0_DIV					182
+#define IMX8QXP_SDHC1_DIV					183
+#define IMX8QXP_SDHC2_DIV					184
+#define IMX8QXP_SDHC0_CLK					185
+#define IMX8QXP_SDHC1_CLK					186
+#define IMX8QXP_SDHC2_CLK					187
+#define IMX8QXP_ENET0_ROOT_DIV					188
+#define IMX8QXP_ENET0_REF_DIV					189
+#define IMX8QXP_ENET1_REF_DIV					190
+#define IMX8QXP_ENET0_BYPASS_DIV				191
+#define IMX8QXP_ENET0_RGMII_DIV					192
+#define IMX8QXP_ENET1_ROOT_DIV					193
+#define IMX8QXP_ENET1_BYPASS_DIV				194
+#define IMX8QXP_ENET1_RGMII_DIV					195
+#define IMX8QXP_ENET0_AHB_CLK					196
+#define IMX8QXP_ENET0_IPG_S_CLK					197
+#define IMX8QXP_ENET0_IPG_CLK					198
+#define IMX8QXP_ENET1_AHB_CLK					199
+#define IMX8QXP_ENET1_IPG_S_CLK					200
+#define IMX8QXP_ENET1_IPG_CLK					201
+#define IMX8QXP_ENET0_ROOT_CLK					202
+#define IMX8QXP_ENET1_ROOT_CLK					203
+#define IMX8QXP_ENET0_TX_CLK					204
+#define IMX8QXP_ENET1_TX_CLK					205
+#define IMX8QXP_ENET0_PTP_CLK					206
+#define IMX8QXP_ENET1_PTP_CLK					207
+#define IMX8QXP_ENET0_REF_25MHZ_125MHZ_SEL			208
+#define IMX8QXP_ENET1_REF_25MHZ_125MHZ_SEL			209
+#define IMX8QXP_ENET0_RMII_TX_SEL				210
+#define IMX8QXP_ENET1_RMII_TX_SEL				211
+#define IMX8QXP_ENET0_RGMII_TX_CLK				212
+#define IMX8QXP_ENET1_RGMII_TX_CLK				213
+#define IMX8QXP_ENET0_RMII_RX_CLK				214
+#define IMX8QXP_ENET1_RMII_RX_CLK				215
+#define IMX8QXP_ENET0_REF_25MHZ_125MHZ_CLK			216
+#define IMX8QXP_ENET1_REF_25MHZ_125MHZ_CLK			217
+#define IMX8QXP_ENET0_REF_50MHZ_CLK				218
+#define IMX8QXP_ENET1_REF_50MHZ_CLK				219
+#define IMX8QXP_GPMI_BCH_IO_DIV					220
+#define IMX8QXP_GPMI_BCH_DIV					221
+#define IMX8QXP_GPMI_APB_CLK					222
+#define IMX8QXP_GPMI_APB_BCH_CLK				223
+#define IMX8QXP_GPMI_BCH_IO_CLK					224
+#define IMX8QXP_GPMI_BCH_CLK					225
+#define IMX8QXP_APBHDMA_CLK					226
+#define IMX8QXP_USB3_ACLK_DIV					227
+#define IMX8QXP_USB3_BUS_DIV					228
+#define IMX8QXP_USB3_LPM_DIV					229
+#define IMX8QXP_USB3_IPG_CLK					230
+#define IMX8QXP_USB3_CORE_PCLK					231
+#define IMX8QXP_USB3_PHY_CLK					232
+#define IMX8QXP_USB3_ACLK					233
+#define IMX8QXP_USB3_BUS_CLK					234
+#define IMX8QXP_USB3_LPM_CLK					235
+#define IMX8QXP_USB2_OH_AHB_CLK					236
+#define IMX8QXP_USB2_OH_IPG_S_CLK				237
+#define IMX8QXP_USB2_OH_IPG_S_PL301_CLK				238
+#define IMX8QXP_USB2_PHY_IPG_CLK				239
+#define IMX8QXP_EDMA_CLK					240
+#define IMX8QXP_EDMA_IPG_CLK					241
+#define IMX8QXP_MLB_HCLK					242
+#define IMX8QXP_MLB_CLK						243
+#define IMX8QXP_MLB_IPG_CLK					244
+
+/* Display controller SS */
+/* DC part1 */
+#define IMX8QXP_DC_AXI_EXT_CLK					245
+#define IMX8QXP_DC_AXI_INT_CLK					246
+#define IMX8QXP_DC_CFG_CLK					247
+#define IMX8QXP_DC0_DISP0_CLK					248
+#define IMX8QXP_DC0_DISP1_CLK					249
+#define IMX8QXP_DC0_PRG0_RTRAM_CLK				250
+#define IMX8QXP_DC0_PRG0_APB_CLK				251
+#define IMX8QXP_DC0_PRG1_RTRAM_CLK				252
+#define IMX8QXP_DC0_PRG1_APB_CLK				253
+#define IMX8QXP_DC0_PRG2_RTRAM_CLK				254
+#define IMX8QXP_DC0_PRG2_APB_CLK				255
+#define IMX8QXP_DC0_PRG3_RTRAM_CLK				256
+#define IMX8QXP_DC0_PRG3_APB_CLK				257
+#define IMX8QXP_DC0_PRG4_RTRAM_CLK				258
+#define IMX8QXP_DC0_PRG4_APB_CLK				259
+#define IMX8QXP_DC0_PRG5_RTRAM_CLK				260
+#define IMX8QXP_DC0_PRG5_APB_CLK				261
+#define IMX8QXP_DC0_PRG6_RTRAM_CLK				262
+#define IMX8QXP_DC0_PRG6_APB_CLK				263
+#define IMX8QXP_DC0_PRG7_RTRAM_CLK				264
+#define IMX8QXP_DC0_PRG7_APB_CLK				265
+#define IMX8QXP_DC0_PRG8_RTRAM_CLK				266
+#define IMX8QXP_DC0_PRG8_APB_CLK				267
+#define IMX8QXP_DC0_DPR0_APB_CLK				268
+#define IMX8QXP_DC0_DPR0_B_CLK					269
+#define IMX8QXP_DC0_RTRAM0_CLK					270
+#define IMX8QXP_DC0_RTRAM1_CLK					271
+
+/* MIPI-LVDS part1 */
+#define IMX8QXP_MIPI_IPG_CLK					272
+#define IMX8QXP_MIPI0_I2C0_DIV					273
+#define IMX8QXP_MIPI0_I2C1_DIV					274
+#define IMX8QXP_MIPI0_I2C0_CLK					275
+#define IMX8QXP_MIPI0_I2C1_CLK					276
+#define IMX8QXP_MIPI0_I2C0_IPG_CLK				278
+#define IMX8QXP_MIPI0_I2C1_IPG_CLK				280
+#define IMX8QXP_MIPI0_PWM_IPG_CLK				282
+#define IMX8QXP_MIPI0_PWM_32K_CLK				283
+#define IMX8QXP_MIPI0_GPIO_IPG_CLK				284
+
+#define IMX8QXP_IMG_JPEG_ENC_IPG_CLK				285
+#define IMX8QXP_IMG_JPEG_ENC_CLK				286
+#define IMX8QXP_IMG_JPEG_DEC_IPG_CLK				287
+#define IMX8QXP_IMG_JPEG_DEC_CLK				288
+#define IMX8QXP_IMG_PXL_LINK_DC0_CLK				289
+#define IMX8QXP_IMG_PXL_LINK_DC1_CLK				290
+#define IMX8QXP_IMG_PXL_LINK_CSI0_CLK				291
+#define IMX8QXP_IMG_PXL_LINK_CSI1_CLK				292
+#define IMX8QXP_IMG_PXL_LINK_HDMI_IN_CLK			293
+#define IMX8QXP_IMG_PDMA_0_CLK					294
+#define IMX8QXP_IMG_PDMA_1_CLK					295
+#define IMX8QXP_IMG_PDMA_2_CLK					296
+#define IMX8QXP_IMG_PDMA_3_CLK					297
+#define IMX8QXP_IMG_PDMA_4_CLK					298
+#define IMX8QXP_IMG_PDMA_5_CLK					299
+#define IMX8QXP_IMG_PDMA_6_CLK					300
+#define IMX8QXP_IMG_PDMA_7_CLK					301
+#define IMX8QXP_IMG_AXI_CLK					302
+#define IMX8QXP_IMG_IPG_CLK					303
+#define IMX8QXP_IMG_PXL_CLK					304
+
+#define IMX8QXP_CSI0_I2C0_DIV					305
+#define IMX8QXP_CSI0_PWM0_DIV					306
+#define IMX8QXP_CSI0_CORE_DIV					307
+#define IMX8QXP_CSI0_ESC_DIV					308
+#define IMX8QXP_CSI0_IPG_CLK_S					309
+#define IMX8QXP_CSI0_IPG_CLK					310
+#define IMX8QXP_CSI0_APB_CLK					311
+#define IMX8QXP_CSI0_I2C0_IPG_CLK				312
+#define IMX8QXP_CSI0_I2C0_CLK					313
+#define IMX8QXP_CSI0_PWM0_IPG_CLK				314
+#define IMX8QXP_CSI0_PWM0_CLK					315
+#define IMX8QXP_CSI0_CORE_CLK					316
+#define IMX8QXP_CSI0_ESC_CLK					317
+
+#define IMX8QXP_HSIO_AXI_CLK					318
+#define IMX8QXP_HSIO_PER_CLK					319
+#define IMX8QXP_HSIO_PCIE_MSTR_AXI_CLK				320
+#define IMX8QXP_HSIO_PCIE_SLV_AXI_CLK				321
+#define IMX8QXP_HSIO_PCIE_DBI_AXI_CLK				322
+#define IMX8QXP_HSIO_PCIE_X1_PER_CLK				323
+#define IMX8QXP_HSIO_PHY_X1_PER_CLK				324
+#define IMX8QXP_HSIO_MISC_PER_CLK				325
+#define IMX8QXP_HSIO_PHY_X1_APB_CLK				326
+#define IMX8QXP_HSIO_GPIO_CLK					327
+#define IMX8QXP_HSIO_PHY_X1_PCLK				328
+
+#define IMX8QXP_A35_DIV						329
+
+/* ACM */
+#define IMX8QXP_EXT_AUD_MCLK0					330
+#define IMX8QXP_EXT_AUD_MCLK1					331
+#define IMX8QXP_ESAI0_RX_CLK					332
+#define IMX8QXP_ESAI0_RX_HF_CLK					333
+#define IMX8QXP_ESAI0_TX_CLK					334
+#define IMX8QXP_ESAI0_TX_HF_CLK					335
+#define IMX8QXP_SPDIF0_RX					336
+#define IMX8QXP_SAI0_RX_BCLK					337
+#define IMX8QXP_SAI0_TX_BCLK					338
+#define IMX8QXP_SAI1_RX_BCLK					339
+#define IMX8QXP_SAI1_TX_BCLK					340
+#define IMX8QXP_SAI2_RX_BCLK					341
+#define IMX8QXP_SAI3_RX_BCLK					342
+#define IMX8QXP_SAI4_RX_BCLK					343
+
+#define IMX8QXP_ACM_AUD_CLK0_SEL				344
+#define IMX8QXP_ACM_AUD_CLK0_CLK				345
+#define IMX8QXP_ACM_AUD_CLK1_SEL				346
+#define IMX8QXP_ACM_AUD_CLK1_CLK				347
+#define IMX8QXP_ACM_MCLKOUT0_SEL				348
+#define IMX8QXP_ACM_MCLKOUT0_CLK				349
+#define IMX8QXP_ACM_MCLKOUT1_SEL				350
+#define IMX8QXP_ACM_MCLKOUT1_CLK				351
+#define IMX8QXP_ACM_ESAI0_MCLK_SEL				352
+#define IMX8QXP_ACM_ESAI0_MCLK_CLK				353
+#define IMX8QXP_ACM_GPT0_MUX_CLK_SEL				354
+#define IMX8QXP_ACM_GPT0_MUX_CLK_CLK				355
+#define IMX8QXP_ACM_GPT1_MUX_CLK_SEL				356
+#define IMX8QXP_ACM_GPT1_MUX_CLK_CLK				357
+#define IMX8QXP_ACM_GPT2_MUX_CLK_SEL				358
+#define IMX8QXP_ACM_GPT2_MUX_CLK_CLK				359
+#define IMX8QXP_ACM_GPT3_MUX_CLK_SEL				360
+#define IMX8QXP_ACM_GPT3_MUX_CLK_CLK				361
+#define IMX8QXP_ACM_GPT4_MUX_CLK_SEL				362
+#define IMX8QXP_ACM_GPT4_MUX_CLK_CLK				363
+#define IMX8QXP_ACM_GPT5_MUX_CLK_SEL				364
+#define IMX8QXP_ACM_GPT5_MUX_CLK_CLK				365
+#define IMX8QXP_ACM_SAI0_MCLK_SEL				366
+#define IMX8QXP_ACM_SAI0_MCLK_CLK				367
+#define IMX8QXP_ACM_SAI1_MCLK_SEL				368
+#define IMX8QXP_ACM_SAI1_MCLK_CLK				369
+#define IMX8QXP_ACM_SAI2_MCLK_SEL				370
+#define IMX8QXP_ACM_SAI2_MCLK_CLK				371
+#define IMX8QXP_ACM_SAI3_MCLK_SEL				372
+#define IMX8QXP_ACM_SAI3_MCLK_CLK				373
+#define IMX8QXP_ACM_SAI4_MCLK_SEL				374
+#define IMX8QXP_ACM_SAI4_MCLK_CLK				375
+#define IMX8QXP_ACM_SAI5_MCLK_SEL				376
+#define IMX8QXP_ACM_SAI5_MCLK_CLK				377
+#define IMX8QXP_ACM_SPDIF0_TX_CLK_SEL				378
+#define IMX8QXP_ACM_SPDIF0_TX_CLK_CLK				379
+#define IMX8QXP_ACM_MQS_TX_CLK_SEL				380
+#define IMX8QXP_ACM_MQS_TX_CLK_CLK				381
+#define IMX8QXP_ACM_ASRC0_MUX_CLK_SEL				382
+#define IMX8QXP_ACM_ASRC1_MUX_CLK_SEL				383
+#define IMX8QXP_ACM_ASRC0_MUX_CLK_CLK				384
+#define IMX8QXP_ACM_ASRC1_MUX_CLK_CLK				385
+
+#define IMX8QXP_IPG_AUD_CLK_ROOT				386
+
+/* Audio */
+#define IMX8QXP_AUD_PLL0_DIV					387
+#define IMX8QXP_AUD_PLL0					388
+#define IMX8QXP_AUD_PLL1_DIV					389
+#define IMX8QXP_AUD_PLL1					390
+#define IMX8QXP_AUD_AMIX_IPG					391
+#define IMX8QXP_AUD_ESAI_0_IPG					392
+#define IMX8QXP_AUD_ESAI_0_EXTAL_IPG				393
+#define IMX8QXP_AUD_SAI_0_IPG					394
+#define IMX8QXP_AUD_SAI_0_MCLK					395
+#define IMX8QXP_AUD_SAI_1_IPG					396
+#define IMX8QXP_AUD_SAI_1_MCLK					397
+#define IMX8QXP_AUD_SAI_2_IPG					398
+#define IMX8QXP_AUD_SAI_2_MCLK					399
+#define IMX8QXP_AUD_SAI_3_IPG					400
+#define IMX8QXP_AUD_SAI_3_MCLK					401
+#define IMX8QXP_AUD_SAI_4_IPG					402
+#define IMX8QXP_AUD_SAI_4_MCLK					403
+#define IMX8QXP_AUD_SAI_5_IPG					404
+#define IMX8QXP_AUD_SAI_5_MCLK					405
+#define IMX8QXP_AUD_MQS_IPG					406
+#define IMX8QXP_AUD_MQS_HMCLK					407
+#define IMX8QXP_AUD_GPT5_IPG					408
+#define IMX8QXP_AUD_GPT5_CLKIN					409
+#define IMX8QXP_AUD_GPT6_IPG					410
+#define IMX8QXP_AUD_GPT6_CLKIN					411
+#define IMX8QXP_AUD_GPT7_IPG					412
+#define IMX8QXP_AUD_GPT7_CLKIN					413
+#define IMX8QXP_AUD_GPT8_IPG					414
+#define IMX8QXP_AUD_GPT8_CLKIN					415
+#define IMX8QXP_AUD_GPT9_IPG					416
+#define IMX8QXP_AUD_GPT9_CLKIN					417
+#define IMX8QXP_AUD_GPT10_IPG					418
+#define IMX8QXP_AUD_GPT10_CLKIN					419
+#define IMX8QXP_AUD_ACM_AUD_PLL_CLK0_DIV			420
+#define IMX8QXP_AUD_ACM_AUD_PLL_CLK0_CLK			421
+#define IMX8QXP_AUD_ACM_AUD_PLL_CLK1_DIV			422
+#define IMX8QXP_AUD_ACM_AUD_PLL_CLK1_CLK			423
+#define IMX8QXP_AUD_ACM_AUD_REC_CLK0_DIV			424
+#define IMX8QXP_AUD_ACM_AUD_REC_CLK0_CLK			425
+#define IMX8QXP_AUD_ACM_AUD_REC_CLK1_DIV			426
+#define IMX8QXP_AUD_ACM_AUD_REC_CLK1_CLK			427
+#define IMX8QXP_AUD_MCLKOUT0					428
+#define IMX8QXP_AUD_MCLKOUT1					429
+#define IMX8QXP_AUD_SPDIF_0_TX_CLK				430
+#define IMX8QXP_AUD_SPDIF_0_GCLKW				431
+#define IMX8QXP_AUD_SPDIF_0_IPG					432
+#define IMX8QXP_AUD_ASRC_0_IPG					433
+#define IMX8QXP_AUD_ASRC_1_IPG					434
+#define IMX8QXP_AUD_DSP_ADB_ACLK				435
+#define IMX8QXP_AUD_DSP_IPG				        436
+#define IMX8QXP_AUD_DSP_CORE_CLK				437
+#define IMX8QXP_AUD_OCRAM_IPG					438
+
+/* DC part2 */
+#define IMX8QXP_DC0_DISP0_DIV					439
+#define IMX8QXP_DC0_DISP1_DIV					440
+#define IMX8QXP_DC0_BYPASS_0_DIV				441
+#define IMX8QXP_DC0_BYPASS_1_DIV				442
+#define IMX8QXP_DC0_PLL0_DIV					443
+#define IMX8QXP_DC0_PLL1_DIV					444
+#define IMX8QXP_DC0_PLL0_CLK					445
+#define IMX8QXP_DC0_PLL1_CLK					446
+
+/* MIPI-LVDS part2 */
+#define IMX8QXP_MIPI0_BYPASS_CLK				447
+#define IMX8QXP_MIPI0_PIXEL_DIV					448
+#define IMX8QXP_MIPI0_PIXEL_CLK					449
+#define IMX8QXP_MIPI0_LVDS_PIXEL_DIV				450
+#define IMX8QXP_MIPI0_LVDS_PIXEL_CLK				451
+#define IMX8QXP_MIPI0_LVDS_BYPASS_CLK				452
+#define IMX8QXP_MIPI0_LVDS_PHY_DIV				453
+#define IMX8QXP_MIPI0_LVDS_PHY_CLK				454
+#define IMX8QXP_MIPI0_DSI_TX_ESC_DIV				455
+#define IMX8QXP_MIPI0_DSI_RX_ESC_DIV				456
+#define IMX8QXP_MIPI0_DSI_TX_ESC_CLK				457
+#define IMX8QXP_MIPI0_DSI_RX_ESC_CLK				458
+#define IMX8QXP_MIPI0_LIS_IPG_CLK				459
+#define IMX8QXP_MIPI1_I2C0_DIV					460
+#define IMX8QXP_MIPI1_I2C1_DIV					461
+#define IMX8QXP_MIPI1_I2C0_CLK					462
+#define IMX8QXP_MIPI1_I2C1_CLK					463
+#define IMX8QXP_MIPI1_I2C0_IPG_CLK				465
+#define IMX8QXP_MIPI1_I2C1_IPG_CLK				467
+#define IMX8QXP_MIPI1_PWM_IPG_CLK				469
+#define IMX8QXP_MIPI1_PWM_32K_CLK				470
+#define IMX8QXP_MIPI1_GPIO_IPG_CLK				471
+#define IMX8QXP_MIPI1_BYPASS_CLK				472
+#define IMX8QXP_MIPI1_PIXEL_DIV					473
+#define IMX8QXP_MIPI1_PIXEL_CLK					474
+#define IMX8QXP_MIPI1_LVDS_PIXEL_DIV				475
+#define IMX8QXP_MIPI1_LVDS_PIXEL_CLK				476
+#define IMX8QXP_MIPI1_LVDS_BYPASS_CLK				477
+#define IMX8QXP_MIPI1_LVDS_PHY_DIV				478
+#define IMX8QXP_MIPI1_LVDS_PHY_CLK				479
+#define IMX8QXP_MIPI1_DSI_TX_ESC_DIV				480
+#define IMX8QXP_MIPI1_DSI_RX_ESC_DIV				481
+#define IMX8QXP_MIPI1_DSI_TX_ESC_CLK				482
+#define IMX8QXP_MIPI1_DSI_RX_ESC_CLK				483
+
+#define IMX8QXP_MIPI1_LIS_IPG_CLK				484
+
+/* CM40 */
+#define IMX8QXP_CM40_IPG_CLK					485
+#define IMX8QXP_CM40_I2C_DIV					486
+#define IMX8QXP_CM40_I2C_CLK					487
+#define IMX8QXP_CM40_I2C_IPG_CLK				488
+
+/* VPU clocks. */
+#define IMX8QXP_VPU_ENC_CLK					489
+#define IMX8QXP_VPU_DEC_CLK					490
+
+/* MIPI-LVDS part3 */
+#define IMX8QXP_MIPI0_DSI_PLL_CLK				491
+#define IMX8QXP_MIPI0_DSI_PLL_DIV2_CLK				492
+#define IMX8QXP_MIPI0_LVDS_PIXEL_SEL				493
+#define IMX8QXP_MIPI0_LVDS_PHY_SEL				494
+#define IMX8QXP_MIPI0_DSI_TX_ESC_SEL				495
+#define IMX8QXP_MIPI0_DSI_RX_ESC_SEL				496
+#define IMX8QXP_MIPI0_DSI_PHY_SEL				498
+#define IMX8QXP_MIPI0_DSI_PHY_DIV				499
+#define IMX8QXP_MIPI0_DSI_PHY_CLK				500
+#define IMX8QXP_MIPI1_DSI_PLL_CLK				501
+#define IMX8QXP_MIPI1_DSI_PLL_DIV2_CLK				502
+#define IMX8QXP_MIPI1_LVDS_PIXEL_SEL				503
+#define IMX8QXP_MIPI1_LVDS_PHY_SEL				504
+#define IMX8QXP_MIPI1_DSI_TX_ESC_SEL				505
+#define IMX8QXP_MIPI1_DSI_RX_ESC_SEL				506
+#define IMX8QXP_MIPI1_DSI_PHY_SEL				507
+#define IMX8QXP_MIPI1_DSI_PHY_DIV				508
+#define IMX8QXP_MIPI1_DSI_PHY_CLK				509
+
+/* DC part3 */
+#define IMX8QXP_DC0_DPR1_APB_CLK				510
+#define IMX8QXP_DC0_DPR1_B_CLK					511
+
+#define	IMX8QXP_CONN_PLL0_CLK					512
+#define	IMX8QXP_CONN_PLL1_CLK					513
+#define IMX8QXP_SDHC0_SEL					514
+#define IMX8QXP_SDHC1_SEL					515
+#define IMX8QXP_SDHC2_SEL					516
+
+/* PARALLER CSI */
+#define IMX8QXP_PARALLEL_CSI_CLK_DPLL		517
+#define IMX8QXP_PARALLEL_CSI_CLK_SEL		518
+#define IMX8QXP_PARALLEL_CSI_PER_CLK_DIV	519
+#define IMX8QXP_PARALLEL_CSI_PIXEL_CLK		520
+#define IMX8QXP_PARALLEL_CSI_IPG_CLK		521
+#define IMX8QXP_PARALLEL_CSI_MCLK_DIV		522
+#define IMX8QXP_PARALLEL_CSI_MISC0_CLK		523
+
+#define IMX8QXP_MIPI0_PWM_DIV					524
+#define IMX8QXP_MIPI1_PWM_DIV					525
+#define IMX8QXP_MIPI0_PWM_CLK					526
+#define IMX8QXP_MIPI1_PWM_CLK					527
+
+#define IMX8QXP_LSIO_MU5A_IPG_S_CLK		528
+#define IMX8QXP_LSIO_MU5A_IPG_CLK		529
+
+
+/* LCD part2 */
+#define IMX8QXP_LCD_PXL_BYPASS_DIV			530
+#define IMX8QXP_LCD_PXL_SEL				531
+#define IMX8QXP_LCD_PXL_DIV				532
+#define IMX8QXP_LCD_PXL_CLK				533
+#define IMX8QXP_ELCDIF_PLL_DIV				534
+#define IMX8QXP_ELCDIF_PLL				535
+#define IMX8QXP_LCD_SEL					536
+
+#define IMX8QXP_CLK_END					537
+#endif /* __DT_BINDINGS_CLOCK_IMX8QXP_H */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/jz4740-cgu.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/jz4740-cgu.h
new file mode 100644
index 0000000000000000000000000000000000000000..6ed83f926ae71608e44e469b9fb8fb26ba006577
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/jz4740-cgu.h
@@ -0,0 +1,38 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * This header provides clock numbers for the ingenic,jz4740-cgu DT binding.
+ *
+ * They are roughly ordered as:
+ *   - external clocks
+ *   - PLLs
+ *   - muxes/dividers in the order they appear in the jz4740 programmers manual
+ *   - gates in order of their bit in the CLKGR* registers
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_JZ4740_CGU_H__
+#define __DT_BINDINGS_CLOCK_JZ4740_CGU_H__
+
+#define JZ4740_CLK_EXT		0
+#define JZ4740_CLK_RTC		1
+#define JZ4740_CLK_PLL		2
+#define JZ4740_CLK_PLL_HALF	3
+#define JZ4740_CLK_CCLK		4
+#define JZ4740_CLK_HCLK		5
+#define JZ4740_CLK_PCLK		6
+#define JZ4740_CLK_MCLK		7
+#define JZ4740_CLK_LCD		8
+#define JZ4740_CLK_LCD_PCLK	9
+#define JZ4740_CLK_I2S		10
+#define JZ4740_CLK_SPI		11
+#define JZ4740_CLK_MMC		12
+#define JZ4740_CLK_UHC		13
+#define JZ4740_CLK_UDC		14
+#define JZ4740_CLK_UART0	15
+#define JZ4740_CLK_UART1	16
+#define JZ4740_CLK_DMA		17
+#define JZ4740_CLK_IPU		18
+#define JZ4740_CLK_ADC		19
+#define JZ4740_CLK_I2C		20
+#define JZ4740_CLK_AIC		21
+
+#endif /* __DT_BINDINGS_CLOCK_JZ4740_CGU_H__ */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/jz4770-cgu.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/jz4770-cgu.h
new file mode 100644
index 0000000000000000000000000000000000000000..d68a7695a1f89fa8a1d4edccd79a44ad8d4b3b9d
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/jz4770-cgu.h
@@ -0,0 +1,58 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * This header provides clock numbers for the ingenic,jz4770-cgu DT binding.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_JZ4770_CGU_H__
+#define __DT_BINDINGS_CLOCK_JZ4770_CGU_H__
+
+#define JZ4770_CLK_EXT		0
+#define JZ4770_CLK_OSC32K	1
+#define JZ4770_CLK_PLL0		2
+#define JZ4770_CLK_PLL1		3
+#define JZ4770_CLK_CCLK		4
+#define JZ4770_CLK_H0CLK	5
+#define JZ4770_CLK_H1CLK	6
+#define JZ4770_CLK_H2CLK	7
+#define JZ4770_CLK_C1CLK	8
+#define JZ4770_CLK_PCLK		9
+#define JZ4770_CLK_MMC0_MUX	10
+#define JZ4770_CLK_MMC0		11
+#define JZ4770_CLK_MMC1_MUX	12
+#define JZ4770_CLK_MMC1		13
+#define JZ4770_CLK_MMC2_MUX	14
+#define JZ4770_CLK_MMC2		15
+#define JZ4770_CLK_CIM		16
+#define JZ4770_CLK_UHC		17
+#define JZ4770_CLK_GPU		18
+#define JZ4770_CLK_BCH		19
+#define JZ4770_CLK_LPCLK_MUX	20
+#define JZ4770_CLK_GPS		21
+#define JZ4770_CLK_SSI_MUX	22
+#define JZ4770_CLK_PCM_MUX	23
+#define JZ4770_CLK_I2S		24
+#define JZ4770_CLK_OTG		25
+#define JZ4770_CLK_SSI0		26
+#define JZ4770_CLK_SSI1		27
+#define JZ4770_CLK_SSI2		28
+#define JZ4770_CLK_PCM0		29
+#define JZ4770_CLK_PCM1		30
+#define JZ4770_CLK_DMA		31
+#define JZ4770_CLK_I2C0		32
+#define JZ4770_CLK_I2C1		33
+#define JZ4770_CLK_I2C2		34
+#define JZ4770_CLK_UART0	35
+#define JZ4770_CLK_UART1	36
+#define JZ4770_CLK_UART2	37
+#define JZ4770_CLK_UART3	38
+#define JZ4770_CLK_IPU		39
+#define JZ4770_CLK_ADC		40
+#define JZ4770_CLK_AIC		41
+#define JZ4770_CLK_AUX		42
+#define JZ4770_CLK_VPU		43
+#define JZ4770_CLK_UHC_PHY	44
+#define JZ4770_CLK_OTG_PHY	45
+#define JZ4770_CLK_EXT512	46
+#define JZ4770_CLK_RTC		47
+
+#endif /* __DT_BINDINGS_CLOCK_JZ4770_CGU_H__ */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/jz4780-cgu.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/jz4780-cgu.h
new file mode 100644
index 0000000000000000000000000000000000000000..1859ce53ee388d4e21f82950cb9e072959737a47
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/jz4780-cgu.h
@@ -0,0 +1,89 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * This header provides clock numbers for the ingenic,jz4780-cgu DT binding.
+ *
+ * They are roughly ordered as:
+ *   - external clocks
+ *   - PLLs
+ *   - muxes/dividers in the order they appear in the jz4780 programmers manual
+ *   - gates in order of their bit in the CLKGR* registers
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_JZ4780_CGU_H__
+#define __DT_BINDINGS_CLOCK_JZ4780_CGU_H__
+
+#define JZ4780_CLK_EXCLK	0
+#define JZ4780_CLK_RTCLK	1
+#define JZ4780_CLK_APLL		2
+#define JZ4780_CLK_MPLL		3
+#define JZ4780_CLK_EPLL		4
+#define JZ4780_CLK_VPLL		5
+#define JZ4780_CLK_OTGPHY	6
+#define JZ4780_CLK_SCLKA	7
+#define JZ4780_CLK_CPUMUX	8
+#define JZ4780_CLK_CPU		9
+#define JZ4780_CLK_L2CACHE	10
+#define JZ4780_CLK_AHB0		11
+#define JZ4780_CLK_AHB2PMUX	12
+#define JZ4780_CLK_AHB2		13
+#define JZ4780_CLK_PCLK		14
+#define JZ4780_CLK_DDR		15
+#define JZ4780_CLK_VPU		16
+#define JZ4780_CLK_I2SPLL	17
+#define JZ4780_CLK_I2S		18
+#define JZ4780_CLK_LCD0PIXCLK	19
+#define JZ4780_CLK_LCD1PIXCLK	20
+#define JZ4780_CLK_MSCMUX	21
+#define JZ4780_CLK_MSC0		22
+#define JZ4780_CLK_MSC1		23
+#define JZ4780_CLK_MSC2		24
+#define JZ4780_CLK_UHC		25
+#define JZ4780_CLK_SSIPLL	26
+#define JZ4780_CLK_SSI		27
+#define JZ4780_CLK_CIMMCLK	28
+#define JZ4780_CLK_PCMPLL	29
+#define JZ4780_CLK_PCM		30
+#define JZ4780_CLK_GPU		31
+#define JZ4780_CLK_HDMI		32
+#define JZ4780_CLK_BCH		33
+#define JZ4780_CLK_NEMC		34
+#define JZ4780_CLK_OTG0		35
+#define JZ4780_CLK_SSI0		36
+#define JZ4780_CLK_SMB0		37
+#define JZ4780_CLK_SMB1		38
+#define JZ4780_CLK_SCC		39
+#define JZ4780_CLK_AIC		40
+#define JZ4780_CLK_TSSI0	41
+#define JZ4780_CLK_OWI		42
+#define JZ4780_CLK_KBC		43
+#define JZ4780_CLK_SADC		44
+#define JZ4780_CLK_UART0	45
+#define JZ4780_CLK_UART1	46
+#define JZ4780_CLK_UART2	47
+#define JZ4780_CLK_UART3	48
+#define JZ4780_CLK_SSI1		49
+#define JZ4780_CLK_SSI2		50
+#define JZ4780_CLK_PDMA		51
+#define JZ4780_CLK_GPS		52
+#define JZ4780_CLK_MAC		53
+#define JZ4780_CLK_SMB2		54
+#define JZ4780_CLK_CIM		55
+#define JZ4780_CLK_LCD		56
+#define JZ4780_CLK_TVE		57
+#define JZ4780_CLK_IPU		58
+#define JZ4780_CLK_DDR0		59
+#define JZ4780_CLK_DDR1		60
+#define JZ4780_CLK_SMB3		61
+#define JZ4780_CLK_TSSI1	62
+#define JZ4780_CLK_COMPRESS	63
+#define JZ4780_CLK_AIC1		64
+#define JZ4780_CLK_GPVLC	65
+#define JZ4780_CLK_OTG1		66
+#define JZ4780_CLK_UART4	67
+#define JZ4780_CLK_AHBMON	68
+#define JZ4780_CLK_SMB4		69
+#define JZ4780_CLK_DES		70
+#define JZ4780_CLK_X2D		71
+#define JZ4780_CLK_CORE1	72
+
+#endif /* __DT_BINDINGS_CLOCK_JZ4780_CGU_H__ */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/lpc18xx-ccu.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/lpc18xx-ccu.h
new file mode 100644
index 0000000000000000000000000000000000000000..bbfe00b6ab7d584393d75e040fe76e879cb0b78a
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/lpc18xx-ccu.h
@@ -0,0 +1,74 @@
+/*
+ * Copyright (c) 2015 Joachim Eastwood <manabian@gmail.com>
+ *
+ * This code is released using a dual license strategy: BSD/GPL
+ * You can choose the licence that better fits your requirements.
+ *
+ * Released under the terms of 3-clause BSD License
+ * Released under the terms of GNU General Public License Version 2.0
+ *
+ */
+
+/* Clock Control Unit 1 (CCU1) clock offsets */
+#define CLK_APB3_BUS		0x100
+#define CLK_APB3_I2C1		0x108
+#define CLK_APB3_DAC		0x110
+#define CLK_APB3_ADC0		0x118
+#define CLK_APB3_ADC1		0x120
+#define CLK_APB3_CAN0		0x128
+#define CLK_APB1_BUS		0x200
+#define CLK_APB1_MOTOCON_PWM	0x208
+#define CLK_APB1_I2C0		0x210
+#define CLK_APB1_I2S		0x218
+#define CLK_APB1_CAN1		0x220
+#define CLK_SPIFI		0x300
+#define CLK_CPU_BUS		0x400
+#define CLK_CPU_SPIFI		0x408
+#define CLK_CPU_GPIO		0x410
+#define CLK_CPU_LCD		0x418
+#define CLK_CPU_ETHERNET	0x420
+#define CLK_CPU_USB0		0x428
+#define CLK_CPU_EMC		0x430
+#define CLK_CPU_SDIO		0x438
+#define CLK_CPU_DMA		0x440
+#define CLK_CPU_CORE		0x448
+#define CLK_CPU_SCT		0x468
+#define CLK_CPU_USB1		0x470
+#define CLK_CPU_EMCDIV		0x478
+#define CLK_CPU_FLASHA		0x480
+#define CLK_CPU_FLASHB		0x488
+#define CLK_CPU_M0APP		0x490
+#define CLK_CPU_ADCHS		0x498
+#define CLK_CPU_EEPROM		0x4a0
+#define CLK_CPU_WWDT		0x500
+#define CLK_CPU_UART0		0x508
+#define CLK_CPU_UART1		0x510
+#define CLK_CPU_SSP0		0x518
+#define CLK_CPU_TIMER0		0x520
+#define CLK_CPU_TIMER1		0x528
+#define CLK_CPU_SCU		0x530
+#define CLK_CPU_CREG		0x538
+#define CLK_CPU_RITIMER		0x600
+#define CLK_CPU_UART2		0x608
+#define CLK_CPU_UART3		0x610
+#define CLK_CPU_TIMER2		0x618
+#define CLK_CPU_TIMER3		0x620
+#define CLK_CPU_SSP1		0x628
+#define CLK_CPU_QEI		0x630
+#define CLK_PERIPH_BUS		0x700
+#define CLK_PERIPH_CORE		0x710
+#define CLK_PERIPH_SGPIO	0x718
+#define CLK_USB0		0x800
+#define CLK_USB1		0x900
+#define CLK_SPI			0xA00
+#define CLK_ADCHS		0xB00
+
+/* Clock Control Unit 2 (CCU2) clock offsets */
+#define CLK_AUDIO		0x100
+#define CLK_APB2_UART3		0x200
+#define CLK_APB2_UART2		0x300
+#define CLK_APB0_UART1		0x400
+#define CLK_APB0_UART0		0x500
+#define CLK_APB2_SSP1		0x600
+#define CLK_APB0_SSP0		0x700
+#define CLK_SDIO		0x800
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/lpc18xx-cgu.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/lpc18xx-cgu.h
new file mode 100644
index 0000000000000000000000000000000000000000..6e57c6d2ca668d6110effd148968aace7505f671
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/lpc18xx-cgu.h
@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2015 Joachim Eastwood <manabian@gmail.com>
+ *
+ * This code is released using a dual license strategy: BSD/GPL
+ * You can choose the licence that better fits your requirements.
+ *
+ * Released under the terms of 3-clause BSD License
+ * Released under the terms of GNU General Public License Version 2.0
+ *
+ */
+
+/* LPC18xx/43xx base clock ids */
+#define BASE_SAFE_CLK		0
+#define BASE_USB0_CLK		1
+#define BASE_PERIPH_CLK		2
+#define BASE_USB1_CLK		3
+#define BASE_CPU_CLK		4
+#define BASE_SPIFI_CLK		5
+#define BASE_SPI_CLK		6
+#define BASE_PHY_RX_CLK		7
+#define BASE_PHY_TX_CLK		8
+#define BASE_APB1_CLK		9
+#define BASE_APB3_CLK		10
+#define BASE_LCD_CLK		11
+#define BASE_ADCHS_CLK		12
+#define BASE_SDIO_CLK		13
+#define BASE_SSP0_CLK		14
+#define BASE_SSP1_CLK		15
+#define BASE_UART0_CLK		16
+#define BASE_UART1_CLK		17
+#define BASE_UART2_CLK		18
+#define BASE_UART3_CLK		19
+#define BASE_OUT_CLK		20
+#define BASE_RES1_CLK		21
+#define BASE_RES2_CLK		22
+#define BASE_RES3_CLK		23
+#define BASE_RES4_CLK		24
+#define BASE_AUDIO_CLK		25
+#define BASE_CGU_OUT0_CLK	26
+#define BASE_CGU_OUT1_CLK	27
+#define BASE_CLK_MAX		(BASE_CGU_OUT1_CLK + 1)
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/lpc32xx-clock.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/lpc32xx-clock.h
new file mode 100644
index 0000000000000000000000000000000000000000..e624d3a527983135e14862a5580e7e1a4112ee53
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/lpc32xx-clock.h
@@ -0,0 +1,58 @@
+/*
+ * Copyright (c) 2015 Vladimir Zapolskiy <vz@mleia.com>
+ *
+ * This code is released using a dual license strategy: BSD/GPL
+ * You can choose the licence that better fits your requirements.
+ *
+ * Released under the terms of 3-clause BSD License
+ * Released under the terms of GNU General Public License Version 2.0
+ *
+ */
+
+#ifndef __DT_BINDINGS_LPC32XX_CLOCK_H
+#define __DT_BINDINGS_LPC32XX_CLOCK_H
+
+/* LPC32XX System Control Block clocks */
+#define LPC32XX_CLK_RTC		1
+#define LPC32XX_CLK_DMA		2
+#define LPC32XX_CLK_MLC		3
+#define LPC32XX_CLK_SLC		4
+#define LPC32XX_CLK_LCD		5
+#define LPC32XX_CLK_MAC		6
+#define LPC32XX_CLK_SD		7
+#define LPC32XX_CLK_DDRAM	8
+#define LPC32XX_CLK_SSP0	9
+#define LPC32XX_CLK_SSP1	10
+#define LPC32XX_CLK_UART3	11
+#define LPC32XX_CLK_UART4	12
+#define LPC32XX_CLK_UART5	13
+#define LPC32XX_CLK_UART6	14
+#define LPC32XX_CLK_IRDA	15
+#define LPC32XX_CLK_I2C1	16
+#define LPC32XX_CLK_I2C2	17
+#define LPC32XX_CLK_TIMER0	18
+#define LPC32XX_CLK_TIMER1	19
+#define LPC32XX_CLK_TIMER2	20
+#define LPC32XX_CLK_TIMER3	21
+#define LPC32XX_CLK_TIMER4	22
+#define LPC32XX_CLK_TIMER5	23
+#define LPC32XX_CLK_WDOG	24
+#define LPC32XX_CLK_I2S0	25
+#define LPC32XX_CLK_I2S1	26
+#define LPC32XX_CLK_SPI1	27
+#define LPC32XX_CLK_SPI2	28
+#define LPC32XX_CLK_MCPWM	29
+#define LPC32XX_CLK_HSTIMER	30
+#define LPC32XX_CLK_KEY		31
+#define LPC32XX_CLK_PWM1	32
+#define LPC32XX_CLK_PWM2	33
+#define LPC32XX_CLK_ADC		34
+#define LPC32XX_CLK_HCLK_PLL	35
+#define LPC32XX_CLK_PERIPH	36
+
+/* LPC32XX USB clocks */
+#define LPC32XX_USB_CLK_I2C	1
+#define LPC32XX_USB_CLK_DEVICE	2
+#define LPC32XX_USB_CLK_HOST	3
+
+#endif /* __DT_BINDINGS_LPC32XX_CLOCK_H */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/lsi,axm5516-clks.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/lsi,axm5516-clks.h
new file mode 100644
index 0000000000000000000000000000000000000000..beb41ace5dd684966ff0a5a29797a5f5a8f8b3ed
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/lsi,axm5516-clks.h
@@ -0,0 +1,36 @@
+/*
+ * Copyright (c) 2014 LSI Corporation
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ */
+
+#ifndef _DT_BINDINGS_CLK_AXM5516_H
+#define _DT_BINDINGS_CLK_AXM5516_H
+
+#define AXXIA_CLK_FAB_PLL	0
+#define AXXIA_CLK_CPU_PLL	1
+#define AXXIA_CLK_SYS_PLL	2
+#define AXXIA_CLK_SM0_PLL	3
+#define AXXIA_CLK_SM1_PLL	4
+#define AXXIA_CLK_FAB_DIV	5
+#define AXXIA_CLK_SYS_DIV	6
+#define AXXIA_CLK_NRCP_DIV	7
+#define AXXIA_CLK_CPU0_DIV	8
+#define AXXIA_CLK_CPU1_DIV	9
+#define AXXIA_CLK_CPU2_DIV	10
+#define AXXIA_CLK_CPU3_DIV	11
+#define AXXIA_CLK_PER_DIV	12
+#define AXXIA_CLK_MMC_DIV	13
+#define AXXIA_CLK_FAB		14
+#define AXXIA_CLK_SYS		15
+#define AXXIA_CLK_NRCP		16
+#define AXXIA_CLK_CPU0		17
+#define AXXIA_CLK_CPU1		18
+#define AXXIA_CLK_CPU2		19
+#define AXXIA_CLK_CPU3		20
+#define AXXIA_CLK_PER		21
+#define AXXIA_CLK_MMC		22
+
+#endif
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/marvell,mmp2.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/marvell,mmp2.h
new file mode 100644
index 0000000000000000000000000000000000000000..228a5e234af048ce8388bb02326a16c183fb4444
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/marvell,mmp2.h
@@ -0,0 +1,76 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __DTS_MARVELL_MMP2_CLOCK_H
+#define __DTS_MARVELL_MMP2_CLOCK_H
+
+/* fixed clocks and plls */
+#define MMP2_CLK_CLK32			1
+#define MMP2_CLK_VCTCXO			2
+#define MMP2_CLK_PLL1			3
+#define MMP2_CLK_PLL1_2			8
+#define MMP2_CLK_PLL1_4			9
+#define MMP2_CLK_PLL1_8			10
+#define MMP2_CLK_PLL1_16		11
+#define MMP2_CLK_PLL1_3			12
+#define MMP2_CLK_PLL1_6			13
+#define MMP2_CLK_PLL1_12		14
+#define MMP2_CLK_PLL1_20		15
+#define MMP2_CLK_PLL2			16
+#define MMP2_CLK_PLL2_2			17
+#define MMP2_CLK_PLL2_4			18
+#define MMP2_CLK_PLL2_8			19
+#define MMP2_CLK_PLL2_16		20
+#define MMP2_CLK_PLL2_3			21
+#define MMP2_CLK_PLL2_6			22
+#define MMP2_CLK_PLL2_12		23
+#define MMP2_CLK_VCTCXO_2		24
+#define MMP2_CLK_VCTCXO_4		25
+#define MMP2_CLK_UART_PLL		26
+#define MMP2_CLK_USB_PLL		27
+
+/* apb periphrals */
+#define MMP2_CLK_TWSI0			60
+#define MMP2_CLK_TWSI1			61
+#define MMP2_CLK_TWSI2			62
+#define MMP2_CLK_TWSI3			63
+#define MMP2_CLK_TWSI4			64
+#define MMP2_CLK_TWSI5			65
+#define MMP2_CLK_GPIO			66
+#define MMP2_CLK_KPC			67
+#define MMP2_CLK_RTC			68
+#define MMP2_CLK_PWM0			69
+#define MMP2_CLK_PWM1			70
+#define MMP2_CLK_PWM2			71
+#define MMP2_CLK_PWM3			72
+#define MMP2_CLK_UART0			73
+#define MMP2_CLK_UART1			74
+#define MMP2_CLK_UART2			75
+#define MMP2_CLK_UART3			76
+#define MMP2_CLK_SSP0			77
+#define MMP2_CLK_SSP1			78
+#define MMP2_CLK_SSP2			79
+#define MMP2_CLK_SSP3			80
+#define MMP2_CLK_TIMER			81
+
+/* axi periphrals */
+#define MMP2_CLK_SDH0			101
+#define MMP2_CLK_SDH1			102
+#define MMP2_CLK_SDH2			103
+#define MMP2_CLK_SDH3			104
+#define MMP2_CLK_USB			105
+#define MMP2_CLK_DISP0			106
+#define MMP2_CLK_DISP0_MUX		107
+#define MMP2_CLK_DISP0_SPHY		108
+#define MMP2_CLK_DISP1			109
+#define MMP2_CLK_DISP1_MUX		110
+#define MMP2_CLK_CCIC_ARBITER		111
+#define MMP2_CLK_CCIC0			112
+#define MMP2_CLK_CCIC0_MIX		113
+#define MMP2_CLK_CCIC0_PHY		114
+#define MMP2_CLK_CCIC0_SPHY		115
+#define MMP2_CLK_CCIC1			116
+#define MMP2_CLK_CCIC1_MIX		117
+#define MMP2_CLK_CCIC1_PHY		118
+#define MMP2_CLK_CCIC1_SPHY		119
+
+#define MMP2_NR_CLKS			200
+#endif
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/marvell,pxa168.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/marvell,pxa168.h
new file mode 100644
index 0000000000000000000000000000000000000000..caf90436b84836ad4bb62f6591c7ea5e479169f5
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/marvell,pxa168.h
@@ -0,0 +1,61 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __DTS_MARVELL_PXA168_CLOCK_H
+#define __DTS_MARVELL_PXA168_CLOCK_H
+
+/* fixed clocks and plls */
+#define PXA168_CLK_CLK32		1
+#define PXA168_CLK_VCTCXO		2
+#define PXA168_CLK_PLL1			3
+#define PXA168_CLK_PLL1_2		8
+#define PXA168_CLK_PLL1_4		9
+#define PXA168_CLK_PLL1_8		10
+#define PXA168_CLK_PLL1_16		11
+#define PXA168_CLK_PLL1_6		12
+#define PXA168_CLK_PLL1_12		13
+#define PXA168_CLK_PLL1_24		14
+#define PXA168_CLK_PLL1_48		15
+#define PXA168_CLK_PLL1_96		16
+#define PXA168_CLK_PLL1_13		17
+#define PXA168_CLK_PLL1_13_1_5		18
+#define PXA168_CLK_PLL1_2_1_5		19
+#define PXA168_CLK_PLL1_3_16		20
+#define PXA168_CLK_PLL1_192		21
+#define PXA168_CLK_UART_PLL		27
+#define PXA168_CLK_USB_PLL		28
+
+/* apb periphrals */
+#define PXA168_CLK_TWSI0		60
+#define PXA168_CLK_TWSI1		61
+#define PXA168_CLK_TWSI2		62
+#define PXA168_CLK_TWSI3		63
+#define PXA168_CLK_GPIO			64
+#define PXA168_CLK_KPC			65
+#define PXA168_CLK_RTC			66
+#define PXA168_CLK_PWM0			67
+#define PXA168_CLK_PWM1			68
+#define PXA168_CLK_PWM2			69
+#define PXA168_CLK_PWM3			70
+#define PXA168_CLK_UART0		71
+#define PXA168_CLK_UART1		72
+#define PXA168_CLK_UART2		73
+#define PXA168_CLK_SSP0			74
+#define PXA168_CLK_SSP1			75
+#define PXA168_CLK_SSP2			76
+#define PXA168_CLK_SSP3			77
+#define PXA168_CLK_SSP4			78
+#define PXA168_CLK_TIMER		79
+
+/* axi periphrals */
+#define PXA168_CLK_DFC			100
+#define PXA168_CLK_SDH0			101
+#define PXA168_CLK_SDH1			102
+#define PXA168_CLK_SDH2			103
+#define PXA168_CLK_USB			104
+#define PXA168_CLK_SPH			105
+#define PXA168_CLK_DISP0		106
+#define PXA168_CLK_CCIC0		107
+#define PXA168_CLK_CCIC0_PHY		108
+#define PXA168_CLK_CCIC0_SPHY		109
+
+#define PXA168_NR_CLKS			200
+#endif
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/marvell,pxa1928.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/marvell,pxa1928.h
new file mode 100644
index 0000000000000000000000000000000000000000..5dca4820297fed620587c438f7b7c4ee4abad426
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/marvell,pxa1928.h
@@ -0,0 +1,58 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __DTS_MARVELL_PXA1928_CLOCK_H
+#define __DTS_MARVELL_PXA1928_CLOCK_H
+
+/*
+ * Clock ID values here correspond to the control register offset/4.
+ */
+
+/* apb peripherals */
+#define PXA1928_CLK_RTC			0x00
+#define PXA1928_CLK_TWSI0		0x01
+#define PXA1928_CLK_TWSI1		0x02
+#define PXA1928_CLK_TWSI2		0x03
+#define PXA1928_CLK_TWSI3		0x04
+#define PXA1928_CLK_OWIRE		0x05
+#define PXA1928_CLK_KPC			0x06
+#define PXA1928_CLK_TB_ROTARY		0x07
+#define PXA1928_CLK_SW_JTAG		0x08
+#define PXA1928_CLK_TIMER1		0x09
+#define PXA1928_CLK_UART0		0x0b
+#define PXA1928_CLK_UART1		0x0c
+#define PXA1928_CLK_UART2		0x0d
+#define PXA1928_CLK_GPIO		0x0e
+#define PXA1928_CLK_PWM0		0x0f
+#define PXA1928_CLK_PWM1		0x10
+#define PXA1928_CLK_PWM2		0x11
+#define PXA1928_CLK_PWM3		0x12
+#define PXA1928_CLK_SSP0		0x13
+#define PXA1928_CLK_SSP1		0x14
+#define PXA1928_CLK_SSP2		0x15
+
+#define PXA1928_CLK_TWSI4		0x1f
+#define PXA1928_CLK_TWSI5		0x20
+#define PXA1928_CLK_UART3		0x22
+#define PXA1928_CLK_THSENS_GLOB		0x24
+#define PXA1928_CLK_THSENS_CPU		0x26
+#define PXA1928_CLK_THSENS_VPU		0x27
+#define PXA1928_CLK_THSENS_GC		0x28
+#define PXA1928_APBC_NR_CLKS		0x30
+
+
+/* axi peripherals */
+#define PXA1928_CLK_SDH0		0x15
+#define PXA1928_CLK_SDH1		0x16
+#define PXA1928_CLK_USB			0x17
+#define PXA1928_CLK_NAND		0x18
+#define PXA1928_CLK_DMA			0x19
+
+#define PXA1928_CLK_SDH2		0x3a
+#define PXA1928_CLK_SDH3		0x3b
+#define PXA1928_CLK_HSIC		0x3e
+#define PXA1928_CLK_SDH4		0x57
+#define PXA1928_CLK_GC3D		0x5d
+#define PXA1928_CLK_GC2D		0x5f
+
+#define PXA1928_APMU_NR_CLKS		0x60
+
+#endif
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/marvell,pxa910.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/marvell,pxa910.h
new file mode 100644
index 0000000000000000000000000000000000000000..7bf46238946eb2edb290a32c79ba02f09f62d1ed
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/marvell,pxa910.h
@@ -0,0 +1,59 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __DTS_MARVELL_PXA910_CLOCK_H
+#define __DTS_MARVELL_PXA910_CLOCK_H
+
+/* fixed clocks and plls */
+#define PXA910_CLK_CLK32		1
+#define PXA910_CLK_VCTCXO		2
+#define PXA910_CLK_PLL1			3
+#define PXA910_CLK_PLL1_2		8
+#define PXA910_CLK_PLL1_4		9
+#define PXA910_CLK_PLL1_8		10
+#define PXA910_CLK_PLL1_16		11
+#define PXA910_CLK_PLL1_6		12
+#define PXA910_CLK_PLL1_12		13
+#define PXA910_CLK_PLL1_24		14
+#define PXA910_CLK_PLL1_48		15
+#define PXA910_CLK_PLL1_96		16
+#define PXA910_CLK_PLL1_13		17
+#define PXA910_CLK_PLL1_13_1_5		18
+#define PXA910_CLK_PLL1_2_1_5		19
+#define PXA910_CLK_PLL1_3_16		20
+#define PXA910_CLK_PLL1_192		21
+#define PXA910_CLK_UART_PLL		27
+#define PXA910_CLK_USB_PLL		28
+
+/* apb periphrals */
+#define PXA910_CLK_TWSI0		60
+#define PXA910_CLK_TWSI1		61
+#define PXA910_CLK_TWSI2		62
+#define PXA910_CLK_TWSI3		63
+#define PXA910_CLK_GPIO			64
+#define PXA910_CLK_KPC			65
+#define PXA910_CLK_RTC			66
+#define PXA910_CLK_PWM0			67
+#define PXA910_CLK_PWM1			68
+#define PXA910_CLK_PWM2			69
+#define PXA910_CLK_PWM3			70
+#define PXA910_CLK_UART0		71
+#define PXA910_CLK_UART1		72
+#define PXA910_CLK_UART2		73
+#define PXA910_CLK_SSP0			74
+#define PXA910_CLK_SSP1			75
+#define PXA910_CLK_TIMER0		76
+#define PXA910_CLK_TIMER1		77
+
+/* axi periphrals */
+#define PXA910_CLK_DFC			100
+#define PXA910_CLK_SDH0			101
+#define PXA910_CLK_SDH1			102
+#define PXA910_CLK_SDH2			103
+#define PXA910_CLK_USB			104
+#define PXA910_CLK_SPH			105
+#define PXA910_CLK_DISP0		106
+#define PXA910_CLK_CCIC0		107
+#define PXA910_CLK_CCIC0_PHY		108
+#define PXA910_CLK_CCIC0_SPHY		109
+
+#define PXA910_NR_CLKS			200
+#endif
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/maxim,max77620.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/maxim,max77620.h
new file mode 100644
index 0000000000000000000000000000000000000000..82aba2849681768c9ca7eb9e6e0f3c61443388a7
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/maxim,max77620.h
@@ -0,0 +1,21 @@
+/*
+ * Copyright (C) 2016 NVIDIA CORPORATION. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Device Tree binding constants clocks for the Maxim 77620 PMIC.
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_MAXIM_MAX77620_CLOCK_H
+#define _DT_BINDINGS_CLOCK_MAXIM_MAX77620_CLOCK_H
+
+/* Fixed rate clocks. */
+
+#define MAX77620_CLK_32K_OUT0		0
+
+/* Total number of clocks. */
+#define MAX77620_CLKS_NUM		(MAX77620_CLK_32K_OUT0 + 1)
+
+#endif /* _DT_BINDINGS_CLOCK_MAXIM_MAX77620_CLOCK_H */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/maxim,max77686.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/maxim,max77686.h
new file mode 100644
index 0000000000000000000000000000000000000000..7b28b09058699a31b2c6441189fc222667680c79
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/maxim,max77686.h
@@ -0,0 +1,23 @@
+/*
+ * Copyright (C) 2014 Google, Inc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Device Tree binding constants clocks for the Maxim 77686 PMIC.
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_MAXIM_MAX77686_CLOCK_H
+#define _DT_BINDINGS_CLOCK_MAXIM_MAX77686_CLOCK_H
+
+/* Fixed rate clocks. */
+
+#define MAX77686_CLK_AP		0
+#define MAX77686_CLK_CP		1
+#define MAX77686_CLK_PMIC	2
+
+/* Total number of clocks. */
+#define MAX77686_CLKS_NUM		(MAX77686_CLK_PMIC + 1)
+
+#endif /* _DT_BINDINGS_CLOCK_MAXIM_MAX77686_CLOCK_H */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/maxim,max77802.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/maxim,max77802.h
new file mode 100644
index 0000000000000000000000000000000000000000..997312edcbb5b059375f1c31e745bb66568411ed
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/maxim,max77802.h
@@ -0,0 +1,22 @@
+/*
+ * Copyright (C) 2014 Google, Inc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Device Tree binding constants clocks for the Maxim 77802 PMIC.
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_MAXIM_MAX77802_CLOCK_H
+#define _DT_BINDINGS_CLOCK_MAXIM_MAX77802_CLOCK_H
+
+/* Fixed rate clocks. */
+
+#define MAX77802_CLK_32K_AP		0
+#define MAX77802_CLK_32K_CP		1
+
+/* Total number of clocks. */
+#define MAX77802_CLKS_NUM		(MAX77802_CLK_32K_CP + 1)
+
+#endif /* _DT_BINDINGS_CLOCK_MAXIM_MAX77802_CLOCK_H */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/maxim,max9485.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/maxim,max9485.h
new file mode 100644
index 0000000000000000000000000000000000000000..185b09ce18697be7fca93b1ba566e62557dd6841
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/maxim,max9485.h
@@ -0,0 +1,18 @@
+/*
+ * Copyright (C) 2018 Daniel Mack
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __DT_BINDINGS_MAX9485_CLK_H
+#define __DT_BINDINGS_MAX9485_CLK_H
+
+#define MAX9485_MCLKOUT	0
+#define MAX9485_CLKOUT	1
+#define MAX9485_CLKOUT1	2
+#define MAX9485_CLKOUT2	3
+
+#endif /* __DT_BINDINGS_MAX9485_CLK_H */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/meson8b-clkc.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/meson8b-clkc.h
new file mode 100644
index 0000000000000000000000000000000000000000..a60f47b49231db7b644eb59e86c30117cb6e28a5
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/meson8b-clkc.h
@@ -0,0 +1,107 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Meson8b clock tree IDs
+ */
+
+#ifndef __MESON8B_CLKC_H
+#define __MESON8B_CLKC_H
+
+#define CLKID_UNUSED		0
+#define CLKID_XTAL		1
+#define CLKID_PLL_FIXED		2
+#define CLKID_PLL_VID		3
+#define CLKID_PLL_SYS		4
+#define CLKID_FCLK_DIV2		5
+#define CLKID_FCLK_DIV3		6
+#define CLKID_FCLK_DIV4		7
+#define CLKID_FCLK_DIV5		8
+#define CLKID_FCLK_DIV7		9
+#define CLKID_CLK81		10
+#define CLKID_MALI		11
+#define CLKID_CPUCLK		12
+#define CLKID_ZERO		13
+#define CLKID_MPEG_SEL		14
+#define CLKID_MPEG_DIV		15
+#define CLKID_DDR		16
+#define CLKID_DOS		17
+#define CLKID_ISA		18
+#define CLKID_PL301		19
+#define CLKID_PERIPHS		20
+#define CLKID_SPICC		21
+#define CLKID_I2C		22
+#define CLKID_SAR_ADC		23
+#define CLKID_SMART_CARD	24
+#define CLKID_RNG0		25
+#define CLKID_UART0		26
+#define CLKID_SDHC		27
+#define CLKID_STREAM		28
+#define CLKID_ASYNC_FIFO	29
+#define CLKID_SDIO		30
+#define CLKID_ABUF		31
+#define CLKID_HIU_IFACE		32
+#define CLKID_ASSIST_MISC	33
+#define CLKID_SPI		34
+#define CLKID_I2S_SPDIF		35
+#define CLKID_ETH		36
+#define CLKID_DEMUX		37
+#define CLKID_AIU_GLUE		38
+#define CLKID_IEC958		39
+#define CLKID_I2S_OUT		40
+#define CLKID_AMCLK		41
+#define CLKID_AIFIFO2		42
+#define CLKID_MIXER		43
+#define CLKID_MIXER_IFACE	44
+#define CLKID_ADC		45
+#define CLKID_BLKMV		46
+#define CLKID_AIU		47
+#define CLKID_UART1		48
+#define CLKID_G2D		49
+#define CLKID_USB0		50
+#define CLKID_USB1		51
+#define CLKID_RESET		52
+#define CLKID_NAND		53
+#define CLKID_DOS_PARSER	54
+#define CLKID_USB		55
+#define CLKID_VDIN1		56
+#define CLKID_AHB_ARB0		57
+#define CLKID_EFUSE		58
+#define CLKID_BOOT_ROM		59
+#define CLKID_AHB_DATA_BUS	60
+#define CLKID_AHB_CTRL_BUS	61
+#define CLKID_HDMI_INTR_SYNC	62
+#define CLKID_HDMI_PCLK		63
+#define CLKID_USB1_DDR_BRIDGE	64
+#define CLKID_USB0_DDR_BRIDGE	65
+#define CLKID_MMC_PCLK		66
+#define CLKID_DVIN		67
+#define CLKID_UART2		68
+#define CLKID_SANA		69
+#define CLKID_VPU_INTR		70
+#define CLKID_SEC_AHB_AHB3_BRIDGE	71
+#define CLKID_CLK81_A9		72
+#define CLKID_VCLK2_VENCI0	73
+#define CLKID_VCLK2_VENCI1	74
+#define CLKID_VCLK2_VENCP0	75
+#define CLKID_VCLK2_VENCP1	76
+#define CLKID_GCLK_VENCI_INT	77
+#define CLKID_GCLK_VENCP_INT	78
+#define CLKID_DAC_CLK		79
+#define CLKID_AOCLK_GATE	80
+#define CLKID_IEC958_GATE	81
+#define CLKID_ENC480P		82
+#define CLKID_RNG1		83
+#define CLKID_GCLK_VENCL_INT	84
+#define CLKID_VCLK2_VENCLMCC	85
+#define CLKID_VCLK2_VENCL	86
+#define CLKID_VCLK2_OTHER	87
+#define CLKID_EDP		88
+#define CLKID_AO_MEDIA_CPU	89
+#define CLKID_AO_AHB_SRAM	90
+#define CLKID_AO_AHB_BUS	91
+#define CLKID_AO_IFACE		92
+#define CLKID_MPLL0		93
+#define CLKID_MPLL1		94
+#define CLKID_MPLL2		95
+#define CLKID_NAND_CLK		112
+
+#endif /* __MESON8B_CLKC_H */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/microchip,pic32-clock.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/microchip,pic32-clock.h
new file mode 100644
index 0000000000000000000000000000000000000000..184647a6a8de6e1a026a8818e72627e62e36682e
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/microchip,pic32-clock.h
@@ -0,0 +1,42 @@
+/*
+ * Purna Chandra Mandal,<purna.mandal@microchip.com>
+ * Copyright (C) 2015 Microchip Technology Inc.  All rights reserved.
+ *
+ * This program is free software; you can distribute it and/or modify it
+ * under the terms of the GNU General Public License (Version 2) as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ * for more details.
+ */
+
+#ifndef _DT_BINDINGS_CLK_MICROCHIP_PIC32_H_
+#define _DT_BINDINGS_CLK_MICROCHIP_PIC32_H_
+
+/* clock output indices */
+#define POSCCLK		0
+#define FRCCLK		1
+#define BFRCCLK		2
+#define LPRCCLK		3
+#define SOSCCLK		4
+#define FRCDIVCLK	5
+#define PLLCLK		6
+#define SCLK		7
+#define PB1CLK		8
+#define PB2CLK		9
+#define PB3CLK		10
+#define PB4CLK		11
+#define PB5CLK		12
+#define PB6CLK		13
+#define PB7CLK		14
+#define REF1CLK		15
+#define REF2CLK		16
+#define REF3CLK		17
+#define REF4CLK		18
+#define REF5CLK		19
+#define UPLLCLK		20
+#define MAXCLKS		21
+
+#endif	/* _DT_BINDINGS_CLK_MICROCHIP_PIC32_H_ */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/mpc512x-clock.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/mpc512x-clock.h
new file mode 100644
index 0000000000000000000000000000000000000000..13c316bf2796b7b8aeb345a0b9d65c159196346d
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/mpc512x-clock.h
@@ -0,0 +1,77 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * This header provides constants for MPC512x clock specs in DT bindings.
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_MPC512x_CLOCK_H
+#define _DT_BINDINGS_CLOCK_MPC512x_CLOCK_H
+
+#define MPC512x_CLK_DUMMY		0
+#define MPC512x_CLK_REF			1
+#define MPC512x_CLK_SYS			2
+#define MPC512x_CLK_DIU			3
+#define MPC512x_CLK_VIU			4
+#define MPC512x_CLK_CSB			5
+#define MPC512x_CLK_E300		6
+#define MPC512x_CLK_IPS			7
+#define MPC512x_CLK_FEC			8
+#define MPC512x_CLK_SATA		9
+#define MPC512x_CLK_PATA		10
+#define MPC512x_CLK_NFC			11
+#define MPC512x_CLK_LPC			12
+#define MPC512x_CLK_MBX_BUS		13
+#define MPC512x_CLK_MBX			14
+#define MPC512x_CLK_MBX_3D		15
+#define MPC512x_CLK_AXE			16
+#define MPC512x_CLK_USB1		17
+#define MPC512x_CLK_USB2		18
+#define MPC512x_CLK_I2C			19
+#define MPC512x_CLK_MSCAN0_MCLK		20
+#define MPC512x_CLK_MSCAN1_MCLK		21
+#define MPC512x_CLK_MSCAN2_MCLK		22
+#define MPC512x_CLK_MSCAN3_MCLK		23
+#define MPC512x_CLK_BDLC		24
+#define MPC512x_CLK_SDHC		25
+#define MPC512x_CLK_PCI			26
+#define MPC512x_CLK_PSC_MCLK_IN		27
+#define MPC512x_CLK_SPDIF_TX		28
+#define MPC512x_CLK_SPDIF_RX		29
+#define MPC512x_CLK_SPDIF_MCLK		30
+#define MPC512x_CLK_SPDIF		31
+#define MPC512x_CLK_AC97		32
+#define MPC512x_CLK_PSC0_MCLK		33
+#define MPC512x_CLK_PSC1_MCLK		34
+#define MPC512x_CLK_PSC2_MCLK		35
+#define MPC512x_CLK_PSC3_MCLK		36
+#define MPC512x_CLK_PSC4_MCLK		37
+#define MPC512x_CLK_PSC5_MCLK		38
+#define MPC512x_CLK_PSC6_MCLK		39
+#define MPC512x_CLK_PSC7_MCLK		40
+#define MPC512x_CLK_PSC8_MCLK		41
+#define MPC512x_CLK_PSC9_MCLK		42
+#define MPC512x_CLK_PSC10_MCLK		43
+#define MPC512x_CLK_PSC11_MCLK		44
+#define MPC512x_CLK_PSC_FIFO		45
+#define MPC512x_CLK_PSC0		46
+#define MPC512x_CLK_PSC1		47
+#define MPC512x_CLK_PSC2		48
+#define MPC512x_CLK_PSC3		49
+#define MPC512x_CLK_PSC4		50
+#define MPC512x_CLK_PSC5		51
+#define MPC512x_CLK_PSC6		52
+#define MPC512x_CLK_PSC7		53
+#define MPC512x_CLK_PSC8		54
+#define MPC512x_CLK_PSC9		55
+#define MPC512x_CLK_PSC10		56
+#define MPC512x_CLK_PSC11		57
+#define MPC512x_CLK_SDHC2		58
+#define MPC512x_CLK_FEC2		59
+#define MPC512x_CLK_OUT0_CLK		60
+#define MPC512x_CLK_OUT1_CLK		61
+#define MPC512x_CLK_OUT2_CLK		62
+#define MPC512x_CLK_OUT3_CLK		63
+#define MPC512x_CLK_CAN_CLK_IN		64
+
+#define MPC512x_CLK_LAST_PUBLIC		64
+
+#endif
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/mt2701-clk.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/mt2701-clk.h
new file mode 100644
index 0000000000000000000000000000000000000000..9ac2f2b5710ab80ffd0c6e5b5366b6b83d99ff47
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/mt2701-clk.h
@@ -0,0 +1,492 @@
+/*
+ * Copyright (c) 2014 MediaTek Inc.
+ * Author: Shunli Wang <shunli.wang@mediatek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_CLK_MT2701_H
+#define _DT_BINDINGS_CLK_MT2701_H
+
+/* TOPCKGEN */
+#define CLK_TOP_SYSPLL				1
+#define CLK_TOP_SYSPLL_D2			2
+#define CLK_TOP_SYSPLL_D3			3
+#define CLK_TOP_SYSPLL_D5			4
+#define CLK_TOP_SYSPLL_D7			5
+#define CLK_TOP_SYSPLL1_D2			6
+#define CLK_TOP_SYSPLL1_D4			7
+#define CLK_TOP_SYSPLL1_D8			8
+#define CLK_TOP_SYSPLL1_D16			9
+#define CLK_TOP_SYSPLL2_D2			10
+#define CLK_TOP_SYSPLL2_D4			11
+#define CLK_TOP_SYSPLL2_D8			12
+#define CLK_TOP_SYSPLL3_D2			13
+#define CLK_TOP_SYSPLL3_D4			14
+#define CLK_TOP_SYSPLL4_D2			15
+#define CLK_TOP_SYSPLL4_D4			16
+#define CLK_TOP_UNIVPLL				17
+#define CLK_TOP_UNIVPLL_D2			18
+#define CLK_TOP_UNIVPLL_D3			19
+#define CLK_TOP_UNIVPLL_D5			20
+#define CLK_TOP_UNIVPLL_D7			21
+#define CLK_TOP_UNIVPLL_D26			22
+#define CLK_TOP_UNIVPLL_D52			23
+#define CLK_TOP_UNIVPLL_D108			24
+#define CLK_TOP_USB_PHY48M			25
+#define CLK_TOP_UNIVPLL1_D2			26
+#define CLK_TOP_UNIVPLL1_D4			27
+#define CLK_TOP_UNIVPLL1_D8			28
+#define CLK_TOP_UNIVPLL2_D2			29
+#define CLK_TOP_UNIVPLL2_D4			30
+#define CLK_TOP_UNIVPLL2_D8			31
+#define CLK_TOP_UNIVPLL2_D16			32
+#define CLK_TOP_UNIVPLL2_D32			33
+#define CLK_TOP_UNIVPLL3_D2			34
+#define CLK_TOP_UNIVPLL3_D4			35
+#define CLK_TOP_UNIVPLL3_D8			36
+#define CLK_TOP_MSDCPLL				37
+#define CLK_TOP_MSDCPLL_D2			38
+#define CLK_TOP_MSDCPLL_D4			39
+#define CLK_TOP_MSDCPLL_D8			40
+#define CLK_TOP_MMPLL				41
+#define CLK_TOP_MMPLL_D2			42
+#define CLK_TOP_DMPLL				43
+#define CLK_TOP_DMPLL_D2			44
+#define CLK_TOP_DMPLL_D4			45
+#define CLK_TOP_DMPLL_X2			46
+#define CLK_TOP_TVDPLL				47
+#define CLK_TOP_TVDPLL_D2			48
+#define CLK_TOP_TVDPLL_D4			49
+#define CLK_TOP_TVD2PLL				50
+#define CLK_TOP_TVD2PLL_D2			51
+#define CLK_TOP_HADDS2PLL_98M			52
+#define CLK_TOP_HADDS2PLL_294M			53
+#define CLK_TOP_HADDS2_FB			54
+#define CLK_TOP_MIPIPLL_D2			55
+#define CLK_TOP_MIPIPLL_D4			56
+#define CLK_TOP_HDMIPLL				57
+#define CLK_TOP_HDMIPLL_D2			58
+#define CLK_TOP_HDMIPLL_D3			59
+#define CLK_TOP_HDMI_SCL_RX			60
+#define CLK_TOP_HDMI_0_PIX340M			61
+#define CLK_TOP_HDMI_0_DEEP340M			62
+#define CLK_TOP_HDMI_0_PLL340M			63
+#define CLK_TOP_AUD1PLL_98M			64
+#define CLK_TOP_AUD2PLL_90M			65
+#define CLK_TOP_AUDPLL				66
+#define CLK_TOP_AUDPLL_D4			67
+#define CLK_TOP_AUDPLL_D8			68
+#define CLK_TOP_AUDPLL_D16			69
+#define CLK_TOP_AUDPLL_D24			70
+#define CLK_TOP_ETHPLL_500M			71
+#define CLK_TOP_VDECPLL				72
+#define CLK_TOP_VENCPLL				73
+#define CLK_TOP_MIPIPLL				74
+#define CLK_TOP_ARMPLL_1P3G			75
+
+#define CLK_TOP_MM_SEL				76
+#define CLK_TOP_DDRPHYCFG_SEL			77
+#define CLK_TOP_MEM_SEL				78
+#define CLK_TOP_AXI_SEL				79
+#define CLK_TOP_CAMTG_SEL			80
+#define CLK_TOP_MFG_SEL				81
+#define CLK_TOP_VDEC_SEL			82
+#define CLK_TOP_PWM_SEL				83
+#define CLK_TOP_MSDC30_0_SEL			84
+#define CLK_TOP_USB20_SEL			85
+#define CLK_TOP_SPI0_SEL			86
+#define CLK_TOP_UART_SEL			87
+#define CLK_TOP_AUDINTBUS_SEL			88
+#define CLK_TOP_AUDIO_SEL			89
+#define CLK_TOP_MSDC30_2_SEL			90
+#define CLK_TOP_MSDC30_1_SEL			91
+#define CLK_TOP_DPI1_SEL			92
+#define CLK_TOP_DPI0_SEL			93
+#define CLK_TOP_SCP_SEL				94
+#define CLK_TOP_PMICSPI_SEL			95
+#define CLK_TOP_APLL_SEL			96
+#define CLK_TOP_HDMI_SEL			97
+#define CLK_TOP_TVE_SEL				98
+#define CLK_TOP_EMMC_HCLK_SEL			99
+#define CLK_TOP_NFI2X_SEL			100
+#define CLK_TOP_RTC_SEL				101
+#define CLK_TOP_OSD_SEL				102
+#define CLK_TOP_NR_SEL				103
+#define CLK_TOP_DI_SEL				104
+#define CLK_TOP_FLASH_SEL			105
+#define CLK_TOP_ASM_M_SEL			106
+#define CLK_TOP_ASM_I_SEL			107
+#define CLK_TOP_INTDIR_SEL			108
+#define CLK_TOP_HDMIRX_BIST_SEL			109
+#define CLK_TOP_ETHIF_SEL			110
+#define CLK_TOP_MS_CARD_SEL			111
+#define CLK_TOP_ASM_H_SEL			112
+#define CLK_TOP_SPI1_SEL			113
+#define CLK_TOP_CMSYS_SEL			114
+#define CLK_TOP_MSDC30_3_SEL			115
+#define CLK_TOP_HDMIRX26_24_SEL			116
+#define CLK_TOP_AUD2DVD_SEL			117
+#define CLK_TOP_8BDAC_SEL			118
+#define CLK_TOP_SPI2_SEL			119
+#define CLK_TOP_AUD_MUX1_SEL			120
+#define CLK_TOP_AUD_MUX2_SEL			121
+#define CLK_TOP_AUDPLL_MUX_SEL			122
+#define CLK_TOP_AUD_K1_SRC_SEL			123
+#define CLK_TOP_AUD_K2_SRC_SEL			124
+#define CLK_TOP_AUD_K3_SRC_SEL			125
+#define CLK_TOP_AUD_K4_SRC_SEL			126
+#define CLK_TOP_AUD_K5_SRC_SEL			127
+#define CLK_TOP_AUD_K6_SRC_SEL			128
+#define CLK_TOP_PADMCLK_SEL			129
+#define CLK_TOP_AUD_EXTCK1_DIV			130
+#define CLK_TOP_AUD_EXTCK2_DIV			131
+#define CLK_TOP_AUD_MUX1_DIV			132
+#define CLK_TOP_AUD_MUX2_DIV			133
+#define CLK_TOP_AUD_K1_SRC_DIV			134
+#define CLK_TOP_AUD_K2_SRC_DIV			135
+#define CLK_TOP_AUD_K3_SRC_DIV			136
+#define CLK_TOP_AUD_K4_SRC_DIV			137
+#define CLK_TOP_AUD_K5_SRC_DIV			138
+#define CLK_TOP_AUD_K6_SRC_DIV			139
+#define CLK_TOP_AUD_I2S1_MCLK			140
+#define CLK_TOP_AUD_I2S2_MCLK			141
+#define CLK_TOP_AUD_I2S3_MCLK			142
+#define CLK_TOP_AUD_I2S4_MCLK			143
+#define CLK_TOP_AUD_I2S5_MCLK			144
+#define CLK_TOP_AUD_I2S6_MCLK			145
+#define CLK_TOP_AUD_48K_TIMING			146
+#define CLK_TOP_AUD_44K_TIMING			147
+
+#define CLK_TOP_32K_INTERNAL			148
+#define CLK_TOP_32K_EXTERNAL			149
+#define CLK_TOP_CLK26M_D8			150
+#define CLK_TOP_8BDAC				151
+#define CLK_TOP_WBG_DIG_416M			152
+#define CLK_TOP_DPI				153
+#define CLK_TOP_DSI0_LNTC_DSI			154
+#define CLK_TOP_AUD_EXT1			155
+#define CLK_TOP_AUD_EXT2			156
+#define CLK_TOP_NFI1X_PAD			157
+#define CLK_TOP_AXISEL_D4			158
+#define CLK_TOP_NR				159
+
+/* APMIXEDSYS */
+
+#define CLK_APMIXED_ARMPLL			1
+#define CLK_APMIXED_MAINPLL			2
+#define CLK_APMIXED_UNIVPLL			3
+#define CLK_APMIXED_MMPLL			4
+#define CLK_APMIXED_MSDCPLL			5
+#define CLK_APMIXED_TVDPLL			6
+#define CLK_APMIXED_AUD1PLL			7
+#define CLK_APMIXED_TRGPLL			8
+#define CLK_APMIXED_ETHPLL			9
+#define CLK_APMIXED_VDECPLL			10
+#define CLK_APMIXED_HADDS2PLL			11
+#define CLK_APMIXED_AUD2PLL			12
+#define CLK_APMIXED_TVD2PLL			13
+#define CLK_APMIXED_HDMI_REF			14
+#define CLK_APMIXED_NR				15
+
+/* DDRPHY */
+
+#define CLK_DDRPHY_VENCPLL			1
+#define CLK_DDRPHY_NR				2
+
+/* INFRACFG */
+
+#define CLK_INFRA_DBG				1
+#define CLK_INFRA_SMI				2
+#define CLK_INFRA_QAXI_CM4			3
+#define CLK_INFRA_AUD_SPLIN_B			4
+#define CLK_INFRA_AUDIO				5
+#define CLK_INFRA_EFUSE				6
+#define CLK_INFRA_L2C_SRAM			7
+#define CLK_INFRA_M4U				8
+#define CLK_INFRA_CONNMCU			9
+#define CLK_INFRA_TRNG				10
+#define CLK_INFRA_RAMBUFIF			11
+#define CLK_INFRA_CPUM				12
+#define CLK_INFRA_KP				13
+#define CLK_INFRA_CEC				14
+#define CLK_INFRA_IRRX				15
+#define CLK_INFRA_PMICSPI			16
+#define CLK_INFRA_PMICWRAP			17
+#define CLK_INFRA_DDCCI				18
+#define CLK_INFRA_CLK_13M			19
+#define CLK_INFRA_CPUSEL                        20
+#define CLK_INFRA_NR				21
+
+/* PERICFG */
+
+#define CLK_PERI_NFI				1
+#define CLK_PERI_THERM				2
+#define CLK_PERI_PWM1				3
+#define CLK_PERI_PWM2				4
+#define CLK_PERI_PWM3				5
+#define CLK_PERI_PWM4				6
+#define CLK_PERI_PWM5				7
+#define CLK_PERI_PWM6				8
+#define CLK_PERI_PWM7				9
+#define CLK_PERI_PWM				10
+#define CLK_PERI_USB0				11
+#define CLK_PERI_USB1				12
+#define CLK_PERI_AP_DMA				13
+#define CLK_PERI_MSDC30_0			14
+#define CLK_PERI_MSDC30_1			15
+#define CLK_PERI_MSDC30_2			16
+#define CLK_PERI_MSDC30_3			17
+#define CLK_PERI_MSDC50_3			18
+#define CLK_PERI_NLI				19
+#define CLK_PERI_UART0				20
+#define CLK_PERI_UART1				21
+#define CLK_PERI_UART2				22
+#define CLK_PERI_UART3				23
+#define CLK_PERI_BTIF				24
+#define CLK_PERI_I2C0				25
+#define CLK_PERI_I2C1				26
+#define CLK_PERI_I2C2				27
+#define CLK_PERI_I2C3				28
+#define CLK_PERI_AUXADC				29
+#define CLK_PERI_SPI0				30
+#define CLK_PERI_ETH				31
+#define CLK_PERI_USB0_MCU			32
+
+#define CLK_PERI_USB1_MCU			33
+#define CLK_PERI_USB_SLV			34
+#define CLK_PERI_GCPU				35
+#define CLK_PERI_NFI_ECC			36
+#define CLK_PERI_NFI_PAD			37
+#define CLK_PERI_FLASH				38
+#define CLK_PERI_HOST89_INT			39
+#define CLK_PERI_HOST89_SPI			40
+#define CLK_PERI_HOST89_DVD			41
+#define CLK_PERI_SPI1				42
+#define CLK_PERI_SPI2				43
+#define CLK_PERI_FCI				44
+
+#define CLK_PERI_UART0_SEL			45
+#define CLK_PERI_UART1_SEL			46
+#define CLK_PERI_UART2_SEL			47
+#define CLK_PERI_UART3_SEL			48
+#define CLK_PERI_NR				49
+
+/* AUDIO */
+
+#define CLK_AUD_AFE				1
+#define CLK_AUD_LRCK_DETECT			2
+#define CLK_AUD_I2S				3
+#define CLK_AUD_APLL_TUNER			4
+#define CLK_AUD_HDMI				5
+#define CLK_AUD_SPDF				6
+#define CLK_AUD_SPDF2				7
+#define CLK_AUD_APLL				8
+#define CLK_AUD_TML				9
+#define CLK_AUD_AHB_IDLE_EXT			10
+#define CLK_AUD_AHB_IDLE_INT			11
+
+#define CLK_AUD_I2SIN1				12
+#define CLK_AUD_I2SIN2				13
+#define CLK_AUD_I2SIN3				14
+#define CLK_AUD_I2SIN4				15
+#define CLK_AUD_I2SIN5				16
+#define CLK_AUD_I2SIN6				17
+#define CLK_AUD_I2SO1				18
+#define CLK_AUD_I2SO2				19
+#define CLK_AUD_I2SO3				20
+#define CLK_AUD_I2SO4				21
+#define CLK_AUD_I2SO5				22
+#define CLK_AUD_I2SO6				23
+#define CLK_AUD_ASRCI1				24
+#define CLK_AUD_ASRCI2				25
+#define CLK_AUD_ASRCO1				26
+#define CLK_AUD_ASRCO2				27
+#define CLK_AUD_ASRC11				28
+#define CLK_AUD_ASRC12				29
+#define CLK_AUD_HDMIRX				30
+#define CLK_AUD_INTDIR				31
+#define CLK_AUD_A1SYS				32
+#define CLK_AUD_A2SYS				33
+#define CLK_AUD_AFE_CONN			34
+#define CLK_AUD_AFE_PCMIF			35
+#define CLK_AUD_AFE_MRGIF			36
+
+#define CLK_AUD_MMIF_UL1			37
+#define CLK_AUD_MMIF_UL2			38
+#define CLK_AUD_MMIF_UL3			39
+#define CLK_AUD_MMIF_UL4			40
+#define CLK_AUD_MMIF_UL5			41
+#define CLK_AUD_MMIF_UL6			42
+#define CLK_AUD_MMIF_DL1			43
+#define CLK_AUD_MMIF_DL2			44
+#define CLK_AUD_MMIF_DL3			45
+#define CLK_AUD_MMIF_DL4			46
+#define CLK_AUD_MMIF_DL5			47
+#define CLK_AUD_MMIF_DL6			48
+#define CLK_AUD_MMIF_DLMCH			49
+#define CLK_AUD_MMIF_ARB1			50
+#define CLK_AUD_MMIF_AWB1			51
+#define CLK_AUD_MMIF_AWB2			52
+#define CLK_AUD_MMIF_DAI			53
+
+#define CLK_AUD_DMIC1				54
+#define CLK_AUD_DMIC2				55
+#define CLK_AUD_ASRCI3				56
+#define CLK_AUD_ASRCI4				57
+#define CLK_AUD_ASRCI5				58
+#define CLK_AUD_ASRCI6				59
+#define CLK_AUD_ASRCO3				60
+#define CLK_AUD_ASRCO4				61
+#define CLK_AUD_ASRCO5				62
+#define CLK_AUD_ASRCO6				63
+#define CLK_AUD_MEM_ASRC1			64
+#define CLK_AUD_MEM_ASRC2			65
+#define CLK_AUD_MEM_ASRC3			66
+#define CLK_AUD_MEM_ASRC4			67
+#define CLK_AUD_MEM_ASRC5			68
+#define CLK_AUD_DSD_ENC				69
+#define CLK_AUD_ASRC_BRG			70
+#define CLK_AUD_NR				71
+
+/* MMSYS */
+
+#define CLK_MM_SMI_COMMON			1
+#define CLK_MM_SMI_LARB0			2
+#define CLK_MM_CMDQ				3
+#define CLK_MM_MUTEX				4
+#define CLK_MM_DISP_COLOR			5
+#define CLK_MM_DISP_BLS				6
+#define CLK_MM_DISP_WDMA			7
+#define CLK_MM_DISP_RDMA			8
+#define CLK_MM_DISP_OVL				9
+#define CLK_MM_MDP_TDSHP			10
+#define CLK_MM_MDP_WROT				11
+#define CLK_MM_MDP_WDMA				12
+#define CLK_MM_MDP_RSZ1				13
+#define CLK_MM_MDP_RSZ0				14
+#define CLK_MM_MDP_RDMA				15
+#define CLK_MM_MDP_BLS_26M			16
+#define CLK_MM_CAM_MDP				17
+#define CLK_MM_FAKE_ENG				18
+#define CLK_MM_MUTEX_32K			19
+#define CLK_MM_DISP_RDMA1			20
+#define CLK_MM_DISP_UFOE			21
+
+#define CLK_MM_DSI_ENGINE			22
+#define CLK_MM_DSI_DIG				23
+#define CLK_MM_DPI_DIGL				24
+#define CLK_MM_DPI_ENGINE			25
+#define CLK_MM_DPI1_DIGL			26
+#define CLK_MM_DPI1_ENGINE			27
+#define CLK_MM_TVE_OUTPUT			28
+#define CLK_MM_TVE_INPUT			29
+#define CLK_MM_HDMI_PIXEL			30
+#define CLK_MM_HDMI_PLL				31
+#define CLK_MM_HDMI_AUDIO			32
+#define CLK_MM_HDMI_SPDIF			33
+#define CLK_MM_TVE_FMM				34
+#define CLK_MM_NR				35
+
+/* IMGSYS */
+
+#define CLK_IMG_SMI_COMM			1
+#define CLK_IMG_RESZ				2
+#define CLK_IMG_JPGDEC_SMI			3
+#define CLK_IMG_JPGDEC				4
+#define CLK_IMG_VENC_LT				5
+#define CLK_IMG_VENC				6
+#define CLK_IMG_NR				7
+
+/* VDEC */
+
+#define CLK_VDEC_CKGEN				1
+#define CLK_VDEC_LARB				2
+#define CLK_VDEC_NR				3
+
+/* HIFSYS */
+
+#define CLK_HIFSYS_USB0PHY			1
+#define CLK_HIFSYS_USB1PHY			2
+#define CLK_HIFSYS_PCIE0			3
+#define CLK_HIFSYS_PCIE1			4
+#define CLK_HIFSYS_PCIE2			5
+#define CLK_HIFSYS_NR				6
+
+/* ETHSYS */
+#define CLK_ETHSYS_HSDMA			1
+#define CLK_ETHSYS_ESW				2
+#define CLK_ETHSYS_GP2				3
+#define CLK_ETHSYS_GP1				4
+#define CLK_ETHSYS_PCM				5
+#define CLK_ETHSYS_GDMA				6
+#define CLK_ETHSYS_I2S				7
+#define CLK_ETHSYS_CRYPTO			8
+#define CLK_ETHSYS_NR				9
+
+/* G3DSYS */
+#define CLK_G3DSYS_CORE				1
+#define CLK_G3DSYS_NR				2
+
+/* BDP */
+
+#define CLK_BDP_BRG_BA				1
+#define CLK_BDP_BRG_DRAM			2
+#define CLK_BDP_LARB_DRAM			3
+#define CLK_BDP_WR_VDI_PXL			4
+#define CLK_BDP_WR_VDI_DRAM			5
+#define CLK_BDP_WR_B				6
+#define CLK_BDP_DGI_IN				7
+#define CLK_BDP_DGI_OUT				8
+#define CLK_BDP_FMT_MAST_27			9
+#define CLK_BDP_FMT_B				10
+#define CLK_BDP_OSD_B				11
+#define CLK_BDP_OSD_DRAM			12
+#define CLK_BDP_OSD_AGENT			13
+#define CLK_BDP_OSD_PXL				14
+#define CLK_BDP_RLE_B				15
+#define CLK_BDP_RLE_AGENT			16
+#define CLK_BDP_RLE_DRAM			17
+#define CLK_BDP_F27M				18
+#define CLK_BDP_F27M_VDOUT			19
+#define CLK_BDP_F27_74_74			20
+#define CLK_BDP_F2FS				21
+#define CLK_BDP_F2FS74_148			22
+#define CLK_BDP_FB				23
+#define CLK_BDP_VDO_DRAM			24
+#define CLK_BDP_VDO_2FS				25
+#define CLK_BDP_VDO_B				26
+#define CLK_BDP_WR_DI_PXL			27
+#define CLK_BDP_WR_DI_DRAM			28
+#define CLK_BDP_WR_DI_B				29
+#define CLK_BDP_NR_PXL				30
+#define CLK_BDP_NR_DRAM				31
+#define CLK_BDP_NR_B				32
+
+#define CLK_BDP_RX_F				33
+#define CLK_BDP_RX_X				34
+#define CLK_BDP_RXPDT				35
+#define CLK_BDP_RX_CSCL_N			36
+#define CLK_BDP_RX_CSCL				37
+#define CLK_BDP_RX_DDCSCL_N			38
+#define CLK_BDP_RX_DDCSCL			39
+#define CLK_BDP_RX_VCO				40
+#define CLK_BDP_RX_DP				41
+#define CLK_BDP_RX_P				42
+#define CLK_BDP_RX_M				43
+#define CLK_BDP_RX_PLL				44
+#define CLK_BDP_BRG_RT_B			45
+#define CLK_BDP_BRG_RT_DRAM			46
+#define CLK_BDP_LARBRT_DRAM			47
+#define CLK_BDP_TMDS_SYN			48
+#define CLK_BDP_HDMI_MON			49
+#define CLK_BDP_NR				50
+
+#endif /* _DT_BINDINGS_CLK_MT2701_H */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/mt2712-clk.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/mt2712-clk.h
new file mode 100644
index 0000000000000000000000000000000000000000..76265836a1e1dcfac22e8fdbc2714de76c7d583d
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/mt2712-clk.h
@@ -0,0 +1,435 @@
+/*
+ * Copyright (c) 2017 MediaTek Inc.
+ * Author: Weiyi Lu <weiyi.lu@mediatek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_CLK_MT2712_H
+#define _DT_BINDINGS_CLK_MT2712_H
+
+/* APMIXEDSYS */
+
+#define CLK_APMIXED_MAINPLL		0
+#define CLK_APMIXED_UNIVPLL		1
+#define CLK_APMIXED_VCODECPLL		2
+#define CLK_APMIXED_VENCPLL		3
+#define CLK_APMIXED_APLL1		4
+#define CLK_APMIXED_APLL2		5
+#define CLK_APMIXED_LVDSPLL		6
+#define CLK_APMIXED_LVDSPLL2		7
+#define CLK_APMIXED_MSDCPLL		8
+#define CLK_APMIXED_MSDCPLL2		9
+#define CLK_APMIXED_TVDPLL		10
+#define CLK_APMIXED_MMPLL		11
+#define CLK_APMIXED_ARMCA35PLL		12
+#define CLK_APMIXED_ARMCA72PLL		13
+#define CLK_APMIXED_ETHERPLL		14
+#define CLK_APMIXED_NR_CLK		15
+
+/* TOPCKGEN */
+
+#define CLK_TOP_ARMCA35PLL		0
+#define CLK_TOP_ARMCA35PLL_600M		1
+#define CLK_TOP_ARMCA35PLL_400M		2
+#define CLK_TOP_ARMCA72PLL		3
+#define CLK_TOP_SYSPLL			4
+#define CLK_TOP_SYSPLL_D2		5
+#define CLK_TOP_SYSPLL1_D2		6
+#define CLK_TOP_SYSPLL1_D4		7
+#define CLK_TOP_SYSPLL1_D8		8
+#define CLK_TOP_SYSPLL1_D16		9
+#define CLK_TOP_SYSPLL_D3		10
+#define CLK_TOP_SYSPLL2_D2		11
+#define CLK_TOP_SYSPLL2_D4		12
+#define CLK_TOP_SYSPLL_D5		13
+#define CLK_TOP_SYSPLL3_D2		14
+#define CLK_TOP_SYSPLL3_D4		15
+#define CLK_TOP_SYSPLL_D7		16
+#define CLK_TOP_SYSPLL4_D2		17
+#define CLK_TOP_SYSPLL4_D4		18
+#define CLK_TOP_UNIVPLL			19
+#define CLK_TOP_UNIVPLL_D7		20
+#define CLK_TOP_UNIVPLL_D26		21
+#define CLK_TOP_UNIVPLL_D52		22
+#define CLK_TOP_UNIVPLL_D104		23
+#define CLK_TOP_UNIVPLL_D208		24
+#define CLK_TOP_UNIVPLL_D2		25
+#define CLK_TOP_UNIVPLL1_D2		26
+#define CLK_TOP_UNIVPLL1_D4		27
+#define CLK_TOP_UNIVPLL1_D8		28
+#define CLK_TOP_UNIVPLL_D3		29
+#define CLK_TOP_UNIVPLL2_D2		30
+#define CLK_TOP_UNIVPLL2_D4		31
+#define CLK_TOP_UNIVPLL2_D8		32
+#define CLK_TOP_UNIVPLL_D5		33
+#define CLK_TOP_UNIVPLL3_D2		34
+#define CLK_TOP_UNIVPLL3_D4		35
+#define CLK_TOP_UNIVPLL3_D8		36
+#define CLK_TOP_F_MP0_PLL1		37
+#define CLK_TOP_F_MP0_PLL2		38
+#define CLK_TOP_F_BIG_PLL1		39
+#define CLK_TOP_F_BIG_PLL2		40
+#define CLK_TOP_F_BUS_PLL1		41
+#define CLK_TOP_F_BUS_PLL2		42
+#define CLK_TOP_APLL1			43
+#define CLK_TOP_APLL1_D2		44
+#define CLK_TOP_APLL1_D4		45
+#define CLK_TOP_APLL1_D8		46
+#define CLK_TOP_APLL1_D16		47
+#define CLK_TOP_APLL2			48
+#define CLK_TOP_APLL2_D2		49
+#define CLK_TOP_APLL2_D4		50
+#define CLK_TOP_APLL2_D8		51
+#define CLK_TOP_APLL2_D16		52
+#define CLK_TOP_LVDSPLL			53
+#define CLK_TOP_LVDSPLL_D2		54
+#define CLK_TOP_LVDSPLL_D4		55
+#define CLK_TOP_LVDSPLL_D8		56
+#define CLK_TOP_LVDSPLL2		57
+#define CLK_TOP_LVDSPLL2_D2		58
+#define CLK_TOP_LVDSPLL2_D4		59
+#define CLK_TOP_LVDSPLL2_D8		60
+#define CLK_TOP_ETHERPLL_125M		61
+#define CLK_TOP_ETHERPLL_50M		62
+#define CLK_TOP_CVBS			63
+#define CLK_TOP_CVBS_D2			64
+#define CLK_TOP_SYS_26M			65
+#define CLK_TOP_MMPLL			66
+#define CLK_TOP_MMPLL_D2		67
+#define CLK_TOP_VENCPLL			68
+#define CLK_TOP_VENCPLL_D2		69
+#define CLK_TOP_VCODECPLL		70
+#define CLK_TOP_VCODECPLL_D2		71
+#define CLK_TOP_TVDPLL			72
+#define CLK_TOP_TVDPLL_D2		73
+#define CLK_TOP_TVDPLL_D4		74
+#define CLK_TOP_TVDPLL_D8		75
+#define CLK_TOP_TVDPLL_429M		76
+#define CLK_TOP_TVDPLL_429M_D2		77
+#define CLK_TOP_TVDPLL_429M_D4		78
+#define CLK_TOP_MSDCPLL			79
+#define CLK_TOP_MSDCPLL_D2		80
+#define CLK_TOP_MSDCPLL_D4		81
+#define CLK_TOP_MSDCPLL2		82
+#define CLK_TOP_MSDCPLL2_D2		83
+#define CLK_TOP_MSDCPLL2_D4		84
+#define CLK_TOP_CLK26M_D2		85
+#define CLK_TOP_D2A_ULCLK_6P5M		86
+#define CLK_TOP_VPLL3_DPIX		87
+#define CLK_TOP_VPLL_DPIX		88
+#define CLK_TOP_LTEPLL_FS26M		89
+#define CLK_TOP_DMPLL			90
+#define CLK_TOP_DSI0_LNTC		91
+#define CLK_TOP_DSI1_LNTC		92
+#define CLK_TOP_LVDSTX3_CLKDIG_CTS	93
+#define CLK_TOP_LVDSTX_CLKDIG_CTS	94
+#define CLK_TOP_CLKRTC_EXT		95
+#define CLK_TOP_CLKRTC_INT		96
+#define CLK_TOP_CSI0			97
+#define CLK_TOP_CVBSPLL			98
+#define CLK_TOP_AXI_SEL			99
+#define CLK_TOP_MEM_SEL			100
+#define CLK_TOP_MM_SEL			101
+#define CLK_TOP_PWM_SEL			102
+#define CLK_TOP_VDEC_SEL		103
+#define CLK_TOP_VENC_SEL		104
+#define CLK_TOP_MFG_SEL			105
+#define CLK_TOP_CAMTG_SEL		106
+#define CLK_TOP_UART_SEL		107
+#define CLK_TOP_SPI_SEL			108
+#define CLK_TOP_USB20_SEL		109
+#define CLK_TOP_USB30_SEL		110
+#define CLK_TOP_MSDC50_0_HCLK_SEL	111
+#define CLK_TOP_MSDC50_0_SEL		112
+#define CLK_TOP_MSDC30_1_SEL		113
+#define CLK_TOP_MSDC30_2_SEL		114
+#define CLK_TOP_MSDC30_3_SEL		115
+#define CLK_TOP_AUDIO_SEL		116
+#define CLK_TOP_AUD_INTBUS_SEL		117
+#define CLK_TOP_PMICSPI_SEL		118
+#define CLK_TOP_DPILVDS1_SEL		119
+#define CLK_TOP_ATB_SEL			120
+#define CLK_TOP_NR_SEL			121
+#define CLK_TOP_NFI2X_SEL		122
+#define CLK_TOP_IRDA_SEL		123
+#define CLK_TOP_CCI400_SEL		124
+#define CLK_TOP_AUD_1_SEL		125
+#define CLK_TOP_AUD_2_SEL		126
+#define CLK_TOP_MEM_MFG_IN_AS_SEL	127
+#define CLK_TOP_AXI_MFG_IN_AS_SEL	128
+#define CLK_TOP_SCAM_SEL		129
+#define CLK_TOP_NFIECC_SEL		130
+#define CLK_TOP_PE2_MAC_P0_SEL		131
+#define CLK_TOP_PE2_MAC_P1_SEL		132
+#define CLK_TOP_DPILVDS_SEL		133
+#define CLK_TOP_MSDC50_3_HCLK_SEL	134
+#define CLK_TOP_HDCP_SEL		135
+#define CLK_TOP_HDCP_24M_SEL		136
+#define CLK_TOP_RTC_SEL			137
+#define CLK_TOP_SPINOR_SEL		138
+#define CLK_TOP_APLL_SEL		139
+#define CLK_TOP_APLL2_SEL		140
+#define CLK_TOP_A1SYS_HP_SEL		141
+#define CLK_TOP_A2SYS_HP_SEL		142
+#define CLK_TOP_ASM_L_SEL		143
+#define CLK_TOP_ASM_M_SEL		144
+#define CLK_TOP_ASM_H_SEL		145
+#define CLK_TOP_I2SO1_SEL		146
+#define CLK_TOP_I2SO2_SEL		147
+#define CLK_TOP_I2SO3_SEL		148
+#define CLK_TOP_TDMO0_SEL		149
+#define CLK_TOP_TDMO1_SEL		150
+#define CLK_TOP_I2SI1_SEL		151
+#define CLK_TOP_I2SI2_SEL		152
+#define CLK_TOP_I2SI3_SEL		153
+#define CLK_TOP_ETHER_125M_SEL		154
+#define CLK_TOP_ETHER_50M_SEL		155
+#define CLK_TOP_JPGDEC_SEL		156
+#define CLK_TOP_SPISLV_SEL		157
+#define CLK_TOP_ETHER_50M_RMII_SEL	158
+#define CLK_TOP_CAM2TG_SEL		159
+#define CLK_TOP_DI_SEL			160
+#define CLK_TOP_TVD_SEL			161
+#define CLK_TOP_I2C_SEL			162
+#define CLK_TOP_PWM_INFRA_SEL		163
+#define CLK_TOP_MSDC0P_AES_SEL		164
+#define CLK_TOP_CMSYS_SEL		165
+#define CLK_TOP_GCPU_SEL		166
+#define CLK_TOP_AUD_APLL1_SEL		167
+#define CLK_TOP_AUD_APLL2_SEL		168
+#define CLK_TOP_DA_AUDULL_VTX_6P5M_SEL	169
+#define CLK_TOP_APLL_DIV0		170
+#define CLK_TOP_APLL_DIV1		171
+#define CLK_TOP_APLL_DIV2		172
+#define CLK_TOP_APLL_DIV3		173
+#define CLK_TOP_APLL_DIV4		174
+#define CLK_TOP_APLL_DIV5		175
+#define CLK_TOP_APLL_DIV6		176
+#define CLK_TOP_APLL_DIV7		177
+#define CLK_TOP_APLL_DIV_PDN0		178
+#define CLK_TOP_APLL_DIV_PDN1		179
+#define CLK_TOP_APLL_DIV_PDN2		180
+#define CLK_TOP_APLL_DIV_PDN3		181
+#define CLK_TOP_APLL_DIV_PDN4		182
+#define CLK_TOP_APLL_DIV_PDN5		183
+#define CLK_TOP_APLL_DIV_PDN6		184
+#define CLK_TOP_APLL_DIV_PDN7		185
+#define CLK_TOP_APLL1_D3		186
+#define CLK_TOP_APLL1_REF_SEL		187
+#define CLK_TOP_APLL2_REF_SEL		188
+#define CLK_TOP_NFI2X_EN		189
+#define CLK_TOP_NFIECC_EN		190
+#define CLK_TOP_NFI1X_CK_EN		191
+#define CLK_TOP_NR_CLK			192
+
+/* INFRACFG */
+
+#define CLK_INFRA_DBGCLK		0
+#define CLK_INFRA_GCE			1
+#define CLK_INFRA_M4U			2
+#define CLK_INFRA_KP			3
+#define CLK_INFRA_AO_SPI0		4
+#define CLK_INFRA_AO_SPI1		5
+#define CLK_INFRA_AO_UART5		6
+#define CLK_INFRA_NR_CLK		7
+
+/* PERICFG */
+
+#define CLK_PERI_NFI			0
+#define CLK_PERI_THERM			1
+#define CLK_PERI_PWM0			2
+#define CLK_PERI_PWM1			3
+#define CLK_PERI_PWM2			4
+#define CLK_PERI_PWM3			5
+#define CLK_PERI_PWM4			6
+#define CLK_PERI_PWM5			7
+#define CLK_PERI_PWM6			8
+#define CLK_PERI_PWM7			9
+#define CLK_PERI_PWM			10
+#define CLK_PERI_AP_DMA			11
+#define CLK_PERI_MSDC30_0		12
+#define CLK_PERI_MSDC30_1		13
+#define CLK_PERI_MSDC30_2		14
+#define CLK_PERI_MSDC30_3		15
+#define CLK_PERI_UART0			16
+#define CLK_PERI_UART1			17
+#define CLK_PERI_UART2			18
+#define CLK_PERI_UART3			19
+#define CLK_PERI_I2C0			20
+#define CLK_PERI_I2C1			21
+#define CLK_PERI_I2C2			22
+#define CLK_PERI_I2C3			23
+#define CLK_PERI_I2C4			24
+#define CLK_PERI_AUXADC			25
+#define CLK_PERI_SPI0			26
+#define CLK_PERI_SPI			27
+#define CLK_PERI_I2C5			28
+#define CLK_PERI_SPI2			29
+#define CLK_PERI_SPI3			30
+#define CLK_PERI_SPI5			31
+#define CLK_PERI_UART4			32
+#define CLK_PERI_SFLASH			33
+#define CLK_PERI_GMAC			34
+#define CLK_PERI_PCIE0			35
+#define CLK_PERI_PCIE1			36
+#define CLK_PERI_GMAC_PCLK		37
+#define CLK_PERI_MSDC50_0_EN		38
+#define CLK_PERI_MSDC30_1_EN		39
+#define CLK_PERI_MSDC30_2_EN		40
+#define CLK_PERI_MSDC30_3_EN		41
+#define CLK_PERI_MSDC50_0_HCLK_EN	42
+#define CLK_PERI_MSDC50_3_HCLK_EN	43
+#define CLK_PERI_MSDC30_0_QTR_EN	44
+#define CLK_PERI_MSDC30_3_QTR_EN	45
+#define CLK_PERI_NR_CLK			46
+
+/* MCUCFG */
+
+#define CLK_MCU_MP0_SEL			0
+#define CLK_MCU_MP2_SEL			1
+#define CLK_MCU_BUS_SEL			2
+#define CLK_MCU_NR_CLK			3
+
+/* MFGCFG */
+
+#define CLK_MFG_BG3D			0
+#define CLK_MFG_NR_CLK			1
+
+/* MMSYS */
+
+#define CLK_MM_SMI_COMMON		0
+#define CLK_MM_SMI_LARB0		1
+#define CLK_MM_CAM_MDP			2
+#define CLK_MM_MDP_RDMA0		3
+#define CLK_MM_MDP_RDMA1		4
+#define CLK_MM_MDP_RSZ0			5
+#define CLK_MM_MDP_RSZ1			6
+#define CLK_MM_MDP_RSZ2			7
+#define CLK_MM_MDP_TDSHP0		8
+#define CLK_MM_MDP_TDSHP1		9
+#define CLK_MM_MDP_CROP			10
+#define CLK_MM_MDP_WDMA			11
+#define CLK_MM_MDP_WROT0		12
+#define CLK_MM_MDP_WROT1		13
+#define CLK_MM_FAKE_ENG			14
+#define CLK_MM_MUTEX_32K		15
+#define CLK_MM_DISP_OVL0		16
+#define CLK_MM_DISP_OVL1		17
+#define CLK_MM_DISP_RDMA0		18
+#define CLK_MM_DISP_RDMA1		19
+#define CLK_MM_DISP_RDMA2		20
+#define CLK_MM_DISP_WDMA0		21
+#define CLK_MM_DISP_WDMA1		22
+#define CLK_MM_DISP_COLOR0		23
+#define CLK_MM_DISP_COLOR1		24
+#define CLK_MM_DISP_AAL			25
+#define CLK_MM_DISP_GAMMA		26
+#define CLK_MM_DISP_UFOE		27
+#define CLK_MM_DISP_SPLIT0		28
+#define CLK_MM_DISP_OD			29
+#define CLK_MM_DISP_PWM0_MM		30
+#define CLK_MM_DISP_PWM0_26M		31
+#define CLK_MM_DISP_PWM1_MM		32
+#define CLK_MM_DISP_PWM1_26M		33
+#define CLK_MM_DSI0_ENGINE		34
+#define CLK_MM_DSI0_DIGITAL		35
+#define CLK_MM_DSI1_ENGINE		36
+#define CLK_MM_DSI1_DIGITAL		37
+#define CLK_MM_DPI_PIXEL		38
+#define CLK_MM_DPI_ENGINE		39
+#define CLK_MM_DPI1_PIXEL		40
+#define CLK_MM_DPI1_ENGINE		41
+#define CLK_MM_LVDS_PIXEL		42
+#define CLK_MM_LVDS_CTS			43
+#define CLK_MM_SMI_LARB4		44
+#define CLK_MM_SMI_COMMON1		45
+#define CLK_MM_SMI_LARB5		46
+#define CLK_MM_MDP_RDMA2		47
+#define CLK_MM_MDP_TDSHP2		48
+#define CLK_MM_DISP_OVL2		49
+#define CLK_MM_DISP_WDMA2		50
+#define CLK_MM_DISP_COLOR2		51
+#define CLK_MM_DISP_AAL1		52
+#define CLK_MM_DISP_OD1			53
+#define CLK_MM_LVDS1_PIXEL		54
+#define CLK_MM_LVDS1_CTS		55
+#define CLK_MM_SMI_LARB7		56
+#define CLK_MM_MDP_RDMA3		57
+#define CLK_MM_MDP_WROT2		58
+#define CLK_MM_DSI2			59
+#define CLK_MM_DSI2_DIGITAL		60
+#define CLK_MM_DSI3			61
+#define CLK_MM_DSI3_DIGITAL		62
+#define CLK_MM_NR_CLK			63
+
+/* IMGSYS */
+
+#define CLK_IMG_SMI_LARB2		0
+#define CLK_IMG_SENINF_SCAM_EN		1
+#define CLK_IMG_SENINF_CAM_EN		2
+#define CLK_IMG_CAM_SV_EN		3
+#define CLK_IMG_CAM_SV1_EN		4
+#define CLK_IMG_CAM_SV2_EN		5
+#define CLK_IMG_NR_CLK			6
+
+/* BDPSYS */
+
+#define CLK_BDP_BRIDGE_B		0
+#define CLK_BDP_BRIDGE_DRAM		1
+#define CLK_BDP_LARB_DRAM		2
+#define CLK_BDP_WR_CHANNEL_VDI_PXL	3
+#define CLK_BDP_WR_CHANNEL_VDI_DRAM	4
+#define CLK_BDP_WR_CHANNEL_VDI_B	5
+#define CLK_BDP_MT_B			6
+#define CLK_BDP_DISPFMT_27M		7
+#define CLK_BDP_DISPFMT_27M_VDOUT	8
+#define CLK_BDP_DISPFMT_27_74_74	9
+#define CLK_BDP_DISPFMT_2FS		10
+#define CLK_BDP_DISPFMT_2FS_2FS74_148	11
+#define CLK_BDP_DISPFMT_B		12
+#define CLK_BDP_VDO_DRAM		13
+#define CLK_BDP_VDO_2FS			14
+#define CLK_BDP_VDO_B			15
+#define CLK_BDP_WR_CHANNEL_DI_PXL	16
+#define CLK_BDP_WR_CHANNEL_DI_DRAM	17
+#define CLK_BDP_WR_CHANNEL_DI_B		18
+#define CLK_BDP_NR_AGENT		19
+#define CLK_BDP_NR_DRAM			20
+#define CLK_BDP_NR_B			21
+#define CLK_BDP_BRIDGE_RT_B		22
+#define CLK_BDP_BRIDGE_RT_DRAM		23
+#define CLK_BDP_LARB_RT_DRAM		24
+#define CLK_BDP_TVD_TDC			25
+#define CLK_BDP_TVD_54			26
+#define CLK_BDP_TVD_CBUS		27
+#define CLK_BDP_NR_CLK			28
+
+/* VDECSYS */
+
+#define CLK_VDEC_CKEN			0
+#define CLK_VDEC_LARB1_CKEN		1
+#define CLK_VDEC_IMGRZ_CKEN		2
+#define CLK_VDEC_NR_CLK			3
+
+/* VENCSYS */
+
+#define CLK_VENC_SMI_COMMON_CON		0
+#define CLK_VENC_VENC			1
+#define CLK_VENC_SMI_LARB6		2
+#define CLK_VENC_NR_CLK			3
+
+/* JPGDECSYS */
+
+#define CLK_JPGDEC_JPGDEC1		0
+#define CLK_JPGDEC_JPGDEC		1
+#define CLK_JPGDEC_NR_CLK		2
+
+#endif /* _DT_BINDINGS_CLK_MT2712_H */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/mt6797-clk.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/mt6797-clk.h
new file mode 100644
index 0000000000000000000000000000000000000000..2f25a5aca01992fa32aa421bb3c5c8c6b3120b38
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/mt6797-clk.h
@@ -0,0 +1,281 @@
+/*
+ * Copyright (c) 2017 MediaTek Inc.
+ * Author: Kevin Chen <kevin-cw.chen@mediatek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_CLK_MT6797_H
+#define _DT_BINDINGS_CLK_MT6797_H
+
+/* TOPCKGEN */
+#define	CLK_TOP_MUX_ULPOSC_AXI_CK_MUX_PRE	1
+#define	CLK_TOP_MUX_ULPOSC_AXI_CK_MUX		2
+#define	CLK_TOP_MUX_AXI				3
+#define	CLK_TOP_MUX_MEM				4
+#define	CLK_TOP_MUX_DDRPHYCFG			5
+#define	CLK_TOP_MUX_MM				6
+#define	CLK_TOP_MUX_PWM				7
+#define	CLK_TOP_MUX_VDEC			8
+#define	CLK_TOP_MUX_VENC			9
+#define	CLK_TOP_MUX_MFG				10
+#define	CLK_TOP_MUX_CAMTG			11
+#define	CLK_TOP_MUX_UART			12
+#define	CLK_TOP_MUX_SPI				13
+#define	CLK_TOP_MUX_ULPOSC_SPI_CK_MUX		14
+#define	CLK_TOP_MUX_USB20			15
+#define	CLK_TOP_MUX_MSDC50_0_HCLK		16
+#define	CLK_TOP_MUX_MSDC50_0			17
+#define	CLK_TOP_MUX_MSDC30_1			18
+#define	CLK_TOP_MUX_MSDC30_2			19
+#define	CLK_TOP_MUX_AUDIO			20
+#define	CLK_TOP_MUX_AUD_INTBUS			21
+#define	CLK_TOP_MUX_PMICSPI			22
+#define	CLK_TOP_MUX_SCP				23
+#define	CLK_TOP_MUX_ATB				24
+#define	CLK_TOP_MUX_MJC				25
+#define	CLK_TOP_MUX_DPI0			26
+#define	CLK_TOP_MUX_AUD_1			27
+#define	CLK_TOP_MUX_AUD_2			28
+#define	CLK_TOP_MUX_SSUSB_TOP_SYS		29
+#define	CLK_TOP_MUX_SPM				30
+#define	CLK_TOP_MUX_BSI_SPI			31
+#define	CLK_TOP_MUX_AUDIO_H			32
+#define	CLK_TOP_MUX_ANC_MD32			33
+#define	CLK_TOP_MUX_MFG_52M			34
+#define	CLK_TOP_SYSPLL_CK			35
+#define	CLK_TOP_SYSPLL_D2			36
+#define	CLK_TOP_SYSPLL1_D2			37
+#define	CLK_TOP_SYSPLL1_D4			38
+#define	CLK_TOP_SYSPLL1_D8			39
+#define	CLK_TOP_SYSPLL1_D16			40
+#define	CLK_TOP_SYSPLL_D3			41
+#define	CLK_TOP_SYSPLL_D3_D3			42
+#define	CLK_TOP_SYSPLL2_D2			43
+#define	CLK_TOP_SYSPLL2_D4			44
+#define	CLK_TOP_SYSPLL2_D8			45
+#define	CLK_TOP_SYSPLL_D5			46
+#define	CLK_TOP_SYSPLL3_D2			47
+#define	CLK_TOP_SYSPLL3_D4			48
+#define	CLK_TOP_SYSPLL_D7			49
+#define	CLK_TOP_SYSPLL4_D2			50
+#define	CLK_TOP_SYSPLL4_D4			51
+#define	CLK_TOP_UNIVPLL_CK			52
+#define	CLK_TOP_UNIVPLL_D7			53
+#define	CLK_TOP_UNIVPLL_D26			54
+#define	CLK_TOP_SSUSB_PHY_48M_CK		55
+#define	CLK_TOP_USB_PHY48M_CK			56
+#define	CLK_TOP_UNIVPLL_D2			57
+#define	CLK_TOP_UNIVPLL1_D2			58
+#define	CLK_TOP_UNIVPLL1_D4			59
+#define	CLK_TOP_UNIVPLL1_D8			60
+#define	CLK_TOP_UNIVPLL_D3			61
+#define	CLK_TOP_UNIVPLL2_D2			62
+#define	CLK_TOP_UNIVPLL2_D4			63
+#define	CLK_TOP_UNIVPLL2_D8			64
+#define	CLK_TOP_UNIVPLL_D5			65
+#define	CLK_TOP_UNIVPLL3_D2			66
+#define	CLK_TOP_UNIVPLL3_D4			67
+#define	CLK_TOP_UNIVPLL3_D8			68
+#define	CLK_TOP_ULPOSC_CK_ORG			69
+#define	CLK_TOP_ULPOSC_CK			70
+#define	CLK_TOP_ULPOSC_D2			71
+#define	CLK_TOP_ULPOSC_D3			72
+#define	CLK_TOP_ULPOSC_D4			73
+#define	CLK_TOP_ULPOSC_D8			74
+#define	CLK_TOP_ULPOSC_D10			75
+#define	CLK_TOP_APLL1_CK			76
+#define	CLK_TOP_APLL2_CK			77
+#define	CLK_TOP_MFGPLL_CK			78
+#define	CLK_TOP_MFGPLL_D2			79
+#define	CLK_TOP_IMGPLL_CK			80
+#define	CLK_TOP_IMGPLL_D2			81
+#define	CLK_TOP_IMGPLL_D4			82
+#define	CLK_TOP_CODECPLL_CK			83
+#define	CLK_TOP_CODECPLL_D2			84
+#define	CLK_TOP_VDECPLL_CK			85
+#define	CLK_TOP_TVDPLL_CK			86
+#define	CLK_TOP_TVDPLL_D2			87
+#define	CLK_TOP_TVDPLL_D4			88
+#define	CLK_TOP_TVDPLL_D8			89
+#define	CLK_TOP_TVDPLL_D16			90
+#define	CLK_TOP_MSDCPLL_CK			91
+#define	CLK_TOP_MSDCPLL_D2			92
+#define	CLK_TOP_MSDCPLL_D4			93
+#define	CLK_TOP_MSDCPLL_D8			94
+#define	CLK_TOP_NR				95
+
+/* APMIXED_SYS */
+#define CLK_APMIXED_MAINPLL			1
+#define CLK_APMIXED_UNIVPLL			2
+#define CLK_APMIXED_MFGPLL			3
+#define CLK_APMIXED_MSDCPLL			4
+#define CLK_APMIXED_IMGPLL			5
+#define CLK_APMIXED_TVDPLL			6
+#define CLK_APMIXED_CODECPLL			7
+#define CLK_APMIXED_VDECPLL			8
+#define CLK_APMIXED_APLL1			9
+#define CLK_APMIXED_APLL2			10
+#define CLK_APMIXED_NR				11
+
+/* INFRA_SYS */
+#define	CLK_INFRA_PMIC_TMR			1
+#define	CLK_INFRA_PMIC_AP			2
+#define	CLK_INFRA_PMIC_MD			3
+#define	CLK_INFRA_PMIC_CONN			4
+#define	CLK_INFRA_SCP				5
+#define	CLK_INFRA_SEJ				6
+#define	CLK_INFRA_APXGPT			7
+#define	CLK_INFRA_SEJ_13M			8
+#define	CLK_INFRA_ICUSB				9
+#define	CLK_INFRA_GCE				10
+#define	CLK_INFRA_THERM				11
+#define	CLK_INFRA_I2C0				12
+#define	CLK_INFRA_I2C1				13
+#define	CLK_INFRA_I2C2				14
+#define	CLK_INFRA_I2C3				15
+#define	CLK_INFRA_PWM_HCLK			16
+#define	CLK_INFRA_PWM1				17
+#define	CLK_INFRA_PWM2				18
+#define	CLK_INFRA_PWM3				19
+#define	CLK_INFRA_PWM4				20
+#define	CLK_INFRA_PWM				21
+#define	CLK_INFRA_UART0				22
+#define	CLK_INFRA_UART1				23
+#define	CLK_INFRA_UART2				24
+#define	CLK_INFRA_UART3				25
+#define	CLK_INFRA_MD2MD_CCIF_0			26
+#define	CLK_INFRA_MD2MD_CCIF_1			27
+#define	CLK_INFRA_MD2MD_CCIF_2			28
+#define	CLK_INFRA_FHCTL				29
+#define	CLK_INFRA_BTIF				30
+#define	CLK_INFRA_MD2MD_CCIF_3			31
+#define	CLK_INFRA_SPI				32
+#define	CLK_INFRA_MSDC0				33
+#define	CLK_INFRA_MD2MD_CCIF_4			34
+#define	CLK_INFRA_MSDC1				35
+#define	CLK_INFRA_MSDC2				36
+#define	CLK_INFRA_MD2MD_CCIF_5			37
+#define	CLK_INFRA_GCPU				38
+#define	CLK_INFRA_TRNG				39
+#define	CLK_INFRA_AUXADC			40
+#define	CLK_INFRA_CPUM				41
+#define	CLK_INFRA_AP_C2K_CCIF_0			42
+#define	CLK_INFRA_AP_C2K_CCIF_1			43
+#define	CLK_INFRA_CLDMA				44
+#define	CLK_INFRA_DISP_PWM			45
+#define	CLK_INFRA_AP_DMA			46
+#define	CLK_INFRA_DEVICE_APC			47
+#define	CLK_INFRA_L2C_SRAM			48
+#define	CLK_INFRA_CCIF_AP			49
+#define	CLK_INFRA_AUDIO				50
+#define	CLK_INFRA_CCIF_MD			51
+#define	CLK_INFRA_DRAMC_F26M			52
+#define	CLK_INFRA_I2C4				53
+#define	CLK_INFRA_I2C_APPM			54
+#define	CLK_INFRA_I2C_GPUPM			55
+#define	CLK_INFRA_I2C2_IMM			56
+#define	CLK_INFRA_I2C2_ARB			57
+#define	CLK_INFRA_I2C3_IMM			58
+#define	CLK_INFRA_I2C3_ARB			59
+#define	CLK_INFRA_I2C5				60
+#define	CLK_INFRA_SYS_CIRQ			61
+#define	CLK_INFRA_SPI1				62
+#define	CLK_INFRA_DRAMC_B_F26M			63
+#define	CLK_INFRA_ANC_MD32			64
+#define	CLK_INFRA_ANC_MD32_32K			65
+#define	CLK_INFRA_DVFS_SPM1			66
+#define	CLK_INFRA_AES_TOP0			67
+#define	CLK_INFRA_AES_TOP1			68
+#define	CLK_INFRA_SSUSB_BUS			69
+#define	CLK_INFRA_SPI2				70
+#define	CLK_INFRA_SPI3				71
+#define	CLK_INFRA_SPI4				72
+#define	CLK_INFRA_SPI5				73
+#define	CLK_INFRA_IRTX				74
+#define	CLK_INFRA_SSUSB_SYS			75
+#define	CLK_INFRA_SSUSB_REF			76
+#define	CLK_INFRA_AUDIO_26M			77
+#define	CLK_INFRA_AUDIO_26M_PAD_TOP		78
+#define	CLK_INFRA_MODEM_TEMP_SHARE		79
+#define	CLK_INFRA_VAD_WRAP_SOC			80
+#define	CLK_INFRA_DRAMC_CONF			81
+#define	CLK_INFRA_DRAMC_B_CONF			82
+#define	CLK_INFRA_MFG_VCG			83
+#define	CLK_INFRA_13M				84
+#define	CLK_INFRA_NR				85
+
+/* IMG_SYS */
+#define	CLK_IMG_FDVT				1
+#define	CLK_IMG_DPE				2
+#define	CLK_IMG_DIP				3
+#define	CLK_IMG_LARB6				4
+#define	CLK_IMG_NR				5
+
+/* MM_SYS */
+#define	CLK_MM_SMI_COMMON			1
+#define	CLK_MM_SMI_LARB0			2
+#define	CLK_MM_SMI_LARB5			3
+#define	CLK_MM_CAM_MDP				4
+#define	CLK_MM_MDP_RDMA0			5
+#define	CLK_MM_MDP_RDMA1			6
+#define	CLK_MM_MDP_RSZ0				7
+#define	CLK_MM_MDP_RSZ1				8
+#define	CLK_MM_MDP_RSZ2				9
+#define	CLK_MM_MDP_TDSHP			10
+#define	CLK_MM_MDP_COLOR			11
+#define	CLK_MM_MDP_WDMA				12
+#define	CLK_MM_MDP_WROT0			13
+#define	CLK_MM_MDP_WROT1			14
+#define	CLK_MM_FAKE_ENG				15
+#define	CLK_MM_DISP_OVL0			16
+#define	CLK_MM_DISP_OVL1			17
+#define	CLK_MM_DISP_OVL0_2L			18
+#define	CLK_MM_DISP_OVL1_2L			19
+#define	CLK_MM_DISP_RDMA0			20
+#define	CLK_MM_DISP_RDMA1			21
+#define	CLK_MM_DISP_WDMA0			22
+#define	CLK_MM_DISP_WDMA1			23
+#define	CLK_MM_DISP_COLOR			24
+#define	CLK_MM_DISP_CCORR			25
+#define	CLK_MM_DISP_AAL				26
+#define	CLK_MM_DISP_GAMMA			27
+#define	CLK_MM_DISP_OD				28
+#define	CLK_MM_DISP_DITHER			29
+#define	CLK_MM_DISP_UFOE			30
+#define	CLK_MM_DISP_DSC				31
+#define	CLK_MM_DISP_SPLIT			32
+#define	CLK_MM_DSI0_MM_CLOCK			33
+#define	CLK_MM_DSI1_MM_CLOCK			34
+#define	CLK_MM_DPI_MM_CLOCK			35
+#define	CLK_MM_DPI_INTERFACE_CLOCK		36
+#define	CLK_MM_LARB4_AXI_ASIF_MM_CLOCK		37
+#define	CLK_MM_LARB4_AXI_ASIF_MJC_CLOCK		38
+#define	CLK_MM_DISP_OVL0_MOUT_CLOCK		39
+#define	CLK_MM_FAKE_ENG2			40
+#define	CLK_MM_DSI0_INTERFACE_CLOCK		41
+#define	CLK_MM_DSI1_INTERFACE_CLOCK		42
+#define	CLK_MM_NR				43
+
+/* VDEC_SYS */
+#define	CLK_VDEC_CKEN_ENG			1
+#define	CLK_VDEC_ACTIVE				2
+#define	CLK_VDEC_CKEN				3
+#define	CLK_VDEC_LARB1_CKEN			4
+#define	CLK_VDEC_NR				5
+
+/* VENC_SYS */
+#define	CLK_VENC_0				1
+#define	CLK_VENC_1				2
+#define	CLK_VENC_2				3
+#define	CLK_VENC_3				4
+#define	CLK_VENC_NR				5
+
+#endif /* _DT_BINDINGS_CLK_MT6797_H */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/mt7622-clk.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/mt7622-clk.h
new file mode 100644
index 0000000000000000000000000000000000000000..e9d77f0e8bce6fc65ff7ad30cc86a1d9c2e753e6
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/mt7622-clk.h
@@ -0,0 +1,290 @@
+/*
+ * Copyright (c) 2017 MediaTek Inc.
+ * Author: Chen Zhong <chen.zhong@mediatek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_CLK_MT7622_H
+#define _DT_BINDINGS_CLK_MT7622_H
+
+/* TOPCKGEN */
+
+#define CLK_TOP_TO_U2_PHY		0
+#define CLK_TOP_TO_U2_PHY_1P		1
+#define CLK_TOP_PCIE0_PIPE_EN		2
+#define CLK_TOP_PCIE1_PIPE_EN		3
+#define CLK_TOP_SSUSB_TX250M		4
+#define CLK_TOP_SSUSB_EQ_RX250M		5
+#define CLK_TOP_SSUSB_CDR_REF		6
+#define CLK_TOP_SSUSB_CDR_FB		7
+#define CLK_TOP_SATA_ASIC		8
+#define CLK_TOP_SATA_RBC		9
+#define CLK_TOP_TO_USB3_SYS		10
+#define CLK_TOP_P1_1MHZ			11
+#define CLK_TOP_4MHZ			12
+#define CLK_TOP_P0_1MHZ			13
+#define CLK_TOP_TXCLK_SRC_PRE		14
+#define CLK_TOP_RTC			15
+#define CLK_TOP_MEMPLL			16
+#define CLK_TOP_DMPLL			17
+#define CLK_TOP_SYSPLL_D2		18
+#define CLK_TOP_SYSPLL1_D2		19
+#define CLK_TOP_SYSPLL1_D4		20
+#define CLK_TOP_SYSPLL1_D8		21
+#define CLK_TOP_SYSPLL2_D4		22
+#define CLK_TOP_SYSPLL2_D8		23
+#define CLK_TOP_SYSPLL_D5		24
+#define CLK_TOP_SYSPLL3_D2		25
+#define CLK_TOP_SYSPLL3_D4		26
+#define CLK_TOP_SYSPLL4_D2		27
+#define CLK_TOP_SYSPLL4_D4		28
+#define CLK_TOP_SYSPLL4_D16		29
+#define CLK_TOP_UNIVPLL			30
+#define CLK_TOP_UNIVPLL_D2		31
+#define CLK_TOP_UNIVPLL1_D2		32
+#define CLK_TOP_UNIVPLL1_D4		33
+#define CLK_TOP_UNIVPLL1_D8		34
+#define CLK_TOP_UNIVPLL1_D16		35
+#define CLK_TOP_UNIVPLL2_D2		36
+#define CLK_TOP_UNIVPLL2_D4		37
+#define CLK_TOP_UNIVPLL2_D8		38
+#define CLK_TOP_UNIVPLL2_D16		39
+#define CLK_TOP_UNIVPLL_D5		40
+#define CLK_TOP_UNIVPLL3_D2		41
+#define CLK_TOP_UNIVPLL3_D4		42
+#define CLK_TOP_UNIVPLL3_D16		43
+#define CLK_TOP_UNIVPLL_D7		44
+#define CLK_TOP_UNIVPLL_D80_D4		45
+#define CLK_TOP_UNIV48M			46
+#define CLK_TOP_SGMIIPLL		47
+#define CLK_TOP_SGMIIPLL_D2		48
+#define CLK_TOP_AUD1PLL			49
+#define CLK_TOP_AUD2PLL			50
+#define CLK_TOP_AUD_I2S2_MCK		51
+#define CLK_TOP_TO_USB3_REF		52
+#define CLK_TOP_PCIE1_MAC_EN		53
+#define CLK_TOP_PCIE0_MAC_EN		54
+#define CLK_TOP_ETH_500M		55
+#define CLK_TOP_AXI_SEL			56
+#define CLK_TOP_MEM_SEL			57
+#define CLK_TOP_DDRPHYCFG_SEL		58
+#define CLK_TOP_ETH_SEL			59
+#define CLK_TOP_PWM_SEL			60
+#define CLK_TOP_F10M_REF_SEL		61
+#define CLK_TOP_NFI_INFRA_SEL		62
+#define CLK_TOP_FLASH_SEL		63
+#define CLK_TOP_UART_SEL		64
+#define CLK_TOP_SPI0_SEL		65
+#define CLK_TOP_SPI1_SEL		66
+#define CLK_TOP_MSDC50_0_SEL		67
+#define CLK_TOP_MSDC30_0_SEL		68
+#define CLK_TOP_MSDC30_1_SEL		69
+#define CLK_TOP_A1SYS_HP_SEL		70
+#define CLK_TOP_A2SYS_HP_SEL		71
+#define CLK_TOP_INTDIR_SEL		72
+#define CLK_TOP_AUD_INTBUS_SEL		73
+#define CLK_TOP_PMICSPI_SEL		74
+#define CLK_TOP_SCP_SEL			75
+#define CLK_TOP_ATB_SEL			76
+#define CLK_TOP_HIF_SEL			77
+#define CLK_TOP_AUDIO_SEL		78
+#define CLK_TOP_U2_SEL			79
+#define CLK_TOP_AUD1_SEL		80
+#define CLK_TOP_AUD2_SEL		81
+#define CLK_TOP_IRRX_SEL		82
+#define CLK_TOP_IRTX_SEL		83
+#define CLK_TOP_ASM_L_SEL		84
+#define CLK_TOP_ASM_M_SEL		85
+#define CLK_TOP_ASM_H_SEL		86
+#define CLK_TOP_APLL1_SEL		87
+#define CLK_TOP_APLL2_SEL		88
+#define CLK_TOP_I2S0_MCK_SEL		89
+#define CLK_TOP_I2S1_MCK_SEL		90
+#define CLK_TOP_I2S2_MCK_SEL		91
+#define CLK_TOP_I2S3_MCK_SEL		92
+#define CLK_TOP_APLL1_DIV		93
+#define CLK_TOP_APLL2_DIV		94
+#define CLK_TOP_I2S0_MCK_DIV		95
+#define CLK_TOP_I2S1_MCK_DIV		96
+#define CLK_TOP_I2S2_MCK_DIV		97
+#define CLK_TOP_I2S3_MCK_DIV		98
+#define CLK_TOP_A1SYS_HP_DIV		99
+#define CLK_TOP_A2SYS_HP_DIV		100
+#define CLK_TOP_APLL1_DIV_PD		101
+#define CLK_TOP_APLL2_DIV_PD		102
+#define CLK_TOP_I2S0_MCK_DIV_PD		103
+#define CLK_TOP_I2S1_MCK_DIV_PD		104
+#define CLK_TOP_I2S2_MCK_DIV_PD		105
+#define CLK_TOP_I2S3_MCK_DIV_PD		106
+#define CLK_TOP_A1SYS_HP_DIV_PD		107
+#define CLK_TOP_A2SYS_HP_DIV_PD		108
+#define CLK_TOP_NR_CLK			109
+
+/* INFRACFG */
+
+#define CLK_INFRA_MUX1_SEL		0
+#define CLK_INFRA_DBGCLK_PD		1
+#define CLK_INFRA_AUDIO_PD		2
+#define CLK_INFRA_IRRX_PD		3
+#define CLK_INFRA_APXGPT_PD		4
+#define CLK_INFRA_PMIC_PD		5
+#define CLK_INFRA_TRNG			6
+#define CLK_INFRA_NR_CLK		7
+
+/* PERICFG */
+
+#define CLK_PERIBUS_SEL			0
+#define CLK_PERI_THERM_PD		1
+#define CLK_PERI_PWM1_PD		2
+#define CLK_PERI_PWM2_PD		3
+#define CLK_PERI_PWM3_PD		4
+#define CLK_PERI_PWM4_PD		5
+#define CLK_PERI_PWM5_PD		6
+#define CLK_PERI_PWM6_PD		7
+#define CLK_PERI_PWM7_PD		8
+#define CLK_PERI_PWM_PD			9
+#define CLK_PERI_AP_DMA_PD		10
+#define CLK_PERI_MSDC30_0_PD		11
+#define CLK_PERI_MSDC30_1_PD		12
+#define CLK_PERI_UART0_PD		13
+#define CLK_PERI_UART1_PD		14
+#define CLK_PERI_UART2_PD		15
+#define CLK_PERI_UART3_PD		16
+#define CLK_PERI_UART4_PD		17
+#define CLK_PERI_BTIF_PD		18
+#define CLK_PERI_I2C0_PD		19
+#define CLK_PERI_I2C1_PD		20
+#define CLK_PERI_I2C2_PD		21
+#define CLK_PERI_SPI1_PD		22
+#define CLK_PERI_AUXADC_PD		23
+#define CLK_PERI_SPI0_PD		24
+#define CLK_PERI_SNFI_PD		25
+#define CLK_PERI_NFI_PD			26
+#define CLK_PERI_NFIECC_PD		27
+#define CLK_PERI_FLASH_PD		28
+#define CLK_PERI_IRTX_PD		29
+#define CLK_PERI_NR_CLK			30
+
+/* APMIXEDSYS */
+
+#define CLK_APMIXED_ARMPLL		0
+#define CLK_APMIXED_MAINPLL		1
+#define CLK_APMIXED_UNIV2PLL		2
+#define CLK_APMIXED_ETH1PLL		3
+#define CLK_APMIXED_ETH2PLL		4
+#define CLK_APMIXED_AUD1PLL		5
+#define CLK_APMIXED_AUD2PLL		6
+#define CLK_APMIXED_TRGPLL		7
+#define CLK_APMIXED_SGMIPLL		8
+#define CLK_APMIXED_MAIN_CORE_EN	9
+#define CLK_APMIXED_NR_CLK		10
+
+/* AUDIOSYS */
+
+#define CLK_AUDIO_AFE			0
+#define CLK_AUDIO_HDMI			1
+#define CLK_AUDIO_SPDF			2
+#define CLK_AUDIO_APLL			3
+#define CLK_AUDIO_I2SIN1		4
+#define CLK_AUDIO_I2SIN2		5
+#define CLK_AUDIO_I2SIN3		6
+#define CLK_AUDIO_I2SIN4		7
+#define CLK_AUDIO_I2SO1			8
+#define CLK_AUDIO_I2SO2			9
+#define CLK_AUDIO_I2SO3			10
+#define CLK_AUDIO_I2SO4			11
+#define CLK_AUDIO_ASRCI1		12
+#define CLK_AUDIO_ASRCI2		13
+#define CLK_AUDIO_ASRCO1		14
+#define CLK_AUDIO_ASRCO2		15
+#define CLK_AUDIO_INTDIR		16
+#define CLK_AUDIO_A1SYS			17
+#define CLK_AUDIO_A2SYS			18
+#define CLK_AUDIO_UL1			19
+#define CLK_AUDIO_UL2			20
+#define CLK_AUDIO_UL3			21
+#define CLK_AUDIO_UL4			22
+#define CLK_AUDIO_UL5			23
+#define CLK_AUDIO_UL6			24
+#define CLK_AUDIO_DL1			25
+#define CLK_AUDIO_DL2			26
+#define CLK_AUDIO_DL3			27
+#define CLK_AUDIO_DL4			28
+#define CLK_AUDIO_DL5			29
+#define CLK_AUDIO_DL6			30
+#define CLK_AUDIO_DLMCH			31
+#define CLK_AUDIO_ARB1			32
+#define CLK_AUDIO_AWB			33
+#define CLK_AUDIO_AWB2			34
+#define CLK_AUDIO_DAI			35
+#define CLK_AUDIO_MOD			36
+#define CLK_AUDIO_ASRCI3		37
+#define CLK_AUDIO_ASRCI4		38
+#define CLK_AUDIO_ASRCO3		39
+#define CLK_AUDIO_ASRCO4		40
+#define CLK_AUDIO_MEM_ASRC1		41
+#define CLK_AUDIO_MEM_ASRC2		42
+#define CLK_AUDIO_MEM_ASRC3		43
+#define CLK_AUDIO_MEM_ASRC4		44
+#define CLK_AUDIO_MEM_ASRC5		45
+#define CLK_AUDIO_AFE_CONN		46
+#define CLK_AUDIO_NR_CLK		47
+
+/* SSUSBSYS */
+
+#define CLK_SSUSB_U2_PHY_1P_EN		0
+#define CLK_SSUSB_U2_PHY_EN		1
+#define CLK_SSUSB_REF_EN		2
+#define CLK_SSUSB_SYS_EN		3
+#define CLK_SSUSB_MCU_EN		4
+#define CLK_SSUSB_DMA_EN		5
+#define CLK_SSUSB_NR_CLK		6
+
+/* PCIESYS */
+
+#define CLK_PCIE_P1_AUX_EN		0
+#define CLK_PCIE_P1_OBFF_EN		1
+#define CLK_PCIE_P1_AHB_EN		2
+#define CLK_PCIE_P1_AXI_EN		3
+#define CLK_PCIE_P1_MAC_EN		4
+#define CLK_PCIE_P1_PIPE_EN		5
+#define CLK_PCIE_P0_AUX_EN		6
+#define CLK_PCIE_P0_OBFF_EN		7
+#define CLK_PCIE_P0_AHB_EN		8
+#define CLK_PCIE_P0_AXI_EN		9
+#define CLK_PCIE_P0_MAC_EN		10
+#define CLK_PCIE_P0_PIPE_EN		11
+#define CLK_SATA_AHB_EN			12
+#define CLK_SATA_AXI_EN			13
+#define CLK_SATA_ASIC_EN		14
+#define CLK_SATA_RBC_EN			15
+#define CLK_SATA_PM_EN			16
+#define CLK_PCIE_NR_CLK			17
+
+/* ETHSYS */
+
+#define CLK_ETH_HSDMA_EN		0
+#define CLK_ETH_ESW_EN			1
+#define CLK_ETH_GP2_EN			2
+#define CLK_ETH_GP1_EN			3
+#define CLK_ETH_GP0_EN			4
+#define CLK_ETH_NR_CLK			5
+
+/* SGMIISYS */
+
+#define CLK_SGMII_TX250M_EN		0
+#define CLK_SGMII_RX250M_EN		1
+#define CLK_SGMII_CDR_REF		2
+#define CLK_SGMII_CDR_FB		3
+#define CLK_SGMII_NR_CLK		4
+
+#endif /* _DT_BINDINGS_CLK_MT7622_H */
+
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/mt8135-clk.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/mt8135-clk.h
new file mode 100644
index 0000000000000000000000000000000000000000..6dac6c091dd29ad479b0faee396ec55f266bf428
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/mt8135-clk.h
@@ -0,0 +1,194 @@
+/*
+ * Copyright (c) 2014 MediaTek Inc.
+ * Author: James Liao <jamesjj.liao@mediatek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_CLK_MT8135_H
+#define _DT_BINDINGS_CLK_MT8135_H
+
+/* TOPCKGEN */
+
+#define CLK_TOP_DSI0_LNTC_DSICLK	1
+#define CLK_TOP_HDMITX_CLKDIG_CTS	2
+#define CLK_TOP_CLKPH_MCK		3
+#define CLK_TOP_CPUM_TCK_IN		4
+#define CLK_TOP_MAINPLL_806M		5
+#define CLK_TOP_MAINPLL_537P3M		6
+#define CLK_TOP_MAINPLL_322P4M		7
+#define CLK_TOP_MAINPLL_230P3M		8
+#define CLK_TOP_UNIVPLL_624M		9
+#define CLK_TOP_UNIVPLL_416M		10
+#define CLK_TOP_UNIVPLL_249P6M		11
+#define CLK_TOP_UNIVPLL_178P3M		12
+#define CLK_TOP_UNIVPLL_48M		13
+#define CLK_TOP_MMPLL_D2		14
+#define CLK_TOP_MMPLL_D3		15
+#define CLK_TOP_MMPLL_D5		16
+#define CLK_TOP_MMPLL_D7		17
+#define CLK_TOP_MMPLL_D4		18
+#define CLK_TOP_MMPLL_D6		19
+#define CLK_TOP_SYSPLL_D2		20
+#define CLK_TOP_SYSPLL_D4		21
+#define CLK_TOP_SYSPLL_D6		22
+#define CLK_TOP_SYSPLL_D8		23
+#define CLK_TOP_SYSPLL_D10		24
+#define CLK_TOP_SYSPLL_D12		25
+#define CLK_TOP_SYSPLL_D16		26
+#define CLK_TOP_SYSPLL_D24		27
+#define CLK_TOP_SYSPLL_D3		28
+#define CLK_TOP_SYSPLL_D2P5		29
+#define CLK_TOP_SYSPLL_D5		30
+#define CLK_TOP_SYSPLL_D3P5		31
+#define CLK_TOP_UNIVPLL1_D2		32
+#define CLK_TOP_UNIVPLL1_D4		33
+#define CLK_TOP_UNIVPLL1_D6		34
+#define CLK_TOP_UNIVPLL1_D8		35
+#define CLK_TOP_UNIVPLL1_D10		36
+#define CLK_TOP_UNIVPLL2_D2		37
+#define CLK_TOP_UNIVPLL2_D4		38
+#define CLK_TOP_UNIVPLL2_D6		39
+#define CLK_TOP_UNIVPLL2_D8		40
+#define CLK_TOP_UNIVPLL_D3		41
+#define CLK_TOP_UNIVPLL_D5		42
+#define CLK_TOP_UNIVPLL_D7		43
+#define CLK_TOP_UNIVPLL_D10		44
+#define CLK_TOP_UNIVPLL_D26		45
+#define CLK_TOP_APLL			46
+#define CLK_TOP_APLL_D4			47
+#define CLK_TOP_APLL_D8			48
+#define CLK_TOP_APLL_D16		49
+#define CLK_TOP_APLL_D24		50
+#define CLK_TOP_LVDSPLL_D2		51
+#define CLK_TOP_LVDSPLL_D4		52
+#define CLK_TOP_LVDSPLL_D8		53
+#define CLK_TOP_LVDSTX_CLKDIG_CT	54
+#define CLK_TOP_VPLL_DPIX		55
+#define CLK_TOP_TVHDMI_H		56
+#define CLK_TOP_HDMITX_CLKDIG_D2	57
+#define CLK_TOP_HDMITX_CLKDIG_D3	58
+#define CLK_TOP_TVHDMI_D2		59
+#define CLK_TOP_TVHDMI_D4		60
+#define CLK_TOP_MEMPLL_MCK_D4		61
+#define CLK_TOP_AXI_SEL			62
+#define CLK_TOP_SMI_SEL			63
+#define CLK_TOP_MFG_SEL			64
+#define CLK_TOP_IRDA_SEL		65
+#define CLK_TOP_CAM_SEL			66
+#define CLK_TOP_AUD_INTBUS_SEL		67
+#define CLK_TOP_JPG_SEL			68
+#define CLK_TOP_DISP_SEL		69
+#define CLK_TOP_MSDC30_1_SEL		70
+#define CLK_TOP_MSDC30_2_SEL		71
+#define CLK_TOP_MSDC30_3_SEL		72
+#define CLK_TOP_MSDC30_4_SEL		73
+#define CLK_TOP_USB20_SEL		74
+#define CLK_TOP_VENC_SEL		75
+#define CLK_TOP_SPI_SEL			76
+#define CLK_TOP_UART_SEL		77
+#define CLK_TOP_MEM_SEL			78
+#define CLK_TOP_CAMTG_SEL		79
+#define CLK_TOP_AUDIO_SEL		80
+#define CLK_TOP_FIX_SEL			81
+#define CLK_TOP_VDEC_SEL		82
+#define CLK_TOP_DDRPHYCFG_SEL		83
+#define CLK_TOP_DPILVDS_SEL		84
+#define CLK_TOP_PMICSPI_SEL		85
+#define CLK_TOP_MSDC30_0_SEL		86
+#define CLK_TOP_SMI_MFG_AS_SEL		87
+#define CLK_TOP_GCPU_SEL		88
+#define CLK_TOP_DPI1_SEL		89
+#define CLK_TOP_CCI_SEL			90
+#define CLK_TOP_APLL_SEL		91
+#define CLK_TOP_HDMIPLL_SEL		92
+#define CLK_TOP_NR_CLK			93
+
+/* APMIXED_SYS */
+
+#define CLK_APMIXED_ARMPLL1		1
+#define CLK_APMIXED_ARMPLL2		2
+#define CLK_APMIXED_MAINPLL		3
+#define CLK_APMIXED_UNIVPLL		4
+#define CLK_APMIXED_MMPLL		5
+#define CLK_APMIXED_MSDCPLL		6
+#define CLK_APMIXED_TVDPLL		7
+#define CLK_APMIXED_LVDSPLL		8
+#define CLK_APMIXED_AUDPLL		9
+#define CLK_APMIXED_VDECPLL		10
+#define CLK_APMIXED_NR_CLK		11
+
+/* INFRA_SYS */
+
+#define CLK_INFRA_PMIC_WRAP		1
+#define CLK_INFRA_PMICSPI		2
+#define CLK_INFRA_CCIF1_AP_CTRL		3
+#define CLK_INFRA_CCIF0_AP_CTRL		4
+#define CLK_INFRA_KP			5
+#define CLK_INFRA_CPUM			6
+#define CLK_INFRA_M4U			7
+#define CLK_INFRA_MFGAXI		8
+#define CLK_INFRA_DEVAPC		9
+#define CLK_INFRA_AUDIO			10
+#define CLK_INFRA_MFG_BUS		11
+#define CLK_INFRA_SMI			12
+#define CLK_INFRA_DBGCLK		13
+#define CLK_INFRA_NR_CLK		14
+
+/* PERI_SYS */
+
+#define CLK_PERI_I2C5			1
+#define CLK_PERI_I2C4			2
+#define CLK_PERI_I2C3			3
+#define CLK_PERI_I2C2			4
+#define CLK_PERI_I2C1			5
+#define CLK_PERI_I2C0			6
+#define CLK_PERI_UART3			7
+#define CLK_PERI_UART2			8
+#define CLK_PERI_UART1			9
+#define CLK_PERI_UART0			10
+#define CLK_PERI_IRDA			11
+#define CLK_PERI_NLI			12
+#define CLK_PERI_MD_HIF			13
+#define CLK_PERI_AP_HIF			14
+#define CLK_PERI_MSDC30_3		15
+#define CLK_PERI_MSDC30_2		16
+#define CLK_PERI_MSDC30_1		17
+#define CLK_PERI_MSDC20_2		18
+#define CLK_PERI_MSDC20_1		19
+#define CLK_PERI_AP_DMA			20
+#define CLK_PERI_USB1			21
+#define CLK_PERI_USB0			22
+#define CLK_PERI_PWM			23
+#define CLK_PERI_PWM7			24
+#define CLK_PERI_PWM6			25
+#define CLK_PERI_PWM5			26
+#define CLK_PERI_PWM4			27
+#define CLK_PERI_PWM3			28
+#define CLK_PERI_PWM2			29
+#define CLK_PERI_PWM1			30
+#define CLK_PERI_THERM			31
+#define CLK_PERI_NFI			32
+#define CLK_PERI_USBSLV			33
+#define CLK_PERI_USB1_MCU		34
+#define CLK_PERI_USB0_MCU		35
+#define CLK_PERI_GCPU			36
+#define CLK_PERI_FHCTL			37
+#define CLK_PERI_SPI1			38
+#define CLK_PERI_AUXADC			39
+#define CLK_PERI_PERI_PWRAP		40
+#define CLK_PERI_I2C6			41
+#define CLK_PERI_UART0_SEL		42
+#define CLK_PERI_UART1_SEL		43
+#define CLK_PERI_UART2_SEL		44
+#define CLK_PERI_UART3_SEL		45
+#define CLK_PERI_NR_CLK			46
+
+#endif /* _DT_BINDINGS_CLK_MT8135_H */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/mt8173-clk.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/mt8173-clk.h
new file mode 100644
index 0000000000000000000000000000000000000000..8aea623dd518e0e3571adf89f5866e4c520f4c42
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/mt8173-clk.h
@@ -0,0 +1,330 @@
+/*
+ * Copyright (c) 2014 MediaTek Inc.
+ * Author: James Liao <jamesjj.liao@mediatek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_CLK_MT8173_H
+#define _DT_BINDINGS_CLK_MT8173_H
+
+/* TOPCKGEN */
+
+#define CLK_TOP_CLKPH_MCK_O		1
+#define CLK_TOP_USB_SYSPLL_125M		3
+#define CLK_TOP_HDMITX_DIG_CTS		4
+#define CLK_TOP_ARMCA7PLL_754M		5
+#define CLK_TOP_ARMCA7PLL_502M		6
+#define CLK_TOP_MAIN_H546M		7
+#define CLK_TOP_MAIN_H364M		8
+#define CLK_TOP_MAIN_H218P4M		9
+#define CLK_TOP_MAIN_H156M		10
+#define CLK_TOP_TVDPLL_445P5M		11
+#define CLK_TOP_TVDPLL_594M		12
+#define CLK_TOP_UNIV_624M		13
+#define CLK_TOP_UNIV_416M		14
+#define CLK_TOP_UNIV_249P6M		15
+#define CLK_TOP_UNIV_178P3M		16
+#define CLK_TOP_UNIV_48M		17
+#define CLK_TOP_CLKRTC_EXT		18
+#define CLK_TOP_CLKRTC_INT		19
+#define CLK_TOP_FPC			20
+#define CLK_TOP_HDMITXPLL_D2		21
+#define CLK_TOP_HDMITXPLL_D3		22
+#define CLK_TOP_ARMCA7PLL_D2		23
+#define CLK_TOP_ARMCA7PLL_D3		24
+#define CLK_TOP_APLL1			25
+#define CLK_TOP_APLL2			26
+#define CLK_TOP_DMPLL			27
+#define CLK_TOP_DMPLL_D2		28
+#define CLK_TOP_DMPLL_D4		29
+#define CLK_TOP_DMPLL_D8		30
+#define CLK_TOP_DMPLL_D16		31
+#define CLK_TOP_LVDSPLL_D2		32
+#define CLK_TOP_LVDSPLL_D4		33
+#define CLK_TOP_LVDSPLL_D8		34
+#define CLK_TOP_MMPLL			35
+#define CLK_TOP_MMPLL_D2		36
+#define CLK_TOP_MSDCPLL			37
+#define CLK_TOP_MSDCPLL_D2		38
+#define CLK_TOP_MSDCPLL_D4		39
+#define CLK_TOP_MSDCPLL2		40
+#define CLK_TOP_MSDCPLL2_D2		41
+#define CLK_TOP_MSDCPLL2_D4		42
+#define CLK_TOP_SYSPLL_D2		43
+#define CLK_TOP_SYSPLL1_D2		44
+#define CLK_TOP_SYSPLL1_D4		45
+#define CLK_TOP_SYSPLL1_D8		46
+#define CLK_TOP_SYSPLL1_D16		47
+#define CLK_TOP_SYSPLL_D3		48
+#define CLK_TOP_SYSPLL2_D2		49
+#define CLK_TOP_SYSPLL2_D4		50
+#define CLK_TOP_SYSPLL_D5		51
+#define CLK_TOP_SYSPLL3_D2		52
+#define CLK_TOP_SYSPLL3_D4		53
+#define CLK_TOP_SYSPLL_D7		54
+#define CLK_TOP_SYSPLL4_D2		55
+#define CLK_TOP_SYSPLL4_D4		56
+#define CLK_TOP_TVDPLL			57
+#define CLK_TOP_TVDPLL_D2		58
+#define CLK_TOP_TVDPLL_D4		59
+#define CLK_TOP_TVDPLL_D8		60
+#define CLK_TOP_TVDPLL_D16		61
+#define CLK_TOP_UNIVPLL_D2		62
+#define CLK_TOP_UNIVPLL1_D2		63
+#define CLK_TOP_UNIVPLL1_D4		64
+#define CLK_TOP_UNIVPLL1_D8		65
+#define CLK_TOP_UNIVPLL_D3		66
+#define CLK_TOP_UNIVPLL2_D2		67
+#define CLK_TOP_UNIVPLL2_D4		68
+#define CLK_TOP_UNIVPLL2_D8		69
+#define CLK_TOP_UNIVPLL_D5		70
+#define CLK_TOP_UNIVPLL3_D2		71
+#define CLK_TOP_UNIVPLL3_D4		72
+#define CLK_TOP_UNIVPLL3_D8		73
+#define CLK_TOP_UNIVPLL_D7		74
+#define CLK_TOP_UNIVPLL_D26		75
+#define CLK_TOP_UNIVPLL_D52		76
+#define CLK_TOP_VCODECPLL		77
+#define CLK_TOP_VCODECPLL_370P5		78
+#define CLK_TOP_VENCPLL			79
+#define CLK_TOP_VENCPLL_D2		80
+#define CLK_TOP_VENCPLL_D4		81
+#define CLK_TOP_AXI_SEL			82
+#define CLK_TOP_MEM_SEL			83
+#define CLK_TOP_DDRPHYCFG_SEL		84
+#define CLK_TOP_MM_SEL			85
+#define CLK_TOP_PWM_SEL			86
+#define CLK_TOP_VDEC_SEL		87
+#define CLK_TOP_VENC_SEL		88
+#define CLK_TOP_MFG_SEL			89
+#define CLK_TOP_CAMTG_SEL		90
+#define CLK_TOP_UART_SEL		91
+#define CLK_TOP_SPI_SEL			92
+#define CLK_TOP_USB20_SEL		93
+#define CLK_TOP_USB30_SEL		94
+#define CLK_TOP_MSDC50_0_H_SEL		95
+#define CLK_TOP_MSDC50_0_SEL		96
+#define CLK_TOP_MSDC30_1_SEL		97
+#define CLK_TOP_MSDC30_2_SEL		98
+#define CLK_TOP_MSDC30_3_SEL		99
+#define CLK_TOP_AUDIO_SEL		100
+#define CLK_TOP_AUD_INTBUS_SEL		101
+#define CLK_TOP_PMICSPI_SEL		102
+#define CLK_TOP_SCP_SEL			103
+#define CLK_TOP_ATB_SEL			104
+#define CLK_TOP_VENC_LT_SEL		105
+#define CLK_TOP_DPI0_SEL		106
+#define CLK_TOP_IRDA_SEL		107
+#define CLK_TOP_CCI400_SEL		108
+#define CLK_TOP_AUD_1_SEL		109
+#define CLK_TOP_AUD_2_SEL		110
+#define CLK_TOP_MEM_MFG_IN_SEL		111
+#define CLK_TOP_AXI_MFG_IN_SEL		112
+#define CLK_TOP_SCAM_SEL		113
+#define CLK_TOP_SPINFI_IFR_SEL		114
+#define CLK_TOP_HDMI_SEL		115
+#define CLK_TOP_DPILVDS_SEL		116
+#define CLK_TOP_MSDC50_2_H_SEL		117
+#define CLK_TOP_HDCP_SEL		118
+#define CLK_TOP_HDCP_24M_SEL		119
+#define CLK_TOP_RTC_SEL			120
+#define CLK_TOP_APLL1_DIV0		121
+#define CLK_TOP_APLL1_DIV1		122
+#define CLK_TOP_APLL1_DIV2		123
+#define CLK_TOP_APLL1_DIV3		124
+#define CLK_TOP_APLL1_DIV4		125
+#define CLK_TOP_APLL1_DIV5		126
+#define CLK_TOP_APLL2_DIV0		127
+#define CLK_TOP_APLL2_DIV1		128
+#define CLK_TOP_APLL2_DIV2		129
+#define CLK_TOP_APLL2_DIV3		130
+#define CLK_TOP_APLL2_DIV4		131
+#define CLK_TOP_APLL2_DIV5		132
+#define CLK_TOP_I2S0_M_SEL		133
+#define CLK_TOP_I2S1_M_SEL		134
+#define CLK_TOP_I2S2_M_SEL		135
+#define CLK_TOP_I2S3_M_SEL		136
+#define CLK_TOP_I2S3_B_SEL		137
+#define CLK_TOP_DSI0_DIG		138
+#define CLK_TOP_DSI1_DIG		139
+#define CLK_TOP_LVDS_PXL		140
+#define CLK_TOP_LVDS_CTS		141
+#define CLK_TOP_NR_CLK			142
+
+/* APMIXED_SYS */
+
+#define CLK_APMIXED_ARMCA15PLL		1
+#define CLK_APMIXED_ARMCA7PLL		2
+#define CLK_APMIXED_MAINPLL		3
+#define CLK_APMIXED_UNIVPLL		4
+#define CLK_APMIXED_MMPLL		5
+#define CLK_APMIXED_MSDCPLL		6
+#define CLK_APMIXED_VENCPLL		7
+#define CLK_APMIXED_TVDPLL		8
+#define CLK_APMIXED_MPLL		9
+#define CLK_APMIXED_VCODECPLL		10
+#define CLK_APMIXED_APLL1		11
+#define CLK_APMIXED_APLL2		12
+#define CLK_APMIXED_LVDSPLL		13
+#define CLK_APMIXED_MSDCPLL2		14
+#define CLK_APMIXED_REF2USB_TX		15
+#define CLK_APMIXED_HDMI_REF		16
+#define CLK_APMIXED_NR_CLK		17
+
+/* INFRA_SYS */
+
+#define CLK_INFRA_DBGCLK		1
+#define CLK_INFRA_SMI			2
+#define CLK_INFRA_AUDIO			3
+#define CLK_INFRA_GCE			4
+#define CLK_INFRA_L2C_SRAM		5
+#define CLK_INFRA_M4U			6
+#define CLK_INFRA_CPUM			7
+#define CLK_INFRA_KP			8
+#define CLK_INFRA_CEC			9
+#define CLK_INFRA_PMICSPI		10
+#define CLK_INFRA_PMICWRAP		11
+#define CLK_INFRA_CLK_13M		12
+#define CLK_INFRA_CA53SEL               13
+#define CLK_INFRA_CA57SEL               14
+#define CLK_INFRA_NR_CLK                15
+
+/* PERI_SYS */
+
+#define CLK_PERI_NFI			1
+#define CLK_PERI_THERM			2
+#define CLK_PERI_PWM1			3
+#define CLK_PERI_PWM2			4
+#define CLK_PERI_PWM3			5
+#define CLK_PERI_PWM4			6
+#define CLK_PERI_PWM5			7
+#define CLK_PERI_PWM6			8
+#define CLK_PERI_PWM7			9
+#define CLK_PERI_PWM			10
+#define CLK_PERI_USB0			11
+#define CLK_PERI_USB1			12
+#define CLK_PERI_AP_DMA			13
+#define CLK_PERI_MSDC30_0		14
+#define CLK_PERI_MSDC30_1		15
+#define CLK_PERI_MSDC30_2		16
+#define CLK_PERI_MSDC30_3		17
+#define CLK_PERI_NLI_ARB		18
+#define CLK_PERI_IRDA			19
+#define CLK_PERI_UART0			20
+#define CLK_PERI_UART1			21
+#define CLK_PERI_UART2			22
+#define CLK_PERI_UART3			23
+#define CLK_PERI_I2C0			24
+#define CLK_PERI_I2C1			25
+#define CLK_PERI_I2C2			26
+#define CLK_PERI_I2C3			27
+#define CLK_PERI_I2C4			28
+#define CLK_PERI_AUXADC			29
+#define CLK_PERI_SPI0			30
+#define CLK_PERI_I2C5			31
+#define CLK_PERI_NFIECC			32
+#define CLK_PERI_SPI			33
+#define CLK_PERI_IRRX			34
+#define CLK_PERI_I2C6			35
+#define CLK_PERI_UART0_SEL		36
+#define CLK_PERI_UART1_SEL		37
+#define CLK_PERI_UART2_SEL		38
+#define CLK_PERI_UART3_SEL		39
+#define CLK_PERI_NR_CLK			40
+
+/* IMG_SYS */
+
+#define CLK_IMG_LARB2_SMI		1
+#define CLK_IMG_CAM_SMI			2
+#define CLK_IMG_CAM_CAM			3
+#define CLK_IMG_SEN_TG			4
+#define CLK_IMG_SEN_CAM			5
+#define CLK_IMG_CAM_SV			6
+#define CLK_IMG_FD			7
+#define CLK_IMG_NR_CLK			8
+
+/* MM_SYS */
+
+#define CLK_MM_SMI_COMMON		1
+#define CLK_MM_SMI_LARB0		2
+#define CLK_MM_CAM_MDP			3
+#define CLK_MM_MDP_RDMA0		4
+#define CLK_MM_MDP_RDMA1		5
+#define CLK_MM_MDP_RSZ0			6
+#define CLK_MM_MDP_RSZ1			7
+#define CLK_MM_MDP_RSZ2			8
+#define CLK_MM_MDP_TDSHP0		9
+#define CLK_MM_MDP_TDSHP1		10
+#define CLK_MM_MDP_WDMA			11
+#define CLK_MM_MDP_WROT0		12
+#define CLK_MM_MDP_WROT1		13
+#define CLK_MM_FAKE_ENG			14
+#define CLK_MM_MUTEX_32K		15
+#define CLK_MM_DISP_OVL0		16
+#define CLK_MM_DISP_OVL1		17
+#define CLK_MM_DISP_RDMA0		18
+#define CLK_MM_DISP_RDMA1		19
+#define CLK_MM_DISP_RDMA2		20
+#define CLK_MM_DISP_WDMA0		21
+#define CLK_MM_DISP_WDMA1		22
+#define CLK_MM_DISP_COLOR0		23
+#define CLK_MM_DISP_COLOR1		24
+#define CLK_MM_DISP_AAL			25
+#define CLK_MM_DISP_GAMMA		26
+#define CLK_MM_DISP_UFOE		27
+#define CLK_MM_DISP_SPLIT0		28
+#define CLK_MM_DISP_SPLIT1		29
+#define CLK_MM_DISP_MERGE		30
+#define CLK_MM_DISP_OD			31
+#define CLK_MM_DISP_PWM0MM		32
+#define CLK_MM_DISP_PWM026M		33
+#define CLK_MM_DISP_PWM1MM		34
+#define CLK_MM_DISP_PWM126M		35
+#define CLK_MM_DSI0_ENGINE		36
+#define CLK_MM_DSI0_DIGITAL		37
+#define CLK_MM_DSI1_ENGINE		38
+#define CLK_MM_DSI1_DIGITAL		39
+#define CLK_MM_DPI_PIXEL		40
+#define CLK_MM_DPI_ENGINE		41
+#define CLK_MM_DPI1_PIXEL		42
+#define CLK_MM_DPI1_ENGINE		43
+#define CLK_MM_HDMI_PIXEL		44
+#define CLK_MM_HDMI_PLLCK		45
+#define CLK_MM_HDMI_AUDIO		46
+#define CLK_MM_HDMI_SPDIF		47
+#define CLK_MM_LVDS_PIXEL		48
+#define CLK_MM_LVDS_CTS			49
+#define CLK_MM_SMI_LARB4		50
+#define CLK_MM_HDMI_HDCP		51
+#define CLK_MM_HDMI_HDCP24M		52
+#define CLK_MM_NR_CLK			53
+
+/* VDEC_SYS */
+
+#define CLK_VDEC_CKEN			1
+#define CLK_VDEC_LARB_CKEN		2
+#define CLK_VDEC_NR_CLK			3
+
+/* VENC_SYS */
+
+#define CLK_VENC_CKE0			1
+#define CLK_VENC_CKE1			2
+#define CLK_VENC_CKE2			3
+#define CLK_VENC_CKE3			4
+#define CLK_VENC_NR_CLK			5
+
+/* VENCLT_SYS */
+
+#define CLK_VENCLT_CKE0			1
+#define CLK_VENCLT_CKE1			2
+#define CLK_VENCLT_NR_CLK		3
+
+#endif /* _DT_BINDINGS_CLK_MT8173_H */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/nuvoton,npcm7xx-clock.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/nuvoton,npcm7xx-clock.h
new file mode 100644
index 0000000000000000000000000000000000000000..f21522605b94b74b57ac7fabece973752c568f81
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/nuvoton,npcm7xx-clock.h
@@ -0,0 +1,44 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Nuvoton NPCM7xx Clock Generator binding
+ * clock binding number for all clocks supportted by nuvoton,npcm7xx-clk
+ *
+ * Copyright (C) 2018 Nuvoton Technologies tali.perry@nuvoton.com
+ *
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_NPCM7XX_H
+#define __DT_BINDINGS_CLOCK_NPCM7XX_H
+
+
+#define NPCM7XX_CLK_CPU 0
+#define NPCM7XX_CLK_GFX_PIXEL 1
+#define NPCM7XX_CLK_MC 2
+#define NPCM7XX_CLK_ADC 3
+#define NPCM7XX_CLK_AHB 4
+#define NPCM7XX_CLK_TIMER 5
+#define NPCM7XX_CLK_UART 6
+#define NPCM7XX_CLK_MMC  7
+#define NPCM7XX_CLK_SPI3 8
+#define NPCM7XX_CLK_PCI  9
+#define NPCM7XX_CLK_AXI 10
+#define NPCM7XX_CLK_APB4 11
+#define NPCM7XX_CLK_APB3 12
+#define NPCM7XX_CLK_APB2 13
+#define NPCM7XX_CLK_APB1 14
+#define NPCM7XX_CLK_APB5 15
+#define NPCM7XX_CLK_CLKOUT 16
+#define NPCM7XX_CLK_GFX  17
+#define NPCM7XX_CLK_SU   18
+#define NPCM7XX_CLK_SU48 19
+#define NPCM7XX_CLK_SDHC 20
+#define NPCM7XX_CLK_SPI0 21
+#define NPCM7XX_CLK_SPIX 22
+
+#define NPCM7XX_CLK_REFCLK 23
+#define NPCM7XX_CLK_SYSBYPCK 24
+#define NPCM7XX_CLK_MCBYPCK 25
+
+#define NPCM7XX_NUM_CLOCKS	 (NPCM7XX_CLK_MCBYPCK+1)
+
+#endif
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/omap4.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/omap4.h
new file mode 100644
index 0000000000000000000000000000000000000000..e86c758e50ced52f98d1c3a5b4c73fe57cd9a1df
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/omap4.h
@@ -0,0 +1,146 @@
+/*
+ * Copyright 2017 Texas Instruments, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#ifndef __DT_BINDINGS_CLK_OMAP4_H
+#define __DT_BINDINGS_CLK_OMAP4_H
+
+#define OMAP4_CLKCTRL_OFFSET	0x20
+#define OMAP4_CLKCTRL_INDEX(offset)	((offset) - OMAP4_CLKCTRL_OFFSET)
+
+/* mpuss clocks */
+#define OMAP4_MPU_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x20)
+
+/* tesla clocks */
+#define OMAP4_DSP_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x20)
+
+/* abe clocks */
+#define OMAP4_L4_ABE_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x20)
+#define OMAP4_AESS_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x28)
+#define OMAP4_MCPDM_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x30)
+#define OMAP4_DMIC_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x38)
+#define OMAP4_MCASP_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x40)
+#define OMAP4_MCBSP1_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x48)
+#define OMAP4_MCBSP2_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x50)
+#define OMAP4_MCBSP3_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x58)
+#define OMAP4_SLIMBUS1_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x60)
+#define OMAP4_TIMER5_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x68)
+#define OMAP4_TIMER6_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x70)
+#define OMAP4_TIMER7_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x78)
+#define OMAP4_TIMER8_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x80)
+#define OMAP4_WD_TIMER3_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x88)
+
+/* l4_ao clocks */
+#define OMAP4_SMARTREFLEX_MPU_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x28)
+#define OMAP4_SMARTREFLEX_IVA_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x30)
+#define OMAP4_SMARTREFLEX_CORE_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x38)
+
+/* l3_1 clocks */
+#define OMAP4_L3_MAIN_1_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x20)
+
+/* l3_2 clocks */
+#define OMAP4_L3_MAIN_2_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x20)
+#define OMAP4_GPMC_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x28)
+#define OMAP4_OCMC_RAM_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x30)
+
+/* ducati clocks */
+#define OMAP4_IPU_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x20)
+
+/* l3_dma clocks */
+#define OMAP4_DMA_SYSTEM_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x20)
+
+/* l3_emif clocks */
+#define OMAP4_DMM_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x20)
+#define OMAP4_EMIF1_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x30)
+#define OMAP4_EMIF2_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x38)
+
+/* d2d clocks */
+#define OMAP4_C2C_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x20)
+
+/* l4_cfg clocks */
+#define OMAP4_L4_CFG_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x20)
+#define OMAP4_SPINLOCK_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x28)
+#define OMAP4_MAILBOX_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x30)
+
+/* l3_instr clocks */
+#define OMAP4_L3_MAIN_3_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x20)
+#define OMAP4_L3_INSTR_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x28)
+#define OMAP4_OCP_WP_NOC_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x40)
+
+/* ivahd clocks */
+#define OMAP4_IVA_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x20)
+#define OMAP4_SL2IF_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x28)
+
+/* iss clocks */
+#define OMAP4_ISS_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x20)
+#define OMAP4_FDIF_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x28)
+
+/* l3_dss clocks */
+#define OMAP4_DSS_CORE_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x20)
+
+/* l3_gfx clocks */
+#define OMAP4_GPU_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x20)
+
+/* l3_init clocks */
+#define OMAP4_MMC1_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x28)
+#define OMAP4_MMC2_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x30)
+#define OMAP4_HSI_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x38)
+#define OMAP4_USB_HOST_HS_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x58)
+#define OMAP4_USB_OTG_HS_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x60)
+#define OMAP4_USB_TLL_HS_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x68)
+#define OMAP4_USB_HOST_FS_CLKCTRL	OMAP4_CLKCTRL_INDEX(0xd0)
+#define OMAP4_OCP2SCP_USB_PHY_CLKCTRL	OMAP4_CLKCTRL_INDEX(0xe0)
+
+/* l4_per clocks */
+#define OMAP4_TIMER10_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x28)
+#define OMAP4_TIMER11_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x30)
+#define OMAP4_TIMER2_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x38)
+#define OMAP4_TIMER3_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x40)
+#define OMAP4_TIMER4_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x48)
+#define OMAP4_TIMER9_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x50)
+#define OMAP4_ELM_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x58)
+#define OMAP4_GPIO2_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x60)
+#define OMAP4_GPIO3_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x68)
+#define OMAP4_GPIO4_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x70)
+#define OMAP4_GPIO5_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x78)
+#define OMAP4_GPIO6_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x80)
+#define OMAP4_HDQ1W_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x88)
+#define OMAP4_I2C1_CLKCTRL	OMAP4_CLKCTRL_INDEX(0xa0)
+#define OMAP4_I2C2_CLKCTRL	OMAP4_CLKCTRL_INDEX(0xa8)
+#define OMAP4_I2C3_CLKCTRL	OMAP4_CLKCTRL_INDEX(0xb0)
+#define OMAP4_I2C4_CLKCTRL	OMAP4_CLKCTRL_INDEX(0xb8)
+#define OMAP4_L4_PER_CLKCTRL	OMAP4_CLKCTRL_INDEX(0xc0)
+#define OMAP4_MCBSP4_CLKCTRL	OMAP4_CLKCTRL_INDEX(0xe0)
+#define OMAP4_MCSPI1_CLKCTRL	OMAP4_CLKCTRL_INDEX(0xf0)
+#define OMAP4_MCSPI2_CLKCTRL	OMAP4_CLKCTRL_INDEX(0xf8)
+#define OMAP4_MCSPI3_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x100)
+#define OMAP4_MCSPI4_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x108)
+#define OMAP4_MMC3_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x120)
+#define OMAP4_MMC4_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x128)
+#define OMAP4_SLIMBUS2_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x138)
+#define OMAP4_UART1_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x140)
+#define OMAP4_UART2_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x148)
+#define OMAP4_UART3_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x150)
+#define OMAP4_UART4_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x158)
+#define OMAP4_MMC5_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x160)
+
+/* l4_wkup clocks */
+#define OMAP4_L4_WKUP_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x20)
+#define OMAP4_WD_TIMER2_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x30)
+#define OMAP4_GPIO1_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x38)
+#define OMAP4_TIMER1_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x40)
+#define OMAP4_COUNTER_32K_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x50)
+#define OMAP4_KBD_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x78)
+
+/* emu_sys clocks */
+#define OMAP4_DEBUGSS_CLKCTRL	OMAP4_CLKCTRL_INDEX(0x20)
+
+#endif
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/omap5.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/omap5.h
new file mode 100644
index 0000000000000000000000000000000000000000..f51821a9121695c2c0120aeae3d4ebcb5b649025
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/omap5.h
@@ -0,0 +1,118 @@
+/*
+ * Copyright 2017 Texas Instruments, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#ifndef __DT_BINDINGS_CLK_OMAP5_H
+#define __DT_BINDINGS_CLK_OMAP5_H
+
+#define OMAP5_CLKCTRL_OFFSET	0x20
+#define OMAP5_CLKCTRL_INDEX(offset)	((offset) - OMAP5_CLKCTRL_OFFSET)
+
+/* mpu clocks */
+#define OMAP5_MPU_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x20)
+
+/* dsp clocks */
+#define OMAP5_MMU_DSP_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x20)
+
+/* abe clocks */
+#define OMAP5_L4_ABE_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x20)
+#define OMAP5_MCPDM_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x30)
+#define OMAP5_DMIC_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x38)
+#define OMAP5_MCBSP1_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x48)
+#define OMAP5_MCBSP2_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x50)
+#define OMAP5_MCBSP3_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x58)
+#define OMAP5_TIMER5_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x68)
+#define OMAP5_TIMER6_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x70)
+#define OMAP5_TIMER7_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x78)
+#define OMAP5_TIMER8_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x80)
+
+/* l3main1 clocks */
+#define OMAP5_L3_MAIN_1_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x20)
+
+/* l3main2 clocks */
+#define OMAP5_L3_MAIN_2_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x20)
+
+/* ipu clocks */
+#define OMAP5_MMU_IPU_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x20)
+
+/* dma clocks */
+#define OMAP5_DMA_SYSTEM_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x20)
+
+/* emif clocks */
+#define OMAP5_DMM_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x20)
+#define OMAP5_EMIF1_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x30)
+#define OMAP5_EMIF2_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x38)
+
+/* l4cfg clocks */
+#define OMAP5_L4_CFG_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x20)
+#define OMAP5_SPINLOCK_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x28)
+#define OMAP5_MAILBOX_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x30)
+
+/* l3instr clocks */
+#define OMAP5_L3_MAIN_3_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x20)
+#define OMAP5_L3_INSTR_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x28)
+
+/* l4per clocks */
+#define OMAP5_TIMER10_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x28)
+#define OMAP5_TIMER11_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x30)
+#define OMAP5_TIMER2_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x38)
+#define OMAP5_TIMER3_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x40)
+#define OMAP5_TIMER4_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x48)
+#define OMAP5_TIMER9_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x50)
+#define OMAP5_GPIO2_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x60)
+#define OMAP5_GPIO3_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x68)
+#define OMAP5_GPIO4_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x70)
+#define OMAP5_GPIO5_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x78)
+#define OMAP5_GPIO6_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x80)
+#define OMAP5_I2C1_CLKCTRL	OMAP5_CLKCTRL_INDEX(0xa0)
+#define OMAP5_I2C2_CLKCTRL	OMAP5_CLKCTRL_INDEX(0xa8)
+#define OMAP5_I2C3_CLKCTRL	OMAP5_CLKCTRL_INDEX(0xb0)
+#define OMAP5_I2C4_CLKCTRL	OMAP5_CLKCTRL_INDEX(0xb8)
+#define OMAP5_L4_PER_CLKCTRL	OMAP5_CLKCTRL_INDEX(0xc0)
+#define OMAP5_MCSPI1_CLKCTRL	OMAP5_CLKCTRL_INDEX(0xf0)
+#define OMAP5_MCSPI2_CLKCTRL	OMAP5_CLKCTRL_INDEX(0xf8)
+#define OMAP5_MCSPI3_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x100)
+#define OMAP5_MCSPI4_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x108)
+#define OMAP5_GPIO7_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x110)
+#define OMAP5_GPIO8_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x118)
+#define OMAP5_MMC3_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x120)
+#define OMAP5_MMC4_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x128)
+#define OMAP5_UART1_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x140)
+#define OMAP5_UART2_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x148)
+#define OMAP5_UART3_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x150)
+#define OMAP5_UART4_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x158)
+#define OMAP5_MMC5_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x160)
+#define OMAP5_I2C5_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x168)
+#define OMAP5_UART5_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x170)
+#define OMAP5_UART6_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x178)
+
+/* dss clocks */
+#define OMAP5_DSS_CORE_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x20)
+
+/* l3init clocks */
+#define OMAP5_MMC1_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x28)
+#define OMAP5_MMC2_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x30)
+#define OMAP5_USB_HOST_HS_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x58)
+#define OMAP5_USB_TLL_HS_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x68)
+#define OMAP5_SATA_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x88)
+#define OMAP5_OCP2SCP1_CLKCTRL	OMAP5_CLKCTRL_INDEX(0xe0)
+#define OMAP5_OCP2SCP3_CLKCTRL	OMAP5_CLKCTRL_INDEX(0xe8)
+#define OMAP5_USB_OTG_SS_CLKCTRL	OMAP5_CLKCTRL_INDEX(0xf0)
+
+/* wkupaon clocks */
+#define OMAP5_L4_WKUP_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x20)
+#define OMAP5_WD_TIMER2_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x30)
+#define OMAP5_GPIO1_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x38)
+#define OMAP5_TIMER1_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x40)
+#define OMAP5_COUNTER_32K_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x50)
+#define OMAP5_KBD_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x78)
+
+#endif
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/oxsemi,ox810se.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/oxsemi,ox810se.h
new file mode 100644
index 0000000000000000000000000000000000000000..d5facb5e83f17fb416176312e9d052f04ac6ad4c
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/oxsemi,ox810se.h
@@ -0,0 +1,30 @@
+/*
+ * Copyright (C) 2016 Neil Armstrong <narmstrong@baylibre.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef DT_CLOCK_OXSEMI_OX810SE_H
+#define DT_CLOCK_OXSEMI_OX810SE_H
+
+#define CLK_810_LEON		0
+#define CLK_810_DMA_SGDMA	1
+#define CLK_810_CIPHER		2
+#define CLK_810_SATA		3
+#define CLK_810_AUDIO		4
+#define CLK_810_USBMPH		5
+#define CLK_810_ETHA		6
+#define CLK_810_PCIEA		7
+#define CLK_810_NAND		8
+
+#endif /* DT_CLOCK_OXSEMI_OX810SE_H */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/oxsemi,ox820.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/oxsemi,ox820.h
new file mode 100644
index 0000000000000000000000000000000000000000..f661ecc8d7603b56ed6db9a3af8ef8589369ceb8
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/oxsemi,ox820.h
@@ -0,0 +1,40 @@
+/*
+ * Copyright (C) 2016 Neil Armstrong <narmstrong@baylibre.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef DT_CLOCK_OXSEMI_OX820_H
+#define DT_CLOCK_OXSEMI_OX820_H
+
+/* PLLs */
+#define CLK_820_PLLA		0
+#define CLK_820_PLLB		1
+
+/* Gate Clocks */
+#define CLK_820_LEON		2
+#define CLK_820_DMA_SGDMA	3
+#define CLK_820_CIPHER		4
+#define CLK_820_SD		5
+#define CLK_820_SATA		6
+#define CLK_820_AUDIO		7
+#define CLK_820_USBMPH		8
+#define CLK_820_ETHA		9
+#define CLK_820_PCIEA		10
+#define CLK_820_NAND		11
+#define CLK_820_PCIEB		12
+#define CLK_820_ETHB		13
+#define CLK_820_REF600		14
+#define CLK_820_USBDEV		15
+
+#endif /* DT_CLOCK_OXSEMI_OX820_H */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/pistachio-clk.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/pistachio-clk.h
new file mode 100644
index 0000000000000000000000000000000000000000..039f83facb6866f3429eb8848cf7d026d4e5501e
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/pistachio-clk.h
@@ -0,0 +1,183 @@
+/*
+ * Copyright (C) 2014 Google, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_PISTACHIO_H
+#define _DT_BINDINGS_CLOCK_PISTACHIO_H
+
+/* PLLs */
+#define CLK_MIPS_PLL			0
+#define CLK_AUDIO_PLL			1
+#define CLK_RPU_V_PLL			2
+#define CLK_RPU_L_PLL			3
+#define CLK_SYS_PLL			4
+#define CLK_WIFI_PLL			5
+#define CLK_BT_PLL			6
+
+/* Fixed-factor clocks */
+#define CLK_WIFI_DIV4			16
+#define CLK_WIFI_DIV8			17
+
+/* Gate clocks */
+#define CLK_MIPS			32
+#define CLK_AUDIO_IN			33
+#define CLK_AUDIO			34
+#define CLK_I2S				35
+#define CLK_SPDIF			36
+#define CLK_AUDIO_DAC			37
+#define CLK_RPU_V			38
+#define CLK_RPU_L			39
+#define CLK_RPU_SLEEP			40
+#define CLK_WIFI_PLL_GATE		41
+#define CLK_RPU_CORE			42
+#define CLK_WIFI_ADC			43
+#define CLK_WIFI_DAC			44
+#define CLK_USB_PHY			45
+#define CLK_ENET_IN			46
+#define CLK_ENET			47
+#define CLK_UART0			48
+#define CLK_UART1			49
+#define CLK_PERIPH_SYS			50
+#define CLK_SPI0			51
+#define CLK_SPI1			52
+#define CLK_EVENT_TIMER			53
+#define CLK_AUX_ADC_INTERNAL		54
+#define CLK_AUX_ADC			55
+#define CLK_SD_HOST			56
+#define CLK_BT				57
+#define CLK_BT_DIV4			58
+#define CLK_BT_DIV8			59
+#define CLK_BT_1MHZ			60
+
+/* Divider clocks */
+#define CLK_MIPS_INTERNAL_DIV		64
+#define CLK_MIPS_DIV			65
+#define CLK_AUDIO_DIV			66
+#define CLK_I2S_DIV			67
+#define CLK_SPDIF_DIV			68
+#define CLK_AUDIO_DAC_DIV		69
+#define CLK_RPU_V_DIV			70
+#define CLK_RPU_L_DIV			71
+#define CLK_RPU_SLEEP_DIV		72
+#define CLK_RPU_CORE_DIV		73
+#define CLK_USB_PHY_DIV			74
+#define CLK_ENET_DIV			75
+#define CLK_UART0_INTERNAL_DIV		76
+#define CLK_UART0_DIV			77
+#define CLK_UART1_INTERNAL_DIV		78
+#define CLK_UART1_DIV			79
+#define CLK_SYS_INTERNAL_DIV		80
+#define CLK_SPI0_INTERNAL_DIV		81
+#define CLK_SPI0_DIV			82
+#define CLK_SPI1_INTERNAL_DIV		83
+#define CLK_SPI1_DIV			84
+#define CLK_EVENT_TIMER_INTERNAL_DIV	85
+#define CLK_EVENT_TIMER_DIV		86
+#define CLK_AUX_ADC_INTERNAL_DIV	87
+#define CLK_AUX_ADC_DIV			88
+#define CLK_SD_HOST_DIV			89
+#define CLK_BT_DIV			90
+#define CLK_BT_DIV4_DIV			91
+#define CLK_BT_DIV8_DIV			92
+#define CLK_BT_1MHZ_INTERNAL_DIV	93
+#define CLK_BT_1MHZ_DIV			94
+
+/* Mux clocks */
+#define CLK_AUDIO_REF_MUX		96
+#define CLK_MIPS_PLL_MUX		97
+#define CLK_AUDIO_PLL_MUX		98
+#define CLK_AUDIO_MUX			99
+#define CLK_RPU_V_PLL_MUX		100
+#define CLK_RPU_L_PLL_MUX		101
+#define CLK_RPU_L_MUX			102
+#define CLK_WIFI_PLL_MUX		103
+#define CLK_WIFI_DIV4_MUX		104
+#define CLK_WIFI_DIV8_MUX		105
+#define CLK_RPU_CORE_MUX		106
+#define CLK_SYS_PLL_MUX			107
+#define CLK_ENET_MUX			108
+#define CLK_EVENT_TIMER_MUX		109
+#define CLK_SD_HOST_MUX			110
+#define CLK_BT_PLL_MUX			111
+#define CLK_DEBUG_MUX			112
+
+#define CLK_NR_CLKS			113
+
+/* Peripheral gate clocks */
+#define PERIPH_CLK_SYS			0
+#define PERIPH_CLK_SYS_BUS		1
+#define PERIPH_CLK_DDR			2
+#define PERIPH_CLK_ROM			3
+#define PERIPH_CLK_COUNTER_FAST		4
+#define PERIPH_CLK_COUNTER_SLOW		5
+#define PERIPH_CLK_IR			6
+#define PERIPH_CLK_WD			7
+#define PERIPH_CLK_PDM			8
+#define PERIPH_CLK_PWM			9
+#define PERIPH_CLK_I2C0			10
+#define PERIPH_CLK_I2C1			11
+#define PERIPH_CLK_I2C2			12
+#define PERIPH_CLK_I2C3			13
+
+/* Peripheral divider clocks */
+#define PERIPH_CLK_ROM_DIV		32
+#define PERIPH_CLK_COUNTER_FAST_DIV	33
+#define PERIPH_CLK_COUNTER_SLOW_PRE_DIV	34
+#define PERIPH_CLK_COUNTER_SLOW_DIV	35
+#define PERIPH_CLK_IR_PRE_DIV		36
+#define PERIPH_CLK_IR_DIV		37
+#define PERIPH_CLK_WD_PRE_DIV		38
+#define PERIPH_CLK_WD_DIV		39
+#define PERIPH_CLK_PDM_PRE_DIV		40
+#define PERIPH_CLK_PDM_DIV		41
+#define PERIPH_CLK_PWM_PRE_DIV		42
+#define PERIPH_CLK_PWM_DIV		43
+#define PERIPH_CLK_I2C0_PRE_DIV		44
+#define PERIPH_CLK_I2C0_DIV		45
+#define PERIPH_CLK_I2C1_PRE_DIV		46
+#define PERIPH_CLK_I2C1_DIV		47
+#define PERIPH_CLK_I2C2_PRE_DIV		48
+#define PERIPH_CLK_I2C2_DIV		49
+#define PERIPH_CLK_I2C3_PRE_DIV		50
+#define PERIPH_CLK_I2C3_DIV		51
+
+#define PERIPH_CLK_NR_CLKS		52
+
+/* System gate clocks */
+#define SYS_CLK_I2C0			0
+#define SYS_CLK_I2C1			1
+#define SYS_CLK_I2C2			2
+#define SYS_CLK_I2C3			3
+#define SYS_CLK_I2S_IN			4
+#define SYS_CLK_PAUD_OUT		5
+#define SYS_CLK_SPDIF_OUT		6
+#define SYS_CLK_SPI0_MASTER		7
+#define SYS_CLK_SPI0_SLAVE		8
+#define SYS_CLK_PWM			9
+#define SYS_CLK_UART0			10
+#define SYS_CLK_UART1			11
+#define SYS_CLK_SPI1			12
+#define SYS_CLK_MDC			13
+#define SYS_CLK_SD_HOST			14
+#define SYS_CLK_ENET			15
+#define SYS_CLK_IR			16
+#define SYS_CLK_WD			17
+#define SYS_CLK_TIMER			18
+#define SYS_CLK_I2S_OUT			24
+#define SYS_CLK_SPDIF_IN		25
+#define SYS_CLK_EVENT_TIMER		26
+#define SYS_CLK_HASH			27
+
+#define SYS_CLK_NR_CLKS			28
+
+/* Gates for external input clocks */
+#define EXT_CLK_AUDIO_IN		0
+#define EXT_CLK_ENET_IN			1
+
+#define EXT_CLK_NR_CLKS			2
+
+#endif /* _DT_BINDINGS_CLOCK_PISTACHIO_H */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/px30-cru.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/px30-cru.h
new file mode 100644
index 0000000000000000000000000000000000000000..00101479f7c401851e64d55a327898a7c13c859d
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/px30-cru.h
@@ -0,0 +1,389 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+#ifndef _DT_BINDINGS_CLK_ROCKCHIP_PX30_H
+#define _DT_BINDINGS_CLK_ROCKCHIP_PX30_H
+
+/* core clocks */
+#define PLL_APLL		1
+#define PLL_DPLL		2
+#define PLL_CPLL		3
+#define PLL_NPLL		4
+#define APLL_BOOST_H		5
+#define APLL_BOOST_L		6
+#define ARMCLK			7
+
+/* sclk gates (special clocks) */
+#define USB480M			14
+#define SCLK_PDM		15
+#define SCLK_I2S0_TX		16
+#define SCLK_I2S0_TX_OUT	17
+#define SCLK_I2S0_RX		18
+#define SCLK_I2S0_RX_OUT	19
+#define SCLK_I2S1		20
+#define SCLK_I2S1_OUT		21
+#define SCLK_I2S2		22
+#define SCLK_I2S2_OUT		23
+#define SCLK_UART1		24
+#define SCLK_UART2		25
+#define SCLK_UART3		26
+#define SCLK_UART4		27
+#define SCLK_UART5		28
+#define SCLK_I2C0		29
+#define SCLK_I2C1		30
+#define SCLK_I2C2		31
+#define SCLK_I2C3		32
+#define SCLK_I2C4		33
+#define SCLK_PWM0		34
+#define SCLK_PWM1		35
+#define SCLK_SPI0		36
+#define SCLK_SPI1		37
+#define SCLK_TIMER0		38
+#define SCLK_TIMER1		39
+#define SCLK_TIMER2		40
+#define SCLK_TIMER3		41
+#define SCLK_TIMER4		42
+#define SCLK_TIMER5		43
+#define SCLK_TSADC		44
+#define SCLK_SARADC		45
+#define SCLK_OTP		46
+#define SCLK_OTP_USR		47
+#define SCLK_CRYPTO		48
+#define SCLK_CRYPTO_APK		49
+#define SCLK_DDRC		50
+#define SCLK_ISP		51
+#define SCLK_CIF_OUT		52
+#define SCLK_RGA_CORE		53
+#define SCLK_VOPB_PWM		54
+#define SCLK_NANDC		55
+#define SCLK_SDIO		56
+#define SCLK_EMMC		57
+#define SCLK_SFC		58
+#define SCLK_SDMMC		59
+#define SCLK_OTG_ADP		60
+#define SCLK_GMAC_SRC		61
+#define SCLK_GMAC		62
+#define SCLK_GMAC_RX_TX		63
+#define SCLK_MAC_REF		64
+#define SCLK_MAC_REFOUT		65
+#define SCLK_MAC_OUT		66
+#define SCLK_SDMMC_DRV		67
+#define SCLK_SDMMC_SAMPLE	68
+#define SCLK_SDIO_DRV		69
+#define SCLK_SDIO_SAMPLE	70
+#define SCLK_EMMC_DRV		71
+#define SCLK_EMMC_SAMPLE	72
+#define SCLK_GPU		73
+#define SCLK_PVTM		74
+#define SCLK_CORE_VPU		75
+#define SCLK_GMAC_RMII		76
+#define SCLK_UART2_SRC		77
+#define SCLK_NANDC_DIV		78
+#define SCLK_NANDC_DIV50	79
+#define SCLK_SDIO_DIV		80
+#define SCLK_SDIO_DIV50		81
+#define SCLK_EMMC_DIV		82
+#define SCLK_EMMC_DIV50		83
+#define SCLK_DDRCLK		84
+#define SCLK_UART1_SRC		85
+
+/* dclk gates */
+#define DCLK_VOPB		150
+#define DCLK_VOPL		151
+
+/* aclk gates */
+#define ACLK_GPU		170
+#define ACLK_BUS_PRE		171
+#define ACLK_CRYPTO		172
+#define ACLK_VI_PRE		173
+#define ACLK_VO_PRE		174
+#define ACLK_VPU		175
+#define ACLK_PERI_PRE		176
+#define ACLK_GMAC		178
+#define ACLK_CIF		179
+#define ACLK_ISP		180
+#define ACLK_VOPB		181
+#define ACLK_VOPL		182
+#define ACLK_RGA		183
+#define ACLK_GIC		184
+#define ACLK_DCF		186
+#define ACLK_DMAC		187
+#define ACLK_BUS_SRC		188
+#define ACLK_PERI_SRC		189
+
+/* hclk gates */
+#define HCLK_BUS_PRE		240
+#define HCLK_CRYPTO		241
+#define HCLK_VI_PRE		242
+#define HCLK_VO_PRE		243
+#define HCLK_VPU		244
+#define HCLK_PERI_PRE		245
+#define HCLK_MMC_NAND		246
+#define HCLK_SDMMC		247
+#define HCLK_USB		248
+#define HCLK_CIF		249
+#define HCLK_ISP		250
+#define HCLK_VOPB		251
+#define HCLK_VOPL		252
+#define HCLK_RGA		253
+#define HCLK_NANDC		254
+#define HCLK_SDIO		255
+#define HCLK_EMMC		256
+#define HCLK_SFC		257
+#define HCLK_OTG		258
+#define HCLK_HOST		259
+#define HCLK_HOST_ARB		260
+#define HCLK_PDM		261
+#define HCLK_I2S0		262
+#define HCLK_I2S1		263
+#define HCLK_I2S2		264
+
+/* pclk gates */
+#define PCLK_BUS_PRE		320
+#define PCLK_DDR		321
+#define PCLK_VO_PRE		322
+#define PCLK_GMAC		323
+#define PCLK_MIPI_DSI		324
+#define PCLK_MIPIDSIPHY		325
+#define PCLK_MIPICSIPHY		326
+#define PCLK_USB_GRF		327
+#define PCLK_DCF		328
+#define PCLK_UART1		329
+#define PCLK_UART2		330
+#define PCLK_UART3		331
+#define PCLK_UART4		332
+#define PCLK_UART5		333
+#define PCLK_I2C0		334
+#define PCLK_I2C1		335
+#define PCLK_I2C2		336
+#define PCLK_I2C3		337
+#define PCLK_I2C4		338
+#define PCLK_PWM0		339
+#define PCLK_PWM1		340
+#define PCLK_SPI0		341
+#define PCLK_SPI1		342
+#define PCLK_SARADC		343
+#define PCLK_TSADC		344
+#define PCLK_TIMER		345
+#define PCLK_OTP_NS		346
+#define PCLK_WDT_NS		347
+#define PCLK_GPIO1		348
+#define PCLK_GPIO2		349
+#define PCLK_GPIO3		350
+#define PCLK_ISP		351
+#define PCLK_CIF		352
+#define PCLK_OTP_PHY		353
+
+#define CLK_NR_CLKS		(PCLK_OTP_PHY + 1)
+
+/* pmu-clocks indices */
+
+#define PLL_GPLL		1
+
+#define SCLK_RTC32K_PMU		4
+#define SCLK_WIFI_PMU		5
+#define SCLK_UART0_PMU		6
+#define SCLK_PVTM_PMU		7
+#define PCLK_PMU_PRE		8
+#define SCLK_REF24M_PMU		9
+#define SCLK_USBPHY_REF		10
+#define SCLK_MIPIDSIPHY_REF	11
+
+#define XIN24M_DIV		12
+
+#define PCLK_GPIO0_PMU		20
+#define PCLK_UART0_PMU		21
+
+#define CLKPMU_NR_CLKS		(PCLK_UART0_PMU + 1)
+
+/* soft-reset indices */
+#define SRST_CORE0_PO		0
+#define SRST_CORE1_PO		1
+#define SRST_CORE2_PO		2
+#define SRST_CORE3_PO		3
+#define SRST_CORE0		4
+#define SRST_CORE1		5
+#define SRST_CORE2		6
+#define SRST_CORE3		7
+#define SRST_CORE0_DBG		8
+#define SRST_CORE1_DBG		9
+#define SRST_CORE2_DBG		10
+#define SRST_CORE3_DBG		11
+#define SRST_TOPDBG		12
+#define SRST_CORE_NOC		13
+#define SRST_STRC_A		14
+#define SRST_L2C		15
+
+#define SRST_DAP		16
+#define SRST_CORE_PVTM		17
+#define SRST_GPU		18
+#define SRST_GPU_NIU		19
+#define SRST_UPCTL2		20
+#define SRST_UPCTL2_A		21
+#define SRST_UPCTL2_P		22
+#define SRST_MSCH		23
+#define SRST_MSCH_P		24
+#define SRST_DDRMON_P		25
+#define SRST_DDRSTDBY_P		26
+#define SRST_DDRSTDBY		27
+#define SRST_DDRGRF_p		28
+#define SRST_AXI_SPLIT_A	29
+#define SRST_AXI_CMD_A		30
+#define SRST_AXI_CMD_P		31
+
+#define SRST_DDRPHY		32
+#define SRST_DDRPHYDIV		33
+#define SRST_DDRPHY_P		34
+#define SRST_VPU_A		36
+#define SRST_VPU_NIU_A		37
+#define SRST_VPU_H		38
+#define SRST_VPU_NIU_H		39
+#define SRST_VI_NIU_A		40
+#define SRST_VI_NIU_H		41
+#define SRST_ISP_H		42
+#define SRST_ISP		43
+#define SRST_CIF_A		44
+#define SRST_CIF_H		45
+#define SRST_CIF_PCLKIN		46
+#define SRST_MIPICSIPHY_P	47
+
+#define SRST_VO_NIU_A		48
+#define SRST_VO_NIU_H		49
+#define SRST_VO_NIU_P		50
+#define SRST_VOPB_A		51
+#define SRST_VOPB_H		52
+#define SRST_VOPB		53
+#define SRST_PWM_VOPB		54
+#define SRST_VOPL_A		55
+#define SRST_VOPL_H		56
+#define SRST_VOPL		57
+#define SRST_RGA_A		58
+#define SRST_RGA_H		59
+#define SRST_RGA		60
+#define SRST_MIPIDSI_HOST_P	61
+#define SRST_MIPIDSIPHY_P	62
+#define SRST_VPU_CORE		63
+
+#define SRST_PERI_NIU_A		64
+#define SRST_USB_NIU_H		65
+#define SRST_USB2OTG_H		66
+#define SRST_USB2OTG		67
+#define SRST_USB2OTG_ADP	68
+#define SRST_USB2HOST_H		69
+#define SRST_USB2HOST_ARB_H	70
+#define SRST_USB2HOST_AUX_H	71
+#define SRST_USB2HOST_EHCI	72
+#define SRST_USB2HOST		73
+#define SRST_USBPHYPOR		74
+#define SRST_USBPHY_OTG_PORT	75
+#define SRST_USBPHY_HOST_PORT	76
+#define SRST_USBPHY_GRF		77
+#define SRST_CPU_BOOST_P	78
+#define SRST_CPU_BOOST		79
+
+#define SRST_MMC_NAND_NIU_H	80
+#define SRST_SDIO_H		81
+#define SRST_EMMC_H		82
+#define SRST_SFC_H		83
+#define SRST_SFC		84
+#define SRST_SDCARD_NIU_H	85
+#define SRST_SDMMC_H		86
+#define SRST_NANDC_H		89
+#define SRST_NANDC		90
+#define SRST_GMAC_NIU_A		92
+#define SRST_GMAC_NIU_P		93
+#define SRST_GMAC_A		94
+
+#define SRST_PMU_NIU_P		96
+#define SRST_PMU_SGRF_P		97
+#define SRST_PMU_GRF_P		98
+#define SRST_PMU		99
+#define SRST_PMU_MEM_P		100
+#define SRST_PMU_GPIO0_P	101
+#define SRST_PMU_UART0_P	102
+#define SRST_PMU_CRU_P		103
+#define SRST_PMU_PVTM		104
+#define SRST_PMU_UART		105
+#define SRST_PMU_NIU_H		106
+#define SRST_PMU_DDR_FAIL_SAVE	107
+#define SRST_PMU_CORE_PERF_A	108
+#define SRST_PMU_CORE_GRF_P	109
+#define SRST_PMU_GPU_PERF_A	110
+#define SRST_PMU_GPU_GRF_P	111
+
+#define SRST_CRYPTO_NIU_A	112
+#define SRST_CRYPTO_NIU_H	113
+#define SRST_CRYPTO_A		114
+#define SRST_CRYPTO_H		115
+#define SRST_CRYPTO		116
+#define SRST_CRYPTO_APK		117
+#define SRST_BUS_NIU_H		120
+#define SRST_USB_NIU_P		121
+#define SRST_BUS_TOP_NIU_P	122
+#define SRST_INTMEM_A		123
+#define SRST_GIC_A		124
+#define SRST_ROM_H		126
+#define SRST_DCF_A		127
+
+#define SRST_DCF_P		128
+#define SRST_PDM_H		129
+#define SRST_PDM		130
+#define SRST_I2S0_H		131
+#define SRST_I2S0_TX		132
+#define SRST_I2S1_H		133
+#define SRST_I2S1		134
+#define SRST_I2S2_H		135
+#define SRST_I2S2		136
+#define SRST_UART1_P		137
+#define SRST_UART1		138
+#define SRST_UART2_P		139
+#define SRST_UART2		140
+#define SRST_UART3_P		141
+#define SRST_UART3		142
+#define SRST_UART4_P		143
+
+#define SRST_UART4		144
+#define SRST_UART5_P		145
+#define SRST_UART5		146
+#define SRST_I2C0_P		147
+#define SRST_I2C0		148
+#define SRST_I2C1_P		149
+#define SRST_I2C1		150
+#define SRST_I2C2_P		151
+#define SRST_I2C2		152
+#define SRST_I2C3_P		153
+#define SRST_I2C3		154
+#define SRST_PWM0_P		157
+#define SRST_PWM0		158
+#define SRST_PWM1_P		159
+
+#define SRST_PWM1		160
+#define SRST_SPI0_P		161
+#define SRST_SPI0		162
+#define SRST_SPI1_P		163
+#define SRST_SPI1		164
+#define SRST_SARADC_P		165
+#define SRST_SARADC		166
+#define SRST_TSADC_P		167
+#define SRST_TSADC		168
+#define SRST_TIMER_P		169
+#define SRST_TIMER0		170
+#define SRST_TIMER1		171
+#define SRST_TIMER2		172
+#define SRST_TIMER3		173
+#define SRST_TIMER4		174
+#define SRST_TIMER5		175
+
+#define SRST_OTP_NS_P		176
+#define SRST_OTP_NS_SBPI	177
+#define SRST_OTP_NS_USR		178
+#define SRST_OTP_PHY_P		179
+#define SRST_OTP_PHY		180
+#define SRST_WDT_NS_P		181
+#define SRST_GPIO1_P		182
+#define SRST_GPIO2_P		183
+#define SRST_GPIO3_P		184
+#define SRST_SGRF_P		185
+#define SRST_GRF_P		186
+#define SRST_I2S0_RX		191
+
+#endif
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/pxa-clock.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/pxa-clock.h
new file mode 100644
index 0000000000000000000000000000000000000000..0b0fd2b015389f0c4911aca6d97a0032ca0f6f98
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/pxa-clock.h
@@ -0,0 +1,78 @@
+/*
+ * Inspired by original work from pxa2xx-regs.h by Nicolas Pitre
+ * Copyright (C) 2014 Robert Jarzmik
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_PXA2XX_H__
+#define __DT_BINDINGS_CLOCK_PXA2XX_H__
+
+#define CLK_NONE 0
+#define CLK_1WIRE 1
+#define CLK_AC97 2
+#define CLK_AC97CONF 3
+#define CLK_ASSP 4
+#define CLK_BOOT 5
+#define CLK_BTUART 6
+#define CLK_CAMERA 7
+#define CLK_CIR 8
+#define CLK_CORE 9
+#define CLK_DMC 10
+#define CLK_FFUART 11
+#define CLK_FICP 12
+#define CLK_GPIO 13
+#define CLK_HSIO2 14
+#define CLK_HWUART 15
+#define CLK_I2C 16
+#define CLK_I2S 17
+#define CLK_IM 18
+#define CLK_INC 19
+#define CLK_ISC 20
+#define CLK_KEYPAD 21
+#define CLK_LCD 22
+#define CLK_MEMC 23
+#define CLK_MEMSTK 24
+#define CLK_MINI_IM 25
+#define CLK_MINI_LCD 26
+#define CLK_MMC 27
+#define CLK_MMC1 28
+#define CLK_MMC2 29
+#define CLK_MMC3 30
+#define CLK_MSL 31
+#define CLK_MSL0 32
+#define CLK_MVED 33
+#define CLK_NAND 34
+#define CLK_NSSP 35
+#define CLK_OSTIMER 36
+#define CLK_PWM0 37
+#define CLK_PWM1 38
+#define CLK_PWM2 39
+#define CLK_PWM3 40
+#define CLK_PWRI2C 41
+#define CLK_PXA300_GCU 42
+#define CLK_PXA320_GCU 43
+#define CLK_SMC 44
+#define CLK_SSP 45
+#define CLK_SSP1 46
+#define CLK_SSP2 47
+#define CLK_SSP3 48
+#define CLK_SSP4 49
+#define CLK_STUART 50
+#define CLK_TOUCH 51
+#define CLK_TPM 52
+#define CLK_UDC 53
+#define CLK_USB 54
+#define CLK_USB2 55
+#define CLK_USBH 56
+#define CLK_USBHOST 57
+#define CLK_USIM 58
+#define CLK_USIM1 59
+#define CLK_USMI0 60
+#define CLK_OSC32k768 61
+#define CLK_MAX 62
+
+#endif
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/qcom,dispcc-sdm845.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/qcom,dispcc-sdm845.h
new file mode 100644
index 0000000000000000000000000000000000000000..11eed4bc964646e9553ff76a29457b050caa2471
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/qcom,dispcc-sdm845.h
@@ -0,0 +1,45 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_CLK_SDM_DISP_CC_SDM845_H
+#define _DT_BINDINGS_CLK_SDM_DISP_CC_SDM845_H
+
+/* DISP_CC clock registers */
+#define DISP_CC_MDSS_AHB_CLK					0
+#define DISP_CC_MDSS_AXI_CLK					1
+#define DISP_CC_MDSS_BYTE0_CLK					2
+#define DISP_CC_MDSS_BYTE0_CLK_SRC				3
+#define DISP_CC_MDSS_BYTE0_INTF_CLK				4
+#define DISP_CC_MDSS_BYTE1_CLK					5
+#define DISP_CC_MDSS_BYTE1_CLK_SRC				6
+#define DISP_CC_MDSS_BYTE1_INTF_CLK				7
+#define DISP_CC_MDSS_ESC0_CLK					8
+#define DISP_CC_MDSS_ESC0_CLK_SRC				9
+#define DISP_CC_MDSS_ESC1_CLK					10
+#define DISP_CC_MDSS_ESC1_CLK_SRC				11
+#define DISP_CC_MDSS_MDP_CLK					12
+#define DISP_CC_MDSS_MDP_CLK_SRC				13
+#define DISP_CC_MDSS_MDP_LUT_CLK				14
+#define DISP_CC_MDSS_PCLK0_CLK					15
+#define DISP_CC_MDSS_PCLK0_CLK_SRC				16
+#define DISP_CC_MDSS_PCLK1_CLK					17
+#define DISP_CC_MDSS_PCLK1_CLK_SRC				18
+#define DISP_CC_MDSS_ROT_CLK					19
+#define DISP_CC_MDSS_ROT_CLK_SRC				20
+#define DISP_CC_MDSS_RSCC_AHB_CLK				21
+#define DISP_CC_MDSS_RSCC_VSYNC_CLK				22
+#define DISP_CC_MDSS_VSYNC_CLK					23
+#define DISP_CC_MDSS_VSYNC_CLK_SRC				24
+#define DISP_CC_PLL0						25
+#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC				26
+#define DISP_CC_MDSS_BYTE1_DIV_CLK_SRC				27
+
+/* DISP_CC Reset */
+#define DISP_CC_MDSS_RSCC_BCR					0
+
+/* DISP_CC GDSCR */
+#define MDSS_GDSC						0
+
+#endif
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/qcom,gcc-apq8084.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/qcom,gcc-apq8084.h
new file mode 100644
index 0000000000000000000000000000000000000000..5aa7ebeae411091ef5c073d4c91651242fc723c3
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/qcom,gcc-apq8084.h
@@ -0,0 +1,357 @@
+/*
+ * Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_CLK_APQ_GCC_8084_H
+#define _DT_BINDINGS_CLK_APQ_GCC_8084_H
+
+#define GPLL0						0
+#define GPLL0_VOTE					1
+#define GPLL1						2
+#define GPLL1_VOTE					3
+#define GPLL2						4
+#define GPLL2_VOTE					5
+#define GPLL3						6
+#define GPLL3_VOTE					7
+#define GPLL4						8
+#define GPLL4_VOTE					9
+#define CONFIG_NOC_CLK_SRC				10
+#define PERIPH_NOC_CLK_SRC				11
+#define SYSTEM_NOC_CLK_SRC				12
+#define BLSP_UART_SIM_CLK_SRC				13
+#define QDSS_TSCTR_CLK_SRC				14
+#define UFS_AXI_CLK_SRC					15
+#define RPM_CLK_SRC					16
+#define KPSS_AHB_CLK_SRC				17
+#define QDSS_AT_CLK_SRC					18
+#define BIMC_DDR_CLK_SRC				19
+#define USB30_MASTER_CLK_SRC				20
+#define USB30_SEC_MASTER_CLK_SRC			21
+#define USB_HSIC_AHB_CLK_SRC				22
+#define MMSS_BIMC_GFX_CLK_SRC				23
+#define QDSS_STM_CLK_SRC				24
+#define ACC_CLK_SRC					25
+#define SEC_CTRL_CLK_SRC				26
+#define BLSP1_QUP1_I2C_APPS_CLK_SRC			27
+#define BLSP1_QUP1_SPI_APPS_CLK_SRC			28
+#define BLSP1_QUP2_I2C_APPS_CLK_SRC			29
+#define BLSP1_QUP2_SPI_APPS_CLK_SRC			30
+#define BLSP1_QUP3_I2C_APPS_CLK_SRC			31
+#define BLSP1_QUP3_SPI_APPS_CLK_SRC			32
+#define BLSP1_QUP4_I2C_APPS_CLK_SRC			33
+#define BLSP1_QUP4_SPI_APPS_CLK_SRC			34
+#define BLSP1_QUP5_I2C_APPS_CLK_SRC			35
+#define BLSP1_QUP5_SPI_APPS_CLK_SRC			36
+#define BLSP1_QUP6_I2C_APPS_CLK_SRC			37
+#define BLSP1_QUP6_SPI_APPS_CLK_SRC			38
+#define BLSP1_UART1_APPS_CLK_SRC			39
+#define BLSP1_UART2_APPS_CLK_SRC			40
+#define BLSP1_UART3_APPS_CLK_SRC			41
+#define BLSP1_UART4_APPS_CLK_SRC			42
+#define BLSP1_UART5_APPS_CLK_SRC			43
+#define BLSP1_UART6_APPS_CLK_SRC			44
+#define BLSP2_QUP1_I2C_APPS_CLK_SRC			45
+#define BLSP2_QUP1_SPI_APPS_CLK_SRC			46
+#define BLSP2_QUP2_I2C_APPS_CLK_SRC			47
+#define BLSP2_QUP2_SPI_APPS_CLK_SRC			48
+#define BLSP2_QUP3_I2C_APPS_CLK_SRC			49
+#define BLSP2_QUP3_SPI_APPS_CLK_SRC			50
+#define BLSP2_QUP4_I2C_APPS_CLK_SRC			51
+#define BLSP2_QUP4_SPI_APPS_CLK_SRC			52
+#define BLSP2_QUP5_I2C_APPS_CLK_SRC			53
+#define BLSP2_QUP5_SPI_APPS_CLK_SRC			54
+#define BLSP2_QUP6_I2C_APPS_CLK_SRC			55
+#define BLSP2_QUP6_SPI_APPS_CLK_SRC			56
+#define BLSP2_UART1_APPS_CLK_SRC			57
+#define BLSP2_UART2_APPS_CLK_SRC			58
+#define BLSP2_UART3_APPS_CLK_SRC			59
+#define BLSP2_UART4_APPS_CLK_SRC			60
+#define BLSP2_UART5_APPS_CLK_SRC			61
+#define BLSP2_UART6_APPS_CLK_SRC			62
+#define CE1_CLK_SRC					63
+#define CE2_CLK_SRC					64
+#define CE3_CLK_SRC					65
+#define GP1_CLK_SRC					66
+#define GP2_CLK_SRC					67
+#define GP3_CLK_SRC					68
+#define PDM2_CLK_SRC					69
+#define QDSS_TRACECLKIN_CLK_SRC				70
+#define RBCPR_CLK_SRC					71
+#define SATA_ASIC0_CLK_SRC				72
+#define SATA_PMALIVE_CLK_SRC				73
+#define SATA_RX_CLK_SRC					74
+#define SATA_RX_OOB_CLK_SRC				75
+#define SDCC1_APPS_CLK_SRC				76
+#define SDCC2_APPS_CLK_SRC				77
+#define SDCC3_APPS_CLK_SRC				78
+#define SDCC4_APPS_CLK_SRC				79
+#define GCC_SNOC_BUS_TIMEOUT0_AHB_CLK			80
+#define SPMI_AHB_CLK_SRC				81
+#define SPMI_SER_CLK_SRC				82
+#define TSIF_REF_CLK_SRC				83
+#define USB30_MOCK_UTMI_CLK_SRC				84
+#define USB30_SEC_MOCK_UTMI_CLK_SRC			85
+#define USB_HS_SYSTEM_CLK_SRC				86
+#define USB_HSIC_CLK_SRC				87
+#define USB_HSIC_IO_CAL_CLK_SRC				88
+#define USB_HSIC_MOCK_UTMI_CLK_SRC			89
+#define USB_HSIC_SYSTEM_CLK_SRC				90
+#define GCC_BAM_DMA_AHB_CLK				91
+#define GCC_BAM_DMA_INACTIVITY_TIMERS_CLK		92
+#define DDR_CLK_SRC					93
+#define GCC_BIMC_CFG_AHB_CLK				94
+#define GCC_BIMC_CLK					95
+#define GCC_BIMC_KPSS_AXI_CLK				96
+#define GCC_BIMC_SLEEP_CLK				97
+#define GCC_BIMC_SYSNOC_AXI_CLK				98
+#define GCC_BIMC_XO_CLK					99
+#define GCC_BLSP1_AHB_CLK				100
+#define GCC_BLSP1_SLEEP_CLK				101
+#define GCC_BLSP1_QUP1_I2C_APPS_CLK			102
+#define GCC_BLSP1_QUP1_SPI_APPS_CLK			103
+#define GCC_BLSP1_QUP2_I2C_APPS_CLK			104
+#define GCC_BLSP1_QUP2_SPI_APPS_CLK			105
+#define GCC_BLSP1_QUP3_I2C_APPS_CLK			106
+#define GCC_BLSP1_QUP3_SPI_APPS_CLK			107
+#define GCC_BLSP1_QUP4_I2C_APPS_CLK			108
+#define GCC_BLSP1_QUP4_SPI_APPS_CLK			109
+#define GCC_BLSP1_QUP5_I2C_APPS_CLK			110
+#define GCC_BLSP1_QUP5_SPI_APPS_CLK			111
+#define GCC_BLSP1_QUP6_I2C_APPS_CLK			112
+#define GCC_BLSP1_QUP6_SPI_APPS_CLK			113
+#define GCC_BLSP1_UART1_APPS_CLK			114
+#define GCC_BLSP1_UART1_SIM_CLK				115
+#define GCC_BLSP1_UART2_APPS_CLK			116
+#define GCC_BLSP1_UART2_SIM_CLK				117
+#define GCC_BLSP1_UART3_APPS_CLK			118
+#define GCC_BLSP1_UART3_SIM_CLK				119
+#define GCC_BLSP1_UART4_APPS_CLK			120
+#define GCC_BLSP1_UART4_SIM_CLK				121
+#define GCC_BLSP1_UART5_APPS_CLK			122
+#define GCC_BLSP1_UART5_SIM_CLK				123
+#define GCC_BLSP1_UART6_APPS_CLK			124
+#define GCC_BLSP1_UART6_SIM_CLK				125
+#define GCC_BLSP2_AHB_CLK				126
+#define GCC_BLSP2_SLEEP_CLK				127
+#define GCC_BLSP2_QUP1_I2C_APPS_CLK			128
+#define GCC_BLSP2_QUP1_SPI_APPS_CLK			129
+#define GCC_BLSP2_QUP2_I2C_APPS_CLK			130
+#define GCC_BLSP2_QUP2_SPI_APPS_CLK			131
+#define GCC_BLSP2_QUP3_I2C_APPS_CLK			132
+#define GCC_BLSP2_QUP3_SPI_APPS_CLK			133
+#define GCC_BLSP2_QUP4_I2C_APPS_CLK			134
+#define GCC_BLSP2_QUP4_SPI_APPS_CLK			135
+#define GCC_BLSP2_QUP5_I2C_APPS_CLK			136
+#define GCC_BLSP2_QUP5_SPI_APPS_CLK			137
+#define GCC_BLSP2_QUP6_I2C_APPS_CLK			138
+#define GCC_BLSP2_QUP6_SPI_APPS_CLK			139
+#define GCC_BLSP2_UART1_APPS_CLK			140
+#define GCC_BLSP2_UART1_SIM_CLK				141
+#define GCC_BLSP2_UART2_APPS_CLK			142
+#define GCC_BLSP2_UART2_SIM_CLK				143
+#define GCC_BLSP2_UART3_APPS_CLK			144
+#define GCC_BLSP2_UART3_SIM_CLK				145
+#define GCC_BLSP2_UART4_APPS_CLK			146
+#define GCC_BLSP2_UART4_SIM_CLK				147
+#define GCC_BLSP2_UART5_APPS_CLK			148
+#define GCC_BLSP2_UART5_SIM_CLK				149
+#define GCC_BLSP2_UART6_APPS_CLK			150
+#define GCC_BLSP2_UART6_SIM_CLK				151
+#define GCC_BOOT_ROM_AHB_CLK				152
+#define GCC_CE1_AHB_CLK					153
+#define GCC_CE1_AXI_CLK					154
+#define GCC_CE1_CLK					155
+#define GCC_CE2_AHB_CLK					156
+#define GCC_CE2_AXI_CLK					157
+#define GCC_CE2_CLK					158
+#define GCC_CE3_AHB_CLK					159
+#define GCC_CE3_AXI_CLK					160
+#define GCC_CE3_CLK					161
+#define GCC_CNOC_BUS_TIMEOUT0_AHB_CLK			162
+#define GCC_CNOC_BUS_TIMEOUT1_AHB_CLK			163
+#define GCC_CNOC_BUS_TIMEOUT2_AHB_CLK			164
+#define GCC_CNOC_BUS_TIMEOUT3_AHB_CLK			165
+#define GCC_CNOC_BUS_TIMEOUT4_AHB_CLK			166
+#define GCC_CNOC_BUS_TIMEOUT5_AHB_CLK			167
+#define GCC_CNOC_BUS_TIMEOUT6_AHB_CLK			168
+#define GCC_CNOC_BUS_TIMEOUT7_AHB_CLK			169
+#define GCC_CFG_NOC_AHB_CLK				170
+#define GCC_CFG_NOC_DDR_CFG_CLK				171
+#define GCC_CFG_NOC_RPM_AHB_CLK				172
+#define GCC_COPSS_SMMU_AHB_CLK				173
+#define GCC_COPSS_SMMU_AXI_CLK				174
+#define GCC_DCD_XO_CLK					175
+#define GCC_BIMC_DDR_CH0_CLK				176
+#define GCC_BIMC_DDR_CH1_CLK				177
+#define GCC_BIMC_DDR_CPLL0_CLK				178
+#define GCC_BIMC_DDR_CPLL1_CLK				179
+#define GCC_BIMC_GFX_CLK				180
+#define GCC_DDR_DIM_CFG_CLK				181
+#define GCC_DDR_DIM_SLEEP_CLK				182
+#define GCC_DEHR_CLK					183
+#define GCC_AHB_CLK					184
+#define GCC_IM_SLEEP_CLK				185
+#define GCC_XO_CLK					186
+#define GCC_XO_DIV4_CLK					187
+#define GCC_GP1_CLK					188
+#define GCC_GP2_CLK					189
+#define GCC_GP3_CLK					190
+#define GCC_IMEM_AXI_CLK				191
+#define GCC_IMEM_CFG_AHB_CLK				192
+#define GCC_KPSS_AHB_CLK				193
+#define GCC_KPSS_AXI_CLK				194
+#define GCC_LPASS_MPORT_AXI_CLK				195
+#define GCC_LPASS_Q6_AXI_CLK				196
+#define GCC_LPASS_SWAY_CLK				197
+#define GCC_MMSS_BIMC_GFX_CLK				198
+#define GCC_MMSS_NOC_AT_CLK				199
+#define GCC_MMSS_NOC_CFG_AHB_CLK			200
+#define GCC_MMSS_VPU_MAPLE_SYS_NOC_AXI_CLK		201
+#define GCC_OCMEM_NOC_CFG_AHB_CLK			202
+#define GCC_OCMEM_SYS_NOC_AXI_CLK			203
+#define GCC_MPM_AHB_CLK					204
+#define GCC_MSG_RAM_AHB_CLK				205
+#define GCC_NOC_CONF_XPU_AHB_CLK			206
+#define GCC_PDM2_CLK					207
+#define GCC_PDM_AHB_CLK					208
+#define GCC_PDM_XO4_CLK					209
+#define GCC_PERIPH_NOC_AHB_CLK				210
+#define GCC_PERIPH_NOC_AT_CLK				211
+#define GCC_PERIPH_NOC_CFG_AHB_CLK			212
+#define GCC_PERIPH_NOC_USB_HSIC_AHB_CLK			213
+#define GCC_PERIPH_NOC_MPU_CFG_AHB_CLK			214
+#define GCC_PERIPH_XPU_AHB_CLK				215
+#define GCC_PNOC_BUS_TIMEOUT0_AHB_CLK			216
+#define GCC_PNOC_BUS_TIMEOUT1_AHB_CLK			217
+#define GCC_PNOC_BUS_TIMEOUT2_AHB_CLK			218
+#define GCC_PNOC_BUS_TIMEOUT3_AHB_CLK			219
+#define GCC_PNOC_BUS_TIMEOUT4_AHB_CLK			220
+#define GCC_PRNG_AHB_CLK				221
+#define GCC_QDSS_AT_CLK					222
+#define GCC_QDSS_CFG_AHB_CLK				223
+#define GCC_QDSS_DAP_AHB_CLK				224
+#define GCC_QDSS_DAP_CLK				225
+#define GCC_QDSS_ETR_USB_CLK				226
+#define GCC_QDSS_STM_CLK				227
+#define GCC_QDSS_TRACECLKIN_CLK				228
+#define GCC_QDSS_TSCTR_DIV16_CLK			229
+#define GCC_QDSS_TSCTR_DIV2_CLK				230
+#define GCC_QDSS_TSCTR_DIV3_CLK				231
+#define GCC_QDSS_TSCTR_DIV4_CLK				232
+#define GCC_QDSS_TSCTR_DIV8_CLK				233
+#define GCC_QDSS_RBCPR_XPU_AHB_CLK			234
+#define GCC_RBCPR_AHB_CLK				235
+#define GCC_RBCPR_CLK					236
+#define GCC_RPM_BUS_AHB_CLK				237
+#define GCC_RPM_PROC_HCLK				238
+#define GCC_RPM_SLEEP_CLK				239
+#define GCC_RPM_TIMER_CLK				240
+#define GCC_SATA_ASIC0_CLK				241
+#define GCC_SATA_AXI_CLK				242
+#define GCC_SATA_CFG_AHB_CLK				243
+#define GCC_SATA_PMALIVE_CLK				244
+#define GCC_SATA_RX_CLK					245
+#define GCC_SATA_RX_OOB_CLK				246
+#define GCC_SDCC1_AHB_CLK				247
+#define GCC_SDCC1_APPS_CLK				248
+#define GCC_SDCC1_CDCCAL_FF_CLK				249
+#define GCC_SDCC1_CDCCAL_SLEEP_CLK			250
+#define GCC_SDCC2_AHB_CLK				251
+#define GCC_SDCC2_APPS_CLK				252
+#define GCC_SDCC2_INACTIVITY_TIMERS_CLK			253
+#define GCC_SDCC3_AHB_CLK				254
+#define GCC_SDCC3_APPS_CLK				255
+#define GCC_SDCC3_INACTIVITY_TIMERS_CLK			256
+#define GCC_SDCC4_AHB_CLK				257
+#define GCC_SDCC4_APPS_CLK				258
+#define GCC_SDCC4_INACTIVITY_TIMERS_CLK			259
+#define GCC_SEC_CTRL_ACC_CLK				260
+#define GCC_SEC_CTRL_AHB_CLK				261
+#define GCC_SEC_CTRL_BOOT_ROM_PATCH_CLK			262
+#define GCC_SEC_CTRL_CLK				263
+#define GCC_SEC_CTRL_SENSE_CLK				264
+#define GCC_SNOC_BUS_TIMEOUT2_AHB_CLK			265
+#define GCC_SNOC_BUS_TIMEOUT3_AHB_CLK			266
+#define GCC_SPDM_BIMC_CY_CLK				267
+#define GCC_SPDM_CFG_AHB_CLK				268
+#define GCC_SPDM_DEBUG_CY_CLK				269
+#define GCC_SPDM_FF_CLK					270
+#define GCC_SPDM_MSTR_AHB_CLK				271
+#define GCC_SPDM_PNOC_CY_CLK				272
+#define GCC_SPDM_RPM_CY_CLK				273
+#define GCC_SPDM_SNOC_CY_CLK				274
+#define GCC_SPMI_AHB_CLK				275
+#define GCC_SPMI_CNOC_AHB_CLK				276
+#define GCC_SPMI_SER_CLK				277
+#define GCC_SPSS_AHB_CLK				278
+#define GCC_SNOC_CNOC_AHB_CLK				279
+#define GCC_SNOC_PNOC_AHB_CLK				280
+#define GCC_SYS_NOC_AT_CLK				281
+#define GCC_SYS_NOC_AXI_CLK				282
+#define GCC_SYS_NOC_KPSS_AHB_CLK			283
+#define GCC_SYS_NOC_QDSS_STM_AXI_CLK			284
+#define GCC_SYS_NOC_UFS_AXI_CLK				285
+#define GCC_SYS_NOC_USB3_AXI_CLK			286
+#define GCC_SYS_NOC_USB3_SEC_AXI_CLK			287
+#define GCC_TCSR_AHB_CLK				288
+#define GCC_TLMM_AHB_CLK				289
+#define GCC_TLMM_CLK					290
+#define GCC_TSIF_AHB_CLK				291
+#define GCC_TSIF_INACTIVITY_TIMERS_CLK			292
+#define GCC_TSIF_REF_CLK				293
+#define GCC_UFS_AHB_CLK					294
+#define GCC_UFS_AXI_CLK					295
+#define GCC_UFS_RX_CFG_CLK				296
+#define GCC_UFS_RX_SYMBOL_0_CLK				297
+#define GCC_UFS_RX_SYMBOL_1_CLK				298
+#define GCC_UFS_TX_CFG_CLK				299
+#define GCC_UFS_TX_SYMBOL_0_CLK				300
+#define GCC_UFS_TX_SYMBOL_1_CLK				301
+#define GCC_USB2A_PHY_SLEEP_CLK				302
+#define GCC_USB2B_PHY_SLEEP_CLK				303
+#define GCC_USB30_MASTER_CLK				304
+#define GCC_USB30_MOCK_UTMI_CLK				305
+#define GCC_USB30_SLEEP_CLK				306
+#define GCC_USB30_SEC_MASTER_CLK			307
+#define GCC_USB30_SEC_MOCK_UTMI_CLK			308
+#define GCC_USB30_SEC_SLEEP_CLK				309
+#define GCC_USB_HS_AHB_CLK				310
+#define GCC_USB_HS_INACTIVITY_TIMERS_CLK		311
+#define GCC_USB_HS_SYSTEM_CLK				312
+#define GCC_USB_HSIC_AHB_CLK				313
+#define GCC_USB_HSIC_CLK				314
+#define GCC_USB_HSIC_IO_CAL_CLK				315
+#define GCC_USB_HSIC_IO_CAL_SLEEP_CLK			316
+#define GCC_USB_HSIC_MOCK_UTMI_CLK			317
+#define GCC_USB_HSIC_SYSTEM_CLK				318
+#define PCIE_0_AUX_CLK_SRC				319
+#define PCIE_0_PIPE_CLK_SRC				320
+#define PCIE_1_AUX_CLK_SRC				321
+#define PCIE_1_PIPE_CLK_SRC				322
+#define GCC_PCIE_0_AUX_CLK				323
+#define GCC_PCIE_0_CFG_AHB_CLK				324
+#define GCC_PCIE_0_MSTR_AXI_CLK				325
+#define GCC_PCIE_0_PIPE_CLK				326
+#define GCC_PCIE_0_SLV_AXI_CLK				327
+#define GCC_PCIE_1_AUX_CLK				328
+#define GCC_PCIE_1_CFG_AHB_CLK				329
+#define GCC_PCIE_1_MSTR_AXI_CLK				330
+#define GCC_PCIE_1_PIPE_CLK				331
+#define GCC_PCIE_1_SLV_AXI_CLK				332
+
+/* gdscs */
+#define USB_HS_HSIC_GDSC				0
+#define PCIE0_GDSC					1
+#define PCIE1_GDSC					2
+#define USB30_GDSC					3
+
+#endif
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/qcom,gcc-ipq4019.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/qcom,gcc-ipq4019.h
new file mode 100644
index 0000000000000000000000000000000000000000..7e8a7be6dcdaa90051155131f93e119bdaa3f71a
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/qcom,gcc-ipq4019.h
@@ -0,0 +1,169 @@
+/* Copyright (c) 2015 The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+#ifndef __QCOM_CLK_IPQ4019_H__
+#define __QCOM_CLK_IPQ4019_H__
+
+#define GCC_DUMMY_CLK					0
+#define AUDIO_CLK_SRC					1
+#define BLSP1_QUP1_I2C_APPS_CLK_SRC			2
+#define BLSP1_QUP1_SPI_APPS_CLK_SRC			3
+#define BLSP1_QUP2_I2C_APPS_CLK_SRC			4
+#define BLSP1_QUP2_SPI_APPS_CLK_SRC			5
+#define BLSP1_UART1_APPS_CLK_SRC			6
+#define BLSP1_UART2_APPS_CLK_SRC			7
+#define GCC_USB3_MOCK_UTMI_CLK_SRC			8
+#define GCC_APPS_CLK_SRC				9
+#define GCC_APPS_AHB_CLK_SRC				10
+#define GP1_CLK_SRC					11
+#define GP2_CLK_SRC					12
+#define GP3_CLK_SRC					13
+#define SDCC1_APPS_CLK_SRC				14
+#define FEPHY_125M_DLY_CLK_SRC				15
+#define WCSS2G_CLK_SRC					16
+#define WCSS5G_CLK_SRC					17
+#define GCC_APSS_AHB_CLK				18
+#define GCC_AUDIO_AHB_CLK				19
+#define GCC_AUDIO_PWM_CLK				20
+#define GCC_BLSP1_AHB_CLK				21
+#define GCC_BLSP1_QUP1_I2C_APPS_CLK			22
+#define GCC_BLSP1_QUP1_SPI_APPS_CLK			23
+#define GCC_BLSP1_QUP2_I2C_APPS_CLK			24
+#define GCC_BLSP1_QUP2_SPI_APPS_CLK			25
+#define GCC_BLSP1_UART1_APPS_CLK			26
+#define GCC_BLSP1_UART2_APPS_CLK			27
+#define GCC_DCD_XO_CLK					28
+#define GCC_GP1_CLK					29
+#define GCC_GP2_CLK					30
+#define GCC_GP3_CLK					31
+#define GCC_BOOT_ROM_AHB_CLK				32
+#define GCC_CRYPTO_AHB_CLK				33
+#define GCC_CRYPTO_AXI_CLK				34
+#define GCC_CRYPTO_CLK					35
+#define GCC_ESS_CLK					36
+#define GCC_IMEM_AXI_CLK				37
+#define GCC_IMEM_CFG_AHB_CLK				38
+#define GCC_PCIE_AHB_CLK				39
+#define GCC_PCIE_AXI_M_CLK				40
+#define GCC_PCIE_AXI_S_CLK				41
+#define GCC_PCNOC_AHB_CLK				42
+#define GCC_PRNG_AHB_CLK				43
+#define GCC_QPIC_AHB_CLK				44
+#define GCC_QPIC_CLK					45
+#define GCC_SDCC1_AHB_CLK				46
+#define GCC_SDCC1_APPS_CLK				47
+#define GCC_SNOC_PCNOC_AHB_CLK				48
+#define GCC_SYS_NOC_125M_CLK				49
+#define GCC_SYS_NOC_AXI_CLK				50
+#define GCC_TCSR_AHB_CLK				51
+#define GCC_TLMM_AHB_CLK				52
+#define GCC_USB2_MASTER_CLK				53
+#define GCC_USB2_SLEEP_CLK				54
+#define GCC_USB2_MOCK_UTMI_CLK				55
+#define GCC_USB3_MASTER_CLK				56
+#define GCC_USB3_SLEEP_CLK				57
+#define GCC_USB3_MOCK_UTMI_CLK				58
+#define GCC_WCSS2G_CLK					59
+#define GCC_WCSS2G_REF_CLK				60
+#define GCC_WCSS2G_RTC_CLK				61
+#define GCC_WCSS5G_CLK					62
+#define GCC_WCSS5G_REF_CLK				63
+#define GCC_WCSS5G_RTC_CLK				64
+#define GCC_APSS_DDRPLL_VCO				65
+#define GCC_SDCC_PLLDIV_CLK				66
+#define GCC_FEPLL_VCO					67
+#define GCC_FEPLL125_CLK				68
+#define GCC_FEPLL125DLY_CLK				69
+#define GCC_FEPLL200_CLK				70
+#define GCC_FEPLL500_CLK				71
+#define GCC_FEPLL_WCSS2G_CLK				72
+#define GCC_FEPLL_WCSS5G_CLK				73
+#define GCC_APSS_CPU_PLLDIV_CLK				74
+#define GCC_PCNOC_AHB_CLK_SRC				75
+
+#define WIFI0_CPU_INIT_RESET				0
+#define WIFI0_RADIO_SRIF_RESET				1
+#define WIFI0_RADIO_WARM_RESET				2
+#define WIFI0_RADIO_COLD_RESET				3
+#define WIFI0_CORE_WARM_RESET				4
+#define WIFI0_CORE_COLD_RESET				5
+#define WIFI1_CPU_INIT_RESET				6
+#define WIFI1_RADIO_SRIF_RESET				7
+#define WIFI1_RADIO_WARM_RESET				8
+#define WIFI1_RADIO_COLD_RESET				9
+#define WIFI1_CORE_WARM_RESET				10
+#define WIFI1_CORE_COLD_RESET				11
+#define USB3_UNIPHY_PHY_ARES				12
+#define USB3_HSPHY_POR_ARES				13
+#define USB3_HSPHY_S_ARES				14
+#define USB2_HSPHY_POR_ARES				15
+#define USB2_HSPHY_S_ARES				16
+#define PCIE_PHY_AHB_ARES				17
+#define PCIE_AHB_ARES					18
+#define PCIE_PWR_ARES					19
+#define PCIE_PIPE_STICKY_ARES				20
+#define PCIE_AXI_M_STICKY_ARES				21
+#define PCIE_PHY_ARES					22
+#define PCIE_PARF_XPU_ARES				23
+#define PCIE_AXI_S_XPU_ARES				24
+#define PCIE_AXI_M_VMIDMT_ARES				25
+#define PCIE_PIPE_ARES					26
+#define PCIE_AXI_S_ARES					27
+#define PCIE_AXI_M_ARES					28
+#define ESS_RESET					29
+#define GCC_BLSP1_BCR					30
+#define GCC_BLSP1_QUP1_BCR				31
+#define GCC_BLSP1_UART1_BCR				32
+#define GCC_BLSP1_QUP2_BCR				33
+#define GCC_BLSP1_UART2_BCR				34
+#define GCC_BIMC_BCR					35
+#define GCC_TLMM_BCR					36
+#define GCC_IMEM_BCR					37
+#define GCC_ESS_BCR					38
+#define GCC_PRNG_BCR					39
+#define GCC_BOOT_ROM_BCR				40
+#define GCC_CRYPTO_BCR					41
+#define GCC_SDCC1_BCR					42
+#define GCC_SEC_CTRL_BCR				43
+#define GCC_AUDIO_BCR					44
+#define GCC_QPIC_BCR					45
+#define GCC_PCIE_BCR					46
+#define GCC_USB2_BCR					47
+#define GCC_USB2_PHY_BCR				48
+#define GCC_USB3_BCR					49
+#define GCC_USB3_PHY_BCR				50
+#define GCC_SYSTEM_NOC_BCR				51
+#define GCC_PCNOC_BCR					52
+#define GCC_DCD_BCR					53
+#define GCC_SNOC_BUS_TIMEOUT0_BCR			54
+#define GCC_SNOC_BUS_TIMEOUT1_BCR			55
+#define GCC_SNOC_BUS_TIMEOUT2_BCR			56
+#define GCC_SNOC_BUS_TIMEOUT3_BCR			57
+#define GCC_PCNOC_BUS_TIMEOUT0_BCR			58
+#define GCC_PCNOC_BUS_TIMEOUT1_BCR			59
+#define GCC_PCNOC_BUS_TIMEOUT2_BCR			60
+#define GCC_PCNOC_BUS_TIMEOUT3_BCR			61
+#define GCC_PCNOC_BUS_TIMEOUT4_BCR			62
+#define GCC_PCNOC_BUS_TIMEOUT5_BCR			63
+#define GCC_PCNOC_BUS_TIMEOUT6_BCR			64
+#define GCC_PCNOC_BUS_TIMEOUT7_BCR			65
+#define GCC_PCNOC_BUS_TIMEOUT8_BCR			66
+#define GCC_PCNOC_BUS_TIMEOUT9_BCR			67
+#define GCC_TCSR_BCR					68
+#define GCC_QDSS_BCR					69
+#define GCC_MPM_BCR					70
+#define GCC_SPDM_BCR					71
+
+#endif
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/qcom,gcc-ipq806x.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/qcom,gcc-ipq806x.h
new file mode 100644
index 0000000000000000000000000000000000000000..dc4254b8cbbc2075bf1bb2debadd4587d3721b1f
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/qcom,gcc-ipq806x.h
@@ -0,0 +1,295 @@
+/*
+ * Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_CLK_GCC_IPQ806X_H
+#define _DT_BINDINGS_CLK_GCC_IPQ806X_H
+
+#define AFAB_CLK_SRC				0
+#define QDSS_STM_CLK				1
+#define SCSS_A_CLK				2
+#define SCSS_H_CLK				3
+#define AFAB_CORE_CLK				4
+#define SCSS_XO_SRC_CLK				5
+#define AFAB_EBI1_CH0_A_CLK			6
+#define AFAB_EBI1_CH1_A_CLK			7
+#define AFAB_AXI_S0_FCLK			8
+#define AFAB_AXI_S1_FCLK			9
+#define AFAB_AXI_S2_FCLK			10
+#define AFAB_AXI_S3_FCLK			11
+#define AFAB_AXI_S4_FCLK			12
+#define SFAB_CORE_CLK				13
+#define SFAB_AXI_S0_FCLK			14
+#define SFAB_AXI_S1_FCLK			15
+#define SFAB_AXI_S2_FCLK			16
+#define SFAB_AXI_S3_FCLK			17
+#define SFAB_AXI_S4_FCLK			18
+#define SFAB_AXI_S5_FCLK			19
+#define SFAB_AHB_S0_FCLK			20
+#define SFAB_AHB_S1_FCLK			21
+#define SFAB_AHB_S2_FCLK			22
+#define SFAB_AHB_S3_FCLK			23
+#define SFAB_AHB_S4_FCLK			24
+#define SFAB_AHB_S5_FCLK			25
+#define SFAB_AHB_S6_FCLK			26
+#define SFAB_AHB_S7_FCLK			27
+#define QDSS_AT_CLK_SRC				28
+#define QDSS_AT_CLK				29
+#define QDSS_TRACECLKIN_CLK_SRC			30
+#define QDSS_TRACECLKIN_CLK			31
+#define QDSS_TSCTR_CLK_SRC			32
+#define QDSS_TSCTR_CLK				33
+#define SFAB_ADM0_M0_A_CLK			34
+#define SFAB_ADM0_M1_A_CLK			35
+#define SFAB_ADM0_M2_H_CLK			36
+#define ADM0_CLK				37
+#define ADM0_PBUS_CLK				38
+#define IMEM0_A_CLK				39
+#define QDSS_H_CLK				40
+#define PCIE_A_CLK				41
+#define PCIE_AUX_CLK				42
+#define PCIE_H_CLK				43
+#define PCIE_PHY_CLK				44
+#define SFAB_CLK_SRC				45
+#define SFAB_LPASS_Q6_A_CLK			46
+#define SFAB_AFAB_M_A_CLK			47
+#define AFAB_SFAB_M0_A_CLK			48
+#define AFAB_SFAB_M1_A_CLK			49
+#define SFAB_SATA_S_H_CLK			50
+#define DFAB_CLK_SRC				51
+#define DFAB_CLK				52
+#define SFAB_DFAB_M_A_CLK			53
+#define DFAB_SFAB_M_A_CLK			54
+#define DFAB_SWAY0_H_CLK			55
+#define DFAB_SWAY1_H_CLK			56
+#define DFAB_ARB0_H_CLK				57
+#define DFAB_ARB1_H_CLK				58
+#define PPSS_H_CLK				59
+#define PPSS_PROC_CLK				60
+#define PPSS_TIMER0_CLK				61
+#define PPSS_TIMER1_CLK				62
+#define PMEM_A_CLK				63
+#define DMA_BAM_H_CLK				64
+#define SIC_H_CLK				65
+#define SPS_TIC_H_CLK				66
+#define CFPB_2X_CLK_SRC				67
+#define CFPB_CLK				68
+#define CFPB0_H_CLK				69
+#define CFPB1_H_CLK				70
+#define CFPB2_H_CLK				71
+#define SFAB_CFPB_M_H_CLK			72
+#define CFPB_MASTER_H_CLK			73
+#define SFAB_CFPB_S_H_CLK			74
+#define CFPB_SPLITTER_H_CLK			75
+#define TSIF_H_CLK				76
+#define TSIF_INACTIVITY_TIMERS_CLK		77
+#define TSIF_REF_SRC				78
+#define TSIF_REF_CLK				79
+#define CE1_H_CLK				80
+#define CE1_CORE_CLK				81
+#define CE1_SLEEP_CLK				82
+#define CE2_H_CLK				83
+#define CE2_CORE_CLK				84
+#define SFPB_H_CLK_SRC				85
+#define SFPB_H_CLK				86
+#define SFAB_SFPB_M_H_CLK			87
+#define SFAB_SFPB_S_H_CLK			88
+#define RPM_PROC_CLK				89
+#define RPM_BUS_H_CLK				90
+#define RPM_SLEEP_CLK				91
+#define RPM_TIMER_CLK				92
+#define RPM_MSG_RAM_H_CLK			93
+#define PMIC_ARB0_H_CLK				94
+#define PMIC_ARB1_H_CLK				95
+#define PMIC_SSBI2_SRC				96
+#define PMIC_SSBI2_CLK				97
+#define SDC1_H_CLK				98
+#define SDC2_H_CLK				99
+#define SDC3_H_CLK				100
+#define SDC4_H_CLK				101
+#define SDC1_SRC				102
+#define SDC1_CLK				103
+#define SDC2_SRC				104
+#define SDC2_CLK				105
+#define SDC3_SRC				106
+#define SDC3_CLK				107
+#define SDC4_SRC				108
+#define SDC4_CLK				109
+#define USB_HS1_H_CLK				110
+#define USB_HS1_XCVR_SRC			111
+#define USB_HS1_XCVR_CLK			112
+#define USB_HSIC_H_CLK				113
+#define USB_HSIC_XCVR_SRC			114
+#define USB_HSIC_XCVR_CLK			115
+#define USB_HSIC_SYSTEM_CLK_SRC			116
+#define USB_HSIC_SYSTEM_CLK			117
+#define CFPB0_C0_H_CLK				118
+#define CFPB0_D0_H_CLK				119
+#define CFPB0_C1_H_CLK				120
+#define CFPB0_D1_H_CLK				121
+#define USB_FS1_H_CLK				122
+#define USB_FS1_XCVR_SRC			123
+#define USB_FS1_XCVR_CLK			124
+#define USB_FS1_SYSTEM_CLK			125
+#define GSBI_COMMON_SIM_SRC			126
+#define GSBI1_H_CLK				127
+#define GSBI2_H_CLK				128
+#define GSBI3_H_CLK				129
+#define GSBI4_H_CLK				130
+#define GSBI5_H_CLK				131
+#define GSBI6_H_CLK				132
+#define GSBI7_H_CLK				133
+#define GSBI1_QUP_SRC				134
+#define GSBI1_QUP_CLK				135
+#define GSBI2_QUP_SRC				136
+#define GSBI2_QUP_CLK				137
+#define GSBI3_QUP_SRC				138
+#define GSBI3_QUP_CLK				139
+#define GSBI4_QUP_SRC				140
+#define GSBI4_QUP_CLK				141
+#define GSBI5_QUP_SRC				142
+#define GSBI5_QUP_CLK				143
+#define GSBI6_QUP_SRC				144
+#define GSBI6_QUP_CLK				145
+#define GSBI7_QUP_SRC				146
+#define GSBI7_QUP_CLK				147
+#define GSBI1_UART_SRC				148
+#define GSBI1_UART_CLK				149
+#define GSBI2_UART_SRC				150
+#define GSBI2_UART_CLK				151
+#define GSBI3_UART_SRC				152
+#define GSBI3_UART_CLK				153
+#define GSBI4_UART_SRC				154
+#define GSBI4_UART_CLK				155
+#define GSBI5_UART_SRC				156
+#define GSBI5_UART_CLK				157
+#define GSBI6_UART_SRC				158
+#define GSBI6_UART_CLK				159
+#define GSBI7_UART_SRC				160
+#define GSBI7_UART_CLK				161
+#define GSBI1_SIM_CLK				162
+#define GSBI2_SIM_CLK				163
+#define GSBI3_SIM_CLK				164
+#define GSBI4_SIM_CLK				165
+#define GSBI5_SIM_CLK				166
+#define GSBI6_SIM_CLK				167
+#define GSBI7_SIM_CLK				168
+#define USB_HSIC_HSIC_CLK_SRC			169
+#define USB_HSIC_HSIC_CLK			170
+#define USB_HSIC_HSIO_CAL_CLK			171
+#define SPDM_CFG_H_CLK				172
+#define SPDM_MSTR_H_CLK				173
+#define SPDM_FF_CLK_SRC				174
+#define SPDM_FF_CLK				175
+#define SEC_CTRL_CLK				176
+#define SEC_CTRL_ACC_CLK_SRC			177
+#define SEC_CTRL_ACC_CLK			178
+#define TLMM_H_CLK				179
+#define TLMM_CLK				180
+#define SATA_H_CLK				181
+#define SATA_CLK_SRC				182
+#define SATA_RXOOB_CLK				183
+#define SATA_PMALIVE_CLK			184
+#define SATA_PHY_REF_CLK			185
+#define SATA_A_CLK				186
+#define SATA_PHY_CFG_CLK			187
+#define TSSC_CLK_SRC				188
+#define TSSC_CLK				189
+#define PDM_SRC					190
+#define PDM_CLK					191
+#define GP0_SRC					192
+#define GP0_CLK					193
+#define GP1_SRC					194
+#define GP1_CLK					195
+#define GP2_SRC					196
+#define GP2_CLK					197
+#define MPM_CLK					198
+#define EBI1_CLK_SRC				199
+#define EBI1_CH0_CLK				200
+#define EBI1_CH1_CLK				201
+#define EBI1_2X_CLK				202
+#define EBI1_CH0_DQ_CLK				203
+#define EBI1_CH1_DQ_CLK				204
+#define EBI1_CH0_CA_CLK				205
+#define EBI1_CH1_CA_CLK				206
+#define EBI1_XO_CLK				207
+#define SFAB_SMPSS_S_H_CLK			208
+#define PRNG_SRC				209
+#define PRNG_CLK				210
+#define PXO_SRC					211
+#define SPDM_CY_PORT0_CLK			212
+#define SPDM_CY_PORT1_CLK			213
+#define SPDM_CY_PORT2_CLK			214
+#define SPDM_CY_PORT3_CLK			215
+#define SPDM_CY_PORT4_CLK			216
+#define SPDM_CY_PORT5_CLK			217
+#define SPDM_CY_PORT6_CLK			218
+#define SPDM_CY_PORT7_CLK			219
+#define PLL0					220
+#define PLL0_VOTE				221
+#define PLL3					222
+#define PLL3_VOTE				223
+#define PLL4_VOTE				225
+#define PLL8					226
+#define PLL8_VOTE				227
+#define PLL9					228
+#define PLL10					229
+#define PLL11					230
+#define PLL12					231
+#define PLL14					232
+#define PLL14_VOTE				233
+#define PLL18					234
+#define CE5_SRC					235
+#define CE5_H_CLK				236
+#define CE5_CORE_CLK				237
+#define CE3_SLEEP_CLK				238
+#define SFAB_AHB_S8_FCLK			239
+#define SPDM_CY_PORT8_CLK			246
+#define PCIE_ALT_REF_SRC			247
+#define PCIE_ALT_REF_CLK			248
+#define PCIE_1_A_CLK				249
+#define PCIE_1_AUX_CLK				250
+#define PCIE_1_H_CLK				251
+#define PCIE_1_PHY_CLK				252
+#define PCIE_1_ALT_REF_SRC			253
+#define PCIE_1_ALT_REF_CLK			254
+#define PCIE_2_A_CLK				255
+#define PCIE_2_AUX_CLK				256
+#define PCIE_2_H_CLK				257
+#define PCIE_2_PHY_CLK				258
+#define PCIE_2_ALT_REF_SRC			259
+#define PCIE_2_ALT_REF_CLK			260
+#define EBI2_CLK				261
+#define USB30_SLEEP_CLK				262
+#define USB30_UTMI_SRC				263
+#define USB30_0_UTMI_CLK			264
+#define USB30_1_UTMI_CLK			265
+#define USB30_MASTER_SRC			266
+#define USB30_0_MASTER_CLK			267
+#define USB30_1_MASTER_CLK			268
+#define GMAC_CORE1_CLK_SRC			269
+#define GMAC_CORE2_CLK_SRC			270
+#define GMAC_CORE3_CLK_SRC			271
+#define GMAC_CORE4_CLK_SRC			272
+#define GMAC_CORE1_CLK				273
+#define GMAC_CORE2_CLK				274
+#define GMAC_CORE3_CLK				275
+#define GMAC_CORE4_CLK				276
+#define UBI32_CORE1_CLK_SRC			277
+#define UBI32_CORE2_CLK_SRC			278
+#define UBI32_CORE1_CLK				279
+#define UBI32_CORE2_CLK				280
+#define EBI2_AON_CLK				281
+#define NSSTCM_CLK_SRC				282
+#define NSSTCM_CLK				283
+
+#endif
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/qcom,gcc-ipq8074.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/qcom,gcc-ipq8074.h
new file mode 100644
index 0000000000000000000000000000000000000000..238f872e52f4ba7eca36d7b582e924a4fc1991ea
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/qcom,gcc-ipq8074.h
@@ -0,0 +1,374 @@
+/*
+ * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_IPQ_GCC_8074_H
+#define _DT_BINDINGS_CLOCK_IPQ_GCC_8074_H
+
+#define GPLL0					0
+#define GPLL0_MAIN				1
+#define GCC_SLEEP_CLK_SRC			2
+#define BLSP1_QUP1_I2C_APPS_CLK_SRC		3
+#define BLSP1_QUP1_SPI_APPS_CLK_SRC		4
+#define BLSP1_QUP2_I2C_APPS_CLK_SRC		5
+#define BLSP1_QUP2_SPI_APPS_CLK_SRC		6
+#define BLSP1_QUP3_I2C_APPS_CLK_SRC		7
+#define BLSP1_QUP3_SPI_APPS_CLK_SRC		8
+#define BLSP1_QUP4_I2C_APPS_CLK_SRC		9
+#define BLSP1_QUP4_SPI_APPS_CLK_SRC		10
+#define BLSP1_QUP5_I2C_APPS_CLK_SRC		11
+#define BLSP1_QUP5_SPI_APPS_CLK_SRC		12
+#define BLSP1_QUP6_I2C_APPS_CLK_SRC		13
+#define BLSP1_QUP6_SPI_APPS_CLK_SRC		14
+#define BLSP1_UART1_APPS_CLK_SRC		15
+#define BLSP1_UART2_APPS_CLK_SRC		16
+#define BLSP1_UART3_APPS_CLK_SRC		17
+#define BLSP1_UART4_APPS_CLK_SRC		18
+#define BLSP1_UART5_APPS_CLK_SRC		19
+#define BLSP1_UART6_APPS_CLK_SRC		20
+#define GCC_BLSP1_AHB_CLK			21
+#define GCC_BLSP1_QUP1_I2C_APPS_CLK		22
+#define GCC_BLSP1_QUP1_SPI_APPS_CLK		23
+#define GCC_BLSP1_QUP2_I2C_APPS_CLK		24
+#define GCC_BLSP1_QUP2_SPI_APPS_CLK		25
+#define GCC_BLSP1_QUP3_I2C_APPS_CLK		26
+#define GCC_BLSP1_QUP3_SPI_APPS_CLK		27
+#define GCC_BLSP1_QUP4_I2C_APPS_CLK		28
+#define GCC_BLSP1_QUP4_SPI_APPS_CLK		29
+#define GCC_BLSP1_QUP5_I2C_APPS_CLK		30
+#define GCC_BLSP1_QUP5_SPI_APPS_CLK		31
+#define GCC_BLSP1_QUP6_I2C_APPS_CLK		32
+#define GCC_BLSP1_QUP6_SPI_APPS_CLK		33
+#define GCC_BLSP1_UART1_APPS_CLK		34
+#define GCC_BLSP1_UART2_APPS_CLK		35
+#define GCC_BLSP1_UART3_APPS_CLK		36
+#define GCC_BLSP1_UART4_APPS_CLK		37
+#define GCC_BLSP1_UART5_APPS_CLK		38
+#define GCC_BLSP1_UART6_APPS_CLK		39
+#define GCC_PRNG_AHB_CLK			40
+#define GCC_QPIC_AHB_CLK			41
+#define GCC_QPIC_CLK				42
+#define PCNOC_BFDCD_CLK_SRC			43
+#define GPLL2_MAIN				44
+#define GPLL2					45
+#define GPLL4_MAIN				46
+#define GPLL4					47
+#define GPLL6_MAIN				48
+#define GPLL6					49
+#define UBI32_PLL_MAIN				50
+#define UBI32_PLL				51
+#define NSS_CRYPTO_PLL_MAIN			52
+#define NSS_CRYPTO_PLL				53
+#define PCIE0_AXI_CLK_SRC			54
+#define PCIE0_AUX_CLK_SRC			55
+#define PCIE0_PIPE_CLK_SRC			56
+#define PCIE1_AXI_CLK_SRC			57
+#define PCIE1_AUX_CLK_SRC			58
+#define PCIE1_PIPE_CLK_SRC			59
+#define SDCC1_APPS_CLK_SRC			60
+#define SDCC1_ICE_CORE_CLK_SRC			61
+#define SDCC2_APPS_CLK_SRC			62
+#define USB0_MASTER_CLK_SRC			63
+#define USB0_AUX_CLK_SRC			64
+#define USB0_MOCK_UTMI_CLK_SRC			65
+#define USB0_PIPE_CLK_SRC			66
+#define USB1_MASTER_CLK_SRC			67
+#define USB1_AUX_CLK_SRC			68
+#define USB1_MOCK_UTMI_CLK_SRC			69
+#define USB1_PIPE_CLK_SRC			70
+#define GCC_XO_CLK_SRC				71
+#define SYSTEM_NOC_BFDCD_CLK_SRC		72
+#define NSS_CE_CLK_SRC				73
+#define NSS_NOC_BFDCD_CLK_SRC			74
+#define NSS_CRYPTO_CLK_SRC			75
+#define NSS_UBI0_CLK_SRC			76
+#define NSS_UBI0_DIV_CLK_SRC			77
+#define NSS_UBI1_CLK_SRC			78
+#define NSS_UBI1_DIV_CLK_SRC			79
+#define UBI_MPT_CLK_SRC				80
+#define NSS_IMEM_CLK_SRC			81
+#define NSS_PPE_CLK_SRC				82
+#define NSS_PORT1_RX_CLK_SRC			83
+#define NSS_PORT1_RX_DIV_CLK_SRC		84
+#define NSS_PORT1_TX_CLK_SRC			85
+#define NSS_PORT1_TX_DIV_CLK_SRC		86
+#define NSS_PORT2_RX_CLK_SRC			87
+#define NSS_PORT2_RX_DIV_CLK_SRC		88
+#define NSS_PORT2_TX_CLK_SRC			89
+#define NSS_PORT2_TX_DIV_CLK_SRC		90
+#define NSS_PORT3_RX_CLK_SRC			91
+#define NSS_PORT3_RX_DIV_CLK_SRC		92
+#define NSS_PORT3_TX_CLK_SRC			93
+#define NSS_PORT3_TX_DIV_CLK_SRC		94
+#define NSS_PORT4_RX_CLK_SRC			95
+#define NSS_PORT4_RX_DIV_CLK_SRC		96
+#define NSS_PORT4_TX_CLK_SRC			97
+#define NSS_PORT4_TX_DIV_CLK_SRC		98
+#define NSS_PORT5_RX_CLK_SRC			99
+#define NSS_PORT5_RX_DIV_CLK_SRC		100
+#define NSS_PORT5_TX_CLK_SRC			101
+#define NSS_PORT5_TX_DIV_CLK_SRC		102
+#define NSS_PORT6_RX_CLK_SRC			103
+#define NSS_PORT6_RX_DIV_CLK_SRC		104
+#define NSS_PORT6_TX_CLK_SRC			105
+#define NSS_PORT6_TX_DIV_CLK_SRC		106
+#define CRYPTO_CLK_SRC				107
+#define GP1_CLK_SRC				108
+#define GP2_CLK_SRC				109
+#define GP3_CLK_SRC				110
+#define GCC_PCIE0_AHB_CLK			111
+#define GCC_PCIE0_AUX_CLK			112
+#define GCC_PCIE0_AXI_M_CLK			113
+#define GCC_PCIE0_AXI_S_CLK			114
+#define GCC_PCIE0_PIPE_CLK			115
+#define GCC_SYS_NOC_PCIE0_AXI_CLK		116
+#define GCC_PCIE1_AHB_CLK			117
+#define GCC_PCIE1_AUX_CLK			118
+#define GCC_PCIE1_AXI_M_CLK			119
+#define GCC_PCIE1_AXI_S_CLK			120
+#define GCC_PCIE1_PIPE_CLK			121
+#define GCC_SYS_NOC_PCIE1_AXI_CLK		122
+#define GCC_USB0_AUX_CLK			123
+#define GCC_SYS_NOC_USB0_AXI_CLK		124
+#define GCC_USB0_MASTER_CLK			125
+#define GCC_USB0_MOCK_UTMI_CLK			126
+#define GCC_USB0_PHY_CFG_AHB_CLK		127
+#define GCC_USB0_PIPE_CLK			128
+#define GCC_USB0_SLEEP_CLK			129
+#define GCC_USB1_AUX_CLK			130
+#define GCC_SYS_NOC_USB1_AXI_CLK		131
+#define GCC_USB1_MASTER_CLK			132
+#define GCC_USB1_MOCK_UTMI_CLK			133
+#define GCC_USB1_PHY_CFG_AHB_CLK		134
+#define GCC_USB1_PIPE_CLK			135
+#define GCC_USB1_SLEEP_CLK			136
+#define GCC_SDCC1_AHB_CLK			137
+#define GCC_SDCC1_APPS_CLK			138
+#define GCC_SDCC1_ICE_CORE_CLK			139
+#define GCC_SDCC2_AHB_CLK			140
+#define GCC_SDCC2_APPS_CLK			141
+#define GCC_MEM_NOC_NSS_AXI_CLK			142
+#define GCC_NSS_CE_APB_CLK			143
+#define GCC_NSS_CE_AXI_CLK			144
+#define GCC_NSS_CFG_CLK				145
+#define GCC_NSS_CRYPTO_CLK			146
+#define GCC_NSS_CSR_CLK				147
+#define GCC_NSS_EDMA_CFG_CLK			148
+#define GCC_NSS_EDMA_CLK			149
+#define GCC_NSS_IMEM_CLK			150
+#define GCC_NSS_NOC_CLK				151
+#define GCC_NSS_PPE_BTQ_CLK			152
+#define GCC_NSS_PPE_CFG_CLK			153
+#define GCC_NSS_PPE_CLK				154
+#define GCC_NSS_PPE_IPE_CLK			155
+#define GCC_NSS_PTP_REF_CLK			156
+#define GCC_NSSNOC_CE_APB_CLK			157
+#define GCC_NSSNOC_CE_AXI_CLK			158
+#define GCC_NSSNOC_CRYPTO_CLK			159
+#define GCC_NSSNOC_PPE_CFG_CLK			160
+#define GCC_NSSNOC_PPE_CLK			161
+#define GCC_NSSNOC_QOSGEN_REF_CLK		162
+#define GCC_NSSNOC_SNOC_CLK			163
+#define GCC_NSSNOC_TIMEOUT_REF_CLK		164
+#define GCC_NSSNOC_UBI0_AHB_CLK			165
+#define GCC_NSSNOC_UBI1_AHB_CLK			166
+#define GCC_UBI0_AHB_CLK			167
+#define GCC_UBI0_AXI_CLK			168
+#define GCC_UBI0_NC_AXI_CLK			169
+#define GCC_UBI0_CORE_CLK			170
+#define GCC_UBI0_MPT_CLK			171
+#define GCC_UBI1_AHB_CLK			172
+#define GCC_UBI1_AXI_CLK			173
+#define GCC_UBI1_NC_AXI_CLK			174
+#define GCC_UBI1_CORE_CLK			175
+#define GCC_UBI1_MPT_CLK			176
+#define GCC_CMN_12GPLL_AHB_CLK			177
+#define GCC_CMN_12GPLL_SYS_CLK			178
+#define GCC_MDIO_AHB_CLK			179
+#define GCC_UNIPHY0_AHB_CLK			180
+#define GCC_UNIPHY0_SYS_CLK			181
+#define GCC_UNIPHY1_AHB_CLK			182
+#define GCC_UNIPHY1_SYS_CLK			183
+#define GCC_UNIPHY2_AHB_CLK			184
+#define GCC_UNIPHY2_SYS_CLK			185
+#define GCC_NSS_PORT1_RX_CLK			186
+#define GCC_NSS_PORT1_TX_CLK			187
+#define GCC_NSS_PORT2_RX_CLK			188
+#define GCC_NSS_PORT2_TX_CLK			189
+#define GCC_NSS_PORT3_RX_CLK			190
+#define GCC_NSS_PORT3_TX_CLK			191
+#define GCC_NSS_PORT4_RX_CLK			192
+#define GCC_NSS_PORT4_TX_CLK			193
+#define GCC_NSS_PORT5_RX_CLK			194
+#define GCC_NSS_PORT5_TX_CLK			195
+#define GCC_NSS_PORT6_RX_CLK			196
+#define GCC_NSS_PORT6_TX_CLK			197
+#define GCC_PORT1_MAC_CLK			198
+#define GCC_PORT2_MAC_CLK			199
+#define GCC_PORT3_MAC_CLK			200
+#define GCC_PORT4_MAC_CLK			201
+#define GCC_PORT5_MAC_CLK			202
+#define GCC_PORT6_MAC_CLK			203
+#define GCC_UNIPHY0_PORT1_RX_CLK		204
+#define GCC_UNIPHY0_PORT1_TX_CLK		205
+#define GCC_UNIPHY0_PORT2_RX_CLK		206
+#define GCC_UNIPHY0_PORT2_TX_CLK		207
+#define GCC_UNIPHY0_PORT3_RX_CLK		208
+#define GCC_UNIPHY0_PORT3_TX_CLK		209
+#define GCC_UNIPHY0_PORT4_RX_CLK		210
+#define GCC_UNIPHY0_PORT4_TX_CLK		211
+#define GCC_UNIPHY0_PORT5_RX_CLK		212
+#define GCC_UNIPHY0_PORT5_TX_CLK		213
+#define GCC_UNIPHY1_PORT5_RX_CLK		214
+#define GCC_UNIPHY1_PORT5_TX_CLK		215
+#define GCC_UNIPHY2_PORT6_RX_CLK		216
+#define GCC_UNIPHY2_PORT6_TX_CLK		217
+#define GCC_CRYPTO_AHB_CLK			218
+#define GCC_CRYPTO_AXI_CLK			219
+#define GCC_CRYPTO_CLK				220
+#define GCC_GP1_CLK				221
+#define GCC_GP2_CLK				222
+#define GCC_GP3_CLK				223
+
+#define GCC_BLSP1_BCR				0
+#define GCC_BLSP1_QUP1_BCR			1
+#define GCC_BLSP1_UART1_BCR			2
+#define GCC_BLSP1_QUP2_BCR			3
+#define GCC_BLSP1_UART2_BCR			4
+#define GCC_BLSP1_QUP3_BCR			5
+#define GCC_BLSP1_UART3_BCR			6
+#define GCC_BLSP1_QUP4_BCR			7
+#define GCC_BLSP1_UART4_BCR			8
+#define GCC_BLSP1_QUP5_BCR			9
+#define GCC_BLSP1_UART5_BCR			10
+#define GCC_BLSP1_QUP6_BCR			11
+#define GCC_BLSP1_UART6_BCR			12
+#define GCC_IMEM_BCR				13
+#define GCC_SMMU_BCR				14
+#define GCC_APSS_TCU_BCR			15
+#define GCC_SMMU_XPU_BCR			16
+#define GCC_PCNOC_TBU_BCR			17
+#define GCC_SMMU_CFG_BCR			18
+#define GCC_PRNG_BCR				19
+#define GCC_BOOT_ROM_BCR			20
+#define GCC_CRYPTO_BCR				21
+#define GCC_WCSS_BCR				22
+#define GCC_WCSS_Q6_BCR				23
+#define GCC_NSS_BCR				24
+#define GCC_SEC_CTRL_BCR			25
+#define GCC_ADSS_BCR				26
+#define GCC_DDRSS_BCR				27
+#define GCC_SYSTEM_NOC_BCR			28
+#define GCC_PCNOC_BCR				29
+#define GCC_TCSR_BCR				30
+#define GCC_QDSS_BCR				31
+#define GCC_DCD_BCR				32
+#define GCC_MSG_RAM_BCR				33
+#define GCC_MPM_BCR				34
+#define GCC_SPMI_BCR				35
+#define GCC_SPDM_BCR				36
+#define GCC_RBCPR_BCR				37
+#define GCC_RBCPR_MX_BCR			38
+#define GCC_TLMM_BCR				39
+#define GCC_RBCPR_WCSS_BCR			40
+#define GCC_USB0_PHY_BCR			41
+#define GCC_USB3PHY_0_PHY_BCR			42
+#define GCC_USB0_BCR				43
+#define GCC_USB1_PHY_BCR			44
+#define GCC_USB3PHY_1_PHY_BCR			45
+#define GCC_USB1_BCR				46
+#define GCC_QUSB2_0_PHY_BCR			47
+#define GCC_QUSB2_1_PHY_BCR			48
+#define GCC_SDCC1_BCR				49
+#define GCC_SDCC2_BCR				50
+#define GCC_SNOC_BUS_TIMEOUT0_BCR		51
+#define GCC_SNOC_BUS_TIMEOUT2_BCR		52
+#define GCC_SNOC_BUS_TIMEOUT3_BCR		53
+#define GCC_PCNOC_BUS_TIMEOUT0_BCR		54
+#define GCC_PCNOC_BUS_TIMEOUT1_BCR		55
+#define GCC_PCNOC_BUS_TIMEOUT2_BCR		56
+#define GCC_PCNOC_BUS_TIMEOUT3_BCR		57
+#define GCC_PCNOC_BUS_TIMEOUT4_BCR		58
+#define GCC_PCNOC_BUS_TIMEOUT5_BCR		59
+#define GCC_PCNOC_BUS_TIMEOUT6_BCR		60
+#define GCC_PCNOC_BUS_TIMEOUT7_BCR		61
+#define GCC_PCNOC_BUS_TIMEOUT8_BCR		62
+#define GCC_PCNOC_BUS_TIMEOUT9_BCR		63
+#define GCC_UNIPHY0_BCR				64
+#define GCC_UNIPHY1_BCR				65
+#define GCC_UNIPHY2_BCR				66
+#define GCC_CMN_12GPLL_BCR			67
+#define GCC_QPIC_BCR				68
+#define GCC_MDIO_BCR				69
+#define GCC_PCIE1_TBU_BCR			70
+#define GCC_WCSS_CORE_TBU_BCR			71
+#define GCC_WCSS_Q6_TBU_BCR			72
+#define GCC_USB0_TBU_BCR			73
+#define GCC_USB1_TBU_BCR			74
+#define GCC_PCIE0_TBU_BCR			75
+#define GCC_NSS_NOC_TBU_BCR			76
+#define GCC_PCIE0_BCR				77
+#define GCC_PCIE0_PHY_BCR			78
+#define GCC_PCIE0PHY_PHY_BCR			79
+#define GCC_PCIE0_LINK_DOWN_BCR			80
+#define GCC_PCIE1_BCR				81
+#define GCC_PCIE1_PHY_BCR			82
+#define GCC_PCIE1PHY_PHY_BCR			83
+#define GCC_PCIE1_LINK_DOWN_BCR			84
+#define GCC_DCC_BCR				85
+#define GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR	86
+#define GCC_APC1_VOLTAGE_DROOP_DETECTOR_BCR	87
+#define GCC_SMMU_CATS_BCR			88
+#define GCC_UBI0_AXI_ARES			89
+#define GCC_UBI0_AHB_ARES			90
+#define GCC_UBI0_NC_AXI_ARES			91
+#define GCC_UBI0_DBG_ARES			92
+#define GCC_UBI0_CORE_CLAMP_ENABLE		93
+#define GCC_UBI0_CLKRST_CLAMP_ENABLE		94
+#define GCC_UBI1_AXI_ARES			95
+#define GCC_UBI1_AHB_ARES			96
+#define GCC_UBI1_NC_AXI_ARES			97
+#define GCC_UBI1_DBG_ARES			98
+#define GCC_UBI1_CORE_CLAMP_ENABLE		99
+#define GCC_UBI1_CLKRST_CLAMP_ENABLE		100
+#define GCC_NSS_CFG_ARES			101
+#define GCC_NSS_IMEM_ARES			102
+#define GCC_NSS_NOC_ARES			103
+#define GCC_NSS_CRYPTO_ARES			104
+#define GCC_NSS_CSR_ARES			105
+#define GCC_NSS_CE_APB_ARES			106
+#define GCC_NSS_CE_AXI_ARES			107
+#define GCC_NSSNOC_CE_APB_ARES			108
+#define GCC_NSSNOC_CE_AXI_ARES			109
+#define GCC_NSSNOC_UBI0_AHB_ARES		110
+#define GCC_NSSNOC_UBI1_AHB_ARES		111
+#define GCC_NSSNOC_SNOC_ARES			112
+#define GCC_NSSNOC_CRYPTO_ARES			113
+#define GCC_NSSNOC_ATB_ARES			114
+#define GCC_NSSNOC_QOSGEN_REF_ARES		115
+#define GCC_NSSNOC_TIMEOUT_REF_ARES		116
+#define GCC_PCIE0_PIPE_ARES			117
+#define GCC_PCIE0_SLEEP_ARES			118
+#define GCC_PCIE0_CORE_STICKY_ARES		119
+#define GCC_PCIE0_AXI_MASTER_ARES		120
+#define GCC_PCIE0_AXI_SLAVE_ARES		121
+#define GCC_PCIE0_AHB_ARES			122
+#define GCC_PCIE0_AXI_MASTER_STICKY_ARES	123
+#define GCC_PCIE1_PIPE_ARES			124
+#define GCC_PCIE1_SLEEP_ARES			125
+#define GCC_PCIE1_CORE_STICKY_ARES		126
+#define GCC_PCIE1_AXI_MASTER_ARES		127
+#define GCC_PCIE1_AXI_SLAVE_ARES		128
+#define GCC_PCIE1_AHB_ARES			129
+#define GCC_PCIE1_AXI_MASTER_STICKY_ARES	130
+
+#endif
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/qcom,gcc-mdm9615.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/qcom,gcc-mdm9615.h
new file mode 100644
index 0000000000000000000000000000000000000000..787e448958bd492b811871931df38e08b8bf8c2c
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/qcom,gcc-mdm9615.h
@@ -0,0 +1,329 @@
+/*
+ * Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ * Copyright (c) BayLibre, SAS.
+ * Author : Neil Armstrong <narmstrong@baylibre.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_CLK_MDM_GCC_9615_H
+#define _DT_BINDINGS_CLK_MDM_GCC_9615_H
+
+#define AFAB_CLK_SRC				0
+#define AFAB_CORE_CLK				1
+#define SFAB_MSS_Q6_SW_A_CLK			2
+#define SFAB_MSS_Q6_FW_A_CLK			3
+#define QDSS_STM_CLK				4
+#define SCSS_A_CLK				5
+#define SCSS_H_CLK				6
+#define SCSS_XO_SRC_CLK				7
+#define AFAB_EBI1_CH0_A_CLK			8
+#define AFAB_EBI1_CH1_A_CLK			9
+#define AFAB_AXI_S0_FCLK			10
+#define AFAB_AXI_S1_FCLK			11
+#define AFAB_AXI_S2_FCLK			12
+#define AFAB_AXI_S3_FCLK			13
+#define AFAB_AXI_S4_FCLK			14
+#define SFAB_CORE_CLK				15
+#define SFAB_AXI_S0_FCLK			16
+#define SFAB_AXI_S1_FCLK			17
+#define SFAB_AXI_S2_FCLK			18
+#define SFAB_AXI_S3_FCLK			19
+#define SFAB_AXI_S4_FCLK			20
+#define SFAB_AHB_S0_FCLK			21
+#define SFAB_AHB_S1_FCLK			22
+#define SFAB_AHB_S2_FCLK			23
+#define SFAB_AHB_S3_FCLK			24
+#define SFAB_AHB_S4_FCLK			25
+#define SFAB_AHB_S5_FCLK			26
+#define SFAB_AHB_S6_FCLK			27
+#define SFAB_AHB_S7_FCLK			28
+#define QDSS_AT_CLK_SRC				29
+#define QDSS_AT_CLK				30
+#define QDSS_TRACECLKIN_CLK_SRC			31
+#define QDSS_TRACECLKIN_CLK			32
+#define QDSS_TSCTR_CLK_SRC			33
+#define QDSS_TSCTR_CLK				34
+#define SFAB_ADM0_M0_A_CLK			35
+#define SFAB_ADM0_M1_A_CLK			36
+#define SFAB_ADM0_M2_H_CLK			37
+#define ADM0_CLK				38
+#define ADM0_PBUS_CLK				39
+#define MSS_XPU_CLK				40
+#define IMEM0_A_CLK				41
+#define QDSS_H_CLK				42
+#define PCIE_A_CLK				43
+#define PCIE_AUX_CLK				44
+#define PCIE_PHY_REF_CLK			45
+#define PCIE_H_CLK				46
+#define SFAB_CLK_SRC				47
+#define MAHB0_CLK				48
+#define Q6SW_CLK_SRC				49
+#define Q6SW_CLK				50
+#define Q6FW_CLK_SRC				51
+#define Q6FW_CLK				52
+#define SFAB_MSS_M_A_CLK			53
+#define SFAB_USB3_M_A_CLK			54
+#define SFAB_LPASS_Q6_A_CLK			55
+#define SFAB_AFAB_M_A_CLK			56
+#define AFAB_SFAB_M0_A_CLK			57
+#define AFAB_SFAB_M1_A_CLK			58
+#define SFAB_SATA_S_H_CLK			59
+#define DFAB_CLK_SRC				60
+#define DFAB_CLK				61
+#define SFAB_DFAB_M_A_CLK			62
+#define DFAB_SFAB_M_A_CLK			63
+#define DFAB_SWAY0_H_CLK			64
+#define DFAB_SWAY1_H_CLK			65
+#define DFAB_ARB0_H_CLK				66
+#define DFAB_ARB1_H_CLK				67
+#define PPSS_H_CLK				68
+#define PPSS_PROC_CLK				69
+#define PPSS_TIMER0_CLK				70
+#define PPSS_TIMER1_CLK				71
+#define PMEM_A_CLK				72
+#define DMA_BAM_H_CLK				73
+#define SIC_H_CLK				74
+#define SPS_TIC_H_CLK				75
+#define SLIMBUS_H_CLK				76
+#define SLIMBUS_XO_SRC_CLK			77
+#define CFPB_2X_CLK_SRC				78
+#define CFPB_CLK				79
+#define CFPB0_H_CLK				80
+#define CFPB1_H_CLK				81
+#define CFPB2_H_CLK				82
+#define SFAB_CFPB_M_H_CLK			83
+#define CFPB_MASTER_H_CLK			84
+#define SFAB_CFPB_S_H_CLK			85
+#define CFPB_SPLITTER_H_CLK			86
+#define TSIF_H_CLK				87
+#define TSIF_INACTIVITY_TIMERS_CLK		88
+#define TSIF_REF_SRC				89
+#define TSIF_REF_CLK				90
+#define CE1_H_CLK				91
+#define CE1_CORE_CLK				92
+#define CE1_SLEEP_CLK				93
+#define CE2_H_CLK				94
+#define CE2_CORE_CLK				95
+#define SFPB_H_CLK_SRC				97
+#define SFPB_H_CLK				98
+#define SFAB_SFPB_M_H_CLK			99
+#define SFAB_SFPB_S_H_CLK			100
+#define RPM_PROC_CLK				101
+#define RPM_BUS_H_CLK				102
+#define RPM_SLEEP_CLK				103
+#define RPM_TIMER_CLK				104
+#define RPM_MSG_RAM_H_CLK			105
+#define PMIC_ARB0_H_CLK				106
+#define PMIC_ARB1_H_CLK				107
+#define PMIC_SSBI2_SRC				108
+#define PMIC_SSBI2_CLK				109
+#define SDC1_H_CLK				110
+#define SDC2_H_CLK				111
+#define SDC3_H_CLK				112
+#define SDC4_H_CLK				113
+#define SDC5_H_CLK				114
+#define SDC1_SRC				115
+#define SDC2_SRC				116
+#define SDC3_SRC				117
+#define SDC4_SRC				118
+#define SDC5_SRC				119
+#define SDC1_CLK				120
+#define SDC2_CLK				121
+#define SDC3_CLK				122
+#define SDC4_CLK				123
+#define SDC5_CLK				124
+#define DFAB_A2_H_CLK				125
+#define USB_HS1_H_CLK				126
+#define USB_HS1_XCVR_SRC			127
+#define USB_HS1_XCVR_CLK			128
+#define USB_HSIC_H_CLK				129
+#define USB_HSIC_XCVR_FS_SRC			130
+#define USB_HSIC_XCVR_FS_CLK			131
+#define USB_HSIC_SYSTEM_CLK_SRC			132
+#define USB_HSIC_SYSTEM_CLK			133
+#define CFPB0_C0_H_CLK				134
+#define CFPB0_C1_H_CLK				135
+#define CFPB0_D0_H_CLK				136
+#define CFPB0_D1_H_CLK				137
+#define USB_FS1_H_CLK				138
+#define USB_FS1_XCVR_FS_SRC			139
+#define USB_FS1_XCVR_FS_CLK			140
+#define USB_FS1_SYSTEM_CLK			141
+#define USB_FS2_H_CLK				142
+#define USB_FS2_XCVR_FS_SRC			143
+#define USB_FS2_XCVR_FS_CLK			144
+#define USB_FS2_SYSTEM_CLK			145
+#define GSBI_COMMON_SIM_SRC			146
+#define GSBI1_H_CLK				147
+#define GSBI2_H_CLK				148
+#define GSBI3_H_CLK				149
+#define GSBI4_H_CLK				150
+#define GSBI5_H_CLK				151
+#define GSBI6_H_CLK				152
+#define GSBI7_H_CLK				153
+#define GSBI8_H_CLK				154
+#define GSBI9_H_CLK				155
+#define GSBI10_H_CLK				156
+#define GSBI11_H_CLK				157
+#define GSBI12_H_CLK				158
+#define GSBI1_UART_SRC				159
+#define GSBI1_UART_CLK				160
+#define GSBI2_UART_SRC				161
+#define GSBI2_UART_CLK				162
+#define GSBI3_UART_SRC				163
+#define GSBI3_UART_CLK				164
+#define GSBI4_UART_SRC				165
+#define GSBI4_UART_CLK				166
+#define GSBI5_UART_SRC				167
+#define GSBI5_UART_CLK				168
+#define GSBI6_UART_SRC				169
+#define GSBI6_UART_CLK				170
+#define GSBI7_UART_SRC				171
+#define GSBI7_UART_CLK				172
+#define GSBI8_UART_SRC				173
+#define GSBI8_UART_CLK				174
+#define GSBI9_UART_SRC				175
+#define GSBI9_UART_CLK				176
+#define GSBI10_UART_SRC				177
+#define GSBI10_UART_CLK				178
+#define GSBI11_UART_SRC				179
+#define GSBI11_UART_CLK				180
+#define GSBI12_UART_SRC				181
+#define GSBI12_UART_CLK				182
+#define GSBI1_QUP_SRC				183
+#define GSBI1_QUP_CLK				184
+#define GSBI2_QUP_SRC				185
+#define GSBI2_QUP_CLK				186
+#define GSBI3_QUP_SRC				187
+#define GSBI3_QUP_CLK				188
+#define GSBI4_QUP_SRC				189
+#define GSBI4_QUP_CLK				190
+#define GSBI5_QUP_SRC				191
+#define GSBI5_QUP_CLK				192
+#define GSBI6_QUP_SRC				193
+#define GSBI6_QUP_CLK				194
+#define GSBI7_QUP_SRC				195
+#define GSBI7_QUP_CLK				196
+#define GSBI8_QUP_SRC				197
+#define GSBI8_QUP_CLK				198
+#define GSBI9_QUP_SRC				199
+#define GSBI9_QUP_CLK				200
+#define GSBI10_QUP_SRC				201
+#define GSBI10_QUP_CLK				202
+#define GSBI11_QUP_SRC				203
+#define GSBI11_QUP_CLK				204
+#define GSBI12_QUP_SRC				205
+#define GSBI12_QUP_CLK				206
+#define GSBI1_SIM_CLK				207
+#define GSBI2_SIM_CLK				208
+#define GSBI3_SIM_CLK				209
+#define GSBI4_SIM_CLK				210
+#define GSBI5_SIM_CLK				211
+#define GSBI6_SIM_CLK				212
+#define GSBI7_SIM_CLK				213
+#define GSBI8_SIM_CLK				214
+#define GSBI9_SIM_CLK				215
+#define GSBI10_SIM_CLK				216
+#define GSBI11_SIM_CLK				217
+#define GSBI12_SIM_CLK				218
+#define USB_HSIC_HSIC_CLK_SRC			219
+#define USB_HSIC_HSIC_CLK			220
+#define USB_HSIC_HSIO_CAL_CLK			221
+#define SPDM_CFG_H_CLK				222
+#define SPDM_MSTR_H_CLK				223
+#define SPDM_FF_CLK_SRC				224
+#define SPDM_FF_CLK				225
+#define SEC_CTRL_CLK				226
+#define SEC_CTRL_ACC_CLK_SRC			227
+#define SEC_CTRL_ACC_CLK			228
+#define TLMM_H_CLK				229
+#define TLMM_CLK				230
+#define SFAB_MSS_S_H_CLK			231
+#define MSS_SLP_CLK				232
+#define MSS_Q6SW_JTAG_CLK			233
+#define MSS_Q6FW_JTAG_CLK			234
+#define MSS_S_H_CLK				235
+#define MSS_CXO_SRC_CLK				236
+#define SATA_H_CLK				237
+#define SATA_CLK_SRC				238
+#define SATA_RXOOB_CLK				239
+#define SATA_PMALIVE_CLK			240
+#define SATA_PHY_REF_CLK			241
+#define TSSC_CLK_SRC				242
+#define TSSC_CLK				243
+#define PDM_SRC					244
+#define PDM_CLK					245
+#define GP0_SRC					246
+#define GP0_CLK					247
+#define GP1_SRC					248
+#define GP1_CLK					249
+#define GP2_SRC					250
+#define GP2_CLK					251
+#define MPM_CLK					252
+#define EBI1_CLK_SRC				253
+#define EBI1_CH0_CLK				254
+#define EBI1_CH1_CLK				255
+#define EBI1_2X_CLK				256
+#define EBI1_CH0_DQ_CLK				257
+#define EBI1_CH1_DQ_CLK				258
+#define EBI1_CH0_CA_CLK				259
+#define EBI1_CH1_CA_CLK				260
+#define EBI1_XO_CLK				261
+#define SFAB_SMPSS_S_H_CLK			262
+#define PRNG_SRC				263
+#define PRNG_CLK				264
+#define PXO_SRC					265
+#define LPASS_CXO_CLK				266
+#define LPASS_PXO_CLK				267
+#define SPDM_CY_PORT0_CLK			268
+#define SPDM_CY_PORT1_CLK			269
+#define SPDM_CY_PORT2_CLK			270
+#define SPDM_CY_PORT3_CLK			271
+#define SPDM_CY_PORT4_CLK			272
+#define SPDM_CY_PORT5_CLK			273
+#define SPDM_CY_PORT6_CLK			274
+#define SPDM_CY_PORT7_CLK			275
+#define PLL0					276
+#define PLL0_VOTE				277
+#define PLL3					278
+#define PLL3_VOTE				279
+#define PLL4_VOTE				280
+#define PLL5					281
+#define PLL5_VOTE				282
+#define PLL6					283
+#define PLL6_VOTE				284
+#define PLL7_VOTE				285
+#define PLL8					286
+#define PLL8_VOTE				287
+#define PLL9					288
+#define PLL10					289
+#define PLL11					290
+#define PLL12					291
+#define PLL13					292
+#define PLL14					293
+#define PLL14_VOTE				294
+#define USB_HS3_H_CLK				295
+#define USB_HS3_XCVR_SRC			296
+#define USB_HS3_XCVR_CLK			297
+#define USB_HS4_H_CLK				298
+#define USB_HS4_XCVR_SRC			299
+#define USB_HS4_XCVR_CLK			300
+#define SATA_PHY_CFG_CLK			301
+#define SATA_A_CLK				302
+#define CE3_SRC					303
+#define CE3_CORE_CLK				304
+#define CE3_H_CLK				305
+#define USB_HS1_SYSTEM_CLK_SRC			306
+#define USB_HS1_SYSTEM_CLK			307
+#define EBI2_CLK				308
+#define EBI2_AON_CLK				309
+
+#endif
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/qcom,gcc-msm8660.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/qcom,gcc-msm8660.h
new file mode 100644
index 0000000000000000000000000000000000000000..67665f6813ddea9d1d8fa00081ecd0098a665f19
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/qcom,gcc-msm8660.h
@@ -0,0 +1,276 @@
+/*
+ * Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_CLK_MSM_GCC_8660_H
+#define _DT_BINDINGS_CLK_MSM_GCC_8660_H
+
+#define AFAB_CLK_SRC				0
+#define AFAB_CORE_CLK				1
+#define SCSS_A_CLK				2
+#define SCSS_H_CLK				3
+#define SCSS_XO_SRC_CLK				4
+#define AFAB_EBI1_CH0_A_CLK			5
+#define AFAB_EBI1_CH1_A_CLK			6
+#define AFAB_AXI_S0_FCLK			7
+#define AFAB_AXI_S1_FCLK			8
+#define AFAB_AXI_S2_FCLK			9
+#define AFAB_AXI_S3_FCLK			10
+#define AFAB_AXI_S4_FCLK			11
+#define SFAB_CORE_CLK				12
+#define SFAB_AXI_S0_FCLK			13
+#define SFAB_AXI_S1_FCLK			14
+#define SFAB_AXI_S2_FCLK			15
+#define SFAB_AXI_S3_FCLK			16
+#define SFAB_AXI_S4_FCLK			17
+#define SFAB_AHB_S0_FCLK			18
+#define SFAB_AHB_S1_FCLK			19
+#define SFAB_AHB_S2_FCLK			20
+#define SFAB_AHB_S3_FCLK			21
+#define SFAB_AHB_S4_FCLK			22
+#define SFAB_AHB_S5_FCLK			23
+#define SFAB_AHB_S6_FCLK			24
+#define SFAB_ADM0_M0_A_CLK			25
+#define SFAB_ADM0_M1_A_CLK			26
+#define SFAB_ADM0_M2_A_CLK			27
+#define ADM0_CLK				28
+#define ADM0_PBUS_CLK				29
+#define SFAB_ADM1_M0_A_CLK			30
+#define SFAB_ADM1_M1_A_CLK			31
+#define SFAB_ADM1_M2_A_CLK			32
+#define MMFAB_ADM1_M3_A_CLK			33
+#define ADM1_CLK				34
+#define ADM1_PBUS_CLK				35
+#define IMEM0_A_CLK				36
+#define MAHB0_CLK				37
+#define SFAB_LPASS_Q6_A_CLK			38
+#define SFAB_AFAB_M_A_CLK			39
+#define AFAB_SFAB_M0_A_CLK			40
+#define AFAB_SFAB_M1_A_CLK			41
+#define DFAB_CLK_SRC				42
+#define DFAB_CLK				43
+#define DFAB_CORE_CLK				44
+#define SFAB_DFAB_M_A_CLK			45
+#define DFAB_SFAB_M_A_CLK			46
+#define DFAB_SWAY0_H_CLK			47
+#define DFAB_SWAY1_H_CLK			48
+#define DFAB_ARB0_H_CLK				49
+#define DFAB_ARB1_H_CLK				50
+#define PPSS_H_CLK				51
+#define PPSS_PROC_CLK				52
+#define PPSS_TIMER0_CLK				53
+#define PPSS_TIMER1_CLK				54
+#define PMEM_A_CLK				55
+#define DMA_BAM_H_CLK				56
+#define SIC_H_CLK				57
+#define SPS_TIC_H_CLK				58
+#define SLIMBUS_H_CLK				59
+#define SLIMBUS_XO_SRC_CLK			60
+#define CFPB_2X_CLK_SRC				61
+#define CFPB_CLK				62
+#define CFPB0_H_CLK				63
+#define CFPB1_H_CLK				64
+#define CFPB2_H_CLK				65
+#define EBI2_2X_CLK				66
+#define EBI2_CLK				67
+#define SFAB_CFPB_M_H_CLK			68
+#define CFPB_MASTER_H_CLK			69
+#define SFAB_CFPB_S_HCLK			70
+#define CFPB_SPLITTER_H_CLK			71
+#define TSIF_H_CLK				72
+#define TSIF_INACTIVITY_TIMERS_CLK		73
+#define TSIF_REF_SRC				74
+#define TSIF_REF_CLK				75
+#define CE1_H_CLK				76
+#define CE2_H_CLK				77
+#define SFPB_H_CLK_SRC				78
+#define SFPB_H_CLK				79
+#define SFAB_SFPB_M_H_CLK			80
+#define SFAB_SFPB_S_H_CLK			81
+#define RPM_PROC_CLK				82
+#define RPM_BUS_H_CLK				83
+#define RPM_SLEEP_CLK				84
+#define RPM_TIMER_CLK				85
+#define MODEM_AHB1_H_CLK			86
+#define MODEM_AHB2_H_CLK			87
+#define RPM_MSG_RAM_H_CLK			88
+#define SC_H_CLK				89
+#define SC_A_CLK				90
+#define PMIC_ARB0_H_CLK				91
+#define PMIC_ARB1_H_CLK				92
+#define PMIC_SSBI2_SRC				93
+#define PMIC_SSBI2_CLK				94
+#define SDC1_H_CLK				95
+#define SDC2_H_CLK				96
+#define SDC3_H_CLK				97
+#define SDC4_H_CLK				98
+#define SDC5_H_CLK				99
+#define SDC1_SRC				100
+#define SDC2_SRC				101
+#define SDC3_SRC				102
+#define SDC4_SRC				103
+#define SDC5_SRC				104
+#define SDC1_CLK				105
+#define SDC2_CLK				106
+#define SDC3_CLK				107
+#define SDC4_CLK				108
+#define SDC5_CLK				109
+#define USB_HS1_H_CLK				110
+#define USB_HS1_XCVR_SRC			111
+#define USB_HS1_XCVR_CLK			112
+#define USB_HS2_H_CLK				113
+#define USB_HS2_XCVR_SRC			114
+#define USB_HS2_XCVR_CLK			115
+#define USB_FS1_H_CLK				116
+#define USB_FS1_XCVR_FS_SRC			117
+#define USB_FS1_XCVR_FS_CLK			118
+#define USB_FS1_SYSTEM_CLK			119
+#define USB_FS2_H_CLK				120
+#define USB_FS2_XCVR_FS_SRC			121
+#define USB_FS2_XCVR_FS_CLK			122
+#define USB_FS2_SYSTEM_CLK			123
+#define GSBI_COMMON_SIM_SRC			124
+#define GSBI1_H_CLK				125
+#define GSBI2_H_CLK				126
+#define GSBI3_H_CLK				127
+#define GSBI4_H_CLK				128
+#define GSBI5_H_CLK				129
+#define GSBI6_H_CLK				130
+#define GSBI7_H_CLK				131
+#define GSBI8_H_CLK				132
+#define GSBI9_H_CLK				133
+#define GSBI10_H_CLK				134
+#define GSBI11_H_CLK				135
+#define GSBI12_H_CLK				136
+#define GSBI1_UART_SRC				137
+#define GSBI1_UART_CLK				138
+#define GSBI2_UART_SRC				139
+#define GSBI2_UART_CLK				140
+#define GSBI3_UART_SRC				141
+#define GSBI3_UART_CLK				142
+#define GSBI4_UART_SRC				143
+#define GSBI4_UART_CLK				144
+#define GSBI5_UART_SRC				145
+#define GSBI5_UART_CLK				146
+#define GSBI6_UART_SRC				147
+#define GSBI6_UART_CLK				148
+#define GSBI7_UART_SRC				149
+#define GSBI7_UART_CLK				150
+#define GSBI8_UART_SRC				151
+#define GSBI8_UART_CLK				152
+#define GSBI9_UART_SRC				153
+#define GSBI9_UART_CLK				154
+#define GSBI10_UART_SRC				155
+#define GSBI10_UART_CLK				156
+#define GSBI11_UART_SRC				157
+#define GSBI11_UART_CLK				158
+#define GSBI12_UART_SRC				159
+#define GSBI12_UART_CLK				160
+#define GSBI1_QUP_SRC				161
+#define GSBI1_QUP_CLK				162
+#define GSBI2_QUP_SRC				163
+#define GSBI2_QUP_CLK				164
+#define GSBI3_QUP_SRC				165
+#define GSBI3_QUP_CLK				166
+#define GSBI4_QUP_SRC				167
+#define GSBI4_QUP_CLK				168
+#define GSBI5_QUP_SRC				169
+#define GSBI5_QUP_CLK				170
+#define GSBI6_QUP_SRC				171
+#define GSBI6_QUP_CLK				172
+#define GSBI7_QUP_SRC				173
+#define GSBI7_QUP_CLK				174
+#define GSBI8_QUP_SRC				175
+#define GSBI8_QUP_CLK				176
+#define GSBI9_QUP_SRC				177
+#define GSBI9_QUP_CLK				178
+#define GSBI10_QUP_SRC				179
+#define GSBI10_QUP_CLK				180
+#define GSBI11_QUP_SRC				181
+#define GSBI11_QUP_CLK				182
+#define GSBI12_QUP_SRC				183
+#define GSBI12_QUP_CLK				184
+#define GSBI1_SIM_CLK				185
+#define GSBI2_SIM_CLK				186
+#define GSBI3_SIM_CLK				187
+#define GSBI4_SIM_CLK				188
+#define GSBI5_SIM_CLK				189
+#define GSBI6_SIM_CLK				190
+#define GSBI7_SIM_CLK				191
+#define GSBI8_SIM_CLK				192
+#define GSBI9_SIM_CLK				193
+#define GSBI10_SIM_CLK				194
+#define GSBI11_SIM_CLK				195
+#define GSBI12_SIM_CLK				196
+#define SPDM_CFG_H_CLK				197
+#define SPDM_MSTR_H_CLK				198
+#define SPDM_FF_CLK_SRC				199
+#define SPDM_FF_CLK				200
+#define SEC_CTRL_CLK				201
+#define SEC_CTRL_ACC_CLK_SRC			202
+#define SEC_CTRL_ACC_CLK			203
+#define TLMM_H_CLK				204
+#define TLMM_CLK				205
+#define MARM_CLK_SRC				206
+#define MARM_CLK				207
+#define MAHB1_SRC				208
+#define MAHB1_CLK				209
+#define SFAB_MSS_S_H_CLK			210
+#define MAHB2_SRC				211
+#define MAHB2_CLK				212
+#define MSS_MODEM_CLK_SRC			213
+#define MSS_MODEM_CXO_CLK			214
+#define MSS_SLP_CLK				215
+#define MSS_SYS_REF_CLK				216
+#define TSSC_CLK_SRC				217
+#define TSSC_CLK				218
+#define PDM_SRC					219
+#define PDM_CLK					220
+#define GP0_SRC					221
+#define GP0_CLK					222
+#define GP1_SRC					223
+#define GP1_CLK					224
+#define GP2_SRC					225
+#define GP2_CLK					226
+#define PMEM_CLK				227
+#define MPM_CLK					228
+#define EBI1_ASFAB_SRC				229
+#define EBI1_CLK_SRC				230
+#define EBI1_CH0_CLK				231
+#define EBI1_CH1_CLK				232
+#define SFAB_SMPSS_S_H_CLK			233
+#define PRNG_SRC				234
+#define PRNG_CLK				235
+#define PXO_SRC					236
+#define LPASS_CXO_CLK				237
+#define LPASS_PXO_CLK				238
+#define SPDM_CY_PORT0_CLK			239
+#define SPDM_CY_PORT1_CLK			240
+#define SPDM_CY_PORT2_CLK			241
+#define SPDM_CY_PORT3_CLK			242
+#define SPDM_CY_PORT4_CLK			243
+#define SPDM_CY_PORT5_CLK			244
+#define SPDM_CY_PORT6_CLK			245
+#define SPDM_CY_PORT7_CLK			246
+#define PLL0					247
+#define PLL0_VOTE				248
+#define PLL5					249
+#define PLL6					250
+#define PLL6_VOTE				251
+#define PLL8					252
+#define PLL8_VOTE				253
+#define PLL9					254
+#define PLL10					255
+#define PLL11					256
+#define PLL12					257
+
+#endif
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/qcom,gcc-msm8916.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/qcom,gcc-msm8916.h
new file mode 100644
index 0000000000000000000000000000000000000000..28a27a4ed3c3c27e03dc04bfa13f03ee16d00d47
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/qcom,gcc-msm8916.h
@@ -0,0 +1,187 @@
+/*
+ * Copyright 2015 Linaro Limited
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_CLK_MSM_GCC_8916_H
+#define _DT_BINDINGS_CLK_MSM_GCC_8916_H
+
+#define GPLL0					0
+#define GPLL0_VOTE				1
+#define BIMC_PLL				2
+#define BIMC_PLL_VOTE				3
+#define GPLL1					4
+#define GPLL1_VOTE				5
+#define GPLL2					6
+#define GPLL2_VOTE				7
+#define PCNOC_BFDCD_CLK_SRC			8
+#define SYSTEM_NOC_BFDCD_CLK_SRC		9
+#define CAMSS_AHB_CLK_SRC			10
+#define APSS_AHB_CLK_SRC			11
+#define CSI0_CLK_SRC				12
+#define CSI1_CLK_SRC				13
+#define GFX3D_CLK_SRC				14
+#define VFE0_CLK_SRC				15
+#define BLSP1_QUP1_I2C_APPS_CLK_SRC		16
+#define BLSP1_QUP1_SPI_APPS_CLK_SRC		17
+#define BLSP1_QUP2_I2C_APPS_CLK_SRC		18
+#define BLSP1_QUP2_SPI_APPS_CLK_SRC		19
+#define BLSP1_QUP3_I2C_APPS_CLK_SRC		20
+#define BLSP1_QUP3_SPI_APPS_CLK_SRC		21
+#define BLSP1_QUP4_I2C_APPS_CLK_SRC		22
+#define BLSP1_QUP4_SPI_APPS_CLK_SRC		23
+#define BLSP1_QUP5_I2C_APPS_CLK_SRC		24
+#define BLSP1_QUP5_SPI_APPS_CLK_SRC		25
+#define BLSP1_QUP6_I2C_APPS_CLK_SRC		26
+#define BLSP1_QUP6_SPI_APPS_CLK_SRC		27
+#define BLSP1_UART1_APPS_CLK_SRC		28
+#define BLSP1_UART2_APPS_CLK_SRC		29
+#define CCI_CLK_SRC				30
+#define CAMSS_GP0_CLK_SRC			31
+#define CAMSS_GP1_CLK_SRC			32
+#define JPEG0_CLK_SRC				33
+#define MCLK0_CLK_SRC				34
+#define MCLK1_CLK_SRC				35
+#define CSI0PHYTIMER_CLK_SRC			36
+#define CSI1PHYTIMER_CLK_SRC			37
+#define CPP_CLK_SRC				38
+#define CRYPTO_CLK_SRC				39
+#define GP1_CLK_SRC				40
+#define GP2_CLK_SRC				41
+#define GP3_CLK_SRC				42
+#define BYTE0_CLK_SRC				43
+#define ESC0_CLK_SRC				44
+#define MDP_CLK_SRC				45
+#define PCLK0_CLK_SRC				46
+#define VSYNC_CLK_SRC				47
+#define PDM2_CLK_SRC				48
+#define SDCC1_APPS_CLK_SRC			49
+#define SDCC2_APPS_CLK_SRC			50
+#define APSS_TCU_CLK_SRC			51
+#define USB_HS_SYSTEM_CLK_SRC			52
+#define VCODEC0_CLK_SRC				53
+#define GCC_BLSP1_AHB_CLK			54
+#define GCC_BLSP1_SLEEP_CLK			55
+#define GCC_BLSP1_QUP1_I2C_APPS_CLK		56
+#define GCC_BLSP1_QUP1_SPI_APPS_CLK		57
+#define GCC_BLSP1_QUP2_I2C_APPS_CLK		58
+#define GCC_BLSP1_QUP2_SPI_APPS_CLK		59
+#define GCC_BLSP1_QUP3_I2C_APPS_CLK		60
+#define GCC_BLSP1_QUP3_SPI_APPS_CLK		61
+#define GCC_BLSP1_QUP4_I2C_APPS_CLK		62
+#define GCC_BLSP1_QUP4_SPI_APPS_CLK		63
+#define GCC_BLSP1_QUP5_I2C_APPS_CLK		64
+#define GCC_BLSP1_QUP5_SPI_APPS_CLK		65
+#define GCC_BLSP1_QUP6_I2C_APPS_CLK		66
+#define GCC_BLSP1_QUP6_SPI_APPS_CLK		67
+#define GCC_BLSP1_UART1_APPS_CLK		68
+#define GCC_BLSP1_UART2_APPS_CLK		69
+#define GCC_BOOT_ROM_AHB_CLK			70
+#define GCC_CAMSS_CCI_AHB_CLK			71
+#define GCC_CAMSS_CCI_CLK			72
+#define GCC_CAMSS_CSI0_AHB_CLK			73
+#define GCC_CAMSS_CSI0_CLK			74
+#define GCC_CAMSS_CSI0PHY_CLK			75
+#define GCC_CAMSS_CSI0PIX_CLK			76
+#define GCC_CAMSS_CSI0RDI_CLK			77
+#define GCC_CAMSS_CSI1_AHB_CLK			78
+#define GCC_CAMSS_CSI1_CLK			79
+#define GCC_CAMSS_CSI1PHY_CLK			80
+#define GCC_CAMSS_CSI1PIX_CLK			81
+#define GCC_CAMSS_CSI1RDI_CLK			82
+#define GCC_CAMSS_CSI_VFE0_CLK			83
+#define GCC_CAMSS_GP0_CLK			84
+#define GCC_CAMSS_GP1_CLK			85
+#define GCC_CAMSS_ISPIF_AHB_CLK			86
+#define GCC_CAMSS_JPEG0_CLK			87
+#define GCC_CAMSS_JPEG_AHB_CLK			88
+#define GCC_CAMSS_JPEG_AXI_CLK			89
+#define GCC_CAMSS_MCLK0_CLK			90
+#define GCC_CAMSS_MCLK1_CLK			91
+#define GCC_CAMSS_MICRO_AHB_CLK			92
+#define GCC_CAMSS_CSI0PHYTIMER_CLK		93
+#define GCC_CAMSS_CSI1PHYTIMER_CLK		94
+#define GCC_CAMSS_AHB_CLK			95
+#define GCC_CAMSS_TOP_AHB_CLK			96
+#define GCC_CAMSS_CPP_AHB_CLK			97
+#define GCC_CAMSS_CPP_CLK			98
+#define GCC_CAMSS_VFE0_CLK			99
+#define GCC_CAMSS_VFE_AHB_CLK			100
+#define GCC_CAMSS_VFE_AXI_CLK			101
+#define GCC_CRYPTO_AHB_CLK			102
+#define GCC_CRYPTO_AXI_CLK			103
+#define GCC_CRYPTO_CLK				104
+#define GCC_OXILI_GMEM_CLK			105
+#define GCC_GP1_CLK				106
+#define GCC_GP2_CLK				107
+#define GCC_GP3_CLK				108
+#define GCC_MDSS_AHB_CLK			109
+#define GCC_MDSS_AXI_CLK			110
+#define GCC_MDSS_BYTE0_CLK			111
+#define GCC_MDSS_ESC0_CLK			112
+#define GCC_MDSS_MDP_CLK			113
+#define GCC_MDSS_PCLK0_CLK			114
+#define GCC_MDSS_VSYNC_CLK			115
+#define GCC_MSS_CFG_AHB_CLK			116
+#define GCC_OXILI_AHB_CLK			117
+#define GCC_OXILI_GFX3D_CLK			118
+#define GCC_PDM2_CLK				119
+#define GCC_PDM_AHB_CLK				120
+#define GCC_PRNG_AHB_CLK			121
+#define GCC_SDCC1_AHB_CLK			122
+#define GCC_SDCC1_APPS_CLK			123
+#define GCC_SDCC2_AHB_CLK			124
+#define GCC_SDCC2_APPS_CLK			125
+#define GCC_GTCU_AHB_CLK			126
+#define GCC_JPEG_TBU_CLK			127
+#define GCC_MDP_TBU_CLK				128
+#define GCC_SMMU_CFG_CLK			129
+#define GCC_VENUS_TBU_CLK			130
+#define GCC_VFE_TBU_CLK				131
+#define GCC_USB2A_PHY_SLEEP_CLK			132
+#define GCC_USB_HS_AHB_CLK			133
+#define GCC_USB_HS_SYSTEM_CLK			134
+#define GCC_VENUS0_AHB_CLK			135
+#define GCC_VENUS0_AXI_CLK			136
+#define GCC_VENUS0_VCODEC0_CLK			137
+#define BIMC_DDR_CLK_SRC			138
+#define GCC_APSS_TCU_CLK			139
+#define GCC_GFX_TCU_CLK				140
+#define BIMC_GPU_CLK_SRC			141
+#define GCC_BIMC_GFX_CLK			142
+#define GCC_BIMC_GPU_CLK			143
+#define ULTAUDIO_LPAIF_PRI_I2S_CLK_SRC		144
+#define ULTAUDIO_LPAIF_SEC_I2S_CLK_SRC		145
+#define ULTAUDIO_LPAIF_AUX_I2S_CLK_SRC		146
+#define ULTAUDIO_XO_CLK_SRC			147
+#define ULTAUDIO_AHBFABRIC_CLK_SRC		148
+#define CODEC_DIGCODEC_CLK_SRC			149
+#define GCC_ULTAUDIO_PCNOC_MPORT_CLK		150
+#define GCC_ULTAUDIO_PCNOC_SWAY_CLK		151
+#define GCC_ULTAUDIO_AVSYNC_XO_CLK		152
+#define GCC_ULTAUDIO_STC_XO_CLK			153
+#define GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK	154
+#define GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_CLK	155
+#define GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK		156
+#define GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK		157
+#define GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK		158
+#define GCC_CODEC_DIGCODEC_CLK			159
+#define GCC_MSS_Q6_BIMC_AXI_CLK			160
+
+/* Indexes for GDSCs */
+#define BIMC_GDSC				0
+#define VENUS_GDSC				1
+#define MDSS_GDSC				2
+#define JPEG_GDSC				3
+#define VFE_GDSC				4
+#define OXILI_GDSC				5
+
+#endif
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/qcom,gcc-msm8960.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/qcom,gcc-msm8960.h
new file mode 100644
index 0000000000000000000000000000000000000000..7d20eedfee9898592ce7265da188d0482e04420d
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/qcom,gcc-msm8960.h
@@ -0,0 +1,323 @@
+/*
+ * Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_CLK_MSM_GCC_8960_H
+#define _DT_BINDINGS_CLK_MSM_GCC_8960_H
+
+#define AFAB_CLK_SRC				0
+#define AFAB_CORE_CLK				1
+#define SFAB_MSS_Q6_SW_A_CLK			2
+#define SFAB_MSS_Q6_FW_A_CLK			3
+#define QDSS_STM_CLK				4
+#define SCSS_A_CLK				5
+#define SCSS_H_CLK				6
+#define SCSS_XO_SRC_CLK				7
+#define AFAB_EBI1_CH0_A_CLK			8
+#define AFAB_EBI1_CH1_A_CLK			9
+#define AFAB_AXI_S0_FCLK			10
+#define AFAB_AXI_S1_FCLK			11
+#define AFAB_AXI_S2_FCLK			12
+#define AFAB_AXI_S3_FCLK			13
+#define AFAB_AXI_S4_FCLK			14
+#define SFAB_CORE_CLK				15
+#define SFAB_AXI_S0_FCLK			16
+#define SFAB_AXI_S1_FCLK			17
+#define SFAB_AXI_S2_FCLK			18
+#define SFAB_AXI_S3_FCLK			19
+#define SFAB_AXI_S4_FCLK			20
+#define SFAB_AHB_S0_FCLK			21
+#define SFAB_AHB_S1_FCLK			22
+#define SFAB_AHB_S2_FCLK			23
+#define SFAB_AHB_S3_FCLK			24
+#define SFAB_AHB_S4_FCLK			25
+#define SFAB_AHB_S5_FCLK			26
+#define SFAB_AHB_S6_FCLK			27
+#define SFAB_AHB_S7_FCLK			28
+#define QDSS_AT_CLK_SRC				29
+#define QDSS_AT_CLK				30
+#define QDSS_TRACECLKIN_CLK_SRC			31
+#define QDSS_TRACECLKIN_CLK			32
+#define QDSS_TSCTR_CLK_SRC			33
+#define QDSS_TSCTR_CLK				34
+#define SFAB_ADM0_M0_A_CLK			35
+#define SFAB_ADM0_M1_A_CLK			36
+#define SFAB_ADM0_M2_H_CLK			37
+#define ADM0_CLK				38
+#define ADM0_PBUS_CLK				39
+#define MSS_XPU_CLK				40
+#define IMEM0_A_CLK				41
+#define QDSS_H_CLK				42
+#define PCIE_A_CLK				43
+#define PCIE_AUX_CLK				44
+#define PCIE_PHY_REF_CLK			45
+#define PCIE_H_CLK				46
+#define SFAB_CLK_SRC				47
+#define MAHB0_CLK				48
+#define Q6SW_CLK_SRC				49
+#define Q6SW_CLK				50
+#define Q6FW_CLK_SRC				51
+#define Q6FW_CLK				52
+#define SFAB_MSS_M_A_CLK			53
+#define SFAB_USB3_M_A_CLK			54
+#define SFAB_LPASS_Q6_A_CLK			55
+#define SFAB_AFAB_M_A_CLK			56
+#define AFAB_SFAB_M0_A_CLK			57
+#define AFAB_SFAB_M1_A_CLK			58
+#define SFAB_SATA_S_H_CLK			59
+#define DFAB_CLK_SRC				60
+#define DFAB_CLK				61
+#define SFAB_DFAB_M_A_CLK			62
+#define DFAB_SFAB_M_A_CLK			63
+#define DFAB_SWAY0_H_CLK			64
+#define DFAB_SWAY1_H_CLK			65
+#define DFAB_ARB0_H_CLK				66
+#define DFAB_ARB1_H_CLK				67
+#define PPSS_H_CLK				68
+#define PPSS_PROC_CLK				69
+#define PPSS_TIMER0_CLK				70
+#define PPSS_TIMER1_CLK				71
+#define PMEM_A_CLK				72
+#define DMA_BAM_H_CLK				73
+#define SIC_H_CLK				74
+#define SPS_TIC_H_CLK				75
+#define SLIMBUS_H_CLK				76
+#define SLIMBUS_XO_SRC_CLK			77
+#define CFPB_2X_CLK_SRC				78
+#define CFPB_CLK				79
+#define CFPB0_H_CLK				80
+#define CFPB1_H_CLK				81
+#define CFPB2_H_CLK				82
+#define SFAB_CFPB_M_H_CLK			83
+#define CFPB_MASTER_H_CLK			84
+#define SFAB_CFPB_S_H_CLK			85
+#define CFPB_SPLITTER_H_CLK			86
+#define TSIF_H_CLK				87
+#define TSIF_INACTIVITY_TIMERS_CLK		88
+#define TSIF_REF_SRC				89
+#define TSIF_REF_CLK				90
+#define CE1_H_CLK				91
+#define CE1_CORE_CLK				92
+#define CE1_SLEEP_CLK				93
+#define CE2_H_CLK				94
+#define CE2_CORE_CLK				95
+#define SFPB_H_CLK_SRC				97
+#define SFPB_H_CLK				98
+#define SFAB_SFPB_M_H_CLK			99
+#define SFAB_SFPB_S_H_CLK			100
+#define RPM_PROC_CLK				101
+#define RPM_BUS_H_CLK				102
+#define RPM_SLEEP_CLK				103
+#define RPM_TIMER_CLK				104
+#define RPM_MSG_RAM_H_CLK			105
+#define PMIC_ARB0_H_CLK				106
+#define PMIC_ARB1_H_CLK				107
+#define PMIC_SSBI2_SRC				108
+#define PMIC_SSBI2_CLK				109
+#define SDC1_H_CLK				110
+#define SDC2_H_CLK				111
+#define SDC3_H_CLK				112
+#define SDC4_H_CLK				113
+#define SDC5_H_CLK				114
+#define SDC1_SRC				115
+#define SDC2_SRC				116
+#define SDC3_SRC				117
+#define SDC4_SRC				118
+#define SDC5_SRC				119
+#define SDC1_CLK				120
+#define SDC2_CLK				121
+#define SDC3_CLK				122
+#define SDC4_CLK				123
+#define SDC5_CLK				124
+#define DFAB_A2_H_CLK				125
+#define USB_HS1_H_CLK				126
+#define USB_HS1_XCVR_SRC			127
+#define USB_HS1_XCVR_CLK			128
+#define USB_HSIC_H_CLK				129
+#define USB_HSIC_XCVR_FS_SRC			130
+#define USB_HSIC_XCVR_FS_CLK			131
+#define USB_HSIC_SYSTEM_CLK_SRC			132
+#define USB_HSIC_SYSTEM_CLK			133
+#define CFPB0_C0_H_CLK				134
+#define CFPB0_C1_H_CLK				135
+#define CFPB0_D0_H_CLK				136
+#define CFPB0_D1_H_CLK				137
+#define USB_FS1_H_CLK				138
+#define USB_FS1_XCVR_FS_SRC			139
+#define USB_FS1_XCVR_FS_CLK			140
+#define USB_FS1_SYSTEM_CLK			141
+#define USB_FS2_H_CLK				142
+#define USB_FS2_XCVR_FS_SRC			143
+#define USB_FS2_XCVR_FS_CLK			144
+#define USB_FS2_SYSTEM_CLK			145
+#define GSBI_COMMON_SIM_SRC			146
+#define GSBI1_H_CLK				147
+#define GSBI2_H_CLK				148
+#define GSBI3_H_CLK				149
+#define GSBI4_H_CLK				150
+#define GSBI5_H_CLK				151
+#define GSBI6_H_CLK				152
+#define GSBI7_H_CLK				153
+#define GSBI8_H_CLK				154
+#define GSBI9_H_CLK				155
+#define GSBI10_H_CLK				156
+#define GSBI11_H_CLK				157
+#define GSBI12_H_CLK				158
+#define GSBI1_UART_SRC				159
+#define GSBI1_UART_CLK				160
+#define GSBI2_UART_SRC				161
+#define GSBI2_UART_CLK				162
+#define GSBI3_UART_SRC				163
+#define GSBI3_UART_CLK				164
+#define GSBI4_UART_SRC				165
+#define GSBI4_UART_CLK				166
+#define GSBI5_UART_SRC				167
+#define GSBI5_UART_CLK				168
+#define GSBI6_UART_SRC				169
+#define GSBI6_UART_CLK				170
+#define GSBI7_UART_SRC				171
+#define GSBI7_UART_CLK				172
+#define GSBI8_UART_SRC				173
+#define GSBI8_UART_CLK				174
+#define GSBI9_UART_SRC				175
+#define GSBI9_UART_CLK				176
+#define GSBI10_UART_SRC				177
+#define GSBI10_UART_CLK				178
+#define GSBI11_UART_SRC				179
+#define GSBI11_UART_CLK				180
+#define GSBI12_UART_SRC				181
+#define GSBI12_UART_CLK				182
+#define GSBI1_QUP_SRC				183
+#define GSBI1_QUP_CLK				184
+#define GSBI2_QUP_SRC				185
+#define GSBI2_QUP_CLK				186
+#define GSBI3_QUP_SRC				187
+#define GSBI3_QUP_CLK				188
+#define GSBI4_QUP_SRC				189
+#define GSBI4_QUP_CLK				190
+#define GSBI5_QUP_SRC				191
+#define GSBI5_QUP_CLK				192
+#define GSBI6_QUP_SRC				193
+#define GSBI6_QUP_CLK				194
+#define GSBI7_QUP_SRC				195
+#define GSBI7_QUP_CLK				196
+#define GSBI8_QUP_SRC				197
+#define GSBI8_QUP_CLK				198
+#define GSBI9_QUP_SRC				199
+#define GSBI9_QUP_CLK				200
+#define GSBI10_QUP_SRC				201
+#define GSBI10_QUP_CLK				202
+#define GSBI11_QUP_SRC				203
+#define GSBI11_QUP_CLK				204
+#define GSBI12_QUP_SRC				205
+#define GSBI12_QUP_CLK				206
+#define GSBI1_SIM_CLK				207
+#define GSBI2_SIM_CLK				208
+#define GSBI3_SIM_CLK				209
+#define GSBI4_SIM_CLK				210
+#define GSBI5_SIM_CLK				211
+#define GSBI6_SIM_CLK				212
+#define GSBI7_SIM_CLK				213
+#define GSBI8_SIM_CLK				214
+#define GSBI9_SIM_CLK				215
+#define GSBI10_SIM_CLK				216
+#define GSBI11_SIM_CLK				217
+#define GSBI12_SIM_CLK				218
+#define USB_HSIC_HSIC_CLK_SRC			219
+#define USB_HSIC_HSIC_CLK			220
+#define USB_HSIC_HSIO_CAL_CLK			221
+#define SPDM_CFG_H_CLK				222
+#define SPDM_MSTR_H_CLK				223
+#define SPDM_FF_CLK_SRC				224
+#define SPDM_FF_CLK				225
+#define SEC_CTRL_CLK				226
+#define SEC_CTRL_ACC_CLK_SRC			227
+#define SEC_CTRL_ACC_CLK			228
+#define TLMM_H_CLK				229
+#define TLMM_CLK				230
+#define SFAB_MSS_S_H_CLK			231
+#define MSS_SLP_CLK				232
+#define MSS_Q6SW_JTAG_CLK			233
+#define MSS_Q6FW_JTAG_CLK			234
+#define MSS_S_H_CLK				235
+#define MSS_CXO_SRC_CLK				236
+#define SATA_H_CLK				237
+#define SATA_CLK_SRC				238
+#define SATA_RXOOB_CLK				239
+#define SATA_PMALIVE_CLK			240
+#define SATA_PHY_REF_CLK			241
+#define TSSC_CLK_SRC				242
+#define TSSC_CLK				243
+#define PDM_SRC					244
+#define PDM_CLK					245
+#define GP0_SRC					246
+#define GP0_CLK					247
+#define GP1_SRC					248
+#define GP1_CLK					249
+#define GP2_SRC					250
+#define GP2_CLK					251
+#define MPM_CLK					252
+#define EBI1_CLK_SRC				253
+#define EBI1_CH0_CLK				254
+#define EBI1_CH1_CLK				255
+#define EBI1_2X_CLK				256
+#define EBI1_CH0_DQ_CLK				257
+#define EBI1_CH1_DQ_CLK				258
+#define EBI1_CH0_CA_CLK				259
+#define EBI1_CH1_CA_CLK				260
+#define EBI1_XO_CLK				261
+#define SFAB_SMPSS_S_H_CLK			262
+#define PRNG_SRC				263
+#define PRNG_CLK				264
+#define PXO_SRC					265
+#define LPASS_CXO_CLK				266
+#define LPASS_PXO_CLK				267
+#define SPDM_CY_PORT0_CLK			268
+#define SPDM_CY_PORT1_CLK			269
+#define SPDM_CY_PORT2_CLK			270
+#define SPDM_CY_PORT3_CLK			271
+#define SPDM_CY_PORT4_CLK			272
+#define SPDM_CY_PORT5_CLK			273
+#define SPDM_CY_PORT6_CLK			274
+#define SPDM_CY_PORT7_CLK			275
+#define PLL0					276
+#define PLL0_VOTE				277
+#define PLL3					278
+#define PLL3_VOTE				279
+#define PLL4_VOTE				280
+#define PLL5					281
+#define PLL5_VOTE				282
+#define PLL6					283
+#define PLL6_VOTE				284
+#define PLL7_VOTE				285
+#define PLL8					286
+#define PLL8_VOTE				287
+#define PLL9					288
+#define PLL10					289
+#define PLL11					290
+#define PLL12					291
+#define PLL13					292
+#define PLL14					293
+#define PLL14_VOTE				294
+#define USB_HS3_H_CLK				295
+#define USB_HS3_XCVR_SRC			296
+#define USB_HS3_XCVR_CLK			297
+#define USB_HS4_H_CLK				298
+#define USB_HS4_XCVR_SRC			299
+#define USB_HS4_XCVR_CLK			300
+#define SATA_PHY_CFG_CLK			301
+#define SATA_A_CLK				302
+#define CE3_SRC					303
+#define CE3_CORE_CLK				304
+#define CE3_H_CLK				305
+
+#endif
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/qcom,gcc-msm8974.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/qcom,gcc-msm8974.h
new file mode 100644
index 0000000000000000000000000000000000000000..81d32f63919007403ae576e15dfb87a70c23f9cd
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/qcom,gcc-msm8974.h
@@ -0,0 +1,327 @@
+/*
+ * Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_CLK_MSM_GCC_8974_H
+#define _DT_BINDINGS_CLK_MSM_GCC_8974_H
+
+#define GPLL0							0
+#define GPLL0_VOTE						1
+#define CONFIG_NOC_CLK_SRC					2
+#define GPLL2							3
+#define GPLL2_VOTE						4
+#define GPLL3							5
+#define GPLL3_VOTE						6
+#define PERIPH_NOC_CLK_SRC					7
+#define BLSP_UART_SIM_CLK_SRC					8
+#define QDSS_TSCTR_CLK_SRC					9
+#define BIMC_DDR_CLK_SRC					10
+#define SYSTEM_NOC_CLK_SRC					11
+#define GPLL1							12
+#define GPLL1_VOTE						13
+#define RPM_CLK_SRC						14
+#define GCC_BIMC_CLK						15
+#define BIMC_DDR_CPLL0_ROOT_CLK_SRC				16
+#define KPSS_AHB_CLK_SRC					17
+#define QDSS_AT_CLK_SRC						18
+#define USB30_MASTER_CLK_SRC					19
+#define BIMC_DDR_CPLL1_ROOT_CLK_SRC				20
+#define QDSS_STM_CLK_SRC					21
+#define ACC_CLK_SRC						22
+#define SEC_CTRL_CLK_SRC					23
+#define BLSP1_QUP1_I2C_APPS_CLK_SRC				24
+#define BLSP1_QUP1_SPI_APPS_CLK_SRC				25
+#define BLSP1_QUP2_I2C_APPS_CLK_SRC				26
+#define BLSP1_QUP2_SPI_APPS_CLK_SRC				27
+#define BLSP1_QUP3_I2C_APPS_CLK_SRC				28
+#define BLSP1_QUP3_SPI_APPS_CLK_SRC				29
+#define BLSP1_QUP4_I2C_APPS_CLK_SRC				30
+#define BLSP1_QUP4_SPI_APPS_CLK_SRC				31
+#define BLSP1_QUP5_I2C_APPS_CLK_SRC				32
+#define BLSP1_QUP5_SPI_APPS_CLK_SRC				33
+#define BLSP1_QUP6_I2C_APPS_CLK_SRC				34
+#define BLSP1_QUP6_SPI_APPS_CLK_SRC				35
+#define BLSP1_UART1_APPS_CLK_SRC				36
+#define BLSP1_UART2_APPS_CLK_SRC				37
+#define BLSP1_UART3_APPS_CLK_SRC				38
+#define BLSP1_UART4_APPS_CLK_SRC				39
+#define BLSP1_UART5_APPS_CLK_SRC				40
+#define BLSP1_UART6_APPS_CLK_SRC				41
+#define BLSP2_QUP1_I2C_APPS_CLK_SRC				42
+#define BLSP2_QUP1_SPI_APPS_CLK_SRC				43
+#define BLSP2_QUP2_I2C_APPS_CLK_SRC				44
+#define BLSP2_QUP2_SPI_APPS_CLK_SRC				45
+#define BLSP2_QUP3_I2C_APPS_CLK_SRC				46
+#define BLSP2_QUP3_SPI_APPS_CLK_SRC				47
+#define BLSP2_QUP4_I2C_APPS_CLK_SRC				48
+#define BLSP2_QUP4_SPI_APPS_CLK_SRC				49
+#define BLSP2_QUP5_I2C_APPS_CLK_SRC				50
+#define BLSP2_QUP5_SPI_APPS_CLK_SRC				51
+#define BLSP2_QUP6_I2C_APPS_CLK_SRC				52
+#define BLSP2_QUP6_SPI_APPS_CLK_SRC				53
+#define BLSP2_UART1_APPS_CLK_SRC				54
+#define BLSP2_UART2_APPS_CLK_SRC				55
+#define BLSP2_UART3_APPS_CLK_SRC				56
+#define BLSP2_UART4_APPS_CLK_SRC				57
+#define BLSP2_UART5_APPS_CLK_SRC				58
+#define BLSP2_UART6_APPS_CLK_SRC				59
+#define CE1_CLK_SRC						60
+#define CE2_CLK_SRC						61
+#define GP1_CLK_SRC						62
+#define GP2_CLK_SRC						63
+#define GP3_CLK_SRC						64
+#define PDM2_CLK_SRC						65
+#define QDSS_TRACECLKIN_CLK_SRC					66
+#define RBCPR_CLK_SRC						67
+#define SDCC1_APPS_CLK_SRC					68
+#define SDCC2_APPS_CLK_SRC					69
+#define SDCC3_APPS_CLK_SRC					70
+#define SDCC4_APPS_CLK_SRC					71
+#define SPMI_AHB_CLK_SRC					72
+#define SPMI_SER_CLK_SRC					73
+#define TSIF_REF_CLK_SRC					74
+#define USB30_MOCK_UTMI_CLK_SRC					75
+#define USB_HS_SYSTEM_CLK_SRC					76
+#define USB_HSIC_CLK_SRC					77
+#define USB_HSIC_IO_CAL_CLK_SRC					78
+#define USB_HSIC_SYSTEM_CLK_SRC					79
+#define GCC_BAM_DMA_AHB_CLK					80
+#define GCC_BAM_DMA_INACTIVITY_TIMERS_CLK			81
+#define GCC_BIMC_CFG_AHB_CLK					82
+#define GCC_BIMC_KPSS_AXI_CLK					83
+#define GCC_BIMC_SLEEP_CLK					84
+#define GCC_BIMC_SYSNOC_AXI_CLK					85
+#define GCC_BIMC_XO_CLK						86
+#define GCC_BLSP1_AHB_CLK					87
+#define GCC_BLSP1_SLEEP_CLK					88
+#define GCC_BLSP1_QUP1_I2C_APPS_CLK				89
+#define GCC_BLSP1_QUP1_SPI_APPS_CLK				90
+#define GCC_BLSP1_QUP2_I2C_APPS_CLK				91
+#define GCC_BLSP1_QUP2_SPI_APPS_CLK				92
+#define GCC_BLSP1_QUP3_I2C_APPS_CLK				93
+#define GCC_BLSP1_QUP3_SPI_APPS_CLK				94
+#define GCC_BLSP1_QUP4_I2C_APPS_CLK				95
+#define GCC_BLSP1_QUP4_SPI_APPS_CLK				96
+#define GCC_BLSP1_QUP5_I2C_APPS_CLK				97
+#define GCC_BLSP1_QUP5_SPI_APPS_CLK				98
+#define GCC_BLSP1_QUP6_I2C_APPS_CLK				99
+#define GCC_BLSP1_QUP6_SPI_APPS_CLK				100
+#define GCC_BLSP1_UART1_APPS_CLK				101
+#define GCC_BLSP1_UART1_SIM_CLK					102
+#define GCC_BLSP1_UART2_APPS_CLK				103
+#define GCC_BLSP1_UART2_SIM_CLK					104
+#define GCC_BLSP1_UART3_APPS_CLK				105
+#define GCC_BLSP1_UART3_SIM_CLK					106
+#define GCC_BLSP1_UART4_APPS_CLK				107
+#define GCC_BLSP1_UART4_SIM_CLK					108
+#define GCC_BLSP1_UART5_APPS_CLK				109
+#define GCC_BLSP1_UART5_SIM_CLK					110
+#define GCC_BLSP1_UART6_APPS_CLK				111
+#define GCC_BLSP1_UART6_SIM_CLK					112
+#define GCC_BLSP2_AHB_CLK					113
+#define GCC_BLSP2_SLEEP_CLK					114
+#define GCC_BLSP2_QUP1_I2C_APPS_CLK				115
+#define GCC_BLSP2_QUP1_SPI_APPS_CLK				116
+#define GCC_BLSP2_QUP2_I2C_APPS_CLK				117
+#define GCC_BLSP2_QUP2_SPI_APPS_CLK				118
+#define GCC_BLSP2_QUP3_I2C_APPS_CLK				119
+#define GCC_BLSP2_QUP3_SPI_APPS_CLK				120
+#define GCC_BLSP2_QUP4_I2C_APPS_CLK				121
+#define GCC_BLSP2_QUP4_SPI_APPS_CLK				122
+#define GCC_BLSP2_QUP5_I2C_APPS_CLK				123
+#define GCC_BLSP2_QUP5_SPI_APPS_CLK				124
+#define GCC_BLSP2_QUP6_I2C_APPS_CLK				125
+#define GCC_BLSP2_QUP6_SPI_APPS_CLK				126
+#define GCC_BLSP2_UART1_APPS_CLK				127
+#define GCC_BLSP2_UART1_SIM_CLK					128
+#define GCC_BLSP2_UART2_APPS_CLK				129
+#define GCC_BLSP2_UART2_SIM_CLK					130
+#define GCC_BLSP2_UART3_APPS_CLK				131
+#define GCC_BLSP2_UART3_SIM_CLK					132
+#define GCC_BLSP2_UART4_APPS_CLK				133
+#define GCC_BLSP2_UART4_SIM_CLK					134
+#define GCC_BLSP2_UART5_APPS_CLK				135
+#define GCC_BLSP2_UART5_SIM_CLK					136
+#define GCC_BLSP2_UART6_APPS_CLK				137
+#define GCC_BLSP2_UART6_SIM_CLK					138
+#define GCC_BOOT_ROM_AHB_CLK					139
+#define GCC_CE1_AHB_CLK						140
+#define GCC_CE1_AXI_CLK						141
+#define GCC_CE1_CLK						142
+#define GCC_CE2_AHB_CLK						143
+#define GCC_CE2_AXI_CLK						144
+#define GCC_CE2_CLK						145
+#define GCC_CNOC_BUS_TIMEOUT0_AHB_CLK				146
+#define GCC_CNOC_BUS_TIMEOUT1_AHB_CLK				147
+#define GCC_CNOC_BUS_TIMEOUT2_AHB_CLK				148
+#define GCC_CNOC_BUS_TIMEOUT3_AHB_CLK				149
+#define GCC_CNOC_BUS_TIMEOUT4_AHB_CLK				150
+#define GCC_CNOC_BUS_TIMEOUT5_AHB_CLK				151
+#define GCC_CNOC_BUS_TIMEOUT6_AHB_CLK				152
+#define GCC_CFG_NOC_AHB_CLK					153
+#define GCC_CFG_NOC_DDR_CFG_CLK					154
+#define GCC_CFG_NOC_RPM_AHB_CLK					155
+#define GCC_BIMC_DDR_CPLL0_CLK					156
+#define GCC_BIMC_DDR_CPLL1_CLK					157
+#define GCC_DDR_DIM_CFG_CLK					158
+#define GCC_DDR_DIM_SLEEP_CLK					159
+#define GCC_DEHR_CLK						160
+#define GCC_AHB_CLK						161
+#define GCC_IM_SLEEP_CLK					162
+#define GCC_XO_CLK						163
+#define GCC_XO_DIV4_CLK						164
+#define GCC_GP1_CLK						165
+#define GCC_GP2_CLK						166
+#define GCC_GP3_CLK						167
+#define GCC_IMEM_AXI_CLK					168
+#define GCC_IMEM_CFG_AHB_CLK					169
+#define GCC_KPSS_AHB_CLK					170
+#define GCC_KPSS_AXI_CLK					171
+#define GCC_LPASS_Q6_AXI_CLK					172
+#define GCC_MMSS_NOC_AT_CLK					173
+#define GCC_MMSS_NOC_CFG_AHB_CLK				174
+#define GCC_OCMEM_NOC_CFG_AHB_CLK				175
+#define GCC_OCMEM_SYS_NOC_AXI_CLK				176
+#define GCC_MPM_AHB_CLK						177
+#define GCC_MSG_RAM_AHB_CLK					178
+#define GCC_MSS_CFG_AHB_CLK					179
+#define GCC_MSS_Q6_BIMC_AXI_CLK					180
+#define GCC_NOC_CONF_XPU_AHB_CLK				181
+#define GCC_PDM2_CLK						182
+#define GCC_PDM_AHB_CLK						183
+#define GCC_PDM_XO4_CLK						184
+#define GCC_PERIPH_NOC_AHB_CLK					185
+#define GCC_PERIPH_NOC_AT_CLK					186
+#define GCC_PERIPH_NOC_CFG_AHB_CLK				187
+#define GCC_PERIPH_NOC_MPU_CFG_AHB_CLK				188
+#define GCC_PERIPH_XPU_AHB_CLK					189
+#define GCC_PNOC_BUS_TIMEOUT0_AHB_CLK				190
+#define GCC_PNOC_BUS_TIMEOUT1_AHB_CLK				191
+#define GCC_PNOC_BUS_TIMEOUT2_AHB_CLK				192
+#define GCC_PNOC_BUS_TIMEOUT3_AHB_CLK				193
+#define GCC_PNOC_BUS_TIMEOUT4_AHB_CLK				194
+#define GCC_PRNG_AHB_CLK					195
+#define GCC_QDSS_AT_CLK						196
+#define GCC_QDSS_CFG_AHB_CLK					197
+#define GCC_QDSS_DAP_AHB_CLK					198
+#define GCC_QDSS_DAP_CLK					199
+#define GCC_QDSS_ETR_USB_CLK					200
+#define GCC_QDSS_STM_CLK					201
+#define GCC_QDSS_TRACECLKIN_CLK					202
+#define GCC_QDSS_TSCTR_DIV16_CLK				203
+#define GCC_QDSS_TSCTR_DIV2_CLK					204
+#define GCC_QDSS_TSCTR_DIV3_CLK					205
+#define GCC_QDSS_TSCTR_DIV4_CLK					206
+#define GCC_QDSS_TSCTR_DIV8_CLK					207
+#define GCC_QDSS_RBCPR_XPU_AHB_CLK				208
+#define GCC_RBCPR_AHB_CLK					209
+#define GCC_RBCPR_CLK						210
+#define GCC_RPM_BUS_AHB_CLK					211
+#define GCC_RPM_PROC_HCLK					212
+#define GCC_RPM_SLEEP_CLK					213
+#define GCC_RPM_TIMER_CLK					214
+#define GCC_SDCC1_AHB_CLK					215
+#define GCC_SDCC1_APPS_CLK					216
+#define GCC_SDCC1_INACTIVITY_TIMERS_CLK				217
+#define GCC_SDCC2_AHB_CLK					218
+#define GCC_SDCC2_APPS_CLK					219
+#define GCC_SDCC2_INACTIVITY_TIMERS_CLK				220
+#define GCC_SDCC3_AHB_CLK					221
+#define GCC_SDCC3_APPS_CLK					222
+#define GCC_SDCC3_INACTIVITY_TIMERS_CLK				223
+#define GCC_SDCC4_AHB_CLK					224
+#define GCC_SDCC4_APPS_CLK					225
+#define GCC_SDCC4_INACTIVITY_TIMERS_CLK				226
+#define GCC_SEC_CTRL_ACC_CLK					227
+#define GCC_SEC_CTRL_AHB_CLK					228
+#define GCC_SEC_CTRL_BOOT_ROM_PATCH_CLK				229
+#define GCC_SEC_CTRL_CLK					230
+#define GCC_SEC_CTRL_SENSE_CLK					231
+#define GCC_SNOC_BUS_TIMEOUT0_AHB_CLK				232
+#define GCC_SNOC_BUS_TIMEOUT2_AHB_CLK				233
+#define GCC_SPDM_BIMC_CY_CLK					234
+#define GCC_SPDM_CFG_AHB_CLK					235
+#define GCC_SPDM_DEBUG_CY_CLK					236
+#define GCC_SPDM_FF_CLK						237
+#define GCC_SPDM_MSTR_AHB_CLK					238
+#define GCC_SPDM_PNOC_CY_CLK					239
+#define GCC_SPDM_RPM_CY_CLK					240
+#define GCC_SPDM_SNOC_CY_CLK					241
+#define GCC_SPMI_AHB_CLK					242
+#define GCC_SPMI_CNOC_AHB_CLK					243
+#define GCC_SPMI_SER_CLK					244
+#define GCC_SNOC_CNOC_AHB_CLK					245
+#define GCC_SNOC_PNOC_AHB_CLK					246
+#define GCC_SYS_NOC_AT_CLK					247
+#define GCC_SYS_NOC_AXI_CLK					248
+#define GCC_SYS_NOC_KPSS_AHB_CLK				249
+#define GCC_SYS_NOC_QDSS_STM_AXI_CLK				250
+#define GCC_SYS_NOC_USB3_AXI_CLK				251
+#define GCC_TCSR_AHB_CLK					252
+#define GCC_TLMM_AHB_CLK					253
+#define GCC_TLMM_CLK						254
+#define GCC_TSIF_AHB_CLK					255
+#define GCC_TSIF_INACTIVITY_TIMERS_CLK				256
+#define GCC_TSIF_REF_CLK					257
+#define GCC_USB2A_PHY_SLEEP_CLK					258
+#define GCC_USB2B_PHY_SLEEP_CLK					259
+#define GCC_USB30_MASTER_CLK					260
+#define GCC_USB30_MOCK_UTMI_CLK					261
+#define GCC_USB30_SLEEP_CLK					262
+#define GCC_USB_HS_AHB_CLK					263
+#define GCC_USB_HS_INACTIVITY_TIMERS_CLK			264
+#define GCC_USB_HS_SYSTEM_CLK					265
+#define GCC_USB_HSIC_AHB_CLK					266
+#define GCC_USB_HSIC_CLK					267
+#define GCC_USB_HSIC_IO_CAL_CLK					268
+#define GCC_USB_HSIC_IO_CAL_SLEEP_CLK				269
+#define GCC_USB_HSIC_SYSTEM_CLK					270
+#define GCC_WCSS_GPLL1_CLK_SRC					271
+#define GCC_MMSS_GPLL0_CLK_SRC					272
+#define GCC_LPASS_GPLL0_CLK_SRC					273
+#define GCC_WCSS_GPLL1_CLK_SRC_SLEEP_ENA			274
+#define GCC_MMSS_GPLL0_CLK_SRC_SLEEP_ENA			275
+#define GCC_LPASS_GPLL0_CLK_SRC_SLEEP_ENA			276
+#define GCC_IMEM_AXI_CLK_SLEEP_ENA				277
+#define GCC_SYS_NOC_KPSS_AHB_CLK_SLEEP_ENA			278
+#define GCC_BIMC_KPSS_AXI_CLK_SLEEP_ENA				279
+#define GCC_KPSS_AHB_CLK_SLEEP_ENA				280
+#define GCC_KPSS_AXI_CLK_SLEEP_ENA				281
+#define GCC_MPM_AHB_CLK_SLEEP_ENA				282
+#define GCC_OCMEM_SYS_NOC_AXI_CLK_SLEEP_ENA			283
+#define GCC_BLSP1_AHB_CLK_SLEEP_ENA				284
+#define GCC_BLSP1_SLEEP_CLK_SLEEP_ENA				285
+#define GCC_BLSP2_AHB_CLK_SLEEP_ENA				286
+#define GCC_BLSP2_SLEEP_CLK_SLEEP_ENA				287
+#define GCC_PRNG_AHB_CLK_SLEEP_ENA				288
+#define GCC_BAM_DMA_AHB_CLK_SLEEP_ENA				289
+#define GCC_BAM_DMA_INACTIVITY_TIMERS_CLK_SLEEP_ENA		290
+#define GCC_BOOT_ROM_AHB_CLK_SLEEP_ENA				291
+#define GCC_MSG_RAM_AHB_CLK_SLEEP_ENA				292
+#define GCC_TLMM_AHB_CLK_SLEEP_ENA				293
+#define GCC_TLMM_CLK_SLEEP_ENA					294
+#define GCC_SPMI_CNOC_AHB_CLK_SLEEP_ENA				295
+#define GCC_CE1_CLK_SLEEP_ENA					296
+#define GCC_CE1_AXI_CLK_SLEEP_ENA				297
+#define GCC_CE1_AHB_CLK_SLEEP_ENA				298
+#define GCC_CE2_CLK_SLEEP_ENA					299
+#define GCC_CE2_AXI_CLK_SLEEP_ENA				300
+#define GCC_CE2_AHB_CLK_SLEEP_ENA				301
+#define GPLL4							302
+#define GPLL4_VOTE						303
+#define GCC_SDCC1_CDCCAL_SLEEP_CLK				304
+#define GCC_SDCC1_CDCCAL_FF_CLK					305
+
+/* gdscs */
+#define USB_HS_HSIC_GDSC					0
+
+#endif
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/qcom,gcc-msm8994.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/qcom,gcc-msm8994.h
new file mode 100644
index 0000000000000000000000000000000000000000..df47da0860f74f33e4f114a28e2f7c9b2142c8d4
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/qcom,gcc-msm8994.h
@@ -0,0 +1,138 @@
+/*
+ * Copyright (c) 2016, The Linux Foundation. All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+
+#ifndef _DT_BINDINGS_CLK_MSM_GCC_8994_H
+#define _DT_BINDINGS_CLK_MSM_GCC_8994_H
+
+#define GPLL0_EARLY				0
+#define GPLL0					1
+#define GPLL4_EARLY				2
+#define GPLL4					3
+#define UFS_AXI_CLK_SRC				4
+#define USB30_MASTER_CLK_SRC			5
+#define BLSP1_QUP1_I2C_APPS_CLK_SRC		6
+#define BLSP1_QUP1_SPI_APPS_CLK_SRC		7
+#define BLSP1_QUP2_I2C_APPS_CLK_SRC		8
+#define BLSP1_QUP2_SPI_APPS_CLK_SRC		9
+#define BLSP1_QUP3_I2C_APPS_CLK_SRC		10
+#define BLSP1_QUP3_SPI_APPS_CLK_SRC		11
+#define BLSP1_QUP4_I2C_APPS_CLK_SRC		12
+#define BLSP1_QUP4_SPI_APPS_CLK_SRC		13
+#define BLSP1_QUP5_I2C_APPS_CLK_SRC		14
+#define BLSP1_QUP5_SPI_APPS_CLK_SRC		15
+#define BLSP1_QUP6_I2C_APPS_CLK_SRC		16
+#define BLSP1_QUP6_SPI_APPS_CLK_SRC		17
+#define BLSP1_UART1_APPS_CLK_SRC		18
+#define BLSP1_UART2_APPS_CLK_SRC		19
+#define BLSP1_UART3_APPS_CLK_SRC		20
+#define BLSP1_UART4_APPS_CLK_SRC		21
+#define BLSP1_UART5_APPS_CLK_SRC		22
+#define BLSP1_UART6_APPS_CLK_SRC		23
+#define BLSP2_QUP1_I2C_APPS_CLK_SRC		24
+#define BLSP2_QUP1_SPI_APPS_CLK_SRC		25
+#define BLSP2_QUP2_I2C_APPS_CLK_SRC		26
+#define BLSP2_QUP2_SPI_APPS_CLK_SRC		27
+#define BLSP2_QUP3_I2C_APPS_CLK_SRC		28
+#define BLSP2_QUP3_SPI_APPS_CLK_SRC		29
+#define BLSP2_QUP4_I2C_APPS_CLK_SRC		30
+#define BLSP2_QUP4_SPI_APPS_CLK_SRC		31
+#define BLSP2_QUP5_I2C_APPS_CLK_SRC		32
+#define BLSP2_QUP5_SPI_APPS_CLK_SRC		33
+#define BLSP2_QUP6_I2C_APPS_CLK_SRC		34
+#define BLSP2_QUP6_SPI_APPS_CLK_SRC		35
+#define BLSP2_UART1_APPS_CLK_SRC		36
+#define BLSP2_UART2_APPS_CLK_SRC		37
+#define BLSP2_UART3_APPS_CLK_SRC		38
+#define BLSP2_UART4_APPS_CLK_SRC		39
+#define BLSP2_UART5_APPS_CLK_SRC		40
+#define BLSP2_UART6_APPS_CLK_SRC		41
+#define GP1_CLK_SRC				42
+#define GP2_CLK_SRC				43
+#define GP3_CLK_SRC				44
+#define PCIE_0_AUX_CLK_SRC			45
+#define PCIE_0_PIPE_CLK_SRC			46
+#define PCIE_1_AUX_CLK_SRC			47
+#define PCIE_1_PIPE_CLK_SRC			48
+#define PDM2_CLK_SRC				49
+#define SDCC1_APPS_CLK_SRC			50
+#define SDCC2_APPS_CLK_SRC			51
+#define SDCC3_APPS_CLK_SRC			52
+#define SDCC4_APPS_CLK_SRC			53
+#define TSIF_REF_CLK_SRC			54
+#define USB30_MOCK_UTMI_CLK_SRC			55
+#define USB3_PHY_AUX_CLK_SRC			56
+#define USB_HS_SYSTEM_CLK_SRC			57
+#define GCC_BLSP1_AHB_CLK			58
+#define GCC_BLSP1_QUP1_I2C_APPS_CLK		59
+#define GCC_BLSP1_QUP1_SPI_APPS_CLK		60
+#define GCC_BLSP1_QUP2_I2C_APPS_CLK		61
+#define GCC_BLSP1_QUP2_SPI_APPS_CLK		62
+#define GCC_BLSP1_QUP3_I2C_APPS_CLK		63
+#define GCC_BLSP1_QUP3_SPI_APPS_CLK		64
+#define GCC_BLSP1_QUP4_I2C_APPS_CLK		65
+#define GCC_BLSP1_QUP4_SPI_APPS_CLK		66
+#define GCC_BLSP1_QUP5_I2C_APPS_CLK		67
+#define GCC_BLSP1_QUP5_SPI_APPS_CLK		68
+#define GCC_BLSP1_QUP6_I2C_APPS_CLK		69
+#define GCC_BLSP1_QUP6_SPI_APPS_CLK		70
+#define GCC_BLSP1_UART1_APPS_CLK		71
+#define GCC_BLSP1_UART2_APPS_CLK		72
+#define GCC_BLSP1_UART3_APPS_CLK		73
+#define GCC_BLSP1_UART4_APPS_CLK		74
+#define GCC_BLSP1_UART5_APPS_CLK		75
+#define GCC_BLSP1_UART6_APPS_CLK		76
+#define GCC_BLSP2_AHB_CLK			77
+#define GCC_BLSP2_QUP1_I2C_APPS_CLK		78
+#define GCC_BLSP2_QUP1_SPI_APPS_CLK		79
+#define GCC_BLSP2_QUP2_I2C_APPS_CLK		80
+#define GCC_BLSP2_QUP2_SPI_APPS_CLK		81
+#define GCC_BLSP2_QUP3_I2C_APPS_CLK		82
+#define GCC_BLSP2_QUP3_SPI_APPS_CLK		83
+#define GCC_BLSP2_QUP4_I2C_APPS_CLK		84
+#define GCC_BLSP2_QUP4_SPI_APPS_CLK		85
+#define GCC_BLSP2_QUP5_I2C_APPS_CLK		86
+#define GCC_BLSP2_QUP5_SPI_APPS_CLK		87
+#define GCC_BLSP2_QUP6_I2C_APPS_CLK		88
+#define GCC_BLSP2_QUP6_SPI_APPS_CLK		89
+#define GCC_BLSP2_UART1_APPS_CLK		90
+#define GCC_BLSP2_UART2_APPS_CLK		91
+#define GCC_BLSP2_UART3_APPS_CLK		92
+#define GCC_BLSP2_UART4_APPS_CLK		93
+#define GCC_BLSP2_UART5_APPS_CLK		94
+#define GCC_BLSP2_UART6_APPS_CLK		95
+#define GCC_GP1_CLK				96
+#define GCC_GP2_CLK				97
+#define GCC_GP3_CLK				98
+#define GCC_PCIE_0_AUX_CLK			99
+#define GCC_PCIE_0_PIPE_CLK			100
+#define GCC_PCIE_1_AUX_CLK			101
+#define GCC_PCIE_1_PIPE_CLK			102
+#define GCC_PDM2_CLK				103
+#define GCC_SDCC1_APPS_CLK			104
+#define GCC_SDCC2_APPS_CLK			105
+#define GCC_SDCC3_APPS_CLK			106
+#define GCC_SDCC4_APPS_CLK			107
+#define GCC_SYS_NOC_UFS_AXI_CLK			108
+#define GCC_SYS_NOC_USB3_AXI_CLK		109
+#define GCC_TSIF_REF_CLK			110
+#define GCC_UFS_AXI_CLK				111
+#define GCC_UFS_RX_CFG_CLK			112
+#define GCC_UFS_TX_CFG_CLK			113
+#define GCC_USB30_MASTER_CLK			114
+#define GCC_USB30_MOCK_UTMI_CLK			115
+#define GCC_USB3_PHY_AUX_CLK			116
+#define GCC_USB_HS_SYSTEM_CLK			117
+#define GCC_SDCC1_AHB_CLK			118
+
+#endif
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/qcom,gcc-msm8996.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/qcom,gcc-msm8996.h
new file mode 100644
index 0000000000000000000000000000000000000000..75b07cf5eed0f9a2941f0367af601b77c0bd1599
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/qcom,gcc-msm8996.h
@@ -0,0 +1,358 @@
+/*
+ * Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_CLK_MSM_GCC_8996_H
+#define _DT_BINDINGS_CLK_MSM_GCC_8996_H
+
+#define GPLL0_EARLY						0
+#define GPLL0							1
+#define GPLL1_EARLY						2
+#define GPLL1							3
+#define GPLL2_EARLY						4
+#define GPLL2							5
+#define GPLL3_EARLY						6
+#define GPLL3							7
+#define GPLL4_EARLY						8
+#define GPLL4							9
+#define SYSTEM_NOC_CLK_SRC					10
+#define CONFIG_NOC_CLK_SRC					11
+#define PERIPH_NOC_CLK_SRC					12
+#define MMSS_BIMC_GFX_CLK_SRC					13
+#define USB30_MASTER_CLK_SRC					14
+#define USB30_MOCK_UTMI_CLK_SRC					15
+#define USB3_PHY_AUX_CLK_SRC					16
+#define USB20_MASTER_CLK_SRC					17
+#define USB20_MOCK_UTMI_CLK_SRC					18
+#define SDCC1_APPS_CLK_SRC					19
+#define SDCC1_ICE_CORE_CLK_SRC					20
+#define SDCC2_APPS_CLK_SRC					21
+#define SDCC3_APPS_CLK_SRC					22
+#define SDCC4_APPS_CLK_SRC					23
+#define BLSP1_QUP1_SPI_APPS_CLK_SRC				24
+#define BLSP1_QUP1_I2C_APPS_CLK_SRC				25
+#define BLSP1_UART1_APPS_CLK_SRC				26
+#define BLSP1_QUP2_SPI_APPS_CLK_SRC				27
+#define BLSP1_QUP2_I2C_APPS_CLK_SRC				28
+#define BLSP1_UART2_APPS_CLK_SRC				29
+#define BLSP1_QUP3_SPI_APPS_CLK_SRC				30
+#define BLSP1_QUP3_I2C_APPS_CLK_SRC				31
+#define BLSP1_UART3_APPS_CLK_SRC				32
+#define BLSP1_QUP4_SPI_APPS_CLK_SRC				33
+#define BLSP1_QUP4_I2C_APPS_CLK_SRC				34
+#define BLSP1_UART4_APPS_CLK_SRC				35
+#define BLSP1_QUP5_SPI_APPS_CLK_SRC				36
+#define BLSP1_QUP5_I2C_APPS_CLK_SRC				37
+#define BLSP1_UART5_APPS_CLK_SRC				38
+#define BLSP1_QUP6_SPI_APPS_CLK_SRC				39
+#define BLSP1_QUP6_I2C_APPS_CLK_SRC				40
+#define BLSP1_UART6_APPS_CLK_SRC				41
+#define BLSP2_QUP1_SPI_APPS_CLK_SRC				42
+#define BLSP2_QUP1_I2C_APPS_CLK_SRC				43
+#define BLSP2_UART1_APPS_CLK_SRC				44
+#define BLSP2_QUP2_SPI_APPS_CLK_SRC				45
+#define BLSP2_QUP2_I2C_APPS_CLK_SRC				46
+#define BLSP2_UART2_APPS_CLK_SRC				47
+#define BLSP2_QUP3_SPI_APPS_CLK_SRC				48
+#define BLSP2_QUP3_I2C_APPS_CLK_SRC				49
+#define BLSP2_UART3_APPS_CLK_SRC				50
+#define BLSP2_QUP4_SPI_APPS_CLK_SRC				51
+#define BLSP2_QUP4_I2C_APPS_CLK_SRC				52
+#define BLSP2_UART4_APPS_CLK_SRC				53
+#define BLSP2_QUP5_SPI_APPS_CLK_SRC				54
+#define BLSP2_QUP5_I2C_APPS_CLK_SRC				55
+#define BLSP2_UART5_APPS_CLK_SRC				56
+#define BLSP2_QUP6_SPI_APPS_CLK_SRC				57
+#define BLSP2_QUP6_I2C_APPS_CLK_SRC				58
+#define BLSP2_UART6_APPS_CLK_SRC				59
+#define PDM2_CLK_SRC						60
+#define TSIF_REF_CLK_SRC					61
+#define CE1_CLK_SRC						62
+#define GCC_SLEEP_CLK_SRC					63
+#define BIMC_CLK_SRC						64
+#define HMSS_AHB_CLK_SRC					65
+#define BIMC_HMSS_AXI_CLK_SRC					66
+#define HMSS_RBCPR_CLK_SRC					67
+#define HMSS_GPLL0_CLK_SRC					68
+#define GP1_CLK_SRC						69
+#define GP2_CLK_SRC						70
+#define GP3_CLK_SRC						71
+#define PCIE_AUX_CLK_SRC					72
+#define UFS_AXI_CLK_SRC						73
+#define UFS_ICE_CORE_CLK_SRC					74
+#define QSPI_SER_CLK_SRC					75
+#define GCC_SYS_NOC_AXI_CLK					76
+#define GCC_SYS_NOC_HMSS_AHB_CLK				77
+#define GCC_SNOC_CNOC_AHB_CLK					78
+#define GCC_SNOC_PNOC_AHB_CLK					79
+#define GCC_SYS_NOC_AT_CLK					80
+#define GCC_SYS_NOC_USB3_AXI_CLK				81
+#define GCC_SYS_NOC_UFS_AXI_CLK					82
+#define GCC_CFG_NOC_AHB_CLK					83
+#define GCC_PERIPH_NOC_AHB_CLK					84
+#define GCC_PERIPH_NOC_USB20_AHB_CLK				85
+#define GCC_TIC_CLK						86
+#define GCC_IMEM_AXI_CLK					87
+#define GCC_MMSS_SYS_NOC_AXI_CLK				88
+#define GCC_MMSS_NOC_CFG_AHB_CLK				89
+#define GCC_MMSS_BIMC_GFX_CLK					90
+#define GCC_USB30_MASTER_CLK					91
+#define GCC_USB30_SLEEP_CLK					92
+#define GCC_USB30_MOCK_UTMI_CLK					93
+#define GCC_USB3_PHY_AUX_CLK					94
+#define GCC_USB3_PHY_PIPE_CLK					95
+#define GCC_USB20_MASTER_CLK					96
+#define GCC_USB20_SLEEP_CLK					97
+#define GCC_USB20_MOCK_UTMI_CLK					98
+#define GCC_USB_PHY_CFG_AHB2PHY_CLK				99
+#define GCC_SDCC1_APPS_CLK					100
+#define GCC_SDCC1_AHB_CLK					101
+#define GCC_SDCC1_ICE_CORE_CLK					102
+#define GCC_SDCC2_APPS_CLK					103
+#define GCC_SDCC2_AHB_CLK					104
+#define GCC_SDCC3_APPS_CLK					105
+#define GCC_SDCC3_AHB_CLK					106
+#define GCC_SDCC4_APPS_CLK					107
+#define GCC_SDCC4_AHB_CLK					108
+#define GCC_BLSP1_AHB_CLK					109
+#define GCC_BLSP1_SLEEP_CLK					110
+#define GCC_BLSP1_QUP1_SPI_APPS_CLK				111
+#define GCC_BLSP1_QUP1_I2C_APPS_CLK				112
+#define GCC_BLSP1_UART1_APPS_CLK				113
+#define GCC_BLSP1_QUP2_SPI_APPS_CLK				114
+#define GCC_BLSP1_QUP2_I2C_APPS_CLK				115
+#define GCC_BLSP1_UART2_APPS_CLK				116
+#define GCC_BLSP1_QUP3_SPI_APPS_CLK				117
+#define GCC_BLSP1_QUP3_I2C_APPS_CLK				118
+#define GCC_BLSP1_UART3_APPS_CLK				119
+#define GCC_BLSP1_QUP4_SPI_APPS_CLK				120
+#define GCC_BLSP1_QUP4_I2C_APPS_CLK				121
+#define GCC_BLSP1_UART4_APPS_CLK				122
+#define GCC_BLSP1_QUP5_SPI_APPS_CLK				123
+#define GCC_BLSP1_QUP5_I2C_APPS_CLK				124
+#define GCC_BLSP1_UART5_APPS_CLK				125
+#define GCC_BLSP1_QUP6_SPI_APPS_CLK				126
+#define GCC_BLSP1_QUP6_I2C_APPS_CLK				127
+#define GCC_BLSP1_UART6_APPS_CLK				128
+#define GCC_BLSP2_AHB_CLK					129
+#define GCC_BLSP2_SLEEP_CLK					130
+#define GCC_BLSP2_QUP1_SPI_APPS_CLK				131
+#define GCC_BLSP2_QUP1_I2C_APPS_CLK				132
+#define GCC_BLSP2_UART1_APPS_CLK				133
+#define GCC_BLSP2_QUP2_SPI_APPS_CLK				134
+#define GCC_BLSP2_QUP2_I2C_APPS_CLK				135
+#define GCC_BLSP2_UART2_APPS_CLK				136
+#define GCC_BLSP2_QUP3_SPI_APPS_CLK				137
+#define GCC_BLSP2_QUP3_I2C_APPS_CLK				138
+#define GCC_BLSP2_UART3_APPS_CLK				139
+#define GCC_BLSP2_QUP4_SPI_APPS_CLK				140
+#define GCC_BLSP2_QUP4_I2C_APPS_CLK				141
+#define GCC_BLSP2_UART4_APPS_CLK				142
+#define GCC_BLSP2_QUP5_SPI_APPS_CLK				143
+#define GCC_BLSP2_QUP5_I2C_APPS_CLK				144
+#define GCC_BLSP2_UART5_APPS_CLK				145
+#define GCC_BLSP2_QUP6_SPI_APPS_CLK				146
+#define GCC_BLSP2_QUP6_I2C_APPS_CLK				147
+#define GCC_BLSP2_UART6_APPS_CLK				148
+#define GCC_PDM_AHB_CLK						149
+#define GCC_PDM_XO4_CLK						150
+#define GCC_PDM2_CLK						151
+#define GCC_PRNG_AHB_CLK					152
+#define GCC_TSIF_AHB_CLK					153
+#define GCC_TSIF_REF_CLK					154
+#define GCC_TSIF_INACTIVITY_TIMERS_CLK				155
+#define GCC_TCSR_AHB_CLK					156
+#define GCC_BOOT_ROM_AHB_CLK					157
+#define GCC_MSG_RAM_AHB_CLK					158
+#define GCC_TLMM_AHB_CLK					159
+#define GCC_TLMM_CLK						160
+#define GCC_MPM_AHB_CLK						161
+#define GCC_SPMI_SER_CLK					162
+#define GCC_SPMI_CNOC_AHB_CLK					163
+#define GCC_CE1_CLK						164
+#define GCC_CE1_AXI_CLK						165
+#define GCC_CE1_AHB_CLK						166
+#define GCC_BIMC_HMSS_AXI_CLK					167
+#define GCC_BIMC_GFX_CLK					168
+#define GCC_HMSS_AHB_CLK					169
+#define GCC_HMSS_SLV_AXI_CLK					170
+#define GCC_HMSS_MSTR_AXI_CLK					171
+#define GCC_HMSS_RBCPR_CLK					172
+#define GCC_GP1_CLK						173
+#define GCC_GP2_CLK						174
+#define GCC_GP3_CLK						175
+#define GCC_PCIE_0_SLV_AXI_CLK					176
+#define GCC_PCIE_0_MSTR_AXI_CLK					177
+#define GCC_PCIE_0_CFG_AHB_CLK					178
+#define GCC_PCIE_0_AUX_CLK					179
+#define GCC_PCIE_0_PIPE_CLK					180
+#define GCC_PCIE_1_SLV_AXI_CLK					181
+#define GCC_PCIE_1_MSTR_AXI_CLK					182
+#define GCC_PCIE_1_CFG_AHB_CLK					183
+#define GCC_PCIE_1_AUX_CLK					184
+#define GCC_PCIE_1_PIPE_CLK					185
+#define GCC_PCIE_2_SLV_AXI_CLK					186
+#define GCC_PCIE_2_MSTR_AXI_CLK					187
+#define GCC_PCIE_2_CFG_AHB_CLK					188
+#define GCC_PCIE_2_AUX_CLK					189
+#define GCC_PCIE_2_PIPE_CLK					190
+#define GCC_PCIE_PHY_CFG_AHB_CLK				191
+#define GCC_PCIE_PHY_AUX_CLK					192
+#define GCC_UFS_AXI_CLK						193
+#define GCC_UFS_AHB_CLK						194
+#define GCC_UFS_TX_CFG_CLK					195
+#define GCC_UFS_RX_CFG_CLK					196
+#define GCC_UFS_TX_SYMBOL_0_CLK					197
+#define GCC_UFS_RX_SYMBOL_0_CLK					198
+#define GCC_UFS_RX_SYMBOL_1_CLK					199
+#define GCC_UFS_UNIPRO_CORE_CLK					200
+#define GCC_UFS_ICE_CORE_CLK					201
+#define GCC_UFS_SYS_CLK_CORE_CLK				202
+#define GCC_UFS_TX_SYMBOL_CLK_CORE_CLK				203
+#define GCC_AGGRE0_SNOC_AXI_CLK					204
+#define GCC_AGGRE0_CNOC_AHB_CLK					205
+#define GCC_SMMU_AGGRE0_AXI_CLK					206
+#define GCC_SMMU_AGGRE0_AHB_CLK					207
+#define GCC_AGGRE1_PNOC_AHB_CLK					208
+#define GCC_AGGRE2_UFS_AXI_CLK					209
+#define GCC_AGGRE2_USB3_AXI_CLK					210
+#define GCC_QSPI_AHB_CLK					211
+#define GCC_QSPI_SER_CLK					212
+#define GCC_USB3_CLKREF_CLK					213
+#define GCC_HDMI_CLKREF_CLK					214
+#define GCC_UFS_CLKREF_CLK					215
+#define GCC_PCIE_CLKREF_CLK					216
+#define GCC_RX2_USB2_CLKREF_CLK					217
+#define GCC_RX1_USB2_CLKREF_CLK					218
+#define GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CLK			219
+#define GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK			220
+
+#define GCC_SYSTEM_NOC_BCR					0
+#define GCC_CONFIG_NOC_BCR					1
+#define GCC_PERIPH_NOC_BCR					2
+#define GCC_IMEM_BCR						3
+#define GCC_MMSS_BCR						4
+#define GCC_PIMEM_BCR						5
+#define GCC_QDSS_BCR						6
+#define GCC_USB_30_BCR						7
+#define GCC_USB_20_BCR						8
+#define GCC_QUSB2PHY_PRIM_BCR					9
+#define GCC_QUSB2PHY_SEC_BCR					10
+#define GCC_USB_PHY_CFG_AHB2PHY_BCR				11
+#define GCC_SDCC1_BCR						12
+#define GCC_SDCC2_BCR						13
+#define GCC_SDCC3_BCR						14
+#define GCC_SDCC4_BCR						15
+#define GCC_BLSP1_BCR						16
+#define GCC_BLSP1_QUP1_BCR					17
+#define GCC_BLSP1_UART1_BCR					18
+#define GCC_BLSP1_QUP2_BCR					19
+#define GCC_BLSP1_UART2_BCR					20
+#define GCC_BLSP1_QUP3_BCR					21
+#define GCC_BLSP1_UART3_BCR					22
+#define GCC_BLSP1_QUP4_BCR					23
+#define GCC_BLSP1_UART4_BCR					24
+#define GCC_BLSP1_QUP5_BCR					25
+#define GCC_BLSP1_UART5_BCR					26
+#define GCC_BLSP1_QUP6_BCR					27
+#define GCC_BLSP1_UART6_BCR					28
+#define GCC_BLSP2_BCR						29
+#define GCC_BLSP2_QUP1_BCR					30
+#define GCC_BLSP2_UART1_BCR					31
+#define GCC_BLSP2_QUP2_BCR					32
+#define GCC_BLSP2_UART2_BCR					33
+#define GCC_BLSP2_QUP3_BCR					34
+#define GCC_BLSP2_UART3_BCR					35
+#define GCC_BLSP2_QUP4_BCR					36
+#define GCC_BLSP2_UART4_BCR					37
+#define GCC_BLSP2_QUP5_BCR					38
+#define GCC_BLSP2_UART5_BCR					39
+#define GCC_BLSP2_QUP6_BCR					40
+#define GCC_BLSP2_UART6_BCR					41
+#define GCC_PDM_BCR						42
+#define GCC_PRNG_BCR						43
+#define GCC_TSIF_BCR						44
+#define GCC_TCSR_BCR						45
+#define GCC_BOOT_ROM_BCR					46
+#define GCC_MSG_RAM_BCR						47
+#define GCC_TLMM_BCR						48
+#define GCC_MPM_BCR						49
+#define GCC_SEC_CTRL_BCR					50
+#define GCC_SPMI_BCR						51
+#define GCC_SPDM_BCR						52
+#define GCC_CE1_BCR						53
+#define GCC_BIMC_BCR						54
+#define GCC_SNOC_BUS_TIMEOUT0_BCR				55
+#define GCC_SNOC_BUS_TIMEOUT2_BCR				56
+#define GCC_SNOC_BUS_TIMEOUT1_BCR				57
+#define GCC_SNOC_BUS_TIMEOUT3_BCR				58
+#define GCC_SNOC_BUS_TIMEOUT_EXTREF_BCR				59
+#define GCC_PNOC_BUS_TIMEOUT0_BCR				60
+#define GCC_PNOC_BUS_TIMEOUT1_BCR				61
+#define GCC_PNOC_BUS_TIMEOUT2_BCR				62
+#define GCC_PNOC_BUS_TIMEOUT3_BCR				63
+#define GCC_PNOC_BUS_TIMEOUT4_BCR				64
+#define GCC_CNOC_BUS_TIMEOUT0_BCR				65
+#define GCC_CNOC_BUS_TIMEOUT1_BCR				66
+#define GCC_CNOC_BUS_TIMEOUT2_BCR				67
+#define GCC_CNOC_BUS_TIMEOUT3_BCR				68
+#define GCC_CNOC_BUS_TIMEOUT4_BCR				69
+#define GCC_CNOC_BUS_TIMEOUT5_BCR				70
+#define GCC_CNOC_BUS_TIMEOUT6_BCR				71
+#define GCC_CNOC_BUS_TIMEOUT7_BCR				72
+#define GCC_CNOC_BUS_TIMEOUT8_BCR				73
+#define GCC_CNOC_BUS_TIMEOUT9_BCR				74
+#define GCC_CNOC_BUS_TIMEOUT_EXTREF_BCR				75
+#define GCC_APB2JTAG_BCR					76
+#define GCC_RBCPR_CX_BCR					77
+#define GCC_RBCPR_MX_BCR					78
+#define GCC_PCIE_0_BCR						79
+#define GCC_PCIE_0_PHY_BCR					80
+#define GCC_PCIE_1_BCR						81
+#define GCC_PCIE_1_PHY_BCR					82
+#define GCC_PCIE_2_BCR						83
+#define GCC_PCIE_2_PHY_BCR					84
+#define GCC_PCIE_PHY_BCR					85
+#define GCC_DCD_BCR						86
+#define GCC_OBT_ODT_BCR						87
+#define GCC_UFS_BCR						88
+#define GCC_SSC_BCR						89
+#define GCC_VS_BCR						90
+#define GCC_AGGRE0_NOC_BCR					91
+#define GCC_AGGRE1_NOC_BCR					92
+#define GCC_AGGRE2_NOC_BCR					93
+#define GCC_DCC_BCR						94
+#define GCC_IPA_BCR						95
+#define GCC_QSPI_BCR						96
+#define GCC_SKL_BCR						97
+#define GCC_MSMPU_BCR						98
+#define GCC_MSS_Q6_BCR						99
+#define GCC_QREFS_VBG_CAL_BCR					100
+#define GCC_PCIE_PHY_COM_BCR					101
+#define GCC_PCIE_PHY_COM_NOCSR_BCR				102
+#define GCC_USB3_PHY_BCR					103
+#define GCC_USB3PHY_PHY_BCR					104
+#define GCC_MSS_RESTART						105
+
+
+/* Indexes for GDSCs */
+#define AGGRE0_NOC_GDSC			0
+#define HLOS1_VOTE_AGGRE0_NOC_GDSC	1
+#define HLOS1_VOTE_LPASS_ADSP_GDSC	2
+#define HLOS1_VOTE_LPASS_CORE_GDSC	3
+#define USB30_GDSC			4
+#define PCIE0_GDSC			5
+#define PCIE1_GDSC			6
+#define PCIE2_GDSC			7
+#define UFS_GDSC			8
+
+#endif
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/qcom,gcc-msm8998.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/qcom,gcc-msm8998.h
new file mode 100644
index 0000000000000000000000000000000000000000..58a242e656b1146133c2c24ae7fe67f33093a74c
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/qcom,gcc-msm8998.h
@@ -0,0 +1,208 @@
+/*
+ * Copyright (c) 2016, The Linux Foundation. All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_CLK_MSM_GCC_COBALT_H
+#define _DT_BINDINGS_CLK_MSM_GCC_COBALT_H
+
+#define BLSP1_QUP1_I2C_APPS_CLK_SRC				0
+#define BLSP1_QUP1_SPI_APPS_CLK_SRC				1
+#define BLSP1_QUP2_I2C_APPS_CLK_SRC				2
+#define BLSP1_QUP2_SPI_APPS_CLK_SRC				3
+#define BLSP1_QUP3_I2C_APPS_CLK_SRC				4
+#define BLSP1_QUP3_SPI_APPS_CLK_SRC				5
+#define BLSP1_QUP4_I2C_APPS_CLK_SRC				6
+#define BLSP1_QUP4_SPI_APPS_CLK_SRC				7
+#define BLSP1_QUP5_I2C_APPS_CLK_SRC				8
+#define BLSP1_QUP5_SPI_APPS_CLK_SRC				9
+#define BLSP1_QUP6_I2C_APPS_CLK_SRC				10
+#define BLSP1_QUP6_SPI_APPS_CLK_SRC				11
+#define BLSP1_UART1_APPS_CLK_SRC				12
+#define BLSP1_UART2_APPS_CLK_SRC				13
+#define BLSP1_UART3_APPS_CLK_SRC				14
+#define BLSP2_QUP1_I2C_APPS_CLK_SRC				15
+#define BLSP2_QUP1_SPI_APPS_CLK_SRC				16
+#define BLSP2_QUP2_I2C_APPS_CLK_SRC				17
+#define BLSP2_QUP2_SPI_APPS_CLK_SRC				18
+#define BLSP2_QUP3_I2C_APPS_CLK_SRC				19
+#define BLSP2_QUP3_SPI_APPS_CLK_SRC				20
+#define BLSP2_QUP4_I2C_APPS_CLK_SRC				21
+#define BLSP2_QUP4_SPI_APPS_CLK_SRC				22
+#define BLSP2_QUP5_I2C_APPS_CLK_SRC				23
+#define BLSP2_QUP5_SPI_APPS_CLK_SRC				24
+#define BLSP2_QUP6_I2C_APPS_CLK_SRC				25
+#define BLSP2_QUP6_SPI_APPS_CLK_SRC				26
+#define BLSP2_UART1_APPS_CLK_SRC				27
+#define BLSP2_UART2_APPS_CLK_SRC				28
+#define BLSP2_UART3_APPS_CLK_SRC				29
+#define GCC_AGGRE1_NOC_XO_CLK					30
+#define GCC_AGGRE1_UFS_AXI_CLK					31
+#define GCC_AGGRE1_USB3_AXI_CLK					32
+#define GCC_APSS_QDSS_TSCTR_DIV2_CLK				33
+#define GCC_APSS_QDSS_TSCTR_DIV8_CLK				34
+#define GCC_BIMC_HMSS_AXI_CLK					35
+#define GCC_BIMC_MSS_Q6_AXI_CLK					36
+#define GCC_BLSP1_AHB_CLK					37
+#define GCC_BLSP1_QUP1_I2C_APPS_CLK				38
+#define GCC_BLSP1_QUP1_SPI_APPS_CLK				39
+#define GCC_BLSP1_QUP2_I2C_APPS_CLK				40
+#define GCC_BLSP1_QUP2_SPI_APPS_CLK				41
+#define GCC_BLSP1_QUP3_I2C_APPS_CLK				42
+#define GCC_BLSP1_QUP3_SPI_APPS_CLK				43
+#define GCC_BLSP1_QUP4_I2C_APPS_CLK				44
+#define GCC_BLSP1_QUP4_SPI_APPS_CLK				45
+#define GCC_BLSP1_QUP5_I2C_APPS_CLK				46
+#define GCC_BLSP1_QUP5_SPI_APPS_CLK				47
+#define GCC_BLSP1_QUP6_I2C_APPS_CLK				48
+#define GCC_BLSP1_QUP6_SPI_APPS_CLK				49
+#define GCC_BLSP1_SLEEP_CLK					50
+#define GCC_BLSP1_UART1_APPS_CLK				51
+#define GCC_BLSP1_UART2_APPS_CLK				52
+#define GCC_BLSP1_UART3_APPS_CLK				53
+#define GCC_BLSP2_AHB_CLK					54
+#define GCC_BLSP2_QUP1_I2C_APPS_CLK				55
+#define GCC_BLSP2_QUP1_SPI_APPS_CLK				56
+#define GCC_BLSP2_QUP2_I2C_APPS_CLK				57
+#define GCC_BLSP2_QUP2_SPI_APPS_CLK				58
+#define GCC_BLSP2_QUP3_I2C_APPS_CLK				59
+#define GCC_BLSP2_QUP3_SPI_APPS_CLK				60
+#define GCC_BLSP2_QUP4_I2C_APPS_CLK				61
+#define GCC_BLSP2_QUP4_SPI_APPS_CLK				62
+#define GCC_BLSP2_QUP5_I2C_APPS_CLK				63
+#define GCC_BLSP2_QUP5_SPI_APPS_CLK				64
+#define GCC_BLSP2_QUP6_I2C_APPS_CLK				65
+#define GCC_BLSP2_QUP6_SPI_APPS_CLK				66
+#define GCC_BLSP2_SLEEP_CLK					67
+#define GCC_BLSP2_UART1_APPS_CLK				68
+#define GCC_BLSP2_UART2_APPS_CLK				69
+#define GCC_BLSP2_UART3_APPS_CLK				70
+#define GCC_CFG_NOC_USB3_AXI_CLK				71
+#define GCC_GP1_CLK						72
+#define GCC_GP2_CLK						73
+#define GCC_GP3_CLK						74
+#define GCC_GPU_BIMC_GFX_CLK					75
+#define GCC_GPU_BIMC_GFX_SRC_CLK				76
+#define GCC_GPU_CFG_AHB_CLK					77
+#define GCC_GPU_SNOC_DVM_GFX_CLK				78
+#define GCC_HMSS_AHB_CLK					79
+#define GCC_HMSS_AT_CLK						80
+#define GCC_HMSS_DVM_BUS_CLK					81
+#define GCC_HMSS_RBCPR_CLK					82
+#define GCC_HMSS_TRIG_CLK					83
+#define GCC_LPASS_AT_CLK					84
+#define GCC_LPASS_TRIG_CLK					85
+#define GCC_MMSS_NOC_CFG_AHB_CLK				86
+#define GCC_MMSS_QM_AHB_CLK					87
+#define GCC_MMSS_QM_CORE_CLK					88
+#define GCC_MMSS_SYS_NOC_AXI_CLK				89
+#define GCC_MSS_AT_CLK						90
+#define GCC_PCIE_0_AUX_CLK					91
+#define GCC_PCIE_0_CFG_AHB_CLK					92
+#define GCC_PCIE_0_MSTR_AXI_CLK					93
+#define GCC_PCIE_0_PIPE_CLK					94
+#define GCC_PCIE_0_SLV_AXI_CLK					95
+#define GCC_PCIE_PHY_AUX_CLK					96
+#define GCC_PDM2_CLK						97
+#define GCC_PDM_AHB_CLK						98
+#define GCC_PDM_XO4_CLK						99
+#define GCC_PRNG_AHB_CLK					100
+#define GCC_SDCC2_AHB_CLK					101
+#define GCC_SDCC2_APPS_CLK					102
+#define GCC_SDCC4_AHB_CLK					103
+#define GCC_SDCC4_APPS_CLK					104
+#define GCC_TSIF_AHB_CLK					105
+#define GCC_TSIF_INACTIVITY_TIMERS_CLK				106
+#define GCC_TSIF_REF_CLK					107
+#define GCC_UFS_AHB_CLK						108
+#define GCC_UFS_AXI_CLK						109
+#define GCC_UFS_ICE_CORE_CLK					110
+#define GCC_UFS_PHY_AUX_CLK					111
+#define GCC_UFS_RX_SYMBOL_0_CLK					112
+#define GCC_UFS_RX_SYMBOL_1_CLK					113
+#define GCC_UFS_TX_SYMBOL_0_CLK					114
+#define GCC_UFS_UNIPRO_CORE_CLK					115
+#define GCC_USB30_MASTER_CLK					116
+#define GCC_USB30_MOCK_UTMI_CLK					117
+#define GCC_USB30_SLEEP_CLK					118
+#define GCC_USB3_PHY_AUX_CLK					119
+#define GCC_USB3_PHY_PIPE_CLK					120
+#define GCC_USB_PHY_CFG_AHB2PHY_CLK				121
+#define GP1_CLK_SRC						122
+#define GP2_CLK_SRC						123
+#define GP3_CLK_SRC						124
+#define GPLL0							125
+#define GPLL0_OUT_EVEN						126
+#define GPLL0_OUT_MAIN						127
+#define GPLL0_OUT_ODD						128
+#define GPLL0_OUT_TEST						129
+#define GPLL1							130
+#define GPLL1_OUT_EVEN						131
+#define GPLL1_OUT_MAIN						132
+#define GPLL1_OUT_ODD						133
+#define GPLL1_OUT_TEST						134
+#define GPLL2							135
+#define GPLL2_OUT_EVEN						136
+#define GPLL2_OUT_MAIN						137
+#define GPLL2_OUT_ODD						138
+#define GPLL2_OUT_TEST						139
+#define GPLL3							140
+#define GPLL3_OUT_EVEN						141
+#define GPLL3_OUT_MAIN						142
+#define GPLL3_OUT_ODD						143
+#define GPLL3_OUT_TEST						144
+#define GPLL4							145
+#define GPLL4_OUT_EVEN						146
+#define GPLL4_OUT_MAIN						147
+#define GPLL4_OUT_ODD						148
+#define GPLL4_OUT_TEST						149
+#define GPLL6							150
+#define GPLL6_OUT_EVEN						151
+#define GPLL6_OUT_MAIN						152
+#define GPLL6_OUT_ODD						153
+#define GPLL6_OUT_TEST						154
+#define HMSS_AHB_CLK_SRC					155
+#define HMSS_RBCPR_CLK_SRC					156
+#define PCIE_AUX_CLK_SRC					157
+#define PDM2_CLK_SRC						158
+#define SDCC2_APPS_CLK_SRC					159
+#define SDCC4_APPS_CLK_SRC					160
+#define TSIF_REF_CLK_SRC					161
+#define UFS_AXI_CLK_SRC						162
+#define USB30_MASTER_CLK_SRC					163
+#define USB30_MOCK_UTMI_CLK_SRC					164
+#define USB3_PHY_AUX_CLK_SRC					165
+
+#define PCIE_0_GDSC						0
+#define UFS_GDSC						1
+#define USB_30_GDSC						2
+
+#define GCC_BLSP1_QUP1_BCR					0
+#define GCC_BLSP1_QUP2_BCR					1
+#define GCC_BLSP1_QUP3_BCR					2
+#define GCC_BLSP1_QUP4_BCR					3
+#define GCC_BLSP1_QUP5_BCR					4
+#define GCC_BLSP1_QUP6_BCR					5
+#define GCC_BLSP2_QUP1_BCR					6
+#define GCC_BLSP2_QUP2_BCR					7
+#define GCC_BLSP2_QUP3_BCR					8
+#define GCC_BLSP2_QUP4_BCR					9
+#define GCC_BLSP2_QUP5_BCR					10
+#define GCC_BLSP2_QUP6_BCR					11
+#define GCC_PCIE_0_BCR						12
+#define GCC_PDM_BCR						13
+#define GCC_SDCC2_BCR						14
+#define GCC_SDCC4_BCR						15
+#define GCC_TSIF_BCR						16
+#define GCC_UFS_BCR						17
+#define GCC_USB_30_BCR						18
+
+#endif
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/qcom,gcc-sdm845.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/qcom,gcc-sdm845.h
new file mode 100644
index 0000000000000000000000000000000000000000..f96fc2dbf60e0dd74b03b1b8d48394e2fd957b52
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/qcom,gcc-sdm845.h
@@ -0,0 +1,241 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_CLK_SDM_GCC_SDM845_H
+#define _DT_BINDINGS_CLK_SDM_GCC_SDM845_H
+
+/* GCC clock registers */
+#define GCC_AGGRE_NOC_PCIE_TBU_CLK				0
+#define GCC_AGGRE_UFS_CARD_AXI_CLK				1
+#define GCC_AGGRE_UFS_PHY_AXI_CLK				2
+#define GCC_AGGRE_USB3_PRIM_AXI_CLK				3
+#define GCC_AGGRE_USB3_SEC_AXI_CLK				4
+#define GCC_BOOT_ROM_AHB_CLK					5
+#define GCC_CAMERA_AHB_CLK					6
+#define GCC_CAMERA_AXI_CLK					7
+#define GCC_CAMERA_XO_CLK					8
+#define GCC_CE1_AHB_CLK						9
+#define GCC_CE1_AXI_CLK						10
+#define GCC_CE1_CLK						11
+#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK				12
+#define GCC_CFG_NOC_USB3_SEC_AXI_CLK				13
+#define GCC_CPUSS_AHB_CLK					14
+#define GCC_CPUSS_AHB_CLK_SRC					15
+#define GCC_CPUSS_RBCPR_CLK					16
+#define GCC_CPUSS_RBCPR_CLK_SRC					17
+#define GCC_DDRSS_GPU_AXI_CLK					18
+#define GCC_DISP_AHB_CLK					19
+#define GCC_DISP_AXI_CLK					20
+#define GCC_DISP_GPLL0_CLK_SRC					21
+#define GCC_DISP_GPLL0_DIV_CLK_SRC				22
+#define GCC_DISP_XO_CLK						23
+#define GCC_GP1_CLK						24
+#define GCC_GP1_CLK_SRC						25
+#define GCC_GP2_CLK						26
+#define GCC_GP2_CLK_SRC						27
+#define GCC_GP3_CLK						28
+#define GCC_GP3_CLK_SRC						29
+#define GCC_GPU_CFG_AHB_CLK					30
+#define GCC_GPU_GPLL0_CLK_SRC					31
+#define GCC_GPU_GPLL0_DIV_CLK_SRC				32
+#define GCC_GPU_MEMNOC_GFX_CLK					33
+#define GCC_GPU_SNOC_DVM_GFX_CLK				34
+#define GCC_MSS_AXIS2_CLK					35
+#define GCC_MSS_CFG_AHB_CLK					36
+#define GCC_MSS_GPLL0_DIV_CLK_SRC				37
+#define GCC_MSS_MFAB_AXIS_CLK					38
+#define GCC_MSS_Q6_MEMNOC_AXI_CLK				39
+#define GCC_MSS_SNOC_AXI_CLK					40
+#define GCC_PCIE_0_AUX_CLK					41
+#define GCC_PCIE_0_AUX_CLK_SRC					42
+#define GCC_PCIE_0_CFG_AHB_CLK					43
+#define GCC_PCIE_0_CLKREF_CLK					44
+#define GCC_PCIE_0_MSTR_AXI_CLK					45
+#define GCC_PCIE_0_PIPE_CLK					46
+#define GCC_PCIE_0_SLV_AXI_CLK					47
+#define GCC_PCIE_0_SLV_Q2A_AXI_CLK				48
+#define GCC_PCIE_1_AUX_CLK					49
+#define GCC_PCIE_1_AUX_CLK_SRC					50
+#define GCC_PCIE_1_CFG_AHB_CLK					51
+#define GCC_PCIE_1_CLKREF_CLK					52
+#define GCC_PCIE_1_MSTR_AXI_CLK					53
+#define GCC_PCIE_1_PIPE_CLK					54
+#define GCC_PCIE_1_SLV_AXI_CLK					55
+#define GCC_PCIE_1_SLV_Q2A_AXI_CLK				56
+#define GCC_PCIE_PHY_AUX_CLK					57
+#define GCC_PCIE_PHY_REFGEN_CLK					58
+#define GCC_PCIE_PHY_REFGEN_CLK_SRC				59
+#define GCC_PDM2_CLK						60
+#define GCC_PDM2_CLK_SRC					61
+#define GCC_PDM_AHB_CLK						62
+#define GCC_PDM_XO4_CLK						63
+#define GCC_PRNG_AHB_CLK					64
+#define GCC_QMIP_CAMERA_AHB_CLK					65
+#define GCC_QMIP_DISP_AHB_CLK					66
+#define GCC_QMIP_VIDEO_AHB_CLK					67
+#define GCC_QUPV3_WRAP0_S0_CLK					68
+#define GCC_QUPV3_WRAP0_S0_CLK_SRC				69
+#define GCC_QUPV3_WRAP0_S1_CLK					70
+#define GCC_QUPV3_WRAP0_S1_CLK_SRC				71
+#define GCC_QUPV3_WRAP0_S2_CLK					72
+#define GCC_QUPV3_WRAP0_S2_CLK_SRC				73
+#define GCC_QUPV3_WRAP0_S3_CLK					74
+#define GCC_QUPV3_WRAP0_S3_CLK_SRC				75
+#define GCC_QUPV3_WRAP0_S4_CLK					76
+#define GCC_QUPV3_WRAP0_S4_CLK_SRC				77
+#define GCC_QUPV3_WRAP0_S5_CLK					78
+#define GCC_QUPV3_WRAP0_S5_CLK_SRC				79
+#define GCC_QUPV3_WRAP0_S6_CLK					80
+#define GCC_QUPV3_WRAP0_S6_CLK_SRC				81
+#define GCC_QUPV3_WRAP0_S7_CLK					82
+#define GCC_QUPV3_WRAP0_S7_CLK_SRC				83
+#define GCC_QUPV3_WRAP1_S0_CLK					84
+#define GCC_QUPV3_WRAP1_S0_CLK_SRC				85
+#define GCC_QUPV3_WRAP1_S1_CLK					86
+#define GCC_QUPV3_WRAP1_S1_CLK_SRC				87
+#define GCC_QUPV3_WRAP1_S2_CLK					88
+#define GCC_QUPV3_WRAP1_S2_CLK_SRC				89
+#define GCC_QUPV3_WRAP1_S3_CLK					90
+#define GCC_QUPV3_WRAP1_S3_CLK_SRC				91
+#define GCC_QUPV3_WRAP1_S4_CLK					92
+#define GCC_QUPV3_WRAP1_S4_CLK_SRC				93
+#define GCC_QUPV3_WRAP1_S5_CLK					94
+#define GCC_QUPV3_WRAP1_S5_CLK_SRC				95
+#define GCC_QUPV3_WRAP1_S6_CLK					96
+#define GCC_QUPV3_WRAP1_S6_CLK_SRC				97
+#define GCC_QUPV3_WRAP1_S7_CLK					98
+#define GCC_QUPV3_WRAP1_S7_CLK_SRC				99
+#define GCC_QUPV3_WRAP_0_M_AHB_CLK				100
+#define GCC_QUPV3_WRAP_0_S_AHB_CLK				101
+#define GCC_QUPV3_WRAP_1_M_AHB_CLK				102
+#define GCC_QUPV3_WRAP_1_S_AHB_CLK				103
+#define GCC_SDCC2_AHB_CLK					104
+#define GCC_SDCC2_APPS_CLK					105
+#define GCC_SDCC2_APPS_CLK_SRC					106
+#define GCC_SDCC4_AHB_CLK					107
+#define GCC_SDCC4_APPS_CLK					108
+#define GCC_SDCC4_APPS_CLK_SRC					109
+#define GCC_SYS_NOC_CPUSS_AHB_CLK				110
+#define GCC_TSIF_AHB_CLK					111
+#define GCC_TSIF_INACTIVITY_TIMERS_CLK				112
+#define GCC_TSIF_REF_CLK					113
+#define GCC_TSIF_REF_CLK_SRC					114
+#define GCC_UFS_CARD_AHB_CLK					115
+#define GCC_UFS_CARD_AXI_CLK					116
+#define GCC_UFS_CARD_AXI_CLK_SRC				117
+#define GCC_UFS_CARD_CLKREF_CLK					118
+#define GCC_UFS_CARD_ICE_CORE_CLK				119
+#define GCC_UFS_CARD_ICE_CORE_CLK_SRC				120
+#define GCC_UFS_CARD_PHY_AUX_CLK				121
+#define GCC_UFS_CARD_PHY_AUX_CLK_SRC				122
+#define GCC_UFS_CARD_RX_SYMBOL_0_CLK				123
+#define GCC_UFS_CARD_RX_SYMBOL_1_CLK				124
+#define GCC_UFS_CARD_TX_SYMBOL_0_CLK				125
+#define GCC_UFS_CARD_UNIPRO_CORE_CLK				126
+#define GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC			127
+#define GCC_UFS_MEM_CLKREF_CLK					128
+#define GCC_UFS_PHY_AHB_CLK					129
+#define GCC_UFS_PHY_AXI_CLK					130
+#define GCC_UFS_PHY_AXI_CLK_SRC					131
+#define GCC_UFS_PHY_ICE_CORE_CLK				132
+#define GCC_UFS_PHY_ICE_CORE_CLK_SRC				133
+#define GCC_UFS_PHY_PHY_AUX_CLK					134
+#define GCC_UFS_PHY_PHY_AUX_CLK_SRC				135
+#define GCC_UFS_PHY_RX_SYMBOL_0_CLK				136
+#define GCC_UFS_PHY_RX_SYMBOL_1_CLK				137
+#define GCC_UFS_PHY_TX_SYMBOL_0_CLK				138
+#define GCC_UFS_PHY_UNIPRO_CORE_CLK				139
+#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC				140
+#define GCC_USB30_PRIM_MASTER_CLK				141
+#define GCC_USB30_PRIM_MASTER_CLK_SRC				142
+#define GCC_USB30_PRIM_MOCK_UTMI_CLK				143
+#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC			144
+#define GCC_USB30_PRIM_SLEEP_CLK				145
+#define GCC_USB30_SEC_MASTER_CLK				146
+#define GCC_USB30_SEC_MASTER_CLK_SRC				147
+#define GCC_USB30_SEC_MOCK_UTMI_CLK				148
+#define GCC_USB30_SEC_MOCK_UTMI_CLK_SRC				149
+#define GCC_USB30_SEC_SLEEP_CLK					150
+#define GCC_USB3_PRIM_CLKREF_CLK				151
+#define GCC_USB3_PRIM_PHY_AUX_CLK				152
+#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC				153
+#define GCC_USB3_PRIM_PHY_COM_AUX_CLK				154
+#define GCC_USB3_PRIM_PHY_PIPE_CLK				155
+#define GCC_USB3_SEC_CLKREF_CLK					156
+#define GCC_USB3_SEC_PHY_AUX_CLK				157
+#define GCC_USB3_SEC_PHY_AUX_CLK_SRC				158
+#define GCC_USB3_SEC_PHY_PIPE_CLK				159
+#define GCC_USB3_SEC_PHY_COM_AUX_CLK				160
+#define GCC_USB_PHY_CFG_AHB2PHY_CLK				161
+#define GCC_VIDEO_AHB_CLK					162
+#define GCC_VIDEO_AXI_CLK					163
+#define GCC_VIDEO_XO_CLK					164
+#define GPLL0							165
+#define GPLL0_OUT_EVEN						166
+#define GPLL0_OUT_MAIN						167
+#define GCC_GPU_IREF_CLK					168
+#define GCC_SDCC1_AHB_CLK					169
+#define GCC_SDCC1_APPS_CLK					170
+#define GCC_SDCC1_ICE_CORE_CLK					171
+#define GCC_SDCC1_APPS_CLK_SRC					172
+#define GCC_SDCC1_ICE_CORE_CLK_SRC				173
+#define GCC_APC_VS_CLK						174
+#define GCC_GPU_VS_CLK						175
+#define GCC_MSS_VS_CLK						176
+#define GCC_VDDA_VS_CLK						177
+#define GCC_VDDCX_VS_CLK					178
+#define GCC_VDDMX_VS_CLK					179
+#define GCC_VS_CTRL_AHB_CLK					180
+#define GCC_VS_CTRL_CLK						181
+#define GCC_VS_CTRL_CLK_SRC					182
+#define GCC_VSENSOR_CLK_SRC					183
+#define GPLL4							184
+#define GCC_CPUSS_DVM_BUS_CLK					185
+#define GCC_CPUSS_GNOC_CLK					186
+
+/* GCC Resets */
+#define GCC_MMSS_BCR						0
+#define GCC_PCIE_0_BCR						1
+#define GCC_PCIE_1_BCR						2
+#define GCC_PCIE_PHY_BCR					3
+#define GCC_PDM_BCR						4
+#define GCC_PRNG_BCR						5
+#define GCC_QUPV3_WRAPPER_0_BCR					6
+#define GCC_QUPV3_WRAPPER_1_BCR					7
+#define GCC_QUSB2PHY_PRIM_BCR					8
+#define GCC_QUSB2PHY_SEC_BCR					9
+#define GCC_SDCC2_BCR						10
+#define GCC_SDCC4_BCR						11
+#define GCC_TSIF_BCR						12
+#define GCC_UFS_CARD_BCR					13
+#define GCC_UFS_PHY_BCR						14
+#define GCC_USB30_PRIM_BCR					15
+#define GCC_USB30_SEC_BCR					16
+#define GCC_USB3_PHY_PRIM_BCR					17
+#define GCC_USB3PHY_PHY_PRIM_BCR				18
+#define GCC_USB3_DP_PHY_PRIM_BCR				19
+#define GCC_USB3_PHY_SEC_BCR					20
+#define GCC_USB3PHY_PHY_SEC_BCR					21
+#define GCC_USB3_DP_PHY_SEC_BCR					22
+#define GCC_USB_PHY_CFG_AHB2PHY_BCR				23
+#define GCC_PCIE_0_PHY_BCR					24
+#define GCC_PCIE_1_PHY_BCR					25
+
+/* GCC GDSCRs */
+#define PCIE_0_GDSC						0
+#define PCIE_1_GDSC						1
+#define UFS_CARD_GDSC						2
+#define UFS_PHY_GDSC						3
+#define USB30_PRIM_GDSC						4
+#define USB30_SEC_GDSC						5
+#define HLOS1_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDSC			6
+#define HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDSC			7
+#define HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_GDSC			8
+#define HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_GDSC			9
+#define HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC			10
+#define HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC			11
+#define HLOS1_VOTE_MMNOC_MMU_TBU_SF_GDSC			12
+
+#endif
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/qcom,lcc-ipq806x.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/qcom,lcc-ipq806x.h
new file mode 100644
index 0000000000000000000000000000000000000000..4e944b85c56d4703d37f9a585d400a09888a5ce6
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/qcom,lcc-ipq806x.h
@@ -0,0 +1,30 @@
+/*
+ * Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_CLK_LCC_IPQ806X_H
+#define _DT_BINDINGS_CLK_LCC_IPQ806X_H
+
+#define PLL4				0
+#define MI2S_OSR_SRC			1
+#define MI2S_OSR_CLK			2
+#define MI2S_DIV_CLK			3
+#define MI2S_BIT_DIV_CLK		4
+#define MI2S_BIT_CLK			5
+#define PCM_SRC				6
+#define PCM_CLK_OUT			7
+#define PCM_CLK				8
+#define SPDIF_SRC			9
+#define SPDIF_CLK			10
+#define AHBIX_CLK			11
+
+#endif
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/qcom,lcc-mdm9615.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/qcom,lcc-mdm9615.h
new file mode 100644
index 0000000000000000000000000000000000000000..cac963a2fdcb4f4ec5696ee87f29c404fdf761fc
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/qcom,lcc-mdm9615.h
@@ -0,0 +1,52 @@
+/*
+ * Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ * Copyright (c) BayLibre, SAS.
+ * Author : Neil Armstrong <narmstrong@baylibre.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_CLK_LCC_MDM9615_H
+#define _DT_BINDINGS_CLK_LCC_MDM9615_H
+
+#define PLL4				0
+#define MI2S_OSR_SRC			1
+#define MI2S_OSR_CLK			2
+#define MI2S_DIV_CLK			3
+#define MI2S_BIT_DIV_CLK		4
+#define MI2S_BIT_CLK			5
+#define PCM_SRC				6
+#define PCM_CLK_OUT			7
+#define PCM_CLK				8
+#define SLIMBUS_SRC			9
+#define AUDIO_SLIMBUS_CLK		10
+#define SPS_SLIMBUS_CLK			11
+#define CODEC_I2S_MIC_OSR_SRC		12
+#define CODEC_I2S_MIC_OSR_CLK		13
+#define CODEC_I2S_MIC_DIV_CLK		14
+#define CODEC_I2S_MIC_BIT_DIV_CLK	15
+#define CODEC_I2S_MIC_BIT_CLK		16
+#define SPARE_I2S_MIC_OSR_SRC		17
+#define SPARE_I2S_MIC_OSR_CLK		18
+#define SPARE_I2S_MIC_DIV_CLK		19
+#define SPARE_I2S_MIC_BIT_DIV_CLK	20
+#define SPARE_I2S_MIC_BIT_CLK		21
+#define CODEC_I2S_SPKR_OSR_SRC		22
+#define CODEC_I2S_SPKR_OSR_CLK		23
+#define CODEC_I2S_SPKR_DIV_CLK		24
+#define CODEC_I2S_SPKR_BIT_DIV_CLK	25
+#define CODEC_I2S_SPKR_BIT_CLK		26
+#define SPARE_I2S_SPKR_OSR_SRC		27
+#define SPARE_I2S_SPKR_OSR_CLK		28
+#define SPARE_I2S_SPKR_DIV_CLK		29
+#define SPARE_I2S_SPKR_BIT_DIV_CLK	30
+#define SPARE_I2S_SPKR_BIT_CLK		31
+
+#endif
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/qcom,lcc-msm8960.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/qcom,lcc-msm8960.h
new file mode 100644
index 0000000000000000000000000000000000000000..4fb2aa64d9fe7e492addfe6da2fca7b1e61ad815
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/qcom,lcc-msm8960.h
@@ -0,0 +1,50 @@
+/*
+ * Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_CLK_LCC_MSM8960_H
+#define _DT_BINDINGS_CLK_LCC_MSM8960_H
+
+#define PLL4				0
+#define MI2S_OSR_SRC			1
+#define MI2S_OSR_CLK			2
+#define MI2S_DIV_CLK			3
+#define MI2S_BIT_DIV_CLK		4
+#define MI2S_BIT_CLK			5
+#define PCM_SRC				6
+#define PCM_CLK_OUT			7
+#define PCM_CLK				8
+#define SLIMBUS_SRC			9
+#define AUDIO_SLIMBUS_CLK		10
+#define SPS_SLIMBUS_CLK			11
+#define CODEC_I2S_MIC_OSR_SRC		12
+#define CODEC_I2S_MIC_OSR_CLK		13
+#define CODEC_I2S_MIC_DIV_CLK		14
+#define CODEC_I2S_MIC_BIT_DIV_CLK	15
+#define CODEC_I2S_MIC_BIT_CLK		16
+#define SPARE_I2S_MIC_OSR_SRC		17
+#define SPARE_I2S_MIC_OSR_CLK		18
+#define SPARE_I2S_MIC_DIV_CLK		19
+#define SPARE_I2S_MIC_BIT_DIV_CLK	20
+#define SPARE_I2S_MIC_BIT_CLK		21
+#define CODEC_I2S_SPKR_OSR_SRC		22
+#define CODEC_I2S_SPKR_OSR_CLK		23
+#define CODEC_I2S_SPKR_DIV_CLK		24
+#define CODEC_I2S_SPKR_BIT_DIV_CLK	25
+#define CODEC_I2S_SPKR_BIT_CLK		26
+#define SPARE_I2S_SPKR_OSR_SRC		27
+#define SPARE_I2S_SPKR_OSR_CLK		28
+#define SPARE_I2S_SPKR_DIV_CLK		29
+#define SPARE_I2S_SPKR_BIT_DIV_CLK	30
+#define SPARE_I2S_SPKR_BIT_CLK		31
+
+#endif
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/qcom,mmcc-apq8084.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/qcom,mmcc-apq8084.h
new file mode 100644
index 0000000000000000000000000000000000000000..03861e3f498ef480840f0d860be9d33535f0410a
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/qcom,mmcc-apq8084.h
@@ -0,0 +1,193 @@
+/*
+ * Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_CLK_APQ_MMCC_8084_H
+#define _DT_BINDINGS_CLK_APQ_MMCC_8084_H
+
+#define MMSS_AHB_CLK_SRC		0
+#define MMSS_AXI_CLK_SRC		1
+#define MMPLL0				2
+#define MMPLL0_VOTE			3
+#define MMPLL1				4
+#define MMPLL1_VOTE			5
+#define MMPLL2				6
+#define MMPLL3				7
+#define MMPLL4				8
+#define CSI0_CLK_SRC			9
+#define CSI1_CLK_SRC			10
+#define CSI2_CLK_SRC			11
+#define CSI3_CLK_SRC			12
+#define VCODEC0_CLK_SRC			13
+#define VFE0_CLK_SRC			14
+#define VFE1_CLK_SRC			15
+#define MDP_CLK_SRC			16
+#define PCLK0_CLK_SRC			17
+#define PCLK1_CLK_SRC			18
+#define OCMEMNOC_CLK_SRC		19
+#define GFX3D_CLK_SRC			20
+#define JPEG0_CLK_SRC			21
+#define JPEG1_CLK_SRC			22
+#define JPEG2_CLK_SRC			23
+#define EDPPIXEL_CLK_SRC		24
+#define EXTPCLK_CLK_SRC			25
+#define VP_CLK_SRC			26
+#define CCI_CLK_SRC			27
+#define CAMSS_GP0_CLK_SRC		28
+#define CAMSS_GP1_CLK_SRC		29
+#define MCLK0_CLK_SRC			30
+#define MCLK1_CLK_SRC			31
+#define MCLK2_CLK_SRC			32
+#define MCLK3_CLK_SRC			33
+#define CSI0PHYTIMER_CLK_SRC		34
+#define CSI1PHYTIMER_CLK_SRC		35
+#define CSI2PHYTIMER_CLK_SRC		36
+#define CPP_CLK_SRC			37
+#define BYTE0_CLK_SRC			38
+#define BYTE1_CLK_SRC			39
+#define EDPAUX_CLK_SRC			40
+#define EDPLINK_CLK_SRC			41
+#define ESC0_CLK_SRC			42
+#define ESC1_CLK_SRC			43
+#define HDMI_CLK_SRC			44
+#define VSYNC_CLK_SRC			45
+#define MMSS_RBCPR_CLK_SRC		46
+#define RBBMTIMER_CLK_SRC		47
+#define MAPLE_CLK_SRC			48
+#define VDP_CLK_SRC			49
+#define VPU_BUS_CLK_SRC			50
+#define MMSS_CXO_CLK			51
+#define MMSS_SLEEPCLK_CLK		52
+#define AVSYNC_AHB_CLK			53
+#define AVSYNC_EDPPIXEL_CLK		54
+#define AVSYNC_EXTPCLK_CLK		55
+#define AVSYNC_PCLK0_CLK		56
+#define AVSYNC_PCLK1_CLK		57
+#define AVSYNC_VP_CLK			58
+#define CAMSS_AHB_CLK			59
+#define CAMSS_CCI_CCI_AHB_CLK		60
+#define CAMSS_CCI_CCI_CLK		61
+#define CAMSS_CSI0_AHB_CLK		62
+#define CAMSS_CSI0_CLK			63
+#define CAMSS_CSI0PHY_CLK		64
+#define CAMSS_CSI0PIX_CLK		65
+#define CAMSS_CSI0RDI_CLK		66
+#define CAMSS_CSI1_AHB_CLK		67
+#define CAMSS_CSI1_CLK			68
+#define CAMSS_CSI1PHY_CLK		69
+#define CAMSS_CSI1PIX_CLK		70
+#define CAMSS_CSI1RDI_CLK		71
+#define CAMSS_CSI2_AHB_CLK		72
+#define CAMSS_CSI2_CLK			73
+#define CAMSS_CSI2PHY_CLK		74
+#define CAMSS_CSI2PIX_CLK		75
+#define CAMSS_CSI2RDI_CLK		76
+#define CAMSS_CSI3_AHB_CLK		77
+#define CAMSS_CSI3_CLK			78
+#define CAMSS_CSI3PHY_CLK		79
+#define CAMSS_CSI3PIX_CLK		80
+#define CAMSS_CSI3RDI_CLK		81
+#define CAMSS_CSI_VFE0_CLK		82
+#define CAMSS_CSI_VFE1_CLK		83
+#define CAMSS_GP0_CLK			84
+#define CAMSS_GP1_CLK			85
+#define CAMSS_ISPIF_AHB_CLK		86
+#define CAMSS_JPEG_JPEG0_CLK		87
+#define CAMSS_JPEG_JPEG1_CLK		88
+#define CAMSS_JPEG_JPEG2_CLK		89
+#define CAMSS_JPEG_JPEG_AHB_CLK		90
+#define CAMSS_JPEG_JPEG_AXI_CLK		91
+#define CAMSS_MCLK0_CLK			92
+#define CAMSS_MCLK1_CLK			93
+#define CAMSS_MCLK2_CLK			94
+#define CAMSS_MCLK3_CLK			95
+#define CAMSS_MICRO_AHB_CLK		96
+#define CAMSS_PHY0_CSI0PHYTIMER_CLK	97
+#define CAMSS_PHY1_CSI1PHYTIMER_CLK	98
+#define CAMSS_PHY2_CSI2PHYTIMER_CLK	99
+#define CAMSS_TOP_AHB_CLK		100
+#define CAMSS_VFE_CPP_AHB_CLK		101
+#define CAMSS_VFE_CPP_CLK		102
+#define CAMSS_VFE_VFE0_CLK		103
+#define CAMSS_VFE_VFE1_CLK		104
+#define CAMSS_VFE_VFE_AHB_CLK		105
+#define CAMSS_VFE_VFE_AXI_CLK		106
+#define MDSS_AHB_CLK			107
+#define MDSS_AXI_CLK			108
+#define MDSS_BYTE0_CLK			109
+#define MDSS_BYTE1_CLK			110
+#define MDSS_EDPAUX_CLK			111
+#define MDSS_EDPLINK_CLK		112
+#define MDSS_EDPPIXEL_CLK		113
+#define MDSS_ESC0_CLK			114
+#define MDSS_ESC1_CLK			115
+#define MDSS_EXTPCLK_CLK		116
+#define MDSS_HDMI_AHB_CLK		117
+#define MDSS_HDMI_CLK			118
+#define MDSS_MDP_CLK			119
+#define MDSS_MDP_LUT_CLK		120
+#define MDSS_PCLK0_CLK			121
+#define MDSS_PCLK1_CLK			122
+#define MDSS_VSYNC_CLK			123
+#define MMSS_RBCPR_AHB_CLK		124
+#define MMSS_RBCPR_CLK			125
+#define MMSS_SPDM_AHB_CLK		126
+#define MMSS_SPDM_AXI_CLK		127
+#define MMSS_SPDM_CSI0_CLK		128
+#define MMSS_SPDM_GFX3D_CLK		129
+#define MMSS_SPDM_JPEG0_CLK		130
+#define MMSS_SPDM_JPEG1_CLK		131
+#define MMSS_SPDM_JPEG2_CLK		132
+#define MMSS_SPDM_MDP_CLK		133
+#define MMSS_SPDM_PCLK0_CLK		134
+#define MMSS_SPDM_PCLK1_CLK		135
+#define MMSS_SPDM_VCODEC0_CLK		136
+#define MMSS_SPDM_VFE0_CLK		137
+#define MMSS_SPDM_VFE1_CLK		138
+#define MMSS_SPDM_RM_AXI_CLK		139
+#define MMSS_SPDM_RM_OCMEMNOC_CLK	140
+#define MMSS_MISC_AHB_CLK		141
+#define MMSS_MMSSNOC_AHB_CLK		142
+#define MMSS_MMSSNOC_BTO_AHB_CLK	143
+#define MMSS_MMSSNOC_AXI_CLK		144
+#define MMSS_S0_AXI_CLK			145
+#define OCMEMCX_AHB_CLK			146
+#define OCMEMCX_OCMEMNOC_CLK		147
+#define OXILI_OCMEMGX_CLK		148
+#define OXILI_GFX3D_CLK			149
+#define OXILI_RBBMTIMER_CLK		150
+#define OXILICX_AHB_CLK			151
+#define VENUS0_AHB_CLK			152
+#define VENUS0_AXI_CLK			153
+#define VENUS0_CORE0_VCODEC_CLK		154
+#define VENUS0_CORE1_VCODEC_CLK		155
+#define VENUS0_OCMEMNOC_CLK		156
+#define VENUS0_VCODEC0_CLK		157
+#define VPU_AHB_CLK			158
+#define VPU_AXI_CLK			159
+#define VPU_BUS_CLK			160
+#define VPU_CXO_CLK			161
+#define VPU_MAPLE_CLK			162
+#define VPU_SLEEP_CLK			163
+#define VPU_VDP_CLK			164
+
+/* GDSCs */
+#define VENUS0_GDSC			0
+#define VENUS0_CORE0_GDSC		1
+#define VENUS0_CORE1_GDSC		2
+#define MDSS_GDSC			3
+#define CAMSS_JPEG_GDSC			4
+#define CAMSS_VFE_GDSC			5
+#define OXILI_GDSC			6
+#define OXILICX_GDSC			7
+
+#endif
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/qcom,mmcc-msm8960.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/qcom,mmcc-msm8960.h
new file mode 100644
index 0000000000000000000000000000000000000000..85041b28f97fd9ae8dbe8c20501a98e13ede82d6
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/qcom,mmcc-msm8960.h
@@ -0,0 +1,145 @@
+/*
+ * Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_CLK_MSM_MMCC_8960_H
+#define _DT_BINDINGS_CLK_MSM_MMCC_8960_H
+
+#define MMSS_AHB_SRC					0
+#define FAB_AHB_CLK					1
+#define APU_AHB_CLK					2
+#define TV_ENC_AHB_CLK					3
+#define AMP_AHB_CLK					4
+#define DSI2_S_AHB_CLK					5
+#define JPEGD_AHB_CLK					6
+#define GFX2D0_AHB_CLK					7
+#define DSI_S_AHB_CLK					8
+#define DSI2_M_AHB_CLK					9
+#define VPE_AHB_CLK					10
+#define SMMU_AHB_CLK					11
+#define HDMI_M_AHB_CLK					12
+#define VFE_AHB_CLK					13
+#define ROT_AHB_CLK					14
+#define VCODEC_AHB_CLK					15
+#define MDP_AHB_CLK					16
+#define DSI_M_AHB_CLK					17
+#define CSI_AHB_CLK					18
+#define MMSS_IMEM_AHB_CLK				19
+#define IJPEG_AHB_CLK					20
+#define HDMI_S_AHB_CLK					21
+#define GFX3D_AHB_CLK					22
+#define GFX2D1_AHB_CLK					23
+#define MMSS_FPB_CLK					24
+#define MMSS_AXI_SRC					25
+#define MMSS_FAB_CORE					26
+#define FAB_MSP_AXI_CLK					27
+#define JPEGD_AXI_CLK					28
+#define GMEM_AXI_CLK					29
+#define MDP_AXI_CLK					30
+#define MMSS_IMEM_AXI_CLK				31
+#define IJPEG_AXI_CLK					32
+#define GFX3D_AXI_CLK					33
+#define VCODEC_AXI_CLK					34
+#define VFE_AXI_CLK					35
+#define VPE_AXI_CLK					36
+#define ROT_AXI_CLK					37
+#define VCODEC_AXI_A_CLK				38
+#define VCODEC_AXI_B_CLK				39
+#define MM_AXI_S3_FCLK					40
+#define MM_AXI_S2_FCLK					41
+#define MM_AXI_S1_FCLK					42
+#define MM_AXI_S0_FCLK					43
+#define MM_AXI_S2_CLK					44
+#define MM_AXI_S1_CLK					45
+#define MM_AXI_S0_CLK					46
+#define CSI0_SRC					47
+#define CSI0_CLK					48
+#define CSI0_PHY_CLK					49
+#define CSI1_SRC					50
+#define CSI1_CLK					51
+#define CSI1_PHY_CLK					52
+#define CSI2_SRC					53
+#define CSI2_CLK					54
+#define CSI2_PHY_CLK					55
+#define DSI_SRC						56
+#define DSI_CLK						57
+#define CSI_PIX_CLK					58
+#define CSI_RDI_CLK					59
+#define MDP_VSYNC_CLK					60
+#define HDMI_DIV_CLK					61
+#define HDMI_APP_CLK					62
+#define CSI_PIX1_CLK					63
+#define CSI_RDI2_CLK					64
+#define CSI_RDI1_CLK					65
+#define GFX2D0_SRC					66
+#define GFX2D0_CLK					67
+#define GFX2D1_SRC					68
+#define GFX2D1_CLK					69
+#define GFX3D_SRC					70
+#define GFX3D_CLK					71
+#define IJPEG_SRC					72
+#define IJPEG_CLK					73
+#define JPEGD_SRC					74
+#define JPEGD_CLK					75
+#define MDP_SRC						76
+#define MDP_CLK						77
+#define MDP_LUT_CLK					78
+#define DSI2_PIXEL_SRC					79
+#define DSI2_PIXEL_CLK					80
+#define DSI2_SRC					81
+#define DSI2_CLK					82
+#define DSI1_BYTE_SRC					83
+#define DSI1_BYTE_CLK					84
+#define DSI2_BYTE_SRC					85
+#define DSI2_BYTE_CLK					86
+#define DSI1_ESC_SRC					87
+#define DSI1_ESC_CLK					88
+#define DSI2_ESC_SRC					89
+#define DSI2_ESC_CLK					90
+#define ROT_SRC						91
+#define ROT_CLK						92
+#define TV_ENC_CLK					93
+#define TV_DAC_CLK					94
+#define HDMI_TV_CLK					95
+#define MDP_TV_CLK					96
+#define TV_SRC						97
+#define VCODEC_SRC					98
+#define VCODEC_CLK					99
+#define VFE_SRC						100
+#define VFE_CLK						101
+#define VFE_CSI_CLK					102
+#define VPE_SRC						103
+#define VPE_CLK						104
+#define DSI_PIXEL_SRC					105
+#define DSI_PIXEL_CLK					106
+#define CAMCLK0_SRC					107
+#define CAMCLK0_CLK					108
+#define CAMCLK1_SRC					109
+#define CAMCLK1_CLK					110
+#define CAMCLK2_SRC					111
+#define CAMCLK2_CLK					112
+#define CSIPHYTIMER_SRC					113
+#define CSIPHY2_TIMER_CLK				114
+#define CSIPHY1_TIMER_CLK				115
+#define CSIPHY0_TIMER_CLK				116
+#define PLL1						117
+#define PLL2						118
+#define RGB_TV_CLK					119
+#define NPL_TV_CLK					120
+#define VCAP_AHB_CLK					121
+#define VCAP_AXI_CLK					122
+#define VCAP_SRC					123
+#define VCAP_CLK					124
+#define VCAP_NPL_CLK					125
+#define PLL15						126
+
+#endif
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/qcom,mmcc-msm8974.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/qcom,mmcc-msm8974.h
new file mode 100644
index 0000000000000000000000000000000000000000..28651e54c9aeeb8a1b41ad025e69aeb4cc04a4c1
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/qcom,mmcc-msm8974.h
@@ -0,0 +1,169 @@
+/*
+ * Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_CLK_MSM_MMCC_8974_H
+#define _DT_BINDINGS_CLK_MSM_MMCC_8974_H
+
+#define MMSS_AHB_CLK_SRC				0
+#define MMSS_AXI_CLK_SRC				1
+#define MMPLL0						2
+#define MMPLL0_VOTE					3
+#define MMPLL1						4
+#define MMPLL1_VOTE					5
+#define MMPLL2						6
+#define MMPLL3						7
+#define CSI0_CLK_SRC					8
+#define CSI1_CLK_SRC					9
+#define CSI2_CLK_SRC					10
+#define CSI3_CLK_SRC					11
+#define VFE0_CLK_SRC					12
+#define VFE1_CLK_SRC					13
+#define MDP_CLK_SRC					14
+#define GFX3D_CLK_SRC					15
+#define JPEG0_CLK_SRC					16
+#define JPEG1_CLK_SRC					17
+#define JPEG2_CLK_SRC					18
+#define PCLK0_CLK_SRC					19
+#define PCLK1_CLK_SRC					20
+#define VCODEC0_CLK_SRC					21
+#define CCI_CLK_SRC					22
+#define CAMSS_GP0_CLK_SRC				23
+#define CAMSS_GP1_CLK_SRC				24
+#define MCLK0_CLK_SRC					25
+#define MCLK1_CLK_SRC					26
+#define MCLK2_CLK_SRC					27
+#define MCLK3_CLK_SRC					28
+#define CSI0PHYTIMER_CLK_SRC				29
+#define CSI1PHYTIMER_CLK_SRC				30
+#define CSI2PHYTIMER_CLK_SRC				31
+#define CPP_CLK_SRC					32
+#define BYTE0_CLK_SRC					33
+#define BYTE1_CLK_SRC					34
+#define EDPAUX_CLK_SRC					35
+#define EDPLINK_CLK_SRC					36
+#define EDPPIXEL_CLK_SRC				37
+#define ESC0_CLK_SRC					38
+#define ESC1_CLK_SRC					39
+#define EXTPCLK_CLK_SRC					40
+#define HDMI_CLK_SRC					41
+#define VSYNC_CLK_SRC					42
+#define MMSS_RBCPR_CLK_SRC				43
+#define CAMSS_CCI_CCI_AHB_CLK				44
+#define CAMSS_CCI_CCI_CLK				45
+#define CAMSS_CSI0_AHB_CLK				46
+#define CAMSS_CSI0_CLK					47
+#define CAMSS_CSI0PHY_CLK				48
+#define CAMSS_CSI0PIX_CLK				49
+#define CAMSS_CSI0RDI_CLK				50
+#define CAMSS_CSI1_AHB_CLK				51
+#define CAMSS_CSI1_CLK					52
+#define CAMSS_CSI1PHY_CLK				53
+#define CAMSS_CSI1PIX_CLK				54
+#define CAMSS_CSI1RDI_CLK				55
+#define CAMSS_CSI2_AHB_CLK				56
+#define CAMSS_CSI2_CLK					57
+#define CAMSS_CSI2PHY_CLK				58
+#define CAMSS_CSI2PIX_CLK				59
+#define CAMSS_CSI2RDI_CLK				60
+#define CAMSS_CSI3_AHB_CLK				61
+#define CAMSS_CSI3_CLK					62
+#define CAMSS_CSI3PHY_CLK				63
+#define CAMSS_CSI3PIX_CLK				64
+#define CAMSS_CSI3RDI_CLK				65
+#define CAMSS_CSI_VFE0_CLK				66
+#define CAMSS_CSI_VFE1_CLK				67
+#define CAMSS_GP0_CLK					68
+#define CAMSS_GP1_CLK					69
+#define CAMSS_ISPIF_AHB_CLK				70
+#define CAMSS_JPEG_JPEG0_CLK				71
+#define CAMSS_JPEG_JPEG1_CLK				72
+#define CAMSS_JPEG_JPEG2_CLK				73
+#define CAMSS_JPEG_JPEG_AHB_CLK				74
+#define CAMSS_JPEG_JPEG_AXI_CLK				75
+#define CAMSS_JPEG_JPEG_OCMEMNOC_CLK			76
+#define CAMSS_MCLK0_CLK					77
+#define CAMSS_MCLK1_CLK					78
+#define CAMSS_MCLK2_CLK					79
+#define CAMSS_MCLK3_CLK					80
+#define CAMSS_MICRO_AHB_CLK				81
+#define CAMSS_PHY0_CSI0PHYTIMER_CLK			82
+#define CAMSS_PHY1_CSI1PHYTIMER_CLK			83
+#define CAMSS_PHY2_CSI2PHYTIMER_CLK			84
+#define CAMSS_TOP_AHB_CLK				85
+#define CAMSS_VFE_CPP_AHB_CLK				86
+#define CAMSS_VFE_CPP_CLK				87
+#define CAMSS_VFE_VFE0_CLK				88
+#define CAMSS_VFE_VFE1_CLK				89
+#define CAMSS_VFE_VFE_AHB_CLK				90
+#define CAMSS_VFE_VFE_AXI_CLK				91
+#define CAMSS_VFE_VFE_OCMEMNOC_CLK			92
+#define MDSS_AHB_CLK					93
+#define MDSS_AXI_CLK					94
+#define MDSS_BYTE0_CLK					95
+#define MDSS_BYTE1_CLK					96
+#define MDSS_EDPAUX_CLK					97
+#define MDSS_EDPLINK_CLK				98
+#define MDSS_EDPPIXEL_CLK				99
+#define MDSS_ESC0_CLK					100
+#define MDSS_ESC1_CLK					101
+#define MDSS_EXTPCLK_CLK				102
+#define MDSS_HDMI_AHB_CLK				103
+#define MDSS_HDMI_CLK					104
+#define MDSS_MDP_CLK					105
+#define MDSS_MDP_LUT_CLK				106
+#define MDSS_PCLK0_CLK					107
+#define MDSS_PCLK1_CLK					108
+#define MDSS_VSYNC_CLK					109
+#define MMSS_MISC_AHB_CLK				110
+#define MMSS_MMSSNOC_AHB_CLK				111
+#define MMSS_MMSSNOC_BTO_AHB_CLK			112
+#define MMSS_MMSSNOC_AXI_CLK				113
+#define MMSS_S0_AXI_CLK					114
+#define OCMEMCX_AHB_CLK					115
+#define OCMEMCX_OCMEMNOC_CLK				116
+#define OXILI_OCMEMGX_CLK				117
+#define OCMEMNOC_CLK					118
+#define OXILI_GFX3D_CLK					119
+#define OXILICX_AHB_CLK					120
+#define OXILICX_AXI_CLK					121
+#define VENUS0_AHB_CLK					122
+#define VENUS0_AXI_CLK					123
+#define VENUS0_OCMEMNOC_CLK				124
+#define VENUS0_VCODEC0_CLK				125
+#define OCMEMNOC_CLK_SRC				126
+#define SPDM_JPEG0					127
+#define SPDM_JPEG1					128
+#define SPDM_MDP					129
+#define SPDM_AXI					130
+#define SPDM_VCODEC0					131
+#define SPDM_VFE0					132
+#define SPDM_VFE1					133
+#define SPDM_JPEG2					134
+#define SPDM_PCLK1					135
+#define SPDM_GFX3D					136
+#define SPDM_AHB					137
+#define SPDM_PCLK0					138
+#define SPDM_OCMEMNOC					139
+#define SPDM_CSI0					140
+#define SPDM_RM_AXI					141
+#define SPDM_RM_OCMEMNOC				142
+
+/* gdscs */
+#define VENUS0_GDSC					0
+#define MDSS_GDSC					1
+#define CAMSS_JPEG_GDSC					2
+#define CAMSS_VFE_GDSC					3
+#define OXILI_GDSC					4
+#define OXILICX_GDSC					5
+
+#endif
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/qcom,mmcc-msm8996.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/qcom,mmcc-msm8996.h
new file mode 100644
index 0000000000000000000000000000000000000000..5abc445ad8152d7bc847cba177f1a85e633ffdbd
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/qcom,mmcc-msm8996.h
@@ -0,0 +1,303 @@
+/*
+ * Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_CLK_MSM_MMCC_8996_H
+#define _DT_BINDINGS_CLK_MSM_MMCC_8996_H
+
+#define MMPLL0_EARLY					0
+#define MMPLL0_PLL					1
+#define MMPLL1_EARLY					2
+#define MMPLL1_PLL					3
+#define MMPLL2_EARLY					4
+#define MMPLL2_PLL					5
+#define MMPLL3_EARLY					6
+#define MMPLL3_PLL					7
+#define MMPLL4_EARLY					8
+#define MMPLL4_PLL					9
+#define MMPLL5_EARLY					10
+#define MMPLL5_PLL					11
+#define MMPLL8_EARLY					12
+#define MMPLL8_PLL					13
+#define MMPLL9_EARLY					14
+#define MMPLL9_PLL					15
+#define AHB_CLK_SRC					16
+#define AXI_CLK_SRC					17
+#define MAXI_CLK_SRC					18
+#define DSA_CORE_CLK_SRC				19
+#define GFX3D_CLK_SRC					20
+#define RBBMTIMER_CLK_SRC				21
+#define ISENSE_CLK_SRC					22
+#define RBCPR_CLK_SRC					23
+#define VIDEO_CORE_CLK_SRC				24
+#define VIDEO_SUBCORE0_CLK_SRC				25
+#define VIDEO_SUBCORE1_CLK_SRC				26
+#define PCLK0_CLK_SRC					27
+#define PCLK1_CLK_SRC					28
+#define MDP_CLK_SRC					29
+#define EXTPCLK_CLK_SRC					30
+#define VSYNC_CLK_SRC					31
+#define HDMI_CLK_SRC					32
+#define BYTE0_CLK_SRC					33
+#define BYTE1_CLK_SRC					34
+#define ESC0_CLK_SRC					35
+#define ESC1_CLK_SRC					36
+#define CAMSS_GP0_CLK_SRC				37
+#define CAMSS_GP1_CLK_SRC				38
+#define MCLK0_CLK_SRC					39
+#define MCLK1_CLK_SRC					40
+#define MCLK2_CLK_SRC					41
+#define MCLK3_CLK_SRC					42
+#define CCI_CLK_SRC					43
+#define CSI0PHYTIMER_CLK_SRC				44
+#define CSI1PHYTIMER_CLK_SRC				45
+#define CSI2PHYTIMER_CLK_SRC				46
+#define CSIPHY0_3P_CLK_SRC				47
+#define CSIPHY1_3P_CLK_SRC				48
+#define CSIPHY2_3P_CLK_SRC				49
+#define JPEG0_CLK_SRC					50
+#define JPEG2_CLK_SRC					51
+#define JPEG_DMA_CLK_SRC				52
+#define VFE0_CLK_SRC					53
+#define VFE1_CLK_SRC					54
+#define CPP_CLK_SRC					55
+#define CSI0_CLK_SRC					56
+#define CSI1_CLK_SRC					57
+#define CSI2_CLK_SRC					58
+#define CSI3_CLK_SRC					59
+#define FD_CORE_CLK_SRC					60
+#define MMSS_CXO_CLK					61
+#define MMSS_SLEEPCLK_CLK				62
+#define MMSS_MMAGIC_AHB_CLK				63
+#define MMSS_MMAGIC_CFG_AHB_CLK				64
+#define MMSS_MISC_AHB_CLK				65
+#define MMSS_MISC_CXO_CLK				66
+#define MMSS_BTO_AHB_CLK				67
+#define MMSS_MMAGIC_AXI_CLK				68
+#define MMSS_S0_AXI_CLK					69
+#define MMSS_MMAGIC_MAXI_CLK				70
+#define DSA_CORE_CLK					71
+#define DSA_NOC_CFG_AHB_CLK				72
+#define MMAGIC_CAMSS_AXI_CLK				73
+#define MMAGIC_CAMSS_NOC_CFG_AHB_CLK			74
+#define THROTTLE_CAMSS_CXO_CLK				75
+#define THROTTLE_CAMSS_AHB_CLK				76
+#define THROTTLE_CAMSS_AXI_CLK				77
+#define SMMU_VFE_AHB_CLK				78
+#define SMMU_VFE_AXI_CLK				79
+#define SMMU_CPP_AHB_CLK				80
+#define SMMU_CPP_AXI_CLK				81
+#define SMMU_JPEG_AHB_CLK				82
+#define SMMU_JPEG_AXI_CLK				83
+#define MMAGIC_MDSS_AXI_CLK				84
+#define MMAGIC_MDSS_NOC_CFG_AHB_CLK			85
+#define THROTTLE_MDSS_CXO_CLK				86
+#define THROTTLE_MDSS_AHB_CLK				87
+#define THROTTLE_MDSS_AXI_CLK				88
+#define SMMU_ROT_AHB_CLK				89
+#define SMMU_ROT_AXI_CLK				90
+#define SMMU_MDP_AHB_CLK				91
+#define SMMU_MDP_AXI_CLK				92
+#define MMAGIC_VIDEO_AXI_CLK				93
+#define MMAGIC_VIDEO_NOC_CFG_AHB_CLK			94
+#define THROTTLE_VIDEO_CXO_CLK				95
+#define THROTTLE_VIDEO_AHB_CLK				96
+#define THROTTLE_VIDEO_AXI_CLK				97
+#define SMMU_VIDEO_AHB_CLK				98
+#define SMMU_VIDEO_AXI_CLK				99
+#define MMAGIC_BIMC_AXI_CLK				100
+#define MMAGIC_BIMC_NOC_CFG_AHB_CLK			101
+#define GPU_GX_GFX3D_CLK				102
+#define GPU_GX_RBBMTIMER_CLK				103
+#define GPU_AHB_CLK					104
+#define GPU_AON_ISENSE_CLK				105
+#define VMEM_MAXI_CLK					106
+#define VMEM_AHB_CLK					107
+#define MMSS_RBCPR_CLK					108
+#define MMSS_RBCPR_AHB_CLK				109
+#define VIDEO_CORE_CLK					110
+#define VIDEO_AXI_CLK					111
+#define VIDEO_MAXI_CLK					112
+#define VIDEO_AHB_CLK					113
+#define VIDEO_SUBCORE0_CLK				114
+#define VIDEO_SUBCORE1_CLK				115
+#define MDSS_AHB_CLK					116
+#define MDSS_HDMI_AHB_CLK				117
+#define MDSS_AXI_CLK					118
+#define MDSS_PCLK0_CLK					119
+#define MDSS_PCLK1_CLK					120
+#define MDSS_MDP_CLK					121
+#define MDSS_EXTPCLK_CLK				122
+#define MDSS_VSYNC_CLK					123
+#define MDSS_HDMI_CLK					124
+#define MDSS_BYTE0_CLK					125
+#define MDSS_BYTE1_CLK					126
+#define MDSS_ESC0_CLK					127
+#define MDSS_ESC1_CLK					128
+#define CAMSS_TOP_AHB_CLK				129
+#define CAMSS_AHB_CLK					130
+#define CAMSS_MICRO_AHB_CLK				131
+#define CAMSS_GP0_CLK					132
+#define CAMSS_GP1_CLK					133
+#define CAMSS_MCLK0_CLK					134
+#define CAMSS_MCLK1_CLK					135
+#define CAMSS_MCLK2_CLK					136
+#define CAMSS_MCLK3_CLK					137
+#define CAMSS_CCI_CLK					138
+#define CAMSS_CCI_AHB_CLK				139
+#define CAMSS_CSI0PHYTIMER_CLK				140
+#define CAMSS_CSI1PHYTIMER_CLK				141
+#define CAMSS_CSI2PHYTIMER_CLK				142
+#define CAMSS_CSIPHY0_3P_CLK				143
+#define CAMSS_CSIPHY1_3P_CLK				144
+#define CAMSS_CSIPHY2_3P_CLK				145
+#define CAMSS_JPEG0_CLK					146
+#define CAMSS_JPEG2_CLK					147
+#define CAMSS_JPEG_DMA_CLK				148
+#define CAMSS_JPEG_AHB_CLK				149
+#define CAMSS_JPEG_AXI_CLK				150
+#define CAMSS_VFE_AHB_CLK				151
+#define CAMSS_VFE_AXI_CLK				152
+#define CAMSS_VFE0_CLK					153
+#define CAMSS_VFE0_STREAM_CLK				154
+#define CAMSS_VFE0_AHB_CLK				155
+#define CAMSS_VFE1_CLK					156
+#define CAMSS_VFE1_STREAM_CLK				157
+#define CAMSS_VFE1_AHB_CLK				158
+#define CAMSS_CSI_VFE0_CLK				159
+#define CAMSS_CSI_VFE1_CLK				160
+#define CAMSS_CPP_VBIF_AHB_CLK				161
+#define CAMSS_CPP_AXI_CLK				162
+#define CAMSS_CPP_CLK					163
+#define CAMSS_CPP_AHB_CLK				164
+#define CAMSS_CSI0_CLK					165
+#define CAMSS_CSI0_AHB_CLK				166
+#define CAMSS_CSI0PHY_CLK				167
+#define CAMSS_CSI0RDI_CLK				168
+#define CAMSS_CSI0PIX_CLK				169
+#define CAMSS_CSI1_CLK					170
+#define CAMSS_CSI1_AHB_CLK				171
+#define CAMSS_CSI1PHY_CLK				172
+#define CAMSS_CSI1RDI_CLK				173
+#define CAMSS_CSI1PIX_CLK				174
+#define CAMSS_CSI2_CLK					175
+#define CAMSS_CSI2_AHB_CLK				176
+#define CAMSS_CSI2PHY_CLK				177
+#define CAMSS_CSI2RDI_CLK				178
+#define CAMSS_CSI2PIX_CLK				179
+#define CAMSS_CSI3_CLK					180
+#define CAMSS_CSI3_AHB_CLK				181
+#define CAMSS_CSI3PHY_CLK				182
+#define CAMSS_CSI3RDI_CLK				183
+#define CAMSS_CSI3PIX_CLK				184
+#define CAMSS_ISPIF_AHB_CLK				185
+#define FD_CORE_CLK					186
+#define FD_CORE_UAR_CLK					187
+#define FD_AHB_CLK					188
+#define MMSS_SPDM_CSI0_CLK				189
+#define MMSS_SPDM_JPEG_DMA_CLK				190
+#define MMSS_SPDM_CPP_CLK				191
+#define MMSS_SPDM_PCLK0_CLK				192
+#define MMSS_SPDM_AHB_CLK				193
+#define MMSS_SPDM_GFX3D_CLK				194
+#define MMSS_SPDM_PCLK1_CLK				195
+#define MMSS_SPDM_JPEG2_CLK				196
+#define MMSS_SPDM_DEBUG_CLK				197
+#define MMSS_SPDM_VFE1_CLK				198
+#define MMSS_SPDM_VFE0_CLK				199
+#define MMSS_SPDM_VIDEO_CORE_CLK			200
+#define MMSS_SPDM_AXI_CLK				201
+#define MMSS_SPDM_MDP_CLK				202
+#define MMSS_SPDM_JPEG0_CLK				203
+#define MMSS_SPDM_RM_AXI_CLK				204
+#define MMSS_SPDM_RM_MAXI_CLK				205
+
+#define MMAGICAHB_BCR					0
+#define MMAGIC_CFG_BCR					1
+#define MISC_BCR					2
+#define BTO_BCR						3
+#define MMAGICAXI_BCR					4
+#define MMAGICMAXI_BCR					5
+#define DSA_BCR						6
+#define MMAGIC_CAMSS_BCR				7
+#define THROTTLE_CAMSS_BCR				8
+#define SMMU_VFE_BCR					9
+#define SMMU_CPP_BCR					10
+#define SMMU_JPEG_BCR					11
+#define MMAGIC_MDSS_BCR					12
+#define THROTTLE_MDSS_BCR				13
+#define SMMU_ROT_BCR					14
+#define SMMU_MDP_BCR					15
+#define MMAGIC_VIDEO_BCR				16
+#define THROTTLE_VIDEO_BCR				17
+#define SMMU_VIDEO_BCR					18
+#define MMAGIC_BIMC_BCR					19
+#define GPU_GX_BCR					20
+#define GPU_BCR						21
+#define GPU_AON_BCR					22
+#define VMEM_BCR					23
+#define MMSS_RBCPR_BCR					24
+#define VIDEO_BCR					25
+#define MDSS_BCR					26
+#define CAMSS_TOP_BCR					27
+#define CAMSS_AHB_BCR					28
+#define CAMSS_MICRO_BCR					29
+#define CAMSS_CCI_BCR					30
+#define CAMSS_PHY0_BCR					31
+#define CAMSS_PHY1_BCR					32
+#define CAMSS_PHY2_BCR					33
+#define CAMSS_CSIPHY0_3P_BCR				34
+#define CAMSS_CSIPHY1_3P_BCR				35
+#define CAMSS_CSIPHY2_3P_BCR				36
+#define CAMSS_JPEG_BCR					37
+#define CAMSS_VFE_BCR					38
+#define CAMSS_VFE0_BCR					39
+#define CAMSS_VFE1_BCR					40
+#define CAMSS_CSI_VFE0_BCR				41
+#define CAMSS_CSI_VFE1_BCR				42
+#define CAMSS_CPP_TOP_BCR				43
+#define CAMSS_CPP_BCR					44
+#define CAMSS_CSI0_BCR					45
+#define CAMSS_CSI0RDI_BCR				46
+#define CAMSS_CSI0PIX_BCR				47
+#define CAMSS_CSI1_BCR					48
+#define CAMSS_CSI1RDI_BCR				49
+#define CAMSS_CSI1PIX_BCR				50
+#define CAMSS_CSI2_BCR					51
+#define CAMSS_CSI2RDI_BCR				52
+#define CAMSS_CSI2PIX_BCR				53
+#define CAMSS_CSI3_BCR					54
+#define CAMSS_CSI3RDI_BCR				55
+#define CAMSS_CSI3PIX_BCR				56
+#define CAMSS_ISPIF_BCR					57
+#define FD_BCR						58
+#define MMSS_SPDM_RM_BCR				59
+
+/* Indexes for GDSCs */
+#define MMAGIC_VIDEO_GDSC	0
+#define MMAGIC_MDSS_GDSC	1
+#define MMAGIC_CAMSS_GDSC	2
+#define GPU_GDSC		3
+#define VENUS_GDSC		4
+#define VENUS_CORE0_GDSC	5
+#define VENUS_CORE1_GDSC	6
+#define CAMSS_GDSC		7
+#define VFE0_GDSC		8
+#define VFE1_GDSC		9
+#define JPEG_GDSC		10
+#define CPP_GDSC		11
+#define FD_GDSC			12
+#define MDSS_GDSC		13
+#define GPU_GX_GDSC		14
+#define MMAGIC_BIMC_GDSC	15
+
+#endif
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/qcom,rpmcc.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/qcom,rpmcc.h
new file mode 100644
index 0000000000000000000000000000000000000000..c585b82b9c056d489f8f383d8da9cf40bfb6948f
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/qcom,rpmcc.h
@@ -0,0 +1,127 @@
+/*
+ * Copyright 2015 Linaro Limited
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_CLK_MSM_RPMCC_H
+#define _DT_BINDINGS_CLK_MSM_RPMCC_H
+
+/* RPM clocks */
+#define RPM_PXO_CLK				0
+#define RPM_PXO_A_CLK				1
+#define RPM_CXO_CLK				2
+#define RPM_CXO_A_CLK				3
+#define RPM_APPS_FABRIC_CLK			4
+#define RPM_APPS_FABRIC_A_CLK			5
+#define RPM_CFPB_CLK				6
+#define RPM_CFPB_A_CLK				7
+#define RPM_QDSS_CLK				8
+#define RPM_QDSS_A_CLK				9
+#define RPM_DAYTONA_FABRIC_CLK			10
+#define RPM_DAYTONA_FABRIC_A_CLK		11
+#define RPM_EBI1_CLK				12
+#define RPM_EBI1_A_CLK				13
+#define RPM_MM_FABRIC_CLK			14
+#define RPM_MM_FABRIC_A_CLK			15
+#define RPM_MMFPB_CLK				16
+#define RPM_MMFPB_A_CLK				17
+#define RPM_SYS_FABRIC_CLK			18
+#define RPM_SYS_FABRIC_A_CLK			19
+#define RPM_SFPB_CLK				20
+#define RPM_SFPB_A_CLK				21
+#define RPM_SMI_CLK				22
+#define RPM_SMI_A_CLK				23
+#define RPM_PLL4_CLK				24
+#define RPM_XO_D0				25
+#define RPM_XO_D1				26
+#define RPM_XO_A0				27
+#define RPM_XO_A1				28
+#define RPM_XO_A2				29
+
+/* SMD RPM clocks */
+#define RPM_SMD_XO_CLK_SRC				0
+#define RPM_SMD_XO_A_CLK_SRC			1
+#define RPM_SMD_PCNOC_CLK				2
+#define RPM_SMD_PCNOC_A_CLK				3
+#define RPM_SMD_SNOC_CLK				4
+#define RPM_SMD_SNOC_A_CLK				5
+#define RPM_SMD_BIMC_CLK				6
+#define RPM_SMD_BIMC_A_CLK				7
+#define RPM_SMD_QDSS_CLK				8
+#define RPM_SMD_QDSS_A_CLK				9
+#define RPM_SMD_BB_CLK1				10
+#define RPM_SMD_BB_CLK1_A				11
+#define RPM_SMD_BB_CLK2				12
+#define RPM_SMD_BB_CLK2_A				13
+#define RPM_SMD_RF_CLK1				14
+#define RPM_SMD_RF_CLK1_A				15
+#define RPM_SMD_RF_CLK2				16
+#define RPM_SMD_RF_CLK2_A				17
+#define RPM_SMD_BB_CLK1_PIN				18
+#define RPM_SMD_BB_CLK1_A_PIN			19
+#define RPM_SMD_BB_CLK2_PIN				20
+#define RPM_SMD_BB_CLK2_A_PIN			21
+#define RPM_SMD_RF_CLK1_PIN				22
+#define RPM_SMD_RF_CLK1_A_PIN			23
+#define RPM_SMD_RF_CLK2_PIN				24
+#define RPM_SMD_RF_CLK2_A_PIN			25
+#define RPM_SMD_PNOC_CLK			26
+#define RPM_SMD_PNOC_A_CLK			27
+#define RPM_SMD_CNOC_CLK			28
+#define RPM_SMD_CNOC_A_CLK			29
+#define RPM_SMD_MMSSNOC_AHB_CLK			30
+#define RPM_SMD_MMSSNOC_AHB_A_CLK		31
+#define RPM_SMD_GFX3D_CLK_SRC			32
+#define RPM_SMD_GFX3D_A_CLK_SRC			33
+#define RPM_SMD_OCMEMGX_CLK			34
+#define RPM_SMD_OCMEMGX_A_CLK			35
+#define RPM_SMD_CXO_D0				36
+#define RPM_SMD_CXO_D0_A			37
+#define RPM_SMD_CXO_D1				38
+#define RPM_SMD_CXO_D1_A			39
+#define RPM_SMD_CXO_A0				40
+#define RPM_SMD_CXO_A0_A			41
+#define RPM_SMD_CXO_A1				42
+#define RPM_SMD_CXO_A1_A			43
+#define RPM_SMD_CXO_A2				44
+#define RPM_SMD_CXO_A2_A			45
+#define RPM_SMD_DIV_CLK1			46
+#define RPM_SMD_DIV_A_CLK1			47
+#define RPM_SMD_DIV_CLK2			48
+#define RPM_SMD_DIV_A_CLK2			49
+#define RPM_SMD_DIFF_CLK			50
+#define RPM_SMD_DIFF_A_CLK			51
+#define RPM_SMD_CXO_D0_PIN			52
+#define RPM_SMD_CXO_D0_A_PIN			53
+#define RPM_SMD_CXO_D1_PIN			54
+#define RPM_SMD_CXO_D1_A_PIN			55
+#define RPM_SMD_CXO_A0_PIN			56
+#define RPM_SMD_CXO_A0_A_PIN			57
+#define RPM_SMD_CXO_A1_PIN			58
+#define RPM_SMD_CXO_A1_A_PIN			59
+#define RPM_SMD_CXO_A2_PIN			60
+#define RPM_SMD_CXO_A2_A_PIN			61
+#define RPM_SMD_AGGR1_NOC_CLK			62
+#define RPM_SMD_AGGR1_NOC_A_CLK			63
+#define RPM_SMD_AGGR2_NOC_CLK			64
+#define RPM_SMD_AGGR2_NOC_A_CLK			65
+#define RPM_SMD_MMAXI_CLK			66
+#define RPM_SMD_MMAXI_A_CLK			67
+#define RPM_SMD_IPA_CLK				68
+#define RPM_SMD_IPA_A_CLK			69
+#define RPM_SMD_CE1_CLK				70
+#define RPM_SMD_CE1_A_CLK			71
+#define RPM_SMD_DIV_CLK3			72
+#define RPM_SMD_DIV_A_CLK3			73
+#define RPM_SMD_LN_BB_CLK			74
+#define RPM_SMD_LN_BB_A_CLK			75
+
+#endif
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/qcom,rpmh.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/qcom,rpmh.h
new file mode 100644
index 0000000000000000000000000000000000000000..f48fbd6f2095272849f58e46e7e25a1c71750a6b
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/qcom,rpmh.h
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright (c) 2018, The Linux Foundation. All rights reserved. */
+
+
+#ifndef _DT_BINDINGS_CLK_MSM_RPMH_H
+#define _DT_BINDINGS_CLK_MSM_RPMH_H
+
+/* RPMh controlled clocks */
+#define RPMH_CXO_CLK				0
+#define RPMH_CXO_CLK_A				1
+#define RPMH_LN_BB_CLK2				2
+#define RPMH_LN_BB_CLK2_A			3
+#define RPMH_LN_BB_CLK3				4
+#define RPMH_LN_BB_CLK3_A			5
+#define RPMH_RF_CLK1				6
+#define RPMH_RF_CLK1_A				7
+#define RPMH_RF_CLK2				8
+#define RPMH_RF_CLK2_A				9
+#define RPMH_RF_CLK3				10
+#define RPMH_RF_CLK3_A				11
+
+#endif
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/qcom,videocc-sdm845.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/qcom,videocc-sdm845.h
new file mode 100644
index 0000000000000000000000000000000000000000..1b868165e8ceb35ea43aaefa373fb1b51d1edd19
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/qcom,videocc-sdm845.h
@@ -0,0 +1,35 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_CLK_SDM_VIDEO_CC_SDM845_H
+#define _DT_BINDINGS_CLK_SDM_VIDEO_CC_SDM845_H
+
+/* VIDEO_CC clock registers */
+#define VIDEO_CC_APB_CLK		0
+#define VIDEO_CC_AT_CLK			1
+#define VIDEO_CC_QDSS_TRIG_CLK		2
+#define VIDEO_CC_QDSS_TSCTR_DIV8_CLK	3
+#define VIDEO_CC_VCODEC0_AXI_CLK	4
+#define VIDEO_CC_VCODEC0_CORE_CLK	5
+#define VIDEO_CC_VCODEC1_AXI_CLK	6
+#define VIDEO_CC_VCODEC1_CORE_CLK	7
+#define VIDEO_CC_VENUS_AHB_CLK		8
+#define VIDEO_CC_VENUS_CLK_SRC		9
+#define VIDEO_CC_VENUS_CTL_AXI_CLK	10
+#define VIDEO_CC_VENUS_CTL_CORE_CLK	11
+#define VIDEO_PLL0			12
+
+/* VIDEO_CC Resets */
+#define VIDEO_CC_VENUS_BCR		0
+#define VIDEO_CC_VCODEC0_BCR		1
+#define VIDEO_CC_VCODEC1_BCR		2
+#define VIDEO_CC_INTERFACE_BCR		3
+
+/* VIDEO_CC GDSCRs */
+#define VENUS_GDSC			0
+#define VCODEC0_GDSC			1
+#define VCODEC1_GDSC			2
+
+#endif
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/r7s72100-clock.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/r7s72100-clock.h
new file mode 100644
index 0000000000000000000000000000000000000000..0dcb3e87d44c121ec55b8614cee46fae6b1417d7
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/r7s72100-clock.h
@@ -0,0 +1,115 @@
+/*
+ * Copyright (C) 2014 Renesas Solutions Corp.
+ * Copyright (C) 2014 Wolfram Sang, Sang Engineering <wsa@sang-engineering.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_R7S72100_H__
+#define __DT_BINDINGS_CLOCK_R7S72100_H__
+
+#define R7S72100_CLK_PLL	0
+#define R7S72100_CLK_I		1
+#define R7S72100_CLK_G		2
+
+/* MSTP2 */
+#define R7S72100_CLK_CORESIGHT	0
+
+/* MSTP3 */
+#define R7S72100_CLK_IEBUS	7
+#define R7S72100_CLK_IRDA	6
+#define R7S72100_CLK_LIN0	5
+#define R7S72100_CLK_LIN1	4
+#define R7S72100_CLK_MTU2	3
+#define R7S72100_CLK_CAN	2
+#define R7S72100_CLK_ADCPWR	1
+#define R7S72100_CLK_PWM	0
+
+/* MSTP4 */
+#define R7S72100_CLK_SCIF0	7
+#define R7S72100_CLK_SCIF1	6
+#define R7S72100_CLK_SCIF2	5
+#define R7S72100_CLK_SCIF3	4
+#define R7S72100_CLK_SCIF4	3
+#define R7S72100_CLK_SCIF5	2
+#define R7S72100_CLK_SCIF6	1
+#define R7S72100_CLK_SCIF7	0
+
+/* MSTP5 */
+#define R7S72100_CLK_SCI0	7
+#define R7S72100_CLK_SCI1	6
+#define R7S72100_CLK_SG0	5
+#define R7S72100_CLK_SG1	4
+#define R7S72100_CLK_SG2	3
+#define R7S72100_CLK_SG3	2
+#define R7S72100_CLK_OSTM0	1
+#define R7S72100_CLK_OSTM1	0
+
+/* MSTP6 */
+#define R7S72100_CLK_ADC	7
+#define R7S72100_CLK_CEU	6
+#define R7S72100_CLK_DOC0	5
+#define R7S72100_CLK_DOC1	4
+#define R7S72100_CLK_DRC0	3
+#define R7S72100_CLK_DRC1	2
+#define R7S72100_CLK_JCU	1
+#define R7S72100_CLK_RTC	0
+
+/* MSTP7 */
+#define R7S72100_CLK_VDEC0	7
+#define R7S72100_CLK_VDEC1	6
+#define R7S72100_CLK_ETHER	4
+#define R7S72100_CLK_NAND	3
+#define R7S72100_CLK_USB0	1
+#define R7S72100_CLK_USB1	0
+
+/* MSTP8 */
+#define R7S72100_CLK_IMR0	7
+#define R7S72100_CLK_IMR1	6
+#define R7S72100_CLK_IMRDISP	5
+#define R7S72100_CLK_MMCIF	4
+#define R7S72100_CLK_MLB	3
+#define R7S72100_CLK_ETHAVB	2
+#define R7S72100_CLK_SCUX	1
+
+/* MSTP9 */
+#define R7S72100_CLK_I2C0	7
+#define R7S72100_CLK_I2C1	6
+#define R7S72100_CLK_I2C2	5
+#define R7S72100_CLK_I2C3	4
+#define R7S72100_CLK_SPIBSC0	3
+#define R7S72100_CLK_SPIBSC1	2
+#define R7S72100_CLK_VDC50	1	/* and LVDS */
+#define R7S72100_CLK_VDC51	0
+
+/* MSTP10 */
+#define R7S72100_CLK_SPI0	7
+#define R7S72100_CLK_SPI1	6
+#define R7S72100_CLK_SPI2	5
+#define R7S72100_CLK_SPI3	4
+#define R7S72100_CLK_SPI4	3
+#define R7S72100_CLK_CDROM	2
+#define R7S72100_CLK_SPDIF	1
+#define R7S72100_CLK_RGPVG2	0
+
+/* MSTP11 */
+#define R7S72100_CLK_SSI0	5
+#define R7S72100_CLK_SSI1	4
+#define R7S72100_CLK_SSI2	3
+#define R7S72100_CLK_SSI3	2
+#define R7S72100_CLK_SSI4	1
+#define R7S72100_CLK_SSI5	0
+
+/* MSTP12 */
+#define R7S72100_CLK_SDHI00	3
+#define R7S72100_CLK_SDHI01	2
+#define R7S72100_CLK_SDHI10	1
+#define R7S72100_CLK_SDHI11	0
+
+/* MSTP13 */
+#define R7S72100_CLK_PIX1	2
+#define R7S72100_CLK_PIX0	1
+
+#endif /* __DT_BINDINGS_CLOCK_R7S72100_H__ */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/r8a73a4-clock.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/r8a73a4-clock.h
new file mode 100644
index 0000000000000000000000000000000000000000..4b36681572570c15874e7027b5d987dd61ecaa3d
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/r8a73a4-clock.h
@@ -0,0 +1,64 @@
+/*
+ * Copyright 2014 Ulrich Hecht
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_R8A73A4_H__
+#define __DT_BINDINGS_CLOCK_R8A73A4_H__
+
+/* CPG */
+#define R8A73A4_CLK_MAIN	0
+#define R8A73A4_CLK_PLL0	1
+#define R8A73A4_CLK_PLL1	2
+#define R8A73A4_CLK_PLL2	3
+#define R8A73A4_CLK_PLL2S	4
+#define R8A73A4_CLK_PLL2H	5
+#define R8A73A4_CLK_Z		6
+#define R8A73A4_CLK_Z2		7
+#define R8A73A4_CLK_I		8
+#define R8A73A4_CLK_M3		9
+#define R8A73A4_CLK_B		10
+#define R8A73A4_CLK_M1		11
+#define R8A73A4_CLK_M2		12
+#define R8A73A4_CLK_ZX		13
+#define R8A73A4_CLK_ZS		14
+#define R8A73A4_CLK_HP		15
+
+/* MSTP2 */
+#define R8A73A4_CLK_DMAC	18
+#define R8A73A4_CLK_SCIFB3	17
+#define R8A73A4_CLK_SCIFB2	16
+#define R8A73A4_CLK_SCIFB1	7
+#define R8A73A4_CLK_SCIFB0	6
+#define R8A73A4_CLK_SCIFA0	4
+#define R8A73A4_CLK_SCIFA1	3
+
+/* MSTP3 */
+#define R8A73A4_CLK_CMT1	29
+#define R8A73A4_CLK_IIC1	23
+#define R8A73A4_CLK_IIC0	18
+#define R8A73A4_CLK_IIC7	17
+#define R8A73A4_CLK_IIC6	16
+#define R8A73A4_CLK_MMCIF0	15
+#define R8A73A4_CLK_SDHI0	14
+#define R8A73A4_CLK_SDHI1	13
+#define R8A73A4_CLK_SDHI2	12
+#define R8A73A4_CLK_MMCIF1	5
+#define R8A73A4_CLK_IIC2	0
+
+/* MSTP4 */
+#define R8A73A4_CLK_IIC3	11
+#define R8A73A4_CLK_IIC4	10
+#define R8A73A4_CLK_IIC5	9
+#define R8A73A4_CLK_INTC_SYS	8
+#define R8A73A4_CLK_IRQC	7
+
+/* MSTP5 */
+#define R8A73A4_CLK_THERMAL	22
+#define R8A73A4_CLK_IIC8	15
+
+#endif /* __DT_BINDINGS_CLOCK_R8A73A4_H__ */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/r8a7740-clock.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/r8a7740-clock.h
new file mode 100644
index 0000000000000000000000000000000000000000..476135da0f238811889460a6ca524230fc51a368
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/r8a7740-clock.h
@@ -0,0 +1,78 @@
+/*
+ * Copyright 2014 Ulrich Hecht
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_R8A7740_H__
+#define __DT_BINDINGS_CLOCK_R8A7740_H__
+
+/* CPG */
+#define R8A7740_CLK_SYSTEM	0
+#define R8A7740_CLK_PLLC0	1
+#define R8A7740_CLK_PLLC1	2
+#define R8A7740_CLK_PLLC2	3
+#define R8A7740_CLK_R		4
+#define R8A7740_CLK_USB24S	5
+#define R8A7740_CLK_I		6
+#define R8A7740_CLK_ZG		7
+#define R8A7740_CLK_B		8
+#define R8A7740_CLK_M1		9
+#define R8A7740_CLK_HP		10
+#define R8A7740_CLK_HPP		11
+#define R8A7740_CLK_USBP	12
+#define R8A7740_CLK_S		13
+#define R8A7740_CLK_ZB		14
+#define R8A7740_CLK_M3		15
+#define R8A7740_CLK_CP		16
+
+/* MSTP1 */
+#define R8A7740_CLK_CEU21	28
+#define R8A7740_CLK_CEU20	27
+#define R8A7740_CLK_TMU0	25
+#define R8A7740_CLK_LCDC1	17
+#define R8A7740_CLK_IIC0	16
+#define R8A7740_CLK_TMU1	11
+#define R8A7740_CLK_LCDC0	0
+
+/* MSTP2 */
+#define R8A7740_CLK_SCIFA6	30
+#define R8A7740_CLK_INTCA	29
+#define R8A7740_CLK_SCIFA7	22
+#define R8A7740_CLK_DMAC1	18
+#define R8A7740_CLK_DMAC2	17
+#define R8A7740_CLK_DMAC3	16
+#define R8A7740_CLK_USBDMAC	14
+#define R8A7740_CLK_SCIFA5	7
+#define R8A7740_CLK_SCIFB	6
+#define R8A7740_CLK_SCIFA0	4
+#define R8A7740_CLK_SCIFA1	3
+#define R8A7740_CLK_SCIFA2	2
+#define R8A7740_CLK_SCIFA3	1
+#define R8A7740_CLK_SCIFA4	0
+
+/* MSTP3 */
+#define R8A7740_CLK_CMT1	29
+#define R8A7740_CLK_FSI		28
+#define R8A7740_CLK_IIC1	23
+#define R8A7740_CLK_USBF	20
+#define R8A7740_CLK_SDHI0	14
+#define R8A7740_CLK_SDHI1	13
+#define R8A7740_CLK_MMC		12
+#define R8A7740_CLK_GETHER	9
+#define R8A7740_CLK_TPU0	4
+
+/* MSTP4 */
+#define R8A7740_CLK_USBH	16
+#define R8A7740_CLK_SDHI2	15
+#define R8A7740_CLK_USBFUNC	7
+#define R8A7740_CLK_USBPHY	6
+
+/* SUBCK* */
+#define R8A7740_CLK_SUBCK	9
+#define R8A7740_CLK_SUBCK2	10
+
+#endif /* __DT_BINDINGS_CLOCK_R8A7740_H__ */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/r8a7743-cpg-mssr.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/r8a7743-cpg-mssr.h
new file mode 100644
index 0000000000000000000000000000000000000000..e1d1f3c6a99ea95c72bd3500cead514aef40d3f8
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/r8a7743-cpg-mssr.h
@@ -0,0 +1,43 @@
+/*
+ * Copyright (C) 2016 Cogent Embedded Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#ifndef __DT_BINDINGS_CLOCK_R8A7743_CPG_MSSR_H__
+#define __DT_BINDINGS_CLOCK_R8A7743_CPG_MSSR_H__
+
+#include <dt-bindings/clock/renesas-cpg-mssr.h>
+
+/* r8a7743 CPG Core Clocks */
+#define R8A7743_CLK_Z		0
+#define R8A7743_CLK_ZG		1
+#define R8A7743_CLK_ZTR		2
+#define R8A7743_CLK_ZTRD2	3
+#define R8A7743_CLK_ZT		4
+#define R8A7743_CLK_ZX		5
+#define R8A7743_CLK_ZS		6
+#define R8A7743_CLK_HP		7
+#define R8A7743_CLK_B		9
+#define R8A7743_CLK_LB		10
+#define R8A7743_CLK_P		11
+#define R8A7743_CLK_CL		12
+#define R8A7743_CLK_M2		13
+#define R8A7743_CLK_ZB3		15
+#define R8A7743_CLK_ZB3D2	16
+#define R8A7743_CLK_DDR		17
+#define R8A7743_CLK_SDH		18
+#define R8A7743_CLK_SD0		19
+#define R8A7743_CLK_SD2		20
+#define R8A7743_CLK_SD3		21
+#define R8A7743_CLK_MMC0	22
+#define R8A7743_CLK_MP		23
+#define R8A7743_CLK_QSPI	26
+#define R8A7743_CLK_CP		27
+#define R8A7743_CLK_RCAN	28
+#define R8A7743_CLK_R		29
+#define R8A7743_CLK_OSC		30
+
+#endif /* __DT_BINDINGS_CLOCK_R8A7743_CPG_MSSR_H__ */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/r8a7745-cpg-mssr.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/r8a7745-cpg-mssr.h
new file mode 100644
index 0000000000000000000000000000000000000000..56ad6f0c67606d74bd99098a6ed5d401d5799c39
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/r8a7745-cpg-mssr.h
@@ -0,0 +1,44 @@
+/*
+ * Copyright (C) 2016 Cogent Embedded Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#ifndef __DT_BINDINGS_CLOCK_R8A7745_CPG_MSSR_H__
+#define __DT_BINDINGS_CLOCK_R8A7745_CPG_MSSR_H__
+
+#include <dt-bindings/clock/renesas-cpg-mssr.h>
+
+/* r8a7745 CPG Core Clocks */
+#define R8A7745_CLK_Z2		0
+#define R8A7745_CLK_ZG		1
+#define R8A7745_CLK_ZTR		2
+#define R8A7745_CLK_ZTRD2	3
+#define R8A7745_CLK_ZT		4
+#define R8A7745_CLK_ZX		5
+#define R8A7745_CLK_ZS		6
+#define R8A7745_CLK_HP		7
+#define R8A7745_CLK_B		9
+#define R8A7745_CLK_LB		10
+#define R8A7745_CLK_P		11
+#define R8A7745_CLK_CL		12
+#define R8A7745_CLK_CP		13
+#define R8A7745_CLK_M2		14
+#define R8A7745_CLK_ZB3		16
+#define R8A7745_CLK_ZB3D2	17
+#define R8A7745_CLK_DDR		18
+#define R8A7745_CLK_SDH		19
+#define R8A7745_CLK_SD0		20
+#define R8A7745_CLK_SD2		21
+#define R8A7745_CLK_SD3		22
+#define R8A7745_CLK_MMC0	23
+#define R8A7745_CLK_MP		24
+#define R8A7745_CLK_QSPI	25
+#define R8A7745_CLK_CPEX	26
+#define R8A7745_CLK_RCAN	27
+#define R8A7745_CLK_R		28
+#define R8A7745_CLK_OSC		29
+
+#endif /* __DT_BINDINGS_CLOCK_R8A7745_CPG_MSSR_H__ */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/r8a77470-cpg-mssr.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/r8a77470-cpg-mssr.h
new file mode 100644
index 0000000000000000000000000000000000000000..34cba49d0f8460bc856b9e4fe56e82794b5db5bb
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/r8a77470-cpg-mssr.h
@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (C) 2018 Renesas Electronics Corp.
+ */
+#ifndef __DT_BINDINGS_CLOCK_R8A77470_CPG_MSSR_H__
+#define __DT_BINDINGS_CLOCK_R8A77470_CPG_MSSR_H__
+
+#include <dt-bindings/clock/renesas-cpg-mssr.h>
+
+/* r8a77470 CPG Core Clocks */
+#define R8A77470_CLK_Z2		0
+#define R8A77470_CLK_ZTR	1
+#define R8A77470_CLK_ZTRD2	2
+#define R8A77470_CLK_ZT		3
+#define R8A77470_CLK_ZX		4
+#define R8A77470_CLK_ZS		5
+#define R8A77470_CLK_HP		6
+#define R8A77470_CLK_B		7
+#define R8A77470_CLK_LB		8
+#define R8A77470_CLK_P		9
+#define R8A77470_CLK_CL		10
+#define R8A77470_CLK_CP		11
+#define R8A77470_CLK_M2		12
+#define R8A77470_CLK_ZB3	13
+#define R8A77470_CLK_SDH	14
+#define R8A77470_CLK_SD0	15
+#define R8A77470_CLK_SD1	16
+#define R8A77470_CLK_SD2	17
+#define R8A77470_CLK_MP		18
+#define R8A77470_CLK_QSPI	19
+#define R8A77470_CLK_CPEX	20
+#define R8A77470_CLK_RCAN	21
+#define R8A77470_CLK_R		22
+#define R8A77470_CLK_OSC	23
+
+#endif /* __DT_BINDINGS_CLOCK_R8A77470_CPG_MSSR_H__ */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/r8a7778-clock.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/r8a7778-clock.h
new file mode 100644
index 0000000000000000000000000000000000000000..f6b07c5399dec1f9a3c42c6990cb54f3785a69b5
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/r8a7778-clock.h
@@ -0,0 +1,71 @@
+/*
+ * Copyright (C) 2014 Ulrich Hecht
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_R8A7778_H__
+#define __DT_BINDINGS_CLOCK_R8A7778_H__
+
+/* CPG */
+#define R8A7778_CLK_PLLA	0
+#define R8A7778_CLK_PLLB	1
+#define R8A7778_CLK_B		2
+#define R8A7778_CLK_OUT		3
+#define R8A7778_CLK_P		4
+#define R8A7778_CLK_S		5
+#define R8A7778_CLK_S1		6
+
+/* MSTP0 */
+#define R8A7778_CLK_I2C0	30
+#define R8A7778_CLK_I2C1	29
+#define R8A7778_CLK_I2C2	28
+#define R8A7778_CLK_I2C3	27
+#define R8A7778_CLK_SCIF0	26
+#define R8A7778_CLK_SCIF1	25
+#define R8A7778_CLK_SCIF2	24
+#define R8A7778_CLK_SCIF3	23
+#define R8A7778_CLK_SCIF4	22
+#define R8A7778_CLK_SCIF5	21
+#define R8A7778_CLK_TMU0	16
+#define R8A7778_CLK_TMU1	15
+#define R8A7778_CLK_TMU2	14
+#define R8A7778_CLK_SSI0	12
+#define R8A7778_CLK_SSI1	11
+#define R8A7778_CLK_SSI2	10
+#define R8A7778_CLK_SSI3	9
+#define R8A7778_CLK_SRU		8
+#define R8A7778_CLK_HSPI	7
+
+/* MSTP1 */
+#define R8A7778_CLK_ETHER	14
+#define R8A7778_CLK_VIN0	10
+#define R8A7778_CLK_VIN1	9
+#define R8A7778_CLK_USB		0
+
+/* MSTP3 */
+#define R8A7778_CLK_MMC		31
+#define R8A7778_CLK_SDHI0	23
+#define R8A7778_CLK_SDHI1	22
+#define R8A7778_CLK_SDHI2	21
+#define R8A7778_CLK_SSI4	11
+#define R8A7778_CLK_SSI5	10
+#define R8A7778_CLK_SSI6	9
+#define R8A7778_CLK_SSI7	8
+#define R8A7778_CLK_SSI8	7
+
+/* MSTP5 */
+#define R8A7778_CLK_SRU_SRC0	31
+#define R8A7778_CLK_SRU_SRC1	30
+#define R8A7778_CLK_SRU_SRC2	29
+#define R8A7778_CLK_SRU_SRC3	28
+#define R8A7778_CLK_SRU_SRC4	27
+#define R8A7778_CLK_SRU_SRC5	26
+#define R8A7778_CLK_SRU_SRC6	25
+#define R8A7778_CLK_SRU_SRC7	24
+#define R8A7778_CLK_SRU_SRC8	23
+
+#endif /* __DT_BINDINGS_CLOCK_R8A7778_H__ */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/r8a7779-clock.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/r8a7779-clock.h
new file mode 100644
index 0000000000000000000000000000000000000000..381a6114237a5e5e89403c0bbd17e5e67cfc5951
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/r8a7779-clock.h
@@ -0,0 +1,64 @@
+/*
+ * Copyright (C) 2013  Horms Solutions Ltd.
+ *
+ * Contact: Simon Horman <horms@verge.net.au>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_R8A7779_H__
+#define __DT_BINDINGS_CLOCK_R8A7779_H__
+
+/* CPG */
+#define R8A7779_CLK_PLLA	0
+#define R8A7779_CLK_Z		1
+#define R8A7779_CLK_ZS		2
+#define R8A7779_CLK_S		3
+#define R8A7779_CLK_S1		4
+#define R8A7779_CLK_P		5
+#define R8A7779_CLK_B		6
+#define R8A7779_CLK_OUT		7
+
+/* MSTP 0 */
+#define R8A7779_CLK_HSPI	7
+#define R8A7779_CLK_TMU2	14
+#define R8A7779_CLK_TMU1	15
+#define R8A7779_CLK_TMU0	16
+#define R8A7779_CLK_HSCIF1	18
+#define R8A7779_CLK_HSCIF0	19
+#define R8A7779_CLK_SCIF5	21
+#define R8A7779_CLK_SCIF4	22
+#define R8A7779_CLK_SCIF3	23
+#define R8A7779_CLK_SCIF2	24
+#define R8A7779_CLK_SCIF1	25
+#define R8A7779_CLK_SCIF0	26
+#define R8A7779_CLK_I2C3	27
+#define R8A7779_CLK_I2C2	28
+#define R8A7779_CLK_I2C1	29
+#define R8A7779_CLK_I2C0	30
+
+/* MSTP 1 */
+#define R8A7779_CLK_USB01	0
+#define R8A7779_CLK_USB2	1
+#define R8A7779_CLK_DU		3
+#define R8A7779_CLK_VIN2	8
+#define R8A7779_CLK_VIN1	9
+#define R8A7779_CLK_VIN0	10
+#define R8A7779_CLK_ETHER	14
+#define R8A7779_CLK_SATA	15
+#define R8A7779_CLK_PCIE	16
+#define R8A7779_CLK_VIN3	20
+
+/* MSTP 3 */
+#define R8A7779_CLK_SDHI3	20
+#define R8A7779_CLK_SDHI2	21
+#define R8A7779_CLK_SDHI1	22
+#define R8A7779_CLK_SDHI0	23
+#define R8A7779_CLK_MMC1	30
+#define R8A7779_CLK_MMC0	31
+
+
+#endif /* __DT_BINDINGS_CLOCK_R8A7779_H__ */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/r8a7790-clock.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/r8a7790-clock.h
new file mode 100644
index 0000000000000000000000000000000000000000..20641fa68e731ec0a49f3c44b24a8629fca30dd8
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/r8a7790-clock.h
@@ -0,0 +1,162 @@
+/*
+ * Copyright 2013 Ideas On Board SPRL
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_R8A7790_H__
+#define __DT_BINDINGS_CLOCK_R8A7790_H__
+
+/* CPG */
+#define R8A7790_CLK_MAIN		0
+#define R8A7790_CLK_PLL0		1
+#define R8A7790_CLK_PLL1		2
+#define R8A7790_CLK_PLL3		3
+#define R8A7790_CLK_LB			4
+#define R8A7790_CLK_QSPI		5
+#define R8A7790_CLK_SDH			6
+#define R8A7790_CLK_SD0			7
+#define R8A7790_CLK_SD1			8
+#define R8A7790_CLK_Z			9
+#define R8A7790_CLK_RCAN		10
+#define R8A7790_CLK_ADSP		11
+
+/* MSTP0 */
+#define R8A7790_CLK_MSIOF0		0
+
+/* MSTP1 */
+#define R8A7790_CLK_VCP1		0
+#define R8A7790_CLK_VCP0		1
+#define R8A7790_CLK_VPC1		2
+#define R8A7790_CLK_VPC0		3
+#define R8A7790_CLK_JPU			6
+#define R8A7790_CLK_SSP1		9
+#define R8A7790_CLK_TMU1		11
+#define R8A7790_CLK_3DG			12
+#define R8A7790_CLK_2DDMAC		15
+#define R8A7790_CLK_FDP1_2		17
+#define R8A7790_CLK_FDP1_1		18
+#define R8A7790_CLK_FDP1_0		19
+#define R8A7790_CLK_TMU3		21
+#define R8A7790_CLK_TMU2		22
+#define R8A7790_CLK_CMT0		24
+#define R8A7790_CLK_TMU0		25
+#define R8A7790_CLK_VSP1_DU1		27
+#define R8A7790_CLK_VSP1_DU0		28
+#define R8A7790_CLK_VSP1_R		30
+#define R8A7790_CLK_VSP1_S		31
+
+/* MSTP2 */
+#define R8A7790_CLK_SCIFA2		2
+#define R8A7790_CLK_SCIFA1		3
+#define R8A7790_CLK_SCIFA0		4
+#define R8A7790_CLK_MSIOF2		5
+#define R8A7790_CLK_SCIFB0		6
+#define R8A7790_CLK_SCIFB1		7
+#define R8A7790_CLK_MSIOF1		8
+#define R8A7790_CLK_MSIOF3		15
+#define R8A7790_CLK_SCIFB2		16
+#define R8A7790_CLK_SYS_DMAC1		18
+#define R8A7790_CLK_SYS_DMAC0		19
+
+/* MSTP3 */
+#define R8A7790_CLK_IIC2		0
+#define R8A7790_CLK_TPU0		4
+#define R8A7790_CLK_MMCIF1		5
+#define R8A7790_CLK_SCIF2		10
+#define R8A7790_CLK_SDHI3		11
+#define R8A7790_CLK_SDHI2		12
+#define R8A7790_CLK_SDHI1		13
+#define R8A7790_CLK_SDHI0		14
+#define R8A7790_CLK_MMCIF0		15
+#define R8A7790_CLK_IIC0		18
+#define R8A7790_CLK_PCIEC		19
+#define R8A7790_CLK_IIC1		23
+#define R8A7790_CLK_SSUSB		28
+#define R8A7790_CLK_CMT1		29
+#define R8A7790_CLK_USBDMAC0		30
+#define R8A7790_CLK_USBDMAC1		31
+
+/* MSTP4 */
+#define R8A7790_CLK_IRQC		7
+#define R8A7790_CLK_INTC_SYS		8
+
+/* MSTP5 */
+#define R8A7790_CLK_AUDIO_DMAC1		1
+#define R8A7790_CLK_AUDIO_DMAC0		2
+#define R8A7790_CLK_ADSP_MOD		6
+#define R8A7790_CLK_THERMAL		22
+#define R8A7790_CLK_PWM			23
+
+/* MSTP7 */
+#define R8A7790_CLK_EHCI		3
+#define R8A7790_CLK_HSUSB		4
+#define R8A7790_CLK_HSCIF1		16
+#define R8A7790_CLK_HSCIF0		17
+#define R8A7790_CLK_SCIF1		20
+#define R8A7790_CLK_SCIF0		21
+#define R8A7790_CLK_DU2			22
+#define R8A7790_CLK_DU1			23
+#define R8A7790_CLK_DU0			24
+#define R8A7790_CLK_LVDS1		25
+#define R8A7790_CLK_LVDS0		26
+
+/* MSTP8 */
+#define R8A7790_CLK_MLB			2
+#define R8A7790_CLK_VIN3		8
+#define R8A7790_CLK_VIN2		9
+#define R8A7790_CLK_VIN1		10
+#define R8A7790_CLK_VIN0		11
+#define R8A7790_CLK_ETHERAVB		12
+#define R8A7790_CLK_ETHER		13
+#define R8A7790_CLK_SATA1		14
+#define R8A7790_CLK_SATA0		15
+
+/* MSTP9 */
+#define R8A7790_CLK_GPIO5		7
+#define R8A7790_CLK_GPIO4		8
+#define R8A7790_CLK_GPIO3		9
+#define R8A7790_CLK_GPIO2		10
+#define R8A7790_CLK_GPIO1		11
+#define R8A7790_CLK_GPIO0		12
+#define R8A7790_CLK_RCAN1		15
+#define R8A7790_CLK_RCAN0		16
+#define R8A7790_CLK_QSPI_MOD		17
+#define R8A7790_CLK_IICDVFS		26
+#define R8A7790_CLK_I2C3		28
+#define R8A7790_CLK_I2C2		29
+#define R8A7790_CLK_I2C1		30
+#define R8A7790_CLK_I2C0		31
+
+/* MSTP10 */
+#define R8A7790_CLK_SSI_ALL		5
+#define R8A7790_CLK_SSI9		6
+#define R8A7790_CLK_SSI8		7
+#define R8A7790_CLK_SSI7		8
+#define R8A7790_CLK_SSI6		9
+#define R8A7790_CLK_SSI5		10
+#define R8A7790_CLK_SSI4		11
+#define R8A7790_CLK_SSI3		12
+#define R8A7790_CLK_SSI2		13
+#define R8A7790_CLK_SSI1		14
+#define R8A7790_CLK_SSI0		15
+#define R8A7790_CLK_SCU_ALL		17
+#define R8A7790_CLK_SCU_DVC1		18
+#define R8A7790_CLK_SCU_DVC0		19
+#define R8A7790_CLK_SCU_CTU1_MIX1	20
+#define R8A7790_CLK_SCU_CTU0_MIX0	21
+#define R8A7790_CLK_SCU_SRC9		22
+#define R8A7790_CLK_SCU_SRC8		23
+#define R8A7790_CLK_SCU_SRC7		24
+#define R8A7790_CLK_SCU_SRC6		25
+#define R8A7790_CLK_SCU_SRC5		26
+#define R8A7790_CLK_SCU_SRC4		27
+#define R8A7790_CLK_SCU_SRC3		28
+#define R8A7790_CLK_SCU_SRC2		29
+#define R8A7790_CLK_SCU_SRC1		30
+#define R8A7790_CLK_SCU_SRC0		31
+
+#endif /* __DT_BINDINGS_CLOCK_R8A7790_H__ */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/r8a7790-cpg-mssr.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/r8a7790-cpg-mssr.h
new file mode 100644
index 0000000000000000000000000000000000000000..1625b8bf34822b6e8f41f1dbdead56c8ce13bff6
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/r8a7790-cpg-mssr.h
@@ -0,0 +1,52 @@
+/*
+ * Copyright (C) 2015 Renesas Electronics Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_R8A7790_CPG_MSSR_H__
+#define __DT_BINDINGS_CLOCK_R8A7790_CPG_MSSR_H__
+
+#include <dt-bindings/clock/renesas-cpg-mssr.h>
+
+/* r8a7790 CPG Core Clocks */
+#define R8A7790_CLK_Z			0
+#define R8A7790_CLK_Z2			1
+#define R8A7790_CLK_ZG			2
+#define R8A7790_CLK_ZTR			3
+#define R8A7790_CLK_ZTRD2		4
+#define R8A7790_CLK_ZT			5
+#define R8A7790_CLK_ZX			6
+#define R8A7790_CLK_ZS			7
+#define R8A7790_CLK_HP			8
+#define R8A7790_CLK_I			9
+#define R8A7790_CLK_B			10
+#define R8A7790_CLK_LB			11
+#define R8A7790_CLK_P			12
+#define R8A7790_CLK_CL			13
+#define R8A7790_CLK_M2			14
+#define R8A7790_CLK_ADSP		15
+#define R8A7790_CLK_IMP			16
+#define R8A7790_CLK_ZB3			17
+#define R8A7790_CLK_ZB3D2		18
+#define R8A7790_CLK_DDR			19
+#define R8A7790_CLK_SDH			20
+#define R8A7790_CLK_SD0			21
+#define R8A7790_CLK_SD1			22
+#define R8A7790_CLK_SD2			23
+#define R8A7790_CLK_SD3			24
+#define R8A7790_CLK_MMC0		25
+#define R8A7790_CLK_MMC1		26
+#define R8A7790_CLK_MP			27
+#define R8A7790_CLK_SSP			28
+#define R8A7790_CLK_SSPRS		29
+#define R8A7790_CLK_QSPI		30
+#define R8A7790_CLK_CP			31
+#define R8A7790_CLK_RCAN		32
+#define R8A7790_CLK_R			33
+#define R8A7790_CLK_OSC			34
+
+#endif /* __DT_BINDINGS_CLOCK_R8A7790_CPG_MSSR_H__ */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/r8a7791-clock.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/r8a7791-clock.h
new file mode 100644
index 0000000000000000000000000000000000000000..ef692134146b27b9041ea2ec8400539e10714680
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/r8a7791-clock.h
@@ -0,0 +1,165 @@
+/*
+ * Copyright 2013 Ideas On Board SPRL
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_R8A7791_H__
+#define __DT_BINDINGS_CLOCK_R8A7791_H__
+
+/* CPG */
+#define R8A7791_CLK_MAIN		0
+#define R8A7791_CLK_PLL0		1
+#define R8A7791_CLK_PLL1		2
+#define R8A7791_CLK_PLL3		3
+#define R8A7791_CLK_LB			4
+#define R8A7791_CLK_QSPI		5
+#define R8A7791_CLK_SDH			6
+#define R8A7791_CLK_SD0			7
+#define R8A7791_CLK_Z			8
+#define R8A7791_CLK_RCAN		9
+#define R8A7791_CLK_ADSP		10
+
+/* MSTP0 */
+#define R8A7791_CLK_MSIOF0		0
+
+/* MSTP1 */
+#define R8A7791_CLK_VCP0		1
+#define R8A7791_CLK_VPC0		3
+#define R8A7791_CLK_JPU			6
+#define R8A7791_CLK_SSP1		9
+#define R8A7791_CLK_TMU1		11
+#define R8A7791_CLK_3DG			12
+#define R8A7791_CLK_2DDMAC		15
+#define R8A7791_CLK_FDP1_1		18
+#define R8A7791_CLK_FDP1_0		19
+#define R8A7791_CLK_TMU3		21
+#define R8A7791_CLK_TMU2		22
+#define R8A7791_CLK_CMT0		24
+#define R8A7791_CLK_TMU0		25
+#define R8A7791_CLK_VSP1_DU1		27
+#define R8A7791_CLK_VSP1_DU0		28
+#define R8A7791_CLK_VSP1_S		31
+
+/* MSTP2 */
+#define R8A7791_CLK_SCIFA2		2
+#define R8A7791_CLK_SCIFA1		3
+#define R8A7791_CLK_SCIFA0		4
+#define R8A7791_CLK_MSIOF2		5
+#define R8A7791_CLK_SCIFB0		6
+#define R8A7791_CLK_SCIFB1		7
+#define R8A7791_CLK_MSIOF1		8
+#define R8A7791_CLK_SCIFB2		16
+#define R8A7791_CLK_SYS_DMAC1		18
+#define R8A7791_CLK_SYS_DMAC0		19
+
+/* MSTP3 */
+#define R8A7791_CLK_TPU0		4
+#define R8A7791_CLK_SDHI2		11
+#define R8A7791_CLK_SDHI1		12
+#define R8A7791_CLK_SDHI0		14
+#define R8A7791_CLK_MMCIF0		15
+#define R8A7791_CLK_IIC0		18
+#define R8A7791_CLK_PCIEC		19
+#define R8A7791_CLK_IIC1		23
+#define R8A7791_CLK_SSUSB		28
+#define R8A7791_CLK_CMT1		29
+#define R8A7791_CLK_USBDMAC0		30
+#define R8A7791_CLK_USBDMAC1		31
+
+/* MSTP4 */
+#define R8A7791_CLK_IRQC		7
+#define R8A7791_CLK_INTC_SYS		8
+
+/* MSTP5 */
+#define R8A7791_CLK_AUDIO_DMAC1		1
+#define R8A7791_CLK_AUDIO_DMAC0		2
+#define R8A7791_CLK_ADSP_MOD		6
+#define R8A7791_CLK_THERMAL		22
+#define R8A7791_CLK_PWM			23
+
+/* MSTP7 */
+#define R8A7791_CLK_EHCI		3
+#define R8A7791_CLK_HSUSB		4
+#define R8A7791_CLK_HSCIF2		13
+#define R8A7791_CLK_SCIF5		14
+#define R8A7791_CLK_SCIF4		15
+#define R8A7791_CLK_HSCIF1		16
+#define R8A7791_CLK_HSCIF0		17
+#define R8A7791_CLK_SCIF3		18
+#define R8A7791_CLK_SCIF2		19
+#define R8A7791_CLK_SCIF1		20
+#define R8A7791_CLK_SCIF0		21
+#define R8A7791_CLK_DU1			23
+#define R8A7791_CLK_DU0			24
+#define R8A7791_CLK_LVDS0		26
+
+/* MSTP8 */
+#define R8A7791_CLK_IPMMU_SGX		0
+#define R8A7791_CLK_MLB			2
+#define R8A7791_CLK_VIN2		9
+#define R8A7791_CLK_VIN1		10
+#define R8A7791_CLK_VIN0		11
+#define R8A7791_CLK_ETHERAVB		12
+#define R8A7791_CLK_ETHER		13
+#define R8A7791_CLK_SATA1		14
+#define R8A7791_CLK_SATA0		15
+
+/* MSTP9 */
+#define R8A7791_CLK_GYROADC		1
+#define R8A7791_CLK_GPIO7		4
+#define R8A7791_CLK_GPIO6		5
+#define R8A7791_CLK_GPIO5		7
+#define R8A7791_CLK_GPIO4		8
+#define R8A7791_CLK_GPIO3		9
+#define R8A7791_CLK_GPIO2		10
+#define R8A7791_CLK_GPIO1		11
+#define R8A7791_CLK_GPIO0		12
+#define R8A7791_CLK_RCAN1		15
+#define R8A7791_CLK_RCAN0		16
+#define R8A7791_CLK_QSPI_MOD		17
+#define R8A7791_CLK_I2C5		25
+#define R8A7791_CLK_IICDVFS		26
+#define R8A7791_CLK_I2C4		27
+#define R8A7791_CLK_I2C3		28
+#define R8A7791_CLK_I2C2		29
+#define R8A7791_CLK_I2C1		30
+#define R8A7791_CLK_I2C0		31
+
+/* MSTP10 */
+#define R8A7791_CLK_SSI_ALL		5
+#define R8A7791_CLK_SSI9		6
+#define R8A7791_CLK_SSI8		7
+#define R8A7791_CLK_SSI7		8
+#define R8A7791_CLK_SSI6		9
+#define R8A7791_CLK_SSI5		10
+#define R8A7791_CLK_SSI4		11
+#define R8A7791_CLK_SSI3		12
+#define R8A7791_CLK_SSI2		13
+#define R8A7791_CLK_SSI1		14
+#define R8A7791_CLK_SSI0		15
+#define R8A7791_CLK_SCU_ALL		17
+#define R8A7791_CLK_SCU_DVC1		18
+#define R8A7791_CLK_SCU_DVC0		19
+#define R8A7791_CLK_SCU_CTU1_MIX1	20
+#define R8A7791_CLK_SCU_CTU0_MIX0	21
+#define R8A7791_CLK_SCU_SRC9		22
+#define R8A7791_CLK_SCU_SRC8		23
+#define R8A7791_CLK_SCU_SRC7		24
+#define R8A7791_CLK_SCU_SRC6		25
+#define R8A7791_CLK_SCU_SRC5		26
+#define R8A7791_CLK_SCU_SRC4		27
+#define R8A7791_CLK_SCU_SRC3		28
+#define R8A7791_CLK_SCU_SRC2		29
+#define R8A7791_CLK_SCU_SRC1		30
+#define R8A7791_CLK_SCU_SRC0		31
+
+/* MSTP11 */
+#define R8A7791_CLK_SCIFA3		6
+#define R8A7791_CLK_SCIFA4		7
+#define R8A7791_CLK_SCIFA5		8
+
+#endif /* __DT_BINDINGS_CLOCK_R8A7791_H__ */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/r8a7791-cpg-mssr.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/r8a7791-cpg-mssr.h
new file mode 100644
index 0000000000000000000000000000000000000000..e8823410c01c5a09d0676ddf547c1821b42cf619
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/r8a7791-cpg-mssr.h
@@ -0,0 +1,48 @@
+/*
+ * Copyright (C) 2015 Renesas Electronics Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_R8A7791_CPG_MSSR_H__
+#define __DT_BINDINGS_CLOCK_R8A7791_CPG_MSSR_H__
+
+#include <dt-bindings/clock/renesas-cpg-mssr.h>
+
+/* r8a7791 CPG Core Clocks */
+#define R8A7791_CLK_Z			0
+#define R8A7791_CLK_ZG			1
+#define R8A7791_CLK_ZTR			2
+#define R8A7791_CLK_ZTRD2		3
+#define R8A7791_CLK_ZT			4
+#define R8A7791_CLK_ZX			5
+#define R8A7791_CLK_ZS			6
+#define R8A7791_CLK_HP			7
+#define R8A7791_CLK_I			8
+#define R8A7791_CLK_B			9
+#define R8A7791_CLK_LB			10
+#define R8A7791_CLK_P			11
+#define R8A7791_CLK_CL			12
+#define R8A7791_CLK_M2			13
+#define R8A7791_CLK_ADSP		14
+#define R8A7791_CLK_ZB3			15
+#define R8A7791_CLK_ZB3D2		16
+#define R8A7791_CLK_DDR			17
+#define R8A7791_CLK_SDH			18
+#define R8A7791_CLK_SD0			19
+#define R8A7791_CLK_SD2			20
+#define R8A7791_CLK_SD3			21
+#define R8A7791_CLK_MMC0		22
+#define R8A7791_CLK_MP			23
+#define R8A7791_CLK_SSP			24
+#define R8A7791_CLK_SSPRS		25
+#define R8A7791_CLK_QSPI		26
+#define R8A7791_CLK_CP			27
+#define R8A7791_CLK_RCAN		28
+#define R8A7791_CLK_R			29
+#define R8A7791_CLK_OSC			30
+
+#endif /* __DT_BINDINGS_CLOCK_R8A7791_CPG_MSSR_H__ */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/r8a7792-clock.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/r8a7792-clock.h
new file mode 100644
index 0000000000000000000000000000000000000000..5be90bc23bd7909788e658069f385f6ebec7fc7e
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/r8a7792-clock.h
@@ -0,0 +1,102 @@
+/*
+ * Copyright (C) 2016 Cogent Embedded, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_R8A7792_H__
+#define __DT_BINDINGS_CLOCK_R8A7792_H__
+
+/* CPG */
+#define R8A7792_CLK_MAIN		0
+#define R8A7792_CLK_PLL0		1
+#define R8A7792_CLK_PLL1		2
+#define R8A7792_CLK_PLL3		3
+#define R8A7792_CLK_LB			4
+#define R8A7792_CLK_QSPI		5
+
+/* MSTP0 */
+#define R8A7792_CLK_MSIOF0		0
+
+/* MSTP1 */
+#define R8A7792_CLK_JPU			6
+#define R8A7792_CLK_TMU1		11
+#define R8A7792_CLK_TMU3		21
+#define R8A7792_CLK_TMU2		22
+#define R8A7792_CLK_CMT0		24
+#define R8A7792_CLK_TMU0		25
+#define R8A7792_CLK_VSP1DU1		27
+#define R8A7792_CLK_VSP1DU0		28
+#define R8A7792_CLK_VSP1_SY		31
+
+/* MSTP2 */
+#define R8A7792_CLK_MSIOF1		8
+#define R8A7792_CLK_SYS_DMAC1		18
+#define R8A7792_CLK_SYS_DMAC0		19
+
+/* MSTP3 */
+#define R8A7792_CLK_TPU0		4
+#define R8A7792_CLK_SDHI0		14
+#define R8A7792_CLK_CMT1		29
+
+/* MSTP4 */
+#define R8A7792_CLK_IRQC		7
+#define R8A7792_CLK_INTC_SYS		8
+
+/* MSTP5 */
+#define R8A7792_CLK_AUDIO_DMAC0		2
+#define R8A7792_CLK_THERMAL		22
+#define R8A7792_CLK_PWM			23
+
+/* MSTP7 */
+#define R8A7792_CLK_HSCIF1		16
+#define R8A7792_CLK_HSCIF0		17
+#define R8A7792_CLK_SCIF3		18
+#define R8A7792_CLK_SCIF2		19
+#define R8A7792_CLK_SCIF1		20
+#define R8A7792_CLK_SCIF0		21
+#define R8A7792_CLK_DU1			23
+#define R8A7792_CLK_DU0			24
+
+/* MSTP8 */
+#define R8A7792_CLK_VIN5		4
+#define R8A7792_CLK_VIN4		5
+#define R8A7792_CLK_VIN3		8
+#define R8A7792_CLK_VIN2		9
+#define R8A7792_CLK_VIN1		10
+#define R8A7792_CLK_VIN0		11
+#define R8A7792_CLK_ETHERAVB		12
+
+/* MSTP9 */
+#define R8A7792_CLK_GPIO7		4
+#define R8A7792_CLK_GPIO6		5
+#define R8A7792_CLK_GPIO5		7
+#define R8A7792_CLK_GPIO4		8
+#define R8A7792_CLK_GPIO3		9
+#define R8A7792_CLK_GPIO2		10
+#define R8A7792_CLK_GPIO1		11
+#define R8A7792_CLK_GPIO0		12
+#define R8A7792_CLK_GPIO11		13
+#define R8A7792_CLK_GPIO10		14
+#define R8A7792_CLK_CAN1		15
+#define R8A7792_CLK_CAN0		16
+#define R8A7792_CLK_QSPI_MOD		17
+#define R8A7792_CLK_GPIO9		19
+#define R8A7792_CLK_GPIO8		21
+#define R8A7792_CLK_I2C5		25
+#define R8A7792_CLK_IICDVFS		26
+#define R8A7792_CLK_I2C4		27
+#define R8A7792_CLK_I2C3		28
+#define R8A7792_CLK_I2C2		29
+#define R8A7792_CLK_I2C1		30
+#define R8A7792_CLK_I2C0		31
+
+/* MSTP10 */
+#define R8A7792_CLK_SSI_ALL		5
+#define R8A7792_CLK_SSI4		11
+#define R8A7792_CLK_SSI3		12
+
+#endif /* __DT_BINDINGS_CLOCK_R8A7792_H__ */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/r8a7792-cpg-mssr.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/r8a7792-cpg-mssr.h
new file mode 100644
index 0000000000000000000000000000000000000000..72ce85cb2f94b0abb206145d9332dc14a47f738c
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/r8a7792-cpg-mssr.h
@@ -0,0 +1,43 @@
+/*
+ * Copyright (C) 2015 Renesas Electronics Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_R8A7792_CPG_MSSR_H__
+#define __DT_BINDINGS_CLOCK_R8A7792_CPG_MSSR_H__
+
+#include <dt-bindings/clock/renesas-cpg-mssr.h>
+
+/* r8a7792 CPG Core Clocks */
+#define R8A7792_CLK_Z			0
+#define R8A7792_CLK_ZG			1
+#define R8A7792_CLK_ZTR			2
+#define R8A7792_CLK_ZTRD2		3
+#define R8A7792_CLK_ZT			4
+#define R8A7792_CLK_ZX			5
+#define R8A7792_CLK_ZS			6
+#define R8A7792_CLK_HP			7
+#define R8A7792_CLK_I			8
+#define R8A7792_CLK_B			9
+#define R8A7792_CLK_LB			10
+#define R8A7792_CLK_P			11
+#define R8A7792_CLK_CL			12
+#define R8A7792_CLK_M2			13
+#define R8A7792_CLK_IMP			14
+#define R8A7792_CLK_ZB3			15
+#define R8A7792_CLK_ZB3D2		16
+#define R8A7792_CLK_DDR			17
+#define R8A7792_CLK_SD			18
+#define R8A7792_CLK_MP			19
+#define R8A7792_CLK_QSPI		20
+#define R8A7792_CLK_CP			21
+#define R8A7792_CLK_CPEX		22
+#define R8A7792_CLK_RCAN		23
+#define R8A7792_CLK_R			24
+#define R8A7792_CLK_OSC			25
+
+#endif /* __DT_BINDINGS_CLOCK_R8A7792_CPG_MSSR_H__ */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/r8a7793-clock.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/r8a7793-clock.h
new file mode 100644
index 0000000000000000000000000000000000000000..7318d45d4e7e9888c41aa1fb66def087b4cb6ff4
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/r8a7793-clock.h
@@ -0,0 +1,167 @@
+/*
+ * r8a7793 clock definition
+ *
+ * Copyright (C) 2014  Renesas Electronics Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_R8A7793_H__
+#define __DT_BINDINGS_CLOCK_R8A7793_H__
+
+/* CPG */
+#define R8A7793_CLK_MAIN		0
+#define R8A7793_CLK_PLL0		1
+#define R8A7793_CLK_PLL1		2
+#define R8A7793_CLK_PLL3		3
+#define R8A7793_CLK_LB			4
+#define R8A7793_CLK_QSPI		5
+#define R8A7793_CLK_SDH			6
+#define R8A7793_CLK_SD0			7
+#define R8A7793_CLK_Z			8
+#define R8A7793_CLK_RCAN		9
+#define R8A7793_CLK_ADSP		10
+
+/* MSTP0 */
+#define R8A7793_CLK_MSIOF0		0
+
+/* MSTP1 */
+#define R8A7793_CLK_VCP0		1
+#define R8A7793_CLK_VPC0		3
+#define R8A7793_CLK_SSP1		9
+#define R8A7793_CLK_TMU1		11
+#define R8A7793_CLK_3DG			12
+#define R8A7793_CLK_2DDMAC		15
+#define R8A7793_CLK_FDP1_1		18
+#define R8A7793_CLK_FDP1_0		19
+#define R8A7793_CLK_TMU3		21
+#define R8A7793_CLK_TMU2		22
+#define R8A7793_CLK_CMT0		24
+#define R8A7793_CLK_TMU0		25
+#define R8A7793_CLK_VSP1_DU1		27
+#define R8A7793_CLK_VSP1_DU0		28
+#define R8A7793_CLK_VSP1_S		31
+
+/* MSTP2 */
+#define R8A7793_CLK_SCIFA2		2
+#define R8A7793_CLK_SCIFA1		3
+#define R8A7793_CLK_SCIFA0		4
+#define R8A7793_CLK_MSIOF2		5
+#define R8A7793_CLK_SCIFB0		6
+#define R8A7793_CLK_SCIFB1		7
+#define R8A7793_CLK_MSIOF1		8
+#define R8A7793_CLK_SCIFB2		16
+#define R8A7793_CLK_SYS_DMAC1		18
+#define R8A7793_CLK_SYS_DMAC0		19
+
+/* MSTP3 */
+#define R8A7793_CLK_TPU0		4
+#define R8A7793_CLK_SDHI2		11
+#define R8A7793_CLK_SDHI1		12
+#define R8A7793_CLK_SDHI0		14
+#define R8A7793_CLK_MMCIF0		15
+#define R8A7793_CLK_IIC0		18
+#define R8A7793_CLK_PCIEC		19
+#define R8A7793_CLK_IIC1		23
+#define R8A7793_CLK_SSUSB		28
+#define R8A7793_CLK_CMT1		29
+#define R8A7793_CLK_USBDMAC0		30
+#define R8A7793_CLK_USBDMAC1		31
+
+/* MSTP4 */
+#define R8A7793_CLK_IRQC		7
+#define R8A7793_CLK_INTC_SYS		8
+
+/* MSTP5 */
+#define R8A7793_CLK_AUDIO_DMAC1		1
+#define R8A7793_CLK_AUDIO_DMAC0		2
+#define R8A7793_CLK_ADSP_MOD		6
+#define R8A7793_CLK_THERMAL		22
+#define R8A7793_CLK_PWM			23
+
+/* MSTP7 */
+#define R8A7793_CLK_EHCI		3
+#define R8A7793_CLK_HSUSB		4
+#define R8A7793_CLK_HSCIF2		13
+#define R8A7793_CLK_SCIF5		14
+#define R8A7793_CLK_SCIF4		15
+#define R8A7793_CLK_HSCIF1		16
+#define R8A7793_CLK_HSCIF0		17
+#define R8A7793_CLK_SCIF3		18
+#define R8A7793_CLK_SCIF2		19
+#define R8A7793_CLK_SCIF1		20
+#define R8A7793_CLK_SCIF0		21
+#define R8A7793_CLK_DU1			23
+#define R8A7793_CLK_DU0			24
+#define R8A7793_CLK_LVDS0		26
+
+/* MSTP8 */
+#define R8A7793_CLK_IPMMU_SGX		0
+#define R8A7793_CLK_VIN2		9
+#define R8A7793_CLK_VIN1		10
+#define R8A7793_CLK_VIN0		11
+#define R8A7793_CLK_ETHER		13
+#define R8A7793_CLK_SATA1		14
+#define R8A7793_CLK_SATA0		15
+
+/* MSTP9 */
+#define R8A7793_CLK_GPIO7		4
+#define R8A7793_CLK_GPIO6		5
+#define R8A7793_CLK_GPIO5		7
+#define R8A7793_CLK_GPIO4		8
+#define R8A7793_CLK_GPIO3		9
+#define R8A7793_CLK_GPIO2		10
+#define R8A7793_CLK_GPIO1		11
+#define R8A7793_CLK_GPIO0		12
+#define R8A7793_CLK_RCAN1		15
+#define R8A7793_CLK_RCAN0		16
+#define R8A7793_CLK_QSPI_MOD		17
+#define R8A7793_CLK_I2C5		25
+#define R8A7793_CLK_IICDVFS		26
+#define R8A7793_CLK_I2C4		27
+#define R8A7793_CLK_I2C3		28
+#define R8A7793_CLK_I2C2		29
+#define R8A7793_CLK_I2C1		30
+#define R8A7793_CLK_I2C0		31
+
+/* MSTP10 */
+#define R8A7793_CLK_SSI_ALL		5
+#define R8A7793_CLK_SSI9		6
+#define R8A7793_CLK_SSI8		7
+#define R8A7793_CLK_SSI7		8
+#define R8A7793_CLK_SSI6		9
+#define R8A7793_CLK_SSI5		10
+#define R8A7793_CLK_SSI4		11
+#define R8A7793_CLK_SSI3		12
+#define R8A7793_CLK_SSI2		13
+#define R8A7793_CLK_SSI1		14
+#define R8A7793_CLK_SSI0		15
+#define R8A7793_CLK_SCU_ALL		17
+#define R8A7793_CLK_SCU_DVC1		18
+#define R8A7793_CLK_SCU_DVC0		19
+#define R8A7793_CLK_SCU_CTU1_MIX1	20
+#define R8A7793_CLK_SCU_CTU0_MIX0	21
+#define R8A7793_CLK_SCU_SRC9		22
+#define R8A7793_CLK_SCU_SRC8		23
+#define R8A7793_CLK_SCU_SRC7		24
+#define R8A7793_CLK_SCU_SRC6		25
+#define R8A7793_CLK_SCU_SRC5		26
+#define R8A7793_CLK_SCU_SRC4		27
+#define R8A7793_CLK_SCU_SRC3		28
+#define R8A7793_CLK_SCU_SRC2		29
+#define R8A7793_CLK_SCU_SRC1		30
+#define R8A7793_CLK_SCU_SRC0		31
+
+/* MSTP11 */
+#define R8A7793_CLK_SCIFA3		6
+#define R8A7793_CLK_SCIFA4		7
+#define R8A7793_CLK_SCIFA5		8
+
+#endif /* __DT_BINDINGS_CLOCK_R8A7793_H__ */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/r8a7793-cpg-mssr.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/r8a7793-cpg-mssr.h
new file mode 100644
index 0000000000000000000000000000000000000000..8809b0f62d615457f07a463a3c4699d0276a0250
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/r8a7793-cpg-mssr.h
@@ -0,0 +1,48 @@
+/*
+ * Copyright (C) 2015 Renesas Electronics Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_R8A7793_CPG_MSSR_H__
+#define __DT_BINDINGS_CLOCK_R8A7793_CPG_MSSR_H__
+
+#include <dt-bindings/clock/renesas-cpg-mssr.h>
+
+/* r8a7793 CPG Core Clocks */
+#define R8A7793_CLK_Z			0
+#define R8A7793_CLK_ZG			1
+#define R8A7793_CLK_ZTR			2
+#define R8A7793_CLK_ZTRD2		3
+#define R8A7793_CLK_ZT			4
+#define R8A7793_CLK_ZX			5
+#define R8A7793_CLK_ZS			6
+#define R8A7793_CLK_HP			7
+#define R8A7793_CLK_I			8
+#define R8A7793_CLK_B			9
+#define R8A7793_CLK_LB			10
+#define R8A7793_CLK_P			11
+#define R8A7793_CLK_CL			12
+#define R8A7793_CLK_M2			13
+#define R8A7793_CLK_ADSP		14
+#define R8A7793_CLK_ZB3			15
+#define R8A7793_CLK_ZB3D2		16
+#define R8A7793_CLK_DDR			17
+#define R8A7793_CLK_SDH			18
+#define R8A7793_CLK_SD0			19
+#define R8A7793_CLK_SD2			20
+#define R8A7793_CLK_SD3			21
+#define R8A7793_CLK_MMC0		22
+#define R8A7793_CLK_MP			23
+#define R8A7793_CLK_SSP			24
+#define R8A7793_CLK_SSPRS		25
+#define R8A7793_CLK_QSPI		26
+#define R8A7793_CLK_CP			27
+#define R8A7793_CLK_RCAN		28
+#define R8A7793_CLK_R			29
+#define R8A7793_CLK_OSC			30
+
+#endif /* __DT_BINDINGS_CLOCK_R8A7793_CPG_MSSR_H__ */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/r8a7794-clock.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/r8a7794-clock.h
new file mode 100644
index 0000000000000000000000000000000000000000..93e99c3ffc8dafebef94d0644cb15532c86ab1b4
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/r8a7794-clock.h
@@ -0,0 +1,141 @@
+/*
+ * Copyright (C) 2014 Renesas Electronics Corporation
+ * Copyright 2013 Ideas On Board SPRL
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_R8A7794_H__
+#define __DT_BINDINGS_CLOCK_R8A7794_H__
+
+/* CPG */
+#define R8A7794_CLK_MAIN		0
+#define R8A7794_CLK_PLL0		1
+#define R8A7794_CLK_PLL1		2
+#define R8A7794_CLK_PLL3		3
+#define R8A7794_CLK_LB			4
+#define R8A7794_CLK_QSPI		5
+#define R8A7794_CLK_SDH			6
+#define R8A7794_CLK_SD0			7
+#define R8A7794_CLK_RCAN		8
+
+/* MSTP0 */
+#define R8A7794_CLK_MSIOF0		0
+
+/* MSTP1 */
+#define R8A7794_CLK_VCP0		1
+#define R8A7794_CLK_VPC0		3
+#define R8A7794_CLK_TMU1		11
+#define R8A7794_CLK_3DG			12
+#define R8A7794_CLK_2DDMAC		15
+#define R8A7794_CLK_FDP1_0		19
+#define R8A7794_CLK_TMU3		21
+#define R8A7794_CLK_TMU2		22
+#define R8A7794_CLK_CMT0		24
+#define R8A7794_CLK_TMU0		25
+#define R8A7794_CLK_VSP1_DU0		28
+#define R8A7794_CLK_VSP1_S		31
+
+/* MSTP2 */
+#define R8A7794_CLK_SCIFA2		2
+#define R8A7794_CLK_SCIFA1		3
+#define R8A7794_CLK_SCIFA0		4
+#define R8A7794_CLK_MSIOF2		5
+#define R8A7794_CLK_SCIFB0		6
+#define R8A7794_CLK_SCIFB1		7
+#define R8A7794_CLK_MSIOF1		8
+#define R8A7794_CLK_SCIFB2		16
+#define R8A7794_CLK_SYS_DMAC1		18
+#define R8A7794_CLK_SYS_DMAC0		19
+
+/* MSTP3 */
+#define R8A7794_CLK_SDHI2		11
+#define R8A7794_CLK_SDHI1		12
+#define R8A7794_CLK_SDHI0		14
+#define R8A7794_CLK_MMCIF0		15
+#define R8A7794_CLK_IIC0		18
+#define R8A7794_CLK_IIC1		23
+#define R8A7794_CLK_CMT1		29
+#define R8A7794_CLK_USBDMAC0		30
+#define R8A7794_CLK_USBDMAC1		31
+
+/* MSTP4 */
+#define R8A7794_CLK_IRQC		7
+#define R8A7794_CLK_INTC_SYS		8
+
+/* MSTP5 */
+#define R8A7794_CLK_AUDIO_DMAC0		2
+#define R8A7794_CLK_PWM			23
+
+/* MSTP7 */
+#define R8A7794_CLK_EHCI		3
+#define R8A7794_CLK_HSUSB		4
+#define R8A7794_CLK_HSCIF2		13
+#define R8A7794_CLK_SCIF5		14
+#define R8A7794_CLK_SCIF4		15
+#define R8A7794_CLK_HSCIF1		16
+#define R8A7794_CLK_HSCIF0		17
+#define R8A7794_CLK_SCIF3		18
+#define R8A7794_CLK_SCIF2		19
+#define R8A7794_CLK_SCIF1		20
+#define R8A7794_CLK_SCIF0		21
+#define R8A7794_CLK_DU1			23
+#define R8A7794_CLK_DU0			24
+
+/* MSTP8 */
+#define R8A7794_CLK_VIN1		10
+#define R8A7794_CLK_VIN0		11
+#define R8A7794_CLK_ETHERAVB		12
+#define R8A7794_CLK_ETHER		13
+
+/* MSTP9 */
+#define R8A7794_CLK_GPIO6		5
+#define R8A7794_CLK_GPIO5		7
+#define R8A7794_CLK_GPIO4		8
+#define R8A7794_CLK_GPIO3		9
+#define R8A7794_CLK_GPIO2		10
+#define R8A7794_CLK_GPIO1		11
+#define R8A7794_CLK_GPIO0		12
+#define R8A7794_CLK_RCAN1		15
+#define R8A7794_CLK_RCAN0		16
+#define R8A7794_CLK_QSPI_MOD		17
+#define R8A7794_CLK_I2C5		25
+#define R8A7794_CLK_I2C4		27
+#define R8A7794_CLK_I2C3		28
+#define R8A7794_CLK_I2C2		29
+#define R8A7794_CLK_I2C1		30
+#define R8A7794_CLK_I2C0		31
+
+/* MSTP10 */
+#define R8A7794_CLK_SSI_ALL		5
+#define R8A7794_CLK_SSI9		6
+#define R8A7794_CLK_SSI8		7
+#define R8A7794_CLK_SSI7		8
+#define R8A7794_CLK_SSI6		9
+#define R8A7794_CLK_SSI5		10
+#define R8A7794_CLK_SSI4		11
+#define R8A7794_CLK_SSI3		12
+#define R8A7794_CLK_SSI2		13
+#define R8A7794_CLK_SSI1		14
+#define R8A7794_CLK_SSI0		15
+#define R8A7794_CLK_SCU_ALL		17
+#define R8A7794_CLK_SCU_DVC1		18
+#define R8A7794_CLK_SCU_DVC0		19
+#define R8A7794_CLK_SCU_CTU1_MIX1	20
+#define R8A7794_CLK_SCU_CTU0_MIX0	21
+#define R8A7794_CLK_SCU_SRC6		25
+#define R8A7794_CLK_SCU_SRC5		26
+#define R8A7794_CLK_SCU_SRC4		27
+#define R8A7794_CLK_SCU_SRC3		28
+#define R8A7794_CLK_SCU_SRC2		29
+#define R8A7794_CLK_SCU_SRC1		30
+
+/* MSTP11 */
+#define R8A7794_CLK_SCIFA3		6
+#define R8A7794_CLK_SCIFA4		7
+#define R8A7794_CLK_SCIFA5		8
+
+#endif /* __DT_BINDINGS_CLOCK_R8A7794_H__ */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/r8a7794-cpg-mssr.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/r8a7794-cpg-mssr.h
new file mode 100644
index 0000000000000000000000000000000000000000..9d720311ae3a229a324febbeeaf698f0ec977c5c
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/r8a7794-cpg-mssr.h
@@ -0,0 +1,47 @@
+/*
+ * Copyright (C) 2015 Renesas Electronics Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_R8A7794_CPG_MSSR_H__
+#define __DT_BINDINGS_CLOCK_R8A7794_CPG_MSSR_H__
+
+#include <dt-bindings/clock/renesas-cpg-mssr.h>
+
+/* r8a7794 CPG Core Clocks */
+#define R8A7794_CLK_Z2			0
+#define R8A7794_CLK_ZG			1
+#define R8A7794_CLK_ZTR			2
+#define R8A7794_CLK_ZTRD2		3
+#define R8A7794_CLK_ZT			4
+#define R8A7794_CLK_ZX			5
+#define R8A7794_CLK_ZS			6
+#define R8A7794_CLK_HP			7
+#define R8A7794_CLK_I			8
+#define R8A7794_CLK_B			9
+#define R8A7794_CLK_LB			10
+#define R8A7794_CLK_P			11
+#define R8A7794_CLK_CL			12
+#define R8A7794_CLK_CP			13
+#define R8A7794_CLK_M2			14
+#define R8A7794_CLK_ADSP		15
+#define R8A7794_CLK_ZB3			16
+#define R8A7794_CLK_ZB3D2		17
+#define R8A7794_CLK_DDR			18
+#define R8A7794_CLK_SDH			19
+#define R8A7794_CLK_SD0			20
+#define R8A7794_CLK_SD2			21
+#define R8A7794_CLK_SD3			22
+#define R8A7794_CLK_MMC0		23
+#define R8A7794_CLK_MP			24
+#define R8A7794_CLK_QSPI		25
+#define R8A7794_CLK_CPEX		26
+#define R8A7794_CLK_RCAN		27
+#define R8A7794_CLK_R			28
+#define R8A7794_CLK_OSC			29
+
+#endif /* __DT_BINDINGS_CLOCK_R8A7794_CPG_MSSR_H__ */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/r8a7795-cpg-mssr.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/r8a7795-cpg-mssr.h
new file mode 100644
index 0000000000000000000000000000000000000000..f047eaf261f34ac783b2187997894daffe552572
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/r8a7795-cpg-mssr.h
@@ -0,0 +1,70 @@
+/*
+ * Copyright (C) 2015 Renesas Electronics Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#ifndef __DT_BINDINGS_CLOCK_R8A7795_CPG_MSSR_H__
+#define __DT_BINDINGS_CLOCK_R8A7795_CPG_MSSR_H__
+
+#include <dt-bindings/clock/renesas-cpg-mssr.h>
+
+/* r8a7795 CPG Core Clocks */
+#define R8A7795_CLK_Z			0
+#define R8A7795_CLK_Z2			1
+#define R8A7795_CLK_ZR			2
+#define R8A7795_CLK_ZG			3
+#define R8A7795_CLK_ZTR			4
+#define R8A7795_CLK_ZTRD2		5
+#define R8A7795_CLK_ZT			6
+#define R8A7795_CLK_ZX			7
+#define R8A7795_CLK_S0D1		8
+#define R8A7795_CLK_S0D4		9
+#define R8A7795_CLK_S1D1		10
+#define R8A7795_CLK_S1D2		11
+#define R8A7795_CLK_S1D4		12
+#define R8A7795_CLK_S2D1		13
+#define R8A7795_CLK_S2D2		14
+#define R8A7795_CLK_S2D4		15
+#define R8A7795_CLK_S3D1		16
+#define R8A7795_CLK_S3D2		17
+#define R8A7795_CLK_S3D4		18
+#define R8A7795_CLK_LB			19
+#define R8A7795_CLK_CL			20
+#define R8A7795_CLK_ZB3			21
+#define R8A7795_CLK_ZB3D2		22
+#define R8A7795_CLK_CR			23
+#define R8A7795_CLK_CRD2		24
+#define R8A7795_CLK_SD0H		25
+#define R8A7795_CLK_SD0			26
+#define R8A7795_CLK_SD1H		27
+#define R8A7795_CLK_SD1			28
+#define R8A7795_CLK_SD2H		29
+#define R8A7795_CLK_SD2			30
+#define R8A7795_CLK_SD3H		31
+#define R8A7795_CLK_SD3			32
+#define R8A7795_CLK_SSP2		33
+#define R8A7795_CLK_SSP1		34
+#define R8A7795_CLK_SSPRS		35
+#define R8A7795_CLK_RPC			36
+#define R8A7795_CLK_RPCD2		37
+#define R8A7795_CLK_MSO			38
+#define R8A7795_CLK_CANFD		39
+#define R8A7795_CLK_HDMI		40
+#define R8A7795_CLK_CSI0		41
+#define R8A7795_CLK_CSIREF		42
+#define R8A7795_CLK_CP			43
+#define R8A7795_CLK_CPEX		44
+#define R8A7795_CLK_R			45
+#define R8A7795_CLK_OSC			46
+
+/* r8a7795 ES2.0 CPG Core Clocks */
+#define R8A7795_CLK_S0D2		47
+#define R8A7795_CLK_S0D3		48
+#define R8A7795_CLK_S0D6		49
+#define R8A7795_CLK_S0D8		50
+#define R8A7795_CLK_S0D12		51
+
+#endif /* __DT_BINDINGS_CLOCK_R8A7795_CPG_MSSR_H__ */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/r8a7796-cpg-mssr.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/r8a7796-cpg-mssr.h
new file mode 100644
index 0000000000000000000000000000000000000000..1e5942695f0dd057e0e3976824e0205b357eb6b9
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/r8a7796-cpg-mssr.h
@@ -0,0 +1,69 @@
+/*
+ * Copyright (C) 2016 Renesas Electronics Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#ifndef __DT_BINDINGS_CLOCK_R8A7796_CPG_MSSR_H__
+#define __DT_BINDINGS_CLOCK_R8A7796_CPG_MSSR_H__
+
+#include <dt-bindings/clock/renesas-cpg-mssr.h>
+
+/* r8a7796 CPG Core Clocks */
+#define R8A7796_CLK_Z			0
+#define R8A7796_CLK_Z2			1
+#define R8A7796_CLK_ZR			2
+#define R8A7796_CLK_ZG			3
+#define R8A7796_CLK_ZTR			4
+#define R8A7796_CLK_ZTRD2		5
+#define R8A7796_CLK_ZT			6
+#define R8A7796_CLK_ZX			7
+#define R8A7796_CLK_S0D1		8
+#define R8A7796_CLK_S0D2		9
+#define R8A7796_CLK_S0D3		10
+#define R8A7796_CLK_S0D4		11
+#define R8A7796_CLK_S0D6		12
+#define R8A7796_CLK_S0D8		13
+#define R8A7796_CLK_S0D12		14
+#define R8A7796_CLK_S1D1		15
+#define R8A7796_CLK_S1D2		16
+#define R8A7796_CLK_S1D4		17
+#define R8A7796_CLK_S2D1		18
+#define R8A7796_CLK_S2D2		19
+#define R8A7796_CLK_S2D4		20
+#define R8A7796_CLK_S3D1		21
+#define R8A7796_CLK_S3D2		22
+#define R8A7796_CLK_S3D4		23
+#define R8A7796_CLK_LB			24
+#define R8A7796_CLK_CL			25
+#define R8A7796_CLK_ZB3			26
+#define R8A7796_CLK_ZB3D2		27
+#define R8A7796_CLK_ZB3D4		28
+#define R8A7796_CLK_CR			29
+#define R8A7796_CLK_CRD2		30
+#define R8A7796_CLK_SD0H		31
+#define R8A7796_CLK_SD0			32
+#define R8A7796_CLK_SD1H		33
+#define R8A7796_CLK_SD1			34
+#define R8A7796_CLK_SD2H		35
+#define R8A7796_CLK_SD2			36
+#define R8A7796_CLK_SD3H		37
+#define R8A7796_CLK_SD3			38
+#define R8A7796_CLK_SSP2		39
+#define R8A7796_CLK_SSP1		40
+#define R8A7796_CLK_SSPRS		41
+#define R8A7796_CLK_RPC			42
+#define R8A7796_CLK_RPCD2		43
+#define R8A7796_CLK_MSO			44
+#define R8A7796_CLK_CANFD		45
+#define R8A7796_CLK_HDMI		46
+#define R8A7796_CLK_CSI0		47
+#define R8A7796_CLK_CSIREF		48
+#define R8A7796_CLK_CP			49
+#define R8A7796_CLK_CPEX		50
+#define R8A7796_CLK_R			51
+#define R8A7796_CLK_OSC			52
+
+#endif /* __DT_BINDINGS_CLOCK_R8A7796_CPG_MSSR_H__ */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/r8a77965-cpg-mssr.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/r8a77965-cpg-mssr.h
new file mode 100644
index 0000000000000000000000000000000000000000..6d3b5a9a60840e9a553ea9bbfd410735fb7d4ece
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/r8a77965-cpg-mssr.h
@@ -0,0 +1,62 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2018 Jacopo Mondi <jacopo+renesas@jmondi.org>
+ */
+#ifndef __DT_BINDINGS_CLOCK_R8A77965_CPG_MSSR_H__
+#define __DT_BINDINGS_CLOCK_R8A77965_CPG_MSSR_H__
+
+#include <dt-bindings/clock/renesas-cpg-mssr.h>
+
+/* r8a77965 CPG Core Clocks */
+#define R8A77965_CLK_Z			0
+#define R8A77965_CLK_ZR			1
+#define R8A77965_CLK_ZG			2
+#define R8A77965_CLK_ZTR		3
+#define R8A77965_CLK_ZTRD2		4
+#define R8A77965_CLK_ZT			5
+#define R8A77965_CLK_ZX			6
+#define R8A77965_CLK_S0D1		7
+#define R8A77965_CLK_S0D2		8
+#define R8A77965_CLK_S0D3		9
+#define R8A77965_CLK_S0D4		10
+#define R8A77965_CLK_S0D6		11
+#define R8A77965_CLK_S0D8		12
+#define R8A77965_CLK_S0D12		13
+#define R8A77965_CLK_S1D1		14
+#define R8A77965_CLK_S1D2		15
+#define R8A77965_CLK_S1D4		16
+#define R8A77965_CLK_S2D1		17
+#define R8A77965_CLK_S2D2		18
+#define R8A77965_CLK_S2D4		19
+#define R8A77965_CLK_S3D1		20
+#define R8A77965_CLK_S3D2		21
+#define R8A77965_CLK_S3D4		22
+#define R8A77965_CLK_LB			23
+#define R8A77965_CLK_CL			24
+#define R8A77965_CLK_ZB3		25
+#define R8A77965_CLK_ZB3D2		26
+#define R8A77965_CLK_CR			27
+#define R8A77965_CLK_CRD2		28
+#define R8A77965_CLK_SD0H		29
+#define R8A77965_CLK_SD0		30
+#define R8A77965_CLK_SD1H		31
+#define R8A77965_CLK_SD1		32
+#define R8A77965_CLK_SD2H		33
+#define R8A77965_CLK_SD2		34
+#define R8A77965_CLK_SD3H		35
+#define R8A77965_CLK_SD3		36
+#define R8A77965_CLK_SSP2		37
+#define R8A77965_CLK_SSP1		38
+#define R8A77965_CLK_SSPRS		39
+#define R8A77965_CLK_RPC		40
+#define R8A77965_CLK_RPCD2		41
+#define R8A77965_CLK_MSO		42
+#define R8A77965_CLK_CANFD		43
+#define R8A77965_CLK_HDMI		44
+#define R8A77965_CLK_CSI0		45
+#define R8A77965_CLK_CP			46
+#define R8A77965_CLK_CPEX		47
+#define R8A77965_CLK_R			48
+#define R8A77965_CLK_OSC		49
+
+#endif /* __DT_BINDINGS_CLOCK_R8A77965_CPG_MSSR_H__ */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/r8a77970-cpg-mssr.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/r8a77970-cpg-mssr.h
new file mode 100644
index 0000000000000000000000000000000000000000..4146395595b10bda7a255d7c309ec17b29dc552b
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/r8a77970-cpg-mssr.h
@@ -0,0 +1,48 @@
+/*
+ * Copyright (C) 2016 Renesas Electronics Corp.
+ * Copyright (C) 2017 Cogent Embedded, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#ifndef __DT_BINDINGS_CLOCK_R8A77970_CPG_MSSR_H__
+#define __DT_BINDINGS_CLOCK_R8A77970_CPG_MSSR_H__
+
+#include <dt-bindings/clock/renesas-cpg-mssr.h>
+
+/* r8a77970 CPG Core Clocks */
+#define R8A77970_CLK_Z2			0
+#define R8A77970_CLK_ZR			1
+#define R8A77970_CLK_ZTR		2
+#define R8A77970_CLK_ZTRD2		3
+#define R8A77970_CLK_ZT			4
+#define R8A77970_CLK_ZX			5
+#define R8A77970_CLK_S1D1		6
+#define R8A77970_CLK_S1D2		7
+#define R8A77970_CLK_S1D4		8
+#define R8A77970_CLK_S2D1		9
+#define R8A77970_CLK_S2D2		10
+#define R8A77970_CLK_S2D4		11
+#define R8A77970_CLK_LB			12
+#define R8A77970_CLK_CL			13
+#define R8A77970_CLK_ZB3		14
+#define R8A77970_CLK_ZB3D2		15
+#define R8A77970_CLK_DDR		16
+#define R8A77970_CLK_CR			17
+#define R8A77970_CLK_CRD2		18
+#define R8A77970_CLK_SD0H		19
+#define R8A77970_CLK_SD0		20
+#define R8A77970_CLK_RPC		21
+#define R8A77970_CLK_RPCD2		22
+#define R8A77970_CLK_MSO		23
+#define R8A77970_CLK_CANFD		24
+#define R8A77970_CLK_CSI0		25
+#define R8A77970_CLK_FRAY		26
+#define R8A77970_CLK_CP			27
+#define R8A77970_CLK_CPEX		28
+#define R8A77970_CLK_R			29
+#define R8A77970_CLK_OSC		30
+
+#endif /* __DT_BINDINGS_CLOCK_R8A77970_CPG_MSSR_H__ */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/r8a77980-cpg-mssr.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/r8a77980-cpg-mssr.h
new file mode 100644
index 0000000000000000000000000000000000000000..a4c0d76c392e0124ebd2bc7a2735cbf38a434727
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/r8a77980-cpg-mssr.h
@@ -0,0 +1,51 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2018 Renesas Electronics Corp.
+ * Copyright (C) 2018 Cogent Embedded, Inc.
+ */
+#ifndef __DT_BINDINGS_CLOCK_R8A77980_CPG_MSSR_H__
+#define __DT_BINDINGS_CLOCK_R8A77980_CPG_MSSR_H__
+
+#include <dt-bindings/clock/renesas-cpg-mssr.h>
+
+/* r8a77980 CPG Core Clocks */
+#define R8A77980_CLK_Z2			0
+#define R8A77980_CLK_ZR			1
+#define R8A77980_CLK_ZTR		2
+#define R8A77980_CLK_ZTRD2		3
+#define R8A77980_CLK_ZT			4
+#define R8A77980_CLK_ZX			5
+#define R8A77980_CLK_S0D1		6
+#define R8A77980_CLK_S0D2		7
+#define R8A77980_CLK_S0D3		8
+#define R8A77980_CLK_S0D4		9
+#define R8A77980_CLK_S0D6		10
+#define R8A77980_CLK_S0D12		11
+#define R8A77980_CLK_S0D24		12
+#define R8A77980_CLK_S1D1		13
+#define R8A77980_CLK_S1D2		14
+#define R8A77980_CLK_S1D4		15
+#define R8A77980_CLK_S2D1		16
+#define R8A77980_CLK_S2D2		17
+#define R8A77980_CLK_S2D4		18
+#define R8A77980_CLK_S3D1		19
+#define R8A77980_CLK_S3D2		20
+#define R8A77980_CLK_S3D4		21
+#define R8A77980_CLK_LB			22
+#define R8A77980_CLK_CL			23
+#define R8A77980_CLK_ZB3		24
+#define R8A77980_CLK_ZB3D2		25
+#define R8A77980_CLK_ZB3D4		26
+#define R8A77980_CLK_SD0H		27
+#define R8A77980_CLK_SD0		28
+#define R8A77980_CLK_RPC		29
+#define R8A77980_CLK_RPCD2		30
+#define R8A77980_CLK_MSO		31
+#define R8A77980_CLK_CANFD		32
+#define R8A77980_CLK_CSI0		33
+#define R8A77980_CLK_CP			34
+#define R8A77980_CLK_CPEX		35
+#define R8A77980_CLK_R			36
+#define R8A77980_CLK_OSC		37
+
+#endif /* __DT_BINDINGS_CLOCK_R8A77980_CPG_MSSR_H__ */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/r8a77990-cpg-mssr.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/r8a77990-cpg-mssr.h
new file mode 100644
index 0000000000000000000000000000000000000000..a596a482f3a9bc10f1b5fc04a96b3902a7ac01d1
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/r8a77990-cpg-mssr.h
@@ -0,0 +1,62 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2018 Renesas Electronics Corp.
+ */
+#ifndef __DT_BINDINGS_CLOCK_R8A77990_CPG_MSSR_H__
+#define __DT_BINDINGS_CLOCK_R8A77990_CPG_MSSR_H__
+
+#include <dt-bindings/clock/renesas-cpg-mssr.h>
+
+/* r8a77990 CPG Core Clocks */
+#define R8A77990_CLK_Z2			0
+#define R8A77990_CLK_ZR			1
+#define R8A77990_CLK_ZG			2
+#define R8A77990_CLK_ZTR		3
+#define R8A77990_CLK_ZT			4
+#define R8A77990_CLK_ZX			5
+#define R8A77990_CLK_S0D1		6
+#define R8A77990_CLK_S0D3		7
+#define R8A77990_CLK_S0D6		8
+#define R8A77990_CLK_S0D12		9
+#define R8A77990_CLK_S0D24		10
+#define R8A77990_CLK_S1D1		11
+#define R8A77990_CLK_S1D2		12
+#define R8A77990_CLK_S1D4		13
+#define R8A77990_CLK_S2D1		14
+#define R8A77990_CLK_S2D2		15
+#define R8A77990_CLK_S2D4		16
+#define R8A77990_CLK_S3D1		17
+#define R8A77990_CLK_S3D2		18
+#define R8A77990_CLK_S3D4		19
+#define R8A77990_CLK_S0D6C		20
+#define R8A77990_CLK_S3D1C		21
+#define R8A77990_CLK_S3D2C		22
+#define R8A77990_CLK_S3D4C		23
+#define R8A77990_CLK_LB			24
+#define R8A77990_CLK_CL			25
+#define R8A77990_CLK_ZB3		26
+#define R8A77990_CLK_ZB3D2		27
+#define R8A77990_CLK_CR			28
+#define R8A77990_CLK_CRD2		29
+#define R8A77990_CLK_SD0H		30
+#define R8A77990_CLK_SD0		31
+#define R8A77990_CLK_SD1H		32
+#define R8A77990_CLK_SD1		33
+#define R8A77990_CLK_SD3H		34
+#define R8A77990_CLK_SD3		35
+#define R8A77990_CLK_RPC		36
+#define R8A77990_CLK_RPCD2		37
+#define R8A77990_CLK_ZA2		38
+#define R8A77990_CLK_ZA8		39
+#define R8A77990_CLK_Z2D		40
+#define R8A77990_CLK_CANFD		41
+#define R8A77990_CLK_MSO		42
+#define R8A77990_CLK_R			43
+#define R8A77990_CLK_OSC		44
+#define R8A77990_CLK_LV0		45
+#define R8A77990_CLK_LV1		46
+#define R8A77990_CLK_CSI0		47
+#define R8A77990_CLK_CP			48
+#define R8A77990_CLK_CPEX		49
+
+#endif /* __DT_BINDINGS_CLOCK_R8A77990_CPG_MSSR_H__ */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/r8a77995-cpg-mssr.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/r8a77995-cpg-mssr.h
new file mode 100644
index 0000000000000000000000000000000000000000..4e8ae3dee5901b01374e6fd609e7e988d4107676
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/r8a77995-cpg-mssr.h
@@ -0,0 +1,57 @@
+/*
+ * Copyright (C) 2017 Glider bvba
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#ifndef __DT_BINDINGS_CLOCK_R8A77995_CPG_MSSR_H__
+#define __DT_BINDINGS_CLOCK_R8A77995_CPG_MSSR_H__
+
+#include <dt-bindings/clock/renesas-cpg-mssr.h>
+
+/* r8a77995 CPG Core Clocks */
+#define R8A77995_CLK_Z2			0
+#define R8A77995_CLK_ZG			1
+#define R8A77995_CLK_ZTR		2
+#define R8A77995_CLK_ZT			3
+#define R8A77995_CLK_ZX			4
+#define R8A77995_CLK_S0D1		5
+#define R8A77995_CLK_S1D1		6
+#define R8A77995_CLK_S1D2		7
+#define R8A77995_CLK_S1D4		8
+#define R8A77995_CLK_S2D1		9
+#define R8A77995_CLK_S2D2		10
+#define R8A77995_CLK_S2D4		11
+#define R8A77995_CLK_S3D1		12
+#define R8A77995_CLK_S3D2		13
+#define R8A77995_CLK_S3D4		14
+#define R8A77995_CLK_S1D4C		15
+#define R8A77995_CLK_S3D1C		16
+#define R8A77995_CLK_S3D2C		17
+#define R8A77995_CLK_S3D4C		18
+#define R8A77995_CLK_LB			19
+#define R8A77995_CLK_CL			20
+#define R8A77995_CLK_ZB3		21
+#define R8A77995_CLK_ZB3D2		22
+#define R8A77995_CLK_CR			23
+#define R8A77995_CLK_CRD2		24
+#define R8A77995_CLK_SD0H		25
+#define R8A77995_CLK_SD0		26
+#define R8A77995_CLK_SSP2		27
+#define R8A77995_CLK_SSP1		28
+#define R8A77995_CLK_RPC		29
+#define R8A77995_CLK_RPCD2		30
+#define R8A77995_CLK_ZA2		31
+#define R8A77995_CLK_ZA8		32
+#define R8A77995_CLK_Z2D		33
+#define R8A77995_CLK_CANFD		34
+#define R8A77995_CLK_MSO		35
+#define R8A77995_CLK_R			36
+#define R8A77995_CLK_OSC		37
+#define R8A77995_CLK_LV0		38
+#define R8A77995_CLK_LV1		39
+#define R8A77995_CLK_CP			40
+
+#endif /* __DT_BINDINGS_CLOCK_R8A77995_CPG_MSSR_H__ */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/r9a06g032-sysctrl.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/r9a06g032-sysctrl.h
new file mode 100644
index 0000000000000000000000000000000000000000..90c0f3dc1ba19ff3ea97608650f4d3e6c3b51b3b
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/r9a06g032-sysctrl.h
@@ -0,0 +1,148 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * R9A06G032 sysctrl IDs
+ *
+ * Copyright (C) 2018 Renesas Electronics Europe Limited
+ *
+ * Michel Pollet <michel.pollet@bp.renesas.com>, <buserror@gmail.com>
+ */
+
+#ifndef __DT_BINDINGS_R9A06G032_SYSCTRL_H__
+#define __DT_BINDINGS_R9A06G032_SYSCTRL_H__
+
+#define R9A06G032_CLK_PLL_USB		1
+#define R9A06G032_CLK_48		1	/* AKA CLK_PLL_USB */
+#define R9A06G032_MSEBIS_CLK		3	/* AKA CLKOUT_D16 */
+#define R9A06G032_MSEBIM_CLK		3	/* AKA CLKOUT_D16 */
+#define R9A06G032_CLK_DDRPHY_PLLCLK	5	/* AKA CLKOUT_D1OR2 */
+#define R9A06G032_CLK50			6	/* AKA CLKOUT_D20 */
+#define R9A06G032_CLK25			7	/* AKA CLKOUT_D40 */
+#define R9A06G032_CLK125		9	/* AKA CLKOUT_D8 */
+#define R9A06G032_CLK_P5_PG1		17	/* AKA DIV_P5_PG */
+#define R9A06G032_CLK_REF_SYNC		21	/* AKA DIV_REF_SYNC */
+#define R9A06G032_CLK_25_PG4		26
+#define R9A06G032_CLK_25_PG5		27
+#define R9A06G032_CLK_25_PG6		28
+#define R9A06G032_CLK_25_PG7		29
+#define R9A06G032_CLK_25_PG8		30
+#define R9A06G032_CLK_ADC		31
+#define R9A06G032_CLK_ECAT100		32
+#define R9A06G032_CLK_HSR100		33
+#define R9A06G032_CLK_I2C0		34
+#define R9A06G032_CLK_I2C1		35
+#define R9A06G032_CLK_MII_REF		36
+#define R9A06G032_CLK_NAND		37
+#define R9A06G032_CLK_NOUSBP2_PG6	38
+#define R9A06G032_CLK_P1_PG2		39
+#define R9A06G032_CLK_P1_PG3		40
+#define R9A06G032_CLK_P1_PG4		41
+#define R9A06G032_CLK_P4_PG3		42
+#define R9A06G032_CLK_P4_PG4		43
+#define R9A06G032_CLK_P6_PG1		44
+#define R9A06G032_CLK_P6_PG2		45
+#define R9A06G032_CLK_P6_PG3		46
+#define R9A06G032_CLK_P6_PG4		47
+#define R9A06G032_CLK_PCI_USB		48
+#define R9A06G032_CLK_QSPI0		49
+#define R9A06G032_CLK_QSPI1		50
+#define R9A06G032_CLK_RGMII_REF		51
+#define R9A06G032_CLK_RMII_REF		52
+#define R9A06G032_CLK_SDIO0		53
+#define R9A06G032_CLK_SDIO1		54
+#define R9A06G032_CLK_SERCOS100		55
+#define R9A06G032_CLK_SLCD		56
+#define R9A06G032_CLK_SPI0		57
+#define R9A06G032_CLK_SPI1		58
+#define R9A06G032_CLK_SPI2		59
+#define R9A06G032_CLK_SPI3		60
+#define R9A06G032_CLK_SPI4		61
+#define R9A06G032_CLK_SPI5		62
+#define R9A06G032_CLK_SWITCH		63
+#define R9A06G032_HCLK_ECAT125		65
+#define R9A06G032_HCLK_PINCONFIG	66
+#define R9A06G032_HCLK_SERCOS		67
+#define R9A06G032_HCLK_SGPIO2		68
+#define R9A06G032_HCLK_SGPIO3		69
+#define R9A06G032_HCLK_SGPIO4		70
+#define R9A06G032_HCLK_TIMER0		71
+#define R9A06G032_HCLK_TIMER1		72
+#define R9A06G032_HCLK_USBF		73
+#define R9A06G032_HCLK_USBH		74
+#define R9A06G032_HCLK_USBPM		75
+#define R9A06G032_CLK_48_PG_F		76
+#define R9A06G032_CLK_48_PG4		77
+#define R9A06G032_CLK_DDRPHY_PCLK	81	/* AKA CLK_REF_SYNC_D4 */
+#define R9A06G032_CLK_FW		81	/* AKA CLK_REF_SYNC_D4 */
+#define R9A06G032_CLK_CRYPTO		81	/* AKA CLK_REF_SYNC_D4 */
+#define R9A06G032_CLK_A7MP		84	/* AKA DIV_CA7 */
+#define R9A06G032_HCLK_CAN0		85
+#define R9A06G032_HCLK_CAN1		86
+#define R9A06G032_HCLK_DELTASIGMA	87
+#define R9A06G032_HCLK_PWMPTO		88
+#define R9A06G032_HCLK_RSV		89
+#define R9A06G032_HCLK_SGPIO0		90
+#define R9A06G032_HCLK_SGPIO1		91
+#define R9A06G032_RTOS_MDC		92
+#define R9A06G032_CLK_CM3		93
+#define R9A06G032_CLK_DDRC		94
+#define R9A06G032_CLK_ECAT25		95
+#define R9A06G032_CLK_HSR50		96
+#define R9A06G032_CLK_HW_RTOS		97
+#define R9A06G032_CLK_SERCOS50		98
+#define R9A06G032_HCLK_ADC		99
+#define R9A06G032_HCLK_CM3		100
+#define R9A06G032_HCLK_CRYPTO_EIP150	101
+#define R9A06G032_HCLK_CRYPTO_EIP93	102
+#define R9A06G032_HCLK_DDRC		103
+#define R9A06G032_HCLK_DMA0		104
+#define R9A06G032_HCLK_DMA1		105
+#define R9A06G032_HCLK_GMAC0		106
+#define R9A06G032_HCLK_GMAC1		107
+#define R9A06G032_HCLK_GPIO0		108
+#define R9A06G032_HCLK_GPIO1		109
+#define R9A06G032_HCLK_GPIO2		110
+#define R9A06G032_HCLK_HSR		111
+#define R9A06G032_HCLK_I2C0		112
+#define R9A06G032_HCLK_I2C1		113
+#define R9A06G032_HCLK_LCD		114
+#define R9A06G032_HCLK_MSEBI_M		115
+#define R9A06G032_HCLK_MSEBI_S		116
+#define R9A06G032_HCLK_NAND		117
+#define R9A06G032_HCLK_PG_I		118
+#define R9A06G032_HCLK_PG19		119
+#define R9A06G032_HCLK_PG20		120
+#define R9A06G032_HCLK_PG3		121
+#define R9A06G032_HCLK_PG4		122
+#define R9A06G032_HCLK_QSPI0		123
+#define R9A06G032_HCLK_QSPI1		124
+#define R9A06G032_HCLK_ROM		125
+#define R9A06G032_HCLK_RTC		126
+#define R9A06G032_HCLK_SDIO0		127
+#define R9A06G032_HCLK_SDIO1		128
+#define R9A06G032_HCLK_SEMAP		129
+#define R9A06G032_HCLK_SPI0		130
+#define R9A06G032_HCLK_SPI1		131
+#define R9A06G032_HCLK_SPI2		132
+#define R9A06G032_HCLK_SPI3		133
+#define R9A06G032_HCLK_SPI4		134
+#define R9A06G032_HCLK_SPI5		135
+#define R9A06G032_HCLK_SWITCH		136
+#define R9A06G032_HCLK_SWITCH_RG	137
+#define R9A06G032_HCLK_UART0		138
+#define R9A06G032_HCLK_UART1		139
+#define R9A06G032_HCLK_UART2		140
+#define R9A06G032_HCLK_UART3		141
+#define R9A06G032_HCLK_UART4		142
+#define R9A06G032_HCLK_UART5		143
+#define R9A06G032_HCLK_UART6		144
+#define R9A06G032_HCLK_UART7		145
+#define R9A06G032_CLK_UART0		146
+#define R9A06G032_CLK_UART1		147
+#define R9A06G032_CLK_UART2		148
+#define R9A06G032_CLK_UART3		149
+#define R9A06G032_CLK_UART4		150
+#define R9A06G032_CLK_UART5		151
+#define R9A06G032_CLK_UART6		152
+#define R9A06G032_CLK_UART7		153
+
+#endif /* __DT_BINDINGS_R9A06G032_SYSCTRL_H__ */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/renesas-cpg-mssr.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/renesas-cpg-mssr.h
new file mode 100644
index 0000000000000000000000000000000000000000..569a3cc33ffb5bc7ed35cc2bd1948a8651d2e62a
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/renesas-cpg-mssr.h
@@ -0,0 +1,15 @@
+/*
+ * Copyright (C) 2015 Renesas Electronics Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#ifndef __DT_BINDINGS_CLOCK_RENESAS_CPG_MSSR_H__
+#define __DT_BINDINGS_CLOCK_RENESAS_CPG_MSSR_H__
+
+#define CPG_CORE			0	/* Core Clock */
+#define CPG_MOD				1	/* Module Clock */
+
+#endif /* __DT_BINDINGS_CLOCK_RENESAS_CPG_MSSR_H__ */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/rk3036-cru.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/rk3036-cru.h
new file mode 100644
index 0000000000000000000000000000000000000000..de44109a3a0429cc92785a38663c651cd3b0e99e
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/rk3036-cru.h
@@ -0,0 +1,195 @@
+/*
+ * Copyright (c) 2015 Rockchip Electronics Co. Ltd.
+ * Author: Xing Zheng <zhengxing@rock-chips.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3036_H
+#define _DT_BINDINGS_CLK_ROCKCHIP_RK3036_H
+
+/* core clocks */
+#define PLL_APLL		1
+#define PLL_DPLL		2
+#define PLL_GPLL		3
+#define ARMCLK			4
+
+/* sclk gates (special clocks) */
+#define SCLK_GPU		64
+#define SCLK_SPI		65
+#define SCLK_SDMMC		68
+#define SCLK_SDIO		69
+#define SCLK_EMMC		71
+#define SCLK_NANDC		76
+#define SCLK_UART0		77
+#define SCLK_UART1		78
+#define SCLK_UART2		79
+#define SCLK_I2S		82
+#define SCLK_SPDIF		83
+#define SCLK_TIMER0		85
+#define SCLK_TIMER1		86
+#define SCLK_TIMER2		87
+#define SCLK_TIMER3		88
+#define SCLK_OTGPHY0		93
+#define SCLK_LCDC		100
+#define SCLK_HDMI		109
+#define SCLK_HEVC		111
+#define SCLK_I2S_OUT		113
+#define SCLK_SDMMC_DRV		114
+#define SCLK_SDIO_DRV		115
+#define SCLK_EMMC_DRV		117
+#define SCLK_SDMMC_SAMPLE	118
+#define SCLK_SDIO_SAMPLE	119
+#define SCLK_EMMC_SAMPLE	121
+#define SCLK_PVTM_CORE		123
+#define SCLK_PVTM_GPU		124
+#define SCLK_PVTM_VIDEO		125
+#define SCLK_MAC		151
+#define SCLK_MACREF		152
+#define SCLK_MACPLL		153
+#define SCLK_SFC		160
+
+/* aclk gates */
+#define ACLK_DMAC2		194
+#define ACLK_LCDC		197
+#define ACLK_VIO		203
+#define ACLK_VCODEC		208
+#define ACLK_CPU		209
+#define ACLK_PERI		210
+
+/* pclk gates */
+#define PCLK_GPIO0		320
+#define PCLK_GPIO1		321
+#define PCLK_GPIO2		322
+#define PCLK_GRF		329
+#define PCLK_I2C0		332
+#define PCLK_I2C1		333
+#define PCLK_I2C2		334
+#define PCLK_SPI		338
+#define PCLK_UART0		341
+#define PCLK_UART1		342
+#define PCLK_UART2		343
+#define PCLK_PWM		350
+#define PCLK_TIMER		353
+#define PCLK_HDMI		360
+#define PCLK_CPU		362
+#define PCLK_PERI		363
+#define PCLK_DDRUPCTL		364
+#define PCLK_WDT		368
+#define PCLK_ACODEC		369
+
+/* hclk gates */
+#define HCLK_OTG0		449
+#define HCLK_OTG1		450
+#define HCLK_NANDC		453
+#define HCLK_SDMMC		456
+#define HCLK_SDIO		457
+#define HCLK_EMMC		459
+#define HCLK_MAC		460
+#define HCLK_I2S		462
+#define HCLK_LCDC		465
+#define HCLK_ROM		467
+#define HCLK_VIO_BUS		472
+#define HCLK_VCODEC		476
+#define HCLK_CPU		477
+#define HCLK_PERI		478
+
+#define CLK_NR_CLKS		(HCLK_PERI + 1)
+
+/* soft-reset indices */
+#define SRST_CORE0		0
+#define SRST_CORE1		1
+#define SRST_CORE0_DBG		4
+#define SRST_CORE1_DBG		5
+#define SRST_CORE0_POR		8
+#define SRST_CORE1_POR		9
+#define SRST_L2C		12
+#define SRST_TOPDBG		13
+#define SRST_STRC_SYS_A		14
+#define SRST_PD_CORE_NIU	15
+
+#define SRST_TIMER2		16
+#define SRST_CPUSYS_H		17
+#define SRST_AHB2APB_H		19
+#define SRST_TIMER3		20
+#define SRST_INTMEM		21
+#define SRST_ROM		22
+#define SRST_PERI_NIU		23
+#define SRST_I2S		24
+#define SRST_DDR_PLL		25
+#define SRST_GPU_DLL		26
+#define SRST_TIMER0		27
+#define SRST_TIMER1		28
+#define SRST_CORE_DLL		29
+#define SRST_EFUSE_P		30
+#define SRST_ACODEC_P		31
+
+#define SRST_GPIO0		32
+#define SRST_GPIO1		33
+#define SRST_GPIO2		34
+#define SRST_UART0		39
+#define SRST_UART1		40
+#define SRST_UART2		41
+#define SRST_I2C0		43
+#define SRST_I2C1		44
+#define SRST_I2C2		45
+#define SRST_SFC		47
+
+#define SRST_PWM0		48
+#define SRST_DAP		51
+#define SRST_DAP_SYS		52
+#define SRST_GRF		55
+#define SRST_PERIPHSYS_A	57
+#define SRST_PERIPHSYS_H	58
+#define SRST_PERIPHSYS_P	59
+#define SRST_CPU_PERI		61
+#define SRST_EMEM_PERI		62
+#define SRST_USB_PERI		63
+
+#define SRST_DMA2		64
+#define SRST_MAC		66
+#define SRST_NANDC		68
+#define SRST_USBOTG0		69
+#define SRST_OTGC0		71
+#define SRST_USBOTG1		72
+#define SRST_OTGC1		74
+#define SRST_DDRMSCH		79
+
+#define SRST_MMC0		81
+#define SRST_SDIO		82
+#define SRST_EMMC		83
+#define SRST_SPI0		84
+#define SRST_WDT		86
+#define SRST_DDRPHY		88
+#define SRST_DDRPHY_P		89
+#define SRST_DDRCTRL		90
+#define SRST_DDRCTRL_P		91
+
+#define SRST_HDMI_P		96
+#define SRST_VIO_BUS_H		99
+#define SRST_UTMI0		103
+#define SRST_UTMI1		104
+#define SRST_USBPOR		105
+
+#define SRST_VCODEC_A		112
+#define SRST_VCODEC_H		113
+#define SRST_VIO1_A		114
+#define SRST_HEVC		115
+#define SRST_VCODEC_NIU_A	116
+#define SRST_LCDC1_A		117
+#define SRST_LCDC1_H		118
+#define SRST_LCDC1_D		119
+#define SRST_GPU		120
+#define SRST_GPU_NIU_A		122
+
+#define SRST_DBG_P		131
+
+#endif
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/rk3066a-cru.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/rk3066a-cru.h
new file mode 100644
index 0000000000000000000000000000000000000000..d3a9824ef6462d775405b38fa41f7b31740d7508
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/rk3066a-cru.h
@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2014 MundoReader S.L.
+ * Author: Heiko Stuebner <heiko@sntech.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3066A_H
+#define _DT_BINDINGS_CLK_ROCKCHIP_RK3066A_H
+
+#include <dt-bindings/clock/rk3188-cru-common.h>
+
+/* soft-reset indices */
+#define SRST_SRST1		0
+#define SRST_SRST2		1
+
+#define SRST_L2MEM		18
+#define SRST_I2S0		23
+#define SRST_I2S1		24
+#define SRST_I2S2		25
+#define SRST_TIMER2		29
+
+#define SRST_GPIO4		36
+#define SRST_GPIO6		38
+
+#define SRST_TSADC		92
+
+#define SRST_HDMI		96
+#define SRST_HDMI_APB		97
+#define SRST_CIF1		111
+
+#endif
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/rk3128-cru.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/rk3128-cru.h
new file mode 100644
index 0000000000000000000000000000000000000000..92894f4306cff1c8f4e417701c14a306b28f09f8
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/rk3128-cru.h
@@ -0,0 +1,282 @@
+/*
+ * Copyright (c) 2017 Rockchip Electronics Co. Ltd.
+ * Author: Elaine <zhangqing@rock-chips.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3128_H
+#define _DT_BINDINGS_CLK_ROCKCHIP_RK3128_H
+
+/* core clocks */
+#define PLL_APLL		1
+#define PLL_DPLL		2
+#define PLL_CPLL		3
+#define PLL_GPLL		4
+#define ARMCLK			5
+#define PLL_GPLL_DIV2		6
+#define PLL_GPLL_DIV3		7
+
+/* sclk gates (special clocks) */
+#define SCLK_SPI0		65
+#define SCLK_NANDC		67
+#define SCLK_SDMMC		68
+#define SCLK_SDIO		69
+#define SCLK_EMMC		71
+#define SCLK_UART0		77
+#define SCLK_UART1		78
+#define SCLK_UART2		79
+#define SCLK_I2S0		80
+#define SCLK_I2S1		81
+#define SCLK_SPDIF		83
+#define SCLK_TIMER0		85
+#define SCLK_TIMER1		86
+#define SCLK_TIMER2		87
+#define SCLK_TIMER3		88
+#define SCLK_TIMER4		89
+#define SCLK_TIMER5		90
+#define SCLK_SARADC		91
+#define SCLK_I2S_OUT		113
+#define SCLK_SDMMC_DRV		114
+#define SCLK_SDIO_DRV		115
+#define SCLK_EMMC_DRV		117
+#define SCLK_SDMMC_SAMPLE	118
+#define SCLK_SDIO_SAMPLE	119
+#define SCLK_EMMC_SAMPLE	121
+#define SCLK_VOP		122
+#define SCLK_MAC_SRC		124
+#define SCLK_MAC		126
+#define SCLK_MAC_REFOUT		127
+#define SCLK_MAC_REF		128
+#define SCLK_MAC_RX		129
+#define SCLK_MAC_TX		130
+#define SCLK_HEVC_CORE		134
+#define SCLK_RGA		135
+#define SCLK_CRYPTO		138
+#define SCLK_TSP		139
+#define SCLK_OTGPHY0		142
+#define SCLK_OTGPHY1		143
+#define SCLK_DDRC		144
+#define SCLK_PVTM_FUNC		145
+#define SCLK_PVTM_CORE		146
+#define SCLK_PVTM_GPU		147
+#define SCLK_MIPI_24M		148
+#define SCLK_PVTM		149
+#define SCLK_CIF_SRC		150
+#define SCLK_CIF_OUT_SRC	151
+#define SCLK_CIF_OUT		152
+#define SCLK_SFC		153
+#define SCLK_USB480M		154
+
+/* dclk gates */
+#define DCLK_VOP		190
+#define DCLK_EBC		191
+
+/* aclk gates */
+#define ACLK_VIO0		192
+#define ACLK_VIO1		193
+#define ACLK_DMAC		194
+#define ACLK_CPU		195
+#define ACLK_VEPU		196
+#define ACLK_VDPU		197
+#define ACLK_CIF		198
+#define ACLK_IEP		199
+#define ACLK_LCDC0		204
+#define ACLK_RGA		205
+#define ACLK_PERI		210
+#define ACLK_VOP		211
+#define ACLK_GMAC		212
+#define ACLK_GPU		213
+
+/* pclk gates */
+#define PCLK_SARADC		318
+#define PCLK_WDT		319
+#define PCLK_GPIO0		320
+#define PCLK_GPIO1		321
+#define PCLK_GPIO2		322
+#define PCLK_GPIO3		323
+#define PCLK_VIO_H2P		324
+#define PCLK_MIPI		325
+#define PCLK_EFUSE		326
+#define PCLK_HDMI		327
+#define PCLK_ACODEC		328
+#define PCLK_GRF		329
+#define PCLK_I2C0		332
+#define PCLK_I2C1		333
+#define PCLK_I2C2		334
+#define PCLK_I2C3		335
+#define PCLK_SPI0		338
+#define PCLK_UART0		341
+#define PCLK_UART1		342
+#define PCLK_UART2		343
+#define PCLK_TSADC		344
+#define PCLK_PWM		350
+#define PCLK_TIMER		353
+#define PCLK_CPU		354
+#define PCLK_PERI		363
+#define PCLK_GMAC		367
+#define PCLK_PMU_PRE		368
+#define PCLK_SIM_CARD		369
+
+/* hclk gates */
+#define HCLK_SPDIF		440
+#define HCLK_GPS		441
+#define HCLK_USBHOST		442
+#define HCLK_I2S_8CH		443
+#define HCLK_I2S_2CH		444
+#define HCLK_VOP		452
+#define HCLK_NANDC		453
+#define HCLK_SDMMC		456
+#define HCLK_SDIO		457
+#define HCLK_EMMC		459
+#define HCLK_CPU		460
+#define HCLK_VEPU		461
+#define HCLK_VDPU		462
+#define HCLK_LCDC0		463
+#define HCLK_EBC		465
+#define HCLK_VIO		466
+#define HCLK_RGA		467
+#define HCLK_IEP		468
+#define HCLK_VIO_H2P		469
+#define HCLK_CIF		470
+#define HCLK_HOST2		473
+#define HCLK_OTG		474
+#define HCLK_TSP		475
+#define HCLK_CRYPTO		476
+#define HCLK_PERI		478
+
+#define CLK_NR_CLKS		(HCLK_PERI + 1)
+
+/* soft-reset indices */
+#define SRST_CORE0_PO		0
+#define SRST_CORE1_PO		1
+#define SRST_CORE2_PO		2
+#define SRST_CORE3_PO		3
+#define SRST_CORE0		4
+#define SRST_CORE1		5
+#define SRST_CORE2		6
+#define SRST_CORE3		7
+#define SRST_CORE0_DBG		8
+#define SRST_CORE1_DBG		9
+#define SRST_CORE2_DBG		10
+#define SRST_CORE3_DBG		11
+#define SRST_TOPDBG		12
+#define SRST_ACLK_CORE		13
+#define SRST_STRC_SYS_A		14
+#define SRST_L2C		15
+
+#define SRST_CPUSYS_H		18
+#define SRST_AHB2APBSYS_H	19
+#define SRST_SPDIF		20
+#define SRST_INTMEM		21
+#define SRST_ROM		22
+#define SRST_PERI_NIU		23
+#define SRST_I2S_2CH		24
+#define SRST_I2S_8CH		25
+#define SRST_GPU_PVTM		26
+#define SRST_FUNC_PVTM		27
+#define SRST_CORE_PVTM		29
+#define SRST_EFUSE_P		30
+#define SRST_ACODEC_P		31
+
+#define SRST_GPIO0		32
+#define SRST_GPIO1		33
+#define SRST_GPIO2		34
+#define SRST_GPIO3		35
+#define SRST_MIPIPHY_P		36
+#define SRST_UART0		39
+#define SRST_UART1		40
+#define SRST_UART2		41
+#define SRST_I2C0		43
+#define SRST_I2C1		44
+#define SRST_I2C2		45
+#define SRST_I2C3		46
+#define SRST_SFC		47
+
+#define SRST_PWM		48
+#define SRST_DAP_PO		50
+#define SRST_DAP		51
+#define SRST_DAP_SYS		52
+#define SRST_CRYPTO		53
+#define SRST_GRF		55
+#define SRST_GMAC		56
+#define SRST_PERIPH_SYS_A	57
+#define SRST_PERIPH_SYS_H	58
+#define SRST_PERIPH_SYS_P       59
+#define SRST_SMART_CARD		60
+#define SRST_CPU_PERI		61
+#define SRST_EMEM_PERI		62
+#define SRST_USB_PERI		63
+
+#define SRST_DMA		64
+#define SRST_GPS		67
+#define SRST_NANDC		68
+#define SRST_USBOTG0		69
+#define SRST_OTGC0		71
+#define SRST_USBOTG1		72
+#define SRST_OTGC1		74
+#define SRST_DDRMSCH		79
+
+#define SRST_SDMMC		81
+#define SRST_SDIO		82
+#define SRST_EMMC		83
+#define SRST_SPI		84
+#define SRST_WDT		86
+#define SRST_SARADC		87
+#define SRST_DDRPHY		88
+#define SRST_DDRPHY_P		89
+#define SRST_DDRCTRL		90
+#define SRST_DDRCTRL_P		91
+#define SRST_TSP		92
+#define SRST_TSP_CLKIN		93
+#define SRST_HOST0_ECHI		94
+
+#define SRST_HDMI_P		96
+#define SRST_VIO_ARBI_H		97
+#define SRST_VIO0_A		98
+#define SRST_VIO_BUS_H		99
+#define SRST_VOP_A		100
+#define SRST_VOP_H		101
+#define SRST_VOP_D		102
+#define SRST_UTMI0		103
+#define SRST_UTMI1		104
+#define SRST_USBPOR		105
+#define SRST_IEP_A		106
+#define SRST_IEP_H		107
+#define SRST_RGA_A		108
+#define SRST_RGA_H		109
+#define SRST_CIF0		110
+#define SRST_PMU		111
+
+#define SRST_VCODEC_A		112
+#define SRST_VCODEC_H		113
+#define SRST_VIO1_A		114
+#define SRST_HEVC_CORE		115
+#define SRST_VCODEC_NIU_A	116
+#define SRST_PMU_NIU_P		117
+#define SRST_LCDC0_S		119
+#define SRST_GPU		120
+#define SRST_GPU_NIU_A		122
+#define SRST_EBC_A		123
+#define SRST_EBC_H		124
+
+#define SRST_CORE_DBG		128
+#define SRST_DBG_P		129
+#define SRST_TIMER0		130
+#define SRST_TIMER1		131
+#define SRST_TIMER2		132
+#define SRST_TIMER3		133
+#define SRST_TIMER4		134
+#define SRST_TIMER5		135
+#define SRST_VIO_H2P		136
+#define SRST_VIO_MIPI_DSI	137
+
+#endif
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/rk3188-cru-common.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/rk3188-cru-common.h
new file mode 100644
index 0000000000000000000000000000000000000000..b9462b7d3dfe67bf495431786d19f53b61f4a8cf
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/rk3188-cru-common.h
@@ -0,0 +1,269 @@
+/*
+ * Copyright (c) 2014 MundoReader S.L.
+ * Author: Heiko Stuebner <heiko@sntech.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3188_COMMON_H
+#define _DT_BINDINGS_CLK_ROCKCHIP_RK3188_COMMON_H
+
+/* core clocks from */
+#define PLL_APLL		1
+#define PLL_DPLL		2
+#define PLL_CPLL		3
+#define PLL_GPLL		4
+#define CORE_PERI		5
+#define CORE_L2C		6
+#define ARMCLK			7
+
+/* sclk gates (special clocks) */
+#define SCLK_UART0		64
+#define SCLK_UART1		65
+#define SCLK_UART2		66
+#define SCLK_UART3		67
+#define SCLK_MAC		68
+#define SCLK_SPI0		69
+#define SCLK_SPI1		70
+#define SCLK_SARADC		71
+#define SCLK_SDMMC		72
+#define SCLK_SDIO		73
+#define SCLK_EMMC		74
+#define SCLK_I2S0		75
+#define SCLK_I2S1		76
+#define SCLK_I2S2		77
+#define SCLK_SPDIF		78
+#define SCLK_CIF0		79
+#define SCLK_CIF1		80
+#define SCLK_OTGPHY0		81
+#define SCLK_OTGPHY1		82
+#define SCLK_HSADC		83
+#define SCLK_TIMER0		84
+#define SCLK_TIMER1		85
+#define SCLK_TIMER2		86
+#define SCLK_TIMER3		87
+#define SCLK_TIMER4		88
+#define SCLK_TIMER5		89
+#define SCLK_TIMER6		90
+#define SCLK_JTAG		91
+#define SCLK_SMC		92
+#define SCLK_TSADC		93
+
+#define DCLK_LCDC0		190
+#define DCLK_LCDC1		191
+
+/* aclk gates */
+#define ACLK_DMA1		192
+#define ACLK_DMA2		193
+#define ACLK_GPS		194
+#define ACLK_LCDC0		195
+#define ACLK_LCDC1		196
+#define ACLK_GPU		197
+#define ACLK_SMC		198
+#define ACLK_CIF1		199
+#define ACLK_IPP		200
+#define ACLK_RGA		201
+#define ACLK_CIF0		202
+#define ACLK_CPU		203
+#define ACLK_PERI		204
+#define ACLK_VEPU		205
+#define ACLK_VDPU		206
+
+/* pclk gates */
+#define PCLK_GRF		320
+#define PCLK_PMU		321
+#define PCLK_TIMER0		322
+#define PCLK_TIMER1		323
+#define PCLK_TIMER2		324
+#define PCLK_TIMER3		325
+#define PCLK_PWM01		326
+#define PCLK_PWM23		327
+#define PCLK_SPI0		328
+#define PCLK_SPI1		329
+#define PCLK_SARADC		330
+#define PCLK_WDT		331
+#define PCLK_UART0		332
+#define PCLK_UART1		333
+#define PCLK_UART2		334
+#define PCLK_UART3		335
+#define PCLK_I2C0		336
+#define PCLK_I2C1		337
+#define PCLK_I2C2		338
+#define PCLK_I2C3		339
+#define PCLK_I2C4		340
+#define PCLK_GPIO0		341
+#define PCLK_GPIO1		342
+#define PCLK_GPIO2		343
+#define PCLK_GPIO3		344
+#define PCLK_GPIO4		345
+#define PCLK_GPIO6		346
+#define PCLK_EFUSE		347
+#define PCLK_TZPC		348
+#define PCLK_TSADC		349
+#define PCLK_CPU		350
+#define PCLK_PERI		351
+#define PCLK_DDRUPCTL		352
+#define PCLK_PUBL		353
+
+/* hclk gates */
+#define HCLK_SDMMC		448
+#define HCLK_SDIO		449
+#define HCLK_EMMC		450
+#define HCLK_OTG0		451
+#define HCLK_EMAC		452
+#define HCLK_SPDIF		453
+#define HCLK_I2S0		454
+#define HCLK_I2S1		455
+#define HCLK_I2S2		456
+#define HCLK_OTG1		457
+#define HCLK_HSIC		458
+#define HCLK_HSADC		459
+#define HCLK_PIDF		460
+#define HCLK_LCDC0		461
+#define HCLK_LCDC1		462
+#define HCLK_ROM		463
+#define HCLK_CIF0		464
+#define HCLK_IPP		465
+#define HCLK_RGA		466
+#define HCLK_NANDC0		467
+#define HCLK_CPU		468
+#define HCLK_PERI		469
+#define HCLK_CIF1		470
+#define HCLK_VEPU		471
+#define HCLK_VDPU		472
+
+#define CLK_NR_CLKS		(HCLK_VDPU + 1)
+
+/* soft-reset indices */
+#define SRST_MCORE		2
+#define SRST_CORE0		3
+#define SRST_CORE1		4
+#define SRST_MCORE_DBG		7
+#define SRST_CORE0_DBG		8
+#define SRST_CORE1_DBG		9
+#define SRST_CORE0_WDT		12
+#define SRST_CORE1_WDT		13
+#define SRST_STRC_SYS		14
+#define SRST_L2C		15
+
+#define SRST_CPU_AHB		17
+#define SRST_AHB2APB		19
+#define SRST_DMA1		20
+#define SRST_INTMEM		21
+#define SRST_ROM		22
+#define SRST_SPDIF		26
+#define SRST_TIMER0		27
+#define SRST_TIMER1		28
+#define SRST_EFUSE		30
+
+#define SRST_GPIO0		32
+#define SRST_GPIO1		33
+#define SRST_GPIO2		34
+#define SRST_GPIO3		35
+
+#define SRST_UART0		39
+#define SRST_UART1		40
+#define SRST_UART2		41
+#define SRST_UART3		42
+#define SRST_I2C0		43
+#define SRST_I2C1		44
+#define SRST_I2C2		45
+#define SRST_I2C3		46
+#define SRST_I2C4		47
+
+#define SRST_PWM0		48
+#define SRST_PWM1		49
+#define SRST_DAP_PO		50
+#define SRST_DAP		51
+#define SRST_DAP_SYS		52
+#define SRST_TPIU_ATB		53
+#define SRST_PMU_APB		54
+#define SRST_GRF		55
+#define SRST_PMU		56
+#define SRST_PERI_AXI		57
+#define SRST_PERI_AHB		58
+#define SRST_PERI_APB		59
+#define SRST_PERI_NIU		60
+#define SRST_CPU_PERI		61
+#define SRST_EMEM_PERI		62
+#define SRST_USB_PERI		63
+
+#define SRST_DMA2		64
+#define SRST_SMC		65
+#define SRST_MAC		66
+#define SRST_NANC0		68
+#define SRST_USBOTG0		69
+#define SRST_USBPHY0		70
+#define SRST_OTGC0		71
+#define SRST_USBOTG1		72
+#define SRST_USBPHY1		73
+#define SRST_OTGC1		74
+#define SRST_HSADC		76
+#define SRST_PIDFILTER		77
+#define SRST_DDR_MSCH		79
+
+#define SRST_TZPC		80
+#define SRST_SDMMC		81
+#define SRST_SDIO		82
+#define SRST_EMMC		83
+#define SRST_SPI0		84
+#define SRST_SPI1		85
+#define SRST_WDT		86
+#define SRST_SARADC		87
+#define SRST_DDRPHY		88
+#define SRST_DDRPHY_APB		89
+#define SRST_DDRCTL		90
+#define SRST_DDRCTL_APB		91
+#define SRST_DDRPUB		93
+
+#define SRST_VIO0_AXI		98
+#define SRST_VIO0_AHB		99
+#define SRST_LCDC0_AXI		100
+#define SRST_LCDC0_AHB		101
+#define SRST_LCDC0_DCLK		102
+#define SRST_LCDC1_AXI		103
+#define SRST_LCDC1_AHB		104
+#define SRST_LCDC1_DCLK		105
+#define SRST_IPP_AXI		106
+#define SRST_IPP_AHB		107
+#define SRST_RGA_AXI		108
+#define SRST_RGA_AHB		109
+#define SRST_CIF0		110
+
+#define SRST_VCODEC_AXI		112
+#define SRST_VCODEC_AHB		113
+#define SRST_VIO1_AXI		114
+#define SRST_VCODEC_CPU		115
+#define SRST_VCODEC_NIU		116
+#define SRST_GPU		120
+#define SRST_GPU_NIU		122
+#define SRST_TFUN_ATB		125
+#define SRST_TFUN_APB		126
+#define SRST_CTI4_APB		127
+
+#define SRST_TPIU_APB		128
+#define SRST_TRACE		129
+#define SRST_CORE_DBG		130
+#define SRST_DBG_APB		131
+#define SRST_CTI0		132
+#define SRST_CTI0_APB		133
+#define SRST_CTI1		134
+#define SRST_CTI1_APB		135
+#define SRST_PTM_CORE0		136
+#define SRST_PTM_CORE1		137
+#define SRST_PTM0		138
+#define SRST_PTM0_ATB		139
+#define SRST_PTM1		140
+#define SRST_PTM1_ATB		141
+#define SRST_CTM		142
+#define SRST_TS			143
+
+#endif
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/rk3188-cru.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/rk3188-cru.h
new file mode 100644
index 0000000000000000000000000000000000000000..9f2e631f2651001327c7761d5c1fdc86cb4bf35b
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/rk3188-cru.h
@@ -0,0 +1,56 @@
+/*
+ * Copyright (c) 2014 MundoReader S.L.
+ * Author: Heiko Stuebner <heiko@sntech.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3188_H
+#define _DT_BINDINGS_CLK_ROCKCHIP_RK3188_H
+
+#include <dt-bindings/clock/rk3188-cru-common.h>
+
+/* soft-reset indices */
+#define SRST_PTM_CORE2		0
+#define SRST_PTM_CORE3		1
+#define SRST_CORE2		5
+#define SRST_CORE3		6
+#define SRST_CORE2_DBG		10
+#define SRST_CORE3_DBG		11
+
+#define SRST_TIMER2		16
+#define SRST_TIMER4		23
+#define SRST_I2S0		24
+#define SRST_TIMER5		25
+#define SRST_TIMER3		29
+#define SRST_TIMER6		31
+
+#define SRST_PTM3		36
+#define SRST_PTM3_ATB		37
+
+#define SRST_GPS		67
+#define SRST_HSICPHY		75
+#define SRST_TIMER		78
+
+#define SRST_PTM2		92
+#define SRST_CORE2_WDT		94
+#define SRST_CORE3_WDT		95
+
+#define SRST_PTM2_ATB		111
+
+#define SRST_HSIC		117
+#define SRST_CTI2		118
+#define SRST_CTI2_APB		119
+#define SRST_GPU_BRIDGE		121
+#define SRST_CTI3		123
+#define SRST_CTI3_APB		124
+
+#endif
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/rk3228-cru.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/rk3228-cru.h
new file mode 100644
index 0000000000000000000000000000000000000000..55655ab0a4c47a2c538f7e866409a5361be285f8
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/rk3228-cru.h
@@ -0,0 +1,295 @@
+/*
+ * Copyright (c) 2015 Rockchip Electronics Co. Ltd.
+ * Author: Jeffy Chen <jeffy.chen@rock-chips.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3228_H
+#define _DT_BINDINGS_CLK_ROCKCHIP_RK3228_H
+
+/* core clocks */
+#define PLL_APLL		1
+#define PLL_DPLL		2
+#define PLL_CPLL		3
+#define PLL_GPLL		4
+#define ARMCLK			5
+
+/* sclk gates (special clocks) */
+#define SCLK_SPI0		65
+#define SCLK_NANDC		67
+#define SCLK_SDMMC		68
+#define SCLK_SDIO		69
+#define SCLK_EMMC		71
+#define SCLK_TSADC		72
+#define SCLK_UART0		77
+#define SCLK_UART1		78
+#define SCLK_UART2		79
+#define SCLK_I2S0		80
+#define SCLK_I2S1		81
+#define SCLK_I2S2		82
+#define SCLK_SPDIF		83
+#define SCLK_TIMER0		85
+#define SCLK_TIMER1		86
+#define SCLK_TIMER2		87
+#define SCLK_TIMER3		88
+#define SCLK_TIMER4		89
+#define SCLK_TIMER5		90
+#define SCLK_I2S_OUT		113
+#define SCLK_SDMMC_DRV		114
+#define SCLK_SDIO_DRV		115
+#define SCLK_EMMC_DRV		117
+#define SCLK_SDMMC_SAMPLE	118
+#define SCLK_SDIO_SAMPLE	119
+#define SCLK_SDIO_SRC		120
+#define SCLK_EMMC_SAMPLE	121
+#define SCLK_VOP		122
+#define SCLK_HDMI_HDCP		123
+#define SCLK_MAC_SRC		124
+#define SCLK_MAC_EXTCLK		125
+#define SCLK_MAC		126
+#define SCLK_MAC_REFOUT		127
+#define SCLK_MAC_REF		128
+#define SCLK_MAC_RX		129
+#define SCLK_MAC_TX		130
+#define SCLK_MAC_PHY		131
+#define SCLK_MAC_OUT		132
+#define SCLK_VDEC_CABAC		133
+#define SCLK_VDEC_CORE		134
+#define SCLK_RGA		135
+#define SCLK_HDCP		136
+#define SCLK_HDMI_CEC		137
+#define SCLK_CRYPTO		138
+#define SCLK_TSP		139
+#define SCLK_HSADC		140
+#define SCLK_WIFI		141
+#define SCLK_OTGPHY0		142
+#define SCLK_OTGPHY1		143
+
+/* dclk gates */
+#define DCLK_VOP		190
+#define DCLK_HDMI_PHY		191
+
+/* aclk gates */
+#define ACLK_DMAC		194
+#define ACLK_CPU		195
+#define ACLK_VPU_PRE		196
+#define ACLK_RKVDEC_PRE		197
+#define ACLK_RGA_PRE		198
+#define ACLK_IEP_PRE		199
+#define ACLK_HDCP_PRE		200
+#define ACLK_VOP_PRE		201
+#define ACLK_VPU		202
+#define ACLK_RKVDEC		203
+#define ACLK_IEP		204
+#define ACLK_RGA		205
+#define ACLK_HDCP		206
+#define ACLK_PERI		210
+#define ACLK_VOP		211
+#define ACLK_GMAC		212
+#define ACLK_GPU		213
+
+/* pclk gates */
+#define PCLK_GPIO0		320
+#define PCLK_GPIO1		321
+#define PCLK_GPIO2		322
+#define PCLK_GPIO3		323
+#define PCLK_VIO_H2P		324
+#define PCLK_HDCP		325
+#define PCLK_EFUSE_1024		326
+#define PCLK_EFUSE_256		327
+#define PCLK_GRF		329
+#define PCLK_I2C0		332
+#define PCLK_I2C1		333
+#define PCLK_I2C2		334
+#define PCLK_I2C3		335
+#define PCLK_SPI0		338
+#define PCLK_UART0		341
+#define PCLK_UART1		342
+#define PCLK_UART2		343
+#define PCLK_TSADC		344
+#define PCLK_PWM		350
+#define PCLK_TIMER		353
+#define PCLK_CPU		354
+#define PCLK_PERI		363
+#define PCLK_HDMI_CTRL		364
+#define PCLK_HDMI_PHY		365
+#define PCLK_GMAC		367
+
+/* hclk gates */
+#define HCLK_I2S0_8CH		442
+#define HCLK_I2S1_8CH		443
+#define HCLK_I2S2_2CH		444
+#define HCLK_SPDIF_8CH		445
+#define HCLK_VOP		452
+#define HCLK_NANDC		453
+#define HCLK_SDMMC		456
+#define HCLK_SDIO		457
+#define HCLK_EMMC		459
+#define HCLK_CPU		460
+#define HCLK_VPU_PRE		461
+#define HCLK_RKVDEC_PRE		462
+#define HCLK_VIO_PRE		463
+#define HCLK_VPU		464
+#define HCLK_RKVDEC		465
+#define HCLK_VIO		466
+#define HCLK_RGA		467
+#define HCLK_IEP		468
+#define HCLK_VIO_H2P		469
+#define HCLK_HDCP_MMU		470
+#define HCLK_HOST0		471
+#define HCLK_HOST1		472
+#define HCLK_HOST2		473
+#define HCLK_OTG		474
+#define HCLK_TSP		475
+#define HCLK_M_CRYPTO		476
+#define HCLK_S_CRYPTO		477
+#define HCLK_PERI		478
+
+#define CLK_NR_CLKS		(HCLK_PERI + 1)
+
+/* soft-reset indices */
+#define SRST_CORE0_PO		0
+#define SRST_CORE1_PO		1
+#define SRST_CORE2_PO		2
+#define SRST_CORE3_PO		3
+#define SRST_CORE0		4
+#define SRST_CORE1		5
+#define SRST_CORE2		6
+#define SRST_CORE3		7
+#define SRST_CORE0_DBG		8
+#define SRST_CORE1_DBG		9
+#define SRST_CORE2_DBG		10
+#define SRST_CORE3_DBG		11
+#define SRST_TOPDBG		12
+#define SRST_ACLK_CORE		13
+#define SRST_NOC		14
+#define SRST_L2C		15
+
+#define SRST_CPUSYS_H		18
+#define SRST_BUSSYS_H		19
+#define SRST_SPDIF		20
+#define SRST_INTMEM		21
+#define SRST_ROM		22
+#define SRST_OTG_ADP		23
+#define SRST_I2S0		24
+#define SRST_I2S1		25
+#define SRST_I2S2		26
+#define SRST_ACODEC_P		27
+#define SRST_DFIMON		28
+#define SRST_MSCH		29
+#define SRST_EFUSE1024		30
+#define SRST_EFUSE256		31
+
+#define SRST_GPIO0		32
+#define SRST_GPIO1		33
+#define SRST_GPIO2		34
+#define SRST_GPIO3		35
+#define SRST_PERIPH_NOC_A	36
+#define SRST_PERIPH_NOC_BUS_H	37
+#define SRST_PERIPH_NOC_P	38
+#define SRST_UART0		39
+#define SRST_UART1		40
+#define SRST_UART2		41
+#define SRST_PHYNOC		42
+#define SRST_I2C0		43
+#define SRST_I2C1		44
+#define SRST_I2C2		45
+#define SRST_I2C3		46
+
+#define SRST_PWM		48
+#define SRST_A53_GIC		49
+#define SRST_DAP		51
+#define SRST_DAP_NOC		52
+#define SRST_CRYPTO		53
+#define SRST_SGRF		54
+#define SRST_GRF		55
+#define SRST_GMAC		56
+#define SRST_PERIPH_NOC_H	58
+#define SRST_MACPHY		63
+
+#define SRST_DMA		64
+#define SRST_NANDC		68
+#define SRST_USBOTG		69
+#define SRST_OTGC		70
+#define SRST_USBHOST0		71
+#define SRST_HOST_CTRL0		72
+#define SRST_USBHOST1		73
+#define SRST_HOST_CTRL1		74
+#define SRST_USBHOST2		75
+#define SRST_HOST_CTRL2		76
+#define SRST_USBPOR0		77
+#define SRST_USBPOR1		78
+#define SRST_DDRMSCH		79
+
+#define SRST_SMART_CARD		80
+#define SRST_SDMMC		81
+#define SRST_SDIO		82
+#define SRST_EMMC		83
+#define SRST_SPI		84
+#define SRST_TSP_H		85
+#define SRST_TSP		86
+#define SRST_TSADC		87
+#define SRST_DDRPHY		88
+#define SRST_DDRPHY_P		89
+#define SRST_DDRCTRL		90
+#define SRST_DDRCTRL_P		91
+#define SRST_HOST0_ECHI		92
+#define SRST_HOST1_ECHI		93
+#define SRST_HOST2_ECHI		94
+#define SRST_VOP_NOC_A		95
+
+#define SRST_HDMI_P		96
+#define SRST_VIO_ARBI_H		97
+#define SRST_IEP_NOC_A		98
+#define SRST_VIO_NOC_H		99
+#define SRST_VOP_A		100
+#define SRST_VOP_H		101
+#define SRST_VOP_D		102
+#define SRST_UTMI0		103
+#define SRST_UTMI1		104
+#define SRST_UTMI2		105
+#define SRST_UTMI3		106
+#define SRST_RGA		107
+#define SRST_RGA_NOC_A		108
+#define SRST_RGA_A		109
+#define SRST_RGA_H		110
+#define SRST_HDCP_A		111
+
+#define SRST_VPU_A		112
+#define SRST_VPU_H		113
+#define SRST_VPU_NOC_A		116
+#define SRST_VPU_NOC_H		117
+#define SRST_RKVDEC_A		118
+#define SRST_RKVDEC_NOC_A	119
+#define SRST_RKVDEC_H		120
+#define SRST_RKVDEC_NOC_H	121
+#define SRST_RKVDEC_CORE	122
+#define SRST_RKVDEC_CABAC	123
+#define SRST_IEP_A		124
+#define SRST_IEP_H		125
+#define SRST_GPU_A		126
+#define SRST_GPU_NOC_A		127
+
+#define SRST_CORE_DBG		128
+#define SRST_DBG_P		129
+#define SRST_TIMER0		130
+#define SRST_TIMER1		131
+#define SRST_TIMER2		132
+#define SRST_TIMER3		133
+#define SRST_TIMER4		134
+#define SRST_TIMER5		135
+#define SRST_VIO_H2P		136
+#define SRST_HDMIPHY		139
+#define SRST_VDAC		140
+#define SRST_TIMER_6CH_P	141
+
+#endif
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/rk3288-cru.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/rk3288-cru.h
new file mode 100644
index 0000000000000000000000000000000000000000..d7b6c83ea63f1883e09aa8424d23667ee79e9832
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/rk3288-cru.h
@@ -0,0 +1,389 @@
+/*
+ * Copyright (c) 2014 MundoReader S.L.
+ * Author: Heiko Stuebner <heiko@sntech.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3288_H
+#define _DT_BINDINGS_CLK_ROCKCHIP_RK3288_H
+
+/* core clocks */
+#define PLL_APLL		1
+#define PLL_DPLL		2
+#define PLL_CPLL		3
+#define PLL_GPLL		4
+#define PLL_NPLL		5
+#define ARMCLK			6
+
+/* sclk gates (special clocks) */
+#define SCLK_GPU		64
+#define SCLK_SPI0		65
+#define SCLK_SPI1		66
+#define SCLK_SPI2		67
+#define SCLK_SDMMC		68
+#define SCLK_SDIO0		69
+#define SCLK_SDIO1		70
+#define SCLK_EMMC		71
+#define SCLK_TSADC		72
+#define SCLK_SARADC		73
+#define SCLK_PS2C		74
+#define SCLK_NANDC0		75
+#define SCLK_NANDC1		76
+#define SCLK_UART0		77
+#define SCLK_UART1		78
+#define SCLK_UART2		79
+#define SCLK_UART3		80
+#define SCLK_UART4		81
+#define SCLK_I2S0		82
+#define SCLK_SPDIF		83
+#define SCLK_SPDIF8CH		84
+#define SCLK_TIMER0		85
+#define SCLK_TIMER1		86
+#define SCLK_TIMER2		87
+#define SCLK_TIMER3		88
+#define SCLK_TIMER4		89
+#define SCLK_TIMER5		90
+#define SCLK_TIMER6		91
+#define SCLK_HSADC		92
+#define SCLK_OTGPHY0		93
+#define SCLK_OTGPHY1		94
+#define SCLK_OTGPHY2		95
+#define SCLK_OTG_ADP		96
+#define SCLK_HSICPHY480M	97
+#define SCLK_HSICPHY12M		98
+#define SCLK_MACREF		99
+#define SCLK_LCDC_PWM0		100
+#define SCLK_LCDC_PWM1		101
+#define SCLK_MAC_RX		102
+#define SCLK_MAC_TX		103
+#define SCLK_EDP_24M		104
+#define SCLK_EDP		105
+#define SCLK_RGA		106
+#define SCLK_ISP		107
+#define SCLK_ISP_JPE		108
+#define SCLK_HDMI_HDCP		109
+#define SCLK_HDMI_CEC		110
+#define SCLK_HEVC_CABAC		111
+#define SCLK_HEVC_CORE		112
+#define SCLK_I2S0_OUT		113
+#define SCLK_SDMMC_DRV		114
+#define SCLK_SDIO0_DRV		115
+#define SCLK_SDIO1_DRV		116
+#define SCLK_EMMC_DRV		117
+#define SCLK_SDMMC_SAMPLE	118
+#define SCLK_SDIO0_SAMPLE	119
+#define SCLK_SDIO1_SAMPLE	120
+#define SCLK_EMMC_SAMPLE	121
+#define SCLK_USBPHY480M_SRC	122
+#define SCLK_PVTM_CORE		123
+#define SCLK_PVTM_GPU		124
+#define SCLK_CRYPTO		125
+#define SCLK_MIPIDSI_24M	126
+#define SCLK_VIP_OUT		127
+
+#define SCLK_MAC		151
+#define SCLK_MACREF_OUT		152
+
+#define DCLK_VOP0		190
+#define DCLK_VOP1		191
+
+/* aclk gates */
+#define ACLK_GPU		192
+#define ACLK_DMAC1		193
+#define ACLK_DMAC2		194
+#define ACLK_MMU		195
+#define ACLK_GMAC		196
+#define ACLK_VOP0		197
+#define ACLK_VOP1		198
+#define ACLK_CRYPTO		199
+#define ACLK_RGA		200
+#define ACLK_RGA_NIU		201
+#define ACLK_IEP		202
+#define ACLK_VIO0_NIU		203
+#define ACLK_VIP		204
+#define ACLK_ISP		205
+#define ACLK_VIO1_NIU		206
+#define ACLK_HEVC		207
+#define ACLK_VCODEC		208
+#define ACLK_CPU		209
+#define ACLK_PERI		210
+
+/* pclk gates */
+#define PCLK_GPIO0		320
+#define PCLK_GPIO1		321
+#define PCLK_GPIO2		322
+#define PCLK_GPIO3		323
+#define PCLK_GPIO4		324
+#define PCLK_GPIO5		325
+#define PCLK_GPIO6		326
+#define PCLK_GPIO7		327
+#define PCLK_GPIO8		328
+#define PCLK_GRF		329
+#define PCLK_SGRF		330
+#define PCLK_PMU		331
+#define PCLK_I2C0		332
+#define PCLK_I2C1		333
+#define PCLK_I2C2		334
+#define PCLK_I2C3		335
+#define PCLK_I2C4		336
+#define PCLK_I2C5		337
+#define PCLK_SPI0		338
+#define PCLK_SPI1		339
+#define PCLK_SPI2		340
+#define PCLK_UART0		341
+#define PCLK_UART1		342
+#define PCLK_UART2		343
+#define PCLK_UART3		344
+#define PCLK_UART4		345
+#define PCLK_TSADC		346
+#define PCLK_SARADC		347
+#define PCLK_SIM		348
+#define PCLK_GMAC		349
+#define PCLK_PWM		350
+#define PCLK_RKPWM		351
+#define PCLK_PS2C		352
+#define PCLK_TIMER		353
+#define PCLK_TZPC		354
+#define PCLK_EDP_CTRL		355
+#define PCLK_MIPI_DSI0		356
+#define PCLK_MIPI_DSI1		357
+#define PCLK_MIPI_CSI		358
+#define PCLK_LVDS_PHY		359
+#define PCLK_HDMI_CTRL		360
+#define PCLK_VIO2_H2P		361
+#define PCLK_CPU		362
+#define PCLK_PERI		363
+#define PCLK_DDRUPCTL0		364
+#define PCLK_PUBL0		365
+#define PCLK_DDRUPCTL1		366
+#define PCLK_PUBL1		367
+#define PCLK_WDT		368
+#define PCLK_EFUSE256		369
+#define PCLK_EFUSE1024		370
+#define PCLK_ISP_IN		371
+
+/* hclk gates */
+#define HCLK_GPS		448
+#define HCLK_OTG0		449
+#define HCLK_USBHOST0		450
+#define HCLK_USBHOST1		451
+#define HCLK_HSIC		452
+#define HCLK_NANDC0		453
+#define HCLK_NANDC1		454
+#define HCLK_TSP		455
+#define HCLK_SDMMC		456
+#define HCLK_SDIO0		457
+#define HCLK_SDIO1		458
+#define HCLK_EMMC		459
+#define HCLK_HSADC		460
+#define HCLK_CRYPTO		461
+#define HCLK_I2S0		462
+#define HCLK_SPDIF		463
+#define HCLK_SPDIF8CH		464
+#define HCLK_VOP0		465
+#define HCLK_VOP1		466
+#define HCLK_ROM		467
+#define HCLK_IEP		468
+#define HCLK_ISP		469
+#define HCLK_RGA		470
+#define HCLK_VIO_AHB_ARBI	471
+#define HCLK_VIO_NIU		472
+#define HCLK_VIP		473
+#define HCLK_VIO2_H2P		474
+#define HCLK_HEVC		475
+#define HCLK_VCODEC		476
+#define HCLK_CPU		477
+#define HCLK_PERI		478
+
+#define CLK_NR_CLKS		(HCLK_PERI + 1)
+
+/* soft-reset indices */
+#define SRST_CORE0		0
+#define SRST_CORE1		1
+#define SRST_CORE2		2
+#define SRST_CORE3		3
+#define SRST_CORE0_PO		4
+#define SRST_CORE1_PO		5
+#define SRST_CORE2_PO		6
+#define SRST_CORE3_PO		7
+#define SRST_PDCORE_STRSYS	8
+#define SRST_PDBUS_STRSYS	9
+#define SRST_L2C		10
+#define SRST_TOPDBG		11
+#define SRST_CORE0_DBG		12
+#define SRST_CORE1_DBG		13
+#define SRST_CORE2_DBG		14
+#define SRST_CORE3_DBG		15
+
+#define SRST_PDBUG_AHB_ARBITOR	16
+#define SRST_EFUSE256		17
+#define SRST_DMAC1		18
+#define SRST_INTMEM		19
+#define SRST_ROM		20
+#define SRST_SPDIF8CH		21
+#define SRST_TIMER		22
+#define SRST_I2S0		23
+#define SRST_SPDIF		24
+#define SRST_TIMER0		25
+#define SRST_TIMER1		26
+#define SRST_TIMER2		27
+#define SRST_TIMER3		28
+#define SRST_TIMER4		29
+#define SRST_TIMER5		30
+#define SRST_EFUSE		31
+
+#define SRST_GPIO0		32
+#define SRST_GPIO1		33
+#define SRST_GPIO2		34
+#define SRST_GPIO3		35
+#define SRST_GPIO4		36
+#define SRST_GPIO5		37
+#define SRST_GPIO6		38
+#define SRST_GPIO7		39
+#define SRST_GPIO8		40
+#define SRST_I2C0		42
+#define SRST_I2C1		43
+#define SRST_I2C2		44
+#define SRST_I2C3		45
+#define SRST_I2C4		46
+#define SRST_I2C5		47
+
+#define SRST_DWPWM		48
+#define SRST_MMC_PERI		49
+#define SRST_PERIPH_MMU		50
+#define SRST_DAP		51
+#define SRST_DAP_SYS		52
+#define SRST_TPIU		53
+#define SRST_PMU_APB		54
+#define SRST_GRF		55
+#define SRST_PMU		56
+#define SRST_PERIPH_AXI		57
+#define SRST_PERIPH_AHB		58
+#define SRST_PERIPH_APB		59
+#define SRST_PERIPH_NIU		60
+#define SRST_PDPERI_AHB_ARBI	61
+#define SRST_EMEM		62
+#define SRST_USB_PERI		63
+
+#define SRST_DMAC2		64
+#define SRST_MAC		66
+#define SRST_GPS		67
+#define SRST_RKPWM		69
+#define SRST_CCP		71
+#define SRST_USBHOST0		72
+#define SRST_HSIC		73
+#define SRST_HSIC_AUX		74
+#define SRST_HSIC_PHY		75
+#define SRST_HSADC		76
+#define SRST_NANDC0		77
+#define SRST_NANDC1		78
+
+#define SRST_TZPC		80
+#define SRST_SPI0		83
+#define SRST_SPI1		84
+#define SRST_SPI2		85
+#define SRST_SARADC		87
+#define SRST_PDALIVE_NIU	88
+#define SRST_PDPMU_INTMEM	89
+#define SRST_PDPMU_NIU		90
+#define SRST_SGRF		91
+
+#define SRST_VIO_ARBI		96
+#define SRST_RGA_NIU		97
+#define SRST_VIO0_NIU_AXI	98
+#define SRST_VIO_NIU_AHB	99
+#define SRST_LCDC0_AXI		100
+#define SRST_LCDC0_AHB		101
+#define SRST_LCDC0_DCLK		102
+#define SRST_VIO1_NIU_AXI	103
+#define SRST_VIP		104
+#define SRST_RGA_CORE		105
+#define SRST_IEP_AXI		106
+#define SRST_IEP_AHB		107
+#define SRST_RGA_AXI		108
+#define SRST_RGA_AHB		109
+#define SRST_ISP		110
+#define SRST_EDP		111
+
+#define SRST_VCODEC_AXI		112
+#define SRST_VCODEC_AHB		113
+#define SRST_VIO_H2P		114
+#define SRST_MIPIDSI0		115
+#define SRST_MIPIDSI1		116
+#define SRST_MIPICSI		117
+#define SRST_LVDS_PHY		118
+#define SRST_LVDS_CON		119
+#define SRST_GPU		120
+#define SRST_HDMI		121
+#define SRST_CORE_PVTM		124
+#define SRST_GPU_PVTM		125
+
+#define SRST_MMC0		128
+#define SRST_SDIO0		129
+#define SRST_SDIO1		130
+#define SRST_EMMC		131
+#define SRST_USBOTG_AHB		132
+#define SRST_USBOTG_PHY		133
+#define SRST_USBOTG_CON		134
+#define SRST_USBHOST0_AHB	135
+#define SRST_USBHOST0_PHY	136
+#define SRST_USBHOST0_CON	137
+#define SRST_USBHOST1_AHB	138
+#define SRST_USBHOST1_PHY	139
+#define SRST_USBHOST1_CON	140
+#define SRST_USB_ADP		141
+#define SRST_ACC_EFUSE		142
+
+#define SRST_CORESIGHT		144
+#define SRST_PD_CORE_AHB_NOC	145
+#define SRST_PD_CORE_APB_NOC	146
+#define SRST_PD_CORE_MP_AXI	147
+#define SRST_GIC		148
+#define SRST_LCDC_PWM0		149
+#define SRST_LCDC_PWM1		150
+#define SRST_VIO0_H2P_BRG	151
+#define SRST_VIO1_H2P_BRG	152
+#define SRST_RGA_H2P_BRG	153
+#define SRST_HEVC		154
+#define SRST_TSADC		159
+
+#define SRST_DDRPHY0		160
+#define SRST_DDRPHY0_APB	161
+#define SRST_DDRCTRL0		162
+#define SRST_DDRCTRL0_APB	163
+#define SRST_DDRPHY0_CTRL	164
+#define SRST_DDRPHY1		165
+#define SRST_DDRPHY1_APB	166
+#define SRST_DDRCTRL1		167
+#define SRST_DDRCTRL1_APB	168
+#define SRST_DDRPHY1_CTRL	169
+#define SRST_DDRMSCH0		170
+#define SRST_DDRMSCH1		171
+#define SRST_CRYPTO		174
+#define SRST_C2C_HOST		175
+
+#define SRST_LCDC1_AXI		176
+#define SRST_LCDC1_AHB		177
+#define SRST_LCDC1_DCLK		178
+#define SRST_UART0		179
+#define SRST_UART1		180
+#define SRST_UART2		181
+#define SRST_UART3		182
+#define SRST_UART4		183
+#define SRST_SIMC		186
+#define SRST_PS2C		187
+#define SRST_TSP		188
+#define SRST_TSP_CLKIN0		189
+#define SRST_TSP_CLKIN1		190
+#define SRST_TSP_27M		191
+
+#endif
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/rk3328-cru.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/rk3328-cru.h
new file mode 100644
index 0000000000000000000000000000000000000000..a82a0109faffe92689fcd05cdc2d963dca5dee78
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/rk3328-cru.h
@@ -0,0 +1,400 @@
+/*
+ * Copyright (c) 2016 Rockchip Electronics Co. Ltd.
+ * Author: Elaine <zhangqing@rock-chips.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3328_H
+#define _DT_BINDINGS_CLK_ROCKCHIP_RK3328_H
+
+/* core clocks */
+#define PLL_APLL		1
+#define PLL_DPLL		2
+#define PLL_CPLL		3
+#define PLL_GPLL		4
+#define PLL_NPLL		5
+#define ARMCLK			6
+
+/* sclk gates (special clocks) */
+#define SCLK_RTC32K		30
+#define SCLK_SDMMC_EXT		31
+#define SCLK_SPI		32
+#define SCLK_SDMMC		33
+#define SCLK_SDIO		34
+#define SCLK_EMMC		35
+#define SCLK_TSADC		36
+#define SCLK_SARADC		37
+#define SCLK_UART0		38
+#define SCLK_UART1		39
+#define SCLK_UART2		40
+#define SCLK_I2S0		41
+#define SCLK_I2S1		42
+#define SCLK_I2S2		43
+#define SCLK_I2S1_OUT		44
+#define SCLK_I2S2_OUT		45
+#define SCLK_SPDIF		46
+#define SCLK_TIMER0		47
+#define SCLK_TIMER1		48
+#define SCLK_TIMER2		49
+#define SCLK_TIMER3		50
+#define SCLK_TIMER4		51
+#define SCLK_TIMER5		52
+#define SCLK_WIFI		53
+#define SCLK_CIF_OUT		54
+#define SCLK_I2C0		55
+#define SCLK_I2C1		56
+#define SCLK_I2C2		57
+#define SCLK_I2C3		58
+#define SCLK_CRYPTO		59
+#define SCLK_PWM		60
+#define SCLK_PDM		61
+#define SCLK_EFUSE		62
+#define SCLK_OTP		63
+#define SCLK_DDRCLK		64
+#define SCLK_VDEC_CABAC		65
+#define SCLK_VDEC_CORE		66
+#define SCLK_VENC_DSP		67
+#define SCLK_VENC_CORE		68
+#define SCLK_RGA		69
+#define SCLK_HDMI_SFC		70
+#define SCLK_HDMI_CEC		71
+#define SCLK_USB3_REF		72
+#define SCLK_USB3_SUSPEND	73
+#define SCLK_SDMMC_DRV		74
+#define SCLK_SDIO_DRV		75
+#define SCLK_EMMC_DRV		76
+#define SCLK_SDMMC_EXT_DRV	77
+#define SCLK_SDMMC_SAMPLE	78
+#define SCLK_SDIO_SAMPLE	79
+#define SCLK_EMMC_SAMPLE	80
+#define SCLK_SDMMC_EXT_SAMPLE	81
+#define SCLK_VOP		82
+#define SCLK_MAC2PHY_RXTX	83
+#define SCLK_MAC2PHY_SRC	84
+#define SCLK_MAC2PHY_REF	85
+#define SCLK_MAC2PHY_OUT	86
+#define SCLK_MAC2IO_RX		87
+#define SCLK_MAC2IO_TX		88
+#define SCLK_MAC2IO_REFOUT	89
+#define SCLK_MAC2IO_REF		90
+#define SCLK_MAC2IO_OUT		91
+#define SCLK_TSP		92
+#define SCLK_HSADC_TSP		93
+#define SCLK_USB3PHY_REF	94
+#define SCLK_REF_USB3OTG	95
+#define SCLK_USB3OTG_REF	96
+#define SCLK_USB3OTG_SUSPEND	97
+#define SCLK_REF_USB3OTG_SRC	98
+#define SCLK_MAC2IO_SRC		99
+#define SCLK_MAC2IO		100
+#define SCLK_MAC2PHY		101
+#define SCLK_MAC2IO_EXT		102
+
+/* dclk gates */
+#define DCLK_LCDC		120
+#define DCLK_HDMIPHY		121
+#define HDMIPHY			122
+#define USB480M			123
+#define DCLK_LCDC_SRC		124
+
+/* aclk gates */
+#define ACLK_AXISRAM		130
+#define ACLK_VOP_PRE		131
+#define ACLK_USB3OTG		132
+#define ACLK_RGA_PRE		133
+#define ACLK_DMAC		134
+#define ACLK_GPU		135
+#define ACLK_BUS_PRE		136
+#define ACLK_PERI_PRE		137
+#define ACLK_RKVDEC_PRE		138
+#define ACLK_RKVDEC		139
+#define ACLK_RKVENC		140
+#define ACLK_VPU_PRE		141
+#define ACLK_VIO_PRE		142
+#define ACLK_VPU		143
+#define ACLK_VIO		144
+#define ACLK_VOP		145
+#define ACLK_GMAC		146
+#define ACLK_H265		147
+#define ACLK_H264		148
+#define ACLK_MAC2PHY		149
+#define ACLK_MAC2IO		150
+#define ACLK_DCF		151
+#define ACLK_TSP		152
+#define ACLK_PERI		153
+#define ACLK_RGA		154
+#define ACLK_IEP		155
+#define ACLK_CIF		156
+#define ACLK_HDCP		157
+
+/* pclk gates */
+#define PCLK_GPIO0		200
+#define PCLK_GPIO1		201
+#define PCLK_GPIO2		202
+#define PCLK_GPIO3		203
+#define PCLK_GRF		204
+#define PCLK_I2C0		205
+#define PCLK_I2C1		206
+#define PCLK_I2C2		207
+#define PCLK_I2C3		208
+#define PCLK_SPI		209
+#define PCLK_UART0		210
+#define PCLK_UART1		211
+#define PCLK_UART2		212
+#define PCLK_TSADC		213
+#define PCLK_PWM		214
+#define PCLK_TIMER		215
+#define PCLK_BUS_PRE		216
+#define PCLK_PERI_PRE		217
+#define PCLK_HDMI_CTRL		218
+#define PCLK_HDMI_PHY		219
+#define PCLK_GMAC		220
+#define PCLK_H265		221
+#define PCLK_MAC2PHY		222
+#define PCLK_MAC2IO		223
+#define PCLK_USB3PHY_OTG	224
+#define PCLK_USB3PHY_PIPE	225
+#define PCLK_USB3_GRF		226
+#define PCLK_USB2_GRF		227
+#define PCLK_HDMIPHY		228
+#define PCLK_DDR		229
+#define PCLK_PERI		230
+#define PCLK_HDMI		231
+#define PCLK_HDCP		232
+#define PCLK_DCF		233
+#define PCLK_SARADC		234
+
+/* hclk gates */
+#define HCLK_PERI		308
+#define HCLK_TSP		309
+#define HCLK_GMAC		310
+#define HCLK_I2S0_8CH		311
+#define HCLK_I2S1_8CH		313
+#define HCLK_I2S2_2CH		313
+#define HCLK_SPDIF_8CH		314
+#define HCLK_VOP		315
+#define HCLK_NANDC		316
+#define HCLK_SDMMC		317
+#define HCLK_SDIO		318
+#define HCLK_EMMC		319
+#define HCLK_SDMMC_EXT		320
+#define HCLK_RKVDEC_PRE		321
+#define HCLK_RKVDEC		322
+#define HCLK_RKVENC		323
+#define HCLK_VPU_PRE		324
+#define HCLK_VIO_PRE		325
+#define HCLK_VPU		326
+#define HCLK_BUS_PRE		328
+#define HCLK_PERI_PRE		329
+#define HCLK_H264		330
+#define HCLK_CIF		331
+#define HCLK_OTG_PMU		332
+#define HCLK_OTG		333
+#define HCLK_HOST0		334
+#define HCLK_HOST0_ARB		335
+#define HCLK_CRYPTO_MST		336
+#define HCLK_CRYPTO_SLV		337
+#define HCLK_PDM		338
+#define HCLK_IEP		339
+#define HCLK_RGA		340
+#define HCLK_HDCP		341
+
+#define CLK_NR_CLKS		(HCLK_HDCP + 1)
+
+/* soft-reset indices */
+#define SRST_CORE0_PO		0
+#define SRST_CORE1_PO		1
+#define SRST_CORE2_PO		2
+#define SRST_CORE3_PO		3
+#define SRST_CORE0		4
+#define SRST_CORE1		5
+#define SRST_CORE2		6
+#define SRST_CORE3		7
+#define SRST_CORE0_DBG		8
+#define SRST_CORE1_DBG		9
+#define SRST_CORE2_DBG		10
+#define SRST_CORE3_DBG		11
+#define SRST_TOPDBG		12
+#define SRST_CORE_NIU		13
+#define SRST_STRC_A		14
+#define SRST_L2C		15
+
+#define SRST_A53_GIC		18
+#define SRST_DAP		19
+#define SRST_PMU_P		21
+#define SRST_EFUSE		22
+#define SRST_BUSSYS_H		23
+#define SRST_BUSSYS_P		24
+#define SRST_SPDIF		25
+#define SRST_INTMEM		26
+#define SRST_ROM		27
+#define SRST_GPIO0		28
+#define SRST_GPIO1		29
+#define SRST_GPIO2		30
+#define SRST_GPIO3		31
+
+#define SRST_I2S0		32
+#define SRST_I2S1		33
+#define SRST_I2S2		34
+#define SRST_I2S0_H		35
+#define SRST_I2S1_H		36
+#define SRST_I2S2_H		37
+#define SRST_UART0		38
+#define SRST_UART1		39
+#define SRST_UART2		40
+#define SRST_UART0_P		41
+#define SRST_UART1_P		42
+#define SRST_UART2_P		43
+#define SRST_I2C0		44
+#define SRST_I2C1		45
+#define SRST_I2C2		46
+#define SRST_I2C3		47
+
+#define SRST_I2C0_P		48
+#define SRST_I2C1_P		49
+#define SRST_I2C2_P		50
+#define SRST_I2C3_P		51
+#define SRST_EFUSE_SE_P		52
+#define SRST_EFUSE_NS_P		53
+#define SRST_PWM0		54
+#define SRST_PWM0_P		55
+#define SRST_DMA		56
+#define SRST_TSP_A		57
+#define SRST_TSP_H		58
+#define SRST_TSP		59
+#define SRST_TSP_HSADC		60
+#define SRST_DCF_A		61
+#define SRST_DCF_P		62
+
+#define SRST_SCR		64
+#define SRST_SPI		65
+#define SRST_TSADC		66
+#define SRST_TSADC_P		67
+#define SRST_CRYPTO		68
+#define SRST_SGRF		69
+#define SRST_GRF		70
+#define SRST_USB_GRF		71
+#define SRST_TIMER_6CH_P	72
+#define SRST_TIMER0		73
+#define SRST_TIMER1		74
+#define SRST_TIMER2		75
+#define SRST_TIMER3		76
+#define SRST_TIMER4		77
+#define SRST_TIMER5		78
+#define SRST_USB3GRF		79
+
+#define SRST_PHYNIU		80
+#define SRST_HDMIPHY		81
+#define SRST_VDAC		82
+#define SRST_ACODEC_p		83
+#define SRST_SARADC		85
+#define SRST_SARADC_P		86
+#define SRST_GRF_DDR		87
+#define SRST_DFIMON		88
+#define SRST_MSCH		89
+#define SRST_DDRMSCH		91
+#define SRST_DDRCTRL		92
+#define SRST_DDRCTRL_P		93
+#define SRST_DDRPHY		94
+#define SRST_DDRPHY_P		95
+
+#define SRST_GMAC_NIU_A		96
+#define SRST_GMAC_NIU_P		97
+#define SRST_GMAC2PHY_A		98
+#define SRST_GMAC2IO_A		99
+#define SRST_MACPHY		100
+#define SRST_OTP_PHY		101
+#define SRST_GPU_A		102
+#define SRST_GPU_NIU_A		103
+#define SRST_SDMMCEXT		104
+#define SRST_PERIPH_NIU_A	105
+#define SRST_PERIHP_NIU_H	106
+#define SRST_PERIHP_P		107
+#define SRST_PERIPHSYS_H	108
+#define SRST_MMC0		109
+#define SRST_SDIO		110
+#define SRST_EMMC		111
+
+#define SRST_USB2OTG_H		112
+#define SRST_USB2OTG		113
+#define SRST_USB2OTG_ADP	114
+#define SRST_USB2HOST_H		115
+#define SRST_USB2HOST_ARB	116
+#define SRST_USB2HOST_AUX	117
+#define SRST_USB2HOST_EHCIPHY	118
+#define SRST_USB2HOST_UTMI	119
+#define SRST_USB3OTG		120
+#define SRST_USBPOR		121
+#define SRST_USB2OTG_UTMI	122
+#define SRST_USB2HOST_PHY_UTMI	123
+#define SRST_USB3OTG_UTMI	124
+#define SRST_USB3PHY_U2		125
+#define SRST_USB3PHY_U3		126
+#define SRST_USB3PHY_PIPE	127
+
+#define SRST_VIO_A		128
+#define SRST_VIO_BUS_H		129
+#define SRST_VIO_H2P_H		130
+#define SRST_VIO_ARBI_H		131
+#define SRST_VOP_NIU_A		132
+#define SRST_VOP_A		133
+#define SRST_VOP_H		134
+#define SRST_VOP_D		135
+#define SRST_RGA		136
+#define SRST_RGA_NIU_A		137
+#define SRST_RGA_A		138
+#define SRST_RGA_H		139
+#define SRST_IEP_A		140
+#define SRST_IEP_H		141
+#define SRST_HDMI		142
+#define SRST_HDMI_P		143
+
+#define SRST_HDCP_A		144
+#define SRST_HDCP		145
+#define SRST_HDCP_H		146
+#define SRST_CIF_A		147
+#define SRST_CIF_H		148
+#define SRST_CIF_P		149
+#define SRST_OTP_P		150
+#define SRST_OTP_SBPI		151
+#define SRST_OTP_USER		152
+#define SRST_DDRCTRL_A		153
+#define SRST_DDRSTDY_P		154
+#define SRST_DDRSTDY		155
+#define SRST_PDM_H		156
+#define SRST_PDM		157
+#define SRST_USB3PHY_OTG_P	158
+#define SRST_USB3PHY_PIPE_P	159
+
+#define SRST_VCODEC_A		160
+#define SRST_VCODEC_NIU_A	161
+#define SRST_VCODEC_H		162
+#define SRST_VCODEC_NIU_H	163
+#define SRST_VDEC_A		164
+#define SRST_VDEC_NIU_A		165
+#define SRST_VDEC_H		166
+#define SRST_VDEC_NIU_H		167
+#define SRST_VDEC_CORE		168
+#define SRST_VDEC_CABAC		169
+#define SRST_DDRPHYDIV		175
+
+#define SRST_RKVENC_NIU_A	176
+#define SRST_RKVENC_NIU_H	177
+#define SRST_RKVENC_H265_A	178
+#define SRST_RKVENC_H265_P	179
+#define SRST_RKVENC_H265_CORE	180
+#define SRST_RKVENC_H265_DSP	181
+#define SRST_RKVENC_H264_A	182
+#define SRST_RKVENC_H264_H	183
+#define SRST_RKVENC_INTMEM	184
+
+#endif
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/rk3368-cru.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/rk3368-cru.h
new file mode 100644
index 0000000000000000000000000000000000000000..a0063ed7284a59b7a3afc7ff0297acb6c33a44b2
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/rk3368-cru.h
@@ -0,0 +1,390 @@
+/*
+ * Copyright (c) 2015 Heiko Stuebner <heiko@sntech.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3368_H
+#define _DT_BINDINGS_CLK_ROCKCHIP_RK3368_H
+
+/* core clocks */
+#define PLL_APLLB		1
+#define PLL_APLLL		2
+#define PLL_DPLL		3
+#define PLL_CPLL		4
+#define PLL_GPLL		5
+#define PLL_NPLL		6
+#define ARMCLKB			7
+#define ARMCLKL			8
+
+/* sclk gates (special clocks) */
+#define SCLK_GPU_CORE		64
+#define SCLK_SPI0		65
+#define SCLK_SPI1		66
+#define SCLK_SPI2		67
+#define SCLK_SDMMC		68
+#define SCLK_SDIO0		69
+#define SCLK_EMMC		71
+#define SCLK_TSADC		72
+#define SCLK_SARADC		73
+#define SCLK_NANDC0		75
+#define SCLK_UART0		77
+#define SCLK_UART1		78
+#define SCLK_UART2		79
+#define SCLK_UART3		80
+#define SCLK_UART4		81
+#define SCLK_I2S_8CH		82
+#define SCLK_SPDIF_8CH		83
+#define SCLK_I2S_2CH		84
+#define SCLK_TIMER00		85
+#define SCLK_TIMER01		86
+#define SCLK_TIMER02		87
+#define SCLK_TIMER03		88
+#define SCLK_TIMER04		89
+#define SCLK_TIMER05		90
+#define SCLK_OTGPHY0		93
+#define SCLK_OTG_ADP		96
+#define SCLK_HSICPHY480M	97
+#define SCLK_HSICPHY12M		98
+#define SCLK_MACREF		99
+#define SCLK_VOP0_PWM		100
+#define SCLK_MAC_RX		102
+#define SCLK_MAC_TX		103
+#define SCLK_EDP_24M		104
+#define SCLK_EDP		105
+#define SCLK_RGA		106
+#define SCLK_ISP		107
+#define SCLK_HDCP		108
+#define SCLK_HDMI_HDCP		109
+#define SCLK_HDMI_CEC		110
+#define SCLK_HEVC_CABAC		111
+#define SCLK_HEVC_CORE		112
+#define SCLK_I2S_8CH_OUT	113
+#define SCLK_SDMMC_DRV		114
+#define SCLK_SDIO0_DRV		115
+#define SCLK_EMMC_DRV		117
+#define SCLK_SDMMC_SAMPLE	118
+#define SCLK_SDIO0_SAMPLE	119
+#define SCLK_EMMC_SAMPLE	121
+#define SCLK_USBPHY480M		122
+#define SCLK_PVTM_CORE		123
+#define SCLK_PVTM_GPU		124
+#define SCLK_PVTM_PMU		125
+#define SCLK_SFC		126
+#define SCLK_MAC		127
+#define SCLK_MACREF_OUT		128
+#define SCLK_TIMER10		133
+#define SCLK_TIMER11		134
+#define SCLK_TIMER12		135
+#define SCLK_TIMER13		136
+#define SCLK_TIMER14		137
+#define SCLK_TIMER15		138
+
+#define DCLK_VOP		190
+#define MCLK_CRYPTO		191
+
+/* aclk gates */
+#define ACLK_GPU_MEM		192
+#define ACLK_GPU_CFG		193
+#define ACLK_DMAC_BUS		194
+#define ACLK_DMAC_PERI		195
+#define ACLK_PERI_MMU		196
+#define ACLK_GMAC		197
+#define ACLK_VOP		198
+#define ACLK_VOP_IEP		199
+#define ACLK_RGA		200
+#define ACLK_HDCP		201
+#define ACLK_IEP		202
+#define ACLK_VIO0_NOC		203
+#define ACLK_VIP		204
+#define ACLK_ISP		205
+#define ACLK_VIO1_NOC		206
+#define ACLK_VIDEO		208
+#define ACLK_BUS		209
+#define ACLK_PERI		210
+
+/* pclk gates */
+#define PCLK_GPIO0		320
+#define PCLK_GPIO1		321
+#define PCLK_GPIO2		322
+#define PCLK_GPIO3		323
+#define PCLK_PMUGRF		324
+#define PCLK_MAILBOX		325
+#define PCLK_GRF		329
+#define PCLK_SGRF		330
+#define PCLK_PMU		331
+#define PCLK_I2C0		332
+#define PCLK_I2C1		333
+#define PCLK_I2C2		334
+#define PCLK_I2C3		335
+#define PCLK_I2C4		336
+#define PCLK_I2C5		337
+#define PCLK_SPI0		338
+#define PCLK_SPI1		339
+#define PCLK_SPI2		340
+#define PCLK_UART0		341
+#define PCLK_UART1		342
+#define PCLK_UART2		343
+#define PCLK_UART3		344
+#define PCLK_UART4		345
+#define PCLK_TSADC		346
+#define PCLK_SARADC		347
+#define PCLK_SIM		348
+#define PCLK_GMAC		349
+#define PCLK_PWM0		350
+#define PCLK_PWM1		351
+#define PCLK_TIMER0		353
+#define PCLK_TIMER1		354
+#define PCLK_EDP_CTRL		355
+#define PCLK_MIPI_DSI0		356
+#define PCLK_MIPI_CSI		358
+#define PCLK_HDCP		359
+#define PCLK_HDMI_CTRL		360
+#define PCLK_VIO_H2P		361
+#define PCLK_BUS		362
+#define PCLK_PERI		363
+#define PCLK_DDRUPCTL		364
+#define PCLK_DDRPHY		365
+#define PCLK_ISP		366
+#define PCLK_VIP		367
+#define PCLK_WDT		368
+#define PCLK_EFUSE256		369
+
+/* hclk gates */
+#define HCLK_SFC		448
+#define HCLK_OTG0		449
+#define HCLK_HOST0		450
+#define HCLK_HOST1		451
+#define HCLK_HSIC		452
+#define HCLK_NANDC0		453
+#define HCLK_TSP		455
+#define HCLK_SDMMC		456
+#define HCLK_SDIO0		457
+#define HCLK_EMMC		459
+#define HCLK_HSADC		460
+#define HCLK_CRYPTO		461
+#define HCLK_I2S_2CH		462
+#define HCLK_I2S_8CH		463
+#define HCLK_SPDIF		464
+#define HCLK_VOP		465
+#define HCLK_ROM		467
+#define HCLK_IEP		468
+#define HCLK_ISP		469
+#define HCLK_RGA		470
+#define HCLK_VIO_AHB_ARBI	471
+#define HCLK_VIO_NOC		472
+#define HCLK_VIP		473
+#define HCLK_VIO_H2P		474
+#define HCLK_VIO_HDCPMMU	475
+#define HCLK_VIDEO		476
+#define HCLK_BUS		477
+#define HCLK_PERI		478
+
+#define CLK_NR_CLKS		(HCLK_PERI + 1)
+
+/* soft-reset indices */
+#define SRST_CORE_B0		0
+#define SRST_CORE_B1		1
+#define SRST_CORE_B2		2
+#define SRST_CORE_B3		3
+#define SRST_CORE_B0_PO		4
+#define SRST_CORE_B1_PO		5
+#define SRST_CORE_B2_PO		6
+#define SRST_CORE_B3_PO		7
+#define SRST_L2_B		8
+#define SRST_ADB_B		9
+#define SRST_PD_CORE_B_NIU	10
+#define SRST_PDBUS_STRSYS	11
+#define SRST_SOCDBG_B		14
+#define SRST_CORE_B_DBG		15
+
+#define SRST_DMAC1		18
+#define SRST_INTMEM		19
+#define SRST_ROM		20
+#define SRST_SPDIF8CH		21
+#define SRST_I2S8CH		23
+#define SRST_MAILBOX		24
+#define SRST_I2S2CH		25
+#define SRST_EFUSE_256		26
+#define SRST_MCU_SYS		28
+#define SRST_MCU_PO		29
+#define SRST_MCU_NOC		30
+#define SRST_EFUSE		31
+
+#define SRST_GPIO0		32
+#define SRST_GPIO1		33
+#define SRST_GPIO2		34
+#define SRST_GPIO3		35
+#define SRST_GPIO4		36
+#define SRST_PMUGRF		41
+#define SRST_I2C0		42
+#define SRST_I2C1		43
+#define SRST_I2C2		44
+#define SRST_I2C3		45
+#define SRST_I2C4		46
+#define SRST_I2C5		47
+
+#define SRST_DWPWM		48
+#define SRST_MMC_PERI		49
+#define SRST_PERIPH_MMU		50
+#define SRST_GRF		55
+#define SRST_PMU		56
+#define SRST_PERIPH_AXI		57
+#define SRST_PERIPH_AHB		58
+#define SRST_PERIPH_APB		59
+#define SRST_PERIPH_NIU		60
+#define SRST_PDPERI_AHB_ARBI	61
+#define SRST_EMEM		62
+#define SRST_USB_PERI		63
+
+#define SRST_DMAC2		64
+#define SRST_MAC		66
+#define SRST_GPS		67
+#define SRST_RKPWM		69
+#define SRST_USBHOST0		72
+#define SRST_HSIC		73
+#define SRST_HSIC_AUX		74
+#define SRST_HSIC_PHY		75
+#define SRST_HSADC		76
+#define SRST_NANDC0		77
+#define SRST_SFC		79
+
+#define SRST_SPI0		83
+#define SRST_SPI1		84
+#define SRST_SPI2		85
+#define SRST_SARADC		87
+#define SRST_PDALIVE_NIU	88
+#define SRST_PDPMU_INTMEM	89
+#define SRST_PDPMU_NIU		90
+#define SRST_SGRF		91
+
+#define SRST_VIO_ARBI		96
+#define SRST_RGA_NIU		97
+#define SRST_VIO0_NIU_AXI	98
+#define SRST_VIO_NIU_AHB	99
+#define SRST_LCDC0_AXI		100
+#define SRST_LCDC0_AHB		101
+#define SRST_LCDC0_DCLK		102
+#define SRST_VIP		104
+#define SRST_RGA_CORE		105
+#define SRST_IEP_AXI		106
+#define SRST_IEP_AHB		107
+#define SRST_RGA_AXI		108
+#define SRST_RGA_AHB		109
+#define SRST_ISP		110
+#define SRST_EDP_24M		111
+
+#define SRST_VIDEO_AXI		112
+#define SRST_VIDEO_AHB		113
+#define SRST_MIPIDPHYTX		114
+#define SRST_MIPIDSI0		115
+#define SRST_MIPIDPHYRX		116
+#define SRST_MIPICSI		117
+#define SRST_GPU		120
+#define SRST_HDMI		121
+#define SRST_EDP		122
+#define SRST_PMU_PVTM		123
+#define SRST_CORE_PVTM		124
+#define SRST_GPU_PVTM		125
+#define SRST_GPU_SYS		126
+#define SRST_GPU_MEM_NIU	127
+
+#define SRST_MMC0		128
+#define SRST_SDIO0		129
+#define SRST_EMMC		131
+#define SRST_USBOTG_AHB		132
+#define SRST_USBOTG_PHY		133
+#define SRST_USBOTG_CON		134
+#define SRST_USBHOST0_AHB	135
+#define SRST_USBHOST0_PHY	136
+#define SRST_USBHOST0_CON	137
+#define SRST_USBOTG_UTMI	138
+#define SRST_USBHOST1_UTMI	139
+#define SRST_USB_ADP		141
+
+#define SRST_CORESIGHT		144
+#define SRST_PD_CORE_AHB_NOC	145
+#define SRST_PD_CORE_APB_NOC	146
+#define SRST_GIC		148
+#define SRST_LCDC_PWM0		149
+#define SRST_RGA_H2P_BRG	153
+#define SRST_VIDEO		154
+#define SRST_GPU_CFG_NIU	157
+#define SRST_TSADC		159
+
+#define SRST_DDRPHY0		160
+#define SRST_DDRPHY0_APB	161
+#define SRST_DDRCTRL0		162
+#define SRST_DDRCTRL0_APB	163
+#define SRST_VIDEO_NIU		165
+#define SRST_VIDEO_NIU_AHB	167
+#define SRST_DDRMSCH0		170
+#define SRST_PDBUS_AHB		173
+#define SRST_CRYPTO		174
+
+#define SRST_UART0		179
+#define SRST_UART1		180
+#define SRST_UART2		181
+#define SRST_UART3		182
+#define SRST_UART4		183
+#define SRST_SIMC		186
+#define SRST_TSP		188
+#define SRST_TSP_CLKIN0		189
+
+#define SRST_CORE_L0		192
+#define SRST_CORE_L1		193
+#define SRST_CORE_L2		194
+#define SRST_CORE_L3		195
+#define SRST_CORE_L0_PO		195
+#define SRST_CORE_L1_PO		197
+#define SRST_CORE_L2_PO		198
+#define SRST_CORE_L3_PO		199
+#define SRST_L2_L		200
+#define SRST_ADB_L		201
+#define SRST_PD_CORE_L_NIU	202
+#define SRST_CCI_SYS		203
+#define SRST_CCI_DDR		204
+#define SRST_CCI		205
+#define SRST_SOCDBG_L		206
+#define SRST_CORE_L_DBG		207
+
+#define SRST_CORE_B0_NC		208
+#define SRST_CORE_B0_PO_NC	209
+#define SRST_L2_B_NC		210
+#define SRST_ADB_B_NC		211
+#define SRST_PD_CORE_B_NIU_NC	212
+#define SRST_PDBUS_STRSYS_NC	213
+#define SRST_CORE_L0_NC		214
+#define SRST_CORE_L0_PO_NC	215
+#define SRST_L2_L_NC		216
+#define SRST_ADB_L_NC		217
+#define SRST_PD_CORE_L_NIU_NC	218
+#define SRST_CCI_SYS_NC		219
+#define SRST_CCI_DDR_NC		220
+#define SRST_CCI_NC		221
+#define SRST_TRACE_NC		222
+
+#define SRST_TIMER00		224
+#define SRST_TIMER01		225
+#define SRST_TIMER02		226
+#define SRST_TIMER03		227
+#define SRST_TIMER04		228
+#define SRST_TIMER05		229
+#define SRST_TIMER10		230
+#define SRST_TIMER11		231
+#define SRST_TIMER12		232
+#define SRST_TIMER13		233
+#define SRST_TIMER14		234
+#define SRST_TIMER15		235
+#define SRST_TIMER0_APB		236
+#define SRST_TIMER1_APB		237
+
+#endif
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/rk3399-cru.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/rk3399-cru.h
new file mode 100644
index 0000000000000000000000000000000000000000..22cb1dfa9004ac1ef00ab9aa59ee92c7ed4f8af2
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/rk3399-cru.h
@@ -0,0 +1,760 @@
+/*
+ * Copyright (c) 2016 Rockchip Electronics Co. Ltd.
+ * Author: Xing Zheng <zhengxing@rock-chips.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3399_H
+#define _DT_BINDINGS_CLK_ROCKCHIP_RK3399_H
+
+/* core clocks */
+#define PLL_APLLL			1
+#define PLL_APLLB			2
+#define PLL_DPLL			3
+#define PLL_CPLL			4
+#define PLL_GPLL			5
+#define PLL_NPLL			6
+#define PLL_VPLL			7
+#define ARMCLKL				8
+#define ARMCLKB				9
+
+/* sclk gates (special clocks) */
+#define SCLK_I2C1			65
+#define SCLK_I2C2			66
+#define SCLK_I2C3			67
+#define SCLK_I2C5			68
+#define SCLK_I2C6			69
+#define SCLK_I2C7			70
+#define SCLK_SPI0			71
+#define SCLK_SPI1			72
+#define SCLK_SPI2			73
+#define SCLK_SPI4			74
+#define SCLK_SPI5			75
+#define SCLK_SDMMC			76
+#define SCLK_SDIO			77
+#define SCLK_EMMC			78
+#define SCLK_TSADC			79
+#define SCLK_SARADC			80
+#define SCLK_UART0			81
+#define SCLK_UART1			82
+#define SCLK_UART2			83
+#define SCLK_UART3			84
+#define SCLK_SPDIF_8CH			85
+#define SCLK_I2S0_8CH			86
+#define SCLK_I2S1_8CH			87
+#define SCLK_I2S2_8CH			88
+#define SCLK_I2S_8CH_OUT		89
+#define SCLK_TIMER00			90
+#define SCLK_TIMER01			91
+#define SCLK_TIMER02			92
+#define SCLK_TIMER03			93
+#define SCLK_TIMER04			94
+#define SCLK_TIMER05			95
+#define SCLK_TIMER06			96
+#define SCLK_TIMER07			97
+#define SCLK_TIMER08			98
+#define SCLK_TIMER09			99
+#define SCLK_TIMER10			100
+#define SCLK_TIMER11			101
+#define SCLK_MACREF			102
+#define SCLK_MAC_RX			103
+#define SCLK_MAC_TX			104
+#define SCLK_MAC			105
+#define SCLK_MACREF_OUT			106
+#define SCLK_VOP0_PWM			107
+#define SCLK_VOP1_PWM			108
+#define SCLK_RGA_CORE			109
+#define SCLK_ISP0			110
+#define SCLK_ISP1			111
+#define SCLK_HDMI_CEC			112
+#define SCLK_HDMI_SFR			113
+#define SCLK_DP_CORE			114
+#define SCLK_PVTM_CORE_L		115
+#define SCLK_PVTM_CORE_B		116
+#define SCLK_PVTM_GPU			117
+#define SCLK_PVTM_DDR			118
+#define SCLK_MIPIDPHY_REF		119
+#define SCLK_MIPIDPHY_CFG		120
+#define SCLK_HSICPHY			121
+#define SCLK_USBPHY480M			122
+#define SCLK_USB2PHY0_REF		123
+#define SCLK_USB2PHY1_REF		124
+#define SCLK_UPHY0_TCPDPHY_REF		125
+#define SCLK_UPHY0_TCPDCORE		126
+#define SCLK_UPHY1_TCPDPHY_REF		127
+#define SCLK_UPHY1_TCPDCORE		128
+#define SCLK_USB3OTG0_REF		129
+#define SCLK_USB3OTG1_REF		130
+#define SCLK_USB3OTG0_SUSPEND		131
+#define SCLK_USB3OTG1_SUSPEND		132
+#define SCLK_CRYPTO0			133
+#define SCLK_CRYPTO1			134
+#define SCLK_CCI_TRACE			135
+#define SCLK_CS				136
+#define SCLK_CIF_OUT			137
+#define SCLK_PCIEPHY_REF		138
+#define SCLK_PCIE_CORE			139
+#define SCLK_M0_PERILP			140
+#define SCLK_M0_PERILP_DEC		141
+#define SCLK_CM0S			142
+#define SCLK_DBG_NOC			143
+#define SCLK_DBG_PD_CORE_B		144
+#define SCLK_DBG_PD_CORE_L		145
+#define SCLK_DFIMON0_TIMER		146
+#define SCLK_DFIMON1_TIMER		147
+#define SCLK_INTMEM0			148
+#define SCLK_INTMEM1			149
+#define SCLK_INTMEM2			150
+#define SCLK_INTMEM3			151
+#define SCLK_INTMEM4			152
+#define SCLK_INTMEM5			153
+#define SCLK_SDMMC_DRV			154
+#define SCLK_SDMMC_SAMPLE		155
+#define SCLK_SDIO_DRV			156
+#define SCLK_SDIO_SAMPLE		157
+#define SCLK_VDU_CORE			158
+#define SCLK_VDU_CA			159
+#define SCLK_PCIE_PM			160
+#define SCLK_SPDIF_REC_DPTX		161
+#define SCLK_DPHY_PLL			162
+#define SCLK_DPHY_TX0_CFG		163
+#define SCLK_DPHY_TX1RX1_CFG		164
+#define SCLK_DPHY_RX0_CFG		165
+#define SCLK_RMII_SRC			166
+#define SCLK_PCIEPHY_REF100M		167
+#define SCLK_DDRC			168
+#define SCLK_TESTCLKOUT1		169
+#define SCLK_TESTCLKOUT2		170
+
+#define DCLK_VOP0			180
+#define DCLK_VOP1			181
+#define DCLK_VOP0_DIV			182
+#define DCLK_VOP1_DIV			183
+#define DCLK_M0_PERILP			184
+#define DCLK_VOP0_FRAC			185
+#define DCLK_VOP1_FRAC			186
+
+#define FCLK_CM0S			190
+
+/* aclk gates */
+#define ACLK_PERIHP			192
+#define ACLK_PERIHP_NOC			193
+#define ACLK_PERILP0			194
+#define ACLK_PERILP0_NOC		195
+#define ACLK_PERF_PCIE			196
+#define ACLK_PCIE			197
+#define ACLK_INTMEM			198
+#define ACLK_TZMA			199
+#define ACLK_DCF			200
+#define ACLK_CCI			201
+#define ACLK_CCI_NOC0			202
+#define ACLK_CCI_NOC1			203
+#define ACLK_CCI_GRF			204
+#define ACLK_CENTER			205
+#define ACLK_CENTER_MAIN_NOC		206
+#define ACLK_CENTER_PERI_NOC		207
+#define ACLK_GPU			208
+#define ACLK_PERF_GPU			209
+#define ACLK_GPU_GRF			210
+#define ACLK_DMAC0_PERILP		211
+#define ACLK_DMAC1_PERILP		212
+#define ACLK_GMAC			213
+#define ACLK_GMAC_NOC			214
+#define ACLK_PERF_GMAC			215
+#define ACLK_VOP0_NOC			216
+#define ACLK_VOP0			217
+#define ACLK_VOP1_NOC			218
+#define ACLK_VOP1			219
+#define ACLK_RGA			220
+#define ACLK_RGA_NOC			221
+#define ACLK_HDCP			222
+#define ACLK_HDCP_NOC			223
+#define ACLK_HDCP22			224
+#define ACLK_IEP			225
+#define ACLK_IEP_NOC			226
+#define ACLK_VIO			227
+#define ACLK_VIO_NOC			228
+#define ACLK_ISP0			229
+#define ACLK_ISP1			230
+#define ACLK_ISP0_NOC			231
+#define ACLK_ISP1_NOC			232
+#define ACLK_ISP0_WRAPPER		233
+#define ACLK_ISP1_WRAPPER		234
+#define ACLK_VCODEC			235
+#define ACLK_VCODEC_NOC			236
+#define ACLK_VDU			237
+#define ACLK_VDU_NOC			238
+#define ACLK_PERI			239
+#define ACLK_EMMC			240
+#define ACLK_EMMC_CORE			241
+#define ACLK_EMMC_NOC			242
+#define ACLK_EMMC_GRF			243
+#define ACLK_USB3			244
+#define ACLK_USB3_NOC			245
+#define ACLK_USB3OTG0			246
+#define ACLK_USB3OTG1			247
+#define ACLK_USB3_RKSOC_AXI_PERF	248
+#define ACLK_USB3_GRF			249
+#define ACLK_GIC			250
+#define ACLK_GIC_NOC			251
+#define ACLK_GIC_ADB400_CORE_L_2_GIC	252
+#define ACLK_GIC_ADB400_CORE_B_2_GIC	253
+#define ACLK_GIC_ADB400_GIC_2_CORE_L	254
+#define ACLK_GIC_ADB400_GIC_2_CORE_B	255
+#define ACLK_CORE_ADB400_CORE_L_2_CCI500 256
+#define ACLK_CORE_ADB400_CORE_B_2_CCI500 257
+#define ACLK_ADB400M_PD_CORE_L		258
+#define ACLK_ADB400M_PD_CORE_B		259
+#define ACLK_PERF_CORE_L		260
+#define ACLK_PERF_CORE_B		261
+#define ACLK_GIC_PRE			262
+#define ACLK_VOP0_PRE			263
+#define ACLK_VOP1_PRE			264
+
+/* pclk gates */
+#define PCLK_PERIHP			320
+#define PCLK_PERIHP_NOC			321
+#define PCLK_PERILP0			322
+#define PCLK_PERILP1			323
+#define PCLK_PERILP1_NOC		324
+#define PCLK_PERILP_SGRF		325
+#define PCLK_PERIHP_GRF			326
+#define PCLK_PCIE			327
+#define PCLK_SGRF			328
+#define PCLK_INTR_ARB			329
+#define PCLK_CENTER_MAIN_NOC		330
+#define PCLK_CIC			331
+#define PCLK_COREDBG_B			332
+#define PCLK_COREDBG_L			333
+#define PCLK_DBG_CXCS_PD_CORE_B		334
+#define PCLK_DCF			335
+#define PCLK_GPIO2			336
+#define PCLK_GPIO3			337
+#define PCLK_GPIO4			338
+#define PCLK_GRF			339
+#define PCLK_HSICPHY			340
+#define PCLK_I2C1			341
+#define PCLK_I2C2			342
+#define PCLK_I2C3			343
+#define PCLK_I2C5			344
+#define PCLK_I2C6			345
+#define PCLK_I2C7			346
+#define PCLK_SPI0			347
+#define PCLK_SPI1			348
+#define PCLK_SPI2			349
+#define PCLK_SPI4			350
+#define PCLK_SPI5			351
+#define PCLK_UART0			352
+#define PCLK_UART1			353
+#define PCLK_UART2			354
+#define PCLK_UART3			355
+#define PCLK_TSADC			356
+#define PCLK_SARADC			357
+#define PCLK_GMAC			358
+#define PCLK_GMAC_NOC			359
+#define PCLK_TIMER0			360
+#define PCLK_TIMER1			361
+#define PCLK_EDP			362
+#define PCLK_EDP_NOC			363
+#define PCLK_EDP_CTRL			364
+#define PCLK_VIO			365
+#define PCLK_VIO_NOC			366
+#define PCLK_VIO_GRF			367
+#define PCLK_MIPI_DSI0			368
+#define PCLK_MIPI_DSI1			369
+#define PCLK_HDCP			370
+#define PCLK_HDCP_NOC			371
+#define PCLK_HDMI_CTRL			372
+#define PCLK_DP_CTRL			373
+#define PCLK_HDCP22			374
+#define PCLK_GASKET			375
+#define PCLK_DDR			376
+#define PCLK_DDR_MON			377
+#define PCLK_DDR_SGRF			378
+#define PCLK_ISP1_WRAPPER		379
+#define PCLK_WDT			380
+#define PCLK_EFUSE1024NS		381
+#define PCLK_EFUSE1024S			382
+#define PCLK_PMU_INTR_ARB		383
+#define PCLK_MAILBOX0			384
+#define PCLK_USBPHY_MUX_G		385
+#define PCLK_UPHY0_TCPHY_G		386
+#define PCLK_UPHY0_TCPD_G		387
+#define PCLK_UPHY1_TCPHY_G		388
+#define PCLK_UPHY1_TCPD_G		389
+#define PCLK_ALIVE			390
+
+/* hclk gates */
+#define HCLK_PERIHP			448
+#define HCLK_PERILP0			449
+#define HCLK_PERILP1			450
+#define HCLK_PERILP0_NOC		451
+#define HCLK_PERILP1_NOC		452
+#define HCLK_M0_PERILP			453
+#define HCLK_M0_PERILP_NOC		454
+#define HCLK_AHB1TOM			455
+#define HCLK_HOST0			456
+#define HCLK_HOST0_ARB			457
+#define HCLK_HOST1			458
+#define HCLK_HOST1_ARB			459
+#define HCLK_HSIC			460
+#define HCLK_SD				461
+#define HCLK_SDMMC			462
+#define HCLK_SDMMC_NOC			463
+#define HCLK_M_CRYPTO0			464
+#define HCLK_M_CRYPTO1			465
+#define HCLK_S_CRYPTO0			466
+#define HCLK_S_CRYPTO1			467
+#define HCLK_I2S0_8CH			468
+#define HCLK_I2S1_8CH			469
+#define HCLK_I2S2_8CH			470
+#define HCLK_SPDIF			471
+#define HCLK_VOP0_NOC			472
+#define HCLK_VOP0			473
+#define HCLK_VOP1_NOC			474
+#define HCLK_VOP1			475
+#define HCLK_ROM			476
+#define HCLK_IEP			477
+#define HCLK_IEP_NOC			478
+#define HCLK_ISP0			479
+#define HCLK_ISP1			480
+#define HCLK_ISP0_NOC			481
+#define HCLK_ISP1_NOC			482
+#define HCLK_ISP0_WRAPPER		483
+#define HCLK_ISP1_WRAPPER		484
+#define HCLK_RGA			485
+#define HCLK_RGA_NOC			486
+#define HCLK_HDCP			487
+#define HCLK_HDCP_NOC			488
+#define HCLK_HDCP22			489
+#define HCLK_VCODEC			490
+#define HCLK_VCODEC_NOC			491
+#define HCLK_VDU			492
+#define HCLK_VDU_NOC			493
+#define HCLK_SDIO			494
+#define HCLK_SDIO_NOC			495
+#define HCLK_SDIOAUDIO_NOC		496
+
+#define CLK_NR_CLKS			(HCLK_SDIOAUDIO_NOC + 1)
+
+/* pmu-clocks indices */
+
+#define PLL_PPLL			1
+
+#define SCLK_32K_SUSPEND_PMU		2
+#define SCLK_SPI3_PMU			3
+#define SCLK_TIMER12_PMU		4
+#define SCLK_TIMER13_PMU		5
+#define SCLK_UART4_PMU			6
+#define SCLK_PVTM_PMU			7
+#define SCLK_WIFI_PMU			8
+#define SCLK_I2C0_PMU			9
+#define SCLK_I2C4_PMU			10
+#define SCLK_I2C8_PMU			11
+
+#define PCLK_SRC_PMU			19
+#define PCLK_PMU			20
+#define PCLK_PMUGRF_PMU			21
+#define PCLK_INTMEM1_PMU		22
+#define PCLK_GPIO0_PMU			23
+#define PCLK_GPIO1_PMU			24
+#define PCLK_SGRF_PMU			25
+#define PCLK_NOC_PMU			26
+#define PCLK_I2C0_PMU			27
+#define PCLK_I2C4_PMU			28
+#define PCLK_I2C8_PMU			29
+#define PCLK_RKPWM_PMU			30
+#define PCLK_SPI3_PMU			31
+#define PCLK_TIMER_PMU			32
+#define PCLK_MAILBOX_PMU		33
+#define PCLK_UART4_PMU			34
+#define PCLK_WDT_M0_PMU			35
+
+#define FCLK_CM0S_SRC_PMU		44
+#define FCLK_CM0S_PMU			45
+#define SCLK_CM0S_PMU			46
+#define HCLK_CM0S_PMU			47
+#define DCLK_CM0S_PMU			48
+#define PCLK_INTR_ARB_PMU		49
+#define HCLK_NOC_PMU			50
+
+#define CLKPMU_NR_CLKS			(HCLK_NOC_PMU + 1)
+
+/* soft-reset indices */
+
+/* cru_softrst_con0 */
+#define SRST_CORE_L0			0
+#define SRST_CORE_B0			1
+#define SRST_CORE_PO_L0			2
+#define SRST_CORE_PO_B0			3
+#define SRST_L2_L			4
+#define SRST_L2_B			5
+#define SRST_ADB_L			6
+#define SRST_ADB_B			7
+#define SRST_A_CCI			8
+#define SRST_A_CCIM0_NOC		9
+#define SRST_A_CCIM1_NOC		10
+#define SRST_DBG_NOC			11
+
+/* cru_softrst_con1 */
+#define SRST_CORE_L0_T			16
+#define SRST_CORE_L1			17
+#define SRST_CORE_L2			18
+#define SRST_CORE_L3			19
+#define SRST_CORE_PO_L0_T		20
+#define SRST_CORE_PO_L1			21
+#define SRST_CORE_PO_L2			22
+#define SRST_CORE_PO_L3			23
+#define SRST_A_ADB400_GIC2COREL		24
+#define SRST_A_ADB400_COREL2GIC		25
+#define SRST_P_DBG_L			26
+#define SRST_L2_L_T			28
+#define SRST_ADB_L_T			29
+#define SRST_A_RKPERF_L			30
+#define SRST_PVTM_CORE_L		31
+
+/* cru_softrst_con2 */
+#define SRST_CORE_B0_T			32
+#define SRST_CORE_B1			33
+#define SRST_CORE_PO_B0_T		36
+#define SRST_CORE_PO_B1			37
+#define SRST_A_ADB400_GIC2COREB		40
+#define SRST_A_ADB400_COREB2GIC		41
+#define SRST_P_DBG_B			42
+#define SRST_L2_B_T			43
+#define SRST_ADB_B_T			45
+#define SRST_A_RKPERF_B			46
+#define SRST_PVTM_CORE_B		47
+
+/* cru_softrst_con3 */
+#define SRST_A_CCI_T			50
+#define SRST_A_CCIM0_NOC_T		51
+#define SRST_A_CCIM1_NOC_T		52
+#define SRST_A_ADB400M_PD_CORE_B_T	53
+#define SRST_A_ADB400M_PD_CORE_L_T	54
+#define SRST_DBG_NOC_T			55
+#define SRST_DBG_CXCS			56
+#define SRST_CCI_TRACE			57
+#define SRST_P_CCI_GRF			58
+
+/* cru_softrst_con4 */
+#define SRST_A_CENTER_MAIN_NOC		64
+#define SRST_A_CENTER_PERI_NOC		65
+#define SRST_P_CENTER_MAIN		66
+#define SRST_P_DDRMON			67
+#define SRST_P_CIC			68
+#define SRST_P_CENTER_SGRF		69
+#define SRST_DDR0_MSCH			70
+#define SRST_DDRCFG0_MSCH		71
+#define SRST_DDR0			72
+#define SRST_DDRPHY0			73
+#define SRST_DDR1_MSCH			74
+#define SRST_DDRCFG1_MSCH		75
+#define SRST_DDR1			76
+#define SRST_DDRPHY1			77
+#define SRST_DDR_CIC			78
+#define SRST_PVTM_DDR			79
+
+/* cru_softrst_con5 */
+#define SRST_A_VCODEC_NOC		80
+#define SRST_A_VCODEC			81
+#define SRST_H_VCODEC_NOC		82
+#define SRST_H_VCODEC			83
+#define SRST_A_VDU_NOC			88
+#define SRST_A_VDU			89
+#define SRST_H_VDU_NOC			90
+#define SRST_H_VDU			91
+#define SRST_VDU_CORE			92
+#define SRST_VDU_CA			93
+
+/* cru_softrst_con6 */
+#define SRST_A_IEP_NOC			96
+#define SRST_A_VOP_IEP			97
+#define SRST_A_IEP			98
+#define SRST_H_IEP_NOC			99
+#define SRST_H_IEP			100
+#define SRST_A_RGA_NOC			102
+#define SRST_A_RGA			103
+#define SRST_H_RGA_NOC			104
+#define SRST_H_RGA			105
+#define SRST_RGA_CORE			106
+#define SRST_EMMC_NOC			108
+#define SRST_EMMC			109
+#define SRST_EMMC_GRF			110
+
+/* cru_softrst_con7 */
+#define SRST_A_PERIHP_NOC		112
+#define SRST_P_PERIHP_GRF		113
+#define SRST_H_PERIHP_NOC		114
+#define SRST_USBHOST0			115
+#define SRST_HOSTC0_AUX			116
+#define SRST_HOST0_ARB			117
+#define SRST_USBHOST1			118
+#define SRST_HOSTC1_AUX			119
+#define SRST_HOST1_ARB			120
+#define SRST_SDIO0			121
+#define SRST_SDMMC			122
+#define SRST_HSIC			123
+#define SRST_HSIC_AUX			124
+#define SRST_AHB1TOM			125
+#define SRST_P_PERIHP_NOC		126
+#define SRST_HSICPHY			127
+
+/* cru_softrst_con8 */
+#define SRST_A_PCIE			128
+#define SRST_P_PCIE			129
+#define SRST_PCIE_CORE			130
+#define SRST_PCIE_MGMT			131
+#define SRST_PCIE_MGMT_STICKY		132
+#define SRST_PCIE_PIPE			133
+#define SRST_PCIE_PM			134
+#define SRST_PCIEPHY			135
+#define SRST_A_GMAC_NOC			136
+#define SRST_A_GMAC			137
+#define SRST_P_GMAC_NOC			138
+#define SRST_P_GMAC_GRF			140
+#define SRST_HSICPHY_POR		142
+#define SRST_HSICPHY_UTMI		143
+
+/* cru_softrst_con9 */
+#define SRST_USB2PHY0_POR		144
+#define SRST_USB2PHY0_UTMI_PORT0	145
+#define SRST_USB2PHY0_UTMI_PORT1	146
+#define SRST_USB2PHY0_EHCIPHY		147
+#define SRST_UPHY0_PIPE_L00		148
+#define SRST_UPHY0			149
+#define SRST_UPHY0_TCPDPWRUP		150
+#define SRST_USB2PHY1_POR		152
+#define SRST_USB2PHY1_UTMI_PORT0	153
+#define SRST_USB2PHY1_UTMI_PORT1	154
+#define SRST_USB2PHY1_EHCIPHY		155
+#define SRST_UPHY1_PIPE_L00		156
+#define SRST_UPHY1			157
+#define SRST_UPHY1_TCPDPWRUP		158
+
+/* cru_softrst_con10 */
+#define SRST_A_PERILP0_NOC		160
+#define SRST_A_DCF			161
+#define SRST_GIC500			162
+#define SRST_DMAC0_PERILP0		163
+#define SRST_DMAC1_PERILP0		164
+#define SRST_TZMA			165
+#define SRST_INTMEM			166
+#define SRST_ADB400_MST0		167
+#define SRST_ADB400_MST1		168
+#define SRST_ADB400_SLV0		169
+#define SRST_ADB400_SLV1		170
+#define SRST_H_PERILP0			171
+#define SRST_H_PERILP0_NOC		172
+#define SRST_ROM			173
+#define SRST_CRYPTO_S			174
+#define SRST_CRYPTO_M			175
+
+/* cru_softrst_con11 */
+#define SRST_P_DCF			176
+#define SRST_CM0S_NOC			177
+#define SRST_CM0S			178
+#define SRST_CM0S_DBG			179
+#define SRST_CM0S_PO			180
+#define SRST_CRYPTO			181
+#define SRST_P_PERILP1_SGRF		182
+#define SRST_P_PERILP1_GRF		183
+#define SRST_CRYPTO1_S			184
+#define SRST_CRYPTO1_M			185
+#define SRST_CRYPTO1			186
+#define SRST_GIC_NOC			188
+#define SRST_SD_NOC			189
+#define SRST_SDIOAUDIO_BRG		190
+
+/* cru_softrst_con12 */
+#define SRST_H_PERILP1			192
+#define SRST_H_PERILP1_NOC		193
+#define SRST_H_I2S0_8CH			194
+#define SRST_H_I2S1_8CH			195
+#define SRST_H_I2S2_8CH			196
+#define SRST_H_SPDIF_8CH		197
+#define SRST_P_PERILP1_NOC		198
+#define SRST_P_EFUSE_1024		199
+#define SRST_P_EFUSE_1024S		200
+#define SRST_P_I2C0			201
+#define SRST_P_I2C1			202
+#define SRST_P_I2C2			203
+#define SRST_P_I2C3			204
+#define SRST_P_I2C4			205
+#define SRST_P_I2C5			206
+#define SRST_P_MAILBOX0			207
+
+/* cru_softrst_con13 */
+#define SRST_P_UART0			208
+#define SRST_P_UART1			209
+#define SRST_P_UART2			210
+#define SRST_P_UART3			211
+#define SRST_P_SARADC			212
+#define SRST_P_TSADC			213
+#define SRST_P_SPI0			214
+#define SRST_P_SPI1			215
+#define SRST_P_SPI2			216
+#define SRST_P_SPI3			217
+#define SRST_P_SPI4			218
+#define SRST_SPI0			219
+#define SRST_SPI1			220
+#define SRST_SPI2			221
+#define SRST_SPI3			222
+#define SRST_SPI4			223
+
+/* cru_softrst_con14 */
+#define SRST_I2S0_8CH			224
+#define SRST_I2S1_8CH			225
+#define SRST_I2S2_8CH			226
+#define SRST_SPDIF_8CH			227
+#define SRST_UART0			228
+#define SRST_UART1			229
+#define SRST_UART2			230
+#define SRST_UART3			231
+#define SRST_TSADC			232
+#define SRST_I2C0			233
+#define SRST_I2C1			234
+#define SRST_I2C2			235
+#define SRST_I2C3			236
+#define SRST_I2C4			237
+#define SRST_I2C5			238
+#define SRST_SDIOAUDIO_NOC		239
+
+/* cru_softrst_con15 */
+#define SRST_A_VIO_NOC			240
+#define SRST_A_HDCP_NOC			241
+#define SRST_A_HDCP			242
+#define SRST_H_HDCP_NOC			243
+#define SRST_H_HDCP			244
+#define SRST_P_HDCP_NOC			245
+#define SRST_P_HDCP			246
+#define SRST_P_HDMI_CTRL		247
+#define SRST_P_DP_CTRL			248
+#define SRST_S_DP_CTRL			249
+#define SRST_C_DP_CTRL			250
+#define SRST_P_MIPI_DSI0		251
+#define SRST_P_MIPI_DSI1		252
+#define SRST_DP_CORE			253
+#define SRST_DP_I2S			254
+
+/* cru_softrst_con16 */
+#define SRST_GASKET			256
+#define SRST_VIO_GRF			258
+#define SRST_DPTX_SPDIF_REC		259
+#define SRST_HDMI_CTRL			260
+#define SRST_HDCP_CTRL			261
+#define SRST_A_ISP0_NOC			262
+#define SRST_A_ISP1_NOC			263
+#define SRST_H_ISP0_NOC			266
+#define SRST_H_ISP1_NOC			267
+#define SRST_H_ISP0			268
+#define SRST_H_ISP1			269
+#define SRST_ISP0			270
+#define SRST_ISP1			271
+
+/* cru_softrst_con17 */
+#define SRST_A_VOP0_NOC			272
+#define SRST_A_VOP1_NOC			273
+#define SRST_A_VOP0			274
+#define SRST_A_VOP1			275
+#define SRST_H_VOP0_NOC			276
+#define SRST_H_VOP1_NOC			277
+#define SRST_H_VOP0			278
+#define SRST_H_VOP1			279
+#define SRST_D_VOP0			280
+#define SRST_D_VOP1			281
+#define SRST_VOP0_PWM			282
+#define SRST_VOP1_PWM			283
+#define SRST_P_EDP_NOC			284
+#define SRST_P_EDP_CTRL			285
+
+/* cru_softrst_con18 */
+#define SRST_A_GPU			288
+#define SRST_A_GPU_NOC			289
+#define SRST_A_GPU_GRF			290
+#define SRST_PVTM_GPU			291
+#define SRST_A_USB3_NOC			292
+#define SRST_A_USB3_OTG0		293
+#define SRST_A_USB3_OTG1		294
+#define SRST_A_USB3_GRF			295
+#define SRST_PMU			296
+
+/* cru_softrst_con19 */
+#define SRST_P_TIMER0_5			304
+#define SRST_TIMER0			305
+#define SRST_TIMER1			306
+#define SRST_TIMER2			307
+#define SRST_TIMER3			308
+#define SRST_TIMER4			309
+#define SRST_TIMER5			310
+#define SRST_P_TIMER6_11		311
+#define SRST_TIMER6			312
+#define SRST_TIMER7			313
+#define SRST_TIMER8			314
+#define SRST_TIMER9			315
+#define SRST_TIMER10			316
+#define SRST_TIMER11			317
+#define SRST_P_INTR_ARB_PMU		318
+#define SRST_P_ALIVE_SGRF		319
+
+/* cru_softrst_con20 */
+#define SRST_P_GPIO2			320
+#define SRST_P_GPIO3			321
+#define SRST_P_GPIO4			322
+#define SRST_P_GRF			323
+#define SRST_P_ALIVE_NOC		324
+#define SRST_P_WDT0			325
+#define SRST_P_WDT1			326
+#define SRST_P_INTR_ARB			327
+#define SRST_P_UPHY0_DPTX		328
+#define SRST_P_UPHY0_APB		330
+#define SRST_P_UPHY0_TCPHY		332
+#define SRST_P_UPHY1_TCPHY		333
+#define SRST_P_UPHY0_TCPDCTRL		334
+#define SRST_P_UPHY1_TCPDCTRL		335
+
+/* pmu soft-reset indices */
+
+/* pmu_cru_softrst_con0 */
+#define SRST_P_NOC			0
+#define SRST_P_INTMEM			1
+#define SRST_H_CM0S			2
+#define SRST_H_CM0S_NOC			3
+#define SRST_DBG_CM0S			4
+#define SRST_PO_CM0S			5
+#define SRST_P_SPI6			6
+#define SRST_SPI6			7
+#define SRST_P_TIMER_0_1		8
+#define SRST_P_TIMER_0			9
+#define SRST_P_TIMER_1			10
+#define SRST_P_UART4			11
+#define SRST_UART4			12
+#define SRST_P_WDT			13
+
+/* pmu_cru_softrst_con1 */
+#define SRST_P_I2C6			16
+#define SRST_P_I2C7			17
+#define SRST_P_I2C8			18
+#define SRST_P_MAILBOX			19
+#define SRST_P_RKPWM			20
+#define SRST_P_PMUGRF			21
+#define SRST_P_SGRF			22
+#define SRST_P_GPIO0			23
+#define SRST_P_GPIO1			24
+#define SRST_P_CRU			25
+#define SRST_P_INTR			26
+#define SRST_PVTM			27
+#define SRST_I2C6			28
+#define SRST_I2C7			29
+#define SRST_I2C8			30
+
+#endif
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/rk3399-ddr.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/rk3399-ddr.h
new file mode 100644
index 0000000000000000000000000000000000000000..ed228084496351c64f3770fedb5050ef07cbf933
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/rk3399-ddr.h
@@ -0,0 +1,56 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+
+#ifndef DT_BINDINGS_DDR_H
+#define DT_BINDINGS_DDR_H
+
+/*
+ * DDR3 SDRAM Standard Speed Bins include tCK, tRCD, tRP, tRAS and tRC for
+ * each corresponding bin.
+ */
+
+/* DDR3-800 (5-5-5) */
+#define DDR3_800D	0
+/* DDR3-800 (6-6-6) */
+#define DDR3_800E	1
+/* DDR3-1066 (6-6-6) */
+#define DDR3_1066E	2
+/* DDR3-1066 (7-7-7) */
+#define DDR3_1066F	3
+/* DDR3-1066 (8-8-8) */
+#define DDR3_1066G	4
+/* DDR3-1333 (7-7-7) */
+#define DDR3_1333F	5
+/* DDR3-1333 (8-8-8) */
+#define DDR3_1333G	6
+/* DDR3-1333 (9-9-9) */
+#define DDR3_1333H	7
+/* DDR3-1333 (10-10-10) */
+#define DDR3_1333J 	8
+/* DDR3-1600 (8-8-8) */
+#define DDR3_1600G	9
+/* DDR3-1600 (9-9-9) */
+#define DDR3_1600H	10
+/* DDR3-1600 (10-10-10) */
+#define DDR3_1600J	11
+/* DDR3-1600 (11-11-11) */
+#define DDR3_1600K	12
+/* DDR3-1600 (10-10-10) */
+#define DDR3_1866J	13
+/* DDR3-1866 (11-11-11) */
+#define DDR3_1866K	14
+/* DDR3-1866 (12-12-12) */
+#define DDR3_1866L	15
+/* DDR3-1866 (13-13-13) */
+#define DDR3_1866M	16
+/* DDR3-2133 (11-11-11) */
+#define DDR3_2133K	17
+/* DDR3-2133 (12-12-12) */
+#define DDR3_2133L	18
+/* DDR3-2133 (13-13-13) */
+#define DDR3_2133M	19
+/* DDR3-2133 (14-14-14) */
+#define DDR3_2133N	20
+/* DDR3 ATF default */
+#define DDR3_DEFAULT	21
+
+#endif
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/rockchip,rk808.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/rockchip,rk808.h
new file mode 100644
index 0000000000000000000000000000000000000000..75dabfc6adc14aae4c2f4f24603244ad07cb9e4b
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/rockchip,rk808.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * This header provides constants clk index RK808 pmic clkout
+ */
+#ifndef _CLK_ROCKCHIP_RK808
+#define _CLK_ROCKCHIP_RK808
+
+/* CLOCKOUT index */
+#define RK808_CLKOUT0		0
+#define RK808_CLKOUT1		1
+
+#endif
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/rv1108-cru.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/rv1108-cru.h
new file mode 100644
index 0000000000000000000000000000000000000000..d8d0e0456dc24dc1d5d788b378103807d2dd8faa
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/rv1108-cru.h
@@ -0,0 +1,362 @@
+/*
+ * Copyright (c) 2016 Rockchip Electronics Co. Ltd.
+ * Author: Shawn Lin <shawn.lin@rock-chips.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RV1108_H
+#define _DT_BINDINGS_CLK_ROCKCHIP_RV1108_H
+
+/* pll id */
+#define PLL_APLL			0
+#define PLL_DPLL			1
+#define PLL_GPLL			2
+#define ARMCLK				3
+
+/* sclk gates (special clocks) */
+#define SCLK_SPI0			65
+#define SCLK_NANDC			67
+#define SCLK_SDMMC			68
+#define SCLK_SDIO			69
+#define SCLK_EMMC			71
+#define SCLK_UART0			72
+#define SCLK_UART1			73
+#define SCLK_UART2			74
+#define SCLK_I2S0			75
+#define SCLK_I2S1			76
+#define SCLK_I2S2			77
+#define SCLK_TIMER0			78
+#define SCLK_TIMER1			79
+#define SCLK_SFC			80
+#define SCLK_SDMMC_DRV			81
+#define SCLK_SDIO_DRV			82
+#define SCLK_EMMC_DRV			83
+#define SCLK_SDMMC_SAMPLE		84
+#define SCLK_SDIO_SAMPLE		85
+#define SCLK_EMMC_SAMPLE		86
+#define SCLK_VENC_CORE			87
+#define SCLK_HEVC_CORE			88
+#define SCLK_HEVC_CABAC			89
+#define SCLK_PWM0_PMU			90
+#define SCLK_I2C0_PMU			91
+#define SCLK_WIFI			92
+#define SCLK_CIFOUT			93
+#define SCLK_MIPI_CSI_OUT		94
+#define SCLK_CIF0			95
+#define SCLK_CIF1			96
+#define SCLK_CIF2			97
+#define SCLK_CIF3			98
+#define SCLK_DSP			99
+#define SCLK_DSP_IOP			100
+#define SCLK_DSP_EPP			101
+#define SCLK_DSP_EDP			102
+#define SCLK_DSP_EDAP			103
+#define SCLK_CVBS_HOST			104
+#define SCLK_HDMI_SFR			105
+#define SCLK_HDMI_CEC			106
+#define SCLK_CRYPTO			107
+#define SCLK_SPI			108
+#define SCLK_SARADC			109
+#define SCLK_TSADC			110
+#define SCLK_MAC_PRE			111
+#define SCLK_MAC			112
+#define SCLK_MAC_RX			113
+#define SCLK_MAC_REF			114
+#define SCLK_MAC_REFOUT			115
+#define SCLK_DSP_PFM			116
+#define SCLK_RGA			117
+#define SCLK_I2C1			118
+#define SCLK_I2C2			119
+#define SCLK_I2C3			120
+#define SCLK_PWM			121
+#define SCLK_ISP			122
+#define SCLK_USBPHY			123
+#define SCLK_I2S0_SRC			124
+#define SCLK_I2S1_SRC			125
+#define SCLK_I2S2_SRC			126
+#define SCLK_UART0_SRC			127
+#define SCLK_UART1_SRC			128
+#define SCLK_UART2_SRC			129
+
+#define DCLK_VOP_SRC			185
+#define DCLK_HDMIPHY			186
+#define DCLK_VOP			187
+
+/* aclk gates */
+#define ACLK_DMAC			192
+#define ACLK_PRE			193
+#define ACLK_CORE			194
+#define ACLK_ENMCORE			195
+#define ACLK_RKVENC			196
+#define ACLK_RKVDEC			197
+#define ACLK_VPU			198
+#define ACLK_CIF0			199
+#define ACLK_VIO0			200
+#define ACLK_VIO1			201
+#define ACLK_VOP			202
+#define ACLK_IEP			203
+#define ACLK_RGA			204
+#define ACLK_ISP			205
+#define ACLK_CIF1			206
+#define ACLK_CIF2			207
+#define ACLK_CIF3			208
+#define ACLK_PERI			209
+#define ACLK_GMAC			210
+
+/* pclk gates */
+#define PCLK_GPIO1			256
+#define PCLK_GPIO2			257
+#define PCLK_GPIO3			258
+#define PCLK_GRF			259
+#define PCLK_I2C1			260
+#define PCLK_I2C2			261
+#define PCLK_I2C3			262
+#define PCLK_SPI			263
+#define PCLK_SFC			264
+#define PCLK_UART0			265
+#define PCLK_UART1			266
+#define PCLK_UART2			267
+#define PCLK_TSADC			268
+#define PCLK_PWM			269
+#define PCLK_TIMER			270
+#define PCLK_PERI			271
+#define PCLK_GPIO0_PMU			272
+#define PCLK_I2C0_PMU			273
+#define PCLK_PWM0_PMU			274
+#define PCLK_ISP			275
+#define PCLK_VIO			276
+#define PCLK_MIPI_DSI			277
+#define PCLK_HDMI_CTRL			278
+#define PCLK_SARADC			279
+#define PCLK_DSP_CFG			280
+#define PCLK_BUS			281
+#define PCLK_EFUSE0			282
+#define PCLK_EFUSE1			283
+#define PCLK_WDT			284
+#define PCLK_GMAC			285
+
+/* hclk gates */
+#define HCLK_I2S0_8CH			320
+#define HCLK_I2S1_2CH			321
+#define HCLK_I2S2_2CH			322
+#define HCLK_NANDC			323
+#define HCLK_SDMMC			324
+#define HCLK_SDIO			325
+#define HCLK_EMMC			326
+#define HCLK_PERI			327
+#define HCLK_SFC			328
+#define HCLK_RKVENC			329
+#define HCLK_RKVDEC			330
+#define HCLK_CIF0			331
+#define HCLK_VIO			332
+#define HCLK_VOP			333
+#define HCLK_IEP			334
+#define HCLK_RGA			335
+#define HCLK_ISP			336
+#define HCLK_CRYPTO_MST			337
+#define HCLK_CRYPTO_SLV			338
+#define HCLK_HOST0			339
+#define HCLK_OTG			340
+#define HCLK_CIF1			341
+#define HCLK_CIF2			342
+#define HCLK_CIF3			343
+#define HCLK_BUS			344
+#define HCLK_VPU			345
+
+#define CLK_NR_CLKS			(HCLK_VPU + 1)
+
+/* reset id */
+#define SRST_CORE_PO_AD			0
+#define SRST_CORE_AD			1
+#define SRST_L2_AD			2
+#define SRST_CPU_NIU_AD			3
+#define SRST_CORE_PO			4
+#define SRST_CORE			5
+#define SRST_L2				6
+#define SRST_CORE_DBG			8
+#define PRST_DBG			9
+#define RST_DAP				10
+#define PRST_DBG_NIU			11
+#define ARST_STRC_SYS_AD		15
+
+#define SRST_DDRPHY_CLKDIV		16
+#define SRST_DDRPHY			17
+#define PRST_DDRPHY			18
+#define PRST_HDMIPHY			19
+#define PRST_VDACPHY			20
+#define PRST_VADCPHY			21
+#define PRST_MIPI_CSI_PHY		22
+#define PRST_MIPI_DSI_PHY		23
+#define PRST_ACODEC			24
+#define ARST_BUS_NIU			25
+#define PRST_TOP_NIU			26
+#define ARST_INTMEM			27
+#define HRST_ROM			28
+#define ARST_DMAC			29
+#define SRST_MSCH_NIU			30
+#define PRST_MSCH_NIU			31
+
+#define PRST_DDRUPCTL			32
+#define NRST_DDRUPCTL			33
+#define PRST_DDRMON			34
+#define HRST_I2S0_8CH			35
+#define MRST_I2S0_8CH			36
+#define HRST_I2S1_2CH			37
+#define MRST_IS21_2CH			38
+#define HRST_I2S2_2CH			39
+#define MRST_I2S2_2CH			40
+#define HRST_CRYPTO			41
+#define SRST_CRYPTO			42
+#define PRST_SPI			43
+#define SRST_SPI			44
+#define PRST_UART0			45
+#define PRST_UART1			46
+#define PRST_UART2			47
+
+#define SRST_UART0			48
+#define SRST_UART1			49
+#define SRST_UART2			50
+#define PRST_I2C1			51
+#define PRST_I2C2			52
+#define PRST_I2C3			53
+#define SRST_I2C1			54
+#define SRST_I2C2			55
+#define SRST_I2C3			56
+#define PRST_PWM1			58
+#define SRST_PWM1			60
+#define PRST_WDT			61
+#define PRST_GPIO1			62
+#define PRST_GPIO2			63
+
+#define PRST_GPIO3			64
+#define PRST_GRF			65
+#define PRST_EFUSE			66
+#define PRST_EFUSE512			67
+#define PRST_TIMER0			68
+#define SRST_TIMER0			69
+#define SRST_TIMER1			70
+#define PRST_TSADC			71
+#define SRST_TSADC			72
+#define PRST_SARADC			73
+#define SRST_SARADC			74
+#define HRST_SYSBUS			75
+#define PRST_USBGRF			76
+
+#define ARST_PERIPH_NIU			80
+#define HRST_PERIPH_NIU			81
+#define PRST_PERIPH_NIU			82
+#define HRST_PERIPH			83
+#define HRST_SDMMC			84
+#define HRST_SDIO			85
+#define HRST_EMMC			86
+#define HRST_NANDC			87
+#define NRST_NANDC			88
+#define HRST_SFC			89
+#define SRST_SFC			90
+#define ARST_GMAC			91
+#define HRST_OTG			92
+#define SRST_OTG			93
+#define SRST_OTG_ADP			94
+#define HRST_HOST0			95
+
+#define HRST_HOST0_AUX			96
+#define HRST_HOST0_ARB			97
+#define SRST_HOST0_EHCIPHY		98
+#define SRST_HOST0_UTMI			99
+#define SRST_USBPOR			100
+#define SRST_UTMI0			101
+#define SRST_UTMI1			102
+
+#define ARST_VIO0_NIU			102
+#define ARST_VIO1_NIU			103
+#define HRST_VIO_NIU			104
+#define PRST_VIO_NIU			105
+#define ARST_VOP			106
+#define HRST_VOP			107
+#define DRST_VOP			108
+#define ARST_IEP			109
+#define HRST_IEP			110
+#define ARST_RGA			111
+#define HRST_RGA			112
+#define SRST_RGA			113
+#define PRST_CVBS			114
+#define PRST_HDMI			115
+#define SRST_HDMI			116
+#define PRST_MIPI_DSI			117
+
+#define ARST_ISP_NIU			118
+#define HRST_ISP_NIU			119
+#define HRST_ISP			120
+#define SRST_ISP			121
+#define ARST_VIP0			122
+#define HRST_VIP0			123
+#define PRST_VIP0			124
+#define ARST_VIP1			125
+#define HRST_VIP1			126
+#define PRST_VIP1			127
+#define ARST_VIP2			128
+#define HRST_VIP2			129
+#define PRST_VIP2			120
+#define ARST_VIP3			121
+#define HRST_VIP3			122
+#define PRST_VIP4			123
+
+#define PRST_CIF1TO4			124
+#define SRST_CVBS_CLK			125
+#define HRST_CVBS			126
+
+#define ARST_VPU_NIU			140
+#define HRST_VPU_NIU			141
+#define ARST_VPU			142
+#define HRST_VPU			143
+#define ARST_RKVDEC_NIU			144
+#define HRST_RKVDEC_NIU			145
+#define ARST_RKVDEC			146
+#define HRST_RKVDEC			147
+#define SRST_RKVDEC_CABAC		148
+#define SRST_RKVDEC_CORE		149
+#define ARST_RKVENC_NIU			150
+#define HRST_RKVENC_NIU			151
+#define ARST_RKVENC			152
+#define HRST_RKVENC			153
+#define SRST_RKVENC_CORE		154
+
+#define SRST_DSP_CORE			156
+#define SRST_DSP_SYS			157
+#define SRST_DSP_GLOBAL			158
+#define SRST_DSP_OECM			159
+#define PRST_DSP_IOP_NIU		160
+#define ARST_DSP_EPP_NIU		161
+#define ARST_DSP_EDP_NIU		162
+#define PRST_DSP_DBG_NIU		163
+#define PRST_DSP_CFG_NIU		164
+#define PRST_DSP_GRF			165
+#define PRST_DSP_MAILBOX		166
+#define PRST_DSP_INTC			167
+#define PRST_DSP_PFM_MON		169
+#define SRST_DSP_PFM_MON		170
+#define ARST_DSP_EDAP_NIU		171
+
+#define SRST_PMU			172
+#define SRST_PMU_I2C0			173
+#define PRST_PMU_I2C0			174
+#define PRST_PMU_GPIO0			175
+#define PRST_PMU_INTMEM			176
+#define PRST_PMU_PWM0			177
+#define SRST_PMU_PWM0			178
+#define PRST_PMU_GRF			179
+#define SRST_PMU_NIU			180
+#define SRST_PMU_PVTM			181
+#define ARST_DSP_EDP_PERF		184
+#define ARST_DSP_EPP_PERF		185
+
+#endif /* _DT_BINDINGS_CLK_ROCKCHIP_RV1108_H */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/s3c2410.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/s3c2410.h
new file mode 100644
index 0000000000000000000000000000000000000000..352a7673fc69939a2c7f71679856732f654dddf1
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/s3c2410.h
@@ -0,0 +1,62 @@
+/*
+ * Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Device Tree binding constants clock controllers of Samsung S3C2410 and later.
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_SAMSUNG_S3C2410_CLOCK_H
+#define _DT_BINDINGS_CLOCK_SAMSUNG_S3C2410_CLOCK_H
+
+/*
+ * Let each exported clock get a unique index, which is used on DT-enabled
+ * platforms to lookup the clock from a clock specifier. These indices are
+ * therefore considered an ABI and so must not be changed. This implies
+ * that new clocks should be added either in free spaces between clock groups
+ * or at the end.
+ */
+
+/* Core clocks. */
+
+/* id 1 is reserved */
+#define MPLL			2
+#define UPLL			3
+#define FCLK			4
+#define HCLK			5
+#define PCLK			6
+#define UCLK			7
+#define ARMCLK			8
+
+/* pclk-gates */
+#define PCLK_UART0		16
+#define PCLK_UART1		17
+#define PCLK_UART2		18
+#define PCLK_I2C		19
+#define PCLK_SDI		20
+#define PCLK_SPI		21
+#define PCLK_ADC		22
+#define PCLK_AC97		23
+#define PCLK_I2S		24
+#define PCLK_PWM		25
+#define PCLK_RTC		26
+#define PCLK_GPIO		27
+
+
+/* hclk-gates */
+#define HCLK_LCD		32
+#define HCLK_USBH		33
+#define HCLK_USBD		34
+#define HCLK_NAND		35
+#define HCLK_CAM		36
+
+
+#define CAMIF			40
+
+
+/* Total number of clocks. */
+#define NR_CLKS			(CAMIF + 1)
+
+#endif /* _DT_BINDINGS_CLOCK_SAMSUNG_S3C2443_CLOCK_H */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/s3c2412.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/s3c2412.h
new file mode 100644
index 0000000000000000000000000000000000000000..aac1dcfda81cdb005fe8ff067768c3653a077b8f
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/s3c2412.h
@@ -0,0 +1,73 @@
+/*
+ * Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Device Tree binding constants clock controllers of Samsung S3C2412.
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_SAMSUNG_S3C2412_CLOCK_H
+#define _DT_BINDINGS_CLOCK_SAMSUNG_S3C2412_CLOCK_H
+
+/*
+ * Let each exported clock get a unique index, which is used on DT-enabled
+ * platforms to lookup the clock from a clock specifier. These indices are
+ * therefore considered an ABI and so must not be changed. This implies
+ * that new clocks should be added either in free spaces between clock groups
+ * or at the end.
+ */
+
+/* Core clocks. */
+
+/* id 1 is reserved */
+#define MPLL			2
+#define UPLL			3
+#define MDIVCLK			4
+#define MSYSCLK			5
+#define USYSCLK			6
+#define HCLK			7
+#define PCLK			8
+#define ARMDIV			9
+#define ARMCLK			10
+
+
+/* Special clocks */
+#define SCLK_CAM		16
+#define SCLK_UART		17
+#define SCLK_I2S		18
+#define SCLK_USBD		19
+#define SCLK_USBH		20
+
+/* pclk-gates */
+#define PCLK_WDT		32
+#define PCLK_SPI		33
+#define PCLK_I2S		34
+#define PCLK_I2C		35
+#define PCLK_ADC		36
+#define PCLK_RTC		37
+#define PCLK_GPIO		38
+#define PCLK_UART2		39
+#define PCLK_UART1		40
+#define PCLK_UART0		41
+#define PCLK_SDI		42
+#define PCLK_PWM		43
+#define PCLK_USBD		44
+
+/* hclk-gates */
+#define HCLK_HALF		48
+#define HCLK_X2			49
+#define HCLK_SDRAM		50
+#define HCLK_USBH		51
+#define HCLK_LCD		52
+#define HCLK_NAND		53
+#define HCLK_DMA3		54
+#define HCLK_DMA2		55
+#define HCLK_DMA1		56
+#define HCLK_DMA0		57
+
+/* Total number of clocks. */
+#define NR_CLKS			(HCLK_DMA0 + 1)
+
+#endif /* _DT_BINDINGS_CLOCK_SAMSUNG_S3C2412_CLOCK_H */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/s3c2443.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/s3c2443.h
new file mode 100644
index 0000000000000000000000000000000000000000..f3ba68a25ecb2a82dbb92169928165a11fb642e5
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/s3c2443.h
@@ -0,0 +1,94 @@
+/*
+ * Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Device Tree binding constants clock controllers of Samsung S3C2443 and later.
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_SAMSUNG_S3C2443_CLOCK_H
+#define _DT_BINDINGS_CLOCK_SAMSUNG_S3C2443_CLOCK_H
+
+/*
+ * Let each exported clock get a unique index, which is used on DT-enabled
+ * platforms to lookup the clock from a clock specifier. These indices are
+ * therefore considered an ABI and so must not be changed. This implies
+ * that new clocks should be added either in free spaces between clock groups
+ * or at the end.
+ */
+
+/* Core clocks. */
+#define MSYSCLK			1
+#define ESYSCLK			2
+#define ARMDIV			3
+#define ARMCLK			4
+#define HCLK			5
+#define PCLK			6
+#define MPLL			7
+#define EPLL			8
+
+/* Special clocks */
+#define SCLK_HSSPI0		16
+#define SCLK_FIMD		17
+#define SCLK_I2S0		18
+#define SCLK_I2S1		19
+#define SCLK_HSMMC1		20
+#define SCLK_HSMMC_EXT		21
+#define SCLK_CAM		22
+#define SCLK_UART		23
+#define SCLK_USBH		24
+
+/* Muxes */
+#define MUX_HSSPI0		32
+#define MUX_HSSPI1		33
+#define MUX_HSMMC0		34
+#define MUX_HSMMC1		35
+
+/* hclk-gates */
+#define HCLK_DMA0		48
+#define HCLK_DMA1		49
+#define HCLK_DMA2		50
+#define HCLK_DMA3		51
+#define HCLK_DMA4		52
+#define HCLK_DMA5		53
+#define HCLK_DMA6		54
+#define HCLK_DMA7		55
+#define HCLK_CAM		56
+#define HCLK_LCD		57
+#define HCLK_USBH		58
+#define HCLK_USBD		59
+#define HCLK_IROM		60
+#define HCLK_HSMMC0		61
+#define HCLK_HSMMC1		62
+#define HCLK_CFC		63
+#define HCLK_SSMC		64
+#define HCLK_DRAM		65
+#define HCLK_2D			66
+
+/* pclk-gates */
+#define PCLK_UART0		72
+#define PCLK_UART1		73
+#define PCLK_UART2		74
+#define PCLK_UART3		75
+#define PCLK_I2C0		76
+#define PCLK_SDI		77
+#define PCLK_SPI0		78
+#define PCLK_ADC		79
+#define PCLK_AC97		80
+#define PCLK_I2S0		81
+#define PCLK_PWM		82
+#define PCLK_WDT		83
+#define PCLK_RTC		84
+#define PCLK_GPIO		85
+#define PCLK_SPI1		86
+#define PCLK_CHIPID		87
+#define PCLK_I2C1		88
+#define PCLK_I2S1		89
+#define PCLK_PCM		90
+
+/* Total number of clocks. */
+#define NR_CLKS			(PCLK_PCM + 1)
+
+#endif /* _DT_BINDINGS_CLOCK_SAMSUNG_S3C2443_CLOCK_H */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/s5pv210-audss.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/s5pv210-audss.h
new file mode 100644
index 0000000000000000000000000000000000000000..fe57406e24de375d51b8cf0570390c26d4adda69
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/s5pv210-audss.h
@@ -0,0 +1,34 @@
+/*
+ * Copyright (c) 2014 Tomasz Figa <tomasz.figa@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This header provides constants for Samsung audio subsystem
+ * clock controller.
+ *
+ * The constants defined in this header are being used in dts
+ * and s5pv210 audss driver.
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_S5PV210_AUDSS_H
+#define _DT_BINDINGS_CLOCK_S5PV210_AUDSS_H
+
+#define CLK_MOUT_AUDSS		0
+#define CLK_MOUT_I2S_A		1
+
+#define CLK_DOUT_AUD_BUS	2
+#define CLK_DOUT_I2S_A		3
+
+#define CLK_I2S			4
+#define CLK_HCLK_I2S		5
+#define CLK_HCLK_UART		6
+#define CLK_HCLK_HWA		7
+#define CLK_HCLK_DMA		8
+#define CLK_HCLK_BUF		9
+#define CLK_HCLK_RP		10
+
+#define AUDSS_MAX_CLKS		11
+
+#endif
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/s5pv210.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/s5pv210.h
new file mode 100644
index 0000000000000000000000000000000000000000..e88986b7c6773c58410867447e6205a9c827c4b7
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/s5pv210.h
@@ -0,0 +1,239 @@
+/*
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * Author: Mateusz Krawczuk <m.krawczuk@partner.samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Device Tree binding constants for Samsung S5PV210 clock controller.
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_S5PV210_H
+#define _DT_BINDINGS_CLOCK_S5PV210_H
+
+/* Core clocks. */
+#define FIN_PLL			1
+#define FOUT_APLL		2
+#define FOUT_MPLL		3
+#define FOUT_EPLL		4
+#define FOUT_VPLL		5
+
+/* Muxes. */
+#define MOUT_FLASH		6
+#define MOUT_PSYS		7
+#define MOUT_DSYS		8
+#define MOUT_MSYS		9
+#define MOUT_VPLL		10
+#define MOUT_EPLL		11
+#define MOUT_MPLL		12
+#define MOUT_APLL		13
+#define MOUT_VPLLSRC		14
+#define MOUT_CSIS		15
+#define MOUT_FIMD		16
+#define MOUT_CAM1		17
+#define MOUT_CAM0		18
+#define MOUT_DAC		19
+#define MOUT_MIXER		20
+#define MOUT_HDMI		21
+#define MOUT_G2D		22
+#define MOUT_MFC		23
+#define MOUT_G3D		24
+#define MOUT_FIMC2		25
+#define MOUT_FIMC1		26
+#define MOUT_FIMC0		27
+#define MOUT_UART3		28
+#define MOUT_UART2		29
+#define MOUT_UART1		30
+#define MOUT_UART0		31
+#define MOUT_MMC3		32
+#define MOUT_MMC2		33
+#define MOUT_MMC1		34
+#define MOUT_MMC0		35
+#define MOUT_PWM		36
+#define MOUT_SPI0		37
+#define MOUT_SPI1		38
+#define MOUT_DMC0		39
+#define MOUT_PWI		40
+#define MOUT_HPM		41
+#define MOUT_SPDIF		42
+#define MOUT_AUDIO2		43
+#define MOUT_AUDIO1		44
+#define MOUT_AUDIO0		45
+
+/* Dividers. */
+#define DOUT_PCLKP		46
+#define DOUT_HCLKP		47
+#define DOUT_PCLKD		48
+#define DOUT_HCLKD		49
+#define DOUT_PCLKM		50
+#define DOUT_HCLKM		51
+#define DOUT_A2M		52
+#define DOUT_APLL		53
+#define DOUT_CSIS		54
+#define DOUT_FIMD		55
+#define DOUT_CAM1		56
+#define DOUT_CAM0		57
+#define DOUT_TBLK		58
+#define DOUT_G2D		59
+#define DOUT_MFC		60
+#define DOUT_G3D		61
+#define DOUT_FIMC2		62
+#define DOUT_FIMC1		63
+#define DOUT_FIMC0		64
+#define DOUT_UART3		65
+#define DOUT_UART2		66
+#define DOUT_UART1		67
+#define DOUT_UART0		68
+#define DOUT_MMC3		69
+#define DOUT_MMC2		70
+#define DOUT_MMC1		71
+#define DOUT_MMC0		72
+#define DOUT_PWM		73
+#define DOUT_SPI1		74
+#define DOUT_SPI0		75
+#define DOUT_DMC0		76
+#define DOUT_PWI		77
+#define DOUT_HPM		78
+#define DOUT_COPY		79
+#define DOUT_FLASH		80
+#define DOUT_AUDIO2		81
+#define DOUT_AUDIO1		82
+#define DOUT_AUDIO0		83
+#define DOUT_DPM		84
+#define DOUT_DVSEM		85
+
+/* Gates */
+#define SCLK_FIMC		86
+#define CLK_CSIS		87
+#define CLK_ROTATOR		88
+#define CLK_FIMC2		89
+#define CLK_FIMC1		90
+#define CLK_FIMC0		91
+#define CLK_MFC			92
+#define CLK_G2D			93
+#define CLK_G3D			94
+#define CLK_IMEM		95
+#define CLK_PDMA1		96
+#define CLK_PDMA0		97
+#define CLK_MDMA		98
+#define CLK_DMC1		99
+#define CLK_DMC0		100
+#define CLK_NFCON		101
+#define CLK_SROMC		102
+#define CLK_CFCON		103
+#define CLK_NANDXL		104
+#define CLK_USB_HOST		105
+#define CLK_USB_OTG		106
+#define CLK_HDMI		107
+#define CLK_TVENC		108
+#define CLK_MIXER		109
+#define CLK_VP			110
+#define CLK_DSIM		111
+#define CLK_FIMD		112
+#define CLK_TZIC3		113
+#define CLK_TZIC2		114
+#define CLK_TZIC1		115
+#define CLK_TZIC0		116
+#define CLK_VIC3		117
+#define CLK_VIC2		118
+#define CLK_VIC1		119
+#define CLK_VIC0		120
+#define CLK_TSI			121
+#define CLK_HSMMC3		122
+#define CLK_HSMMC2		123
+#define CLK_HSMMC1		124
+#define CLK_HSMMC0		125
+#define CLK_JTAG		126
+#define CLK_MODEMIF		127
+#define CLK_CORESIGHT		128
+#define CLK_SDM			129
+#define CLK_SECSS		130
+#define CLK_PCM2		131
+#define CLK_PCM1		132
+#define CLK_PCM0		133
+#define CLK_SYSCON		134
+#define CLK_GPIO		135
+#define CLK_TSADC		136
+#define CLK_PWM			137
+#define CLK_WDT			138
+#define CLK_KEYIF		139
+#define CLK_UART3		140
+#define CLK_UART2		141
+#define CLK_UART1		142
+#define CLK_UART0		143
+#define CLK_SYSTIMER		144
+#define CLK_RTC			145
+#define CLK_SPI1		146
+#define CLK_SPI0		147
+#define CLK_I2C_HDMI_PHY	148
+#define CLK_I2C1		149
+#define CLK_I2C2		150
+#define CLK_I2C0		151
+#define CLK_I2S1		152
+#define CLK_I2S2		153
+#define CLK_I2S0		154
+#define CLK_AC97		155
+#define CLK_SPDIF		156
+#define CLK_TZPC3		157
+#define CLK_TZPC2		158
+#define CLK_TZPC1		159
+#define CLK_TZPC0		160
+#define CLK_SECKEY		161
+#define CLK_IEM_APC		162
+#define CLK_IEM_IEC		163
+#define CLK_CHIPID		164
+#define CLK_JPEG		163
+
+/* Special clocks*/
+#define SCLK_PWI		164
+#define SCLK_SPDIF		165
+#define SCLK_AUDIO2		166
+#define SCLK_AUDIO1		167
+#define SCLK_AUDIO0		168
+#define SCLK_PWM		169
+#define SCLK_SPI1		170
+#define SCLK_SPI0		171
+#define SCLK_UART3		172
+#define SCLK_UART2		173
+#define SCLK_UART1		174
+#define SCLK_UART0		175
+#define SCLK_MMC3		176
+#define SCLK_MMC2		177
+#define SCLK_MMC1		178
+#define SCLK_MMC0		179
+#define SCLK_FINVPLL		180
+#define SCLK_CSIS		181
+#define SCLK_FIMD		182
+#define SCLK_CAM1		183
+#define SCLK_CAM0		184
+#define SCLK_DAC		185
+#define SCLK_MIXER		186
+#define SCLK_HDMI		187
+#define SCLK_FIMC2		188
+#define SCLK_FIMC1		189
+#define SCLK_FIMC0		190
+#define SCLK_HDMI27M		191
+#define SCLK_HDMIPHY		192
+#define SCLK_USBPHY0		193
+#define SCLK_USBPHY1		194
+
+/* S5P6442-specific clocks */
+#define MOUT_D0SYNC		195
+#define MOUT_D1SYNC		196
+#define DOUT_MIXER		197
+#define CLK_ETB			198
+#define CLK_ETM			199
+
+/* CLKOUT */
+#define FOUT_APLL_CLKOUT	200
+#define FOUT_MPLL_CLKOUT	201
+#define DOUT_APLL_CLKOUT	202
+#define MOUT_CLKSEL		203
+#define DOUT_CLKOUT		204
+#define MOUT_CLKOUT		205
+
+/* Total number of clocks. */
+#define NR_CLKS			206
+
+#endif /* _DT_BINDINGS_CLOCK_S5PV210_H */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/samsung,s2mps11.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/samsung,s2mps11.h
new file mode 100644
index 0000000000000000000000000000000000000000..b903d7de27c92e2fda9ca66b685c9fea953a372d
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/samsung,s2mps11.h
@@ -0,0 +1,23 @@
+/*
+ * Copyright (C) 2015 Markus Reichl
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Device Tree binding constants clocks for the Samsung S2MPS11 PMIC.
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_SAMSUNG_S2MPS11_CLOCK_H
+#define _DT_BINDINGS_CLOCK_SAMSUNG_S2MPS11_CLOCK_H
+
+/* Fixed rate clocks. */
+
+#define S2MPS11_CLK_AP		0
+#define S2MPS11_CLK_CP		1
+#define S2MPS11_CLK_BT		2
+
+/* Total number of clocks. */
+#define S2MPS11_CLKS_NUM		(S2MPS11_CLK_BT + 1)
+
+#endif /* _DT_BINDINGS_CLOCK_SAMSUNG_S2MPS11_CLOCK_H */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/samsung,s3c64xx-clock.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/samsung,s3c64xx-clock.h
new file mode 100644
index 0000000000000000000000000000000000000000..ad95c7f50090c749c32c7fe6f7936f179f240606
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/samsung,s3c64xx-clock.h
@@ -0,0 +1,178 @@
+/*
+ * Copyright (c) 2013 Tomasz Figa <tomasz.figa at gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Device Tree binding constants for Samsung S3C64xx clock controller.
+*/
+
+#ifndef _DT_BINDINGS_CLOCK_SAMSUNG_S3C64XX_CLOCK_H
+#define _DT_BINDINGS_CLOCK_SAMSUNG_S3C64XX_CLOCK_H
+
+/*
+ * Let each exported clock get a unique index, which is used on DT-enabled
+ * platforms to lookup the clock from a clock specifier. These indices are
+ * therefore considered an ABI and so must not be changed. This implies
+ * that new clocks should be added either in free spaces between clock groups
+ * or at the end.
+ */
+
+/* Core clocks. */
+#define CLK27M			1
+#define CLK48M			2
+#define FOUT_APLL		3
+#define FOUT_MPLL		4
+#define FOUT_EPLL		5
+#define ARMCLK			6
+#define HCLKX2			7
+#define HCLK			8
+#define PCLK			9
+
+/* HCLK bus clocks. */
+#define HCLK_3DSE		16
+#define HCLK_UHOST		17
+#define HCLK_SECUR		18
+#define HCLK_SDMA1		19
+#define HCLK_SDMA0		20
+#define HCLK_IROM		21
+#define HCLK_DDR1		22
+#define HCLK_MEM1		23
+#define HCLK_MEM0		24
+#define HCLK_USB		25
+#define HCLK_HSMMC2		26
+#define HCLK_HSMMC1		27
+#define HCLK_HSMMC0		28
+#define HCLK_MDP		29
+#define HCLK_DHOST		30
+#define HCLK_IHOST		31
+#define HCLK_DMA1		32
+#define HCLK_DMA0		33
+#define HCLK_JPEG		34
+#define HCLK_CAMIF		35
+#define HCLK_SCALER		36
+#define HCLK_2D			37
+#define HCLK_TV			38
+#define HCLK_POST0		39
+#define HCLK_ROT		40
+#define HCLK_LCD		41
+#define HCLK_TZIC		42
+#define HCLK_INTC		43
+#define HCLK_MFC		44
+#define HCLK_DDR0		45
+
+/* PCLK bus clocks. */
+#define PCLK_IIC1		48
+#define PCLK_IIS2		49
+#define PCLK_SKEY		50
+#define PCLK_CHIPID		51
+#define PCLK_SPI1		52
+#define PCLK_SPI0		53
+#define PCLK_HSIRX		54
+#define PCLK_HSITX		55
+#define PCLK_GPIO		56
+#define PCLK_IIC0		57
+#define PCLK_IIS1		58
+#define PCLK_IIS0		59
+#define PCLK_AC97		60
+#define PCLK_TZPC		61
+#define PCLK_TSADC		62
+#define PCLK_KEYPAD		63
+#define PCLK_IRDA		64
+#define PCLK_PCM1		65
+#define PCLK_PCM0		66
+#define PCLK_PWM		67
+#define PCLK_RTC		68
+#define PCLK_WDT		69
+#define PCLK_UART3		70
+#define PCLK_UART2		71
+#define PCLK_UART1		72
+#define PCLK_UART0		73
+#define PCLK_MFC		74
+
+/* Special clocks. */
+#define SCLK_UHOST		80
+#define SCLK_MMC2_48		81
+#define SCLK_MMC1_48		82
+#define SCLK_MMC0_48		83
+#define SCLK_MMC2		84
+#define SCLK_MMC1		85
+#define SCLK_MMC0		86
+#define SCLK_SPI1_48		87
+#define SCLK_SPI0_48		88
+#define SCLK_SPI1		89
+#define SCLK_SPI0		90
+#define SCLK_DAC27		91
+#define SCLK_TV27		92
+#define SCLK_SCALER27		93
+#define SCLK_SCALER		94
+#define SCLK_LCD27		95
+#define SCLK_LCD		96
+#define SCLK_FIMC		97
+#define SCLK_POST0_27		98
+#define SCLK_AUDIO2		99
+#define SCLK_POST0		100
+#define SCLK_AUDIO1		101
+#define SCLK_AUDIO0		102
+#define SCLK_SECUR		103
+#define SCLK_IRDA		104
+#define SCLK_UART		105
+#define SCLK_MFC		106
+#define SCLK_CAM		107
+#define SCLK_JPEG		108
+#define SCLK_ONENAND		109
+
+/* MEM0 bus clocks - S3C6410-specific. */
+#define MEM0_CFCON		112
+#define MEM0_ONENAND1		113
+#define MEM0_ONENAND0		114
+#define MEM0_NFCON		115
+#define MEM0_SROM		116
+
+/* Muxes. */
+#define MOUT_APLL		128
+#define MOUT_MPLL		129
+#define MOUT_EPLL		130
+#define MOUT_MFC		131
+#define MOUT_AUDIO0		132
+#define MOUT_AUDIO1		133
+#define MOUT_UART		134
+#define MOUT_SPI0		135
+#define MOUT_SPI1		136
+#define MOUT_MMC0		137
+#define MOUT_MMC1		138
+#define MOUT_MMC2		139
+#define MOUT_UHOST		140
+#define MOUT_IRDA		141
+#define MOUT_LCD		142
+#define MOUT_SCALER		143
+#define MOUT_DAC27		144
+#define MOUT_TV27		145
+#define MOUT_AUDIO2		146
+
+/* Dividers. */
+#define DOUT_MPLL		160
+#define DOUT_SECUR		161
+#define DOUT_CAM		162
+#define DOUT_JPEG		163
+#define DOUT_MFC		164
+#define DOUT_MMC0		165
+#define DOUT_MMC1		166
+#define DOUT_MMC2		167
+#define DOUT_LCD		168
+#define DOUT_SCALER		169
+#define DOUT_UHOST		170
+#define DOUT_SPI0		171
+#define DOUT_SPI1		172
+#define DOUT_AUDIO0		173
+#define DOUT_AUDIO1		174
+#define DOUT_UART		175
+#define DOUT_IRDA		176
+#define DOUT_FIMC		177
+#define DOUT_AUDIO2		178
+
+/* Total number of clocks. */
+#define NR_CLKS			(DOUT_AUDIO2 + 1)
+
+#endif /* _DT_BINDINGS_CLOCK_SAMSUNG_S3C64XX_CLOCK_H */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/sh73a0-clock.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/sh73a0-clock.h
new file mode 100644
index 0000000000000000000000000000000000000000..2eca353a29d74bc6fb8d8983473b13b4752c3866
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/sh73a0-clock.h
@@ -0,0 +1,86 @@
+/*
+ * Copyright 2014 Ulrich Hecht
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_SH73A0_H__
+#define __DT_BINDINGS_CLOCK_SH73A0_H__
+
+/* CPG */
+#define SH73A0_CLK_MAIN		0
+#define SH73A0_CLK_PLL0		1
+#define SH73A0_CLK_PLL1		2
+#define SH73A0_CLK_PLL2		3
+#define SH73A0_CLK_PLL3		4
+#define SH73A0_CLK_DSI0PHY	5
+#define SH73A0_CLK_DSI1PHY	6
+#define SH73A0_CLK_ZG		7
+#define SH73A0_CLK_M3		8
+#define SH73A0_CLK_B		9
+#define SH73A0_CLK_M1		10
+#define SH73A0_CLK_M2		11
+#define SH73A0_CLK_Z		12
+#define SH73A0_CLK_ZX		13
+#define SH73A0_CLK_HP		14
+
+/* MSTP0 */
+#define SH73A0_CLK_IIC2		1
+#define SH73A0_CLK_MSIOF0	0
+
+/* MSTP1 */
+#define SH73A0_CLK_CEU1		29
+#define SH73A0_CLK_CSI2_RX1	28
+#define SH73A0_CLK_CEU0		27
+#define SH73A0_CLK_CSI2_RX0	26
+#define SH73A0_CLK_TMU0		25
+#define SH73A0_CLK_DSITX0	18
+#define SH73A0_CLK_IIC0		16
+#define SH73A0_CLK_SGX		12
+#define SH73A0_CLK_LCDC0	0
+
+/* MSTP2 */
+#define SH73A0_CLK_SCIFA7	19
+#define SH73A0_CLK_SY_DMAC	18
+#define SH73A0_CLK_MP_DMAC	17
+#define SH73A0_CLK_MSIOF3	15
+#define SH73A0_CLK_MSIOF1	8
+#define SH73A0_CLK_SCIFA5	7
+#define SH73A0_CLK_SCIFB	6
+#define SH73A0_CLK_MSIOF2	5
+#define SH73A0_CLK_SCIFA0	4
+#define SH73A0_CLK_SCIFA1	3
+#define SH73A0_CLK_SCIFA2	2
+#define SH73A0_CLK_SCIFA3	1
+#define SH73A0_CLK_SCIFA4	0
+
+/* MSTP3 */
+#define SH73A0_CLK_SCIFA6	31
+#define SH73A0_CLK_CMT1		29
+#define SH73A0_CLK_FSI		28
+#define SH73A0_CLK_IRDA		25
+#define SH73A0_CLK_IIC1		23
+#define SH73A0_CLK_USB		22
+#define SH73A0_CLK_FLCTL	15
+#define SH73A0_CLK_SDHI0	14
+#define SH73A0_CLK_SDHI1	13
+#define SH73A0_CLK_MMCIF0	12
+#define SH73A0_CLK_SDHI2	11
+#define SH73A0_CLK_TPU0		4
+#define SH73A0_CLK_TPU1		3
+#define SH73A0_CLK_TPU2		2
+#define SH73A0_CLK_TPU3		1
+#define SH73A0_CLK_TPU4		0
+
+/* MSTP4 */
+#define SH73A0_CLK_IIC3		11
+#define SH73A0_CLK_IIC4		10
+#define SH73A0_CLK_KEYSC	3
+
+/* MSTP5 */
+#define SH73A0_CLK_INTCA0	8
+
+#endif
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/sprd,sc9860-clk.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/sprd,sc9860-clk.h
new file mode 100644
index 0000000000000000000000000000000000000000..f2ab4631df0dd850504d5b2b9ee433e55e73f4d3
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/sprd,sc9860-clk.h
@@ -0,0 +1,423 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+//
+// Spreadtrum SC9860 platform clocks
+//
+// Copyright (C) 2017, Spreadtrum Communications Inc.
+
+#ifndef _DT_BINDINGS_CLK_SC9860_H_
+#define _DT_BINDINGS_CLK_SC9860_H_
+
+#define	CLK_FAC_4M		0
+#define	CLK_FAC_2M		1
+#define	CLK_FAC_1M		2
+#define	CLK_FAC_250K		3
+#define	CLK_FAC_RPLL0_26M	4
+#define	CLK_FAC_RPLL1_26M	5
+#define	CLK_FAC_RCO25M		6
+#define	CLK_FAC_RCO4M		7
+#define	CLK_FAC_RCO2M		8
+#define	CLK_FAC_3K2		9
+#define	CLK_FAC_1K		10
+#define	CLK_MPLL0_GATE		11
+#define	CLK_MPLL1_GATE		12
+#define	CLK_DPLL0_GATE		13
+#define	CLK_DPLL1_GATE		14
+#define	CLK_LTEPLL0_GATE	15
+#define	CLK_TWPLL_GATE		16
+#define	CLK_LTEPLL1_GATE	17
+#define	CLK_RPLL0_GATE		18
+#define	CLK_RPLL1_GATE		19
+#define	CLK_CPPLL_GATE		20
+#define	CLK_GPLL_GATE		21
+#define CLK_PMU_GATE_NUM	(CLK_GPLL_GATE + 1)
+
+#define	CLK_MPLL0		0
+#define	CLK_MPLL1		1
+#define	CLK_DPLL0		2
+#define	CLK_DPLL1		3
+#define	CLK_RPLL0		4
+#define	CLK_RPLL1		5
+#define	CLK_TWPLL		6
+#define	CLK_LTEPLL0		7
+#define	CLK_LTEPLL1		8
+#define	CLK_GPLL		9
+#define	CLK_CPPLL		10
+#define	CLK_GPLL_42M5		11
+#define	CLK_TWPLL_768M		12
+#define	CLK_TWPLL_384M		13
+#define	CLK_TWPLL_192M		14
+#define	CLK_TWPLL_96M		15
+#define	CLK_TWPLL_48M		16
+#define	CLK_TWPLL_24M		17
+#define	CLK_TWPLL_12M		18
+#define	CLK_TWPLL_512M		19
+#define	CLK_TWPLL_256M		20
+#define	CLK_TWPLL_128M		21
+#define	CLK_TWPLL_64M		22
+#define	CLK_TWPLL_307M2		23
+#define	CLK_TWPLL_153M6		24
+#define	CLK_TWPLL_76M8		25
+#define	CLK_TWPLL_51M2		26
+#define	CLK_TWPLL_38M4		27
+#define	CLK_TWPLL_19M2		28
+#define	CLK_L0_614M4		29
+#define	CLK_L0_409M6		30
+#define	CLK_L0_38M		31
+#define	CLK_L1_38M		32
+#define	CLK_RPLL0_192M		33
+#define	CLK_RPLL0_96M		34
+#define	CLK_RPLL0_48M		35
+#define	CLK_RPLL1_468M		36
+#define	CLK_RPLL1_192M		37
+#define	CLK_RPLL1_96M		38
+#define	CLK_RPLL1_64M		39
+#define	CLK_RPLL1_48M		40
+#define	CLK_DPLL0_50M		41
+#define	CLK_DPLL1_50M		42
+#define	CLK_CPPLL_50M		43
+#define	CLK_M0_39M		44
+#define	CLK_M1_63M		45
+#define CLK_PLL_NUM		(CLK_M1_63M + 1)
+
+
+#define	CLK_AP_APB		0
+#define	CLK_AP_USB3		1
+#define	CLK_UART0		2
+#define	CLK_UART1		3
+#define	CLK_UART2		4
+#define	CLK_UART3		5
+#define	CLK_UART4		6
+#define	CLK_I2C0		7
+#define	CLK_I2C1		8
+#define	CLK_I2C2		9
+#define	CLK_I2C3		10
+#define	CLK_I2C4		11
+#define	CLK_I2C5		12
+#define	CLK_SPI0		13
+#define	CLK_SPI1		14
+#define	CLK_SPI2		15
+#define	CLK_SPI3		16
+#define	CLK_IIS0		17
+#define	CLK_IIS1		18
+#define	CLK_IIS2		19
+#define	CLK_IIS3		20
+#define CLK_AP_CLK_NUM		(CLK_IIS3 + 1)
+
+#define	CLK_AON_APB		0
+#define	CLK_AUX0		1
+#define	CLK_AUX1		2
+#define	CLK_AUX2		3
+#define	CLK_PROBE		4
+#define	CLK_SP_AHB		5
+#define	CLK_CCI			6
+#define	CLK_GIC			7
+#define	CLK_CSSYS		8
+#define	CLK_SDIO0_2X		9
+#define	CLK_SDIO1_2X		10
+#define	CLK_SDIO2_2X		11
+#define	CLK_EMMC_2X		12
+#define	CLK_SDIO0_1X		13
+#define	CLK_SDIO1_1X		14
+#define	CLK_SDIO2_1X		15
+#define	CLK_EMMC_1X		16
+#define	CLK_ADI			17
+#define	CLK_PWM0		18
+#define	CLK_PWM1		19
+#define	CLK_PWM2		20
+#define	CLK_PWM3		21
+#define	CLK_EFUSE		22
+#define	CLK_CM3_UART0		23
+#define	CLK_CM3_UART1		24
+#define	CLK_THM			25
+#define	CLK_CM3_I2C0		26
+#define	CLK_CM3_I2C1		27
+#define	CLK_CM4_SPI		28
+#define	CLK_AON_I2C		29
+#define	CLK_AVS			30
+#define	CLK_CA53_DAP		31
+#define	CLK_CA53_TS		32
+#define	CLK_DJTAG_TCK		33
+#define	CLK_PMU			34
+#define	CLK_PMU_26M		35
+#define	CLK_DEBOUNCE		36
+#define	CLK_OTG2_REF		37
+#define	CLK_USB3_REF		38
+#define	CLK_AP_AXI		39
+#define CLK_AON_PREDIV_NUM	(CLK_AP_AXI + 1)
+
+#define	CLK_USB3_EB		0
+#define	CLK_USB3_SUSPEND_EB	1
+#define	CLK_USB3_REF_EB		2
+#define	CLK_DMA_EB		3
+#define	CLK_SDIO0_EB		4
+#define	CLK_SDIO1_EB		5
+#define	CLK_SDIO2_EB		6
+#define	CLK_EMMC_EB		7
+#define	CLK_ROM_EB		8
+#define	CLK_BUSMON_EB		9
+#define	CLK_CC63S_EB		10
+#define	CLK_CC63P_EB		11
+#define	CLK_CE0_EB		12
+#define	CLK_CE1_EB		13
+#define CLK_APAHB_GATE_NUM	(CLK_CE1_EB + 1)
+
+#define	CLK_AVS_LIT_EB		0
+#define	CLK_AVS_BIG_EB		1
+#define	CLK_AP_INTC5_EB		2
+#define	CLK_GPIO_EB		3
+#define	CLK_PWM0_EB		4
+#define	CLK_PWM1_EB		5
+#define	CLK_PWM2_EB		6
+#define	CLK_PWM3_EB		7
+#define	CLK_KPD_EB		8
+#define	CLK_AON_SYS_EB		9
+#define	CLK_AP_SYS_EB		10
+#define	CLK_AON_TMR_EB		11
+#define	CLK_AP_TMR0_EB		12
+#define	CLK_EFUSE_EB		13
+#define	CLK_EIC_EB		14
+#define	CLK_PUB1_REG_EB		15
+#define	CLK_ADI_EB		16
+#define	CLK_AP_INTC0_EB		17
+#define	CLK_AP_INTC1_EB		18
+#define	CLK_AP_INTC2_EB		19
+#define	CLK_AP_INTC3_EB		20
+#define	CLK_AP_INTC4_EB		21
+#define	CLK_SPLK_EB		22
+#define	CLK_MSPI_EB		23
+#define	CLK_PUB0_REG_EB		24
+#define	CLK_PIN_EB		25
+#define	CLK_AON_CKG_EB		26
+#define	CLK_GPU_EB		27
+#define	CLK_APCPU_TS0_EB	28
+#define	CLK_APCPU_TS1_EB	29
+#define	CLK_DAP_EB		30
+#define	CLK_I2C_EB		31
+#define	CLK_PMU_EB		32
+#define	CLK_THM_EB		33
+#define	CLK_AUX0_EB		34
+#define	CLK_AUX1_EB		35
+#define	CLK_AUX2_EB		36
+#define	CLK_PROBE_EB		37
+#define	CLK_GPU0_AVS_EB		38
+#define	CLK_GPU1_AVS_EB		39
+#define	CLK_APCPU_WDG_EB	40
+#define	CLK_AP_TMR1_EB		41
+#define	CLK_AP_TMR2_EB		42
+#define	CLK_DISP_EMC_EB		43
+#define	CLK_ZIP_EMC_EB		44
+#define	CLK_GSP_EMC_EB		45
+#define	CLK_OSC_AON_EB		46
+#define	CLK_LVDS_TRX_EB		47
+#define	CLK_LVDS_TCXO_EB	48
+#define	CLK_MDAR_EB		49
+#define	CLK_RTC4M0_CAL_EB	50
+#define	CLK_RCT100M_CAL_EB	51
+#define	CLK_DJTAG_EB		52
+#define	CLK_MBOX_EB		53
+#define	CLK_AON_DMA_EB		54
+#define	CLK_DBG_EMC_EB		55
+#define	CLK_LVDS_PLL_DIV_EN	56
+#define	CLK_DEF_EB		57
+#define	CLK_AON_APB_RSV0	58
+#define	CLK_ORP_JTAG_EB		59
+#define	CLK_VSP_EB		60
+#define	CLK_CAM_EB		61
+#define	CLK_DISP_EB		62
+#define	CLK_DBG_AXI_IF_EB	63
+#define	CLK_SDIO0_2X_EN		64
+#define	CLK_SDIO1_2X_EN		65
+#define	CLK_SDIO2_2X_EN		66
+#define	CLK_EMMC_2X_EN		67
+#define	CLK_ARCH_RTC_EB		68
+#define	CLK_KPB_RTC_EB		69
+#define	CLK_AON_SYST_RTC_EB	70
+#define	CLK_AP_SYST_RTC_EB	71
+#define	CLK_AON_TMR_RTC_EB	72
+#define	CLK_AP_TMR0_RTC_EB	73
+#define	CLK_EIC_RTC_EB		74
+#define	CLK_EIC_RTCDV5_EB	75
+#define	CLK_AP_WDG_RTC_EB	76
+#define	CLK_AP_TMR1_RTC_EB	77
+#define	CLK_AP_TMR2_RTC_EB	78
+#define	CLK_DCXO_TMR_RTC_EB	79
+#define	CLK_BB_CAL_RTC_EB	80
+#define	CLK_AVS_BIG_RTC_EB	81
+#define	CLK_AVS_LIT_RTC_EB	82
+#define	CLK_AVS_GPU0_RTC_EB	83
+#define	CLK_AVS_GPU1_RTC_EB	84
+#define	CLK_GPU_TS_EB		85
+#define	CLK_RTCDV10_EB		86
+#define	CLK_AON_GATE_NUM	(CLK_RTCDV10_EB + 1)
+
+#define	CLK_LIT_MCU		0
+#define	CLK_BIG_MCU		1
+#define CLK_AONSECURE_NUM	(CLK_BIG_MCU + 1)
+
+#define	CLK_AGCP_IIS0_EB	0
+#define	CLK_AGCP_IIS1_EB	1
+#define	CLK_AGCP_IIS2_EB	2
+#define	CLK_AGCP_IIS3_EB	3
+#define	CLK_AGCP_UART_EB	4
+#define	CLK_AGCP_DMACP_EB	5
+#define	CLK_AGCP_DMAAP_EB	6
+#define	CLK_AGCP_ARC48K_EB	7
+#define	CLK_AGCP_SRC44P1K_EB	8
+#define	CLK_AGCP_MCDT_EB	9
+#define	CLK_AGCP_VBCIFD_EB	10
+#define	CLK_AGCP_VBC_EB		11
+#define	CLK_AGCP_SPINLOCK_EB	12
+#define	CLK_AGCP_ICU_EB		13
+#define	CLK_AGCP_AP_ASHB_EB	14
+#define	CLK_AGCP_CP_ASHB_EB	15
+#define	CLK_AGCP_AUD_EB		16
+#define	CLK_AGCP_AUDIF_EB	17
+#define CLK_AGCP_GATE_NUM	(CLK_AGCP_AUDIF_EB + 1)
+
+#define	CLK_GPU			0
+#define CLK_GPU_NUM		(CLK_GPU + 1)
+
+#define	CLK_AHB_VSP		0
+#define	CLK_VSP			1
+#define	CLK_VSP_ENC		2
+#define	CLK_VPP			3
+#define	CLK_VSP_26M		4
+#define CLK_VSP_NUM		(CLK_VSP_26M + 1)
+
+#define	CLK_VSP_DEC_EB		0
+#define	CLK_VSP_CKG_EB		1
+#define	CLK_VSP_MMU_EB		2
+#define	CLK_VSP_ENC_EB		3
+#define	CLK_VPP_EB		4
+#define	CLK_VSP_26M_EB		5
+#define	CLK_VSP_AXI_GATE	6
+#define	CLK_VSP_ENC_GATE	7
+#define	CLK_VPP_AXI_GATE	8
+#define	CLK_VSP_BM_GATE		9
+#define	CLK_VSP_ENC_BM_GATE	10
+#define	CLK_VPP_BM_GATE		11
+#define CLK_VSP_GATE_NUM	(CLK_VPP_BM_GATE + 1)
+
+#define	CLK_AHB_CAM		0
+#define	CLK_SENSOR0		1
+#define	CLK_SENSOR1		2
+#define	CLK_SENSOR2		3
+#define	CLK_MIPI_CSI0_EB	4
+#define	CLK_MIPI_CSI1_EB	5
+#define CLK_CAM_NUM		(CLK_MIPI_CSI1_EB + 1)
+
+#define	CLK_DCAM0_EB		0
+#define	CLK_DCAM1_EB		1
+#define	CLK_ISP0_EB		2
+#define	CLK_CSI0_EB		3
+#define	CLK_CSI1_EB		4
+#define	CLK_JPG0_EB		5
+#define	CLK_JPG1_EB		6
+#define	CLK_CAM_CKG_EB		7
+#define	CLK_CAM_MMU_EB		8
+#define	CLK_ISP1_EB		9
+#define	CLK_CPP_EB		10
+#define	CLK_MMU_PF_EB		11
+#define	CLK_ISP2_EB		12
+#define	CLK_DCAM2ISP_IF_EB	13
+#define	CLK_ISP2DCAM_IF_EB	14
+#define	CLK_ISP_LCLK_EB		15
+#define	CLK_ISP_ICLK_EB		16
+#define	CLK_ISP_MCLK_EB		17
+#define	CLK_ISP_PCLK_EB		18
+#define	CLK_ISP_ISP2DCAM_EB	19
+#define	CLK_DCAM0_IF_EB		20
+#define	CLK_CLK26M_IF_EB	21
+#define	CLK_CPHY0_GATE		22
+#define	CLK_MIPI_CSI0_GATE	23
+#define	CLK_CPHY1_GATE		24
+#define	CLK_MIPI_CSI1		25
+#define	CLK_DCAM0_AXI_GATE	26
+#define	CLK_DCAM1_AXI_GATE	27
+#define	CLK_SENSOR0_GATE	28
+#define	CLK_SENSOR1_GATE	29
+#define	CLK_JPG0_AXI_GATE	30
+#define	CLK_GPG1_AXI_GATE	31
+#define	CLK_ISP0_AXI_GATE	32
+#define	CLK_ISP1_AXI_GATE	33
+#define	CLK_ISP2_AXI_GATE	34
+#define	CLK_CPP_AXI_GATE	35
+#define	CLK_D0_IF_AXI_GATE	36
+#define	CLK_D2I_IF_AXI_GATE	37
+#define	CLK_I2D_IF_AXI_GATE	38
+#define	CLK_SPARE_AXI_GATE	39
+#define	CLK_SENSOR2_GATE	40
+#define	CLK_D0IF_IN_D_EN	41
+#define	CLK_D1IF_IN_D_EN	42
+#define	CLK_D0IF_IN_D2I_EN	43
+#define	CLK_D1IF_IN_D2I_EN	44
+#define	CLK_IA_IN_D2I_EN	45
+#define	CLK_IB_IN_D2I_EN	46
+#define	CLK_IC_IN_D2I_EN	47
+#define	CLK_IA_IN_I_EN		48
+#define	CLK_IB_IN_I_EN		49
+#define	CLK_IC_IN_I_EN		50
+#define CLK_CAM_GATE_NUM	(CLK_IC_IN_I_EN + 1)
+
+#define	CLK_AHB_DISP		0
+#define	CLK_DISPC0_DPI		1
+#define	CLK_DISPC1_DPI		2
+#define CLK_DISP_NUM		(CLK_DISPC1_DPI + 1)
+
+#define	CLK_DISPC0_EB		0
+#define	CLK_DISPC1_EB		1
+#define	CLK_DISPC_MMU_EB	2
+#define	CLK_GSP0_EB		3
+#define	CLK_GSP1_EB		4
+#define	CLK_GSP0_MMU_EB		5
+#define	CLK_GSP1_MMU_EB		6
+#define	CLK_DSI0_EB		7
+#define	CLK_DSI1_EB		8
+#define	CLK_DISP_CKG_EB		9
+#define	CLK_DISP_GPU_EB		10
+#define	CLK_GPU_MTX_EB		11
+#define	CLK_GSP_MTX_EB		12
+#define	CLK_TMC_MTX_EB		13
+#define	CLK_DISPC_MTX_EB	14
+#define	CLK_DPHY0_GATE		15
+#define	CLK_DPHY1_GATE		16
+#define	CLK_GSP0_A_GATE		17
+#define	CLK_GSP1_A_GATE		18
+#define	CLK_GSP0_F_GATE		19
+#define	CLK_GSP1_F_GATE		20
+#define	CLK_D_MTX_F_GATE	21
+#define	CLK_D_MTX_A_GATE	22
+#define	CLK_D_NOC_F_GATE	23
+#define	CLK_D_NOC_A_GATE	24
+#define	CLK_GSP_MTX_F_GATE	25
+#define	CLK_GSP_MTX_A_GATE	26
+#define	CLK_GSP_NOC_F_GATE	27
+#define	CLK_GSP_NOC_A_GATE	28
+#define	CLK_DISPM0IDLE_GATE	29
+#define	CLK_GSPM0IDLE_GATE	30
+#define CLK_DISP_GATE_NUM	(CLK_GSPM0IDLE_GATE + 1)
+
+#define	CLK_SIM0_EB		0
+#define	CLK_IIS0_EB		1
+#define	CLK_IIS1_EB		2
+#define	CLK_IIS2_EB		3
+#define	CLK_IIS3_EB		4
+#define	CLK_SPI0_EB		5
+#define	CLK_SPI1_EB		6
+#define	CLK_SPI2_EB		7
+#define	CLK_I2C0_EB		8
+#define	CLK_I2C1_EB		9
+#define	CLK_I2C2_EB		10
+#define	CLK_I2C3_EB		11
+#define	CLK_I2C4_EB		12
+#define	CLK_I2C5_EB		13
+#define	CLK_UART0_EB		14
+#define	CLK_UART1_EB		15
+#define	CLK_UART2_EB		16
+#define	CLK_UART3_EB		17
+#define	CLK_UART4_EB		18
+#define	CLK_AP_CKG_EB		19
+#define	CLK_SPI3_EB		20
+#define CLK_APAPB_GATE_NUM	(CLK_SPI3_EB + 1)
+
+#endif /* _DT_BINDINGS_CLK_SC9860_H_ */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/ste-ab8500.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/ste-ab8500.h
new file mode 100644
index 0000000000000000000000000000000000000000..fb42dd0cab5fc00e0999473e2135eb48ad42a692
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/ste-ab8500.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __STE_CLK_AB8500_H__
+#define __STE_CLK_AB8500_H__
+
+#define AB8500_SYSCLK_BUF2	0
+#define AB8500_SYSCLK_BUF3	1
+#define AB8500_SYSCLK_BUF4	2
+#define AB8500_SYSCLK_ULP	3
+#define AB8500_SYSCLK_INT	4
+#define AB8500_SYSCLK_AUDIO	5
+
+#endif
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/stih407-clks.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/stih407-clks.h
new file mode 100644
index 0000000000000000000000000000000000000000..f0936c13377212e776e7a84976212205549f4245
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/stih407-clks.h
@@ -0,0 +1,91 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * This header provides constants clk index STMicroelectronics
+ * STiH407 SoC.
+ */
+#ifndef _DT_BINDINGS_CLK_STIH407
+#define _DT_BINDINGS_CLK_STIH407
+
+/* CLOCKGEN A0 */
+#define CLK_IC_LMI0		0
+#define CLK_IC_LMI1		1
+
+/* CLOCKGEN C0 */
+#define CLK_ICN_GPU		0
+#define CLK_FDMA		1
+#define CLK_NAND		2
+#define CLK_HVA			3
+#define CLK_PROC_STFE		4
+#define CLK_PROC_TP		5
+#define CLK_RX_ICN_DMU		6
+#define CLK_RX_ICN_DISP_0	6
+#define CLK_RX_ICN_DISP_1	6
+#define CLK_RX_ICN_HVA		7
+#define CLK_RX_ICN_TS		7
+#define CLK_ICN_CPU		8
+#define CLK_TX_ICN_DMU		9
+#define CLK_TX_ICN_HVA		9
+#define CLK_TX_ICN_TS		9
+#define CLK_ICN_COMPO		9
+#define CLK_MMC_0		10
+#define CLK_MMC_1		11
+#define CLK_JPEGDEC		12
+#define CLK_ICN_REG		13
+#define CLK_TRACE_A9		13
+#define CLK_PTI_STM		13
+#define CLK_EXT2F_A9		13
+#define CLK_IC_BDISP_0		14
+#define CLK_IC_BDISP_1		15
+#define CLK_PP_DMU		16
+#define CLK_VID_DMU		17
+#define CLK_DSS_LPC		18
+#define CLK_ST231_AUD_0		19
+#define CLK_ST231_GP_0		19
+#define CLK_ST231_GP_1		20
+#define CLK_ST231_DMU		21
+#define CLK_ICN_LMI		22
+#define CLK_TX_ICN_DISP_0	23
+#define CLK_TX_ICN_DISP_1	23
+#define CLK_ICN_SBC		24
+#define CLK_STFE_FRC2		25
+#define CLK_ETH_PHY		26
+#define CLK_ETH_REF_PHYCLK	27
+#define CLK_FLASH_PROMIP	28
+#define CLK_MAIN_DISP		29
+#define CLK_AUX_DISP		30
+#define CLK_COMPO_DVP		31
+
+/* CLOCKGEN D0 */
+#define CLK_PCM_0		0
+#define CLK_PCM_1		1
+#define CLK_PCM_2		2
+#define CLK_SPDIFF		3
+
+/* CLOCKGEN D2 */
+#define CLK_PIX_MAIN_DISP	0
+#define CLK_PIX_PIP		1
+#define CLK_PIX_GDP1		2
+#define CLK_PIX_GDP2		3
+#define CLK_PIX_GDP3		4
+#define CLK_PIX_GDP4		5
+#define CLK_PIX_AUX_DISP	6
+#define CLK_DENC		7
+#define CLK_PIX_HDDAC		8
+#define CLK_HDDAC		9
+#define CLK_SDDAC		10
+#define CLK_PIX_DVO		11
+#define CLK_DVO			12
+#define CLK_PIX_HDMI		13
+#define CLK_TMDS_HDMI		14
+#define CLK_REF_HDMIPHY		15
+
+/* CLOCKGEN D3 */
+#define CLK_STFE_FRC1		0
+#define CLK_TSOUT_0		1
+#define CLK_TSOUT_1		2
+#define CLK_MCHI		3
+#define CLK_VSENS_COMPO		4
+#define CLK_FRC1_REMOTE		5
+#define CLK_LPC_0		6
+#define CLK_LPC_1		7
+#endif
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/stih410-clks.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/stih410-clks.h
new file mode 100644
index 0000000000000000000000000000000000000000..90cbe6154c3904fe033251200873e0fcb6f15055
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/stih410-clks.h
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * This header provides constants clk index STMicroelectronics
+ * STiH410 SoC.
+ */
+#ifndef _DT_BINDINGS_CLK_STIH410
+#define _DT_BINDINGS_CLK_STIH410
+
+#include "stih407-clks.h"
+
+/* STiH410 introduces new clock outputs compared to STiH407 */
+
+/* CLOCKGEN C0 */
+#define CLK_TX_ICN_HADES	32
+#define CLK_RX_ICN_HADES	33
+#define CLK_ICN_REG_16		34
+#define CLK_PP_HADES		35
+#define CLK_CLUST_HADES		36
+#define CLK_HWPE_HADES		37
+#define CLK_FC_HADES		38
+
+/* CLOCKGEN D0 */
+#define CLK_PCMR10_MASTER	4
+#define CLK_USB2_PHY		5
+
+#endif
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/stih416-clks.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/stih416-clks.h
new file mode 100644
index 0000000000000000000000000000000000000000..74302278024ea91ed0cdfc0968346e6beeabd976
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/stih416-clks.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * This header provides constants clk index STMicroelectronics
+ * STiH416 SoC.
+ */
+#ifndef _CLK_STIH416
+#define _CLK_STIH416
+
+/* CLOCKGEN A0 */
+#define CLK_ICN_REG		0
+#define CLK_ETH1_PHY		4
+
+/* CLOCKGEN A1 */
+#define CLK_ICN_IF_2		0
+#define CLK_GMAC0_PHY		3
+
+#endif
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/stih418-clks.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/stih418-clks.h
new file mode 100644
index 0000000000000000000000000000000000000000..0e7fba0c52b32efaeca82d58ea4699c37dfec0da
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/stih418-clks.h
@@ -0,0 +1,35 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * This header provides constants clk index STMicroelectronics
+ * STiH418 SoC.
+ */
+#ifndef _DT_BINDINGS_CLK_STIH418
+#define _DT_BINDINGS_CLK_STIH418
+
+#include "stih410-clks.h"
+
+/* STiH418 introduces new clock outputs compared to STiH410 */
+
+/* CLOCKGEN C0 */
+#define CLK_PROC_BDISP_0        14
+#define CLK_PROC_BDISP_1        15
+#define CLK_TX_ICN_1            23
+#define CLK_ETH_PHYREF          27
+#define CLK_PP_HEVC             35
+#define CLK_CLUST_HEVC          36
+#define CLK_HWPE_HEVC           37
+#define CLK_FC_HEVC             38
+#define CLK_PROC_MIXER		39
+#define CLK_PROC_SC		40
+#define CLK_AVSP_HEVC		41
+
+/* CLOCKGEN D2 */
+#undef CLK_PIX_PIP
+#undef CLK_PIX_GDP1
+#undef CLK_PIX_GDP2
+#undef CLK_PIX_GDP3
+#undef CLK_PIX_GDP4
+
+#define CLK_TMDS_HDMI_DIV2	5
+#define CLK_VP9			47
+#endif
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/stm32fx-clock.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/stm32fx-clock.h
new file mode 100644
index 0000000000000000000000000000000000000000..58d8b515be55f4a2a44aaf3b10b41191747cb994
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/stm32fx-clock.h
@@ -0,0 +1,60 @@
+/*
+ * stm32fx-clock.h
+ *
+ * Copyright (C) 2016 STMicroelectronics
+ * Author: Gabriel Fernandez for STMicroelectronics.
+ * License terms:  GNU General Public License (GPL), version 2
+ */
+
+/*
+ * List of clocks wich are not derived from system clock (SYSCLOCK)
+ *
+ * The index of these clocks is the secondary index of DT bindings
+ * (see Documentatoin/devicetree/bindings/clock/st,stm32-rcc.txt)
+ *
+ * e.g:
+	<assigned-clocks = <&rcc 1 CLK_LSE>;
+*/
+
+#ifndef _DT_BINDINGS_CLK_STMFX_H
+#define _DT_BINDINGS_CLK_STMFX_H
+
+#define SYSTICK			0
+#define FCLK			1
+#define CLK_LSI			2
+#define CLK_LSE			3
+#define CLK_HSE_RTC		4
+#define CLK_RTC			5
+#define PLL_VCO_I2S		6
+#define PLL_VCO_SAI		7
+#define CLK_LCD			8
+#define CLK_I2S			9
+#define CLK_SAI1		10
+#define CLK_SAI2		11
+#define CLK_I2SQ_PDIV		12
+#define CLK_SAIQ_PDIV		13
+#define CLK_HSI			14
+#define CLK_SYSCLK		15
+#define CLK_F469_DSI		16
+
+#define END_PRIMARY_CLK		17
+
+#define CLK_HDMI_CEC		16
+#define CLK_SPDIF		17
+#define CLK_USART1		18
+#define CLK_USART2		19
+#define CLK_USART3		20
+#define CLK_UART4		21
+#define CLK_UART5		22
+#define CLK_USART6		23
+#define CLK_UART7		24
+#define CLK_UART8		25
+#define CLK_I2C1		26
+#define CLK_I2C2		27
+#define CLK_I2C3		28
+#define CLK_I2C4		29
+#define CLK_LPTIMER		30
+
+#define END_PRIMARY_CLK_F7	31
+
+#endif
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/stm32h7-clks.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/stm32h7-clks.h
new file mode 100644
index 0000000000000000000000000000000000000000..6637272b324244f96497817756aa1e25102c1ba0
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/stm32h7-clks.h
@@ -0,0 +1,165 @@
+/* SYS, CORE AND BUS CLOCKS */
+#define SYS_D1CPRE 0
+#define HCLK 1
+#define PCLK1 2
+#define PCLK2 3
+#define PCLK3 4
+#define PCLK4 5
+#define HSI_DIV 6
+#define HSE_1M 7
+#define I2S_CKIN 8
+#define CK_DSI_PHY 9
+#define HSE_CK 10
+#define LSE_CK 11
+#define CSI_KER_DIV122 12
+#define RTC_CK 13
+#define CPU_SYSTICK 14
+
+/* OSCILLATOR BANK */
+#define OSC_BANK 18
+#define HSI_CK 18
+#define HSI_KER_CK 19
+#define CSI_CK 20
+#define CSI_KER_CK 21
+#define RC48_CK 22
+#define LSI_CK 23
+
+/* MCLOCK BANK */
+#define MCLK_BANK 28
+#define PER_CK 28
+#define PLLSRC 29
+#define SYS_CK 30
+#define TRACEIN_CK 31
+
+/* ODF BANK */
+#define ODF_BANK 32
+#define PLL1_P 32
+#define PLL1_Q 33
+#define PLL1_R 34
+#define PLL2_P 35
+#define PLL2_Q 36
+#define PLL2_R 37
+#define PLL3_P 38
+#define PLL3_Q 39
+#define PLL3_R 40
+
+/* MCO BANK */
+#define MCO_BANK 41
+#define MCO1 41
+#define MCO2 42
+
+/* PERIF BANK */
+#define PERIF_BANK 50
+#define D1SRAM1_CK 50
+#define ITCM_CK 51
+#define DTCM2_CK 52
+#define DTCM1_CK 53
+#define FLITF_CK 54
+#define JPGDEC_CK 55
+#define DMA2D_CK 56
+#define MDMA_CK 57
+#define USB2ULPI_CK 58
+#define USB1ULPI_CK 59
+#define ETH1RX_CK 60
+#define ETH1TX_CK 61
+#define ETH1MAC_CK 62
+#define ART_CK 63
+#define DMA2_CK 64
+#define DMA1_CK 65
+#define D2SRAM3_CK 66
+#define D2SRAM2_CK 67
+#define D2SRAM1_CK 68
+#define HASH_CK 69
+#define CRYPT_CK 70
+#define CAMITF_CK 71
+#define BKPRAM_CK 72
+#define HSEM_CK 73
+#define BDMA_CK 74
+#define CRC_CK 75
+#define GPIOK_CK 76
+#define GPIOJ_CK 77
+#define GPIOI_CK 78
+#define GPIOH_CK 79
+#define GPIOG_CK 80
+#define GPIOF_CK 81
+#define GPIOE_CK 82
+#define GPIOD_CK 83
+#define GPIOC_CK 84
+#define GPIOB_CK 85
+#define GPIOA_CK 86
+#define WWDG1_CK 87
+#define DAC12_CK 88
+#define WWDG2_CK 89
+#define TIM14_CK 90
+#define TIM13_CK 91
+#define TIM12_CK 92
+#define TIM7_CK 93
+#define TIM6_CK 94
+#define TIM5_CK 95
+#define TIM4_CK 96
+#define TIM3_CK 97
+#define TIM2_CK 98
+#define MDIOS_CK 99
+#define OPAMP_CK 100
+#define CRS_CK 101
+#define TIM17_CK 102
+#define TIM16_CK 103
+#define TIM15_CK 104
+#define TIM8_CK 105
+#define TIM1_CK 106
+#define TMPSENS_CK 107
+#define RTCAPB_CK 108
+#define VREF_CK 109
+#define COMP12_CK 110
+#define SYSCFG_CK 111
+
+/* KERNEL BANK */
+#define KERN_BANK 120
+#define SDMMC1_CK 120
+#define QUADSPI_CK 121
+#define FMC_CK 122
+#define USB2OTG_CK 123
+#define USB1OTG_CK 124
+#define ADC12_CK 125
+#define SDMMC2_CK 126
+#define RNG_CK 127
+#define ADC3_CK 128
+#define DSI_CK 129
+#define LTDC_CK 130
+#define USART8_CK 131
+#define USART7_CK 132
+#define HDMICEC_CK 133
+#define I2C3_CK 134
+#define I2C2_CK 135
+#define I2C1_CK 136
+#define UART5_CK 137
+#define UART4_CK 138
+#define USART3_CK 139
+#define USART2_CK 140
+#define SPDIFRX_CK 141
+#define SPI3_CK 142
+#define SPI2_CK 143
+#define LPTIM1_CK 144
+#define FDCAN_CK 145
+#define SWP_CK 146
+#define HRTIM_CK 147
+#define DFSDM1_CK 148
+#define SAI3_CK 149
+#define SAI2_CK 150
+#define SAI1_CK 151
+#define SPI5_CK 152
+#define SPI4_CK 153
+#define SPI1_CK 154
+#define USART6_CK 155
+#define USART1_CK 156
+#define SAI4B_CK 157
+#define SAI4A_CK 158
+#define LPTIM5_CK 159
+#define LPTIM4_CK 160
+#define LPTIM3_CK 161
+#define LPTIM2_CK 162
+#define I2C4_CK 163
+#define SPI6_CK 164
+#define LPUART1_CK 165
+
+#define STM32H7_MAX_CLKS 166
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/stm32mp1-clks.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/stm32mp1-clks.h
new file mode 100644
index 0000000000000000000000000000000000000000..90ec780bfc68622f264e7e7c7e1e030c3b83cfba
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/stm32mp1-clks.h
@@ -0,0 +1,254 @@
+/* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */
+/*
+ * Copyright (C) STMicroelectronics 2018 - All Rights Reserved
+ * Author: Gabriel Fernandez <gabriel.fernandez@st.com> for STMicroelectronics.
+ */
+
+#ifndef _DT_BINDINGS_STM32MP1_CLKS_H_
+#define _DT_BINDINGS_STM32MP1_CLKS_H_
+
+/* OSCILLATOR clocks */
+#define CK_HSE		0
+#define CK_CSI		1
+#define CK_LSI		2
+#define CK_LSE		3
+#define CK_HSI		4
+#define CK_HSE_DIV2	5
+
+/* Bus clocks */
+#define TIM2		6
+#define TIM3		7
+#define TIM4		8
+#define TIM5		9
+#define TIM6		10
+#define TIM7		11
+#define TIM12		12
+#define TIM13		13
+#define TIM14		14
+#define LPTIM1		15
+#define SPI2		16
+#define SPI3		17
+#define USART2		18
+#define USART3		19
+#define UART4		20
+#define UART5		21
+#define UART7		22
+#define UART8		23
+#define I2C1		24
+#define I2C2		25
+#define I2C3		26
+#define I2C5		27
+#define SPDIF		28
+#define CEC		29
+#define DAC12		30
+#define MDIO		31
+#define TIM1		32
+#define TIM8		33
+#define TIM15		34
+#define TIM16		35
+#define TIM17		36
+#define SPI1		37
+#define SPI4		38
+#define SPI5		39
+#define USART6		40
+#define SAI1		41
+#define SAI2		42
+#define SAI3		43
+#define DFSDM		44
+#define FDCAN		45
+#define LPTIM2		46
+#define LPTIM3		47
+#define LPTIM4		48
+#define LPTIM5		49
+#define SAI4		50
+#define SYSCFG		51
+#define VREF		52
+#define TMPSENS		53
+#define PMBCTRL		54
+#define HDP		55
+#define LTDC		56
+#define DSI		57
+#define IWDG2		58
+#define USBPHY		59
+#define STGENRO		60
+#define SPI6		61
+#define I2C4		62
+#define I2C6		63
+#define USART1		64
+#define RTCAPB		65
+#define TZC1		66
+#define TZPC		67
+#define IWDG1		68
+#define BSEC		69
+#define STGEN		70
+#define DMA1		71
+#define DMA2		72
+#define DMAMUX		73
+#define ADC12		74
+#define USBO		75
+#define SDMMC3		76
+#define DCMI		77
+#define CRYP2		78
+#define HASH2		79
+#define RNG2		80
+#define CRC2		81
+#define HSEM		82
+#define IPCC		83
+#define GPIOA		84
+#define GPIOB		85
+#define GPIOC		86
+#define GPIOD		87
+#define GPIOE		88
+#define GPIOF		89
+#define GPIOG		90
+#define GPIOH		91
+#define GPIOI		92
+#define GPIOJ		93
+#define GPIOK		94
+#define GPIOZ		95
+#define CRYP1		96
+#define HASH1		97
+#define RNG1		98
+#define BKPSRAM		99
+#define MDMA		100
+#define GPU		101
+#define ETHCK		102
+#define ETHTX		103
+#define ETHRX		104
+#define ETHMAC		105
+#define FMC		106
+#define QSPI		107
+#define SDMMC1		108
+#define SDMMC2		109
+#define CRC1		110
+#define USBH		111
+#define ETHSTP		112
+#define TZC2		113
+
+/* Kernel clocks */
+#define SDMMC1_K	118
+#define SDMMC2_K	119
+#define SDMMC3_K	120
+#define FMC_K		121
+#define QSPI_K		122
+#define ETHCK_K		123
+#define RNG1_K		124
+#define RNG2_K		125
+#define GPU_K		126
+#define USBPHY_K	127
+#define STGEN_K		128
+#define SPDIF_K		129
+#define SPI1_K		130
+#define SPI2_K		131
+#define SPI3_K		132
+#define SPI4_K		133
+#define SPI5_K		134
+#define SPI6_K		135
+#define CEC_K		136
+#define I2C1_K		137
+#define I2C2_K		138
+#define I2C3_K		139
+#define I2C4_K		140
+#define I2C5_K		141
+#define I2C6_K		142
+#define LPTIM1_K	143
+#define LPTIM2_K	144
+#define LPTIM3_K	145
+#define LPTIM4_K	146
+#define LPTIM5_K	147
+#define USART1_K	148
+#define USART2_K	149
+#define USART3_K	150
+#define UART4_K		151
+#define UART5_K		152
+#define USART6_K	153
+#define UART7_K		154
+#define UART8_K		155
+#define DFSDM_K		156
+#define FDCAN_K		157
+#define SAI1_K		158
+#define SAI2_K		159
+#define SAI3_K		160
+#define SAI4_K		161
+#define ADC12_K		162
+#define DSI_K		163
+#define DSI_PX		164
+#define ADFSDM_K	165
+#define USBO_K		166
+#define LTDC_PX		167
+#define DAC12_K		168
+#define ETHPTP_K	169
+
+/* PLL */
+#define PLL1		176
+#define PLL2		177
+#define PLL3		178
+#define PLL4		179
+
+/* ODF */
+#define PLL1_P		180
+#define PLL1_Q		181
+#define PLL1_R		182
+#define PLL2_P		183
+#define PLL2_Q		184
+#define PLL2_R		185
+#define PLL3_P		186
+#define PLL3_Q		187
+#define PLL3_R		188
+#define PLL4_P		189
+#define PLL4_Q		190
+#define PLL4_R		191
+
+/* AUX */
+#define RTC		192
+
+/* MCLK */
+#define CK_PER		193
+#define CK_MPU		194
+#define CK_AXI		195
+#define CK_MCU		196
+
+/* Time base */
+#define TIM2_K		197
+#define TIM3_K		198
+#define TIM4_K		199
+#define TIM5_K		200
+#define TIM6_K		201
+#define TIM7_K		202
+#define TIM12_K		203
+#define TIM13_K		204
+#define TIM14_K		205
+#define TIM1_K		206
+#define TIM8_K		207
+#define TIM15_K		208
+#define TIM16_K		209
+#define TIM17_K		210
+
+/* MCO clocks */
+#define CK_MCO1		211
+#define CK_MCO2		212
+
+/* TRACE & DEBUG clocks */
+#define CK_DBG		214
+#define CK_TRACE	215
+
+/* DDR */
+#define DDRC1		220
+#define DDRC1LP		221
+#define DDRC2		222
+#define DDRC2LP		223
+#define DDRPHYC		224
+#define DDRPHYCLP	225
+#define DDRCAPB		226
+#define DDRCAPBLP	227
+#define AXIDCG		228
+#define DDRPHYCAPB	229
+#define DDRPHYCAPBLP	230
+#define DDRPERFM	231
+
+#define STM32MP1_LAST_CLK 232
+
+#define LTDC_K		LTDC_PX
+#define ETHMAC_K	ETHCK_K
+
+#endif /* _DT_BINDINGS_STM32MP1_CLKS_H_ */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/stratix10-clock.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/stratix10-clock.h
new file mode 100644
index 0000000000000000000000000000000000000000..0ac1c90a18bf8601a0ef24d94915fe102b923f8c
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/stratix10-clock.h
@@ -0,0 +1,84 @@
+/* SPDX-License-Identifier:	GPL-2.0 */
+/*
+ * Copyright (C) 2017, Intel Corporation
+ */
+
+#ifndef __STRATIX10_CLOCK_H
+#define __STRATIX10_CLOCK_H
+
+/* fixed rate clocks */
+#define STRATIX10_OSC1			0
+#define STRATIX10_CB_INTOSC_HS_DIV2_CLK	1
+#define STRATIX10_CB_INTOSC_LS_CLK	2
+#define STRATIX10_F2S_FREE_CLK		3
+
+/* fixed factor clocks */
+#define STRATIX10_L4_SYS_FREE_CLK	4
+#define STRATIX10_MPU_PERIPH_CLK	5
+#define STRATIX10_MPU_L2RAM_CLK		6
+#define STRATIX10_SDMMC_CIU_CLK		7
+
+/* PLL clocks */
+#define STRATIX10_MAIN_PLL_CLK		8
+#define STRATIX10_PERIPH_PLL_CLK	9
+#define STRATIX10_BOOT_CLK		10
+
+/* Periph clocks */
+#define STRATIX10_MAIN_MPU_BASE_CLK	11
+#define STRATIX10_MAIN_NOC_BASE_CLK	12
+#define STRATIX10_MAIN_EMACA_CLK	13
+#define STRATIX10_MAIN_EMACB_CLK	14
+#define STRATIX10_MAIN_EMAC_PTP_CLK	15
+#define STRATIX10_MAIN_GPIO_DB_CLK	16
+#define STRATIX10_MAIN_SDMMC_CLK	17
+#define STRATIX10_MAIN_S2F_USR0_CLK	18
+#define STRATIX10_MAIN_S2F_USR1_CLK	19
+#define STRATIX10_MAIN_PSI_REF_CLK	20
+
+#define STRATIX10_PERI_MPU_BASE_CLK	21
+#define STRATIX10_PERI_NOC_BASE_CLK	22
+#define STRATIX10_PERI_EMACA_CLK	23
+#define STRATIX10_PERI_EMACB_CLK	24
+#define STRATIX10_PERI_EMAC_PTP_CLK	25
+#define STRATIX10_PERI_GPIO_DB_CLK	26
+#define STRATIX10_PERI_SDMMC_CLK	27
+#define STRATIX10_PERI_S2F_USR0_CLK	28
+#define STRATIX10_PERI_S2F_USR1_CLK	29
+#define STRATIX10_PERI_PSI_REF_CLK	30
+
+#define STRATIX10_MPU_FREE_CLK		31
+#define STRATIX10_NOC_FREE_CLK		32
+#define STRATIX10_S2F_USR0_CLK		33
+#define STRATIX10_NOC_CLK		34
+#define STRATIX10_EMAC_A_FREE_CLK	35
+#define STRATIX10_EMAC_B_FREE_CLK	36
+#define STRATIX10_EMAC_PTP_FREE_CLK	37
+#define STRATIX10_GPIO_DB_FREE_CLK	38
+#define STRATIX10_SDMMC_FREE_CLK	39
+#define STRATIX10_S2F_USER1_FREE_CLK	40
+#define STRATIX10_PSI_REF_FREE_CLK	41
+
+/* Gate clocks */
+#define STRATIX10_MPU_CLK		42
+#define STRATIX10_L4_MAIN_CLK		43
+#define STRATIX10_L4_MP_CLK		44
+#define STRATIX10_L4_SP_CLK		45
+#define STRATIX10_CS_AT_CLK		46
+#define STRATIX10_CS_TRACE_CLK		47
+#define STRATIX10_CS_PDBG_CLK		48
+#define STRATIX10_CS_TIMER_CLK		49
+#define STRATIX10_S2F_USER0_CLK		50
+#define STRATIX10_S2F_USER1_CLK		51
+#define STRATIX10_EMAC0_CLK		52
+#define STRATIX10_EMAC1_CLK		53
+#define STRATIX10_EMAC2_CLK		54
+#define STRATIX10_EMAC_PTP_CLK		55
+#define STRATIX10_GPIO_DB_CLK		56
+#define STRATIX10_SDMMC_CLK		57
+#define STRATIX10_PSI_REF_CLK		58
+#define STRATIX10_USB_CLK		59
+#define STRATIX10_SPI_M_CLK		60
+#define STRATIX10_NAND_CLK		61
+#define STRATIX10_NUM_CLKS		62
+
+#endif	/* __STRATIX10_CLOCK_H */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/sun4i-a10-ccu.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/sun4i-a10-ccu.h
new file mode 100644
index 0000000000000000000000000000000000000000..e4fa61be5c759087c3629441258c38200f400286
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/sun4i-a10-ccu.h
@@ -0,0 +1,202 @@
+/*
+ * Copyright (C) 2017 Priit Laes <plaes@plaes.org>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _DT_BINDINGS_CLK_SUN4I_A10_H_
+#define _DT_BINDINGS_CLK_SUN4I_A10_H_
+
+#define CLK_HOSC		1
+#define CLK_PLL_VIDEO0_2X	9
+#define CLK_PLL_VIDEO1_2X	18
+#define CLK_CPU			20
+
+/* AHB Gates */
+#define CLK_AHB_OTG		26
+#define CLK_AHB_EHCI0		27
+#define CLK_AHB_OHCI0		28
+#define CLK_AHB_EHCI1		29
+#define CLK_AHB_OHCI1		30
+#define CLK_AHB_SS		31
+#define CLK_AHB_DMA		32
+#define CLK_AHB_BIST		33
+#define CLK_AHB_MMC0		34
+#define CLK_AHB_MMC1		35
+#define CLK_AHB_MMC2		36
+#define CLK_AHB_MMC3		37
+#define CLK_AHB_MS		38
+#define CLK_AHB_NAND		39
+#define CLK_AHB_SDRAM		40
+#define CLK_AHB_ACE		41
+#define CLK_AHB_EMAC		42
+#define CLK_AHB_TS		43
+#define CLK_AHB_SPI0		44
+#define CLK_AHB_SPI1		45
+#define CLK_AHB_SPI2		46
+#define CLK_AHB_SPI3		47
+#define CLK_AHB_PATA		48
+#define CLK_AHB_SATA		49
+#define CLK_AHB_GPS		50
+#define CLK_AHB_HSTIMER		51
+#define CLK_AHB_VE		52
+#define CLK_AHB_TVD		53
+#define CLK_AHB_TVE0		54
+#define CLK_AHB_TVE1		55
+#define CLK_AHB_LCD0		56
+#define CLK_AHB_LCD1		57
+#define CLK_AHB_CSI0		58
+#define CLK_AHB_CSI1		59
+#define CLK_AHB_HDMI0		60
+#define CLK_AHB_HDMI1		61
+#define CLK_AHB_DE_BE0		62
+#define CLK_AHB_DE_BE1		63
+#define CLK_AHB_DE_FE0		64
+#define CLK_AHB_DE_FE1		65
+#define CLK_AHB_GMAC		66
+#define CLK_AHB_MP		67
+#define CLK_AHB_GPU		68
+
+/* APB0 Gates */
+#define CLK_APB0_CODEC		69
+#define CLK_APB0_SPDIF		70
+#define CLK_APB0_I2S0		71
+#define CLK_APB0_AC97		72
+#define CLK_APB0_I2S1		73
+#define CLK_APB0_PIO		74
+#define CLK_APB0_IR0		75
+#define CLK_APB0_IR1		76
+#define CLK_APB0_I2S2		77
+#define CLK_APB0_KEYPAD		78
+
+/* APB1 Gates */
+#define CLK_APB1_I2C0		79
+#define CLK_APB1_I2C1		80
+#define CLK_APB1_I2C2		81
+#define CLK_APB1_I2C3		82
+#define CLK_APB1_CAN		83
+#define CLK_APB1_SCR		84
+#define CLK_APB1_PS20		85
+#define CLK_APB1_PS21		86
+#define CLK_APB1_I2C4		87
+#define CLK_APB1_UART0		88
+#define CLK_APB1_UART1		89
+#define CLK_APB1_UART2		90
+#define CLK_APB1_UART3		91
+#define CLK_APB1_UART4		92
+#define CLK_APB1_UART5		93
+#define CLK_APB1_UART6		94
+#define CLK_APB1_UART7		95
+
+/* IP clocks */
+#define CLK_NAND		96
+#define CLK_MS			97
+#define CLK_MMC0		98
+#define CLK_MMC0_OUTPUT		99
+#define CLK_MMC0_SAMPLE		100
+#define CLK_MMC1		101
+#define CLK_MMC1_OUTPUT		102
+#define CLK_MMC1_SAMPLE		103
+#define CLK_MMC2		104
+#define CLK_MMC2_OUTPUT		105
+#define CLK_MMC2_SAMPLE		106
+#define CLK_MMC3		107
+#define CLK_MMC3_OUTPUT		108
+#define CLK_MMC3_SAMPLE		109
+#define CLK_TS			110
+#define CLK_SS			111
+#define CLK_SPI0		112
+#define CLK_SPI1		113
+#define CLK_SPI2		114
+#define CLK_PATA		115
+#define CLK_IR0			116
+#define CLK_IR1			117
+#define CLK_I2S0		118
+#define CLK_AC97		119
+#define CLK_SPDIF		120
+#define CLK_KEYPAD		121
+#define CLK_SATA		122
+#define CLK_USB_OHCI0		123
+#define CLK_USB_OHCI1		124
+#define CLK_USB_PHY		125
+#define CLK_GPS			126
+#define CLK_SPI3		127
+#define CLK_I2S1		128
+#define CLK_I2S2		129
+
+/* DRAM Gates */
+#define CLK_DRAM_VE		130
+#define CLK_DRAM_CSI0		131
+#define CLK_DRAM_CSI1		132
+#define CLK_DRAM_TS		133
+#define CLK_DRAM_TVD		134
+#define CLK_DRAM_TVE0		135
+#define CLK_DRAM_TVE1		136
+#define CLK_DRAM_OUT		137
+#define CLK_DRAM_DE_FE1		138
+#define CLK_DRAM_DE_FE0		139
+#define CLK_DRAM_DE_BE0		140
+#define CLK_DRAM_DE_BE1		141
+#define CLK_DRAM_MP		142
+#define CLK_DRAM_ACE		143
+
+/* Display Engine Clocks */
+#define CLK_DE_BE0		144
+#define CLK_DE_BE1		145
+#define CLK_DE_FE0		146
+#define CLK_DE_FE1		147
+#define CLK_DE_MP		148
+#define CLK_TCON0_CH0		149
+#define CLK_TCON1_CH0		150
+#define CLK_CSI_SCLK		151
+#define CLK_TVD_SCLK2		152
+#define CLK_TVD			153
+#define CLK_TCON0_CH1_SCLK2	154
+#define CLK_TCON0_CH1		155
+#define CLK_TCON1_CH1_SCLK2	156
+#define CLK_TCON1_CH1		157
+#define CLK_CSI0		158
+#define CLK_CSI1		159
+#define CLK_CODEC		160
+#define CLK_VE			161
+#define CLK_AVS			162
+#define CLK_ACE			163
+#define CLK_HDMI		164
+#define CLK_GPU			165
+
+#endif /* _DT_BINDINGS_CLK_SUN4I_A10_H_ */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/sun4i-a10-pll2.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/sun4i-a10-pll2.h
new file mode 100644
index 0000000000000000000000000000000000000000..071c8112d531b246fcafbb1168285da049df4da8
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/sun4i-a10-pll2.h
@@ -0,0 +1,53 @@
+/*
+ * Copyright 2015 Maxime Ripard
+ *
+ * Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_SUN4I_A10_PLL2_H_
+#define __DT_BINDINGS_CLOCK_SUN4I_A10_PLL2_H_
+
+#define SUN4I_A10_PLL2_1X	0
+#define SUN4I_A10_PLL2_2X	1
+#define SUN4I_A10_PLL2_4X	2
+#define SUN4I_A10_PLL2_8X	3
+
+#endif /* __DT_BINDINGS_CLOCK_SUN4I_A10_PLL2_H_ */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/sun50i-a64-ccu.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/sun50i-a64-ccu.h
new file mode 100644
index 0000000000000000000000000000000000000000..d66432c6e6759730fff0a705edacb88be94fd40b
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/sun50i-a64-ccu.h
@@ -0,0 +1,136 @@
+/*
+ * Copyright (C) 2016 Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _DT_BINDINGS_CLK_SUN50I_A64_H_
+#define _DT_BINDINGS_CLK_SUN50I_A64_H_
+
+#define CLK_PLL_PERIPH0		11
+
+#define CLK_BUS_MIPI_DSI	28
+#define CLK_BUS_CE		29
+#define CLK_BUS_DMA		30
+#define CLK_BUS_MMC0		31
+#define CLK_BUS_MMC1		32
+#define CLK_BUS_MMC2		33
+#define CLK_BUS_NAND		34
+#define CLK_BUS_DRAM		35
+#define CLK_BUS_EMAC		36
+#define CLK_BUS_TS		37
+#define CLK_BUS_HSTIMER		38
+#define CLK_BUS_SPI0		39
+#define CLK_BUS_SPI1		40
+#define CLK_BUS_OTG		41
+#define CLK_BUS_EHCI0		42
+#define CLK_BUS_EHCI1		43
+#define CLK_BUS_OHCI0		44
+#define CLK_BUS_OHCI1		45
+#define CLK_BUS_VE		46
+#define CLK_BUS_TCON0		47
+#define CLK_BUS_TCON1		48
+#define CLK_BUS_DEINTERLACE	49
+#define CLK_BUS_CSI		50
+#define CLK_BUS_HDMI		51
+#define CLK_BUS_DE		52
+#define CLK_BUS_GPU		53
+#define CLK_BUS_MSGBOX		54
+#define CLK_BUS_SPINLOCK	55
+#define CLK_BUS_CODEC		56
+#define CLK_BUS_SPDIF		57
+#define CLK_BUS_PIO		58
+#define CLK_BUS_THS		59
+#define CLK_BUS_I2S0		60
+#define CLK_BUS_I2S1		61
+#define CLK_BUS_I2S2		62
+#define CLK_BUS_I2C0		63
+#define CLK_BUS_I2C1		64
+#define CLK_BUS_I2C2		65
+#define CLK_BUS_SCR		66
+#define CLK_BUS_UART0		67
+#define CLK_BUS_UART1		68
+#define CLK_BUS_UART2		69
+#define CLK_BUS_UART3		70
+#define CLK_BUS_UART4		71
+#define CLK_BUS_DBG		72
+#define CLK_THS			73
+#define CLK_NAND		74
+#define CLK_MMC0		75
+#define CLK_MMC1		76
+#define CLK_MMC2		77
+#define CLK_TS			78
+#define CLK_CE			79
+#define CLK_SPI0		80
+#define CLK_SPI1		81
+#define CLK_I2S0		82
+#define CLK_I2S1		83
+#define CLK_I2S2		84
+#define CLK_SPDIF		85
+#define CLK_USB_PHY0		86
+#define CLK_USB_PHY1		87
+#define CLK_USB_HSIC		88
+#define CLK_USB_HSIC_12M	89
+
+#define CLK_USB_OHCI0		91
+
+#define CLK_USB_OHCI1		93
+
+#define CLK_DRAM_VE		95
+#define CLK_DRAM_CSI		96
+#define CLK_DRAM_DEINTERLACE	97
+#define CLK_DRAM_TS		98
+#define CLK_DE			99
+#define CLK_TCON0		100
+#define CLK_TCON1		101
+#define CLK_DEINTERLACE		102
+#define CLK_CSI_MISC		103
+#define CLK_CSI_SCLK		104
+#define CLK_CSI_MCLK		105
+#define CLK_VE			106
+#define CLK_AC_DIG		107
+#define CLK_AC_DIG_4X		108
+#define CLK_AVS			109
+#define CLK_HDMI		110
+#define CLK_HDMI_DDC		111
+
+#define CLK_DSI_DPHY		113
+#define CLK_GPU			114
+
+#endif /* _DT_BINDINGS_CLK_SUN50I_H_ */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/sun50i-h6-ccu.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/sun50i-h6-ccu.h
new file mode 100644
index 0000000000000000000000000000000000000000..a1545cd60e75584c762e188674201a7c5f441646
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/sun50i-h6-ccu.h
@@ -0,0 +1,125 @@
+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
+/*
+ * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
+ */
+
+#ifndef _DT_BINDINGS_CLK_SUN50I_H6_H_
+#define _DT_BINDINGS_CLK_SUN50I_H6_H_
+
+#define CLK_PLL_PERIPH0		3
+
+#define CLK_CPUX		21
+
+#define CLK_APB1		26
+
+#define CLK_DE			29
+#define CLK_BUS_DE		30
+#define CLK_DEINTERLACE		31
+#define CLK_BUS_DEINTERLACE	32
+#define CLK_GPU			33
+#define CLK_BUS_GPU		34
+#define CLK_CE			35
+#define CLK_BUS_CE		36
+#define CLK_VE			37
+#define CLK_BUS_VE		38
+#define CLK_EMCE		39
+#define CLK_BUS_EMCE		40
+#define CLK_VP9			41
+#define CLK_BUS_VP9		42
+#define CLK_BUS_DMA		43
+#define CLK_BUS_MSGBOX		44
+#define CLK_BUS_SPINLOCK	45
+#define CLK_BUS_HSTIMER		46
+#define CLK_AVS			47
+#define CLK_BUS_DBG		48
+#define CLK_BUS_PSI		49
+#define CLK_BUS_PWM		50
+#define CLK_BUS_IOMMU		51
+
+#define CLK_MBUS_DMA		53
+#define CLK_MBUS_VE		54
+#define CLK_MBUS_CE		55
+#define CLK_MBUS_TS		56
+#define CLK_MBUS_NAND		57
+#define CLK_MBUS_CSI		58
+#define CLK_MBUS_DEINTERLACE	59
+
+#define CLK_NAND0		61
+#define CLK_NAND1		62
+#define CLK_BUS_NAND		63
+#define CLK_MMC0		64
+#define CLK_MMC1		65
+#define CLK_MMC2		66
+#define CLK_BUS_MMC0		67
+#define CLK_BUS_MMC1		68
+#define CLK_BUS_MMC2		69
+#define CLK_BUS_UART0		70
+#define CLK_BUS_UART1		71
+#define CLK_BUS_UART2		72
+#define CLK_BUS_UART3		73
+#define CLK_BUS_I2C0		74
+#define CLK_BUS_I2C1		75
+#define CLK_BUS_I2C2		76
+#define CLK_BUS_I2C3		77
+#define CLK_BUS_SCR0		78
+#define CLK_BUS_SCR1		79
+#define CLK_SPI0		80
+#define CLK_SPI1		81
+#define CLK_BUS_SPI0		82
+#define CLK_BUS_SPI1		83
+#define CLK_BUS_EMAC		84
+#define CLK_TS			85
+#define CLK_BUS_TS		86
+#define CLK_IR_TX		87
+#define CLK_BUS_IR_TX		88
+#define CLK_BUS_THS		89
+#define CLK_I2S3		90
+#define CLK_I2S0		91
+#define CLK_I2S1		92
+#define CLK_I2S2		93
+#define CLK_BUS_I2S0		94
+#define CLK_BUS_I2S1		95
+#define CLK_BUS_I2S2		96
+#define CLK_BUS_I2S3		97
+#define CLK_SPDIF		98
+#define CLK_BUS_SPDIF		99
+#define CLK_DMIC		100
+#define CLK_BUS_DMIC		101
+#define CLK_AUDIO_HUB		102
+#define CLK_BUS_AUDIO_HUB	103
+#define CLK_USB_OHCI0		104
+#define CLK_USB_PHY0		105
+#define CLK_USB_PHY1		106
+#define CLK_USB_OHCI3		107
+#define CLK_USB_PHY3		108
+#define CLK_USB_HSIC_12M	109
+#define CLK_USB_HSIC		110
+#define CLK_BUS_OHCI0		111
+#define CLK_BUS_OHCI3		112
+#define CLK_BUS_EHCI0		113
+#define CLK_BUS_XHCI		114
+#define CLK_BUS_EHCI3		115
+#define CLK_BUS_OTG		116
+#define CLK_PCIE_REF_100M	117
+#define CLK_PCIE_REF		118
+#define CLK_PCIE_REF_OUT	119
+#define CLK_PCIE_MAXI		120
+#define CLK_PCIE_AUX		121
+#define CLK_BUS_PCIE		122
+#define CLK_HDMI		123
+#define CLK_HDMI_SLOW		124
+#define CLK_HDMI_CEC		125
+#define CLK_BUS_HDMI		126
+#define CLK_BUS_TCON_TOP	127
+#define CLK_TCON_LCD0		128
+#define CLK_BUS_TCON_LCD0	129
+#define CLK_TCON_TV0		130
+#define CLK_BUS_TCON_TV0	131
+#define CLK_CSI_CCI		132
+#define CLK_CSI_TOP		133
+#define CLK_CSI_MCLK		134
+#define CLK_BUS_CSI		135
+#define CLK_HDCP		136
+#define CLK_BUS_HDCP		137
+
+#endif /* _DT_BINDINGS_CLK_SUN50I_H6_H_ */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/sun50i-h6-r-ccu.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/sun50i-h6-r-ccu.h
new file mode 100644
index 0000000000000000000000000000000000000000..76136132a13e98dcfa952b0fc0f02f98b33203b6
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/sun50i-h6-r-ccu.h
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2017 Icenowy Zheng <icenowy@aosc.xyz>
+ */
+
+#ifndef _DT_BINDINGS_CLK_SUN50I_H6_R_CCU_H_
+#define _DT_BINDINGS_CLK_SUN50I_H6_R_CCU_H_
+
+#define CLK_AR100		0
+
+#define CLK_R_APB1		2
+
+#define CLK_R_APB1_TIMER	4
+#define CLK_R_APB1_TWD		5
+#define CLK_R_APB1_PWM		6
+#define CLK_R_APB2_UART		7
+#define CLK_R_APB2_I2C		8
+#define CLK_R_APB1_IR		9
+#define CLK_R_APB1_W1		10
+
+#define CLK_IR			11
+#define CLK_W1			12
+
+#endif /* _DT_BINDINGS_CLK_SUN50I_H6_R_CCU_H_ */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/sun5i-ccu.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/sun5i-ccu.h
new file mode 100644
index 0000000000000000000000000000000000000000..81f34d477aeba7ef4e7baa2512d21dfed2db569b
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/sun5i-ccu.h
@@ -0,0 +1,106 @@
+/*
+ * Copyright 2016 Maxime Ripard
+ *
+ * Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_CLK_SUN5I_H_
+#define _DT_BINDINGS_CLK_SUN5I_H_
+
+#define CLK_HOSC		1
+
+#define CLK_PLL_VIDEO0_2X	9
+
+#define CLK_PLL_VIDEO1_2X	16
+#define CLK_CPU			17
+
+#define CLK_AHB_OTG		23
+#define CLK_AHB_EHCI		24
+#define CLK_AHB_OHCI		25
+#define CLK_AHB_SS		26
+#define CLK_AHB_DMA		27
+#define CLK_AHB_BIST		28
+#define CLK_AHB_MMC0		29
+#define CLK_AHB_MMC1		30
+#define CLK_AHB_MMC2		31
+#define CLK_AHB_NAND		32
+#define CLK_AHB_SDRAM		33
+#define CLK_AHB_EMAC		34
+#define CLK_AHB_TS		35
+#define CLK_AHB_SPI0		36
+#define CLK_AHB_SPI1		37
+#define CLK_AHB_SPI2		38
+#define CLK_AHB_GPS		39
+#define CLK_AHB_HSTIMER		40
+#define CLK_AHB_VE		41
+#define CLK_AHB_TVE		42
+#define CLK_AHB_LCD		43
+#define CLK_AHB_CSI		44
+#define CLK_AHB_HDMI		45
+#define CLK_AHB_DE_BE		46
+#define CLK_AHB_DE_FE		47
+#define CLK_AHB_IEP		48
+#define CLK_AHB_GPU		49
+#define CLK_APB0_CODEC		50
+#define CLK_APB0_SPDIF		51
+#define CLK_APB0_I2S		52
+#define CLK_APB0_PIO		53
+#define CLK_APB0_IR		54
+#define CLK_APB0_KEYPAD		55
+#define CLK_APB1_I2C0		56
+#define CLK_APB1_I2C1		57
+#define CLK_APB1_I2C2		58
+#define CLK_APB1_UART0		59
+#define CLK_APB1_UART1		60
+#define CLK_APB1_UART2		61
+#define CLK_APB1_UART3		62
+#define CLK_NAND		63
+#define CLK_MMC0		64
+#define CLK_MMC1		65
+#define CLK_MMC2		66
+#define CLK_TS			67
+#define CLK_SS			68
+#define CLK_SPI0		69
+#define CLK_SPI1		70
+#define CLK_SPI2		71
+#define CLK_IR			72
+#define CLK_I2S			73
+#define CLK_SPDIF		74
+#define CLK_KEYPAD		75
+#define CLK_USB_OHCI		76
+#define CLK_USB_PHY0		77
+#define CLK_USB_PHY1		78
+#define CLK_GPS			79
+#define CLK_DRAM_VE		80
+#define CLK_DRAM_CSI		81
+#define CLK_DRAM_TS		82
+#define CLK_DRAM_TVE		83
+#define CLK_DRAM_DE_FE		84
+#define CLK_DRAM_DE_BE		85
+#define CLK_DRAM_ACE		86
+#define CLK_DRAM_IEP		87
+#define CLK_DE_BE		88
+#define CLK_DE_FE		89
+#define CLK_TCON_CH0		90
+
+#define CLK_TCON_CH1		92
+#define CLK_CSI			93
+#define CLK_VE			94
+#define CLK_CODEC		95
+#define CLK_AVS			96
+#define CLK_HDMI		97
+#define CLK_GPU			98
+
+#define CLK_IEP			100
+
+#endif /* _DT_BINDINGS_CLK_SUN5I_H_ */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/sun6i-a31-ccu.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/sun6i-a31-ccu.h
new file mode 100644
index 0000000000000000000000000000000000000000..c5d13340184aada0817376a662f7ae247648aeb5
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/sun6i-a31-ccu.h
@@ -0,0 +1,191 @@
+/*
+ * Copyright (C) 2016 Chen-Yu Tsai <wens@csie.org>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _DT_BINDINGS_CLK_SUN6I_A31_H_
+#define _DT_BINDINGS_CLK_SUN6I_A31_H_
+
+#define CLK_PLL_VIDEO0_2X	7
+
+#define CLK_PLL_PERIPH		10
+
+#define CLK_PLL_VIDEO1_2X	13
+
+#define CLK_CPU			18
+
+#define CLK_AHB1_MIPIDSI	23
+#define CLK_AHB1_SS		24
+#define CLK_AHB1_DMA		25
+#define CLK_AHB1_MMC0		26
+#define CLK_AHB1_MMC1		27
+#define CLK_AHB1_MMC2		28
+#define CLK_AHB1_MMC3		29
+#define CLK_AHB1_NAND1		30
+#define CLK_AHB1_NAND0		31
+#define CLK_AHB1_SDRAM		32
+#define CLK_AHB1_EMAC		33
+#define CLK_AHB1_TS		34
+#define CLK_AHB1_HSTIMER	35
+#define CLK_AHB1_SPI0		36
+#define CLK_AHB1_SPI1		37
+#define CLK_AHB1_SPI2		38
+#define CLK_AHB1_SPI3		39
+#define CLK_AHB1_OTG		40
+#define CLK_AHB1_EHCI0		41
+#define CLK_AHB1_EHCI1		42
+#define CLK_AHB1_OHCI0		43
+#define CLK_AHB1_OHCI1		44
+#define CLK_AHB1_OHCI2		45
+#define CLK_AHB1_VE		46
+#define CLK_AHB1_LCD0		47
+#define CLK_AHB1_LCD1		48
+#define CLK_AHB1_CSI		49
+#define CLK_AHB1_HDMI		50
+#define CLK_AHB1_BE0		51
+#define CLK_AHB1_BE1		52
+#define CLK_AHB1_FE0		53
+#define CLK_AHB1_FE1		54
+#define CLK_AHB1_MP		55
+#define CLK_AHB1_GPU		56
+#define CLK_AHB1_DEU0		57
+#define CLK_AHB1_DEU1		58
+#define CLK_AHB1_DRC0		59
+#define CLK_AHB1_DRC1		60
+
+#define CLK_APB1_CODEC		61
+#define CLK_APB1_SPDIF		62
+#define CLK_APB1_DIGITAL_MIC	63
+#define CLK_APB1_PIO		64
+#define CLK_APB1_DAUDIO0	65
+#define CLK_APB1_DAUDIO1	66
+
+#define CLK_APB2_I2C0		67
+#define CLK_APB2_I2C1		68
+#define CLK_APB2_I2C2		69
+#define CLK_APB2_I2C3		70
+#define CLK_APB2_UART0		71
+#define CLK_APB2_UART1		72
+#define CLK_APB2_UART2		73
+#define CLK_APB2_UART3		74
+#define CLK_APB2_UART4		75
+#define CLK_APB2_UART5		76
+
+#define CLK_NAND0		77
+#define CLK_NAND1		78
+#define CLK_MMC0		79
+#define CLK_MMC0_SAMPLE		80
+#define CLK_MMC0_OUTPUT		81
+#define CLK_MMC1		82
+#define CLK_MMC1_SAMPLE		83
+#define CLK_MMC1_OUTPUT		84
+#define CLK_MMC2		85
+#define CLK_MMC2_SAMPLE		86
+#define CLK_MMC2_OUTPUT		87
+#define CLK_MMC3		88
+#define CLK_MMC3_SAMPLE		89
+#define CLK_MMC3_OUTPUT		90
+#define CLK_TS			91
+#define CLK_SS			92
+#define CLK_SPI0		93
+#define CLK_SPI1		94
+#define CLK_SPI2		95
+#define CLK_SPI3		96
+#define CLK_DAUDIO0		97
+#define CLK_DAUDIO1		98
+#define CLK_SPDIF		99
+#define CLK_USB_PHY0		100
+#define CLK_USB_PHY1		101
+#define CLK_USB_PHY2		102
+#define CLK_USB_OHCI0		103
+#define CLK_USB_OHCI1		104
+#define CLK_USB_OHCI2		105
+
+#define CLK_DRAM_VE		110
+#define CLK_DRAM_CSI_ISP	111
+#define CLK_DRAM_TS		112
+#define CLK_DRAM_DRC0		113
+#define CLK_DRAM_DRC1		114
+#define CLK_DRAM_DEU0		115
+#define CLK_DRAM_DEU1		116
+#define CLK_DRAM_FE0		117
+#define CLK_DRAM_FE1		118
+#define CLK_DRAM_BE0		119
+#define CLK_DRAM_BE1		120
+#define CLK_DRAM_MP		121
+
+#define CLK_BE0			122
+#define CLK_BE1			123
+#define CLK_FE0			124
+#define CLK_FE1			125
+#define CLK_MP			126
+#define CLK_LCD0_CH0		127
+#define CLK_LCD1_CH0		128
+#define CLK_LCD0_CH1		129
+#define CLK_LCD1_CH1		130
+#define CLK_CSI0_SCLK		131
+#define CLK_CSI0_MCLK		132
+#define CLK_CSI1_MCLK		133
+#define CLK_VE			134
+#define CLK_CODEC		135
+#define CLK_AVS			136
+#define CLK_DIGITAL_MIC		137
+#define CLK_HDMI		138
+#define CLK_HDMI_DDC		139
+#define CLK_PS			140
+
+#define CLK_MIPI_DSI		143
+#define CLK_MIPI_DSI_DPHY	144
+#define CLK_MIPI_CSI_DPHY	145
+#define CLK_IEP_DRC0		146
+#define CLK_IEP_DRC1		147
+#define CLK_IEP_DEU0		148
+#define CLK_IEP_DEU1		149
+#define CLK_GPU_CORE		150
+#define CLK_GPU_MEMORY		151
+#define CLK_GPU_HYD		152
+#define CLK_ATS			153
+#define CLK_TRACE		154
+
+#define CLK_OUT_A		155
+#define CLK_OUT_B		156
+#define CLK_OUT_C		157
+
+#endif /* _DT_BINDINGS_CLK_SUN6I_A31_H_ */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/sun7i-a20-ccu.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/sun7i-a20-ccu.h
new file mode 100644
index 0000000000000000000000000000000000000000..045a5178da0c618d3ea5cf6f6fa56eda8baf370e
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/sun7i-a20-ccu.h
@@ -0,0 +1,53 @@
+/*
+ * Copyright (C) 2017 Priit Laes <plaes@plaes.org>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _DT_BINDINGS_CLK_SUN7I_A20_H_
+#define _DT_BINDINGS_CLK_SUN7I_A20_H_
+
+#include <dt-bindings/clock/sun4i-a10-ccu.h>
+
+#define CLK_MBUS		166
+#define CLK_HDMI1_SLOW		167
+#define CLK_HDMI1		168
+#define CLK_OUT_A		169
+#define CLK_OUT_B		170
+
+#endif /* _DT_BINDINGS_CLK_SUN7I_A20_H_ */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/sun8i-a23-a33-ccu.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/sun8i-a23-a33-ccu.h
new file mode 100644
index 0000000000000000000000000000000000000000..f8222b6b2cc31b83fceb05596eed826186054ceb
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/sun8i-a23-a33-ccu.h
@@ -0,0 +1,127 @@
+/*
+ * Copyright (C) 2016 Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _DT_BINDINGS_CLK_SUN8I_A23_A33_H_
+#define _DT_BINDINGS_CLK_SUN8I_A23_A33_H_
+
+#define CLK_CPUX		18
+
+#define CLK_BUS_MIPI_DSI	23
+#define CLK_BUS_SS		24
+#define CLK_BUS_DMA		25
+#define CLK_BUS_MMC0		26
+#define CLK_BUS_MMC1		27
+#define CLK_BUS_MMC2		28
+#define CLK_BUS_NAND		29
+#define CLK_BUS_DRAM		30
+#define CLK_BUS_HSTIMER		31
+#define CLK_BUS_SPI0		32
+#define CLK_BUS_SPI1		33
+#define CLK_BUS_OTG		34
+#define CLK_BUS_EHCI		35
+#define CLK_BUS_OHCI		36
+#define CLK_BUS_VE		37
+#define CLK_BUS_LCD		38
+#define CLK_BUS_CSI		39
+#define CLK_BUS_DE_BE		40
+#define CLK_BUS_DE_FE		41
+#define CLK_BUS_GPU		42
+#define CLK_BUS_MSGBOX		43
+#define CLK_BUS_SPINLOCK	44
+#define CLK_BUS_DRC		45
+#define CLK_BUS_SAT		46
+#define CLK_BUS_CODEC		47
+#define CLK_BUS_PIO		48
+#define CLK_BUS_I2S0		49
+#define CLK_BUS_I2S1		50
+#define CLK_BUS_I2C0		51
+#define CLK_BUS_I2C1		52
+#define CLK_BUS_I2C2		53
+#define CLK_BUS_UART0		54
+#define CLK_BUS_UART1		55
+#define CLK_BUS_UART2		56
+#define CLK_BUS_UART3		57
+#define CLK_BUS_UART4		58
+#define CLK_NAND		59
+#define CLK_MMC0		60
+#define CLK_MMC0_SAMPLE		61
+#define CLK_MMC0_OUTPUT		62
+#define CLK_MMC1		63
+#define CLK_MMC1_SAMPLE		64
+#define CLK_MMC1_OUTPUT		65
+#define CLK_MMC2		66
+#define CLK_MMC2_SAMPLE		67
+#define CLK_MMC2_OUTPUT		68
+#define CLK_SS			69
+#define CLK_SPI0		70
+#define CLK_SPI1		71
+#define CLK_I2S0		72
+#define CLK_I2S1		73
+#define CLK_USB_PHY0		74
+#define CLK_USB_PHY1		75
+#define CLK_USB_HSIC		76
+#define CLK_USB_HSIC_12M	77
+#define CLK_USB_OHCI		78
+
+#define CLK_DRAM_VE		80
+#define CLK_DRAM_CSI		81
+#define CLK_DRAM_DRC		82
+#define CLK_DRAM_DE_FE		83
+#define CLK_DRAM_DE_BE		84
+#define CLK_DE_BE		85
+#define CLK_DE_FE		86
+#define CLK_LCD_CH0		87
+#define CLK_LCD_CH1		88
+#define CLK_CSI_SCLK		89
+#define CLK_CSI_MCLK		90
+#define CLK_VE			91
+#define CLK_AC_DIG		92
+#define CLK_AC_DIG_4X		93
+#define CLK_AVS			94
+
+#define CLK_DSI_SCLK		96
+#define CLK_DSI_DPHY		97
+#define CLK_DRC			98
+#define CLK_GPU			99
+#define CLK_ATS			100
+
+#endif /* _DT_BINDINGS_CLK_SUN8I_A23_A33_H_ */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/sun8i-a83t-ccu.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/sun8i-a83t-ccu.h
new file mode 100644
index 0000000000000000000000000000000000000000..78af5085f6308a378a31608bd10bac4db7fcba8b
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/sun8i-a83t-ccu.h
@@ -0,0 +1,140 @@
+/*
+ * Copyright (C) 2017 Chen-Yu Tsai <wens@csie.org>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_SUN8I_A83T_CCU_H_
+#define _DT_BINDINGS_CLOCK_SUN8I_A83T_CCU_H_
+
+#define CLK_PLL_PERIPH		6
+
+#define CLK_PLL_DE		9
+
+#define CLK_C0CPUX		11
+#define CLK_C1CPUX		12
+
+#define CLK_BUS_MIPI_DSI	19
+#define CLK_BUS_SS		20
+#define CLK_BUS_DMA		21
+#define CLK_BUS_MMC0		22
+#define CLK_BUS_MMC1		23
+#define CLK_BUS_MMC2		24
+#define CLK_BUS_NAND		25
+#define CLK_BUS_DRAM		26
+#define CLK_BUS_EMAC		27
+#define CLK_BUS_HSTIMER		28
+#define CLK_BUS_SPI0		29
+#define CLK_BUS_SPI1		30
+#define CLK_BUS_OTG		31
+#define CLK_BUS_EHCI0		32
+#define CLK_BUS_EHCI1		33
+#define CLK_BUS_OHCI0		34
+
+#define CLK_BUS_VE		35
+#define CLK_BUS_TCON0		36
+#define CLK_BUS_TCON1		37
+#define CLK_BUS_CSI		38
+#define CLK_BUS_HDMI		39
+#define CLK_BUS_DE		40
+#define CLK_BUS_GPU		41
+#define CLK_BUS_MSGBOX		42
+#define CLK_BUS_SPINLOCK	43
+
+#define CLK_BUS_SPDIF		44
+#define CLK_BUS_PIO		45
+#define CLK_BUS_I2S0		46
+#define CLK_BUS_I2S1		47
+#define CLK_BUS_I2S2		48
+#define CLK_BUS_TDM		49
+
+#define CLK_BUS_I2C0		50
+#define CLK_BUS_I2C1		51
+#define CLK_BUS_I2C2		52
+#define CLK_BUS_UART0		53
+#define CLK_BUS_UART1		54
+#define CLK_BUS_UART2		55
+#define CLK_BUS_UART3		56
+#define CLK_BUS_UART4		57
+
+#define CLK_NAND		59
+#define CLK_MMC0		60
+#define CLK_MMC0_SAMPLE		61
+#define CLK_MMC0_OUTPUT		62
+#define CLK_MMC1		63
+#define CLK_MMC1_SAMPLE		64
+#define CLK_MMC1_OUTPUT		65
+#define CLK_MMC2		66
+#define CLK_MMC2_SAMPLE		67
+#define CLK_MMC2_OUTPUT		68
+#define CLK_SS			69
+#define CLK_SPI0		70
+#define CLK_SPI1		71
+#define CLK_I2S0		72
+#define CLK_I2S1		73
+#define CLK_I2S2		74
+#define CLK_TDM			75
+#define CLK_SPDIF		76
+#define CLK_USB_PHY0		77
+#define CLK_USB_PHY1		78
+#define CLK_USB_HSIC		79
+#define CLK_USB_HSIC_12M	80
+#define CLK_USB_OHCI0		81
+
+#define CLK_DRAM_VE		83
+#define CLK_DRAM_CSI		84
+
+#define CLK_TCON0		85
+#define CLK_TCON1		86
+#define CLK_CSI_MISC		87
+#define CLK_MIPI_CSI		88
+#define CLK_CSI_MCLK		89
+#define CLK_CSI_SCLK		90
+#define CLK_VE			91
+#define CLK_AVS			92
+#define CLK_HDMI		93
+#define CLK_HDMI_SLOW		94
+
+#define CLK_MIPI_DSI0		96
+#define CLK_MIPI_DSI1		97
+#define CLK_GPU_CORE		98
+#define CLK_GPU_MEMORY		99
+#define CLK_GPU_HYD		100
+
+#endif /* _DT_BINDINGS_CLOCK_SUN8I_A83T_CCU_H_ */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/sun8i-de2.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/sun8i-de2.h
new file mode 100644
index 0000000000000000000000000000000000000000..3bed63b524aa16e6e780b960d80433c3812c501b
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/sun8i-de2.h
@@ -0,0 +1,18 @@
+/*
+ * Copyright (C) 2016 Icenowy Zheng <icenowy@aosc.io>
+ *
+ * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_SUN8I_DE2_H_
+#define _DT_BINDINGS_CLOCK_SUN8I_DE2_H_
+
+#define CLK_BUS_MIXER0		0
+#define CLK_BUS_MIXER1		1
+#define CLK_BUS_WB		2
+
+#define CLK_MIXER0		6
+#define CLK_MIXER1		7
+#define CLK_WB			8
+
+#endif /* _DT_BINDINGS_CLOCK_SUN8I_DE2_H_ */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/sun8i-h3-ccu.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/sun8i-h3-ccu.h
new file mode 100644
index 0000000000000000000000000000000000000000..c5f7e9a70968956e60e40ace87f80b842c5a072e
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/sun8i-h3-ccu.h
@@ -0,0 +1,152 @@
+/*
+ * Copyright (C) 2016 Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _DT_BINDINGS_CLK_SUN8I_H3_H_
+#define _DT_BINDINGS_CLK_SUN8I_H3_H_
+
+#define CLK_PLL_VIDEO		6
+
+#define CLK_PLL_PERIPH0		9
+
+#define CLK_CPUX		14
+
+#define CLK_BUS_CE		20
+#define CLK_BUS_DMA		21
+#define CLK_BUS_MMC0		22
+#define CLK_BUS_MMC1		23
+#define CLK_BUS_MMC2		24
+#define CLK_BUS_NAND		25
+#define CLK_BUS_DRAM		26
+#define CLK_BUS_EMAC		27
+#define CLK_BUS_TS		28
+#define CLK_BUS_HSTIMER		29
+#define CLK_BUS_SPI0		30
+#define CLK_BUS_SPI1		31
+#define CLK_BUS_OTG		32
+#define CLK_BUS_EHCI0		33
+#define CLK_BUS_EHCI1		34
+#define CLK_BUS_EHCI2		35
+#define CLK_BUS_EHCI3		36
+#define CLK_BUS_OHCI0		37
+#define CLK_BUS_OHCI1		38
+#define CLK_BUS_OHCI2		39
+#define CLK_BUS_OHCI3		40
+#define CLK_BUS_VE		41
+#define CLK_BUS_TCON0		42
+#define CLK_BUS_TCON1		43
+#define CLK_BUS_DEINTERLACE	44
+#define CLK_BUS_CSI		45
+#define CLK_BUS_TVE		46
+#define CLK_BUS_HDMI		47
+#define CLK_BUS_DE		48
+#define CLK_BUS_GPU		49
+#define CLK_BUS_MSGBOX		50
+#define CLK_BUS_SPINLOCK	51
+#define CLK_BUS_CODEC		52
+#define CLK_BUS_SPDIF		53
+#define CLK_BUS_PIO		54
+#define CLK_BUS_THS		55
+#define CLK_BUS_I2S0		56
+#define CLK_BUS_I2S1		57
+#define CLK_BUS_I2S2		58
+#define CLK_BUS_I2C0		59
+#define CLK_BUS_I2C1		60
+#define CLK_BUS_I2C2		61
+#define CLK_BUS_UART0		62
+#define CLK_BUS_UART1		63
+#define CLK_BUS_UART2		64
+#define CLK_BUS_UART3		65
+#define CLK_BUS_SCR0		66
+#define CLK_BUS_EPHY		67
+#define CLK_BUS_DBG		68
+
+#define CLK_THS			69
+#define CLK_NAND		70
+#define CLK_MMC0		71
+#define CLK_MMC0_SAMPLE		72
+#define CLK_MMC0_OUTPUT		73
+#define CLK_MMC1		74
+#define CLK_MMC1_SAMPLE		75
+#define CLK_MMC1_OUTPUT		76
+#define CLK_MMC2		77
+#define CLK_MMC2_SAMPLE		78
+#define CLK_MMC2_OUTPUT		79
+#define CLK_TS			80
+#define CLK_CE			81
+#define CLK_SPI0		82
+#define CLK_SPI1		83
+#define CLK_I2S0		84
+#define CLK_I2S1		85
+#define CLK_I2S2		86
+#define CLK_SPDIF		87
+#define CLK_USB_PHY0		88
+#define CLK_USB_PHY1		89
+#define CLK_USB_PHY2		90
+#define CLK_USB_PHY3		91
+#define CLK_USB_OHCI0		92
+#define CLK_USB_OHCI1		93
+#define CLK_USB_OHCI2		94
+#define CLK_USB_OHCI3		95
+
+#define CLK_DRAM_VE		97
+#define CLK_DRAM_CSI		98
+#define CLK_DRAM_DEINTERLACE	99
+#define CLK_DRAM_TS		100
+#define CLK_DE			101
+#define CLK_TCON0		102
+#define CLK_TVE			103
+#define CLK_DEINTERLACE		104
+#define CLK_CSI_MISC		105
+#define CLK_CSI_SCLK		106
+#define CLK_CSI_MCLK		107
+#define CLK_VE			108
+#define CLK_AC_DIG		109
+#define CLK_AVS			110
+#define CLK_HDMI		111
+#define CLK_HDMI_DDC		112
+
+#define CLK_GPU			114
+
+/* New clocks imported in H5 */
+#define CLK_BUS_SCR1		115
+
+#endif /* _DT_BINDINGS_CLK_SUN8I_H3_H_ */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/sun8i-r-ccu.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/sun8i-r-ccu.h
new file mode 100644
index 0000000000000000000000000000000000000000..779d20aa0d05cffd8d565f5d570be52f8b94cee6
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/sun8i-r-ccu.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) 2016 Icenowy Zheng <icenowy@aosc.xyz>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _DT_BINDINGS_CLK_SUN8I_R_CCU_H_
+#define _DT_BINDINGS_CLK_SUN8I_R_CCU_H_
+
+#define CLK_AR100		0
+
+#define CLK_APB0_PIO		3
+#define CLK_APB0_IR		4
+#define CLK_APB0_TIMER		5
+#define CLK_APB0_RSB		6
+#define CLK_APB0_UART		7
+/* 8 is reserved for CLK_APB0_W1 on A31 */
+#define CLK_APB0_I2C		9
+#define CLK_APB0_TWD		10
+
+#define CLK_IR			11
+
+#endif /* _DT_BINDINGS_CLK_SUN8I_R_CCU_H_ */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/sun8i-r40-ccu.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/sun8i-r40-ccu.h
new file mode 100644
index 0000000000000000000000000000000000000000..f9e15a235626521726e88b65096943b1a3868c02
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/sun8i-r40-ccu.h
@@ -0,0 +1,191 @@
+/*
+ * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _DT_BINDINGS_CLK_SUN8I_R40_H_
+#define _DT_BINDINGS_CLK_SUN8I_R40_H_
+
+#define CLK_PLL_VIDEO0		7
+
+#define CLK_PLL_VIDEO1		16
+
+#define CLK_CPU			24
+
+#define CLK_BUS_MIPI_DSI	29
+#define CLK_BUS_CE		30
+#define CLK_BUS_DMA		31
+#define CLK_BUS_MMC0		32
+#define CLK_BUS_MMC1		33
+#define CLK_BUS_MMC2		34
+#define CLK_BUS_MMC3		35
+#define CLK_BUS_NAND		36
+#define CLK_BUS_DRAM		37
+#define CLK_BUS_EMAC		38
+#define CLK_BUS_TS		39
+#define CLK_BUS_HSTIMER		40
+#define CLK_BUS_SPI0		41
+#define CLK_BUS_SPI1		42
+#define CLK_BUS_SPI2		43
+#define CLK_BUS_SPI3		44
+#define CLK_BUS_SATA		45
+#define CLK_BUS_OTG		46
+#define CLK_BUS_EHCI0		47
+#define CLK_BUS_EHCI1		48
+#define CLK_BUS_EHCI2		49
+#define CLK_BUS_OHCI0		50
+#define CLK_BUS_OHCI1		51
+#define CLK_BUS_OHCI2		52
+#define CLK_BUS_VE		53
+#define CLK_BUS_MP		54
+#define CLK_BUS_DEINTERLACE	55
+#define CLK_BUS_CSI0		56
+#define CLK_BUS_CSI1		57
+#define CLK_BUS_HDMI1		58
+#define CLK_BUS_HDMI0		59
+#define CLK_BUS_DE		60
+#define CLK_BUS_TVE0		61
+#define CLK_BUS_TVE1		62
+#define CLK_BUS_TVE_TOP		63
+#define CLK_BUS_GMAC		64
+#define CLK_BUS_GPU		65
+#define CLK_BUS_TVD0		66
+#define CLK_BUS_TVD1		67
+#define CLK_BUS_TVD2		68
+#define CLK_BUS_TVD3		69
+#define CLK_BUS_TVD_TOP		70
+#define CLK_BUS_TCON_LCD0	71
+#define CLK_BUS_TCON_LCD1	72
+#define CLK_BUS_TCON_TV0	73
+#define CLK_BUS_TCON_TV1	74
+#define CLK_BUS_TCON_TOP	75
+#define CLK_BUS_CODEC		76
+#define CLK_BUS_SPDIF		77
+#define CLK_BUS_AC97		78
+#define CLK_BUS_PIO		79
+#define CLK_BUS_IR0		80
+#define CLK_BUS_IR1		81
+#define CLK_BUS_THS		82
+#define CLK_BUS_KEYPAD		83
+#define CLK_BUS_I2S0		84
+#define CLK_BUS_I2S1		85
+#define CLK_BUS_I2S2		86
+#define CLK_BUS_I2C0		87
+#define CLK_BUS_I2C1		88
+#define CLK_BUS_I2C2		89
+#define CLK_BUS_I2C3		90
+#define CLK_BUS_CAN		91
+#define CLK_BUS_SCR		92
+#define CLK_BUS_PS20		93
+#define CLK_BUS_PS21		94
+#define CLK_BUS_I2C4		95
+#define CLK_BUS_UART0		96
+#define CLK_BUS_UART1		97
+#define CLK_BUS_UART2		98
+#define CLK_BUS_UART3		99
+#define CLK_BUS_UART4		100
+#define CLK_BUS_UART5		101
+#define CLK_BUS_UART6		102
+#define CLK_BUS_UART7		103
+#define CLK_BUS_DBG		104
+
+#define CLK_THS			105
+#define CLK_NAND		106
+#define CLK_MMC0		107
+#define CLK_MMC1		108
+#define CLK_MMC2		109
+#define CLK_MMC3		110
+#define CLK_TS			111
+#define CLK_CE			112
+#define CLK_SPI0		113
+#define CLK_SPI1		114
+#define CLK_SPI2		115
+#define CLK_SPI3		116
+#define CLK_I2S0		117
+#define CLK_I2S1		118
+#define CLK_I2S2		119
+#define CLK_AC97		120
+#define CLK_SPDIF		121
+#define CLK_KEYPAD		122
+#define CLK_SATA		123
+#define CLK_USB_PHY0		124
+#define CLK_USB_PHY1		125
+#define CLK_USB_PHY2		126
+#define CLK_USB_OHCI0		127
+#define CLK_USB_OHCI1		128
+#define CLK_USB_OHCI2		129
+#define CLK_IR0			130
+#define CLK_IR1			131
+
+#define CLK_DRAM_VE		133
+#define CLK_DRAM_CSI0		134
+#define CLK_DRAM_CSI1		135
+#define CLK_DRAM_TS		136
+#define CLK_DRAM_TVD		137
+#define CLK_DRAM_MP		138
+#define CLK_DRAM_DEINTERLACE	139
+#define CLK_DE			140
+#define CLK_MP			141
+#define CLK_TCON_LCD0		142
+#define CLK_TCON_LCD1		143
+#define CLK_TCON_TV0		144
+#define CLK_TCON_TV1		145
+#define CLK_DEINTERLACE		146
+#define CLK_CSI1_MCLK		147
+#define CLK_CSI_SCLK		148
+#define CLK_CSI0_MCLK		149
+#define CLK_VE			150
+#define CLK_CODEC		151
+#define CLK_AVS			152
+#define CLK_HDMI		153
+#define CLK_HDMI_SLOW		154
+
+#define CLK_DSI_DPHY		156
+#define CLK_TVE0		157
+#define CLK_TVE1		158
+#define CLK_TVD0		159
+#define CLK_TVD1		160
+#define CLK_TVD2		161
+#define CLK_TVD3		162
+#define CLK_GPU			163
+#define CLK_OUTA		164
+#define CLK_OUTB		165
+
+#endif /* _DT_BINDINGS_CLK_SUN8I_R40_H_ */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/sun8i-tcon-top.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/sun8i-tcon-top.h
new file mode 100644
index 0000000000000000000000000000000000000000..25164d76783539c777af7e56f0d89d5396246806
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/sun8i-tcon-top.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/* Copyright (C) 2018 Jernej Skrabec <jernej.skrabec@siol.net> */
+
+#ifndef _DT_BINDINGS_CLOCK_SUN8I_TCON_TOP_H_
+#define _DT_BINDINGS_CLOCK_SUN8I_TCON_TOP_H_
+
+#define CLK_TCON_TOP_TV0	0
+#define CLK_TCON_TOP_TV1	1
+#define CLK_TCON_TOP_DSI	2
+
+#endif /* _DT_BINDINGS_CLOCK_SUN8I_TCON_TOP_H_ */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/sun8i-v3s-ccu.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/sun8i-v3s-ccu.h
new file mode 100644
index 0000000000000000000000000000000000000000..c0d5d5599c87f5a50c740e0da2352f90388b67b2
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/sun8i-v3s-ccu.h
@@ -0,0 +1,107 @@
+/*
+ * Copyright (c) 2016 Icenowy Zheng <icenowy@aosc.xyz>
+ *
+ * Based on sun8i-h3-ccu.h, which is:
+ * Copyright (C) 2016 Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _DT_BINDINGS_CLK_SUN8I_V3S_H_
+#define _DT_BINDINGS_CLK_SUN8I_V3S_H_
+
+#define CLK_CPU			14
+
+#define CLK_BUS_CE		20
+#define CLK_BUS_DMA		21
+#define CLK_BUS_MMC0		22
+#define CLK_BUS_MMC1		23
+#define CLK_BUS_MMC2		24
+#define CLK_BUS_DRAM		25
+#define CLK_BUS_EMAC		26
+#define CLK_BUS_HSTIMER		27
+#define CLK_BUS_SPI0		28
+#define CLK_BUS_OTG		29
+#define CLK_BUS_EHCI0		30
+#define CLK_BUS_OHCI0		31
+#define CLK_BUS_VE		32
+#define CLK_BUS_TCON0		33
+#define CLK_BUS_CSI		34
+#define CLK_BUS_DE		35
+#define CLK_BUS_CODEC		36
+#define CLK_BUS_PIO		37
+#define CLK_BUS_I2C0		38
+#define CLK_BUS_I2C1		39
+#define CLK_BUS_UART0		40
+#define CLK_BUS_UART1		41
+#define CLK_BUS_UART2		42
+#define CLK_BUS_EPHY		43
+#define CLK_BUS_DBG		44
+
+#define CLK_MMC0		45
+#define CLK_MMC0_SAMPLE		46
+#define CLK_MMC0_OUTPUT		47
+#define CLK_MMC1		48
+#define CLK_MMC1_SAMPLE		49
+#define CLK_MMC1_OUTPUT		50
+#define CLK_MMC2		51
+#define CLK_MMC2_SAMPLE		52
+#define CLK_MMC2_OUTPUT		53
+#define CLK_CE			54
+#define CLK_SPI0		55
+#define CLK_USB_PHY0		56
+#define CLK_USB_OHCI0		57
+
+#define CLK_DRAM_VE		59
+#define CLK_DRAM_CSI		60
+#define CLK_DRAM_EHCI		61
+#define CLK_DRAM_OHCI		62
+#define CLK_DE			63
+#define CLK_TCON0		64
+#define CLK_CSI_MISC		65
+#define CLK_CSI0_MCLK		66
+#define CLK_CSI1_SCLK		67
+#define CLK_CSI1_MCLK		68
+#define CLK_VE			69
+#define CLK_AC_DIG		70
+#define CLK_AVS			71
+
+#define CLK_MIPI_CSI		73
+
+#endif /* _DT_BINDINGS_CLK_SUN8I_V3S_H_ */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/sun9i-a80-ccu.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/sun9i-a80-ccu.h
new file mode 100644
index 0000000000000000000000000000000000000000..6ea1492a73a656645fbaef9efbd89295201f3618
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/sun9i-a80-ccu.h
@@ -0,0 +1,162 @@
+/*
+ * Copyright (C) 2016 Chen-Yu Tsai <wens@csie.org>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_SUN9I_A80_CCU_H_
+#define _DT_BINDINGS_CLOCK_SUN9I_A80_CCU_H_
+
+#define CLK_PLL_AUDIO		2
+#define CLK_PLL_PERIPH0		3
+
+#define CLK_C0CPUX		12
+#define CLK_C1CPUX		13
+
+#define CLK_OUT_A		27
+#define CLK_OUT_B		28
+
+#define CLK_NAND0_0		29
+#define CLK_NAND0_1		30
+#define CLK_NAND1_0		31
+#define CLK_NAND1_1		32
+#define CLK_MMC0		33
+#define CLK_MMC0_SAMPLE		34
+#define CLK_MMC0_OUTPUT		35
+#define CLK_MMC1		36
+#define CLK_MMC1_SAMPLE		37
+#define CLK_MMC1_OUTPUT		38
+#define CLK_MMC2		39
+#define CLK_MMC2_SAMPLE		40
+#define CLK_MMC2_OUTPUT		41
+#define CLK_MMC3		42
+#define CLK_MMC3_SAMPLE		43
+#define CLK_MMC3_OUTPUT		44
+#define CLK_TS			45
+#define CLK_SS			46
+#define CLK_SPI0		47
+#define CLK_SPI1		48
+#define CLK_SPI2		49
+#define CLK_SPI3		50
+#define CLK_I2S0		51
+#define CLK_I2S1		52
+#define CLK_SPDIF		53
+#define CLK_SDRAM		54
+#define CLK_DE			55
+#define CLK_EDP			56
+#define CLK_MP			57
+#define CLK_LCD0		58
+#define CLK_LCD1		59
+#define CLK_MIPI_DSI0		60
+#define CLK_MIPI_DSI1		61
+#define CLK_HDMI		62
+#define CLK_HDMI_SLOW		63
+#define CLK_MIPI_CSI		64
+#define CLK_CSI_ISP		65
+#define CLK_CSI_MISC		66
+#define CLK_CSI0_MCLK		67
+#define CLK_CSI1_MCLK		68
+#define CLK_FD			69
+#define CLK_VE			70
+#define CLK_AVS			71
+#define CLK_GPU_CORE		72
+#define CLK_GPU_MEMORY		73
+#define CLK_GPU_AXI		74
+#define CLK_SATA		75
+#define CLK_AC97		76
+#define CLK_MIPI_HSI		77
+#define CLK_GPADC		78
+#define CLK_CIR_TX		79
+
+#define CLK_BUS_FD		80
+#define CLK_BUS_VE		81
+#define CLK_BUS_GPU_CTRL	82
+#define CLK_BUS_SS		83
+#define CLK_BUS_MMC		84
+#define CLK_BUS_NAND0		85
+#define CLK_BUS_NAND1		86
+#define CLK_BUS_SDRAM		87
+#define CLK_BUS_MIPI_HSI	88
+#define CLK_BUS_SATA		89
+#define CLK_BUS_TS		90
+#define CLK_BUS_SPI0		91
+#define CLK_BUS_SPI1		92
+#define CLK_BUS_SPI2		93
+#define CLK_BUS_SPI3		94
+
+#define CLK_BUS_OTG		95
+#define CLK_BUS_USB		96
+#define CLK_BUS_GMAC		97
+#define CLK_BUS_MSGBOX		98
+#define CLK_BUS_SPINLOCK	99
+#define CLK_BUS_HSTIMER		100
+#define CLK_BUS_DMA		101
+
+#define CLK_BUS_LCD0		102
+#define CLK_BUS_LCD1		103
+#define CLK_BUS_EDP		104
+#define CLK_BUS_CSI		105
+#define CLK_BUS_HDMI		106
+#define CLK_BUS_DE		107
+#define CLK_BUS_MP		108
+#define CLK_BUS_MIPI_DSI	109
+
+#define CLK_BUS_SPDIF		110
+#define CLK_BUS_PIO		111
+#define CLK_BUS_AC97		112
+#define CLK_BUS_I2S0		113
+#define CLK_BUS_I2S1		114
+#define CLK_BUS_LRADC		115
+#define CLK_BUS_GPADC		116
+#define CLK_BUS_TWD		117
+#define CLK_BUS_CIR_TX		118
+
+#define CLK_BUS_I2C0		119
+#define CLK_BUS_I2C1		120
+#define CLK_BUS_I2C2		121
+#define CLK_BUS_I2C3		122
+#define CLK_BUS_I2C4		123
+#define CLK_BUS_UART0		124
+#define CLK_BUS_UART1		125
+#define CLK_BUS_UART2		126
+#define CLK_BUS_UART3		127
+#define CLK_BUS_UART4		128
+#define CLK_BUS_UART5		129
+
+#endif /* _DT_BINDINGS_CLOCK_SUN9I_A80_CCU_H_ */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/sun9i-a80-de.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/sun9i-a80-de.h
new file mode 100644
index 0000000000000000000000000000000000000000..3dad6c3cd1314f16eab49b3ad4f7583b5d3cee8c
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/sun9i-a80-de.h
@@ -0,0 +1,80 @@
+/*
+ * Copyright (C) 2016 Chen-Yu Tsai <wens@csie.org>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_SUN9I_A80_DE_H_
+#define _DT_BINDINGS_CLOCK_SUN9I_A80_DE_H_
+
+#define CLK_FE0			0
+#define CLK_FE1			1
+#define CLK_FE2			2
+#define CLK_IEP_DEU0		3
+#define CLK_IEP_DEU1		4
+#define CLK_BE0			5
+#define CLK_BE1			6
+#define CLK_BE2			7
+#define CLK_IEP_DRC0		8
+#define CLK_IEP_DRC1		9
+#define CLK_MERGE		10
+
+#define CLK_DRAM_FE0		11
+#define CLK_DRAM_FE1		12
+#define CLK_DRAM_FE2		13
+#define CLK_DRAM_DEU0		14
+#define CLK_DRAM_DEU1		15
+#define CLK_DRAM_BE0		16
+#define CLK_DRAM_BE1		17
+#define CLK_DRAM_BE2		18
+#define CLK_DRAM_DRC0		19
+#define CLK_DRAM_DRC1		20
+
+#define CLK_BUS_FE0		21
+#define CLK_BUS_FE1		22
+#define CLK_BUS_FE2		23
+#define CLK_BUS_DEU0		24
+#define CLK_BUS_DEU1		25
+#define CLK_BUS_BE0		26
+#define CLK_BUS_BE1		27
+#define CLK_BUS_BE2		28
+#define CLK_BUS_DRC0		29
+#define CLK_BUS_DRC1		30
+
+#endif /* _DT_BINDINGS_CLOCK_SUN9I_A80_DE_H_ */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/sun9i-a80-usb.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/sun9i-a80-usb.h
new file mode 100644
index 0000000000000000000000000000000000000000..783a60d2cceafa2ad6ad74baa10936f967be64e6
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/sun9i-a80-usb.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright (C) 2016 Chen-Yu Tsai <wens@csie.org>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_SUN9I_A80_USB_H_
+#define _DT_BINDINGS_CLOCK_SUN9I_A80_USB_H_
+
+#define CLK_BUS_HCI0	0
+#define CLK_USB_OHCI0	1
+#define CLK_BUS_HCI1	2
+#define CLK_BUS_HCI2	3
+#define CLK_USB_OHCI2	4
+
+#define CLK_USB0_PHY	5
+#define CLK_USB1_HSIC	6
+#define CLK_USB1_PHY	7
+#define CLK_USB2_HSIC	8
+#define CLK_USB2_PHY	9
+#define CLK_USB_HSIC	10
+
+#endif /* _DT_BINDINGS_CLOCK_SUN9I_A80_USB_H_ */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/tegra114-car.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/tegra114-car.h
new file mode 100644
index 0000000000000000000000000000000000000000..bb5c2c999c0596bd3fce25e71119bce7b2230bc2
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/tegra114-car.h
@@ -0,0 +1,344 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * This header provides constants for binding nvidia,tegra114-car.
+ *
+ * The first 160 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB
+ * registers. These IDs often match those in the CAR's RST_DEVICES registers,
+ * but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In
+ * this case, those clocks are assigned IDs above 160 in order to highlight
+ * this issue. Implementations that interpret these clock IDs as bit values
+ * within the CLK_OUT_ENB or RST_DEVICES registers should be careful to
+ * explicitly handle these special cases.
+ *
+ * The balance of the clocks controlled by the CAR are assigned IDs of 160 and
+ * above.
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_TEGRA114_CAR_H
+#define _DT_BINDINGS_CLOCK_TEGRA114_CAR_H
+
+/* 0 */
+/* 1 */
+/* 2 */
+/* 3 */
+#define TEGRA114_CLK_RTC 4
+#define TEGRA114_CLK_TIMER 5
+#define TEGRA114_CLK_UARTA 6
+/* 7 (register bit affects uartb and vfir) */
+/* 8 */
+#define TEGRA114_CLK_SDMMC2 9
+/* 10 (register bit affects spdif_in and spdif_out) */
+#define TEGRA114_CLK_I2S1 11
+#define TEGRA114_CLK_I2C1 12
+#define TEGRA114_CLK_NDFLASH 13
+#define TEGRA114_CLK_SDMMC1 14
+#define TEGRA114_CLK_SDMMC4 15
+/* 16 */
+#define TEGRA114_CLK_PWM 17
+#define TEGRA114_CLK_I2S2 18
+#define TEGRA114_CLK_EPP 19
+/* 20 (register bit affects vi and vi_sensor) */
+#define TEGRA114_CLK_GR2D 21
+#define TEGRA114_CLK_USBD 22
+#define TEGRA114_CLK_ISP 23
+#define TEGRA114_CLK_GR3D 24
+/* 25 */
+#define TEGRA114_CLK_DISP2 26
+#define TEGRA114_CLK_DISP1 27
+#define TEGRA114_CLK_HOST1X 28
+#define TEGRA114_CLK_VCP 29
+#define TEGRA114_CLK_I2S0 30
+/* 31 */
+
+#define TEGRA114_CLK_MC 32
+/* 33 */
+#define TEGRA114_CLK_APBDMA 34
+/* 35 */
+#define TEGRA114_CLK_KBC 36
+/* 37 */
+/* 38 */
+/* 39 (register bit affects fuse and fuse_burn) */
+#define TEGRA114_CLK_KFUSE 40
+#define TEGRA114_CLK_SBC1 41
+#define TEGRA114_CLK_NOR 42
+/* 43 */
+#define TEGRA114_CLK_SBC2 44
+/* 45 */
+#define TEGRA114_CLK_SBC3 46
+#define TEGRA114_CLK_I2C5 47
+#define TEGRA114_CLK_DSIA 48
+/* 49 */
+#define TEGRA114_CLK_MIPI 50
+#define TEGRA114_CLK_HDMI 51
+#define TEGRA114_CLK_CSI 52
+/* 53 */
+#define TEGRA114_CLK_I2C2 54
+#define TEGRA114_CLK_UARTC 55
+#define TEGRA114_CLK_MIPI_CAL 56
+#define TEGRA114_CLK_EMC 57
+#define TEGRA114_CLK_USB2 58
+#define TEGRA114_CLK_USB3 59
+/* 60 */
+#define TEGRA114_CLK_VDE 61
+#define TEGRA114_CLK_BSEA 62
+#define TEGRA114_CLK_BSEV 63
+
+/* 64 */
+#define TEGRA114_CLK_UARTD 65
+/* 66 */
+#define TEGRA114_CLK_I2C3 67
+#define TEGRA114_CLK_SBC4 68
+#define TEGRA114_CLK_SDMMC3 69
+/* 70 */
+#define TEGRA114_CLK_OWR 71
+/* 72 */
+#define TEGRA114_CLK_CSITE 73
+/* 74 */
+/* 75 */
+#define TEGRA114_CLK_LA 76
+#define TEGRA114_CLK_TRACE 77
+#define TEGRA114_CLK_SOC_THERM 78
+#define TEGRA114_CLK_DTV 79
+#define TEGRA114_CLK_NDSPEED 80
+#define TEGRA114_CLK_I2CSLOW 81
+#define TEGRA114_CLK_DSIB 82
+#define TEGRA114_CLK_TSEC 83
+/* 84 */
+/* 85 */
+/* 86 */
+/* 87 */
+/* 88 */
+#define TEGRA114_CLK_XUSB_HOST 89
+/* 90 */
+#define TEGRA114_CLK_MSENC 91
+#define TEGRA114_CLK_CSUS 92
+/* 93 */
+/* 94 */
+/* 95 (bit affects xusb_dev and xusb_dev_src) */
+
+/* 96 */
+/* 97 */
+/* 98 */
+#define TEGRA114_CLK_MSELECT 99
+#define TEGRA114_CLK_TSENSOR 100
+#define TEGRA114_CLK_I2S3 101
+#define TEGRA114_CLK_I2S4 102
+#define TEGRA114_CLK_I2C4 103
+#define TEGRA114_CLK_SBC5 104
+#define TEGRA114_CLK_SBC6 105
+#define TEGRA114_CLK_D_AUDIO 106
+#define TEGRA114_CLK_APBIF 107
+#define TEGRA114_CLK_DAM0 108
+#define TEGRA114_CLK_DAM1 109
+#define TEGRA114_CLK_DAM2 110
+#define TEGRA114_CLK_HDA2CODEC_2X 111
+/* 112 */
+#define TEGRA114_CLK_AUDIO0_2X 113
+#define TEGRA114_CLK_AUDIO1_2X 114
+#define TEGRA114_CLK_AUDIO2_2X 115
+#define TEGRA114_CLK_AUDIO3_2X 116
+#define TEGRA114_CLK_AUDIO4_2X 117
+#define TEGRA114_CLK_SPDIF_2X 118
+#define TEGRA114_CLK_ACTMON 119
+#define TEGRA114_CLK_EXTERN1 120
+#define TEGRA114_CLK_EXTERN2 121
+#define TEGRA114_CLK_EXTERN3 122
+/* 123 */
+/* 124 */
+#define TEGRA114_CLK_HDA 125
+/* 126 */
+#define TEGRA114_CLK_SE 127
+
+#define TEGRA114_CLK_HDA2HDMI 128
+/* 129 */
+/* 130 */
+/* 131 */
+/* 132 */
+/* 133 */
+/* 134 */
+/* 135 */
+#define TEGRA114_CLK_CEC 136
+/* 137 */
+/* 138 */
+/* 139 */
+/* 140 */
+/* 141 */
+/* 142 */
+/* 143 (bit affects xusb_falcon_src, xusb_fs_src, */
+/*      xusb_host_src and xusb_ss_src) */
+#define TEGRA114_CLK_CILAB 144
+#define TEGRA114_CLK_CILCD 145
+#define TEGRA114_CLK_CILE 146
+#define TEGRA114_CLK_DSIALP 147
+#define TEGRA114_CLK_DSIBLP 148
+/* 149 */
+#define TEGRA114_CLK_DDS 150
+/* 151 */
+#define TEGRA114_CLK_DP2 152
+#define TEGRA114_CLK_AMX 153
+#define TEGRA114_CLK_ADX 154
+/* 155 (bit affects dfll_ref and dfll_soc) */
+#define TEGRA114_CLK_XUSB_SS 156
+/* 157 */
+/* 158 */
+/* 159 */
+
+/* 160 */
+/* 161 */
+/* 162 */
+/* 163 */
+/* 164 */
+/* 165 */
+/* 166 */
+/* 167 */
+/* 168 */
+/* 169 */
+/* 170 */
+/* 171 */
+/* 172 */
+/* 173 */
+/* 174 */
+/* 175 */
+/* 176 */
+/* 177 */
+/* 178 */
+/* 179 */
+/* 180 */
+/* 181 */
+/* 182 */
+/* 183 */
+/* 184 */
+/* 185 */
+/* 186 */
+/* 187 */
+/* 188 */
+/* 189 */
+/* 190 */
+/* 191 */
+
+#define TEGRA114_CLK_UARTB 192
+#define TEGRA114_CLK_VFIR 193
+#define TEGRA114_CLK_SPDIF_IN 194
+#define TEGRA114_CLK_SPDIF_OUT 195
+#define TEGRA114_CLK_VI 196
+#define TEGRA114_CLK_VI_SENSOR 197
+#define TEGRA114_CLK_FUSE 198
+#define TEGRA114_CLK_FUSE_BURN 199
+#define TEGRA114_CLK_CLK_32K 200
+#define TEGRA114_CLK_CLK_M 201
+#define TEGRA114_CLK_CLK_M_DIV2 202
+#define TEGRA114_CLK_CLK_M_DIV4 203
+#define TEGRA114_CLK_PLL_REF 204
+#define TEGRA114_CLK_PLL_C 205
+#define TEGRA114_CLK_PLL_C_OUT1 206
+#define TEGRA114_CLK_PLL_C2 207
+#define TEGRA114_CLK_PLL_C3 208
+#define TEGRA114_CLK_PLL_M 209
+#define TEGRA114_CLK_PLL_M_OUT1 210
+#define TEGRA114_CLK_PLL_P 211
+#define TEGRA114_CLK_PLL_P_OUT1 212
+#define TEGRA114_CLK_PLL_P_OUT2 213
+#define TEGRA114_CLK_PLL_P_OUT3 214
+#define TEGRA114_CLK_PLL_P_OUT4 215
+#define TEGRA114_CLK_PLL_A 216
+#define TEGRA114_CLK_PLL_A_OUT0 217
+#define TEGRA114_CLK_PLL_D 218
+#define TEGRA114_CLK_PLL_D_OUT0 219
+#define TEGRA114_CLK_PLL_D2 220
+#define TEGRA114_CLK_PLL_D2_OUT0 221
+#define TEGRA114_CLK_PLL_U 222
+#define TEGRA114_CLK_PLL_U_480M 223
+
+#define TEGRA114_CLK_PLL_U_60M 224
+#define TEGRA114_CLK_PLL_U_48M 225
+#define TEGRA114_CLK_PLL_U_12M 226
+#define TEGRA114_CLK_PLL_X 227
+#define TEGRA114_CLK_PLL_X_OUT0 228
+#define TEGRA114_CLK_PLL_RE_VCO 229
+#define TEGRA114_CLK_PLL_RE_OUT 230
+#define TEGRA114_CLK_PLL_E_OUT0 231
+#define TEGRA114_CLK_SPDIF_IN_SYNC 232
+#define TEGRA114_CLK_I2S0_SYNC 233
+#define TEGRA114_CLK_I2S1_SYNC 234
+#define TEGRA114_CLK_I2S2_SYNC 235
+#define TEGRA114_CLK_I2S3_SYNC 236
+#define TEGRA114_CLK_I2S4_SYNC 237
+#define TEGRA114_CLK_VIMCLK_SYNC 238
+#define TEGRA114_CLK_AUDIO0 239
+#define TEGRA114_CLK_AUDIO1 240
+#define TEGRA114_CLK_AUDIO2 241
+#define TEGRA114_CLK_AUDIO3 242
+#define TEGRA114_CLK_AUDIO4 243
+#define TEGRA114_CLK_SPDIF 244
+#define TEGRA114_CLK_CLK_OUT_1 245
+#define TEGRA114_CLK_CLK_OUT_2 246
+#define TEGRA114_CLK_CLK_OUT_3 247
+#define TEGRA114_CLK_BLINK 248
+/* 249 */
+/* 250 */
+/* 251 */
+#define TEGRA114_CLK_XUSB_HOST_SRC 252
+#define TEGRA114_CLK_XUSB_FALCON_SRC 253
+#define TEGRA114_CLK_XUSB_FS_SRC 254
+#define TEGRA114_CLK_XUSB_SS_SRC 255
+
+#define TEGRA114_CLK_XUSB_DEV_SRC 256
+#define TEGRA114_CLK_XUSB_DEV 257
+#define TEGRA114_CLK_XUSB_HS_SRC 258
+#define TEGRA114_CLK_SCLK 259
+#define TEGRA114_CLK_HCLK 260
+#define TEGRA114_CLK_PCLK 261
+#define TEGRA114_CLK_CCLK_G 262
+#define TEGRA114_CLK_CCLK_LP 263
+#define TEGRA114_CLK_DFLL_REF 264
+#define TEGRA114_CLK_DFLL_SOC 265
+/* 266 */
+/* 267 */
+/* 268 */
+/* 269 */
+/* 270 */
+/* 271 */
+/* 272 */
+/* 273 */
+/* 274 */
+/* 275 */
+/* 276 */
+/* 277 */
+/* 278 */
+/* 279 */
+/* 280 */
+/* 281 */
+/* 282 */
+/* 283 */
+/* 284 */
+/* 285 */
+/* 286 */
+/* 287 */
+
+/* 288 */
+/* 289 */
+/* 290 */
+/* 291 */
+/* 292 */
+/* 293 */
+/* 294 */
+/* 295 */
+/* 296 */
+/* 297 */
+/* 298 */
+/* 299 */
+#define TEGRA114_CLK_AUDIO0_MUX 300
+#define TEGRA114_CLK_AUDIO1_MUX 301
+#define TEGRA114_CLK_AUDIO2_MUX 302
+#define TEGRA114_CLK_AUDIO3_MUX 303
+#define TEGRA114_CLK_AUDIO4_MUX 304
+#define TEGRA114_CLK_SPDIF_MUX 305
+#define TEGRA114_CLK_CLK_OUT_1_MUX 306
+#define TEGRA114_CLK_CLK_OUT_2_MUX 307
+#define TEGRA114_CLK_CLK_OUT_3_MUX 308
+#define TEGRA114_CLK_DSIA_MUX 309
+#define TEGRA114_CLK_DSIB_MUX 310
+#define TEGRA114_CLK_XUSB_SS_DIV2 311
+#define TEGRA114_CLK_CLK_MAX 312
+
+#endif	/* _DT_BINDINGS_CLOCK_TEGRA114_CAR_H */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/tegra124-car-common.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/tegra124-car-common.h
new file mode 100644
index 0000000000000000000000000000000000000000..4331f1df6ebeeda1fc6a9aa7f1dfdeb1b47c5e1c
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/tegra124-car-common.h
@@ -0,0 +1,346 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * This header provides constants for binding nvidia,tegra124-car or
+ * nvidia,tegra132-car.
+ *
+ * The first 192 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB
+ * registers. These IDs often match those in the CAR's RST_DEVICES registers,
+ * but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In
+ * this case, those clocks are assigned IDs above 185 in order to highlight
+ * this issue. Implementations that interpret these clock IDs as bit values
+ * within the CLK_OUT_ENB or RST_DEVICES registers should be careful to
+ * explicitly handle these special cases.
+ *
+ * The balance of the clocks controlled by the CAR are assigned IDs of 185 and
+ * above.
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_TEGRA124_CAR_COMMON_H
+#define _DT_BINDINGS_CLOCK_TEGRA124_CAR_COMMON_H
+
+/* 0 */
+/* 1 */
+/* 2 */
+#define TEGRA124_CLK_ISPB 3
+#define TEGRA124_CLK_RTC 4
+#define TEGRA124_CLK_TIMER 5
+#define TEGRA124_CLK_UARTA 6
+/* 7 (register bit affects uartb and vfir) */
+/* 8 */
+#define TEGRA124_CLK_SDMMC2 9
+/* 10 (register bit affects spdif_in and spdif_out) */
+#define TEGRA124_CLK_I2S1 11
+#define TEGRA124_CLK_I2C1 12
+/* 13 */
+#define TEGRA124_CLK_SDMMC1 14
+#define TEGRA124_CLK_SDMMC4 15
+/* 16 */
+#define TEGRA124_CLK_PWM 17
+#define TEGRA124_CLK_I2S2 18
+/* 20 (register bit affects vi and vi_sensor) */
+/* 21 */
+#define TEGRA124_CLK_USBD 22
+#define TEGRA124_CLK_ISP 23
+/* 26 */
+/* 25 */
+#define TEGRA124_CLK_DISP2 26
+#define TEGRA124_CLK_DISP1 27
+#define TEGRA124_CLK_HOST1X 28
+#define TEGRA124_CLK_VCP 29
+#define TEGRA124_CLK_I2S0 30
+/* 31 */
+
+#define TEGRA124_CLK_MC 32
+/* 33 */
+#define TEGRA124_CLK_APBDMA 34
+/* 35 */
+#define TEGRA124_CLK_KBC 36
+/* 37 */
+/* 38 */
+/* 39 (register bit affects fuse and fuse_burn) */
+#define TEGRA124_CLK_KFUSE 40
+#define TEGRA124_CLK_SBC1 41
+#define TEGRA124_CLK_NOR 42
+/* 43 */
+#define TEGRA124_CLK_SBC2 44
+/* 45 */
+#define TEGRA124_CLK_SBC3 46
+#define TEGRA124_CLK_I2C5 47
+#define TEGRA124_CLK_DSIA 48
+/* 49 */
+#define TEGRA124_CLK_MIPI 50
+#define TEGRA124_CLK_HDMI 51
+#define TEGRA124_CLK_CSI 52
+/* 53 */
+#define TEGRA124_CLK_I2C2 54
+#define TEGRA124_CLK_UARTC 55
+#define TEGRA124_CLK_MIPI_CAL 56
+#define TEGRA124_CLK_EMC 57
+#define TEGRA124_CLK_USB2 58
+#define TEGRA124_CLK_USB3 59
+/* 60 */
+#define TEGRA124_CLK_VDE 61
+#define TEGRA124_CLK_BSEA 62
+#define TEGRA124_CLK_BSEV 63
+
+/* 64 */
+#define TEGRA124_CLK_UARTD 65
+/* 66 */
+#define TEGRA124_CLK_I2C3 67
+#define TEGRA124_CLK_SBC4 68
+#define TEGRA124_CLK_SDMMC3 69
+#define TEGRA124_CLK_PCIE 70
+#define TEGRA124_CLK_OWR 71
+#define TEGRA124_CLK_AFI 72
+#define TEGRA124_CLK_CSITE 73
+/* 74 */
+/* 75 */
+#define TEGRA124_CLK_LA 76
+#define TEGRA124_CLK_TRACE 77
+#define TEGRA124_CLK_SOC_THERM 78
+#define TEGRA124_CLK_DTV 79
+/* 80 */
+#define TEGRA124_CLK_I2CSLOW 81
+#define TEGRA124_CLK_DSIB 82
+#define TEGRA124_CLK_TSEC 83
+/* 84 */
+/* 85 */
+/* 86 */
+/* 87 */
+/* 88 */
+#define TEGRA124_CLK_XUSB_HOST 89
+/* 90 */
+#define TEGRA124_CLK_MSENC 91
+#define TEGRA124_CLK_CSUS 92
+/* 93 */
+/* 94 */
+/* 95 (bit affects xusb_dev and xusb_dev_src) */
+
+/* 96 */
+/* 97 */
+/* 98 */
+#define TEGRA124_CLK_MSELECT 99
+#define TEGRA124_CLK_TSENSOR 100
+#define TEGRA124_CLK_I2S3 101
+#define TEGRA124_CLK_I2S4 102
+#define TEGRA124_CLK_I2C4 103
+#define TEGRA124_CLK_SBC5 104
+#define TEGRA124_CLK_SBC6 105
+#define TEGRA124_CLK_D_AUDIO 106
+#define TEGRA124_CLK_APBIF 107
+#define TEGRA124_CLK_DAM0 108
+#define TEGRA124_CLK_DAM1 109
+#define TEGRA124_CLK_DAM2 110
+#define TEGRA124_CLK_HDA2CODEC_2X 111
+/* 112 */
+#define TEGRA124_CLK_AUDIO0_2X 113
+#define TEGRA124_CLK_AUDIO1_2X 114
+#define TEGRA124_CLK_AUDIO2_2X 115
+#define TEGRA124_CLK_AUDIO3_2X 116
+#define TEGRA124_CLK_AUDIO4_2X 117
+#define TEGRA124_CLK_SPDIF_2X 118
+#define TEGRA124_CLK_ACTMON 119
+#define TEGRA124_CLK_EXTERN1 120
+#define TEGRA124_CLK_EXTERN2 121
+#define TEGRA124_CLK_EXTERN3 122
+#define TEGRA124_CLK_SATA_OOB 123
+#define TEGRA124_CLK_SATA 124
+#define TEGRA124_CLK_HDA 125
+/* 126 */
+#define TEGRA124_CLK_SE 127
+
+#define TEGRA124_CLK_HDA2HDMI 128
+#define TEGRA124_CLK_SATA_COLD 129
+/* 130 */
+/* 131 */
+/* 132 */
+/* 133 */
+/* 134 */
+/* 135 */
+#define TEGRA124_CLK_CEC 136
+/* 137 */
+/* 138 */
+/* 139 */
+/* 140 */
+/* 141 */
+/* 142 */
+/* 143 (bit affects xusb_falcon_src, xusb_fs_src, */
+/*      xusb_host_src and xusb_ss_src) */
+#define TEGRA124_CLK_CILAB 144
+#define TEGRA124_CLK_CILCD 145
+#define TEGRA124_CLK_CILE 146
+#define TEGRA124_CLK_DSIALP 147
+#define TEGRA124_CLK_DSIBLP 148
+#define TEGRA124_CLK_ENTROPY 149
+#define TEGRA124_CLK_DDS 150
+/* 151 */
+#define TEGRA124_CLK_DP2 152
+#define TEGRA124_CLK_AMX 153
+#define TEGRA124_CLK_ADX 154
+/* 155 (bit affects dfll_ref and dfll_soc) */
+#define TEGRA124_CLK_XUSB_SS 156
+/* 157 */
+/* 158 */
+/* 159 */
+
+/* 160 */
+/* 161 */
+/* 162 */
+/* 163 */
+/* 164 */
+/* 165 */
+#define TEGRA124_CLK_I2C6 166
+/* 167 */
+/* 168 */
+/* 169 */
+/* 170 */
+#define TEGRA124_CLK_VIM2_CLK 171
+/* 172 */
+/* 173 */
+/* 174 */
+/* 175 */
+#define TEGRA124_CLK_HDMI_AUDIO 176
+#define TEGRA124_CLK_CLK72MHZ 177
+#define TEGRA124_CLK_VIC03 178
+/* 179 */
+#define TEGRA124_CLK_ADX1 180
+#define TEGRA124_CLK_DPAUX 181
+#define TEGRA124_CLK_SOR0 182
+/* 183 */
+#define TEGRA124_CLK_GPU 184
+#define TEGRA124_CLK_AMX1 185
+/* 186 */
+/* 187 */
+/* 188 */
+/* 189 */
+/* 190 */
+/* 191 */
+#define TEGRA124_CLK_UARTB 192
+#define TEGRA124_CLK_VFIR 193
+#define TEGRA124_CLK_SPDIF_IN 194
+#define TEGRA124_CLK_SPDIF_OUT 195
+#define TEGRA124_CLK_VI 196
+#define TEGRA124_CLK_VI_SENSOR 197
+#define TEGRA124_CLK_FUSE 198
+#define TEGRA124_CLK_FUSE_BURN 199
+#define TEGRA124_CLK_CLK_32K 200
+#define TEGRA124_CLK_CLK_M 201
+#define TEGRA124_CLK_CLK_M_DIV2 202
+#define TEGRA124_CLK_CLK_M_DIV4 203
+#define TEGRA124_CLK_PLL_REF 204
+#define TEGRA124_CLK_PLL_C 205
+#define TEGRA124_CLK_PLL_C_OUT1 206
+#define TEGRA124_CLK_PLL_C2 207
+#define TEGRA124_CLK_PLL_C3 208
+#define TEGRA124_CLK_PLL_M 209
+#define TEGRA124_CLK_PLL_M_OUT1 210
+#define TEGRA124_CLK_PLL_P 211
+#define TEGRA124_CLK_PLL_P_OUT1 212
+#define TEGRA124_CLK_PLL_P_OUT2 213
+#define TEGRA124_CLK_PLL_P_OUT3 214
+#define TEGRA124_CLK_PLL_P_OUT4 215
+#define TEGRA124_CLK_PLL_A 216
+#define TEGRA124_CLK_PLL_A_OUT0 217
+#define TEGRA124_CLK_PLL_D 218
+#define TEGRA124_CLK_PLL_D_OUT0 219
+#define TEGRA124_CLK_PLL_D2 220
+#define TEGRA124_CLK_PLL_D2_OUT0 221
+#define TEGRA124_CLK_PLL_U 222
+#define TEGRA124_CLK_PLL_U_480M 223
+
+#define TEGRA124_CLK_PLL_U_60M 224
+#define TEGRA124_CLK_PLL_U_48M 225
+#define TEGRA124_CLK_PLL_U_12M 226
+/* 227 */
+/* 228 */
+#define TEGRA124_CLK_PLL_RE_VCO 229
+#define TEGRA124_CLK_PLL_RE_OUT 230
+#define TEGRA124_CLK_PLL_E 231
+#define TEGRA124_CLK_SPDIF_IN_SYNC 232
+#define TEGRA124_CLK_I2S0_SYNC 233
+#define TEGRA124_CLK_I2S1_SYNC 234
+#define TEGRA124_CLK_I2S2_SYNC 235
+#define TEGRA124_CLK_I2S3_SYNC 236
+#define TEGRA124_CLK_I2S4_SYNC 237
+#define TEGRA124_CLK_VIMCLK_SYNC 238
+#define TEGRA124_CLK_AUDIO0 239
+#define TEGRA124_CLK_AUDIO1 240
+#define TEGRA124_CLK_AUDIO2 241
+#define TEGRA124_CLK_AUDIO3 242
+#define TEGRA124_CLK_AUDIO4 243
+#define TEGRA124_CLK_SPDIF 244
+#define TEGRA124_CLK_CLK_OUT_1 245
+#define TEGRA124_CLK_CLK_OUT_2 246
+#define TEGRA124_CLK_CLK_OUT_3 247
+#define TEGRA124_CLK_BLINK 248
+/* 249 */
+/* 250 */
+/* 251 */
+#define TEGRA124_CLK_XUSB_HOST_SRC 252
+#define TEGRA124_CLK_XUSB_FALCON_SRC 253
+#define TEGRA124_CLK_XUSB_FS_SRC 254
+#define TEGRA124_CLK_XUSB_SS_SRC 255
+
+#define TEGRA124_CLK_XUSB_DEV_SRC 256
+#define TEGRA124_CLK_XUSB_DEV 257
+#define TEGRA124_CLK_XUSB_HS_SRC 258
+#define TEGRA124_CLK_SCLK 259
+#define TEGRA124_CLK_HCLK 260
+#define TEGRA124_CLK_PCLK 261
+/* 262 */
+/* 263 */
+#define TEGRA124_CLK_DFLL_REF 264
+#define TEGRA124_CLK_DFLL_SOC 265
+#define TEGRA124_CLK_VI_SENSOR2 266
+#define TEGRA124_CLK_PLL_P_OUT5 267
+#define TEGRA124_CLK_CML0 268
+#define TEGRA124_CLK_CML1 269
+#define TEGRA124_CLK_PLL_C4 270
+#define TEGRA124_CLK_PLL_DP 271
+#define TEGRA124_CLK_PLL_E_MUX 272
+#define TEGRA124_CLK_PLL_D_DSI_OUT 273
+/* 274 */
+/* 275 */
+/* 276 */
+/* 277 */
+/* 278 */
+/* 279 */
+/* 280 */
+/* 281 */
+/* 282 */
+/* 283 */
+/* 284 */
+/* 285 */
+/* 286 */
+/* 287 */
+
+/* 288 */
+/* 289 */
+/* 290 */
+/* 291 */
+/* 292 */
+/* 293 */
+/* 294 */
+/* 295 */
+/* 296 */
+/* 297 */
+/* 298 */
+/* 299 */
+#define TEGRA124_CLK_AUDIO0_MUX 300
+#define TEGRA124_CLK_AUDIO1_MUX 301
+#define TEGRA124_CLK_AUDIO2_MUX 302
+#define TEGRA124_CLK_AUDIO3_MUX 303
+#define TEGRA124_CLK_AUDIO4_MUX 304
+#define TEGRA124_CLK_SPDIF_MUX 305
+#define TEGRA124_CLK_CLK_OUT_1_MUX 306
+#define TEGRA124_CLK_CLK_OUT_2_MUX 307
+#define TEGRA124_CLK_CLK_OUT_3_MUX 308
+/* 309 */
+/* 310 */
+#define TEGRA124_CLK_SOR0_LVDS 311
+#define TEGRA124_CLK_XUSB_SS_DIV2 312
+
+#define TEGRA124_CLK_PLL_M_UD 313
+#define TEGRA124_CLK_PLL_C_UD 314
+
+#endif	/* _DT_BINDINGS_CLOCK_TEGRA124_CAR_COMMON_H */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/tegra124-car.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/tegra124-car.h
new file mode 100644
index 0000000000000000000000000000000000000000..c520ee2319509033736674a537fad35770583e5d
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/tegra124-car.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * This header provides Tegra124-specific constants for binding
+ * nvidia,tegra124-car.
+ */
+
+#include <dt-bindings/clock/tegra124-car-common.h>
+
+#ifndef _DT_BINDINGS_CLOCK_TEGRA124_CAR_H
+#define _DT_BINDINGS_CLOCK_TEGRA124_CAR_H
+
+#define TEGRA124_CLK_PLL_X		227
+#define TEGRA124_CLK_PLL_X_OUT0		228
+
+#define TEGRA124_CLK_CCLK_G		262
+#define TEGRA124_CLK_CCLK_LP		263
+
+#define TEGRA124_CLK_CLK_MAX		315
+
+#endif	/* _DT_BINDINGS_CLOCK_TEGRA124_CAR_H */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/tegra186-clock.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/tegra186-clock.h
new file mode 100644
index 0000000000000000000000000000000000000000..d6b525f4566fa28f813955cff1da3b5cf43effe1
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/tegra186-clock.h
@@ -0,0 +1,941 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/** @file */
+
+#ifndef _MACH_T186_CLK_T186_H
+#define _MACH_T186_CLK_T186_H
+
+/**
+ * @defgroup clock_ids Clock Identifiers
+ * @{
+ *   @defgroup extern_input external input clocks
+ *   @{
+ *     @def TEGRA186_CLK_OSC
+ *     @def TEGRA186_CLK_CLK_32K
+ *     @def TEGRA186_CLK_DTV_INPUT
+ *     @def TEGRA186_CLK_SOR0_PAD_CLKOUT
+ *     @def TEGRA186_CLK_SOR1_PAD_CLKOUT
+ *     @def TEGRA186_CLK_I2S1_SYNC_INPUT
+ *     @def TEGRA186_CLK_I2S2_SYNC_INPUT
+ *     @def TEGRA186_CLK_I2S3_SYNC_INPUT
+ *     @def TEGRA186_CLK_I2S4_SYNC_INPUT
+ *     @def TEGRA186_CLK_I2S5_SYNC_INPUT
+ *     @def TEGRA186_CLK_I2S6_SYNC_INPUT
+ *     @def TEGRA186_CLK_SPDIFIN_SYNC_INPUT
+ *   @}
+ *
+ *   @defgroup extern_output external output clocks
+ *   @{
+ *     @def TEGRA186_CLK_EXTPERIPH1
+ *     @def TEGRA186_CLK_EXTPERIPH2
+ *     @def TEGRA186_CLK_EXTPERIPH3
+ *     @def TEGRA186_CLK_EXTPERIPH4
+ *   @}
+ *
+ *   @defgroup display_clks display related clocks
+ *   @{
+ *     @def TEGRA186_CLK_CEC
+ *     @def TEGRA186_CLK_DSIC
+ *     @def TEGRA186_CLK_DSIC_LP
+ *     @def TEGRA186_CLK_DSID
+ *     @def TEGRA186_CLK_DSID_LP
+ *     @def TEGRA186_CLK_DPAUX1
+ *     @def TEGRA186_CLK_DPAUX
+ *     @def TEGRA186_CLK_HDA2HDMICODEC
+ *     @def TEGRA186_CLK_NVDISPLAY_DISP
+ *     @def TEGRA186_CLK_NVDISPLAY_DSC
+ *     @def TEGRA186_CLK_NVDISPLAY_P0
+ *     @def TEGRA186_CLK_NVDISPLAY_P1
+ *     @def TEGRA186_CLK_NVDISPLAY_P2
+ *     @def TEGRA186_CLK_NVDISPLAYHUB
+ *     @def TEGRA186_CLK_SOR_SAFE
+ *     @def TEGRA186_CLK_SOR0
+ *     @def TEGRA186_CLK_SOR0_OUT
+ *     @def TEGRA186_CLK_SOR1
+ *     @def TEGRA186_CLK_SOR1_OUT
+ *     @def TEGRA186_CLK_DSI
+ *     @def TEGRA186_CLK_MIPI_CAL
+ *     @def TEGRA186_CLK_DSIA_LP
+ *     @def TEGRA186_CLK_DSIB
+ *     @def TEGRA186_CLK_DSIB_LP
+ *   @}
+ *
+ *   @defgroup camera_clks camera related clocks
+ *   @{
+ *     @def TEGRA186_CLK_NVCSI
+ *     @def TEGRA186_CLK_NVCSILP
+ *     @def TEGRA186_CLK_VI
+ *   @}
+ *
+ *   @defgroup audio_clks audio related clocks
+ *   @{
+ *     @def TEGRA186_CLK_ACLK
+ *     @def TEGRA186_CLK_ADSP
+ *     @def TEGRA186_CLK_ADSPNEON
+ *     @def TEGRA186_CLK_AHUB
+ *     @def TEGRA186_CLK_APE
+ *     @def TEGRA186_CLK_APB2APE
+ *     @def TEGRA186_CLK_AUD_MCLK
+ *     @def TEGRA186_CLK_DMIC1
+ *     @def TEGRA186_CLK_DMIC2
+ *     @def TEGRA186_CLK_DMIC3
+ *     @def TEGRA186_CLK_DMIC4
+ *     @def TEGRA186_CLK_DSPK1
+ *     @def TEGRA186_CLK_DSPK2
+ *     @def TEGRA186_CLK_HDA
+ *     @def TEGRA186_CLK_HDA2CODEC_2X
+ *     @def TEGRA186_CLK_I2S1
+ *     @def TEGRA186_CLK_I2S2
+ *     @def TEGRA186_CLK_I2S3
+ *     @def TEGRA186_CLK_I2S4
+ *     @def TEGRA186_CLK_I2S5
+ *     @def TEGRA186_CLK_I2S6
+ *     @def TEGRA186_CLK_MAUD
+ *     @def TEGRA186_CLK_PLL_A_OUT0
+ *     @def TEGRA186_CLK_SPDIF_DOUBLER
+ *     @def TEGRA186_CLK_SPDIF_IN
+ *     @def TEGRA186_CLK_SPDIF_OUT
+ *     @def TEGRA186_CLK_SYNC_DMIC1
+ *     @def TEGRA186_CLK_SYNC_DMIC2
+ *     @def TEGRA186_CLK_SYNC_DMIC3
+ *     @def TEGRA186_CLK_SYNC_DMIC4
+ *     @def TEGRA186_CLK_SYNC_DMIC5
+ *     @def TEGRA186_CLK_SYNC_DSPK1
+ *     @def TEGRA186_CLK_SYNC_DSPK2
+ *     @def TEGRA186_CLK_SYNC_I2S1
+ *     @def TEGRA186_CLK_SYNC_I2S2
+ *     @def TEGRA186_CLK_SYNC_I2S3
+ *     @def TEGRA186_CLK_SYNC_I2S4
+ *     @def TEGRA186_CLK_SYNC_I2S5
+ *     @def TEGRA186_CLK_SYNC_I2S6
+ *     @def TEGRA186_CLK_SYNC_SPDIF
+ *   @}
+ *
+ *   @defgroup uart_clks UART clocks
+ *   @{
+ *     @def TEGRA186_CLK_AON_UART_FST_MIPI_CAL
+ *     @def TEGRA186_CLK_UARTA
+ *     @def TEGRA186_CLK_UARTB
+ *     @def TEGRA186_CLK_UARTC
+ *     @def TEGRA186_CLK_UARTD
+ *     @def TEGRA186_CLK_UARTE
+ *     @def TEGRA186_CLK_UARTF
+ *     @def TEGRA186_CLK_UARTG
+ *     @def TEGRA186_CLK_UART_FST_MIPI_CAL
+ *   @}
+ *
+ *   @defgroup i2c_clks I2C clocks
+ *   @{
+ *     @def TEGRA186_CLK_AON_I2C_SLOW
+ *     @def TEGRA186_CLK_I2C1
+ *     @def TEGRA186_CLK_I2C2
+ *     @def TEGRA186_CLK_I2C3
+ *     @def TEGRA186_CLK_I2C4
+ *     @def TEGRA186_CLK_I2C5
+ *     @def TEGRA186_CLK_I2C6
+ *     @def TEGRA186_CLK_I2C8
+ *     @def TEGRA186_CLK_I2C9
+ *     @def TEGRA186_CLK_I2C1
+ *     @def TEGRA186_CLK_I2C12
+ *     @def TEGRA186_CLK_I2C13
+ *     @def TEGRA186_CLK_I2C14
+ *     @def TEGRA186_CLK_I2C_SLOW
+ *     @def TEGRA186_CLK_VI_I2C
+ *   @}
+ *
+ *   @defgroup spi_clks SPI clocks
+ *   @{
+ *     @def TEGRA186_CLK_SPI1
+ *     @def TEGRA186_CLK_SPI2
+ *     @def TEGRA186_CLK_SPI3
+ *     @def TEGRA186_CLK_SPI4
+ *   @}
+ *
+ *   @defgroup storage storage related clocks
+ *   @{
+ *     @def TEGRA186_CLK_SATA
+ *     @def TEGRA186_CLK_SATA_OOB
+ *     @def TEGRA186_CLK_SATA_IOBIST
+ *     @def TEGRA186_CLK_SDMMC_LEGACY_TM
+ *     @def TEGRA186_CLK_SDMMC1
+ *     @def TEGRA186_CLK_SDMMC2
+ *     @def TEGRA186_CLK_SDMMC3
+ *     @def TEGRA186_CLK_SDMMC4
+ *     @def TEGRA186_CLK_QSPI
+ *     @def TEGRA186_CLK_QSPI_OUT
+ *     @def TEGRA186_CLK_UFSDEV_REF
+ *     @def TEGRA186_CLK_UFSHC
+ *   @}
+ *
+ *   @defgroup pwm_clks PWM clocks
+ *   @{
+ *     @def TEGRA186_CLK_PWM1
+ *     @def TEGRA186_CLK_PWM2
+ *     @def TEGRA186_CLK_PWM3
+ *     @def TEGRA186_CLK_PWM4
+ *     @def TEGRA186_CLK_PWM5
+ *     @def TEGRA186_CLK_PWM6
+ *     @def TEGRA186_CLK_PWM7
+ *     @def TEGRA186_CLK_PWM8
+ *   @}
+ *
+ *   @defgroup plls PLLs and related clocks
+ *   @{
+ *     @def TEGRA186_CLK_PLLREFE_OUT_GATED
+ *     @def TEGRA186_CLK_PLLREFE_OUT1
+ *     @def TEGRA186_CLK_PLLD_OUT1
+ *     @def TEGRA186_CLK_PLLP_OUT0
+ *     @def TEGRA186_CLK_PLLP_OUT5
+ *     @def TEGRA186_CLK_PLLA
+ *     @def TEGRA186_CLK_PLLE_PWRSEQ
+ *     @def TEGRA186_CLK_PLLA_OUT1
+ *     @def TEGRA186_CLK_PLLREFE_REF
+ *     @def TEGRA186_CLK_UPHY_PLL0_PWRSEQ
+ *     @def TEGRA186_CLK_UPHY_PLL1_PWRSEQ
+ *     @def TEGRA186_CLK_PLLREFE_PLLE_PASSTHROUGH
+ *     @def TEGRA186_CLK_PLLREFE_PEX
+ *     @def TEGRA186_CLK_PLLREFE_IDDQ
+ *     @def TEGRA186_CLK_PLLC_OUT_AON
+ *     @def TEGRA186_CLK_PLLC_OUT_ISP
+ *     @def TEGRA186_CLK_PLLC_OUT_VE
+ *     @def TEGRA186_CLK_PLLC4_OUT
+ *     @def TEGRA186_CLK_PLLREFE_OUT
+ *     @def TEGRA186_CLK_PLLREFE_PLL_REF
+ *     @def TEGRA186_CLK_PLLE
+ *     @def TEGRA186_CLK_PLLC
+ *     @def TEGRA186_CLK_PLLP
+ *     @def TEGRA186_CLK_PLLD
+ *     @def TEGRA186_CLK_PLLD2
+ *     @def TEGRA186_CLK_PLLREFE_VCO
+ *     @def TEGRA186_CLK_PLLC2
+ *     @def TEGRA186_CLK_PLLC3
+ *     @def TEGRA186_CLK_PLLDP
+ *     @def TEGRA186_CLK_PLLC4_VCO
+ *     @def TEGRA186_CLK_PLLA1
+ *     @def TEGRA186_CLK_PLLNVCSI
+ *     @def TEGRA186_CLK_PLLDISPHUB
+ *     @def TEGRA186_CLK_PLLD3
+ *     @def TEGRA186_CLK_PLLBPMPCAM
+ *     @def TEGRA186_CLK_PLLAON
+ *     @def TEGRA186_CLK_PLLU
+ *     @def TEGRA186_CLK_PLLC4_VCO_DIV2
+ *     @def TEGRA186_CLK_PLL_REF
+ *     @def TEGRA186_CLK_PLLREFE_OUT1_DIV5
+ *     @def TEGRA186_CLK_UTMIP_PLL_PWRSEQ
+ *     @def TEGRA186_CLK_PLL_U_48M
+ *     @def TEGRA186_CLK_PLL_U_480M
+ *     @def TEGRA186_CLK_PLLC4_OUT0
+ *     @def TEGRA186_CLK_PLLC4_OUT1
+ *     @def TEGRA186_CLK_PLLC4_OUT2
+ *     @def TEGRA186_CLK_PLLC4_OUT_MUX
+ *     @def TEGRA186_CLK_DFLLDISP_DIV
+ *     @def TEGRA186_CLK_PLLDISPHUB_DIV
+ *     @def TEGRA186_CLK_PLLP_DIV8
+ *   @}
+ *
+ *   @defgroup nafll_clks NAFLL clock sources
+ *   @{
+ *     @def TEGRA186_CLK_NAFLL_AXI_CBB
+ *     @def TEGRA186_CLK_NAFLL_BCPU
+ *     @def TEGRA186_CLK_NAFLL_BPMP
+ *     @def TEGRA186_CLK_NAFLL_DISP
+ *     @def TEGRA186_CLK_NAFLL_GPU
+ *     @def TEGRA186_CLK_NAFLL_ISP
+ *     @def TEGRA186_CLK_NAFLL_MCPU
+ *     @def TEGRA186_CLK_NAFLL_NVDEC
+ *     @def TEGRA186_CLK_NAFLL_NVENC
+ *     @def TEGRA186_CLK_NAFLL_NVJPG
+ *     @def TEGRA186_CLK_NAFLL_SCE
+ *     @def TEGRA186_CLK_NAFLL_SE
+ *     @def TEGRA186_CLK_NAFLL_TSEC
+ *     @def TEGRA186_CLK_NAFLL_TSECB
+ *     @def TEGRA186_CLK_NAFLL_VI
+ *     @def TEGRA186_CLK_NAFLL_VIC
+ *   @}
+ *
+ *   @defgroup mphy MPHY related clocks
+ *   @{
+ *     @def TEGRA186_CLK_MPHY_L0_RX_SYMB
+ *     @def TEGRA186_CLK_MPHY_L0_RX_LS_BIT
+ *     @def TEGRA186_CLK_MPHY_L0_TX_SYMB
+ *     @def TEGRA186_CLK_MPHY_L0_TX_LS_3XBIT
+ *     @def TEGRA186_CLK_MPHY_L0_RX_ANA
+ *     @def TEGRA186_CLK_MPHY_L1_RX_ANA
+ *     @def TEGRA186_CLK_MPHY_IOBIST
+ *     @def TEGRA186_CLK_MPHY_TX_1MHZ_REF
+ *     @def TEGRA186_CLK_MPHY_CORE_PLL_FIXED
+ *   @}
+ *
+ *   @defgroup eavb EAVB related clocks
+ *   @{
+ *     @def TEGRA186_CLK_EQOS_AXI
+ *     @def TEGRA186_CLK_EQOS_PTP_REF
+ *     @def TEGRA186_CLK_EQOS_RX
+ *     @def TEGRA186_CLK_EQOS_RX_INPUT
+ *     @def TEGRA186_CLK_EQOS_TX
+ *   @}
+ *
+ *   @defgroup usb USB related clocks
+ *   @{
+ *     @def TEGRA186_CLK_PEX_USB_PAD0_MGMT
+ *     @def TEGRA186_CLK_PEX_USB_PAD1_MGMT
+ *     @def TEGRA186_CLK_HSIC_TRK
+ *     @def TEGRA186_CLK_USB2_TRK
+ *     @def TEGRA186_CLK_USB2_HSIC_TRK
+ *     @def TEGRA186_CLK_XUSB_CORE_SS
+ *     @def TEGRA186_CLK_XUSB_CORE_DEV
+ *     @def TEGRA186_CLK_XUSB_FALCON
+ *     @def TEGRA186_CLK_XUSB_FS
+ *     @def TEGRA186_CLK_XUSB
+ *     @def TEGRA186_CLK_XUSB_DEV
+ *     @def TEGRA186_CLK_XUSB_HOST
+ *     @def TEGRA186_CLK_XUSB_SS
+ *   @}
+ *
+ *   @defgroup bigblock compute block related clocks
+ *   @{
+ *     @def TEGRA186_CLK_GPCCLK
+ *     @def TEGRA186_CLK_GPC2CLK
+ *     @def TEGRA186_CLK_GPU
+ *     @def TEGRA186_CLK_HOST1X
+ *     @def TEGRA186_CLK_ISP
+ *     @def TEGRA186_CLK_NVDEC
+ *     @def TEGRA186_CLK_NVENC
+ *     @def TEGRA186_CLK_NVJPG
+ *     @def TEGRA186_CLK_SE
+ *     @def TEGRA186_CLK_TSEC
+ *     @def TEGRA186_CLK_TSECB
+ *     @def TEGRA186_CLK_VIC
+ *   @}
+ *
+ *   @defgroup can CAN bus related clocks
+ *   @{
+ *     @def TEGRA186_CLK_CAN1
+ *     @def TEGRA186_CLK_CAN1_HOST
+ *     @def TEGRA186_CLK_CAN2
+ *     @def TEGRA186_CLK_CAN2_HOST
+ *   @}
+ *
+ *   @defgroup system basic system clocks
+ *   @{
+ *     @def TEGRA186_CLK_ACTMON
+ *     @def TEGRA186_CLK_AON_APB
+ *     @def TEGRA186_CLK_AON_CPU_NIC
+ *     @def TEGRA186_CLK_AON_NIC
+ *     @def TEGRA186_CLK_AXI_CBB
+ *     @def TEGRA186_CLK_BPMP_APB
+ *     @def TEGRA186_CLK_BPMP_CPU_NIC
+ *     @def TEGRA186_CLK_BPMP_NIC_RATE
+ *     @def TEGRA186_CLK_CLK_M
+ *     @def TEGRA186_CLK_EMC
+ *     @def TEGRA186_CLK_MSS_ENCRYPT
+ *     @def TEGRA186_CLK_SCE_APB
+ *     @def TEGRA186_CLK_SCE_CPU_NIC
+ *     @def TEGRA186_CLK_SCE_NIC
+ *     @def TEGRA186_CLK_TSC
+ *   @}
+ *
+ *   @defgroup pcie_clks PCIe related clocks
+ *   @{
+ *     @def TEGRA186_CLK_AFI
+ *     @def TEGRA186_CLK_PCIE
+ *     @def TEGRA186_CLK_PCIE2_IOBIST
+ *     @def TEGRA186_CLK_PCIERX0
+ *     @def TEGRA186_CLK_PCIERX1
+ *     @def TEGRA186_CLK_PCIERX2
+ *     @def TEGRA186_CLK_PCIERX3
+ *     @def TEGRA186_CLK_PCIERX4
+ *   @}
+ */
+
+/** @brief output of gate CLK_ENB_FUSE */
+#define TEGRA186_CLK_FUSE 0
+/**
+ * @brief It's not what you think
+ * @details output of gate CLK_ENB_GPU. This output connects to the GPU
+ * pwrclk. @warning: This is almost certainly not the clock you think
+ * it is. If you're looking for the clock of the graphics engine, see
+ * TEGRA186_GPCCLK
+ */
+#define TEGRA186_CLK_GPU 1
+/** @brief output of gate CLK_ENB_PCIE */
+#define TEGRA186_CLK_PCIE 3
+/** @brief output of the divider IPFS_CLK_DIVISOR */
+#define TEGRA186_CLK_AFI 4
+/** @brief output of gate CLK_ENB_PCIE2_IOBIST */
+#define TEGRA186_CLK_PCIE2_IOBIST 5
+/** @brief output of gate CLK_ENB_PCIERX0*/
+#define TEGRA186_CLK_PCIERX0 6
+/** @brief output of gate CLK_ENB_PCIERX1*/
+#define TEGRA186_CLK_PCIERX1 7
+/** @brief output of gate CLK_ENB_PCIERX2*/
+#define TEGRA186_CLK_PCIERX2 8
+/** @brief output of gate CLK_ENB_PCIERX3*/
+#define TEGRA186_CLK_PCIERX3 9
+/** @brief output of gate CLK_ENB_PCIERX4*/
+#define TEGRA186_CLK_PCIERX4 10
+/** @brief output branch of PLL_C for ISP, controlled by gate CLK_ENB_PLLC_OUT_ISP */
+#define TEGRA186_CLK_PLLC_OUT_ISP 11
+/** @brief output branch of PLL_C for VI, controlled by gate CLK_ENB_PLLC_OUT_VE */
+#define TEGRA186_CLK_PLLC_OUT_VE 12
+/** @brief output branch of PLL_C for AON domain, controlled by gate CLK_ENB_PLLC_OUT_AON */
+#define TEGRA186_CLK_PLLC_OUT_AON 13
+/** @brief output of gate CLK_ENB_SOR_SAFE */
+#define TEGRA186_CLK_SOR_SAFE 39
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S2 */
+#define TEGRA186_CLK_I2S2 42
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S3 */
+#define TEGRA186_CLK_I2S3 43
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPDF_IN */
+#define TEGRA186_CLK_SPDIF_IN 44
+/** @brief output of gate CLK_ENB_SPDIF_DOUBLER */
+#define TEGRA186_CLK_SPDIF_DOUBLER 45
+/**  @clkdesc{spi_clks, out, mux, CLK_RST_CONTROLLER_CLK_SOURCE_SPI3} */
+#define TEGRA186_CLK_SPI3 46
+/** @clkdesc{i2c_clks, out, mux, CLK_RST_CONTROLLER_CLK_SOURCE_I2C1} */
+#define TEGRA186_CLK_I2C1 47
+/** @clkdesc{i2c_clks, out, mux, CLK_RST_CONTROLLER_CLK_SOURCE_I2C5} */
+#define TEGRA186_CLK_I2C5 48
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPI1 */
+#define TEGRA186_CLK_SPI1 49
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_ISP */
+#define TEGRA186_CLK_ISP 50
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_VI */
+#define TEGRA186_CLK_VI 51
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1 */
+#define TEGRA186_CLK_SDMMC1 52
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2 */
+#define TEGRA186_CLK_SDMMC2 53
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4 */
+#define TEGRA186_CLK_SDMMC4 54
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTA */
+#define TEGRA186_CLK_UARTA 55
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTB */
+#define TEGRA186_CLK_UARTB 56
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X */
+#define TEGRA186_CLK_HOST1X 57
+/**
+ * @brief controls the EMC clock frequency.
+ * @details Doing a clk_set_rate on this clock will select the
+ * appropriate clock source, program the source rate and execute a
+ * specific sequence to switch to the new clock source for both memory
+ * controllers. This can be used to control the balance between memory
+ * throughput and memory controller power.
+ */
+#define TEGRA186_CLK_EMC 58
+/* @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH4 */
+#define TEGRA186_CLK_EXTPERIPH4 73
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPI4 */
+#define TEGRA186_CLK_SPI4 74
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C3 */
+#define TEGRA186_CLK_I2C3 75
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3 */
+#define TEGRA186_CLK_SDMMC3 76
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTD */
+#define TEGRA186_CLK_UARTD 77
+/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S1 */
+#define TEGRA186_CLK_I2S1 79
+/** output of gate CLK_ENB_DTV */
+#define TEGRA186_CLK_DTV 80
+/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_TSEC */
+#define TEGRA186_CLK_TSEC 81
+/** @brief output of gate CLK_ENB_DP2 */
+#define TEGRA186_CLK_DP2 82
+/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S4 */
+#define TEGRA186_CLK_I2S4 84
+/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S5 */
+#define TEGRA186_CLK_I2S5 85
+/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C4 */
+#define TEGRA186_CLK_I2C4 86
+/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AHUB */
+#define TEGRA186_CLK_AHUB 87
+/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_HDA2CODEC_2X */
+#define TEGRA186_CLK_HDA2CODEC_2X 88
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH1 */
+#define TEGRA186_CLK_EXTPERIPH1 89
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH2 */
+#define TEGRA186_CLK_EXTPERIPH2 90
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH3 */
+#define TEGRA186_CLK_EXTPERIPH3 91
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C_SLOW */
+#define TEGRA186_CLK_I2C_SLOW 92
+/** @brief output of the SOR1_CLK_SRC mux in CLK_RST_CONTROLLER_CLK_SOURCE_SOR1 */
+#define TEGRA186_CLK_SOR1 93
+/** @brief output of gate CLK_ENB_CEC */
+#define TEGRA186_CLK_CEC 94
+/** @brief output of gate CLK_ENB_DPAUX1 */
+#define TEGRA186_CLK_DPAUX1 95
+/** @brief output of gate CLK_ENB_DPAUX */
+#define TEGRA186_CLK_DPAUX 96
+/** @brief output of the SOR0_CLK_SRC mux in CLK_RST_CONTROLLER_CLK_SOURCE_SOR0 */
+#define TEGRA186_CLK_SOR0 97
+/** @brief output of gate CLK_ENB_HDA2HDMICODEC */
+#define TEGRA186_CLK_HDA2HDMICODEC 98
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SATA */
+#define TEGRA186_CLK_SATA 99
+/** @brief output of gate CLK_ENB_SATA_OOB */
+#define TEGRA186_CLK_SATA_OOB 100
+/** @brief output of gate CLK_ENB_SATA_IOBIST */
+#define TEGRA186_CLK_SATA_IOBIST 101
+/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_HDA */
+#define TEGRA186_CLK_HDA 102
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SE */
+#define TEGRA186_CLK_SE 103
+/** @brief output of gate CLK_ENB_APB2APE */
+#define TEGRA186_CLK_APB2APE 104
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_APE */
+#define TEGRA186_CLK_APE 105
+/** @brief output of gate CLK_ENB_IQC1 */
+#define TEGRA186_CLK_IQC1 106
+/** @brief output of gate CLK_ENB_IQC2 */
+#define TEGRA186_CLK_IQC2 107
+/** divide by 2 version of TEGRA186_CLK_PLLREFE_VCO */
+#define TEGRA186_CLK_PLLREFE_OUT 108
+/** @brief output of gate CLK_ENB_PLLREFE_PLL_REF */
+#define TEGRA186_CLK_PLLREFE_PLL_REF 109
+/** @brief output of gate CLK_ENB_PLLC4_OUT */
+#define TEGRA186_CLK_PLLC4_OUT 110
+/** @brief output of mux xusb_core_clk_switch on page 67 of T186_Clocks_IAS.doc */
+#define TEGRA186_CLK_XUSB 111
+/** controls xusb_dev_ce signal on page 66 and 67 of T186_Clocks_IAS.doc */
+#define TEGRA186_CLK_XUSB_DEV 112
+/** controls xusb_host_ce signal on page 67 of T186_Clocks_IAS.doc */
+#define TEGRA186_CLK_XUSB_HOST 113
+/** controls xusb_ss_ce signal on page 67 of T186_Clocks_IAS.doc */
+#define TEGRA186_CLK_XUSB_SS 114
+/** @brief output of gate CLK_ENB_DSI */
+#define TEGRA186_CLK_DSI 115
+/** @brief output of gate CLK_ENB_MIPI_CAL */
+#define TEGRA186_CLK_MIPI_CAL 116
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSIA_LP */
+#define TEGRA186_CLK_DSIA_LP 117
+/** @brief output of gate CLK_ENB_DSIB */
+#define TEGRA186_CLK_DSIB 118
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSIB_LP */
+#define TEGRA186_CLK_DSIB_LP 119
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC1 */
+#define TEGRA186_CLK_DMIC1 122
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC2 */
+#define TEGRA186_CLK_DMIC2 123
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AUD_MCLK */
+#define TEGRA186_CLK_AUD_MCLK 124
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C6 */
+#define TEGRA186_CLK_I2C6 125
+/**output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIPI_CAL */
+#define TEGRA186_CLK_UART_FST_MIPI_CAL 126
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_VIC */
+#define TEGRA186_CLK_VIC 127
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM */
+#define TEGRA186_CLK_SDMMC_LEGACY_TM 128
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC */
+#define TEGRA186_CLK_NVDEC 129
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVJPG */
+#define TEGRA186_CLK_NVJPG 130
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVENC */
+#define TEGRA186_CLK_NVENC 131
+/** @brief output of the QSPI_CLK_SRC mux in CLK_RST_CONTROLLER_CLK_SOURCE_QSPI */
+#define TEGRA186_CLK_QSPI 132
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_VI_I2C */
+#define TEGRA186_CLK_VI_I2C 133
+/** @brief output of gate CLK_ENB_HSIC_TRK */
+#define TEGRA186_CLK_HSIC_TRK 134
+/** @brief output of gate CLK_ENB_USB2_TRK */
+#define TEGRA186_CLK_USB2_TRK 135
+/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_MAUD */
+#define TEGRA186_CLK_MAUD 136
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_TSECB */
+#define TEGRA186_CLK_TSECB 137
+/** @brief output of gate CLK_ENB_ADSP */
+#define TEGRA186_CLK_ADSP 138
+/** @brief output of gate CLK_ENB_ADSPNEON */
+#define TEGRA186_CLK_ADSPNEON 139
+/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_RX_LS_SYMB */
+#define TEGRA186_CLK_MPHY_L0_RX_SYMB 140
+/** @brief output of gate CLK_ENB_MPHY_L0_RX_LS_BIT */
+#define TEGRA186_CLK_MPHY_L0_RX_LS_BIT 141
+/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_TX_LS_SYMB */
+#define TEGRA186_CLK_MPHY_L0_TX_SYMB 142
+/** @brief output of gate CLK_ENB_MPHY_L0_TX_LS_3XBIT */
+#define TEGRA186_CLK_MPHY_L0_TX_LS_3XBIT 143
+/** @brief output of gate CLK_ENB_MPHY_L0_RX_ANA */
+#define TEGRA186_CLK_MPHY_L0_RX_ANA 144
+/** @brief output of gate CLK_ENB_MPHY_L1_RX_ANA */
+#define TEGRA186_CLK_MPHY_L1_RX_ANA 145
+/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_IOBIST */
+#define TEGRA186_CLK_MPHY_IOBIST 146
+/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_TX_1MHZ_REF */
+#define TEGRA186_CLK_MPHY_TX_1MHZ_REF 147
+/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_CORE_PLL_FIXED */
+#define TEGRA186_CLK_MPHY_CORE_PLL_FIXED 148
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AXI_CBB */
+#define TEGRA186_CLK_AXI_CBB 149
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC3 */
+#define TEGRA186_CLK_DMIC3 150
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC4 */
+#define TEGRA186_CLK_DMIC4 151
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSPK1 */
+#define TEGRA186_CLK_DSPK1 152
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSPK2 */
+#define TEGRA186_CLK_DSPK2 153
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C6 */
+#define TEGRA186_CLK_I2S6 154
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P0 */
+#define TEGRA186_CLK_NVDISPLAY_P0 155
+/** @brief output of the NVDISPLAY_DISP_CLK_SRC mux in CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_DISP */
+#define TEGRA186_CLK_NVDISPLAY_DISP 156
+/** @brief output of gate CLK_ENB_NVDISPLAY_DSC */
+#define TEGRA186_CLK_NVDISPLAY_DSC 157
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAYHUB */
+#define TEGRA186_CLK_NVDISPLAYHUB 158
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P1 */
+#define TEGRA186_CLK_NVDISPLAY_P1 159
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P2 */
+#define TEGRA186_CLK_NVDISPLAY_P2 160
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_TACH */
+#define TEGRA186_CLK_TACH 166
+/** @brief output of gate CLK_ENB_EQOS */
+#define TEGRA186_CLK_EQOS_AXI 167
+/** @brief output of gate CLK_ENB_EQOS_RX */
+#define TEGRA186_CLK_EQOS_RX 168
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UFSHC_CG_SYS */
+#define TEGRA186_CLK_UFSHC 178
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UFSDEV_REF */
+#define TEGRA186_CLK_UFSDEV_REF 179
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI */
+#define TEGRA186_CLK_NVCSI 180
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVCSILP */
+#define TEGRA186_CLK_NVCSILP 181
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C7 */
+#define TEGRA186_CLK_I2C7 182
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C9 */
+#define TEGRA186_CLK_I2C9 183
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C12 */
+#define TEGRA186_CLK_I2C12 184
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C13 */
+#define TEGRA186_CLK_I2C13 185
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C14 */
+#define TEGRA186_CLK_I2C14 186
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM1 */
+#define TEGRA186_CLK_PWM1 187
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM2 */
+#define TEGRA186_CLK_PWM2 188
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM3 */
+#define TEGRA186_CLK_PWM3 189
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM5 */
+#define TEGRA186_CLK_PWM5 190
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM6 */
+#define TEGRA186_CLK_PWM6 191
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM7 */
+#define TEGRA186_CLK_PWM7 192
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM8 */
+#define TEGRA186_CLK_PWM8 193
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTE */
+#define TEGRA186_CLK_UARTE 194
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTF */
+#define TEGRA186_CLK_UARTF 195
+/** @deprecated */
+#define TEGRA186_CLK_DBGAPB 196
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC */
+#define TEGRA186_CLK_BPMP_CPU_NIC 197
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB */
+#define TEGRA186_CLK_BPMP_APB 199
+/** @brief output of mux controlled by TEGRA186_CLK_SOC_ACTMON */
+#define TEGRA186_CLK_ACTMON 201
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC */
+#define TEGRA186_CLK_AON_CPU_NIC 208
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_CAN1 */
+#define TEGRA186_CLK_CAN1 210
+/** @brief output of gate CLK_ENB_CAN1_HOST */
+#define TEGRA186_CLK_CAN1_HOST 211
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_CAN2 */
+#define TEGRA186_CLK_CAN2 212
+/** @brief output of gate CLK_ENB_CAN2_HOST */
+#define TEGRA186_CLK_CAN2_HOST 213
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB */
+#define TEGRA186_CLK_AON_APB 214
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTC */
+#define TEGRA186_CLK_UARTC 215
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTG */
+#define TEGRA186_CLK_UARTG 216
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AON_UART_FST_MIPI_CAL */
+#define TEGRA186_CLK_AON_UART_FST_MIPI_CAL 217
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C2 */
+#define TEGRA186_CLK_I2C2 218
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C8 */
+#define TEGRA186_CLK_I2C8 219
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C10 */
+#define TEGRA186_CLK_I2C10 220
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AON_I2C_SLOW */
+#define TEGRA186_CLK_AON_I2C_SLOW 221
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPI2 */
+#define TEGRA186_CLK_SPI2 222
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC5 */
+#define TEGRA186_CLK_DMIC5 223
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AON_TOUCH */
+#define TEGRA186_CLK_AON_TOUCH 224
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM4 */
+#define TEGRA186_CLK_PWM4 225
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_TSC. This clock object is read only and is used for all timers in the system. */
+#define TEGRA186_CLK_TSC 226
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_MSS_ENCRYPT */
+#define TEGRA186_CLK_MSS_ENCRYPT 227
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC */
+#define TEGRA186_CLK_SCE_CPU_NIC 228
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB */
+#define TEGRA186_CLK_SCE_APB 230
+/** @brief output of gate CLK_ENB_DSIC */
+#define TEGRA186_CLK_DSIC 231
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSIC_LP */
+#define TEGRA186_CLK_DSIC_LP 232
+/** @brief output of gate CLK_ENB_DSID */
+#define TEGRA186_CLK_DSID 233
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSID_LP */
+#define TEGRA186_CLK_DSID_LP 234
+/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_PEX_SATA_USB_RX_BYP */
+#define TEGRA186_CLK_PEX_SATA_USB_RX_BYP 236
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT */
+#define TEGRA186_CLK_SPDIF_OUT 238
+/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_PTP_REF_CLK_0 */
+#define TEGRA186_CLK_EQOS_PTP_REF 239
+/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_TX_CLK */
+#define TEGRA186_CLK_EQOS_TX 240
+/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_USB2_HSIC_TRK */
+#define TEGRA186_CLK_USB2_HSIC_TRK 241
+/** @brief output of mux xusb_ss_clk_switch on page 66 of T186_Clocks_IAS.doc */
+#define TEGRA186_CLK_XUSB_CORE_SS 242
+/** @brief output of mux xusb_core_dev_clk_switch on page 67 of T186_Clocks_IAS.doc */
+#define TEGRA186_CLK_XUSB_CORE_DEV 243
+/** @brief output of mux xusb_core_falcon_clk_switch on page 67 of T186_Clocks_IAS.doc */
+#define TEGRA186_CLK_XUSB_FALCON 244
+/** @brief output of mux xusb_fs_clk_switch on page 66 of T186_Clocks_IAS.doc */
+#define TEGRA186_CLK_XUSB_FS 245
+/** @brief output of the divider CLK_RST_CONTROLLER_PLLA_OUT */
+#define TEGRA186_CLK_PLL_A_OUT0 246
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S1 */
+#define TEGRA186_CLK_SYNC_I2S1 247
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S2 */
+#define TEGRA186_CLK_SYNC_I2S2 248
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S3 */
+#define TEGRA186_CLK_SYNC_I2S3 249
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S4 */
+#define TEGRA186_CLK_SYNC_I2S4 250
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S5 */
+#define TEGRA186_CLK_SYNC_I2S5 251
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S6 */
+#define TEGRA186_CLK_SYNC_I2S6 252
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK1 */
+#define TEGRA186_CLK_SYNC_DSPK1 253
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK2 */
+#define TEGRA186_CLK_SYNC_DSPK2 254
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC1 */
+#define TEGRA186_CLK_SYNC_DMIC1 255
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC2 */
+#define TEGRA186_CLK_SYNC_DMIC2 256
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC3 */
+#define TEGRA186_CLK_SYNC_DMIC3 257
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC4 */
+#define TEGRA186_CLK_SYNC_DMIC4 259
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_SPDIF */
+#define TEGRA186_CLK_SYNC_SPDIF 260
+/** @brief output of gate CLK_ENB_PLLREFE_OUT */
+#define TEGRA186_CLK_PLLREFE_OUT_GATED 261
+/** @brief output of the divider PLLREFE_DIVP in CLK_RST_CONTROLLER_PLLREFE_BASE. PLLREFE has 2 outputs:
+  *      * VCO/pdiv defined by this clock object
+  *      * VCO/2 defined by TEGRA186_CLK_PLLREFE_OUT
+  */
+#define TEGRA186_CLK_PLLREFE_OUT1 262
+#define TEGRA186_CLK_PLLD_OUT1 267
+/** @brief output of the divider PLLP_DIVP in CLK_RST_CONTROLLER_PLLP_BASE */
+#define TEGRA186_CLK_PLLP_OUT0 269
+/** @brief output of the divider CLK_RST_CONTROLLER_PLLP_OUTC */
+#define TEGRA186_CLK_PLLP_OUT5 270
+/** PLL controlled by CLK_RST_CONTROLLER_PLLA_BASE for use by audio clocks */
+#define TEGRA186_CLK_PLLA 271
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_ACLK_BURST_POLICY divided by the divider controlled by ACLK_CLK_DIVISOR in CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER */
+#define TEGRA186_CLK_ACLK 273
+/** fixed 48MHz clock divided down from TEGRA186_CLK_PLL_U */
+#define TEGRA186_CLK_PLL_U_48M 274
+/** fixed 480MHz clock divided down from TEGRA186_CLK_PLL_U */
+#define TEGRA186_CLK_PLL_U_480M 275
+/** @brief output of the divider PLLC4_DIVP in CLK_RST_CONTROLLER_PLLC4_BASE. Output frequency is TEGRA186_CLK_PLLC4_VCO/PLLC4_DIVP */
+#define TEGRA186_CLK_PLLC4_OUT0 276
+/** fixed /3 divider. Output frequency of this clock is TEGRA186_CLK_PLLC4_VCO/3 */
+#define TEGRA186_CLK_PLLC4_OUT1 277
+/** fixed /5 divider. Output frequency of this clock is TEGRA186_CLK_PLLC4_VCO/5 */
+#define TEGRA186_CLK_PLLC4_OUT2 278
+/** @brief output of mux controlled by PLLC4_CLK_SEL in CLK_RST_CONTROLLER_PLLC4_MISC1 */
+#define TEGRA186_CLK_PLLC4_OUT_MUX 279
+/** @brief output of divider NVDISPLAY_DISP_CLK_DIVISOR in CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_DISP when DFLLDISP_DIV is selected in NVDISPLAY_DISP_CLK_SRC */
+#define TEGRA186_CLK_DFLLDISP_DIV 284
+/** @brief output of divider NVDISPLAY_DISP_CLK_DIVISOR in CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_DISP when PLLDISPHUB_DIV is selected in NVDISPLAY_DISP_CLK_SRC */
+#define TEGRA186_CLK_PLLDISPHUB_DIV 285
+/** fixed /8 divider which is used as the input for TEGRA186_CLK_SOR_SAFE */
+#define TEGRA186_CLK_PLLP_DIV8 286
+/** @brief output of divider CLK_RST_CONTROLLER_BPMP_NIC_RATE */
+#define TEGRA186_CLK_BPMP_NIC 287
+/** @brief output of the divider CLK_RST_CONTROLLER_PLLA1_OUT1 */
+#define TEGRA186_CLK_PLL_A_OUT1 288
+/** @deprecated */
+#define TEGRA186_CLK_GPC2CLK 289
+/** A fake clock which must be enabled during KFUSE read operations to ensure adequate VDD_CORE voltage. */
+#define TEGRA186_CLK_KFUSE 293
+/**
+ * @brief controls the PLLE hardware sequencer.
+ * @details This clock only has enable and disable methods. When the
+ * PLLE hw sequencer is enabled, PLLE, will be enabled or disabled by
+ * hw based on the control signals from the PCIe, SATA and XUSB
+ * clocks. When the PLLE hw sequencer is disabled, the state of PLLE
+ * is controlled by sw using clk_enable/clk_disable on
+ * TEGRA186_CLK_PLLE.
+ */
+#define TEGRA186_CLK_PLLE_PWRSEQ 294
+/** fixed 60MHz clock divided down from, TEGRA186_CLK_PLL_U */
+#define TEGRA186_CLK_PLLREFE_REF 295
+/** @brief output of mux controlled by SOR0_CLK_SEL0 and SOR0_CLK_SEL1 in CLK_RST_CONTROLLER_CLK_SOURCE_SOR0 */
+#define TEGRA186_CLK_SOR0_OUT 296
+/** @brief output of mux controlled by SOR1_CLK_SEL0 and SOR1_CLK_SEL1 in CLK_RST_CONTROLLER_CLK_SOURCE_SOR1 */
+#define TEGRA186_CLK_SOR1_OUT 297
+/** @brief fixed /5 divider.  Output frequency of this clock is TEGRA186_CLK_PLLREFE_OUT1/5. Used as input for TEGRA186_CLK_EQOS_AXI */
+#define TEGRA186_CLK_PLLREFE_OUT1_DIV5 298
+/** @brief controls the UTMIP_PLL (aka PLLU) hardware sqeuencer */
+#define TEGRA186_CLK_UTMIP_PLL_PWRSEQ 301
+/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL0_MGMT */
+#define TEGRA186_CLK_PEX_USB_PAD0_MGMT 302
+/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL1_MGMT */
+#define TEGRA186_CLK_PEX_USB_PAD1_MGMT 303
+/** @brief controls the UPHY_PLL0 hardware sqeuencer */
+#define TEGRA186_CLK_UPHY_PLL0_PWRSEQ 304
+/** @brief controls the UPHY_PLL1 hardware sqeuencer */
+#define TEGRA186_CLK_UPHY_PLL1_PWRSEQ 305
+/** @brief control for PLLREFE_IDDQ in CLK_RST_CONTROLLER_PLLREFE_MISC so the bypass output even be used when the PLL is disabled */
+#define TEGRA186_CLK_PLLREFE_PLLE_PASSTHROUGH 306
+/** @brief output of the mux controlled by PLLREFE_SEL_CLKIN_PEX in CLK_RST_CONTROLLER_PLLREFE_MISC */
+#define TEGRA186_CLK_PLLREFE_PEX 307
+/** @brief control for PLLREFE_IDDQ in CLK_RST_CONTROLLER_PLLREFE_MISC to turn on the PLL when enabled */
+#define TEGRA186_CLK_PLLREFE_IDDQ 308
+/** @brief output of the divider QSPI_CLK_DIV2_SEL in CLK_RST_CONTROLLER_CLK_SOURCE_QSPI */
+#define TEGRA186_CLK_QSPI_OUT 309
+/**
+ * @brief GPC2CLK-div-2
+ * @details fixed /2 divider. Output frequency is
+ * TEGRA186_CLK_GPC2CLK/2. The frequency of this clock is the
+ * frequency at which the GPU graphics engine runs. */
+#define TEGRA186_CLK_GPCCLK 310
+/** @brief output of divider CLK_RST_CONTROLLER_AON_NIC_RATE */
+#define TEGRA186_CLK_AON_NIC 450
+/** @brief output of divider CLK_RST_CONTROLLER_SCE_NIC_RATE */
+#define TEGRA186_CLK_SCE_NIC 451
+/** Fixed 100MHz PLL for PCIe, SATA and superspeed USB */
+#define TEGRA186_CLK_PLLE 512
+/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC_BASE */
+#define TEGRA186_CLK_PLLC 513
+/** Fixed 408MHz PLL for use by peripheral clocks */
+#define TEGRA186_CLK_PLLP 516
+/** @deprecated */
+#define TEGRA186_CLK_PLL_P TEGRA186_CLK_PLLP
+/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLD_BASE for use by DSI */
+#define TEGRA186_CLK_PLLD 518
+/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLD2_BASE for use by HDMI or DP */
+#define TEGRA186_CLK_PLLD2 519
+/**
+ * @brief PLL controlled by CLK_RST_CONTROLLER_PLLREFE_BASE.
+ * @details Note that this clock only controls the VCO output, before
+ * the post-divider. See TEGRA186_CLK_PLLREFE_OUT1 for more
+ * information.
+ */
+#define TEGRA186_CLK_PLLREFE_VCO 520
+/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC2_BASE */
+#define TEGRA186_CLK_PLLC2 521
+/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC3_BASE */
+#define TEGRA186_CLK_PLLC3 522
+/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLDP_BASE for use as the DP link clock */
+#define TEGRA186_CLK_PLLDP 523
+/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC4_BASE */
+#define TEGRA186_CLK_PLLC4_VCO 524
+/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLA1_BASE for use by audio clocks */
+#define TEGRA186_CLK_PLLA1 525
+/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLNVCSI_BASE */
+#define TEGRA186_CLK_PLLNVCSI 526
+/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLDISPHUB_BASE */
+#define TEGRA186_CLK_PLLDISPHUB 527
+/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLD3_BASE for use by HDMI or DP */
+#define TEGRA186_CLK_PLLD3 528
+/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLBPMPCAM_BASE */
+#define TEGRA186_CLK_PLLBPMPCAM 531
+/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLAON_BASE for use by IP blocks in the AON domain */
+#define TEGRA186_CLK_PLLAON 532
+/** Fixed frequency 960MHz PLL for USB and EAVB */
+#define TEGRA186_CLK_PLLU 533
+/** fixed /2 divider. Output frequency is TEGRA186_CLK_PLLC4_VCO/2 */
+#define TEGRA186_CLK_PLLC4_VCO_DIV2 535
+/** @brief NAFLL clock source for AXI_CBB */
+#define TEGRA186_CLK_NAFLL_AXI_CBB 564
+/** @brief NAFLL clock source for BPMP */
+#define TEGRA186_CLK_NAFLL_BPMP 565
+/** @brief NAFLL clock source for ISP */
+#define TEGRA186_CLK_NAFLL_ISP 566
+/** @brief NAFLL clock source for NVDEC */
+#define TEGRA186_CLK_NAFLL_NVDEC 567
+/** @brief NAFLL clock source for NVENC */
+#define TEGRA186_CLK_NAFLL_NVENC 568
+/** @brief NAFLL clock source for NVJPG */
+#define TEGRA186_CLK_NAFLL_NVJPG 569
+/** @brief NAFLL clock source for SCE */
+#define TEGRA186_CLK_NAFLL_SCE 570
+/** @brief NAFLL clock source for SE */
+#define TEGRA186_CLK_NAFLL_SE 571
+/** @brief NAFLL clock source for TSEC */
+#define TEGRA186_CLK_NAFLL_TSEC 572
+/** @brief NAFLL clock source for TSECB */
+#define TEGRA186_CLK_NAFLL_TSECB 573
+/** @brief NAFLL clock source for VI */
+#define TEGRA186_CLK_NAFLL_VI 574
+/** @brief NAFLL clock source for VIC */
+#define TEGRA186_CLK_NAFLL_VIC 575
+/** @brief NAFLL clock source for DISP */
+#define TEGRA186_CLK_NAFLL_DISP 576
+/** @brief NAFLL clock source for GPU */
+#define TEGRA186_CLK_NAFLL_GPU 577
+/** @brief NAFLL clock source for M-CPU cluster */
+#define TEGRA186_CLK_NAFLL_MCPU 578
+/** @brief NAFLL clock source for B-CPU cluster */
+#define TEGRA186_CLK_NAFLL_BCPU 579
+/** @brief input from Tegra's CLK_32K_IN pad */
+#define TEGRA186_CLK_CLK_32K 608
+/** @brief output of divider CLK_RST_CONTROLLER_CLK_M_DIVIDE */
+#define TEGRA186_CLK_CLK_M 609
+/** @brief output of divider PLL_REF_DIV in CLK_RST_CONTROLLER_OSC_CTRL */
+#define TEGRA186_CLK_PLL_REF 610
+/** @brief input from Tegra's XTAL_IN */
+#define TEGRA186_CLK_OSC 612
+/** @brief clock recovered from EAVB input */
+#define TEGRA186_CLK_EQOS_RX_INPUT 613
+/** @brief clock recovered from DTV input */
+#define TEGRA186_CLK_DTV_INPUT 614
+/** @brief SOR0 brick output which feeds into SOR0_CLK_SEL mux in CLK_RST_CONTROLLER_CLK_SOURCE_SOR0*/
+#define TEGRA186_CLK_SOR0_PAD_CLKOUT 615
+/** @brief SOR1 brick output which feeds into SOR1_CLK_SEL mux in CLK_RST_CONTROLLER_CLK_SOURCE_SOR1*/
+#define TEGRA186_CLK_SOR1_PAD_CLKOUT 616
+/** @brief clock recovered from I2S1 input */
+#define TEGRA186_CLK_I2S1_SYNC_INPUT 617
+/** @brief clock recovered from I2S2 input */
+#define TEGRA186_CLK_I2S2_SYNC_INPUT 618
+/** @brief clock recovered from I2S3 input */
+#define TEGRA186_CLK_I2S3_SYNC_INPUT 619
+/** @brief clock recovered from I2S4 input */
+#define TEGRA186_CLK_I2S4_SYNC_INPUT 620
+/** @brief clock recovered from I2S5 input */
+#define TEGRA186_CLK_I2S5_SYNC_INPUT 621
+/** @brief clock recovered from I2S6 input */
+#define TEGRA186_CLK_I2S6_SYNC_INPUT 622
+/** @brief clock recovered from SPDIFIN input */
+#define TEGRA186_CLK_SPDIFIN_SYNC_INPUT 623
+
+/**
+ * @brief subject to change
+ * @details maximum clock identifier value plus one.
+ */
+#define TEGRA186_CLK_CLK_MAX 624
+
+/** @} */
+
+#endif
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/tegra194-clock.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/tegra194-clock.h
new file mode 100644
index 0000000000000000000000000000000000000000..a2ff66342d69ec29f03b5a1de296a86093d63c7b
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/tegra194-clock.h
@@ -0,0 +1,321 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. */
+
+#ifndef __ABI_MACH_T194_CLOCK_H
+#define __ABI_MACH_T194_CLOCK_H
+
+#define TEGRA194_CLK_ACTMON			1
+#define TEGRA194_CLK_ADSP			2
+#define TEGRA194_CLK_ADSPNEON			3
+#define TEGRA194_CLK_AHUB			4
+#define TEGRA194_CLK_APB2APE			5
+#define TEGRA194_CLK_APE			6
+#define TEGRA194_CLK_AUD_MCLK			7
+#define TEGRA194_CLK_AXI_CBB			8
+#define TEGRA194_CLK_CAN1			9
+#define TEGRA194_CLK_CAN1_HOST			10
+#define TEGRA194_CLK_CAN2			11
+#define TEGRA194_CLK_CAN2_HOST			12
+#define TEGRA194_CLK_CEC			13
+#define TEGRA194_CLK_CLK_M			14
+#define TEGRA194_CLK_DMIC1			15
+#define TEGRA194_CLK_DMIC2			16
+#define TEGRA194_CLK_DMIC3			17
+#define TEGRA194_CLK_DMIC4			18
+#define TEGRA194_CLK_DPAUX			19
+#define TEGRA194_CLK_DPAUX1			20
+#define TEGRA194_CLK_ACLK			21
+#define TEGRA194_CLK_MSS_ENCRYPT		22
+#define TEGRA194_CLK_EQOS_RX_INPUT		23
+#define TEGRA194_CLK_IQC2			24
+#define TEGRA194_CLK_AON_APB			25
+#define TEGRA194_CLK_AON_NIC			26
+#define TEGRA194_CLK_AON_CPU_NIC		27
+#define TEGRA194_CLK_PLLA1			28
+#define TEGRA194_CLK_DSPK1			29
+#define TEGRA194_CLK_DSPK2			30
+#define TEGRA194_CLK_EMC			31
+#define TEGRA194_CLK_EQOS_AXI			32
+#define TEGRA194_CLK_EQOS_PTP_REF		33
+#define TEGRA194_CLK_EQOS_RX			34
+#define TEGRA194_CLK_EQOS_TX			35
+#define TEGRA194_CLK_EXTPERIPH1			36
+#define TEGRA194_CLK_EXTPERIPH2			37
+#define TEGRA194_CLK_EXTPERIPH3			38
+#define TEGRA194_CLK_EXTPERIPH4			39
+#define TEGRA194_CLK_FUSE			40
+#define TEGRA194_CLK_GPCCLK			41
+#define TEGRA194_CLK_GPU_PWR			42
+#define TEGRA194_CLK_HDA			43
+#define TEGRA194_CLK_HDA2CODEC_2X		44
+#define TEGRA194_CLK_HDA2HDMICODEC		45
+#define TEGRA194_CLK_HOST1X			46
+#define TEGRA194_CLK_HSIC_TRK			47
+#define TEGRA194_CLK_I2C1			48
+#define TEGRA194_CLK_I2C2			49
+#define TEGRA194_CLK_I2C3			50
+#define TEGRA194_CLK_I2C4			51
+#define TEGRA194_CLK_I2C6			52
+#define TEGRA194_CLK_I2C7			53
+#define TEGRA194_CLK_I2C8			54
+#define TEGRA194_CLK_I2C9			55
+#define TEGRA194_CLK_I2S1			56
+#define TEGRA194_CLK_I2S1_SYNC_INPUT		57
+#define TEGRA194_CLK_I2S2			58
+#define TEGRA194_CLK_I2S2_SYNC_INPUT		59
+#define TEGRA194_CLK_I2S3			60
+#define TEGRA194_CLK_I2S3_SYNC_INPUT		61
+#define TEGRA194_CLK_I2S4			62
+#define TEGRA194_CLK_I2S4_SYNC_INPUT		63
+#define TEGRA194_CLK_I2S5			64
+#define TEGRA194_CLK_I2S5_SYNC_INPUT		65
+#define TEGRA194_CLK_I2S6			66
+#define TEGRA194_CLK_I2S6_SYNC_INPUT		67
+#define TEGRA194_CLK_IQC1			68
+#define TEGRA194_CLK_ISP			69
+#define TEGRA194_CLK_KFUSE			70
+#define TEGRA194_CLK_MAUD			71
+#define TEGRA194_CLK_MIPI_CAL			72
+#define TEGRA194_CLK_MPHY_CORE_PLL_FIXED	73
+#define TEGRA194_CLK_MPHY_L0_RX_ANA		74
+#define TEGRA194_CLK_MPHY_L0_RX_LS_BIT		75
+#define TEGRA194_CLK_MPHY_L0_RX_SYMB		76
+#define TEGRA194_CLK_MPHY_L0_TX_LS_3XBIT	77
+#define TEGRA194_CLK_MPHY_L0_TX_SYMB		78
+#define TEGRA194_CLK_MPHY_L1_RX_ANA		79
+#define TEGRA194_CLK_MPHY_TX_1MHZ_REF		80
+#define TEGRA194_CLK_NVCSI			81
+#define TEGRA194_CLK_NVCSILP			82
+#define TEGRA194_CLK_NVDEC			83
+#define TEGRA194_CLK_NVDISPLAYHUB		84
+#define TEGRA194_CLK_NVDISPLAY_DISP		85
+#define TEGRA194_CLK_NVDISPLAY_P0		86
+#define TEGRA194_CLK_NVDISPLAY_P1		87
+#define TEGRA194_CLK_NVDISPLAY_P2		88
+#define TEGRA194_CLK_NVENC			89
+#define TEGRA194_CLK_NVJPG			90
+#define TEGRA194_CLK_OSC			91
+#define TEGRA194_CLK_AON_TOUCH			92
+#define TEGRA194_CLK_PLLA			93
+#define TEGRA194_CLK_PLLAON			94
+#define TEGRA194_CLK_PLLD			95
+#define TEGRA194_CLK_PLLD2			96
+#define TEGRA194_CLK_PLLD3			97
+#define TEGRA194_CLK_PLLDP			98
+#define TEGRA194_CLK_PLLD4			99
+#define TEGRA194_CLK_PLLE			100
+#define TEGRA194_CLK_PLLP			101
+#define TEGRA194_CLK_PLLP_OUT0			102
+#define TEGRA194_CLK_UTMIPLL			103
+#define TEGRA194_CLK_PLLA_OUT0			104
+#define TEGRA194_CLK_PWM1			105
+#define TEGRA194_CLK_PWM2			106
+#define TEGRA194_CLK_PWM3			107
+#define TEGRA194_CLK_PWM4			108
+#define TEGRA194_CLK_PWM5			109
+#define TEGRA194_CLK_PWM6			110
+#define TEGRA194_CLK_PWM7			111
+#define TEGRA194_CLK_PWM8			112
+#define TEGRA194_CLK_RCE_CPU_NIC		113
+#define TEGRA194_CLK_RCE_NIC			114
+#define TEGRA194_CLK_SATA			115
+#define TEGRA194_CLK_SATA_OOB			116
+#define TEGRA194_CLK_AON_I2C_SLOW		117
+#define TEGRA194_CLK_SCE_CPU_NIC		118
+#define TEGRA194_CLK_SCE_NIC			119
+#define TEGRA194_CLK_SDMMC1			120
+#define TEGRA194_CLK_UPHY_PLL3			121
+#define TEGRA194_CLK_SDMMC3			122
+#define TEGRA194_CLK_SDMMC4			123
+#define TEGRA194_CLK_SE				124
+#define TEGRA194_CLK_SOR0_OUT			125
+#define TEGRA194_CLK_SOR0_REF			126
+#define TEGRA194_CLK_SOR0_PAD_CLKOUT		127
+#define TEGRA194_CLK_SOR1_OUT			128
+#define TEGRA194_CLK_SOR1_REF			129
+#define TEGRA194_CLK_SOR1_PAD_CLKOUT		130
+#define TEGRA194_CLK_SOR_SAFE			131
+#define TEGRA194_CLK_IQC1_IN			132
+#define TEGRA194_CLK_IQC2_IN			133
+#define TEGRA194_CLK_DMIC5			134
+#define TEGRA194_CLK_SPI1			135
+#define TEGRA194_CLK_SPI2			136
+#define TEGRA194_CLK_SPI3			137
+#define TEGRA194_CLK_I2C_SLOW			138
+#define TEGRA194_CLK_SYNC_DMIC1			139
+#define TEGRA194_CLK_SYNC_DMIC2			140
+#define TEGRA194_CLK_SYNC_DMIC3			141
+#define TEGRA194_CLK_SYNC_DMIC4			142
+#define TEGRA194_CLK_SYNC_DSPK1			143
+#define TEGRA194_CLK_SYNC_DSPK2			144
+#define TEGRA194_CLK_SYNC_I2S1			145
+#define TEGRA194_CLK_SYNC_I2S2			146
+#define TEGRA194_CLK_SYNC_I2S3			147
+#define TEGRA194_CLK_SYNC_I2S4			148
+#define TEGRA194_CLK_SYNC_I2S5			149
+#define TEGRA194_CLK_SYNC_I2S6			150
+#define TEGRA194_CLK_MPHY_FORCE_LS_MODE		151
+#define TEGRA194_CLK_TACH			152
+#define TEGRA194_CLK_TSEC			153
+#define TEGRA194_CLK_TSECB			154
+#define TEGRA194_CLK_UARTA			155
+#define TEGRA194_CLK_UARTB			156
+#define TEGRA194_CLK_UARTC			157
+#define TEGRA194_CLK_UARTD			158
+#define TEGRA194_CLK_UARTE			159
+#define TEGRA194_CLK_UARTF			160
+#define TEGRA194_CLK_UARTG			161
+#define TEGRA194_CLK_UART_FST_MIPI_CAL		162
+#define TEGRA194_CLK_UFSDEV_REF			163
+#define TEGRA194_CLK_UFSHC			164
+#define TEGRA194_CLK_USB2_TRK			165
+#define TEGRA194_CLK_VI				166
+#define TEGRA194_CLK_VIC			167
+#define TEGRA194_CLK_PVA0_AXI			168
+#define TEGRA194_CLK_PVA0_VPS0			169
+#define TEGRA194_CLK_PVA0_VPS1			170
+#define TEGRA194_CLK_PVA1_AXI			171
+#define TEGRA194_CLK_PVA1_VPS0			172
+#define TEGRA194_CLK_PVA1_VPS1			173
+#define TEGRA194_CLK_DLA0_FALCON		174
+#define TEGRA194_CLK_DLA0_CORE			175
+#define TEGRA194_CLK_DLA1_FALCON		176
+#define TEGRA194_CLK_DLA1_CORE			177
+#define TEGRA194_CLK_SOR2_OUT			178
+#define TEGRA194_CLK_SOR2_REF			179
+#define TEGRA194_CLK_SOR2_PAD_CLKOUT		180
+#define TEGRA194_CLK_SOR3_OUT			181
+#define TEGRA194_CLK_SOR3_REF			182
+#define TEGRA194_CLK_SOR3_PAD_CLKOUT		183
+#define TEGRA194_CLK_NVDISPLAY_P3		184
+#define TEGRA194_CLK_DPAUX2			185
+#define TEGRA194_CLK_DPAUX3			186
+#define TEGRA194_CLK_NVDEC1			187
+#define TEGRA194_CLK_NVENC1			188
+#define TEGRA194_CLK_SE_FREE			189
+#define TEGRA194_CLK_UARTH			190
+#define TEGRA194_CLK_FUSE_SERIAL		191
+#define TEGRA194_CLK_QSPI0			192
+#define TEGRA194_CLK_QSPI1			193
+#define TEGRA194_CLK_QSPI0_PM			194
+#define TEGRA194_CLK_QSPI1_PM			195
+#define TEGRA194_CLK_VI_CONST			196
+#define TEGRA194_CLK_NAFLL_BPMP			197
+#define TEGRA194_CLK_NAFLL_SCE			198
+#define TEGRA194_CLK_NAFLL_NVDEC		199
+#define TEGRA194_CLK_NAFLL_NVJPG		200
+#define TEGRA194_CLK_NAFLL_TSEC			201
+#define TEGRA194_CLK_NAFLL_TSECB		202
+#define TEGRA194_CLK_NAFLL_VI			203
+#define TEGRA194_CLK_NAFLL_SE			204
+#define TEGRA194_CLK_NAFLL_NVENC		205
+#define TEGRA194_CLK_NAFLL_ISP			206
+#define TEGRA194_CLK_NAFLL_VIC			207
+#define TEGRA194_CLK_NAFLL_NVDISPLAYHUB		208
+#define TEGRA194_CLK_NAFLL_AXICBB		209
+#define TEGRA194_CLK_NAFLL_DLA			210
+#define TEGRA194_CLK_NAFLL_PVA_CORE		211
+#define TEGRA194_CLK_NAFLL_PVA_VPS		212
+#define TEGRA194_CLK_NAFLL_CVNAS		213
+#define TEGRA194_CLK_NAFLL_RCE			214
+#define TEGRA194_CLK_NAFLL_NVENC1		215
+#define TEGRA194_CLK_NAFLL_DLA_FALCON		216
+#define TEGRA194_CLK_NAFLL_NVDEC1		217
+#define TEGRA194_CLK_NAFLL_GPU			218
+#define TEGRA194_CLK_SDMMC_LEGACY_TM		219
+#define TEGRA194_CLK_PEX0_CORE_0		220
+#define TEGRA194_CLK_PEX0_CORE_1		221
+#define TEGRA194_CLK_PEX0_CORE_2		222
+#define TEGRA194_CLK_PEX0_CORE_3		223
+#define TEGRA194_CLK_PEX0_CORE_4		224
+#define TEGRA194_CLK_PEX1_CORE_5		225
+#define TEGRA194_CLK_PEX_REF1			226
+#define TEGRA194_CLK_PEX_REF2			227
+#define TEGRA194_CLK_CSI_A			229
+#define TEGRA194_CLK_CSI_B			230
+#define TEGRA194_CLK_CSI_C			231
+#define TEGRA194_CLK_CSI_D			232
+#define TEGRA194_CLK_CSI_E			233
+#define TEGRA194_CLK_CSI_F			234
+#define TEGRA194_CLK_CSI_G			235
+#define TEGRA194_CLK_CSI_H			236
+#define TEGRA194_CLK_PLLC4			237
+#define TEGRA194_CLK_PLLC4_OUT			238
+#define TEGRA194_CLK_PLLC4_OUT1			239
+#define TEGRA194_CLK_PLLC4_OUT2			240
+#define TEGRA194_CLK_PLLC4_MUXED		241
+#define TEGRA194_CLK_PLLC4_VCO_DIV2		242
+#define TEGRA194_CLK_CSI_A_PAD			244
+#define TEGRA194_CLK_CSI_B_PAD			245
+#define TEGRA194_CLK_CSI_C_PAD			246
+#define TEGRA194_CLK_CSI_D_PAD			247
+#define TEGRA194_CLK_CSI_E_PAD			248
+#define TEGRA194_CLK_CSI_F_PAD			249
+#define TEGRA194_CLK_CSI_G_PAD			250
+#define TEGRA194_CLK_CSI_H_PAD			251
+#define TEGRA194_CLK_PEX_SATA_USB_RX_BYP	254
+#define TEGRA194_CLK_PEX_USB_PAD_PLL0_MGMT	255
+#define TEGRA194_CLK_PEX_USB_PAD_PLL1_MGMT	256
+#define TEGRA194_CLK_PEX_USB_PAD_PLL2_MGMT	257
+#define TEGRA194_CLK_PEX_USB_PAD_PLL3_MGMT	258
+#define TEGRA194_CLK_XUSB_CORE_DEV		265
+#define TEGRA194_CLK_XUSB_CORE_MUX		266
+#define TEGRA194_CLK_XUSB_CORE_HOST		267
+#define TEGRA194_CLK_XUSB_CORE_SS		268
+#define TEGRA194_CLK_XUSB_FALCON		269
+#define TEGRA194_CLK_XUSB_FALCON_HOST		270
+#define TEGRA194_CLK_XUSB_FALCON_SS		271
+#define TEGRA194_CLK_XUSB_FS			272
+#define TEGRA194_CLK_XUSB_FS_HOST		273
+#define TEGRA194_CLK_XUSB_FS_DEV		274
+#define TEGRA194_CLK_XUSB_SS			275
+#define TEGRA194_CLK_XUSB_SS_DEV		276
+#define TEGRA194_CLK_XUSB_SS_SUPERSPEED		277
+#define TEGRA194_CLK_PLLDISPHUB			278
+#define TEGRA194_CLK_PLLDISPHUB_DIV		279
+#define TEGRA194_CLK_NAFLL_CLUSTER0		280
+#define TEGRA194_CLK_NAFLL_CLUSTER1		281
+#define TEGRA194_CLK_NAFLL_CLUSTER2		282
+#define TEGRA194_CLK_NAFLL_CLUSTER3		283
+#define TEGRA194_CLK_CAN1_CORE			284
+#define TEGRA194_CLK_CAN2_CORE			285
+#define TEGRA194_CLK_PLLA1_OUT1			286
+#define TEGRA194_CLK_PLLREFE_VCOOUT		288
+#define TEGRA194_CLK_CLK_32K			289
+#define TEGRA194_CLK_SPDIFIN_SYNC_INPUT		290
+#define TEGRA194_CLK_UTMIPLL_CLKOUT48		291
+#define TEGRA194_CLK_UTMIPLL_CLKOUT480		292
+#define TEGRA194_CLK_CVNAS			293
+#define TEGRA194_CLK_PLLNVCSI			294
+#define TEGRA194_CLK_PVA0_CPU_AXI		295
+#define TEGRA194_CLK_PVA1_CPU_AXI		296
+#define TEGRA194_CLK_PVA0_VPS			297
+#define TEGRA194_CLK_PVA1_VPS			298
+#define TEGRA194_CLK_DLA0_FALCON_MUX		299
+#define TEGRA194_CLK_DLA1_FALCON_MUX		300
+#define TEGRA194_CLK_DLA0_CORE_MUX		301
+#define TEGRA194_CLK_DLA1_CORE_MUX		302
+#define TEGRA194_CLK_UTMIPLL_HPS		304
+#define TEGRA194_CLK_I2C5			305
+#define TEGRA194_CLK_I2C10			306
+#define TEGRA194_CLK_BPMP_CPU_NIC		307
+#define TEGRA194_CLK_BPMP_APB			308
+#define TEGRA194_CLK_TSC			309
+#define TEGRA194_CLK_EMCSA			310
+#define TEGRA194_CLK_EMCSB			311
+#define TEGRA194_CLK_EMCSC			312
+#define TEGRA194_CLK_EMCSD			313
+#define TEGRA194_CLK_PLLC			314
+#define TEGRA194_CLK_PLLC2			315
+#define TEGRA194_CLK_PLLC3			316
+#define TEGRA194_CLK_TSC_REF			317
+#define TEGRA194_CLK_FUSE_BURN			318
+#define TEGRA194_CLK_PEX0_CORE_0M		319
+#define TEGRA194_CLK_PEX0_CORE_1M		320
+#define TEGRA194_CLK_PEX0_CORE_2M		321
+#define TEGRA194_CLK_PEX0_CORE_3M		322
+#define TEGRA194_CLK_PEX0_CORE_4M		323
+#define TEGRA194_CLK_PEX1_CORE_5M		324
+#define TEGRA194_CLK_PLLE_HPS			326
+
+#endif
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/tegra20-car.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/tegra20-car.h
new file mode 100644
index 0000000000000000000000000000000000000000..b21a0eb329214b055df6dddc8b16aec748abb6d7
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/tegra20-car.h
@@ -0,0 +1,159 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * This header provides constants for binding nvidia,tegra20-car.
+ *
+ * The first 96 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB
+ * registers. These IDs often match those in the CAR's RST_DEVICES registers,
+ * but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In
+ * this case, those clocks are assigned IDs above 95 in order to highlight
+ * this issue. Implementations that interpret these clock IDs as bit values
+ * within the CLK_OUT_ENB or RST_DEVICES registers should be careful to
+ * explicitly handle these special cases.
+ *
+ * The balance of the clocks controlled by the CAR are assigned IDs of 96 and
+ * above.
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_TEGRA20_CAR_H
+#define _DT_BINDINGS_CLOCK_TEGRA20_CAR_H
+
+#define TEGRA20_CLK_CPU 0
+/* 1 */
+/* 2 */
+#define TEGRA20_CLK_AC97 3
+#define TEGRA20_CLK_RTC 4
+#define TEGRA20_CLK_TIMER 5
+#define TEGRA20_CLK_UARTA 6
+/* 7 (register bit affects uart2 and vfir) */
+#define TEGRA20_CLK_GPIO 8
+#define TEGRA20_CLK_SDMMC2 9
+/* 10 (register bit affects spdif_in and spdif_out) */
+#define TEGRA20_CLK_I2S1 11
+#define TEGRA20_CLK_I2C1 12
+#define TEGRA20_CLK_NDFLASH 13
+#define TEGRA20_CLK_SDMMC1 14
+#define TEGRA20_CLK_SDMMC4 15
+#define TEGRA20_CLK_TWC 16
+#define TEGRA20_CLK_PWM 17
+#define TEGRA20_CLK_I2S2 18
+#define TEGRA20_CLK_EPP 19
+/* 20 (register bit affects vi and vi_sensor) */
+#define TEGRA20_CLK_GR2D 21
+#define TEGRA20_CLK_USBD 22
+#define TEGRA20_CLK_ISP 23
+#define TEGRA20_CLK_GR3D 24
+#define TEGRA20_CLK_IDE 25
+#define TEGRA20_CLK_DISP2 26
+#define TEGRA20_CLK_DISP1 27
+#define TEGRA20_CLK_HOST1X 28
+#define TEGRA20_CLK_VCP 29
+/* 30 */
+#define TEGRA20_CLK_CACHE2 31
+
+#define TEGRA20_CLK_MC 32
+#define TEGRA20_CLK_AHBDMA 33
+#define TEGRA20_CLK_APBDMA 34
+/* 35 */
+#define TEGRA20_CLK_KBC 36
+#define TEGRA20_CLK_STAT_MON 37
+#define TEGRA20_CLK_PMC 38
+#define TEGRA20_CLK_FUSE 39
+#define TEGRA20_CLK_KFUSE 40
+#define TEGRA20_CLK_SBC1 41
+#define TEGRA20_CLK_NOR 42
+#define TEGRA20_CLK_SPI 43
+#define TEGRA20_CLK_SBC2 44
+#define TEGRA20_CLK_XIO 45
+#define TEGRA20_CLK_SBC3 46
+#define TEGRA20_CLK_DVC 47
+#define TEGRA20_CLK_DSI 48
+/* 49 (register bit affects tvo and cve) */
+#define TEGRA20_CLK_MIPI 50
+#define TEGRA20_CLK_HDMI 51
+#define TEGRA20_CLK_CSI 52
+#define TEGRA20_CLK_TVDAC 53
+#define TEGRA20_CLK_I2C2 54
+#define TEGRA20_CLK_UARTC 55
+/* 56 */
+#define TEGRA20_CLK_EMC 57
+#define TEGRA20_CLK_USB2 58
+#define TEGRA20_CLK_USB3 59
+#define TEGRA20_CLK_MPE 60
+#define TEGRA20_CLK_VDE 61
+#define TEGRA20_CLK_BSEA 62
+#define TEGRA20_CLK_BSEV 63
+
+#define TEGRA20_CLK_SPEEDO 64
+#define TEGRA20_CLK_UARTD 65
+#define TEGRA20_CLK_UARTE 66
+#define TEGRA20_CLK_I2C3 67
+#define TEGRA20_CLK_SBC4 68
+#define TEGRA20_CLK_SDMMC3 69
+#define TEGRA20_CLK_PEX 70
+#define TEGRA20_CLK_OWR 71
+#define TEGRA20_CLK_AFI 72
+#define TEGRA20_CLK_CSITE 73
+/* 74 */
+#define TEGRA20_CLK_AVPUCQ 75
+#define TEGRA20_CLK_LA 76
+/* 77 */
+/* 78 */
+/* 79 */
+/* 80 */
+/* 81 */
+/* 82 */
+/* 83 */
+#define TEGRA20_CLK_IRAMA 84
+#define TEGRA20_CLK_IRAMB 85
+#define TEGRA20_CLK_IRAMC 86
+#define TEGRA20_CLK_IRAMD 87
+#define TEGRA20_CLK_CRAM2 88
+#define TEGRA20_CLK_AUDIO_2X 89 /* a/k/a audio_2x_sync_clk */
+#define TEGRA20_CLK_CLK_D 90
+/* 91 */
+#define TEGRA20_CLK_CSUS 92
+#define TEGRA20_CLK_CDEV2 93
+#define TEGRA20_CLK_CDEV1 94
+/* 95 */
+
+#define TEGRA20_CLK_UARTB 96
+#define TEGRA20_CLK_VFIR 97
+#define TEGRA20_CLK_SPDIF_IN 98
+#define TEGRA20_CLK_SPDIF_OUT 99
+#define TEGRA20_CLK_VI 100
+#define TEGRA20_CLK_VI_SENSOR 101
+#define TEGRA20_CLK_TVO 102
+#define TEGRA20_CLK_CVE 103
+#define TEGRA20_CLK_OSC 104
+#define TEGRA20_CLK_CLK_32K 105 /* a/k/a clk_s */
+#define TEGRA20_CLK_CLK_M 106
+#define TEGRA20_CLK_SCLK 107
+#define TEGRA20_CLK_CCLK 108
+#define TEGRA20_CLK_HCLK 109
+#define TEGRA20_CLK_PCLK 110
+#define TEGRA20_CLK_BLINK 111
+#define TEGRA20_CLK_PLL_A 112
+#define TEGRA20_CLK_PLL_A_OUT0 113
+#define TEGRA20_CLK_PLL_C 114
+#define TEGRA20_CLK_PLL_C_OUT1 115
+#define TEGRA20_CLK_PLL_D 116
+#define TEGRA20_CLK_PLL_D_OUT0 117
+#define TEGRA20_CLK_PLL_E 118
+#define TEGRA20_CLK_PLL_M 119
+#define TEGRA20_CLK_PLL_M_OUT1 120
+#define TEGRA20_CLK_PLL_P 121
+#define TEGRA20_CLK_PLL_P_OUT1 122
+#define TEGRA20_CLK_PLL_P_OUT2 123
+#define TEGRA20_CLK_PLL_P_OUT3 124
+#define TEGRA20_CLK_PLL_P_OUT4 125
+#define TEGRA20_CLK_PLL_S 126
+#define TEGRA20_CLK_PLL_U 127
+
+#define TEGRA20_CLK_PLL_X 128
+#define TEGRA20_CLK_COP 129 /* a/k/a avp */
+#define TEGRA20_CLK_AUDIO 130 /* a/k/a audio_sync_clk */
+#define TEGRA20_CLK_PLL_REF 131
+#define TEGRA20_CLK_TWD 132
+#define TEGRA20_CLK_CLK_MAX 133
+
+#endif	/* _DT_BINDINGS_CLOCK_TEGRA20_CAR_H */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/tegra210-car.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/tegra210-car.h
new file mode 100644
index 0000000000000000000000000000000000000000..6b77e721f6b1f1ebb9406e3294f704f4195a57dd
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/tegra210-car.h
@@ -0,0 +1,412 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * This header provides constants for binding nvidia,tegra210-car.
+ *
+ * The first 224 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB
+ * registers. These IDs often match those in the CAR's RST_DEVICES registers,
+ * but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In
+ * this case, those clocks are assigned IDs above 224 in order to highlight
+ * this issue. Implementations that interpret these clock IDs as bit values
+ * within the CLK_OUT_ENB or RST_DEVICES registers should be careful to
+ * explicitly handle these special cases.
+ *
+ * The balance of the clocks controlled by the CAR are assigned IDs of 224 and
+ * above.
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_TEGRA210_CAR_H
+#define _DT_BINDINGS_CLOCK_TEGRA210_CAR_H
+
+/* 0 */
+/* 1 */
+/* 2 */
+#define TEGRA210_CLK_ISPB 3
+#define TEGRA210_CLK_RTC 4
+#define TEGRA210_CLK_TIMER 5
+#define TEGRA210_CLK_UARTA 6
+/* 7 (register bit affects uartb and vfir) */
+#define TEGRA210_CLK_GPIO 8
+#define TEGRA210_CLK_SDMMC2 9
+/* 10 (register bit affects spdif_in and spdif_out) */
+#define TEGRA210_CLK_I2S1 11
+#define TEGRA210_CLK_I2C1 12
+/* 13 */
+#define TEGRA210_CLK_SDMMC1 14
+#define TEGRA210_CLK_SDMMC4 15
+/* 16 */
+#define TEGRA210_CLK_PWM 17
+#define TEGRA210_CLK_I2S2 18
+/* 19 */
+/* 20 (register bit affects vi and vi_sensor) */
+/* 21 */
+#define TEGRA210_CLK_USBD 22
+#define TEGRA210_CLK_ISPA 23
+/* 24 */
+/* 25 */
+#define TEGRA210_CLK_DISP2 26
+#define TEGRA210_CLK_DISP1 27
+#define TEGRA210_CLK_HOST1X 28
+/* 29 */
+#define TEGRA210_CLK_I2S0 30
+/* 31 */
+
+#define TEGRA210_CLK_MC 32
+#define TEGRA210_CLK_AHBDMA 33
+#define TEGRA210_CLK_APBDMA 34
+/* 35 */
+/* 36 */
+/* 37 */
+#define TEGRA210_CLK_PMC 38
+/* 39 (register bit affects fuse and fuse_burn) */
+#define TEGRA210_CLK_KFUSE 40
+#define TEGRA210_CLK_SBC1 41
+/* 42 */
+/* 43 */
+#define TEGRA210_CLK_SBC2 44
+/* 45 */
+#define TEGRA210_CLK_SBC3 46
+#define TEGRA210_CLK_I2C5 47
+#define TEGRA210_CLK_DSIA 48
+/* 49 */
+/* 50 */
+/* 51 */
+#define TEGRA210_CLK_CSI 52
+/* 53 */
+#define TEGRA210_CLK_I2C2 54
+#define TEGRA210_CLK_UARTC 55
+#define TEGRA210_CLK_MIPI_CAL 56
+#define TEGRA210_CLK_EMC 57
+#define TEGRA210_CLK_USB2 58
+/* 59 */
+/* 60 */
+/* 61 */
+/* 62 */
+#define TEGRA210_CLK_BSEV 63
+
+/* 64 */
+#define TEGRA210_CLK_UARTD 65
+/* 66 */
+#define TEGRA210_CLK_I2C3 67
+#define TEGRA210_CLK_SBC4 68
+#define TEGRA210_CLK_SDMMC3 69
+#define TEGRA210_CLK_PCIE 70
+#define TEGRA210_CLK_OWR 71
+#define TEGRA210_CLK_AFI 72
+#define TEGRA210_CLK_CSITE 73
+/* 74 */
+/* 75 */
+#define TEGRA210_CLK_LA 76
+/* 77 */
+#define TEGRA210_CLK_SOC_THERM 78
+#define TEGRA210_CLK_DTV 79
+/* 80 */
+#define TEGRA210_CLK_I2CSLOW 81
+#define TEGRA210_CLK_DSIB 82
+#define TEGRA210_CLK_TSEC 83
+/* 84 */
+/* 85 */
+/* 86 */
+/* 87 */
+/* 88 */
+#define TEGRA210_CLK_XUSB_HOST 89
+/* 90 */
+/* 91 */
+#define TEGRA210_CLK_CSUS 92
+/* 93 */
+/* 94 */
+/* 95 (bit affects xusb_dev and xusb_dev_src) */
+
+/* 96 */
+/* 97 */
+/* 98 */
+#define TEGRA210_CLK_MSELECT 99
+#define TEGRA210_CLK_TSENSOR 100
+#define TEGRA210_CLK_I2S3 101
+#define TEGRA210_CLK_I2S4 102
+#define TEGRA210_CLK_I2C4 103
+/* 104 */
+/* 105 */
+#define TEGRA210_CLK_D_AUDIO 106
+#define TEGRA210_CLK_APB2APE 107
+/* 108 */
+/* 109 */
+/* 110 */
+#define TEGRA210_CLK_HDA2CODEC_2X 111
+/* 112 */
+/* 113 */
+/* 114 */
+/* 115 */
+/* 116 */
+/* 117 */
+#define TEGRA210_CLK_SPDIF_2X 118
+#define TEGRA210_CLK_ACTMON 119
+#define TEGRA210_CLK_EXTERN1 120
+#define TEGRA210_CLK_EXTERN2 121
+#define TEGRA210_CLK_EXTERN3 122
+#define TEGRA210_CLK_SATA_OOB 123
+#define TEGRA210_CLK_SATA 124
+#define TEGRA210_CLK_HDA 125
+/* 126 */
+/* 127 */
+
+#define TEGRA210_CLK_HDA2HDMI 128
+/* 129 */
+/* 130 */
+/* 131 */
+/* 132 */
+/* 133 */
+/* 134 */
+/* 135 */
+#define TEGRA210_CLK_CEC 136
+/* 137 */
+/* 138 */
+/* 139 */
+/* 140 */
+/* 141 */
+/* 142 */
+/* (bit affects xusb_falcon_src, xusb_fs_src, xusb_host_src and xusb_ss_src) */
+#define TEGRA210_CLK_XUSB_GATE 143
+#define TEGRA210_CLK_CILAB 144
+#define TEGRA210_CLK_CILCD 145
+#define TEGRA210_CLK_CILE 146
+#define TEGRA210_CLK_DSIALP 147
+#define TEGRA210_CLK_DSIBLP 148
+#define TEGRA210_CLK_ENTROPY 149
+/* 150 */
+/* 151 */
+#define TEGRA210_CLK_DP2 152
+/* 153 */
+/* 154 */
+/* 155 (bit affects dfll_ref and dfll_soc) */
+#define TEGRA210_CLK_XUSB_SS 156
+/* 157 */
+/* 158 */
+/* 159 */
+
+/* 160 */
+#define TEGRA210_CLK_DMIC1 161
+#define TEGRA210_CLK_DMIC2 162
+/* 163 */
+/* 164 */
+/* 165 */
+#define TEGRA210_CLK_I2C6 166
+/* 167 */
+/* 168 */
+/* 169 */
+/* 170 */
+#define TEGRA210_CLK_VIM2_CLK 171
+/* 172 */
+#define TEGRA210_CLK_MIPIBIF 173
+/* 174 */
+/* 175 */
+/* 176 */
+#define TEGRA210_CLK_CLK72MHZ 177
+#define TEGRA210_CLK_VIC03 178
+/* 179 */
+/* 180 */
+#define TEGRA210_CLK_DPAUX 181
+#define TEGRA210_CLK_SOR0 182
+#define TEGRA210_CLK_SOR1 183
+#define TEGRA210_CLK_GPU 184
+#define TEGRA210_CLK_DBGAPB 185
+/* 186 */
+#define TEGRA210_CLK_PLL_P_OUT_ADSP 187
+/* 188 ((bit affects pll_a_out_adsp and pll_a_out0_out_adsp)*/
+#define TEGRA210_CLK_PLL_G_REF 189
+/* 190 */
+/* 191 */
+
+/* 192 */
+#define TEGRA210_CLK_SDMMC_LEGACY 193
+#define TEGRA210_CLK_NVDEC 194
+#define TEGRA210_CLK_NVJPG 195
+/* 196 */
+#define TEGRA210_CLK_DMIC3 197
+#define TEGRA210_CLK_APE 198
+#define TEGRA210_CLK_ADSP 199
+/* 200 */
+/* 201 */
+#define TEGRA210_CLK_MAUD 202
+/* 203 */
+/* 204 */
+/* 205 */
+#define TEGRA210_CLK_TSECB 206
+#define TEGRA210_CLK_DPAUX1 207
+#define TEGRA210_CLK_VI_I2C 208
+#define TEGRA210_CLK_HSIC_TRK 209
+#define TEGRA210_CLK_USB2_TRK 210
+#define TEGRA210_CLK_QSPI 211
+#define TEGRA210_CLK_UARTAPE 212
+/* 213 */
+/* 214 */
+/* 215 */
+/* 216 */
+/* 217 */
+#define TEGRA210_CLK_ADSP_NEON 218
+#define TEGRA210_CLK_NVENC 219
+#define TEGRA210_CLK_IQC2 220
+#define TEGRA210_CLK_IQC1 221
+#define TEGRA210_CLK_SOR_SAFE 222
+#define TEGRA210_CLK_PLL_P_OUT_CPU 223
+
+
+#define TEGRA210_CLK_UARTB 224
+#define TEGRA210_CLK_VFIR 225
+#define TEGRA210_CLK_SPDIF_IN 226
+#define TEGRA210_CLK_SPDIF_OUT 227
+#define TEGRA210_CLK_VI 228
+#define TEGRA210_CLK_VI_SENSOR 229
+#define TEGRA210_CLK_FUSE 230
+#define TEGRA210_CLK_FUSE_BURN 231
+#define TEGRA210_CLK_CLK_32K 232
+#define TEGRA210_CLK_CLK_M 233
+#define TEGRA210_CLK_CLK_M_DIV2 234
+#define TEGRA210_CLK_CLK_M_DIV4 235
+#define TEGRA210_CLK_PLL_REF 236
+#define TEGRA210_CLK_PLL_C 237
+#define TEGRA210_CLK_PLL_C_OUT1 238
+#define TEGRA210_CLK_PLL_C2 239
+#define TEGRA210_CLK_PLL_C3 240
+#define TEGRA210_CLK_PLL_M 241
+#define TEGRA210_CLK_PLL_M_OUT1 242
+#define TEGRA210_CLK_PLL_P 243
+#define TEGRA210_CLK_PLL_P_OUT1 244
+#define TEGRA210_CLK_PLL_P_OUT2 245
+#define TEGRA210_CLK_PLL_P_OUT3 246
+#define TEGRA210_CLK_PLL_P_OUT4 247
+#define TEGRA210_CLK_PLL_A 248
+#define TEGRA210_CLK_PLL_A_OUT0 249
+#define TEGRA210_CLK_PLL_D 250
+#define TEGRA210_CLK_PLL_D_OUT0 251
+#define TEGRA210_CLK_PLL_D2 252
+#define TEGRA210_CLK_PLL_D2_OUT0 253
+#define TEGRA210_CLK_PLL_U 254
+#define TEGRA210_CLK_PLL_U_480M 255
+
+#define TEGRA210_CLK_PLL_U_60M 256
+#define TEGRA210_CLK_PLL_U_48M 257
+/* 258 */
+#define TEGRA210_CLK_PLL_X 259
+#define TEGRA210_CLK_PLL_X_OUT0 260
+#define TEGRA210_CLK_PLL_RE_VCO 261
+#define TEGRA210_CLK_PLL_RE_OUT 262
+#define TEGRA210_CLK_PLL_E 263
+#define TEGRA210_CLK_SPDIF_IN_SYNC 264
+#define TEGRA210_CLK_I2S0_SYNC 265
+#define TEGRA210_CLK_I2S1_SYNC 266
+#define TEGRA210_CLK_I2S2_SYNC 267
+#define TEGRA210_CLK_I2S3_SYNC 268
+#define TEGRA210_CLK_I2S4_SYNC 269
+#define TEGRA210_CLK_VIMCLK_SYNC 270
+#define TEGRA210_CLK_AUDIO0 271
+#define TEGRA210_CLK_AUDIO1 272
+#define TEGRA210_CLK_AUDIO2 273
+#define TEGRA210_CLK_AUDIO3 274
+#define TEGRA210_CLK_AUDIO4 275
+#define TEGRA210_CLK_SPDIF 276
+#define TEGRA210_CLK_CLK_OUT_1 277
+#define TEGRA210_CLK_CLK_OUT_2 278
+#define TEGRA210_CLK_CLK_OUT_3 279
+#define TEGRA210_CLK_BLINK 280
+/* 281 */
+#define TEGRA210_CLK_SOR1_SRC 282
+#define TEGRA210_CLK_SOR1_OUT 282
+/* 283 */
+#define TEGRA210_CLK_XUSB_HOST_SRC 284
+#define TEGRA210_CLK_XUSB_FALCON_SRC 285
+#define TEGRA210_CLK_XUSB_FS_SRC 286
+#define TEGRA210_CLK_XUSB_SS_SRC 287
+
+#define TEGRA210_CLK_XUSB_DEV_SRC 288
+#define TEGRA210_CLK_XUSB_DEV 289
+#define TEGRA210_CLK_XUSB_HS_SRC 290
+#define TEGRA210_CLK_SCLK 291
+#define TEGRA210_CLK_HCLK 292
+#define TEGRA210_CLK_PCLK 293
+#define TEGRA210_CLK_CCLK_G 294
+#define TEGRA210_CLK_CCLK_LP 295
+#define TEGRA210_CLK_DFLL_REF 296
+#define TEGRA210_CLK_DFLL_SOC 297
+#define TEGRA210_CLK_VI_SENSOR2 298
+#define TEGRA210_CLK_PLL_P_OUT5 299
+#define TEGRA210_CLK_CML0 300
+#define TEGRA210_CLK_CML1 301
+#define TEGRA210_CLK_PLL_C4 302
+#define TEGRA210_CLK_PLL_DP 303
+#define TEGRA210_CLK_PLL_E_MUX 304
+#define TEGRA210_CLK_PLL_MB 305
+#define TEGRA210_CLK_PLL_A1 306
+#define TEGRA210_CLK_PLL_D_DSI_OUT 307
+#define TEGRA210_CLK_PLL_C4_OUT0 308
+#define TEGRA210_CLK_PLL_C4_OUT1 309
+#define TEGRA210_CLK_PLL_C4_OUT2 310
+#define TEGRA210_CLK_PLL_C4_OUT3 311
+#define TEGRA210_CLK_PLL_U_OUT 312
+#define TEGRA210_CLK_PLL_U_OUT1 313
+#define TEGRA210_CLK_PLL_U_OUT2 314
+#define TEGRA210_CLK_USB2_HSIC_TRK 315
+#define TEGRA210_CLK_PLL_P_OUT_HSIO 316
+#define TEGRA210_CLK_PLL_P_OUT_XUSB 317
+#define TEGRA210_CLK_XUSB_SSP_SRC 318
+#define TEGRA210_CLK_PLL_RE_OUT1 319
+/* 320 */
+/* 321 */
+#define TEGRA210_CLK_ISP 322
+#define TEGRA210_CLK_PLL_A_OUT_ADSP 323
+#define TEGRA210_CLK_PLL_A_OUT0_OUT_ADSP 324
+/* 325 */
+/* 326 */
+/* 327 */
+/* 328 */
+/* 329 */
+/* 330 */
+/* 331 */
+/* 332 */
+/* 333 */
+/* 334 */
+/* 335 */
+/* 336 */
+/* 337 */
+/* 338 */
+/* 339 */
+/* 340 */
+/* 341 */
+/* 342 */
+/* 343 */
+/* 344 */
+/* 345 */
+/* 346 */
+/* 347 */
+/* 348 */
+/* 349 */
+
+#define TEGRA210_CLK_AUDIO0_MUX 350
+#define TEGRA210_CLK_AUDIO1_MUX 351
+#define TEGRA210_CLK_AUDIO2_MUX 352
+#define TEGRA210_CLK_AUDIO3_MUX 353
+#define TEGRA210_CLK_AUDIO4_MUX 354
+#define TEGRA210_CLK_SPDIF_MUX 355
+#define TEGRA210_CLK_CLK_OUT_1_MUX 356
+#define TEGRA210_CLK_CLK_OUT_2_MUX 357
+#define TEGRA210_CLK_CLK_OUT_3_MUX 358
+#define TEGRA210_CLK_DSIA_MUX 359
+#define TEGRA210_CLK_DSIB_MUX 360
+#define TEGRA210_CLK_SOR0_LVDS 361
+#define TEGRA210_CLK_XUSB_SS_DIV2 362
+
+#define TEGRA210_CLK_PLL_M_UD 363
+#define TEGRA210_CLK_PLL_C_UD 364
+#define TEGRA210_CLK_SCLK_MUX 365
+
+#define TEGRA210_CLK_ACLK 370
+
+#define TEGRA210_CLK_DMIC1_SYNC_CLK 388
+#define TEGRA210_CLK_DMIC1_SYNC_CLK_MUX 389
+#define TEGRA210_CLK_DMIC2_SYNC_CLK 390
+#define TEGRA210_CLK_DMIC2_SYNC_CLK_MUX 391
+#define TEGRA210_CLK_DMIC3_SYNC_CLK 392
+#define TEGRA210_CLK_DMIC3_SYNC_CLK_MUX 393
+
+#define TEGRA210_CLK_CLK_MAX 394
+
+#endif	/* _DT_BINDINGS_CLOCK_TEGRA210_CAR_H */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/tegra30-car.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/tegra30-car.h
new file mode 100644
index 0000000000000000000000000000000000000000..3c90f1535551a43dd7b67afe9de4a135bd062fee
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/tegra30-car.h
@@ -0,0 +1,274 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * This header provides constants for binding nvidia,tegra30-car.
+ *
+ * The first 130 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB
+ * registers. These IDs often match those in the CAR's RST_DEVICES registers,
+ * but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In
+ * this case, those clocks are assigned IDs above 160 in order to highlight
+ * this issue. Implementations that interpret these clock IDs as bit values
+ * within the CLK_OUT_ENB or RST_DEVICES registers should be careful to
+ * explicitly handle these special cases.
+ *
+ * The balance of the clocks controlled by the CAR are assigned IDs of 160 and
+ * above.
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_TEGRA30_CAR_H
+#define _DT_BINDINGS_CLOCK_TEGRA30_CAR_H
+
+#define TEGRA30_CLK_CPU 0
+/* 1 */
+/* 2 */
+/* 3 */
+#define TEGRA30_CLK_RTC 4
+#define TEGRA30_CLK_TIMER 5
+#define TEGRA30_CLK_UARTA 6
+/* 7 (register bit affects uartb and vfir) */
+#define TEGRA30_CLK_GPIO 8
+#define TEGRA30_CLK_SDMMC2 9
+/* 10 (register bit affects spdif_in and spdif_out) */
+#define TEGRA30_CLK_I2S1 11
+#define TEGRA30_CLK_I2C1 12
+#define TEGRA30_CLK_NDFLASH 13
+#define TEGRA30_CLK_SDMMC1 14
+#define TEGRA30_CLK_SDMMC4 15
+/* 16 */
+#define TEGRA30_CLK_PWM 17
+#define TEGRA30_CLK_I2S2 18
+#define TEGRA30_CLK_EPP 19
+/* 20 (register bit affects vi and vi_sensor) */
+#define TEGRA30_CLK_GR2D 21
+#define TEGRA30_CLK_USBD 22
+#define TEGRA30_CLK_ISP 23
+#define TEGRA30_CLK_GR3D 24
+/* 25 */
+#define TEGRA30_CLK_DISP2 26
+#define TEGRA30_CLK_DISP1 27
+#define TEGRA30_CLK_HOST1X 28
+#define TEGRA30_CLK_VCP 29
+#define TEGRA30_CLK_I2S0 30
+#define TEGRA30_CLK_COP_CACHE 31
+
+#define TEGRA30_CLK_MC 32
+#define TEGRA30_CLK_AHBDMA 33
+#define TEGRA30_CLK_APBDMA 34
+/* 35 */
+#define TEGRA30_CLK_KBC 36
+#define TEGRA30_CLK_STATMON 37
+#define TEGRA30_CLK_PMC 38
+/* 39 (register bit affects fuse and fuse_burn) */
+#define TEGRA30_CLK_KFUSE 40
+#define TEGRA30_CLK_SBC1 41
+#define TEGRA30_CLK_NOR 42
+/* 43 */
+#define TEGRA30_CLK_SBC2 44
+/* 45 */
+#define TEGRA30_CLK_SBC3 46
+#define TEGRA30_CLK_I2C5 47
+#define TEGRA30_CLK_DSIA 48
+/* 49 (register bit affects cve and tvo) */
+#define TEGRA30_CLK_MIPI 50
+#define TEGRA30_CLK_HDMI 51
+#define TEGRA30_CLK_CSI 52
+#define TEGRA30_CLK_TVDAC 53
+#define TEGRA30_CLK_I2C2 54
+#define TEGRA30_CLK_UARTC 55
+/* 56 */
+#define TEGRA30_CLK_EMC 57
+#define TEGRA30_CLK_USB2 58
+#define TEGRA30_CLK_USB3 59
+#define TEGRA30_CLK_MPE 60
+#define TEGRA30_CLK_VDE 61
+#define TEGRA30_CLK_BSEA 62
+#define TEGRA30_CLK_BSEV 63
+
+#define TEGRA30_CLK_SPEEDO 64
+#define TEGRA30_CLK_UARTD 65
+#define TEGRA30_CLK_UARTE 66
+#define TEGRA30_CLK_I2C3 67
+#define TEGRA30_CLK_SBC4 68
+#define TEGRA30_CLK_SDMMC3 69
+#define TEGRA30_CLK_PCIE 70
+#define TEGRA30_CLK_OWR 71
+#define TEGRA30_CLK_AFI 72
+#define TEGRA30_CLK_CSITE 73
+/* 74 */
+#define TEGRA30_CLK_AVPUCQ 75
+#define TEGRA30_CLK_LA 76
+/* 77 */
+/* 78 */
+#define TEGRA30_CLK_DTV 79
+#define TEGRA30_CLK_NDSPEED 80
+#define TEGRA30_CLK_I2CSLOW 81
+#define TEGRA30_CLK_DSIB 82
+/* 83 */
+#define TEGRA30_CLK_IRAMA 84
+#define TEGRA30_CLK_IRAMB 85
+#define TEGRA30_CLK_IRAMC 86
+#define TEGRA30_CLK_IRAMD 87
+#define TEGRA30_CLK_CRAM2 88
+/* 89 */
+#define TEGRA30_CLK_AUDIO_2X 90 /* a/k/a audio_2x_sync_clk */
+/* 91 */
+#define TEGRA30_CLK_CSUS 92
+#define TEGRA30_CLK_CDEV2 93
+#define TEGRA30_CLK_CDEV1 94
+/* 95 */
+
+#define TEGRA30_CLK_CPU_G 96
+#define TEGRA30_CLK_CPU_LP 97
+#define TEGRA30_CLK_GR3D2 98
+#define TEGRA30_CLK_MSELECT 99
+#define TEGRA30_CLK_TSENSOR 100
+#define TEGRA30_CLK_I2S3 101
+#define TEGRA30_CLK_I2S4 102
+#define TEGRA30_CLK_I2C4 103
+#define TEGRA30_CLK_SBC5 104
+#define TEGRA30_CLK_SBC6 105
+#define TEGRA30_CLK_D_AUDIO 106
+#define TEGRA30_CLK_APBIF 107
+#define TEGRA30_CLK_DAM0 108
+#define TEGRA30_CLK_DAM1 109
+#define TEGRA30_CLK_DAM2 110
+#define TEGRA30_CLK_HDA2CODEC_2X 111
+#define TEGRA30_CLK_ATOMICS 112
+#define TEGRA30_CLK_AUDIO0_2X 113
+#define TEGRA30_CLK_AUDIO1_2X 114
+#define TEGRA30_CLK_AUDIO2_2X 115
+#define TEGRA30_CLK_AUDIO3_2X 116
+#define TEGRA30_CLK_AUDIO4_2X 117
+#define TEGRA30_CLK_SPDIF_2X 118
+#define TEGRA30_CLK_ACTMON 119
+#define TEGRA30_CLK_EXTERN1 120
+#define TEGRA30_CLK_EXTERN2 121
+#define TEGRA30_CLK_EXTERN3 122
+#define TEGRA30_CLK_SATA_OOB 123
+#define TEGRA30_CLK_SATA 124
+#define TEGRA30_CLK_HDA 125
+/* 126 */
+#define TEGRA30_CLK_SE 127
+
+#define TEGRA30_CLK_HDA2HDMI 128
+#define TEGRA30_CLK_SATA_COLD 129
+/* 130 */
+/* 131 */
+/* 132 */
+/* 133 */
+/* 134 */
+/* 135 */
+#define TEGRA30_CLK_CEC 136
+/* 137 */
+/* 138 */
+/* 139 */
+/* 140 */
+/* 141 */
+/* 142 */
+/* 143 */
+/* 144 */
+/* 145 */
+/* 146 */
+/* 147 */
+/* 148 */
+/* 149 */
+/* 150 */
+/* 151 */
+/* 152 */
+/* 153 */
+/* 154 */
+/* 155 */
+/* 156 */
+/* 157 */
+/* 158 */
+/* 159 */
+
+#define TEGRA30_CLK_UARTB 160
+#define TEGRA30_CLK_VFIR 161
+#define TEGRA30_CLK_SPDIF_IN 162
+#define TEGRA30_CLK_SPDIF_OUT 163
+#define TEGRA30_CLK_VI 164
+#define TEGRA30_CLK_VI_SENSOR 165
+#define TEGRA30_CLK_FUSE 166
+#define TEGRA30_CLK_FUSE_BURN 167
+#define TEGRA30_CLK_CVE 168
+#define TEGRA30_CLK_TVO 169
+#define TEGRA30_CLK_CLK_32K 170
+#define TEGRA30_CLK_CLK_M 171
+#define TEGRA30_CLK_CLK_M_DIV2 172
+#define TEGRA30_CLK_CLK_M_DIV4 173
+#define TEGRA30_CLK_PLL_REF 174
+#define TEGRA30_CLK_PLL_C 175
+#define TEGRA30_CLK_PLL_C_OUT1 176
+#define TEGRA30_CLK_PLL_M 177
+#define TEGRA30_CLK_PLL_M_OUT1 178
+#define TEGRA30_CLK_PLL_P 179
+#define TEGRA30_CLK_PLL_P_OUT1 180
+#define TEGRA30_CLK_PLL_P_OUT2 181
+#define TEGRA30_CLK_PLL_P_OUT3 182
+#define TEGRA30_CLK_PLL_P_OUT4 183
+#define TEGRA30_CLK_PLL_A 184
+#define TEGRA30_CLK_PLL_A_OUT0 185
+#define TEGRA30_CLK_PLL_D 186
+#define TEGRA30_CLK_PLL_D_OUT0 187
+#define TEGRA30_CLK_PLL_D2 188
+#define TEGRA30_CLK_PLL_D2_OUT0 189
+#define TEGRA30_CLK_PLL_U 190
+#define TEGRA30_CLK_PLL_X 191
+
+#define TEGRA30_CLK_PLL_X_OUT0 192
+#define TEGRA30_CLK_PLL_E 193
+#define TEGRA30_CLK_SPDIF_IN_SYNC 194
+#define TEGRA30_CLK_I2S0_SYNC 195
+#define TEGRA30_CLK_I2S1_SYNC 196
+#define TEGRA30_CLK_I2S2_SYNC 197
+#define TEGRA30_CLK_I2S3_SYNC 198
+#define TEGRA30_CLK_I2S4_SYNC 199
+#define TEGRA30_CLK_VIMCLK_SYNC 200
+#define TEGRA30_CLK_AUDIO0 201
+#define TEGRA30_CLK_AUDIO1 202
+#define TEGRA30_CLK_AUDIO2 203
+#define TEGRA30_CLK_AUDIO3 204
+#define TEGRA30_CLK_AUDIO4 205
+#define TEGRA30_CLK_SPDIF 206
+#define TEGRA30_CLK_CLK_OUT_1 207 /* (extern1) */
+#define TEGRA30_CLK_CLK_OUT_2 208 /* (extern2) */
+#define TEGRA30_CLK_CLK_OUT_3 209 /* (extern3) */
+#define TEGRA30_CLK_SCLK 210
+#define TEGRA30_CLK_BLINK 211
+#define TEGRA30_CLK_CCLK_G 212
+#define TEGRA30_CLK_CCLK_LP 213
+#define TEGRA30_CLK_TWD 214
+#define TEGRA30_CLK_CML0 215
+#define TEGRA30_CLK_CML1 216
+#define TEGRA30_CLK_HCLK 217
+#define TEGRA30_CLK_PCLK 218
+/* 219 */
+/* 220 */
+/* 221 */
+/* 222 */
+/* 223 */
+
+/* 288 */
+/* 289 */
+/* 290 */
+/* 291 */
+/* 292 */
+/* 293 */
+/* 294 */
+/* 295 */
+/* 296 */
+/* 297 */
+/* 298 */
+/* 299 */
+#define TEGRA30_CLK_CLK_OUT_1_MUX 300
+#define TEGRA30_CLK_CLK_OUT_2_MUX 301
+#define TEGRA30_CLK_CLK_OUT_3_MUX 302
+#define TEGRA30_CLK_AUDIO0_MUX 303
+#define TEGRA30_CLK_AUDIO1_MUX 304
+#define TEGRA30_CLK_AUDIO2_MUX 305
+#define TEGRA30_CLK_AUDIO3_MUX 306
+#define TEGRA30_CLK_AUDIO4_MUX 307
+#define TEGRA30_CLK_SPDIF_MUX 308
+#define TEGRA30_CLK_CLK_MAX 309
+
+#endif	/* _DT_BINDINGS_CLOCK_TEGRA30_CAR_H */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/vf610-clock.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/vf610-clock.h
new file mode 100644
index 0000000000000000000000000000000000000000..45997750c8a02a8e4bf75ee6d3da305d0668e922
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/vf610-clock.h
@@ -0,0 +1,204 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_VF610_H
+#define __DT_BINDINGS_CLOCK_VF610_H
+
+#define VF610_CLK_DUMMY			0
+#define VF610_CLK_SIRC_128K		1
+#define VF610_CLK_SIRC_32K		2
+#define VF610_CLK_FIRC			3
+#define VF610_CLK_SXOSC			4
+#define VF610_CLK_FXOSC			5
+#define VF610_CLK_FXOSC_HALF		6
+#define VF610_CLK_SLOW_CLK_SEL		7
+#define VF610_CLK_FASK_CLK_SEL		8
+#define VF610_CLK_AUDIO_EXT		9
+#define VF610_CLK_ENET_EXT		10
+#define VF610_CLK_PLL1_SYS		11
+#define VF610_CLK_PLL1_PFD1		12
+#define VF610_CLK_PLL1_PFD2		13
+#define VF610_CLK_PLL1_PFD3		14
+#define VF610_CLK_PLL1_PFD4		15
+#define VF610_CLK_PLL2_BUS		16
+#define VF610_CLK_PLL2_PFD1		17
+#define VF610_CLK_PLL2_PFD2		18
+#define VF610_CLK_PLL2_PFD3		19
+#define VF610_CLK_PLL2_PFD4		20
+#define VF610_CLK_PLL3_USB_OTG		21
+#define VF610_CLK_PLL3_PFD1		22
+#define VF610_CLK_PLL3_PFD2		23
+#define VF610_CLK_PLL3_PFD3		24
+#define VF610_CLK_PLL3_PFD4		25
+#define VF610_CLK_PLL4_AUDIO		26
+#define VF610_CLK_PLL5_ENET		27
+#define VF610_CLK_PLL6_VIDEO		28
+#define VF610_CLK_PLL3_MAIN_DIV		29
+#define VF610_CLK_PLL4_MAIN_DIV		30
+#define VF610_CLK_PLL6_MAIN_DIV		31
+#define VF610_CLK_PLL1_PFD_SEL		32
+#define VF610_CLK_PLL2_PFD_SEL		33
+#define VF610_CLK_SYS_SEL		34
+#define VF610_CLK_DDR_SEL		35
+#define VF610_CLK_SYS_BUS		36
+#define VF610_CLK_PLATFORM_BUS		37
+#define VF610_CLK_IPG_BUS		38
+#define VF610_CLK_UART0			39
+#define VF610_CLK_UART1			40
+#define VF610_CLK_UART2			41
+#define VF610_CLK_UART3			42
+#define VF610_CLK_UART4			43
+#define VF610_CLK_UART5			44
+#define VF610_CLK_PIT			45
+#define VF610_CLK_I2C0			46
+#define VF610_CLK_I2C1			47
+#define VF610_CLK_I2C2			48
+#define VF610_CLK_I2C3			49
+#define VF610_CLK_FTM0_EXT_SEL		50
+#define VF610_CLK_FTM0_FIX_SEL		51
+#define VF610_CLK_FTM0_EXT_FIX_EN	52
+#define VF610_CLK_FTM1_EXT_SEL		53
+#define VF610_CLK_FTM1_FIX_SEL		54
+#define VF610_CLK_FTM1_EXT_FIX_EN	55
+#define VF610_CLK_FTM2_EXT_SEL		56
+#define VF610_CLK_FTM2_FIX_SEL		57
+#define VF610_CLK_FTM2_EXT_FIX_EN	58
+#define VF610_CLK_FTM3_EXT_SEL		59
+#define VF610_CLK_FTM3_FIX_SEL		60
+#define VF610_CLK_FTM3_EXT_FIX_EN	61
+#define VF610_CLK_FTM0			62
+#define VF610_CLK_FTM1			63
+#define VF610_CLK_FTM2			64
+#define VF610_CLK_FTM3			65
+#define VF610_CLK_ENET_50M		66
+#define VF610_CLK_ENET_25M		67
+#define VF610_CLK_ENET_SEL		68
+#define VF610_CLK_ENET			69
+#define VF610_CLK_ENET_TS_SEL		70
+#define VF610_CLK_ENET_TS		71
+#define VF610_CLK_DSPI0			72
+#define VF610_CLK_DSPI1			73
+#define VF610_CLK_DSPI2			74
+#define VF610_CLK_DSPI3			75
+#define VF610_CLK_WDT			76
+#define VF610_CLK_ESDHC0_SEL		77
+#define VF610_CLK_ESDHC0_EN		78
+#define VF610_CLK_ESDHC0_DIV		79
+#define VF610_CLK_ESDHC0		80
+#define VF610_CLK_ESDHC1_SEL		81
+#define VF610_CLK_ESDHC1_EN		82
+#define VF610_CLK_ESDHC1_DIV		83
+#define VF610_CLK_ESDHC1		84
+#define VF610_CLK_DCU0_SEL		85
+#define VF610_CLK_DCU0_EN		86
+#define VF610_CLK_DCU0_DIV		87
+#define VF610_CLK_DCU0			88
+#define VF610_CLK_DCU1_SEL		89
+#define VF610_CLK_DCU1_EN		90
+#define VF610_CLK_DCU1_DIV		91
+#define VF610_CLK_DCU1			92
+#define VF610_CLK_ESAI_SEL		93
+#define VF610_CLK_ESAI_EN		94
+#define VF610_CLK_ESAI_DIV		95
+#define VF610_CLK_ESAI			96
+#define VF610_CLK_SAI0_SEL		97
+#define VF610_CLK_SAI0_EN		98
+#define VF610_CLK_SAI0_DIV		99
+#define VF610_CLK_SAI0			100
+#define VF610_CLK_SAI1_SEL		101
+#define VF610_CLK_SAI1_EN		102
+#define VF610_CLK_SAI1_DIV		103
+#define VF610_CLK_SAI1			104
+#define VF610_CLK_SAI2_SEL		105
+#define VF610_CLK_SAI2_EN		106
+#define VF610_CLK_SAI2_DIV		107
+#define VF610_CLK_SAI2			108
+#define VF610_CLK_SAI3_SEL		109
+#define VF610_CLK_SAI3_EN		110
+#define VF610_CLK_SAI3_DIV		111
+#define VF610_CLK_SAI3			112
+#define VF610_CLK_USBC0			113
+#define VF610_CLK_USBC1			114
+#define VF610_CLK_QSPI0_SEL		115
+#define VF610_CLK_QSPI0_EN		116
+#define VF610_CLK_QSPI0_X4_DIV		117
+#define VF610_CLK_QSPI0_X2_DIV		118
+#define VF610_CLK_QSPI0_X1_DIV		119
+#define VF610_CLK_QSPI1_SEL		120
+#define VF610_CLK_QSPI1_EN		121
+#define VF610_CLK_QSPI1_X4_DIV		122
+#define VF610_CLK_QSPI1_X2_DIV		123
+#define VF610_CLK_QSPI1_X1_DIV		124
+#define VF610_CLK_QSPI0			125
+#define VF610_CLK_QSPI1			126
+#define VF610_CLK_NFC_SEL		127
+#define VF610_CLK_NFC_EN		128
+#define VF610_CLK_NFC_PRE_DIV		129
+#define VF610_CLK_NFC_FRAC_DIV		130
+#define VF610_CLK_NFC_INV		131
+#define VF610_CLK_NFC			132
+#define VF610_CLK_VADC_SEL		133
+#define VF610_CLK_VADC_EN		134
+#define VF610_CLK_VADC_DIV		135
+#define VF610_CLK_VADC_DIV_HALF		136
+#define VF610_CLK_VADC			137
+#define VF610_CLK_ADC0			138
+#define VF610_CLK_ADC1			139
+#define VF610_CLK_DAC0			140
+#define VF610_CLK_DAC1			141
+#define VF610_CLK_FLEXCAN0		142
+#define VF610_CLK_FLEXCAN1		143
+#define VF610_CLK_ASRC			144
+#define VF610_CLK_GPU_SEL		145
+#define VF610_CLK_GPU_EN		146
+#define VF610_CLK_GPU2D			147
+#define VF610_CLK_ENET0			148
+#define VF610_CLK_ENET1			149
+#define VF610_CLK_DMAMUX0		150
+#define VF610_CLK_DMAMUX1		151
+#define VF610_CLK_DMAMUX2		152
+#define VF610_CLK_DMAMUX3		153
+#define VF610_CLK_FLEXCAN0_EN		154
+#define VF610_CLK_FLEXCAN1_EN		155
+#define VF610_CLK_PLL7_USB_HOST		156
+#define VF610_CLK_USBPHY0		157
+#define VF610_CLK_USBPHY1		158
+#define VF610_CLK_LVDS1_IN		159
+#define VF610_CLK_ANACLK1		160
+#define VF610_CLK_PLL1_BYPASS_SRC	161
+#define VF610_CLK_PLL2_BYPASS_SRC	162
+#define VF610_CLK_PLL3_BYPASS_SRC	163
+#define VF610_CLK_PLL4_BYPASS_SRC	164
+#define VF610_CLK_PLL5_BYPASS_SRC	165
+#define VF610_CLK_PLL6_BYPASS_SRC	166
+#define VF610_CLK_PLL7_BYPASS_SRC	167
+#define VF610_CLK_PLL1			168
+#define VF610_CLK_PLL2			169
+#define VF610_CLK_PLL3			170
+#define VF610_CLK_PLL4			171
+#define VF610_CLK_PLL5			172
+#define VF610_CLK_PLL6			173
+#define VF610_CLK_PLL7			174
+#define VF610_PLL1_BYPASS		175
+#define VF610_PLL2_BYPASS		176
+#define VF610_PLL3_BYPASS		177
+#define VF610_PLL4_BYPASS		178
+#define VF610_PLL5_BYPASS		179
+#define VF610_PLL6_BYPASS		180
+#define VF610_PLL7_BYPASS		181
+#define VF610_CLK_SNVS			182
+#define VF610_CLK_DAP			183
+#define VF610_CLK_OCOTP			184
+#define VF610_CLK_DDRMC			185
+#define VF610_CLK_WKPU			186
+#define VF610_CLK_TCON0			187
+#define VF610_CLK_TCON1			188
+#define VF610_CLK_END			189
+
+#endif /* __DT_BINDINGS_CLOCK_VF610_H */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/zx296702-clock.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/zx296702-clock.h
new file mode 100644
index 0000000000000000000000000000000000000000..26ee564b0e6892809869ba98c1902cedb9ea9d14
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/zx296702-clock.h
@@ -0,0 +1,183 @@
+/*
+ * Copyright 2014 Linaro Ltd.
+ * Copyright (C) 2014 ZTE Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_ZX296702_H
+#define __DT_BINDINGS_CLOCK_ZX296702_H
+
+#define ZX296702_OSC				0
+#define ZX296702_PLL_A9				1
+#define ZX296702_PLL_A9_350M			2
+#define ZX296702_PLL_MAC_1000M			3
+#define ZX296702_PLL_MAC_333M			4
+#define ZX296702_PLL_MM0_1188M			5
+#define ZX296702_PLL_MM0_396M			6
+#define ZX296702_PLL_MM0_198M			7
+#define ZX296702_PLL_MM1_108M			8
+#define ZX296702_PLL_MM1_72M			9
+#define ZX296702_PLL_MM1_54M			10
+#define ZX296702_PLL_LSP_104M			11
+#define ZX296702_PLL_LSP_26M			12
+#define ZX296702_PLL_AUDIO_294M912		13
+#define ZX296702_PLL_DDR_266M			14
+#define ZX296702_CLK_148M5			15
+#define ZX296702_MATRIX_ACLK			16
+#define ZX296702_MAIN_HCLK			17
+#define ZX296702_MAIN_PCLK			18
+#define ZX296702_CLK_500			19
+#define ZX296702_CLK_250			20
+#define ZX296702_CLK_125			21
+#define ZX296702_CLK_74M25			22
+#define ZX296702_A9_WCLK			23
+#define ZX296702_A9_AS1_ACLK_MUX		24
+#define ZX296702_A9_TRACE_CLKIN_MUX		25
+#define ZX296702_A9_AS1_ACLK_DIV		26
+#define ZX296702_CLK_2				27
+#define ZX296702_CLK_27				28
+#define ZX296702_DECPPU_ACLK_MUX		29
+#define ZX296702_PPU_ACLK_MUX			30
+#define ZX296702_MALI400_ACLK_MUX		31
+#define ZX296702_VOU_ACLK_MUX			32
+#define ZX296702_VOU_MAIN_WCLK_MUX		33
+#define ZX296702_VOU_AUX_WCLK_MUX		34
+#define ZX296702_VOU_SCALER_WCLK_MUX		35
+#define ZX296702_R2D_ACLK_MUX			36
+#define ZX296702_R2D_WCLK_MUX			37
+#define ZX296702_CLK_50				38
+#define ZX296702_CLK_25				39
+#define ZX296702_CLK_12				40
+#define ZX296702_CLK_16M384			41
+#define ZX296702_CLK_32K768			42
+#define ZX296702_SEC_WCLK_DIV			43
+#define ZX296702_DDR_WCLK_MUX			44
+#define ZX296702_NAND_WCLK_MUX			45
+#define ZX296702_LSP_26_WCLK_MUX		46
+#define ZX296702_A9_AS0_ACLK			47
+#define ZX296702_A9_AS1_ACLK			48
+#define ZX296702_A9_TRACE_CLKIN			49
+#define ZX296702_DECPPU_AXI_M_ACLK		50
+#define ZX296702_DECPPU_AHB_S_HCLK		51
+#define ZX296702_PPU_AXI_M_ACLK			52
+#define ZX296702_PPU_AHB_S_HCLK			53
+#define ZX296702_VOU_AXI_M_ACLK			54
+#define ZX296702_VOU_APB_PCLK			55
+#define ZX296702_VOU_MAIN_CHANNEL_WCLK		56
+#define ZX296702_VOU_AUX_CHANNEL_WCLK		57
+#define ZX296702_VOU_HDMI_OSCLK_CEC		58
+#define ZX296702_VOU_SCALER_WCLK		59
+#define ZX296702_MALI400_AXI_M_ACLK		60
+#define ZX296702_MALI400_APB_PCLK		61
+#define ZX296702_R2D_WCLK			62
+#define ZX296702_R2D_AXI_M_ACLK			63
+#define ZX296702_R2D_AHB_HCLK			64
+#define ZX296702_DDR3_AXI_S0_ACLK		65
+#define ZX296702_DDR3_APB_PCLK			66
+#define ZX296702_DDR3_WCLK			67
+#define ZX296702_USB20_0_AHB_HCLK		68
+#define ZX296702_USB20_0_EXTREFCLK		69
+#define ZX296702_USB20_1_AHB_HCLK		70
+#define ZX296702_USB20_1_EXTREFCLK		71
+#define ZX296702_USB20_2_AHB_HCLK		72
+#define ZX296702_USB20_2_EXTREFCLK		73
+#define ZX296702_GMAC_AXI_M_ACLK		74
+#define ZX296702_GMAC_APB_PCLK			75
+#define ZX296702_GMAC_125_CLKIN			76
+#define ZX296702_GMAC_RMII_CLKIN		77
+#define ZX296702_GMAC_25M_CLK			78
+#define ZX296702_NANDFLASH_AHB_HCLK		79
+#define ZX296702_NANDFLASH_WCLK			80
+#define ZX296702_LSP0_APB_PCLK			81
+#define ZX296702_LSP0_AHB_HCLK			82
+#define ZX296702_LSP0_26M_WCLK			83
+#define ZX296702_LSP0_104M_WCLK			84
+#define ZX296702_LSP0_16M384_WCLK		85
+#define ZX296702_LSP1_APB_PCLK			86
+#define ZX296702_LSP1_26M_WCLK			87
+#define ZX296702_LSP1_104M_WCLK			88
+#define ZX296702_LSP1_32K_CLK			89
+#define ZX296702_AON_HCLK			90
+#define ZX296702_SYS_CTRL_PCLK			91
+#define ZX296702_DMA_PCLK			92
+#define ZX296702_DMA_ACLK			93
+#define ZX296702_SEC_HCLK			94
+#define ZX296702_AES_WCLK			95
+#define ZX296702_DES_WCLK			96
+#define ZX296702_IRAM_ACLK			97
+#define ZX296702_IROM_ACLK			98
+#define ZX296702_BOOT_CTRL_HCLK			99
+#define ZX296702_EFUSE_CLK_30			100
+#define ZX296702_VOU_MAIN_CHANNEL_DIV		101
+#define ZX296702_VOU_AUX_CHANNEL_DIV		102
+#define ZX296702_VOU_TV_ENC_HD_DIV		103
+#define ZX296702_VOU_TV_ENC_SD_DIV		104
+#define ZX296702_VL0_MUX			105
+#define ZX296702_VL1_MUX			106
+#define ZX296702_VL2_MUX			107
+#define ZX296702_GL0_MUX			108
+#define ZX296702_GL1_MUX			109
+#define ZX296702_GL2_MUX			110
+#define ZX296702_WB_MUX				111
+#define ZX296702_HDMI_MUX			112
+#define ZX296702_VOU_TV_ENC_HD_MUX		113
+#define ZX296702_VOU_TV_ENC_SD_MUX		114
+#define ZX296702_VL0_CLK			115
+#define ZX296702_VL1_CLK			116
+#define ZX296702_VL2_CLK			117
+#define ZX296702_GL0_CLK			118
+#define ZX296702_GL1_CLK			119
+#define ZX296702_GL2_CLK			120
+#define ZX296702_WB_CLK				121
+#define ZX296702_CL_CLK				122
+#define ZX296702_MAIN_MIX_CLK			123
+#define ZX296702_AUX_MIX_CLK			124
+#define ZX296702_HDMI_CLK			125
+#define ZX296702_VOU_TV_ENC_HD_DAC_CLK		126
+#define ZX296702_VOU_TV_ENC_SD_DAC_CLK		127
+#define ZX296702_A9_PERIPHCLK			128
+#define ZX296702_TOPCLK_END			129
+
+#define ZX296702_SDMMC1_WCLK_MUX		0
+#define ZX296702_SDMMC1_WCLK_DIV		1
+#define ZX296702_SDMMC1_WCLK			2
+#define ZX296702_SDMMC1_PCLK			3
+#define ZX296702_SPDIF0_WCLK_MUX		4
+#define ZX296702_SPDIF0_WCLK			5
+#define ZX296702_SPDIF0_PCLK			6
+#define ZX296702_SPDIF0_DIV			7
+#define ZX296702_I2S0_WCLK_MUX			8
+#define ZX296702_I2S0_WCLK			9
+#define ZX296702_I2S0_PCLK			10
+#define ZX296702_I2S0_DIV			11
+#define ZX296702_I2S1_WCLK_MUX			12
+#define ZX296702_I2S1_WCLK			13
+#define ZX296702_I2S1_PCLK			14
+#define ZX296702_I2S1_DIV			15
+#define ZX296702_I2S2_WCLK_MUX			16
+#define ZX296702_I2S2_WCLK			17
+#define ZX296702_I2S2_PCLK			18
+#define ZX296702_I2S2_DIV			19
+#define ZX296702_GPIO_CLK			20
+#define ZX296702_LSP0CLK_END			21
+
+#define ZX296702_UART0_WCLK_MUX			0
+#define ZX296702_UART0_WCLK			1
+#define ZX296702_UART0_PCLK			2
+#define ZX296702_UART1_WCLK_MUX			3
+#define ZX296702_UART1_WCLK			4
+#define ZX296702_UART1_PCLK			5
+#define ZX296702_SDMMC0_WCLK_MUX		6
+#define ZX296702_SDMMC0_WCLK_DIV		7
+#define ZX296702_SDMMC0_WCLK			8
+#define ZX296702_SDMMC0_PCLK			9
+#define ZX296702_SPDIF1_WCLK_MUX		10
+#define ZX296702_SPDIF1_WCLK			11
+#define ZX296702_SPDIF1_PCLK			12
+#define ZX296702_SPDIF1_DIV			13
+#define ZX296702_LSP1CLK_END			14
+
+#endif /* __DT_BINDINGS_CLOCK_ZX296702_H */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/zx296718-clock.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/zx296718-clock.h
new file mode 100644
index 0000000000000000000000000000000000000000..092c9751a697eaea73e1e44b370dfa2082e974a2
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/clock/zx296718-clock.h
@@ -0,0 +1,167 @@
+/*
+ * Copyright (C) 2015 - 2016 ZTE Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __DT_BINDINGS_CLOCK_ZX296718_H
+#define __DT_BINDINGS_CLOCK_ZX296718_H
+
+/* PLL */
+#define ZX296718_PLL_CPU	1
+#define ZX296718_PLL_MAC	2
+#define ZX296718_PLL_MM0	3
+#define ZX296718_PLL_MM1	4
+#define ZX296718_PLL_VGA	5
+#define ZX296718_PLL_DDR	6
+#define ZX296718_PLL_AUDIO	7
+#define ZX296718_PLL_HSIC	8
+#define CPU_DBG_GATE		9
+#define A72_GATE		10
+#define CPU_PERI_GATE		11
+#define A53_GATE		12
+#define DDR1_GATE		13
+#define DDR0_GATE		14
+#define SD1_WCLK		15
+#define SD1_AHB			16
+#define SD0_WCLK		17
+#define SD0_AHB			18
+#define EMMC_WCLK		19
+#define EMMC_NAND_AXI		20
+#define NAND_WCLK		21
+#define EMMC_NAND_AHB		22
+#define LSP1_148M5		23
+#define LSP1_99M		24
+#define LSP1_24M		25
+#define LSP0_74M25		26
+#define LSP0_32K		27
+#define LSP0_148M5		28
+#define LSP0_99M		29
+#define LSP0_24M		30
+#define DEMUX_AXI		31
+#define DEMUX_APB		32
+#define DEMUX_148M5		33
+#define DEMUX_108M		34
+#define AUDIO_APB		35
+#define AUDIO_99M		36
+#define AUDIO_24M		37
+#define AUDIO_16M384		38
+#define AUDIO_32K		39
+#define WDT_WCLK		40
+#define TIMER_WCLK		41
+#define VDE_ACLK		42
+#define VCE_ACLK		43
+#define HDE_ACLK		44
+#define GPU_ACLK		45
+#define SAPPU_ACLK		46
+#define SAPPU_WCLK		47
+#define VOU_ACLK		48
+#define VOU_MAIN_WCLK		49
+#define VOU_AUX_WCLK		50
+#define VOU_PPU_WCLK		51
+#define MIPI_CFG_CLK		52
+#define VGA_I2C_WCLK		53
+#define MIPI_REF_CLK		54
+#define HDMI_OSC_CEC		55
+#define HDMI_OSC_CLK		56
+#define HDMI_XCLK		57
+#define VIU_M0_ACLK		58
+#define VIU_M1_ACLK		59
+#define VIU_WCLK		60
+#define VIU_JPEG_WCLK		61
+#define VIU_CFG_CLK		62
+#define TS_SYS_WCLK		63
+#define TS_SYS_108M		64
+#define USB20_HCLK		65
+#define USB20_PHY_CLK		66
+#define USB21_HCLK		67
+#define USB21_PHY_CLK		68
+#define GMAC_RMIICLK		69
+#define GMAC_PCLK		70
+#define GMAC_ACLK		71
+#define GMAC_RFCLK		72
+#define TEMPSENSOR_GATE		73
+
+#define TOP_NR_CLKS		74
+
+
+#define LSP0_TIMER3_PCLK	1
+#define LSP0_TIMER3_WCLK	2
+#define LSP0_TIMER4_PCLK	3
+#define LSP0_TIMER4_WCLK	4
+#define LSP0_TIMER5_PCLK	5
+#define LSP0_TIMER5_WCLK	6
+#define LSP0_UART3_PCLK		7
+#define LSP0_UART3_WCLK		8
+#define LSP0_UART1_PCLK		9
+#define LSP0_UART1_WCLK		10
+#define LSP0_UART2_PCLK		11
+#define LSP0_UART2_WCLK		12
+#define LSP0_SPIFC0_PCLK	13
+#define LSP0_SPIFC0_WCLK	14
+#define LSP0_I2C4_PCLK		15
+#define LSP0_I2C4_WCLK		16
+#define LSP0_I2C5_PCLK		17
+#define LSP0_I2C5_WCLK		18
+#define LSP0_SSP0_PCLK		19
+#define LSP0_SSP0_WCLK		20
+#define LSP0_SSP1_PCLK		21
+#define LSP0_SSP1_WCLK		22
+#define LSP0_USIM_PCLK		23
+#define LSP0_USIM_WCLK		24
+#define LSP0_GPIO_PCLK		25
+#define LSP0_GPIO_WCLK		26
+#define LSP0_I2C3_PCLK		27
+#define LSP0_I2C3_WCLK		28
+
+#define LSP0_NR_CLKS		29
+
+
+#define LSP1_UART4_PCLK		1
+#define LSP1_UART4_WCLK		2
+#define LSP1_UART5_PCLK		3
+#define LSP1_UART5_WCLK		4
+#define LSP1_PWM_PCLK		5
+#define LSP1_PWM_WCLK		6
+#define LSP1_I2C2_PCLK		7
+#define LSP1_I2C2_WCLK		8
+#define LSP1_SSP2_PCLK		9
+#define LSP1_SSP2_WCLK		10
+#define LSP1_SSP3_PCLK		11
+#define LSP1_SSP3_WCLK		12
+#define LSP1_SSP4_PCLK		13
+#define LSP1_SSP4_WCLK		14
+#define LSP1_USIM1_PCLK		15
+#define LSP1_USIM1_WCLK		16
+
+#define LSP1_NR_CLKS		17
+
+
+#define AUDIO_I2S0_WCLK		1
+#define AUDIO_I2S0_PCLK		2
+#define AUDIO_I2S1_WCLK		3
+#define AUDIO_I2S1_PCLK		4
+#define AUDIO_I2S2_WCLK		5
+#define AUDIO_I2S2_PCLK		6
+#define AUDIO_I2S3_WCLK		7
+#define AUDIO_I2S3_PCLK		8
+#define AUDIO_I2C0_WCLK		9
+#define AUDIO_I2C0_PCLK		10
+#define AUDIO_SPDIF0_WCLK	11
+#define AUDIO_SPDIF0_PCLK	12
+#define AUDIO_SPDIF1_WCLK	13
+#define AUDIO_SPDIF1_PCLK	14
+#define AUDIO_TIMER_WCLK	15
+#define AUDIO_TIMER_PCLK	16
+#define AUDIO_TDM_WCLK		17
+#define AUDIO_TDM_PCLK		18
+#define AUDIO_TS_PCLK		19
+#define I2S0_WCLK_MUX		20
+#define I2S1_WCLK_MUX		21
+#define I2S2_WCLK_MUX		22
+#define I2S3_WCLK_MUX		23
+
+#define AUDIO_NR_CLKS		24
+
+#endif
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/display/tda998x.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/display/tda998x.h
new file mode 100644
index 0000000000000000000000000000000000000000..746831ff396c26b1bd10ff3c11ec82aa702f7a67
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/display/tda998x.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef _DT_BINDINGS_TDA998X_H
+#define _DT_BINDINGS_TDA998X_H
+
+#define TDA998x_SPDIF	1
+#define TDA998x_I2S	2
+
+#endif /*_DT_BINDINGS_TDA998X_H */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/gpio/gpio.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/gpio/gpio.h
new file mode 100644
index 0000000000000000000000000000000000000000..c029467e828b29f79dc4150792a4ed2fd87e00b2
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/gpio/gpio.h
@@ -0,0 +1,42 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * This header provides constants for most GPIO bindings.
+ *
+ * Most GPIO bindings include a flags cell as part of the GPIO specifier.
+ * In most cases, the format of the flags cell uses the standard values
+ * defined in this header.
+ */
+
+#ifndef _DT_BINDINGS_GPIO_GPIO_H
+#define _DT_BINDINGS_GPIO_GPIO_H
+
+/* Bit 0 express polarity */
+#define GPIO_ACTIVE_HIGH 0
+#define GPIO_ACTIVE_LOW 1
+
+/* Bit 1 express single-endedness */
+#define GPIO_PUSH_PULL 0
+#define GPIO_SINGLE_ENDED 2
+
+/* Bit 2 express Open drain or open source */
+#define GPIO_LINE_OPEN_SOURCE 0
+#define GPIO_LINE_OPEN_DRAIN 4
+
+/*
+ * Open Drain/Collector is the combination of single-ended open drain interface.
+ * Open Source/Emitter is the combination of single-ended open source interface.
+ */
+#define GPIO_OPEN_DRAIN (GPIO_SINGLE_ENDED | GPIO_LINE_OPEN_DRAIN)
+#define GPIO_OPEN_SOURCE (GPIO_SINGLE_ENDED | GPIO_LINE_OPEN_SOURCE)
+
+/* Bit 3 express GPIO suspend/resume and reset persistence */
+#define GPIO_PERSISTENT 0
+#define GPIO_TRANSITORY 8
+
+/* Bit 4 express pull up */
+#define GPIO_PULL_UP 16
+
+/* Bit 5 express pull down */
+#define GPIO_PULL_DOWN 32
+
+#endif
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/input/gpio-keys.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/input/gpio-keys.h
new file mode 100644
index 0000000000000000000000000000000000000000..8962df79e753b7b80bf793d9d180154a543ef416
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/input/gpio-keys.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * This header provides constants for gpio keys bindings.
+ */
+
+#ifndef _DT_BINDINGS_GPIO_KEYS_H
+#define _DT_BINDINGS_GPIO_KEYS_H
+
+#define EV_ACT_ANY		0x00	/* asserted or deasserted */
+#define EV_ACT_ASSERTED		0x01	/* asserted */
+#define EV_ACT_DEASSERTED	0x02	/* deasserted */
+
+#endif /* _DT_BINDINGS_GPIO_KEYS_H */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/input/input-event-codes.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/input/input-event-codes.h
new file mode 100644
index 0000000000000000000000000000000000000000..61a5799b440b9f66758be86f4b20f6be6e877387
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/input/input-event-codes.h
@@ -0,0 +1,851 @@
+/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
+/*
+ * Input event codes
+ *
+ *    *** IMPORTANT ***
+ * This file is not only included from C-code but also from devicetree source
+ * files. As such this file MUST only contain comments and defines.
+ *
+ * Copyright (c) 1999-2002 Vojtech Pavlik
+ * Copyright (c) 2015 Hans de Goede <hdegoede@redhat.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ */
+#ifndef _UAPI_INPUT_EVENT_CODES_H
+#define _UAPI_INPUT_EVENT_CODES_H
+
+/*
+ * Device properties and quirks
+ */
+
+#define INPUT_PROP_POINTER		0x00	/* needs a pointer */
+#define INPUT_PROP_DIRECT		0x01	/* direct input devices */
+#define INPUT_PROP_BUTTONPAD		0x02	/* has button(s) under pad */
+#define INPUT_PROP_SEMI_MT		0x03	/* touch rectangle only */
+#define INPUT_PROP_TOPBUTTONPAD		0x04	/* softbuttons at top of pad */
+#define INPUT_PROP_POINTING_STICK	0x05	/* is a pointing stick */
+#define INPUT_PROP_ACCELEROMETER	0x06	/* has accelerometer */
+
+#define INPUT_PROP_MAX			0x1f
+#define INPUT_PROP_CNT			(INPUT_PROP_MAX + 1)
+
+/*
+ * Event types
+ */
+
+#define EV_SYN			0x00
+#define EV_KEY			0x01
+#define EV_REL			0x02
+#define EV_ABS			0x03
+#define EV_MSC			0x04
+#define EV_SW			0x05
+#define EV_LED			0x11
+#define EV_SND			0x12
+#define EV_REP			0x14
+#define EV_FF			0x15
+#define EV_PWR			0x16
+#define EV_FF_STATUS		0x17
+#define EV_MAX			0x1f
+#define EV_CNT			(EV_MAX+1)
+
+/*
+ * Synchronization events.
+ */
+
+#define SYN_REPORT		0
+#define SYN_CONFIG		1
+#define SYN_MT_REPORT		2
+#define SYN_DROPPED		3
+#define SYN_MAX			0xf
+#define SYN_CNT			(SYN_MAX+1)
+
+/*
+ * Keys and buttons
+ *
+ * Most of the keys/buttons are modeled after USB HUT 1.12
+ * (see http://www.usb.org/developers/hidpage).
+ * Abbreviations in the comments:
+ * AC - Application Control
+ * AL - Application Launch Button
+ * SC - System Control
+ */
+
+#define KEY_RESERVED		0
+#define KEY_ESC			1
+#define KEY_1			2
+#define KEY_2			3
+#define KEY_3			4
+#define KEY_4			5
+#define KEY_5			6
+#define KEY_6			7
+#define KEY_7			8
+#define KEY_8			9
+#define KEY_9			10
+#define KEY_0			11
+#define KEY_MINUS		12
+#define KEY_EQUAL		13
+#define KEY_BACKSPACE		14
+#define KEY_TAB			15
+#define KEY_Q			16
+#define KEY_W			17
+#define KEY_E			18
+#define KEY_R			19
+#define KEY_T			20
+#define KEY_Y			21
+#define KEY_U			22
+#define KEY_I			23
+#define KEY_O			24
+#define KEY_P			25
+#define KEY_LEFTBRACE		26
+#define KEY_RIGHTBRACE		27
+#define KEY_ENTER		28
+#define KEY_LEFTCTRL		29
+#define KEY_A			30
+#define KEY_S			31
+#define KEY_D			32
+#define KEY_F			33
+#define KEY_G			34
+#define KEY_H			35
+#define KEY_J			36
+#define KEY_K			37
+#define KEY_L			38
+#define KEY_SEMICOLON		39
+#define KEY_APOSTROPHE		40
+#define KEY_GRAVE		41
+#define KEY_LEFTSHIFT		42
+#define KEY_BACKSLASH		43
+#define KEY_Z			44
+#define KEY_X			45
+#define KEY_C			46
+#define KEY_V			47
+#define KEY_B			48
+#define KEY_N			49
+#define KEY_M			50
+#define KEY_COMMA		51
+#define KEY_DOT			52
+#define KEY_SLASH		53
+#define KEY_RIGHTSHIFT		54
+#define KEY_KPASTERISK		55
+#define KEY_LEFTALT		56
+#define KEY_SPACE		57
+#define KEY_CAPSLOCK		58
+#define KEY_F1			59
+#define KEY_F2			60
+#define KEY_F3			61
+#define KEY_F4			62
+#define KEY_F5			63
+#define KEY_F6			64
+#define KEY_F7			65
+#define KEY_F8			66
+#define KEY_F9			67
+#define KEY_F10			68
+#define KEY_NUMLOCK		69
+#define KEY_SCROLLLOCK		70
+#define KEY_KP7			71
+#define KEY_KP8			72
+#define KEY_KP9			73
+#define KEY_KPMINUS		74
+#define KEY_KP4			75
+#define KEY_KP5			76
+#define KEY_KP6			77
+#define KEY_KPPLUS		78
+#define KEY_KP1			79
+#define KEY_KP2			80
+#define KEY_KP3			81
+#define KEY_KP0			82
+#define KEY_KPDOT		83
+
+#define KEY_ZENKAKUHANKAKU	85
+#define KEY_102ND		86
+#define KEY_F11			87
+#define KEY_F12			88
+#define KEY_RO			89
+#define KEY_KATAKANA		90
+#define KEY_HIRAGANA		91
+#define KEY_HENKAN		92
+#define KEY_KATAKANAHIRAGANA	93
+#define KEY_MUHENKAN		94
+#define KEY_KPJPCOMMA		95
+#define KEY_KPENTER		96
+#define KEY_RIGHTCTRL		97
+#define KEY_KPSLASH		98
+#define KEY_SYSRQ		99
+#define KEY_RIGHTALT		100
+#define KEY_LINEFEED		101
+#define KEY_HOME		102
+#define KEY_UP			103
+#define KEY_PAGEUP		104
+#define KEY_LEFT		105
+#define KEY_RIGHT		106
+#define KEY_END			107
+#define KEY_DOWN		108
+#define KEY_PAGEDOWN		109
+#define KEY_INSERT		110
+#define KEY_DELETE		111
+#define KEY_MACRO		112
+#define KEY_MUTE		113
+#define KEY_VOLUMEDOWN		114
+#define KEY_VOLUMEUP		115
+#define KEY_POWER		116	/* SC System Power Down */
+#define KEY_KPEQUAL		117
+#define KEY_KPPLUSMINUS		118
+#define KEY_PAUSE		119
+#define KEY_SCALE		120	/* AL Compiz Scale (Expose) */
+
+#define KEY_KPCOMMA		121
+#define KEY_HANGEUL		122
+#define KEY_HANGUEL		KEY_HANGEUL
+#define KEY_HANJA		123
+#define KEY_YEN			124
+#define KEY_LEFTMETA		125
+#define KEY_RIGHTMETA		126
+#define KEY_COMPOSE		127
+
+#define KEY_STOP		128	/* AC Stop */
+#define KEY_AGAIN		129
+#define KEY_PROPS		130	/* AC Properties */
+#define KEY_UNDO		131	/* AC Undo */
+#define KEY_FRONT		132
+#define KEY_COPY		133	/* AC Copy */
+#define KEY_OPEN		134	/* AC Open */
+#define KEY_PASTE		135	/* AC Paste */
+#define KEY_FIND		136	/* AC Search */
+#define KEY_CUT			137	/* AC Cut */
+#define KEY_HELP		138	/* AL Integrated Help Center */
+#define KEY_MENU		139	/* Menu (show menu) */
+#define KEY_CALC		140	/* AL Calculator */
+#define KEY_SETUP		141
+#define KEY_SLEEP		142	/* SC System Sleep */
+#define KEY_WAKEUP		143	/* System Wake Up */
+#define KEY_FILE		144	/* AL Local Machine Browser */
+#define KEY_SENDFILE		145
+#define KEY_DELETEFILE		146
+#define KEY_XFER		147
+#define KEY_PROG1		148
+#define KEY_PROG2		149
+#define KEY_WWW			150	/* AL Internet Browser */
+#define KEY_MSDOS		151
+#define KEY_COFFEE		152	/* AL Terminal Lock/Screensaver */
+#define KEY_SCREENLOCK		KEY_COFFEE
+#define KEY_ROTATE_DISPLAY	153	/* Display orientation for e.g. tablets */
+#define KEY_DIRECTION		KEY_ROTATE_DISPLAY
+#define KEY_CYCLEWINDOWS	154
+#define KEY_MAIL		155
+#define KEY_BOOKMARKS		156	/* AC Bookmarks */
+#define KEY_COMPUTER		157
+#define KEY_BACK		158	/* AC Back */
+#define KEY_FORWARD		159	/* AC Forward */
+#define KEY_CLOSECD		160
+#define KEY_EJECTCD		161
+#define KEY_EJECTCLOSECD	162
+#define KEY_NEXTSONG		163
+#define KEY_PLAYPAUSE		164
+#define KEY_PREVIOUSSONG	165
+#define KEY_STOPCD		166
+#define KEY_RECORD		167
+#define KEY_REWIND		168
+#define KEY_PHONE		169	/* Media Select Telephone */
+#define KEY_ISO			170
+#define KEY_CONFIG		171	/* AL Consumer Control Configuration */
+#define KEY_HOMEPAGE		172	/* AC Home */
+#define KEY_REFRESH		173	/* AC Refresh */
+#define KEY_EXIT		174	/* AC Exit */
+#define KEY_MOVE		175
+#define KEY_EDIT		176
+#define KEY_SCROLLUP		177
+#define KEY_SCROLLDOWN		178
+#define KEY_KPLEFTPAREN		179
+#define KEY_KPRIGHTPAREN	180
+#define KEY_NEW			181	/* AC New */
+#define KEY_REDO		182	/* AC Redo/Repeat */
+
+#define KEY_F13			183
+#define KEY_F14			184
+#define KEY_F15			185
+#define KEY_F16			186
+#define KEY_F17			187
+#define KEY_F18			188
+#define KEY_F19			189
+#define KEY_F20			190
+#define KEY_F21			191
+#define KEY_F22			192
+#define KEY_F23			193
+#define KEY_F24			194
+
+#define KEY_PLAYCD		200
+#define KEY_PAUSECD		201
+#define KEY_PROG3		202
+#define KEY_PROG4		203
+#define KEY_DASHBOARD		204	/* AL Dashboard */
+#define KEY_SUSPEND		205
+#define KEY_CLOSE		206	/* AC Close */
+#define KEY_PLAY		207
+#define KEY_FASTFORWARD		208
+#define KEY_BASSBOOST		209
+#define KEY_PRINT		210	/* AC Print */
+#define KEY_HP			211
+#define KEY_CAMERA		212
+#define KEY_SOUND		213
+#define KEY_QUESTION		214
+#define KEY_EMAIL		215
+#define KEY_CHAT		216
+#define KEY_SEARCH		217
+#define KEY_CONNECT		218
+#define KEY_FINANCE		219	/* AL Checkbook/Finance */
+#define KEY_SPORT		220
+#define KEY_SHOP		221
+#define KEY_ALTERASE		222
+#define KEY_CANCEL		223	/* AC Cancel */
+#define KEY_BRIGHTNESSDOWN	224
+#define KEY_BRIGHTNESSUP	225
+#define KEY_MEDIA		226
+
+#define KEY_SWITCHVIDEOMODE	227	/* Cycle between available video
+					   outputs (Monitor/LCD/TV-out/etc) */
+#define KEY_KBDILLUMTOGGLE	228
+#define KEY_KBDILLUMDOWN	229
+#define KEY_KBDILLUMUP		230
+
+#define KEY_SEND		231	/* AC Send */
+#define KEY_REPLY		232	/* AC Reply */
+#define KEY_FORWARDMAIL		233	/* AC Forward Msg */
+#define KEY_SAVE		234	/* AC Save */
+#define KEY_DOCUMENTS		235
+
+#define KEY_BATTERY		236
+
+#define KEY_BLUETOOTH		237
+#define KEY_WLAN		238
+#define KEY_UWB			239
+
+#define KEY_UNKNOWN		240
+
+#define KEY_VIDEO_NEXT		241	/* drive next video source */
+#define KEY_VIDEO_PREV		242	/* drive previous video source */
+#define KEY_BRIGHTNESS_CYCLE	243	/* brightness up, after max is min */
+#define KEY_BRIGHTNESS_AUTO	244	/* Set Auto Brightness: manual
+					  brightness control is off,
+					  rely on ambient */
+#define KEY_BRIGHTNESS_ZERO	KEY_BRIGHTNESS_AUTO
+#define KEY_DISPLAY_OFF		245	/* display device to off state */
+
+#define KEY_WWAN		246	/* Wireless WAN (LTE, UMTS, GSM, etc.) */
+#define KEY_WIMAX		KEY_WWAN
+#define KEY_RFKILL		247	/* Key that controls all radios */
+
+#define KEY_MICMUTE		248	/* Mute / unmute the microphone */
+
+/* Code 255 is reserved for special needs of AT keyboard driver */
+
+#define BTN_MISC		0x100
+#define BTN_0			0x100
+#define BTN_1			0x101
+#define BTN_2			0x102
+#define BTN_3			0x103
+#define BTN_4			0x104
+#define BTN_5			0x105
+#define BTN_6			0x106
+#define BTN_7			0x107
+#define BTN_8			0x108
+#define BTN_9			0x109
+
+#define BTN_MOUSE		0x110
+#define BTN_LEFT		0x110
+#define BTN_RIGHT		0x111
+#define BTN_MIDDLE		0x112
+#define BTN_SIDE		0x113
+#define BTN_EXTRA		0x114
+#define BTN_FORWARD		0x115
+#define BTN_BACK		0x116
+#define BTN_TASK		0x117
+
+#define BTN_JOYSTICK		0x120
+#define BTN_TRIGGER		0x120
+#define BTN_THUMB		0x121
+#define BTN_THUMB2		0x122
+#define BTN_TOP			0x123
+#define BTN_TOP2		0x124
+#define BTN_PINKIE		0x125
+#define BTN_BASE		0x126
+#define BTN_BASE2		0x127
+#define BTN_BASE3		0x128
+#define BTN_BASE4		0x129
+#define BTN_BASE5		0x12a
+#define BTN_BASE6		0x12b
+#define BTN_DEAD		0x12f
+
+#define BTN_GAMEPAD		0x130
+#define BTN_SOUTH		0x130
+#define BTN_A			BTN_SOUTH
+#define BTN_EAST		0x131
+#define BTN_B			BTN_EAST
+#define BTN_C			0x132
+#define BTN_NORTH		0x133
+#define BTN_X			BTN_NORTH
+#define BTN_WEST		0x134
+#define BTN_Y			BTN_WEST
+#define BTN_Z			0x135
+#define BTN_TL			0x136
+#define BTN_TR			0x137
+#define BTN_TL2			0x138
+#define BTN_TR2			0x139
+#define BTN_SELECT		0x13a
+#define BTN_START		0x13b
+#define BTN_MODE		0x13c
+#define BTN_THUMBL		0x13d
+#define BTN_THUMBR		0x13e
+
+#define BTN_DIGI		0x140
+#define BTN_TOOL_PEN		0x140
+#define BTN_TOOL_RUBBER		0x141
+#define BTN_TOOL_BRUSH		0x142
+#define BTN_TOOL_PENCIL		0x143
+#define BTN_TOOL_AIRBRUSH	0x144
+#define BTN_TOOL_FINGER		0x145
+#define BTN_TOOL_MOUSE		0x146
+#define BTN_TOOL_LENS		0x147
+#define BTN_TOOL_QUINTTAP	0x148	/* Five fingers on trackpad */
+#define BTN_STYLUS3		0x149
+#define BTN_TOUCH		0x14a
+#define BTN_STYLUS		0x14b
+#define BTN_STYLUS2		0x14c
+#define BTN_TOOL_DOUBLETAP	0x14d
+#define BTN_TOOL_TRIPLETAP	0x14e
+#define BTN_TOOL_QUADTAP	0x14f	/* Four fingers on trackpad */
+
+#define BTN_WHEEL		0x150
+#define BTN_GEAR_DOWN		0x150
+#define BTN_GEAR_UP		0x151
+
+#define KEY_OK			0x160
+#define KEY_SELECT		0x161
+#define KEY_GOTO		0x162
+#define KEY_CLEAR		0x163
+#define KEY_POWER2		0x164
+#define KEY_OPTION		0x165
+#define KEY_INFO		0x166	/* AL OEM Features/Tips/Tutorial */
+#define KEY_TIME		0x167
+#define KEY_VENDOR		0x168
+#define KEY_ARCHIVE		0x169
+#define KEY_PROGRAM		0x16a	/* Media Select Program Guide */
+#define KEY_CHANNEL		0x16b
+#define KEY_FAVORITES		0x16c
+#define KEY_EPG			0x16d
+#define KEY_PVR			0x16e	/* Media Select Home */
+#define KEY_MHP			0x16f
+#define KEY_LANGUAGE		0x170
+#define KEY_TITLE		0x171
+#define KEY_SUBTITLE		0x172
+#define KEY_ANGLE		0x173
+#define KEY_ZOOM		0x174
+#define KEY_MODE		0x175
+#define KEY_KEYBOARD		0x176
+#define KEY_SCREEN		0x177
+#define KEY_PC			0x178	/* Media Select Computer */
+#define KEY_TV			0x179	/* Media Select TV */
+#define KEY_TV2			0x17a	/* Media Select Cable */
+#define KEY_VCR			0x17b	/* Media Select VCR */
+#define KEY_VCR2		0x17c	/* VCR Plus */
+#define KEY_SAT			0x17d	/* Media Select Satellite */
+#define KEY_SAT2		0x17e
+#define KEY_CD			0x17f	/* Media Select CD */
+#define KEY_TAPE		0x180	/* Media Select Tape */
+#define KEY_RADIO		0x181
+#define KEY_TUNER		0x182	/* Media Select Tuner */
+#define KEY_PLAYER		0x183
+#define KEY_TEXT		0x184
+#define KEY_DVD			0x185	/* Media Select DVD */
+#define KEY_AUX			0x186
+#define KEY_MP3			0x187
+#define KEY_AUDIO		0x188	/* AL Audio Browser */
+#define KEY_VIDEO		0x189	/* AL Movie Browser */
+#define KEY_DIRECTORY		0x18a
+#define KEY_LIST		0x18b
+#define KEY_MEMO		0x18c	/* Media Select Messages */
+#define KEY_CALENDAR		0x18d
+#define KEY_RED			0x18e
+#define KEY_GREEN		0x18f
+#define KEY_YELLOW		0x190
+#define KEY_BLUE		0x191
+#define KEY_CHANNELUP		0x192	/* Channel Increment */
+#define KEY_CHANNELDOWN		0x193	/* Channel Decrement */
+#define KEY_FIRST		0x194
+#define KEY_LAST		0x195	/* Recall Last */
+#define KEY_AB			0x196
+#define KEY_NEXT		0x197
+#define KEY_RESTART		0x198
+#define KEY_SLOW		0x199
+#define KEY_SHUFFLE		0x19a
+#define KEY_BREAK		0x19b
+#define KEY_PREVIOUS		0x19c
+#define KEY_DIGITS		0x19d
+#define KEY_TEEN		0x19e
+#define KEY_TWEN		0x19f
+#define KEY_VIDEOPHONE		0x1a0	/* Media Select Video Phone */
+#define KEY_GAMES		0x1a1	/* Media Select Games */
+#define KEY_ZOOMIN		0x1a2	/* AC Zoom In */
+#define KEY_ZOOMOUT		0x1a3	/* AC Zoom Out */
+#define KEY_ZOOMRESET		0x1a4	/* AC Zoom */
+#define KEY_WORDPROCESSOR	0x1a5	/* AL Word Processor */
+#define KEY_EDITOR		0x1a6	/* AL Text Editor */
+#define KEY_SPREADSHEET		0x1a7	/* AL Spreadsheet */
+#define KEY_GRAPHICSEDITOR	0x1a8	/* AL Graphics Editor */
+#define KEY_PRESENTATION	0x1a9	/* AL Presentation App */
+#define KEY_DATABASE		0x1aa	/* AL Database App */
+#define KEY_NEWS		0x1ab	/* AL Newsreader */
+#define KEY_VOICEMAIL		0x1ac	/* AL Voicemail */
+#define KEY_ADDRESSBOOK		0x1ad	/* AL Contacts/Address Book */
+#define KEY_MESSENGER		0x1ae	/* AL Instant Messaging */
+#define KEY_DISPLAYTOGGLE	0x1af	/* Turn display (LCD) on and off */
+#define KEY_BRIGHTNESS_TOGGLE	KEY_DISPLAYTOGGLE
+#define KEY_SPELLCHECK		0x1b0   /* AL Spell Check */
+#define KEY_LOGOFF		0x1b1   /* AL Logoff */
+
+#define KEY_DOLLAR		0x1b2
+#define KEY_EURO		0x1b3
+
+#define KEY_FRAMEBACK		0x1b4	/* Consumer - transport controls */
+#define KEY_FRAMEFORWARD	0x1b5
+#define KEY_CONTEXT_MENU	0x1b6	/* GenDesc - system context menu */
+#define KEY_MEDIA_REPEAT	0x1b7	/* Consumer - transport control */
+#define KEY_10CHANNELSUP	0x1b8	/* 10 channels up (10+) */
+#define KEY_10CHANNELSDOWN	0x1b9	/* 10 channels down (10-) */
+#define KEY_IMAGES		0x1ba	/* AL Image Browser */
+
+#define KEY_DEL_EOL		0x1c0
+#define KEY_DEL_EOS		0x1c1
+#define KEY_INS_LINE		0x1c2
+#define KEY_DEL_LINE		0x1c3
+
+#define KEY_FN			0x1d0
+#define KEY_FN_ESC		0x1d1
+#define KEY_FN_F1		0x1d2
+#define KEY_FN_F2		0x1d3
+#define KEY_FN_F3		0x1d4
+#define KEY_FN_F4		0x1d5
+#define KEY_FN_F5		0x1d6
+#define KEY_FN_F6		0x1d7
+#define KEY_FN_F7		0x1d8
+#define KEY_FN_F8		0x1d9
+#define KEY_FN_F9		0x1da
+#define KEY_FN_F10		0x1db
+#define KEY_FN_F11		0x1dc
+#define KEY_FN_F12		0x1dd
+#define KEY_FN_1		0x1de
+#define KEY_FN_2		0x1df
+#define KEY_FN_D		0x1e0
+#define KEY_FN_E		0x1e1
+#define KEY_FN_F		0x1e2
+#define KEY_FN_S		0x1e3
+#define KEY_FN_B		0x1e4
+
+#define KEY_BRL_DOT1		0x1f1
+#define KEY_BRL_DOT2		0x1f2
+#define KEY_BRL_DOT3		0x1f3
+#define KEY_BRL_DOT4		0x1f4
+#define KEY_BRL_DOT5		0x1f5
+#define KEY_BRL_DOT6		0x1f6
+#define KEY_BRL_DOT7		0x1f7
+#define KEY_BRL_DOT8		0x1f8
+#define KEY_BRL_DOT9		0x1f9
+#define KEY_BRL_DOT10		0x1fa
+
+#define KEY_NUMERIC_0		0x200	/* used by phones, remote controls, */
+#define KEY_NUMERIC_1		0x201	/* and other keypads */
+#define KEY_NUMERIC_2		0x202
+#define KEY_NUMERIC_3		0x203
+#define KEY_NUMERIC_4		0x204
+#define KEY_NUMERIC_5		0x205
+#define KEY_NUMERIC_6		0x206
+#define KEY_NUMERIC_7		0x207
+#define KEY_NUMERIC_8		0x208
+#define KEY_NUMERIC_9		0x209
+#define KEY_NUMERIC_STAR	0x20a
+#define KEY_NUMERIC_POUND	0x20b
+#define KEY_NUMERIC_A		0x20c	/* Phone key A - HUT Telephony 0xb9 */
+#define KEY_NUMERIC_B		0x20d
+#define KEY_NUMERIC_C		0x20e
+#define KEY_NUMERIC_D		0x20f
+
+#define KEY_CAMERA_FOCUS	0x210
+#define KEY_WPS_BUTTON		0x211	/* WiFi Protected Setup key */
+
+#define KEY_TOUCHPAD_TOGGLE	0x212	/* Request switch touchpad on or off */
+#define KEY_TOUCHPAD_ON		0x213
+#define KEY_TOUCHPAD_OFF	0x214
+
+#define KEY_CAMERA_ZOOMIN	0x215
+#define KEY_CAMERA_ZOOMOUT	0x216
+#define KEY_CAMERA_UP		0x217
+#define KEY_CAMERA_DOWN		0x218
+#define KEY_CAMERA_LEFT		0x219
+#define KEY_CAMERA_RIGHT	0x21a
+
+#define KEY_ATTENDANT_ON	0x21b
+#define KEY_ATTENDANT_OFF	0x21c
+#define KEY_ATTENDANT_TOGGLE	0x21d	/* Attendant call on or off */
+#define KEY_LIGHTS_TOGGLE	0x21e	/* Reading light on or off */
+
+#define BTN_DPAD_UP		0x220
+#define BTN_DPAD_DOWN		0x221
+#define BTN_DPAD_LEFT		0x222
+#define BTN_DPAD_RIGHT		0x223
+
+#define KEY_ALS_TOGGLE		0x230	/* Ambient light sensor */
+#define KEY_ROTATE_LOCK_TOGGLE	0x231	/* Display rotation lock */
+
+#define KEY_BUTTONCONFIG		0x240	/* AL Button Configuration */
+#define KEY_TASKMANAGER		0x241	/* AL Task/Project Manager */
+#define KEY_JOURNAL		0x242	/* AL Log/Journal/Timecard */
+#define KEY_CONTROLPANEL		0x243	/* AL Control Panel */
+#define KEY_APPSELECT		0x244	/* AL Select Task/Application */
+#define KEY_SCREENSAVER		0x245	/* AL Screen Saver */
+#define KEY_VOICECOMMAND		0x246	/* Listening Voice Command */
+#define KEY_ASSISTANT		0x247	/* AL Context-aware desktop assistant */
+
+#define KEY_BRIGHTNESS_MIN		0x250	/* Set Brightness to Minimum */
+#define KEY_BRIGHTNESS_MAX		0x251	/* Set Brightness to Maximum */
+
+#define KEY_KBDINPUTASSIST_PREV		0x260
+#define KEY_KBDINPUTASSIST_NEXT		0x261
+#define KEY_KBDINPUTASSIST_PREVGROUP		0x262
+#define KEY_KBDINPUTASSIST_NEXTGROUP		0x263
+#define KEY_KBDINPUTASSIST_ACCEPT		0x264
+#define KEY_KBDINPUTASSIST_CANCEL		0x265
+
+/* Diagonal movement keys */
+#define KEY_RIGHT_UP			0x266
+#define KEY_RIGHT_DOWN			0x267
+#define KEY_LEFT_UP			0x268
+#define KEY_LEFT_DOWN			0x269
+
+#define KEY_ROOT_MENU			0x26a /* Show Device's Root Menu */
+/* Show Top Menu of the Media (e.g. DVD) */
+#define KEY_MEDIA_TOP_MENU		0x26b
+#define KEY_NUMERIC_11			0x26c
+#define KEY_NUMERIC_12			0x26d
+/*
+ * Toggle Audio Description: refers to an audio service that helps blind and
+ * visually impaired consumers understand the action in a program. Note: in
+ * some countries this is referred to as "Video Description".
+ */
+#define KEY_AUDIO_DESC			0x26e
+#define KEY_3D_MODE			0x26f
+#define KEY_NEXT_FAVORITE		0x270
+#define KEY_STOP_RECORD			0x271
+#define KEY_PAUSE_RECORD		0x272
+#define KEY_VOD				0x273 /* Video on Demand */
+#define KEY_UNMUTE			0x274
+#define KEY_FASTREVERSE			0x275
+#define KEY_SLOWREVERSE			0x276
+/*
+ * Control a data application associated with the currently viewed channel,
+ * e.g. teletext or data broadcast application (MHEG, MHP, HbbTV, etc.)
+ */
+#define KEY_DATA			0x277
+#define KEY_ONSCREEN_KEYBOARD		0x278
+
+#define BTN_TRIGGER_HAPPY		0x2c0
+#define BTN_TRIGGER_HAPPY1		0x2c0
+#define BTN_TRIGGER_HAPPY2		0x2c1
+#define BTN_TRIGGER_HAPPY3		0x2c2
+#define BTN_TRIGGER_HAPPY4		0x2c3
+#define BTN_TRIGGER_HAPPY5		0x2c4
+#define BTN_TRIGGER_HAPPY6		0x2c5
+#define BTN_TRIGGER_HAPPY7		0x2c6
+#define BTN_TRIGGER_HAPPY8		0x2c7
+#define BTN_TRIGGER_HAPPY9		0x2c8
+#define BTN_TRIGGER_HAPPY10		0x2c9
+#define BTN_TRIGGER_HAPPY11		0x2ca
+#define BTN_TRIGGER_HAPPY12		0x2cb
+#define BTN_TRIGGER_HAPPY13		0x2cc
+#define BTN_TRIGGER_HAPPY14		0x2cd
+#define BTN_TRIGGER_HAPPY15		0x2ce
+#define BTN_TRIGGER_HAPPY16		0x2cf
+#define BTN_TRIGGER_HAPPY17		0x2d0
+#define BTN_TRIGGER_HAPPY18		0x2d1
+#define BTN_TRIGGER_HAPPY19		0x2d2
+#define BTN_TRIGGER_HAPPY20		0x2d3
+#define BTN_TRIGGER_HAPPY21		0x2d4
+#define BTN_TRIGGER_HAPPY22		0x2d5
+#define BTN_TRIGGER_HAPPY23		0x2d6
+#define BTN_TRIGGER_HAPPY24		0x2d7
+#define BTN_TRIGGER_HAPPY25		0x2d8
+#define BTN_TRIGGER_HAPPY26		0x2d9
+#define BTN_TRIGGER_HAPPY27		0x2da
+#define BTN_TRIGGER_HAPPY28		0x2db
+#define BTN_TRIGGER_HAPPY29		0x2dc
+#define BTN_TRIGGER_HAPPY30		0x2dd
+#define BTN_TRIGGER_HAPPY31		0x2de
+#define BTN_TRIGGER_HAPPY32		0x2df
+#define BTN_TRIGGER_HAPPY33		0x2e0
+#define BTN_TRIGGER_HAPPY34		0x2e1
+#define BTN_TRIGGER_HAPPY35		0x2e2
+#define BTN_TRIGGER_HAPPY36		0x2e3
+#define BTN_TRIGGER_HAPPY37		0x2e4
+#define BTN_TRIGGER_HAPPY38		0x2e5
+#define BTN_TRIGGER_HAPPY39		0x2e6
+#define BTN_TRIGGER_HAPPY40		0x2e7
+
+/* We avoid low common keys in module aliases so they don't get huge. */
+#define KEY_MIN_INTERESTING	KEY_MUTE
+#define KEY_MAX			0x2ff
+#define KEY_CNT			(KEY_MAX+1)
+
+/*
+ * Relative axes
+ */
+
+#define REL_X			0x00
+#define REL_Y			0x01
+#define REL_Z			0x02
+#define REL_RX			0x03
+#define REL_RY			0x04
+#define REL_RZ			0x05
+#define REL_HWHEEL		0x06
+#define REL_DIAL		0x07
+#define REL_WHEEL		0x08
+#define REL_MISC		0x09
+#define REL_MAX			0x0f
+#define REL_CNT			(REL_MAX+1)
+
+/*
+ * Absolute axes
+ */
+
+#define ABS_X			0x00
+#define ABS_Y			0x01
+#define ABS_Z			0x02
+#define ABS_RX			0x03
+#define ABS_RY			0x04
+#define ABS_RZ			0x05
+#define ABS_THROTTLE		0x06
+#define ABS_RUDDER		0x07
+#define ABS_WHEEL		0x08
+#define ABS_GAS			0x09
+#define ABS_BRAKE		0x0a
+#define ABS_HAT0X		0x10
+#define ABS_HAT0Y		0x11
+#define ABS_HAT1X		0x12
+#define ABS_HAT1Y		0x13
+#define ABS_HAT2X		0x14
+#define ABS_HAT2Y		0x15
+#define ABS_HAT3X		0x16
+#define ABS_HAT3Y		0x17
+#define ABS_PRESSURE		0x18
+#define ABS_DISTANCE		0x19
+#define ABS_TILT_X		0x1a
+#define ABS_TILT_Y		0x1b
+#define ABS_TOOL_WIDTH		0x1c
+
+#define ABS_VOLUME		0x20
+
+#define ABS_MISC		0x28
+
+/*
+ * 0x2e is reserved and should not be used in input drivers.
+ * It was used by HID as ABS_MISC+6 and userspace needs to detect if
+ * the next ABS_* event is correct or is just ABS_MISC + n.
+ * We define here ABS_RESERVED so userspace can rely on it and detect
+ * the situation described above.
+ */
+#define ABS_RESERVED		0x2e
+
+#define ABS_MT_SLOT		0x2f	/* MT slot being modified */
+#define ABS_MT_TOUCH_MAJOR	0x30	/* Major axis of touching ellipse */
+#define ABS_MT_TOUCH_MINOR	0x31	/* Minor axis (omit if circular) */
+#define ABS_MT_WIDTH_MAJOR	0x32	/* Major axis of approaching ellipse */
+#define ABS_MT_WIDTH_MINOR	0x33	/* Minor axis (omit if circular) */
+#define ABS_MT_ORIENTATION	0x34	/* Ellipse orientation */
+#define ABS_MT_POSITION_X	0x35	/* Center X touch position */
+#define ABS_MT_POSITION_Y	0x36	/* Center Y touch position */
+#define ABS_MT_TOOL_TYPE	0x37	/* Type of touching device */
+#define ABS_MT_BLOB_ID		0x38	/* Group a set of packets as a blob */
+#define ABS_MT_TRACKING_ID	0x39	/* Unique ID of initiated contact */
+#define ABS_MT_PRESSURE		0x3a	/* Pressure on contact area */
+#define ABS_MT_DISTANCE		0x3b	/* Contact hover distance */
+#define ABS_MT_TOOL_X		0x3c	/* Center X tool position */
+#define ABS_MT_TOOL_Y		0x3d	/* Center Y tool position */
+
+
+#define ABS_MAX			0x3f
+#define ABS_CNT			(ABS_MAX+1)
+
+/*
+ * Switch events
+ */
+
+#define SW_LID			0x00  /* set = lid shut */
+#define SW_TABLET_MODE		0x01  /* set = tablet mode */
+#define SW_HEADPHONE_INSERT	0x02  /* set = inserted */
+#define SW_RFKILL_ALL		0x03  /* rfkill master switch, type "any"
+					 set = radio enabled */
+#define SW_RADIO		SW_RFKILL_ALL	/* deprecated */
+#define SW_MICROPHONE_INSERT	0x04  /* set = inserted */
+#define SW_DOCK			0x05  /* set = plugged into dock */
+#define SW_LINEOUT_INSERT	0x06  /* set = inserted */
+#define SW_JACK_PHYSICAL_INSERT 0x07  /* set = mechanical switch set */
+#define SW_VIDEOOUT_INSERT	0x08  /* set = inserted */
+#define SW_CAMERA_LENS_COVER	0x09  /* set = lens covered */
+#define SW_KEYPAD_SLIDE		0x0a  /* set = keypad slide out */
+#define SW_FRONT_PROXIMITY	0x0b  /* set = front proximity sensor active */
+#define SW_ROTATE_LOCK		0x0c  /* set = rotate locked/disabled */
+#define SW_LINEIN_INSERT	0x0d  /* set = inserted */
+#define SW_MUTE_DEVICE		0x0e  /* set = device disabled */
+#define SW_PEN_INSERTED		0x0f  /* set = pen inserted */
+#define SW_MAX			0x0f
+#define SW_CNT			(SW_MAX+1)
+
+/*
+ * Misc events
+ */
+
+#define MSC_SERIAL		0x00
+#define MSC_PULSELED		0x01
+#define MSC_GESTURE		0x02
+#define MSC_RAW			0x03
+#define MSC_SCAN		0x04
+#define MSC_TIMESTAMP		0x05
+#define MSC_MAX			0x07
+#define MSC_CNT			(MSC_MAX+1)
+
+/*
+ * LEDs
+ */
+
+#define LED_NUML		0x00
+#define LED_CAPSL		0x01
+#define LED_SCROLLL		0x02
+#define LED_COMPOSE		0x03
+#define LED_KANA		0x04
+#define LED_SLEEP		0x05
+#define LED_SUSPEND		0x06
+#define LED_MUTE		0x07
+#define LED_MISC		0x08
+#define LED_MAIL		0x09
+#define LED_CHARGING		0x0a
+#define LED_MAX			0x0f
+#define LED_CNT			(LED_MAX+1)
+
+/*
+ * Autorepeat values
+ */
+
+#define REP_DELAY		0x00
+#define REP_PERIOD		0x01
+#define REP_MAX			0x01
+#define REP_CNT			(REP_MAX+1)
+
+/*
+ * Sounds
+ */
+
+#define SND_CLICK		0x00
+#define SND_BELL		0x01
+#define SND_TONE		0x02
+#define SND_MAX			0x07
+#define SND_CNT			(SND_MAX+1)
+
+#endif
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/input/input.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/input/input.h
new file mode 100644
index 0000000000000000000000000000000000000000..daa418607e8cf82091048585ed5f8319c372ca3b
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/input/input.h
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * This header provides constants for most input bindings.
+ *
+ * Most input bindings include key code, matrix key code format.
+ * In most cases, key code and matrix key code format uses
+ * the standard values/macro defined in this header.
+ */
+
+#ifndef _DT_BINDINGS_INPUT_INPUT_H
+#define _DT_BINDINGS_INPUT_INPUT_H
+
+#include "linux-event-codes.h"
+
+#define MATRIX_KEY(row, col, code)	\
+	((((row) & 0xFF) << 24) | (((col) & 0xFF) << 16) | ((code) & 0xFFFF))
+
+#define FT5416     0x54160002
+#define FT5426     0x54260002
+
+#endif /* _DT_BINDINGS_INPUT_INPUT_H */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/input/linux-event-codes.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/input/linux-event-codes.h
new file mode 100644
index 0000000000000000000000000000000000000000..61a5799b440b9f66758be86f4b20f6be6e877387
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/input/linux-event-codes.h
@@ -0,0 +1,851 @@
+/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
+/*
+ * Input event codes
+ *
+ *    *** IMPORTANT ***
+ * This file is not only included from C-code but also from devicetree source
+ * files. As such this file MUST only contain comments and defines.
+ *
+ * Copyright (c) 1999-2002 Vojtech Pavlik
+ * Copyright (c) 2015 Hans de Goede <hdegoede@redhat.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ */
+#ifndef _UAPI_INPUT_EVENT_CODES_H
+#define _UAPI_INPUT_EVENT_CODES_H
+
+/*
+ * Device properties and quirks
+ */
+
+#define INPUT_PROP_POINTER		0x00	/* needs a pointer */
+#define INPUT_PROP_DIRECT		0x01	/* direct input devices */
+#define INPUT_PROP_BUTTONPAD		0x02	/* has button(s) under pad */
+#define INPUT_PROP_SEMI_MT		0x03	/* touch rectangle only */
+#define INPUT_PROP_TOPBUTTONPAD		0x04	/* softbuttons at top of pad */
+#define INPUT_PROP_POINTING_STICK	0x05	/* is a pointing stick */
+#define INPUT_PROP_ACCELEROMETER	0x06	/* has accelerometer */
+
+#define INPUT_PROP_MAX			0x1f
+#define INPUT_PROP_CNT			(INPUT_PROP_MAX + 1)
+
+/*
+ * Event types
+ */
+
+#define EV_SYN			0x00
+#define EV_KEY			0x01
+#define EV_REL			0x02
+#define EV_ABS			0x03
+#define EV_MSC			0x04
+#define EV_SW			0x05
+#define EV_LED			0x11
+#define EV_SND			0x12
+#define EV_REP			0x14
+#define EV_FF			0x15
+#define EV_PWR			0x16
+#define EV_FF_STATUS		0x17
+#define EV_MAX			0x1f
+#define EV_CNT			(EV_MAX+1)
+
+/*
+ * Synchronization events.
+ */
+
+#define SYN_REPORT		0
+#define SYN_CONFIG		1
+#define SYN_MT_REPORT		2
+#define SYN_DROPPED		3
+#define SYN_MAX			0xf
+#define SYN_CNT			(SYN_MAX+1)
+
+/*
+ * Keys and buttons
+ *
+ * Most of the keys/buttons are modeled after USB HUT 1.12
+ * (see http://www.usb.org/developers/hidpage).
+ * Abbreviations in the comments:
+ * AC - Application Control
+ * AL - Application Launch Button
+ * SC - System Control
+ */
+
+#define KEY_RESERVED		0
+#define KEY_ESC			1
+#define KEY_1			2
+#define KEY_2			3
+#define KEY_3			4
+#define KEY_4			5
+#define KEY_5			6
+#define KEY_6			7
+#define KEY_7			8
+#define KEY_8			9
+#define KEY_9			10
+#define KEY_0			11
+#define KEY_MINUS		12
+#define KEY_EQUAL		13
+#define KEY_BACKSPACE		14
+#define KEY_TAB			15
+#define KEY_Q			16
+#define KEY_W			17
+#define KEY_E			18
+#define KEY_R			19
+#define KEY_T			20
+#define KEY_Y			21
+#define KEY_U			22
+#define KEY_I			23
+#define KEY_O			24
+#define KEY_P			25
+#define KEY_LEFTBRACE		26
+#define KEY_RIGHTBRACE		27
+#define KEY_ENTER		28
+#define KEY_LEFTCTRL		29
+#define KEY_A			30
+#define KEY_S			31
+#define KEY_D			32
+#define KEY_F			33
+#define KEY_G			34
+#define KEY_H			35
+#define KEY_J			36
+#define KEY_K			37
+#define KEY_L			38
+#define KEY_SEMICOLON		39
+#define KEY_APOSTROPHE		40
+#define KEY_GRAVE		41
+#define KEY_LEFTSHIFT		42
+#define KEY_BACKSLASH		43
+#define KEY_Z			44
+#define KEY_X			45
+#define KEY_C			46
+#define KEY_V			47
+#define KEY_B			48
+#define KEY_N			49
+#define KEY_M			50
+#define KEY_COMMA		51
+#define KEY_DOT			52
+#define KEY_SLASH		53
+#define KEY_RIGHTSHIFT		54
+#define KEY_KPASTERISK		55
+#define KEY_LEFTALT		56
+#define KEY_SPACE		57
+#define KEY_CAPSLOCK		58
+#define KEY_F1			59
+#define KEY_F2			60
+#define KEY_F3			61
+#define KEY_F4			62
+#define KEY_F5			63
+#define KEY_F6			64
+#define KEY_F7			65
+#define KEY_F8			66
+#define KEY_F9			67
+#define KEY_F10			68
+#define KEY_NUMLOCK		69
+#define KEY_SCROLLLOCK		70
+#define KEY_KP7			71
+#define KEY_KP8			72
+#define KEY_KP9			73
+#define KEY_KPMINUS		74
+#define KEY_KP4			75
+#define KEY_KP5			76
+#define KEY_KP6			77
+#define KEY_KPPLUS		78
+#define KEY_KP1			79
+#define KEY_KP2			80
+#define KEY_KP3			81
+#define KEY_KP0			82
+#define KEY_KPDOT		83
+
+#define KEY_ZENKAKUHANKAKU	85
+#define KEY_102ND		86
+#define KEY_F11			87
+#define KEY_F12			88
+#define KEY_RO			89
+#define KEY_KATAKANA		90
+#define KEY_HIRAGANA		91
+#define KEY_HENKAN		92
+#define KEY_KATAKANAHIRAGANA	93
+#define KEY_MUHENKAN		94
+#define KEY_KPJPCOMMA		95
+#define KEY_KPENTER		96
+#define KEY_RIGHTCTRL		97
+#define KEY_KPSLASH		98
+#define KEY_SYSRQ		99
+#define KEY_RIGHTALT		100
+#define KEY_LINEFEED		101
+#define KEY_HOME		102
+#define KEY_UP			103
+#define KEY_PAGEUP		104
+#define KEY_LEFT		105
+#define KEY_RIGHT		106
+#define KEY_END			107
+#define KEY_DOWN		108
+#define KEY_PAGEDOWN		109
+#define KEY_INSERT		110
+#define KEY_DELETE		111
+#define KEY_MACRO		112
+#define KEY_MUTE		113
+#define KEY_VOLUMEDOWN		114
+#define KEY_VOLUMEUP		115
+#define KEY_POWER		116	/* SC System Power Down */
+#define KEY_KPEQUAL		117
+#define KEY_KPPLUSMINUS		118
+#define KEY_PAUSE		119
+#define KEY_SCALE		120	/* AL Compiz Scale (Expose) */
+
+#define KEY_KPCOMMA		121
+#define KEY_HANGEUL		122
+#define KEY_HANGUEL		KEY_HANGEUL
+#define KEY_HANJA		123
+#define KEY_YEN			124
+#define KEY_LEFTMETA		125
+#define KEY_RIGHTMETA		126
+#define KEY_COMPOSE		127
+
+#define KEY_STOP		128	/* AC Stop */
+#define KEY_AGAIN		129
+#define KEY_PROPS		130	/* AC Properties */
+#define KEY_UNDO		131	/* AC Undo */
+#define KEY_FRONT		132
+#define KEY_COPY		133	/* AC Copy */
+#define KEY_OPEN		134	/* AC Open */
+#define KEY_PASTE		135	/* AC Paste */
+#define KEY_FIND		136	/* AC Search */
+#define KEY_CUT			137	/* AC Cut */
+#define KEY_HELP		138	/* AL Integrated Help Center */
+#define KEY_MENU		139	/* Menu (show menu) */
+#define KEY_CALC		140	/* AL Calculator */
+#define KEY_SETUP		141
+#define KEY_SLEEP		142	/* SC System Sleep */
+#define KEY_WAKEUP		143	/* System Wake Up */
+#define KEY_FILE		144	/* AL Local Machine Browser */
+#define KEY_SENDFILE		145
+#define KEY_DELETEFILE		146
+#define KEY_XFER		147
+#define KEY_PROG1		148
+#define KEY_PROG2		149
+#define KEY_WWW			150	/* AL Internet Browser */
+#define KEY_MSDOS		151
+#define KEY_COFFEE		152	/* AL Terminal Lock/Screensaver */
+#define KEY_SCREENLOCK		KEY_COFFEE
+#define KEY_ROTATE_DISPLAY	153	/* Display orientation for e.g. tablets */
+#define KEY_DIRECTION		KEY_ROTATE_DISPLAY
+#define KEY_CYCLEWINDOWS	154
+#define KEY_MAIL		155
+#define KEY_BOOKMARKS		156	/* AC Bookmarks */
+#define KEY_COMPUTER		157
+#define KEY_BACK		158	/* AC Back */
+#define KEY_FORWARD		159	/* AC Forward */
+#define KEY_CLOSECD		160
+#define KEY_EJECTCD		161
+#define KEY_EJECTCLOSECD	162
+#define KEY_NEXTSONG		163
+#define KEY_PLAYPAUSE		164
+#define KEY_PREVIOUSSONG	165
+#define KEY_STOPCD		166
+#define KEY_RECORD		167
+#define KEY_REWIND		168
+#define KEY_PHONE		169	/* Media Select Telephone */
+#define KEY_ISO			170
+#define KEY_CONFIG		171	/* AL Consumer Control Configuration */
+#define KEY_HOMEPAGE		172	/* AC Home */
+#define KEY_REFRESH		173	/* AC Refresh */
+#define KEY_EXIT		174	/* AC Exit */
+#define KEY_MOVE		175
+#define KEY_EDIT		176
+#define KEY_SCROLLUP		177
+#define KEY_SCROLLDOWN		178
+#define KEY_KPLEFTPAREN		179
+#define KEY_KPRIGHTPAREN	180
+#define KEY_NEW			181	/* AC New */
+#define KEY_REDO		182	/* AC Redo/Repeat */
+
+#define KEY_F13			183
+#define KEY_F14			184
+#define KEY_F15			185
+#define KEY_F16			186
+#define KEY_F17			187
+#define KEY_F18			188
+#define KEY_F19			189
+#define KEY_F20			190
+#define KEY_F21			191
+#define KEY_F22			192
+#define KEY_F23			193
+#define KEY_F24			194
+
+#define KEY_PLAYCD		200
+#define KEY_PAUSECD		201
+#define KEY_PROG3		202
+#define KEY_PROG4		203
+#define KEY_DASHBOARD		204	/* AL Dashboard */
+#define KEY_SUSPEND		205
+#define KEY_CLOSE		206	/* AC Close */
+#define KEY_PLAY		207
+#define KEY_FASTFORWARD		208
+#define KEY_BASSBOOST		209
+#define KEY_PRINT		210	/* AC Print */
+#define KEY_HP			211
+#define KEY_CAMERA		212
+#define KEY_SOUND		213
+#define KEY_QUESTION		214
+#define KEY_EMAIL		215
+#define KEY_CHAT		216
+#define KEY_SEARCH		217
+#define KEY_CONNECT		218
+#define KEY_FINANCE		219	/* AL Checkbook/Finance */
+#define KEY_SPORT		220
+#define KEY_SHOP		221
+#define KEY_ALTERASE		222
+#define KEY_CANCEL		223	/* AC Cancel */
+#define KEY_BRIGHTNESSDOWN	224
+#define KEY_BRIGHTNESSUP	225
+#define KEY_MEDIA		226
+
+#define KEY_SWITCHVIDEOMODE	227	/* Cycle between available video
+					   outputs (Monitor/LCD/TV-out/etc) */
+#define KEY_KBDILLUMTOGGLE	228
+#define KEY_KBDILLUMDOWN	229
+#define KEY_KBDILLUMUP		230
+
+#define KEY_SEND		231	/* AC Send */
+#define KEY_REPLY		232	/* AC Reply */
+#define KEY_FORWARDMAIL		233	/* AC Forward Msg */
+#define KEY_SAVE		234	/* AC Save */
+#define KEY_DOCUMENTS		235
+
+#define KEY_BATTERY		236
+
+#define KEY_BLUETOOTH		237
+#define KEY_WLAN		238
+#define KEY_UWB			239
+
+#define KEY_UNKNOWN		240
+
+#define KEY_VIDEO_NEXT		241	/* drive next video source */
+#define KEY_VIDEO_PREV		242	/* drive previous video source */
+#define KEY_BRIGHTNESS_CYCLE	243	/* brightness up, after max is min */
+#define KEY_BRIGHTNESS_AUTO	244	/* Set Auto Brightness: manual
+					  brightness control is off,
+					  rely on ambient */
+#define KEY_BRIGHTNESS_ZERO	KEY_BRIGHTNESS_AUTO
+#define KEY_DISPLAY_OFF		245	/* display device to off state */
+
+#define KEY_WWAN		246	/* Wireless WAN (LTE, UMTS, GSM, etc.) */
+#define KEY_WIMAX		KEY_WWAN
+#define KEY_RFKILL		247	/* Key that controls all radios */
+
+#define KEY_MICMUTE		248	/* Mute / unmute the microphone */
+
+/* Code 255 is reserved for special needs of AT keyboard driver */
+
+#define BTN_MISC		0x100
+#define BTN_0			0x100
+#define BTN_1			0x101
+#define BTN_2			0x102
+#define BTN_3			0x103
+#define BTN_4			0x104
+#define BTN_5			0x105
+#define BTN_6			0x106
+#define BTN_7			0x107
+#define BTN_8			0x108
+#define BTN_9			0x109
+
+#define BTN_MOUSE		0x110
+#define BTN_LEFT		0x110
+#define BTN_RIGHT		0x111
+#define BTN_MIDDLE		0x112
+#define BTN_SIDE		0x113
+#define BTN_EXTRA		0x114
+#define BTN_FORWARD		0x115
+#define BTN_BACK		0x116
+#define BTN_TASK		0x117
+
+#define BTN_JOYSTICK		0x120
+#define BTN_TRIGGER		0x120
+#define BTN_THUMB		0x121
+#define BTN_THUMB2		0x122
+#define BTN_TOP			0x123
+#define BTN_TOP2		0x124
+#define BTN_PINKIE		0x125
+#define BTN_BASE		0x126
+#define BTN_BASE2		0x127
+#define BTN_BASE3		0x128
+#define BTN_BASE4		0x129
+#define BTN_BASE5		0x12a
+#define BTN_BASE6		0x12b
+#define BTN_DEAD		0x12f
+
+#define BTN_GAMEPAD		0x130
+#define BTN_SOUTH		0x130
+#define BTN_A			BTN_SOUTH
+#define BTN_EAST		0x131
+#define BTN_B			BTN_EAST
+#define BTN_C			0x132
+#define BTN_NORTH		0x133
+#define BTN_X			BTN_NORTH
+#define BTN_WEST		0x134
+#define BTN_Y			BTN_WEST
+#define BTN_Z			0x135
+#define BTN_TL			0x136
+#define BTN_TR			0x137
+#define BTN_TL2			0x138
+#define BTN_TR2			0x139
+#define BTN_SELECT		0x13a
+#define BTN_START		0x13b
+#define BTN_MODE		0x13c
+#define BTN_THUMBL		0x13d
+#define BTN_THUMBR		0x13e
+
+#define BTN_DIGI		0x140
+#define BTN_TOOL_PEN		0x140
+#define BTN_TOOL_RUBBER		0x141
+#define BTN_TOOL_BRUSH		0x142
+#define BTN_TOOL_PENCIL		0x143
+#define BTN_TOOL_AIRBRUSH	0x144
+#define BTN_TOOL_FINGER		0x145
+#define BTN_TOOL_MOUSE		0x146
+#define BTN_TOOL_LENS		0x147
+#define BTN_TOOL_QUINTTAP	0x148	/* Five fingers on trackpad */
+#define BTN_STYLUS3		0x149
+#define BTN_TOUCH		0x14a
+#define BTN_STYLUS		0x14b
+#define BTN_STYLUS2		0x14c
+#define BTN_TOOL_DOUBLETAP	0x14d
+#define BTN_TOOL_TRIPLETAP	0x14e
+#define BTN_TOOL_QUADTAP	0x14f	/* Four fingers on trackpad */
+
+#define BTN_WHEEL		0x150
+#define BTN_GEAR_DOWN		0x150
+#define BTN_GEAR_UP		0x151
+
+#define KEY_OK			0x160
+#define KEY_SELECT		0x161
+#define KEY_GOTO		0x162
+#define KEY_CLEAR		0x163
+#define KEY_POWER2		0x164
+#define KEY_OPTION		0x165
+#define KEY_INFO		0x166	/* AL OEM Features/Tips/Tutorial */
+#define KEY_TIME		0x167
+#define KEY_VENDOR		0x168
+#define KEY_ARCHIVE		0x169
+#define KEY_PROGRAM		0x16a	/* Media Select Program Guide */
+#define KEY_CHANNEL		0x16b
+#define KEY_FAVORITES		0x16c
+#define KEY_EPG			0x16d
+#define KEY_PVR			0x16e	/* Media Select Home */
+#define KEY_MHP			0x16f
+#define KEY_LANGUAGE		0x170
+#define KEY_TITLE		0x171
+#define KEY_SUBTITLE		0x172
+#define KEY_ANGLE		0x173
+#define KEY_ZOOM		0x174
+#define KEY_MODE		0x175
+#define KEY_KEYBOARD		0x176
+#define KEY_SCREEN		0x177
+#define KEY_PC			0x178	/* Media Select Computer */
+#define KEY_TV			0x179	/* Media Select TV */
+#define KEY_TV2			0x17a	/* Media Select Cable */
+#define KEY_VCR			0x17b	/* Media Select VCR */
+#define KEY_VCR2		0x17c	/* VCR Plus */
+#define KEY_SAT			0x17d	/* Media Select Satellite */
+#define KEY_SAT2		0x17e
+#define KEY_CD			0x17f	/* Media Select CD */
+#define KEY_TAPE		0x180	/* Media Select Tape */
+#define KEY_RADIO		0x181
+#define KEY_TUNER		0x182	/* Media Select Tuner */
+#define KEY_PLAYER		0x183
+#define KEY_TEXT		0x184
+#define KEY_DVD			0x185	/* Media Select DVD */
+#define KEY_AUX			0x186
+#define KEY_MP3			0x187
+#define KEY_AUDIO		0x188	/* AL Audio Browser */
+#define KEY_VIDEO		0x189	/* AL Movie Browser */
+#define KEY_DIRECTORY		0x18a
+#define KEY_LIST		0x18b
+#define KEY_MEMO		0x18c	/* Media Select Messages */
+#define KEY_CALENDAR		0x18d
+#define KEY_RED			0x18e
+#define KEY_GREEN		0x18f
+#define KEY_YELLOW		0x190
+#define KEY_BLUE		0x191
+#define KEY_CHANNELUP		0x192	/* Channel Increment */
+#define KEY_CHANNELDOWN		0x193	/* Channel Decrement */
+#define KEY_FIRST		0x194
+#define KEY_LAST		0x195	/* Recall Last */
+#define KEY_AB			0x196
+#define KEY_NEXT		0x197
+#define KEY_RESTART		0x198
+#define KEY_SLOW		0x199
+#define KEY_SHUFFLE		0x19a
+#define KEY_BREAK		0x19b
+#define KEY_PREVIOUS		0x19c
+#define KEY_DIGITS		0x19d
+#define KEY_TEEN		0x19e
+#define KEY_TWEN		0x19f
+#define KEY_VIDEOPHONE		0x1a0	/* Media Select Video Phone */
+#define KEY_GAMES		0x1a1	/* Media Select Games */
+#define KEY_ZOOMIN		0x1a2	/* AC Zoom In */
+#define KEY_ZOOMOUT		0x1a3	/* AC Zoom Out */
+#define KEY_ZOOMRESET		0x1a4	/* AC Zoom */
+#define KEY_WORDPROCESSOR	0x1a5	/* AL Word Processor */
+#define KEY_EDITOR		0x1a6	/* AL Text Editor */
+#define KEY_SPREADSHEET		0x1a7	/* AL Spreadsheet */
+#define KEY_GRAPHICSEDITOR	0x1a8	/* AL Graphics Editor */
+#define KEY_PRESENTATION	0x1a9	/* AL Presentation App */
+#define KEY_DATABASE		0x1aa	/* AL Database App */
+#define KEY_NEWS		0x1ab	/* AL Newsreader */
+#define KEY_VOICEMAIL		0x1ac	/* AL Voicemail */
+#define KEY_ADDRESSBOOK		0x1ad	/* AL Contacts/Address Book */
+#define KEY_MESSENGER		0x1ae	/* AL Instant Messaging */
+#define KEY_DISPLAYTOGGLE	0x1af	/* Turn display (LCD) on and off */
+#define KEY_BRIGHTNESS_TOGGLE	KEY_DISPLAYTOGGLE
+#define KEY_SPELLCHECK		0x1b0   /* AL Spell Check */
+#define KEY_LOGOFF		0x1b1   /* AL Logoff */
+
+#define KEY_DOLLAR		0x1b2
+#define KEY_EURO		0x1b3
+
+#define KEY_FRAMEBACK		0x1b4	/* Consumer - transport controls */
+#define KEY_FRAMEFORWARD	0x1b5
+#define KEY_CONTEXT_MENU	0x1b6	/* GenDesc - system context menu */
+#define KEY_MEDIA_REPEAT	0x1b7	/* Consumer - transport control */
+#define KEY_10CHANNELSUP	0x1b8	/* 10 channels up (10+) */
+#define KEY_10CHANNELSDOWN	0x1b9	/* 10 channels down (10-) */
+#define KEY_IMAGES		0x1ba	/* AL Image Browser */
+
+#define KEY_DEL_EOL		0x1c0
+#define KEY_DEL_EOS		0x1c1
+#define KEY_INS_LINE		0x1c2
+#define KEY_DEL_LINE		0x1c3
+
+#define KEY_FN			0x1d0
+#define KEY_FN_ESC		0x1d1
+#define KEY_FN_F1		0x1d2
+#define KEY_FN_F2		0x1d3
+#define KEY_FN_F3		0x1d4
+#define KEY_FN_F4		0x1d5
+#define KEY_FN_F5		0x1d6
+#define KEY_FN_F6		0x1d7
+#define KEY_FN_F7		0x1d8
+#define KEY_FN_F8		0x1d9
+#define KEY_FN_F9		0x1da
+#define KEY_FN_F10		0x1db
+#define KEY_FN_F11		0x1dc
+#define KEY_FN_F12		0x1dd
+#define KEY_FN_1		0x1de
+#define KEY_FN_2		0x1df
+#define KEY_FN_D		0x1e0
+#define KEY_FN_E		0x1e1
+#define KEY_FN_F		0x1e2
+#define KEY_FN_S		0x1e3
+#define KEY_FN_B		0x1e4
+
+#define KEY_BRL_DOT1		0x1f1
+#define KEY_BRL_DOT2		0x1f2
+#define KEY_BRL_DOT3		0x1f3
+#define KEY_BRL_DOT4		0x1f4
+#define KEY_BRL_DOT5		0x1f5
+#define KEY_BRL_DOT6		0x1f6
+#define KEY_BRL_DOT7		0x1f7
+#define KEY_BRL_DOT8		0x1f8
+#define KEY_BRL_DOT9		0x1f9
+#define KEY_BRL_DOT10		0x1fa
+
+#define KEY_NUMERIC_0		0x200	/* used by phones, remote controls, */
+#define KEY_NUMERIC_1		0x201	/* and other keypads */
+#define KEY_NUMERIC_2		0x202
+#define KEY_NUMERIC_3		0x203
+#define KEY_NUMERIC_4		0x204
+#define KEY_NUMERIC_5		0x205
+#define KEY_NUMERIC_6		0x206
+#define KEY_NUMERIC_7		0x207
+#define KEY_NUMERIC_8		0x208
+#define KEY_NUMERIC_9		0x209
+#define KEY_NUMERIC_STAR	0x20a
+#define KEY_NUMERIC_POUND	0x20b
+#define KEY_NUMERIC_A		0x20c	/* Phone key A - HUT Telephony 0xb9 */
+#define KEY_NUMERIC_B		0x20d
+#define KEY_NUMERIC_C		0x20e
+#define KEY_NUMERIC_D		0x20f
+
+#define KEY_CAMERA_FOCUS	0x210
+#define KEY_WPS_BUTTON		0x211	/* WiFi Protected Setup key */
+
+#define KEY_TOUCHPAD_TOGGLE	0x212	/* Request switch touchpad on or off */
+#define KEY_TOUCHPAD_ON		0x213
+#define KEY_TOUCHPAD_OFF	0x214
+
+#define KEY_CAMERA_ZOOMIN	0x215
+#define KEY_CAMERA_ZOOMOUT	0x216
+#define KEY_CAMERA_UP		0x217
+#define KEY_CAMERA_DOWN		0x218
+#define KEY_CAMERA_LEFT		0x219
+#define KEY_CAMERA_RIGHT	0x21a
+
+#define KEY_ATTENDANT_ON	0x21b
+#define KEY_ATTENDANT_OFF	0x21c
+#define KEY_ATTENDANT_TOGGLE	0x21d	/* Attendant call on or off */
+#define KEY_LIGHTS_TOGGLE	0x21e	/* Reading light on or off */
+
+#define BTN_DPAD_UP		0x220
+#define BTN_DPAD_DOWN		0x221
+#define BTN_DPAD_LEFT		0x222
+#define BTN_DPAD_RIGHT		0x223
+
+#define KEY_ALS_TOGGLE		0x230	/* Ambient light sensor */
+#define KEY_ROTATE_LOCK_TOGGLE	0x231	/* Display rotation lock */
+
+#define KEY_BUTTONCONFIG		0x240	/* AL Button Configuration */
+#define KEY_TASKMANAGER		0x241	/* AL Task/Project Manager */
+#define KEY_JOURNAL		0x242	/* AL Log/Journal/Timecard */
+#define KEY_CONTROLPANEL		0x243	/* AL Control Panel */
+#define KEY_APPSELECT		0x244	/* AL Select Task/Application */
+#define KEY_SCREENSAVER		0x245	/* AL Screen Saver */
+#define KEY_VOICECOMMAND		0x246	/* Listening Voice Command */
+#define KEY_ASSISTANT		0x247	/* AL Context-aware desktop assistant */
+
+#define KEY_BRIGHTNESS_MIN		0x250	/* Set Brightness to Minimum */
+#define KEY_BRIGHTNESS_MAX		0x251	/* Set Brightness to Maximum */
+
+#define KEY_KBDINPUTASSIST_PREV		0x260
+#define KEY_KBDINPUTASSIST_NEXT		0x261
+#define KEY_KBDINPUTASSIST_PREVGROUP		0x262
+#define KEY_KBDINPUTASSIST_NEXTGROUP		0x263
+#define KEY_KBDINPUTASSIST_ACCEPT		0x264
+#define KEY_KBDINPUTASSIST_CANCEL		0x265
+
+/* Diagonal movement keys */
+#define KEY_RIGHT_UP			0x266
+#define KEY_RIGHT_DOWN			0x267
+#define KEY_LEFT_UP			0x268
+#define KEY_LEFT_DOWN			0x269
+
+#define KEY_ROOT_MENU			0x26a /* Show Device's Root Menu */
+/* Show Top Menu of the Media (e.g. DVD) */
+#define KEY_MEDIA_TOP_MENU		0x26b
+#define KEY_NUMERIC_11			0x26c
+#define KEY_NUMERIC_12			0x26d
+/*
+ * Toggle Audio Description: refers to an audio service that helps blind and
+ * visually impaired consumers understand the action in a program. Note: in
+ * some countries this is referred to as "Video Description".
+ */
+#define KEY_AUDIO_DESC			0x26e
+#define KEY_3D_MODE			0x26f
+#define KEY_NEXT_FAVORITE		0x270
+#define KEY_STOP_RECORD			0x271
+#define KEY_PAUSE_RECORD		0x272
+#define KEY_VOD				0x273 /* Video on Demand */
+#define KEY_UNMUTE			0x274
+#define KEY_FASTREVERSE			0x275
+#define KEY_SLOWREVERSE			0x276
+/*
+ * Control a data application associated with the currently viewed channel,
+ * e.g. teletext or data broadcast application (MHEG, MHP, HbbTV, etc.)
+ */
+#define KEY_DATA			0x277
+#define KEY_ONSCREEN_KEYBOARD		0x278
+
+#define BTN_TRIGGER_HAPPY		0x2c0
+#define BTN_TRIGGER_HAPPY1		0x2c0
+#define BTN_TRIGGER_HAPPY2		0x2c1
+#define BTN_TRIGGER_HAPPY3		0x2c2
+#define BTN_TRIGGER_HAPPY4		0x2c3
+#define BTN_TRIGGER_HAPPY5		0x2c4
+#define BTN_TRIGGER_HAPPY6		0x2c5
+#define BTN_TRIGGER_HAPPY7		0x2c6
+#define BTN_TRIGGER_HAPPY8		0x2c7
+#define BTN_TRIGGER_HAPPY9		0x2c8
+#define BTN_TRIGGER_HAPPY10		0x2c9
+#define BTN_TRIGGER_HAPPY11		0x2ca
+#define BTN_TRIGGER_HAPPY12		0x2cb
+#define BTN_TRIGGER_HAPPY13		0x2cc
+#define BTN_TRIGGER_HAPPY14		0x2cd
+#define BTN_TRIGGER_HAPPY15		0x2ce
+#define BTN_TRIGGER_HAPPY16		0x2cf
+#define BTN_TRIGGER_HAPPY17		0x2d0
+#define BTN_TRIGGER_HAPPY18		0x2d1
+#define BTN_TRIGGER_HAPPY19		0x2d2
+#define BTN_TRIGGER_HAPPY20		0x2d3
+#define BTN_TRIGGER_HAPPY21		0x2d4
+#define BTN_TRIGGER_HAPPY22		0x2d5
+#define BTN_TRIGGER_HAPPY23		0x2d6
+#define BTN_TRIGGER_HAPPY24		0x2d7
+#define BTN_TRIGGER_HAPPY25		0x2d8
+#define BTN_TRIGGER_HAPPY26		0x2d9
+#define BTN_TRIGGER_HAPPY27		0x2da
+#define BTN_TRIGGER_HAPPY28		0x2db
+#define BTN_TRIGGER_HAPPY29		0x2dc
+#define BTN_TRIGGER_HAPPY30		0x2dd
+#define BTN_TRIGGER_HAPPY31		0x2de
+#define BTN_TRIGGER_HAPPY32		0x2df
+#define BTN_TRIGGER_HAPPY33		0x2e0
+#define BTN_TRIGGER_HAPPY34		0x2e1
+#define BTN_TRIGGER_HAPPY35		0x2e2
+#define BTN_TRIGGER_HAPPY36		0x2e3
+#define BTN_TRIGGER_HAPPY37		0x2e4
+#define BTN_TRIGGER_HAPPY38		0x2e5
+#define BTN_TRIGGER_HAPPY39		0x2e6
+#define BTN_TRIGGER_HAPPY40		0x2e7
+
+/* We avoid low common keys in module aliases so they don't get huge. */
+#define KEY_MIN_INTERESTING	KEY_MUTE
+#define KEY_MAX			0x2ff
+#define KEY_CNT			(KEY_MAX+1)
+
+/*
+ * Relative axes
+ */
+
+#define REL_X			0x00
+#define REL_Y			0x01
+#define REL_Z			0x02
+#define REL_RX			0x03
+#define REL_RY			0x04
+#define REL_RZ			0x05
+#define REL_HWHEEL		0x06
+#define REL_DIAL		0x07
+#define REL_WHEEL		0x08
+#define REL_MISC		0x09
+#define REL_MAX			0x0f
+#define REL_CNT			(REL_MAX+1)
+
+/*
+ * Absolute axes
+ */
+
+#define ABS_X			0x00
+#define ABS_Y			0x01
+#define ABS_Z			0x02
+#define ABS_RX			0x03
+#define ABS_RY			0x04
+#define ABS_RZ			0x05
+#define ABS_THROTTLE		0x06
+#define ABS_RUDDER		0x07
+#define ABS_WHEEL		0x08
+#define ABS_GAS			0x09
+#define ABS_BRAKE		0x0a
+#define ABS_HAT0X		0x10
+#define ABS_HAT0Y		0x11
+#define ABS_HAT1X		0x12
+#define ABS_HAT1Y		0x13
+#define ABS_HAT2X		0x14
+#define ABS_HAT2Y		0x15
+#define ABS_HAT3X		0x16
+#define ABS_HAT3Y		0x17
+#define ABS_PRESSURE		0x18
+#define ABS_DISTANCE		0x19
+#define ABS_TILT_X		0x1a
+#define ABS_TILT_Y		0x1b
+#define ABS_TOOL_WIDTH		0x1c
+
+#define ABS_VOLUME		0x20
+
+#define ABS_MISC		0x28
+
+/*
+ * 0x2e is reserved and should not be used in input drivers.
+ * It was used by HID as ABS_MISC+6 and userspace needs to detect if
+ * the next ABS_* event is correct or is just ABS_MISC + n.
+ * We define here ABS_RESERVED so userspace can rely on it and detect
+ * the situation described above.
+ */
+#define ABS_RESERVED		0x2e
+
+#define ABS_MT_SLOT		0x2f	/* MT slot being modified */
+#define ABS_MT_TOUCH_MAJOR	0x30	/* Major axis of touching ellipse */
+#define ABS_MT_TOUCH_MINOR	0x31	/* Minor axis (omit if circular) */
+#define ABS_MT_WIDTH_MAJOR	0x32	/* Major axis of approaching ellipse */
+#define ABS_MT_WIDTH_MINOR	0x33	/* Minor axis (omit if circular) */
+#define ABS_MT_ORIENTATION	0x34	/* Ellipse orientation */
+#define ABS_MT_POSITION_X	0x35	/* Center X touch position */
+#define ABS_MT_POSITION_Y	0x36	/* Center Y touch position */
+#define ABS_MT_TOOL_TYPE	0x37	/* Type of touching device */
+#define ABS_MT_BLOB_ID		0x38	/* Group a set of packets as a blob */
+#define ABS_MT_TRACKING_ID	0x39	/* Unique ID of initiated contact */
+#define ABS_MT_PRESSURE		0x3a	/* Pressure on contact area */
+#define ABS_MT_DISTANCE		0x3b	/* Contact hover distance */
+#define ABS_MT_TOOL_X		0x3c	/* Center X tool position */
+#define ABS_MT_TOOL_Y		0x3d	/* Center Y tool position */
+
+
+#define ABS_MAX			0x3f
+#define ABS_CNT			(ABS_MAX+1)
+
+/*
+ * Switch events
+ */
+
+#define SW_LID			0x00  /* set = lid shut */
+#define SW_TABLET_MODE		0x01  /* set = tablet mode */
+#define SW_HEADPHONE_INSERT	0x02  /* set = inserted */
+#define SW_RFKILL_ALL		0x03  /* rfkill master switch, type "any"
+					 set = radio enabled */
+#define SW_RADIO		SW_RFKILL_ALL	/* deprecated */
+#define SW_MICROPHONE_INSERT	0x04  /* set = inserted */
+#define SW_DOCK			0x05  /* set = plugged into dock */
+#define SW_LINEOUT_INSERT	0x06  /* set = inserted */
+#define SW_JACK_PHYSICAL_INSERT 0x07  /* set = mechanical switch set */
+#define SW_VIDEOOUT_INSERT	0x08  /* set = inserted */
+#define SW_CAMERA_LENS_COVER	0x09  /* set = lens covered */
+#define SW_KEYPAD_SLIDE		0x0a  /* set = keypad slide out */
+#define SW_FRONT_PROXIMITY	0x0b  /* set = front proximity sensor active */
+#define SW_ROTATE_LOCK		0x0c  /* set = rotate locked/disabled */
+#define SW_LINEIN_INSERT	0x0d  /* set = inserted */
+#define SW_MUTE_DEVICE		0x0e  /* set = device disabled */
+#define SW_PEN_INSERTED		0x0f  /* set = pen inserted */
+#define SW_MAX			0x0f
+#define SW_CNT			(SW_MAX+1)
+
+/*
+ * Misc events
+ */
+
+#define MSC_SERIAL		0x00
+#define MSC_PULSELED		0x01
+#define MSC_GESTURE		0x02
+#define MSC_RAW			0x03
+#define MSC_SCAN		0x04
+#define MSC_TIMESTAMP		0x05
+#define MSC_MAX			0x07
+#define MSC_CNT			(MSC_MAX+1)
+
+/*
+ * LEDs
+ */
+
+#define LED_NUML		0x00
+#define LED_CAPSL		0x01
+#define LED_SCROLLL		0x02
+#define LED_COMPOSE		0x03
+#define LED_KANA		0x04
+#define LED_SLEEP		0x05
+#define LED_SUSPEND		0x06
+#define LED_MUTE		0x07
+#define LED_MISC		0x08
+#define LED_MAIL		0x09
+#define LED_CHARGING		0x0a
+#define LED_MAX			0x0f
+#define LED_CNT			(LED_MAX+1)
+
+/*
+ * Autorepeat values
+ */
+
+#define REP_DELAY		0x00
+#define REP_PERIOD		0x01
+#define REP_MAX			0x01
+#define REP_CNT			(REP_MAX+1)
+
+/*
+ * Sounds
+ */
+
+#define SND_CLICK		0x00
+#define SND_BELL		0x01
+#define SND_TONE		0x02
+#define SND_MAX			0x07
+#define SND_CNT			(SND_MAX+1)
+
+#endif
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/input/ti-drv260x.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/input/ti-drv260x.h
new file mode 100644
index 0000000000000000000000000000000000000000..2626e6d9f7078ab9a3efd4e214b96f3fcde1cd2f
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/input/ti-drv260x.h
@@ -0,0 +1,36 @@
+/*
+ * DRV260X haptics driver family
+ *
+ * Author: Dan Murphy <dmurphy@ti.com>
+ *
+ * Copyright:   (C) 2014 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_TI_DRV260X_H
+#define _DT_BINDINGS_TI_DRV260X_H
+
+/* Calibration Types */
+#define DRV260X_LRA_MODE		0x00
+#define DRV260X_LRA_NO_CAL_MODE	0x01
+#define DRV260X_ERM_MODE		0x02
+
+/* Library Selection */
+#define DRV260X_LIB_EMPTY			0x00
+#define DRV260X_ERM_LIB_A			0x01
+#define DRV260X_ERM_LIB_B			0x02
+#define DRV260X_ERM_LIB_C			0x03
+#define DRV260X_ERM_LIB_D			0x04
+#define DRV260X_ERM_LIB_E			0x05
+#define DRV260X_LIB_LRA			0x06
+#define DRV260X_ERM_LIB_F			0x07
+
+#endif
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/interrupt-controller/arm-gic.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/interrupt-controller/arm-gic.h
new file mode 100644
index 0000000000000000000000000000000000000000..0c85f65c81c7da2554f65e7702b1d053df3f6b06
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/interrupt-controller/arm-gic.h
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * This header provides constants for the ARM GIC.
+ */
+
+#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_ARM_GIC_H
+#define _DT_BINDINGS_INTERRUPT_CONTROLLER_ARM_GIC_H
+
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/* interrupt specifier cell 0 */
+
+#define GIC_SPI 0
+#define GIC_PPI 1
+
+/*
+ * Interrupt specifier cell 2.
+ * The flags in irq.h are valid, plus those below.
+ */
+#define GIC_CPU_MASK_RAW(x) ((x) << 8)
+#define GIC_CPU_MASK_SIMPLE(num) GIC_CPU_MASK_RAW((1 << (num)) - 1)
+
+#endif
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/interrupt-controller/irq-st.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/interrupt-controller/irq-st.h
new file mode 100644
index 0000000000000000000000000000000000000000..4c59aceb9be006498aeae2997916d830e8d50309
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/interrupt-controller/irq-st.h
@@ -0,0 +1,30 @@
+/*
+ *  include/linux/irqchip/irq-st.h
+ *
+ *  Copyright (C) 2014 STMicroelectronics – All Rights Reserved
+ *
+ *  Author: Lee Jones <lee.jones@linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_ST_H
+#define _DT_BINDINGS_INTERRUPT_CONTROLLER_ST_H
+
+#define ST_IRQ_SYSCFG_EXT_0		0
+#define ST_IRQ_SYSCFG_EXT_1		1
+#define ST_IRQ_SYSCFG_EXT_2		2
+#define ST_IRQ_SYSCFG_CTI_0		3
+#define ST_IRQ_SYSCFG_CTI_1		4
+#define ST_IRQ_SYSCFG_PMU_0		5
+#define ST_IRQ_SYSCFG_PMU_1		6
+#define ST_IRQ_SYSCFG_pl310_L2		7
+#define ST_IRQ_SYSCFG_DISABLED		0xFFFFFFFF
+
+#define ST_IRQ_SYSCFG_EXT_1_INV		0x1
+#define ST_IRQ_SYSCFG_EXT_2_INV		0x2
+#define ST_IRQ_SYSCFG_EXT_3_INV		0x4
+
+#endif
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/interrupt-controller/irq.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/interrupt-controller/irq.h
new file mode 100644
index 0000000000000000000000000000000000000000..9e3d183e138191fe5227cb5ffc5ff52d81036b15
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/interrupt-controller/irq.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0 OR MIT */
+/*
+ * This header provides constants for most IRQ bindings.
+ *
+ * Most IRQ bindings include a flags cell as part of the IRQ specifier.
+ * In most cases, the format of the flags cell uses the standard values
+ * defined in this header.
+ */
+
+#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_IRQ_H
+#define _DT_BINDINGS_INTERRUPT_CONTROLLER_IRQ_H
+
+#define IRQ_TYPE_NONE		0
+#define IRQ_TYPE_EDGE_RISING	1
+#define IRQ_TYPE_EDGE_FALLING	2
+#define IRQ_TYPE_EDGE_BOTH	(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)
+#define IRQ_TYPE_LEVEL_HIGH	4
+#define IRQ_TYPE_LEVEL_LOW	8
+
+#endif
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/interrupt-controller/mips-gic.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/interrupt-controller/mips-gic.h
new file mode 100644
index 0000000000000000000000000000000000000000..bd45cee0c3f05bea9df7262e8b457d06860ab88e
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/interrupt-controller/mips-gic.h
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_MIPS_GIC_H
+#define _DT_BINDINGS_INTERRUPT_CONTROLLER_MIPS_GIC_H
+
+#include <dt-bindings/interrupt-controller/irq.h>
+
+#define GIC_SHARED 0
+#define GIC_LOCAL 1
+
+#endif
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/interrupt-controller/mvebu-icu.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/interrupt-controller/mvebu-icu.h
new file mode 100644
index 0000000000000000000000000000000000000000..bb5217c64206a3eccd53442639395d2516427fea
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/interrupt-controller/mvebu-icu.h
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * This header provides constants for the MVEBU ICU driver.
+ */
+
+#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_MVEBU_ICU_H
+#define _DT_BINDINGS_INTERRUPT_CONTROLLER_MVEBU_ICU_H
+
+/* interrupt specifier cell 0 */
+
+#define ICU_GRP_NSR		0x0
+#define ICU_GRP_SR		0x1
+#define ICU_GRP_SEI		0x4
+#define ICU_GRP_REI		0x5
+
+#endif
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/pinctrl/am33xx.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/pinctrl/am33xx.h
new file mode 100644
index 0000000000000000000000000000000000000000..17877e85980b290137d12f23a08cf41e743d2325
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/pinctrl/am33xx.h
@@ -0,0 +1,172 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * This header provides constants specific to AM33XX pinctrl bindings.
+ */
+
+#ifndef _DT_BINDINGS_PINCTRL_AM33XX_H
+#define _DT_BINDINGS_PINCTRL_AM33XX_H
+
+#include <dt-bindings/pinctrl/omap.h>
+
+/* am33xx specific mux bit defines */
+#undef PULL_ENA
+#undef INPUT_EN
+
+#define PULL_DISABLE		(1 << 3)
+#define INPUT_EN		(1 << 5)
+#define SLEWCTRL_SLOW		(1 << 6)
+#define SLEWCTRL_FAST		0
+
+/* update macro depending on INPUT_EN and PULL_ENA */
+#undef PIN_OUTPUT
+#undef PIN_OUTPUT_PULLUP
+#undef PIN_OUTPUT_PULLDOWN
+#undef PIN_INPUT
+#undef PIN_INPUT_PULLUP
+#undef PIN_INPUT_PULLDOWN
+
+#define PIN_OUTPUT		(PULL_DISABLE)
+#define PIN_OUTPUT_PULLUP	(PULL_UP)
+#define PIN_OUTPUT_PULLDOWN	0
+#define PIN_INPUT		(INPUT_EN | PULL_DISABLE)
+#define PIN_INPUT_PULLUP	(INPUT_EN | PULL_UP)
+#define PIN_INPUT_PULLDOWN	(INPUT_EN)
+
+/* undef non-existing modes */
+#undef PIN_OFF_NONE
+#undef PIN_OFF_OUTPUT_HIGH
+#undef PIN_OFF_OUTPUT_LOW
+#undef PIN_OFF_INPUT_PULLUP
+#undef PIN_OFF_INPUT_PULLDOWN
+#undef PIN_OFF_WAKEUPENABLE
+
+#define AM335X_PIN_OFFSET_MIN			0x0800U
+
+#define AM335X_PIN_GPMC_AD0			0x800
+#define AM335X_PIN_GPMC_AD1			0x804
+#define AM335X_PIN_GPMC_AD2			0x808
+#define AM335X_PIN_GPMC_AD3			0x80c
+#define AM335X_PIN_GPMC_AD4			0x810
+#define AM335X_PIN_GPMC_AD5			0x814
+#define AM335X_PIN_GPMC_AD6			0x818
+#define AM335X_PIN_GPMC_AD7			0x81c
+#define AM335X_PIN_GPMC_AD8			0x820
+#define AM335X_PIN_GPMC_AD9			0x824
+#define AM335X_PIN_GPMC_AD10			0x828
+#define AM335X_PIN_GPMC_AD11			0x82c
+#define AM335X_PIN_GPMC_AD12			0x830
+#define AM335X_PIN_GPMC_AD13			0x834
+#define AM335X_PIN_GPMC_AD14			0x838
+#define AM335X_PIN_GPMC_AD15			0x83c
+#define AM335X_PIN_GPMC_A0			0x840
+#define AM335X_PIN_GPMC_A1			0x844
+#define AM335X_PIN_GPMC_A2			0x848
+#define AM335X_PIN_GPMC_A3			0x84c
+#define AM335X_PIN_GPMC_A4			0x850
+#define AM335X_PIN_GPMC_A5			0x854
+#define AM335X_PIN_GPMC_A6			0x858
+#define AM335X_PIN_GPMC_A7			0x85c
+#define AM335X_PIN_GPMC_A8			0x860
+#define AM335X_PIN_GPMC_A9			0x864
+#define AM335X_PIN_GPMC_A10			0x868
+#define AM335X_PIN_GPMC_A11			0x86c
+#define AM335X_PIN_GPMC_WAIT0			0x870
+#define AM335X_PIN_GPMC_WPN			0x874
+#define AM335X_PIN_GPMC_BEN1			0x878
+#define AM335X_PIN_GPMC_CSN0			0x87c
+#define AM335X_PIN_GPMC_CSN1			0x880
+#define AM335X_PIN_GPMC_CSN2			0x884
+#define AM335X_PIN_GPMC_CSN3			0x888
+#define AM335X_PIN_GPMC_CLK			0x88c
+#define AM335X_PIN_GPMC_ADVN_ALE		0x890
+#define AM335X_PIN_GPMC_OEN_REN			0x894
+#define AM335X_PIN_GPMC_WEN			0x898
+#define AM335X_PIN_GPMC_BEN0_CLE		0x89c
+#define AM335X_PIN_LCD_DATA0			0x8a0
+#define AM335X_PIN_LCD_DATA1			0x8a4
+#define AM335X_PIN_LCD_DATA2			0x8a8
+#define AM335X_PIN_LCD_DATA3			0x8ac
+#define AM335X_PIN_LCD_DATA4			0x8b0
+#define AM335X_PIN_LCD_DATA5			0x8b4
+#define AM335X_PIN_LCD_DATA6			0x8b8
+#define AM335X_PIN_LCD_DATA7			0x8bc
+#define AM335X_PIN_LCD_DATA8			0x8c0
+#define AM335X_PIN_LCD_DATA9			0x8c4
+#define AM335X_PIN_LCD_DATA10			0x8c8
+#define AM335X_PIN_LCD_DATA11			0x8cc
+#define AM335X_PIN_LCD_DATA12			0x8d0
+#define AM335X_PIN_LCD_DATA13			0x8d4
+#define AM335X_PIN_LCD_DATA14			0x8d8
+#define AM335X_PIN_LCD_DATA15			0x8dc
+#define AM335X_PIN_LCD_VSYNC			0x8e0
+#define AM335X_PIN_LCD_HSYNC			0x8e4
+#define AM335X_PIN_LCD_PCLK			0x8e8
+#define AM335X_PIN_LCD_AC_BIAS_EN		0x8ec
+#define AM335X_PIN_MMC0_DAT3			0x8f0
+#define AM335X_PIN_MMC0_DAT2			0x8f4
+#define AM335X_PIN_MMC0_DAT1			0x8f8
+#define AM335X_PIN_MMC0_DAT0			0x8fc
+#define AM335X_PIN_MMC0_CLK			0x900
+#define AM335X_PIN_MMC0_CMD			0x904
+#define AM335X_PIN_MII1_COL			0x908
+#define AM335X_PIN_MII1_CRS			0x90c
+#define AM335X_PIN_MII1_RX_ER			0x910
+#define AM335X_PIN_MII1_TX_EN			0x914
+#define AM335X_PIN_MII1_RX_DV			0x918
+#define AM335X_PIN_MII1_TXD3			0x91c
+#define AM335X_PIN_MII1_TXD2			0x920
+#define AM335X_PIN_MII1_TXD1			0x924
+#define AM335X_PIN_MII1_TXD0			0x928
+#define AM335X_PIN_MII1_TX_CLK			0x92c
+#define AM335X_PIN_MII1_RX_CLK			0x930
+#define AM335X_PIN_MII1_RXD3			0x934
+#define AM335X_PIN_MII1_RXD2			0x938
+#define AM335X_PIN_MII1_RXD1			0x93c
+#define AM335X_PIN_MII1_RXD0			0x940
+#define AM335X_PIN_RMII1_REF_CLK		0x944
+#define AM335X_PIN_MDIO				0x948
+#define AM335X_PIN_MDC				0x94c
+#define AM335X_PIN_SPI0_SCLK			0x950
+#define AM335X_PIN_SPI0_D0			0x954
+#define AM335X_PIN_SPI0_D1			0x958
+#define AM335X_PIN_SPI0_CS0			0x95c
+#define AM335X_PIN_SPI0_CS1			0x960
+#define AM335X_PIN_ECAP0_IN_PWM0_OUT		0x964
+#define AM335X_PIN_UART0_CTSN			0x968
+#define AM335X_PIN_UART0_RTSN			0x96c
+#define AM335X_PIN_UART0_RXD			0x970
+#define AM335X_PIN_UART0_TXD			0x974
+#define AM335X_PIN_UART1_CTSN			0x978
+#define AM335X_PIN_UART1_RTSN			0x97c
+#define AM335X_PIN_UART1_RXD			0x980
+#define AM335X_PIN_UART1_TXD			0x984
+#define AM335X_PIN_I2C0_SDA			0x988
+#define AM335X_PIN_I2C0_SCL			0x98c
+#define AM335X_PIN_MCASP0_ACLKX			0x990
+#define AM335X_PIN_MCASP0_FSX			0x994
+#define AM335X_PIN_MCASP0_AXR0			0x998
+#define AM335X_PIN_MCASP0_AHCLKR		0x99c
+#define AM335X_PIN_MCASP0_ACLKR			0x9a0
+#define AM335X_PIN_MCASP0_FSR			0x9a4
+#define AM335X_PIN_MCASP0_AXR1			0x9a8
+#define AM335X_PIN_MCASP0_AHCLKX		0x9ac
+#define AM335X_PIN_XDMA_EVENT_INTR0		0x9b0
+#define AM335X_PIN_XDMA_EVENT_INTR1		0x9b4
+#define AM335X_PIN_WARMRSTN			0x9b8
+#define AM335X_PIN_NNMI				0x9c0
+#define AM335X_PIN_TMS				0x9d0
+#define AM335X_PIN_TDI				0x9d4
+#define AM335X_PIN_TDO				0x9d8
+#define AM335X_PIN_TCK				0x9dc
+#define AM335X_PIN_TRSTN			0x9e0
+#define AM335X_PIN_EMU0				0x9e4
+#define AM335X_PIN_EMU1				0x9e8
+#define AM335X_PIN_RTC_PWRONRSTN		0x9f8
+#define AM335X_PIN_PMIC_POWER_EN		0x9fc
+#define AM335X_PIN_EXT_WAKEUP			0xa00
+#define AM335X_PIN_USB0_DRVVBUS			0xa1c
+#define AM335X_PIN_USB1_DRVVBUS			0xa34
+
+#define AM335X_PIN_OFFSET_MAX			0x0a34U
+
+#endif
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/pinctrl/dra.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/pinctrl/dra.h
new file mode 100644
index 0000000000000000000000000000000000000000..18ec5df5a5812a9f037247b6c95de1d15fba2546
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/pinctrl/dra.h
@@ -0,0 +1,80 @@
+/*
+ * This header provides constants for DRA pinctrl bindings.
+ *
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ * Author: Rajendra Nayak <rnayak@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef _DT_BINDINGS_PINCTRL_DRA_H
+#define _DT_BINDINGS_PINCTRL_DRA_H
+
+/* DRA7 mux mode options for each pin. See TRM for options */
+#define MUX_MODE0	0x0
+#define MUX_MODE1	0x1
+#define MUX_MODE2	0x2
+#define MUX_MODE3	0x3
+#define MUX_MODE4	0x4
+#define MUX_MODE5	0x5
+#define MUX_MODE6	0x6
+#define MUX_MODE7	0x7
+#define MUX_MODE8	0x8
+#define MUX_MODE9	0x9
+#define MUX_MODE10	0xa
+#define MUX_MODE11	0xb
+#define MUX_MODE12	0xc
+#define MUX_MODE13	0xd
+#define MUX_MODE14	0xe
+#define MUX_MODE15	0xf
+
+/* Certain pins need virtual mode, but note: they may glitch */
+#define MUX_VIRTUAL_MODE0	(MODE_SELECT | (0x0 << 4))
+#define MUX_VIRTUAL_MODE1	(MODE_SELECT | (0x1 << 4))
+#define MUX_VIRTUAL_MODE2	(MODE_SELECT | (0x2 << 4))
+#define MUX_VIRTUAL_MODE3	(MODE_SELECT | (0x3 << 4))
+#define MUX_VIRTUAL_MODE4	(MODE_SELECT | (0x4 << 4))
+#define MUX_VIRTUAL_MODE5	(MODE_SELECT | (0x5 << 4))
+#define MUX_VIRTUAL_MODE6	(MODE_SELECT | (0x6 << 4))
+#define MUX_VIRTUAL_MODE7	(MODE_SELECT | (0x7 << 4))
+#define MUX_VIRTUAL_MODE8	(MODE_SELECT | (0x8 << 4))
+#define MUX_VIRTUAL_MODE9	(MODE_SELECT | (0x9 << 4))
+#define MUX_VIRTUAL_MODE10	(MODE_SELECT | (0xa << 4))
+#define MUX_VIRTUAL_MODE11	(MODE_SELECT | (0xb << 4))
+#define MUX_VIRTUAL_MODE12	(MODE_SELECT | (0xc << 4))
+#define MUX_VIRTUAL_MODE13	(MODE_SELECT | (0xd << 4))
+#define MUX_VIRTUAL_MODE14	(MODE_SELECT | (0xe << 4))
+#define MUX_VIRTUAL_MODE15	(MODE_SELECT | (0xf << 4))
+
+#define MODE_SELECT		(1 << 8)
+
+#define PULL_ENA		(0 << 16)
+#define PULL_DIS		(1 << 16)
+#define PULL_UP			(1 << 17)
+#define INPUT_EN		(1 << 18)
+#define SLEWCONTROL		(1 << 19)
+#define WAKEUP_EN		(1 << 24)
+#define WAKEUP_EVENT		(1 << 25)
+
+/* Active pin states */
+#define PIN_OUTPUT		(0 | PULL_DIS)
+#define PIN_OUTPUT_PULLUP	(PULL_UP)
+#define PIN_OUTPUT_PULLDOWN	(0)
+#define PIN_INPUT		(INPUT_EN | PULL_DIS)
+#define PIN_INPUT_SLEW		(INPUT_EN | SLEWCONTROL)
+#define PIN_INPUT_PULLUP	(PULL_ENA | INPUT_EN | PULL_UP)
+#define PIN_INPUT_PULLDOWN	(PULL_ENA | INPUT_EN)
+
+/*
+ * Macro to allow using the absolute physical address instead of the
+ * padconf registers instead of the offset from padconf base.
+ */
+#define DRA7XX_CORE_IOPAD(pa, val)	(((pa) & 0xffff) - 0x3400) (val)
+
+/* DRA7 IODELAY configuration parameters */
+#define A_DELAY_PS(val)			((val) & 0xffff)
+#define G_DELAY_PS(val)			((val) & 0xffff)
+#endif
+
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/pinctrl/omap.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/pinctrl/omap.h
new file mode 100644
index 0000000000000000000000000000000000000000..146ad0843b56db9b59a957efce546186e673b72c
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/dt-bindings/pinctrl/omap.h
@@ -0,0 +1,94 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * This header provides constants for OMAP pinctrl bindings.
+ *
+ * Copyright (C) 2009 Nokia
+ * Copyright (C) 2009-2010 Texas Instruments
+ */
+
+#ifndef _DT_BINDINGS_PINCTRL_OMAP_H
+#define _DT_BINDINGS_PINCTRL_OMAP_H
+
+/* 34xx mux mode options for each pin. See TRM for options */
+#define MUX_MODE0	0
+#define MUX_MODE1	1
+#define MUX_MODE2	2
+#define MUX_MODE3	3
+#define MUX_MODE4	4
+#define MUX_MODE5	5
+#define MUX_MODE6	6
+#define MUX_MODE7	7
+
+/* 24xx/34xx mux bit defines */
+#define PULL_ENA		(1 << 3)
+#define PULL_UP			(1 << 4)
+#define ALTELECTRICALSEL	(1 << 5)
+
+/* omap3/4/5 specific mux bit defines */
+#define INPUT_EN		(1 << 8)
+#define OFF_EN			(1 << 9)
+#define OFFOUT_EN		(1 << 10)
+#define OFFOUT_VAL		(1 << 11)
+#define OFF_PULL_EN		(1 << 12)
+#define OFF_PULL_UP		(1 << 13)
+#define WAKEUP_EN		(1 << 14)
+#define WAKEUP_EVENT		(1 << 15)
+
+/* Active pin states */
+#define PIN_OUTPUT		0
+#define PIN_OUTPUT_PULLUP	(PIN_OUTPUT | PULL_ENA | PULL_UP)
+#define PIN_OUTPUT_PULLDOWN	(PIN_OUTPUT | PULL_ENA)
+#define PIN_INPUT		INPUT_EN
+#define PIN_INPUT_PULLUP	(PULL_ENA | INPUT_EN | PULL_UP)
+#define PIN_INPUT_PULLDOWN	(PULL_ENA | INPUT_EN)
+
+/* Off mode states */
+#define PIN_OFF_NONE		0
+#define PIN_OFF_OUTPUT_HIGH	(OFF_EN | OFFOUT_EN | OFFOUT_VAL)
+#define PIN_OFF_OUTPUT_LOW	(OFF_EN | OFFOUT_EN)
+#define PIN_OFF_INPUT_PULLUP	(OFF_EN | OFFOUT_EN | OFF_PULL_EN | OFF_PULL_UP)
+#define PIN_OFF_INPUT_PULLDOWN	(OFF_EN | OFFOUT_EN | OFF_PULL_EN)
+#define PIN_OFF_WAKEUPENABLE	WAKEUP_EN
+
+/*
+ * Macros to allow using the absolute physical address instead of the
+ * padconf registers instead of the offset from padconf base.
+ */
+#define OMAP_IOPAD_OFFSET(pa, offset)	(((pa) & 0xffff) - (offset))
+
+#define OMAP2420_CORE_IOPAD(pa, val)	OMAP_IOPAD_OFFSET((pa), 0x0030) (val)
+#define OMAP2430_CORE_IOPAD(pa, val)	OMAP_IOPAD_OFFSET((pa), 0x2030) (val)
+#define OMAP3_CORE1_IOPAD(pa, val)	OMAP_IOPAD_OFFSET((pa), 0x2030) (val)
+#define OMAP3430_CORE2_IOPAD(pa, val)	OMAP_IOPAD_OFFSET((pa), 0x25d8) (val)
+#define OMAP3630_CORE2_IOPAD(pa, val)	OMAP_IOPAD_OFFSET((pa), 0x25a0) (val)
+#define OMAP3_WKUP_IOPAD(pa, val)	OMAP_IOPAD_OFFSET((pa), 0x2a00) (val)
+#define DM814X_IOPAD(pa, val)		OMAP_IOPAD_OFFSET((pa), 0x0800) (val)
+#define DM816X_IOPAD(pa, val)		OMAP_IOPAD_OFFSET((pa), 0x0800) (val)
+#define AM33XX_IOPAD(pa, val)		OMAP_IOPAD_OFFSET((pa), 0x0800) (val)
+#define AM33XX_PADCONF(pa, dir, mux)	OMAP_IOPAD_OFFSET((pa), 0x0800) ((dir) | (mux))
+#define AM4372_IOPAD(pa, val)		OMAP_IOPAD_OFFSET((pa), 0x0800) (val)
+#define DRA7XX_CORE_IOPAD(pa, val)	OMAP_IOPAD_OFFSET((pa), 0x3400) (val)
+
+/*
+ * Macros to allow using the offset from the padconf physical address
+ * instead  of the offset from padconf base.
+ */
+#define OMAP_PADCONF_OFFSET(offset, base_offset)	((offset) - (base_offset))
+
+#define OMAP4_IOPAD(offset, val)	OMAP_PADCONF_OFFSET((offset), 0x0040) (val)
+#define OMAP5_IOPAD(offset, val)	OMAP_PADCONF_OFFSET((offset), 0x0040) (val)
+
+/*
+ * Define some commonly used pins configured by the boards.
+ * Note that some boards use alternative pins, so check
+ * the schematics before using these.
+ */
+#define OMAP3_UART1_RX		0x152
+#define OMAP3_UART2_RX		0x14a
+#define OMAP3_UART3_RX		0x16e
+#define OMAP4_UART2_RX		0xdc
+#define OMAP4_UART3_RX		0x104
+#define OMAP4_UART4_RX		0x11c
+
+#endif
+
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/imx1-pinfunc.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/imx1-pinfunc.h
new file mode 100644
index 0000000000000000000000000000000000000000..22bec8b87680484d8ead4ed57cb00b7599808d78
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/imx1-pinfunc.h
@@ -0,0 +1,302 @@
+/*
+ * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#ifndef __DTS_IMX1_PINFUNC_H
+#define __DTS_IMX1_PINFUNC_H
+
+/*
+ * The pin function ID is a tuple of
+ * <pin mux_id>
+ * mux_id consists of
+ * function + (direction << 2) + (gpio_oconf << 4) + (gpio_iconfa << 8) + (gpio_iconfb << 10)
+ *
+ * function:      0 - Primary function
+ *                1 - Alternate function
+ *                2 - GPIO
+ * direction:     0 - Input
+ *                1 - Output
+ * gpio_oconf:    0 - A_IN
+ *                1 - B_IN
+ *                2 - A_OUT
+ *                3 - Data Register
+ * gpio_iconfa/b: 0 - GPIO_IN
+ *                1 - Interrupt Status Register
+ *                2 - 0
+ *                3 - 1
+ *
+ * 'pin' is an integer between 0 and 0xbf. i.MX1 has 4 ports with 32 configurable
+ * configurable pins each. 'pin' is PORT * 32 + PORT_PIN, PORT_PIN is the pin
+ * number on the specific port (between 0 and 31).
+ */
+
+#define MX1_PAD_A24__A24			0x00 0x004
+#define MX1_PAD_A24__GPIO1_0			0x00 0x032
+#define MX1_PAD_A24__SPI2_CLK			0x00 0x006
+#define MX1_PAD_TIN__TIN			0x01 0x000
+#define MX1_PAD_TIN__GPIO1_1			0x01 0x032
+#define MX1_PAD_TIN__SPI2_RXD			0x01 0x022
+#define MX1_PAD_PWMO__PWMO			0x02 0x004
+#define MX1_PAD_PWMO__GPIO1_2			0x02 0x032
+#define MX1_PAD_CSI_MCLK__CSI_MCLK		0x03 0x004
+#define MX1_PAD_CSI_MCLK__GPIO1_3		0x03 0x032
+#define MX1_PAD_CSI_D0__CSI_D0			0x04 0x000
+#define MX1_PAD_CSI_D0__GPIO1_4			0x04 0x032
+#define MX1_PAD_CSI_D1__CSI_D1			0x05 0x000
+#define MX1_PAD_CSI_D1__GPIO1_5			0x05 0x032
+#define MX1_PAD_CSI_D2__CSI_D2			0x06 0x000
+#define MX1_PAD_CSI_D2__GPIO1_6			0x06 0x032
+#define MX1_PAD_CSI_D3__CSI_D3			0x07 0x000
+#define MX1_PAD_CSI_D3__GPIO1_7			0x07 0x032
+#define MX1_PAD_CSI_D4__CSI_D4			0x08 0x000
+#define MX1_PAD_CSI_D4__GPIO1_8			0x08 0x032
+#define MX1_PAD_CSI_D5__CSI_D5			0x09 0x000
+#define MX1_PAD_CSI_D5__GPIO1_9			0x09 0x032
+#define MX1_PAD_CSI_D6__CSI_D6			0x0a 0x000
+#define MX1_PAD_CSI_D6__GPIO1_10		0x0a 0x032
+#define MX1_PAD_CSI_D7__CSI_D7			0x0b 0x000
+#define MX1_PAD_CSI_D7__GPIO1_11		0x0b 0x032
+#define MX1_PAD_CSI_VSYNC__CSI_VSYNC		0x0c 0x000
+#define MX1_PAD_CSI_VSYNC__GPIO1_12		0x0c 0x032
+#define MX1_PAD_CSI_HSYNC__CSI_HSYNC		0x0d 0x000
+#define MX1_PAD_CSI_HSYNC__GPIO1_13		0x0d 0x032
+#define MX1_PAD_CSI_PIXCLK__CSI_PIXCLK		0x0e 0x000
+#define MX1_PAD_CSI_PIXCLK__GPIO1_14		0x0e 0x032
+#define MX1_PAD_I2C_SDA__I2C_SDA		0x0f 0x000
+#define MX1_PAD_I2C_SDA__GPIO1_15		0x0f 0x032
+#define MX1_PAD_I2C_SCL__I2C_SCL		0x10 0x004
+#define MX1_PAD_I2C_SCL__GPIO1_16		0x10 0x032
+#define MX1_PAD_DTACK__DTACK			0x11 0x000
+#define MX1_PAD_DTACK__GPIO1_17			0x11 0x032
+#define MX1_PAD_DTACK__SPI2_SS			0x11 0x002
+#define MX1_PAD_DTACK__A25			0x11 0x016
+#define MX1_PAD_BCLK__BCLK			0x12 0x004
+#define MX1_PAD_BCLK__GPIO1_18			0x12 0x032
+#define MX1_PAD_LBA__LBA			0x13 0x004
+#define MX1_PAD_LBA__GPIO1_19			0x13 0x032
+#define MX1_PAD_ECB__ECB			0x14 0x000
+#define MX1_PAD_ECB__GPIO1_20			0x14 0x032
+#define MX1_PAD_A0__A0				0x15 0x004
+#define MX1_PAD_A0__GPIO1_21			0x15 0x032
+#define MX1_PAD_CS4__CS4			0x16 0x004
+#define MX1_PAD_CS4__GPIO1_22			0x16 0x032
+#define MX1_PAD_CS5__CS5			0x17 0x004
+#define MX1_PAD_CS5__GPIO1_23			0x17 0x032
+#define MX1_PAD_A16__A16			0x18 0x004
+#define MX1_PAD_A16__GPIO1_24			0x18 0x032
+#define MX1_PAD_A17__A17			0x19 0x004
+#define MX1_PAD_A17__GPIO1_25			0x19 0x032
+#define MX1_PAD_A18__A18			0x1a 0x004
+#define MX1_PAD_A18__GPIO1_26			0x1a 0x032
+#define MX1_PAD_A19__A19			0x1b 0x004
+#define MX1_PAD_A19__GPIO1_27			0x1b 0x032
+#define MX1_PAD_A20__A20			0x1c 0x004
+#define MX1_PAD_A20__GPIO1_28			0x1c 0x032
+#define MX1_PAD_A21__A21			0x1d 0x004
+#define MX1_PAD_A21__GPIO1_29			0x1d 0x032
+#define MX1_PAD_A22__A22			0x1e 0x004
+#define MX1_PAD_A22__GPIO1_30			0x1e 0x032
+#define MX1_PAD_A23__A23			0x1f 0x004
+#define MX1_PAD_A23__GPIO1_31			0x1f 0x032
+#define MX1_PAD_SD_DAT0__SD_DAT0		0x28 0x000
+#define MX1_PAD_SD_DAT0__MS_PI0			0x28 0x001
+#define MX1_PAD_SD_DAT0__GPIO2_8		0x28 0x032
+#define MX1_PAD_SD_DAT1__SD_DAT1		0x29 0x000
+#define MX1_PAD_SD_DAT1__MS_PI1			0x29 0x001
+#define MX1_PAD_SD_DAT1__GPIO2_9		0x29 0x032
+#define MX1_PAD_SD_DAT2__SD_DAT2		0x2a 0x000
+#define MX1_PAD_SD_DAT2__MS_SCLKI		0x2a 0x001
+#define MX1_PAD_SD_DAT2__GPIO2_10		0x2a 0x032
+#define MX1_PAD_SD_DAT3__SD_DAT3		0x2b 0x000
+#define MX1_PAD_SD_DAT3__MS_SDIO		0x2b 0x001
+#define MX1_PAD_SD_DAT3__GPIO2_11		0x2b 0x032
+#define MX1_PAD_SD_SCLK__SD_SCLK		0x2c 0x004
+#define MX1_PAD_SD_SCLK__MS_SCLKO		0x2c 0x005
+#define MX1_PAD_SD_SCLK__GPIO2_12		0x2c 0x032
+#define MX1_PAD_SD_CMD__SD_CMD			0x2d 0x000
+#define MX1_PAD_SD_CMD__MS_BS			0x2d 0x005
+#define MX1_PAD_SD_CMD__GPIO2_13		0x2d 0x032
+#define MX1_PAD_SIM_SVEN__SIM_SVEN		0x2e 0x004
+#define MX1_PAD_SIM_SVEN__SSI_RXFS		0x2e 0x001
+#define MX1_PAD_SIM_SVEN__GPIO2_14		0x2e 0x032
+#define MX1_PAD_SIM_PD__SIM_PD			0x2f 0x000
+#define MX1_PAD_SIM_PD__SSI_RXCLK		0x2f 0x001
+#define MX1_PAD_SIM_PD__GPIO2_15		0x2f 0x032
+#define MX1_PAD_SIM_TX__SIM_TX			0x30 0x000
+#define MX1_PAD_SIM_TX__SSI_RXDAT		0x30 0x001
+#define MX1_PAD_SIM_TX__GPIO2_16		0x30 0x032
+#define MX1_PAD_SIM_RX__SIM_RX			0x31 0x000
+#define MX1_PAD_SIM_RX__SSI_TXDAT		0x31 0x005
+#define MX1_PAD_SIM_RX__GPIO2_17		0x31 0x032
+#define MX1_PAD_SIM_RST__SIM_RST		0x32 0x004
+#define MX1_PAD_SIM_RST__SSI_TXFS		0x32 0x001
+#define MX1_PAD_SIM_RST__GPIO2_18		0x32 0x032
+#define MX1_PAD_SIM_CLK__SIM_CLK		0x33 0x004
+#define MX1_PAD_SIM_CLK__SSI_TXCLK		0x33 0x001
+#define MX1_PAD_SIM_CLK__GPIO2_19		0x33 0x032
+#define MX1_PAD_USBD_AFE__USBD_AFE		0x34 0x004
+#define MX1_PAD_USBD_AFE__GPIO2_20		0x34 0x032
+#define MX1_PAD_USBD_OE__USBD_OE		0x35 0x004
+#define MX1_PAD_USBD_OE__GPIO2_21		0x35 0x032
+#define MX1_PAD_USBD_RCV__USBD_RCV		0x36 0x000
+#define MX1_PAD_USBD_RCV__GPIO2_22		0x36 0x032
+#define MX1_PAD_USBD_SUSPND__USBD_SUSPND	0x37 0x004
+#define MX1_PAD_USBD_SUSPND__GPIO2_23		0x37 0x032
+#define MX1_PAD_USBD_VP__USBD_VP		0x38 0x000
+#define MX1_PAD_USBD_VP__GPIO2_24		0x38 0x032
+#define MX1_PAD_USBD_VM__USBD_VM		0x39 0x000
+#define MX1_PAD_USBD_VM__GPIO2_25		0x39 0x032
+#define MX1_PAD_USBD_VPO__USBD_VPO		0x3a 0x004
+#define MX1_PAD_USBD_VPO__GPIO2_26		0x3a 0x032
+#define MX1_PAD_USBD_VMO__USBD_VMO		0x3b 0x004
+#define MX1_PAD_USBD_VMO__GPIO2_27		0x3b 0x032
+#define MX1_PAD_UART2_CTS__UART2_CTS		0x3c 0x004
+#define MX1_PAD_UART2_CTS__GPIO2_28		0x3c 0x032
+#define MX1_PAD_UART2_RTS__UART2_RTS		0x3d 0x000
+#define MX1_PAD_UART2_RTS__GPIO2_29		0x3d 0x032
+#define MX1_PAD_UART2_TXD__UART2_TXD		0x3e 0x004
+#define MX1_PAD_UART2_TXD__GPIO2_30		0x3e 0x032
+#define MX1_PAD_UART2_RXD__UART2_RXD		0x3f 0x000
+#define MX1_PAD_UART2_RXD__GPIO2_31		0x3f 0x032
+#define MX1_PAD_SSI_RXFS__SSI_RXFS		0x43 0x000
+#define MX1_PAD_SSI_RXFS__GPIO3_3		0x43 0x032
+#define MX1_PAD_SSI_RXCLK__SSI_RXCLK		0x44 0x000
+#define MX1_PAD_SSI_RXCLK__GPIO3_4		0x44 0x032
+#define MX1_PAD_SSI_RXDAT__SSI_RXDAT		0x45 0x000
+#define MX1_PAD_SSI_RXDAT__GPIO3_5		0x45 0x032
+#define MX1_PAD_SSI_TXDAT__SSI_TXDAT		0x46 0x004
+#define MX1_PAD_SSI_TXDAT__GPIO3_6		0x46 0x032
+#define MX1_PAD_SSI_TXFS__SSI_TXFS		0x47 0x000
+#define MX1_PAD_SSI_TXFS__GPIO3_7		0x47 0x032
+#define MX1_PAD_SSI_TXCLK__SSI_TXCLK		0x48 0x000
+#define MX1_PAD_SSI_TXCLK__GPIO3_8		0x48 0x032
+#define MX1_PAD_UART1_CTS__UART1_CTS		0x49 0x004
+#define MX1_PAD_UART1_CTS__GPIO3_9		0x49 0x032
+#define MX1_PAD_UART1_RTS__UART1_RTS		0x4a 0x000
+#define MX1_PAD_UART1_RTS__GPIO3_10		0x4a 0x032
+#define MX1_PAD_UART1_TXD__UART1_TXD		0x4b 0x004
+#define MX1_PAD_UART1_TXD__GPIO3_11		0x4b 0x032
+#define MX1_PAD_UART1_RXD__UART1_RXD		0x4c 0x000
+#define MX1_PAD_UART1_RXD__GPIO3_12		0x4c 0x032
+#define MX1_PAD_SPI1_RDY__SPI1_RDY		0x4d 0x000
+#define MX1_PAD_SPI1_RDY__GPIO3_13		0x4d 0x032
+#define MX1_PAD_SPI1_SCLK__SPI1_SCLK		0x4e 0x004
+#define MX1_PAD_SPI1_SCLK__GPIO3_14		0x4e 0x032
+#define MX1_PAD_SPI1_SS__SPI1_SS		0x4f 0x000
+#define MX1_PAD_SPI1_SS__GPIO3_15		0x4f 0x032
+#define MX1_PAD_SPI1_MISO__SPI1_MISO		0x50 0x000
+#define MX1_PAD_SPI1_MISO__GPIO3_16		0x50 0x032
+#define MX1_PAD_SPI1_MOSI__SPI1_MOSI		0x51 0x004
+#define MX1_PAD_SPI1_MOSI__GPIO3_17		0x51 0x032
+#define MX1_PAD_BT13__BT13			0x53 0x004
+#define MX1_PAD_BT13__SSI2_RXCLK		0x53 0x001
+#define MX1_PAD_BT13__GPIO3_19			0x53 0x032
+#define MX1_PAD_BT12__BT12			0x54 0x004
+#define MX1_PAD_BT12__SSI2_TXFS			0x54 0x001
+#define MX1_PAD_BT12__GPIO3_20			0x54 0x032
+#define MX1_PAD_BT11__BT11			0x55 0x004
+#define MX1_PAD_BT11__SSI2_TXCLK		0x55 0x001
+#define MX1_PAD_BT11__GPIO3_21			0x55 0x032
+#define MX1_PAD_BT10__BT10			0x56 0x004
+#define MX1_PAD_BT10__SSI2_TX			0x56 0x001
+#define MX1_PAD_BT10__GPIO3_22			0x56 0x032
+#define MX1_PAD_BT9__BT9			0x57 0x004
+#define MX1_PAD_BT9__SSI2_RX			0x57 0x001
+#define MX1_PAD_BT9__GPIO3_23			0x57 0x032
+#define MX1_PAD_BT8__BT8			0x58 0x004
+#define MX1_PAD_BT8__SSI2_RXFS			0x58 0x001
+#define MX1_PAD_BT8__GPIO3_24			0x58 0x032
+#define MX1_PAD_BT8__UART3_RI			0x58 0x016
+#define MX1_PAD_BT7__BT7			0x59 0x004
+#define MX1_PAD_BT7__GPIO3_25			0x59 0x032
+#define MX1_PAD_BT7__UART3_DSR			0x59 0x016
+#define MX1_PAD_BT6__BT6			0x5a 0x004
+#define MX1_PAD_BT6__GPIO3_26			0x5a 0x032
+#define MX1_PAD_BT6__SPI2_SS3			0x5a 0x016
+#define MX1_PAD_BT6__UART3_DTR			0x5a 0x022
+#define MX1_PAD_BT5__BT5			0x5b 0x000
+#define MX1_PAD_BT5__GPIO3_27			0x5b 0x032
+#define MX1_PAD_BT5__UART3_DCD			0x5b 0x016
+#define MX1_PAD_BT4__BT4			0x5c 0x000
+#define MX1_PAD_BT4__GPIO3_28			0x5c 0x032
+#define MX1_PAD_BT4__UART3_CTS			0x5c 0x016
+#define MX1_PAD_BT3__BT3			0x5d 0x000
+#define MX1_PAD_BT3__GPIO3_29			0x5d 0x032
+#define MX1_PAD_BT3__UART3_RTS			0x5d 0x022
+#define MX1_PAD_BT2__BT2			0x5e 0x004
+#define MX1_PAD_BT2__GPIO3_30			0x5e 0x032
+#define MX1_PAD_BT2__UART3_TX			0x5e 0x016
+#define MX1_PAD_BT1__BT1			0x5f 0x000
+#define MX1_PAD_BT1__GPIO3_31			0x5f 0x032
+#define MX1_PAD_BT1__UART3_RX			0x5f 0x022
+#define MX1_PAD_LSCLK__LSCLK			0x66 0x004
+#define MX1_PAD_LSCLK__GPIO4_6			0x66 0x032
+#define MX1_PAD_REV__REV			0x67 0x004
+#define MX1_PAD_REV__UART2_DTR			0x67 0x001
+#define MX1_PAD_REV__GPIO4_7			0x67 0x032
+#define MX1_PAD_REV__SPI2_CLK			0x67 0x006
+#define MX1_PAD_CLS__CLS			0x68 0x004
+#define MX1_PAD_CLS__UART2_DCD			0x68 0x005
+#define MX1_PAD_CLS__GPIO4_8			0x68 0x032
+#define MX1_PAD_CLS__SPI2_SS			0x68 0x002
+#define MX1_PAD_PS__PS				0x69 0x004
+#define MX1_PAD_PS__UART2_RI			0x69 0x005
+#define MX1_PAD_PS__GPIO4_9			0x69 0x032
+#define MX1_PAD_PS__SPI2_RXD			0x69 0x022
+#define MX1_PAD_SPL_SPR__SPL_SPR		0x6a 0x004
+#define MX1_PAD_SPL_SPR__UART2_DSR		0x6a 0x005
+#define MX1_PAD_SPL_SPR__GPIO4_10		0x6a 0x032
+#define MX1_PAD_SPL_SPR__SPI2_TXD		0x6a 0x006
+#define MX1_PAD_CONTRAST__CONTRAST		0x6b 0x004
+#define MX1_PAD_CONTRAST__GPIO4_11		0x6b 0x032
+#define MX1_PAD_CONTRAST__SPI2_SS2		0x6b 0x012
+#define MX1_PAD_ACD_OE__ACD_OE			0x6c 0x004
+#define MX1_PAD_ACD_OE__GPIO4_12		0x6c 0x032
+#define MX1_PAD_LP_HSYNC__LP_HSYNC		0x6d 0x004
+#define MX1_PAD_LP_HSYNC__GPIO4_13		0x6d 0x032
+#define MX1_PAD_FLM_VSYNC__FLM_VSYNC		0x6e 0x004
+#define MX1_PAD_FLM_VSYNC__GPIO4_14		0x6e 0x032
+#define MX1_PAD_LD0__LD0			0x6f 0x004
+#define MX1_PAD_LD0__GPIO4_15			0x6f 0x032
+#define MX1_PAD_LD1__LD1			0x70 0x004
+#define MX1_PAD_LD1__GPIO4_16			0x70 0x032
+#define MX1_PAD_LD2__LD2			0x71 0x004
+#define MX1_PAD_LD2__GPIO4_17			0x71 0x032
+#define MX1_PAD_LD3__LD3			0x72 0x004
+#define MX1_PAD_LD3__GPIO4_18			0x72 0x032
+#define MX1_PAD_LD4__LD4			0x73 0x004
+#define MX1_PAD_LD4__GPIO4_19			0x73 0x032
+#define MX1_PAD_LD5__LD5			0x74 0x004
+#define MX1_PAD_LD5__GPIO4_20			0x74 0x032
+#define MX1_PAD_LD6__LD6			0x75 0x004
+#define MX1_PAD_LD6__GPIO4_21			0x75 0x032
+#define MX1_PAD_LD7__LD7			0x76 0x004
+#define MX1_PAD_LD7__GPIO4_22			0x76 0x032
+#define MX1_PAD_LD8__LD8			0x77 0x004
+#define MX1_PAD_LD8__GPIO4_23			0x77 0x032
+#define MX1_PAD_LD9__LD9			0x78 0x004
+#define MX1_PAD_LD9__GPIO4_24			0x78 0x032
+#define MX1_PAD_LD10__LD10			0x79 0x004
+#define MX1_PAD_LD10__GPIO4_25			0x79 0x032
+#define MX1_PAD_LD11__LD11			0x7a 0x004
+#define MX1_PAD_LD11__GPIO4_26			0x7a 0x032
+#define MX1_PAD_LD12__LD12			0x7b 0x004
+#define MX1_PAD_LD12__GPIO4_27			0x7b 0x032
+#define MX1_PAD_LD13__LD13			0x7c 0x004
+#define MX1_PAD_LD13__GPIO4_28			0x7c 0x032
+#define MX1_PAD_LD14__LD14			0x7d 0x004
+#define MX1_PAD_LD14__GPIO4_29			0x7d 0x032
+#define MX1_PAD_LD15__LD15			0x7e 0x004
+#define MX1_PAD_LD15__GPIO4_30			0x7e 0x032
+#define MX1_PAD_TMR2OUT__TMR2OUT		0x7f 0x000
+#define MX1_PAD_TMR2OUT__GPIO4_31		0x7f 0x032
+#define MX1_PAD_TMR2OUT__SPI2_TXD		0x7f 0x006
+
+#endif
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/imx23-pinfunc.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/imx23-pinfunc.h
new file mode 100644
index 0000000000000000000000000000000000000000..5c0f32ca3a93a22cd79d959362496f22a28c9ecf
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/imx23-pinfunc.h
@@ -0,0 +1,333 @@
+/*
+ * Header providing constants for i.MX23 pinctrl bindings.
+ *
+ * Copyright (C) 2013 Lothar Waßmann <LW@KARO-electronics.de>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#ifndef __DT_BINDINGS_MX23_PINCTRL_H__
+#define __DT_BINDINGS_MX23_PINCTRL_H__
+
+#include "mxs-pinfunc.h"
+
+#define MX23_PAD_GPMI_D00__GPMI_D00			0x0000
+#define MX23_PAD_GPMI_D01__GPMI_D01			0x0010
+#define MX23_PAD_GPMI_D02__GPMI_D02			0x0020
+#define MX23_PAD_GPMI_D03__GPMI_D03			0x0030
+#define MX23_PAD_GPMI_D04__GPMI_D04			0x0040
+#define MX23_PAD_GPMI_D05__GPMI_D05			0x0050
+#define MX23_PAD_GPMI_D06__GPMI_D06			0x0060
+#define MX23_PAD_GPMI_D07__GPMI_D07			0x0070
+#define MX23_PAD_GPMI_D08__GPMI_D08			0x0080
+#define MX23_PAD_GPMI_D09__GPMI_D09			0x0090
+#define MX23_PAD_GPMI_D10__GPMI_D10			0x00a0
+#define MX23_PAD_GPMI_D11__GPMI_D11			0x00b0
+#define MX23_PAD_GPMI_D12__GPMI_D12			0x00c0
+#define MX23_PAD_GPMI_D13__GPMI_D13			0x00d0
+#define MX23_PAD_GPMI_D14__GPMI_D14			0x00e0
+#define MX23_PAD_GPMI_D15__GPMI_D15			0x00f0
+#define MX23_PAD_GPMI_CLE__GPMI_CLE			0x0100
+#define MX23_PAD_GPMI_ALE__GPMI_ALE			0x0110
+#define MX23_PAD_GPMI_CE2N__GPMI_CE2N			0x0120
+#define MX23_PAD_GPMI_RDY0__GPMI_RDY0			0x0130
+#define MX23_PAD_GPMI_RDY1__GPMI_RDY1			0x0140
+#define MX23_PAD_GPMI_RDY2__GPMI_RDY2			0x0150
+#define MX23_PAD_GPMI_RDY3__GPMI_RDY3			0x0160
+#define MX23_PAD_GPMI_WPN__GPMI_WPN			0x0170
+#define MX23_PAD_GPMI_WRN__GPMI_WRN			0x0180
+#define MX23_PAD_GPMI_RDN__GPMI_RDN			0x0190
+#define MX23_PAD_AUART1_CTS__AUART1_CTS			0x01a0
+#define MX23_PAD_AUART1_RTS__AUART1_RTS			0x01b0
+#define MX23_PAD_AUART1_RX__AUART1_RX			0x01c0
+#define MX23_PAD_AUART1_TX__AUART1_TX			0x01d0
+#define MX23_PAD_I2C_SCL__I2C_SCL			0x01e0
+#define MX23_PAD_I2C_SDA__I2C_SDA			0x01f0
+#define MX23_PAD_LCD_D00__LCD_D00			0x1000
+#define MX23_PAD_LCD_D01__LCD_D01			0x1010
+#define MX23_PAD_LCD_D02__LCD_D02			0x1020
+#define MX23_PAD_LCD_D03__LCD_D03			0x1030
+#define MX23_PAD_LCD_D04__LCD_D04			0x1040
+#define MX23_PAD_LCD_D05__LCD_D05			0x1050
+#define MX23_PAD_LCD_D06__LCD_D06			0x1060
+#define MX23_PAD_LCD_D07__LCD_D07			0x1070
+#define MX23_PAD_LCD_D08__LCD_D08			0x1080
+#define MX23_PAD_LCD_D09__LCD_D09			0x1090
+#define MX23_PAD_LCD_D10__LCD_D10			0x10a0
+#define MX23_PAD_LCD_D11__LCD_D11			0x10b0
+#define MX23_PAD_LCD_D12__LCD_D12			0x10c0
+#define MX23_PAD_LCD_D13__LCD_D13			0x10d0
+#define MX23_PAD_LCD_D14__LCD_D14			0x10e0
+#define MX23_PAD_LCD_D15__LCD_D15			0x10f0
+#define MX23_PAD_LCD_D16__LCD_D16			0x1100
+#define MX23_PAD_LCD_D17__LCD_D17			0x1110
+#define MX23_PAD_LCD_RESET__LCD_RESET			0x1120
+#define MX23_PAD_LCD_RS__LCD_RS				0x1130
+#define MX23_PAD_LCD_WR__LCD_WR				0x1140
+#define MX23_PAD_LCD_CS__LCD_CS				0x1150
+#define MX23_PAD_LCD_DOTCK__LCD_DOTCK			0x1160
+#define MX23_PAD_LCD_ENABLE__LCD_ENABLE			0x1170
+#define MX23_PAD_LCD_HSYNC__LCD_HSYNC			0x1180
+#define MX23_PAD_LCD_VSYNC__LCD_VSYNC			0x1190
+#define MX23_PAD_PWM0__PWM0				0x11a0
+#define MX23_PAD_PWM1__PWM1				0x11b0
+#define MX23_PAD_PWM2__PWM2				0x11c0
+#define MX23_PAD_PWM3__PWM3				0x11d0
+#define MX23_PAD_PWM4__PWM4				0x11e0
+#define MX23_PAD_SSP1_CMD__SSP1_CMD			0x2000
+#define MX23_PAD_SSP1_DETECT__SSP1_DETECT		0x2010
+#define MX23_PAD_SSP1_DATA0__SSP1_DATA0			0x2020
+#define MX23_PAD_SSP1_DATA1__SSP1_DATA1			0x2030
+#define MX23_PAD_SSP1_DATA2__SSP1_DATA2			0x2040
+#define MX23_PAD_SSP1_DATA3__SSP1_DATA3			0x2050
+#define MX23_PAD_SSP1_SCK__SSP1_SCK			0x2060
+#define MX23_PAD_ROTARYA__ROTARYA			0x2070
+#define MX23_PAD_ROTARYB__ROTARYB			0x2080
+#define MX23_PAD_EMI_A00__EMI_A00			0x2090
+#define MX23_PAD_EMI_A01__EMI_A01			0x20a0
+#define MX23_PAD_EMI_A02__EMI_A02			0x20b0
+#define MX23_PAD_EMI_A03__EMI_A03			0x20c0
+#define MX23_PAD_EMI_A04__EMI_A04			0x20d0
+#define MX23_PAD_EMI_A05__EMI_A05			0x20e0
+#define MX23_PAD_EMI_A06__EMI_A06			0x20f0
+#define MX23_PAD_EMI_A07__EMI_A07			0x2100
+#define MX23_PAD_EMI_A08__EMI_A08			0x2110
+#define MX23_PAD_EMI_A09__EMI_A09			0x2120
+#define MX23_PAD_EMI_A10__EMI_A10			0x2130
+#define MX23_PAD_EMI_A11__EMI_A11			0x2140
+#define MX23_PAD_EMI_A12__EMI_A12			0x2150
+#define MX23_PAD_EMI_BA0__EMI_BA0			0x2160
+#define MX23_PAD_EMI_BA1__EMI_BA1			0x2170
+#define MX23_PAD_EMI_CASN__EMI_CASN			0x2180
+#define MX23_PAD_EMI_CE0N__EMI_CE0N			0x2190
+#define MX23_PAD_EMI_CE1N__EMI_CE1N			0x21a0
+#define MX23_PAD_GPMI_CE1N__GPMI_CE1N			0x21b0
+#define MX23_PAD_GPMI_CE0N__GPMI_CE0N			0x21c0
+#define MX23_PAD_EMI_CKE__EMI_CKE			0x21d0
+#define MX23_PAD_EMI_RASN__EMI_RASN			0x21e0
+#define MX23_PAD_EMI_WEN__EMI_WEN			0x21f0
+#define MX23_PAD_EMI_D00__EMI_D00			0x3000
+#define MX23_PAD_EMI_D01__EMI_D01			0x3010
+#define MX23_PAD_EMI_D02__EMI_D02			0x3020
+#define MX23_PAD_EMI_D03__EMI_D03			0x3030
+#define MX23_PAD_EMI_D04__EMI_D04			0x3040
+#define MX23_PAD_EMI_D05__EMI_D05			0x3050
+#define MX23_PAD_EMI_D06__EMI_D06			0x3060
+#define MX23_PAD_EMI_D07__EMI_D07			0x3070
+#define MX23_PAD_EMI_D08__EMI_D08			0x3080
+#define MX23_PAD_EMI_D09__EMI_D09			0x3090
+#define MX23_PAD_EMI_D10__EMI_D10			0x30a0
+#define MX23_PAD_EMI_D11__EMI_D11			0x30b0
+#define MX23_PAD_EMI_D12__EMI_D12			0x30c0
+#define MX23_PAD_EMI_D13__EMI_D13			0x30d0
+#define MX23_PAD_EMI_D14__EMI_D14			0x30e0
+#define MX23_PAD_EMI_D15__EMI_D15			0x30f0
+#define MX23_PAD_EMI_DQM0__EMI_DQM0			0x3100
+#define MX23_PAD_EMI_DQM1__EMI_DQM1			0x3110
+#define MX23_PAD_EMI_DQS0__EMI_DQS0			0x3120
+#define MX23_PAD_EMI_DQS1__EMI_DQS1			0x3130
+#define MX23_PAD_EMI_CLK__EMI_CLK			0x3140
+#define MX23_PAD_EMI_CLKN__EMI_CLKN			0x3150
+#define MX23_PAD_GPMI_D00__LCD_D8			0x0001
+#define MX23_PAD_GPMI_D01__LCD_D9			0x0011
+#define MX23_PAD_GPMI_D02__LCD_D10			0x0021
+#define MX23_PAD_GPMI_D03__LCD_D11			0x0031
+#define MX23_PAD_GPMI_D04__LCD_D12			0x0041
+#define MX23_PAD_GPMI_D05__LCD_D13			0x0051
+#define MX23_PAD_GPMI_D06__LCD_D14			0x0061
+#define MX23_PAD_GPMI_D07__LCD_D15			0x0071
+#define MX23_PAD_GPMI_D08__LCD_D18			0x0081
+#define MX23_PAD_GPMI_D09__LCD_D19			0x0091
+#define MX23_PAD_GPMI_D10__LCD_D20			0x00a1
+#define MX23_PAD_GPMI_D11__LCD_D21			0x00b1
+#define MX23_PAD_GPMI_D12__LCD_D22			0x00c1
+#define MX23_PAD_GPMI_D13__LCD_D23			0x00d1
+#define MX23_PAD_GPMI_D14__AUART2_RX			0x00e1
+#define MX23_PAD_GPMI_D15__AUART2_TX			0x00f1
+#define MX23_PAD_GPMI_CLE__LCD_D16			0x0101
+#define MX23_PAD_GPMI_ALE__LCD_D17			0x0111
+#define MX23_PAD_GPMI_CE2N__ATA_A2			0x0121
+#define MX23_PAD_AUART1_RTS__IR_CLK			0x01b1
+#define MX23_PAD_AUART1_RX__IR_RX			0x01c1
+#define MX23_PAD_AUART1_TX__IR_TX			0x01d1
+#define MX23_PAD_I2C_SCL__GPMI_RDY2			0x01e1
+#define MX23_PAD_I2C_SDA__GPMI_CE2N			0x01f1
+#define MX23_PAD_LCD_D00__ETM_DA8			0x1001
+#define MX23_PAD_LCD_D01__ETM_DA9			0x1011
+#define MX23_PAD_LCD_D02__ETM_DA10			0x1021
+#define MX23_PAD_LCD_D03__ETM_DA11			0x1031
+#define MX23_PAD_LCD_D04__ETM_DA12			0x1041
+#define MX23_PAD_LCD_D05__ETM_DA13			0x1051
+#define MX23_PAD_LCD_D06__ETM_DA14			0x1061
+#define MX23_PAD_LCD_D07__ETM_DA15			0x1071
+#define MX23_PAD_LCD_D08__ETM_DA0			0x1081
+#define MX23_PAD_LCD_D09__ETM_DA1			0x1091
+#define MX23_PAD_LCD_D10__ETM_DA2			0x10a1
+#define MX23_PAD_LCD_D11__ETM_DA3			0x10b1
+#define MX23_PAD_LCD_D12__ETM_DA4			0x10c1
+#define MX23_PAD_LCD_D13__ETM_DA5			0x10d1
+#define MX23_PAD_LCD_D14__ETM_DA6			0x10e1
+#define MX23_PAD_LCD_D15__ETM_DA7			0x10f1
+#define MX23_PAD_LCD_RESET__ETM_TCTL			0x1121
+#define MX23_PAD_LCD_RS__ETM_TCLK			0x1131
+#define MX23_PAD_LCD_DOTCK__GPMI_RDY3			0x1161
+#define MX23_PAD_LCD_ENABLE__I2C_SCL			0x1171
+#define MX23_PAD_LCD_HSYNC__I2C_SDA			0x1181
+#define MX23_PAD_LCD_VSYNC__LCD_BUSY			0x1191
+#define MX23_PAD_PWM0__ROTARYA				0x11a1
+#define MX23_PAD_PWM1__ROTARYB				0x11b1
+#define MX23_PAD_PWM2__GPMI_RDY3			0x11c1
+#define MX23_PAD_PWM3__ETM_TCTL				0x11d1
+#define MX23_PAD_PWM4__ETM_TCLK				0x11e1
+#define MX23_PAD_SSP1_DETECT__GPMI_CE3N			0x2011
+#define MX23_PAD_SSP1_DATA1__I2C_SCL			0x2031
+#define MX23_PAD_SSP1_DATA2__I2C_SDA			0x2041
+#define MX23_PAD_ROTARYA__AUART2_RTS			0x2071
+#define MX23_PAD_ROTARYB__AUART2_CTS			0x2081
+#define MX23_PAD_GPMI_D00__SSP2_DATA0			0x0002
+#define MX23_PAD_GPMI_D01__SSP2_DATA1			0x0012
+#define MX23_PAD_GPMI_D02__SSP2_DATA2			0x0022
+#define MX23_PAD_GPMI_D03__SSP2_DATA3			0x0032
+#define MX23_PAD_GPMI_D04__SSP2_DATA4			0x0042
+#define MX23_PAD_GPMI_D05__SSP2_DATA5			0x0052
+#define MX23_PAD_GPMI_D06__SSP2_DATA6			0x0062
+#define MX23_PAD_GPMI_D07__SSP2_DATA7			0x0072
+#define MX23_PAD_GPMI_D08__SSP1_DATA4			0x0082
+#define MX23_PAD_GPMI_D09__SSP1_DATA5			0x0092
+#define MX23_PAD_GPMI_D10__SSP1_DATA6			0x00a2
+#define MX23_PAD_GPMI_D11__SSP1_DATA7			0x00b2
+#define MX23_PAD_GPMI_D15__GPMI_CE3N			0x00f2
+#define MX23_PAD_GPMI_RDY0__SSP2_DETECT			0x0132
+#define MX23_PAD_GPMI_RDY1__SSP2_CMD			0x0142
+#define MX23_PAD_GPMI_WRN__SSP2_SCK			0x0182
+#define MX23_PAD_AUART1_CTS__SSP1_DATA4			0x01a2
+#define MX23_PAD_AUART1_RTS__SSP1_DATA5			0x01b2
+#define MX23_PAD_AUART1_RX__SSP1_DATA6			0x01c2
+#define MX23_PAD_AUART1_TX__SSP1_DATA7			0x01d2
+#define MX23_PAD_I2C_SCL__AUART1_TX			0x01e2
+#define MX23_PAD_I2C_SDA__AUART1_RX			0x01f2
+#define MX23_PAD_LCD_D08__SAIF2_SDATA0			0x1082
+#define MX23_PAD_LCD_D09__SAIF1_SDATA0			0x1092
+#define MX23_PAD_LCD_D10__SAIF_MCLK_BITCLK		0x10a2
+#define MX23_PAD_LCD_D11__SAIF_LRCLK			0x10b2
+#define MX23_PAD_LCD_D12__SAIF2_SDATA1			0x10c2
+#define MX23_PAD_LCD_D13__SAIF2_SDATA2			0x10d2
+#define MX23_PAD_LCD_D14__SAIF1_SDATA2			0x10e2
+#define MX23_PAD_LCD_D15__SAIF1_SDATA1			0x10f2
+#define MX23_PAD_LCD_D16__SAIF_ALT_BITCLK		0x1102
+#define MX23_PAD_LCD_RESET__GPMI_CE3N			0x1122
+#define MX23_PAD_PWM0__DUART_RX				0x11a2
+#define MX23_PAD_PWM1__DUART_TX				0x11b2
+#define MX23_PAD_PWM3__AUART1_CTS			0x11d2
+#define MX23_PAD_PWM4__AUART1_RTS			0x11e2
+#define MX23_PAD_SSP1_CMD__JTAG_TDO			0x2002
+#define MX23_PAD_SSP1_DETECT__USB_OTG_ID		0x2012
+#define MX23_PAD_SSP1_DATA0__JTAG_TDI			0x2022
+#define MX23_PAD_SSP1_DATA1__JTAG_TCLK			0x2032
+#define MX23_PAD_SSP1_DATA2__JTAG_RTCK			0x2042
+#define MX23_PAD_SSP1_DATA3__JTAG_TMS			0x2052
+#define MX23_PAD_SSP1_SCK__JTAG_TRST			0x2062
+#define MX23_PAD_ROTARYA__SPDIF				0x2072
+#define MX23_PAD_ROTARYB__GPMI_CE3N			0x2082
+#define MX23_PAD_GPMI_D00__GPIO_0_0			0x0003
+#define MX23_PAD_GPMI_D01__GPIO_0_1			0x0013
+#define MX23_PAD_GPMI_D02__GPIO_0_2			0x0023
+#define MX23_PAD_GPMI_D03__GPIO_0_3			0x0033
+#define MX23_PAD_GPMI_D04__GPIO_0_4			0x0043
+#define MX23_PAD_GPMI_D05__GPIO_0_5			0x0053
+#define MX23_PAD_GPMI_D06__GPIO_0_6			0x0063
+#define MX23_PAD_GPMI_D07__GPIO_0_7			0x0073
+#define MX23_PAD_GPMI_D08__GPIO_0_8			0x0083
+#define MX23_PAD_GPMI_D09__GPIO_0_9			0x0093
+#define MX23_PAD_GPMI_D10__GPIO_0_10			0x00a3
+#define MX23_PAD_GPMI_D11__GPIO_0_11			0x00b3
+#define MX23_PAD_GPMI_D12__GPIO_0_12			0x00c3
+#define MX23_PAD_GPMI_D13__GPIO_0_13			0x00d3
+#define MX23_PAD_GPMI_D14__GPIO_0_14			0x00e3
+#define MX23_PAD_GPMI_D15__GPIO_0_15			0x00f3
+#define MX23_PAD_GPMI_CLE__GPIO_0_16			0x0103
+#define MX23_PAD_GPMI_ALE__GPIO_0_17			0x0113
+#define MX23_PAD_GPMI_CE2N__GPIO_0_18			0x0123
+#define MX23_PAD_GPMI_RDY0__GPIO_0_19			0x0133
+#define MX23_PAD_GPMI_RDY1__GPIO_0_20			0x0143
+#define MX23_PAD_GPMI_RDY2__GPIO_0_21			0x0153
+#define MX23_PAD_GPMI_RDY3__GPIO_0_22			0x0163
+#define MX23_PAD_GPMI_WPN__GPIO_0_23			0x0173
+#define MX23_PAD_GPMI_WRN__GPIO_0_24			0x0183
+#define MX23_PAD_GPMI_RDN__GPIO_0_25			0x0193
+#define MX23_PAD_AUART1_CTS__GPIO_0_26			0x01a3
+#define MX23_PAD_AUART1_RTS__GPIO_0_27			0x01b3
+#define MX23_PAD_AUART1_RX__GPIO_0_28			0x01c3
+#define MX23_PAD_AUART1_TX__GPIO_0_29			0x01d3
+#define MX23_PAD_I2C_SCL__GPIO_0_30			0x01e3
+#define MX23_PAD_I2C_SDA__GPIO_0_31			0x01f3
+#define MX23_PAD_LCD_D00__GPIO_1_0			0x1003
+#define MX23_PAD_LCD_D01__GPIO_1_1			0x1013
+#define MX23_PAD_LCD_D02__GPIO_1_2			0x1023
+#define MX23_PAD_LCD_D03__GPIO_1_3			0x1033
+#define MX23_PAD_LCD_D04__GPIO_1_4			0x1043
+#define MX23_PAD_LCD_D05__GPIO_1_5			0x1053
+#define MX23_PAD_LCD_D06__GPIO_1_6			0x1063
+#define MX23_PAD_LCD_D07__GPIO_1_7			0x1073
+#define MX23_PAD_LCD_D08__GPIO_1_8			0x1083
+#define MX23_PAD_LCD_D09__GPIO_1_9			0x1093
+#define MX23_PAD_LCD_D10__GPIO_1_10			0x10a3
+#define MX23_PAD_LCD_D11__GPIO_1_11			0x10b3
+#define MX23_PAD_LCD_D12__GPIO_1_12			0x10c3
+#define MX23_PAD_LCD_D13__GPIO_1_13			0x10d3
+#define MX23_PAD_LCD_D14__GPIO_1_14			0x10e3
+#define MX23_PAD_LCD_D15__GPIO_1_15			0x10f3
+#define MX23_PAD_LCD_D16__GPIO_1_16			0x1103
+#define MX23_PAD_LCD_D17__GPIO_1_17			0x1113
+#define MX23_PAD_LCD_RESET__GPIO_1_18			0x1123
+#define MX23_PAD_LCD_RS__GPIO_1_19			0x1133
+#define MX23_PAD_LCD_WR__GPIO_1_20			0x1143
+#define MX23_PAD_LCD_CS__GPIO_1_21			0x1153
+#define MX23_PAD_LCD_DOTCK__GPIO_1_22			0x1163
+#define MX23_PAD_LCD_ENABLE__GPIO_1_23			0x1173
+#define MX23_PAD_LCD_HSYNC__GPIO_1_24			0x1183
+#define MX23_PAD_LCD_VSYNC__GPIO_1_25			0x1193
+#define MX23_PAD_PWM0__GPIO_1_26			0x11a3
+#define MX23_PAD_PWM1__GPIO_1_27			0x11b3
+#define MX23_PAD_PWM2__GPIO_1_28			0x11c3
+#define MX23_PAD_PWM3__GPIO_1_29			0x11d3
+#define MX23_PAD_PWM4__GPIO_1_30			0x11e3
+#define MX23_PAD_SSP1_CMD__GPIO_2_0			0x2003
+#define MX23_PAD_SSP1_DETECT__GPIO_2_1			0x2013
+#define MX23_PAD_SSP1_DATA0__GPIO_2_2			0x2023
+#define MX23_PAD_SSP1_DATA1__GPIO_2_3			0x2033
+#define MX23_PAD_SSP1_DATA2__GPIO_2_4			0x2043
+#define MX23_PAD_SSP1_DATA3__GPIO_2_5			0x2053
+#define MX23_PAD_SSP1_SCK__GPIO_2_6			0x2063
+#define MX23_PAD_ROTARYA__GPIO_2_7			0x2073
+#define MX23_PAD_ROTARYB__GPIO_2_8			0x2083
+#define MX23_PAD_EMI_A00__GPIO_2_9			0x2093
+#define MX23_PAD_EMI_A01__GPIO_2_10			0x20a3
+#define MX23_PAD_EMI_A02__GPIO_2_11			0x20b3
+#define MX23_PAD_EMI_A03__GPIO_2_12			0x20c3
+#define MX23_PAD_EMI_A04__GPIO_2_13			0x20d3
+#define MX23_PAD_EMI_A05__GPIO_2_14			0x20e3
+#define MX23_PAD_EMI_A06__GPIO_2_15			0x20f3
+#define MX23_PAD_EMI_A07__GPIO_2_16			0x2103
+#define MX23_PAD_EMI_A08__GPIO_2_17			0x2113
+#define MX23_PAD_EMI_A09__GPIO_2_18			0x2123
+#define MX23_PAD_EMI_A10__GPIO_2_19			0x2133
+#define MX23_PAD_EMI_A11__GPIO_2_20			0x2143
+#define MX23_PAD_EMI_A12__GPIO_2_21			0x2153
+#define MX23_PAD_EMI_BA0__GPIO_2_22			0x2163
+#define MX23_PAD_EMI_BA1__GPIO_2_23			0x2173
+#define MX23_PAD_EMI_CASN__GPIO_2_24			0x2183
+#define MX23_PAD_EMI_CE0N__GPIO_2_25			0x2193
+#define MX23_PAD_EMI_CE1N__GPIO_2_26			0x21a3
+#define MX23_PAD_GPMI_CE1N__GPIO_2_27			0x21b3
+#define MX23_PAD_GPMI_CE0N__GPIO_2_28			0x21c3
+#define MX23_PAD_EMI_CKE__GPIO_2_29			0x21d3
+#define MX23_PAD_EMI_RASN__GPIO_2_30			0x21e3
+#define MX23_PAD_EMI_WEN__GPIO_2_31			0x21f3
+
+#endif /* __DT_BINDINGS_MX23_PINCTRL_H__ */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/imx25-pinfunc.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/imx25-pinfunc.h
new file mode 100644
index 0000000000000000000000000000000000000000..a4807062a90f00d3ae58fa7d91e3c55770eaa571
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/imx25-pinfunc.h
@@ -0,0 +1,632 @@
+/*
+ * Copyright 2013 Eukréa Electromatique <denis@eukrea.com>
+ * Based on imx35-pinfunc.h in the same directory Which is:
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __DTS_IMX25_PINFUNC_H
+#define __DTS_IMX25_PINFUNC_H
+
+/*
+ * The pin function ID is a tuple of
+ * <mux_reg conf_reg input_reg mux_mode input_val>
+ */
+
+#define MX25_PAD_A10__A10			0x008 0x000 0x000 0x00 0x000
+#define MX25_PAD_A10__GPIO_4_0			0x008 0x000 0x000 0x05 0x000
+
+#define MX25_PAD_A13__A13			0x00c 0x22C 0x000 0x00 0x000
+#define MX25_PAD_A13__GPIO_4_1			0x00c 0x22C 0x000 0x05 0x000
+#define MX25_PAD_A13__LCDC_CLS			0x00c 0x22C 0x000 0x07 0x000
+
+#define MX25_PAD_A14__A14			0x010 0x230 0x000 0x00 0x000
+#define MX25_PAD_A14__GPIO_2_0			0x010 0x230 0x000 0x05 0x000
+#define MX25_PAD_A14__SIM1_CLK1			0x010 0x230 0x000 0x06 0x000
+#define MX25_PAD_A14__LCDC_SPL			0x010 0x230 0x000 0x07 0x000
+
+#define MX25_PAD_A15__A15			0x014 0x234 0x000 0x00 0x000
+#define MX25_PAD_A15__GPIO_2_1			0x014 0x234 0x000 0x05 0x000
+#define MX25_PAD_A15__SIM1_RST1			0x014 0x234 0x000 0x06 0x000
+#define MX25_PAD_A15__LCDC_PS			0x014 0x234 0x000 0x07 0x000
+
+#define MX25_PAD_A16__A16			0x018 0x000 0x000 0x00 0x000
+#define MX25_PAD_A16__GPIO_2_2			0x018 0x000 0x000 0x05 0x000
+#define MX25_PAD_A16__SIM1_VEN1			0x018 0x000 0x000 0x06 0x000
+#define MX25_PAD_A16__LCDC_REV			0x018 0x000 0x000 0x07 0x000
+
+#define MX25_PAD_A17__A17			0x01c 0x238 0x000 0x00 0x000
+#define MX25_PAD_A17__GPIO_2_3			0x01c 0x238 0x000 0x05 0x000
+#define MX25_PAD_A17__SIM1_TX			0x01c 0x238 0x554 0x06 0x000
+#define MX25_PAD_A17__FEC_TX_ERR		0x01c 0x238 0x000 0x07 0x000
+
+#define MX25_PAD_A18__A18			0x020 0x23c 0x000 0x00 0x000
+#define MX25_PAD_A18__GPIO_2_4			0x020 0x23c 0x000 0x05 0x000
+#define MX25_PAD_A18__SIM1_PD1			0x020 0x23c 0x550 0x06 0x000
+#define MX25_PAD_A18__FEC_COL			0x020 0x23c 0x504 0x07 0x000
+
+#define MX25_PAD_A19__A19			0x024 0x240 0x000 0x00 0x000
+#define MX25_PAD_A19__GPIO_2_5			0x024 0x240 0x000 0x05 0x000
+#define MX25_PAD_A19__SIM1_RX1			0x024 0x240 0x54c 0x06 0x000
+#define MX25_PAD_A19__FEC_RX_ERR		0x024 0x240 0x518 0x07 0x000
+
+#define MX25_PAD_A20__A20			0x028 0x244 0x000 0x00 0x000
+#define MX25_PAD_A20__GPIO_2_6			0x028 0x244 0x000 0x05 0x000
+#define MX25_PAD_A20__SIM2_CLK1			0x028 0x244 0x000 0x06 0x000
+#define MX25_PAD_A20__FEC_RDATA2		0x028 0x244 0x50c 0x07 0x000
+
+#define MX25_PAD_A21__A21			0x02c 0x248 0x000 0x00 0x000
+#define MX25_PAD_A21__GPIO_2_7			0x02c 0x248 0x000 0x05 0x000
+#define MX25_PAD_A21__SIM2_RST1			0x02c 0x248 0x000 0x06 0x000
+#define MX25_PAD_A21__FEC_RDATA3		0x02c 0x248 0x510 0x07 0x000
+
+#define MX25_PAD_A22__A22			0x030 0x000 0x000 0x00 0x000
+#define MX25_PAD_A22__GPIO_2_8			0x030 0x000 0x000 0x05 0x000
+#define MX25_PAD_A22__SIM2_VEN1			0x030 0x000 0x000 0x06 0x000
+#define MX25_PAD_A22__FEC_TDATA2		0x030 0x000 0x000 0x07 0x000
+
+#define MX25_PAD_A23__A23			0x034 0x24c 0x000 0x00 0x000
+#define MX25_PAD_A23__GPIO_2_9			0x034 0x24c 0x000 0x05 0x000
+#define MX25_PAD_A23__SIM2_TX1			0x034 0x24c 0x560 0x06 0x000
+#define MX25_PAD_A23__FEC_TDATA3		0x034 0x24c 0x000 0x07 0x000
+
+#define MX25_PAD_A24__A24			0x038 0x250 0x000 0x00 0x000
+#define MX25_PAD_A24__GPIO_2_10			0x038 0x250 0x000 0x05 0x000
+#define MX25_PAD_A24__SIM2_PD1			0x038 0x250 0x55c 0x06 0x000
+#define MX25_PAD_A24__FEC_RX_CLK		0x038 0x250 0x514 0x07 0x000
+
+#define MX25_PAD_A25__A25			0x03c 0x254 0x000 0x00 0x000
+#define MX25_PAD_A25__GPIO_2_11			0x03c 0x254 0x000 0x05 0x000
+#define MX25_PAD_A25__FEC_CRS			0x03c 0x254 0x508 0x07 0x000
+
+#define MX25_PAD_EB0__EB0			0x040 0x258 0x000 0x00 0x000
+#define MX25_PAD_EB0__AUD4_TXD			0x040 0x258 0x464 0x04 0x000
+#define MX25_PAD_EB0__GPIO_2_12			0x040 0x258 0x000 0x05 0x000
+
+#define MX25_PAD_EB1__EB1			0x044 0x25c 0x000 0x00 0x000
+#define MX25_PAD_EB1__AUD4_RXD			0x044 0x25c 0x460 0x04 0x000
+#define MX25_PAD_EB1__GPIO_2_13			0x044 0x25c 0x000 0x05 0x000
+
+#define MX25_PAD_OE__OE				0x048 0x260 0x000 0x00 0x000
+#define MX25_PAD_OE__AUD4_TXC			0x048 0x260 0x000 0x04 0x000
+#define MX25_PAD_OE__GPIO_2_14			0x048 0x260 0x000 0x05 0x000
+
+#define MX25_PAD_CS0__CS0			0x04c 0x000 0x000 0x00 0x000
+#define MX25_PAD_CS0__GPIO_4_2			0x04c 0x000 0x000 0x05 0x000
+
+#define MX25_PAD_CS1__CS1			0x050 0x000 0x000 0x00 0x000
+#define MX25_PAD_CS1__NF_CE3			0x050 0x000 0x000 0x01 0x000
+#define MX25_PAD_CS1__GPIO_4_3			0x050 0x000 0x000 0x05 0x000
+
+#define MX25_PAD_CS4__CS4			0x054 0x264 0x000 0x00 0x000
+#define MX25_PAD_CS4__NF_CE1			0x054 0x264 0x000 0x01 0x000
+#define MX25_PAD_CS4__UART5_CTS			0x054 0x264 0x000 0x03 0x000
+#define MX25_PAD_CS4__GPIO_3_20			0x054 0x264 0x000 0x05 0x000
+
+#define MX25_PAD_CS5__CS5			0x058 0x268 0x000 0x00 0x000
+#define MX25_PAD_CS5__NF_CE2			0x058 0x268 0x000 0x01 0x000
+#define MX25_PAD_CS5__UART5_RTS			0x058 0x268 0x574 0x03 0x000
+#define MX25_PAD_CS5__GPIO_3_21			0x058 0x268 0x000 0x05 0x000
+
+#define MX25_PAD_NF_CE0__NF_CE0			0x05c 0x26c 0x000 0x00 0x000
+#define MX25_PAD_NF_CE0__GPIO_3_22		0x05c 0x26c 0x000 0x05 0x000
+
+#define MX25_PAD_ECB__ECB			0x060 0x270 0x000 0x00 0x000
+#define MX25_PAD_ECB__UART5_TXD			0x060 0x270 0x000 0x03 0x000
+#define MX25_PAD_ECB__GPIO_3_23			0x060 0x270 0x000 0x05 0x000
+
+#define MX25_PAD_LBA__LBA			0x064 0x274 0x000 0x00 0x000
+#define MX25_PAD_LBA__UART5_RXD			0x064 0x274 0x578 0x03 0x000
+#define MX25_PAD_LBA__GPIO_3_24			0x064 0x274 0x000 0x05 0x000
+
+#define MX25_PAD_BCLK__BCLK			0x068 0x000 0x000 0x00 0x000
+#define MX25_PAD_BCLK__GPIO_4_4			0x068 0x000 0x000 0x05 0x000
+
+#define MX25_PAD_RW__RW				0x06c 0x278 0x000 0x00 0x000
+#define MX25_PAD_RW__AUD4_TXFS			0x06c 0x278 0x474 0x04 0x000
+#define MX25_PAD_RW__GPIO_3_25			0x06c 0x278 0x000 0x05 0x000
+
+#define MX25_PAD_NFWE_B__NFWE_B			0x070 0x000 0x000 0x00 0x000
+#define MX25_PAD_NFWE_B__GPIO_3_26		0x070 0x000 0x000 0x05 0x000
+
+#define MX25_PAD_NFRE_B__NFRE_B			0x074 0x000 0x000 0x00 0x000
+#define MX25_PAD_NFRE_B__GPIO_3_27		0x074 0x000 0x000 0x05 0x000
+
+#define MX25_PAD_NFALE__NFALE			0x078 0x000 0x000 0x00 0x000
+#define MX25_PAD_NFALE__GPIO_3_28		0x078 0x000 0x000 0x05 0x000
+
+#define MX25_PAD_NFCLE__NFCLE			0x07c 0x000 0x000 0x00 0x000
+#define MX25_PAD_NFCLE__GPIO_3_29		0x07c 0x000 0x000 0x05 0x000
+
+#define MX25_PAD_NFWP_B__NFWP_B			0x080 0x000 0x000 0x00 0x000
+#define MX25_PAD_NFWP_B__GPIO_3_30		0x080 0x000 0x000 0x05 0x000
+
+#define MX25_PAD_NFRB__NFRB			0x084 0x27c 0x000 0x00 0x000
+#define MX25_PAD_NFRB__GPIO_3_31		0x084 0x27c 0x000 0x05 0x000
+
+#define MX25_PAD_D15__D15			0x088 0x280 0x000 0x00 0x000
+#define MX25_PAD_D15__LD16			0x088 0x280 0x000 0x01 0x000
+#define MX25_PAD_D15__GPIO_4_5			0x088 0x280 0x000 0x05 0x000
+#define MX25_PAD_D15__ESDHC1_DAT7		0x088 0x280 0x4d8 0x06 0x000
+
+#define MX25_PAD_D14__D14			0x08c 0x284 0x000 0x00 0x000
+#define MX25_PAD_D14__LD17			0x08c 0x284 0x000 0x01 0x000
+#define MX25_PAD_D14__GPIO_4_6			0x08c 0x284 0x000 0x05 0x000
+#define MX25_PAD_D14__ESDHC1_DAT6		0x08c 0x284 0x4d4 0x06 0x000
+
+#define MX25_PAD_D13__D13			0x090 0x288 0x000 0x00 0x000
+#define MX25_PAD_D13__LD18			0x090 0x288 0x000 0x01 0x000
+#define MX25_PAD_D13__GPIO_4_7			0x090 0x288 0x000 0x05 0x000
+#define MX25_PAD_D13__ESDHC1_DAT5		0x090 0x288 0x4d0 0x06 0x000
+
+#define MX25_PAD_D12__D12			0x094 0x28c 0x000 0x00 0x000
+#define MX25_PAD_D12__GPIO_4_8			0x094 0x28c 0x000 0x05 0x000
+#define MX25_PAD_D12__ESDHC1_DAT4		0x094 0x28c 0x4cc 0x06 0x000
+
+#define MX25_PAD_D11__D11			0x098 0x290 0x000 0x00 0x000
+#define MX25_PAD_D11__GPIO_4_9			0x098 0x290 0x000 0x05 0x000
+#define MX25_PAD_D11__USBOTG_PWR		0x098 0x290 0x000 0x06 0x000
+
+#define MX25_PAD_D10__D10			0x09c 0x294 0x000 0x00 0x000
+#define MX25_PAD_D10__GPIO_4_10			0x09c 0x294 0x000 0x05 0x000
+#define MX25_PAD_D10__USBOTG_OC			0x09c 0x294 0x57c 0x06 0x000
+
+#define MX25_PAD_D9__D9				0x0a0 0x298 0x000 0x00 0x000
+#define MX25_PAD_D9__GPIO_4_11			0x0a0 0x298 0x000 0x05 0x000
+#define MX25_PAD_D9__USBH2_PWR			0x0a0 0x298 0x000 0x06 0x000
+
+#define MX25_PAD_D8__D8				0x0a4 0x29c 0x000 0x00 0x000
+#define MX25_PAD_D8__GPIO_4_12			0x0a4 0x29c 0x000 0x05 0x000
+#define MX25_PAD_D8__USBH2_OC			0x0a4 0x29c 0x580 0x06 0x000
+
+#define MX25_PAD_D7__D7				0x0a8 0x2a0 0x000 0x00 0x000
+#define MX25_PAD_D7__GPIO_4_13			0x0a8 0x2a0 0x000 0x05 0x000
+
+#define MX25_PAD_D6__D6				0x0ac 0x2a4 0x000 0x00 0x000
+#define MX25_PAD_D6__GPIO_4_14			0x0ac 0x2a4 0x000 0x05 0x000
+
+#define MX25_PAD_D5__D5				0x0b0 0x2a8 0x000 0x00 0x000
+#define MX25_PAD_D5__GPIO_4_15			0x0b0 0x2a8 0x000 0x05 0x000
+
+#define MX25_PAD_D4__D4				0x0b4 0x2ac 0x000 0x00 0x000
+#define MX25_PAD_D4__GPIO_4_16			0x0b4 0x2ac 0x000 0x05 0x000
+
+#define MX25_PAD_D3__D3				0x0b8 0x2b0 0x000 0x00 0x000
+#define MX25_PAD_D3__GPIO_4_17			0x0b8 0x2b0 0x000 0x05 0x000
+
+#define MX25_PAD_D2__D2				0x0bc 0x2b4 0x000 0x00 0x000
+#define MX25_PAD_D2__GPIO_4_18			0x0bc 0x2b4 0x000 0x05 0x000
+
+#define MX25_PAD_D1__D1				0x0c0 0x2b8 0x000 0x00 0x000
+#define MX25_PAD_D1__GPIO_4_19			0x0c0 0x2b8 0x000 0x05 0x000
+
+#define MX25_PAD_D0__D0				0x0c4 0x2bc 0x000 0x00 0x000
+#define MX25_PAD_D0__GPIO_4_20			0x0c4 0x2bc 0x000 0x05 0x000
+
+#define MX25_PAD_LD0__LD0			0x0c8 0x2c0 0x000 0x00 0x000
+#define MX25_PAD_LD0__CSI_D0			0x0c8 0x2c0 0x488 0x02 0x000
+#define MX25_PAD_LD0__GPIO_2_15			0x0c8 0x2c0 0x000 0x05 0x000
+
+#define MX25_PAD_LD1__LD1			0x0cc 0x2c4 0x000 0x00 0x000
+#define MX25_PAD_LD1__CSI_D1			0x0cc 0x2c4 0x48c 0x02 0x000
+#define MX25_PAD_LD1__GPIO_2_16			0x0cc 0x2c4 0x000 0x05 0x000
+
+#define MX25_PAD_LD2__LD2			0x0d0 0x2c8 0x000 0x00 0x000
+#define MX25_PAD_LD2__GPIO_2_17			0x0d0 0x2c8 0x000 0x05 0x000
+
+#define MX25_PAD_LD3__LD3			0x0d4 0x2cc 0x000 0x00 0x000
+#define MX25_PAD_LD3__GPIO_2_18			0x0d4 0x2cc 0x000 0x05 0x000
+
+#define MX25_PAD_LD4__LD4			0x0d8 0x2d0 0x000 0x00 0x000
+#define MX25_PAD_LD4__GPIO_2_19			0x0d8 0x2d0 0x000 0x05 0x000
+
+#define MX25_PAD_LD5__LD5			0x0dc 0x2d4 0x000 0x00 0x000
+#define MX25_PAD_LD5__GPIO_1_19			0x0dc 0x2d4 0x000 0x05 0x000
+
+#define MX25_PAD_LD6__LD6			0x0e0 0x2d8 0x000 0x00 0x000
+#define MX25_PAD_LD6__GPIO_1_20			0x0e0 0x2d8 0x000 0x05 0x000
+
+#define MX25_PAD_LD7__LD7			0x0e4 0x2dc 0x000 0x00 0x000
+#define MX25_PAD_LD7__GPIO_1_21			0x0e4 0x2dc 0x000 0x05 0x000
+
+#define MX25_PAD_LD8__LD8			0x0e8 0x2e0 0x000 0x00 0x000
+#define MX25_PAD_LD8__UART4_RXD			0x0e8 0x2e0 0x570 0x02 0x000
+#define MX25_PAD_LD8__FEC_TX_ERR		0x0e8 0x2e0 0x000 0x05 0x000
+/* SION must be set; see the comment for MX25_PAD_SD1_CMD__ESDHC1_CMD. */
+#define MX25_PAD_LD8__ESDHC2_CMD		0x0e8 0x2e0 0x4e0 0x16 0x000
+
+#define MX25_PAD_LD9__LD9			0x0ec 0x2e4 0x000 0x00 0x000
+#define MX25_PAD_LD9__UART4_TXD			0x0ec 0x2e4 0x000 0x02 0x000
+#define MX25_PAD_LD9__FEC_COL			0x0ec 0x2e4 0x504 0x05 0x001
+#define MX25_PAD_LD9__ESDHC2_CLK		0x0ec 0x2e4 0x4dc 0x06 0x000
+
+#define MX25_PAD_LD10__LD10			0x0f0 0x2e8 0x000 0x00 0x000
+#define MX25_PAD_LD10__UART4_RTS		0x0f0 0x2e8 0x56c 0x02 0x000
+#define MX25_PAD_LD10__FEC_RX_ERR		0x0f0 0x2e8 0x518 0x05 0x001
+
+#define MX25_PAD_LD11__LD11			0x0f4 0x2ec 0x000 0x00 0x000
+#define MX25_PAD_LD11__UART4_CTS		0x0f4 0x2ec 0x000 0x02 0x000
+#define MX25_PAD_LD11__FEC_RDATA2		0x0f4 0x2ec 0x50c 0x05 0x001
+#define MX25_PAD_LD11__ESDHC2_DAT1		0x0f4 0x2ec 0x4e8 0x06 0x000
+
+#define MX25_PAD_LD12__LD12			0x0f8 0x2f0 0x000 0x00 0x000
+#define MX25_PAD_LD12__CSPI2_MOSI		0x0f8 0x2f0 0x4a0 0x02 0x000
+#define MX25_PAD_LD12__FEC_RDATA3		0x0f8 0x2f0 0x510 0x05 0x001
+
+#define MX25_PAD_LD13__LD13			0x0fc 0x2f4 0x000 0x00 0x000
+#define MX25_PAD_LD13__CSPI2_MISO		0x0fc 0x2f4 0x49c 0x02 0x000
+#define MX25_PAD_LD13__FEC_TDATA2		0x0fc 0x2f4 0x000 0x05 0x000
+
+#define MX25_PAD_LD14__LD14			0x100 0x2f8 0x000 0x00 0x000
+#define MX25_PAD_LD14__CSPI2_SCLK		0x100 0x2f8 0x494 0x02 0x000
+#define MX25_PAD_LD14__FEC_TDATA3		0x100 0x2f8 0x000 0x05 0x000
+
+#define MX25_PAD_LD15__LD15			0x104 0x2fc 0x000 0x00 0x000
+#define MX25_PAD_LD15__CSPI2_RDY		0x104 0x2fc 0x498 0x02 0x000
+#define MX25_PAD_LD15__FEC_RX_CLK		0x104 0x2fc 0x514 0x05 0x001
+
+#define MX25_PAD_HSYNC__HSYNC			0x108 0x300 0x000 0x00 0x000
+#define MX25_PAD_HSYNC__GPIO_1_22		0x108 0x300 0x000 0x05 0x000
+
+#define MX25_PAD_VSYNC__VSYNC			0x10c 0x304 0x000 0x00 0x000
+#define MX25_PAD_VSYNC__GPIO_1_23		0x10c 0x304 0x000 0x05 0x000
+
+#define MX25_PAD_LSCLK__LSCLK			0x110 0x308 0x000 0x00 0x000
+#define MX25_PAD_LSCLK__GPIO_1_24		0x110 0x308 0x000 0x05 0x000
+
+#define MX25_PAD_OE_ACD__OE_ACD			0x114 0x30c 0x000 0x00 0x000
+#define MX25_PAD_OE_ACD__CSPI2_SS0		0x114 0x30c 0x4a4 0x02 0x000
+#define MX25_PAD_OE_ACD__GPIO_1_25		0x114 0x30c 0x000 0x05 0x000
+
+#define MX25_PAD_CONTRAST__CONTRAST		0x118 0x310 0x000 0x00 0x000
+#define MX25_PAD_CONTRAST__CC4			0x118 0x310 0x000 0x01 0x000
+#define MX25_PAD_CONTRAST__PWM4_PWMO		0x118 0x310 0x000 0x04 0x000
+#define MX25_PAD_CONTRAST__FEC_CRS		0x118 0x310 0x508 0x05 0x001
+#define MX25_PAD_CONTRAST__USBH2_PWR		0x118 0x310 0x000 0x06 0x000
+
+#define MX25_PAD_PWM__PWM			0x11c 0x314 0x000 0x00 0x000
+#define MX25_PAD_PWM__GPIO_1_26			0x11c 0x314 0x000 0x05 0x000
+#define MX25_PAD_PWM__USBH2_OC			0x11c 0x314 0x580 0x06 0x001
+
+#define MX25_PAD_CSI_D2__CSI_D2			0x120 0x318 0x000 0x00 0x000
+#define MX25_PAD_CSI_D2__UART5_RXD		0x120 0x318 0x578 0x01 0x001
+#define MX25_PAD_CSI_D2__SIM1_CLK0		0x120 0x318 0x000 0x04 0x000
+#define MX25_PAD_CSI_D2__GPIO_1_27		0x120 0x318 0x000 0x05 0x000
+#define MX25_PAD_CSI_D2__CSPI3_MOSI		0x120 0x318 0x000 0x07 0x000
+
+#define MX25_PAD_CSI_D3__CSI_D3			0x124 0x31c 0x000 0x00 0x000
+#define MX25_PAD_CSI_D3__UART5_TXD		0x124 0x31c 0x000 0x01 0x000
+#define MX25_PAD_CSI_D3__SIM1_RST0		0x124 0x31c 0x000 0x04 0x000
+#define MX25_PAD_CSI_D3__GPIO_1_28		0x124 0x31c 0x000 0x05 0x000
+#define MX25_PAD_CSI_D3__CSPI3_MISO		0x124 0x31c 0x4b4 0x07 0x001
+
+#define MX25_PAD_CSI_D4__CSI_D4			0x128 0x320 0x000 0x00 0x000
+#define MX25_PAD_CSI_D4__UART5_RTS		0x128 0x320 0x574 0x01 0x001
+#define MX25_PAD_CSI_D4__SIM1_VEN0		0x128 0x320 0x000 0x04 0x000
+#define MX25_PAD_CSI_D4__GPIO_1_29		0x128 0x320 0x000 0x05 0x000
+#define MX25_PAD_CSI_D4__CSPI3_SCLK		0x128 0x320 0x000 0x07 0x000
+
+#define MX25_PAD_CSI_D5__CSI_D5			0x12c 0x324 0x000 0x00 0x000
+#define MX25_PAD_CSI_D5__UART5_CTS		0x12c 0x324 0x000 0x01 0x000
+#define MX25_PAD_CSI_D5__SIM1_TX0		0x12c 0x324 0x000 0x04 0x000
+#define MX25_PAD_CSI_D5__GPIO_1_30		0x12c 0x324 0x000 0x05 0x000
+#define MX25_PAD_CSI_D5__CSPI3_RDY		0x12c 0x324 0x000 0x07 0x000
+
+#define MX25_PAD_CSI_D6__CSI_D6			0x130 0x328 0x000 0x00 0x000
+/* SION must be set; see the comment for MX25_PAD_SD1_CMD__ESDHC1_CMD. */
+#define MX25_PAD_CSI_D6__ESDHC2_CMD		0x130 0x328 0x4e0 0x12 0x001
+#define MX25_PAD_CSI_D6__SIM1_PD0		0x130 0x328 0x000 0x04 0x000
+#define MX25_PAD_CSI_D6__GPIO_1_31		0x130 0x328 0x000 0x05 0x000
+
+#define MX25_PAD_CSI_D7__CSI_D7			0x134 0x32c 0x000 0x00 0x000
+#define MX25_PAD_CSI_D7__ESDHC2_CLK		0x134 0x32C 0x4dc 0x02 0x001
+#define MX25_PAD_CSI_D7__GPIO_1_6		0x134 0x32c 0x000 0x05 0x000
+
+#define MX25_PAD_CSI_D8__CSI_D8			0x138 0x330 0x000 0x00 0x000
+#define MX25_PAD_CSI_D8__AUD6_RXC		0x138 0x330 0x000 0x02 0x000
+#define MX25_PAD_CSI_D8__GPIO_1_7		0x138 0x330 0x000 0x05 0x000
+#define MX25_PAD_CSI_D8__CSPI3_SS2		0x138 0x330 0x4c4 0x07 0x000
+
+#define MX25_PAD_CSI_D9__CSI_D9			0x13c 0x334 0x000 0x00 0x000
+#define MX25_PAD_CSI_D9__AUD6_RXFS		0x13c 0x334 0x000 0x02 0x000
+#define MX25_PAD_CSI_D9__GPIO_4_21		0x13c 0x334 0x000 0x05 0x000
+#define MX25_PAD_CSI_D9__CSPI3_SS3		0x13c 0x334 0x4c8 0x07 0x000
+
+#define MX25_PAD_CSI_MCLK__CSI_MCLK		0x140 0x338 0x000 0x00 0x000
+#define MX25_PAD_CSI_MCLK__AUD6_TXD		0x140 0x338 0x000 0x01 0x000
+#define MX25_PAD_CSI_MCLK__ESDHC2_DAT0		0x140 0x338 0x4e4 0x02 0x001
+#define MX25_PAD_CSI_MCLK__GPIO_1_8		0x140 0x338 0x000 0x05 0x000
+
+#define MX25_PAD_CSI_VSYNC__CSI_VSYNC		0x144 0x33c 0x000 0x00 0x000
+#define MX25_PAD_CSI_VSYNC__AUD6_RXD		0x144 0x33c 0x000 0x01 0x000
+#define MX25_PAD_CSI_VSYNC__ESDHC2_DAT1		0x144 0x33c 0x4e8 0x02 0x001
+#define MX25_PAD_CSI_VSYNC__GPIO_1_9		0x144 0x33c 0x000 0x05 0x000
+
+#define MX25_PAD_CSI_HSYNC__CSI_HSYNC		0x148 0x340 0x000 0x00 0x000
+#define MX25_PAD_CSI_HSYNC__AUD6_TXC		0x148 0x340 0x000 0x01 0x000
+#define MX25_PAD_CSI_HSYNC__ESDHC2_DAT2		0x148 0x340 0x4ec 0x02 0x001
+#define MX25_PAD_CSI_HSYNC__GPIO_1_10		0x148 0x340 0x000 0x05 0x000
+
+#define MX25_PAD_CSI_PIXCLK__CSI_PIXCLK		0x14c 0x344 0x000 0x00 0x000
+#define MX25_PAD_CSI_PIXCLK__AUD6_TXFS		0x14c 0x344 0x000 0x01 0x000
+#define MX25_PAD_CSI_PIXCLK__ESDHC2_DAT3	0x14c 0x344 0x4f0 0x02 0x001
+#define MX25_PAD_CSI_PIXCLK__GPIO_1_11		0x14c 0x344 0x000 0x05 0x000
+
+#define MX25_PAD_I2C1_CLK__I2C1_CLK		0x150 0x348 0x000 0x00 0x000
+#define MX25_PAD_I2C1_CLK__GPIO_1_12		0x150 0x348 0x000 0x05 0x000
+
+#define MX25_PAD_I2C1_DAT__I2C1_DAT		0x154 0x34c 0x000 0x00 0x000
+#define MX25_PAD_I2C1_DAT__GPIO_1_13		0x154 0x34c 0x000 0x05 0x000
+
+#define MX25_PAD_CSPI1_MOSI__CSPI1_MOSI		0x158 0x350 0x000 0x00 0x000
+#define MX25_PAD_CSPI1_MOSI__UART3_RXD		0x158 0x350 0x568 0x02 0x000
+#define MX25_PAD_CSPI1_MOSI__GPIO_1_14		0x158 0x350 0x000 0x05 0x000
+
+#define MX25_PAD_CSPI1_MISO__CSPI1_MISO		0x15c 0x354 0x000 0x00 0x000
+#define MX25_PAD_CSPI1_MISO__UART3_TXD		0x15c 0x354 0x000 0x02 0x000
+#define MX25_PAD_CSPI1_MISO__GPIO_1_15		0x15c 0x354 0x000 0x05 0x000
+
+#define MX25_PAD_CSPI1_SS0__CSPI1_SS0		0x160 0x358 0x000 0x00 0x000
+#define MX25_PAD_CSPI1_SS0__PWM2_PWMO		0x160 0x358 0x000 0x02 0x000
+#define MX25_PAD_CSPI1_SS0__GPIO_1_16		0x160 0x358 0x000 0x05 0x000
+
+#define MX25_PAD_CSPI1_SS1__CSPI1_SS1		0x164 0x35c 0x000 0x00 0x000
+#define MX25_PAD_CSPI1_SS1__I2C3_DAT		0x164 0x35C 0x528 0x01 0x001
+#define MX25_PAD_CSPI1_SS1__UART3_RTS		0x164 0x35c 0x000 0x02 0x000
+#define MX25_PAD_CSPI1_SS1__GPIO_1_17		0x164 0x35c 0x000 0x05 0x000
+
+#define MX25_PAD_CSPI1_SCLK__CSPI1_SCLK		0x168 0x360 0x000 0x00 0x000
+#define MX25_PAD_CSPI1_SCLK__UART3_CTS		0x168 0x360 0x000 0x02 0x000
+#define MX25_PAD_CSPI1_SCLK__GPIO_1_18		0x168 0x360 0x000 0x05 0x000
+
+#define MX25_PAD_CSPI1_RDY__CSPI1_RDY		0x16c 0x364 0x000 0x00 0x000
+#define MX25_PAD_CSPI1_RDY__GPIO_2_22		0x16c 0x364 0x000 0x05 0x000
+
+#define MX25_PAD_UART1_RXD__UART1_RXD		0x170 0x368 0x000 0x00 0x000
+#define MX25_PAD_UART1_RXD__UART2_DTR		0x170 0x368 0x000 0x03 0x000
+#define MX25_PAD_UART1_RXD__GPIO_4_22		0x170 0x368 0x000 0x05 0x000
+
+#define MX25_PAD_UART1_TXD__UART1_TXD		0x174 0x36c 0x000 0x00 0x000
+#define MX25_PAD_UART1_TXD__UART2_DSR		0x174 0x36c 0x000 0x03 0x000
+#define MX25_PAD_UART1_TXD__GPIO_4_23		0x174 0x36c 0x000 0x05 0x000
+
+#define MX25_PAD_UART1_RTS__UART1_RTS		0x178 0x370 0x000 0x00 0x000
+#define MX25_PAD_UART1_RTS__CSI_D0		0x178 0x370 0x488 0x01 0x001
+#define MX25_PAD_UART1_RTS__CC3			0x178 0x370 0x000 0x02 0x000
+#define MX25_PAD_UART1_RTS__UART2_DCD		0x178 0x370 0x000 0x03 0x000
+#define MX25_PAD_UART1_RTS__GPIO_4_24		0x178 0x370 0x000 0x05 0x000
+
+#define MX25_PAD_UART1_CTS__UART1_CTS		0x17c 0x374 0x000 0x00 0x000
+#define MX25_PAD_UART1_CTS__CSI_D1		0x17c 0x374 0x48c 0x01 0x001
+#define MX25_PAD_UART1_CTS__UART2_RI		0x17c 0x374 0x000 0x03 0x001
+#define MX25_PAD_UART1_CTS__GPIO_4_25		0x17c 0x374 0x000 0x05 0x000
+
+#define MX25_PAD_UART2_RXD__UART2_RXD		0x180 0x378 0x000 0x00 0x000
+#define MX25_PAD_UART2_RXD__GPIO_4_26		0x180 0x378 0x000 0x05 0x000
+
+#define MX25_PAD_UART2_TXD__UART2_TXD		0x184 0x37c 0x000 0x00 0x000
+#define MX25_PAD_UART2_TXD__GPIO_4_27		0x184 0x37c 0x000 0x05 0x000
+
+#define MX25_PAD_UART2_RTS__UART2_RTS		0x188 0x380 0x000 0x00 0x000
+#define MX25_PAD_UART2_RTS__FEC_COL		0x188 0x380 0x504 0x02 0x002
+#define MX25_PAD_UART2_RTS__CC1			0x188 0x380 0x000 0x03 0x000
+#define MX25_PAD_UART2_RTS__GPIO_4_28		0x188 0x380 0x000 0x05 0x000
+
+#define MX25_PAD_UART2_CTS__UART2_CTS		0x18c 0x384 0x000 0x00 0x000
+#define MX25_PAD_UART2_CTS__FEC_RX_ERR		0x18c 0x384 0x518 0x02 0x002
+#define MX25_PAD_UART2_CTS__GPIO_4_29		0x18c 0x384 0x000 0x05 0x000
+
+/*
+ * Removing the SION bit from MX25_PAD_*__ESDHCn_CMD breaks detecting an SD
+ * card. According to the i.MX25 reference manual (e.g. Figure 23-2 in IMX25RM
+ * Rev. 2 from 01/2011) this pin is bidirectional. So it seems to be a silicon
+ * bug that configuring the ESDHCn_CMD function doesn't enable the input path
+ * for this pin.
+ * This might have side effects for other hardware units that are connected to
+ * that pin and use the respective function as input.
+ */
+#define MX25_PAD_SD1_CMD__ESDHC1_CMD		0x190 0x388 0x000 0x10 0x000
+#define MX25_PAD_SD1_CMD__CSPI2_MOSI		0x190 0x388 0x4a0 0x01 0x001
+#define MX25_PAD_SD1_CMD__FEC_RDATA2		0x190 0x388 0x50c 0x02 0x002
+#define MX25_PAD_SD1_CMD__GPIO_2_23		0x190 0x388 0x000 0x05 0x000
+
+#define MX25_PAD_SD1_CLK__ESDHC1_CLK		0x194 0x38c 0x000 0x00 0x000
+#define MX25_PAD_SD1_CLK__CSPI2_MISO		0x194 0x38c 0x49c 0x01 0x001
+#define MX25_PAD_SD1_CLK__FEC_RDATA3		0x194 0x38c 0x510 0x02 0x002
+#define MX25_PAD_SD1_CLK__GPIO_2_24		0x194 0x38c 0x000 0x05 0x000
+
+#define MX25_PAD_SD1_DATA0__ESDHC1_DAT0		0x198 0x390 0x000 0x00 0x000
+#define MX25_PAD_SD1_DATA0__CSPI2_SCLK		0x198 0x390 0x494 0x01 0x001
+#define MX25_PAD_SD1_DATA0__GPIO_2_25		0x198 0x390 0x000 0x05 0x000
+
+#define MX25_PAD_SD1_DATA1__ESDHC1_DAT1		0x19c 0x394 0x000 0x00 0x000
+#define MX25_PAD_SD1_DATA1__AUD7_RXD		0x19c 0x394 0x478 0x03 0x000
+#define MX25_PAD_SD1_DATA1__GPIO_2_26		0x19c 0x394 0x000 0x05 0x000
+
+#define MX25_PAD_SD1_DATA2__ESDHC1_DAT2		0x1a0 0x398 0x000 0x00 0x000
+#define MX25_PAD_SD1_DATA2__FEC_RX_CLK		0x1a0 0x398 0x514 0x02 0x002
+#define MX25_PAD_SD1_DATA2__GPIO_2_27		0x1a0 0x398 0x000 0x05 0x000
+
+#define MX25_PAD_SD1_DATA3__ESDHC1_DAT3		0x1a4 0x39c 0x000 0x00 0x000
+#define MX25_PAD_SD1_DATA3__FEC_CRS		0x1a4 0x39c 0x508 0x02 0x002
+#define MX25_PAD_SD1_DATA3__GPIO_2_28		0x1a4 0x39c 0x000 0x05 0x000
+
+#define MX25_PAD_KPP_ROW0__KPP_ROW0		0x1a8 0x3a0 0x000 0x00 0x000
+#define MX25_PAD_KPP_ROW0__UART3_RXD		0x1a8 0x3a0 0x568 0x01 0x001
+#define MX25_PAD_KPP_ROW0__UART1_DTR		0x1a8 0x3a0 0x000 0x04 0x000
+#define MX25_PAD_KPP_ROW0__GPIO_2_29		0x1a8 0x3a0 0x000 0x05 0x000
+
+#define MX25_PAD_KPP_ROW1__KPP_ROW1		0x1ac 0x3a4 0x000 0x00 0x000
+#define MX25_PAD_KPP_ROW1__UART3_TXD		0x1ac 0x3a4 0x000 0x01 0x000
+#define MX25_PAD_KPP_ROW1__UART1_DSR		0x1ac 0x3a4 0x000 0x04 0x000
+#define MX25_PAD_KPP_ROW1__GPIO_2_30		0x1ac 0x3a4 0x000 0x05 0x000
+
+#define MX25_PAD_KPP_ROW2__KPP_ROW2		0x1b0 0x3a8 0x000 0x00 0x000
+#define MX25_PAD_KPP_ROW2__UART3_RTS		0x1b0 0x3a8 0x000 0x01 0x000
+#define MX25_PAD_KPP_ROW2__CSI_D0		0x1b0 0x3a8 0x488 0x03 0x002
+#define MX25_PAD_KPP_ROW2__UART1_DCD		0x1b0 0x3a8 0x000 0x04 0x000
+#define MX25_PAD_KPP_ROW2__GPIO_2_31		0x1b0 0x3a8 0x000 0x05 0x000
+
+#define MX25_PAD_KPP_ROW3__KPP_ROW3		0x1b4 0x3ac 0x000 0x00 0x000
+#define MX25_PAD_KPP_ROW3__UART3_CTS		0x1b4 0x3ac 0x000 0x01 0x000
+#define MX25_PAD_KPP_ROW3__CSI_D1		0x1b4 0x3ac 0x48c 0x03 0x002
+#define MX25_PAD_KPP_ROW3__UART1_RI		0x1b4 0x3ac 0x000 0x04 0x000
+#define MX25_PAD_KPP_ROW3__GPIO_3_0		0x1b4 0x3ac 0x000 0x05 0x000
+
+#define MX25_PAD_KPP_COL0__KPP_COL0		0x1b8 0x3b0 0x000 0x00 0x000
+#define MX25_PAD_KPP_COL0__UART4_RXD		0x1b8 0x3b0 0x570 0x01 0x001
+#define MX25_PAD_KPP_COL0__AUD5_TXD		0x1b8 0x3b0 0x000 0x02 0x000
+#define MX25_PAD_KPP_COL0__GPIO_3_1		0x1b8 0x3b0 0x000 0x05 0x000
+
+#define MX25_PAD_KPP_COL1__KPP_COL1		0x1bc 0x3b4 0x000 0x00 0x000
+#define MX25_PAD_KPP_COL1__UART4_TXD		0x1bc 0x3b4 0x000 0x01 0x000
+#define MX25_PAD_KPP_COL1__AUD5_RXD		0x1bc 0x3b4 0x000 0x02 0x000
+#define MX25_PAD_KPP_COL1__GPIO_3_2		0x1bc 0x3b4 0x000 0x05 0x000
+
+#define MX25_PAD_KPP_COL2__KPP_COL2		0x1c0 0x3b8 0x000 0x00 0x000
+#define MX25_PAD_KPP_COL2__UART4_RTS		0x1c0 0x3b8 0x56c 0x01 0x001
+#define MX25_PAD_KPP_COL2__AUD5_TXC		0x1c0 0x3b8 0x000 0x02 0x000
+#define MX25_PAD_KPP_COL2__GPIO_3_3		0x1c0 0x3b8 0x000 0x05 0x000
+
+#define MX25_PAD_KPP_COL3__KPP_COL3		0x1c4 0x3bc 0x000 0x00 0x000
+#define MX25_PAD_KPP_COL3__UART4_CTS		0x1c4 0x3bc 0x000 0x01 0x000
+#define MX25_PAD_KPP_COL3__AUD5_TXFS		0x1c4 0x3bc 0x000 0x02 0x000
+#define MX25_PAD_KPP_COL3__GPIO_3_4		0x1c4 0x3bc 0x000 0x05 0x000
+
+#define MX25_PAD_FEC_MDC__FEC_MDC		0x1c8 0x3c0 0x000 0x00 0x000
+/* SION must be set; see the comment for MX25_PAD_SD1_CMD__ESDHC1_CMD. */
+#define MX25_PAD_FEC_MDC__ESDHC2_CMD		0x1c8 0x3c0 0x4e0 0x11 0x002
+#define MX25_PAD_FEC_MDC__AUD4_TXD		0x1c8 0x3c0 0x464 0x02 0x001
+#define MX25_PAD_FEC_MDC__GPIO_3_5		0x1c8 0x3c0 0x000 0x05 0x000
+
+#define MX25_PAD_FEC_MDIO__FEC_MDIO		0x1cc 0x3c4 0x000 0x00 0x000
+#define MX25_PAD_FEC_MDIO__AUD4_RXD		0x1cc 0x3c4 0x460 0x02 0x001
+#define MX25_PAD_FEC_MDIO__GPIO_3_6		0x1cc 0x3c4 0x000 0x05 0x000
+
+#define MX25_PAD_FEC_TDATA0__FEC_TDATA0		0x1d0 0x3c8 0x000 0x00 0x000
+#define MX25_PAD_FEC_TDATA0__GPIO_3_7		0x1d0 0x3c8 0x000 0x05 0x000
+
+#define MX25_PAD_FEC_TDATA1__FEC_TDATA1		0x1d4 0x3cc 0x000 0x00 0x000
+#define MX25_PAD_FEC_TDATA1__AUD4_TXFS		0x1d4 0x3cc 0x474 0x02 0x001
+#define MX25_PAD_FEC_TDATA1__GPIO_3_8		0x1d4 0x3cc 0x000 0x05 0x000
+
+#define MX25_PAD_FEC_TX_EN__FEC_TX_EN		0x1d8 0x3d0 0x000 0x00 0x000
+#define MX25_PAD_FEC_TX_EN__GPIO_3_9		0x1d8 0x3d0 0x000 0x05 0x000
+
+#define MX25_PAD_FEC_RDATA0__FEC_RDATA0		0x1dc 0x3d4 0x000 0x00 0x000
+#define MX25_PAD_FEC_RDATA0__GPIO_3_10		0x1dc 0x3d4 0x000 0x05 0x000
+
+#define MX25_PAD_FEC_RDATA1__FEC_RDATA1		0x1e0 0x3d8 0x000 0x00 0x000
+/*
+ * According to the i.MX25 Reference manual (IMX25RM, Rev. 2,
+ * 01/2011) this is CAN1_TX but that's wrong.
+ */
+#define MX25_PAD_FEC_RDATA1__CAN2_TX		0x1e0 0x3d8 0x000 0x04 0x000
+#define MX25_PAD_FEC_RDATA1__GPIO_3_11		0x1e0 0x3d8 0x000 0x05 0x000
+
+#define MX25_PAD_FEC_RX_DV__FEC_RX_DV		0x1e4 0x3dc 0x000 0x00 0x000
+/*
+ * According to the i.MX25 Reference manual (IMX25RM, Rev. 2,
+ * 01/2011) this is CAN1_RX but that's wrong.
+ */
+#define MX25_PAD_FEC_RX_DV__CAN2_RX		0x1e4 0x3dc 0x484 0x04 0x000
+#define MX25_PAD_FEC_RX_DV__GPIO_3_12		0x1e4 0x3dc 0x000 0x05 0x000
+
+#define MX25_PAD_FEC_TX_CLK__FEC_TX_CLK		0x1e8 0x3e0 0x000 0x00 0x000
+#define MX25_PAD_FEC_TX_CLK__GPIO_3_13		0x1e8 0x3e0 0x000 0x05 0x000
+
+#define MX25_PAD_RTCK__RTCK			0x1ec 0x3e4 0x000 0x00 0x000
+#define MX25_PAD_RTCK__OWIRE			0x1ec 0x3e4 0x000 0x01 0x000
+#define MX25_PAD_RTCK__GPIO_3_14		0x1ec 0x3e4 0x000 0x05 0x000
+
+#define MX25_PAD_TDO__TDO			0x000 0x3e8 0x000 0x00 0x000
+
+#define MX25_PAD_DE_B__DE_B			0x1f0 0x3ec 0x000 0x00 0x000
+#define MX25_PAD_DE_B__GPIO_2_20		0x1f0 0x3ec 0x000 0x05 0x000
+
+#define MX25_PAD_GPIO_A__GPIO_A			0x1f4 0x3f0 0x000 0x00 0x000
+#define MX25_PAD_GPIO_A__CAN1_TX		0x1f4 0x3f0 0x000 0x06 0x000
+#define MX25_PAD_GPIO_A__USBOTG_PWR		0x1f4 0x3f0 0x000 0x02 0x000
+
+#define MX25_PAD_GPIO_B__GPIO_B			0x1f8 0x3f4 0x000 0x00 0x000
+#define MX25_PAD_GPIO_B__USBOTG_OC		0x1f8 0x3f4 0x57c 0x02 0x001
+#define MX25_PAD_GPIO_B__CAN1_RX		0x1f8 0x3f4 0x480 0x06 0x001
+
+#define MX25_PAD_GPIO_C__GPIO_C			0x1fc 0x3f8 0x000 0x00 0x000
+#define MX25_PAD_GPIO_C__PWM4_PWMO		0x1fc 0x3f8 0x000 0x01 0x000
+#define MX25_PAD_GPIO_C__I2C2_SCL		0x1fc 0x3f8 0x51c 0x02 0x001
+#define MX25_PAD_GPIO_C__KPP_COL4		0x1fc 0x3f8 0x52c 0x03 0x001
+#define MX25_PAD_GPIO_C__CAN2_TX		0x1fc 0x3f8 0x000 0x06 0x000
+
+#define MX25_PAD_GPIO_D__GPIO_D			0x200 0x3fc 0x000 0x00 0x000
+#define MX25_PAD_GPIO_D__I2C2_SDA		0x200 0x3fc 0x520 0x02 0x001
+#define MX25_PAD_GPIO_D__CAN2_RX		0x200 0x3fc 0x484 0x06 0x001
+
+#define MX25_PAD_GPIO_E__GPIO_E			0x204 0x400 0x000 0x00 0x000
+#define MX25_PAD_GPIO_E__I2C3_CLK		0x204 0x400 0x524 0x01 0x002
+#define MX25_PAD_GPIO_E__LD16			0x204 0x400 0x000 0x02 0x000
+#define MX25_PAD_GPIO_E__AUD7_TXD		0x204 0x400 0x000 0x04 0x000
+#define MX25_PAD_GPIO_E__UART4_RXD		0x204 0x400 0x570 0x06 0x002
+
+#define MX25_PAD_GPIO_F__GPIO_F			0x208 0x404 0x000 0x00 0x000
+#define MX25_PAD_GPIO_F__LD17			0x208 0x404 0x000 0x02 0x000
+#define MX25_PAD_GPIO_F__AUD7_TXC		0x208 0x404 0x000 0x04 0x000
+#define MX25_PAD_GPIO_F__UART4_TXD		0x208 0x404 0x000 0x06 0x000
+
+#define MX25_PAD_EXT_ARMCLK__EXT_ARMCLK		0x20c 0x000 0x000 0x00 0x000
+#define MX25_PAD_EXT_ARMCLK__GPIO_3_15		0x20c 0x000 0x000 0x05 0x000
+
+#define MX25_PAD_UPLL_BYPCLK__UPLL_BYPCLK	0x210 0x000 0x000 0x00 0x000
+#define MX25_PAD_UPLL_BYPCLK__GPIO_3_16		0x210 0x000 0x000 0x05 0x000
+
+#define MX25_PAD_VSTBY_REQ__VSTBY_REQ		0x214 0x408 0x000 0x00 0x000
+#define MX25_PAD_VSTBY_REQ__AUD7_TXFS		0x214 0x408 0x000 0x04 0x000
+#define MX25_PAD_VSTBY_REQ__GPIO_3_17		0x214 0x408 0x000 0x05 0x000
+#define MX25_PAD_VSTBY_REQ__UART4_RTS		0x214 0x408 0x56c 0x06 0x002
+
+#define MX25_PAD_VSTBY_ACK__VSTBY_ACK		0x218 0x40c 0x000 0x00 0x000
+#define MX25_PAD_VSTBY_ACK__GPIO_3_18		0x218 0x40c 0x000 0x05 0x000
+
+#define MX25_PAD_POWER_FAIL__POWER_FAIL		0x21c 0x410 0x000 0x00 0x000
+#define MX25_PAD_POWER_FAIL__AUD7_RXD		0x21c 0x410 0x478 0x04 0x001
+#define MX25_PAD_POWER_FAIL__GPIO_3_19		0x21c 0x410 0x000 0x05 0x000
+#define MX25_PAD_POWER_FAIL__UART4_CTS		0x21c 0x410 0x000 0x06 0x000
+
+#define MX25_PAD_CLKO__CLKO			0x220 0x414 0x000 0x00 0x000
+#define MX25_PAD_CLKO__GPIO_2_21		0x220 0x414 0x000 0x05 0x000
+
+#define MX25_PAD_BOOT_MODE0__BOOT_MODE0		0x224 0x000 0x000 0x00 0x000
+#define MX25_PAD_BOOT_MODE0__GPIO_4_30		0x224 0x000 0x000 0x05 0x000
+
+#define MX25_PAD_BOOT_MODE1__BOOT_MODE1		0x228 0x000 0x000 0x00 0x000
+#define MX25_PAD_BOOT_MODE1__GPIO_4_31		0x228 0x000 0x000 0x05 0x000
+
+/*
+ * Compatibility defines for out-of-tree users. You should update if you make
+ * use of one of them.
+ */
+#define MX25_PAD_D15__SDHC1_DAT7		MX25_PAD_D15__ESDHC1_DAT7
+#define MX25_PAD_D14__SDHC1_DAT6		MX25_PAD_D14__ESDHC1_DAT6
+#define MX25_PAD_D13__SDHC1_DAT5		MX25_PAD_D13__ESDHC1_DAT5
+#define MX25_PAD_D12__SDHC1_DAT4		MX25_PAD_D12__ESDHC1_DAT4
+#define MX25_PAD_LD8__SDHC2_CMD			MX25_PAD_LD8__ESDHC2_CMD
+#define MX25_PAD_LD9__SDHC2_CLK			MX25_PAD_LD9__ESDHC2_CLK
+#define MX25_PAD_LD11__SDHC2_DAT1		MX25_PAD_LD11__ESDHC2_DAT1
+#define MX25_PAD_CSI_D6__SDHC2_CMD		MX25_PAD_CSI_D6__ESDHC2_CMD
+#define MX25_PAD_CSI_D7__SDHC2_DAT_CLK		MX25_PAD_CSI_D7__ESDHC2_CLK
+#define MX25_PAD_CSI_MCLK__SDHC2_DAT0		MX25_PAD_CSI_MCLK__ESDHC2_DAT0
+#define MX25_PAD_CSI_VSYNC__SDHC2_DAT1		MX25_PAD_CSI_VSYNC__ESDHC2_DAT1
+#define MX25_PAD_CSI_HSYNC__SDHC2_DAT2		MX25_PAD_CSI_HSYNC__ESDHC2_DAT2
+#define MX25_PAD_CSI_PIXCLK__SDHC2_DAT3		MX25_PAD_CSI_PIXCLK__ESDHC2_DAT3
+#define MX25_PAD_SD1_CMD__SD1_CMD		MX25_PAD_SD1_CMD__ESDHC1_CMD
+#define MX25_PAD_SD1_CLK__SD1_CLK		MX25_PAD_SD1_CLK__ESDHC1_CLK
+#define MX25_PAD_SD1_DATA0__SD1_DATA0		MX25_PAD_SD1_DATA0__ESDHC1_DAT0
+#define MX25_PAD_SD1_DATA1__SD1_DATA1		MX25_PAD_SD1_DATA1__ESDHC1_DAT1
+#define MX25_PAD_SD1_DATA2__SD1_DATA2		MX25_PAD_SD1_DATA2__ESDHC1_DAT2
+#define MX25_PAD_SD1_DATA3__SD1_DATA3		MX25_PAD_SD1_DATA3__ESDHC1_DAT3
+
+#endif /* __DTS_IMX25_PINFUNC_H */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/imx27-pinfunc.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/imx27-pinfunc.h
new file mode 100644
index 0000000000000000000000000000000000000000..597bb5f74dcc5ecccaa664274f672d8608297dac
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/imx27-pinfunc.h
@@ -0,0 +1,480 @@
+/*
+ * Copyright 2013 Markus Pargmann <mpa@pengutronix.de>, Pengutronix
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#ifndef __DTS_IMX27_PINFUNC_H
+#define __DTS_IMX27_PINFUNC_H
+
+/*
+ * The pin function ID is a tuple of
+ * <pin mux_id>
+ * mux_id consists of
+ * function + (direction << 2) + (gpio_oconf << 4) + (gpio_iconfa << 8) + (gpio_iconfb << 10)
+ *
+ * function:      0 - Primary function
+ *                1 - Alternate function
+ *                2 - GPIO
+ * direction:     0 - Input
+ *                1 - Output
+ * gpio_oconf:    0 - A_IN
+ *                1 - B_IN
+ *                2 - C_IN
+ *                3 - Data Register
+ * gpio_iconfa/b: 0 - GPIO_IN
+ *                1 - Interrupt Status Register
+ *                2 - 0
+ *                3 - 1
+ *
+ * 'pin' is an integer between 0 and 0xbf. imx27 has 6 ports with 32 configurable
+ * configurable pins each. 'pin' is PORT * 32 + PORT_PIN, PORT_PIN is the pin
+ * number on the specific port (between 0 and 31).
+ */
+
+#define MX27_PAD_USBH2_CLK__USBH2_CLK                      0x00 0x000
+#define MX27_PAD_USBH2_CLK__GPIO1_0                        0x00 0x032
+#define MX27_PAD_USBH2_DIR__USBH2_DIR                      0x01 0x000
+#define MX27_PAD_USBH2_DIR__GPIO1_1                        0x01 0x032
+#define MX27_PAD_USBH2_DATA7__USBH2_DATA7                  0x02 0x004
+#define MX27_PAD_USBH2_DATA7__GPIO1_2                      0x02 0x032
+#define MX27_PAD_USBH2_NXT__USBH2_NXT                      0x03 0x000
+#define MX27_PAD_USBH2_NXT__GPIO1_3                        0x03 0x032
+#define MX27_PAD_USBH2_STP__USBH2_STP                      0x04 0x004
+#define MX27_PAD_USBH2_STP__GPIO1_4                        0x04 0x032
+#define MX27_PAD_LSCLK__LSCLK                              0x05 0x004
+#define MX27_PAD_LSCLK__GPIO1_5                            0x05 0x032
+#define MX27_PAD_LD0__LD0                                  0x06 0x004
+#define MX27_PAD_LD0__GPIO1_6                              0x06 0x032
+#define MX27_PAD_LD1__LD1                                  0x07 0x004
+#define MX27_PAD_LD1__GPIO1_7                              0x07 0x032
+#define MX27_PAD_LD2__LD2                                  0x08 0x004
+#define MX27_PAD_LD2__GPIO1_8                              0x08 0x032
+#define MX27_PAD_LD3__LD3                                  0x09 0x004
+#define MX27_PAD_LD3__GPIO1_9                              0x09 0x032
+#define MX27_PAD_LD4__LD4                                  0x0a 0x004
+#define MX27_PAD_LD4__GPIO1_10                             0x0a 0x032
+#define MX27_PAD_LD5__LD5                                  0x0b 0x004
+#define MX27_PAD_LD5__GPIO1_11                             0x0b 0x032
+#define MX27_PAD_LD6__LD6                                  0x0c 0x004
+#define MX27_PAD_LD6__GPIO1_12                             0x0c 0x032
+#define MX27_PAD_LD7__LD7                                  0x0d 0x004
+#define MX27_PAD_LD7__GPIO1_13                             0x0d 0x032
+#define MX27_PAD_LD8__LD8                                  0x0e 0x004
+#define MX27_PAD_LD8__GPIO1_14                             0x0e 0x032
+#define MX27_PAD_LD9__LD9                                  0x0f 0x004
+#define MX27_PAD_LD9__GPIO1_15                             0x0f 0x032
+#define MX27_PAD_LD10__LD10                                0x10 0x004
+#define MX27_PAD_LD10__GPIO1_16                            0x10 0x032
+#define MX27_PAD_LD11__LD11                                0x11 0x004
+#define MX27_PAD_LD11__GPIO1_17                            0x11 0x032
+#define MX27_PAD_LD12__LD12                                0x12 0x004
+#define MX27_PAD_LD12__GPIO1_18                            0x12 0x032
+#define MX27_PAD_LD13__LD13                                0x13 0x004
+#define MX27_PAD_LD13__GPIO1_19                            0x13 0x032
+#define MX27_PAD_LD14__LD14                                0x14 0x004
+#define MX27_PAD_LD14__GPIO1_20                            0x14 0x032
+#define MX27_PAD_LD15__LD15                                0x15 0x004
+#define MX27_PAD_LD15__GPIO1_21                            0x15 0x032
+#define MX27_PAD_LD16__LD16                                0x16 0x004
+#define MX27_PAD_LD16__GPIO1_22                            0x16 0x032
+#define MX27_PAD_LD17__LD17                                0x17 0x004
+#define MX27_PAD_LD17__GPIO1_23                            0x17 0x032
+#define MX27_PAD_REV__REV                                  0x18 0x004
+#define MX27_PAD_REV__GPIO1_24                             0x18 0x032
+#define MX27_PAD_CLS__CLS                                  0x19 0x004
+#define MX27_PAD_CLS__GPIO1_25                             0x19 0x032
+#define MX27_PAD_PS__PS                                    0x1a 0x004
+#define MX27_PAD_PS__GPIO1_26                              0x1a 0x032
+#define MX27_PAD_SPL_SPR__SPL_SPR                          0x1b 0x004
+#define MX27_PAD_SPL_SPR__GPIO1_27                         0x1b 0x032
+#define MX27_PAD_HSYNC__HSYNC                              0x1c 0x004
+#define MX27_PAD_HSYNC__GPIO1_28                           0x1c 0x032
+#define MX27_PAD_VSYNC__VSYNC                              0x1d 0x004
+#define MX27_PAD_VSYNC__GPIO1_29                           0x1d 0x032
+#define MX27_PAD_CONTRAST__CONTRAST                        0x1e 0x004
+#define MX27_PAD_CONTRAST__GPIO1_30                        0x1e 0x032
+#define MX27_PAD_OE_ACD__OE_ACD                            0x1f 0x004
+#define MX27_PAD_OE_ACD__GPIO1_31                          0x1f 0x032
+#define MX27_PAD_SD2_D0__SD2_D0                            0x24 0x004
+#define MX27_PAD_SD2_D0__MSHC_DATA0                        0x24 0x005
+#define MX27_PAD_SD2_D0__GPIO2_4                           0x24 0x032
+#define MX27_PAD_SD2_D1__SD2_D1                            0x25 0x004
+#define MX27_PAD_SD2_D1__MSHC_DATA1                        0x25 0x005
+#define MX27_PAD_SD2_D1__GPIO2_5                           0x25 0x032
+#define MX27_PAD_SD2_D2__SD2_D2                            0x26 0x004
+#define MX27_PAD_SD2_D2__MSHC_DATA2                        0x26 0x005
+#define MX27_PAD_SD2_D2__GPIO2_6                           0x26 0x032
+#define MX27_PAD_SD2_D3__SD2_D3                            0x27 0x004
+#define MX27_PAD_SD2_D3__MSHC_DATA3                        0x27 0x005
+#define MX27_PAD_SD2_D3__GPIO2_7                           0x27 0x032
+#define MX27_PAD_SD2_CMD__SD2_CMD                          0x28 0x004
+#define MX27_PAD_SD2_CMD__MSHC_BS                          0x28 0x005
+#define MX27_PAD_SD2_CMD__GPIO2_8                          0x28 0x032
+#define MX27_PAD_SD2_CLK__SD2_CLK                          0x29 0x004
+#define MX27_PAD_SD2_CLK__MSHC_SCLK                        0x29 0x005
+#define MX27_PAD_SD2_CLK__GPIO2_9                          0x29 0x032
+#define MX27_PAD_CSI_D0__CSI_D0                            0x2a 0x000
+#define MX27_PAD_CSI_D0__UART6_TXD                         0x2a 0x005
+#define MX27_PAD_CSI_D0__GPIO2_10                          0x2a 0x032
+#define MX27_PAD_CSI_D1__CSI_D1                            0x2b 0x000
+#define MX27_PAD_CSI_D1__UART6_RXD                         0x2b 0x001
+#define MX27_PAD_CSI_D1__GPIO2_11                          0x2b 0x032
+#define MX27_PAD_CSI_D2__CSI_D2                            0x2c 0x000
+#define MX27_PAD_CSI_D2__UART6_CTS                         0x2c 0x005
+#define MX27_PAD_CSI_D2__GPIO2_12                          0x2c 0x032
+#define MX27_PAD_CSI_D3__CSI_D3                            0x2d 0x000
+#define MX27_PAD_CSI_D3__UART6_RTS                         0x2d 0x001
+#define MX27_PAD_CSI_D3__GPIO2_13                          0x2d 0x032
+#define MX27_PAD_CSI_D4__CSI_D4                            0x2e 0x000
+#define MX27_PAD_CSI_D4__GPIO2_14                          0x2e 0x032
+#define MX27_PAD_CSI_MCLK__CSI_MCLK                        0x2f 0x004
+#define MX27_PAD_CSI_MCLK__GPIO2_15                        0x2f 0x032
+#define MX27_PAD_CSI_PIXCLK__CSI_PIXCLK                    0x30 0x000
+#define MX27_PAD_CSI_PIXCLK__GPIO2_16                      0x30 0x032
+#define MX27_PAD_CSI_D5__CSI_D5                            0x31 0x000
+#define MX27_PAD_CSI_D5__GPIO2_17                          0x31 0x032
+#define MX27_PAD_CSI_D6__CSI_D6                            0x32 0x000
+#define MX27_PAD_CSI_D6__UART5_TXD                         0x32 0x005
+#define MX27_PAD_CSI_D6__GPIO2_18                          0x32 0x032
+#define MX27_PAD_CSI_D7__CSI_D7                            0x33 0x000
+#define MX27_PAD_CSI_D7__UART5_RXD                         0x33 0x001
+#define MX27_PAD_CSI_D7__GPIO2_19                          0x33 0x032
+#define MX27_PAD_CSI_VSYNC__CSI_VSYNC                      0x34 0x000
+#define MX27_PAD_CSI_VSYNC__UART5_CTS                      0x34 0x005
+#define MX27_PAD_CSI_VSYNC__GPIO2_20                       0x34 0x032
+#define MX27_PAD_CSI_HSYNC__CSI_HSYNC                      0x35 0x000
+#define MX27_PAD_CSI_HSYNC__UART5_RTS                      0x35 0x001
+#define MX27_PAD_CSI_HSYNC__GPIO2_21                       0x35 0x032
+#define MX27_PAD_USBH1_SUSP__USBH1_SUSP                    0x36 0x004
+#define MX27_PAD_USBH1_SUSP__GPIO2_22                      0x36 0x032
+#define MX27_PAD_USB_PWR__USB_PWR                          0x37 0x004
+#define MX27_PAD_USB_PWR__GPIO2_23                         0x37 0x032
+#define MX27_PAD_USB_OC_B__USB_OC_B                        0x38 0x000
+#define MX27_PAD_USB_OC_B__GPIO2_24                        0x38 0x032
+#define MX27_PAD_USBH1_RCV__USBH1_RCV                      0x39 0x004
+#define MX27_PAD_USBH1_RCV__GPIO2_25                       0x39 0x032
+#define MX27_PAD_USBH1_FS__USBH1_FS                        0x3a 0x004
+#define MX27_PAD_USBH1_FS__UART4_RTS                       0x3a 0x001
+#define MX27_PAD_USBH1_FS__GPIO2_26                        0x3a 0x032
+#define MX27_PAD_USBH1_OE_B__USBH1_OE_B                    0x3b 0x004
+#define MX27_PAD_USBH1_OE_B__GPIO2_27                      0x3b 0x032
+#define MX27_PAD_USBH1_TXDM__USBH1_TXDM                    0x3c 0x004
+#define MX27_PAD_USBH1_TXDM__UART4_TXD                     0x3c 0x005
+#define MX27_PAD_USBH1_TXDM__GPIO2_28                      0x3c 0x032
+#define MX27_PAD_USBH1_TXDP__USBH1_TXDP                    0x3d 0x004
+#define MX27_PAD_USBH1_TXDP__UART4_CTS                     0x3d 0x005
+#define MX27_PAD_USBH1_TXDP__GPIO2_29                      0x3d 0x032
+#define MX27_PAD_USBH1_RXDM__USBH1_RXDM                    0x3e 0x004
+#define MX27_PAD_USBH1_RXDM__GPIO2_30                      0x3e 0x032
+#define MX27_PAD_USBH1_RXDP__USBH1_RXDP                    0x3f 0x004
+#define MX27_PAD_USBH1_RXDP__UART4_RXD                     0x3f 0x001
+#define MX27_PAD_USBH1_RXDP__GPIO2_31                      0x3f 0x032
+#define MX27_PAD_I2C2_SDA__I2C2_SDA                        0x45 0x004
+#define MX27_PAD_I2C2_SDA__GPIO3_5                         0x45 0x032
+#define MX27_PAD_I2C2_SCL__I2C2_SCL                        0x46 0x004
+#define MX27_PAD_I2C2_SCL__GPIO3_6                         0x46 0x032
+#define MX27_PAD_USBOTG_DATA5__USBOTG_DATA5                0x47 0x004
+#define MX27_PAD_USBOTG_DATA5__GPIO3_7                     0x47 0x032
+#define MX27_PAD_USBOTG_DATA6__USBOTG_DATA6                0x48 0x004
+#define MX27_PAD_USBOTG_DATA6__GPIO3_8                     0x48 0x032
+#define MX27_PAD_USBOTG_DATA0__USBOTG_DATA0                0x49 0x004
+#define MX27_PAD_USBOTG_DATA0__GPIO3_9                     0x49 0x032
+#define MX27_PAD_USBOTG_DATA2__USBOTG_DATA2                0x4a 0x004
+#define MX27_PAD_USBOTG_DATA2__GPIO3_10                    0x4a 0x032
+#define MX27_PAD_USBOTG_DATA1__USBOTG_DATA1                0x4b 0x004
+#define MX27_PAD_USBOTG_DATA1__GPIO3_11                    0x4b 0x032
+#define MX27_PAD_USBOTG_DATA4__USBOTG_DATA4                0x4c 0x004
+#define MX27_PAD_USBOTG_DATA4__GPIO3_12                    0x4c 0x032
+#define MX27_PAD_USBOTG_DATA3__USBOTG_DATA3                0x4d 0x004
+#define MX27_PAD_USBOTG_DATA3__GPIO3_13                    0x4d 0x032
+#define MX27_PAD_TOUT__TOUT                                0x4e 0x004
+#define MX27_PAD_TOUT__GPIO3_14                            0x4e 0x032
+#define MX27_PAD_TIN__TIN                                  0x4f 0x000
+#define MX27_PAD_TIN__GPIO3_15                             0x4f 0x032
+#define MX27_PAD_SSI4_FS__SSI4_FS                          0x50 0x004
+#define MX27_PAD_SSI4_FS__GPIO3_16                         0x50 0x032
+#define MX27_PAD_SSI4_RXDAT__SSI4_RXDAT                    0x51 0x004
+#define MX27_PAD_SSI4_RXDAT__GPIO3_17                      0x51 0x032
+#define MX27_PAD_SSI4_TXDAT__SSI4_TXDAT                    0x52 0x004
+#define MX27_PAD_SSI4_TXDAT__GPIO3_18                      0x52 0x032
+#define MX27_PAD_SSI4_CLK__SSI4_CLK                        0x53 0x004
+#define MX27_PAD_SSI4_CLK__GPIO3_19                        0x53 0x032
+#define MX27_PAD_SSI1_FS__SSI1_FS                          0x54 0x004
+#define MX27_PAD_SSI1_FS__GPIO3_20                         0x54 0x032
+#define MX27_PAD_SSI1_RXDAT__SSI1_RXDAT                    0x55 0x004
+#define MX27_PAD_SSI1_RXDAT__GPIO3_21                      0x55 0x032
+#define MX27_PAD_SSI1_TXDAT__SSI1_TXDAT                    0x56 0x004
+#define MX27_PAD_SSI1_TXDAT__GPIO3_22                      0x56 0x032
+#define MX27_PAD_SSI1_CLK__SSI1_CLK                        0x57 0x004
+#define MX27_PAD_SSI1_CLK__GPIO3_23                        0x57 0x032
+#define MX27_PAD_SSI2_FS__SSI2_FS                          0x58 0x004
+#define MX27_PAD_SSI2_FS__GPT5_TOUT                        0x58 0x005
+#define MX27_PAD_SSI2_FS__GPIO3_24                         0x58 0x032
+#define MX27_PAD_SSI2_RXDAT__SSI2_RXDAT                    0x59 0x004
+#define MX27_PAD_SSI2_RXDAT__GPTS_TIN                      0x59 0x001
+#define MX27_PAD_SSI2_RXDAT__GPIO3_25                      0x59 0x032
+#define MX27_PAD_SSI2_TXDAT__SSI2_TXDAT                    0x5a 0x004
+#define MX27_PAD_SSI2_TXDAT__GPT4_TOUT                     0x5a 0x005
+#define MX27_PAD_SSI2_TXDAT__GPIO3_26                      0x5a 0x032
+#define MX27_PAD_SSI2_CLK__SSI2_CLK                        0x5b 0x004
+#define MX27_PAD_SSI2_CLK__GPT4_TIN                        0x5b 0x001
+#define MX27_PAD_SSI2_CLK__GPIO3_27                        0x5b 0x032
+#define MX27_PAD_SSI3_FS__SSI3_FS                          0x5c 0x004
+#define MX27_PAD_SSI3_FS__SLCDC2_D0                        0x5c 0x001
+#define MX27_PAD_SSI3_FS__GPIO3_28                         0x5c 0x032
+#define MX27_PAD_SSI3_RXDAT__SSI3_RXDAT                    0x5d 0x004
+#define MX27_PAD_SSI3_RXDAT__SLCDC2_RS                     0x5d 0x001
+#define MX27_PAD_SSI3_RXDAT__GPIO3_29                      0x5d 0x032
+#define MX27_PAD_SSI3_TXDAT__SSI3_TXDAT                    0x5e 0x004
+#define MX27_PAD_SSI3_TXDAT__SLCDC2_CS                     0x5e 0x001
+#define MX27_PAD_SSI3_TXDAT__GPIO3_30                      0x5e 0x032
+#define MX27_PAD_SSI3_CLK__SSI3_CLK                        0x5f 0x004
+#define MX27_PAD_SSI3_CLK__SLCDC2_CLK                      0x5f 0x001
+#define MX27_PAD_SSI3_CLK__GPIO3_31                        0x5f 0x032
+#define MX27_PAD_SD3_CMD__SD3_CMD                          0x60 0x004
+#define MX27_PAD_SD3_CMD__FEC_TXD0                         0x60 0x006
+#define MX27_PAD_SD3_CMD__GPIO4_0                          0x60 0x032
+#define MX27_PAD_SD3_CLK__SD3_CLK                          0x61 0x004
+#define MX27_PAD_SD3_CLK__ETMTRACEPKT15                    0x61 0x005
+#define MX27_PAD_SD3_CLK__FEC_TXD1                         0x61 0x006
+#define MX27_PAD_SD3_CLK__GPIO4_1                          0x61 0x032
+#define MX27_PAD_ATA_DATA0__ATA_DATA0                      0x62 0x004
+#define MX27_PAD_ATA_DATA0__SD3_D0                         0x62 0x005
+#define MX27_PAD_ATA_DATA0__FEC_TXD2                       0x62 0x006
+#define MX27_PAD_ATA_DATA0__GPIO4_2                        0x62 0x032
+#define MX27_PAD_ATA_DATA1__ATA_DATA1                      0x63 0x004
+#define MX27_PAD_ATA_DATA1__SD3_D1                         0x63 0x005
+#define MX27_PAD_ATA_DATA1__FEC_TXD3                       0x63 0x006
+#define MX27_PAD_ATA_DATA1__GPIO4_3                        0x63 0x032
+#define MX27_PAD_ATA_DATA2__ATA_DATA2                      0x64 0x004
+#define MX27_PAD_ATA_DATA2__SD3_D2                         0x64 0x005
+#define MX27_PAD_ATA_DATA2__FEC_RX_ER                      0x64 0x002
+#define MX27_PAD_ATA_DATA2__GPIO4_4                        0x64 0x032
+#define MX27_PAD_ATA_DATA3__ATA_DATA3                      0x65 0x004
+#define MX27_PAD_ATA_DATA3__SD3_D3                         0x65 0x005
+#define MX27_PAD_ATA_DATA3__FEC_RXD1                       0x65 0x002
+#define MX27_PAD_ATA_DATA3__GPIO4_5                        0x65 0x032
+#define MX27_PAD_ATA_DATA4__ATA_DATA4                      0x66 0x004
+#define MX27_PAD_ATA_DATA4__ETMTRACEPKT14                  0x66 0x005
+#define MX27_PAD_ATA_DATA4__FEC_RXD2                       0x66 0x002
+#define MX27_PAD_ATA_DATA4__GPIO4_6                        0x66 0x032
+#define MX27_PAD_ATA_DATA5__ATA_DATA5                      0x67 0x004
+#define MX27_PAD_ATA_DATA5__ETMTRACEPKT13                  0x67 0x005
+#define MX27_PAD_ATA_DATA5__FEC_RXD3                       0x67 0x002
+#define MX27_PAD_ATA_DATA5__GPIO4_7                        0x67 0x032
+#define MX27_PAD_ATA_DATA6__ATA_DATA6                      0x68 0x004
+#define MX27_PAD_ATA_DATA6__FEC_MDIO                       0x68 0x005
+#define MX27_PAD_ATA_DATA6__GPIO4_8                        0x68 0x032
+#define MX27_PAD_ATA_DATA7__ATA_DATA7                      0x69 0x004
+#define MX27_PAD_ATA_DATA7__ETMTRACEPKT12                  0x69 0x005
+#define MX27_PAD_ATA_DATA7__FEC_MDC                        0x69 0x006
+#define MX27_PAD_ATA_DATA7__GPIO4_9                        0x69 0x032
+#define MX27_PAD_ATA_DATA8__ATA_DATA8                      0x6a 0x004
+#define MX27_PAD_ATA_DATA8__ETMTRACEPKT11                  0x6a 0x005
+#define MX27_PAD_ATA_DATA8__FEC_CRS                        0x6a 0x002
+#define MX27_PAD_ATA_DATA8__GPIO4_10                       0x6a 0x032
+#define MX27_PAD_ATA_DATA9__ATA_DATA9                      0x6b 0x004
+#define MX27_PAD_ATA_DATA9__ETMTRACEPKT10                  0x6b 0x005
+#define MX27_PAD_ATA_DATA9__FEC_TX_CLK                     0x6b 0x002
+#define MX27_PAD_ATA_DATA9__GPIO4_11                       0x6b 0x032
+#define MX27_PAD_ATA_DATA10__ATA_DATA10                    0x6c 0x004
+#define MX27_PAD_ATA_DATA10__ETMTRACEPKT9                  0x6c 0x005
+#define MX27_PAD_ATA_DATA10__FEC_RXD0                      0x6c 0x002
+#define MX27_PAD_ATA_DATA10__GPIO4_12                      0x6c 0x032
+#define MX27_PAD_ATA_DATA11__ATA_DATA11                    0x6d 0x004
+#define MX27_PAD_ATA_DATA11__ETMTRACEPKT8                  0x6d 0x005
+#define MX27_PAD_ATA_DATA11__FEC_RX_DV                     0x6d 0x002
+#define MX27_PAD_ATA_DATA11__GPIO4_13                      0x6d 0x032
+#define MX27_PAD_ATA_DATA12__ATA_DATA12                    0x6e 0x004
+#define MX27_PAD_ATA_DATA12__ETMTRACEPKT7                  0x6e 0x005
+#define MX27_PAD_ATA_DATA12__FEC_RX_CLK                    0x6e 0x002
+#define MX27_PAD_ATA_DATA12__GPIO4_14                      0x6e 0x032
+#define MX27_PAD_ATA_DATA13__ATA_DATA13                    0x6f 0x004
+#define MX27_PAD_ATA_DATA13__ETMTRACEPKT6                  0x6f 0x005
+#define MX27_PAD_ATA_DATA13__FEC_COL                       0x6f 0x002
+#define MX27_PAD_ATA_DATA13__GPIO4_15                      0x6f 0x032
+#define MX27_PAD_ATA_DATA14__ATA_DATA14                    0x70 0x004
+#define MX27_PAD_ATA_DATA14__ETMTRACEPKT5                  0x70 0x005
+#define MX27_PAD_ATA_DATA14__FEC_TX_ER                     0x70 0x006
+#define MX27_PAD_ATA_DATA14__GPIO4_16                      0x70 0x032
+#define MX27_PAD_I2C_DATA__I2C_DATA                        0x71 0x004
+#define MX27_PAD_I2C_DATA__GPIO4_17                        0x71 0x032
+#define MX27_PAD_I2C_CLK__I2C_CLK                          0x72 0x004
+#define MX27_PAD_I2C_CLK__GPIO4_18                         0x72 0x032
+#define MX27_PAD_CSPI2_SS2__CSPI2_SS2                      0x73 0x004
+#define MX27_PAD_CSPI2_SS2__USBH2_DATA4                    0x73 0x005
+#define MX27_PAD_CSPI2_SS2__GPIO4_19                       0x73 0x032
+#define MX27_PAD_CSPI2_SS1__CSPI2_SS1                      0x74 0x004
+#define MX27_PAD_CSPI2_SS1__USBH2_DATA3                    0x74 0x005
+#define MX27_PAD_CSPI2_SS1__GPIO4_20                       0x74 0x032
+#define MX27_PAD_CSPI2_SS0__CSPI2_SS0                      0x75 0x004
+#define MX27_PAD_CSPI2_SS0__USBH2_DATA6                    0x75 0x005
+#define MX27_PAD_CSPI2_SS0__GPIO4_21                       0x75 0x032
+#define MX27_PAD_CSPI2_SCLK__CSPI2_SCLK                    0x76 0x004
+#define MX27_PAD_CSPI2_SCLK__USBH2_DATA0                   0x76 0x005
+#define MX27_PAD_CSPI2_SCLK__GPIO4_22                      0x76 0x032
+#define MX27_PAD_CSPI2_MISO__CSPI2_MISO                    0x77 0x004
+#define MX27_PAD_CSPI2_MISO__USBH2_DATA2                   0x77 0x005
+#define MX27_PAD_CSPI2_MISO__GPIO4_23                      0x77 0x032
+#define MX27_PAD_CSPI2_MOSI__CSPI2_MOSI                    0x78 0x004
+#define MX27_PAD_CSPI2_MOSI__USBH2_DATA1                   0x78 0x005
+#define MX27_PAD_CSPI2_MOSI__GPIO4_24                      0x78 0x032
+#define MX27_PAD_CSPI1_RDY__CSPI1_RDY                      0x79 0x000
+#define MX27_PAD_CSPI1_RDY__GPIO4_25                       0x79 0x032
+#define MX27_PAD_CSPI1_SS2__CSPI1_SS2                      0x7a 0x004
+#define MX27_PAD_CSPI1_SS2__USBH2_DATA5                    0x7a 0x005
+#define MX27_PAD_CSPI1_SS2__GPIO4_26                       0x7a 0x032
+#define MX27_PAD_CSPI1_SS1__CSPI1_SS1                      0x7b 0x004
+#define MX27_PAD_CSPI1_SS1__GPIO4_27                       0x7b 0x032
+#define MX27_PAD_CSPI1_SS0__CSPI1_SS0                      0x7c 0x004
+#define MX27_PAD_CSPI1_SS0__GPIO4_28                       0x7c 0x032
+#define MX27_PAD_CSPI1_SCLK__CSPI1_SCLK                    0x7d 0x004
+#define MX27_PAD_CSPI1_SCLK__GPIO4_29                      0x7d 0x032
+#define MX27_PAD_CSPI1_MISO__CSPI1_MISO                    0x7e 0x004
+#define MX27_PAD_CSPI1_MISO__GPIO4_30                      0x7e 0x032
+#define MX27_PAD_CSPI1_MOSI__CSPI1_MOSI                    0x7f 0x004
+#define MX27_PAD_CSPI1_MOSI__GPIO4_31                      0x7f 0x032
+#define MX27_PAD_USBOTG_NXT__USBOTG_NXT                    0x80 0x000
+#define MX27_PAD_USBOTG_NXT__KP_COL6A                      0x80 0x005
+#define MX27_PAD_USBOTG_NXT__GPIO5_0                       0x80 0x032
+#define MX27_PAD_USBOTG_STP__USBOTG_STP                    0x81 0x004
+#define MX27_PAD_USBOTG_STP__KP_ROW6A                      0x81 0x005
+#define MX27_PAD_USBOTG_STP__GPIO5_1                       0x81 0x032
+#define MX27_PAD_USBOTG_DIR__USBOTG_DIR                    0x82 0x000
+#define MX27_PAD_USBOTG_DIR__KP_ROW7A                      0x82 0x005
+#define MX27_PAD_USBOTG_DIR__GPIO5_2                       0x82 0x032
+#define MX27_PAD_UART2_CTS__UART2_CTS                      0x83 0x004
+#define MX27_PAD_UART2_CTS__KP_COL7                        0x83 0x005
+#define MX27_PAD_UART2_CTS__GPIO5_3                        0x83 0x032
+#define MX27_PAD_UART2_RTS__UART2_RTS                      0x84 0x000
+#define MX27_PAD_UART2_RTS__KP_ROW7                        0x84 0x005
+#define MX27_PAD_UART2_RTS__GPIO5_4                        0x84 0x032
+#define MX27_PAD_PWMO__PWMO                                0x85 0x004
+#define MX27_PAD_PWMO__GPIO5_5                             0x85 0x032
+#define MX27_PAD_UART2_TXD__UART2_TXD                      0x86 0x004
+#define MX27_PAD_UART2_TXD__KP_COL6                        0x86 0x005
+#define MX27_PAD_UART2_TXD__GPIO5_6                        0x86 0x032
+#define MX27_PAD_UART2_RXD__UART2_RXD                      0x87 0x000
+#define MX27_PAD_UART2_RXD__KP_ROW6                        0x87 0x005
+#define MX27_PAD_UART2_RXD__GPIO5_7                        0x87 0x032
+#define MX27_PAD_UART3_TXD__UART3_TXD                      0x88 0x004
+#define MX27_PAD_UART3_TXD__GPIO5_8                        0x88 0x032
+#define MX27_PAD_UART3_RXD__UART3_RXD                      0x89 0x000
+#define MX27_PAD_UART3_RXD__GPIO5_9                        0x89 0x032
+#define MX27_PAD_UART3_CTS__UART3_CTS                      0x8a 0x004
+#define MX27_PAD_UART3_CTS__GPIO5_10                       0x8a 0x032
+#define MX27_PAD_UART3_RTS__UART3_RTS                      0x8b 0x000
+#define MX27_PAD_UART3_RTS__GPIO5_11                       0x8b 0x032
+#define MX27_PAD_UART1_TXD__UART1_TXD                      0x8c 0x004
+#define MX27_PAD_UART1_TXD__GPIO5_12                       0x8c 0x032
+#define MX27_PAD_UART1_RXD__UART1_RXD                      0x8d 0x000
+#define MX27_PAD_UART1_RXD__GPIO5_13                       0x8d 0x032
+#define MX27_PAD_UART1_CTS__UART1_CTS                      0x8e 0x004
+#define MX27_PAD_UART1_CTS__GPIO5_14                       0x8e 0x032
+#define MX27_PAD_UART1_RTS__UART1_RTS                      0x8f 0x000
+#define MX27_PAD_UART1_RTS__GPIO5_15                       0x8f 0x032
+#define MX27_PAD_RTCK__RTCK                                0x90 0x004
+#define MX27_PAD_RTCK__OWIRE                               0x90 0x005
+#define MX27_PAD_RTCK__GPIO5_16                            0x90 0x032
+#define MX27_PAD_RESET_OUT_B__RESET_OUT_B                  0x91 0x004
+#define MX27_PAD_RESET_OUT_B__GPIO5_17                     0x91 0x032
+#define MX27_PAD_SD1_D0__SD1_D0                            0x92 0x004
+#define MX27_PAD_SD1_D0__CSPI3_MISO                        0x92 0x001
+#define MX27_PAD_SD1_D0__GPIO5_18                          0x92 0x032
+#define MX27_PAD_SD1_D1__SD1_D1                            0x93 0x004
+#define MX27_PAD_SD1_D1__GPIO5_19                          0x93 0x032
+#define MX27_PAD_SD1_D2__SD1_D2                            0x94 0x004
+#define MX27_PAD_SD1_D2__GPIO5_20                          0x94 0x032
+#define MX27_PAD_SD1_D3__SD1_D3                            0x95 0x004
+#define MX27_PAD_SD1_D3__CSPI3_SS                          0x95 0x005
+#define MX27_PAD_SD1_D3__GPIO5_21                          0x95 0x032
+#define MX27_PAD_SD1_CMD__SD1_CMD                          0x96 0x004
+#define MX27_PAD_SD1_CMD__CSPI3_MOSI                       0x96 0x005
+#define MX27_PAD_SD1_CMD__GPIO5_22                         0x96 0x032
+#define MX27_PAD_SD1_CLK__SD1_CLK                          0x97 0x004
+#define MX27_PAD_SD1_CLK__CSPI3_SCLK                       0x97 0x005
+#define MX27_PAD_SD1_CLK__GPIO5_23                         0x97 0x032
+#define MX27_PAD_USBOTG_CLK__USBOTG_CLK                    0x98 0x000
+#define MX27_PAD_USBOTG_CLK__GPIO5_24                      0x98 0x032
+#define MX27_PAD_USBOTG_DATA7__USBOTG_DATA7                0x99 0x004
+#define MX27_PAD_USBOTG_DATA7__GPIO5_25                    0x99 0x032
+#define MX27_PAD_NFRB__NFRB                                0xa0 0x000
+#define MX27_PAD_NFRB__ETMTRACEPKT3                        0xa0 0x005
+#define MX27_PAD_NFRB__GPIO6_0                             0xa0 0x032
+#define MX27_PAD_NFCLE__NFCLE                              0xa1 0x004
+#define MX27_PAD_NFCLE__ETMTRACEPKT0                       0xa1 0x005
+#define MX27_PAD_NFCLE__GPIO6_1                            0xa1 0x032
+#define MX27_PAD_NFWP_B__NFWP_B                            0xa2 0x004
+#define MX27_PAD_NFWP_B__ETMTRACEPKT1                      0xa2 0x005
+#define MX27_PAD_NFWP_B__GPIO6_2                           0xa2 0x032
+#define MX27_PAD_NFCE_B__NFCE_B                            0xa3 0x004
+#define MX27_PAD_NFCE_B__ETMTRACEPKT2                      0xa3 0x005
+#define MX27_PAD_NFCE_B__GPIO6_3                           0xa3 0x032
+#define MX27_PAD_NFALE__NFALE                              0xa4 0x004
+#define MX27_PAD_NFALE__ETMPIPESTAT0                       0xa4 0x005
+#define MX27_PAD_NFALE__GPIO6_4                            0xa4 0x032
+#define MX27_PAD_NFRE_B__NFRE_B                            0xa5 0x004
+#define MX27_PAD_NFRE_B__ETMPIPESTAT1                      0xa5 0x005
+#define MX27_PAD_NFRE_B__GPIO6_5                           0xa5 0x032
+#define MX27_PAD_NFWE_B__NFWE_B                            0xa6 0x004
+#define MX27_PAD_NFWE_B__ETMPIPESTAT2                      0xa6 0x005
+#define MX27_PAD_NFWE_B__GPIO6_6                           0xa6 0x032
+#define MX27_PAD_PC_POE__PC_POE                            0xa7 0x004
+#define MX27_PAD_PC_POE__ATA_BUFFER_EN                     0xa7 0x005
+#define MX27_PAD_PC_POE__GPIO6_7                           0xa7 0x032
+#define MX27_PAD_PC_RW_B__PC_RW_B                          0xa8 0x004
+#define MX27_PAD_PC_RW_B__ATA_IORDY                        0xa8 0x001
+#define MX27_PAD_PC_RW_B__GPIO6_8                          0xa8 0x032
+#define MX27_PAD_IOIS16__IOIS16                            0xa9 0x000
+#define MX27_PAD_IOIS16__ATA_INTRQ                         0xa9 0x001
+#define MX27_PAD_IOIS16__GPIO6_9                           0xa9 0x032
+#define MX27_PAD_PC_RST__PC_RST                            0xaa 0x004
+#define MX27_PAD_PC_RST__ATA_RESET_B                       0xaa 0x005
+#define MX27_PAD_PC_RST__GPIO6_10                          0xaa 0x032
+#define MX27_PAD_PC_BVD2__PC_BVD2                          0xab 0x000
+#define MX27_PAD_PC_BVD2__ATA_DMACK                        0xab 0x005
+#define MX27_PAD_PC_BVD2__GPIO6_11                         0xab 0x032
+#define MX27_PAD_PC_BVD1__PC_BVD1                          0xac 0x000
+#define MX27_PAD_PC_BVD1__ATA_DMARQ                        0xac 0x001
+#define MX27_PAD_PC_BVD1__GPIO6_12                         0xac 0x032
+#define MX27_PAD_PC_VS2__PC_VS2                            0xad 0x000
+#define MX27_PAD_PC_VS2__ATA_DA0                           0xad 0x005
+#define MX27_PAD_PC_VS2__GPIO6_13                          0xad 0x032
+#define MX27_PAD_PC_VS1__PC_VS1                            0xae 0x000
+#define MX27_PAD_PC_VS1__ATA_DA1                           0xae 0x005
+#define MX27_PAD_PC_VS1__GPIO6_14                          0xae 0x032
+#define MX27_PAD_CLKO__CLKO                                0xaf 0x004
+#define MX27_PAD_CLKO__GPIO6_15                            0xaf 0x032
+#define MX27_PAD_PC_PWRON__PC_PWRON                        0xb0 0x000
+#define MX27_PAD_PC_PWRON__ATA_DA2                         0xb0 0x005
+#define MX27_PAD_PC_PWRON__GPIO6_16                        0xb0 0x032
+#define MX27_PAD_PC_READY__PC_READY                        0xb1 0x000
+#define MX27_PAD_PC_READY__ATA_CS0                         0xb1 0x005
+#define MX27_PAD_PC_READY__GPIO6_17                        0xb1 0x032
+#define MX27_PAD_PC_WAIT_B__PC_WAIT_B                      0xb2 0x000
+#define MX27_PAD_PC_WAIT_B__ATA_CS1                        0xb2 0x005
+#define MX27_PAD_PC_WAIT_B__GPIO6_18                       0xb2 0x032
+#define MX27_PAD_PC_CD2_B__PC_CD2_B                        0xb3 0x000
+#define MX27_PAD_PC_CD2_B__ATA_DIOW                        0xb3 0x005
+#define MX27_PAD_PC_CD2_B__GPIO6_19                        0xb3 0x032
+#define MX27_PAD_PC_CD1_B__PC_CD1_B                        0xb4 0x000
+#define MX27_PAD_PC_CD1_B__ATA_DIOR                        0xb4 0x005
+#define MX27_PAD_PC_CD1_B__GPIO6_20                        0xb4 0x032
+#define MX27_PAD_CS4_B__CS4_B                              0xb5 0x004
+#define MX27_PAD_CS4_B__ETMTRACESYNC                       0xb5 0x005
+#define MX27_PAD_CS4_B__GPIO6_21                           0xb5 0x032
+#define MX27_PAD_CS5_B__CS5_B                              0xb6 0x004
+#define MX27_PAD_CS5_B__ETMTRACECLK                        0xb6 0x005
+#define MX27_PAD_CS5_B__GPIO6_22                           0xb6 0x032
+#define MX27_PAD_ATA_DATA15__ATA_DATA15                    0xb7 0x004
+#define MX27_PAD_ATA_DATA15__ETMTRACEPKT4                  0xb7 0x005
+#define MX27_PAD_ATA_DATA15__FEC_TX_EN                     0xb7 0x006
+#define MX27_PAD_ATA_DATA15__GPIO6_23                      0xb7 0x032
+
+#endif /* __DTS_IMX27_PINFUNC_H */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/imx28-pinfunc.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/imx28-pinfunc.h
new file mode 100644
index 0000000000000000000000000000000000000000..e11f69ba0fe4b8d0dff85cb4e527ea16fdabeb19
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/imx28-pinfunc.h
@@ -0,0 +1,506 @@
+/*
+ * Header providing constants for i.MX28 pinctrl bindings.
+ *
+ * Copyright (C) 2013 Lothar Waßmann <LW@KARO-electronics.de>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#ifndef __DT_BINDINGS_MX28_PINCTRL_H__
+#define __DT_BINDINGS_MX28_PINCTRL_H__
+
+#include "mxs-pinfunc.h"
+
+#define MX28_PAD_GPMI_D00__GPMI_D0			0x0000
+#define MX28_PAD_GPMI_D01__GPMI_D1			0x0010
+#define MX28_PAD_GPMI_D02__GPMI_D2			0x0020
+#define MX28_PAD_GPMI_D03__GPMI_D3			0x0030
+#define MX28_PAD_GPMI_D04__GPMI_D4			0x0040
+#define MX28_PAD_GPMI_D05__GPMI_D5			0x0050
+#define MX28_PAD_GPMI_D06__GPMI_D6			0x0060
+#define MX28_PAD_GPMI_D07__GPMI_D7			0x0070
+#define MX28_PAD_GPMI_CE0N__GPMI_CE0N			0x0100
+#define MX28_PAD_GPMI_CE1N__GPMI_CE1N			0x0110
+#define MX28_PAD_GPMI_CE2N__GPMI_CE2N			0x0120
+#define MX28_PAD_GPMI_CE3N__GPMI_CE3N			0x0130
+#define MX28_PAD_GPMI_RDY0__GPMI_READY0			0x0140
+#define MX28_PAD_GPMI_RDY1__GPMI_READY1			0x0150
+#define MX28_PAD_GPMI_RDY2__GPMI_READY2			0x0160
+#define MX28_PAD_GPMI_RDY3__GPMI_READY3			0x0170
+#define MX28_PAD_GPMI_RDN__GPMI_RDN			0x0180
+#define MX28_PAD_GPMI_WRN__GPMI_WRN			0x0190
+#define MX28_PAD_GPMI_ALE__GPMI_ALE			0x01a0
+#define MX28_PAD_GPMI_CLE__GPMI_CLE			0x01b0
+#define MX28_PAD_GPMI_RESETN__GPMI_RESETN		0x01c0
+#define MX28_PAD_LCD_D00__LCD_D0			0x1000
+#define MX28_PAD_LCD_D01__LCD_D1			0x1010
+#define MX28_PAD_LCD_D02__LCD_D2			0x1020
+#define MX28_PAD_LCD_D03__LCD_D3			0x1030
+#define MX28_PAD_LCD_D04__LCD_D4			0x1040
+#define MX28_PAD_LCD_D05__LCD_D5			0x1050
+#define MX28_PAD_LCD_D06__LCD_D6			0x1060
+#define MX28_PAD_LCD_D07__LCD_D7			0x1070
+#define MX28_PAD_LCD_D08__LCD_D8			0x1080
+#define MX28_PAD_LCD_D09__LCD_D9			0x1090
+#define MX28_PAD_LCD_D10__LCD_D10			0x10a0
+#define MX28_PAD_LCD_D11__LCD_D11			0x10b0
+#define MX28_PAD_LCD_D12__LCD_D12			0x10c0
+#define MX28_PAD_LCD_D13__LCD_D13			0x10d0
+#define MX28_PAD_LCD_D14__LCD_D14			0x10e0
+#define MX28_PAD_LCD_D15__LCD_D15			0x10f0
+#define MX28_PAD_LCD_D16__LCD_D16			0x1100
+#define MX28_PAD_LCD_D17__LCD_D17			0x1110
+#define MX28_PAD_LCD_D18__LCD_D18			0x1120
+#define MX28_PAD_LCD_D19__LCD_D19			0x1130
+#define MX28_PAD_LCD_D20__LCD_D20			0x1140
+#define MX28_PAD_LCD_D21__LCD_D21			0x1150
+#define MX28_PAD_LCD_D22__LCD_D22			0x1160
+#define MX28_PAD_LCD_D23__LCD_D23			0x1170
+#define MX28_PAD_LCD_RD_E__LCD_RD_E			0x1180
+#define MX28_PAD_LCD_WR_RWN__LCD_WR_RWN			0x1190
+#define MX28_PAD_LCD_RS__LCD_RS				0x11a0
+#define MX28_PAD_LCD_CS__LCD_CS				0x11b0
+#define MX28_PAD_LCD_VSYNC__LCD_VSYNC			0x11c0
+#define MX28_PAD_LCD_HSYNC__LCD_HSYNC			0x11d0
+#define MX28_PAD_LCD_DOTCLK__LCD_DOTCLK			0x11e0
+#define MX28_PAD_LCD_ENABLE__LCD_ENABLE			0x11f0
+#define MX28_PAD_SSP0_DATA0__SSP0_D0			0x2000
+#define MX28_PAD_SSP0_DATA1__SSP0_D1			0x2010
+#define MX28_PAD_SSP0_DATA2__SSP0_D2			0x2020
+#define MX28_PAD_SSP0_DATA3__SSP0_D3			0x2030
+#define MX28_PAD_SSP0_DATA4__SSP0_D4			0x2040
+#define MX28_PAD_SSP0_DATA5__SSP0_D5			0x2050
+#define MX28_PAD_SSP0_DATA6__SSP0_D6			0x2060
+#define MX28_PAD_SSP0_DATA7__SSP0_D7			0x2070
+#define MX28_PAD_SSP0_CMD__SSP0_CMD			0x2080
+#define MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT		0x2090
+#define MX28_PAD_SSP0_SCK__SSP0_SCK			0x20a0
+#define MX28_PAD_SSP1_SCK__SSP1_SCK			0x20c0
+#define MX28_PAD_SSP1_CMD__SSP1_CMD			0x20d0
+#define MX28_PAD_SSP1_DATA0__SSP1_D0			0x20e0
+#define MX28_PAD_SSP1_DATA3__SSP1_D3			0x20f0
+#define MX28_PAD_SSP2_SCK__SSP2_SCK			0x2100
+#define MX28_PAD_SSP2_MOSI__SSP2_CMD			0x2110
+#define MX28_PAD_SSP2_MISO__SSP2_D0			0x2120
+#define MX28_PAD_SSP2_SS0__SSP2_D3			0x2130
+#define MX28_PAD_SSP2_SS1__SSP2_D4			0x2140
+#define MX28_PAD_SSP2_SS2__SSP2_D5			0x2150
+#define MX28_PAD_SSP3_SCK__SSP3_SCK			0x2180
+#define MX28_PAD_SSP3_MOSI__SSP3_CMD			0x2190
+#define MX28_PAD_SSP3_MISO__SSP3_D0			0x21a0
+#define MX28_PAD_SSP3_SS0__SSP3_D3			0x21b0
+#define MX28_PAD_AUART0_RX__AUART0_RX			0x3000
+#define MX28_PAD_AUART0_TX__AUART0_TX			0x3010
+#define MX28_PAD_AUART0_CTS__AUART0_CTS			0x3020
+#define MX28_PAD_AUART0_RTS__AUART0_RTS			0x3030
+#define MX28_PAD_AUART1_RX__AUART1_RX			0x3040
+#define MX28_PAD_AUART1_TX__AUART1_TX			0x3050
+#define MX28_PAD_AUART1_CTS__AUART1_CTS			0x3060
+#define MX28_PAD_AUART1_RTS__AUART1_RTS			0x3070
+#define MX28_PAD_AUART2_RX__AUART2_RX			0x3080
+#define MX28_PAD_AUART2_TX__AUART2_TX			0x3090
+#define MX28_PAD_AUART2_CTS__AUART2_CTS			0x30a0
+#define MX28_PAD_AUART2_RTS__AUART2_RTS			0x30b0
+#define MX28_PAD_AUART3_RX__AUART3_RX			0x30c0
+#define MX28_PAD_AUART3_TX__AUART3_TX			0x30d0
+#define MX28_PAD_AUART3_CTS__AUART3_CTS			0x30e0
+#define MX28_PAD_AUART3_RTS__AUART3_RTS			0x30f0
+#define MX28_PAD_PWM0__PWM_0				0x3100
+#define MX28_PAD_PWM1__PWM_1				0x3110
+#define MX28_PAD_PWM2__PWM_2				0x3120
+#define MX28_PAD_SAIF0_MCLK__SAIF0_MCLK			0x3140
+#define MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK		0x3150
+#define MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK		0x3160
+#define MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0		0x3170
+#define MX28_PAD_I2C0_SCL__I2C0_SCL			0x3180
+#define MX28_PAD_I2C0_SDA__I2C0_SDA			0x3190
+#define MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0		0x31a0
+#define MX28_PAD_SPDIF__SPDIF_TX			0x31b0
+#define MX28_PAD_PWM3__PWM_3				0x31c0
+#define MX28_PAD_PWM4__PWM_4				0x31d0
+#define MX28_PAD_LCD_RESET__LCD_RESET			0x31e0
+#define MX28_PAD_ENET0_MDC__ENET0_MDC			0x4000
+#define MX28_PAD_ENET0_MDIO__ENET0_MDIO			0x4010
+#define MX28_PAD_ENET0_RX_EN__ENET0_RX_EN		0x4020
+#define MX28_PAD_ENET0_RXD0__ENET0_RXD0			0x4030
+#define MX28_PAD_ENET0_RXD1__ENET0_RXD1			0x4040
+#define MX28_PAD_ENET0_TX_CLK__ENET0_TX_CLK		0x4050
+#define MX28_PAD_ENET0_TX_EN__ENET0_TX_EN		0x4060
+#define MX28_PAD_ENET0_TXD0__ENET0_TXD0			0x4070
+#define MX28_PAD_ENET0_TXD1__ENET0_TXD1			0x4080
+#define MX28_PAD_ENET0_RXD2__ENET0_RXD2			0x4090
+#define MX28_PAD_ENET0_RXD3__ENET0_RXD3			0x40a0
+#define MX28_PAD_ENET0_TXD2__ENET0_TXD2			0x40b0
+#define MX28_PAD_ENET0_TXD3__ENET0_TXD3			0x40c0
+#define MX28_PAD_ENET0_RX_CLK__ENET0_RX_CLK		0x40d0
+#define MX28_PAD_ENET0_COL__ENET0_COL			0x40e0
+#define MX28_PAD_ENET0_CRS__ENET0_CRS			0x40f0
+#define MX28_PAD_ENET_CLK__CLKCTRL_ENET			0x4100
+#define MX28_PAD_JTAG_RTCK__JTAG_RTCK			0x4140
+#define MX28_PAD_EMI_D00__EMI_DATA0			0x5000
+#define MX28_PAD_EMI_D01__EMI_DATA1			0x5010
+#define MX28_PAD_EMI_D02__EMI_DATA2			0x5020
+#define MX28_PAD_EMI_D03__EMI_DATA3			0x5030
+#define MX28_PAD_EMI_D04__EMI_DATA4			0x5040
+#define MX28_PAD_EMI_D05__EMI_DATA5			0x5050
+#define MX28_PAD_EMI_D06__EMI_DATA6			0x5060
+#define MX28_PAD_EMI_D07__EMI_DATA7			0x5070
+#define MX28_PAD_EMI_D08__EMI_DATA8			0x5080
+#define MX28_PAD_EMI_D09__EMI_DATA9			0x5090
+#define MX28_PAD_EMI_D10__EMI_DATA10			0x50a0
+#define MX28_PAD_EMI_D11__EMI_DATA11			0x50b0
+#define MX28_PAD_EMI_D12__EMI_DATA12			0x50c0
+#define MX28_PAD_EMI_D13__EMI_DATA13			0x50d0
+#define MX28_PAD_EMI_D14__EMI_DATA14			0x50e0
+#define MX28_PAD_EMI_D15__EMI_DATA15			0x50f0
+#define MX28_PAD_EMI_ODT0__EMI_ODT0			0x5100
+#define MX28_PAD_EMI_DQM0__EMI_DQM0			0x5110
+#define MX28_PAD_EMI_ODT1__EMI_ODT1			0x5120
+#define MX28_PAD_EMI_DQM1__EMI_DQM1			0x5130
+#define MX28_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK	0x5140
+#define MX28_PAD_EMI_CLK__EMI_CLK			0x5150
+#define MX28_PAD_EMI_DQS0__EMI_DQS0			0x5160
+#define MX28_PAD_EMI_DQS1__EMI_DQS1			0x5170
+#define MX28_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN		0x51a0
+#define MX28_PAD_EMI_A00__EMI_ADDR0			0x6000
+#define MX28_PAD_EMI_A01__EMI_ADDR1			0x6010
+#define MX28_PAD_EMI_A02__EMI_ADDR2			0x6020
+#define MX28_PAD_EMI_A03__EMI_ADDR3			0x6030
+#define MX28_PAD_EMI_A04__EMI_ADDR4			0x6040
+#define MX28_PAD_EMI_A05__EMI_ADDR5			0x6050
+#define MX28_PAD_EMI_A06__EMI_ADDR6			0x6060
+#define MX28_PAD_EMI_A07__EMI_ADDR7			0x6070
+#define MX28_PAD_EMI_A08__EMI_ADDR8			0x6080
+#define MX28_PAD_EMI_A09__EMI_ADDR9			0x6090
+#define MX28_PAD_EMI_A10__EMI_ADDR10			0x60a0
+#define MX28_PAD_EMI_A11__EMI_ADDR11			0x60b0
+#define MX28_PAD_EMI_A12__EMI_ADDR12			0x60c0
+#define MX28_PAD_EMI_A13__EMI_ADDR13			0x60d0
+#define MX28_PAD_EMI_A14__EMI_ADDR14			0x60e0
+#define MX28_PAD_EMI_BA0__EMI_BA0			0x6100
+#define MX28_PAD_EMI_BA1__EMI_BA1			0x6110
+#define MX28_PAD_EMI_BA2__EMI_BA2			0x6120
+#define MX28_PAD_EMI_CASN__EMI_CASN			0x6130
+#define MX28_PAD_EMI_RASN__EMI_RASN			0x6140
+#define MX28_PAD_EMI_WEN__EMI_WEN			0x6150
+#define MX28_PAD_EMI_CE0N__EMI_CE0N			0x6160
+#define MX28_PAD_EMI_CE1N__EMI_CE1N			0x6170
+#define MX28_PAD_EMI_CKE__EMI_CKE			0x6180
+#define MX28_PAD_GPMI_D00__SSP1_D0			0x0001
+#define MX28_PAD_GPMI_D01__SSP1_D1			0x0011
+#define MX28_PAD_GPMI_D02__SSP1_D2			0x0021
+#define MX28_PAD_GPMI_D03__SSP1_D3			0x0031
+#define MX28_PAD_GPMI_D04__SSP1_D4			0x0041
+#define MX28_PAD_GPMI_D05__SSP1_D5			0x0051
+#define MX28_PAD_GPMI_D06__SSP1_D6			0x0061
+#define MX28_PAD_GPMI_D07__SSP1_D7			0x0071
+#define MX28_PAD_GPMI_CE0N__SSP3_D0			0x0101
+#define MX28_PAD_GPMI_CE1N__SSP3_D3			0x0111
+#define MX28_PAD_GPMI_CE2N__CAN1_TX			0x0121
+#define MX28_PAD_GPMI_CE3N__CAN1_RX			0x0131
+#define MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT		0x0141
+#define MX28_PAD_GPMI_RDY1__SSP1_CMD			0x0151
+#define MX28_PAD_GPMI_RDY2__CAN0_TX			0x0161
+#define MX28_PAD_GPMI_RDY3__CAN0_RX			0x0171
+#define MX28_PAD_GPMI_RDN__SSP3_SCK			0x0181
+#define MX28_PAD_GPMI_WRN__SSP1_SCK			0x0191
+#define MX28_PAD_GPMI_ALE__SSP3_D1			0x01a1
+#define MX28_PAD_GPMI_CLE__SSP3_D2			0x01b1
+#define MX28_PAD_GPMI_RESETN__SSP3_CMD			0x01c1
+#define MX28_PAD_LCD_D03__ETM_DA8			0x1031
+#define MX28_PAD_LCD_D04__ETM_DA9			0x1041
+#define MX28_PAD_LCD_D08__ETM_DA3			0x1081
+#define MX28_PAD_LCD_D09__ETM_DA4			0x1091
+#define MX28_PAD_LCD_D20__ENET1_1588_EVENT2_OUT		0x1141
+#define MX28_PAD_LCD_D21__ENET1_1588_EVENT2_IN		0x1151
+#define MX28_PAD_LCD_D22__ENET1_1588_EVENT3_OUT		0x1161
+#define MX28_PAD_LCD_D23__ENET1_1588_EVENT3_IN		0x1171
+#define MX28_PAD_LCD_RD_E__LCD_VSYNC			0x1181
+#define MX28_PAD_LCD_WR_RWN__LCD_HSYNC			0x1191
+#define MX28_PAD_LCD_RS__LCD_DOTCLK			0x11a1
+#define MX28_PAD_LCD_CS__LCD_ENABLE			0x11b1
+#define MX28_PAD_LCD_VSYNC__SAIF1_SDATA0		0x11c1
+#define MX28_PAD_LCD_HSYNC__SAIF1_SDATA1		0x11d1
+#define MX28_PAD_LCD_DOTCLK__SAIF1_MCLK			0x11e1
+#define MX28_PAD_SSP0_DATA4__SSP2_D0			0x2041
+#define MX28_PAD_SSP0_DATA5__SSP2_D3			0x2051
+#define MX28_PAD_SSP0_DATA6__SSP2_CMD			0x2061
+#define MX28_PAD_SSP0_DATA7__SSP2_SCK			0x2071
+#define MX28_PAD_SSP1_SCK__SSP2_D1			0x20c1
+#define MX28_PAD_SSP1_CMD__SSP2_D2			0x20d1
+#define MX28_PAD_SSP1_DATA0__SSP2_D6			0x20e1
+#define MX28_PAD_SSP1_DATA3__SSP2_D7			0x20f1
+#define MX28_PAD_SSP2_SCK__AUART2_RX			0x2101
+#define MX28_PAD_SSP2_MOSI__AUART2_TX			0x2111
+#define MX28_PAD_SSP2_MISO__AUART3_RX			0x2121
+#define MX28_PAD_SSP2_SS0__AUART3_TX			0x2131
+#define MX28_PAD_SSP2_SS1__SSP2_D1			0x2141
+#define MX28_PAD_SSP2_SS2__SSP2_D2			0x2151
+#define MX28_PAD_SSP3_SCK__AUART4_TX			0x2181
+#define MX28_PAD_SSP3_MOSI__AUART4_RX			0x2191
+#define MX28_PAD_SSP3_MISO__AUART4_RTS			0x21a1
+#define MX28_PAD_SSP3_SS0__AUART4_CTS			0x21b1
+#define MX28_PAD_AUART0_RX__I2C0_SCL			0x3001
+#define MX28_PAD_AUART0_TX__I2C0_SDA			0x3011
+#define MX28_PAD_AUART0_CTS__AUART4_RX			0x3021
+#define MX28_PAD_AUART0_RTS__AUART4_TX			0x3031
+#define MX28_PAD_AUART1_RX__SSP2_CARD_DETECT		0x3041
+#define MX28_PAD_AUART1_TX__SSP3_CARD_DETECT		0x3051
+#define MX28_PAD_AUART1_CTS__USB0_OVERCURRENT		0x3061
+#define MX28_PAD_AUART1_RTS__USB0_ID			0x3071
+#define MX28_PAD_AUART2_RX__SSP3_D1			0x3081
+#define MX28_PAD_AUART2_TX__SSP3_D2			0x3091
+#define MX28_PAD_AUART2_CTS__I2C1_SCL			0x30a1
+#define MX28_PAD_AUART2_RTS__I2C1_SDA			0x30b1
+#define MX28_PAD_AUART3_RX__CAN0_TX			0x30c1
+#define MX28_PAD_AUART3_TX__CAN0_RX			0x30d1
+#define MX28_PAD_AUART3_CTS__CAN1_TX			0x30e1
+#define MX28_PAD_AUART3_RTS__CAN1_RX			0x30f1
+#define MX28_PAD_PWM0__I2C1_SCL				0x3101
+#define MX28_PAD_PWM1__I2C1_SDA				0x3111
+#define MX28_PAD_PWM2__USB0_ID				0x3121
+#define MX28_PAD_SAIF0_MCLK__PWM_3			0x3141
+#define MX28_PAD_SAIF0_LRCLK__PWM_4			0x3151
+#define MX28_PAD_SAIF0_BITCLK__PWM_5			0x3161
+#define MX28_PAD_SAIF0_SDATA0__PWM_6			0x3171
+#define MX28_PAD_I2C0_SCL__TIMROT_ROTARYA		0x3181
+#define MX28_PAD_I2C0_SDA__TIMROT_ROTARYB		0x3191
+#define MX28_PAD_SAIF1_SDATA0__PWM_7			0x31a1
+#define MX28_PAD_LCD_RESET__LCD_VSYNC			0x31e1
+#define MX28_PAD_ENET0_MDC__GPMI_CE4N			0x4001
+#define MX28_PAD_ENET0_MDIO__GPMI_CE5N			0x4011
+#define MX28_PAD_ENET0_RX_EN__GPMI_CE6N			0x4021
+#define MX28_PAD_ENET0_RXD0__GPMI_CE7N			0x4031
+#define MX28_PAD_ENET0_RXD1__GPMI_READY4		0x4041
+#define MX28_PAD_ENET0_TX_CLK__HSADC_TRIGGER		0x4051
+#define MX28_PAD_ENET0_TX_EN__GPMI_READY5		0x4061
+#define MX28_PAD_ENET0_TXD0__GPMI_READY6		0x4071
+#define MX28_PAD_ENET0_TXD1__GPMI_READY7		0x4081
+#define MX28_PAD_ENET0_RXD2__ENET1_RXD0			0x4091
+#define MX28_PAD_ENET0_RXD3__ENET1_RXD1			0x40a1
+#define MX28_PAD_ENET0_TXD2__ENET1_TXD0			0x40b1
+#define MX28_PAD_ENET0_TXD3__ENET1_TXD1			0x40c1
+#define MX28_PAD_ENET0_RX_CLK__ENET0_RX_ER		0x40d1
+#define MX28_PAD_ENET0_COL__ENET1_TX_EN			0x40e1
+#define MX28_PAD_ENET0_CRS__ENET1_RX_EN			0x40f1
+#define MX28_PAD_GPMI_CE2N__ENET0_RX_ER			0x0122
+#define MX28_PAD_GPMI_CE3N__SAIF1_MCLK			0x0132
+#define MX28_PAD_GPMI_RDY0__USB0_ID			0x0142
+#define MX28_PAD_GPMI_RDY2__ENET0_TX_ER			0x0162
+#define MX28_PAD_GPMI_RDY3__HSADC_TRIGGER		0x0172
+#define MX28_PAD_GPMI_ALE__SSP3_D4			0x01a2
+#define MX28_PAD_GPMI_CLE__SSP3_D5			0x01b2
+#define MX28_PAD_LCD_D00__ETM_DA0			0x1002
+#define MX28_PAD_LCD_D01__ETM_DA1			0x1012
+#define MX28_PAD_LCD_D02__ETM_DA2			0x1022
+#define MX28_PAD_LCD_D03__ETM_DA3			0x1032
+#define MX28_PAD_LCD_D04__ETM_DA4			0x1042
+#define MX28_PAD_LCD_D05__ETM_DA5			0x1052
+#define MX28_PAD_LCD_D06__ETM_DA6			0x1062
+#define MX28_PAD_LCD_D07__ETM_DA7			0x1072
+#define MX28_PAD_LCD_D08__ETM_DA8			0x1082
+#define MX28_PAD_LCD_D09__ETM_DA9			0x1092
+#define MX28_PAD_LCD_D10__ETM_DA10			0x10a2
+#define MX28_PAD_LCD_D11__ETM_DA11			0x10b2
+#define MX28_PAD_LCD_D12__ETM_DA12			0x10c2
+#define MX28_PAD_LCD_D13__ETM_DA13			0x10d2
+#define MX28_PAD_LCD_D14__ETM_DA14			0x10e2
+#define MX28_PAD_LCD_D15__ETM_DA15			0x10f2
+#define MX28_PAD_LCD_D16__ETM_DA7			0x1102
+#define MX28_PAD_LCD_D17__ETM_DA6			0x1112
+#define MX28_PAD_LCD_D18__ETM_DA5			0x1122
+#define MX28_PAD_LCD_D19__ETM_DA4			0x1132
+#define MX28_PAD_LCD_D20__ETM_DA3			0x1142
+#define MX28_PAD_LCD_D21__ETM_DA2			0x1152
+#define MX28_PAD_LCD_D22__ETM_DA1			0x1162
+#define MX28_PAD_LCD_D23__ETM_DA0			0x1172
+#define MX28_PAD_LCD_RD_E__ETM_TCTL			0x1182
+#define MX28_PAD_LCD_WR_RWN__ETM_TCLK			0x1192
+#define MX28_PAD_LCD_HSYNC__ETM_TCTL			0x11d2
+#define MX28_PAD_LCD_DOTCLK__ETM_TCLK			0x11e2
+#define MX28_PAD_SSP1_SCK__ENET0_1588_EVENT2_OUT	0x20c2
+#define MX28_PAD_SSP1_CMD__ENET0_1588_EVENT2_IN		0x20d2
+#define MX28_PAD_SSP1_DATA0__ENET0_1588_EVENT3_OUT	0x20e2
+#define MX28_PAD_SSP1_DATA3__ENET0_1588_EVENT3_IN	0x20f2
+#define MX28_PAD_SSP2_SCK__SAIF0_SDATA1			0x2102
+#define MX28_PAD_SSP2_MOSI__SAIF0_SDATA2		0x2112
+#define MX28_PAD_SSP2_MISO__SAIF1_SDATA1		0x2122
+#define MX28_PAD_SSP2_SS0__SAIF1_SDATA2			0x2132
+#define MX28_PAD_SSP2_SS1__USB1_OVERCURRENT		0x2142
+#define MX28_PAD_SSP2_SS2__USB0_OVERCURRENT		0x2152
+#define MX28_PAD_SSP3_SCK__ENET1_1588_EVENT0_OUT	0x2182
+#define MX28_PAD_SSP3_MOSI__ENET1_1588_EVENT0_IN	0x2192
+#define MX28_PAD_SSP3_MISO__ENET1_1588_EVENT1_OUT	0x21a2
+#define MX28_PAD_SSP3_SS0__ENET1_1588_EVENT1_IN		0x21b2
+#define MX28_PAD_AUART0_RX__DUART_CTS			0x3002
+#define MX28_PAD_AUART0_TX__DUART_RTS			0x3012
+#define MX28_PAD_AUART0_CTS__DUART_RX			0x3022
+#define MX28_PAD_AUART0_RTS__DUART_TX			0x3032
+#define MX28_PAD_AUART1_RX__PWM_0			0x3042
+#define MX28_PAD_AUART1_TX__PWM_1			0x3052
+#define MX28_PAD_AUART1_CTS__TIMROT_ROTARYA		0x3062
+#define MX28_PAD_AUART1_RTS__TIMROT_ROTARYB		0x3072
+#define MX28_PAD_AUART2_RX__SSP3_D4			0x3082
+#define MX28_PAD_AUART2_TX__SSP3_D5			0x3092
+#define MX28_PAD_AUART2_CTS__SAIF1_BITCLK		0x30a2
+#define MX28_PAD_AUART2_RTS__SAIF1_LRCLK		0x30b2
+#define MX28_PAD_AUART3_RX__ENET0_1588_EVENT0_OUT	0x30c2
+#define MX28_PAD_AUART3_TX__ENET0_1588_EVENT0_IN	0x30d2
+#define MX28_PAD_AUART3_CTS__ENET0_1588_EVENT1_OUT	0x30e2
+#define MX28_PAD_AUART3_RTS__ENET0_1588_EVENT1_IN	0x30f2
+#define MX28_PAD_PWM0__DUART_RX				0x3102
+#define MX28_PAD_PWM1__DUART_TX				0x3112
+#define MX28_PAD_PWM2__USB1_OVERCURRENT			0x3122
+#define MX28_PAD_SAIF0_MCLK__AUART4_CTS			0x3142
+#define MX28_PAD_SAIF0_LRCLK__AUART4_RTS		0x3152
+#define MX28_PAD_SAIF0_BITCLK__AUART4_RX		0x3162
+#define MX28_PAD_SAIF0_SDATA0__AUART4_TX		0x3172
+#define MX28_PAD_I2C0_SCL__DUART_RX			0x3182
+#define MX28_PAD_I2C0_SDA__DUART_TX			0x3192
+#define MX28_PAD_SAIF1_SDATA0__SAIF0_SDATA1		0x31a2
+#define MX28_PAD_SPDIF__ENET1_RX_ER			0x31b2
+#define MX28_PAD_ENET0_MDC__SAIF0_SDATA1		0x4002
+#define MX28_PAD_ENET0_MDIO__SAIF0_SDATA2		0x4012
+#define MX28_PAD_ENET0_RX_EN__SAIF1_SDATA1		0x4022
+#define MX28_PAD_ENET0_RXD0__SAIF1_SDATA2		0x4032
+#define MX28_PAD_ENET0_TX_CLK__ENET0_1588_EVENT2_OUT	0x4052
+#define MX28_PAD_ENET0_RXD2__ENET0_1588_EVENT0_OUT	0x4092
+#define MX28_PAD_ENET0_RXD3__ENET0_1588_EVENT0_IN	0x40a2
+#define MX28_PAD_ENET0_TXD2__ENET0_1588_EVENT1_OUT	0x40b2
+#define MX28_PAD_ENET0_TXD3__ENET0_1588_EVENT1_IN	0x40c2
+#define MX28_PAD_ENET0_RX_CLK__ENET0_1588_EVENT2_IN	0x40d2
+#define MX28_PAD_ENET0_COL__ENET0_1588_EVENT3_OUT	0x40e2
+#define MX28_PAD_ENET0_CRS__ENET0_1588_EVENT3_IN	0x40f2
+#define MX28_PAD_GPMI_D00__GPIO_0_0			0x0003
+#define MX28_PAD_GPMI_D01__GPIO_0_1			0x0013
+#define MX28_PAD_GPMI_D02__GPIO_0_2			0x0023
+#define MX28_PAD_GPMI_D03__GPIO_0_3			0x0033
+#define MX28_PAD_GPMI_D04__GPIO_0_4			0x0043
+#define MX28_PAD_GPMI_D05__GPIO_0_5			0x0053
+#define MX28_PAD_GPMI_D06__GPIO_0_6			0x0063
+#define MX28_PAD_GPMI_D07__GPIO_0_7			0x0073
+#define MX28_PAD_GPMI_CE0N__GPIO_0_16			0x0103
+#define MX28_PAD_GPMI_CE1N__GPIO_0_17			0x0113
+#define MX28_PAD_GPMI_CE2N__GPIO_0_18			0x0123
+#define MX28_PAD_GPMI_CE3N__GPIO_0_19			0x0133
+#define MX28_PAD_GPMI_RDY0__GPIO_0_20			0x0143
+#define MX28_PAD_GPMI_RDY1__GPIO_0_21			0x0153
+#define MX28_PAD_GPMI_RDY2__GPIO_0_22			0x0163
+#define MX28_PAD_GPMI_RDY3__GPIO_0_23			0x0173
+#define MX28_PAD_GPMI_RDN__GPIO_0_24			0x0183
+#define MX28_PAD_GPMI_WRN__GPIO_0_25			0x0193
+#define MX28_PAD_GPMI_ALE__GPIO_0_26			0x01a3
+#define MX28_PAD_GPMI_CLE__GPIO_0_27			0x01b3
+#define MX28_PAD_GPMI_RESETN__GPIO_0_28			0x01c3
+#define MX28_PAD_LCD_D00__GPIO_1_0			0x1003
+#define MX28_PAD_LCD_D01__GPIO_1_1			0x1013
+#define MX28_PAD_LCD_D02__GPIO_1_2			0x1023
+#define MX28_PAD_LCD_D03__GPIO_1_3			0x1033
+#define MX28_PAD_LCD_D04__GPIO_1_4			0x1043
+#define MX28_PAD_LCD_D05__GPIO_1_5			0x1053
+#define MX28_PAD_LCD_D06__GPIO_1_6			0x1063
+#define MX28_PAD_LCD_D07__GPIO_1_7			0x1073
+#define MX28_PAD_LCD_D08__GPIO_1_8			0x1083
+#define MX28_PAD_LCD_D09__GPIO_1_9			0x1093
+#define MX28_PAD_LCD_D10__GPIO_1_10			0x10a3
+#define MX28_PAD_LCD_D11__GPIO_1_11			0x10b3
+#define MX28_PAD_LCD_D12__GPIO_1_12			0x10c3
+#define MX28_PAD_LCD_D13__GPIO_1_13			0x10d3
+#define MX28_PAD_LCD_D14__GPIO_1_14			0x10e3
+#define MX28_PAD_LCD_D15__GPIO_1_15			0x10f3
+#define MX28_PAD_LCD_D16__GPIO_1_16			0x1103
+#define MX28_PAD_LCD_D17__GPIO_1_17			0x1113
+#define MX28_PAD_LCD_D18__GPIO_1_18			0x1123
+#define MX28_PAD_LCD_D19__GPIO_1_19			0x1133
+#define MX28_PAD_LCD_D20__GPIO_1_20			0x1143
+#define MX28_PAD_LCD_D21__GPIO_1_21			0x1153
+#define MX28_PAD_LCD_D22__GPIO_1_22			0x1163
+#define MX28_PAD_LCD_D23__GPIO_1_23			0x1173
+#define MX28_PAD_LCD_RD_E__GPIO_1_24			0x1183
+#define MX28_PAD_LCD_WR_RWN__GPIO_1_25			0x1193
+#define MX28_PAD_LCD_RS__GPIO_1_26			0x11a3
+#define MX28_PAD_LCD_CS__GPIO_1_27			0x11b3
+#define MX28_PAD_LCD_VSYNC__GPIO_1_28			0x11c3
+#define MX28_PAD_LCD_HSYNC__GPIO_1_29			0x11d3
+#define MX28_PAD_LCD_DOTCLK__GPIO_1_30			0x11e3
+#define MX28_PAD_LCD_ENABLE__GPIO_1_31			0x11f3
+#define MX28_PAD_SSP0_DATA0__GPIO_2_0			0x2003
+#define MX28_PAD_SSP0_DATA1__GPIO_2_1			0x2013
+#define MX28_PAD_SSP0_DATA2__GPIO_2_2			0x2023
+#define MX28_PAD_SSP0_DATA3__GPIO_2_3			0x2033
+#define MX28_PAD_SSP0_DATA4__GPIO_2_4			0x2043
+#define MX28_PAD_SSP0_DATA5__GPIO_2_5			0x2053
+#define MX28_PAD_SSP0_DATA6__GPIO_2_6			0x2063
+#define MX28_PAD_SSP0_DATA7__GPIO_2_7			0x2073
+#define MX28_PAD_SSP0_CMD__GPIO_2_8			0x2083
+#define MX28_PAD_SSP0_DETECT__GPIO_2_9			0x2093
+#define MX28_PAD_SSP0_SCK__GPIO_2_10			0x20a3
+#define MX28_PAD_SSP1_SCK__GPIO_2_12			0x20c3
+#define MX28_PAD_SSP1_CMD__GPIO_2_13			0x20d3
+#define MX28_PAD_SSP1_DATA0__GPIO_2_14			0x20e3
+#define MX28_PAD_SSP1_DATA3__GPIO_2_15			0x20f3
+#define MX28_PAD_SSP2_SCK__GPIO_2_16			0x2103
+#define MX28_PAD_SSP2_MOSI__GPIO_2_17			0x2113
+#define MX28_PAD_SSP2_MISO__GPIO_2_18			0x2123
+#define MX28_PAD_SSP2_SS0__GPIO_2_19			0x2133
+#define MX28_PAD_SSP2_SS1__GPIO_2_20			0x2143
+#define MX28_PAD_SSP2_SS2__GPIO_2_21			0x2153
+#define MX28_PAD_SSP3_SCK__GPIO_2_24			0x2183
+#define MX28_PAD_SSP3_MOSI__GPIO_2_25			0x2193
+#define MX28_PAD_SSP3_MISO__GPIO_2_26			0x21a3
+#define MX28_PAD_SSP3_SS0__GPIO_2_27			0x21b3
+#define MX28_PAD_AUART0_RX__GPIO_3_0			0x3003
+#define MX28_PAD_AUART0_TX__GPIO_3_1			0x3013
+#define MX28_PAD_AUART0_CTS__GPIO_3_2			0x3023
+#define MX28_PAD_AUART0_RTS__GPIO_3_3			0x3033
+#define MX28_PAD_AUART1_RX__GPIO_3_4			0x3043
+#define MX28_PAD_AUART1_TX__GPIO_3_5			0x3053
+#define MX28_PAD_AUART1_CTS__GPIO_3_6			0x3063
+#define MX28_PAD_AUART1_RTS__GPIO_3_7			0x3073
+#define MX28_PAD_AUART2_RX__GPIO_3_8			0x3083
+#define MX28_PAD_AUART2_TX__GPIO_3_9			0x3093
+#define MX28_PAD_AUART2_CTS__GPIO_3_10			0x30a3
+#define MX28_PAD_AUART2_RTS__GPIO_3_11			0x30b3
+#define MX28_PAD_AUART3_RX__GPIO_3_12			0x30c3
+#define MX28_PAD_AUART3_TX__GPIO_3_13			0x30d3
+#define MX28_PAD_AUART3_CTS__GPIO_3_14			0x30e3
+#define MX28_PAD_AUART3_RTS__GPIO_3_15			0x30f3
+#define MX28_PAD_PWM0__GPIO_3_16			0x3103
+#define MX28_PAD_PWM1__GPIO_3_17			0x3113
+#define MX28_PAD_PWM2__GPIO_3_18			0x3123
+#define MX28_PAD_SAIF0_MCLK__GPIO_3_20			0x3143
+#define MX28_PAD_SAIF0_LRCLK__GPIO_3_21			0x3153
+#define MX28_PAD_SAIF0_BITCLK__GPIO_3_22		0x3163
+#define MX28_PAD_SAIF0_SDATA0__GPIO_3_23		0x3173
+#define MX28_PAD_I2C0_SCL__GPIO_3_24			0x3183
+#define MX28_PAD_I2C0_SDA__GPIO_3_25			0x3193
+#define MX28_PAD_SAIF1_SDATA0__GPIO_3_26		0x31a3
+#define MX28_PAD_SPDIF__GPIO_3_27			0x31b3
+#define MX28_PAD_PWM3__GPIO_3_28			0x31c3
+#define MX28_PAD_PWM4__GPIO_3_29			0x31d3
+#define MX28_PAD_LCD_RESET__GPIO_3_30			0x31e3
+#define MX28_PAD_ENET0_MDC__GPIO_4_0			0x4003
+#define MX28_PAD_ENET0_MDIO__GPIO_4_1			0x4013
+#define MX28_PAD_ENET0_RX_EN__GPIO_4_2			0x4023
+#define MX28_PAD_ENET0_RXD0__GPIO_4_3			0x4033
+#define MX28_PAD_ENET0_RXD1__GPIO_4_4			0x4043
+#define MX28_PAD_ENET0_TX_CLK__GPIO_4_5			0x4053
+#define MX28_PAD_ENET0_TX_EN__GPIO_4_6			0x4063
+#define MX28_PAD_ENET0_TXD0__GPIO_4_7			0x4073
+#define MX28_PAD_ENET0_TXD1__GPIO_4_8			0x4083
+#define MX28_PAD_ENET0_RXD2__GPIO_4_9			0x4093
+#define MX28_PAD_ENET0_RXD3__GPIO_4_10			0x40a3
+#define MX28_PAD_ENET0_TXD2__GPIO_4_11			0x40b3
+#define MX28_PAD_ENET0_TXD3__GPIO_4_12			0x40c3
+#define MX28_PAD_ENET0_RX_CLK__GPIO_4_13		0x40d3
+#define MX28_PAD_ENET0_COL__GPIO_4_14			0x40e3
+#define MX28_PAD_ENET0_CRS__GPIO_4_15			0x40f3
+#define MX28_PAD_ENET_CLK__GPIO_4_16			0x4103
+#define MX28_PAD_JTAG_RTCK__GPIO_4_20			0x4143
+
+#endif /* __DT_BINDINGS_MX28_PINCTRL_H__ */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/imx35-pinfunc.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/imx35-pinfunc.h
new file mode 100644
index 0000000000000000000000000000000000000000..4911f2c405fa5bb40c851558c7ad56995a39ffbf
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/imx35-pinfunc.h
@@ -0,0 +1,970 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __DTS_IMX35_PINFUNC_H
+#define __DTS_IMX35_PINFUNC_H
+
+/*
+ * The pin function ID is a tuple of
+ * <mux_reg conf_reg input_reg mux_mode input_val>
+ */
+#define MX35_PAD_CAPTURE__GPT_CAPIN1				0x004 0x328 0x000 0x0 0x0
+#define MX35_PAD_CAPTURE__GPT_CMPOUT2				0x004 0x328 0x000 0x1 0x0
+#define MX35_PAD_CAPTURE__CSPI2_SS1				0x004 0x328 0x7f4 0x2 0x0
+#define MX35_PAD_CAPTURE__EPIT1_EPITO				0x004 0x328 0x000 0x3 0x0
+#define MX35_PAD_CAPTURE__CCM_CLK32K				0x004 0x328 0x7d0 0x4 0x0
+#define MX35_PAD_CAPTURE__GPIO1_4				0x004 0x328 0x850 0x5 0x0
+#define MX35_PAD_COMPARE__GPT_CMPOUT1				0x008 0x32c 0x000 0x0 0x0
+#define MX35_PAD_COMPARE__GPT_CAPIN2				0x008 0x32c 0x000 0x1 0x0
+#define MX35_PAD_COMPARE__GPT_CMPOUT3				0x008 0x32c 0x000 0x2 0x0
+#define MX35_PAD_COMPARE__EPIT2_EPITO				0x008 0x32c 0x000 0x3 0x0
+#define MX35_PAD_COMPARE__GPIO1_5				0x008 0x32c 0x854 0x5 0x0
+#define MX35_PAD_COMPARE__SDMA_EXTDMA_2				0x008 0x32c 0x000 0x7 0x0
+#define MX35_PAD_WDOG_RST__WDOG_WDOG_B				0x00c 0x330 0x000 0x0 0x0
+#define MX35_PAD_WDOG_RST__IPU_FLASH_STROBE			0x00c 0x330 0x000 0x3 0x0
+#define MX35_PAD_WDOG_RST__GPIO1_6				0x00c 0x330 0x858 0x5 0x0
+#define MX35_PAD_GPIO1_0__GPIO1_0				0x010 0x334 0x82c 0x0 0x0
+#define MX35_PAD_GPIO1_0__CCM_PMIC_RDY				0x010 0x334 0x7d4 0x1 0x0
+#define MX35_PAD_GPIO1_0__OWIRE_LINE				0x010 0x334 0x990 0x2 0x0
+#define MX35_PAD_GPIO1_0__SDMA_EXTDMA_0				0x010 0x334 0x000 0x7 0x0
+#define MX35_PAD_GPIO1_1__GPIO1_1				0x014 0x338 0x838 0x0 0x0
+#define MX35_PAD_GPIO1_1__PWM_PWMO				0x014 0x338 0x000 0x2 0x0
+#define MX35_PAD_GPIO1_1__CSPI1_SS2				0x014 0x338 0x7d8 0x3 0x0
+#define MX35_PAD_GPIO1_1__SCC_TAMPER_DETECT			0x014 0x338 0x000 0x6 0x0
+#define MX35_PAD_GPIO1_1__SDMA_EXTDMA_1				0x014 0x338 0x000 0x7 0x0
+#define MX35_PAD_GPIO2_0__GPIO2_0				0x018 0x33c 0x868 0x0 0x0
+#define MX35_PAD_GPIO2_0__USB_TOP_USBOTG_CLK			0x018 0x33c 0x000 0x1 0x0
+#define MX35_PAD_GPIO3_0__GPIO3_0				0x01c 0x340 0x8e8 0x0 0x0
+#define MX35_PAD_GPIO3_0__USB_TOP_USBH2_CLK			0x01c 0x340 0x000 0x1 0x0
+#define MX35_PAD_RESET_IN_B__CCM_RESET_IN_B			0x000 0x344 0x000 0x0 0x0
+#define MX35_PAD_POR_B__CCM_POR_B				0x000 0x348 0x000 0x0 0x0
+#define MX35_PAD_CLKO__CCM_CLKO					0x020 0x34c 0x000 0x0 0x0
+#define MX35_PAD_CLKO__GPIO1_8					0x020 0x34c 0x860 0x5 0x0
+#define MX35_PAD_BOOT_MODE0__CCM_BOOT_MODE_0			0x000 0x350 0x000 0x0 0x0
+#define MX35_PAD_BOOT_MODE1__CCM_BOOT_MODE_1			0x000 0x354 0x000 0x0 0x0
+#define MX35_PAD_CLK_MODE0__CCM_CLK_MODE_0			0x000 0x358 0x000 0x0 0x0
+#define MX35_PAD_CLK_MODE1__CCM_CLK_MODE_1			0x000 0x35c 0x000 0x0 0x0
+#define MX35_PAD_POWER_FAIL__CCM_DSM_WAKEUP_INT_26		0x000 0x360 0x000 0x0 0x0
+#define MX35_PAD_VSTBY__CCM_VSTBY				0x024 0x364 0x000 0x0 0x0
+#define MX35_PAD_VSTBY__GPIO1_7					0x024 0x364 0x85c 0x5 0x0
+#define MX35_PAD_A0__EMI_EIM_DA_L_0				0x028 0x368 0x000 0x0 0x0
+#define MX35_PAD_A1__EMI_EIM_DA_L_1				0x02c 0x36c 0x000 0x0 0x0
+#define MX35_PAD_A2__EMI_EIM_DA_L_2				0x030 0x370 0x000 0x0 0x0
+#define MX35_PAD_A3__EMI_EIM_DA_L_3				0x034 0x374 0x000 0x0 0x0
+#define MX35_PAD_A4__EMI_EIM_DA_L_4				0x038 0x378 0x000 0x0 0x0
+#define MX35_PAD_A5__EMI_EIM_DA_L_5				0x03c 0x37c 0x000 0x0 0x0
+#define MX35_PAD_A6__EMI_EIM_DA_L_6				0x040 0x380 0x000 0x0 0x0
+#define MX35_PAD_A7__EMI_EIM_DA_L_7				0x044 0x384 0x000 0x0 0x0
+#define MX35_PAD_A8__EMI_EIM_DA_H_8				0x048 0x388 0x000 0x0 0x0
+#define MX35_PAD_A9__EMI_EIM_DA_H_9				0x04c 0x38c 0x000 0x0 0x0
+#define MX35_PAD_A10__EMI_EIM_DA_H_10				0x050 0x390 0x000 0x0 0x0
+#define MX35_PAD_MA10__EMI_MA10					0x054 0x394 0x000 0x0 0x0
+#define MX35_PAD_A11__EMI_EIM_DA_H_11				0x058 0x398 0x000 0x0 0x0
+#define MX35_PAD_A12__EMI_EIM_DA_H_12				0x05c 0x39c 0x000 0x0 0x0
+#define MX35_PAD_A13__EMI_EIM_DA_H_13				0x060 0x3a0 0x000 0x0 0x0
+#define MX35_PAD_A14__EMI_EIM_DA_H2_14				0x064 0x3a4 0x000 0x0 0x0
+#define MX35_PAD_A15__EMI_EIM_DA_H2_15				0x068 0x3a8 0x000 0x0 0x0
+#define MX35_PAD_A16__EMI_EIM_A_16				0x06c 0x3ac 0x000 0x0 0x0
+#define MX35_PAD_A17__EMI_EIM_A_17				0x070 0x3b0 0x000 0x0 0x0
+#define MX35_PAD_A18__EMI_EIM_A_18				0x074 0x3b4 0x000 0x0 0x0
+#define MX35_PAD_A19__EMI_EIM_A_19				0x078 0x3b8 0x000 0x0 0x0
+#define MX35_PAD_A20__EMI_EIM_A_20				0x07c 0x3bc 0x000 0x0 0x0
+#define MX35_PAD_A21__EMI_EIM_A_21				0x080 0x3c0 0x000 0x0 0x0
+#define MX35_PAD_A22__EMI_EIM_A_22				0x084 0x3c4 0x000 0x0 0x0
+#define MX35_PAD_A23__EMI_EIM_A_23				0x088 0x3c8 0x000 0x0 0x0
+#define MX35_PAD_A24__EMI_EIM_A_24				0x08c 0x3cc 0x000 0x0 0x0
+#define MX35_PAD_A25__EMI_EIM_A_25				0x090 0x3d0 0x000 0x0 0x0
+#define MX35_PAD_SDBA1__EMI_EIM_SDBA1				0x000 0x3d4 0x000 0x0 0x0
+#define MX35_PAD_SDBA0__EMI_EIM_SDBA0				0x000 0x3d8 0x000 0x0 0x0
+#define MX35_PAD_SD0__EMI_DRAM_D_0				0x000 0x3dc 0x000 0x0 0x0
+#define MX35_PAD_SD1__EMI_DRAM_D_1				0x000 0x3e0 0x000 0x0 0x0
+#define MX35_PAD_SD2__EMI_DRAM_D_2				0x000 0x3e4 0x000 0x0 0x0
+#define MX35_PAD_SD3__EMI_DRAM_D_3				0x000 0x3e8 0x000 0x0 0x0
+#define MX35_PAD_SD4__EMI_DRAM_D_4				0x000 0x3ec 0x000 0x0 0x0
+#define MX35_PAD_SD5__EMI_DRAM_D_5				0x000 0x3f0 0x000 0x0 0x0
+#define MX35_PAD_SD6__EMI_DRAM_D_6				0x000 0x3f4 0x000 0x0 0x0
+#define MX35_PAD_SD7__EMI_DRAM_D_7				0x000 0x3f8 0x000 0x0 0x0
+#define MX35_PAD_SD8__EMI_DRAM_D_8				0x000 0x3fc 0x000 0x0 0x0
+#define MX35_PAD_SD9__EMI_DRAM_D_9				0x000 0x400 0x000 0x0 0x0
+#define MX35_PAD_SD10__EMI_DRAM_D_10				0x000 0x404 0x000 0x0 0x0
+#define MX35_PAD_SD11__EMI_DRAM_D_11				0x000 0x408 0x000 0x0 0x0
+#define MX35_PAD_SD12__EMI_DRAM_D_12				0x000 0x40c 0x000 0x0 0x0
+#define MX35_PAD_SD13__EMI_DRAM_D_13				0x000 0x410 0x000 0x0 0x0
+#define MX35_PAD_SD14__EMI_DRAM_D_14				0x000 0x414 0x000 0x0 0x0
+#define MX35_PAD_SD15__EMI_DRAM_D_15				0x000 0x418 0x000 0x0 0x0
+#define MX35_PAD_SD16__EMI_DRAM_D_16				0x000 0x41c 0x000 0x0 0x0
+#define MX35_PAD_SD17__EMI_DRAM_D_17				0x000 0x420 0x000 0x0 0x0
+#define MX35_PAD_SD18__EMI_DRAM_D_18				0x000 0x424 0x000 0x0 0x0
+#define MX35_PAD_SD19__EMI_DRAM_D_19				0x000 0x428 0x000 0x0 0x0
+#define MX35_PAD_SD20__EMI_DRAM_D_20				0x000 0x42c 0x000 0x0 0x0
+#define MX35_PAD_SD21__EMI_DRAM_D_21				0x000 0x430 0x000 0x0 0x0
+#define MX35_PAD_SD22__EMI_DRAM_D_22				0x000 0x434 0x000 0x0 0x0
+#define MX35_PAD_SD23__EMI_DRAM_D_23				0x000 0x438 0x000 0x0 0x0
+#define MX35_PAD_SD24__EMI_DRAM_D_24				0x000 0x43c 0x000 0x0 0x0
+#define MX35_PAD_SD25__EMI_DRAM_D_25				0x000 0x440 0x000 0x0 0x0
+#define MX35_PAD_SD26__EMI_DRAM_D_26				0x000 0x444 0x000 0x0 0x0
+#define MX35_PAD_SD27__EMI_DRAM_D_27				0x000 0x448 0x000 0x0 0x0
+#define MX35_PAD_SD28__EMI_DRAM_D_28				0x000 0x44c 0x000 0x0 0x0
+#define MX35_PAD_SD29__EMI_DRAM_D_29				0x000 0x450 0x000 0x0 0x0
+#define MX35_PAD_SD30__EMI_DRAM_D_30				0x000 0x454 0x000 0x0 0x0
+#define MX35_PAD_SD31__EMI_DRAM_D_31				0x000 0x458 0x000 0x0 0x0
+#define MX35_PAD_DQM0__EMI_DRAM_DQM_0				0x000 0x45c 0x000 0x0 0x0
+#define MX35_PAD_DQM1__EMI_DRAM_DQM_1				0x000 0x460 0x000 0x0 0x0
+#define MX35_PAD_DQM2__EMI_DRAM_DQM_2				0x000 0x464 0x000 0x0 0x0
+#define MX35_PAD_DQM3__EMI_DRAM_DQM_3				0x000 0x468 0x000 0x0 0x0
+#define MX35_PAD_EB0__EMI_EIM_EB0_B				0x094 0x46c 0x000 0x0 0x0
+#define MX35_PAD_EB1__EMI_EIM_EB1_B				0x098 0x470 0x000 0x0 0x0
+#define MX35_PAD_OE__EMI_EIM_OE					0x09c 0x474 0x000 0x0 0x0
+#define MX35_PAD_CS0__EMI_EIM_CS0				0x0a0 0x478 0x000 0x0 0x0
+#define MX35_PAD_CS1__EMI_EIM_CS1				0x0a4 0x47c 0x000 0x0 0x0
+#define MX35_PAD_CS1__EMI_NANDF_CE3				0x0a4 0x47c 0x000 0x3 0x0
+#define MX35_PAD_CS2__EMI_EIM_CS2				0x0a8 0x480 0x000 0x0 0x0
+#define MX35_PAD_CS3__EMI_EIM_CS3				0x0ac 0x484 0x000 0x0 0x0
+#define MX35_PAD_CS4__EMI_EIM_CS4				0x0b0 0x488 0x000 0x0 0x0
+#define MX35_PAD_CS4__EMI_DTACK_B				0x0b0 0x488 0x800 0x1 0x0
+#define MX35_PAD_CS4__EMI_NANDF_CE1				0x0b0 0x488 0x000 0x3 0x0
+#define MX35_PAD_CS4__GPIO1_20					0x0b0 0x488 0x83c 0x5 0x0
+#define MX35_PAD_CS5__EMI_EIM_CS5				0x0b4 0x48c 0x000 0x0 0x0
+#define MX35_PAD_CS5__CSPI2_SS2					0x0b4 0x48c 0x7f8 0x1 0x0
+#define MX35_PAD_CS5__CSPI1_SS2					0x0b4 0x48c 0x7d8 0x2 0x1
+#define MX35_PAD_CS5__EMI_NANDF_CE2				0x0b4 0x48c 0x000 0x3 0x0
+#define MX35_PAD_CS5__GPIO1_21					0x0b4 0x48c 0x840 0x5 0x0
+#define MX35_PAD_NF_CE0__EMI_NANDF_CE0				0x0b8 0x490 0x000 0x0 0x0
+#define MX35_PAD_NF_CE0__GPIO1_22				0x0b8 0x490 0x844 0x5 0x0
+#define MX35_PAD_ECB__EMI_EIM_ECB				0x000 0x494 0x000 0x0 0x0
+#define MX35_PAD_LBA__EMI_EIM_LBA				0x0bc 0x498 0x000 0x0 0x0
+#define MX35_PAD_BCLK__EMI_EIM_BCLK				0x0c0 0x49c 0x000 0x0 0x0
+#define MX35_PAD_RW__EMI_EIM_RW					0x0c4 0x4a0 0x000 0x0 0x0
+#define MX35_PAD_RAS__EMI_DRAM_RAS				0x000 0x4a4 0x000 0x0 0x0
+#define MX35_PAD_CAS__EMI_DRAM_CAS				0x000 0x4a8 0x000 0x0 0x0
+#define MX35_PAD_SDWE__EMI_DRAM_SDWE				0x000 0x4ac 0x000 0x0 0x0
+#define MX35_PAD_SDCKE0__EMI_DRAM_SDCKE_0			0x000 0x4b0 0x000 0x0 0x0
+#define MX35_PAD_SDCKE1__EMI_DRAM_SDCKE_1			0x000 0x4b4 0x000 0x0 0x0
+#define MX35_PAD_SDCLK__EMI_DRAM_SDCLK				0x000 0x4b8 0x000 0x0 0x0
+#define MX35_PAD_SDQS0__EMI_DRAM_SDQS_0				0x000 0x4bc 0x000 0x0 0x0
+#define MX35_PAD_SDQS1__EMI_DRAM_SDQS_1				0x000 0x4c0 0x000 0x0 0x0
+#define MX35_PAD_SDQS2__EMI_DRAM_SDQS_2				0x000 0x4c4 0x000 0x0 0x0
+#define MX35_PAD_SDQS3__EMI_DRAM_SDQS_3				0x000 0x4c8 0x000 0x0 0x0
+#define MX35_PAD_NFWE_B__EMI_NANDF_WE_B				0x0c8 0x4cc 0x000 0x0 0x0
+#define MX35_PAD_NFWE_B__USB_TOP_USBH2_DATA_3			0x0c8 0x4cc 0x9d8 0x1 0x0
+#define MX35_PAD_NFWE_B__IPU_DISPB_D0_VSYNC			0x0c8 0x4cc 0x924 0x2 0x0
+#define MX35_PAD_NFWE_B__GPIO2_18				0x0c8 0x4cc 0x88c 0x5 0x0
+#define MX35_PAD_NFWE_B__ARM11P_TOP_TRACE_0			0x0c8 0x4cc 0x000 0x7 0x0
+#define MX35_PAD_NFRE_B__EMI_NANDF_RE_B				0x0cc 0x4d0 0x000 0x0 0x0
+#define MX35_PAD_NFRE_B__USB_TOP_USBH2_DIR			0x0cc 0x4d0 0x9ec 0x1 0x0
+#define MX35_PAD_NFRE_B__IPU_DISPB_BCLK				0x0cc 0x4d0 0x000 0x2 0x0
+#define MX35_PAD_NFRE_B__GPIO2_19				0x0cc 0x4d0 0x890 0x5 0x0
+#define MX35_PAD_NFRE_B__ARM11P_TOP_TRACE_1			0x0cc 0x4d0 0x000 0x7 0x0
+#define MX35_PAD_NFALE__EMI_NANDF_ALE				0x0d0 0x4d4 0x000 0x0 0x0
+#define MX35_PAD_NFALE__USB_TOP_USBH2_STP			0x0d0 0x4d4 0x000 0x1 0x0
+#define MX35_PAD_NFALE__IPU_DISPB_CS0				0x0d0 0x4d4 0x000 0x2 0x0
+#define MX35_PAD_NFALE__GPIO2_20				0x0d0 0x4d4 0x898 0x5 0x0
+#define MX35_PAD_NFALE__ARM11P_TOP_TRACE_2			0x0d0 0x4d4 0x000 0x7 0x0
+#define MX35_PAD_NFCLE__EMI_NANDF_CLE				0x0d4 0x4d8 0x000 0x0 0x0
+#define MX35_PAD_NFCLE__USB_TOP_USBH2_NXT			0x0d4 0x4d8 0x9f0 0x1 0x0
+#define MX35_PAD_NFCLE__IPU_DISPB_PAR_RS			0x0d4 0x4d8 0x000 0x2 0x0
+#define MX35_PAD_NFCLE__GPIO2_21				0x0d4 0x4d8 0x89c 0x5 0x0
+#define MX35_PAD_NFCLE__ARM11P_TOP_TRACE_3			0x0d4 0x4d8 0x000 0x7 0x0
+#define MX35_PAD_NFWP_B__EMI_NANDF_WP_B				0x0d8 0x4dc 0x000 0x0 0x0
+#define MX35_PAD_NFWP_B__USB_TOP_USBH2_DATA_7			0x0d8 0x4dc 0x9e8 0x1 0x0
+#define MX35_PAD_NFWP_B__IPU_DISPB_WR				0x0d8 0x4dc 0x000 0x2 0x0
+#define MX35_PAD_NFWP_B__GPIO2_22				0x0d8 0x4dc 0x8a0 0x5 0x0
+#define MX35_PAD_NFWP_B__ARM11P_TOP_TRCTL			0x0d8 0x4dc 0x000 0x7 0x0
+#define MX35_PAD_NFRB__EMI_NANDF_RB				0x0dc 0x4e0 0x000 0x0 0x0
+#define MX35_PAD_NFRB__IPU_DISPB_RD				0x0dc 0x4e0 0x000 0x2 0x0
+#define MX35_PAD_NFRB__GPIO2_23					0x0dc 0x4e0 0x8a4 0x5 0x0
+#define MX35_PAD_NFRB__ARM11P_TOP_TRCLK				0x0dc 0x4e0 0x000 0x7 0x0
+#define MX35_PAD_D15__EMI_EIM_D_15				0x000 0x4e4 0x000 0x0 0x0
+#define MX35_PAD_D14__EMI_EIM_D_14				0x000 0x4e8 0x000 0x0 0x0
+#define MX35_PAD_D13__EMI_EIM_D_13				0x000 0x4ec 0x000 0x0 0x0
+#define MX35_PAD_D12__EMI_EIM_D_12				0x000 0x4f0 0x000 0x0 0x0
+#define MX35_PAD_D11__EMI_EIM_D_11				0x000 0x4f4 0x000 0x0 0x0
+#define MX35_PAD_D10__EMI_EIM_D_10				0x000 0x4f8 0x000 0x0 0x0
+#define MX35_PAD_D9__EMI_EIM_D_9				0x000 0x4fc 0x000 0x0 0x0
+#define MX35_PAD_D8__EMI_EIM_D_8				0x000 0x500 0x000 0x0 0x0
+#define MX35_PAD_D7__EMI_EIM_D_7				0x000 0x504 0x000 0x0 0x0
+#define MX35_PAD_D6__EMI_EIM_D_6				0x000 0x508 0x000 0x0 0x0
+#define MX35_PAD_D5__EMI_EIM_D_5				0x000 0x50c 0x000 0x0 0x0
+#define MX35_PAD_D4__EMI_EIM_D_4				0x000 0x510 0x000 0x0 0x0
+#define MX35_PAD_D3__EMI_EIM_D_3				0x000 0x514 0x000 0x0 0x0
+#define MX35_PAD_D2__EMI_EIM_D_2				0x000 0x518 0x000 0x0 0x0
+#define MX35_PAD_D1__EMI_EIM_D_1				0x000 0x51c 0x000 0x0 0x0
+#define MX35_PAD_D0__EMI_EIM_D_0				0x000 0x520 0x000 0x0 0x0
+#define MX35_PAD_CSI_D8__IPU_CSI_D_8				0x0e0 0x524 0x000 0x0 0x0
+#define MX35_PAD_CSI_D8__KPP_COL_0				0x0e0 0x524 0x950 0x1 0x0
+#define MX35_PAD_CSI_D8__GPIO1_20				0x0e0 0x524 0x83c 0x5 0x1
+#define MX35_PAD_CSI_D8__ARM11P_TOP_EVNTBUS_13			0x0e0 0x524 0x000 0x7 0x0
+#define MX35_PAD_CSI_D9__IPU_CSI_D_9				0x0e4 0x528 0x000 0x0 0x0
+#define MX35_PAD_CSI_D9__KPP_COL_1				0x0e4 0x528 0x954 0x1 0x0
+#define MX35_PAD_CSI_D9__GPIO1_21				0x0e4 0x528 0x840 0x5 0x1
+#define MX35_PAD_CSI_D9__ARM11P_TOP_EVNTBUS_14			0x0e4 0x528 0x000 0x7 0x0
+#define MX35_PAD_CSI_D10__IPU_CSI_D_10				0x0e8 0x52c 0x000 0x0 0x0
+#define MX35_PAD_CSI_D10__KPP_COL_2				0x0e8 0x52c 0x958 0x1 0x0
+#define MX35_PAD_CSI_D10__GPIO1_22				0x0e8 0x52c 0x844 0x5 0x1
+#define MX35_PAD_CSI_D10__ARM11P_TOP_EVNTBUS_15			0x0e8 0x52c 0x000 0x7 0x0
+#define MX35_PAD_CSI_D11__IPU_CSI_D_11				0x0ec 0x530 0x000 0x0 0x0
+#define MX35_PAD_CSI_D11__KPP_COL_3				0x0ec 0x530 0x95c 0x1 0x0
+#define MX35_PAD_CSI_D11__GPIO1_23				0x0ec 0x530 0x000 0x5 0x0
+#define MX35_PAD_CSI_D12__IPU_CSI_D_12				0x0f0 0x534 0x000 0x0 0x0
+#define MX35_PAD_CSI_D12__KPP_ROW_0				0x0f0 0x534 0x970 0x1 0x0
+#define MX35_PAD_CSI_D12__GPIO1_24				0x0f0 0x534 0x000 0x5 0x0
+#define MX35_PAD_CSI_D13__IPU_CSI_D_13				0x0f4 0x538 0x000 0x0 0x0
+#define MX35_PAD_CSI_D13__KPP_ROW_1				0x0f4 0x538 0x974 0x1 0x0
+#define MX35_PAD_CSI_D13__GPIO1_25				0x0f4 0x538 0x000 0x5 0x0
+#define MX35_PAD_CSI_D14__IPU_CSI_D_14				0x0f8 0x53c 0x000 0x0 0x0
+#define MX35_PAD_CSI_D14__KPP_ROW_2				0x0f8 0x53c 0x978 0x1 0x0
+#define MX35_PAD_CSI_D14__GPIO1_26				0x0f8 0x53c 0x000 0x5 0x0
+#define MX35_PAD_CSI_D15__IPU_CSI_D_15				0x0fc 0x540 0x97c 0x0 0x0
+#define MX35_PAD_CSI_D15__KPP_ROW_3				0x0fc 0x540 0x000 0x1 0x0
+#define MX35_PAD_CSI_D15__GPIO1_27				0x0fc 0x540 0x000 0x5 0x0
+#define MX35_PAD_CSI_MCLK__IPU_CSI_MCLK				0x100 0x544 0x000 0x0 0x0
+#define MX35_PAD_CSI_MCLK__GPIO1_28				0x100 0x544 0x000 0x5 0x0
+#define MX35_PAD_CSI_VSYNC__IPU_CSI_VSYNC			0x104 0x548 0x000 0x0 0x0
+#define MX35_PAD_CSI_VSYNC__GPIO1_29				0x104 0x548 0x000 0x5 0x0
+#define MX35_PAD_CSI_HSYNC__IPU_CSI_HSYNC			0x108 0x54c 0x000 0x0 0x0
+#define MX35_PAD_CSI_HSYNC__GPIO1_30				0x108 0x54c 0x000 0x5 0x0
+#define MX35_PAD_CSI_PIXCLK__IPU_CSI_PIXCLK			0x10c 0x550 0x000 0x0 0x0
+#define MX35_PAD_CSI_PIXCLK__GPIO1_31				0x10c 0x550 0x000 0x5 0x0
+#define MX35_PAD_I2C1_CLK__I2C1_SCL				0x110 0x554 0x000 0x0 0x0
+#define MX35_PAD_I2C1_CLK__GPIO2_24				0x110 0x554 0x8a8 0x5 0x0
+#define MX35_PAD_I2C1_CLK__CCM_USB_BYP_CLK			0x110 0x554 0x000 0x6 0x0
+#define MX35_PAD_I2C1_DAT__I2C1_SDA				0x114 0x558 0x000 0x0 0x0
+#define MX35_PAD_I2C1_DAT__GPIO2_25				0x114 0x558 0x8ac 0x5 0x0
+#define MX35_PAD_I2C2_CLK__I2C2_SCL				0x118 0x55c 0x000 0x0 0x0
+#define MX35_PAD_I2C2_CLK__CAN1_TXCAN				0x118 0x55c 0x000 0x1 0x0
+#define MX35_PAD_I2C2_CLK__USB_TOP_USBH2_PWR			0x118 0x55c 0x000 0x2 0x0
+#define MX35_PAD_I2C2_CLK__GPIO2_26				0x118 0x55c 0x8b0 0x5 0x0
+#define MX35_PAD_I2C2_CLK__SDMA_DEBUG_BUS_DEVICE_2		0x118 0x55c 0x000 0x6 0x0
+#define MX35_PAD_I2C2_DAT__I2C2_SDA				0x11c 0x560 0x000 0x0 0x0
+#define MX35_PAD_I2C2_DAT__CAN1_RXCAN				0x11c 0x560 0x7c8 0x1 0x0
+#define MX35_PAD_I2C2_DAT__USB_TOP_USBH2_OC			0x11c 0x560 0x9f4 0x2 0x0
+#define MX35_PAD_I2C2_DAT__GPIO2_27				0x11c 0x560 0x8b4 0x5 0x0
+#define MX35_PAD_I2C2_DAT__SDMA_DEBUG_BUS_DEVICE_3		0x11c 0x560 0x000 0x6 0x0
+#define MX35_PAD_STXD4__AUDMUX_AUD4_TXD				0x120 0x564 0x000 0x0 0x0
+#define MX35_PAD_STXD4__GPIO2_28				0x120 0x564 0x8b8 0x5 0x0
+#define MX35_PAD_STXD4__ARM11P_TOP_ARM_COREASID0		0x120 0x564 0x000 0x7 0x0
+#define MX35_PAD_SRXD4__AUDMUX_AUD4_RXD				0x124 0x568 0x000 0x0 0x0
+#define MX35_PAD_SRXD4__GPIO2_29				0x124 0x568 0x8bc 0x5 0x0
+#define MX35_PAD_SRXD4__ARM11P_TOP_ARM_COREASID1		0x124 0x568 0x000 0x7 0x0
+#define MX35_PAD_SCK4__AUDMUX_AUD4_TXC				0x128 0x56c 0x000 0x0 0x0
+#define MX35_PAD_SCK4__GPIO2_30					0x128 0x56c 0x8c4 0x5 0x0
+#define MX35_PAD_SCK4__ARM11P_TOP_ARM_COREASID2			0x128 0x56c 0x000 0x7 0x0
+#define MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS			0x12c 0x570 0x000 0x0 0x0
+#define MX35_PAD_STXFS4__GPIO2_31				0x12c 0x570 0x8c8 0x5 0x0
+#define MX35_PAD_STXFS4__ARM11P_TOP_ARM_COREASID3		0x12c 0x570 0x000 0x7 0x0
+#define MX35_PAD_STXD5__AUDMUX_AUD5_TXD				0x130 0x574 0x000 0x0 0x0
+#define MX35_PAD_STXD5__SPDIF_SPDIF_OUT1			0x130 0x574 0x000 0x1 0x0
+#define MX35_PAD_STXD5__CSPI2_MOSI				0x130 0x574 0x7ec 0x2 0x0
+#define MX35_PAD_STXD5__GPIO1_0					0x130 0x574 0x82c 0x5 0x1
+#define MX35_PAD_STXD5__ARM11P_TOP_ARM_COREASID4		0x130 0x574 0x000 0x7 0x0
+#define MX35_PAD_SRXD5__AUDMUX_AUD5_RXD				0x134 0x578 0x000 0x0 0x0
+#define MX35_PAD_SRXD5__SPDIF_SPDIF_IN1				0x134 0x578 0x998 0x1 0x0
+#define MX35_PAD_SRXD5__CSPI2_MISO				0x134 0x578 0x7e8 0x2 0x0
+#define MX35_PAD_SRXD5__GPIO1_1					0x134 0x578 0x838 0x5 0x1
+#define MX35_PAD_SRXD5__ARM11P_TOP_ARM_COREASID5		0x134 0x578 0x000 0x7 0x0
+#define MX35_PAD_SCK5__AUDMUX_AUD5_TXC				0x138 0x57c 0x000 0x0 0x0
+#define MX35_PAD_SCK5__SPDIF_SPDIF_EXTCLK			0x138 0x57c 0x994 0x1 0x0
+#define MX35_PAD_SCK5__CSPI2_SCLK				0x138 0x57c 0x7e0 0x2 0x0
+#define MX35_PAD_SCK5__GPIO1_2					0x138 0x57c 0x848 0x5 0x0
+#define MX35_PAD_SCK5__ARM11P_TOP_ARM_COREASID6			0x138 0x57c 0x000 0x7 0x0
+#define MX35_PAD_STXFS5__AUDMUX_AUD5_TXFS			0x13c 0x580 0x000 0x0 0x0
+#define MX35_PAD_STXFS5__CSPI2_RDY				0x13c 0x580 0x7e4 0x2 0x0
+#define MX35_PAD_STXFS5__GPIO1_3				0x13c 0x580 0x84c 0x5 0x0
+#define MX35_PAD_STXFS5__ARM11P_TOP_ARM_COREASID7		0x13c 0x580 0x000 0x7 0x0
+#define MX35_PAD_SCKR__ESAI_SCKR				0x140 0x584 0x000 0x0 0x0
+#define MX35_PAD_SCKR__GPIO1_4					0x140 0x584 0x850 0x5 0x1
+#define MX35_PAD_SCKR__ARM11P_TOP_EVNTBUS_10			0x140 0x584 0x000 0x7 0x0
+#define MX35_PAD_FSR__ESAI_FSR					0x144 0x588 0x000 0x0 0x0
+#define MX35_PAD_FSR__GPIO1_5					0x144 0x588 0x854 0x5 0x1
+#define MX35_PAD_FSR__ARM11P_TOP_EVNTBUS_11			0x144 0x588 0x000 0x7 0x0
+#define MX35_PAD_HCKR__ESAI_HCKR				0x148 0x58c 0x000 0x0 0x0
+#define MX35_PAD_HCKR__AUDMUX_AUD5_RXFS				0x148 0x58c 0x000 0x1 0x0
+#define MX35_PAD_HCKR__CSPI2_SS0				0x148 0x58c 0x7f0 0x2 0x0
+#define MX35_PAD_HCKR__IPU_FLASH_STROBE				0x148 0x58c 0x000 0x3 0x0
+#define MX35_PAD_HCKR__GPIO1_6					0x148 0x58c 0x858 0x5 0x1
+#define MX35_PAD_HCKR__ARM11P_TOP_EVNTBUS_12			0x148 0x58c 0x000 0x7 0x0
+#define MX35_PAD_SCKT__ESAI_SCKT				0x14c 0x590 0x000 0x0 0x0
+#define MX35_PAD_SCKT__GPIO1_7					0x14c 0x590 0x85c 0x5 0x1
+#define MX35_PAD_SCKT__IPU_CSI_D_0				0x14c 0x590 0x930 0x6 0x0
+#define MX35_PAD_SCKT__KPP_ROW_2				0x14c 0x590 0x978 0x7 0x1
+#define MX35_PAD_FST__ESAI_FST					0x150 0x594 0x000 0x0 0x0
+#define MX35_PAD_FST__GPIO1_8					0x150 0x594 0x860 0x5 0x1
+#define MX35_PAD_FST__IPU_CSI_D_1				0x150 0x594 0x934 0x6 0x0
+#define MX35_PAD_FST__KPP_ROW_3					0x150 0x594 0x97c 0x7 0x1
+#define MX35_PAD_HCKT__ESAI_HCKT				0x154 0x598 0x000 0x0 0x0
+#define MX35_PAD_HCKT__AUDMUX_AUD5_RXC				0x154 0x598 0x7a8 0x1 0x0
+#define MX35_PAD_HCKT__GPIO1_9					0x154 0x598 0x864 0x5 0x0
+#define MX35_PAD_HCKT__IPU_CSI_D_2				0x154 0x598 0x938 0x6 0x0
+#define MX35_PAD_HCKT__KPP_COL_3				0x154 0x598 0x95c 0x7 0x1
+#define MX35_PAD_TX5_RX0__ESAI_TX5_RX0				0x158 0x59c 0x000 0x0 0x0
+#define MX35_PAD_TX5_RX0__AUDMUX_AUD4_RXC			0x158 0x59c 0x000 0x1 0x0
+#define MX35_PAD_TX5_RX0__CSPI2_SS2				0x158 0x59c 0x7f8 0x2 0x1
+#define MX35_PAD_TX5_RX0__CAN2_TXCAN				0x158 0x59c 0x000 0x3 0x0
+#define MX35_PAD_TX5_RX0__UART2_DTR				0x158 0x59c 0x000 0x4 0x0
+#define MX35_PAD_TX5_RX0__GPIO1_10				0x158 0x59c 0x830 0x5 0x0
+#define MX35_PAD_TX5_RX0__EMI_M3IF_CHOSEN_MASTER_0		0x158 0x59c 0x000 0x7 0x0
+#define MX35_PAD_TX4_RX1__ESAI_TX4_RX1				0x15c 0x5a0 0x000 0x0 0x0
+#define MX35_PAD_TX4_RX1__AUDMUX_AUD4_RXFS			0x15c 0x5a0 0x000 0x1 0x0
+#define MX35_PAD_TX4_RX1__CSPI2_SS3				0x15c 0x5a0 0x7fc 0x2 0x0
+#define MX35_PAD_TX4_RX1__CAN2_RXCAN				0x15c 0x5a0 0x7cc 0x3 0x0
+#define MX35_PAD_TX4_RX1__UART2_DSR				0x15c 0x5a0 0x000 0x4 0x0
+#define MX35_PAD_TX4_RX1__GPIO1_11				0x15c 0x5a0 0x834 0x5 0x0
+#define MX35_PAD_TX4_RX1__IPU_CSI_D_3				0x15c 0x5a0 0x93c 0x6 0x0
+#define MX35_PAD_TX4_RX1__KPP_ROW_0				0x15c 0x5a0 0x970 0x7 0x1
+#define MX35_PAD_TX3_RX2__ESAI_TX3_RX2				0x160 0x5a4 0x000 0x0 0x0
+#define MX35_PAD_TX3_RX2__I2C3_SCL				0x160 0x5a4 0x91c 0x1 0x0
+#define MX35_PAD_TX3_RX2__EMI_NANDF_CE1				0x160 0x5a4 0x000 0x3 0x0
+#define MX35_PAD_TX3_RX2__GPIO1_12				0x160 0x5a4 0x000 0x5 0x0
+#define MX35_PAD_TX3_RX2__IPU_CSI_D_4				0x160 0x5a4 0x940 0x6 0x0
+#define MX35_PAD_TX3_RX2__KPP_ROW_1				0x160 0x5a4 0x974 0x7 0x1
+#define MX35_PAD_TX2_RX3__ESAI_TX2_RX3				0x164 0x5a8 0x000 0x0 0x0
+#define MX35_PAD_TX2_RX3__I2C3_SDA				0x164 0x5a8 0x920 0x1 0x0
+#define MX35_PAD_TX2_RX3__EMI_NANDF_CE2				0x164 0x5a8 0x000 0x3 0x0
+#define MX35_PAD_TX2_RX3__GPIO1_13				0x164 0x5a8 0x000 0x5 0x0
+#define MX35_PAD_TX2_RX3__IPU_CSI_D_5				0x164 0x5a8 0x944 0x6 0x0
+#define MX35_PAD_TX2_RX3__KPP_COL_0				0x164 0x5a8 0x950 0x7 0x1
+#define MX35_PAD_TX1__ESAI_TX1					0x168 0x5ac 0x000 0x0 0x0
+#define MX35_PAD_TX1__CCM_PMIC_RDY				0x168 0x5ac 0x7d4 0x1 0x1
+#define MX35_PAD_TX1__CSPI1_SS2					0x168 0x5ac 0x7d8 0x2 0x2
+#define MX35_PAD_TX1__EMI_NANDF_CE3				0x168 0x5ac 0x000 0x3 0x0
+#define MX35_PAD_TX1__UART2_RI					0x168 0x5ac 0x000 0x4 0x0
+#define MX35_PAD_TX1__GPIO1_14					0x168 0x5ac 0x000 0x5 0x0
+#define MX35_PAD_TX1__IPU_CSI_D_6				0x168 0x5ac 0x948 0x6 0x0
+#define MX35_PAD_TX1__KPP_COL_1					0x168 0x5ac 0x954 0x7 0x1
+#define MX35_PAD_TX0__ESAI_TX0					0x16c 0x5b0 0x000 0x0 0x0
+#define MX35_PAD_TX0__SPDIF_SPDIF_EXTCLK			0x16c 0x5b0 0x994 0x1 0x1
+#define MX35_PAD_TX0__CSPI1_SS3					0x16c 0x5b0 0x7dc 0x2 0x0
+#define MX35_PAD_TX0__EMI_DTACK_B				0x16c 0x5b0 0x800 0x3 0x1
+#define MX35_PAD_TX0__UART2_DCD					0x16c 0x5b0 0x000 0x4 0x0
+#define MX35_PAD_TX0__GPIO1_15					0x16c 0x5b0 0x000 0x5 0x0
+#define MX35_PAD_TX0__IPU_CSI_D_7				0x16c 0x5b0 0x94c 0x6 0x0
+#define MX35_PAD_TX0__KPP_COL_2					0x16c 0x5b0 0x958 0x7 0x1
+#define MX35_PAD_CSPI1_MOSI__CSPI1_MOSI				0x170 0x5b4 0x000 0x0 0x0
+#define MX35_PAD_CSPI1_MOSI__GPIO1_16				0x170 0x5b4 0x000 0x5 0x0
+#define MX35_PAD_CSPI1_MOSI__ECT_CTI_TRIG_OUT1_2		0x170 0x5b4 0x000 0x7 0x0
+#define MX35_PAD_CSPI1_MISO__CSPI1_MISO				0x174 0x5b8 0x000 0x0 0x0
+#define MX35_PAD_CSPI1_MISO__GPIO1_17				0x174 0x5b8 0x000 0x5 0x0
+#define MX35_PAD_CSPI1_MISO__ECT_CTI_TRIG_OUT1_3		0x174 0x5b8 0x000 0x7 0x0
+#define MX35_PAD_CSPI1_SS0__CSPI1_SS0				0x178 0x5bc 0x000 0x0 0x0
+#define MX35_PAD_CSPI1_SS0__OWIRE_LINE				0x178 0x5bc 0x990 0x1 0x1
+#define MX35_PAD_CSPI1_SS0__CSPI2_SS3				0x178 0x5bc 0x7fc 0x2 0x1
+#define MX35_PAD_CSPI1_SS0__GPIO1_18				0x178 0x5bc 0x000 0x5 0x0
+#define MX35_PAD_CSPI1_SS0__ECT_CTI_TRIG_OUT1_4			0x178 0x5bc 0x000 0x7 0x0
+#define MX35_PAD_CSPI1_SS1__CSPI1_SS1				0x17c 0x5c0 0x000 0x0 0x0
+#define MX35_PAD_CSPI1_SS1__PWM_PWMO				0x17c 0x5c0 0x000 0x1 0x0
+#define MX35_PAD_CSPI1_SS1__CCM_CLK32K				0x17c 0x5c0 0x7d0 0x2 0x1
+#define MX35_PAD_CSPI1_SS1__GPIO1_19				0x17c 0x5c0 0x000 0x5 0x0
+#define MX35_PAD_CSPI1_SS1__IPU_DIAGB_29			0x17c 0x5c0 0x000 0x6 0x0
+#define MX35_PAD_CSPI1_SS1__ECT_CTI_TRIG_OUT1_5			0x17c 0x5c0 0x000 0x7 0x0
+#define MX35_PAD_CSPI1_SCLK__CSPI1_SCLK				0x180 0x5c4 0x000 0x0 0x0
+#define MX35_PAD_CSPI1_SCLK__GPIO3_4				0x180 0x5c4 0x904 0x5 0x0
+#define MX35_PAD_CSPI1_SCLK__IPU_DIAGB_30			0x180 0x5c4 0x000 0x6 0x0
+#define MX35_PAD_CSPI1_SCLK__EMI_M3IF_CHOSEN_MASTER_1		0x180 0x5c4 0x000 0x7 0x0
+#define MX35_PAD_CSPI1_SPI_RDY__CSPI1_RDY			0x184 0x5c8 0x000 0x0 0x0
+#define MX35_PAD_CSPI1_SPI_RDY__GPIO3_5				0x184 0x5c8 0x908 0x5 0x0
+#define MX35_PAD_CSPI1_SPI_RDY__IPU_DIAGB_31			0x184 0x5c8 0x000 0x6 0x0
+#define MX35_PAD_CSPI1_SPI_RDY__EMI_M3IF_CHOSEN_MASTER_2	0x184 0x5c8 0x000 0x7 0x0
+#define MX35_PAD_RXD1__UART1_RXD_MUX				0x188 0x5cc 0x000 0x0 0x0
+#define MX35_PAD_RXD1__CSPI2_MOSI				0x188 0x5cc 0x7ec 0x1 0x1
+#define MX35_PAD_RXD1__KPP_COL_4				0x188 0x5cc 0x960 0x4 0x0
+#define MX35_PAD_RXD1__GPIO3_6					0x188 0x5cc 0x90c 0x5 0x0
+#define MX35_PAD_RXD1__ARM11P_TOP_EVNTBUS_16			0x188 0x5cc 0x000 0x7 0x0
+#define MX35_PAD_TXD1__UART1_TXD_MUX				0x18c 0x5d0 0x000 0x0 0x0
+#define MX35_PAD_TXD1__CSPI2_MISO				0x18c 0x5d0 0x7e8 0x1 0x1
+#define MX35_PAD_TXD1__KPP_COL_5				0x18c 0x5d0 0x964 0x4 0x0
+#define MX35_PAD_TXD1__GPIO3_7					0x18c 0x5d0 0x910 0x5 0x0
+#define MX35_PAD_TXD1__ARM11P_TOP_EVNTBUS_17			0x18c 0x5d0 0x000 0x7 0x0
+#define MX35_PAD_RTS1__UART1_RTS				0x190 0x5d4 0x000 0x0 0x0
+#define MX35_PAD_RTS1__CSPI2_SCLK				0x190 0x5d4 0x7e0 0x1 0x1
+#define MX35_PAD_RTS1__I2C3_SCL					0x190 0x5d4 0x91c 0x2 0x1
+#define MX35_PAD_RTS1__IPU_CSI_D_0				0x190 0x5d4 0x930 0x3 0x1
+#define MX35_PAD_RTS1__KPP_COL_6				0x190 0x5d4 0x968 0x4 0x0
+#define MX35_PAD_RTS1__GPIO3_8					0x190 0x5d4 0x914 0x5 0x0
+#define MX35_PAD_RTS1__EMI_NANDF_CE1				0x190 0x5d4 0x000 0x6 0x0
+#define MX35_PAD_RTS1__ARM11P_TOP_EVNTBUS_18			0x190 0x5d4 0x000 0x7 0x0
+#define MX35_PAD_CTS1__UART1_CTS				0x194 0x5d8 0x000 0x0 0x0
+#define MX35_PAD_CTS1__CSPI2_RDY				0x194 0x5d8 0x7e4 0x1 0x1
+#define MX35_PAD_CTS1__I2C3_SDA					0x194 0x5d8 0x920 0x2 0x1
+#define MX35_PAD_CTS1__IPU_CSI_D_1				0x194 0x5d8 0x934 0x3 0x1
+#define MX35_PAD_CTS1__KPP_COL_7				0x194 0x5d8 0x96c 0x4 0x0
+#define MX35_PAD_CTS1__GPIO3_9					0x194 0x5d8 0x918 0x5 0x0
+#define MX35_PAD_CTS1__EMI_NANDF_CE2				0x194 0x5d8 0x000 0x6 0x0
+#define MX35_PAD_CTS1__ARM11P_TOP_EVNTBUS_19			0x194 0x5d8 0x000 0x7 0x0
+#define MX35_PAD_RXD2__UART2_RXD_MUX				0x198 0x5dc 0x000 0x0 0x0
+#define MX35_PAD_RXD2__KPP_ROW_4				0x198 0x5dc 0x980 0x4 0x0
+#define MX35_PAD_RXD2__GPIO3_10					0x198 0x5dc 0x8ec 0x5 0x0
+#define MX35_PAD_TXD2__UART2_TXD_MUX				0x19c 0x5e0 0x000 0x0 0x0
+#define MX35_PAD_TXD2__SPDIF_SPDIF_EXTCLK			0x19c 0x5e0 0x994 0x1 0x2
+#define MX35_PAD_TXD2__KPP_ROW_5				0x19c 0x5e0 0x984 0x4 0x0
+#define MX35_PAD_TXD2__GPIO3_11					0x19c 0x5e0 0x8f0 0x5 0x0
+#define MX35_PAD_RTS2__UART2_RTS				0x1a0 0x5e4 0x000 0x0 0x0
+#define MX35_PAD_RTS2__SPDIF_SPDIF_IN1				0x1a0 0x5e4 0x998 0x1 0x1
+#define MX35_PAD_RTS2__CAN2_RXCAN				0x1a0 0x5e4 0x7cc 0x2 0x1
+#define MX35_PAD_RTS2__IPU_CSI_D_2				0x1a0 0x5e4 0x938 0x3 0x1
+#define MX35_PAD_RTS2__KPP_ROW_6				0x1a0 0x5e4 0x988 0x4 0x0
+#define MX35_PAD_RTS2__GPIO3_12					0x1a0 0x5e4 0x8f4 0x5 0x0
+#define MX35_PAD_RTS2__AUDMUX_AUD5_RXC				0x1a0 0x5e4 0x000 0x6 0x0
+#define MX35_PAD_RTS2__UART3_RXD_MUX				0x1a0 0x5e4 0x9a0 0x7 0x0
+#define MX35_PAD_CTS2__UART2_CTS				0x1a4 0x5e8 0x000 0x0 0x0
+#define MX35_PAD_CTS2__SPDIF_SPDIF_OUT1				0x1a4 0x5e8 0x000 0x1 0x0
+#define MX35_PAD_CTS2__CAN2_TXCAN				0x1a4 0x5e8 0x000 0x2 0x0
+#define MX35_PAD_CTS2__IPU_CSI_D_3				0x1a4 0x5e8 0x93c 0x3 0x1
+#define MX35_PAD_CTS2__KPP_ROW_7				0x1a4 0x5e8 0x98c 0x4 0x0
+#define MX35_PAD_CTS2__GPIO3_13					0x1a4 0x5e8 0x8f8 0x5 0x0
+#define MX35_PAD_CTS2__AUDMUX_AUD5_RXFS				0x1a4 0x5e8 0x000 0x6 0x0
+#define MX35_PAD_CTS2__UART3_TXD_MUX				0x1a4 0x5e8 0x000 0x7 0x0
+#define MX35_PAD_RTCK__ARM11P_TOP_RTCK				0x000 0x5ec 0x000 0x0 0x0
+#define MX35_PAD_TCK__SJC_TCK					0x000 0x5f0 0x000 0x0 0x0
+#define MX35_PAD_TMS__SJC_TMS					0x000 0x5f4 0x000 0x0 0x0
+#define MX35_PAD_TDI__SJC_TDI					0x000 0x5f8 0x000 0x0 0x0
+#define MX35_PAD_TDO__SJC_TDO					0x000 0x5fc 0x000 0x0 0x0
+#define MX35_PAD_TRSTB__SJC_TRSTB				0x000 0x600 0x000 0x0 0x0
+#define MX35_PAD_DE_B__SJC_DE_B					0x000 0x604 0x000 0x0 0x0
+#define MX35_PAD_SJC_MOD__SJC_MOD				0x000 0x608 0x000 0x0 0x0
+#define MX35_PAD_USBOTG_PWR__USB_TOP_USBOTG_PWR			0x1a8 0x60c 0x000 0x0 0x0
+#define MX35_PAD_USBOTG_PWR__USB_TOP_USBH2_PWR			0x1a8 0x60c 0x000 0x1 0x0
+#define MX35_PAD_USBOTG_PWR__GPIO3_14				0x1a8 0x60c 0x8fc 0x5 0x0
+#define MX35_PAD_USBOTG_OC__USB_TOP_USBOTG_OC			0x1ac 0x610 0x000 0x0 0x0
+#define MX35_PAD_USBOTG_OC__USB_TOP_USBH2_OC			0x1ac 0x610 0x9f4 0x1 0x1
+#define MX35_PAD_USBOTG_OC__GPIO3_15				0x1ac 0x610 0x900 0x5 0x0
+#define MX35_PAD_LD0__IPU_DISPB_DAT_0				0x1b0 0x614 0x000 0x0 0x0
+#define MX35_PAD_LD0__GPIO2_0					0x1b0 0x614 0x868 0x5 0x1
+#define MX35_PAD_LD0__SDMA_SDMA_DEBUG_PC_0			0x1b0 0x614 0x000 0x6 0x0
+#define MX35_PAD_LD1__IPU_DISPB_DAT_1				0x1b4 0x618 0x000 0x0 0x0
+#define MX35_PAD_LD1__GPIO2_1					0x1b4 0x618 0x894 0x5 0x0
+#define MX35_PAD_LD1__SDMA_SDMA_DEBUG_PC_1			0x1b4 0x618 0x000 0x6 0x0
+#define MX35_PAD_LD2__IPU_DISPB_DAT_2				0x1b8 0x61c 0x000 0x0 0x0
+#define MX35_PAD_LD2__GPIO2_2					0x1b8 0x61c 0x8c0 0x5 0x0
+#define MX35_PAD_LD2__SDMA_SDMA_DEBUG_PC_2			0x1b8 0x61c 0x000 0x6 0x0
+#define MX35_PAD_LD3__IPU_DISPB_DAT_3				0x1bc 0x620 0x000 0x0 0x0
+#define MX35_PAD_LD3__GPIO2_3					0x1bc 0x620 0x8cc 0x5 0x0
+#define MX35_PAD_LD3__SDMA_SDMA_DEBUG_PC_3			0x1bc 0x620 0x000 0x6 0x0
+#define MX35_PAD_LD4__IPU_DISPB_DAT_4				0x1c0 0x624 0x000 0x0 0x0
+#define MX35_PAD_LD4__GPIO2_4					0x1c0 0x624 0x8d0 0x5 0x0
+#define MX35_PAD_LD4__SDMA_SDMA_DEBUG_PC_4			0x1c0 0x624 0x000 0x6 0x0
+#define MX35_PAD_LD5__IPU_DISPB_DAT_5				0x1c4 0x628 0x000 0x0 0x0
+#define MX35_PAD_LD5__GPIO2_5					0x1c4 0x628 0x8d4 0x5 0x0
+#define MX35_PAD_LD5__SDMA_SDMA_DEBUG_PC_5			0x1c4 0x628 0x000 0x6 0x0
+#define MX35_PAD_LD6__IPU_DISPB_DAT_6				0x1c8 0x62c 0x000 0x0 0x0
+#define MX35_PAD_LD6__GPIO2_6					0x1c8 0x62c 0x8d8 0x5 0x0
+#define MX35_PAD_LD6__SDMA_SDMA_DEBUG_PC_6			0x1c8 0x62c 0x000 0x6 0x0
+#define MX35_PAD_LD7__IPU_DISPB_DAT_7				0x1cc 0x630 0x000 0x0 0x0
+#define MX35_PAD_LD7__GPIO2_7					0x1cc 0x630 0x8dc 0x5 0x0
+#define MX35_PAD_LD7__SDMA_SDMA_DEBUG_PC_7			0x1cc 0x630 0x000 0x6 0x0
+#define MX35_PAD_LD8__IPU_DISPB_DAT_8				0x1d0 0x634 0x000 0x0 0x0
+#define MX35_PAD_LD8__GPIO2_8					0x1d0 0x634 0x8e0 0x5 0x0
+#define MX35_PAD_LD8__SDMA_SDMA_DEBUG_PC_8			0x1d0 0x634 0x000 0x6 0x0
+#define MX35_PAD_LD9__IPU_DISPB_DAT_9				0x1d4 0x638 0x000 0x0 0x0
+#define MX35_PAD_LD9__GPIO2_9					0x1d4 0x638 0x8e4 0x5 0x0
+#define MX35_PAD_LD9__SDMA_SDMA_DEBUG_PC_9			0x1d4 0x638 0x000 0x6 0x0
+#define MX35_PAD_LD10__IPU_DISPB_DAT_10				0x1d8 0x63c 0x000 0x0 0x0
+#define MX35_PAD_LD10__GPIO2_10					0x1d8 0x63c 0x86c 0x5 0x0
+#define MX35_PAD_LD10__SDMA_SDMA_DEBUG_PC_10			0x1d8 0x63c 0x000 0x6 0x0
+#define MX35_PAD_LD11__IPU_DISPB_DAT_11				0x1dc 0x640 0x000 0x0 0x0
+#define MX35_PAD_LD11__GPIO2_11					0x1dc 0x640 0x870 0x5 0x0
+#define MX35_PAD_LD11__SDMA_SDMA_DEBUG_PC_11			0x1dc 0x640 0x000 0x6 0x0
+#define MX35_PAD_LD11__ARM11P_TOP_TRACE_4			0x1dc 0x640 0x000 0x7 0x0
+#define MX35_PAD_LD12__IPU_DISPB_DAT_12				0x1e0 0x644 0x000 0x0 0x0
+#define MX35_PAD_LD12__GPIO2_12					0x1e0 0x644 0x874 0x5 0x0
+#define MX35_PAD_LD12__SDMA_SDMA_DEBUG_PC_12			0x1e0 0x644 0x000 0x6 0x0
+#define MX35_PAD_LD12__ARM11P_TOP_TRACE_5			0x1e0 0x644 0x000 0x7 0x0
+#define MX35_PAD_LD13__IPU_DISPB_DAT_13				0x1e4 0x648 0x000 0x0 0x0
+#define MX35_PAD_LD13__GPIO2_13					0x1e4 0x648 0x878 0x5 0x0
+#define MX35_PAD_LD13__SDMA_SDMA_DEBUG_PC_13			0x1e4 0x648 0x000 0x6 0x0
+#define MX35_PAD_LD13__ARM11P_TOP_TRACE_6			0x1e4 0x648 0x000 0x7 0x0
+#define MX35_PAD_LD14__IPU_DISPB_DAT_14				0x1e8 0x64c 0x000 0x0 0x0
+#define MX35_PAD_LD14__GPIO2_14					0x1e8 0x64c 0x87c 0x5 0x0
+#define MX35_PAD_LD14__SDMA_SDMA_DEBUG_EVENT_CHANNEL_0		0x1e8 0x64c 0x000 0x6 0x0
+#define MX35_PAD_LD14__ARM11P_TOP_TRACE_7			0x1e8 0x64c 0x000 0x7 0x0
+#define MX35_PAD_LD15__IPU_DISPB_DAT_15				0x1ec 0x650 0x000 0x0 0x0
+#define MX35_PAD_LD15__GPIO2_15					0x1ec 0x650 0x880 0x5 0x0
+#define MX35_PAD_LD15__SDMA_SDMA_DEBUG_EVENT_CHANNEL_1		0x1ec 0x650 0x000 0x6 0x0
+#define MX35_PAD_LD15__ARM11P_TOP_TRACE_8			0x1ec 0x650 0x000 0x7 0x0
+#define MX35_PAD_LD16__IPU_DISPB_DAT_16				0x1f0 0x654 0x000 0x0 0x0
+#define MX35_PAD_LD16__IPU_DISPB_D12_VSYNC			0x1f0 0x654 0x928 0x2 0x0
+#define MX35_PAD_LD16__GPIO2_16					0x1f0 0x654 0x884 0x5 0x0
+#define MX35_PAD_LD16__SDMA_SDMA_DEBUG_EVENT_CHANNEL_2		0x1f0 0x654 0x000 0x6 0x0
+#define MX35_PAD_LD16__ARM11P_TOP_TRACE_9			0x1f0 0x654 0x000 0x7 0x0
+#define MX35_PAD_LD17__IPU_DISPB_DAT_17				0x1f4 0x658 0x000 0x0 0x0
+#define MX35_PAD_LD17__IPU_DISPB_CS2				0x1f4 0x658 0x000 0x2 0x0
+#define MX35_PAD_LD17__GPIO2_17					0x1f4 0x658 0x888 0x5 0x0
+#define MX35_PAD_LD17__SDMA_SDMA_DEBUG_EVENT_CHANNEL_3		0x1f4 0x658 0x000 0x6 0x0
+#define MX35_PAD_LD17__ARM11P_TOP_TRACE_10			0x1f4 0x658 0x000 0x7 0x0
+#define MX35_PAD_LD18__IPU_DISPB_DAT_18				0x1f8 0x65c 0x000 0x0 0x0
+#define MX35_PAD_LD18__IPU_DISPB_D0_VSYNC			0x1f8 0x65c 0x924 0x1 0x1
+#define MX35_PAD_LD18__IPU_DISPB_D12_VSYNC			0x1f8 0x65c 0x928 0x2 0x1
+#define MX35_PAD_LD18__ESDHC3_CMD				0x1f8 0x65c 0x818 0x3 0x0
+#define MX35_PAD_LD18__USB_TOP_USBOTG_DATA_3			0x1f8 0x65c 0x9b0 0x4 0x0
+#define MX35_PAD_LD18__GPIO3_24					0x1f8 0x65c 0x000 0x5 0x0
+#define MX35_PAD_LD18__SDMA_SDMA_DEBUG_EVENT_CHANNEL_4		0x1f8 0x65c 0x000 0x6 0x0
+#define MX35_PAD_LD18__ARM11P_TOP_TRACE_11			0x1f8 0x65c 0x000 0x7 0x0
+#define MX35_PAD_LD19__IPU_DISPB_DAT_19				0x1fc 0x660 0x000 0x0 0x0
+#define MX35_PAD_LD19__IPU_DISPB_BCLK				0x1fc 0x660 0x000 0x1 0x0
+#define MX35_PAD_LD19__IPU_DISPB_CS1				0x1fc 0x660 0x000 0x2 0x0
+#define MX35_PAD_LD19__ESDHC3_CLK				0x1fc 0x660 0x814 0x3 0x0
+#define MX35_PAD_LD19__USB_TOP_USBOTG_DIR			0x1fc 0x660 0x9c4 0x4 0x0
+#define MX35_PAD_LD19__GPIO3_25					0x1fc 0x660 0x000 0x5 0x0
+#define MX35_PAD_LD19__SDMA_SDMA_DEBUG_EVENT_CHANNEL_5		0x1fc 0x660 0x000 0x6 0x0
+#define MX35_PAD_LD19__ARM11P_TOP_TRACE_12			0x1fc 0x660 0x000 0x7 0x0
+#define MX35_PAD_LD20__IPU_DISPB_DAT_20				0x200 0x664 0x000 0x0 0x0
+#define MX35_PAD_LD20__IPU_DISPB_CS0				0x200 0x664 0x000 0x1 0x0
+#define MX35_PAD_LD20__IPU_DISPB_SD_CLK				0x200 0x664 0x000 0x2 0x0
+#define MX35_PAD_LD20__ESDHC3_DAT0				0x200 0x664 0x81c 0x3 0x0
+#define MX35_PAD_LD20__GPIO3_26					0x200 0x664 0x000 0x5 0x0
+#define MX35_PAD_LD20__SDMA_SDMA_DEBUG_CORE_STATUS_3		0x200 0x664 0x000 0x6 0x0
+#define MX35_PAD_LD20__ARM11P_TOP_TRACE_13			0x200 0x664 0x000 0x7 0x0
+#define MX35_PAD_LD21__IPU_DISPB_DAT_21				0x204 0x668 0x000 0x0 0x0
+#define MX35_PAD_LD21__IPU_DISPB_PAR_RS				0x204 0x668 0x000 0x1 0x0
+#define MX35_PAD_LD21__IPU_DISPB_SER_RS				0x204 0x668 0x000 0x2 0x0
+#define MX35_PAD_LD21__ESDHC3_DAT1				0x204 0x668 0x820 0x3 0x0
+#define MX35_PAD_LD21__USB_TOP_USBOTG_STP			0x204 0x668 0x000 0x4 0x0
+#define MX35_PAD_LD21__GPIO3_27					0x204 0x668 0x000 0x5 0x0
+#define MX35_PAD_LD21__SDMA_DEBUG_EVENT_CHANNEL_SEL		0x204 0x668 0x000 0x6 0x0
+#define MX35_PAD_LD21__ARM11P_TOP_TRACE_14			0x204 0x668 0x000 0x7 0x0
+#define MX35_PAD_LD22__IPU_DISPB_DAT_22				0x208 0x66c 0x000 0x0 0x0
+#define MX35_PAD_LD22__IPU_DISPB_WR				0x208 0x66c 0x000 0x1 0x0
+#define MX35_PAD_LD22__IPU_DISPB_SD_D_I				0x208 0x66c 0x92c 0x2 0x0
+#define MX35_PAD_LD22__ESDHC3_DAT2				0x208 0x66c 0x824 0x3 0x0
+#define MX35_PAD_LD22__USB_TOP_USBOTG_NXT			0x208 0x66c 0x9c8 0x4 0x0
+#define MX35_PAD_LD22__GPIO3_28					0x208 0x66c 0x000 0x5 0x0
+#define MX35_PAD_LD22__SDMA_DEBUG_BUS_ERROR			0x208 0x66c 0x000 0x6 0x0
+#define MX35_PAD_LD22__ARM11P_TOP_TRCTL				0x208 0x66c 0x000 0x7 0x0
+#define MX35_PAD_LD23__IPU_DISPB_DAT_23				0x20c 0x670 0x000 0x0 0x0
+#define MX35_PAD_LD23__IPU_DISPB_RD				0x20c 0x670 0x000 0x1 0x0
+#define MX35_PAD_LD23__IPU_DISPB_SD_D_IO			0x20c 0x670 0x92c 0x2 0x1
+#define MX35_PAD_LD23__ESDHC3_DAT3				0x20c 0x670 0x828 0x3 0x0
+#define MX35_PAD_LD23__USB_TOP_USBOTG_DATA_7			0x20c 0x670 0x9c0 0x4 0x0
+#define MX35_PAD_LD23__GPIO3_29					0x20c 0x670 0x000 0x5 0x0
+#define MX35_PAD_LD23__SDMA_DEBUG_MATCHED_DMBUS			0x20c 0x670 0x000 0x6 0x0
+#define MX35_PAD_LD23__ARM11P_TOP_TRCLK				0x20c 0x670 0x000 0x7 0x0
+#define MX35_PAD_D3_HSYNC__IPU_DISPB_D3_HSYNC			0x210 0x674 0x000 0x0 0x0
+#define MX35_PAD_D3_HSYNC__IPU_DISPB_SD_D_IO			0x210 0x674 0x92c 0x2 0x2
+#define MX35_PAD_D3_HSYNC__GPIO3_30				0x210 0x674 0x000 0x5 0x0
+#define MX35_PAD_D3_HSYNC__SDMA_DEBUG_RTBUFFER_WRITE		0x210 0x674 0x000 0x6 0x0
+#define MX35_PAD_D3_HSYNC__ARM11P_TOP_TRACE_15			0x210 0x674 0x000 0x7 0x0
+#define MX35_PAD_D3_FPSHIFT__IPU_DISPB_D3_CLK			0x214 0x678 0x000 0x0 0x0
+#define MX35_PAD_D3_FPSHIFT__IPU_DISPB_SD_CLK			0x214 0x678 0x000 0x2 0x0
+#define MX35_PAD_D3_FPSHIFT__GPIO3_31				0x214 0x678 0x000 0x5 0x0
+#define MX35_PAD_D3_FPSHIFT__SDMA_SDMA_DEBUG_CORE_STATUS_0	0x214 0x678 0x000 0x6 0x0
+#define MX35_PAD_D3_FPSHIFT__ARM11P_TOP_TRACE_16		0x214 0x678 0x000 0x7 0x0
+#define MX35_PAD_D3_DRDY__IPU_DISPB_D3_DRDY			0x218 0x67c 0x000 0x0 0x0
+#define MX35_PAD_D3_DRDY__IPU_DISPB_SD_D_O			0x218 0x67c 0x000 0x2 0x0
+#define MX35_PAD_D3_DRDY__GPIO1_0				0x218 0x67c 0x82c 0x5 0x2
+#define MX35_PAD_D3_DRDY__SDMA_SDMA_DEBUG_CORE_STATUS_1		0x218 0x67c 0x000 0x6 0x0
+#define MX35_PAD_D3_DRDY__ARM11P_TOP_TRACE_17			0x218 0x67c 0x000 0x7 0x0
+#define MX35_PAD_CONTRAST__IPU_DISPB_CONTR			0x21c 0x680 0x000 0x0 0x0
+#define MX35_PAD_CONTRAST__GPIO1_1				0x21c 0x680 0x838 0x5 0x2
+#define MX35_PAD_CONTRAST__SDMA_SDMA_DEBUG_CORE_STATUS_2	0x21c 0x680 0x000 0x6 0x0
+#define MX35_PAD_CONTRAST__ARM11P_TOP_TRACE_18			0x21c 0x680 0x000 0x7 0x0
+#define MX35_PAD_D3_VSYNC__IPU_DISPB_D3_VSYNC			0x220 0x684 0x000 0x0 0x0
+#define MX35_PAD_D3_VSYNC__IPU_DISPB_CS1			0x220 0x684 0x000 0x2 0x0
+#define MX35_PAD_D3_VSYNC__GPIO1_2				0x220 0x684 0x848 0x5 0x1
+#define MX35_PAD_D3_VSYNC__SDMA_DEBUG_YIELD			0x220 0x684 0x000 0x6 0x0
+#define MX35_PAD_D3_VSYNC__ARM11P_TOP_TRACE_19			0x220 0x684 0x000 0x7 0x0
+#define MX35_PAD_D3_REV__IPU_DISPB_D3_REV			0x224 0x688 0x000 0x0 0x0
+#define MX35_PAD_D3_REV__IPU_DISPB_SER_RS			0x224 0x688 0x000 0x2 0x0
+#define MX35_PAD_D3_REV__GPIO1_3				0x224 0x688 0x84c 0x5 0x1
+#define MX35_PAD_D3_REV__SDMA_DEBUG_BUS_RWB			0x224 0x688 0x000 0x6 0x0
+#define MX35_PAD_D3_REV__ARM11P_TOP_TRACE_20			0x224 0x688 0x000 0x7 0x0
+#define MX35_PAD_D3_CLS__IPU_DISPB_D3_CLS			0x228 0x68c 0x000 0x0 0x0
+#define MX35_PAD_D3_CLS__IPU_DISPB_CS2				0x228 0x68c 0x000 0x2 0x0
+#define MX35_PAD_D3_CLS__GPIO1_4				0x228 0x68c 0x850 0x5 0x2
+#define MX35_PAD_D3_CLS__SDMA_DEBUG_BUS_DEVICE_0		0x228 0x68c 0x000 0x6 0x0
+#define MX35_PAD_D3_CLS__ARM11P_TOP_TRACE_21			0x228 0x68c 0x000 0x7 0x0
+#define MX35_PAD_D3_SPL__IPU_DISPB_D3_SPL			0x22c 0x690 0x000 0x0 0x0
+#define MX35_PAD_D3_SPL__IPU_DISPB_D12_VSYNC			0x22c 0x690 0x928 0x2 0x2
+#define MX35_PAD_D3_SPL__GPIO1_5				0x22c 0x690 0x854 0x5 0x2
+#define MX35_PAD_D3_SPL__SDMA_DEBUG_BUS_DEVICE_1		0x22c 0x690 0x000 0x6 0x0
+#define MX35_PAD_D3_SPL__ARM11P_TOP_TRACE_22			0x22c 0x690 0x000 0x7 0x0
+#define MX35_PAD_SD1_CMD__ESDHC1_CMD				0x230 0x694 0x000 0x0 0x0
+#define MX35_PAD_SD1_CMD__MSHC_SCLK				0x230 0x694 0x000 0x1 0x0
+#define MX35_PAD_SD1_CMD__IPU_DISPB_D0_VSYNC			0x230 0x694 0x924 0x3 0x2
+#define MX35_PAD_SD1_CMD__USB_TOP_USBOTG_DATA_4			0x230 0x694 0x9b4 0x4 0x0
+#define MX35_PAD_SD1_CMD__GPIO1_6				0x230 0x694 0x858 0x5 0x2
+#define MX35_PAD_SD1_CMD__ARM11P_TOP_TRCTL			0x230 0x694 0x000 0x7 0x0
+#define MX35_PAD_SD1_CLK__ESDHC1_CLK				0x234 0x698 0x000 0x0 0x0
+#define MX35_PAD_SD1_CLK__MSHC_BS				0x234 0x698 0x000 0x1 0x0
+#define MX35_PAD_SD1_CLK__IPU_DISPB_BCLK			0x234 0x698 0x000 0x3 0x0
+#define MX35_PAD_SD1_CLK__USB_TOP_USBOTG_DATA_5			0x234 0x698 0x9b8 0x4 0x0
+#define MX35_PAD_SD1_CLK__GPIO1_7				0x234 0x698 0x85c 0x5 0x2
+#define MX35_PAD_SD1_CLK__ARM11P_TOP_TRCLK			0x234 0x698 0x000 0x7 0x0
+#define MX35_PAD_SD1_DATA0__ESDHC1_DAT0				0x238 0x69c 0x000 0x0 0x0
+#define MX35_PAD_SD1_DATA0__MSHC_DATA_0				0x238 0x69c 0x000 0x1 0x0
+#define MX35_PAD_SD1_DATA0__IPU_DISPB_CS0			0x238 0x69c 0x000 0x3 0x0
+#define MX35_PAD_SD1_DATA0__USB_TOP_USBOTG_DATA_6		0x238 0x69c 0x9bc 0x4 0x0
+#define MX35_PAD_SD1_DATA0__GPIO1_8				0x238 0x69c 0x860 0x5 0x2
+#define MX35_PAD_SD1_DATA0__ARM11P_TOP_TRACE_23			0x238 0x69c 0x000 0x7 0x0
+#define MX35_PAD_SD1_DATA1__ESDHC1_DAT1				0x23c 0x6a0 0x000 0x0 0x0
+#define MX35_PAD_SD1_DATA1__MSHC_DATA_1				0x23c 0x6a0 0x000 0x1 0x0
+#define MX35_PAD_SD1_DATA1__IPU_DISPB_PAR_RS			0x23c 0x6a0 0x000 0x3 0x0
+#define MX35_PAD_SD1_DATA1__USB_TOP_USBOTG_DATA_0		0x23c 0x6a0 0x9a4 0x4 0x0
+#define MX35_PAD_SD1_DATA1__GPIO1_9				0x23c 0x6a0 0x864 0x5 0x1
+#define MX35_PAD_SD1_DATA1__ARM11P_TOP_TRACE_24			0x23c 0x6a0 0x000 0x7 0x0
+#define MX35_PAD_SD1_DATA2__ESDHC1_DAT2				0x240 0x6a4 0x000 0x0 0x0
+#define MX35_PAD_SD1_DATA2__MSHC_DATA_2				0x240 0x6a4 0x000 0x1 0x0
+#define MX35_PAD_SD1_DATA2__IPU_DISPB_WR			0x240 0x6a4 0x000 0x3 0x0
+#define MX35_PAD_SD1_DATA2__USB_TOP_USBOTG_DATA_1		0x240 0x6a4 0x9a8 0x4 0x0
+#define MX35_PAD_SD1_DATA2__GPIO1_10				0x240 0x6a4 0x830 0x5 0x1
+#define MX35_PAD_SD1_DATA2__ARM11P_TOP_TRACE_25			0x240 0x6a4 0x000 0x7 0x0
+#define MX35_PAD_SD1_DATA3__ESDHC1_DAT3				0x244 0x6a8 0x000 0x0 0x0
+#define MX35_PAD_SD1_DATA3__MSHC_DATA_3				0x244 0x6a8 0x000 0x1 0x0
+#define MX35_PAD_SD1_DATA3__IPU_DISPB_RD			0x244 0x6a8 0x000 0x3 0x0
+#define MX35_PAD_SD1_DATA3__USB_TOP_USBOTG_DATA_2		0x244 0x6a8 0x9ac 0x4 0x0
+#define MX35_PAD_SD1_DATA3__GPIO1_11				0x244 0x6a8 0x834 0x5 0x1
+#define MX35_PAD_SD1_DATA3__ARM11P_TOP_TRACE_26			0x244 0x6a8 0x000 0x7 0x0
+#define MX35_PAD_SD2_CMD__ESDHC2_CMD				0x248 0x6ac 0x000 0x0 0x0
+#define MX35_PAD_SD2_CMD__I2C3_SCL				0x248 0x6ac 0x91c 0x1 0x2
+#define MX35_PAD_SD2_CMD__ESDHC1_DAT4				0x248 0x6ac 0x804 0x2 0x0
+#define MX35_PAD_SD2_CMD__IPU_CSI_D_2				0x248 0x6ac 0x938 0x3 0x2
+#define MX35_PAD_SD2_CMD__USB_TOP_USBH2_DATA_4			0x248 0x6ac 0x9dc 0x4 0x0
+#define MX35_PAD_SD2_CMD__GPIO2_0				0x248 0x6ac 0x868 0x5 0x2
+#define MX35_PAD_SD2_CMD__SPDIF_SPDIF_OUT1			0x248 0x6ac 0x000 0x6 0x0
+#define MX35_PAD_SD2_CMD__IPU_DISPB_D12_VSYNC			0x248 0x6ac 0x928 0x7 0x3
+#define MX35_PAD_SD2_CLK__ESDHC2_CLK				0x24c 0x6b0 0x000 0x0 0x0
+#define MX35_PAD_SD2_CLK__I2C3_SDA				0x24c 0x6b0 0x920 0x1 0x2
+#define MX35_PAD_SD2_CLK__ESDHC1_DAT5				0x24c 0x6b0 0x808 0x2 0x0
+#define MX35_PAD_SD2_CLK__IPU_CSI_D_3				0x24c 0x6b0 0x93c 0x3 0x2
+#define MX35_PAD_SD2_CLK__USB_TOP_USBH2_DATA_5			0x24c 0x6b0 0x9e0 0x4 0x0
+#define MX35_PAD_SD2_CLK__GPIO2_1				0x24c 0x6b0 0x894 0x5 0x1
+#define MX35_PAD_SD2_CLK__SPDIF_SPDIF_IN1			0x24c 0x6b0 0x998 0x6 0x2
+#define MX35_PAD_SD2_CLK__IPU_DISPB_CS2				0x24c 0x6b0 0x000 0x7 0x0
+#define MX35_PAD_SD2_DATA0__ESDHC2_DAT0				0x250 0x6b4 0x000 0x0 0x0
+#define MX35_PAD_SD2_DATA0__UART3_RXD_MUX			0x250 0x6b4 0x9a0 0x1 0x1
+#define MX35_PAD_SD2_DATA0__ESDHC1_DAT6				0x250 0x6b4 0x80c 0x2 0x0
+#define MX35_PAD_SD2_DATA0__IPU_CSI_D_4				0x250 0x6b4 0x940 0x3 0x1
+#define MX35_PAD_SD2_DATA0__USB_TOP_USBH2_DATA_6		0x250 0x6b4 0x9e4 0x4 0x0
+#define MX35_PAD_SD2_DATA0__GPIO2_2				0x250 0x6b4 0x8c0 0x5 0x1
+#define MX35_PAD_SD2_DATA0__SPDIF_SPDIF_EXTCLK			0x250 0x6b4 0x994 0x6 0x3
+#define MX35_PAD_SD2_DATA1__ESDHC2_DAT1				0x254 0x6b8 0x000 0x0 0x0
+#define MX35_PAD_SD2_DATA1__UART3_TXD_MUX			0x254 0x6b8 0x000 0x1 0x0
+#define MX35_PAD_SD2_DATA1__ESDHC1_DAT7				0x254 0x6b8 0x810 0x2 0x0
+#define MX35_PAD_SD2_DATA1__IPU_CSI_D_5				0x254 0x6b8 0x944 0x3 0x1
+#define MX35_PAD_SD2_DATA1__USB_TOP_USBH2_DATA_0		0x254 0x6b8 0x9cc 0x4 0x0
+#define MX35_PAD_SD2_DATA1__GPIO2_3				0x254 0x6b8 0x8cc 0x5 0x1
+#define MX35_PAD_SD2_DATA2__ESDHC2_DAT2				0x258 0x6bc 0x000 0x0 0x0
+#define MX35_PAD_SD2_DATA2__UART3_RTS				0x258 0x6bc 0x99c 0x1 0x0
+#define MX35_PAD_SD2_DATA2__CAN1_RXCAN				0x258 0x6bc 0x7c8 0x2 0x1
+#define MX35_PAD_SD2_DATA2__IPU_CSI_D_6				0x258 0x6bc 0x948 0x3 0x1
+#define MX35_PAD_SD2_DATA2__USB_TOP_USBH2_DATA_1		0x258 0x6bc 0x9d0 0x4 0x0
+#define MX35_PAD_SD2_DATA2__GPIO2_4				0x258 0x6bc 0x8d0 0x5 0x1
+#define MX35_PAD_SD2_DATA3__ESDHC2_DAT3				0x25c 0x6c0 0x000 0x0 0x0
+#define MX35_PAD_SD2_DATA3__UART3_CTS				0x25c 0x6c0 0x000 0x1 0x0
+#define MX35_PAD_SD2_DATA3__CAN1_TXCAN				0x25c 0x6c0 0x000 0x2 0x0
+#define MX35_PAD_SD2_DATA3__IPU_CSI_D_7				0x25c 0x6c0 0x94c 0x3 0x1
+#define MX35_PAD_SD2_DATA3__USB_TOP_USBH2_DATA_2		0x25c 0x6c0 0x9d4 0x4 0x0
+#define MX35_PAD_SD2_DATA3__GPIO2_5				0x25c 0x6c0 0x8d4 0x5 0x1
+#define MX35_PAD_ATA_CS0__ATA_CS0				0x260 0x6c4 0x000 0x0 0x0
+#define MX35_PAD_ATA_CS0__CSPI1_SS3				0x260 0x6c4 0x7dc 0x1 0x1
+#define MX35_PAD_ATA_CS0__IPU_DISPB_CS1				0x260 0x6c4 0x000 0x3 0x0
+#define MX35_PAD_ATA_CS0__GPIO2_6				0x260 0x6c4 0x8d8 0x5 0x1
+#define MX35_PAD_ATA_CS0__IPU_DIAGB_0				0x260 0x6c4 0x000 0x6 0x0
+#define MX35_PAD_ATA_CS0__ARM11P_TOP_MAX1_HMASTER_0		0x260 0x6c4 0x000 0x7 0x0
+#define MX35_PAD_ATA_CS1__ATA_CS1				0x264 0x6c8 0x000 0x0 0x0
+#define MX35_PAD_ATA_CS1__IPU_DISPB_CS2				0x264 0x6c8 0x000 0x3 0x0
+#define MX35_PAD_ATA_CS1__CSPI2_SS0				0x264 0x6c8 0x7f0 0x4 0x1
+#define MX35_PAD_ATA_CS1__GPIO2_7				0x264 0x6c8 0x8dc 0x5 0x1
+#define MX35_PAD_ATA_CS1__IPU_DIAGB_1				0x264 0x6c8 0x000 0x6 0x0
+#define MX35_PAD_ATA_CS1__ARM11P_TOP_MAX1_HMASTER_1		0x264 0x6c8 0x000 0x7 0x0
+#define MX35_PAD_ATA_DIOR__ATA_DIOR				0x268 0x6cc 0x000 0x0 0x0
+#define MX35_PAD_ATA_DIOR__ESDHC3_DAT0				0x268 0x6cc 0x81c 0x1 0x1
+#define MX35_PAD_ATA_DIOR__USB_TOP_USBOTG_DIR			0x268 0x6cc 0x9c4 0x2 0x1
+#define MX35_PAD_ATA_DIOR__IPU_DISPB_BE0			0x268 0x6cc 0x000 0x3 0x0
+#define MX35_PAD_ATA_DIOR__CSPI2_SS1				0x268 0x6cc 0x7f4 0x4 0x1
+#define MX35_PAD_ATA_DIOR__GPIO2_8				0x268 0x6cc 0x8e0 0x5 0x1
+#define MX35_PAD_ATA_DIOR__IPU_DIAGB_2				0x268 0x6cc 0x000 0x6 0x0
+#define MX35_PAD_ATA_DIOR__ARM11P_TOP_MAX1_HMASTER_2		0x268 0x6cc 0x000 0x7 0x0
+#define MX35_PAD_ATA_DIOW__ATA_DIOW				0x26c 0x6d0 0x000 0x0 0x0
+#define MX35_PAD_ATA_DIOW__ESDHC3_DAT1				0x26c 0x6d0 0x820 0x1 0x1
+#define MX35_PAD_ATA_DIOW__USB_TOP_USBOTG_STP			0x26c 0x6d0 0x000 0x2 0x0
+#define MX35_PAD_ATA_DIOW__IPU_DISPB_BE1			0x26c 0x6d0 0x000 0x3 0x0
+#define MX35_PAD_ATA_DIOW__CSPI2_MOSI				0x26c 0x6d0 0x7ec 0x4 0x2
+#define MX35_PAD_ATA_DIOW__GPIO2_9				0x26c 0x6d0 0x8e4 0x5 0x1
+#define MX35_PAD_ATA_DIOW__IPU_DIAGB_3				0x26c 0x6d0 0x000 0x6 0x0
+#define MX35_PAD_ATA_DIOW__ARM11P_TOP_MAX1_HMASTER_3		0x26c 0x6d0 0x000 0x7 0x0
+#define MX35_PAD_ATA_DMACK__ATA_DMACK				0x270 0x6d4 0x000 0x0 0x0
+#define MX35_PAD_ATA_DMACK__ESDHC3_DAT2				0x270 0x6d4 0x824 0x1 0x1
+#define MX35_PAD_ATA_DMACK__USB_TOP_USBOTG_NXT			0x270 0x6d4 0x9c8 0x2 0x1
+#define MX35_PAD_ATA_DMACK__CSPI2_MISO				0x270 0x6d4 0x7e8 0x4 0x2
+#define MX35_PAD_ATA_DMACK__GPIO2_10				0x270 0x6d4 0x86c 0x5 0x1
+#define MX35_PAD_ATA_DMACK__IPU_DIAGB_4				0x270 0x6d4 0x000 0x6 0x0
+#define MX35_PAD_ATA_DMACK__ARM11P_TOP_MAX0_HMASTER_0		0x270 0x6d4 0x000 0x7 0x0
+#define MX35_PAD_ATA_RESET_B__ATA_RESET_B			0x274 0x6d8 0x000 0x0 0x0
+#define MX35_PAD_ATA_RESET_B__ESDHC3_DAT3			0x274 0x6d8 0x828 0x1 0x1
+#define MX35_PAD_ATA_RESET_B__USB_TOP_USBOTG_DATA_0		0x274 0x6d8 0x9a4 0x2 0x1
+#define MX35_PAD_ATA_RESET_B__IPU_DISPB_SD_D_O			0x274 0x6d8 0x000 0x3 0x0
+#define MX35_PAD_ATA_RESET_B__CSPI2_RDY				0x274 0x6d8 0x7e4 0x4 0x2
+#define MX35_PAD_ATA_RESET_B__GPIO2_11				0x274 0x6d8 0x870 0x5 0x1
+#define MX35_PAD_ATA_RESET_B__IPU_DIAGB_5			0x274 0x6d8 0x000 0x6 0x0
+#define MX35_PAD_ATA_RESET_B__ARM11P_TOP_MAX0_HMASTER_1		0x274 0x6d8 0x000 0x7 0x0
+#define MX35_PAD_ATA_IORDY__ATA_IORDY				0x278 0x6dc 0x000 0x0 0x0
+#define MX35_PAD_ATA_IORDY__ESDHC3_DAT4				0x278 0x6dc 0x000 0x1 0x0
+#define MX35_PAD_ATA_IORDY__USB_TOP_USBOTG_DATA_1		0x278 0x6dc 0x9a8 0x2 0x1
+#define MX35_PAD_ATA_IORDY__IPU_DISPB_SD_D_IO			0x278 0x6dc 0x92c 0x3 0x3
+#define MX35_PAD_ATA_IORDY__ESDHC2_DAT4				0x278 0x6dc 0x000 0x4 0x0
+#define MX35_PAD_ATA_IORDY__GPIO2_12				0x278 0x6dc 0x874 0x5 0x1
+#define MX35_PAD_ATA_IORDY__IPU_DIAGB_6				0x278 0x6dc 0x000 0x6 0x0
+#define MX35_PAD_ATA_IORDY__ARM11P_TOP_MAX0_HMASTER_2		0x278 0x6dc 0x000 0x7 0x0
+#define MX35_PAD_ATA_DATA0__ATA_DATA_0				0x27c 0x6e0 0x000 0x0 0x0
+#define MX35_PAD_ATA_DATA0__ESDHC3_DAT5				0x27c 0x6e0 0x000 0x1 0x0
+#define MX35_PAD_ATA_DATA0__USB_TOP_USBOTG_DATA_2		0x27c 0x6e0 0x9ac 0x2 0x1
+#define MX35_PAD_ATA_DATA0__IPU_DISPB_D12_VSYNC			0x27c 0x6e0 0x928 0x3 0x4
+#define MX35_PAD_ATA_DATA0__ESDHC2_DAT5				0x27c 0x6e0 0x000 0x4 0x0
+#define MX35_PAD_ATA_DATA0__GPIO2_13				0x27c 0x6e0 0x878 0x5 0x1
+#define MX35_PAD_ATA_DATA0__IPU_DIAGB_7				0x27c 0x6e0 0x000 0x6 0x0
+#define MX35_PAD_ATA_DATA0__ARM11P_TOP_MAX0_HMASTER_3		0x27c 0x6e0 0x000 0x7 0x0
+#define MX35_PAD_ATA_DATA1__ATA_DATA_1				0x280 0x6e4 0x000 0x0 0x0
+#define MX35_PAD_ATA_DATA1__ESDHC3_DAT6				0x280 0x6e4 0x000 0x1 0x0
+#define MX35_PAD_ATA_DATA1__USB_TOP_USBOTG_DATA_3		0x280 0x6e4 0x9b0 0x2 0x1
+#define MX35_PAD_ATA_DATA1__IPU_DISPB_SD_CLK			0x280 0x6e4 0x000 0x3 0x0
+#define MX35_PAD_ATA_DATA1__ESDHC2_DAT6				0x280 0x6e4 0x000 0x4 0x0
+#define MX35_PAD_ATA_DATA1__GPIO2_14				0x280 0x6e4 0x87c 0x5 0x1
+#define MX35_PAD_ATA_DATA1__IPU_DIAGB_8				0x280 0x6e4 0x000 0x6 0x0
+#define MX35_PAD_ATA_DATA1__ARM11P_TOP_TRACE_27			0x280 0x6e4 0x000 0x7 0x0
+#define MX35_PAD_ATA_DATA2__ATA_DATA_2				0x284 0x6e8 0x000 0x0 0x0
+#define MX35_PAD_ATA_DATA2__ESDHC3_DAT7				0x284 0x6e8 0x000 0x1 0x0
+#define MX35_PAD_ATA_DATA2__USB_TOP_USBOTG_DATA_4		0x284 0x6e8 0x9b4 0x2 0x1
+#define MX35_PAD_ATA_DATA2__IPU_DISPB_SER_RS			0x284 0x6e8 0x000 0x3 0x0
+#define MX35_PAD_ATA_DATA2__ESDHC2_DAT7				0x284 0x6e8 0x000 0x4 0x0
+#define MX35_PAD_ATA_DATA2__GPIO2_15				0x284 0x6e8 0x880 0x5 0x1
+#define MX35_PAD_ATA_DATA2__IPU_DIAGB_9				0x284 0x6e8 0x000 0x6 0x0
+#define MX35_PAD_ATA_DATA2__ARM11P_TOP_TRACE_28			0x284 0x6e8 0x000 0x7 0x0
+#define MX35_PAD_ATA_DATA3__ATA_DATA_3				0x288 0x6ec 0x000 0x0 0x0
+#define MX35_PAD_ATA_DATA3__ESDHC3_CLK				0x288 0x6ec 0x814 0x1 0x1
+#define MX35_PAD_ATA_DATA3__USB_TOP_USBOTG_DATA_5		0x288 0x6ec 0x9b8 0x2 0x1
+#define MX35_PAD_ATA_DATA3__CSPI2_SCLK				0x288 0x6ec 0x7e0 0x4 0x2
+#define MX35_PAD_ATA_DATA3__GPIO2_16				0x288 0x6ec 0x884 0x5 0x1
+#define MX35_PAD_ATA_DATA3__IPU_DIAGB_10			0x288 0x6ec 0x000 0x6 0x0
+#define MX35_PAD_ATA_DATA3__ARM11P_TOP_TRACE_29			0x288 0x6ec 0x000 0x7 0x0
+#define MX35_PAD_ATA_DATA4__ATA_DATA_4				0x28c 0x6f0 0x000 0x0 0x0
+#define MX35_PAD_ATA_DATA4__ESDHC3_CMD				0x28c 0x6f0 0x818 0x1 0x1
+#define MX35_PAD_ATA_DATA4__USB_TOP_USBOTG_DATA_6		0x28c 0x6f0 0x9bc 0x2 0x1
+#define MX35_PAD_ATA_DATA4__GPIO2_17				0x28c 0x6f0 0x888 0x5 0x1
+#define MX35_PAD_ATA_DATA4__IPU_DIAGB_11			0x28c 0x6f0 0x000 0x6 0x0
+#define MX35_PAD_ATA_DATA4__ARM11P_TOP_TRACE_30			0x28c 0x6f0 0x000 0x7 0x0
+#define MX35_PAD_ATA_DATA5__ATA_DATA_5				0x290 0x6f4 0x000 0x0 0x0
+#define MX35_PAD_ATA_DATA5__USB_TOP_USBOTG_DATA_7		0x290 0x6f4 0x9c0 0x2 0x1
+#define MX35_PAD_ATA_DATA5__GPIO2_18				0x290 0x6f4 0x88c 0x5 0x1
+#define MX35_PAD_ATA_DATA5__IPU_DIAGB_12			0x290 0x6f4 0x000 0x6 0x0
+#define MX35_PAD_ATA_DATA5__ARM11P_TOP_TRACE_31			0x290 0x6f4 0x000 0x7 0x0
+#define MX35_PAD_ATA_DATA6__ATA_DATA_6				0x294 0x6f8 0x000 0x0 0x0
+#define MX35_PAD_ATA_DATA6__CAN1_TXCAN				0x294 0x6f8 0x000 0x1 0x0
+#define MX35_PAD_ATA_DATA6__UART1_DTR				0x294 0x6f8 0x000 0x2 0x0
+#define MX35_PAD_ATA_DATA6__AUDMUX_AUD6_TXD			0x294 0x6f8 0x7b4 0x3 0x0
+#define MX35_PAD_ATA_DATA6__GPIO2_19				0x294 0x6f8 0x890 0x5 0x1
+#define MX35_PAD_ATA_DATA6__IPU_DIAGB_13			0x294 0x6f8 0x000 0x6 0x0
+#define MX35_PAD_ATA_DATA7__ATA_DATA_7				0x298 0x6fc 0x000 0x0 0x0
+#define MX35_PAD_ATA_DATA7__CAN1_RXCAN				0x298 0x6fc 0x7c8 0x1 0x2
+#define MX35_PAD_ATA_DATA7__UART1_DSR				0x298 0x6fc 0x000 0x2 0x0
+#define MX35_PAD_ATA_DATA7__AUDMUX_AUD6_RXD			0x298 0x6fc 0x7b0 0x3 0x0
+#define MX35_PAD_ATA_DATA7__GPIO2_20				0x298 0x6fc 0x898 0x5 0x1
+#define MX35_PAD_ATA_DATA7__IPU_DIAGB_14			0x298 0x6fc 0x000 0x6 0x0
+#define MX35_PAD_ATA_DATA8__ATA_DATA_8				0x29c 0x700 0x000 0x0 0x0
+#define MX35_PAD_ATA_DATA8__UART3_RTS				0x29c 0x700 0x99c 0x1 0x1
+#define MX35_PAD_ATA_DATA8__UART1_RI				0x29c 0x700 0x000 0x2 0x0
+#define MX35_PAD_ATA_DATA8__AUDMUX_AUD6_TXC			0x29c 0x700 0x7c0 0x3 0x0
+#define MX35_PAD_ATA_DATA8__GPIO2_21				0x29c 0x700 0x89c 0x5 0x1
+#define MX35_PAD_ATA_DATA8__IPU_DIAGB_15			0x29c 0x700 0x000 0x6 0x0
+#define MX35_PAD_ATA_DATA9__ATA_DATA_9				0x2a0 0x704 0x000 0x0 0x0
+#define MX35_PAD_ATA_DATA9__UART3_CTS				0x2a0 0x704 0x000 0x1 0x0
+#define MX35_PAD_ATA_DATA9__UART1_DCD				0x2a0 0x704 0x000 0x2 0x0
+#define MX35_PAD_ATA_DATA9__AUDMUX_AUD6_TXFS			0x2a0 0x704 0x7c4 0x3 0x0
+#define MX35_PAD_ATA_DATA9__GPIO2_22				0x2a0 0x704 0x8a0 0x5 0x1
+#define MX35_PAD_ATA_DATA9__IPU_DIAGB_16			0x2a0 0x704 0x000 0x6 0x0
+#define MX35_PAD_ATA_DATA10__ATA_DATA_10			0x2a4 0x708 0x000 0x0 0x0
+#define MX35_PAD_ATA_DATA10__UART3_RXD_MUX			0x2a4 0x708 0x9a0 0x1 0x2
+#define MX35_PAD_ATA_DATA10__AUDMUX_AUD6_RXC			0x2a4 0x708 0x7b8 0x3 0x0
+#define MX35_PAD_ATA_DATA10__GPIO2_23				0x2a4 0x708 0x8a4 0x5 0x1
+#define MX35_PAD_ATA_DATA10__IPU_DIAGB_17			0x2a4 0x708 0x000 0x6 0x0
+#define MX35_PAD_ATA_DATA11__ATA_DATA_11			0x2a8 0x70c 0x000 0x0 0x0
+#define MX35_PAD_ATA_DATA11__UART3_TXD_MUX			0x2a8 0x70c 0x000 0x1 0x0
+#define MX35_PAD_ATA_DATA11__AUDMUX_AUD6_RXFS			0x2a8 0x70c 0x7bc 0x3 0x0
+#define MX35_PAD_ATA_DATA11__GPIO2_24				0x2a8 0x70c 0x8a8 0x5 0x1
+#define MX35_PAD_ATA_DATA11__IPU_DIAGB_18			0x2a8 0x70c 0x000 0x6 0x0
+#define MX35_PAD_ATA_DATA12__ATA_DATA_12			0x2ac 0x710 0x000 0x0 0x0
+#define MX35_PAD_ATA_DATA12__I2C3_SCL				0x2ac 0x710 0x91c 0x1 0x3
+#define MX35_PAD_ATA_DATA12__GPIO2_25				0x2ac 0x710 0x8ac 0x5 0x1
+#define MX35_PAD_ATA_DATA12__IPU_DIAGB_19			0x2ac 0x710 0x000 0x6 0x0
+#define MX35_PAD_ATA_DATA13__ATA_DATA_13			0x2b0 0x714 0x000 0x0 0x0
+#define MX35_PAD_ATA_DATA13__I2C3_SDA				0x2b0 0x714 0x920 0x1 0x3
+#define MX35_PAD_ATA_DATA13__GPIO2_26				0x2b0 0x714 0x8b0 0x5 0x1
+#define MX35_PAD_ATA_DATA13__IPU_DIAGB_20			0x2b0 0x714 0x000 0x6 0x0
+#define MX35_PAD_ATA_DATA14__ATA_DATA_14			0x2b4 0x718 0x000 0x0 0x0
+#define MX35_PAD_ATA_DATA14__IPU_CSI_D_0			0x2b4 0x718 0x930 0x1 0x2
+#define MX35_PAD_ATA_DATA14__KPP_ROW_0				0x2b4 0x718 0x970 0x3 0x2
+#define MX35_PAD_ATA_DATA14__GPIO2_27				0x2b4 0x718 0x8b4 0x5 0x1
+#define MX35_PAD_ATA_DATA14__IPU_DIAGB_21			0x2b4 0x718 0x000 0x6 0x0
+#define MX35_PAD_ATA_DATA15__ATA_DATA_15			0x2b8 0x71c 0x000 0x0 0x0
+#define MX35_PAD_ATA_DATA15__IPU_CSI_D_1			0x2b8 0x71c 0x934 0x1 0x2
+#define MX35_PAD_ATA_DATA15__KPP_ROW_1				0x2b8 0x71c 0x974 0x3 0x2
+#define MX35_PAD_ATA_DATA15__GPIO2_28				0x2b8 0x71c 0x8b8 0x5 0x1
+#define MX35_PAD_ATA_DATA15__IPU_DIAGB_22			0x2b8 0x71c 0x000 0x6 0x0
+#define MX35_PAD_ATA_INTRQ__ATA_INTRQ				0x2bc 0x720 0x000 0x0 0x0
+#define MX35_PAD_ATA_INTRQ__IPU_CSI_D_2				0x2bc 0x720 0x938 0x1 0x3
+#define MX35_PAD_ATA_INTRQ__KPP_ROW_2				0x2bc 0x720 0x978 0x3 0x2
+#define MX35_PAD_ATA_INTRQ__GPIO2_29				0x2bc 0x720 0x8bc 0x5 0x1
+#define MX35_PAD_ATA_INTRQ__IPU_DIAGB_23			0x2bc 0x720 0x000 0x6 0x0
+#define MX35_PAD_ATA_BUFF_EN__ATA_BUFFER_EN			0x2c0 0x724 0x000 0x0 0x0
+#define MX35_PAD_ATA_BUFF_EN__IPU_CSI_D_3			0x2c0 0x724 0x93c 0x1 0x3
+#define MX35_PAD_ATA_BUFF_EN__KPP_ROW_3				0x2c0 0x724 0x97c 0x3 0x2
+#define MX35_PAD_ATA_BUFF_EN__GPIO2_30				0x2c0 0x724 0x8c4 0x5 0x1
+#define MX35_PAD_ATA_BUFF_EN__IPU_DIAGB_24			0x2c0 0x724 0x000 0x6 0x0
+#define MX35_PAD_ATA_DMARQ__ATA_DMARQ				0x2c4 0x728 0x000 0x0 0x0
+#define MX35_PAD_ATA_DMARQ__IPU_CSI_D_4				0x2c4 0x728 0x940 0x1 0x2
+#define MX35_PAD_ATA_DMARQ__KPP_COL_0				0x2c4 0x728 0x950 0x3 0x2
+#define MX35_PAD_ATA_DMARQ__GPIO2_31				0x2c4 0x728 0x8c8 0x5 0x1
+#define MX35_PAD_ATA_DMARQ__IPU_DIAGB_25			0x2c4 0x728 0x000 0x6 0x0
+#define MX35_PAD_ATA_DMARQ__ECT_CTI_TRIG_IN1_4			0x2c4 0x728 0x000 0x7 0x0
+#define MX35_PAD_ATA_DA0__ATA_DA_0				0x2c8 0x72c 0x000 0x0 0x0
+#define MX35_PAD_ATA_DA0__IPU_CSI_D_5				0x2c8 0x72c 0x944 0x1 0x2
+#define MX35_PAD_ATA_DA0__KPP_COL_1				0x2c8 0x72c 0x954 0x3 0x2
+#define MX35_PAD_ATA_DA0__GPIO3_0				0x2c8 0x72c 0x8e8 0x5 0x1
+#define MX35_PAD_ATA_DA0__IPU_DIAGB_26				0x2c8 0x72c 0x000 0x6 0x0
+#define MX35_PAD_ATA_DA0__ECT_CTI_TRIG_IN1_5			0x2c8 0x72c 0x000 0x7 0x0
+#define MX35_PAD_ATA_DA1__ATA_DA_1				0x2cc 0x730 0x000 0x0 0x0
+#define MX35_PAD_ATA_DA1__IPU_CSI_D_6				0x2cc 0x730 0x948 0x1 0x2
+#define MX35_PAD_ATA_DA1__KPP_COL_2				0x2cc 0x730 0x958 0x3 0x2
+#define MX35_PAD_ATA_DA1__GPIO3_1				0x2cc 0x730 0x000 0x5 0x0
+#define MX35_PAD_ATA_DA1__IPU_DIAGB_27				0x2cc 0x730 0x000 0x6 0x0
+#define MX35_PAD_ATA_DA1__ECT_CTI_TRIG_IN1_6			0x2cc 0x730 0x000 0x7 0x0
+#define MX35_PAD_ATA_DA2__ATA_DA_2				0x2d0 0x734 0x000 0x0 0x0
+#define MX35_PAD_ATA_DA2__IPU_CSI_D_7				0x2d0 0x734 0x94c 0x1 0x2
+#define MX35_PAD_ATA_DA2__KPP_COL_3				0x2d0 0x734 0x95c 0x3 0x2
+#define MX35_PAD_ATA_DA2__GPIO3_2				0x2d0 0x734 0x000 0x5 0x0
+#define MX35_PAD_ATA_DA2__IPU_DIAGB_28				0x2d0 0x734 0x000 0x6 0x0
+#define MX35_PAD_ATA_DA2__ECT_CTI_TRIG_IN1_7			0x2d0 0x734 0x000 0x7 0x0
+#define MX35_PAD_MLB_CLK__MLB_MLBCLK				0x2d4 0x738 0x000 0x0 0x0
+#define MX35_PAD_MLB_CLK__GPIO3_3				0x2d4 0x738 0x000 0x5 0x0
+#define MX35_PAD_MLB_DAT__MLB_MLBDAT				0x2d8 0x73c 0x000 0x0 0x0
+#define MX35_PAD_MLB_DAT__GPIO3_4				0x2d8 0x73c 0x904 0x5 0x1
+#define MX35_PAD_MLB_SIG__MLB_MLBSIG				0x2dc 0x740 0x000 0x0 0x0
+#define MX35_PAD_MLB_SIG__GPIO3_5				0x2dc 0x740 0x908 0x5 0x1
+#define MX35_PAD_FEC_TX_CLK__FEC_TX_CLK				0x2e0 0x744 0x000 0x0 0x0
+#define MX35_PAD_FEC_TX_CLK__ESDHC1_DAT4			0x2e0 0x744 0x804 0x1 0x1
+#define MX35_PAD_FEC_TX_CLK__UART3_RXD_MUX			0x2e0 0x744 0x9a0 0x2 0x3
+#define MX35_PAD_FEC_TX_CLK__USB_TOP_USBH2_DIR			0x2e0 0x744 0x9ec 0x3 0x1
+#define MX35_PAD_FEC_TX_CLK__CSPI2_MOSI				0x2e0 0x744 0x7ec 0x4 0x3
+#define MX35_PAD_FEC_TX_CLK__GPIO3_6				0x2e0 0x744 0x90c 0x5 0x1
+#define MX35_PAD_FEC_TX_CLK__IPU_DISPB_D12_VSYNC		0x2e0 0x744 0x928 0x6 0x5
+#define MX35_PAD_FEC_TX_CLK__ARM11P_TOP_EVNTBUS_0		0x2e0 0x744 0x000 0x7 0x0
+#define MX35_PAD_FEC_RX_CLK__FEC_RX_CLK				0x2e4 0x748 0x000 0x0 0x0
+#define MX35_PAD_FEC_RX_CLK__ESDHC1_DAT5			0x2e4 0x748 0x808 0x1 0x1
+#define MX35_PAD_FEC_RX_CLK__UART3_TXD_MUX			0x2e4 0x748 0x000 0x2 0x0
+#define MX35_PAD_FEC_RX_CLK__USB_TOP_USBH2_STP			0x2e4 0x748 0x000 0x3 0x0
+#define MX35_PAD_FEC_RX_CLK__CSPI2_MISO				0x2e4 0x748 0x7e8 0x4 0x3
+#define MX35_PAD_FEC_RX_CLK__GPIO3_7				0x2e4 0x748 0x910 0x5 0x1
+#define MX35_PAD_FEC_RX_CLK__IPU_DISPB_SD_D_I			0x2e4 0x748 0x92c 0x6 0x4
+#define MX35_PAD_FEC_RX_CLK__ARM11P_TOP_EVNTBUS_1		0x2e4 0x748 0x000 0x7 0x0
+#define MX35_PAD_FEC_RX_DV__FEC_RX_DV				0x2e8 0x74c 0x000 0x0 0x0
+#define MX35_PAD_FEC_RX_DV__ESDHC1_DAT6				0x2e8 0x74c 0x80c 0x1 0x1
+#define MX35_PAD_FEC_RX_DV__UART3_RTS				0x2e8 0x74c 0x99c 0x2 0x2
+#define MX35_PAD_FEC_RX_DV__USB_TOP_USBH2_NXT			0x2e8 0x74c 0x9f0 0x3 0x1
+#define MX35_PAD_FEC_RX_DV__CSPI2_SCLK				0x2e8 0x74c 0x7e0 0x4 0x3
+#define MX35_PAD_FEC_RX_DV__GPIO3_8				0x2e8 0x74c 0x914 0x5 0x1
+#define MX35_PAD_FEC_RX_DV__IPU_DISPB_SD_CLK			0x2e8 0x74c 0x000 0x6 0x0
+#define MX35_PAD_FEC_RX_DV__ARM11P_TOP_EVNTBUS_2		0x2e8 0x74c 0x000 0x7 0x0
+#define MX35_PAD_FEC_COL__FEC_COL				0x2ec 0x750 0x000 0x0 0x0
+#define MX35_PAD_FEC_COL__ESDHC1_DAT7				0x2ec 0x750 0x810 0x1 0x1
+#define MX35_PAD_FEC_COL__UART3_CTS				0x2ec 0x750 0x000 0x2 0x0
+#define MX35_PAD_FEC_COL__USB_TOP_USBH2_DATA_0			0x2ec 0x750 0x9cc 0x3 0x1
+#define MX35_PAD_FEC_COL__CSPI2_RDY				0x2ec 0x750 0x7e4 0x4 0x3
+#define MX35_PAD_FEC_COL__GPIO3_9				0x2ec 0x750 0x918 0x5 0x1
+#define MX35_PAD_FEC_COL__IPU_DISPB_SER_RS			0x2ec 0x750 0x000 0x6 0x0
+#define MX35_PAD_FEC_COL__ARM11P_TOP_EVNTBUS_3			0x2ec 0x750 0x000 0x7 0x0
+#define MX35_PAD_FEC_RDATA0__FEC_RDATA_0			0x2f0 0x754 0x000 0x0 0x0
+#define MX35_PAD_FEC_RDATA0__PWM_PWMO				0x2f0 0x754 0x000 0x1 0x0
+#define MX35_PAD_FEC_RDATA0__UART3_DTR				0x2f0 0x754 0x000 0x2 0x0
+#define MX35_PAD_FEC_RDATA0__USB_TOP_USBH2_DATA_1		0x2f0 0x754 0x9d0 0x3 0x1
+#define MX35_PAD_FEC_RDATA0__CSPI2_SS0				0x2f0 0x754 0x7f0 0x4 0x2
+#define MX35_PAD_FEC_RDATA0__GPIO3_10				0x2f0 0x754 0x8ec 0x5 0x1
+#define MX35_PAD_FEC_RDATA0__IPU_DISPB_CS1			0x2f0 0x754 0x000 0x6 0x0
+#define MX35_PAD_FEC_RDATA0__ARM11P_TOP_EVNTBUS_4		0x2f0 0x754 0x000 0x7 0x0
+#define MX35_PAD_FEC_TDATA0__FEC_TDATA_0			0x2f4 0x758 0x000 0x0 0x0
+#define MX35_PAD_FEC_TDATA0__SPDIF_SPDIF_OUT1			0x2f4 0x758 0x000 0x1 0x0
+#define MX35_PAD_FEC_TDATA0__UART3_DSR				0x2f4 0x758 0x000 0x2 0x0
+#define MX35_PAD_FEC_TDATA0__USB_TOP_USBH2_DATA_2		0x2f4 0x758 0x9d4 0x3 0x1
+#define MX35_PAD_FEC_TDATA0__CSPI2_SS1				0x2f4 0x758 0x7f4 0x4 0x2
+#define MX35_PAD_FEC_TDATA0__GPIO3_11				0x2f4 0x758 0x8f0 0x5 0x1
+#define MX35_PAD_FEC_TDATA0__IPU_DISPB_CS0			0x2f4 0x758 0x000 0x6 0x0
+#define MX35_PAD_FEC_TDATA0__ARM11P_TOP_EVNTBUS_5		0x2f4 0x758 0x000 0x7 0x0
+#define MX35_PAD_FEC_TX_EN__FEC_TX_EN				0x2f8 0x75c 0x000 0x0 0x0
+#define MX35_PAD_FEC_TX_EN__SPDIF_SPDIF_IN1			0x2f8 0x75c 0x998 0x1 0x3
+#define MX35_PAD_FEC_TX_EN__UART3_RI				0x2f8 0x75c 0x000 0x2 0x0
+#define MX35_PAD_FEC_TX_EN__USB_TOP_USBH2_DATA_3		0x2f8 0x75c 0x9d8 0x3 0x1
+#define MX35_PAD_FEC_TX_EN__GPIO3_12				0x2f8 0x75c 0x8f4 0x5 0x1
+#define MX35_PAD_FEC_TX_EN__IPU_DISPB_PAR_RS			0x2f8 0x75c 0x000 0x6 0x0
+#define MX35_PAD_FEC_TX_EN__ARM11P_TOP_EVNTBUS_6		0x2f8 0x75c 0x000 0x7 0x0
+#define MX35_PAD_FEC_MDC__FEC_MDC				0x2fc 0x760 0x000 0x0 0x0
+#define MX35_PAD_FEC_MDC__CAN2_TXCAN				0x2fc 0x760 0x000 0x1 0x0
+#define MX35_PAD_FEC_MDC__UART3_DCD				0x2fc 0x760 0x000 0x2 0x0
+#define MX35_PAD_FEC_MDC__USB_TOP_USBH2_DATA_4			0x2fc 0x760 0x9dc 0x3 0x1
+#define MX35_PAD_FEC_MDC__GPIO3_13				0x2fc 0x760 0x8f8 0x5 0x1
+#define MX35_PAD_FEC_MDC__IPU_DISPB_WR				0x2fc 0x760 0x000 0x6 0x0
+#define MX35_PAD_FEC_MDC__ARM11P_TOP_EVNTBUS_7			0x2fc 0x760 0x000 0x7 0x0
+#define MX35_PAD_FEC_MDIO__FEC_MDIO				0x300 0x764 0x000 0x0 0x0
+#define MX35_PAD_FEC_MDIO__CAN2_RXCAN				0x300 0x764 0x7cc 0x1 0x2
+#define MX35_PAD_FEC_MDIO__USB_TOP_USBH2_DATA_5			0x300 0x764 0x9e0 0x3 0x1
+#define MX35_PAD_FEC_MDIO__GPIO3_14				0x300 0x764 0x8fc 0x5 0x1
+#define MX35_PAD_FEC_MDIO__IPU_DISPB_RD				0x300 0x764 0x000 0x6 0x0
+#define MX35_PAD_FEC_MDIO__ARM11P_TOP_EVNTBUS_8			0x300 0x764 0x000 0x7 0x0
+#define MX35_PAD_FEC_TX_ERR__FEC_TX_ERR				0x304 0x768 0x000 0x0 0x0
+#define MX35_PAD_FEC_TX_ERR__OWIRE_LINE				0x304 0x768 0x990 0x1 0x2
+#define MX35_PAD_FEC_TX_ERR__SPDIF_SPDIF_EXTCLK			0x304 0x768 0x994 0x2 0x4
+#define MX35_PAD_FEC_TX_ERR__USB_TOP_USBH2_DATA_6		0x304 0x768 0x9e4 0x3 0x1
+#define MX35_PAD_FEC_TX_ERR__GPIO3_15				0x304 0x768 0x900 0x5 0x1
+#define MX35_PAD_FEC_TX_ERR__IPU_DISPB_D0_VSYNC			0x304 0x768 0x924 0x6 0x3
+#define MX35_PAD_FEC_TX_ERR__ARM11P_TOP_EVNTBUS_9		0x304 0x768 0x000 0x7 0x0
+#define MX35_PAD_FEC_RX_ERR__FEC_RX_ERR				0x308 0x76c 0x000 0x0 0x0
+#define MX35_PAD_FEC_RX_ERR__IPU_CSI_D_0			0x308 0x76c 0x930 0x1 0x3
+#define MX35_PAD_FEC_RX_ERR__USB_TOP_USBH2_DATA_7		0x308 0x76c 0x9e8 0x3 0x1
+#define MX35_PAD_FEC_RX_ERR__KPP_COL_4				0x308 0x76c 0x960 0x4 0x1
+#define MX35_PAD_FEC_RX_ERR__GPIO3_16				0x308 0x76c 0x000 0x5 0x0
+#define MX35_PAD_FEC_RX_ERR__IPU_DISPB_SD_D_IO			0x308 0x76c 0x92c 0x6 0x5
+#define MX35_PAD_FEC_CRS__FEC_CRS				0x30c 0x770 0x000 0x0 0x0
+#define MX35_PAD_FEC_CRS__IPU_CSI_D_1				0x30c 0x770 0x934 0x1 0x3
+#define MX35_PAD_FEC_CRS__USB_TOP_USBH2_PWR			0x30c 0x770 0x000 0x3 0x0
+#define MX35_PAD_FEC_CRS__KPP_COL_5				0x30c 0x770 0x964 0x4 0x1
+#define MX35_PAD_FEC_CRS__GPIO3_17				0x30c 0x770 0x000 0x5 0x0
+#define MX35_PAD_FEC_CRS__IPU_FLASH_STROBE			0x30c 0x770 0x000 0x6 0x0
+#define MX35_PAD_FEC_RDATA1__FEC_RDATA_1			0x310 0x774 0x000 0x0 0x0
+#define MX35_PAD_FEC_RDATA1__IPU_CSI_D_2			0x310 0x774 0x938 0x1 0x4
+#define MX35_PAD_FEC_RDATA1__AUDMUX_AUD6_RXC			0x310 0x774 0x000 0x2 0x0
+#define MX35_PAD_FEC_RDATA1__USB_TOP_USBH2_OC			0x310 0x774 0x9f4 0x3 0x2
+#define MX35_PAD_FEC_RDATA1__KPP_COL_6				0x310 0x774 0x968 0x4 0x1
+#define MX35_PAD_FEC_RDATA1__GPIO3_18				0x310 0x774 0x000 0x5 0x0
+#define MX35_PAD_FEC_RDATA1__IPU_DISPB_BE0			0x310 0x774 0x000 0x6 0x0
+#define MX35_PAD_FEC_TDATA1__FEC_TDATA_1			0x314 0x778 0x000 0x0 0x0
+#define MX35_PAD_FEC_TDATA1__IPU_CSI_D_3			0x314 0x778 0x93c 0x1 0x4
+#define MX35_PAD_FEC_TDATA1__AUDMUX_AUD6_RXFS			0x314 0x778 0x7bc 0x2 0x1
+#define MX35_PAD_FEC_TDATA1__KPP_COL_7				0x314 0x778 0x96c 0x4 0x1
+#define MX35_PAD_FEC_TDATA1__GPIO3_19				0x314 0x778 0x000 0x5 0x0
+#define MX35_PAD_FEC_TDATA1__IPU_DISPB_BE1			0x314 0x778 0x000 0x6 0x0
+#define MX35_PAD_FEC_RDATA2__FEC_RDATA_2			0x318 0x77c 0x000 0x0 0x0
+#define MX35_PAD_FEC_RDATA2__IPU_CSI_D_4			0x318 0x77c 0x940 0x1 0x3
+#define MX35_PAD_FEC_RDATA2__AUDMUX_AUD6_TXD			0x318 0x77c 0x7b4 0x2 0x1
+#define MX35_PAD_FEC_RDATA2__KPP_ROW_4				0x318 0x77c 0x980 0x4 0x1
+#define MX35_PAD_FEC_RDATA2__GPIO3_20				0x318 0x77c 0x000 0x5 0x0
+#define MX35_PAD_FEC_TDATA2__FEC_TDATA_2			0x31c 0x780 0x000 0x0 0x0
+#define MX35_PAD_FEC_TDATA2__IPU_CSI_D_5			0x31c 0x780 0x944 0x1 0x3
+#define MX35_PAD_FEC_TDATA2__AUDMUX_AUD6_RXD			0x31c 0x780 0x7b0 0x2 0x1
+#define MX35_PAD_FEC_TDATA2__KPP_ROW_5				0x31c 0x780 0x984 0x4 0x1
+#define MX35_PAD_FEC_TDATA2__GPIO3_21				0x31c 0x780 0x000 0x5 0x0
+#define MX35_PAD_FEC_RDATA3__FEC_RDATA_3			0x320 0x784 0x000 0x0 0x0
+#define MX35_PAD_FEC_RDATA3__IPU_CSI_D_6			0x320 0x784 0x948 0x1 0x3
+#define MX35_PAD_FEC_RDATA3__AUDMUX_AUD6_TXC			0x320 0x784 0x7c0 0x2 0x1
+#define MX35_PAD_FEC_RDATA3__KPP_ROW_6				0x320 0x784 0x988 0x4 0x1
+#define MX35_PAD_FEC_RDATA3__GPIO3_22				0x320 0x784 0x000 0x6 0x0
+#define MX35_PAD_FEC_TDATA3__FEC_TDATA_3			0x324 0x788 0x000 0x0 0x0
+#define MX35_PAD_FEC_TDATA3__IPU_CSI_D_7			0x324 0x788 0x94c 0x1 0x3
+#define MX35_PAD_FEC_TDATA3__AUDMUX_AUD6_TXFS			0x324 0x788 0x7c4 0x2 0x1
+#define MX35_PAD_FEC_TDATA3__KPP_ROW_7				0x324 0x788 0x98c 0x4 0x1
+#define MX35_PAD_FEC_TDATA3__GPIO3_23				0x324 0x788 0x000 0x5 0x0
+#define MX35_PAD_EXT_ARMCLK__CCM_EXT_ARMCLK			0x000 0x78c 0x000 0x0 0x0
+#define MX35_PAD_TEST_MODE__TCU_TEST_MODE			0x000 0x790 0x000 0x0 0x0
+
+#endif /* __DTS_IMX35_PINFUNC_H */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/imx50-pinfunc.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/imx50-pinfunc.h
new file mode 100644
index 0000000000000000000000000000000000000000..43863347362e83adefbff9ebecc018a3e3ae220c
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/imx50-pinfunc.h
@@ -0,0 +1,923 @@
+/*
+ * Copyright 2013 Greg Ungerer <gerg@uclinux.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __DTS_IMX50_PINFUNC_H
+#define __DTS_IMX50_PINFUNC_H
+
+/*
+ * The pin function ID is a tuple of
+ * <mux_reg conf_reg input_reg mux_mode input_val>
+ */
+#define MX50_PAD_KEY_COL0__KPP_COL_0				0x020 0x2cc 0x000 0x0 0x0
+#define MX50_PAD_KEY_COL0__GPIO4_0				0x020 0x2cc 0x000 0x1 0x0
+#define MX50_PAD_KEY_COL0__EIM_NANDF_CLE			0x020 0x2cc 0x000 0x2 0x0
+#define MX50_PAD_KEY_COL0__CTI_TRIGIN7				0x020 0x2cc 0x000 0x6 0x0
+#define MX50_PAD_KEY_COL0__USBPHY1_TXREADY			0x020 0x2cc 0x000 0x7 0x0
+#define MX50_PAD_KEY_ROW0__KPP_ROW_0				0x024 0x2d0 0x000 0x0 0x0
+#define MX50_PAD_KEY_ROW0__GPIO4_1				0x024 0x2d0 0x000 0x1 0x0
+#define MX50_PAD_KEY_ROW0__EIM_NANDF_ALE			0x024 0x2d0 0x000 0x2 0x0
+#define MX50_PAD_KEY_ROW0__CTI_TRIGIN_ACK7			0x024 0x2d0 0x000 0x6 0x0
+#define MX50_PAD_KEY_ROW0__USBPHY1_RXVALID			0x024 0x2d0 0x000 0x7 0x0
+#define MX50_PAD_KEY_COL1__KPP_COL_1				0x028 0x2d4 0x000 0x0 0x0
+#define MX50_PAD_KEY_COL1__GPIO4_2				0x028 0x2d4 0x000 0x1 0x0
+#define MX50_PAD_KEY_COL1__EIM_NANDF_CEN_0			0x028 0x2d4 0x000 0x2 0x0
+#define MX50_PAD_KEY_COL1__CTI_TRIGOUT_ACK6			0x028 0x2d4 0x000 0x6 0x0
+#define MX50_PAD_KEY_COL1__USBPHY1_RXACTIVE			0x028 0x2d4 0x000 0x7 0x0
+#define MX50_PAD_KEY_ROW1__KPP_ROW_1				0x02c 0x2d8 0x000 0x0 0x0
+#define MX50_PAD_KEY_ROW1__GPIO4_3				0x02c 0x2d8 0x000 0x1 0x0
+#define MX50_PAD_KEY_ROW1__EIM_NANDF_CEN_1			0x02c 0x2d8 0x000 0x2 0x0
+#define MX50_PAD_KEY_ROW1__CTI_TRIGOUT_ACK7			0x02c 0x2d8 0x000 0x6 0x0
+#define MX50_PAD_KEY_ROW1__USBPHY1_RXERROR			0x02c 0x2d8 0x000 0x7 0x0
+#define MX50_PAD_KEY_COL2__KPP_COL_2				0x030 0x2dc 0x000 0x0 0x0
+#define MX50_PAD_KEY_COL2__GPIO4_4				0x030 0x2dc 0x000 0x1 0x0
+#define MX50_PAD_KEY_COL2__EIM_NANDF_CEN_2			0x030 0x2dc 0x000 0x2 0x0
+#define MX50_PAD_KEY_COL2__CTI_TRIGOUT6				0x030 0x2dc 0x000 0x6 0x0
+#define MX50_PAD_KEY_COL2__USBPHY1_SIECLOCK			0x030 0x2dc 0x000 0x7 0x0
+#define MX50_PAD_KEY_ROW2__KPP_ROW_2				0x034 0x2e0 0x000 0x0 0x0
+#define MX50_PAD_KEY_ROW2__GPIO4_5				0x034 0x2e0 0x000 0x1 0x0
+#define MX50_PAD_KEY_ROW2__EIM_NANDF_CEN_3			0x034 0x2e0 0x000 0x2 0x0
+#define MX50_PAD_KEY_ROW2__CTI_TRIGOUT7				0x034 0x2e0 0x000 0x6 0x0
+#define MX50_PAD_KEY_ROW2__USBPHY1_LINESTATE_0			0x034 0x2e0 0x000 0x7 0x0
+#define MX50_PAD_KEY_COL3__KPP_COL_3				0x038 0x2e4 0x000 0x0 0x0
+#define MX50_PAD_KEY_COL3__GPIO4_6				0x038 0x2e4 0x000 0x1 0x0
+#define MX50_PAD_KEY_COL3__EIM_NANDF_READY0			0x038 0x2e4 0x7b4 0x2 0x0
+#define MX50_PAD_KEY_COL3__SDMA_EXT_EVENT_0			0x038 0x2e4 0x7b8 0x6 0x0
+#define MX50_PAD_KEY_COL3__USBPHY1_LINESTATE_1			0x038 0x2e4 0x000 0x7 0x0
+#define MX50_PAD_KEY_ROW3__KPP_ROW_3				0x03c 0x2e8 0x000 0x0 0x0
+#define MX50_PAD_KEY_ROW3__GPIO4_7				0x03c 0x2e8 0x000 0x1 0x0
+#define MX50_PAD_KEY_ROW3__EIM_NANDF_DQS			0x03c 0x2e8 0x7b0 0x2 0x0
+#define MX50_PAD_KEY_ROW3__SDMA_EXT_EVENT_1			0x03c 0x2e8 0x7bc 0x6 0x0
+#define MX50_PAD_KEY_ROW3__USBPHY1_VBUSVALID			0x03c 0x2e8 0x000 0x7 0x0
+#define MX50_PAD_I2C1_SCL__I2C1_SCL				0x040 0x2ec 0x000 0x0 0x0
+#define MX50_PAD_I2C1_SCL__GPIO6_18				0x040 0x2ec 0x000 0x1 0x0
+#define MX50_PAD_I2C1_SCL__UART2_TXD_MUX			0x040 0x2ec 0x7cc 0x2 0x0
+#define MX50_PAD_I2C1_SDA__I2C1_SDA				0x044 0x2f0 0x000 0x0 0x0
+#define MX50_PAD_I2C1_SDA__GPIO6_19				0x044 0x2f0 0x000 0x1 0x0
+#define MX50_PAD_I2C1_SDA__UART2_RXD_MUX			0x044 0x2f0 0x7cc 0x2 0x1
+#define MX50_PAD_I2C2_SCL__I2C2_SCL				0x048 0x2f4 0x000 0x0 0x0
+#define MX50_PAD_I2C2_SCL__GPIO6_20				0x048 0x2f4 0x000 0x1 0x0
+#define MX50_PAD_I2C2_SCL__UART2_CTS				0x048 0x2f4 0x000 0x2 0x0
+#define MX50_PAD_I2C2_SDA__I2C2_SDA				0x04c 0x2f8 0x000 0x0 0x0
+#define MX50_PAD_I2C2_SDA__GPIO6_21				0x04c 0x2f8 0x000 0x1 0x0
+#define MX50_PAD_I2C2_SDA__UART2_RTS				0x04c 0x2f8 0x7c8 0x2 0x1
+#define MX50_PAD_I2C3_SCL__I2C3_SCL				0x050 0x2fc 0x000 0x0 0x0
+#define MX50_PAD_I2C3_SCL__GPIO6_22				0x050 0x2fc 0x000 0x1 0x0
+#define MX50_PAD_I2C3_SCL__FEC_MDC				0x050 0x2fc 0x000 0x2 0x0
+#define MX50_PAD_I2C3_SCL__GPC_PMIC_RDY				0x050 0x2fc 0x000 0x3 0x0
+#define MX50_PAD_I2C3_SCL__GPT_CAPIN1				0x050 0x2fc 0x000 0x5 0x0
+#define MX50_PAD_I2C3_SCL__OBSERVE_MUX_OBSRV_INT_OUT0		0x050 0x2fc 0x000 0x6 0x0
+#define MX50_PAD_I2C3_SCL__USBOH1_USBOTG_OC			0x050 0x2fc 0x7e8 0x7 0x0
+#define MX50_PAD_I2C3_SDA__I2C3_SDA				0x054 0x300 0x000 0x0 0x0
+#define MX50_PAD_I2C3_SDA__GPIO6_23				0x054 0x300 0x000 0x1 0x0
+#define MX50_PAD_I2C3_SDA__FEC_MDIO				0x054 0x300 0x774 0x2 0x0
+#define MX50_PAD_I2C3_SDA__TZIC_PWRFAIL_INT			0x054 0x300 0x000 0x3 0x0
+#define MX50_PAD_I2C3_SDA__SRTC_ALARM_DEB			0x054 0x300 0x000 0x4 0x0
+#define MX50_PAD_I2C3_SDA__GPT_CAPIN2				0x054 0x300 0x000 0x5 0x0
+#define MX50_PAD_I2C3_SDA__OBSERVE_MUX_OBSRV_INT_OUT1		0x054 0x300 0x000 0x6 0x0
+#define MX50_PAD_I2C3_SDA__USBOH1_USBOTG_PWR			0x054 0x300 0x000 0x7 0x0
+#define MX50_PAD_PWM1__PWM1_PWMO				0x058 0x304 0x000 0x0 0x0
+#define MX50_PAD_PWM1__GPIO6_24					0x058 0x304 0x000 0x1 0x0
+#define MX50_PAD_PWM1__USBOH1_USBOTG_OC				0x058 0x304 0x7e8 0x2 0x1
+#define MX50_PAD_PWM1__GPT_CMPOUT1				0x058 0x304 0x000 0x5 0x0
+#define MX50_PAD_PWM1__OBSERVE_MUX_OBSRV_INT_OUT2		0x058 0x304 0x000 0x6 0x0
+#define MX50_PAD_PWM1__SJC_FAIL					0x058 0x304 0x000 0x7 0x0
+#define MX50_PAD_PWM2__PWM2_PWMO				0x05c 0x308 0x000 0x0 0x0
+#define MX50_PAD_PWM2__GPIO6_25					0x05c 0x308 0x000 0x1 0x0
+#define MX50_PAD_PWM2__USBOH1_USBOTG_PWR			0x05c 0x308 0x000 0x2 0x0
+#define MX50_PAD_PWM2__GPT_CMPOUT2				0x05c 0x308 0x000 0x5 0x0
+#define MX50_PAD_PWM2__OBSERVE_MUX_OBSRV_INT_OUT3		0x05c 0x308 0x000 0x6 0x0
+#define MX50_PAD_PWM2__SRC_ANY_PU_RST				0x05c 0x308 0x000 0x7 0x0
+#define MX50_PAD_OWIRE__OWIRE_LINE				0x060 0x30c 0x000 0x0 0x0
+#define MX50_PAD_OWIRE__GPIO6_26				0x060 0x30c 0x000 0x1 0x0
+#define MX50_PAD_OWIRE__USBOH1_USBH1_OC				0x060 0x30c 0x000 0x2 0x0
+#define MX50_PAD_OWIRE__CCM_SSI_EXT1_CLK			0x060 0x30c 0x000 0x3 0x0
+#define MX50_PAD_OWIRE__EPDC_PWRIRQ				0x060 0x30c 0x000 0x4 0x0
+#define MX50_PAD_OWIRE__GPT_CMPOUT3				0x060 0x30c 0x000 0x5 0x0
+#define MX50_PAD_OWIRE__OBSERVE_MUX_OBSRV_INT_OUT4		0x060 0x30c 0x000 0x6 0x0
+#define MX50_PAD_OWIRE__SJC_JTAG_ACT				0x060 0x30c 0x000 0x7 0x0
+#define MX50_PAD_EPITO__EPIT1_EPITO				0x064 0x310 0x000 0x0 0x0
+#define MX50_PAD_EPITO__GPIO6_27				0x064 0x310 0x000 0x1 0x0
+#define MX50_PAD_EPITO__USBOH1_USBH1_PWR			0x064 0x310 0x000 0x2 0x0
+#define MX50_PAD_EPITO__CCM_SSI_EXT2_CLK			0x064 0x310 0x000 0x3 0x0
+#define MX50_PAD_EPITO__DPLLIP1_TOG_EN				0x064 0x310 0x000 0x4 0x0
+#define MX50_PAD_EPITO__GPT_CLK_IN				0x064 0x310 0x000 0x5 0x0
+#define MX50_PAD_EPITO__PMU_IRQ_B				0x064 0x310 0x000 0x6 0x0
+#define MX50_PAD_EPITO__SJC_DE_B				0x064 0x310 0x000 0x7 0x0
+#define MX50_PAD_WDOG__WDOG1_WDOG_B				0x068 0x314 0x000 0x0 0x0
+#define MX50_PAD_WDOG__GPIO6_28					0x068 0x314 0x000 0x1 0x0
+#define MX50_PAD_WDOG__WDOG1_WDOG_RST_B_DEB			0x068 0x314 0x000 0x2 0x0
+#define MX50_PAD_WDOG__CCM_XTAL32K				0x068 0x314 0x000 0x6 0x0
+#define MX50_PAD_WDOG__SJC_DONE					0x068 0x314 0x000 0x7 0x0
+#define MX50_PAD_SSI_TXFS__AUDMUX_AUD3_TXFS			0x06c 0x318 0x000 0x0 0x0
+#define MX50_PAD_SSI_TXFS__GPIO6_0				0x06c 0x318 0x000 0x1 0x0
+#define MX50_PAD_SSI_TXFS__SRC_BT_FUSE_RSV_1			0x06c 0x318 0x000 0x6 0x0
+#define MX50_PAD_SSI_TXFS__USBPHY1_DATAOUT_8			0x06c 0x318 0x000 0x7 0x0
+#define MX50_PAD_SSI_TXC__AUDMUX_AUD3_TXC			0x070 0x31c 0x000 0x0 0x0
+#define MX50_PAD_SSI_TXC__GPIO6_1				0x070 0x31c 0x000 0x1 0x0
+#define MX50_PAD_SSI_TXC__SRC_BT_FUSE_RSV_0			0x070 0x31c 0x000 0x6 0x0
+#define MX50_PAD_SSI_TXC__USBPHY1_DATAOUT_9			0x070 0x31c 0x000 0x7 0x0
+#define MX50_PAD_SSI_TXD__AUDMUX_AUD3_TXD			0x074 0x320 0x000 0x0 0x0
+#define MX50_PAD_SSI_TXD__GPIO6_2				0x074 0x320 0x000 0x1 0x0
+#define MX50_PAD_SSI_TXD__CSPI_RDY				0x074 0x320 0x6e8 0x4 0x0
+#define MX50_PAD_SSI_TXD__USBPHY1_DATAOUT_10			0x074 0x320 0x000 0x7 0x0
+#define MX50_PAD_SSI_RXD__AUDMUX_AUD3_RXD			0x078 0x324 0x000 0x0 0x0
+#define MX50_PAD_SSI_RXD__GPIO6_3				0x078 0x324 0x000 0x1 0x0
+#define MX50_PAD_SSI_RXD__CSPI_SS3				0x078 0x324 0x6f4 0x4 0x0
+#define MX50_PAD_SSI_RXD__USBPHY1_DATAOUT_11			0x078 0x324 0x000 0x7 0x0
+#define MX50_PAD_SSI_RXFS__AUDMUX_AUD3_RXFS			0x07c 0x328 0x000 0x0 0x0
+#define MX50_PAD_SSI_RXFS__GPIO6_4				0x07c 0x328 0x000 0x1 0x0
+#define MX50_PAD_SSI_RXFS__UART5_TXD_MUX			0x07c 0x328 0x7e4 0x2 0x0
+#define MX50_PAD_SSI_RXFS__EIM_WEIM_D_6				0x07c 0x328 0x804 0x3 0x0
+#define MX50_PAD_SSI_RXFS__CSPI_SS2				0x07c 0x328 0x6f0 0x4 0x0
+#define MX50_PAD_SSI_RXFS__FEC_COL				0x07c 0x328 0x770 0x5 0x0
+#define MX50_PAD_SSI_RXFS__FEC_MDC				0x07c 0x328 0x000 0x6 0x0
+#define MX50_PAD_SSI_RXFS__USBPHY1_DATAOUT_12			0x07c 0x328 0x000 0x7 0x0
+#define MX50_PAD_SSI_RXC__AUDMUX_AUD3_RXC			0x080 0x32c 0x000 0x0 0x0
+#define MX50_PAD_SSI_RXC__GPIO6_5				0x080 0x32c 0x000 0x1 0x0
+#define MX50_PAD_SSI_RXC__UART5_RXD_MUX				0x080 0x32c 0x7e4 0x2 0x1
+#define MX50_PAD_SSI_RXC__EIM_WEIM_D_7				0x080 0x32c 0x808 0x3 0x0
+#define MX50_PAD_SSI_RXC__CSPI_SS1				0x080 0x32c 0x6ec 0x4 0x0
+#define MX50_PAD_SSI_RXC__FEC_RX_CLK				0x080 0x32c 0x780 0x5 0x0
+#define MX50_PAD_SSI_RXC__FEC_MDIO				0x080 0x32c 0x774 0x6 0x1
+#define MX50_PAD_SSI_RXC__USBPHY1_DATAOUT_13			0x080 0x32c 0x000 0x7 0x0
+#define MX50_PAD_UART1_TXD__UART1_TXD_MUX			0x084 0x330 0x7c4 0x0 0x0
+#define MX50_PAD_UART1_TXD__GPIO6_6				0x084 0x330 0x000 0x1 0x0
+#define MX50_PAD_UART1_TXD__USBPHY1_DATAOUT_14			0x084 0x330 0x000 0x7 0x0
+#define MX50_PAD_UART1_RXD__UART1_RXD_MUX			0x088 0x334 0x7c4 0x0 0x1
+#define MX50_PAD_UART1_RXD__GPIO6_7				0x088 0x334 0x000 0x1 0x0
+#define MX50_PAD_UART1_RXD__USBPHY1_DATAOUT_15			0x088 0x334 0x000 0x7 0x0
+#define MX50_PAD_UART1_CTS__UART1_CTS				0x08c 0x338 0x000 0x0 0x0
+#define MX50_PAD_UART1_CTS__GPIO6_8				0x08c 0x338 0x000 0x1 0x0
+#define MX50_PAD_UART1_CTS__UART5_TXD_MUX			0x08c 0x338 0x7e4 0x2 0x2
+#define MX50_PAD_UART1_CTS__ESDHC4_DAT4				0x08c 0x338 0x760 0x4 0x0
+#define MX50_PAD_UART1_CTS__ESDHC4_CMD				0x08c 0x338 0x74c 0x5 0x0
+#define MX50_PAD_UART1_CTS__USBPHY2_DATAOUT_8			0x08c 0x338 0x000 0x7 0x0
+#define MX50_PAD_UART1_RTS__UART1_RTS				0x090 0x33c 0x7c0 0x0 0x3
+#define MX50_PAD_UART1_RTS__GPIO6_9				0x090 0x33c 0x000 0x1 0x0
+#define MX50_PAD_UART1_RTS__UART5_RXD_MUX			0x090 0x33c 0x7e4 0x2 0x3
+#define MX50_PAD_UART1_RTS__ESDHC4_DAT5				0x090 0x33c 0x764 0x4 0x0
+#define MX50_PAD_UART1_RTS__ESDHC4_CLK				0x090 0x33c 0x748 0x5 0x0
+#define MX50_PAD_UART1_RTS__USBPHY2_DATAOUT_9			0x090 0x33c 0x000 0x7 0x0
+#define MX50_PAD_UART2_TXD__UART2_TXD_MUX			0x094 0x340 0x7cc 0x0 0x2
+#define MX50_PAD_UART2_TXD__GPIO6_10				0x094 0x340 0x000 0x1 0x0
+#define MX50_PAD_UART2_TXD__ESDHC4_DAT6				0x094 0x340 0x768 0x4 0x0
+#define MX50_PAD_UART2_TXD__ESDHC4_DAT4				0x094 0x340 0x760 0x5 0x1
+#define MX50_PAD_UART2_TXD__USBPHY2_DATAOUT_10			0x094 0x340 0x000 0x7 0x0
+#define MX50_PAD_UART2_RXD__UART2_RXD_MUX			0x098 0x344 0x7cc 0x0 0x3
+#define MX50_PAD_UART2_RXD__GPIO6_11				0x098 0x344 0x000 0x1 0x0
+#define MX50_PAD_UART2_RXD__ESDHC4_DAT7				0x098 0x344 0x76c 0x4 0x0
+#define MX50_PAD_UART2_RXD__ESDHC4_DAT5				0x098 0x344 0x764 0x5 0x1
+#define MX50_PAD_UART2_RXD__USBPHY2_DATAOUT_11			0x098 0x344 0x000 0x7 0x0
+#define MX50_PAD_UART2_CTS__UART2_CTS				0x09c 0x348 0x000 0x0 0x0
+#define MX50_PAD_UART2_CTS__GPIO6_12				0x09c 0x348 0x000 0x1 0x0
+#define MX50_PAD_UART2_CTS__ESDHC4_CMD				0x09c 0x348 0x74c 0x4 0x1
+#define MX50_PAD_UART2_CTS__ESDHC4_DAT6				0x09c 0x348 0x768 0x5 0x1
+#define MX50_PAD_UART2_CTS__USBPHY2_DATAOUT_12			0x09c 0x348 0x000 0x7 0x0
+#define MX50_PAD_UART2_RTS__UART2_RTS				0x0a0 0x34c 0x7c8 0x0 0x2
+#define MX50_PAD_UART2_RTS__GPIO6_13				0x0a0 0x34c 0x000 0x1 0x0
+#define MX50_PAD_UART2_RTS__ESDHC4_CLK				0x0a0 0x34c 0x748 0x4 0x1
+#define MX50_PAD_UART2_RTS__ESDHC4_DAT7				0x0a0 0x34c 0x76c 0x5 0x1
+#define MX50_PAD_UART2_RTS__USBPHY2_DATAOUT_13			0x0a0 0x34c 0x000 0x7 0x0
+#define MX50_PAD_UART3_TXD__UART3_TXD_MUX			0x0a4 0x350 0x7d4 0x0 0x0
+#define MX50_PAD_UART3_TXD__GPIO6_14				0x0a4 0x350 0x000 0x1 0x0
+#define MX50_PAD_UART3_TXD__ESDHC1_DAT4				0x0a4 0x350 0x000 0x3 0x0
+#define MX50_PAD_UART3_TXD__ESDHC4_DAT0				0x0a4 0x350 0x000 0x4 0x0
+#define MX50_PAD_UART3_TXD__ESDHC2_WP				0x0a4 0x350 0x744 0x5 0x0
+#define MX50_PAD_UART3_TXD__EIM_WEIM_D_12			0x0a4 0x350 0x81c 0x6 0x0
+#define MX50_PAD_UART3_TXD__USBPHY2_DATAOUT_14			0x0a4 0x350 0x000 0x7 0x0
+#define MX50_PAD_UART3_RXD__UART3_RXD_MUX			0x0a8 0x354 0x7d4 0x0 0x1
+#define MX50_PAD_UART3_RXD__GPIO6_15				0x0a8 0x354 0x000 0x1 0x0
+#define MX50_PAD_UART3_RXD__ESDHC1_DAT5				0x0a8 0x354 0x000 0x3 0x0
+#define MX50_PAD_UART3_RXD__ESDHC4_DAT1				0x0a8 0x354 0x754 0x4 0x0
+#define MX50_PAD_UART3_RXD__ESDHC2_CD				0x0a8 0x354 0x740 0x5 0x0
+#define MX50_PAD_UART3_RXD__EIM_WEIM_D_13			0x0a8 0x354 0x820 0x6 0x0
+#define MX50_PAD_UART3_RXD__USBPHY2_DATAOUT_15			0x0a8 0x354 0x000 0x7 0x0
+#define MX50_PAD_UART4_TXD__UART4_TXD_MUX			0x0ac 0x358 0x7dc 0x0 0x0
+#define MX50_PAD_UART4_TXD__GPIO6_16				0x0ac 0x358 0x000 0x1 0x0
+#define MX50_PAD_UART4_TXD__UART3_CTS				0x0ac 0x358 0x7d0 0x2 0x0
+#define MX50_PAD_UART4_TXD__ESDHC1_DAT6				0x0ac 0x358 0x000 0x3 0x0
+#define MX50_PAD_UART4_TXD__ESDHC4_DAT2				0x0ac 0x358 0x758 0x4 0x0
+#define MX50_PAD_UART4_TXD__ESDHC2_LCTL				0x0ac 0x358 0x000 0x5 0x0
+#define MX50_PAD_UART4_TXD__EIM_WEIM_D_14			0x0ac 0x358 0x824 0x6 0x0
+#define MX50_PAD_UART4_RXD__UART4_RXD_MUX			0x0b0 0x35c 0x7dc 0x0 0x1
+#define MX50_PAD_UART4_RXD__GPIO6_17				0x0b0 0x35c 0x000 0x1 0x0
+#define MX50_PAD_UART4_RXD__UART3_RTS				0x0b0 0x35c 0x7d0 0x2 0x1
+#define MX50_PAD_UART4_RXD__ESDHC1_DAT7				0x0b0 0x35c 0x000 0x3 0x0
+#define MX50_PAD_UART4_RXD__ESDHC4_DAT3				0x0b0 0x35c 0x75c 0x4 0x0
+#define MX50_PAD_UART4_RXD__ESDHC1_LCTL				0x0b0 0x35c 0x000 0x5 0x0
+#define MX50_PAD_UART4_RXD__EIM_WEIM_D_15			0x0b0 0x35c 0x828 0x6 0x0
+#define MX50_PAD_CSPI_SCLK__CSPI_SCLK				0x0b4 0x360 0x000 0x0 0x0
+#define MX50_PAD_CSPI_SCLK__GPIO4_8				0x0b4 0x360 0x000 0x1 0x0
+#define MX50_PAD_CSPI_MOSI__CSPI_MOSI				0x0b8 0x364 0x000 0x0 0x0
+#define MX50_PAD_CSPI_MOSI__GPIO4_9				0x0b8 0x364 0x000 0x1 0x0
+#define MX50_PAD_CSPI_MISO__CSPI_MISO				0x0bc 0x368 0x000 0x0 0x0
+#define MX50_PAD_CSPI_MISO__GPIO4_10				0x0bc 0x368 0x000 0x1 0x0
+#define MX50_PAD_CSPI_SS0__CSPI_SS0				0x0c0 0x36c 0x000 0x0 0x0
+#define MX50_PAD_CSPI_SS0__GPIO4_11				0x0c0 0x36c 0x000 0x1 0x0
+#define MX50_PAD_ECSPI1_SCLK__ECSPI1_SCLK			0x0c4 0x370 0x000 0x0 0x0
+#define MX50_PAD_ECSPI1_SCLK__GPIO4_12				0x0c4 0x370 0x000 0x1 0x0
+#define MX50_PAD_ECSPI1_SCLK__CSPI_RDY				0x0c4 0x370 0x6e8 0x2 0x1
+#define MX50_PAD_ECSPI1_SCLK__ECSPI2_RDY			0x0c4 0x370 0x000 0x3 0x0
+#define MX50_PAD_ECSPI1_SCLK__UART3_RTS				0x0c4 0x370 0x7d0 0x4 0x2
+#define MX50_PAD_ECSPI1_SCLK__EPDC_SDCE_6			0x0c4 0x370 0x000 0x5 0x0
+#define MX50_PAD_ECSPI1_SCLK__EIM_WEIM_D_8			0x0c4 0x370 0x80c 0x7 0x0
+#define MX50_PAD_ECSPI1_MOSI__ECSPI1_MOSI			0x0c8 0x374 0x000 0x0 0x0
+#define MX50_PAD_ECSPI1_MOSI__GPIO4_13				0x0c8 0x374 0x000 0x1 0x0
+#define MX50_PAD_ECSPI1_MOSI__CSPI_SS1				0x0c8 0x374 0x6ec 0x2 0x1
+#define MX50_PAD_ECSPI1_MOSI__ECSPI2_SS1			0x0c8 0x374 0x000 0x3 0x0
+#define MX50_PAD_ECSPI1_MOSI__UART3_CTS				0x0c8 0x374 0x000 0x4 0x0
+#define MX50_PAD_ECSPI1_MOSI__EPDC_SDCE_7			0x0c8 0x374 0x000 0x5 0x0
+#define MX50_PAD_ECSPI1_MOSI__EIM_WEIM_D_9			0x0c8 0x374 0x810 0x7 0x0
+#define MX50_PAD_ECSPI1_MISO__ECSPI1_MISO			0x0cc 0x378 0x000 0x0 0x0
+#define MX50_PAD_ECSPI1_MISO__GPIO4_14				0x0cc 0x378 0x000 0x1 0x0
+#define MX50_PAD_ECSPI1_MISO__CSPI_SS2				0x0cc 0x378 0x6f0 0x2 0x1
+#define MX50_PAD_ECSPI1_MISO__ECSPI2_SS2			0x0cc 0x378 0x000 0x3 0x0
+#define MX50_PAD_ECSPI1_MISO__UART4_RTS				0x0cc 0x378 0x7d8 0x4 0x0
+#define MX50_PAD_ECSPI1_MISO__EPDC_SDCE_8			0x0cc 0x378 0x000 0x5 0x0
+#define MX50_PAD_ECSPI1_MISO__EIM_WEIM_D_10			0x0cc 0x378 0x814 0x7 0x0
+#define MX50_PAD_ECSPI1_SS0__ECSPI1_SS0				0x0d0 0x37c 0x000 0x0 0x0
+#define MX50_PAD_ECSPI1_SS0__GPIO4_15				0x0d0 0x37c 0x000 0x1 0x0
+#define MX50_PAD_ECSPI1_SS0__CSPI_SS3				0x0d0 0x37c 0x6f4 0x2 0x1
+#define MX50_PAD_ECSPI1_SS0__ECSPI2_SS3				0x0d0 0x37c 0x000 0x3 0x0
+#define MX50_PAD_ECSPI1_SS0__UART4_CTS				0x0d0 0x37c 0x000 0x4 0x0
+#define MX50_PAD_ECSPI1_SS0__EPDC_SDCE_9			0x0d0 0x37c 0x000 0x5 0x0
+#define MX50_PAD_ECSPI1_SS0__EIM_WEIM_D_11			0x0d0 0x37c 0x818 0x7 0x0
+#define MX50_PAD_ECSPI2_SCLK__ECSPI2_SCLK			0x0d4 0x380 0x000 0x0 0x0
+#define MX50_PAD_ECSPI2_SCLK__GPIO4_16				0x0d4 0x380 0x000 0x1 0x0
+#define MX50_PAD_ECSPI2_SCLK__ELCDIF_WR_RWN			0x0d4 0x380 0x000 0x2 0x0
+#define MX50_PAD_ECSPI2_SCLK__ECSPI1_RDY			0x0d4 0x380 0x000 0x3 0x0
+#define MX50_PAD_ECSPI2_SCLK__UART5_RTS				0x0d4 0x380 0x7e0 0x4 0x0
+#define MX50_PAD_ECSPI2_SCLK__ELCDIF_DOTCLK			0x0d4 0x380 0x000 0x5 0x0
+#define MX50_PAD_ECSPI2_SCLK__EIM_NANDF_CEN_4			0x0d4 0x380 0x000 0x6 0x0
+#define MX50_PAD_ECSPI2_SCLK__EIM_WEIM_D_8			0x0d4 0x380 0x80c 0x7 0x1
+#define MX50_PAD_ECSPI2_MOSI__ECSPI2_MOSI			0x0d8 0x384 0x000 0x0 0x0
+#define MX50_PAD_ECSPI2_MOSI__GPIO4_17				0x0d8 0x384 0x000 0x1 0x0
+#define MX50_PAD_ECSPI2_MOSI__ELCDIF_RE_E			0x0d8 0x384 0x000 0x2 0x0
+#define MX50_PAD_ECSPI2_MOSI__ECSPI1_SS1			0x0d8 0x384 0x000 0x3 0x0
+#define MX50_PAD_ECSPI2_MOSI__UART5_CTS				0x0d8 0x384 0x7e0 0x4 0x1
+#define MX50_PAD_ECSPI2_MOSI__ELCDIF_ENABLE			0x0d8 0x384 0x000 0x5 0x0
+#define MX50_PAD_ECSPI2_MOSI__EIM_NANDF_CEN_5			0x0d8 0x384 0x000 0x6 0x0
+#define MX50_PAD_ECSPI2_MOSI__EIM_WEIM_D_9			0x0d8 0x384 0x810 0x7 0x1
+#define MX50_PAD_ECSPI2_MISO__ECSPI2_MISO			0x0dc 0x388 0x000 0x0 0x0
+#define MX50_PAD_ECSPI2_MISO__GPIO4_18				0x0dc 0x388 0x000 0x1 0x0
+#define MX50_PAD_ECSPI2_MISO__ELCDIF_RS				0x0dc 0x388 0x000 0x2 0x0
+#define MX50_PAD_ECSPI2_MISO__ECSPI1_SS2			0x0dc 0x388 0x000 0x3 0x0
+#define MX50_PAD_ECSPI2_MISO__UART5_TXD_MUX			0x0dc 0x388 0x7e4 0x4 0x4
+#define MX50_PAD_ECSPI2_MISO__ELCDIF_VSYNC			0x0dc 0x388 0x73c 0x5 0x0
+#define MX50_PAD_ECSPI2_MISO__EIM_NANDF_CEN_6			0x0dc 0x388 0x000 0x6 0x0
+#define MX50_PAD_ECSPI2_MISO__EIM_WEIM_D_10			0x0dc 0x388 0x814 0x7 0x1
+#define MX50_PAD_ECSPI2_SS0__ECSPI2_SS0				0x0e0 0x38c 0x000 0x0 0x0
+#define MX50_PAD_ECSPI2_SS0__GPIO4_19				0x0e0 0x38c 0x000 0x1 0x0
+#define MX50_PAD_ECSPI2_SS0__ELCDIF_CS				0x0e0 0x38c 0x000 0x2 0x0
+#define MX50_PAD_ECSPI2_SS0__ECSPI2_SS3				0x0e0 0x38c 0x000 0x3 0x0
+#define MX50_PAD_ECSPI2_SS0__UART5_RXD_MUX			0x0e0 0x38c 0x7e4 0x4 0x5
+#define MX50_PAD_ECSPI2_SS0__ELCDIF_HSYNC			0x0e0 0x38c 0x6f8 0x5 0x0
+#define MX50_PAD_ECSPI2_SS0__EIM_NANDF_CEN_7			0x0e0 0x38c 0x000 0x6 0x0
+#define MX50_PAD_ECSPI2_SS0__EIM_WEIM_D_11			0x0e0 0x38c 0x818 0x7 0x1
+#define MX50_PAD_SD1_CLK__ESDHC1_CLK				0x0e4 0x390 0x000 0x0 0x0
+#define MX50_PAD_SD1_CLK__GPIO5_0				0x0e4 0x390 0x000 0x1 0x0
+#define MX50_PAD_SD1_CLK__CCM_CLKO				0x0e4 0x390 0x000 0x7 0x0
+#define MX50_PAD_SD1_CMD__ESDHC1_CMD				0x0e8 0x394 0x000 0x0 0x0
+#define MX50_PAD_SD1_CMD__GPIO5_1				0x0e8 0x394 0x000 0x1 0x0
+#define MX50_PAD_SD1_CMD__CCM_CLKO2				0x0e8 0x394 0x000 0x7 0x0
+#define MX50_PAD_SD1_D0__ESDHC1_DAT0				0x0ec 0x398 0x000 0x0 0x0
+#define MX50_PAD_SD1_D0__GPIO5_2				0x0ec 0x398 0x000 0x1 0x0
+#define MX50_PAD_SD1_D0__CCM_PLL1_BYP				0x0ec 0x398 0x6dc 0x7 0x0
+#define MX50_PAD_SD1_D1__ESDHC1_DAT1				0x0f0 0x39c 0x000 0x0 0x0
+#define MX50_PAD_SD1_D1__GPIO5_3				0x0f0 0x39c 0x000 0x1 0x0
+#define MX50_PAD_SD1_D1__CCM_PLL2_BYP				0x0f0 0x39c 0x000 0x7 0x0
+#define MX50_PAD_SD1_D2__ESDHC1_DAT2				0x0f4 0x3a0 0x000 0x0 0x0
+#define MX50_PAD_SD1_D2__GPIO5_4				0x0f4 0x3a0 0x000 0x1 0x0
+#define MX50_PAD_SD1_D2__CCM_PLL3_BYP				0x0f4 0x3a0 0x6e4 0x7 0x0
+#define MX50_PAD_SD1_D3__ESDHC1_DAT3				0x0f8 0x3a4 0x000 0x0 0x0
+#define MX50_PAD_SD1_D3__GPIO5_5				0x0f8 0x3a4 0x000 0x1 0x0
+#define MX50_PAD_SD2_CLK__ESDHC2_CLK				0x0fc 0x3a8 0x000 0x0 0x0
+#define MX50_PAD_SD2_CLK__GPIO5_6				0x0fc 0x3a8 0x000 0x1 0x0
+#define MX50_PAD_SD2_CLK__MSHC_SCLK				0x0fc 0x3a8 0x000 0x2 0x0
+#define MX50_PAD_SD2_CMD__ESDHC2_CMD				0x100 0x3ac 0x000 0x0 0x0
+#define MX50_PAD_SD2_CMD__GPIO5_7				0x100 0x3ac 0x000 0x1 0x0
+#define MX50_PAD_SD2_CMD__MSHC_BS				0x100 0x3ac 0x000 0x2 0x0
+#define MX50_PAD_SD2_D0__ESDHC2_DAT0				0x104 0x3b0 0x000 0x0 0x0
+#define MX50_PAD_SD2_D0__GPIO5_8				0x104 0x3b0 0x000 0x1 0x0
+#define MX50_PAD_SD2_D0__MSHC_DATA_0				0x104 0x3b0 0x000 0x2 0x0
+#define MX50_PAD_SD2_D0__KPP_COL_4				0x104 0x3b0 0x790 0x3 0x0
+#define MX50_PAD_SD2_D1__ESDHC2_DAT1				0x108 0x3b4 0x000 0x0 0x0
+#define MX50_PAD_SD2_D1__GPIO5_9				0x108 0x3b4 0x000 0x1 0x0
+#define MX50_PAD_SD2_D1__MSHC_DATA_1				0x108 0x3b4 0x000 0x2 0x0
+#define MX50_PAD_SD2_D1__KPP_ROW_4				0x108 0x3b4 0x7a0 0x3 0x0
+#define MX50_PAD_SD2_D2__ESDHC2_DAT2				0x10c 0x3b8 0x000 0x0 0x0
+#define MX50_PAD_SD2_D2__GPIO5_10				0x10c 0x3b8 0x000 0x1 0x0
+#define MX50_PAD_SD2_D2__MSHC_DATA_2				0x10c 0x3b8 0x000 0x2 0x0
+#define MX50_PAD_SD2_D2__KPP_COL_5				0x10c 0x3b8 0x794 0x3 0x0
+#define MX50_PAD_SD2_D3__ESDHC2_DAT3				0x110 0x3bc 0x000 0x0 0x0
+#define MX50_PAD_SD2_D3__GPIO5_11				0x110 0x3bc 0x000 0x1 0x0
+#define MX50_PAD_SD2_D3__MSHC_DATA_3				0x110 0x3bc 0x000 0x2 0x0
+#define MX50_PAD_SD2_D3__KPP_ROW_5				0x110 0x3bc 0x7a4 0x3 0x0
+#define MX50_PAD_SD2_D4__ESDHC2_DAT4				0x114 0x3c0 0x000 0x0 0x0
+#define MX50_PAD_SD2_D4__GPIO5_12				0x114 0x3c0 0x000 0x1 0x0
+#define MX50_PAD_SD2_D4__AUDMUX_AUD4_RXFS			0x114 0x3c0 0x6d0 0x2 0x0
+#define MX50_PAD_SD2_D4__KPP_COL_6				0x114 0x3c0 0x798 0x3 0x0
+#define MX50_PAD_SD2_D4__EIM_WEIM_D_0				0x114 0x3c0 0x7ec 0x4 0x0
+#define MX50_PAD_SD2_D4__CCM_CCM_OUT_0				0x114 0x3c0 0x000 0x7 0x0
+#define MX50_PAD_SD2_D5__ESDHC2_DAT5				0x118 0x3c4 0x000 0x0 0x0
+#define MX50_PAD_SD2_D5__GPIO5_13				0x118 0x3c4 0x000 0x1 0x0
+#define MX50_PAD_SD2_D5__AUDMUX_AUD4_RXC			0x118 0x3c4 0x6cc 0x2 0x0
+#define MX50_PAD_SD2_D5__KPP_ROW_6				0x118 0x3c4 0x7a8 0x3 0x0
+#define MX50_PAD_SD2_D5__EIM_WEIM_D_1				0x118 0x3c4 0x7f0 0x4 0x0
+#define MX50_PAD_SD2_D5__CCM_CCM_OUT_1				0x118 0x3c4 0x000 0x7 0x0
+#define MX50_PAD_SD2_D6__ESDHC2_DAT6				0x11c 0x3c8 0x000 0x0 0x0
+#define MX50_PAD_SD2_D6__GPIO5_14				0x11c 0x3c8 0x000 0x1 0x0
+#define MX50_PAD_SD2_D6__AUDMUX_AUD4_RXD			0x11c 0x3c8 0x6c4 0x2 0x0
+#define MX50_PAD_SD2_D6__KPP_COL_7				0x11c 0x3c8 0x79c 0x3 0x0
+#define MX50_PAD_SD2_D6__EIM_WEIM_D_2				0x11c 0x3c8 0x7f4 0x4 0x0
+#define MX50_PAD_SD2_D6__CCM_CCM_OUT_2				0x11c 0x3c8 0x000 0x7 0x0
+#define MX50_PAD_SD2_D7__ESDHC2_DAT7				0x120 0x3cc 0x000 0x0 0x0
+#define MX50_PAD_SD2_D7__GPIO5_15				0x120 0x3cc 0x000 0x1 0x0
+#define MX50_PAD_SD2_D7__AUDMUX_AUD4_TXFS			0x120 0x3cc 0x6d8 0x2 0x0
+#define MX50_PAD_SD2_D7__KPP_ROW_7				0x120 0x3cc 0x7ac 0x3 0x0
+#define MX50_PAD_SD2_D7__EIM_WEIM_D_3				0x120 0x3cc 0x7f8 0x4 0x0
+#define MX50_PAD_SD2_D7__CCM_STOP				0x120 0x3cc 0x000 0x7 0x0
+#define MX50_PAD_SD2_WP__ESDHC2_WP				0x124 0x3d0 0x744 0x0 0x1
+#define MX50_PAD_SD2_WP__GPIO5_16				0x124 0x3d0 0x000 0x1 0x0
+#define MX50_PAD_SD2_WP__AUDMUX_AUD4_TXD			0x124 0x3d0 0x6c8 0x2 0x0
+#define MX50_PAD_SD2_WP__EIM_WEIM_D_4				0x124 0x3d0 0x7fc 0x4 0x0
+#define MX50_PAD_SD2_WP__CCM_WAIT				0x124 0x3d0 0x000 0x7 0x0
+#define MX50_PAD_SD2_CD__ESDHC2_CD				0x128 0x3d4 0x740 0x0 0x1
+#define MX50_PAD_SD2_CD__GPIO5_17				0x128 0x3d4 0x000 0x1 0x0
+#define MX50_PAD_SD2_CD__AUDMUX_AUD4_TXC			0x128 0x3d4 0x6d4 0x2 0x0
+#define MX50_PAD_SD2_CD__EIM_WEIM_D_5				0x128 0x3d4 0x800 0x4 0x0
+#define MX50_PAD_SD2_CD__CCM_REF_EN_B				0x128 0x3d4 0x000 0x7 0x0
+#define MX50_PAD_DISP_D0__ELCDIF_DAT_0				0x12c 0x40c 0x6fc 0x0 0x0
+#define MX50_PAD_DISP_D0__GPIO2_0				0x12c 0x40c 0x000 0x1 0x0
+#define MX50_PAD_DISP_D0__FEC_TX_CLK				0x12c 0x40c 0x78c 0x2 0x0
+#define MX50_PAD_DISP_D0__EIM_WEIM_A_16				0x12c 0x40c 0x000 0x3 0x0
+#define MX50_PAD_DISP_D0__SDMA_DEBUG_PC_0			0x12c 0x40c 0x000 0x6 0x0
+#define MX50_PAD_DISP_D0__USBPHY1_VSTATUS_0			0x12c 0x40c 0x000 0x7 0x0
+#define MX50_PAD_DISP_D1__ELCDIF_DAT_1				0x130 0x410 0x700 0x0 0x0
+#define MX50_PAD_DISP_D1__GPIO2_1				0x130 0x410 0x000 0x1 0x0
+#define MX50_PAD_DISP_D1__FEC_RX_ERR				0x130 0x410 0x788 0x2 0x0
+#define MX50_PAD_DISP_D1__EIM_WEIM_A_17				0x130 0x410 0x000 0x3 0x0
+#define MX50_PAD_DISP_D1__SDMA_DEBUG_PC_1			0x130 0x410 0x000 0x6 0x0
+#define MX50_PAD_DISP_D1__USBPHY1_VSTATUS_1			0x130 0x410 0x000 0x7 0x0
+#define MX50_PAD_DISP_D2__ELCDIF_DAT_2				0x134 0x414 0x704 0x0 0x0
+#define MX50_PAD_DISP_D2__GPIO2_2				0x134 0x414 0x000 0x1 0x0
+#define MX50_PAD_DISP_D2__FEC_RX_DV				0x134 0x414 0x784 0x2 0x0
+#define MX50_PAD_DISP_D2__EIM_WEIM_A_18				0x134 0x414 0x000 0x3 0x0
+#define MX50_PAD_DISP_D2__SDMA_DEBUG_PC_2			0x134 0x414 0x000 0x6 0x0
+#define MX50_PAD_DISP_D2__USBPHY1_VSTATUS_2			0x134 0x414 0x000 0x7 0x0
+#define MX50_PAD_DISP_D3__ELCDIF_DAT_3				0x138 0x418 0x708 0x0 0x0
+#define MX50_PAD_DISP_D3__GPIO2_3				0x138 0x418 0x000 0x1 0x0
+#define MX50_PAD_DISP_D3__FEC_RDATA_1				0x138 0x418 0x77c 0x2 0x0
+#define MX50_PAD_DISP_D3__EIM_WEIM_A_19				0x138 0x418 0x000 0x3 0x0
+#define MX50_PAD_DISP_D3__FEC_COL				0x138 0x418 0x770 0x4 0x1
+#define MX50_PAD_DISP_D3__SDMA_DEBUG_PC_3			0x138 0x418 0x000 0x6 0x0
+#define MX50_PAD_DISP_D3__USBPHY1_VSTATUS_3			0x138 0x418 0x000 0x7 0x0
+#define MX50_PAD_DISP_D4__ELCDIF_DAT_4				0x13c 0x41c 0x70c 0x0 0x0
+#define MX50_PAD_DISP_D4__GPIO2_4				0x13c 0x41c 0x000 0x1 0x0
+#define MX50_PAD_DISP_D4__FEC_RDATA_0				0x13c 0x41c 0x778 0x2 0x0
+#define MX50_PAD_DISP_D4__EIM_WEIM_A_20				0x13c 0x41c 0x000 0x3 0x0
+#define MX50_PAD_DISP_D4__SDMA_DEBUG_PC_4			0x13c 0x41c 0x000 0x6 0x0
+#define MX50_PAD_DISP_D4__USBPHY1_VSTATUS_4			0x13c 0x41c 0x000 0x7 0x0
+#define MX50_PAD_DISP_D5__ELCDIF_DAT_5				0x140 0x420 0x710 0x0 0x0
+#define MX50_PAD_DISP_D5__GPIO2_5				0x140 0x420 0x000 0x1 0x0
+#define MX50_PAD_DISP_D5__FEC_TX_EN				0x140 0x420 0x000 0x2 0x0
+#define MX50_PAD_DISP_D5__EIM_WEIM_A_21				0x140 0x420 0x000 0x3 0x0
+#define MX50_PAD_DISP_D5__SDMA_DEBUG_PC_5			0x140 0x420 0x000 0x6 0x0
+#define MX50_PAD_DISP_D5__USBPHY1_VSTATUS_5			0x140 0x420 0x000 0x7 0x0
+#define MX50_PAD_DISP_D6__ELCDIF_DAT_6				0x144 0x424 0x714 0x0 0x0
+#define MX50_PAD_DISP_D6__GPIO2_6				0x144 0x424 0x000 0x1 0x0
+#define MX50_PAD_DISP_D6__FEC_TDATA_1				0x144 0x424 0x000 0x2 0x0
+#define MX50_PAD_DISP_D6__EIM_WEIM_A_22				0x144 0x424 0x000 0x3 0x0
+#define MX50_PAD_DISP_D6__FEC_RX_CLK				0x144 0x424 0x780 0x4 0x1
+#define MX50_PAD_DISP_D6__SDMA_DEBUG_PC_6			0x144 0x424 0x000 0x6 0x0
+#define MX50_PAD_DISP_D6__USBPHY1_VSTATUS_6			0x144 0x424 0x000 0x7 0x0
+#define MX50_PAD_DISP_D7__ELCDIF_DAT_7				0x148 0x428 0x718 0x0 0x0
+#define MX50_PAD_DISP_D7__GPIO2_7				0x148 0x428 0x000 0x1 0x0
+#define MX50_PAD_DISP_D7__FEC_TDATA_0				0x148 0x428 0x000 0x2 0x0
+#define MX50_PAD_DISP_D7__EIM_WEIM_A_23				0x148 0x428 0x000 0x3 0x0
+#define MX50_PAD_DISP_D7__SDMA_DEBUG_PC_7			0x148 0x428 0x000 0x6 0x0
+#define MX50_PAD_DISP_D7__USBPHY1_VSTATUS_7			0x148 0x428 0x000 0x7 0x0
+#define MX50_PAD_DISP_WR__ELCDIF_WR_RWN				0x14c 0x42c 0x000 0x0 0x0
+#define MX50_PAD_DISP_WR__GPIO2_16				0x14c 0x42c 0x000 0x1 0x0
+#define MX50_PAD_DISP_WR__ELCDIF_DOTCLK				0x14c 0x42c 0x000 0x2 0x0
+#define MX50_PAD_DISP_WR__EIM_WEIM_A_24				0x14c 0x42c 0x000 0x3 0x0
+#define MX50_PAD_DISP_WR__SDMA_DEBUG_PC_8			0x14c 0x42c 0x000 0x6 0x0
+#define MX50_PAD_DISP_WR__USBPHY1_AVALID			0x14c 0x42c 0x000 0x7 0x0
+#define MX50_PAD_DISP_RD__ELCDIF_RD_E				0x150 0x430 0x000 0x0 0x0
+#define MX50_PAD_DISP_RD__GPIO2_19				0x150 0x430 0x000 0x1 0x0
+#define MX50_PAD_DISP_RD__ELCDIF_ENABLE				0x150 0x430 0x000 0x2 0x0
+#define MX50_PAD_DISP_RD__EIM_WEIM_A_25				0x150 0x430 0x000 0x3 0x0
+#define MX50_PAD_DISP_RD__SDMA_DEBUG_PC_9			0x150 0x430 0x000 0x6 0x0
+#define MX50_PAD_DISP_RD__USBPHY1_BVALID			0x150 0x430 0x000 0x7 0x0
+#define MX50_PAD_DISP_RS__ELCDIF_RS				0x154 0x434 0x000 0x0 0x0
+#define MX50_PAD_DISP_RS__GPIO2_17				0x154 0x434 0x000 0x1 0x0
+#define MX50_PAD_DISP_RS__ELCDIF_VSYNC				0x154 0x434 0x73c 0x2 0x1
+#define MX50_PAD_DISP_RS__EIM_WEIM_A_26				0x154 0x434 0x000 0x3 0x0
+#define MX50_PAD_DISP_RS__SDMA_DEBUG_PC_10			0x154 0x434 0x000 0x6 0x0
+#define MX50_PAD_DISP_RS__USBPHY1_ENDSESSION			0x154 0x434 0x000 0x7 0x0
+#define MX50_PAD_DISP_CS__ELCDIF_CS				0x158 0x438 0x000 0x0 0x0
+#define MX50_PAD_DISP_CS__GPIO2_21				0x158 0x438 0x000 0x1 0x0
+#define MX50_PAD_DISP_CS__ELCDIF_HSYNC				0x158 0x438 0x6f8 0x2 0x1
+#define MX50_PAD_DISP_CS__EIM_WEIM_A_27				0x158 0x438 0x000 0x3 0x0
+#define MX50_PAD_DISP_CS__EIM_WEIM_CS_3				0x158 0x438 0x000 0x4 0x0
+#define MX50_PAD_DISP_CS__SDMA_DEBUG_PC_11			0x158 0x438 0x000 0x6 0x0
+#define MX50_PAD_DISP_CS__USBPHY1_IDDIG				0x158 0x438 0x000 0x7 0x0
+#define MX50_PAD_DISP_BUSY__ELCDIF_BUSY				0x15c 0x43c 0x6f8 0x0 0x2
+#define MX50_PAD_DISP_BUSY__GPIO2_18				0x15c 0x43c 0x000 0x1 0x0
+#define MX50_PAD_DISP_BUSY__EIM_WEIM_CS_3			0x15c 0x43c 0x000 0x4 0x0
+#define MX50_PAD_DISP_BUSY__SDMA_DEBUG_PC_12			0x15c 0x43c 0x000 0x6 0x0
+#define MX50_PAD_DISP_BUSY__USBPHY2_HOSTDISCONNECT		0x15c 0x43c 0x000 0x7 0x0
+#define MX50_PAD_DISP_RESET__ELCDIF_RESET			0x160 0x440 0x000 0x0 0x0
+#define MX50_PAD_DISP_RESET__GPIO2_20				0x160 0x440 0x000 0x1 0x0
+#define MX50_PAD_DISP_RESET__EIM_WEIM_CS_3			0x160 0x440 0x000 0x4 0x0
+#define MX50_PAD_DISP_RESET__SDMA_DEBUG_PC_13			0x160 0x440 0x000 0x6 0x0
+#define MX50_PAD_DISP_RESET__USBPHY2_BISTOK			0x160 0x440 0x000 0x7 0x0
+#define MX50_PAD_SD3_CMD__ESDHC3_CMD				0x164 0x444 0x000 0x0 0x0
+#define MX50_PAD_SD3_CMD__GPIO5_18				0x164 0x444 0x000 0x1 0x0
+#define MX50_PAD_SD3_CMD__EIM_NANDF_WRN				0x164 0x444 0x000 0x2 0x0
+#define MX50_PAD_SD3_CMD__SSP_CMD				0x164 0x444 0x000 0x3 0x0
+#define MX50_PAD_SD3_CLK__ESDHC3_CLK				0x168 0x448 0x000 0x0 0x0
+#define MX50_PAD_SD3_CLK__GPIO5_19				0x168 0x448 0x000 0x1 0x0
+#define MX50_PAD_SD3_CLK__EIM_NANDF_RDN				0x168 0x448 0x000 0x2 0x0
+#define MX50_PAD_SD3_CLK__SSP_CLK				0x168 0x448 0x000 0x3 0x0
+#define MX50_PAD_SD3_D0__ESDHC3_DAT0				0x16c 0x44c 0x000 0x0 0x0
+#define MX50_PAD_SD3_D0__GPIO5_20				0x16c 0x44c 0x000 0x1 0x0
+#define MX50_PAD_SD3_D0__EIM_NANDF_D_4				0x16c 0x44c 0x000 0x2 0x0
+#define MX50_PAD_SD3_D0__SSP_D0					0x16c 0x44c 0x000 0x3 0x0
+#define MX50_PAD_SD3_D0__CCM_PLL1_BYP				0x16c 0x44c 0x6dc 0x7 0x1
+#define MX50_PAD_SD3_D1__ESDHC3_DAT1				0x170 0x450 0x000 0x0 0x0
+#define MX50_PAD_SD3_D1__GPIO5_21				0x170 0x450 0x000 0x1 0x0
+#define MX50_PAD_SD3_D1__EIM_NANDF_D_5				0x170 0x450 0x000 0x2 0x0
+#define MX50_PAD_SD3_D1__SSP_D1					0x170 0x450 0x000 0x3 0x0
+#define MX50_PAD_SD3_D1__CCM_PLL2_BYP				0x170 0x450 0x000 0x7 0x0
+#define MX50_PAD_SD3_D2__ESDHC3_DAT2				0x174 0x454 0x000 0x0 0x0
+#define MX50_PAD_SD3_D2__GPIO5_22				0x174 0x454 0x000 0x1 0x0
+#define MX50_PAD_SD3_D2__EIM_NANDF_D_6				0x174 0x454 0x000 0x2 0x0
+#define MX50_PAD_SD3_D2__SSP_D2					0x174 0x454 0x000 0x3 0x0
+#define MX50_PAD_SD3_D2__CCM_PLL3_BYP				0x174 0x454 0x6e4 0x7 0x1
+#define MX50_PAD_SD3_D3__ESDHC3_DAT3				0x178 0x458 0x000 0x0 0x0
+#define MX50_PAD_SD3_D3__GPIO5_23				0x178 0x458 0x000 0x1 0x0
+#define MX50_PAD_SD3_D3__EIM_NANDF_D_7				0x178 0x458 0x000 0x2 0x0
+#define MX50_PAD_SD3_D3__SSP_D3					0x178 0x458 0x000 0x3 0x0
+#define MX50_PAD_SD3_D4__ESDHC3_DAT4				0x17c 0x45c 0x000 0x0 0x0
+#define MX50_PAD_SD3_D4__GPIO5_24				0x17c 0x45c 0x000 0x1 0x0
+#define MX50_PAD_SD3_D4__EIM_NANDF_D_0				0x17c 0x45c 0x000 0x2 0x0
+#define MX50_PAD_SD3_D4__SSP_D4					0x17c 0x45c 0x000 0x3 0x0
+#define MX50_PAD_SD3_D5__ESDHC3_DAT5				0x180 0x460 0x000 0x0 0x0
+#define MX50_PAD_SD3_D5__GPIO5_25				0x180 0x460 0x000 0x1 0x0
+#define MX50_PAD_SD3_D5__EIM_NANDF_D_1				0x180 0x460 0x000 0x2 0x0
+#define MX50_PAD_SD3_D5__SSP_D5					0x180 0x460 0x000 0x3 0x0
+#define MX50_PAD_SD3_D6__ESDHC3_DAT6				0x184 0x464 0x000 0x0 0x0
+#define MX50_PAD_SD3_D6__GPIO5_26				0x184 0x464 0x000 0x1 0x0
+#define MX50_PAD_SD3_D6__EIM_NANDF_D_2				0x184 0x464 0x000 0x2 0x0
+#define MX50_PAD_SD3_D6__SSP_D6					0x184 0x464 0x000 0x3 0x0
+#define MX50_PAD_SD3_D7__ESDHC3_DAT7				0x188 0x468 0x000 0x0 0x0
+#define MX50_PAD_SD3_D7__GPIO5_27				0x188 0x468 0x000 0x1 0x0
+#define MX50_PAD_SD3_D7__EIM_NANDF_D_3				0x188 0x468 0x000 0x2 0x0
+#define MX50_PAD_SD3_D7__SSP_D7					0x188 0x468 0x000 0x3 0x0
+#define MX50_PAD_SD3_WP__ESDHC3_WP				0x18c 0x46C 0x000 0x0 0x0
+#define MX50_PAD_SD3_WP__GPIO5_28				0x18c 0x46C 0x000 0x1 0x0
+#define MX50_PAD_SD3_WP__EIM_NANDF_RESETN			0x18c 0x46C 0x000 0x2 0x0
+#define MX50_PAD_SD3_WP__SSP_CD					0x18c 0x46C 0x000 0x3 0x0
+#define MX50_PAD_SD3_WP__ESDHC4_LCTL				0x18c 0x46C 0x000 0x4 0x0
+#define MX50_PAD_SD3_WP__EIM_WEIM_CS_3				0x18c 0x46C 0x000 0x5 0x0
+#define MX50_PAD_DISP_D8__ELCDIF_DAT_8				0x190 0x470 0x71c 0x0 0x0
+#define MX50_PAD_DISP_D8__GPIO2_8				0x190 0x470 0x000 0x1 0x0
+#define MX50_PAD_DISP_D8__EIM_NANDF_CLE				0x190 0x470 0x000 0x2 0x0
+#define MX50_PAD_DISP_D8__ESDHC1_LCTL				0x190 0x470 0x000 0x3 0x0
+#define MX50_PAD_DISP_D8__ESDHC4_CMD				0x190 0x470 0x74c 0x4 0x2
+#define MX50_PAD_DISP_D8__KPP_COL_4				0x190 0x470 0x790 0x5 0x1
+#define MX50_PAD_DISP_D8__FEC_TX_CLK				0x190 0x470 0x78c 0x6 0x1
+#define MX50_PAD_DISP_D8__USBPHY1_DATAOUT_0			0x190 0x470 0x000 0x7 0x0
+#define MX50_PAD_DISP_D9__ELCDIF_DAT_9				0x194 0x474 0x720 0x0 0x0
+#define MX50_PAD_DISP_D9__GPIO2_9				0x194 0x474 0x000 0x1 0x0
+#define MX50_PAD_DISP_D9__EIM_NANDF_ALE				0x194 0x474 0x000 0x2 0x0
+#define MX50_PAD_DISP_D9__ESDHC2_LCTL				0x194 0x474 0x000 0x3 0x0
+#define MX50_PAD_DISP_D9__ESDHC4_CLK				0x194 0x474 0x748 0x4 0x2
+#define MX50_PAD_DISP_D9__KPP_ROW_4				0x194 0x474 0x7a0 0x5 0x1
+#define MX50_PAD_DISP_D9__FEC_RX_ER				0x194 0x474 0x788 0x6 0x1
+#define MX50_PAD_DISP_D9__USBPHY1_DATAOUT_1			0x194 0x474 0x000 0x7 0x0
+#define MX50_PAD_DISP_D10__ELCDIF_DAT_10			0x198 0x478 0x724 0x0 0x0
+#define MX50_PAD_DISP_D10__GPIO2_10				0x198 0x478 0x000 0x1 0x0
+#define MX50_PAD_DISP_D10__EIM_NANDF_CEN_0			0x198 0x478 0x000 0x2 0x0
+#define MX50_PAD_DISP_D10__ESDHC3_LCTL				0x198 0x478 0x000 0x3 0x0
+#define MX50_PAD_DISP_D10__ESDHC4_DAT0				0x198 0x478 0x000 0x4 0x0
+#define MX50_PAD_DISP_D10__KPP_COL_5				0x198 0x478 0x794 0x5 0x1
+#define MX50_PAD_DISP_D10__FEC_RX_DV				0x198 0x478 0x784 0x6 0x1
+#define MX50_PAD_DISP_D10__USBPHY1_DATAOUT_2			0x198 0x478 0x000 0x7 0x0
+#define MX50_PAD_DISP_D11__ELCDIF_DAT_11			0x19c 0x47c 0x728 0x0 0x0
+#define MX50_PAD_DISP_D11__GPIO2_11				0x19c 0x47c 0x000 0x1 0x0
+#define MX50_PAD_DISP_D11__EIM_NANDF_CEN_1			0x19c 0x47c 0x000 0x2 0x0
+#define MX50_PAD_DISP_D11__ESDHC4_DAT1				0x19c 0x47c 0x754 0x4 0x1
+#define MX50_PAD_DISP_D11__KPP_ROW_5				0x19c 0x47c 0x7a4 0x5 0x1
+#define MX50_PAD_DISP_D11__FEC_RDATA_1				0x19c 0x47c 0x77c 0x6 0x1
+#define MX50_PAD_DISP_D11__USBPHY1_DATAOUT_3			0x19c 0x47c 0x000 0x7 0x0
+#define MX50_PAD_DISP_D12__ELCDIF_DAT_12			0x1a0 0x480 0x72c 0x0 0x0
+#define MX50_PAD_DISP_D12__GPIO2_12				0x1a0 0x480 0x000 0x1 0x0
+#define MX50_PAD_DISP_D12__EIM_NANDF_CEN_2			0x1a0 0x480 0x000 0x2 0x0
+#define MX50_PAD_DISP_D12__ESDHC1_CD				0x1a0 0x480 0x000 0x3 0x0
+#define MX50_PAD_DISP_D12__ESDHC4_DAT2				0x1a0 0x480 0x758 0x4 0x1
+#define MX50_PAD_DISP_D12__KPP_COL_6				0x1a0 0x480 0x798 0x5 0x1
+#define MX50_PAD_DISP_D12__FEC_RDATA_0				0x1a0 0x480 0x778 0x6 0x1
+#define MX50_PAD_DISP_D12__USBPHY1_DATAOUT_4			0x1a0 0x480 0x000 0x7 0x0
+#define MX50_PAD_DISP_D13__ELCDIF_DAT_13			0x1a4 0x484 0x730 0x0 0x0
+#define MX50_PAD_DISP_D13__GPIO2_13				0x1a4 0x484 0x000 0x1 0x0
+#define MX50_PAD_DISP_D13__EIM_NANDF_CEN_3			0x1a4 0x484 0x000 0x2 0x0
+#define MX50_PAD_DISP_D13__ESDHC3_CD				0x1a4 0x484 0x000 0x3 0x0
+#define MX50_PAD_DISP_D13__ESDHC4_DAT3				0x1a4 0x484 0x75c 0x4 0x1
+#define MX50_PAD_DISP_D13__KPP_ROW_6				0x1a4 0x484 0x7a8 0x5 0x1
+#define MX50_PAD_DISP_D13__FEC_TX_EN				0x1a4 0x484 0x000 0x6 0x0
+#define MX50_PAD_DISP_D13__USBPHY1_DATAOUT_5			0x1a4 0x484 0x000 0x7 0x0
+#define MX50_PAD_DISP_D14__ELCDIF_DAT_14			0x1a8 0x488 0x734 0x0 0x0
+#define MX50_PAD_DISP_D14__GPIO2_14				0x1a8 0x488 0x000 0x1 0x0
+#define MX50_PAD_DISP_D14__EIM_NANDF_READY0			0x1a8 0x488 0x7b4 0x2 0x1
+#define MX50_PAD_DISP_D14__ESDHC1_WP				0x1a8 0x488 0x000 0x3 0x0
+#define MX50_PAD_DISP_D14__ESDHC4_WP				0x1a8 0x488 0x000 0x4 0x0
+#define MX50_PAD_DISP_D14__KPP_COL_7				0x1a8 0x488 0x79c 0x5 0x1
+#define MX50_PAD_DISP_D14__FEC_TDATA_1				0x1a8 0x488 0x000 0x6 0x0
+#define MX50_PAD_DISP_D14__USBPHY1_DATAOUT_6			0x1a8 0x488 0x000 0x7 0x0
+#define MX50_PAD_DISP_D15__ELCDIF_DAT_15			0x1ac 0x48c 0x738 0x0 0x0
+#define MX50_PAD_DISP_D15__GPIO2_15				0x1ac 0x48c 0x000 0x1 0x0
+#define MX50_PAD_DISP_D15__EIM_NANDF_DQS			0x1ac 0x48c 0x7b0 0x2 0x1
+#define MX50_PAD_DISP_D15__ESDHC3_RST				0x1ac 0x48c 0x000 0x3 0x0
+#define MX50_PAD_DISP_D15__ESDHC4_CD				0x1ac 0x48c 0x000 0x4 0x0
+#define MX50_PAD_DISP_D15__KPP_ROW_7				0x1ac 0x48c 0x7ac 0x5 0x1
+#define MX50_PAD_DISP_D15__FEC_TDATA_0				0x1ac 0x48c 0x000 0x6 0x0
+#define MX50_PAD_DISP_D15__USBPHY1_DATAOUT_7			0x1ac 0x48c 0x000 0x7 0x0
+#define MX50_PAD_EPDC_D0__EPDC_SDDO_0				0x1b0 0x54c 0x000 0x0 0x0
+#define MX50_PAD_EPDC_D0__GPIO3_0				0x1b0 0x54c 0x000 0x1 0x0
+#define MX50_PAD_EPDC_D0__EIM_WEIM_D_0				0x1b0 0x54c 0x7ec 0x2 0x1
+#define MX50_PAD_EPDC_D0__ELCDIF_RS				0x1b0 0x54c 0x000 0x3 0x0
+#define MX50_PAD_EPDC_D0__ELCDIF_DOTCLK				0x1b0 0x54c 0x000 0x4 0x0
+#define MX50_PAD_EPDC_D0__SDMA_DEBUG_EVT_CHN_LINES_0		0x1b0 0x54c 0x000 0x6 0x0
+#define MX50_PAD_EPDC_D0__USBPHY2_DATAOUT_0			0x1b0 0x54c 0x000 0x7 0x0
+#define MX50_PAD_EPDC_D1__EPDC_SDDO_1				0x1b4 0x550 0x000 0x0 0x0
+#define MX50_PAD_EPDC_D1__GPIO3_1				0x1b4 0x550 0x000 0x1 0x0
+#define MX50_PAD_EPDC_D1__EIM_WEIM_D_1				0x1b4 0x550 0x7f0 0x2 0x1
+#define MX50_PAD_EPDC_D1__ELCDIF_CS				0x1b4 0x550 0x000 0x3 0x0
+#define MX50_PAD_EPDC_D1__ELCDIF_ENABLE				0x1b4 0x550 0x000 0x4 0x0
+#define MX50_PAD_EPDC_D1__SDMA_DEBUG_EVT_CHN_LINES_1		0x1b4 0x550 0x000 0x6 0x0
+#define MX50_PAD_EPDC_D1__USBPHY2_DATAOUT_1			0x1b4 0x550 0x000 0x7 0x0
+#define MX50_PAD_EPDC_D2__EPDC_SDDO_2				0x1b8 0x554 0x000 0x0 0x0
+#define MX50_PAD_EPDC_D2__GPIO3_2				0x1b8 0x554 0x000 0x1 0x0
+#define MX50_PAD_EPDC_D2__EIM_WEIM_D_2				0x1b8 0x554 0x7f4 0x2 0x1
+#define MX50_PAD_EPDC_D2__ELCDIF_WR_RWN				0x1b8 0x554 0x000 0x3 0x0
+#define MX50_PAD_EPDC_D2__ELCDIF_VSYNC				0x1b8 0x554 0x73c 0x4 0x2
+#define MX50_PAD_EPDC_D2__SDMA_DEBUG_EVT_CHN_LINES_2		0x1b8 0x554 0x000 0x6 0x0
+#define MX50_PAD_EPDC_D2__USBPHY2_DATAOUT_2			0x1b8 0x554 0x000 0x7 0x0
+#define MX50_PAD_EPDC_D3__EPDC_SDDO_3				0x1bc 0x558 0x000 0x0 0x0
+#define MX50_PAD_EPDC_D3__GPIO3_3				0x1bc 0x558 0x000 0x1 0x0
+#define MX50_PAD_EPDC_D3__EIM_WEIM_D_3				0x1bc 0x558 0x7f8 0x2 0x1
+#define MX50_PAD_EPDC_D3__ELCDIF_RD_E				0x1bc 0x558 0x000 0x3 0x0
+#define MX50_PAD_EPDC_D3__ELCDIF_HSYNC				0x1bc 0x558 0x6f8 0x4 0x3
+#define MX50_PAD_EPDC_D3__SDMA_DEBUG_EVT_CHN_LINES_3		0x1bc 0x558 0x000 0x6 0x0
+#define MX50_PAD_EPDC_D3__USBPHY2_DATAOUT_3			0x1bc 0x558 0x000 0x7 0x0
+#define MX50_PAD_EPDC_D4__EPDC_SDDO_4				0x1c0 0x55c 0x000 0x0 0x0
+#define MX50_PAD_EPDC_D4__GPIO3_4				0x1c0 0x55c 0x000 0x1 0x0
+#define MX50_PAD_EPDC_D4__EIM_WEIM_D_4				0x1c0 0x55c 0x7fc 0x2 0x1
+#define MX50_PAD_EPDC_D4__SDMA_DEBUG_EVT_CHN_LINES_4		0x1c0 0x55c 0x000 0x6 0x0
+#define MX50_PAD_EPDC_D4__USBPHY2_DATAOUT_4			0x1c0 0x55c 0x000 0x7 0x0
+#define MX50_PAD_EPDC_D5__EPDC_SDDO_5				0x1c4 0x560 0x000 0x0 0x0
+#define MX50_PAD_EPDC_D5__GPIO3_5				0x1c4 0x560 0x000 0x1 0x0
+#define MX50_PAD_EPDC_D5__EIM_WEIM_D_5				0x1c4 0x560 0x800 0x2 0x1
+#define MX50_PAD_EPDC_D5__SDMA_DEBUG_EVT_CHN_LINES_5		0x1c4 0x560 0x000 0x6 0x0
+#define MX50_PAD_EPDC_D5__USBPHY2_DATAOUT_5			0x1c4 0x560 0x000 0x7 0x0
+#define MX50_PAD_EPDC_D6__EPDC_SDDO_6				0x1c8 0x564 0x000 0x0 0x0
+#define MX50_PAD_EPDC_D6__GPIO3_6				0x1c8 0x564 0x000 0x1 0x0
+#define MX50_PAD_EPDC_D6__EIM_WEIM_D_6				0x1c8 0x564 0x804 0x2 0x1
+#define MX50_PAD_EPDC_D6__SDMA_DEBUG_EVT_CHN_LINES_6		0x1c8 0x564 0x000 0x6 0x0
+#define MX50_PAD_EPDC_D6__USBPHY2_DATAOUT_6			0x1c8 0x564 0x000 0x7 0x0
+#define MX50_PAD_EPDC_D7__EPDC_SDDO_7				0x1cc 0x568 0x000 0x0 0x0
+#define MX50_PAD_EPDC_D7__GPIO3_7				0x1cc 0x568 0x000 0x1 0x0
+#define MX50_PAD_EPDC_D7__EIM_WEIM_D_7				0x1cc 0x568 0x808 0x2 0x1
+#define MX50_PAD_EPDC_D7__SDMA_DEBUG_EVT_CHN_LINES_7		0x1cc 0x568 0x000 0x6 0x0
+#define MX50_PAD_EPDC_D7__USBPHY2_DATAOUT_7			0x1cc 0x568 0x000 0x7 0x0
+#define MX50_PAD_EPDC_D8__EPDC_SDDO_8				0x1d0 0x56c 0x000 0x0 0x0
+#define MX50_PAD_EPDC_D8__GPIO3_8				0x1d0 0x56c 0x000 0x1 0x0
+#define MX50_PAD_EPDC_D8__EIM_WEIM_D_8				0x1d0 0x56c 0x80c 0x2 0x2
+#define MX50_PAD_EPDC_D8__ELCDIF_DAT_24				0x1d0 0x56c 0x000 0x3 0x0
+#define MX50_PAD_EPDC_D8__SDMA_DEBUG_MATCHED_DMBUS		0x1d0 0x56c 0x000 0x6 0x0
+#define MX50_PAD_EPDC_D8__USBPHY2_VSTATUS_0			0x1d0 0x56c 0x000 0x7 0x0
+#define MX50_PAD_EPDC_D9__EPDC_SDDO_9				0x1d4 0x570 0x000 0x0 0x0
+#define MX50_PAD_EPDC_D9__GPIO3_9				0x1d4 0x570 0x000 0x1 0x0
+#define MX50_PAD_EPDC_D9__EIM_WEIM_D_9				0x1d4 0x570 0x810 0x2 0x2
+#define MX50_PAD_EPDC_D9__ELCDIF_DAT_25				0x1d4 0x570 0x000 0x3 0x0
+#define MX50_PAD_EPDC_D9__SDMA_DEBUG_EVENT_CHANNEL_SEL		0x1d4 0x570 0x000 0x6 0x0
+#define MX50_PAD_EPDC_D9__USBPHY2_VSTATUS_1			0x1d4 0x570 0x000 0x7 0x0
+#define MX50_PAD_EPDC_D10__EPDC_SDDO_10				0x1d8 0x574 0x000 0x0 0x0
+#define MX50_PAD_EPDC_D10__GPIO3_10				0x1d8 0x574 0x000 0x1 0x0
+#define MX50_PAD_EPDC_D10__EIM_WEIM_D_10			0x1d8 0x574 0x814 0x2 0x2
+#define MX50_PAD_EPDC_D10__ELCDIF_DAT_26			0x1d8 0x574 0x000 0x3 0x0
+#define MX50_PAD_EPDC_D10__SDMA_DEBUG_EVENT_CHANNEL_0		0x1d8 0x574 0x000 0x6 0x0
+#define MX50_PAD_EPDC_D10__USBPHY2_VSTATUS_2			0x1d8 0x574 0x000 0x7 0x0
+#define MX50_PAD_EPDC_D11__EPDC_SDDO_11				0x1dc 0x578 0x000 0x0 0x0
+#define MX50_PAD_EPDC_D11__GPIO3_11				0x1dc 0x578 0x000 0x1 0x0
+#define MX50_PAD_EPDC_D11__EIM_WEIM_D_11			0x1dc 0x578 0x818 0x2 0x2
+#define MX50_PAD_EPDC_D11__ELCDIF_DAT_27			0x1dc 0x578 0x000 0x3 0x0
+#define MX50_PAD_EPDC_D11__SDMA_DEBUG_EVENT_CHANNEL_1		0x1dc 0x578 0x000 0x6 0x0
+#define MX50_PAD_EPDC_D11__USBPHY2_VSTATUS_3			0x1dc 0x578 0x000 0x7 0x0
+#define MX50_PAD_EPDC_D12__EPDC_SDDO_12				0x1e0 0x57c 0x000 0x0 0x0
+#define MX50_PAD_EPDC_D12__GPIO3_12				0x1e0 0x57c 0x000 0x1 0x0
+#define MX50_PAD_EPDC_D12__EIM_WEIM_D_12			0x1e0 0x57c 0x81c 0x2 0x1
+#define MX50_PAD_EPDC_D12__ELCDIF_DAT_28			0x1e0 0x57c 0x000 0x3 0x0
+#define MX50_PAD_EPDC_D12__SDMA_DEBUG_EVENT_CHANNEL_2		0x1e0 0x57c 0x000 0x6 0x0
+#define MX50_PAD_EPDC_D12__USBPHY2_VSTATUS_4			0x1e0 0x57c 0x000 0x7 0x0
+#define MX50_PAD_EPDC_D13__EPDC_SDDO_13				0x1e4 0x580 0x000 0x0 0x0
+#define MX50_PAD_EPDC_D13__GPIO3_13				0x1e4 0x580 0x000 0x1 0x0
+#define MX50_PAD_EPDC_D13__EIM_WEIM_D_13			0x1e4 0x580 0x820 0x2 0x1
+#define MX50_PAD_EPDC_D13__ELCDIF_DAT_29			0x1e4 0x580 0x000 0x3 0x0
+#define MX50_PAD_EPDC_D13__SDMA_DEBUG_EVENT_CHANNEL_3		0x1e4 0x580 0x000 0x6 0x0
+#define MX50_PAD_EPDC_D13__USBPHY2_VSTATUS_5			0x1e4 0x580 0x000 0x7 0x0
+#define MX50_PAD_EPDC_D14__EPDC_SDDO_14				0x1e8 0x584 0x000 0x0 0x0
+#define MX50_PAD_EPDC_D14__GPIO3_14				0x1e8 0x584 0x000 0x1 0x0
+#define MX50_PAD_EPDC_D14__EIM_WEIM_D_14			0x1e8 0x584 0x824 0x2 0x1
+#define MX50_PAD_EPDC_D14__ELCDIF_DAT_30			0x1e8 0x584 0x000 0x3 0x0
+#define MX50_PAD_EPDC_D14__AUDMUX_AUD6_TXD			0x1e8 0x584 0x000 0x4 0x0
+#define MX50_PAD_EPDC_D14__SDMA_DEBUG_EVENT_CHANNEL_4		0x1e8 0x584 0x000 0x6 0x0
+#define MX50_PAD_EPDC_D14__USBPHY2_VSTATUS_6			0x1e8 0x584 0x000 0x7 0x0
+#define MX50_PAD_EPDC_D15__EPDC_SDDO_15				0x1ec 0x588 0x000 0x0 0x0
+#define MX50_PAD_EPDC_D15__GPIO3_15				0x1ec 0x588 0x000 0x1 0x0
+#define MX50_PAD_EPDC_D15__EIM_WEIM_D_15			0x1ec 0x588 0x828 0x2 0x1
+#define MX50_PAD_EPDC_D15__ELCDIF_DAT_31			0x1ec 0x588 0x000 0x3 0x0
+#define MX50_PAD_EPDC_D15__AUDMUX_AUD6_TXC			0x1ec 0x588 0x000 0x4 0x0
+#define MX50_PAD_EPDC_D15__SDMA_DEBUG_EVENT_CHANNEL_5		0x1ec 0x588 0x000 0x6 0x0
+#define MX50_PAD_EPDC_D15__USBPHY2_VSTATUS_7			0x1ec 0x588 0x000 0x7 0x0
+#define MX50_PAD_EPDC_GDCLK__EPDC_GDCLK				0x1f0 0x58c 0x000 0x0 0x0
+#define MX50_PAD_EPDC_GDCLK__GPIO3_16				0x1f0 0x58c 0x000 0x1 0x0
+#define MX50_PAD_EPDC_GDCLK__EIM_WEIM_D_16			0x1f0 0x58c 0x000 0x2 0x0
+#define MX50_PAD_EPDC_GDCLK__ELCDIF_DAT_16			0x1f0 0x58c 0x000 0x3 0x0
+#define MX50_PAD_EPDC_GDCLK__AUDMUX_AUD6_TXFS			0x1f0 0x58c 0x000 0x4 0x0
+#define MX50_PAD_EPDC_GDCLK__SDMA_DEBUG_CORE_STATE_0		0x1f0 0x58c 0x000 0x6 0x0
+#define MX50_PAD_EPDC_GDCLK__USBPHY2_BISTOK			0x1f0 0x58c 0x000 0x7 0x0
+#define MX50_PAD_EPDC_GDSP__EPCD_GDSP				0x1f4 0x590 0x000 0x0 0x0
+#define MX50_PAD_EPDC_GDSP__GPIO3_17				0x1f4 0x590 0x000 0x1 0x0
+#define MX50_PAD_EPDC_GDSP__EIM_WEIM_D_17			0x1f4 0x590 0x000 0x2 0x0
+#define MX50_PAD_EPDC_GDSP__ELCDIF_DAT_17			0x1f4 0x590 0x000 0x3 0x0
+#define MX50_PAD_EPDC_GDSP__AUDMUX_AUD6_RXD			0x1f4 0x590 0x000 0x4 0x0
+#define MX50_PAD_EPDC_GDSP__SDMA_DEBUG_CORE_STATE_1		0x1f4 0x590 0x000 0x6 0x0
+#define MX50_PAD_EPDC_GDSP__USBPHY2_BVALID			0x1f4 0x590 0x000 0x7 0x0
+#define MX50_PAD_EPDC_GDOE__EPCD_GDOE				0x1f8 0x594 0x000 0x0 0x0
+#define MX50_PAD_EPDC_GDOE__GPIO3_18				0x1f8 0x594 0x000 0x1 0x0
+#define MX50_PAD_EPDC_GDOE__EIM_WEIM_D_18			0x1f8 0x594 0x000 0x2 0x0
+#define MX50_PAD_EPDC_GDOE__ELCDIF_DAT_18			0x1f8 0x594 0x000 0x3 0x0
+#define MX50_PAD_EPDC_GDOE__AUDMUX_AUD6_RXC			0x1f8 0x594 0x000 0x4 0x0
+#define MX50_PAD_EPDC_GDOE__SDMA_DEBUG_CORE_STATE_2		0x1f8 0x594 0x000 0x6 0x0
+#define MX50_PAD_EPDC_GDOE__USBPHY2_ENDSESSION			0x1f8 0x594 0x000 0x7 0x0
+#define MX50_PAD_EPDC_GDRL__EPCD_GDRL				0x1fc 0x598 0x000 0x0 0x0
+#define MX50_PAD_EPDC_GDRL__GPIO3_19				0x1fc 0x598 0x000 0x1 0x0
+#define MX50_PAD_EPDC_GDRL__EIM_WEIM_D_19			0x1f8 0x598 0x000 0x2 0x0
+#define MX50_PAD_EPDC_GDRL__ELCDIF_DAT_19			0x1fc 0x598 0x000 0x3 0x0
+#define MX50_PAD_EPDC_GDRL__AUDMUX_AUD6_RXFS			0x1fc 0x598 0x000 0x4 0x0
+#define MX50_PAD_EPDC_GDRL__SDMA_DEBUG_CORE_STATE_3		0x1fc 0x598 0x000 0x6 0x0
+#define MX50_PAD_EPDC_GDRL__USBPHY2_IDDIG			0x1fc 0x598 0x000 0x7 0x0
+#define MX50_PAD_EPDC_SDCLK__EPCD_SDCLK				0x200 0x59c 0x000 0x0 0x0
+#define MX50_PAD_EPDC_SDCLK__GPIO3_20				0x200 0x59c 0x000 0x1 0x0
+#define MX50_PAD_EPDC_SDCLK__EIM_WEIM_D_20			0x200 0x59c 0x000 0x2 0x0
+#define MX50_PAD_EPDC_SDCLK__ELCDIF_DAT_20			0x200 0x59c 0x000 0x3 0x0
+#define MX50_PAD_EPDC_SDCLK__AUDMUX_AUD5_TXD			0x200 0x59c 0x000 0x4 0x0
+#define MX50_PAD_EPDC_SDCLK__SDMA_DEBUG_BUS_DEVICE_0		0x200 0x59c 0x000 0x6 0x0
+#define MX50_PAD_EPDC_SDCLK__USBPHY2_HOSTDISCONNECT		0x200 0x59c 0x000 0x7 0x0
+#define MX50_PAD_EPDC_SDOEZ__EPCD_SDOEZ				0x204 0x5a0 0x000 0x0 0x0
+#define MX50_PAD_EPDC_SDOEZ__GPIO3_21				0x204 0x5a0 0x000 0x1 0x0
+#define MX50_PAD_EPDC_SDOEZ__EIM_WEIM_D_21			0x204 0x5a0 0x000 0x2 0x0
+#define MX50_PAD_EPDC_SDOEZ__ELCDIF_DAT_21			0x204 0x5a0 0x000 0x3 0x0
+#define MX50_PAD_EPDC_SDOEZ__AUDMUX_AUD5_TXC			0x204 0x5a0 0x000 0x4 0x0
+#define MX50_PAD_EPDC_SDOEZ__SDMA_DEBUG_BUS_DEVICE_1		0x204 0x5a0 0x000 0x6 0x0
+#define MX50_PAD_EPDC_SDOEZ__USBPHY2_TXREADY			0x204 0x5a0 0x000 0x7 0x0
+#define MX50_PAD_EPDC_SDOED__EPCD_SDOED				0x208 0x5a4 0x000 0x0 0x0
+#define MX50_PAD_EPDC_SDOED__GPIO3_22				0x208 0x5a4 0x000 0x1 0x0
+#define MX50_PAD_EPDC_SDOED__EIM_WEIM_D_22			0x208 0x5a4 0x000 0x2 0x0
+#define MX50_PAD_EPDC_SDOED__ELCDIF_DAT_22			0x208 0x5a4 0x000 0x3 0x0
+#define MX50_PAD_EPDC_SDOED__AUDMUX_AUD5_TXFS			0x208 0x5a4 0x000 0x4 0x0
+#define MX50_PAD_EPDC_SDOED__SDMA_DEBUG_BUS_DEVICE_2		0x208 0x5a4 0x000 0x6 0x0
+#define MX50_PAD_EPDC_SDOED__USBPHY2_RXVALID			0x208 0x5a4 0x000 0x7 0x0
+#define MX50_PAD_EPDC_SDOE__EPCD_SDOE				0x20c 0x5a8 0x000 0x0 0x0
+#define MX50_PAD_EPDC_SDOE__GPIO3_23				0x20c 0x5a8 0x000 0x1 0x0
+#define MX50_PAD_EPDC_SDOE__EIM_WEIM_D_23			0x20c 0x5a8 0x000 0x2 0x0
+#define MX50_PAD_EPDC_SDOE__ELCDIF_DAT_23			0x20c 0x5a8 0x000 0x3 0x0
+#define MX50_PAD_EPDC_SDOE__AUDMUX_AUD5_RXD			0x20c 0x5a8 0x000 0x4 0x0
+#define MX50_PAD_EPDC_SDOE__SDMA_DEBUG_BUS_DEVICE_3		0x20c 0x5a8 0x000 0x6 0x0
+#define MX50_PAD_EPDC_SDOE__USBPHY2_RXACTIVE			0x20c 0x5a8 0x000 0x7 0x0
+#define MX50_PAD_EPDC_SDLE__EPCD_SDLE				0x210 0x5ac 0x000 0x0 0x0
+#define MX50_PAD_EPDC_SDLE__GPIO3_24				0x210 0x5ac 0x000 0x1 0x0
+#define MX50_PAD_EPDC_SDLE__EIM_WEIM_D_24			0x210 0x5ac 0x000 0x2 0x0
+#define MX50_PAD_EPDC_SDLE__ELCDIF_DAT_8			0x210 0x5ac 0x71c 0x3 0x1
+#define MX50_PAD_EPDC_SDLE__AUDMUX_AUD5_RXC			0x210 0x5ac 0x000 0x4 0x0
+#define MX50_PAD_EPDC_SDLE__SDMA_DEBUG_BUS_DEVICE_4		0x210 0x5ac 0x000 0x6 0x0
+#define MX50_PAD_EPDC_SDLE__USBPHY2_RXERROR			0x210 0x5ac 0x000 0x7 0x0
+#define MX50_PAD_EPDC_SDCLKN__EPCD_SDCLKN			0x214 0x5b0 0x000 0x0 0x0
+#define MX50_PAD_EPDC_SDCLKN__GPIO3_25				0x214 0x5b0 0x000 0x1 0x0
+#define MX50_PAD_EPDC_SDCLKN__EIM_WEIM_D_25			0x214 0x5b0 0x000 0x2 0x0
+#define MX50_PAD_EPDC_SDCLKN__ELCDIF_DAT_9			0x214 0x5b0 0x720 0x3 0x1
+#define MX50_PAD_EPDC_SDCLKN__AUDMUX_AUD5_RXFS			0x214 0x5b0 0x000 0x4 0x0
+#define MX50_PAD_EPDC_SDCLKN__SDMA_DEBUG_BUS_ERROR		0x214 0x5b0 0x000 0x6 0x0
+#define MX50_PAD_EPDC_SDCLKN__USBPHY2_SIECLOCK			0x214 0x5b0 0x000 0x7 0x0
+#define MX50_PAD_EPDC_SDSHR__EPCD_SDSHR				0x218 0x5b4 0x000 0x0 0x0
+#define MX50_PAD_EPDC_SDSHR__GPIO3_26				0x218 0x5b4 0x000 0x1 0x0
+#define MX50_PAD_EPDC_SDSHR__EIM_WEIM_D_26			0x218 0x5b4 0x000 0x2 0x0
+#define MX50_PAD_EPDC_SDSHR__ELCDIF_DAT_10			0x218 0x5b4 0x724 0x3 0x1
+#define MX50_PAD_EPDC_SDSHR__AUDMUX_AUD4_TXD			0x218 0x5b4 0x6c8 0x4 0x1
+#define MX50_PAD_EPDC_SDSHR__SDMA_DEBUG_BUS_RWB			0x218 0x5b4 0x000 0x6 0x0
+#define MX50_PAD_EPDC_SDSHR__USBPHY2_LINESTATE_0		0x218 0x5b4 0x000 0x7 0x0
+#define MX50_PAD_EPDC_PWRCOM__EPCD_PWRCOM			0x21c 0x5b8 0x000 0x0 0x0
+#define MX50_PAD_EPDC_PWRCOM__GPIO3_27				0x21c 0x5b8 0x000 0x1 0x0
+#define MX50_PAD_EPDC_PWRCOM__EIM_WEIM_D_27			0x21c 0x5b8 0x000 0x2 0x0
+#define MX50_PAD_EPDC_PWRCOM__ELCDIF_DAT_11			0x21c 0x5b8 0x728 0x3 0x1
+#define MX50_PAD_EPDC_PWRCOM__AUDMUX_AUD4_TXC			0x21c 0x5b8 0x6d4 0x4 0x1
+#define MX50_PAD_EPDC_PWRCOM__SDMA_DEBUG_CORE_RUN		0x21c 0x5b8 0x000 0x6 0x0
+#define MX50_PAD_EPDC_PWRCOM__USBPHY2_LINESTATE_1		0x21c 0x5b8 0x000 0x7 0x0
+#define MX50_PAD_EPDC_PWRSTAT__EPCD_PWRSTAT			0x220 0x5bc 0x000 0x0 0x0
+#define MX50_PAD_EPDC_PWRSTAT__GPIO3_28				0x220 0x5bc 0x000 0x1 0x0
+#define MX50_PAD_EPDC_PWRSTAT__EIM_WEIM_D_28			0x220 0x5bc 0x000 0x2 0x0
+#define MX50_PAD_EPDC_PWRSTAT__ELCDIF_DAT_12			0x220 0x5bc 0x72c 0x3 0x1
+#define MX50_PAD_EPDC_PWRSTAT__AUDMUX_AUD4_TXFS			0x220 0x5bc 0x6d8 0x4 0x1
+#define MX50_PAD_EPDC_PWRSTAT__SDMA_DEBUG_MODE			0x220 0x5bc 0x000 0x6 0x0
+#define MX50_PAD_EPDC_PWRSTAT__USBPHY2_VBUSVALID		0x220 0x5bc 0x000 0x7 0x0
+#define MX50_PAD_EPDC_PWRCTRL0__EPCD_PWRCTRL0			0x224 0x5c0 0x000 0x0 0x0
+#define MX50_PAD_EPDC_PWRCTRL0__GPIO3_29			0x224 0x5c0 0x000 0x1 0x0
+#define MX50_PAD_EPDC_PWRCTRL0__EIM_WEIM_D_29			0x224 0x5c0 0x000 0x2 0x0
+#define MX50_PAD_EPDC_PWRCTRL0__ELCDIF_DAT_13			0x224 0x5c0 0x730 0x3 0x1
+#define MX50_PAD_EPDC_PWRCTRL0__AUDMUX_AUD4_RXD			0x224 0x5c0 0x6c4 0x4 0x1
+#define MX50_PAD_EPDC_PWRCTRL0__SDMA_DEBUG_RTBUFFER_WRITE	0x224 0x5c0 0x000 0x6 0x0
+#define MX50_PAD_EPDC_PWRCTRL0__USBPHY2_AVALID			0x224 0x5c0 0x000 0x7 0x0
+#define MX50_PAD_EPDC_PWRCTRL1__EPCD_PWRCTRL1			0x228 0x5c4 0x000 0x0 0x0
+#define MX50_PAD_EPDC_PWRCTRL1__GPIO3_30			0x228 0x5c4 0x000 0x1 0x0
+#define MX50_PAD_EPDC_PWRCTRL1__EIM_WEIM_D_30			0x228 0x5c4 0x000 0x2 0x0
+#define MX50_PAD_EPDC_PWRCTRL1__ELCDIF_DAT_14			0x228 0x5c4 0x734 0x3 0x1
+#define MX50_PAD_EPDC_PWRCTRL1__AUDMUX_AUD4_RXC			0x228 0x5c4 0x6cc 0x4 0x1
+#define MX50_PAD_EPDC_PWRCTRL1__SDMA_DEBUG_YIELD		0x228 0x5c4 0x000 0x6 0x0
+#define MX50_PAD_EPDC_PWRCTRL1__USBPHY1_ONBIST			0x228 0x5c4 0x000 0x7 0x0
+#define MX50_PAD_EPDC_PWRCTRL2__EPCD_PWRCTRL2			0x22c 0x5c8 0x000 0x0 0x0
+#define MX50_PAD_EPDC_PWRCTRL2__GPIO3_31			0x22c 0x5c8 0x000 0x1 0x0
+#define MX50_PAD_EPDC_PWRCTRL2__EIM_WEIM_D_31			0x22c 0x5c8 0x000 0x2 0x0
+#define MX50_PAD_EPDC_PWRCTRL2__ELCDIF_DAT_15			0x22c 0x5c8 0x738 0x3 0x1
+#define MX50_PAD_EPDC_PWRCTRL2__AUDMUX_AUD4_RXFS		0x22c 0x5c8 0x6d0 0x4 0x1
+#define MX50_PAD_EPDC_PWRCTRL2__SDMA_EXT_EVENT_0		0x22c 0x5c8 0x7b8 0x6 0x1
+#define MX50_PAD_EPDC_PWRCTRL2__USBPHY2_ONBIST			0x22c 0x5c8 0x000 0x7 0x0
+#define MX50_PAD_EPDC_PWRCTRL3__EPCD_PWRCTRL3			0x230 0x5cc 0x000 0x0 0x0
+#define MX50_PAD_EPDC_PWRCTRL3__GPIO4_20			0x230 0x5cc 0x000 0x1 0x0
+#define MX50_PAD_EPDC_PWRCTRL3__EIM_WEIM_EB_2			0x230 0x5cc 0x000 0x2 0x0
+#define MX50_PAD_EPDC_PWRCTRL3__SDMA_EXT_EVENT_1		0x230 0x5cc 0x7bc 0x6 0x1
+#define MX50_PAD_EPDC_PWRCTRL3__USBPHY1_BISTOK			0x230 0x5cc 0x000 0x7 0x0
+#define MX50_PAD_EPDC_VCOM0__EPCD_VCOM_0			0x234 0x5d0 0x000 0x0 0x0
+#define MX50_PAD_EPDC_VCOM0__GPIO4_21				0x234 0x5d0 0x000 0x1 0x0
+#define MX50_PAD_EPDC_VCOM0__EIM_WEIM_EB_3			0x234 0x5d0 0x000 0x2 0x0
+#define MX50_PAD_EPDC_VCOM0__USBPHY2_BISTOK			0x234 0x5d0 0x000 0x7 0x0
+#define MX50_PAD_EPDC_VCOM1__EPCD_VCOM_1			0x238 0x5d4 0x000 0x0 0x0
+#define MX50_PAD_EPDC_VCOM1__GPIO4_22				0x238 0x5d4 0x000 0x1 0x0
+#define MX50_PAD_EPDC_VCOM1__EIM_WEIM_CS_3			0x238 0x5d4 0x000 0x2 0x0
+#define MX50_PAD_EPDC_BDR0__EPCD_BDR_0				0x23c 0x5d8 0x000 0x0 0x0
+#define MX50_PAD_EPDC_BDR0__GPIO4_23				0x23c 0x5d8 0x000 0x1 0x0
+#define MX50_PAD_EPDC_BDR0__ELCDIF_DAT_7			0x23c 0x5d8 0x718 0x3 0x1
+#define MX50_PAD_EPDC_BDR1__EPCD_BDR_1				0x240 0x5dc 0x000 0x0 0x0
+#define MX50_PAD_EPDC_BDR1__GPIO4_24				0x240 0x5dc 0x000 0x1 0x0
+#define MX50_PAD_EPDC_BDR1__ELCDIF_DAT_6			0x240 0x5dc 0x714 0x3 0x1
+#define MX50_PAD_EPDC_SDCE0__EPCD_SDCE_0			0x244 0x5e0 0x000 0x0 0x0
+#define MX50_PAD_EPDC_SDCE0__GPIO4_25				0x244 0x5e0 0x000 0x1 0x0
+#define MX50_PAD_EPDC_SDCE0__ELCDIF_DAT_5			0x244 0x5e0 0x710 0x3 0x1
+#define MX50_PAD_EPDC_SDCE1__EPCD_SDCE_1			0x248 0x5e4 0x000 0x0 0x0
+#define MX50_PAD_EPDC_SDCE1__GPIO4_26				0x248 0x5e4 0x000 0x1 0x0
+#define MX50_PAD_EPDC_SDCE1__ELCDIF_DAT_4			0x248 0x5e4 0x70c 0x3 0x0
+#define MX50_PAD_EPDC_SDCE2__EPCD_SDCE_2			0x24c 0x5e8 0x000 0x0 0x0
+#define MX50_PAD_EPDC_SDCE2__GPIO4_27				0x24c 0x5e8 0x000 0x1 0x0
+#define MX50_PAD_EPDC_SDCE2__ELCDIF_DAT_3			0x24c 0x5e8 0x708 0x3 0x1
+#define MX50_PAD_EPDC_SDCE3__EPCD_SDCE_3			0x250 0x5ec 0x000 0x0 0x0
+#define MX50_PAD_EPDC_SDCE3__GPIO4_28				0x250 0x5ec 0x000 0x1 0x0
+#define MX50_PAD_EPDC_SDCE3__ELCDIF_DAT_2			0x250 0x5ec 0x704 0x3 0x1
+#define MX50_PAD_EPDC_SDCE4__EPCD_SDCE_4			0x254 0x5f0 0x000 0x0 0x0
+#define MX50_PAD_EPDC_SDCE4__GPIO4_29				0x254 0x5f0 0x000 0x1 0x0
+#define MX50_PAD_EPDC_SDCE4__ELCDIF_DAT_1			0x254 0x5f0 0x700 0x3 0x1
+#define MX50_PAD_EPDC_SDCE5__EPCD_SDCE_5			0x258 0x5f4 0x000 0x0 0x0
+#define MX50_PAD_EPDC_SDCE5__GPIO4_30				0x258 0x5f4 0x000 0x1 0x0
+#define MX50_PAD_EPDC_SDCE5__ELCDIF_DAT_0			0x258 0x5f4 0x6fc 0x3 0x1
+#define MX50_PAD_EIM_DA0__EIM_WEIM_A_0				0x25c 0x5f8 0x000 0x0 0x0
+#define MX50_PAD_EIM_DA0__GPIO1_0				0x25c 0x5f8 0x000 0x1 0x0
+#define MX50_PAD_EIM_DA0__KPP_COL_4				0x25c 0x5f8 0x790 0x3 0x2
+#define MX50_PAD_EIM_DA0__TPIU_TRACE_0				0x25c 0x5f8 0x000 0x6 0x0
+#define MX50_PAD_EIM_DA0__SRC_BT_CFG1_0				0x25c 0x5f8 0x000 0x7 0x0
+#define MX50_PAD_EIM_DA1__EIM_WEIM_A_1				0x260 0x5fc 0x000 0x0 0x0
+#define MX50_PAD_EIM_DA1__GPIO1_1				0x260 0x5fc 0x000 0x1 0x0
+#define MX50_PAD_EIM_DA1__KPP_ROW_4				0x260 0x5fc 0x7a0 0x3 0x2
+#define MX50_PAD_EIM_DA1__TPIU_TRACE_1				0x260 0x5fc 0x000 0x6 0x0
+#define MX50_PAD_EIM_DA1__SRC_BT_CFG1_1				0x260 0x5fc 0x000 0x7 0x0
+#define MX50_PAD_EIM_DA2__EIM_WEIM_A_2				0x264 0x600 0x000 0x0 0x0
+#define MX50_PAD_EIM_DA2__GPIO1_2				0x264 0x600 0x000 0x1 0x0
+#define MX50_PAD_EIM_DA2__KPP_COL_5				0x264 0x600 0x794 0x3 0x2
+#define MX50_PAD_EIM_DA2__TPIU_TRACE_2				0x264 0x600 0x000 0x6 0x0
+#define MX50_PAD_EIM_DA2__SRC_BT_CFG1_2				0x264 0x600 0x000 0x7 0x0
+#define MX50_PAD_EIM_DA3__EIM_WEIM_A_3				0x268 0x604 0x000 0x0 0x0
+#define MX50_PAD_EIM_DA3__GPIO1_3				0x268 0x604 0x000 0x1 0x0
+#define MX50_PAD_EIM_DA3__KPP_ROW_5				0x268 0x604 0x7a4 0x3 0x2
+#define MX50_PAD_EIM_DA3__TPIU_TRACE_3				0x268 0x604 0x000 0x6 0x0
+#define MX50_PAD_EIM_DA3__SRC_BT_CFG1_3				0x268 0x604 0x000 0x7 0x0
+#define MX50_PAD_EIM_DA4__EIM_WEIM_A_4				0x26c 0x608 0x000 0x0 0x0
+#define MX50_PAD_EIM_DA4__GPIO1_4				0x26c 0x608 0x000 0x1 0x0
+#define MX50_PAD_EIM_DA4__KPP_COL_6				0x26c 0x608 0x798 0x3 0x2
+#define MX50_PAD_EIM_DA4__TPIU_TRACE_4				0x26c 0x608 0x000 0x6 0x0
+#define MX50_PAD_EIM_DA4__SRC_BT_CFG1_4				0x26c 0x608 0x000 0x7 0x0
+#define MX50_PAD_EIM_DA5__EIM_WEIM_A_5				0x270 0x60c 0x000 0x0 0x0
+#define MX50_PAD_EIM_DA5__GPIO1_5				0x270 0x60c 0x000 0x1 0x0
+#define MX50_PAD_EIM_DA5__KPP_ROW_6				0x270 0x60c 0x7a8 0x3 0x2
+#define MX50_PAD_EIM_DA5__TPIU_TRACE_5				0x270 0x60c 0x000 0x6 0x0
+#define MX50_PAD_EIM_DA5__SRC_BT_CFG1_5				0x270 0x60c 0x000 0x7 0x0
+#define MX50_PAD_EIM_DA6__EIM_WEIM_A_6				0x274 0x610 0x000 0x0 0x0
+#define MX50_PAD_EIM_DA6__GPIO1_6				0x274 0x610 0x000 0x1 0x0
+#define MX50_PAD_EIM_DA6__KPP_COL_7				0x274 0x610 0x79c 0x3 0x2
+#define MX50_PAD_EIM_DA6__TPIU_TRACE_6				0x274 0x610 0x000 0x6 0x0
+#define MX50_PAD_EIM_DA6__SRC_BT_CFG1_6				0x274 0x610 0x000 0x7 0x0
+#define MX50_PAD_EIM_DA7__EIM_WEIM_A_7				0x278 0x614 0x000 0x0 0x0
+#define MX50_PAD_EIM_DA7__GPIO1_7				0x278 0x614 0x000 0x1 0x0
+#define MX50_PAD_EIM_DA7__KPP_ROW_7				0x278 0x614 0x7ac 0x3 0x2
+#define MX50_PAD_EIM_DA7__TPIU_TRACE_7				0x278 0x614 0x000 0x6 0x0
+#define MX50_PAD_EIM_DA7__SRC_BT_CFG1_7				0x278 0x614 0x000 0x7 0x0
+#define MX50_PAD_EIM_DA8__EIM_WEIM_A_8				0x27c 0x618 0x000 0x0 0x0
+#define MX50_PAD_EIM_DA8__GPIO1_8				0x27c 0x618 0x000 0x1 0x0
+#define MX50_PAD_EIM_DA8__EIM_NANDF_CLE				0x27c 0x618 0x000 0x2 0x0
+#define MX50_PAD_EIM_DA8__TPIU_TRACE_8				0x27c 0x618 0x000 0x6 0x0
+#define MX50_PAD_EIM_DA8__SRC_BT_CFG2_0				0x27c 0x618 0x000 0x7 0x0
+#define MX50_PAD_EIM_DA9__EIM_WEIM_A_9				0x280 0x61c 0x000 0x0 0x0
+#define MX50_PAD_EIM_DA9__GPIO1_9				0x280 0x61c 0x000 0x1 0x0
+#define MX50_PAD_EIM_DA9__EIM_NANDF_ALE				0x280 0x61c 0x000 0x2 0x0
+#define MX50_PAD_EIM_DA9__TPIU_TRACE_9				0x280 0x61c 0x000 0x6 0x0
+#define MX50_PAD_EIM_DA9__SRC_BT_CFG2_1				0x280 0x61c 0x000 0x7 0x0
+#define MX50_PAD_EIM_DA10__EIM_WEIM_A_10			0x284 0x620 0x000 0x0 0x0
+#define MX50_PAD_EIM_DA10__GPIO1_10				0x284 0x620 0x000 0x1 0x0
+#define MX50_PAD_EIM_DA10__EIM_NANDF_CEN_0			0x284 0x620 0x000 0x2 0x0
+#define MX50_PAD_EIM_DA10__TPIU_TRACE_10			0x284 0x620 0x000 0x6 0x0
+#define MX50_PAD_EIM_DA10__SRC_BT_CFG2_2			0x284 0x620 0x000 0x7 0x0
+#define MX50_PAD_EIM_DA11__EIM_WEIM_A_11			0x288 0x624 0x000 0x0 0x0
+#define MX50_PAD_EIM_DA11__GPIO1_11				0x288 0x624 0x000 0x1 0x0
+#define MX50_PAD_EIM_DA11__EIM_NANDF_CEN_1			0x288 0x624 0x000 0x2 0x0
+#define MX50_PAD_EIM_DA11__TPIU_TRACE_11			0x288 0x624 0x000 0x6 0x0
+#define MX50_PAD_EIM_DA11__SRC_BT_CFG2_3			0x288 0x624 0x000 0x7 0x0
+#define MX50_PAD_EIM_DA12__EIM_WEIM_A_12			0x28c 0x628 0x000 0x0 0x0
+#define MX50_PAD_EIM_DA12__GPIO1_12				0x28c 0x628 0x000 0x1 0x0
+#define MX50_PAD_EIM_DA12__EIM_NANDF_CEN_2			0x28c 0x628 0x000 0x2 0x0
+#define MX50_PAD_EIM_DA12__EPDC_SDCE_6				0x28c 0x628 0x000 0x3 0x0
+#define MX50_PAD_EIM_DA12__TPIU_TRACE_12			0x28c 0x628 0x000 0x6 0x0
+#define MX50_PAD_EIM_DA12__SRC_BT_CFG2_4			0x28c 0x628 0x000 0x7 0x0
+#define MX50_PAD_EIM_DA13__EIM_WEIM_A_13			0x290 0x62c 0x000 0x0 0x0
+#define MX50_PAD_EIM_DA13__GPIO1_13				0x290 0x62c 0x000 0x1 0x0
+#define MX50_PAD_EIM_DA13__EIM_NANDF_CEN_3			0x290 0x62c 0x000 0x2 0x0
+#define MX50_PAD_EIM_DA13__EPDC_SDCE_7				0x290 0x62c 0x000 0x3 0x0
+#define MX50_PAD_EIM_DA13__TPIU_TRACE_13			0x290 0x62c 0x000 0x6 0x0
+#define MX50_PAD_EIM_DA13__SRC_BT_CFG2_5			0x290 0x62c 0x000 0x7 0x0
+#define MX50_PAD_EIM_DA14__EIM_WEIM_A_14			0x294 0x630 0x000 0x0 0x0
+#define MX50_PAD_EIM_DA14__GPIO1_14				0x294 0x630 0x000 0x1 0x0
+#define MX50_PAD_EIM_DA14__EIM_NANDF_READY0			0x294 0x630 0x7b4 0x2 0x2
+#define MX50_PAD_EIM_DA14__EPDC_SDCE_8				0x294 0x630 0x000 0x3 0x0
+#define MX50_PAD_EIM_DA14__TPIU_TRACE_14			0x294 0x630 0x000 0x6 0x0
+#define MX50_PAD_EIM_DA14__SRC_BT_CFG2_6			0x294 0x630 0x000 0x7 0x0
+#define MX50_PAD_EIM_DA15__EIM_WEIM_A_15			0x298 0x634 0x000 0x0 0x0
+#define MX50_PAD_EIM_DA15__GPIO1_15				0x298 0x634 0x000 0x1 0x0
+#define MX50_PAD_EIM_DA15__EIM_NANDF_DQS			0x298 0x634 0x7b0 0x2 0x2
+#define MX50_PAD_EIM_DA15__EPDC_SDCE_9				0x298 0x634 0x000 0x3 0x0
+#define MX50_PAD_EIM_DA15__TPIU_TRACE_15			0x298 0x634 0x000 0x6 0x0
+#define MX50_PAD_EIM_DA15__SRC_BT_CFG2_7			0x298 0x634 0x000 0x7 0x0
+#define MX50_PAD_EIM_CS2__EIM_WEIM_CS_2				0x29c 0x638 0x000 0x0 0x0
+#define MX50_PAD_EIM_CS2__GPIO1_16				0x29c 0x638 0x000 0x1 0x0
+#define MX50_PAD_EIM_CS2__EIM_WEIM_A_27				0x29c 0x638 0x000 0x2 0x0
+#define MX50_PAD_EIM_CS2__TPIU_TRCLK				0x29c 0x638 0x000 0x6 0x0
+#define MX50_PAD_EIM_CS2__SRC_BT_CFG3_0				0x29c 0x638 0x000 0x7 0x0
+#define MX50_PAD_EIM_CS1__EIM_WEIM_CS_1				0x2a0 0x63c 0x000 0x0 0x0
+#define MX50_PAD_EIM_CS1__GPIO1_17				0x2a0 0x63c 0x000 0x1 0x0
+#define MX50_PAD_EIM_CS1__TPIU_TRCTL				0x2a0 0x63c 0x000 0x6 0x0
+#define MX50_PAD_EIM_CS1__SRC_BT_CFG3_1				0x2a0 0x63c 0x000 0x7 0x0
+#define MX50_PAD_EIM_CS0__EIM_WEIM_CS_0				0x2a4 0x640 0x000 0x0 0x0
+#define MX50_PAD_EIM_CS0__GPIO1_18				0x2a4 0x640 0x000 0x1 0x0
+#define MX50_PAD_EIM_CS0__SRC_BT_CFG3_2				0x2a4 0x640 0x000 0x7 0x0
+#define MX50_PAD_EIM_EB0__EIM_WEIM_EB_0				0x2a8 0x644 0x000 0x0 0x0
+#define MX50_PAD_EIM_EB0__GPIO1_19				0x2a8 0x644 0x000 0x1 0x0
+#define MX50_PAD_EIM_EB0__SRC_BT_CFG3_3				0x2a8 0x644 0x000 0x7 0x0
+#define MX50_PAD_EIM_EB1__EIM_WEIM_EB_1				0x2ac 0x648 0x000 0x0 0x0
+#define MX50_PAD_EIM_EB1__GPIO1_20				0x2ac 0x648 0x000 0x1 0x0
+#define MX50_PAD_EIM_EB1__SRC_BT_CFG3_4				0x2ac 0x648 0x000 0x7 0x0
+#define MX50_PAD_EIM_WAIT__EIM_WEIM_WAIT			0x2b0 0x64c 0x000 0x0 0x0
+#define MX50_PAD_EIM_WAIT__GPIO1_21				0x2b0 0x64c 0x000 0x1 0x0
+#define MX50_PAD_EIM_WAIT__EIM_WEIM_DTACK_B			0x2b0 0x64c 0x000 0x2 0x0
+#define MX50_PAD_EIM_WAIT__SRC_BT_CFG3_5			0x2b0 0x64c 0x000 0x7 0x0
+#define MX50_PAD_EIM_BCLK__EIM_WEIM_BCLK			0x2b4 0x650 0x000 0x0 0x0
+#define MX50_PAD_EIM_BCLK__GPIO1_22				0x2b4 0x650 0x000 0x1 0x0
+#define MX50_PAD_EIM_BCLK__SRC_BT_CFG3_6			0x2b4 0x650 0x000 0x7 0x0
+#define MX50_PAD_EIM_RDY__EIM_WEIM_RDY				0x2b8 0x654 0x000 0x0 0x0
+#define MX50_PAD_EIM_RDY__GPIO1_23				0x2b8 0x654 0x000 0x1 0x0
+#define MX50_PAD_EIM_RDY__SRC_BT_CFG3_7				0x2b8 0x654 0x000 0x7 0x0
+#define MX50_PAD_EIM_OE__EIM_WEIM_OE				0x2bc 0x658 0x000 0x0 0x0
+#define MX50_PAD_EIM_OE__GPIO1_24				0x2bc 0x658 0x000 0x1 0x0
+#define MX50_PAD_EIM_OE__INT_BOOT				0x2bc 0x658 0x000 0x7 0x0
+#define MX50_PAD_EIM_RW__EIM_WEIM_RW				0x2c0 0x65c 0x000 0x0 0x0
+#define MX50_PAD_EIM_RW__GPIO1_25				0x2c0 0x65c 0x000 0x1 0x0
+#define MX50_PAD_EIM_RW__SYSTEM_RST				0x2c0 0x65c 0x000 0x7 0x0
+#define MX50_PAD_EIM_LBA__EIM_WEIM_LBA				0x2c4 0x660 0x000 0x0 0x0
+#define MX50_PAD_EIM_LBA__GPIO1_26				0x2c4 0x660 0x000 0x1 0x0
+#define MX50_PAD_EIM_LBA__TESTER_ACK				0x2c4 0x660 0x000 0x7 0x0
+#define MX50_PAD_EIM_CRE__EIM_WEIM_CRE				0x2c8 0x664 0x000 0x0 0x0
+#define MX50_PAD_EIM_CRE__GPIO1_27				0x2c8 0x664 0x000 0x1 0x0
+
+#endif /* __DTS_IMX50_PINFUNC_H */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/imx51-pinfunc.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/imx51-pinfunc.h
new file mode 100644
index 0000000000000000000000000000000000000000..82eae3c8a3ce26703b4e7b99f1a021a65a07853f
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/imx51-pinfunc.h
@@ -0,0 +1,772 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __DTS_IMX51_PINFUNC_H
+#define __DTS_IMX51_PINFUNC_H
+
+/*
+ * The pin function ID is a tuple of
+ * <mux_reg conf_reg input_reg mux_mode input_val>
+ */
+#define MX51_PAD_EIM_D16__AUD4_RXFS			0x05c 0x3f0 0x000 0x5 0x0
+#define MX51_PAD_EIM_D16__AUD5_TXD			0x05c 0x3f0 0x8d8 0x7 0x0
+#define MX51_PAD_EIM_D16__EIM_D16			0x05c 0x3f0 0x000 0x0 0x0
+#define MX51_PAD_EIM_D16__GPIO2_0			0x05c 0x3f0 0x000 0x1 0x0
+#define MX51_PAD_EIM_D16__I2C1_SDA			0x05c 0x3f0 0x9b4 0x4 0x0
+#define MX51_PAD_EIM_D16__UART2_CTS			0x05c 0x3f0 0x000 0x3 0x0
+#define MX51_PAD_EIM_D16__USBH2_DATA0			0x05c 0x3f0 0x000 0x2 0x0
+#define MX51_PAD_EIM_D17__AUD5_RXD			0x060 0x3f4 0x8d4 0x7 0x0
+#define MX51_PAD_EIM_D17__EIM_D17			0x060 0x3f4 0x000 0x0 0x0
+#define MX51_PAD_EIM_D17__GPIO2_1			0x060 0x3f4 0x000 0x1 0x0
+#define MX51_PAD_EIM_D17__UART2_RXD			0x060 0x3f4 0x9ec 0x3 0x0
+#define MX51_PAD_EIM_D17__UART3_CTS			0x060 0x3f4 0x000 0x4 0x0
+#define MX51_PAD_EIM_D17__USBH2_DATA1			0x060 0x3f4 0x000 0x2 0x0
+#define MX51_PAD_EIM_D18__AUD5_TXC			0x064 0x3f8 0x8e4 0x7 0x0
+#define MX51_PAD_EIM_D18__EIM_D18			0x064 0x3f8 0x000 0x0 0x0
+#define MX51_PAD_EIM_D18__GPIO2_2			0x064 0x3f8 0x000 0x1 0x0
+#define MX51_PAD_EIM_D18__UART2_TXD			0x064 0x3f8 0x000 0x3 0x0
+#define MX51_PAD_EIM_D18__UART3_RTS			0x064 0x3f8 0x9f0 0x4 0x1
+#define MX51_PAD_EIM_D18__USBH2_DATA2			0x064 0x3f8 0x000 0x2 0x0
+#define MX51_PAD_EIM_D19__AUD4_RXC			0x068 0x3fc 0x000 0x5 0x0
+#define MX51_PAD_EIM_D19__AUD5_TXFS			0x068 0x3fc 0x8e8 0x7 0x0
+#define MX51_PAD_EIM_D19__EIM_D19			0x068 0x3fc 0x000 0x0 0x0
+#define MX51_PAD_EIM_D19__GPIO2_3			0x068 0x3fc 0x000 0x1 0x0
+#define MX51_PAD_EIM_D19__I2C1_SCL			0x068 0x3fc 0x9b0 0x4 0x0
+#define MX51_PAD_EIM_D19__UART2_RTS			0x068 0x3fc 0x9e8 0x3 0x1
+#define MX51_PAD_EIM_D19__USBH2_DATA3			0x068 0x3fc 0x000 0x2 0x0
+#define MX51_PAD_EIM_D20__AUD4_TXD			0x06c 0x400 0x8c8 0x5 0x0
+#define MX51_PAD_EIM_D20__EIM_D20			0x06c 0x400 0x000 0x0 0x0
+#define MX51_PAD_EIM_D20__GPIO2_4			0x06c 0x400 0x000 0x1 0x0
+#define MX51_PAD_EIM_D20__SRTC_ALARM_DEB		0x06c 0x400 0x000 0x4 0x0
+#define MX51_PAD_EIM_D20__USBH2_DATA4			0x06c 0x400 0x000 0x2 0x0
+#define MX51_PAD_EIM_D21__AUD4_RXD			0x070 0x404 0x8c4 0x5 0x0
+#define MX51_PAD_EIM_D21__EIM_D21			0x070 0x404 0x000 0x0 0x0
+#define MX51_PAD_EIM_D21__GPIO2_5			0x070 0x404 0x000 0x1 0x0
+#define MX51_PAD_EIM_D21__SRTC_ALARM_DEB		0x070 0x404 0x000 0x3 0x0
+#define MX51_PAD_EIM_D21__USBH2_DATA5			0x070 0x404 0x000 0x2 0x0
+#define MX51_PAD_EIM_D22__AUD4_TXC			0x074 0x408 0x8cc 0x5 0x0
+#define MX51_PAD_EIM_D22__EIM_D22			0x074 0x408 0x000 0x0 0x0
+#define MX51_PAD_EIM_D22__GPIO2_6			0x074 0x408 0x000 0x1 0x0
+#define MX51_PAD_EIM_D22__USBH2_DATA6			0x074 0x408 0x000 0x2 0x0
+#define MX51_PAD_EIM_D23__AUD4_TXFS			0x078 0x40c 0x8d0 0x5 0x0
+#define MX51_PAD_EIM_D23__EIM_D23			0x078 0x40c 0x000 0x0 0x0
+#define MX51_PAD_EIM_D23__GPIO2_7			0x078 0x40c 0x000 0x1 0x0
+#define MX51_PAD_EIM_D23__SPDIF_OUT1			0x078 0x40c 0x000 0x4 0x0
+#define MX51_PAD_EIM_D23__USBH2_DATA7			0x078 0x40c 0x000 0x2 0x0
+#define MX51_PAD_EIM_D24__AUD6_RXFS			0x07c 0x410 0x8f8 0x5 0x0
+#define MX51_PAD_EIM_D24__EIM_D24			0x07c 0x410 0x000 0x0 0x0
+#define MX51_PAD_EIM_D24__GPIO2_8			0x07c 0x410 0x000 0x1 0x0
+#define MX51_PAD_EIM_D24__I2C2_SDA			0x07c 0x410 0x9bc 0x4 0x0
+#define MX51_PAD_EIM_D24__UART3_CTS			0x07c 0x410 0x000 0x3 0x0
+#define MX51_PAD_EIM_D24__USBOTG_DATA0			0x07c 0x410 0x000 0x2 0x0
+#define MX51_PAD_EIM_D25__EIM_D25			0x080 0x414 0x000 0x0 0x0
+#define MX51_PAD_EIM_D25__KEY_COL6			0x080 0x414 0x9c8 0x1 0x0
+#define MX51_PAD_EIM_D25__UART2_CTS			0x080 0x414 0x000 0x4 0x0
+#define MX51_PAD_EIM_D25__UART3_RXD			0x080 0x414 0x9f4 0x3 0x0
+#define MX51_PAD_EIM_D25__USBOTG_DATA1			0x080 0x414 0x000 0x2 0x0
+#define MX51_PAD_EIM_D26__EIM_D26			0x084 0x418 0x000 0x0 0x0
+#define MX51_PAD_EIM_D26__KEY_COL7			0x084 0x418 0x9cc 0x1 0x0
+#define MX51_PAD_EIM_D26__UART2_RTS			0x084 0x418 0x9e8 0x4 0x3
+#define MX51_PAD_EIM_D26__UART3_TXD			0x084 0x418 0x000 0x3 0x0
+#define MX51_PAD_EIM_D26__USBOTG_DATA2			0x084 0x418 0x000 0x2 0x0
+#define MX51_PAD_EIM_D27__AUD6_RXC			0x088 0x41c 0x8f4 0x5 0x0
+#define MX51_PAD_EIM_D27__EIM_D27			0x088 0x41c 0x000 0x0 0x0
+#define MX51_PAD_EIM_D27__GPIO2_9			0x088 0x41c 0x000 0x1 0x0
+#define MX51_PAD_EIM_D27__I2C2_SCL			0x088 0x41c 0x9b8 0x4 0x0
+#define MX51_PAD_EIM_D27__UART3_RTS			0x088 0x41c 0x9f0 0x3 0x3
+#define MX51_PAD_EIM_D27__USBOTG_DATA3			0x088 0x41c 0x000 0x2 0x0
+#define MX51_PAD_EIM_D28__AUD6_TXD			0x08c 0x420 0x8f0 0x5 0x0
+#define MX51_PAD_EIM_D28__EIM_D28			0x08c 0x420 0x000 0x0 0x0
+#define MX51_PAD_EIM_D28__KEY_ROW4			0x08c 0x420 0x9d0 0x1 0x0
+#define MX51_PAD_EIM_D28__USBOTG_DATA4			0x08c 0x420 0x000 0x2 0x0
+#define MX51_PAD_EIM_D29__AUD6_RXD			0x090 0x424 0x8ec 0x5 0x0
+#define MX51_PAD_EIM_D29__EIM_D29			0x090 0x424 0x000 0x0 0x0
+#define MX51_PAD_EIM_D29__KEY_ROW5			0x090 0x424 0x9d4 0x1 0x0
+#define MX51_PAD_EIM_D29__USBOTG_DATA5			0x090 0x424 0x000 0x2 0x0
+#define MX51_PAD_EIM_D30__AUD6_TXC			0x094 0x428 0x8fc 0x5 0x0
+#define MX51_PAD_EIM_D30__EIM_D30			0x094 0x428 0x000 0x0 0x0
+#define MX51_PAD_EIM_D30__KEY_ROW6			0x094 0x428 0x9d8 0x1 0x0
+#define MX51_PAD_EIM_D30__USBOTG_DATA6			0x094 0x428 0x000 0x2 0x0
+#define MX51_PAD_EIM_D31__AUD6_TXFS			0x098 0x42c 0x900 0x5 0x0
+#define MX51_PAD_EIM_D31__EIM_D31			0x098 0x42c 0x000 0x0 0x0
+#define MX51_PAD_EIM_D31__KEY_ROW7			0x098 0x42c 0x9dc 0x1 0x0
+#define MX51_PAD_EIM_D31__USBOTG_DATA7			0x098 0x42c 0x000 0x2 0x0
+#define MX51_PAD_EIM_A16__EIM_A16			0x09c 0x430 0x000 0x0 0x0
+#define MX51_PAD_EIM_A16__GPIO2_10			0x09c 0x430 0x000 0x1 0x0
+#define MX51_PAD_EIM_A16__OSC_FREQ_SEL0			0x09c 0x430 0x000 0x7 0x0
+#define MX51_PAD_EIM_A17__EIM_A17			0x0a0 0x434 0x000 0x0 0x0
+#define MX51_PAD_EIM_A17__GPIO2_11			0x0a0 0x434 0x000 0x1 0x0
+#define MX51_PAD_EIM_A17__OSC_FREQ_SEL1			0x0a0 0x434 0x000 0x7 0x0
+#define MX51_PAD_EIM_A18__BOOT_LPB0			0x0a4 0x438 0x000 0x7 0x0
+#define MX51_PAD_EIM_A18__EIM_A18			0x0a4 0x438 0x000 0x0 0x0
+#define MX51_PAD_EIM_A18__GPIO2_12			0x0a4 0x438 0x000 0x1 0x0
+#define MX51_PAD_EIM_A19__BOOT_LPB1			0x0a8 0x43c 0x000 0x7 0x0
+#define MX51_PAD_EIM_A19__EIM_A19			0x0a8 0x43c 0x000 0x0 0x0
+#define MX51_PAD_EIM_A19__GPIO2_13			0x0a8 0x43c 0x000 0x1 0x0
+#define MX51_PAD_EIM_A20__BOOT_UART_SRC0		0x0ac 0x440 0x000 0x7 0x0
+#define MX51_PAD_EIM_A20__EIM_A20			0x0ac 0x440 0x000 0x0 0x0
+#define MX51_PAD_EIM_A20__GPIO2_14			0x0ac 0x440 0x000 0x1 0x0
+#define MX51_PAD_EIM_A21__BOOT_UART_SRC1		0x0b0 0x444 0x000 0x7 0x0
+#define MX51_PAD_EIM_A21__EIM_A21			0x0b0 0x444 0x000 0x0 0x0
+#define MX51_PAD_EIM_A21__GPIO2_15			0x0b0 0x444 0x000 0x1 0x0
+#define MX51_PAD_EIM_A22__EIM_A22			0x0b4 0x448 0x000 0x0 0x0
+#define MX51_PAD_EIM_A22__GPIO2_16			0x0b4 0x448 0x000 0x1 0x0
+#define MX51_PAD_EIM_A23__BOOT_HPN_EN			0x0b8 0x44c 0x000 0x7 0x0
+#define MX51_PAD_EIM_A23__EIM_A23			0x0b8 0x44c 0x000 0x0 0x0
+#define MX51_PAD_EIM_A23__GPIO2_17			0x0b8 0x44c 0x000 0x1 0x0
+#define MX51_PAD_EIM_A24__EIM_A24			0x0bc 0x450 0x000 0x0 0x0
+#define MX51_PAD_EIM_A24__GPIO2_18			0x0bc 0x450 0x000 0x1 0x0
+#define MX51_PAD_EIM_A24__USBH2_CLK			0x0bc 0x450 0x000 0x2 0x0
+#define MX51_PAD_EIM_A25__DISP1_PIN4			0x0c0 0x454 0x000 0x6 0x0
+#define MX51_PAD_EIM_A25__EIM_A25			0x0c0 0x454 0x000 0x0 0x0
+#define MX51_PAD_EIM_A25__GPIO2_19			0x0c0 0x454 0x000 0x1 0x0
+#define MX51_PAD_EIM_A25__USBH2_DIR			0x0c0 0x454 0x000 0x2 0x0
+#define MX51_PAD_EIM_A26__CSI1_DATA_EN			0x0c4 0x458 0x9a0 0x5 0x0
+#define MX51_PAD_EIM_A26__DISP2_EXT_CLK			0x0c4 0x458 0x908 0x6 0x0
+#define MX51_PAD_EIM_A26__EIM_A26			0x0c4 0x458 0x000 0x0 0x0
+#define MX51_PAD_EIM_A26__GPIO2_20			0x0c4 0x458 0x000 0x1 0x0
+#define MX51_PAD_EIM_A26__USBH2_STP			0x0c4 0x458 0x000 0x2 0x0
+#define MX51_PAD_EIM_A27__CSI2_DATA_EN			0x0c8 0x45c 0x99c 0x5 0x0
+#define MX51_PAD_EIM_A27__DISP1_PIN1			0x0c8 0x45c 0x9a4 0x6 0x0
+#define MX51_PAD_EIM_A27__EIM_A27			0x0c8 0x45c 0x000 0x0 0x0
+#define MX51_PAD_EIM_A27__GPIO2_21			0x0c8 0x45c 0x000 0x1 0x0
+#define MX51_PAD_EIM_A27__USBH2_NXT			0x0c8 0x45c 0x000 0x2 0x0
+#define MX51_PAD_EIM_EB0__EIM_EB0			0x0cc 0x460 0x000 0x0 0x0
+#define MX51_PAD_EIM_EB1__EIM_EB1			0x0d0 0x464 0x000 0x0 0x0
+#define MX51_PAD_EIM_EB2__AUD5_RXFS			0x0d4 0x468 0x8e0 0x6 0x0
+#define MX51_PAD_EIM_EB2__CSI1_D2			0x0d4 0x468 0x000 0x5 0x0
+#define MX51_PAD_EIM_EB2__EIM_EB2			0x0d4 0x468 0x000 0x0 0x0
+#define MX51_PAD_EIM_EB2__FEC_MDIO			0x0d4 0x468 0x954 0x3 0x0
+#define MX51_PAD_EIM_EB2__GPIO2_22			0x0d4 0x468 0x000 0x1 0x0
+#define MX51_PAD_EIM_EB2__GPT_CMPOUT1			0x0d4 0x468 0x000 0x7 0x0
+#define MX51_PAD_EIM_EB3__AUD5_RXC			0x0d8 0x46c 0x8dc 0x6 0x0
+#define MX51_PAD_EIM_EB3__CSI1_D3			0x0d8 0x46c 0x000 0x5 0x0
+#define MX51_PAD_EIM_EB3__EIM_EB3			0x0d8 0x46c 0x000 0x0 0x0
+#define MX51_PAD_EIM_EB3__FEC_RDATA1			0x0d8 0x46c 0x95c 0x3 0x0
+#define MX51_PAD_EIM_EB3__GPIO2_23			0x0d8 0x46c 0x000 0x1 0x0
+#define MX51_PAD_EIM_EB3__GPT_CMPOUT2			0x0d8 0x46c 0x000 0x7 0x0
+#define MX51_PAD_EIM_OE__EIM_OE				0x0dc 0x470 0x000 0x0 0x0
+#define MX51_PAD_EIM_OE__GPIO2_24			0x0dc 0x470 0x000 0x1 0x0
+#define MX51_PAD_EIM_CS0__EIM_CS0			0x0e0 0x474 0x000 0x0 0x0
+#define MX51_PAD_EIM_CS0__GPIO2_25			0x0e0 0x474 0x000 0x1 0x0
+#define MX51_PAD_EIM_CS1__EIM_CS1			0x0e4 0x478 0x000 0x0 0x0
+#define MX51_PAD_EIM_CS1__GPIO2_26			0x0e4 0x478 0x000 0x1 0x0
+#define MX51_PAD_EIM_CS2__AUD5_TXD			0x0e8 0x47c 0x8d8 0x6 0x1
+#define MX51_PAD_EIM_CS2__CSI1_D4			0x0e8 0x47c 0x000 0x5 0x0
+#define MX51_PAD_EIM_CS2__EIM_CS2			0x0e8 0x47c 0x000 0x0 0x0
+#define MX51_PAD_EIM_CS2__FEC_RDATA2			0x0e8 0x47c 0x960 0x3 0x0
+#define MX51_PAD_EIM_CS2__GPIO2_27			0x0e8 0x47c 0x000 0x1 0x0
+#define MX51_PAD_EIM_CS2__USBOTG_STP			0x0e8 0x47c 0x000 0x2 0x0
+#define MX51_PAD_EIM_CS3__AUD5_RXD			0x0ec 0x480 0x8d4 0x6 0x1
+#define MX51_PAD_EIM_CS3__CSI1_D5			0x0ec 0x480 0x000 0x5 0x0
+#define MX51_PAD_EIM_CS3__EIM_CS3			0x0ec 0x480 0x000 0x0 0x0
+#define MX51_PAD_EIM_CS3__FEC_RDATA3			0x0ec 0x480 0x964 0x3 0x0
+#define MX51_PAD_EIM_CS3__GPIO2_28			0x0ec 0x480 0x000 0x1 0x0
+#define MX51_PAD_EIM_CS3__USBOTG_NXT			0x0ec 0x480 0x000 0x2 0x0
+#define MX51_PAD_EIM_CS4__AUD5_TXC			0x0f0 0x484 0x8e4 0x6 0x1
+#define MX51_PAD_EIM_CS4__CSI1_D6			0x0f0 0x484 0x000 0x5 0x0
+#define MX51_PAD_EIM_CS4__EIM_CS4			0x0f0 0x484 0x000 0x0 0x0
+#define MX51_PAD_EIM_CS4__FEC_RX_ER			0x0f0 0x484 0x970 0x3 0x0
+#define MX51_PAD_EIM_CS4__GPIO2_29			0x0f0 0x484 0x000 0x1 0x0
+#define MX51_PAD_EIM_CS4__USBOTG_CLK			0x0f0 0x484 0x000 0x2 0x0
+#define MX51_PAD_EIM_CS5__AUD5_TXFS			0x0f4 0x488 0x8e8 0x6 0x1
+#define MX51_PAD_EIM_CS5__CSI1_D7			0x0f4 0x488 0x000 0x5 0x0
+#define MX51_PAD_EIM_CS5__DISP1_EXT_CLK			0x0f4 0x488 0x904 0x4 0x0
+#define MX51_PAD_EIM_CS5__EIM_CS5			0x0f4 0x488 0x000 0x0 0x0
+#define MX51_PAD_EIM_CS5__FEC_CRS			0x0f4 0x488 0x950 0x3 0x0
+#define MX51_PAD_EIM_CS5__GPIO2_30			0x0f4 0x488 0x000 0x1 0x0
+#define MX51_PAD_EIM_CS5__USBOTG_DIR			0x0f4 0x488 0x000 0x2 0x0
+#define MX51_PAD_EIM_DTACK__EIM_DTACK			0x0f8 0x48c 0x000 0x0 0x0
+#define MX51_PAD_EIM_DTACK__GPIO2_31			0x0f8 0x48c 0x000 0x1 0x0
+#define MX51_PAD_EIM_LBA__EIM_LBA			0x0fc 0x494 0x000 0x0 0x0
+#define MX51_PAD_EIM_LBA__GPIO3_1			0x0fc 0x494 0x978 0x1 0x0
+#define MX51_PAD_EIM_CRE__EIM_CRE			0x100 0x4a0 0x000 0x0 0x0
+#define MX51_PAD_EIM_CRE__GPIO3_2			0x100 0x4a0 0x97c 0x1 0x0
+#define MX51_PAD_DRAM_CS1__DRAM_CS1			0x104 0x4d0 0x000 0x0 0x0
+#define MX51_PAD_NANDF_WE_B__GPIO3_3			0x108 0x4e4 0x980 0x3 0x0
+#define MX51_PAD_NANDF_WE_B__NANDF_WE_B			0x108 0x4e4 0x000 0x0 0x0
+#define MX51_PAD_NANDF_WE_B__PATA_DIOW			0x108 0x4e4 0x000 0x1 0x0
+#define MX51_PAD_NANDF_WE_B__SD3_DATA0			0x108 0x4e4 0x93c 0x2 0x0
+#define MX51_PAD_NANDF_RE_B__GPIO3_4			0x10c 0x4e8 0x984 0x3 0x0
+#define MX51_PAD_NANDF_RE_B__NANDF_RE_B			0x10c 0x4e8 0x000 0x0 0x0
+#define MX51_PAD_NANDF_RE_B__PATA_DIOR			0x10c 0x4e8 0x000 0x1 0x0
+#define MX51_PAD_NANDF_RE_B__SD3_DATA1			0x10c 0x4e8 0x940 0x2 0x0
+#define MX51_PAD_NANDF_ALE__GPIO3_5			0x110 0x4ec 0x988 0x3 0x0
+#define MX51_PAD_NANDF_ALE__NANDF_ALE			0x110 0x4ec 0x000 0x0 0x0
+#define MX51_PAD_NANDF_ALE__PATA_BUFFER_EN		0x110 0x4ec 0x000 0x1 0x0
+#define MX51_PAD_NANDF_CLE__GPIO3_6			0x114 0x4f0 0x98c 0x3 0x0
+#define MX51_PAD_NANDF_CLE__NANDF_CLE			0x114 0x4f0 0x000 0x0 0x0
+#define MX51_PAD_NANDF_CLE__PATA_RESET_B		0x114 0x4f0 0x000 0x1 0x0
+#define MX51_PAD_NANDF_WP_B__GPIO3_7			0x118 0x4f4 0x990 0x3 0x0
+#define MX51_PAD_NANDF_WP_B__NANDF_WP_B			0x118 0x4f4 0x000 0x0 0x0
+#define MX51_PAD_NANDF_WP_B__PATA_DMACK			0x118 0x4f4 0x000 0x1 0x0
+#define MX51_PAD_NANDF_WP_B__SD3_DATA2			0x118 0x4f4 0x944 0x2 0x0
+#define MX51_PAD_NANDF_RB0__ECSPI2_SS1			0x11c 0x4f8 0x930 0x5 0x0
+#define MX51_PAD_NANDF_RB0__GPIO3_8			0x11c 0x4f8 0x994 0x3 0x0
+#define MX51_PAD_NANDF_RB0__NANDF_RB0			0x11c 0x4f8 0x000 0x0 0x0
+#define MX51_PAD_NANDF_RB0__PATA_DMARQ			0x11c 0x4f8 0x000 0x1 0x0
+#define MX51_PAD_NANDF_RB0__SD3_DATA3			0x11c 0x4f8 0x948 0x2 0x0
+#define MX51_PAD_NANDF_RB1__CSPI_MOSI			0x120 0x4fc 0x91c 0x6 0x0
+#define MX51_PAD_NANDF_RB1__ECSPI2_RDY			0x120 0x4fc 0x000 0x2 0x0
+#define MX51_PAD_NANDF_RB1__GPIO3_9			0x120 0x4fc 0x000 0x3 0x0
+#define MX51_PAD_NANDF_RB1__NANDF_RB1			0x120 0x4fc 0x000 0x0 0x0
+#define MX51_PAD_NANDF_RB1__PATA_IORDY			0x120 0x4fc 0x000 0x1 0x0
+#define MX51_PAD_NANDF_RB1__SD4_CMD			0x120 0x4fc 0x000 0x5 0x0
+#define MX51_PAD_NANDF_RB2__DISP2_WAIT			0x124 0x500 0x9a8 0x5 0x0
+#define MX51_PAD_NANDF_RB2__ECSPI2_SCLK			0x124 0x500 0x000 0x2 0x0
+#define MX51_PAD_NANDF_RB2__FEC_COL			0x124 0x500 0x94c 0x1 0x0
+#define MX51_PAD_NANDF_RB2__GPIO3_10			0x124 0x500 0x000 0x3 0x0
+#define MX51_PAD_NANDF_RB2__NANDF_RB2			0x124 0x500 0x000 0x0 0x0
+#define MX51_PAD_NANDF_RB2__USBH3_H3_DP			0x124 0x500 0x000 0x7 0x0
+#define MX51_PAD_NANDF_RB2__USBH3_NXT			0x124 0x500 0xa20 0x6 0x0
+#define MX51_PAD_NANDF_RB3__DISP1_WAIT			0x128 0x504 0x000 0x5 0x0
+#define MX51_PAD_NANDF_RB3__ECSPI2_MISO			0x128 0x504 0x000 0x2 0x0
+#define MX51_PAD_NANDF_RB3__FEC_RX_CLK			0x128 0x504 0x968 0x1 0x0
+#define MX51_PAD_NANDF_RB3__GPIO3_11			0x128 0x504 0x000 0x3 0x0
+#define MX51_PAD_NANDF_RB3__NANDF_RB3			0x128 0x504 0x000 0x0 0x0
+#define MX51_PAD_NANDF_RB3__USBH3_CLK			0x128 0x504 0x9f8 0x6 0x0
+#define MX51_PAD_NANDF_RB3__USBH3_H3_DM			0x128 0x504 0x000 0x7 0x0
+#define MX51_PAD_GPIO_NAND__GPIO_NAND			0x12c 0x514 0x998 0x0 0x0
+#define MX51_PAD_GPIO_NAND__PATA_INTRQ			0x12c 0x514 0x000 0x1 0x0
+#define MX51_PAD_NANDF_CS0__GPIO3_16			0x130 0x518 0x000 0x3 0x0
+#define MX51_PAD_NANDF_CS0__NANDF_CS0			0x130 0x518 0x000 0x0 0x0
+#define MX51_PAD_NANDF_CS1__GPIO3_17			0x134 0x51c 0x000 0x3 0x0
+#define MX51_PAD_NANDF_CS1__NANDF_CS1			0x134 0x51c 0x000 0x0 0x0
+#define MX51_PAD_NANDF_CS2__CSPI_SCLK			0x138 0x520 0x914 0x6 0x0
+#define MX51_PAD_NANDF_CS2__FEC_TX_ER			0x138 0x520 0x000 0x2 0x0
+#define MX51_PAD_NANDF_CS2__GPIO3_18			0x138 0x520 0x000 0x3 0x0
+#define MX51_PAD_NANDF_CS2__NANDF_CS2			0x138 0x520 0x000 0x0 0x0
+#define MX51_PAD_NANDF_CS2__PATA_CS_0			0x138 0x520 0x000 0x1 0x0
+#define MX51_PAD_NANDF_CS2__SD4_CLK			0x138 0x520 0x000 0x5 0x0
+#define MX51_PAD_NANDF_CS2__USBH3_H1_DP			0x138 0x520 0x000 0x7 0x0
+#define MX51_PAD_NANDF_CS3__FEC_MDC			0x13c 0x524 0x000 0x2 0x0
+#define MX51_PAD_NANDF_CS3__GPIO3_19			0x13c 0x524 0x000 0x3 0x0
+#define MX51_PAD_NANDF_CS3__NANDF_CS3			0x13c 0x524 0x000 0x0 0x0
+#define MX51_PAD_NANDF_CS3__PATA_CS_1			0x13c 0x524 0x000 0x1 0x0
+#define MX51_PAD_NANDF_CS3__SD4_DAT0			0x13c 0x524 0x000 0x5 0x0
+#define MX51_PAD_NANDF_CS3__USBH3_H1_DM			0x13c 0x524 0x000 0x7 0x0
+#define MX51_PAD_NANDF_CS4__FEC_TDATA1			0x140 0x528 0x000 0x2 0x0
+#define MX51_PAD_NANDF_CS4__GPIO3_20			0x140 0x528 0x000 0x3 0x0
+#define MX51_PAD_NANDF_CS4__NANDF_CS4			0x140 0x528 0x000 0x0 0x0
+#define MX51_PAD_NANDF_CS4__PATA_DA_0			0x140 0x528 0x000 0x1 0x0
+#define MX51_PAD_NANDF_CS4__SD4_DAT1			0x140 0x528 0x000 0x5 0x0
+#define MX51_PAD_NANDF_CS4__USBH3_STP			0x140 0x528 0xa24 0x7 0x0
+#define MX51_PAD_NANDF_CS5__FEC_TDATA2			0x144 0x52c 0x000 0x2 0x0
+#define MX51_PAD_NANDF_CS5__GPIO3_21			0x144 0x52c 0x000 0x3 0x0
+#define MX51_PAD_NANDF_CS5__NANDF_CS5			0x144 0x52c 0x000 0x0 0x0
+#define MX51_PAD_NANDF_CS5__PATA_DA_1			0x144 0x52c 0x000 0x1 0x0
+#define MX51_PAD_NANDF_CS5__SD4_DAT2			0x144 0x52c 0x000 0x5 0x0
+#define MX51_PAD_NANDF_CS5__USBH3_DIR			0x144 0x52c 0xa1c 0x7 0x0
+#define MX51_PAD_NANDF_CS6__CSPI_SS3			0x148 0x530 0x928 0x7 0x0
+#define MX51_PAD_NANDF_CS6__FEC_TDATA3			0x148 0x530 0x000 0x2 0x0
+#define MX51_PAD_NANDF_CS6__GPIO3_22			0x148 0x530 0x000 0x3 0x0
+#define MX51_PAD_NANDF_CS6__NANDF_CS6			0x148 0x530 0x000 0x0 0x0
+#define MX51_PAD_NANDF_CS6__PATA_DA_2			0x148 0x530 0x000 0x1 0x0
+#define MX51_PAD_NANDF_CS6__SD4_DAT3			0x148 0x530 0x000 0x5 0x0
+#define MX51_PAD_NANDF_CS7__FEC_TX_EN			0x14c 0x534 0x000 0x1 0x0
+#define MX51_PAD_NANDF_CS7__GPIO3_23			0x14c 0x534 0x000 0x3 0x0
+#define MX51_PAD_NANDF_CS7__NANDF_CS7			0x14c 0x534 0x000 0x0 0x0
+#define MX51_PAD_NANDF_CS7__SD3_CLK			0x14c 0x534 0x000 0x5 0x0
+#define MX51_PAD_NANDF_RDY_INT__ECSPI2_SS0		0x150 0x538 0x000 0x2 0x0
+#define MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK		0x150 0x538 0x974 0x1 0x0
+#define MX51_PAD_NANDF_RDY_INT__GPIO3_24		0x150 0x538 0x000 0x3 0x0
+#define MX51_PAD_NANDF_RDY_INT__NANDF_RDY_INT		0x150 0x538 0x938 0x0 0x0
+#define MX51_PAD_NANDF_RDY_INT__SD3_CMD			0x150 0x538 0x000 0x5 0x0
+#define MX51_PAD_NANDF_D15__ECSPI2_MOSI			0x154 0x53c 0x000 0x2 0x0
+#define MX51_PAD_NANDF_D15__GPIO3_25			0x154 0x53c 0x000 0x3 0x0
+#define MX51_PAD_NANDF_D15__NANDF_D15			0x154 0x53c 0x000 0x0 0x0
+#define MX51_PAD_NANDF_D15__PATA_DATA15			0x154 0x53c 0x000 0x1 0x0
+#define MX51_PAD_NANDF_D15__SD3_DAT7			0x154 0x53c 0x000 0x5 0x0
+#define MX51_PAD_NANDF_D14__ECSPI2_SS3			0x158 0x540 0x934 0x2 0x0
+#define MX51_PAD_NANDF_D14__GPIO3_26			0x158 0x540 0x000 0x3 0x0
+#define MX51_PAD_NANDF_D14__NANDF_D14			0x158 0x540 0x000 0x0 0x0
+#define MX51_PAD_NANDF_D14__PATA_DATA14			0x158 0x540 0x000 0x1 0x0
+#define MX51_PAD_NANDF_D14__SD3_DAT6			0x158 0x540 0x000 0x5 0x0
+#define MX51_PAD_NANDF_D13__ECSPI2_SS2			0x15c 0x544 0x000 0x2 0x0
+#define MX51_PAD_NANDF_D13__GPIO3_27			0x15c 0x544 0x000 0x3 0x0
+#define MX51_PAD_NANDF_D13__NANDF_D13			0x15c 0x544 0x000 0x0 0x0
+#define MX51_PAD_NANDF_D13__PATA_DATA13			0x15c 0x544 0x000 0x1 0x0
+#define MX51_PAD_NANDF_D13__SD3_DAT5			0x15c 0x544 0x000 0x5 0x0
+#define MX51_PAD_NANDF_D12__ECSPI2_SS1			0x160 0x548 0x930 0x2 0x1
+#define MX51_PAD_NANDF_D12__GPIO3_28			0x160 0x548 0x000 0x3 0x0
+#define MX51_PAD_NANDF_D12__NANDF_D12			0x160 0x548 0x000 0x0 0x0
+#define MX51_PAD_NANDF_D12__PATA_DATA12			0x160 0x548 0x000 0x1 0x0
+#define MX51_PAD_NANDF_D12__SD3_DAT4			0x160 0x548 0x000 0x5 0x0
+#define MX51_PAD_NANDF_D11__FEC_RX_DV			0x164 0x54c 0x96c 0x2 0x0
+#define MX51_PAD_NANDF_D11__GPIO3_29			0x164 0x54c 0x000 0x3 0x0
+#define MX51_PAD_NANDF_D11__NANDF_D11			0x164 0x54c 0x000 0x0 0x0
+#define MX51_PAD_NANDF_D11__PATA_DATA11			0x164 0x54c 0x000 0x1 0x0
+#define MX51_PAD_NANDF_D11__SD3_DATA3			0x164 0x54c 0x948 0x5 0x1
+#define MX51_PAD_NANDF_D10__GPIO3_30			0x168 0x550 0x000 0x3 0x0
+#define MX51_PAD_NANDF_D10__NANDF_D10			0x168 0x550 0x000 0x0 0x0
+#define MX51_PAD_NANDF_D10__PATA_DATA10			0x168 0x550 0x000 0x1 0x0
+#define MX51_PAD_NANDF_D10__SD3_DATA2			0x168 0x550 0x944 0x5 0x1
+#define MX51_PAD_NANDF_D9__FEC_RDATA0			0x16c 0x554 0x958 0x2 0x0
+#define MX51_PAD_NANDF_D9__GPIO3_31			0x16c 0x554 0x000 0x3 0x0
+#define MX51_PAD_NANDF_D9__NANDF_D9			0x16c 0x554 0x000 0x0 0x0
+#define MX51_PAD_NANDF_D9__PATA_DATA9			0x16c 0x554 0x000 0x1 0x0
+#define MX51_PAD_NANDF_D9__SD3_DATA1			0x16c 0x554 0x940 0x5 0x1
+#define MX51_PAD_NANDF_D8__FEC_TDATA0			0x170 0x558 0x000 0x2 0x0
+#define MX51_PAD_NANDF_D8__GPIO4_0			0x170 0x558 0x000 0x3 0x0
+#define MX51_PAD_NANDF_D8__NANDF_D8			0x170 0x558 0x000 0x0 0x0
+#define MX51_PAD_NANDF_D8__PATA_DATA8			0x170 0x558 0x000 0x1 0x0
+#define MX51_PAD_NANDF_D8__SD3_DATA0			0x170 0x558 0x93c 0x5 0x1
+#define MX51_PAD_NANDF_D7__GPIO4_1			0x174 0x55c 0x000 0x3 0x0
+#define MX51_PAD_NANDF_D7__NANDF_D7			0x174 0x55c 0x000 0x0 0x0
+#define MX51_PAD_NANDF_D7__PATA_DATA7			0x174 0x55c 0x000 0x1 0x0
+#define MX51_PAD_NANDF_D7__USBH3_DATA0			0x174 0x55c 0x9fc 0x5 0x0
+#define MX51_PAD_NANDF_D6__GPIO4_2			0x178 0x560 0x000 0x3 0x0
+#define MX51_PAD_NANDF_D6__NANDF_D6			0x178 0x560 0x000 0x0 0x0
+#define MX51_PAD_NANDF_D6__PATA_DATA6			0x178 0x560 0x000 0x1 0x0
+#define MX51_PAD_NANDF_D6__SD4_LCTL			0x178 0x560 0x000 0x2 0x0
+#define MX51_PAD_NANDF_D6__USBH3_DATA1			0x178 0x560 0xa00 0x5 0x0
+#define MX51_PAD_NANDF_D5__GPIO4_3			0x17c 0x564 0x000 0x3 0x0
+#define MX51_PAD_NANDF_D5__NANDF_D5			0x17c 0x564 0x000 0x0 0x0
+#define MX51_PAD_NANDF_D5__PATA_DATA5			0x17c 0x564 0x000 0x1 0x0
+#define MX51_PAD_NANDF_D5__SD4_WP			0x17c 0x564 0x000 0x2 0x0
+#define MX51_PAD_NANDF_D5__USBH3_DATA2			0x17c 0x564 0xa04 0x5 0x0
+#define MX51_PAD_NANDF_D4__GPIO4_4			0x180 0x568 0x000 0x3 0x0
+#define MX51_PAD_NANDF_D4__NANDF_D4			0x180 0x568 0x000 0x0 0x0
+#define MX51_PAD_NANDF_D4__PATA_DATA4			0x180 0x568 0x000 0x1 0x0
+#define MX51_PAD_NANDF_D4__SD4_CD			0x180 0x568 0x000 0x2 0x0
+#define MX51_PAD_NANDF_D4__USBH3_DATA3			0x180 0x568 0xa08 0x5 0x0
+#define MX51_PAD_NANDF_D3__GPIO4_5			0x184 0x56c 0x000 0x3 0x0
+#define MX51_PAD_NANDF_D3__NANDF_D3			0x184 0x56c 0x000 0x0 0x0
+#define MX51_PAD_NANDF_D3__PATA_DATA3			0x184 0x56c 0x000 0x1 0x0
+#define MX51_PAD_NANDF_D3__SD4_DAT4			0x184 0x56c 0x000 0x2 0x0
+#define MX51_PAD_NANDF_D3__USBH3_DATA4			0x184 0x56c 0xa0c 0x5 0x0
+#define MX51_PAD_NANDF_D2__GPIO4_6			0x188 0x570 0x000 0x3 0x0
+#define MX51_PAD_NANDF_D2__NANDF_D2			0x188 0x570 0x000 0x0 0x0
+#define MX51_PAD_NANDF_D2__PATA_DATA2			0x188 0x570 0x000 0x1 0x0
+#define MX51_PAD_NANDF_D2__SD4_DAT5			0x188 0x570 0x000 0x2 0x0
+#define MX51_PAD_NANDF_D2__USBH3_DATA5			0x188 0x570 0xa10 0x5 0x0
+#define MX51_PAD_NANDF_D1__GPIO4_7			0x18c 0x574 0x000 0x3 0x0
+#define MX51_PAD_NANDF_D1__NANDF_D1			0x18c 0x574 0x000 0x0 0x0
+#define MX51_PAD_NANDF_D1__PATA_DATA1			0x18c 0x574 0x000 0x1 0x0
+#define MX51_PAD_NANDF_D1__SD4_DAT6			0x18c 0x574 0x000 0x2 0x0
+#define MX51_PAD_NANDF_D1__USBH3_DATA6			0x18c 0x574 0xa14 0x5 0x0
+#define MX51_PAD_NANDF_D0__GPIO4_8			0x190 0x578 0x000 0x3 0x0
+#define MX51_PAD_NANDF_D0__NANDF_D0			0x190 0x578 0x000 0x0 0x0
+#define MX51_PAD_NANDF_D0__PATA_DATA0			0x190 0x578 0x000 0x1 0x0
+#define MX51_PAD_NANDF_D0__SD4_DAT7			0x190 0x578 0x000 0x2 0x0
+#define MX51_PAD_NANDF_D0__USBH3_DATA7			0x190 0x578 0xa18 0x5 0x0
+#define MX51_PAD_CSI1_D8__CSI1_D8			0x194 0x57c 0x000 0x0 0x0
+#define MX51_PAD_CSI1_D8__GPIO3_12			0x194 0x57c 0x998 0x3 0x1
+#define MX51_PAD_CSI1_D9__CSI1_D9			0x198 0x580 0x000 0x0 0x0
+#define MX51_PAD_CSI1_D9__GPIO3_13			0x198 0x580 0x000 0x3 0x0
+#define MX51_PAD_CSI1_D10__CSI1_D10			0x19c 0x584 0x000 0x0 0x0
+#define MX51_PAD_CSI1_D11__CSI1_D11			0x1a0 0x588 0x000 0x0 0x0
+#define MX51_PAD_CSI1_D12__CSI1_D12			0x1a4 0x58c 0x000 0x0 0x0
+#define MX51_PAD_CSI1_D13__CSI1_D13			0x1a8 0x590 0x000 0x0 0x0
+#define MX51_PAD_CSI1_D14__CSI1_D14			0x1ac 0x594 0x000 0x0 0x0
+#define MX51_PAD_CSI1_D15__CSI1_D15			0x1b0 0x598 0x000 0x0 0x0
+#define MX51_PAD_CSI1_D16__CSI1_D16			0x1b4 0x59c 0x000 0x0 0x0
+#define MX51_PAD_CSI1_D17__CSI1_D17			0x1b8 0x5a0 0x000 0x0 0x0
+#define MX51_PAD_CSI1_D18__CSI1_D18			0x1bc 0x5a4 0x000 0x0 0x0
+#define MX51_PAD_CSI1_D19__CSI1_D19			0x1c0 0x5a8 0x000 0x0 0x0
+#define MX51_PAD_CSI1_VSYNC__CSI1_VSYNC			0x1c4 0x5ac 0x000 0x0 0x0
+#define MX51_PAD_CSI1_VSYNC__GPIO3_14			0x1c4 0x5ac 0x000 0x3 0x0
+#define MX51_PAD_CSI1_HSYNC__CSI1_HSYNC			0x1c8 0x5b0 0x000 0x0 0x0
+#define MX51_PAD_CSI1_HSYNC__GPIO3_15			0x1c8 0x5b0 0x000 0x3 0x0
+#define MX51_PAD_CSI1_PIXCLK__CSI1_PIXCLK		0x000 0x5b4 0x000 0x0 0x0
+#define MX51_PAD_CSI1_MCLK__CSI1_MCLK			0x000 0x5b8 0x000 0x0 0x0
+#define MX51_PAD_CSI2_D12__CSI2_D12			0x1cc 0x5bc 0x000 0x0 0x0
+#define MX51_PAD_CSI2_D12__GPIO4_9			0x1cc 0x5bc 0x000 0x3 0x0
+#define MX51_PAD_CSI2_D13__CSI2_D13			0x1d0 0x5c0 0x000 0x0 0x0
+#define MX51_PAD_CSI2_D13__GPIO4_10			0x1d0 0x5c0 0x000 0x3 0x0
+#define MX51_PAD_CSI2_D14__CSI2_D14			0x1d4 0x5c4 0x000 0x0 0x0
+#define MX51_PAD_CSI2_D15__CSI2_D15			0x1d8 0x5c8 0x000 0x0 0x0
+#define MX51_PAD_CSI2_D16__CSI2_D16			0x1dc 0x5cc 0x000 0x0 0x0
+#define MX51_PAD_CSI2_D17__CSI2_D17			0x1e0 0x5d0 0x000 0x0 0x0
+#define MX51_PAD_CSI2_D18__CSI2_D18			0x1e4 0x5d4 0x000 0x0 0x0
+#define MX51_PAD_CSI2_D18__GPIO4_11			0x1e4 0x5d4 0x000 0x3 0x0
+#define MX51_PAD_CSI2_D19__CSI2_D19			0x1e8 0x5d8 0x000 0x0 0x0
+#define MX51_PAD_CSI2_D19__GPIO4_12			0x1e8 0x5d8 0x000 0x3 0x0
+#define MX51_PAD_CSI2_VSYNC__CSI2_VSYNC			0x1ec 0x5dc 0x000 0x0 0x0
+#define MX51_PAD_CSI2_VSYNC__GPIO4_13			0x1ec 0x5dc 0x000 0x3 0x0
+#define MX51_PAD_CSI2_HSYNC__CSI2_HSYNC			0x1f0 0x5e0 0x000 0x0 0x0
+#define MX51_PAD_CSI2_HSYNC__GPIO4_14			0x1f0 0x5e0 0x000 0x3 0x0
+#define MX51_PAD_CSI2_PIXCLK__CSI2_PIXCLK		0x1f4 0x5e4 0x000 0x0 0x0
+#define MX51_PAD_CSI2_PIXCLK__GPIO4_15			0x1f4 0x5e4 0x000 0x3 0x0
+#define MX51_PAD_I2C1_CLK__GPIO4_16			0x1f8 0x5e8 0x000 0x3 0x0
+#define MX51_PAD_I2C1_CLK__I2C1_CLK			0x1f8 0x5e8 0x000 0x0 0x0
+#define MX51_PAD_I2C1_DAT__GPIO4_17			0x1fc 0x5ec 0x000 0x3 0x0
+#define MX51_PAD_I2C1_DAT__I2C1_DAT			0x1fc 0x5ec 0x000 0x0 0x0
+#define MX51_PAD_AUD3_BB_TXD__AUD3_TXD			0x200 0x5f0 0x000 0x0 0x0
+#define MX51_PAD_AUD3_BB_TXD__GPIO4_18			0x200 0x5f0 0x000 0x3 0x0
+#define MX51_PAD_AUD3_BB_RXD__AUD3_RXD			0x204 0x5f4 0x000 0x0 0x0
+#define MX51_PAD_AUD3_BB_RXD__GPIO4_19			0x204 0x5f4 0x000 0x3 0x0
+#define MX51_PAD_AUD3_BB_RXD__UART3_RXD			0x204 0x5f4 0x9f4 0x1 0x2
+#define MX51_PAD_AUD3_BB_CK__AUD3_TXC			0x208 0x5f8 0x000 0x0 0x0
+#define MX51_PAD_AUD3_BB_CK__GPIO4_20			0x208 0x5f8 0x000 0x3 0x0
+#define MX51_PAD_AUD3_BB_FS__AUD3_TXFS			0x20c 0x5fc 0x000 0x0 0x0
+#define MX51_PAD_AUD3_BB_FS__GPIO4_21			0x20c 0x5fc 0x000 0x3 0x0
+#define MX51_PAD_AUD3_BB_FS__UART3_TXD			0x20c 0x5fc 0x000 0x1 0x0
+#define MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI		0x210 0x600 0x000 0x0 0x0
+#define MX51_PAD_CSPI1_MOSI__GPIO4_22			0x210 0x600 0x000 0x3 0x0
+#define MX51_PAD_CSPI1_MOSI__I2C1_SDA			0x210 0x600 0x9b4 0x1 0x1
+#define MX51_PAD_CSPI1_MISO__AUD4_RXD			0x214 0x604 0x8c4 0x1 0x1
+#define MX51_PAD_CSPI1_MISO__ECSPI1_MISO		0x214 0x604 0x000 0x0 0x0
+#define MX51_PAD_CSPI1_MISO__GPIO4_23			0x214 0x604 0x000 0x3 0x0
+#define MX51_PAD_CSPI1_SS0__AUD4_TXC			0x218 0x608 0x8cc 0x1 0x1
+#define MX51_PAD_CSPI1_SS0__ECSPI1_SS0			0x218 0x608 0x000 0x0 0x0
+#define MX51_PAD_CSPI1_SS0__GPIO4_24			0x218 0x608 0x000 0x3 0x0
+#define MX51_PAD_CSPI1_SS1__AUD4_TXD			0x21c 0x60c 0x8c8 0x1 0x1
+#define MX51_PAD_CSPI1_SS1__ECSPI1_SS1			0x21c 0x60c 0x000 0x0 0x0
+#define MX51_PAD_CSPI1_SS1__GPIO4_25			0x21c 0x60c 0x000 0x3 0x0
+#define MX51_PAD_CSPI1_RDY__AUD4_TXFS			0x220 0x610 0x8d0 0x1 0x1
+#define MX51_PAD_CSPI1_RDY__ECSPI1_RDY			0x220 0x610 0x000 0x0 0x0
+#define MX51_PAD_CSPI1_RDY__GPIO4_26			0x220 0x610 0x000 0x3 0x0
+#define MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK		0x224 0x614 0x000 0x0 0x0
+#define MX51_PAD_CSPI1_SCLK__GPIO4_27			0x224 0x614 0x000 0x3 0x0
+#define MX51_PAD_CSPI1_SCLK__I2C1_SCL			0x224 0x614 0x9b0 0x1 0x1
+#define MX51_PAD_UART1_RXD__GPIO4_28			0x228 0x618 0x000 0x3 0x0
+#define MX51_PAD_UART1_RXD__UART1_RXD			0x228 0x618 0x9e4 0x0 0x0
+#define MX51_PAD_UART1_TXD__GPIO4_29			0x22c 0x61c 0x000 0x3 0x0
+#define MX51_PAD_UART1_TXD__PWM2_PWMO			0x22c 0x61c 0x000 0x1 0x0
+#define MX51_PAD_UART1_TXD__UART1_TXD			0x22c 0x61c 0x000 0x0 0x0
+#define MX51_PAD_UART1_RTS__GPIO4_30			0x230 0x620 0x000 0x3 0x0
+#define MX51_PAD_UART1_RTS__UART1_RTS			0x230 0x620 0x9e0 0x0 0x0
+#define MX51_PAD_UART1_CTS__GPIO4_31			0x234 0x624 0x000 0x3 0x0
+#define MX51_PAD_UART1_CTS__UART1_CTS			0x234 0x624 0x000 0x0 0x0
+#define MX51_PAD_UART2_RXD__FIRI_TXD			0x238 0x628 0x000 0x1 0x0
+#define MX51_PAD_UART2_RXD__GPIO1_20			0x238 0x628 0x000 0x3 0x0
+#define MX51_PAD_UART2_RXD__UART2_RXD			0x238 0x628 0x9ec 0x0 0x2
+#define MX51_PAD_UART2_TXD__FIRI_RXD			0x23c 0x62c 0x000 0x1 0x0
+#define MX51_PAD_UART2_TXD__GPIO1_21			0x23c 0x62c 0x000 0x3 0x0
+#define MX51_PAD_UART2_TXD__UART2_TXD			0x23c 0x62c 0x000 0x0 0x0
+#define MX51_PAD_UART3_RXD__CSI1_D0			0x240 0x630 0x000 0x2 0x0
+#define MX51_PAD_UART3_RXD__GPIO1_22			0x240 0x630 0x000 0x3 0x0
+#define MX51_PAD_UART3_RXD__UART1_DTR			0x240 0x630 0x000 0x0 0x0
+#define MX51_PAD_UART3_RXD__UART3_RXD			0x240 0x630 0x9f4 0x1 0x4
+#define MX51_PAD_UART3_TXD__CSI1_D1			0x244 0x634 0x000 0x2 0x0
+#define MX51_PAD_UART3_TXD__GPIO1_23			0x244 0x634 0x000 0x3 0x0
+#define MX51_PAD_UART3_TXD__UART1_DSR			0x244 0x634 0x000 0x0 0x0
+#define MX51_PAD_UART3_TXD__UART3_TXD			0x244 0x634 0x000 0x1 0x0
+#define MX51_PAD_OWIRE_LINE__GPIO1_24			0x248 0x638 0x000 0x3 0x0
+#define MX51_PAD_OWIRE_LINE__OWIRE_LINE			0x248 0x638 0x000 0x0 0x0
+#define MX51_PAD_OWIRE_LINE__SPDIF_OUT			0x248 0x638 0x000 0x6 0x0
+#define MX51_PAD_KEY_ROW0__KEY_ROW0			0x24c 0x63c 0x000 0x0 0x0
+#define MX51_PAD_KEY_ROW1__KEY_ROW1			0x250 0x640 0x000 0x0 0x0
+#define MX51_PAD_KEY_ROW2__KEY_ROW2			0x254 0x644 0x000 0x0 0x0
+#define MX51_PAD_KEY_ROW3__KEY_ROW3			0x258 0x648 0x000 0x0 0x0
+#define MX51_PAD_KEY_COL0__KEY_COL0			0x25c 0x64c 0x000 0x0 0x0
+#define MX51_PAD_KEY_COL0__PLL1_BYP			0x25c 0x64c 0x90c 0x7 0x0
+#define MX51_PAD_KEY_COL1__KEY_COL1			0x260 0x650 0x000 0x0 0x0
+#define MX51_PAD_KEY_COL1__PLL2_BYP			0x260 0x650 0x910 0x7 0x0
+#define MX51_PAD_KEY_COL2__KEY_COL2			0x264 0x654 0x000 0x0 0x0
+#define MX51_PAD_KEY_COL2__PLL3_BYP			0x264 0x654 0x000 0x7 0x0
+#define MX51_PAD_KEY_COL3__KEY_COL3			0x268 0x658 0x000 0x0 0x0
+#define MX51_PAD_KEY_COL4__I2C2_SCL			0x26c 0x65c 0x9b8 0x3 0x1
+#define MX51_PAD_KEY_COL4__KEY_COL4			0x26c 0x65c 0x000 0x0 0x0
+#define MX51_PAD_KEY_COL4__SPDIF_OUT1			0x26c 0x65c 0x000 0x6 0x0
+#define MX51_PAD_KEY_COL4__UART1_RI			0x26c 0x65c 0x000 0x1 0x0
+#define MX51_PAD_KEY_COL4__UART3_RTS			0x26c 0x65c 0x9f0 0x2 0x4
+#define MX51_PAD_KEY_COL5__I2C2_SDA			0x270 0x660 0x9bc 0x3 0x1
+#define MX51_PAD_KEY_COL5__KEY_COL5			0x270 0x660 0x000 0x0 0x0
+#define MX51_PAD_KEY_COL5__UART1_DCD			0x270 0x660 0x000 0x1 0x0
+#define MX51_PAD_KEY_COL5__UART3_CTS			0x270 0x660 0x000 0x2 0x0
+#define MX51_PAD_USBH1_CLK__CSPI_SCLK			0x278 0x678 0x914 0x1 0x1
+#define MX51_PAD_USBH1_CLK__GPIO1_25			0x278 0x678 0x000 0x2 0x0
+#define MX51_PAD_USBH1_CLK__I2C2_SCL			0x278 0x678 0x9b8 0x5 0x2
+#define MX51_PAD_USBH1_CLK__USBH1_CLK			0x278 0x678 0x000 0x0 0x0
+#define MX51_PAD_USBH1_DIR__CSPI_MOSI			0x27c 0x67c 0x91c 0x1 0x1
+#define MX51_PAD_USBH1_DIR__GPIO1_26			0x27c 0x67c 0x000 0x2 0x0
+#define MX51_PAD_USBH1_DIR__I2C2_SDA			0x27c 0x67c 0x9bc 0x5 0x2
+#define MX51_PAD_USBH1_DIR__USBH1_DIR			0x27c 0x67c 0x000 0x0 0x0
+#define MX51_PAD_USBH1_STP__CSPI_RDY			0x280 0x680 0x000 0x1 0x0
+#define MX51_PAD_USBH1_STP__GPIO1_27			0x280 0x680 0x000 0x2 0x0
+#define MX51_PAD_USBH1_STP__UART3_RXD			0x280 0x680 0x9f4 0x5 0x6
+#define MX51_PAD_USBH1_STP__USBH1_STP			0x280 0x680 0x000 0x0 0x0
+#define MX51_PAD_USBH1_NXT__CSPI_MISO			0x284 0x684 0x918 0x1 0x0
+#define MX51_PAD_USBH1_NXT__GPIO1_28			0x284 0x684 0x000 0x2 0x0
+#define MX51_PAD_USBH1_NXT__UART3_TXD			0x284 0x684 0x000 0x5 0x0
+#define MX51_PAD_USBH1_NXT__USBH1_NXT			0x284 0x684 0x000 0x0 0x0
+#define MX51_PAD_USBH1_DATA0__GPIO1_11			0x288 0x688 0x000 0x2 0x0
+#define MX51_PAD_USBH1_DATA0__UART2_CTS			0x288 0x688 0x000 0x1 0x0
+#define MX51_PAD_USBH1_DATA0__USBH1_DATA0		0x288 0x688 0x000 0x0 0x0
+#define MX51_PAD_USBH1_DATA1__GPIO1_12			0x28c 0x68c 0x000 0x2 0x0
+#define MX51_PAD_USBH1_DATA1__UART2_RXD			0x28c 0x68c 0x9ec 0x1 0x4
+#define MX51_PAD_USBH1_DATA1__USBH1_DATA1		0x28c 0x68c 0x000 0x0 0x0
+#define MX51_PAD_USBH1_DATA2__GPIO1_13			0x290 0x690 0x000 0x2 0x0
+#define MX51_PAD_USBH1_DATA2__UART2_TXD			0x290 0x690 0x000 0x1 0x0
+#define MX51_PAD_USBH1_DATA2__USBH1_DATA2		0x290 0x690 0x000 0x0 0x0
+#define MX51_PAD_USBH1_DATA3__GPIO1_14			0x294 0x694 0x000 0x2 0x0
+#define MX51_PAD_USBH1_DATA3__UART2_RTS			0x294 0x694 0x9e8 0x1 0x5
+#define MX51_PAD_USBH1_DATA3__USBH1_DATA3		0x294 0x694 0x000 0x0 0x0
+#define MX51_PAD_USBH1_DATA4__CSPI_SS0			0x298 0x698 0x000 0x1 0x0
+#define MX51_PAD_USBH1_DATA4__GPIO1_15			0x298 0x698 0x000 0x2 0x0
+#define MX51_PAD_USBH1_DATA4__USBH1_DATA4		0x298 0x698 0x000 0x0 0x0
+#define MX51_PAD_USBH1_DATA5__CSPI_SS1			0x29c 0x69c 0x920 0x1 0x0
+#define MX51_PAD_USBH1_DATA5__GPIO1_16			0x29c 0x69c 0x000 0x2 0x0
+#define MX51_PAD_USBH1_DATA5__USBH1_DATA5		0x29c 0x69c 0x000 0x0 0x0
+#define MX51_PAD_USBH1_DATA6__CSPI_SS3			0x2a0 0x6a0 0x928 0x1 0x1
+#define MX51_PAD_USBH1_DATA6__GPIO1_17			0x2a0 0x6a0 0x000 0x2 0x0
+#define MX51_PAD_USBH1_DATA6__USBH1_DATA6		0x2a0 0x6a0 0x000 0x0 0x0
+#define MX51_PAD_USBH1_DATA7__ECSPI1_SS3		0x2a4 0x6a4 0x000 0x1 0x0
+#define MX51_PAD_USBH1_DATA7__ECSPI2_SS3		0x2a4 0x6a4 0x934 0x5 0x1
+#define MX51_PAD_USBH1_DATA7__GPIO1_18			0x2a4 0x6a4 0x000 0x2 0x0
+#define MX51_PAD_USBH1_DATA7__USBH1_DATA7		0x2a4 0x6a4 0x000 0x0 0x0
+#define MX51_PAD_DI1_PIN11__DI1_PIN11			0x2a8 0x6a8 0x000 0x0 0x0
+#define MX51_PAD_DI1_PIN11__ECSPI1_SS2			0x2a8 0x6a8 0x000 0x7 0x0
+#define MX51_PAD_DI1_PIN11__GPIO3_0			0x2a8 0x6a8 0x000 0x4 0x0
+#define MX51_PAD_DI1_PIN12__DI1_PIN12			0x2ac 0x6ac 0x000 0x0 0x0
+#define MX51_PAD_DI1_PIN12__GPIO3_1			0x2ac 0x6ac 0x978 0x4 0x1
+#define MX51_PAD_DI1_PIN13__DI1_PIN13			0x2b0 0x6b0 0x000 0x0 0x0
+#define MX51_PAD_DI1_PIN13__GPIO3_2			0x2b0 0x6b0 0x97c 0x4 0x1
+#define MX51_PAD_DI1_D0_CS__DI1_D0_CS			0x2b4 0x6b4 0x000 0x0 0x0
+#define MX51_PAD_DI1_D0_CS__GPIO3_3			0x2b4 0x6b4 0x980 0x4 0x1
+#define MX51_PAD_DI1_D1_CS__DI1_D1_CS			0x2b8 0x6b8 0x000 0x0 0x0
+#define MX51_PAD_DI1_D1_CS__DISP1_PIN14			0x2b8 0x6b8 0x000 0x2 0x0
+#define MX51_PAD_DI1_D1_CS__DISP1_PIN5			0x2b8 0x6b8 0x000 0x3 0x0
+#define MX51_PAD_DI1_D1_CS__GPIO3_4			0x2b8 0x6b8 0x984 0x4 0x1
+#define MX51_PAD_DISPB2_SER_DIN__DISP1_PIN1		0x2bc 0x6bc 0x9a4 0x2 0x1
+#define MX51_PAD_DISPB2_SER_DIN__DISPB2_SER_DIN		0x2bc 0x6bc 0x9c4 0x0 0x0
+#define MX51_PAD_DISPB2_SER_DIN__GPIO3_5		0x2bc 0x6bc 0x988 0x4 0x1
+#define MX51_PAD_DISPB2_SER_DIO__DISP1_PIN6		0x2c0 0x6c0 0x000 0x3 0x0
+#define MX51_PAD_DISPB2_SER_DIO__DISPB2_SER_DIO		0x2c0 0x6c0 0x9c4 0x0 0x1
+#define MX51_PAD_DISPB2_SER_DIO__GPIO3_6		0x2c0 0x6c0 0x98c 0x4 0x1
+#define MX51_PAD_DISPB2_SER_CLK__DISP1_PIN17		0x2c4 0x6c4 0x000 0x2 0x0
+#define MX51_PAD_DISPB2_SER_CLK__DISP1_PIN7		0x2c4 0x6c4 0x000 0x3 0x0
+#define MX51_PAD_DISPB2_SER_CLK__DISPB2_SER_CLK		0x2c4 0x6c4 0x000 0x0 0x0
+#define MX51_PAD_DISPB2_SER_CLK__GPIO3_7		0x2c4 0x6c4 0x990 0x4 0x1
+#define MX51_PAD_DISPB2_SER_RS__DISP1_PIN16		0x2c8 0x6c8 0x000 0x2 0x0
+#define MX51_PAD_DISPB2_SER_RS__DISP1_PIN8		0x2c8 0x6c8 0x000 0x3 0x0
+#define MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS		0x2c8 0x6c8 0x000 0x0 0x0
+#define MX51_PAD_DISPB2_SER_RS__GPIO3_8			0x2c8 0x6c8 0x994 0x4 0x1
+#define MX51_PAD_DISP1_DAT0__DISP1_DAT0			0x2cc 0x6cc 0x000 0x0 0x0
+#define MX51_PAD_DISP1_DAT1__DISP1_DAT1			0x2d0 0x6d0 0x000 0x0 0x0
+#define MX51_PAD_DISP1_DAT2__DISP1_DAT2			0x2d4 0x6d4 0x000 0x0 0x0
+#define MX51_PAD_DISP1_DAT3__DISP1_DAT3			0x2d8 0x6d8 0x000 0x0 0x0
+#define MX51_PAD_DISP1_DAT4__DISP1_DAT4			0x2dc 0x6dc 0x000 0x0 0x0
+#define MX51_PAD_DISP1_DAT5__DISP1_DAT5			0x2e0 0x6e0 0x000 0x0 0x0
+#define MX51_PAD_DISP1_DAT6__BOOT_USB_SRC		0x2e4 0x6e4 0x000 0x7 0x0
+#define MX51_PAD_DISP1_DAT6__DISP1_DAT6			0x2e4 0x6e4 0x000 0x0 0x0
+#define MX51_PAD_DISP1_DAT7__BOOT_EEPROM_CFG		0x2e8 0x6e8 0x000 0x7 0x0
+#define MX51_PAD_DISP1_DAT7__DISP1_DAT7			0x2e8 0x6e8 0x000 0x0 0x0
+#define MX51_PAD_DISP1_DAT8__BOOT_SRC0			0x2ec 0x6ec 0x000 0x7 0x0
+#define MX51_PAD_DISP1_DAT8__DISP1_DAT8			0x2ec 0x6ec 0x000 0x0 0x0
+#define MX51_PAD_DISP1_DAT9__BOOT_SRC1			0x2f0 0x6f0 0x000 0x7 0x0
+#define MX51_PAD_DISP1_DAT9__DISP1_DAT9			0x2f0 0x6f0 0x000 0x0 0x0
+#define MX51_PAD_DISP1_DAT10__BOOT_SPARE_SIZE		0x2f4 0x6f4 0x000 0x7 0x0
+#define MX51_PAD_DISP1_DAT10__DISP1_DAT10		0x2f4 0x6f4 0x000 0x0 0x0
+#define MX51_PAD_DISP1_DAT11__BOOT_LPB_FREQ2		0x2f8 0x6f8 0x000 0x7 0x0
+#define MX51_PAD_DISP1_DAT11__DISP1_DAT11		0x2f8 0x6f8 0x000 0x0 0x0
+#define MX51_PAD_DISP1_DAT12__BOOT_MLC_SEL		0x2fc 0x6fc 0x000 0x7 0x0
+#define MX51_PAD_DISP1_DAT12__DISP1_DAT12		0x2fc 0x6fc 0x000 0x0 0x0
+#define MX51_PAD_DISP1_DAT13__BOOT_MEM_CTL0		0x300 0x700 0x000 0x7 0x0
+#define MX51_PAD_DISP1_DAT13__DISP1_DAT13		0x300 0x700 0x000 0x0 0x0
+#define MX51_PAD_DISP1_DAT14__BOOT_MEM_CTL1		0x304 0x704 0x000 0x7 0x0
+#define MX51_PAD_DISP1_DAT14__DISP1_DAT14		0x304 0x704 0x000 0x0 0x0
+#define MX51_PAD_DISP1_DAT15__BOOT_BUS_WIDTH		0x308 0x708 0x000 0x7 0x0
+#define MX51_PAD_DISP1_DAT15__DISP1_DAT15		0x308 0x708 0x000 0x0 0x0
+#define MX51_PAD_DISP1_DAT16__BOOT_PAGE_SIZE0		0x30c 0x70c 0x000 0x7 0x0
+#define MX51_PAD_DISP1_DAT16__DISP1_DAT16		0x30c 0x70c 0x000 0x0 0x0
+#define MX51_PAD_DISP1_DAT17__BOOT_PAGE_SIZE1		0x310 0x710 0x000 0x7 0x0
+#define MX51_PAD_DISP1_DAT17__DISP1_DAT17		0x310 0x710 0x000 0x0 0x0
+#define MX51_PAD_DISP1_DAT18__BOOT_WEIM_MUXED0		0x314 0x714 0x000 0x7 0x0
+#define MX51_PAD_DISP1_DAT18__DISP1_DAT18		0x314 0x714 0x000 0x0 0x0
+#define MX51_PAD_DISP1_DAT18__DISP2_PIN11		0x314 0x714 0x000 0x5 0x0
+#define MX51_PAD_DISP1_DAT18__DISP2_PIN5		0x314 0x714 0x000 0x4 0x0
+#define MX51_PAD_DISP1_DAT19__BOOT_WEIM_MUXED1		0x318 0x718 0x000 0x7 0x0
+#define MX51_PAD_DISP1_DAT19__DISP1_DAT19		0x318 0x718 0x000 0x0 0x0
+#define MX51_PAD_DISP1_DAT19__DISP2_PIN12		0x318 0x718 0x000 0x5 0x0
+#define MX51_PAD_DISP1_DAT19__DISP2_PIN6		0x318 0x718 0x000 0x4 0x0
+#define MX51_PAD_DISP1_DAT20__BOOT_MEM_TYPE0		0x31c 0x71c 0x000 0x7 0x0
+#define MX51_PAD_DISP1_DAT20__DISP1_DAT20		0x31c 0x71c 0x000 0x0 0x0
+#define MX51_PAD_DISP1_DAT20__DISP2_PIN13		0x31c 0x71c 0x000 0x5 0x0
+#define MX51_PAD_DISP1_DAT20__DISP2_PIN7		0x31c 0x71c 0x000 0x4 0x0
+#define MX51_PAD_DISP1_DAT21__BOOT_MEM_TYPE1		0x320 0x720 0x000 0x7 0x0
+#define MX51_PAD_DISP1_DAT21__DISP1_DAT21		0x320 0x720 0x000 0x0 0x0
+#define MX51_PAD_DISP1_DAT21__DISP2_PIN14		0x320 0x720 0x000 0x5 0x0
+#define MX51_PAD_DISP1_DAT21__DISP2_PIN8		0x320 0x720 0x000 0x4 0x0
+#define MX51_PAD_DISP1_DAT22__BOOT_LPB_FREQ0		0x324 0x724 0x000 0x7 0x0
+#define MX51_PAD_DISP1_DAT22__DISP1_DAT22		0x324 0x724 0x000 0x0 0x0
+#define MX51_PAD_DISP1_DAT22__DISP2_D0_CS		0x324 0x724 0x000 0x6 0x0
+#define MX51_PAD_DISP1_DAT22__DISP2_DAT16		0x324 0x724 0x000 0x5 0x0
+#define MX51_PAD_DISP1_DAT23__BOOT_LPB_FREQ1		0x328 0x728 0x000 0x7 0x0
+#define MX51_PAD_DISP1_DAT23__DISP1_DAT23		0x328 0x728 0x000 0x0 0x0
+#define MX51_PAD_DISP1_DAT23__DISP2_D1_CS		0x328 0x728 0x000 0x6 0x0
+#define MX51_PAD_DISP1_DAT23__DISP2_DAT17		0x328 0x728 0x000 0x5 0x0
+#define MX51_PAD_DISP1_DAT23__DISP2_SER_CS		0x328 0x728 0x000 0x4 0x0
+#define MX51_PAD_DI1_PIN3__DI1_PIN3			0x32c 0x72c 0x000 0x0 0x0
+#define MX51_PAD_DI1_PIN2__DI1_PIN2			0x330 0x734 0x000 0x0 0x0
+#define MX51_PAD_DI_GP2__DISP1_SER_CLK			0x338 0x740 0x000 0x0 0x0
+#define MX51_PAD_DI_GP2__DISP2_WAIT			0x338 0x740 0x9a8 0x2 0x1
+#define MX51_PAD_DI_GP3__CSI1_DATA_EN			0x33c 0x744 0x9a0 0x3 0x1
+#define MX51_PAD_DI_GP3__DISP1_SER_DIO			0x33c 0x744 0x9c0 0x0 0x0
+#define MX51_PAD_DI_GP3__FEC_TX_ER			0x33c 0x744 0x000 0x2 0x0
+#define MX51_PAD_DI2_PIN4__CSI2_DATA_EN			0x340 0x748 0x99c 0x3 0x1
+#define MX51_PAD_DI2_PIN4__DI2_PIN4			0x340 0x748 0x000 0x0 0x0
+#define MX51_PAD_DI2_PIN4__FEC_CRS			0x340 0x748 0x950 0x2 0x1
+#define MX51_PAD_DI2_PIN2__DI2_PIN2			0x344 0x74c 0x000 0x0 0x0
+#define MX51_PAD_DI2_PIN2__FEC_MDC			0x344 0x74c 0x000 0x2 0x0
+#define MX51_PAD_DI2_PIN3__DI2_PIN3			0x348 0x750 0x000 0x0 0x0
+#define MX51_PAD_DI2_PIN3__FEC_MDIO			0x348 0x750 0x954 0x2 0x1
+#define MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK		0x34c 0x754 0x000 0x0 0x0
+#define MX51_PAD_DI2_DISP_CLK__FEC_RDATA1		0x34c 0x754 0x95c 0x2 0x1
+#define MX51_PAD_DI_GP4__DI2_PIN15			0x350 0x758 0x000 0x4 0x0
+#define MX51_PAD_DI_GP4__DISP1_SER_DIN			0x350 0x758 0x9c0 0x0 0x1
+#define MX51_PAD_DI_GP4__DISP2_PIN1			0x350 0x758 0x000 0x3 0x0
+#define MX51_PAD_DI_GP4__FEC_RDATA2			0x350 0x758 0x960 0x2 0x1
+#define MX51_PAD_DISP2_DAT0__DISP2_DAT0			0x354 0x75c 0x000 0x0 0x0
+#define MX51_PAD_DISP2_DAT0__FEC_RDATA3			0x354 0x75c 0x964 0x2 0x1
+#define MX51_PAD_DISP2_DAT0__KEY_COL6			0x354 0x75c 0x9c8 0x4 0x1
+#define MX51_PAD_DISP2_DAT0__UART3_RXD			0x354 0x75c 0x9f4 0x5 0x8
+#define MX51_PAD_DISP2_DAT0__USBH3_CLK			0x354 0x75c 0x9f8 0x3 0x1
+#define MX51_PAD_DISP2_DAT1__DISP2_DAT1			0x358 0x760 0x000 0x0 0x0
+#define MX51_PAD_DISP2_DAT1__FEC_RX_ER			0x358 0x760 0x970 0x2 0x1
+#define MX51_PAD_DISP2_DAT1__KEY_COL7			0x358 0x760 0x9cc 0x4 0x1
+#define MX51_PAD_DISP2_DAT1__UART3_TXD			0x358 0x760 0x000 0x5 0x0
+#define MX51_PAD_DISP2_DAT1__USBH3_DIR			0x358 0x760 0xa1c 0x3 0x1
+#define MX51_PAD_DISP2_DAT2__DISP2_DAT2			0x35c 0x764 0x000 0x0 0x0
+#define MX51_PAD_DISP2_DAT3__DISP2_DAT3			0x360 0x768 0x000 0x0 0x0
+#define MX51_PAD_DISP2_DAT4__DISP2_DAT4			0x364 0x76c 0x000 0x0 0x0
+#define MX51_PAD_DISP2_DAT5__DISP2_DAT5			0x368 0x770 0x000 0x0 0x0
+#define MX51_PAD_DISP2_DAT6__DISP2_DAT6			0x36c 0x774 0x000 0x0 0x0
+#define MX51_PAD_DISP2_DAT6__FEC_TDATA1			0x36c 0x774 0x000 0x2 0x0
+#define MX51_PAD_DISP2_DAT6__GPIO1_19			0x36c 0x774 0x000 0x5 0x0
+#define MX51_PAD_DISP2_DAT6__KEY_ROW4			0x36c 0x774 0x9d0 0x4 0x1
+#define MX51_PAD_DISP2_DAT6__USBH3_STP			0x36c 0x774 0xa24 0x3 0x1
+#define MX51_PAD_DISP2_DAT7__DISP2_DAT7			0x370 0x778 0x000 0x0 0x0
+#define MX51_PAD_DISP2_DAT7__FEC_TDATA2			0x370 0x778 0x000 0x2 0x0
+#define MX51_PAD_DISP2_DAT7__GPIO1_29			0x370 0x778 0x000 0x5 0x0
+#define MX51_PAD_DISP2_DAT7__KEY_ROW5			0x370 0x778 0x9d4 0x4 0x1
+#define MX51_PAD_DISP2_DAT7__USBH3_NXT			0x370 0x778 0xa20 0x3 0x1
+#define MX51_PAD_DISP2_DAT8__DISP2_DAT8			0x374 0x77c 0x000 0x0 0x0
+#define MX51_PAD_DISP2_DAT8__FEC_TDATA3			0x374 0x77c 0x000 0x2 0x0
+#define MX51_PAD_DISP2_DAT8__GPIO1_30			0x374 0x77c 0x000 0x5 0x0
+#define MX51_PAD_DISP2_DAT8__KEY_ROW6			0x374 0x77c 0x9d8 0x4 0x1
+#define MX51_PAD_DISP2_DAT8__USBH3_DATA0		0x374 0x77c 0x9fc 0x3 0x1
+#define MX51_PAD_DISP2_DAT9__AUD6_RXC			0x378 0x780 0x8f4 0x4 0x1
+#define MX51_PAD_DISP2_DAT9__DISP2_DAT9			0x378 0x780 0x000 0x0 0x0
+#define MX51_PAD_DISP2_DAT9__FEC_TX_EN			0x378 0x780 0x000 0x2 0x0
+#define MX51_PAD_DISP2_DAT9__GPIO1_31			0x378 0x780 0x000 0x5 0x0
+#define MX51_PAD_DISP2_DAT9__USBH3_DATA1		0x378 0x780 0xa00 0x3 0x1
+#define MX51_PAD_DISP2_DAT10__DISP2_DAT10		0x37c 0x784 0x000 0x0 0x0
+#define MX51_PAD_DISP2_DAT10__DISP2_SER_CS		0x37c 0x784 0x000 0x5 0x0
+#define MX51_PAD_DISP2_DAT10__FEC_COL			0x37c 0x784 0x94c 0x2 0x1
+#define MX51_PAD_DISP2_DAT10__KEY_ROW7			0x37c 0x784 0x9dc 0x4 0x1
+#define MX51_PAD_DISP2_DAT10__USBH3_DATA2		0x37c 0x784 0xa04 0x3 0x1
+#define MX51_PAD_DISP2_DAT11__AUD6_TXD			0x380 0x788 0x8f0 0x4 0x1
+#define MX51_PAD_DISP2_DAT11__DISP2_DAT11		0x380 0x788 0x000 0x0 0x0
+#define MX51_PAD_DISP2_DAT11__FEC_RX_CLK		0x380 0x788 0x968 0x2 0x1
+#define MX51_PAD_DISP2_DAT11__GPIO1_10			0x380 0x788 0x000 0x7 0x0
+#define MX51_PAD_DISP2_DAT11__USBH3_DATA3		0x380 0x788 0xa08 0x3 0x1
+#define MX51_PAD_DISP2_DAT12__AUD6_RXD			0x384 0x78c 0x8ec 0x4 0x1
+#define MX51_PAD_DISP2_DAT12__DISP2_DAT12		0x384 0x78c 0x000 0x0 0x0
+#define MX51_PAD_DISP2_DAT12__FEC_RX_DV			0x384 0x78c 0x96c 0x2 0x1
+#define MX51_PAD_DISP2_DAT12__USBH3_DATA4		0x384 0x78c 0xa0c 0x3 0x1
+#define MX51_PAD_DISP2_DAT13__AUD6_TXC			0x388 0x790 0x8fc 0x4 0x1
+#define MX51_PAD_DISP2_DAT13__DISP2_DAT13		0x388 0x790 0x000 0x0 0x0
+#define MX51_PAD_DISP2_DAT13__FEC_TX_CLK		0x388 0x790 0x974 0x2 0x1
+#define MX51_PAD_DISP2_DAT13__USBH3_DATA5		0x388 0x790 0xa10 0x3 0x1
+#define MX51_PAD_DISP2_DAT14__AUD6_TXFS			0x38c 0x794 0x900 0x4 0x1
+#define MX51_PAD_DISP2_DAT14__DISP2_DAT14		0x38c 0x794 0x000 0x0 0x0
+#define MX51_PAD_DISP2_DAT14__FEC_RDATA0		0x38c 0x794 0x958 0x2 0x1
+#define MX51_PAD_DISP2_DAT14__USBH3_DATA6		0x38c 0x794 0xa14 0x3 0x1
+#define MX51_PAD_DISP2_DAT15__AUD6_RXFS			0x390 0x798 0x8f8 0x4 0x1
+#define MX51_PAD_DISP2_DAT15__DISP1_SER_CS		0x390 0x798 0x000 0x5 0x0
+#define MX51_PAD_DISP2_DAT15__DISP2_DAT15		0x390 0x798 0x000 0x0 0x0
+#define MX51_PAD_DISP2_DAT15__FEC_TDATA0		0x390 0x798 0x000 0x2 0x0
+#define MX51_PAD_DISP2_DAT15__USBH3_DATA7		0x390 0x798 0xa18 0x3 0x1
+#define MX51_PAD_SD1_CMD__AUD5_RXFS			0x394 0x79c 0x8e0 0x1 0x1
+#define MX51_PAD_SD1_CMD__CSPI_MOSI			0x394 0x79c 0x91c 0x2 0x2
+#define MX51_PAD_SD1_CMD__SD1_CMD			0x394 0x79c 0x000 0x0 0x0
+#define MX51_PAD_SD1_CLK__AUD5_RXC			0x398 0x7a0 0x8dc 0x1 0x1
+#define MX51_PAD_SD1_CLK__CSPI_SCLK			0x398 0x7a0 0x914 0x2 0x2
+#define MX51_PAD_SD1_CLK__SD1_CLK			0x398 0x7a0 0x000 0x0 0x0
+#define MX51_PAD_SD1_DATA0__AUD5_TXD			0x39c 0x7a4 0x8d8 0x1 0x2
+#define MX51_PAD_SD1_DATA0__CSPI_MISO			0x39c 0x7a4 0x918 0x2 0x1
+#define MX51_PAD_SD1_DATA0__SD1_DATA0			0x39c 0x7a4 0x000 0x0 0x0
+#define MX51_PAD_EIM_DA0__EIM_DA0			0x01c 0x000 0x000 0x0 0x0
+#define MX51_PAD_EIM_DA1__EIM_DA1			0x020 0x000 0x000 0x0 0x0
+#define MX51_PAD_EIM_DA2__EIM_DA2			0x024 0x000 0x000 0x0 0x0
+#define MX51_PAD_EIM_DA3__EIM_DA3			0x028 0x000 0x000 0x0 0x0
+#define MX51_PAD_SD1_DATA1__AUD5_RXD			0x3a0 0x7a8 0x8d4 0x1 0x2
+#define MX51_PAD_SD1_DATA1__SD1_DATA1			0x3a0 0x7a8 0x000 0x0 0x0
+#define MX51_PAD_EIM_DA4__EIM_DA4			0x02c 0x000 0x000 0x0 0x0
+#define MX51_PAD_EIM_DA5__EIM_DA5			0x030 0x000 0x000 0x0 0x0
+#define MX51_PAD_EIM_DA6__EIM_DA6			0x034 0x000 0x000 0x0 0x0
+#define MX51_PAD_EIM_DA7__EIM_DA7			0x038 0x000 0x000 0x0 0x0
+#define MX51_PAD_SD1_DATA2__AUD5_TXC			0x3a4 0x7ac 0x8e4 0x1 0x2
+#define MX51_PAD_SD1_DATA2__SD1_DATA2			0x3a4 0x7ac 0x000 0x0 0x0
+#define MX51_PAD_EIM_DA10__EIM_DA10			0x044 0x000 0x000 0x0 0x0
+#define MX51_PAD_EIM_DA11__EIM_DA11			0x048 0x000 0x000 0x0 0x0
+#define MX51_PAD_EIM_DA8__EIM_DA8			0x03c 0x000 0x000 0x0 0x0
+#define MX51_PAD_EIM_DA9__EIM_DA9			0x040 0x000 0x000 0x0 0x0
+#define MX51_PAD_SD1_DATA3__AUD5_TXFS			0x3a8 0x7b0 0x8e8 0x1 0x2
+#define MX51_PAD_SD1_DATA3__CSPI_SS1			0x3a8 0x7b0 0x920 0x2 0x1
+#define MX51_PAD_SD1_DATA3__SD1_DATA3			0x3a8 0x7b0 0x000 0x0 0x0
+#define MX51_PAD_GPIO1_0__CSPI_SS2			0x3ac 0x7b4 0x924 0x2 0x0
+#define MX51_PAD_GPIO1_0__GPIO1_0			0x3ac 0x7b4 0x000 0x1 0x0
+#define MX51_PAD_GPIO1_0__SD1_CD			0x3ac 0x7b4 0x000 0x0 0x0
+#define MX51_PAD_GPIO1_1__CSPI_MISO			0x3b0 0x7b8 0x918 0x2 0x2
+#define MX51_PAD_GPIO1_1__GPIO1_1			0x3b0 0x7b8 0x000 0x1 0x0
+#define MX51_PAD_GPIO1_1__SD1_WP			0x3b0 0x7b8 0x000 0x0 0x0
+#define MX51_PAD_EIM_DA12__EIM_DA12			0x04c 0x000 0x000 0x0 0x0
+#define MX51_PAD_EIM_DA13__EIM_DA13			0x050 0x000 0x000 0x0 0x0
+#define MX51_PAD_EIM_DA14__EIM_DA14			0x054 0x000 0x000 0x0 0x0
+#define MX51_PAD_EIM_DA15__EIM_DA15			0x058 0x000 0x000 0x0 0x0
+#define MX51_PAD_SD2_CMD__CSPI_MOSI			0x3b4 0x7bc 0x91c 0x2 0x3
+#define MX51_PAD_SD2_CMD__I2C1_SCL			0x3b4 0x7bc 0x9b0 0x1 0x2
+#define MX51_PAD_SD2_CMD__SD2_CMD			0x3b4 0x7bc 0x000 0x0 0x0
+#define MX51_PAD_SD2_CLK__CSPI_SCLK			0x3b8 0x7c0 0x914 0x2 0x3
+#define MX51_PAD_SD2_CLK__I2C1_SDA			0x3b8 0x7c0 0x9b4 0x1 0x2
+#define MX51_PAD_SD2_CLK__SD2_CLK			0x3b8 0x7c0 0x000 0x0 0x0
+#define MX51_PAD_SD2_DATA0__CSPI_MISO			0x3bc 0x7c4 0x918 0x2 0x3
+#define MX51_PAD_SD2_DATA0__SD1_DAT4			0x3bc 0x7c4 0x000 0x1 0x0
+#define MX51_PAD_SD2_DATA0__SD2_DATA0			0x3bc 0x7c4 0x000 0x0 0x0
+#define MX51_PAD_SD2_DATA1__SD1_DAT5			0x3c0 0x7c8 0x000 0x1 0x0
+#define MX51_PAD_SD2_DATA1__SD2_DATA1			0x3c0 0x7c8 0x000 0x0 0x0
+#define MX51_PAD_SD2_DATA1__USBH3_H2_DP			0x3c0 0x7c8 0x000 0x2 0x0
+#define MX51_PAD_SD2_DATA2__SD1_DAT6			0x3c4 0x7cc 0x000 0x1 0x0
+#define MX51_PAD_SD2_DATA2__SD2_DATA2			0x3c4 0x7cc 0x000 0x0 0x0
+#define MX51_PAD_SD2_DATA2__USBH3_H2_DM			0x3c4 0x7cc 0x000 0x2 0x0
+#define MX51_PAD_SD2_DATA3__CSPI_SS2			0x3c8 0x7d0 0x924 0x2 0x1
+#define MX51_PAD_SD2_DATA3__SD1_DAT7			0x3c8 0x7d0 0x000 0x1 0x0
+#define MX51_PAD_SD2_DATA3__SD2_DATA3			0x3c8 0x7d0 0x000 0x0 0x0
+#define MX51_PAD_GPIO1_2__CCM_OUT_2			0x3cc 0x7d4 0x000 0x5 0x0
+#define MX51_PAD_GPIO1_2__GPIO1_2			0x3cc 0x7d4 0x000 0x0 0x0
+#define MX51_PAD_GPIO1_2__I2C2_SCL			0x3cc 0x7d4 0x9b8 0x2 0x3
+#define MX51_PAD_GPIO1_2__PLL1_BYP			0x3cc 0x7d4 0x90c 0x7 0x1
+#define MX51_PAD_GPIO1_2__PWM1_PWMO			0x3cc 0x7d4 0x000 0x1 0x0
+#define MX51_PAD_GPIO1_3__GPIO1_3			0x3d0 0x7d8 0x000 0x0 0x0
+#define MX51_PAD_GPIO1_3__I2C2_SDA			0x3d0 0x7d8 0x9bc 0x2 0x3
+#define MX51_PAD_GPIO1_3__PLL2_BYP			0x3d0 0x7d8 0x910 0x7 0x1
+#define MX51_PAD_GPIO1_3__PWM2_PWMO			0x3d0 0x7d8 0x000 0x1 0x0
+#define MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ		0x3d4 0x7fc 0x000 0x0 0x0
+#define MX51_PAD_PMIC_INT_REQ__PMIC_PMU_IRQ_B		0x3d4 0x7fc 0x000 0x1 0x0
+#define MX51_PAD_GPIO1_4__DISP2_EXT_CLK			0x3d8 0x804 0x908 0x4 0x1
+#define MX51_PAD_GPIO1_4__EIM_RDY			0x3d8 0x804 0x938 0x3 0x1
+#define MX51_PAD_GPIO1_4__GPIO1_4			0x3d8 0x804 0x000 0x0 0x0
+#define MX51_PAD_GPIO1_4__WDOG1_WDOG_B			0x3d8 0x804 0x000 0x2 0x0
+#define MX51_PAD_GPIO1_5__CSI2_MCLK			0x3dc 0x808 0x000 0x6 0x0
+#define MX51_PAD_GPIO1_5__DISP2_PIN16			0x3dc 0x808 0x000 0x3 0x0
+#define MX51_PAD_GPIO1_5__GPIO1_5			0x3dc 0x808 0x000 0x0 0x0
+#define MX51_PAD_GPIO1_5__WDOG2_WDOG_B			0x3dc 0x808 0x000 0x2 0x0
+#define MX51_PAD_GPIO1_6__DISP2_PIN17			0x3e0 0x80c 0x000 0x4 0x0
+#define MX51_PAD_GPIO1_6__GPIO1_6			0x3e0 0x80c 0x000 0x0 0x0
+#define MX51_PAD_GPIO1_6__REF_EN_B			0x3e0 0x80c 0x000 0x3 0x0
+#define MX51_PAD_GPIO1_7__CCM_OUT_0			0x3e4 0x810 0x000 0x3 0x0
+#define MX51_PAD_GPIO1_7__GPIO1_7			0x3e4 0x810 0x000 0x0 0x0
+#define MX51_PAD_GPIO1_7__SD2_WP			0x3e4 0x810 0x000 0x6 0x0
+#define MX51_PAD_GPIO1_7__SPDIF_OUT1			0x3e4 0x810 0x000 0x2 0x0
+#define MX51_PAD_GPIO1_8__CSI2_DATA_EN			0x3e8 0x814 0x99c 0x2 0x2
+#define MX51_PAD_GPIO1_8__GPIO1_8			0x3e8 0x814 0x000 0x0 0x0
+#define MX51_PAD_GPIO1_8__SD2_CD			0x3e8 0x814 0x000 0x6 0x0
+#define MX51_PAD_GPIO1_8__USBH3_PWR			0x3e8 0x814 0x000 0x1 0x0
+#define MX51_PAD_GPIO1_9__CCM_OUT_1			0x3ec 0x818 0x000 0x3 0x0
+#define MX51_PAD_GPIO1_9__DISP2_D1_CS			0x3ec 0x818 0x000 0x2 0x0
+#define MX51_PAD_GPIO1_9__DISP2_SER_CS			0x3ec 0x818 0x000 0x7 0x0
+#define MX51_PAD_GPIO1_9__GPIO1_9			0x3ec 0x818 0x000 0x0 0x0
+#define MX51_PAD_GPIO1_9__SD2_LCTL			0x3ec 0x818 0x000 0x6 0x0
+#define MX51_PAD_GPIO1_9__USBH3_OC			0x3ec 0x818 0x000 0x1 0x0
+
+#endif /* __DTS_IMX51_PINFUNC_H */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/imx53-pinfunc.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/imx53-pinfunc.h
new file mode 100644
index 0000000000000000000000000000000000000000..59f9c29e3fe2ff37a626a2bdf51bdbff44d844cf
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/imx53-pinfunc.h
@@ -0,0 +1,1193 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __DTS_IMX53_PINFUNC_H
+#define __DTS_IMX53_PINFUNC_H
+
+/*
+ * The pin function ID is a tuple of
+ * <mux_reg conf_reg input_reg mux_mode input_val>
+ */
+#define MX53_PAD_GPIO_19__KPP_COL_5				0x020 0x348 0x840 0x0 0x0
+#define MX53_PAD_GPIO_19__GPIO4_5				0x020 0x348 0x000 0x1 0x0
+#define MX53_PAD_GPIO_19__CCM_CLKO				0x020 0x348 0x000 0x2 0x0
+#define MX53_PAD_GPIO_19__SPDIF_OUT1				0x020 0x348 0x000 0x3 0x0
+#define MX53_PAD_GPIO_19__RTC_CE_RTC_EXT_TRIG2			0x020 0x348 0x000 0x4 0x0
+#define MX53_PAD_GPIO_19__ECSPI1_RDY				0x020 0x348 0x000 0x5 0x0
+#define MX53_PAD_GPIO_19__FEC_TDATA_3				0x020 0x348 0x000 0x6 0x0
+#define MX53_PAD_GPIO_19__SRC_INT_BOOT				0x020 0x348 0x000 0x7 0x0
+#define MX53_PAD_KEY_COL0__KPP_COL_0				0x024 0x34c 0x000 0x0 0x0
+#define MX53_PAD_KEY_COL0__GPIO4_6				0x024 0x34c 0x000 0x1 0x0
+#define MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC			0x024 0x34c 0x758 0x2 0x0
+#define MX53_PAD_KEY_COL0__UART4_TXD_MUX			0x024 0x34c 0x000 0x4 0x0
+#define MX53_PAD_KEY_COL0__ECSPI1_SCLK				0x024 0x34c 0x79c 0x5 0x0
+#define MX53_PAD_KEY_COL0__FEC_RDATA_3				0x024 0x34c 0x000 0x6 0x0
+#define MX53_PAD_KEY_COL0__SRC_ANY_PU_RST			0x024 0x34c 0x000 0x7 0x0
+#define MX53_PAD_KEY_ROW0__KPP_ROW_0				0x028 0x350 0x000 0x0 0x0
+#define MX53_PAD_KEY_ROW0__GPIO4_7				0x028 0x350 0x000 0x1 0x0
+#define MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD			0x028 0x350 0x74c 0x2 0x0
+#define MX53_PAD_KEY_ROW0__UART4_RXD_MUX			0x028 0x350 0x890 0x4 0x1
+#define MX53_PAD_KEY_ROW0__ECSPI1_MOSI				0x028 0x350 0x7a4 0x5 0x0
+#define MX53_PAD_KEY_ROW0__FEC_TX_ER				0x028 0x350 0x000 0x6 0x0
+#define MX53_PAD_KEY_COL1__KPP_COL_1				0x02c 0x354 0x000 0x0 0x0
+#define MX53_PAD_KEY_COL1__GPIO4_8				0x02c 0x354 0x000 0x1 0x0
+#define MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS			0x02c 0x354 0x75c 0x2 0x0
+#define MX53_PAD_KEY_COL1__UART5_TXD_MUX			0x02c 0x354 0x000 0x4 0x0
+#define MX53_PAD_KEY_COL1__ECSPI1_MISO				0x02c 0x354 0x7a0 0x5 0x0
+#define MX53_PAD_KEY_COL1__FEC_RX_CLK				0x02c 0x354 0x808 0x6 0x0
+#define MX53_PAD_KEY_COL1__USBPHY1_TXREADY			0x02c 0x354 0x000 0x7 0x0
+#define MX53_PAD_KEY_ROW1__KPP_ROW_1				0x030 0x358 0x000 0x0 0x0
+#define MX53_PAD_KEY_ROW1__GPIO4_9				0x030 0x358 0x000 0x1 0x0
+#define MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD			0x030 0x358 0x748 0x2 0x0
+#define MX53_PAD_KEY_ROW1__UART5_RXD_MUX			0x030 0x358 0x898 0x4 0x1
+#define MX53_PAD_KEY_ROW1__ECSPI1_SS0				0x030 0x358 0x7a8 0x5 0x0
+#define MX53_PAD_KEY_ROW1__FEC_COL				0x030 0x358 0x800 0x6 0x0
+#define MX53_PAD_KEY_ROW1__USBPHY1_RXVALID			0x030 0x358 0x000 0x7 0x0
+#define MX53_PAD_KEY_COL2__KPP_COL_2				0x034 0x35c 0x000 0x0 0x0
+#define MX53_PAD_KEY_COL2__GPIO4_10				0x034 0x35c 0x000 0x1 0x0
+#define MX53_PAD_KEY_COL2__CAN1_TXCAN				0x034 0x35c 0x000 0x2 0x0
+#define MX53_PAD_KEY_COL2__FEC_MDIO				0x034 0x35c 0x804 0x4 0x0
+#define MX53_PAD_KEY_COL2__ECSPI1_SS1				0x034 0x35c 0x7ac 0x5 0x0
+#define MX53_PAD_KEY_COL2__FEC_RDATA_2				0x034 0x35c 0x000 0x6 0x0
+#define MX53_PAD_KEY_COL2__USBPHY1_RXACTIVE			0x034 0x35c 0x000 0x7 0x0
+#define MX53_PAD_KEY_ROW2__KPP_ROW_2				0x038 0x360 0x000 0x0 0x0
+#define MX53_PAD_KEY_ROW2__GPIO4_11				0x038 0x360 0x000 0x1 0x0
+#define MX53_PAD_KEY_ROW2__CAN1_RXCAN				0x038 0x360 0x760 0x2 0x0
+#define MX53_PAD_KEY_ROW2__FEC_MDC				0x038 0x360 0x000 0x4 0x0
+#define MX53_PAD_KEY_ROW2__ECSPI1_SS2				0x038 0x360 0x7b0 0x5 0x0
+#define MX53_PAD_KEY_ROW2__FEC_TDATA_2				0x038 0x360 0x000 0x6 0x0
+#define MX53_PAD_KEY_ROW2__USBPHY1_RXERROR			0x038 0x360 0x000 0x7 0x0
+#define MX53_PAD_KEY_COL3__KPP_COL_3				0x03c 0x364 0x000 0x0 0x0
+#define MX53_PAD_KEY_COL3__GPIO4_12				0x03c 0x364 0x000 0x1 0x0
+#define MX53_PAD_KEY_COL3__USBOH3_H2_DP				0x03c 0x364 0x000 0x2 0x0
+#define MX53_PAD_KEY_COL3__SPDIF_IN1				0x03c 0x364 0x870 0x3 0x0
+#define MX53_PAD_KEY_COL3__I2C2_SCL				0x03c 0x364 0x81c 0x4 0x0
+#define MX53_PAD_KEY_COL3__ECSPI1_SS3				0x03c 0x364 0x7b4 0x5 0x0
+#define MX53_PAD_KEY_COL3__FEC_CRS				0x03c 0x364 0x000 0x6 0x0
+#define MX53_PAD_KEY_COL3__USBPHY1_SIECLOCK			0x03c 0x364 0x000 0x7 0x0
+#define MX53_PAD_KEY_ROW3__KPP_ROW_3				0x040 0x368 0x000 0x0 0x0
+#define MX53_PAD_KEY_ROW3__GPIO4_13				0x040 0x368 0x000 0x1 0x0
+#define MX53_PAD_KEY_ROW3__USBOH3_H2_DM				0x040 0x368 0x000 0x2 0x0
+#define MX53_PAD_KEY_ROW3__CCM_ASRC_EXT_CLK			0x040 0x368 0x768 0x3 0x0
+#define MX53_PAD_KEY_ROW3__I2C2_SDA				0x040 0x368 0x820 0x4 0x0
+#define MX53_PAD_KEY_ROW3__OSC32K_32K_OUT			0x040 0x368 0x000 0x5 0x0
+#define MX53_PAD_KEY_ROW3__CCM_PLL4_BYP				0x040 0x368 0x77c 0x6 0x0
+#define MX53_PAD_KEY_ROW3__USBPHY1_LINESTATE_0			0x040 0x368 0x000 0x7 0x0
+#define MX53_PAD_KEY_COL4__KPP_COL_4				0x044 0x36c 0x000 0x0 0x0
+#define MX53_PAD_KEY_COL4__GPIO4_14				0x044 0x36c 0x000 0x1 0x0
+#define MX53_PAD_KEY_COL4__CAN2_TXCAN				0x044 0x36c 0x000 0x2 0x0
+#define MX53_PAD_KEY_COL4__IPU_SISG_4				0x044 0x36c 0x000 0x3 0x0
+#define MX53_PAD_KEY_COL4__UART5_RTS				0x044 0x36c 0x894 0x4 0x0
+#define MX53_PAD_KEY_COL4__USBOH3_USBOTG_OC			0x044 0x36c 0x89c 0x5 0x0
+#define MX53_PAD_KEY_COL4__USBPHY1_LINESTATE_1			0x044 0x36c 0x000 0x7 0x0
+#define MX53_PAD_KEY_ROW4__KPP_ROW_4				0x048 0x370 0x000 0x0 0x0
+#define MX53_PAD_KEY_ROW4__GPIO4_15				0x048 0x370 0x000 0x1 0x0
+#define MX53_PAD_KEY_ROW4__CAN2_RXCAN				0x048 0x370 0x764 0x2 0x0
+#define MX53_PAD_KEY_ROW4__IPU_SISG_5				0x048 0x370 0x000 0x3 0x0
+#define MX53_PAD_KEY_ROW4__UART5_CTS				0x048 0x370 0x000 0x4 0x0
+#define MX53_PAD_KEY_ROW4__USBOH3_USBOTG_PWR			0x048 0x370 0x000 0x5 0x0
+#define MX53_PAD_KEY_ROW4__USBPHY1_VBUSVALID			0x048 0x370 0x000 0x7 0x0
+#define MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK			0x04c 0x378 0x000 0x0 0x0
+#define MX53_PAD_DI0_DISP_CLK__GPIO4_16				0x04c 0x378 0x000 0x1 0x0
+#define MX53_PAD_DI0_DISP_CLK__USBOH3_USBH2_DIR			0x04c 0x378 0x000 0x2 0x0
+#define MX53_PAD_DI0_DISP_CLK__SDMA_DEBUG_CORE_STATE_0		0x04c 0x378 0x000 0x5 0x0
+#define MX53_PAD_DI0_DISP_CLK__EMI_EMI_DEBUG_0			0x04c 0x378 0x000 0x6 0x0
+#define MX53_PAD_DI0_DISP_CLK__USBPHY1_AVALID			0x04c 0x378 0x000 0x7 0x0
+#define MX53_PAD_DI0_PIN15__IPU_DI0_PIN15			0x050 0x37c 0x000 0x0 0x0
+#define MX53_PAD_DI0_PIN15__GPIO4_17				0x050 0x37c 0x000 0x1 0x0
+#define MX53_PAD_DI0_PIN15__AUDMUX_AUD6_TXC			0x050 0x37c 0x000 0x2 0x0
+#define MX53_PAD_DI0_PIN15__SDMA_DEBUG_CORE_STATE_1		0x050 0x37c 0x000 0x5 0x0
+#define MX53_PAD_DI0_PIN15__EMI_EMI_DEBUG_1			0x050 0x37c 0x000 0x6 0x0
+#define MX53_PAD_DI0_PIN15__USBPHY1_BVALID			0x050 0x37c 0x000 0x7 0x0
+#define MX53_PAD_DI0_PIN2__IPU_DI0_PIN2				0x054 0x380 0x000 0x0 0x0
+#define MX53_PAD_DI0_PIN2__GPIO4_18				0x054 0x380 0x000 0x1 0x0
+#define MX53_PAD_DI0_PIN2__AUDMUX_AUD6_TXD			0x054 0x380 0x000 0x2 0x0
+#define MX53_PAD_DI0_PIN2__SDMA_DEBUG_CORE_STATE_2		0x054 0x380 0x000 0x5 0x0
+#define MX53_PAD_DI0_PIN2__EMI_EMI_DEBUG_2			0x054 0x380 0x000 0x6 0x0
+#define MX53_PAD_DI0_PIN2__USBPHY1_ENDSESSION			0x054 0x380 0x000 0x7 0x0
+#define MX53_PAD_DI0_PIN3__IPU_DI0_PIN3				0x058 0x384 0x000 0x0 0x0
+#define MX53_PAD_DI0_PIN3__GPIO4_19				0x058 0x384 0x000 0x1 0x0
+#define MX53_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS			0x058 0x384 0x000 0x2 0x0
+#define MX53_PAD_DI0_PIN3__SDMA_DEBUG_CORE_STATE_3		0x058 0x384 0x000 0x5 0x0
+#define MX53_PAD_DI0_PIN3__EMI_EMI_DEBUG_3			0x058 0x384 0x000 0x6 0x0
+#define MX53_PAD_DI0_PIN3__USBPHY1_IDDIG			0x058 0x384 0x000 0x7 0x0
+#define MX53_PAD_DI0_PIN4__IPU_DI0_PIN4				0x05c 0x388 0x000 0x0 0x0
+#define MX53_PAD_DI0_PIN4__GPIO4_20				0x05c 0x388 0x000 0x1 0x0
+#define MX53_PAD_DI0_PIN4__AUDMUX_AUD6_RXD			0x05c 0x388 0x000 0x2 0x0
+#define MX53_PAD_DI0_PIN4__ESDHC1_WP				0x05c 0x388 0x7fc 0x3 0x0
+#define MX53_PAD_DI0_PIN4__SDMA_DEBUG_YIELD			0x05c 0x388 0x000 0x5 0x0
+#define MX53_PAD_DI0_PIN4__EMI_EMI_DEBUG_4			0x05c 0x388 0x000 0x6 0x0
+#define MX53_PAD_DI0_PIN4__USBPHY1_HOSTDISCONNECT		0x05c 0x388 0x000 0x7 0x0
+#define MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0			0x060 0x38c 0x000 0x0 0x0
+#define MX53_PAD_DISP0_DAT0__GPIO4_21				0x060 0x38c 0x000 0x1 0x0
+#define MX53_PAD_DISP0_DAT0__CSPI_SCLK				0x060 0x38c 0x780 0x2 0x0
+#define MX53_PAD_DISP0_DAT0__USBOH3_USBH2_DATA_0		0x060 0x38c 0x000 0x3 0x0
+#define MX53_PAD_DISP0_DAT0__SDMA_DEBUG_CORE_RUN		0x060 0x38c 0x000 0x5 0x0
+#define MX53_PAD_DISP0_DAT0__EMI_EMI_DEBUG_5			0x060 0x38c 0x000 0x6 0x0
+#define MX53_PAD_DISP0_DAT0__USBPHY2_TXREADY			0x060 0x38c 0x000 0x7 0x0
+#define MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1			0x064 0x390 0x000 0x0 0x0
+#define MX53_PAD_DISP0_DAT1__GPIO4_22				0x064 0x390 0x000 0x1 0x0
+#define MX53_PAD_DISP0_DAT1__CSPI_MOSI				0x064 0x390 0x788 0x2 0x0
+#define MX53_PAD_DISP0_DAT1__USBOH3_USBH2_DATA_1		0x064 0x390 0x000 0x3 0x0
+#define MX53_PAD_DISP0_DAT1__SDMA_DEBUG_EVENT_CHANNEL_SEL	0x064 0x390 0x000 0x5 0x0
+#define MX53_PAD_DISP0_DAT1__EMI_EMI_DEBUG_6			0x064 0x390 0x000 0x6 0x0
+#define MX53_PAD_DISP0_DAT1__USBPHY2_RXVALID			0x064 0x390 0x000 0x7 0x0
+#define MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2			0x068 0x394 0x000 0x0 0x0
+#define MX53_PAD_DISP0_DAT2__GPIO4_23				0x068 0x394 0x000 0x1 0x0
+#define MX53_PAD_DISP0_DAT2__CSPI_MISO				0x068 0x394 0x784 0x2 0x0
+#define MX53_PAD_DISP0_DAT2__USBOH3_USBH2_DATA_2		0x068 0x394 0x000 0x3 0x0
+#define MX53_PAD_DISP0_DAT2__SDMA_DEBUG_MODE			0x068 0x394 0x000 0x5 0x0
+#define MX53_PAD_DISP0_DAT2__EMI_EMI_DEBUG_7			0x068 0x394 0x000 0x6 0x0
+#define MX53_PAD_DISP0_DAT2__USBPHY2_RXACTIVE			0x068 0x394 0x000 0x7 0x0
+#define MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3			0x06c 0x398 0x000 0x0 0x0
+#define MX53_PAD_DISP0_DAT3__GPIO4_24				0x06c 0x398 0x000 0x1 0x0
+#define MX53_PAD_DISP0_DAT3__CSPI_SS0				0x06c 0x398 0x78c 0x2 0x0
+#define MX53_PAD_DISP0_DAT3__USBOH3_USBH2_DATA_3		0x06c 0x398 0x000 0x3 0x0
+#define MX53_PAD_DISP0_DAT3__SDMA_DEBUG_BUS_ERROR		0x06c 0x398 0x000 0x5 0x0
+#define MX53_PAD_DISP0_DAT3__EMI_EMI_DEBUG_8			0x06c 0x398 0x000 0x6 0x0
+#define MX53_PAD_DISP0_DAT3__USBPHY2_RXERROR			0x06c 0x398 0x000 0x7 0x0
+#define MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4			0x070 0x39c 0x000 0x0 0x0
+#define MX53_PAD_DISP0_DAT4__GPIO4_25				0x070 0x39c 0x000 0x1 0x0
+#define MX53_PAD_DISP0_DAT4__CSPI_SS1				0x070 0x39c 0x790 0x2 0x0
+#define MX53_PAD_DISP0_DAT4__USBOH3_USBH2_DATA_4		0x070 0x39c 0x000 0x3 0x0
+#define MX53_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB			0x070 0x39c 0x000 0x5 0x0
+#define MX53_PAD_DISP0_DAT4__EMI_EMI_DEBUG_9			0x070 0x39c 0x000 0x6 0x0
+#define MX53_PAD_DISP0_DAT4__USBPHY2_SIECLOCK			0x070 0x39c 0x000 0x7 0x0
+#define MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5			0x074 0x3a0 0x000 0x0 0x0
+#define MX53_PAD_DISP0_DAT5__GPIO4_26				0x074 0x3a0 0x000 0x1 0x0
+#define MX53_PAD_DISP0_DAT5__CSPI_SS2				0x074 0x3a0 0x794 0x2 0x0
+#define MX53_PAD_DISP0_DAT5__USBOH3_USBH2_DATA_5		0x074 0x3a0 0x000 0x3 0x0
+#define MX53_PAD_DISP0_DAT5__SDMA_DEBUG_MATCHED_DMBUS		0x074 0x3a0 0x000 0x5 0x0
+#define MX53_PAD_DISP0_DAT5__EMI_EMI_DEBUG_10			0x074 0x3a0 0x000 0x6 0x0
+#define MX53_PAD_DISP0_DAT5__USBPHY2_LINESTATE_0		0x074 0x3a0 0x000 0x7 0x0
+#define MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6			0x078 0x3a4 0x000 0x0 0x0
+#define MX53_PAD_DISP0_DAT6__GPIO4_27				0x078 0x3a4 0x000 0x1 0x0
+#define MX53_PAD_DISP0_DAT6__CSPI_SS3				0x078 0x3a4 0x798 0x2 0x0
+#define MX53_PAD_DISP0_DAT6__USBOH3_USBH2_DATA_6		0x078 0x3a4 0x000 0x3 0x0
+#define MX53_PAD_DISP0_DAT6__SDMA_DEBUG_RTBUFFER_WRITE		0x078 0x3a4 0x000 0x5 0x0
+#define MX53_PAD_DISP0_DAT6__EMI_EMI_DEBUG_11			0x078 0x3a4 0x000 0x6 0x0
+#define MX53_PAD_DISP0_DAT6__USBPHY2_LINESTATE_1		0x078 0x3a4 0x000 0x7 0x0
+#define MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7			0x07c 0x3a8 0x000 0x0 0x0
+#define MX53_PAD_DISP0_DAT7__GPIO4_28				0x07c 0x3a8 0x000 0x1 0x0
+#define MX53_PAD_DISP0_DAT7__CSPI_RDY				0x07c 0x3a8 0x000 0x2 0x0
+#define MX53_PAD_DISP0_DAT7__USBOH3_USBH2_DATA_7		0x07c 0x3a8 0x000 0x3 0x0
+#define MX53_PAD_DISP0_DAT7__SDMA_DEBUG_EVENT_CHANNEL_0		0x07c 0x3a8 0x000 0x5 0x0
+#define MX53_PAD_DISP0_DAT7__EMI_EMI_DEBUG_12			0x07c 0x3a8 0x000 0x6 0x0
+#define MX53_PAD_DISP0_DAT7__USBPHY2_VBUSVALID			0x07c 0x3a8 0x000 0x7 0x0
+#define MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8			0x080 0x3ac 0x000 0x0 0x0
+#define MX53_PAD_DISP0_DAT8__GPIO4_29				0x080 0x3ac 0x000 0x1 0x0
+#define MX53_PAD_DISP0_DAT8__PWM1_PWMO				0x080 0x3ac 0x000 0x2 0x0
+#define MX53_PAD_DISP0_DAT8__WDOG1_WDOG_B			0x080 0x3ac 0x000 0x3 0x0
+#define MX53_PAD_DISP0_DAT8__SDMA_DEBUG_EVENT_CHANNEL_1		0x080 0x3ac 0x000 0x5 0x0
+#define MX53_PAD_DISP0_DAT8__EMI_EMI_DEBUG_13			0x080 0x3ac 0x000 0x6 0x0
+#define MX53_PAD_DISP0_DAT8__USBPHY2_AVALID			0x080 0x3ac 0x000 0x7 0x0
+#define MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9			0x084 0x3b0 0x000 0x0 0x0
+#define MX53_PAD_DISP0_DAT9__GPIO4_30				0x084 0x3b0 0x000 0x1 0x0
+#define MX53_PAD_DISP0_DAT9__PWM2_PWMO				0x084 0x3b0 0x000 0x2 0x0
+#define MX53_PAD_DISP0_DAT9__WDOG2_WDOG_B			0x084 0x3b0 0x000 0x3 0x0
+#define MX53_PAD_DISP0_DAT9__SDMA_DEBUG_EVENT_CHANNEL_2		0x084 0x3b0 0x000 0x5 0x0
+#define MX53_PAD_DISP0_DAT9__EMI_EMI_DEBUG_14			0x084 0x3b0 0x000 0x6 0x0
+#define MX53_PAD_DISP0_DAT9__USBPHY2_VSTATUS_0			0x084 0x3b0 0x000 0x7 0x0
+#define MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10			0x088 0x3b4 0x000 0x0 0x0
+#define MX53_PAD_DISP0_DAT10__GPIO4_31				0x088 0x3b4 0x000 0x1 0x0
+#define MX53_PAD_DISP0_DAT10__USBOH3_USBH2_STP			0x088 0x3b4 0x000 0x2 0x0
+#define MX53_PAD_DISP0_DAT10__SDMA_DEBUG_EVENT_CHANNEL_3	0x088 0x3b4 0x000 0x5 0x0
+#define MX53_PAD_DISP0_DAT10__EMI_EMI_DEBUG_15			0x088 0x3b4 0x000 0x6 0x0
+#define MX53_PAD_DISP0_DAT10__USBPHY2_VSTATUS_1			0x088 0x3b4 0x000 0x7 0x0
+#define MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11			0x08c 0x3b8 0x000 0x0 0x0
+#define MX53_PAD_DISP0_DAT11__GPIO5_5				0x08c 0x3b8 0x000 0x1 0x0
+#define MX53_PAD_DISP0_DAT11__USBOH3_USBH2_NXT			0x08c 0x3b8 0x000 0x2 0x0
+#define MX53_PAD_DISP0_DAT11__SDMA_DEBUG_EVENT_CHANNEL_4	0x08c 0x3b8 0x000 0x5 0x0
+#define MX53_PAD_DISP0_DAT11__EMI_EMI_DEBUG_16			0x08c 0x3b8 0x000 0x6 0x0
+#define MX53_PAD_DISP0_DAT11__USBPHY2_VSTATUS_2			0x08c 0x3b8 0x000 0x7 0x0
+#define MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12			0x090 0x3bc 0x000 0x0 0x0
+#define MX53_PAD_DISP0_DAT12__GPIO5_6				0x090 0x3bc 0x000 0x1 0x0
+#define MX53_PAD_DISP0_DAT12__USBOH3_USBH2_CLK			0x090 0x3bc 0x000 0x2 0x0
+#define MX53_PAD_DISP0_DAT12__SDMA_DEBUG_EVENT_CHANNEL_5	0x090 0x3bc 0x000 0x5 0x0
+#define MX53_PAD_DISP0_DAT12__EMI_EMI_DEBUG_17			0x090 0x3bc 0x000 0x6 0x0
+#define MX53_PAD_DISP0_DAT12__USBPHY2_VSTATUS_3			0x090 0x3bc 0x000 0x7 0x0
+#define MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13			0x094 0x3c0 0x000 0x0 0x0
+#define MX53_PAD_DISP0_DAT13__GPIO5_7				0x094 0x3c0 0x000 0x1 0x0
+#define MX53_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS			0x094 0x3c0 0x754 0x3 0x0
+#define MX53_PAD_DISP0_DAT13__SDMA_DEBUG_EVT_CHN_LINES_0	0x094 0x3c0 0x000 0x5 0x0
+#define MX53_PAD_DISP0_DAT13__EMI_EMI_DEBUG_18			0x094 0x3c0 0x000 0x6 0x0
+#define MX53_PAD_DISP0_DAT13__USBPHY2_VSTATUS_4			0x094 0x3c0 0x000 0x7 0x0
+#define MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14			0x098 0x3c4 0x000 0x0 0x0
+#define MX53_PAD_DISP0_DAT14__GPIO5_8				0x098 0x3c4 0x000 0x1 0x0
+#define MX53_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC			0x098 0x3c4 0x750 0x3 0x0
+#define MX53_PAD_DISP0_DAT14__SDMA_DEBUG_EVT_CHN_LINES_1	0x098 0x3c4 0x000 0x5 0x0
+#define MX53_PAD_DISP0_DAT14__EMI_EMI_DEBUG_19			0x098 0x3c4 0x000 0x6 0x0
+#define MX53_PAD_DISP0_DAT14__USBPHY2_VSTATUS_5			0x098 0x3c4 0x000 0x7 0x0
+#define MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15			0x09c 0x3c8 0x000 0x0 0x0
+#define MX53_PAD_DISP0_DAT15__GPIO5_9				0x09c 0x3c8 0x000 0x1 0x0
+#define MX53_PAD_DISP0_DAT15__ECSPI1_SS1			0x09c 0x3c8 0x7ac 0x2 0x1
+#define MX53_PAD_DISP0_DAT15__ECSPI2_SS1			0x09c 0x3c8 0x7c8 0x3 0x0
+#define MX53_PAD_DISP0_DAT15__SDMA_DEBUG_EVT_CHN_LINES_2	0x09c 0x3c8 0x000 0x5 0x0
+#define MX53_PAD_DISP0_DAT15__EMI_EMI_DEBUG_20			0x09c 0x3c8 0x000 0x6 0x0
+#define MX53_PAD_DISP0_DAT15__USBPHY2_VSTATUS_6			0x09c 0x3c8 0x000 0x7 0x0
+#define MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16			0x0a0 0x3cc 0x000 0x0 0x0
+#define MX53_PAD_DISP0_DAT16__GPIO5_10				0x0a0 0x3cc 0x000 0x1 0x0
+#define MX53_PAD_DISP0_DAT16__ECSPI2_MOSI			0x0a0 0x3cc 0x7c0 0x2 0x0
+#define MX53_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC			0x0a0 0x3cc 0x758 0x3 0x1
+#define MX53_PAD_DISP0_DAT16__SDMA_EXT_EVENT_0			0x0a0 0x3cc 0x868 0x4 0x0
+#define MX53_PAD_DISP0_DAT16__SDMA_DEBUG_EVT_CHN_LINES_3	0x0a0 0x3cc 0x000 0x5 0x0
+#define MX53_PAD_DISP0_DAT16__EMI_EMI_DEBUG_21			0x0a0 0x3cc 0x000 0x6 0x0
+#define MX53_PAD_DISP0_DAT16__USBPHY2_VSTATUS_7			0x0a0 0x3cc 0x000 0x7 0x0
+#define MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17			0x0a4 0x3d0 0x000 0x0 0x0
+#define MX53_PAD_DISP0_DAT17__GPIO5_11				0x0a4 0x3d0 0x000 0x1 0x0
+#define MX53_PAD_DISP0_DAT17__ECSPI2_MISO			0x0a4 0x3d0 0x7bc 0x2 0x0
+#define MX53_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD			0x0a4 0x3d0 0x74c 0x3 0x1
+#define MX53_PAD_DISP0_DAT17__SDMA_EXT_EVENT_1			0x0a4 0x3d0 0x86c 0x4 0x0
+#define MX53_PAD_DISP0_DAT17__SDMA_DEBUG_EVT_CHN_LINES_4	0x0a4 0x3d0 0x000 0x5 0x0
+#define MX53_PAD_DISP0_DAT17__EMI_EMI_DEBUG_22			0x0a4 0x3d0 0x000 0x6 0x0
+#define MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18			0x0a8 0x3d4 0x000 0x0 0x0
+#define MX53_PAD_DISP0_DAT18__GPIO5_12				0x0a8 0x3d4 0x000 0x1 0x0
+#define MX53_PAD_DISP0_DAT18__ECSPI2_SS0			0x0a8 0x3d4 0x7c4 0x2 0x0
+#define MX53_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS			0x0a8 0x3d4 0x75c 0x3 0x1
+#define MX53_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS			0x0a8 0x3d4 0x73c 0x4 0x0
+#define MX53_PAD_DISP0_DAT18__SDMA_DEBUG_EVT_CHN_LINES_5	0x0a8 0x3d4 0x000 0x5 0x0
+#define MX53_PAD_DISP0_DAT18__EMI_EMI_DEBUG_23			0x0a8 0x3d4 0x000 0x6 0x0
+#define MX53_PAD_DISP0_DAT18__EMI_WEIM_CS_2			0x0a8 0x3d4 0x000 0x7 0x0
+#define MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19			0x0ac 0x3d8 0x000 0x0 0x0
+#define MX53_PAD_DISP0_DAT19__GPIO5_13				0x0ac 0x3d8 0x000 0x1 0x0
+#define MX53_PAD_DISP0_DAT19__ECSPI2_SCLK			0x0ac 0x3d8 0x7b8 0x2 0x0
+#define MX53_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD			0x0ac 0x3d8 0x748 0x3 0x1
+#define MX53_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC			0x0ac 0x3d8 0x738 0x4 0x0
+#define MX53_PAD_DISP0_DAT19__SDMA_DEBUG_EVT_CHN_LINES_6	0x0ac 0x3d8 0x000 0x5 0x0
+#define MX53_PAD_DISP0_DAT19__EMI_EMI_DEBUG_24			0x0ac 0x3d8 0x000 0x6 0x0
+#define MX53_PAD_DISP0_DAT19__EMI_WEIM_CS_3			0x0ac 0x3d8 0x000 0x7 0x0
+#define MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20			0x0b0 0x3dc 0x000 0x0 0x0
+#define MX53_PAD_DISP0_DAT20__GPIO5_14				0x0b0 0x3dc 0x000 0x1 0x0
+#define MX53_PAD_DISP0_DAT20__ECSPI1_SCLK			0x0b0 0x3dc 0x79c 0x2 0x1
+#define MX53_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC			0x0b0 0x3dc 0x740 0x3 0x0
+#define MX53_PAD_DISP0_DAT20__SDMA_DEBUG_EVT_CHN_LINES_7	0x0b0 0x3dc 0x000 0x5 0x0
+#define MX53_PAD_DISP0_DAT20__EMI_EMI_DEBUG_25			0x0b0 0x3dc 0x000 0x6 0x0
+#define MX53_PAD_DISP0_DAT20__SATA_PHY_TDI			0x0b0 0x3dc 0x000 0x7 0x0
+#define MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21			0x0b4 0x3e0 0x000 0x0 0x0
+#define MX53_PAD_DISP0_DAT21__GPIO5_15				0x0b4 0x3e0 0x000 0x1 0x0
+#define MX53_PAD_DISP0_DAT21__ECSPI1_MOSI			0x0b4 0x3e0 0x7a4 0x2 0x1
+#define MX53_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD			0x0b4 0x3e0 0x734 0x3 0x0
+#define MX53_PAD_DISP0_DAT21__SDMA_DEBUG_BUS_DEVICE_0		0x0b4 0x3e0 0x000 0x5 0x0
+#define MX53_PAD_DISP0_DAT21__EMI_EMI_DEBUG_26			0x0b4 0x3e0 0x000 0x6 0x0
+#define MX53_PAD_DISP0_DAT21__SATA_PHY_TDO			0x0b4 0x3e0 0x000 0x7 0x0
+#define MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22			0x0b8 0x3e4 0x000 0x0 0x0
+#define MX53_PAD_DISP0_DAT22__GPIO5_16				0x0b8 0x3e4 0x000 0x1 0x0
+#define MX53_PAD_DISP0_DAT22__ECSPI1_MISO			0x0b8 0x3e4 0x7a0 0x2 0x1
+#define MX53_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS			0x0b8 0x3e4 0x744 0x3 0x0
+#define MX53_PAD_DISP0_DAT22__SDMA_DEBUG_BUS_DEVICE_1		0x0b8 0x3e4 0x000 0x5 0x0
+#define MX53_PAD_DISP0_DAT22__EMI_EMI_DEBUG_27			0x0b8 0x3e4 0x000 0x6 0x0
+#define MX53_PAD_DISP0_DAT22__SATA_PHY_TCK			0x0b8 0x3e4 0x000 0x7 0x0
+#define MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23			0x0bc 0x3e8 0x000 0x0 0x0
+#define MX53_PAD_DISP0_DAT23__GPIO5_17				0x0bc 0x3e8 0x000 0x1 0x0
+#define MX53_PAD_DISP0_DAT23__ECSPI1_SS0			0x0bc 0x3e8 0x7a8 0x2 0x1
+#define MX53_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD			0x0bc 0x3e8 0x730 0x3 0x0
+#define MX53_PAD_DISP0_DAT23__SDMA_DEBUG_BUS_DEVICE_2		0x0bc 0x3e8 0x000 0x5 0x0
+#define MX53_PAD_DISP0_DAT23__EMI_EMI_DEBUG_28			0x0bc 0x3e8 0x000 0x6 0x0
+#define MX53_PAD_DISP0_DAT23__SATA_PHY_TMS			0x0bc 0x3e8 0x000 0x7 0x0
+#define MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK			0x0c0 0x3ec 0x000 0x0 0x0
+#define MX53_PAD_CSI0_PIXCLK__GPIO5_18				0x0c0 0x3ec 0x000 0x1 0x0
+#define MX53_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0			0x0c0 0x3ec 0x000 0x5 0x0
+#define MX53_PAD_CSI0_PIXCLK__EMI_EMI_DEBUG_29			0x0c0 0x3ec 0x000 0x6 0x0
+#define MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC			0x0c4 0x3f0 0x000 0x0 0x0
+#define MX53_PAD_CSI0_MCLK__GPIO5_19				0x0c4 0x3f0 0x000 0x1 0x0
+#define MX53_PAD_CSI0_MCLK__CCM_CSI0_MCLK			0x0c4 0x3f0 0x000 0x2 0x0
+#define MX53_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1			0x0c4 0x3f0 0x000 0x5 0x0
+#define MX53_PAD_CSI0_MCLK__EMI_EMI_DEBUG_30			0x0c4 0x3f0 0x000 0x6 0x0
+#define MX53_PAD_CSI0_MCLK__TPIU_TRCTL				0x0c4 0x3f0 0x000 0x7 0x0
+#define MX53_PAD_CSI0_DATA_EN__IPU_CSI0_DATA_EN			0x0c8 0x3f4 0x000 0x0 0x0
+#define MX53_PAD_CSI0_DATA_EN__GPIO5_20				0x0c8 0x3f4 0x000 0x1 0x0
+#define MX53_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2			0x0c8 0x3f4 0x000 0x5 0x0
+#define MX53_PAD_CSI0_DATA_EN__EMI_EMI_DEBUG_31			0x0c8 0x3f4 0x000 0x6 0x0
+#define MX53_PAD_CSI0_DATA_EN__TPIU_TRCLK			0x0c8 0x3f4 0x000 0x7 0x0
+#define MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC			0x0cc 0x3f8 0x000 0x0 0x0
+#define MX53_PAD_CSI0_VSYNC__GPIO5_21				0x0cc 0x3f8 0x000 0x1 0x0
+#define MX53_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3			0x0cc 0x3f8 0x000 0x5 0x0
+#define MX53_PAD_CSI0_VSYNC__EMI_EMI_DEBUG_32			0x0cc 0x3f8 0x000 0x6 0x0
+#define MX53_PAD_CSI0_VSYNC__TPIU_TRACE_0			0x0cc 0x3f8 0x000 0x7 0x0
+#define MX53_PAD_CSI0_DAT4__IPU_CSI0_D_4			0x0d0 0x3fc 0x000 0x0 0x0
+#define MX53_PAD_CSI0_DAT4__GPIO5_22				0x0d0 0x3fc 0x000 0x1 0x0
+#define MX53_PAD_CSI0_DAT4__KPP_COL_5				0x0d0 0x3fc 0x840 0x2 0x1
+#define MX53_PAD_CSI0_DAT4__ECSPI1_SCLK				0x0d0 0x3fc 0x79c 0x3 0x2
+#define MX53_PAD_CSI0_DAT4__USBOH3_USBH3_STP			0x0d0 0x3fc 0x000 0x4 0x0
+#define MX53_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC			0x0d0 0x3fc 0x000 0x5 0x0
+#define MX53_PAD_CSI0_DAT4__EMI_EMI_DEBUG_33			0x0d0 0x3fc 0x000 0x6 0x0
+#define MX53_PAD_CSI0_DAT4__TPIU_TRACE_1			0x0d0 0x3fc 0x000 0x7 0x0
+#define MX53_PAD_CSI0_DAT5__IPU_CSI0_D_5			0x0d4 0x400 0x000 0x0 0x0
+#define MX53_PAD_CSI0_DAT5__GPIO5_23				0x0d4 0x400 0x000 0x1 0x0
+#define MX53_PAD_CSI0_DAT5__KPP_ROW_5				0x0d4 0x400 0x84c 0x2 0x0
+#define MX53_PAD_CSI0_DAT5__ECSPI1_MOSI				0x0d4 0x400 0x7a4 0x3 0x2
+#define MX53_PAD_CSI0_DAT5__USBOH3_USBH3_NXT			0x0d4 0x400 0x000 0x4 0x0
+#define MX53_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD			0x0d4 0x400 0x000 0x5 0x0
+#define MX53_PAD_CSI0_DAT5__EMI_EMI_DEBUG_34			0x0d4 0x400 0x000 0x6 0x0
+#define MX53_PAD_CSI0_DAT5__TPIU_TRACE_2			0x0d4 0x400 0x000 0x7 0x0
+#define MX53_PAD_CSI0_DAT6__IPU_CSI0_D_6			0x0d8 0x404 0x000 0x0 0x0
+#define MX53_PAD_CSI0_DAT6__GPIO5_24				0x0d8 0x404 0x000 0x1 0x0
+#define MX53_PAD_CSI0_DAT6__KPP_COL_6				0x0d8 0x404 0x844 0x2 0x0
+#define MX53_PAD_CSI0_DAT6__ECSPI1_MISO				0x0d8 0x404 0x7a0 0x3 0x2
+#define MX53_PAD_CSI0_DAT6__USBOH3_USBH3_CLK			0x0d8 0x404 0x000 0x4 0x0
+#define MX53_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS			0x0d8 0x404 0x000 0x5 0x0
+#define MX53_PAD_CSI0_DAT6__EMI_EMI_DEBUG_35			0x0d8 0x404 0x000 0x6 0x0
+#define MX53_PAD_CSI0_DAT6__TPIU_TRACE_3			0x0d8 0x404 0x000 0x7 0x0
+#define MX53_PAD_CSI0_DAT7__IPU_CSI0_D_7			0x0dc 0x408 0x000 0x0 0x0
+#define MX53_PAD_CSI0_DAT7__GPIO5_25				0x0dc 0x408 0x000 0x1 0x0
+#define MX53_PAD_CSI0_DAT7__KPP_ROW_6				0x0dc 0x408 0x850 0x2 0x0
+#define MX53_PAD_CSI0_DAT7__ECSPI1_SS0				0x0dc 0x408 0x7a8 0x3 0x2
+#define MX53_PAD_CSI0_DAT7__USBOH3_USBH3_DIR			0x0dc 0x408 0x000 0x4 0x0
+#define MX53_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD			0x0dc 0x408 0x000 0x5 0x0
+#define MX53_PAD_CSI0_DAT7__EMI_EMI_DEBUG_36			0x0dc 0x408 0x000 0x6 0x0
+#define MX53_PAD_CSI0_DAT7__TPIU_TRACE_4			0x0dc 0x408 0x000 0x7 0x0
+#define MX53_PAD_CSI0_DAT8__IPU_CSI0_D_8			0x0e0 0x40c 0x000 0x0 0x0
+#define MX53_PAD_CSI0_DAT8__GPIO5_26				0x0e0 0x40c 0x000 0x1 0x0
+#define MX53_PAD_CSI0_DAT8__KPP_COL_7				0x0e0 0x40c 0x848 0x2 0x0
+#define MX53_PAD_CSI0_DAT8__ECSPI2_SCLK				0x0e0 0x40c 0x7b8 0x3 0x1
+#define MX53_PAD_CSI0_DAT8__USBOH3_USBH3_OC			0x0e0 0x40c 0x000 0x4 0x0
+#define MX53_PAD_CSI0_DAT8__I2C1_SDA				0x0e0 0x40c 0x818 0x5 0x0
+#define MX53_PAD_CSI0_DAT8__EMI_EMI_DEBUG_37			0x0e0 0x40c 0x000 0x6 0x0
+#define MX53_PAD_CSI0_DAT8__TPIU_TRACE_5			0x0e0 0x40c 0x000 0x7 0x0
+#define MX53_PAD_CSI0_DAT9__IPU_CSI0_D_9			0x0e4 0x410 0x000 0x0 0x0
+#define MX53_PAD_CSI0_DAT9__GPIO5_27				0x0e4 0x410 0x000 0x1 0x0
+#define MX53_PAD_CSI0_DAT9__KPP_ROW_7				0x0e4 0x410 0x854 0x2 0x0
+#define MX53_PAD_CSI0_DAT9__ECSPI2_MOSI				0x0e4 0x410 0x7c0 0x3 0x1
+#define MX53_PAD_CSI0_DAT9__USBOH3_USBH3_PWR			0x0e4 0x410 0x000 0x4 0x0
+#define MX53_PAD_CSI0_DAT9__I2C1_SCL				0x0e4 0x410 0x814 0x5 0x0
+#define MX53_PAD_CSI0_DAT9__EMI_EMI_DEBUG_38			0x0e4 0x410 0x000 0x6 0x0
+#define MX53_PAD_CSI0_DAT9__TPIU_TRACE_6			0x0e4 0x410 0x000 0x7 0x0
+#define MX53_PAD_CSI0_DAT10__IPU_CSI0_D_10			0x0e8 0x414 0x000 0x0 0x0
+#define MX53_PAD_CSI0_DAT10__GPIO5_28				0x0e8 0x414 0x000 0x1 0x0
+#define MX53_PAD_CSI0_DAT10__UART1_TXD_MUX			0x0e8 0x414 0x000 0x2 0x0
+#define MX53_PAD_CSI0_DAT10__ECSPI2_MISO			0x0e8 0x414 0x7bc 0x3 0x1
+#define MX53_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC			0x0e8 0x414 0x000 0x4 0x0
+#define MX53_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4			0x0e8 0x414 0x000 0x5 0x0
+#define MX53_PAD_CSI0_DAT10__EMI_EMI_DEBUG_39			0x0e8 0x414 0x000 0x6 0x0
+#define MX53_PAD_CSI0_DAT10__TPIU_TRACE_7			0x0e8 0x414 0x000 0x7 0x0
+#define MX53_PAD_CSI0_DAT11__IPU_CSI0_D_11			0x0ec 0x418 0x000 0x0 0x0
+#define MX53_PAD_CSI0_DAT11__GPIO5_29				0x0ec 0x418 0x000 0x1 0x0
+#define MX53_PAD_CSI0_DAT11__UART1_RXD_MUX			0x0ec 0x418 0x878 0x2 0x1
+#define MX53_PAD_CSI0_DAT11__ECSPI2_SS0				0x0ec 0x418 0x7c4 0x3 0x1
+#define MX53_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS			0x0ec 0x418 0x000 0x4 0x0
+#define MX53_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5			0x0ec 0x418 0x000 0x5 0x0
+#define MX53_PAD_CSI0_DAT11__EMI_EMI_DEBUG_40			0x0ec 0x418 0x000 0x6 0x0
+#define MX53_PAD_CSI0_DAT11__TPIU_TRACE_8			0x0ec 0x418 0x000 0x7 0x0
+#define MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12			0x0f0 0x41c 0x000 0x0 0x0
+#define MX53_PAD_CSI0_DAT12__GPIO5_30				0x0f0 0x41c 0x000 0x1 0x0
+#define MX53_PAD_CSI0_DAT12__UART4_TXD_MUX			0x0f0 0x41c 0x000 0x2 0x0
+#define MX53_PAD_CSI0_DAT12__USBOH3_USBH3_DATA_0		0x0f0 0x41c 0x000 0x4 0x0
+#define MX53_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6			0x0f0 0x41c 0x000 0x5 0x0
+#define MX53_PAD_CSI0_DAT12__EMI_EMI_DEBUG_41			0x0f0 0x41c 0x000 0x6 0x0
+#define MX53_PAD_CSI0_DAT12__TPIU_TRACE_9			0x0f0 0x41c 0x000 0x7 0x0
+#define MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13			0x0f4 0x420 0x000 0x0 0x0
+#define MX53_PAD_CSI0_DAT13__GPIO5_31				0x0f4 0x420 0x000 0x1 0x0
+#define MX53_PAD_CSI0_DAT13__UART4_RXD_MUX			0x0f4 0x420 0x890 0x2 0x3
+#define MX53_PAD_CSI0_DAT13__USBOH3_USBH3_DATA_1		0x0f4 0x420 0x000 0x4 0x0
+#define MX53_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7			0x0f4 0x420 0x000 0x5 0x0
+#define MX53_PAD_CSI0_DAT13__EMI_EMI_DEBUG_42			0x0f4 0x420 0x000 0x6 0x0
+#define MX53_PAD_CSI0_DAT13__TPIU_TRACE_10			0x0f4 0x420 0x000 0x7 0x0
+#define MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14			0x0f8 0x424 0x000 0x0 0x0
+#define MX53_PAD_CSI0_DAT14__GPIO6_0				0x0f8 0x424 0x000 0x1 0x0
+#define MX53_PAD_CSI0_DAT14__UART5_TXD_MUX			0x0f8 0x424 0x000 0x2 0x0
+#define MX53_PAD_CSI0_DAT14__USBOH3_USBH3_DATA_2		0x0f8 0x424 0x000 0x4 0x0
+#define MX53_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8			0x0f8 0x424 0x000 0x5 0x0
+#define MX53_PAD_CSI0_DAT14__EMI_EMI_DEBUG_43			0x0f8 0x424 0x000 0x6 0x0
+#define MX53_PAD_CSI0_DAT14__TPIU_TRACE_11			0x0f8 0x424 0x000 0x7 0x0
+#define MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15			0x0fc 0x428 0x000 0x0 0x0
+#define MX53_PAD_CSI0_DAT15__GPIO6_1				0x0fc 0x428 0x000 0x1 0x0
+#define MX53_PAD_CSI0_DAT15__UART5_RXD_MUX			0x0fc 0x428 0x898 0x2 0x3
+#define MX53_PAD_CSI0_DAT15__USBOH3_USBH3_DATA_3		0x0fc 0x428 0x000 0x4 0x0
+#define MX53_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9			0x0fc 0x428 0x000 0x5 0x0
+#define MX53_PAD_CSI0_DAT15__EMI_EMI_DEBUG_44			0x0fc 0x428 0x000 0x6 0x0
+#define MX53_PAD_CSI0_DAT15__TPIU_TRACE_12			0x0fc 0x428 0x000 0x7 0x0
+#define MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16			0x100 0x42c 0x000 0x0 0x0
+#define MX53_PAD_CSI0_DAT16__GPIO6_2				0x100 0x42c 0x000 0x1 0x0
+#define MX53_PAD_CSI0_DAT16__UART4_RTS				0x100 0x42c 0x88c 0x2 0x0
+#define MX53_PAD_CSI0_DAT16__USBOH3_USBH3_DATA_4		0x100 0x42c 0x000 0x4 0x0
+#define MX53_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10			0x100 0x42c 0x000 0x5 0x0
+#define MX53_PAD_CSI0_DAT16__EMI_EMI_DEBUG_45			0x100 0x42c 0x000 0x6 0x0
+#define MX53_PAD_CSI0_DAT16__TPIU_TRACE_13			0x100 0x42c 0x000 0x7 0x0
+#define MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17			0x104 0x430 0x000 0x0 0x0
+#define MX53_PAD_CSI0_DAT17__GPIO6_3				0x104 0x430 0x000 0x1 0x0
+#define MX53_PAD_CSI0_DAT17__UART4_CTS				0x104 0x430 0x000 0x2 0x0
+#define MX53_PAD_CSI0_DAT17__USBOH3_USBH3_DATA_5		0x104 0x430 0x000 0x4 0x0
+#define MX53_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11			0x104 0x430 0x000 0x5 0x0
+#define MX53_PAD_CSI0_DAT17__EMI_EMI_DEBUG_46			0x104 0x430 0x000 0x6 0x0
+#define MX53_PAD_CSI0_DAT17__TPIU_TRACE_14			0x104 0x430 0x000 0x7 0x0
+#define MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18			0x108 0x434 0x000 0x0 0x0
+#define MX53_PAD_CSI0_DAT18__GPIO6_4				0x108 0x434 0x000 0x1 0x0
+#define MX53_PAD_CSI0_DAT18__UART5_RTS				0x108 0x434 0x894 0x2 0x2
+#define MX53_PAD_CSI0_DAT18__USBOH3_USBH3_DATA_6		0x108 0x434 0x000 0x4 0x0
+#define MX53_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12			0x108 0x434 0x000 0x5 0x0
+#define MX53_PAD_CSI0_DAT18__EMI_EMI_DEBUG_47			0x108 0x434 0x000 0x6 0x0
+#define MX53_PAD_CSI0_DAT18__TPIU_TRACE_15			0x108 0x434 0x000 0x7 0x0
+#define MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19			0x10c 0x438 0x000 0x0 0x0
+#define MX53_PAD_CSI0_DAT19__GPIO6_5				0x10c 0x438 0x000 0x1 0x0
+#define MX53_PAD_CSI0_DAT19__UART5_CTS				0x10c 0x438 0x000 0x2 0x0
+#define MX53_PAD_CSI0_DAT19__USBOH3_USBH3_DATA_7		0x10c 0x438 0x000 0x4 0x0
+#define MX53_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13			0x10c 0x438 0x000 0x5 0x0
+#define MX53_PAD_CSI0_DAT19__EMI_EMI_DEBUG_48			0x10c 0x438 0x000 0x6 0x0
+#define MX53_PAD_CSI0_DAT19__USBPHY2_BISTOK			0x10c 0x438 0x000 0x7 0x0
+#define MX53_PAD_EIM_A25__EMI_WEIM_A_25				0x110 0x458 0x000 0x0 0x0
+#define MX53_PAD_EIM_A25__GPIO5_2				0x110 0x458 0x000 0x1 0x0
+#define MX53_PAD_EIM_A25__ECSPI2_RDY				0x110 0x458 0x000 0x2 0x0
+#define MX53_PAD_EIM_A25__IPU_DI1_PIN12				0x110 0x458 0x000 0x3 0x0
+#define MX53_PAD_EIM_A25__CSPI_SS1				0x110 0x458 0x790 0x4 0x1
+#define MX53_PAD_EIM_A25__IPU_DI0_D1_CS				0x110 0x458 0x000 0x6 0x0
+#define MX53_PAD_EIM_A25__USBPHY1_BISTOK			0x110 0x458 0x000 0x7 0x0
+#define MX53_PAD_EIM_EB2__EMI_WEIM_EB_2				0x114 0x45c 0x000 0x0 0x0
+#define MX53_PAD_EIM_EB2__GPIO2_30				0x114 0x45c 0x000 0x1 0x0
+#define MX53_PAD_EIM_EB2__CCM_DI1_EXT_CLK			0x114 0x45c 0x76c 0x2 0x0
+#define MX53_PAD_EIM_EB2__IPU_SER_DISP1_CS			0x114 0x45c 0x000 0x3 0x0
+#define MX53_PAD_EIM_EB2__ECSPI1_SS0				0x114 0x45c 0x7a8 0x4 0x3
+#define MX53_PAD_EIM_EB2__I2C2_SCL				0x114 0x45c 0x81c 0x5 0x1
+#define MX53_PAD_EIM_D16__EMI_WEIM_D_16				0x118 0x460 0x000 0x0 0x0
+#define MX53_PAD_EIM_D16__GPIO3_16				0x118 0x460 0x000 0x1 0x0
+#define MX53_PAD_EIM_D16__IPU_DI0_PIN5				0x118 0x460 0x000 0x2 0x0
+#define MX53_PAD_EIM_D16__IPU_DISPB1_SER_CLK			0x118 0x460 0x000 0x3 0x0
+#define MX53_PAD_EIM_D16__ECSPI1_SCLK				0x118 0x460 0x79c 0x4 0x3
+#define MX53_PAD_EIM_D16__I2C2_SDA				0x118 0x460 0x820 0x5 0x1
+#define MX53_PAD_EIM_D17__EMI_WEIM_D_17				0x11c 0x464 0x000 0x0 0x0
+#define MX53_PAD_EIM_D17__GPIO3_17				0x11c 0x464 0x000 0x1 0x0
+#define MX53_PAD_EIM_D17__IPU_DI0_PIN6				0x11c 0x464 0x000 0x2 0x0
+#define MX53_PAD_EIM_D17__IPU_DISPB1_SER_DIN			0x11c 0x464 0x830 0x3 0x0
+#define MX53_PAD_EIM_D17__ECSPI1_MISO				0x11c 0x464 0x7a0 0x4 0x3
+#define MX53_PAD_EIM_D17__I2C3_SCL				0x11c 0x464 0x824 0x5 0x0
+#define MX53_PAD_EIM_D18__EMI_WEIM_D_18				0x120 0x468 0x000 0x0 0x0
+#define MX53_PAD_EIM_D18__GPIO3_18				0x120 0x468 0x000 0x1 0x0
+#define MX53_PAD_EIM_D18__IPU_DI0_PIN7				0x120 0x468 0x000 0x2 0x0
+#define MX53_PAD_EIM_D18__IPU_DISPB1_SER_DIO			0x120 0x468 0x830 0x3 0x1
+#define MX53_PAD_EIM_D18__ECSPI1_MOSI				0x120 0x468 0x7a4 0x4 0x3
+#define MX53_PAD_EIM_D18__I2C3_SDA				0x120 0x468 0x828 0x5 0x0
+#define MX53_PAD_EIM_D18__IPU_DI1_D0_CS				0x120 0x468 0x000 0x6 0x0
+#define MX53_PAD_EIM_D19__EMI_WEIM_D_19				0x124 0x46c 0x000 0x0 0x0
+#define MX53_PAD_EIM_D19__GPIO3_19				0x124 0x46c 0x000 0x1 0x0
+#define MX53_PAD_EIM_D19__IPU_DI0_PIN8				0x124 0x46c 0x000 0x2 0x0
+#define MX53_PAD_EIM_D19__IPU_DISPB1_SER_RS			0x124 0x46c 0x000 0x3 0x0
+#define MX53_PAD_EIM_D19__ECSPI1_SS1				0x124 0x46c 0x7ac 0x4 0x2
+#define MX53_PAD_EIM_D19__EPIT1_EPITO				0x124 0x46c 0x000 0x5 0x0
+#define MX53_PAD_EIM_D19__UART1_CTS				0x124 0x46c 0x000 0x6 0x0
+#define MX53_PAD_EIM_D19__USBOH3_USBH2_OC			0x124 0x46c 0x8a4 0x7 0x0
+#define MX53_PAD_EIM_D20__EMI_WEIM_D_20				0x128 0x470 0x000 0x0 0x0
+#define MX53_PAD_EIM_D20__GPIO3_20				0x128 0x470 0x000 0x1 0x0
+#define MX53_PAD_EIM_D20__IPU_DI0_PIN16				0x128 0x470 0x000 0x2 0x0
+#define MX53_PAD_EIM_D20__IPU_SER_DISP0_CS			0x128 0x470 0x000 0x3 0x0
+#define MX53_PAD_EIM_D20__CSPI_SS0				0x128 0x470 0x78c 0x4 0x1
+#define MX53_PAD_EIM_D20__EPIT2_EPITO				0x128 0x470 0x000 0x5 0x0
+#define MX53_PAD_EIM_D20__UART1_RTS				0x128 0x470 0x874 0x6 0x1
+#define MX53_PAD_EIM_D20__USBOH3_USBH2_PWR			0x128 0x470 0x000 0x7 0x0
+#define MX53_PAD_EIM_D21__EMI_WEIM_D_21				0x12c 0x474 0x000 0x0 0x0
+#define MX53_PAD_EIM_D21__GPIO3_21				0x12c 0x474 0x000 0x1 0x0
+#define MX53_PAD_EIM_D21__IPU_DI0_PIN17				0x12c 0x474 0x000 0x2 0x0
+#define MX53_PAD_EIM_D21__IPU_DISPB0_SER_CLK			0x12c 0x474 0x000 0x3 0x0
+#define MX53_PAD_EIM_D21__CSPI_SCLK				0x12c 0x474 0x780 0x4 0x1
+#define MX53_PAD_EIM_D21__I2C1_SCL				0x12c 0x474 0x814 0x5 0x1
+#define MX53_PAD_EIM_D21__USBOH3_USBOTG_OC			0x12c 0x474 0x89c 0x6 0x1
+#define MX53_PAD_EIM_D22__EMI_WEIM_D_22				0x130 0x478 0x000 0x0 0x0
+#define MX53_PAD_EIM_D22__GPIO3_22				0x130 0x478 0x000 0x1 0x0
+#define MX53_PAD_EIM_D22__IPU_DI0_PIN1				0x130 0x478 0x000 0x2 0x0
+#define MX53_PAD_EIM_D22__IPU_DISPB0_SER_DIN			0x130 0x478 0x82c 0x3 0x0
+#define MX53_PAD_EIM_D22__CSPI_MISO				0x130 0x478 0x784 0x4 0x1
+#define MX53_PAD_EIM_D22__USBOH3_USBOTG_PWR			0x130 0x478 0x000 0x6 0x0
+#define MX53_PAD_EIM_D23__EMI_WEIM_D_23				0x134 0x47c 0x000 0x0 0x0
+#define MX53_PAD_EIM_D23__GPIO3_23				0x134 0x47c 0x000 0x1 0x0
+#define MX53_PAD_EIM_D23__UART3_CTS				0x134 0x47c 0x000 0x2 0x0
+#define MX53_PAD_EIM_D23__UART1_DCD				0x134 0x47c 0x000 0x3 0x0
+#define MX53_PAD_EIM_D23__IPU_DI0_D0_CS				0x134 0x47c 0x000 0x4 0x0
+#define MX53_PAD_EIM_D23__IPU_DI1_PIN2				0x134 0x47c 0x000 0x5 0x0
+#define MX53_PAD_EIM_D23__IPU_CSI1_DATA_EN			0x134 0x47c 0x834 0x6 0x0
+#define MX53_PAD_EIM_D23__IPU_DI1_PIN14				0x134 0x47c 0x000 0x7 0x0
+#define MX53_PAD_EIM_EB3__EMI_WEIM_EB_3				0x138 0x480 0x000 0x0 0x0
+#define MX53_PAD_EIM_EB3__GPIO2_31				0x138 0x480 0x000 0x1 0x0
+#define MX53_PAD_EIM_EB3__UART3_RTS				0x138 0x480 0x884 0x2 0x1
+#define MX53_PAD_EIM_EB3__UART1_RI				0x138 0x480 0x000 0x3 0x0
+#define MX53_PAD_EIM_EB3__IPU_DI1_PIN3				0x138 0x480 0x000 0x5 0x0
+#define MX53_PAD_EIM_EB3__IPU_CSI1_HSYNC			0x138 0x480 0x838 0x6 0x0
+#define MX53_PAD_EIM_EB3__IPU_DI1_PIN16				0x138 0x480 0x000 0x7 0x0
+#define MX53_PAD_EIM_D24__EMI_WEIM_D_24				0x13c 0x484 0x000 0x0 0x0
+#define MX53_PAD_EIM_D24__GPIO3_24				0x13c 0x484 0x000 0x1 0x0
+#define MX53_PAD_EIM_D24__UART3_TXD_MUX				0x13c 0x484 0x000 0x2 0x0
+#define MX53_PAD_EIM_D24__ECSPI1_SS2				0x13c 0x484 0x7b0 0x3 0x1
+#define MX53_PAD_EIM_D24__CSPI_SS2				0x13c 0x484 0x794 0x4 0x1
+#define MX53_PAD_EIM_D24__AUDMUX_AUD5_RXFS			0x13c 0x484 0x754 0x5 0x1
+#define MX53_PAD_EIM_D24__ECSPI2_SS2				0x13c 0x484 0x000 0x6 0x0
+#define MX53_PAD_EIM_D24__UART1_DTR				0x13c 0x484 0x000 0x7 0x0
+#define MX53_PAD_EIM_D25__EMI_WEIM_D_25				0x140 0x488 0x000 0x0 0x0
+#define MX53_PAD_EIM_D25__GPIO3_25				0x140 0x488 0x000 0x1 0x0
+#define MX53_PAD_EIM_D25__UART3_RXD_MUX				0x140 0x488 0x888 0x2 0x1
+#define MX53_PAD_EIM_D25__ECSPI1_SS3				0x140 0x488 0x7b4 0x3 0x1
+#define MX53_PAD_EIM_D25__CSPI_SS3				0x140 0x488 0x798 0x4 0x1
+#define MX53_PAD_EIM_D25__AUDMUX_AUD5_RXC			0x140 0x488 0x750 0x5 0x1
+#define MX53_PAD_EIM_D25__ECSPI2_SS3				0x140 0x488 0x000 0x6 0x0
+#define MX53_PAD_EIM_D25__UART1_DSR				0x140 0x488 0x000 0x7 0x0
+#define MX53_PAD_EIM_D26__EMI_WEIM_D_26				0x144 0x48c 0x000 0x0 0x0
+#define MX53_PAD_EIM_D26__GPIO3_26				0x144 0x48c 0x000 0x1 0x0
+#define MX53_PAD_EIM_D26__UART2_RXD_MUX				0x144 0x48c 0x880 0x2 0x0
+#define MX53_PAD_EIM_D26__UART2_TXD_MUX				0x144 0x48c 0x000 0x2 0x0
+#define MX53_PAD_EIM_D26__FIRI_RXD				0x144 0x48c 0x80c 0x3 0x0
+#define MX53_PAD_EIM_D26__IPU_CSI0_D_1				0x144 0x48c 0x000 0x4 0x0
+#define MX53_PAD_EIM_D26__IPU_DI1_PIN11				0x144 0x48c 0x000 0x5 0x0
+#define MX53_PAD_EIM_D26__IPU_SISG_2				0x144 0x48c 0x000 0x6 0x0
+#define MX53_PAD_EIM_D26__IPU_DISP1_DAT_22			0x144 0x48c 0x000 0x7 0x0
+#define MX53_PAD_EIM_D27__EMI_WEIM_D_27				0x148 0x490 0x000 0x0 0x0
+#define MX53_PAD_EIM_D27__GPIO3_27				0x148 0x490 0x000 0x1 0x0
+#define MX53_PAD_EIM_D27__UART2_RXD_MUX				0x148 0x490 0x880 0x2 0x1
+#define MX53_PAD_EIM_D27__UART2_TXD_MUX				0x148 0x490 0x000 0x2 0x0
+#define MX53_PAD_EIM_D27__FIRI_TXD				0x148 0x490 0x000 0x3 0x0
+#define MX53_PAD_EIM_D27__IPU_CSI0_D_0				0x148 0x490 0x000 0x4 0x0
+#define MX53_PAD_EIM_D27__IPU_DI1_PIN13				0x148 0x490 0x000 0x5 0x0
+#define MX53_PAD_EIM_D27__IPU_SISG_3				0x148 0x490 0x000 0x6 0x0
+#define MX53_PAD_EIM_D27__IPU_DISP1_DAT_23			0x148 0x490 0x000 0x7 0x0
+#define MX53_PAD_EIM_D28__EMI_WEIM_D_28				0x14c 0x494 0x000 0x0 0x0
+#define MX53_PAD_EIM_D28__GPIO3_28				0x14c 0x494 0x000 0x1 0x0
+#define MX53_PAD_EIM_D28__UART2_CTS				0x14c 0x494 0x000 0x2 0x0
+#define MX53_PAD_EIM_D28__UART2_RTS				0x14c 0x494 0x87c 0x2 0x0
+#define MX53_PAD_EIM_D28__IPU_DISPB0_SER_DIO			0x14c 0x494 0x82c 0x3 0x1
+#define MX53_PAD_EIM_D28__CSPI_MOSI				0x14c 0x494 0x788 0x4 0x1
+#define MX53_PAD_EIM_D28__I2C1_SDA				0x14c 0x494 0x818 0x5 0x1
+#define MX53_PAD_EIM_D28__IPU_EXT_TRIG				0x14c 0x494 0x000 0x6 0x0
+#define MX53_PAD_EIM_D28__IPU_DI0_PIN13				0x14c 0x494 0x000 0x7 0x0
+#define MX53_PAD_EIM_D29__EMI_WEIM_D_29				0x150 0x498 0x000 0x0 0x0
+#define MX53_PAD_EIM_D29__GPIO3_29				0x150 0x498 0x000 0x1 0x0
+#define MX53_PAD_EIM_D29__UART2_CTS				0x150 0x498 0x000 0x2 0x0
+#define MX53_PAD_EIM_D29__UART2_RTS				0x150 0x498 0x87c 0x2 0x1
+#define MX53_PAD_EIM_D29__IPU_DISPB0_SER_RS			0x150 0x498 0x000 0x3 0x0
+#define MX53_PAD_EIM_D29__CSPI_SS0				0x150 0x498 0x78c 0x4 0x2
+#define MX53_PAD_EIM_D29__IPU_DI1_PIN15				0x150 0x498 0x000 0x5 0x0
+#define MX53_PAD_EIM_D29__IPU_CSI1_VSYNC			0x150 0x498 0x83c 0x6 0x0
+#define MX53_PAD_EIM_D29__IPU_DI0_PIN14				0x150 0x498 0x000 0x7 0x0
+#define MX53_PAD_EIM_D30__EMI_WEIM_D_30				0x154 0x49c 0x000 0x0 0x0
+#define MX53_PAD_EIM_D30__GPIO3_30				0x154 0x49c 0x000 0x1 0x0
+#define MX53_PAD_EIM_D30__UART3_CTS				0x154 0x49c 0x000 0x2 0x0
+#define MX53_PAD_EIM_D30__IPU_CSI0_D_3				0x154 0x49c 0x000 0x3 0x0
+#define MX53_PAD_EIM_D30__IPU_DI0_PIN11				0x154 0x49c 0x000 0x4 0x0
+#define MX53_PAD_EIM_D30__IPU_DISP1_DAT_21			0x154 0x49c 0x000 0x5 0x0
+#define MX53_PAD_EIM_D30__USBOH3_USBH1_OC			0x154 0x49c 0x8a0 0x6 0x0
+#define MX53_PAD_EIM_D30__USBOH3_USBH2_OC			0x154 0x49c 0x8a4 0x7 0x1
+#define MX53_PAD_EIM_D31__EMI_WEIM_D_31				0x158 0x4a0 0x000 0x0 0x0
+#define MX53_PAD_EIM_D31__GPIO3_31				0x158 0x4a0 0x000 0x1 0x0
+#define MX53_PAD_EIM_D31__UART3_RTS				0x158 0x4a0 0x884 0x2 0x3
+#define MX53_PAD_EIM_D31__IPU_CSI0_D_2				0x158 0x4a0 0x000 0x3 0x0
+#define MX53_PAD_EIM_D31__IPU_DI0_PIN12				0x158 0x4a0 0x000 0x4 0x0
+#define MX53_PAD_EIM_D31__IPU_DISP1_DAT_20			0x158 0x4a0 0x000 0x5 0x0
+#define MX53_PAD_EIM_D31__USBOH3_USBH1_PWR			0x158 0x4a0 0x000 0x6 0x0
+#define MX53_PAD_EIM_D31__USBOH3_USBH2_PWR			0x158 0x4a0 0x000 0x7 0x0
+#define MX53_PAD_EIM_A24__EMI_WEIM_A_24				0x15c 0x4a8 0x000 0x0 0x0
+#define MX53_PAD_EIM_A24__GPIO5_4				0x15c 0x4a8 0x000 0x1 0x0
+#define MX53_PAD_EIM_A24__IPU_DISP1_DAT_19			0x15c 0x4a8 0x000 0x2 0x0
+#define MX53_PAD_EIM_A24__IPU_CSI1_D_19				0x15c 0x4a8 0x000 0x3 0x0
+#define MX53_PAD_EIM_A24__IPU_SISG_2				0x15c 0x4a8 0x000 0x6 0x0
+#define MX53_PAD_EIM_A24__USBPHY2_BVALID			0x15c 0x4a8 0x000 0x7 0x0
+#define MX53_PAD_EIM_A23__EMI_WEIM_A_23				0x160 0x4ac 0x000 0x0 0x0
+#define MX53_PAD_EIM_A23__GPIO6_6				0x160 0x4ac 0x000 0x1 0x0
+#define MX53_PAD_EIM_A23__IPU_DISP1_DAT_18			0x160 0x4ac 0x000 0x2 0x0
+#define MX53_PAD_EIM_A23__IPU_CSI1_D_18				0x160 0x4ac 0x000 0x3 0x0
+#define MX53_PAD_EIM_A23__IPU_SISG_3				0x160 0x4ac 0x000 0x6 0x0
+#define MX53_PAD_EIM_A23__USBPHY2_ENDSESSION			0x160 0x4ac 0x000 0x7 0x0
+#define MX53_PAD_EIM_A22__EMI_WEIM_A_22				0x164 0x4b0 0x000 0x0 0x0
+#define MX53_PAD_EIM_A22__GPIO2_16				0x164 0x4b0 0x000 0x1 0x0
+#define MX53_PAD_EIM_A22__IPU_DISP1_DAT_17			0x164 0x4b0 0x000 0x2 0x0
+#define MX53_PAD_EIM_A22__IPU_CSI1_D_17				0x164 0x4b0 0x000 0x3 0x0
+#define MX53_PAD_EIM_A22__SRC_BT_CFG1_7				0x164 0x4b0 0x000 0x7 0x0
+#define MX53_PAD_EIM_A21__EMI_WEIM_A_21				0x168 0x4b4 0x000 0x0 0x0
+#define MX53_PAD_EIM_A21__GPIO2_17				0x168 0x4b4 0x000 0x1 0x0
+#define MX53_PAD_EIM_A21__IPU_DISP1_DAT_16			0x168 0x4b4 0x000 0x2 0x0
+#define MX53_PAD_EIM_A21__IPU_CSI1_D_16				0x168 0x4b4 0x000 0x3 0x0
+#define MX53_PAD_EIM_A21__SRC_BT_CFG1_6				0x168 0x4b4 0x000 0x7 0x0
+#define MX53_PAD_EIM_A20__EMI_WEIM_A_20				0x16c 0x4b8 0x000 0x0 0x0
+#define MX53_PAD_EIM_A20__GPIO2_18				0x16c 0x4b8 0x000 0x1 0x0
+#define MX53_PAD_EIM_A20__IPU_DISP1_DAT_15			0x16c 0x4b8 0x000 0x2 0x0
+#define MX53_PAD_EIM_A20__IPU_CSI1_D_15				0x16c 0x4b8 0x000 0x3 0x0
+#define MX53_PAD_EIM_A20__SRC_BT_CFG1_5				0x16c 0x4b8 0x000 0x7 0x0
+#define MX53_PAD_EIM_A19__EMI_WEIM_A_19				0x170 0x4bc 0x000 0x0 0x0
+#define MX53_PAD_EIM_A19__GPIO2_19				0x170 0x4bc 0x000 0x1 0x0
+#define MX53_PAD_EIM_A19__IPU_DISP1_DAT_14			0x170 0x4bc 0x000 0x2 0x0
+#define MX53_PAD_EIM_A19__IPU_CSI1_D_14				0x170 0x4bc 0x000 0x3 0x0
+#define MX53_PAD_EIM_A19__SRC_BT_CFG1_4				0x170 0x4bc 0x000 0x7 0x0
+#define MX53_PAD_EIM_A18__EMI_WEIM_A_18				0x174 0x4c0 0x000 0x0 0x0
+#define MX53_PAD_EIM_A18__GPIO2_20				0x174 0x4c0 0x000 0x1 0x0
+#define MX53_PAD_EIM_A18__IPU_DISP1_DAT_13			0x174 0x4c0 0x000 0x2 0x0
+#define MX53_PAD_EIM_A18__IPU_CSI1_D_13				0x174 0x4c0 0x000 0x3 0x0
+#define MX53_PAD_EIM_A18__SRC_BT_CFG1_3				0x174 0x4c0 0x000 0x7 0x0
+#define MX53_PAD_EIM_A17__EMI_WEIM_A_17				0x178 0x4c4 0x000 0x0 0x0
+#define MX53_PAD_EIM_A17__GPIO2_21				0x178 0x4c4 0x000 0x1 0x0
+#define MX53_PAD_EIM_A17__IPU_DISP1_DAT_12			0x178 0x4c4 0x000 0x2 0x0
+#define MX53_PAD_EIM_A17__IPU_CSI1_D_12				0x178 0x4c4 0x000 0x3 0x0
+#define MX53_PAD_EIM_A17__SRC_BT_CFG1_2				0x178 0x4c4 0x000 0x7 0x0
+#define MX53_PAD_EIM_A16__EMI_WEIM_A_16				0x17c 0x4c8 0x000 0x0 0x0
+#define MX53_PAD_EIM_A16__GPIO2_22				0x17c 0x4c8 0x000 0x1 0x0
+#define MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK			0x17c 0x4c8 0x000 0x2 0x0
+#define MX53_PAD_EIM_A16__IPU_CSI1_PIXCLK			0x17c 0x4c8 0x000 0x3 0x0
+#define MX53_PAD_EIM_A16__SRC_BT_CFG1_1				0x17c 0x4c8 0x000 0x7 0x0
+#define MX53_PAD_EIM_CS0__EMI_WEIM_CS_0				0x180 0x4cc 0x000 0x0 0x0
+#define MX53_PAD_EIM_CS0__GPIO2_23				0x180 0x4cc 0x000 0x1 0x0
+#define MX53_PAD_EIM_CS0__ECSPI2_SCLK				0x180 0x4cc 0x7b8 0x2 0x2
+#define MX53_PAD_EIM_CS0__IPU_DI1_PIN5				0x180 0x4cc 0x000 0x3 0x0
+#define MX53_PAD_EIM_CS1__EMI_WEIM_CS_1				0x184 0x4d0 0x000 0x0 0x0
+#define MX53_PAD_EIM_CS1__GPIO2_24				0x184 0x4d0 0x000 0x1 0x0
+#define MX53_PAD_EIM_CS1__ECSPI2_MOSI				0x184 0x4d0 0x7c0 0x2 0x2
+#define MX53_PAD_EIM_CS1__IPU_DI1_PIN6				0x184 0x4d0 0x000 0x3 0x0
+#define MX53_PAD_EIM_OE__EMI_WEIM_OE				0x188 0x4d4 0x000 0x0 0x0
+#define MX53_PAD_EIM_OE__GPIO2_25				0x188 0x4d4 0x000 0x1 0x0
+#define MX53_PAD_EIM_OE__ECSPI2_MISO				0x188 0x4d4 0x7bc 0x2 0x2
+#define MX53_PAD_EIM_OE__IPU_DI1_PIN7				0x188 0x4d4 0x000 0x3 0x0
+#define MX53_PAD_EIM_OE__USBPHY2_IDDIG				0x188 0x4d4 0x000 0x7 0x0
+#define MX53_PAD_EIM_RW__EMI_WEIM_RW				0x18c 0x4d8 0x000 0x0 0x0
+#define MX53_PAD_EIM_RW__GPIO2_26				0x18c 0x4d8 0x000 0x1 0x0
+#define MX53_PAD_EIM_RW__ECSPI2_SS0				0x18c 0x4d8 0x7c4 0x2 0x2
+#define MX53_PAD_EIM_RW__IPU_DI1_PIN8				0x18c 0x4d8 0x000 0x3 0x0
+#define MX53_PAD_EIM_RW__USBPHY2_HOSTDISCONNECT			0x18c 0x4d8 0x000 0x7 0x0
+#define MX53_PAD_EIM_LBA__EMI_WEIM_LBA				0x190 0x4dc 0x000 0x0 0x0
+#define MX53_PAD_EIM_LBA__GPIO2_27				0x190 0x4dc 0x000 0x1 0x0
+#define MX53_PAD_EIM_LBA__ECSPI2_SS1				0x190 0x4dc 0x7c8 0x2 0x1
+#define MX53_PAD_EIM_LBA__IPU_DI1_PIN17				0x190 0x4dc 0x000 0x3 0x0
+#define MX53_PAD_EIM_LBA__SRC_BT_CFG1_0				0x190 0x4dc 0x000 0x7 0x0
+#define MX53_PAD_EIM_EB0__EMI_WEIM_EB_0				0x194 0x4e4 0x000 0x0 0x0
+#define MX53_PAD_EIM_EB0__GPIO2_28				0x194 0x4e4 0x000 0x1 0x0
+#define MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11			0x194 0x4e4 0x000 0x3 0x0
+#define MX53_PAD_EIM_EB0__IPU_CSI1_D_11				0x194 0x4e4 0x000 0x4 0x0
+#define MX53_PAD_EIM_EB0__GPC_PMIC_RDY				0x194 0x4e4 0x810 0x5 0x0
+#define MX53_PAD_EIM_EB0__SRC_BT_CFG2_7				0x194 0x4e4 0x000 0x7 0x0
+#define MX53_PAD_EIM_EB1__EMI_WEIM_EB_1				0x198 0x4e8 0x000 0x0 0x0
+#define MX53_PAD_EIM_EB1__GPIO2_29				0x198 0x4e8 0x000 0x1 0x0
+#define MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10			0x198 0x4e8 0x000 0x3 0x0
+#define MX53_PAD_EIM_EB1__IPU_CSI1_D_10				0x198 0x4e8 0x000 0x4 0x0
+#define MX53_PAD_EIM_EB1__SRC_BT_CFG2_6				0x198 0x4e8 0x000 0x7 0x0
+#define MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0			0x19c 0x4ec 0x000 0x0 0x0
+#define MX53_PAD_EIM_DA0__GPIO3_0				0x19c 0x4ec 0x000 0x1 0x0
+#define MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9			0x19c 0x4ec 0x000 0x3 0x0
+#define MX53_PAD_EIM_DA0__IPU_CSI1_D_9				0x19c 0x4ec 0x000 0x4 0x0
+#define MX53_PAD_EIM_DA0__SRC_BT_CFG2_5				0x19c 0x4ec 0x000 0x7 0x0
+#define MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1			0x1a0 0x4f0 0x000 0x0 0x0
+#define MX53_PAD_EIM_DA1__GPIO3_1				0x1a0 0x4f0 0x000 0x1 0x0
+#define MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8			0x1a0 0x4f0 0x000 0x3 0x0
+#define MX53_PAD_EIM_DA1__IPU_CSI1_D_8				0x1a0 0x4f0 0x000 0x4 0x0
+#define MX53_PAD_EIM_DA1__SRC_BT_CFG2_4				0x1a0 0x4f0 0x000 0x7 0x0
+#define MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2			0x1a4 0x4f4 0x000 0x0 0x0
+#define MX53_PAD_EIM_DA2__GPIO3_2				0x1a4 0x4f4 0x000 0x1 0x0
+#define MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7			0x1a4 0x4f4 0x000 0x3 0x0
+#define MX53_PAD_EIM_DA2__IPU_CSI1_D_7				0x1a4 0x4f4 0x000 0x4 0x0
+#define MX53_PAD_EIM_DA2__SRC_BT_CFG2_3				0x1a4 0x4f4 0x000 0x7 0x0
+#define MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3			0x1a8 0x4f8 0x000 0x0 0x0
+#define MX53_PAD_EIM_DA3__GPIO3_3				0x1a8 0x4f8 0x000 0x1 0x0
+#define MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6			0x1a8 0x4f8 0x000 0x3 0x0
+#define MX53_PAD_EIM_DA3__IPU_CSI1_D_6				0x1a8 0x4f8 0x000 0x4 0x0
+#define MX53_PAD_EIM_DA3__SRC_BT_CFG2_2				0x1a8 0x4f8 0x000 0x7 0x0
+#define MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4			0x1ac 0x4fc 0x000 0x0 0x0
+#define MX53_PAD_EIM_DA4__GPIO3_4				0x1ac 0x4fc 0x000 0x1 0x0
+#define MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5			0x1ac 0x4fc 0x000 0x3 0x0
+#define MX53_PAD_EIM_DA4__IPU_CSI1_D_5				0x1ac 0x4fc 0x000 0x4 0x0
+#define MX53_PAD_EIM_DA4__SRC_BT_CFG3_7				0x1ac 0x4fc 0x000 0x7 0x0
+#define MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5			0x1b0 0x500 0x000 0x0 0x0
+#define MX53_PAD_EIM_DA5__GPIO3_5				0x1b0 0x500 0x000 0x1 0x0
+#define MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4			0x1b0 0x500 0x000 0x3 0x0
+#define MX53_PAD_EIM_DA5__IPU_CSI1_D_4				0x1b0 0x500 0x000 0x4 0x0
+#define MX53_PAD_EIM_DA5__SRC_BT_CFG3_6				0x1b0 0x500 0x000 0x7 0x0
+#define MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6			0x1b4 0x504 0x000 0x0 0x0
+#define MX53_PAD_EIM_DA6__GPIO3_6				0x1b4 0x504 0x000 0x1 0x0
+#define MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3			0x1b4 0x504 0x000 0x3 0x0
+#define MX53_PAD_EIM_DA6__IPU_CSI1_D_3				0x1b4 0x504 0x000 0x4 0x0
+#define MX53_PAD_EIM_DA6__SRC_BT_CFG3_5				0x1b4 0x504 0x000 0x7 0x0
+#define MX53_PAD_EIM_DA7__EMI_NAND_WEIM_DA_7			0x1b8 0x508 0x000 0x0 0x0
+#define MX53_PAD_EIM_DA7__GPIO3_7				0x1b8 0x508 0x000 0x1 0x0
+#define MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2			0x1b8 0x508 0x000 0x3 0x0
+#define MX53_PAD_EIM_DA7__IPU_CSI1_D_2				0x1b8 0x508 0x000 0x4 0x0
+#define MX53_PAD_EIM_DA7__SRC_BT_CFG3_4				0x1b8 0x508 0x000 0x7 0x0
+#define MX53_PAD_EIM_DA8__EMI_NAND_WEIM_DA_8			0x1bc 0x50c 0x000 0x0 0x0
+#define MX53_PAD_EIM_DA8__GPIO3_8				0x1bc 0x50c 0x000 0x1 0x0
+#define MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1			0x1bc 0x50c 0x000 0x3 0x0
+#define MX53_PAD_EIM_DA8__IPU_CSI1_D_1				0x1bc 0x50c 0x000 0x4 0x0
+#define MX53_PAD_EIM_DA8__SRC_BT_CFG3_3				0x1bc 0x50c 0x000 0x7 0x0
+#define MX53_PAD_EIM_DA9__EMI_NAND_WEIM_DA_9			0x1c0 0x510 0x000 0x0 0x0
+#define MX53_PAD_EIM_DA9__GPIO3_9				0x1c0 0x510 0x000 0x1 0x0
+#define MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0			0x1c0 0x510 0x000 0x3 0x0
+#define MX53_PAD_EIM_DA9__IPU_CSI1_D_0				0x1c0 0x510 0x000 0x4 0x0
+#define MX53_PAD_EIM_DA9__SRC_BT_CFG3_2				0x1c0 0x510 0x000 0x7 0x0
+#define MX53_PAD_EIM_DA10__EMI_NAND_WEIM_DA_10			0x1c4 0x514 0x000 0x0 0x0
+#define MX53_PAD_EIM_DA10__GPIO3_10				0x1c4 0x514 0x000 0x1 0x0
+#define MX53_PAD_EIM_DA10__IPU_DI1_PIN15			0x1c4 0x514 0x000 0x3 0x0
+#define MX53_PAD_EIM_DA10__IPU_CSI1_DATA_EN			0x1c4 0x514 0x834 0x4 0x1
+#define MX53_PAD_EIM_DA10__SRC_BT_CFG3_1			0x1c4 0x514 0x000 0x7 0x0
+#define MX53_PAD_EIM_DA11__EMI_NAND_WEIM_DA_11			0x1c8 0x518 0x000 0x0 0x0
+#define MX53_PAD_EIM_DA11__GPIO3_11				0x1c8 0x518 0x000 0x1 0x0
+#define MX53_PAD_EIM_DA11__IPU_DI1_PIN2				0x1c8 0x518 0x000 0x3 0x0
+#define MX53_PAD_EIM_DA11__IPU_CSI1_HSYNC			0x1c8 0x518 0x838 0x4 0x1
+#define MX53_PAD_EIM_DA12__EMI_NAND_WEIM_DA_12			0x1cc 0x51c 0x000 0x0 0x0
+#define MX53_PAD_EIM_DA12__GPIO3_12				0x1cc 0x51c 0x000 0x1 0x0
+#define MX53_PAD_EIM_DA12__IPU_DI1_PIN3				0x1cc 0x51c 0x000 0x3 0x0
+#define MX53_PAD_EIM_DA12__IPU_CSI1_VSYNC			0x1cc 0x51c 0x83c 0x4 0x1
+#define MX53_PAD_EIM_DA13__EMI_NAND_WEIM_DA_13			0x1d0 0x520 0x000 0x0 0x0
+#define MX53_PAD_EIM_DA13__GPIO3_13				0x1d0 0x520 0x000 0x1 0x0
+#define MX53_PAD_EIM_DA13__IPU_DI1_D0_CS			0x1d0 0x520 0x000 0x3 0x0
+#define MX53_PAD_EIM_DA13__CCM_DI1_EXT_CLK			0x1d0 0x520 0x76c 0x4 0x1
+#define MX53_PAD_EIM_DA14__EMI_NAND_WEIM_DA_14			0x1d4 0x524 0x000 0x0 0x0
+#define MX53_PAD_EIM_DA14__GPIO3_14				0x1d4 0x524 0x000 0x1 0x0
+#define MX53_PAD_EIM_DA14__IPU_DI1_D1_CS			0x1d4 0x524 0x000 0x3 0x0
+#define MX53_PAD_EIM_DA14__CCM_DI0_EXT_CLK			0x1d4 0x524 0x000 0x4 0x0
+#define MX53_PAD_EIM_DA15__EMI_NAND_WEIM_DA_15			0x1d8 0x528 0x000 0x0 0x0
+#define MX53_PAD_EIM_DA15__GPIO3_15				0x1d8 0x528 0x000 0x1 0x0
+#define MX53_PAD_EIM_DA15__IPU_DI1_PIN1				0x1d8 0x528 0x000 0x3 0x0
+#define MX53_PAD_EIM_DA15__IPU_DI1_PIN4				0x1d8 0x528 0x000 0x4 0x0
+#define MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B			0x1dc 0x52c 0x000 0x0 0x0
+#define MX53_PAD_NANDF_WE_B__GPIO6_12				0x1dc 0x52c 0x000 0x1 0x0
+#define MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B			0x1e0 0x530 0x000 0x0 0x0
+#define MX53_PAD_NANDF_RE_B__GPIO6_13				0x1e0 0x530 0x000 0x1 0x0
+#define MX53_PAD_EIM_WAIT__EMI_WEIM_WAIT			0x1e4 0x534 0x000 0x0 0x0
+#define MX53_PAD_EIM_WAIT__GPIO5_0				0x1e4 0x534 0x000 0x1 0x0
+#define MX53_PAD_EIM_WAIT__EMI_WEIM_DTACK_B			0x1e4 0x534 0x000 0x2 0x0
+#define MX53_PAD_LVDS1_TX3_P__GPIO6_22				0x1ec 0x000 0x000 0x0 0x0
+#define MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3			0x1ec 0x000 0x000 0x1 0x0
+#define MX53_PAD_LVDS1_TX2_P__GPIO6_24				0x1f0 0x000 0x000 0x0 0x0
+#define MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2			0x1f0 0x000 0x000 0x1 0x0
+#define MX53_PAD_LVDS1_CLK_P__GPIO6_26				0x1f4 0x000 0x000 0x0 0x0
+#define MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK			0x1f4 0x000 0x000 0x1 0x0
+#define MX53_PAD_LVDS1_TX1_P__GPIO6_28				0x1f8 0x000 0x000 0x0 0x0
+#define MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1			0x1f8 0x000 0x000 0x1 0x0
+#define MX53_PAD_LVDS1_TX0_P__GPIO6_30				0x1fc 0x000 0x000 0x0 0x0
+#define MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0			0x1fc 0x000 0x000 0x1 0x0
+#define MX53_PAD_LVDS0_TX3_P__GPIO7_22				0x200 0x000 0x000 0x0 0x0
+#define MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3			0x200 0x000 0x000 0x1 0x0
+#define MX53_PAD_LVDS0_CLK_P__GPIO7_24				0x204 0x000 0x000 0x0 0x0
+#define MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK			0x204 0x000 0x000 0x1 0x0
+#define MX53_PAD_LVDS0_TX2_P__GPIO7_26				0x208 0x000 0x000 0x0 0x0
+#define MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2			0x208 0x000 0x000 0x1 0x0
+#define MX53_PAD_LVDS0_TX1_P__GPIO7_28				0x20c 0x000 0x000 0x0 0x0
+#define MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1			0x20c 0x000 0x000 0x1 0x0
+#define MX53_PAD_LVDS0_TX0_P__GPIO7_30				0x210 0x000 0x000 0x0 0x0
+#define MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0			0x210 0x000 0x000 0x1 0x0
+#define MX53_PAD_GPIO_10__GPIO4_0				0x214 0x540 0x000 0x0 0x0
+#define MX53_PAD_GPIO_10__OSC32k_32K_OUT			0x214 0x540 0x000 0x1 0x0
+#define MX53_PAD_GPIO_11__GPIO4_1				0x218 0x544 0x000 0x0 0x0
+#define MX53_PAD_GPIO_12__GPIO4_2				0x21c 0x548 0x000 0x0 0x0
+#define MX53_PAD_GPIO_13__GPIO4_3				0x220 0x54c 0x000 0x0 0x0
+#define MX53_PAD_GPIO_14__GPIO4_4				0x224 0x550 0x000 0x0 0x0
+#define MX53_PAD_NANDF_CLE__EMI_NANDF_CLE			0x228 0x5a0 0x000 0x0 0x0
+#define MX53_PAD_NANDF_CLE__GPIO6_7				0x228 0x5a0 0x000 0x1 0x0
+#define MX53_PAD_NANDF_CLE__USBPHY1_VSTATUS_0			0x228 0x5a0 0x000 0x7 0x0
+#define MX53_PAD_NANDF_ALE__EMI_NANDF_ALE			0x22c 0x5a4 0x000 0x0 0x0
+#define MX53_PAD_NANDF_ALE__GPIO6_8				0x22c 0x5a4 0x000 0x1 0x0
+#define MX53_PAD_NANDF_ALE__USBPHY1_VSTATUS_1			0x22c 0x5a4 0x000 0x7 0x0
+#define MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B			0x230 0x5a8 0x000 0x0 0x0
+#define MX53_PAD_NANDF_WP_B__GPIO6_9				0x230 0x5a8 0x000 0x1 0x0
+#define MX53_PAD_NANDF_WP_B__USBPHY1_VSTATUS_2			0x230 0x5a8 0x000 0x7 0x0
+#define MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0			0x234 0x5ac 0x000 0x0 0x0
+#define MX53_PAD_NANDF_RB0__GPIO6_10				0x234 0x5ac 0x000 0x1 0x0
+#define MX53_PAD_NANDF_RB0__USBPHY1_VSTATUS_3			0x234 0x5ac 0x000 0x7 0x0
+#define MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0			0x238 0x5b0 0x000 0x0 0x0
+#define MX53_PAD_NANDF_CS0__GPIO6_11				0x238 0x5b0 0x000 0x1 0x0
+#define MX53_PAD_NANDF_CS0__USBPHY1_VSTATUS_4			0x238 0x5b0 0x000 0x7 0x0
+#define MX53_PAD_NANDF_CS1__EMI_NANDF_CS_1			0x23c 0x5b4 0x000 0x0 0x0
+#define MX53_PAD_NANDF_CS1__GPIO6_14				0x23c 0x5b4 0x000 0x1 0x0
+#define MX53_PAD_NANDF_CS1__MLB_MLBCLK				0x23c 0x5b4 0x858 0x6 0x0
+#define MX53_PAD_NANDF_CS1__USBPHY1_VSTATUS_5			0x23c 0x5b4 0x000 0x7 0x0
+#define MX53_PAD_NANDF_CS2__EMI_NANDF_CS_2			0x240 0x5b8 0x000 0x0 0x0
+#define MX53_PAD_NANDF_CS2__GPIO6_15				0x240 0x5b8 0x000 0x1 0x0
+#define MX53_PAD_NANDF_CS2__IPU_SISG_0				0x240 0x5b8 0x000 0x2 0x0
+#define MX53_PAD_NANDF_CS2__ESAI1_TX0				0x240 0x5b8 0x7e4 0x3 0x0
+#define MX53_PAD_NANDF_CS2__EMI_WEIM_CRE			0x240 0x5b8 0x000 0x4 0x0
+#define MX53_PAD_NANDF_CS2__CCM_CSI0_MCLK			0x240 0x5b8 0x000 0x5 0x0
+#define MX53_PAD_NANDF_CS2__MLB_MLBSIG				0x240 0x5b8 0x860 0x6 0x0
+#define MX53_PAD_NANDF_CS2__USBPHY1_VSTATUS_6			0x240 0x5b8 0x000 0x7 0x0
+#define MX53_PAD_NANDF_CS3__EMI_NANDF_CS_3			0x244 0x5bc 0x000 0x0 0x0
+#define MX53_PAD_NANDF_CS3__GPIO6_16				0x244 0x5bc 0x000 0x1 0x0
+#define MX53_PAD_NANDF_CS3__IPU_SISG_1				0x244 0x5bc 0x000 0x2 0x0
+#define MX53_PAD_NANDF_CS3__ESAI1_TX1				0x244 0x5bc 0x7e8 0x3 0x0
+#define MX53_PAD_NANDF_CS3__EMI_WEIM_A_26			0x244 0x5bc 0x000 0x4 0x0
+#define MX53_PAD_NANDF_CS3__MLB_MLBDAT				0x244 0x5bc 0x85c 0x6 0x0
+#define MX53_PAD_NANDF_CS3__USBPHY1_VSTATUS_7			0x244 0x5bc 0x000 0x7 0x0
+#define MX53_PAD_FEC_MDIO__FEC_MDIO				0x248 0x5c4 0x804 0x0 0x1
+#define MX53_PAD_FEC_MDIO__GPIO1_22				0x248 0x5c4 0x000 0x1 0x0
+#define MX53_PAD_FEC_MDIO__ESAI1_SCKR				0x248 0x5c4 0x7dc 0x2 0x0
+#define MX53_PAD_FEC_MDIO__FEC_COL				0x248 0x5c4 0x800 0x3 0x1
+#define MX53_PAD_FEC_MDIO__RTC_CE_RTC_PS2			0x248 0x5c4 0x000 0x4 0x0
+#define MX53_PAD_FEC_MDIO__SDMA_DEBUG_BUS_DEVICE_3		0x248 0x5c4 0x000 0x5 0x0
+#define MX53_PAD_FEC_MDIO__EMI_EMI_DEBUG_49			0x248 0x5c4 0x000 0x6 0x0
+#define MX53_PAD_FEC_REF_CLK__FEC_TX_CLK			0x24c 0x5c8 0x000 0x0 0x0
+#define MX53_PAD_FEC_REF_CLK__GPIO1_23				0x24c 0x5c8 0x000 0x1 0x0
+#define MX53_PAD_FEC_REF_CLK__ESAI1_FSR				0x24c 0x5c8 0x7cc 0x2 0x0
+#define MX53_PAD_FEC_REF_CLK__SDMA_DEBUG_BUS_DEVICE_4		0x24c 0x5c8 0x000 0x5 0x0
+#define MX53_PAD_FEC_REF_CLK__EMI_EMI_DEBUG_50			0x24c 0x5c8 0x000 0x6 0x0
+#define MX53_PAD_FEC_RX_ER__FEC_RX_ER				0x250 0x5cc 0x000 0x0 0x0
+#define MX53_PAD_FEC_RX_ER__GPIO1_24				0x250 0x5cc 0x000 0x1 0x0
+#define MX53_PAD_FEC_RX_ER__ESAI1_HCKR				0x250 0x5cc 0x7d4 0x2 0x0
+#define MX53_PAD_FEC_RX_ER__FEC_RX_CLK				0x250 0x5cc 0x808 0x3 0x1
+#define MX53_PAD_FEC_RX_ER__RTC_CE_RTC_PS3			0x250 0x5cc 0x000 0x4 0x0
+#define MX53_PAD_FEC_CRS_DV__FEC_RX_DV				0x254 0x5d0 0x000 0x0 0x0
+#define MX53_PAD_FEC_CRS_DV__GPIO1_25				0x254 0x5d0 0x000 0x1 0x0
+#define MX53_PAD_FEC_CRS_DV__ESAI1_SCKT				0x254 0x5d0 0x7e0 0x2 0x0
+#define MX53_PAD_FEC_RXD1__FEC_RDATA_1				0x258 0x5d4 0x000 0x0 0x0
+#define MX53_PAD_FEC_RXD1__GPIO1_26				0x258 0x5d4 0x000 0x1 0x0
+#define MX53_PAD_FEC_RXD1__ESAI1_FST				0x258 0x5d4 0x7d0 0x2 0x0
+#define MX53_PAD_FEC_RXD1__MLB_MLBSIG				0x258 0x5d4 0x860 0x3 0x1
+#define MX53_PAD_FEC_RXD1__RTC_CE_RTC_PS1			0x258 0x5d4 0x000 0x4 0x0
+#define MX53_PAD_FEC_RXD0__FEC_RDATA_0				0x25c 0x5d8 0x000 0x0 0x0
+#define MX53_PAD_FEC_RXD0__GPIO1_27				0x25c 0x5d8 0x000 0x1 0x0
+#define MX53_PAD_FEC_RXD0__ESAI1_HCKT				0x25c 0x5d8 0x7d8 0x2 0x0
+#define MX53_PAD_FEC_RXD0__OSC32k_32K_OUT			0x25c 0x5d8 0x000 0x3 0x0
+#define MX53_PAD_FEC_TX_EN__FEC_TX_EN				0x260 0x5dc 0x000 0x0 0x0
+#define MX53_PAD_FEC_TX_EN__GPIO1_28				0x260 0x5dc 0x000 0x1 0x0
+#define MX53_PAD_FEC_TX_EN__ESAI1_TX3_RX2			0x260 0x5dc 0x7f0 0x2 0x0
+#define MX53_PAD_FEC_TXD1__FEC_TDATA_1				0x264 0x5e0 0x000 0x0 0x0
+#define MX53_PAD_FEC_TXD1__GPIO1_29				0x264 0x5e0 0x000 0x1 0x0
+#define MX53_PAD_FEC_TXD1__ESAI1_TX2_RX3			0x264 0x5e0 0x7ec 0x2 0x0
+#define MX53_PAD_FEC_TXD1__MLB_MLBCLK				0x264 0x5e0 0x858 0x3 0x1
+#define MX53_PAD_FEC_TXD1__RTC_CE_RTC_PRSC_CLK			0x264 0x5e0 0x000 0x4 0x0
+#define MX53_PAD_FEC_TXD0__FEC_TDATA_0				0x268 0x5e4 0x000 0x0 0x0
+#define MX53_PAD_FEC_TXD0__GPIO1_30				0x268 0x5e4 0x000 0x1 0x0
+#define MX53_PAD_FEC_TXD0__ESAI1_TX4_RX1			0x268 0x5e4 0x7f4 0x2 0x0
+#define MX53_PAD_FEC_TXD0__USBPHY2_DATAOUT_0			0x268 0x5e4 0x000 0x7 0x0
+#define MX53_PAD_FEC_MDC__FEC_MDC				0x26c 0x5e8 0x000 0x0 0x0
+#define MX53_PAD_FEC_MDC__GPIO1_31				0x26c 0x5e8 0x000 0x1 0x0
+#define MX53_PAD_FEC_MDC__ESAI1_TX5_RX0				0x26c 0x5e8 0x7f8 0x2 0x0
+#define MX53_PAD_FEC_MDC__MLB_MLBDAT				0x26c 0x5e8 0x85c 0x3 0x1
+#define MX53_PAD_FEC_MDC__RTC_CE_RTC_ALARM1_TRIG		0x26c 0x5e8 0x000 0x4 0x0
+#define MX53_PAD_FEC_MDC__USBPHY2_DATAOUT_1			0x26c 0x5e8 0x000 0x7 0x0
+#define MX53_PAD_PATA_DIOW__PATA_DIOW				0x270 0x5f0 0x000 0x0 0x0
+#define MX53_PAD_PATA_DIOW__GPIO6_17				0x270 0x5f0 0x000 0x1 0x0
+#define MX53_PAD_PATA_DIOW__UART1_TXD_MUX			0x270 0x5f0 0x000 0x3 0x0
+#define MX53_PAD_PATA_DIOW__USBPHY2_DATAOUT_2			0x270 0x5f0 0x000 0x7 0x0
+#define MX53_PAD_PATA_DMACK__PATA_DMACK				0x274 0x5f4 0x000 0x0 0x0
+#define MX53_PAD_PATA_DMACK__GPIO6_18				0x274 0x5f4 0x000 0x1 0x0
+#define MX53_PAD_PATA_DMACK__UART1_RXD_MUX			0x274 0x5f4 0x878 0x3 0x3
+#define MX53_PAD_PATA_DMACK__USBPHY2_DATAOUT_3			0x274 0x5f4 0x000 0x7 0x0
+#define MX53_PAD_PATA_DMARQ__PATA_DMARQ				0x278 0x5f8 0x000 0x0 0x0
+#define MX53_PAD_PATA_DMARQ__GPIO7_0				0x278 0x5f8 0x000 0x1 0x0
+#define MX53_PAD_PATA_DMARQ__UART2_TXD_MUX			0x278 0x5f8 0x000 0x3 0x0
+#define MX53_PAD_PATA_DMARQ__CCM_CCM_OUT_0			0x278 0x5f8 0x000 0x5 0x0
+#define MX53_PAD_PATA_DMARQ__USBPHY2_DATAOUT_4			0x278 0x5f8 0x000 0x7 0x0
+#define MX53_PAD_PATA_BUFFER_EN__PATA_BUFFER_EN			0x27c 0x5fc 0x000 0x0 0x0
+#define MX53_PAD_PATA_BUFFER_EN__GPIO7_1			0x27c 0x5fc 0x000 0x1 0x0
+#define MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX			0x27c 0x5fc 0x880 0x3 0x3
+#define MX53_PAD_PATA_BUFFER_EN__CCM_CCM_OUT_1			0x27c 0x5fc 0x000 0x5 0x0
+#define MX53_PAD_PATA_BUFFER_EN__USBPHY2_DATAOUT_5		0x27c 0x5fc 0x000 0x7 0x0
+#define MX53_PAD_PATA_INTRQ__PATA_INTRQ				0x280 0x600 0x000 0x0 0x0
+#define MX53_PAD_PATA_INTRQ__GPIO7_2				0x280 0x600 0x000 0x1 0x0
+#define MX53_PAD_PATA_INTRQ__UART2_CTS				0x280 0x600 0x000 0x3 0x0
+#define MX53_PAD_PATA_INTRQ__CAN1_TXCAN				0x280 0x600 0x000 0x4 0x0
+#define MX53_PAD_PATA_INTRQ__CCM_CCM_OUT_2			0x280 0x600 0x000 0x5 0x0
+#define MX53_PAD_PATA_INTRQ__USBPHY2_DATAOUT_6			0x280 0x600 0x000 0x7 0x0
+#define MX53_PAD_PATA_DIOR__PATA_DIOR				0x284 0x604 0x000 0x0 0x0
+#define MX53_PAD_PATA_DIOR__GPIO7_3				0x284 0x604 0x000 0x1 0x0
+#define MX53_PAD_PATA_DIOR__UART2_RTS				0x284 0x604 0x87c 0x3 0x3
+#define MX53_PAD_PATA_DIOR__CAN1_RXCAN				0x284 0x604 0x760 0x4 0x1
+#define MX53_PAD_PATA_DIOR__USBPHY2_DATAOUT_7			0x284 0x604 0x000 0x7 0x0
+#define MX53_PAD_PATA_RESET_B__PATA_PATA_RESET_B		0x288 0x608 0x000 0x0 0x0
+#define MX53_PAD_PATA_RESET_B__GPIO7_4				0x288 0x608 0x000 0x1 0x0
+#define MX53_PAD_PATA_RESET_B__ESDHC3_CMD			0x288 0x608 0x000 0x2 0x0
+#define MX53_PAD_PATA_RESET_B__UART1_CTS			0x288 0x608 0x000 0x3 0x0
+#define MX53_PAD_PATA_RESET_B__CAN2_TXCAN			0x288 0x608 0x000 0x4 0x0
+#define MX53_PAD_PATA_RESET_B__USBPHY1_DATAOUT_0		0x288 0x608 0x000 0x7 0x0
+#define MX53_PAD_PATA_IORDY__PATA_IORDY				0x28c 0x60c 0x000 0x0 0x0
+#define MX53_PAD_PATA_IORDY__GPIO7_5				0x28c 0x60c 0x000 0x1 0x0
+#define MX53_PAD_PATA_IORDY__ESDHC3_CLK				0x28c 0x60c 0x000 0x2 0x0
+#define MX53_PAD_PATA_IORDY__UART1_RTS				0x28c 0x60c 0x874 0x3 0x3
+#define MX53_PAD_PATA_IORDY__CAN2_RXCAN				0x28c 0x60c 0x764 0x4 0x1
+#define MX53_PAD_PATA_IORDY__USBPHY1_DATAOUT_1			0x28c 0x60c 0x000 0x7 0x0
+#define MX53_PAD_PATA_DA_0__PATA_DA_0				0x290 0x610 0x000 0x0 0x0
+#define MX53_PAD_PATA_DA_0__GPIO7_6				0x290 0x610 0x000 0x1 0x0
+#define MX53_PAD_PATA_DA_0__ESDHC3_RST				0x290 0x610 0x000 0x2 0x0
+#define MX53_PAD_PATA_DA_0__OWIRE_LINE				0x290 0x610 0x864 0x4 0x0
+#define MX53_PAD_PATA_DA_0__USBPHY1_DATAOUT_2			0x290 0x610 0x000 0x7 0x0
+#define MX53_PAD_PATA_DA_1__PATA_DA_1				0x294 0x614 0x000 0x0 0x0
+#define MX53_PAD_PATA_DA_1__GPIO7_7				0x294 0x614 0x000 0x1 0x0
+#define MX53_PAD_PATA_DA_1__ESDHC4_CMD				0x294 0x614 0x000 0x2 0x0
+#define MX53_PAD_PATA_DA_1__UART3_CTS				0x294 0x614 0x000 0x4 0x0
+#define MX53_PAD_PATA_DA_1__USBPHY1_DATAOUT_3			0x294 0x614 0x000 0x7 0x0
+#define MX53_PAD_PATA_DA_2__PATA_DA_2				0x298 0x618 0x000 0x0 0x0
+#define MX53_PAD_PATA_DA_2__GPIO7_8				0x298 0x618 0x000 0x1 0x0
+#define MX53_PAD_PATA_DA_2__ESDHC4_CLK				0x298 0x618 0x000 0x2 0x0
+#define MX53_PAD_PATA_DA_2__UART3_RTS				0x298 0x618 0x884 0x4 0x5
+#define MX53_PAD_PATA_DA_2__USBPHY1_DATAOUT_4			0x298 0x618 0x000 0x7 0x0
+#define MX53_PAD_PATA_CS_0__PATA_CS_0				0x29c 0x61c 0x000 0x0 0x0
+#define MX53_PAD_PATA_CS_0__GPIO7_9				0x29c 0x61c 0x000 0x1 0x0
+#define MX53_PAD_PATA_CS_0__UART3_TXD_MUX			0x29c 0x61c 0x000 0x4 0x0
+#define MX53_PAD_PATA_CS_0__USBPHY1_DATAOUT_5			0x29c 0x61c 0x000 0x7 0x0
+#define MX53_PAD_PATA_CS_1__PATA_CS_1				0x2a0 0x620 0x000 0x0 0x0
+#define MX53_PAD_PATA_CS_1__GPIO7_10				0x2a0 0x620 0x000 0x1 0x0
+#define MX53_PAD_PATA_CS_1__UART3_RXD_MUX			0x2a0 0x620 0x888 0x4 0x3
+#define MX53_PAD_PATA_CS_1__USBPHY1_DATAOUT_6			0x2a0 0x620 0x000 0x7 0x0
+#define MX53_PAD_PATA_DATA0__PATA_DATA_0			0x2a4 0x628 0x000 0x0 0x0
+#define MX53_PAD_PATA_DATA0__GPIO2_0				0x2a4 0x628 0x000 0x1 0x0
+#define MX53_PAD_PATA_DATA0__EMI_NANDF_D_0			0x2a4 0x628 0x000 0x3 0x0
+#define MX53_PAD_PATA_DATA0__ESDHC3_DAT4			0x2a4 0x628 0x000 0x4 0x0
+#define MX53_PAD_PATA_DATA0__GPU3d_GPU_DEBUG_OUT_0		0x2a4 0x628 0x000 0x5 0x0
+#define MX53_PAD_PATA_DATA0__IPU_DIAG_BUS_0			0x2a4 0x628 0x000 0x6 0x0
+#define MX53_PAD_PATA_DATA0__USBPHY1_DATAOUT_7			0x2a4 0x628 0x000 0x7 0x0
+#define MX53_PAD_PATA_DATA1__PATA_DATA_1			0x2a8 0x62c 0x000 0x0 0x0
+#define MX53_PAD_PATA_DATA1__GPIO2_1				0x2a8 0x62c 0x000 0x1 0x0
+#define MX53_PAD_PATA_DATA1__EMI_NANDF_D_1			0x2a8 0x62c 0x000 0x3 0x0
+#define MX53_PAD_PATA_DATA1__ESDHC3_DAT5			0x2a8 0x62c 0x000 0x4 0x0
+#define MX53_PAD_PATA_DATA1__GPU3d_GPU_DEBUG_OUT_1		0x2a8 0x62c 0x000 0x5 0x0
+#define MX53_PAD_PATA_DATA1__IPU_DIAG_BUS_1			0x2a8 0x62c 0x000 0x6 0x0
+#define MX53_PAD_PATA_DATA2__PATA_DATA_2			0x2ac 0x630 0x000 0x0 0x0
+#define MX53_PAD_PATA_DATA2__GPIO2_2				0x2ac 0x630 0x000 0x1 0x0
+#define MX53_PAD_PATA_DATA2__EMI_NANDF_D_2			0x2ac 0x630 0x000 0x3 0x0
+#define MX53_PAD_PATA_DATA2__ESDHC3_DAT6			0x2ac 0x630 0x000 0x4 0x0
+#define MX53_PAD_PATA_DATA2__GPU3d_GPU_DEBUG_OUT_2		0x2ac 0x630 0x000 0x5 0x0
+#define MX53_PAD_PATA_DATA2__IPU_DIAG_BUS_2			0x2ac 0x630 0x000 0x6 0x0
+#define MX53_PAD_PATA_DATA3__PATA_DATA_3			0x2b0 0x634 0x000 0x0 0x0
+#define MX53_PAD_PATA_DATA3__GPIO2_3				0x2b0 0x634 0x000 0x1 0x0
+#define MX53_PAD_PATA_DATA3__EMI_NANDF_D_3			0x2b0 0x634 0x000 0x3 0x0
+#define MX53_PAD_PATA_DATA3__ESDHC3_DAT7			0x2b0 0x634 0x000 0x4 0x0
+#define MX53_PAD_PATA_DATA3__GPU3d_GPU_DEBUG_OUT_3		0x2b0 0x634 0x000 0x5 0x0
+#define MX53_PAD_PATA_DATA3__IPU_DIAG_BUS_3			0x2b0 0x634 0x000 0x6 0x0
+#define MX53_PAD_PATA_DATA4__PATA_DATA_4			0x2b4 0x638 0x000 0x0 0x0
+#define MX53_PAD_PATA_DATA4__GPIO2_4				0x2b4 0x638 0x000 0x1 0x0
+#define MX53_PAD_PATA_DATA4__EMI_NANDF_D_4			0x2b4 0x638 0x000 0x3 0x0
+#define MX53_PAD_PATA_DATA4__ESDHC4_DAT4			0x2b4 0x638 0x000 0x4 0x0
+#define MX53_PAD_PATA_DATA4__GPU3d_GPU_DEBUG_OUT_4		0x2b4 0x638 0x000 0x5 0x0
+#define MX53_PAD_PATA_DATA4__IPU_DIAG_BUS_4			0x2b4 0x638 0x000 0x6 0x0
+#define MX53_PAD_PATA_DATA5__PATA_DATA_5			0x2b8 0x63c 0x000 0x0 0x0
+#define MX53_PAD_PATA_DATA5__GPIO2_5				0x2b8 0x63c 0x000 0x1 0x0
+#define MX53_PAD_PATA_DATA5__EMI_NANDF_D_5			0x2b8 0x63c 0x000 0x3 0x0
+#define MX53_PAD_PATA_DATA5__ESDHC4_DAT5			0x2b8 0x63c 0x000 0x4 0x0
+#define MX53_PAD_PATA_DATA5__GPU3d_GPU_DEBUG_OUT_5		0x2b8 0x63c 0x000 0x5 0x0
+#define MX53_PAD_PATA_DATA5__IPU_DIAG_BUS_5			0x2b8 0x63c 0x000 0x6 0x0
+#define MX53_PAD_PATA_DATA6__PATA_DATA_6			0x2bc 0x640 0x000 0x0 0x0
+#define MX53_PAD_PATA_DATA6__GPIO2_6				0x2bc 0x640 0x000 0x1 0x0
+#define MX53_PAD_PATA_DATA6__EMI_NANDF_D_6			0x2bc 0x640 0x000 0x3 0x0
+#define MX53_PAD_PATA_DATA6__ESDHC4_DAT6			0x2bc 0x640 0x000 0x4 0x0
+#define MX53_PAD_PATA_DATA6__GPU3d_GPU_DEBUG_OUT_6		0x2bc 0x640 0x000 0x5 0x0
+#define MX53_PAD_PATA_DATA6__IPU_DIAG_BUS_6			0x2bc 0x640 0x000 0x6 0x0
+#define MX53_PAD_PATA_DATA7__PATA_DATA_7			0x2c0 0x644 0x000 0x0 0x0
+#define MX53_PAD_PATA_DATA7__GPIO2_7				0x2c0 0x644 0x000 0x1 0x0
+#define MX53_PAD_PATA_DATA7__EMI_NANDF_D_7			0x2c0 0x644 0x000 0x3 0x0
+#define MX53_PAD_PATA_DATA7__ESDHC4_DAT7			0x2c0 0x644 0x000 0x4 0x0
+#define MX53_PAD_PATA_DATA7__GPU3d_GPU_DEBUG_OUT_7		0x2c0 0x644 0x000 0x5 0x0
+#define MX53_PAD_PATA_DATA7__IPU_DIAG_BUS_7			0x2c0 0x644 0x000 0x6 0x0
+#define MX53_PAD_PATA_DATA8__PATA_DATA_8			0x2c4 0x648 0x000 0x0 0x0
+#define MX53_PAD_PATA_DATA8__GPIO2_8				0x2c4 0x648 0x000 0x1 0x0
+#define MX53_PAD_PATA_DATA8__ESDHC1_DAT4			0x2c4 0x648 0x000 0x2 0x0
+#define MX53_PAD_PATA_DATA8__EMI_NANDF_D_8			0x2c4 0x648 0x000 0x3 0x0
+#define MX53_PAD_PATA_DATA8__ESDHC3_DAT0			0x2c4 0x648 0x000 0x4 0x0
+#define MX53_PAD_PATA_DATA8__GPU3d_GPU_DEBUG_OUT_8		0x2c4 0x648 0x000 0x5 0x0
+#define MX53_PAD_PATA_DATA8__IPU_DIAG_BUS_8			0x2c4 0x648 0x000 0x6 0x0
+#define MX53_PAD_PATA_DATA9__PATA_DATA_9			0x2c8 0x64c 0x000 0x0 0x0
+#define MX53_PAD_PATA_DATA9__GPIO2_9				0x2c8 0x64c 0x000 0x1 0x0
+#define MX53_PAD_PATA_DATA9__ESDHC1_DAT5			0x2c8 0x64c 0x000 0x2 0x0
+#define MX53_PAD_PATA_DATA9__EMI_NANDF_D_9			0x2c8 0x64c 0x000 0x3 0x0
+#define MX53_PAD_PATA_DATA9__ESDHC3_DAT1			0x2c8 0x64c 0x000 0x4 0x0
+#define MX53_PAD_PATA_DATA9__GPU3d_GPU_DEBUG_OUT_9		0x2c8 0x64c 0x000 0x5 0x0
+#define MX53_PAD_PATA_DATA9__IPU_DIAG_BUS_9			0x2c8 0x64c 0x000 0x6 0x0
+#define MX53_PAD_PATA_DATA10__PATA_DATA_10			0x2cc 0x650 0x000 0x0 0x0
+#define MX53_PAD_PATA_DATA10__GPIO2_10				0x2cc 0x650 0x000 0x1 0x0
+#define MX53_PAD_PATA_DATA10__ESDHC1_DAT6			0x2cc 0x650 0x000 0x2 0x0
+#define MX53_PAD_PATA_DATA10__EMI_NANDF_D_10			0x2cc 0x650 0x000 0x3 0x0
+#define MX53_PAD_PATA_DATA10__ESDHC3_DAT2			0x2cc 0x650 0x000 0x4 0x0
+#define MX53_PAD_PATA_DATA10__GPU3d_GPU_DEBUG_OUT_10		0x2cc 0x650 0x000 0x5 0x0
+#define MX53_PAD_PATA_DATA10__IPU_DIAG_BUS_10			0x2cc 0x650 0x000 0x6 0x0
+#define MX53_PAD_PATA_DATA11__PATA_DATA_11			0x2d0 0x654 0x000 0x0 0x0
+#define MX53_PAD_PATA_DATA11__GPIO2_11				0x2d0 0x654 0x000 0x1 0x0
+#define MX53_PAD_PATA_DATA11__ESDHC1_DAT7			0x2d0 0x654 0x000 0x2 0x0
+#define MX53_PAD_PATA_DATA11__EMI_NANDF_D_11			0x2d0 0x654 0x000 0x3 0x0
+#define MX53_PAD_PATA_DATA11__ESDHC3_DAT3			0x2d0 0x654 0x000 0x4 0x0
+#define MX53_PAD_PATA_DATA11__GPU3d_GPU_DEBUG_OUT_11		0x2d0 0x654 0x000 0x5 0x0
+#define MX53_PAD_PATA_DATA11__IPU_DIAG_BUS_11			0x2d0 0x654 0x000 0x6 0x0
+#define MX53_PAD_PATA_DATA12__PATA_DATA_12			0x2d4 0x658 0x000 0x0 0x0
+#define MX53_PAD_PATA_DATA12__GPIO2_12				0x2d4 0x658 0x000 0x1 0x0
+#define MX53_PAD_PATA_DATA12__ESDHC2_DAT4			0x2d4 0x658 0x000 0x2 0x0
+#define MX53_PAD_PATA_DATA12__EMI_NANDF_D_12			0x2d4 0x658 0x000 0x3 0x0
+#define MX53_PAD_PATA_DATA12__ESDHC4_DAT0			0x2d4 0x658 0x000 0x4 0x0
+#define MX53_PAD_PATA_DATA12__GPU3d_GPU_DEBUG_OUT_12		0x2d4 0x658 0x000 0x5 0x0
+#define MX53_PAD_PATA_DATA12__IPU_DIAG_BUS_12			0x2d4 0x658 0x000 0x6 0x0
+#define MX53_PAD_PATA_DATA13__PATA_DATA_13			0x2d8 0x65c 0x000 0x0 0x0
+#define MX53_PAD_PATA_DATA13__GPIO2_13				0x2d8 0x65c 0x000 0x1 0x0
+#define MX53_PAD_PATA_DATA13__ESDHC2_DAT5			0x2d8 0x65c 0x000 0x2 0x0
+#define MX53_PAD_PATA_DATA13__EMI_NANDF_D_13			0x2d8 0x65c 0x000 0x3 0x0
+#define MX53_PAD_PATA_DATA13__ESDHC4_DAT1			0x2d8 0x65c 0x000 0x4 0x0
+#define MX53_PAD_PATA_DATA13__GPU3d_GPU_DEBUG_OUT_13		0x2d8 0x65c 0x000 0x5 0x0
+#define MX53_PAD_PATA_DATA13__IPU_DIAG_BUS_13			0x2d8 0x65c 0x000 0x6 0x0
+#define MX53_PAD_PATA_DATA14__PATA_DATA_14			0x2dc 0x660 0x000 0x0 0x0
+#define MX53_PAD_PATA_DATA14__GPIO2_14				0x2dc 0x660 0x000 0x1 0x0
+#define MX53_PAD_PATA_DATA14__ESDHC2_DAT6			0x2dc 0x660 0x000 0x2 0x0
+#define MX53_PAD_PATA_DATA14__EMI_NANDF_D_14			0x2dc 0x660 0x000 0x3 0x0
+#define MX53_PAD_PATA_DATA14__ESDHC4_DAT2			0x2dc 0x660 0x000 0x4 0x0
+#define MX53_PAD_PATA_DATA14__GPU3d_GPU_DEBUG_OUT_14		0x2dc 0x660 0x000 0x5 0x0
+#define MX53_PAD_PATA_DATA14__IPU_DIAG_BUS_14			0x2dc 0x660 0x000 0x6 0x0
+#define MX53_PAD_PATA_DATA15__PATA_DATA_15			0x2e0 0x664 0x000 0x0 0x0
+#define MX53_PAD_PATA_DATA15__GPIO2_15				0x2e0 0x664 0x000 0x1 0x0
+#define MX53_PAD_PATA_DATA15__ESDHC2_DAT7			0x2e0 0x664 0x000 0x2 0x0
+#define MX53_PAD_PATA_DATA15__EMI_NANDF_D_15			0x2e0 0x664 0x000 0x3 0x0
+#define MX53_PAD_PATA_DATA15__ESDHC4_DAT3			0x2e0 0x664 0x000 0x4 0x0
+#define MX53_PAD_PATA_DATA15__GPU3d_GPU_DEBUG_OUT_15		0x2e0 0x664 0x000 0x5 0x0
+#define MX53_PAD_PATA_DATA15__IPU_DIAG_BUS_15			0x2e0 0x664 0x000 0x6 0x0
+#define MX53_PAD_SD1_DATA0__ESDHC1_DAT0				0x2e4 0x66c 0x000 0x0 0x0
+#define MX53_PAD_SD1_DATA0__GPIO1_16				0x2e4 0x66c 0x000 0x1 0x0
+#define MX53_PAD_SD1_DATA0__GPT_CAPIN1				0x2e4 0x66c 0x000 0x3 0x0
+#define MX53_PAD_SD1_DATA0__CSPI_MISO				0x2e4 0x66c 0x784 0x5 0x2
+#define MX53_PAD_SD1_DATA0__CCM_PLL3_BYP			0x2e4 0x66c 0x778 0x7 0x0
+#define MX53_PAD_SD1_DATA1__ESDHC1_DAT1				0x2e8 0x670 0x000 0x0 0x0
+#define MX53_PAD_SD1_DATA1__GPIO1_17				0x2e8 0x670 0x000 0x1 0x0
+#define MX53_PAD_SD1_DATA1__GPT_CAPIN2				0x2e8 0x670 0x000 0x3 0x0
+#define MX53_PAD_SD1_DATA1__CSPI_SS0				0x2e8 0x670 0x78c 0x5 0x3
+#define MX53_PAD_SD1_DATA1__CCM_PLL4_BYP			0x2e8 0x670 0x77c 0x7 0x1
+#define MX53_PAD_SD1_CMD__ESDHC1_CMD				0x2ec 0x674 0x000 0x0 0x0
+#define MX53_PAD_SD1_CMD__GPIO1_18				0x2ec 0x674 0x000 0x1 0x0
+#define MX53_PAD_SD1_CMD__GPT_CMPOUT1				0x2ec 0x674 0x000 0x3 0x0
+#define MX53_PAD_SD1_CMD__CSPI_MOSI				0x2ec 0x674 0x788 0x5 0x2
+#define MX53_PAD_SD1_CMD__CCM_PLL1_BYP				0x2ec 0x674 0x770 0x7 0x0
+#define MX53_PAD_SD1_DATA2__ESDHC1_DAT2				0x2f0 0x678 0x000 0x0 0x0
+#define MX53_PAD_SD1_DATA2__GPIO1_19				0x2f0 0x678 0x000 0x1 0x0
+#define MX53_PAD_SD1_DATA2__GPT_CMPOUT2				0x2f0 0x678 0x000 0x2 0x0
+#define MX53_PAD_SD1_DATA2__PWM2_PWMO				0x2f0 0x678 0x000 0x3 0x0
+#define MX53_PAD_SD1_DATA2__WDOG1_WDOG_B			0x2f0 0x678 0x000 0x4 0x0
+#define MX53_PAD_SD1_DATA2__CSPI_SS1				0x2f0 0x678 0x790 0x5 0x2
+#define MX53_PAD_SD1_DATA2__WDOG1_WDOG_RST_B_DEB		0x2f0 0x678 0x000 0x6 0x0
+#define MX53_PAD_SD1_DATA2__CCM_PLL2_BYP			0x2f0 0x678 0x774 0x7 0x0
+#define MX53_PAD_SD1_CLK__ESDHC1_CLK				0x2f4 0x67c 0x000 0x0 0x0
+#define MX53_PAD_SD1_CLK__GPIO1_20				0x2f4 0x67c 0x000 0x1 0x0
+#define MX53_PAD_SD1_CLK__OSC32k_32K_OUT			0x2f4 0x67c 0x000 0x2 0x0
+#define MX53_PAD_SD1_CLK__GPT_CLKIN				0x2f4 0x67c 0x000 0x3 0x0
+#define MX53_PAD_SD1_CLK__CSPI_SCLK				0x2f4 0x67c 0x780 0x5 0x2
+#define MX53_PAD_SD1_CLK__SATA_PHY_DTB_0			0x2f4 0x67c 0x000 0x7 0x0
+#define MX53_PAD_SD1_DATA3__ESDHC1_DAT3				0x2f8 0x680 0x000 0x0 0x0
+#define MX53_PAD_SD1_DATA3__GPIO1_21				0x2f8 0x680 0x000 0x1 0x0
+#define MX53_PAD_SD1_DATA3__GPT_CMPOUT3				0x2f8 0x680 0x000 0x2 0x0
+#define MX53_PAD_SD1_DATA3__PWM1_PWMO				0x2f8 0x680 0x000 0x3 0x0
+#define MX53_PAD_SD1_DATA3__WDOG2_WDOG_B			0x2f8 0x680 0x000 0x4 0x0
+#define MX53_PAD_SD1_DATA3__CSPI_SS2				0x2f8 0x680 0x794 0x5 0x2
+#define MX53_PAD_SD1_DATA3__WDOG2_WDOG_RST_B_DEB		0x2f8 0x680 0x000 0x6 0x0
+#define MX53_PAD_SD1_DATA3__SATA_PHY_DTB_1			0x2f8 0x680 0x000 0x7 0x0
+#define MX53_PAD_SD2_CLK__ESDHC2_CLK				0x2fc 0x688 0x000 0x0 0x0
+#define MX53_PAD_SD2_CLK__GPIO1_10				0x2fc 0x688 0x000 0x1 0x0
+#define MX53_PAD_SD2_CLK__KPP_COL_5				0x2fc 0x688 0x840 0x2 0x2
+#define MX53_PAD_SD2_CLK__AUDMUX_AUD4_RXFS			0x2fc 0x688 0x73c 0x3 0x1
+#define MX53_PAD_SD2_CLK__CSPI_SCLK				0x2fc 0x688 0x780 0x5 0x3
+#define MX53_PAD_SD2_CLK__SCC_RANDOM_V				0x2fc 0x688 0x000 0x7 0x0
+#define MX53_PAD_SD2_CMD__ESDHC2_CMD				0x300 0x68c 0x000 0x0 0x0
+#define MX53_PAD_SD2_CMD__GPIO1_11				0x300 0x68c 0x000 0x1 0x0
+#define MX53_PAD_SD2_CMD__KPP_ROW_5				0x300 0x68c 0x84c 0x2 0x1
+#define MX53_PAD_SD2_CMD__AUDMUX_AUD4_RXC			0x300 0x68c 0x738 0x3 0x1
+#define MX53_PAD_SD2_CMD__CSPI_MOSI				0x300 0x68c 0x788 0x5 0x3
+#define MX53_PAD_SD2_CMD__SCC_RANDOM				0x300 0x68c 0x000 0x7 0x0
+#define MX53_PAD_SD2_DATA3__ESDHC2_DAT3				0x304 0x690 0x000 0x0 0x0
+#define MX53_PAD_SD2_DATA3__GPIO1_12				0x304 0x690 0x000 0x1 0x0
+#define MX53_PAD_SD2_DATA3__KPP_COL_6				0x304 0x690 0x844 0x2 0x1
+#define MX53_PAD_SD2_DATA3__AUDMUX_AUD4_TXC			0x304 0x690 0x740 0x3 0x1
+#define MX53_PAD_SD2_DATA3__CSPI_SS2				0x304 0x690 0x794 0x5 0x3
+#define MX53_PAD_SD2_DATA3__SJC_DONE				0x304 0x690 0x000 0x7 0x0
+#define MX53_PAD_SD2_DATA2__ESDHC2_DAT2				0x308 0x694 0x000 0x0 0x0
+#define MX53_PAD_SD2_DATA2__GPIO1_13				0x308 0x694 0x000 0x1 0x0
+#define MX53_PAD_SD2_DATA2__KPP_ROW_6				0x308 0x694 0x850 0x2 0x1
+#define MX53_PAD_SD2_DATA2__AUDMUX_AUD4_TXD			0x308 0x694 0x734 0x3 0x1
+#define MX53_PAD_SD2_DATA2__CSPI_SS1				0x308 0x694 0x790 0x5 0x3
+#define MX53_PAD_SD2_DATA2__SJC_FAIL				0x308 0x694 0x000 0x7 0x0
+#define MX53_PAD_SD2_DATA1__ESDHC2_DAT1				0x30c 0x698 0x000 0x0 0x0
+#define MX53_PAD_SD2_DATA1__GPIO1_14				0x30c 0x698 0x000 0x1 0x0
+#define MX53_PAD_SD2_DATA1__KPP_COL_7				0x30c 0x698 0x848 0x2 0x1
+#define MX53_PAD_SD2_DATA1__AUDMUX_AUD4_TXFS			0x30c 0x698 0x744 0x3 0x1
+#define MX53_PAD_SD2_DATA1__CSPI_SS0				0x30c 0x698 0x78c 0x5 0x4
+#define MX53_PAD_SD2_DATA1__RTIC_SEC_VIO			0x30c 0x698 0x000 0x7 0x0
+#define MX53_PAD_SD2_DATA0__ESDHC2_DAT0				0x310 0x69c 0x000 0x0 0x0
+#define MX53_PAD_SD2_DATA0__GPIO1_15				0x310 0x69c 0x000 0x1 0x0
+#define MX53_PAD_SD2_DATA0__KPP_ROW_7				0x310 0x69c 0x854 0x2 0x1
+#define MX53_PAD_SD2_DATA0__AUDMUX_AUD4_RXD			0x310 0x69c 0x730 0x3 0x1
+#define MX53_PAD_SD2_DATA0__CSPI_MISO				0x310 0x69c 0x784 0x5 0x3
+#define MX53_PAD_SD2_DATA0__RTIC_DONE_INT			0x310 0x69c 0x000 0x7 0x0
+#define MX53_PAD_GPIO_0__CCM_CLKO				0x314 0x6a4 0x000 0x0 0x0
+#define MX53_PAD_GPIO_0__GPIO1_0				0x314 0x6a4 0x000 0x1 0x0
+#define MX53_PAD_GPIO_0__KPP_COL_5				0x314 0x6a4 0x840 0x2 0x3
+#define MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK			0x314 0x6a4 0x000 0x3 0x0
+#define MX53_PAD_GPIO_0__EPIT1_EPITO				0x314 0x6a4 0x000 0x4 0x0
+#define MX53_PAD_GPIO_0__SRTC_ALARM_DEB				0x314 0x6a4 0x000 0x5 0x0
+#define MX53_PAD_GPIO_0__USBOH3_USBH1_PWR			0x314 0x6a4 0x000 0x6 0x0
+#define MX53_PAD_GPIO_0__CSU_TD					0x314 0x6a4 0x000 0x7 0x0
+#define MX53_PAD_GPIO_1__ESAI1_SCKR				0x318 0x6a8 0x7dc 0x0 0x1
+#define MX53_PAD_GPIO_1__GPIO1_1				0x318 0x6a8 0x000 0x1 0x0
+#define MX53_PAD_GPIO_1__KPP_ROW_5				0x318 0x6a8 0x84c 0x2 0x2
+#define MX53_PAD_GPIO_1__CCM_SSI_EXT2_CLK			0x318 0x6a8 0x000 0x3 0x0
+#define MX53_PAD_GPIO_1__PWM2_PWMO				0x318 0x6a8 0x000 0x4 0x0
+#define MX53_PAD_GPIO_1__WDOG2_WDOG_B				0x318 0x6a8 0x000 0x5 0x0
+#define MX53_PAD_GPIO_1__ESDHC1_CD				0x318 0x6a8 0x000 0x6 0x0
+#define MX53_PAD_GPIO_1__SRC_TESTER_ACK				0x318 0x6a8 0x000 0x7 0x0
+#define MX53_PAD_GPIO_9__ESAI1_FSR				0x31c 0x6ac 0x7cc 0x0 0x1
+#define MX53_PAD_GPIO_9__GPIO1_9				0x31c 0x6ac 0x000 0x1 0x0
+#define MX53_PAD_GPIO_9__KPP_COL_6				0x31c 0x6ac 0x844 0x2 0x2
+#define MX53_PAD_GPIO_9__CCM_REF_EN_B				0x31c 0x6ac 0x000 0x3 0x0
+#define MX53_PAD_GPIO_9__PWM1_PWMO				0x31c 0x6ac 0x000 0x4 0x0
+#define MX53_PAD_GPIO_9__WDOG1_WDOG_B				0x31c 0x6ac 0x000 0x5 0x0
+#define MX53_PAD_GPIO_9__ESDHC1_WP				0x31c 0x6ac 0x7fc 0x6 0x1
+#define MX53_PAD_GPIO_9__SCC_FAIL_STATE				0x31c 0x6ac 0x000 0x7 0x0
+#define MX53_PAD_GPIO_3__ESAI1_HCKR				0x320 0x6b0 0x7d4 0x0 0x1
+#define MX53_PAD_GPIO_3__GPIO1_3				0x320 0x6b0 0x000 0x1 0x0
+#define MX53_PAD_GPIO_3__I2C3_SCL				0x320 0x6b0 0x824 0x2 0x1
+#define MX53_PAD_GPIO_3__DPLLIP1_TOG_EN				0x320 0x6b0 0x000 0x3 0x0
+#define MX53_PAD_GPIO_3__CCM_CLKO2				0x320 0x6b0 0x000 0x4 0x0
+#define MX53_PAD_GPIO_3__OBSERVE_MUX_OBSRV_INT_OUT0		0x320 0x6b0 0x000 0x5 0x0
+#define MX53_PAD_GPIO_3__USBOH3_USBH1_OC			0x320 0x6b0 0x8a0 0x6 0x1
+#define MX53_PAD_GPIO_3__MLB_MLBCLK				0x320 0x6b0 0x858 0x7 0x2
+#define MX53_PAD_GPIO_6__ESAI1_SCKT				0x324 0x6b4 0x7e0 0x0 0x1
+#define MX53_PAD_GPIO_6__GPIO1_6				0x324 0x6b4 0x000 0x1 0x0
+#define MX53_PAD_GPIO_6__I2C3_SDA				0x324 0x6b4 0x828 0x2 0x1
+#define MX53_PAD_GPIO_6__CCM_CCM_OUT_0				0x324 0x6b4 0x000 0x3 0x0
+#define MX53_PAD_GPIO_6__CSU_CSU_INT_DEB			0x324 0x6b4 0x000 0x4 0x0
+#define MX53_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1		0x324 0x6b4 0x000 0x5 0x0
+#define MX53_PAD_GPIO_6__ESDHC2_LCTL				0x324 0x6b4 0x000 0x6 0x0
+#define MX53_PAD_GPIO_6__MLB_MLBSIG				0x324 0x6b4 0x860 0x7 0x2
+#define MX53_PAD_GPIO_2__ESAI1_FST				0x328 0x6b8 0x7d0 0x0 0x1
+#define MX53_PAD_GPIO_2__GPIO1_2				0x328 0x6b8 0x000 0x1 0x0
+#define MX53_PAD_GPIO_2__KPP_ROW_6				0x328 0x6b8 0x850 0x2 0x2
+#define MX53_PAD_GPIO_2__CCM_CCM_OUT_1				0x328 0x6b8 0x000 0x3 0x0
+#define MX53_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0			0x328 0x6b8 0x000 0x4 0x0
+#define MX53_PAD_GPIO_2__OBSERVE_MUX_OBSRV_INT_OUT2		0x328 0x6b8 0x000 0x5 0x0
+#define MX53_PAD_GPIO_2__ESDHC2_WP				0x328 0x6b8 0x000 0x6 0x0
+#define MX53_PAD_GPIO_2__MLB_MLBDAT				0x328 0x6b8 0x85c 0x7 0x2
+#define MX53_PAD_GPIO_4__ESAI1_HCKT				0x32c 0x6bc 0x7d8 0x0 0x1
+#define MX53_PAD_GPIO_4__GPIO1_4				0x32c 0x6bc 0x000 0x1 0x0
+#define MX53_PAD_GPIO_4__KPP_COL_7				0x32c 0x6bc 0x848 0x2 0x2
+#define MX53_PAD_GPIO_4__CCM_CCM_OUT_2				0x32c 0x6bc 0x000 0x3 0x0
+#define MX53_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1			0x32c 0x6bc 0x000 0x4 0x0
+#define MX53_PAD_GPIO_4__OBSERVE_MUX_OBSRV_INT_OUT3		0x32c 0x6bc 0x000 0x5 0x0
+#define MX53_PAD_GPIO_4__ESDHC2_CD				0x32c 0x6bc 0x000 0x6 0x0
+#define MX53_PAD_GPIO_4__SCC_SEC_STATE				0x32c 0x6bc 0x000 0x7 0x0
+#define MX53_PAD_GPIO_5__ESAI1_TX2_RX3				0x330 0x6c0 0x7ec 0x0 0x1
+#define MX53_PAD_GPIO_5__GPIO1_5				0x330 0x6c0 0x000 0x1 0x0
+#define MX53_PAD_GPIO_5__KPP_ROW_7				0x330 0x6c0 0x854 0x2 0x2
+#define MX53_PAD_GPIO_5__CCM_CLKO				0x330 0x6c0 0x000 0x3 0x0
+#define MX53_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2			0x330 0x6c0 0x000 0x4 0x0
+#define MX53_PAD_GPIO_5__OBSERVE_MUX_OBSRV_INT_OUT4		0x330 0x6c0 0x000 0x5 0x0
+#define MX53_PAD_GPIO_5__I2C3_SCL				0x330 0x6c0 0x824 0x6 0x2
+#define MX53_PAD_GPIO_5__CCM_PLL1_BYP				0x330 0x6c0 0x770 0x7 0x1
+#define MX53_PAD_GPIO_7__ESAI1_TX4_RX1				0x334 0x6c4 0x7f4 0x0 0x1
+#define MX53_PAD_GPIO_7__GPIO1_7				0x334 0x6c4 0x000 0x1 0x0
+#define MX53_PAD_GPIO_7__EPIT1_EPITO				0x334 0x6c4 0x000 0x2 0x0
+#define MX53_PAD_GPIO_7__CAN1_TXCAN				0x334 0x6c4 0x000 0x3 0x0
+#define MX53_PAD_GPIO_7__UART2_TXD_MUX				0x334 0x6c4 0x000 0x4 0x0
+#define MX53_PAD_GPIO_7__FIRI_RXD				0x334 0x6c4 0x80c 0x5 0x1
+#define MX53_PAD_GPIO_7__SPDIF_PLOCK				0x334 0x6c4 0x000 0x6 0x0
+#define MX53_PAD_GPIO_7__CCM_PLL2_BYP				0x334 0x6c4 0x774 0x7 0x1
+#define MX53_PAD_GPIO_8__ESAI1_TX5_RX0				0x338 0x6c8 0x7f8 0x0 0x1
+#define MX53_PAD_GPIO_8__GPIO1_8				0x338 0x6c8 0x000 0x1 0x0
+#define MX53_PAD_GPIO_8__EPIT2_EPITO				0x338 0x6c8 0x000 0x2 0x0
+#define MX53_PAD_GPIO_8__CAN1_RXCAN				0x338 0x6c8 0x760 0x3 0x2
+#define MX53_PAD_GPIO_8__UART2_RXD_MUX				0x338 0x6c8 0x880 0x4 0x5
+#define MX53_PAD_GPIO_8__FIRI_TXD				0x338 0x6c8 0x000 0x5 0x0
+#define MX53_PAD_GPIO_8__SPDIF_SRCLK				0x338 0x6c8 0x000 0x6 0x0
+#define MX53_PAD_GPIO_8__CCM_PLL3_BYP				0x338 0x6c8 0x778 0x7 0x1
+#define MX53_PAD_GPIO_16__ESAI1_TX3_RX2				0x33c 0x6cc 0x7f0 0x0 0x1
+#define MX53_PAD_GPIO_16__GPIO7_11				0x33c 0x6cc 0x000 0x1 0x0
+#define MX53_PAD_GPIO_16__TZIC_PWRFAIL_INT			0x33c 0x6cc 0x000 0x2 0x0
+#define MX53_PAD_GPIO_16__RTC_CE_RTC_EXT_TRIG1			0x33c 0x6cc 0x000 0x4 0x0
+#define MX53_PAD_GPIO_16__SPDIF_IN1				0x33c 0x6cc 0x870 0x5 0x1
+#define MX53_PAD_GPIO_16__I2C3_SDA				0x33c 0x6cc 0x828 0x6 0x2
+#define MX53_PAD_GPIO_16__SJC_DE_B				0x33c 0x6cc 0x000 0x7 0x0
+#define MX53_PAD_GPIO_17__ESAI1_TX0				0x340 0x6d0 0x7e4 0x0 0x1
+#define MX53_PAD_GPIO_17__GPIO7_12				0x340 0x6d0 0x000 0x1 0x0
+#define MX53_PAD_GPIO_17__SDMA_EXT_EVENT_0			0x340 0x6d0 0x868 0x2 0x1
+#define MX53_PAD_GPIO_17__GPC_PMIC_RDY				0x340 0x6d0 0x810 0x3 0x1
+#define MX53_PAD_GPIO_17__RTC_CE_RTC_FSV_TRIG			0x340 0x6d0 0x000 0x4 0x0
+#define MX53_PAD_GPIO_17__SPDIF_OUT1				0x340 0x6d0 0x000 0x5 0x0
+#define MX53_PAD_GPIO_17__IPU_SNOOP2				0x340 0x6d0 0x000 0x6 0x0
+#define MX53_PAD_GPIO_17__SJC_JTAG_ACT				0x340 0x6d0 0x000 0x7 0x0
+#define MX53_PAD_GPIO_18__ESAI1_TX1				0x344 0x6d4 0x7e8 0x0 0x1
+#define MX53_PAD_GPIO_18__GPIO7_13				0x344 0x6d4 0x000 0x1 0x0
+#define MX53_PAD_GPIO_18__SDMA_EXT_EVENT_1			0x344 0x6d4 0x86c 0x2 0x1
+#define MX53_PAD_GPIO_18__OWIRE_LINE				0x344 0x6d4 0x864 0x3 0x1
+#define MX53_PAD_GPIO_18__RTC_CE_RTC_ALARM2_TRIG		0x344 0x6d4 0x000 0x4 0x0
+#define MX53_PAD_GPIO_18__CCM_ASRC_EXT_CLK			0x344 0x6d4 0x768 0x5 0x1
+#define MX53_PAD_GPIO_18__ESDHC1_LCTL				0x344 0x6d4 0x000 0x6 0x0
+#define MX53_PAD_GPIO_18__SRC_SYSTEM_RST			0x344 0x6d4 0x000 0x7 0x0
+
+#endif /* __DTS_IMX53_PINFUNC_H */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/imx6dl-pinfunc.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/imx6dl-pinfunc.h
new file mode 100644
index 0000000000000000000000000000000000000000..37e430a261de642c5eb6619eeff2eeb357cf4a57
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/imx6dl-pinfunc.h
@@ -0,0 +1,1092 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __DTS_IMX6DL_PINFUNC_H
+#define __DTS_IMX6DL_PINFUNC_H
+
+/*
+ * The pin function ID is a tuple of
+ * <mux_reg conf_reg input_reg mux_mode input_val>
+ */
+#define MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10     0x04c 0x360 0x000 0x0 0x0
+#define MX6QDL_PAD_CSI0_DAT10__AUD3_RXC             0x04c 0x360 0x000 0x1 0x0
+#define MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO          0x04c 0x360 0x7f8 0x2 0x0
+#define MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA        0x04c 0x360 0x000 0x3 0x0
+#define MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA        0x04c 0x360 0x8fc 0x3 0x0
+#define MX6QDL_PAD_CSI0_DAT10__GPIO5_IO28           0x04c 0x360 0x000 0x5 0x0
+#define MX6QDL_PAD_CSI0_DAT10__ARM_TRACE07          0x04c 0x360 0x000 0x7 0x0
+#define MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11     0x050 0x364 0x000 0x0 0x0
+#define MX6QDL_PAD_CSI0_DAT11__AUD3_RXFS            0x050 0x364 0x000 0x1 0x0
+#define MX6QDL_PAD_CSI0_DAT11__ECSPI2_SS0           0x050 0x364 0x800 0x2 0x0
+#define MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA        0x050 0x364 0x8fc 0x3 0x1
+#define MX6QDL_PAD_CSI0_DAT11__UART1_TX_DATA        0x050 0x364 0x000 0x3 0x0
+#define MX6QDL_PAD_CSI0_DAT11__GPIO5_IO29           0x050 0x364 0x000 0x5 0x0
+#define MX6QDL_PAD_CSI0_DAT11__ARM_TRACE08          0x050 0x364 0x000 0x7 0x0
+#define MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12     0x054 0x368 0x000 0x0 0x0
+#define MX6QDL_PAD_CSI0_DAT12__EIM_DATA08           0x054 0x368 0x000 0x1 0x0
+#define MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA        0x054 0x368 0x000 0x3 0x0
+#define MX6QDL_PAD_CSI0_DAT12__UART4_RX_DATA        0x054 0x368 0x914 0x3 0x0
+#define MX6QDL_PAD_CSI0_DAT12__GPIO5_IO30           0x054 0x368 0x000 0x5 0x0
+#define MX6QDL_PAD_CSI0_DAT12__ARM_TRACE09          0x054 0x368 0x000 0x7 0x0
+#define MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13     0x058 0x36c 0x000 0x0 0x0
+#define MX6QDL_PAD_CSI0_DAT13__EIM_DATA09           0x058 0x36c 0x000 0x1 0x0
+#define MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA        0x058 0x36c 0x914 0x3 0x1
+#define MX6QDL_PAD_CSI0_DAT13__UART4_TX_DATA        0x058 0x36c 0x000 0x3 0x0
+#define MX6QDL_PAD_CSI0_DAT13__GPIO5_IO31           0x058 0x36c 0x000 0x5 0x0
+#define MX6QDL_PAD_CSI0_DAT13__ARM_TRACE10          0x058 0x36c 0x000 0x7 0x0
+#define MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14     0x05c 0x370 0x000 0x0 0x0
+#define MX6QDL_PAD_CSI0_DAT14__EIM_DATA10           0x05c 0x370 0x000 0x1 0x0
+#define MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA        0x05c 0x370 0x000 0x3 0x0
+#define MX6QDL_PAD_CSI0_DAT14__UART5_RX_DATA        0x05c 0x370 0x91c 0x3 0x0
+#define MX6QDL_PAD_CSI0_DAT14__GPIO6_IO00           0x05c 0x370 0x000 0x5 0x0
+#define MX6QDL_PAD_CSI0_DAT14__ARM_TRACE11          0x05c 0x370 0x000 0x7 0x0
+#define MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15     0x060 0x374 0x000 0x0 0x0
+#define MX6QDL_PAD_CSI0_DAT15__EIM_DATA11           0x060 0x374 0x000 0x1 0x0
+#define MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA        0x060 0x374 0x91c 0x3 0x1
+#define MX6QDL_PAD_CSI0_DAT15__UART5_TX_DATA        0x060 0x374 0x000 0x3 0x0
+#define MX6QDL_PAD_CSI0_DAT15__GPIO6_IO01           0x060 0x374 0x000 0x5 0x0
+#define MX6QDL_PAD_CSI0_DAT15__ARM_TRACE12          0x060 0x374 0x000 0x7 0x0
+#define MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16     0x064 0x378 0x000 0x0 0x0
+#define MX6QDL_PAD_CSI0_DAT16__EIM_DATA12           0x064 0x378 0x000 0x1 0x0
+#define MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B          0x064 0x378 0x910 0x3 0x0
+#define MX6QDL_PAD_CSI0_DAT16__UART4_CTS_B          0x064 0x378 0x000 0x3 0x0
+#define MX6QDL_PAD_CSI0_DAT16__GPIO6_IO02           0x064 0x378 0x000 0x5 0x0
+#define MX6QDL_PAD_CSI0_DAT16__ARM_TRACE13          0x064 0x378 0x000 0x7 0x0
+#define MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17     0x068 0x37c 0x000 0x0 0x0
+#define MX6QDL_PAD_CSI0_DAT17__EIM_DATA13           0x068 0x37c 0x000 0x1 0x0
+#define MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B          0x068 0x37c 0x000 0x3 0x0
+#define MX6QDL_PAD_CSI0_DAT17__UART4_RTS_B          0x068 0x37c 0x910 0x3 0x1
+#define MX6QDL_PAD_CSI0_DAT17__GPIO6_IO03           0x068 0x37c 0x000 0x5 0x0
+#define MX6QDL_PAD_CSI0_DAT17__ARM_TRACE14          0x068 0x37c 0x000 0x7 0x0
+#define MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18     0x06c 0x380 0x000 0x0 0x0
+#define MX6QDL_PAD_CSI0_DAT18__EIM_DATA14           0x06c 0x380 0x000 0x1 0x0
+#define MX6QDL_PAD_CSI0_DAT18__UART5_RTS_B          0x06c 0x380 0x918 0x3 0x0
+#define MX6QDL_PAD_CSI0_DAT18__UART5_CTS_B          0x06c 0x380 0x000 0x3 0x0
+#define MX6QDL_PAD_CSI0_DAT18__GPIO6_IO04           0x06c 0x380 0x000 0x5 0x0
+#define MX6QDL_PAD_CSI0_DAT18__ARM_TRACE15          0x06c 0x380 0x000 0x7 0x0
+#define MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19     0x070 0x384 0x000 0x0 0x0
+#define MX6QDL_PAD_CSI0_DAT19__EIM_DATA15           0x070 0x384 0x000 0x1 0x0
+#define MX6QDL_PAD_CSI0_DAT19__UART5_CTS_B          0x070 0x384 0x000 0x3 0x0
+#define MX6QDL_PAD_CSI0_DAT19__UART5_RTS_B          0x070 0x384 0x918 0x3 0x1
+#define MX6QDL_PAD_CSI0_DAT19__GPIO6_IO05           0x070 0x384 0x000 0x5 0x0
+#define MX6QDL_PAD_CSI0_DAT4__IPU1_CSI0_DATA04      0x074 0x388 0x000 0x0 0x0
+#define MX6QDL_PAD_CSI0_DAT4__EIM_DATA02            0x074 0x388 0x000 0x1 0x0
+#define MX6QDL_PAD_CSI0_DAT4__ECSPI1_SCLK           0x074 0x388 0x7d8 0x2 0x0
+#define MX6QDL_PAD_CSI0_DAT4__KEY_COL5              0x074 0x388 0x8c0 0x3 0x0
+#define MX6QDL_PAD_CSI0_DAT4__AUD3_TXC              0x074 0x388 0x000 0x4 0x0
+#define MX6QDL_PAD_CSI0_DAT4__GPIO5_IO22            0x074 0x388 0x000 0x5 0x0
+#define MX6QDL_PAD_CSI0_DAT4__ARM_TRACE01           0x074 0x388 0x000 0x7 0x0
+#define MX6QDL_PAD_CSI0_DAT5__IPU1_CSI0_DATA05      0x078 0x38c 0x000 0x0 0x0
+#define MX6QDL_PAD_CSI0_DAT5__EIM_DATA03            0x078 0x38c 0x000 0x1 0x0
+#define MX6QDL_PAD_CSI0_DAT5__ECSPI1_MOSI           0x078 0x38c 0x7e0 0x2 0x0
+#define MX6QDL_PAD_CSI0_DAT5__KEY_ROW5              0x078 0x38c 0x8cc 0x3 0x0
+#define MX6QDL_PAD_CSI0_DAT5__AUD3_TXD              0x078 0x38c 0x000 0x4 0x0
+#define MX6QDL_PAD_CSI0_DAT5__GPIO5_IO23            0x078 0x38c 0x000 0x5 0x0
+#define MX6QDL_PAD_CSI0_DAT5__ARM_TRACE02           0x078 0x38c 0x000 0x7 0x0
+#define MX6QDL_PAD_CSI0_DAT6__IPU1_CSI0_DATA06      0x07c 0x390 0x000 0x0 0x0
+#define MX6QDL_PAD_CSI0_DAT6__EIM_DATA04            0x07c 0x390 0x000 0x1 0x0
+#define MX6QDL_PAD_CSI0_DAT6__ECSPI1_MISO           0x07c 0x390 0x7dc 0x2 0x0
+#define MX6QDL_PAD_CSI0_DAT6__KEY_COL6              0x07c 0x390 0x8c4 0x3 0x0
+#define MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS             0x07c 0x390 0x000 0x4 0x0
+#define MX6QDL_PAD_CSI0_DAT6__GPIO5_IO24            0x07c 0x390 0x000 0x5 0x0
+#define MX6QDL_PAD_CSI0_DAT6__ARM_TRACE03           0x07c 0x390 0x000 0x7 0x0
+#define MX6QDL_PAD_CSI0_DAT7__IPU1_CSI0_DATA07      0x080 0x394 0x000 0x0 0x0
+#define MX6QDL_PAD_CSI0_DAT7__EIM_DATA05            0x080 0x394 0x000 0x1 0x0
+#define MX6QDL_PAD_CSI0_DAT7__ECSPI1_SS0            0x080 0x394 0x7e4 0x2 0x0
+#define MX6QDL_PAD_CSI0_DAT7__KEY_ROW6              0x080 0x394 0x8d0 0x3 0x0
+#define MX6QDL_PAD_CSI0_DAT7__AUD3_RXD              0x080 0x394 0x000 0x4 0x0
+#define MX6QDL_PAD_CSI0_DAT7__GPIO5_IO25            0x080 0x394 0x000 0x5 0x0
+#define MX6QDL_PAD_CSI0_DAT7__ARM_TRACE04           0x080 0x394 0x000 0x7 0x0
+#define MX6QDL_PAD_CSI0_DAT8__IPU1_CSI0_DATA08      0x084 0x398 0x000 0x0 0x0
+#define MX6QDL_PAD_CSI0_DAT8__EIM_DATA06            0x084 0x398 0x000 0x1 0x0
+#define MX6QDL_PAD_CSI0_DAT8__ECSPI2_SCLK           0x084 0x398 0x7f4 0x2 0x0
+#define MX6QDL_PAD_CSI0_DAT8__KEY_COL7              0x084 0x398 0x8c8 0x3 0x0
+#define MX6QDL_PAD_CSI0_DAT8__I2C1_SDA              0x084 0x398 0x86c 0x4 0x0
+#define MX6QDL_PAD_CSI0_DAT8__GPIO5_IO26            0x084 0x398 0x000 0x5 0x0
+#define MX6QDL_PAD_CSI0_DAT8__ARM_TRACE05           0x084 0x398 0x000 0x7 0x0
+#define MX6QDL_PAD_CSI0_DAT9__IPU1_CSI0_DATA09      0x088 0x39c 0x000 0x0 0x0
+#define MX6QDL_PAD_CSI0_DAT9__EIM_DATA07            0x088 0x39c 0x000 0x1 0x0
+#define MX6QDL_PAD_CSI0_DAT9__ECSPI2_MOSI           0x088 0x39c 0x7fc 0x2 0x0
+#define MX6QDL_PAD_CSI0_DAT9__KEY_ROW7              0x088 0x39c 0x8d4 0x3 0x0
+#define MX6QDL_PAD_CSI0_DAT9__I2C1_SCL              0x088 0x39c 0x868 0x4 0x0
+#define MX6QDL_PAD_CSI0_DAT9__GPIO5_IO27            0x088 0x39c 0x000 0x5 0x0
+#define MX6QDL_PAD_CSI0_DAT9__ARM_TRACE06           0x088 0x39c 0x000 0x7 0x0
+#define MX6QDL_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN  0x08c 0x3a0 0x000 0x0 0x0
+#define MX6QDL_PAD_CSI0_DATA_EN__EIM_DATA00         0x08c 0x3a0 0x000 0x1 0x0
+#define MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20         0x08c 0x3a0 0x000 0x5 0x0
+#define MX6QDL_PAD_CSI0_DATA_EN__ARM_TRACE_CLK      0x08c 0x3a0 0x000 0x7 0x0
+#define MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC       0x090 0x3a4 0x000 0x0 0x0
+#define MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1             0x090 0x3a4 0x000 0x3 0x0
+#define MX6QDL_PAD_CSI0_MCLK__GPIO5_IO19            0x090 0x3a4 0x000 0x5 0x0
+#define MX6QDL_PAD_CSI0_MCLK__ARM_TRACE_CTL         0x090 0x3a4 0x000 0x7 0x0
+#define MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK    0x094 0x3a8 0x000 0x0 0x0
+#define MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18          0x094 0x3a8 0x000 0x5 0x0
+#define MX6QDL_PAD_CSI0_PIXCLK__ARM_EVENTO          0x094 0x3a8 0x000 0x7 0x0
+#define MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC      0x098 0x3ac 0x000 0x0 0x0
+#define MX6QDL_PAD_CSI0_VSYNC__EIM_DATA01           0x098 0x3ac 0x000 0x1 0x0
+#define MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21           0x098 0x3ac 0x000 0x5 0x0
+#define MX6QDL_PAD_CSI0_VSYNC__ARM_TRACE00          0x098 0x3ac 0x000 0x7 0x0
+#define MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK  0x09c 0x3b0 0x000 0x0 0x0
+#define MX6QDL_PAD_DI0_DISP_CLK__LCD_CLK            0x09c 0x3b0 0x000 0x1 0x0
+#define MX6QDL_PAD_DI0_DISP_CLK__GPIO4_IO16         0x09c 0x3b0 0x000 0x5 0x0
+#define MX6QDL_PAD_DI0_DISP_CLK__LCD_WR_RWN         0x09c 0x3b0 0x000 0x8 0x0
+#define MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15        0x0a0 0x3b4 0x000 0x0 0x0
+#define MX6QDL_PAD_DI0_PIN15__LCD_ENABLE            0x0a0 0x3b4 0x000 0x1 0x0
+#define MX6QDL_PAD_DI0_PIN15__AUD6_TXC              0x0a0 0x3b4 0x000 0x2 0x0
+#define MX6QDL_PAD_DI0_PIN15__GPIO4_IO17            0x0a0 0x3b4 0x000 0x5 0x0
+#define MX6QDL_PAD_DI0_PIN15__LCD_RD_E              0x0a0 0x3b4 0x000 0x8 0x0
+#define MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02         0x0a4 0x3b8 0x000 0x0 0x0
+#define MX6QDL_PAD_DI0_PIN2__LCD_HSYNC              0x0a4 0x3b8 0x8d8 0x1 0x0
+#define MX6QDL_PAD_DI0_PIN2__AUD6_TXD               0x0a4 0x3b8 0x000 0x2 0x0
+#define MX6QDL_PAD_DI0_PIN2__GPIO4_IO18             0x0a4 0x3b8 0x000 0x5 0x0
+#define MX6QDL_PAD_DI0_PIN2__LCD_RS                 0x0a4 0x3b8 0x000 0x8 0x0
+#define MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03         0x0a8 0x3bc 0x000 0x0 0x0
+#define MX6QDL_PAD_DI0_PIN3__LCD_VSYNC              0x0a8 0x3bc 0x000 0x1 0x0
+#define MX6QDL_PAD_DI0_PIN3__AUD6_TXFS              0x0a8 0x3bc 0x000 0x2 0x0
+#define MX6QDL_PAD_DI0_PIN3__GPIO4_IO19             0x0a8 0x3bc 0x000 0x5 0x0
+#define MX6QDL_PAD_DI0_PIN3__LCD_CS                 0x0a8 0x3bc 0x000 0x8 0x0
+#define MX6QDL_PAD_DI0_PIN4__IPU1_DI0_PIN04         0x0ac 0x3c0 0x000 0x0 0x0
+#define MX6QDL_PAD_DI0_PIN4__LCD_BUSY               0x0ac 0x3c0 0x8d8 0x1 0x1
+#define MX6QDL_PAD_DI0_PIN4__AUD6_RXD               0x0ac 0x3c0 0x000 0x2 0x0
+#define MX6QDL_PAD_DI0_PIN4__SD1_WP                 0x0ac 0x3c0 0x92c 0x3 0x0
+#define MX6QDL_PAD_DI0_PIN4__GPIO4_IO20             0x0ac 0x3c0 0x000 0x5 0x0
+#define MX6QDL_PAD_DI0_PIN4__LCD_RESET              0x0ac 0x3c0 0x000 0x8 0x0
+#define MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00    0x0b0 0x3c4 0x000 0x0 0x0
+#define MX6QDL_PAD_DISP0_DAT0__LCD_DATA00           0x0b0 0x3c4 0x000 0x1 0x0
+#define MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK          0x0b0 0x3c4 0x000 0x2 0x0
+#define MX6QDL_PAD_DISP0_DAT0__GPIO4_IO21           0x0b0 0x3c4 0x000 0x5 0x0
+#define MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01    0x0b4 0x3c8 0x000 0x0 0x0
+#define MX6QDL_PAD_DISP0_DAT1__LCD_DATA01           0x0b4 0x3c8 0x000 0x1 0x0
+#define MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI          0x0b4 0x3c8 0x000 0x2 0x0
+#define MX6QDL_PAD_DISP0_DAT1__GPIO4_IO22           0x0b4 0x3c8 0x000 0x5 0x0
+#define MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10   0x0b8 0x3cc 0x000 0x0 0x0
+#define MX6QDL_PAD_DISP0_DAT10__LCD_DATA10          0x0b8 0x3cc 0x000 0x1 0x0
+#define MX6QDL_PAD_DISP0_DAT10__GPIO4_IO31          0x0b8 0x3cc 0x000 0x5 0x0
+#define MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11   0x0bc 0x3d0 0x000 0x0 0x0
+#define MX6QDL_PAD_DISP0_DAT11__LCD_DATA11          0x0bc 0x3d0 0x000 0x1 0x0
+#define MX6QDL_PAD_DISP0_DAT11__GPIO5_IO05          0x0bc 0x3d0 0x000 0x5 0x0
+#define MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12   0x0c0 0x3d4 0x000 0x0 0x0
+#define MX6QDL_PAD_DISP0_DAT12__LCD_DATA12          0x0c0 0x3d4 0x000 0x1 0x0
+#define MX6QDL_PAD_DISP0_DAT12__GPIO5_IO06          0x0c0 0x3d4 0x000 0x5 0x0
+#define MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13   0x0c4 0x3d8 0x000 0x0 0x0
+#define MX6QDL_PAD_DISP0_DAT13__LCD_DATA13          0x0c4 0x3d8 0x000 0x1 0x0
+#define MX6QDL_PAD_DISP0_DAT13__AUD5_RXFS           0x0c4 0x3d8 0x7bc 0x3 0x0
+#define MX6QDL_PAD_DISP0_DAT13__GPIO5_IO07          0x0c4 0x3d8 0x000 0x5 0x0
+#define MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14   0x0c8 0x3dc 0x000 0x0 0x0
+#define MX6QDL_PAD_DISP0_DAT14__LCD_DATA14          0x0c8 0x3dc 0x000 0x1 0x0
+#define MX6QDL_PAD_DISP0_DAT14__AUD5_RXC            0x0c8 0x3dc 0x7b8 0x3 0x0
+#define MX6QDL_PAD_DISP0_DAT14__GPIO5_IO08          0x0c8 0x3dc 0x000 0x5 0x0
+#define MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15   0x0cc 0x3e0 0x000 0x0 0x0
+#define MX6QDL_PAD_DISP0_DAT15__LCD_DATA15          0x0cc 0x3e0 0x000 0x1 0x0
+#define MX6QDL_PAD_DISP0_DAT15__ECSPI1_SS1          0x0cc 0x3e0 0x7e8 0x2 0x0
+#define MX6QDL_PAD_DISP0_DAT15__ECSPI2_SS1          0x0cc 0x3e0 0x804 0x3 0x0
+#define MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09          0x0cc 0x3e0 0x000 0x5 0x0
+#define MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16   0x0d0 0x3e4 0x000 0x0 0x0
+#define MX6QDL_PAD_DISP0_DAT16__LCD_DATA16          0x0d0 0x3e4 0x000 0x1 0x0
+#define MX6QDL_PAD_DISP0_DAT16__ECSPI2_MOSI         0x0d0 0x3e4 0x7fc 0x2 0x1
+#define MX6QDL_PAD_DISP0_DAT16__AUD5_TXC            0x0d0 0x3e4 0x7c0 0x3 0x0
+#define MX6QDL_PAD_DISP0_DAT16__SDMA_EXT_EVENT0     0x0d0 0x3e4 0x8e8 0x4 0x0
+#define MX6QDL_PAD_DISP0_DAT16__GPIO5_IO10          0x0d0 0x3e4 0x000 0x5 0x0
+#define MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17   0x0d4 0x3e8 0x000 0x0 0x0
+#define MX6QDL_PAD_DISP0_DAT17__LCD_DATA17          0x0d4 0x3e8 0x000 0x1 0x0
+#define MX6QDL_PAD_DISP0_DAT17__ECSPI2_MISO         0x0d4 0x3e8 0x7f8 0x2 0x1
+#define MX6QDL_PAD_DISP0_DAT17__AUD5_TXD            0x0d4 0x3e8 0x7b4 0x3 0x0
+#define MX6QDL_PAD_DISP0_DAT17__SDMA_EXT_EVENT1     0x0d4 0x3e8 0x8ec 0x4 0x0
+#define MX6QDL_PAD_DISP0_DAT17__GPIO5_IO11          0x0d4 0x3e8 0x000 0x5 0x0
+#define MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18   0x0d8 0x3ec 0x000 0x0 0x0
+#define MX6QDL_PAD_DISP0_DAT18__LCD_DATA18          0x0d8 0x3ec 0x000 0x1 0x0
+#define MX6QDL_PAD_DISP0_DAT18__ECSPI2_SS0          0x0d8 0x3ec 0x800 0x2 0x1
+#define MX6QDL_PAD_DISP0_DAT18__AUD5_TXFS           0x0d8 0x3ec 0x7c4 0x3 0x0
+#define MX6QDL_PAD_DISP0_DAT18__AUD4_RXFS           0x0d8 0x3ec 0x7a4 0x4 0x0
+#define MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12          0x0d8 0x3ec 0x000 0x5 0x0
+#define MX6QDL_PAD_DISP0_DAT18__EIM_CS2_B           0x0d8 0x3ec 0x000 0x7 0x0
+#define MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19   0x0dc 0x3f0 0x000 0x0 0x0
+#define MX6QDL_PAD_DISP0_DAT19__LCD_DATA19          0x0dc 0x3f0 0x000 0x1 0x0
+#define MX6QDL_PAD_DISP0_DAT19__ECSPI2_SCLK         0x0dc 0x3f0 0x7f4 0x2 0x1
+#define MX6QDL_PAD_DISP0_DAT19__AUD5_RXD            0x0dc 0x3f0 0x7b0 0x3 0x0
+#define MX6QDL_PAD_DISP0_DAT19__AUD4_RXC            0x0dc 0x3f0 0x7a0 0x4 0x0
+#define MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13          0x0dc 0x3f0 0x000 0x5 0x0
+#define MX6QDL_PAD_DISP0_DAT19__EIM_CS3_B           0x0dc 0x3f0 0x000 0x7 0x0
+#define MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02    0x0e0 0x3f4 0x000 0x0 0x0
+#define MX6QDL_PAD_DISP0_DAT2__LCD_DATA02           0x0e0 0x3f4 0x000 0x1 0x0
+#define MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO          0x0e0 0x3f4 0x000 0x2 0x0
+#define MX6QDL_PAD_DISP0_DAT2__GPIO4_IO23           0x0e0 0x3f4 0x000 0x5 0x0
+#define MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20   0x0e4 0x3f8 0x000 0x0 0x0
+#define MX6QDL_PAD_DISP0_DAT20__LCD_DATA20          0x0e4 0x3f8 0x000 0x1 0x0
+#define MX6QDL_PAD_DISP0_DAT20__ECSPI1_SCLK         0x0e4 0x3f8 0x7d8 0x2 0x1
+#define MX6QDL_PAD_DISP0_DAT20__AUD4_TXC            0x0e4 0x3f8 0x7a8 0x3 0x0
+#define MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14          0x0e4 0x3f8 0x000 0x5 0x0
+#define MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21   0x0e8 0x3fc 0x000 0x0 0x0
+#define MX6QDL_PAD_DISP0_DAT21__LCD_DATA21          0x0e8 0x3fc 0x000 0x1 0x0
+#define MX6QDL_PAD_DISP0_DAT21__ECSPI1_MOSI         0x0e8 0x3fc 0x7e0 0x2 0x1
+#define MX6QDL_PAD_DISP0_DAT21__AUD4_TXD            0x0e8 0x3fc 0x79c 0x3 0x0
+#define MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15          0x0e8 0x3fc 0x000 0x5 0x0
+#define MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22   0x0ec 0x400 0x000 0x0 0x0
+#define MX6QDL_PAD_DISP0_DAT22__LCD_DATA22          0x0ec 0x400 0x000 0x1 0x0
+#define MX6QDL_PAD_DISP0_DAT22__ECSPI1_MISO         0x0ec 0x400 0x7dc 0x2 0x1
+#define MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS           0x0ec 0x400 0x7ac 0x3 0x0
+#define MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16          0x0ec 0x400 0x000 0x5 0x0
+#define MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23   0x0f0 0x404 0x000 0x0 0x0
+#define MX6QDL_PAD_DISP0_DAT23__LCD_DATA23          0x0f0 0x404 0x000 0x1 0x0
+#define MX6QDL_PAD_DISP0_DAT23__ECSPI1_SS0          0x0f0 0x404 0x7e4 0x2 0x1
+#define MX6QDL_PAD_DISP0_DAT23__AUD4_RXD            0x0f0 0x404 0x798 0x3 0x0
+#define MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17          0x0f0 0x404 0x000 0x5 0x0
+#define MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03    0x0f4 0x408 0x000 0x0 0x0
+#define MX6QDL_PAD_DISP0_DAT3__LCD_DATA03           0x0f4 0x408 0x000 0x1 0x0
+#define MX6QDL_PAD_DISP0_DAT3__ECSPI3_SS0           0x0f4 0x408 0x000 0x2 0x0
+#define MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24           0x0f4 0x408 0x000 0x5 0x0
+#define MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04    0x0f8 0x40c 0x000 0x0 0x0
+#define MX6QDL_PAD_DISP0_DAT4__LCD_DATA04           0x0f8 0x40c 0x000 0x1 0x0
+#define MX6QDL_PAD_DISP0_DAT4__ECSPI3_SS1           0x0f8 0x40c 0x000 0x2 0x0
+#define MX6QDL_PAD_DISP0_DAT4__GPIO4_IO25           0x0f8 0x40c 0x000 0x5 0x0
+#define MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05    0x0fc 0x410 0x000 0x0 0x0
+#define MX6QDL_PAD_DISP0_DAT5__LCD_DATA05           0x0fc 0x410 0x000 0x1 0x0
+#define MX6QDL_PAD_DISP0_DAT5__ECSPI3_SS2           0x0fc 0x410 0x000 0x2 0x0
+#define MX6QDL_PAD_DISP0_DAT5__AUD6_RXFS            0x0fc 0x410 0x000 0x3 0x0
+#define MX6QDL_PAD_DISP0_DAT5__GPIO4_IO26           0x0fc 0x410 0x000 0x5 0x0
+#define MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06    0x100 0x414 0x000 0x0 0x0
+#define MX6QDL_PAD_DISP0_DAT6__LCD_DATA06           0x100 0x414 0x000 0x1 0x0
+#define MX6QDL_PAD_DISP0_DAT6__ECSPI3_SS3           0x100 0x414 0x000 0x2 0x0
+#define MX6QDL_PAD_DISP0_DAT6__AUD6_RXC             0x100 0x414 0x000 0x3 0x0
+#define MX6QDL_PAD_DISP0_DAT6__GPIO4_IO27           0x100 0x414 0x000 0x5 0x0
+#define MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07    0x104 0x418 0x000 0x0 0x0
+#define MX6QDL_PAD_DISP0_DAT7__LCD_DATA07           0x104 0x418 0x000 0x1 0x0
+#define MX6QDL_PAD_DISP0_DAT7__ECSPI3_RDY           0x104 0x418 0x000 0x2 0x0
+#define MX6QDL_PAD_DISP0_DAT7__GPIO4_IO28           0x104 0x418 0x000 0x5 0x0
+#define MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08    0x108 0x41c 0x000 0x0 0x0
+#define MX6QDL_PAD_DISP0_DAT8__LCD_DATA08           0x108 0x41c 0x000 0x1 0x0
+#define MX6QDL_PAD_DISP0_DAT8__PWM1_OUT             0x108 0x41c 0x000 0x2 0x0
+#define MX6QDL_PAD_DISP0_DAT8__WDOG1_B              0x108 0x41c 0x000 0x3 0x0
+#define MX6QDL_PAD_DISP0_DAT8__GPIO4_IO29           0x108 0x41c 0x000 0x5 0x0
+#define MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09    0x10c 0x420 0x000 0x0 0x0
+#define MX6QDL_PAD_DISP0_DAT9__LCD_DATA09           0x10c 0x420 0x000 0x1 0x0
+#define MX6QDL_PAD_DISP0_DAT9__PWM2_OUT             0x10c 0x420 0x000 0x2 0x0
+#define MX6QDL_PAD_DISP0_DAT9__WDOG2_B              0x10c 0x420 0x000 0x3 0x0
+#define MX6QDL_PAD_DISP0_DAT9__GPIO4_IO30           0x10c 0x420 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_A16__EIM_ADDR16              0x110 0x4e0 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_A16__IPU1_DI1_DISP_CLK       0x110 0x4e0 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_A16__IPU1_CSI1_PIXCLK        0x110 0x4e0 0x8b8 0x2 0x0
+#define MX6QDL_PAD_EIM_A16__GPIO2_IO22              0x110 0x4e0 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_A16__SRC_BOOT_CFG16          0x110 0x4e0 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_A16__EPDC_DATA00             0x110 0x4e0 0x000 0x8 0x0
+#define MX6QDL_PAD_EIM_A17__EIM_ADDR17              0x114 0x4e4 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_A17__IPU1_DISP1_DATA12       0x114 0x4e4 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_A17__IPU1_CSI1_DATA12        0x114 0x4e4 0x890 0x2 0x0
+#define MX6QDL_PAD_EIM_A17__GPIO2_IO21              0x114 0x4e4 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_A17__SRC_BOOT_CFG17          0x114 0x4e4 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_A17__EPDC_PWR_STAT           0x114 0x4e4 0x000 0x8 0x0
+#define MX6QDL_PAD_EIM_A18__EIM_ADDR18              0x118 0x4e8 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_A18__IPU1_DISP1_DATA13       0x118 0x4e8 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_A18__IPU1_CSI1_DATA13        0x118 0x4e8 0x894 0x2 0x0
+#define MX6QDL_PAD_EIM_A18__GPIO2_IO20              0x118 0x4e8 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_A18__SRC_BOOT_CFG18          0x118 0x4e8 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_A18__EPDC_PWR_CTRL0          0x118 0x4e8 0x000 0x8 0x0
+#define MX6QDL_PAD_EIM_A19__EIM_ADDR19              0x11c 0x4ec 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_A19__IPU1_DISP1_DATA14       0x11c 0x4ec 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_A19__IPU1_CSI1_DATA14        0x11c 0x4ec 0x898 0x2 0x0
+#define MX6QDL_PAD_EIM_A19__GPIO2_IO19              0x11c 0x4ec 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_A19__SRC_BOOT_CFG19          0x11c 0x4ec 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_A19__EPDC_PWR_CTRL1          0x11c 0x4ec 0x000 0x8 0x0
+#define MX6QDL_PAD_EIM_A20__EIM_ADDR20              0x120 0x4f0 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_A20__IPU1_DISP1_DATA15       0x120 0x4f0 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_A20__IPU1_CSI1_DATA15        0x120 0x4f0 0x89c 0x2 0x0
+#define MX6QDL_PAD_EIM_A20__GPIO2_IO18              0x120 0x4f0 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_A20__SRC_BOOT_CFG20          0x120 0x4f0 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_A20__EPDC_PWR_CTRL2          0x120 0x4f0 0x000 0x8 0x0
+#define MX6QDL_PAD_EIM_A21__EIM_ADDR21              0x124 0x4f4 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_A21__IPU1_DISP1_DATA16       0x124 0x4f4 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_A21__IPU1_CSI1_DATA16        0x124 0x4f4 0x8a0 0x2 0x0
+#define MX6QDL_PAD_EIM_A21__GPIO2_IO17              0x124 0x4f4 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_A21__SRC_BOOT_CFG21          0x124 0x4f4 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_A21__EPDC_GDCLK              0x124 0x4f4 0x000 0x8 0x0
+#define MX6QDL_PAD_EIM_A22__EIM_ADDR22              0x128 0x4f8 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_A22__IPU1_DISP1_DATA17       0x128 0x4f8 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_A22__IPU1_CSI1_DATA17        0x128 0x4f8 0x8a4 0x2 0x0
+#define MX6QDL_PAD_EIM_A22__GPIO2_IO16              0x128 0x4f8 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_A22__SRC_BOOT_CFG22          0x128 0x4f8 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_A22__EPDC_GDSP               0x128 0x4f8 0x000 0x8 0x0
+#define MX6QDL_PAD_EIM_A23__EIM_ADDR23              0x12c 0x4fc 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_A23__IPU1_DISP1_DATA18       0x12c 0x4fc 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_A23__IPU1_CSI1_DATA18        0x12c 0x4fc 0x8a8 0x2 0x0
+#define MX6QDL_PAD_EIM_A23__IPU1_SISG3              0x12c 0x4fc 0x000 0x4 0x0
+#define MX6QDL_PAD_EIM_A23__GPIO6_IO06              0x12c 0x4fc 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_A23__SRC_BOOT_CFG23          0x12c 0x4fc 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_A23__EPDC_GDOE               0x12c 0x4fc 0x000 0x8 0x0
+#define MX6QDL_PAD_EIM_A24__EIM_ADDR24              0x130 0x500 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_A24__IPU1_DISP1_DATA19       0x130 0x500 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_A24__IPU1_CSI1_DATA19        0x130 0x500 0x8ac 0x2 0x0
+#define MX6QDL_PAD_EIM_A24__IPU1_SISG2              0x130 0x500 0x000 0x4 0x0
+#define MX6QDL_PAD_EIM_A24__GPIO5_IO04              0x130 0x500 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_A24__SRC_BOOT_CFG24          0x130 0x500 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_A24__EPDC_GDRL               0x130 0x500 0x000 0x8 0x0
+#define MX6QDL_PAD_EIM_A25__EIM_ADDR25              0x134 0x504 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_A25__ECSPI4_SS1              0x134 0x504 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_A25__ECSPI2_RDY              0x134 0x504 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_A25__IPU1_DI1_PIN12          0x134 0x504 0x000 0x3 0x0
+#define MX6QDL_PAD_EIM_A25__IPU1_DI0_D1_CS          0x134 0x504 0x000 0x4 0x0
+#define MX6QDL_PAD_EIM_A25__GPIO5_IO02              0x134 0x504 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE        0x134 0x504 0x85c 0x6 0x0
+#define MX6QDL_PAD_EIM_A25__EPDC_DATA15             0x134 0x504 0x000 0x8 0x0
+#define MX6QDL_PAD_EIM_A25__EIM_ACLK_FREERUN        0x134 0x504 0x000 0x9 0x0
+#define MX6QDL_PAD_EIM_BCLK__EIM_BCLK               0x138 0x508 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_BCLK__IPU1_DI1_PIN16         0x138 0x508 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_BCLK__GPIO6_IO31             0x138 0x508 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_BCLK__EPDC_SDCE9             0x138 0x508 0x000 0x8 0x0
+#define MX6QDL_PAD_EIM_CS0__EIM_CS0_B               0x13c 0x50c 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_CS0__IPU1_DI1_PIN05          0x13c 0x50c 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK             0x13c 0x50c 0x7f4 0x2 0x2
+#define MX6QDL_PAD_EIM_CS0__GPIO2_IO23              0x13c 0x50c 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_CS0__EPDC_DATA06             0x13c 0x50c 0x000 0x8 0x0
+#define MX6QDL_PAD_EIM_CS1__EIM_CS1_B               0x140 0x510 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_CS1__IPU1_DI1_PIN06          0x140 0x510 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI             0x140 0x510 0x7fc 0x2 0x2
+#define MX6QDL_PAD_EIM_CS1__GPIO2_IO24              0x140 0x510 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_CS1__EPDC_DATA08             0x140 0x510 0x000 0x8 0x0
+#define MX6QDL_PAD_EIM_D16__EIM_DATA16              0x144 0x514 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_D16__ECSPI1_SCLK             0x144 0x514 0x7d8 0x1 0x2
+#define MX6QDL_PAD_EIM_D16__IPU1_DI0_PIN05          0x144 0x514 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_D16__IPU1_CSI1_DATA18        0x144 0x514 0x8a8 0x3 0x1
+#define MX6QDL_PAD_EIM_D16__HDMI_TX_DDC_SDA         0x144 0x514 0x864 0x4 0x0
+#define MX6QDL_PAD_EIM_D16__GPIO3_IO16              0x144 0x514 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_D16__I2C2_SDA                0x144 0x514 0x874 0x6 0x0
+#define MX6QDL_PAD_EIM_D16__EPDC_DATA10             0x144 0x514 0x000 0x8 0x0
+#define MX6QDL_PAD_EIM_D17__EIM_DATA17              0x148 0x518 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_D17__ECSPI1_MISO             0x148 0x518 0x7dc 0x1 0x2
+#define MX6QDL_PAD_EIM_D17__IPU1_DI0_PIN06          0x148 0x518 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_D17__IPU1_CSI1_PIXCLK        0x148 0x518 0x8b8 0x3 0x1
+#define MX6QDL_PAD_EIM_D17__DCIC1_OUT               0x148 0x518 0x000 0x4 0x0
+#define MX6QDL_PAD_EIM_D17__GPIO3_IO17              0x148 0x518 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_D17__I2C3_SCL                0x148 0x518 0x878 0x6 0x0
+#define MX6QDL_PAD_EIM_D17__EPDC_VCOM0              0x148 0x518 0x000 0x8 0x0
+#define MX6QDL_PAD_EIM_D18__EIM_DATA18              0x14c 0x51c 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_D18__ECSPI1_MOSI             0x14c 0x51c 0x7e0 0x1 0x2
+#define MX6QDL_PAD_EIM_D18__IPU1_DI0_PIN07          0x14c 0x51c 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_D18__IPU1_CSI1_DATA17        0x14c 0x51c 0x8a4 0x3 0x1
+#define MX6QDL_PAD_EIM_D18__IPU1_DI1_D0_CS          0x14c 0x51c 0x000 0x4 0x0
+#define MX6QDL_PAD_EIM_D18__GPIO3_IO18              0x14c 0x51c 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_D18__I2C3_SDA                0x14c 0x51c 0x87c 0x6 0x0
+#define MX6QDL_PAD_EIM_D18__EPDC_VCOM1              0x14c 0x51c 0x000 0x8 0x0
+#define MX6QDL_PAD_EIM_D19__EIM_DATA19              0x150 0x520 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_D19__ECSPI1_SS1              0x150 0x520 0x7e8 0x1 0x1
+#define MX6QDL_PAD_EIM_D19__IPU1_DI0_PIN08          0x150 0x520 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_D19__IPU1_CSI1_DATA16        0x150 0x520 0x8a0 0x3 0x1
+#define MX6QDL_PAD_EIM_D19__UART1_CTS_B             0x150 0x520 0x000 0x4 0x0
+#define MX6QDL_PAD_EIM_D19__UART1_RTS_B             0x150 0x520 0x8f8 0x4 0x0
+#define MX6QDL_PAD_EIM_D19__GPIO3_IO19              0x150 0x520 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_D19__EPIT1_OUT               0x150 0x520 0x000 0x6 0x0
+#define MX6QDL_PAD_EIM_D19__EPDC_DATA12             0x150 0x520 0x000 0x8 0x0
+#define MX6QDL_PAD_EIM_D20__EIM_DATA20              0x154 0x524 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_D20__ECSPI4_SS0              0x154 0x524 0x808 0x1 0x0
+#define MX6QDL_PAD_EIM_D20__IPU1_DI0_PIN16          0x154 0x524 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_D20__IPU1_CSI1_DATA15        0x154 0x524 0x89c 0x3 0x1
+#define MX6QDL_PAD_EIM_D20__UART1_RTS_B             0x154 0x524 0x8f8 0x4 0x1
+#define MX6QDL_PAD_EIM_D20__UART1_CTS_B             0x154 0x524 0x000 0x4 0x0
+#define MX6QDL_PAD_EIM_D20__GPIO3_IO20              0x154 0x524 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_D20__EPIT2_OUT               0x154 0x524 0x000 0x6 0x0
+#define MX6QDL_PAD_EIM_D21__EIM_DATA21              0x158 0x528 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_D21__ECSPI4_SCLK             0x158 0x528 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_D21__IPU1_DI0_PIN17          0x158 0x528 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_D21__IPU1_CSI1_DATA11        0x158 0x528 0x88c 0x3 0x0
+#define MX6QDL_PAD_EIM_D21__USB_OTG_OC              0x158 0x528 0x920 0x4 0x0
+#define MX6QDL_PAD_EIM_D21__GPIO3_IO21              0x158 0x528 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_D21__I2C1_SCL                0x158 0x528 0x868 0x6 0x1
+#define MX6QDL_PAD_EIM_D21__SPDIF_IN                0x158 0x528 0x8f0 0x7 0x0
+#define MX6QDL_PAD_EIM_D22__EIM_DATA22              0x15c 0x52c 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_D22__ECSPI4_MISO             0x15c 0x52c 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_D22__IPU1_DI0_PIN01          0x15c 0x52c 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_D22__IPU1_CSI1_DATA10        0x15c 0x52c 0x888 0x3 0x0
+#define MX6QDL_PAD_EIM_D22__USB_OTG_PWR             0x15c 0x52c 0x000 0x4 0x0
+#define MX6QDL_PAD_EIM_D22__GPIO3_IO22              0x15c 0x52c 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_D22__SPDIF_OUT               0x15c 0x52c 0x000 0x6 0x0
+#define MX6QDL_PAD_EIM_D22__EPDC_SDCE6              0x15c 0x52c 0x000 0x8 0x0
+#define MX6QDL_PAD_EIM_D23__EIM_DATA23              0x160 0x530 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_D23__IPU1_DI0_D0_CS          0x160 0x530 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_D23__UART3_CTS_B             0x160 0x530 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_D23__UART3_RTS_B             0x160 0x530 0x908 0x2 0x0
+#define MX6QDL_PAD_EIM_D23__UART1_DCD_B             0x160 0x530 0x000 0x3 0x0
+#define MX6QDL_PAD_EIM_D23__IPU1_CSI1_DATA_EN       0x160 0x530 0x8b0 0x4 0x0
+#define MX6QDL_PAD_EIM_D23__GPIO3_IO23              0x160 0x530 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_D23__IPU1_DI1_PIN02          0x160 0x530 0x000 0x6 0x0
+#define MX6QDL_PAD_EIM_D23__IPU1_DI1_PIN14          0x160 0x530 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_D23__EPDC_DATA11             0x160 0x530 0x000 0x8 0x0
+#define MX6QDL_PAD_EIM_D24__EIM_DATA24              0x164 0x534 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_D24__ECSPI4_SS2              0x164 0x534 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_D24__UART3_TX_DATA           0x164 0x534 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_D24__UART3_RX_DATA           0x164 0x534 0x90c 0x2 0x0
+#define MX6QDL_PAD_EIM_D24__ECSPI1_SS2              0x164 0x534 0x7ec 0x3 0x0
+#define MX6QDL_PAD_EIM_D24__ECSPI2_SS2              0x164 0x534 0x000 0x4 0x0
+#define MX6QDL_PAD_EIM_D24__GPIO3_IO24              0x164 0x534 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_D24__AUD5_RXFS               0x164 0x534 0x7bc 0x6 0x1
+#define MX6QDL_PAD_EIM_D24__UART1_DTR_B             0x164 0x534 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_D24__EPDC_SDCE7              0x164 0x534 0x000 0x8 0x0
+#define MX6QDL_PAD_EIM_D25__EIM_DATA25              0x168 0x538 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_D25__ECSPI4_SS3              0x168 0x538 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_D25__UART3_RX_DATA           0x168 0x538 0x90c 0x2 0x1
+#define MX6QDL_PAD_EIM_D25__UART3_TX_DATA           0x168 0x538 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_D25__ECSPI1_SS3              0x168 0x538 0x7f0 0x3 0x0
+#define MX6QDL_PAD_EIM_D25__ECSPI2_SS3              0x168 0x538 0x000 0x4 0x0
+#define MX6QDL_PAD_EIM_D25__GPIO3_IO25              0x168 0x538 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_D25__AUD5_RXC                0x168 0x538 0x7b8 0x6 0x1
+#define MX6QDL_PAD_EIM_D25__UART1_DSR_B             0x168 0x538 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_D25__EPDC_SDCE8              0x168 0x538 0x000 0x8 0x0
+#define MX6QDL_PAD_EIM_D26__EIM_DATA26              0x16c 0x53c 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_D26__IPU1_DI1_PIN11          0x16c 0x53c 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_D26__IPU1_CSI0_DATA01        0x16c 0x53c 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_D26__IPU1_CSI1_DATA14        0x16c 0x53c 0x898 0x3 0x1
+#define MX6QDL_PAD_EIM_D26__UART2_TX_DATA           0x16c 0x53c 0x000 0x4 0x0
+#define MX6QDL_PAD_EIM_D26__UART2_RX_DATA           0x16c 0x53c 0x904 0x4 0x0
+#define MX6QDL_PAD_EIM_D26__GPIO3_IO26              0x16c 0x53c 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_D26__IPU1_SISG2              0x16c 0x53c 0x000 0x6 0x0
+#define MX6QDL_PAD_EIM_D26__IPU1_DISP1_DATA22       0x16c 0x53c 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_D26__EPDC_SDOED              0x16c 0x53c 0x000 0x8 0x0
+#define MX6QDL_PAD_EIM_D27__EIM_DATA27              0x170 0x540 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_D27__IPU1_DI1_PIN13          0x170 0x540 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_D27__IPU1_CSI0_DATA00        0x170 0x540 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_D27__IPU1_CSI1_DATA13        0x170 0x540 0x894 0x3 0x1
+#define MX6QDL_PAD_EIM_D27__UART2_RX_DATA           0x170 0x540 0x904 0x4 0x1
+#define MX6QDL_PAD_EIM_D27__UART2_TX_DATA           0x170 0x540 0x000 0x4 0x0
+#define MX6QDL_PAD_EIM_D27__GPIO3_IO27              0x170 0x540 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_D27__IPU1_SISG3              0x170 0x540 0x000 0x6 0x0
+#define MX6QDL_PAD_EIM_D27__IPU1_DISP1_DATA23       0x170 0x540 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_D27__EPDC_SDOE               0x170 0x540 0x000 0x8 0x0
+#define MX6QDL_PAD_EIM_D28__EIM_DATA28              0x174 0x544 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_D28__I2C1_SDA                0x174 0x544 0x86c 0x1 0x1
+#define MX6QDL_PAD_EIM_D28__ECSPI4_MOSI             0x174 0x544 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_D28__IPU1_CSI1_DATA12        0x174 0x544 0x890 0x3 0x1
+#define MX6QDL_PAD_EIM_D28__UART2_CTS_B             0x174 0x544 0x000 0x4 0x0
+#define MX6QDL_PAD_EIM_D28__UART2_RTS_B             0x174 0x544 0x900 0x4 0x0
+#define MX6QDL_PAD_EIM_D28__UART2_DTE_CTS_B         0x174 0x544 0x900 0x4 0x0
+#define MX6QDL_PAD_EIM_D28__UART2_DTE_RTS_B         0x174 0x544 0x000 0x4 0x0
+#define MX6QDL_PAD_EIM_D28__GPIO3_IO28              0x174 0x544 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_D28__IPU1_EXT_TRIG           0x174 0x544 0x000 0x6 0x0
+#define MX6QDL_PAD_EIM_D28__IPU1_DI0_PIN13          0x174 0x544 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_D28__EPDC_PWR_CTRL3          0x174 0x544 0x000 0x8 0x0
+#define MX6QDL_PAD_EIM_D29__EIM_DATA29              0x178 0x548 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_D29__IPU1_DI1_PIN15          0x178 0x548 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_D29__ECSPI4_SS0              0x178 0x548 0x808 0x2 0x1
+#define MX6QDL_PAD_EIM_D29__UART2_RTS_B             0x178 0x548 0x900 0x4 0x1
+#define MX6QDL_PAD_EIM_D29__UART2_CTS_B             0x178 0x548 0x000 0x4 0x0
+#define MX6QDL_PAD_EIM_D29__UART2_DTE_RTS_B         0x178 0x548 0x000 0x4 0x0
+#define MX6QDL_PAD_EIM_D29__UART2_DTE_CTS_B         0x178 0x548 0x900 0x4 0x1
+#define MX6QDL_PAD_EIM_D29__GPIO3_IO29              0x178 0x548 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_D29__IPU1_CSI1_VSYNC         0x178 0x548 0x8bc 0x6 0x0
+#define MX6QDL_PAD_EIM_D29__IPU1_DI0_PIN14          0x178 0x548 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_D29__EPDC_PWR_WAKE           0x178 0x548 0x000 0x8 0x0
+#define MX6QDL_PAD_EIM_D30__EIM_DATA30              0x17c 0x54c 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_D30__IPU1_DISP1_DATA21       0x17c 0x54c 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_D30__IPU1_DI0_PIN11          0x17c 0x54c 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_D30__IPU1_CSI0_DATA03        0x17c 0x54c 0x000 0x3 0x0
+#define MX6QDL_PAD_EIM_D30__UART3_CTS_B             0x17c 0x54c 0x000 0x4 0x0
+#define MX6QDL_PAD_EIM_D30__UART3_RTS_B             0x17c 0x54c 0x908 0x4 0x1
+#define MX6QDL_PAD_EIM_D30__GPIO3_IO30              0x17c 0x54c 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_D30__USB_H1_OC               0x17c 0x54c 0x924 0x6 0x0
+#define MX6QDL_PAD_EIM_D30__EPDC_SDOEZ              0x17c 0x54c 0x000 0x8 0x0
+#define MX6QDL_PAD_EIM_D31__EIM_DATA31              0x180 0x550 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_D31__IPU1_DISP1_DATA20       0x180 0x550 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_D31__IPU1_DI0_PIN12          0x180 0x550 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_D31__IPU1_CSI0_DATA02        0x180 0x550 0x000 0x3 0x0
+#define MX6QDL_PAD_EIM_D31__UART3_RTS_B             0x180 0x550 0x908 0x4 0x2
+#define MX6QDL_PAD_EIM_D31__UART3_CTS_B             0x180 0x550 0x000 0x4 0x0
+#define MX6QDL_PAD_EIM_D31__GPIO3_IO31              0x180 0x550 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_D31__USB_H1_PWR              0x180 0x550 0x000 0x6 0x0
+#define MX6QDL_PAD_EIM_D31__EPDC_SDCLK_P            0x180 0x550 0x000 0x8 0x0
+#define MX6QDL_PAD_EIM_D31__EIM_ACLK_FREERUN        0x180 0x550 0x000 0x9 0x0
+#define MX6QDL_PAD_EIM_DA0__EIM_AD00                0x184 0x554 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_DA0__IPU1_DISP1_DATA09       0x184 0x554 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_DA0__IPU1_CSI1_DATA09        0x184 0x554 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_DA0__GPIO3_IO00              0x184 0x554 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_DA0__SRC_BOOT_CFG00          0x184 0x554 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_DA0__EPDC_SDCLK_N            0x184 0x554 0x000 0x8 0x0
+#define MX6QDL_PAD_EIM_DA1__EIM_AD01                0x188 0x558 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_DA1__IPU1_DISP1_DATA08       0x188 0x558 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_DA1__IPU1_CSI1_DATA08        0x188 0x558 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_DA1__GPIO3_IO01              0x188 0x558 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_DA1__SRC_BOOT_CFG01          0x188 0x558 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_DA1__EPDC_SDLE               0x188 0x558 0x000 0x8 0x0
+#define MX6QDL_PAD_EIM_DA10__EIM_AD10               0x18c 0x55c 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_DA10__IPU1_DI1_PIN15         0x18c 0x55c 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_DA10__IPU1_CSI1_DATA_EN      0x18c 0x55c 0x8b0 0x2 0x1
+#define MX6QDL_PAD_EIM_DA10__GPIO3_IO10             0x18c 0x55c 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_DA10__SRC_BOOT_CFG10         0x18c 0x55c 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_DA10__EPDC_DATA01            0x18c 0x55c 0x000 0x8 0x0
+#define MX6QDL_PAD_EIM_DA11__EIM_AD11               0x190 0x560 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_DA11__IPU1_DI1_PIN02         0x190 0x560 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_DA11__IPU1_CSI1_HSYNC        0x190 0x560 0x8b4 0x2 0x0
+#define MX6QDL_PAD_EIM_DA11__GPIO3_IO11             0x190 0x560 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_DA11__SRC_BOOT_CFG11         0x190 0x560 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_DA11__EPDC_DATA03            0x190 0x560 0x000 0x8 0x0
+#define MX6QDL_PAD_EIM_DA12__EIM_AD12               0x194 0x564 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_DA12__IPU1_DI1_PIN03         0x194 0x564 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_DA12__IPU1_CSI1_VSYNC        0x194 0x564 0x8bc 0x2 0x1
+#define MX6QDL_PAD_EIM_DA12__GPIO3_IO12             0x194 0x564 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_DA12__SRC_BOOT_CFG12         0x194 0x564 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_DA12__EPDC_DATA02            0x194 0x564 0x000 0x8 0x0
+#define MX6QDL_PAD_EIM_DA13__EIM_AD13               0x198 0x568 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_DA13__IPU1_DI1_D0_CS         0x198 0x568 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_DA13__GPIO3_IO13             0x198 0x568 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_DA13__SRC_BOOT_CFG13         0x198 0x568 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_DA13__EPDC_DATA13            0x198 0x568 0x000 0x8 0x0
+#define MX6QDL_PAD_EIM_DA14__EIM_AD14               0x19c 0x56c 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_DA14__IPU1_DI1_D1_CS         0x19c 0x56c 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_DA14__GPIO3_IO14             0x19c 0x56c 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_DA14__SRC_BOOT_CFG14         0x19c 0x56c 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_DA14__EPDC_DATA14            0x19c 0x56c 0x000 0x8 0x0
+#define MX6QDL_PAD_EIM_DA15__EIM_AD15               0x1a0 0x570 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_DA15__IPU1_DI1_PIN01         0x1a0 0x570 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_DA15__IPU1_DI1_PIN04         0x1a0 0x570 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_DA15__GPIO3_IO15             0x1a0 0x570 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_DA15__SRC_BOOT_CFG15         0x1a0 0x570 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_DA15__EPDC_DATA09            0x1a0 0x570 0x000 0x8 0x0
+#define MX6QDL_PAD_EIM_DA2__EIM_AD02                0x1a4 0x574 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_DA2__IPU1_DISP1_DATA07       0x1a4 0x574 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_DA2__IPU1_CSI1_DATA07        0x1a4 0x574 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_DA2__GPIO3_IO02              0x1a4 0x574 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_DA2__SRC_BOOT_CFG02          0x1a4 0x574 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_DA2__EPDC_BDR0               0x1a4 0x574 0x000 0x8 0x0
+#define MX6QDL_PAD_EIM_DA3__EIM_AD03                0x1a8 0x578 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_DA3__IPU1_DISP1_DATA06       0x1a8 0x578 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_DA3__IPU1_CSI1_DATA06        0x1a8 0x578 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_DA3__GPIO3_IO03              0x1a8 0x578 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_DA3__SRC_BOOT_CFG03          0x1a8 0x578 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_DA3__EPDC_BDR1               0x1a8 0x578 0x000 0x8 0x0
+#define MX6QDL_PAD_EIM_DA4__EIM_AD04                0x1ac 0x57c 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_DA4__IPU1_DISP1_DATA05       0x1ac 0x57c 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_DA4__IPU1_CSI1_DATA05        0x1ac 0x57c 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_DA4__GPIO3_IO04              0x1ac 0x57c 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_DA4__SRC_BOOT_CFG04          0x1ac 0x57c 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_DA4__EPDC_SDCE0              0x1ac 0x57c 0x000 0x8 0x0
+#define MX6QDL_PAD_EIM_DA5__EIM_AD05                0x1b0 0x580 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_DA5__IPU1_DISP1_DATA04       0x1b0 0x580 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_DA5__IPU1_CSI1_DATA04        0x1b0 0x580 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_DA5__GPIO3_IO05              0x1b0 0x580 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_DA5__SRC_BOOT_CFG05          0x1b0 0x580 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_DA5__EPDC_SDCE1              0x1b0 0x580 0x000 0x8 0x0
+#define MX6QDL_PAD_EIM_DA6__EIM_AD06                0x1b4 0x584 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_DA6__IPU1_DISP1_DATA03       0x1b4 0x584 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_DA6__IPU1_CSI1_DATA03        0x1b4 0x584 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_DA6__GPIO3_IO06              0x1b4 0x584 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_DA6__SRC_BOOT_CFG06          0x1b4 0x584 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_DA6__EPDC_SDCE2              0x1b4 0x584 0x000 0x8 0x0
+#define MX6QDL_PAD_EIM_DA7__EIM_AD07                0x1b8 0x588 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_DA7__IPU1_DISP1_DATA02       0x1b8 0x588 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_DA7__IPU1_CSI1_DATA02        0x1b8 0x588 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_DA7__GPIO3_IO07              0x1b8 0x588 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_DA7__SRC_BOOT_CFG07          0x1b8 0x588 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_DA7__EPDC_SDCE3              0x1b8 0x588 0x000 0x8 0x0
+#define MX6QDL_PAD_EIM_DA8__EIM_AD08                0x1bc 0x58c 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_DA8__IPU1_DISP1_DATA01       0x1bc 0x58c 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_DA8__IPU1_CSI1_DATA01        0x1bc 0x58c 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_DA8__GPIO3_IO08              0x1bc 0x58c 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_DA8__SRC_BOOT_CFG08          0x1bc 0x58c 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_DA8__EPDC_SDCE4              0x1bc 0x58c 0x000 0x8 0x0
+#define MX6QDL_PAD_EIM_DA9__EIM_AD09                0x1c0 0x590 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_DA9__IPU1_DISP1_DATA00       0x1c0 0x590 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_DA9__IPU1_CSI1_DATA00        0x1c0 0x590 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_DA9__GPIO3_IO09              0x1c0 0x590 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_DA9__SRC_BOOT_CFG09          0x1c0 0x590 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_DA9__EPDC_SDCE5              0x1c0 0x590 0x000 0x8 0x0
+#define MX6QDL_PAD_EIM_EB0__EIM_EB0_B               0x1c4 0x594 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_EB0__IPU1_DISP1_DATA11       0x1c4 0x594 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_EB0__IPU1_CSI1_DATA11        0x1c4 0x594 0x88c 0x2 0x1
+#define MX6QDL_PAD_EIM_EB0__CCM_PMIC_READY          0x1c4 0x594 0x7d4 0x4 0x0
+#define MX6QDL_PAD_EIM_EB0__GPIO2_IO28              0x1c4 0x594 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_EB0__SRC_BOOT_CFG27          0x1c4 0x594 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_EB0__EPDC_PWR_COM            0x1c4 0x594 0x000 0x8 0x0
+#define MX6QDL_PAD_EIM_EB1__EIM_EB1_B               0x1c8 0x598 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_EB1__IPU1_DISP1_DATA10       0x1c8 0x598 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_EB1__IPU1_CSI1_DATA10        0x1c8 0x598 0x888 0x2 0x1
+#define MX6QDL_PAD_EIM_EB1__GPIO2_IO29              0x1c8 0x598 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_EB1__SRC_BOOT_CFG28          0x1c8 0x598 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_EB1__EPDC_SDSHR              0x1c8 0x598 0x000 0x8 0x0
+#define MX6QDL_PAD_EIM_EB2__EIM_EB2_B               0x1cc 0x59c 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_EB2__ECSPI1_SS0              0x1cc 0x59c 0x7e4 0x1 0x2
+#define MX6QDL_PAD_EIM_EB2__IPU1_CSI1_DATA19        0x1cc 0x59c 0x8ac 0x3 0x1
+#define MX6QDL_PAD_EIM_EB2__HDMI_TX_DDC_SCL         0x1cc 0x59c 0x860 0x4 0x0
+#define MX6QDL_PAD_EIM_EB2__GPIO2_IO30              0x1cc 0x59c 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_EB2__I2C2_SCL                0x1cc 0x59c 0x870 0x6 0x0
+#define MX6QDL_PAD_EIM_EB2__SRC_BOOT_CFG30          0x1cc 0x59c 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_EB2__EPDC_DATA05             0x1cc 0x59c 0x000 0x8 0x0
+#define MX6QDL_PAD_EIM_EB3__EIM_EB3_B               0x1d0 0x5a0 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_EB3__ECSPI4_RDY              0x1d0 0x5a0 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_EB3__UART3_RTS_B             0x1d0 0x5a0 0x908 0x2 0x3
+#define MX6QDL_PAD_EIM_EB3__UART3_CTS_B             0x1d0 0x5a0 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_EB3__UART1_RI_B              0x1d0 0x5a0 0x000 0x3 0x0
+#define MX6QDL_PAD_EIM_EB3__IPU1_CSI1_HSYNC         0x1d0 0x5a0 0x8b4 0x4 0x1
+#define MX6QDL_PAD_EIM_EB3__GPIO2_IO31              0x1d0 0x5a0 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_EB3__IPU1_DI1_PIN03          0x1d0 0x5a0 0x000 0x6 0x0
+#define MX6QDL_PAD_EIM_EB3__SRC_BOOT_CFG31          0x1d0 0x5a0 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_EB3__EPDC_SDCE0              0x1d0 0x5a0 0x000 0x8 0x0
+#define MX6QDL_PAD_EIM_EB3__EIM_ACLK_FREERUN        0x1d0 0x5a0 0x000 0x9 0x0
+#define MX6QDL_PAD_EIM_LBA__EIM_LBA_B               0x1d4 0x5a4 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_LBA__IPU1_DI1_PIN17          0x1d4 0x5a4 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_LBA__ECSPI2_SS1              0x1d4 0x5a4 0x804 0x2 0x1
+#define MX6QDL_PAD_EIM_LBA__GPIO2_IO27              0x1d4 0x5a4 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_LBA__SRC_BOOT_CFG26          0x1d4 0x5a4 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_LBA__EPDC_DATA04             0x1d4 0x5a4 0x000 0x8 0x0
+#define MX6QDL_PAD_EIM_OE__EIM_OE_B                 0x1d8 0x5a8 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_OE__IPU1_DI1_PIN07           0x1d8 0x5a8 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_OE__ECSPI2_MISO              0x1d8 0x5a8 0x7f8 0x2 0x2
+#define MX6QDL_PAD_EIM_OE__GPIO2_IO25               0x1d8 0x5a8 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_OE__EPDC_PWR_IRQ             0x1d8 0x5a8 0x000 0x8 0x0
+#define MX6QDL_PAD_EIM_RW__EIM_RW                   0x1dc 0x5ac 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_RW__IPU1_DI1_PIN08           0x1dc 0x5ac 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_RW__ECSPI2_SS0               0x1dc 0x5ac 0x800 0x2 0x2
+#define MX6QDL_PAD_EIM_RW__GPIO2_IO26               0x1dc 0x5ac 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_RW__SRC_BOOT_CFG29           0x1dc 0x5ac 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_RW__EPDC_DATA07              0x1dc 0x5ac 0x000 0x8 0x0
+#define MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B             0x1e0 0x5b0 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_WAIT__EIM_DTACK_B            0x1e0 0x5b0 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_WAIT__GPIO5_IO00             0x1e0 0x5b0 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_WAIT__SRC_BOOT_CFG25         0x1e0 0x5b0 0x000 0x7 0x0
+#define MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN          0x1e4 0x5b4 0x828 0x1 0x0
+#define MX6QDL_PAD_ENET_CRS_DV__ESAI_TX_CLK         0x1e4 0x5b4 0x840 0x2 0x0
+#define MX6QDL_PAD_ENET_CRS_DV__SPDIF_EXT_CLK       0x1e4 0x5b4 0x8f4 0x3 0x0
+#define MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25          0x1e4 0x5b4 0x000 0x5 0x0
+#define MX6QDL_PAD_ENET_MDC__MLB_DATA               0x1e8 0x5b8 0x8e0 0x0 0x0
+#define MX6QDL_PAD_ENET_MDC__ENET_MDC               0x1e8 0x5b8 0x000 0x1 0x0
+#define MX6QDL_PAD_ENET_MDC__ESAI_TX5_RX0           0x1e8 0x5b8 0x858 0x2 0x0
+#define MX6QDL_PAD_ENET_MDC__ENET_1588_EVENT1_IN    0x1e8 0x5b8 0x000 0x4 0x0
+#define MX6QDL_PAD_ENET_MDC__GPIO1_IO31             0x1e8 0x5b8 0x000 0x5 0x0
+#define MX6QDL_PAD_ENET_MDIO__ENET_MDIO             0x1ec 0x5bc 0x810 0x1 0x0
+#define MX6QDL_PAD_ENET_MDIO__ESAI_RX_CLK           0x1ec 0x5bc 0x83c 0x2 0x0
+#define MX6QDL_PAD_ENET_MDIO__ENET_1588_EVENT1_OUT  0x1ec 0x5bc 0x000 0x4 0x0
+#define MX6QDL_PAD_ENET_MDIO__GPIO1_IO22            0x1ec 0x5bc 0x000 0x5 0x0
+#define MX6QDL_PAD_ENET_MDIO__SPDIF_LOCK            0x1ec 0x5bc 0x000 0x6 0x0
+#define MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK        0x1f0 0x5c0 0x000 0x1 0x0
+#define MX6QDL_PAD_ENET_REF_CLK__ESAI_RX_FS         0x1f0 0x5c0 0x82c 0x2 0x0
+#define MX6QDL_PAD_ENET_REF_CLK__GPIO1_IO23         0x1f0 0x5c0 0x000 0x5 0x0
+#define MX6QDL_PAD_ENET_REF_CLK__SPDIF_SR_CLK       0x1f0 0x5c0 0x000 0x6 0x0
+#define MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID           0x1f4 0x5c4 0x790 0x0 0x0
+#define MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER           0x1f4 0x5c4 0x000 0x1 0x0
+#define MX6QDL_PAD_ENET_RX_ER__ESAI_RX_HF_CLK       0x1f4 0x5c4 0x834 0x2 0x0
+#define MX6QDL_PAD_ENET_RX_ER__SPDIF_IN             0x1f4 0x5c4 0x8f0 0x3 0x1
+#define MX6QDL_PAD_ENET_RX_ER__ENET_1588_EVENT2_OUT 0x1f4 0x5c4 0x000 0x4 0x0
+#define MX6QDL_PAD_ENET_RX_ER__GPIO1_IO24           0x1f4 0x5c4 0x000 0x5 0x0
+#define MX6QDL_PAD_ENET_RXD0__OSC32K_32K_OUT        0x1f8 0x5c8 0x000 0x0 0x0
+#define MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0         0x1f8 0x5c8 0x818 0x1 0x0
+#define MX6QDL_PAD_ENET_RXD0__ESAI_TX_HF_CLK        0x1f8 0x5c8 0x838 0x2 0x0
+#define MX6QDL_PAD_ENET_RXD0__SPDIF_OUT             0x1f8 0x5c8 0x000 0x3 0x0
+#define MX6QDL_PAD_ENET_RXD0__GPIO1_IO27            0x1f8 0x5c8 0x000 0x5 0x0
+#define MX6QDL_PAD_ENET_RXD1__MLB_SIG               0x1fc 0x5cc 0x8e4 0x0 0x0
+#define MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1         0x1fc 0x5cc 0x81c 0x1 0x0
+#define MX6QDL_PAD_ENET_RXD1__ESAI_TX_FS            0x1fc 0x5cc 0x830 0x2 0x0
+#define MX6QDL_PAD_ENET_RXD1__ENET_1588_EVENT3_OUT  0x1fc 0x5cc 0x000 0x4 0x0
+#define MX6QDL_PAD_ENET_RXD1__GPIO1_IO26            0x1fc 0x5cc 0x000 0x5 0x0
+#define MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN           0x200 0x5d0 0x000 0x1 0x0
+#define MX6QDL_PAD_ENET_TX_EN__ESAI_TX3_RX2         0x200 0x5d0 0x850 0x2 0x0
+#define MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28           0x200 0x5d0 0x000 0x5 0x0
+#define MX6QDL_PAD_ENET_TX_EN__I2C4_SCL             0x200 0x5d0 0x880 0x9 0x0
+#define MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0         0x204 0x5d4 0x000 0x1 0x0
+#define MX6QDL_PAD_ENET_TXD0__ESAI_TX4_RX1          0x204 0x5d4 0x854 0x2 0x0
+#define MX6QDL_PAD_ENET_TXD0__GPIO1_IO30            0x204 0x5d4 0x000 0x5 0x0
+#define MX6QDL_PAD_ENET_TXD1__MLB_CLK               0x208 0x5d8 0x8dc 0x0 0x0
+#define MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1         0x208 0x5d8 0x000 0x1 0x0
+#define MX6QDL_PAD_ENET_TXD1__ESAI_TX2_RX3          0x208 0x5d8 0x84c 0x2 0x0
+#define MX6QDL_PAD_ENET_TXD1__ENET_1588_EVENT0_IN   0x208 0x5d8 0x000 0x4 0x0
+#define MX6QDL_PAD_ENET_TXD1__GPIO1_IO29            0x208 0x5d8 0x000 0x5 0x0
+#define MX6QDL_PAD_ENET_TXD1__I2C4_SDA              0x208 0x5d8 0x884 0x9 0x0
+#define MX6QDL_PAD_GPIO_0__CCM_CLKO1                0x20c 0x5dc 0x000 0x0 0x0
+#define MX6QDL_PAD_GPIO_0__KEY_COL5                 0x20c 0x5dc 0x8c0 0x2 0x1
+#define MX6QDL_PAD_GPIO_0__ASRC_EXT_CLK             0x20c 0x5dc 0x794 0x3 0x0
+#define MX6QDL_PAD_GPIO_0__EPIT1_OUT                0x20c 0x5dc 0x000 0x4 0x0
+#define MX6QDL_PAD_GPIO_0__GPIO1_IO00               0x20c 0x5dc 0x000 0x5 0x0
+#define MX6QDL_PAD_GPIO_0__USB_H1_PWR               0x20c 0x5dc 0x000 0x6 0x0
+#define MX6QDL_PAD_GPIO_0__SNVS_VIO_5               0x20c 0x5dc 0x000 0x7 0x0
+#define MX6QDL_PAD_GPIO_1__ESAI_RX_CLK              0x210 0x5e0 0x83c 0x0 0x1
+#define MX6QDL_PAD_GPIO_1__WDOG2_B                  0x210 0x5e0 0x000 0x1 0x0
+#define MX6QDL_PAD_GPIO_1__KEY_ROW5                 0x210 0x5e0 0x8cc 0x2 0x1
+#define MX6QDL_PAD_GPIO_1__USB_OTG_ID               0x210 0x5e0 0x790 0x3 0x1
+#define MX6QDL_PAD_GPIO_1__PWM2_OUT                 0x210 0x5e0 0x000 0x4 0x0
+#define MX6QDL_PAD_GPIO_1__GPIO1_IO01               0x210 0x5e0 0x000 0x5 0x0
+#define MX6QDL_PAD_GPIO_1__SD1_CD_B                 0x210 0x5e0 0x000 0x6 0x0
+#define MX6QDL_PAD_GPIO_16__ESAI_TX3_RX2            0x214 0x5e4 0x850 0x0 0x1
+#define MX6QDL_PAD_GPIO_16__ENET_1588_EVENT2_IN     0x214 0x5e4 0x000 0x1 0x0
+#define MX6QDL_PAD_GPIO_16__ENET_REF_CLK            0x214 0x5e4 0x80c 0x2 0x0
+#define MX6QDL_PAD_GPIO_16__SD1_LCTL                0x214 0x5e4 0x000 0x3 0x0
+#define MX6QDL_PAD_GPIO_16__SPDIF_IN                0x214 0x5e4 0x8f0 0x4 0x2
+#define MX6QDL_PAD_GPIO_16__GPIO7_IO11              0x214 0x5e4 0x000 0x5 0x0
+#define MX6QDL_PAD_GPIO_16__I2C3_SDA                0x214 0x5e4 0x87c 0x6 0x1
+#define MX6QDL_PAD_GPIO_16__JTAG_DE_B               0x214 0x5e4 0x000 0x7 0x0
+#define MX6QDL_PAD_GPIO_17__ESAI_TX0                0x218 0x5e8 0x844 0x0 0x0
+#define MX6QDL_PAD_GPIO_17__ENET_1588_EVENT3_IN     0x218 0x5e8 0x000 0x1 0x0
+#define MX6QDL_PAD_GPIO_17__CCM_PMIC_READY          0x218 0x5e8 0x7d4 0x2 0x1
+#define MX6QDL_PAD_GPIO_17__SDMA_EXT_EVENT0         0x218 0x5e8 0x8e8 0x3 0x1
+#define MX6QDL_PAD_GPIO_17__SPDIF_OUT               0x218 0x5e8 0x000 0x4 0x0
+#define MX6QDL_PAD_GPIO_17__GPIO7_IO12              0x218 0x5e8 0x000 0x5 0x0
+#define MX6QDL_PAD_GPIO_18__ESAI_TX1                0x21c 0x5ec 0x848 0x0 0x0
+#define MX6QDL_PAD_GPIO_18__ENET_RX_CLK             0x21c 0x5ec 0x814 0x1 0x0
+#define MX6QDL_PAD_GPIO_18__SD3_VSELECT             0x21c 0x5ec 0x000 0x2 0x0
+#define MX6QDL_PAD_GPIO_18__SDMA_EXT_EVENT1         0x21c 0x5ec 0x8ec 0x3 0x1
+#define MX6QDL_PAD_GPIO_18__ASRC_EXT_CLK            0x21c 0x5ec 0x794 0x4 0x1
+#define MX6QDL_PAD_GPIO_18__GPIO7_IO13              0x21c 0x5ec 0x000 0x5 0x0
+#define MX6QDL_PAD_GPIO_18__SNVS_VIO_5_CTL          0x21c 0x5ec 0x000 0x6 0x0
+#define MX6QDL_PAD_GPIO_19__KEY_COL5                0x220 0x5f0 0x8c0 0x0 0x2
+#define MX6QDL_PAD_GPIO_19__ENET_1588_EVENT0_OUT    0x220 0x5f0 0x000 0x1 0x0
+#define MX6QDL_PAD_GPIO_19__SPDIF_OUT               0x220 0x5f0 0x000 0x2 0x0
+#define MX6QDL_PAD_GPIO_19__CCM_CLKO1               0x220 0x5f0 0x000 0x3 0x0
+#define MX6QDL_PAD_GPIO_19__ECSPI1_RDY              0x220 0x5f0 0x000 0x4 0x0
+#define MX6QDL_PAD_GPIO_19__GPIO4_IO05              0x220 0x5f0 0x000 0x5 0x0
+#define MX6QDL_PAD_GPIO_19__ENET_TX_ER              0x220 0x5f0 0x000 0x6 0x0
+#define MX6QDL_PAD_GPIO_2__ESAI_TX_FS               0x224 0x5f4 0x830 0x0 0x1
+#define MX6QDL_PAD_GPIO_2__KEY_ROW6                 0x224 0x5f4 0x8d0 0x2 0x1
+#define MX6QDL_PAD_GPIO_2__GPIO1_IO02               0x224 0x5f4 0x000 0x5 0x0
+#define MX6QDL_PAD_GPIO_2__SD2_WP                   0x224 0x5f4 0x000 0x6 0x0
+#define MX6QDL_PAD_GPIO_2__MLB_DATA                 0x224 0x5f4 0x8e0 0x7 0x1
+#define MX6QDL_PAD_GPIO_3__ESAI_RX_HF_CLK           0x228 0x5f8 0x834 0x0 0x1
+#define MX6QDL_PAD_GPIO_3__I2C3_SCL                 0x228 0x5f8 0x878 0x2 0x1
+#define MX6QDL_PAD_GPIO_3__XTALOSC_REF_CLK_24M      0x228 0x5f8 0x000 0x3 0x0
+#define MX6QDL_PAD_GPIO_3__CCM_CLKO2                0x228 0x5f8 0x000 0x4 0x0
+#define MX6QDL_PAD_GPIO_3__GPIO1_IO03               0x228 0x5f8 0x000 0x5 0x0
+#define MX6QDL_PAD_GPIO_3__USB_H1_OC                0x228 0x5f8 0x924 0x6 0x1
+#define MX6QDL_PAD_GPIO_3__MLB_CLK                  0x228 0x5f8 0x8dc 0x7 0x1
+#define MX6QDL_PAD_GPIO_4__ESAI_TX_HF_CLK           0x22c 0x5fc 0x838 0x0 0x1
+#define MX6QDL_PAD_GPIO_4__KEY_COL7                 0x22c 0x5fc 0x8c8 0x2 0x1
+#define MX6QDL_PAD_GPIO_4__GPIO1_IO04               0x22c 0x5fc 0x000 0x5 0x0
+#define MX6QDL_PAD_GPIO_4__SD2_CD_B                 0x22c 0x5fc 0x000 0x6 0x0
+#define MX6QDL_PAD_GPIO_5__ESAI_TX2_RX3             0x230 0x600 0x84c 0x0 0x1
+#define MX6QDL_PAD_GPIO_5__KEY_ROW7                 0x230 0x600 0x8d4 0x2 0x1
+#define MX6QDL_PAD_GPIO_5__CCM_CLKO1                0x230 0x600 0x000 0x3 0x0
+#define MX6QDL_PAD_GPIO_5__GPIO1_IO05               0x230 0x600 0x000 0x5 0x0
+#define MX6QDL_PAD_GPIO_5__I2C3_SCL                 0x230 0x600 0x878 0x6 0x2
+#define MX6QDL_PAD_GPIO_5__ARM_EVENTI               0x230 0x600 0x000 0x7 0x0
+#define MX6QDL_PAD_GPIO_6__ESAI_TX_CLK              0x234 0x604 0x840 0x0 0x1
+#define MX6QDL_PAD_GPIO_6__ENET_IRQ		    0x234 0x604 0x03c 0x11 0xff000609
+#define MX6QDL_PAD_GPIO_6__I2C3_SDA                 0x234 0x604 0x87c 0x2 0x2
+#define MX6QDL_PAD_GPIO_6__GPIO1_IO06               0x234 0x604 0x000 0x5 0x0
+#define MX6QDL_PAD_GPIO_6__SD2_LCTL                 0x234 0x604 0x000 0x6 0x0
+#define MX6QDL_PAD_GPIO_6__MLB_SIG                  0x234 0x604 0x8e4 0x7 0x1
+#define MX6QDL_PAD_GPIO_7__ESAI_TX4_RX1             0x238 0x608 0x854 0x0 0x1
+#define MX6QDL_PAD_GPIO_7__EPIT1_OUT                0x238 0x608 0x000 0x2 0x0
+#define MX6QDL_PAD_GPIO_7__FLEXCAN1_TX              0x238 0x608 0x000 0x3 0x0
+#define MX6QDL_PAD_GPIO_7__UART2_TX_DATA            0x238 0x608 0x000 0x4 0x0
+#define MX6QDL_PAD_GPIO_7__UART2_RX_DATA            0x238 0x608 0x904 0x4 0x2
+#define MX6QDL_PAD_GPIO_7__GPIO1_IO07               0x238 0x608 0x000 0x5 0x0
+#define MX6QDL_PAD_GPIO_7__SPDIF_LOCK               0x238 0x608 0x000 0x6 0x0
+#define MX6QDL_PAD_GPIO_7__USB_OTG_HOST_MODE        0x238 0x608 0x000 0x7 0x0
+#define MX6QDL_PAD_GPIO_7__I2C4_SCL                 0x238 0x608 0x880 0x8 0x1
+#define MX6QDL_PAD_GPIO_8__ESAI_TX5_RX0             0x23c 0x60c 0x858 0x0 0x1
+#define MX6QDL_PAD_GPIO_8__XTALOSC_REF_CLK_32K      0x23c 0x60c 0x000 0x1 0x0
+#define MX6QDL_PAD_GPIO_8__EPIT2_OUT                0x23c 0x60c 0x000 0x2 0x0
+#define MX6QDL_PAD_GPIO_8__FLEXCAN1_RX              0x23c 0x60c 0x7c8 0x3 0x0
+#define MX6QDL_PAD_GPIO_8__UART2_RX_DATA            0x23c 0x60c 0x904 0x4 0x3
+#define MX6QDL_PAD_GPIO_8__UART2_TX_DATA            0x23c 0x60c 0x000 0x4 0x0
+#define MX6QDL_PAD_GPIO_8__GPIO1_IO08               0x23c 0x60c 0x000 0x5 0x0
+#define MX6QDL_PAD_GPIO_8__SPDIF_SR_CLK             0x23c 0x60c 0x000 0x6 0x0
+#define MX6QDL_PAD_GPIO_8__USB_OTG_PWR_CTL_WAKE     0x23c 0x60c 0x000 0x7 0x0
+#define MX6QDL_PAD_GPIO_8__I2C4_SDA                 0x23c 0x60c 0x884 0x8 0x1
+#define MX6QDL_PAD_GPIO_9__ESAI_RX_FS               0x240 0x610 0x82c 0x0 0x1
+#define MX6QDL_PAD_GPIO_9__WDOG1_B                  0x240 0x610 0x000 0x1 0x0
+#define MX6QDL_PAD_GPIO_9__KEY_COL6                 0x240 0x610 0x8c4 0x2 0x1
+#define MX6QDL_PAD_GPIO_9__CCM_REF_EN_B             0x240 0x610 0x000 0x3 0x0
+#define MX6QDL_PAD_GPIO_9__PWM1_OUT                 0x240 0x610 0x000 0x4 0x0
+#define MX6QDL_PAD_GPIO_9__GPIO1_IO09               0x240 0x610 0x000 0x5 0x0
+#define MX6QDL_PAD_GPIO_9__SD1_WP                   0x240 0x610 0x92c 0x6 0x1
+#define MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK            0x244 0x62c 0x7d8 0x0 0x3
+#define MX6QDL_PAD_KEY_COL0__ENET_RX_DATA3          0x244 0x62c 0x824 0x1 0x0
+#define MX6QDL_PAD_KEY_COL0__AUD5_TXC               0x244 0x62c 0x7c0 0x2 0x1
+#define MX6QDL_PAD_KEY_COL0__KEY_COL0               0x244 0x62c 0x000 0x3 0x0
+#define MX6QDL_PAD_KEY_COL0__UART4_TX_DATA          0x244 0x62c 0x000 0x4 0x0
+#define MX6QDL_PAD_KEY_COL0__UART4_RX_DATA          0x244 0x62c 0x914 0x4 0x2
+#define MX6QDL_PAD_KEY_COL0__GPIO4_IO06             0x244 0x62c 0x000 0x5 0x0
+#define MX6QDL_PAD_KEY_COL0__DCIC1_OUT              0x244 0x62c 0x000 0x6 0x0
+#define MX6QDL_PAD_KEY_COL1__ECSPI1_MISO            0x248 0x630 0x7dc 0x0 0x3
+#define MX6QDL_PAD_KEY_COL1__ENET_MDIO              0x248 0x630 0x810 0x1 0x1
+#define MX6QDL_PAD_KEY_COL1__AUD5_TXFS              0x248 0x630 0x7c4 0x2 0x1
+#define MX6QDL_PAD_KEY_COL1__KEY_COL1               0x248 0x630 0x000 0x3 0x0
+#define MX6QDL_PAD_KEY_COL1__UART5_TX_DATA          0x248 0x630 0x000 0x4 0x0
+#define MX6QDL_PAD_KEY_COL1__UART5_RX_DATA          0x248 0x630 0x91c 0x4 0x2
+#define MX6QDL_PAD_KEY_COL1__GPIO4_IO08             0x248 0x630 0x000 0x5 0x0
+#define MX6QDL_PAD_KEY_COL1__SD1_VSELECT            0x248 0x630 0x000 0x6 0x0
+#define MX6QDL_PAD_KEY_COL2__ECSPI1_SS1             0x24c 0x634 0x7e8 0x0 0x2
+#define MX6QDL_PAD_KEY_COL2__ENET_RX_DATA2          0x24c 0x634 0x820 0x1 0x0
+#define MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX            0x24c 0x634 0x000 0x2 0x0
+#define MX6QDL_PAD_KEY_COL2__KEY_COL2               0x24c 0x634 0x000 0x3 0x0
+#define MX6QDL_PAD_KEY_COL2__ENET_MDC               0x24c 0x634 0x000 0x4 0x0
+#define MX6QDL_PAD_KEY_COL2__GPIO4_IO10             0x24c 0x634 0x000 0x5 0x0
+#define MX6QDL_PAD_KEY_COL2__USB_H1_PWR_CTL_WAKE    0x24c 0x634 0x000 0x6 0x0
+#define MX6QDL_PAD_KEY_COL3__ECSPI1_SS3             0x250 0x638 0x7f0 0x0 0x1
+#define MX6QDL_PAD_KEY_COL3__ENET_CRS               0x250 0x638 0x000 0x1 0x0
+#define MX6QDL_PAD_KEY_COL3__HDMI_TX_DDC_SCL        0x250 0x638 0x860 0x2 0x1
+#define MX6QDL_PAD_KEY_COL3__KEY_COL3               0x250 0x638 0x000 0x3 0x0
+#define MX6QDL_PAD_KEY_COL3__I2C2_SCL               0x250 0x638 0x870 0x4 0x1
+#define MX6QDL_PAD_KEY_COL3__GPIO4_IO12             0x250 0x638 0x000 0x5 0x0
+#define MX6QDL_PAD_KEY_COL3__SPDIF_IN               0x250 0x638 0x8f0 0x6 0x3
+#define MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX            0x254 0x63c 0x000 0x0 0x0
+#define MX6QDL_PAD_KEY_COL4__IPU1_SISG4             0x254 0x63c 0x000 0x1 0x0
+#define MX6QDL_PAD_KEY_COL4__USB_OTG_OC             0x254 0x63c 0x920 0x2 0x1
+#define MX6QDL_PAD_KEY_COL4__KEY_COL4               0x254 0x63c 0x000 0x3 0x0
+#define MX6QDL_PAD_KEY_COL4__UART5_RTS_B            0x254 0x63c 0x918 0x4 0x2
+#define MX6QDL_PAD_KEY_COL4__UART5_CTS_B            0x254 0x63c 0x000 0x4 0x0
+#define MX6QDL_PAD_KEY_COL4__GPIO4_IO14             0x254 0x63c 0x000 0x5 0x0
+#define MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI            0x258 0x640 0x7e0 0x0 0x3
+#define MX6QDL_PAD_KEY_ROW0__ENET_TX_DATA3          0x258 0x640 0x000 0x1 0x0
+#define MX6QDL_PAD_KEY_ROW0__AUD5_TXD               0x258 0x640 0x7b4 0x2 0x1
+#define MX6QDL_PAD_KEY_ROW0__KEY_ROW0               0x258 0x640 0x000 0x3 0x0
+#define MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA          0x258 0x640 0x914 0x4 0x3
+#define MX6QDL_PAD_KEY_ROW0__UART4_TX_DATA          0x258 0x640 0x000 0x4 0x0
+#define MX6QDL_PAD_KEY_ROW0__GPIO4_IO07             0x258 0x640 0x000 0x5 0x0
+#define MX6QDL_PAD_KEY_ROW0__DCIC2_OUT              0x258 0x640 0x000 0x6 0x0
+#define MX6QDL_PAD_KEY_ROW1__ECSPI1_SS0             0x25c 0x644 0x7e4 0x0 0x3
+#define MX6QDL_PAD_KEY_ROW1__ENET_COL               0x25c 0x644 0x000 0x1 0x0
+#define MX6QDL_PAD_KEY_ROW1__AUD5_RXD               0x25c 0x644 0x7b0 0x2 0x1
+#define MX6QDL_PAD_KEY_ROW1__KEY_ROW1               0x25c 0x644 0x000 0x3 0x0
+#define MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA          0x25c 0x644 0x91c 0x4 0x3
+#define MX6QDL_PAD_KEY_ROW1__UART5_TX_DATA          0x25c 0x644 0x000 0x4 0x0
+#define MX6QDL_PAD_KEY_ROW1__GPIO4_IO09             0x25c 0x644 0x000 0x5 0x0
+#define MX6QDL_PAD_KEY_ROW1__SD2_VSELECT            0x25c 0x644 0x000 0x6 0x0
+#define MX6QDL_PAD_KEY_ROW2__ECSPI1_SS2             0x260 0x648 0x7ec 0x0 0x1
+#define MX6QDL_PAD_KEY_ROW2__ENET_TX_DATA2          0x260 0x648 0x000 0x1 0x0
+#define MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX            0x260 0x648 0x7c8 0x2 0x1
+#define MX6QDL_PAD_KEY_ROW2__KEY_ROW2               0x260 0x648 0x000 0x3 0x0
+#define MX6QDL_PAD_KEY_ROW2__SD2_VSELECT            0x260 0x648 0x000 0x4 0x0
+#define MX6QDL_PAD_KEY_ROW2__GPIO4_IO11             0x260 0x648 0x000 0x5 0x0
+#define MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE       0x260 0x648 0x85c 0x6 0x1
+#define MX6QDL_PAD_KEY_ROW3__ASRC_EXT_CLK           0x264 0x64c 0x794 0x1 0x2
+#define MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA        0x264 0x64c 0x864 0x2 0x1
+#define MX6QDL_PAD_KEY_ROW3__KEY_ROW3               0x264 0x64c 0x000 0x3 0x0
+#define MX6QDL_PAD_KEY_ROW3__I2C2_SDA               0x264 0x64c 0x874 0x4 0x1
+#define MX6QDL_PAD_KEY_ROW3__GPIO4_IO13             0x264 0x64c 0x000 0x5 0x0
+#define MX6QDL_PAD_KEY_ROW3__SD1_VSELECT            0x264 0x64c 0x000 0x6 0x0
+#define MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX            0x268 0x650 0x7cc 0x0 0x0
+#define MX6QDL_PAD_KEY_ROW4__IPU1_SISG5             0x268 0x650 0x000 0x1 0x0
+#define MX6QDL_PAD_KEY_ROW4__USB_OTG_PWR            0x268 0x650 0x000 0x2 0x0
+#define MX6QDL_PAD_KEY_ROW4__KEY_ROW4               0x268 0x650 0x000 0x3 0x0
+#define MX6QDL_PAD_KEY_ROW4__UART5_CTS_B            0x268 0x650 0x000 0x4 0x0
+#define MX6QDL_PAD_KEY_ROW4__UART5_RTS_B            0x268 0x650 0x918 0x4 0x3
+#define MX6QDL_PAD_KEY_ROW4__GPIO4_IO15             0x268 0x650 0x000 0x5 0x0
+#define MX6QDL_PAD_NANDF_ALE__NAND_ALE              0x26c 0x654 0x000 0x0 0x0
+#define MX6QDL_PAD_NANDF_ALE__SD4_RESET             0x26c 0x654 0x000 0x1 0x0
+#define MX6QDL_PAD_NANDF_ALE__GPIO6_IO08            0x26c 0x654 0x000 0x5 0x0
+#define MX6QDL_PAD_NANDF_CLE__NAND_CLE              0x270 0x658 0x000 0x0 0x0
+#define MX6QDL_PAD_NANDF_CLE__GPIO6_IO07            0x270 0x658 0x000 0x5 0x0
+#define MX6QDL_PAD_NANDF_CS0__NAND_CE0_B            0x274 0x65c 0x000 0x0 0x0
+#define MX6QDL_PAD_NANDF_CS0__GPIO6_IO11            0x274 0x65c 0x000 0x5 0x0
+#define MX6QDL_PAD_NANDF_CS1__NAND_CE1_B            0x278 0x660 0x000 0x0 0x0
+#define MX6QDL_PAD_NANDF_CS1__SD4_VSELECT           0x278 0x660 0x000 0x1 0x0
+#define MX6QDL_PAD_NANDF_CS1__SD3_VSELECT           0x278 0x660 0x000 0x2 0x0
+#define MX6QDL_PAD_NANDF_CS1__GPIO6_IO14            0x278 0x660 0x000 0x5 0x0
+#define MX6QDL_PAD_NANDF_CS2__NAND_CE2_B            0x27c 0x664 0x000 0x0 0x0
+#define MX6QDL_PAD_NANDF_CS2__IPU1_SISG0            0x27c 0x664 0x000 0x1 0x0
+#define MX6QDL_PAD_NANDF_CS2__ESAI_TX0              0x27c 0x664 0x844 0x2 0x1
+#define MX6QDL_PAD_NANDF_CS2__EIM_CRE               0x27c 0x664 0x000 0x3 0x0
+#define MX6QDL_PAD_NANDF_CS2__CCM_CLKO2             0x27c 0x664 0x000 0x4 0x0
+#define MX6QDL_PAD_NANDF_CS2__GPIO6_IO15            0x27c 0x664 0x000 0x5 0x0
+#define MX6QDL_PAD_NANDF_CS3__NAND_CE3_B            0x280 0x668 0x000 0x0 0x0
+#define MX6QDL_PAD_NANDF_CS3__IPU1_SISG1            0x280 0x668 0x000 0x1 0x0
+#define MX6QDL_PAD_NANDF_CS3__ESAI_TX1              0x280 0x668 0x848 0x2 0x1
+#define MX6QDL_PAD_NANDF_CS3__EIM_ADDR26            0x280 0x668 0x000 0x3 0x0
+#define MX6QDL_PAD_NANDF_CS3__GPIO6_IO16            0x280 0x668 0x000 0x5 0x0
+#define MX6QDL_PAD_NANDF_CS3__I2C4_SDA              0x280 0x668 0x884 0x9 0x2
+#define MX6QDL_PAD_NANDF_D0__NAND_DATA00            0x284 0x66c 0x000 0x0 0x0
+#define MX6QDL_PAD_NANDF_D0__SD1_DATA4              0x284 0x66c 0x000 0x1 0x0
+#define MX6QDL_PAD_NANDF_D0__GPIO2_IO00             0x284 0x66c 0x000 0x5 0x0
+#define MX6QDL_PAD_NANDF_D1__NAND_DATA01            0x288 0x670 0x000 0x0 0x0
+#define MX6QDL_PAD_NANDF_D1__SD1_DATA5              0x288 0x670 0x000 0x1 0x0
+#define MX6QDL_PAD_NANDF_D1__GPIO2_IO01             0x288 0x670 0x000 0x5 0x0
+#define MX6QDL_PAD_NANDF_D2__NAND_DATA02            0x28c 0x674 0x000 0x0 0x0
+#define MX6QDL_PAD_NANDF_D2__SD1_DATA6              0x28c 0x674 0x000 0x1 0x0
+#define MX6QDL_PAD_NANDF_D2__GPIO2_IO02             0x28c 0x674 0x000 0x5 0x0
+#define MX6QDL_PAD_NANDF_D3__NAND_DATA03            0x290 0x678 0x000 0x0 0x0
+#define MX6QDL_PAD_NANDF_D3__SD1_DATA7              0x290 0x678 0x000 0x1 0x0
+#define MX6QDL_PAD_NANDF_D3__GPIO2_IO03             0x290 0x678 0x000 0x5 0x0
+#define MX6QDL_PAD_NANDF_D4__NAND_DATA04            0x294 0x67c 0x000 0x0 0x0
+#define MX6QDL_PAD_NANDF_D4__SD2_DATA4              0x294 0x67c 0x000 0x1 0x0
+#define MX6QDL_PAD_NANDF_D4__GPIO2_IO04             0x294 0x67c 0x000 0x5 0x0
+#define MX6QDL_PAD_NANDF_D5__NAND_DATA05            0x298 0x680 0x000 0x0 0x0
+#define MX6QDL_PAD_NANDF_D5__SD2_DATA5              0x298 0x680 0x000 0x1 0x0
+#define MX6QDL_PAD_NANDF_D5__GPIO2_IO05             0x298 0x680 0x000 0x5 0x0
+#define MX6QDL_PAD_NANDF_D6__NAND_DATA06            0x29c 0x684 0x000 0x0 0x0
+#define MX6QDL_PAD_NANDF_D6__SD2_DATA6              0x29c 0x684 0x000 0x1 0x0
+#define MX6QDL_PAD_NANDF_D6__GPIO2_IO06             0x29c 0x684 0x000 0x5 0x0
+#define MX6QDL_PAD_NANDF_D7__NAND_DATA07            0x2a0 0x688 0x000 0x0 0x0
+#define MX6QDL_PAD_NANDF_D7__SD2_DATA7              0x2a0 0x688 0x000 0x1 0x0
+#define MX6QDL_PAD_NANDF_D7__GPIO2_IO07             0x2a0 0x688 0x000 0x5 0x0
+#define MX6QDL_PAD_NANDF_RB0__NAND_READY_B          0x2a4 0x68c 0x000 0x0 0x0
+#define MX6QDL_PAD_NANDF_RB0__GPIO6_IO10            0x2a4 0x68c 0x000 0x5 0x0
+#define MX6QDL_PAD_NANDF_WP_B__NAND_WP_B            0x2a8 0x690 0x000 0x0 0x0
+#define MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09           0x2a8 0x690 0x000 0x5 0x0
+#define MX6QDL_PAD_NANDF_WP_B__I2C4_SCL             0x2a8 0x690 0x880 0x9 0x2
+#define MX6QDL_PAD_RGMII_RD0__HSI_RX_READY          0x2ac 0x694 0x000 0x0 0x0
+#define MX6QDL_PAD_RGMII_RD0__RGMII_RD0             0x2ac 0x694 0x818 0x1 0x1
+#define MX6QDL_PAD_RGMII_RD0__GPIO6_IO25            0x2ac 0x694 0x000 0x5 0x0
+#define MX6QDL_PAD_RGMII_RD1__HSI_TX_FLAG           0x2b0 0x698 0x000 0x0 0x0
+#define MX6QDL_PAD_RGMII_RD1__RGMII_RD1             0x2b0 0x698 0x81c 0x1 0x1
+#define MX6QDL_PAD_RGMII_RD1__GPIO6_IO27            0x2b0 0x698 0x000 0x5 0x0
+#define MX6QDL_PAD_RGMII_RD2__HSI_TX_DATA           0x2b4 0x69c 0x000 0x0 0x0
+#define MX6QDL_PAD_RGMII_RD2__RGMII_RD2             0x2b4 0x69c 0x820 0x1 0x1
+#define MX6QDL_PAD_RGMII_RD2__GPIO6_IO28            0x2b4 0x69c 0x000 0x5 0x0
+#define MX6QDL_PAD_RGMII_RD3__HSI_TX_WAKE           0x2b8 0x6a0 0x000 0x0 0x0
+#define MX6QDL_PAD_RGMII_RD3__RGMII_RD3             0x2b8 0x6a0 0x824 0x1 0x1
+#define MX6QDL_PAD_RGMII_RD3__GPIO6_IO29            0x2b8 0x6a0 0x000 0x5 0x0
+#define MX6QDL_PAD_RGMII_RX_CTL__USB_H3_DATA        0x2bc 0x6a4 0x000 0x0 0x0
+#define MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL       0x2bc 0x6a4 0x828 0x1 0x1
+#define MX6QDL_PAD_RGMII_RX_CTL__GPIO6_IO24         0x2bc 0x6a4 0x000 0x5 0x0
+#define MX6QDL_PAD_RGMII_RXC__USB_H3_STROBE         0x2c0 0x6a8 0x000 0x0 0x0
+#define MX6QDL_PAD_RGMII_RXC__RGMII_RXC             0x2c0 0x6a8 0x814 0x1 0x1
+#define MX6QDL_PAD_RGMII_RXC__GPIO6_IO30            0x2c0 0x6a8 0x000 0x5 0x0
+#define MX6QDL_PAD_RGMII_TD0__HSI_TX_READY          0x2c4 0x6ac 0x000 0x0 0x0
+#define MX6QDL_PAD_RGMII_TD0__RGMII_TD0             0x2c4 0x6ac 0x000 0x1 0x0
+#define MX6QDL_PAD_RGMII_TD0__GPIO6_IO20            0x2c4 0x6ac 0x000 0x5 0x0
+#define MX6QDL_PAD_RGMII_TD1__HSI_RX_FLAG           0x2c8 0x6b0 0x000 0x0 0x0
+#define MX6QDL_PAD_RGMII_TD1__RGMII_TD1             0x2c8 0x6b0 0x000 0x1 0x0
+#define MX6QDL_PAD_RGMII_TD1__GPIO6_IO21            0x2c8 0x6b0 0x000 0x5 0x0
+#define MX6QDL_PAD_RGMII_TD2__HSI_RX_DATA           0x2cc 0x6b4 0x000 0x0 0x0
+#define MX6QDL_PAD_RGMII_TD2__RGMII_TD2             0x2cc 0x6b4 0x000 0x1 0x0
+#define MX6QDL_PAD_RGMII_TD2__GPIO6_IO22            0x2cc 0x6b4 0x000 0x5 0x0
+#define MX6QDL_PAD_RGMII_TD3__HSI_RX_WAKE           0x2d0 0x6b8 0x000 0x0 0x0
+#define MX6QDL_PAD_RGMII_TD3__RGMII_TD3             0x2d0 0x6b8 0x000 0x1 0x0
+#define MX6QDL_PAD_RGMII_TD3__GPIO6_IO23            0x2d0 0x6b8 0x000 0x5 0x0
+#define MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE      0x2d4 0x6bc 0x000 0x0 0x0
+#define MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL       0x2d4 0x6bc 0x000 0x1 0x0
+#define MX6QDL_PAD_RGMII_TX_CTL__GPIO6_IO26         0x2d4 0x6bc 0x000 0x5 0x0
+#define MX6QDL_PAD_RGMII_TX_CTL__ENET_REF_CLK       0x2d4 0x6bc 0x80c 0x7 0x1
+#define MX6QDL_PAD_RGMII_TXC__USB_H2_DATA           0x2d8 0x6c0 0x000 0x0 0x0
+#define MX6QDL_PAD_RGMII_TXC__RGMII_TXC             0x2d8 0x6c0 0x000 0x1 0x0
+#define MX6QDL_PAD_RGMII_TXC__SPDIF_EXT_CLK         0x2d8 0x6c0 0x8f4 0x2 0x1
+#define MX6QDL_PAD_RGMII_TXC__GPIO6_IO19            0x2d8 0x6c0 0x000 0x5 0x0
+#define MX6QDL_PAD_RGMII_TXC__XTALOSC_REF_CLK_24M   0x2d8 0x6c0 0x000 0x7 0x0
+#define MX6QDL_PAD_SD1_CLK__SD1_CLK                 0x2dc 0x6c4 0x928 0x0 0x1
+#define MX6QDL_PAD_SD1_CLK__OSC32K_32K_OUT          0x2dc 0x6c4 0x000 0x2 0x0
+#define MX6QDL_PAD_SD1_CLK__GPT_CLKIN               0x2dc 0x6c4 0x000 0x3 0x0
+#define MX6QDL_PAD_SD1_CLK__GPIO1_IO20              0x2dc 0x6c4 0x000 0x5 0x0
+#define MX6QDL_PAD_SD1_CMD__SD1_CMD                 0x2e0 0x6c8 0x000 0x0 0x0
+#define MX6QDL_PAD_SD1_CMD__PWM4_OUT                0x2e0 0x6c8 0x000 0x2 0x0
+#define MX6QDL_PAD_SD1_CMD__GPT_COMPARE1            0x2e0 0x6c8 0x000 0x3 0x0
+#define MX6QDL_PAD_SD1_CMD__GPIO1_IO18              0x2e0 0x6c8 0x000 0x5 0x0
+#define MX6QDL_PAD_SD1_DAT0__SD1_DATA0              0x2e4 0x6cc 0x000 0x0 0x0
+#define MX6QDL_PAD_SD1_DAT0__GPT_CAPTURE1           0x2e4 0x6cc 0x000 0x3 0x0
+#define MX6QDL_PAD_SD1_DAT0__GPIO1_IO16             0x2e4 0x6cc 0x000 0x5 0x0
+#define MX6QDL_PAD_SD1_DAT1__SD1_DATA1              0x2e8 0x6d0 0x000 0x0 0x0
+#define MX6QDL_PAD_SD1_DAT1__PWM3_OUT               0x2e8 0x6d0 0x000 0x2 0x0
+#define MX6QDL_PAD_SD1_DAT1__GPT_CAPTURE2           0x2e8 0x6d0 0x000 0x3 0x0
+#define MX6QDL_PAD_SD1_DAT1__GPIO1_IO17             0x2e8 0x6d0 0x000 0x5 0x0
+#define MX6QDL_PAD_SD1_DAT2__SD1_DATA2              0x2ec 0x6d4 0x000 0x0 0x0
+#define MX6QDL_PAD_SD1_DAT2__GPT_COMPARE2           0x2ec 0x6d4 0x000 0x2 0x0
+#define MX6QDL_PAD_SD1_DAT2__PWM2_OUT               0x2ec 0x6d4 0x000 0x3 0x0
+#define MX6QDL_PAD_SD1_DAT2__WDOG1_B                0x2ec 0x6d4 0x000 0x4 0x0
+#define MX6QDL_PAD_SD1_DAT2__GPIO1_IO19             0x2ec 0x6d4 0x000 0x5 0x0
+#define MX6QDL_PAD_SD1_DAT2__WDOG1_RESET_B_DEB      0x2ec 0x6d4 0x000 0x6 0x0
+#define MX6QDL_PAD_SD1_DAT3__SD1_DATA3              0x2f0 0x6d8 0x000 0x0 0x0
+#define MX6QDL_PAD_SD1_DAT3__GPT_COMPARE3           0x2f0 0x6d8 0x000 0x2 0x0
+#define MX6QDL_PAD_SD1_DAT3__PWM1_OUT               0x2f0 0x6d8 0x000 0x3 0x0
+#define MX6QDL_PAD_SD1_DAT3__WDOG2_B                0x2f0 0x6d8 0x000 0x4 0x0
+#define MX6QDL_PAD_SD1_DAT3__GPIO1_IO21             0x2f0 0x6d8 0x000 0x5 0x0
+#define MX6QDL_PAD_SD1_DAT3__WDOG2_RESET_B_DEB      0x2f0 0x6d8 0x000 0x6 0x0
+#define MX6QDL_PAD_SD2_CLK__SD2_CLK                 0x2f4 0x6dc 0x930 0x0 0x1
+#define MX6QDL_PAD_SD2_CLK__KEY_COL5                0x2f4 0x6dc 0x8c0 0x2 0x3
+#define MX6QDL_PAD_SD2_CLK__AUD4_RXFS               0x2f4 0x6dc 0x7a4 0x3 0x1
+#define MX6QDL_PAD_SD2_CLK__GPIO1_IO10              0x2f4 0x6dc 0x000 0x5 0x0
+#define MX6QDL_PAD_SD2_CMD__SD2_CMD                 0x2f8 0x6e0 0x000 0x0 0x0
+#define MX6QDL_PAD_SD2_CMD__KEY_ROW5                0x2f8 0x6e0 0x8cc 0x2 0x2
+#define MX6QDL_PAD_SD2_CMD__AUD4_RXC                0x2f8 0x6e0 0x7a0 0x3 0x1
+#define MX6QDL_PAD_SD2_CMD__GPIO1_IO11              0x2f8 0x6e0 0x000 0x5 0x0
+#define MX6QDL_PAD_SD2_DAT0__SD2_DATA0              0x2fc 0x6e4 0x000 0x0 0x0
+#define MX6QDL_PAD_SD2_DAT0__AUD4_RXD               0x2fc 0x6e4 0x798 0x3 0x1
+#define MX6QDL_PAD_SD2_DAT0__KEY_ROW7               0x2fc 0x6e4 0x8d4 0x4 0x2
+#define MX6QDL_PAD_SD2_DAT0__GPIO1_IO15             0x2fc 0x6e4 0x000 0x5 0x0
+#define MX6QDL_PAD_SD2_DAT0__DCIC2_OUT              0x2fc 0x6e4 0x000 0x6 0x0
+#define MX6QDL_PAD_SD2_DAT1__SD2_DATA1              0x300 0x6e8 0x000 0x0 0x0
+#define MX6QDL_PAD_SD2_DAT1__EIM_CS2_B              0x300 0x6e8 0x000 0x2 0x0
+#define MX6QDL_PAD_SD2_DAT1__AUD4_TXFS              0x300 0x6e8 0x7ac 0x3 0x1
+#define MX6QDL_PAD_SD2_DAT1__KEY_COL7               0x300 0x6e8 0x8c8 0x4 0x2
+#define MX6QDL_PAD_SD2_DAT1__GPIO1_IO14             0x300 0x6e8 0x000 0x5 0x0
+#define MX6QDL_PAD_SD2_DAT2__SD2_DATA2              0x304 0x6ec 0x000 0x0 0x0
+#define MX6QDL_PAD_SD2_DAT2__EIM_CS3_B              0x304 0x6ec 0x000 0x2 0x0
+#define MX6QDL_PAD_SD2_DAT2__AUD4_TXD               0x304 0x6ec 0x79c 0x3 0x1
+#define MX6QDL_PAD_SD2_DAT2__KEY_ROW6               0x304 0x6ec 0x8d0 0x4 0x2
+#define MX6QDL_PAD_SD2_DAT2__GPIO1_IO13             0x304 0x6ec 0x000 0x5 0x0
+#define MX6QDL_PAD_SD2_DAT3__SD2_DATA3              0x308 0x6f0 0x000 0x0 0x0
+#define MX6QDL_PAD_SD2_DAT3__KEY_COL6               0x308 0x6f0 0x8c4 0x2 0x2
+#define MX6QDL_PAD_SD2_DAT3__AUD4_TXC               0x308 0x6f0 0x7a8 0x3 0x1
+#define MX6QDL_PAD_SD2_DAT3__GPIO1_IO12             0x308 0x6f0 0x000 0x5 0x0
+#define MX6QDL_PAD_SD3_CLK__SD3_CLK                 0x30c 0x6f4 0x934 0x0 0x1
+#define MX6QDL_PAD_SD3_CLK__UART2_RTS_B             0x30c 0x6f4 0x900 0x1 0x2
+#define MX6QDL_PAD_SD3_CLK__UART2_CTS_B             0x30c 0x6f4 0x000 0x1 0x0
+#define MX6QDL_PAD_SD3_CLK__FLEXCAN1_RX             0x30c 0x6f4 0x7c8 0x2 0x2
+#define MX6QDL_PAD_SD3_CLK__GPIO7_IO03              0x30c 0x6f4 0x000 0x5 0x0
+#define MX6QDL_PAD_SD3_CMD__SD3_CMD                 0x310 0x6f8 0x000 0x0 0x0
+#define MX6QDL_PAD_SD3_CMD__UART2_CTS_B             0x310 0x6f8 0x000 0x1 0x0
+#define MX6QDL_PAD_SD3_CMD__UART2_RTS_B             0x310 0x6f8 0x900 0x1 0x3
+#define MX6QDL_PAD_SD3_CMD__FLEXCAN1_TX             0x310 0x6f8 0x000 0x2 0x0
+#define MX6QDL_PAD_SD3_CMD__GPIO7_IO02              0x310 0x6f8 0x000 0x5 0x0
+#define MX6QDL_PAD_SD3_DAT0__SD3_DATA0              0x314 0x6fc 0x000 0x0 0x0
+#define MX6QDL_PAD_SD3_DAT0__UART1_CTS_B            0x314 0x6fc 0x000 0x1 0x0
+#define MX6QDL_PAD_SD3_DAT0__UART1_RTS_B            0x314 0x6fc 0x8f8 0x1 0x2
+#define MX6QDL_PAD_SD3_DAT0__FLEXCAN2_TX            0x314 0x6fc 0x000 0x2 0x0
+#define MX6QDL_PAD_SD3_DAT0__GPIO7_IO04             0x314 0x6fc 0x000 0x5 0x0
+#define MX6QDL_PAD_SD3_DAT1__SD3_DATA1              0x318 0x700 0x000 0x0 0x0
+#define MX6QDL_PAD_SD3_DAT1__UART1_RTS_B            0x318 0x700 0x8f8 0x1 0x3
+#define MX6QDL_PAD_SD3_DAT1__UART1_CTS_B            0x318 0x700 0x000 0x1 0x0
+#define MX6QDL_PAD_SD3_DAT1__FLEXCAN2_RX            0x318 0x700 0x7cc 0x2 0x1
+#define MX6QDL_PAD_SD3_DAT1__GPIO7_IO05             0x318 0x700 0x000 0x5 0x0
+#define MX6QDL_PAD_SD3_DAT2__SD3_DATA2              0x31c 0x704 0x000 0x0 0x0
+#define MX6QDL_PAD_SD3_DAT2__GPIO7_IO06             0x31c 0x704 0x000 0x5 0x0
+#define MX6QDL_PAD_SD3_DAT3__SD3_DATA3              0x320 0x708 0x000 0x0 0x0
+#define MX6QDL_PAD_SD3_DAT3__UART3_CTS_B            0x320 0x708 0x000 0x1 0x0
+#define MX6QDL_PAD_SD3_DAT3__UART3_RTS_B            0x320 0x708 0x908 0x1 0x4
+#define MX6QDL_PAD_SD3_DAT3__GPIO7_IO07             0x320 0x708 0x000 0x5 0x0
+#define MX6QDL_PAD_SD3_DAT4__SD3_DATA4              0x324 0x70c 0x000 0x0 0x0
+#define MX6QDL_PAD_SD3_DAT4__UART2_RX_DATA          0x324 0x70c 0x904 0x1 0x4
+#define MX6QDL_PAD_SD3_DAT4__UART2_TX_DATA          0x324 0x70c 0x000 0x1 0x0
+#define MX6QDL_PAD_SD3_DAT4__GPIO7_IO01             0x324 0x70c 0x000 0x5 0x0
+#define MX6QDL_PAD_SD3_DAT5__SD3_DATA5              0x328 0x710 0x000 0x0 0x0
+#define MX6QDL_PAD_SD3_DAT5__UART2_TX_DATA          0x328 0x710 0x000 0x1 0x0
+#define MX6QDL_PAD_SD3_DAT5__UART2_RX_DATA          0x328 0x710 0x904 0x1 0x5
+#define MX6QDL_PAD_SD3_DAT5__GPIO7_IO00             0x328 0x710 0x000 0x5 0x0
+#define MX6QDL_PAD_SD3_DAT6__SD3_DATA6              0x32c 0x714 0x000 0x0 0x0
+#define MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA          0x32c 0x714 0x8fc 0x1 0x2
+#define MX6QDL_PAD_SD3_DAT6__UART1_TX_DATA          0x32c 0x714 0x000 0x1 0x0
+#define MX6QDL_PAD_SD3_DAT6__GPIO6_IO18             0x32c 0x714 0x000 0x5 0x0
+#define MX6QDL_PAD_SD3_DAT7__SD3_DATA7              0x330 0x718 0x000 0x0 0x0
+#define MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA          0x330 0x718 0x000 0x1 0x0
+#define MX6QDL_PAD_SD3_DAT7__UART1_RX_DATA          0x330 0x718 0x8fc 0x1 0x3
+#define MX6QDL_PAD_SD3_DAT7__GPIO6_IO17             0x330 0x718 0x000 0x5 0x0
+#define MX6QDL_PAD_SD3_RST__SD3_RESET               0x334 0x71c 0x000 0x0 0x0
+#define MX6QDL_PAD_SD3_RST__UART3_RTS_B             0x334 0x71c 0x908 0x1 0x5
+#define MX6QDL_PAD_SD3_RST__UART3_CTS_B             0x334 0x71c 0x000 0x1 0x0
+#define MX6QDL_PAD_SD3_RST__GPIO7_IO08              0x334 0x71c 0x000 0x5 0x0
+#define MX6QDL_PAD_SD4_CLK__SD4_CLK                 0x338 0x720 0x938 0x0 0x1
+#define MX6QDL_PAD_SD4_CLK__NAND_WE_B               0x338 0x720 0x000 0x1 0x0
+#define MX6QDL_PAD_SD4_CLK__UART3_RX_DATA           0x338 0x720 0x90c 0x2 0x2
+#define MX6QDL_PAD_SD4_CLK__UART3_TX_DATA           0x338 0x720 0x000 0x2 0x0
+#define MX6QDL_PAD_SD4_CLK__GPIO7_IO10              0x338 0x720 0x000 0x5 0x0
+#define MX6QDL_PAD_SD4_CMD__SD4_CMD                 0x33c 0x724 0x000 0x0 0x0
+#define MX6QDL_PAD_SD4_CMD__NAND_RE_B               0x33c 0x724 0x000 0x1 0x0
+#define MX6QDL_PAD_SD4_CMD__UART3_TX_DATA           0x33c 0x724 0x000 0x2 0x0
+#define MX6QDL_PAD_SD4_CMD__UART3_RX_DATA           0x33c 0x724 0x90c 0x2 0x3
+#define MX6QDL_PAD_SD4_CMD__GPIO7_IO09              0x33c 0x724 0x000 0x5 0x0
+#define MX6QDL_PAD_SD4_DAT0__SD4_DATA0              0x340 0x728 0x000 0x1 0x0
+#define MX6QDL_PAD_SD4_DAT0__NAND_DQS               0x340 0x728 0x000 0x2 0x0
+#define MX6QDL_PAD_SD4_DAT0__GPIO2_IO08             0x340 0x728 0x000 0x5 0x0
+#define MX6QDL_PAD_SD4_DAT1__SD4_DATA1              0x344 0x72c 0x000 0x1 0x0
+#define MX6QDL_PAD_SD4_DAT1__PWM3_OUT               0x344 0x72c 0x000 0x2 0x0
+#define MX6QDL_PAD_SD4_DAT1__GPIO2_IO09             0x344 0x72c 0x000 0x5 0x0
+#define MX6QDL_PAD_SD4_DAT2__SD4_DATA2              0x348 0x730 0x000 0x1 0x0
+#define MX6QDL_PAD_SD4_DAT2__PWM4_OUT               0x348 0x730 0x000 0x2 0x0
+#define MX6QDL_PAD_SD4_DAT2__GPIO2_IO10             0x348 0x730 0x000 0x5 0x0
+#define MX6QDL_PAD_SD4_DAT3__SD4_DATA3              0x34c 0x734 0x000 0x1 0x0
+#define MX6QDL_PAD_SD4_DAT3__GPIO2_IO11             0x34c 0x734 0x000 0x5 0x0
+#define MX6QDL_PAD_SD4_DAT4__SD4_DATA4              0x350 0x738 0x000 0x1 0x0
+#define MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA          0x350 0x738 0x904 0x2 0x6
+#define MX6QDL_PAD_SD4_DAT4__UART2_TX_DATA          0x350 0x738 0x000 0x2 0x0
+#define MX6QDL_PAD_SD4_DAT4__GPIO2_IO12             0x350 0x738 0x000 0x5 0x0
+#define MX6QDL_PAD_SD4_DAT5__SD4_DATA5              0x354 0x73c 0x000 0x1 0x0
+#define MX6QDL_PAD_SD4_DAT5__UART2_RTS_B            0x354 0x73c 0x900 0x2 0x4
+#define MX6QDL_PAD_SD4_DAT5__UART2_CTS_B            0x354 0x73c 0x000 0x2 0x0
+#define MX6QDL_PAD_SD4_DAT5__GPIO2_IO13             0x354 0x73c 0x000 0x5 0x0
+#define MX6QDL_PAD_SD4_DAT6__SD4_DATA6              0x358 0x740 0x000 0x1 0x0
+#define MX6QDL_PAD_SD4_DAT6__UART2_CTS_B            0x358 0x740 0x000 0x2 0x0
+#define MX6QDL_PAD_SD4_DAT6__UART2_RTS_B            0x358 0x740 0x900 0x2 0x5
+#define MX6QDL_PAD_SD4_DAT6__GPIO2_IO14             0x358 0x740 0x000 0x5 0x0
+#define MX6QDL_PAD_SD4_DAT7__SD4_DATA7              0x35c 0x744 0x000 0x1 0x0
+#define MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA          0x35c 0x744 0x000 0x2 0x0
+#define MX6QDL_PAD_SD4_DAT7__UART2_RX_DATA          0x35c 0x744 0x904 0x2 0x7
+#define MX6QDL_PAD_SD4_DAT7__GPIO2_IO15             0x35c 0x744 0x000 0x5 0x0
+
+#endif /* __DTS_IMX6DL_PINFUNC_H */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/imx6q-pinfunc.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/imx6q-pinfunc.h
new file mode 100644
index 0000000000000000000000000000000000000000..cfb11d3e739c997d547aad7705b39fe71793fbad
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/imx6q-pinfunc.h
@@ -0,0 +1,1048 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __DTS_IMX6Q_PINFUNC_H
+#define __DTS_IMX6Q_PINFUNC_H
+
+/*
+ * The pin function ID is a tuple of
+ * <mux_reg conf_reg input_reg mux_mode input_val>
+ */
+#define MX6QDL_PAD_SD2_DAT1__SD2_DATA1              0x04c 0x360 0x000 0x0 0x0
+#define MX6QDL_PAD_SD2_DAT1__ECSPI5_SS0             0x04c 0x360 0x834 0x1 0x0
+#define MX6QDL_PAD_SD2_DAT1__EIM_CS2_B              0x04c 0x360 0x000 0x2 0x0
+#define MX6QDL_PAD_SD2_DAT1__AUD4_TXFS              0x04c 0x360 0x7c8 0x3 0x0
+#define MX6QDL_PAD_SD2_DAT1__KEY_COL7               0x04c 0x360 0x8f0 0x4 0x0
+#define MX6QDL_PAD_SD2_DAT1__GPIO1_IO14             0x04c 0x360 0x000 0x5 0x0
+#define MX6QDL_PAD_SD2_DAT2__SD2_DATA2              0x050 0x364 0x000 0x0 0x0
+#define MX6QDL_PAD_SD2_DAT2__ECSPI5_SS1             0x050 0x364 0x838 0x1 0x0
+#define MX6QDL_PAD_SD2_DAT2__EIM_CS3_B              0x050 0x364 0x000 0x2 0x0
+#define MX6QDL_PAD_SD2_DAT2__AUD4_TXD               0x050 0x364 0x7b8 0x3 0x0
+#define MX6QDL_PAD_SD2_DAT2__KEY_ROW6               0x050 0x364 0x8f8 0x4 0x0
+#define MX6QDL_PAD_SD2_DAT2__GPIO1_IO13             0x050 0x364 0x000 0x5 0x0
+#define MX6QDL_PAD_SD2_DAT0__SD2_DATA0              0x054 0x368 0x000 0x0 0x0
+#define MX6QDL_PAD_SD2_DAT0__ECSPI5_MISO            0x054 0x368 0x82c 0x1 0x0
+#define MX6QDL_PAD_SD2_DAT0__AUD4_RXD               0x054 0x368 0x7b4 0x3 0x0
+#define MX6QDL_PAD_SD2_DAT0__KEY_ROW7               0x054 0x368 0x8fc 0x4 0x0
+#define MX6QDL_PAD_SD2_DAT0__GPIO1_IO15             0x054 0x368 0x000 0x5 0x0
+#define MX6QDL_PAD_SD2_DAT0__DCIC2_OUT              0x054 0x368 0x000 0x6 0x0
+#define MX6QDL_PAD_RGMII_TXC__USB_H2_DATA           0x058 0x36c 0x000 0x0 0x0
+#define MX6QDL_PAD_RGMII_TXC__RGMII_TXC             0x058 0x36c 0x000 0x1 0x0
+#define MX6QDL_PAD_RGMII_TXC__SPDIF_EXT_CLK         0x058 0x36c 0x918 0x2 0x0
+#define MX6QDL_PAD_RGMII_TXC__GPIO6_IO19            0x058 0x36c 0x000 0x5 0x0
+#define MX6QDL_PAD_RGMII_TXC__XTALOSC_REF_CLK_24M   0x058 0x36c 0x000 0x7 0x0
+#define MX6QDL_PAD_RGMII_TD0__HSI_TX_READY          0x05c 0x370 0x000 0x0 0x0
+#define MX6QDL_PAD_RGMII_TD0__RGMII_TD0             0x05c 0x370 0x000 0x1 0x0
+#define MX6QDL_PAD_RGMII_TD0__GPIO6_IO20            0x05c 0x370 0x000 0x5 0x0
+#define MX6QDL_PAD_RGMII_TD1__HSI_RX_FLAG           0x060 0x374 0x000 0x0 0x0
+#define MX6QDL_PAD_RGMII_TD1__RGMII_TD1             0x060 0x374 0x000 0x1 0x0
+#define MX6QDL_PAD_RGMII_TD1__GPIO6_IO21            0x060 0x374 0x000 0x5 0x0
+#define MX6QDL_PAD_RGMII_TD2__HSI_RX_DATA           0x064 0x378 0x000 0x0 0x0
+#define MX6QDL_PAD_RGMII_TD2__RGMII_TD2             0x064 0x378 0x000 0x1 0x0
+#define MX6QDL_PAD_RGMII_TD2__GPIO6_IO22            0x064 0x378 0x000 0x5 0x0
+#define MX6QDL_PAD_RGMII_TD3__HSI_RX_WAKE           0x068 0x37c 0x000 0x0 0x0
+#define MX6QDL_PAD_RGMII_TD3__RGMII_TD3             0x068 0x37c 0x000 0x1 0x0
+#define MX6QDL_PAD_RGMII_TD3__GPIO6_IO23            0x068 0x37c 0x000 0x5 0x0
+#define MX6QDL_PAD_RGMII_RX_CTL__USB_H3_DATA        0x06c 0x380 0x000 0x0 0x0
+#define MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL       0x06c 0x380 0x858 0x1 0x0
+#define MX6QDL_PAD_RGMII_RX_CTL__GPIO6_IO24         0x06c 0x380 0x000 0x5 0x0
+#define MX6QDL_PAD_RGMII_RD0__HSI_RX_READY          0x070 0x384 0x000 0x0 0x0
+#define MX6QDL_PAD_RGMII_RD0__RGMII_RD0             0x070 0x384 0x848 0x1 0x0
+#define MX6QDL_PAD_RGMII_RD0__GPIO6_IO25            0x070 0x384 0x000 0x5 0x0
+#define MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE      0x074 0x388 0x000 0x0 0x0
+#define MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL       0x074 0x388 0x000 0x1 0x0
+#define MX6QDL_PAD_RGMII_TX_CTL__GPIO6_IO26         0x074 0x388 0x000 0x5 0x0
+#define MX6QDL_PAD_RGMII_TX_CTL__ENET_REF_CLK       0x074 0x388 0x83c 0x7 0x0
+#define MX6QDL_PAD_RGMII_RD1__HSI_TX_FLAG           0x078 0x38c 0x000 0x0 0x0
+#define MX6QDL_PAD_RGMII_RD1__RGMII_RD1             0x078 0x38c 0x84c 0x1 0x0
+#define MX6QDL_PAD_RGMII_RD1__GPIO6_IO27            0x078 0x38c 0x000 0x5 0x0
+#define MX6QDL_PAD_RGMII_RD2__HSI_TX_DATA           0x07c 0x390 0x000 0x0 0x0
+#define MX6QDL_PAD_RGMII_RD2__RGMII_RD2             0x07c 0x390 0x850 0x1 0x0
+#define MX6QDL_PAD_RGMII_RD2__GPIO6_IO28            0x07c 0x390 0x000 0x5 0x0
+#define MX6QDL_PAD_RGMII_RD3__HSI_TX_WAKE           0x080 0x394 0x000 0x0 0x0
+#define MX6QDL_PAD_RGMII_RD3__RGMII_RD3             0x080 0x394 0x854 0x1 0x0
+#define MX6QDL_PAD_RGMII_RD3__GPIO6_IO29            0x080 0x394 0x000 0x5 0x0
+#define MX6QDL_PAD_RGMII_RXC__USB_H3_STROBE         0x084 0x398 0x000 0x0 0x0
+#define MX6QDL_PAD_RGMII_RXC__RGMII_RXC             0x084 0x398 0x844 0x1 0x0
+#define MX6QDL_PAD_RGMII_RXC__GPIO6_IO30            0x084 0x398 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_A25__EIM_ADDR25              0x088 0x39c 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_A25__ECSPI4_SS1              0x088 0x39c 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_A25__ECSPI2_RDY              0x088 0x39c 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_A25__IPU1_DI1_PIN12          0x088 0x39c 0x000 0x3 0x0
+#define MX6QDL_PAD_EIM_A25__IPU1_DI0_D1_CS          0x088 0x39c 0x000 0x4 0x0
+#define MX6QDL_PAD_EIM_A25__GPIO5_IO02              0x088 0x39c 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE        0x088 0x39c 0x88c 0x6 0x0
+#define MX6QDL_PAD_EIM_EB2__EIM_EB2_B               0x08c 0x3a0 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_EB2__ECSPI1_SS0              0x08c 0x3a0 0x800 0x1 0x0
+#define MX6QDL_PAD_EIM_EB2__IPU2_CSI1_DATA19        0x08c 0x3a0 0x8d4 0x3 0x0
+#define MX6QDL_PAD_EIM_EB2__HDMI_TX_DDC_SCL         0x08c 0x3a0 0x890 0x4 0x0
+#define MX6QDL_PAD_EIM_EB2__GPIO2_IO30              0x08c 0x3a0 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_EB2__I2C2_SCL                0x08c 0x3a0 0x8a0 0x6 0x0
+#define MX6QDL_PAD_EIM_EB2__SRC_BOOT_CFG30          0x08c 0x3a0 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_D16__EIM_DATA16              0x090 0x3a4 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_D16__ECSPI1_SCLK             0x090 0x3a4 0x7f4 0x1 0x0
+#define MX6QDL_PAD_EIM_D16__IPU1_DI0_PIN05          0x090 0x3a4 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_D16__IPU2_CSI1_DATA18        0x090 0x3a4 0x8d0 0x3 0x0
+#define MX6QDL_PAD_EIM_D16__HDMI_TX_DDC_SDA         0x090 0x3a4 0x894 0x4 0x0
+#define MX6QDL_PAD_EIM_D16__GPIO3_IO16              0x090 0x3a4 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_D16__I2C2_SDA                0x090 0x3a4 0x8a4 0x6 0x0
+#define MX6QDL_PAD_EIM_D17__EIM_DATA17              0x094 0x3a8 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_D17__ECSPI1_MISO             0x094 0x3a8 0x7f8 0x1 0x0
+#define MX6QDL_PAD_EIM_D17__IPU1_DI0_PIN06          0x094 0x3a8 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_D17__IPU2_CSI1_PIXCLK        0x094 0x3a8 0x8e0 0x3 0x0
+#define MX6QDL_PAD_EIM_D17__DCIC1_OUT               0x094 0x3a8 0x000 0x4 0x0
+#define MX6QDL_PAD_EIM_D17__GPIO3_IO17              0x094 0x3a8 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_D17__I2C3_SCL                0x094 0x3a8 0x8a8 0x6 0x0
+#define MX6QDL_PAD_EIM_D18__EIM_DATA18              0x098 0x3ac 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_D18__ECSPI1_MOSI             0x098 0x3ac 0x7fc 0x1 0x0
+#define MX6QDL_PAD_EIM_D18__IPU1_DI0_PIN07          0x098 0x3ac 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_D18__IPU2_CSI1_DATA17        0x098 0x3ac 0x8cc 0x3 0x0
+#define MX6QDL_PAD_EIM_D18__IPU1_DI1_D0_CS          0x098 0x3ac 0x000 0x4 0x0
+#define MX6QDL_PAD_EIM_D18__GPIO3_IO18              0x098 0x3ac 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_D18__I2C3_SDA                0x098 0x3ac 0x8ac 0x6 0x0
+#define MX6QDL_PAD_EIM_D19__EIM_DATA19              0x09c 0x3b0 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_D19__ECSPI1_SS1              0x09c 0x3b0 0x804 0x1 0x0
+#define MX6QDL_PAD_EIM_D19__IPU1_DI0_PIN08          0x09c 0x3b0 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_D19__IPU2_CSI1_DATA16        0x09c 0x3b0 0x8c8 0x3 0x0
+#define MX6QDL_PAD_EIM_D19__UART1_CTS_B             0x09c 0x3b0 0x000 0x4 0x0
+#define MX6QDL_PAD_EIM_D19__UART1_RTS_B             0x09c 0x3b0 0x91c 0x4 0x0
+#define MX6QDL_PAD_EIM_D19__GPIO3_IO19              0x09c 0x3b0 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_D19__EPIT1_OUT               0x09c 0x3b0 0x000 0x6 0x0
+#define MX6QDL_PAD_EIM_D20__EIM_DATA20              0x0a0 0x3b4 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_D20__ECSPI4_SS0              0x0a0 0x3b4 0x824 0x1 0x0
+#define MX6QDL_PAD_EIM_D20__IPU1_DI0_PIN16          0x0a0 0x3b4 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_D20__IPU2_CSI1_DATA15        0x0a0 0x3b4 0x8c4 0x3 0x0
+#define MX6QDL_PAD_EIM_D20__UART1_RTS_B             0x0a0 0x3b4 0x91c 0x4 0x1
+#define MX6QDL_PAD_EIM_D20__UART1_CTS_B             0x0a0 0x3b4 0x000 0x4 0x0
+#define MX6QDL_PAD_EIM_D20__GPIO3_IO20              0x0a0 0x3b4 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_D20__EPIT2_OUT               0x0a0 0x3b4 0x000 0x6 0x0
+#define MX6QDL_PAD_EIM_D21__EIM_DATA21              0x0a4 0x3b8 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_D21__ECSPI4_SCLK             0x0a4 0x3b8 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_D21__IPU1_DI0_PIN17          0x0a4 0x3b8 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_D21__IPU2_CSI1_DATA11        0x0a4 0x3b8 0x8b4 0x3 0x0
+#define MX6QDL_PAD_EIM_D21__USB_OTG_OC              0x0a4 0x3b8 0x944 0x4 0x0
+#define MX6QDL_PAD_EIM_D21__GPIO3_IO21              0x0a4 0x3b8 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_D21__I2C1_SCL                0x0a4 0x3b8 0x898 0x6 0x0
+#define MX6QDL_PAD_EIM_D21__SPDIF_IN                0x0a4 0x3b8 0x914 0x7 0x0
+#define MX6QDL_PAD_EIM_D22__EIM_DATA22              0x0a8 0x3bc 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_D22__ECSPI4_MISO             0x0a8 0x3bc 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_D22__IPU1_DI0_PIN01          0x0a8 0x3bc 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_D22__IPU2_CSI1_DATA10        0x0a8 0x3bc 0x8b0 0x3 0x0
+#define MX6QDL_PAD_EIM_D22__USB_OTG_PWR             0x0a8 0x3bc 0x000 0x4 0x0
+#define MX6QDL_PAD_EIM_D22__GPIO3_IO22              0x0a8 0x3bc 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_D22__SPDIF_OUT               0x0a8 0x3bc 0x000 0x6 0x0
+#define MX6QDL_PAD_EIM_D23__EIM_DATA23              0x0ac 0x3c0 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_D23__IPU1_DI0_D0_CS          0x0ac 0x3c0 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_D23__UART3_CTS_B             0x0ac 0x3c0 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_D23__UART3_RTS_B             0x0ac 0x3c0 0x92c 0x2 0x0
+#define MX6QDL_PAD_EIM_D23__UART1_DCD_B             0x0ac 0x3c0 0x000 0x3 0x0
+#define MX6QDL_PAD_EIM_D23__IPU2_CSI1_DATA_EN       0x0ac 0x3c0 0x8d8 0x4 0x0
+#define MX6QDL_PAD_EIM_D23__GPIO3_IO23              0x0ac 0x3c0 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_D23__IPU1_DI1_PIN02          0x0ac 0x3c0 0x000 0x6 0x0
+#define MX6QDL_PAD_EIM_D23__IPU1_DI1_PIN14          0x0ac 0x3c0 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_EB3__EIM_EB3_B               0x0b0 0x3c4 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_EB3__ECSPI4_RDY              0x0b0 0x3c4 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_EB3__UART3_RTS_B             0x0b0 0x3c4 0x92c 0x2 0x1
+#define MX6QDL_PAD_EIM_EB3__UART3_CTS_B             0x0b0 0x3c4 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_EB3__UART1_RI_B              0x0b0 0x3c4 0x000 0x3 0x0
+#define MX6QDL_PAD_EIM_EB3__IPU2_CSI1_HSYNC         0x0b0 0x3c4 0x8dc 0x4 0x0
+#define MX6QDL_PAD_EIM_EB3__GPIO2_IO31              0x0b0 0x3c4 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_EB3__IPU1_DI1_PIN03          0x0b0 0x3c4 0x000 0x6 0x0
+#define MX6QDL_PAD_EIM_EB3__SRC_BOOT_CFG31          0x0b0 0x3c4 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_D24__EIM_DATA24              0x0b4 0x3c8 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_D24__ECSPI4_SS2              0x0b4 0x3c8 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_D24__UART3_TX_DATA           0x0b4 0x3c8 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_D24__UART3_RX_DATA           0x0b4 0x3c8 0x930 0x2 0x0
+#define MX6QDL_PAD_EIM_D24__ECSPI1_SS2              0x0b4 0x3c8 0x808 0x3 0x0
+#define MX6QDL_PAD_EIM_D24__ECSPI2_SS2              0x0b4 0x3c8 0x000 0x4 0x0
+#define MX6QDL_PAD_EIM_D24__GPIO3_IO24              0x0b4 0x3c8 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_D24__AUD5_RXFS               0x0b4 0x3c8 0x7d8 0x6 0x0
+#define MX6QDL_PAD_EIM_D24__UART1_DTR_B             0x0b4 0x3c8 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_D25__EIM_DATA25              0x0b8 0x3cc 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_D25__ECSPI4_SS3              0x0b8 0x3cc 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_D25__UART3_RX_DATA           0x0b8 0x3cc 0x930 0x2 0x1
+#define MX6QDL_PAD_EIM_D25__UART3_TX_DATA           0x0b8 0x3cc 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_D25__ECSPI1_SS3              0x0b8 0x3cc 0x80c 0x3 0x0
+#define MX6QDL_PAD_EIM_D25__ECSPI2_SS3              0x0b8 0x3cc 0x000 0x4 0x0
+#define MX6QDL_PAD_EIM_D25__GPIO3_IO25              0x0b8 0x3cc 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_D25__AUD5_RXC                0x0b8 0x3cc 0x7d4 0x6 0x0
+#define MX6QDL_PAD_EIM_D25__UART1_DSR_B             0x0b8 0x3cc 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_D26__EIM_DATA26              0x0bc 0x3d0 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_D26__IPU1_DI1_PIN11          0x0bc 0x3d0 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_D26__IPU1_CSI0_DATA01        0x0bc 0x3d0 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_D26__IPU2_CSI1_DATA14        0x0bc 0x3d0 0x8c0 0x3 0x0
+#define MX6QDL_PAD_EIM_D26__UART2_TX_DATA           0x0bc 0x3d0 0x000 0x4 0x0
+#define MX6QDL_PAD_EIM_D26__UART2_RX_DATA           0x0bc 0x3d0 0x928 0x4 0x0
+#define MX6QDL_PAD_EIM_D26__GPIO3_IO26              0x0bc 0x3d0 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_D26__IPU1_SISG2              0x0bc 0x3d0 0x000 0x6 0x0
+#define MX6QDL_PAD_EIM_D26__IPU1_DISP1_DATA22       0x0bc 0x3d0 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_D27__EIM_DATA27              0x0c0 0x3d4 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_D27__IPU1_DI1_PIN13          0x0c0 0x3d4 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_D27__IPU1_CSI0_DATA00        0x0c0 0x3d4 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_D27__IPU2_CSI1_DATA13        0x0c0 0x3d4 0x8bc 0x3 0x0
+#define MX6QDL_PAD_EIM_D27__UART2_RX_DATA           0x0c0 0x3d4 0x928 0x4 0x1
+#define MX6QDL_PAD_EIM_D27__UART2_TX_DATA           0x0c0 0x3d4 0x000 0x4 0x0
+#define MX6QDL_PAD_EIM_D27__GPIO3_IO27              0x0c0 0x3d4 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_D27__IPU1_SISG3              0x0c0 0x3d4 0x000 0x6 0x0
+#define MX6QDL_PAD_EIM_D27__IPU1_DISP1_DATA23       0x0c0 0x3d4 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_D28__EIM_DATA28              0x0c4 0x3d8 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_D28__I2C1_SDA                0x0c4 0x3d8 0x89c 0x1 0x0
+#define MX6QDL_PAD_EIM_D28__ECSPI4_MOSI             0x0c4 0x3d8 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_D28__IPU2_CSI1_DATA12        0x0c4 0x3d8 0x8b8 0x3 0x0
+#define MX6QDL_PAD_EIM_D28__UART2_CTS_B             0x0c4 0x3d8 0x000 0x4 0x0
+#define MX6QDL_PAD_EIM_D28__UART2_RTS_B             0x0c4 0x3d8 0x924 0x4 0x0
+#define MX6QDL_PAD_EIM_D28__UART2_DTE_CTS_B         0x0c4 0x3d8 0x924 0x4 0x0
+#define MX6QDL_PAD_EIM_D28__UART2_DTE_RTS_B         0x0c4 0x3d8 0x000 0x4 0x0
+#define MX6QDL_PAD_EIM_D28__GPIO3_IO28              0x0c4 0x3d8 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_D28__IPU1_EXT_TRIG           0x0c4 0x3d8 0x000 0x6 0x0
+#define MX6QDL_PAD_EIM_D28__IPU1_DI0_PIN13          0x0c4 0x3d8 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_D29__EIM_DATA29              0x0c8 0x3dc 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_D29__IPU1_DI1_PIN15          0x0c8 0x3dc 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_D29__ECSPI4_SS0              0x0c8 0x3dc 0x824 0x2 0x1
+#define MX6QDL_PAD_EIM_D29__UART2_RTS_B             0x0c8 0x3dc 0x924 0x4 0x1
+#define MX6QDL_PAD_EIM_D29__UART2_CTS_B             0x0c8 0x3dc 0x000 0x4 0x0
+#define MX6QDL_PAD_EIM_D29__UART2_DTE_RTS_B         0x0c8 0x3dc 0x000 0x4 0x0
+#define MX6QDL_PAD_EIM_D29__UART2_DTE_CTS_B         0x0c8 0x3dc 0x924 0x4 0x1
+#define MX6QDL_PAD_EIM_D29__GPIO3_IO29              0x0c8 0x3dc 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_D29__IPU2_CSI1_VSYNC         0x0c8 0x3dc 0x8e4 0x6 0x0
+#define MX6QDL_PAD_EIM_D29__IPU1_DI0_PIN14          0x0c8 0x3dc 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_D30__EIM_DATA30              0x0cc 0x3e0 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_D30__IPU1_DISP1_DATA21       0x0cc 0x3e0 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_D30__IPU1_DI0_PIN11          0x0cc 0x3e0 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_D30__IPU1_CSI0_DATA03        0x0cc 0x3e0 0x000 0x3 0x0
+#define MX6QDL_PAD_EIM_D30__UART3_CTS_B             0x0cc 0x3e0 0x000 0x4 0x0
+#define MX6QDL_PAD_EIM_D30__UART3_RTS_B             0x0cc 0x3e0 0x92c 0x4 0x2
+#define MX6QDL_PAD_EIM_D30__GPIO3_IO30              0x0cc 0x3e0 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_D30__USB_H1_OC               0x0cc 0x3e0 0x948 0x6 0x0
+#define MX6QDL_PAD_EIM_D31__EIM_DATA31              0x0d0 0x3e4 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_D31__IPU1_DISP1_DATA20       0x0d0 0x3e4 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_D31__IPU1_DI0_PIN12          0x0d0 0x3e4 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_D31__IPU1_CSI0_DATA02        0x0d0 0x3e4 0x000 0x3 0x0
+#define MX6QDL_PAD_EIM_D31__UART3_RTS_B             0x0d0 0x3e4 0x92c 0x4 0x3
+#define MX6QDL_PAD_EIM_D31__UART3_CTS_B             0x0d0 0x3e4 0x000 0x4 0x0
+#define MX6QDL_PAD_EIM_D31__GPIO3_IO31              0x0d0 0x3e4 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_D31__USB_H1_PWR              0x0d0 0x3e4 0x000 0x6 0x0
+#define MX6QDL_PAD_EIM_A24__EIM_ADDR24              0x0d4 0x3e8 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_A24__IPU1_DISP1_DATA19       0x0d4 0x3e8 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_A24__IPU2_CSI1_DATA19        0x0d4 0x3e8 0x8d4 0x2 0x1
+#define MX6QDL_PAD_EIM_A24__IPU2_SISG2              0x0d4 0x3e8 0x000 0x3 0x0
+#define MX6QDL_PAD_EIM_A24__IPU1_SISG2              0x0d4 0x3e8 0x000 0x4 0x0
+#define MX6QDL_PAD_EIM_A24__GPIO5_IO04              0x0d4 0x3e8 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_A24__SRC_BOOT_CFG24          0x0d4 0x3e8 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_A23__EIM_ADDR23              0x0d8 0x3ec 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_A23__IPU1_DISP1_DATA18       0x0d8 0x3ec 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_A23__IPU2_CSI1_DATA18        0x0d8 0x3ec 0x8d0 0x2 0x1
+#define MX6QDL_PAD_EIM_A23__IPU2_SISG3              0x0d8 0x3ec 0x000 0x3 0x0
+#define MX6QDL_PAD_EIM_A23__IPU1_SISG3              0x0d8 0x3ec 0x000 0x4 0x0
+#define MX6QDL_PAD_EIM_A23__GPIO6_IO06              0x0d8 0x3ec 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_A23__SRC_BOOT_CFG23          0x0d8 0x3ec 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_A22__EIM_ADDR22              0x0dc 0x3f0 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_A22__IPU1_DISP1_DATA17       0x0dc 0x3f0 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_A22__IPU2_CSI1_DATA17        0x0dc 0x3f0 0x8cc 0x2 0x1
+#define MX6QDL_PAD_EIM_A22__GPIO2_IO16              0x0dc 0x3f0 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_A22__SRC_BOOT_CFG22          0x0dc 0x3f0 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_A21__EIM_ADDR21              0x0e0 0x3f4 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_A21__IPU1_DISP1_DATA16       0x0e0 0x3f4 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_A21__IPU2_CSI1_DATA16        0x0e0 0x3f4 0x8c8 0x2 0x1
+#define MX6QDL_PAD_EIM_A21__GPIO2_IO17              0x0e0 0x3f4 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_A21__SRC_BOOT_CFG21          0x0e0 0x3f4 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_A20__EIM_ADDR20              0x0e4 0x3f8 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_A20__IPU1_DISP1_DATA15       0x0e4 0x3f8 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_A20__IPU2_CSI1_DATA15        0x0e4 0x3f8 0x8c4 0x2 0x1
+#define MX6QDL_PAD_EIM_A20__GPIO2_IO18              0x0e4 0x3f8 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_A20__SRC_BOOT_CFG20          0x0e4 0x3f8 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_A19__EIM_ADDR19              0x0e8 0x3fc 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_A19__IPU1_DISP1_DATA14       0x0e8 0x3fc 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_A19__IPU2_CSI1_DATA14        0x0e8 0x3fc 0x8c0 0x2 0x1
+#define MX6QDL_PAD_EIM_A19__GPIO2_IO19              0x0e8 0x3fc 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_A19__SRC_BOOT_CFG19          0x0e8 0x3fc 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_A18__EIM_ADDR18              0x0ec 0x400 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_A18__IPU1_DISP1_DATA13       0x0ec 0x400 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_A18__IPU2_CSI1_DATA13        0x0ec 0x400 0x8bc 0x2 0x1
+#define MX6QDL_PAD_EIM_A18__GPIO2_IO20              0x0ec 0x400 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_A18__SRC_BOOT_CFG18          0x0ec 0x400 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_A17__EIM_ADDR17              0x0f0 0x404 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_A17__IPU1_DISP1_DATA12       0x0f0 0x404 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_A17__IPU2_CSI1_DATA12        0x0f0 0x404 0x8b8 0x2 0x1
+#define MX6QDL_PAD_EIM_A17__GPIO2_IO21              0x0f0 0x404 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_A17__SRC_BOOT_CFG17          0x0f0 0x404 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_A16__EIM_ADDR16              0x0f4 0x408 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_A16__IPU1_DI1_DISP_CLK       0x0f4 0x408 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_A16__IPU2_CSI1_PIXCLK        0x0f4 0x408 0x8e0 0x2 0x1
+#define MX6QDL_PAD_EIM_A16__GPIO2_IO22              0x0f4 0x408 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_A16__SRC_BOOT_CFG16          0x0f4 0x408 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_CS0__EIM_CS0_B               0x0f8 0x40c 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_CS0__IPU1_DI1_PIN05          0x0f8 0x40c 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK             0x0f8 0x40c 0x810 0x2 0x0
+#define MX6QDL_PAD_EIM_CS0__GPIO2_IO23              0x0f8 0x40c 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_CS1__EIM_CS1_B               0x0fc 0x410 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_CS1__IPU1_DI1_PIN06          0x0fc 0x410 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI             0x0fc 0x410 0x818 0x2 0x0
+#define MX6QDL_PAD_EIM_CS1__GPIO2_IO24              0x0fc 0x410 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_OE__EIM_OE_B                 0x100 0x414 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_OE__IPU1_DI1_PIN07           0x100 0x414 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_OE__ECSPI2_MISO              0x100 0x414 0x814 0x2 0x0
+#define MX6QDL_PAD_EIM_OE__GPIO2_IO25               0x100 0x414 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_RW__EIM_RW                   0x104 0x418 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_RW__IPU1_DI1_PIN08           0x104 0x418 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_RW__ECSPI2_SS0               0x104 0x418 0x81c 0x2 0x0
+#define MX6QDL_PAD_EIM_RW__GPIO2_IO26               0x104 0x418 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_RW__SRC_BOOT_CFG29           0x104 0x418 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_LBA__EIM_LBA_B               0x108 0x41c 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_LBA__IPU1_DI1_PIN17          0x108 0x41c 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_LBA__ECSPI2_SS1              0x108 0x41c 0x820 0x2 0x0
+#define MX6QDL_PAD_EIM_LBA__GPIO2_IO27              0x108 0x41c 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_LBA__SRC_BOOT_CFG26          0x108 0x41c 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_EB0__EIM_EB0_B               0x10c 0x420 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_EB0__IPU1_DISP1_DATA11       0x10c 0x420 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_EB0__IPU2_CSI1_DATA11        0x10c 0x420 0x8b4 0x2 0x1
+#define MX6QDL_PAD_EIM_EB0__CCM_PMIC_READY          0x10c 0x420 0x7f0 0x4 0x0
+#define MX6QDL_PAD_EIM_EB0__GPIO2_IO28              0x10c 0x420 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_EB0__SRC_BOOT_CFG27          0x10c 0x420 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_EB1__EIM_EB1_B               0x110 0x424 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_EB1__IPU1_DISP1_DATA10       0x110 0x424 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_EB1__IPU2_CSI1_DATA10        0x110 0x424 0x8b0 0x2 0x1
+#define MX6QDL_PAD_EIM_EB1__GPIO2_IO29              0x110 0x424 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_EB1__SRC_BOOT_CFG28          0x110 0x424 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_DA0__EIM_AD00                0x114 0x428 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_DA0__IPU1_DISP1_DATA09       0x114 0x428 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_DA0__IPU2_CSI1_DATA09        0x114 0x428 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_DA0__GPIO3_IO00              0x114 0x428 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_DA0__SRC_BOOT_CFG00          0x114 0x428 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_DA1__EIM_AD01                0x118 0x42c 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_DA1__IPU1_DISP1_DATA08       0x118 0x42c 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_DA1__IPU2_CSI1_DATA08        0x118 0x42c 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_DA1__GPIO3_IO01              0x118 0x42c 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_DA1__SRC_BOOT_CFG01          0x118 0x42c 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_DA2__EIM_AD02                0x11c 0x430 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_DA2__IPU1_DISP1_DATA07       0x11c 0x430 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_DA2__IPU2_CSI1_DATA07        0x11c 0x430 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_DA2__GPIO3_IO02              0x11c 0x430 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_DA2__SRC_BOOT_CFG02          0x11c 0x430 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_DA3__EIM_AD03                0x120 0x434 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_DA3__IPU1_DISP1_DATA06       0x120 0x434 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_DA3__IPU2_CSI1_DATA06        0x120 0x434 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_DA3__GPIO3_IO03              0x120 0x434 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_DA3__SRC_BOOT_CFG03          0x120 0x434 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_DA4__EIM_AD04                0x124 0x438 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_DA4__IPU1_DISP1_DATA05       0x124 0x438 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_DA4__IPU2_CSI1_DATA05        0x124 0x438 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_DA4__GPIO3_IO04              0x124 0x438 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_DA4__SRC_BOOT_CFG04          0x124 0x438 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_DA5__EIM_AD05                0x128 0x43c 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_DA5__IPU1_DISP1_DATA04       0x128 0x43c 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_DA5__IPU2_CSI1_DATA04        0x128 0x43c 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_DA5__GPIO3_IO05              0x128 0x43c 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_DA5__SRC_BOOT_CFG05          0x128 0x43c 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_DA6__EIM_AD06                0x12c 0x440 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_DA6__IPU1_DISP1_DATA03       0x12c 0x440 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_DA6__IPU2_CSI1_DATA03        0x12c 0x440 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_DA6__GPIO3_IO06              0x12c 0x440 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_DA6__SRC_BOOT_CFG06          0x12c 0x440 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_DA7__EIM_AD07                0x130 0x444 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_DA7__IPU1_DISP1_DATA02       0x130 0x444 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_DA7__IPU2_CSI1_DATA02        0x130 0x444 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_DA7__GPIO3_IO07              0x130 0x444 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_DA7__SRC_BOOT_CFG07          0x130 0x444 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_DA8__EIM_AD08                0x134 0x448 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_DA8__IPU1_DISP1_DATA01       0x134 0x448 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_DA8__IPU2_CSI1_DATA01        0x134 0x448 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_DA8__GPIO3_IO08              0x134 0x448 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_DA8__SRC_BOOT_CFG08          0x134 0x448 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_DA9__EIM_AD09                0x138 0x44c 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_DA9__IPU1_DISP1_DATA00       0x138 0x44c 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_DA9__IPU2_CSI1_DATA00        0x138 0x44c 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_DA9__GPIO3_IO09              0x138 0x44c 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_DA9__SRC_BOOT_CFG09          0x138 0x44c 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_DA10__EIM_AD10               0x13c 0x450 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_DA10__IPU1_DI1_PIN15         0x13c 0x450 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_DA10__IPU2_CSI1_DATA_EN      0x13c 0x450 0x8d8 0x2 0x1
+#define MX6QDL_PAD_EIM_DA10__GPIO3_IO10             0x13c 0x450 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_DA10__SRC_BOOT_CFG10         0x13c 0x450 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_DA11__EIM_AD11               0x140 0x454 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_DA11__IPU1_DI1_PIN02         0x140 0x454 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_DA11__IPU2_CSI1_HSYNC        0x140 0x454 0x8dc 0x2 0x1
+#define MX6QDL_PAD_EIM_DA11__GPIO3_IO11             0x140 0x454 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_DA11__SRC_BOOT_CFG11         0x140 0x454 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_DA12__EIM_AD12               0x144 0x458 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_DA12__IPU1_DI1_PIN03         0x144 0x458 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_DA12__IPU2_CSI1_VSYNC        0x144 0x458 0x8e4 0x2 0x1
+#define MX6QDL_PAD_EIM_DA12__GPIO3_IO12             0x144 0x458 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_DA12__SRC_BOOT_CFG12         0x144 0x458 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_DA13__EIM_AD13               0x148 0x45c 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_DA13__IPU1_DI1_D0_CS         0x148 0x45c 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_DA13__GPIO3_IO13             0x148 0x45c 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_DA13__SRC_BOOT_CFG13         0x148 0x45c 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_DA14__EIM_AD14               0x14c 0x460 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_DA14__IPU1_DI1_D1_CS         0x14c 0x460 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_DA14__GPIO3_IO14             0x14c 0x460 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_DA14__SRC_BOOT_CFG14         0x14c 0x460 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_DA15__EIM_AD15               0x150 0x464 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_DA15__IPU1_DI1_PIN01         0x150 0x464 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_DA15__IPU1_DI1_PIN04         0x150 0x464 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_DA15__GPIO3_IO15             0x150 0x464 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_DA15__SRC_BOOT_CFG15         0x150 0x464 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B             0x154 0x468 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_WAIT__EIM_DTACK_B            0x154 0x468 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_WAIT__GPIO5_IO00             0x154 0x468 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_WAIT__SRC_BOOT_CFG25         0x154 0x468 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_BCLK__EIM_BCLK               0x158 0x46c 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_BCLK__IPU1_DI1_PIN16         0x158 0x46c 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_BCLK__GPIO6_IO31             0x158 0x46c 0x000 0x5 0x0
+#define MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK  0x15c 0x470 0x000 0x0 0x0
+#define MX6QDL_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK  0x15c 0x470 0x000 0x1 0x0
+#define MX6QDL_PAD_DI0_DISP_CLK__GPIO4_IO16         0x15c 0x470 0x000 0x5 0x0
+#define MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15        0x160 0x474 0x000 0x0 0x0
+#define MX6QDL_PAD_DI0_PIN15__IPU2_DI0_PIN15        0x160 0x474 0x000 0x1 0x0
+#define MX6QDL_PAD_DI0_PIN15__AUD6_TXC              0x160 0x474 0x000 0x2 0x0
+#define MX6QDL_PAD_DI0_PIN15__GPIO4_IO17            0x160 0x474 0x000 0x5 0x0
+#define MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02         0x164 0x478 0x000 0x0 0x0
+#define MX6QDL_PAD_DI0_PIN2__IPU2_DI0_PIN02         0x164 0x478 0x000 0x1 0x0
+#define MX6QDL_PAD_DI0_PIN2__AUD6_TXD               0x164 0x478 0x000 0x2 0x0
+#define MX6QDL_PAD_DI0_PIN2__GPIO4_IO18             0x164 0x478 0x000 0x5 0x0
+#define MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03         0x168 0x47c 0x000 0x0 0x0
+#define MX6QDL_PAD_DI0_PIN3__IPU2_DI0_PIN03         0x168 0x47c 0x000 0x1 0x0
+#define MX6QDL_PAD_DI0_PIN3__AUD6_TXFS              0x168 0x47c 0x000 0x2 0x0
+#define MX6QDL_PAD_DI0_PIN3__GPIO4_IO19             0x168 0x47c 0x000 0x5 0x0
+#define MX6QDL_PAD_DI0_PIN4__IPU1_DI0_PIN04         0x16c 0x480 0x000 0x0 0x0
+#define MX6QDL_PAD_DI0_PIN4__IPU2_DI0_PIN04         0x16c 0x480 0x000 0x1 0x0
+#define MX6QDL_PAD_DI0_PIN4__AUD6_RXD               0x16c 0x480 0x000 0x2 0x0
+#define MX6QDL_PAD_DI0_PIN4__SD1_WP                 0x16c 0x480 0x94c 0x3 0x0
+#define MX6QDL_PAD_DI0_PIN4__GPIO4_IO20             0x16c 0x480 0x000 0x5 0x0
+#define MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00    0x170 0x484 0x000 0x0 0x0
+#define MX6QDL_PAD_DISP0_DAT0__IPU2_DISP0_DATA00    0x170 0x484 0x000 0x1 0x0
+#define MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK          0x170 0x484 0x000 0x2 0x0
+#define MX6QDL_PAD_DISP0_DAT0__GPIO4_IO21           0x170 0x484 0x000 0x5 0x0
+#define MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01    0x174 0x488 0x000 0x0 0x0
+#define MX6QDL_PAD_DISP0_DAT1__IPU2_DISP0_DATA01    0x174 0x488 0x000 0x1 0x0
+#define MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI          0x174 0x488 0x000 0x2 0x0
+#define MX6QDL_PAD_DISP0_DAT1__GPIO4_IO22           0x174 0x488 0x000 0x5 0x0
+#define MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02    0x178 0x48c 0x000 0x0 0x0
+#define MX6QDL_PAD_DISP0_DAT2__IPU2_DISP0_DATA02    0x178 0x48c 0x000 0x1 0x0
+#define MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO          0x178 0x48c 0x000 0x2 0x0
+#define MX6QDL_PAD_DISP0_DAT2__GPIO4_IO23           0x178 0x48c 0x000 0x5 0x0
+#define MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03    0x17c 0x490 0x000 0x0 0x0
+#define MX6QDL_PAD_DISP0_DAT3__IPU2_DISP0_DATA03    0x17c 0x490 0x000 0x1 0x0
+#define MX6QDL_PAD_DISP0_DAT3__ECSPI3_SS0           0x17c 0x490 0x000 0x2 0x0
+#define MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24           0x17c 0x490 0x000 0x5 0x0
+#define MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04    0x180 0x494 0x000 0x0 0x0
+#define MX6QDL_PAD_DISP0_DAT4__IPU2_DISP0_DATA04    0x180 0x494 0x000 0x1 0x0
+#define MX6QDL_PAD_DISP0_DAT4__ECSPI3_SS1           0x180 0x494 0x000 0x2 0x0
+#define MX6QDL_PAD_DISP0_DAT4__GPIO4_IO25           0x180 0x494 0x000 0x5 0x0
+#define MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05    0x184 0x498 0x000 0x0 0x0
+#define MX6QDL_PAD_DISP0_DAT5__IPU2_DISP0_DATA05    0x184 0x498 0x000 0x1 0x0
+#define MX6QDL_PAD_DISP0_DAT5__ECSPI3_SS2           0x184 0x498 0x000 0x2 0x0
+#define MX6QDL_PAD_DISP0_DAT5__AUD6_RXFS            0x184 0x498 0x000 0x3 0x0
+#define MX6QDL_PAD_DISP0_DAT5__GPIO4_IO26           0x184 0x498 0x000 0x5 0x0
+#define MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06    0x188 0x49c 0x000 0x0 0x0
+#define MX6QDL_PAD_DISP0_DAT6__IPU2_DISP0_DATA06    0x188 0x49c 0x000 0x1 0x0
+#define MX6QDL_PAD_DISP0_DAT6__ECSPI3_SS3           0x188 0x49c 0x000 0x2 0x0
+#define MX6QDL_PAD_DISP0_DAT6__AUD6_RXC             0x188 0x49c 0x000 0x3 0x0
+#define MX6QDL_PAD_DISP0_DAT6__GPIO4_IO27           0x188 0x49c 0x000 0x5 0x0
+#define MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07    0x18c 0x4a0 0x000 0x0 0x0
+#define MX6QDL_PAD_DISP0_DAT7__IPU2_DISP0_DATA07    0x18c 0x4a0 0x000 0x1 0x0
+#define MX6QDL_PAD_DISP0_DAT7__ECSPI3_RDY           0x18c 0x4a0 0x000 0x2 0x0
+#define MX6QDL_PAD_DISP0_DAT7__GPIO4_IO28           0x18c 0x4a0 0x000 0x5 0x0
+#define MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08    0x190 0x4a4 0x000 0x0 0x0
+#define MX6QDL_PAD_DISP0_DAT8__IPU2_DISP0_DATA08    0x190 0x4a4 0x000 0x1 0x0
+#define MX6QDL_PAD_DISP0_DAT8__PWM1_OUT             0x190 0x4a4 0x000 0x2 0x0
+#define MX6QDL_PAD_DISP0_DAT8__WDOG1_B              0x190 0x4a4 0x000 0x3 0x0
+#define MX6QDL_PAD_DISP0_DAT8__GPIO4_IO29           0x190 0x4a4 0x000 0x5 0x0
+#define MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09    0x194 0x4a8 0x000 0x0 0x0
+#define MX6QDL_PAD_DISP0_DAT9__IPU2_DISP0_DATA09    0x194 0x4a8 0x000 0x1 0x0
+#define MX6QDL_PAD_DISP0_DAT9__PWM2_OUT             0x194 0x4a8 0x000 0x2 0x0
+#define MX6QDL_PAD_DISP0_DAT9__WDOG2_B              0x194 0x4a8 0x000 0x3 0x0
+#define MX6QDL_PAD_DISP0_DAT9__GPIO4_IO30           0x194 0x4a8 0x000 0x5 0x0
+#define MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10   0x198 0x4ac 0x000 0x0 0x0
+#define MX6QDL_PAD_DISP0_DAT10__IPU2_DISP0_DATA10   0x198 0x4ac 0x000 0x1 0x0
+#define MX6QDL_PAD_DISP0_DAT10__GPIO4_IO31          0x198 0x4ac 0x000 0x5 0x0
+#define MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11   0x19c 0x4b0 0x000 0x0 0x0
+#define MX6QDL_PAD_DISP0_DAT11__IPU2_DISP0_DATA11   0x19c 0x4b0 0x000 0x1 0x0
+#define MX6QDL_PAD_DISP0_DAT11__GPIO5_IO05          0x19c 0x4b0 0x000 0x5 0x0
+#define MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12   0x1a0 0x4b4 0x000 0x0 0x0
+#define MX6QDL_PAD_DISP0_DAT12__IPU2_DISP0_DATA12   0x1a0 0x4b4 0x000 0x1 0x0
+#define MX6QDL_PAD_DISP0_DAT12__GPIO5_IO06          0x1a0 0x4b4 0x000 0x5 0x0
+#define MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13   0x1a4 0x4b8 0x000 0x0 0x0
+#define MX6QDL_PAD_DISP0_DAT13__IPU2_DISP0_DATA13   0x1a4 0x4b8 0x000 0x1 0x0
+#define MX6QDL_PAD_DISP0_DAT13__AUD5_RXFS           0x1a4 0x4b8 0x7d8 0x3 0x1
+#define MX6QDL_PAD_DISP0_DAT13__GPIO5_IO07          0x1a4 0x4b8 0x000 0x5 0x0
+#define MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14   0x1a8 0x4bc 0x000 0x0 0x0
+#define MX6QDL_PAD_DISP0_DAT14__IPU2_DISP0_DATA14   0x1a8 0x4bc 0x000 0x1 0x0
+#define MX6QDL_PAD_DISP0_DAT14__AUD5_RXC            0x1a8 0x4bc 0x7d4 0x3 0x1
+#define MX6QDL_PAD_DISP0_DAT14__GPIO5_IO08          0x1a8 0x4bc 0x000 0x5 0x0
+#define MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15   0x1ac 0x4c0 0x000 0x0 0x0
+#define MX6QDL_PAD_DISP0_DAT15__IPU2_DISP0_DATA15   0x1ac 0x4c0 0x000 0x1 0x0
+#define MX6QDL_PAD_DISP0_DAT15__ECSPI1_SS1          0x1ac 0x4c0 0x804 0x2 0x1
+#define MX6QDL_PAD_DISP0_DAT15__ECSPI2_SS1          0x1ac 0x4c0 0x820 0x3 0x1
+#define MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09          0x1ac 0x4c0 0x000 0x5 0x0
+#define MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16   0x1b0 0x4c4 0x000 0x0 0x0
+#define MX6QDL_PAD_DISP0_DAT16__IPU2_DISP0_DATA16   0x1b0 0x4c4 0x000 0x1 0x0
+#define MX6QDL_PAD_DISP0_DAT16__ECSPI2_MOSI         0x1b0 0x4c4 0x818 0x2 0x1
+#define MX6QDL_PAD_DISP0_DAT16__AUD5_TXC            0x1b0 0x4c4 0x7dc 0x3 0x0
+#define MX6QDL_PAD_DISP0_DAT16__SDMA_EXT_EVENT0     0x1b0 0x4c4 0x90c 0x4 0x0
+#define MX6QDL_PAD_DISP0_DAT16__GPIO5_IO10          0x1b0 0x4c4 0x000 0x5 0x0
+#define MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17   0x1b4 0x4c8 0x000 0x0 0x0
+#define MX6QDL_PAD_DISP0_DAT17__IPU2_DISP0_DATA17   0x1b4 0x4c8 0x000 0x1 0x0
+#define MX6QDL_PAD_DISP0_DAT17__ECSPI2_MISO         0x1b4 0x4c8 0x814 0x2 0x1
+#define MX6QDL_PAD_DISP0_DAT17__AUD5_TXD            0x1b4 0x4c8 0x7d0 0x3 0x0
+#define MX6QDL_PAD_DISP0_DAT17__SDMA_EXT_EVENT1     0x1b4 0x4c8 0x910 0x4 0x0
+#define MX6QDL_PAD_DISP0_DAT17__GPIO5_IO11          0x1b4 0x4c8 0x000 0x5 0x0
+#define MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18   0x1b8 0x4cc 0x000 0x0 0x0
+#define MX6QDL_PAD_DISP0_DAT18__IPU2_DISP0_DATA18   0x1b8 0x4cc 0x000 0x1 0x0
+#define MX6QDL_PAD_DISP0_DAT18__ECSPI2_SS0          0x1b8 0x4cc 0x81c 0x2 0x1
+#define MX6QDL_PAD_DISP0_DAT18__AUD5_TXFS           0x1b8 0x4cc 0x7e0 0x3 0x0
+#define MX6QDL_PAD_DISP0_DAT18__AUD4_RXFS           0x1b8 0x4cc 0x7c0 0x4 0x0
+#define MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12          0x1b8 0x4cc 0x000 0x5 0x0
+#define MX6QDL_PAD_DISP0_DAT18__EIM_CS2_B           0x1b8 0x4cc 0x000 0x7 0x0
+#define MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19   0x1bc 0x4d0 0x000 0x0 0x0
+#define MX6QDL_PAD_DISP0_DAT19__IPU2_DISP0_DATA19   0x1bc 0x4d0 0x000 0x1 0x0
+#define MX6QDL_PAD_DISP0_DAT19__ECSPI2_SCLK         0x1bc 0x4d0 0x810 0x2 0x1
+#define MX6QDL_PAD_DISP0_DAT19__AUD5_RXD            0x1bc 0x4d0 0x7cc 0x3 0x0
+#define MX6QDL_PAD_DISP0_DAT19__AUD4_RXC            0x1bc 0x4d0 0x7bc 0x4 0x0
+#define MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13          0x1bc 0x4d0 0x000 0x5 0x0
+#define MX6QDL_PAD_DISP0_DAT19__EIM_CS3_B           0x1bc 0x4d0 0x000 0x7 0x0
+#define MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20   0x1c0 0x4d4 0x000 0x0 0x0
+#define MX6QDL_PAD_DISP0_DAT20__IPU2_DISP0_DATA20   0x1c0 0x4d4 0x000 0x1 0x0
+#define MX6QDL_PAD_DISP0_DAT20__ECSPI1_SCLK         0x1c0 0x4d4 0x7f4 0x2 0x1
+#define MX6QDL_PAD_DISP0_DAT20__AUD4_TXC            0x1c0 0x4d4 0x7c4 0x3 0x0
+#define MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14          0x1c0 0x4d4 0x000 0x5 0x0
+#define MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21   0x1c4 0x4d8 0x000 0x0 0x0
+#define MX6QDL_PAD_DISP0_DAT21__IPU2_DISP0_DATA21   0x1c4 0x4d8 0x000 0x1 0x0
+#define MX6QDL_PAD_DISP0_DAT21__ECSPI1_MOSI         0x1c4 0x4d8 0x7fc 0x2 0x1
+#define MX6QDL_PAD_DISP0_DAT21__AUD4_TXD            0x1c4 0x4d8 0x7b8 0x3 0x1
+#define MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15          0x1c4 0x4d8 0x000 0x5 0x0
+#define MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22   0x1c8 0x4dc 0x000 0x0 0x0
+#define MX6QDL_PAD_DISP0_DAT22__IPU2_DISP0_DATA22   0x1c8 0x4dc 0x000 0x1 0x0
+#define MX6QDL_PAD_DISP0_DAT22__ECSPI1_MISO         0x1c8 0x4dc 0x7f8 0x2 0x1
+#define MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS           0x1c8 0x4dc 0x7c8 0x3 0x1
+#define MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16          0x1c8 0x4dc 0x000 0x5 0x0
+#define MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23   0x1cc 0x4e0 0x000 0x0 0x0
+#define MX6QDL_PAD_DISP0_DAT23__IPU2_DISP0_DATA23   0x1cc 0x4e0 0x000 0x1 0x0
+#define MX6QDL_PAD_DISP0_DAT23__ECSPI1_SS0          0x1cc 0x4e0 0x800 0x2 0x1
+#define MX6QDL_PAD_DISP0_DAT23__AUD4_RXD            0x1cc 0x4e0 0x7b4 0x3 0x1
+#define MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17          0x1cc 0x4e0 0x000 0x5 0x0
+#define MX6QDL_PAD_ENET_MDIO__ENET_MDIO             0x1d0 0x4e4 0x840 0x1 0x0
+#define MX6QDL_PAD_ENET_MDIO__ESAI_RX_CLK           0x1d0 0x4e4 0x86c 0x2 0x0
+#define MX6QDL_PAD_ENET_MDIO__ENET_1588_EVENT1_OUT  0x1d0 0x4e4 0x000 0x4 0x0
+#define MX6QDL_PAD_ENET_MDIO__GPIO1_IO22            0x1d0 0x4e4 0x000 0x5 0x0
+#define MX6QDL_PAD_ENET_MDIO__SPDIF_LOCK            0x1d0 0x4e4 0x000 0x6 0x0
+#define MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK        0x1d4 0x4e8 0x000 0x1 0x0
+#define MX6QDL_PAD_ENET_REF_CLK__ESAI_RX_FS         0x1d4 0x4e8 0x85c 0x2 0x0
+#define MX6QDL_PAD_ENET_REF_CLK__GPIO1_IO23         0x1d4 0x4e8 0x000 0x5 0x0
+#define MX6QDL_PAD_ENET_REF_CLK__SPDIF_SR_CLK       0x1d4 0x4e8 0x000 0x6 0x0
+#define MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID           0x1d8 0x4ec 0x004 0x0 0xff0d0100
+#define MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER           0x1d8 0x4ec 0x000 0x1 0x0
+#define MX6QDL_PAD_ENET_RX_ER__ESAI_RX_HF_CLK       0x1d8 0x4ec 0x864 0x2 0x0
+#define MX6QDL_PAD_ENET_RX_ER__SPDIF_IN             0x1d8 0x4ec 0x914 0x3 0x1
+#define MX6QDL_PAD_ENET_RX_ER__ENET_1588_EVENT2_OUT 0x1d8 0x4ec 0x000 0x4 0x0
+#define MX6QDL_PAD_ENET_RX_ER__GPIO1_IO24           0x1d8 0x4ec 0x000 0x5 0x0
+#define MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN          0x1dc 0x4f0 0x858 0x1 0x1
+#define MX6QDL_PAD_ENET_CRS_DV__ESAI_TX_CLK         0x1dc 0x4f0 0x870 0x2 0x0
+#define MX6QDL_PAD_ENET_CRS_DV__SPDIF_EXT_CLK       0x1dc 0x4f0 0x918 0x3 0x1
+#define MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25          0x1dc 0x4f0 0x000 0x5 0x0
+#define MX6QDL_PAD_ENET_RXD1__MLB_SIG               0x1e0 0x4f4 0x908 0x0 0x0
+#define MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1         0x1e0 0x4f4 0x84c 0x1 0x1
+#define MX6QDL_PAD_ENET_RXD1__ESAI_TX_FS            0x1e0 0x4f4 0x860 0x2 0x0
+#define MX6QDL_PAD_ENET_RXD1__ENET_1588_EVENT3_OUT  0x1e0 0x4f4 0x000 0x4 0x0
+#define MX6QDL_PAD_ENET_RXD1__GPIO1_IO26            0x1e0 0x4f4 0x000 0x5 0x0
+#define MX6QDL_PAD_ENET_RXD0__OSC32K_32K_OUT        0x1e4 0x4f8 0x000 0x0 0x0
+#define MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0         0x1e4 0x4f8 0x848 0x1 0x1
+#define MX6QDL_PAD_ENET_RXD0__ESAI_TX_HF_CLK        0x1e4 0x4f8 0x868 0x2 0x0
+#define MX6QDL_PAD_ENET_RXD0__SPDIF_OUT             0x1e4 0x4f8 0x000 0x3 0x0
+#define MX6QDL_PAD_ENET_RXD0__GPIO1_IO27            0x1e4 0x4f8 0x000 0x5 0x0
+#define MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN           0x1e8 0x4fc 0x000 0x1 0x0
+#define MX6QDL_PAD_ENET_TX_EN__ESAI_TX3_RX2         0x1e8 0x4fc 0x880 0x2 0x0
+#define MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28           0x1e8 0x4fc 0x000 0x5 0x0
+#define MX6QDL_PAD_ENET_TXD1__MLB_CLK               0x1ec 0x500 0x900 0x0 0x0
+#define MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1         0x1ec 0x500 0x000 0x1 0x0
+#define MX6QDL_PAD_ENET_TXD1__ESAI_TX2_RX3          0x1ec 0x500 0x87c 0x2 0x0
+#define MX6QDL_PAD_ENET_TXD1__ENET_1588_EVENT0_IN   0x1ec 0x500 0x000 0x4 0x0
+#define MX6QDL_PAD_ENET_TXD1__GPIO1_IO29            0x1ec 0x500 0x000 0x5 0x0
+#define MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0         0x1f0 0x504 0x000 0x1 0x0
+#define MX6QDL_PAD_ENET_TXD0__ESAI_TX4_RX1          0x1f0 0x504 0x884 0x2 0x0
+#define MX6QDL_PAD_ENET_TXD0__GPIO1_IO30            0x1f0 0x504 0x000 0x5 0x0
+#define MX6QDL_PAD_ENET_MDC__MLB_DATA               0x1f4 0x508 0x904 0x0 0x0
+#define MX6QDL_PAD_ENET_MDC__ENET_MDC               0x1f4 0x508 0x000 0x1 0x0
+#define MX6QDL_PAD_ENET_MDC__ESAI_TX5_RX0           0x1f4 0x508 0x888 0x2 0x0
+#define MX6QDL_PAD_ENET_MDC__ENET_1588_EVENT1_IN    0x1f4 0x508 0x000 0x4 0x0
+#define MX6QDL_PAD_ENET_MDC__GPIO1_IO31             0x1f4 0x508 0x000 0x5 0x0
+#define MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK            0x1f8 0x5c8 0x7f4 0x0 0x2
+#define MX6QDL_PAD_KEY_COL0__ENET_RX_DATA3          0x1f8 0x5c8 0x854 0x1 0x1
+#define MX6QDL_PAD_KEY_COL0__AUD5_TXC               0x1f8 0x5c8 0x7dc 0x2 0x1
+#define MX6QDL_PAD_KEY_COL0__KEY_COL0               0x1f8 0x5c8 0x000 0x3 0x0
+#define MX6QDL_PAD_KEY_COL0__UART4_TX_DATA          0x1f8 0x5c8 0x000 0x4 0x0
+#define MX6QDL_PAD_KEY_COL0__UART4_RX_DATA          0x1f8 0x5c8 0x938 0x4 0x0
+#define MX6QDL_PAD_KEY_COL0__GPIO4_IO06             0x1f8 0x5c8 0x000 0x5 0x0
+#define MX6QDL_PAD_KEY_COL0__DCIC1_OUT              0x1f8 0x5c8 0x000 0x6 0x0
+#define MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI            0x1fc 0x5cc 0x7fc 0x0 0x2
+#define MX6QDL_PAD_KEY_ROW0__ENET_TX_DATA3          0x1fc 0x5cc 0x000 0x1 0x0
+#define MX6QDL_PAD_KEY_ROW0__AUD5_TXD               0x1fc 0x5cc 0x7d0 0x2 0x1
+#define MX6QDL_PAD_KEY_ROW0__KEY_ROW0               0x1fc 0x5cc 0x000 0x3 0x0
+#define MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA          0x1fc 0x5cc 0x938 0x4 0x1
+#define MX6QDL_PAD_KEY_ROW0__UART4_TX_DATA          0x1fc 0x5cc 0x000 0x4 0x0
+#define MX6QDL_PAD_KEY_ROW0__GPIO4_IO07             0x1fc 0x5cc 0x000 0x5 0x0
+#define MX6QDL_PAD_KEY_ROW0__DCIC2_OUT              0x1fc 0x5cc 0x000 0x6 0x0
+#define MX6QDL_PAD_KEY_COL1__ECSPI1_MISO            0x200 0x5d0 0x7f8 0x0 0x2
+#define MX6QDL_PAD_KEY_COL1__ENET_MDIO              0x200 0x5d0 0x840 0x1 0x1
+#define MX6QDL_PAD_KEY_COL1__AUD5_TXFS              0x200 0x5d0 0x7e0 0x2 0x1
+#define MX6QDL_PAD_KEY_COL1__KEY_COL1               0x200 0x5d0 0x000 0x3 0x0
+#define MX6QDL_PAD_KEY_COL1__UART5_TX_DATA          0x200 0x5d0 0x000 0x4 0x0
+#define MX6QDL_PAD_KEY_COL1__UART5_RX_DATA          0x200 0x5d0 0x940 0x4 0x0
+#define MX6QDL_PAD_KEY_COL1__GPIO4_IO08             0x200 0x5d0 0x000 0x5 0x0
+#define MX6QDL_PAD_KEY_COL1__SD1_VSELECT            0x200 0x5d0 0x000 0x6 0x0
+#define MX6QDL_PAD_KEY_ROW1__ECSPI1_SS0             0x204 0x5d4 0x800 0x0 0x2
+#define MX6QDL_PAD_KEY_ROW1__ENET_COL               0x204 0x5d4 0x000 0x1 0x0
+#define MX6QDL_PAD_KEY_ROW1__AUD5_RXD               0x204 0x5d4 0x7cc 0x2 0x1
+#define MX6QDL_PAD_KEY_ROW1__KEY_ROW1               0x204 0x5d4 0x000 0x3 0x0
+#define MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA          0x204 0x5d4 0x940 0x4 0x1
+#define MX6QDL_PAD_KEY_ROW1__UART5_TX_DATA          0x204 0x5d4 0x000 0x4 0x0
+#define MX6QDL_PAD_KEY_ROW1__GPIO4_IO09             0x204 0x5d4 0x000 0x5 0x0
+#define MX6QDL_PAD_KEY_ROW1__SD2_VSELECT            0x204 0x5d4 0x000 0x6 0x0
+#define MX6QDL_PAD_KEY_COL2__ECSPI1_SS1             0x208 0x5d8 0x804 0x0 0x2
+#define MX6QDL_PAD_KEY_COL2__ENET_RX_DATA2          0x208 0x5d8 0x850 0x1 0x1
+#define MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX            0x208 0x5d8 0x000 0x2 0x0
+#define MX6QDL_PAD_KEY_COL2__KEY_COL2               0x208 0x5d8 0x000 0x3 0x0
+#define MX6QDL_PAD_KEY_COL2__ENET_MDC               0x208 0x5d8 0x000 0x4 0x0
+#define MX6QDL_PAD_KEY_COL2__GPIO4_IO10             0x208 0x5d8 0x000 0x5 0x0
+#define MX6QDL_PAD_KEY_COL2__USB_H1_PWR_CTL_WAKE    0x208 0x5d8 0x000 0x6 0x0
+#define MX6QDL_PAD_KEY_ROW2__ECSPI1_SS2             0x20c 0x5dc 0x808 0x0 0x1
+#define MX6QDL_PAD_KEY_ROW2__ENET_TX_DATA2          0x20c 0x5dc 0x000 0x1 0x0
+#define MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX            0x20c 0x5dc 0x7e4 0x2 0x0
+#define MX6QDL_PAD_KEY_ROW2__KEY_ROW2               0x20c 0x5dc 0x000 0x3 0x0
+#define MX6QDL_PAD_KEY_ROW2__SD2_VSELECT            0x20c 0x5dc 0x000 0x4 0x0
+#define MX6QDL_PAD_KEY_ROW2__GPIO4_IO11             0x20c 0x5dc 0x000 0x5 0x0
+#define MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE       0x20c 0x5dc 0x88c 0x6 0x1
+#define MX6QDL_PAD_KEY_COL3__ECSPI1_SS3             0x210 0x5e0 0x80c 0x0 0x1
+#define MX6QDL_PAD_KEY_COL3__ENET_CRS               0x210 0x5e0 0x000 0x1 0x0
+#define MX6QDL_PAD_KEY_COL3__HDMI_TX_DDC_SCL        0x210 0x5e0 0x890 0x2 0x1
+#define MX6QDL_PAD_KEY_COL3__KEY_COL3               0x210 0x5e0 0x000 0x3 0x0
+#define MX6QDL_PAD_KEY_COL3__I2C2_SCL               0x210 0x5e0 0x8a0 0x4 0x1
+#define MX6QDL_PAD_KEY_COL3__GPIO4_IO12             0x210 0x5e0 0x000 0x5 0x0
+#define MX6QDL_PAD_KEY_COL3__SPDIF_IN               0x210 0x5e0 0x914 0x6 0x2
+#define MX6QDL_PAD_KEY_ROW3__ASRC_EXT_CLK           0x214 0x5e4 0x7b0 0x1 0x0
+#define MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA        0x214 0x5e4 0x894 0x2 0x1
+#define MX6QDL_PAD_KEY_ROW3__KEY_ROW3               0x214 0x5e4 0x000 0x3 0x0
+#define MX6QDL_PAD_KEY_ROW3__I2C2_SDA               0x214 0x5e4 0x8a4 0x4 0x1
+#define MX6QDL_PAD_KEY_ROW3__GPIO4_IO13             0x214 0x5e4 0x000 0x5 0x0
+#define MX6QDL_PAD_KEY_ROW3__SD1_VSELECT            0x214 0x5e4 0x000 0x6 0x0
+#define MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX            0x218 0x5e8 0x000 0x0 0x0
+#define MX6QDL_PAD_KEY_COL4__IPU1_SISG4             0x218 0x5e8 0x000 0x1 0x0
+#define MX6QDL_PAD_KEY_COL4__USB_OTG_OC             0x218 0x5e8 0x944 0x2 0x1
+#define MX6QDL_PAD_KEY_COL4__KEY_COL4               0x218 0x5e8 0x000 0x3 0x0
+#define MX6QDL_PAD_KEY_COL4__UART5_RTS_B            0x218 0x5e8 0x93c 0x4 0x0
+#define MX6QDL_PAD_KEY_COL4__UART5_CTS_B            0x218 0x5e8 0x000 0x4 0x0
+#define MX6QDL_PAD_KEY_COL4__GPIO4_IO14             0x218 0x5e8 0x000 0x5 0x0
+#define MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX            0x21c 0x5ec 0x7e8 0x0 0x0
+#define MX6QDL_PAD_KEY_ROW4__IPU1_SISG5             0x21c 0x5ec 0x000 0x1 0x0
+#define MX6QDL_PAD_KEY_ROW4__USB_OTG_PWR            0x21c 0x5ec 0x000 0x2 0x0
+#define MX6QDL_PAD_KEY_ROW4__KEY_ROW4               0x21c 0x5ec 0x000 0x3 0x0
+#define MX6QDL_PAD_KEY_ROW4__UART5_CTS_B            0x21c 0x5ec 0x000 0x4 0x0
+#define MX6QDL_PAD_KEY_ROW4__UART5_RTS_B            0x21c 0x5ec 0x93c 0x4 0x1
+#define MX6QDL_PAD_KEY_ROW4__GPIO4_IO15             0x21c 0x5ec 0x000 0x5 0x0
+#define MX6QDL_PAD_GPIO_0__CCM_CLKO1                0x220 0x5f0 0x000 0x0 0x0
+#define MX6QDL_PAD_GPIO_0__KEY_COL5                 0x220 0x5f0 0x8e8 0x2 0x0
+#define MX6QDL_PAD_GPIO_0__ASRC_EXT_CLK             0x220 0x5f0 0x7b0 0x3 0x1
+#define MX6QDL_PAD_GPIO_0__EPIT1_OUT                0x220 0x5f0 0x000 0x4 0x0
+#define MX6QDL_PAD_GPIO_0__GPIO1_IO00               0x220 0x5f0 0x000 0x5 0x0
+#define MX6QDL_PAD_GPIO_0__USB_H1_PWR               0x220 0x5f0 0x000 0x6 0x0
+#define MX6QDL_PAD_GPIO_0__SNVS_VIO_5               0x220 0x5f0 0x000 0x7 0x0
+#define MX6QDL_PAD_GPIO_1__ESAI_RX_CLK              0x224 0x5f4 0x86c 0x0 0x1
+#define MX6QDL_PAD_GPIO_1__WDOG2_B                  0x224 0x5f4 0x000 0x1 0x0
+#define MX6QDL_PAD_GPIO_1__KEY_ROW5                 0x224 0x5f4 0x8f4 0x2 0x0
+#define MX6QDL_PAD_GPIO_1__USB_OTG_ID               0x224 0x5f4 0x004 0x3 0xff0d0101
+#define MX6QDL_PAD_GPIO_1__PWM2_OUT                 0x224 0x5f4 0x000 0x4 0x0
+#define MX6QDL_PAD_GPIO_1__GPIO1_IO01               0x224 0x5f4 0x000 0x5 0x0
+#define MX6QDL_PAD_GPIO_1__SD1_CD_B                 0x224 0x5f4 0x000 0x6 0x0
+#define MX6QDL_PAD_GPIO_9__ESAI_RX_FS               0x228 0x5f8 0x85c 0x0 0x1
+#define MX6QDL_PAD_GPIO_9__WDOG1_B                  0x228 0x5f8 0x000 0x1 0x0
+#define MX6QDL_PAD_GPIO_9__KEY_COL6                 0x228 0x5f8 0x8ec 0x2 0x0
+#define MX6QDL_PAD_GPIO_9__CCM_REF_EN_B             0x228 0x5f8 0x000 0x3 0x0
+#define MX6QDL_PAD_GPIO_9__PWM1_OUT                 0x228 0x5f8 0x000 0x4 0x0
+#define MX6QDL_PAD_GPIO_9__GPIO1_IO09               0x228 0x5f8 0x000 0x5 0x0
+#define MX6QDL_PAD_GPIO_9__SD1_WP                   0x228 0x5f8 0x94c 0x6 0x1
+#define MX6QDL_PAD_GPIO_3__ESAI_RX_HF_CLK           0x22c 0x5fc 0x864 0x0 0x1
+#define MX6QDL_PAD_GPIO_3__I2C3_SCL                 0x22c 0x5fc 0x8a8 0x2 0x1
+#define MX6QDL_PAD_GPIO_3__XTALOSC_REF_CLK_24M      0x22c 0x5fc 0x000 0x3 0x0
+#define MX6QDL_PAD_GPIO_3__CCM_CLKO2                0x22c 0x5fc 0x000 0x4 0x0
+#define MX6QDL_PAD_GPIO_3__GPIO1_IO03               0x22c 0x5fc 0x000 0x5 0x0
+#define MX6QDL_PAD_GPIO_3__USB_H1_OC                0x22c 0x5fc 0x948 0x6 0x1
+#define MX6QDL_PAD_GPIO_3__MLB_CLK                  0x22c 0x5fc 0x900 0x7 0x1
+#define MX6QDL_PAD_GPIO_6__ESAI_TX_CLK              0x230 0x600 0x870 0x0 0x1
+#define MX6QDL_PAD_GPIO_6__ENET_IRQ		    0x230 0x600 0x03c 0x11 0xff000609
+#define MX6QDL_PAD_GPIO_6__I2C3_SDA                 0x230 0x600 0x8ac 0x2 0x1
+#define MX6QDL_PAD_GPIO_6__GPIO1_IO06               0x230 0x600 0x000 0x5 0x0
+#define MX6QDL_PAD_GPIO_6__SD2_LCTL                 0x230 0x600 0x000 0x6 0x0
+#define MX6QDL_PAD_GPIO_6__MLB_SIG                  0x230 0x600 0x908 0x7 0x1
+#define MX6QDL_PAD_GPIO_2__ESAI_TX_FS               0x234 0x604 0x860 0x0 0x1
+#define MX6QDL_PAD_GPIO_2__KEY_ROW6                 0x234 0x604 0x8f8 0x2 0x1
+#define MX6QDL_PAD_GPIO_2__GPIO1_IO02               0x234 0x604 0x000 0x5 0x0
+#define MX6QDL_PAD_GPIO_2__SD2_WP                   0x234 0x604 0x000 0x6 0x0
+#define MX6QDL_PAD_GPIO_2__MLB_DATA                 0x234 0x604 0x904 0x7 0x1
+#define MX6QDL_PAD_GPIO_4__ESAI_TX_HF_CLK           0x238 0x608 0x868 0x0 0x1
+#define MX6QDL_PAD_GPIO_4__KEY_COL7                 0x238 0x608 0x8f0 0x2 0x1
+#define MX6QDL_PAD_GPIO_4__GPIO1_IO04               0x238 0x608 0x000 0x5 0x0
+#define MX6QDL_PAD_GPIO_4__SD2_CD_B                 0x238 0x608 0x000 0x6 0x0
+#define MX6QDL_PAD_GPIO_5__ESAI_TX2_RX3             0x23c 0x60c 0x87c 0x0 0x1
+#define MX6QDL_PAD_GPIO_5__KEY_ROW7                 0x23c 0x60c 0x8fc 0x2 0x1
+#define MX6QDL_PAD_GPIO_5__CCM_CLKO1                0x23c 0x60c 0x000 0x3 0x0
+#define MX6QDL_PAD_GPIO_5__GPIO1_IO05               0x23c 0x60c 0x000 0x5 0x0
+#define MX6QDL_PAD_GPIO_5__I2C3_SCL                 0x23c 0x60c 0x8a8 0x6 0x2
+#define MX6QDL_PAD_GPIO_5__ARM_EVENTI               0x23c 0x60c 0x000 0x7 0x0
+#define MX6QDL_PAD_GPIO_7__ESAI_TX4_RX1             0x240 0x610 0x884 0x0 0x1
+#define MX6QDL_PAD_GPIO_7__ECSPI5_RDY               0x240 0x610 0x000 0x1 0x0
+#define MX6QDL_PAD_GPIO_7__EPIT1_OUT                0x240 0x610 0x000 0x2 0x0
+#define MX6QDL_PAD_GPIO_7__FLEXCAN1_TX              0x240 0x610 0x000 0x3 0x0
+#define MX6QDL_PAD_GPIO_7__UART2_TX_DATA            0x240 0x610 0x000 0x4 0x0
+#define MX6QDL_PAD_GPIO_7__UART2_RX_DATA            0x240 0x610 0x928 0x4 0x2
+#define MX6QDL_PAD_GPIO_7__GPIO1_IO07               0x240 0x610 0x000 0x5 0x0
+#define MX6QDL_PAD_GPIO_7__SPDIF_LOCK               0x240 0x610 0x000 0x6 0x0
+#define MX6QDL_PAD_GPIO_7__USB_OTG_HOST_MODE        0x240 0x610 0x000 0x7 0x0
+#define MX6QDL_PAD_GPIO_8__ESAI_TX5_RX0             0x244 0x614 0x888 0x0 0x1
+#define MX6QDL_PAD_GPIO_8__XTALOSC_REF_CLK_32K      0x244 0x614 0x000 0x1 0x0
+#define MX6QDL_PAD_GPIO_8__EPIT2_OUT                0x244 0x614 0x000 0x2 0x0
+#define MX6QDL_PAD_GPIO_8__FLEXCAN1_RX              0x244 0x614 0x7e4 0x3 0x1
+#define MX6QDL_PAD_GPIO_8__UART2_RX_DATA            0x244 0x614 0x928 0x4 0x3
+#define MX6QDL_PAD_GPIO_8__UART2_TX_DATA            0x244 0x614 0x000 0x4 0x0
+#define MX6QDL_PAD_GPIO_8__GPIO1_IO08               0x244 0x614 0x000 0x5 0x0
+#define MX6QDL_PAD_GPIO_8__SPDIF_SR_CLK             0x244 0x614 0x000 0x6 0x0
+#define MX6QDL_PAD_GPIO_8__USB_OTG_PWR_CTL_WAKE     0x244 0x614 0x000 0x7 0x0
+#define MX6QDL_PAD_GPIO_16__ESAI_TX3_RX2            0x248 0x618 0x880 0x0 0x1
+#define MX6QDL_PAD_GPIO_16__ENET_1588_EVENT2_IN     0x248 0x618 0x000 0x1 0x0
+#define MX6QDL_PAD_GPIO_16__ENET_REF_CLK            0x248 0x618 0x83c 0x2 0x1
+#define MX6QDL_PAD_GPIO_16__SD1_LCTL                0x248 0x618 0x000 0x3 0x0
+#define MX6QDL_PAD_GPIO_16__SPDIF_IN                0x248 0x618 0x914 0x4 0x3
+#define MX6QDL_PAD_GPIO_16__GPIO7_IO11              0x248 0x618 0x000 0x5 0x0
+#define MX6QDL_PAD_GPIO_16__I2C3_SDA                0x248 0x618 0x8ac 0x6 0x2
+#define MX6QDL_PAD_GPIO_16__JTAG_DE_B               0x248 0x618 0x000 0x7 0x0
+#define MX6QDL_PAD_GPIO_17__ESAI_TX0                0x24c 0x61c 0x874 0x0 0x0
+#define MX6QDL_PAD_GPIO_17__ENET_1588_EVENT3_IN     0x24c 0x61c 0x000 0x1 0x0
+#define MX6QDL_PAD_GPIO_17__CCM_PMIC_READY          0x24c 0x61c 0x7f0 0x2 0x1
+#define MX6QDL_PAD_GPIO_17__SDMA_EXT_EVENT0         0x24c 0x61c 0x90c 0x3 0x1
+#define MX6QDL_PAD_GPIO_17__SPDIF_OUT               0x24c 0x61c 0x000 0x4 0x0
+#define MX6QDL_PAD_GPIO_17__GPIO7_IO12              0x24c 0x61c 0x000 0x5 0x0
+#define MX6QDL_PAD_GPIO_18__ESAI_TX1                0x250 0x620 0x878 0x0 0x0
+#define MX6QDL_PAD_GPIO_18__ENET_RX_CLK             0x250 0x620 0x844 0x1 0x1
+#define MX6QDL_PAD_GPIO_18__SD3_VSELECT             0x250 0x620 0x000 0x2 0x0
+#define MX6QDL_PAD_GPIO_18__SDMA_EXT_EVENT1         0x250 0x620 0x910 0x3 0x1
+#define MX6QDL_PAD_GPIO_18__ASRC_EXT_CLK            0x250 0x620 0x7b0 0x4 0x2
+#define MX6QDL_PAD_GPIO_18__GPIO7_IO13              0x250 0x620 0x000 0x5 0x0
+#define MX6QDL_PAD_GPIO_18__SNVS_VIO_5_CTL          0x250 0x620 0x000 0x6 0x0
+#define MX6QDL_PAD_GPIO_19__KEY_COL5                0x254 0x624 0x8e8 0x0 0x1
+#define MX6QDL_PAD_GPIO_19__ENET_1588_EVENT0_OUT    0x254 0x624 0x000 0x1 0x0
+#define MX6QDL_PAD_GPIO_19__SPDIF_OUT               0x254 0x624 0x000 0x2 0x0
+#define MX6QDL_PAD_GPIO_19__CCM_CLKO1               0x254 0x624 0x000 0x3 0x0
+#define MX6QDL_PAD_GPIO_19__ECSPI1_RDY              0x254 0x624 0x000 0x4 0x0
+#define MX6QDL_PAD_GPIO_19__GPIO4_IO05              0x254 0x624 0x000 0x5 0x0
+#define MX6QDL_PAD_GPIO_19__ENET_TX_ER              0x254 0x624 0x000 0x6 0x0
+#define MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK    0x258 0x628 0x000 0x0 0x0
+#define MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18          0x258 0x628 0x000 0x5 0x0
+#define MX6QDL_PAD_CSI0_PIXCLK__ARM_EVENTO          0x258 0x628 0x000 0x7 0x0
+#define MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC       0x25c 0x62c 0x000 0x0 0x0
+#define MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1             0x25c 0x62c 0x000 0x3 0x0
+#define MX6QDL_PAD_CSI0_MCLK__GPIO5_IO19            0x25c 0x62c 0x000 0x5 0x0
+#define MX6QDL_PAD_CSI0_MCLK__ARM_TRACE_CTL         0x25c 0x62c 0x000 0x7 0x0
+#define MX6QDL_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN  0x260 0x630 0x000 0x0 0x0
+#define MX6QDL_PAD_CSI0_DATA_EN__EIM_DATA00         0x260 0x630 0x000 0x1 0x0
+#define MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20         0x260 0x630 0x000 0x5 0x0
+#define MX6QDL_PAD_CSI0_DATA_EN__ARM_TRACE_CLK      0x260 0x630 0x000 0x7 0x0
+#define MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC      0x264 0x634 0x000 0x0 0x0
+#define MX6QDL_PAD_CSI0_VSYNC__EIM_DATA01           0x264 0x634 0x000 0x1 0x0
+#define MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21           0x264 0x634 0x000 0x5 0x0
+#define MX6QDL_PAD_CSI0_VSYNC__ARM_TRACE00          0x264 0x634 0x000 0x7 0x0
+#define MX6QDL_PAD_CSI0_DAT4__IPU1_CSI0_DATA04      0x268 0x638 0x000 0x0 0x0
+#define MX6QDL_PAD_CSI0_DAT4__EIM_DATA02            0x268 0x638 0x000 0x1 0x0
+#define MX6QDL_PAD_CSI0_DAT4__ECSPI1_SCLK           0x268 0x638 0x7f4 0x2 0x3
+#define MX6QDL_PAD_CSI0_DAT4__KEY_COL5              0x268 0x638 0x8e8 0x3 0x2
+#define MX6QDL_PAD_CSI0_DAT4__AUD3_TXC              0x268 0x638 0x000 0x4 0x0
+#define MX6QDL_PAD_CSI0_DAT4__GPIO5_IO22            0x268 0x638 0x000 0x5 0x0
+#define MX6QDL_PAD_CSI0_DAT4__ARM_TRACE01           0x268 0x638 0x000 0x7 0x0
+#define MX6QDL_PAD_CSI0_DAT5__IPU1_CSI0_DATA05      0x26c 0x63c 0x000 0x0 0x0
+#define MX6QDL_PAD_CSI0_DAT5__EIM_DATA03            0x26c 0x63c 0x000 0x1 0x0
+#define MX6QDL_PAD_CSI0_DAT5__ECSPI1_MOSI           0x26c 0x63c 0x7fc 0x2 0x3
+#define MX6QDL_PAD_CSI0_DAT5__KEY_ROW5              0x26c 0x63c 0x8f4 0x3 0x1
+#define MX6QDL_PAD_CSI0_DAT5__AUD3_TXD              0x26c 0x63c 0x000 0x4 0x0
+#define MX6QDL_PAD_CSI0_DAT5__GPIO5_IO23            0x26c 0x63c 0x000 0x5 0x0
+#define MX6QDL_PAD_CSI0_DAT5__ARM_TRACE02           0x26c 0x63c 0x000 0x7 0x0
+#define MX6QDL_PAD_CSI0_DAT6__IPU1_CSI0_DATA06      0x270 0x640 0x000 0x0 0x0
+#define MX6QDL_PAD_CSI0_DAT6__EIM_DATA04            0x270 0x640 0x000 0x1 0x0
+#define MX6QDL_PAD_CSI0_DAT6__ECSPI1_MISO           0x270 0x640 0x7f8 0x2 0x3
+#define MX6QDL_PAD_CSI0_DAT6__KEY_COL6              0x270 0x640 0x8ec 0x3 0x1
+#define MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS             0x270 0x640 0x000 0x4 0x0
+#define MX6QDL_PAD_CSI0_DAT6__GPIO5_IO24            0x270 0x640 0x000 0x5 0x0
+#define MX6QDL_PAD_CSI0_DAT6__ARM_TRACE03           0x270 0x640 0x000 0x7 0x0
+#define MX6QDL_PAD_CSI0_DAT7__IPU1_CSI0_DATA07      0x274 0x644 0x000 0x0 0x0
+#define MX6QDL_PAD_CSI0_DAT7__EIM_DATA05            0x274 0x644 0x000 0x1 0x0
+#define MX6QDL_PAD_CSI0_DAT7__ECSPI1_SS0            0x274 0x644 0x800 0x2 0x3
+#define MX6QDL_PAD_CSI0_DAT7__KEY_ROW6              0x274 0x644 0x8f8 0x3 0x2
+#define MX6QDL_PAD_CSI0_DAT7__AUD3_RXD              0x274 0x644 0x000 0x4 0x0
+#define MX6QDL_PAD_CSI0_DAT7__GPIO5_IO25            0x274 0x644 0x000 0x5 0x0
+#define MX6QDL_PAD_CSI0_DAT7__ARM_TRACE04           0x274 0x644 0x000 0x7 0x0
+#define MX6QDL_PAD_CSI0_DAT8__IPU1_CSI0_DATA08      0x278 0x648 0x000 0x0 0x0
+#define MX6QDL_PAD_CSI0_DAT8__EIM_DATA06            0x278 0x648 0x000 0x1 0x0
+#define MX6QDL_PAD_CSI0_DAT8__ECSPI2_SCLK           0x278 0x648 0x810 0x2 0x2
+#define MX6QDL_PAD_CSI0_DAT8__KEY_COL7              0x278 0x648 0x8f0 0x3 0x2
+#define MX6QDL_PAD_CSI0_DAT8__I2C1_SDA              0x278 0x648 0x89c 0x4 0x1
+#define MX6QDL_PAD_CSI0_DAT8__GPIO5_IO26            0x278 0x648 0x000 0x5 0x0
+#define MX6QDL_PAD_CSI0_DAT8__ARM_TRACE05           0x278 0x648 0x000 0x7 0x0
+#define MX6QDL_PAD_CSI0_DAT9__IPU1_CSI0_DATA09      0x27c 0x64c 0x000 0x0 0x0
+#define MX6QDL_PAD_CSI0_DAT9__EIM_DATA07            0x27c 0x64c 0x000 0x1 0x0
+#define MX6QDL_PAD_CSI0_DAT9__ECSPI2_MOSI           0x27c 0x64c 0x818 0x2 0x2
+#define MX6QDL_PAD_CSI0_DAT9__KEY_ROW7              0x27c 0x64c 0x8fc 0x3 0x2
+#define MX6QDL_PAD_CSI0_DAT9__I2C1_SCL              0x27c 0x64c 0x898 0x4 0x1
+#define MX6QDL_PAD_CSI0_DAT9__GPIO5_IO27            0x27c 0x64c 0x000 0x5 0x0
+#define MX6QDL_PAD_CSI0_DAT9__ARM_TRACE06           0x27c 0x64c 0x000 0x7 0x0
+#define MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10     0x280 0x650 0x000 0x0 0x0
+#define MX6QDL_PAD_CSI0_DAT10__AUD3_RXC             0x280 0x650 0x000 0x1 0x0
+#define MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO          0x280 0x650 0x814 0x2 0x2
+#define MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA        0x280 0x650 0x000 0x3 0x0
+#define MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA        0x280 0x650 0x920 0x3 0x0
+#define MX6QDL_PAD_CSI0_DAT10__GPIO5_IO28           0x280 0x650 0x000 0x5 0x0
+#define MX6QDL_PAD_CSI0_DAT10__ARM_TRACE07          0x280 0x650 0x000 0x7 0x0
+#define MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11     0x284 0x654 0x000 0x0 0x0
+#define MX6QDL_PAD_CSI0_DAT11__AUD3_RXFS            0x284 0x654 0x000 0x1 0x0
+#define MX6QDL_PAD_CSI0_DAT11__ECSPI2_SS0           0x284 0x654 0x81c 0x2 0x2
+#define MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA        0x284 0x654 0x920 0x3 0x1
+#define MX6QDL_PAD_CSI0_DAT11__UART1_TX_DATA        0x284 0x654 0x000 0x3 0x0
+#define MX6QDL_PAD_CSI0_DAT11__GPIO5_IO29           0x284 0x654 0x000 0x5 0x0
+#define MX6QDL_PAD_CSI0_DAT11__ARM_TRACE08          0x284 0x654 0x000 0x7 0x0
+#define MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12     0x288 0x658 0x000 0x0 0x0
+#define MX6QDL_PAD_CSI0_DAT12__EIM_DATA08           0x288 0x658 0x000 0x1 0x0
+#define MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA        0x288 0x658 0x000 0x3 0x0
+#define MX6QDL_PAD_CSI0_DAT12__UART4_RX_DATA        0x288 0x658 0x938 0x3 0x2
+#define MX6QDL_PAD_CSI0_DAT12__GPIO5_IO30           0x288 0x658 0x000 0x5 0x0
+#define MX6QDL_PAD_CSI0_DAT12__ARM_TRACE09          0x288 0x658 0x000 0x7 0x0
+#define MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13     0x28c 0x65c 0x000 0x0 0x0
+#define MX6QDL_PAD_CSI0_DAT13__EIM_DATA09           0x28c 0x65c 0x000 0x1 0x0
+#define MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA        0x28c 0x65c 0x938 0x3 0x3
+#define MX6QDL_PAD_CSI0_DAT13__UART4_TX_DATA        0x28c 0x65c 0x000 0x3 0x0
+#define MX6QDL_PAD_CSI0_DAT13__GPIO5_IO31           0x28c 0x65c 0x000 0x5 0x0
+#define MX6QDL_PAD_CSI0_DAT13__ARM_TRACE10          0x28c 0x65c 0x000 0x7 0x0
+#define MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14     0x290 0x660 0x000 0x0 0x0
+#define MX6QDL_PAD_CSI0_DAT14__EIM_DATA10           0x290 0x660 0x000 0x1 0x0
+#define MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA        0x290 0x660 0x000 0x3 0x0
+#define MX6QDL_PAD_CSI0_DAT14__UART5_RX_DATA        0x290 0x660 0x940 0x3 0x2
+#define MX6QDL_PAD_CSI0_DAT14__GPIO6_IO00           0x290 0x660 0x000 0x5 0x0
+#define MX6QDL_PAD_CSI0_DAT14__ARM_TRACE11          0x290 0x660 0x000 0x7 0x0
+#define MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15     0x294 0x664 0x000 0x0 0x0
+#define MX6QDL_PAD_CSI0_DAT15__EIM_DATA11           0x294 0x664 0x000 0x1 0x0
+#define MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA        0x294 0x664 0x940 0x3 0x3
+#define MX6QDL_PAD_CSI0_DAT15__UART5_TX_DATA        0x294 0x664 0x000 0x3 0x0
+#define MX6QDL_PAD_CSI0_DAT15__GPIO6_IO01           0x294 0x664 0x000 0x5 0x0
+#define MX6QDL_PAD_CSI0_DAT15__ARM_TRACE12          0x294 0x664 0x000 0x7 0x0
+#define MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16     0x298 0x668 0x000 0x0 0x0
+#define MX6QDL_PAD_CSI0_DAT16__EIM_DATA12           0x298 0x668 0x000 0x1 0x0
+#define MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B          0x298 0x668 0x934 0x3 0x0
+#define MX6QDL_PAD_CSI0_DAT16__UART4_CTS_B          0x298 0x668 0x000 0x3 0x0
+#define MX6QDL_PAD_CSI0_DAT16__GPIO6_IO02           0x298 0x668 0x000 0x5 0x0
+#define MX6QDL_PAD_CSI0_DAT16__ARM_TRACE13          0x298 0x668 0x000 0x7 0x0
+#define MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17     0x29c 0x66c 0x000 0x0 0x0
+#define MX6QDL_PAD_CSI0_DAT17__EIM_DATA13           0x29c 0x66c 0x000 0x1 0x0
+#define MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B          0x29c 0x66c 0x000 0x3 0x0
+#define MX6QDL_PAD_CSI0_DAT17__UART4_RTS_B          0x29c 0x66c 0x934 0x3 0x1
+#define MX6QDL_PAD_CSI0_DAT17__GPIO6_IO03           0x29c 0x66c 0x000 0x5 0x0
+#define MX6QDL_PAD_CSI0_DAT17__ARM_TRACE14          0x29c 0x66c 0x000 0x7 0x0
+#define MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18     0x2a0 0x670 0x000 0x0 0x0
+#define MX6QDL_PAD_CSI0_DAT18__EIM_DATA14           0x2a0 0x670 0x000 0x1 0x0
+#define MX6QDL_PAD_CSI0_DAT18__UART5_RTS_B          0x2a0 0x670 0x93c 0x3 0x2
+#define MX6QDL_PAD_CSI0_DAT18__UART5_CTS_B          0x2a0 0x670 0x000 0x3 0x0
+#define MX6QDL_PAD_CSI0_DAT18__GPIO6_IO04           0x2a0 0x670 0x000 0x5 0x0
+#define MX6QDL_PAD_CSI0_DAT18__ARM_TRACE15          0x2a0 0x670 0x000 0x7 0x0
+#define MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19     0x2a4 0x674 0x000 0x0 0x0
+#define MX6QDL_PAD_CSI0_DAT19__EIM_DATA15           0x2a4 0x674 0x000 0x1 0x0
+#define MX6QDL_PAD_CSI0_DAT19__UART5_CTS_B          0x2a4 0x674 0x000 0x3 0x0
+#define MX6QDL_PAD_CSI0_DAT19__UART5_RTS_B          0x2a4 0x674 0x93c 0x3 0x3
+#define MX6QDL_PAD_CSI0_DAT19__GPIO6_IO05           0x2a4 0x674 0x000 0x5 0x0
+#define MX6QDL_PAD_SD3_DAT7__SD3_DATA7              0x2a8 0x690 0x000 0x0 0x0
+#define MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA          0x2a8 0x690 0x000 0x1 0x0
+#define MX6QDL_PAD_SD3_DAT7__UART1_RX_DATA          0x2a8 0x690 0x920 0x1 0x2
+#define MX6QDL_PAD_SD3_DAT7__GPIO6_IO17             0x2a8 0x690 0x000 0x5 0x0
+#define MX6QDL_PAD_SD3_DAT6__SD3_DATA6              0x2ac 0x694 0x000 0x0 0x0
+#define MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA          0x2ac 0x694 0x920 0x1 0x3
+#define MX6QDL_PAD_SD3_DAT6__UART1_TX_DATA          0x2ac 0x694 0x000 0x1 0x0
+#define MX6QDL_PAD_SD3_DAT6__GPIO6_IO18             0x2ac 0x694 0x000 0x5 0x0
+#define MX6QDL_PAD_SD3_DAT5__SD3_DATA5              0x2b0 0x698 0x000 0x0 0x0
+#define MX6QDL_PAD_SD3_DAT5__UART2_TX_DATA          0x2b0 0x698 0x000 0x1 0x0
+#define MX6QDL_PAD_SD3_DAT5__UART2_RX_DATA          0x2b0 0x698 0x928 0x1 0x4
+#define MX6QDL_PAD_SD3_DAT5__GPIO7_IO00             0x2b0 0x698 0x000 0x5 0x0
+#define MX6QDL_PAD_SD3_DAT4__SD3_DATA4              0x2b4 0x69c 0x000 0x0 0x0
+#define MX6QDL_PAD_SD3_DAT4__UART2_RX_DATA          0x2b4 0x69c 0x928 0x1 0x5
+#define MX6QDL_PAD_SD3_DAT4__UART2_TX_DATA          0x2b4 0x69c 0x000 0x1 0x0
+#define MX6QDL_PAD_SD3_DAT4__GPIO7_IO01             0x2b4 0x69c 0x000 0x5 0x0
+#define MX6QDL_PAD_SD3_CMD__SD3_CMD                 0x2b8 0x6a0 0x000 0x0 0x0
+#define MX6QDL_PAD_SD3_CMD__UART2_CTS_B             0x2b8 0x6a0 0x000 0x1 0x0
+#define MX6QDL_PAD_SD3_CMD__UART2_RTS_B             0x2b8 0x6a0 0x924 0x1 0x2
+#define MX6QDL_PAD_SD3_CMD__FLEXCAN1_TX             0x2b8 0x6a0 0x000 0x2 0x0
+#define MX6QDL_PAD_SD3_CMD__GPIO7_IO02              0x2b8 0x6a0 0x000 0x5 0x0
+#define MX6QDL_PAD_SD3_CLK__SD3_CLK                 0x2bc 0x6a4 0x000 0x0 0x0
+#define MX6QDL_PAD_SD3_CLK__UART2_RTS_B             0x2bc 0x6a4 0x924 0x1 0x3
+#define MX6QDL_PAD_SD3_CLK__UART2_CTS_B             0x2bc 0x6a4 0x000 0x1 0x0
+#define MX6QDL_PAD_SD3_CLK__FLEXCAN1_RX             0x2bc 0x6a4 0x7e4 0x2 0x2
+#define MX6QDL_PAD_SD3_CLK__GPIO7_IO03              0x2bc 0x6a4 0x000 0x5 0x0
+#define MX6QDL_PAD_SD3_DAT0__SD3_DATA0              0x2c0 0x6a8 0x000 0x0 0x0
+#define MX6QDL_PAD_SD3_DAT0__UART1_CTS_B            0x2c0 0x6a8 0x000 0x1 0x0
+#define MX6QDL_PAD_SD3_DAT0__UART1_RTS_B            0x2c0 0x6a8 0x91c 0x1 0x2
+#define MX6QDL_PAD_SD3_DAT0__FLEXCAN2_TX            0x2c0 0x6a8 0x000 0x2 0x0
+#define MX6QDL_PAD_SD3_DAT0__GPIO7_IO04             0x2c0 0x6a8 0x000 0x5 0x0
+#define MX6QDL_PAD_SD3_DAT1__SD3_DATA1              0x2c4 0x6ac 0x000 0x0 0x0
+#define MX6QDL_PAD_SD3_DAT1__UART1_RTS_B            0x2c4 0x6ac 0x91c 0x1 0x3
+#define MX6QDL_PAD_SD3_DAT1__UART1_CTS_B            0x2c4 0x6ac 0x000 0x1 0x0
+#define MX6QDL_PAD_SD3_DAT1__FLEXCAN2_RX            0x2c4 0x6ac 0x7e8 0x2 0x1
+#define MX6QDL_PAD_SD3_DAT1__GPIO7_IO05             0x2c4 0x6ac 0x000 0x5 0x0
+#define MX6QDL_PAD_SD3_DAT2__SD3_DATA2              0x2c8 0x6b0 0x000 0x0 0x0
+#define MX6QDL_PAD_SD3_DAT2__GPIO7_IO06             0x2c8 0x6b0 0x000 0x5 0x0
+#define MX6QDL_PAD_SD3_DAT3__SD3_DATA3              0x2cc 0x6b4 0x000 0x0 0x0
+#define MX6QDL_PAD_SD3_DAT3__UART3_CTS_B            0x2cc 0x6b4 0x000 0x1 0x0
+#define MX6QDL_PAD_SD3_DAT3__UART3_RTS_B            0x2cc 0x6b4 0x92c 0x1 0x4
+#define MX6QDL_PAD_SD3_DAT3__GPIO7_IO07             0x2cc 0x6b4 0x000 0x5 0x0
+#define MX6QDL_PAD_SD3_RST__SD3_RESET               0x2d0 0x6b8 0x000 0x0 0x0
+#define MX6QDL_PAD_SD3_RST__UART3_RTS_B             0x2d0 0x6b8 0x92c 0x1 0x5
+#define MX6QDL_PAD_SD3_RST__UART3_CTS_B             0x2d0 0x6b8 0x000 0x1 0x0
+#define MX6QDL_PAD_SD3_RST__GPIO7_IO08              0x2d0 0x6b8 0x000 0x5 0x0
+#define MX6QDL_PAD_NANDF_CLE__NAND_CLE              0x2d4 0x6bc 0x000 0x0 0x0
+#define MX6QDL_PAD_NANDF_CLE__IPU2_SISG4            0x2d4 0x6bc 0x000 0x1 0x0
+#define MX6QDL_PAD_NANDF_CLE__GPIO6_IO07            0x2d4 0x6bc 0x000 0x5 0x0
+#define MX6QDL_PAD_NANDF_ALE__NAND_ALE              0x2d8 0x6c0 0x000 0x0 0x0
+#define MX6QDL_PAD_NANDF_ALE__SD4_RESET             0x2d8 0x6c0 0x000 0x1 0x0
+#define MX6QDL_PAD_NANDF_ALE__GPIO6_IO08            0x2d8 0x6c0 0x000 0x5 0x0
+#define MX6QDL_PAD_NANDF_WP_B__NAND_WP_B            0x2dc 0x6c4 0x000 0x0 0x0
+#define MX6QDL_PAD_NANDF_WP_B__IPU2_SISG5           0x2dc 0x6c4 0x000 0x1 0x0
+#define MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09           0x2dc 0x6c4 0x000 0x5 0x0
+#define MX6QDL_PAD_NANDF_RB0__NAND_READY_B          0x2e0 0x6c8 0x000 0x0 0x0
+#define MX6QDL_PAD_NANDF_RB0__IPU2_DI0_PIN01        0x2e0 0x6c8 0x000 0x1 0x0
+#define MX6QDL_PAD_NANDF_RB0__GPIO6_IO10            0x2e0 0x6c8 0x000 0x5 0x0
+#define MX6QDL_PAD_NANDF_CS0__NAND_CE0_B            0x2e4 0x6cc 0x000 0x0 0x0
+#define MX6QDL_PAD_NANDF_CS0__GPIO6_IO11            0x2e4 0x6cc 0x000 0x5 0x0
+#define MX6QDL_PAD_NANDF_CS1__NAND_CE1_B            0x2e8 0x6d0 0x000 0x0 0x0
+#define MX6QDL_PAD_NANDF_CS1__SD4_VSELECT           0x2e8 0x6d0 0x000 0x1 0x0
+#define MX6QDL_PAD_NANDF_CS1__SD3_VSELECT           0x2e8 0x6d0 0x000 0x2 0x0
+#define MX6QDL_PAD_NANDF_CS1__GPIO6_IO14            0x2e8 0x6d0 0x000 0x5 0x0
+#define MX6QDL_PAD_NANDF_CS2__NAND_CE2_B            0x2ec 0x6d4 0x000 0x0 0x0
+#define MX6QDL_PAD_NANDF_CS2__IPU1_SISG0            0x2ec 0x6d4 0x000 0x1 0x0
+#define MX6QDL_PAD_NANDF_CS2__ESAI_TX0              0x2ec 0x6d4 0x874 0x2 0x1
+#define MX6QDL_PAD_NANDF_CS2__EIM_CRE               0x2ec 0x6d4 0x000 0x3 0x0
+#define MX6QDL_PAD_NANDF_CS2__CCM_CLKO2             0x2ec 0x6d4 0x000 0x4 0x0
+#define MX6QDL_PAD_NANDF_CS2__GPIO6_IO15            0x2ec 0x6d4 0x000 0x5 0x0
+#define MX6QDL_PAD_NANDF_CS2__IPU2_SISG0            0x2ec 0x6d4 0x000 0x6 0x0
+#define MX6QDL_PAD_NANDF_CS3__NAND_CE3_B            0x2f0 0x6d8 0x000 0x0 0x0
+#define MX6QDL_PAD_NANDF_CS3__IPU1_SISG1            0x2f0 0x6d8 0x000 0x1 0x0
+#define MX6QDL_PAD_NANDF_CS3__ESAI_TX1              0x2f0 0x6d8 0x878 0x2 0x1
+#define MX6QDL_PAD_NANDF_CS3__EIM_ADDR26            0x2f0 0x6d8 0x000 0x3 0x0
+#define MX6QDL_PAD_NANDF_CS3__GPIO6_IO16            0x2f0 0x6d8 0x000 0x5 0x0
+#define MX6QDL_PAD_NANDF_CS3__IPU2_SISG1            0x2f0 0x6d8 0x000 0x6 0x0
+#define MX6QDL_PAD_SD4_CMD__SD4_CMD                 0x2f4 0x6dc 0x000 0x0 0x0
+#define MX6QDL_PAD_SD4_CMD__NAND_RE_B               0x2f4 0x6dc 0x000 0x1 0x0
+#define MX6QDL_PAD_SD4_CMD__UART3_TX_DATA           0x2f4 0x6dc 0x000 0x2 0x0
+#define MX6QDL_PAD_SD4_CMD__UART3_RX_DATA           0x2f4 0x6dc 0x930 0x2 0x2
+#define MX6QDL_PAD_SD4_CMD__GPIO7_IO09              0x2f4 0x6dc 0x000 0x5 0x0
+#define MX6QDL_PAD_SD4_CLK__SD4_CLK                 0x2f8 0x6e0 0x000 0x0 0x0
+#define MX6QDL_PAD_SD4_CLK__NAND_WE_B               0x2f8 0x6e0 0x000 0x1 0x0
+#define MX6QDL_PAD_SD4_CLK__UART3_RX_DATA           0x2f8 0x6e0 0x930 0x2 0x3
+#define MX6QDL_PAD_SD4_CLK__UART3_TX_DATA           0x2f8 0x6e0 0x000 0x2 0x0
+#define MX6QDL_PAD_SD4_CLK__GPIO7_IO10              0x2f8 0x6e0 0x000 0x5 0x0
+#define MX6QDL_PAD_NANDF_D0__NAND_DATA00            0x2fc 0x6e4 0x000 0x0 0x0
+#define MX6QDL_PAD_NANDF_D0__SD1_DATA4              0x2fc 0x6e4 0x000 0x1 0x0
+#define MX6QDL_PAD_NANDF_D0__GPIO2_IO00             0x2fc 0x6e4 0x000 0x5 0x0
+#define MX6QDL_PAD_NANDF_D1__NAND_DATA01            0x300 0x6e8 0x000 0x0 0x0
+#define MX6QDL_PAD_NANDF_D1__SD1_DATA5              0x300 0x6e8 0x000 0x1 0x0
+#define MX6QDL_PAD_NANDF_D1__GPIO2_IO01             0x300 0x6e8 0x000 0x5 0x0
+#define MX6QDL_PAD_NANDF_D2__NAND_DATA02            0x304 0x6ec 0x000 0x0 0x0
+#define MX6QDL_PAD_NANDF_D2__SD1_DATA6              0x304 0x6ec 0x000 0x1 0x0
+#define MX6QDL_PAD_NANDF_D2__GPIO2_IO02             0x304 0x6ec 0x000 0x5 0x0
+#define MX6QDL_PAD_NANDF_D3__NAND_DATA03            0x308 0x6f0 0x000 0x0 0x0
+#define MX6QDL_PAD_NANDF_D3__SD1_DATA7              0x308 0x6f0 0x000 0x1 0x0
+#define MX6QDL_PAD_NANDF_D3__GPIO2_IO03             0x308 0x6f0 0x000 0x5 0x0
+#define MX6QDL_PAD_NANDF_D4__NAND_DATA04            0x30c 0x6f4 0x000 0x0 0x0
+#define MX6QDL_PAD_NANDF_D4__SD2_DATA4              0x30c 0x6f4 0x000 0x1 0x0
+#define MX6QDL_PAD_NANDF_D4__GPIO2_IO04             0x30c 0x6f4 0x000 0x5 0x0
+#define MX6QDL_PAD_NANDF_D5__NAND_DATA05            0x310 0x6f8 0x000 0x0 0x0
+#define MX6QDL_PAD_NANDF_D5__SD2_DATA5              0x310 0x6f8 0x000 0x1 0x0
+#define MX6QDL_PAD_NANDF_D5__GPIO2_IO05             0x310 0x6f8 0x000 0x5 0x0
+#define MX6QDL_PAD_NANDF_D6__NAND_DATA06            0x314 0x6fc 0x000 0x0 0x0
+#define MX6QDL_PAD_NANDF_D6__SD2_DATA6              0x314 0x6fc 0x000 0x1 0x0
+#define MX6QDL_PAD_NANDF_D6__GPIO2_IO06             0x314 0x6fc 0x000 0x5 0x0
+#define MX6QDL_PAD_NANDF_D7__NAND_DATA07            0x318 0x700 0x000 0x0 0x0
+#define MX6QDL_PAD_NANDF_D7__SD2_DATA7              0x318 0x700 0x000 0x1 0x0
+#define MX6QDL_PAD_NANDF_D7__GPIO2_IO07             0x318 0x700 0x000 0x5 0x0
+#define MX6QDL_PAD_SD4_DAT0__SD4_DATA0              0x31c 0x704 0x000 0x1 0x0
+#define MX6QDL_PAD_SD4_DAT0__NAND_DQS               0x31c 0x704 0x000 0x2 0x0
+#define MX6QDL_PAD_SD4_DAT0__GPIO2_IO08             0x31c 0x704 0x000 0x5 0x0
+#define MX6QDL_PAD_SD4_DAT1__SD4_DATA1              0x320 0x708 0x000 0x1 0x0
+#define MX6QDL_PAD_SD4_DAT1__PWM3_OUT               0x320 0x708 0x000 0x2 0x0
+#define MX6QDL_PAD_SD4_DAT1__GPIO2_IO09             0x320 0x708 0x000 0x5 0x0
+#define MX6QDL_PAD_SD4_DAT2__SD4_DATA2              0x324 0x70c 0x000 0x1 0x0
+#define MX6QDL_PAD_SD4_DAT2__PWM4_OUT               0x324 0x70c 0x000 0x2 0x0
+#define MX6QDL_PAD_SD4_DAT2__GPIO2_IO10             0x324 0x70c 0x000 0x5 0x0
+#define MX6QDL_PAD_SD4_DAT3__SD4_DATA3              0x328 0x710 0x000 0x1 0x0
+#define MX6QDL_PAD_SD4_DAT3__GPIO2_IO11             0x328 0x710 0x000 0x5 0x0
+#define MX6QDL_PAD_SD4_DAT4__SD4_DATA4              0x32c 0x714 0x000 0x1 0x0
+#define MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA          0x32c 0x714 0x928 0x2 0x6
+#define MX6QDL_PAD_SD4_DAT4__UART2_TX_DATA          0x32c 0x714 0x000 0x2 0x0
+#define MX6QDL_PAD_SD4_DAT4__GPIO2_IO12             0x32c 0x714 0x000 0x5 0x0
+#define MX6QDL_PAD_SD4_DAT5__SD4_DATA5              0x330 0x718 0x000 0x1 0x0
+#define MX6QDL_PAD_SD4_DAT5__UART2_RTS_B            0x330 0x718 0x924 0x2 0x4
+#define MX6QDL_PAD_SD4_DAT5__UART2_CTS_B            0x330 0x718 0x000 0x2 0x0
+#define MX6QDL_PAD_SD4_DAT5__GPIO2_IO13             0x330 0x718 0x000 0x5 0x0
+#define MX6QDL_PAD_SD4_DAT6__SD4_DATA6              0x334 0x71c 0x000 0x1 0x0
+#define MX6QDL_PAD_SD4_DAT6__UART2_CTS_B            0x334 0x71c 0x000 0x2 0x0
+#define MX6QDL_PAD_SD4_DAT6__UART2_RTS_B            0x334 0x71c 0x924 0x2 0x5
+#define MX6QDL_PAD_SD4_DAT6__GPIO2_IO14             0x334 0x71c 0x000 0x5 0x0
+#define MX6QDL_PAD_SD4_DAT7__SD4_DATA7              0x338 0x720 0x000 0x1 0x0
+#define MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA          0x338 0x720 0x000 0x2 0x0
+#define MX6QDL_PAD_SD4_DAT7__UART2_RX_DATA          0x338 0x720 0x928 0x2 0x7
+#define MX6QDL_PAD_SD4_DAT7__GPIO2_IO15             0x338 0x720 0x000 0x5 0x0
+#define MX6QDL_PAD_SD1_DAT1__SD1_DATA1              0x33c 0x724 0x000 0x0 0x0
+#define MX6QDL_PAD_SD1_DAT1__ECSPI5_SS0             0x33c 0x724 0x834 0x1 0x1
+#define MX6QDL_PAD_SD1_DAT1__PWM3_OUT               0x33c 0x724 0x000 0x2 0x0
+#define MX6QDL_PAD_SD1_DAT1__GPT_CAPTURE2           0x33c 0x724 0x000 0x3 0x0
+#define MX6QDL_PAD_SD1_DAT1__GPIO1_IO17             0x33c 0x724 0x000 0x5 0x0
+#define MX6QDL_PAD_SD1_DAT0__SD1_DATA0              0x340 0x728 0x000 0x0 0x0
+#define MX6QDL_PAD_SD1_DAT0__ECSPI5_MISO            0x340 0x728 0x82c 0x1 0x1
+#define MX6QDL_PAD_SD1_DAT0__GPT_CAPTURE1           0x340 0x728 0x000 0x3 0x0
+#define MX6QDL_PAD_SD1_DAT0__GPIO1_IO16             0x340 0x728 0x000 0x5 0x0
+#define MX6QDL_PAD_SD1_DAT3__SD1_DATA3              0x344 0x72c 0x000 0x0 0x0
+#define MX6QDL_PAD_SD1_DAT3__ECSPI5_SS2             0x344 0x72c 0x000 0x1 0x0
+#define MX6QDL_PAD_SD1_DAT3__GPT_COMPARE3           0x344 0x72c 0x000 0x2 0x0
+#define MX6QDL_PAD_SD1_DAT3__PWM1_OUT               0x344 0x72c 0x000 0x3 0x0
+#define MX6QDL_PAD_SD1_DAT3__WDOG2_B                0x344 0x72c 0x000 0x4 0x0
+#define MX6QDL_PAD_SD1_DAT3__GPIO1_IO21             0x344 0x72c 0x000 0x5 0x0
+#define MX6QDL_PAD_SD1_DAT3__WDOG2_RESET_B_DEB      0x344 0x72c 0x000 0x6 0x0
+#define MX6QDL_PAD_SD1_CMD__SD1_CMD                 0x348 0x730 0x000 0x0 0x0
+#define MX6QDL_PAD_SD1_CMD__ECSPI5_MOSI             0x348 0x730 0x830 0x1 0x0
+#define MX6QDL_PAD_SD1_CMD__PWM4_OUT                0x348 0x730 0x000 0x2 0x0
+#define MX6QDL_PAD_SD1_CMD__GPT_COMPARE1            0x348 0x730 0x000 0x3 0x0
+#define MX6QDL_PAD_SD1_CMD__GPIO1_IO18              0x348 0x730 0x000 0x5 0x0
+#define MX6QDL_PAD_SD1_DAT2__SD1_DATA2              0x34c 0x734 0x000 0x0 0x0
+#define MX6QDL_PAD_SD1_DAT2__ECSPI5_SS1             0x34c 0x734 0x838 0x1 0x1
+#define MX6QDL_PAD_SD1_DAT2__GPT_COMPARE2           0x34c 0x734 0x000 0x2 0x0
+#define MX6QDL_PAD_SD1_DAT2__PWM2_OUT               0x34c 0x734 0x000 0x3 0x0
+#define MX6QDL_PAD_SD1_DAT2__WDOG1_B                0x34c 0x734 0x000 0x4 0x0
+#define MX6QDL_PAD_SD1_DAT2__GPIO1_IO19             0x34c 0x734 0x000 0x5 0x0
+#define MX6QDL_PAD_SD1_DAT2__WDOG1_RESET_B_DEB      0x34c 0x734 0x000 0x6 0x0
+#define MX6QDL_PAD_SD1_CLK__SD1_CLK                 0x350 0x738 0x000 0x0 0x0
+#define MX6QDL_PAD_SD1_CLK__ECSPI5_SCLK             0x350 0x738 0x828 0x1 0x0
+#define MX6QDL_PAD_SD1_CLK__OSC32K_32K_OUT          0x350 0x738 0x000 0x2 0x0
+#define MX6QDL_PAD_SD1_CLK__GPT_CLKIN               0x350 0x738 0x000 0x3 0x0
+#define MX6QDL_PAD_SD1_CLK__GPIO1_IO20              0x350 0x738 0x000 0x5 0x0
+#define MX6QDL_PAD_SD2_CLK__SD2_CLK                 0x354 0x73c 0x000 0x0 0x0
+#define MX6QDL_PAD_SD2_CLK__ECSPI5_SCLK             0x354 0x73c 0x828 0x1 0x1
+#define MX6QDL_PAD_SD2_CLK__KEY_COL5                0x354 0x73c 0x8e8 0x2 0x3
+#define MX6QDL_PAD_SD2_CLK__AUD4_RXFS               0x354 0x73c 0x7c0 0x3 0x1
+#define MX6QDL_PAD_SD2_CLK__GPIO1_IO10              0x354 0x73c 0x000 0x5 0x0
+#define MX6QDL_PAD_SD2_CMD__SD2_CMD                 0x358 0x740 0x000 0x0 0x0
+#define MX6QDL_PAD_SD2_CMD__ECSPI5_MOSI             0x358 0x740 0x830 0x1 0x1
+#define MX6QDL_PAD_SD2_CMD__KEY_ROW5                0x358 0x740 0x8f4 0x2 0x2
+#define MX6QDL_PAD_SD2_CMD__AUD4_RXC                0x358 0x740 0x7bc 0x3 0x1
+#define MX6QDL_PAD_SD2_CMD__GPIO1_IO11              0x358 0x740 0x000 0x5 0x0
+#define MX6QDL_PAD_SD2_DAT3__SD2_DATA3              0x35c 0x744 0x000 0x0 0x0
+#define MX6QDL_PAD_SD2_DAT3__ECSPI5_SS3             0x35c 0x744 0x000 0x1 0x0
+#define MX6QDL_PAD_SD2_DAT3__KEY_COL6               0x35c 0x744 0x8ec 0x2 0x2
+#define MX6QDL_PAD_SD2_DAT3__AUD4_TXC               0x35c 0x744 0x7c4 0x3 0x1
+#define MX6QDL_PAD_SD2_DAT3__GPIO1_IO12             0x35c 0x744 0x000 0x5 0x0
+
+#endif /* __DTS_IMX6Q_PINFUNC_H */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/imx6sl-pinfunc.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/imx6sl-pinfunc.h
new file mode 100644
index 0000000000000000000000000000000000000000..77b17bcc7b70c17b99305058fd34ece26328eb37
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/imx6sl-pinfunc.h
@@ -0,0 +1,1077 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __DTS_IMX6SL_PINFUNC_H
+#define __DTS_IMX6SL_PINFUNC_H
+
+/*
+ * The pin function ID is a tuple of
+ * <mux_reg conf_reg input_reg mux_mode input_val>
+ */
+#define MX6SL_PAD_AUD_MCLK__AUDIO_CLK_OUT          0x04c 0x2a4 0x000 0x0 0x0
+#define MX6SL_PAD_AUD_MCLK__PWM4_OUT               0x04c 0x2a4 0x000 0x1 0x0
+#define MX6SL_PAD_AUD_MCLK__ECSPI3_RDY             0x04c 0x2a4 0x6b4 0x2 0x0
+#define MX6SL_PAD_AUD_MCLK__FEC_MDC                0x04c 0x2a4 0x000 0x3 0x0
+#define MX6SL_PAD_AUD_MCLK__WDOG2_RESET_B_DEB      0x04c 0x2a4 0x000 0x4 0x0
+#define MX6SL_PAD_AUD_MCLK__GPIO1_IO06             0x04c 0x2a4 0x000 0x5 0x0
+#define MX6SL_PAD_AUD_MCLK__SPDIF_EXT_CLK          0x04c 0x2a4 0x7f4 0x6 0x0
+#define MX6SL_PAD_AUD_RXC__AUD3_RXC                0x050 0x2a8 0x000 0x0 0x0
+#define MX6SL_PAD_AUD_RXC__I2C1_SDA                0x050 0x2a8 0x720 0x1 0x0
+#define MX6SL_PAD_AUD_RXC__UART3_TX_DATA           0x050 0x2a8 0x000 0x2 0x0
+#define MX6SL_PAD_AUD_RXC__UART3_RX_DATA           0x050 0x2a8 0x80c 0x2 0x0
+#define MX6SL_PAD_AUD_RXC__FEC_TX_CLK              0x050 0x2a8 0x70c 0x3 0x0
+#define MX6SL_PAD_AUD_RXC__I2C3_SDA                0x050 0x2a8 0x730 0x4 0x0
+#define MX6SL_PAD_AUD_RXC__GPIO1_IO01              0x050 0x2a8 0x000 0x5 0x0
+#define MX6SL_PAD_AUD_RXC__ECSPI3_SS1              0x050 0x2a8 0x6c4 0x6 0x0
+#define MX6SL_PAD_AUD_RXD__AUD3_RXD                0x054 0x2ac 0x000 0x0 0x0
+#define MX6SL_PAD_AUD_RXD__ECSPI3_MOSI             0x054 0x2ac 0x6bc 0x1 0x0
+#define MX6SL_PAD_AUD_RXD__UART4_RX_DATA           0x054 0x2ac 0x814 0x2 0x0
+#define MX6SL_PAD_AUD_RXD__UART4_TX_DATA           0x054 0x2ac 0x000 0x2 0x0
+#define MX6SL_PAD_AUD_RXD__FEC_RX_ER               0x054 0x2ac 0x708 0x3 0x0
+#define MX6SL_PAD_AUD_RXD__SD1_LCTL                0x054 0x2ac 0x000 0x4 0x0
+#define MX6SL_PAD_AUD_RXD__GPIO1_IO02              0x054 0x2ac 0x000 0x5 0x0
+#define MX6SL_PAD_AUD_RXFS__AUD3_RXFS              0x058 0x2b0 0x000 0x0 0x0
+#define MX6SL_PAD_AUD_RXFS__I2C1_SCL               0x058 0x2b0 0x71c 0x1 0x0
+#define MX6SL_PAD_AUD_RXFS__UART3_RX_DATA          0x058 0x2b0 0x80c 0x2 0x1
+#define MX6SL_PAD_AUD_RXFS__UART3_TX_DATA          0x058 0x2b0 0x000 0x2 0x0
+#define MX6SL_PAD_AUD_RXFS__FEC_MDIO               0x058 0x2b0 0x6f4 0x3 0x0
+#define MX6SL_PAD_AUD_RXFS__I2C3_SCL               0x058 0x2b0 0x72c 0x4 0x0
+#define MX6SL_PAD_AUD_RXFS__GPIO1_IO00             0x058 0x2b0 0x000 0x5 0x0
+#define MX6SL_PAD_AUD_RXFS__ECSPI3_SS0             0x058 0x2b0 0x6c0 0x6 0x0
+#define MX6SL_PAD_AUD_TXC__AUD3_TXC                0x05c 0x2b4 0x000 0x0 0x0
+#define MX6SL_PAD_AUD_TXC__ECSPI3_MISO             0x05c 0x2b4 0x6b8 0x1 0x0
+#define MX6SL_PAD_AUD_TXC__UART4_TX_DATA           0x05c 0x2b4 0x000 0x2 0x0
+#define MX6SL_PAD_AUD_TXC__UART4_RX_DATA           0x05c 0x2b4 0x814 0x2 0x1
+#define MX6SL_PAD_AUD_TXC__FEC_RX_DV               0x05c 0x2b4 0x704 0x3 0x0
+#define MX6SL_PAD_AUD_TXC__SD2_LCTL                0x05c 0x2b4 0x000 0x4 0x0
+#define MX6SL_PAD_AUD_TXC__GPIO1_IO03              0x05c 0x2b4 0x000 0x5 0x0
+#define MX6SL_PAD_AUD_TXD__AUD3_TXD                0x060 0x2b8 0x000 0x0 0x0
+#define MX6SL_PAD_AUD_TXD__ECSPI3_SCLK             0x060 0x2b8 0x6b0 0x1 0x0
+#define MX6SL_PAD_AUD_TXD__UART4_CTS_B             0x060 0x2b8 0x000 0x2 0x0
+#define MX6SL_PAD_AUD_TXD__UART4_RTS_B             0x060 0x2b8 0x810 0x2 0x0
+#define MX6SL_PAD_AUD_TXD__FEC_TX_DATA0            0x060 0x2b8 0x000 0x3 0x0
+#define MX6SL_PAD_AUD_TXD__SD4_LCTL                0x060 0x2b8 0x000 0x4 0x0
+#define MX6SL_PAD_AUD_TXD__GPIO1_IO05              0x060 0x2b8 0x000 0x5 0x0
+#define MX6SL_PAD_AUD_TXFS__AUD3_TXFS              0x064 0x2bc 0x000 0x0 0x0
+#define MX6SL_PAD_AUD_TXFS__PWM3_OUT               0x064 0x2bc 0x000 0x1 0x0
+#define MX6SL_PAD_AUD_TXFS__UART4_RTS_B            0x064 0x2bc 0x810 0x2 0x1
+#define MX6SL_PAD_AUD_TXFS__UART4_CTS_B            0x064 0x2bc 0x000 0x2 0x0
+#define MX6SL_PAD_AUD_TXFS__FEC_RX_DATA1           0x064 0x2bc 0x6fc 0x3 0x0
+#define MX6SL_PAD_AUD_TXFS__SD3_LCTL               0x064 0x2bc 0x000 0x4 0x0
+#define MX6SL_PAD_AUD_TXFS__GPIO1_IO04             0x064 0x2bc 0x000 0x5 0x0
+#define MX6SL_PAD_ECSPI1_MISO__ECSPI1_MISO         0x068 0x358 0x684 0x0 0x0
+#define MX6SL_PAD_ECSPI1_MISO__AUD4_TXFS           0x068 0x358 0x5f8 0x1 0x0
+#define MX6SL_PAD_ECSPI1_MISO__UART5_RTS_B         0x068 0x358 0x818 0x2 0x0
+#define MX6SL_PAD_ECSPI1_MISO__UART5_CTS_B         0x068 0x358 0x000 0x2 0x0
+#define MX6SL_PAD_ECSPI1_MISO__EPDC_BDR0           0x068 0x358 0x000 0x3 0x0
+#define MX6SL_PAD_ECSPI1_MISO__SD2_WP              0x068 0x358 0x834 0x4 0x0
+#define MX6SL_PAD_ECSPI1_MISO__GPIO4_IO10          0x068 0x358 0x000 0x5 0x0
+#define MX6SL_PAD_ECSPI1_MOSI__ECSPI1_MOSI         0x06c 0x35c 0x688 0x0 0x0
+#define MX6SL_PAD_ECSPI1_MOSI__AUD4_TXC            0x06c 0x35c 0x5f4 0x1 0x0
+#define MX6SL_PAD_ECSPI1_MOSI__UART5_TX_DATA       0x06c 0x35c 0x000 0x2 0x0
+#define MX6SL_PAD_ECSPI1_MOSI__UART5_RX_DATA       0x06c 0x35c 0x81c 0x2 0x0
+#define MX6SL_PAD_ECSPI1_MOSI__EPDC_VCOM1          0x06c 0x35c 0x000 0x3 0x0
+#define MX6SL_PAD_ECSPI1_MOSI__SD2_VSELECT         0x06c 0x35c 0x000 0x4 0x0
+#define MX6SL_PAD_ECSPI1_MOSI__GPIO4_IO09          0x06c 0x35c 0x000 0x5 0x0
+#define MX6SL_PAD_ECSPI1_SCLK__ECSPI1_SCLK         0x070 0x360 0x67c 0x0 0x0
+#define MX6SL_PAD_ECSPI1_SCLK__AUD4_TXD            0x070 0x360 0x5e8 0x1 0x0
+#define MX6SL_PAD_ECSPI1_SCLK__UART5_RX_DATA       0x070 0x360 0x81c 0x2 0x1
+#define MX6SL_PAD_ECSPI1_SCLK__UART5_TX_DATA       0x070 0x360 0x000 0x2 0x0
+#define MX6SL_PAD_ECSPI1_SCLK__EPDC_VCOM0          0x070 0x360 0x000 0x3 0x0
+#define MX6SL_PAD_ECSPI1_SCLK__SD2_RESET           0x070 0x360 0x000 0x4 0x0
+#define MX6SL_PAD_ECSPI1_SCLK__GPIO4_IO08          0x070 0x360 0x000 0x5 0x0
+#define MX6SL_PAD_ECSPI1_SCLK__USB_OTG2_OC         0x070 0x360 0x820 0x6 0x0
+#define MX6SL_PAD_ECSPI1_SS0__ECSPI1_SS0           0x074 0x364 0x68c 0x0 0x0
+#define MX6SL_PAD_ECSPI1_SS0__AUD4_RXD             0x074 0x364 0x5e4 0x1 0x0
+#define MX6SL_PAD_ECSPI1_SS0__UART5_CTS_B          0x074 0x364 0x000 0x2 0x0
+#define MX6SL_PAD_ECSPI1_SS0__UART5_RTS_B          0x074 0x364 0x818 0x2 0x1
+#define MX6SL_PAD_ECSPI1_SS0__EPDC_BDR1            0x074 0x364 0x000 0x3 0x0
+#define MX6SL_PAD_ECSPI1_SS0__SD2_CD_B             0x074 0x364 0x830 0x4 0x0
+#define MX6SL_PAD_ECSPI1_SS0__GPIO4_IO11           0x074 0x364 0x000 0x5 0x0
+#define MX6SL_PAD_ECSPI1_SS0__USB_OTG2_PWR         0x074 0x364 0x000 0x6 0x0
+#define MX6SL_PAD_ECSPI2_MISO__ECSPI2_MISO         0x078 0x368 0x6a0 0x0 0x0
+#define MX6SL_PAD_ECSPI2_MISO__SDMA_EXT_EVENT0     0x078 0x368 0x000 0x1 0x0
+#define MX6SL_PAD_ECSPI2_MISO__UART3_RTS_B         0x078 0x368 0x808 0x2 0x0
+#define MX6SL_PAD_ECSPI2_MISO__UART3_CTS_B         0x078 0x368 0x000 0x2 0x0
+#define MX6SL_PAD_ECSPI2_MISO__CSI_MCLK            0x078 0x368 0x000 0x3 0x0
+#define MX6SL_PAD_ECSPI2_MISO__SD1_WP              0x078 0x368 0x82c 0x4 0x0
+#define MX6SL_PAD_ECSPI2_MISO__GPIO4_IO14          0x078 0x368 0x000 0x5 0x0
+#define MX6SL_PAD_ECSPI2_MISO__USB_OTG1_OC         0x078 0x368 0x824 0x6 0x0
+#define MX6SL_PAD_ECSPI2_MOSI__ECSPI2_MOSI         0x07c 0x36c 0x6a4 0x0 0x0
+#define MX6SL_PAD_ECSPI2_MOSI__SDMA_EXT_EVENT1     0x07c 0x36c 0x000 0x1 0x0
+#define MX6SL_PAD_ECSPI2_MOSI__UART3_TX_DATA       0x07c 0x36c 0x000 0x2 0x0
+#define MX6SL_PAD_ECSPI2_MOSI__UART3_RX_DATA       0x07c 0x36c 0x80c 0x2 0x2
+#define MX6SL_PAD_ECSPI2_MOSI__CSI_HSYNC           0x07c 0x36c 0x670 0x3 0x0
+#define MX6SL_PAD_ECSPI2_MOSI__SD1_VSELECT         0x07c 0x36c 0x000 0x4 0x0
+#define MX6SL_PAD_ECSPI2_MOSI__GPIO4_IO13          0x07c 0x36c 0x000 0x5 0x0
+#define MX6SL_PAD_ECSPI2_SCLK__ECSPI2_SCLK         0x080 0x370 0x69c 0x0 0x0
+#define MX6SL_PAD_ECSPI2_SCLK__SPDIF_EXT_CLK       0x080 0x370 0x7f4 0x1 0x1
+#define MX6SL_PAD_ECSPI2_SCLK__UART3_RX_DATA       0x080 0x370 0x80c 0x2 0x3
+#define MX6SL_PAD_ECSPI2_SCLK__UART3_TX_DATA       0x080 0x370 0x000 0x2 0x0
+#define MX6SL_PAD_ECSPI2_SCLK__CSI_PIXCLK          0x080 0x370 0x674 0x3 0x0
+#define MX6SL_PAD_ECSPI2_SCLK__SD1_RESET           0x080 0x370 0x000 0x4 0x0
+#define MX6SL_PAD_ECSPI2_SCLK__GPIO4_IO12          0x080 0x370 0x000 0x5 0x0
+#define MX6SL_PAD_ECSPI2_SCLK__USB_OTG2_OC         0x080 0x370 0x820 0x6 0x1
+#define MX6SL_PAD_ECSPI2_SS0__ECSPI2_SS0           0x084 0x374 0x6a8 0x0 0x0
+#define MX6SL_PAD_ECSPI2_SS0__ECSPI1_SS3           0x084 0x374 0x698 0x1 0x0
+#define MX6SL_PAD_ECSPI2_SS0__UART3_CTS_B          0x084 0x374 0x000 0x2 0x0
+#define MX6SL_PAD_ECSPI2_SS0__UART3_RTS_B          0x084 0x374 0x808 0x2 0x1
+#define MX6SL_PAD_ECSPI2_SS0__CSI_VSYNC            0x084 0x374 0x678 0x3 0x0
+#define MX6SL_PAD_ECSPI2_SS0__SD1_CD_B             0x084 0x374 0x828 0x4 0x0
+#define MX6SL_PAD_ECSPI2_SS0__GPIO4_IO15           0x084 0x374 0x000 0x5 0x0
+#define MX6SL_PAD_ECSPI2_SS0__USB_OTG1_PWR         0x084 0x374 0x000 0x6 0x0
+#define MX6SL_PAD_EPDC_BDR0__EPDC_BDR0             0x088 0x378 0x000 0x0 0x0
+#define MX6SL_PAD_EPDC_BDR0__SD4_CLK               0x088 0x378 0x850 0x1 0x0
+#define MX6SL_PAD_EPDC_BDR0__UART3_RTS_B           0x088 0x378 0x808 0x2 0x2
+#define MX6SL_PAD_EPDC_BDR0__UART3_CTS_B           0x088 0x378 0x000 0x2 0x0
+#define MX6SL_PAD_EPDC_BDR0__EIM_ADDR26            0x088 0x378 0x000 0x3 0x0
+#define MX6SL_PAD_EPDC_BDR0__SPDC_RL               0x088 0x378 0x000 0x4 0x0
+#define MX6SL_PAD_EPDC_BDR0__GPIO2_IO05            0x088 0x378 0x000 0x5 0x0
+#define MX6SL_PAD_EPDC_BDR0__EPDC_SDCE7            0x088 0x378 0x000 0x6 0x0
+#define MX6SL_PAD_EPDC_BDR1__EPDC_BDR1             0x08c 0x37c 0x000 0x0 0x0
+#define MX6SL_PAD_EPDC_BDR1__SD4_CMD               0x08c 0x37c 0x858 0x1 0x0
+#define MX6SL_PAD_EPDC_BDR1__UART3_CTS_B           0x08c 0x37c 0x000 0x2 0x0
+#define MX6SL_PAD_EPDC_BDR1__UART3_RTS_B           0x08c 0x37c 0x808 0x2 0x3
+#define MX6SL_PAD_EPDC_BDR1__EIM_CRE               0x08c 0x37c 0x000 0x3 0x0
+#define MX6SL_PAD_EPDC_BDR1__SPDC_UD               0x08c 0x37c 0x000 0x4 0x0
+#define MX6SL_PAD_EPDC_BDR1__GPIO2_IO06            0x08c 0x37c 0x000 0x5 0x0
+#define MX6SL_PAD_EPDC_BDR1__EPDC_SDCE8            0x08c 0x37c 0x000 0x6 0x0
+#define MX6SL_PAD_EPDC_D0__EPDC_DATA00             0x090 0x380 0x000 0x0 0x0
+#define MX6SL_PAD_EPDC_D0__ECSPI4_MOSI             0x090 0x380 0x6d8 0x1 0x0
+#define MX6SL_PAD_EPDC_D0__LCD_DATA24              0x090 0x380 0x000 0x2 0x0
+#define MX6SL_PAD_EPDC_D0__CSI_DATA00              0x090 0x380 0x630 0x3 0x0
+#define MX6SL_PAD_EPDC_D0__SPDC_DATA00             0x090 0x380 0x000 0x4 0x0
+#define MX6SL_PAD_EPDC_D0__GPIO1_IO07              0x090 0x380 0x000 0x5 0x0
+#define MX6SL_PAD_EPDC_D1__EPDC_DATA01             0x094 0x384 0x000 0x0 0x0
+#define MX6SL_PAD_EPDC_D1__ECSPI4_MISO             0x094 0x384 0x6d4 0x1 0x0
+#define MX6SL_PAD_EPDC_D1__LCD_DATA25              0x094 0x384 0x000 0x2 0x0
+#define MX6SL_PAD_EPDC_D1__CSI_DATA01              0x094 0x384 0x634 0x3 0x0
+#define MX6SL_PAD_EPDC_D1__SPDC_DATA01             0x094 0x384 0x000 0x4 0x0
+#define MX6SL_PAD_EPDC_D1__GPIO1_IO08              0x094 0x384 0x000 0x5 0x0
+#define MX6SL_PAD_EPDC_D10__EPDC_DATA10            0x098 0x388 0x000 0x0 0x0
+#define MX6SL_PAD_EPDC_D10__ECSPI3_SS0             0x098 0x388 0x6c0 0x1 0x1
+#define MX6SL_PAD_EPDC_D10__EPDC_PWR_CTRL2         0x098 0x388 0x000 0x2 0x0
+#define MX6SL_PAD_EPDC_D10__EIM_ADDR18             0x098 0x388 0x000 0x3 0x0
+#define MX6SL_PAD_EPDC_D10__SPDC_DATA10            0x098 0x388 0x000 0x4 0x0
+#define MX6SL_PAD_EPDC_D10__GPIO1_IO17             0x098 0x388 0x000 0x5 0x0
+#define MX6SL_PAD_EPDC_D10__SD4_WP                 0x098 0x388 0x87c 0x6 0x0
+#define MX6SL_PAD_EPDC_D11__EPDC_DATA11            0x09c 0x38c 0x000 0x0 0x0
+#define MX6SL_PAD_EPDC_D11__ECSPI3_SCLK            0x09c 0x38c 0x6b0 0x1 0x1
+#define MX6SL_PAD_EPDC_D11__EPDC_PWR_CTRL3         0x09c 0x38c 0x000 0x2 0x0
+#define MX6SL_PAD_EPDC_D11__EIM_ADDR19             0x09c 0x38c 0x000 0x3 0x0
+#define MX6SL_PAD_EPDC_D11__SPDC_DATA11            0x09c 0x38c 0x000 0x4 0x0
+#define MX6SL_PAD_EPDC_D11__GPIO1_IO18             0x09c 0x38c 0x000 0x5 0x0
+#define MX6SL_PAD_EPDC_D11__SD4_CD_B               0x09c 0x38c 0x854 0x6 0x0
+#define MX6SL_PAD_EPDC_D12__EPDC_DATA12            0x0a0 0x390 0x000 0x0 0x0
+#define MX6SL_PAD_EPDC_D12__UART2_RX_DATA          0x0a0 0x390 0x804 0x1 0x0
+#define MX6SL_PAD_EPDC_D12__UART2_TX_DATA          0x0a0 0x390 0x000 0x1 0x0
+#define MX6SL_PAD_EPDC_D12__EPDC_PWR_COM           0x0a0 0x390 0x000 0x2 0x0
+#define MX6SL_PAD_EPDC_D12__EIM_ADDR20             0x0a0 0x390 0x000 0x3 0x0
+#define MX6SL_PAD_EPDC_D12__SPDC_DATA12            0x0a0 0x390 0x000 0x4 0x0
+#define MX6SL_PAD_EPDC_D12__GPIO1_IO19             0x0a0 0x390 0x000 0x5 0x0
+#define MX6SL_PAD_EPDC_D12__ECSPI3_SS1             0x0a0 0x390 0x6c4 0x6 0x1
+#define MX6SL_PAD_EPDC_D13__EPDC_DATA13            0x0a4 0x394 0x000 0x0 0x0
+#define MX6SL_PAD_EPDC_D13__UART2_TX_DATA          0x0a4 0x394 0x000 0x1 0x0
+#define MX6SL_PAD_EPDC_D13__UART2_RX_DATA          0x0a4 0x394 0x804 0x1 0x1
+#define MX6SL_PAD_EPDC_D13__EPDC_PWR_IRQ           0x0a4 0x394 0x6e8 0x2 0x0
+#define MX6SL_PAD_EPDC_D13__EIM_ADDR21             0x0a4 0x394 0x000 0x3 0x0
+#define MX6SL_PAD_EPDC_D13__SPDC_DATA13            0x0a4 0x394 0x000 0x4 0x0
+#define MX6SL_PAD_EPDC_D13__GPIO1_IO20             0x0a4 0x394 0x000 0x5 0x0
+#define MX6SL_PAD_EPDC_D13__ECSPI3_SS2             0x0a4 0x394 0x6c8 0x6 0x0
+#define MX6SL_PAD_EPDC_D14__EPDC_DATA14            0x0a8 0x398 0x000 0x0 0x0
+#define MX6SL_PAD_EPDC_D14__UART2_RTS_B            0x0a8 0x398 0x800 0x1 0x0
+#define MX6SL_PAD_EPDC_D14__UART2_CTS_B            0x0a8 0x398 0x000 0x1 0x0
+#define MX6SL_PAD_EPDC_D14__EPDC_PWR_STAT          0x0a8 0x398 0x6ec 0x2 0x0
+#define MX6SL_PAD_EPDC_D14__EIM_ADDR22             0x0a8 0x398 0x000 0x3 0x0
+#define MX6SL_PAD_EPDC_D14__SPDC_DATA14            0x0a8 0x398 0x000 0x4 0x0
+#define MX6SL_PAD_EPDC_D14__GPIO1_IO21             0x0a8 0x398 0x000 0x5 0x0
+#define MX6SL_PAD_EPDC_D14__ECSPI3_SS3             0x0a8 0x398 0x6cc 0x6 0x0
+#define MX6SL_PAD_EPDC_D15__EPDC_DATA15            0x0ac 0x39c 0x000 0x0 0x0
+#define MX6SL_PAD_EPDC_D15__UART2_CTS_B            0x0ac 0x39c 0x000 0x1 0x0
+#define MX6SL_PAD_EPDC_D15__UART2_RTS_B            0x0ac 0x39c 0x800 0x1 0x1
+#define MX6SL_PAD_EPDC_D15__EPDC_PWR_WAKE          0x0ac 0x39c 0x000 0x2 0x0
+#define MX6SL_PAD_EPDC_D15__EIM_ADDR23             0x0ac 0x39c 0x000 0x3 0x0
+#define MX6SL_PAD_EPDC_D15__SPDC_DATA15            0x0ac 0x39c 0x000 0x4 0x0
+#define MX6SL_PAD_EPDC_D15__GPIO1_IO22             0x0ac 0x39c 0x000 0x5 0x0
+#define MX6SL_PAD_EPDC_D15__ECSPI3_RDY             0x0ac 0x39c 0x6b4 0x6 0x1
+#define MX6SL_PAD_EPDC_D2__EPDC_DATA02             0x0b0 0x3a0 0x000 0x0 0x0
+#define MX6SL_PAD_EPDC_D2__ECSPI4_SS0              0x0b0 0x3a0 0x6dc 0x1 0x0
+#define MX6SL_PAD_EPDC_D2__LCD_DATA26              0x0b0 0x3a0 0x000 0x2 0x0
+#define MX6SL_PAD_EPDC_D2__CSI_DATA02              0x0b0 0x3a0 0x638 0x3 0x0
+#define MX6SL_PAD_EPDC_D2__SPDC_DATA02             0x0b0 0x3a0 0x000 0x4 0x0
+#define MX6SL_PAD_EPDC_D2__GPIO1_IO09              0x0b0 0x3a0 0x000 0x5 0x0
+#define MX6SL_PAD_EPDC_D3__EPDC_DATA03             0x0b4 0x3a4 0x000 0x0 0x0
+#define MX6SL_PAD_EPDC_D3__ECSPI4_SCLK             0x0b4 0x3a4 0x6d0 0x1 0x0
+#define MX6SL_PAD_EPDC_D3__LCD_DATA27              0x0b4 0x3a4 0x000 0x2 0x0
+#define MX6SL_PAD_EPDC_D3__CSI_DATA03              0x0b4 0x3a4 0x63c 0x3 0x0
+#define MX6SL_PAD_EPDC_D3__SPDC_DATA03             0x0b4 0x3a4 0x000 0x4 0x0
+#define MX6SL_PAD_EPDC_D3__GPIO1_IO10              0x0b4 0x3a4 0x000 0x5 0x0
+#define MX6SL_PAD_EPDC_D4__EPDC_DATA04             0x0b8 0x3a8 0x000 0x0 0x0
+#define MX6SL_PAD_EPDC_D4__ECSPI4_SS1              0x0b8 0x3a8 0x6e0 0x1 0x0
+#define MX6SL_PAD_EPDC_D4__LCD_DATA28              0x0b8 0x3a8 0x000 0x2 0x0
+#define MX6SL_PAD_EPDC_D4__CSI_DATA04              0x0b8 0x3a8 0x640 0x3 0x0
+#define MX6SL_PAD_EPDC_D4__SPDC_DATA04             0x0b8 0x3a8 0x000 0x4 0x0
+#define MX6SL_PAD_EPDC_D4__GPIO1_IO11              0x0b8 0x3a8 0x000 0x5 0x0
+#define MX6SL_PAD_EPDC_D5__EPDC_DATA05             0x0bc 0x3ac 0x000 0x0 0x0
+#define MX6SL_PAD_EPDC_D5__ECSPI4_SS2              0x0bc 0x3ac 0x6e4 0x1 0x0
+#define MX6SL_PAD_EPDC_D5__LCD_DATA29              0x0bc 0x3ac 0x000 0x2 0x0
+#define MX6SL_PAD_EPDC_D5__CSI_DATA05              0x0bc 0x3ac 0x644 0x3 0x0
+#define MX6SL_PAD_EPDC_D5__SPDC_DATA05             0x0bc 0x3ac 0x000 0x4 0x0
+#define MX6SL_PAD_EPDC_D5__GPIO1_IO12              0x0bc 0x3ac 0x000 0x5 0x0
+#define MX6SL_PAD_EPDC_D6__EPDC_DATA06             0x0c0 0x3b0 0x000 0x0 0x0
+#define MX6SL_PAD_EPDC_D6__ECSPI4_SS3              0x0c0 0x3b0 0x000 0x1 0x0
+#define MX6SL_PAD_EPDC_D6__LCD_DATA30              0x0c0 0x3b0 0x000 0x2 0x0
+#define MX6SL_PAD_EPDC_D6__CSI_DATA06              0x0c0 0x3b0 0x648 0x3 0x0
+#define MX6SL_PAD_EPDC_D6__SPDC_DATA06             0x0c0 0x3b0 0x000 0x4 0x0
+#define MX6SL_PAD_EPDC_D6__GPIO1_IO13              0x0c0 0x3b0 0x000 0x5 0x0
+#define MX6SL_PAD_EPDC_D7__EPDC_DATA07             0x0c4 0x3b4 0x000 0x0 0x0
+#define MX6SL_PAD_EPDC_D7__ECSPI4_RDY              0x0c4 0x3b4 0x000 0x1 0x0
+#define MX6SL_PAD_EPDC_D7__LCD_DATA31              0x0c4 0x3b4 0x000 0x2 0x0
+#define MX6SL_PAD_EPDC_D7__CSI_DATA07              0x0c4 0x3b4 0x64c 0x3 0x0
+#define MX6SL_PAD_EPDC_D7__SPDC_DATA07             0x0c4 0x3b4 0x000 0x4 0x0
+#define MX6SL_PAD_EPDC_D7__GPIO1_IO14              0x0c4 0x3b4 0x000 0x5 0x0
+#define MX6SL_PAD_EPDC_D8__EPDC_DATA08             0x0c8 0x3b8 0x000 0x0 0x0
+#define MX6SL_PAD_EPDC_D8__ECSPI3_MOSI             0x0c8 0x3b8 0x6bc 0x1 0x1
+#define MX6SL_PAD_EPDC_D8__EPDC_PWR_CTRL0          0x0c8 0x3b8 0x000 0x2 0x0
+#define MX6SL_PAD_EPDC_D8__EIM_ADDR16              0x0c8 0x3b8 0x000 0x3 0x0
+#define MX6SL_PAD_EPDC_D8__SPDC_DATA08             0x0c8 0x3b8 0x000 0x4 0x0
+#define MX6SL_PAD_EPDC_D8__GPIO1_IO15              0x0c8 0x3b8 0x000 0x5 0x0
+#define MX6SL_PAD_EPDC_D8__SD4_RESET               0x0c8 0x3b8 0x000 0x6 0x0
+#define MX6SL_PAD_EPDC_D9__EPDC_DATA09             0x0cc 0x3bc 0x000 0x0 0x0
+#define MX6SL_PAD_EPDC_D9__ECSPI3_MISO             0x0cc 0x3bc 0x6b8 0x1 0x1
+#define MX6SL_PAD_EPDC_D9__EPDC_PWR_CTRL1          0x0cc 0x3bc 0x000 0x2 0x0
+#define MX6SL_PAD_EPDC_D9__EIM_ADDR17              0x0cc 0x3bc 0x000 0x3 0x0
+#define MX6SL_PAD_EPDC_D9__SPDC_DATA09             0x0cc 0x3bc 0x000 0x4 0x0
+#define MX6SL_PAD_EPDC_D9__GPIO1_IO16              0x0cc 0x3bc 0x000 0x5 0x0
+#define MX6SL_PAD_EPDC_D9__SD4_VSELECT             0x0cc 0x3bc 0x000 0x6 0x0
+#define MX6SL_PAD_EPDC_GDCLK__EPDC_GDCLK           0x0d0 0x3c0 0x000 0x0 0x0
+#define MX6SL_PAD_EPDC_GDCLK__ECSPI2_SS2           0x0d0 0x3c0 0x000 0x1 0x0
+#define MX6SL_PAD_EPDC_GDCLK__SPDC_YCKR            0x0d0 0x3c0 0x000 0x2 0x0
+#define MX6SL_PAD_EPDC_GDCLK__CSI_PIXCLK           0x0d0 0x3c0 0x674 0x3 0x1
+#define MX6SL_PAD_EPDC_GDCLK__SPDC_YCKL            0x0d0 0x3c0 0x000 0x4 0x0
+#define MX6SL_PAD_EPDC_GDCLK__GPIO1_IO31           0x0d0 0x3c0 0x000 0x5 0x0
+#define MX6SL_PAD_EPDC_GDCLK__SD2_RESET            0x0d0 0x3c0 0x000 0x6 0x0
+#define MX6SL_PAD_EPDC_GDOE__EPDC_GDOE             0x0d4 0x3c4 0x000 0x0 0x0
+#define MX6SL_PAD_EPDC_GDOE__ECSPI2_SS3            0x0d4 0x3c4 0x000 0x1 0x0
+#define MX6SL_PAD_EPDC_GDOE__SPDC_YOER             0x0d4 0x3c4 0x000 0x2 0x0
+#define MX6SL_PAD_EPDC_GDOE__CSI_HSYNC             0x0d4 0x3c4 0x670 0x3 0x1
+#define MX6SL_PAD_EPDC_GDOE__SPDC_YOEL             0x0d4 0x3c4 0x000 0x4 0x0
+#define MX6SL_PAD_EPDC_GDOE__GPIO2_IO00            0x0d4 0x3c4 0x000 0x5 0x0
+#define MX6SL_PAD_EPDC_GDOE__SD2_VSELECT           0x0d4 0x3c4 0x000 0x6 0x0
+#define MX6SL_PAD_EPDC_GDRL__EPDC_GDRL             0x0d8 0x3c8 0x000 0x0 0x0
+#define MX6SL_PAD_EPDC_GDRL__ECSPI2_RDY            0x0d8 0x3c8 0x000 0x1 0x0
+#define MX6SL_PAD_EPDC_GDRL__SPDC_YDIOUR           0x0d8 0x3c8 0x000 0x2 0x0
+#define MX6SL_PAD_EPDC_GDRL__CSI_MCLK              0x0d8 0x3c8 0x000 0x3 0x0
+#define MX6SL_PAD_EPDC_GDRL__SPDC_YDIOUL           0x0d8 0x3c8 0x000 0x4 0x0
+#define MX6SL_PAD_EPDC_GDRL__GPIO2_IO01            0x0d8 0x3c8 0x000 0x5 0x0
+#define MX6SL_PAD_EPDC_GDRL__SD2_WP                0x0d8 0x3c8 0x834 0x6 0x1
+#define MX6SL_PAD_EPDC_GDSP__EPDC_GDSP             0x0dc 0x3cc 0x000 0x0 0x0
+#define MX6SL_PAD_EPDC_GDSP__PWM4_OUT              0x0dc 0x3cc 0x000 0x1 0x0
+#define MX6SL_PAD_EPDC_GDSP__SPDC_YDIODR           0x0dc 0x3cc 0x000 0x2 0x0
+#define MX6SL_PAD_EPDC_GDSP__CSI_VSYNC             0x0dc 0x3cc 0x678 0x3 0x1
+#define MX6SL_PAD_EPDC_GDSP__SPDC_YDIODL           0x0dc 0x3cc 0x000 0x4 0x0
+#define MX6SL_PAD_EPDC_GDSP__GPIO2_IO02            0x0dc 0x3cc 0x000 0x5 0x0
+#define MX6SL_PAD_EPDC_GDSP__SD2_CD_B              0x0dc 0x3cc 0x830 0x6 0x1
+#define MX6SL_PAD_EPDC_PWRCOM__EPDC_PWR_COM        0x0e0 0x3d0 0x000 0x0 0x0
+#define MX6SL_PAD_EPDC_PWRCOM__SD4_DATA0           0x0e0 0x3d0 0x85c 0x1 0x0
+#define MX6SL_PAD_EPDC_PWRCOM__LCD_DATA20          0x0e0 0x3d0 0x7c8 0x2 0x0
+#define MX6SL_PAD_EPDC_PWRCOM__EIM_BCLK            0x0e0 0x3d0 0x000 0x3 0x0
+#define MX6SL_PAD_EPDC_PWRCOM__USB_OTG1_ID         0x0e0 0x3d0 0x5dc 0x4 0x0
+#define MX6SL_PAD_EPDC_PWRCOM__GPIO2_IO11          0x0e0 0x3d0 0x000 0x5 0x0
+#define MX6SL_PAD_EPDC_PWRCOM__SD3_RESET           0x0e0 0x3d0 0x000 0x6 0x0
+#define MX6SL_PAD_EPDC_PWRCTRL0__EPDC_PWR_CTRL0    0x0e4 0x3d4 0x000 0x0 0x0
+#define MX6SL_PAD_EPDC_PWRCTRL0__AUD5_RXC          0x0e4 0x3d4 0x604 0x1 0x0
+#define MX6SL_PAD_EPDC_PWRCTRL0__LCD_DATA16        0x0e4 0x3d4 0x7b8 0x2 0x0
+#define MX6SL_PAD_EPDC_PWRCTRL0__EIM_RW            0x0e4 0x3d4 0x000 0x3 0x0
+#define MX6SL_PAD_EPDC_PWRCTRL0__SPDC_YCKL         0x0e4 0x3d4 0x000 0x4 0x0
+#define MX6SL_PAD_EPDC_PWRCTRL0__GPIO2_IO07        0x0e4 0x3d4 0x000 0x5 0x0
+#define MX6SL_PAD_EPDC_PWRCTRL0__SD4_RESET         0x0e4 0x3d4 0x000 0x6 0x0
+#define MX6SL_PAD_EPDC_PWRCTRL1__EPDC_PWR_CTRL1    0x0e8 0x3d8 0x000 0x0 0x0
+#define MX6SL_PAD_EPDC_PWRCTRL1__AUD5_TXFS         0x0e8 0x3d8 0x610 0x1 0x0
+#define MX6SL_PAD_EPDC_PWRCTRL1__LCD_DATA17        0x0e8 0x3d8 0x7bc 0x2 0x0
+#define MX6SL_PAD_EPDC_PWRCTRL1__EIM_OE_B          0x0e8 0x3d8 0x000 0x3 0x0
+#define MX6SL_PAD_EPDC_PWRCTRL1__SPDC_YOEL         0x0e8 0x3d8 0x000 0x4 0x0
+#define MX6SL_PAD_EPDC_PWRCTRL1__GPIO2_IO08        0x0e8 0x3d8 0x000 0x5 0x0
+#define MX6SL_PAD_EPDC_PWRCTRL1__SD4_VSELECT       0x0e8 0x3d8 0x000 0x6 0x0
+#define MX6SL_PAD_EPDC_PWRCTRL2__EPDC_PWR_CTRL2    0x0ec 0x3dc 0x000 0x0 0x0
+#define MX6SL_PAD_EPDC_PWRCTRL2__AUD5_TXD          0x0ec 0x3dc 0x600 0x1 0x0
+#define MX6SL_PAD_EPDC_PWRCTRL2__LCD_DATA18        0x0ec 0x3dc 0x7c0 0x2 0x0
+#define MX6SL_PAD_EPDC_PWRCTRL2__EIM_CS0_B         0x0ec 0x3dc 0x000 0x3 0x0
+#define MX6SL_PAD_EPDC_PWRCTRL2__SPDC_YDIOUL       0x0ec 0x3dc 0x000 0x4 0x0
+#define MX6SL_PAD_EPDC_PWRCTRL2__GPIO2_IO09        0x0ec 0x3dc 0x000 0x5 0x0
+#define MX6SL_PAD_EPDC_PWRCTRL2__SD4_WP            0x0ec 0x3dc 0x87c 0x6 0x1
+#define MX6SL_PAD_EPDC_PWRCTRL3__EPDC_PWR_CTRL3    0x0f0 0x3e0 0x000 0x0 0x0
+#define MX6SL_PAD_EPDC_PWRCTRL3__AUD5_TXC          0x0f0 0x3e0 0x60c 0x1 0x0
+#define MX6SL_PAD_EPDC_PWRCTRL3__LCD_DATA19        0x0f0 0x3e0 0x7c4 0x2 0x0
+#define MX6SL_PAD_EPDC_PWRCTRL3__EIM_CS1_B         0x0f0 0x3e0 0x000 0x3 0x0
+#define MX6SL_PAD_EPDC_PWRCTRL3__SPDC_YDIODL       0x0f0 0x3e0 0x000 0x4 0x0
+#define MX6SL_PAD_EPDC_PWRCTRL3__GPIO2_IO10        0x0f0 0x3e0 0x000 0x5 0x0
+#define MX6SL_PAD_EPDC_PWRCTRL3__SD4_CD_B          0x0f0 0x3e0 0x854 0x6 0x1
+#define MX6SL_PAD_EPDC_PWRINT__EPDC_PWR_IRQ        0x0f4 0x3e4 0x6e8 0x0 0x1
+#define MX6SL_PAD_EPDC_PWRINT__SD4_DATA1           0x0f4 0x3e4 0x860 0x1 0x0
+#define MX6SL_PAD_EPDC_PWRINT__LCD_DATA21          0x0f4 0x3e4 0x7cc 0x2 0x0
+#define MX6SL_PAD_EPDC_PWRINT__EIM_ACLK_FREERUN    0x0f4 0x3e4 0x000 0x3 0x0
+#define MX6SL_PAD_EPDC_PWRINT__USB_OTG2_ID         0x0f4 0x3e4 0x5e0 0x4 0x0
+#define MX6SL_PAD_EPDC_PWRINT__GPIO2_IO12          0x0f4 0x3e4 0x000 0x5 0x0
+#define MX6SL_PAD_EPDC_PWRINT__SD3_VSELECT         0x0f4 0x3e4 0x000 0x6 0x0
+#define MX6SL_PAD_EPDC_PWRSTAT__EPDC_PWR_STAT      0x0f8 0x3e8 0x6ec 0x0 0x1
+#define MX6SL_PAD_EPDC_PWRSTAT__SD4_DATA2          0x0f8 0x3e8 0x864 0x1 0x0
+#define MX6SL_PAD_EPDC_PWRSTAT__LCD_DATA22         0x0f8 0x3e8 0x7d0 0x2 0x0
+#define MX6SL_PAD_EPDC_PWRSTAT__EIM_WAIT_B         0x0f8 0x3e8 0x884 0x3 0x0
+#define MX6SL_PAD_EPDC_PWRSTAT__ARM_EVENTI         0x0f8 0x3e8 0x000 0x4 0x0
+#define MX6SL_PAD_EPDC_PWRSTAT__GPIO2_IO13         0x0f8 0x3e8 0x000 0x5 0x0
+#define MX6SL_PAD_EPDC_PWRSTAT__SD3_WP             0x0f8 0x3e8 0x84c 0x6 0x0
+#define MX6SL_PAD_EPDC_PWRWAKEUP__EPDC_PWR_WAKE    0x0fc 0x3ec 0x000 0x0 0x0
+#define MX6SL_PAD_EPDC_PWRWAKEUP__SD4_DATA3        0x0fc 0x3ec 0x868 0x1 0x0
+#define MX6SL_PAD_EPDC_PWRWAKEUP__LCD_DATA23       0x0fc 0x3ec 0x7d4 0x2 0x0
+#define MX6SL_PAD_EPDC_PWRWAKEUP__EIM_DTACK_B      0x0fc 0x3ec 0x880 0x3 0x0
+#define MX6SL_PAD_EPDC_PWRWAKEUP__ARM_EVENTO       0x0fc 0x3ec 0x000 0x4 0x0
+#define MX6SL_PAD_EPDC_PWRWAKEUP__GPIO2_IO14       0x0fc 0x3ec 0x000 0x5 0x0
+#define MX6SL_PAD_EPDC_PWRWAKEUP__SD3_CD_B         0x0fc 0x3ec 0x838 0x6 0x0
+#define MX6SL_PAD_EPDC_SDCE0__EPDC_SDCE0           0x100 0x3f0 0x000 0x0 0x0
+#define MX6SL_PAD_EPDC_SDCE0__ECSPI2_SS1           0x100 0x3f0 0x6ac 0x1 0x0
+#define MX6SL_PAD_EPDC_SDCE0__PWM3_OUT             0x100 0x3f0 0x000 0x2 0x0
+#define MX6SL_PAD_EPDC_SDCE0__EIM_CS2_B            0x100 0x3f0 0x000 0x3 0x0
+#define MX6SL_PAD_EPDC_SDCE0__SPDC_YCKR            0x100 0x3f0 0x000 0x4 0x0
+#define MX6SL_PAD_EPDC_SDCE0__GPIO1_IO27           0x100 0x3f0 0x000 0x5 0x0
+#define MX6SL_PAD_EPDC_SDCE1__EPDC_SDCE1           0x104 0x3f4 0x000 0x0 0x0
+#define MX6SL_PAD_EPDC_SDCE1__WDOG2_B              0x104 0x3f4 0x000 0x1 0x0
+#define MX6SL_PAD_EPDC_SDCE1__PWM4_OUT             0x104 0x3f4 0x000 0x2 0x0
+#define MX6SL_PAD_EPDC_SDCE1__EIM_LBA_B            0x104 0x3f4 0x000 0x3 0x0
+#define MX6SL_PAD_EPDC_SDCE1__SPDC_YOER            0x104 0x3f4 0x000 0x4 0x0
+#define MX6SL_PAD_EPDC_SDCE1__GPIO1_IO28           0x104 0x3f4 0x000 0x5 0x0
+#define MX6SL_PAD_EPDC_SDCE2__EPDC_SDCE2           0x108 0x3f8 0x000 0x0 0x0
+#define MX6SL_PAD_EPDC_SDCE2__I2C3_SCL             0x108 0x3f8 0x72c 0x1 0x1
+#define MX6SL_PAD_EPDC_SDCE2__PWM1_OUT             0x108 0x3f8 0x000 0x2 0x0
+#define MX6SL_PAD_EPDC_SDCE2__EIM_EB0_B            0x108 0x3f8 0x000 0x3 0x0
+#define MX6SL_PAD_EPDC_SDCE2__SPDC_YDIOUR          0x108 0x3f8 0x000 0x4 0x0
+#define MX6SL_PAD_EPDC_SDCE2__GPIO1_IO29           0x108 0x3f8 0x000 0x5 0x0
+#define MX6SL_PAD_EPDC_SDCE3__EPDC_SDCE3           0x10c 0x3fc 0x000 0x0 0x0
+#define MX6SL_PAD_EPDC_SDCE3__I2C3_SDA             0x10c 0x3fc 0x730 0x1 0x1
+#define MX6SL_PAD_EPDC_SDCE3__PWM2_OUT             0x10c 0x3fc 0x000 0x2 0x0
+#define MX6SL_PAD_EPDC_SDCE3__EIM_EB1_B            0x10c 0x3fc 0x000 0x3 0x0
+#define MX6SL_PAD_EPDC_SDCE3__SPDC_YDIODR          0x10c 0x3fc 0x000 0x4 0x0
+#define MX6SL_PAD_EPDC_SDCE3__GPIO1_IO30           0x10c 0x3fc 0x000 0x5 0x0
+#define MX6SL_PAD_EPDC_SDCLK__EPDC_SDCLK_P         0x110 0x400 0x000 0x0 0x0
+#define MX6SL_PAD_EPDC_SDCLK__ECSPI2_MOSI          0x110 0x400 0x6a4 0x1 0x1
+#define MX6SL_PAD_EPDC_SDCLK__I2C2_SCL             0x110 0x400 0x724 0x2 0x0
+#define MX6SL_PAD_EPDC_SDCLK__CSI_DATA08           0x110 0x400 0x650 0x3 0x0
+#define MX6SL_PAD_EPDC_SDCLK__SPDC_CL              0x110 0x400 0x000 0x4 0x0
+#define MX6SL_PAD_EPDC_SDCLK__GPIO1_IO23           0x110 0x400 0x000 0x5 0x0
+#define MX6SL_PAD_EPDC_SDLE__EPDC_SDLE             0x114 0x404 0x000 0x0 0x0
+#define MX6SL_PAD_EPDC_SDLE__ECSPI2_MISO           0x114 0x404 0x6a0 0x1 0x1
+#define MX6SL_PAD_EPDC_SDLE__I2C2_SDA              0x114 0x404 0x728 0x2 0x0
+#define MX6SL_PAD_EPDC_SDLE__CSI_DATA09            0x114 0x404 0x654 0x3 0x0
+#define MX6SL_PAD_EPDC_SDLE__SPDC_LD               0x114 0x404 0x000 0x4 0x0
+#define MX6SL_PAD_EPDC_SDLE__GPIO1_IO24            0x114 0x404 0x000 0x5 0x0
+#define MX6SL_PAD_EPDC_SDOE__EPDC_SDOE             0x118 0x408 0x000 0x0 0x0
+#define MX6SL_PAD_EPDC_SDOE__ECSPI2_SS0            0x118 0x408 0x6a8 0x1 0x1
+#define MX6SL_PAD_EPDC_SDOE__SPDC_XDIOR            0x118 0x408 0x000 0x2 0x0
+#define MX6SL_PAD_EPDC_SDOE__CSI_DATA10            0x118 0x408 0x658 0x3 0x0
+#define MX6SL_PAD_EPDC_SDOE__SPDC_XDIOL            0x118 0x408 0x000 0x4 0x0
+#define MX6SL_PAD_EPDC_SDOE__GPIO1_IO25            0x118 0x408 0x000 0x5 0x0
+#define MX6SL_PAD_EPDC_SDSHR__EPDC_SDSHR           0x11c 0x40c 0x000 0x0 0x0
+#define MX6SL_PAD_EPDC_SDSHR__ECSPI2_SCLK          0x11c 0x40c 0x69c 0x1 0x1
+#define MX6SL_PAD_EPDC_SDSHR__EPDC_SDCE4           0x11c 0x40c 0x000 0x2 0x0
+#define MX6SL_PAD_EPDC_SDSHR__CSI_DATA11           0x11c 0x40c 0x65c 0x3 0x0
+#define MX6SL_PAD_EPDC_SDSHR__SPDC_XDIOR           0x11c 0x40c 0x000 0x4 0x0
+#define MX6SL_PAD_EPDC_SDSHR__GPIO1_IO26           0x11c 0x40c 0x000 0x5 0x0
+#define MX6SL_PAD_EPDC_VCOM0__EPDC_VCOM0           0x120 0x410 0x000 0x0 0x0
+#define MX6SL_PAD_EPDC_VCOM0__AUD5_RXFS            0x120 0x410 0x608 0x1 0x0
+#define MX6SL_PAD_EPDC_VCOM0__UART3_RX_DATA        0x120 0x410 0x80c 0x2 0x4
+#define MX6SL_PAD_EPDC_VCOM0__UART3_TX_DATA        0x120 0x410 0x000 0x2 0x0
+#define MX6SL_PAD_EPDC_VCOM0__EIM_ADDR24           0x120 0x410 0x000 0x3 0x0
+#define MX6SL_PAD_EPDC_VCOM0__SPDC_VCOM0           0x120 0x410 0x000 0x4 0x0
+#define MX6SL_PAD_EPDC_VCOM0__GPIO2_IO03           0x120 0x410 0x000 0x5 0x0
+#define MX6SL_PAD_EPDC_VCOM0__EPDC_SDCE5           0x120 0x410 0x000 0x6 0x0
+#define MX6SL_PAD_EPDC_VCOM1__EPDC_VCOM1           0x124 0x414 0x000 0x0 0x0
+#define MX6SL_PAD_EPDC_VCOM1__AUD5_RXD             0x124 0x414 0x5fc 0x1 0x0
+#define MX6SL_PAD_EPDC_VCOM1__UART3_TX_DATA        0x124 0x414 0x000 0x2 0x0
+#define MX6SL_PAD_EPDC_VCOM1__UART3_RX_DATA        0x124 0x414 0x80c 0x2 0x5
+#define MX6SL_PAD_EPDC_VCOM1__EIM_ADDR25           0x124 0x414 0x000 0x3 0x0
+#define MX6SL_PAD_EPDC_VCOM1__SPDC_VCOM1           0x124 0x414 0x000 0x4 0x0
+#define MX6SL_PAD_EPDC_VCOM1__GPIO2_IO04           0x124 0x414 0x000 0x5 0x0
+#define MX6SL_PAD_EPDC_VCOM1__EPDC_SDCE6           0x124 0x414 0x000 0x6 0x0
+#define MX6SL_PAD_FEC_CRS_DV__FEC_RX_DV            0x128 0x418 0x704 0x0 0x1
+#define MX6SL_PAD_FEC_CRS_DV__SD4_DATA1            0x128 0x418 0x860 0x1 0x1
+#define MX6SL_PAD_FEC_CRS_DV__AUD6_TXC             0x128 0x418 0x624 0x2 0x0
+#define MX6SL_PAD_FEC_CRS_DV__ECSPI4_MISO          0x128 0x418 0x6d4 0x3 0x1
+#define MX6SL_PAD_FEC_CRS_DV__GPT_COMPARE2         0x128 0x418 0x000 0x4 0x0
+#define MX6SL_PAD_FEC_CRS_DV__GPIO4_IO25           0x128 0x418 0x000 0x5 0x0
+#define MX6SL_PAD_FEC_CRS_DV__ARM_TRACE31          0x128 0x418 0x000 0x6 0x0
+#define MX6SL_PAD_FEC_MDC__FEC_MDC                 0x12c 0x41c 0x000 0x0 0x0
+#define MX6SL_PAD_FEC_MDC__SD4_DATA4               0x12c 0x41c 0x86c 0x1 0x0
+#define MX6SL_PAD_FEC_MDC__AUDIO_CLK_OUT           0x12c 0x41c 0x000 0x2 0x0
+#define MX6SL_PAD_FEC_MDC__SD1_RESET               0x12c 0x41c 0x000 0x3 0x0
+#define MX6SL_PAD_FEC_MDC__SD3_RESET               0x12c 0x41c 0x000 0x4 0x0
+#define MX6SL_PAD_FEC_MDC__GPIO4_IO23              0x12c 0x41c 0x000 0x5 0x0
+#define MX6SL_PAD_FEC_MDC__ARM_TRACE29             0x12c 0x41c 0x000 0x6 0x0
+#define MX6SL_PAD_FEC_MDIO__FEC_MDIO               0x130 0x420 0x6f4 0x0 0x1
+#define MX6SL_PAD_FEC_MDIO__SD4_CLK                0x130 0x420 0x850 0x1 0x1
+#define MX6SL_PAD_FEC_MDIO__AUD6_RXFS              0x130 0x420 0x620 0x2 0x0
+#define MX6SL_PAD_FEC_MDIO__ECSPI4_SS0             0x130 0x420 0x6dc 0x3 0x1
+#define MX6SL_PAD_FEC_MDIO__GPT_CAPTURE1           0x130 0x420 0x710 0x4 0x0
+#define MX6SL_PAD_FEC_MDIO__GPIO4_IO20             0x130 0x420 0x000 0x5 0x0
+#define MX6SL_PAD_FEC_MDIO__ARM_TRACE26            0x130 0x420 0x000 0x6 0x0
+#define MX6SL_PAD_FEC_REF_CLK__FEC_REF_OUT         0x134 0x424 0x000 0x0 0x0
+#define MX6SL_PAD_FEC_REF_CLK__SD4_RESET           0x134 0x424 0x000 0x1 0x0
+#define MX6SL_PAD_FEC_REF_CLK__WDOG1_B             0x134 0x424 0x000 0x2 0x0
+#define MX6SL_PAD_FEC_REF_CLK__PWM4_OUT            0x134 0x424 0x000 0x3 0x0
+#define MX6SL_PAD_FEC_REF_CLK__CCM_PMIC_READY      0x134 0x424 0x62c 0x4 0x0
+#define MX6SL_PAD_FEC_REF_CLK__GPIO4_IO26          0x134 0x424 0x000 0x5 0x0
+#define MX6SL_PAD_FEC_REF_CLK__SPDIF_EXT_CLK       0x134 0x424 0x7f4 0x6 0x2
+#define MX6SL_PAD_FEC_RX_ER__FEC_RX_ER             0x138 0x428 0x708 0x0 0x1
+#define MX6SL_PAD_FEC_RX_ER__SD4_DATA0             0x138 0x428 0x85c 0x1 0x1
+#define MX6SL_PAD_FEC_RX_ER__AUD6_RXD              0x138 0x428 0x614 0x2 0x0
+#define MX6SL_PAD_FEC_RX_ER__ECSPI4_MOSI           0x138 0x428 0x6d8 0x3 0x1
+#define MX6SL_PAD_FEC_RX_ER__GPT_COMPARE1          0x138 0x428 0x000 0x4 0x0
+#define MX6SL_PAD_FEC_RX_ER__GPIO4_IO19            0x138 0x428 0x000 0x5 0x0
+#define MX6SL_PAD_FEC_RX_ER__ARM_TRACE25           0x138 0x428 0x000 0x6 0x0
+#define MX6SL_PAD_FEC_RXD0__FEC_RX_DATA0           0x13c 0x42c 0x6f8 0x0 0x0
+#define MX6SL_PAD_FEC_RXD0__SD4_DATA5              0x13c 0x42c 0x870 0x1 0x0
+#define MX6SL_PAD_FEC_RXD0__USB_OTG1_ID            0x13c 0x42c 0x5dc 0x2 0x1
+#define MX6SL_PAD_FEC_RXD0__SD1_VSELECT            0x13c 0x42c 0x000 0x3 0x0
+#define MX6SL_PAD_FEC_RXD0__SD3_VSELECT            0x13c 0x42c 0x000 0x4 0x0
+#define MX6SL_PAD_FEC_RXD0__GPIO4_IO17             0x13c 0x42c 0x000 0x5 0x0
+#define MX6SL_PAD_FEC_RXD0__ARM_TRACE24            0x13c 0x42c 0x000 0x6 0x0
+#define MX6SL_PAD_FEC_RXD1__FEC_RX_DATA1           0x140 0x430 0x6fc 0x0 0x1
+#define MX6SL_PAD_FEC_RXD1__SD4_DATA2              0x140 0x430 0x864 0x1 0x1
+#define MX6SL_PAD_FEC_RXD1__AUD6_TXFS              0x140 0x430 0x628 0x2 0x0
+#define MX6SL_PAD_FEC_RXD1__ECSPI4_SS1             0x140 0x430 0x6e0 0x3 0x1
+#define MX6SL_PAD_FEC_RXD1__GPT_COMPARE3           0x140 0x430 0x000 0x4 0x0
+#define MX6SL_PAD_FEC_RXD1__GPIO4_IO18             0x140 0x430 0x000 0x5 0x0
+#define MX6SL_PAD_FEC_RXD1__FEC_COL                0x140 0x430 0x6f0 0x6 0x0
+#define MX6SL_PAD_FEC_TX_CLK__FEC_TX_CLK           0x144 0x434 0x70c 0x0 0x1
+#define MX6SL_PAD_FEC_TX_CLK__SD4_CMD              0x144 0x434 0x858 0x1 0x1
+#define MX6SL_PAD_FEC_TX_CLK__AUD6_RXC             0x144 0x434 0x61c 0x2 0x0
+#define MX6SL_PAD_FEC_TX_CLK__ECSPI4_SCLK          0x144 0x434 0x6d0 0x3 0x1
+#define MX6SL_PAD_FEC_TX_CLK__GPT_CAPTURE2         0x144 0x434 0x714 0x4 0x0
+#define MX6SL_PAD_FEC_TX_CLK__GPIO4_IO21           0x144 0x434 0x000 0x5 0x0
+#define MX6SL_PAD_FEC_TX_CLK__ARM_TRACE27          0x144 0x434 0x000 0x6 0x0
+#define MX6SL_PAD_FEC_TX_EN__FEC_TX_EN             0x148 0x438 0x000 0x0 0x0
+#define MX6SL_PAD_FEC_TX_EN__SD4_DATA6             0x148 0x438 0x874 0x1 0x0
+#define MX6SL_PAD_FEC_TX_EN__SPDIF_IN              0x148 0x438 0x7f0 0x2 0x0
+#define MX6SL_PAD_FEC_TX_EN__SD1_WP                0x148 0x438 0x82c 0x3 0x1
+#define MX6SL_PAD_FEC_TX_EN__SD3_WP                0x148 0x438 0x84c 0x4 0x1
+#define MX6SL_PAD_FEC_TX_EN__GPIO4_IO22            0x148 0x438 0x000 0x5 0x0
+#define MX6SL_PAD_FEC_TX_EN__ARM_TRACE28           0x148 0x438 0x000 0x6 0x0
+#define MX6SL_PAD_FEC_TXD0__FEC_TX_DATA0           0x14c 0x43c 0x000 0x0 0x0
+#define MX6SL_PAD_FEC_TXD0__SD4_DATA3              0x14c 0x43c 0x868 0x1 0x1
+#define MX6SL_PAD_FEC_TXD0__AUD6_TXD               0x14c 0x43c 0x618 0x2 0x0
+#define MX6SL_PAD_FEC_TXD0__ECSPI4_SS2             0x14c 0x43c 0x6e4 0x3 0x1
+#define MX6SL_PAD_FEC_TXD0__GPT_CLKIN              0x14c 0x43c 0x718 0x4 0x0
+#define MX6SL_PAD_FEC_TXD0__GPIO4_IO24             0x14c 0x43c 0x000 0x5 0x0
+#define MX6SL_PAD_FEC_TXD0__ARM_TRACE30            0x14c 0x43c 0x000 0x6 0x0
+#define MX6SL_PAD_FEC_TXD1__FEC_TX_DATA1           0x150 0x440 0x000 0x0 0x0
+#define MX6SL_PAD_FEC_TXD1__SD4_DATA7              0x150 0x440 0x878 0x1 0x0
+#define MX6SL_PAD_FEC_TXD1__SPDIF_OUT              0x150 0x440 0x000 0x2 0x0
+#define MX6SL_PAD_FEC_TXD1__SD1_CD_B               0x150 0x440 0x828 0x3 0x1
+#define MX6SL_PAD_FEC_TXD1__SD3_CD_B               0x150 0x440 0x838 0x4 0x1
+#define MX6SL_PAD_FEC_TXD1__GPIO4_IO16             0x150 0x440 0x000 0x5 0x0
+#define MX6SL_PAD_FEC_TXD1__FEC_RX_CLK             0x150 0x440 0x700 0x6 0x0
+#define MX6SL_PAD_HSIC_DAT__USB_H_DATA             0x154 0x444 0x000 0x0 0x0
+#define MX6SL_PAD_HSIC_DAT__I2C1_SCL               0x154 0x444 0x71c 0x1 0x1
+#define MX6SL_PAD_HSIC_DAT__PWM1_OUT               0x154 0x444 0x000 0x2 0x0
+#define MX6SL_PAD_HSIC_DAT__XTALOSC_REF_CLK_24M    0x154 0x444 0x000 0x3 0x0
+#define MX6SL_PAD_HSIC_DAT__GPIO3_IO19             0x154 0x444 0x000 0x5 0x0
+#define MX6SL_PAD_HSIC_STROBE__USB_H_STROBE        0x158 0x448 0x000 0x0 0x0
+#define MX6SL_PAD_HSIC_STROBE__I2C1_SDA            0x158 0x448 0x720 0x1 0x1
+#define MX6SL_PAD_HSIC_STROBE__PWM2_OUT            0x158 0x448 0x000 0x2 0x0
+#define MX6SL_PAD_HSIC_STROBE__XTALOSC_REF_CLK_32K 0x158 0x448 0x000 0x3 0x0
+#define MX6SL_PAD_HSIC_STROBE__GPIO3_IO20          0x158 0x448 0x000 0x5 0x0
+#define MX6SL_PAD_I2C1_SCL__I2C1_SCL               0x15c 0x44c 0x71c 0x0 0x2
+#define MX6SL_PAD_I2C1_SCL__UART1_RTS_B            0x15c 0x44c 0x7f8 0x1 0x0
+#define MX6SL_PAD_I2C1_SCL__UART1_CTS_B            0x15c 0x44c 0x000 0x1 0x0
+#define MX6SL_PAD_I2C1_SCL__ECSPI3_SS2             0x15c 0x44c 0x6c8 0x2 0x1
+#define MX6SL_PAD_I2C1_SCL__FEC_RX_DATA0           0x15c 0x44c 0x6f8 0x3 0x1
+#define MX6SL_PAD_I2C1_SCL__SD3_RESET              0x15c 0x44c 0x000 0x4 0x0
+#define MX6SL_PAD_I2C1_SCL__GPIO3_IO12             0x15c 0x44c 0x000 0x5 0x0
+#define MX6SL_PAD_I2C1_SCL__ECSPI1_SS1             0x15c 0x44c 0x690 0x6 0x0
+#define MX6SL_PAD_I2C1_SDA__I2C1_SDA               0x160 0x450 0x720 0x0 0x2
+#define MX6SL_PAD_I2C1_SDA__UART1_CTS_B            0x160 0x450 0x000 0x1 0x0
+#define MX6SL_PAD_I2C1_SDA__UART1_RTS_B            0x160 0x450 0x7f8 0x1 0x1
+#define MX6SL_PAD_I2C1_SDA__ECSPI3_SS3             0x160 0x450 0x6cc 0x2 0x1
+#define MX6SL_PAD_I2C1_SDA__FEC_TX_EN              0x160 0x450 0x000 0x3 0x0
+#define MX6SL_PAD_I2C1_SDA__SD3_VSELECT            0x160 0x450 0x000 0x4 0x0
+#define MX6SL_PAD_I2C1_SDA__GPIO3_IO13             0x160 0x450 0x000 0x5 0x0
+#define MX6SL_PAD_I2C1_SDA__ECSPI1_SS2             0x160 0x450 0x694 0x6 0x0
+#define MX6SL_PAD_I2C2_SCL__I2C2_SCL               0x164 0x454 0x724 0x0 0x1
+#define MX6SL_PAD_I2C2_SCL__AUD4_RXFS              0x164 0x454 0x5f0 0x1 0x0
+#define MX6SL_PAD_I2C2_SCL__SPDIF_IN               0x164 0x454 0x7f0 0x2 0x1
+#define MX6SL_PAD_I2C2_SCL__FEC_TX_DATA1           0x164 0x454 0x000 0x3 0x0
+#define MX6SL_PAD_I2C2_SCL__SD3_WP                 0x164 0x454 0x84c 0x4 0x2
+#define MX6SL_PAD_I2C2_SCL__GPIO3_IO14             0x164 0x454 0x000 0x5 0x0
+#define MX6SL_PAD_I2C2_SCL__ECSPI1_RDY             0x164 0x454 0x680 0x6 0x0
+#define MX6SL_PAD_I2C2_SDA__I2C2_SDA               0x168 0x458 0x728 0x0 0x1
+#define MX6SL_PAD_I2C2_SDA__AUD4_RXC               0x168 0x458 0x5ec 0x1 0x0
+#define MX6SL_PAD_I2C2_SDA__SPDIF_OUT              0x168 0x458 0x000 0x2 0x0
+#define MX6SL_PAD_I2C2_SDA__FEC_REF_OUT            0x168 0x458 0x000 0x3 0x0
+#define MX6SL_PAD_I2C2_SDA__SD3_CD_B               0x168 0x458 0x838 0x4 0x2
+#define MX6SL_PAD_I2C2_SDA__GPIO3_IO15             0x168 0x458 0x000 0x5 0x0
+#define MX6SL_PAD_KEY_COL0__KEY_COL0               0x16c 0x474 0x734 0x0 0x0
+#define MX6SL_PAD_KEY_COL0__I2C2_SCL               0x16c 0x474 0x724 0x1 0x2
+#define MX6SL_PAD_KEY_COL0__LCD_DATA00             0x16c 0x474 0x778 0x2 0x0
+#define MX6SL_PAD_KEY_COL0__EIM_AD00               0x16c 0x474 0x000 0x3 0x0
+#define MX6SL_PAD_KEY_COL0__SD1_CD_B               0x16c 0x474 0x828 0x4 0x2
+#define MX6SL_PAD_KEY_COL0__GPIO3_IO24             0x16c 0x474 0x000 0x5 0x0
+#define MX6SL_PAD_KEY_COL1__KEY_COL1               0x170 0x478 0x738 0x0 0x0
+#define MX6SL_PAD_KEY_COL1__ECSPI4_MOSI            0x170 0x478 0x6d8 0x1 0x2
+#define MX6SL_PAD_KEY_COL1__LCD_DATA02             0x170 0x478 0x780 0x2 0x0
+#define MX6SL_PAD_KEY_COL1__EIM_AD02               0x170 0x478 0x000 0x3 0x0
+#define MX6SL_PAD_KEY_COL1__SD3_DATA4              0x170 0x478 0x83c 0x4 0x0
+#define MX6SL_PAD_KEY_COL1__GPIO3_IO26             0x170 0x478 0x000 0x5 0x0
+#define MX6SL_PAD_KEY_COL2__KEY_COL2               0x174 0x47c 0x73c 0x0 0x0
+#define MX6SL_PAD_KEY_COL2__ECSPI4_SS0             0x174 0x47c 0x6dc 0x1 0x2
+#define MX6SL_PAD_KEY_COL2__LCD_DATA04             0x174 0x47c 0x788 0x2 0x0
+#define MX6SL_PAD_KEY_COL2__EIM_AD04               0x174 0x47c 0x000 0x3 0x0
+#define MX6SL_PAD_KEY_COL2__SD3_DATA6              0x174 0x47c 0x844 0x4 0x0
+#define MX6SL_PAD_KEY_COL2__GPIO3_IO28             0x174 0x47c 0x000 0x5 0x0
+#define MX6SL_PAD_KEY_COL3__KEY_COL3               0x178 0x480 0x740 0x0 0x0
+#define MX6SL_PAD_KEY_COL3__AUD6_RXFS              0x178 0x480 0x620 0x1 0x1
+#define MX6SL_PAD_KEY_COL3__LCD_DATA06             0x178 0x480 0x790 0x2 0x0
+#define MX6SL_PAD_KEY_COL3__EIM_AD06               0x178 0x480 0x000 0x3 0x0
+#define MX6SL_PAD_KEY_COL3__SD4_DATA6              0x178 0x480 0x874 0x4 0x1
+#define MX6SL_PAD_KEY_COL3__GPIO3_IO30             0x178 0x480 0x000 0x5 0x0
+#define MX6SL_PAD_KEY_COL3__SD1_RESET              0x178 0x480 0x000 0x6 0x0
+#define MX6SL_PAD_KEY_COL4__KEY_COL4               0x17c 0x484 0x744 0x0 0x0
+#define MX6SL_PAD_KEY_COL4__AUD6_RXD               0x17c 0x484 0x614 0x1 0x1
+#define MX6SL_PAD_KEY_COL4__LCD_DATA08             0x17c 0x484 0x798 0x2 0x0
+#define MX6SL_PAD_KEY_COL4__EIM_AD08               0x17c 0x484 0x000 0x3 0x0
+#define MX6SL_PAD_KEY_COL4__SD4_CLK                0x17c 0x484 0x850 0x4 0x2
+#define MX6SL_PAD_KEY_COL4__GPIO4_IO00             0x17c 0x484 0x000 0x5 0x0
+#define MX6SL_PAD_KEY_COL4__USB_OTG1_PWR           0x17c 0x484 0x000 0x6 0x0
+#define MX6SL_PAD_KEY_COL5__KEY_COL5               0x180 0x488 0x748 0x0 0x0
+#define MX6SL_PAD_KEY_COL5__AUD6_TXFS              0x180 0x488 0x628 0x1 0x1
+#define MX6SL_PAD_KEY_COL5__LCD_DATA10             0x180 0x488 0x7a0 0x2 0x0
+#define MX6SL_PAD_KEY_COL5__EIM_AD10               0x180 0x488 0x000 0x3 0x0
+#define MX6SL_PAD_KEY_COL5__SD4_DATA0              0x180 0x488 0x85c 0x4 0x2
+#define MX6SL_PAD_KEY_COL5__GPIO4_IO02             0x180 0x488 0x000 0x5 0x0
+#define MX6SL_PAD_KEY_COL5__USB_OTG2_PWR           0x180 0x488 0x000 0x6 0x0
+#define MX6SL_PAD_KEY_COL6__KEY_COL6               0x184 0x48c 0x74c 0x0 0x0
+#define MX6SL_PAD_KEY_COL6__UART4_RX_DATA          0x184 0x48c 0x814 0x1 0x2
+#define MX6SL_PAD_KEY_COL6__UART4_TX_DATA          0x184 0x48c 0x000 0x1 0x0
+#define MX6SL_PAD_KEY_COL6__LCD_DATA12             0x184 0x48c 0x7a8 0x2 0x0
+#define MX6SL_PAD_KEY_COL6__EIM_AD12               0x184 0x48c 0x000 0x3 0x0
+#define MX6SL_PAD_KEY_COL6__SD4_DATA2              0x184 0x48c 0x864 0x4 0x2
+#define MX6SL_PAD_KEY_COL6__GPIO4_IO04             0x184 0x48c 0x000 0x5 0x0
+#define MX6SL_PAD_KEY_COL6__SD3_RESET              0x184 0x48c 0x000 0x6 0x0
+#define MX6SL_PAD_KEY_COL7__KEY_COL7               0x188 0x490 0x750 0x0 0x0
+#define MX6SL_PAD_KEY_COL7__UART4_RTS_B            0x188 0x490 0x810 0x1 0x2
+#define MX6SL_PAD_KEY_COL7__UART4_CTS_B            0x188 0x490 0x000 0x1 0x0
+#define MX6SL_PAD_KEY_COL7__LCD_DATA14             0x188 0x490 0x7b0 0x2 0x0
+#define MX6SL_PAD_KEY_COL7__EIM_AD14               0x188 0x490 0x000 0x3 0x0
+#define MX6SL_PAD_KEY_COL7__SD4_DATA4              0x188 0x490 0x86c 0x4 0x1
+#define MX6SL_PAD_KEY_COL7__GPIO4_IO06             0x188 0x490 0x000 0x5 0x0
+#define MX6SL_PAD_KEY_COL7__SD1_WP                 0x188 0x490 0x82c 0x6 0x2
+#define MX6SL_PAD_KEY_ROW0__KEY_ROW0               0x18c 0x494 0x754 0x0 0x0
+#define MX6SL_PAD_KEY_ROW0__I2C2_SDA               0x18c 0x494 0x728 0x1 0x2
+#define MX6SL_PAD_KEY_ROW0__LCD_DATA01             0x18c 0x494 0x77c 0x2 0x0
+#define MX6SL_PAD_KEY_ROW0__EIM_AD01               0x18c 0x494 0x000 0x3 0x0
+#define MX6SL_PAD_KEY_ROW0__SD1_WP                 0x18c 0x494 0x82c 0x4 0x3
+#define MX6SL_PAD_KEY_ROW0__GPIO3_IO25             0x18c 0x494 0x000 0x5 0x0
+#define MX6SL_PAD_KEY_ROW1__KEY_ROW1               0x190 0x498 0x758 0x0 0x0
+#define MX6SL_PAD_KEY_ROW1__ECSPI4_MISO            0x190 0x498 0x6d4 0x1 0x2
+#define MX6SL_PAD_KEY_ROW1__LCD_DATA03             0x190 0x498 0x784 0x2 0x0
+#define MX6SL_PAD_KEY_ROW1__EIM_AD03               0x190 0x498 0x000 0x3 0x0
+#define MX6SL_PAD_KEY_ROW1__SD3_DATA5              0x190 0x498 0x840 0x4 0x0
+#define MX6SL_PAD_KEY_ROW1__GPIO3_IO27             0x190 0x498 0x000 0x5 0x0
+#define MX6SL_PAD_KEY_ROW2__KEY_ROW2               0x194 0x49c 0x75c 0x0 0x0
+#define MX6SL_PAD_KEY_ROW2__ECSPI4_SCLK            0x194 0x49c 0x6d0 0x1 0x2
+#define MX6SL_PAD_KEY_ROW2__LCD_DATA05             0x194 0x49c 0x78c 0x2 0x0
+#define MX6SL_PAD_KEY_ROW2__EIM_AD05               0x194 0x49c 0x000 0x3 0x0
+#define MX6SL_PAD_KEY_ROW2__SD3_DATA7              0x194 0x49c 0x848 0x4 0x0
+#define MX6SL_PAD_KEY_ROW2__GPIO3_IO29             0x194 0x49c 0x000 0x5 0x0
+#define MX6SL_PAD_KEY_ROW3__KEY_ROW3               0x198 0x4a0 0x760 0x0 0x0
+#define MX6SL_PAD_KEY_ROW3__AUD6_RXC               0x198 0x4a0 0x61c 0x1 0x1
+#define MX6SL_PAD_KEY_ROW3__LCD_DATA07             0x198 0x4a0 0x794 0x2 0x0
+#define MX6SL_PAD_KEY_ROW3__EIM_AD07               0x198 0x4a0 0x000 0x3 0x0
+#define MX6SL_PAD_KEY_ROW3__SD4_DATA7              0x198 0x4a0 0x878 0x4 0x1
+#define MX6SL_PAD_KEY_ROW3__GPIO3_IO31             0x198 0x4a0 0x000 0x5 0x0
+#define MX6SL_PAD_KEY_ROW3__SD1_VSELECT            0x198 0x4a0 0x000 0x6 0x0
+#define MX6SL_PAD_KEY_ROW4__KEY_ROW4               0x19c 0x4a4 0x764 0x0 0x0
+#define MX6SL_PAD_KEY_ROW4__AUD6_TXC               0x19c 0x4a4 0x624 0x1 0x1
+#define MX6SL_PAD_KEY_ROW4__LCD_DATA09             0x19c 0x4a4 0x79c 0x2 0x0
+#define MX6SL_PAD_KEY_ROW4__EIM_AD09               0x19c 0x4a4 0x000 0x3 0x0
+#define MX6SL_PAD_KEY_ROW4__SD4_CMD                0x19c 0x4a4 0x858 0x4 0x2
+#define MX6SL_PAD_KEY_ROW4__GPIO4_IO01             0x19c 0x4a4 0x000 0x5 0x0
+#define MX6SL_PAD_KEY_ROW4__USB_OTG1_OC            0x19c 0x4a4 0x824 0x6 0x1
+#define MX6SL_PAD_KEY_ROW5__KEY_ROW5               0x1a0 0x4a8 0x768 0x0 0x0
+#define MX6SL_PAD_KEY_ROW5__AUD6_TXD               0x1a0 0x4a8 0x618 0x1 0x1
+#define MX6SL_PAD_KEY_ROW5__LCD_DATA11             0x1a0 0x4a8 0x7a4 0x2 0x0
+#define MX6SL_PAD_KEY_ROW5__EIM_AD11               0x1a0 0x4a8 0x000 0x3 0x0
+#define MX6SL_PAD_KEY_ROW5__SD4_DATA1              0x1a0 0x4a8 0x860 0x4 0x2
+#define MX6SL_PAD_KEY_ROW5__GPIO4_IO03             0x1a0 0x4a8 0x000 0x5 0x0
+#define MX6SL_PAD_KEY_ROW5__USB_OTG2_OC            0x1a0 0x4a8 0x820 0x6 0x2
+#define MX6SL_PAD_KEY_ROW6__KEY_ROW6               0x1a4 0x4ac 0x76c 0x0 0x0
+#define MX6SL_PAD_KEY_ROW6__UART4_TX_DATA          0x1a4 0x4ac 0x000 0x1 0x0
+#define MX6SL_PAD_KEY_ROW6__UART4_RX_DATA          0x1a4 0x4ac 0x814 0x1 0x3
+#define MX6SL_PAD_KEY_ROW6__LCD_DATA13             0x1a4 0x4ac 0x7ac 0x2 0x0
+#define MX6SL_PAD_KEY_ROW6__EIM_AD13               0x1a4 0x4ac 0x000 0x3 0x0
+#define MX6SL_PAD_KEY_ROW6__SD4_DATA3              0x1a4 0x4ac 0x868 0x4 0x2
+#define MX6SL_PAD_KEY_ROW6__GPIO4_IO05             0x1a4 0x4ac 0x000 0x5 0x0
+#define MX6SL_PAD_KEY_ROW6__SD3_VSELECT            0x1a4 0x4ac 0x000 0x6 0x0
+#define MX6SL_PAD_KEY_ROW7__KEY_ROW7               0x1a8 0x4b0 0x770 0x0 0x0
+#define MX6SL_PAD_KEY_ROW7__UART4_CTS_B            0x1a8 0x4b0 0x000 0x1 0x0
+#define MX6SL_PAD_KEY_ROW7__UART4_RTS_B            0x1a8 0x4b0 0x810 0x1 0x3
+#define MX6SL_PAD_KEY_ROW7__LCD_DATA15             0x1a8 0x4b0 0x7b4 0x2 0x0
+#define MX6SL_PAD_KEY_ROW7__EIM_AD15               0x1a8 0x4b0 0x000 0x3 0x0
+#define MX6SL_PAD_KEY_ROW7__SD4_DATA5              0x1a8 0x4b0 0x870 0x4 0x1
+#define MX6SL_PAD_KEY_ROW7__GPIO4_IO07             0x1a8 0x4b0 0x000 0x5 0x0
+#define MX6SL_PAD_KEY_ROW7__SD1_CD_B               0x1a8 0x4b0 0x828 0x6 0x3
+#define MX6SL_PAD_LCD_CLK__LCD_CLK                 0x1ac 0x4b4 0x000 0x0 0x0
+#define MX6SL_PAD_LCD_CLK__SD4_DATA4               0x1ac 0x4b4 0x86c 0x1 0x2
+#define MX6SL_PAD_LCD_CLK__LCD_WR_RWN              0x1ac 0x4b4 0x000 0x2 0x0
+#define MX6SL_PAD_LCD_CLK__EIM_RW                  0x1ac 0x4b4 0x000 0x3 0x0
+#define MX6SL_PAD_LCD_CLK__PWM4_OUT                0x1ac 0x4b4 0x000 0x4 0x0
+#define MX6SL_PAD_LCD_CLK__GPIO2_IO15              0x1ac 0x4b4 0x000 0x5 0x0
+#define MX6SL_PAD_LCD_DAT0__LCD_DATA00             0x1b0 0x4b8 0x778 0x0 0x1
+#define MX6SL_PAD_LCD_DAT0__ECSPI1_MOSI            0x1b0 0x4b8 0x688 0x1 0x1
+#define MX6SL_PAD_LCD_DAT0__USB_OTG2_ID            0x1b0 0x4b8 0x5e0 0x2 0x1
+#define MX6SL_PAD_LCD_DAT0__PWM1_OUT               0x1b0 0x4b8 0x000 0x3 0x0
+#define MX6SL_PAD_LCD_DAT0__UART5_DTR_B            0x1b0 0x4b8 0x000 0x4 0x0
+#define MX6SL_PAD_LCD_DAT0__GPIO2_IO20             0x1b0 0x4b8 0x000 0x5 0x0
+#define MX6SL_PAD_LCD_DAT0__ARM_TRACE00            0x1b0 0x4b8 0x000 0x6 0x0
+#define MX6SL_PAD_LCD_DAT0__SRC_BOOT_CFG00         0x1b0 0x4b8 0x000 0x7 0x0
+#define MX6SL_PAD_LCD_DAT1__LCD_DATA01             0x1b4 0x4bc 0x77c 0x0 0x1
+#define MX6SL_PAD_LCD_DAT1__ECSPI1_MISO            0x1b4 0x4bc 0x684 0x1 0x1
+#define MX6SL_PAD_LCD_DAT1__USB_OTG1_ID            0x1b4 0x4bc 0x5dc 0x2 0x2
+#define MX6SL_PAD_LCD_DAT1__PWM2_OUT               0x1b4 0x4bc 0x000 0x3 0x0
+#define MX6SL_PAD_LCD_DAT1__AUD4_RXFS              0x1b4 0x4bc 0x5f0 0x4 0x1
+#define MX6SL_PAD_LCD_DAT1__GPIO2_IO21             0x1b4 0x4bc 0x000 0x5 0x0
+#define MX6SL_PAD_LCD_DAT1__ARM_TRACE01            0x1b4 0x4bc 0x000 0x6 0x0
+#define MX6SL_PAD_LCD_DAT1__SRC_BOOT_CFG01         0x1b4 0x4bc 0x000 0x7 0x0
+#define MX6SL_PAD_LCD_DAT10__LCD_DATA10            0x1b8 0x4c0 0x7a0 0x0 0x1
+#define MX6SL_PAD_LCD_DAT10__KEY_COL1              0x1b8 0x4c0 0x738 0x1 0x1
+#define MX6SL_PAD_LCD_DAT10__CSI_DATA07            0x1b8 0x4c0 0x64c 0x2 0x1
+#define MX6SL_PAD_LCD_DAT10__EIM_DATA04            0x1b8 0x4c0 0x000 0x3 0x0
+#define MX6SL_PAD_LCD_DAT10__ECSPI2_MISO           0x1b8 0x4c0 0x6a0 0x4 0x2
+#define MX6SL_PAD_LCD_DAT10__GPIO2_IO30            0x1b8 0x4c0 0x000 0x5 0x0
+#define MX6SL_PAD_LCD_DAT10__ARM_TRACE10           0x1b8 0x4c0 0x000 0x6 0x0
+#define MX6SL_PAD_LCD_DAT10__SRC_BOOT_CFG10        0x1b8 0x4c0 0x000 0x7 0x0
+#define MX6SL_PAD_LCD_DAT11__LCD_DATA11            0x1bc 0x4c4 0x7a4 0x0 0x1
+#define MX6SL_PAD_LCD_DAT11__KEY_ROW1              0x1bc 0x4c4 0x758 0x1 0x1
+#define MX6SL_PAD_LCD_DAT11__CSI_DATA06            0x1bc 0x4c4 0x648 0x2 0x1
+#define MX6SL_PAD_LCD_DAT11__EIM_DATA05            0x1bc 0x4c4 0x000 0x3 0x0
+#define MX6SL_PAD_LCD_DAT11__ECSPI2_SS1            0x1bc 0x4c4 0x6ac 0x4 0x1
+#define MX6SL_PAD_LCD_DAT11__GPIO2_IO31            0x1bc 0x4c4 0x000 0x5 0x0
+#define MX6SL_PAD_LCD_DAT11__ARM_TRACE11           0x1bc 0x4c4 0x000 0x6 0x0
+#define MX6SL_PAD_LCD_DAT11__SRC_BOOT_CFG11        0x1bc 0x4c4 0x000 0x7 0x0
+#define MX6SL_PAD_LCD_DAT12__LCD_DATA12            0x1c0 0x4c8 0x7a8 0x0 0x1
+#define MX6SL_PAD_LCD_DAT12__KEY_COL2              0x1c0 0x4c8 0x73c 0x1 0x1
+#define MX6SL_PAD_LCD_DAT12__CSI_DATA05            0x1c0 0x4c8 0x644 0x2 0x1
+#define MX6SL_PAD_LCD_DAT12__EIM_DATA06            0x1c0 0x4c8 0x000 0x3 0x0
+#define MX6SL_PAD_LCD_DAT12__UART5_RTS_B           0x1c0 0x4c8 0x818 0x4 0x2
+#define MX6SL_PAD_LCD_DAT12__UART5_CTS_B           0x1c0 0x4c8 0x000 0x4 0x0
+#define MX6SL_PAD_LCD_DAT12__GPIO3_IO00            0x1c0 0x4c8 0x000 0x5 0x0
+#define MX6SL_PAD_LCD_DAT12__ARM_TRACE12           0x1c0 0x4c8 0x000 0x6 0x0
+#define MX6SL_PAD_LCD_DAT12__SRC_BOOT_CFG12        0x1c0 0x4c8 0x000 0x7 0x0
+#define MX6SL_PAD_LCD_DAT13__LCD_DATA13            0x1c4 0x4cc 0x7ac 0x0 0x1
+#define MX6SL_PAD_LCD_DAT13__KEY_ROW2              0x1c4 0x4cc 0x75c 0x1 0x1
+#define MX6SL_PAD_LCD_DAT13__CSI_DATA04            0x1c4 0x4cc 0x640 0x2 0x1
+#define MX6SL_PAD_LCD_DAT13__EIM_DATA07            0x1c4 0x4cc 0x000 0x3 0x0
+#define MX6SL_PAD_LCD_DAT13__UART5_CTS_B           0x1c4 0x4cc 0x000 0x4 0x0
+#define MX6SL_PAD_LCD_DAT13__UART5_RTS_B           0x1c4 0x4cc 0x818 0x4 0x3
+#define MX6SL_PAD_LCD_DAT13__GPIO3_IO01            0x1c4 0x4cc 0x000 0x5 0x0
+#define MX6SL_PAD_LCD_DAT13__ARM_TRACE13           0x1c4 0x4cc 0x000 0x6 0x0
+#define MX6SL_PAD_LCD_DAT13__SRC_BOOT_CFG13        0x1c4 0x4cc 0x000 0x7 0x0
+#define MX6SL_PAD_LCD_DAT14__LCD_DATA14            0x1c8 0x4d0 0x7b0 0x0 0x1
+#define MX6SL_PAD_LCD_DAT14__KEY_COL3              0x1c8 0x4d0 0x740 0x1 0x1
+#define MX6SL_PAD_LCD_DAT14__CSI_DATA03            0x1c8 0x4d0 0x63c 0x2 0x1
+#define MX6SL_PAD_LCD_DAT14__EIM_DATA08            0x1c8 0x4d0 0x000 0x3 0x0
+#define MX6SL_PAD_LCD_DAT14__UART5_RX_DATA         0x1c8 0x4d0 0x81c 0x4 0x2
+#define MX6SL_PAD_LCD_DAT14__UART5_TX_DATA         0x1c8 0x4d0 0x000 0x4 0x0
+#define MX6SL_PAD_LCD_DAT14__GPIO3_IO02            0x1c8 0x4d0 0x000 0x5 0x0
+#define MX6SL_PAD_LCD_DAT14__ARM_TRACE14           0x1c8 0x4d0 0x000 0x6 0x0
+#define MX6SL_PAD_LCD_DAT14__SRC_BOOT_CFG14        0x1c8 0x4d0 0x000 0x7 0x0
+#define MX6SL_PAD_LCD_DAT15__LCD_DATA15            0x1cc 0x4d4 0x7b4 0x0 0x1
+#define MX6SL_PAD_LCD_DAT15__KEY_ROW3              0x1cc 0x4d4 0x760 0x1 0x1
+#define MX6SL_PAD_LCD_DAT15__CSI_DATA02            0x1cc 0x4d4 0x638 0x2 0x1
+#define MX6SL_PAD_LCD_DAT15__EIM_DATA09            0x1cc 0x4d4 0x000 0x3 0x0
+#define MX6SL_PAD_LCD_DAT15__UART5_TX_DATA         0x1cc 0x4d4 0x000 0x4 0x0
+#define MX6SL_PAD_LCD_DAT15__UART5_RX_DATA         0x1cc 0x4d4 0x81c 0x4 0x3
+#define MX6SL_PAD_LCD_DAT15__GPIO3_IO03            0x1cc 0x4d4 0x000 0x5 0x0
+#define MX6SL_PAD_LCD_DAT15__ARM_TRACE15           0x1cc 0x4d4 0x000 0x6 0x0
+#define MX6SL_PAD_LCD_DAT15__SRC_BOOT_CFG15        0x1cc 0x4d4 0x000 0x7 0x0
+#define MX6SL_PAD_LCD_DAT16__LCD_DATA16            0x1d0 0x4d8 0x7b8 0x0 0x1
+#define MX6SL_PAD_LCD_DAT16__KEY_COL4              0x1d0 0x4d8 0x744 0x1 0x1
+#define MX6SL_PAD_LCD_DAT16__CSI_DATA01            0x1d0 0x4d8 0x634 0x2 0x1
+#define MX6SL_PAD_LCD_DAT16__EIM_DATA10            0x1d0 0x4d8 0x000 0x3 0x0
+#define MX6SL_PAD_LCD_DAT16__I2C2_SCL              0x1d0 0x4d8 0x724 0x4 0x3
+#define MX6SL_PAD_LCD_DAT16__GPIO3_IO04            0x1d0 0x4d8 0x000 0x5 0x0
+#define MX6SL_PAD_LCD_DAT16__ARM_TRACE16           0x1d0 0x4d8 0x000 0x6 0x0
+#define MX6SL_PAD_LCD_DAT16__SRC_BOOT_CFG24        0x1d0 0x4d8 0x000 0x7 0x0
+#define MX6SL_PAD_LCD_DAT17__LCD_DATA17            0x1d4 0x4dc 0x7bc 0x0 0x1
+#define MX6SL_PAD_LCD_DAT17__KEY_ROW4              0x1d4 0x4dc 0x764 0x1 0x1
+#define MX6SL_PAD_LCD_DAT17__CSI_DATA00            0x1d4 0x4dc 0x630 0x2 0x1
+#define MX6SL_PAD_LCD_DAT17__EIM_DATA11            0x1d4 0x4dc 0x000 0x3 0x0
+#define MX6SL_PAD_LCD_DAT17__I2C2_SDA              0x1d4 0x4dc 0x728 0x4 0x3
+#define MX6SL_PAD_LCD_DAT17__GPIO3_IO05            0x1d4 0x4dc 0x000 0x5 0x0
+#define MX6SL_PAD_LCD_DAT17__ARM_TRACE17           0x1d4 0x4dc 0x000 0x6 0x0
+#define MX6SL_PAD_LCD_DAT17__SRC_BOOT_CFG25        0x1d4 0x4dc 0x000 0x7 0x0
+#define MX6SL_PAD_LCD_DAT18__LCD_DATA18            0x1d8 0x4e0 0x7c0 0x0 0x1
+#define MX6SL_PAD_LCD_DAT18__KEY_COL5              0x1d8 0x4e0 0x748 0x1 0x1
+#define MX6SL_PAD_LCD_DAT18__CSI_DATA15            0x1d8 0x4e0 0x66c 0x2 0x0
+#define MX6SL_PAD_LCD_DAT18__EIM_DATA12            0x1d8 0x4e0 0x000 0x3 0x0
+#define MX6SL_PAD_LCD_DAT18__GPT_CAPTURE1          0x1d8 0x4e0 0x710 0x4 0x1
+#define MX6SL_PAD_LCD_DAT18__GPIO3_IO06            0x1d8 0x4e0 0x000 0x5 0x0
+#define MX6SL_PAD_LCD_DAT18__ARM_TRACE18           0x1d8 0x4e0 0x000 0x6 0x0
+#define MX6SL_PAD_LCD_DAT18__SRC_BOOT_CFG26        0x1d8 0x4e0 0x000 0x7 0x0
+#define MX6SL_PAD_LCD_DAT19__LCD_DATA19            0x1dc 0x4e4 0x7c4 0x0 0x1
+#define MX6SL_PAD_LCD_DAT19__KEY_ROW5              0x1dc 0x4e4 0x768 0x1 0x1
+#define MX6SL_PAD_LCD_DAT19__CSI_DATA14            0x1dc 0x4e4 0x668 0x2 0x0
+#define MX6SL_PAD_LCD_DAT19__EIM_DATA13            0x1dc 0x4e4 0x000 0x3 0x0
+#define MX6SL_PAD_LCD_DAT19__GPT_CAPTURE2          0x1dc 0x4e4 0x714 0x4 0x1
+#define MX6SL_PAD_LCD_DAT19__GPIO3_IO07            0x1dc 0x4e4 0x000 0x5 0x0
+#define MX6SL_PAD_LCD_DAT19__ARM_TRACE19           0x1dc 0x4e4 0x000 0x6 0x0
+#define MX6SL_PAD_LCD_DAT19__SRC_BOOT_CFG27        0x1dc 0x4e4 0x000 0x7 0x0
+#define MX6SL_PAD_LCD_DAT2__LCD_DATA02             0x1e0 0x4e8 0x780 0x0 0x1
+#define MX6SL_PAD_LCD_DAT2__ECSPI1_SS0             0x1e0 0x4e8 0x68c 0x1 0x1
+#define MX6SL_PAD_LCD_DAT2__EPIT2_OUT              0x1e0 0x4e8 0x000 0x2 0x0
+#define MX6SL_PAD_LCD_DAT2__PWM3_OUT               0x1e0 0x4e8 0x000 0x3 0x0
+#define MX6SL_PAD_LCD_DAT2__AUD4_RXC               0x1e0 0x4e8 0x5ec 0x4 0x1
+#define MX6SL_PAD_LCD_DAT2__GPIO2_IO22             0x1e0 0x4e8 0x000 0x5 0x0
+#define MX6SL_PAD_LCD_DAT2__ARM_TRACE02            0x1e0 0x4e8 0x000 0x6 0x0
+#define MX6SL_PAD_LCD_DAT2__SRC_BOOT_CFG02         0x1e0 0x4e8 0x000 0x7 0x0
+#define MX6SL_PAD_LCD_DAT20__LCD_DATA20            0x1e4 0x4ec 0x7c8 0x0 0x1
+#define MX6SL_PAD_LCD_DAT20__KEY_COL6              0x1e4 0x4ec 0x74c 0x1 0x1
+#define MX6SL_PAD_LCD_DAT20__CSI_DATA13            0x1e4 0x4ec 0x664 0x2 0x0
+#define MX6SL_PAD_LCD_DAT20__EIM_DATA14            0x1e4 0x4ec 0x000 0x3 0x0
+#define MX6SL_PAD_LCD_DAT20__GPT_COMPARE1          0x1e4 0x4ec 0x000 0x4 0x0
+#define MX6SL_PAD_LCD_DAT20__GPIO3_IO08            0x1e4 0x4ec 0x000 0x5 0x0
+#define MX6SL_PAD_LCD_DAT20__ARM_TRACE20           0x1e4 0x4ec 0x000 0x6 0x0
+#define MX6SL_PAD_LCD_DAT20__SRC_BOOT_CFG28        0x1e4 0x4ec 0x000 0x7 0x0
+#define MX6SL_PAD_LCD_DAT21__LCD_DATA21            0x1e8 0x4f0 0x7cc 0x0 0x1
+#define MX6SL_PAD_LCD_DAT21__KEY_ROW6              0x1e8 0x4f0 0x76c 0x1 0x1
+#define MX6SL_PAD_LCD_DAT21__CSI_DATA12            0x1e8 0x4f0 0x660 0x2 0x0
+#define MX6SL_PAD_LCD_DAT21__EIM_DATA15            0x1e8 0x4f0 0x000 0x3 0x0
+#define MX6SL_PAD_LCD_DAT21__GPT_COMPARE2          0x1e8 0x4f0 0x000 0x4 0x0
+#define MX6SL_PAD_LCD_DAT21__GPIO3_IO09            0x1e8 0x4f0 0x000 0x5 0x0
+#define MX6SL_PAD_LCD_DAT21__ARM_TRACE21           0x1e8 0x4f0 0x000 0x6 0x0
+#define MX6SL_PAD_LCD_DAT21__SRC_BOOT_CFG29        0x1e8 0x4f0 0x000 0x7 0x0
+#define MX6SL_PAD_LCD_DAT22__LCD_DATA22            0x1ec 0x4f4 0x7d0 0x0 0x1
+#define MX6SL_PAD_LCD_DAT22__KEY_COL7              0x1ec 0x4f4 0x750 0x1 0x1
+#define MX6SL_PAD_LCD_DAT22__CSI_DATA11            0x1ec 0x4f4 0x65c 0x2 0x1
+#define MX6SL_PAD_LCD_DAT22__EIM_EB3_B             0x1ec 0x4f4 0x000 0x3 0x0
+#define MX6SL_PAD_LCD_DAT22__GPT_COMPARE3          0x1ec 0x4f4 0x000 0x4 0x0
+#define MX6SL_PAD_LCD_DAT22__GPIO3_IO10            0x1ec 0x4f4 0x000 0x5 0x0
+#define MX6SL_PAD_LCD_DAT22__ARM_TRACE22           0x1ec 0x4f4 0x000 0x6 0x0
+#define MX6SL_PAD_LCD_DAT22__SRC_BOOT_CFG30        0x1ec 0x4f4 0x000 0x7 0x0
+#define MX6SL_PAD_LCD_DAT23__LCD_DATA23            0x1f0 0x4f8 0x7d4 0x0 0x1
+#define MX6SL_PAD_LCD_DAT23__KEY_ROW7              0x1f0 0x4f8 0x770 0x1 0x1
+#define MX6SL_PAD_LCD_DAT23__CSI_DATA10            0x1f0 0x4f8 0x658 0x2 0x1
+#define MX6SL_PAD_LCD_DAT23__EIM_EB2_B             0x1f0 0x4f8 0x000 0x3 0x0
+#define MX6SL_PAD_LCD_DAT23__GPT_CLKIN             0x1f0 0x4f8 0x718 0x4 0x1
+#define MX6SL_PAD_LCD_DAT23__GPIO3_IO11            0x1f0 0x4f8 0x000 0x5 0x0
+#define MX6SL_PAD_LCD_DAT23__ARM_TRACE23           0x1f0 0x4f8 0x000 0x6 0x0
+#define MX6SL_PAD_LCD_DAT23__SRC_BOOT_CFG31        0x1f0 0x4f8 0x000 0x7 0x0
+#define MX6SL_PAD_LCD_DAT3__LCD_DATA03             0x1f4 0x4fc 0x784 0x0 0x1
+#define MX6SL_PAD_LCD_DAT3__ECSPI1_SCLK            0x1f4 0x4fc 0x67c 0x1 0x1
+#define MX6SL_PAD_LCD_DAT3__UART5_DSR_B            0x1f4 0x4fc 0x000 0x2 0x0
+#define MX6SL_PAD_LCD_DAT3__PWM4_OUT               0x1f4 0x4fc 0x000 0x3 0x0
+#define MX6SL_PAD_LCD_DAT3__AUD4_RXD               0x1f4 0x4fc 0x5e4 0x4 0x1
+#define MX6SL_PAD_LCD_DAT3__GPIO2_IO23             0x1f4 0x4fc 0x000 0x5 0x0
+#define MX6SL_PAD_LCD_DAT3__ARM_TRACE03            0x1f4 0x4fc 0x000 0x6 0x0
+#define MX6SL_PAD_LCD_DAT3__SRC_BOOT_CFG03         0x1f4 0x4fc 0x000 0x7 0x0
+#define MX6SL_PAD_LCD_DAT4__LCD_DATA04             0x1f8 0x500 0x788 0x0 0x1
+#define MX6SL_PAD_LCD_DAT4__ECSPI1_SS1             0x1f8 0x500 0x690 0x1 0x1
+#define MX6SL_PAD_LCD_DAT4__CSI_VSYNC              0x1f8 0x500 0x678 0x2 0x2
+#define MX6SL_PAD_LCD_DAT4__WDOG2_RESET_B_DEB      0x1f8 0x500 0x000 0x3 0x0
+#define MX6SL_PAD_LCD_DAT4__AUD4_TXC               0x1f8 0x500 0x5f4 0x4 0x1
+#define MX6SL_PAD_LCD_DAT4__GPIO2_IO24             0x1f8 0x500 0x000 0x5 0x0
+#define MX6SL_PAD_LCD_DAT4__ARM_TRACE04            0x1f8 0x500 0x000 0x6 0x0
+#define MX6SL_PAD_LCD_DAT4__SRC_BOOT_CFG04         0x1f8 0x500 0x000 0x7 0x0
+#define MX6SL_PAD_LCD_DAT5__LCD_DATA05             0x1fc 0x504 0x78c 0x0 0x1
+#define MX6SL_PAD_LCD_DAT5__ECSPI1_SS2             0x1fc 0x504 0x694 0x1 0x1
+#define MX6SL_PAD_LCD_DAT5__CSI_HSYNC              0x1fc 0x504 0x670 0x2 0x2
+#define MX6SL_PAD_LCD_DAT5__EIM_CS3_B              0x1fc 0x504 0x000 0x3 0x0
+#define MX6SL_PAD_LCD_DAT5__AUD4_TXFS              0x1fc 0x504 0x5f8 0x4 0x1
+#define MX6SL_PAD_LCD_DAT5__GPIO2_IO25             0x1fc 0x504 0x000 0x5 0x0
+#define MX6SL_PAD_LCD_DAT5__ARM_TRACE05            0x1fc 0x504 0x000 0x6 0x0
+#define MX6SL_PAD_LCD_DAT5__SRC_BOOT_CFG05         0x1fc 0x504 0x000 0x7 0x0
+#define MX6SL_PAD_LCD_DAT6__LCD_DATA06             0x200 0x508 0x790 0x0 0x1
+#define MX6SL_PAD_LCD_DAT6__ECSPI1_SS3             0x200 0x508 0x698 0x1 0x1
+#define MX6SL_PAD_LCD_DAT6__CSI_PIXCLK             0x200 0x508 0x674 0x2 0x2
+#define MX6SL_PAD_LCD_DAT6__EIM_DATA00             0x200 0x508 0x000 0x3 0x0
+#define MX6SL_PAD_LCD_DAT6__AUD4_TXD               0x200 0x508 0x5e8 0x4 0x1
+#define MX6SL_PAD_LCD_DAT6__GPIO2_IO26             0x200 0x508 0x000 0x5 0x0
+#define MX6SL_PAD_LCD_DAT6__ARM_TRACE06            0x200 0x508 0x000 0x6 0x0
+#define MX6SL_PAD_LCD_DAT6__SRC_BOOT_CFG06         0x200 0x508 0x000 0x7 0x0
+#define MX6SL_PAD_LCD_DAT7__LCD_DATA07             0x204 0x50c 0x794 0x0 0x1
+#define MX6SL_PAD_LCD_DAT7__ECSPI1_RDY             0x204 0x50c 0x680 0x1 0x1
+#define MX6SL_PAD_LCD_DAT7__CSI_MCLK               0x204 0x50c 0x000 0x2 0x0
+#define MX6SL_PAD_LCD_DAT7__EIM_DATA01             0x204 0x50c 0x000 0x3 0x0
+#define MX6SL_PAD_LCD_DAT7__AUDIO_CLK_OUT          0x204 0x50c 0x000 0x4 0x0
+#define MX6SL_PAD_LCD_DAT7__GPIO2_IO27             0x204 0x50c 0x000 0x5 0x0
+#define MX6SL_PAD_LCD_DAT7__ARM_TRACE07            0x204 0x50c 0x000 0x6 0x0
+#define MX6SL_PAD_LCD_DAT7__SRC_BOOT_CFG07         0x204 0x50c 0x000 0x7 0x0
+#define MX6SL_PAD_LCD_DAT8__LCD_DATA08             0x208 0x510 0x798 0x0 0x1
+#define MX6SL_PAD_LCD_DAT8__KEY_COL0               0x208 0x510 0x734 0x1 0x1
+#define MX6SL_PAD_LCD_DAT8__CSI_DATA09             0x208 0x510 0x654 0x2 0x1
+#define MX6SL_PAD_LCD_DAT8__EIM_DATA02             0x208 0x510 0x000 0x3 0x0
+#define MX6SL_PAD_LCD_DAT8__ECSPI2_SCLK            0x208 0x510 0x69c 0x4 0x2
+#define MX6SL_PAD_LCD_DAT8__GPIO2_IO28             0x208 0x510 0x000 0x5 0x0
+#define MX6SL_PAD_LCD_DAT8__ARM_TRACE08            0x208 0x510 0x000 0x6 0x0
+#define MX6SL_PAD_LCD_DAT8__SRC_BOOT_CFG08         0x208 0x510 0x000 0x7 0x0
+#define MX6SL_PAD_LCD_DAT9__LCD_DATA09             0x20c 0x514 0x79c 0x0 0x1
+#define MX6SL_PAD_LCD_DAT9__KEY_ROW0               0x20c 0x514 0x754 0x1 0x1
+#define MX6SL_PAD_LCD_DAT9__CSI_DATA08             0x20c 0x514 0x650 0x2 0x1
+#define MX6SL_PAD_LCD_DAT9__EIM_DATA03             0x20c 0x514 0x000 0x3 0x0
+#define MX6SL_PAD_LCD_DAT9__ECSPI2_MOSI            0x20c 0x514 0x6a4 0x4 0x2
+#define MX6SL_PAD_LCD_DAT9__GPIO2_IO29             0x20c 0x514 0x000 0x5 0x0
+#define MX6SL_PAD_LCD_DAT9__ARM_TRACE09            0x20c 0x514 0x000 0x6 0x0
+#define MX6SL_PAD_LCD_DAT9__SRC_BOOT_CFG09         0x20c 0x514 0x000 0x7 0x0
+#define MX6SL_PAD_LCD_ENABLE__LCD_ENABLE           0x210 0x518 0x000 0x0 0x0
+#define MX6SL_PAD_LCD_ENABLE__SD4_DATA5            0x210 0x518 0x870 0x1 0x2
+#define MX6SL_PAD_LCD_ENABLE__LCD_RD_E             0x210 0x518 0x000 0x2 0x0
+#define MX6SL_PAD_LCD_ENABLE__EIM_OE_B             0x210 0x518 0x000 0x3 0x0
+#define MX6SL_PAD_LCD_ENABLE__UART2_RX_DATA        0x210 0x518 0x804 0x4 0x2
+#define MX6SL_PAD_LCD_ENABLE__UART2_TX_DATA        0x210 0x518 0x000 0x4 0x0
+#define MX6SL_PAD_LCD_ENABLE__GPIO2_IO16           0x210 0x518 0x000 0x5 0x0
+#define MX6SL_PAD_LCD_HSYNC__LCD_HSYNC             0x214 0x51c 0x774 0x0 0x0
+#define MX6SL_PAD_LCD_HSYNC__SD4_DATA6             0x214 0x51c 0x874 0x1 0x2
+#define MX6SL_PAD_LCD_HSYNC__LCD_CS                0x214 0x51c 0x000 0x2 0x0
+#define MX6SL_PAD_LCD_HSYNC__EIM_CS0_B             0x214 0x51c 0x000 0x3 0x0
+#define MX6SL_PAD_LCD_HSYNC__UART2_TX_DATA         0x214 0x51c 0x000 0x4 0x0
+#define MX6SL_PAD_LCD_HSYNC__UART2_RX_DATA         0x214 0x51c 0x804 0x4 0x3
+#define MX6SL_PAD_LCD_HSYNC__GPIO2_IO17            0x214 0x51c 0x000 0x5 0x0
+#define MX6SL_PAD_LCD_HSYNC__ARM_TRACE_CLK         0x214 0x51c 0x000 0x6 0x0
+#define MX6SL_PAD_LCD_RESET__LCD_RESET             0x218 0x520 0x000 0x0 0x0
+#define MX6SL_PAD_LCD_RESET__EIM_DTACK_B           0x218 0x520 0x880 0x1 0x1
+#define MX6SL_PAD_LCD_RESET__LCD_BUSY              0x218 0x520 0x774 0x2 0x1
+#define MX6SL_PAD_LCD_RESET__EIM_WAIT_B            0x218 0x520 0x884 0x3 0x1
+#define MX6SL_PAD_LCD_RESET__UART2_CTS_B           0x218 0x520 0x000 0x4 0x0
+#define MX6SL_PAD_LCD_RESET__UART2_RTS_B           0x218 0x520 0x800 0x4 0x2
+#define MX6SL_PAD_LCD_RESET__GPIO2_IO19            0x218 0x520 0x000 0x5 0x0
+#define MX6SL_PAD_LCD_RESET__CCM_PMIC_READY        0x218 0x520 0x62c 0x6 0x1
+#define MX6SL_PAD_LCD_VSYNC__LCD_VSYNC             0x21c 0x524 0x000 0x0 0x0
+#define MX6SL_PAD_LCD_VSYNC__SD4_DATA7             0x21c 0x524 0x878 0x1 0x2
+#define MX6SL_PAD_LCD_VSYNC__LCD_RS                0x21c 0x524 0x000 0x2 0x0
+#define MX6SL_PAD_LCD_VSYNC__EIM_CS1_B             0x21c 0x524 0x000 0x3 0x0
+#define MX6SL_PAD_LCD_VSYNC__UART2_RTS_B           0x21c 0x524 0x800 0x4 0x3
+#define MX6SL_PAD_LCD_VSYNC__UART2_CTS_B           0x21c 0x524 0x000 0x4 0x0
+#define MX6SL_PAD_LCD_VSYNC__GPIO2_IO18            0x21c 0x524 0x000 0x5 0x0
+#define MX6SL_PAD_LCD_VSYNC__ARM_TRACE_CTL         0x21c 0x524 0x000 0x6 0x0
+#define MX6SL_PAD_PWM1__PWM1_OUT                   0x220 0x528 0x000 0x0 0x0
+#define MX6SL_PAD_PWM1__CCM_CLKO                   0x220 0x528 0x000 0x1 0x0
+#define MX6SL_PAD_PWM1__AUDIO_CLK_OUT              0x220 0x528 0x000 0x2 0x0
+#define MX6SL_PAD_PWM1__FEC_REF_OUT                0x220 0x528 0x000 0x3 0x0
+#define MX6SL_PAD_PWM1__CSI_MCLK                   0x220 0x528 0x000 0x4 0x0
+#define MX6SL_PAD_PWM1__GPIO3_IO23                 0x220 0x528 0x000 0x5 0x0
+#define MX6SL_PAD_PWM1__EPIT1_OUT                  0x220 0x528 0x000 0x6 0x0
+#define MX6SL_PAD_REF_CLK_24M__XTALOSC_REF_CLK_24M 0x224 0x52c 0x000 0x0 0x0
+#define MX6SL_PAD_REF_CLK_24M__I2C3_SCL            0x224 0x52c 0x72c 0x1 0x2
+#define MX6SL_PAD_REF_CLK_24M__PWM3_OUT            0x224 0x52c 0x000 0x2 0x0
+#define MX6SL_PAD_REF_CLK_24M__USB_OTG2_ID         0x224 0x52c 0x5e0 0x3 0x2
+#define MX6SL_PAD_REF_CLK_24M__CCM_PMIC_READY      0x224 0x52c 0x62c 0x4 0x2
+#define MX6SL_PAD_REF_CLK_24M__GPIO3_IO21          0x224 0x52c 0x000 0x5 0x0
+#define MX6SL_PAD_REF_CLK_24M__SD3_WP              0x224 0x52c 0x84c 0x6 0x3
+#define MX6SL_PAD_REF_CLK_32K__XTALOSC_REF_CLK_32K 0x228 0x530 0x000 0x0 0x0
+#define MX6SL_PAD_REF_CLK_32K__I2C3_SDA            0x228 0x530 0x730 0x1 0x2
+#define MX6SL_PAD_REF_CLK_32K__PWM4_OUT            0x228 0x530 0x000 0x2 0x0
+#define MX6SL_PAD_REF_CLK_32K__USB_OTG1_ID         0x228 0x530 0x5dc 0x3 0x3
+#define MX6SL_PAD_REF_CLK_32K__SD1_LCTL            0x228 0x530 0x000 0x4 0x0
+#define MX6SL_PAD_REF_CLK_32K__GPIO3_IO22          0x228 0x530 0x000 0x5 0x0
+#define MX6SL_PAD_REF_CLK_32K__SD3_CD_B            0x228 0x530 0x838 0x6 0x3
+#define MX6SL_PAD_SD1_CLK__SD1_CLK                 0x22c 0x534 0x000 0x0 0x0
+#define MX6SL_PAD_SD1_CLK__FEC_MDIO                0x22c 0x534 0x6f4 0x1 0x2
+#define MX6SL_PAD_SD1_CLK__KEY_COL0                0x22c 0x534 0x734 0x2 0x2
+#define MX6SL_PAD_SD1_CLK__EPDC_SDCE4              0x22c 0x534 0x000 0x3 0x0
+#define MX6SL_PAD_SD1_CLK__GPIO5_IO15              0x22c 0x534 0x000 0x5 0x0
+#define MX6SL_PAD_SD1_CMD__SD1_CMD                 0x230 0x538 0x000 0x0 0x0
+#define MX6SL_PAD_SD1_CMD__FEC_TX_CLK              0x230 0x538 0x70c 0x1 0x2
+#define MX6SL_PAD_SD1_CMD__KEY_ROW0                0x230 0x538 0x754 0x2 0x2
+#define MX6SL_PAD_SD1_CMD__EPDC_SDCE5              0x230 0x538 0x000 0x3 0x0
+#define MX6SL_PAD_SD1_CMD__GPIO5_IO14              0x230 0x538 0x000 0x5 0x0
+#define MX6SL_PAD_SD1_DAT0__SD1_DATA0              0x234 0x53c 0x000 0x0 0x0
+#define MX6SL_PAD_SD1_DAT0__FEC_RX_ER              0x234 0x53c 0x708 0x1 0x2
+#define MX6SL_PAD_SD1_DAT0__KEY_COL1               0x234 0x53c 0x738 0x2 0x2
+#define MX6SL_PAD_SD1_DAT0__EPDC_SDCE6             0x234 0x53c 0x000 0x3 0x0
+#define MX6SL_PAD_SD1_DAT0__GPIO5_IO11             0x234 0x53c 0x000 0x5 0x0
+#define MX6SL_PAD_SD1_DAT1__SD1_DATA1              0x238 0x540 0x000 0x0 0x0
+#define MX6SL_PAD_SD1_DAT1__FEC_RX_DV              0x238 0x540 0x704 0x1 0x2
+#define MX6SL_PAD_SD1_DAT1__KEY_ROW1               0x238 0x540 0x758 0x2 0x2
+#define MX6SL_PAD_SD1_DAT1__EPDC_SDCE7             0x238 0x540 0x000 0x3 0x0
+#define MX6SL_PAD_SD1_DAT1__GPIO5_IO08             0x238 0x540 0x000 0x5 0x0
+#define MX6SL_PAD_SD1_DAT2__SD1_DATA2              0x23c 0x544 0x000 0x0 0x0
+#define MX6SL_PAD_SD1_DAT2__FEC_RX_DATA1           0x23c 0x544 0x6fc 0x1 0x2
+#define MX6SL_PAD_SD1_DAT2__KEY_COL2               0x23c 0x544 0x73c 0x2 0x2
+#define MX6SL_PAD_SD1_DAT2__EPDC_SDCE8             0x23c 0x544 0x000 0x3 0x0
+#define MX6SL_PAD_SD1_DAT2__GPIO5_IO13             0x23c 0x544 0x000 0x5 0x0
+#define MX6SL_PAD_SD1_DAT3__SD1_DATA3              0x240 0x548 0x000 0x0 0x0
+#define MX6SL_PAD_SD1_DAT3__FEC_TX_DATA0           0x240 0x548 0x000 0x1 0x0
+#define MX6SL_PAD_SD1_DAT3__KEY_ROW2               0x240 0x548 0x75c 0x2 0x2
+#define MX6SL_PAD_SD1_DAT3__EPDC_SDCE9             0x240 0x548 0x000 0x3 0x0
+#define MX6SL_PAD_SD1_DAT3__GPIO5_IO06             0x240 0x548 0x000 0x5 0x0
+#define MX6SL_PAD_SD1_DAT4__SD1_DATA4              0x244 0x54c 0x000 0x0 0x0
+#define MX6SL_PAD_SD1_DAT4__FEC_MDC                0x244 0x54c 0x000 0x1 0x0
+#define MX6SL_PAD_SD1_DAT4__KEY_COL3               0x244 0x54c 0x740 0x2 0x2
+#define MX6SL_PAD_SD1_DAT4__EPDC_SDCLK_N           0x244 0x54c 0x000 0x3 0x0
+#define MX6SL_PAD_SD1_DAT4__UART4_RX_DATA          0x244 0x54c 0x814 0x4 0x4
+#define MX6SL_PAD_SD1_DAT4__UART4_TX_DATA          0x244 0x54c 0x000 0x4 0x0
+#define MX6SL_PAD_SD1_DAT4__GPIO5_IO12             0x244 0x54c 0x000 0x5 0x0
+#define MX6SL_PAD_SD1_DAT5__SD1_DATA5              0x248 0x550 0x000 0x0 0x0
+#define MX6SL_PAD_SD1_DAT5__FEC_RX_DATA0           0x248 0x550 0x6f8 0x1 0x2
+#define MX6SL_PAD_SD1_DAT5__KEY_ROW3               0x248 0x550 0x760 0x2 0x2
+#define MX6SL_PAD_SD1_DAT5__EPDC_SDOED             0x248 0x550 0x000 0x3 0x0
+#define MX6SL_PAD_SD1_DAT5__UART4_TX_DATA          0x248 0x550 0x000 0x4 0x0
+#define MX6SL_PAD_SD1_DAT5__UART4_RX_DATA          0x248 0x550 0x814 0x4 0x5
+#define MX6SL_PAD_SD1_DAT5__GPIO5_IO09             0x248 0x550 0x000 0x5 0x0
+#define MX6SL_PAD_SD1_DAT6__SD1_DATA6              0x24c 0x554 0x000 0x0 0x0
+#define MX6SL_PAD_SD1_DAT6__FEC_TX_EN              0x24c 0x554 0x000 0x1 0x0
+#define MX6SL_PAD_SD1_DAT6__KEY_COL4               0x24c 0x554 0x744 0x2 0x2
+#define MX6SL_PAD_SD1_DAT6__EPDC_SDOEZ             0x24c 0x554 0x000 0x3 0x0
+#define MX6SL_PAD_SD1_DAT6__UART4_RTS_B            0x24c 0x554 0x810 0x4 0x4
+#define MX6SL_PAD_SD1_DAT6__UART4_CTS_B            0x24c 0x554 0x000 0x4 0x0
+#define MX6SL_PAD_SD1_DAT6__GPIO5_IO07             0x24c 0x554 0x000 0x5 0x0
+#define MX6SL_PAD_SD1_DAT7__SD1_DATA7              0x250 0x558 0x000 0x0 0x0
+#define MX6SL_PAD_SD1_DAT7__FEC_TX_DATA1           0x250 0x558 0x000 0x1 0x0
+#define MX6SL_PAD_SD1_DAT7__KEY_ROW4               0x250 0x558 0x764 0x2 0x2
+#define MX6SL_PAD_SD1_DAT7__CCM_PMIC_READY         0x250 0x558 0x62c 0x3 0x3
+#define MX6SL_PAD_SD1_DAT7__UART4_CTS_B            0x250 0x558 0x000 0x4 0x0
+#define MX6SL_PAD_SD1_DAT7__UART4_RTS_B            0x250 0x558 0x810 0x4 0x5
+#define MX6SL_PAD_SD1_DAT7__GPIO5_IO10             0x250 0x558 0x000 0x5 0x0
+#define MX6SL_PAD_SD2_CLK__SD2_CLK                 0x254 0x55c 0x000 0x0 0x0
+#define MX6SL_PAD_SD2_CLK__AUD4_RXFS               0x254 0x55c 0x5f0 0x1 0x2
+#define MX6SL_PAD_SD2_CLK__ECSPI3_SCLK             0x254 0x55c 0x6b0 0x2 0x2
+#define MX6SL_PAD_SD2_CLK__CSI_DATA00              0x254 0x55c 0x630 0x3 0x2
+#define MX6SL_PAD_SD2_CLK__GPIO5_IO05              0x254 0x55c 0x000 0x5 0x0
+#define MX6SL_PAD_SD2_CMD__SD2_CMD                 0x258 0x560 0x000 0x0 0x0
+#define MX6SL_PAD_SD2_CMD__AUD4_RXC                0x258 0x560 0x5ec 0x1 0x2
+#define MX6SL_PAD_SD2_CMD__ECSPI3_SS0              0x258 0x560 0x6c0 0x2 0x2
+#define MX6SL_PAD_SD2_CMD__CSI_DATA01              0x258 0x560 0x634 0x3 0x2
+#define MX6SL_PAD_SD2_CMD__EPIT1_OUT               0x258 0x560 0x000 0x4 0x0
+#define MX6SL_PAD_SD2_CMD__GPIO5_IO04              0x258 0x560 0x000 0x5 0x0
+#define MX6SL_PAD_SD2_DAT0__SD2_DATA0              0x25c 0x564 0x000 0x0 0x0
+#define MX6SL_PAD_SD2_DAT0__AUD4_RXD               0x25c 0x564 0x5e4 0x1 0x2
+#define MX6SL_PAD_SD2_DAT0__ECSPI3_MOSI            0x25c 0x564 0x6bc 0x2 0x2
+#define MX6SL_PAD_SD2_DAT0__CSI_DATA02             0x25c 0x564 0x638 0x3 0x2
+#define MX6SL_PAD_SD2_DAT0__UART5_RTS_B            0x25c 0x564 0x818 0x4 0x4
+#define MX6SL_PAD_SD2_DAT0__UART5_CTS_B            0x25c 0x564 0x000 0x4 0x0
+#define MX6SL_PAD_SD2_DAT0__GPIO5_IO01             0x25c 0x564 0x000 0x5 0x0
+#define MX6SL_PAD_SD2_DAT1__SD2_DATA1              0x260 0x568 0x000 0x0 0x0
+#define MX6SL_PAD_SD2_DAT1__AUD4_TXC               0x260 0x568 0x5f4 0x1 0x2
+#define MX6SL_PAD_SD2_DAT1__ECSPI3_MISO            0x260 0x568 0x6b8 0x2 0x2
+#define MX6SL_PAD_SD2_DAT1__CSI_DATA03             0x260 0x568 0x63c 0x3 0x2
+#define MX6SL_PAD_SD2_DAT1__UART5_CTS_B            0x260 0x568 0x000 0x4 0x0
+#define MX6SL_PAD_SD2_DAT1__UART5_RTS_B            0x260 0x568 0x818 0x4 0x5
+#define MX6SL_PAD_SD2_DAT1__GPIO4_IO30             0x260 0x568 0x000 0x5 0x0
+#define MX6SL_PAD_SD2_DAT2__SD2_DATA2              0x264 0x56c 0x000 0x0 0x0
+#define MX6SL_PAD_SD2_DAT2__AUD4_TXFS              0x264 0x56c 0x5f8 0x1 0x2
+#define MX6SL_PAD_SD2_DAT2__FEC_COL                0x264 0x56c 0x6f0 0x2 0x1
+#define MX6SL_PAD_SD2_DAT2__CSI_DATA04             0x264 0x56c 0x640 0x3 0x2
+#define MX6SL_PAD_SD2_DAT2__UART5_RX_DATA          0x264 0x56c 0x81c 0x4 0x4
+#define MX6SL_PAD_SD2_DAT2__UART5_TX_DATA          0x264 0x56c 0x000 0x4 0x0
+#define MX6SL_PAD_SD2_DAT2__GPIO5_IO03             0x264 0x56c 0x000 0x5 0x0
+#define MX6SL_PAD_SD2_DAT3__SD2_DATA3              0x268 0x570 0x000 0x0 0x0
+#define MX6SL_PAD_SD2_DAT3__AUD4_TXD               0x268 0x570 0x5e8 0x1 0x2
+#define MX6SL_PAD_SD2_DAT3__FEC_RX_CLK             0x268 0x570 0x700 0x2 0x1
+#define MX6SL_PAD_SD2_DAT3__CSI_DATA05             0x268 0x570 0x644 0x3 0x2
+#define MX6SL_PAD_SD2_DAT3__UART5_TX_DATA          0x268 0x570 0x000 0x4 0x0
+#define MX6SL_PAD_SD2_DAT3__UART5_RX_DATA          0x268 0x570 0x81c 0x4 0x5
+#define MX6SL_PAD_SD2_DAT3__GPIO4_IO28             0x268 0x570 0x000 0x5 0x0
+#define MX6SL_PAD_SD2_DAT4__SD2_DATA4              0x26c 0x574 0x000 0x0 0x0
+#define MX6SL_PAD_SD2_DAT4__SD3_DATA4              0x26c 0x574 0x83c 0x1 0x1
+#define MX6SL_PAD_SD2_DAT4__UART2_RX_DATA          0x26c 0x574 0x804 0x2 0x4
+#define MX6SL_PAD_SD2_DAT4__UART2_TX_DATA          0x26c 0x574 0x000 0x2 0x0
+#define MX6SL_PAD_SD2_DAT4__CSI_DATA06             0x26c 0x574 0x648 0x3 0x2
+#define MX6SL_PAD_SD2_DAT4__SPDIF_OUT              0x26c 0x574 0x000 0x4 0x0
+#define MX6SL_PAD_SD2_DAT4__GPIO5_IO02             0x26c 0x574 0x000 0x5 0x0
+#define MX6SL_PAD_SD2_DAT5__SD2_DATA5              0x270 0x578 0x000 0x0 0x0
+#define MX6SL_PAD_SD2_DAT5__SD3_DATA5              0x270 0x578 0x840 0x1 0x1
+#define MX6SL_PAD_SD2_DAT5__UART2_TX_DATA          0x270 0x578 0x000 0x2 0x0
+#define MX6SL_PAD_SD2_DAT5__UART2_RX_DATA          0x270 0x578 0x804 0x2 0x5
+#define MX6SL_PAD_SD2_DAT5__CSI_DATA07             0x270 0x578 0x64c 0x3 0x2
+#define MX6SL_PAD_SD2_DAT5__SPDIF_IN               0x270 0x578 0x7f0 0x4 0x2
+#define MX6SL_PAD_SD2_DAT5__GPIO4_IO31             0x270 0x578 0x000 0x5 0x0
+#define MX6SL_PAD_SD2_DAT6__SD2_DATA6              0x274 0x57c 0x000 0x0 0x0
+#define MX6SL_PAD_SD2_DAT6__SD3_DATA6              0x274 0x57c 0x844 0x1 0x1
+#define MX6SL_PAD_SD2_DAT6__UART2_RTS_B            0x274 0x57c 0x800 0x2 0x4
+#define MX6SL_PAD_SD2_DAT6__UART2_CTS_B            0x274 0x57c 0x000 0x2 0x0
+#define MX6SL_PAD_SD2_DAT6__CSI_DATA08             0x274 0x57c 0x650 0x3 0x2
+#define MX6SL_PAD_SD2_DAT6__SD2_WP                 0x274 0x57c 0x834 0x4 0x2
+#define MX6SL_PAD_SD2_DAT6__GPIO4_IO29             0x274 0x57c 0x000 0x5 0x0
+#define MX6SL_PAD_SD2_DAT7__SD2_DATA7              0x278 0x580 0x000 0x0 0x0
+#define MX6SL_PAD_SD2_DAT7__SD3_DATA7              0x278 0x580 0x848 0x1 0x1
+#define MX6SL_PAD_SD2_DAT7__UART2_CTS_B            0x278 0x580 0x000 0x2 0x0
+#define MX6SL_PAD_SD2_DAT7__UART2_RTS_B            0x278 0x580 0x800 0x2 0x5
+#define MX6SL_PAD_SD2_DAT7__CSI_DATA09             0x278 0x580 0x654 0x3 0x2
+#define MX6SL_PAD_SD2_DAT7__SD2_CD_B               0x278 0x580 0x830 0x4 0x2
+#define MX6SL_PAD_SD2_DAT7__GPIO5_IO00             0x278 0x580 0x000 0x5 0x0
+#define MX6SL_PAD_SD2_RST__SD2_RESET               0x27c 0x584 0x000 0x0 0x0
+#define MX6SL_PAD_SD2_RST__FEC_REF_OUT             0x27c 0x584 0x000 0x1 0x0
+#define MX6SL_PAD_SD2_RST__WDOG2_B                 0x27c 0x584 0x000 0x2 0x0
+#define MX6SL_PAD_SD2_RST__SPDIF_OUT               0x27c 0x584 0x000 0x3 0x0
+#define MX6SL_PAD_SD2_RST__CSI_MCLK                0x27c 0x584 0x000 0x4 0x0
+#define MX6SL_PAD_SD2_RST__GPIO4_IO27              0x27c 0x584 0x000 0x5 0x0
+#define MX6SL_PAD_SD3_CLK__SD3_CLK                 0x280 0x588 0x000 0x0 0x0
+#define MX6SL_PAD_SD3_CLK__AUD5_RXFS               0x280 0x588 0x608 0x1 0x1
+#define MX6SL_PAD_SD3_CLK__KEY_COL5                0x280 0x588 0x748 0x2 0x2
+#define MX6SL_PAD_SD3_CLK__CSI_DATA10              0x280 0x588 0x658 0x3 0x2
+#define MX6SL_PAD_SD3_CLK__WDOG1_RESET_B_DEB       0x280 0x588 0x000 0x4 0x0
+#define MX6SL_PAD_SD3_CLK__GPIO5_IO18              0x280 0x588 0x000 0x5 0x0
+#define MX6SL_PAD_SD3_CLK__USB_OTG1_PWR            0x280 0x588 0x000 0x6 0x0
+#define MX6SL_PAD_SD3_CMD__SD3_CMD                 0x284 0x58c 0x000 0x0 0x0
+#define MX6SL_PAD_SD3_CMD__AUD5_RXC                0x284 0x58c 0x604 0x1 0x1
+#define MX6SL_PAD_SD3_CMD__KEY_ROW5                0x284 0x58c 0x768 0x2 0x2
+#define MX6SL_PAD_SD3_CMD__CSI_DATA11              0x284 0x58c 0x65c 0x3 0x2
+#define MX6SL_PAD_SD3_CMD__USB_OTG2_ID             0x284 0x58c 0x5e0 0x4 0x3
+#define MX6SL_PAD_SD3_CMD__GPIO5_IO21              0x284 0x58c 0x000 0x5 0x0
+#define MX6SL_PAD_SD3_CMD__USB_OTG2_PWR            0x284 0x58c 0x000 0x6 0x0
+#define MX6SL_PAD_SD3_DAT0__SD3_DATA0              0x288 0x590 0x000 0x0 0x0
+#define MX6SL_PAD_SD3_DAT0__AUD5_RXD               0x288 0x590 0x5fc 0x1 0x1
+#define MX6SL_PAD_SD3_DAT0__KEY_COL6               0x288 0x590 0x74c 0x2 0x2
+#define MX6SL_PAD_SD3_DAT0__CSI_DATA12             0x288 0x590 0x660 0x3 0x1
+#define MX6SL_PAD_SD3_DAT0__USB_OTG1_ID            0x288 0x590 0x5dc 0x4 0x4
+#define MX6SL_PAD_SD3_DAT0__GPIO5_IO19             0x288 0x590 0x000 0x5 0x0
+#define MX6SL_PAD_SD3_DAT1__SD3_DATA1              0x28c 0x594 0x000 0x0 0x0
+#define MX6SL_PAD_SD3_DAT1__AUD5_TXC               0x28c 0x594 0x60c 0x1 0x1
+#define MX6SL_PAD_SD3_DAT1__KEY_ROW6               0x28c 0x594 0x76c 0x2 0x2
+#define MX6SL_PAD_SD3_DAT1__CSI_DATA13             0x28c 0x594 0x664 0x3 0x1
+#define MX6SL_PAD_SD3_DAT1__SD1_VSELECT            0x28c 0x594 0x000 0x4 0x0
+#define MX6SL_PAD_SD3_DAT1__GPIO5_IO20             0x28c 0x594 0x000 0x5 0x0
+#define MX6SL_PAD_SD3_DAT1__JTAG_DE_B              0x28c 0x594 0x000 0x6 0x0
+#define MX6SL_PAD_SD3_DAT2__SD3_DATA2              0x290 0x598 0x000 0x0 0x0
+#define MX6SL_PAD_SD3_DAT2__AUD5_TXFS              0x290 0x598 0x610 0x1 0x1
+#define MX6SL_PAD_SD3_DAT2__KEY_COL7               0x290 0x598 0x750 0x2 0x2
+#define MX6SL_PAD_SD3_DAT2__CSI_DATA14             0x290 0x598 0x668 0x3 0x1
+#define MX6SL_PAD_SD3_DAT2__EPIT1_OUT              0x290 0x598 0x000 0x4 0x0
+#define MX6SL_PAD_SD3_DAT2__GPIO5_IO16             0x290 0x598 0x000 0x5 0x0
+#define MX6SL_PAD_SD3_DAT2__USB_OTG2_OC            0x290 0x598 0x820 0x6 0x3
+#define MX6SL_PAD_SD3_DAT3__SD3_DATA3              0x294 0x59c 0x000 0x0 0x0
+#define MX6SL_PAD_SD3_DAT3__AUD5_TXD               0x294 0x59c 0x600 0x1 0x1
+#define MX6SL_PAD_SD3_DAT3__KEY_ROW7               0x294 0x59c 0x770 0x2 0x2
+#define MX6SL_PAD_SD3_DAT3__CSI_DATA15             0x294 0x59c 0x66c 0x3 0x1
+#define MX6SL_PAD_SD3_DAT3__EPIT2_OUT              0x294 0x59c 0x000 0x4 0x0
+#define MX6SL_PAD_SD3_DAT3__GPIO5_IO17             0x294 0x59c 0x000 0x5 0x0
+#define MX6SL_PAD_SD3_DAT3__USB_OTG1_OC            0x294 0x59c 0x824 0x6 0x2
+#define MX6SL_PAD_UART1_RXD__UART1_RX_DATA         0x298 0x5a0 0x7fc 0x0 0x0
+#define MX6SL_PAD_UART1_RXD__UART1_TX_DATA         0x298 0x5a0 0x000 0x0 0x0
+#define MX6SL_PAD_UART1_RXD__PWM1_OUT              0x298 0x5a0 0x000 0x1 0x0
+#define MX6SL_PAD_UART1_RXD__UART4_RX_DATA         0x298 0x5a0 0x814 0x2 0x6
+#define MX6SL_PAD_UART1_RXD__UART4_TX_DATA         0x298 0x5a0 0x000 0x2 0x0
+#define MX6SL_PAD_UART1_RXD__FEC_COL               0x298 0x5a0 0x6f0 0x3 0x2
+#define MX6SL_PAD_UART1_RXD__UART5_RX_DATA         0x298 0x5a0 0x81c 0x4 0x6
+#define MX6SL_PAD_UART1_RXD__UART5_TX_DATA         0x298 0x5a0 0x000 0x4 0x0
+#define MX6SL_PAD_UART1_RXD__GPIO3_IO16            0x298 0x5a0 0x000 0x5 0x0
+#define MX6SL_PAD_UART1_TXD__UART1_TX_DATA         0x29c 0x5a4 0x000 0x0 0x0
+#define MX6SL_PAD_UART1_TXD__UART1_RX_DATA         0x29c 0x5a4 0x7fc 0x0 0x1
+#define MX6SL_PAD_UART1_TXD__PWM2_OUT              0x29c 0x5a4 0x000 0x1 0x0
+#define MX6SL_PAD_UART1_TXD__UART4_TX_DATA         0x29c 0x5a4 0x000 0x2 0x0
+#define MX6SL_PAD_UART1_TXD__UART4_RX_DATA         0x29c 0x5a4 0x814 0x2 0x7
+#define MX6SL_PAD_UART1_TXD__FEC_RX_CLK            0x29c 0x5a4 0x700 0x3 0x2
+#define MX6SL_PAD_UART1_TXD__UART5_TX_DATA         0x29c 0x5a4 0x000 0x4 0x0
+#define MX6SL_PAD_UART1_TXD__UART5_RX_DATA         0x29c 0x5a4 0x81c 0x4 0x7
+#define MX6SL_PAD_UART1_TXD__GPIO3_IO17            0x29c 0x5a4 0x000 0x5 0x0
+#define MX6SL_PAD_UART1_TXD__UART5_DCD_B           0x29c 0x5a4 0x000 0x7 0x0
+#define MX6SL_PAD_WDOG_B__WDOG1_B                  0x2a0 0x5a8 0x000 0x0 0x0
+#define MX6SL_PAD_WDOG_B__WDOG1_RESET_B_DEB        0x2a0 0x5a8 0x000 0x1 0x0
+#define MX6SL_PAD_WDOG_B__UART5_RI_B               0x2a0 0x5a8 0x000 0x2 0x0
+#define MX6SL_PAD_WDOG_B__GPIO3_IO18               0x2a0 0x5a8 0x000 0x5 0x0
+
+#endif /* __DTS_IMX6SL_PINFUNC_H */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/imx6sll-pinfunc.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/imx6sll-pinfunc.h
new file mode 100644
index 0000000000000000000000000000000000000000..713a346f4c891d39471544f1348b397fa0a8fa28
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/imx6sll-pinfunc.h
@@ -0,0 +1,880 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017-2018 NXP.
+ *
+ */
+
+#ifndef __DTS_IMX6SLL_PINFUNC_H
+#define __DTS_IMX6SLL_PINFUNC_H
+
+/*
+ * The pin function ID is a tuple of
+ * <mux_reg conf_reg input_reg mux_mode input_val>
+ */
+#define MX6SLL_PAD_WDOG_B__WDOG1_B                                0x0014 0x02DC 0x0000 0x0 0x0
+#define MX6SLL_PAD_WDOG_B__WDOG1_RESET_B_DEB                      0x0014 0x02DC 0x0000 0x1 0x0
+#define MX6SLL_PAD_WDOG_B__UART5_RI_B                             0x0014 0x02DC 0x0000 0x2 0x0
+#define MX6SLL_PAD_WDOG_B__GPIO3_IO18                             0x0014 0x02DC 0x0000 0x5 0x0
+#define MX6SLL_PAD_REF_CLK_24M__XTALOSC_REF_CLK_24M               0x0018 0x02E0 0x0000 0x0 0x0
+#define MX6SLL_PAD_REF_CLK_24M__I2C3_SCL                          0x0018 0x02E0 0x068C 0x1 0x0
+#define MX6SLL_PAD_REF_CLK_24M__PWM3_OUT                          0x0018 0x02E0 0x0000 0x2 0x0
+#define MX6SLL_PAD_REF_CLK_24M__USB_OTG2_ID                       0x0018 0x02E0 0x0560 0x3 0x0
+#define MX6SLL_PAD_REF_CLK_24M__CCM_PMIC_READY                    0x0018 0x02E0 0x05AC 0x4 0x0
+#define MX6SLL_PAD_REF_CLK_24M__GPIO3_IO21                        0x0018 0x02E0 0x0000 0x5 0x0
+#define MX6SLL_PAD_REF_CLK_24M__SD3_WP                            0x0018 0x02E0 0x0794 0x6 0x0
+#define MX6SLL_PAD_REF_CLK_32K__XTALOSC_REF_CLK_32K               0x001C 0x02E4 0x0000 0x0 0x0
+#define MX6SLL_PAD_REF_CLK_32K__I2C3_SDA                          0x001C 0x02E4 0x0690 0x1 0x0
+#define MX6SLL_PAD_REF_CLK_32K__PWM4_OUT                          0x001C 0x02E4 0x0000 0x2 0x0
+#define MX6SLL_PAD_REF_CLK_32K__USB_OTG1_ID                       0x001C 0x02E4 0x055C 0x3 0x0
+#define MX6SLL_PAD_REF_CLK_32K__SD1_LCTL                          0x001C 0x02E4 0x0000 0x4 0x0
+#define MX6SLL_PAD_REF_CLK_32K__GPIO3_IO22                        0x001C 0x02E4 0x0000 0x5 0x0
+#define MX6SLL_PAD_REF_CLK_32K__SD3_CD_B                          0x001C 0x02E4 0x0780 0x6 0x0
+#define MX6SLL_PAD_PWM1__PWM1_OUT                                 0x0020 0x02E8 0x0000 0x0 0x0
+#define MX6SLL_PAD_PWM1__CCM_CLKO                                 0x0020 0x02E8 0x0000 0x1 0x0
+#define MX6SLL_PAD_PWM1__AUDIO_CLK_OUT                            0x0020 0x02E8 0x0000 0x2 0x0
+#define MX6SLL_PAD_PWM1__CSI_MCLK                                 0x0020 0x02E8 0x0000 0x4 0x0
+#define MX6SLL_PAD_PWM1__GPIO3_IO23                               0x0020 0x02E8 0x0000 0x5 0x0
+#define MX6SLL_PAD_PWM1__EPIT1_OUT                                0x0020 0x02E8 0x0000 0x6 0x0
+#define MX6SLL_PAD_KEY_COL0__KEY_COL0                             0x0024 0x02EC 0x06A0 0x0 0x0
+#define MX6SLL_PAD_KEY_COL0__I2C2_SCL                             0x0024 0x02EC 0x0684 0x1 0x0
+#define MX6SLL_PAD_KEY_COL0__LCD_DATA00                           0x0024 0x02EC 0x06D8 0x2 0x0
+#define MX6SLL_PAD_KEY_COL0__SD1_CD_B                             0x0024 0x02EC 0x0770 0x4 0x1
+#define MX6SLL_PAD_KEY_COL0__GPIO3_IO24                           0x0024 0x02EC 0x0000 0x5 0x0
+#define MX6SLL_PAD_KEY_ROW0__KEY_ROW0                             0x0028 0x02F0 0x06C0 0x0 0x0
+#define MX6SLL_PAD_KEY_ROW0__I2C2_SDA                             0x0028 0x02F0 0x0688 0x1 0x0
+#define MX6SLL_PAD_KEY_ROW0__LCD_DATA01                           0x0028 0x02F0 0x06DC 0x2 0x0
+#define MX6SLL_PAD_KEY_ROW0__SD1_WP                               0x0028 0x02F0 0x0774 0x4 0x1
+#define MX6SLL_PAD_KEY_ROW0__GPIO3_IO25                           0x0028 0x02F0 0x0000 0x5 0x0
+#define MX6SLL_PAD_KEY_COL1__KEY_COL1                             0x002C 0x02F4 0x06A4 0x0 0x0
+#define MX6SLL_PAD_KEY_COL1__ECSPI4_MOSI                          0x002C 0x02F4 0x0658 0x1 0x1
+#define MX6SLL_PAD_KEY_COL1__LCD_DATA02                           0x002C 0x02F4 0x06E0 0x2 0x0
+#define MX6SLL_PAD_KEY_COL1__SD3_DATA4                            0x002C 0x02F4 0x0784 0x4 0x0
+#define MX6SLL_PAD_KEY_COL1__GPIO3_IO26                           0x002C 0x02F4 0x0000 0x5 0x0
+#define MX6SLL_PAD_KEY_ROW1__KEY_ROW1                             0x0030 0x02F8 0x06C4 0x0 0x0
+#define MX6SLL_PAD_KEY_ROW1__ECSPI4_MISO                          0x0030 0x02F8 0x0654 0x1 0x1
+#define MX6SLL_PAD_KEY_ROW1__LCD_DATA03                           0x0030 0x02F8 0x06E4 0x2 0x0
+#define MX6SLL_PAD_KEY_ROW1__CSI_FIELD                            0x0030 0x02F8 0x0000 0x3 0x0
+#define MX6SLL_PAD_KEY_ROW1__SD3_DATA5                            0x0030 0x02F8 0x0788 0x4 0x0
+#define MX6SLL_PAD_KEY_ROW1__GPIO3_IO27                           0x0030 0x02F8 0x0000 0x5 0x0
+#define MX6SLL_PAD_KEY_COL2__KEY_COL2                             0x0034 0x02FC 0x06A8 0x0 0x0
+#define MX6SLL_PAD_KEY_COL2__ECSPI4_SS0                           0x0034 0x02FC 0x065C 0x1 0x1
+#define MX6SLL_PAD_KEY_COL2__LCD_DATA04                           0x0034 0x02FC 0x06E8 0x2 0x0
+#define MX6SLL_PAD_KEY_COL2__CSI_DATA12                           0x0034 0x02FC 0x05B8 0x3 0x1
+#define MX6SLL_PAD_KEY_COL2__SD3_DATA6                            0x0034 0x02FC 0x078C 0x4 0x0
+#define MX6SLL_PAD_KEY_COL2__GPIO3_IO28                           0x0034 0x02FC 0x0000 0x5 0x0
+#define MX6SLL_PAD_KEY_ROW2__KEY_ROW2                             0x0038 0x0300 0x06C8 0x0 0x0
+#define MX6SLL_PAD_KEY_ROW2__ECSPI4_SCLK                          0x0038 0x0300 0x0650 0x1 0x1
+#define MX6SLL_PAD_KEY_ROW2__LCD_DATA05                           0x0038 0x0300 0x06EC 0x2 0x0
+#define MX6SLL_PAD_KEY_ROW2__CSI_DATA13                           0x0038 0x0300 0x05BC 0x3 0x1
+#define MX6SLL_PAD_KEY_ROW2__SD3_DATA7                            0x0038 0x0300 0x0790 0x4 0x0
+#define MX6SLL_PAD_KEY_ROW2__GPIO3_IO29                           0x0038 0x0300 0x0000 0x5 0x0
+#define MX6SLL_PAD_KEY_COL3__KEY_COL3                             0x003C 0x0304 0x06AC 0x0 0x0
+#define MX6SLL_PAD_KEY_COL3__AUD6_RXFS                            0x003C 0x0304 0x05A0 0x1 0x1
+#define MX6SLL_PAD_KEY_COL3__LCD_DATA06                           0x003C 0x0304 0x06F0 0x2 0x0
+#define MX6SLL_PAD_KEY_COL3__CSI_DATA14                           0x003C 0x0304 0x05C0 0x3 0x1
+#define MX6SLL_PAD_KEY_COL3__GPIO3_IO30                           0x003C 0x0304 0x0000 0x5 0x0
+#define MX6SLL_PAD_KEY_COL3__SD1_RESET                            0x003C 0x0304 0x0000 0x6 0x0
+#define MX6SLL_PAD_KEY_ROW3__KEY_ROW3                             0x0040 0x0308 0x06CC 0x0 0x1
+#define MX6SLL_PAD_KEY_ROW3__AUD6_RXC                             0x0040 0x0308 0x059C 0x1 0x1
+#define MX6SLL_PAD_KEY_ROW3__LCD_DATA07                           0x0040 0x0308 0x06F4 0x2 0x1
+#define MX6SLL_PAD_KEY_ROW3__CSI_DATA15                           0x0040 0x0308 0x05C4 0x3 0x2
+#define MX6SLL_PAD_KEY_ROW3__GPIO3_IO31                           0x0040 0x0308 0x0000 0x5 0x0
+#define MX6SLL_PAD_KEY_ROW3__SD1_VSELECT                          0x0040 0x0308 0x0000 0x6 0x0
+#define MX6SLL_PAD_KEY_COL4__KEY_COL4                             0x0044 0x030C 0x06B0 0x0 0x1
+#define MX6SLL_PAD_KEY_COL4__AUD6_RXD                             0x0044 0x030C 0x0594 0x1 0x1
+#define MX6SLL_PAD_KEY_COL4__LCD_DATA08                           0x0044 0x030C 0x06F8 0x2 0x1
+#define MX6SLL_PAD_KEY_COL4__CSI_DATA16                           0x0044 0x030C 0x0000 0x3 0x0
+#define MX6SLL_PAD_KEY_COL4__GPIO4_IO00                           0x0044 0x030C 0x0000 0x5 0x0
+#define MX6SLL_PAD_KEY_COL4__USB_OTG1_PWR                         0x0044 0x030C 0x0000 0x6 0x0
+#define MX6SLL_PAD_KEY_ROW4__KEY_ROW4                             0x0048 0x0310 0x06D0 0x0 0x1
+#define MX6SLL_PAD_KEY_ROW4__AUD6_TXC                             0x0048 0x0310 0x05A4 0x1 0x1
+#define MX6SLL_PAD_KEY_ROW4__LCD_DATA09                           0x0048 0x0310 0x06FC 0x2 0x1
+#define MX6SLL_PAD_KEY_ROW4__CSI_DATA17                           0x0048 0x0310 0x0000 0x3 0x0
+#define MX6SLL_PAD_KEY_ROW4__GPIO4_IO01                           0x0048 0x0310 0x0000 0x5 0x0
+#define MX6SLL_PAD_KEY_ROW4__USB_OTG1_OC                          0x0048 0x0310 0x076C 0x6 0x2
+#define MX6SLL_PAD_KEY_COL5__KEY_COL5                             0x004C 0x0314 0x0694 0x0 0x1
+#define MX6SLL_PAD_KEY_COL5__AUD6_TXFS                            0x004C 0x0314 0x05A8 0x1 0x1
+#define MX6SLL_PAD_KEY_COL5__LCD_DATA10                           0x004C 0x0314 0x0700 0x2 0x0
+#define MX6SLL_PAD_KEY_COL5__CSI_DATA18                           0x004C 0x0314 0x0000 0x3 0x0
+#define MX6SLL_PAD_KEY_COL5__GPIO4_IO02                           0x004C 0x0314 0x0000 0x5 0x0
+#define MX6SLL_PAD_KEY_COL5__USB_OTG2_PWR                         0x004C 0x0314 0x0000 0x6 0x0
+#define MX6SLL_PAD_KEY_ROW5__KEY_ROW5                             0x0050 0x0318 0x06B4 0x0 0x2
+#define MX6SLL_PAD_KEY_ROW5__AUD6_TXD                             0x0050 0x0318 0x0598 0x1 0x1
+#define MX6SLL_PAD_KEY_ROW5__LCD_DATA11                           0x0050 0x0318 0x0704 0x2 0x1
+#define MX6SLL_PAD_KEY_ROW5__CSI_DATA19                           0x0050 0x0318 0x0000 0x3 0x0
+#define MX6SLL_PAD_KEY_ROW5__GPIO4_IO03                           0x0050 0x0318 0x0000 0x5 0x0
+#define MX6SLL_PAD_KEY_ROW5__USB_OTG2_OC                          0x0050 0x0318 0x0768 0x6 0x3
+#define MX6SLL_PAD_KEY_COL6__KEY_COL6                             0x0054 0x031C 0x0698 0x0 0x2
+#define MX6SLL_PAD_KEY_COL6__UART4_DCE_RX                         0x0054 0x031C 0x075C 0x1 0x2
+#define MX6SLL_PAD_KEY_COL6__UART4_DTE_TX                         0x0054 0x031C 0x0000 0x1 0x0
+#define MX6SLL_PAD_KEY_COL6__LCD_DATA12                           0x0054 0x031C 0x0708 0x2 0x1
+#define MX6SLL_PAD_KEY_COL6__CSI_DATA20                           0x0054 0x031C 0x0000 0x3 0x0
+#define MX6SLL_PAD_KEY_COL6__GPIO4_IO04                           0x0054 0x031C 0x0000 0x5 0x0
+#define MX6SLL_PAD_KEY_COL6__SD3_RESET                            0x0054 0x031C 0x0000 0x6 0x0
+#define MX6SLL_PAD_KEY_ROW6__KEY_ROW6                             0x0058 0x0320 0x06B8 0x0 0x2
+#define MX6SLL_PAD_KEY_ROW6__UART4_DCE_TX                         0x0058 0x0320 0x0000 0x1 0x0
+#define MX6SLL_PAD_KEY_ROW6__UART4_DTE_RX                         0x0058 0x0320 0x075C 0x1 0x3
+#define MX6SLL_PAD_KEY_ROW6__LCD_DATA13                           0x0058 0x0320 0x070C 0x2 0x1
+#define MX6SLL_PAD_KEY_ROW6__CSI_DATA21                           0x0058 0x0320 0x0000 0x3 0x0
+#define MX6SLL_PAD_KEY_ROW6__GPIO4_IO05                           0x0058 0x0320 0x0000 0x5 0x0
+#define MX6SLL_PAD_KEY_ROW6__SD3_VSELECT                          0x0058 0x0320 0x0000 0x6 0x0
+#define MX6SLL_PAD_KEY_COL7__KEY_COL7                             0x005C 0x0324 0x069C 0x0 0x2
+#define MX6SLL_PAD_KEY_COL7__UART4_DCE_RTS                        0x005C 0x0324 0x0758 0x1 0x2
+#define MX6SLL_PAD_KEY_COL7__UART4_DTE_CTS                        0x005C 0x0324 0x0000 0x1 0x0
+#define MX6SLL_PAD_KEY_COL7__LCD_DATA14                           0x005C 0x0324 0x0710 0x2 0x1
+#define MX6SLL_PAD_KEY_COL7__CSI_DATA22                           0x005C 0x0324 0x0000 0x3 0x0
+#define MX6SLL_PAD_KEY_COL7__GPIO4_IO06                           0x005C 0x0324 0x0000 0x5 0x0
+#define MX6SLL_PAD_KEY_COL7__SD1_WP                               0x005C 0x0324 0x0774 0x6 0x3
+#define MX6SLL_PAD_KEY_ROW7__KEY_ROW7                             0x0060 0x0328 0x06BC 0x0 0x2
+#define MX6SLL_PAD_KEY_ROW7__UART4_DCE_CTS                        0x0060 0x0328 0x0000 0x1 0x0
+#define MX6SLL_PAD_KEY_ROW7__UART4_DTE_RTS                        0x0060 0x0328 0x0758 0x1 0x3
+#define MX6SLL_PAD_KEY_ROW7__LCD_DATA15                           0x0060 0x0328 0x0714 0x2 0x1
+#define MX6SLL_PAD_KEY_ROW7__CSI_DATA23                           0x0060 0x0328 0x0000 0x3 0x0
+#define MX6SLL_PAD_KEY_ROW7__GPIO4_IO07                           0x0060 0x0328 0x0000 0x5 0x0
+#define MX6SLL_PAD_KEY_ROW7__SD1_CD_B                             0x0060 0x0328 0x0770 0x6 0x3
+#define MX6SLL_PAD_EPDC_DATA00__EPDC_DATA00                       0x0064 0x032C 0x0000 0x0 0x0
+#define MX6SLL_PAD_EPDC_DATA00__ECSPI4_MOSI                       0x0064 0x032C 0x0658 0x1 0x2
+#define MX6SLL_PAD_EPDC_DATA00__LCD_DATA24                        0x0064 0x032C 0x0000 0x2 0x0
+#define MX6SLL_PAD_EPDC_DATA00__CSI_DATA00                        0x0064 0x032C 0x05C8 0x3 0x2
+#define MX6SLL_PAD_EPDC_DATA00__GPIO1_IO07                        0x0064 0x032C 0x0000 0x5 0x0
+#define MX6SLL_PAD_EPDC_DATA01__EPDC_DATA01                       0x0068 0x0330 0x0000 0x0 0x0
+#define MX6SLL_PAD_EPDC_DATA01__ECSPI4_MISO                       0x0068 0x0330 0x0654 0x1 0x2
+#define MX6SLL_PAD_EPDC_DATA01__LCD_DATA25                        0x0068 0x0330 0x0000 0x2 0x0
+#define MX6SLL_PAD_EPDC_DATA01__CSI_DATA01                        0x0068 0x0330 0x05CC 0x3 0x2
+#define MX6SLL_PAD_EPDC_DATA01__GPIO1_IO08                        0x0068 0x0330 0x0000 0x5 0x0
+#define MX6SLL_PAD_EPDC_DATA02__EPDC_DATA02                       0x006C 0x0334 0x0000 0x0 0x0
+#define MX6SLL_PAD_EPDC_DATA02__ECSPI4_SS0                        0x006C 0x0334 0x065C 0x1 0x2
+#define MX6SLL_PAD_EPDC_DATA02__LCD_DATA26                        0x006C 0x0334 0x0000 0x2 0x0
+#define MX6SLL_PAD_EPDC_DATA02__CSI_DATA02                        0x006C 0x0334 0x05D0 0x3 0x2
+#define MX6SLL_PAD_EPDC_DATA02__GPIO1_IO09                        0x006C 0x0334 0x0000 0x5 0x0
+#define MX6SLL_PAD_EPDC_DATA03__EPDC_DATA03                       0x0070 0x0338 0x0000 0x0 0x0
+#define MX6SLL_PAD_EPDC_DATA03__ECSPI4_SCLK                       0x0070 0x0338 0x0650 0x1 0x2
+#define MX6SLL_PAD_EPDC_DATA03__LCD_DATA27                        0x0070 0x0338 0x0000 0x2 0x0
+#define MX6SLL_PAD_EPDC_DATA03__CSI_DATA03                        0x0070 0x0338 0x05D4 0x3 0x2
+#define MX6SLL_PAD_EPDC_DATA03__GPIO1_IO10                        0x0070 0x0338 0x0000 0x5 0x0
+#define MX6SLL_PAD_EPDC_DATA04__EPDC_DATA04                       0x0074 0x033C 0x0000 0x0 0x0
+#define MX6SLL_PAD_EPDC_DATA04__ECSPI4_SS1                        0x0074 0x033C 0x0660 0x1 0x1
+#define MX6SLL_PAD_EPDC_DATA04__LCD_DATA28                        0x0074 0x033C 0x0000 0x2 0x0
+#define MX6SLL_PAD_EPDC_DATA04__CSI_DATA04                        0x0074 0x033C 0x05D8 0x3 0x2
+#define MX6SLL_PAD_EPDC_DATA04__GPIO1_IO11                        0x0074 0x033C 0x0000 0x5 0x0
+#define MX6SLL_PAD_EPDC_DATA05__EPDC_DATA05                       0x0078 0x0340 0x0000 0x0 0x0
+#define MX6SLL_PAD_EPDC_DATA05__ECSPI4_SS2                        0x0078 0x0340 0x0664 0x1 0x1
+#define MX6SLL_PAD_EPDC_DATA05__LCD_DATA29                        0x0078 0x0340 0x0000 0x2 0x0
+#define MX6SLL_PAD_EPDC_DATA05__CSI_DATA05                        0x0078 0x0340 0x05DC 0x3 0x2
+#define MX6SLL_PAD_EPDC_DATA05__GPIO1_IO12                        0x0078 0x0340 0x0000 0x5 0x0
+#define MX6SLL_PAD_EPDC_DATA06__EPDC_DATA06                       0x007C 0x0344 0x0000 0x0 0x0
+#define MX6SLL_PAD_EPDC_DATA06__ECSPI4_SS3                        0x007C 0x0344 0x0000 0x1 0x0
+#define MX6SLL_PAD_EPDC_DATA06__LCD_DATA30                        0x007C 0x0344 0x0000 0x2 0x0
+#define MX6SLL_PAD_EPDC_DATA06__CSI_DATA06                        0x007C 0x0344 0x05E0 0x3 0x2
+#define MX6SLL_PAD_EPDC_DATA06__GPIO1_IO13                        0x007C 0x0344 0x0000 0x5 0x0
+#define MX6SLL_PAD_EPDC_DATA07__EPDC_DATA07                       0x0080 0x0348 0x0000 0x0 0x0
+#define MX6SLL_PAD_EPDC_DATA07__ECSPI4_RDY                        0x0080 0x0348 0x0000 0x1 0x0
+#define MX6SLL_PAD_EPDC_DATA07__LCD_DATA31                        0x0080 0x0348 0x0000 0x2 0x0
+#define MX6SLL_PAD_EPDC_DATA07__CSI_DATA07                        0x0080 0x0348 0x05E4 0x3 0x2
+#define MX6SLL_PAD_EPDC_DATA07__GPIO1_IO14                        0x0080 0x0348 0x0000 0x5 0x0
+#define MX6SLL_PAD_EPDC_DATA08__EPDC_DATA08                       0x0084 0x034C 0x0000 0x0 0x0
+#define MX6SLL_PAD_EPDC_DATA08__ECSPI3_MOSI                       0x0084 0x034C 0x063C 0x1 0x2
+#define MX6SLL_PAD_EPDC_DATA08__EPDC_PWR_CTRL0                    0x0084 0x034C 0x0000 0x2 0x0
+#define MX6SLL_PAD_EPDC_DATA08__GPIO1_IO15                        0x0084 0x034C 0x0000 0x5 0x0
+#define MX6SLL_PAD_EPDC_DATA09__EPDC_DATA09                       0x0088 0x0350 0x0000 0x0 0x0
+#define MX6SLL_PAD_EPDC_DATA09__ECSPI3_MISO                       0x0088 0x0350 0x0638 0x1 0x2
+#define MX6SLL_PAD_EPDC_DATA09__EPDC_PWR_CTRL1                    0x0088 0x0350 0x0000 0x2 0x0
+#define MX6SLL_PAD_EPDC_DATA09__GPIO1_IO16                        0x0088 0x0350 0x0000 0x5 0x0
+#define MX6SLL_PAD_EPDC_DATA10__EPDC_DATA10                       0x008C 0x0354 0x0000 0x0 0x0
+#define MX6SLL_PAD_EPDC_DATA10__ECSPI3_SS0                        0x008C 0x0354 0x0648 0x1 0x2
+#define MX6SLL_PAD_EPDC_DATA10__EPDC_PWR_CTRL2                    0x008C 0x0354 0x0000 0x2 0x0
+#define MX6SLL_PAD_EPDC_DATA10__GPIO1_IO17                        0x008C 0x0354 0x0000 0x5 0x0
+#define MX6SLL_PAD_EPDC_DATA11__EPDC_DATA11                       0x0090 0x0358 0x0000 0x0 0x0
+#define MX6SLL_PAD_EPDC_DATA11__ECSPI3_SCLK                       0x0090 0x0358 0x0630 0x1 0x2
+#define MX6SLL_PAD_EPDC_DATA11__EPDC_PWR_CTRL3                    0x0090 0x0358 0x0000 0x2 0x0
+#define MX6SLL_PAD_EPDC_DATA11__GPIO1_IO18                        0x0090 0x0358 0x0000 0x5 0x0
+#define MX6SLL_PAD_EPDC_DATA12__EPDC_DATA12                       0x0094 0x035C 0x0000 0x0 0x0
+#define MX6SLL_PAD_EPDC_DATA12__UART2_DCE_RX                      0x0094 0x035C 0x074C 0x1 0x4
+#define MX6SLL_PAD_EPDC_DATA12__UART2_DTE_TX                      0x0094 0x035C 0x0000 0x1 0x0
+#define MX6SLL_PAD_EPDC_DATA12__EPDC_PWR_COM                      0x0094 0x035C 0x0000 0x2 0x0
+#define MX6SLL_PAD_EPDC_DATA12__GPIO1_IO19                        0x0094 0x035C 0x0000 0x5 0x0
+#define MX6SLL_PAD_EPDC_DATA12__ECSPI3_SS1                        0x0094 0x035C 0x064C 0x6 0x1
+#define MX6SLL_PAD_EPDC_DATA13__EPDC_DATA13                       0x0098 0x0360 0x0000 0x0 0x0
+#define MX6SLL_PAD_EPDC_DATA13__UART2_DCE_TX                      0x0098 0x0360 0x0000 0x1 0x0
+#define MX6SLL_PAD_EPDC_DATA13__UART2_DTE_RX                      0x0098 0x0360 0x074C 0x1 0x5
+#define MX6SLL_PAD_EPDC_DATA13__EPDC_PWR_IRQ                      0x0098 0x0360 0x0668 0x2 0x0
+#define MX6SLL_PAD_EPDC_DATA13__GPIO1_IO20                        0x0098 0x0360 0x0000 0x5 0x0
+#define MX6SLL_PAD_EPDC_DATA13__ECSPI3_SS2                        0x0098 0x0360 0x0640 0x6 0x1
+#define MX6SLL_PAD_EPDC_DATA14__EPDC_DATA14                       0x009C 0x0364 0x0000 0x0 0x0
+#define MX6SLL_PAD_EPDC_DATA14__UART2_DCE_RTS                     0x009C 0x0364 0x0748 0x1 0x4
+#define MX6SLL_PAD_EPDC_DATA14__UART2_DTE_CTS                     0x009C 0x0364 0x0000 0x1 0x0
+#define MX6SLL_PAD_EPDC_DATA14__EPDC_PWR_STAT                     0x009C 0x0364 0x066C 0x2 0x0
+#define MX6SLL_PAD_EPDC_DATA14__GPIO1_IO21                        0x009C 0x0364 0x0000 0x5 0x0
+#define MX6SLL_PAD_EPDC_DATA14__ECSPI3_SS3                        0x009C 0x0364 0x0644 0x6 0x1
+#define MX6SLL_PAD_EPDC_DATA15__EPDC_DATA15                       0x00A0 0x0368 0x0000 0x0 0x0
+#define MX6SLL_PAD_EPDC_DATA15__UART2_DCE_CTS                     0x00A0 0x0368 0x0000 0x1 0x0
+#define MX6SLL_PAD_EPDC_DATA15__UART2_DTE_RTS                     0x00A0 0x0368 0x0748 0x1 0x5
+#define MX6SLL_PAD_EPDC_DATA15__EPDC_PWR_WAKE                     0x00A0 0x0368 0x0000 0x2 0x0
+#define MX6SLL_PAD_EPDC_DATA15__GPIO1_IO22                        0x00A0 0x0368 0x0000 0x5 0x0
+#define MX6SLL_PAD_EPDC_DATA15__ECSPI3_RDY                        0x00A0 0x0368 0x0634 0x6 0x1
+#define MX6SLL_PAD_EPDC_SDCLK__EPDC_SDCLK_P                       0x00A4 0x036C 0x0000 0x0 0x0
+#define MX6SLL_PAD_EPDC_SDCLK__ECSPI2_MOSI                        0x00A4 0x036C 0x0624 0x1 0x2
+#define MX6SLL_PAD_EPDC_SDCLK__I2C2_SCL                           0x00A4 0x036C 0x0684 0x2 0x2
+#define MX6SLL_PAD_EPDC_SDCLK__CSI_DATA08                         0x00A4 0x036C 0x05E8 0x3 0x2
+#define MX6SLL_PAD_EPDC_SDCLK__GPIO1_IO23                         0x00A4 0x036C 0x0000 0x5 0x0
+#define MX6SLL_PAD_EPDC_SDLE__EPDC_SDLE                           0x00A8 0x0370 0x0000 0x0 0x0
+#define MX6SLL_PAD_EPDC_SDLE__ECSPI2_MISO                         0x00A8 0x0370 0x0620 0x1 0x2
+#define MX6SLL_PAD_EPDC_SDLE__I2C2_SDA                            0x00A8 0x0370 0x0688 0x2 0x2
+#define MX6SLL_PAD_EPDC_SDLE__CSI_DATA09                          0x00A8 0x0370 0x05EC 0x3 0x2
+#define MX6SLL_PAD_EPDC_SDLE__GPIO1_IO24                          0x00A8 0x0370 0x0000 0x5 0x0
+#define MX6SLL_PAD_EPDC_SDOE__EPDC_SDOE                           0x00AC 0x0374 0x0000 0x0 0x0
+#define MX6SLL_PAD_EPDC_SDOE__ECSPI2_SS0                          0x00AC 0x0374 0x0628 0x1 0x1
+#define MX6SLL_PAD_EPDC_SDOE__CSI_DATA10                          0x00AC 0x0374 0x05B0 0x3 0x2
+#define MX6SLL_PAD_EPDC_SDOE__GPIO1_IO25                          0x00AC 0x0374 0x0000 0x5 0x0
+#define MX6SLL_PAD_EPDC_SDSHR__EPDC_SDSHR                         0x00B0 0x0378 0x0000 0x0 0x0
+#define MX6SLL_PAD_EPDC_SDSHR__ECSPI2_SCLK                        0x00B0 0x0378 0x061C 0x1 0x2
+#define MX6SLL_PAD_EPDC_SDSHR__EPDC_SDCE4                         0x00B0 0x0378 0x0000 0x2 0x0
+#define MX6SLL_PAD_EPDC_SDSHR__CSI_DATA11                         0x00B0 0x0378 0x05B4 0x3 0x2
+#define MX6SLL_PAD_EPDC_SDSHR__GPIO1_IO26                         0x00B0 0x0378 0x0000 0x5 0x0
+#define MX6SLL_PAD_EPDC_SDCE0__EPDC_SDCE0                         0x00B4 0x037C 0x0000 0x0 0x0
+#define MX6SLL_PAD_EPDC_SDCE0__ECSPI2_SS1                         0x00B4 0x037C 0x062C 0x1 0x1
+#define MX6SLL_PAD_EPDC_SDCE0__PWM3_OUT                           0x00B4 0x037C 0x0000 0x2 0x0
+#define MX6SLL_PAD_EPDC_SDCE0__GPIO1_IO27                         0x00B4 0x037C 0x0000 0x5 0x0
+#define MX6SLL_PAD_EPDC_SDCE1__EPDC_SDCE1                         0x00B8 0x0380 0x0000 0x0 0x0
+#define MX6SLL_PAD_EPDC_SDCE1__WDOG2_B                            0x00B8 0x0380 0x0000 0x1 0x0
+#define MX6SLL_PAD_EPDC_SDCE1__PWM4_OUT                           0x00B8 0x0380 0x0000 0x2 0x0
+#define MX6SLL_PAD_EPDC_SDCE1__GPIO1_IO28                         0x00B8 0x0380 0x0000 0x5 0x0
+#define MX6SLL_PAD_EPDC_SDCE2__EPDC_SDCE2                         0x00BC 0x0384 0x0000 0x0 0x0
+#define MX6SLL_PAD_EPDC_SDCE2__I2C3_SCL                           0x00BC 0x0384 0x068C 0x1 0x2
+#define MX6SLL_PAD_EPDC_SDCE2__PWM1_OUT                           0x00BC 0x0384 0x0000 0x2 0x0
+#define MX6SLL_PAD_EPDC_SDCE2__GPIO1_IO29                         0x00BC 0x0384 0x0000 0x5 0x0
+#define MX6SLL_PAD_EPDC_SDCE3__EPDC_SDCE3                         0x00C0 0x0388 0x0000 0x0 0x0
+#define MX6SLL_PAD_EPDC_SDCE3__I2C3_SDA                           0x00C0 0x0388 0x0690 0x1 0x2
+#define MX6SLL_PAD_EPDC_SDCE3__PWM2_OUT                           0x00C0 0x0388 0x0000 0x2 0x0
+#define MX6SLL_PAD_EPDC_SDCE3__GPIO1_IO30                         0x00C0 0x0388 0x0000 0x5 0x0
+#define MX6SLL_PAD_EPDC_GDCLK__EPDC_GDCLK                         0x00C4 0x038C 0x0000 0x0 0x0
+#define MX6SLL_PAD_EPDC_GDCLK__ECSPI2_SS2                         0x00C4 0x038C 0x0000 0x1 0x0
+#define MX6SLL_PAD_EPDC_GDCLK__CSI_PIXCLK                         0x00C4 0x038C 0x05F4 0x3 0x2
+#define MX6SLL_PAD_EPDC_GDCLK__GPIO1_IO31                         0x00C4 0x038C 0x0000 0x5 0x0
+#define MX6SLL_PAD_EPDC_GDCLK__SD2_RESET                          0x00C4 0x038C 0x0000 0x6 0x0
+#define MX6SLL_PAD_EPDC_GDOE__EPDC_GDOE                           0x00C8 0x0390 0x0000 0x0 0x0
+#define MX6SLL_PAD_EPDC_GDOE__ECSPI2_SS3                          0x00C8 0x0390 0x0000 0x1 0x0
+#define MX6SLL_PAD_EPDC_GDOE__CSI_HSYNC                           0x00C8 0x0390 0x05F0 0x3 0x2
+#define MX6SLL_PAD_EPDC_GDOE__GPIO2_IO00                          0x00C8 0x0390 0x0000 0x5 0x0
+#define MX6SLL_PAD_EPDC_GDOE__SD2_VSELECT                         0x00C8 0x0390 0x0000 0x6 0x0
+#define MX6SLL_PAD_EPDC_GDRL__EPDC_GDRL                           0x00CC 0x0394 0x0000 0x0 0x0
+#define MX6SLL_PAD_EPDC_GDRL__ECSPI2_RDY                          0x00CC 0x0394 0x0000 0x1 0x0
+#define MX6SLL_PAD_EPDC_GDRL__CSI_MCLK                            0x00CC 0x0394 0x0000 0x3 0x0
+#define MX6SLL_PAD_EPDC_GDRL__GPIO2_IO01                          0x00CC 0x0394 0x0000 0x5 0x0
+#define MX6SLL_PAD_EPDC_GDRL__SD2_WP                              0x00CC 0x0394 0x077C 0x6 0x2
+#define MX6SLL_PAD_EPDC_GDSP__EPDC_GDSP                           0x00D0 0x0398 0x0000 0x0 0x0
+#define MX6SLL_PAD_EPDC_GDSP__PWM4_OUT                            0x00D0 0x0398 0x0000 0x1 0x0
+#define MX6SLL_PAD_EPDC_GDSP__CSI_VSYNC                           0x00D0 0x0398 0x05F8 0x3 0x2
+#define MX6SLL_PAD_EPDC_GDSP__GPIO2_IO02                          0x00D0 0x0398 0x0000 0x5 0x0
+#define MX6SLL_PAD_EPDC_GDSP__SD2_CD_B                            0x00D0 0x0398 0x0778 0x6 0x2
+#define MX6SLL_PAD_EPDC_VCOM0__EPDC_VCOM0                         0x00D4 0x039C 0x0000 0x0 0x0
+#define MX6SLL_PAD_EPDC_VCOM0__AUD5_RXFS                          0x00D4 0x039C 0x0588 0x1 0x1
+#define MX6SLL_PAD_EPDC_VCOM0__UART3_DCE_RX                       0x00D4 0x039C 0x0754 0x2 0x4
+#define MX6SLL_PAD_EPDC_VCOM0__UART3_DTE_TX                       0x00D4 0x039C 0x0000 0x2 0x0
+#define MX6SLL_PAD_EPDC_VCOM0__GPIO2_IO03                         0x00D4 0x039C 0x0000 0x5 0x0
+#define MX6SLL_PAD_EPDC_VCOM0__EPDC_SDCE5                         0x00D4 0x039C 0x0000 0x6 0x0
+#define MX6SLL_PAD_EPDC_VCOM1__EPDC_VCOM1                         0x00D8 0x03A0 0x0000 0x0 0x0
+#define MX6SLL_PAD_EPDC_VCOM1__AUD5_RXD                           0x00D8 0x03A0 0x057C 0x1 0x1
+#define MX6SLL_PAD_EPDC_VCOM1__UART3_DCE_TX                       0x00D8 0x03A0 0x0000 0x2 0x0
+#define MX6SLL_PAD_EPDC_VCOM1__UART3_DTE_RX                       0x00D8 0x03A0 0x0754 0x2 0x5
+#define MX6SLL_PAD_EPDC_VCOM1__GPIO2_IO04                         0x00D8 0x03A0 0x0000 0x5 0x0
+#define MX6SLL_PAD_EPDC_VCOM1__EPDC_SDCE6                         0x00D8 0x03A0 0x0000 0x6 0x0
+#define MX6SLL_PAD_EPDC_BDR0__EPDC_BDR0                           0x00DC 0x03A4 0x0000 0x0 0x0
+#define MX6SLL_PAD_EPDC_BDR0__UART3_DCE_RTS                       0x00DC 0x03A4 0x0750 0x2 0x2
+#define MX6SLL_PAD_EPDC_BDR0__UART3_DTE_CTS                       0x00DC 0x03A4 0x0000 0x2 0x0
+#define MX6SLL_PAD_EPDC_BDR0__GPIO2_IO05                          0x00DC 0x03A4 0x0000 0x5 0x0
+#define MX6SLL_PAD_EPDC_BDR0__EPDC_SDCE7                          0x00DC 0x03A4 0x0000 0x6 0x0
+#define MX6SLL_PAD_EPDC_BDR1__EPDC_BDR1                           0x00E0 0x03A8 0x0000 0x0 0x0
+#define MX6SLL_PAD_EPDC_BDR1__UART3_DCE_CTS                       0x00E0 0x03A8 0x0000 0x2 0x0
+#define MX6SLL_PAD_EPDC_BDR1__UART3_DTE_RTS                       0x00E0 0x03A8 0x0750 0x2 0x3
+#define MX6SLL_PAD_EPDC_BDR1__GPIO2_IO06                          0x00E0 0x03A8 0x0000 0x5 0x0
+#define MX6SLL_PAD_EPDC_BDR1__EPDC_SDCE8                          0x00E0 0x03A8 0x0000 0x6 0x0
+#define MX6SLL_PAD_EPDC_PWR_CTRL0__EPDC_PWR_CTRL0                 0x00E4 0x03AC 0x0000 0x0 0x0
+#define MX6SLL_PAD_EPDC_PWR_CTRL0__AUD5_RXC                       0x00E4 0x03AC 0x0584 0x1 0x1
+#define MX6SLL_PAD_EPDC_PWR_CTRL0__LCD_DATA16                     0x00E4 0x03AC 0x0718 0x2 0x1
+#define MX6SLL_PAD_EPDC_PWR_CTRL0__GPIO2_IO07                     0x00E4 0x03AC 0x0000 0x5 0x0
+#define MX6SLL_PAD_EPDC_PWR_CTRL1__EPDC_PWR_CTRL1                 0x00E8 0x03B0 0x0000 0x0 0x0
+#define MX6SLL_PAD_EPDC_PWR_CTRL1__AUD5_TXFS                      0x00E8 0x03B0 0x0590 0x1 0x1
+#define MX6SLL_PAD_EPDC_PWR_CTRL1__LCD_DATA17                     0x00E8 0x03B0 0x071C 0x2 0x1
+#define MX6SLL_PAD_EPDC_PWR_CTRL1__GPIO2_IO08                     0x00E8 0x03B0 0x0000 0x5 0x0
+#define MX6SLL_PAD_EPDC_PWR_CTRL2__EPDC_PWR_CTRL2                 0x00EC 0x03B4 0x0000 0x0 0x0
+#define MX6SLL_PAD_EPDC_PWR_CTRL2__AUD5_TXD                       0x00EC 0x03B4 0x0580 0x1 0x1
+#define MX6SLL_PAD_EPDC_PWR_CTRL2__LCD_DATA18                     0x00EC 0x03B4 0x0720 0x2 0x1
+#define MX6SLL_PAD_EPDC_PWR_CTRL2__GPIO2_IO09                     0x00EC 0x03B4 0x0000 0x5 0x0
+#define MX6SLL_PAD_EPDC_PWR_CTRL3__EPDC_PWR_CTRL3                 0x00F0 0x03B8 0x0000 0x0 0x0
+#define MX6SLL_PAD_EPDC_PWR_CTRL3__AUD5_TXC                       0x00F0 0x03B8 0x058C 0x1 0x1
+#define MX6SLL_PAD_EPDC_PWR_CTRL3__LCD_DATA19                     0x00F0 0x03B8 0x0724 0x2 0x1
+#define MX6SLL_PAD_EPDC_PWR_CTRL3__GPIO2_IO10                     0x00F0 0x03B8 0x0000 0x5 0x0
+#define MX6SLL_PAD_EPDC_PWR_COM__EPDC_PWR_COM                     0x00F4 0x03BC 0x0000 0x0 0x0
+#define MX6SLL_PAD_EPDC_PWR_COM__LCD_DATA20                       0x00F4 0x03BC 0x0728 0x2 0x1
+#define MX6SLL_PAD_EPDC_PWR_COM__USB_OTG1_ID                      0x00F4 0x03BC 0x055C 0x4 0x4
+#define MX6SLL_PAD_EPDC_PWR_COM__GPIO2_IO11                       0x00F4 0x03BC 0x0000 0x5 0x0
+#define MX6SLL_PAD_EPDC_PWR_COM__SD3_RESET                        0x00F4 0x03BC 0x0000 0x6 0x0
+#define MX6SLL_PAD_EPDC_PWR_IRQ__EPDC_PWR_IRQ                     0x00F8 0x03C0 0x0668 0x0 0x1
+#define MX6SLL_PAD_EPDC_PWR_IRQ__LCD_DATA21                       0x00F8 0x03C0 0x072C 0x2 0x1
+#define MX6SLL_PAD_EPDC_PWR_IRQ__USB_OTG2_ID                      0x00F8 0x03C0 0x0560 0x4 0x3
+#define MX6SLL_PAD_EPDC_PWR_IRQ__GPIO2_IO12                       0x00F8 0x03C0 0x0000 0x5 0x0
+#define MX6SLL_PAD_EPDC_PWR_IRQ__SD3_VSELECT                      0x00F8 0x03C0 0x0000 0x6 0x0
+#define MX6SLL_PAD_EPDC_PWR_STAT__EPDC_PWR_STAT                   0x00FC 0x03C4 0x066C 0x0 0x1
+#define MX6SLL_PAD_EPDC_PWR_STAT__LCD_DATA22                      0x00FC 0x03C4 0x0730 0x2 0x1
+#define MX6SLL_PAD_EPDC_PWR_STAT__ARM_EVENTI                      0x00FC 0x03C4 0x0000 0x4 0x0
+#define MX6SLL_PAD_EPDC_PWR_STAT__GPIO2_IO13                      0x00FC 0x03C4 0x0000 0x5 0x0
+#define MX6SLL_PAD_EPDC_PWR_STAT__SD3_WP                          0x00FC 0x03C4 0x0794 0x6 0x2
+#define MX6SLL_PAD_EPDC_PWR_WAKE__EPDC_PWR_WAKE                   0x0100 0x03C8 0x0000 0x0 0x0
+#define MX6SLL_PAD_EPDC_PWR_WAKE__LCD_DATA23                      0x0100 0x03C8 0x0734 0x2 0x1
+#define MX6SLL_PAD_EPDC_PWR_WAKE__ARM_EVENTO                      0x0100 0x03C8 0x0000 0x4 0x0
+#define MX6SLL_PAD_EPDC_PWR_WAKE__GPIO2_IO14                      0x0100 0x03C8 0x0000 0x5 0x0
+#define MX6SLL_PAD_EPDC_PWR_WAKE__SD3_CD_B                        0x0100 0x03C8 0x0780 0x6 0x2
+#define MX6SLL_PAD_LCD_CLK__LCD_CLK                               0x0104 0x03CC 0x0000 0x0 0x0
+#define MX6SLL_PAD_LCD_CLK__LCD_WR_RWN                            0x0104 0x03CC 0x0000 0x2 0x0
+#define MX6SLL_PAD_LCD_CLK__PWM4_OUT                              0x0104 0x03CC 0x0000 0x4 0x0
+#define MX6SLL_PAD_LCD_CLK__GPIO2_IO15                            0x0104 0x03CC 0x0000 0x5 0x0
+#define MX6SLL_PAD_LCD_ENABLE__LCD_ENABLE                         0x0108 0x03D0 0x0000 0x0 0x0
+#define MX6SLL_PAD_LCD_ENABLE__LCD_RD_E                           0x0108 0x03D0 0x0000 0x2 0x0
+#define MX6SLL_PAD_LCD_ENABLE__UART2_DCE_RX                       0x0108 0x03D0 0x0000 0x4 0x0
+#define MX6SLL_PAD_LCD_ENABLE__UART2_DTE_TX                       0x0108 0x03D0 0x0000 0x4 0x0
+#define MX6SLL_PAD_LCD_ENABLE__GPIO2_IO16                         0x0108 0x03D0 0x0000 0x5 0x0
+#define MX6SLL_PAD_LCD_HSYNC__LCD_HSYNC                           0x010C 0x03D4 0x06D4 0x0 0x0
+#define MX6SLL_PAD_LCD_HSYNC__LCD_CS                              0x010C 0x03D4 0x0000 0x2 0x0
+#define MX6SLL_PAD_LCD_HSYNC__UART2_DCE_TX                        0x010C 0x03D4 0x0000 0x4 0x0
+#define MX6SLL_PAD_LCD_HSYNC__UART2_DTE_RX                        0x010C 0x03D4 0x074C 0x4 0x1
+#define MX6SLL_PAD_LCD_HSYNC__GPIO2_IO17                          0x010C 0x03D4 0x0000 0x5 0x0
+#define MX6SLL_PAD_LCD_HSYNC__ARM_TRACE_CLK                       0x010C 0x03D4 0x0000 0x6 0x0
+#define MX6SLL_PAD_LCD_VSYNC__LCD_VSYNC                           0x0110 0x03D8 0x0000 0x0 0x0
+#define MX6SLL_PAD_LCD_VSYNC__LCD_RS                              0x0110 0x03D8 0x0000 0x2 0x0
+#define MX6SLL_PAD_LCD_VSYNC__UART2_DCE_RTS                       0x0110 0x03D8 0x0748 0x4 0x0
+#define MX6SLL_PAD_LCD_VSYNC__UART2_DTE_CTS                       0x0110 0x03D8 0x0000 0x4 0x0
+#define MX6SLL_PAD_LCD_VSYNC__GPIO2_IO18                          0x0110 0x03D8 0x0000 0x5 0x0
+#define MX6SLL_PAD_LCD_VSYNC__ARM_TRACE_CTL                       0x0110 0x03D8 0x0000 0x6 0x0
+#define MX6SLL_PAD_LCD_RESET__LCD_RESET                           0x0114 0x03DC 0x0000 0x0 0x0
+#define MX6SLL_PAD_LCD_RESET__LCD_BUSY                            0x0114 0x03DC 0x06D4 0x2 0x1
+#define MX6SLL_PAD_LCD_RESET__UART2_DCE_CTS                       0x0114 0x03DC 0x0000 0x4 0x0
+#define MX6SLL_PAD_LCD_RESET__UART2_DTE_RTS                       0x0114 0x03DC 0x0748 0x4 0x1
+#define MX6SLL_PAD_LCD_RESET__GPIO2_IO19                          0x0114 0x03DC 0x0000 0x5 0x0
+#define MX6SLL_PAD_LCD_RESET__CCM_PMIC_READY                      0x0114 0x03DC 0x05AC 0x6 0x2
+#define MX6SLL_PAD_LCD_DATA00__LCD_DATA00                         0x0118 0x03E0 0x06D8 0x0 0x1
+#define MX6SLL_PAD_LCD_DATA00__ECSPI1_MOSI                        0x0118 0x03E0 0x0608 0x1 0x0
+#define MX6SLL_PAD_LCD_DATA00__USB_OTG2_ID                        0x0118 0x03E0 0x0560 0x2 0x2
+#define MX6SLL_PAD_LCD_DATA00__PWM1_OUT                           0x0118 0x03E0 0x0000 0x3 0x0
+#define MX6SLL_PAD_LCD_DATA00__UART5_DTR_B                        0x0118 0x03E0 0x0000 0x4 0x0
+#define MX6SLL_PAD_LCD_DATA00__GPIO2_IO20                         0x0118 0x03E0 0x0000 0x5 0x0
+#define MX6SLL_PAD_LCD_DATA00__ARM_TRACE00                        0x0118 0x03E0 0x0000 0x6 0x0
+#define MX6SLL_PAD_LCD_DATA00__SRC_BOOT_CFG00                     0x0118 0x03E0 0x0000 0x7 0x0
+#define MX6SLL_PAD_LCD_DATA01__LCD_DATA01                         0x011C 0x03E4 0x06DC 0x0 0x1
+#define MX6SLL_PAD_LCD_DATA01__ECSPI1_MISO                        0x011C 0x03E4 0x0604 0x1 0x0
+#define MX6SLL_PAD_LCD_DATA01__USB_OTG1_ID                        0x011C 0x03E4 0x055C 0x2 0x3
+#define MX6SLL_PAD_LCD_DATA01__PWM2_OUT                           0x011C 0x03E4 0x0000 0x3 0x0
+#define MX6SLL_PAD_LCD_DATA01__AUD4_RXFS                          0x011C 0x03E4 0x0570 0x4 0x0
+#define MX6SLL_PAD_LCD_DATA01__GPIO2_IO21                         0x011C 0x03E4 0x0000 0x5 0x0
+#define MX6SLL_PAD_LCD_DATA01__ARM_TRACE01                        0x011C 0x03E4 0x0000 0x6 0x0
+#define MX6SLL_PAD_LCD_DATA01__SRC_BOOT_CFG01                     0x011C 0x03E4 0x0000 0x7 0x0
+#define MX6SLL_PAD_LCD_DATA02__LCD_DATA02                         0x0120 0x03E8 0x06E0 0x0 0x1
+#define MX6SLL_PAD_LCD_DATA02__ECSPI1_SS0                         0x0120 0x03E8 0x0614 0x1 0x0
+#define MX6SLL_PAD_LCD_DATA02__EPIT2_OUT                          0x0120 0x03E8 0x0000 0x2 0x0
+#define MX6SLL_PAD_LCD_DATA02__PWM3_OUT                           0x0120 0x03E8 0x0000 0x3 0x0
+#define MX6SLL_PAD_LCD_DATA02__AUD4_RXC                           0x0120 0x03E8 0x056C 0x4 0x0
+#define MX6SLL_PAD_LCD_DATA02__GPIO2_IO22                         0x0120 0x03E8 0x0000 0x5 0x0
+#define MX6SLL_PAD_LCD_DATA02__ARM_TRACE02                        0x0120 0x03E8 0x0000 0x6 0x0
+#define MX6SLL_PAD_LCD_DATA02__SRC_BOOT_CFG02                     0x0120 0x03E8 0x0000 0x7 0x0
+#define MX6SLL_PAD_LCD_DATA03__LCD_DATA03                         0x0124 0x03EC 0x06E4 0x0 0x1
+#define MX6SLL_PAD_LCD_DATA03__ECSPI1_SCLK                        0x0124 0x03EC 0x05FC 0x1 0x0
+#define MX6SLL_PAD_LCD_DATA03__UART5_DSR_B                        0x0124 0x03EC 0x0000 0x2 0x0
+#define MX6SLL_PAD_LCD_DATA03__PWM4_OUT                           0x0124 0x03EC 0x0000 0x3 0x0
+#define MX6SLL_PAD_LCD_DATA03__AUD4_RXD                           0x0124 0x03EC 0x0564 0x4 0x0
+#define MX6SLL_PAD_LCD_DATA03__GPIO2_IO23                         0x0124 0x03EC 0x0000 0x5 0x0
+#define MX6SLL_PAD_LCD_DATA03__ARM_TRACE03                        0x0124 0x03EC 0x0000 0x6 0x0
+#define MX6SLL_PAD_LCD_DATA03__SRC_BOOT_CFG03                     0x0124 0x03EC 0x0000 0x7 0x0
+#define MX6SLL_PAD_LCD_DATA04__LCD_DATA04                         0x0128 0x03F0 0x06E8 0x0 0x1
+#define MX6SLL_PAD_LCD_DATA04__ECSPI1_SS1                         0x0128 0x03F0 0x060C 0x1 0x1
+#define MX6SLL_PAD_LCD_DATA04__CSI_VSYNC                          0x0128 0x03F0 0x05F8 0x2 0x0
+#define MX6SLL_PAD_LCD_DATA04__WDOG2_RESET_B_DEB                  0x0128 0x03F0 0x0000 0x3 0x0
+#define MX6SLL_PAD_LCD_DATA04__AUD4_TXC                           0x0128 0x03F0 0x0574 0x4 0x0
+#define MX6SLL_PAD_LCD_DATA04__GPIO2_IO24                         0x0128 0x03F0 0x0000 0x5 0x0
+#define MX6SLL_PAD_LCD_DATA04__ARM_TRACE04                        0x0128 0x03F0 0x0000 0x6 0x0
+#define MX6SLL_PAD_LCD_DATA04__SRC_BOOT_CFG04                     0x0128 0x03F0 0x0000 0x7 0x0
+#define MX6SLL_PAD_LCD_DATA05__LCD_DATA05                         0x012C 0x03F4 0x06EC 0x0 0x1
+#define MX6SLL_PAD_LCD_DATA05__ECSPI1_SS2                         0x012C 0x03F4 0x0610 0x1 0x1
+#define MX6SLL_PAD_LCD_DATA05__CSI_HSYNC                          0x012C 0x03F4 0x05F0 0x2 0x0
+#define MX6SLL_PAD_LCD_DATA05__AUD4_TXFS                          0x012C 0x03F4 0x0578 0x4 0x0
+#define MX6SLL_PAD_LCD_DATA05__GPIO2_IO25                         0x012C 0x03F4 0x0000 0x5 0x0
+#define MX6SLL_PAD_LCD_DATA05__ARM_TRACE05                        0x012C 0x03F4 0x0000 0x6 0x0
+#define MX6SLL_PAD_LCD_DATA05__SRC_BOOT_CFG05                     0x012C 0x03F4 0x0000 0x7 0x0
+#define MX6SLL_PAD_LCD_DATA06__LCD_DATA06                         0x0130 0x03F8 0x06F0 0x0 0x1
+#define MX6SLL_PAD_LCD_DATA06__ECSPI1_SS3                         0x0130 0x03F8 0x0618 0x1 0x0
+#define MX6SLL_PAD_LCD_DATA06__CSI_PIXCLK                         0x0130 0x03F8 0x05F4 0x2 0x0
+#define MX6SLL_PAD_LCD_DATA06__AUD4_TXD                           0x0130 0x03F8 0x0568 0x4 0x0
+#define MX6SLL_PAD_LCD_DATA06__GPIO2_IO26                         0x0130 0x03F8 0x0000 0x5 0x0
+#define MX6SLL_PAD_LCD_DATA06__ARM_TRACE06                        0x0130 0x03F8 0x0000 0x6 0x0
+#define MX6SLL_PAD_LCD_DATA06__SRC_BOOT_CFG06                     0x0130 0x03F8 0x0000 0x7 0x0
+#define MX6SLL_PAD_LCD_DATA07__LCD_DATA07                         0x0134 0x03FC 0x06F4 0x0 0x0
+#define MX6SLL_PAD_LCD_DATA07__ECSPI1_RDY                         0x0134 0x03FC 0x0600 0x1 0x0
+#define MX6SLL_PAD_LCD_DATA07__CSI_MCLK                           0x0134 0x03FC 0x0000 0x2 0x0
+#define MX6SLL_PAD_LCD_DATA07__AUDIO_CLK_OUT                      0x0134 0x03FC 0x0000 0x4 0x0
+#define MX6SLL_PAD_LCD_DATA07__GPIO2_IO27                         0x0134 0x03FC 0x0000 0x5 0x0
+#define MX6SLL_PAD_LCD_DATA07__ARM_TRACE07                        0x0134 0x03FC 0x0000 0x6 0x0
+#define MX6SLL_PAD_LCD_DATA07__SRC_BOOT_CFG07                     0x0134 0x03FC 0x0000 0x7 0x0
+#define MX6SLL_PAD_LCD_DATA08__LCD_DATA08                         0x0138 0x0400 0x06F8 0x0 0x0
+#define MX6SLL_PAD_LCD_DATA08__KEY_COL0                           0x0138 0x0400 0x06A0 0x1 0x1
+#define MX6SLL_PAD_LCD_DATA08__CSI_DATA09                         0x0138 0x0400 0x05EC 0x2 0x0
+#define MX6SLL_PAD_LCD_DATA08__ECSPI2_SCLK                        0x0138 0x0400 0x061C 0x4 0x0
+#define MX6SLL_PAD_LCD_DATA08__GPIO2_IO28                         0x0138 0x0400 0x0000 0x5 0x0
+#define MX6SLL_PAD_LCD_DATA08__ARM_TRACE08                        0x0138 0x0400 0x0000 0x6 0x0
+#define MX6SLL_PAD_LCD_DATA08__SRC_BOOT_CFG08                     0x0138 0x0400 0x0000 0x7 0x0
+#define MX6SLL_PAD_LCD_DATA09__LCD_DATA09                         0x013C 0x0404 0x06FC 0x0 0x0
+#define MX6SLL_PAD_LCD_DATA09__KEY_ROW0                           0x013C 0x0404 0x06C0 0x1 0x1
+#define MX6SLL_PAD_LCD_DATA09__CSI_DATA08                         0x013C 0x0404 0x05E8 0x2 0x0
+#define MX6SLL_PAD_LCD_DATA09__ECSPI2_MOSI                        0x013C 0x0404 0x0624 0x4 0x0
+#define MX6SLL_PAD_LCD_DATA09__GPIO2_IO29                         0x013C 0x0404 0x0000 0x5 0x0
+#define MX6SLL_PAD_LCD_DATA09__ARM_TRACE09                        0x013C 0x0404 0x0000 0x6 0x0
+#define MX6SLL_PAD_LCD_DATA09__SRC_BOOT_CFG09                     0x013C 0x0404 0x0000 0x7 0x0
+#define MX6SLL_PAD_LCD_DATA10__LCD_DATA10                         0x0140 0x0408 0x0700 0x0 0x1
+#define MX6SLL_PAD_LCD_DATA10__KEY_COL1                           0x0140 0x0408 0x06A4 0x1 0x1
+#define MX6SLL_PAD_LCD_DATA10__CSI_DATA07                         0x0140 0x0408 0x05E4 0x2 0x0
+#define MX6SLL_PAD_LCD_DATA10__ECSPI2_MISO                        0x0140 0x0408 0x0620 0x4 0x0
+#define MX6SLL_PAD_LCD_DATA10__GPIO2_IO30                         0x0140 0x0408 0x0000 0x5 0x0
+#define MX6SLL_PAD_LCD_DATA10__ARM_TRACE10                        0x0140 0x0408 0x0000 0x6 0x0
+#define MX6SLL_PAD_LCD_DATA10__SRC_BOOT_CFG10                     0x0140 0x0408 0x0000 0x7 0x0
+#define MX6SLL_PAD_LCD_DATA11__LCD_DATA11                         0x0144 0x040C 0x0704 0x0 0x0
+#define MX6SLL_PAD_LCD_DATA11__KEY_ROW1                           0x0144 0x040C 0x06C4 0x1 0x1
+#define MX6SLL_PAD_LCD_DATA11__CSI_DATA06                         0x0144 0x040C 0x05E0 0x2 0x0
+#define MX6SLL_PAD_LCD_DATA11__ECSPI2_SS1                         0x0144 0x040C 0x062C 0x4 0x0
+#define MX6SLL_PAD_LCD_DATA11__GPIO2_IO31                         0x0144 0x040C 0x0000 0x5 0x0
+#define MX6SLL_PAD_LCD_DATA11__ARM_TRACE11                        0x0144 0x040C 0x0000 0x6 0x0
+#define MX6SLL_PAD_LCD_DATA11__SRC_BOOT_CFG11                     0x0144 0x040C 0x0000 0x7 0x0
+#define MX6SLL_PAD_LCD_DATA12__LCD_DATA12                         0x0148 0x0410 0x0708 0x0 0x0
+#define MX6SLL_PAD_LCD_DATA12__KEY_COL2                           0x0148 0x0410 0x06A8 0x1 0x1
+#define MX6SLL_PAD_LCD_DATA12__CSI_DATA05                         0x0148 0x0410 0x05DC 0x2 0x0
+#define MX6SLL_PAD_LCD_DATA12__UART5_DCE_RTS                      0x0148 0x0410 0x0760 0x4 0x0
+#define MX6SLL_PAD_LCD_DATA12__UART5_DTE_CTS                      0x0148 0x0410 0x0000 0x4 0x0
+#define MX6SLL_PAD_LCD_DATA12__GPIO3_IO00                         0x0148 0x0410 0x0000 0x5 0x0
+#define MX6SLL_PAD_LCD_DATA12__ARM_TRACE12                        0x0148 0x0410 0x0000 0x6 0x0
+#define MX6SLL_PAD_LCD_DATA12__SRC_BOOT_CFG12                     0x0148 0x0410 0x0000 0x7 0x0
+#define MX6SLL_PAD_LCD_DATA13__LCD_DATA13                         0x014C 0x0414 0x070C 0x0 0x0
+#define MX6SLL_PAD_LCD_DATA13__KEY_ROW2                           0x014C 0x0414 0x06C8 0x1 0x1
+#define MX6SLL_PAD_LCD_DATA13__CSI_DATA04                         0x014C 0x0414 0x05D8 0x2 0x0
+#define MX6SLL_PAD_LCD_DATA13__UART5_DCE_CTS                      0x014C 0x0414 0x0000 0x4 0x0
+#define MX6SLL_PAD_LCD_DATA13__UART5_DTE_RTS                      0x014C 0x0414 0x0760 0x4 0x1
+#define MX6SLL_PAD_LCD_DATA13__GPIO3_IO01                         0x014C 0x0414 0x0000 0x5 0x0
+#define MX6SLL_PAD_LCD_DATA13__ARM_TRACE13                        0x014C 0x0414 0x0000 0x6 0x0
+#define MX6SLL_PAD_LCD_DATA13__SRC_BOOT_CFG13                     0x014C 0x0414 0x0000 0x7 0x0
+#define MX6SLL_PAD_LCD_DATA14__LCD_DATA14                         0x0150 0x0418 0x0710 0x0 0x0
+#define MX6SLL_PAD_LCD_DATA14__KEY_COL3                           0x0150 0x0418 0x06AC 0x1 0x1
+#define MX6SLL_PAD_LCD_DATA14__CSI_DATA03                         0x0150 0x0418 0x05D4 0x2 0x0
+#define MX6SLL_PAD_LCD_DATA14__UART5_DCE_RX                       0x0150 0x0418 0x0764 0x4 0x0
+#define MX6SLL_PAD_LCD_DATA14__UART5_DTE_TX                       0x0150 0x0418 0x0000 0x4 0x0
+#define MX6SLL_PAD_LCD_DATA14__GPIO3_IO02                         0x0150 0x0418 0x0000 0x5 0x0
+#define MX6SLL_PAD_LCD_DATA14__ARM_TRACE14                        0x0150 0x0418 0x0000 0x6 0x0
+#define MX6SLL_PAD_LCD_DATA14__SRC_BOOT_CFG14                     0x0150 0x0418 0x0000 0x7 0x0
+#define MX6SLL_PAD_LCD_DATA15__LCD_DATA15                         0x0154 0x041C 0x0714 0x0 0x0
+#define MX6SLL_PAD_LCD_DATA15__KEY_ROW3                           0x0154 0x041C 0x06CC 0x1 0x0
+#define MX6SLL_PAD_LCD_DATA15__CSI_DATA02                         0x0154 0x041C 0x05D0 0x2 0x0
+#define MX6SLL_PAD_LCD_DATA15__UART5_DCE_TX                       0x0154 0x041C 0x0000 0x4 0x0
+#define MX6SLL_PAD_LCD_DATA15__UART5_DTE_RX                       0x0154 0x041C 0x0764 0x4 0x1
+#define MX6SLL_PAD_LCD_DATA15__GPIO3_IO03                         0x0154 0x041C 0x0000 0x5 0x0
+#define MX6SLL_PAD_LCD_DATA15__ARM_TRACE15                        0x0154 0x041C 0x0000 0x6 0x0
+#define MX6SLL_PAD_LCD_DATA15__SRC_BOOT_CFG15                     0x0154 0x041C 0x0000 0x7 0x0
+#define MX6SLL_PAD_LCD_DATA16__LCD_DATA16                         0x0158 0x0420 0x0718 0x0 0x0
+#define MX6SLL_PAD_LCD_DATA16__KEY_COL4                           0x0158 0x0420 0x06B0 0x1 0x0
+#define MX6SLL_PAD_LCD_DATA16__CSI_DATA01                         0x0158 0x0420 0x05CC 0x2 0x0
+#define MX6SLL_PAD_LCD_DATA16__I2C2_SCL                           0x0158 0x0420 0x0684 0x4 0x1
+#define MX6SLL_PAD_LCD_DATA16__GPIO3_IO04                         0x0158 0x0420 0x0000 0x5 0x0
+#define MX6SLL_PAD_LCD_DATA16__SRC_BOOT_CFG24                     0x0158 0x0420 0x0000 0x7 0x0
+#define MX6SLL_PAD_LCD_DATA17__LCD_DATA17                         0x015C 0x0424 0x071C 0x0 0x0
+#define MX6SLL_PAD_LCD_DATA17__KEY_ROW4                           0x015C 0x0424 0x06D0 0x1 0x0
+#define MX6SLL_PAD_LCD_DATA17__CSI_DATA00                         0x015C 0x0424 0x05C8 0x2 0x0
+#define MX6SLL_PAD_LCD_DATA17__I2C2_SDA                           0x015C 0x0424 0x0688 0x4 0x1
+#define MX6SLL_PAD_LCD_DATA17__GPIO3_IO05                         0x015C 0x0424 0x0000 0x5 0x0
+#define MX6SLL_PAD_LCD_DATA17__SRC_BOOT_CFG25                     0x015C 0x0424 0x0000 0x7 0x0
+#define MX6SLL_PAD_LCD_DATA18__LCD_DATA18                         0x0160 0x0428 0x0720 0x0 0x0
+#define MX6SLL_PAD_LCD_DATA18__KEY_COL5                           0x0160 0x0428 0x0694 0x1 0x2
+#define MX6SLL_PAD_LCD_DATA18__CSI_DATA15                         0x0160 0x0428 0x05C4 0x2 0x1
+#define MX6SLL_PAD_LCD_DATA18__GPT_CAPTURE1                       0x0160 0x0428 0x0670 0x4 0x1
+#define MX6SLL_PAD_LCD_DATA18__GPIO3_IO06                         0x0160 0x0428 0x0000 0x5 0x0
+#define MX6SLL_PAD_LCD_DATA18__SRC_BOOT_CFG26                     0x0160 0x0428 0x0000 0x7 0x0
+#define MX6SLL_PAD_LCD_DATA19__LCD_DATA19                         0x0164 0x042C 0x0724 0x0 0x0
+#define MX6SLL_PAD_LCD_DATA19__KEY_ROW5                           0x0164 0x042C 0x06B4 0x1 0x1
+#define MX6SLL_PAD_LCD_DATA19__CSI_DATA14                         0x0164 0x042C 0x05C0 0x2 0x2
+#define MX6SLL_PAD_LCD_DATA19__GPT_CAPTURE2                       0x0164 0x042C 0x0674 0x4 0x1
+#define MX6SLL_PAD_LCD_DATA19__GPIO3_IO07                         0x0164 0x042C 0x0000 0x5 0x0
+#define MX6SLL_PAD_LCD_DATA19__SRC_BOOT_CFG27                     0x0164 0x042C 0x0000 0x7 0x0
+#define MX6SLL_PAD_LCD_DATA20__LCD_DATA20                         0x0168 0x0430 0x0728 0x0 0x0
+#define MX6SLL_PAD_LCD_DATA20__KEY_COL6                           0x0168 0x0430 0x0698 0x1 0x1
+#define MX6SLL_PAD_LCD_DATA20__CSI_DATA13                         0x0168 0x0430 0x05BC 0x2 0x2
+#define MX6SLL_PAD_LCD_DATA20__GPT_COMPARE1                       0x0168 0x0430 0x0000 0x4 0x0
+#define MX6SLL_PAD_LCD_DATA20__GPIO3_IO08                         0x0168 0x0430 0x0000 0x5 0x0
+#define MX6SLL_PAD_LCD_DATA20__SRC_BOOT_CFG28                     0x0168 0x0430 0x0000 0x7 0x0
+#define MX6SLL_PAD_LCD_DATA21__LCD_DATA21                         0x016C 0x0434 0x072C 0x0 0x0
+#define MX6SLL_PAD_LCD_DATA21__KEY_ROW6                           0x016C 0x0434 0x06B8 0x1 0x1
+#define MX6SLL_PAD_LCD_DATA21__CSI_DATA12                         0x016C 0x0434 0x05B8 0x2 0x2
+#define MX6SLL_PAD_LCD_DATA21__GPT_COMPARE2                       0x016C 0x0434 0x0000 0x4 0x0
+#define MX6SLL_PAD_LCD_DATA21__GPIO3_IO09                         0x016C 0x0434 0x0000 0x5 0x0
+#define MX6SLL_PAD_LCD_DATA21__SRC_BOOT_CFG29                     0x016C 0x0434 0x0000 0x7 0x0
+#define MX6SLL_PAD_LCD_DATA22__LCD_DATA22                         0x0170 0x0438 0x0730 0x0 0x0
+#define MX6SLL_PAD_LCD_DATA22__KEY_COL7                           0x0170 0x0438 0x069C 0x1 0x1
+#define MX6SLL_PAD_LCD_DATA22__CSI_DATA11                         0x0170 0x0438 0x05B4 0x2 0x1
+#define MX6SLL_PAD_LCD_DATA22__GPT_COMPARE3                       0x0170 0x0438 0x0000 0x4 0x0
+#define MX6SLL_PAD_LCD_DATA22__GPIO3_IO10                         0x0170 0x0438 0x0000 0x5 0x0
+#define MX6SLL_PAD_LCD_DATA22__SRC_BOOT_CFG30                     0x0170 0x0438 0x0000 0x7 0x0
+#define MX6SLL_PAD_LCD_DATA23__LCD_DATA23                         0x0174 0x043C 0x0734 0x0 0x0
+#define MX6SLL_PAD_LCD_DATA23__KEY_ROW7                           0x0174 0x043C 0x06BC 0x1 0x1
+#define MX6SLL_PAD_LCD_DATA23__CSI_DATA10                         0x0174 0x043C 0x05B0 0x2 0x1
+#define MX6SLL_PAD_LCD_DATA23__GPT_CLKIN                          0x0174 0x043C 0x0678 0x4 0x1
+#define MX6SLL_PAD_LCD_DATA23__GPIO3_IO11                         0x0174 0x043C 0x0000 0x5 0x0
+#define MX6SLL_PAD_LCD_DATA23__SRC_BOOT_CFG31                     0x0174 0x043C 0x0000 0x7 0x0
+#define MX6SLL_PAD_AUD_RXFS__AUD3_RXFS                            0x0178 0x0440 0x0000 0x0 0x0
+#define MX6SLL_PAD_AUD_RXFS__I2C1_SCL                             0x0178 0x0440 0x067C 0x1 0x1
+#define MX6SLL_PAD_AUD_RXFS__UART3_DCE_RX                         0x0178 0x0440 0x0754 0x2 0x0
+#define MX6SLL_PAD_AUD_RXFS__UART3_DTE_TX                         0x0178 0x0440 0x0000 0x2 0x0
+#define MX6SLL_PAD_AUD_RXFS__I2C3_SCL                             0x0178 0x0440 0x068C 0x4 0x1
+#define MX6SLL_PAD_AUD_RXFS__GPIO1_IO00                           0x0178 0x0440 0x0000 0x5 0x0
+#define MX6SLL_PAD_AUD_RXFS__ECSPI3_SS0                           0x0178 0x0440 0x0648 0x6 0x0
+#define MX6SLL_PAD_AUD_RXFS__MBIST_BEND                           0x0178 0x0440 0x0000 0x7 0x0
+#define MX6SLL_PAD_AUD_RXC__AUD3_RXC                              0x017C 0x0444 0x0000 0x0 0x0
+#define MX6SLL_PAD_AUD_RXC__I2C1_SDA                              0x017C 0x0444 0x0680 0x1 0x1
+#define MX6SLL_PAD_AUD_RXC__UART3_DCE_TX                          0x017C 0x0444 0x0000 0x2 0x0
+#define MX6SLL_PAD_AUD_RXC__UART3_DTE_RX                          0x017C 0x0444 0x0754 0x2 0x1
+#define MX6SLL_PAD_AUD_RXC__I2C3_SDA                              0x017C 0x0444 0x0690 0x4 0x1
+#define MX6SLL_PAD_AUD_RXC__GPIO1_IO01                            0x017C 0x0444 0x0000 0x5 0x0
+#define MX6SLL_PAD_AUD_RXC__ECSPI3_SS1                            0x017C 0x0444 0x064C 0x6 0x0
+#define MX6SLL_PAD_AUD_RXD__AUD3_RXD                              0x0180 0x0448 0x0000 0x0 0x0
+#define MX6SLL_PAD_AUD_RXD__ECSPI3_MOSI                           0x0180 0x0448 0x063C 0x1 0x0
+#define MX6SLL_PAD_AUD_RXD__UART4_DCE_RX                          0x0180 0x0448 0x075C 0x2 0x0
+#define MX6SLL_PAD_AUD_RXD__UART4_DTE_TX                          0x0180 0x0448 0x0000 0x2 0x0
+#define MX6SLL_PAD_AUD_RXD__SD1_LCTL                              0x0180 0x0448 0x0000 0x4 0x0
+#define MX6SLL_PAD_AUD_RXD__GPIO1_IO02                            0x0180 0x0448 0x0000 0x5 0x0
+#define MX6SLL_PAD_AUD_TXC__AUD3_TXC                              0x0184 0x044C 0x0000 0x0 0x0
+#define MX6SLL_PAD_AUD_TXC__ECSPI3_MISO                           0x0184 0x044C 0x0638 0x1 0x0
+#define MX6SLL_PAD_AUD_TXC__UART4_DCE_TX                          0x0184 0x044C 0x0000 0x2 0x0
+#define MX6SLL_PAD_AUD_TXC__UART4_DTE_RX                          0x0184 0x044C 0x075C 0x2 0x1
+#define MX6SLL_PAD_AUD_TXC__SD2_LCTL                              0x0184 0x044C 0x0000 0x4 0x0
+#define MX6SLL_PAD_AUD_TXC__GPIO1_IO03                            0x0184 0x044C 0x0000 0x5 0x0
+#define MX6SLL_PAD_AUD_TXFS__AUD3_TXFS                            0x0188 0x0450 0x0000 0x0 0x0
+#define MX6SLL_PAD_AUD_TXFS__PWM3_OUT                             0x0188 0x0450 0x0000 0x1 0x0
+#define MX6SLL_PAD_AUD_TXFS__UART4_DCE_RTS                        0x0188 0x0450 0x0758 0x2 0x0
+#define MX6SLL_PAD_AUD_TXFS__UART4_DTE_CTS                        0x0188 0x0450 0x0000 0x2 0x0
+#define MX6SLL_PAD_AUD_TXFS__SD3_LCTL                             0x0188 0x0450 0x0000 0x4 0x0
+#define MX6SLL_PAD_AUD_TXFS__GPIO1_IO04                           0x0188 0x0450 0x0000 0x5 0x0
+#define MX6SLL_PAD_AUD_TXD__AUD3_TXD                              0x018C 0x0454 0x0000 0x0 0x0
+#define MX6SLL_PAD_AUD_TXD__ECSPI3_SCLK                           0x018C 0x0454 0x0630 0x1 0x0
+#define MX6SLL_PAD_AUD_TXD__UART4_DCE_CTS                         0x018C 0x0454 0x0000 0x2 0x0
+#define MX6SLL_PAD_AUD_TXD__UART4_DTE_RTS                         0x018C 0x0454 0x0758 0x2 0x1
+#define MX6SLL_PAD_AUD_TXD__GPIO1_IO05                            0x018C 0x0454 0x0000 0x5 0x0
+#define MX6SLL_PAD_AUD_MCLK__AUDIO_CLK_OUT                        0x0190 0x0458 0x0000 0x0 0x0
+#define MX6SLL_PAD_AUD_MCLK__PWM4_OUT                             0x0190 0x0458 0x0000 0x1 0x0
+#define MX6SLL_PAD_AUD_MCLK__ECSPI3_RDY                           0x0190 0x0458 0x0634 0x2 0x0
+#define MX6SLL_PAD_AUD_MCLK__WDOG2_RESET_B_DEB                    0x0190 0x0458 0x0000 0x4 0x0
+#define MX6SLL_PAD_AUD_MCLK__GPIO1_IO06                           0x0190 0x0458 0x0000 0x5 0x0
+#define MX6SLL_PAD_AUD_MCLK__SPDIF_EXT_CLK                        0x0190 0x0458 0x073C 0x6 0x1
+#define MX6SLL_PAD_UART1_RXD__UART1_DCE_RX                        0x0194 0x045C 0x0744 0x0 0x0
+#define MX6SLL_PAD_UART1_RXD__UART1_DTE_TX                        0x0194 0x045C 0x0000 0x0 0x0
+#define MX6SLL_PAD_UART1_RXD__PWM1_OUT                            0x0194 0x045C 0x0000 0x1 0x0
+#define MX6SLL_PAD_UART1_RXD__UART4_DCE_RX                        0x0194 0x045C 0x075C 0x2 0x4
+#define MX6SLL_PAD_UART1_RXD__UART4_DTE_TX                        0x0194 0x045C 0x0000 0x2 0x0
+#define MX6SLL_PAD_UART1_RXD__UART5_DCE_RX                        0x0194 0x045C 0x0764 0x4 0x6
+#define MX6SLL_PAD_UART1_RXD__UART5_DTE_TX                        0x0194 0x045C 0x0000 0x4 0x0
+#define MX6SLL_PAD_UART1_RXD__GPIO3_IO16                          0x0194 0x045C 0x0000 0x5 0x0
+#define MX6SLL_PAD_UART1_TXD__UART1_DCE_TX                        0x0198 0x0460 0x0000 0x0 0x0
+#define MX6SLL_PAD_UART1_TXD__UART1_DTE_RX                        0x0198 0x0460 0x0744 0x0 0x1
+#define MX6SLL_PAD_UART1_TXD__PWM2_OUT                            0x0198 0x0460 0x0000 0x1 0x0
+#define MX6SLL_PAD_UART1_TXD__UART4_DCE_TX                        0x0198 0x0460 0x0000 0x2 0x0
+#define MX6SLL_PAD_UART1_TXD__UART4_DTE_RX                        0x0198 0x0460 0x075C 0x2 0x5
+#define MX6SLL_PAD_UART1_TXD__UART5_DCE_TX                        0x0198 0x0460 0x0000 0x4 0x0
+#define MX6SLL_PAD_UART1_TXD__UART5_DTE_RX                        0x0198 0x0460 0x0764 0x4 0x7
+#define MX6SLL_PAD_UART1_TXD__GPIO3_IO17                          0x0198 0x0460 0x0000 0x5 0x0
+#define MX6SLL_PAD_UART1_TXD__UART5_DCD_B                         0x0198 0x0460 0x0000 0x7 0x0
+#define MX6SLL_PAD_I2C1_SCL__I2C1_SCL                             0x019C 0x0464 0x067C 0x0 0x0
+#define MX6SLL_PAD_I2C1_SCL__UART1_DCE_RTS                        0x019C 0x0464 0x0740 0x1 0x0
+#define MX6SLL_PAD_I2C1_SCL__UART1_DTE_CTS                        0x019C 0x0464 0x0000 0x1 0x0
+#define MX6SLL_PAD_I2C1_SCL__ECSPI3_SS2                           0x019C 0x0464 0x0640 0x2 0x0
+#define MX6SLL_PAD_I2C1_SCL__SD3_RESET                            0x019C 0x0464 0x0000 0x4 0x0
+#define MX6SLL_PAD_I2C1_SCL__GPIO3_IO12                           0x019C 0x0464 0x0000 0x5 0x0
+#define MX6SLL_PAD_I2C1_SCL__ECSPI1_SS1                           0x019C 0x0464 0x060C 0x6 0x0
+#define MX6SLL_PAD_I2C1_SDA__I2C1_SDA                             0x01A0 0x0468 0x0680 0x0 0x0
+#define MX6SLL_PAD_I2C1_SDA__UART1_DCE_CTS                        0x01A0 0x0468 0x0000 0x1 0x0
+#define MX6SLL_PAD_I2C1_SDA__UART1_DTE_RTS                        0x01A0 0x0468 0x0740 0x1 0x1
+#define MX6SLL_PAD_I2C1_SDA__ECSPI3_SS3                           0x01A0 0x0468 0x0644 0x2 0x0
+#define MX6SLL_PAD_I2C1_SDA__SD3_VSELECT                          0x01A0 0x0468 0x0000 0x4 0x0
+#define MX6SLL_PAD_I2C1_SDA__GPIO3_IO13                           0x01A0 0x0468 0x0000 0x5 0x0
+#define MX6SLL_PAD_I2C1_SDA__ECSPI1_SS2                           0x01A0 0x0468 0x0610 0x6 0x0
+#define MX6SLL_PAD_I2C2_SCL__I2C2_SCL                             0x01A4 0x046C 0x0684 0x0 0x3
+#define MX6SLL_PAD_I2C2_SCL__AUD4_RXFS                            0x01A4 0x046C 0x0570 0x1 0x2
+#define MX6SLL_PAD_I2C2_SCL__SPDIF_IN                             0x01A4 0x046C 0x0738 0x2 0x2
+#define MX6SLL_PAD_I2C2_SCL__SD3_WP                               0x01A4 0x046C 0x0794 0x4 0x3
+#define MX6SLL_PAD_I2C2_SCL__GPIO3_IO14                           0x01A4 0x046C 0x0000 0x5 0x0
+#define MX6SLL_PAD_I2C2_SCL__ECSPI1_RDY                           0x01A4 0x046C 0x0600 0x6 0x1
+#define MX6SLL_PAD_I2C2_SDA__I2C2_SDA                             0x01A8 0x0470 0x0688 0x0 0x3
+#define MX6SLL_PAD_I2C2_SDA__AUD4_RXC                             0x01A8 0x0470 0x056C 0x1 0x2
+#define MX6SLL_PAD_I2C2_SDA__SPDIF_OUT                            0x01A8 0x0470 0x0000 0x2 0x0
+#define MX6SLL_PAD_I2C2_SDA__SD3_CD_B                             0x01A8 0x0470 0x0780 0x4 0x3
+#define MX6SLL_PAD_I2C2_SDA__GPIO3_IO15                           0x01A8 0x0470 0x0000 0x5 0x0
+#define MX6SLL_PAD_ECSPI1_SCLK__ECSPI1_SCLK                       0x01AC 0x0474 0x05FC 0x0 0x1
+#define MX6SLL_PAD_ECSPI1_SCLK__AUD4_TXD                          0x01AC 0x0474 0x0568 0x1 0x1
+#define MX6SLL_PAD_ECSPI1_SCLK__UART5_DCE_RX                      0x01AC 0x0474 0x0764 0x2 0x2
+#define MX6SLL_PAD_ECSPI1_SCLK__UART5_DTE_TX                      0x01AC 0x0474 0x0000 0x2 0x0
+#define MX6SLL_PAD_ECSPI1_SCLK__EPDC_VCOM0                        0x01AC 0x0474 0x0000 0x3 0x0
+#define MX6SLL_PAD_ECSPI1_SCLK__SD2_RESET                         0x01AC 0x0474 0x0000 0x4 0x0
+#define MX6SLL_PAD_ECSPI1_SCLK__GPIO4_IO08                        0x01AC 0x0474 0x0000 0x5 0x0
+#define MX6SLL_PAD_ECSPI1_SCLK__USB_OTG2_OC                       0x01AC 0x0474 0x0768 0x6 0x1
+#define MX6SLL_PAD_ECSPI1_MOSI__ECSPI1_MOSI                       0x01B0 0x0478 0x0608 0x0 0x1
+#define MX6SLL_PAD_ECSPI1_MOSI__AUD4_TXC                          0x01B0 0x0478 0x0574 0x1 0x1
+#define MX6SLL_PAD_ECSPI1_MOSI__UART5_DCE_TX                      0x01B0 0x0478 0x0000 0x2 0x0
+#define MX6SLL_PAD_ECSPI1_MOSI__UART5_DTE_RX                      0x01B0 0x0478 0x0764 0x2 0x3
+#define MX6SLL_PAD_ECSPI1_MOSI__EPDC_VCOM1                        0x01B0 0x0478 0x0000 0x3 0x0
+#define MX6SLL_PAD_ECSPI1_MOSI__SD2_VSELECT                       0x01B0 0x0478 0x0000 0x4 0x0
+#define MX6SLL_PAD_ECSPI1_MOSI__GPIO4_IO09                        0x01B0 0x0478 0x0000 0x5 0x0
+#define MX6SLL_PAD_ECSPI1_MISO__ECSPI1_MISO                       0x01B4 0x047C 0x0604 0x0 0x1
+#define MX6SLL_PAD_ECSPI1_MISO__AUD4_TXFS                         0x01B4 0x047C 0x0578 0x1 0x1
+#define MX6SLL_PAD_ECSPI1_MISO__UART5_DCE_RTS                     0x01B4 0x047C 0x0760 0x2 0x2
+#define MX6SLL_PAD_ECSPI1_MISO__UART5_DTE_CTS                     0x01B4 0x047C 0x0000 0x2 0x0
+#define MX6SLL_PAD_ECSPI1_MISO__EPDC_BDR0                         0x01B4 0x047C 0x0000 0x3 0x0
+#define MX6SLL_PAD_ECSPI1_MISO__SD2_WP                            0x01B4 0x047C 0x077C 0x4 0x0
+#define MX6SLL_PAD_ECSPI1_MISO__GPIO4_IO10                        0x01B4 0x047C 0x0000 0x5 0x0
+#define MX6SLL_PAD_ECSPI1_SS0__ECSPI1_SS0                         0x01B8 0x0480 0x0614 0x0 0x1
+#define MX6SLL_PAD_ECSPI1_SS0__AUD4_RXD                           0x01B8 0x0480 0x0564 0x1 0x1
+#define MX6SLL_PAD_ECSPI1_SS0__UART5_DCE_CTS                      0x01B8 0x0480 0x0000 0x2 0x0
+#define MX6SLL_PAD_ECSPI1_SS0__UART5_DTE_RTS                      0x01B8 0x0480 0x0760 0x2 0x3
+#define MX6SLL_PAD_ECSPI1_SS0__EPDC_BDR1                          0x01B8 0x0480 0x0000 0x3 0x0
+#define MX6SLL_PAD_ECSPI1_SS0__SD2_CD_B                           0x01B8 0x0480 0x0778 0x4 0x0
+#define MX6SLL_PAD_ECSPI1_SS0__GPIO4_IO11                         0x01B8 0x0480 0x0000 0x5 0x0
+#define MX6SLL_PAD_ECSPI1_SS0__USB_OTG2_PWR                       0x01B8 0x0480 0x0000 0x6 0x0
+#define MX6SLL_PAD_ECSPI2_SCLK__ECSPI2_SCLK                       0x01BC 0x0484 0x061C 0x0 0x1
+#define MX6SLL_PAD_ECSPI2_SCLK__SPDIF_EXT_CLK                     0x01BC 0x0484 0x073C 0x1 0x2
+#define MX6SLL_PAD_ECSPI2_SCLK__UART3_DCE_RX                      0x01BC 0x0484 0x0754 0x2 0x2
+#define MX6SLL_PAD_ECSPI2_SCLK__UART3_DTE_TX                      0x01BC 0x0484 0x0000 0x2 0x0
+#define MX6SLL_PAD_ECSPI2_SCLK__CSI_PIXCLK                        0x01BC 0x0484 0x05F4 0x3 0x1
+#define MX6SLL_PAD_ECSPI2_SCLK__SD1_RESET                         0x01BC 0x0484 0x0000 0x4 0x0
+#define MX6SLL_PAD_ECSPI2_SCLK__GPIO4_IO12                        0x01BC 0x0484 0x0000 0x5 0x0
+#define MX6SLL_PAD_ECSPI2_SCLK__USB_OTG2_OC                       0x01BC 0x0484 0x0768 0x6 0x2
+#define MX6SLL_PAD_ECSPI2_MOSI__ECSPI2_MOSI                       0x01C0 0x0488 0x0624 0x0 0x1
+#define MX6SLL_PAD_ECSPI2_MOSI__SDMA_EXT_EVENT1                   0x01C0 0x0488 0x0000 0x1 0x0
+#define MX6SLL_PAD_ECSPI2_MOSI__UART3_DCE_TX                      0x01C0 0x0488 0x0000 0x2 0x0
+#define MX6SLL_PAD_ECSPI2_MOSI__UART3_DTE_RX                      0x01C0 0x0488 0x0754 0x2 0x3
+#define MX6SLL_PAD_ECSPI2_MOSI__CSI_HSYNC                         0x01C0 0x0488 0x05F0 0x3 0x1
+#define MX6SLL_PAD_ECSPI2_MOSI__SD1_VSELECT                       0x01C0 0x0488 0x0000 0x4 0x0
+#define MX6SLL_PAD_ECSPI2_MOSI__GPIO4_IO13                        0x01C0 0x0488 0x0000 0x5 0x0
+#define MX6SLL_PAD_ECSPI2_MISO__ECSPI2_MISO                       0x01C4 0x048C 0x0620 0x0 0x1
+#define MX6SLL_PAD_ECSPI2_MISO__SDMA_EXT_EVENT0                   0x01C4 0x048C 0x0000 0x1 0x0
+#define MX6SLL_PAD_ECSPI2_MISO__UART3_DCE_RTS                     0x01C4 0x048C 0x0750 0x2 0x0
+#define MX6SLL_PAD_ECSPI2_MISO__UART3_DTE_CTS                     0x01C4 0x048C 0x0000 0x2 0x0
+#define MX6SLL_PAD_ECSPI2_MISO__CSI_MCLK                          0x01C4 0x048C 0x0000 0x3 0x0
+#define MX6SLL_PAD_ECSPI2_MISO__SD1_WP                            0x01C4 0x048C 0x0774 0x4 0x2
+#define MX6SLL_PAD_ECSPI2_MISO__GPIO4_IO14                        0x01C4 0x048C 0x0000 0x5 0x0
+#define MX6SLL_PAD_ECSPI2_MISO__USB_OTG1_OC                       0x01C4 0x048C 0x076C 0x6 0x1
+#define MX6SLL_PAD_ECSPI2_SS0__ECSPI2_SS0                         0x01C8 0x0490 0x0628 0x0 0x0
+#define MX6SLL_PAD_ECSPI2_SS0__ECSPI1_SS3                         0x01C8 0x0490 0x0618 0x1 0x1
+#define MX6SLL_PAD_ECSPI2_SS0__UART3_DCE_CTS                      0x01C8 0x0490 0x0000 0x2 0x0
+#define MX6SLL_PAD_ECSPI2_SS0__UART3_DTE_RTS                      0x01C8 0x0490 0x0750 0x2 0x1
+#define MX6SLL_PAD_ECSPI2_SS0__CSI_VSYNC                          0x01C8 0x0490 0x05F8 0x3 0x1
+#define MX6SLL_PAD_ECSPI2_SS0__SD1_CD_B                           0x01C8 0x0490 0x0770 0x4 0x2
+#define MX6SLL_PAD_ECSPI2_SS0__GPIO4_IO15                         0x01C8 0x0490 0x0000 0x5 0x0
+#define MX6SLL_PAD_ECSPI2_SS0__USB_OTG1_PWR                       0x01C8 0x0490 0x0000 0x6 0x0
+#define MX6SLL_PAD_SD1_CLK__SD1_CLK                               0x01CC 0x0494 0x0000 0x0 0x0
+#define MX6SLL_PAD_SD1_CLK__KEY_COL0                              0x01CC 0x0494 0x06A0 0x2 0x2
+#define MX6SLL_PAD_SD1_CLK__EPDC_SDCE4                            0x01CC 0x0494 0x0000 0x3 0x0
+#define MX6SLL_PAD_SD1_CLK__GPIO5_IO15                            0x01CC 0x0494 0x0000 0x5 0x0
+#define MX6SLL_PAD_SD1_CMD__SD1_CMD                               0x01D0 0x0498 0x0000 0x0 0x0
+#define MX6SLL_PAD_SD1_CMD__KEY_ROW0                              0x01D0 0x0498 0x06C0 0x2 0x2
+#define MX6SLL_PAD_SD1_CMD__EPDC_SDCE5                            0x01D0 0x0498 0x0000 0x3 0x0
+#define MX6SLL_PAD_SD1_CMD__GPIO5_IO14                            0x01D0 0x0498 0x0000 0x5 0x0
+#define MX6SLL_PAD_SD1_DATA0__SD1_DATA0                           0x01D4 0x049C 0x0000 0x0 0x0
+#define MX6SLL_PAD_SD1_DATA0__KEY_COL1                            0x01D4 0x049C 0x06A4 0x2 0x2
+#define MX6SLL_PAD_SD1_DATA0__EPDC_SDCE6                          0x01D4 0x049C 0x0000 0x3 0x0
+#define MX6SLL_PAD_SD1_DATA0__GPIO5_IO11                          0x01D4 0x049C 0x0000 0x5 0x0
+#define MX6SLL_PAD_SD1_DATA1__SD1_DATA1                           0x01D8 0x04A0 0x0000 0x0 0x0
+#define MX6SLL_PAD_SD1_DATA1__KEY_ROW1                            0x01D8 0x04A0 0x06C4 0x2 0x2
+#define MX6SLL_PAD_SD1_DATA1__EPDC_SDCE7                          0x01D8 0x04A0 0x0000 0x3 0x0
+#define MX6SLL_PAD_SD1_DATA1__GPIO5_IO08                          0x01D8 0x04A0 0x0000 0x5 0x0
+#define MX6SLL_PAD_SD1_DATA2__SD1_DATA2                           0x01DC 0x04A4 0x0000 0x0 0x0
+#define MX6SLL_PAD_SD1_DATA2__KEY_COL2                            0x01DC 0x04A4 0x06A8 0x2 0x2
+#define MX6SLL_PAD_SD1_DATA2__EPDC_SDCE8                          0x01DC 0x04A4 0x0000 0x3 0x0
+#define MX6SLL_PAD_SD1_DATA2__GPIO5_IO13                          0x01DC 0x04A4 0x0000 0x5 0x0
+#define MX6SLL_PAD_SD1_DATA3__SD1_DATA3                           0x01E0 0x04A8 0x0000 0x0 0x0
+#define MX6SLL_PAD_SD1_DATA3__KEY_ROW2                            0x01E0 0x04A8 0x06C8 0x2 0x2
+#define MX6SLL_PAD_SD1_DATA3__EPDC_SDCE9                          0x01E0 0x04A8 0x0000 0x3 0x0
+#define MX6SLL_PAD_SD1_DATA3__GPIO5_IO06                          0x01E0 0x04A8 0x0000 0x5 0x0
+#define MX6SLL_PAD_SD1_DATA4__SD1_DATA4                           0x01E4 0x04AC 0x0000 0x0 0x0
+#define MX6SLL_PAD_SD1_DATA4__KEY_COL3                            0x01E4 0x04AC 0x06AC 0x2 0x2
+#define MX6SLL_PAD_SD1_DATA4__EPDC_SDCLK_N                        0x01E4 0x04AC 0x0000 0x3 0x0
+#define MX6SLL_PAD_SD1_DATA4__UART4_DCE_RX                        0x01E4 0x04AC 0x075C 0x4 0x6
+#define MX6SLL_PAD_SD1_DATA4__UART4_DTE_TX                        0x01E4 0x04AC 0x0000 0x4 0x0
+#define MX6SLL_PAD_SD1_DATA4__GPIO5_IO12                          0x01E4 0x04AC 0x0000 0x5 0x0
+#define MX6SLL_PAD_SD1_DATA5__SD1_DATA5                           0x01E8 0x04B0 0x0000 0x0 0x0
+#define MX6SLL_PAD_SD1_DATA5__KEY_ROW3                            0x01E8 0x04B0 0x06CC 0x2 0x2
+#define MX6SLL_PAD_SD1_DATA5__EPDC_SDOED                          0x01E8 0x04B0 0x0000 0x3 0x0
+#define MX6SLL_PAD_SD1_DATA5__UART4_DCE_TX                        0x01E8 0x04B0 0x0000 0x4 0x0
+#define MX6SLL_PAD_SD1_DATA5__UART4_DTE_RX                        0x01E8 0x04B0 0x075C 0x4 0x7
+#define MX6SLL_PAD_SD1_DATA5__GPIO5_IO09                          0x01E8 0x04B0 0x0000 0x5 0x0
+#define MX6SLL_PAD_SD1_DATA6__SD1_DATA6                           0x01EC 0x04B4 0x0000 0x0 0x0
+#define MX6SLL_PAD_SD1_DATA6__KEY_COL4                            0x01EC 0x04B4 0x06B0 0x2 0x2
+#define MX6SLL_PAD_SD1_DATA6__EPDC_SDOEZ                          0x01EC 0x04B4 0x0000 0x3 0x0
+#define MX6SLL_PAD_SD1_DATA6__UART4_DCE_RTS                       0x01EC 0x04B4 0x0758 0x4 0x4
+#define MX6SLL_PAD_SD1_DATA6__UART4_DTE_CTS                       0x01EC 0x04B4 0x0000 0x4 0x0
+#define MX6SLL_PAD_SD1_DATA6__GPIO5_IO07                          0x01EC 0x04B4 0x0000 0x5 0x0
+#define MX6SLL_PAD_SD1_DATA7__SD1_DATA7                           0x01F0 0x04B8 0x0000 0x0 0x0
+#define MX6SLL_PAD_SD1_DATA7__KEY_ROW4                            0x01F0 0x04B8 0x06D0 0x2 0x2
+#define MX6SLL_PAD_SD1_DATA7__CCM_PMIC_READY                      0x01F0 0x04B8 0x05AC 0x3 0x3
+#define MX6SLL_PAD_SD1_DATA7__UART4_DCE_CTS                       0x01F0 0x04B8 0x0000 0x4 0x0
+#define MX6SLL_PAD_SD1_DATA7__UART4_DTE_RTS                       0x01F0 0x04B8 0x0758 0x4 0x5
+#define MX6SLL_PAD_SD1_DATA7__GPIO5_IO10                          0x01F0 0x04B8 0x0000 0x5 0x0
+#define MX6SLL_PAD_SD2_RESET__SD2_RESET                           0x01F4 0x04BC 0x0000 0x0 0x0
+#define MX6SLL_PAD_SD2_RESET__WDOG2_B                             0x01F4 0x04BC 0x0000 0x2 0x0
+#define MX6SLL_PAD_SD2_RESET__SPDIF_OUT                           0x01F4 0x04BC 0x0000 0x3 0x0
+#define MX6SLL_PAD_SD2_RESET__CSI_MCLK                            0x01F4 0x04BC 0x0000 0x4 0x0
+#define MX6SLL_PAD_SD2_RESET__GPIO4_IO27                          0x01F4 0x04BC 0x0000 0x5 0x0
+#define MX6SLL_PAD_SD2_CLK__SD2_CLK                               0x01F8 0x04C0 0x0000 0x0 0x0
+#define MX6SLL_PAD_SD2_CLK__AUD4_RXFS                             0x01F8 0x04C0 0x0570 0x1 0x1
+#define MX6SLL_PAD_SD2_CLK__ECSPI3_SCLK                           0x01F8 0x04C0 0x0630 0x2 0x1
+#define MX6SLL_PAD_SD2_CLK__CSI_DATA00                            0x01F8 0x04C0 0x05C8 0x3 0x1
+#define MX6SLL_PAD_SD2_CLK__GPIO5_IO05                            0x01F8 0x04C0 0x0000 0x5 0x0
+#define MX6SLL_PAD_SD2_CMD__SD2_CMD                               0x01FC 0x04C4 0x0000 0x0 0x0
+#define MX6SLL_PAD_SD2_CMD__AUD4_RXC                              0x01FC 0x04C4 0x056C 0x1 0x1
+#define MX6SLL_PAD_SD2_CMD__ECSPI3_SS0                            0x01FC 0x04C4 0x0648 0x2 0x1
+#define MX6SLL_PAD_SD2_CMD__CSI_DATA01                            0x01FC 0x04C4 0x05CC 0x3 0x1
+#define MX6SLL_PAD_SD2_CMD__EPIT1_OUT                             0x01FC 0x04C4 0x0000 0x4 0x0
+#define MX6SLL_PAD_SD2_CMD__GPIO5_IO04                            0x01FC 0x04C4 0x0000 0x5 0x0
+#define MX6SLL_PAD_SD2_DATA0__SD2_DATA0                           0x0200 0x04C8 0x0000 0x0 0x0
+#define MX6SLL_PAD_SD2_DATA0__AUD4_RXD                            0x0200 0x04C8 0x0564 0x1 0x2
+#define MX6SLL_PAD_SD2_DATA0__ECSPI3_MOSI                         0x0200 0x04C8 0x063C 0x2 0x1
+#define MX6SLL_PAD_SD2_DATA0__CSI_DATA02                          0x0200 0x04C8 0x05D0 0x3 0x1
+#define MX6SLL_PAD_SD2_DATA0__UART5_DCE_RTS                       0x0200 0x04C8 0x0760 0x4 0x4
+#define MX6SLL_PAD_SD2_DATA0__UART5_DTE_CTS                       0x0200 0x04C8 0x0000 0x4 0x0
+#define MX6SLL_PAD_SD2_DATA0__GPIO5_IO01                          0x0200 0x04C8 0x0000 0x5 0x0
+#define MX6SLL_PAD_SD2_DATA1__SD2_DATA1                           0x0204 0x04CC 0x0000 0x0 0x0
+#define MX6SLL_PAD_SD2_DATA1__AUD4_TXC                            0x0204 0x04CC 0x0574 0x1 0x2
+#define MX6SLL_PAD_SD2_DATA1__ECSPI3_MISO                         0x0204 0x04CC 0x0638 0x2 0x1
+#define MX6SLL_PAD_SD2_DATA1__CSI_DATA03                          0x0204 0x04CC 0x05D4 0x3 0x1
+#define MX6SLL_PAD_SD2_DATA1__UART5_DCE_CTS                       0x0204 0x04CC 0x0000 0x4 0x0
+#define MX6SLL_PAD_SD2_DATA1__UART5_DTE_RTS                       0x0204 0x04CC 0x0760 0x4 0x5
+#define MX6SLL_PAD_SD2_DATA1__GPIO4_IO30                          0x0204 0x04CC 0x0000 0x5 0x0
+#define MX6SLL_PAD_SD2_DATA2__SD2_DATA2                           0x0208 0x04D0 0x0000 0x0 0x0
+#define MX6SLL_PAD_SD2_DATA2__AUD4_TXFS                           0x0208 0x04D0 0x0578 0x1 0x2
+#define MX6SLL_PAD_SD2_DATA2__CSI_DATA04                          0x0208 0x04D0 0x05D8 0x3 0x1
+#define MX6SLL_PAD_SD2_DATA2__UART5_DCE_RX                        0x0208 0x04D0 0x0764 0x4 0x4
+#define MX6SLL_PAD_SD2_DATA2__UART5_DTE_TX                        0x0208 0x04D0 0x0000 0x4 0x0
+#define MX6SLL_PAD_SD2_DATA2__GPIO5_IO03                          0x0208 0x04D0 0x0000 0x5 0x0
+#define MX6SLL_PAD_SD2_DATA3__SD2_DATA3                           0x020C 0x04D4 0x0000 0x0 0x0
+#define MX6SLL_PAD_SD2_DATA3__AUD4_TXD                            0x020C 0x04D4 0x0568 0x1 0x2
+#define MX6SLL_PAD_SD2_DATA3__CSI_DATA05                          0x020C 0x04D4 0x05DC 0x3 0x1
+#define MX6SLL_PAD_SD2_DATA3__UART5_DCE_TX                        0x020C 0x04D4 0x0000 0x4 0x0
+#define MX6SLL_PAD_SD2_DATA3__UART5_DTE_RX                        0x020C 0x04D4 0x0764 0x4 0x5
+#define MX6SLL_PAD_SD2_DATA3__GPIO4_IO28                          0x020C 0x04D4 0x0000 0x5 0x0
+#define MX6SLL_PAD_SD2_DATA4__SD2_DATA4                           0x0210 0x04D8 0x0000 0x0 0x0
+#define MX6SLL_PAD_SD2_DATA4__SD3_DATA4                           0x0210 0x04D8 0x0784 0x1 0x1
+#define MX6SLL_PAD_SD2_DATA4__UART2_DCE_RX                        0x0210 0x04D8 0x074C 0x2 0x2
+#define MX6SLL_PAD_SD2_DATA4__UART2_DTE_TX                        0x0210 0x04D8 0x0000 0x2 0x0
+#define MX6SLL_PAD_SD2_DATA4__CSI_DATA06                          0x0210 0x04D8 0x05E0 0x3 0x1
+#define MX6SLL_PAD_SD2_DATA4__SPDIF_OUT                           0x0210 0x04D8 0x0000 0x4 0x0
+#define MX6SLL_PAD_SD2_DATA4__GPIO5_IO02                          0x0210 0x04D8 0x0000 0x5 0x0
+#define MX6SLL_PAD_SD2_DATA5__SD2_DATA5                           0x0214 0x04DC 0x0000 0x0 0x0
+#define MX6SLL_PAD_SD2_DATA5__SD3_DATA5                           0x0214 0x04DC 0x0788 0x1 0x1
+#define MX6SLL_PAD_SD2_DATA5__UART2_DCE_TX                        0x0214 0x04DC 0x0000 0x2 0x0
+#define MX6SLL_PAD_SD2_DATA5__UART2_DTE_RX                        0x0214 0x04DC 0x074C 0x2 0x3
+#define MX6SLL_PAD_SD2_DATA5__CSI_DATA07                          0x0214 0x04DC 0x05E4 0x3 0x1
+#define MX6SLL_PAD_SD2_DATA5__SPDIF_IN                            0x0214 0x04DC 0x0738 0x4 0x1
+#define MX6SLL_PAD_SD2_DATA5__GPIO4_IO31                          0x0214 0x04DC 0x0000 0x5 0x0
+#define MX6SLL_PAD_SD2_DATA6__SD2_DATA6                           0x0218 0x04E0 0x0000 0x0 0x0
+#define MX6SLL_PAD_SD2_DATA6__SD3_DATA6                           0x0218 0x04E0 0x078C 0x1 0x1
+#define MX6SLL_PAD_SD2_DATA6__UART2_DCE_RTS                       0x0218 0x04E0 0x0748 0x2 0x2
+#define MX6SLL_PAD_SD2_DATA6__UART2_DTE_CTS                       0x0218 0x04E0 0x0000 0x2 0x0
+#define MX6SLL_PAD_SD2_DATA6__CSI_DATA08                          0x0218 0x04E0 0x05E8 0x3 0x1
+#define MX6SLL_PAD_SD2_DATA6__SD2_WP                              0x0218 0x04E0 0x077C 0x4 0x1
+#define MX6SLL_PAD_SD2_DATA6__GPIO4_IO29                          0x0218 0x04E0 0x0000 0x5 0x0
+#define MX6SLL_PAD_SD2_DATA7__SD2_DATA7                           0x021C 0x04E4 0x0000 0x0 0x0
+#define MX6SLL_PAD_SD2_DATA7__SD3_DATA7                           0x021C 0x04E4 0x0790 0x1 0x1
+#define MX6SLL_PAD_SD2_DATA7__UART2_DCE_CTS                       0x021C 0x04E4 0x0000 0x2 0x0
+#define MX6SLL_PAD_SD2_DATA7__UART2_DTE_RTS                       0x021C 0x04E4 0x0748 0x2 0x3
+#define MX6SLL_PAD_SD2_DATA7__CSI_DATA09                          0x021C 0x04E4 0x05EC 0x3 0x1
+#define MX6SLL_PAD_SD2_DATA7__SD2_CD_B                            0x021C 0x04E4 0x0778 0x4 0x1
+#define MX6SLL_PAD_SD2_DATA7__GPIO5_IO00                          0x021C 0x04E4 0x0000 0x5 0x0
+#define MX6SLL_PAD_SD3_CLK__SD3_CLK                               0x0220 0x04E8 0x0000 0x0 0x0
+#define MX6SLL_PAD_SD3_CLK__AUD5_RXFS                             0x0220 0x04E8 0x0588 0x1 0x0
+#define MX6SLL_PAD_SD3_CLK__KEY_COL5                              0x0220 0x04E8 0x0694 0x2 0x0
+#define MX6SLL_PAD_SD3_CLK__CSI_DATA10                            0x0220 0x04E8 0x05B0 0x3 0x0
+#define MX6SLL_PAD_SD3_CLK__WDOG1_RESET_B_DEB                     0x0220 0x04E8 0x0000 0x4 0x0
+#define MX6SLL_PAD_SD3_CLK__GPIO5_IO18                            0x0220 0x04E8 0x0000 0x5 0x0
+#define MX6SLL_PAD_SD3_CLK__USB_OTG1_PWR                          0x0220 0x04E8 0x0000 0x6 0x0
+#define MX6SLL_PAD_SD3_CMD__SD3_CMD                               0x0224 0x04EC 0x0000 0x0 0x0
+#define MX6SLL_PAD_SD3_CMD__AUD5_RXC                              0x0224 0x04EC 0x0584 0x1 0x0
+#define MX6SLL_PAD_SD3_CMD__KEY_ROW5                              0x0224 0x04EC 0x06B4 0x2 0x0
+#define MX6SLL_PAD_SD3_CMD__CSI_DATA11                            0x0224 0x04EC 0x05B4 0x3 0x0
+#define MX6SLL_PAD_SD3_CMD__USB_OTG2_ID                           0x0224 0x04EC 0x0560 0x4 0x1
+#define MX6SLL_PAD_SD3_CMD__GPIO5_IO21                            0x0224 0x04EC 0x0000 0x5 0x0
+#define MX6SLL_PAD_SD3_CMD__USB_OTG2_PWR                          0x0224 0x04EC 0x0000 0x6 0x0
+#define MX6SLL_PAD_SD3_DATA0__SD3_DATA0                           0x0228 0x04F0 0x0000 0x0 0x0
+#define MX6SLL_PAD_SD3_DATA0__AUD5_RXD                            0x0228 0x04F0 0x057C 0x1 0x0
+#define MX6SLL_PAD_SD3_DATA0__KEY_COL6                            0x0228 0x04F0 0x0698 0x2 0x0
+#define MX6SLL_PAD_SD3_DATA0__CSI_DATA12                          0x0228 0x04F0 0x05B8 0x3 0x0
+#define MX6SLL_PAD_SD3_DATA0__USB_OTG1_ID                         0x0228 0x04F0 0x055C 0x4 0x1
+#define MX6SLL_PAD_SD3_DATA0__GPIO5_IO19                          0x0228 0x04F0 0x0000 0x5 0x0
+#define MX6SLL_PAD_SD3_DATA1__SD3_DATA1                           0x022C 0x04F4 0x0000 0x0 0x0
+#define MX6SLL_PAD_SD3_DATA1__AUD5_TXC                            0x022C 0x04F4 0x058C 0x1 0x0
+#define MX6SLL_PAD_SD3_DATA1__KEY_ROW6                            0x022C 0x04F4 0x06B8 0x2 0x0
+#define MX6SLL_PAD_SD3_DATA1__CSI_DATA13                          0x022C 0x04F4 0x05BC 0x3 0x0
+#define MX6SLL_PAD_SD3_DATA1__SD1_VSELECT                         0x022C 0x04F4 0x0000 0x4 0x0
+#define MX6SLL_PAD_SD3_DATA1__GPIO5_IO20                          0x022C 0x04F4 0x0000 0x5 0x0
+#define MX6SLL_PAD_SD3_DATA1__JTAG_DE_B                           0x022C 0x04F4 0x0000 0x6 0x0
+#define MX6SLL_PAD_SD3_DATA2__SD3_DATA2                           0x0230 0x04F8 0x0000 0x0 0x0
+#define MX6SLL_PAD_SD3_DATA2__AUD5_TXFS                           0x0230 0x04F8 0x0590 0x1 0x0
+#define MX6SLL_PAD_SD3_DATA2__KEY_COL7                            0x0230 0x04F8 0x069C 0x2 0x0
+#define MX6SLL_PAD_SD3_DATA2__CSI_DATA14                          0x0230 0x04F8 0x05C0 0x3 0x0
+#define MX6SLL_PAD_SD3_DATA2__EPIT1_OUT                           0x0230 0x04F8 0x0000 0x4 0x0
+#define MX6SLL_PAD_SD3_DATA2__GPIO5_IO16                          0x0230 0x04F8 0x0000 0x5 0x0
+#define MX6SLL_PAD_SD3_DATA2__USB_OTG2_OC                         0x0230 0x04F8 0x0768 0x6 0x0
+#define MX6SLL_PAD_SD3_DATA3__SD3_DATA3                           0x0234 0x04FC 0x0000 0x0 0x0
+#define MX6SLL_PAD_SD3_DATA3__AUD5_TXD                            0x0234 0x04FC 0x0580 0x1 0x0
+#define MX6SLL_PAD_SD3_DATA3__KEY_ROW7                            0x0234 0x04FC 0x06BC 0x2 0x0
+#define MX6SLL_PAD_SD3_DATA3__CSI_DATA15                          0x0234 0x04FC 0x05C4 0x3 0x0
+#define MX6SLL_PAD_SD3_DATA3__EPIT2_OUT                           0x0234 0x04FC 0x0000 0x4 0x0
+#define MX6SLL_PAD_SD3_DATA3__GPIO5_IO17                          0x0234 0x04FC 0x0000 0x5 0x0
+#define MX6SLL_PAD_SD3_DATA3__USB_OTG1_OC                         0x0234 0x04FC 0x076C 0x6 0x0
+#define MX6SLL_PAD_GPIO4_IO20__SD1_STROBE                         0x0238 0x0500 0x0000 0x0 0x0
+#define MX6SLL_PAD_GPIO4_IO20__AUD6_RXFS                          0x0238 0x0500 0x05A0 0x2 0x0
+#define MX6SLL_PAD_GPIO4_IO20__ECSPI4_SS0                         0x0238 0x0500 0x065C 0x3 0x0
+#define MX6SLL_PAD_GPIO4_IO20__GPT_CAPTURE1                       0x0238 0x0500 0x0670 0x4 0x0
+#define MX6SLL_PAD_GPIO4_IO20__GPIO4_IO20                         0x0238 0x0500 0x0000 0x5 0x0
+#define MX6SLL_PAD_GPIO4_IO21__SD2_STROBE                         0x023C 0x0504 0x0000 0x0 0x0
+#define MX6SLL_PAD_GPIO4_IO21__AUD6_RXC                           0x023C 0x0504 0x059C 0x2 0x0
+#define MX6SLL_PAD_GPIO4_IO21__ECSPI4_SCLK                        0x023C 0x0504 0x0650 0x3 0x0
+#define MX6SLL_PAD_GPIO4_IO21__GPT_CAPTURE2                       0x023C 0x0504 0x0674 0x4 0x0
+#define MX6SLL_PAD_GPIO4_IO21__GPIO4_IO21                         0x023C 0x0504 0x0000 0x5 0x0
+#define MX6SLL_PAD_GPIO4_IO19__SD3_STROBE                         0x0240 0x0508 0x0000 0x0 0x0
+#define MX6SLL_PAD_GPIO4_IO19__AUD6_RXD                           0x0240 0x0508 0x0594 0x2 0x0
+#define MX6SLL_PAD_GPIO4_IO19__ECSPI4_MOSI                        0x0240 0x0508 0x0658 0x3 0x0
+#define MX6SLL_PAD_GPIO4_IO19__GPT_COMPARE1                       0x0240 0x0508 0x0000 0x4 0x0
+#define MX6SLL_PAD_GPIO4_IO19__GPIO4_IO19                         0x0240 0x0508 0x0000 0x5 0x0
+#define MX6SLL_PAD_GPIO4_IO25__AUD6_TXC                           0x0244 0x050C 0x05A4 0x2 0x0
+#define MX6SLL_PAD_GPIO4_IO25__ECSPI4_MISO                        0x0244 0x050C 0x0654 0x3 0x0
+#define MX6SLL_PAD_GPIO4_IO25__GPT_COMPARE2                       0x0244 0x050C 0x0000 0x4 0x0
+#define MX6SLL_PAD_GPIO4_IO25__GPIO4_IO25                         0x0244 0x050C 0x0000 0x5 0x0
+#define MX6SLL_PAD_GPIO4_IO18__AUD6_TXFS                          0x0248 0x0510 0x05A8 0x2 0x0
+#define MX6SLL_PAD_GPIO4_IO18__ECSPI4_SS1                         0x0248 0x0510 0x0660 0x3 0x0
+#define MX6SLL_PAD_GPIO4_IO18__GPT_COMPARE3                       0x0248 0x0510 0x0000 0x4 0x0
+#define MX6SLL_PAD_GPIO4_IO18__GPIO4_IO18                         0x0248 0x0510 0x0000 0x5 0x0
+#define MX6SLL_PAD_GPIO4_IO24__AUD6_TXD                           0x024C 0x0514 0x0598 0x2 0x0
+#define MX6SLL_PAD_GPIO4_IO24__ECSPI4_SS2                         0x024C 0x0514 0x0664 0x3 0x0
+#define MX6SLL_PAD_GPIO4_IO24__GPT_CLKIN                          0x024C 0x0514 0x0678 0x4 0x0
+#define MX6SLL_PAD_GPIO4_IO24__GPIO4_IO24                         0x024C 0x0514 0x0000 0x5 0x0
+#define MX6SLL_PAD_GPIO4_IO23__AUDIO_CLK_OUT                      0x0250 0x0518 0x0000 0x2 0x0
+#define MX6SLL_PAD_GPIO4_IO23__SD1_RESET                          0x0250 0x0518 0x0000 0x3 0x0
+#define MX6SLL_PAD_GPIO4_IO23__SD3_RESET                          0x0250 0x0518 0x0000 0x4 0x0
+#define MX6SLL_PAD_GPIO4_IO23__GPIO4_IO23                         0x0250 0x0518 0x0000 0x5 0x0
+#define MX6SLL_PAD_GPIO4_IO17__USB_OTG1_ID                        0x0254 0x051C 0x055C 0x2 0x2
+#define MX6SLL_PAD_GPIO4_IO17__SD1_VSELECT                        0x0254 0x051C 0x0000 0x3 0x0
+#define MX6SLL_PAD_GPIO4_IO17__SD3_VSELECT                        0x0254 0x051C 0x0000 0x4 0x0
+#define MX6SLL_PAD_GPIO4_IO17__GPIO4_IO17                         0x0254 0x051C 0x0000 0x5 0x0
+#define MX6SLL_PAD_GPIO4_IO22__SPDIF_IN                           0x0258 0x0520 0x0738 0x2 0x0
+#define MX6SLL_PAD_GPIO4_IO22__SD1_WP                             0x0258 0x0520 0x0774 0x3 0x0
+#define MX6SLL_PAD_GPIO4_IO22__SD3_WP                             0x0258 0x0520 0x0794 0x4 0x1
+#define MX6SLL_PAD_GPIO4_IO22__GPIO4_IO22                         0x0258 0x0520 0x0000 0x5 0x0
+#define MX6SLL_PAD_GPIO4_IO16__SPDIF_OUT                          0x025C 0x0524 0x0000 0x2 0x0
+#define MX6SLL_PAD_GPIO4_IO16__SD1_CD_B                           0x025C 0x0524 0x0770 0x3 0x0
+#define MX6SLL_PAD_GPIO4_IO16__SD3_CD_B                           0x025C 0x0524 0x0780 0x4 0x1
+#define MX6SLL_PAD_GPIO4_IO16__GPIO4_IO16                         0x025C 0x0524 0x0000 0x5 0x0
+#define MX6SLL_PAD_GPIO4_IO26__WDOG1_B                            0x0260 0x0528 0x0000 0x2 0x0
+#define MX6SLL_PAD_GPIO4_IO26__PWM4_OUT                           0x0260 0x0528 0x0000 0x3 0x0
+#define MX6SLL_PAD_GPIO4_IO26__CCM_PMIC_READY                     0x0260 0x0528 0x05AC 0x4 0x1
+#define MX6SLL_PAD_GPIO4_IO26__GPIO4_IO26                         0x0260 0x0528 0x0000 0x5 0x0
+#define MX6SLL_PAD_GPIO4_IO26__SPDIF_EXT_CLK                      0x0260 0x0528 0x073C 0x6 0x0
+
+#endif /* __DTS_IMX6SLL_PINFUNC_H */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/imx6sx-pinfunc.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/imx6sx-pinfunc.h
new file mode 100644
index 0000000000000000000000000000000000000000..5a989206f3336b1ce3118f8163fbefaa2240d3a9
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/imx6sx-pinfunc.h
@@ -0,0 +1,1584 @@
+/*
+ * Copyright (C) 2014 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __DTS_IMX6SX_PINFUNC_H
+#define __DTS_IMX6SX_PINFUNC_H
+
+/*
+ * The pin function ID is a tuple of
+ * <mux_reg conf_reg input_reg mux_mode input_val>
+ */
+#define MX6SX_PAD_GPIO1_IO00__I2C1_SCL                            0x0014 0x035C 0x07A8 0x0 0x1
+#define MX6SX_PAD_GPIO1_IO00__USDHC1_VSELECT                      0x0014 0x035C 0x0000 0x1 0x0
+#define MX6SX_PAD_GPIO1_IO00__SPDIF_LOCK                          0x0014 0x035C 0x0000 0x2 0x0
+#define MX6SX_PAD_GPIO1_IO00__CCM_WAIT                            0x0014 0x035C 0x0000 0x3 0x0
+#define MX6SX_PAD_GPIO1_IO00__WDOG1_WDOG_ANY                      0x0014 0x035C 0x0000 0x4 0x0
+#define MX6SX_PAD_GPIO1_IO00__GPIO1_IO_0                          0x0014 0x035C 0x0000 0x5 0x0
+#define MX6SX_PAD_GPIO1_IO00__SNVS_HP_WRAPPER_VIO_5               0x0014 0x035C 0x0000 0x6 0x0
+#define MX6SX_PAD_GPIO1_IO00__PHY_DTB_1                           0x0014 0x035C 0x0000 0x7 0x0
+#define MX6SX_PAD_GPIO1_IO01__I2C1_SDA                            0x0018 0x0360 0x07AC 0x0 0x1
+#define MX6SX_PAD_GPIO1_IO01__USDHC1_RESET_B                      0x0018 0x0360 0x0000 0x1 0x0
+#define MX6SX_PAD_GPIO1_IO01__SPDIF_SR_CLK                        0x0018 0x0360 0x0000 0x2 0x0
+#define MX6SX_PAD_GPIO1_IO01__CCM_STOP                            0x0018 0x0360 0x0000 0x3 0x0
+#define MX6SX_PAD_GPIO1_IO01__WDOG3_WDOG_B                        0x0018 0x0360 0x0000 0x4 0x0
+#define MX6SX_PAD_GPIO1_IO01__GPIO1_IO_1                          0x0018 0x0360 0x0000 0x5 0x0
+#define MX6SX_PAD_GPIO1_IO01__SNVS_HP_WRAPPER_VIO_5_CTL           0x0018 0x0360 0x0000 0x6 0x0
+#define MX6SX_PAD_GPIO1_IO01__PHY_DTB_0                           0x0018 0x0360 0x0000 0x7 0x0
+#define MX6SX_PAD_GPIO1_IO02__I2C2_SCL                            0x001C 0x0364 0x07B0 0x0 0x1
+#define MX6SX_PAD_GPIO1_IO02__USDHC1_CD_B                         0x001C 0x0364 0x0864 0x1 0x1
+#define MX6SX_PAD_GPIO1_IO02__CSI2_MCLK                           0x001C 0x0364 0x0000 0x2 0x0
+#define MX6SX_PAD_GPIO1_IO02__CCM_DI0_EXT_CLK                     0x001C 0x0364 0x0000 0x3 0x0
+#define MX6SX_PAD_GPIO1_IO02__WDOG1_WDOG_B                        0x001C 0x0364 0x0000 0x4 0x0
+#define MX6SX_PAD_GPIO1_IO02__GPIO1_IO_2                          0x001C 0x0364 0x0000 0x5 0x0
+#define MX6SX_PAD_GPIO1_IO02__CCM_REF_EN_B                        0x001C 0x0364 0x0000 0x6 0x0
+#define MX6SX_PAD_GPIO1_IO02__PHY_TDI                             0x001C 0x0364 0x0000 0x7 0x0
+#define MX6SX_PAD_GPIO1_IO03__I2C2_SDA                            0x0020 0x0368 0x07B4 0x0 0x1
+#define MX6SX_PAD_GPIO1_IO03__USDHC1_WP                           0x0020 0x0368 0x0868 0x1 0x1
+#define MX6SX_PAD_GPIO1_IO03__ENET1_REF_CLK_25M                   0x0020 0x0368 0x0000 0x2 0x0
+#define MX6SX_PAD_GPIO1_IO03__CCM_DI1_EXT_CLK                     0x0020 0x0368 0x0000 0x3 0x0
+#define MX6SX_PAD_GPIO1_IO03__WDOG2_WDOG_B                        0x0020 0x0368 0x0000 0x4 0x0
+#define MX6SX_PAD_GPIO1_IO03__GPIO1_IO_3                          0x0020 0x0368 0x0000 0x5 0x0
+#define MX6SX_PAD_GPIO1_IO03__CCM_PLL3_BYP                        0x0020 0x0368 0x0000 0x6 0x0
+#define MX6SX_PAD_GPIO1_IO03__PHY_TCK                             0x0020 0x0368 0x0000 0x7 0x0
+#define MX6SX_PAD_GPIO1_IO04__UART1_RX                            0x0024 0x036C 0x0830 0x0 0x0
+#define MX6SX_PAD_GPIO1_IO04__UART1_TX                            0x0024 0x036C 0x0000 0x0 0x0
+#define MX6SX_PAD_GPIO1_IO04__USDHC2_RESET_B                      0x0024 0x036C 0x0000 0x1 0x0
+#define MX6SX_PAD_GPIO1_IO04__ENET1_MDC                           0x0024 0x036C 0x0000 0x2 0x0
+#define MX6SX_PAD_GPIO1_IO04__OSC32K_32K_OUT                      0x0024 0x036C 0x0000 0x3 0x0
+#define MX6SX_PAD_GPIO1_IO04__ENET2_REF_CLK2                      0x0024 0x036C 0x076C 0x4 0x0
+#define MX6SX_PAD_GPIO1_IO04__GPIO1_IO_4                          0x0024 0x036C 0x0000 0x5 0x0
+#define MX6SX_PAD_GPIO1_IO04__CCM_PLL2_BYP                        0x0024 0x036C 0x0000 0x6 0x0
+#define MX6SX_PAD_GPIO1_IO04__PHY_TMS                             0x0024 0x036C 0x0000 0x7 0x0
+#define MX6SX_PAD_GPIO1_IO05__UART1_RX                            0x0028 0x0370 0x0830 0x0 0x1
+#define MX6SX_PAD_GPIO1_IO05__UART1_TX                            0x0028 0x0370 0x0000 0x0 0x0
+#define MX6SX_PAD_GPIO1_IO05__USDHC2_VSELECT                      0x0028 0x0370 0x0000 0x1 0x0
+#define MX6SX_PAD_GPIO1_IO05__ENET1_MDIO                          0x0028 0x0370 0x0764 0x2 0x0
+#define MX6SX_PAD_GPIO1_IO05__ASRC_ASRC_EXT_CLK                   0x0028 0x0370 0x0000 0x3 0x0
+#define MX6SX_PAD_GPIO1_IO05__ENET1_REF_CLK1                      0x0028 0x0370 0x0760 0x4 0x0
+#define MX6SX_PAD_GPIO1_IO05__GPIO1_IO_5                          0x0028 0x0370 0x0000 0x5 0x0
+#define MX6SX_PAD_GPIO1_IO05__SRC_TESTER_ACK                      0x0028 0x0370 0x0000 0x6 0x0
+#define MX6SX_PAD_GPIO1_IO05__PHY_TDO                             0x0028 0x0370 0x0000 0x7 0x0
+#define MX6SX_PAD_GPIO1_IO06__UART2_RX                            0x002C 0x0374 0x0838 0x0 0x0
+#define MX6SX_PAD_GPIO1_IO06__UART2_TX                            0x002C 0x0374 0x0000 0x0 0x0
+#define MX6SX_PAD_GPIO1_IO06__USDHC2_CD_B                         0x002C 0x0374 0x086C 0x1 0x1
+#define MX6SX_PAD_GPIO1_IO06__ENET2_MDC                           0x002C 0x0374 0x0000 0x2 0x0
+#define MX6SX_PAD_GPIO1_IO06__CSI1_MCLK                           0x002C 0x0374 0x0000 0x3 0x0
+#define MX6SX_PAD_GPIO1_IO06__UART1_RTS_B                         0x002C 0x0374 0x082C 0x4 0x0
+#define MX6SX_PAD_GPIO1_IO06__UART1_CTS_B                         0x002C 0x0374 0x0000 0x4 0x0
+#define MX6SX_PAD_GPIO1_IO06__GPIO1_IO_6                          0x002C 0x0374 0x0000 0x5 0x0
+#define MX6SX_PAD_GPIO1_IO06__SRC_ANY_PU_RESET                    0x002C 0x0374 0x0000 0x6 0x0
+#define MX6SX_PAD_GPIO1_IO06__OCOTP_CTRL_WRAPPER_FUSE_LATCHED     0x002C 0x0374 0x0000 0x7 0x0
+#define MX6SX_PAD_GPIO1_IO07__UART2_RX                            0x0030 0x0378 0x0838 0x0 0x1
+#define MX6SX_PAD_GPIO1_IO07__UART2_TX                            0x0030 0x0378 0x0000 0x0 0x0
+#define MX6SX_PAD_GPIO1_IO07__USDHC2_WP                           0x0030 0x0378 0x0870 0x1 0x1
+#define MX6SX_PAD_GPIO1_IO07__ENET2_MDIO                          0x0030 0x0378 0x0770 0x2 0x0
+#define MX6SX_PAD_GPIO1_IO07__AUDMUX_MCLK                         0x0030 0x0378 0x0000 0x3 0x0
+#define MX6SX_PAD_GPIO1_IO07__UART1_CTS_B                         0x0030 0x0378 0x0000 0x4 0x0
+#define MX6SX_PAD_GPIO1_IO07__UART1_RTS_B                         0x0030 0x0378 0x082C 0x4 0x1
+#define MX6SX_PAD_GPIO1_IO07__GPIO1_IO_7                          0x0030 0x0378 0x0000 0x5 0x0
+#define MX6SX_PAD_GPIO1_IO07__SRC_EARLY_RESET                     0x0030 0x0378 0x0000 0x6 0x0
+#define MX6SX_PAD_GPIO1_IO07__DCIC2_OUT                           0x0030 0x0378 0x0000 0x7 0x0
+#define MX6SX_PAD_GPIO1_IO07__VDEC_DEBUG_44                       0x0030 0x0378 0x0000 0x8 0x0
+#define MX6SX_PAD_GPIO1_IO08__USB_OTG1_OC                         0x0034 0x037C 0x0860 0x0 0x0
+#define MX6SX_PAD_GPIO1_IO08__WDOG1_WDOG_B                        0x0034 0x037C 0x0000 0x1 0x0
+#define MX6SX_PAD_GPIO1_IO08__SDMA_EXT_EVENT_0                    0x0034 0x037C 0x081C 0x2 0x0
+#define MX6SX_PAD_GPIO1_IO08__CCM_PMIC_RDY                        0x0034 0x037C 0x069C 0x3 0x1
+#define MX6SX_PAD_GPIO1_IO08__UART2_RTS_B                         0x0034 0x037C 0x0834 0x4 0x0
+#define MX6SX_PAD_GPIO1_IO08__UART2_CTS_B                         0x0034 0x037C 0x0000 0x4 0x0
+#define MX6SX_PAD_GPIO1_IO08__GPIO1_IO_8                          0x0034 0x037C 0x0000 0x5 0x0
+#define MX6SX_PAD_GPIO1_IO08__SRC_SYSTEM_RESET                    0x0034 0x037C 0x0000 0x6 0x0
+#define MX6SX_PAD_GPIO1_IO08__DCIC1_OUT                           0x0034 0x037C 0x0000 0x7 0x0
+#define MX6SX_PAD_GPIO1_IO08__VDEC_DEBUG_43                       0x0034 0x037C 0x0000 0x8 0x0
+#define MX6SX_PAD_GPIO1_IO09__USB_OTG1_PWR                        0x0038 0x0380 0x0000 0x0 0x0
+#define MX6SX_PAD_GPIO1_IO09__WDOG2_WDOG_B                        0x0038 0x0380 0x0000 0x1 0x0
+#define MX6SX_PAD_GPIO1_IO09__SDMA_EXT_EVENT_1                    0x0038 0x0380 0x0820 0x2 0x0
+#define MX6SX_PAD_GPIO1_IO09__CCM_OUT0                            0x0038 0x0380 0x0000 0x3 0x0
+#define MX6SX_PAD_GPIO1_IO09__UART2_CTS_B                         0x0038 0x0380 0x0000 0x4 0x0
+#define MX6SX_PAD_GPIO1_IO09__UART2_RTS_B                         0x0038 0x0380 0x0834 0x4 0x1
+#define MX6SX_PAD_GPIO1_IO09__GPIO1_IO_9                          0x0038 0x0380 0x0000 0x5 0x0
+#define MX6SX_PAD_GPIO1_IO09__SRC_INT_BOOT                        0x0038 0x0380 0x0000 0x6 0x0
+#define MX6SX_PAD_GPIO1_IO09__OBSERVE_MUX_OUT_4                   0x0038 0x0380 0x0000 0x7 0x0
+#define MX6SX_PAD_GPIO1_IO09__VDEC_DEBUG_42                       0x0038 0x0380 0x0000 0x8 0x0
+#define MX6SX_PAD_GPIO1_IO10__ANATOP_OTG1_ID                      0x003C 0x0384 0x0624 0x0 0x0
+#define MX6SX_PAD_GPIO1_IO10__SPDIF_EXT_CLK                       0x003C 0x0384 0x0828 0x1 0x0
+#define MX6SX_PAD_GPIO1_IO10__PWM1_OUT                            0x003C 0x0384 0x0000 0x2 0x0
+#define MX6SX_PAD_GPIO1_IO10__CCM_OUT1                            0x003C 0x0384 0x0000 0x3 0x0
+#define MX6SX_PAD_GPIO1_IO10__CSI1_FIELD                          0x003C 0x0384 0x070C 0x4 0x1
+#define MX6SX_PAD_GPIO1_IO10__GPIO1_IO_10                         0x003C 0x0384 0x0000 0x5 0x0
+#define MX6SX_PAD_GPIO1_IO10__CSU_CSU_INT_DEB                     0x003C 0x0384 0x0000 0x6 0x0
+#define MX6SX_PAD_GPIO1_IO10__OBSERVE_MUX_OUT_3                   0x003C 0x0384 0x0000 0x7 0x0
+#define MX6SX_PAD_GPIO1_IO10__VDEC_DEBUG_41                       0x003C 0x0384 0x0000 0x8 0x0
+#define MX6SX_PAD_GPIO1_IO11__USB_OTG2_OC                         0x0040 0x0388 0x085C 0x0 0x0
+#define MX6SX_PAD_GPIO1_IO11__SPDIF_IN                            0x0040 0x0388 0x0824 0x1 0x2
+#define MX6SX_PAD_GPIO1_IO11__PWM2_OUT                            0x0040 0x0388 0x0000 0x2 0x0
+#define MX6SX_PAD_GPIO1_IO11__CCM_CLKO1                           0x0040 0x0388 0x0000 0x3 0x0
+#define MX6SX_PAD_GPIO1_IO11__MLB_DATA                            0x0040 0x0388 0x07EC 0x4 0x0
+#define MX6SX_PAD_GPIO1_IO11__GPIO1_IO_11                         0x0040 0x0388 0x0000 0x5 0x0
+#define MX6SX_PAD_GPIO1_IO11__CSU_CSU_ALARM_AUT_0                 0x0040 0x0388 0x0000 0x6 0x0
+#define MX6SX_PAD_GPIO1_IO11__OBSERVE_MUX_OUT_2                   0x0040 0x0388 0x0000 0x7 0x0
+#define MX6SX_PAD_GPIO1_IO11__VDEC_DEBUG_40                       0x0040 0x0388 0x0000 0x8 0x0
+#define MX6SX_PAD_GPIO1_IO12__USB_OTG2_PWR                        0x0044 0x038C 0x0000 0x0 0x0
+#define MX6SX_PAD_GPIO1_IO12__SPDIF_OUT                           0x0044 0x038C 0x0000 0x1 0x0
+#define MX6SX_PAD_GPIO1_IO12__PWM3_OUT                            0x0044 0x038C 0x0000 0x2 0x0
+#define MX6SX_PAD_GPIO1_IO12__CCM_CLKO2                           0x0044 0x038C 0x0000 0x3 0x0
+#define MX6SX_PAD_GPIO1_IO12__MLB_CLK                             0x0044 0x038C 0x07E8 0x4 0x0
+#define MX6SX_PAD_GPIO1_IO12__GPIO1_IO_12                         0x0044 0x038C 0x0000 0x5 0x0
+#define MX6SX_PAD_GPIO1_IO12__CSU_CSU_ALARM_AUT_1                 0x0044 0x038C 0x0000 0x6 0x0
+#define MX6SX_PAD_GPIO1_IO12__OBSERVE_MUX_OUT_1                   0x0044 0x038C 0x0000 0x7 0x0
+#define MX6SX_PAD_GPIO1_IO12__VDEC_DEBUG_39                       0x0044 0x038C 0x0000 0x8 0x0
+#define MX6SX_PAD_GPIO1_IO13__WDOG1_WDOG_ANY                      0x0048 0x0390 0x0000 0x0 0x0
+#define MX6SX_PAD_GPIO1_IO13__ANATOP_OTG2_ID                      0x0048 0x0390 0x0628 0x1 0x0
+#define MX6SX_PAD_GPIO1_IO13__PWM4_OUT                            0x0048 0x0390 0x0000 0x2 0x0
+#define MX6SX_PAD_GPIO1_IO13__CCM_OUT2                            0x0048 0x0390 0x0000 0x3 0x0
+#define MX6SX_PAD_GPIO1_IO13__MLB_SIG                             0x0048 0x0390 0x07F0 0x4 0x0
+#define MX6SX_PAD_GPIO1_IO13__GPIO1_IO_13                         0x0048 0x0390 0x0000 0x5 0x0
+#define MX6SX_PAD_GPIO1_IO13__CSU_CSU_ALARM_AUT_2                 0x0048 0x0390 0x0000 0x6 0x0
+#define MX6SX_PAD_GPIO1_IO13__OBSERVE_MUX_OUT_0                   0x0048 0x0390 0x0000 0x7 0x0
+#define MX6SX_PAD_GPIO1_IO13__VDEC_DEBUG_38                       0x0048 0x0390 0x0000 0x8 0x0
+#define MX6SX_PAD_CSI_DATA00__CSI1_DATA_2                         0x004C 0x0394 0x06A8 0x0 0x0
+#define MX6SX_PAD_CSI_DATA00__ESAI_TX_CLK                         0x004C 0x0394 0x078C 0x1 0x1
+#define MX6SX_PAD_CSI_DATA00__AUDMUX_AUD6_TXC                     0x004C 0x0394 0x0684 0x2 0x1
+#define MX6SX_PAD_CSI_DATA00__I2C1_SCL                            0x004C 0x0394 0x07A8 0x3 0x0
+#define MX6SX_PAD_CSI_DATA00__UART6_RI_B                          0x004C 0x0394 0x0000 0x4 0x0
+#define MX6SX_PAD_CSI_DATA00__GPIO1_IO_14                         0x004C 0x0394 0x0000 0x5 0x0
+#define MX6SX_PAD_CSI_DATA00__WEIM_DATA_23                        0x004C 0x0394 0x0000 0x6 0x0
+#define MX6SX_PAD_CSI_DATA00__SAI1_TX_BCLK                        0x004C 0x0394 0x0800 0x7 0x0
+#define MX6SX_PAD_CSI_DATA00__VADC_DATA_4                         0x004C 0x0394 0x0000 0x8 0x0
+#define MX6SX_PAD_CSI_DATA00__MMDC_DEBUG_37                       0x004C 0x0394 0x0000 0x9 0x0
+#define MX6SX_PAD_CSI_DATA01__CSI1_DATA_3                         0x0050 0x0398 0x06AC 0x0 0x0
+#define MX6SX_PAD_CSI_DATA01__ESAI_TX_FS                          0x0050 0x0398 0x077C 0x1 0x1
+#define MX6SX_PAD_CSI_DATA01__AUDMUX_AUD6_TXFS                    0x0050 0x0398 0x0688 0x2 0x1
+#define MX6SX_PAD_CSI_DATA01__I2C1_SDA                            0x0050 0x0398 0x07AC 0x3 0x0
+#define MX6SX_PAD_CSI_DATA01__UART6_DSR_B                         0x0050 0x0398 0x0000 0x4 0x0
+#define MX6SX_PAD_CSI_DATA01__GPIO1_IO_15                         0x0050 0x0398 0x0000 0x5 0x0
+#define MX6SX_PAD_CSI_DATA01__WEIM_DATA_22                        0x0050 0x0398 0x0000 0x6 0x0
+#define MX6SX_PAD_CSI_DATA01__SAI1_TX_SYNC                        0x0050 0x0398 0x0804 0x7 0x0
+#define MX6SX_PAD_CSI_DATA01__VADC_DATA_5                         0x0050 0x0398 0x0000 0x8 0x0
+#define MX6SX_PAD_CSI_DATA01__MMDC_DEBUG_38                       0x0050 0x0398 0x0000 0x9 0x0
+#define MX6SX_PAD_CSI_DATA02__CSI1_DATA_4                         0x0054 0x039C 0x06B0 0x0 0x0
+#define MX6SX_PAD_CSI_DATA02__ESAI_RX_CLK                         0x0054 0x039C 0x0788 0x1 0x1
+#define MX6SX_PAD_CSI_DATA02__AUDMUX_AUD6_RXC                     0x0054 0x039C 0x067C 0x2 0x1
+#define MX6SX_PAD_CSI_DATA02__KPP_COL_5                           0x0054 0x039C 0x07C8 0x3 0x0
+#define MX6SX_PAD_CSI_DATA02__UART6_DTR_B                         0x0054 0x039C 0x0000 0x4 0x0
+#define MX6SX_PAD_CSI_DATA02__GPIO1_IO_16                         0x0054 0x039C 0x0000 0x5 0x0
+#define MX6SX_PAD_CSI_DATA02__WEIM_DATA_21                        0x0054 0x039C 0x0000 0x6 0x0
+#define MX6SX_PAD_CSI_DATA02__SAI1_RX_BCLK                        0x0054 0x039C 0x07F4 0x7 0x0
+#define MX6SX_PAD_CSI_DATA02__VADC_DATA_6                         0x0054 0x039C 0x0000 0x8 0x0
+#define MX6SX_PAD_CSI_DATA02__MMDC_DEBUG_39                       0x0054 0x039C 0x0000 0x9 0x0
+#define MX6SX_PAD_CSI_DATA03__CSI1_DATA_5                         0x0058 0x03A0 0x06B4 0x0 0x0
+#define MX6SX_PAD_CSI_DATA03__ESAI_RX_FS                          0x0058 0x03A0 0x0778 0x1 0x1
+#define MX6SX_PAD_CSI_DATA03__AUDMUX_AUD6_RXFS                    0x0058 0x03A0 0x0680 0x2 0x1
+#define MX6SX_PAD_CSI_DATA03__KPP_ROW_5                           0x0058 0x03A0 0x07D4 0x3 0x0
+#define MX6SX_PAD_CSI_DATA03__UART6_DCD_B                         0x0058 0x03A0 0x0000 0x4 0x0
+#define MX6SX_PAD_CSI_DATA03__GPIO1_IO_17                         0x0058 0x03A0 0x0000 0x5 0x0
+#define MX6SX_PAD_CSI_DATA03__WEIM_DATA_20                        0x0058 0x03A0 0x0000 0x6 0x0
+#define MX6SX_PAD_CSI_DATA03__SAI1_RX_SYNC                        0x0058 0x03A0 0x07FC 0x7 0x0
+#define MX6SX_PAD_CSI_DATA03__VADC_DATA_7                         0x0058 0x03A0 0x0000 0x8 0x0
+#define MX6SX_PAD_CSI_DATA03__MMDC_DEBUG_40                       0x0058 0x03A0 0x0000 0x9 0x0
+#define MX6SX_PAD_CSI_DATA04__CSI1_DATA_6                         0x005C 0x03A4 0x06B8 0x0 0x0
+#define MX6SX_PAD_CSI_DATA04__ESAI_TX1                            0x005C 0x03A4 0x0794 0x1 0x1
+#define MX6SX_PAD_CSI_DATA04__SPDIF_OUT                           0x005C 0x03A4 0x0000 0x2 0x0
+#define MX6SX_PAD_CSI_DATA04__KPP_COL_6                           0x005C 0x03A4 0x07CC 0x3 0x0
+#define MX6SX_PAD_CSI_DATA04__UART6_RX                            0x005C 0x03A4 0x0858 0x4 0x0
+#define MX6SX_PAD_CSI_DATA04__UART6_TX                            0x005C 0x03A4 0x0000 0x4 0x0
+#define MX6SX_PAD_CSI_DATA04__GPIO1_IO_18                         0x005C 0x03A4 0x0000 0x5 0x0
+#define MX6SX_PAD_CSI_DATA04__WEIM_DATA_19                        0x005C 0x03A4 0x0000 0x6 0x0
+#define MX6SX_PAD_CSI_DATA04__PWM5_OUT                            0x005C 0x03A4 0x0000 0x7 0x0
+#define MX6SX_PAD_CSI_DATA04__VADC_DATA_8                         0x005C 0x03A4 0x0000 0x8 0x0
+#define MX6SX_PAD_CSI_DATA04__MMDC_DEBUG_41                       0x005C 0x03A4 0x0000 0x9 0x0
+#define MX6SX_PAD_CSI_DATA05__CSI1_DATA_7                         0x0060 0x03A8 0x06BC 0x0 0x0
+#define MX6SX_PAD_CSI_DATA05__ESAI_TX4_RX1                        0x0060 0x03A8 0x07A0 0x1 0x1
+#define MX6SX_PAD_CSI_DATA05__SPDIF_IN                            0x0060 0x03A8 0x0824 0x2 0x1
+#define MX6SX_PAD_CSI_DATA05__KPP_ROW_6                           0x0060 0x03A8 0x07D8 0x3 0x0
+#define MX6SX_PAD_CSI_DATA05__UART6_RX                            0x0060 0x03A8 0x0858 0x4 0x1
+#define MX6SX_PAD_CSI_DATA05__UART6_TX                            0x0060 0x03A8 0x0000 0x4 0x0
+#define MX6SX_PAD_CSI_DATA05__GPIO1_IO_19                         0x0060 0x03A8 0x0000 0x5 0x0
+#define MX6SX_PAD_CSI_DATA05__WEIM_DATA_18                        0x0060 0x03A8 0x0000 0x6 0x0
+#define MX6SX_PAD_CSI_DATA05__PWM6_OUT                            0x0060 0x03A8 0x0000 0x7 0x0
+#define MX6SX_PAD_CSI_DATA05__VADC_DATA_9                         0x0060 0x03A8 0x0000 0x8 0x0
+#define MX6SX_PAD_CSI_DATA05__MMDC_DEBUG_42                       0x0060 0x03A8 0x0000 0x9 0x0
+#define MX6SX_PAD_CSI_DATA06__CSI1_DATA_8                         0x0064 0x03AC 0x06C0 0x0 0x0
+#define MX6SX_PAD_CSI_DATA06__ESAI_TX2_RX3                        0x0064 0x03AC 0x0798 0x1 0x1
+#define MX6SX_PAD_CSI_DATA06__I2C4_SCL                            0x0064 0x03AC 0x07C0 0x2 0x2
+#define MX6SX_PAD_CSI_DATA06__KPP_COL_7                           0x0064 0x03AC 0x07D0 0x3 0x0
+#define MX6SX_PAD_CSI_DATA06__UART6_RTS_B                         0x0064 0x03AC 0x0854 0x4 0x0
+#define MX6SX_PAD_CSI_DATA06__UART6_CTS_B                         0x0064 0x03AC 0x0000 0x4 0x0
+#define MX6SX_PAD_CSI_DATA06__GPIO1_IO_20                         0x0064 0x03AC 0x0000 0x5 0x0
+#define MX6SX_PAD_CSI_DATA06__WEIM_DATA_17                        0x0064 0x03AC 0x0000 0x6 0x0
+#define MX6SX_PAD_CSI_DATA06__DCIC2_OUT                           0x0064 0x03AC 0x0000 0x7 0x0
+#define MX6SX_PAD_CSI_DATA06__VADC_DATA_10                        0x0064 0x03AC 0x0000 0x8 0x0
+#define MX6SX_PAD_CSI_DATA06__MMDC_DEBUG_43                       0x0064 0x03AC 0x0000 0x9 0x0
+#define MX6SX_PAD_CSI_DATA07__CSI1_DATA_9                         0x0068 0x03B0 0x06C4 0x0 0x0
+#define MX6SX_PAD_CSI_DATA07__ESAI_TX3_RX2                        0x0068 0x03B0 0x079C 0x1 0x1
+#define MX6SX_PAD_CSI_DATA07__I2C4_SDA                            0x0068 0x03B0 0x07C4 0x2 0x2
+#define MX6SX_PAD_CSI_DATA07__KPP_ROW_7                           0x0068 0x03B0 0x07DC 0x3 0x0
+#define MX6SX_PAD_CSI_DATA07__UART6_CTS_B                         0x0068 0x03B0 0x0000 0x4 0x0
+#define MX6SX_PAD_CSI_DATA07__UART6_RTS_B                         0x0068 0x03B0 0x0854 0x4 0x1
+#define MX6SX_PAD_CSI_DATA07__GPIO1_IO_21                         0x0068 0x03B0 0x0000 0x5 0x0
+#define MX6SX_PAD_CSI_DATA07__WEIM_DATA_16                        0x0068 0x03B0 0x0000 0x6 0x0
+#define MX6SX_PAD_CSI_DATA07__DCIC1_OUT                           0x0068 0x03B0 0x0000 0x7 0x0
+#define MX6SX_PAD_CSI_DATA07__VADC_DATA_11                        0x0068 0x03B0 0x0000 0x8 0x0
+#define MX6SX_PAD_CSI_DATA07__MMDC_DEBUG_44                       0x0068 0x03B0 0x0000 0x9 0x0
+#define MX6SX_PAD_CSI_HSYNC__CSI1_HSYNC                           0x006C 0x03B4 0x0700 0x0 0x0
+#define MX6SX_PAD_CSI_HSYNC__ESAI_TX0                             0x006C 0x03B4 0x0790 0x1 0x1
+#define MX6SX_PAD_CSI_HSYNC__AUDMUX_AUD6_TXD                      0x006C 0x03B4 0x0678 0x2 0x1
+#define MX6SX_PAD_CSI_HSYNC__UART4_RTS_B                          0x006C 0x03B4 0x0844 0x3 0x2
+#define MX6SX_PAD_CSI_HSYNC__UART4_CTS_B                          0x006C 0x03B4 0x0000 0x3 0x0
+#define MX6SX_PAD_CSI_HSYNC__MQS_LEFT                             0x006C 0x03B4 0x0000 0x4 0x0
+#define MX6SX_PAD_CSI_HSYNC__GPIO1_IO_22                          0x006C 0x03B4 0x0000 0x5 0x0
+#define MX6SX_PAD_CSI_HSYNC__WEIM_DATA_25                         0x006C 0x03B4 0x0000 0x6 0x0
+#define MX6SX_PAD_CSI_HSYNC__SAI1_TX_DATA_0                       0x006C 0x03B4 0x0000 0x7 0x0
+#define MX6SX_PAD_CSI_HSYNC__VADC_DATA_2                          0x006C 0x03B4 0x0000 0x8 0x0
+#define MX6SX_PAD_CSI_HSYNC__MMDC_DEBUG_35                        0x006C 0x03B4 0x0000 0x9 0x0
+#define MX6SX_PAD_CSI_MCLK__CSI1_MCLK                             0x0070 0x03B8 0x0000 0x0 0x0
+#define MX6SX_PAD_CSI_MCLK__ESAI_TX_HF_CLK                        0x0070 0x03B8 0x0784 0x1 0x1
+#define MX6SX_PAD_CSI_MCLK__OSC32K_32K_OUT                        0x0070 0x03B8 0x0000 0x2 0x0
+#define MX6SX_PAD_CSI_MCLK__UART4_RX                              0x0070 0x03B8 0x0848 0x3 0x2
+#define MX6SX_PAD_CSI_MCLK__UART4_TX                              0x0070 0x03B8 0x0000 0x3 0x0
+#define MX6SX_PAD_CSI_MCLK__ANATOP_32K_OUT                        0x0070 0x03B8 0x0000 0x4 0x0
+#define MX6SX_PAD_CSI_MCLK__GPIO1_IO_23                           0x0070 0x03B8 0x0000 0x5 0x0
+#define MX6SX_PAD_CSI_MCLK__WEIM_DATA_26                          0x0070 0x03B8 0x0000 0x6 0x0
+#define MX6SX_PAD_CSI_MCLK__CSI1_FIELD                            0x0070 0x03B8 0x070C 0x7 0x0
+#define MX6SX_PAD_CSI_MCLK__VADC_DATA_1                           0x0070 0x03B8 0x0000 0x8 0x0
+#define MX6SX_PAD_CSI_MCLK__MMDC_DEBUG_34                         0x0070 0x03B8 0x0000 0x9 0x0
+#define MX6SX_PAD_CSI_PIXCLK__CSI1_PIXCLK                         0x0074 0x03BC 0x0704 0x0 0x0
+#define MX6SX_PAD_CSI_PIXCLK__ESAI_RX_HF_CLK                      0x0074 0x03BC 0x0780 0x1 0x1
+#define MX6SX_PAD_CSI_PIXCLK__AUDMUX_MCLK                         0x0074 0x03BC 0x0000 0x2 0x0
+#define MX6SX_PAD_CSI_PIXCLK__UART4_RX                            0x0074 0x03BC 0x0848 0x3 0x3
+#define MX6SX_PAD_CSI_PIXCLK__UART4_TX                            0x0074 0x03BC 0x0000 0x3 0x0
+#define MX6SX_PAD_CSI_PIXCLK__ANATOP_24M_OUT                      0x0074 0x03BC 0x0000 0x4 0x0
+#define MX6SX_PAD_CSI_PIXCLK__GPIO1_IO_24                         0x0074 0x03BC 0x0000 0x5 0x0
+#define MX6SX_PAD_CSI_PIXCLK__WEIM_DATA_27                        0x0074 0x03BC 0x0000 0x6 0x0
+#define MX6SX_PAD_CSI_PIXCLK__ESAI_TX_HF_CLK                      0x0074 0x03BC 0x0784 0x7 0x2
+#define MX6SX_PAD_CSI_PIXCLK__VADC_CLK                            0x0074 0x03BC 0x0000 0x8 0x0
+#define MX6SX_PAD_CSI_PIXCLK__MMDC_DEBUG_33                       0x0074 0x03BC 0x0000 0x9 0x0
+#define MX6SX_PAD_CSI_VSYNC__CSI1_VSYNC                           0x0078 0x03C0 0x0708 0x0 0x0
+#define MX6SX_PAD_CSI_VSYNC__ESAI_TX5_RX0                         0x0078 0x03C0 0x07A4 0x1 0x1
+#define MX6SX_PAD_CSI_VSYNC__AUDMUX_AUD6_RXD                      0x0078 0x03C0 0x0674 0x2 0x1
+#define MX6SX_PAD_CSI_VSYNC__UART4_CTS_B                          0x0078 0x03C0 0x0000 0x3 0x0
+#define MX6SX_PAD_CSI_VSYNC__UART4_RTS_B                          0x0078 0x03C0 0x0844 0x3 0x3
+#define MX6SX_PAD_CSI_VSYNC__MQS_RIGHT                            0x0078 0x03C0 0x0000 0x4 0x0
+#define MX6SX_PAD_CSI_VSYNC__GPIO1_IO_25                          0x0078 0x03C0 0x0000 0x5 0x0
+#define MX6SX_PAD_CSI_VSYNC__WEIM_DATA_24                         0x0078 0x03C0 0x0000 0x6 0x0
+#define MX6SX_PAD_CSI_VSYNC__SAI1_RX_DATA_0                       0x0078 0x03C0 0x07F8 0x7 0x0
+#define MX6SX_PAD_CSI_VSYNC__VADC_DATA_3                          0x0078 0x03C0 0x0000 0x8 0x0
+#define MX6SX_PAD_CSI_VSYNC__MMDC_DEBUG_36                        0x0078 0x03C0 0x0000 0x9 0x0
+#define MX6SX_PAD_ENET1_COL__ENET1_COL                            0x007C 0x03C4 0x0000 0x0 0x0
+#define MX6SX_PAD_ENET1_COL__ENET2_MDC                            0x007C 0x03C4 0x0000 0x1 0x0
+#define MX6SX_PAD_ENET1_COL__AUDMUX_AUD4_TXC                      0x007C 0x03C4 0x0654 0x2 0x1
+#define MX6SX_PAD_ENET1_COL__UART1_RI_B                           0x007C 0x03C4 0x0000 0x3 0x0
+#define MX6SX_PAD_ENET1_COL__SPDIF_EXT_CLK                        0x007C 0x03C4 0x0828 0x4 0x1
+#define MX6SX_PAD_ENET1_COL__GPIO2_IO_0                           0x007C 0x03C4 0x0000 0x5 0x0
+#define MX6SX_PAD_ENET1_COL__CSI2_DATA_23                         0x007C 0x03C4 0x0000 0x6 0x0
+#define MX6SX_PAD_ENET1_COL__LCDIF2_DATA_16                       0x007C 0x03C4 0x0000 0x7 0x0
+#define MX6SX_PAD_ENET1_COL__VDEC_DEBUG_37                        0x007C 0x03C4 0x0000 0x8 0x0
+#define MX6SX_PAD_ENET1_COL__PCIE_CTRL_DEBUG_31                   0x007C 0x03C4 0x0000 0x9 0x0
+#define MX6SX_PAD_ENET1_CRS__ENET1_CRS                            0x0080 0x03C8 0x0000 0x0 0x0
+#define MX6SX_PAD_ENET1_CRS__ENET2_MDIO                           0x0080 0x03C8 0x0770 0x1 0x1
+#define MX6SX_PAD_ENET1_CRS__AUDMUX_AUD4_TXD                      0x0080 0x03C8 0x0648 0x2 0x1
+#define MX6SX_PAD_ENET1_CRS__UART1_DCD_B                          0x0080 0x03C8 0x0000 0x3 0x0
+#define MX6SX_PAD_ENET1_CRS__SPDIF_LOCK                           0x0080 0x03C8 0x0000 0x4 0x0
+#define MX6SX_PAD_ENET1_CRS__GPIO2_IO_1                           0x0080 0x03C8 0x0000 0x5 0x0
+#define MX6SX_PAD_ENET1_CRS__CSI2_DATA_22                         0x0080 0x03C8 0x0000 0x6 0x0
+#define MX6SX_PAD_ENET1_CRS__LCDIF2_DATA_17                       0x0080 0x03C8 0x0000 0x7 0x0
+#define MX6SX_PAD_ENET1_CRS__VDEC_DEBUG_36                        0x0080 0x03C8 0x0000 0x8 0x0
+#define MX6SX_PAD_ENET1_CRS__PCIE_CTRL_DEBUG_30                   0x0080 0x03C8 0x0000 0x9 0x0
+#define MX6SX_PAD_ENET1_MDC__ENET1_MDC                            0x0084 0x03CC 0x0000 0x0 0x0
+#define MX6SX_PAD_ENET1_MDC__ENET2_MDC                            0x0084 0x03CC 0x0000 0x1 0x0
+#define MX6SX_PAD_ENET1_MDC__AUDMUX_AUD3_RXFS                     0x0084 0x03CC 0x0638 0x2 0x1
+#define MX6SX_PAD_ENET1_MDC__ANATOP_24M_OUT                       0x0084 0x03CC 0x0000 0x3 0x0
+#define MX6SX_PAD_ENET1_MDC__EPIT2_OUT                            0x0084 0x03CC 0x0000 0x4 0x0
+#define MX6SX_PAD_ENET1_MDC__GPIO2_IO_2                           0x0084 0x03CC 0x0000 0x5 0x0
+#define MX6SX_PAD_ENET1_MDC__USB_OTG1_PWR                         0x0084 0x03CC 0x0000 0x6 0x0
+#define MX6SX_PAD_ENET1_MDC__PWM7_OUT                             0x0084 0x03CC 0x0000 0x7 0x0
+#define MX6SX_PAD_ENET1_MDIO__ENET1_MDIO                          0x0088 0x03D0 0x0764 0x0 0x1
+#define MX6SX_PAD_ENET1_MDIO__ENET2_MDIO                          0x0088 0x03D0 0x0770 0x1 0x2
+#define MX6SX_PAD_ENET1_MDIO__AUDMUX_MCLK                         0x0088 0x03D0 0x0000 0x2 0x0
+#define MX6SX_PAD_ENET1_MDIO__OSC32K_32K_OUT                      0x0088 0x03D0 0x0000 0x3 0x0
+#define MX6SX_PAD_ENET1_MDIO__EPIT1_OUT                           0x0088 0x03D0 0x0000 0x4 0x0
+#define MX6SX_PAD_ENET1_MDIO__GPIO2_IO_3                          0x0088 0x03D0 0x0000 0x5 0x0
+#define MX6SX_PAD_ENET1_MDIO__USB_OTG1_OC                         0x0088 0x03D0 0x0860 0x6 0x1
+#define MX6SX_PAD_ENET1_MDIO__PWM8_OUT                            0x0088 0x03D0 0x0000 0x7 0x0
+#define MX6SX_PAD_ENET1_RX_CLK__ENET1_RX_CLK                      0x008C 0x03D4 0x0768 0x0 0x0
+#define MX6SX_PAD_ENET1_RX_CLK__ENET1_REF_CLK_25M                 0x008C 0x03D4 0x0000 0x1 0x0
+#define MX6SX_PAD_ENET1_RX_CLK__AUDMUX_AUD4_TXFS                  0x008C 0x03D4 0x0658 0x2 0x1
+#define MX6SX_PAD_ENET1_RX_CLK__UART1_DSR_B                       0x008C 0x03D4 0x0000 0x3 0x0
+#define MX6SX_PAD_ENET1_RX_CLK__SPDIF_OUT                         0x008C 0x03D4 0x0000 0x4 0x0
+#define MX6SX_PAD_ENET1_RX_CLK__GPIO2_IO_4                        0x008C 0x03D4 0x0000 0x5 0x0
+#define MX6SX_PAD_ENET1_RX_CLK__CSI2_DATA_21                      0x008C 0x03D4 0x0000 0x6 0x0
+#define MX6SX_PAD_ENET1_RX_CLK__LCDIF2_DATA_18                    0x008C 0x03D4 0x0000 0x7 0x0
+#define MX6SX_PAD_ENET1_RX_CLK__VDEC_DEBUG_35                     0x008C 0x03D4 0x0000 0x8 0x0
+#define MX6SX_PAD_ENET1_RX_CLK__PCIE_CTRL_DEBUG_29                0x008C 0x03D4 0x0000 0x9 0x0
+#define MX6SX_PAD_ENET1_TX_CLK__ENET1_TX_CLK                      0x0090 0x03D8 0x0000 0x0 0x0
+/*
+ * SION bit is necessary for ENET1_REF_CLK1 (ENET2_REF_CLK2 untested) if it is
+ * used as clock output of IMX6SX_CLK_ENET_REF (ENET1_TX_CLK) to e.g. supply a
+ * PHY in RMII mode. This configuration is valid if:
+ *  - bit 1 in field IMX6SX_GPR1_FEC_CLOCK_PAD_DIR_MASK is set
+ *  - bit 1 in field IMX6SX_GPR1_FEC_CLOCK_MUX_SEL_MASK unset
+ * It seems to be a silicon bug that in this configuration ENET1_TX reference
+ * clock isn't provided automatically.  According to i.MX6SX reference manual
+ * (IOMUXC_GPR_GPR1 field descriptions: ENET1_CLK_SEL, Rev. 0 from 2/2015) it
+ * should be the case.
+ * So this might have unwanted side effects for other hardware units that are
+ * also connected to that pin and using respective function as input (e.g.
+ * UART1's DTR handling on MX6SX_PAD_ENET1_TX_CLK__UART1_DTR_B).
+ */
+#define MX6SX_PAD_ENET1_TX_CLK__ENET1_REF_CLK1                    0x0090 0x03D8 0x0760 0x1 0x1
+#define MX6SX_PAD_ENET1_TX_CLK__AUDMUX_AUD4_RXD                   0x0090 0x03D8 0x0644 0x2 0x1
+#define MX6SX_PAD_ENET1_TX_CLK__UART1_DTR_B                       0x0090 0x03D8 0x0000 0x3 0x0
+#define MX6SX_PAD_ENET1_TX_CLK__SPDIF_SR_CLK                      0x0090 0x03D8 0x0000 0x4 0x0
+#define MX6SX_PAD_ENET1_TX_CLK__GPIO2_IO_5                        0x0090 0x03D8 0x0000 0x5 0x0
+#define MX6SX_PAD_ENET1_TX_CLK__CSI2_DATA_20                      0x0090 0x03D8 0x0000 0x6 0x0
+#define MX6SX_PAD_ENET1_TX_CLK__LCDIF2_DATA_19                    0x0090 0x03D8 0x0000 0x7 0x0
+#define MX6SX_PAD_ENET1_TX_CLK__VDEC_DEBUG_34                     0x0090 0x03D8 0x0000 0x8 0x0
+#define MX6SX_PAD_ENET1_TX_CLK__PCIE_CTRL_DEBUG_28                0x0090 0x03D8 0x0000 0x9 0x0
+#define MX6SX_PAD_ENET2_COL__ENET2_COL                            0x0094 0x03DC 0x0000 0x0 0x0
+#define MX6SX_PAD_ENET2_COL__ENET1_MDC                            0x0094 0x03DC 0x0000 0x1 0x0
+#define MX6SX_PAD_ENET2_COL__AUDMUX_AUD4_RXC                      0x0094 0x03DC 0x064C 0x2 0x1
+#define MX6SX_PAD_ENET2_COL__UART1_RX                             0x0094 0x03DC 0x0830 0x3 0x2
+#define MX6SX_PAD_ENET2_COL__UART1_TX                             0x0094 0x03DC 0x0000 0x3 0x0
+#define MX6SX_PAD_ENET2_COL__SPDIF_IN                             0x0094 0x03DC 0x0824 0x4 0x3
+#define MX6SX_PAD_ENET2_COL__GPIO2_IO_6                           0x0094 0x03DC 0x0000 0x5 0x0
+#define MX6SX_PAD_ENET2_COL__ANATOP_OTG1_ID                       0x0094 0x03DC 0x0624 0x6 0x1
+#define MX6SX_PAD_ENET2_COL__LCDIF2_DATA_20                       0x0094 0x03DC 0x0000 0x7 0x0
+#define MX6SX_PAD_ENET2_COL__VDEC_DEBUG_33                        0x0094 0x03DC 0x0000 0x8 0x0
+#define MX6SX_PAD_ENET2_COL__PCIE_CTRL_DEBUG_27                   0x0094 0x03DC 0x0000 0x9 0x0
+#define MX6SX_PAD_ENET2_CRS__ENET2_CRS                            0x0098 0x03E0 0x0000 0x0 0x0
+#define MX6SX_PAD_ENET2_CRS__ENET1_MDIO                           0x0098 0x03E0 0x0764 0x1 0x2
+#define MX6SX_PAD_ENET2_CRS__AUDMUX_AUD4_RXFS                     0x0098 0x03E0 0x0650 0x2 0x1
+#define MX6SX_PAD_ENET2_CRS__UART1_RX                             0x0098 0x03E0 0x0830 0x3 0x3
+#define MX6SX_PAD_ENET2_CRS__UART1_TX                             0x0098 0x03E0 0x0000 0x3 0x0
+#define MX6SX_PAD_ENET2_CRS__MLB_SIG                              0x0098 0x03E0 0x07F0 0x4 0x1
+#define MX6SX_PAD_ENET2_CRS__GPIO2_IO_7                           0x0098 0x03E0 0x0000 0x5 0x0
+#define MX6SX_PAD_ENET2_CRS__ANATOP_OTG2_ID                       0x0098 0x03E0 0x0628 0x6 0x1
+#define MX6SX_PAD_ENET2_CRS__LCDIF2_DATA_21                       0x0098 0x03E0 0x0000 0x7 0x0
+#define MX6SX_PAD_ENET2_CRS__VDEC_DEBUG_32                        0x0098 0x03E0 0x0000 0x8 0x0
+#define MX6SX_PAD_ENET2_CRS__PCIE_CTRL_DEBUG_26                   0x0098 0x03E0 0x0000 0x9 0x0
+#define MX6SX_PAD_ENET2_RX_CLK__ENET2_RX_CLK                      0x009C 0x03E4 0x0774 0x0 0x0
+#define MX6SX_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M                 0x009C 0x03E4 0x0000 0x1 0x0
+#define MX6SX_PAD_ENET2_RX_CLK__I2C3_SCL                          0x009C 0x03E4 0x07B8 0x2 0x1
+#define MX6SX_PAD_ENET2_RX_CLK__UART1_RTS_B                       0x009C 0x03E4 0x082C 0x3 0x2
+#define MX6SX_PAD_ENET2_RX_CLK__UART1_CTS_B                       0x009C 0x03E4 0x0000 0x3 0x0
+#define MX6SX_PAD_ENET2_RX_CLK__MLB_DATA                          0x009C 0x03E4 0x07EC 0x4 0x1
+#define MX6SX_PAD_ENET2_RX_CLK__GPIO2_IO_8                        0x009C 0x03E4 0x0000 0x5 0x0
+#define MX6SX_PAD_ENET2_RX_CLK__USB_OTG2_OC                       0x009C 0x03E4 0x085C 0x6 0x1
+#define MX6SX_PAD_ENET2_RX_CLK__LCDIF2_DATA_22                    0x009C 0x03E4 0x0000 0x7 0x0
+#define MX6SX_PAD_ENET2_RX_CLK__VDEC_DEBUG_31                     0x009C 0x03E4 0x0000 0x8 0x0
+#define MX6SX_PAD_ENET2_RX_CLK__PCIE_CTRL_DEBUG_25                0x009C 0x03E4 0x0000 0x9 0x0
+#define MX6SX_PAD_ENET2_TX_CLK__ENET2_TX_CLK                      0x00A0 0x03E8 0x0000 0x0 0x0
+#define MX6SX_PAD_ENET2_TX_CLK__ENET2_REF_CLK2                    0x00A0 0x03E8 0x076C 0x1 0x1
+#define MX6SX_PAD_ENET2_TX_CLK__I2C3_SDA                          0x00A0 0x03E8 0x07BC 0x2 0x1
+#define MX6SX_PAD_ENET2_TX_CLK__UART1_CTS_B                       0x00A0 0x03E8 0x0000 0x3 0x0
+#define MX6SX_PAD_ENET2_TX_CLK__UART1_RTS_B                       0x00A0 0x03E8 0x082C 0x3 0x3
+#define MX6SX_PAD_ENET2_TX_CLK__MLB_CLK                           0x00A0 0x03E8 0x07E8 0x4 0x1
+#define MX6SX_PAD_ENET2_TX_CLK__GPIO2_IO_9                        0x00A0 0x03E8 0x0000 0x5 0x0
+#define MX6SX_PAD_ENET2_TX_CLK__USB_OTG2_PWR                      0x00A0 0x03E8 0x0000 0x6 0x0
+#define MX6SX_PAD_ENET2_TX_CLK__LCDIF2_DATA_23                    0x00A0 0x03E8 0x0000 0x7 0x0
+#define MX6SX_PAD_ENET2_TX_CLK__VDEC_DEBUG_30                     0x00A0 0x03E8 0x0000 0x8 0x0
+#define MX6SX_PAD_ENET2_TX_CLK__PCIE_CTRL_DEBUG_24                0x00A0 0x03E8 0x0000 0x9 0x0
+#define MX6SX_PAD_KEY_COL0__KPP_COL_0                             0x00A4 0x03EC 0x0000 0x0 0x0
+#define MX6SX_PAD_KEY_COL0__USDHC3_CD_B                           0x00A4 0x03EC 0x0000 0x1 0x0
+#define MX6SX_PAD_KEY_COL0__UART6_RTS_B                           0x00A4 0x03EC 0x0854 0x2 0x2
+#define MX6SX_PAD_KEY_COL0__UART6_CTS_B                           0x00A4 0x03EC 0x0000 0x2 0x0
+#define MX6SX_PAD_KEY_COL0__ECSPI1_SCLK                           0x00A4 0x03EC 0x0710 0x3 0x0
+#define MX6SX_PAD_KEY_COL0__AUDMUX_AUD5_TXC                       0x00A4 0x03EC 0x066C 0x4 0x0
+#define MX6SX_PAD_KEY_COL0__GPIO2_IO_10                           0x00A4 0x03EC 0x0000 0x5 0x0
+#define MX6SX_PAD_KEY_COL0__SDMA_EXT_EVENT_1                      0x00A4 0x03EC 0x0820 0x6 0x1
+#define MX6SX_PAD_KEY_COL0__SAI2_TX_BCLK                          0x00A4 0x03EC 0x0814 0x7 0x0
+#define MX6SX_PAD_KEY_COL0__VADC_DATA_0                           0x00A4 0x03EC 0x0000 0x8 0x0
+#define MX6SX_PAD_KEY_COL1__KPP_COL_1                             0x00A8 0x03F0 0x0000 0x0 0x0
+#define MX6SX_PAD_KEY_COL1__USDHC3_RESET_B                        0x00A8 0x03F0 0x0000 0x1 0x0
+#define MX6SX_PAD_KEY_COL1__UART6_RX                              0x00A8 0x03F0 0x0858 0x2 0x2
+#define MX6SX_PAD_KEY_COL1__UART6_TX                              0x00A8 0x03F0 0x0000 0x2 0x0
+#define MX6SX_PAD_KEY_COL1__ECSPI1_MISO                           0x00A8 0x03F0 0x0714 0x3 0x0
+#define MX6SX_PAD_KEY_COL1__AUDMUX_AUD5_TXFS                      0x00A8 0x03F0 0x0670 0x4 0x0
+#define MX6SX_PAD_KEY_COL1__GPIO2_IO_11                           0x00A8 0x03F0 0x0000 0x5 0x0
+#define MX6SX_PAD_KEY_COL1__USDHC3_RESET                          0x00A8 0x03F0 0x0000 0x6 0x0
+#define MX6SX_PAD_KEY_COL1__SAI2_TX_SYNC                          0x00A8 0x03F0 0x0818 0x7 0x0
+#define MX6SX_PAD_KEY_COL2__KPP_COL_2                             0x00AC 0x03F4 0x0000 0x0 0x0
+#define MX6SX_PAD_KEY_COL2__USDHC4_CD_B                           0x00AC 0x03F4 0x0874 0x1 0x1
+#define MX6SX_PAD_KEY_COL2__UART5_RTS_B                           0x00AC 0x03F4 0x084C 0x2 0x2
+#define MX6SX_PAD_KEY_COL2__UART5_CTS_B                           0x00AC 0x03F4 0x0000 0x2 0x0
+#define MX6SX_PAD_KEY_COL2__CAN1_TX                               0x00AC 0x03F4 0x0000 0x3 0x0
+#define MX6SX_PAD_KEY_COL2__CANFD_TX1                             0x00AC 0x03F4 0x0000 0x4 0x0
+#define MX6SX_PAD_KEY_COL2__GPIO2_IO_12                           0x00AC 0x03F4 0x0000 0x5 0x0
+#define MX6SX_PAD_KEY_COL2__WEIM_DATA_30                          0x00AC 0x03F4 0x0000 0x6 0x0
+#define MX6SX_PAD_KEY_COL2__ECSPI1_RDY                            0x00AC 0x03F4 0x0000 0x7 0x0
+#define MX6SX_PAD_KEY_COL3__KPP_COL_3                             0x00B0 0x03F8 0x0000 0x0 0x0
+#define MX6SX_PAD_KEY_COL3__USDHC4_LCTL                           0x00B0 0x03F8 0x0000 0x1 0x0
+#define MX6SX_PAD_KEY_COL3__UART5_RX                              0x00B0 0x03F8 0x0850 0x2 0x2
+#define MX6SX_PAD_KEY_COL3__UART5_TX                              0x00B0 0x03F8 0x0000 0x2 0x0
+#define MX6SX_PAD_KEY_COL3__CAN2_TX                               0x00B0 0x03F8 0x0000 0x3 0x0
+#define MX6SX_PAD_KEY_COL3__CANFD_TX2                             0x00B0 0x03F8 0x0000 0x4 0x0
+#define MX6SX_PAD_KEY_COL3__GPIO2_IO_13                           0x00B0 0x03F8 0x0000 0x5 0x0
+#define MX6SX_PAD_KEY_COL3__WEIM_DATA_28                          0x00B0 0x03F8 0x0000 0x6 0x0
+#define MX6SX_PAD_KEY_COL3__ECSPI1_SS2                            0x00B0 0x03F8 0x0000 0x7 0x0
+#define MX6SX_PAD_KEY_COL4__KPP_COL_4                             0x00B4 0x03FC 0x0000 0x0 0x0
+#define MX6SX_PAD_KEY_COL4__ENET2_MDC                             0x00B4 0x03FC 0x0000 0x1 0x0
+#define MX6SX_PAD_KEY_COL4__I2C3_SCL                              0x00B4 0x03FC 0x07B8 0x2 0x2
+#define MX6SX_PAD_KEY_COL4__USDHC2_LCTL                           0x00B4 0x03FC 0x0000 0x3 0x0
+#define MX6SX_PAD_KEY_COL4__AUDMUX_AUD5_RXC                       0x00B4 0x03FC 0x0664 0x4 0x0
+#define MX6SX_PAD_KEY_COL4__GPIO2_IO_14                           0x00B4 0x03FC 0x0000 0x5 0x0
+#define MX6SX_PAD_KEY_COL4__WEIM_CRE                              0x00B4 0x03FC 0x0000 0x6 0x0
+#define MX6SX_PAD_KEY_COL4__SAI2_RX_BCLK                          0x00B4 0x03FC 0x0808 0x7 0x0
+#define MX6SX_PAD_KEY_ROW0__KPP_ROW_0                             0x00B8 0x0400 0x0000 0x0 0x0
+#define MX6SX_PAD_KEY_ROW0__USDHC3_WP                             0x00B8 0x0400 0x0000 0x1 0x0
+#define MX6SX_PAD_KEY_ROW0__UART6_CTS_B                           0x00B8 0x0400 0x0000 0x2 0x0
+#define MX6SX_PAD_KEY_ROW0__UART6_RTS_B                           0x00B8 0x0400 0x0854 0x2 0x3
+#define MX6SX_PAD_KEY_ROW0__ECSPI1_MOSI                           0x00B8 0x0400 0x0718 0x3 0x0
+#define MX6SX_PAD_KEY_ROW0__AUDMUX_AUD5_TXD                       0x00B8 0x0400 0x0660 0x4 0x0
+#define MX6SX_PAD_KEY_ROW0__GPIO2_IO_15                           0x00B8 0x0400 0x0000 0x5 0x0
+#define MX6SX_PAD_KEY_ROW0__SDMA_EXT_EVENT_0                      0x00B8 0x0400 0x081C 0x6 0x1
+#define MX6SX_PAD_KEY_ROW0__SAI2_TX_DATA_0                        0x00B8 0x0400 0x0000 0x7 0x0
+#define MX6SX_PAD_KEY_ROW0__GPU_IDLE                              0x00B8 0x0400 0x0000 0x8 0x0
+#define MX6SX_PAD_KEY_ROW1__KPP_ROW_1                             0x00BC 0x0404 0x0000 0x0 0x0
+#define MX6SX_PAD_KEY_ROW1__USDHC4_VSELECT                        0x00BC 0x0404 0x0000 0x1 0x0
+#define MX6SX_PAD_KEY_ROW1__UART6_RX                              0x00BC 0x0404 0x0858 0x2 0x3
+#define MX6SX_PAD_KEY_ROW1__UART6_TX                              0x00BC 0x0404 0x0000 0x2 0x0
+#define MX6SX_PAD_KEY_ROW1__ECSPI1_SS0                            0x00BC 0x0404 0x071C 0x3 0x0
+#define MX6SX_PAD_KEY_ROW1__AUDMUX_AUD5_RXD                       0x00BC 0x0404 0x065C 0x4 0x0
+#define MX6SX_PAD_KEY_ROW1__GPIO2_IO_16                           0x00BC 0x0404 0x0000 0x5 0x0
+#define MX6SX_PAD_KEY_ROW1__WEIM_DATA_31                          0x00BC 0x0404 0x0000 0x6 0x0
+#define MX6SX_PAD_KEY_ROW1__SAI2_RX_DATA_0                        0x00BC 0x0404 0x080C 0x7 0x0
+#define MX6SX_PAD_KEY_ROW1__M4_NMI                                0x00BC 0x0404 0x0000 0x8 0x0
+#define MX6SX_PAD_KEY_ROW2__KPP_ROW_2                             0x00C0 0x0408 0x0000 0x0 0x0
+#define MX6SX_PAD_KEY_ROW2__USDHC4_WP                             0x00C0 0x0408 0x0878 0x1 0x1
+#define MX6SX_PAD_KEY_ROW2__UART5_CTS_B                           0x00C0 0x0408 0x0000 0x2 0x0
+#define MX6SX_PAD_KEY_ROW2__UART5_RTS_B                           0x00C0 0x0408 0x084C 0x2 0x3
+#define MX6SX_PAD_KEY_ROW2__CAN1_RX                               0x00C0 0x0408 0x068C 0x3 0x1
+#define MX6SX_PAD_KEY_ROW2__CANFD_RX1                             0x00C0 0x0408 0x0694 0x4 0x1
+#define MX6SX_PAD_KEY_ROW2__GPIO2_IO_17                           0x00C0 0x0408 0x0000 0x5 0x0
+#define MX6SX_PAD_KEY_ROW2__WEIM_DATA_29                          0x00C0 0x0408 0x0000 0x6 0x0
+#define MX6SX_PAD_KEY_ROW2__ECSPI1_SS3                            0x00C0 0x0408 0x0000 0x7 0x0
+#define MX6SX_PAD_KEY_ROW3__KPP_ROW_3                             0x00C4 0x040C 0x0000 0x0 0x0
+#define MX6SX_PAD_KEY_ROW3__USDHC3_LCTL                           0x00C4 0x040C 0x0000 0x1 0x0
+#define MX6SX_PAD_KEY_ROW3__UART5_RX                              0x00C4 0x040C 0x0850 0x2 0x3
+#define MX6SX_PAD_KEY_ROW3__UART5_TX                              0x00C4 0x040C 0x0000 0x2 0x0
+#define MX6SX_PAD_KEY_ROW3__CAN2_RX                               0x00C4 0x040C 0x0690 0x3 0x1
+#define MX6SX_PAD_KEY_ROW3__CANFD_RX2                             0x00C4 0x040C 0x0698 0x4 0x1
+#define MX6SX_PAD_KEY_ROW3__GPIO2_IO_18                           0x00C4 0x040C 0x0000 0x5 0x0
+#define MX6SX_PAD_KEY_ROW3__WEIM_DTACK_B                          0x00C4 0x040C 0x0000 0x6 0x0
+#define MX6SX_PAD_KEY_ROW3__ECSPI1_SS1                            0x00C4 0x040C 0x0000 0x7 0x0
+#define MX6SX_PAD_KEY_ROW4__KPP_ROW_4                             0x00C8 0x0410 0x0000 0x0 0x0
+#define MX6SX_PAD_KEY_ROW4__ENET2_MDIO                            0x00C8 0x0410 0x0770 0x1 0x3
+#define MX6SX_PAD_KEY_ROW4__I2C3_SDA                              0x00C8 0x0410 0x07BC 0x2 0x2
+#define MX6SX_PAD_KEY_ROW4__USDHC1_LCTL                           0x00C8 0x0410 0x0000 0x3 0x0
+#define MX6SX_PAD_KEY_ROW4__AUDMUX_AUD5_RXFS                      0x00C8 0x0410 0x0668 0x4 0x0
+#define MX6SX_PAD_KEY_ROW4__GPIO2_IO_19                           0x00C8 0x0410 0x0000 0x5 0x0
+#define MX6SX_PAD_KEY_ROW4__WEIM_ACLK_FREERUN                     0x00C8 0x0410 0x0000 0x6 0x0
+#define MX6SX_PAD_KEY_ROW4__SAI2_RX_SYNC                          0x00C8 0x0410 0x0810 0x7 0x0
+#define MX6SX_PAD_LCD1_CLK__LCDIF1_CLK                            0x00CC 0x0414 0x0000 0x0 0x0
+#define MX6SX_PAD_LCD1_CLK__LCDIF1_WR_RWN                         0x00CC 0x0414 0x0000 0x1 0x0
+#define MX6SX_PAD_LCD1_CLK__AUDMUX_AUD3_RXC                       0x00CC 0x0414 0x0634 0x2 0x1
+#define MX6SX_PAD_LCD1_CLK__ENET1_1588_EVENT2_IN                  0x00CC 0x0414 0x0000 0x3 0x0
+#define MX6SX_PAD_LCD1_CLK__CSI1_DATA_16                          0x00CC 0x0414 0x06DC 0x4 0x0
+#define MX6SX_PAD_LCD1_CLK__GPIO3_IO_0                            0x00CC 0x0414 0x0000 0x5 0x0
+#define MX6SX_PAD_LCD1_CLK__USDHC1_WP                             0x00CC 0x0414 0x0868 0x6 0x0
+#define MX6SX_PAD_LCD1_CLK__SIM_M_HADDR_16                        0x00CC 0x0414 0x0000 0x7 0x0
+#define MX6SX_PAD_LCD1_CLK__VADC_TEST_0                           0x00CC 0x0414 0x0000 0x8 0x0
+#define MX6SX_PAD_LCD1_CLK__MMDC_DEBUG_0                          0x00CC 0x0414 0x0000 0x9 0x0
+#define MX6SX_PAD_LCD1_DATA00__LCDIF1_DATA_0                      0x00D0 0x0418 0x0000 0x0 0x0
+#define MX6SX_PAD_LCD1_DATA00__WEIM_CS1_B                         0x00D0 0x0418 0x0000 0x1 0x0
+#define MX6SX_PAD_LCD1_DATA00__M4_TRACE_0                         0x00D0 0x0418 0x0000 0x2 0x0
+#define MX6SX_PAD_LCD1_DATA00__KITTEN_TRACE_0                     0x00D0 0x0418 0x0000 0x3 0x0
+#define MX6SX_PAD_LCD1_DATA00__CSI1_DATA_20                       0x00D0 0x0418 0x06EC 0x4 0x0
+#define MX6SX_PAD_LCD1_DATA00__GPIO3_IO_1                         0x00D0 0x0418 0x0000 0x5 0x0
+#define MX6SX_PAD_LCD1_DATA00__SRC_BT_CFG_0                       0x00D0 0x0418 0x0000 0x6 0x0
+#define MX6SX_PAD_LCD1_DATA00__SIM_M_HADDR_21                     0x00D0 0x0418 0x0000 0x7 0x0
+#define MX6SX_PAD_LCD1_DATA00__VADC_TEST_5                        0x00D0 0x0418 0x0000 0x8 0x0
+#define MX6SX_PAD_LCD1_DATA00__MMDC_DEBUG_5                       0x00D0 0x0418 0x0000 0x9 0x0
+#define MX6SX_PAD_LCD1_DATA01__LCDIF1_DATA_1                      0x00D4 0x041C 0x0000 0x0 0x0
+#define MX6SX_PAD_LCD1_DATA01__WEIM_CS2_B                         0x00D4 0x041C 0x0000 0x1 0x0
+#define MX6SX_PAD_LCD1_DATA01__M4_TRACE_1                         0x00D4 0x041C 0x0000 0x2 0x0
+#define MX6SX_PAD_LCD1_DATA01__KITTEN_TRACE_1                     0x00D4 0x041C 0x0000 0x3 0x0
+#define MX6SX_PAD_LCD1_DATA01__CSI1_DATA_21                       0x00D4 0x041C 0x06F0 0x4 0x0
+#define MX6SX_PAD_LCD1_DATA01__GPIO3_IO_2                         0x00D4 0x041C 0x0000 0x5 0x0
+#define MX6SX_PAD_LCD1_DATA01__SRC_BT_CFG_1                       0x00D4 0x041C 0x0000 0x6 0x0
+#define MX6SX_PAD_LCD1_DATA01__SIM_M_HADDR_22                     0x00D4 0x041C 0x0000 0x7 0x0
+#define MX6SX_PAD_LCD1_DATA01__VADC_TEST_6                        0x00D4 0x041C 0x0000 0x8 0x0
+#define MX6SX_PAD_LCD1_DATA01__MMDC_DEBUG_6                       0x00D4 0x041C 0x0000 0x9 0x0
+#define MX6SX_PAD_LCD1_DATA02__LCDIF1_DATA_2                      0x00D8 0x0420 0x0000 0x0 0x0
+#define MX6SX_PAD_LCD1_DATA02__WEIM_CS3_B                         0x00D8 0x0420 0x0000 0x1 0x0
+#define MX6SX_PAD_LCD1_DATA02__M4_TRACE_2                         0x00D8 0x0420 0x0000 0x2 0x0
+#define MX6SX_PAD_LCD1_DATA02__KITTEN_TRACE_2                     0x00D8 0x0420 0x0000 0x3 0x0
+#define MX6SX_PAD_LCD1_DATA02__CSI1_DATA_22                       0x00D8 0x0420 0x06F4 0x4 0x0
+#define MX6SX_PAD_LCD1_DATA02__GPIO3_IO_3                         0x00D8 0x0420 0x0000 0x5 0x0
+#define MX6SX_PAD_LCD1_DATA02__SRC_BT_CFG_2                       0x00D8 0x0420 0x0000 0x6 0x0
+#define MX6SX_PAD_LCD1_DATA02__SIM_M_HADDR_23                     0x00D8 0x0420 0x0000 0x7 0x0
+#define MX6SX_PAD_LCD1_DATA02__VADC_TEST_7                        0x00D8 0x0420 0x0000 0x8 0x0
+#define MX6SX_PAD_LCD1_DATA02__MMDC_DEBUG_7                       0x00D8 0x0420 0x0000 0x9 0x0
+#define MX6SX_PAD_LCD1_DATA03__LCDIF1_DATA_3                      0x00DC 0x0424 0x0000 0x0 0x0
+#define MX6SX_PAD_LCD1_DATA03__WEIM_ADDR_24                       0x00DC 0x0424 0x0000 0x1 0x0
+#define MX6SX_PAD_LCD1_DATA03__M4_TRACE_3                         0x00DC 0x0424 0x0000 0x2 0x0
+#define MX6SX_PAD_LCD1_DATA03__KITTEN_TRACE_3                     0x00DC 0x0424 0x0000 0x3 0x0
+#define MX6SX_PAD_LCD1_DATA03__CSI1_DATA_23                       0x00DC 0x0424 0x06F8 0x4 0x0
+#define MX6SX_PAD_LCD1_DATA03__GPIO3_IO_4                         0x00DC 0x0424 0x0000 0x5 0x0
+#define MX6SX_PAD_LCD1_DATA03__SRC_BT_CFG_3                       0x00DC 0x0424 0x0000 0x6 0x0
+#define MX6SX_PAD_LCD1_DATA03__SIM_M_HADDR_24                     0x00DC 0x0424 0x0000 0x7 0x0
+#define MX6SX_PAD_LCD1_DATA03__VADC_TEST_8                        0x00DC 0x0424 0x0000 0x8 0x0
+#define MX6SX_PAD_LCD1_DATA03__MMDC_DEBUG_8                       0x00DC 0x0424 0x0000 0x9 0x0
+#define MX6SX_PAD_LCD1_DATA04__LCDIF1_DATA_4                      0x00E0 0x0428 0x0000 0x0 0x0
+#define MX6SX_PAD_LCD1_DATA04__WEIM_ADDR_25                       0x00E0 0x0428 0x0000 0x1 0x0
+#define MX6SX_PAD_LCD1_DATA04__KITTEN_TRACE_4                     0x00E0 0x0428 0x0000 0x3 0x0
+#define MX6SX_PAD_LCD1_DATA04__CSI1_VSYNC                         0x00E0 0x0428 0x0708 0x4 0x1
+#define MX6SX_PAD_LCD1_DATA04__GPIO3_IO_5                         0x00E0 0x0428 0x0000 0x5 0x0
+#define MX6SX_PAD_LCD1_DATA04__SRC_BT_CFG_4                       0x00E0 0x0428 0x0000 0x6 0x0
+#define MX6SX_PAD_LCD1_DATA04__SIM_M_HADDR_25                     0x00E0 0x0428 0x0000 0x7 0x0
+#define MX6SX_PAD_LCD1_DATA04__VADC_TEST_9                        0x00E0 0x0428 0x0000 0x8 0x0
+#define MX6SX_PAD_LCD1_DATA04__MMDC_DEBUG_9                       0x00E0 0x0428 0x0000 0x9 0x0
+#define MX6SX_PAD_LCD1_DATA05__LCDIF1_DATA_5                      0x00E4 0x042C 0x0000 0x0 0x0
+#define MX6SX_PAD_LCD1_DATA05__WEIM_ADDR_26                       0x00E4 0x042C 0x0000 0x1 0x0
+#define MX6SX_PAD_LCD1_DATA05__KITTEN_TRACE_5                     0x00E4 0x042C 0x0000 0x3 0x0
+#define MX6SX_PAD_LCD1_DATA05__CSI1_HSYNC                         0x00E4 0x042C 0x0700 0x4 0x1
+#define MX6SX_PAD_LCD1_DATA05__GPIO3_IO_6                         0x00E4 0x042C 0x0000 0x5 0x0
+#define MX6SX_PAD_LCD1_DATA05__SRC_BT_CFG_5                       0x00E4 0x042C 0x0000 0x6 0x0
+#define MX6SX_PAD_LCD1_DATA05__SIM_M_HADDR_26                     0x00E4 0x042C 0x0000 0x7 0x0
+#define MX6SX_PAD_LCD1_DATA05__VADC_TEST_10                       0x00E4 0x042C 0x0000 0x8 0x0
+#define MX6SX_PAD_LCD1_DATA05__MMDC_DEBUG_10                      0x00E4 0x042C 0x0000 0x9 0x0
+#define MX6SX_PAD_LCD1_DATA06__LCDIF1_DATA_6                      0x00E8 0x0430 0x0000 0x0 0x0
+#define MX6SX_PAD_LCD1_DATA06__WEIM_EB_B_2                        0x00E8 0x0430 0x0000 0x1 0x0
+#define MX6SX_PAD_LCD1_DATA06__KITTEN_TRACE_6                     0x00E8 0x0430 0x0000 0x3 0x0
+#define MX6SX_PAD_LCD1_DATA06__CSI1_PIXCLK                        0x00E8 0x0430 0x0704 0x4 0x1
+#define MX6SX_PAD_LCD1_DATA06__GPIO3_IO_7                         0x00E8 0x0430 0x0000 0x5 0x0
+#define MX6SX_PAD_LCD1_DATA06__SRC_BT_CFG_6                       0x00E8 0x0430 0x0000 0x6 0x0
+#define MX6SX_PAD_LCD1_DATA06__SIM_M_HADDR_27                     0x00E8 0x0430 0x0000 0x7 0x0
+#define MX6SX_PAD_LCD1_DATA06__VADC_TEST_11                       0x00E8 0x0430 0x0000 0x8 0x0
+#define MX6SX_PAD_LCD1_DATA06__MMDC_DEBUG_11                      0x00E8 0x0430 0x0000 0x9 0x0
+#define MX6SX_PAD_LCD1_DATA07__LCDIF1_DATA_7                      0x00EC 0x0434 0x0000 0x0 0x0
+#define MX6SX_PAD_LCD1_DATA07__WEIM_EB_B_3                        0x00EC 0x0434 0x0000 0x1 0x0
+#define MX6SX_PAD_LCD1_DATA07__KITTEN_TRACE_7                     0x00EC 0x0434 0x0000 0x3 0x0
+#define MX6SX_PAD_LCD1_DATA07__CSI1_MCLK                          0x00EC 0x0434 0x0000 0x4 0x0
+#define MX6SX_PAD_LCD1_DATA07__GPIO3_IO_8                         0x00EC 0x0434 0x0000 0x5 0x0
+#define MX6SX_PAD_LCD1_DATA07__SRC_BT_CFG_7                       0x00EC 0x0434 0x0000 0x6 0x0
+#define MX6SX_PAD_LCD1_DATA07__SIM_M_HADDR_28                     0x00EC 0x0434 0x0000 0x7 0x0
+#define MX6SX_PAD_LCD1_DATA07__VADC_TEST_12                       0x00EC 0x0434 0x0000 0x8 0x0
+#define MX6SX_PAD_LCD1_DATA07__MMDC_DEBUG_12                      0x00EC 0x0434 0x0000 0x9 0x0
+#define MX6SX_PAD_LCD1_DATA08__LCDIF1_DATA_8                      0x00F0 0x0438 0x0000 0x0 0x0
+#define MX6SX_PAD_LCD1_DATA08__WEIM_AD_8                          0x00F0 0x0438 0x0000 0x1 0x0
+#define MX6SX_PAD_LCD1_DATA08__KITTEN_TRACE_8                     0x00F0 0x0438 0x0000 0x3 0x0
+#define MX6SX_PAD_LCD1_DATA08__CSI1_DATA_9                        0x00F0 0x0438 0x06C4 0x4 0x1
+#define MX6SX_PAD_LCD1_DATA08__GPIO3_IO_9                         0x00F0 0x0438 0x0000 0x5 0x0
+#define MX6SX_PAD_LCD1_DATA08__SRC_BT_CFG_8                       0x00F0 0x0438 0x0000 0x6 0x0
+#define MX6SX_PAD_LCD1_DATA08__SIM_M_HADDR_29                     0x00F0 0x0438 0x0000 0x7 0x0
+#define MX6SX_PAD_LCD1_DATA08__VADC_TEST_13                       0x00F0 0x0438 0x0000 0x8 0x0
+#define MX6SX_PAD_LCD1_DATA08__MMDC_DEBUG_13                      0x00F0 0x0438 0x0000 0x9 0x0
+#define MX6SX_PAD_LCD1_DATA09__LCDIF1_DATA_9                      0x00F4 0x043C 0x0000 0x0 0x0
+#define MX6SX_PAD_LCD1_DATA09__WEIM_AD_9                          0x00F4 0x043C 0x0000 0x1 0x0
+#define MX6SX_PAD_LCD1_DATA09__KITTEN_TRACE_9                     0x00F4 0x043C 0x0000 0x3 0x0
+#define MX6SX_PAD_LCD1_DATA09__CSI1_DATA_8                        0x00F4 0x043C 0x06C0 0x4 0x1
+#define MX6SX_PAD_LCD1_DATA09__GPIO3_IO_10                        0x00F4 0x043C 0x0000 0x5 0x0
+#define MX6SX_PAD_LCD1_DATA09__SRC_BT_CFG_9                       0x00F4 0x043C 0x0000 0x6 0x0
+#define MX6SX_PAD_LCD1_DATA09__SIM_M_HADDR_30                     0x00F4 0x043C 0x0000 0x7 0x0
+#define MX6SX_PAD_LCD1_DATA09__VADC_TEST_14                       0x00F4 0x043C 0x0000 0x8 0x0
+#define MX6SX_PAD_LCD1_DATA09__MMDC_DEBUG_14                      0x00F4 0x043C 0x0000 0x9 0x0
+#define MX6SX_PAD_LCD1_DATA10__LCDIF1_DATA_10                     0x00F8 0x0440 0x0000 0x0 0x0
+#define MX6SX_PAD_LCD1_DATA10__WEIM_AD_10                         0x00F8 0x0440 0x0000 0x1 0x0
+#define MX6SX_PAD_LCD1_DATA10__KITTEN_TRACE_10                    0x00F8 0x0440 0x0000 0x3 0x0
+#define MX6SX_PAD_LCD1_DATA10__CSI1_DATA_7                        0x00F8 0x0440 0x06BC 0x4 0x1
+#define MX6SX_PAD_LCD1_DATA10__GPIO3_IO_11                        0x00F8 0x0440 0x0000 0x5 0x0
+#define MX6SX_PAD_LCD1_DATA10__SRC_BT_CFG_10                      0x00F8 0x0440 0x0000 0x6 0x0
+#define MX6SX_PAD_LCD1_DATA10__SIM_M_HADDR_31                     0x00F8 0x0440 0x0000 0x7 0x0
+#define MX6SX_PAD_LCD1_DATA10__VADC_TEST_15                       0x00F8 0x0440 0x0000 0x8 0x0
+#define MX6SX_PAD_LCD1_DATA10__MMDC_DEBUG_15                      0x00F8 0x0440 0x0000 0x9 0x0
+#define MX6SX_PAD_LCD1_DATA11__LCDIF1_DATA_11                     0x00FC 0x0444 0x0000 0x0 0x0
+#define MX6SX_PAD_LCD1_DATA11__WEIM_AD_11                         0x00FC 0x0444 0x0000 0x1 0x0
+#define MX6SX_PAD_LCD1_DATA11__KITTEN_TRACE_11                    0x00FC 0x0444 0x0000 0x3 0x0
+#define MX6SX_PAD_LCD1_DATA11__CSI1_DATA_6                        0x00FC 0x0444 0x06B8 0x4 0x1
+#define MX6SX_PAD_LCD1_DATA11__GPIO3_IO_12                        0x00FC 0x0444 0x0000 0x5 0x0
+#define MX6SX_PAD_LCD1_DATA11__SRC_BT_CFG_11                      0x00FC 0x0444 0x0000 0x6 0x0
+#define MX6SX_PAD_LCD1_DATA11__SIM_M_HBURST_0                     0x00FC 0x0444 0x0000 0x7 0x0
+#define MX6SX_PAD_LCD1_DATA11__VADC_TEST_16                       0x00FC 0x0444 0x0000 0x8 0x0
+#define MX6SX_PAD_LCD1_DATA11__MMDC_DEBUG_16                      0x00FC 0x0444 0x0000 0x9 0x0
+#define MX6SX_PAD_LCD1_DATA12__LCDIF1_DATA_12                     0x0100 0x0448 0x0000 0x0 0x0
+#define MX6SX_PAD_LCD1_DATA12__WEIM_AD_12                         0x0100 0x0448 0x0000 0x1 0x0
+#define MX6SX_PAD_LCD1_DATA12__KITTEN_TRACE_12                    0x0100 0x0448 0x0000 0x3 0x0
+#define MX6SX_PAD_LCD1_DATA12__CSI1_DATA_5                        0x0100 0x0448 0x06B4 0x4 0x1
+#define MX6SX_PAD_LCD1_DATA12__GPIO3_IO_13                        0x0100 0x0448 0x0000 0x5 0x0
+#define MX6SX_PAD_LCD1_DATA12__SRC_BT_CFG_12                      0x0100 0x0448 0x0000 0x6 0x0
+#define MX6SX_PAD_LCD1_DATA12__SIM_M_HBURST_1                     0x0100 0x0448 0x0000 0x7 0x0
+#define MX6SX_PAD_LCD1_DATA12__VADC_TEST_17                       0x0100 0x0448 0x0000 0x8 0x0
+#define MX6SX_PAD_LCD1_DATA12__MMDC_DEBUG_17                      0x0100 0x0448 0x0000 0x9 0x0
+#define MX6SX_PAD_LCD1_DATA13__LCDIF1_DATA_13                     0x0104 0x044C 0x0000 0x0 0x0
+#define MX6SX_PAD_LCD1_DATA13__WEIM_AD_13                         0x0104 0x044C 0x0000 0x1 0x0
+#define MX6SX_PAD_LCD1_DATA13__KITTEN_TRACE_13                    0x0104 0x044C 0x0000 0x3 0x0
+#define MX6SX_PAD_LCD1_DATA13__CSI1_DATA_4                        0x0104 0x044C 0x06B0 0x4 0x1
+#define MX6SX_PAD_LCD1_DATA13__GPIO3_IO_14                        0x0104 0x044C 0x0000 0x5 0x0
+#define MX6SX_PAD_LCD1_DATA13__SRC_BT_CFG_13                      0x0104 0x044C 0x0000 0x6 0x0
+#define MX6SX_PAD_LCD1_DATA13__SIM_M_HBURST_2                     0x0104 0x044C 0x0000 0x7 0x0
+#define MX6SX_PAD_LCD1_DATA13__VADC_TEST_18                       0x0104 0x044C 0x0000 0x8 0x0
+#define MX6SX_PAD_LCD1_DATA13__MMDC_DEBUG_18                      0x0104 0x044C 0x0000 0x9 0x0
+#define MX6SX_PAD_LCD1_DATA14__LCDIF1_DATA_14                     0x0108 0x0450 0x0000 0x0 0x0
+#define MX6SX_PAD_LCD1_DATA14__WEIM_AD_14                         0x0108 0x0450 0x0000 0x1 0x0
+#define MX6SX_PAD_LCD1_DATA14__KITTEN_TRACE_14                    0x0108 0x0450 0x0000 0x3 0x0
+#define MX6SX_PAD_LCD1_DATA14__CSI1_DATA_3                        0x0108 0x0450 0x06AC 0x4 0x1
+#define MX6SX_PAD_LCD1_DATA14__GPIO3_IO_15                        0x0108 0x0450 0x0000 0x5 0x0
+#define MX6SX_PAD_LCD1_DATA14__SRC_BT_CFG_14                      0x0108 0x0450 0x0000 0x6 0x0
+#define MX6SX_PAD_LCD1_DATA14__SIM_M_HMASTLOCK                    0x0108 0x0450 0x0000 0x7 0x0
+#define MX6SX_PAD_LCD1_DATA14__VADC_TEST_19                       0x0108 0x0450 0x0000 0x8 0x0
+#define MX6SX_PAD_LCD1_DATA14__MMDC_DEBUG_19                      0x0108 0x0450 0x0000 0x9 0x0
+#define MX6SX_PAD_LCD1_DATA15__LCDIF1_DATA_15                     0x010C 0x0454 0x0000 0x0 0x0
+#define MX6SX_PAD_LCD1_DATA15__WEIM_AD_15                         0x010C 0x0454 0x0000 0x1 0x0
+#define MX6SX_PAD_LCD1_DATA15__KITTEN_TRACE_15                    0x010C 0x0454 0x0000 0x3 0x0
+#define MX6SX_PAD_LCD1_DATA15__CSI1_DATA_2                        0x010C 0x0454 0x06A8 0x4 0x1
+#define MX6SX_PAD_LCD1_DATA15__GPIO3_IO_16                        0x010C 0x0454 0x0000 0x5 0x0
+#define MX6SX_PAD_LCD1_DATA15__SRC_BT_CFG_15                      0x010C 0x0454 0x0000 0x6 0x0
+#define MX6SX_PAD_LCD1_DATA15__SIM_M_HPROT_0                      0x010C 0x0454 0x0000 0x7 0x0
+#define MX6SX_PAD_LCD1_DATA15__VDEC_DEBUG_0                       0x010C 0x0454 0x0000 0x8 0x0
+#define MX6SX_PAD_LCD1_DATA15__MMDC_DEBUG_20                      0x010C 0x0454 0x0000 0x9 0x0
+#define MX6SX_PAD_LCD1_DATA16__LCDIF1_DATA_16                     0x0110 0x0458 0x0000 0x0 0x0
+#define MX6SX_PAD_LCD1_DATA16__WEIM_ADDR_16                       0x0110 0x0458 0x0000 0x1 0x0
+#define MX6SX_PAD_LCD1_DATA16__M4_TRACE_CLK                       0x0110 0x0458 0x0000 0x2 0x0
+#define MX6SX_PAD_LCD1_DATA16__KITTEN_TRACE_CLK                   0x0110 0x0458 0x0000 0x3 0x0
+#define MX6SX_PAD_LCD1_DATA16__CSI1_DATA_1                        0x0110 0x0458 0x06A4 0x4 0x0
+#define MX6SX_PAD_LCD1_DATA16__GPIO3_IO_17                        0x0110 0x0458 0x0000 0x5 0x0
+#define MX6SX_PAD_LCD1_DATA16__SRC_BT_CFG_24                      0x0110 0x0458 0x0000 0x6 0x0
+#define MX6SX_PAD_LCD1_DATA16__SIM_M_HPROT_1                      0x0110 0x0458 0x0000 0x7 0x0
+#define MX6SX_PAD_LCD1_DATA16__VDEC_DEBUG_1                       0x0110 0x0458 0x0000 0x8 0x0
+#define MX6SX_PAD_LCD1_DATA16__MMDC_DEBUG_21                      0x0110 0x0458 0x0000 0x9 0x0
+#define MX6SX_PAD_LCD1_DATA17__LCDIF1_DATA_17                     0x0114 0x045C 0x0000 0x0 0x0
+#define MX6SX_PAD_LCD1_DATA17__WEIM_ADDR_17                       0x0114 0x045C 0x0000 0x1 0x0
+#define MX6SX_PAD_LCD1_DATA17__KITTEN_TRACE_CTL                   0x0114 0x045C 0x0000 0x3 0x0
+#define MX6SX_PAD_LCD1_DATA17__CSI1_DATA_0                        0x0114 0x045C 0x06A0 0x4 0x0
+#define MX6SX_PAD_LCD1_DATA17__GPIO3_IO_18                        0x0114 0x045C 0x0000 0x5 0x0
+#define MX6SX_PAD_LCD1_DATA17__SRC_BT_CFG_25                      0x0114 0x045C 0x0000 0x6 0x0
+#define MX6SX_PAD_LCD1_DATA17__SIM_M_HPROT_2                      0x0114 0x045C 0x0000 0x7 0x0
+#define MX6SX_PAD_LCD1_DATA17__VDEC_DEBUG_2                       0x0114 0x045C 0x0000 0x8 0x0
+#define MX6SX_PAD_LCD1_DATA17__MMDC_DEBUG_22                      0x0114 0x045C 0x0000 0x9 0x0
+#define MX6SX_PAD_LCD1_DATA18__LCDIF1_DATA_18                     0x0118 0x0460 0x0000 0x0 0x0
+#define MX6SX_PAD_LCD1_DATA18__WEIM_ADDR_18                       0x0118 0x0460 0x0000 0x1 0x0
+#define MX6SX_PAD_LCD1_DATA18__M4_EVENTO                          0x0118 0x0460 0x0000 0x2 0x0
+#define MX6SX_PAD_LCD1_DATA18__KITTEN_EVENTO                      0x0118 0x0460 0x0000 0x3 0x0
+#define MX6SX_PAD_LCD1_DATA18__CSI1_DATA_15                       0x0118 0x0460 0x06D8 0x4 0x0
+#define MX6SX_PAD_LCD1_DATA18__GPIO3_IO_19                        0x0118 0x0460 0x0000 0x5 0x0
+#define MX6SX_PAD_LCD1_DATA18__SRC_BT_CFG_26                      0x0118 0x0460 0x0000 0x6 0x0
+#define MX6SX_PAD_LCD1_DATA18__SIM_M_HPROT_3                      0x0118 0x0460 0x0000 0x7 0x0
+#define MX6SX_PAD_LCD1_DATA18__VDEC_DEBUG_3                       0x0118 0x0460 0x0000 0x8 0x0
+#define MX6SX_PAD_LCD1_DATA18__MMDC_DEBUG_23                      0x0118 0x0460 0x0000 0x9 0x0
+#define MX6SX_PAD_LCD1_DATA19__LCDIF1_DATA_19                     0x011C 0x0464 0x0000 0x0 0x0
+#define MX6SX_PAD_LCD1_DATA19__WEIM_ADDR_19                       0x011C 0x0464 0x0000 0x1 0x0
+#define MX6SX_PAD_LCD1_DATA19__M4_TRACE_SWO                       0x011C 0x0464 0x0000 0x2 0x0
+#define MX6SX_PAD_LCD1_DATA19__CSI1_DATA_14                       0x011C 0x0464 0x06D4 0x4 0x0
+#define MX6SX_PAD_LCD1_DATA19__GPIO3_IO_20                        0x011C 0x0464 0x0000 0x5 0x0
+#define MX6SX_PAD_LCD1_DATA19__SRC_BT_CFG_27                      0x011C 0x0464 0x0000 0x6 0x0
+#define MX6SX_PAD_LCD1_DATA19__SIM_M_HREADYOUT                    0x011C 0x0464 0x0000 0x7 0x0
+#define MX6SX_PAD_LCD1_DATA19__VDEC_DEBUG_4                       0x011C 0x0464 0x0000 0x8 0x0
+#define MX6SX_PAD_LCD1_DATA19__MMDC_DEBUG_24                      0x011C 0x0464 0x0000 0x9 0x0
+#define MX6SX_PAD_LCD1_DATA20__LCDIF1_DATA_20                     0x0120 0x0468 0x0000 0x0 0x0
+#define MX6SX_PAD_LCD1_DATA20__WEIM_ADDR_20                       0x0120 0x0468 0x0000 0x1 0x0
+#define MX6SX_PAD_LCD1_DATA20__PWM8_OUT                           0x0120 0x0468 0x0000 0x2 0x0
+#define MX6SX_PAD_LCD1_DATA20__ENET1_1588_EVENT2_OUT              0x0120 0x0468 0x0000 0x3 0x0
+#define MX6SX_PAD_LCD1_DATA20__CSI1_DATA_13                       0x0120 0x0468 0x06D0 0x4 0x0
+#define MX6SX_PAD_LCD1_DATA20__GPIO3_IO_21                        0x0120 0x0468 0x0000 0x5 0x0
+#define MX6SX_PAD_LCD1_DATA20__SRC_BT_CFG_28                      0x0120 0x0468 0x0000 0x6 0x0
+#define MX6SX_PAD_LCD1_DATA20__SIM_M_HRESP                        0x0120 0x0468 0x0000 0x7 0x0
+#define MX6SX_PAD_LCD1_DATA20__VDEC_DEBUG_5                       0x0120 0x0468 0x0000 0x8 0x0
+#define MX6SX_PAD_LCD1_DATA20__MMDC_DEBUG_25                      0x0120 0x0468 0x0000 0x9 0x0
+#define MX6SX_PAD_LCD1_DATA21__LCDIF1_DATA_21                     0x0124 0x046C 0x0000 0x0 0x0
+#define MX6SX_PAD_LCD1_DATA21__WEIM_ADDR_21                       0x0124 0x046C 0x0000 0x1 0x0
+#define MX6SX_PAD_LCD1_DATA21__PWM7_OUT                           0x0124 0x046C 0x0000 0x2 0x0
+#define MX6SX_PAD_LCD1_DATA21__ENET1_1588_EVENT3_OUT              0x0124 0x046C 0x0000 0x3 0x0
+#define MX6SX_PAD_LCD1_DATA21__CSI1_DATA_12                       0x0124 0x046C 0x06CC 0x4 0x0
+#define MX6SX_PAD_LCD1_DATA21__GPIO3_IO_22                        0x0124 0x046C 0x0000 0x5 0x0
+#define MX6SX_PAD_LCD1_DATA21__SRC_BT_CFG_29                      0x0124 0x046C 0x0000 0x6 0x0
+#define MX6SX_PAD_LCD1_DATA21__SIM_M_HSIZE_0                      0x0124 0x046C 0x0000 0x7 0x0
+#define MX6SX_PAD_LCD1_DATA21__VDEC_DEBUG_6                       0x0124 0x046C 0x0000 0x8 0x0
+#define MX6SX_PAD_LCD1_DATA21__MMDC_DEBUG_26                      0x0124 0x046C 0x0000 0x9 0x0
+#define MX6SX_PAD_LCD1_DATA22__LCDIF1_DATA_22                     0x0128 0x0470 0x0000 0x0 0x0
+#define MX6SX_PAD_LCD1_DATA22__WEIM_ADDR_22                       0x0128 0x0470 0x0000 0x1 0x0
+#define MX6SX_PAD_LCD1_DATA22__PWM6_OUT                           0x0128 0x0470 0x0000 0x2 0x0
+#define MX6SX_PAD_LCD1_DATA22__ENET2_1588_EVENT2_OUT              0x0128 0x0470 0x0000 0x3 0x0
+#define MX6SX_PAD_LCD1_DATA22__CSI1_DATA_11                       0x0128 0x0470 0x06C8 0x4 0x0
+#define MX6SX_PAD_LCD1_DATA22__GPIO3_IO_23                        0x0128 0x0470 0x0000 0x5 0x0
+#define MX6SX_PAD_LCD1_DATA22__SRC_BT_CFG_30                      0x0128 0x0470 0x0000 0x6 0x0
+#define MX6SX_PAD_LCD1_DATA22__SIM_M_HSIZE_1                      0x0128 0x0470 0x0000 0x7 0x0
+#define MX6SX_PAD_LCD1_DATA22__VDEC_DEBUG_7                       0x0128 0x0470 0x0000 0x8 0x0
+#define MX6SX_PAD_LCD1_DATA22__MMDC_DEBUG_27                      0x0128 0x0470 0x0000 0x9 0x0
+#define MX6SX_PAD_LCD1_DATA23__LCDIF1_DATA_23                     0x012C 0x0474 0x0000 0x0 0x0
+#define MX6SX_PAD_LCD1_DATA23__WEIM_ADDR_23                       0x012C 0x0474 0x0000 0x1 0x0
+#define MX6SX_PAD_LCD1_DATA23__PWM5_OUT                           0x012C 0x0474 0x0000 0x2 0x0
+#define MX6SX_PAD_LCD1_DATA23__ENET2_1588_EVENT3_OUT              0x012C 0x0474 0x0000 0x3 0x0
+#define MX6SX_PAD_LCD1_DATA23__CSI1_DATA_10                       0x012C 0x0474 0x06FC 0x4 0x0
+#define MX6SX_PAD_LCD1_DATA23__GPIO3_IO_24                        0x012C 0x0474 0x0000 0x5 0x0
+#define MX6SX_PAD_LCD1_DATA23__SRC_BT_CFG_31                      0x012C 0x0474 0x0000 0x6 0x0
+#define MX6SX_PAD_LCD1_DATA23__SIM_M_HSIZE_2                      0x012C 0x0474 0x0000 0x7 0x0
+#define MX6SX_PAD_LCD1_DATA23__VDEC_DEBUG_8                       0x012C 0x0474 0x0000 0x8 0x0
+#define MX6SX_PAD_LCD1_DATA23__MMDC_DEBUG_28                      0x012C 0x0474 0x0000 0x9 0x0
+#define MX6SX_PAD_LCD1_ENABLE__LCDIF1_ENABLE                      0x0130 0x0478 0x0000 0x0 0x0
+#define MX6SX_PAD_LCD1_ENABLE__LCDIF1_RD_E                        0x0130 0x0478 0x0000 0x1 0x0
+#define MX6SX_PAD_LCD1_ENABLE__AUDMUX_AUD3_TXC                    0x0130 0x0478 0x063C 0x2 0x1
+#define MX6SX_PAD_LCD1_ENABLE__ENET1_1588_EVENT3_IN               0x0130 0x0478 0x0000 0x3 0x0
+#define MX6SX_PAD_LCD1_ENABLE__CSI1_DATA_17                       0x0130 0x0478 0x06E0 0x4 0x0
+#define MX6SX_PAD_LCD1_ENABLE__GPIO3_IO_25                        0x0130 0x0478 0x0000 0x5 0x0
+#define MX6SX_PAD_LCD1_ENABLE__USDHC1_CD_B                        0x0130 0x0478 0x0864 0x6 0x0
+#define MX6SX_PAD_LCD1_ENABLE__SIM_M_HADDR_17                     0x0130 0x0478 0x0000 0x7 0x0
+#define MX6SX_PAD_LCD1_ENABLE__VADC_TEST_1                        0x0130 0x0478 0x0000 0x8 0x0
+#define MX6SX_PAD_LCD1_ENABLE__MMDC_DEBUG_1                       0x0130 0x0478 0x0000 0x9 0x0
+#define MX6SX_PAD_LCD1_HSYNC__LCDIF1_HSYNC                        0x0134 0x047C 0x07E0 0x0 0x0
+#define MX6SX_PAD_LCD1_HSYNC__LCDIF1_RS                           0x0134 0x047C 0x0000 0x1 0x0
+#define MX6SX_PAD_LCD1_HSYNC__AUDMUX_AUD3_TXD                     0x0134 0x047C 0x0630 0x2 0x1
+#define MX6SX_PAD_LCD1_HSYNC__ENET2_1588_EVENT2_IN                0x0134 0x047C 0x0000 0x3 0x0
+#define MX6SX_PAD_LCD1_HSYNC__CSI1_DATA_18                        0x0134 0x047C 0x06E4 0x4 0x0
+#define MX6SX_PAD_LCD1_HSYNC__GPIO3_IO_26                         0x0134 0x047C 0x0000 0x5 0x0
+#define MX6SX_PAD_LCD1_HSYNC__USDHC2_WP                           0x0134 0x047C 0x0870 0x6 0x0
+#define MX6SX_PAD_LCD1_HSYNC__SIM_M_HADDR_18                      0x0134 0x047C 0x0000 0x7 0x0
+#define MX6SX_PAD_LCD1_HSYNC__VADC_TEST_2                         0x0134 0x047C 0x0000 0x8 0x0
+#define MX6SX_PAD_LCD1_HSYNC__MMDC_DEBUG_2                        0x0134 0x047C 0x0000 0x9 0x0
+#define MX6SX_PAD_LCD1_RESET__LCDIF1_RESET                        0x0138 0x0480 0x0000 0x0 0x0
+#define MX6SX_PAD_LCD1_RESET__LCDIF1_CS                           0x0138 0x0480 0x0000 0x1 0x0
+#define MX6SX_PAD_LCD1_RESET__AUDMUX_AUD3_RXD                     0x0138 0x0480 0x062C 0x2 0x1
+#define MX6SX_PAD_LCD1_RESET__KITTEN_EVENTI                       0x0138 0x0480 0x0000 0x3 0x0
+#define MX6SX_PAD_LCD1_RESET__M4_EVENTI                           0x0138 0x0480 0x0000 0x4 0x0
+#define MX6SX_PAD_LCD1_RESET__GPIO3_IO_27                         0x0138 0x0480 0x0000 0x5 0x0
+#define MX6SX_PAD_LCD1_RESET__CCM_PMIC_RDY                        0x0138 0x0480 0x069C 0x6 0x0
+#define MX6SX_PAD_LCD1_RESET__SIM_M_HADDR_20                      0x0138 0x0480 0x0000 0x7 0x0
+#define MX6SX_PAD_LCD1_RESET__VADC_TEST_4                         0x0138 0x0480 0x0000 0x8 0x0
+#define MX6SX_PAD_LCD1_RESET__MMDC_DEBUG_4                        0x0138 0x0480 0x0000 0x9 0x0
+#define MX6SX_PAD_LCD1_VSYNC__LCDIF1_VSYNC                        0x013C 0x0484 0x0000 0x0 0x0
+#define MX6SX_PAD_LCD1_VSYNC__LCDIF1_BUSY                         0x013C 0x0484 0x07E0 0x1 0x1
+#define MX6SX_PAD_LCD1_VSYNC__AUDMUX_AUD3_TXFS                    0x013C 0x0484 0x0640 0x2 0x1
+#define MX6SX_PAD_LCD1_VSYNC__ENET2_1588_EVENT3_IN                0x013C 0x0484 0x0000 0x3 0x0
+#define MX6SX_PAD_LCD1_VSYNC__CSI1_DATA_19                        0x013C 0x0484 0x06E8 0x4 0x0
+#define MX6SX_PAD_LCD1_VSYNC__GPIO3_IO_28                         0x013C 0x0484 0x0000 0x5 0x0
+#define MX6SX_PAD_LCD1_VSYNC__USDHC2_CD_B                         0x013C 0x0484 0x086C 0x6 0x0
+#define MX6SX_PAD_LCD1_VSYNC__SIM_M_HADDR_19                      0x013C 0x0484 0x0000 0x7 0x0
+#define MX6SX_PAD_LCD1_VSYNC__VADC_TEST_3                         0x013C 0x0484 0x0000 0x8 0x0
+#define MX6SX_PAD_LCD1_VSYNC__MMDC_DEBUG_3                        0x013C 0x0484 0x0000 0x9 0x0
+#define MX6SX_PAD_NAND_ALE__RAWNAND_ALE                           0x0140 0x0488 0x0000 0x0 0x0
+#define MX6SX_PAD_NAND_ALE__I2C3_SDA                              0x0140 0x0488 0x07BC 0x1 0x0
+#define MX6SX_PAD_NAND_ALE__QSPI2_A_SS0_B                         0x0140 0x0488 0x0000 0x2 0x0
+#define MX6SX_PAD_NAND_ALE__ECSPI2_SS0                            0x0140 0x0488 0x072C 0x3 0x0
+#define MX6SX_PAD_NAND_ALE__ESAI_TX3_RX2                          0x0140 0x0488 0x079C 0x4 0x0
+#define MX6SX_PAD_NAND_ALE__GPIO4_IO_0                            0x0140 0x0488 0x0000 0x5 0x0
+#define MX6SX_PAD_NAND_ALE__WEIM_CS0_B                            0x0140 0x0488 0x0000 0x6 0x0
+#define MX6SX_PAD_NAND_ALE__TPSMP_HDATA_0                         0x0140 0x0488 0x0000 0x7 0x0
+#define MX6SX_PAD_NAND_ALE__ANATOP_USBPHY1_TSTI_TX_EN             0x0140 0x0488 0x0000 0x8 0x0
+#define MX6SX_PAD_NAND_ALE__SDMA_DEBUG_PC_12                      0x0140 0x0488 0x0000 0x9 0x0
+#define MX6SX_PAD_NAND_CE0_B__RAWNAND_CE0_B                       0x0144 0x048C 0x0000 0x0 0x0
+#define MX6SX_PAD_NAND_CE0_B__USDHC2_VSELECT                      0x0144 0x048C 0x0000 0x1 0x0
+#define MX6SX_PAD_NAND_CE0_B__QSPI2_A_DATA_2                      0x0144 0x048C 0x0000 0x2 0x0
+#define MX6SX_PAD_NAND_CE0_B__AUDMUX_AUD4_TXC                     0x0144 0x048C 0x0654 0x3 0x0
+#define MX6SX_PAD_NAND_CE0_B__ESAI_TX_CLK                         0x0144 0x048C 0x078C 0x4 0x0
+#define MX6SX_PAD_NAND_CE0_B__GPIO4_IO_1                          0x0144 0x048C 0x0000 0x5 0x0
+#define MX6SX_PAD_NAND_CE0_B__WEIM_LBA_B                          0x0144 0x048C 0x0000 0x6 0x0
+#define MX6SX_PAD_NAND_CE0_B__TPSMP_HDATA_3                       0x0144 0x048C 0x0000 0x7 0x0
+#define MX6SX_PAD_NAND_CE0_B__ANATOP_USBPHY1_TSTI_TX_HIZ          0x0144 0x048C 0x0000 0x8 0x0
+#define MX6SX_PAD_NAND_CE0_B__SDMA_DEBUG_PC_9                     0x0144 0x048C 0x0000 0x9 0x0
+#define MX6SX_PAD_NAND_CE1_B__RAWNAND_CE1_B                       0x0148 0x0490 0x0000 0x0 0x0
+#define MX6SX_PAD_NAND_CE1_B__USDHC3_RESET_B                      0x0148 0x0490 0x0000 0x1 0x0
+#define MX6SX_PAD_NAND_CE1_B__QSPI2_A_DATA_3                      0x0148 0x0490 0x0000 0x2 0x0
+#define MX6SX_PAD_NAND_CE1_B__AUDMUX_AUD4_TXD                     0x0148 0x0490 0x0648 0x3 0x0
+#define MX6SX_PAD_NAND_CE1_B__ESAI_TX0                            0x0148 0x0490 0x0790 0x4 0x0
+#define MX6SX_PAD_NAND_CE1_B__GPIO4_IO_2                          0x0148 0x0490 0x0000 0x5 0x0
+#define MX6SX_PAD_NAND_CE1_B__WEIM_OE                             0x0148 0x0490 0x0000 0x6 0x0
+#define MX6SX_PAD_NAND_CE1_B__TPSMP_HDATA_4                       0x0148 0x0490 0x0000 0x7 0x0
+#define MX6SX_PAD_NAND_CE1_B__ANATOP_USBPHY1_TSTI_TX_LS_MODE      0x0148 0x0490 0x0000 0x8 0x0
+#define MX6SX_PAD_NAND_CE1_B__SDMA_DEBUG_PC_8                     0x0148 0x0490 0x0000 0x9 0x0
+#define MX6SX_PAD_NAND_CLE__RAWNAND_CLE                           0x014C 0x0494 0x0000 0x0 0x0
+#define MX6SX_PAD_NAND_CLE__I2C3_SCL                              0x014C 0x0494 0x07B8 0x1 0x0
+#define MX6SX_PAD_NAND_CLE__QSPI2_A_SCLK                          0x014C 0x0494 0x0000 0x2 0x0
+#define MX6SX_PAD_NAND_CLE__ECSPI2_SCLK                           0x014C 0x0494 0x0720 0x3 0x0
+#define MX6SX_PAD_NAND_CLE__ESAI_TX2_RX3                          0x014C 0x0494 0x0798 0x4 0x0
+#define MX6SX_PAD_NAND_CLE__GPIO4_IO_3                            0x014C 0x0494 0x0000 0x5 0x0
+#define MX6SX_PAD_NAND_CLE__WEIM_BCLK                             0x014C 0x0494 0x0000 0x6 0x0
+#define MX6SX_PAD_NAND_CLE__TPSMP_CLK                             0x014C 0x0494 0x0000 0x7 0x0
+#define MX6SX_PAD_NAND_CLE__ANATOP_USBPHY1_TSTI_TX_DP             0x014C 0x0494 0x0000 0x8 0x0
+#define MX6SX_PAD_NAND_CLE__SDMA_DEBUG_PC_13                      0x014C 0x0494 0x0000 0x9 0x0
+#define MX6SX_PAD_NAND_DATA00__RAWNAND_DATA00                     0x0150 0x0498 0x0000 0x0 0x0
+#define MX6SX_PAD_NAND_DATA00__USDHC1_DATA4                       0x0150 0x0498 0x0000 0x1 0x0
+#define MX6SX_PAD_NAND_DATA00__QSPI2_B_DATA_1                     0x0150 0x0498 0x0000 0x2 0x0
+#define MX6SX_PAD_NAND_DATA00__ECSPI5_MISO                        0x0150 0x0498 0x0754 0x3 0x0
+#define MX6SX_PAD_NAND_DATA00__ESAI_RX_CLK                        0x0150 0x0498 0x0788 0x4 0x0
+#define MX6SX_PAD_NAND_DATA00__GPIO4_IO_4                         0x0150 0x0498 0x0000 0x5 0x0
+#define MX6SX_PAD_NAND_DATA00__WEIM_AD_0                          0x0150 0x0498 0x0000 0x6 0x0
+#define MX6SX_PAD_NAND_DATA00__TPSMP_HDATA_7                      0x0150 0x0498 0x0000 0x7 0x0
+#define MX6SX_PAD_NAND_DATA00__ANATOP_USBPHY1_TSTO_RX_DISCON_DET  0x0150 0x0498 0x0000 0x8 0x0
+#define MX6SX_PAD_NAND_DATA00__SDMA_DEBUG_EVT_CHN_LINES_5         0x0150 0x0498 0x0000 0x9 0x0
+#define MX6SX_PAD_NAND_DATA01__RAWNAND_DATA01                     0x0154 0x049C 0x0000 0x0 0x0
+#define MX6SX_PAD_NAND_DATA01__USDHC1_DATA5                       0x0154 0x049C 0x0000 0x1 0x0
+#define MX6SX_PAD_NAND_DATA01__QSPI2_B_DATA_0                     0x0154 0x049C 0x0000 0x2 0x0
+#define MX6SX_PAD_NAND_DATA01__ECSPI5_MOSI                        0x0154 0x049C 0x0758 0x3 0x0
+#define MX6SX_PAD_NAND_DATA01__ESAI_RX_FS                         0x0154 0x049C 0x0778 0x4 0x0
+#define MX6SX_PAD_NAND_DATA01__GPIO4_IO_5                         0x0154 0x049C 0x0000 0x5 0x0
+#define MX6SX_PAD_NAND_DATA01__WEIM_AD_1                          0x0154 0x049C 0x0000 0x6 0x0
+#define MX6SX_PAD_NAND_DATA01__TPSMP_HDATA_8                      0x0154 0x049C 0x0000 0x7 0x0
+#define MX6SX_PAD_NAND_DATA01__ANATOP_USBPHY1_TSTO_RX_HS_RXD      0x0154 0x049C 0x0000 0x8 0x0
+#define MX6SX_PAD_NAND_DATA01__SDMA_DEBUG_EVT_CHN_LINES_4         0x0154 0x049C 0x0000 0x9 0x0
+#define MX6SX_PAD_NAND_DATA02__RAWNAND_DATA02                     0x0158 0x04A0 0x0000 0x0 0x0
+#define MX6SX_PAD_NAND_DATA02__USDHC1_DATA6                       0x0158 0x04A0 0x0000 0x1 0x0
+#define MX6SX_PAD_NAND_DATA02__QSPI2_B_SCLK                       0x0158 0x04A0 0x0000 0x2 0x0
+#define MX6SX_PAD_NAND_DATA02__ECSPI5_SCLK                        0x0158 0x04A0 0x0750 0x3 0x0
+#define MX6SX_PAD_NAND_DATA02__ESAI_TX_HF_CLK                     0x0158 0x04A0 0x0784 0x4 0x0
+#define MX6SX_PAD_NAND_DATA02__GPIO4_IO_6                         0x0158 0x04A0 0x0000 0x5 0x0
+#define MX6SX_PAD_NAND_DATA02__WEIM_AD_2                          0x0158 0x04A0 0x0000 0x6 0x0
+#define MX6SX_PAD_NAND_DATA02__TPSMP_HDATA_9                      0x0158 0x04A0 0x0000 0x7 0x0
+#define MX6SX_PAD_NAND_DATA02__ANATOP_USBPHY2_TSTO_PLL_CLK20DIV   0x0158 0x04A0 0x0000 0x8 0x0
+#define MX6SX_PAD_NAND_DATA02__SDMA_DEBUG_EVT_CHN_LINES_3         0x0158 0x04A0 0x0000 0x9 0x0
+#define MX6SX_PAD_NAND_DATA03__RAWNAND_DATA03                     0x015C 0x04A4 0x0000 0x0 0x0
+#define MX6SX_PAD_NAND_DATA03__USDHC1_DATA7                       0x015C 0x04A4 0x0000 0x1 0x0
+#define MX6SX_PAD_NAND_DATA03__QSPI2_B_SS0_B                      0x015C 0x04A4 0x0000 0x2 0x0
+#define MX6SX_PAD_NAND_DATA03__ECSPI5_SS0                         0x015C 0x04A4 0x075C 0x3 0x0
+#define MX6SX_PAD_NAND_DATA03__ESAI_RX_HF_CLK                     0x015C 0x04A4 0x0780 0x4 0x0
+#define MX6SX_PAD_NAND_DATA03__GPIO4_IO_7                         0x015C 0x04A4 0x0000 0x5 0x0
+#define MX6SX_PAD_NAND_DATA03__WEIM_AD_3                          0x015C 0x04A4 0x0000 0x6 0x0
+#define MX6SX_PAD_NAND_DATA03__TPSMP_HDATA_10                     0x015C 0x04A4 0x0000 0x7 0x0
+#define MX6SX_PAD_NAND_DATA03__ANATOP_USBPHY1_TSTO_RX_SQUELCH     0x015C 0x04A4 0x0000 0x8 0x0
+#define MX6SX_PAD_NAND_DATA03__SDMA_DEBUG_EVT_CHN_LINES_6         0x015C 0x04A4 0x0000 0x9 0x0
+#define MX6SX_PAD_NAND_DATA04__RAWNAND_DATA04                     0x0160 0x04A8 0x0000 0x0 0x0
+#define MX6SX_PAD_NAND_DATA04__USDHC2_DATA4                       0x0160 0x04A8 0x0000 0x1 0x0
+#define MX6SX_PAD_NAND_DATA04__QSPI2_B_SS1_B                      0x0160 0x04A8 0x0000 0x2 0x0
+#define MX6SX_PAD_NAND_DATA04__UART3_RTS_B                        0x0160 0x04A8 0x083C 0x3 0x0
+#define MX6SX_PAD_NAND_DATA04__UART3_CTS_B                        0x0160 0x04A8 0x0000 0x3 0x0
+#define MX6SX_PAD_NAND_DATA04__AUDMUX_AUD4_RXFS                   0x0160 0x04A8 0x0650 0x4 0x0
+#define MX6SX_PAD_NAND_DATA04__GPIO4_IO_8                         0x0160 0x04A8 0x0000 0x5 0x0
+#define MX6SX_PAD_NAND_DATA04__WEIM_AD_4                          0x0160 0x04A8 0x0000 0x6 0x0
+#define MX6SX_PAD_NAND_DATA04__TPSMP_HDATA_11                     0x0160 0x04A8 0x0000 0x7 0x0
+#define MX6SX_PAD_NAND_DATA04__ANATOP_USBPHY2_TSTO_RX_SQUELCH     0x0160 0x04A8 0x0000 0x8 0x0
+#define MX6SX_PAD_NAND_DATA04__SDMA_DEBUG_CORE_STATE_0            0x0160 0x04A8 0x0000 0x9 0x0
+#define MX6SX_PAD_NAND_DATA05__RAWNAND_DATA05                     0x0164 0x04AC 0x0000 0x0 0x0
+#define MX6SX_PAD_NAND_DATA05__USDHC2_DATA5                       0x0164 0x04AC 0x0000 0x1 0x0
+#define MX6SX_PAD_NAND_DATA05__QSPI2_B_DQS                        0x0164 0x04AC 0x0000 0x2 0x0
+#define MX6SX_PAD_NAND_DATA05__UART3_CTS_B                        0x0164 0x04AC 0x0000 0x3 0x0
+#define MX6SX_PAD_NAND_DATA05__UART3_RTS_B                        0x0164 0x04AC 0x083C 0x3 0x1
+#define MX6SX_PAD_NAND_DATA05__AUDMUX_AUD4_RXC                    0x0164 0x04AC 0x064C 0x4 0x0
+#define MX6SX_PAD_NAND_DATA05__GPIO4_IO_9                         0x0164 0x04AC 0x0000 0x5 0x0
+#define MX6SX_PAD_NAND_DATA05__WEIM_AD_5                          0x0164 0x04AC 0x0000 0x6 0x0
+#define MX6SX_PAD_NAND_DATA05__TPSMP_HDATA_12                     0x0164 0x04AC 0x0000 0x7 0x0
+#define MX6SX_PAD_NAND_DATA05__ANATOP_USBPHY2_TSTO_RX_DISCON_DET  0x0164 0x04AC 0x0000 0x8 0x0
+#define MX6SX_PAD_NAND_DATA05__SDMA_DEBUG_CORE_STATE_1            0x0164 0x04AC 0x0000 0x9 0x0
+#define MX6SX_PAD_NAND_DATA06__RAWNAND_DATA06                     0x0168 0x04B0 0x0000 0x0 0x0
+#define MX6SX_PAD_NAND_DATA06__USDHC2_DATA6                       0x0168 0x04B0 0x0000 0x1 0x0
+#define MX6SX_PAD_NAND_DATA06__QSPI2_A_SS1_B                      0x0168 0x04B0 0x0000 0x2 0x0
+#define MX6SX_PAD_NAND_DATA06__UART3_RX                           0x0168 0x04B0 0x0840 0x3 0x0
+#define MX6SX_PAD_NAND_DATA06__UART3_TX                           0x0168 0x04B0 0x0000 0x3 0x0
+#define MX6SX_PAD_NAND_DATA06__PWM3_OUT                           0x0168 0x04B0 0x0000 0x4 0x0
+#define MX6SX_PAD_NAND_DATA06__GPIO4_IO_10                        0x0168 0x04B0 0x0000 0x5 0x0
+#define MX6SX_PAD_NAND_DATA06__WEIM_AD_6                          0x0168 0x04B0 0x0000 0x6 0x0
+#define MX6SX_PAD_NAND_DATA06__TPSMP_HDATA_13                     0x0168 0x04B0 0x0000 0x7 0x0
+#define MX6SX_PAD_NAND_DATA06__ANATOP_USBPHY2_TSTO_RX_FS_RXD      0x0168 0x04B0 0x0000 0x8 0x0
+#define MX6SX_PAD_NAND_DATA06__SDMA_DEBUG_CORE_STATE_2            0x0168 0x04B0 0x0000 0x9 0x0
+#define MX6SX_PAD_NAND_DATA07__RAWNAND_DATA07                     0x016C 0x04B4 0x0000 0x0 0x0
+#define MX6SX_PAD_NAND_DATA07__USDHC2_DATA7                       0x016C 0x04B4 0x0000 0x1 0x0
+#define MX6SX_PAD_NAND_DATA07__QSPI2_A_DQS                        0x016C 0x04B4 0x0000 0x2 0x0
+#define MX6SX_PAD_NAND_DATA07__UART3_RX                           0x016C 0x04B4 0x0840 0x3 0x1
+#define MX6SX_PAD_NAND_DATA07__UART3_TX                           0x016C 0x04B4 0x0000 0x3 0x0
+#define MX6SX_PAD_NAND_DATA07__PWM4_OUT                           0x016C 0x04B4 0x0000 0x4 0x0
+#define MX6SX_PAD_NAND_DATA07__GPIO4_IO_11                        0x016C 0x04B4 0x0000 0x5 0x0
+#define MX6SX_PAD_NAND_DATA07__WEIM_AD_7                          0x016C 0x04B4 0x0000 0x6 0x0
+#define MX6SX_PAD_NAND_DATA07__TPSMP_HDATA_14                     0x016C 0x04B4 0x0000 0x7 0x0
+#define MX6SX_PAD_NAND_DATA07__ANATOP_USBPHY1_TSTO_RX_FS_RXD      0x016C 0x04B4 0x0000 0x8 0x0
+#define MX6SX_PAD_NAND_DATA07__SDMA_DEBUG_CORE_STATE_3            0x016C 0x04B4 0x0000 0x9 0x0
+#define MX6SX_PAD_NAND_RE_B__RAWNAND_RE_B                         0x0170 0x04B8 0x0000 0x0 0x0
+#define MX6SX_PAD_NAND_RE_B__USDHC2_RESET_B                       0x0170 0x04B8 0x0000 0x1 0x0
+#define MX6SX_PAD_NAND_RE_B__QSPI2_B_DATA_3                       0x0170 0x04B8 0x0000 0x2 0x0
+#define MX6SX_PAD_NAND_RE_B__AUDMUX_AUD4_TXFS                     0x0170 0x04B8 0x0658 0x3 0x0
+#define MX6SX_PAD_NAND_RE_B__ESAI_TX_FS                           0x0170 0x04B8 0x077C 0x4 0x0
+#define MX6SX_PAD_NAND_RE_B__GPIO4_IO_12                          0x0170 0x04B8 0x0000 0x5 0x0
+#define MX6SX_PAD_NAND_RE_B__WEIM_RW                              0x0170 0x04B8 0x0000 0x6 0x0
+#define MX6SX_PAD_NAND_RE_B__TPSMP_HDATA_5                        0x0170 0x04B8 0x0000 0x7 0x0
+#define MX6SX_PAD_NAND_RE_B__ANATOP_USBPHY2_TSTO_RX_HS_RXD        0x0170 0x04B8 0x0000 0x8 0x0
+#define MX6SX_PAD_NAND_RE_B__SDMA_DEBUG_PC_7                      0x0170 0x04B8 0x0000 0x9 0x0
+#define MX6SX_PAD_NAND_READY_B__RAWNAND_READY_B                   0x0174 0x04BC 0x0000 0x0 0x0
+#define MX6SX_PAD_NAND_READY_B__USDHC1_VSELECT                    0x0174 0x04BC 0x0000 0x1 0x0
+#define MX6SX_PAD_NAND_READY_B__QSPI2_A_DATA_1                    0x0174 0x04BC 0x0000 0x2 0x0
+#define MX6SX_PAD_NAND_READY_B__ECSPI2_MISO                       0x0174 0x04BC 0x0724 0x3 0x0
+#define MX6SX_PAD_NAND_READY_B__ESAI_TX1                          0x0174 0x04BC 0x0794 0x4 0x0
+#define MX6SX_PAD_NAND_READY_B__GPIO4_IO_13                       0x0174 0x04BC 0x0000 0x5 0x0
+#define MX6SX_PAD_NAND_READY_B__WEIM_EB_B_1                       0x0174 0x04BC 0x0000 0x6 0x0
+#define MX6SX_PAD_NAND_READY_B__TPSMP_HDATA_2                     0x0174 0x04BC 0x0000 0x7 0x0
+#define MX6SX_PAD_NAND_READY_B__ANATOP_USBPHY1_TSTI_TX_DN         0x0174 0x04BC 0x0000 0x8 0x0
+#define MX6SX_PAD_NAND_READY_B__SDMA_DEBUG_PC_10                  0x0174 0x04BC 0x0000 0x9 0x0
+#define MX6SX_PAD_NAND_WE_B__RAWNAND_WE_B                         0x0178 0x04C0 0x0000 0x0 0x0
+#define MX6SX_PAD_NAND_WE_B__USDHC4_VSELECT                       0x0178 0x04C0 0x0000 0x1 0x0
+#define MX6SX_PAD_NAND_WE_B__QSPI2_B_DATA_2                       0x0178 0x04C0 0x0000 0x2 0x0
+#define MX6SX_PAD_NAND_WE_B__AUDMUX_AUD4_RXD                      0x0178 0x04C0 0x0644 0x3 0x0
+#define MX6SX_PAD_NAND_WE_B__ESAI_TX5_RX0                         0x0178 0x04C0 0x07A4 0x4 0x0
+#define MX6SX_PAD_NAND_WE_B__GPIO4_IO_14                          0x0178 0x04C0 0x0000 0x5 0x0
+#define MX6SX_PAD_NAND_WE_B__WEIM_WAIT                            0x0178 0x04C0 0x0000 0x6 0x0
+#define MX6SX_PAD_NAND_WE_B__TPSMP_HDATA_6                        0x0178 0x04C0 0x0000 0x7 0x0
+#define MX6SX_PAD_NAND_WE_B__ANATOP_USBPHY1_TSTO_PLL_CLK20DIV     0x0178 0x04C0 0x0000 0x8 0x0
+#define MX6SX_PAD_NAND_WE_B__SDMA_DEBUG_PC_6                      0x0178 0x04C0 0x0000 0x9 0x0
+#define MX6SX_PAD_NAND_WP_B__RAWNAND_WP_B                         0x017C 0x04C4 0x0000 0x0 0x0
+#define MX6SX_PAD_NAND_WP_B__USDHC1_RESET_B                       0x017C 0x04C4 0x0000 0x1 0x0
+#define MX6SX_PAD_NAND_WP_B__QSPI2_A_DATA_0                       0x017C 0x04C4 0x0000 0x2 0x0
+#define MX6SX_PAD_NAND_WP_B__ECSPI2_MOSI                          0x017C 0x04C4 0x0728 0x3 0x0
+#define MX6SX_PAD_NAND_WP_B__ESAI_TX4_RX1                         0x017C 0x04C4 0x07A0 0x4 0x0
+#define MX6SX_PAD_NAND_WP_B__GPIO4_IO_15                          0x017C 0x04C4 0x0000 0x5 0x0
+#define MX6SX_PAD_NAND_WP_B__WEIM_EB_B_0                          0x017C 0x04C4 0x0000 0x6 0x0
+#define MX6SX_PAD_NAND_WP_B__TPSMP_HDATA_1                        0x017C 0x04C4 0x0000 0x7 0x0
+#define MX6SX_PAD_NAND_WP_B__ANATOP_USBPHY1_TSTI_TX_HS_MODE       0x017C 0x04C4 0x0000 0x8 0x0
+#define MX6SX_PAD_NAND_WP_B__SDMA_DEBUG_PC_11                     0x017C 0x04C4 0x0000 0x9 0x0
+#define MX6SX_PAD_QSPI1A_DATA0__QSPI1_A_DATA_0                    0x0180 0x04C8 0x0000 0x0 0x0
+#define MX6SX_PAD_QSPI1A_DATA0__USB_OTG2_OC                       0x0180 0x04C8 0x085C 0x1 0x2
+#define MX6SX_PAD_QSPI1A_DATA0__ECSPI1_MOSI                       0x0180 0x04C8 0x0718 0x2 0x1
+#define MX6SX_PAD_QSPI1A_DATA0__ESAI_TX4_RX1                      0x0180 0x04C8 0x07A0 0x3 0x2
+#define MX6SX_PAD_QSPI1A_DATA0__CSI1_DATA_14                      0x0180 0x04C8 0x06D4 0x4 0x1
+#define MX6SX_PAD_QSPI1A_DATA0__GPIO4_IO_16                       0x0180 0x04C8 0x0000 0x5 0x0
+#define MX6SX_PAD_QSPI1A_DATA0__WEIM_DATA_6                       0x0180 0x04C8 0x0000 0x6 0x0
+#define MX6SX_PAD_QSPI1A_DATA0__SIM_M_HADDR_3                     0x0180 0x04C8 0x0000 0x7 0x0
+#define MX6SX_PAD_QSPI1A_DATA0__SDMA_DEBUG_BUS_DEVICE_3           0x0180 0x04C8 0x0000 0x9 0x0
+#define MX6SX_PAD_QSPI1A_DATA1__QSPI1_A_DATA_1                    0x0184 0x04CC 0x0000 0x0 0x0
+#define MX6SX_PAD_QSPI1A_DATA1__ANATOP_OTG1_ID                    0x0184 0x04CC 0x0624 0x1 0x2
+#define MX6SX_PAD_QSPI1A_DATA1__ECSPI1_MISO                       0x0184 0x04CC 0x0714 0x2 0x1
+#define MX6SX_PAD_QSPI1A_DATA1__ESAI_TX1                          0x0184 0x04CC 0x0794 0x3 0x2
+#define MX6SX_PAD_QSPI1A_DATA1__CSI1_DATA_13                      0x0184 0x04CC 0x06D0 0x4 0x1
+#define MX6SX_PAD_QSPI1A_DATA1__GPIO4_IO_17                       0x0184 0x04CC 0x0000 0x5 0x0
+#define MX6SX_PAD_QSPI1A_DATA1__WEIM_DATA_5                       0x0184 0x04CC 0x0000 0x6 0x0
+#define MX6SX_PAD_QSPI1A_DATA1__SIM_M_HADDR_4                     0x0184 0x04CC 0x0000 0x7 0x0
+#define MX6SX_PAD_QSPI1A_DATA1__SDMA_DEBUG_PC_0                   0x0184 0x04CC 0x0000 0x9 0x0
+#define MX6SX_PAD_QSPI1A_DATA2__QSPI1_A_DATA_2                    0x0188 0x04D0 0x0000 0x0 0x0
+#define MX6SX_PAD_QSPI1A_DATA2__USB_OTG1_PWR                      0x0188 0x04D0 0x0000 0x1 0x0
+#define MX6SX_PAD_QSPI1A_DATA2__ECSPI5_SS1                        0x0188 0x04D0 0x0000 0x2 0x0
+#define MX6SX_PAD_QSPI1A_DATA2__ESAI_TX_CLK                       0x0188 0x04D0 0x078C 0x3 0x2
+#define MX6SX_PAD_QSPI1A_DATA2__CSI1_DATA_12                      0x0188 0x04D0 0x06CC 0x4 0x1
+#define MX6SX_PAD_QSPI1A_DATA2__GPIO4_IO_18                       0x0188 0x04D0 0x0000 0x5 0x0
+#define MX6SX_PAD_QSPI1A_DATA2__WEIM_DATA_4                       0x0188 0x04D0 0x0000 0x6 0x0
+#define MX6SX_PAD_QSPI1A_DATA2__SIM_M_HADDR_6                     0x0188 0x04D0 0x0000 0x7 0x0
+#define MX6SX_PAD_QSPI1A_DATA2__SDMA_DEBUG_PC_1                   0x0188 0x04D0 0x0000 0x9 0x0
+#define MX6SX_PAD_QSPI1A_DATA3__QSPI1_A_DATA_3                    0x018C 0x04D4 0x0000 0x0 0x0
+#define MX6SX_PAD_QSPI1A_DATA3__USB_OTG1_OC                       0x018C 0x04D4 0x0860 0x1 0x2
+#define MX6SX_PAD_QSPI1A_DATA3__ECSPI5_SS2                        0x018C 0x04D4 0x0000 0x2 0x0
+#define MX6SX_PAD_QSPI1A_DATA3__ESAI_TX0                          0x018C 0x04D4 0x0790 0x3 0x2
+#define MX6SX_PAD_QSPI1A_DATA3__CSI1_DATA_11                      0x018C 0x04D4 0x06C8 0x4 0x1
+#define MX6SX_PAD_QSPI1A_DATA3__GPIO4_IO_19                       0x018C 0x04D4 0x0000 0x5 0x0
+#define MX6SX_PAD_QSPI1A_DATA3__WEIM_DATA_3                       0x018C 0x04D4 0x0000 0x6 0x0
+#define MX6SX_PAD_QSPI1A_DATA3__SIM_M_HADDR_7                     0x018C 0x04D4 0x0000 0x7 0x0
+#define MX6SX_PAD_QSPI1A_DATA3__SDMA_DEBUG_PC_2                   0x018C 0x04D4 0x0000 0x9 0x0
+#define MX6SX_PAD_QSPI1A_DQS__QSPI1_A_DQS                         0x0190 0x04D8 0x0000 0x0 0x0
+#define MX6SX_PAD_QSPI1A_DQS__CAN2_TX                             0x0190 0x04D8 0x0000 0x1 0x0
+#define MX6SX_PAD_QSPI1A_DQS__CANFD_TX2                           0x0190 0x04D8 0x0000 0x2 0x0
+#define MX6SX_PAD_QSPI1A_DQS__ECSPI5_MOSI                         0x0190 0x04D8 0x0758 0x3 0x1
+#define MX6SX_PAD_QSPI1A_DQS__CSI1_DATA_15                        0x0190 0x04D8 0x06D8 0x4 0x1
+#define MX6SX_PAD_QSPI1A_DQS__GPIO4_IO_20                         0x0190 0x04D8 0x0000 0x5 0x0
+#define MX6SX_PAD_QSPI1A_DQS__WEIM_DATA_7                         0x0190 0x04D8 0x0000 0x6 0x0
+#define MX6SX_PAD_QSPI1A_DQS__SIM_M_HADDR_13                      0x0190 0x04D8 0x0000 0x7 0x0
+#define MX6SX_PAD_QSPI1A_DQS__SDMA_DEBUG_BUS_DEVICE_4             0x0190 0x04D8 0x0000 0x9 0x0
+#define MX6SX_PAD_QSPI1A_SCLK__QSPI1_A_SCLK                       0x0194 0x04DC 0x0000 0x0 0x0
+#define MX6SX_PAD_QSPI1A_SCLK__ANATOP_OTG2_ID                     0x0194 0x04DC 0x0628 0x1 0x2
+#define MX6SX_PAD_QSPI1A_SCLK__ECSPI1_SCLK                        0x0194 0x04DC 0x0710 0x2 0x1
+#define MX6SX_PAD_QSPI1A_SCLK__ESAI_TX2_RX3                       0x0194 0x04DC 0x0798 0x3 0x2
+#define MX6SX_PAD_QSPI1A_SCLK__CSI1_DATA_1                        0x0194 0x04DC 0x06A4 0x4 0x1
+#define MX6SX_PAD_QSPI1A_SCLK__GPIO4_IO_21                        0x0194 0x04DC 0x0000 0x5 0x0
+#define MX6SX_PAD_QSPI1A_SCLK__WEIM_DATA_0                        0x0194 0x04DC 0x0000 0x6 0x0
+#define MX6SX_PAD_QSPI1A_SCLK__SIM_M_HADDR_0                      0x0194 0x04DC 0x0000 0x7 0x0
+#define MX6SX_PAD_QSPI1A_SCLK__SDMA_DEBUG_PC_5                    0x0194 0x04DC 0x0000 0x9 0x0
+#define MX6SX_PAD_QSPI1A_SS0_B__QSPI1_A_SS0_B                     0x0198 0x04E0 0x0000 0x0 0x0
+#define MX6SX_PAD_QSPI1A_SS0_B__USB_OTG2_PWR                      0x0198 0x04E0 0x0000 0x1 0x0
+#define MX6SX_PAD_QSPI1A_SS0_B__ECSPI1_SS0                        0x0198 0x04E0 0x071C 0x2 0x1
+#define MX6SX_PAD_QSPI1A_SS0_B__ESAI_TX3_RX2                      0x0198 0x04E0 0x079C 0x3 0x2
+#define MX6SX_PAD_QSPI1A_SS0_B__CSI1_DATA_0                       0x0198 0x04E0 0x06A0 0x4 0x1
+#define MX6SX_PAD_QSPI1A_SS0_B__GPIO4_IO_22                       0x0198 0x04E0 0x0000 0x5 0x0
+#define MX6SX_PAD_QSPI1A_SS0_B__WEIM_DATA_1                       0x0198 0x04E0 0x0000 0x6 0x0
+#define MX6SX_PAD_QSPI1A_SS0_B__SIM_M_HADDR_1                     0x0198 0x04E0 0x0000 0x7 0x0
+#define MX6SX_PAD_QSPI1A_SS0_B__SDMA_DEBUG_PC_4                   0x0198 0x04E0 0x0000 0x9 0x0
+#define MX6SX_PAD_QSPI1A_SS1_B__QSPI1_A_SS1_B                     0x019C 0x04E4 0x0000 0x0 0x0
+#define MX6SX_PAD_QSPI1A_SS1_B__CAN1_RX                           0x019C 0x04E4 0x068C 0x1 0x2
+#define MX6SX_PAD_QSPI1A_SS1_B__CANFD_RX1                         0x019C 0x04E4 0x0694 0x2 0x2
+#define MX6SX_PAD_QSPI1A_SS1_B__ECSPI5_MISO                       0x019C 0x04E4 0x0754 0x3 0x1
+#define MX6SX_PAD_QSPI1A_SS1_B__CSI1_DATA_10                      0x019C 0x04E4 0x06FC 0x4 0x1
+#define MX6SX_PAD_QSPI1A_SS1_B__GPIO4_IO_23                       0x019C 0x04E4 0x0000 0x5 0x0
+#define MX6SX_PAD_QSPI1A_SS1_B__WEIM_DATA_2                       0x019C 0x04E4 0x0000 0x6 0x0
+#define MX6SX_PAD_QSPI1A_SS1_B__SIM_M_HADDR_12                    0x019C 0x04E4 0x0000 0x7 0x0
+#define MX6SX_PAD_QSPI1A_SS1_B__SDMA_DEBUG_PC_3                   0x019C 0x04E4 0x0000 0x9 0x0
+#define MX6SX_PAD_QSPI1B_DATA0__QSPI1_B_DATA_0                    0x01A0 0x04E8 0x0000 0x0 0x0
+#define MX6SX_PAD_QSPI1B_DATA0__UART3_CTS_B                       0x01A0 0x04E8 0x0000 0x1 0x0
+#define MX6SX_PAD_QSPI1B_DATA0__UART3_RTS_B                       0x01A0 0x04E8 0x083C 0x1 0x4
+#define MX6SX_PAD_QSPI1B_DATA0__ECSPI3_MOSI                       0x01A0 0x04E8 0x0738 0x2 0x1
+#define MX6SX_PAD_QSPI1B_DATA0__ESAI_RX_FS                        0x01A0 0x04E8 0x0778 0x3 0x2
+#define MX6SX_PAD_QSPI1B_DATA0__CSI1_DATA_22                      0x01A0 0x04E8 0x06F4 0x4 0x1
+#define MX6SX_PAD_QSPI1B_DATA0__GPIO4_IO_24                       0x01A0 0x04E8 0x0000 0x5 0x0
+#define MX6SX_PAD_QSPI1B_DATA0__WEIM_DATA_14                      0x01A0 0x04E8 0x0000 0x6 0x0
+#define MX6SX_PAD_QSPI1B_DATA0__SIM_M_HADDR_9                     0x01A0 0x04E8 0x0000 0x7 0x0
+#define MX6SX_PAD_QSPI1B_DATA1__QSPI1_B_DATA_1                    0x01A4 0x04EC 0x0000 0x0 0x0
+#define MX6SX_PAD_QSPI1B_DATA1__UART3_RTS_B                       0x01A4 0x04EC 0x083C 0x1 0x5
+#define MX6SX_PAD_QSPI1B_DATA1__UART3_CTS_B                       0x01A4 0x04EC 0x0000 0x1 0x0
+#define MX6SX_PAD_QSPI1B_DATA1__ECSPI3_MISO                       0x01A4 0x04EC 0x0734 0x2 0x1
+#define MX6SX_PAD_QSPI1B_DATA1__ESAI_RX_CLK                       0x01A4 0x04EC 0x0788 0x3 0x2
+#define MX6SX_PAD_QSPI1B_DATA1__CSI1_DATA_21                      0x01A4 0x04EC 0x06F0 0x4 0x1
+#define MX6SX_PAD_QSPI1B_DATA1__GPIO4_IO_25                       0x01A4 0x04EC 0x0000 0x5 0x0
+#define MX6SX_PAD_QSPI1B_DATA1__WEIM_DATA_13                      0x01A4 0x04EC 0x0000 0x6 0x0
+#define MX6SX_PAD_QSPI1B_DATA1__SIM_M_HADDR_8                     0x01A4 0x04EC 0x0000 0x7 0x0
+#define MX6SX_PAD_QSPI1B_DATA2__QSPI1_B_DATA_2                    0x01A8 0x04F0 0x0000 0x0 0x0
+#define MX6SX_PAD_QSPI1B_DATA2__I2C2_SDA                          0x01A8 0x04F0 0x07B4 0x1 0x2
+#define MX6SX_PAD_QSPI1B_DATA2__ECSPI5_RDY                        0x01A8 0x04F0 0x0000 0x2 0x0
+#define MX6SX_PAD_QSPI1B_DATA2__ESAI_TX5_RX0                      0x01A8 0x04F0 0x07A4 0x3 0x2
+#define MX6SX_PAD_QSPI1B_DATA2__CSI1_DATA_20                      0x01A8 0x04F0 0x06EC 0x4 0x1
+#define MX6SX_PAD_QSPI1B_DATA2__GPIO4_IO_26                       0x01A8 0x04F0 0x0000 0x5 0x0
+#define MX6SX_PAD_QSPI1B_DATA2__WEIM_DATA_12                      0x01A8 0x04F0 0x0000 0x6 0x0
+#define MX6SX_PAD_QSPI1B_DATA2__SIM_M_HADDR_5                     0x01A8 0x04F0 0x0000 0x7 0x0
+#define MX6SX_PAD_QSPI1B_DATA3__QSPI1_B_DATA_3                    0x01AC 0x04F4 0x0000 0x0 0x0
+#define MX6SX_PAD_QSPI1B_DATA3__I2C2_SCL                          0x01AC 0x04F4 0x07B0 0x1 0x2
+#define MX6SX_PAD_QSPI1B_DATA3__ECSPI5_SS3                        0x01AC 0x04F4 0x0000 0x2 0x0
+#define MX6SX_PAD_QSPI1B_DATA3__ESAI_TX_FS                        0x01AC 0x04F4 0x077C 0x3 0x2
+#define MX6SX_PAD_QSPI1B_DATA3__CSI1_DATA_19                      0x01AC 0x04F4 0x06E8 0x4 0x1
+#define MX6SX_PAD_QSPI1B_DATA3__GPIO4_IO_27                       0x01AC 0x04F4 0x0000 0x5 0x0
+#define MX6SX_PAD_QSPI1B_DATA3__WEIM_DATA_11                      0x01AC 0x04F4 0x0000 0x6 0x0
+#define MX6SX_PAD_QSPI1B_DATA3__SIM_M_HADDR_2                     0x01AC 0x04F4 0x0000 0x7 0x0
+#define MX6SX_PAD_QSPI1B_DQS__QSPI1_B_DQS                         0x01B0 0x04F8 0x0000 0x0 0x0
+#define MX6SX_PAD_QSPI1B_DQS__CAN1_TX                             0x01B0 0x04F8 0x0000 0x1 0x0
+#define MX6SX_PAD_QSPI1B_DQS__CANFD_TX1                           0x01B0 0x04F8 0x0000 0x2 0x0
+#define MX6SX_PAD_QSPI1B_DQS__ECSPI5_SS0                          0x01B0 0x04F8 0x075C 0x3 0x1
+#define MX6SX_PAD_QSPI1B_DQS__CSI1_DATA_23                        0x01B0 0x04F8 0x06F8 0x4 0x1
+#define MX6SX_PAD_QSPI1B_DQS__GPIO4_IO_28                         0x01B0 0x04F8 0x0000 0x5 0x0
+#define MX6SX_PAD_QSPI1B_DQS__WEIM_DATA_15                        0x01B0 0x04F8 0x0000 0x6 0x0
+#define MX6SX_PAD_QSPI1B_DQS__SIM_M_HADDR_15                      0x01B0 0x04F8 0x0000 0x7 0x0
+#define MX6SX_PAD_QSPI1B_SCLK__QSPI1_B_SCLK                       0x01B4 0x04FC 0x0000 0x0 0x0
+#define MX6SX_PAD_QSPI1B_SCLK__UART3_RX                           0x01B4 0x04FC 0x0840 0x1 0x4
+#define MX6SX_PAD_QSPI1B_SCLK__UART3_TX                           0x01B4 0x04FC 0x0000 0x0 0x0
+#define MX6SX_PAD_QSPI1B_SCLK__ECSPI3_SCLK                        0x01B4 0x04FC 0x0730 0x2 0x1
+#define MX6SX_PAD_QSPI1B_SCLK__ESAI_RX_HF_CLK                     0x01B4 0x04FC 0x0780 0x3 0x2
+#define MX6SX_PAD_QSPI1B_SCLK__CSI1_DATA_16                       0x01B4 0x04FC 0x06DC 0x4 0x1
+#define MX6SX_PAD_QSPI1B_SCLK__GPIO4_IO_29                        0x01B4 0x04FC 0x0000 0x5 0x0
+#define MX6SX_PAD_QSPI1B_SCLK__WEIM_DATA_8                        0x01B4 0x04FC 0x0000 0x6 0x0
+#define MX6SX_PAD_QSPI1B_SCLK__SIM_M_HADDR_11                     0x01B4 0x04FC 0x0000 0x7 0x0
+#define MX6SX_PAD_QSPI1B_SS0_B__QSPI1_B_SS0_B                     0x01B8 0x0500 0x0000 0x0 0x0
+#define MX6SX_PAD_QSPI1B_SS0_B__UART3_RX                          0x01B8 0x0500 0x0840 0x1 0x5
+#define MX6SX_PAD_QSPI1B_SS0_B__UART3_TX                          0x01B8 0x0500 0x0000 0x1 0x0
+#define MX6SX_PAD_QSPI1B_SS0_B__ECSPI3_SS0                        0x01B8 0x0500 0x073C 0x2 0x1
+#define MX6SX_PAD_QSPI1B_SS0_B__ESAI_TX_HF_CLK                    0x01B8 0x0500 0x0784 0x3 0x3
+#define MX6SX_PAD_QSPI1B_SS0_B__CSI1_DATA_17                      0x01B8 0x0500 0x06E0 0x4 0x1
+#define MX6SX_PAD_QSPI1B_SS0_B__GPIO4_IO_30                       0x01B8 0x0500 0x0000 0x5 0x0
+#define MX6SX_PAD_QSPI1B_SS0_B__WEIM_DATA_9                       0x01B8 0x0500 0x0000 0x6 0x0
+#define MX6SX_PAD_QSPI1B_SS0_B__SIM_M_HADDR_10                    0x01B8 0x0500 0x0000 0x7 0x0
+#define MX6SX_PAD_QSPI1B_SS1_B__QSPI1_B_SS1_B                     0x01BC 0x0504 0x0000 0x0 0x0
+#define MX6SX_PAD_QSPI1B_SS1_B__CAN2_RX                           0x01BC 0x0504 0x0690 0x1 0x2
+#define MX6SX_PAD_QSPI1B_SS1_B__CANFD_RX2                         0x01BC 0x0504 0x0698 0x2 0x2
+#define MX6SX_PAD_QSPI1B_SS1_B__ECSPI5_SCLK                       0x01BC 0x0504 0x0750 0x3 0x1
+#define MX6SX_PAD_QSPI1B_SS1_B__CSI1_DATA_18                      0x01BC 0x0504 0x06E4 0x4 0x1
+#define MX6SX_PAD_QSPI1B_SS1_B__GPIO4_IO_31                       0x01BC 0x0504 0x0000 0x5 0x0
+#define MX6SX_PAD_QSPI1B_SS1_B__WEIM_DATA_10                      0x01BC 0x0504 0x0000 0x6 0x0
+#define MX6SX_PAD_QSPI1B_SS1_B__SIM_M_HADDR_14                    0x01BC 0x0504 0x0000 0x7 0x0
+#define MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0                     0x01C0 0x0508 0x0000 0x0 0x0
+#define MX6SX_PAD_RGMII1_RD0__GPIO5_IO_0                          0x01C0 0x0508 0x0000 0x5 0x0
+#define MX6SX_PAD_RGMII1_RD0__CSI2_DATA_10                        0x01C0 0x0508 0x0000 0x6 0x0
+#define MX6SX_PAD_RGMII1_RD0__ANATOP_TESTI_0                      0x01C0 0x0508 0x0000 0x7 0x0
+#define MX6SX_PAD_RGMII1_RD0__RAWNAND_TESTER_TRIGGER              0x01C0 0x0508 0x0000 0x8 0x0
+#define MX6SX_PAD_RGMII1_RD0__PCIE_CTRL_DEBUG_0                   0x01C0 0x0508 0x0000 0x9 0x0
+#define MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1                     0x01C4 0x050C 0x0000 0x0 0x0
+#define MX6SX_PAD_RGMII1_RD1__GPIO5_IO_1                          0x01C4 0x050C 0x0000 0x5 0x0
+#define MX6SX_PAD_RGMII1_RD1__CSI2_DATA_11                        0x01C4 0x050C 0x0000 0x6 0x0
+#define MX6SX_PAD_RGMII1_RD1__ANATOP_TESTI_1                      0x01C4 0x050C 0x0000 0x7 0x0
+#define MX6SX_PAD_RGMII1_RD1__USDHC1_TESTER_TRIGGER               0x01C4 0x050C 0x0000 0x8 0x0
+#define MX6SX_PAD_RGMII1_RD1__PCIE_CTRL_DEBUG_1                   0x01C4 0x050C 0x0000 0x9 0x0
+#define MX6SX_PAD_RGMII1_RD2__ENET1_RX_DATA_2                     0x01C8 0x0510 0x0000 0x0 0x0
+#define MX6SX_PAD_RGMII1_RD2__GPIO5_IO_2                          0x01C8 0x0510 0x0000 0x5 0x0
+#define MX6SX_PAD_RGMII1_RD2__CSI2_DATA_12                        0x01C8 0x0510 0x0000 0x6 0x0
+#define MX6SX_PAD_RGMII1_RD2__ANATOP_TESTI_2                      0x01C8 0x0510 0x0000 0x7 0x0
+#define MX6SX_PAD_RGMII1_RD2__USDHC2_TESTER_TRIGGER               0x01C8 0x0510 0x0000 0x8 0x0
+#define MX6SX_PAD_RGMII1_RD2__PCIE_CTRL_DEBUG_2                   0x01C8 0x0510 0x0000 0x9 0x0
+#define MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3                     0x01CC 0x0514 0x0000 0x0 0x0
+#define MX6SX_PAD_RGMII1_RD3__GPIO5_IO_3                          0x01CC 0x0514 0x0000 0x5 0x0
+#define MX6SX_PAD_RGMII1_RD3__CSI2_DATA_13                        0x01CC 0x0514 0x0000 0x6 0x0
+#define MX6SX_PAD_RGMII1_RD3__ANATOP_TESTI_3                      0x01CC 0x0514 0x0000 0x7 0x0
+#define MX6SX_PAD_RGMII1_RD3__USDHC3_TESTER_TRIGGER               0x01CC 0x0514 0x0000 0x8 0x0
+#define MX6SX_PAD_RGMII1_RD3__PCIE_CTRL_DEBUG_3                   0x01CC 0x0514 0x0000 0x9 0x0
+#define MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN                      0x01D0 0x0518 0x0000 0x0 0x0
+#define MX6SX_PAD_RGMII1_RX_CTL__GPIO5_IO_4                       0x01D0 0x0518 0x0000 0x5 0x0
+#define MX6SX_PAD_RGMII1_RX_CTL__CSI2_DATA_14                     0x01D0 0x0518 0x0000 0x6 0x0
+#define MX6SX_PAD_RGMII1_RX_CTL__ANATOP_TESTO_0                   0x01D0 0x0518 0x0000 0x7 0x0
+#define MX6SX_PAD_RGMII1_RX_CTL__USDHC4_TESTER_TRIGGER            0x01D0 0x0518 0x0000 0x8 0x0
+#define MX6SX_PAD_RGMII1_RX_CTL__PCIE_CTRL_DEBUG_4                0x01D0 0x0518 0x0000 0x9 0x0
+#define MX6SX_PAD_RGMII1_RXC__ENET1_RX_CLK                        0x01D4 0x051C 0x0768 0x0 0x1
+#define MX6SX_PAD_RGMII1_RXC__ENET1_RX_ER                         0x01D4 0x051C 0x0000 0x1 0x0
+#define MX6SX_PAD_RGMII1_RXC__GPIO5_IO_5                          0x01D4 0x051C 0x0000 0x5 0x0
+#define MX6SX_PAD_RGMII1_RXC__CSI2_DATA_15                        0x01D4 0x051C 0x0000 0x6 0x0
+#define MX6SX_PAD_RGMII1_RXC__ANATOP_TESTO_1                      0x01D4 0x051C 0x0000 0x7 0x0
+#define MX6SX_PAD_RGMII1_RXC__ECSPI1_TESTER_TRIGGER               0x01D4 0x051C 0x0000 0x8 0x0
+#define MX6SX_PAD_RGMII1_RXC__PCIE_CTRL_DEBUG_5                   0x01D4 0x051C 0x0000 0x9 0x0
+#define MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0                     0x01D8 0x0520 0x0000 0x0 0x0
+#define MX6SX_PAD_RGMII1_TD0__SAI2_RX_SYNC                        0x01D8 0x0520 0x0810 0x2 0x1
+#define MX6SX_PAD_RGMII1_TD0__GPIO5_IO_6                          0x01D8 0x0520 0x0000 0x5 0x0
+#define MX6SX_PAD_RGMII1_TD0__CSI2_DATA_16                        0x01D8 0x0520 0x0000 0x6 0x0
+#define MX6SX_PAD_RGMII1_TD0__ANATOP_TESTO_2                      0x01D8 0x0520 0x0000 0x7 0x0
+#define MX6SX_PAD_RGMII1_TD0__ECSPI2_TESTER_TRIGGER               0x01D8 0x0520 0x0000 0x8 0x0
+#define MX6SX_PAD_RGMII1_TD0__PCIE_CTRL_DEBUG_6                   0x01D8 0x0520 0x0000 0x9 0x0
+#define MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1                     0x01DC 0x0524 0x0000 0x0 0x0
+#define MX6SX_PAD_RGMII1_TD1__SAI2_RX_BCLK                        0x01DC 0x0524 0x0808 0x2 0x1
+#define MX6SX_PAD_RGMII1_TD1__GPIO5_IO_7                          0x01DC 0x0524 0x0000 0x5 0x0
+#define MX6SX_PAD_RGMII1_TD1__CSI2_DATA_17                        0x01DC 0x0524 0x0000 0x6 0x0
+#define MX6SX_PAD_RGMII1_TD1__ANATOP_TESTO_3                      0x01DC 0x0524 0x0000 0x7 0x0
+#define MX6SX_PAD_RGMII1_TD1__ECSPI3_TESTER_TRIGGER               0x01DC 0x0524 0x0000 0x8 0x0
+#define MX6SX_PAD_RGMII1_TD1__PCIE_CTRL_DEBUG_7                   0x01DC 0x0524 0x0000 0x9 0x0
+#define MX6SX_PAD_RGMII1_TD2__ENET1_TX_DATA_2                     0x01E0 0x0528 0x0000 0x0 0x0
+#define MX6SX_PAD_RGMII1_TD2__SAI2_TX_SYNC                        0x01E0 0x0528 0x0818 0x2 0x1
+#define MX6SX_PAD_RGMII1_TD2__GPIO5_IO_8                          0x01E0 0x0528 0x0000 0x5 0x0
+#define MX6SX_PAD_RGMII1_TD2__CSI2_DATA_18                        0x01E0 0x0528 0x0000 0x6 0x0
+#define MX6SX_PAD_RGMII1_TD2__ANATOP_TESTO_4                      0x01E0 0x0528 0x0000 0x7 0x0
+#define MX6SX_PAD_RGMII1_TD2__ECSPI4_TESTER_TRIGGER               0x01E0 0x0528 0x0000 0x8 0x0
+#define MX6SX_PAD_RGMII1_TD2__PCIE_CTRL_DEBUG_8                   0x01E0 0x0528 0x0000 0x9 0x0
+#define MX6SX_PAD_RGMII1_TD3__ENET1_TX_DATA_3                     0x01E4 0x052C 0x0000 0x0 0x0
+#define MX6SX_PAD_RGMII1_TD3__SAI2_TX_BCLK                        0x01E4 0x052C 0x0814 0x2 0x1
+#define MX6SX_PAD_RGMII1_TD3__GPIO5_IO_9                          0x01E4 0x052C 0x0000 0x5 0x0
+#define MX6SX_PAD_RGMII1_TD3__CSI2_DATA_19                        0x01E4 0x052C 0x0000 0x6 0x0
+#define MX6SX_PAD_RGMII1_TD3__ANATOP_TESTO_5                      0x01E4 0x052C 0x0000 0x7 0x0
+#define MX6SX_PAD_RGMII1_TD3__ECSPI5_TESTER_TRIGGER               0x01E4 0x052C 0x0000 0x8 0x0
+#define MX6SX_PAD_RGMII1_TD3__PCIE_CTRL_DEBUG_9                   0x01E4 0x052C 0x0000 0x9 0x0
+#define MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN                      0x01E8 0x0530 0x0000 0x0 0x0
+#define MX6SX_PAD_RGMII1_TX_CTL__SAI2_RX_DATA_0                   0x01E8 0x0530 0x080C 0x2 0x1
+#define MX6SX_PAD_RGMII1_TX_CTL__GPIO5_IO_10                      0x01E8 0x0530 0x0000 0x5 0x0
+#define MX6SX_PAD_RGMII1_TX_CTL__CSI2_DATA_0                      0x01E8 0x0530 0x0000 0x6 0x0
+#define MX6SX_PAD_RGMII1_TX_CTL__ANATOP_TESTO_6                   0x01E8 0x0530 0x0000 0x7 0x0
+#define MX6SX_PAD_RGMII1_TX_CTL__QSPI1_TESTER_TRIGGER             0x01E8 0x0530 0x0000 0x8 0x0
+#define MX6SX_PAD_RGMII1_TX_CTL__PCIE_CTRL_DEBUG_10               0x01E8 0x0530 0x0000 0x9 0x0
+#define MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC                     0x01EC 0x0534 0x0000 0x0 0x0
+#define MX6SX_PAD_RGMII1_TXC__ENET1_TX_ER                         0x01EC 0x0534 0x0000 0x1 0x0
+#define MX6SX_PAD_RGMII1_TXC__SAI2_TX_DATA_0                      0x01EC 0x0534 0x0000 0x2 0x0
+#define MX6SX_PAD_RGMII1_TXC__GPIO5_IO_11                         0x01EC 0x0534 0x0000 0x5 0x0
+#define MX6SX_PAD_RGMII1_TXC__CSI2_DATA_1                         0x01EC 0x0534 0x0000 0x6 0x0
+#define MX6SX_PAD_RGMII1_TXC__ANATOP_TESTO_7                      0x01EC 0x0534 0x0000 0x7 0x0
+#define MX6SX_PAD_RGMII1_TXC__QSPI2_TESTER_TRIGGER                0x01EC 0x0534 0x0000 0x8 0x0
+#define MX6SX_PAD_RGMII1_TXC__PCIE_CTRL_DEBUG_11                  0x01EC 0x0534 0x0000 0x9 0x0
+#define MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0                     0x01F0 0x0538 0x0000 0x0 0x0
+#define MX6SX_PAD_RGMII2_RD0__PWM4_OUT                            0x01F0 0x0538 0x0000 0x2 0x0
+#define MX6SX_PAD_RGMII2_RD0__GPIO5_IO_12                         0x01F0 0x0538 0x0000 0x5 0x0
+#define MX6SX_PAD_RGMII2_RD0__CSI2_DATA_2                         0x01F0 0x0538 0x0000 0x6 0x0
+#define MX6SX_PAD_RGMII2_RD0__ANATOP_TESTO_8                      0x01F0 0x0538 0x0000 0x7 0x0
+#define MX6SX_PAD_RGMII2_RD0__VDEC_DEBUG_18                       0x01F0 0x0538 0x0000 0x8 0x0
+#define MX6SX_PAD_RGMII2_RD0__PCIE_CTRL_DEBUG_12                  0x01F0 0x0538 0x0000 0x9 0x0
+#define MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1                     0x01F4 0x053C 0x0000 0x0 0x0
+#define MX6SX_PAD_RGMII2_RD1__PWM3_OUT                            0x01F4 0x053C 0x0000 0x2 0x0
+#define MX6SX_PAD_RGMII2_RD1__GPIO5_IO_13                         0x01F4 0x053C 0x0000 0x5 0x0
+#define MX6SX_PAD_RGMII2_RD1__CSI2_DATA_3                         0x01F4 0x053C 0x0000 0x6 0x0
+#define MX6SX_PAD_RGMII2_RD1__ANATOP_TESTO_9                      0x01F4 0x053C 0x0000 0x7 0x0
+#define MX6SX_PAD_RGMII2_RD1__VDEC_DEBUG_19                       0x01F4 0x053C 0x0000 0x8 0x0
+#define MX6SX_PAD_RGMII2_RD1__PCIE_CTRL_DEBUG_13                  0x01F4 0x053C 0x0000 0x9 0x0
+#define MX6SX_PAD_RGMII2_RD2__ENET2_RX_DATA_2                     0x01F8 0x0540 0x0000 0x0 0x0
+#define MX6SX_PAD_RGMII2_RD2__PWM2_OUT                            0x01F8 0x0540 0x0000 0x2 0x0
+#define MX6SX_PAD_RGMII2_RD2__GPIO5_IO_14                         0x01F8 0x0540 0x0000 0x5 0x0
+#define MX6SX_PAD_RGMII2_RD2__CSI2_DATA_4                         0x01F8 0x0540 0x0000 0x6 0x0
+#define MX6SX_PAD_RGMII2_RD2__ANATOP_TESTO_10                     0x01F8 0x0540 0x0000 0x7 0x0
+#define MX6SX_PAD_RGMII2_RD2__VDEC_DEBUG_20                       0x01F8 0x0540 0x0000 0x8 0x0
+#define MX6SX_PAD_RGMII2_RD2__PCIE_CTRL_DEBUG_14                  0x01F8 0x0540 0x0000 0x9 0x0
+#define MX6SX_PAD_RGMII2_RD3__ENET2_RX_DATA_3                     0x01FC 0x0544 0x0000 0x0 0x0
+#define MX6SX_PAD_RGMII2_RD3__PWM1_OUT                            0x01FC 0x0544 0x0000 0x2 0x0
+#define MX6SX_PAD_RGMII2_RD3__GPIO5_IO_15                         0x01FC 0x0544 0x0000 0x5 0x0
+#define MX6SX_PAD_RGMII2_RD3__CSI2_DATA_5                         0x01FC 0x0544 0x0000 0x6 0x0
+#define MX6SX_PAD_RGMII2_RD3__ANATOP_TESTO_11                     0x01FC 0x0544 0x0000 0x7 0x0
+#define MX6SX_PAD_RGMII2_RD3__VDEC_DEBUG_21                       0x01FC 0x0544 0x0000 0x8 0x0
+#define MX6SX_PAD_RGMII2_RD3__PCIE_CTRL_DEBUG_15                  0x01FC 0x0544 0x0000 0x9 0x0
+#define MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN                      0x0200 0x0548 0x0000 0x0 0x0
+#define MX6SX_PAD_RGMII2_RX_CTL__GPIO5_IO_16                      0x0200 0x0548 0x0000 0x5 0x0
+#define MX6SX_PAD_RGMII2_RX_CTL__CSI2_DATA_6                      0x0200 0x0548 0x0000 0x6 0x0
+#define MX6SX_PAD_RGMII2_RX_CTL__ANATOP_TESTO_12                  0x0200 0x0548 0x0000 0x7 0x0
+#define MX6SX_PAD_RGMII2_RX_CTL__VDEC_DEBUG_22                    0x0200 0x0548 0x0000 0x8 0x0
+#define MX6SX_PAD_RGMII2_RX_CTL__PCIE_CTRL_DEBUG_16               0x0200 0x0548 0x0000 0x9 0x0
+#define MX6SX_PAD_RGMII2_RXC__ENET2_RX_CLK                        0x0204 0x054C 0x0774 0x0 0x1
+#define MX6SX_PAD_RGMII2_RXC__ENET2_RX_ER                         0x0204 0x054C 0x0000 0x1 0x0
+#define MX6SX_PAD_RGMII2_RXC__GPIO5_IO_17                         0x0204 0x054C 0x0000 0x5 0x0
+#define MX6SX_PAD_RGMII2_RXC__CSI2_DATA_7                         0x0204 0x054C 0x0000 0x6 0x0
+#define MX6SX_PAD_RGMII2_RXC__ANATOP_TESTO_13                     0x0204 0x054C 0x0000 0x7 0x0
+#define MX6SX_PAD_RGMII2_RXC__VDEC_DEBUG_23                       0x0204 0x054C 0x0000 0x8 0x0
+#define MX6SX_PAD_RGMII2_RXC__PCIE_CTRL_DEBUG_17                  0x0204 0x054C 0x0000 0x9 0x0
+#define MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0                     0x0208 0x0550 0x0000 0x0 0x0
+#define MX6SX_PAD_RGMII2_TD0__SAI1_RX_SYNC                        0x0208 0x0550 0x07FC 0x2 0x1
+#define MX6SX_PAD_RGMII2_TD0__PWM8_OUT                            0x0208 0x0550 0x0000 0x3 0x0
+#define MX6SX_PAD_RGMII2_TD0__GPIO5_IO_18                         0x0208 0x0550 0x0000 0x5 0x0
+#define MX6SX_PAD_RGMII2_TD0__CSI2_DATA_8                         0x0208 0x0550 0x0000 0x6 0x0
+#define MX6SX_PAD_RGMII2_TD0__ANATOP_TESTO_14                     0x0208 0x0550 0x0000 0x7 0x0
+#define MX6SX_PAD_RGMII2_TD0__VDEC_DEBUG_24                       0x0208 0x0550 0x0000 0x8 0x0
+#define MX6SX_PAD_RGMII2_TD0__PCIE_CTRL_DEBUG_18                  0x0208 0x0550 0x0000 0x9 0x0
+#define MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1                     0x020C 0x0554 0x0000 0x0 0x0
+#define MX6SX_PAD_RGMII2_TD1__SAI1_RX_BCLK                        0x020C 0x0554 0x07F4 0x2 0x1
+#define MX6SX_PAD_RGMII2_TD1__PWM7_OUT                            0x020C 0x0554 0x0000 0x3 0x0
+#define MX6SX_PAD_RGMII2_TD1__GPIO5_IO_19                         0x020C 0x0554 0x0000 0x5 0x0
+#define MX6SX_PAD_RGMII2_TD1__CSI2_DATA_9                         0x020C 0x0554 0x0000 0x6 0x0
+#define MX6SX_PAD_RGMII2_TD1__ANATOP_TESTO_15                     0x020C 0x0554 0x0000 0x7 0x0
+#define MX6SX_PAD_RGMII2_TD1__VDEC_DEBUG_25                       0x020C 0x0554 0x0000 0x8 0x0
+#define MX6SX_PAD_RGMII2_TD1__PCIE_CTRL_DEBUG_19                  0x020C 0x0554 0x0000 0x9 0x0
+#define MX6SX_PAD_RGMII2_TD2__ENET2_TX_DATA_2                     0x0210 0x0558 0x0000 0x0 0x0
+#define MX6SX_PAD_RGMII2_TD2__SAI1_TX_SYNC                        0x0210 0x0558 0x0804 0x2 0x1
+#define MX6SX_PAD_RGMII2_TD2__PWM6_OUT                            0x0210 0x0558 0x0000 0x3 0x0
+#define MX6SX_PAD_RGMII2_TD2__GPIO5_IO_20                         0x0210 0x0558 0x0000 0x5 0x0
+#define MX6SX_PAD_RGMII2_TD2__CSI2_VSYNC                          0x0210 0x0558 0x0000 0x6 0x0
+#define MX6SX_PAD_RGMII2_TD2__SJC_FAIL                            0x0210 0x0558 0x0000 0x7 0x0
+#define MX6SX_PAD_RGMII2_TD2__VDEC_DEBUG_26                       0x0210 0x0558 0x0000 0x8 0x0
+#define MX6SX_PAD_RGMII2_TD2__PCIE_CTRL_DEBUG_20                  0x0210 0x0558 0x0000 0x9 0x0
+#define MX6SX_PAD_RGMII2_TD3__ENET2_TX_DATA_3                     0x0214 0x055C 0x0000 0x0 0x0
+#define MX6SX_PAD_RGMII2_TD3__SAI1_TX_BCLK                        0x0214 0x055C 0x0800 0x2 0x1
+#define MX6SX_PAD_RGMII2_TD3__PWM5_OUT                            0x0214 0x055C 0x0000 0x3 0x0
+#define MX6SX_PAD_RGMII2_TD3__GPIO5_IO_21                         0x0214 0x055C 0x0000 0x5 0x0
+#define MX6SX_PAD_RGMII2_TD3__CSI2_HSYNC                          0x0214 0x055C 0x0000 0x6 0x0
+#define MX6SX_PAD_RGMII2_TD3__SJC_JTAG_ACT                        0x0214 0x055C 0x0000 0x7 0x0
+#define MX6SX_PAD_RGMII2_TD3__VDEC_DEBUG_27                       0x0214 0x055C 0x0000 0x8 0x0
+#define MX6SX_PAD_RGMII2_TD3__PCIE_CTRL_DEBUG_21                  0x0214 0x055C 0x0000 0x9 0x0
+#define MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN                      0x0218 0x0560 0x0000 0x0 0x0
+#define MX6SX_PAD_RGMII2_TX_CTL__SAI1_RX_DATA_0                   0x0218 0x0560 0x07F8 0x2 0x1
+#define MX6SX_PAD_RGMII2_TX_CTL__GPIO5_IO_22                      0x0218 0x0560 0x0000 0x5 0x0
+#define MX6SX_PAD_RGMII2_TX_CTL__CSI2_FIELD                       0x0218 0x0560 0x0000 0x6 0x0
+#define MX6SX_PAD_RGMII2_TX_CTL__SJC_DE_B                         0x0218 0x0560 0x0000 0x7 0x0
+#define MX6SX_PAD_RGMII2_TX_CTL__VDEC_DEBUG_28                    0x0218 0x0560 0x0000 0x8 0x0
+#define MX6SX_PAD_RGMII2_TX_CTL__PCIE_CTRL_DEBUG_22               0x0218 0x0560 0x0000 0x9 0x0
+#define MX6SX_PAD_RGMII2_TXC__ENET2_RGMII_TXC                     0x021C 0x0564 0x0000 0x0 0x0
+#define MX6SX_PAD_RGMII2_TXC__ENET2_TX_ER                         0x021C 0x0564 0x0000 0x1 0x0
+#define MX6SX_PAD_RGMII2_TXC__SAI1_TX_DATA_0                      0x021C 0x0564 0x0000 0x2 0x0
+#define MX6SX_PAD_RGMII2_TXC__GPIO5_IO_23                         0x021C 0x0564 0x0000 0x5 0x0
+#define MX6SX_PAD_RGMII2_TXC__CSI2_PIXCLK                         0x021C 0x0564 0x0000 0x6 0x0
+#define MX6SX_PAD_RGMII2_TXC__SJC_DONE                            0x021C 0x0564 0x0000 0x7 0x0
+#define MX6SX_PAD_RGMII2_TXC__VDEC_DEBUG_29                       0x021C 0x0564 0x0000 0x8 0x0
+#define MX6SX_PAD_RGMII2_TXC__PCIE_CTRL_DEBUG_23                  0x021C 0x0564 0x0000 0x9 0x0
+#define MX6SX_PAD_SD1_CLK__USDHC1_CLK                             0x0220 0x0568 0x0000 0x0 0x0
+#define MX6SX_PAD_SD1_CLK__AUDMUX_AUD5_RXFS                       0x0220 0x0568 0x0668 0x1 0x1
+#define MX6SX_PAD_SD1_CLK__WDOG2_WDOG_B                           0x0220 0x0568 0x0000 0x2 0x0
+#define MX6SX_PAD_SD1_CLK__GPT_CLK                                0x0220 0x0568 0x0000 0x3 0x0
+#define MX6SX_PAD_SD1_CLK__WDOG2_WDOG_RST_B_DEB                   0x0220 0x0568 0x0000 0x4 0x0
+#define MX6SX_PAD_SD1_CLK__GPIO6_IO_0                             0x0220 0x0568 0x0000 0x5 0x0
+#define MX6SX_PAD_SD1_CLK__ENET2_1588_EVENT1_OUT                  0x0220 0x0568 0x0000 0x6 0x0
+#define MX6SX_PAD_SD1_CLK__CCM_OUT1                               0x0220 0x0568 0x0000 0x7 0x0
+#define MX6SX_PAD_SD1_CLK__VADC_ADC_PROC_CLK                      0x0220 0x0568 0x0000 0x8 0x0
+#define MX6SX_PAD_SD1_CLK__MMDC_DEBUG_45                          0x0220 0x0568 0x0000 0x9 0x0
+#define MX6SX_PAD_SD1_CMD__USDHC1_CMD                             0x0224 0x056C 0x0000 0x0 0x0
+#define MX6SX_PAD_SD1_CMD__AUDMUX_AUD5_RXC                        0x0224 0x056C 0x0664 0x1 0x1
+#define MX6SX_PAD_SD1_CMD__WDOG1_WDOG_B                           0x0224 0x056C 0x0000 0x2 0x0
+#define MX6SX_PAD_SD1_CMD__GPT_COMPARE1                           0x0224 0x056C 0x0000 0x3 0x0
+#define MX6SX_PAD_SD1_CMD__WDOG1_WDOG_RST_B_DEB                   0x0224 0x056C 0x0000 0x4 0x0
+#define MX6SX_PAD_SD1_CMD__GPIO6_IO_1                             0x0224 0x056C 0x0000 0x5 0x0
+#define MX6SX_PAD_SD1_CMD__ENET2_1588_EVENT1_IN                   0x0224 0x056C 0x0000 0x6 0x0
+#define MX6SX_PAD_SD1_CMD__CCM_CLKO1                              0x0224 0x056C 0x0000 0x7 0x0
+#define MX6SX_PAD_SD1_CMD__VADC_EXT_SYSCLK                        0x0224 0x056C 0x0000 0x8 0x0
+#define MX6SX_PAD_SD1_CMD__MMDC_DEBUG_46                          0x0224 0x056C 0x0000 0x9 0x0
+#define MX6SX_PAD_SD1_DATA0__USDHC1_DATA0                         0x0228 0x0570 0x0000 0x0 0x0
+#define MX6SX_PAD_SD1_DATA0__AUDMUX_AUD5_RXD                      0x0228 0x0570 0x065C 0x1 0x1
+#define MX6SX_PAD_SD1_DATA0__CAAM_WRAPPER_RNG_OSC_OBS             0x0228 0x0570 0x0000 0x2 0x0
+#define MX6SX_PAD_SD1_DATA0__GPT_CAPTURE1                         0x0228 0x0570 0x0000 0x3 0x0
+#define MX6SX_PAD_SD1_DATA0__UART2_RX                             0x0228 0x0570 0x0838 0x4 0x2
+#define MX6SX_PAD_SD1_DATA0__UART2_TX                             0x0228 0x0570 0x0000 0x4 0x0
+#define MX6SX_PAD_SD1_DATA0__GPIO6_IO_2                           0x0228 0x0570 0x0000 0x5 0x0
+#define MX6SX_PAD_SD1_DATA0__ENET1_1588_EVENT1_IN                 0x0228 0x0570 0x0000 0x6 0x0
+#define MX6SX_PAD_SD1_DATA0__CCM_OUT2                             0x0228 0x0570 0x0000 0x7 0x0
+#define MX6SX_PAD_SD1_DATA0__VADC_CLAMP_UP                        0x0228 0x0570 0x0000 0x8 0x0
+#define MX6SX_PAD_SD1_DATA0__MMDC_DEBUG_48                        0x0228 0x0570 0x0000 0x9 0x0
+#define MX6SX_PAD_SD1_DATA1__USDHC1_DATA1                         0x022C 0x0574 0x0000 0x0 0x0
+#define MX6SX_PAD_SD1_DATA1__AUDMUX_AUD5_TXC                      0x022C 0x0574 0x066C 0x1 0x1
+#define MX6SX_PAD_SD1_DATA1__PWM4_OUT                             0x022C 0x0574 0x0000 0x2 0x0
+#define MX6SX_PAD_SD1_DATA1__GPT_CAPTURE2                         0x022C 0x0574 0x0000 0x3 0x0
+#define MX6SX_PAD_SD1_DATA1__UART2_RX                             0x022C 0x0574 0x0838 0x4 0x3
+#define MX6SX_PAD_SD1_DATA1__UART2_TX                             0x022C 0x0574 0x0000 0x4 0x0
+#define MX6SX_PAD_SD1_DATA1__GPIO6_IO_3                           0x022C 0x0574 0x0000 0x5 0x0
+#define MX6SX_PAD_SD1_DATA1__ENET1_1588_EVENT1_OUT                0x022C 0x0574 0x0000 0x6 0x0
+#define MX6SX_PAD_SD1_DATA1__CCM_CLKO2                            0x022C 0x0574 0x0000 0x7 0x0
+#define MX6SX_PAD_SD1_DATA1__VADC_CLAMP_DOWN                      0x022C 0x0574 0x0000 0x8 0x0
+#define MX6SX_PAD_SD1_DATA1__MMDC_DEBUG_47                        0x022C 0x0574 0x0000 0x9 0x0
+#define MX6SX_PAD_SD1_DATA2__USDHC1_DATA2                         0x0230 0x0578 0x0000 0x0 0x0
+#define MX6SX_PAD_SD1_DATA2__AUDMUX_AUD5_TXFS                     0x0230 0x0578 0x0670 0x1 0x1
+#define MX6SX_PAD_SD1_DATA2__PWM3_OUT                             0x0230 0x0578 0x0000 0x2 0x0
+#define MX6SX_PAD_SD1_DATA2__GPT_COMPARE2                         0x0230 0x0578 0x0000 0x3 0x0
+#define MX6SX_PAD_SD1_DATA2__UART2_CTS_B                          0x0230 0x0578 0x0000 0x4 0x0
+#define MX6SX_PAD_SD1_DATA2__UART2_RTS_B                          0x0230 0x0578 0x0834 0x4 0x2
+#define MX6SX_PAD_SD1_DATA2__GPIO6_IO_4                           0x0230 0x0578 0x0000 0x5 0x0
+#define MX6SX_PAD_SD1_DATA2__ECSPI4_RDY                           0x0230 0x0578 0x0000 0x6 0x0
+#define MX6SX_PAD_SD1_DATA2__CCM_OUT0                             0x0230 0x0578 0x0000 0x7 0x0
+#define MX6SX_PAD_SD1_DATA2__VADC_EXT_PD_N                        0x0230 0x0578 0x0000 0x8 0x0
+#define MX6SX_PAD_SD1_DATA3__USDHC1_DATA3                         0x0234 0x057C 0x0000 0x0 0x0
+#define MX6SX_PAD_SD1_DATA3__AUDMUX_AUD5_TXD                      0x0234 0x057C 0x0660 0x1 0x1
+#define MX6SX_PAD_SD1_DATA3__AUDMUX_AUD5_RXD                      0x0234 0x057C 0x065C 0x2 0x2
+#define MX6SX_PAD_SD1_DATA3__GPT_COMPARE3                         0x0234 0x057C 0x0000 0x3 0x0
+#define MX6SX_PAD_SD1_DATA3__UART2_RTS_B                          0x0234 0x057C 0x0834 0x4 0x3
+#define MX6SX_PAD_SD1_DATA3__UART2_CTS_B                          0x0234 0x057C 0x0000 0x4 0x0
+#define MX6SX_PAD_SD1_DATA3__GPIO6_IO_5                           0x0234 0x057C 0x0000 0x5 0x0
+#define MX6SX_PAD_SD1_DATA3__ECSPI4_SS1                           0x0234 0x057C 0x0000 0x6 0x0
+#define MX6SX_PAD_SD1_DATA3__CCM_PMIC_RDY                         0x0234 0x057C 0x069C 0x7 0x2
+#define MX6SX_PAD_SD1_DATA3__VADC_RST_N                           0x0234 0x057C 0x0000 0x8 0x0
+#define MX6SX_PAD_SD2_CLK__USDHC2_CLK                             0x0238 0x0580 0x0000 0x0 0x0
+#define MX6SX_PAD_SD2_CLK__AUDMUX_AUD6_RXFS                       0x0238 0x0580 0x0680 0x1 0x2
+#define MX6SX_PAD_SD2_CLK__KPP_COL_5                              0x0238 0x0580 0x07C8 0x2 0x1
+#define MX6SX_PAD_SD2_CLK__ECSPI4_SCLK                            0x0238 0x0580 0x0740 0x3 0x1
+#define MX6SX_PAD_SD2_CLK__MLB_SIG                                0x0238 0x0580 0x07F0 0x4 0x2
+#define MX6SX_PAD_SD2_CLK__GPIO6_IO_6                             0x0238 0x0580 0x0000 0x5 0x0
+#define MX6SX_PAD_SD2_CLK__MQS_RIGHT                              0x0238 0x0580 0x0000 0x6 0x0
+#define MX6SX_PAD_SD2_CLK__WDOG1_WDOG_ANY                         0x0238 0x0580 0x0000 0x7 0x0
+#define MX6SX_PAD_SD2_CLK__VADC_CLAMP_CURRENT_5                   0x0238 0x0580 0x0000 0x8 0x0
+#define MX6SX_PAD_SD2_CLK__MMDC_DEBUG_29                          0x0238 0x0580 0x0000 0x9 0x0
+#define MX6SX_PAD_SD2_CMD__USDHC2_CMD                             0x023C 0x0584 0x0000 0x0 0x0
+#define MX6SX_PAD_SD2_CMD__AUDMUX_AUD6_RXC                        0x023C 0x0584 0x067C 0x1 0x2
+#define MX6SX_PAD_SD2_CMD__KPP_ROW_5                              0x023C 0x0584 0x07D4 0x2 0x1
+#define MX6SX_PAD_SD2_CMD__ECSPI4_MOSI                            0x023C 0x0584 0x0748 0x3 0x1
+#define MX6SX_PAD_SD2_CMD__MLB_CLK                                0x023C 0x0584 0x07E8 0x4 0x2
+#define MX6SX_PAD_SD2_CMD__GPIO6_IO_7                             0x023C 0x0584 0x0000 0x5 0x0
+#define MX6SX_PAD_SD2_CMD__MQS_LEFT                               0x023C 0x0584 0x0000 0x6 0x0
+#define MX6SX_PAD_SD2_CMD__WDOG3_WDOG_B                           0x023C 0x0584 0x0000 0x7 0x0
+#define MX6SX_PAD_SD2_CMD__VADC_CLAMP_CURRENT_4                   0x023C 0x0584 0x0000 0x8 0x0
+#define MX6SX_PAD_SD2_CMD__MMDC_DEBUG_30                          0x023C 0x0584 0x0000 0x9 0x0
+#define MX6SX_PAD_SD2_DATA0__USDHC2_DATA0                         0x0240 0x0588 0x0000 0x0 0x0
+#define MX6SX_PAD_SD2_DATA0__AUDMUX_AUD6_RXD                      0x0240 0x0588 0x0674 0x1 0x2
+#define MX6SX_PAD_SD2_DATA0__KPP_ROW_7                            0x0240 0x0588 0x07DC 0x2 0x1
+#define MX6SX_PAD_SD2_DATA0__PWM1_OUT                             0x0240 0x0588 0x0000 0x3 0x0
+#define MX6SX_PAD_SD2_DATA0__I2C4_SDA                             0x0240 0x0588 0x07C4 0x4 0x3
+#define MX6SX_PAD_SD2_DATA0__GPIO6_IO_8                           0x0240 0x0588 0x0000 0x5 0x0
+#define MX6SX_PAD_SD2_DATA0__ECSPI4_SS3                           0x0240 0x0588 0x0000 0x6 0x0
+#define MX6SX_PAD_SD2_DATA0__UART4_RX                             0x0240 0x0588 0x0848 0x7 0x4
+#define MX6SX_PAD_SD2_DATA0__UART4_TX                             0x0240 0x0588 0x0000 0x7 0x0
+#define MX6SX_PAD_SD2_DATA0__VADC_CLAMP_CURRENT_0                 0x0240 0x0588 0x0000 0x8 0x0
+#define MX6SX_PAD_SD2_DATA0__MMDC_DEBUG_50                        0x0240 0x0588 0x0000 0x9 0x0
+#define MX6SX_PAD_SD2_DATA1__USDHC2_DATA1                         0x0244 0x058C 0x0000 0x0 0x0
+#define MX6SX_PAD_SD2_DATA1__AUDMUX_AUD6_TXC                      0x0244 0x058C 0x0684 0x1 0x2
+#define MX6SX_PAD_SD2_DATA1__KPP_COL_7                            0x0244 0x058C 0x07D0 0x2 0x1
+#define MX6SX_PAD_SD2_DATA1__PWM2_OUT                             0x0244 0x058C 0x0000 0x3 0x0
+#define MX6SX_PAD_SD2_DATA1__I2C4_SCL                             0x0244 0x058C 0x07C0 0x4 0x3
+#define MX6SX_PAD_SD2_DATA1__GPIO6_IO_9                           0x0244 0x058C 0x0000 0x5 0x0
+#define MX6SX_PAD_SD2_DATA1__ECSPI4_SS2                           0x0244 0x058C 0x0000 0x6 0x0
+#define MX6SX_PAD_SD2_DATA1__UART4_RX                             0x0244 0x058C 0x0848 0x7 0x5
+#define MX6SX_PAD_SD2_DATA1__UART4_TX                             0x0244 0x058C 0x0000 0x7 0x0
+#define MX6SX_PAD_SD2_DATA1__VADC_CLAMP_CURRENT_1                 0x0244 0x058C 0x0000 0x8 0x0
+#define MX6SX_PAD_SD2_DATA1__MMDC_DEBUG_49                        0x0244 0x058C 0x0000 0x9 0x0
+#define MX6SX_PAD_SD2_DATA2__USDHC2_DATA2                         0x0248 0x0590 0x0000 0x0 0x0
+#define MX6SX_PAD_SD2_DATA2__AUDMUX_AUD6_TXFS                     0x0248 0x0590 0x0688 0x1 0x2
+#define MX6SX_PAD_SD2_DATA2__KPP_ROW_6                            0x0248 0x0590 0x07D8 0x2 0x1
+#define MX6SX_PAD_SD2_DATA2__ECSPI4_SS0                           0x0248 0x0590 0x074C 0x3 0x1
+#define MX6SX_PAD_SD2_DATA2__SDMA_EXT_EVENT_0                     0x0248 0x0590 0x081C 0x4 0x2
+#define MX6SX_PAD_SD2_DATA2__GPIO6_IO_10                          0x0248 0x0590 0x0000 0x5 0x0
+#define MX6SX_PAD_SD2_DATA2__SPDIF_OUT                            0x0248 0x0590 0x0000 0x6 0x0
+#define MX6SX_PAD_SD2_DATA2__UART6_RX                             0x0248 0x0590 0x0858 0x7 0x4
+#define MX6SX_PAD_SD2_DATA2__UART6_TX                             0x0248 0x0590 0x0000 0x7 0x0
+#define MX6SX_PAD_SD2_DATA2__VADC_CLAMP_CURRENT_2                 0x0248 0x0590 0x0000 0x8 0x0
+#define MX6SX_PAD_SD2_DATA2__MMDC_DEBUG_32                        0x0248 0x0590 0x0000 0x9 0x0
+#define MX6SX_PAD_SD2_DATA3__USDHC2_DATA3                         0x024C 0x0594 0x0000 0x0 0x0
+#define MX6SX_PAD_SD2_DATA3__AUDMUX_AUD6_TXD                      0x024C 0x0594 0x0678 0x1 0x2
+#define MX6SX_PAD_SD2_DATA3__KPP_COL_6                            0x024C 0x0594 0x07CC 0x2 0x1
+#define MX6SX_PAD_SD2_DATA3__ECSPI4_MISO                          0x024C 0x0594 0x0744 0x3 0x1
+#define MX6SX_PAD_SD2_DATA3__MLB_DATA                             0x024C 0x0594 0x07EC 0x4 0x2
+#define MX6SX_PAD_SD2_DATA3__GPIO6_IO_11                          0x024C 0x0594 0x0000 0x5 0x0
+#define MX6SX_PAD_SD2_DATA3__SPDIF_IN                             0x024C 0x0594 0x0824 0x6 0x4
+#define MX6SX_PAD_SD2_DATA3__UART6_RX                             0x024C 0x0594 0x0858 0x7 0x5
+#define MX6SX_PAD_SD2_DATA3__UART6_TX                             0x024C 0x0594 0x0000 0x7 0x0
+#define MX6SX_PAD_SD2_DATA3__VADC_CLAMP_CURRENT_3                 0x024C 0x0594 0x0000 0x8 0x0
+#define MX6SX_PAD_SD2_DATA3__MMDC_DEBUG_31                        0x024C 0x0594 0x0000 0x9 0x0
+#define MX6SX_PAD_SD3_CLK__USDHC3_CLK                             0x0250 0x0598 0x0000 0x0 0x0
+#define MX6SX_PAD_SD3_CLK__UART4_CTS_B                            0x0250 0x0598 0x0000 0x1 0x0
+#define MX6SX_PAD_SD3_CLK__UART4_RTS_B                            0x0250 0x0598 0x0844 0x1 0x0
+#define MX6SX_PAD_SD3_CLK__ECSPI4_SCLK                            0x0250 0x0598 0x0740 0x2 0x0
+#define MX6SX_PAD_SD3_CLK__AUDMUX_AUD6_RXFS                       0x0250 0x0598 0x0680 0x3 0x0
+#define MX6SX_PAD_SD3_CLK__LCDIF2_VSYNC                           0x0250 0x0598 0x0000 0x4 0x0
+#define MX6SX_PAD_SD3_CLK__GPIO7_IO_0                             0x0250 0x0598 0x0000 0x5 0x0
+#define MX6SX_PAD_SD3_CLK__LCDIF2_BUSY                            0x0250 0x0598 0x07E4 0x6 0x0
+#define MX6SX_PAD_SD3_CLK__TPSMP_HDATA_29                         0x0250 0x0598 0x0000 0x7 0x0
+#define MX6SX_PAD_SD3_CLK__SDMA_DEBUG_EVENT_CHANNEL_5             0x0250 0x0598 0x0000 0x9 0x0
+#define MX6SX_PAD_SD3_CMD__USDHC3_CMD                             0x0254 0x059C 0x0000 0x0 0x0
+#define MX6SX_PAD_SD3_CMD__UART4_RX                               0x0254 0x059C 0x0848 0x1 0x0
+#define MX6SX_PAD_SD3_CMD__UART4_TX                               0x0254 0x059C 0x0000 0x1 0x0
+#define MX6SX_PAD_SD3_CMD__ECSPI4_MOSI                            0x0254 0x059C 0x0748 0x2 0x0
+#define MX6SX_PAD_SD3_CMD__AUDMUX_AUD6_RXC                        0x0254 0x059C 0x067C 0x3 0x0
+#define MX6SX_PAD_SD3_CMD__LCDIF2_HSYNC                           0x0254 0x059C 0x07E4 0x4 0x1
+#define MX6SX_PAD_SD3_CMD__GPIO7_IO_1                             0x0254 0x059C 0x0000 0x5 0x0
+#define MX6SX_PAD_SD3_CMD__LCDIF2_RS                              0x0254 0x059C 0x0000 0x6 0x0
+#define MX6SX_PAD_SD3_CMD__TPSMP_HDATA_28                         0x0254 0x059C 0x0000 0x7 0x0
+#define MX6SX_PAD_SD3_CMD__SDMA_DEBUG_EVENT_CHANNEL_4             0x0254 0x059C 0x0000 0x9 0x0
+#define MX6SX_PAD_SD3_DATA0__USDHC3_DATA0                         0x0258 0x05A0 0x0000 0x0 0x0
+#define MX6SX_PAD_SD3_DATA0__I2C4_SCL                             0x0258 0x05A0 0x07C0 0x1 0x0
+#define MX6SX_PAD_SD3_DATA0__ECSPI2_SS1                           0x0258 0x05A0 0x0000 0x2 0x0
+#define MX6SX_PAD_SD3_DATA0__AUDMUX_AUD6_RXD                      0x0258 0x05A0 0x0674 0x3 0x0
+#define MX6SX_PAD_SD3_DATA0__LCDIF2_DATA_1                        0x0258 0x05A0 0x0000 0x4 0x0
+#define MX6SX_PAD_SD3_DATA0__GPIO7_IO_2                           0x0258 0x05A0 0x0000 0x5 0x0
+#define MX6SX_PAD_SD3_DATA0__DCIC1_OUT                            0x0258 0x05A0 0x0000 0x6 0x0
+#define MX6SX_PAD_SD3_DATA0__TPSMP_HDATA_30                       0x0258 0x05A0 0x0000 0x7 0x0
+#define MX6SX_PAD_SD3_DATA0__GPU_DEBUG_0                          0x0258 0x05A0 0x0000 0x8 0x0
+#define MX6SX_PAD_SD3_DATA0__SDMA_DEBUG_EVT_CHN_LINES_0           0x0258 0x05A0 0x0000 0x9 0x0
+#define MX6SX_PAD_SD3_DATA1__USDHC3_DATA1                         0x025C 0x05A4 0x0000 0x0 0x0
+#define MX6SX_PAD_SD3_DATA1__I2C4_SDA                             0x025C 0x05A4 0x07C4 0x1 0x0
+#define MX6SX_PAD_SD3_DATA1__ECSPI2_SS2                           0x025C 0x05A4 0x0000 0x2 0x0
+#define MX6SX_PAD_SD3_DATA1__AUDMUX_AUD6_TXC                      0x025C 0x05A4 0x0684 0x3 0x0
+#define MX6SX_PAD_SD3_DATA1__LCDIF2_DATA_0                        0x025C 0x05A4 0x0000 0x4 0x0
+#define MX6SX_PAD_SD3_DATA1__GPIO7_IO_3                           0x025C 0x05A4 0x0000 0x5 0x0
+#define MX6SX_PAD_SD3_DATA1__DCIC2_OUT                            0x025C 0x05A4 0x0000 0x6 0x0
+#define MX6SX_PAD_SD3_DATA1__TPSMP_HDATA_31                       0x025C 0x05A4 0x0000 0x7 0x0
+#define MX6SX_PAD_SD3_DATA1__GPU_DEBUG_1                          0x025C 0x05A4 0x0000 0x8 0x0
+#define MX6SX_PAD_SD3_DATA1__SDMA_DEBUG_EVT_CHN_LINES_1           0x025C 0x05A4 0x0000 0x9 0x0
+#define MX6SX_PAD_SD3_DATA2__USDHC3_DATA2                         0x0260 0x05A8 0x0000 0x0 0x0
+#define MX6SX_PAD_SD3_DATA2__UART4_RTS_B                          0x0260 0x05A8 0x0844 0x1 0x1
+#define MX6SX_PAD_SD3_DATA2__UART4_CTS_B                          0x0260 0x05A8 0x0000 0x1 0x0
+#define MX6SX_PAD_SD3_DATA2__ECSPI4_SS0                           0x0260 0x05A8 0x074C 0x2 0x0
+#define MX6SX_PAD_SD3_DATA2__AUDMUX_AUD6_TXFS                     0x0260 0x05A8 0x0688 0x3 0x0
+#define MX6SX_PAD_SD3_DATA2__LCDIF2_CLK                           0x0260 0x05A8 0x0000 0x4 0x0
+#define MX6SX_PAD_SD3_DATA2__GPIO7_IO_4                           0x0260 0x05A8 0x0000 0x5 0x0
+#define MX6SX_PAD_SD3_DATA2__LCDIF2_WR_RWN                        0x0260 0x05A8 0x0000 0x6 0x0
+#define MX6SX_PAD_SD3_DATA2__TPSMP_HDATA_26                       0x0260 0x05A8 0x0000 0x7 0x0
+#define MX6SX_PAD_SD3_DATA2__GPU_DEBUG_2                          0x0260 0x05A8 0x0000 0x8 0x0
+#define MX6SX_PAD_SD3_DATA2__SDMA_DEBUG_EVENT_CHANNEL_2           0x0260 0x05A8 0x0000 0x9 0x0
+#define MX6SX_PAD_SD3_DATA3__USDHC3_DATA3                         0x0264 0x05AC 0x0000 0x0 0x0
+#define MX6SX_PAD_SD3_DATA3__UART4_RX                             0x0264 0x05AC 0x0848 0x1 0x1
+#define MX6SX_PAD_SD3_DATA3__UART4_TX                             0x0264 0x05AC 0x0000 0x1 0x0
+#define MX6SX_PAD_SD3_DATA3__ECSPI4_MISO                          0x0264 0x05AC 0x0744 0x2 0x0
+#define MX6SX_PAD_SD3_DATA3__AUDMUX_AUD6_TXD                      0x0264 0x05AC 0x0678 0x3 0x0
+#define MX6SX_PAD_SD3_DATA3__LCDIF2_ENABLE                        0x0264 0x05AC 0x0000 0x4 0x0
+#define MX6SX_PAD_SD3_DATA3__GPIO7_IO_5                           0x0264 0x05AC 0x0000 0x5 0x0
+#define MX6SX_PAD_SD3_DATA3__LCDIF2_RD_E                          0x0264 0x05AC 0x0000 0x6 0x0
+#define MX6SX_PAD_SD3_DATA3__TPSMP_HDATA_27                       0x0264 0x05AC 0x0000 0x7 0x0
+#define MX6SX_PAD_SD3_DATA3__GPU_DEBUG_3                          0x0264 0x05AC 0x0000 0x8 0x0
+#define MX6SX_PAD_SD3_DATA3__SDMA_DEBUG_EVENT_CHANNEL_3           0x0264 0x05AC 0x0000 0x9 0x0
+#define MX6SX_PAD_SD3_DATA4__USDHC3_DATA4                         0x0268 0x05B0 0x0000 0x0 0x0
+#define MX6SX_PAD_SD3_DATA4__CAN2_RX                              0x0268 0x05B0 0x0690 0x1 0x0
+#define MX6SX_PAD_SD3_DATA4__CANFD_RX2                            0x0268 0x05B0 0x0698 0x2 0x0
+#define MX6SX_PAD_SD3_DATA4__UART3_RX                             0x0268 0x05B0 0x0840 0x3 0x2
+#define MX6SX_PAD_SD3_DATA4__UART3_TX                             0x0268 0x05B0 0x0000 0x3 0x0
+#define MX6SX_PAD_SD3_DATA4__LCDIF2_DATA_3                        0x0268 0x05B0 0x0000 0x4 0x0
+#define MX6SX_PAD_SD3_DATA4__GPIO7_IO_6                           0x0268 0x05B0 0x0000 0x5 0x0
+#define MX6SX_PAD_SD3_DATA4__ENET2_1588_EVENT0_IN                 0x0268 0x05B0 0x0000 0x6 0x0
+#define MX6SX_PAD_SD3_DATA4__TPSMP_HTRANS_1                       0x0268 0x05B0 0x0000 0x7 0x0
+#define MX6SX_PAD_SD3_DATA4__GPU_DEBUG_4                          0x0268 0x05B0 0x0000 0x8 0x0
+#define MX6SX_PAD_SD3_DATA4__SDMA_DEBUG_BUS_DEVICE_0              0x0268 0x05B0 0x0000 0x9 0x0
+#define MX6SX_PAD_SD3_DATA5__USDHC3_DATA5                         0x026C 0x05B4 0x0000 0x0 0x0
+#define MX6SX_PAD_SD3_DATA5__CAN1_TX                              0x026C 0x05B4 0x0000 0x1 0x0
+#define MX6SX_PAD_SD3_DATA5__CANFD_TX1                            0x026C 0x05B4 0x0000 0x2 0x0
+#define MX6SX_PAD_SD3_DATA5__UART3_RX                             0x026C 0x05B4 0x0840 0x3 0x3
+#define MX6SX_PAD_SD3_DATA5__UART3_TX                             0x026C 0x05B4 0x0000 0x3 0x0
+#define MX6SX_PAD_SD3_DATA5__LCDIF2_DATA_2                        0x026C 0x05B4 0x0000 0x4 0x0
+#define MX6SX_PAD_SD3_DATA5__GPIO7_IO_7                           0x026C 0x05B4 0x0000 0x5 0x0
+#define MX6SX_PAD_SD3_DATA5__ENET2_1588_EVENT0_OUT                0x026C 0x05B4 0x0000 0x6 0x0
+#define MX6SX_PAD_SD3_DATA5__SIM_M_HWRITE                         0x026C 0x05B4 0x0000 0x7 0x0
+#define MX6SX_PAD_SD3_DATA5__GPU_DEBUG_5                          0x026C 0x05B4 0x0000 0x8 0x0
+#define MX6SX_PAD_SD3_DATA5__SDMA_DEBUG_BUS_DEVICE_1              0x026C 0x05B4 0x0000 0x9 0x0
+#define MX6SX_PAD_SD3_DATA6__USDHC3_DATA6                         0x0270 0x05B8 0x0000 0x0 0x0
+#define MX6SX_PAD_SD3_DATA6__CAN2_TX                              0x0270 0x05B8 0x0000 0x1 0x0
+#define MX6SX_PAD_SD3_DATA6__CANFD_TX2                            0x0270 0x05B8 0x0000 0x2 0x0
+#define MX6SX_PAD_SD3_DATA6__UART3_RTS_B                          0x0270 0x05B8 0x083C 0x3 0x2
+#define MX6SX_PAD_SD3_DATA6__UART3_CTS_B                          0x0270 0x05B8 0x0000 0x3 0x0
+#define MX6SX_PAD_SD3_DATA6__LCDIF2_DATA_4                        0x0270 0x05B8 0x0000 0x4 0x0
+#define MX6SX_PAD_SD3_DATA6__GPIO7_IO_8                           0x0270 0x05B8 0x0000 0x5 0x0
+#define MX6SX_PAD_SD3_DATA6__ENET1_1588_EVENT0_OUT                0x0270 0x05B8 0x0000 0x6 0x0
+#define MX6SX_PAD_SD3_DATA6__TPSMP_HTRANS_0                       0x0270 0x05B8 0x0000 0x7 0x0
+#define MX6SX_PAD_SD3_DATA6__GPU_DEBUG_7                          0x0270 0x05B8 0x0000 0x8 0x0
+#define MX6SX_PAD_SD3_DATA6__SDMA_DEBUG_EVT_CHN_LINES_7           0x0270 0x05B8 0x0000 0x9 0x0
+#define MX6SX_PAD_SD3_DATA7__USDHC3_DATA7                         0x0274 0x05BC 0x0000 0x0 0x0
+#define MX6SX_PAD_SD3_DATA7__CAN1_RX                              0x0274 0x05BC 0x068C 0x1 0x0
+#define MX6SX_PAD_SD3_DATA7__CANFD_RX1                            0x0274 0x05BC 0x0694 0x2 0x0
+#define MX6SX_PAD_SD3_DATA7__UART3_CTS_B                          0x0274 0x05BC 0x0000 0x3 0x0
+#define MX6SX_PAD_SD3_DATA7__UART3_RTS_B                          0x0274 0x05BC 0x083C 0x3 0x3
+#define MX6SX_PAD_SD3_DATA7__LCDIF2_DATA_5                        0x0274 0x05BC 0x0000 0x4 0x0
+#define MX6SX_PAD_SD3_DATA7__GPIO7_IO_9                           0x0274 0x05BC 0x0000 0x5 0x0
+#define MX6SX_PAD_SD3_DATA7__ENET1_1588_EVENT0_IN                 0x0274 0x05BC 0x0000 0x6 0x0
+#define MX6SX_PAD_SD3_DATA7__TPSMP_HDATA_DIR                      0x0274 0x05BC 0x0000 0x7 0x0
+#define MX6SX_PAD_SD3_DATA7__GPU_DEBUG_6                          0x0274 0x05BC 0x0000 0x8 0x0
+#define MX6SX_PAD_SD3_DATA7__SDMA_DEBUG_EVT_CHN_LINES_2           0x0274 0x05BC 0x0000 0x9 0x0
+#define MX6SX_PAD_SD4_CLK__USDHC4_CLK                             0x0278 0x05C0 0x0000 0x0 0x0
+#define MX6SX_PAD_SD4_CLK__RAWNAND_DATA15                         0x0278 0x05C0 0x0000 0x1 0x0
+#define MX6SX_PAD_SD4_CLK__ECSPI2_MISO                            0x0278 0x05C0 0x0724 0x2 0x1
+#define MX6SX_PAD_SD4_CLK__AUDMUX_AUD3_RXFS                       0x0278 0x05C0 0x0638 0x3 0x0
+#define MX6SX_PAD_SD4_CLK__LCDIF2_DATA_13                         0x0278 0x05C0 0x0000 0x4 0x0
+#define MX6SX_PAD_SD4_CLK__GPIO6_IO_12                            0x0278 0x05C0 0x0000 0x5 0x0
+#define MX6SX_PAD_SD4_CLK__ECSPI3_SS2                             0x0278 0x05C0 0x0000 0x6 0x0
+#define MX6SX_PAD_SD4_CLK__TPSMP_HDATA_20                         0x0278 0x05C0 0x0000 0x7 0x0
+#define MX6SX_PAD_SD4_CLK__VDEC_DEBUG_12                          0x0278 0x05C0 0x0000 0x8 0x0
+#define MX6SX_PAD_SD4_CLK__SDMA_DEBUG_EVENT_CHANNEL_SEL           0x0278 0x05C0 0x0000 0x9 0x0
+#define MX6SX_PAD_SD4_CMD__USDHC4_CMD                             0x027C 0x05C4 0x0000 0x0 0x0
+#define MX6SX_PAD_SD4_CMD__RAWNAND_DATA14                         0x027C 0x05C4 0x0000 0x1 0x0
+#define MX6SX_PAD_SD4_CMD__ECSPI2_MOSI                            0x027C 0x05C4 0x0728 0x2 0x1
+#define MX6SX_PAD_SD4_CMD__AUDMUX_AUD3_RXC                        0x027C 0x05C4 0x0634 0x3 0x0
+#define MX6SX_PAD_SD4_CMD__LCDIF2_DATA_14                         0x027C 0x05C4 0x0000 0x4 0x0
+#define MX6SX_PAD_SD4_CMD__GPIO6_IO_13                            0x027C 0x05C4 0x0000 0x5 0x0
+#define MX6SX_PAD_SD4_CMD__ECSPI3_SS1                             0x027C 0x05C4 0x0000 0x6 0x0
+#define MX6SX_PAD_SD4_CMD__TPSMP_HDATA_19                         0x027C 0x05C4 0x0000 0x7 0x0
+#define MX6SX_PAD_SD4_CMD__VDEC_DEBUG_11                          0x027C 0x05C4 0x0000 0x8 0x0
+#define MX6SX_PAD_SD4_CMD__SDMA_DEBUG_CORE_RUN                    0x027C 0x05C4 0x0000 0x9 0x0
+#define MX6SX_PAD_SD4_DATA0__USDHC4_DATA0                         0x0280 0x05C8 0x0000 0x0 0x0
+#define MX6SX_PAD_SD4_DATA0__RAWNAND_DATA10                       0x0280 0x05C8 0x0000 0x1 0x0
+#define MX6SX_PAD_SD4_DATA0__ECSPI2_SS0                           0x0280 0x05C8 0x072C 0x2 0x1
+#define MX6SX_PAD_SD4_DATA0__AUDMUX_AUD3_RXD                      0x0280 0x05C8 0x062C 0x3 0x0
+#define MX6SX_PAD_SD4_DATA0__LCDIF2_DATA_12                       0x0280 0x05C8 0x0000 0x4 0x0
+#define MX6SX_PAD_SD4_DATA0__GPIO6_IO_14                          0x0280 0x05C8 0x0000 0x5 0x0
+#define MX6SX_PAD_SD4_DATA0__ECSPI3_SS3                           0x0280 0x05C8 0x0000 0x6 0x0
+#define MX6SX_PAD_SD4_DATA0__TPSMP_HDATA_21                       0x0280 0x05C8 0x0000 0x7 0x0
+#define MX6SX_PAD_SD4_DATA0__VDEC_DEBUG_13                        0x0280 0x05C8 0x0000 0x8 0x0
+#define MX6SX_PAD_SD4_DATA0__SDMA_DEBUG_MODE                      0x0280 0x05C8 0x0000 0x9 0x0
+#define MX6SX_PAD_SD4_DATA1__USDHC4_DATA1                         0x0284 0x05CC 0x0000 0x0 0x0
+#define MX6SX_PAD_SD4_DATA1__RAWNAND_DATA11                       0x0284 0x05CC 0x0000 0x1 0x0
+#define MX6SX_PAD_SD4_DATA1__ECSPI2_SCLK                          0x0284 0x05CC 0x0720 0x2 0x1
+#define MX6SX_PAD_SD4_DATA1__AUDMUX_AUD3_TXC                      0x0284 0x05CC 0x063C 0x3 0x0
+#define MX6SX_PAD_SD4_DATA1__LCDIF2_DATA_11                       0x0284 0x05CC 0x0000 0x4 0x0
+#define MX6SX_PAD_SD4_DATA1__GPIO6_IO_15                          0x0284 0x05CC 0x0000 0x5 0x0
+#define MX6SX_PAD_SD4_DATA1__ECSPI3_RDY                           0x0284 0x05CC 0x0000 0x6 0x0
+#define MX6SX_PAD_SD4_DATA1__TPSMP_HDATA_22                       0x0284 0x05CC 0x0000 0x7 0x0
+#define MX6SX_PAD_SD4_DATA1__VDEC_DEBUG_14                        0x0284 0x05CC 0x0000 0x8 0x0
+#define MX6SX_PAD_SD4_DATA1__SDMA_DEBUG_BUS_ERROR                 0x0284 0x05CC 0x0000 0x9 0x0
+#define MX6SX_PAD_SD4_DATA2__USDHC4_DATA2                         0x0288 0x05D0 0x0000 0x0 0x0
+#define MX6SX_PAD_SD4_DATA2__RAWNAND_DATA12                       0x0288 0x05D0 0x0000 0x1 0x0
+#define MX6SX_PAD_SD4_DATA2__I2C2_SDA                             0x0288 0x05D0 0x07B4 0x2 0x0
+#define MX6SX_PAD_SD4_DATA2__AUDMUX_AUD3_TXFS                     0x0288 0x05D0 0x0640 0x3 0x0
+#define MX6SX_PAD_SD4_DATA2__LCDIF2_DATA_10                       0x0288 0x05D0 0x0000 0x4 0x0
+#define MX6SX_PAD_SD4_DATA2__GPIO6_IO_16                          0x0288 0x05D0 0x0000 0x5 0x0
+#define MX6SX_PAD_SD4_DATA2__ECSPI2_SS3                           0x0288 0x05D0 0x0000 0x6 0x0
+#define MX6SX_PAD_SD4_DATA2__TPSMP_HDATA_23                       0x0288 0x05D0 0x0000 0x7 0x0
+#define MX6SX_PAD_SD4_DATA2__VDEC_DEBUG_15                        0x0288 0x05D0 0x0000 0x8 0x0
+#define MX6SX_PAD_SD4_DATA2__SDMA_DEBUG_BUS_RWB                   0x0288 0x05D0 0x0000 0x9 0x0
+#define MX6SX_PAD_SD4_DATA3__USDHC4_DATA3                         0x028C 0x05D4 0x0000 0x0 0x0
+#define MX6SX_PAD_SD4_DATA3__RAWNAND_DATA13                       0x028C 0x05D4 0x0000 0x1 0x0
+#define MX6SX_PAD_SD4_DATA3__I2C2_SCL                             0x028C 0x05D4 0x07B0 0x2 0x0
+#define MX6SX_PAD_SD4_DATA3__AUDMUX_AUD3_TXD                      0x028C 0x05D4 0x0630 0x3 0x0
+#define MX6SX_PAD_SD4_DATA3__LCDIF2_DATA_9                        0x028C 0x05D4 0x0000 0x4 0x0
+#define MX6SX_PAD_SD4_DATA3__GPIO6_IO_17                          0x028C 0x05D4 0x0000 0x5 0x0
+#define MX6SX_PAD_SD4_DATA3__ECSPI2_RDY                           0x028C 0x05D4 0x0000 0x6 0x0
+#define MX6SX_PAD_SD4_DATA3__TPSMP_HDATA_24                       0x028C 0x05D4 0x0000 0x7 0x0
+#define MX6SX_PAD_SD4_DATA3__VDEC_DEBUG_16                        0x028C 0x05D4 0x0000 0x8 0x0
+#define MX6SX_PAD_SD4_DATA3__SDMA_DEBUG_MATCHED_DMBUS             0x028C 0x05D4 0x0000 0x9 0x0
+#define MX6SX_PAD_SD4_DATA4__USDHC4_DATA4                         0x0290 0x05D8 0x0000 0x0 0x0
+#define MX6SX_PAD_SD4_DATA4__RAWNAND_DATA09                       0x0290 0x05D8 0x0000 0x1 0x0
+#define MX6SX_PAD_SD4_DATA4__UART5_RX                             0x0290 0x05D8 0x0850 0x2 0x0
+#define MX6SX_PAD_SD4_DATA4__UART5_TX                             0x0290 0x05D8 0x0000 0x2 0x0
+#define MX6SX_PAD_SD4_DATA4__ECSPI3_SCLK                          0x0290 0x05D8 0x0730 0x3 0x0
+#define MX6SX_PAD_SD4_DATA4__LCDIF2_DATA_8                        0x0290 0x05D8 0x0000 0x4 0x0
+#define MX6SX_PAD_SD4_DATA4__GPIO6_IO_18                          0x0290 0x05D8 0x0000 0x5 0x0
+#define MX6SX_PAD_SD4_DATA4__SPDIF_OUT                            0x0290 0x05D8 0x0000 0x6 0x0
+#define MX6SX_PAD_SD4_DATA4__TPSMP_HDATA_16                       0x0290 0x05D8 0x0000 0x7 0x0
+#define MX6SX_PAD_SD4_DATA4__USB_OTG_HOST_MODE                    0x0290 0x05D8 0x0000 0x8 0x0
+#define MX6SX_PAD_SD4_DATA4__SDMA_DEBUG_RTBUFFER_WRITE            0x0290 0x05D8 0x0000 0x9 0x0
+#define MX6SX_PAD_SD4_DATA5__USDHC4_DATA5                         0x0294 0x05DC 0x0000 0x0 0x0
+#define MX6SX_PAD_SD4_DATA5__RAWNAND_CE2_B                        0x0294 0x05DC 0x0000 0x1 0x0
+#define MX6SX_PAD_SD4_DATA5__UART5_RX                             0x0294 0x05DC 0x0850 0x2 0x1
+#define MX6SX_PAD_SD4_DATA5__UART5_TX                             0x0294 0x05DC 0x0000 0x2 0x0
+#define MX6SX_PAD_SD4_DATA5__ECSPI3_MOSI                          0x0294 0x05DC 0x0738 0x3 0x0
+#define MX6SX_PAD_SD4_DATA5__LCDIF2_DATA_7                        0x0294 0x05DC 0x0000 0x4 0x0
+#define MX6SX_PAD_SD4_DATA5__GPIO6_IO_19                          0x0294 0x05DC 0x0000 0x5 0x0
+#define MX6SX_PAD_SD4_DATA5__SPDIF_IN                             0x0294 0x05DC 0x0824 0x6 0x0
+#define MX6SX_PAD_SD4_DATA5__TPSMP_HDATA_17                       0x0294 0x05DC 0x0000 0x7 0x0
+#define MX6SX_PAD_SD4_DATA5__VDEC_DEBUG_9                         0x0294 0x05DC 0x0000 0x8 0x0
+#define MX6SX_PAD_SD4_DATA5__SDMA_DEBUG_EVENT_CHANNEL_0           0x0294 0x05DC 0x0000 0x9 0x0
+#define MX6SX_PAD_SD4_DATA6__USDHC4_DATA6                         0x0298 0x05E0 0x0000 0x0 0x0
+#define MX6SX_PAD_SD4_DATA6__RAWNAND_CE3_B                        0x0298 0x05E0 0x0000 0x1 0x0
+#define MX6SX_PAD_SD4_DATA6__UART5_RTS_B                          0x0298 0x05E0 0x084C 0x2 0x0
+#define MX6SX_PAD_SD4_DATA6__UART5_CTS_B                          0x0298 0x05E0 0x0000 0x2 0x0
+#define MX6SX_PAD_SD4_DATA6__ECSPI3_MISO                          0x0298 0x05E0 0x0734 0x3 0x0
+#define MX6SX_PAD_SD4_DATA6__LCDIF2_DATA_6                        0x0298 0x05E0 0x0000 0x4 0x0
+#define MX6SX_PAD_SD4_DATA6__GPIO6_IO_20                          0x0298 0x05E0 0x0000 0x5 0x0
+#define MX6SX_PAD_SD4_DATA6__USDHC4_WP                            0x0298 0x05E0 0x0878 0x6 0x0
+#define MX6SX_PAD_SD4_DATA6__TPSMP_HDATA_18                       0x0298 0x05E0 0x0000 0x7 0x0
+#define MX6SX_PAD_SD4_DATA6__VDEC_DEBUG_10                        0x0298 0x05E0 0x0000 0x8 0x0
+#define MX6SX_PAD_SD4_DATA6__SDMA_DEBUG_EVENT_CHANNEL_1           0x0298 0x05E0 0x0000 0x9 0x0
+#define MX6SX_PAD_SD4_DATA7__USDHC4_DATA7                         0x029C 0x05E4 0x0000 0x0 0x0
+#define MX6SX_PAD_SD4_DATA7__RAWNAND_DATA08                       0x029C 0x05E4 0x0000 0x1 0x0
+#define MX6SX_PAD_SD4_DATA7__UART5_CTS_B                          0x029C 0x05E4 0x0000 0x2 0x0
+#define MX6SX_PAD_SD4_DATA7__UART5_RTS_B                          0x029C 0x05E4 0x084C 0x2 0x1
+#define MX6SX_PAD_SD4_DATA7__ECSPI3_SS0                           0x029C 0x05E4 0x073C 0x3 0x0
+#define MX6SX_PAD_SD4_DATA7__LCDIF2_DATA_15                       0x029C 0x05E4 0x0000 0x4 0x0
+#define MX6SX_PAD_SD4_DATA7__GPIO6_IO_21                          0x029C 0x05E4 0x0000 0x5 0x0
+#define MX6SX_PAD_SD4_DATA7__USDHC4_CD_B                          0x029C 0x05E4 0x0874 0x6 0x0
+#define MX6SX_PAD_SD4_DATA7__TPSMP_HDATA_15                       0x029C 0x05E4 0x0000 0x7 0x0
+#define MX6SX_PAD_SD4_DATA7__USB_OTG_PWR_WAKE                     0x029C 0x05E4 0x0000 0x8 0x0
+#define MX6SX_PAD_SD4_DATA7__SDMA_DEBUG_YIELD                     0x029C 0x05E4 0x0000 0x9 0x0
+#define MX6SX_PAD_SD4_RESET_B__USDHC4_RESET_B                     0x02A0 0x05E8 0x0000 0x0 0x0
+#define MX6SX_PAD_SD4_RESET_B__RAWNAND_DQS                        0x02A0 0x05E8 0x0000 0x1 0x0
+#define MX6SX_PAD_SD4_RESET_B__USDHC4_RESET                       0x02A0 0x05E8 0x0000 0x2 0x0
+#define MX6SX_PAD_SD4_RESET_B__AUDMUX_MCLK                        0x02A0 0x05E8 0x0000 0x3 0x0
+#define MX6SX_PAD_SD4_RESET_B__LCDIF2_RESET                       0x02A0 0x05E8 0x0000 0x4 0x0
+#define MX6SX_PAD_SD4_RESET_B__GPIO6_IO_22                        0x02A0 0x05E8 0x0000 0x5 0x0
+#define MX6SX_PAD_SD4_RESET_B__LCDIF2_CS                          0x02A0 0x05E8 0x0000 0x6 0x0
+#define MX6SX_PAD_SD4_RESET_B__TPSMP_HDATA_25                     0x02A0 0x05E8 0x0000 0x7 0x0
+#define MX6SX_PAD_SD4_RESET_B__VDEC_DEBUG_17                      0x02A0 0x05E8 0x0000 0x8 0x0
+#define MX6SX_PAD_SD4_RESET_B__SDMA_DEBUG_BUS_DEVICE_2            0x02A0 0x05E8 0x0000 0x9 0x0
+#define MX6SX_PAD_USB_H_DATA__USB_H_DATA                          0x02A4 0x05EC 0x0000 0x0 0x0
+#define MX6SX_PAD_USB_H_DATA__PWM2_OUT                            0x02A4 0x05EC 0x0000 0x1 0x0
+#define MX6SX_PAD_USB_H_DATA__ANATOP_24M_OUT                      0x02A4 0x05EC 0x0000 0x2 0x0
+#define MX6SX_PAD_USB_H_DATA__I2C4_SDA                            0x02A4 0x05EC 0x07C4 0x3 0x1
+#define MX6SX_PAD_USB_H_DATA__WDOG3_WDOG_B                        0x02A4 0x05EC 0x0000 0x4 0x0
+#define MX6SX_PAD_USB_H_DATA__GPIO7_IO_10                         0x02A4 0x05EC 0x0000 0x5 0x0
+#define MX6SX_PAD_USB_H_STROBE__USB_H_STROBE                      0x02A8 0x05F0 0x0000 0x0 0x0
+#define MX6SX_PAD_USB_H_STROBE__PWM1_OUT                          0x02A8 0x05F0 0x0000 0x1 0x0
+#define MX6SX_PAD_USB_H_STROBE__ANATOP_32K_OUT                    0x02A8 0x05F0 0x0000 0x2 0x0
+#define MX6SX_PAD_USB_H_STROBE__I2C4_SCL                          0x02A8 0x05F0 0x07C0 0x3 0x1
+#define MX6SX_PAD_USB_H_STROBE__WDOG3_WDOG_RST_B_DEB              0x02A8 0x05F0 0x0000 0x4 0x0
+#define MX6SX_PAD_USB_H_STROBE__GPIO7_IO_11                       0x02A8 0x05F0 0x0000 0x5 0x0
+
+#endif /* __DTS_IMX6SX_PINFUNC_H */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/imx6ul-pinfunc.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/imx6ul-pinfunc.h
new file mode 100644
index 0000000000000000000000000000000000000000..046c94879f6363dcf527c11bfe5145976b684fae
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/imx6ul-pinfunc.h
@@ -0,0 +1,963 @@
+/*
+ * Copyright 2014 - 2015 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __DTS_IMX6UL_PINFUNC_H
+#define __DTS_IMX6UL_PINFUNC_H
+
+/*
+ * The pin function ID is a tuple of
+ * <mux_reg conf_reg input_reg mux_mode input_val>
+ */
+#define MX6UL_PAD_BOOT_MODE0__GPIO5_IO10		0x0014 0x02a0 0x0000 5 0
+#define MX6UL_PAD_BOOT_MODE1__GPIO5_IO11		0x0018 0x02a4 0x0000 5 0
+
+#define MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00		0x001c 0x02a8 0x0000 5 0
+#define MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01		0x0020 0x02ac 0x0000 5 0
+#define MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02		0x0024 0x02b0 0x0000 5 0
+#define MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03		0x0028 0x02b4 0x0000 5 0
+#define MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04		0x002c 0x02b8 0x0000 5 0
+#define MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05		0x0030 0x02bc 0x0000 5 0
+#define MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06		0x0034 0x02c0 0x0000 5 0
+#define MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07		0x0038 0x02c4 0x0000 5 0
+#define MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08		0x003c 0x02c8 0x0000 5 0
+#define MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09		0x0040 0x02cc 0x0000 5 0
+
+#define MX6UL_PAD_JTAG_MOD__SJC_MOD			0x0044 0x02d0 0x0000 0 0
+#define MX6UL_PAD_JTAG_MOD__GPT2_CLK			0x0044 0x02d0 0x05a0 1 0
+#define MX6UL_PAD_JTAG_MOD__SPDIF_OUT			0x0044 0x02d0 0x0000 2 0
+#define MX6UL_PAD_JTAG_MOD__ENET1_REF_CLK_25M		0x0044 0x02d0 0x0000 3 0
+#define MX6UL_PAD_JTAG_MOD__CCM_PMIC_RDY		0x0044 0x02d0 0x04c0 4 0
+#define MX6UL_PAD_JTAG_MOD__GPIO1_IO10			0x0044 0x02d0 0x0000 5 0
+#define MX6UL_PAD_JTAG_MOD__SDMA_EXT_EVENT00		0x0044 0x02d0 0x0610 6 0
+#define MX6UL_PAD_JTAG_TMS__SJC_TMS			0x0048 0x02d4 0x0000 0 0
+#define MX6UL_PAD_JTAG_TMS__GPT2_CAPTURE1		0x0048 0x02d4 0x0598 1 0
+#define MX6UL_PAD_JTAG_TMS__SAI2_MCLK			0x0048 0x02d4 0x05f0 2 0
+#define MX6UL_PAD_JTAG_TMS__CCM_CLKO1			0x0048 0x02d4 0x0000 3 0
+#define MX6UL_PAD_JTAG_TMS__CCM_WAIT			0x0048 0x02d4 0x0000 4 0
+#define MX6UL_PAD_JTAG_TMS__GPIO1_IO11			0x0048 0x02d4 0x0000 5 0
+#define MX6UL_PAD_JTAG_TMS__SDMA_EXT_EVENT01		0x0048 0x02d4 0x0614 6 0
+#define MX6UL_PAD_JTAG_TMS__EPIT1_OUT			0x0048 0x02d4 0x0000 8 0
+#define MX6UL_PAD_JTAG_TDO__SJC_TDO			0x004c 0x02d8 0x0000 0 0
+#define MX6UL_PAD_JTAG_TDO__GPT2_CAPTURE2		0x004c 0x02d8 0x059c 1 0
+#define MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC		0x004c 0x02d8 0x05fc 2 0
+#define MX6UL_PAD_JTAG_TDO__CCM_CLKO2			0x004c 0x02d8 0x0000 3 0
+#define MX6UL_PAD_JTAG_TDO__CCM_STOP			0x004c 0x02d8 0x0000 4 0
+#define MX6UL_PAD_JTAG_TDO__GPIO1_IO12			0x004c 0x02d8 0x0000 5 0
+#define MX6UL_PAD_JTAG_TDO__MQS_RIGHT			0x004c 0x02d8 0x0000 6 0
+#define MX6UL_PAD_JTAG_TDO__EPIT2_OUT			0x004c 0x02d8 0x0000 8 0
+#define MX6UL_PAD_JTAG_TDI__SJC_TDI			0x0050 0x02dc 0x0000 0 0
+#define MX6UL_PAD_JTAG_TDI__GPT2_COMPARE1		0x0050 0x02dc 0x0000 1 0
+#define MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK		0x0050 0x02dc 0x05f8 2 0
+#define MX6UL_PAD_JTAG_TDI__PWM6_OUT			0x0050 0x02dc 0x0000 4 0
+#define MX6UL_PAD_JTAG_TDI__GPIO1_IO13			0x0050 0x02dc 0x0000 5 0
+#define MX6UL_PAD_JTAG_TDI__MQS_LEFT			0x0050 0x02dc 0x0000 6 0
+#define MX6UL_PAD_JTAG_TDI__SIM1_POWER_FAIL		0x0050 0x02dc 0x0000 8 0
+#define MX6UL_PAD_JTAG_TCK__SJC_TCK			0x0054 0x02e0 0x0000 0 0
+#define MX6UL_PAD_JTAG_TCK__GPT2_COMPARE2		0x0054 0x02e0 0x0000 1 0
+#define MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA		0x0054 0x02e0 0x05f4 2 0
+#define MX6UL_PAD_JTAG_TCK__PWM7_OUT			0x0054 0x02e0 0x0000 4 0
+#define MX6UL_PAD_JTAG_TCK__GPIO1_IO14			0x0054 0x02e0 0x0000 5 0
+#define MX6UL_PAD_JTAG_TCK__OSC32K_32K_OUT			0x0054 0x02e0 0x0000 6 0
+#define MX6UL_PAD_JTAG_TCK__SIM2_POWER_FAIL		0x0054 0x02e0 0x0000 8 0
+#define MX6UL_PAD_JTAG_TRST_B__SJC_TRSTB		0x0058 0x02e4 0x0000 0 0
+#define MX6UL_PAD_JTAG_TRST_B__GPT2_COMPARE3		0x0058 0x02e4 0x0000 1 0
+#define MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA		0x0058 0x02e4 0x0000 2 0
+#define MX6UL_PAD_JTAG_TRST_B__PWM8_OUT			0x0058 0x02e4 0x0000 4 0
+#define MX6UL_PAD_JTAG_TRST_B__GPIO1_IO15		0x0058 0x02e4 0x0000 5 0
+#define MX6UL_PAD_JTAG_TRST_B__REF_CLK_24M		0x0058 0x02e4 0x0000 6 0
+#define MX6UL_PAD_JTAG_TRST_B__CAAM_RNG_OSC_OBS		0x0058 0x02e4 0x0000 8 0
+#define MX6UL_PAD_GPIO1_IO00__I2C2_SCL			0x005c 0x02e8 0x05ac 0 1
+#define MX6UL_PAD_GPIO1_IO00__GPT1_CAPTURE1		0x005c 0x02e8 0x058c 1 0
+#define MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID		0x005c 0x02e8 0x04b8 2 0
+#define MX6UL_PAD_GPIO1_IO00__ENET1_REF_CLK1		0x005c 0x02e8 0x0574 3 0
+#define MX6UL_PAD_GPIO1_IO00__MQS_RIGHT			0x005c 0x02e8 0x0000 4 0
+#define MX6UL_PAD_GPIO1_IO00__GPIO1_IO00		0x005c 0x02e8 0x0000 5 0
+#define MX6UL_PAD_GPIO1_IO00__ENET1_1588_EVENT0_IN	0x005c 0x02e8 0x0000 6 0
+#define MX6UL_PAD_GPIO1_IO00__SRC_SYSTEM_RESET		0x005c 0x02e8 0x0000 7 0
+#define MX6UL_PAD_GPIO1_IO00__WDOG3_WDOG_B		0x005c 0x02e8 0x0000 8 0
+#define MX6UL_PAD_GPIO1_IO01__I2C2_SDA			0x0060 0x02ec 0x05b0 0 1
+#define MX6UL_PAD_GPIO1_IO01__GPT1_COMPARE1		0x0060 0x02ec 0x0000 1 0
+#define MX6UL_PAD_GPIO1_IO01__USB_OTG1_OC		0x0060 0x02ec 0x0664 2 0
+#define MX6UL_PAD_GPIO1_IO01__ENET2_REF_CLK2		0x0060 0x02ec 0x057c 3 0
+#define MX6UL_PAD_GPIO1_IO01__MQS_LEFT			0x0060 0x02ec 0x0000 4 0
+#define MX6UL_PAD_GPIO1_IO01__GPIO1_IO01		0x0060 0x02ec 0x0000 5 0
+#define MX6UL_PAD_GPIO1_IO01__ENET1_1588_EVENT0_OUT	0x0060 0x02ec 0x0000 6 0
+#define MX6UL_PAD_GPIO1_IO01__SRC_EARLY_RESET		0x0060 0x02ec 0x0000 7 0
+#define MX6UL_PAD_GPIO1_IO01__WDOG1_WDOG_B		0x0060 0x02ec 0x0000 8 0
+#define MX6UL_PAD_GPIO1_IO02__I2C1_SCL			0x0064 0x02f0 0x05a4 0 0
+#define MX6UL_PAD_GPIO1_IO02__GPT1_COMPARE2		0x0064 0x02f0 0x0000 1 0
+#define MX6UL_PAD_GPIO1_IO02__USB_OTG2_PWR		0x0064 0x02f0 0x0000 2 0
+#define MX6UL_PAD_GPIO1_IO02__ENET1_REF_CLK_25M		0x0064 0x02f0 0x0000 3 0
+#define MX6UL_PAD_GPIO1_IO02__USDHC1_WP			0x0064 0x02f0 0x066c 4 0
+#define MX6UL_PAD_GPIO1_IO02__GPIO1_IO02		0x0064 0x02f0 0x0000 5 0
+#define MX6UL_PAD_GPIO1_IO02__SDMA_EXT_EVENT00		0x0064 0x02f0 0x0610 6 1
+#define MX6UL_PAD_GPIO1_IO02__SRC_ANY_PU_RESET		0x0064 0x02f0 0x0000 7 0
+#define MX6UL_PAD_GPIO1_IO02__UART1_DCE_TX		0x0064 0x02f0 0x0000 8 0
+#define MX6UL_PAD_GPIO1_IO02__UART1_DTE_RX		0x0064 0x02f0 0x0624 8 0
+#define MX6UL_PAD_GPIO1_IO03__I2C1_SDA			0x0068 0x02f4 0x05a8 0 1
+#define MX6UL_PAD_GPIO1_IO03__GPT1_COMPARE3		0x0068 0x02f4 0x0000 1 0
+#define MX6UL_PAD_GPIO1_IO03__USB_OTG2_OC		0x0068 0x02f4 0x0660 2 0
+#define MX6UL_PAD_GPIO1_IO03__OSC32K_32K_OUT		0x0068 0x02f4 0x0000 3 0
+#define MX6UL_PAD_GPIO1_IO03__USDHC1_CD_B		0x0068 0x02f4 0x0668 4 0
+#define MX6UL_PAD_GPIO1_IO03__GPIO1_IO03		0x0068 0x02f4 0x0000 5 0
+#define MX6UL_PAD_GPIO1_IO03__CCM_DI0_EXT_CLK		0x0068 0x02f4 0x0000 6 0
+#define MX6UL_PAD_GPIO1_IO03__SRC_TESTER_ACK		0x0068 0x02f4 0x0000 7 0
+#define MX6UL_PAD_GPIO1_IO03__UART1_DCE_RX		0x0068 0x02f4 0x0624 8 1
+#define MX6UL_PAD_GPIO1_IO03__UART1_DTE_TX		0x0068 0x02f4 0x0000 8 0
+#define MX6UL_PAD_GPIO1_IO04__ENET1_REF_CLK1		0x006c 0x02f8 0x0574 0 1
+#define MX6UL_PAD_GPIO1_IO04__PWM3_OUT			0x006c 0x02f8 0x0000 1 0
+#define MX6UL_PAD_GPIO1_IO04__USB_OTG1_PWR		0x006c 0x02f8 0x0000 2 0
+#define MX6UL_PAD_GPIO1_IO04__REF_CLK_24M		0x006c 0x02f8 0x0000 3 0
+#define MX6UL_PAD_GPIO1_IO04__USDHC1_RESET_B		0x006c 0x02f8 0x0000 4 0
+#define MX6UL_PAD_GPIO1_IO04__GPIO1_IO04		0x006c 0x02f8 0x0000 5 0
+#define MX6UL_PAD_GPIO1_IO04__ENET2_1588_EVENT0_IN	0x006c 0x02f8 0x0000 6 0
+#define MX6UL_PAD_GPIO1_IO04__UART5_DCE_TX		0x006c 0x02f8 0x0000 8 0
+#define MX6UL_PAD_GPIO1_IO04__UART5_DTE_RX		0x006c 0x02f8 0x0644 8 2
+#define MX6UL_PAD_GPIO1_IO05__ENET2_REF_CLK2		0x0070 0x02fc 0x057c 0 1
+#define MX6UL_PAD_GPIO1_IO05__PWM4_OUT			0x0070 0x02fc 0x0000 1 0
+#define MX6UL_PAD_GPIO1_IO05__ANATOP_OTG2_ID		0x0070 0x02fc 0x04bc 2 0
+#define MX6UL_PAD_GPIO1_IO05__CSI_FIELD			0x0070 0x02fc 0x0530 3 0
+#define MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT		0x0070 0x02fc 0x0000 4 0
+#define MX6UL_PAD_GPIO1_IO05__GPIO1_IO05		0x0070 0x02fc 0x0000 5 0
+#define MX6UL_PAD_GPIO1_IO05__ENET2_1588_EVENT0_OUT	0x0070 0x02fc 0x0000 6 0
+#define MX6UL_PAD_GPIO1_IO05__UART5_DCE_RX		0x0070 0x02fc 0x0644 8 3
+#define MX6UL_PAD_GPIO1_IO05__UART5_DTE_TX		0x0070 0x02fc 0x0000 8 0
+#define MX6UL_PAD_GPIO1_IO06__ENET1_MDIO		0x0074 0x0300 0x0578 0 0
+#define MX6UL_PAD_GPIO1_IO06__ENET2_MDIO		0x0074 0x0300 0x0580 1 0
+#define MX6UL_PAD_GPIO1_IO06__USB_OTG_PWR_WAKE		0x0074 0x0300 0x0000 2 0
+#define MX6UL_PAD_GPIO1_IO06__CSI_MCLK			0x0074 0x0300 0x0000 3 0
+#define MX6UL_PAD_GPIO1_IO06__USDHC2_WP			0x0074 0x0300 0x069c 4 0
+#define MX6UL_PAD_GPIO1_IO06__GPIO1_IO06		0x0074 0x0300 0x0000 5 0
+#define MX6UL_PAD_GPIO1_IO06__CCM_WAIT			0x0074 0x0300 0x0000 6 0
+#define MX6UL_PAD_GPIO1_IO06__CCM_REF_EN_B		0x0074 0x0300 0x0000 7 0
+#define MX6UL_PAD_GPIO1_IO06__UART1_DCE_CTS		0x0074 0x0300 0x0000 8 0
+#define MX6UL_PAD_GPIO1_IO06__UART1_DTE_RTS		0x0074 0x0300 0x0620 8 0
+#define MX6UL_PAD_GPIO1_IO07__ENET1_MDC			0x0078 0x0304 0x0000 0 0
+#define MX6UL_PAD_GPIO1_IO07__ENET2_MDC			0x0078 0x0304 0x0000 1 0
+#define MX6UL_PAD_GPIO1_IO07__USB_OTG_HOST_MODE		0x0078 0x0304 0x0000 2 0
+#define MX6UL_PAD_GPIO1_IO07__CSI_PIXCLK		0x0078 0x0304 0x0528 3 0
+#define MX6UL_PAD_GPIO1_IO07__USDHC2_CD_B		0x0078 0x0304 0x0674 4 1
+#define MX6UL_PAD_GPIO1_IO07__GPIO1_IO07		0x0078 0x0304 0x0000 5 0
+#define MX6UL_PAD_GPIO1_IO07__CCM_STOP			0x0078 0x0304 0x0000 6 0
+#define MX6UL_PAD_GPIO1_IO07__UART1_DCE_RTS		0x0078 0x0304 0x0620 8 1
+#define MX6UL_PAD_GPIO1_IO07__UART1_DTE_CTS		0x0078 0x0304 0x0000 8 0
+#define MX6UL_PAD_GPIO1_IO08__PWM1_OUT			0x007c 0x0308 0x0000 0 0
+#define MX6UL_PAD_GPIO1_IO08__WDOG1_WDOG_B		0x007c 0x0308 0x0000 1 0
+#define MX6UL_PAD_GPIO1_IO08__SPDIF_OUT			0x007c 0x0308 0x0000 2 0
+#define MX6UL_PAD_GPIO1_IO08__CSI_VSYNC			0x007c 0x0308 0x052c 3 1
+#define MX6UL_PAD_GPIO1_IO08__USDHC2_VSELECT		0x007c 0x0308 0x0000 4 0
+#define MX6UL_PAD_GPIO1_IO08__GPIO1_IO08		0x007c 0x0308 0x0000 5 0
+#define MX6UL_PAD_GPIO1_IO08__CCM_PMIC_RDY		0x007c 0x0308 0x04c0 6 1
+#define MX6UL_PAD_GPIO1_IO08__UART5_DCE_RTS		0x007c 0x0308 0x0640 8 1
+#define MX6UL_PAD_GPIO1_IO08__UART5_DTE_CTS		0x007c 0x0308 0x0000 8 0
+#define MX6UL_PAD_GPIO1_IO09__PWM2_OUT			0x0080 0x030c 0x0000 0 0
+#define MX6UL_PAD_GPIO1_IO09__WDOG1_WDOG_ANY		0x0080 0x030c 0x0000 1 0
+#define MX6UL_PAD_GPIO1_IO09__SPDIF_IN			0x0080 0x030c 0x0618 2 0
+#define MX6UL_PAD_GPIO1_IO09__CSI_HSYNC			0x0080 0x030c 0x0524 3 1
+#define MX6UL_PAD_GPIO1_IO09__USDHC2_RESET_B		0x0080 0x030c 0x0000 4 0
+#define MX6UL_PAD_GPIO1_IO09__GPIO1_IO09		0x0080 0x030c 0x0000 5 0
+#define MX6UL_PAD_GPIO1_IO09__USDHC1_RESET_B		0x0080 0x030c 0x0000 6 0
+#define MX6UL_PAD_GPIO1_IO09__UART5_DCE_CTS		0x0080 0x030c 0x0000 8 0
+#define MX6UL_PAD_GPIO1_IO09__UART5_DTE_RTS		0x0080 0x030c 0x0640 8 2
+#define MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX		0x0084 0x0310 0x0000 0 0
+#define MX6UL_PAD_UART1_TX_DATA__UART1_DTE_RX		0x0084 0x0310 0x0624 0 2
+#define MX6UL_PAD_UART1_TX_DATA__ENET1_RDATA02		0x0084 0x0310 0x0000 1 0
+#define MX6UL_PAD_UART1_TX_DATA__I2C3_SCL		0x0084 0x0310 0x05b4 2 0
+#define MX6UL_PAD_UART1_TX_DATA__CSI_DATA02		0x0084 0x0310 0x04c4 3 1
+#define MX6UL_PAD_UART1_TX_DATA__GPT1_COMPARE1		0x0084 0x0310 0x0000 4 0
+#define MX6UL_PAD_UART1_TX_DATA__GPIO1_IO16		0x0084 0x0310 0x0000 5 0
+#define MX6UL_PAD_UART1_TX_DATA__SPDIF_OUT		0x0084 0x0310 0x0000 8 0
+#define MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX		0x0088 0x0314 0x0624 0 3
+#define MX6UL_PAD_UART1_RX_DATA__UART1_DTE_TX		0x0088 0x0314 0x0000 0 0
+#define MX6UL_PAD_UART1_RX_DATA__ENET1_RDATA03		0x0088 0x0314 0x0000 1 0
+#define MX6UL_PAD_UART1_RX_DATA__I2C3_SDA		0x0088 0x0314 0x05b8 2 0
+#define MX6UL_PAD_UART1_RX_DATA__CSI_DATA03		0x0088 0x0314 0x04c8 3 1
+#define MX6UL_PAD_UART1_RX_DATA__GPT1_CLK		0x0088 0x0314 0x0594 4 0
+#define MX6UL_PAD_UART1_RX_DATA__GPIO1_IO17		0x0088 0x0314 0x0000 5 0
+#define MX6UL_PAD_UART1_RX_DATA__SPDIF_IN		0x0088 0x0314 0x0618 8 1
+#define MX6UL_PAD_UART1_CTS_B__UART1_DCE_CTS		0x008c 0x0318 0x0000 0 0
+#define MX6UL_PAD_UART1_CTS_B__UART1_DTE_RTS		0x008c 0x0318 0x0620 0 2
+#define MX6UL_PAD_UART1_CTS_B__ENET1_RX_CLK		0x008c 0x0318 0x0000 1 0
+#define MX6UL_PAD_UART1_CTS_B__USDHC1_WP		0x008c 0x0318 0x066c 2 1
+#define MX6UL_PAD_UART1_CTS_B__CSI_DATA04		0x008c 0x0318 0x04d8 3 0
+#define MX6UL_PAD_UART1_CTS_B__ENET2_1588_EVENT1_IN	0x008c 0x0318 0x0000 4 0
+#define MX6UL_PAD_UART1_CTS_B__GPIO1_IO18		0x008c 0x0318 0x0000 5 0
+#define MX6UL_PAD_UART1_CTS_B__USDHC2_WP		0x008c 0x0318 0x069c 8 1
+#define MX6UL_PAD_UART1_RTS_B__UART1_DCE_RTS		0x0090 0x031c 0x0620 0 3
+#define MX6UL_PAD_UART1_RTS_B__UART1_DTE_CTS		0x0090 0x031c 0x0000 0 0
+#define MX6UL_PAD_UART1_RTS_B__ENET1_TX_ER		0x0090 0x031c 0x0000 1 0
+#define MX6UL_PAD_UART1_RTS_B__USDHC1_CD_B		0x0090 0x031c 0x0668 2 1
+#define MX6UL_PAD_UART1_RTS_B__CSI_DATA05		0x0090 0x031c 0x04cc 3 1
+#define MX6UL_PAD_UART1_RTS_B__ENET2_1588_EVENT1_OUT	0x0090 0x031c 0x0000 4 0
+#define MX6UL_PAD_UART1_RTS_B__GPIO1_IO19		0x0090 0x031c 0x0000 5 0
+#define MX6UL_PAD_UART1_RTS_B__USDHC2_CD_B		0x0090 0x031c 0x0674 8 2
+#define MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX		0x0094 0x0320 0x0000 0 0
+#define MX6UL_PAD_UART2_TX_DATA__UART2_DTE_RX		0x0094 0x0320 0x062c 0 0
+#define MX6UL_PAD_UART2_TX_DATA__ENET1_TDATA02		0x0094 0x0320 0x0000 1 0
+#define MX6UL_PAD_UART2_TX_DATA__I2C4_SCL		0x0094 0x0320 0x05bc 2 0
+#define MX6UL_PAD_UART2_TX_DATA__CSI_DATA06		0x0094 0x0320 0x04dc 3 0
+#define MX6UL_PAD_UART2_TX_DATA__GPT1_CAPTURE1		0x0094 0x0320 0x058c 4 1
+#define MX6UL_PAD_UART2_TX_DATA__GPIO1_IO20		0x0094 0x0320 0x0000 5 0
+#define MX6UL_PAD_UART2_TX_DATA__ECSPI3_SS0		0x0094 0x0320 0x0560 8 0
+#define MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX		0x0098 0x0324 0x062c 0 1
+#define MX6UL_PAD_UART2_RX_DATA__UART2_DTE_TX		0x0098 0x0324 0x0000 0 0
+#define MX6UL_PAD_UART2_RX_DATA__ENET1_TDATA03		0x0098 0x0324 0x0000 1 0
+#define MX6UL_PAD_UART2_RX_DATA__I2C4_SDA		0x0098 0x0324 0x05c0 2 0
+#define MX6UL_PAD_UART2_RX_DATA__CSI_DATA07		0x0098 0x0324 0x04e0 3 0
+#define MX6UL_PAD_UART2_RX_DATA__GPT1_CAPTURE2		0x0098 0x0324 0x0590 4 0
+#define MX6UL_PAD_UART2_RX_DATA__GPIO1_IO21		0x0098 0x0324 0x0000 5 0
+#define MX6UL_PAD_UART2_RX_DATA__SJC_DONE		0x0098 0x0324 0x0000 7 0
+#define MX6UL_PAD_UART2_RX_DATA__ECSPI3_SCLK		0x0098 0x0324 0x0554 8 0
+#define MX6UL_PAD_UART2_CTS_B__UART2_DCE_CTS		0x009c 0x0328 0x0000 0 0
+#define MX6UL_PAD_UART2_CTS_B__UART2_DTE_RTS		0x009c 0x0328 0x0628 0 0
+#define MX6UL_PAD_UART2_CTS_B__ENET1_CRS		0x009c 0x0328 0x0000 1 0
+#define MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX		0x009c 0x0328 0x0000 2 0
+#define MX6UL_PAD_UART2_CTS_B__CSI_DATA08		0x009c 0x0328 0x04e4 3 0
+#define MX6UL_PAD_UART2_CTS_B__GPT1_COMPARE2		0x009c 0x0328 0x0000 4 0
+#define MX6UL_PAD_UART2_CTS_B__GPIO1_IO22		0x009c 0x0328 0x0000 5 0
+#define MX6UL_PAD_UART2_CTS_B__SJC_DE_B			0x009c 0x0328 0x0000 7 0
+#define MX6UL_PAD_UART2_CTS_B__ECSPI3_MOSI		0x009c 0x0328 0x055c 8 0
+#define MX6UL_PAD_UART2_RTS_B__UART2_DCE_RTS		0x00a0 0x032c 0x0628 0 1
+#define MX6UL_PAD_UART2_RTS_B__UART2_DTE_CTS		0x00a0 0x032c 0x0000 0 0
+#define MX6UL_PAD_UART2_RTS_B__ENET1_COL		0x00a0 0x032c 0x0000 1 0
+#define MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX		0x00a0 0x032c 0x0588 2 0
+#define MX6UL_PAD_UART2_RTS_B__CSI_DATA09		0x00a0 0x032c 0x04e8 3 0
+#define MX6UL_PAD_UART2_RTS_B__GPT1_COMPARE3		0x00a0 0x032c 0x0000 4 0
+#define MX6UL_PAD_UART2_RTS_B__GPIO1_IO23		0x00a0 0x032c 0x0000 5 0
+#define MX6UL_PAD_UART2_RTS_B__SJC_FAIL			0x00a0 0x032c 0x0000 7 0
+#define MX6UL_PAD_UART2_RTS_B__ECSPI3_MISO		0x00a0 0x032c 0x0558 8 0
+#define MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX		0x00a4 0x0330 0x0000 0 0
+#define MX6UL_PAD_UART3_TX_DATA__UART3_DTE_RX		0x00a4 0x0330 0x0634 0 0
+#define MX6UL_PAD_UART3_TX_DATA__ENET2_RDATA02		0x00a4 0x0330 0x0000 1 0
+#define MX6UL_PAD_UART3_TX_DATA__SIM1_PORT0_PD		0x00a4 0x0330 0x0000 2 0
+#define MX6UL_PAD_UART3_TX_DATA__CSI_DATA01		0x00a4 0x0330 0x04d4 3 0
+#define MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS		0x00a4 0x0330 0x0000 4 0
+#define MX6UL_PAD_UART3_TX_DATA__UART2_DTE_RTS		0x00a4 0x0330 0x0628 4 2
+#define MX6UL_PAD_UART3_TX_DATA__GPIO1_IO24		0x00a4 0x0330 0x0000 5 0
+#define MX6UL_PAD_UART3_TX_DATA__SJC_JTAG_ACT		0x00a4 0x0330 0x0000 7 0
+#define MX6UL_PAD_UART3_TX_DATA__ANATOP_OTG1_ID		0x00a4 0x0330 0x04b8 8 1
+#define MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX		0x00a8 0x0334 0x0634 0 1
+#define MX6UL_PAD_UART3_RX_DATA__UART3_DTE_TX		0x00a8 0x0334 0x0000 0 0
+#define MX6UL_PAD_UART3_RX_DATA__ENET2_RDATA03		0x00a8 0x0334 0x0000 1 0
+#define MX6UL_PAD_UART3_RX_DATA__SIM2_PORT0_PD		0x00a8 0x0334 0x0000 2 0
+#define MX6UL_PAD_UART3_RX_DATA__CSI_DATA00		0x00a8 0x0334 0x04d0 3 0
+#define MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS		0x00a8 0x0334 0x0628 4 3
+#define MX6UL_PAD_UART3_RX_DATA__UART2_DTE_CTS		0x00a8 0x0334 0x0000 4 0
+#define MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25		0x00a8 0x0334 0x0000 5 0
+#define MX6UL_PAD_UART3_RX_DATA__EPIT1_OUT		0x00a8 0x0334 0x0000 8 0
+#define MX6UL_PAD_UART3_CTS_B__UART3_DCE_CTS		0x00ac 0x0338 0x0000 0 0
+#define MX6UL_PAD_UART3_CTS_B__UART3_DTE_RTS		0x00ac 0x0338 0x0630 0 0
+#define MX6UL_PAD_UART3_CTS_B__ENET2_RX_CLK		0x00ac 0x0338 0x0000 1 0
+#define MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX		0x00ac 0x0338 0x0000 2 0
+#define MX6UL_PAD_UART3_CTS_B__CSI_DATA10		0x00ac 0x0338 0x04ec 3 0
+#define MX6UL_PAD_UART3_CTS_B__ENET1_1588_EVENT1_IN	0x00ac 0x0338 0x0000 4 0
+#define MX6UL_PAD_UART3_CTS_B__GPIO1_IO26		0x00ac 0x0338 0x0000 5 0
+#define MX6UL_PAD_UART3_CTS_B__EPIT2_OUT		0x00ac 0x0338 0x0000 8 0
+#define MX6UL_PAD_UART3_RTS_B__UART3_DCE_RTS		0x00b0 0x033c 0x0630 0 1
+#define MX6UL_PAD_UART3_RTS_B__UART3_DTE_CTS		0x00b0 0x033c 0x0000 0 0
+#define MX6UL_PAD_UART3_RTS_B__ENET2_TX_ER		0x00b0 0x033c 0x0000 1 0
+#define MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX		0x00b0 0x033c 0x0584 2 0
+#define MX6UL_PAD_UART3_RTS_B__CSI_DATA11		0x00b0 0x033c 0x04f0 3 0
+#define MX6UL_PAD_UART3_RTS_B__ENET1_1588_EVENT1_OUT	0x00b0 0x033c 0x0000 4 0
+#define MX6UL_PAD_UART3_RTS_B__GPIO1_IO27		0x00b0 0x033c 0x0000 5 0
+#define MX6UL_PAD_UART3_RTS_B__WDOG1_WDOG_B		0x00b0 0x033c 0x0000 8 0
+#define MX6UL_PAD_UART4_TX_DATA__UART4_DCE_TX		0x00b4 0x0340 0x0000 0 0
+#define MX6UL_PAD_UART4_TX_DATA__UART4_DTE_RX		0x00b4 0x0340 0x063c 0 0
+#define MX6UL_PAD_UART4_TX_DATA__ENET2_TDATA02		0x00b4 0x0340 0x0000 1 0
+#define MX6UL_PAD_UART4_TX_DATA__I2C1_SCL		0x00b4 0x0340 0x05a4 2 1
+#define MX6UL_PAD_UART4_TX_DATA__CSI_DATA12		0x00b4 0x0340 0x04f4 3 0
+#define MX6UL_PAD_UART4_TX_DATA__CSU_CSU_ALARM_AUT02	0x00b4 0x0340 0x0000 4 0
+#define MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28		0x00b4 0x0340 0x0000 5 0
+#define MX6UL_PAD_UART4_TX_DATA__ECSPI2_SCLK		0x00b4 0x0340 0x0544 8 1
+#define MX6UL_PAD_UART4_RX_DATA__UART4_DCE_RX		0x00b8 0x0344 0x063c 0 1
+#define MX6UL_PAD_UART4_RX_DATA__UART4_DTE_TX		0x00b8 0x0344 0x0000 0 0
+#define MX6UL_PAD_UART4_RX_DATA__ENET2_TDATA03		0x00b8 0x0344 0x0000 1 0
+#define MX6UL_PAD_UART4_RX_DATA__I2C1_SDA		0x00b8 0x0344 0x05a8 2 2
+#define MX6UL_PAD_UART4_RX_DATA__CSI_DATA13		0x00b8 0x0344 0x04f8 3 0
+#define MX6UL_PAD_UART4_RX_DATA__CSU_CSU_ALARM_AUT01	0x00b8 0x0344 0x0000 4 0
+#define MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29		0x00b8 0x0344 0x0000 5 0
+#define MX6UL_PAD_UART4_RX_DATA__ECSPI2_SS0		0x00b8 0x0344 0x0550 8 1
+#define MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30		0x00bc 0x0348 0x0000 5 0
+#define MX6UL_PAD_UART5_TX_DATA__ECSPI2_MOSI		0x00bc 0x0348 0x054c 8 0
+#define MX6UL_PAD_UART5_TX_DATA__UART5_DCE_TX		0x00bc 0x0348 0x0000 0 0
+#define MX6UL_PAD_UART5_TX_DATA__UART5_DTE_RX		0x00bc 0x0348 0x0644 0 4
+#define MX6UL_PAD_UART5_TX_DATA__ENET2_CRS		0x00bc 0x0348 0x0000 1 0
+#define MX6UL_PAD_UART5_TX_DATA__I2C2_SCL		0x00bc 0x0348 0x05ac 2 2
+#define MX6UL_PAD_UART5_TX_DATA__CSI_DATA14		0x00bc 0x0348 0x04fc 3 0
+#define MX6UL_PAD_UART5_TX_DATA__CSU_CSU_ALARM_AUT00	0x00bc 0x0348 0x0000 4 0
+#define MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX		0x00c0 0x034c 0x0644 0 5
+#define MX6UL_PAD_UART5_RX_DATA__UART5_DTE_TX		0x00c0 0x034c 0x0000 0 0
+#define MX6UL_PAD_UART5_RX_DATA__ENET2_COL		0x00c0 0x034c 0x0000 1 0
+#define MX6UL_PAD_UART5_RX_DATA__I2C2_SDA		0x00c0 0x034c 0x05b0 2 2
+#define MX6UL_PAD_UART5_RX_DATA__CSI_DATA15		0x00c0 0x034c 0x0500 3 0
+#define MX6UL_PAD_UART5_RX_DATA__CSU_CSU_INT_DEB	0x00c0 0x034c 0x0000 4 0
+#define MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31		0x00c0 0x034c 0x0000 5 0
+#define MX6UL_PAD_UART5_RX_DATA__ECSPI2_MISO		0x00c0 0x034c 0x0548 8 1
+#define MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00		0x00c4 0x0350 0x0000 0 0
+#define MX6UL_PAD_ENET1_RX_DATA0__UART4_DCE_RTS		0x00c4 0x0350 0x0638 1 0
+#define MX6UL_PAD_ENET1_RX_DATA0__UART4_DTE_CTS		0x00c4 0x0350 0x0000 1 0
+#define MX6UL_PAD_ENET1_RX_DATA0__PWM1_OUT		0x00c4 0x0350 0x0000 2 0
+#define MX6UL_PAD_ENET1_RX_DATA0__CSI_DATA16		0x00c4 0x0350 0x0504 3 0
+#define MX6UL_PAD_ENET1_RX_DATA0__FLEXCAN1_TX		0x00c4 0x0350 0x0000 4 0
+#define MX6UL_PAD_ENET1_RX_DATA0__GPIO2_IO00		0x00c4 0x0350 0x0000 5 0
+#define MX6UL_PAD_ENET1_RX_DATA0__KPP_ROW00		0x00c4 0x0350 0x05d0 6 0
+#define MX6UL_PAD_ENET1_RX_DATA0__USDHC1_LCTL		0x00c4 0x0350 0x0000 8 0
+#define MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01		0x00c8 0x0354 0x0000 0 0
+#define MX6UL_PAD_ENET1_RX_DATA1__UART4_DCE_CTS		0x00c8 0x0354 0x0000 1 0
+#define MX6UL_PAD_ENET1_RX_DATA1__UART4_DTE_RTS		0x00c8 0x0354 0x0638 1 1
+#define MX6UL_PAD_ENET1_RX_DATA1__PWM2_OUT		0x00c8 0x0354 0x0000 2 0
+#define MX6UL_PAD_ENET1_RX_DATA1__CSI_DATA17		0x00c8 0x0354 0x0508 3 0
+#define MX6UL_PAD_ENET1_RX_DATA1__FLEXCAN1_RX		0x00c8 0x0354 0x0584 4 1
+#define MX6UL_PAD_ENET1_RX_DATA1__GPIO2_IO01		0x00c8 0x0354 0x0000 5 0
+#define MX6UL_PAD_ENET1_RX_DATA1__KPP_COL00		0x00c8 0x0354 0x05c4 6 0
+#define MX6UL_PAD_ENET1_RX_DATA1__USDHC2_LCTL		0x00c8 0x0354 0x0000 8 0
+#define MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN		0x00cc 0x0358 0x0000 0 0
+#define MX6UL_PAD_ENET1_RX_EN__UART5_DCE_RTS		0x00cc 0x0358 0x0640 1 3
+#define MX6UL_PAD_ENET1_RX_EN__UART5_DTE_CTS		0x00cc 0x0358 0x0000 1 0
+#define MX6UL_PAD_ENET1_RX_EN__OSC32K_32K_OUT		0x00cc 0x0358 0x0000 2 0
+#define MX6UL_PAD_ENET1_RX_EN__CSI_DATA18		0x00cc 0x0358 0x050c 3 0
+#define MX6UL_PAD_ENET1_RX_EN__FLEXCAN2_TX		0x00cc 0x0358 0x0000 4 0
+#define MX6UL_PAD_ENET1_RX_EN__GPIO2_IO02		0x00cc 0x0358 0x0000 5 0
+#define MX6UL_PAD_ENET1_RX_EN__KPP_ROW01		0x00cc 0x0358 0x05d4 6 0
+#define MX6UL_PAD_ENET1_RX_EN__USDHC1_VSELECT		0x00cc 0x0358 0x0000 8 0
+#define MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00		0x00d0 0x035c 0x0000 0 0
+#define MX6UL_PAD_ENET1_TX_DATA0__UART5_DCE_CTS		0x00d0 0x035c 0x0000 1 0
+#define MX6UL_PAD_ENET1_TX_DATA0__UART5_DTE_RTS		0x00d0 0x035c 0x0640 1 4
+#define MX6UL_PAD_ENET1_TX_DATA0__REF_CLK_24M		0x00d0 0x035c 0x0000 2 0
+#define MX6UL_PAD_ENET1_TX_DATA0__CSI_DATA19		0x00d0 0x035c 0x0510 3 0
+#define MX6UL_PAD_ENET1_TX_DATA0__FLEXCAN2_RX		0x00d0 0x035c 0x0588 4 1
+#define MX6UL_PAD_ENET1_TX_DATA0__GPIO2_IO03		0x00d0 0x035c 0x0000 5 0
+#define MX6UL_PAD_ENET1_TX_DATA0__KPP_COL01		0x00d0 0x035c 0x05c8 6 0
+#define MX6UL_PAD_ENET1_TX_DATA0__USDHC2_VSELECT	0x00d0 0x035c 0x0000 8 0
+#define MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01		0x00d4 0x0360 0x0000 0 0
+#define MX6UL_PAD_ENET1_TX_DATA1__UART6_DCE_CTS		0x00d4 0x0360 0x0000 1 0
+#define MX6UL_PAD_ENET1_TX_DATA1__UART6_DTE_RTS		0x00d4 0x0360 0x0648 1 2
+#define MX6UL_PAD_ENET1_TX_DATA1__PWM5_OUT		0x00d4 0x0360 0x0000 2 0
+#define MX6UL_PAD_ENET1_TX_DATA1__CSI_DATA20		0x00d4 0x0360 0x0514 3 0
+#define MX6UL_PAD_ENET1_TX_DATA1__ENET2_MDIO		0x00d4 0x0360 0x0580 4 1
+#define MX6UL_PAD_ENET1_TX_DATA1__GPIO2_IO04		0x00d4 0x0360 0x0000 5 0
+#define MX6UL_PAD_ENET1_TX_DATA1__KPP_ROW02		0x00d4 0x0360 0x05d8 6 0
+#define MX6UL_PAD_ENET1_TX_DATA1__WDOG1_WDOG_RST_B_DEB	0x00d4 0x0360 0x0000 8 0
+#define MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN		0x00d8 0x0364 0x0000 0 0
+#define MX6UL_PAD_ENET1_TX_EN__UART6_DCE_RTS		0x00d8 0x0364 0x0648 1 3
+#define MX6UL_PAD_ENET1_TX_EN__UART6_DTE_CTS		0x00d8 0x0364 0x0000 1 0
+#define MX6UL_PAD_ENET1_TX_EN__PWM6_OUT			0x00d8 0x0364 0x0000 2 0
+#define MX6UL_PAD_ENET1_TX_EN__CSI_DATA21		0x00d8 0x0364 0x0518 3 0
+#define MX6UL_PAD_ENET1_TX_EN__ENET2_MDC		0x00d8 0x0364 0x0000 4 0
+#define MX6UL_PAD_ENET1_TX_EN__GPIO2_IO05		0x00d8 0x0364 0x0000 5 0
+#define MX6UL_PAD_ENET1_TX_EN__KPP_COL02		0x00d8 0x0364 0x05cc 6 0
+#define MX6UL_PAD_ENET1_TX_EN__WDOG2_WDOG_RST_B_DEB	0x00d8 0x0364 0x0000 8 0
+#define MX6UL_PAD_ENET1_TX_CLK__ENET1_TX_CLK		0x00dc 0x0368 0x0000 0 0
+#define MX6UL_PAD_ENET1_TX_CLK__UART7_DCE_CTS		0x00dc 0x0368 0x0000 1 0
+#define MX6UL_PAD_ENET1_TX_CLK__UART7_DTE_RTS		0x00dc 0x0368 0x0650 1 0
+#define MX6UL_PAD_ENET1_TX_CLK__PWM7_OUT		0x00dc 0x0368 0x0000 2 0
+#define MX6UL_PAD_ENET1_TX_CLK__CSI_DATA22		0x00dc 0x0368 0x051c 3 0
+#define MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1		0x00dc 0x0368 0x0574 4 2
+#define MX6UL_PAD_ENET1_TX_CLK__GPIO2_IO06		0x00dc 0x0368 0x0000 5 0
+#define MX6UL_PAD_ENET1_TX_CLK__KPP_ROW03		0x00dc 0x0368 0x0000 6 0
+#define MX6UL_PAD_ENET1_TX_CLK__GPT1_CLK		0x00dc 0x0368 0x0594 8 1
+#define MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER		0x00e0 0x036c 0x0000 0 0
+#define MX6UL_PAD_ENET1_RX_ER__UART7_DCE_RTS		0x00e0 0x036c 0x0650 1 1
+#define MX6UL_PAD_ENET1_RX_ER__UART7_DTE_CTS		0x00e0 0x036c 0x0000 1 0
+#define MX6UL_PAD_ENET1_RX_ER__PWM8_OUT			0x00e0 0x036c 0x0000 2 0
+#define MX6UL_PAD_ENET1_RX_ER__CSI_DATA23		0x00e0 0x036c 0x0520 3 0
+#define MX6UL_PAD_ENET1_RX_ER__EIM_CRE			0x00e0 0x036c 0x0000 4 0
+#define MX6UL_PAD_ENET1_RX_ER__GPIO2_IO07		0x00e0 0x036c 0x0000 5 0
+#define MX6UL_PAD_ENET1_RX_ER__KPP_COL03		0x00e0 0x036c 0x0000 6 0
+#define MX6UL_PAD_ENET1_RX_ER__GPT1_CAPTURE2		0x00e0 0x036c 0x0590 8 1
+#define MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00		0x00e4 0x0370 0x0000 0 0
+#define MX6UL_PAD_ENET2_RX_DATA0__UART6_DCE_TX		0x00e4 0x0370 0x0000 1 0
+#define MX6UL_PAD_ENET2_RX_DATA0__UART6_DTE_RX		0x00e4 0x0370 0x064c 1 1
+#define MX6UL_PAD_ENET2_RX_DATA0__SIM1_PORT0_TRXD	0x00e4 0x0370 0x0000 2 0
+#define MX6UL_PAD_ENET2_RX_DATA0__I2C3_SCL		0x00e4 0x0370 0x05b4 3 1
+#define MX6UL_PAD_ENET2_RX_DATA0__ENET1_MDIO		0x00e4 0x0370 0x0578 4 1
+#define MX6UL_PAD_ENET2_RX_DATA0__GPIO2_IO08		0x00e4 0x0370 0x0000 5 0
+#define MX6UL_PAD_ENET2_RX_DATA0__KPP_ROW04		0x00e4 0x0370 0x0000 6 0
+#define MX6UL_PAD_ENET2_RX_DATA0__USB_OTG1_PWR		0x00e4 0x0370 0x0000 8 0
+#define MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01		0x00e8 0x0374 0x0000 0 0
+#define MX6UL_PAD_ENET2_RX_DATA1__UART6_DCE_RX		0x00e8 0x0374 0x064c 1 2
+#define MX6UL_PAD_ENET2_RX_DATA1__UART6_DTE_TX		0x00e8 0x0374 0x0000 1 0
+#define MX6UL_PAD_ENET2_RX_DATA1__SIM1_PORT0_CLK	0x00e8 0x0374 0x0000 2 0
+#define MX6UL_PAD_ENET2_RX_DATA1__I2C3_SDA		0x00e8 0x0374 0x05b8 3 1
+#define MX6UL_PAD_ENET2_RX_DATA1__ENET1_MDC		0x00e8 0x0374 0x0000 4 0
+#define MX6UL_PAD_ENET2_RX_DATA1__GPIO2_IO09		0x00e8 0x0374 0x0000 5 0
+#define MX6UL_PAD_ENET2_RX_DATA1__KPP_COL04		0x00e8 0x0374 0x0000 6 0
+#define MX6UL_PAD_ENET2_RX_DATA1__USB_OTG1_OC		0x00e8 0x0374 0x0664 8 1
+#define MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN		0x00ec 0x0378 0x0000 0 0
+#define MX6UL_PAD_ENET2_RX_EN__UART7_DCE_TX		0x00ec 0x0378 0x0000 1 0
+#define MX6UL_PAD_ENET2_RX_EN__UART7_DTE_RX		0x00ec 0x0378 0x0654 1 0
+#define MX6UL_PAD_ENET2_RX_EN__SIM1_PORT0_RST_B		0x00ec 0x0378 0x0000 2 0
+#define MX6UL_PAD_ENET2_RX_EN__I2C4_SCL			0x00ec 0x0378 0x05bc 3 1
+#define MX6UL_PAD_ENET2_RX_EN__EIM_ADDR26		0x00ec 0x0378 0x0000 4 0
+#define MX6UL_PAD_ENET2_RX_EN__GPIO2_IO10		0x00ec 0x0378 0x0000 5 0
+#define MX6UL_PAD_ENET2_RX_EN__KPP_ROW05		0x00ec 0x0378 0x0000 6 0
+#define MX6UL_PAD_ENET2_RX_EN__ENET1_REF_CLK_25M	0x00ec 0x0378 0x0000 8 0
+#define MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00		0x00f0 0x037c 0x0000 0 0
+#define MX6UL_PAD_ENET2_TX_DATA0__UART7_DCE_RX		0x00f0 0x037c 0x0654 1 1
+#define MX6UL_PAD_ENET2_TX_DATA0__UART7_DTE_TX		0x00f0 0x037c 0x0000 1 0
+#define MX6UL_PAD_ENET2_TX_DATA0__SIM1_PORT0_SVEN	0x00f0 0x037c 0x0000 2 0
+#define MX6UL_PAD_ENET2_TX_DATA0__I2C4_SDA		0x00f0 0x037c 0x05c0 3 1
+#define MX6UL_PAD_ENET2_TX_DATA0__EIM_EB_B02		0x00f0 0x037c 0x0000 4 0
+#define MX6UL_PAD_ENET2_TX_DATA0__GPIO2_IO11		0x00f0 0x037c 0x0000 5 0
+#define MX6UL_PAD_ENET2_TX_DATA0__KPP_COL05		0x00f0 0x037c 0x0000 6 0
+#define MX6UL_PAD_ENET2_TX_DATA0__REF_CLK_24M		0x00f0 0x037c 0x0000 8 0
+#define MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01		0x00f4 0x0380 0x0000 0 0
+#define MX6UL_PAD_ENET2_TX_DATA1__UART8_DCE_TX		0x00f4 0x0380 0x0000 1 0
+#define MX6UL_PAD_ENET2_TX_DATA1__UART8_DTE_RX		0x00f4 0x0380 0x065c 1 0
+#define MX6UL_PAD_ENET2_TX_DATA1__SIM2_PORT0_TRXD	0x00f4 0x0380 0x0000 2 0
+#define MX6UL_PAD_ENET2_TX_DATA1__ECSPI4_SCLK		0x00f4 0x0380 0x0564 3 0
+#define MX6UL_PAD_ENET2_TX_DATA1__EIM_EB_B03		0x00f4 0x0380 0x0000 4 0
+#define MX6UL_PAD_ENET2_TX_DATA1__GPIO2_IO12		0x00f4 0x0380 0x0000 5 0
+#define MX6UL_PAD_ENET2_TX_DATA1__KPP_ROW06		0x00f4 0x0380 0x0000 6 0
+#define MX6UL_PAD_ENET2_TX_DATA1__USB_OTG2_PWR		0x00f4 0x0380 0x0000 8 0
+#define MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN		0x00f8 0x0384 0x0000 0 0
+#define MX6UL_PAD_ENET2_TX_EN__UART8_DCE_RX		0x00f8 0x0384 0x065c 1 1
+#define MX6UL_PAD_ENET2_TX_EN__UART8_DTE_TX		0x00f8 0x0384 0x0000 1 0
+#define MX6UL_PAD_ENET2_TX_EN__SIM2_PORT0_CLK		0x00f8 0x0384 0x0000 2 0
+#define MX6UL_PAD_ENET2_TX_EN__ECSPI4_MOSI		0x00f8 0x0384 0x056c 3 0
+#define MX6UL_PAD_ENET2_TX_EN__EIM_ACLK_FREERUN		0x00f8 0x0384 0x0000 4 0
+#define MX6UL_PAD_ENET2_TX_EN__GPIO2_IO13		0x00f8 0x0384 0x0000 5 0
+#define MX6UL_PAD_ENET2_TX_EN__KPP_COL06		0x00f8 0x0384 0x0000 6 0
+#define MX6UL_PAD_ENET2_TX_EN__USB_OTG2_OC		0x00f8 0x0384 0x0660 8 1
+#define MX6UL_PAD_ENET2_TX_CLK__ENET2_TX_CLK		0x00fc 0x0388 0x0000 0 0
+#define MX6UL_PAD_ENET2_TX_CLK__UART8_DCE_CTS		0x00fc 0x0388 0x0000 1 0
+#define MX6UL_PAD_ENET2_TX_CLK__UART8_DTE_RTS		0x00fc 0x0388 0x0658 1 0
+#define MX6UL_PAD_ENET2_TX_CLK__SIM2_PORT0_RST_B	0x00fc 0x0388 0x0000 2 0
+#define MX6UL_PAD_ENET2_TX_CLK__ECSPI4_MISO		0x00fc 0x0388 0x0568 3 0
+#define MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2		0x00fc 0x0388 0x057c 4 2
+#define MX6UL_PAD_ENET2_TX_CLK__GPIO2_IO14		0x00fc 0x0388 0x0000 5 0
+#define MX6UL_PAD_ENET2_TX_CLK__KPP_ROW07		0x00fc 0x0388 0x0000 6 0
+#define MX6UL_PAD_ENET2_TX_CLK__ANATOP_OTG2_ID		0x00fc 0x0388 0x04bc 8 1
+#define MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER		0x0100 0x038c 0x0000 0 0
+#define MX6UL_PAD_ENET2_RX_ER__UART8_DCE_RTS		0x0100 0x038c 0x0658 1 1
+#define MX6UL_PAD_ENET2_RX_ER__UART8_DTE_CTS		0x0100 0x038c 0x0000 1 0
+#define MX6UL_PAD_ENET2_RX_ER__SIM2_PORT0_SVEN		0x0100 0x038c 0x0000 2 0
+#define MX6UL_PAD_ENET2_RX_ER__ECSPI4_SS0		0x0100 0x038c 0x0570 3 0
+#define MX6UL_PAD_ENET2_RX_ER__EIM_ADDR25		0x0100 0x038c 0x0000 4 0
+#define MX6UL_PAD_ENET2_RX_ER__GPIO2_IO15		0x0100 0x038c 0x0000 5 0
+#define MX6UL_PAD_ENET2_RX_ER__KPP_COL07		0x0100 0x038c 0x0000 6 0
+#define MX6UL_PAD_ENET2_RX_ER__WDOG1_WDOG_ANY		0x0100 0x038c 0x0000 8 0
+#define MX6UL_PAD_LCD_CLK__LCDIF_CLK			0x0104 0x0390 0x0000 0 0
+#define MX6UL_PAD_LCD_CLK__LCDIF_WR_RWN			0x0104 0x0390 0x0000 1 0
+#define MX6UL_PAD_LCD_CLK__UART4_DCE_TX			0x0104 0x0390 0x0000 2 0
+#define MX6UL_PAD_LCD_CLK__UART4_DTE_RX			0x0104 0x0390 0x063c 2 2
+#define MX6UL_PAD_LCD_CLK__SAI3_MCLK			0x0104 0x0390 0x0600 3 0
+#define MX6UL_PAD_LCD_CLK__EIM_CS2_B			0x0104 0x0390 0x0000 4 0
+#define MX6UL_PAD_LCD_CLK__GPIO3_IO00			0x0104 0x0390 0x0000 5 0
+#define MX6UL_PAD_LCD_CLK__WDOG1_WDOG_RST_B_DEB		0x0104 0x0390 0x0000 8 0
+#define MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE		0x0108 0x0394 0x0000 0 0
+#define MX6UL_PAD_LCD_ENABLE__LCDIF_RD_E		0x0108 0x0394 0x0000 1 0
+#define MX6UL_PAD_LCD_ENABLE__UART4_DCE_RX		0x0108 0x0394 0x063c 2 3
+#define MX6UL_PAD_LCD_ENABLE__UART4_DTE_TX		0x0108 0x0394 0x0000 2 0
+#define MX6UL_PAD_LCD_ENABLE__SAI3_TX_SYNC		0x0108 0x0394 0x060c 3 0
+#define MX6UL_PAD_LCD_ENABLE__EIM_CS3_B			0x0108 0x0394 0x0000 4 0
+#define MX6UL_PAD_LCD_ENABLE__GPIO3_IO01		0x0108 0x0394 0x0000 5 0
+#define MX6UL_PAD_LCD_ENABLE__ECSPI2_RDY		0x0108 0x0394 0x0000 8 0
+#define MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC		0x010c 0x0398 0x05dc 0 0
+#define MX6UL_PAD_LCD_HSYNC__LCDIF_RS			0x010c 0x0398 0x0000 1 0
+#define MX6UL_PAD_LCD_HSYNC__UART4_DCE_CTS		0x010c 0x0398 0x0000 2 0
+#define MX6UL_PAD_LCD_HSYNC__UART4_DTE_RTS		0x010c 0x0398 0x0638 2 2
+#define MX6UL_PAD_LCD_HSYNC__SAI3_TX_BCLK		0x010c 0x0398 0x0608 3 0
+#define MX6UL_PAD_LCD_HSYNC__WDOG3_WDOG_RST_B_DEB	0x010c 0x0398 0x0000 4 0
+#define MX6UL_PAD_LCD_HSYNC__GPIO3_IO02			0x010c 0x0398 0x0000 5 0
+#define MX6UL_PAD_LCD_HSYNC__ECSPI2_SS1			0x010c 0x0398 0x0000 8 0
+#define MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC		0x0110 0x039c 0x0000 0 0
+#define MX6UL_PAD_LCD_VSYNC__LCDIF_BUSY			0x0110 0x039c 0x05dc 1 1
+#define MX6UL_PAD_LCD_VSYNC__UART4_DCE_RTS		0x0110 0x039c 0x0638 2 3
+#define MX6UL_PAD_LCD_VSYNC__UART4_DTE_CTS		0x0110 0x039c 0x0000 2 0
+#define MX6UL_PAD_LCD_VSYNC__SAI3_RX_DATA		0x0110 0x039c 0x0604 3 0
+#define MX6UL_PAD_LCD_VSYNC__WDOG2_WDOG_B		0x0110 0x039c 0x0000 4 0
+#define MX6UL_PAD_LCD_VSYNC__GPIO3_IO03			0x0110 0x039c 0x0000 5 0
+#define MX6UL_PAD_LCD_VSYNC__ECSPI2_SS2			0x0110 0x039c 0x0000 8 0
+#define MX6UL_PAD_LCD_RESET__LCDIF_RESET		0x0114 0x03a0 0x0000 0 0
+#define MX6UL_PAD_LCD_RESET__LCDIF_CS			0x0114 0x03a0 0x0000 1 0
+#define MX6UL_PAD_LCD_RESET__CA7_MX6UL_EVENTI		0x0114 0x03a0 0x0000 2 0
+#define MX6UL_PAD_LCD_RESET__SAI3_TX_DATA		0x0114 0x03a0 0x0000 3 0
+#define MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY		0x0114 0x03a0 0x0000 4 0
+#define MX6UL_PAD_LCD_RESET__GPIO3_IO04			0x0114 0x03a0 0x0000 5 0
+#define MX6UL_PAD_LCD_RESET__ECSPI2_SS3			0x0114 0x03a0 0x0000 8 0
+#define MX6UL_PAD_LCD_DATA00__LCDIF_DATA00		0x0118 0x03a4 0x0000 0 0
+#define MX6UL_PAD_LCD_DATA00__PWM1_OUT			0x0118 0x03a4 0x0000 1 0
+#define MX6UL_PAD_LCD_DATA00__CA7_MX6UL_TRACE0		0x0118 0x03a4 0x0000 2 0
+#define MX6UL_PAD_LCD_DATA00__ENET1_1588_EVENT2_IN	0x0118 0x03a4 0x0000 3 0
+#define MX6UL_PAD_LCD_DATA00__I2C3_SDA			0x0118 0x03a4 0x05b8 4 2
+#define MX6UL_PAD_LCD_DATA00__GPIO3_IO05		0x0118 0x03a4 0x0000 5 0
+#define MX6UL_PAD_LCD_DATA00__SRC_BT_CFG00		0x0118 0x03a4 0x0000 6 0
+#define MX6UL_PAD_LCD_DATA00__SAI1_MCLK			0x0118 0x03a4 0x05e0 8 1
+#define MX6UL_PAD_LCD_DATA01__LCDIF_DATA01		0x011c 0x03a8 0x0000 0 0
+#define MX6UL_PAD_LCD_DATA01__PWM2_OUT			0x011c 0x03a8 0x0000 1 0
+#define MX6UL_PAD_LCD_DATA01__CA7_MX6UL_TRACE1		0x011c 0x03a8 0x0000 2 0
+#define MX6UL_PAD_LCD_DATA01__ENET1_1588_EVENT2_OUT	0x011c 0x03a8 0x0000 3 0
+#define MX6UL_PAD_LCD_DATA01__I2C3_SCL			0x011c 0x03a8 0x05b4 4 2
+#define MX6UL_PAD_LCD_DATA01__GPIO3_IO06		0x011c 0x03a8 0x0000 5 0
+#define MX6UL_PAD_LCD_DATA01__SRC_BT_CFG01		0x011c 0x03a8 0x0000 6 0
+#define MX6UL_PAD_LCD_DATA01__SAI1_TX_SYNC		0x011c 0x03a8 0x05ec 8 0
+#define MX6UL_PAD_LCD_DATA02__LCDIF_DATA02		0x0120 0x03ac 0x0000 0 0
+#define MX6UL_PAD_LCD_DATA02__PWM3_OUT			0x0120 0x03ac 0x0000 1 0
+#define MX6UL_PAD_LCD_DATA02__CA7_MX6UL_TRACE2		0x0120 0x03ac 0x0000 2 0
+#define MX6UL_PAD_LCD_DATA02__ENET1_1588_EVENT3_IN	0x0120 0x03ac 0x0000 3 0
+#define MX6UL_PAD_LCD_DATA02__I2C4_SDA			0x0120 0x03ac 0x05c0 4 2
+#define MX6UL_PAD_LCD_DATA02__GPIO3_IO07		0x0120 0x03ac 0x0000 5 0
+#define MX6UL_PAD_LCD_DATA02__SRC_BT_CFG02		0x0120 0x03ac 0x0000 6 0
+#define MX6UL_PAD_LCD_DATA02__SAI1_TX_BCLK		0x0120 0x03ac 0x05e8 8 0
+#define MX6UL_PAD_LCD_DATA03__LCDIF_DATA03		0x0124 0x03b0 0x0000 0 0
+#define MX6UL_PAD_LCD_DATA03__PWM4_OUT			0x0124 0x03b0 0x0000 1 0
+#define MX6UL_PAD_LCD_DATA03__CA7_MX6UL_TRACE3		0x0124 0x03b0 0x0000 2 0
+#define MX6UL_PAD_LCD_DATA03__ENET1_1588_EVENT3_OUT	0x0124 0x03b0 0x0000 3 0
+#define MX6UL_PAD_LCD_DATA03__I2C4_SCL			0x0124 0x03b0 0x05bc 4 2
+#define MX6UL_PAD_LCD_DATA03__GPIO3_IO08		0x0124 0x03b0 0x0000 5 0
+#define MX6UL_PAD_LCD_DATA03__SRC_BT_CFG03		0x0124 0x03b0 0x0000 6 0
+#define MX6UL_PAD_LCD_DATA03__SAI1_RX_DATA		0x0124 0x03b0 0x05e4 8 0
+#define MX6UL_PAD_LCD_DATA04__LCDIF_DATA04		0x0128 0x03b4 0x0000 0 0
+#define MX6UL_PAD_LCD_DATA04__UART8_DCE_CTS		0x0128 0x03b4 0x0000 1 0
+#define MX6UL_PAD_LCD_DATA04__UART8_DTE_RTS		0x0128 0x03b4 0x0658 1 2
+#define MX6UL_PAD_LCD_DATA04__CA7_MX6UL_TRACE4		0x0128 0x03b4 0x0000 2 0
+#define MX6UL_PAD_LCD_DATA04__ENET2_1588_EVENT2_IN	0x0128 0x03b4 0x0000 3 0
+#define MX6UL_PAD_LCD_DATA04__SPDIF_SR_CLK		0x0128 0x03b4 0x0000 4 0
+#define MX6UL_PAD_LCD_DATA04__GPIO3_IO09		0x0128 0x03b4 0x0000 5 0
+#define MX6UL_PAD_LCD_DATA04__SRC_BT_CFG04		0x0128 0x03b4 0x0000 6 0
+#define MX6UL_PAD_LCD_DATA04__SAI1_TX_DATA		0x0128 0x03b4 0x0000 8 0
+#define MX6UL_PAD_LCD_DATA05__LCDIF_DATA05		0x012c 0x03b8 0x0000 0 0
+#define MX6UL_PAD_LCD_DATA05__UART8_DCE_RTS		0x012c 0x03b8 0x0658 1 3
+#define MX6UL_PAD_LCD_DATA05__UART8_DTE_CTS		0x012c 0x03b8 0x0000 1 0
+#define MX6UL_PAD_LCD_DATA05__CA7_MX6UL_TRACE5		0x012c 0x03b8 0x0000 2 0
+#define MX6UL_PAD_LCD_DATA05__ENET2_1588_EVENT2_OUT	0x012c 0x03b8 0x0000 3 0
+#define MX6UL_PAD_LCD_DATA05__SPDIF_OUT			0x012c 0x03b8 0x0000 4 0
+#define MX6UL_PAD_LCD_DATA05__GPIO3_IO10		0x012c 0x03b8 0x0000 5 0
+#define MX6UL_PAD_LCD_DATA05__SRC_BT_CFG05		0x012c 0x03b8 0x0000 6 0
+#define MX6UL_PAD_LCD_DATA05__ECSPI1_SS1		0x012c 0x03b8 0x0000 8 0
+#define MX6UL_PAD_LCD_DATA06__LCDIF_DATA06		0x0130 0x03bc 0x0000 0 0
+#define MX6UL_PAD_LCD_DATA06__UART7_DCE_CTS		0x0130 0x03bc 0x0000 1 0
+#define MX6UL_PAD_LCD_DATA06__UART7_DTE_RTS		0x0130 0x03bc 0x0650 1 2
+#define MX6UL_PAD_LCD_DATA06__CA7_MX6UL_TRACE6		0x0130 0x03bc 0x0000 2 0
+#define MX6UL_PAD_LCD_DATA06__ENET2_1588_EVENT3_IN	0x0130 0x03bc 0x0000 3 0
+#define MX6UL_PAD_LCD_DATA06__SPDIF_LOCK		0x0130 0x03bc 0x0000 4 0
+#define MX6UL_PAD_LCD_DATA06__GPIO3_IO11		0x0130 0x03bc 0x0000 5 0
+#define MX6UL_PAD_LCD_DATA06__SRC_BT_CFG06		0x0130 0x03bc 0x0000 6 0
+#define MX6UL_PAD_LCD_DATA06__ECSPI1_SS2		0x0130 0x03bc 0x0000 8 0
+#define MX6UL_PAD_LCD_DATA07__LCDIF_DATA07		0x0134 0x03c0 0x0000 0 0
+#define MX6UL_PAD_LCD_DATA07__UART7_DCE_RTS		0x0134 0x03c0 0x0650 1 3
+#define MX6UL_PAD_LCD_DATA07__UART7_DTE_CTS		0x0134 0x03c0 0x0000 1 0
+#define MX6UL_PAD_LCD_DATA07__CA7_MX6UL_TRACE7		0x0134 0x03c0 0x0000 2 0
+#define MX6UL_PAD_LCD_DATA07__ENET2_1588_EVENT3_OUT	0x0134 0x03c0 0x0000 3 0
+#define MX6UL_PAD_LCD_DATA07__SPDIF_EXT_CLK		0x0134 0x03c0 0x061c 4 0
+#define MX6UL_PAD_LCD_DATA07__GPIO3_IO12		0x0134 0x03c0 0x0000 5 0
+#define MX6UL_PAD_LCD_DATA07__SRC_BT_CFG07		0x0134 0x03c0 0x0000 6 0
+#define MX6UL_PAD_LCD_DATA07__ECSPI1_SS3		0x0134 0x03c0 0x0000 8 0
+#define MX6UL_PAD_LCD_DATA08__LCDIF_DATA08		0x0138 0x03c4 0x0000 0 0
+#define MX6UL_PAD_LCD_DATA08__SPDIF_IN			0x0138 0x03c4 0x0618 1 2
+#define MX6UL_PAD_LCD_DATA08__CA7_MX6UL_TRACE8		0x0138 0x03c4 0x0000 2 0
+#define MX6UL_PAD_LCD_DATA08__CSI_DATA16		0x0138 0x03c4 0x0504 3 1
+#define MX6UL_PAD_LCD_DATA08__EIM_DATA00		0x0138 0x03c4 0x0000 4 0
+#define MX6UL_PAD_LCD_DATA08__GPIO3_IO13		0x0138 0x03c4 0x0000 5 0
+#define MX6UL_PAD_LCD_DATA08__SRC_BT_CFG08		0x0138 0x03c4 0x0000 6 0
+#define MX6UL_PAD_LCD_DATA08__FLEXCAN1_TX		0x0138 0x03c4 0x0000 8 0
+#define MX6UL_PAD_LCD_DATA09__LCDIF_DATA09		0x013c 0x03c8 0x0000 0 0
+#define MX6UL_PAD_LCD_DATA09__SAI3_MCLK			0x013c 0x03c8 0x0600 1 1
+#define MX6UL_PAD_LCD_DATA09__CA7_MX6UL_TRACE9		0x013c 0x03c8 0x0000 2 0
+#define MX6UL_PAD_LCD_DATA09__CSI_DATA17		0x013c 0x03c8 0x0508 3 1
+#define MX6UL_PAD_LCD_DATA09__EIM_DATA01		0x013c 0x03c8 0x0000 4 0
+#define MX6UL_PAD_LCD_DATA09__GPIO3_IO14		0x013c 0x03c8 0x0000 5 0
+#define MX6UL_PAD_LCD_DATA09__SRC_BT_CFG09		0x013c 0x03c8 0x0000 6 0
+#define MX6UL_PAD_LCD_DATA09__FLEXCAN1_RX		0x013c 0x03c8 0x0584 8 2
+#define MX6UL_PAD_LCD_DATA10__LCDIF_DATA10		0x0140 0x03cc 0x0000 0 0
+#define MX6UL_PAD_LCD_DATA10__SAI3_RX_SYNC		0x0140 0x03cc 0x0000 1 0
+#define MX6UL_PAD_LCD_DATA10__CA7_MX6UL_TRACE10		0x0140 0x03cc 0x0000 2 0
+#define MX6UL_PAD_LCD_DATA10__CSI_DATA18		0x0140 0x03cc 0x050c 3 1
+#define MX6UL_PAD_LCD_DATA10__EIM_DATA02		0x0140 0x03cc 0x0000 4 0
+#define MX6UL_PAD_LCD_DATA10__GPIO3_IO15		0x0140 0x03cc 0x0000 5 0
+#define MX6UL_PAD_LCD_DATA10__SRC_BT_CFG10		0x0140 0x03cc 0x0000 6 0
+#define MX6UL_PAD_LCD_DATA10__FLEXCAN2_TX		0x0140 0x03cc 0x0000 8 0
+#define MX6UL_PAD_LCD_DATA11__LCDIF_DATA11		0x0144 0x03d0 0x0000 0 0
+#define MX6UL_PAD_LCD_DATA11__SAI3_RX_BCLK		0x0144 0x03d0 0x0000 1 0
+#define MX6UL_PAD_LCD_DATA11__CA7_MX6UL_TRACE11		0x0144 0x03d0 0x0000 2 0
+#define MX6UL_PAD_LCD_DATA11__CSI_DATA19		0x0144 0x03d0 0x0510 3 1
+#define MX6UL_PAD_LCD_DATA11__EIM_DATA03		0x0144 0x03d0 0x0000 4 0
+#define MX6UL_PAD_LCD_DATA11__GPIO3_IO16		0x0144 0x03d0 0x0000 5 0
+#define MX6UL_PAD_LCD_DATA11__SRC_BT_CFG11		0x0144 0x03d0 0x0000 6 0
+#define MX6UL_PAD_LCD_DATA11__FLEXCAN2_RX		0x0144 0x03d0 0x0588 8 2
+#define MX6UL_PAD_LCD_DATA12__LCDIF_DATA12		0x0148 0x03d4 0x0000 0 0
+#define MX6UL_PAD_LCD_DATA12__SAI3_TX_SYNC		0x0148 0x03d4 0x060c 1 1
+#define MX6UL_PAD_LCD_DATA12__CA7_MX6UL_TRACE12		0x0148 0x03d4 0x0000 2 0
+#define MX6UL_PAD_LCD_DATA12__CSI_DATA20		0x0148 0x03d4 0x0514 3 1
+#define MX6UL_PAD_LCD_DATA12__EIM_DATA04		0x0148 0x03d4 0x0000 4 0
+#define MX6UL_PAD_LCD_DATA12__GPIO3_IO17		0x0148 0x03d4 0x0000 5 0
+#define MX6UL_PAD_LCD_DATA12__SRC_BT_CFG12		0x0148 0x03d4 0x0000 6 0
+#define MX6UL_PAD_LCD_DATA12__ECSPI1_RDY		0x0148 0x03d4 0x0000 8 0
+#define MX6UL_PAD_LCD_DATA13__LCDIF_DATA13		0x014c 0x03d8 0x0000 0 0
+#define MX6UL_PAD_LCD_DATA13__SAI3_TX_BCLK		0x014c 0x03d8 0x0608 1 1
+#define MX6UL_PAD_LCD_DATA13__CA7_MX6UL_TRACE13		0x014c 0x03d8 0x0000 2 0
+#define MX6UL_PAD_LCD_DATA13__CSI_DATA21		0x014c 0x03d8 0x0518 3 1
+#define MX6UL_PAD_LCD_DATA13__EIM_DATA05		0x014c 0x03d8 0x0000 4 0
+#define MX6UL_PAD_LCD_DATA13__GPIO3_IO18		0x014c 0x03d8 0x0000 5 0
+#define MX6UL_PAD_LCD_DATA13__SRC_BT_CFG13		0x014c 0x03d8 0x0000 6 0
+#define MX6UL_PAD_LCD_DATA13__USDHC2_RESET_B		0x014c 0x03d8 0x0000 8 0
+#define MX6UL_PAD_LCD_DATA14__LCDIF_DATA14		0x0150 0x03dc 0x0000 0 0
+#define MX6UL_PAD_LCD_DATA14__SAI3_RX_DATA		0x0150 0x03dc 0x0604 1 1
+#define MX6UL_PAD_LCD_DATA14__CA7_MX6UL_TRACE14		0x0150 0x03dc 0x0000 2 0
+#define MX6UL_PAD_LCD_DATA14__CSI_DATA22		0x0150 0x03dc 0x051c 3 1
+#define MX6UL_PAD_LCD_DATA14__EIM_DATA06		0x0150 0x03dc 0x0000 4 0
+#define MX6UL_PAD_LCD_DATA14__GPIO3_IO19		0x0150 0x03dc 0x0000 5 0
+#define MX6UL_PAD_LCD_DATA14__SRC_BT_CFG14		0x0150 0x03dc 0x0000 6 0
+#define MX6UL_PAD_LCD_DATA14__USDHC2_DATA4		0x0150 0x03dc 0x068c 8 0
+#define MX6UL_PAD_LCD_DATA15__LCDIF_DATA15		0x0154 0x03e0 0x0000 0 0
+#define MX6UL_PAD_LCD_DATA15__SAI3_TX_DATA		0x0154 0x03e0 0x0000 1 0
+#define MX6UL_PAD_LCD_DATA15__CA7_MX6UL_TRACE15		0x0154 0x03e0 0x0000 2 0
+#define MX6UL_PAD_LCD_DATA15__CSI_DATA23		0x0154 0x03e0 0x0520 3 1
+#define MX6UL_PAD_LCD_DATA15__EIM_DATA07		0x0154 0x03e0 0x0000 4 0
+#define MX6UL_PAD_LCD_DATA15__GPIO3_IO20		0x0154 0x03e0 0x0000 5 0
+#define MX6UL_PAD_LCD_DATA15__SRC_BT_CFG15		0x0154 0x03e0 0x0000 6 0
+#define MX6UL_PAD_LCD_DATA15__USDHC2_DATA5		0x0154 0x03e0 0x0690 8 0
+#define MX6UL_PAD_LCD_DATA16__LCDIF_DATA16		0x0158 0x03e4 0x0000 0 0
+#define MX6UL_PAD_LCD_DATA16__UART7_DCE_TX		0x0158 0x03e4 0x0000 1 0
+#define MX6UL_PAD_LCD_DATA16__UART7_DTE_RX		0x0158 0x03e4 0x0654 1 2
+#define MX6UL_PAD_LCD_DATA16__CA7_MX6UL_TRACE_CLK	0x0158 0x03e4 0x0000 2 0
+#define MX6UL_PAD_LCD_DATA16__CSI_DATA01		0x0158 0x03e4 0x04d4 3 1
+#define MX6UL_PAD_LCD_DATA16__EIM_DATA08		0x0158 0x03e4 0x0000 4 0
+#define MX6UL_PAD_LCD_DATA16__GPIO3_IO21		0x0158 0x03e4 0x0000 5 0
+#define MX6UL_PAD_LCD_DATA16__SRC_BT_CFG24		0x0158 0x03e4 0x0000 6 0
+#define MX6UL_PAD_LCD_DATA16__USDHC2_DATA6		0x0158 0x03e4 0x0694 8 0
+#define MX6UL_PAD_LCD_DATA17__LCDIF_DATA17		0x015c 0x03e8 0x0000 0 0
+#define MX6UL_PAD_LCD_DATA17__UART7_DCE_RX		0x015c 0x03e8 0x0654 1 3
+#define MX6UL_PAD_LCD_DATA17__UART7_DTE_TX		0x015c 0x03e8 0x0000 1 0
+#define MX6UL_PAD_LCD_DATA17__CA7_MX6UL_TRACE_CTL	0x015c 0x03e8 0x0000 2 0
+#define MX6UL_PAD_LCD_DATA17__CSI_DATA00		0x015c 0x03e8 0x04d0 3 1
+#define MX6UL_PAD_LCD_DATA17__EIM_DATA09		0x015c 0x03e8 0x0000 4 0
+#define MX6UL_PAD_LCD_DATA17__GPIO3_IO22		0x015c 0x03e8 0x0000 5 0
+#define MX6UL_PAD_LCD_DATA17__SRC_BT_CFG25		0x015c 0x03e8 0x0000 6 0
+#define MX6UL_PAD_LCD_DATA17__USDHC2_DATA7		0x015c 0x03e8 0x0698 8 0
+#define MX6UL_PAD_LCD_DATA18__LCDIF_DATA18		0x0160 0x03ec 0x0000 0 0
+#define MX6UL_PAD_LCD_DATA18__PWM5_OUT			0x0160 0x03ec 0x0000 1 0
+#define MX6UL_PAD_LCD_DATA18__CA7_MX6UL_EVENTO		0x0160 0x03ec 0x0000 2 0
+#define MX6UL_PAD_LCD_DATA18__CSI_DATA10		0x0160 0x03ec 0x04ec 3 1
+#define MX6UL_PAD_LCD_DATA18__EIM_DATA10		0x0160 0x03ec 0x0000 4 0
+#define MX6UL_PAD_LCD_DATA18__GPIO3_IO23		0x0160 0x03ec 0x0000 5 0
+#define MX6UL_PAD_LCD_DATA18__SRC_BT_CFG26		0x0160 0x03ec 0x0000 6 0
+#define MX6UL_PAD_LCD_DATA18__USDHC2_CMD		0x0160 0x03ec 0x0678 8 1
+#define MX6UL_PAD_LCD_DATA19__EIM_DATA11		0x0164 0x03f0 0x0000 4 0
+#define MX6UL_PAD_LCD_DATA19__GPIO3_IO24		0x0164 0x03f0 0x0000 5 0
+#define MX6UL_PAD_LCD_DATA19__SRC_BT_CFG27		0x0164 0x03f0 0x0000 6 0
+#define MX6UL_PAD_LCD_DATA19__USDHC2_CLK		0x0164 0x03f0 0x0670 8 1
+#define MX6UL_PAD_LCD_DATA19__LCDIF_DATA19		0x0164 0x03f0 0x0000 0 0
+#define MX6UL_PAD_LCD_DATA19__PWM6_OUT			0x0164 0x03f0 0x0000 1 0
+#define MX6UL_PAD_LCD_DATA19__WDOG1_WDOG_ANY		0x0164 0x03f0 0x0000 2 0
+#define MX6UL_PAD_LCD_DATA19__CSI_DATA11		0x0164 0x03f0 0x04f0 3 1
+#define MX6UL_PAD_LCD_DATA20__EIM_DATA12		0x0168 0x03f4 0x0000 4 0
+#define MX6UL_PAD_LCD_DATA20__GPIO3_IO25		0x0168 0x03f4 0x0000 5 0
+#define MX6UL_PAD_LCD_DATA20__SRC_BT_CFG28		0x0168 0x03f4 0x0000 6 0
+#define MX6UL_PAD_LCD_DATA20__USDHC2_DATA0		0x0168 0x03f4 0x067c 8 1
+#define MX6UL_PAD_LCD_DATA20__LCDIF_DATA20		0x0168 0x03f4 0x0000 0 0
+#define MX6UL_PAD_LCD_DATA20__UART8_DCE_TX		0x0168 0x03f4 0x0000 1 0
+#define MX6UL_PAD_LCD_DATA20__UART8_DTE_RX		0x0168 0x03f4 0x065c 1 2
+#define MX6UL_PAD_LCD_DATA20__ECSPI1_SCLK		0x0168 0x03f4 0x0534 2 0
+#define MX6UL_PAD_LCD_DATA20__CSI_DATA12		0x0168 0x03f4 0x04f4 3 1
+#define MX6UL_PAD_LCD_DATA21__LCDIF_DATA21		0x016c 0x03f8 0x0000 0 0
+#define MX6UL_PAD_LCD_DATA21__UART8_DCE_RX		0x016c 0x03f8 0x065c 1 3
+#define MX6UL_PAD_LCD_DATA21__UART8_DTE_TX		0x016c 0x03f8 0x0000 1 0
+#define MX6UL_PAD_LCD_DATA21__ECSPI1_SS0		0x016c 0x03f8 0x0540 2 0
+#define MX6UL_PAD_LCD_DATA21__CSI_DATA13		0x016c 0x03f8 0x04f8 3 1
+#define MX6UL_PAD_LCD_DATA21__EIM_DATA13		0x016c 0x03f8 0x0000 4 0
+#define MX6UL_PAD_LCD_DATA21__GPIO3_IO26		0x016c 0x03f8 0x0000 5 0
+#define MX6UL_PAD_LCD_DATA21__SRC_BT_CFG29		0x016c 0x03f8 0x0000 6 0
+#define MX6UL_PAD_LCD_DATA21__USDHC2_DATA1		0x016c 0x03f8 0x0680 8 1
+#define MX6UL_PAD_LCD_DATA22__LCDIF_DATA22		0x0170 0x03fc 0x0000 0 0
+#define MX6UL_PAD_LCD_DATA22__MQS_RIGHT			0x0170 0x03fc 0x0000 1 0
+#define MX6UL_PAD_LCD_DATA22__ECSPI1_MOSI		0x0170 0x03fc 0x053c 2 0
+#define MX6UL_PAD_LCD_DATA22__CSI_DATA14		0x0170 0x03fc 0x04fc 3 1
+#define MX6UL_PAD_LCD_DATA22__EIM_DATA14		0x0170 0x03fc 0x0000 4 0
+#define MX6UL_PAD_LCD_DATA22__GPIO3_IO27		0x0170 0x03fc 0x0000 5 0
+#define MX6UL_PAD_LCD_DATA22__SRC_BT_CFG30		0x0170 0x03fc 0x0000 6 0
+#define MX6UL_PAD_LCD_DATA22__USDHC2_DATA2		0x0170 0x03fc 0x0684 8 0
+#define MX6UL_PAD_LCD_DATA23__LCDIF_DATA23		0x0174 0x0400 0x0000 0 0
+#define MX6UL_PAD_LCD_DATA23__MQS_LEFT			0x0174 0x0400 0x0000 1 0
+#define MX6UL_PAD_LCD_DATA23__ECSPI1_MISO		0x0174 0x0400 0x0538 2 0
+#define MX6UL_PAD_LCD_DATA23__CSI_DATA15		0x0174 0x0400 0x0500 3 1
+#define MX6UL_PAD_LCD_DATA23__EIM_DATA15		0x0174 0x0400 0x0000 4 0
+#define MX6UL_PAD_LCD_DATA23__GPIO3_IO28		0x0174 0x0400 0x0000 5 0
+#define MX6UL_PAD_LCD_DATA23__SRC_BT_CFG31		0x0174 0x0400 0x0000 6 0
+#define MX6UL_PAD_LCD_DATA23__USDHC2_DATA3		0x0174 0x0400 0x0688 8 1
+#define MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B		0x0178 0x0404 0x0000 0 0
+#define MX6UL_PAD_NAND_RE_B__USDHC2_CLK			0x0178 0x0404 0x0670 1 2
+#define MX6UL_PAD_NAND_RE_B__QSPI_B_SCLK		0x0178 0x0404 0x0000 2 0
+#define MX6UL_PAD_NAND_RE_B__KPP_ROW00			0x0178 0x0404 0x05d0 3 1
+#define MX6UL_PAD_NAND_RE_B__EIM_EB_B00			0x0178 0x0404 0x0000 4 0
+#define MX6UL_PAD_NAND_RE_B__GPIO4_IO00			0x0178 0x0404 0x0000 5 0
+#define MX6UL_PAD_NAND_RE_B__ECSPI3_SS2			0x0178 0x0404 0x0000 8 0
+#define MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B		0x017c 0x0408 0x0000 0 0
+#define MX6UL_PAD_NAND_WE_B__USDHC2_CMD			0x017c 0x0408 0x0678 1 2
+#define MX6UL_PAD_NAND_WE_B__QSPI_B_SS0_B		0x017c 0x0408 0x0000 2 0
+#define MX6UL_PAD_NAND_WE_B__KPP_COL00			0x017c 0x0408 0x05c4 3 1
+#define MX6UL_PAD_NAND_WE_B__EIM_EB_B01			0x017c 0x0408 0x0000 4 0
+#define MX6UL_PAD_NAND_WE_B__GPIO4_IO01			0x017c 0x0408 0x0000 5 0
+#define MX6UL_PAD_NAND_WE_B__ECSPI3_SS3			0x017c 0x0408 0x0000 8 0
+#define MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00		0x0180 0x040c 0x0000 0 0
+#define MX6UL_PAD_NAND_DATA00__USDHC2_DATA0		0x0180 0x040c 0x067c 1 2
+#define MX6UL_PAD_NAND_DATA00__QSPI_B_SS1_B		0x0180 0x040c 0x0000 2 0
+#define MX6UL_PAD_NAND_DATA00__KPP_ROW01		0x0180 0x040c 0x05d4 3 1
+#define MX6UL_PAD_NAND_DATA00__EIM_AD08			0x0180 0x040c 0x0000 4 0
+#define MX6UL_PAD_NAND_DATA00__GPIO4_IO02		0x0180 0x040c 0x0000 5 0
+#define MX6UL_PAD_NAND_DATA00__ECSPI4_RDY		0x0180 0x040c 0x0000 8 0
+#define MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01		0x0184 0x0410 0x0000 0 0
+#define MX6UL_PAD_NAND_DATA01__USDHC2_DATA1		0x0184 0x0410 0x0680 1 2
+#define MX6UL_PAD_NAND_DATA01__QSPI_B_DQS		0x0184 0x0410 0x0000 2 0
+#define MX6UL_PAD_NAND_DATA01__KPP_COL01		0x0184 0x0410 0x05c8 3 1
+#define MX6UL_PAD_NAND_DATA01__EIM_AD09			0x0184 0x0410 0x0000 4 0
+#define MX6UL_PAD_NAND_DATA01__GPIO4_IO03		0x0184 0x0410 0x0000 5 0
+#define MX6UL_PAD_NAND_DATA01__ECSPI4_SS1		0x0184 0x0410 0x0000 8 0
+#define MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02		0x0188 0x0414 0x0000 0 0
+#define MX6UL_PAD_NAND_DATA02__USDHC2_DATA2		0x0188 0x0414 0x0684 1 1
+#define MX6UL_PAD_NAND_DATA02__QSPI_B_DATA00		0x0188 0x0414 0x0000 2 0
+#define MX6UL_PAD_NAND_DATA02__KPP_ROW02		0x0188 0x0414 0x05d8 3 1
+#define MX6UL_PAD_NAND_DATA02__EIM_AD10			0x0188 0x0414 0x0000 4 0
+#define MX6UL_PAD_NAND_DATA02__GPIO4_IO04		0x0188 0x0414 0x0000 5 0
+#define MX6UL_PAD_NAND_DATA02__ECSPI4_SS2		0x0188 0x0414 0x0000 8 0
+#define MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03		0x018c 0x0418 0x0000 0 0
+#define MX6UL_PAD_NAND_DATA03__USDHC2_DATA3		0x018c 0x0418 0x0688 1 2
+#define MX6UL_PAD_NAND_DATA03__QSPI_B_DATA01		0x018c 0x0418 0x0000 2 0
+#define MX6UL_PAD_NAND_DATA03__KPP_COL02		0x018c 0x0418 0x05cc 3 1
+#define MX6UL_PAD_NAND_DATA03__EIM_AD11			0x018c 0x0418 0x0000 4 0
+#define MX6UL_PAD_NAND_DATA03__GPIO4_IO05		0x018c 0x0418 0x0000 5 0
+#define MX6UL_PAD_NAND_DATA03__ECSPI4_SS3		0x018c 0x0418 0x0000 8 0
+#define MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04		0x0190 0x041c 0x0000 0 0
+#define MX6UL_PAD_NAND_DATA04__USDHC2_DATA4		0x0190 0x041c 0x068c 1 1
+#define MX6UL_PAD_NAND_DATA04__QSPI_B_DATA02		0x0190 0x041c 0x0000 2 0
+#define MX6UL_PAD_NAND_DATA04__ECSPI4_SCLK		0x0190 0x041c 0x0564 3 1
+#define MX6UL_PAD_NAND_DATA04__EIM_AD12			0x0190 0x041c 0x0000 4 0
+#define MX6UL_PAD_NAND_DATA04__GPIO4_IO06		0x0190 0x041c 0x0000 5 0
+#define MX6UL_PAD_NAND_DATA04__UART2_DCE_TX		0x0190 0x041c 0x0000 8 0
+#define MX6UL_PAD_NAND_DATA04__UART2_DTE_RX		0x0190 0x041c 0x062c 8 2
+#define MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05		0x0194 0x0420 0x0000 0 0
+#define MX6UL_PAD_NAND_DATA05__USDHC2_DATA5		0x0194 0x0420 0x0690 1 1
+#define MX6UL_PAD_NAND_DATA05__QSPI_B_DATA03		0x0194 0x0420 0x0000 2 0
+#define MX6UL_PAD_NAND_DATA05__ECSPI4_MOSI		0x0194 0x0420 0x056c 3 1
+#define MX6UL_PAD_NAND_DATA05__EIM_AD13			0x0194 0x0420 0x0000 4 0
+#define MX6UL_PAD_NAND_DATA05__GPIO4_IO07		0x0194 0x0420 0x0000 5 0
+#define MX6UL_PAD_NAND_DATA05__UART2_DCE_RX		0x0194 0x0420 0x062c 8 3
+#define MX6UL_PAD_NAND_DATA05__UART2_DTE_TX		0x0194 0x0420 0x0000 8 0
+#define MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06		0x0198 0x0424 0x0000 0 0
+#define MX6UL_PAD_NAND_DATA06__USDHC2_DATA6		0x0198 0x0424 0x0694 1 1
+#define MX6UL_PAD_NAND_DATA06__SAI2_RX_BCLK		0x0198 0x0424 0x0000 2 0
+#define MX6UL_PAD_NAND_DATA06__ECSPI4_MISO		0x0198 0x0424 0x0568 3 1
+#define MX6UL_PAD_NAND_DATA06__EIM_AD14			0x0198 0x0424 0x0000 4 0
+#define MX6UL_PAD_NAND_DATA06__GPIO4_IO08		0x0198 0x0424 0x0000 5 0
+#define MX6UL_PAD_NAND_DATA06__UART2_DCE_CTS		0x0198 0x0424 0x0000 8 0
+#define MX6UL_PAD_NAND_DATA06__UART2_DTE_RTS		0x0198 0x0424 0x0628 8 4
+#define MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07		0x019c 0x0428 0x0000 0 0
+#define MX6UL_PAD_NAND_DATA07__USDHC2_DATA7		0x019c 0x0428 0x0698 1 1
+#define MX6UL_PAD_NAND_DATA07__QSPI_A_SS1_B		0x019c 0x0428 0x0000 2 0
+#define MX6UL_PAD_NAND_DATA07__ECSPI4_SS0		0x019c 0x0428 0x0570 3 1
+#define MX6UL_PAD_NAND_DATA07__EIM_AD15			0x019c 0x0428 0x0000 4 0
+#define MX6UL_PAD_NAND_DATA07__GPIO4_IO09		0x019c 0x0428 0x0000 5 0
+#define MX6UL_PAD_NAND_DATA07__UART2_DCE_RTS		0x019c 0x0428 0x0628 8 5
+#define MX6UL_PAD_NAND_DATA07__UART2_DTE_CTS		0x019c 0x0428 0x0000 8 0
+#define MX6UL_PAD_NAND_ALE__RAWNAND_ALE			0x01a0 0x042c 0x0000 0 0
+#define MX6UL_PAD_NAND_ALE__USDHC2_RESET_B		0x01a0 0x042c 0x0000 1 0
+#define MX6UL_PAD_NAND_ALE__QSPI_A_DQS			0x01a0 0x042c 0x0000 2 0
+#define MX6UL_PAD_NAND_ALE__PWM3_OUT			0x01a0 0x042c 0x0000 3 0
+#define MX6UL_PAD_NAND_ALE__EIM_ADDR17			0x01a0 0x042c 0x0000 4 0
+#define MX6UL_PAD_NAND_ALE__GPIO4_IO10			0x01a0 0x042c 0x0000 5 0
+#define MX6UL_PAD_NAND_ALE__ECSPI3_SS1			0x01a0 0x042c 0x0000 8 0
+#define MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B		0x01a4 0x0430 0x0000 0 0
+#define MX6UL_PAD_NAND_WP_B__USDHC1_RESET_B		0x01a4 0x0430 0x0000 1 0
+#define MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK		0x01a4 0x0430 0x0000 2 0
+#define MX6UL_PAD_NAND_WP_B__PWM4_OUT			0x01a4 0x0430 0x0000 3 0
+#define MX6UL_PAD_NAND_WP_B__EIM_BCLK			0x01a4 0x0430 0x0000 4 0
+#define MX6UL_PAD_NAND_WP_B__GPIO4_IO11			0x01a4 0x0430 0x0000 5 0
+#define MX6UL_PAD_NAND_WP_B__ECSPI3_RDY			0x01a4 0x0430 0x0000 8 0
+#define MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B		0x01a8 0x0434 0x0000 0 0
+#define MX6UL_PAD_NAND_READY_B__USDHC1_DATA4		0x01a8 0x0434 0x0000 1 0
+#define MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00		0x01a8 0x0434 0x0000 2 0
+#define MX6UL_PAD_NAND_READY_B__ECSPI3_SS0		0x01a8 0x0434 0x0560 3 1
+#define MX6UL_PAD_NAND_READY_B__EIM_CS1_B		0x01a8 0x0434 0x0000 4 0
+#define MX6UL_PAD_NAND_READY_B__GPIO4_IO12		0x01a8 0x0434 0x0000 5 0
+#define MX6UL_PAD_NAND_READY_B__UART3_DCE_TX		0x01a8 0x0434 0x0000 8 0
+#define MX6UL_PAD_NAND_READY_B__UART3_DTE_RX		0x01a8 0x0434 0x0634 8 2
+#define MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B		0x01ac 0x0438 0x0000 0 0
+#define MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5		0x01ac 0x0438 0x0000 1 0
+#define MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01		0x01ac 0x0438 0x0000 2 0
+#define MX6UL_PAD_NAND_CE0_B__ECSPI3_SCLK		0x01ac 0x0438 0x0554 3 1
+#define MX6UL_PAD_NAND_CE0_B__EIM_DTACK_B		0x01ac 0x0438 0x0000 4 0
+#define MX6UL_PAD_NAND_CE0_B__GPIO4_IO13		0x01ac 0x0438 0x0000 5 0
+#define MX6UL_PAD_NAND_CE0_B__UART3_DCE_RX		0x01ac 0x0438 0x0634 8 3
+#define MX6UL_PAD_NAND_CE0_B__UART3_DTE_TX		0x01ac 0x0438 0x0000 8 0
+#define MX6UL_PAD_NAND_CE1_B__RAWNAND_CE1_B		0x01b0 0x043c 0x0000 0 0
+#define MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6		0x01b0 0x043c 0x0000 1 0
+#define MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02		0x01b0 0x043c 0x0000 2 0
+#define MX6UL_PAD_NAND_CE1_B__ECSPI3_MOSI		0x01b0 0x043c 0x055c 3 1
+#define MX6UL_PAD_NAND_CE1_B__EIM_ADDR18		0x01b0 0x043c 0x0000 4 0
+#define MX6UL_PAD_NAND_CE1_B__GPIO4_IO14		0x01b0 0x043c 0x0000 5 0
+#define MX6UL_PAD_NAND_CE1_B__UART3_DCE_CTS		0x01b0 0x043c 0x0000 8 0
+#define MX6UL_PAD_NAND_CE1_B__UART3_DTE_RTS		0x01b0 0x043c 0x0630 8 2
+#define MX6UL_PAD_NAND_CLE__RAWNAND_CLE			0x01b4 0x0440 0x0000 0 0
+#define MX6UL_PAD_NAND_CLE__USDHC1_DATA7		0x01b4 0x0440 0x0000 1 0
+#define MX6UL_PAD_NAND_CLE__QSPI_A_DATA03		0x01b4 0x0440 0x0000 2 0
+#define MX6UL_PAD_NAND_CLE__ECSPI3_MISO			0x01b4 0x0440 0x0558 3 1
+#define MX6UL_PAD_NAND_CLE__EIM_ADDR16			0x01b4 0x0440 0x0000 4 0
+#define MX6UL_PAD_NAND_CLE__GPIO4_IO15			0x01b4 0x0440 0x0000 5 0
+#define MX6UL_PAD_NAND_CLE__UART3_DCE_RTS		0x01b4 0x0440 0x0630 8 3
+#define MX6UL_PAD_NAND_CLE__UART3_DTE_CTS		0x01b4 0x0440 0x0000 8 0
+#define MX6UL_PAD_NAND_DQS__RAWNAND_DQS			0x01b8 0x0444 0x0000 0 0
+#define MX6UL_PAD_NAND_DQS__CSI_FIELD			0x01b8 0x0444 0x0530 1 1
+#define MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B		0x01b8 0x0444 0x0000 2 0
+#define MX6UL_PAD_NAND_DQS__PWM5_OUT			0x01b8 0x0444 0x0000 3 0
+#define MX6UL_PAD_NAND_DQS__EIM_WAIT			0x01b8 0x0444 0x0000 4 0
+#define MX6UL_PAD_NAND_DQS__GPIO4_IO16			0x01b8 0x0444 0x0000 5 0
+#define MX6UL_PAD_NAND_DQS__SDMA_EXT_EVENT01		0x01b8 0x0444 0x0614 6 1
+#define MX6UL_PAD_NAND_DQS__SPDIF_EXT_CLK		0x01b8 0x0444 0x061c 8 1
+#define MX6UL_PAD_SD1_CMD__USDHC1_CMD			0x01bc 0x0448 0x0000 0 0
+#define MX6UL_PAD_SD1_CMD__GPT2_COMPARE1		0x01bc 0x0448 0x0000 1 0
+#define MX6UL_PAD_SD1_CMD__SAI2_RX_SYNC			0x01bc 0x0448 0x0000 2 0
+#define MX6UL_PAD_SD1_CMD__SPDIF_OUT			0x01bc 0x0448 0x0000 3 0
+#define MX6UL_PAD_SD1_CMD__EIM_ADDR19			0x01bc 0x0448 0x0000 4 0
+#define MX6UL_PAD_SD1_CMD__GPIO2_IO16			0x01bc 0x0448 0x0000 5 0
+#define MX6UL_PAD_SD1_CMD__SDMA_EXT_EVENT00		0x01bc 0x0448 0x0610 6 2
+#define MX6UL_PAD_SD1_CMD__USB_OTG1_PWR			0x01bc 0x0448 0x0000 8 0
+#define MX6UL_PAD_SD1_CLK__USDHC1_CLK			0x01c0 0x044c 0x0000 0 0
+#define MX6UL_PAD_SD1_CLK__GPT2_COMPARE2		0x01c0 0x044c 0x0000 1 0
+#define MX6UL_PAD_SD1_CLK__SAI2_MCLK			0x01c0 0x044c 0x05f0 2 1
+#define MX6UL_PAD_SD1_CLK__SPDIF_IN			0x01c0 0x044c 0x0618 3 3
+#define MX6UL_PAD_SD1_CLK__EIM_ADDR20			0x01c0 0x044c 0x0000 4 0
+#define MX6UL_PAD_SD1_CLK__GPIO2_IO17			0x01c0 0x044c 0x0000 5 0
+#define MX6UL_PAD_SD1_CLK__USB_OTG1_OC			0x01c0 0x044c 0x0664 8 2
+#define MX6UL_PAD_SD1_DATA0__USDHC1_DATA0		0x01c4 0x0450 0x0000 0 0
+#define MX6UL_PAD_SD1_DATA0__GPT2_COMPARE3		0x01c4 0x0450 0x0000 1 0
+#define MX6UL_PAD_SD1_DATA0__SAI2_TX_SYNC		0x01c4 0x0450 0x05fc 2 1
+#define MX6UL_PAD_SD1_DATA0__FLEXCAN1_TX		0x01c4 0x0450 0x0000 3 0
+#define MX6UL_PAD_SD1_DATA0__EIM_ADDR21			0x01c4 0x0450 0x0000 4 0
+#define MX6UL_PAD_SD1_DATA0__GPIO2_IO18			0x01c4 0x0450 0x0000 5 0
+#define MX6UL_PAD_SD1_DATA0__ANATOP_OTG1_ID		0x01c4 0x0450 0x04b8 8 2
+#define MX6UL_PAD_SD1_DATA1__USDHC1_DATA1		0x01c8 0x0454 0x0000 0 0
+#define MX6UL_PAD_SD1_DATA1__GPT2_CLK			0x01c8 0x0454 0x05a0 1 1
+#define MX6UL_PAD_SD1_DATA1__SAI2_TX_BCLK		0x01c8 0x0454 0x05f8 2 1
+#define MX6UL_PAD_SD1_DATA1__FLEXCAN1_RX		0x01c8 0x0454 0x0584 3 3
+#define MX6UL_PAD_SD1_DATA1__EIM_ADDR22			0x01c8 0x0454 0x0000 4 0
+#define MX6UL_PAD_SD1_DATA1__GPIO2_IO19			0x01c8 0x0454 0x0000 5 0
+#define MX6UL_PAD_SD1_DATA1__USB_OTG2_PWR		0x01c8 0x0454 0x0000 8 0
+#define MX6UL_PAD_SD1_DATA2__USDHC1_DATA2		0x01cc 0x0458 0x0000 0 0
+#define MX6UL_PAD_SD1_DATA2__GPT2_CAPTURE1		0x01cc 0x0458 0x0598 1 1
+#define MX6UL_PAD_SD1_DATA2__SAI2_RX_DATA		0x01cc 0x0458 0x05f4 2 1
+#define MX6UL_PAD_SD1_DATA2__FLEXCAN2_TX		0x01cc 0x0458 0x0000 3 0
+#define MX6UL_PAD_SD1_DATA2__EIM_ADDR23			0x01cc 0x0458 0x0000 4 0
+#define MX6UL_PAD_SD1_DATA2__GPIO2_IO20			0x01cc 0x0458 0x0000 5 0
+#define MX6UL_PAD_SD1_DATA2__CCM_CLKO1			0x01cc 0x0458 0x0000 6 0
+#define MX6UL_PAD_SD1_DATA2__USB_OTG2_OC		0x01cc 0x0458 0x0660 8 2
+#define MX6UL_PAD_SD1_DATA3__USDHC1_DATA3		0x01d0 0x045c 0x0000 0 0
+#define MX6UL_PAD_SD1_DATA3__GPT2_CAPTURE2		0x01d0 0x045c 0x059c 1 1
+#define MX6UL_PAD_SD1_DATA3__SAI2_TX_DATA		0x01d0 0x045c 0x0000 2 0
+#define MX6UL_PAD_SD1_DATA3__FLEXCAN2_RX		0x01d0 0x045c 0x0588 3 3
+#define MX6UL_PAD_SD1_DATA3__EIM_ADDR24			0x01d0 0x045c 0x0000 4 0
+#define MX6UL_PAD_SD1_DATA3__GPIO2_IO21			0x01d0 0x045c 0x0000 5 0
+#define MX6UL_PAD_SD1_DATA3__CCM_CLKO2			0x01d0 0x045c 0x0000 6 0
+#define MX6UL_PAD_SD1_DATA3__ANATOP_OTG2_ID		0x01d0 0x045c 0x04bc 8 2
+#define MX6UL_PAD_CSI_MCLK__CSI_MCLK			0x01d4 0x0460 0x0000 0 0
+#define MX6UL_PAD_CSI_MCLK__USDHC2_CD_B			0x01d4 0x0460 0x0674 1 0
+#define MX6UL_PAD_CSI_MCLK__RAWNAND_CE2_B		0x01d4 0x0460 0x0000 2 0
+#define MX6UL_PAD_CSI_MCLK__I2C1_SDA			0x01d4 0x0460 0x05a8 3 0
+#define MX6UL_PAD_CSI_MCLK__EIM_CS0_B			0x01d4 0x0460 0x0000 4 0
+#define MX6UL_PAD_CSI_MCLK__GPIO4_IO17			0x01d4 0x0460 0x0000 5 0
+#define MX6UL_PAD_CSI_MCLK__SNVS_HP_VIO_5_CTL		0x01d4 0x0460 0x0000 6 0
+#define MX6UL_PAD_CSI_MCLK__UART6_DCE_TX		0x01d4 0x0460 0x0000 8 0
+#define MX6UL_PAD_CSI_MCLK__UART6_DTE_RX		0x01d4 0x0460 0x064c 8 0
+#define MX6UL_PAD_CSI_PIXCLK__CSI_PIXCLK		0x01d8 0x0464 0x0528 0 1
+#define MX6UL_PAD_CSI_PIXCLK__USDHC2_WP			0x01d8 0x0464 0x069c 1 2
+#define MX6UL_PAD_CSI_PIXCLK__RAWNAND_CE3_B		0x01d8 0x0464 0x0000 2 0
+#define MX6UL_PAD_CSI_PIXCLK__I2C1_SCL			0x01d8 0x0464 0x05a4 3 2
+#define MX6UL_PAD_CSI_PIXCLK__EIM_OE			0x01d8 0x0464 0x0000 4 0
+#define MX6UL_PAD_CSI_PIXCLK__GPIO4_IO18		0x01d8 0x0464 0x0000 5 0
+#define MX6UL_PAD_CSI_PIXCLK__SNVS_HP_VIO_5		0x01d8 0x0464 0x0000 6 0
+#define MX6UL_PAD_CSI_PIXCLK__UART6_DCE_RX		0x01d8 0x0464 0x064c 8 3
+#define MX6UL_PAD_CSI_PIXCLK__UART6_DTE_TX		0x01d8 0x0464 0x0000 8 0
+#define MX6UL_PAD_CSI_VSYNC__CSI_VSYNC			0x01dc 0x0468 0x052c 0 0
+#define MX6UL_PAD_CSI_VSYNC__USDHC2_CLK			0x01dc 0x0468 0x0670 1 0
+#define MX6UL_PAD_CSI_VSYNC__SIM1_PORT1_CLK		0x01dc 0x0468 0x0000 2 0
+#define MX6UL_PAD_CSI_VSYNC__I2C2_SDA			0x01dc 0x0468 0x05b0 3 0
+#define MX6UL_PAD_CSI_VSYNC__EIM_RW			0x01dc 0x0468 0x0000 4 0
+#define MX6UL_PAD_CSI_VSYNC__GPIO4_IO19			0x01dc 0x0468 0x0000 5 0
+#define MX6UL_PAD_CSI_VSYNC__PWM7_OUT			0x01dc 0x0468 0x0000 6 0
+#define MX6UL_PAD_CSI_VSYNC__UART6_DCE_RTS		0x01dc 0x0468 0x0648 8 0
+#define MX6UL_PAD_CSI_VSYNC__UART6_DTE_CTS		0x01dc 0x0468 0x0000 8 0
+#define MX6UL_PAD_CSI_HSYNC__CSI_HSYNC			0x01e0 0x046c 0x0524 0 0
+#define MX6UL_PAD_CSI_HSYNC__USDHC2_CMD			0x01e0 0x046c 0x0678 1 0
+#define MX6UL_PAD_CSI_HSYNC__SIM1_PORT1_PD		0x01e0 0x046c 0x0000 2 0
+#define MX6UL_PAD_CSI_HSYNC__I2C2_SCL			0x01e0 0x046c 0x05ac 3 0
+#define MX6UL_PAD_CSI_HSYNC__EIM_LBA_B			0x01e0 0x046c 0x0000 4 0
+#define MX6UL_PAD_CSI_VSYNC__GPIO4_IO20			0x01e0 0x046c 0x0000 5 0
+#define MX6UL_PAD_CSI_HSYNC__PWM8_OUT			0x01e0 0x046c 0x0000 6 0
+#define MX6UL_PAD_CSI_HSYNC__UART6_DCE_CTS		0x01e0 0x046c 0x0000 8 0
+#define MX6UL_PAD_CSI_HSYNC__UART6_DTE_RTS		0x01e0 0x046c 0x0648 8 1
+#define MX6UL_PAD_CSI_DATA00__CSI_DATA02		0x01e4 0x0470 0x04c4 0 0
+#define MX6UL_PAD_CSI_DATA00__USDHC2_DATA0		0x01e4 0x0470 0x067c 1 0
+#define MX6UL_PAD_CSI_DATA00__SIM1_PORT1_RST_B		0x01e4 0x0470 0x0000 2 0
+#define MX6UL_PAD_CSI_DATA00__ECSPI2_SCLK		0x01e4 0x0470 0x0544 3 0
+#define MX6UL_PAD_CSI_DATA00__EIM_AD00			0x01e4 0x0470 0x0000 4 0
+#define MX6UL_PAD_CSI_DATA00__GPIO4_IO21		0x01e4 0x0470 0x0000 5 0
+#define MX6UL_PAD_CSI_DATA00__SRC_INT_BOOT		0x01e4 0x0470 0x0000 6 0
+#define MX6UL_PAD_CSI_DATA00__UART5_DCE_TX		0x01e4 0x0470 0x0000 8 0
+#define MX6UL_PAD_CSI_DATA00__UART5_DTE_RX		0x01e4 0x0470 0x0644 8 0
+#define MX6UL_PAD_CSI_DATA01__CSI_DATA03		0x01e8 0x0474 0x04c8 0 0
+#define MX6UL_PAD_CSI_DATA01__USDHC2_DATA1		0x01e8 0x0474 0x0680 1 0
+#define MX6UL_PAD_CSI_DATA01__SIM1_PORT1_SVEN		0x01e8 0x0474 0x0000 2 0
+#define MX6UL_PAD_CSI_DATA01__ECSPI2_SS0		0x01e8 0x0474 0x0550 3 0
+#define MX6UL_PAD_CSI_DATA01__EIM_AD01			0x01e8 0x0474 0x0000 4 0
+#define MX6UL_PAD_CSI_DATA01__GPIO4_IO22		0x01e8 0x0474 0x0000 5 0
+#define MX6UL_PAD_CSI_DATA01__SAI1_MCLK			0x01e8 0x0474 0x05e0 6 0
+#define MX6UL_PAD_CSI_DATA01__UART5_DCE_RX		0x01e8 0x0474 0x0644 8 1
+#define MX6UL_PAD_CSI_DATA01__UART5_DTE_TX		0x01e8 0x0474 0x0000 8 0
+#define MX6UL_PAD_CSI_DATA02__CSI_DATA04		0x01ec 0x0478 0x04d8 0 1
+#define MX6UL_PAD_CSI_DATA02__USDHC2_DATA2		0x01ec 0x0478 0x0684 1 2
+#define MX6UL_PAD_CSI_DATA02__SIM1_PORT1_TRXD		0x01ec 0x0478 0x0000 2 0
+#define MX6UL_PAD_CSI_DATA02__ECSPI2_MOSI		0x01ec 0x0478 0x054c 3 1
+#define MX6UL_PAD_CSI_DATA02__EIM_AD02			0x01ec 0x0478 0x0000 4 0
+#define MX6UL_PAD_CSI_DATA02__GPIO4_IO23		0x01ec 0x0478 0x0000 5 0
+#define MX6UL_PAD_CSI_DATA02__SAI1_RX_SYNC		0x01ec 0x0478 0x0000 6 0
+#define MX6UL_PAD_CSI_DATA02__UART5_DCE_RTS		0x01ec 0x0478 0x0640 8 5
+#define MX6UL_PAD_CSI_DATA02__UART5_DTE_CTS		0x01ec 0x0478 0x0000 8 0
+#define MX6UL_PAD_CSI_DATA03__CSI_DATA05		0x01f0 0x047c 0x04cc 0 0
+#define MX6UL_PAD_CSI_DATA03__USDHC2_DATA3		0x01f0 0x047c 0x0688 1 0
+#define MX6UL_PAD_CSI_DATA03__SIM2_PORT1_PD		0x01f0 0x047c 0x0000 2 0
+#define MX6UL_PAD_CSI_DATA03__ECSPI2_MISO		0x01f0 0x047c 0x0548 3 0
+#define MX6UL_PAD_CSI_DATA03__EIM_AD03			0x01f0 0x047c 0x0000 4 0
+#define MX6UL_PAD_CSI_DATA03__GPIO4_IO24		0x01f0 0x047c 0x0000 5 0
+#define MX6UL_PAD_CSI_DATA03__SAI1_RX_BCLK		0x01f0 0x047c 0x0000 6 0
+#define MX6UL_PAD_CSI_DATA03__UART5_DCE_CTS		0x01f0 0x047c 0x0000 8 0
+#define MX6UL_PAD_CSI_DATA03__UART5_DTE_RTS		0x01f0 0x047c 0x0640 8 0
+#define MX6UL_PAD_CSI_DATA04__CSI_DATA06		0x01f4 0x0480 0x04dc 0 1
+#define MX6UL_PAD_CSI_DATA04__USDHC2_DATA4		0x01f4 0x0480 0x068c 1 2
+#define MX6UL_PAD_CSI_DATA04__SIM2_PORT1_CLK		0x01f4 0x0480 0x0000 2 0
+#define MX6UL_PAD_CSI_DATA04__ECSPI1_SCLK		0x01f4 0x0480 0x0534 3 1
+#define MX6UL_PAD_CSI_DATA04__EIM_AD04			0x01f4 0x0480 0x0000 4 0
+#define MX6UL_PAD_CSI_DATA04__GPIO4_IO25		0x01f4 0x0480 0x0000 5 0
+#define MX6UL_PAD_CSI_DATA04__SAI1_TX_SYNC		0x01f4 0x0480 0x05ec 6 1
+#define MX6UL_PAD_CSI_DATA04__USDHC1_WP			0x01f4 0x0480 0x066c 8 2
+#define MX6UL_PAD_CSI_DATA05__CSI_DATA07		0x01f8 0x0484 0x04e0 0 1
+#define MX6UL_PAD_CSI_DATA05__USDHC2_DATA5		0x01f8 0x0484 0x0690 1 2
+#define MX6UL_PAD_CSI_DATA05__SIM2_PORT1_RST_B		0x01f8 0x0484 0x0000 2 0
+#define MX6UL_PAD_CSI_DATA05__ECSPI1_SS0		0x01f8 0x0484 0x0540 3 1
+#define MX6UL_PAD_CSI_DATA05__EIM_AD05			0x01f8 0x0484 0x0000 4 0
+#define MX6UL_PAD_CSI_DATA05__GPIO4_IO26		0x01f8 0x0484 0x0000 5 0
+#define MX6UL_PAD_CSI_DATA05__SAI1_TX_BCLK		0x01f8 0x0484 0x05e8 6 1
+#define MX6UL_PAD_CSI_DATA05__USDHC1_CD_B		0x01f8 0x0484 0x0668 8 2
+#define MX6UL_PAD_CSI_DATA06__CSI_DATA08		0x01fc 0x0488 0x04e4 0 1
+#define MX6UL_PAD_CSI_DATA06__USDHC2_DATA6		0x01fc 0x0488 0x0694 1 2
+#define MX6UL_PAD_CSI_DATA06__SIM2_PORT1_SVEN		0x01fc 0x0488 0x0000 2 0
+#define MX6UL_PAD_CSI_DATA06__ECSPI1_MOSI		0x01fc 0x0488 0x053c 3 1
+#define MX6UL_PAD_CSI_DATA06__EIM_AD06			0x01fc 0x0488 0x0000 4 0
+#define MX6UL_PAD_CSI_DATA06__GPIO4_IO27		0x01fc 0x0488 0x0000 5 0
+#define MX6UL_PAD_CSI_DATA06__SAI1_RX_DATA		0x01fc 0x0488 0x05e4 6 1
+#define MX6UL_PAD_CSI_DATA06__USDHC1_RESET_B		0x01fc 0x0488 0x0000 8 0
+#define MX6UL_PAD_CSI_DATA07__CSI_DATA09		0x0200 0x048c 0x04e8 0 1
+#define MX6UL_PAD_CSI_DATA07__USDHC2_DATA7		0x0200 0x048c 0x0698 1 2
+#define MX6UL_PAD_CSI_DATA07__SIM2_PORT1_TRXD		0x0200 0x048c 0x0000 2 0
+#define MX6UL_PAD_CSI_DATA07__ECSPI1_MISO		0x0200 0x048c 0x0538 3 1
+#define MX6UL_PAD_CSI_DATA07__EIM_AD07			0x0200 0x048c 0x0000 4 0
+#define MX6UL_PAD_CSI_DATA07__GPIO4_IO28		0x0200 0x048c 0x0000 5 0
+#define MX6UL_PAD_CSI_DATA07__SAI1_TX_DATA		0x0200 0x048c 0x0000 6 0
+#define MX6UL_PAD_CSI_DATA07__USDHC1_VSELECT		0x0200 0x048c 0x0000 8 0
+
+#endif /* __DTS_IMX6UL_PINFUNC_H */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/imx6ull-pinfunc-snvs.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/imx6ull-pinfunc-snvs.h
new file mode 100644
index 0000000000000000000000000000000000000000..f6fb6783c1933154049768297372832f68586a04
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/imx6ull-pinfunc-snvs.h
@@ -0,0 +1,26 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright (C) 2017 NXP
+ */
+
+#ifndef __DTS_IMX6ULL_PINFUNC_SNVS_H
+#define __DTS_IMX6ULL_PINFUNC_SNVS_H
+/*
+ * The pin function ID is a tuple of
+ * <mux_reg conf_reg input_reg mux_mode input_val>
+ */
+#define MX6ULL_PAD_BOOT_MODE0__GPIO5_IO10                          0x0000 0x0044 0x0000 0x5 0x0
+#define MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11                          0x0004 0x0048 0x0000 0x5 0x0
+#define MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00                        0x0008 0x004C 0x0000 0x5 0x0
+#define MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01                        0x000C 0x0050 0x0000 0x5 0x0
+#define MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02                        0x0010 0x0054 0x0000 0x5 0x0
+#define MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03                        0x0014 0x0058 0x0000 0x5 0x0
+#define MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04                        0x0018 0x005C 0x0000 0x5 0x0
+#define MX6ULL_PAD_SNVS_TAMPER5__GPIO5_IO05                        0x001C 0x0060 0x0000 0x5 0x0
+#define MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06                        0x0020 0x0064 0x0000 0x5 0x0
+#define MX6ULL_PAD_SNVS_TAMPER7__GPIO5_IO07                        0x0024 0x0068 0x0000 0x5 0x0
+#define MX6ULL_PAD_SNVS_TAMPER8__GPIO5_IO08                        0x0028 0x006C 0x0000 0x5 0x0
+#define MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09                        0x002C 0x0070 0x0000 0x5 0x0
+
+#endif /* __DTS_IMX6ULL_PINFUNC_SNVS_H */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/imx6ull-pinfunc.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/imx6ull-pinfunc.h
new file mode 100644
index 0000000000000000000000000000000000000000..014e00243cbd37058aee5abb6c7c5a3f1aceae6f
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/imx6ull-pinfunc.h
@@ -0,0 +1,104 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __DTS_IMX6ULL_PINFUNC_H
+#define __DTS_IMX6ULL_PINFUNC_H
+
+#include "imx6ul-pinfunc.h"
+/*
+ * The pin function ID is a tuple of
+ * <mux_reg conf_reg input_reg mux_mode input_val>
+ */
+
+#define MX6ULL_PAD_UART1_TX_DATA__UART5_DTE_RX                    0x0084 0x0310 0x0644 0x9 0x4
+#define MX6ULL_PAD_UART1_RX_DATA__UART5_DCE_RX                    0x0088 0x0314 0x0644 0x9 0x5
+#define MX6ULL_PAD_UART1_CTS_B__UART5_DCE_RTS                     0x008C 0x0318 0x0640 0x9 0x3
+#define MX6ULL_PAD_UART1_RTS_B__UART5_DTE_RTS                     0x0090 0x031C 0x0640 0x9 0x4
+
+#define MX6ULL_PAD_UART5_TX_DATA__UART5_DTE_RX                    0x00BC 0x0348 0x0644 0x0 0x6
+#define MX6ULL_PAD_UART5_RX_DATA__UART5_DCE_RX                    0x00C0 0x034C 0x0644 0x0 0x7
+#define MX6ULL_PAD_ENET1_RX_EN__UART5_DCE_RTS                     0x00CC 0x0358 0x0640 0x1 0x5
+#define MX6ULL_PAD_ENET1_TX_DATA0__UART5_DTE_RTS                  0x00D0 0x035C 0x0640 0x1 0x6
+
+#define MX6ULL_PAD_ENET1_RX_DATA0__EPDC_SDCE04                    0x00C4 0x0350 0x0000 0x9 0x0
+#define MX6ULL_PAD_ENET1_RX_DATA1__EPDC_SDCE05                    0x00C8 0x0354 0x0000 0x9 0x0
+#define MX6ULL_PAD_ENET1_RX_EN__EPDC_SDCE06                       0x00CC 0x0358 0x0000 0x9 0x0
+#define MX6ULL_PAD_ENET1_TX_DATA0__EPDC_SDCE07                    0x00D0 0x035C 0x0000 0x9 0x0
+#define MX6ULL_PAD_ENET1_TX_DATA1__EPDC_SDCE08                    0x00D4 0x0360 0x0000 0x9 0x0
+#define MX6ULL_PAD_ENET1_TX_EN__EPDC_SDCE09                       0x00D8 0x0364 0x0000 0x9 0x0
+#define MX6ULL_PAD_ENET1_TX_CLK__EPDC_SDOED                       0x00DC 0x0368 0x0000 0x9 0x0
+#define MX6ULL_PAD_ENET1_RX_ER__EPDC_SDOEZ                        0x00E0 0x036C 0x0000 0x9 0x0
+
+#define MX6ULL_PAD_ENET2_RX_DATA0__EPDC_SDDO08                    0x00E4 0x0370 0x0000 0x9 0x0
+#define MX6ULL_PAD_ENET2_RX_DATA1__EPDC_SDDO09                    0x00E8 0x0374 0x0000 0x9 0x0
+#define MX6ULL_PAD_ENET2_RX_EN__EPDC_SDDO10                       0x00EC 0x0378 0x0000 0x9 0x0
+#define MX6ULL_PAD_ENET2_TX_DATA0__EPDC_SDDO11                    0x00F0 0x037C 0x0000 0x9 0x0
+#define MX6ULL_PAD_ENET2_TX_DATA1__EPDC_SDDO12                    0x00F4 0x0380 0x0000 0x9 0x0
+#define MX6ULL_PAD_ENET2_TX_EN__EPDC_SDDO13                       0x00F8 0x0384 0x0000 0x9 0x0
+#define MX6ULL_PAD_ENET2_TX_CLK__EPDC_SDDO14                      0x00FC 0x0388 0x0000 0x9 0x0
+#define MX6ULL_PAD_ENET2_RX_ER__EPDC_SDDO15                       0x0100 0x038C 0x0000 0x9 0x0
+#define MX6ULL_PAD_LCD_CLK__EPDC_SDCLK                            0x0104 0x0390 0x0000 0x9 0x0
+#define MX6ULL_PAD_LCD_ENABLE__EPDC_SDLE                          0x0108 0x0394 0x0000 0x9 0x0
+#define MX6ULL_PAD_LCD_HSYNC__EPDC_SDOE                           0x010C 0x0398 0x0000 0x9 0x0
+#define MX6ULL_PAD_LCD_VSYNC__EPDC_SDCE0                          0x0110 0x039C 0x0000 0x9 0x0
+#define MX6ULL_PAD_LCD_RESET__EPDC_GDOE                           0x0114 0x03A0 0x0000 0x9 0x0
+#define MX6ULL_PAD_LCD_DATA00__EPDC_SDDO00                        0x0118 0x03A4 0x0000 0x9 0x0
+#define MX6ULL_PAD_LCD_DATA01__EPDC_SDDO01                        0x011C 0x03A8 0x0000 0x9 0x0
+#define MX6ULL_PAD_LCD_DATA02__EPDC_SDDO02                        0x0120 0x03AC 0x0000 0x9 0x0
+#define MX6ULL_PAD_LCD_DATA03__EPDC_SDDO03                        0x0124 0x03B0 0x0000 0x9 0x0
+#define MX6ULL_PAD_LCD_DATA04__EPDC_SDDO04                        0x0128 0x03B4 0x0000 0x9 0x0
+#define MX6ULL_PAD_LCD_DATA05__EPDC_SDDO05                        0x012C 0x03B8 0x0000 0x9 0x0
+#define MX6ULL_PAD_LCD_DATA06__EPDC_SDDO06                        0x0130 0x03BC 0x0000 0x9 0x0
+#define MX6ULL_PAD_LCD_DATA07__EPDC_SDDO07                        0x0134 0x03C0 0x0000 0x9 0x0
+#define MX6ULL_PAD_LCD_DATA14__EPDC_SDSHR                         0x0150 0x03DC 0x0000 0x9 0x0
+#define MX6ULL_PAD_LCD_DATA15__EPDC_GDRL                          0x0154 0x03E0 0x0000 0x9 0x0
+#define MX6ULL_PAD_LCD_DATA16__EPDC_GDCLK                         0x0158 0x03E4 0x0000 0x9 0x0
+#define MX6ULL_PAD_LCD_DATA17__EPDC_GDSP                          0x015C 0x03E8 0x0000 0x9 0x0
+#define MX6ULL_PAD_LCD_DATA21__EPDC_SDCE1                         0x016C 0x03F8 0x0000 0x9 0x0
+#define MX6ULL_PAD_LCD_DATA22__EPDC_SDCE02                        0x0170 0x03FC 0x0000 0x9 0x0
+#define MX6ULL_PAD_LCD_DATA23__EPDC_SDCE03                        0x0174 0x0400 0x0000 0x9 0x0
+#define MX6ULL_PAD_CSI_MCLK__ESAI_TX3_RX2                         0x01D4 0x0460 0x0000 0x9 0x0
+#define MX6ULL_PAD_CSI_PIXCLK__ESAI_TX2_RX3                       0x01D8 0x0464 0x0000 0x9 0x0
+#define MX6ULL_PAD_CSI_VSYNC__ESAI_TX4_RX1                        0x01DC 0x0468 0x0000 0x9 0x0
+#define MX6ULL_PAD_CSI_HSYNC__ESAI_TX1                            0x01E0 0x046C 0x0000 0x9 0x0
+#define MX6ULL_PAD_CSI_DATA00__ESAI_TX_HF_CLK                     0x01E4 0x0470 0x0000 0x9 0x0
+#define MX6ULL_PAD_CSI_DATA01__ESAI_RX_HF_CLK                     0x01E8 0x0474 0x0000 0x9 0x0
+#define MX6ULL_PAD_CSI_DATA02__ESAI_RX_FS                         0x01EC 0x0478 0x0000 0x9 0x0
+#define MX6ULL_PAD_CSI_DATA03__ESAI_RX_CLK                        0x01F0 0x047C 0x0000 0x9 0x0
+#define MX6ULL_PAD_CSI_DATA04__ESAI_TX_FS                         0x01F4 0x0480 0x0000 0x9 0x0
+#define MX6ULL_PAD_CSI_DATA05__ESAI_TX_CLK                        0x01F8 0x0484 0x0000 0x9 0x0
+#define MX6ULL_PAD_CSI_DATA06__ESAI_TX5_RX0                       0x01FC 0x0488 0x0000 0x9 0x0
+#define MX6ULL_PAD_CSI_DATA07__ESAI_T0                            0x0200 0x048C 0x0000 0x9 0x0
+
+#define MX6UL_PAD_UART1_TX_DATA__UART5_DCE_TX                    0x0084 0x0310 0x0000 0x9 0x0
+#define MX6UL_PAD_UART1_TX_DATA__UART5_DTE_RX                    0x0084 0x0310 0x0644 0x9 0x4
+#define MX6UL_PAD_UART1_RX_DATA__UART5_DCE_RX                    0x0088 0x0314 0x0644 0x9 0x5
+#define MX6UL_PAD_UART1_RX_DATA__UART5_DTE_TX                    0x0088 0x0314 0x0000 0x9 0x0
+#define MX6UL_PAD_UART1_CTS_B__UART5_DCE_CTS                     0x008C 0x0318 0x0000 0x9 0x0
+#define MX6UL_PAD_UART1_CTS_B__UART5_DTE_RTS                     0x008C 0x0318 0x0640 0x9 0x3
+#define MX6UL_PAD_UART1_RTS_B__UART5_DCE_RTS                     0x0090 0x031C 0x0640 0x9 0x4
+#define MX6UL_PAD_UART1_RTS_B__UART5_DTE_CTS                     0x0090 0x031C 0x0000 0x9 0x0
+#define MX6UL_PAD_UART4_RX_DATA__EPDC_PWRCTRL01                  0x00B8 0x0344 0x0000 0x9 0x0
+#define MX6UL_PAD_UART5_TX_DATA__EPDC_PWRCTRL02                  0x00BC 0x0348 0x0000 0x9 0x0
+#define MX6UL_PAD_UART5_RX_DATA__EPDC_PWRCTRL03                  0x00C0 0x034C 0x0000 0x9 0x0
+
+/* Below pinfunc are different with i.MX6UL, so override them in here
+ * To avoid build warning, firstly undef them.
+ */
+#undef MX6UL_PAD_UART5_TX_DATA__UART5_DTE_RX
+#undef MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX
+#undef MX6UL_PAD_ENET1_RX_EN__UART5_DCE_RTS
+#undef MX6UL_PAD_ENET1_TX_DATA0__UART5_DTE_RTS
+#undef MX6UL_PAD_CSI_DATA02__UART5_DCE_RTS
+#define MX6UL_PAD_UART5_TX_DATA__UART5_DTE_RX                    0x00BC 0x0348 0x0644 0x0 0x6
+#define MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX                    0x00C0 0x034C 0x0644 0x0 0x7
+#define MX6UL_PAD_ENET1_RX_EN__UART5_DCE_RTS                     0x00CC 0x0358 0x0640 0x1 0x5
+#define MX6UL_PAD_ENET1_TX_DATA0__UART5_DTE_RTS                  0x00D0 0x035C 0x0640 0x1 0x6
+#define MX6UL_PAD_CSI_DATA02__UART5_DCE_RTS                      0x01EC 0x0478 0x0640 0x8 0x7
+
+#endif /* __DTS_IMX6ULL_PINFUNC_H */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/imx7d-pinfunc.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/imx7d-pinfunc.h
new file mode 100644
index 0000000000000000000000000000000000000000..aa9dbead4b8b9373569fa2c41b444a6c7b8ad916
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/imx7d-pinfunc.h
@@ -0,0 +1,1158 @@
+/*
+ * Copyright (C) 2014-2015 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __DTS_IMX7D_PINFUNC_H
+#define __DTS_IMX7D_PINFUNC_H
+
+/*
+ * The pin function ID is a tuple of
+ * <mux_reg conf_reg input_reg mux_mode input_val>
+ */
+
+#define MX7D_PAD_LPSR_GPIO1_IO00__GPIO1_IO0                       0x0000 0x0030 0x0000 0x0 0x0
+#define MX7D_PAD_LPSR_GPIO1_IO00__PWM4_OUT                        0x0000 0x0030 0x0000 0x1 0x0
+#define MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_ANY                  0x0000 0x0030 0x0000 0x2 0x0
+#define MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B                    0x0000 0x0030 0x0000 0x3 0x0
+#define MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG__RST_B_DEB           0x0000 0x0030 0x0000 0x4 0x0
+#define MX7D_PAD_LPSR_GPIO1_IO01__GPIO1_IO1                       0x0004 0x0034 0x0000 0x0 0x0
+#define MX7D_PAD_LPSR_GPIO1_IO01__PWM1_OUT                        0x0004 0x0034 0x0000 0x1 0x0
+#define MX7D_PAD_LPSR_GPIO1_IO01__CCM_ENET_REF_CLK3               0x0004 0x0034 0x0000 0x2 0x0
+#define MX7D_PAD_LPSR_GPIO1_IO01__SAI1_MCLK                       0x0004 0x0034 0x0000 0x3 0x0
+#define MX7D_PAD_LPSR_GPIO1_IO01__ANATOP_24M_OUT                  0x0004 0x0034 0x0000 0x4 0x0
+#define MX7D_PAD_LPSR_GPIO1_IO01__OBSERVE0_OUT                    0x0004 0x0034 0x0000 0x6 0x0
+#define MX7D_PAD_LPSR_GPIO1_IO02__GPIO1_IO2                       0x0008 0x0038 0x0000 0x0 0x0
+#define MX7D_PAD_LPSR_GPIO1_IO02__PWM2_OUT                        0x0008 0x0038 0x0000 0x1 0x0
+#define MX7D_PAD_LPSR_GPIO1_IO02__CCM_ENET_REF_CLK1               0x0008 0x0038 0x0564 0x2 0x3
+#define MX7D_PAD_LPSR_GPIO1_IO02__SAI2_MCLK                       0x0008 0x0038 0x0000 0x3 0x0
+#define MX7D_PAD_LPSR_GPIO1_IO02__CCM_CLKO1                       0x0008 0x0038 0x0000 0x5 0x0
+#define MX7D_PAD_LPSR_GPIO1_IO02__OBSERVE1_OUT                    0x0008 0x0038 0x0000 0x6 0x0
+#define MX7D_PAD_LPSR_GPIO1_IO02__USB_OTG1_ID                     0x0008 0x0038 0x0734 0x7 0x3
+#define MX7D_PAD_LPSR_GPIO1_IO03__GPIO1_IO3                       0x000C 0x003C 0x0000 0x0 0x0
+#define MX7D_PAD_LPSR_GPIO1_IO03__PWM3_OUT                        0x000C 0x003C 0x0000 0x1 0x0
+#define MX7D_PAD_LPSR_GPIO1_IO03__CCM_ENET_REF_CLK2               0x000C 0x003C 0x0570 0x2 0x3
+#define MX7D_PAD_LPSR_GPIO1_IO03__SAI3_MCLK                       0x000C 0x003C 0x0000 0x3 0x0
+#define MX7D_PAD_LPSR_GPIO1_IO03__CCM_CLKO2                       0x000C 0x003C 0x0000 0x5 0x0
+#define MX7D_PAD_LPSR_GPIO1_IO03__OBSERVE2_OUT                    0x000C 0x003C 0x0000 0x6 0x0
+#define MX7D_PAD_LPSR_GPIO1_IO03__USB_OTG2_ID                     0x000C 0x003C 0x0730 0x7 0x3
+#define MX7D_PAD_LPSR_GPIO1_IO04__GPIO1_IO4                       0x0010 0x0040 0x0000 0x0 0x0
+#define MX7D_PAD_LPSR_GPIO1_IO04__USB_OTG1_OC                     0x0010 0x0040 0x072C 0x1 0x1
+#define MX7D_PAD_LPSR_GPIO1_IO04__FLEXTIMER1_CH4                  0x0010 0x0040 0x0594 0x2 0x1
+#define MX7D_PAD_LPSR_GPIO1_IO04__UART5_DCE_CTS                   0x0010 0x0040 0x0000 0x3 0x0
+#define MX7D_PAD_LPSR_GPIO1_IO04__UART5_DTE_RTS                   0x0010 0x0040 0x0710 0x3 0x4
+#define MX7D_PAD_LPSR_GPIO1_IO04__I2C1_SCL                        0x0010 0x0040 0x05D4 0x4 0x2
+#define MX7D_PAD_LPSR_GPIO1_IO04__OBSERVE3_OUT                    0x0010 0x0040 0x0000 0x6 0x0
+#define MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5                       0x0014 0x0044 0x0000 0x0 0x0
+#define MX7D_PAD_LPSR_GPIO1_IO05__USB_OTG1_PWR                    0x0014 0x0044 0x0000 0x1 0x0
+#define MX7D_PAD_LPSR_GPIO1_IO05__FLEXTIMER1_CH5                  0x0014 0x0044 0x0598 0x2 0x1
+#define MX7D_PAD_LPSR_GPIO1_IO05__UART5_DCE_RTS                   0x0014 0x0044 0x0710 0x3 0x5
+#define MX7D_PAD_LPSR_GPIO1_IO05__UART5_DTE_CTS                   0x0014 0x0044 0x0000 0x3 0x0
+#define MX7D_PAD_LPSR_GPIO1_IO05__I2C1_SDA                        0x0014 0x0044 0x05D8 0x4 0x2
+#define MX7D_PAD_LPSR_GPIO1_IO05__OBSERVE4_OUT                    0x0014 0x0044 0x0000 0x6 0x0
+#define MX7D_PAD_LPSR_GPIO1_IO06__GPIO1_IO6                       0x0018 0x0048 0x0000 0x0 0x0
+#define MX7D_PAD_LPSR_GPIO1_IO06__USB_OTG2_OC                     0x0018 0x0048 0x0728 0x1 0x1
+#define MX7D_PAD_LPSR_GPIO1_IO06__FLEXTIMER1_CH6                  0x0018 0x0048 0x059C 0x2 0x1
+#define MX7D_PAD_LPSR_GPIO1_IO06__UART5_DCE_RX                    0x0018 0x0048 0x0714 0x3 0x4
+#define MX7D_PAD_LPSR_GPIO1_IO06__UART5_DTE_TX                    0x0018 0x0048 0x0000 0x3 0x0
+#define MX7D_PAD_LPSR_GPIO1_IO06__I2C2_SCL                        0x0018 0x0048 0x05DC 0x4 0x2
+#define MX7D_PAD_LPSR_GPIO1_IO06__CCM_WAIT                        0x0018 0x0048 0x0000 0x5 0x0
+#define MX7D_PAD_LPSR_GPIO1_IO06__KPP_ROW4                        0x0018 0x0048 0x0624 0x6 0x1
+#define MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7                       0x001C 0x004C 0x0000 0x0 0x0
+#define MX7D_PAD_LPSR_GPIO1_IO07__USB_OTG2_PWR                    0x001C 0x004C 0x0000 0x1 0x0
+#define MX7D_PAD_LPSR_GPIO1_IO07__FLEXTIMER1_CH7                  0x001C 0x004C 0x05A0 0x2 0x1
+#define MX7D_PAD_LPSR_GPIO1_IO07__UART5_DCE_TX                    0x001C 0x004C 0x0000 0x3 0x0
+#define MX7D_PAD_LPSR_GPIO1_IO07__UART5_DTE_RX                    0x001C 0x004C 0x0714 0x3 0x5
+#define MX7D_PAD_LPSR_GPIO1_IO07__I2C2_SDA                        0x001C 0x004C 0x05E0 0x4 0x2
+#define MX7D_PAD_LPSR_GPIO1_IO07__CCM_STOP                        0x001C 0x004C 0x0000 0x5 0x0
+#define MX7D_PAD_LPSR_GPIO1_IO07__KPP_COL4                        0x001C 0x004C 0x0604 0x6 0x1
+#define MX7D_PAD_GPIO1_IO08__GPIO1_IO8                            0x0014 0x026C 0x0000 0x0 0x0
+#define MX7D_PAD_GPIO1_IO08__SD1_VSELECT                          0x0014 0x026C 0x0000 0x1 0x0
+#define MX7D_PAD_GPIO1_IO08__WDOG1_WDOG_B                         0x0014 0x026C 0x0000 0x2 0x0
+#define MX7D_PAD_GPIO1_IO08__UART3_DCE_RX                         0x0014 0x026C 0x0704 0x3 0x0
+#define MX7D_PAD_GPIO1_IO08__UART3_DTE_TX                         0x0014 0x026C 0x0000 0x3 0x0
+#define MX7D_PAD_GPIO1_IO08__I2C3_SCL                             0x0014 0x026C 0x05E4 0x4 0x0
+#define MX7D_PAD_GPIO1_IO08__KPP_COL5                             0x0014 0x026C 0x0608 0x6 0x0
+#define MX7D_PAD_GPIO1_IO08__PWM1_OUT                             0x0014 0x026C 0x0000 0x7 0x0
+#define MX7D_PAD_GPIO1_IO09__GPIO1_IO9                            0x0018 0x0270 0x0000 0x0 0x0
+#define MX7D_PAD_GPIO1_IO09__SD1_LCTL                             0x0018 0x0270 0x0000 0x1 0x0
+#define MX7D_PAD_GPIO1_IO09__CCM_ENET_REF_CLK3                    0x0018 0x0270 0x0000 0x2 0x0
+#define MX7D_PAD_GPIO1_IO09__UART3_DCE_TX                         0x0018 0x0270 0x0000 0x3 0x0
+#define MX7D_PAD_GPIO1_IO09__UART3_DTE_RX                         0x0018 0x0270 0x0704 0x3 0x1
+#define MX7D_PAD_GPIO1_IO09__I2C3_SDA                             0x0018 0x0270 0x05E8 0x4 0x0
+#define MX7D_PAD_GPIO1_IO09__CCM_PMIC_READY                       0x0018 0x0270 0x04F4 0x5 0x0
+#define MX7D_PAD_GPIO1_IO09__KPP_ROW5                             0x0018 0x0270 0x0628 0x6 0x0
+#define MX7D_PAD_GPIO1_IO09__PWM2_OUT                             0x0018 0x0270 0x0000 0x7 0x0
+#define MX7D_PAD_GPIO1_IO10__GPIO1_IO10                           0x001C 0x0274 0x0000 0x0 0x0
+#define MX7D_PAD_GPIO1_IO10__SD2_LCTL                             0x001C 0x0274 0x0000 0x1 0x0
+#define MX7D_PAD_GPIO1_IO10__ENET1_MDIO                           0x001C 0x0274 0x0568 0x2 0x0
+#define MX7D_PAD_GPIO1_IO10__UART3_DCE_RTS                        0x001C 0x0274 0x0700 0x3 0x0
+#define MX7D_PAD_GPIO1_IO10__UART3_DTE_CTS                        0x001C 0x0274 0x0000 0x3 0x0
+#define MX7D_PAD_GPIO1_IO10__I2C4_SCL                             0x001C 0x0274 0x05EC 0x4 0x0
+#define MX7D_PAD_GPIO1_IO10__FLEXTIMER1_PHA                       0x001C 0x0274 0x05A4 0x5 0x0
+#define MX7D_PAD_GPIO1_IO10__KPP_COL6                             0x001C 0x0274 0x060C 0x6 0x0
+#define MX7D_PAD_GPIO1_IO10__PWM3_OUT                             0x001C 0x0274 0x0000 0x7 0x0
+#define MX7D_PAD_GPIO1_IO11__GPIO1_IO11                           0x0020 0x0278 0x0000 0x0 0x0
+#define MX7D_PAD_GPIO1_IO11__SD3_LCTL                             0x0020 0x0278 0x0000 0x1 0x0
+#define MX7D_PAD_GPIO1_IO11__ENET1_MDC                            0x0020 0x0278 0x0000 0x2 0x0
+#define MX7D_PAD_GPIO1_IO11__UART3_DCE_CTS                        0x0020 0x0278 0x0000 0x3 0x0
+#define MX7D_PAD_GPIO1_IO11__UART3_DTE_RTS                        0x0020 0x0278 0x0700 0x3 0x1
+#define MX7D_PAD_GPIO1_IO11__I2C4_SDA                             0x0020 0x0278 0x05F0 0x4 0x0
+#define MX7D_PAD_GPIO1_IO11__FLEXTIMER1_PHB                       0x0020 0x0278 0x05A8 0x5 0x0
+#define MX7D_PAD_GPIO1_IO11__KPP_ROW6                             0x0020 0x0278 0x062C 0x6 0x0
+#define MX7D_PAD_GPIO1_IO11__PWM4_OUT                             0x0020 0x0278 0x0000 0x7 0x0
+#define MX7D_PAD_GPIO1_IO12__GPIO1_IO12                           0x0024 0x027C 0x0000 0x0 0x0
+#define MX7D_PAD_GPIO1_IO12__SD2_VSELECT                          0x0024 0x027C 0x0000 0x1 0x0
+#define MX7D_PAD_GPIO1_IO12__CCM_ENET_REF_CLK1                    0x0024 0x027C 0x0564 0x2 0x0
+#define MX7D_PAD_GPIO1_IO12__FLEXCAN1_RX                          0x0024 0x027C 0x04DC 0x3 0x0
+#define MX7D_PAD_GPIO1_IO12__CM4_NMI                              0x0024 0x027C 0x0000 0x4 0x0
+#define MX7D_PAD_GPIO1_IO12__CCM_EXT_CLK1                         0x0024 0x027C 0x04E4 0x5 0x0
+#define MX7D_PAD_GPIO1_IO12__SNVS_VIO_5                           0x0024 0x027C 0x0000 0x6 0x0
+#define MX7D_PAD_GPIO1_IO12__USB_OTG1_ID                          0x0024 0x027C 0x0734 0x7 0x0
+#define MX7D_PAD_GPIO1_IO13__GPIO1_IO13                           0x0028 0x0280 0x0000 0x0 0x0
+#define MX7D_PAD_GPIO1_IO13__SD3_VSELECT                          0x0028 0x0280 0x0000 0x1 0x0
+#define MX7D_PAD_GPIO1_IO13__CCM_ENET_REF_CLK2                    0x0028 0x0280 0x0570 0x2 0x0
+#define MX7D_PAD_GPIO1_IO13__FLEXCAN1_TX                          0x0028 0x0280 0x0000 0x3 0x0
+#define MX7D_PAD_GPIO1_IO13__CCM_PMIC_READY                       0x0028 0x0280 0x04F4 0x4 0x1
+#define MX7D_PAD_GPIO1_IO13__CCM_EXT_CLK2                         0x0028 0x0280 0x04E8 0x5 0x0
+#define MX7D_PAD_GPIO1_IO13__SNVS_VIO_5_CTL                       0x0028 0x0280 0x0000 0x6 0x0
+#define MX7D_PAD_GPIO1_IO13__USB_OTG2_ID                          0x0028 0x0280 0x0730 0x7 0x0
+#define MX7D_PAD_GPIO1_IO14__GPIO1_IO14                           0x002C 0x0284 0x0000 0x0 0x0
+#define MX7D_PAD_GPIO1_IO14__SD3_CD_B                             0x002C 0x0284 0x0738 0x1 0x0
+#define MX7D_PAD_GPIO1_IO14__ENET2_MDIO                           0x002C 0x0284 0x0574 0x2 0x0
+#define MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX                          0x002C 0x0284 0x04E0 0x3 0x0
+#define MX7D_PAD_GPIO1_IO14__WDOG3_WDOG_B                         0x002C 0x0284 0x0000 0x4 0x0
+#define MX7D_PAD_GPIO1_IO14__CCM_EXT_CLK3                         0x002C 0x0284 0x04EC 0x5 0x0
+#define MX7D_PAD_GPIO1_IO14__SDMA_EXT_EVENT0                      0x002C 0x0284 0x06D8 0x6 0x0
+#define MX7D_PAD_GPIO1_IO15__GPIO1_IO15                           0x0030 0x0288 0x0000 0x0 0x0
+#define MX7D_PAD_GPIO1_IO15__SD3_WP                               0x0030 0x0288 0x073C 0x1 0x0
+#define MX7D_PAD_GPIO1_IO15__ENET2_MDC                            0x0030 0x0288 0x0000 0x2 0x0
+#define MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX                          0x0030 0x0288 0x0000 0x3 0x0
+#define MX7D_PAD_GPIO1_IO15__WDOG4_WDOG_B                         0x0030 0x0288 0x0000 0x4 0x0
+#define MX7D_PAD_GPIO1_IO15__CCM_EXT_CLK4                         0x0030 0x0288 0x04F0 0x5 0x0
+#define MX7D_PAD_GPIO1_IO15__SDMA_EXT_EVENT1                      0x0030 0x0288 0x06DC 0x6 0x0
+#define MX7D_PAD_EPDC_DATA00__EPDC_DATA0                          0x0034 0x02A4 0x0000 0x0 0x0
+#define MX7D_PAD_EPDC_DATA00__SIM1_PORT2_TRXD                     0x0034 0x02A4 0x0000 0x1 0x0
+#define MX7D_PAD_EPDC_DATA00__QSPI_A_DATA0                        0x0034 0x02A4 0x0000 0x2 0x0
+#define MX7D_PAD_EPDC_DATA00__KPP_ROW3                            0x0034 0x02A4 0x0620 0x3 0x0
+#define MX7D_PAD_EPDC_DATA00__EIM_AD0                             0x0034 0x02A4 0x0000 0x4 0x0
+#define MX7D_PAD_EPDC_DATA00__GPIO2_IO0                           0x0034 0x02A4 0x0000 0x5 0x0
+#define MX7D_PAD_EPDC_DATA00__LCD_DATA0                           0x0034 0x02A4 0x0638 0x6 0x0
+#define MX7D_PAD_EPDC_DATA00__LCD_CLK                             0x0034 0x02A4 0x0000 0x7 0x0
+#define MX7D_PAD_EPDC_DATA01__EPDC_DATA1                          0x0038 0x02A8 0x0000 0x0 0x0
+#define MX7D_PAD_EPDC_DATA01__SIM1_PORT2_CLK                      0x0038 0x02A8 0x0000 0x1 0x0
+#define MX7D_PAD_EPDC_DATA01__QSPI_A_DATA1                        0x0038 0x02A8 0x0000 0x2 0x0
+#define MX7D_PAD_EPDC_DATA01__KPP_COL3                            0x0038 0x02A8 0x0600 0x3 0x0
+#define MX7D_PAD_EPDC_DATA01__EIM_AD1                             0x0038 0x02A8 0x0000 0x4 0x0
+#define MX7D_PAD_EPDC_DATA01__GPIO2_IO1                           0x0038 0x02A8 0x0000 0x5 0x0
+#define MX7D_PAD_EPDC_DATA01__LCD_DATA1                           0x0038 0x02A8 0x063C 0x6 0x0
+#define MX7D_PAD_EPDC_DATA01__LCD_ENABLE                          0x0038 0x02A8 0x0000 0x7 0x0
+#define MX7D_PAD_EPDC_DATA02__EPDC_DATA2                          0x003C 0x02AC 0x0000 0x0 0x0
+#define MX7D_PAD_EPDC_DATA02__SIM1_PORT2_RST_B                    0x003C 0x02AC 0x0000 0x1 0x0
+#define MX7D_PAD_EPDC_DATA02__QSPI_A_DATA2                        0x003C 0x02AC 0x0000 0x2 0x0
+#define MX7D_PAD_EPDC_DATA02__KPP_ROW2                            0x003C 0x02AC 0x061C 0x3 0x0
+#define MX7D_PAD_EPDC_DATA02__EIM_AD2                             0x003C 0x02AC 0x0000 0x4 0x0
+#define MX7D_PAD_EPDC_DATA02__GPIO2_IO2                           0x003C 0x02AC 0x0000 0x5 0x0
+#define MX7D_PAD_EPDC_DATA02__LCD_DATA2                           0x003C 0x02AC 0x0640 0x6 0x0
+#define MX7D_PAD_EPDC_DATA02__LCD_VSYNC                           0x003C 0x02AC 0x0698 0x7 0x0
+#define MX7D_PAD_EPDC_DATA03__EPDC_DATA3                          0x0040 0x02B0 0x0000 0x0 0x0
+#define MX7D_PAD_EPDC_DATA03__SIM1_PORT2_SVEN                     0x0040 0x02B0 0x0000 0x1 0x0
+#define MX7D_PAD_EPDC_DATA03__QSPI_A_DATA3                        0x0040 0x02B0 0x0000 0x2 0x0
+#define MX7D_PAD_EPDC_DATA03__KPP_COL2                            0x0040 0x02B0 0x05FC 0x3 0x0
+#define MX7D_PAD_EPDC_DATA03__EIM_AD3                             0x0040 0x02B0 0x0000 0x4 0x0
+#define MX7D_PAD_EPDC_DATA03__GPIO2_IO3                           0x0040 0x02B0 0x0000 0x5 0x0
+#define MX7D_PAD_EPDC_DATA03__LCD_DATA3                           0x0040 0x02B0 0x0644 0x6 0x0
+#define MX7D_PAD_EPDC_DATA03__LCD_HSYNC                           0x0040 0x02B0 0x0000 0x7 0x0
+#define MX7D_PAD_EPDC_DATA04__EPDC_DATA4                          0x0044 0x02B4 0x0000 0x0 0x0
+#define MX7D_PAD_EPDC_DATA04__SIM1_PORT2_PD                       0x0044 0x02B4 0x0000 0x1 0x0
+#define MX7D_PAD_EPDC_DATA04__QSPI_A_DQS                          0x0044 0x02B4 0x0000 0x2 0x0
+#define MX7D_PAD_EPDC_DATA04__KPP_ROW1                            0x0044 0x02B4 0x0618 0x3 0x0
+#define MX7D_PAD_EPDC_DATA04__EIM_AD4                             0x0044 0x02B4 0x0000 0x4 0x0
+#define MX7D_PAD_EPDC_DATA04__GPIO2_IO4                           0x0044 0x02B4 0x0000 0x5 0x0
+#define MX7D_PAD_EPDC_DATA04__LCD_DATA4                           0x0044 0x02B4 0x0648 0x6 0x0
+#define MX7D_PAD_EPDC_DATA04__JTAG_FAIL                           0x0044 0x02B4 0x0000 0x7 0x0
+#define MX7D_PAD_EPDC_DATA05__EPDC_DATA5                          0x0048 0x02B8 0x0000 0x0 0x0
+#define MX7D_PAD_EPDC_DATA05__SIM2_PORT2_TRXD                     0x0048 0x02B8 0x0000 0x1 0x0
+#define MX7D_PAD_EPDC_DATA05__QSPI_A_SCLK                         0x0048 0x02B8 0x0000 0x2 0x0
+#define MX7D_PAD_EPDC_DATA05__KPP_COL1                            0x0048 0x02B8 0x05F8 0x3 0x0
+#define MX7D_PAD_EPDC_DATA05__EIM_AD5                             0x0048 0x02B8 0x0000 0x4 0x0
+#define MX7D_PAD_EPDC_DATA05__GPIO2_IO5                           0x0048 0x02B8 0x0000 0x5 0x0
+#define MX7D_PAD_EPDC_DATA05__LCD_DATA5                           0x0048 0x02B8 0x064C 0x6 0x0
+#define MX7D_PAD_EPDC_DATA05__JTAG_ACTIVE                         0x0048 0x02B8 0x0000 0x7 0x0
+#define MX7D_PAD_EPDC_DATA06__EPDC_DATA6                          0x004C 0x02BC 0x0000 0x0 0x0
+#define MX7D_PAD_EPDC_DATA06__SIM2_PORT2_CLK                      0x004C 0x02BC 0x0000 0x1 0x0
+#define MX7D_PAD_EPDC_DATA06__QSPI_A_SS0_B                        0x004C 0x02BC 0x0000 0x2 0x0
+#define MX7D_PAD_EPDC_DATA06__KPP_ROW0                            0x004C 0x02BC 0x0614 0x3 0x0
+#define MX7D_PAD_EPDC_DATA06__EIM_AD6                             0x004C 0x02BC 0x0000 0x4 0x0
+#define MX7D_PAD_EPDC_DATA06__GPIO2_IO6                           0x004C 0x02BC 0x0000 0x5 0x0
+#define MX7D_PAD_EPDC_DATA06__LCD_DATA6                           0x004C 0x02BC 0x0650 0x6 0x0
+#define MX7D_PAD_EPDC_DATA06__JTAG_DE_B                           0x004C 0x02BC 0x0000 0x7 0x0
+#define MX7D_PAD_EPDC_DATA07__EPDC_DATA7                          0x0050 0x02C0 0x0000 0x0 0x0
+#define MX7D_PAD_EPDC_DATA07__SIM2_PORT2_RST_B                    0x0050 0x02C0 0x0000 0x1 0x0
+#define MX7D_PAD_EPDC_DATA07__QSPI_A_SS1_B                        0x0050 0x02C0 0x0000 0x2 0x0
+#define MX7D_PAD_EPDC_DATA07__KPP_COL0                            0x0050 0x02C0 0x05F4 0x3 0x0
+#define MX7D_PAD_EPDC_DATA07__EIM_AD7                             0x0050 0x02C0 0x0000 0x4 0x0
+#define MX7D_PAD_EPDC_DATA07__GPIO2_IO7                           0x0050 0x02C0 0x0000 0x5 0x0
+#define MX7D_PAD_EPDC_DATA07__LCD_DATA7                           0x0050 0x02C0 0x0654 0x6 0x0
+#define MX7D_PAD_EPDC_DATA07__JTAG_DONE                           0x0050 0x02C0 0x0000 0x7 0x0
+#define MX7D_PAD_EPDC_DATA08__EPDC_DATA8                          0x0054 0x02C4 0x0000 0x0 0x0
+#define MX7D_PAD_EPDC_DATA08__SIM1_PORT1_TRXD                     0x0054 0x02C4 0x06E4 0x1 0x0
+#define MX7D_PAD_EPDC_DATA08__QSPI_B_DATA0                        0x0054 0x02C4 0x0000 0x2 0x0
+#define MX7D_PAD_EPDC_DATA08__UART6_DCE_RX                        0x0054 0x02C4 0x071C 0x3 0x0
+#define MX7D_PAD_EPDC_DATA08__UART6_DTE_TX                        0x0054 0x02C4 0x0000 0x3 0x0
+#define MX7D_PAD_EPDC_DATA08__EIM_OE                              0x0054 0x02C4 0x0000 0x4 0x0
+#define MX7D_PAD_EPDC_DATA08__GPIO2_IO8                           0x0054 0x02C4 0x0000 0x5 0x0
+#define MX7D_PAD_EPDC_DATA08__LCD_DATA8                           0x0054 0x02C4 0x0658 0x6 0x0
+#define MX7D_PAD_EPDC_DATA08__LCD_BUSY                            0x0054 0x02C4 0x0634 0x7 0x0
+#define MX7D_PAD_EPDC_DATA08__EPDC_SDCLK                          0x0054 0x02C4 0x0000 0x8 0x0
+#define MX7D_PAD_EPDC_DATA09__EPDC_DATA9                          0x0058 0x02C8 0x0000 0x0 0x0
+#define MX7D_PAD_EPDC_DATA09__SIM1_PORT1_CLK                      0x0058 0x02C8 0x0000 0x1 0x0
+#define MX7D_PAD_EPDC_DATA09__QSPI_B_DATA1                        0x0058 0x02C8 0x0000 0x2 0x0
+#define MX7D_PAD_EPDC_DATA09__UART6_DCE_TX                        0x0058 0x02C8 0x0000 0x3 0x0
+#define MX7D_PAD_EPDC_DATA09__UART6_DTE_RX                        0x0058 0x02C8 0x071C 0x3 0x1
+#define MX7D_PAD_EPDC_DATA09__EIM_RW                              0x0058 0x02C8 0x0000 0x4 0x0
+#define MX7D_PAD_EPDC_DATA09__GPIO2_IO9                           0x0058 0x02C8 0x0000 0x5 0x0
+#define MX7D_PAD_EPDC_DATA09__LCD_DATA9                           0x0058 0x02C8 0x065C 0x6 0x0
+#define MX7D_PAD_EPDC_DATA09__LCD_DATA0                           0x0058 0x02C8 0x0638 0x7 0x1
+#define MX7D_PAD_EPDC_DATA09__EPDC_SDLE                           0x0058 0x02C8 0x0000 0x8 0x0
+#define MX7D_PAD_EPDC_DATA10__EPDC_DATA10                         0x005C 0x02CC 0x0000 0x0 0x0
+#define MX7D_PAD_EPDC_DATA10__SIM1_PORT1_RST_B                    0x005C 0x02CC 0x0000 0x1 0x0
+#define MX7D_PAD_EPDC_DATA10__QSPI_B_DATA2                        0x005C 0x02CC 0x0000 0x2 0x0
+#define MX7D_PAD_EPDC_DATA10__UART6_DCE_RTS                       0x005C 0x02CC 0x0718 0x3 0x0
+#define MX7D_PAD_EPDC_DATA10__UART6_DTE_CTS                       0x005C 0x02CC 0x0000 0x3 0x0
+#define MX7D_PAD_EPDC_DATA10__EIM_CS0_B                           0x005C 0x02CC 0x0000 0x4 0x0
+#define MX7D_PAD_EPDC_DATA10__GPIO2_IO10                          0x005C 0x02CC 0x0000 0x5 0x0
+#define MX7D_PAD_EPDC_DATA10__LCD_DATA10                          0x005C 0x02CC 0x0660 0x6 0x0
+#define MX7D_PAD_EPDC_DATA10__LCD_DATA9                           0x005C 0x02CC 0x065C 0x7 0x1
+#define MX7D_PAD_EPDC_DATA10__EPDC_SDOE                           0x005C 0x02CC 0x0000 0x8 0x0
+#define MX7D_PAD_EPDC_DATA11__EPDC_DATA11                         0x0060 0x02D0 0x0000 0x0 0x0
+#define MX7D_PAD_EPDC_DATA11__SIM1_PORT1_SVEN                     0x0060 0x02D0 0x0000 0x1 0x0
+#define MX7D_PAD_EPDC_DATA11__QSPI_B_DATA3                        0x0060 0x02D0 0x0000 0x2 0x0
+#define MX7D_PAD_EPDC_DATA11__UART6_DCE_CTS                       0x0060 0x02D0 0x0000 0x3 0x0
+#define MX7D_PAD_EPDC_DATA11__UART6_DTE_RTS                       0x0060 0x02D0 0x0718 0x3 0x1
+#define MX7D_PAD_EPDC_DATA11__EIM_BCLK                            0x0060 0x02D0 0x0000 0x4 0x0
+#define MX7D_PAD_EPDC_DATA11__GPIO2_IO11                          0x0060 0x02D0 0x0000 0x5 0x0
+#define MX7D_PAD_EPDC_DATA11__LCD_DATA11                          0x0060 0x02D0 0x0664 0x6 0x0
+#define MX7D_PAD_EPDC_DATA11__LCD_DATA1                           0x0060 0x02D0 0x063C 0x7 0x1
+#define MX7D_PAD_EPDC_DATA11__EPDC_SDCE0                          0x0060 0x02D0 0x0000 0x8 0x0
+#define MX7D_PAD_EPDC_DATA12__EPDC_DATA12                         0x0064 0x02D4 0x0000 0x0 0x0
+#define MX7D_PAD_EPDC_DATA12__SIM1_PORT1_PD                       0x0064 0x02D4 0x06E0 0x1 0x0
+#define MX7D_PAD_EPDC_DATA12__QSPI_B_DQS                          0x0064 0x02D4 0x0000 0x2 0x0
+#define MX7D_PAD_EPDC_DATA12__UART7_DCE_RX                        0x0064 0x02D4 0x0724 0x3 0x0
+#define MX7D_PAD_EPDC_DATA12__UART7_DTE_TX                        0x0064 0x02D4 0x0000 0x3 0x0
+#define MX7D_PAD_EPDC_DATA12__EIM_LBA_B                           0x0064 0x02D4 0x0000 0x4 0x0
+#define MX7D_PAD_EPDC_DATA12__GPIO2_IO12                          0x0064 0x02D4 0x0000 0x5 0x0
+#define MX7D_PAD_EPDC_DATA12__LCD_DATA12                          0x0064 0x02D4 0x0668 0x6 0x0
+#define MX7D_PAD_EPDC_DATA12__LCD_DATA21                          0x0064 0x02D4 0x068C 0x7 0x0
+#define MX7D_PAD_EPDC_DATA12__EPDC_GDCLK                          0x0064 0x02D4 0x0000 0x8 0x0
+#define MX7D_PAD_EPDC_DATA13__EPDC_DATA13                         0x0068 0x02D8 0x0000 0x0 0x0
+#define MX7D_PAD_EPDC_DATA13__SIM2_PORT1_TRXD                     0x0068 0x02D8 0x06EC 0x1 0x0
+#define MX7D_PAD_EPDC_DATA13__QSPI_B_SCLK                         0x0068 0x02D8 0x0000 0x2 0x0
+#define MX7D_PAD_EPDC_DATA13__UART7_DCE_TX                        0x0068 0x02D8 0x0000 0x3 0x0
+#define MX7D_PAD_EPDC_DATA13__UART7_DTE_RX                        0x0068 0x02D8 0x0724 0x3 0x1
+#define MX7D_PAD_EPDC_DATA13__EIM_WAIT                            0x0068 0x02D8 0x0000 0x4 0x0
+#define MX7D_PAD_EPDC_DATA13__GPIO2_IO13                          0x0068 0x02D8 0x0000 0x5 0x0
+#define MX7D_PAD_EPDC_DATA13__LCD_DATA13                          0x0068 0x02D8 0x066C 0x6 0x0
+#define MX7D_PAD_EPDC_DATA13__LCD_CS                              0x0068 0x02D8 0x0000 0x7 0x0
+#define MX7D_PAD_EPDC_DATA13__EPDC_GDOE                           0x0068 0x02D8 0x0000 0x8 0x0
+#define MX7D_PAD_EPDC_DATA14__EPDC_DATA14                         0x006C 0x02DC 0x0000 0x0 0x0
+#define MX7D_PAD_EPDC_DATA14__SIM2_PORT1_CLK                      0x006C 0x02DC 0x0000 0x1 0x0
+#define MX7D_PAD_EPDC_DATA14__QSPI_B_SS0_B                        0x006C 0x02DC 0x0000 0x2 0x0
+#define MX7D_PAD_EPDC_DATA14__UART7_DCE_RTS                       0x006C 0x02DC 0x0720 0x3 0x0
+#define MX7D_PAD_EPDC_DATA14__UART7_DTE_CTS                       0x006C 0x02DC 0x0000 0x3 0x0
+#define MX7D_PAD_EPDC_DATA14__EIM_EB_B0                           0x006C 0x02DC 0x0000 0x4 0x0
+#define MX7D_PAD_EPDC_DATA14__GPIO2_IO14                          0x006C 0x02DC 0x0000 0x5 0x0
+#define MX7D_PAD_EPDC_DATA14__LCD_DATA14                          0x006C 0x02DC 0x0670 0x6 0x0
+#define MX7D_PAD_EPDC_DATA14__LCD_DATA22                          0x006C 0x02DC 0x0690 0x7 0x0
+#define MX7D_PAD_EPDC_DATA14__EPDC_GDSP                           0x006C 0x02DC 0x0000 0x8 0x0
+#define MX7D_PAD_EPDC_DATA15__EPDC_DATA15                         0x0070 0x02E0 0x0000 0x0 0x0
+#define MX7D_PAD_EPDC_DATA15__SIM2_PORT1_RST_B                    0x0070 0x02E0 0x0000 0x1 0x0
+#define MX7D_PAD_EPDC_DATA15__QSPI_B_SS1_B                        0x0070 0x02E0 0x0000 0x2 0x0
+#define MX7D_PAD_EPDC_DATA15__UART7_DCE_CTS                       0x0070 0x02E0 0x0000 0x3 0x0
+#define MX7D_PAD_EPDC_DATA15__UART7_DTE_RTS                       0x0070 0x02E0 0x0720 0x3 0x1
+#define MX7D_PAD_EPDC_DATA15__EIM_CS1_B                           0x0070 0x02E0 0x0000 0x4 0x0
+#define MX7D_PAD_EPDC_DATA15__GPIO2_IO15                          0x0070 0x02E0 0x0000 0x5 0x0
+#define MX7D_PAD_EPDC_DATA15__LCD_DATA15                          0x0070 0x02E0 0x0674 0x6 0x0
+#define MX7D_PAD_EPDC_DATA15__LCD_WR_RWN                          0x0070 0x02E0 0x0000 0x7 0x0
+#define MX7D_PAD_EPDC_DATA15__EPDC_PWR_COM                        0x0070 0x02E0 0x0000 0x8 0x0
+#define MX7D_PAD_EPDC_SDCLK__EPDC_SDCLK                           0x0074 0x02E4 0x0000 0x0 0x0
+#define MX7D_PAD_EPDC_SDCLK__SIM2_PORT2_SVEN                      0x0074 0x02E4 0x0000 0x1 0x0
+#define MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0                      0x0074 0x02E4 0x0000 0x2 0x0
+#define MX7D_PAD_EPDC_SDCLK__KPP_ROW4                             0x0074 0x02E4 0x0624 0x3 0x0
+#define MX7D_PAD_EPDC_SDCLK__EIM_AD10                             0x0074 0x02E4 0x0000 0x4 0x0
+#define MX7D_PAD_EPDC_SDCLK__GPIO2_IO16                           0x0074 0x02E4 0x0000 0x5 0x0
+#define MX7D_PAD_EPDC_SDCLK__LCD_CLK                              0x0074 0x02E4 0x0000 0x6 0x0
+#define MX7D_PAD_EPDC_SDCLK__LCD_DATA20                           0x0074 0x02E4 0x0688 0x7 0x0
+#define MX7D_PAD_EPDC_SDLE__EPDC_SDLE                             0x0078 0x02E8 0x0000 0x0 0x0
+#define MX7D_PAD_EPDC_SDLE__SIM2_PORT2_PD                         0x0078 0x02E8 0x0000 0x1 0x0
+#define MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1                       0x0078 0x02E8 0x0000 0x2 0x0
+#define MX7D_PAD_EPDC_SDLE__KPP_COL4                              0x0078 0x02E8 0x0604 0x3 0x0
+#define MX7D_PAD_EPDC_SDLE__EIM_AD11                              0x0078 0x02E8 0x0000 0x4 0x0
+#define MX7D_PAD_EPDC_SDLE__GPIO2_IO17                            0x0078 0x02E8 0x0000 0x5 0x0
+#define MX7D_PAD_EPDC_SDLE__LCD_DATA16                            0x0078 0x02E8 0x0678 0x6 0x0
+#define MX7D_PAD_EPDC_SDLE__LCD_DATA8                             0x0078 0x02E8 0x0658 0x7 0x1
+#define MX7D_PAD_EPDC_SDOE__EPDC_SDOE                             0x007C 0x02EC 0x0000 0x0 0x0
+#define MX7D_PAD_EPDC_SDOE__FLEXTIMER1_CH0                        0x007C 0x02EC 0x0584 0x1 0x0
+#define MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2                       0x007C 0x02EC 0x0000 0x2 0x0
+#define MX7D_PAD_EPDC_SDOE__KPP_COL5                              0x007C 0x02EC 0x0608 0x3 0x1
+#define MX7D_PAD_EPDC_SDOE__EIM_AD12                              0x007C 0x02EC 0x0000 0x4 0x0
+#define MX7D_PAD_EPDC_SDOE__GPIO2_IO18                            0x007C 0x02EC 0x0000 0x5 0x0
+#define MX7D_PAD_EPDC_SDOE__LCD_DATA17                            0x007C 0x02EC 0x067C 0x6 0x0
+#define MX7D_PAD_EPDC_SDOE__LCD_DATA23                            0x007C 0x02EC 0x0694 0x7 0x0
+#define MX7D_PAD_EPDC_SDSHR__EPDC_SDSHR                           0x0080 0x02F0 0x0000 0x0 0x0
+#define MX7D_PAD_EPDC_SDSHR__FLEXTIMER1_CH1                       0x0080 0x02F0 0x0588 0x1 0x0
+#define MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3                      0x0080 0x02F0 0x0000 0x2 0x0
+#define MX7D_PAD_EPDC_SDSHR__KPP_ROW5                             0x0080 0x02F0 0x0628 0x3 0x1
+#define MX7D_PAD_EPDC_SDSHR__EIM_AD13                             0x0080 0x02F0 0x0000 0x4 0x0
+#define MX7D_PAD_EPDC_SDSHR__GPIO2_IO19                           0x0080 0x02F0 0x0000 0x5 0x0
+#define MX7D_PAD_EPDC_SDSHR__LCD_DATA18                           0x0080 0x02F0 0x0680 0x6 0x0
+#define MX7D_PAD_EPDC_SDSHR__LCD_DATA10                           0x0080 0x02F0 0x0660 0x7 0x1
+#define MX7D_PAD_EPDC_SDCE0__EPDC_SDCE0                           0x0084 0x02F4 0x0000 0x0 0x0
+#define MX7D_PAD_EPDC_SDCE0__FLEXTIMER1_CH2                       0x0084 0x02F4 0x058C 0x1 0x0
+#define MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL                   0x0084 0x02F4 0x0000 0x2 0x0
+#define MX7D_PAD_EPDC_SDCE0__EIM_AD14                             0x0084 0x02F4 0x0000 0x4 0x0
+#define MX7D_PAD_EPDC_SDCE0__GPIO2_IO20                           0x0084 0x02F4 0x0000 0x5 0x0
+#define MX7D_PAD_EPDC_SDCE0__LCD_DATA19                           0x0084 0x02F4 0x0684 0x6 0x0
+#define MX7D_PAD_EPDC_SDCE0__LCD_DATA5                            0x0084 0x02F4 0x064C 0x7 0x1
+#define MX7D_PAD_EPDC_SDCE1__EPDC_SDCE1                           0x0088 0x02F8 0x0000 0x0 0x0
+#define MX7D_PAD_EPDC_SDCE1__FLEXTIMER1_CH3                       0x0088 0x02F8 0x0590 0x1 0x0
+#define MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC                      0x0088 0x02F8 0x0578 0x2 0x0
+#define MX7D_PAD_EPDC_SDCE1__ENET2_RX_ER                          0x0088 0x02F8 0x0000 0x3 0x0
+#define MX7D_PAD_EPDC_SDCE1__EIM_AD15                             0x0088 0x02F8 0x0000 0x4 0x0
+#define MX7D_PAD_EPDC_SDCE1__GPIO2_IO21                           0x0088 0x02F8 0x0000 0x5 0x0
+#define MX7D_PAD_EPDC_SDCE1__LCD_DATA20                           0x0088 0x02F8 0x0688 0x6 0x1
+#define MX7D_PAD_EPDC_SDCE1__LCD_DATA4                            0x0088 0x02F8 0x0648 0x7 0x1
+#define MX7D_PAD_EPDC_SDCE2__EPDC_SDCE2                           0x008C 0x02FC 0x0000 0x0 0x0
+#define MX7D_PAD_EPDC_SDCE2__SIM2_PORT1_SVEN                      0x008C 0x02FC 0x0000 0x1 0x0
+#define MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0                      0x008C 0x02FC 0x0000 0x2 0x0
+#define MX7D_PAD_EPDC_SDCE2__KPP_COL6                             0x008C 0x02FC 0x060C 0x3 0x1
+#define MX7D_PAD_EPDC_SDCE2__EIM_ADDR16                           0x008C 0x02FC 0x0000 0x4 0x0
+#define MX7D_PAD_EPDC_SDCE2__GPIO2_IO22                           0x008C 0x02FC 0x0000 0x5 0x0
+#define MX7D_PAD_EPDC_SDCE2__LCD_DATA21                           0x008C 0x02FC 0x068C 0x6 0x1
+#define MX7D_PAD_EPDC_SDCE2__LCD_DATA3                            0x008C 0x02FC 0x0644 0x7 0x1
+#define MX7D_PAD_EPDC_SDCE3__EPDC_SDCE3                           0x0090 0x0300 0x0000 0x0 0x0
+#define MX7D_PAD_EPDC_SDCE3__SIM2_PORT1_PD                        0x0090 0x0300 0x06E8 0x1 0x0
+#define MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1                      0x0090 0x0300 0x0000 0x2 0x0
+#define MX7D_PAD_EPDC_SDCE3__KPP_ROW6                             0x0090 0x0300 0x062C 0x3 0x1
+#define MX7D_PAD_EPDC_SDCE3__EIM_ADDR17                           0x0090 0x0300 0x0000 0x4 0x0
+#define MX7D_PAD_EPDC_SDCE3__GPIO2_IO23                           0x0090 0x0300 0x0000 0x5 0x0
+#define MX7D_PAD_EPDC_SDCE3__LCD_DATA22                           0x0090 0x0300 0x0690 0x6 0x1
+#define MX7D_PAD_EPDC_SDCE3__LCD_DATA2                            0x0090 0x0300 0x0640 0x7 0x1
+#define MX7D_PAD_EPDC_GDCLK__EPDC_GDCLK                           0x0094 0x0304 0x0000 0x0 0x0
+#define MX7D_PAD_EPDC_GDCLK__FLEXTIMER2_CH0                       0x0094 0x0304 0x05AC 0x1 0x0
+#define MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2                      0x0094 0x0304 0x0000 0x2 0x0
+#define MX7D_PAD_EPDC_GDCLK__KPP_COL7                             0x0094 0x0304 0x0610 0x3 0x0
+#define MX7D_PAD_EPDC_GDCLK__EIM_ADDR18                           0x0094 0x0304 0x0000 0x4 0x0
+#define MX7D_PAD_EPDC_GDCLK__GPIO2_IO24                           0x0094 0x0304 0x0000 0x5 0x0
+#define MX7D_PAD_EPDC_GDCLK__LCD_DATA23                           0x0094 0x0304 0x0694 0x6 0x1
+#define MX7D_PAD_EPDC_GDCLK__LCD_DATA16                           0x0094 0x0304 0x0678 0x7 0x1
+#define MX7D_PAD_EPDC_GDOE__EPDC_GDOE                             0x0098 0x0308 0x0000 0x0 0x0
+#define MX7D_PAD_EPDC_GDOE__FLEXTIMER2_CH1                        0x0098 0x0308 0x05B0 0x1 0x0
+#define MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3                       0x0098 0x0308 0x0000 0x2 0x0
+#define MX7D_PAD_EPDC_GDOE__KPP_ROW7                              0x0098 0x0308 0x0630 0x3 0x0
+#define MX7D_PAD_EPDC_GDOE__EIM_ADDR19                            0x0098 0x0308 0x0000 0x4 0x0
+#define MX7D_PAD_EPDC_GDOE__GPIO2_IO25                            0x0098 0x0308 0x0000 0x5 0x0
+#define MX7D_PAD_EPDC_GDOE__LCD_WR_RWN                            0x0098 0x0308 0x0000 0x6 0x0
+#define MX7D_PAD_EPDC_GDOE__LCD_DATA18                            0x0098 0x0308 0x0680 0x7 0x1
+#define MX7D_PAD_EPDC_GDRL__EPDC_GDRL                             0x009C 0x030C 0x0000 0x0 0x0
+#define MX7D_PAD_EPDC_GDRL__FLEXTIMER2_CH2                        0x009C 0x030C 0x05B4 0x1 0x0
+#define MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL                    0x009C 0x030C 0x0000 0x2 0x0
+#define MX7D_PAD_EPDC_GDRL__EIM_ADDR20                            0x009C 0x030C 0x0000 0x4 0x0
+#define MX7D_PAD_EPDC_GDRL__GPIO2_IO26                            0x009C 0x030C 0x0000 0x5 0x0
+#define MX7D_PAD_EPDC_GDRL__LCD_RD_E                              0x009C 0x030C 0x0000 0x6 0x0
+#define MX7D_PAD_EPDC_GDRL__LCD_DATA19                            0x009C 0x030C 0x0684 0x7 0x1
+#define MX7D_PAD_EPDC_GDSP__EPDC_GDSP                             0x00A0 0x0310 0x0000 0x0 0x0
+#define MX7D_PAD_EPDC_GDSP__FLEXTIMER2_CH3                        0x00A0 0x0310 0x05B8 0x1 0x0
+#define MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC                       0x00A0 0x0310 0x0000 0x2 0x0
+#define MX7D_PAD_EPDC_GDSP__ENET2_TX_ER                           0x00A0 0x0310 0x0000 0x3 0x0
+#define MX7D_PAD_EPDC_GDSP__EIM_ADDR21                            0x00A0 0x0310 0x0000 0x4 0x0
+#define MX7D_PAD_EPDC_GDSP__GPIO2_IO27                            0x00A0 0x0310 0x0000 0x5 0x0
+#define MX7D_PAD_EPDC_GDSP__LCD_BUSY                              0x00A0 0x0310 0x0634 0x6 0x1
+#define MX7D_PAD_EPDC_GDSP__LCD_DATA17                            0x00A0 0x0310 0x067C 0x7 0x1
+#define MX7D_PAD_EPDC_BDR0__EPDC_BDR0                             0x00A4 0x0314 0x0000 0x0 0x0
+#define MX7D_PAD_EPDC_BDR0__ENET2_TX_CLK                          0x00A4 0x0314 0x0000 0x2 0x0
+#define MX7D_PAD_EPDC_BDR0__CCM_ENET_REF_CLK2                     0x00A4 0x0314 0x0570 0x3 0x1
+#define MX7D_PAD_EPDC_BDR0__EIM_ADDR22                            0x00A4 0x0314 0x0000 0x4 0x0
+#define MX7D_PAD_EPDC_BDR0__GPIO2_IO28                            0x00A4 0x0314 0x0000 0x5 0x0
+#define MX7D_PAD_EPDC_BDR0__LCD_CS                                0x00A4 0x0314 0x0000 0x6 0x0
+#define MX7D_PAD_EPDC_BDR0__LCD_DATA7                             0x00A4 0x0314 0x0654 0x7 0x1
+#define MX7D_PAD_EPDC_BDR1__EPDC_BDR1                             0x00A8 0x0318 0x0000 0x0 0x0
+#define MX7D_PAD_EPDC_BDR1__EPDC_SDCLKN                           0x00A8 0x0318 0x0000 0x1 0x0
+#define MX7D_PAD_EPDC_BDR1__ENET2_RX_CLK                          0x00A8 0x0318 0x0578 0x2 0x1
+#define MX7D_PAD_EPDC_BDR1__EIM_AD8                               0x00A8 0x0318 0x0000 0x4 0x0
+#define MX7D_PAD_EPDC_BDR1__GPIO2_IO29                            0x00A8 0x0318 0x0000 0x5 0x0
+#define MX7D_PAD_EPDC_BDR1__LCD_ENABLE                            0x00A8 0x0318 0x0000 0x6 0x0
+#define MX7D_PAD_EPDC_BDR1__LCD_DATA6                             0x00A8 0x0318 0x0650 0x7 0x1
+#define MX7D_PAD_EPDC_PWR_COM__EPDC_PWR_COM                       0x00AC 0x031C 0x0000 0x0 0x0
+#define MX7D_PAD_EPDC_PWR_COM__FLEXTIMER2_PHA                     0x00AC 0x031C 0x05CC 0x1 0x0
+#define MX7D_PAD_EPDC_PWR_COM__ENET2_CRS                          0x00AC 0x031C 0x0000 0x2 0x0
+#define MX7D_PAD_EPDC_PWR_COM__EIM_AD9                            0x00AC 0x031C 0x0000 0x4 0x0
+#define MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30                         0x00AC 0x031C 0x0000 0x5 0x0
+#define MX7D_PAD_EPDC_PWR_COM__LCD_HSYNC                          0x00AC 0x031C 0x0000 0x6 0x0
+#define MX7D_PAD_EPDC_PWR_COM__LCD_DATA11                         0x00AC 0x031C 0x0664 0x7 0x1
+#define MX7D_PAD_EPDC_PWR_STAT__EPDC_PWR_STAT                     0x00B0 0x0320 0x0580 0x0 0x0
+#define MX7D_PAD_EPDC_PWR_STAT__FLEXTIMER2_PHB                    0x00B0 0x0320 0x05D0 0x1 0x0
+#define MX7D_PAD_EPDC_PWR_STAT__ENET2_COL                         0x00B0 0x0320 0x0000 0x2 0x0
+#define MX7D_PAD_EPDC_PWR_STAT__EIM_EB_B1                         0x00B0 0x0320 0x0000 0x4 0x0
+#define MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31                        0x00B0 0x0320 0x0000 0x5 0x0
+#define MX7D_PAD_EPDC_PWR_STAT__LCD_VSYNC                         0x00B0 0x0320 0x0698 0x6 0x1
+#define MX7D_PAD_EPDC_PWR_STAT__LCD_DATA12                        0x00B0 0x0320 0x0668 0x7 0x1
+#define MX7D_PAD_LCD_CLK__LCD_CLK                                 0x00B4 0x0324 0x0000 0x0 0x0
+#define MX7D_PAD_LCD_CLK__ECSPI4_MISO                             0x00B4 0x0324 0x0558 0x1 0x0
+#define MX7D_PAD_LCD_CLK__ENET1_1588_EVENT2_IN                    0x00B4 0x0324 0x0000 0x2 0x0
+#define MX7D_PAD_LCD_CLK__CSI_DATA16                              0x00B4 0x0324 0x0000 0x3 0x0
+#define MX7D_PAD_LCD_CLK__UART2_DCE_RX                            0x00B4 0x0324 0x06FC 0x4 0x0
+#define MX7D_PAD_LCD_CLK__UART2_DTE_TX                            0x00B4 0x0324 0x0000 0x4 0x0
+#define MX7D_PAD_LCD_CLK__GPIO3_IO0                               0x00B4 0x0324 0x0000 0x5 0x0
+#define MX7D_PAD_LCD_ENABLE__LCD_ENABLE                           0x00B8 0x0328 0x0000 0x0 0x0
+#define MX7D_PAD_LCD_ENABLE__ECSPI4_MOSI                          0x00B8 0x0328 0x055C 0x1 0x0
+#define MX7D_PAD_LCD_ENABLE__ENET1_1588_EVENT3_IN                 0x00B8 0x0328 0x0000 0x2 0x0
+#define MX7D_PAD_LCD_ENABLE__CSI_DATA17                           0x00B8 0x0328 0x0000 0x3 0x0
+#define MX7D_PAD_LCD_ENABLE__UART2_DCE_TX                         0x00B8 0x0328 0x0000 0x4 0x0
+#define MX7D_PAD_LCD_ENABLE__UART2_DTE_RX                         0x00B8 0x0328 0x06FC 0x4 0x1
+#define MX7D_PAD_LCD_ENABLE__GPIO3_IO1                            0x00B8 0x0328 0x0000 0x5 0x0
+#define MX7D_PAD_LCD_HSYNC__LCD_HSYNC                             0x00BC 0x032C 0x0000 0x0 0x0
+#define MX7D_PAD_LCD_HSYNC__ECSPI4_SCLK                           0x00BC 0x032C 0x0554 0x1 0x0
+#define MX7D_PAD_LCD_HSYNC__ENET2_1588_EVENT2_IN                  0x00BC 0x032C 0x0000 0x2 0x0
+#define MX7D_PAD_LCD_HSYNC__CSI_DATA18                            0x00BC 0x032C 0x0000 0x3 0x0
+#define MX7D_PAD_LCD_HSYNC__UART2_DCE_RTS                         0x00BC 0x032C 0x06F8 0x4 0x0
+#define MX7D_PAD_LCD_HSYNC__UART2_DTE_CTS                         0x00BC 0x032C 0x0000 0x4 0x0
+#define MX7D_PAD_LCD_HSYNC__GPIO3_IO2                             0x00BC 0x032C 0x0000 0x5 0x0
+#define MX7D_PAD_LCD_VSYNC__LCD_VSYNC                             0x00C0 0x0330 0x0698 0x0 0x2
+#define MX7D_PAD_LCD_VSYNC__ECSPI4_SS0                            0x00C0 0x0330 0x0560 0x1 0x0
+#define MX7D_PAD_LCD_VSYNC__ENET2_1588_EVENT3_IN                  0x00C0 0x0330 0x0000 0x2 0x0
+#define MX7D_PAD_LCD_VSYNC__CSI_DATA19                            0x00C0 0x0330 0x0000 0x3 0x0
+#define MX7D_PAD_LCD_VSYNC__UART2_DCE_CTS                         0x00C0 0x0330 0x0000 0x4 0x0
+#define MX7D_PAD_LCD_VSYNC__UART2_DTE_RTS                         0x00C0 0x0330 0x06F8 0x4 0x1
+#define MX7D_PAD_LCD_VSYNC__GPIO3_IO3                             0x00C0 0x0330 0x0000 0x5 0x0
+#define MX7D_PAD_LCD_RESET__LCD_RESET                             0x00C4 0x0334 0x0000 0x0 0x0
+#define MX7D_PAD_LCD_RESET__GPT1_COMPARE1                         0x00C4 0x0334 0x0000 0x1 0x0
+#define MX7D_PAD_LCD_RESET__ARM_PLATFORM_EVENTI                   0x00C4 0x0334 0x0000 0x2 0x0
+#define MX7D_PAD_LCD_RESET__CSI_FIELD                             0x00C4 0x0334 0x0000 0x3 0x0
+#define MX7D_PAD_LCD_RESET__EIM_DTACK_B                           0x00C4 0x0334 0x0000 0x4 0x0
+#define MX7D_PAD_LCD_RESET__GPIO3_IO4                             0x00C4 0x0334 0x0000 0x5 0x0
+#define MX7D_PAD_LCD_DATA00__LCD_DATA0                            0x00C8 0x0338 0x0638 0x0 0x2
+#define MX7D_PAD_LCD_DATA00__GPT1_COMPARE2                        0x00C8 0x0338 0x0000 0x1 0x0
+#define MX7D_PAD_LCD_DATA00__CSI_DATA20                           0x00C8 0x0338 0x0000 0x3 0x0
+#define MX7D_PAD_LCD_DATA00__EIM_DATA0                            0x00C8 0x0338 0x0000 0x4 0x0
+#define MX7D_PAD_LCD_DATA00__GPIO3_IO5                            0x00C8 0x0338 0x0000 0x5 0x0
+#define MX7D_PAD_LCD_DATA00__SRC_BOOT_CFG0                        0x00C8 0x0338 0x0000 0x6 0x0
+#define MX7D_PAD_LCD_DATA01__LCD_DATA1                            0x00CC 0x033C 0x063C 0x0 0x2
+#define MX7D_PAD_LCD_DATA01__GPT1_COMPARE3                        0x00CC 0x033C 0x0000 0x1 0x0
+#define MX7D_PAD_LCD_DATA01__CSI_DATA21                           0x00CC 0x033C 0x0000 0x3 0x0
+#define MX7D_PAD_LCD_DATA01__EIM_DATA1                            0x00CC 0x033C 0x0000 0x4 0x0
+#define MX7D_PAD_LCD_DATA01__GPIO3_IO6                            0x00CC 0x033C 0x0000 0x5 0x0
+#define MX7D_PAD_LCD_DATA01__SRC_BOOT_CFG1                        0x00CC 0x033C 0x0000 0x6 0x0
+#define MX7D_PAD_LCD_DATA02__LCD_DATA2                            0x00D0 0x0340 0x0640 0x0 0x2
+#define MX7D_PAD_LCD_DATA02__GPT1_CLK                             0x00D0 0x0340 0x0000 0x1 0x0
+#define MX7D_PAD_LCD_DATA02__CSI_DATA22                           0x00D0 0x0340 0x0000 0x3 0x0
+#define MX7D_PAD_LCD_DATA02__EIM_DATA2                            0x00D0 0x0340 0x0000 0x4 0x0
+#define MX7D_PAD_LCD_DATA02__GPIO3_IO7                            0x00D0 0x0340 0x0000 0x5 0x0
+#define MX7D_PAD_LCD_DATA02__SRC_BOOT_CFG2                        0x00D0 0x0340 0x0000 0x6 0x0
+#define MX7D_PAD_LCD_DATA03__LCD_DATA3                            0x00D4 0x0344 0x0644 0x0 0x2
+#define MX7D_PAD_LCD_DATA03__GPT1_CAPTURE1                        0x00D4 0x0344 0x0000 0x1 0x0
+#define MX7D_PAD_LCD_DATA03__CSI_DATA23                           0x00D4 0x0344 0x0000 0x3 0x0
+#define MX7D_PAD_LCD_DATA03__EIM_DATA3                            0x00D4 0x0344 0x0000 0x4 0x0
+#define MX7D_PAD_LCD_DATA03__GPIO3_IO8                            0x00D4 0x0344 0x0000 0x5 0x0
+#define MX7D_PAD_LCD_DATA03__SRC_BOOT_CFG3                        0x00D4 0x0344 0x0000 0x6 0x0
+#define MX7D_PAD_LCD_DATA04__LCD_DATA4                            0x00D8 0x0348 0x0648 0x0 0x2
+#define MX7D_PAD_LCD_DATA04__GPT1_CAPTURE2                        0x00D8 0x0348 0x0000 0x1 0x0
+#define MX7D_PAD_LCD_DATA04__CSI_VSYNC                            0x00D8 0x0348 0x0520 0x3 0x0
+#define MX7D_PAD_LCD_DATA04__EIM_DATA4                            0x00D8 0x0348 0x0000 0x4 0x0
+#define MX7D_PAD_LCD_DATA04__GPIO3_IO9                            0x00D8 0x0348 0x0000 0x5 0x0
+#define MX7D_PAD_LCD_DATA04__SRC_BOOT_CFG4                        0x00D8 0x0348 0x0000 0x6 0x0
+#define MX7D_PAD_LCD_DATA05__LCD_DATA5                            0x00DC 0x034C 0x064C 0x0 0x2
+#define MX7D_PAD_LCD_DATA05__CSI_HSYNC                            0x00DC 0x034C 0x0518 0x3 0x0
+#define MX7D_PAD_LCD_DATA05__EIM_DATA5                            0x00DC 0x034C 0x0000 0x4 0x0
+#define MX7D_PAD_LCD_DATA05__GPIO3_IO10                           0x00DC 0x034C 0x0000 0x5 0x0
+#define MX7D_PAD_LCD_DATA05__SRC_BOOT_CFG5                        0x00DC 0x034C 0x0000 0x6 0x0
+#define MX7D_PAD_LCD_DATA06__LCD_DATA6                            0x00E0 0x0350 0x0650 0x0 0x2
+#define MX7D_PAD_LCD_DATA06__CSI_PIXCLK                           0x00E0 0x0350 0x051C 0x3 0x0
+#define MX7D_PAD_LCD_DATA06__EIM_DATA6                            0x00E0 0x0350 0x0000 0x4 0x0
+#define MX7D_PAD_LCD_DATA06__GPIO3_IO11                           0x00E0 0x0350 0x0000 0x5 0x0
+#define MX7D_PAD_LCD_DATA06__SRC_BOOT_CFG6                        0x00E0 0x0350 0x0000 0x6 0x0
+#define MX7D_PAD_LCD_DATA07__LCD_DATA7                            0x00E4 0x0354 0x0654 0x0 0x2
+#define MX7D_PAD_LCD_DATA07__CSI_MCLK                             0x00E4 0x0354 0x0000 0x3 0x0
+#define MX7D_PAD_LCD_DATA07__EIM_DATA7                            0x00E4 0x0354 0x0000 0x4 0x0
+#define MX7D_PAD_LCD_DATA07__GPIO3_IO12                           0x00E4 0x0354 0x0000 0x5 0x0
+#define MX7D_PAD_LCD_DATA07__SRC_BOOT_CFG7                        0x00E4 0x0354 0x0000 0x6 0x0
+#define MX7D_PAD_LCD_DATA08__LCD_DATA8                            0x00E8 0x0358 0x0658 0x0 0x2
+#define MX7D_PAD_LCD_DATA08__CSI_DATA9                            0x00E8 0x0358 0x0514 0x3 0x0
+#define MX7D_PAD_LCD_DATA08__EIM_DATA8                            0x00E8 0x0358 0x0000 0x4 0x0
+#define MX7D_PAD_LCD_DATA08__GPIO3_IO13                           0x00E8 0x0358 0x0000 0x5 0x0
+#define MX7D_PAD_LCD_DATA08__SRC_BOOT_CFG8                        0x00E8 0x0358 0x0000 0x6 0x0
+#define MX7D_PAD_LCD_DATA09__LCD_DATA9                            0x00EC 0x035C 0x065C 0x0 0x2
+#define MX7D_PAD_LCD_DATA09__CSI_DATA8                            0x00EC 0x035C 0x0510 0x3 0x0
+#define MX7D_PAD_LCD_DATA09__EIM_DATA9                            0x00EC 0x035C 0x0000 0x4 0x0
+#define MX7D_PAD_LCD_DATA09__GPIO3_IO14                           0x00EC 0x035C 0x0000 0x5 0x0
+#define MX7D_PAD_LCD_DATA09__SRC_BOOT_CFG9                        0x00EC 0x035C 0x0000 0x6 0x0
+#define MX7D_PAD_LCD_DATA10__LCD_DATA10                           0x00F0 0x0360 0x0660 0x0 0x2
+#define MX7D_PAD_LCD_DATA10__CSI_DATA7                            0x00F0 0x0360 0x050C 0x3 0x0
+#define MX7D_PAD_LCD_DATA10__EIM_DATA10                           0x00F0 0x0360 0x0000 0x4 0x0
+#define MX7D_PAD_LCD_DATA10__GPIO3_IO15                           0x00F0 0x0360 0x0000 0x5 0x0
+#define MX7D_PAD_LCD_DATA10__SRC_BOOT_CFG10                       0x00F0 0x0360 0x0000 0x6 0x0
+#define MX7D_PAD_LCD_DATA11__LCD_DATA11                           0x00F4 0x0364 0x0664 0x0 0x2
+#define MX7D_PAD_LCD_DATA11__CSI_DATA6                            0x00F4 0x0364 0x0508 0x3 0x0
+#define MX7D_PAD_LCD_DATA11__EIM_DATA11                           0x00F4 0x0364 0x0000 0x4 0x0
+#define MX7D_PAD_LCD_DATA11__GPIO3_IO16                           0x00F4 0x0364 0x0000 0x5 0x0
+#define MX7D_PAD_LCD_DATA11__SRC_BOOT_CFG11                       0x00F4 0x0364 0x0000 0x6 0x0
+#define MX7D_PAD_LCD_DATA12__LCD_DATA12                           0x00F8 0x0368 0x0668 0x0 0x2
+#define MX7D_PAD_LCD_DATA12__CSI_DATA5                            0x00F8 0x0368 0x0504 0x3 0x0
+#define MX7D_PAD_LCD_DATA12__EIM_DATA12                           0x00F8 0x0368 0x0000 0x4 0x0
+#define MX7D_PAD_LCD_DATA12__GPIO3_IO17                           0x00F8 0x0368 0x0000 0x5 0x0
+#define MX7D_PAD_LCD_DATA12__SRC_BOOT_CFG12                       0x00F8 0x0368 0x0000 0x6 0x0
+#define MX7D_PAD_LCD_DATA13__LCD_DATA13                           0x00FC 0x036C 0x066C 0x0 0x1
+#define MX7D_PAD_LCD_DATA13__CSI_DATA4                            0x00FC 0x036C 0x0500 0x3 0x0
+#define MX7D_PAD_LCD_DATA13__EIM_DATA13                           0x00FC 0x036C 0x0000 0x4 0x0
+#define MX7D_PAD_LCD_DATA13__GPIO3_IO18                           0x00FC 0x036C 0x0000 0x5 0x0
+#define MX7D_PAD_LCD_DATA13__SRC_BOOT_CFG13                       0x00FC 0x036C 0x0000 0x6 0x0
+#define MX7D_PAD_LCD_DATA14__LCD_DATA14                           0x0100 0x0370 0x0670 0x0 0x1
+#define MX7D_PAD_LCD_DATA14__CSI_DATA3                            0x0100 0x0370 0x04FC 0x3 0x0
+#define MX7D_PAD_LCD_DATA14__EIM_DATA14                           0x0100 0x0370 0x0000 0x4 0x0
+#define MX7D_PAD_LCD_DATA14__GPIO3_IO19                           0x0100 0x0370 0x0000 0x5 0x0
+#define MX7D_PAD_LCD_DATA14__SRC_BOOT_CFG14                       0x0100 0x0370 0x0000 0x6 0x0
+#define MX7D_PAD_LCD_DATA15__LCD_DATA15                           0x0104 0x0374 0x0674 0x0 0x1
+#define MX7D_PAD_LCD_DATA15__CSI_DATA2                            0x0104 0x0374 0x04F8 0x3 0x0
+#define MX7D_PAD_LCD_DATA15__EIM_DATA15                           0x0104 0x0374 0x0000 0x4 0x0
+#define MX7D_PAD_LCD_DATA15__GPIO3_IO20                           0x0104 0x0374 0x0000 0x5 0x0
+#define MX7D_PAD_LCD_DATA15__SRC_BOOT_CFG15                       0x0104 0x0374 0x0000 0x6 0x0
+#define MX7D_PAD_LCD_DATA16__LCD_DATA16                           0x0108 0x0378 0x0678 0x0 0x2
+#define MX7D_PAD_LCD_DATA16__FLEXTIMER1_CH4                       0x0108 0x0378 0x0594 0x1 0x0
+#define MX7D_PAD_LCD_DATA16__CSI_DATA1                            0x0108 0x0378 0x0000 0x3 0x0
+#define MX7D_PAD_LCD_DATA16__EIM_CRE                              0x0108 0x0378 0x0000 0x4 0x0
+#define MX7D_PAD_LCD_DATA16__GPIO3_IO21                           0x0108 0x0378 0x0000 0x5 0x0
+#define MX7D_PAD_LCD_DATA16__SRC_BOOT_CFG16                       0x0108 0x0378 0x0000 0x6 0x0
+#define MX7D_PAD_LCD_DATA17__LCD_DATA17                           0x010C 0x037C 0x067C 0x0 0x2
+#define MX7D_PAD_LCD_DATA17__FLEXTIMER1_CH5                       0x010C 0x037C 0x0598 0x1 0x0
+#define MX7D_PAD_LCD_DATA17__CSI_DATA0                            0x010C 0x037C 0x0000 0x3 0x0
+#define MX7D_PAD_LCD_DATA17__EIM_ACLK_FREERUN                     0x010C 0x037C 0x0000 0x4 0x0
+#define MX7D_PAD_LCD_DATA17__GPIO3_IO22                           0x010C 0x037C 0x0000 0x5 0x0
+#define MX7D_PAD_LCD_DATA17__SRC_BOOT_CFG17                       0x010C 0x037C 0x0000 0x6 0x0
+#define MX7D_PAD_LCD_DATA18__LCD_DATA18                           0x0110 0x0380 0x0680 0x0 0x2
+#define MX7D_PAD_LCD_DATA18__FLEXTIMER1_CH6                       0x0110 0x0380 0x059C 0x1 0x0
+#define MX7D_PAD_LCD_DATA18__ARM_PLATFORM_EVENTO                  0x0110 0x0380 0x0000 0x2 0x0
+#define MX7D_PAD_LCD_DATA18__CSI_DATA15                           0x0110 0x0380 0x0000 0x3 0x0
+#define MX7D_PAD_LCD_DATA18__EIM_CS2_B                            0x0110 0x0380 0x0000 0x4 0x0
+#define MX7D_PAD_LCD_DATA18__GPIO3_IO23                           0x0110 0x0380 0x0000 0x5 0x0
+#define MX7D_PAD_LCD_DATA18__SRC_BOOT_CFG18                       0x0110 0x0380 0x0000 0x6 0x0
+#define MX7D_PAD_LCD_DATA19__EIM_CS3_B                            0x0114 0x0384 0x0000 0x4 0x0
+#define MX7D_PAD_LCD_DATA19__GPIO3_IO24                           0x0114 0x0384 0x0000 0x5 0x0
+#define MX7D_PAD_LCD_DATA19__SRC_BOOT_CFG19                       0x0114 0x0384 0x0000 0x6 0x0
+#define MX7D_PAD_LCD_DATA19__LCD_DATA19                           0x0114 0x0384 0x0684 0x0 0x2
+#define MX7D_PAD_LCD_DATA19__FLEXTIMER1_CH7                       0x0114 0x0384 0x05A0 0x1 0x0
+#define MX7D_PAD_LCD_DATA19__CSI_DATA14                           0x0114 0x0384 0x0000 0x3 0x0
+#define MX7D_PAD_LCD_DATA20__EIM_ADDR23                           0x0118 0x0388 0x0000 0x4 0x0
+#define MX7D_PAD_LCD_DATA20__GPIO3_IO25                           0x0118 0x0388 0x0000 0x5 0x0
+#define MX7D_PAD_LCD_DATA20__I2C3_SCL                             0x0118 0x0388 0x05E4 0x6 0x1
+#define MX7D_PAD_LCD_DATA20__LCD_DATA20                           0x0118 0x0388 0x0688 0x0 0x2
+#define MX7D_PAD_LCD_DATA20__FLEXTIMER2_CH4                       0x0118 0x0388 0x05BC 0x1 0x0
+#define MX7D_PAD_LCD_DATA20__ENET1_1588_EVENT2_OUT                0x0118 0x0388 0x0000 0x2 0x0
+#define MX7D_PAD_LCD_DATA20__CSI_DATA13                           0x0118 0x0388 0x0000 0x3 0x0
+#define MX7D_PAD_LCD_DATA21__LCD_DATA21                           0x011C 0x038C 0x068C 0x0 0x2
+#define MX7D_PAD_LCD_DATA21__FLEXTIMER2_CH5                       0x011C 0x038C 0x05C0 0x1 0x0
+#define MX7D_PAD_LCD_DATA21__ENET1_1588_EVENT3_OUT                0x011C 0x038C 0x0000 0x2 0x0
+#define MX7D_PAD_LCD_DATA21__CSI_DATA12                           0x011C 0x038C 0x0000 0x3 0x0
+#define MX7D_PAD_LCD_DATA21__EIM_ADDR24                           0x011C 0x038C 0x0000 0x4 0x0
+#define MX7D_PAD_LCD_DATA21__GPIO3_IO26                           0x011C 0x038C 0x0000 0x5 0x0
+#define MX7D_PAD_LCD_DATA21__I2C3_SDA                             0x011C 0x038C 0x05E8 0x6 0x1
+#define MX7D_PAD_LCD_DATA22__LCD_DATA22                           0x0120 0x0390 0x0690 0x0 0x2
+#define MX7D_PAD_LCD_DATA22__FLEXTIMER2_CH6                       0x0120 0x0390 0x05C4 0x1 0x0
+#define MX7D_PAD_LCD_DATA22__ENET2_1588_EVENT2_OUT                0x0120 0x0390 0x0000 0x2 0x0
+#define MX7D_PAD_LCD_DATA22__CSI_DATA11                           0x0120 0x0390 0x0000 0x3 0x0
+#define MX7D_PAD_LCD_DATA22__EIM_ADDR25                           0x0120 0x0390 0x0000 0x4 0x0
+#define MX7D_PAD_LCD_DATA22__GPIO3_IO27                           0x0120 0x0390 0x0000 0x5 0x0
+#define MX7D_PAD_LCD_DATA22__I2C4_SCL                             0x0120 0x0390 0x05EC 0x6 0x1
+#define MX7D_PAD_LCD_DATA23__LCD_DATA23                           0x0124 0x0394 0x0694 0x0 0x2
+#define MX7D_PAD_LCD_DATA23__FLEXTIMER2_CH7                       0x0124 0x0394 0x05C8 0x1 0x0
+#define MX7D_PAD_LCD_DATA23__ENET2_1588_EVENT3_OUT                0x0124 0x0394 0x0000 0x2 0x0
+#define MX7D_PAD_LCD_DATA23__CSI_DATA10                           0x0124 0x0394 0x0000 0x3 0x0
+#define MX7D_PAD_LCD_DATA23__EIM_ADDR26                           0x0124 0x0394 0x0000 0x4 0x0
+#define MX7D_PAD_LCD_DATA23__GPIO3_IO28                           0x0124 0x0394 0x0000 0x5 0x0
+#define MX7D_PAD_LCD_DATA23__I2C4_SDA                             0x0124 0x0394 0x05F0 0x6 0x1
+#define MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX                      0x0128 0x0398 0x06F4 0x0 0x0
+#define MX7D_PAD_UART1_RX_DATA__UART1_DTE_TX                      0x0128 0x0398 0x0000 0x0 0x0
+#define MX7D_PAD_UART1_RX_DATA__I2C1_SCL                          0x0128 0x0398 0x05D4 0x1 0x0
+#define MX7D_PAD_UART1_RX_DATA__CCM_PMIC_READY                    0x0128 0x0398 0x0000 0x2 0x0
+#define MX7D_PAD_UART1_RX_DATA__ECSPI1_SS1                        0x0128 0x0398 0x0000 0x3 0x0
+#define MX7D_PAD_UART1_RX_DATA__ENET2_1588_EVENT0_IN              0x0128 0x0398 0x0000 0x4 0x0
+#define MX7D_PAD_UART1_RX_DATA__GPIO4_IO0                         0x0128 0x0398 0x0000 0x5 0x0
+#define MX7D_PAD_UART1_RX_DATA__ENET1_MDIO                        0x0128 0x0398 0x0000 0x6 0x0
+#define MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX                      0x012C 0x039C 0x0000 0x0 0x0
+#define MX7D_PAD_UART1_TX_DATA__UART1_DTE_RX                      0x012C 0x039C 0x06F4 0x0 0x1
+#define MX7D_PAD_UART1_TX_DATA__I2C1_SDA                          0x012C 0x039C 0x05D8 0x1 0x0
+#define MX7D_PAD_UART1_TX_DATA__SAI3_MCLK                         0x012C 0x039C 0x0000 0x2 0x0
+#define MX7D_PAD_UART1_TX_DATA__ECSPI1_SS2                        0x012C 0x039C 0x0000 0x3 0x0
+#define MX7D_PAD_UART1_TX_DATA__ENET2_1588_EVENT0_OUT             0x012C 0x039C 0x0000 0x4 0x0
+#define MX7D_PAD_UART1_TX_DATA__GPIO4_IO1                         0x012C 0x039C 0x0000 0x5 0x0
+#define MX7D_PAD_UART1_TX_DATA__ENET1_MDC                         0x012C 0x039C 0x0000 0x6 0x0
+#define MX7D_PAD_UART2_RX_DATA__UART2_DCE_RX                      0x0130 0x03A0 0x06FC 0x0 0x2
+#define MX7D_PAD_UART2_RX_DATA__UART2_DTE_TX                      0x0130 0x03A0 0x0000 0x0 0x0
+#define MX7D_PAD_UART2_RX_DATA__I2C2_SCL                          0x0130 0x03A0 0x05DC 0x1 0x0
+#define MX7D_PAD_UART2_RX_DATA__SAI3_RX_BCLK                      0x0130 0x03A0 0x06C4 0x2 0x0
+#define MX7D_PAD_UART2_RX_DATA__ECSPI1_SS3                        0x0130 0x03A0 0x0000 0x3 0x0
+#define MX7D_PAD_UART2_RX_DATA__ENET2_1588_EVENT1_IN              0x0130 0x03A0 0x0000 0x4 0x0
+#define MX7D_PAD_UART2_RX_DATA__GPIO4_IO2                         0x0130 0x03A0 0x0000 0x5 0x0
+#define MX7D_PAD_UART2_RX_DATA__ENET2_MDIO                        0x0130 0x03A0 0x0000 0x6 0x0
+#define MX7D_PAD_UART2_TX_DATA__UART2_DCE_TX                      0x0134 0x03A4 0x0000 0x0 0x0
+#define MX7D_PAD_UART2_TX_DATA__UART2_DTE_RX                      0x0134 0x03A4 0x06FC 0x0 0x3
+#define MX7D_PAD_UART2_TX_DATA__I2C2_SDA                          0x0134 0x03A4 0x05E0 0x1 0x0
+#define MX7D_PAD_UART2_TX_DATA__SAI3_RX_DATA0                     0x0134 0x03A4 0x06C8 0x2 0x0
+#define MX7D_PAD_UART2_TX_DATA__ECSPI1_RDY                        0x0134 0x03A4 0x0000 0x3 0x0
+#define MX7D_PAD_UART2_TX_DATA__ENET2_1588_EVENT1_OUT             0x0134 0x03A4 0x0000 0x4 0x0
+#define MX7D_PAD_UART2_TX_DATA__GPIO4_IO3                         0x0134 0x03A4 0x0000 0x5 0x0
+#define MX7D_PAD_UART2_TX_DATA__ENET2_MDC                         0x0134 0x03A4 0x0000 0x6 0x0
+#define MX7D_PAD_UART3_RX_DATA__UART3_DCE_RX                      0x0138 0x03A8 0x0704 0x0 0x2
+#define MX7D_PAD_UART3_RX_DATA__UART3_DTE_TX                      0x0138 0x03A8 0x0000 0x0 0x0
+#define MX7D_PAD_UART3_RX_DATA__USB_OTG1_OC                       0x0138 0x03A8 0x072C 0x1 0x0
+#define MX7D_PAD_UART3_RX_DATA__SAI3_RX_SYNC                      0x0138 0x03A8 0x06CC 0x2 0x0
+#define MX7D_PAD_UART3_RX_DATA__ECSPI1_MISO                       0x0138 0x03A8 0x0528 0x3 0x0
+#define MX7D_PAD_UART3_RX_DATA__ENET1_1588_EVENT0_IN              0x0138 0x03A8 0x0000 0x4 0x0
+#define MX7D_PAD_UART3_RX_DATA__GPIO4_IO4                         0x0138 0x03A8 0x0000 0x5 0x0
+#define MX7D_PAD_UART3_RX_DATA__SD1_LCTL                          0x0138 0x03A8 0x0000 0x6 0x0
+#define MX7D_PAD_UART3_TX_DATA__UART3_DCE_TX                      0x013C 0x03AC 0x0000 0x0 0x0
+#define MX7D_PAD_UART3_TX_DATA__UART3_DTE_RX                      0x013C 0x03AC 0x0704 0x0 0x3
+#define MX7D_PAD_UART3_TX_DATA__USB_OTG1_PWR                      0x013C 0x03AC 0x0000 0x1 0x0
+#define MX7D_PAD_UART3_TX_DATA__SAI3_TX_BCLK                      0x013C 0x03AC 0x06D0 0x2 0x0
+#define MX7D_PAD_UART3_TX_DATA__ECSPI1_MOSI                       0x013C 0x03AC 0x052C 0x3 0x0
+#define MX7D_PAD_UART3_TX_DATA__ENET1_1588_EVENT0_OUT             0x013C 0x03AC 0x0000 0x4 0x0
+#define MX7D_PAD_UART3_TX_DATA__GPIO4_IO5                         0x013C 0x03AC 0x0000 0x5 0x0
+#define MX7D_PAD_UART3_TX_DATA__SD2_LCTL                          0x013C 0x03AC 0x0000 0x6 0x0
+#define MX7D_PAD_UART3_RTS_B__UART3_DCE_RTS                       0x0140 0x03B0 0x0700 0x0 0x2
+#define MX7D_PAD_UART3_RTS_B__UART3_DTE_CTS                       0x0140 0x03B0 0x0000 0x0 0x0
+#define MX7D_PAD_UART3_RTS_B__USB_OTG2_OC                         0x0140 0x03B0 0x0728 0x1 0x0
+#define MX7D_PAD_UART3_RTS_B__SAI3_TX_DATA0                       0x0140 0x03B0 0x0000 0x2 0x0
+#define MX7D_PAD_UART3_RTS_B__ECSPI1_SCLK                         0x0140 0x03B0 0x0000 0x3 0x0
+#define MX7D_PAD_UART3_RTS_B__ENET1_1588_EVENT1_IN                0x0140 0x03B0 0x0000 0x4 0x0
+#define MX7D_PAD_UART3_RTS_B__GPIO4_IO6                           0x0140 0x03B0 0x0000 0x5 0x0
+#define MX7D_PAD_UART3_RTS_B__SD3_LCTL                            0x0140 0x03B0 0x0000 0x6 0x0
+#define MX7D_PAD_UART3_CTS_B__UART3_DCE_CTS                       0x0144 0x03B4 0x0000 0x0 0x0
+#define MX7D_PAD_UART3_CTS_B__UART3_DTE_RTS                       0x0144 0x03B4 0x0700 0x0 0x3
+#define MX7D_PAD_UART3_CTS_B__USB_OTG2_PWR                        0x0144 0x03B4 0x0000 0x1 0x0
+#define MX7D_PAD_UART3_CTS_B__SAI3_TX_SYNC                        0x0144 0x03B4 0x06D4 0x2 0x0
+#define MX7D_PAD_UART3_CTS_B__ECSPI1_SS0                          0x0144 0x03B4 0x0530 0x3 0x0
+#define MX7D_PAD_UART3_CTS_B__ENET1_1588_EVENT1_OUT               0x0144 0x03B4 0x0000 0x4 0x0
+#define MX7D_PAD_UART3_CTS_B__GPIO4_IO7                           0x0144 0x03B4 0x0000 0x5 0x0
+#define MX7D_PAD_UART3_CTS_B__SD1_VSELECT                         0x0144 0x03B4 0x0000 0x6 0x0
+#define MX7D_PAD_I2C1_SCL__I2C1_SCL                               0x0148 0x03B8 0x05D4 0x0 0x1
+#define MX7D_PAD_I2C1_SCL__UART4_DCE_CTS                          0x0148 0x03B8 0x0000 0x1 0x0
+#define MX7D_PAD_I2C1_SCL__UART4_DTE_RTS                          0x0148 0x03B8 0x0708 0x1 0x0
+#define MX7D_PAD_I2C1_SCL__FLEXCAN1_RX                            0x0148 0x03B8 0x04DC 0x2 0x1
+#define MX7D_PAD_I2C1_SCL__ECSPI3_MISO                            0x0148 0x03B8 0x0548 0x3 0x0
+#define MX7D_PAD_I2C1_SCL__GPIO4_IO8                              0x0148 0x03B8 0x0000 0x5 0x0
+#define MX7D_PAD_I2C1_SCL__SD2_VSELECT                            0x0148 0x03B8 0x0000 0x6 0x0
+#define MX7D_PAD_I2C1_SDA__I2C1_SDA                               0x014C 0x03BC 0x05D8 0x0 0x1
+#define MX7D_PAD_I2C1_SDA__UART4_DCE_RTS                          0x014C 0x03BC 0x0708 0x1 0x1
+#define MX7D_PAD_I2C1_SDA__UART4_DTE_CTS                          0x014C 0x03BC 0x0000 0x1 0x0
+#define MX7D_PAD_I2C1_SDA__FLEXCAN1_TX                            0x014C 0x03BC 0x0000 0x2 0x0
+#define MX7D_PAD_I2C1_SDA__ECSPI3_MOSI                            0x014C 0x03BC 0x054C 0x3 0x0
+#define MX7D_PAD_I2C1_SDA__CCM_ENET_REF_CLK1                      0x014C 0x03BC 0x0564 0x4 0x1
+#define MX7D_PAD_I2C1_SDA__GPIO4_IO9                              0x014C 0x03BC 0x0000 0x5 0x0
+#define MX7D_PAD_I2C1_SDA__SD3_VSELECT                            0x014C 0x03BC 0x0000 0x6 0x0
+#define MX7D_PAD_I2C2_SCL__I2C2_SCL                               0x0150 0x03C0 0x05DC 0x0 0x1
+#define MX7D_PAD_I2C2_SCL__UART4_DCE_RX                           0x0150 0x03C0 0x070C 0x1 0x0
+#define MX7D_PAD_I2C2_SCL__UART4_DTE_TX                           0x0150 0x03C0 0x0000 0x1 0x0
+#define MX7D_PAD_I2C2_SCL__WDOG3_WDOG_B                           0x0150 0x03C0 0x0000 0x2 0x0
+#define MX7D_PAD_I2C2_SCL__ECSPI3_SCLK                            0x0150 0x03C0 0x0544 0x3 0x0
+#define MX7D_PAD_I2C2_SCL__CCM_ENET_REF_CLK2                      0x0150 0x03C0 0x0570 0x4 0x2
+#define MX7D_PAD_I2C2_SCL__GPIO4_IO10                             0x0150 0x03C0 0x0000 0x5 0x0
+#define MX7D_PAD_I2C2_SCL__SD3_CD_B                               0x0150 0x03C0 0x0738 0x6 0x1
+#define MX7D_PAD_I2C2_SDA__I2C2_SDA                               0x0154 0x03C4 0x05E0 0x0 0x1
+#define MX7D_PAD_I2C2_SDA__UART4_DCE_TX                           0x0154 0x03C4 0x0000 0x1 0x0
+#define MX7D_PAD_I2C2_SDA__UART4_DTE_RX                           0x0154 0x03C4 0x070C 0x1 0x1
+#define MX7D_PAD_I2C2_SDA__WDOG3_WDOG_RST_B_DEB                   0x0154 0x03C4 0x0000 0x2 0x0
+#define MX7D_PAD_I2C2_SDA__ECSPI3_SS0                             0x0154 0x03C4 0x0550 0x3 0x0
+#define MX7D_PAD_I2C2_SDA__CCM_ENET_REF_CLK3                      0x0154 0x03C4 0x0000 0x4 0x0
+#define MX7D_PAD_I2C2_SDA__GPIO4_IO11                             0x0154 0x03C4 0x0000 0x5 0x0
+#define MX7D_PAD_I2C2_SDA__SD3_WP                                 0x0154 0x03C4 0x073C 0x6 0x1
+#define MX7D_PAD_I2C3_SCL__I2C3_SCL                               0x0158 0x03C8 0x05E4 0x0 0x2
+#define MX7D_PAD_I2C3_SCL__UART5_DCE_CTS                          0x0158 0x03C8 0x0000 0x1 0x0
+#define MX7D_PAD_I2C3_SCL__UART5_DTE_RTS                          0x0158 0x03C8 0x0710 0x1 0x0
+#define MX7D_PAD_I2C3_SCL__FLEXCAN2_RX                            0x0158 0x03C8 0x04E0 0x2 0x1
+#define MX7D_PAD_I2C3_SCL__CSI_VSYNC                              0x0158 0x03C8 0x0520 0x3 0x1
+#define MX7D_PAD_I2C3_SCL__SDMA_EXT_EVENT0                        0x0158 0x03C8 0x06D8 0x4 0x1
+#define MX7D_PAD_I2C3_SCL__GPIO4_IO12                             0x0158 0x03C8 0x0000 0x5 0x0
+#define MX7D_PAD_I2C3_SCL__EPDC_BDR0                              0x0158 0x03C8 0x0000 0x6 0x0
+#define MX7D_PAD_I2C3_SDA__I2C3_SDA                               0x015C 0x03CC 0x05E8 0x0 0x2
+#define MX7D_PAD_I2C3_SDA__UART5_DCE_RTS                          0x015C 0x03CC 0x0710 0x1 0x1
+#define MX7D_PAD_I2C3_SDA__UART5_DTE_CTS                          0x015C 0x03CC 0x0000 0x1 0x0
+#define MX7D_PAD_I2C3_SDA__FLEXCAN2_TX                            0x015C 0x03CC 0x0000 0x2 0x0
+#define MX7D_PAD_I2C3_SDA__CSI_HSYNC                              0x015C 0x03CC 0x0518 0x3 0x1
+#define MX7D_PAD_I2C3_SDA__SDMA_EXT_EVENT1                        0x015C 0x03CC 0x06DC 0x4 0x1
+#define MX7D_PAD_I2C3_SDA__GPIO4_IO13                             0x015C 0x03CC 0x0000 0x5 0x0
+#define MX7D_PAD_I2C3_SDA__EPDC_BDR1                              0x015C 0x03CC 0x0000 0x6 0x0
+#define MX7D_PAD_I2C4_SCL__I2C4_SCL                               0x0160 0x03D0 0x05EC 0x0 0x2
+#define MX7D_PAD_I2C4_SCL__UART5_DCE_RX                           0x0160 0x03D0 0x0714 0x1 0x0
+#define MX7D_PAD_I2C4_SCL__UART5_DTE_TX                           0x0160 0x03D0 0x0000 0x1 0x0
+#define MX7D_PAD_I2C4_SCL__WDOG4_WDOG_B                           0x0160 0x03D0 0x0000 0x2 0x0
+#define MX7D_PAD_I2C4_SCL__CSI_PIXCLK                             0x0160 0x03D0 0x051C 0x3 0x1
+#define MX7D_PAD_I2C4_SCL__USB_OTG1_ID                            0x0160 0x03D0 0x0734 0x4 0x1
+#define MX7D_PAD_I2C4_SCL__GPIO4_IO14                             0x0160 0x03D0 0x0000 0x5 0x0
+#define MX7D_PAD_I2C4_SCL__EPDC_VCOM0                             0x0160 0x03D0 0x0000 0x6 0x0
+#define MX7D_PAD_I2C4_SDA__I2C4_SDA                               0x0164 0x03D4 0x05F0 0x0 0x2
+#define MX7D_PAD_I2C4_SDA__UART5_DCE_TX                           0x0164 0x03D4 0x0000 0x1 0x0
+#define MX7D_PAD_I2C4_SDA__UART5_DTE_RX                           0x0164 0x03D4 0x0714 0x1 0x1
+#define MX7D_PAD_I2C4_SDA__WDOG4_WDOG_RST_B_DEB                   0x0164 0x03D4 0x0000 0x2 0x0
+#define MX7D_PAD_I2C4_SDA__CSI_MCLK                               0x0164 0x03D4 0x0000 0x3 0x0
+#define MX7D_PAD_I2C4_SDA__USB_OTG2_ID                            0x0164 0x03D4 0x0730 0x4 0x1
+#define MX7D_PAD_I2C4_SDA__GPIO4_IO15                             0x0164 0x03D4 0x0000 0x5 0x0
+#define MX7D_PAD_I2C4_SDA__EPDC_VCOM1                             0x0164 0x03D4 0x0000 0x6 0x0
+#define MX7D_PAD_ECSPI1_SCLK__ECSPI1_SCLK                         0x0168 0x03D8 0x0524 0x0 0x1
+#define MX7D_PAD_ECSPI1_SCLK__UART6_DCE_RX                        0x0168 0x03D8 0x071C 0x1 0x2
+#define MX7D_PAD_ECSPI1_SCLK__UART6_DTE_TX                        0x0168 0x03D8 0x0000 0x1 0x0
+#define MX7D_PAD_ECSPI1_SCLK__SD2_DATA4                           0x0168 0x03D8 0x0000 0x2 0x0
+#define MX7D_PAD_ECSPI1_SCLK__CSI_DATA2                           0x0168 0x03D8 0x04F8 0x3 0x1
+#define MX7D_PAD_ECSPI1_SCLK__GPIO4_IO16                          0x0168 0x03D8 0x0000 0x5 0x0
+#define MX7D_PAD_ECSPI1_SCLK__EPDC_PWR_COM                        0x0168 0x03D8 0x0000 0x6 0x0
+#define MX7D_PAD_ECSPI1_MOSI__ECSPI1_MOSI                         0x016C 0x03DC 0x052C 0x0 0x1
+#define MX7D_PAD_ECSPI1_MOSI__UART6_DCE_TX                        0x016C 0x03DC 0x0000 0x1 0x0
+#define MX7D_PAD_ECSPI1_MOSI__UART6_DTE_RX                        0x016C 0x03DC 0x071C 0x1 0x3
+#define MX7D_PAD_ECSPI1_MOSI__SD2_DATA5                           0x016C 0x03DC 0x0000 0x2 0x0
+#define MX7D_PAD_ECSPI1_MOSI__CSI_DATA3                           0x016C 0x03DC 0x04FC 0x3 0x1
+#define MX7D_PAD_ECSPI1_MOSI__GPIO4_IO17                          0x016C 0x03DC 0x0000 0x5 0x0
+#define MX7D_PAD_ECSPI1_MOSI__EPDC_PWR_STAT                       0x016C 0x03DC 0x0580 0x6 0x1
+#define MX7D_PAD_ECSPI1_MISO__ECSPI1_MISO                         0x0170 0x03E0 0x0528 0x0 0x1
+#define MX7D_PAD_ECSPI1_MISO__UART6_DCE_RTS                       0x0170 0x03E0 0x0718 0x1 0x2
+#define MX7D_PAD_ECSPI1_MISO__UART6_DTE_CTS                       0x0170 0x03E0 0x0000 0x1 0x0
+#define MX7D_PAD_ECSPI1_MISO__SD2_DATA6                           0x0170 0x03E0 0x0000 0x2 0x0
+#define MX7D_PAD_ECSPI1_MISO__CSI_DATA4                           0x0170 0x03E0 0x0500 0x3 0x1
+#define MX7D_PAD_ECSPI1_MISO__GPIO4_IO18                          0x0170 0x03E0 0x0000 0x5 0x0
+#define MX7D_PAD_ECSPI1_MISO__EPDC_PWR_IRQ                        0x0170 0x03E0 0x057C 0x6 0x0
+#define MX7D_PAD_ECSPI1_SS0__ECSPI1_SS0                           0x0174 0x03E4 0x0530 0x0 0x1
+#define MX7D_PAD_ECSPI1_SS0__UART6_DCE_CTS                        0x0174 0x03E4 0x0000 0x1 0x0
+#define MX7D_PAD_ECSPI1_SS0__UART6_DTE_RTS                        0x0174 0x03E4 0x0718 0x1 0x3
+#define MX7D_PAD_ECSPI1_SS0__SD2_DATA7                            0x0174 0x03E4 0x0000 0x2 0x0
+#define MX7D_PAD_ECSPI1_SS0__CSI_DATA5                            0x0174 0x03E4 0x0504 0x3 0x1
+#define MX7D_PAD_ECSPI1_SS0__GPIO4_IO19                           0x0174 0x03E4 0x0000 0x5 0x0
+#define MX7D_PAD_ECSPI1_SS0__EPDC_PWR_CTRL3                       0x0174 0x03E4 0x0000 0x6 0x0
+#define MX7D_PAD_ECSPI2_SCLK__ECSPI2_SCLK                         0x0178 0x03E8 0x0534 0x0 0x0
+#define MX7D_PAD_ECSPI2_SCLK__UART7_DCE_RX                        0x0178 0x03E8 0x0724 0x1 0x2
+#define MX7D_PAD_ECSPI2_SCLK__UART7_DTE_TX                        0x0178 0x03E8 0x0000 0x1 0x0
+#define MX7D_PAD_ECSPI2_SCLK__SD1_DATA4                           0x0178 0x03E8 0x0000 0x2 0x0
+#define MX7D_PAD_ECSPI2_SCLK__CSI_DATA6                           0x0178 0x03E8 0x0508 0x3 0x1
+#define MX7D_PAD_ECSPI2_SCLK__LCD_DATA13                          0x0178 0x03E8 0x066C 0x4 0x2
+#define MX7D_PAD_ECSPI2_SCLK__GPIO4_IO20                          0x0178 0x03E8 0x0000 0x5 0x0
+#define MX7D_PAD_ECSPI2_SCLK__EPDC_PWR_CTRL0                      0x0178 0x03E8 0x0000 0x6 0x0
+#define MX7D_PAD_ECSPI2_MOSI__ECSPI2_MOSI                         0x017C 0x03EC 0x053C 0x0 0x0
+#define MX7D_PAD_ECSPI2_MOSI__UART7_DCE_TX                        0x017C 0x03EC 0x0000 0x1 0x0
+#define MX7D_PAD_ECSPI2_MOSI__UART7_DTE_RX                        0x017C 0x03EC 0x0724 0x1 0x3
+#define MX7D_PAD_ECSPI2_MOSI__SD1_DATA5                           0x017C 0x03EC 0x0000 0x2 0x0
+#define MX7D_PAD_ECSPI2_MOSI__CSI_DATA7                           0x017C 0x03EC 0x050C 0x3 0x1
+#define MX7D_PAD_ECSPI2_MOSI__LCD_DATA14                          0x017C 0x03EC 0x0670 0x4 0x2
+#define MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21                          0x017C 0x03EC 0x0000 0x5 0x0
+#define MX7D_PAD_ECSPI2_MOSI__EPDC_PWR_CTRL1                      0x017C 0x03EC 0x0000 0x6 0x0
+#define MX7D_PAD_ECSPI2_MISO__GPIO4_IO22                          0x0180 0x03F0 0x0000 0x5 0x0
+#define MX7D_PAD_ECSPI2_MISO__EPDC_PWR_CTRL2                      0x0180 0x03F0 0x0000 0x6 0x0
+#define MX7D_PAD_ECSPI2_MISO__ECSPI2_MISO                         0x0180 0x03F0 0x0538 0x0 0x0
+#define MX7D_PAD_ECSPI2_MISO__UART7_DCE_RTS                       0x0180 0x03F0 0x0720 0x1 0x2
+#define MX7D_PAD_ECSPI2_MISO__UART7_DTE_CTS                       0x0180 0x03F0 0x0000 0x1 0x0
+#define MX7D_PAD_ECSPI2_MISO__SD1_DATA6                           0x0180 0x03F0 0x0000 0x2 0x0
+#define MX7D_PAD_ECSPI2_MISO__CSI_DATA8                           0x0180 0x03F0 0x0510 0x3 0x1
+#define MX7D_PAD_ECSPI2_MISO__LCD_DATA15                          0x0180 0x03F0 0x0674 0x4 0x2
+#define MX7D_PAD_ECSPI2_SS0__ECSPI2_SS0                           0x0184 0x03F4 0x0540 0x0 0x0
+#define MX7D_PAD_ECSPI2_SS0__UART7_DCE_CTS                        0x0184 0x03F4 0x0000 0x1 0x0
+#define MX7D_PAD_ECSPI2_SS0__UART7_DTE_RTS                        0x0184 0x03F4 0x0720 0x1 0x3
+#define MX7D_PAD_ECSPI2_SS0__SD1_DATA7                            0x0184 0x03F4 0x0000 0x2 0x0
+#define MX7D_PAD_ECSPI2_SS0__CSI_DATA9                            0x0184 0x03F4 0x0514 0x3 0x1
+#define MX7D_PAD_ECSPI2_SS0__LCD_RESET                            0x0184 0x03F4 0x0000 0x4 0x0
+#define MX7D_PAD_ECSPI2_SS0__GPIO4_IO23                           0x0184 0x03F4 0x0000 0x5 0x0
+#define MX7D_PAD_ECSPI2_SS0__EPDC_PWR_WAKE                        0x0184 0x03F4 0x0000 0x6 0x0
+#define MX7D_PAD_SD1_CD_B__SD1_CD_B                               0x0188 0x03F8 0x0000 0x0 0x0
+#define MX7D_PAD_SD1_CD_B__UART6_DCE_RX                           0x0188 0x03F8 0x071C 0x2 0x4
+#define MX7D_PAD_SD1_CD_B__UART6_DTE_TX                           0x0188 0x03F8 0x0000 0x2 0x0
+#define MX7D_PAD_SD1_CD_B__ECSPI4_MISO                            0x0188 0x03F8 0x0558 0x3 0x1
+#define MX7D_PAD_SD1_CD_B__FLEXTIMER1_CH0                         0x0188 0x03F8 0x0584 0x4 0x1
+#define MX7D_PAD_SD1_CD_B__GPIO5_IO0                              0x0188 0x03F8 0x0000 0x5 0x0
+#define MX7D_PAD_SD1_CD_B__CCM_CLKO1                              0x0188 0x03F8 0x0000 0x6 0x0
+#define MX7D_PAD_SD1_WP__SD1_WP                                   0x018C 0x03FC 0x0000 0x0 0x0
+#define MX7D_PAD_SD1_WP__UART6_DCE_TX                             0x018C 0x03FC 0x0000 0x2 0x0
+#define MX7D_PAD_SD1_WP__UART6_DTE_RX                             0x018C 0x03FC 0x071C 0x2 0x5
+#define MX7D_PAD_SD1_WP__ECSPI4_MOSI                              0x018C 0x03FC 0x055C 0x3 0x1
+#define MX7D_PAD_SD1_WP__FLEXTIMER1_CH1                           0x018C 0x03FC 0x0588 0x4 0x1
+#define MX7D_PAD_SD1_WP__GPIO5_IO1                                0x018C 0x03FC 0x0000 0x5 0x0
+#define MX7D_PAD_SD1_WP__CCM_CLKO2                                0x018C 0x03FC 0x0000 0x6 0x0
+#define MX7D_PAD_SD1_RESET_B__SD1_RESET_B                         0x0190 0x0400 0x0000 0x0 0x0
+#define MX7D_PAD_SD1_RESET_B__SAI3_MCLK                           0x0190 0x0400 0x0000 0x1 0x0
+#define MX7D_PAD_SD1_RESET_B__UART6_DCE_RTS                       0x0190 0x0400 0x0718 0x2 0x4
+#define MX7D_PAD_SD1_RESET_B__UART6_DTE_CTS                       0x0190 0x0400 0x0000 0x2 0x0
+#define MX7D_PAD_SD1_RESET_B__ECSPI4_SCLK                         0x0190 0x0400 0x0554 0x3 0x1
+#define MX7D_PAD_SD1_RESET_B__FLEXTIMER1_CH2                      0x0190 0x0400 0x058C 0x4 0x1
+#define MX7D_PAD_SD1_RESET_B__GPIO5_IO2                           0x0190 0x0400 0x0000 0x5 0x0
+#define MX7D_PAD_SD1_CLK__SD1_CLK                                 0x0194 0x0404 0x0000 0x0 0x0
+#define MX7D_PAD_SD1_CLK__SAI3_RX_SYNC                            0x0194 0x0404 0x06CC 0x1 0x1
+#define MX7D_PAD_SD1_CLK__UART6_DCE_CTS                           0x0194 0x0404 0x0000 0x2 0x0
+#define MX7D_PAD_SD1_CLK__UART6_DTE_RTS                           0x0194 0x0404 0x0718 0x2 0x5
+#define MX7D_PAD_SD1_CLK__ECSPI4_SS0                              0x0194 0x0404 0x0560 0x3 0x1
+#define MX7D_PAD_SD1_CLK__FLEXTIMER1_CH3                          0x0194 0x0404 0x0590 0x4 0x1
+#define MX7D_PAD_SD1_CLK__GPIO5_IO3                               0x0194 0x0404 0x0000 0x5 0x0
+#define MX7D_PAD_SD1_CMD__SD1_CMD                                 0x0198 0x0408 0x0000 0x0 0x0
+#define MX7D_PAD_SD1_CMD__SAI3_RX_BCLK                            0x0198 0x0408 0x06C4 0x1 0x1
+#define MX7D_PAD_SD1_CMD__ECSPI4_SS1                              0x0198 0x0408 0x0000 0x3 0x0
+#define MX7D_PAD_SD1_CMD__FLEXTIMER2_CH0                          0x0198 0x0408 0x05AC 0x4 0x1
+#define MX7D_PAD_SD1_CMD__GPIO5_IO4                               0x0198 0x0408 0x0000 0x5 0x0
+#define MX7D_PAD_SD1_DATA0__SD1_DATA0                             0x019C 0x040C 0x0000 0x0 0x0
+#define MX7D_PAD_SD1_DATA0__SAI3_RX_DATA0                         0x019C 0x040C 0x06C8 0x1 0x1
+#define MX7D_PAD_SD1_DATA0__UART7_DCE_RX                          0x019C 0x040C 0x0724 0x2 0x4
+#define MX7D_PAD_SD1_DATA0__UART7_DTE_TX                          0x019C 0x040C 0x0000 0x2 0x0
+#define MX7D_PAD_SD1_DATA0__ECSPI4_SS2                            0x019C 0x040C 0x0000 0x3 0x0
+#define MX7D_PAD_SD1_DATA0__FLEXTIMER2_CH1                        0x019C 0x040C 0x05B0 0x4 0x1
+#define MX7D_PAD_SD1_DATA0__GPIO5_IO5                             0x019C 0x040C 0x0000 0x5 0x0
+#define MX7D_PAD_SD1_DATA0__CCM_EXT_CLK1                          0x019C 0x040C 0x04E4 0x6 0x1
+#define MX7D_PAD_SD1_DATA1__SD1_DATA1                             0x01A0 0x0410 0x0000 0x0 0x0
+#define MX7D_PAD_SD1_DATA1__SAI3_TX_BCLK                          0x01A0 0x0410 0x06D0 0x1 0x1
+#define MX7D_PAD_SD1_DATA1__UART7_DCE_TX                          0x01A0 0x0410 0x0000 0x2 0x0
+#define MX7D_PAD_SD1_DATA1__UART7_DTE_RX                          0x01A0 0x0410 0x0724 0x2 0x5
+#define MX7D_PAD_SD1_DATA1__ECSPI4_SS3                            0x01A0 0x0410 0x0000 0x3 0x0
+#define MX7D_PAD_SD1_DATA1__FLEXTIMER2_CH2                        0x01A0 0x0410 0x05B4 0x4 0x1
+#define MX7D_PAD_SD1_DATA1__GPIO5_IO6                             0x01A0 0x0410 0x0000 0x5 0x0
+#define MX7D_PAD_SD1_DATA1__CCM_EXT_CLK2                          0x01A0 0x0410 0x04E8 0x6 0x1
+#define MX7D_PAD_SD1_DATA2__SD1_DATA2                             0x01A4 0x0414 0x0000 0x0 0x0
+#define MX7D_PAD_SD1_DATA2__SAI3_TX_SYNC                          0x01A4 0x0414 0x06D4 0x1 0x1
+#define MX7D_PAD_SD1_DATA2__UART7_DCE_CTS                         0x01A4 0x0414 0x0000 0x2 0x0
+#define MX7D_PAD_SD1_DATA2__UART7_DTE_RTS                         0x01A4 0x0414 0x0720 0x2 0x4
+#define MX7D_PAD_SD1_DATA2__ECSPI4_RDY                            0x01A4 0x0414 0x0000 0x3 0x0
+#define MX7D_PAD_SD1_DATA2__FLEXTIMER2_CH3                        0x01A4 0x0414 0x05B8 0x4 0x1
+#define MX7D_PAD_SD1_DATA2__GPIO5_IO7                             0x01A4 0x0414 0x0000 0x5 0x0
+#define MX7D_PAD_SD1_DATA2__CCM_EXT_CLK3                          0x01A4 0x0414 0x04EC 0x6 0x1
+#define MX7D_PAD_SD1_DATA3__SD1_DATA3                             0x01A8 0x0418 0x0000 0x0 0x0
+#define MX7D_PAD_SD1_DATA3__SAI3_TX_DATA0                         0x01A8 0x0418 0x0000 0x1 0x0
+#define MX7D_PAD_SD1_DATA3__UART7_DCE_RTS                         0x01A8 0x0418 0x0720 0x2 0x5
+#define MX7D_PAD_SD1_DATA3__UART7_DTE_CTS                         0x01A8 0x0418 0x0000 0x2 0x0
+#define MX7D_PAD_SD1_DATA3__ECSPI3_SS1                            0x01A8 0x0418 0x0000 0x3 0x0
+#define MX7D_PAD_SD1_DATA3__FLEXTIMER1_PHA                        0x01A8 0x0418 0x05A4 0x4 0x1
+#define MX7D_PAD_SD1_DATA3__GPIO5_IO8                             0x01A8 0x0418 0x0000 0x5 0x0
+#define MX7D_PAD_SD1_DATA3__CCM_EXT_CLK4                          0x01A8 0x0418 0x04F0 0x6 0x1
+#define MX7D_PAD_SD2_CD_B__SD2_CD_B                               0x01AC 0x041C 0x0000 0x0 0x0
+#define MX7D_PAD_SD2_CD_B__ENET1_MDIO                             0x01AC 0x041C 0x0568 0x1 0x2
+#define MX7D_PAD_SD2_CD_B__ENET2_MDIO                             0x01AC 0x041C 0x0574 0x2 0x2
+#define MX7D_PAD_SD2_CD_B__ECSPI3_SS2                             0x01AC 0x041C 0x0000 0x3 0x0
+#define MX7D_PAD_SD2_CD_B__FLEXTIMER1_PHB                         0x01AC 0x041C 0x05A8 0x4 0x1
+#define MX7D_PAD_SD2_CD_B__GPIO5_IO9                              0x01AC 0x041C 0x0000 0x5 0x0
+#define MX7D_PAD_SD2_CD_B__SDMA_EXT_EVENT0                        0x01AC 0x041C 0x06D8 0x6 0x2
+#define MX7D_PAD_SD2_WP__SD2_WP                                   0x01B0 0x0420 0x0000 0x0 0x0
+#define MX7D_PAD_SD2_WP__ENET1_MDC                                0x01B0 0x0420 0x0000 0x1 0x0
+#define MX7D_PAD_SD2_WP__ENET2_MDC                                0x01B0 0x0420 0x0000 0x2 0x0
+#define MX7D_PAD_SD2_WP__ECSPI3_SS3                               0x01B0 0x0420 0x0000 0x3 0x0
+#define MX7D_PAD_SD2_WP__USB_OTG1_ID                              0x01B0 0x0420 0x0734 0x4 0x2
+#define MX7D_PAD_SD2_WP__GPIO5_IO10                               0x01B0 0x0420 0x0000 0x5 0x0
+#define MX7D_PAD_SD2_WP__SDMA_EXT_EVENT1                          0x01B0 0x0420 0x06DC 0x6 0x2
+#define MX7D_PAD_SD2_RESET_B__SD2_RESET_B                         0x01B4 0x0424 0x0000 0x0 0x0
+#define MX7D_PAD_SD2_RESET_B__SAI2_MCLK                           0x01B4 0x0424 0x0000 0x1 0x0
+#define MX7D_PAD_SD2_RESET_B__SD2_RESET                           0x01B4 0x0424 0x0000 0x2 0x0
+#define MX7D_PAD_SD2_RESET_B__ECSPI3_RDY                          0x01B4 0x0424 0x0000 0x3 0x0
+#define MX7D_PAD_SD2_RESET_B__USB_OTG2_ID                         0x01B4 0x0424 0x0730 0x4 0x2
+#define MX7D_PAD_SD2_RESET_B__GPIO5_IO11                          0x01B4 0x0424 0x0000 0x5 0x0
+#define MX7D_PAD_SD2_CLK__SD2_CLK                                 0x01B8 0x0428 0x0000 0x0 0x0
+#define MX7D_PAD_SD2_CLK__SAI2_RX_SYNC                            0x01B8 0x0428 0x06B8 0x1 0x0
+#define MX7D_PAD_SD2_CLK__MQS_RIGHT                               0x01B8 0x0428 0x0000 0x2 0x0
+#define MX7D_PAD_SD2_CLK__GPT4_CLK                                0x01B8 0x0428 0x0000 0x3 0x0
+#define MX7D_PAD_SD2_CLK__GPIO5_IO12                              0x01B8 0x0428 0x0000 0x5 0x0
+#define MX7D_PAD_SD2_CMD__SD2_CMD                                 0x01BC 0x042C 0x0000 0x0 0x0
+#define MX7D_PAD_SD2_CMD__SAI2_RX_BCLK                            0x01BC 0x042C 0x06B0 0x1 0x0
+#define MX7D_PAD_SD2_CMD__MQS_LEFT                                0x01BC 0x042C 0x0000 0x2 0x0
+#define MX7D_PAD_SD2_CMD__GPT4_CAPTURE1                           0x01BC 0x042C 0x0000 0x3 0x0
+#define MX7D_PAD_SD2_CMD__SIM2_PORT1_TRXD                         0x01BC 0x042C 0x06EC 0x4 0x1
+#define MX7D_PAD_SD2_CMD__GPIO5_IO13                              0x01BC 0x042C 0x0000 0x5 0x0
+#define MX7D_PAD_SD2_DATA0__SD2_DATA0                             0x01C0 0x0430 0x0000 0x0 0x0
+#define MX7D_PAD_SD2_DATA0__SAI2_RX_DATA0                         0x01C0 0x0430 0x06B4 0x1 0x0
+#define MX7D_PAD_SD2_DATA0__UART4_DCE_RX                          0x01C0 0x0430 0x070C 0x2 0x2
+#define MX7D_PAD_SD2_DATA0__UART4_DTE_TX                          0x01C0 0x0430 0x0000 0x2 0x0
+#define MX7D_PAD_SD2_DATA0__GPT4_CAPTURE2                         0x01C0 0x0430 0x0000 0x3 0x0
+#define MX7D_PAD_SD2_DATA0__SIM2_PORT1_CLK                        0x01C0 0x0430 0x0000 0x4 0x0
+#define MX7D_PAD_SD2_DATA0__GPIO5_IO14                            0x01C0 0x0430 0x0000 0x5 0x0
+#define MX7D_PAD_SD2_DATA1__SD2_DATA1                             0x01C4 0x0434 0x0000 0x0 0x0
+#define MX7D_PAD_SD2_DATA1__SAI2_TX_BCLK                          0x01C4 0x0434 0x06BC 0x1 0x0
+#define MX7D_PAD_SD2_DATA1__UART4_DCE_TX                          0x01C4 0x0434 0x0000 0x2 0x0
+#define MX7D_PAD_SD2_DATA1__UART4_DTE_RX                          0x01C4 0x0434 0x070C 0x2 0x3
+#define MX7D_PAD_SD2_DATA1__GPT4_COMPARE1                         0x01C4 0x0434 0x0000 0x3 0x0
+#define MX7D_PAD_SD2_DATA1__SIM2_PORT1_RST_B                      0x01C4 0x0434 0x0000 0x4 0x0
+#define MX7D_PAD_SD2_DATA1__GPIO5_IO15                            0x01C4 0x0434 0x0000 0x5 0x0
+#define MX7D_PAD_SD2_DATA2__SD2_DATA2                             0x01C8 0x0438 0x0000 0x0 0x0
+#define MX7D_PAD_SD2_DATA2__SAI2_TX_SYNC                          0x01C8 0x0438 0x06C0 0x1 0x0
+#define MX7D_PAD_SD2_DATA2__UART4_DCE_CTS                         0x01C8 0x0438 0x0000 0x2 0x0
+#define MX7D_PAD_SD2_DATA2__UART4_DTE_RTS                         0x01C8 0x0438 0x0708 0x2 0x2
+#define MX7D_PAD_SD2_DATA2__GPT4_COMPARE2                         0x01C8 0x0438 0x0000 0x3 0x0
+#define MX7D_PAD_SD2_DATA2__SIM2_PORT1_SVEN                       0x01C8 0x0438 0x0000 0x4 0x0
+#define MX7D_PAD_SD2_DATA2__GPIO5_IO16                            0x01C8 0x0438 0x0000 0x5 0x0
+#define MX7D_PAD_SD2_DATA3__SD2_DATA3                             0x01CC 0x043C 0x0000 0x0 0x0
+#define MX7D_PAD_SD2_DATA3__SAI2_TX_DATA0                         0x01CC 0x043C 0x0000 0x1 0x0
+#define MX7D_PAD_SD2_DATA3__UART4_DCE_RTS                         0x01CC 0x043C 0x0708 0x2 0x3
+#define MX7D_PAD_SD2_DATA3__UART4_DTE_CTS                         0x01CC 0x043C 0x0000 0x2 0x0
+#define MX7D_PAD_SD2_DATA3__GPT4_COMPARE3                         0x01CC 0x043C 0x0000 0x3 0x0
+#define MX7D_PAD_SD2_DATA3__SIM2_PORT1_PD                         0x01CC 0x043C 0x06E8 0x4 0x1
+#define MX7D_PAD_SD2_DATA3__GPIO5_IO17                            0x01CC 0x043C 0x0000 0x5 0x0
+#define MX7D_PAD_SD3_CLK__SD3_CLK                                 0x01D0 0x0440 0x0000 0x0 0x0
+#define MX7D_PAD_SD3_CLK__NAND_CLE                                0x01D0 0x0440 0x0000 0x1 0x0
+#define MX7D_PAD_SD3_CLK__ECSPI4_MISO                             0x01D0 0x0440 0x0558 0x2 0x2
+#define MX7D_PAD_SD3_CLK__SAI3_RX_SYNC                            0x01D0 0x0440 0x06CC 0x3 0x2
+#define MX7D_PAD_SD3_CLK__GPT3_CLK                                0x01D0 0x0440 0x0000 0x4 0x0
+#define MX7D_PAD_SD3_CLK__GPIO6_IO0                               0x01D0 0x0440 0x0000 0x5 0x0
+#define MX7D_PAD_SD3_CMD__SD3_CMD                                 0x01D4 0x0444 0x0000 0x0 0x0
+#define MX7D_PAD_SD3_CMD__NAND_ALE                                0x01D4 0x0444 0x0000 0x1 0x0
+#define MX7D_PAD_SD3_CMD__ECSPI4_MOSI                             0x01D4 0x0444 0x055C 0x2 0x2
+#define MX7D_PAD_SD3_CMD__SAI3_RX_BCLK                            0x01D4 0x0444 0x06C4 0x3 0x2
+#define MX7D_PAD_SD3_CMD__GPT3_CAPTURE1                           0x01D4 0x0444 0x0000 0x4 0x0
+#define MX7D_PAD_SD3_CMD__GPIO6_IO1                               0x01D4 0x0444 0x0000 0x5 0x0
+#define MX7D_PAD_SD3_DATA0__SD3_DATA0                             0x01D8 0x0448 0x0000 0x0 0x0
+#define MX7D_PAD_SD3_DATA0__NAND_DATA00                           0x01D8 0x0448 0x0000 0x1 0x0
+#define MX7D_PAD_SD3_DATA0__ECSPI4_SS0                            0x01D8 0x0448 0x0560 0x2 0x2
+#define MX7D_PAD_SD3_DATA0__SAI3_RX_DATA0                         0x01D8 0x0448 0x06C8 0x3 0x2
+#define MX7D_PAD_SD3_DATA0__GPT3_CAPTURE2                         0x01D8 0x0448 0x0000 0x4 0x0
+#define MX7D_PAD_SD3_DATA0__GPIO6_IO2                             0x01D8 0x0448 0x0000 0x5 0x0
+#define MX7D_PAD_SD3_DATA1__SD3_DATA1                             0x01DC 0x044C 0x0000 0x0 0x0
+#define MX7D_PAD_SD3_DATA1__NAND_DATA01                           0x01DC 0x044C 0x0000 0x1 0x0
+#define MX7D_PAD_SD3_DATA1__ECSPI4_SCLK                           0x01DC 0x044C 0x0554 0x2 0x2
+#define MX7D_PAD_SD3_DATA1__SAI3_TX_BCLK                          0x01DC 0x044C 0x06D0 0x3 0x2
+#define MX7D_PAD_SD3_DATA1__GPT3_COMPARE1                         0x01DC 0x044C 0x0000 0x4 0x0
+#define MX7D_PAD_SD3_DATA1__GPIO6_IO3                             0x01DC 0x044C 0x0000 0x5 0x0
+#define MX7D_PAD_SD3_DATA2__SD3_DATA2                             0x01E0 0x0450 0x0000 0x0 0x0
+#define MX7D_PAD_SD3_DATA2__NAND_DATA02                           0x01E0 0x0450 0x0000 0x1 0x0
+#define MX7D_PAD_SD3_DATA2__I2C3_SDA                              0x01E0 0x0450 0x05E8 0x2 0x3
+#define MX7D_PAD_SD3_DATA2__SAI3_TX_SYNC                          0x01E0 0x0450 0x06D4 0x3 0x2
+#define MX7D_PAD_SD3_DATA2__GPT3_COMPARE2                         0x01E0 0x0450 0x0000 0x4 0x0
+#define MX7D_PAD_SD3_DATA2__GPIO6_IO4                             0x01E0 0x0450 0x0000 0x5 0x0
+#define MX7D_PAD_SD3_DATA3__SD3_DATA3                             0x01E4 0x0454 0x0000 0x0 0x0
+#define MX7D_PAD_SD3_DATA3__NAND_DATA03                           0x01E4 0x0454 0x0000 0x1 0x0
+#define MX7D_PAD_SD3_DATA3__I2C3_SCL                              0x01E4 0x0454 0x05E4 0x2 0x3
+#define MX7D_PAD_SD3_DATA3__SAI3_TX_DATA0                         0x01E4 0x0454 0x0000 0x3 0x0
+#define MX7D_PAD_SD3_DATA3__GPT3_COMPARE3                         0x01E4 0x0454 0x0000 0x4 0x0
+#define MX7D_PAD_SD3_DATA3__GPIO6_IO5                             0x01E4 0x0454 0x0000 0x5 0x0
+#define MX7D_PAD_SD3_DATA4__SD3_DATA4                             0x01E8 0x0458 0x0000 0x0 0x0
+#define MX7D_PAD_SD3_DATA4__NAND_DATA04                           0x01E8 0x0458 0x0000 0x1 0x0
+#define MX7D_PAD_SD3_DATA4__UART3_DCE_RX                          0x01E8 0x0458 0x0704 0x3 0x4
+#define MX7D_PAD_SD3_DATA4__UART3_DTE_TX                          0x01E8 0x0458 0x0000 0x3 0x0
+#define MX7D_PAD_SD3_DATA4__FLEXCAN2_RX                           0x01E8 0x0458 0x04E0 0x4 0x2
+#define MX7D_PAD_SD3_DATA4__GPIO6_IO6                             0x01E8 0x0458 0x0000 0x5 0x0
+#define MX7D_PAD_SD3_DATA5__SD3_DATA5                             0x01EC 0x045C 0x0000 0x0 0x0
+#define MX7D_PAD_SD3_DATA5__NAND_DATA05                           0x01EC 0x045C 0x0000 0x1 0x0
+#define MX7D_PAD_SD3_DATA5__UART3_DCE_TX                          0x01EC 0x045C 0x0000 0x3 0x0
+#define MX7D_PAD_SD3_DATA5__UART3_DTE_RX                          0x01EC 0x045C 0x0704 0x3 0x5
+#define MX7D_PAD_SD3_DATA5__FLEXCAN1_TX                           0x01EC 0x045C 0x0000 0x4 0x0
+#define MX7D_PAD_SD3_DATA5__GPIO6_IO7                             0x01EC 0x045C 0x0000 0x5 0x0
+#define MX7D_PAD_SD3_DATA6__SD3_DATA6                             0x01F0 0x0460 0x0000 0x0 0x0
+#define MX7D_PAD_SD3_DATA6__NAND_DATA06                           0x01F0 0x0460 0x0000 0x1 0x0
+#define MX7D_PAD_SD3_DATA6__SD3_WP                                0x01F0 0x0460 0x073C 0x2 0x2
+#define MX7D_PAD_SD3_DATA6__UART3_DCE_RTS                         0x01F0 0x0460 0x0700 0x3 0x4
+#define MX7D_PAD_SD3_DATA6__UART3_DTE_CTS                         0x01F0 0x0460 0x0000 0x3 0x0
+#define MX7D_PAD_SD3_DATA6__FLEXCAN2_TX                           0x01F0 0x0460 0x0000 0x4 0x0
+#define MX7D_PAD_SD3_DATA6__GPIO6_IO8                             0x01F0 0x0460 0x0000 0x5 0x0
+#define MX7D_PAD_SD3_DATA7__SD3_DATA7                             0x01F4 0x0464 0x0000 0x0 0x0
+#define MX7D_PAD_SD3_DATA7__NAND_DATA07                           0x01F4 0x0464 0x0000 0x1 0x0
+#define MX7D_PAD_SD3_DATA7__SD3_CD_B                              0x01F4 0x0464 0x0738 0x2 0x2
+#define MX7D_PAD_SD3_DATA7__UART3_DCE_CTS                         0x01F4 0x0464 0x0000 0x3 0x0
+#define MX7D_PAD_SD3_DATA7__UART3_DTE_RTS                         0x01F4 0x0464 0x0700 0x3 0x5
+#define MX7D_PAD_SD3_DATA7__FLEXCAN1_RX                           0x01F4 0x0464 0x04DC 0x4 0x2
+#define MX7D_PAD_SD3_DATA7__GPIO6_IO9                             0x01F4 0x0464 0x0000 0x5 0x0
+#define MX7D_PAD_SD3_STROBE__SD3_STROBE                           0x01F8 0x0468 0x0000 0x0 0x0
+#define MX7D_PAD_SD3_STROBE__NAND_RE_B                            0x01F8 0x0468 0x0000 0x1 0x0
+#define MX7D_PAD_SD3_STROBE__GPIO6_IO10                           0x01F8 0x0468 0x0000 0x5 0x0
+#define MX7D_PAD_SD3_RESET_B__SD3_RESET_B                         0x01FC 0x046C 0x0000 0x0 0x0
+#define MX7D_PAD_SD3_RESET_B__NAND_WE_B                           0x01FC 0x046C 0x0000 0x1 0x0
+#define MX7D_PAD_SD3_RESET_B__SD3_RESET                           0x01FC 0x046C 0x0000 0x2 0x0
+#define MX7D_PAD_SD3_RESET_B__SAI3_MCLK                           0x01FC 0x046C 0x0000 0x3 0x0
+#define MX7D_PAD_SD3_RESET_B__GPIO6_IO11                          0x01FC 0x046C 0x0000 0x5 0x0
+#define MX7D_PAD_SAI1_RX_DATA__SAI1_RX_DATA0                      0x0200 0x0470 0x06A0 0x0 0x0
+#define MX7D_PAD_SAI1_RX_DATA__NAND_CE1_B                         0x0200 0x0470 0x0000 0x1 0x0
+#define MX7D_PAD_SAI1_RX_DATA__UART5_DCE_RX                       0x0200 0x0470 0x0714 0x2 0x2
+#define MX7D_PAD_SAI1_RX_DATA__UART5_DTE_TX                       0x0200 0x0470 0x0000 0x2 0x0
+#define MX7D_PAD_SAI1_RX_DATA__FLEXCAN1_RX                        0x0200 0x0470 0x04DC 0x3 0x3
+#define MX7D_PAD_SAI1_RX_DATA__SIM1_PORT1_TRXD                    0x0200 0x0470 0x06E4 0x4 0x1
+#define MX7D_PAD_SAI1_RX_DATA__GPIO6_IO12                         0x0200 0x0470 0x0000 0x5 0x0
+#define MX7D_PAD_SAI1_RX_DATA__SRC_ANY_PU_RESET                   0x0200 0x0470 0x0000 0x7 0x0
+#define MX7D_PAD_SAI1_TX_BCLK__SAI1_TX_BCLK                       0x0204 0x0474 0x06A8 0x0 0x0
+#define MX7D_PAD_SAI1_TX_BCLK__NAND_CE0_B                         0x0204 0x0474 0x0000 0x1 0x0
+#define MX7D_PAD_SAI1_TX_BCLK__UART5_DCE_TX                       0x0204 0x0474 0x0000 0x2 0x0
+#define MX7D_PAD_SAI1_TX_BCLK__UART5_DTE_RX                       0x0204 0x0474 0x0714 0x2 0x3
+#define MX7D_PAD_SAI1_TX_BCLK__FLEXCAN1_TX                        0x0204 0x0474 0x0000 0x3 0x0
+#define MX7D_PAD_SAI1_TX_BCLK__SIM1_PORT1_CLK                     0x0204 0x0474 0x0000 0x4 0x0
+#define MX7D_PAD_SAI1_TX_BCLK__GPIO6_IO13                         0x0204 0x0474 0x0000 0x5 0x0
+#define MX7D_PAD_SAI1_TX_BCLK__SRC_EARLY_RESET                    0x0204 0x0474 0x0000 0x7 0x0
+#define MX7D_PAD_SAI1_TX_SYNC__SAI1_TX_SYNC                       0x0208 0x0478 0x06AC 0x0 0x0
+#define MX7D_PAD_SAI1_TX_SYNC__NAND_DQS                           0x0208 0x0478 0x0000 0x1 0x0
+#define MX7D_PAD_SAI1_TX_SYNC__UART5_DCE_CTS                      0x0208 0x0478 0x0000 0x2 0x0
+#define MX7D_PAD_SAI1_TX_SYNC__UART5_DTE_RTS                      0x0208 0x0478 0x0710 0x2 0x2
+#define MX7D_PAD_SAI1_TX_SYNC__FLEXCAN2_RX                        0x0208 0x0478 0x04E0 0x3 0x3
+#define MX7D_PAD_SAI1_TX_SYNC__SIM1_PORT1_RST_B                   0x0208 0x0478 0x0000 0x4 0x0
+#define MX7D_PAD_SAI1_TX_SYNC__GPIO6_IO14                         0x0208 0x0478 0x0000 0x5 0x0
+#define MX7D_PAD_SAI1_TX_SYNC__SRC_INT_BOOT                       0x0208 0x0478 0x0000 0x7 0x0
+#define MX7D_PAD_SAI1_TX_DATA__SAI1_TX_DATA0                      0x020C 0x047C 0x0000 0x0 0x0
+#define MX7D_PAD_SAI1_TX_DATA__NAND_READY_B                       0x020C 0x047C 0x0000 0x1 0x0
+#define MX7D_PAD_SAI1_TX_DATA__UART5_DCE_RTS                      0x020C 0x047C 0x0710 0x2 0x3
+#define MX7D_PAD_SAI1_TX_DATA__UART5_DTE_CTS                      0x020C 0x047C 0x0000 0x2 0x0
+#define MX7D_PAD_SAI1_TX_DATA__FLEXCAN2_TX                        0x020C 0x047C 0x0000 0x3 0x0
+#define MX7D_PAD_SAI1_TX_DATA__SIM1_PORT1_SVEN                    0x020C 0x047C 0x0000 0x4 0x0
+#define MX7D_PAD_SAI1_TX_DATA__GPIO6_IO15                         0x020C 0x047C 0x0000 0x5 0x0
+#define MX7D_PAD_SAI1_TX_DATA__SRC_SYSTEM_RESET                   0x020C 0x047C 0x0000 0x7 0x0
+#define MX7D_PAD_SAI1_RX_SYNC__SAI1_RX_SYNC                       0x0210 0x0480 0x06A4 0x0 0x0
+#define MX7D_PAD_SAI1_RX_SYNC__NAND_CE2_B                         0x0210 0x0480 0x0000 0x1 0x0
+#define MX7D_PAD_SAI1_RX_SYNC__SAI2_RX_SYNC                       0x0210 0x0480 0x06B8 0x2 0x1
+#define MX7D_PAD_SAI1_RX_SYNC__I2C4_SCL                           0x0210 0x0480 0x05EC 0x3 0x3
+#define MX7D_PAD_SAI1_RX_SYNC__SIM1_PORT1_PD                      0x0210 0x0480 0x06E0 0x4 0x1
+#define MX7D_PAD_SAI1_RX_SYNC__GPIO6_IO16                         0x0210 0x0480 0x0000 0x5 0x0
+#define MX7D_PAD_SAI1_RX_SYNC__MQS_RIGHT                          0x0210 0x0480 0x0000 0x6 0x0
+#define MX7D_PAD_SAI1_RX_SYNC__SRC_CA7_RESET_B0                   0x0210 0x0480 0x0000 0x7 0x0
+#define MX7D_PAD_SAI1_RX_BCLK__SAI1_RX_BCLK                       0x0214 0x0484 0x069C 0x0 0x0
+#define MX7D_PAD_SAI1_RX_BCLK__NAND_CE3_B                         0x0214 0x0484 0x0000 0x1 0x0
+#define MX7D_PAD_SAI1_RX_BCLK__SAI2_RX_BCLK                       0x0214 0x0484 0x06B0 0x2 0x1
+#define MX7D_PAD_SAI1_RX_BCLK__I2C4_SDA                           0x0214 0x0484 0x05F0 0x3 0x3
+#define MX7D_PAD_SAI1_RX_BCLK__FLEXTIMER2_PHA                     0x0214 0x0484 0x05CC 0x4 0x1
+#define MX7D_PAD_SAI1_RX_BCLK__GPIO6_IO17                         0x0214 0x0484 0x0000 0x5 0x0
+#define MX7D_PAD_SAI1_RX_BCLK__MQS_LEFT                           0x0214 0x0484 0x0000 0x6 0x0
+#define MX7D_PAD_SAI1_RX_BCLK__SRC_CA7_RESET_B1                   0x0214 0x0484 0x0000 0x7 0x0
+#define MX7D_PAD_SAI1_MCLK__SAI1_MCLK                             0x0218 0x0488 0x0000 0x0 0x0
+#define MX7D_PAD_SAI1_MCLK__NAND_WP_B                             0x0218 0x0488 0x0000 0x1 0x0
+#define MX7D_PAD_SAI1_MCLK__SAI2_MCLK                             0x0218 0x0488 0x0000 0x2 0x0
+#define MX7D_PAD_SAI1_MCLK__CCM_PMIC_READY                        0x0218 0x0488 0x04F4 0x3 0x3
+#define MX7D_PAD_SAI1_MCLK__FLEXTIMER2_PHB                        0x0218 0x0488 0x05D0 0x4 0x1
+#define MX7D_PAD_SAI1_MCLK__GPIO6_IO18                            0x0218 0x0488 0x0000 0x5 0x0
+#define MX7D_PAD_SAI1_MCLK__SRC_TESTER_ACK                        0x0218 0x0488 0x0000 0x7 0x0
+#define MX7D_PAD_SAI2_TX_SYNC__SAI2_TX_SYNC                       0x021C 0x048C 0x06C0 0x0 0x1
+#define MX7D_PAD_SAI2_TX_SYNC__ECSPI3_MISO                        0x021C 0x048C 0x0548 0x1 0x1
+#define MX7D_PAD_SAI2_TX_SYNC__UART4_DCE_RX                       0x021C 0x048C 0x070C 0x2 0x4
+#define MX7D_PAD_SAI2_TX_SYNC__UART4_DTE_TX                       0x021C 0x048C 0x0000 0x2 0x0
+#define MX7D_PAD_SAI2_TX_SYNC__UART1_DCE_CTS                      0x021C 0x048C 0x0000 0x3 0x0
+#define MX7D_PAD_SAI2_TX_SYNC__UART1_DTE_RTS                      0x021C 0x048C 0x06F0 0x3 0x0
+#define MX7D_PAD_SAI2_TX_SYNC__FLEXTIMER2_CH4                     0x021C 0x048C 0x05BC 0x4 0x1
+#define MX7D_PAD_SAI2_TX_SYNC__GPIO6_IO19                         0x021C 0x048C 0x0000 0x5 0x0
+#define MX7D_PAD_SAI2_TX_BCLK__SAI2_TX_BCLK                       0x0220 0x0490 0x06BC 0x0 0x1
+#define MX7D_PAD_SAI2_TX_BCLK__ECSPI3_MOSI                        0x0220 0x0490 0x054C 0x1 0x1
+#define MX7D_PAD_SAI2_TX_BCLK__UART4_DCE_TX                       0x0220 0x0490 0x0000 0x2 0x0
+#define MX7D_PAD_SAI2_TX_BCLK__UART4_DTE_RX                       0x0220 0x0490 0x070C 0x2 0x5
+#define MX7D_PAD_SAI2_TX_BCLK__UART1_DCE_RTS                      0x0220 0x0490 0x06F0 0x3 0x1
+#define MX7D_PAD_SAI2_TX_BCLK__UART1_DTE_CTS                      0x0220 0x0490 0x0000 0x3 0x0
+#define MX7D_PAD_SAI2_TX_BCLK__FLEXTIMER2_CH5                     0x0220 0x0490 0x05C0 0x4 0x1
+#define MX7D_PAD_SAI2_TX_BCLK__GPIO6_IO20                         0x0220 0x0490 0x0000 0x5 0x0
+#define MX7D_PAD_SAI2_RX_DATA__SAI2_RX_DATA0                      0x0224 0x0494 0x06B4 0x0 0x1
+#define MX7D_PAD_SAI2_RX_DATA__ECSPI3_SCLK                        0x0224 0x0494 0x0544 0x1 0x1
+#define MX7D_PAD_SAI2_RX_DATA__UART4_DCE_CTS                      0x0224 0x0494 0x0000 0x2 0x0
+#define MX7D_PAD_SAI2_RX_DATA__UART4_DTE_RTS                      0x0224 0x0494 0x0708 0x2 0x4
+#define MX7D_PAD_SAI2_RX_DATA__UART2_DCE_CTS                      0x0224 0x0494 0x0000 0x3 0x0
+#define MX7D_PAD_SAI2_RX_DATA__UART2_DTE_RTS                      0x0224 0x0494 0x06F8 0x3 0x2
+#define MX7D_PAD_SAI2_RX_DATA__FLEXTIMER2_CH6                     0x0224 0x0494 0x05C4 0x4 0x1
+#define MX7D_PAD_SAI2_RX_DATA__GPIO6_IO21                         0x0224 0x0494 0x0000 0x5 0x0
+#define MX7D_PAD_SAI2_RX_DATA__KPP_COL7                           0x0224 0x0494 0x0610 0x6 0x1
+#define MX7D_PAD_SAI2_TX_DATA__SAI2_TX_DATA0                      0x0228 0x0498 0x0000 0x0 0x0
+#define MX7D_PAD_SAI2_TX_DATA__ECSPI3_SS0                         0x0228 0x0498 0x0550 0x1 0x1
+#define MX7D_PAD_SAI2_TX_DATA__UART4_DCE_RTS                      0x0228 0x0498 0x0708 0x2 0x5
+#define MX7D_PAD_SAI2_TX_DATA__UART4_DTE_CTS                      0x0228 0x0498 0x0000 0x2 0x0
+#define MX7D_PAD_SAI2_TX_DATA__UART2_DCE_RTS                      0x0228 0x0498 0x06F8 0x3 0x3
+#define MX7D_PAD_SAI2_TX_DATA__UART2_DTE_CTS                      0x0228 0x0498 0x0000 0x3 0x0
+#define MX7D_PAD_SAI2_TX_DATA__FLEXTIMER2_CH7                     0x0228 0x0498 0x05C8 0x4 0x1
+#define MX7D_PAD_SAI2_TX_DATA__GPIO6_IO22                         0x0228 0x0498 0x0000 0x5 0x0
+#define MX7D_PAD_SAI2_TX_DATA__KPP_ROW7                           0x0228 0x0498 0x0630 0x6 0x1
+#define MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0                 0x022C 0x049C 0x0000 0x0 0x0
+#define MX7D_PAD_ENET1_RGMII_RD0__PWM1_OUT                        0x022C 0x049C 0x0000 0x1 0x0
+#define MX7D_PAD_ENET1_RGMII_RD0__I2C3_SCL                        0x022C 0x049C 0x05E4 0x2 0x4
+#define MX7D_PAD_ENET1_RGMII_RD0__UART1_DCE_CTS                   0x022C 0x049C 0x0000 0x3 0x0
+#define MX7D_PAD_ENET1_RGMII_RD0__UART1_DTE_RTS                   0x022C 0x049C 0x06F0 0x3 0x2
+#define MX7D_PAD_ENET1_RGMII_RD0__EPDC_VCOM0                      0x022C 0x049C 0x0000 0x4 0x0
+#define MX7D_PAD_ENET1_RGMII_RD0__GPIO7_IO0                       0x022C 0x049C 0x0000 0x5 0x0
+#define MX7D_PAD_ENET1_RGMII_RD0__KPP_ROW3                        0x022C 0x049C 0x0620 0x6 0x1
+#define MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1                 0x0230 0x04A0 0x0000 0x0 0x0
+#define MX7D_PAD_ENET1_RGMII_RD1__PWM2_OUT                        0x0230 0x04A0 0x0000 0x1 0x0
+#define MX7D_PAD_ENET1_RGMII_RD1__I2C3_SDA                        0x0230 0x04A0 0x05E8 0x2 0x4
+#define MX7D_PAD_ENET1_RGMII_RD1__UART1_DCE_RTS                   0x0230 0x04A0 0x06F0 0x3 0x3
+#define MX7D_PAD_ENET1_RGMII_RD1__UART1_DTE_CTS                   0x0230 0x04A0 0x0000 0x3 0x0
+#define MX7D_PAD_ENET1_RGMII_RD1__EPDC_VCOM1                      0x0230 0x04A0 0x0000 0x4 0x0
+#define MX7D_PAD_ENET1_RGMII_RD1__GPIO7_IO1                       0x0230 0x04A0 0x0000 0x5 0x0
+#define MX7D_PAD_ENET1_RGMII_RD1__KPP_COL3                        0x0230 0x04A0 0x0600 0x6 0x1
+#define MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2                 0x0234 0x04A4 0x0000 0x0 0x0
+#define MX7D_PAD_ENET1_RGMII_RD2__FLEXCAN1_RX                     0x0234 0x04A4 0x04DC 0x1 0x4
+#define MX7D_PAD_ENET1_RGMII_RD2__ECSPI2_SCLK                     0x0234 0x04A4 0x0534 0x2 0x1
+#define MX7D_PAD_ENET1_RGMII_RD2__UART1_DCE_RX                    0x0234 0x04A4 0x06F4 0x3 0x2
+#define MX7D_PAD_ENET1_RGMII_RD2__UART1_DTE_TX                    0x0234 0x04A4 0x0000 0x3 0x0
+#define MX7D_PAD_ENET1_RGMII_RD2__EPDC_SDCE4                      0x0234 0x04A4 0x0000 0x4 0x0
+#define MX7D_PAD_ENET1_RGMII_RD2__GPIO7_IO2                       0x0234 0x04A4 0x0000 0x5 0x0
+#define MX7D_PAD_ENET1_RGMII_RD2__KPP_ROW2                        0x0234 0x04A4 0x061C 0x6 0x1
+#define MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3                 0x0238 0x04A8 0x0000 0x0 0x0
+#define MX7D_PAD_ENET1_RGMII_RD3__FLEXCAN1_TX                     0x0238 0x04A8 0x0000 0x1 0x0
+#define MX7D_PAD_ENET1_RGMII_RD3__ECSPI2_MOSI                     0x0238 0x04A8 0x053C 0x2 0x1
+#define MX7D_PAD_ENET1_RGMII_RD3__UART1_DCE_TX                    0x0238 0x04A8 0x0000 0x3 0x0
+#define MX7D_PAD_ENET1_RGMII_RD3__UART1_DTE_RX                    0x0238 0x04A8 0x06F4 0x3 0x3
+#define MX7D_PAD_ENET1_RGMII_RD3__EPDC_SDCE5                      0x0238 0x04A8 0x0000 0x4 0x0
+#define MX7D_PAD_ENET1_RGMII_RD3__GPIO7_IO3                       0x0238 0x04A8 0x0000 0x5 0x0
+#define MX7D_PAD_ENET1_RGMII_RD3__KPP_COL2                        0x0238 0x04A8 0x05FC 0x6 0x1
+#define MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL           0x023C 0x04AC 0x0000 0x0 0x0
+#define MX7D_PAD_ENET1_RGMII_RX_CTL__ECSPI2_SS1                   0x023C 0x04AC 0x0000 0x2 0x0
+#define MX7D_PAD_ENET1_RGMII_RX_CTL__EPDC_SDCE6                   0x023C 0x04AC 0x0000 0x4 0x0
+#define MX7D_PAD_ENET1_RGMII_RX_CTL__GPIO7_IO4                    0x023C 0x04AC 0x0000 0x5 0x0
+#define MX7D_PAD_ENET1_RGMII_RX_CTL__KPP_ROW1                     0x023C 0x04AC 0x0618 0x6 0x1
+#define MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC                 0x0240 0x04B0 0x0000 0x0 0x0
+#define MX7D_PAD_ENET1_RGMII_RXC__ENET1_RX_ER                     0x0240 0x04B0 0x0000 0x1 0x0
+#define MX7D_PAD_ENET1_RGMII_RXC__ECSPI2_SS2                      0x0240 0x04B0 0x0000 0x2 0x0
+#define MX7D_PAD_ENET1_RGMII_RXC__EPDC_SDCE7                      0x0240 0x04B0 0x0000 0x4 0x0
+#define MX7D_PAD_ENET1_RGMII_RXC__GPIO7_IO5                       0x0240 0x04B0 0x0000 0x5 0x0
+#define MX7D_PAD_ENET1_RGMII_RXC__KPP_COL1                        0x0240 0x04B0 0x0000 0x6 0x0
+#define MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0                 0x0244 0x04B4 0x0000 0x0 0x0
+#define MX7D_PAD_ENET1_RGMII_TD0__PWM3_OUT                        0x0244 0x04B4 0x0000 0x1 0x0
+#define MX7D_PAD_ENET1_RGMII_TD0__ECSPI2_SS3                      0x0244 0x04B4 0x0000 0x2 0x0
+#define MX7D_PAD_ENET1_RGMII_TD0__EPDC_SDCE8                      0x0244 0x04B4 0x0000 0x4 0x0
+#define MX7D_PAD_ENET1_RGMII_TD0__GPIO7_IO6                       0x0244 0x04B4 0x0000 0x5 0x0
+#define MX7D_PAD_ENET1_RGMII_TD0__KPP_ROW0                        0x0244 0x04B4 0x0614 0x6 0x1
+#define MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1                 0x0248 0x04B8 0x0000 0x0 0x0
+#define MX7D_PAD_ENET1_RGMII_TD1__PWM4_OUT                        0x0248 0x04B8 0x0000 0x1 0x0
+#define MX7D_PAD_ENET1_RGMII_TD1__ECSPI2_RDY                      0x0248 0x04B8 0x0000 0x2 0x0
+#define MX7D_PAD_ENET1_RGMII_TD1__EPDC_SDCE9                      0x0248 0x04B8 0x0000 0x4 0x0
+#define MX7D_PAD_ENET1_RGMII_TD1__GPIO7_IO7                       0x0248 0x04B8 0x0000 0x5 0x0
+#define MX7D_PAD_ENET1_RGMII_TD1__KPP_COL0                        0x0248 0x04B8 0x05F4 0x6 0x1
+#define MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2                 0x024C 0x04BC 0x0000 0x0 0x0
+#define MX7D_PAD_ENET1_RGMII_TD2__FLEXCAN2_RX                     0x024C 0x04BC 0x04E0 0x1 0x4
+#define MX7D_PAD_ENET1_RGMII_TD2__ECSPI2_MISO                     0x024C 0x04BC 0x0538 0x2 0x1
+#define MX7D_PAD_ENET1_RGMII_TD2__I2C4_SCL                        0x024C 0x04BC 0x05EC 0x3 0x4
+#define MX7D_PAD_ENET1_RGMII_TD2__EPDC_SDOED                      0x024C 0x04BC 0x0000 0x4 0x0
+#define MX7D_PAD_ENET1_RGMII_TD2__GPIO7_IO8                       0x024C 0x04BC 0x0000 0x5 0x0
+#define MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3                 0x0250 0x04C0 0x0000 0x0 0x0
+#define MX7D_PAD_ENET1_RGMII_TD3__FLEXCAN2_TX                     0x0250 0x04C0 0x0000 0x1 0x0
+#define MX7D_PAD_ENET1_RGMII_TD3__ECSPI2_SS0                      0x0250 0x04C0 0x0540 0x2 0x1
+#define MX7D_PAD_ENET1_RGMII_TD3__I2C4_SDA                        0x0250 0x04C0 0x05F0 0x3 0x4
+#define MX7D_PAD_ENET1_RGMII_TD3__EPDC_SDOEZ                      0x0250 0x04C0 0x0000 0x4 0x0
+#define MX7D_PAD_ENET1_RGMII_TD3__GPIO7_IO9                       0x0250 0x04C0 0x0000 0x5 0x0
+#define MX7D_PAD_ENET1_RGMII_TD3__CAAM_RNG_OSC_OBS                0x0250 0x04C0 0x0000 0x7 0x0
+#define MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL           0x0254 0x04C4 0x0000 0x0 0x0
+#define MX7D_PAD_ENET1_RGMII_TX_CTL__SAI1_RX_SYNC                 0x0254 0x04C4 0x06A4 0x2 0x1
+#define MX7D_PAD_ENET1_RGMII_TX_CTL__GPT2_COMPARE1                0x0254 0x04C4 0x0000 0x3 0x0
+#define MX7D_PAD_ENET1_RGMII_TX_CTL__EPDC_PWR_CTRL2               0x0254 0x04C4 0x0000 0x4 0x0
+#define MX7D_PAD_ENET1_RGMII_TX_CTL__GPIO7_IO10                   0x0254 0x04C4 0x0000 0x5 0x0
+#define MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC                 0x0258 0x04C8 0x0000 0x0 0x0
+#define MX7D_PAD_ENET1_RGMII_TXC__ENET1_TX_ER                     0x0258 0x04C8 0x0000 0x1 0x0
+#define MX7D_PAD_ENET1_RGMII_TXC__SAI1_RX_BCLK                    0x0258 0x04C8 0x069C 0x2 0x1
+#define MX7D_PAD_ENET1_RGMII_TXC__GPT2_COMPARE2                   0x0258 0x04C8 0x0000 0x3 0x0
+#define MX7D_PAD_ENET1_RGMII_TXC__EPDC_PWR_CTRL3                  0x0258 0x04C8 0x0000 0x4 0x0
+#define MX7D_PAD_ENET1_RGMII_TXC__GPIO7_IO11                      0x0258 0x04C8 0x0000 0x5 0x0
+#define MX7D_PAD_ENET1_TX_CLK__ENET1_TX_CLK                       0x025C 0x04CC 0x0000 0x0 0x0
+#define MX7D_PAD_ENET1_TX_CLK__CCM_ENET_REF_CLK1                  0x025C 0x04CC 0x0564 0x1 0x2
+#define MX7D_PAD_ENET1_TX_CLK__SAI1_RX_DATA0                      0x025C 0x04CC 0x06A0 0x2 0x1
+#define MX7D_PAD_ENET1_TX_CLK__GPT2_COMPARE3                      0x025C 0x04CC 0x0000 0x3 0x0
+#define MX7D_PAD_ENET1_TX_CLK__EPDC_PWR_IRQ                       0x025C 0x04CC 0x057C 0x4 0x1
+#define MX7D_PAD_ENET1_TX_CLK__GPIO7_IO12                         0x025C 0x04CC 0x0000 0x5 0x0
+#define MX7D_PAD_ENET1_TX_CLK__CCM_EXT_CLK1                       0x025C 0x04CC 0x04E4 0x6 0x2
+#define MX7D_PAD_ENET1_TX_CLK__CSU_ALARM_AUT0                     0x025C 0x04CC 0x0000 0x7 0x0
+#define MX7D_PAD_ENET1_RX_CLK__ENET1_RX_CLK                       0x0260 0x04D0 0x056C 0x0 0x0
+#define MX7D_PAD_ENET1_RX_CLK__WDOG2_WDOG_B                       0x0260 0x04D0 0x0000 0x1 0x0
+#define MX7D_PAD_ENET1_RX_CLK__SAI1_TX_BCLK                       0x0260 0x04D0 0x06A8 0x2 0x1
+#define MX7D_PAD_ENET1_RX_CLK__GPT2_CLK                           0x0260 0x04D0 0x0000 0x3 0x0
+#define MX7D_PAD_ENET1_RX_CLK__EPDC_PWR_WAKE                      0x0260 0x04D0 0x0000 0x4 0x0
+#define MX7D_PAD_ENET1_RX_CLK__GPIO7_IO13                         0x0260 0x04D0 0x0000 0x5 0x0
+#define MX7D_PAD_ENET1_RX_CLK__CCM_EXT_CLK2                       0x0260 0x04D0 0x04E8 0x6 0x2
+#define MX7D_PAD_ENET1_RX_CLK__CSU_ALARM_AUT1                     0x0260 0x04D0 0x0000 0x7 0x0
+#define MX7D_PAD_ENET1_CRS__ENET1_CRS                             0x0264 0x04D4 0x0000 0x0 0x0
+#define MX7D_PAD_ENET1_CRS__WDOG2_WDOG_RST_B_DEB                  0x0264 0x04D4 0x0000 0x1 0x0
+#define MX7D_PAD_ENET1_CRS__SAI1_TX_SYNC                          0x0264 0x04D4 0x06AC 0x2 0x1
+#define MX7D_PAD_ENET1_CRS__GPT2_CAPTURE1                         0x0264 0x04D4 0x0000 0x3 0x0
+#define MX7D_PAD_ENET1_CRS__EPDC_PWR_CTRL0                        0x0264 0x04D4 0x0000 0x4 0x0
+#define MX7D_PAD_ENET1_CRS__GPIO7_IO14                            0x0264 0x04D4 0x0000 0x5 0x0
+#define MX7D_PAD_ENET1_CRS__CCM_EXT_CLK3                          0x0264 0x04D4 0x04EC 0x6 0x2
+#define MX7D_PAD_ENET1_CRS__CSU_ALARM_AUT2                        0x0264 0x04D4 0x0000 0x7 0x0
+#define MX7D_PAD_ENET1_COL__ENET1_COL                             0x0268 0x04D8 0x0000 0x0 0x0
+#define MX7D_PAD_ENET1_COL__WDOG1_WDOG_ANY                        0x0268 0x04D8 0x0000 0x1 0x0
+#define MX7D_PAD_ENET1_COL__SAI1_TX_DATA0                         0x0268 0x04D8 0x0000 0x2 0x0
+#define MX7D_PAD_ENET1_COL__GPT2_CAPTURE2                         0x0268 0x04D8 0x0000 0x3 0x0
+#define MX7D_PAD_ENET1_COL__EPDC_PWR_CTRL1                        0x0268 0x04D8 0x0000 0x4 0x0
+#define MX7D_PAD_ENET1_COL__GPIO7_IO15                            0x0268 0x04D8 0x0000 0x5 0x0
+#define MX7D_PAD_ENET1_COL__CCM_EXT_CLK4                          0x0268 0x04D8 0x04F0 0x6 0x2
+#define MX7D_PAD_ENET1_COL__CSU_INT_DEB                           0x0268 0x04D8 0x0000 0x7 0x0
+
+#endif /* __DTS_IMX7D_PINFUNC_H */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/imx7ulp-pinfunc.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/imx7ulp-pinfunc.h
new file mode 100644
index 0000000000000000000000000000000000000000..777d7f094751fef48bcd1236a5673cc4bd739e7f
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/imx7ulp-pinfunc.h
@@ -0,0 +1,892 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 - 2018 NXP
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __DTS_IMX7ULP_PINFUNC_H
+#define __DTS_IMX7ULP_PINFUNC_H
+
+/*
+ * The pin function ID is a tuple of
+ * <mux_conf_reg input_reg mux_mode input_val>
+ */
+#define IMX7ULP_PAD_PTA0__CMP0_IN1_3V                                0x0000 0x0000 0x0 0x0
+#define IMX7ULP_PAD_PTA0__PTA0                                       0x0000 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTA0__LPSPI0_PCS1                                0x0000 0x0104 0x3 0x2
+#define IMX7ULP_PAD_PTA0__LPUART0_CTS_B                              0x0000 0x01F8 0x4 0x2
+#define IMX7ULP_PAD_PTA0__LPI2C0_SCL                                 0x0000 0x017C 0x5 0x2
+#define IMX7ULP_PAD_PTA0__TPM0_CLKIN                                 0x0000 0x01A8 0x6 0x2
+#define IMX7ULP_PAD_PTA0__I2S0_RX_BCLK                               0x0000 0x01B8 0x7 0x2
+#define IMX7ULP_PAD_PTA0__LLWU0_P0                                   0x0000 0x0000 0xd 0x0
+#define IMX7ULP_PAD_PTA1__CMP0_IN2_3V                                0x0004 0x0000 0x0 0x0
+#define IMX7ULP_PAD_PTA1__PTA1                                       0x0004 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTA1__LPSPI0_PCS2                                0x0004 0x0108 0x3 0x1
+#define IMX7ULP_PAD_PTA1__LPUART0_RTS_B                              0x0004 0x0000 0x4 0x0
+#define IMX7ULP_PAD_PTA1__LPI2C0_SDA                                 0x0004 0x0180 0x5 0x1
+#define IMX7ULP_PAD_PTA1__TPM0_CH0                                   0x0004 0x0138 0x6 0x1
+#define IMX7ULP_PAD_PTA1__I2S0_RX_FS                                 0x0004 0x01BC 0x7 0x1
+#define IMX7ULP_PAD_PTA2__CMP1_IN2_3V                                0x0008 0x0000 0x0 0x0
+#define IMX7ULP_PAD_PTA2__PTA2                                       0x0008 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTA2__LPSPI0_PCS3                                0x0008 0x010C 0x3 0x1
+#define IMX7ULP_PAD_PTA2__LPUART0_TX                                 0x0008 0x0200 0x4 0x1
+#define IMX7ULP_PAD_PTA2__LPI2C0_HREQ                                0x0008 0x0178 0x5 0x1
+#define IMX7ULP_PAD_PTA2__TPM0_CH1                                   0x0008 0x013C 0x6 0x1
+#define IMX7ULP_PAD_PTA2__I2S0_RXD0                                  0x0008 0x01DC 0x7 0x1
+#define IMX7ULP_PAD_PTA3__CMP1_IN4_3V                                0x000C 0x0000 0x0 0x0
+#define IMX7ULP_PAD_PTA3__PTA3                                       0x000C 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTA3__LPSPI0_PCS0                                0x000C 0x0100 0x3 0x1
+#define IMX7ULP_PAD_PTA3__LPUART0_RX                                 0x000C 0x01FC 0x4 0x1
+#define IMX7ULP_PAD_PTA3__TPM0_CH2                                   0x000C 0x0140 0x6 0x1
+#define IMX7ULP_PAD_PTA3__I2S0_RXD1                                  0x000C 0x01E0 0x7 0x1
+#define IMX7ULP_PAD_PTA3__CMP0_OUT                                   0x000C 0x0000 0xb 0x0
+#define IMX7ULP_PAD_PTA3__LLWU0_P1                                   0x000C 0x0000 0xd 0x0
+#define IMX7ULP_PAD_PTA4__ADC1_CH3A                                  0x0010 0x0000 0x0 0x0
+#define IMX7ULP_PAD_PTA4__PTA4                                       0x0010 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTA4__LPSPI0_SIN                                 0x0010 0x0114 0x3 0x1
+#define IMX7ULP_PAD_PTA4__LPUART1_CTS_B                              0x0010 0x0204 0x4 0x1
+#define IMX7ULP_PAD_PTA4__LPI2C1_SCL                                 0x0010 0x0188 0x5 0x1
+#define IMX7ULP_PAD_PTA4__TPM0_CH3                                   0x0010 0x0144 0x6 0x1
+#define IMX7ULP_PAD_PTA4__I2S0_MCLK                                  0x0010 0x01B4 0x7 0x1
+#define IMX7ULP_PAD_PTA5__ADC1_CH3B                                  0x0014 0x0000 0x0 0x0
+#define IMX7ULP_PAD_PTA5__PTA5                                       0x0014 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTA5__LPSPI0_SOUT                                0x0014 0x0118 0x3 0x1
+#define IMX7ULP_PAD_PTA5__LPUART1_RTS_B                              0x0014 0x0000 0x4 0x0
+#define IMX7ULP_PAD_PTA5__LPI2C1_SDA                                 0x0014 0x018C 0x5 0x1
+#define IMX7ULP_PAD_PTA5__TPM0_CH4                                   0x0014 0x0148 0x6 0x1
+#define IMX7ULP_PAD_PTA5__I2S0_TX_BCLK                               0x0014 0x01C0 0x7 0x1
+#define IMX7ULP_PAD_PTA6__ADC1_CH4A                                  0x0018 0x0000 0x0 0x0
+#define IMX7ULP_PAD_PTA6__PTA6                                       0x0018 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTA6__LPSPI0_SCK                                 0x0018 0x0110 0x3 0x1
+#define IMX7ULP_PAD_PTA6__LPUART1_TX                                 0x0018 0x020C 0x4 0x1
+#define IMX7ULP_PAD_PTA6__LPI2C1_HREQ                                0x0018 0x0184 0x5 0x1
+#define IMX7ULP_PAD_PTA6__TPM0_CH5                                   0x0018 0x014C 0x6 0x1
+#define IMX7ULP_PAD_PTA6__I2S0_TX_FS                                 0x0018 0x01C4 0x7 0x1
+#define IMX7ULP_PAD_PTA7__ADC1_CH4B                                  0x001C 0x0000 0x0 0x0
+#define IMX7ULP_PAD_PTA7__PTA7                                       0x001C 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTA7__LPUART1_RX                                 0x001C 0x0208 0x4 0x1
+#define IMX7ULP_PAD_PTA7__TPM1_CH1                                   0x001C 0x0154 0x6 0x1
+#define IMX7ULP_PAD_PTA7__I2S0_TXD0                                  0x001C 0x0000 0x7 0x0
+#define IMX7ULP_PAD_PTA8__ADC1_CH5A                                  0x0020 0x0000 0x0 0x0
+#define IMX7ULP_PAD_PTA8__PTA8                                       0x0020 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTA8__LPSPI1_PCS1                                0x0020 0x0120 0x3 0x1
+#define IMX7ULP_PAD_PTA8__LPUART2_CTS_B                              0x0020 0x0210 0x4 0x1
+#define IMX7ULP_PAD_PTA8__LPI2C2_SCL                                 0x0020 0x0194 0x5 0x1
+#define IMX7ULP_PAD_PTA8__TPM1_CLKIN                                 0x0020 0x01AC 0x6 0x1
+#define IMX7ULP_PAD_PTA8__I2S0_TXD1                                  0x0020 0x0000 0x7 0x0
+#define IMX7ULP_PAD_PTA9__ADC1_CH5B                                  0x0024 0x0000 0x0 0x0
+#define IMX7ULP_PAD_PTA9__PTA9                                       0x0024 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTA9__LPSPI1_PCS2                                0x0024 0x0124 0x3 0x1
+#define IMX7ULP_PAD_PTA9__LPUART2_RTS_B                              0x0024 0x0000 0x4 0x0
+#define IMX7ULP_PAD_PTA9__LPI2C2_SDA                                 0x0024 0x0198 0x5 0x1
+#define IMX7ULP_PAD_PTA9__TPM1_CH0                                   0x0024 0x0150 0x6 0x1
+#define IMX7ULP_PAD_PTA9__NMI0_B                                     0x0024 0x0000 0xb 0x0
+#define IMX7ULP_PAD_PTA10__ADC1_CH6A                                 0x0028 0x0000 0x0 0x0
+#define IMX7ULP_PAD_PTA10__PTA10                                     0x0028 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTA10__LPSPI1_PCS3                               0x0028 0x0128 0x3 0x1
+#define IMX7ULP_PAD_PTA10__LPUART2_TX                                0x0028 0x0218 0x4 0x1
+#define IMX7ULP_PAD_PTA10__LPI2C2_HREQ                               0x0028 0x0190 0x5 0x1
+#define IMX7ULP_PAD_PTA10__TPM2_CLKIN                                0x0028 0x01F4 0x6 0x1
+#define IMX7ULP_PAD_PTA10__I2S0_RX_BCLK                              0x0028 0x01B8 0x7 0x1
+#define IMX7ULP_PAD_PTA11__ADC1_CH6B                                 0x002C 0x0000 0x0 0x0
+#define IMX7ULP_PAD_PTA11__PTA11                                     0x002C 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTA11__LPUART2_RX                                0x002C 0x0214 0x4 0x1
+#define IMX7ULP_PAD_PTA11__TPM2_CH0                                  0x002C 0x0158 0x6 0x1
+#define IMX7ULP_PAD_PTA11__I2S0_RX_FS                                0x002C 0x01BC 0x7 0x2
+#define IMX7ULP_PAD_PTA12__ADC1_CH7A                                 0x0030 0x0000 0x0 0x0
+#define IMX7ULP_PAD_PTA12__PTA12                                     0x0030 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTA12__LPSPI1_SIN                                0x0030 0x0130 0x3 0x1
+#define IMX7ULP_PAD_PTA12__LPUART3_CTS_B                             0x0030 0x021C 0x4 0x1
+#define IMX7ULP_PAD_PTA12__LPI2C3_SCL                                0x0030 0x01A0 0x5 0x1
+#define IMX7ULP_PAD_PTA12__TPM2_CH1                                  0x0030 0x015C 0x6 0x1
+#define IMX7ULP_PAD_PTA12__I2S0_RXD0                                 0x0030 0x01DC 0x7 0x2
+#define IMX7ULP_PAD_PTA13__ADC1_CH7B                                 0x0034 0x0000 0x0 0x0
+#define IMX7ULP_PAD_PTA13__PTA13                                     0x0034 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTA13__LPSPI1_SOUT                               0x0034 0x0134 0x3 0x2
+#define IMX7ULP_PAD_PTA13__LPUART3_RTS_B                             0x0034 0x0000 0x4 0x0
+#define IMX7ULP_PAD_PTA13__LPI2C3_SDA                                0x0034 0x01A4 0x5 0x2
+#define IMX7ULP_PAD_PTA13__TPM3_CLKIN                                0x0034 0x01B0 0x6 0x1
+#define IMX7ULP_PAD_PTA13__I2S0_RXD1                                 0x0034 0x01E0 0x7 0x2
+#define IMX7ULP_PAD_PTA13__CMP0_OUT                                  0x0034 0x0000 0xb 0x0
+#define IMX7ULP_PAD_PTA13__LLWU0_P2                                  0x0034 0x0000 0xd 0x0
+#define IMX7ULP_PAD_PTA14__ADC1_CH8A                                 0x0038 0x0000 0x0 0x0
+#define IMX7ULP_PAD_PTA14__PTA14                                     0x0038 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTA14__LPSPI1_SCK                                0x0038 0x012C 0x3 0x2
+#define IMX7ULP_PAD_PTA14__LPUART3_TX                                0x0038 0x0224 0x4 0x2
+#define IMX7ULP_PAD_PTA14__LPI2C3_HREQ                               0x0038 0x019C 0x5 0x2
+#define IMX7ULP_PAD_PTA14__TPM3_CH0                                  0x0038 0x0160 0x6 0x1
+#define IMX7ULP_PAD_PTA14__I2S0_MCLK                                 0x0038 0x01B4 0x7 0x2
+#define IMX7ULP_PAD_PTA14__LLWU0_P3                                  0x0038 0x0000 0xd 0x0
+#define IMX7ULP_PAD_PTA15__ADC1_CH8B                                 0x003C 0x0000 0x0 0x0
+#define IMX7ULP_PAD_PTA15__PTA15                                     0x003C 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTA15__LPSPI1_PCS0                               0x003C 0x011C 0x3 0x1
+#define IMX7ULP_PAD_PTA15__LPUART3_RX                                0x003C 0x0220 0x4 0x1
+#define IMX7ULP_PAD_PTA15__TPM3_CH1                                  0x003C 0x0164 0x6 0x1
+#define IMX7ULP_PAD_PTA15__I2S0_TX_BCLK                              0x003C 0x01C0 0x7 0x2
+#define IMX7ULP_PAD_PTA16__CMP1_IN5_3V                               0x0040 0x0000 0x0 0x0
+#define IMX7ULP_PAD_PTA16__PTA16                                     0x0040 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTA16__FXIO0_D0                                  0x0040 0x0000 0x2 0x0
+#define IMX7ULP_PAD_PTA16__LPSPI0_SOUT                               0x0040 0x0118 0x3 0x2
+#define IMX7ULP_PAD_PTA16__LPUART0_CTS_B                             0x0040 0x01F8 0x4 0x1
+#define IMX7ULP_PAD_PTA16__LPI2C0_SCL                                0x0040 0x017C 0x5 0x1
+#define IMX7ULP_PAD_PTA16__TPM3_CH2                                  0x0040 0x0168 0x6 0x1
+#define IMX7ULP_PAD_PTA16__I2S0_TX_FS                                0x0040 0x01C4 0x7 0x2
+#define IMX7ULP_PAD_PTA17__CMP1_IN6_3V                               0x0044 0x0000 0x0 0x0
+#define IMX7ULP_PAD_PTA17__PTA17                                     0x0044 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTA17__FXIO0_D1                                  0x0044 0x0000 0x2 0x0
+#define IMX7ULP_PAD_PTA17__LPSPI0_SCK                                0x0044 0x0110 0x3 0x2
+#define IMX7ULP_PAD_PTA17__LPUART0_RTS_B                             0x0044 0x0000 0x4 0x0
+#define IMX7ULP_PAD_PTA17__LPI2C0_SDA                                0x0044 0x0180 0x5 0x2
+#define IMX7ULP_PAD_PTA17__TPM3_CH3                                  0x0044 0x016C 0x6 0x1
+#define IMX7ULP_PAD_PTA17__I2S0_TXD0                                 0x0044 0x0000 0x7 0x0
+#define IMX7ULP_PAD_PTA18__CMP1_IN1_3V                               0x0048 0x0000 0x0 0x0
+#define IMX7ULP_PAD_PTA18__PTA18                                     0x0048 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTA18__FXIO0_D2                                  0x0048 0x0000 0x2 0x0
+#define IMX7ULP_PAD_PTA18__LPSPI0_PCS0                               0x0048 0x0100 0x3 0x2
+#define IMX7ULP_PAD_PTA18__LPUART0_TX                                0x0048 0x0200 0x4 0x2
+#define IMX7ULP_PAD_PTA18__LPI2C0_HREQ                               0x0048 0x0178 0x5 0x2
+#define IMX7ULP_PAD_PTA18__TPM3_CH4                                  0x0048 0x0170 0x6 0x1
+#define IMX7ULP_PAD_PTA18__I2S0_TXD1                                 0x0048 0x0000 0x7 0x0
+#define IMX7ULP_PAD_PTA18__LLWU0_P4                                  0x0048 0x0000 0xd 0x0
+#define IMX7ULP_PAD_PTA19__CMP1_IN3_3V                               0x004C 0x0000 0x0 0x0
+#define IMX7ULP_PAD_PTA19__PTA19                                     0x004C 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTA19__FXIO0_D3                                  0x004C 0x0000 0x2 0x0
+#define IMX7ULP_PAD_PTA19__LPUART0_RX                                0x004C 0x01FC 0x4 0x2
+#define IMX7ULP_PAD_PTA19__TPM3_CH5                                  0x004C 0x0174 0x6 0x1
+#define IMX7ULP_PAD_PTA19__I2S1_RX_BCLK                              0x004C 0x01CC 0x7 0x1
+#define IMX7ULP_PAD_PTA19__LPTMR0_ALT3                               0x004C 0x0000 0xb 0x0
+#define IMX7ULP_PAD_PTA19__LLWU0_P5                                  0x004C 0x0000 0xd 0x0
+#define IMX7ULP_PAD_PTA20__ADC0_CH10A                                0x0050 0x0000 0x0 0x0
+#define IMX7ULP_PAD_PTA20__PTA20                                     0x0050 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTA20__FXIO0_D4                                  0x0050 0x0000 0x2 0x0
+#define IMX7ULP_PAD_PTA20__LPSPI0_SIN                                0x0050 0x0114 0x3 0x2
+#define IMX7ULP_PAD_PTA20__LPUART1_CTS_B                             0x0050 0x0204 0x4 0x2
+#define IMX7ULP_PAD_PTA20__LPI2C1_SCL                                0x0050 0x0188 0x5 0x2
+#define IMX7ULP_PAD_PTA20__TPM0_CLKIN                                0x0050 0x01A8 0x6 0x1
+#define IMX7ULP_PAD_PTA20__I2S1_RX_FS                                0x0050 0x01D0 0x7 0x1
+#define IMX7ULP_PAD_PTA21__ADC0_CH10B                                0x0054 0x0000 0x0 0x0
+#define IMX7ULP_PAD_PTA21__PTA21                                     0x0054 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTA21__FXIO0_D5                                  0x0054 0x0000 0x2 0x0
+#define IMX7ULP_PAD_PTA21__LPSPI0_PCS1                               0x0054 0x0104 0x3 0x1
+#define IMX7ULP_PAD_PTA21__LPUART1_RTS_B                             0x0054 0x0000 0x4 0x0
+#define IMX7ULP_PAD_PTA21__LPI2C1_SDA                                0x0054 0x018C 0x5 0x2
+#define IMX7ULP_PAD_PTA21__TPM0_CH0                                  0x0054 0x0138 0x6 0x2
+#define IMX7ULP_PAD_PTA21__I2S1_RXD0                                 0x0054 0x01E4 0x7 0x1
+#define IMX7ULP_PAD_PTA22__ADC0_CH9A                                 0x0058 0x0000 0x0 0x0
+#define IMX7ULP_PAD_PTA22__PTA22                                     0x0058 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTA22__FXIO0_D6                                  0x0058 0x0000 0x2 0x0
+#define IMX7ULP_PAD_PTA22__LPSPI0_PCS2                               0x0058 0x0108 0x3 0x2
+#define IMX7ULP_PAD_PTA22__LPUART1_TX                                0x0058 0x020C 0x4 0x2
+#define IMX7ULP_PAD_PTA22__LPI2C1_HREQ                               0x0058 0x0184 0x5 0x2
+#define IMX7ULP_PAD_PTA22__TPM0_CH1                                  0x0058 0x013C 0x6 0x2
+#define IMX7ULP_PAD_PTA22__I2S1_RXD1                                 0x0058 0x01E8 0x7 0x1
+#define IMX7ULP_PAD_PTA22__LPTMR0_ALT2                               0x0058 0x0000 0xb 0x0
+#define IMX7ULP_PAD_PTA22__EWM_OUT_B                                 0x0058 0x0000 0xc 0x0
+#define IMX7ULP_PAD_PTA23__ADC0_CH9B                                 0x005C 0x0000 0x0 0x0
+#define IMX7ULP_PAD_PTA23__PTA23                                     0x005C 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTA23__FXIO0_D7                                  0x005C 0x0000 0x2 0x0
+#define IMX7ULP_PAD_PTA23__LPSPI0_PCS3                               0x005C 0x010C 0x3 0x2
+#define IMX7ULP_PAD_PTA23__LPUART1_RX                                0x005C 0x0208 0x4 0x2
+#define IMX7ULP_PAD_PTA23__TPM0_CH2                                  0x005C 0x0140 0x6 0x2
+#define IMX7ULP_PAD_PTA23__I2S1_MCLK                                 0x005C 0x01C8 0x7 0x1
+#define IMX7ULP_PAD_PTA23__LLWU0_P6                                  0x005C 0x0000 0xd 0x0
+#define IMX7ULP_PAD_PTA24__ADC0_CH8A                                 0x0060 0x0000 0x0 0x0
+#define IMX7ULP_PAD_PTA24__PTA24                                     0x0060 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTA24__FXIO0_D8                                  0x0060 0x0000 0x2 0x0
+#define IMX7ULP_PAD_PTA24__LPSPI1_PCS1                               0x0060 0x0120 0x3 0x2
+#define IMX7ULP_PAD_PTA24__LPUART2_CTS_B                             0x0060 0x0210 0x4 0x2
+#define IMX7ULP_PAD_PTA24__LPI2C2_SCL                                0x0060 0x0194 0x5 0x2
+#define IMX7ULP_PAD_PTA24__TPM0_CH3                                  0x0060 0x0144 0x6 0x2
+#define IMX7ULP_PAD_PTA24__I2S1_TX_BCLK                              0x0060 0x01D4 0x7 0x1
+#define IMX7ULP_PAD_PTA25__ADC0_CH8B                                 0x0064 0x0000 0x0 0x0
+#define IMX7ULP_PAD_PTA25__PTA25                                     0x0064 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTA25__FXIO0_D9                                  0x0064 0x0000 0x2 0x0
+#define IMX7ULP_PAD_PTA25__LPSPI1_PCS2                               0x0064 0x0124 0x3 0x2
+#define IMX7ULP_PAD_PTA25__LPUART2_RTS_B                             0x0064 0x0000 0x4 0x0
+#define IMX7ULP_PAD_PTA25__LPI2C2_SDA                                0x0064 0x0198 0x5 0x2
+#define IMX7ULP_PAD_PTA25__TPM0_CH4                                  0x0064 0x0148 0x6 0x2
+#define IMX7ULP_PAD_PTA25__I2S1_TX_FS                                0x0064 0x01D8 0x7 0x1
+#define IMX7ULP_PAD_PTA26__PTA26                                     0x0068 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTA26__JTAG_TMS_SWD_DIO                          0x0068 0x0000 0xa 0x0
+#define IMX7ULP_PAD_PTA26__FXIO0_D10                                 0x0068 0x0000 0x2 0x0
+#define IMX7ULP_PAD_PTA26__LPSPI1_PCS3                               0x0068 0x0128 0x3 0x2
+#define IMX7ULP_PAD_PTA26__LPUART2_TX                                0x0068 0x0218 0x4 0x2
+#define IMX7ULP_PAD_PTA26__LPI2C2_HREQ                               0x0068 0x0190 0x5 0x2
+#define IMX7ULP_PAD_PTA26__TPM0_CH5                                  0x0068 0x014C 0x6 0x2
+#define IMX7ULP_PAD_PTA26__I2S1_RXD2                                 0x0068 0x01EC 0x7 0x1
+#define IMX7ULP_PAD_PTA27__PTA27                                     0x006C 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTA27__JTAG_TDO                                  0x006C 0x0000 0xa 0x0
+#define IMX7ULP_PAD_PTA27__FXIO0_D11                                 0x006C 0x0000 0x2 0x0
+#define IMX7ULP_PAD_PTA27__LPUART2_RX                                0x006C 0x0214 0x4 0x2
+#define IMX7ULP_PAD_PTA27__TPM1_CH1                                  0x006C 0x0154 0x6 0x2
+#define IMX7ULP_PAD_PTA27__I2S1_RXD3                                 0x006C 0x01F0 0x7 0x1
+#define IMX7ULP_PAD_PTA28__PTA28                                     0x0070 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTA28__JTAG_TDI                                  0x0070 0x0000 0xa 0x0
+#define IMX7ULP_PAD_PTA28__FXIO0_D12                                 0x0070 0x0000 0x2 0x0
+#define IMX7ULP_PAD_PTA28__LPSPI1_SIN                                0x0070 0x0130 0x3 0x2
+#define IMX7ULP_PAD_PTA28__LPUART3_CTS_B                             0x0070 0x021C 0x4 0x2
+#define IMX7ULP_PAD_PTA28__LPI2C3_SCL                                0x0070 0x01A0 0x5 0x2
+#define IMX7ULP_PAD_PTA28__TPM1_CLKIN                                0x0070 0x01AC 0x6 0x2
+#define IMX7ULP_PAD_PTA28__I2S1_TXD2                                 0x0070 0x0000 0x7 0x0
+#define IMX7ULP_PAD_PTA29__PTA29                                     0x0074 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTA29__JTAG_TCLK_SWD_CLK                         0x0074 0x0000 0xa 0x0
+#define IMX7ULP_PAD_PTA29__FXIO0_D13                                 0x0074 0x0000 0x2 0x0
+#define IMX7ULP_PAD_PTA29__LPSPI1_SOUT                               0x0074 0x0134 0x3 0x1
+#define IMX7ULP_PAD_PTA29__LPUART3_RTS_B                             0x0074 0x0000 0x4 0x0
+#define IMX7ULP_PAD_PTA29__LPI2C3_SDA                                0x0074 0x01A4 0x5 0x1
+#define IMX7ULP_PAD_PTA29__TPM1_CH0                                  0x0074 0x0150 0x6 0x2
+#define IMX7ULP_PAD_PTA29__I2S1_TXD3                                 0x0074 0x0000 0x7 0x0
+#define IMX7ULP_PAD_PTA30__ADC0_CH1A                                 0x0078 0x0000 0x0 0x0
+#define IMX7ULP_PAD_PTA30__PTA30                                     0x0078 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTA30__FXIO0_D14                                 0x0078 0x0000 0x2 0x0
+#define IMX7ULP_PAD_PTA30__LPSPI1_SCK                                0x0078 0x012C 0x3 0x1
+#define IMX7ULP_PAD_PTA30__LPUART3_TX                                0x0078 0x0224 0x4 0x1
+#define IMX7ULP_PAD_PTA30__LPI2C3_HREQ                               0x0078 0x019C 0x5 0x1
+#define IMX7ULP_PAD_PTA30__TPM2_CLKIN                                0x0078 0x01F4 0x6 0x2
+#define IMX7ULP_PAD_PTA30__I2S1_TXD0                                 0x0078 0x0000 0x7 0x0
+#define IMX7ULP_PAD_PTA30__JTAG_TRST_B                               0x0078 0x0000 0xa 0x0
+#define IMX7ULP_PAD_PTA31__ADC0_CH1B                                 0x007C 0x0000 0x0 0x0
+#define IMX7ULP_PAD_PTA31__PTA31                                     0x007C 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTA31__FXIO0_D15                                 0x007C 0x0000 0x2 0x0
+#define IMX7ULP_PAD_PTA31__LPSPI1_PCS0                               0x007C 0x011C 0x3 0x2
+#define IMX7ULP_PAD_PTA31__LPUART3_RX                                0x007C 0x0220 0x4 0x2
+#define IMX7ULP_PAD_PTA31__TPM2_CH0                                  0x007C 0x0158 0x6 0x2
+#define IMX7ULP_PAD_PTA31__I2S1_TXD1                                 0x007C 0x0000 0x7 0x0
+#define IMX7ULP_PAD_PTA31__LPTMR0_ALT1                               0x007C 0x0000 0xb 0x0
+#define IMX7ULP_PAD_PTA31__EWM_IN                                    0x007C 0x0228 0xc 0x1
+#define IMX7ULP_PAD_PTA31__LLWU0_P7                                  0x007C 0x0000 0xd 0x0
+#define IMX7ULP_PAD_PTB0__ADC0_CH0A                                  0x0080 0x0000 0x0 0x0
+#define IMX7ULP_PAD_PTB0__PTB0                                       0x0080 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTB0__FXIO0_D16                                  0x0080 0x0000 0x2 0x0
+#define IMX7ULP_PAD_PTB0__LPSPI0_SIN                                 0x0080 0x0114 0x3 0x3
+#define IMX7ULP_PAD_PTB0__LPUART0_TX                                 0x0080 0x0200 0x4 0x3
+#define IMX7ULP_PAD_PTB0__TPM2_CH1                                   0x0080 0x015C 0x6 0x2
+#define IMX7ULP_PAD_PTB0__CLKOUT0                                    0x0080 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTB0__CMP1_OUT                                   0x0080 0x0000 0xb 0x0
+#define IMX7ULP_PAD_PTB0__EWM_OUT_B                                  0x0080 0x0000 0xc 0x0
+#define IMX7ULP_PAD_PTB1__ADC0_CH0B                                  0x0084 0x0000 0x0 0x0
+#define IMX7ULP_PAD_PTB1__PTB1                                       0x0084 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTB1__FXIO0_D17                                  0x0084 0x0000 0x2 0x0
+#define IMX7ULP_PAD_PTB1__LPSPI0_SOUT                                0x0084 0x0118 0x3 0x3
+#define IMX7ULP_PAD_PTB1__LPUART0_RX                                 0x0084 0x01FC 0x4 0x3
+#define IMX7ULP_PAD_PTB1__TPM3_CLKIN                                 0x0084 0x01B0 0x6 0x3
+#define IMX7ULP_PAD_PTB1__I2S1_TX_BCLK                               0x0084 0x01D4 0x7 0x2
+#define IMX7ULP_PAD_PTB1__RTC_CLKOUT                                 0x0084 0x0000 0xb 0x0
+#define IMX7ULP_PAD_PTB1__EWM_IN                                     0x0084 0x0228 0xc 0x2
+#define IMX7ULP_PAD_PTB1__LLWU0_P8                                   0x0084 0x0000 0xd 0x0
+#define IMX7ULP_PAD_PTB2__ADC0_CH6A                                  0x0088 0x0000 0x0 0x0
+#define IMX7ULP_PAD_PTB2__PTB2                                       0x0088 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTB2__FXIO0_D18                                  0x0088 0x0000 0x2 0x0
+#define IMX7ULP_PAD_PTB2__LPSPI0_SCK                                 0x0088 0x0110 0x3 0x3
+#define IMX7ULP_PAD_PTB2__LPUART1_TX                                 0x0088 0x020C 0x4 0x3
+#define IMX7ULP_PAD_PTB2__TPM3_CH0                                   0x0088 0x0160 0x6 0x2
+#define IMX7ULP_PAD_PTB2__I2S1_TX_FS                                 0x0088 0x01D8 0x7 0x2
+#define IMX7ULP_PAD_PTB2__TRACE_CLKOUT                               0x0088 0x0000 0xa 0x0
+#define IMX7ULP_PAD_PTB3__ADC0_CH6B                                  0x008C 0x0000 0x0 0x0
+#define IMX7ULP_PAD_PTB3__PTB3                                       0x008C 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTB3__FXIO0_D19                                  0x008C 0x0000 0x2 0x0
+#define IMX7ULP_PAD_PTB3__LPSPI0_PCS0                                0x008C 0x0100 0x3 0x3
+#define IMX7ULP_PAD_PTB3__LPUART1_RX                                 0x008C 0x0208 0x4 0x3
+#define IMX7ULP_PAD_PTB3__TPM3_CH1                                   0x008C 0x0164 0x6 0x2
+#define IMX7ULP_PAD_PTB3__I2S1_TXD0                                  0x008C 0x0000 0x7 0x0
+#define IMX7ULP_PAD_PTB3__TRACE_D0                                   0x008C 0x0000 0xa 0x0
+#define IMX7ULP_PAD_PTB3__LPTMR1_ALT2                                0x008C 0x0000 0xb 0x0
+#define IMX7ULP_PAD_PTB3__LLWU0_P9                                   0x008C 0x0000 0xd 0x0
+#define IMX7ULP_PAD_PTB4__PTB4                                       0x0090 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTB4__FXIO0_D20                                  0x0090 0x0000 0x2 0x0
+#define IMX7ULP_PAD_PTB4__LPSPI0_PCS1                                0x0090 0x0104 0x3 0x3
+#define IMX7ULP_PAD_PTB4__LPUART2_TX                                 0x0090 0x0218 0x4 0x3
+#define IMX7ULP_PAD_PTB4__LPI2C0_HREQ                                0x0090 0x0178 0x5 0x3
+#define IMX7ULP_PAD_PTB4__TPM3_CH2                                   0x0090 0x0168 0x6 0x2
+#define IMX7ULP_PAD_PTB4__I2S1_TXD1                                  0x0090 0x0000 0x7 0x0
+#define IMX7ULP_PAD_PTB4__QSPIA_DATA7                                0x0090 0x0000 0x8 0x0
+#define IMX7ULP_PAD_PTB4__TRACE_D1                                   0x0090 0x0000 0xa 0x0
+#define IMX7ULP_PAD_PTB4__SEC_VIO_B                                  0x0090 0x0000 0xb 0x0
+#define IMX7ULP_PAD_PTB5__PTB5                                       0x0094 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTB5__FXIO0_D21                                  0x0094 0x0000 0x2 0x0
+#define IMX7ULP_PAD_PTB5__LPSPI0_PCS2                                0x0094 0x0108 0x3 0x3
+#define IMX7ULP_PAD_PTB5__LPUART2_RX                                 0x0094 0x0214 0x4 0x3
+#define IMX7ULP_PAD_PTB5__LPI2C1_HREQ                                0x0094 0x0184 0x5 0x3
+#define IMX7ULP_PAD_PTB5__TPM3_CH3                                   0x0094 0x016C 0x6 0x2
+#define IMX7ULP_PAD_PTB5__I2S1_TXD2                                  0x0094 0x0000 0x7 0x0
+#define IMX7ULP_PAD_PTB5__QSPIA_DATA6                                0x0094 0x0000 0x8 0x0
+#define IMX7ULP_PAD_PTB5__TRACE_D2                                   0x0094 0x0000 0xa 0x0
+#define IMX7ULP_PAD_PTB5__RTC_CLKOUT                                 0x0094 0x0000 0xb 0x0
+#define IMX7ULP_PAD_PTB6__ADC1_CH1A                                  0x0098 0x0000 0x0 0x0
+#define IMX7ULP_PAD_PTB6__PTB6                                       0x0098 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTB6__FXIO0_D22                                  0x0098 0x0000 0x2 0x0
+#define IMX7ULP_PAD_PTB6__LPSPI0_PCS3                                0x0098 0x010C 0x3 0x3
+#define IMX7ULP_PAD_PTB6__LPUART3_TX                                 0x0098 0x0224 0x4 0x3
+#define IMX7ULP_PAD_PTB6__LPI2C0_SCL                                 0x0098 0x017C 0x5 0x3
+#define IMX7ULP_PAD_PTB6__TPM3_CH4                                   0x0098 0x0170 0x6 0x2
+#define IMX7ULP_PAD_PTB6__I2S1_TXD3                                  0x0098 0x0000 0x7 0x0
+#define IMX7ULP_PAD_PTB6__QSPIA_DATA5                                0x0098 0x0000 0x8 0x0
+#define IMX7ULP_PAD_PTB6__TRACE_D3                                   0x0098 0x0000 0xa 0x0
+#define IMX7ULP_PAD_PTB6__LPTMR1_ALT3                                0x0098 0x0000 0xb 0x0
+#define IMX7ULP_PAD_PTB6__LLWU0_P10                                  0x0098 0x0000 0xd 0x0
+#define IMX7ULP_PAD_PTB7__ADC1_CH1B                                  0x009C 0x0000 0x0 0x0
+#define IMX7ULP_PAD_PTB7__PTB7                                       0x009C 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTB7__FXIO0_D23                                  0x009C 0x0000 0x2 0x0
+#define IMX7ULP_PAD_PTB7__LPSPI1_SIN                                 0x009C 0x0130 0x3 0x3
+#define IMX7ULP_PAD_PTB7__LPUART3_RX                                 0x009C 0x0220 0x4 0x3
+#define IMX7ULP_PAD_PTB7__LPI2C0_SDA                                 0x009C 0x0180 0x5 0x3
+#define IMX7ULP_PAD_PTB7__TPM3_CH5                                   0x009C 0x0174 0x6 0x2
+#define IMX7ULP_PAD_PTB7__I2S1_MCLK                                  0x009C 0x01C8 0x7 0x2
+#define IMX7ULP_PAD_PTB7__QSPIA_SS1_B                                0x009C 0x0000 0x8 0x0
+#define IMX7ULP_PAD_PTB7__CMP1_OUT                                   0x009C 0x0000 0xb 0x0
+#define IMX7ULP_PAD_PTB7__LLWU0_P11                                  0x009C 0x0000 0xd 0x0
+#define IMX7ULP_PAD_PTB8__ADC0_CH14A_CMP0_IN0                        0x00A0 0x0000 0x0 0x0
+#define IMX7ULP_PAD_PTB8__PTB8                                       0x00A0 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTB8__FXIO0_D24                                  0x00A0 0x0000 0x2 0x0
+#define IMX7ULP_PAD_PTB8__LPSPI1_SOUT                                0x00A0 0x0134 0x3 0x3
+#define IMX7ULP_PAD_PTB8__LPI2C1_SCL                                 0x00A0 0x0188 0x5 0x3
+#define IMX7ULP_PAD_PTB8__TPM0_CLKIN                                 0x00A0 0x01A8 0x6 0x3
+#define IMX7ULP_PAD_PTB8__I2S1_RX_BCLK                               0x00A0 0x01CC 0x7 0x2
+#define IMX7ULP_PAD_PTB8__QSPIA_SS0_B                                0x00A0 0x0000 0x8 0x0
+#define IMX7ULP_PAD_PTB8__RTC_CLKOUT                                 0x00A0 0x0000 0xb 0x0
+#define IMX7ULP_PAD_PTB9__ADC0_CH14B_CMP0_IN2                        0x00A4 0x0000 0x0 0x0
+#define IMX7ULP_PAD_PTB9__PTB9                                       0x00A4 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTB9__FXIO0_D25                                  0x00A4 0x0000 0x2 0x0
+#define IMX7ULP_PAD_PTB9__LPSPI1_SCK                                 0x00A4 0x012C 0x3 0x3
+#define IMX7ULP_PAD_PTB9__LPI2C1_SDA                                 0x00A4 0x018C 0x5 0x3
+#define IMX7ULP_PAD_PTB9__TPM0_CH0                                   0x00A4 0x0138 0x6 0x3
+#define IMX7ULP_PAD_PTB9__I2S1_RX_FS                                 0x00A4 0x01D0 0x7 0x2
+#define IMX7ULP_PAD_PTB9__QSPIA_DQS                                  0x00A4 0x0000 0x8 0x0
+#define IMX7ULP_PAD_PTB9__LLWU0_P12                                  0x00A4 0x0000 0xd 0x0
+#define IMX7ULP_PAD_PTB10__CMP0_IN1                                  0x00A8 0x0000 0x0 0x0
+#define IMX7ULP_PAD_PTB10__PTB10                                     0x00A8 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTB10__FXIO0_D26                                 0x00A8 0x0000 0x2 0x0
+#define IMX7ULP_PAD_PTB10__LPSPI1_PCS0                               0x00A8 0x011C 0x3 0x3
+#define IMX7ULP_PAD_PTB10__LPI2C2_SCL                                0x00A8 0x0194 0x5 0x3
+#define IMX7ULP_PAD_PTB10__TPM0_CH1                                  0x00A8 0x013C 0x6 0x3
+#define IMX7ULP_PAD_PTB10__I2S1_RXD0                                 0x00A8 0x01E4 0x7 0x2
+#define IMX7ULP_PAD_PTB10__TRACE_D4                                  0x00A8 0x0000 0xa 0x0
+#define IMX7ULP_PAD_PTB11__CMP0_IN3                                  0x00AC 0x0000 0x0 0x0
+#define IMX7ULP_PAD_PTB11__PTB11                                     0x00AC 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTB11__FXIO0_D27                                 0x00AC 0x0000 0x2 0x0
+#define IMX7ULP_PAD_PTB11__LPSPI1_PCS1                               0x00AC 0x0120 0x3 0x3
+#define IMX7ULP_PAD_PTB11__LPI2C2_SDA                                0x00AC 0x0198 0x5 0x3
+#define IMX7ULP_PAD_PTB11__TPM1_CLKIN                                0x00AC 0x01AC 0x6 0x3
+#define IMX7ULP_PAD_PTB11__I2S1_RXD1                                 0x00AC 0x01E8 0x7 0x2
+#define IMX7ULP_PAD_PTB11__TRACE_D5                                  0x00AC 0x0000 0xa 0x0
+#define IMX7ULP_PAD_PTB12__ADC1_CH13A_CMP1_IN0                       0x00B0 0x0000 0x0 0x0
+#define IMX7ULP_PAD_PTB12__PTB12                                     0x00B0 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTB12__FXIO0_D28                                 0x00B0 0x0000 0x2 0x0
+#define IMX7ULP_PAD_PTB12__LPSPI1_PCS2                               0x00B0 0x0124 0x3 0x3
+#define IMX7ULP_PAD_PTB12__LPUART2_TX                                0x00B0 0x0218 0x4 0x4
+#define IMX7ULP_PAD_PTB12__LPI2C3_SCL                                0x00B0 0x01A0 0x5 0x3
+#define IMX7ULP_PAD_PTB12__TPM1_CH0                                  0x00B0 0x0150 0x6 0x3
+#define IMX7ULP_PAD_PTB12__I2S1_RXD2                                 0x00B0 0x01EC 0x7 0x2
+#define IMX7ULP_PAD_PTB12__TRACE_D6                                  0x00B0 0x0000 0xa 0x0
+#define IMX7ULP_PAD_PTB13__ADC1_CH13B_CMP1_IN1                       0x00B4 0x0000 0x0 0x0
+#define IMX7ULP_PAD_PTB13__PTB13                                     0x00B4 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTB13__FXIO0_D29                                 0x00B4 0x0000 0x2 0x0
+#define IMX7ULP_PAD_PTB13__LPSPI1_PCS3                               0x00B4 0x0128 0x3 0x3
+#define IMX7ULP_PAD_PTB13__LPUART2_RX                                0x00B4 0x0214 0x4 0x4
+#define IMX7ULP_PAD_PTB13__LPI2C3_SDA                                0x00B4 0x01A4 0x5 0x3
+#define IMX7ULP_PAD_PTB13__TPM1_CH1                                  0x00B4 0x0154 0x6 0x3
+#define IMX7ULP_PAD_PTB13__I2S1_RXD3                                 0x00B4 0x01F0 0x7 0x2
+#define IMX7ULP_PAD_PTB13__QSPIA_DATA4                               0x00B4 0x0000 0x8 0x0
+#define IMX7ULP_PAD_PTB13__TRACE_D7                                  0x00B4 0x0000 0xa 0x0
+#define IMX7ULP_PAD_PTB14__ADC1_CH2A                                 0x00B8 0x0000 0x0 0x0
+#define IMX7ULP_PAD_PTB14__PTB14                                     0x00B8 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTB14__FXIO0_D30                                 0x00B8 0x0000 0x2 0x0
+#define IMX7ULP_PAD_PTB14__LPI2C2_HREQ                               0x00B8 0x0190 0x5 0x3
+#define IMX7ULP_PAD_PTB14__TPM2_CLKIN                                0x00B8 0x01F4 0x6 0x3
+#define IMX7ULP_PAD_PTB14__QSPIA_SS1_B                               0x00B8 0x0000 0x8 0x0
+#define IMX7ULP_PAD_PTB14__QSPIA_SCLK_B                              0x00B8 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTB14__RTC_CLKOUT                                0x00B8 0x0000 0xb 0x0
+#define IMX7ULP_PAD_PTB14__LLWU0_P13                                 0x00B8 0x0000 0xd 0x0
+#define IMX7ULP_PAD_PTB15__ADC1_CH2B                                 0x00BC 0x0000 0x0 0x0
+#define IMX7ULP_PAD_PTB15__PTB15                                     0x00BC 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTB15__FXIO0_D31                                 0x00BC 0x0000 0x2 0x0
+#define IMX7ULP_PAD_PTB15__LPI2C3_HREQ                               0x00BC 0x019C 0x5 0x3
+#define IMX7ULP_PAD_PTB15__TPM2_CH0                                  0x00BC 0x0158 0x6 0x3
+#define IMX7ULP_PAD_PTB15__QSPIA_SCLK                                0x00BC 0x0000 0x8 0x0
+#define IMX7ULP_PAD_PTB16__ADC0_CH4A                                 0x00C0 0x0000 0x0 0x0
+#define IMX7ULP_PAD_PTB16__PTB16                                     0x00C0 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTB16__TPM2_CH1                                  0x00C0 0x015C 0x6 0x3
+#define IMX7ULP_PAD_PTB16__QSPIA_DATA3                               0x00C0 0x0000 0x8 0x0
+#define IMX7ULP_PAD_PTB16__LLWU0_P14                                 0x00C0 0x0000 0xd 0x0
+#define IMX7ULP_PAD_PTB17__ADC0_CH4B                                 0x00C4 0x0000 0x0 0x0
+#define IMX7ULP_PAD_PTB17__PTB17                                     0x00C4 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTB17__TPM3_CLKIN                                0x00C4 0x01B0 0x6 0x2
+#define IMX7ULP_PAD_PTB17__QSPIA_DATA2                               0x00C4 0x0000 0x8 0x0
+#define IMX7ULP_PAD_PTB18__ADC0_CH5A                                 0x00C8 0x0000 0x0 0x0
+#define IMX7ULP_PAD_PTB18__PTB18                                     0x00C8 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTB18__TPM3_CH0                                  0x00C8 0x0160 0x6 0x3
+#define IMX7ULP_PAD_PTB18__QSPIA_DATA1                               0x00C8 0x0000 0x8 0x0
+#define IMX7ULP_PAD_PTB19__ADC0_CH5B                                 0x00CC 0x0000 0x0 0x0
+#define IMX7ULP_PAD_PTB19__PTB19                                     0x00CC 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTB19__TPM3_CH1                                  0x00CC 0x0164 0x6 0x3
+#define IMX7ULP_PAD_PTB19__QSPIA_DATA0                               0x00CC 0x0000 0x8 0x0
+#define IMX7ULP_PAD_PTB19__USB0_ID                                   0x00CC 0x0338 0xa 0x0
+#define IMX7ULP_PAD_PTB19__LLWU0_P15                                 0x00CC 0x0000 0xd 0x0
+#define IMX7ULP_PAD_PTC0__PTC0                                       0x0000 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTC0__LPUART4_CTS_B                              0x0000 0x0244 0x4 0x1
+#define IMX7ULP_PAD_PTC0__LPI2C4_SCL                                 0x0000 0x0278 0x5 0x1
+#define IMX7ULP_PAD_PTC0__TPM4_CLKIN                                 0x0000 0x0298 0x6 0x1
+#define IMX7ULP_PAD_PTC0__FB_AD0                                     0x0000 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTC0__TRACE_D15                                  0x0000 0x0000 0xa 0x0
+#define IMX7ULP_PAD_PTC1__PTC1                                       0x0004 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTC1__LPUART4_RTS_B                              0x0004 0x0000 0x4 0x0
+#define IMX7ULP_PAD_PTC1__LPI2C4_SDA                                 0x0004 0x027C 0x5 0x1
+#define IMX7ULP_PAD_PTC1__TPM4_CH0                                   0x0004 0x0280 0x6 0x1
+#define IMX7ULP_PAD_PTC1__FB_AD1                                     0x0004 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTC1__TRACE_D14                                  0x0004 0x0000 0xa 0x0
+#define IMX7ULP_PAD_PTC2__PTC2                                       0x0008 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTC2__LPUART4_TX                                 0x0008 0x024C 0x4 0x1
+#define IMX7ULP_PAD_PTC2__LPI2C4_HREQ                                0x0008 0x0274 0x5 0x1
+#define IMX7ULP_PAD_PTC2__TPM4_CH1                                   0x0008 0x0284 0x6 0x1
+#define IMX7ULP_PAD_PTC2__FB_AD2                                     0x0008 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTC2__TRACE_D13                                  0x0008 0x0000 0xa 0x0
+#define IMX7ULP_PAD_PTC3__PTC3                                       0x000C 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTC3__LPUART4_RX                                 0x000C 0x0248 0x4 0x1
+#define IMX7ULP_PAD_PTC3__TPM4_CH2                                   0x000C 0x0288 0x6 0x1
+#define IMX7ULP_PAD_PTC3__FB_AD3                                     0x000C 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTC3__TRACE_D12                                  0x000C 0x0000 0xa 0x0
+#define IMX7ULP_PAD_PTC4__PTC4                                       0x0010 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTC4__FXIO1_D0                                   0x0010 0x0204 0x2 0x1
+#define IMX7ULP_PAD_PTC4__LPSPI2_PCS1                                0x0010 0x02A0 0x3 0x1
+#define IMX7ULP_PAD_PTC4__LPUART5_CTS_B                              0x0010 0x0250 0x4 0x1
+#define IMX7ULP_PAD_PTC4__LPI2C5_SCL                                 0x0010 0x02BC 0x5 0x1
+#define IMX7ULP_PAD_PTC4__TPM4_CH3                                   0x0010 0x028C 0x6 0x1
+#define IMX7ULP_PAD_PTC4__FB_AD4                                     0x0010 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTC4__TRACE_D11                                  0x0010 0x0000 0xa 0x0
+#define IMX7ULP_PAD_PTC5__PTC5                                       0x0014 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTC5__FXIO1_D1                                   0x0014 0x0208 0x2 0x1
+#define IMX7ULP_PAD_PTC5__LPSPI2_PCS2                                0x0014 0x02A4 0x3 0x1
+#define IMX7ULP_PAD_PTC5__LPUART5_RTS_B                              0x0014 0x0000 0x4 0x0
+#define IMX7ULP_PAD_PTC5__LPI2C5_SDA                                 0x0014 0x02C0 0x5 0x1
+#define IMX7ULP_PAD_PTC5__TPM4_CH4                                   0x0014 0x0290 0x6 0x1
+#define IMX7ULP_PAD_PTC5__FB_AD5                                     0x0014 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTC5__TRACE_D10                                  0x0014 0x0000 0xa 0x0
+#define IMX7ULP_PAD_PTC6__PTC6                                       0x0018 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTC6__FXIO1_D2                                   0x0018 0x020C 0x2 0x1
+#define IMX7ULP_PAD_PTC6__LPSPI2_PCS3                                0x0018 0x02A8 0x3 0x1
+#define IMX7ULP_PAD_PTC6__LPUART5_TX                                 0x0018 0x0258 0x4 0x1
+#define IMX7ULP_PAD_PTC6__LPI2C5_HREQ                                0x0018 0x02B8 0x5 0x1
+#define IMX7ULP_PAD_PTC6__TPM4_CH5                                   0x0018 0x0294 0x6 0x1
+#define IMX7ULP_PAD_PTC6__FB_AD6                                     0x0018 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTC6__TRACE_D9                                   0x0018 0x0000 0xa 0x0
+#define IMX7ULP_PAD_PTC7__PTC7                                       0x001C 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTC7__FXIO1_D3                                   0x001C 0x0210 0x2 0x1
+#define IMX7ULP_PAD_PTC7__LPUART5_RX                                 0x001C 0x0254 0x4 0x1
+#define IMX7ULP_PAD_PTC7__TPM5_CH1                                   0x001C 0x02C8 0x6 0x1
+#define IMX7ULP_PAD_PTC7__FB_AD7                                     0x001C 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTC7__TRACE_D8                                   0x001C 0x0000 0xa 0x0
+#define IMX7ULP_PAD_PTC8__PTC8                                       0x0020 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTC8__FXIO1_D4                                   0x0020 0x0214 0x2 0x1
+#define IMX7ULP_PAD_PTC8__LPSPI2_SIN                                 0x0020 0x02B0 0x3 0x1
+#define IMX7ULP_PAD_PTC8__LPUART6_CTS_B                              0x0020 0x025C 0x4 0x1
+#define IMX7ULP_PAD_PTC8__LPI2C6_SCL                                 0x0020 0x02FC 0x5 0x1
+#define IMX7ULP_PAD_PTC8__TPM5_CLKIN                                 0x0020 0x02CC 0x6 0x1
+#define IMX7ULP_PAD_PTC8__FB_AD8                                     0x0020 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTC8__TRACE_D7                                   0x0020 0x0000 0xa 0x0
+#define IMX7ULP_PAD_PTC9__PTC9                                       0x0024 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTC9__FXIO1_D5                                   0x0024 0x0218 0x2 0x1
+#define IMX7ULP_PAD_PTC9__LPSPI2_SOUT                                0x0024 0x02B4 0x3 0x1
+#define IMX7ULP_PAD_PTC9__LPUART6_RTS_B                              0x0024 0x0000 0x4 0x0
+#define IMX7ULP_PAD_PTC9__LPI2C6_SDA                                 0x0024 0x0300 0x5 0x1
+#define IMX7ULP_PAD_PTC9__TPM5_CH0                                   0x0024 0x02C4 0x6 0x1
+#define IMX7ULP_PAD_PTC9__FB_AD9                                     0x0024 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTC9__TRACE_D6                                   0x0024 0x0000 0xa 0x0
+#define IMX7ULP_PAD_PTC10__PTC10                                     0x0028 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTC10__FXIO1_D6                                  0x0028 0x021C 0x2 0x1
+#define IMX7ULP_PAD_PTC10__LPSPI2_SCK                                0x0028 0x02AC 0x3 0x1
+#define IMX7ULP_PAD_PTC10__LPUART6_TX                                0x0028 0x0264 0x4 0x1
+#define IMX7ULP_PAD_PTC10__LPI2C6_HREQ                               0x0028 0x02F8 0x5 0x1
+#define IMX7ULP_PAD_PTC10__TPM7_CH3                                  0x0028 0x02E8 0x6 0x1
+#define IMX7ULP_PAD_PTC10__FB_AD10                                   0x0028 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTC10__TRACE_D5                                  0x0028 0x0000 0xa 0x0
+#define IMX7ULP_PAD_PTC11__PTC11                                     0x002C 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTC11__FXIO1_D7                                  0x002C 0x0220 0x2 0x1
+#define IMX7ULP_PAD_PTC11__LPSPI2_PCS0                               0x002C 0x029C 0x3 0x1
+#define IMX7ULP_PAD_PTC11__LPUART6_RX                                0x002C 0x0260 0x4 0x1
+#define IMX7ULP_PAD_PTC11__TPM7_CH4                                  0x002C 0x02EC 0x6 0x1
+#define IMX7ULP_PAD_PTC11__FB_AD11                                   0x002C 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTC11__TRACE_D4                                  0x002C 0x0000 0xa 0x0
+#define IMX7ULP_PAD_PTC12__PTC12                                     0x0030 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTC12__FXIO1_D8                                  0x0030 0x0224 0x2 0x1
+#define IMX7ULP_PAD_PTC12__LPSPI3_PCS1                               0x0030 0x0314 0x3 0x1
+#define IMX7ULP_PAD_PTC12__LPUART7_CTS_B                             0x0030 0x0268 0x4 0x1
+#define IMX7ULP_PAD_PTC12__LPI2C7_SCL                                0x0030 0x0308 0x5 0x1
+#define IMX7ULP_PAD_PTC12__TPM7_CH5                                  0x0030 0x02F0 0x6 0x1
+#define IMX7ULP_PAD_PTC12__FB_AD12                                   0x0030 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTC12__TRACE_D3                                  0x0030 0x0000 0xa 0x0
+#define IMX7ULP_PAD_PTC13__PTC13                                     0x0034 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTC13__FXIO1_D9                                  0x0034 0x0228 0x2 0x1
+#define IMX7ULP_PAD_PTC13__LPSPI3_PCS2                               0x0034 0x0318 0x3 0x1
+#define IMX7ULP_PAD_PTC13__LPUART7_RTS_B                             0x0034 0x0000 0x4 0x0
+#define IMX7ULP_PAD_PTC13__LPI2C7_SDA                                0x0034 0x030C 0x5 0x1
+#define IMX7ULP_PAD_PTC13__TPM7_CLKIN                                0x0034 0x02F4 0x6 0x1
+#define IMX7ULP_PAD_PTC13__FB_AD13                                   0x0034 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTC13__TRACE_D2                                  0x0034 0x0000 0xa 0x0
+#define IMX7ULP_PAD_PTC13__USB0_ID                                   0x0034 0x0338 0xb 0x1
+#define IMX7ULP_PAD_PTC14__PTC14                                     0x0038 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTC14__FXIO1_D10                                 0x0038 0x022C 0x2 0x1
+#define IMX7ULP_PAD_PTC14__LPSPI3_PCS3                               0x0038 0x031C 0x3 0x1
+#define IMX7ULP_PAD_PTC14__LPUART7_TX                                0x0038 0x0270 0x4 0x1
+#define IMX7ULP_PAD_PTC14__LPI2C7_HREQ                               0x0038 0x0304 0x5 0x1
+#define IMX7ULP_PAD_PTC14__TPM7_CH0                                  0x0038 0x02DC 0x6 0x1
+#define IMX7ULP_PAD_PTC14__FB_AD14                                   0x0038 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTC14__TRACE_D1                                  0x0038 0x0000 0xa 0x0
+#define IMX7ULP_PAD_PTC15__PTC15                                     0x003C 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTC15__FXIO1_D11                                 0x003C 0x0230 0x2 0x1
+#define IMX7ULP_PAD_PTC15__LPUART7_RX                                0x003C 0x026C 0x4 0x1
+#define IMX7ULP_PAD_PTC15__TPM7_CH1                                  0x003C 0x02E0 0x6 0x1
+#define IMX7ULP_PAD_PTC15__FB_AD15                                   0x003C 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTC15__TRACE_D0                                  0x003C 0x0000 0xa 0x0
+#define IMX7ULP_PAD_PTC16__PTC16                                     0x0040 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTC16__FXIO1_D12                                 0x0040 0x0234 0x2 0x1
+#define IMX7ULP_PAD_PTC16__LPSPI3_SIN                                0x0040 0x0324 0x3 0x1
+#define IMX7ULP_PAD_PTC16__TPM7_CH2                                  0x0040 0x02E4 0x6 0x1
+#define IMX7ULP_PAD_PTC16__FB_ALE_FB_CS1_B_FB_TS_B                   0x0040 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTC16__TRACE_CLKOUT                              0x0040 0x0000 0xa 0x0
+#define IMX7ULP_PAD_PTC16__USB1_OC2                                  0x0040 0x0334 0xb 0x1
+#define IMX7ULP_PAD_PTC17__PTC17                                     0x0044 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTC17__FXIO1_D13                                 0x0044 0x0238 0x2 0x1
+#define IMX7ULP_PAD_PTC17__LPSPI3_SOUT                               0x0044 0x0328 0x3 0x1
+#define IMX7ULP_PAD_PTC17__TPM6_CLKIN                                0x0044 0x02D8 0x6 0x1
+#define IMX7ULP_PAD_PTC17__FB_CS0_B                                  0x0044 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTC18__PTC18                                     0x0048 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTC18__FXIO1_D14                                 0x0048 0x023C 0x2 0x1
+#define IMX7ULP_PAD_PTC18__LPSPI3_SCK                                0x0048 0x0320 0x3 0x1
+#define IMX7ULP_PAD_PTC18__TPM6_CH0                                  0x0048 0x02D0 0x6 0x1
+#define IMX7ULP_PAD_PTC18__FB_OE_B                                   0x0048 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTC18__USB0_ID                                   0x0048 0x0338 0xb 0x2
+#define IMX7ULP_PAD_PTC18__VIU_DE                                    0x0048 0x033C 0xc 0x1
+#define IMX7ULP_PAD_PTC19__PTC19                                     0x004C 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTC19__FXIO1_D15                                 0x004C 0x0240 0x2 0x1
+#define IMX7ULP_PAD_PTC19__LPSPI3_PCS0                               0x004C 0x0310 0x3 0x1
+#define IMX7ULP_PAD_PTC19__TPM6_CH1                                  0x004C 0x02D4 0x6 0x1
+#define IMX7ULP_PAD_PTC19__FB_A16                                    0x004C 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTC19__USB0_ID                                   0x004C 0x0338 0xa 0x3
+#define IMX7ULP_PAD_PTC19__USB1_PWR2                                 0x004C 0x0000 0xb 0x0
+#define IMX7ULP_PAD_PTC19__VIU_DE                                    0x004C 0x033C 0xc 0x3
+#define IMX7ULP_PAD_PTD0__PTD0                                       0x0080 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTD0__SDHC0_RESET_B                              0x0080 0x0000 0x8 0x0
+#define IMX7ULP_PAD_PTD1__PTD1                                       0x0084 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTD1__SDHC0_CMD                                  0x0084 0x0000 0x8 0x0
+#define IMX7ULP_PAD_PTD2__PTD2                                       0x0088 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTD2__SDHC0_CLK                                  0x0088 0x0000 0x8 0x0
+#define IMX7ULP_PAD_PTD3__PTD3                                       0x008C 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTD3__SDHC0_D7                                   0x008C 0x0000 0x8 0x0
+#define IMX7ULP_PAD_PTD4__PTD4                                       0x0090 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTD4__SDHC0_D6                                   0x0090 0x0000 0x8 0x0
+#define IMX7ULP_PAD_PTD5__PTD5                                       0x0094 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTD5__SDHC0_D5                                   0x0094 0x0000 0x8 0x0
+#define IMX7ULP_PAD_PTD6__PTD6                                       0x0098 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTD6__SDHC0_D4                                   0x0098 0x0000 0x8 0x0
+#define IMX7ULP_PAD_PTD7__PTD7                                       0x009C 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTD7__SDHC0_D3                                   0x009C 0x0000 0x8 0x0
+#define IMX7ULP_PAD_PTD8__PTD8                                       0x00A0 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTD8__TPM4_CLKIN                                 0x00A0 0x0298 0x6 0x2
+#define IMX7ULP_PAD_PTD8__SDHC0_D2                                   0x00A0 0x0000 0x8 0x0
+#define IMX7ULP_PAD_PTD9__PTD9                                       0x00A4 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTD9__TPM4_CH0                                   0x00A4 0x0280 0x6 0x2
+#define IMX7ULP_PAD_PTD9__SDHC0_D1                                   0x00A4 0x0000 0x8 0x0
+#define IMX7ULP_PAD_PTD10__PTD10                                     0x00A8 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTD10__TPM4_CH1                                  0x00A8 0x0284 0x6 0x2
+#define IMX7ULP_PAD_PTD10__SDHC0_D0                                  0x00A8 0x0000 0x8 0x0
+#define IMX7ULP_PAD_PTD11__PTD11                                     0x00AC 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTD11__TPM4_CH2                                  0x00AC 0x0288 0x6 0x2
+#define IMX7ULP_PAD_PTD11__SDHC0_DQS                                 0x00AC 0x0000 0x8 0x0
+#define IMX7ULP_PAD_PTE0__PTE0                                       0x0100 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTE0__FXIO1_D31                                  0x0100 0x0000 0x2 0x0
+#define IMX7ULP_PAD_PTE0__LPSPI2_PCS1                                0x0100 0x02A0 0x3 0x2
+#define IMX7ULP_PAD_PTE0__LPUART4_CTS_B                              0x0100 0x0244 0x4 0x2
+#define IMX7ULP_PAD_PTE0__LPI2C4_SCL                                 0x0100 0x0278 0x5 0x2
+#define IMX7ULP_PAD_PTE0__SDHC1_D1                                   0x0100 0x0000 0x8 0x0
+#define IMX7ULP_PAD_PTE0__FB_A25                                     0x0100 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTE1__PTE1                                       0x0104 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTE1__FXIO1_D30                                  0x0104 0x0000 0x2 0x0
+#define IMX7ULP_PAD_PTE1__LPSPI2_PCS2                                0x0104 0x02A4 0x3 0x2
+#define IMX7ULP_PAD_PTE1__LPUART4_RTS_B                              0x0104 0x0000 0x4 0x0
+#define IMX7ULP_PAD_PTE1__LPI2C4_SDA                                 0x0104 0x027C 0x5 0x2
+#define IMX7ULP_PAD_PTE1__SDHC1_D0                                   0x0104 0x0000 0x8 0x0
+#define IMX7ULP_PAD_PTE1__FB_A26                                     0x0104 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTE2__PTE2                                       0x0108 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTE2__FXIO1_D29                                  0x0108 0x0000 0x2 0x0
+#define IMX7ULP_PAD_PTE2__LPSPI2_PCS3                                0x0108 0x02A8 0x3 0x2
+#define IMX7ULP_PAD_PTE2__LPUART4_TX                                 0x0108 0x024C 0x4 0x2
+#define IMX7ULP_PAD_PTE2__LPI2C4_HREQ                                0x0108 0x0274 0x5 0x2
+#define IMX7ULP_PAD_PTE2__SDHC1_CLK                                  0x0108 0x0000 0x8 0x0
+#define IMX7ULP_PAD_PTE3__PTE3                                       0x010C 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTE3__FXIO1_D28                                  0x010C 0x0000 0x2 0x0
+#define IMX7ULP_PAD_PTE3__LPUART4_RX                                 0x010C 0x0248 0x4 0x2
+#define IMX7ULP_PAD_PTE3__TPM5_CH1                                   0x010C 0x02C8 0x6 0x2
+#define IMX7ULP_PAD_PTE3__SDHC1_CMD                                  0x010C 0x0000 0x8 0x0
+#define IMX7ULP_PAD_PTE4__PTE4                                       0x0110 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTE4__FXIO1_D27                                  0x0110 0x0000 0x2 0x0
+#define IMX7ULP_PAD_PTE4__LPSPI2_SIN                                 0x0110 0x02B0 0x3 0x2
+#define IMX7ULP_PAD_PTE4__LPUART5_CTS_B                              0x0110 0x0250 0x4 0x2
+#define IMX7ULP_PAD_PTE4__LPI2C5_SCL                                 0x0110 0x02BC 0x5 0x2
+#define IMX7ULP_PAD_PTE4__TPM5_CLKIN                                 0x0110 0x02CC 0x6 0x2
+#define IMX7ULP_PAD_PTE4__SDHC1_D3                                   0x0110 0x0000 0x8 0x0
+#define IMX7ULP_PAD_PTE5__PTE5                                       0x0114 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTE5__FXIO1_D26                                  0x0114 0x0000 0x2 0x0
+#define IMX7ULP_PAD_PTE5__LPSPI2_SOUT                                0x0114 0x02B4 0x3 0x2
+#define IMX7ULP_PAD_PTE5__LPUART5_RTS_B                              0x0114 0x0000 0x4 0x0
+#define IMX7ULP_PAD_PTE5__LPI2C5_SDA                                 0x0114 0x02C0 0x5 0x2
+#define IMX7ULP_PAD_PTE5__TPM5_CH0                                   0x0114 0x02C4 0x6 0x2
+#define IMX7ULP_PAD_PTE5__SDHC1_D2                                   0x0114 0x0000 0x8 0x0
+#define IMX7ULP_PAD_PTE5__VIU_DE                                     0x0114 0x033C 0xc 0x2
+#define IMX7ULP_PAD_PTE6__PTE6                                       0x0118 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTE6__FXIO1_D25                                  0x0118 0x0000 0x2 0x0
+#define IMX7ULP_PAD_PTE6__LPSPI2_SCK                                 0x0118 0x02AC 0x3 0x2
+#define IMX7ULP_PAD_PTE6__LPUART5_TX                                 0x0118 0x0258 0x4 0x2
+#define IMX7ULP_PAD_PTE6__LPI2C5_HREQ                                0x0118 0x02B8 0x5 0x2
+#define IMX7ULP_PAD_PTE6__TPM7_CH3                                   0x0118 0x02E8 0x6 0x2
+#define IMX7ULP_PAD_PTE6__SDHC1_D4                                   0x0118 0x0000 0x8 0x0
+#define IMX7ULP_PAD_PTE6__FB_A17                                     0x0118 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTE6__USB0_OC                                    0x0118 0x0330 0xb 0x1
+#define IMX7ULP_PAD_PTE7__PTE7                                       0x011C 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTE7__FXIO1_D24                                  0x011C 0x0000 0x2 0x0
+#define IMX7ULP_PAD_PTE7__LPSPI2_PCS0                                0x011C 0x029C 0x3 0x2
+#define IMX7ULP_PAD_PTE7__LPUART5_RX                                 0x011C 0x0254 0x4 0x2
+#define IMX7ULP_PAD_PTE7__TPM7_CH4                                   0x011C 0x02EC 0x6 0x2
+#define IMX7ULP_PAD_PTE7__SDHC1_D5                                   0x011C 0x0000 0x8 0x0
+#define IMX7ULP_PAD_PTE7__FB_A18                                     0x011C 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTE7__TRACE_D7                                   0x011C 0x0000 0xa 0x0
+#define IMX7ULP_PAD_PTE7__USB0_PWR                                   0x011C 0x0000 0xb 0x0
+#define IMX7ULP_PAD_PTE7__VIU_FID                                    0x011C 0x0000 0xc 0x0
+#define IMX7ULP_PAD_PTE8__PTE8                                       0x0120 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTE8__TRACE_D6                                   0x0120 0x0000 0xa 0x0
+#define IMX7ULP_PAD_PTE8__VIU_D16                                    0x0120 0x0000 0xc 0x0
+#define IMX7ULP_PAD_PTE8__FXIO1_D23                                  0x0120 0x0000 0x2 0x0
+#define IMX7ULP_PAD_PTE8__LPSPI3_PCS1                                0x0120 0x0314 0x3 0x2
+#define IMX7ULP_PAD_PTE8__LPUART6_CTS_B                              0x0120 0x025C 0x4 0x2
+#define IMX7ULP_PAD_PTE8__LPI2C6_SCL                                 0x0120 0x02FC 0x5 0x2
+#define IMX7ULP_PAD_PTE8__TPM7_CH5                                   0x0120 0x02F0 0x6 0x2
+#define IMX7ULP_PAD_PTE8__SDHC1_WP                                   0x0120 0x0200 0x7 0x1
+#define IMX7ULP_PAD_PTE8__SDHC1_D6                                   0x0120 0x0000 0x8 0x0
+#define IMX7ULP_PAD_PTE8__FB_CS3_B_FB_BE7_0_BLS31_24_B               0x0120 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTE9__PTE9                                       0x0124 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTE9__TRACE_D5                                   0x0124 0x0000 0xa 0x0
+#define IMX7ULP_PAD_PTE9__VIU_D17                                    0x0124 0x0000 0xc 0x0
+#define IMX7ULP_PAD_PTE9__FXIO1_D22                                  0x0124 0x0000 0x2 0x0
+#define IMX7ULP_PAD_PTE9__LPSPI3_PCS2                                0x0124 0x0318 0x3 0x2
+#define IMX7ULP_PAD_PTE9__LPUART6_RTS_B                              0x0124 0x0000 0x4 0x0
+#define IMX7ULP_PAD_PTE9__LPI2C6_SDA                                 0x0124 0x0300 0x5 0x2
+#define IMX7ULP_PAD_PTE9__TPM7_CLKIN                                 0x0124 0x02F4 0x6 0x2
+#define IMX7ULP_PAD_PTE9__SDHC1_CD                                   0x0124 0x032C 0x7 0x1
+#define IMX7ULP_PAD_PTE9__SDHC1_D7                                   0x0124 0x0000 0x8 0x0
+#define IMX7ULP_PAD_PTE9__FB_TBST_B_FB_CS2_B_FB_BE15_8_BLS23_16_B    0x0124 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTE10__PTE10                                     0x0128 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTE10__TRACE_D4                                  0x0128 0x0000 0xa 0x0
+#define IMX7ULP_PAD_PTE10__VIU_D18                                   0x0128 0x0000 0xc 0x0
+#define IMX7ULP_PAD_PTE10__FXIO1_D21                                 0x0128 0x0000 0x2 0x0
+#define IMX7ULP_PAD_PTE10__LPSPI3_PCS3                               0x0128 0x031C 0x3 0x2
+#define IMX7ULP_PAD_PTE10__LPUART6_TX                                0x0128 0x0264 0x4 0x2
+#define IMX7ULP_PAD_PTE10__LPI2C6_HREQ                               0x0128 0x02F8 0x5 0x2
+#define IMX7ULP_PAD_PTE10__TPM7_CH0                                  0x0128 0x02DC 0x6 0x2
+#define IMX7ULP_PAD_PTE10__SDHC1_VS                                  0x0128 0x0000 0x7 0x0
+#define IMX7ULP_PAD_PTE10__SDHC1_DQS                                 0x0128 0x0000 0x8 0x0
+#define IMX7ULP_PAD_PTE10__FB_A19                                    0x0128 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTE11__PTE11                                     0x012C 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTE11__TRACE_D3                                  0x012C 0x0000 0xa 0x0
+#define IMX7ULP_PAD_PTE11__VIU_D19                                   0x012C 0x0000 0xc 0x0
+#define IMX7ULP_PAD_PTE11__FXIO1_D20                                 0x012C 0x0000 0x2 0x0
+#define IMX7ULP_PAD_PTE11__LPUART6_RX                                0x012C 0x0260 0x4 0x2
+#define IMX7ULP_PAD_PTE11__TPM7_CH1                                  0x012C 0x02E0 0x6 0x2
+#define IMX7ULP_PAD_PTE11__SDHC1_RESET_B                             0x012C 0x0000 0x8 0x0
+#define IMX7ULP_PAD_PTE11__FB_A20                                    0x012C 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTE12__PTE12                                     0x0130 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTE12__FXIO1_D19                                 0x0130 0x0000 0x2 0x0
+#define IMX7ULP_PAD_PTE12__LPSPI3_SIN                                0x0130 0x0324 0x3 0x2
+#define IMX7ULP_PAD_PTE12__LPUART7_CTS_B                             0x0130 0x0268 0x4 0x2
+#define IMX7ULP_PAD_PTE12__LPI2C7_SCL                                0x0130 0x0308 0x5 0x2
+#define IMX7ULP_PAD_PTE12__TPM7_CH2                                  0x0130 0x02E4 0x6 0x2
+#define IMX7ULP_PAD_PTE12__SDHC1_WP                                  0x0130 0x0200 0x8 0x2
+#define IMX7ULP_PAD_PTE12__FB_A21                                    0x0130 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTE12__TRACE_D2                                  0x0130 0x0000 0xa 0x0
+#define IMX7ULP_PAD_PTE12__USB1_OC2                                  0x0130 0x0334 0xb 0x2
+#define IMX7ULP_PAD_PTE12__VIU_D20                                   0x0130 0x0000 0xc 0x0
+#define IMX7ULP_PAD_PTE13__PTE13                                     0x0134 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTE13__FXIO1_D18                                 0x0134 0x0000 0x2 0x0
+#define IMX7ULP_PAD_PTE13__LPSPI3_SOUT                               0x0134 0x0328 0x3 0x2
+#define IMX7ULP_PAD_PTE13__LPUART7_RTS_B                             0x0134 0x0000 0x4 0x0
+#define IMX7ULP_PAD_PTE13__LPI2C7_SDA                                0x0134 0x030C 0x5 0x2
+#define IMX7ULP_PAD_PTE13__TPM6_CLKIN                                0x0134 0x02D8 0x6 0x2
+#define IMX7ULP_PAD_PTE13__SDHC1_CD                                  0x0134 0x032C 0x8 0x2
+#define IMX7ULP_PAD_PTE13__FB_A22                                    0x0134 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTE13__TRACE_D1                                  0x0134 0x0000 0xa 0x0
+#define IMX7ULP_PAD_PTE13__USB1_PWR2                                 0x0134 0x0000 0xb 0x0
+#define IMX7ULP_PAD_PTE13__VIU_D21                                   0x0134 0x0000 0xc 0x0
+#define IMX7ULP_PAD_PTE14__PTE14                                     0x0138 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTE14__FXIO1_D17                                 0x0138 0x0000 0x2 0x0
+#define IMX7ULP_PAD_PTE14__LPSPI3_SCK                                0x0138 0x0320 0x3 0x2
+#define IMX7ULP_PAD_PTE14__LPUART7_TX                                0x0138 0x0270 0x4 0x2
+#define IMX7ULP_PAD_PTE14__LPI2C7_HREQ                               0x0138 0x0304 0x5 0x2
+#define IMX7ULP_PAD_PTE14__TPM6_CH0                                  0x0138 0x02D0 0x6 0x2
+#define IMX7ULP_PAD_PTE14__SDHC1_VS                                  0x0138 0x0000 0x8 0x0
+#define IMX7ULP_PAD_PTE14__FB_A23                                    0x0138 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTE14__TRACE_D0                                  0x0138 0x0000 0xa 0x0
+#define IMX7ULP_PAD_PTE14__USB0_OC                                   0x0138 0x0330 0xb 0x2
+#define IMX7ULP_PAD_PTE14__VIU_D22                                   0x0138 0x0000 0xc 0x0
+#define IMX7ULP_PAD_PTE15__PTE15                                     0x013C 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTE15__FXIO1_D16                                 0x013C 0x0000 0x2 0x0
+#define IMX7ULP_PAD_PTE15__LPSPI3_PCS0                               0x013C 0x0310 0x3 0x2
+#define IMX7ULP_PAD_PTE15__LPUART7_RX                                0x013C 0x026C 0x4 0x2
+#define IMX7ULP_PAD_PTE15__TPM6_CH1                                  0x013C 0x02D4 0x6 0x2
+#define IMX7ULP_PAD_PTE15__FB_A24                                    0x013C 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTE15__TRACE_CLKOUT                              0x013C 0x0000 0xa 0x0
+#define IMX7ULP_PAD_PTE15__USB0_PWR                                  0x013C 0x0000 0xb 0x0
+#define IMX7ULP_PAD_PTE15__VIU_D23                                   0x013C 0x0000 0xc 0x0
+#define IMX7ULP_PAD_PTF0__PTF0                                       0x0180 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTF0__LPUART4_CTS_B                              0x0180 0x0244 0x4 0x3
+#define IMX7ULP_PAD_PTF0__LPI2C4_SCL                                 0x0180 0x0278 0x5 0x3
+#define IMX7ULP_PAD_PTF0__TPM4_CLKIN                                 0x0180 0x0298 0x6 0x3
+#define IMX7ULP_PAD_PTF0__FB_RW_B                                    0x0180 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTF0__VIU_DE                                     0x0180 0x033C 0xc 0x0
+#define IMX7ULP_PAD_PTF1__PTF1                                       0x0184 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTF1__LPUART4_RTS_B                              0x0184 0x0000 0x4 0x0
+#define IMX7ULP_PAD_PTF1__LPI2C4_SDA                                 0x0184 0x027C 0x5 0x3
+#define IMX7ULP_PAD_PTF1__TPM4_CH0                                   0x0184 0x0280 0x6 0x3
+#define IMX7ULP_PAD_PTF1__CLKOUT                                     0x0184 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTF1__VIU_HSYNC                                  0x0184 0x0000 0xc 0x0
+#define IMX7ULP_PAD_PTF2__PTF2                                       0x0188 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTF2__LPUART4_TX                                 0x0188 0x024C 0x4 0x3
+#define IMX7ULP_PAD_PTF2__LPI2C4_HREQ                                0x0188 0x0274 0x5 0x3
+#define IMX7ULP_PAD_PTF2__TPM4_CH1                                   0x0188 0x0284 0x6 0x3
+#define IMX7ULP_PAD_PTF2__FB_TSIZ1_FB_CS5_B_FB_BE23_16_BLS15_8_B     0x0188 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTF2__VIU_VSYNC                                  0x0188 0x0000 0xc 0x0
+#define IMX7ULP_PAD_PTF3__PTF3                                       0x018C 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTF3__LPUART4_RX                                 0x018C 0x0248 0x4 0x3
+#define IMX7ULP_PAD_PTF3__TPM4_CH2                                   0x018C 0x0288 0x6 0x3
+#define IMX7ULP_PAD_PTF3__FB_AD16                                    0x018C 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTF3__VIU_PCLK                                   0x018C 0x0000 0xc 0x0
+#define IMX7ULP_PAD_PTF4__PTF4                                       0x0190 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTF4__FXIO1_D0                                   0x0190 0x0204 0x2 0x2
+#define IMX7ULP_PAD_PTF4__LPSPI2_PCS1                                0x0190 0x02A0 0x3 0x3
+#define IMX7ULP_PAD_PTF4__LPUART5_CTS_B                              0x0190 0x0250 0x4 0x3
+#define IMX7ULP_PAD_PTF4__LPI2C5_SCL                                 0x0190 0x02BC 0x5 0x3
+#define IMX7ULP_PAD_PTF4__TPM4_CH3                                   0x0190 0x028C 0x6 0x2
+#define IMX7ULP_PAD_PTF4__FB_AD17                                    0x0190 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTF4__VIU_D0                                     0x0190 0x0000 0xc 0x0
+#define IMX7ULP_PAD_PTF5__PTF5                                       0x0194 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTF5__FXIO1_D1                                   0x0194 0x0208 0x2 0x2
+#define IMX7ULP_PAD_PTF5__LPSPI2_PCS2                                0x0194 0x02A4 0x3 0x3
+#define IMX7ULP_PAD_PTF5__LPUART5_RTS_B                              0x0194 0x0000 0x4 0x0
+#define IMX7ULP_PAD_PTF5__LPI2C5_SDA                                 0x0194 0x02C0 0x5 0x3
+#define IMX7ULP_PAD_PTF5__TPM4_CH4                                   0x0194 0x0290 0x6 0x2
+#define IMX7ULP_PAD_PTF5__FB_AD18                                    0x0194 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTF5__VIU_D1                                     0x0194 0x0000 0xc 0x0
+#define IMX7ULP_PAD_PTF6__PTF6                                       0x0198 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTF6__FXIO1_D2                                   0x0198 0x020C 0x2 0x2
+#define IMX7ULP_PAD_PTF6__LPSPI2_PCS3                                0x0198 0x02A8 0x3 0x3
+#define IMX7ULP_PAD_PTF6__LPUART5_TX                                 0x0198 0x0258 0x4 0x3
+#define IMX7ULP_PAD_PTF6__LPI2C5_HREQ                                0x0198 0x02B8 0x5 0x3
+#define IMX7ULP_PAD_PTF6__TPM4_CH5                                   0x0198 0x0294 0x6 0x2
+#define IMX7ULP_PAD_PTF6__FB_AD19                                    0x0198 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTF6__VIU_D2                                     0x0198 0x0000 0xc 0x0
+#define IMX7ULP_PAD_PTF7__PTF7                                       0x019C 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTF7__FXIO1_D3                                   0x019C 0x0210 0x2 0x2
+#define IMX7ULP_PAD_PTF7__LPUART5_RX                                 0x019C 0x0254 0x4 0x3
+#define IMX7ULP_PAD_PTF7__TPM5_CH1                                   0x019C 0x02C8 0x6 0x3
+#define IMX7ULP_PAD_PTF7__FB_AD20                                    0x019C 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTF7__VIU_D3                                     0x019C 0x0000 0xc 0x0
+#define IMX7ULP_PAD_PTF8__PTF8                                       0x01A0 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTF8__FXIO1_D4                                   0x01A0 0x0214 0x2 0x2
+#define IMX7ULP_PAD_PTF8__LPSPI2_SIN                                 0x01A0 0x02B0 0x3 0x3
+#define IMX7ULP_PAD_PTF8__LPUART6_CTS_B                              0x01A0 0x025C 0x4 0x3
+#define IMX7ULP_PAD_PTF8__LPI2C6_SCL                                 0x01A0 0x02FC 0x5 0x3
+#define IMX7ULP_PAD_PTF8__TPM5_CLKIN                                 0x01A0 0x02CC 0x6 0x3
+#define IMX7ULP_PAD_PTF8__FB_AD21                                    0x01A0 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTF8__USB1_CLK                                   0x01A0 0x0000 0xb 0x0
+#define IMX7ULP_PAD_PTF8__VIU_D4                                     0x01A0 0x0000 0xc 0x0
+#define IMX7ULP_PAD_PTF9__PTF9                                       0x01A4 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTF9__FXIO1_D5                                   0x01A4 0x0218 0x2 0x2
+#define IMX7ULP_PAD_PTF9__LPSPI2_SOUT                                0x01A4 0x02B4 0x3 0x3
+#define IMX7ULP_PAD_PTF9__LPUART6_RTS_B                              0x01A4 0x0000 0x4 0x0
+#define IMX7ULP_PAD_PTF9__LPI2C6_SDA                                 0x01A4 0x0300 0x5 0x3
+#define IMX7ULP_PAD_PTF9__TPM5_CH0                                   0x01A4 0x02C4 0x6 0x3
+#define IMX7ULP_PAD_PTF9__FB_AD22                                    0x01A4 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTF9__USB1_NXT                                   0x01A4 0x0000 0xb 0x0
+#define IMX7ULP_PAD_PTF9__VIU_D5                                     0x01A4 0x0000 0xc 0x0
+#define IMX7ULP_PAD_PTF10__PTF10                                     0x01A8 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTF10__FXIO1_D6                                  0x01A8 0x021C 0x2 0x2
+#define IMX7ULP_PAD_PTF10__LPSPI2_SCK                                0x01A8 0x02AC 0x3 0x3
+#define IMX7ULP_PAD_PTF10__LPUART6_TX                                0x01A8 0x0264 0x4 0x3
+#define IMX7ULP_PAD_PTF10__LPI2C6_HREQ                               0x01A8 0x02F8 0x5 0x3
+#define IMX7ULP_PAD_PTF10__TPM7_CH3                                  0x01A8 0x02E8 0x6 0x3
+#define IMX7ULP_PAD_PTF10__FB_AD23                                   0x01A8 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTF10__USB1_STP                                  0x01A8 0x0000 0xb 0x0
+#define IMX7ULP_PAD_PTF10__VIU_D6                                    0x01A8 0x0000 0xc 0x0
+#define IMX7ULP_PAD_PTF11__PTF11                                     0x01AC 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTF11__FXIO1_D7                                  0x01AC 0x0220 0x2 0x2
+#define IMX7ULP_PAD_PTF11__LPSPI2_PCS0                               0x01AC 0x029C 0x3 0x3
+#define IMX7ULP_PAD_PTF11__LPUART6_RX                                0x01AC 0x0260 0x4 0x3
+#define IMX7ULP_PAD_PTF11__TPM7_CH4                                  0x01AC 0x02EC 0x6 0x3
+#define IMX7ULP_PAD_PTF11__FB_CS4_B_FB_TSIZ0_FB_BE31_24_BLS7_0_B     0x01AC 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTF11__USB1_DIR                                  0x01AC 0x0000 0xb 0x0
+#define IMX7ULP_PAD_PTF11__VIU_D7                                    0x01AC 0x0000 0xc 0x0
+#define IMX7ULP_PAD_PTF12__PTF12                                     0x01B0 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTF12__FXIO1_D8                                  0x01B0 0x0224 0x2 0x2
+#define IMX7ULP_PAD_PTF12__LPSPI3_PCS1                               0x01B0 0x0314 0x3 0x3
+#define IMX7ULP_PAD_PTF12__LPUART7_CTS_B                             0x01B0 0x0268 0x4 0x3
+#define IMX7ULP_PAD_PTF12__LPI2C7_SCL                                0x01B0 0x0308 0x5 0x3
+#define IMX7ULP_PAD_PTF12__TPM7_CH5                                  0x01B0 0x02F0 0x6 0x3
+#define IMX7ULP_PAD_PTF12__FB_AD24                                   0x01B0 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTF12__USB1_DATA0                                0x01B0 0x0000 0xb 0x0
+#define IMX7ULP_PAD_PTF12__VIU_D8                                    0x01B0 0x0000 0xc 0x0
+#define IMX7ULP_PAD_PTF13__PTF13                                     0x01B4 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTF13__FXIO1_D9                                  0x01B4 0x0228 0x2 0x2
+#define IMX7ULP_PAD_PTF13__LPSPI3_PCS2                               0x01B4 0x0318 0x3 0x3
+#define IMX7ULP_PAD_PTF13__LPUART7_RTS_B                             0x01B4 0x0000 0x4 0x0
+#define IMX7ULP_PAD_PTF13__LPI2C7_SDA                                0x01B4 0x030C 0x5 0x3
+#define IMX7ULP_PAD_PTF13__TPM7_CLKIN                                0x01B4 0x02F4 0x6 0x3
+#define IMX7ULP_PAD_PTF13__FB_AD25                                   0x01B4 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTF13__USB1_DATA1                                0x01B4 0x0000 0xb 0x0
+#define IMX7ULP_PAD_PTF13__VIU_D9                                    0x01B4 0x0000 0xc 0x0
+#define IMX7ULP_PAD_PTF14__PTF14                                     0x01B8 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTF14__FXIO1_D10                                 0x01B8 0x022C 0x2 0x2
+#define IMX7ULP_PAD_PTF14__LPSPI3_PCS3                               0x01B8 0x031C 0x3 0x3
+#define IMX7ULP_PAD_PTF14__LPUART7_TX                                0x01B8 0x0270 0x4 0x3
+#define IMX7ULP_PAD_PTF14__LPI2C7_HREQ                               0x01B8 0x0304 0x5 0x3
+#define IMX7ULP_PAD_PTF14__TPM7_CH0                                  0x01B8 0x02DC 0x6 0x3
+#define IMX7ULP_PAD_PTF14__FB_AD26                                   0x01B8 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTF14__USB1_DATA2                                0x01B8 0x0000 0xb 0x0
+#define IMX7ULP_PAD_PTF14__VIU_D10                                   0x01B8 0x0000 0xc 0x0
+#define IMX7ULP_PAD_PTF15__PTF15                                     0x01BC 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTF15__FXIO1_D11                                 0x01BC 0x0230 0x2 0x2
+#define IMX7ULP_PAD_PTF15__LPUART7_RX                                0x01BC 0x026C 0x4 0x3
+#define IMX7ULP_PAD_PTF15__TPM7_CH1                                  0x01BC 0x02E0 0x6 0x3
+#define IMX7ULP_PAD_PTF15__FB_AD27                                   0x01BC 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTF15__USB1_DATA3                                0x01BC 0x0000 0xb 0x0
+#define IMX7ULP_PAD_PTF15__VIU_D11                                   0x01BC 0x0000 0xc 0x0
+#define IMX7ULP_PAD_PTF16__PTF16                                     0x01C0 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTF16__USB1_DATA4                                0x01C0 0x0000 0xb 0x0
+#define IMX7ULP_PAD_PTF16__VIU_D12                                   0x01C0 0x0000 0xc 0x0
+#define IMX7ULP_PAD_PTF16__FXIO1_D12                                 0x01C0 0x0234 0x2 0x2
+#define IMX7ULP_PAD_PTF16__LPSPI3_SIN                                0x01C0 0x0324 0x3 0x3
+#define IMX7ULP_PAD_PTF16__TPM7_CH2                                  0x01C0 0x02E4 0x6 0x3
+#define IMX7ULP_PAD_PTF16__FB_AD28                                   0x01C0 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTF17__PTF17                                     0x01C4 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTF17__USB1_DATA5                                0x01C4 0x0000 0xb 0x0
+#define IMX7ULP_PAD_PTF17__VIU_D13                                   0x01C4 0x0000 0xc 0x0
+#define IMX7ULP_PAD_PTF17__FXIO1_D13                                 0x01C4 0x0238 0x2 0x2
+#define IMX7ULP_PAD_PTF17__LPSPI3_SOUT                               0x01C4 0x0328 0x3 0x3
+#define IMX7ULP_PAD_PTF17__TPM6_CLKIN                                0x01C4 0x02D8 0x6 0x3
+#define IMX7ULP_PAD_PTF17__FB_AD29                                   0x01C4 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTF18__PTF18                                     0x01C8 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTF18__USB1_DATA6                                0x01C8 0x0000 0xb 0x0
+#define IMX7ULP_PAD_PTF18__VIU_D14                                   0x01C8 0x0000 0xc 0x0
+#define IMX7ULP_PAD_PTF18__FXIO1_D14                                 0x01C8 0x023C 0x2 0x2
+#define IMX7ULP_PAD_PTF18__LPSPI3_SCK                                0x01C8 0x0320 0x3 0x3
+#define IMX7ULP_PAD_PTF18__TPM6_CH0                                  0x01C8 0x02D0 0x6 0x3
+#define IMX7ULP_PAD_PTF18__FB_AD30                                   0x01C8 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTF19__PTF19                                     0x01CC 0x0000 0x1 0x0
+#define IMX7ULP_PAD_PTF19__USB1_DATA7                                0x01CC 0x0000 0xb 0x0
+#define IMX7ULP_PAD_PTF19__VIU_D15                                   0x01CC 0x0000 0xc 0x0
+#define IMX7ULP_PAD_PTF19__FXIO1_D15                                 0x01CC 0x0240 0x2 0x2
+#define IMX7ULP_PAD_PTF19__LPSPI3_PCS0                               0x01CC 0x0310 0x3 0x3
+#define IMX7ULP_PAD_PTF19__TPM6_CH1                                  0x01CC 0x02D4 0x6 0x3
+#define IMX7ULP_PAD_PTF19__FB_AD31                                   0x01CC 0x0000 0x9 0x0
+
+#endif /* __DTS_IMX7ULP_PINFUNC_H */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/mt2701-pinfunc.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/mt2701-pinfunc.h
new file mode 100644
index 0000000000000000000000000000000000000000..e24ebc8d928e7c5bd0d4ac592e335556b312db3f
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/mt2701-pinfunc.h
@@ -0,0 +1,735 @@
+/*
+ * Copyright (c) 2015 MediaTek Inc.
+ * Author: Biao Huang <biao.huang@mediatek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __DTS_MT2701_PINFUNC_H
+#define __DTS_MT2701_PINFUNC_H
+
+#include <dt-bindings/pinctrl/mt65xx.h>
+
+#define MT2701_PIN_0_PWRAP_SPI0_MI__FUNC_GPIO0 (MTK_PIN_NO(0) | 0)
+#define MT2701_PIN_0_PWRAP_SPI0_MI__FUNC_PWRAP_SPIDO (MTK_PIN_NO(0) | 1)
+#define MT2701_PIN_0_PWRAP_SPI0_MI__FUNC_PWRAP_SPIDI (MTK_PIN_NO(0) | 2)
+
+#define MT2701_PIN_1_PWRAP_SPI0_MO__FUNC_GPIO1 (MTK_PIN_NO(1) | 0)
+#define MT2701_PIN_1_PWRAP_SPI0_MO__FUNC_PWRAP_SPIDI (MTK_PIN_NO(1) | 1)
+#define MT2701_PIN_1_PWRAP_SPI0_MO__FUNC_PWRAP_SPIDO (MTK_PIN_NO(1) | 2)
+
+#define MT2701_PIN_2_PWRAP_INT__FUNC_GPIO2 (MTK_PIN_NO(2) | 0)
+#define MT2701_PIN_2_PWRAP_INT__FUNC_PWRAP_INT (MTK_PIN_NO(2) | 1)
+
+#define MT2701_PIN_3_PWRAP_SPI0_CK__FUNC_GPIO3 (MTK_PIN_NO(3) | 0)
+#define MT2701_PIN_3_PWRAP_SPI0_CK__FUNC_PWRAP_SPICK_I (MTK_PIN_NO(3) | 1)
+
+#define MT2701_PIN_4_PWRAP_SPI0_CSN__FUNC_GPIO4 (MTK_PIN_NO(4) | 0)
+#define MT2701_PIN_4_PWRAP_SPI0_CSN__FUNC_PWRAP_SPICS_B_I (MTK_PIN_NO(4) | 1)
+
+#define MT2701_PIN_5_PWRAP_SPI0_CK2__FUNC_GPIO5 (MTK_PIN_NO(5) | 0)
+#define MT2701_PIN_5_PWRAP_SPI0_CK2__FUNC_PWRAP_SPICK2_I (MTK_PIN_NO(5) | 1)
+#define MT2701_PIN_5_PWRAP_SPI0_CK2__FUNC_ANT_SEL1 (MTK_PIN_NO(5) | 5)
+
+#define MT2701_PIN_6_PWRAP_SPI0_CSN2__FUNC_GPIO6 (MTK_PIN_NO(6) | 0)
+#define MT2701_PIN_6_PWRAP_SPI0_CSN2__FUNC_PWRAP_SPICS2_B_I (MTK_PIN_NO(6) | 1)
+#define MT2701_PIN_6_PWRAP_SPI0_CSN2__FUNC_ANT_SEL0 (MTK_PIN_NO(6) | 5)
+#define MT2701_PIN_6_PWRAP_SPI0_CSN2__FUNC_DBG_MON_A_0 (MTK_PIN_NO(6) | 7)
+
+#define MT2701_PIN_7_SPI1_CSN__FUNC_GPIO7 (MTK_PIN_NO(7) | 0)
+#define MT2701_PIN_7_SPI1_CSN__FUNC_SPI1_CS (MTK_PIN_NO(7) | 1)
+#define MT2701_PIN_7_SPI1_CSN__FUNC_KCOL0 (MTK_PIN_NO(7) | 4)
+#define MT2701_PIN_7_SPI1_CSN__FUNC_DBG_MON_B_12 (MTK_PIN_NO(7) | 7)
+
+#define MT2701_PIN_8_SPI1_MI__FUNC_GPIO8 (MTK_PIN_NO(8) | 0)
+#define MT2701_PIN_8_SPI1_MI__FUNC_SPI1_MI (MTK_PIN_NO(8) | 1)
+#define MT2701_PIN_8_SPI1_MI__FUNC_SPI1_MO (MTK_PIN_NO(8) | 2)
+#define MT2701_PIN_8_SPI1_MI__FUNC_KCOL1 (MTK_PIN_NO(8) | 4)
+#define MT2701_PIN_8_SPI1_MI__FUNC_DBG_MON_B_13 (MTK_PIN_NO(8) | 7)
+
+#define MT2701_PIN_9_SPI1_MO__FUNC_GPIO9 (MTK_PIN_NO(9) | 0)
+#define MT2701_PIN_9_SPI1_MO__FUNC_SPI1_MO (MTK_PIN_NO(9) | 1)
+#define MT2701_PIN_9_SPI1_MO__FUNC_SPI1_MI (MTK_PIN_NO(9) | 2)
+#define MT2701_PIN_9_SPI1_MO__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(9) | 3)
+#define MT2701_PIN_9_SPI1_MO__FUNC_KCOL2 (MTK_PIN_NO(9) | 4)
+#define MT2701_PIN_9_SPI1_MO__FUNC_DBG_MON_B_14 (MTK_PIN_NO(9) | 7)
+
+#define MT2701_PIN_10_RTC32K_CK__FUNC_GPIO10 (MTK_PIN_NO(10) | 0)
+#define MT2701_PIN_10_RTC32K_CK__FUNC_RTC32K_CK (MTK_PIN_NO(10) | 1)
+
+#define MT2701_PIN_11_WATCHDOG__FUNC_GPIO11 (MTK_PIN_NO(11) | 0)
+#define MT2701_PIN_11_WATCHDOG__FUNC_WATCHDOG (MTK_PIN_NO(11) | 1)
+
+#define MT2701_PIN_12_SRCLKENA__FUNC_GPIO12 (MTK_PIN_NO(12) | 0)
+#define MT2701_PIN_12_SRCLKENA__FUNC_SRCLKENA (MTK_PIN_NO(12) | 1)
+
+#define MT2701_PIN_13_SRCLKENAI__FUNC_GPIO13 (MTK_PIN_NO(13) | 0)
+#define MT2701_PIN_13_SRCLKENAI__FUNC_SRCLKENAI (MTK_PIN_NO(13) | 1)
+
+#define MT2701_PIN_14_URXD2__FUNC_GPIO14 (MTK_PIN_NO(14) | 0)
+#define MT2701_PIN_14_URXD2__FUNC_URXD2 (MTK_PIN_NO(14) | 1)
+#define MT2701_PIN_14_URXD2__FUNC_UTXD2 (MTK_PIN_NO(14) | 2)
+#define MT2701_PIN_14_URXD2__FUNC_SRCCLKENAI2 (MTK_PIN_NO(14) | 5)
+#define MT2701_PIN_14_URXD2__FUNC_DBG_MON_B_30 (MTK_PIN_NO(14) | 7)
+
+#define MT2701_PIN_15_UTXD2__FUNC_GPIO15 (MTK_PIN_NO(15) | 0)
+#define MT2701_PIN_15_UTXD2__FUNC_UTXD2 (MTK_PIN_NO(15) | 1)
+#define MT2701_PIN_15_UTXD2__FUNC_URXD2 (MTK_PIN_NO(15) | 2)
+#define MT2701_PIN_15_UTXD2__FUNC_DBG_MON_B_31 (MTK_PIN_NO(15) | 7)
+
+#define MT2701_PIN_18_PCM_CLK__FUNC_GPIO18 (MTK_PIN_NO(18) | 0)
+#define MT2701_PIN_18_PCM_CLK__FUNC_PCM_CLK0 (MTK_PIN_NO(18) | 1)
+#define MT2701_PIN_18_PCM_CLK__FUNC_MRG_CLK (MTK_PIN_NO(18) | 2)
+#define MT2701_PIN_18_PCM_CLK__FUNC_MM_TEST_CK (MTK_PIN_NO(18) | 4)
+#define MT2701_PIN_18_PCM_CLK__FUNC_CONN_DSP_JCK (MTK_PIN_NO(18) | 5)
+#define MT2701_PIN_18_PCM_CLK__FUNC_WCN_PCM_CLKO (MTK_PIN_NO(18) | 6)
+#define MT2701_PIN_18_PCM_CLK__FUNC_DBG_MON_A_3 (MTK_PIN_NO(18) | 7)
+
+#define MT2701_PIN_19_PCM_SYNC__FUNC_GPIO19 (MTK_PIN_NO(19) | 0)
+#define MT2701_PIN_19_PCM_SYNC__FUNC_PCM_SYNC (MTK_PIN_NO(19) | 1)
+#define MT2701_PIN_19_PCM_SYNC__FUNC_MRG_SYNC (MTK_PIN_NO(19) | 2)
+#define MT2701_PIN_19_PCM_SYNC__FUNC_CONN_DSP_JINTP (MTK_PIN_NO(19) | 5)
+#define MT2701_PIN_19_PCM_SYNC__FUNC_WCN_PCM_SYNC (MTK_PIN_NO(19) | 6)
+#define MT2701_PIN_19_PCM_SYNC__FUNC_DBG_MON_A_5 (MTK_PIN_NO(19) | 7)
+
+#define MT2701_PIN_20_PCM_RX__FUNC_GPIO20 (MTK_PIN_NO(20) | 0)
+#define MT2701_PIN_20_PCM_RX__FUNC_PCM_RX (MTK_PIN_NO(20) | 1)
+#define MT2701_PIN_20_PCM_RX__FUNC_MRG_RX (MTK_PIN_NO(20) | 2)
+#define MT2701_PIN_20_PCM_RX__FUNC_MRG_TX (MTK_PIN_NO(20) | 3)
+#define MT2701_PIN_20_PCM_RX__FUNC_PCM_TX (MTK_PIN_NO(20) | 4)
+#define MT2701_PIN_20_PCM_RX__FUNC_CONN_DSP_JDI (MTK_PIN_NO(20) | 5)
+#define MT2701_PIN_20_PCM_RX__FUNC_WCN_PCM_RX (MTK_PIN_NO(20) | 6)
+#define MT2701_PIN_20_PCM_RX__FUNC_DBG_MON_A_4 (MTK_PIN_NO(20) | 7)
+
+#define MT2701_PIN_21_PCM_TX__FUNC_GPIO21 (MTK_PIN_NO(21) | 0)
+#define MT2701_PIN_21_PCM_TX__FUNC_PCM_TX (MTK_PIN_NO(21) | 1)
+#define MT2701_PIN_21_PCM_TX__FUNC_MRG_TX (MTK_PIN_NO(21) | 2)
+#define MT2701_PIN_21_PCM_TX__FUNC_MRG_RX (MTK_PIN_NO(21) | 3)
+#define MT2701_PIN_21_PCM_TX__FUNC_PCM_RX (MTK_PIN_NO(21) | 4)
+#define MT2701_PIN_21_PCM_TX__FUNC_CONN_DSP_JMS (MTK_PIN_NO(21) | 5)
+#define MT2701_PIN_21_PCM_TX__FUNC_WCN_PCM_TX (MTK_PIN_NO(21) | 6)
+#define MT2701_PIN_21_PCM_TX__FUNC_DBG_MON_A_2 (MTK_PIN_NO(21) | 7)
+
+#define MT2701_PIN_22_EINT0__FUNC_GPIO22 (MTK_PIN_NO(22) | 0)
+#define MT2701_PIN_22_EINT0__FUNC_UCTS0 (MTK_PIN_NO(22) | 1)
+#define MT2701_PIN_22_EINT0__FUNC_KCOL3 (MTK_PIN_NO(22) | 3)
+#define MT2701_PIN_22_EINT0__FUNC_CONN_DSP_JDO (MTK_PIN_NO(22) | 4)
+#define MT2701_PIN_22_EINT0__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(22) | 5)
+#define MT2701_PIN_22_EINT0__FUNC_DBG_MON_A_30 (MTK_PIN_NO(22) | 7)
+#define MT2701_PIN_22_EINT0__FUNC_PCIE0_PERST_N (MTK_PIN_NO(22) | 10)
+
+#define MT2701_PIN_23_EINT1__FUNC_GPIO23 (MTK_PIN_NO(23) | 0)
+#define MT2701_PIN_23_EINT1__FUNC_URTS0 (MTK_PIN_NO(23) | 1)
+#define MT2701_PIN_23_EINT1__FUNC_KCOL2 (MTK_PIN_NO(23) | 3)
+#define MT2701_PIN_23_EINT1__FUNC_CONN_MCU_TDO (MTK_PIN_NO(23) | 4)
+#define MT2701_PIN_23_EINT1__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(23) | 5)
+#define MT2701_PIN_23_EINT1__FUNC_DBG_MON_A_29 (MTK_PIN_NO(23) | 7)
+#define MT2701_PIN_23_EINT1__FUNC_PCIE1_PERST_N (MTK_PIN_NO(23) | 10)
+
+#define MT2701_PIN_24_EINT2__FUNC_GPIO24 (MTK_PIN_NO(24) | 0)
+#define MT2701_PIN_24_EINT2__FUNC_UCTS1 (MTK_PIN_NO(24) | 1)
+#define MT2701_PIN_24_EINT2__FUNC_KCOL1 (MTK_PIN_NO(24) | 3)
+#define MT2701_PIN_24_EINT2__FUNC_CONN_MCU_DBGACK_N (MTK_PIN_NO(24) | 4)
+#define MT2701_PIN_24_EINT2__FUNC_DBG_MON_A_28 (MTK_PIN_NO(24) | 7)
+#define MT2701_PIN_24_EINT2__FUNC_PCIE2_PERST_N (MTK_PIN_NO(24) | 10)
+
+#define MT2701_PIN_25_EINT3__FUNC_GPIO25 (MTK_PIN_NO(25) | 0)
+#define MT2701_PIN_25_EINT3__FUNC_URTS1 (MTK_PIN_NO(25) | 1)
+#define MT2701_PIN_25_EINT3__FUNC_KCOL0 (MTK_PIN_NO(25) | 3)
+#define MT2701_PIN_25_EINT3__FUNC_CONN_MCU_DBGI_N (MTK_PIN_NO(25) | 4)
+#define MT2701_PIN_25_EINT3__FUNC_DBG_MON_A_27 (MTK_PIN_NO(25) | 7)
+
+#define MT2701_PIN_26_EINT4__FUNC_GPIO26 (MTK_PIN_NO(26) | 0)
+#define MT2701_PIN_26_EINT4__FUNC_UCTS3 (MTK_PIN_NO(26) | 1)
+#define MT2701_PIN_26_EINT4__FUNC_DRV_VBUS_P1 (MTK_PIN_NO(26) | 2)
+#define MT2701_PIN_26_EINT4__FUNC_KROW3 (MTK_PIN_NO(26) | 3)
+#define MT2701_PIN_26_EINT4__FUNC_CONN_MCU_TCK0 (MTK_PIN_NO(26) | 4)
+#define MT2701_PIN_26_EINT4__FUNC_CONN_MCU_AICE_JCKC (MTK_PIN_NO(26) | 5)
+#define MT2701_PIN_26_EINT4__FUNC_PCIE2_WAKE_N (MTK_PIN_NO(26) | 6)
+#define MT2701_PIN_26_EINT4__FUNC_DBG_MON_A_26 (MTK_PIN_NO(26) | 7)
+
+#define MT2701_PIN_27_EINT5__FUNC_GPIO27 (MTK_PIN_NO(27) | 0)
+#define MT2701_PIN_27_EINT5__FUNC_URTS3 (MTK_PIN_NO(27) | 1)
+#define MT2701_PIN_27_EINT5__FUNC_IDDIG_P1 (MTK_PIN_NO(27) | 2)
+#define MT2701_PIN_27_EINT5__FUNC_KROW2 (MTK_PIN_NO(27) | 3)
+#define MT2701_PIN_27_EINT5__FUNC_CONN_MCU_TDI (MTK_PIN_NO(27) | 4)
+#define MT2701_PIN_27_EINT5__FUNC_PCIE1_WAKE_N (MTK_PIN_NO(27) | 6)
+#define MT2701_PIN_27_EINT5__FUNC_DBG_MON_A_25 (MTK_PIN_NO(27) | 7)
+
+#define MT2701_PIN_28_EINT6__FUNC_GPIO28 (MTK_PIN_NO(28) | 0)
+#define MT2701_PIN_28_EINT6__FUNC_DRV_VBUS (MTK_PIN_NO(28) | 1)
+#define MT2701_PIN_28_EINT6__FUNC_KROW1 (MTK_PIN_NO(28) | 3)
+#define MT2701_PIN_28_EINT6__FUNC_CONN_MCU_TRST_B (MTK_PIN_NO(28) | 4)
+#define MT2701_PIN_28_EINT6__FUNC_PCIE0_WAKE_N (MTK_PIN_NO(28) | 6)
+#define MT2701_PIN_28_EINT6__FUNC_DBG_MON_A_24 (MTK_PIN_NO(28) | 7)
+
+#define MT2701_PIN_29_EINT7__FUNC_GPIO29 (MTK_PIN_NO(29) | 0)
+#define MT2701_PIN_29_EINT7__FUNC_IDDIG (MTK_PIN_NO(29) | 1)
+#define MT2701_PIN_29_EINT7__FUNC_MSDC1_WP (MTK_PIN_NO(29) | 2)
+#define MT2701_PIN_29_EINT7__FUNC_KROW0 (MTK_PIN_NO(29) | 3)
+#define MT2701_PIN_29_EINT7__FUNC_CONN_MCU_TMS (MTK_PIN_NO(29) | 4)
+#define MT2701_PIN_29_EINT7__FUNC_CONN_MCU_AICE_JMSC (MTK_PIN_NO(29) | 5)
+#define MT2701_PIN_29_EINT7__FUNC_DBG_MON_A_23 (MTK_PIN_NO(29) | 7)
+#define MT2701_PIN_29_EINT7__FUNC_PCIE2_PERST_N (MTK_PIN_NO(29) | 14)
+
+#define MT2701_PIN_33_I2S1_DATA__FUNC_GPIO33 (MTK_PIN_NO(33) | 0)
+#define MT2701_PIN_33_I2S1_DATA__FUNC_I2S1_DATA (MTK_PIN_NO(33) | 1)
+#define MT2701_PIN_33_I2S1_DATA__FUNC_I2S1_DATA_BYPS (MTK_PIN_NO(33) | 2)
+#define MT2701_PIN_33_I2S1_DATA__FUNC_PCM_TX (MTK_PIN_NO(33) | 3)
+#define MT2701_PIN_33_I2S1_DATA__FUNC_IMG_TEST_CK (MTK_PIN_NO(33) | 4)
+#define MT2701_PIN_33_I2S1_DATA__FUNC_G1_RXD0 (MTK_PIN_NO(33) | 5)
+#define MT2701_PIN_33_I2S1_DATA__FUNC_WCN_PCM_TX (MTK_PIN_NO(33) | 6)
+#define MT2701_PIN_33_I2S1_DATA__FUNC_DBG_MON_B_8 (MTK_PIN_NO(33) | 7)
+
+#define MT2701_PIN_34_I2S1_DATA_IN__FUNC_GPIO34 (MTK_PIN_NO(34) | 0)
+#define MT2701_PIN_34_I2S1_DATA_IN__FUNC_I2S1_DATA_IN (MTK_PIN_NO(34) | 1)
+#define MT2701_PIN_34_I2S1_DATA_IN__FUNC_PCM_RX (MTK_PIN_NO(34) | 3)
+#define MT2701_PIN_34_I2S1_DATA_IN__FUNC_VDEC_TEST_CK (MTK_PIN_NO(34) | 4)
+#define MT2701_PIN_34_I2S1_DATA_IN__FUNC_G1_RXD1 (MTK_PIN_NO(34) | 5)
+#define MT2701_PIN_34_I2S1_DATA_IN__FUNC_WCN_PCM_RX (MTK_PIN_NO(34) | 6)
+#define MT2701_PIN_34_I2S1_DATA_IN__FUNC_DBG_MON_B_7 (MTK_PIN_NO(34) | 7)
+
+#define MT2701_PIN_35_I2S1_BCK__FUNC_GPIO35 (MTK_PIN_NO(35) | 0)
+#define MT2701_PIN_35_I2S1_BCK__FUNC_I2S1_BCK (MTK_PIN_NO(35) | 1)
+#define MT2701_PIN_35_I2S1_BCK__FUNC_PCM_CLK0 (MTK_PIN_NO(35) | 3)
+#define MT2701_PIN_35_I2S1_BCK__FUNC_G1_RXD2 (MTK_PIN_NO(35) | 5)
+#define MT2701_PIN_35_I2S1_BCK__FUNC_WCN_PCM_CLKO (MTK_PIN_NO(35) | 6)
+#define MT2701_PIN_35_I2S1_BCK__FUNC_DBG_MON_B_9 (MTK_PIN_NO(35) | 7)
+
+#define MT2701_PIN_36_I2S1_LRCK__FUNC_GPIO36 (MTK_PIN_NO(36) | 0)
+#define MT2701_PIN_36_I2S1_LRCK__FUNC_I2S1_LRCK (MTK_PIN_NO(36) | 1)
+#define MT2701_PIN_36_I2S1_LRCK__FUNC_PCM_SYNC (MTK_PIN_NO(36) | 3)
+#define MT2701_PIN_36_I2S1_LRCK__FUNC_G1_RXD3 (MTK_PIN_NO(36) | 5)
+#define MT2701_PIN_36_I2S1_LRCK__FUNC_WCN_PCM_SYNC (MTK_PIN_NO(36) | 6)
+#define MT2701_PIN_36_I2S1_LRCK__FUNC_DBG_MON_B_10 (MTK_PIN_NO(36) | 7)
+
+#define MT2701_PIN_37_I2S1_MCLK__FUNC_GPIO37 (MTK_PIN_NO(37) | 0)
+#define MT2701_PIN_37_I2S1_MCLK__FUNC_I2S1_MCLK (MTK_PIN_NO(37) | 1)
+#define MT2701_PIN_37_I2S1_MCLK__FUNC_G1_RXDV (MTK_PIN_NO(37) | 5)
+#define MT2701_PIN_37_I2S1_MCLK__FUNC_DBG_MON_B_11 (MTK_PIN_NO(37) | 7)
+
+#define MT2701_PIN_39_JTMS__FUNC_GPIO39 (MTK_PIN_NO(39) | 0)
+#define MT2701_PIN_39_JTMS__FUNC_JTMS (MTK_PIN_NO(39) | 1)
+#define MT2701_PIN_39_JTMS__FUNC_CONN_MCU_TMS (MTK_PIN_NO(39) | 2)
+#define MT2701_PIN_39_JTMS__FUNC_CONN_MCU_AICE_JMSC (MTK_PIN_NO(39) | 3)
+#define MT2701_PIN_39_JTMS__FUNC_DFD_TMS_XI (MTK_PIN_NO(39) | 4)
+
+#define MT2701_PIN_40_JTCK__FUNC_GPIO40 (MTK_PIN_NO(40) | 0)
+#define MT2701_PIN_40_JTCK__FUNC_JTCK (MTK_PIN_NO(40) | 1)
+#define MT2701_PIN_40_JTCK__FUNC_CONN_MCU_TCK1 (MTK_PIN_NO(40) | 2)
+#define MT2701_PIN_40_JTCK__FUNC_CONN_MCU_AICE_JCKC (MTK_PIN_NO(40) | 3)
+#define MT2701_PIN_40_JTCK__FUNC_DFD_TCK_XI (MTK_PIN_NO(40) | 4)
+
+#define MT2701_PIN_41_JTDI__FUNC_GPIO41 (MTK_PIN_NO(41) | 0)
+#define MT2701_PIN_41_JTDI__FUNC_JTDI (MTK_PIN_NO(41) | 1)
+#define MT2701_PIN_41_JTDI__FUNC_CONN_MCU_TDI (MTK_PIN_NO(41) | 2)
+#define MT2701_PIN_41_JTDI__FUNC_DFD_TDI_XI (MTK_PIN_NO(41) | 4)
+
+#define MT2701_PIN_42_JTDO__FUNC_GPIO42 (MTK_PIN_NO(42) | 0)
+#define MT2701_PIN_42_JTDO__FUNC_JTDO (MTK_PIN_NO(42) | 1)
+#define MT2701_PIN_42_JTDO__FUNC_CONN_MCU_TDO (MTK_PIN_NO(42) | 2)
+#define MT2701_PIN_42_JTDO__FUNC_DFD_TDO (MTK_PIN_NO(42) | 4)
+
+#define MT2701_PIN_43_NCLE__FUNC_GPIO43 (MTK_PIN_NO(43) | 0)
+#define MT2701_PIN_43_NCLE__FUNC_NCLE (MTK_PIN_NO(43) | 1)
+#define MT2701_PIN_43_NCLE__FUNC_EXT_XCS2 (MTK_PIN_NO(43) | 2)
+
+#define MT2701_PIN_44_NCEB1__FUNC_GPIO44 (MTK_PIN_NO(44) | 0)
+#define MT2701_PIN_44_NCEB1__FUNC_NCEB1 (MTK_PIN_NO(44) | 1)
+#define MT2701_PIN_44_NCEB1__FUNC_IDDIG (MTK_PIN_NO(44) | 2)
+
+#define MT2701_PIN_45_NCEB0__FUNC_GPIO45 (MTK_PIN_NO(45) | 0)
+#define MT2701_PIN_45_NCEB0__FUNC_NCEB0 (MTK_PIN_NO(45) | 1)
+#define MT2701_PIN_45_NCEB0__FUNC_DRV_VBUS (MTK_PIN_NO(45) | 2)
+
+#define MT2701_PIN_46_IR__FUNC_GPIO46 (MTK_PIN_NO(46) | 0)
+#define MT2701_PIN_46_IR__FUNC_IR (MTK_PIN_NO(46) | 1)
+
+#define MT2701_PIN_47_NREB__FUNC_GPIO47 (MTK_PIN_NO(47) | 0)
+#define MT2701_PIN_47_NREB__FUNC_NREB (MTK_PIN_NO(47) | 1)
+#define MT2701_PIN_47_NREB__FUNC_IDDIG_P1 (MTK_PIN_NO(47) | 2)
+
+#define MT2701_PIN_48_NRNB__FUNC_GPIO48 (MTK_PIN_NO(48) | 0)
+#define MT2701_PIN_48_NRNB__FUNC_NRNB (MTK_PIN_NO(48) | 1)
+#define MT2701_PIN_48_NRNB__FUNC_DRV_VBUS_P1 (MTK_PIN_NO(48) | 2)
+
+#define MT2701_PIN_49_I2S0_DATA__FUNC_GPIO49 (MTK_PIN_NO(49) | 0)
+#define MT2701_PIN_49_I2S0_DATA__FUNC_I2S0_DATA (MTK_PIN_NO(49) | 1)
+#define MT2701_PIN_49_I2S0_DATA__FUNC_I2S0_DATA_BYPS (MTK_PIN_NO(49) | 2)
+#define MT2701_PIN_49_I2S0_DATA__FUNC_PCM_TX (MTK_PIN_NO(49) | 3)
+#define MT2701_PIN_49_I2S0_DATA__FUNC_WCN_I2S_DO (MTK_PIN_NO(49) | 6)
+#define MT2701_PIN_49_I2S0_DATA__FUNC_DBG_MON_B_3 (MTK_PIN_NO(49) | 7)
+
+#define MT2701_PIN_53_SPI0_CSN__FUNC_GPIO53 (MTK_PIN_NO(53) | 0)
+#define MT2701_PIN_53_SPI0_CSN__FUNC_SPI0_CS (MTK_PIN_NO(53) | 1)
+#define MT2701_PIN_53_SPI0_CSN__FUNC_SPDIF (MTK_PIN_NO(53) | 3)
+#define MT2701_PIN_53_SPI0_CSN__FUNC_ADC_CK (MTK_PIN_NO(53) | 4)
+#define MT2701_PIN_53_SPI0_CSN__FUNC_PWM1 (MTK_PIN_NO(53) | 5)
+#define MT2701_PIN_53_SPI0_CSN__FUNC_DBG_MON_A_7 (MTK_PIN_NO(53) | 7)
+
+#define MT2701_PIN_54_SPI0_CK__FUNC_GPIO54 (MTK_PIN_NO(54) | 0)
+#define MT2701_PIN_54_SPI0_CK__FUNC_SPI0_CK (MTK_PIN_NO(54) | 1)
+#define MT2701_PIN_54_SPI0_CK__FUNC_SPDIF_IN1 (MTK_PIN_NO(54) | 3)
+#define MT2701_PIN_54_SPI0_CK__FUNC_ADC_DAT_IN (MTK_PIN_NO(54) | 4)
+#define MT2701_PIN_54_SPI0_CK__FUNC_DBG_MON_A_10 (MTK_PIN_NO(54) | 7)
+
+#define MT2701_PIN_55_SPI0_MI__FUNC_GPIO55 (MTK_PIN_NO(55) | 0)
+#define MT2701_PIN_55_SPI0_MI__FUNC_SPI0_MI (MTK_PIN_NO(55) | 1)
+#define MT2701_PIN_55_SPI0_MI__FUNC_SPI0_MO (MTK_PIN_NO(55) | 2)
+#define MT2701_PIN_55_SPI0_MI__FUNC_MSDC1_WP (MTK_PIN_NO(55) | 3)
+#define MT2701_PIN_55_SPI0_MI__FUNC_ADC_WS (MTK_PIN_NO(55) | 4)
+#define MT2701_PIN_55_SPI0_MI__FUNC_PWM2 (MTK_PIN_NO(55) | 5)
+#define MT2701_PIN_55_SPI0_MI__FUNC_DBG_MON_A_8 (MTK_PIN_NO(55) | 7)
+
+#define MT2701_PIN_56_SPI0_MO__FUNC_GPIO56 (MTK_PIN_NO(56) | 0)
+#define MT2701_PIN_56_SPI0_MO__FUNC_SPI0_MO (MTK_PIN_NO(56) | 1)
+#define MT2701_PIN_56_SPI0_MO__FUNC_SPI0_MI (MTK_PIN_NO(56) | 2)
+#define MT2701_PIN_56_SPI0_MO__FUNC_SPDIF_IN0 (MTK_PIN_NO(56) | 3)
+#define MT2701_PIN_56_SPI0_MO__FUNC_DBG_MON_A_9 (MTK_PIN_NO(56) | 7)
+
+#define MT2701_PIN_57_SDA1__FUNC_GPIO57 (MTK_PIN_NO(57) | 0)
+#define MT2701_PIN_57_SDA1__FUNC_SDA1 (MTK_PIN_NO(57) | 1)
+
+#define MT2701_PIN_58_SCL1__FUNC_GPIO58 (MTK_PIN_NO(58) | 0)
+#define MT2701_PIN_58_SCL1__FUNC_SCL1 (MTK_PIN_NO(58) | 1)
+
+#define MT2701_PIN_72_I2S0_DATA_IN__FUNC_GPIO72 (MTK_PIN_NO(72) | 0)
+#define MT2701_PIN_72_I2S0_DATA_IN__FUNC_I2S0_DATA_IN (MTK_PIN_NO(72) | 1)
+#define MT2701_PIN_72_I2S0_DATA_IN__FUNC_PCM_RX (MTK_PIN_NO(72) | 3)
+#define MT2701_PIN_72_I2S0_DATA_IN__FUNC_PWM0 (MTK_PIN_NO(72) | 4)
+#define MT2701_PIN_72_I2S0_DATA_IN__FUNC_DISP_PWM (MTK_PIN_NO(72) | 5)
+#define MT2701_PIN_72_I2S0_DATA_IN__FUNC_WCN_I2S_DI (MTK_PIN_NO(72) | 6)
+#define MT2701_PIN_72_I2S0_DATA_IN__FUNC_DBG_MON_B_2 (MTK_PIN_NO(72) | 7)
+
+#define MT2701_PIN_73_I2S0_LRCK__FUNC_GPIO73 (MTK_PIN_NO(73) | 0)
+#define MT2701_PIN_73_I2S0_LRCK__FUNC_I2S0_LRCK (MTK_PIN_NO(73) | 1)
+#define MT2701_PIN_73_I2S0_LRCK__FUNC_PCM_SYNC (MTK_PIN_NO(73) | 3)
+#define MT2701_PIN_73_I2S0_LRCK__FUNC_WCN_I2S_LRCK (MTK_PIN_NO(73) | 6)
+#define MT2701_PIN_73_I2S0_LRCK__FUNC_DBG_MON_B_5 (MTK_PIN_NO(73) | 7)
+
+#define MT2701_PIN_74_I2S0_BCK__FUNC_GPIO74 (MTK_PIN_NO(74) | 0)
+#define MT2701_PIN_74_I2S0_BCK__FUNC_I2S0_BCK (MTK_PIN_NO(74) | 1)
+#define MT2701_PIN_74_I2S0_BCK__FUNC_PCM_CLK0 (MTK_PIN_NO(74) | 3)
+#define MT2701_PIN_74_I2S0_BCK__FUNC_WCN_I2S_BCK (MTK_PIN_NO(74) | 6)
+#define MT2701_PIN_74_I2S0_BCK__FUNC_DBG_MON_B_4 (MTK_PIN_NO(74) | 7)
+
+#define MT2701_PIN_75_SDA0__FUNC_GPIO75 (MTK_PIN_NO(75) | 0)
+#define MT2701_PIN_75_SDA0__FUNC_SDA0 (MTK_PIN_NO(75) | 1)
+
+#define MT2701_PIN_76_SCL0__FUNC_GPIO76 (MTK_PIN_NO(76) | 0)
+#define MT2701_PIN_76_SCL0__FUNC_SCL0 (MTK_PIN_NO(76) | 1)
+
+#define MT2701_PIN_77_SDA2__FUNC_GPIO77 (MTK_PIN_NO(77) | 0)
+#define MT2701_PIN_77_SDA2__FUNC_SDA2 (MTK_PIN_NO(77) | 1)
+
+#define MT2701_PIN_78_SCL2__FUNC_GPIO78 (MTK_PIN_NO(78) | 0)
+#define MT2701_PIN_78_SCL2__FUNC_SCL2 (MTK_PIN_NO(78) | 1)
+
+#define MT2701_PIN_79_URXD0__FUNC_GPIO79 (MTK_PIN_NO(79) | 0)
+#define MT2701_PIN_79_URXD0__FUNC_URXD0 (MTK_PIN_NO(79) | 1)
+#define MT2701_PIN_79_URXD0__FUNC_UTXD0 (MTK_PIN_NO(79) | 2)
+#define MT2701_PIN_79_URXD0__FUNC_ (MTK_PIN_NO(79) | 5)
+
+#define MT2701_PIN_80_UTXD0__FUNC_GPIO80 (MTK_PIN_NO(80) | 0)
+#define MT2701_PIN_80_UTXD0__FUNC_UTXD0 (MTK_PIN_NO(80) | 1)
+#define MT2701_PIN_80_UTXD0__FUNC_URXD0 (MTK_PIN_NO(80) | 2)
+
+#define MT2701_PIN_81_URXD1__FUNC_GPIO81 (MTK_PIN_NO(81) | 0)
+#define MT2701_PIN_81_URXD1__FUNC_URXD1 (MTK_PIN_NO(81) | 1)
+#define MT2701_PIN_81_URXD1__FUNC_UTXD1 (MTK_PIN_NO(81) | 2)
+
+#define MT2701_PIN_82_UTXD1__FUNC_GPIO82 (MTK_PIN_NO(82) | 0)
+#define MT2701_PIN_82_UTXD1__FUNC_UTXD1 (MTK_PIN_NO(82) | 1)
+#define MT2701_PIN_82_UTXD1__FUNC_URXD1 (MTK_PIN_NO(82) | 2)
+
+#define MT2701_PIN_83_LCM_RST__FUNC_GPIO83 (MTK_PIN_NO(83) | 0)
+#define MT2701_PIN_83_LCM_RST__FUNC_LCM_RST (MTK_PIN_NO(83) | 1)
+#define MT2701_PIN_83_LCM_RST__FUNC_VDAC_CK_XI (MTK_PIN_NO(83) | 2)
+#define MT2701_PIN_83_LCM_RST__FUNC_DBG_MON_B_1 (MTK_PIN_NO(83) | 7)
+
+#define MT2701_PIN_84_DSI_TE__FUNC_GPIO84 (MTK_PIN_NO(84) | 0)
+#define MT2701_PIN_84_DSI_TE__FUNC_DSI_TE (MTK_PIN_NO(84) | 1)
+#define MT2701_PIN_84_DSI_TE__FUNC_DBG_MON_B_0 (MTK_PIN_NO(84) | 7)
+
+#define MT2701_PIN_91_TDN3__FUNC_GPI91 (MTK_PIN_NO(91) | 0)
+#define MT2701_PIN_91_TDN3__FUNC_TDN3 (MTK_PIN_NO(91) | 1)
+
+#define MT2701_PIN_92_TDP3__FUNC_GPI92 (MTK_PIN_NO(92) | 0)
+#define MT2701_PIN_92_TDP3__FUNC_TDP3 (MTK_PIN_NO(92) | 1)
+
+#define MT2701_PIN_93_TDN2__FUNC_GPI93 (MTK_PIN_NO(93) | 0)
+#define MT2701_PIN_93_TDN2__FUNC_TDN2 (MTK_PIN_NO(93) | 1)
+
+#define MT2701_PIN_94_TDP2__FUNC_GPI94 (MTK_PIN_NO(94) | 0)
+#define MT2701_PIN_94_TDP2__FUNC_TDP2 (MTK_PIN_NO(94) | 1)
+
+#define MT2701_PIN_95_TCN__FUNC_GPI95 (MTK_PIN_NO(95) | 0)
+#define MT2701_PIN_95_TCN__FUNC_TCN (MTK_PIN_NO(95) | 1)
+
+#define MT2701_PIN_96_TCP__FUNC_GPI96 (MTK_PIN_NO(96) | 0)
+#define MT2701_PIN_96_TCP__FUNC_TCP (MTK_PIN_NO(96) | 1)
+
+#define MT2701_PIN_97_TDN1__FUNC_GPI97 (MTK_PIN_NO(97) | 0)
+#define MT2701_PIN_97_TDN1__FUNC_TDN1 (MTK_PIN_NO(97) | 1)
+
+#define MT2701_PIN_98_TDP1__FUNC_GPI98 (MTK_PIN_NO(98) | 0)
+#define MT2701_PIN_98_TDP1__FUNC_TDP1 (MTK_PIN_NO(98) | 1)
+
+#define MT2701_PIN_99_TDN0__FUNC_GPI99 (MTK_PIN_NO(99) | 0)
+#define MT2701_PIN_99_TDN0__FUNC_TDN0 (MTK_PIN_NO(99) | 1)
+
+#define MT2701_PIN_100_TDP0__FUNC_GPI100 (MTK_PIN_NO(100) | 0)
+#define MT2701_PIN_100_TDP0__FUNC_TDP0 (MTK_PIN_NO(100) | 1)
+
+#define MT2701_PIN_101_SPI2_CSN__FUNC_GPIO101 (MTK_PIN_NO(101) | 0)
+#define MT2701_PIN_101_SPI2_CSN__FUNC_SPI2_CS (MTK_PIN_NO(101) | 1)
+#define MT2701_PIN_101_SPI2_CSN__FUNC_SCL3 (MTK_PIN_NO(101) | 3)
+#define MT2701_PIN_101_SPI2_CSN__FUNC_KROW0 (MTK_PIN_NO(101) | 4)
+
+#define MT2701_PIN_102_SPI2_MI__FUNC_GPIO102 (MTK_PIN_NO(102) | 0)
+#define MT2701_PIN_102_SPI2_MI__FUNC_SPI2_MI (MTK_PIN_NO(102) | 1)
+#define MT2701_PIN_102_SPI2_MI__FUNC_SPI2_MO (MTK_PIN_NO(102) | 2)
+#define MT2701_PIN_102_SPI2_MI__FUNC_SDA3 (MTK_PIN_NO(102) | 3)
+#define MT2701_PIN_102_SPI2_MI__FUNC_KROW1 (MTK_PIN_NO(102) | 4)
+
+#define MT2701_PIN_103_SPI2_MO__FUNC_GPIO103 (MTK_PIN_NO(103) | 0)
+#define MT2701_PIN_103_SPI2_MO__FUNC_SPI2_MO (MTK_PIN_NO(103) | 1)
+#define MT2701_PIN_103_SPI2_MO__FUNC_SPI2_MI (MTK_PIN_NO(103) | 2)
+#define MT2701_PIN_103_SPI2_MO__FUNC_SCL3 (MTK_PIN_NO(103) | 3)
+#define MT2701_PIN_103_SPI2_MO__FUNC_KROW2 (MTK_PIN_NO(103) | 4)
+
+#define MT2701_PIN_104_SPI2_CLK__FUNC_GPIO104 (MTK_PIN_NO(104) | 0)
+#define MT2701_PIN_104_SPI2_CLK__FUNC_SPI2_CK (MTK_PIN_NO(104) | 1)
+#define MT2701_PIN_104_SPI2_CLK__FUNC_SDA3 (MTK_PIN_NO(104) | 3)
+#define MT2701_PIN_104_SPI2_CLK__FUNC_KROW3 (MTK_PIN_NO(104) | 4)
+
+#define MT2701_PIN_105_MSDC1_CMD__FUNC_GPIO105 (MTK_PIN_NO(105) | 0)
+#define MT2701_PIN_105_MSDC1_CMD__FUNC_MSDC1_CMD (MTK_PIN_NO(105) | 1)
+#define MT2701_PIN_105_MSDC1_CMD__FUNC_ANT_SEL0 (MTK_PIN_NO(105) | 2)
+#define MT2701_PIN_105_MSDC1_CMD__FUNC_SDA1 (MTK_PIN_NO(105) | 3)
+#define MT2701_PIN_105_MSDC1_CMD__FUNC_I2SOUT_BCK (MTK_PIN_NO(105) | 6)
+#define MT2701_PIN_105_MSDC1_CMD__FUNC_DBG_MON_B_27 (MTK_PIN_NO(105) | 7)
+
+#define MT2701_PIN_106_MSDC1_CLK__FUNC_GPIO106 (MTK_PIN_NO(106) | 0)
+#define MT2701_PIN_106_MSDC1_CLK__FUNC_MSDC1_CLK (MTK_PIN_NO(106) | 1)
+#define MT2701_PIN_106_MSDC1_CLK__FUNC_ANT_SEL1 (MTK_PIN_NO(106) | 2)
+#define MT2701_PIN_106_MSDC1_CLK__FUNC_SCL1 (MTK_PIN_NO(106) | 3)
+#define MT2701_PIN_106_MSDC1_CLK__FUNC_I2SOUT_LRCK (MTK_PIN_NO(106) | 6)
+#define MT2701_PIN_106_MSDC1_CLK__FUNC_DBG_MON_B_28 (MTK_PIN_NO(106) | 7)
+
+#define MT2701_PIN_107_MSDC1_DAT0__FUNC_GPIO107 (MTK_PIN_NO(107) | 0)
+#define MT2701_PIN_107_MSDC1_DAT0__FUNC_MSDC1_DAT0 (MTK_PIN_NO(107) | 1)
+#define MT2701_PIN_107_MSDC1_DAT0__FUNC_ANT_SEL2 (MTK_PIN_NO(107) | 2)
+#define MT2701_PIN_107_MSDC1_DAT0__FUNC_UTXD0 (MTK_PIN_NO(107) | 5)
+#define MT2701_PIN_107_MSDC1_DAT0__FUNC_I2SOUT_DATA_OUT (MTK_PIN_NO(107) | 6)
+#define MT2701_PIN_107_MSDC1_DAT0__FUNC_DBG_MON_B_26 (MTK_PIN_NO(107) | 7)
+
+#define MT2701_PIN_108_MSDC1_DAT1__FUNC_GPIO108 (MTK_PIN_NO(108) | 0)
+#define MT2701_PIN_108_MSDC1_DAT1__FUNC_MSDC1_DAT1 (MTK_PIN_NO(108) | 1)
+#define MT2701_PIN_108_MSDC1_DAT1__FUNC_ANT_SEL3 (MTK_PIN_NO(108) | 2)
+#define MT2701_PIN_108_MSDC1_DAT1__FUNC_PWM0 (MTK_PIN_NO(108) | 3)
+#define MT2701_PIN_108_MSDC1_DAT1__FUNC_URXD0 (MTK_PIN_NO(108) | 5)
+#define MT2701_PIN_108_MSDC1_DAT1__FUNC_PWM1 (MTK_PIN_NO(108) | 6)
+#define MT2701_PIN_108_MSDC1_DAT1__FUNC_DBG_MON_B_25 (MTK_PIN_NO(108) | 7)
+
+#define MT2701_PIN_109_MSDC1_DAT2__FUNC_GPIO109 (MTK_PIN_NO(109) | 0)
+#define MT2701_PIN_109_MSDC1_DAT2__FUNC_MSDC1_DAT2 (MTK_PIN_NO(109) | 1)
+#define MT2701_PIN_109_MSDC1_DAT2__FUNC_ANT_SEL4 (MTK_PIN_NO(109) | 2)
+#define MT2701_PIN_109_MSDC1_DAT2__FUNC_SDA2 (MTK_PIN_NO(109) | 3)
+#define MT2701_PIN_109_MSDC1_DAT2__FUNC_UTXD1 (MTK_PIN_NO(109) | 5)
+#define MT2701_PIN_109_MSDC1_DAT2__FUNC_PWM2 (MTK_PIN_NO(109) | 6)
+#define MT2701_PIN_109_MSDC1_DAT2__FUNC_DBG_MON_B_24 (MTK_PIN_NO(109) | 7)
+
+#define MT2701_PIN_110_MSDC1_DAT3__FUNC_GPIO110 (MTK_PIN_NO(110) | 0)
+#define MT2701_PIN_110_MSDC1_DAT3__FUNC_MSDC1_DAT3 (MTK_PIN_NO(110) | 1)
+#define MT2701_PIN_110_MSDC1_DAT3__FUNC_ANT_SEL5 (MTK_PIN_NO(110) | 2)
+#define MT2701_PIN_110_MSDC1_DAT3__FUNC_SCL2 (MTK_PIN_NO(110) | 3)
+#define MT2701_PIN_110_MSDC1_DAT3__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(110) | 4)
+#define MT2701_PIN_110_MSDC1_DAT3__FUNC_URXD1 (MTK_PIN_NO(110) | 5)
+#define MT2701_PIN_110_MSDC1_DAT3__FUNC_PWM3 (MTK_PIN_NO(110) | 6)
+#define MT2701_PIN_110_MSDC1_DAT3__FUNC_DBG_MON_B_23 (MTK_PIN_NO(110) | 7)
+
+#define MT2701_PIN_111_MSDC0_DAT7__FUNC_GPIO111 (MTK_PIN_NO(111) | 0)
+#define MT2701_PIN_111_MSDC0_DAT7__FUNC_MSDC0_DAT7 (MTK_PIN_NO(111) | 1)
+#define MT2701_PIN_111_MSDC0_DAT7__FUNC_NLD7 (MTK_PIN_NO(111) | 4)
+
+#define MT2701_PIN_112_MSDC0_DAT6__FUNC_GPIO112 (MTK_PIN_NO(112) | 0)
+#define MT2701_PIN_112_MSDC0_DAT6__FUNC_MSDC0_DAT6 (MTK_PIN_NO(112) | 1)
+#define MT2701_PIN_112_MSDC0_DAT6__FUNC_NLD6 (MTK_PIN_NO(112) | 4)
+
+#define MT2701_PIN_113_MSDC0_DAT5__FUNC_GPIO113 (MTK_PIN_NO(113) | 0)
+#define MT2701_PIN_113_MSDC0_DAT5__FUNC_MSDC0_DAT5 (MTK_PIN_NO(113) | 1)
+#define MT2701_PIN_113_MSDC0_DAT5__FUNC_NLD5 (MTK_PIN_NO(113) | 4)
+
+#define MT2701_PIN_114_MSDC0_DAT4__FUNC_GPIO114 (MTK_PIN_NO(114) | 0)
+#define MT2701_PIN_114_MSDC0_DAT4__FUNC_MSDC0_DAT4 (MTK_PIN_NO(114) | 1)
+#define MT2701_PIN_114_MSDC0_DAT4__FUNC_NLD4 (MTK_PIN_NO(114) | 4)
+
+#define MT2701_PIN_115_MSDC0_RSTB__FUNC_GPIO115 (MTK_PIN_NO(115) | 0)
+#define MT2701_PIN_115_MSDC0_RSTB__FUNC_MSDC0_RSTB (MTK_PIN_NO(115) | 1)
+#define MT2701_PIN_115_MSDC0_RSTB__FUNC_NLD8 (MTK_PIN_NO(115) | 4)
+
+#define MT2701_PIN_116_MSDC0_CMD__FUNC_GPIO116 (MTK_PIN_NO(116) | 0)
+#define MT2701_PIN_116_MSDC0_CMD__FUNC_MSDC0_CMD (MTK_PIN_NO(116) | 1)
+#define MT2701_PIN_116_MSDC0_CMD__FUNC_NALE (MTK_PIN_NO(116) | 4)
+
+#define MT2701_PIN_117_MSDC0_CLK__FUNC_GPIO117 (MTK_PIN_NO(117) | 0)
+#define MT2701_PIN_117_MSDC0_CLK__FUNC_MSDC0_CLK (MTK_PIN_NO(117) | 1)
+#define MT2701_PIN_117_MSDC0_CLK__FUNC_NWEB (MTK_PIN_NO(117) | 4)
+
+#define MT2701_PIN_118_MSDC0_DAT3__FUNC_GPIO118 (MTK_PIN_NO(118) | 0)
+#define MT2701_PIN_118_MSDC0_DAT3__FUNC_MSDC0_DAT3 (MTK_PIN_NO(118) | 1)
+#define MT2701_PIN_118_MSDC0_DAT3__FUNC_NLD3 (MTK_PIN_NO(118) | 4)
+
+#define MT2701_PIN_119_MSDC0_DAT2__FUNC_GPIO119 (MTK_PIN_NO(119) | 0)
+#define MT2701_PIN_119_MSDC0_DAT2__FUNC_MSDC0_DAT2 (MTK_PIN_NO(119) | 1)
+#define MT2701_PIN_119_MSDC0_DAT2__FUNC_NLD2 (MTK_PIN_NO(119) | 4)
+
+#define MT2701_PIN_120_MSDC0_DAT1__FUNC_GPIO120 (MTK_PIN_NO(120) | 0)
+#define MT2701_PIN_120_MSDC0_DAT1__FUNC_MSDC0_DAT1 (MTK_PIN_NO(120) | 1)
+#define MT2701_PIN_120_MSDC0_DAT1__FUNC_NLD1 (MTK_PIN_NO(120) | 4)
+
+#define MT2701_PIN_121_MSDC0_DAT0__FUNC_GPIO121 (MTK_PIN_NO(121) | 0)
+#define MT2701_PIN_121_MSDC0_DAT0__FUNC_MSDC0_DAT0 (MTK_PIN_NO(121) | 1)
+#define MT2701_PIN_121_MSDC0_DAT0__FUNC_NLD0 (MTK_PIN_NO(121) | 4)
+#define MT2701_PIN_121_MSDC0_DAT0__FUNC_WATCHDOG (MTK_PIN_NO(121) | 5)
+
+#define MT2701_PIN_122_CEC__FUNC_GPIO122 (MTK_PIN_NO(122) | 0)
+#define MT2701_PIN_122_CEC__FUNC_CEC (MTK_PIN_NO(122) | 1)
+#define MT2701_PIN_122_CEC__FUNC_SDA2 (MTK_PIN_NO(122) | 4)
+#define MT2701_PIN_122_CEC__FUNC_URXD0 (MTK_PIN_NO(122) | 5)
+
+#define MT2701_PIN_123_HTPLG__FUNC_GPIO123 (MTK_PIN_NO(123) | 0)
+#define MT2701_PIN_123_HTPLG__FUNC_HTPLG (MTK_PIN_NO(123) | 1)
+#define MT2701_PIN_123_HTPLG__FUNC_SCL2 (MTK_PIN_NO(123) | 4)
+#define MT2701_PIN_123_HTPLG__FUNC_UTXD0 (MTK_PIN_NO(123) | 5)
+
+#define MT2701_PIN_124_HDMISCK__FUNC_GPIO124 (MTK_PIN_NO(124) | 0)
+#define MT2701_PIN_124_HDMISCK__FUNC_HDMISCK (MTK_PIN_NO(124) | 1)
+#define MT2701_PIN_124_HDMISCK__FUNC_SDA1 (MTK_PIN_NO(124) | 4)
+#define MT2701_PIN_124_HDMISCK__FUNC_PWM3 (MTK_PIN_NO(124) | 5)
+
+#define MT2701_PIN_125_HDMISD__FUNC_GPIO125 (MTK_PIN_NO(125) | 0)
+#define MT2701_PIN_125_HDMISD__FUNC_HDMISD (MTK_PIN_NO(125) | 1)
+#define MT2701_PIN_125_HDMISD__FUNC_SCL1 (MTK_PIN_NO(125) | 4)
+#define MT2701_PIN_125_HDMISD__FUNC_PWM4 (MTK_PIN_NO(125) | 5)
+
+#define MT2701_PIN_126_I2S0_MCLK__FUNC_GPIO126 (MTK_PIN_NO(126) | 0)
+#define MT2701_PIN_126_I2S0_MCLK__FUNC_I2S0_MCLK (MTK_PIN_NO(126) | 1)
+#define MT2701_PIN_126_I2S0_MCLK__FUNC_WCN_I2S_MCLK (MTK_PIN_NO(126) | 6)
+#define MT2701_PIN_126_I2S0_MCLK__FUNC_DBG_MON_B_6 (MTK_PIN_NO(126) | 7)
+
+#define MT2701_PIN_199_SPI1_CLK__FUNC_GPIO199 (MTK_PIN_NO(199) | 0)
+#define MT2701_PIN_199_SPI1_CLK__FUNC_SPI1_CK (MTK_PIN_NO(199) | 1)
+#define MT2701_PIN_199_SPI1_CLK__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(199) | 3)
+#define MT2701_PIN_199_SPI1_CLK__FUNC_KCOL3 (MTK_PIN_NO(199) | 4)
+#define MT2701_PIN_199_SPI1_CLK__FUNC_DBG_MON_B_15 (MTK_PIN_NO(199) | 7)
+
+#define MT2701_PIN_200_SPDIF_OUT__FUNC_GPIO200 (MTK_PIN_NO(200) | 0)
+#define MT2701_PIN_200_SPDIF_OUT__FUNC_SPDIF_OUT (MTK_PIN_NO(200) | 1)
+#define MT2701_PIN_200_SPDIF_OUT__FUNC_G1_TXD3 (MTK_PIN_NO(200) | 5)
+#define MT2701_PIN_200_SPDIF_OUT__FUNC_URXD2 (MTK_PIN_NO(200) | 6)
+#define MT2701_PIN_200_SPDIF_OUT__FUNC_DBG_MON_B_16 (MTK_PIN_NO(200) | 7)
+
+#define MT2701_PIN_201_SPDIF_IN0__FUNC_GPIO201 (MTK_PIN_NO(201) | 0)
+#define MT2701_PIN_201_SPDIF_IN0__FUNC_SPDIF_IN0 (MTK_PIN_NO(201) | 1)
+#define MT2701_PIN_201_SPDIF_IN0__FUNC_G1_TXEN (MTK_PIN_NO(201) | 5)
+#define MT2701_PIN_201_SPDIF_IN0__FUNC_UTXD2 (MTK_PIN_NO(201) | 6)
+#define MT2701_PIN_201_SPDIF_IN0__FUNC_DBG_MON_B_17 (MTK_PIN_NO(201) | 7)
+
+#define MT2701_PIN_202_SPDIF_IN1__FUNC_GPIO202 (MTK_PIN_NO(202) | 0)
+#define MT2701_PIN_202_SPDIF_IN1__FUNC_SPDIF_IN1 (MTK_PIN_NO(202) | 1)
+
+#define MT2701_PIN_203_PWM0__FUNC_GPIO203 (MTK_PIN_NO(203) | 0)
+#define MT2701_PIN_203_PWM0__FUNC_PWM0 (MTK_PIN_NO(203) | 1)
+#define MT2701_PIN_203_PWM0__FUNC_DISP_PWM (MTK_PIN_NO(203) | 2)
+#define MT2701_PIN_203_PWM0__FUNC_G1_TXD2 (MTK_PIN_NO(203) | 5)
+#define MT2701_PIN_203_PWM0__FUNC_DBG_MON_B_18 (MTK_PIN_NO(203) | 7)
+#define MT2701_PIN_203_PWM0__FUNC_I2S2_DATA (MTK_PIN_NO(203) | 9)
+
+#define MT2701_PIN_204_PWM1__FUNC_GPIO204 (MTK_PIN_NO(204) | 0)
+#define MT2701_PIN_204_PWM1__FUNC_PWM1 (MTK_PIN_NO(204) | 1)
+#define MT2701_PIN_204_PWM1__FUNC_CLKM3 (MTK_PIN_NO(204) | 2)
+#define MT2701_PIN_204_PWM1__FUNC_G1_TXD1 (MTK_PIN_NO(204) | 5)
+#define MT2701_PIN_204_PWM1__FUNC_DBG_MON_B_19 (MTK_PIN_NO(204) | 7)
+#define MT2701_PIN_204_PWM1__FUNC_I2S3_DATA (MTK_PIN_NO(204) | 9)
+
+#define MT2701_PIN_205_PWM2__FUNC_GPIO205 (MTK_PIN_NO(205) | 0)
+#define MT2701_PIN_205_PWM2__FUNC_PWM2 (MTK_PIN_NO(205) | 1)
+#define MT2701_PIN_205_PWM2__FUNC_CLKM2 (MTK_PIN_NO(205) | 2)
+#define MT2701_PIN_205_PWM2__FUNC_G1_TXD0 (MTK_PIN_NO(205) | 5)
+#define MT2701_PIN_205_PWM2__FUNC_DBG_MON_B_20 (MTK_PIN_NO(205) | 7)
+
+#define MT2701_PIN_206_PWM3__FUNC_GPIO206 (MTK_PIN_NO(206) | 0)
+#define MT2701_PIN_206_PWM3__FUNC_PWM3 (MTK_PIN_NO(206) | 1)
+#define MT2701_PIN_206_PWM3__FUNC_CLKM1 (MTK_PIN_NO(206) | 2)
+#define MT2701_PIN_206_PWM3__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(206) | 3)
+#define MT2701_PIN_206_PWM3__FUNC_G1_TXC (MTK_PIN_NO(206) | 5)
+#define MT2701_PIN_206_PWM3__FUNC_DBG_MON_B_21 (MTK_PIN_NO(206) | 7)
+
+#define MT2701_PIN_207_PWM4__FUNC_GPIO207 (MTK_PIN_NO(207) | 0)
+#define MT2701_PIN_207_PWM4__FUNC_PWM4 (MTK_PIN_NO(207) | 1)
+#define MT2701_PIN_207_PWM4__FUNC_CLKM0 (MTK_PIN_NO(207) | 2)
+#define MT2701_PIN_207_PWM4__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(207) | 3)
+#define MT2701_PIN_207_PWM4__FUNC_G1_RXC (MTK_PIN_NO(207) | 5)
+#define MT2701_PIN_207_PWM4__FUNC_DBG_MON_B_22 (MTK_PIN_NO(207) | 7)
+
+#define MT2701_PIN_208_AUD_EXT_CK1__FUNC_GPIO208 (MTK_PIN_NO(208) | 0)
+#define MT2701_PIN_208_AUD_EXT_CK1__FUNC_AUD_EXT_CK1 (MTK_PIN_NO(208) | 1)
+#define MT2701_PIN_208_AUD_EXT_CK1__FUNC_PWM0 (MTK_PIN_NO(208) | 2)
+#define MT2701_PIN_208_AUD_EXT_CK1__FUNC_ANT_SEL5 (MTK_PIN_NO(208) | 4)
+#define MT2701_PIN_208_AUD_EXT_CK1__FUNC_DISP_PWM (MTK_PIN_NO(208) | 5)
+#define MT2701_PIN_208_AUD_EXT_CK1__FUNC_DBG_MON_A_31 (MTK_PIN_NO(208) | 7)
+#define MT2701_PIN_208_AUD_EXT_CK1__FUNC_PCIE0_PERST_N (MTK_PIN_NO(208) | 11)
+
+#define MT2701_PIN_209_AUD_EXT_CK2__FUNC_GPIO209 (MTK_PIN_NO(209) | 0)
+#define MT2701_PIN_209_AUD_EXT_CK2__FUNC_AUD_EXT_CK2 (MTK_PIN_NO(209) | 1)
+#define MT2701_PIN_209_AUD_EXT_CK2__FUNC_MSDC1_WP (MTK_PIN_NO(209) | 2)
+#define MT2701_PIN_209_AUD_EXT_CK2__FUNC_PWM1 (MTK_PIN_NO(209) | 5)
+#define MT2701_PIN_209_AUD_EXT_CK2__FUNC_DBG_MON_A_32 (MTK_PIN_NO(209) | 7)
+#define MT2701_PIN_209_AUD_EXT_CK2__FUNC_PCIE1_PERST_N (MTK_PIN_NO(209) | 11)
+
+#define MT2701_PIN_236_EXT_SDIO3__FUNC_GPIO236 (MTK_PIN_NO(236) | 0)
+#define MT2701_PIN_236_EXT_SDIO3__FUNC_EXT_SDIO3 (MTK_PIN_NO(236) | 1)
+#define MT2701_PIN_236_EXT_SDIO3__FUNC_IDDIG (MTK_PIN_NO(236) | 2)
+#define MT2701_PIN_236_EXT_SDIO3__FUNC_DBG_MON_A_1 (MTK_PIN_NO(236) | 7)
+
+#define MT2701_PIN_237_EXT_SDIO2__FUNC_GPIO237 (MTK_PIN_NO(237) | 0)
+#define MT2701_PIN_237_EXT_SDIO2__FUNC_EXT_SDIO2 (MTK_PIN_NO(237) | 1)
+#define MT2701_PIN_237_EXT_SDIO2__FUNC_DRV_VBUS (MTK_PIN_NO(237) | 2)
+
+#define MT2701_PIN_238_EXT_SDIO1__FUNC_GPIO238 (MTK_PIN_NO(238) | 0)
+#define MT2701_PIN_238_EXT_SDIO1__FUNC_EXT_SDIO1 (MTK_PIN_NO(238) | 1)
+#define MT2701_PIN_238_EXT_SDIO1__FUNC_IDDIG_P1 (MTK_PIN_NO(238) | 2)
+
+#define MT2701_PIN_239_EXT_SDIO0__FUNC_GPIO239 (MTK_PIN_NO(239) | 0)
+#define MT2701_PIN_239_EXT_SDIO0__FUNC_EXT_SDIO0 (MTK_PIN_NO(239) | 1)
+#define MT2701_PIN_239_EXT_SDIO0__FUNC_DRV_VBUS_P1 (MTK_PIN_NO(239) | 2)
+
+#define MT2701_PIN_240_EXT_XCS__FUNC_GPIO240 (MTK_PIN_NO(240) | 0)
+#define MT2701_PIN_240_EXT_XCS__FUNC_EXT_XCS (MTK_PIN_NO(240) | 1)
+
+#define MT2701_PIN_241_EXT_SCK__FUNC_GPIO241 (MTK_PIN_NO(241) | 0)
+#define MT2701_PIN_241_EXT_SCK__FUNC_EXT_SCK (MTK_PIN_NO(241) | 1)
+
+#define MT2701_PIN_242_URTS2__FUNC_GPIO242 (MTK_PIN_NO(242) | 0)
+#define MT2701_PIN_242_URTS2__FUNC_URTS2 (MTK_PIN_NO(242) | 1)
+#define MT2701_PIN_242_URTS2__FUNC_UTXD3 (MTK_PIN_NO(242) | 2)
+#define MT2701_PIN_242_URTS2__FUNC_URXD3 (MTK_PIN_NO(242) | 3)
+#define MT2701_PIN_242_URTS2__FUNC_SCL1 (MTK_PIN_NO(242) | 4)
+#define MT2701_PIN_242_URTS2__FUNC_DBG_MON_B_32 (MTK_PIN_NO(242) | 7)
+
+#define MT2701_PIN_243_UCTS2__FUNC_GPIO243 (MTK_PIN_NO(243) | 0)
+#define MT2701_PIN_243_UCTS2__FUNC_UCTS2 (MTK_PIN_NO(243) | 1)
+#define MT2701_PIN_243_UCTS2__FUNC_URXD3 (MTK_PIN_NO(243) | 2)
+#define MT2701_PIN_243_UCTS2__FUNC_UTXD3 (MTK_PIN_NO(243) | 3)
+#define MT2701_PIN_243_UCTS2__FUNC_SDA1 (MTK_PIN_NO(243) | 4)
+#define MT2701_PIN_243_UCTS2__FUNC_DBG_MON_A_6 (MTK_PIN_NO(243) | 7)
+
+#define MT2701_PIN_244_HDMI_SDA_RX__FUNC_GPIO244 (MTK_PIN_NO(244) | 0)
+#define MT2701_PIN_244_HDMI_SDA_RX__FUNC_HDMI_SDA_RX (MTK_PIN_NO(244) | 1)
+
+#define MT2701_PIN_245_HDMI_SCL_RX__FUNC_GPIO245 (MTK_PIN_NO(245) | 0)
+#define MT2701_PIN_245_HDMI_SCL_RX__FUNC_HDMI_SCL_RX (MTK_PIN_NO(245) | 1)
+
+#define MT2701_PIN_246_MHL_SENCE__FUNC_GPIO246 (MTK_PIN_NO(246) | 0)
+
+#define MT2701_PIN_247_HDMI_HPD_CBUS_RX__FUNC_GPIO247 (MTK_PIN_NO(247) | 0)
+#define MT2701_PIN_247_HDMI_HPD_CBUS_RX__FUNC_HDMI_HPD_RX (MTK_PIN_NO(247) | 1)
+
+#define MT2701_PIN_248_HDMI_TESTOUTP_RX__FUNC_GPIO248 (MTK_PIN_NO(248) | 0)
+#define MT2701_PIN_248_HDMI_TESTOUTP_RX__FUNC_HDMI_TESTOUTP_RX (MTK_PIN_NO(248) | 1)
+
+#define MT2701_PIN_249_MSDC0E_RSTB__FUNC_MSDC0E_RSTB (MTK_PIN_NO(249) | 9)
+
+#define MT2701_PIN_250_MSDC0E_DAT7__FUNC_MSDC3_DAT7 (MTK_PIN_NO(250) | 9)
+#define MT2701_PIN_250_MSDC0E_DAT7__FUNC_PCIE0_CLKREQ_N (MTK_PIN_NO(250) | 14)
+
+#define MT2701_PIN_251_MSDC0E_DAT6__FUNC_MSDC3_DAT6 (MTK_PIN_NO(251) | 9)
+#define MT2701_PIN_251_MSDC0E_DAT6__FUNC_PCIE0_WAKE_N (MTK_PIN_NO(251) | 14)
+
+#define MT2701_PIN_252_MSDC0E_DAT5__FUNC_MSDC3_DAT5 (MTK_PIN_NO(252) | 9)
+#define MT2701_PIN_252_MSDC0E_DAT5__FUNC_PCIE1_CLKREQ_N (MTK_PIN_NO(252) | 14)
+
+#define MT2701_PIN_253_MSDC0E_DAT4__FUNC_MSDC3_DAT4 (MTK_PIN_NO(253) | 9)
+#define MT2701_PIN_253_MSDC0E_DAT4__FUNC_PCIE1_WAKE_N (MTK_PIN_NO(253) | 14)
+
+#define MT2701_PIN_254_MSDC0E_DAT3__FUNC_MSDC3_DAT3 (MTK_PIN_NO(254) | 9)
+#define MT2701_PIN_254_MSDC0E_DAT3__FUNC_PCIE2_CLKREQ_N (MTK_PIN_NO(254) | 14)
+
+#define MT2701_PIN_255_MSDC0E_DAT2__FUNC_MSDC3_DAT2 (MTK_PIN_NO(255) | 9)
+#define MT2701_PIN_255_MSDC0E_DAT2__FUNC_PCIE2_WAKE_N (MTK_PIN_NO(255) | 14)
+
+#define MT2701_PIN_256_MSDC0E_DAT1__FUNC_MSDC3_DAT1 (MTK_PIN_NO(256) | 9)
+
+#define MT2701_PIN_257_MSDC0E_DAT0__FUNC_MSDC3_DAT0 (MTK_PIN_NO(257) | 9)
+
+#define MT2701_PIN_258_MSDC0E_CMD__FUNC_MSDC3_CMD (MTK_PIN_NO(258) | 9)
+
+#define MT2701_PIN_259_MSDC0E_CLK__FUNC_MSDC3_CLK (MTK_PIN_NO(259) | 9)
+
+#define MT2701_PIN_260_MSDC0E_DSL__FUNC_MSDC3_DSL (MTK_PIN_NO(260) | 9)
+
+#define MT2701_PIN_261_MSDC1_INS__FUNC_GPIO261 (MTK_PIN_NO(261) | 0)
+#define MT2701_PIN_261_MSDC1_INS__FUNC_MSDC1_INS (MTK_PIN_NO(261) | 1)
+#define MT2701_PIN_261_MSDC1_INS__FUNC_DBG_MON_B_29 (MTK_PIN_NO(261) | 7)
+
+#define MT2701_PIN_262_G2_TXEN__FUNC_GPIO262 (MTK_PIN_NO(262) | 0)
+#define MT2701_PIN_262_G2_TXEN__FUNC_G2_TXEN (MTK_PIN_NO(262) | 1)
+
+#define MT2701_PIN_263_G2_TXD3__FUNC_GPIO263 (MTK_PIN_NO(263) | 0)
+#define MT2701_PIN_263_G2_TXD3__FUNC_G2_TXD3 (MTK_PIN_NO(263) | 1)
+#define MT2701_PIN_263_G2_TXD3__FUNC_ANT_SEL5 (MTK_PIN_NO(263) | 6)
+
+#define MT2701_PIN_264_G2_TXD2__FUNC_GPIO264 (MTK_PIN_NO(264) | 0)
+#define MT2701_PIN_264_G2_TXD2__FUNC_G2_TXD2 (MTK_PIN_NO(264) | 1)
+#define MT2701_PIN_264_G2_TXD2__FUNC_ANT_SEL4 (MTK_PIN_NO(264) | 6)
+
+#define MT2701_PIN_265_G2_TXD1__FUNC_GPIO265 (MTK_PIN_NO(265) | 0)
+#define MT2701_PIN_265_G2_TXD1__FUNC_G2_TXD1 (MTK_PIN_NO(265) | 1)
+#define MT2701_PIN_265_G2_TXD1__FUNC_ANT_SEL3 (MTK_PIN_NO(265) | 6)
+
+#define MT2701_PIN_266_G2_TXD0__FUNC_GPIO266 (MTK_PIN_NO(266) | 0)
+#define MT2701_PIN_266_G2_TXD0__FUNC_G2_TXD0 (MTK_PIN_NO(266) | 1)
+#define MT2701_PIN_266_G2_TXD0__FUNC_ANT_SEL2 (MTK_PIN_NO(266) | 6)
+
+#define MT2701_PIN_267_G2_TXC__FUNC_GPIO267 (MTK_PIN_NO(267) | 0)
+#define MT2701_PIN_267_G2_TXC__FUNC_G2_TXC (MTK_PIN_NO(267) | 1)
+
+#define MT2701_PIN_268_G2_RXC__FUNC_GPIO268 (MTK_PIN_NO(268) | 0)
+#define MT2701_PIN_268_G2_RXC__FUNC_G2_RXC (MTK_PIN_NO(268) | 1)
+
+#define MT2701_PIN_269_G2_RXD0__FUNC_GPIO269 (MTK_PIN_NO(269) | 0)
+#define MT2701_PIN_269_G2_RXD0__FUNC_G2_RXD0 (MTK_PIN_NO(269) | 1)
+
+#define MT2701_PIN_270_G2_RXD1__FUNC_GPIO270 (MTK_PIN_NO(270) | 0)
+#define MT2701_PIN_270_G2_RXD1__FUNC_G2_RXD1 (MTK_PIN_NO(270) | 1)
+
+#define MT2701_PIN_271_G2_RXD2__FUNC_GPIO271 (MTK_PIN_NO(271) | 0)
+#define MT2701_PIN_271_G2_RXD2__FUNC_G2_RXD2 (MTK_PIN_NO(271) | 1)
+
+#define MT2701_PIN_272_G2_RXD3__FUNC_GPIO272 (MTK_PIN_NO(272) | 0)
+#define MT2701_PIN_272_G2_RXD3__FUNC_G2_RXD3 (MTK_PIN_NO(272) | 1)
+
+#define MT2701_PIN_274_G2_RXDV__FUNC_GPIO274 (MTK_PIN_NO(274) | 0)
+#define MT2701_PIN_274_G2_RXDV__FUNC_G2_RXDV (MTK_PIN_NO(274) | 1)
+
+#define MT2701_PIN_275_MDC__FUNC_GPIO275 (MTK_PIN_NO(275) | 0)
+#define MT2701_PIN_275_MDC__FUNC_MDC (MTK_PIN_NO(275) | 1)
+#define MT2701_PIN_275_MDC__FUNC_ANT_SEL0 (MTK_PIN_NO(275) | 6)
+
+#define MT2701_PIN_276_MDIO__FUNC_GPIO276 (MTK_PIN_NO(276) | 0)
+#define MT2701_PIN_276_MDIO__FUNC_MDIO (MTK_PIN_NO(276) | 1)
+#define MT2701_PIN_276_MDIO__FUNC_ANT_SEL1 (MTK_PIN_NO(276) | 6)
+
+#define MT2701_PIN_278_JTAG_RESET__FUNC_GPIO278 (MTK_PIN_NO(278) | 0)
+#define MT2701_PIN_278_JTAG_RESET__FUNC_JTAG_RESET (MTK_PIN_NO(278) | 1)
+
+#endif /* __DTS_MT2701_PINFUNC_H */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/mt8135-pinfunc.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/mt8135-pinfunc.h
new file mode 100644
index 0000000000000000000000000000000000000000..5a609875cb18272b98ddcfb4d8beb2caf9aebaee
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/mt8135-pinfunc.h
@@ -0,0 +1,1302 @@
+/*
+ * Copyright (c) 2014 MediaTek Inc.
+ * Author: Hongzhou.Yang <hongzhou.yang@mediatek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __DTS_MT8135_PINFUNC_H
+#define __DTS_MT8135_PINFUNC_H
+
+#include <dt-bindings/pinctrl/mt65xx.h>
+
+#define MT8135_PIN_0_MSDC0_DAT7__FUNC_GPIO0 (MTK_PIN_NO(0) | 0)
+#define MT8135_PIN_0_MSDC0_DAT7__FUNC_MSDC0_DAT7 (MTK_PIN_NO(0) | 1)
+#define MT8135_PIN_0_MSDC0_DAT7__FUNC_EINT49 (MTK_PIN_NO(0) | 2)
+#define MT8135_PIN_0_MSDC0_DAT7__FUNC_I2SOUT_DAT (MTK_PIN_NO(0) | 3)
+#define MT8135_PIN_0_MSDC0_DAT7__FUNC_DAC_DAT_OUT (MTK_PIN_NO(0) | 4)
+#define MT8135_PIN_0_MSDC0_DAT7__FUNC_PCM1_DO (MTK_PIN_NO(0) | 5)
+#define MT8135_PIN_0_MSDC0_DAT7__FUNC_SPI1_MO (MTK_PIN_NO(0) | 6)
+#define MT8135_PIN_0_MSDC0_DAT7__FUNC_NALE (MTK_PIN_NO(0) | 7)
+
+#define MT8135_PIN_1_MSDC0_DAT6__FUNC_GPIO1 (MTK_PIN_NO(1) | 0)
+#define MT8135_PIN_1_MSDC0_DAT6__FUNC_MSDC0_DAT6 (MTK_PIN_NO(1) | 1)
+#define MT8135_PIN_1_MSDC0_DAT6__FUNC_EINT48 (MTK_PIN_NO(1) | 2)
+#define MT8135_PIN_1_MSDC0_DAT6__FUNC_I2SIN_WS (MTK_PIN_NO(1) | 3)
+#define MT8135_PIN_1_MSDC0_DAT6__FUNC_DAC_WS (MTK_PIN_NO(1) | 4)
+#define MT8135_PIN_1_MSDC0_DAT6__FUNC_PCM1_WS (MTK_PIN_NO(1) | 5)
+#define MT8135_PIN_1_MSDC0_DAT6__FUNC_SPI1_CSN (MTK_PIN_NO(1) | 6)
+#define MT8135_PIN_1_MSDC0_DAT6__FUNC_NCLE (MTK_PIN_NO(1) | 7)
+
+#define MT8135_PIN_2_MSDC0_DAT5__FUNC_GPIO2 (MTK_PIN_NO(2) | 0)
+#define MT8135_PIN_2_MSDC0_DAT5__FUNC_MSDC0_DAT5 (MTK_PIN_NO(2) | 1)
+#define MT8135_PIN_2_MSDC0_DAT5__FUNC_EINT47 (MTK_PIN_NO(2) | 2)
+#define MT8135_PIN_2_MSDC0_DAT5__FUNC_I2SIN_CK (MTK_PIN_NO(2) | 3)
+#define MT8135_PIN_2_MSDC0_DAT5__FUNC_DAC_CK (MTK_PIN_NO(2) | 4)
+#define MT8135_PIN_2_MSDC0_DAT5__FUNC_PCM1_CK (MTK_PIN_NO(2) | 5)
+#define MT8135_PIN_2_MSDC0_DAT5__FUNC_SPI1_CLK (MTK_PIN_NO(2) | 6)
+#define MT8135_PIN_2_MSDC0_DAT5__FUNC_NLD4 (MTK_PIN_NO(2) | 7)
+
+#define MT8135_PIN_3_MSDC0_DAT4__FUNC_GPIO3 (MTK_PIN_NO(3) | 0)
+#define MT8135_PIN_3_MSDC0_DAT4__FUNC_MSDC0_DAT4 (MTK_PIN_NO(3) | 1)
+#define MT8135_PIN_3_MSDC0_DAT4__FUNC_EINT46 (MTK_PIN_NO(3) | 2)
+#define MT8135_PIN_3_MSDC0_DAT4__FUNC_A_FUNC_CK (MTK_PIN_NO(3) | 3)
+#define MT8135_PIN_3_MSDC0_DAT4__FUNC_LSCE1B_2X (MTK_PIN_NO(3) | 6)
+#define MT8135_PIN_3_MSDC0_DAT4__FUNC_NLD5 (MTK_PIN_NO(3) | 7)
+
+#define MT8135_PIN_4_MSDC0_CMD__FUNC_GPIO4 (MTK_PIN_NO(4) | 0)
+#define MT8135_PIN_4_MSDC0_CMD__FUNC_MSDC0_CMD (MTK_PIN_NO(4) | 1)
+#define MT8135_PIN_4_MSDC0_CMD__FUNC_EINT41 (MTK_PIN_NO(4) | 2)
+#define MT8135_PIN_4_MSDC0_CMD__FUNC_A_FUNC_DOUT_0 (MTK_PIN_NO(4) | 3)
+#define MT8135_PIN_4_MSDC0_CMD__FUNC_USB_TEST_IO_0 (MTK_PIN_NO(4) | 5)
+#define MT8135_PIN_4_MSDC0_CMD__FUNC_LRSTB_2X (MTK_PIN_NO(4) | 6)
+#define MT8135_PIN_4_MSDC0_CMD__FUNC_NRNB (MTK_PIN_NO(4) | 7)
+
+#define MT8135_PIN_5_MSDC0_CLK__FUNC_GPIO5 (MTK_PIN_NO(5) | 0)
+#define MT8135_PIN_5_MSDC0_CLK__FUNC_MSDC0_CLK (MTK_PIN_NO(5) | 1)
+#define MT8135_PIN_5_MSDC0_CLK__FUNC_EINT40 (MTK_PIN_NO(5) | 2)
+#define MT8135_PIN_5_MSDC0_CLK__FUNC_A_FUNC_DOUT_1 (MTK_PIN_NO(5) | 3)
+#define MT8135_PIN_5_MSDC0_CLK__FUNC_USB_TEST_IO_1 (MTK_PIN_NO(5) | 5)
+#define MT8135_PIN_5_MSDC0_CLK__FUNC_LPTE (MTK_PIN_NO(5) | 6)
+#define MT8135_PIN_5_MSDC0_CLK__FUNC_NREB (MTK_PIN_NO(5) | 7)
+
+#define MT8135_PIN_6_MSDC0_DAT3__FUNC_GPIO6 (MTK_PIN_NO(6) | 0)
+#define MT8135_PIN_6_MSDC0_DAT3__FUNC_MSDC0_DAT3 (MTK_PIN_NO(6) | 1)
+#define MT8135_PIN_6_MSDC0_DAT3__FUNC_EINT45 (MTK_PIN_NO(6) | 2)
+#define MT8135_PIN_6_MSDC0_DAT3__FUNC_A_FUNC_DOUT_2 (MTK_PIN_NO(6) | 3)
+#define MT8135_PIN_6_MSDC0_DAT3__FUNC_USB_TEST_IO_2 (MTK_PIN_NO(6) | 5)
+#define MT8135_PIN_6_MSDC0_DAT3__FUNC_LSCE0B_2X (MTK_PIN_NO(6) | 6)
+#define MT8135_PIN_6_MSDC0_DAT3__FUNC_NLD7 (MTK_PIN_NO(6) | 7)
+
+#define MT8135_PIN_7_MSDC0_DAT2__FUNC_GPIO7 (MTK_PIN_NO(7) | 0)
+#define MT8135_PIN_7_MSDC0_DAT2__FUNC_MSDC0_DAT2 (MTK_PIN_NO(7) | 1)
+#define MT8135_PIN_7_MSDC0_DAT2__FUNC_EINT44 (MTK_PIN_NO(7) | 2)
+#define MT8135_PIN_7_MSDC0_DAT2__FUNC_A_FUNC_DOUT_3 (MTK_PIN_NO(7) | 3)
+#define MT8135_PIN_7_MSDC0_DAT2__FUNC_USB_TEST_IO_3 (MTK_PIN_NO(7) | 5)
+#define MT8135_PIN_7_MSDC0_DAT2__FUNC_LSA0_2X (MTK_PIN_NO(7) | 6)
+#define MT8135_PIN_7_MSDC0_DAT2__FUNC_NLD14 (MTK_PIN_NO(7) | 7)
+
+#define MT8135_PIN_8_MSDC0_DAT1__FUNC_GPIO8 (MTK_PIN_NO(8) | 0)
+#define MT8135_PIN_8_MSDC0_DAT1__FUNC_MSDC0_DAT1 (MTK_PIN_NO(8) | 1)
+#define MT8135_PIN_8_MSDC0_DAT1__FUNC_EINT43 (MTK_PIN_NO(8) | 2)
+#define MT8135_PIN_8_MSDC0_DAT1__FUNC_USB_TEST_IO_4 (MTK_PIN_NO(8) | 5)
+#define MT8135_PIN_8_MSDC0_DAT1__FUNC_LSCK_2X (MTK_PIN_NO(8) | 6)
+#define MT8135_PIN_8_MSDC0_DAT1__FUNC_NLD11 (MTK_PIN_NO(8) | 7)
+
+#define MT8135_PIN_9_MSDC0_DAT0__FUNC_GPIO9 (MTK_PIN_NO(9) | 0)
+#define MT8135_PIN_9_MSDC0_DAT0__FUNC_MSDC0_DAT0 (MTK_PIN_NO(9) | 1)
+#define MT8135_PIN_9_MSDC0_DAT0__FUNC_EINT42 (MTK_PIN_NO(9) | 2)
+#define MT8135_PIN_9_MSDC0_DAT0__FUNC_USB_TEST_IO_5 (MTK_PIN_NO(9) | 5)
+#define MT8135_PIN_9_MSDC0_DAT0__FUNC_LSDA_2X (MTK_PIN_NO(9) | 6)
+
+#define MT8135_PIN_10_NCEB0__FUNC_GPIO10 (MTK_PIN_NO(10) | 0)
+#define MT8135_PIN_10_NCEB0__FUNC_NCEB0 (MTK_PIN_NO(10) | 1)
+#define MT8135_PIN_10_NCEB0__FUNC_EINT139 (MTK_PIN_NO(10) | 2)
+#define MT8135_PIN_10_NCEB0__FUNC_TESTA_OUT4 (MTK_PIN_NO(10) | 7)
+
+#define MT8135_PIN_11_NCEB1__FUNC_GPIO11 (MTK_PIN_NO(11) | 0)
+#define MT8135_PIN_11_NCEB1__FUNC_NCEB1 (MTK_PIN_NO(11) | 1)
+#define MT8135_PIN_11_NCEB1__FUNC_EINT140 (MTK_PIN_NO(11) | 2)
+#define MT8135_PIN_11_NCEB1__FUNC_USB_DRVVBUS (MTK_PIN_NO(11) | 6)
+#define MT8135_PIN_11_NCEB1__FUNC_TESTA_OUT5 (MTK_PIN_NO(11) | 7)
+
+#define MT8135_PIN_12_NRNB__FUNC_GPIO12 (MTK_PIN_NO(12) | 0)
+#define MT8135_PIN_12_NRNB__FUNC_NRNB (MTK_PIN_NO(12) | 1)
+#define MT8135_PIN_12_NRNB__FUNC_EINT141 (MTK_PIN_NO(12) | 2)
+#define MT8135_PIN_12_NRNB__FUNC_A_FUNC_DOUT_4 (MTK_PIN_NO(12) | 3)
+#define MT8135_PIN_12_NRNB__FUNC_TESTA_OUT6 (MTK_PIN_NO(12) | 7)
+
+#define MT8135_PIN_13_NCLE__FUNC_GPIO13 (MTK_PIN_NO(13) | 0)
+#define MT8135_PIN_13_NCLE__FUNC_NCLE (MTK_PIN_NO(13) | 1)
+#define MT8135_PIN_13_NCLE__FUNC_EINT142 (MTK_PIN_NO(13) | 2)
+#define MT8135_PIN_13_NCLE__FUNC_A_FUNC_DOUT_5 (MTK_PIN_NO(13) | 3)
+#define MT8135_PIN_13_NCLE__FUNC_CM2PDN_1X (MTK_PIN_NO(13) | 4)
+#define MT8135_PIN_13_NCLE__FUNC_NALE (MTK_PIN_NO(13) | 6)
+#define MT8135_PIN_13_NCLE__FUNC_TESTA_OUT7 (MTK_PIN_NO(13) | 7)
+
+#define MT8135_PIN_14_NALE__FUNC_GPIO14 (MTK_PIN_NO(14) | 0)
+#define MT8135_PIN_14_NALE__FUNC_NALE (MTK_PIN_NO(14) | 1)
+#define MT8135_PIN_14_NALE__FUNC_EINT143 (MTK_PIN_NO(14) | 2)
+#define MT8135_PIN_14_NALE__FUNC_A_FUNC_DOUT_6 (MTK_PIN_NO(14) | 3)
+#define MT8135_PIN_14_NALE__FUNC_CM2MCLK_1X (MTK_PIN_NO(14) | 4)
+#define MT8135_PIN_14_NALE__FUNC_IRDA_RXD (MTK_PIN_NO(14) | 5)
+#define MT8135_PIN_14_NALE__FUNC_NCLE (MTK_PIN_NO(14) | 6)
+#define MT8135_PIN_14_NALE__FUNC_TESTA_OUT8 (MTK_PIN_NO(14) | 7)
+
+#define MT8135_PIN_15_NREB__FUNC_GPIO15 (MTK_PIN_NO(15) | 0)
+#define MT8135_PIN_15_NREB__FUNC_NREB (MTK_PIN_NO(15) | 1)
+#define MT8135_PIN_15_NREB__FUNC_EINT144 (MTK_PIN_NO(15) | 2)
+#define MT8135_PIN_15_NREB__FUNC_A_FUNC_DOUT_7 (MTK_PIN_NO(15) | 3)
+#define MT8135_PIN_15_NREB__FUNC_CM2RST_1X (MTK_PIN_NO(15) | 4)
+#define MT8135_PIN_15_NREB__FUNC_IRDA_TXD (MTK_PIN_NO(15) | 5)
+#define MT8135_PIN_15_NREB__FUNC_TESTA_OUT9 (MTK_PIN_NO(15) | 7)
+
+#define MT8135_PIN_16_NWEB__FUNC_GPIO16 (MTK_PIN_NO(16) | 0)
+#define MT8135_PIN_16_NWEB__FUNC_NWEB (MTK_PIN_NO(16) | 1)
+#define MT8135_PIN_16_NWEB__FUNC_EINT145 (MTK_PIN_NO(16) | 2)
+#define MT8135_PIN_16_NWEB__FUNC_A_FUNC_DIN_0 (MTK_PIN_NO(16) | 3)
+#define MT8135_PIN_16_NWEB__FUNC_CM2PCLK_1X (MTK_PIN_NO(16) | 4)
+#define MT8135_PIN_16_NWEB__FUNC_IRDA_PDN (MTK_PIN_NO(16) | 5)
+#define MT8135_PIN_16_NWEB__FUNC_TESTA_OUT10 (MTK_PIN_NO(16) | 7)
+
+#define MT8135_PIN_17_NLD0__FUNC_GPIO17 (MTK_PIN_NO(17) | 0)
+#define MT8135_PIN_17_NLD0__FUNC_NLD0 (MTK_PIN_NO(17) | 1)
+#define MT8135_PIN_17_NLD0__FUNC_EINT146 (MTK_PIN_NO(17) | 2)
+#define MT8135_PIN_17_NLD0__FUNC_A_FUNC_DIN_1 (MTK_PIN_NO(17) | 3)
+#define MT8135_PIN_17_NLD0__FUNC_CM2DAT_1X_0 (MTK_PIN_NO(17) | 4)
+#define MT8135_PIN_17_NLD0__FUNC_I2SIN_CK (MTK_PIN_NO(17) | 5)
+#define MT8135_PIN_17_NLD0__FUNC_DAC_CK (MTK_PIN_NO(17) | 6)
+#define MT8135_PIN_17_NLD0__FUNC_TESTA_OUT11 (MTK_PIN_NO(17) | 7)
+
+#define MT8135_PIN_18_NLD1__FUNC_GPIO18 (MTK_PIN_NO(18) | 0)
+#define MT8135_PIN_18_NLD1__FUNC_NLD1 (MTK_PIN_NO(18) | 1)
+#define MT8135_PIN_18_NLD1__FUNC_EINT147 (MTK_PIN_NO(18) | 2)
+#define MT8135_PIN_18_NLD1__FUNC_A_FUNC_DIN_2 (MTK_PIN_NO(18) | 3)
+#define MT8135_PIN_18_NLD1__FUNC_CM2DAT_1X_1 (MTK_PIN_NO(18) | 4)
+#define MT8135_PIN_18_NLD1__FUNC_I2SIN_WS (MTK_PIN_NO(18) | 5)
+#define MT8135_PIN_18_NLD1__FUNC_DAC_WS (MTK_PIN_NO(18) | 6)
+#define MT8135_PIN_18_NLD1__FUNC_TESTA_OUT12 (MTK_PIN_NO(18) | 7)
+
+#define MT8135_PIN_19_NLD2__FUNC_GPIO19 (MTK_PIN_NO(19) | 0)
+#define MT8135_PIN_19_NLD2__FUNC_NLD2 (MTK_PIN_NO(19) | 1)
+#define MT8135_PIN_19_NLD2__FUNC_EINT148 (MTK_PIN_NO(19) | 2)
+#define MT8135_PIN_19_NLD2__FUNC_A_FUNC_DIN_3 (MTK_PIN_NO(19) | 3)
+#define MT8135_PIN_19_NLD2__FUNC_CM2DAT_1X_2 (MTK_PIN_NO(19) | 4)
+#define MT8135_PIN_19_NLD2__FUNC_I2SOUT_DAT (MTK_PIN_NO(19) | 5)
+#define MT8135_PIN_19_NLD2__FUNC_DAC_DAT_OUT (MTK_PIN_NO(19) | 6)
+#define MT8135_PIN_19_NLD2__FUNC_TESTA_OUT13 (MTK_PIN_NO(19) | 7)
+
+#define MT8135_PIN_20_NLD3__FUNC_GPIO20 (MTK_PIN_NO(20) | 0)
+#define MT8135_PIN_20_NLD3__FUNC_NLD3 (MTK_PIN_NO(20) | 1)
+#define MT8135_PIN_20_NLD3__FUNC_EINT149 (MTK_PIN_NO(20) | 2)
+#define MT8135_PIN_20_NLD3__FUNC_A_FUNC_DIN_4 (MTK_PIN_NO(20) | 3)
+#define MT8135_PIN_20_NLD3__FUNC_CM2DAT_1X_3 (MTK_PIN_NO(20) | 4)
+#define MT8135_PIN_20_NLD3__FUNC_TESTA_OUT14 (MTK_PIN_NO(20) | 7)
+
+#define MT8135_PIN_21_NLD4__FUNC_GPIO21 (MTK_PIN_NO(21) | 0)
+#define MT8135_PIN_21_NLD4__FUNC_NLD4 (MTK_PIN_NO(21) | 1)
+#define MT8135_PIN_21_NLD4__FUNC_EINT150 (MTK_PIN_NO(21) | 2)
+#define MT8135_PIN_21_NLD4__FUNC_A_FUNC_DIN_5 (MTK_PIN_NO(21) | 3)
+#define MT8135_PIN_21_NLD4__FUNC_CM2DAT_1X_4 (MTK_PIN_NO(21) | 4)
+#define MT8135_PIN_21_NLD4__FUNC_TESTA_OUT15 (MTK_PIN_NO(21) | 7)
+
+#define MT8135_PIN_22_NLD5__FUNC_GPIO22 (MTK_PIN_NO(22) | 0)
+#define MT8135_PIN_22_NLD5__FUNC_NLD5 (MTK_PIN_NO(22) | 1)
+#define MT8135_PIN_22_NLD5__FUNC_EINT151 (MTK_PIN_NO(22) | 2)
+#define MT8135_PIN_22_NLD5__FUNC_A_FUNC_DIN_6 (MTK_PIN_NO(22) | 3)
+#define MT8135_PIN_22_NLD5__FUNC_CM2DAT_1X_5 (MTK_PIN_NO(22) | 4)
+#define MT8135_PIN_22_NLD5__FUNC_TESTA_OUT16 (MTK_PIN_NO(22) | 7)
+
+#define MT8135_PIN_23_NLD6__FUNC_GPIO23 (MTK_PIN_NO(23) | 0)
+#define MT8135_PIN_23_NLD6__FUNC_NLD6 (MTK_PIN_NO(23) | 1)
+#define MT8135_PIN_23_NLD6__FUNC_EINT152 (MTK_PIN_NO(23) | 2)
+#define MT8135_PIN_23_NLD6__FUNC_A_FUNC_DIN_7 (MTK_PIN_NO(23) | 3)
+#define MT8135_PIN_23_NLD6__FUNC_CM2DAT_1X_6 (MTK_PIN_NO(23) | 4)
+#define MT8135_PIN_23_NLD6__FUNC_TESTA_OUT17 (MTK_PIN_NO(23) | 7)
+
+#define MT8135_PIN_24_NLD7__FUNC_GPIO24 (MTK_PIN_NO(24) | 0)
+#define MT8135_PIN_24_NLD7__FUNC_NLD7 (MTK_PIN_NO(24) | 1)
+#define MT8135_PIN_24_NLD7__FUNC_EINT153 (MTK_PIN_NO(24) | 2)
+#define MT8135_PIN_24_NLD7__FUNC_A_FUNC_DIN_8 (MTK_PIN_NO(24) | 3)
+#define MT8135_PIN_24_NLD7__FUNC_CM2DAT_1X_7 (MTK_PIN_NO(24) | 4)
+#define MT8135_PIN_24_NLD7__FUNC_TESTA_OUT18 (MTK_PIN_NO(24) | 7)
+
+#define MT8135_PIN_25_NLD8__FUNC_GPIO25 (MTK_PIN_NO(25) | 0)
+#define MT8135_PIN_25_NLD8__FUNC_NLD8 (MTK_PIN_NO(25) | 1)
+#define MT8135_PIN_25_NLD8__FUNC_EINT154 (MTK_PIN_NO(25) | 2)
+#define MT8135_PIN_25_NLD8__FUNC_CM2DAT_1X_8 (MTK_PIN_NO(25) | 4)
+
+#define MT8135_PIN_26_NLD9__FUNC_GPIO26 (MTK_PIN_NO(26) | 0)
+#define MT8135_PIN_26_NLD9__FUNC_NLD9 (MTK_PIN_NO(26) | 1)
+#define MT8135_PIN_26_NLD9__FUNC_EINT155 (MTK_PIN_NO(26) | 2)
+#define MT8135_PIN_26_NLD9__FUNC_CM2DAT_1X_9 (MTK_PIN_NO(26) | 4)
+#define MT8135_PIN_26_NLD9__FUNC_PWM1 (MTK_PIN_NO(26) | 5)
+
+#define MT8135_PIN_27_NLD10__FUNC_GPIO27 (MTK_PIN_NO(27) | 0)
+#define MT8135_PIN_27_NLD10__FUNC_NLD10 (MTK_PIN_NO(27) | 1)
+#define MT8135_PIN_27_NLD10__FUNC_EINT156 (MTK_PIN_NO(27) | 2)
+#define MT8135_PIN_27_NLD10__FUNC_CM2VSYNC_1X (MTK_PIN_NO(27) | 4)
+#define MT8135_PIN_27_NLD10__FUNC_PWM2 (MTK_PIN_NO(27) | 5)
+
+#define MT8135_PIN_28_NLD11__FUNC_GPIO28 (MTK_PIN_NO(28) | 0)
+#define MT8135_PIN_28_NLD11__FUNC_NLD11 (MTK_PIN_NO(28) | 1)
+#define MT8135_PIN_28_NLD11__FUNC_EINT157 (MTK_PIN_NO(28) | 2)
+#define MT8135_PIN_28_NLD11__FUNC_CM2HSYNC_1X (MTK_PIN_NO(28) | 4)
+#define MT8135_PIN_28_NLD11__FUNC_PWM3 (MTK_PIN_NO(28) | 5)
+
+#define MT8135_PIN_29_NLD12__FUNC_GPIO29 (MTK_PIN_NO(29) | 0)
+#define MT8135_PIN_29_NLD12__FUNC_NLD12 (MTK_PIN_NO(29) | 1)
+#define MT8135_PIN_29_NLD12__FUNC_EINT158 (MTK_PIN_NO(29) | 2)
+#define MT8135_PIN_29_NLD12__FUNC_I2SIN_CK (MTK_PIN_NO(29) | 3)
+#define MT8135_PIN_29_NLD12__FUNC_DAC_CK (MTK_PIN_NO(29) | 4)
+#define MT8135_PIN_29_NLD12__FUNC_PCM1_CK (MTK_PIN_NO(29) | 5)
+
+#define MT8135_PIN_30_NLD13__FUNC_GPIO30 (MTK_PIN_NO(30) | 0)
+#define MT8135_PIN_30_NLD13__FUNC_NLD13 (MTK_PIN_NO(30) | 1)
+#define MT8135_PIN_30_NLD13__FUNC_EINT159 (MTK_PIN_NO(30) | 2)
+#define MT8135_PIN_30_NLD13__FUNC_I2SIN_WS (MTK_PIN_NO(30) | 3)
+#define MT8135_PIN_30_NLD13__FUNC_DAC_WS (MTK_PIN_NO(30) | 4)
+#define MT8135_PIN_30_NLD13__FUNC_PCM1_WS (MTK_PIN_NO(30) | 5)
+
+#define MT8135_PIN_31_NLD14__FUNC_GPIO31 (MTK_PIN_NO(31) | 0)
+#define MT8135_PIN_31_NLD14__FUNC_NLD14 (MTK_PIN_NO(31) | 1)
+#define MT8135_PIN_31_NLD14__FUNC_EINT160 (MTK_PIN_NO(31) | 2)
+#define MT8135_PIN_31_NLD14__FUNC_I2SOUT_DAT (MTK_PIN_NO(31) | 3)
+#define MT8135_PIN_31_NLD14__FUNC_DAC_DAT_OUT (MTK_PIN_NO(31) | 4)
+#define MT8135_PIN_31_NLD14__FUNC_PCM1_DO (MTK_PIN_NO(31) | 5)
+
+#define MT8135_PIN_32_NLD15__FUNC_GPIO32 (MTK_PIN_NO(32) | 0)
+#define MT8135_PIN_32_NLD15__FUNC_NLD15 (MTK_PIN_NO(32) | 1)
+#define MT8135_PIN_32_NLD15__FUNC_EINT161 (MTK_PIN_NO(32) | 2)
+#define MT8135_PIN_32_NLD15__FUNC_DISP_PWM (MTK_PIN_NO(32) | 3)
+#define MT8135_PIN_32_NLD15__FUNC_PWM4 (MTK_PIN_NO(32) | 4)
+#define MT8135_PIN_32_NLD15__FUNC_PCM1_DI (MTK_PIN_NO(32) | 5)
+
+#define MT8135_PIN_33_MSDC0_RSTB__FUNC_GPIO33 (MTK_PIN_NO(33) | 0)
+#define MT8135_PIN_33_MSDC0_RSTB__FUNC_MSDC0_RSTB (MTK_PIN_NO(33) | 1)
+#define MT8135_PIN_33_MSDC0_RSTB__FUNC_EINT50 (MTK_PIN_NO(33) | 2)
+#define MT8135_PIN_33_MSDC0_RSTB__FUNC_I2SIN_DAT (MTK_PIN_NO(33) | 3)
+#define MT8135_PIN_33_MSDC0_RSTB__FUNC_PCM1_DI (MTK_PIN_NO(33) | 5)
+#define MT8135_PIN_33_MSDC0_RSTB__FUNC_SPI1_MI (MTK_PIN_NO(33) | 6)
+#define MT8135_PIN_33_MSDC0_RSTB__FUNC_NLD10 (MTK_PIN_NO(33) | 7)
+
+#define MT8135_PIN_34_IDDIG__FUNC_GPIO34 (MTK_PIN_NO(34) | 0)
+#define MT8135_PIN_34_IDDIG__FUNC_IDDIG (MTK_PIN_NO(34) | 1)
+#define MT8135_PIN_34_IDDIG__FUNC_EINT34 (MTK_PIN_NO(34) | 2)
+
+#define MT8135_PIN_35_SCL3__FUNC_GPIO35 (MTK_PIN_NO(35) | 0)
+#define MT8135_PIN_35_SCL3__FUNC_SCL3 (MTK_PIN_NO(35) | 1)
+#define MT8135_PIN_35_SCL3__FUNC_EINT96 (MTK_PIN_NO(35) | 2)
+#define MT8135_PIN_35_SCL3__FUNC_CLKM6 (MTK_PIN_NO(35) | 3)
+#define MT8135_PIN_35_SCL3__FUNC_PWM6 (MTK_PIN_NO(35) | 4)
+
+#define MT8135_PIN_36_SDA3__FUNC_GPIO36 (MTK_PIN_NO(36) | 0)
+#define MT8135_PIN_36_SDA3__FUNC_SDA3 (MTK_PIN_NO(36) | 1)
+#define MT8135_PIN_36_SDA3__FUNC_EINT97 (MTK_PIN_NO(36) | 2)
+
+#define MT8135_PIN_37_AUD_CLK_MOSI__FUNC_GPIO37 (MTK_PIN_NO(37) | 0)
+#define MT8135_PIN_37_AUD_CLK_MOSI__FUNC_AUD_CLK (MTK_PIN_NO(37) | 1)
+#define MT8135_PIN_37_AUD_CLK_MOSI__FUNC_ADC_CK (MTK_PIN_NO(37) | 2)
+#define MT8135_PIN_37_AUD_CLK_MOSI__FUNC_HDMI_SDATA0 (MTK_PIN_NO(37) | 3)
+#define MT8135_PIN_37_AUD_CLK_MOSI__FUNC_EINT19 (MTK_PIN_NO(37) | 4)
+#define MT8135_PIN_37_AUD_CLK_MOSI__FUNC_USB_TEST_IO_6 (MTK_PIN_NO(37) | 5)
+#define MT8135_PIN_37_AUD_CLK_MOSI__FUNC_TESTA_OUT19 (MTK_PIN_NO(37) | 7)
+
+#define MT8135_PIN_38_AUD_DAT_MOSI__FUNC_GPIO38 (MTK_PIN_NO(38) | 0)
+#define MT8135_PIN_38_AUD_DAT_MOSI__FUNC_AUD_DAT_MOSI (MTK_PIN_NO(38) | 1)
+#define MT8135_PIN_38_AUD_DAT_MOSI__FUNC_ADC_WS (MTK_PIN_NO(38) | 2)
+#define MT8135_PIN_38_AUD_DAT_MOSI__FUNC_AUD_DAT_MISO (MTK_PIN_NO(38) | 3)
+#define MT8135_PIN_38_AUD_DAT_MOSI__FUNC_EINT21 (MTK_PIN_NO(38) | 4)
+#define MT8135_PIN_38_AUD_DAT_MOSI__FUNC_USB_TEST_IO_7 (MTK_PIN_NO(38) | 5)
+#define MT8135_PIN_38_AUD_DAT_MOSI__FUNC_TESTA_OUT20 (MTK_PIN_NO(38) | 7)
+
+#define MT8135_PIN_39_AUD_DAT_MISO__FUNC_GPIO39 (MTK_PIN_NO(39) | 0)
+#define MT8135_PIN_39_AUD_DAT_MISO__FUNC_AUD_DAT_MISO (MTK_PIN_NO(39) | 1)
+#define MT8135_PIN_39_AUD_DAT_MISO__FUNC_ADC_DAT_IN (MTK_PIN_NO(39) | 2)
+#define MT8135_PIN_39_AUD_DAT_MISO__FUNC_AUD_DAT_MOSI (MTK_PIN_NO(39) | 3)
+#define MT8135_PIN_39_AUD_DAT_MISO__FUNC_EINT20 (MTK_PIN_NO(39) | 4)
+#define MT8135_PIN_39_AUD_DAT_MISO__FUNC_USB_TEST_IO_8 (MTK_PIN_NO(39) | 5)
+#define MT8135_PIN_39_AUD_DAT_MISO__FUNC_TESTA_OUT21 (MTK_PIN_NO(39) | 7)
+
+#define MT8135_PIN_40_DAC_CLK__FUNC_GPIO40 (MTK_PIN_NO(40) | 0)
+#define MT8135_PIN_40_DAC_CLK__FUNC_DAC_CK (MTK_PIN_NO(40) | 1)
+#define MT8135_PIN_40_DAC_CLK__FUNC_EINT22 (MTK_PIN_NO(40) | 2)
+#define MT8135_PIN_40_DAC_CLK__FUNC_HDMI_SDATA1 (MTK_PIN_NO(40) | 3)
+#define MT8135_PIN_40_DAC_CLK__FUNC_USB_TEST_IO_9 (MTK_PIN_NO(40) | 5)
+#define MT8135_PIN_40_DAC_CLK__FUNC_TESTA_OUT22 (MTK_PIN_NO(40) | 7)
+
+#define MT8135_PIN_41_DAC_WS__FUNC_GPIO41 (MTK_PIN_NO(41) | 0)
+#define MT8135_PIN_41_DAC_WS__FUNC_DAC_WS (MTK_PIN_NO(41) | 1)
+#define MT8135_PIN_41_DAC_WS__FUNC_EINT24 (MTK_PIN_NO(41) | 2)
+#define MT8135_PIN_41_DAC_WS__FUNC_HDMI_SDATA2 (MTK_PIN_NO(41) | 3)
+#define MT8135_PIN_41_DAC_WS__FUNC_USB_TEST_IO_10 (MTK_PIN_NO(41) | 5)
+#define MT8135_PIN_41_DAC_WS__FUNC_TESTA_OUT23 (MTK_PIN_NO(41) | 7)
+
+#define MT8135_PIN_42_DAC_DAT_OUT__FUNC_GPIO42 (MTK_PIN_NO(42) | 0)
+#define MT8135_PIN_42_DAC_DAT_OUT__FUNC_DAC_DAT_OUT (MTK_PIN_NO(42) | 1)
+#define MT8135_PIN_42_DAC_DAT_OUT__FUNC_EINT23 (MTK_PIN_NO(42) | 2)
+#define MT8135_PIN_42_DAC_DAT_OUT__FUNC_HDMI_SDATA3 (MTK_PIN_NO(42) | 3)
+#define MT8135_PIN_42_DAC_DAT_OUT__FUNC_USB_TEST_IO_11 (MTK_PIN_NO(42) | 5)
+#define MT8135_PIN_42_DAC_DAT_OUT__FUNC_TESTA_OUT24 (MTK_PIN_NO(42) | 7)
+
+#define MT8135_PIN_43_PWRAP_SPI0_MO__FUNC_GPIO43 (MTK_PIN_NO(43) | 0)
+#define MT8135_PIN_43_PWRAP_SPI0_MO__FUNC_PWRAP_SPIDI (MTK_PIN_NO(43) | 1)
+#define MT8135_PIN_43_PWRAP_SPI0_MO__FUNC_EINT29 (MTK_PIN_NO(43) | 2)
+
+#define MT8135_PIN_44_PWRAP_SPI0_MI__FUNC_GPIO44 (MTK_PIN_NO(44) | 0)
+#define MT8135_PIN_44_PWRAP_SPI0_MI__FUNC_PWRAP_SPIDO (MTK_PIN_NO(44) | 1)
+#define MT8135_PIN_44_PWRAP_SPI0_MI__FUNC_EINT28 (MTK_PIN_NO(44) | 2)
+
+#define MT8135_PIN_45_PWRAP_SPI0_CSN__FUNC_GPIO45 (MTK_PIN_NO(45) | 0)
+#define MT8135_PIN_45_PWRAP_SPI0_CSN__FUNC_PWRAP_SPICS_B_I (MTK_PIN_NO(45) | 1)
+#define MT8135_PIN_45_PWRAP_SPI0_CSN__FUNC_EINT27 (MTK_PIN_NO(45) | 2)
+
+#define MT8135_PIN_46_PWRAP_SPI0_CLK__FUNC_GPIO46 (MTK_PIN_NO(46) | 0)
+#define MT8135_PIN_46_PWRAP_SPI0_CLK__FUNC_PWRAP_SPICK_I (MTK_PIN_NO(46) | 1)
+#define MT8135_PIN_46_PWRAP_SPI0_CLK__FUNC_EINT26 (MTK_PIN_NO(46) | 2)
+
+#define MT8135_PIN_47_PWRAP_EVENT__FUNC_GPIO47 (MTK_PIN_NO(47) | 0)
+#define MT8135_PIN_47_PWRAP_EVENT__FUNC_PWRAP_EVENT_IN (MTK_PIN_NO(47) | 1)
+#define MT8135_PIN_47_PWRAP_EVENT__FUNC_EINT25 (MTK_PIN_NO(47) | 2)
+#define MT8135_PIN_47_PWRAP_EVENT__FUNC_TESTA_OUT2 (MTK_PIN_NO(47) | 7)
+
+#define MT8135_PIN_48_RTC32K_CK__FUNC_GPIO48 (MTK_PIN_NO(48) | 0)
+#define MT8135_PIN_48_RTC32K_CK__FUNC_RTC32K_CK (MTK_PIN_NO(48) | 1)
+
+#define MT8135_PIN_49_WATCHDOG__FUNC_GPIO49 (MTK_PIN_NO(49) | 0)
+#define MT8135_PIN_49_WATCHDOG__FUNC_WATCHDOG (MTK_PIN_NO(49) | 1)
+#define MT8135_PIN_49_WATCHDOG__FUNC_EINT36 (MTK_PIN_NO(49) | 2)
+
+#define MT8135_PIN_50_SRCLKENA__FUNC_GPIO50 (MTK_PIN_NO(50) | 0)
+#define MT8135_PIN_50_SRCLKENA__FUNC_SRCLKENA (MTK_PIN_NO(50) | 1)
+#define MT8135_PIN_50_SRCLKENA__FUNC_EINT38 (MTK_PIN_NO(50) | 2)
+
+#define MT8135_PIN_51_SRCVOLTEN__FUNC_GPIO51 (MTK_PIN_NO(51) | 0)
+#define MT8135_PIN_51_SRCVOLTEN__FUNC_SRCVOLTEN (MTK_PIN_NO(51) | 1)
+#define MT8135_PIN_51_SRCVOLTEN__FUNC_EINT37 (MTK_PIN_NO(51) | 2)
+
+#define MT8135_PIN_52_EINT0__FUNC_GPIO52 (MTK_PIN_NO(52) | 0)
+#define MT8135_PIN_52_EINT0__FUNC_EINT0 (MTK_PIN_NO(52) | 1)
+#define MT8135_PIN_52_EINT0__FUNC_PWM1 (MTK_PIN_NO(52) | 2)
+#define MT8135_PIN_52_EINT0__FUNC_CLKM0 (MTK_PIN_NO(52) | 3)
+#define MT8135_PIN_52_EINT0__FUNC_SPDIF_OUT (MTK_PIN_NO(52) | 4)
+#define MT8135_PIN_52_EINT0__FUNC_USB_TEST_IO_12 (MTK_PIN_NO(52) | 5)
+#define MT8135_PIN_52_EINT0__FUNC_USB_SCL (MTK_PIN_NO(52) | 7)
+
+#define MT8135_PIN_53_URXD2__FUNC_GPIO53 (MTK_PIN_NO(53) | 0)
+#define MT8135_PIN_53_URXD2__FUNC_URXD2 (MTK_PIN_NO(53) | 1)
+#define MT8135_PIN_53_URXD2__FUNC_EINT83 (MTK_PIN_NO(53) | 2)
+#define MT8135_PIN_53_URXD2__FUNC_HDMI_LRCK (MTK_PIN_NO(53) | 4)
+#define MT8135_PIN_53_URXD2__FUNC_CLKM3 (MTK_PIN_NO(53) | 5)
+#define MT8135_PIN_53_URXD2__FUNC_UTXD2 (MTK_PIN_NO(53) | 7)
+
+#define MT8135_PIN_54_UTXD2__FUNC_GPIO54 (MTK_PIN_NO(54) | 0)
+#define MT8135_PIN_54_UTXD2__FUNC_UTXD2 (MTK_PIN_NO(54) | 1)
+#define MT8135_PIN_54_UTXD2__FUNC_EINT82 (MTK_PIN_NO(54) | 2)
+#define MT8135_PIN_54_UTXD2__FUNC_HDMI_BCK_OUT (MTK_PIN_NO(54) | 4)
+#define MT8135_PIN_54_UTXD2__FUNC_CLKM2 (MTK_PIN_NO(54) | 5)
+#define MT8135_PIN_54_UTXD2__FUNC_URXD2 (MTK_PIN_NO(54) | 7)
+
+#define MT8135_PIN_55_UCTS2__FUNC_GPIO55 (MTK_PIN_NO(55) | 0)
+#define MT8135_PIN_55_UCTS2__FUNC_UCTS2 (MTK_PIN_NO(55) | 1)
+#define MT8135_PIN_55_UCTS2__FUNC_EINT84 (MTK_PIN_NO(55) | 2)
+#define MT8135_PIN_55_UCTS2__FUNC_PWM1 (MTK_PIN_NO(55) | 5)
+#define MT8135_PIN_55_UCTS2__FUNC_URTS2 (MTK_PIN_NO(55) | 7)
+
+#define MT8135_PIN_56_URTS2__FUNC_GPIO56 (MTK_PIN_NO(56) | 0)
+#define MT8135_PIN_56_URTS2__FUNC_URTS2 (MTK_PIN_NO(56) | 1)
+#define MT8135_PIN_56_URTS2__FUNC_EINT85 (MTK_PIN_NO(56) | 2)
+#define MT8135_PIN_56_URTS2__FUNC_PWM2 (MTK_PIN_NO(56) | 5)
+#define MT8135_PIN_56_URTS2__FUNC_UCTS2 (MTK_PIN_NO(56) | 7)
+
+#define MT8135_PIN_57_JTCK__FUNC_GPIO57 (MTK_PIN_NO(57) | 0)
+#define MT8135_PIN_57_JTCK__FUNC_JTCK (MTK_PIN_NO(57) | 1)
+#define MT8135_PIN_57_JTCK__FUNC_EINT188 (MTK_PIN_NO(57) | 2)
+#define MT8135_PIN_57_JTCK__FUNC_DSP1_ICK (MTK_PIN_NO(57) | 3)
+
+#define MT8135_PIN_58_JTDO__FUNC_GPIO58 (MTK_PIN_NO(58) | 0)
+#define MT8135_PIN_58_JTDO__FUNC_JTDO (MTK_PIN_NO(58) | 1)
+#define MT8135_PIN_58_JTDO__FUNC_EINT190 (MTK_PIN_NO(58) | 2)
+#define MT8135_PIN_58_JTDO__FUNC_DSP2_IMS (MTK_PIN_NO(58) | 3)
+
+#define MT8135_PIN_59_JTRST_B__FUNC_GPIO59 (MTK_PIN_NO(59) | 0)
+#define MT8135_PIN_59_JTRST_B__FUNC_JTRST_B (MTK_PIN_NO(59) | 1)
+#define MT8135_PIN_59_JTRST_B__FUNC_EINT0 (MTK_PIN_NO(59) | 2)
+#define MT8135_PIN_59_JTRST_B__FUNC_DSP2_ICK (MTK_PIN_NO(59) | 3)
+
+#define MT8135_PIN_60_JTDI__FUNC_GPIO60 (MTK_PIN_NO(60) | 0)
+#define MT8135_PIN_60_JTDI__FUNC_JTDI (MTK_PIN_NO(60) | 1)
+#define MT8135_PIN_60_JTDI__FUNC_EINT189 (MTK_PIN_NO(60) | 2)
+#define MT8135_PIN_60_JTDI__FUNC_DSP1_IMS (MTK_PIN_NO(60) | 3)
+
+#define MT8135_PIN_61_JRTCK__FUNC_GPIO61 (MTK_PIN_NO(61) | 0)
+#define MT8135_PIN_61_JRTCK__FUNC_JRTCK (MTK_PIN_NO(61) | 1)
+#define MT8135_PIN_61_JRTCK__FUNC_EINT187 (MTK_PIN_NO(61) | 2)
+#define MT8135_PIN_61_JRTCK__FUNC_DSP1_ID (MTK_PIN_NO(61) | 3)
+
+#define MT8135_PIN_62_JTMS__FUNC_GPIO62 (MTK_PIN_NO(62) | 0)
+#define MT8135_PIN_62_JTMS__FUNC_JTMS (MTK_PIN_NO(62) | 1)
+#define MT8135_PIN_62_JTMS__FUNC_EINT191 (MTK_PIN_NO(62) | 2)
+#define MT8135_PIN_62_JTMS__FUNC_DSP2_ID (MTK_PIN_NO(62) | 3)
+
+#define MT8135_PIN_63_MSDC1_INSI__FUNC_GPIO63 (MTK_PIN_NO(63) | 0)
+#define MT8135_PIN_63_MSDC1_INSI__FUNC_MSDC1_INSI (MTK_PIN_NO(63) | 1)
+#define MT8135_PIN_63_MSDC1_INSI__FUNC_SCL5 (MTK_PIN_NO(63) | 3)
+#define MT8135_PIN_63_MSDC1_INSI__FUNC_PWM6 (MTK_PIN_NO(63) | 4)
+#define MT8135_PIN_63_MSDC1_INSI__FUNC_CLKM5 (MTK_PIN_NO(63) | 5)
+#define MT8135_PIN_63_MSDC1_INSI__FUNC_TESTB_OUT6 (MTK_PIN_NO(63) | 7)
+
+#define MT8135_PIN_64_MSDC1_SDWPI__FUNC_GPIO64 (MTK_PIN_NO(64) | 0)
+#define MT8135_PIN_64_MSDC1_SDWPI__FUNC_MSDC1_SDWPI (MTK_PIN_NO(64) | 1)
+#define MT8135_PIN_64_MSDC1_SDWPI__FUNC_EINT58 (MTK_PIN_NO(64) | 2)
+#define MT8135_PIN_64_MSDC1_SDWPI__FUNC_SDA5 (MTK_PIN_NO(64) | 3)
+#define MT8135_PIN_64_MSDC1_SDWPI__FUNC_PWM7 (MTK_PIN_NO(64) | 4)
+#define MT8135_PIN_64_MSDC1_SDWPI__FUNC_CLKM6 (MTK_PIN_NO(64) | 5)
+#define MT8135_PIN_64_MSDC1_SDWPI__FUNC_TESTB_OUT7 (MTK_PIN_NO(64) | 7)
+
+#define MT8135_PIN_65_MSDC2_INSI__FUNC_GPIO65 (MTK_PIN_NO(65) | 0)
+#define MT8135_PIN_65_MSDC2_INSI__FUNC_MSDC2_INSI (MTK_PIN_NO(65) | 1)
+#define MT8135_PIN_65_MSDC2_INSI__FUNC_USB_TEST_IO_27 (MTK_PIN_NO(65) | 5)
+#define MT8135_PIN_65_MSDC2_INSI__FUNC_TESTA_OUT3 (MTK_PIN_NO(65) | 7)
+
+#define MT8135_PIN_66_MSDC2_SDWPI__FUNC_GPIO66 (MTK_PIN_NO(66) | 0)
+#define MT8135_PIN_66_MSDC2_SDWPI__FUNC_MSDC2_SDWPI (MTK_PIN_NO(66) | 1)
+#define MT8135_PIN_66_MSDC2_SDWPI__FUNC_EINT66 (MTK_PIN_NO(66) | 2)
+#define MT8135_PIN_66_MSDC2_SDWPI__FUNC_USB_TEST_IO_28 (MTK_PIN_NO(66) | 5)
+
+#define MT8135_PIN_67_URXD4__FUNC_GPIO67 (MTK_PIN_NO(67) | 0)
+#define MT8135_PIN_67_URXD4__FUNC_URXD4 (MTK_PIN_NO(67) | 1)
+#define MT8135_PIN_67_URXD4__FUNC_EINT89 (MTK_PIN_NO(67) | 2)
+#define MT8135_PIN_67_URXD4__FUNC_URXD1 (MTK_PIN_NO(67) | 3)
+#define MT8135_PIN_67_URXD4__FUNC_UTXD4 (MTK_PIN_NO(67) | 6)
+#define MT8135_PIN_67_URXD4__FUNC_TESTB_OUT10 (MTK_PIN_NO(67) | 7)
+
+#define MT8135_PIN_68_UTXD4__FUNC_GPIO68 (MTK_PIN_NO(68) | 0)
+#define MT8135_PIN_68_UTXD4__FUNC_UTXD4 (MTK_PIN_NO(68) | 1)
+#define MT8135_PIN_68_UTXD4__FUNC_EINT88 (MTK_PIN_NO(68) | 2)
+#define MT8135_PIN_68_UTXD4__FUNC_UTXD1 (MTK_PIN_NO(68) | 3)
+#define MT8135_PIN_68_UTXD4__FUNC_URXD4 (MTK_PIN_NO(68) | 6)
+#define MT8135_PIN_68_UTXD4__FUNC_TESTB_OUT11 (MTK_PIN_NO(68) | 7)
+
+#define MT8135_PIN_69_URXD1__FUNC_GPIO69 (MTK_PIN_NO(69) | 0)
+#define MT8135_PIN_69_URXD1__FUNC_URXD1 (MTK_PIN_NO(69) | 1)
+#define MT8135_PIN_69_URXD1__FUNC_EINT79 (MTK_PIN_NO(69) | 2)
+#define MT8135_PIN_69_URXD1__FUNC_URXD4 (MTK_PIN_NO(69) | 3)
+#define MT8135_PIN_69_URXD1__FUNC_UTXD1 (MTK_PIN_NO(69) | 6)
+#define MT8135_PIN_69_URXD1__FUNC_TESTB_OUT24 (MTK_PIN_NO(69) | 7)
+
+#define MT8135_PIN_70_UTXD1__FUNC_GPIO70 (MTK_PIN_NO(70) | 0)
+#define MT8135_PIN_70_UTXD1__FUNC_UTXD1 (MTK_PIN_NO(70) | 1)
+#define MT8135_PIN_70_UTXD1__FUNC_EINT78 (MTK_PIN_NO(70) | 2)
+#define MT8135_PIN_70_UTXD1__FUNC_UTXD4 (MTK_PIN_NO(70) | 3)
+#define MT8135_PIN_70_UTXD1__FUNC_URXD1 (MTK_PIN_NO(70) | 6)
+#define MT8135_PIN_70_UTXD1__FUNC_TESTB_OUT25 (MTK_PIN_NO(70) | 7)
+
+#define MT8135_PIN_71_UCTS1__FUNC_GPIO71 (MTK_PIN_NO(71) | 0)
+#define MT8135_PIN_71_UCTS1__FUNC_UCTS1 (MTK_PIN_NO(71) | 1)
+#define MT8135_PIN_71_UCTS1__FUNC_EINT80 (MTK_PIN_NO(71) | 2)
+#define MT8135_PIN_71_UCTS1__FUNC_CLKM0 (MTK_PIN_NO(71) | 5)
+#define MT8135_PIN_71_UCTS1__FUNC_URTS1 (MTK_PIN_NO(71) | 6)
+#define MT8135_PIN_71_UCTS1__FUNC_TESTB_OUT31 (MTK_PIN_NO(71) | 7)
+
+#define MT8135_PIN_72_URTS1__FUNC_GPIO72 (MTK_PIN_NO(72) | 0)
+#define MT8135_PIN_72_URTS1__FUNC_URTS1 (MTK_PIN_NO(72) | 1)
+#define MT8135_PIN_72_URTS1__FUNC_EINT81 (MTK_PIN_NO(72) | 2)
+#define MT8135_PIN_72_URTS1__FUNC_CLKM1 (MTK_PIN_NO(72) | 5)
+#define MT8135_PIN_72_URTS1__FUNC_UCTS1 (MTK_PIN_NO(72) | 6)
+#define MT8135_PIN_72_URTS1__FUNC_TESTB_OUT21 (MTK_PIN_NO(72) | 7)
+
+#define MT8135_PIN_73_PWM1__FUNC_GPIO73 (MTK_PIN_NO(73) | 0)
+#define MT8135_PIN_73_PWM1__FUNC_PWM1 (MTK_PIN_NO(73) | 1)
+#define MT8135_PIN_73_PWM1__FUNC_EINT73 (MTK_PIN_NO(73) | 2)
+#define MT8135_PIN_73_PWM1__FUNC_USB_DRVVBUS (MTK_PIN_NO(73) | 5)
+#define MT8135_PIN_73_PWM1__FUNC_DISP_PWM (MTK_PIN_NO(73) | 6)
+#define MT8135_PIN_73_PWM1__FUNC_TESTB_OUT8 (MTK_PIN_NO(73) | 7)
+
+#define MT8135_PIN_74_PWM2__FUNC_GPIO74 (MTK_PIN_NO(74) | 0)
+#define MT8135_PIN_74_PWM2__FUNC_PWM2 (MTK_PIN_NO(74) | 1)
+#define MT8135_PIN_74_PWM2__FUNC_EINT74 (MTK_PIN_NO(74) | 2)
+#define MT8135_PIN_74_PWM2__FUNC_DPI33_CK (MTK_PIN_NO(74) | 3)
+#define MT8135_PIN_74_PWM2__FUNC_PWM5 (MTK_PIN_NO(74) | 4)
+#define MT8135_PIN_74_PWM2__FUNC_URXD2 (MTK_PIN_NO(74) | 5)
+#define MT8135_PIN_74_PWM2__FUNC_DISP_PWM (MTK_PIN_NO(74) | 6)
+#define MT8135_PIN_74_PWM2__FUNC_TESTB_OUT9 (MTK_PIN_NO(74) | 7)
+
+#define MT8135_PIN_75_PWM3__FUNC_GPIO75 (MTK_PIN_NO(75) | 0)
+#define MT8135_PIN_75_PWM3__FUNC_PWM3 (MTK_PIN_NO(75) | 1)
+#define MT8135_PIN_75_PWM3__FUNC_EINT75 (MTK_PIN_NO(75) | 2)
+#define MT8135_PIN_75_PWM3__FUNC_DPI33_D0 (MTK_PIN_NO(75) | 3)
+#define MT8135_PIN_75_PWM3__FUNC_PWM6 (MTK_PIN_NO(75) | 4)
+#define MT8135_PIN_75_PWM3__FUNC_UTXD2 (MTK_PIN_NO(75) | 5)
+#define MT8135_PIN_75_PWM3__FUNC_DISP_PWM (MTK_PIN_NO(75) | 6)
+#define MT8135_PIN_75_PWM3__FUNC_TESTB_OUT12 (MTK_PIN_NO(75) | 7)
+
+#define MT8135_PIN_76_PWM4__FUNC_GPIO76 (MTK_PIN_NO(76) | 0)
+#define MT8135_PIN_76_PWM4__FUNC_PWM4 (MTK_PIN_NO(76) | 1)
+#define MT8135_PIN_76_PWM4__FUNC_EINT76 (MTK_PIN_NO(76) | 2)
+#define MT8135_PIN_76_PWM4__FUNC_DPI33_D1 (MTK_PIN_NO(76) | 3)
+#define MT8135_PIN_76_PWM4__FUNC_PWM7 (MTK_PIN_NO(76) | 4)
+#define MT8135_PIN_76_PWM4__FUNC_DISP_PWM (MTK_PIN_NO(76) | 6)
+#define MT8135_PIN_76_PWM4__FUNC_TESTB_OUT13 (MTK_PIN_NO(76) | 7)
+
+#define MT8135_PIN_77_MSDC2_DAT2__FUNC_GPIO77 (MTK_PIN_NO(77) | 0)
+#define MT8135_PIN_77_MSDC2_DAT2__FUNC_MSDC2_DAT2 (MTK_PIN_NO(77) | 1)
+#define MT8135_PIN_77_MSDC2_DAT2__FUNC_EINT63 (MTK_PIN_NO(77) | 2)
+#define MT8135_PIN_77_MSDC2_DAT2__FUNC_DSP2_IMS (MTK_PIN_NO(77) | 4)
+#define MT8135_PIN_77_MSDC2_DAT2__FUNC_DPI33_D6 (MTK_PIN_NO(77) | 6)
+#define MT8135_PIN_77_MSDC2_DAT2__FUNC_TESTA_OUT25 (MTK_PIN_NO(77) | 7)
+
+#define MT8135_PIN_78_MSDC2_DAT3__FUNC_GPIO78 (MTK_PIN_NO(78) | 0)
+#define MT8135_PIN_78_MSDC2_DAT3__FUNC_MSDC2_DAT3 (MTK_PIN_NO(78) | 1)
+#define MT8135_PIN_78_MSDC2_DAT3__FUNC_EINT64 (MTK_PIN_NO(78) | 2)
+#define MT8135_PIN_78_MSDC2_DAT3__FUNC_DSP2_ID (MTK_PIN_NO(78) | 4)
+#define MT8135_PIN_78_MSDC2_DAT3__FUNC_DPI33_D7 (MTK_PIN_NO(78) | 6)
+#define MT8135_PIN_78_MSDC2_DAT3__FUNC_TESTA_OUT26 (MTK_PIN_NO(78) | 7)
+
+#define MT8135_PIN_79_MSDC2_CMD__FUNC_GPIO79 (MTK_PIN_NO(79) | 0)
+#define MT8135_PIN_79_MSDC2_CMD__FUNC_MSDC2_CMD (MTK_PIN_NO(79) | 1)
+#define MT8135_PIN_79_MSDC2_CMD__FUNC_EINT60 (MTK_PIN_NO(79) | 2)
+#define MT8135_PIN_79_MSDC2_CMD__FUNC_DSP1_IMS (MTK_PIN_NO(79) | 4)
+#define MT8135_PIN_79_MSDC2_CMD__FUNC_PCM1_WS (MTK_PIN_NO(79) | 5)
+#define MT8135_PIN_79_MSDC2_CMD__FUNC_DPI33_D3 (MTK_PIN_NO(79) | 6)
+#define MT8135_PIN_79_MSDC2_CMD__FUNC_TESTA_OUT0 (MTK_PIN_NO(79) | 7)
+
+#define MT8135_PIN_80_MSDC2_CLK__FUNC_GPIO80 (MTK_PIN_NO(80) | 0)
+#define MT8135_PIN_80_MSDC2_CLK__FUNC_MSDC2_CLK (MTK_PIN_NO(80) | 1)
+#define MT8135_PIN_80_MSDC2_CLK__FUNC_EINT59 (MTK_PIN_NO(80) | 2)
+#define MT8135_PIN_80_MSDC2_CLK__FUNC_DSP1_ICK (MTK_PIN_NO(80) | 4)
+#define MT8135_PIN_80_MSDC2_CLK__FUNC_PCM1_CK (MTK_PIN_NO(80) | 5)
+#define MT8135_PIN_80_MSDC2_CLK__FUNC_DPI33_D2 (MTK_PIN_NO(80) | 6)
+#define MT8135_PIN_80_MSDC2_CLK__FUNC_TESTA_OUT1 (MTK_PIN_NO(80) | 7)
+
+#define MT8135_PIN_81_MSDC2_DAT1__FUNC_GPIO81 (MTK_PIN_NO(81) | 0)
+#define MT8135_PIN_81_MSDC2_DAT1__FUNC_MSDC2_DAT1 (MTK_PIN_NO(81) | 1)
+#define MT8135_PIN_81_MSDC2_DAT1__FUNC_EINT62 (MTK_PIN_NO(81) | 2)
+#define MT8135_PIN_81_MSDC2_DAT1__FUNC_DSP2_ICK (MTK_PIN_NO(81) | 4)
+#define MT8135_PIN_81_MSDC2_DAT1__FUNC_PCM1_DO (MTK_PIN_NO(81) | 5)
+#define MT8135_PIN_81_MSDC2_DAT1__FUNC_DPI33_D5 (MTK_PIN_NO(81) | 6)
+
+#define MT8135_PIN_82_MSDC2_DAT0__FUNC_GPIO82 (MTK_PIN_NO(82) | 0)
+#define MT8135_PIN_82_MSDC2_DAT0__FUNC_MSDC2_DAT0 (MTK_PIN_NO(82) | 1)
+#define MT8135_PIN_82_MSDC2_DAT0__FUNC_EINT61 (MTK_PIN_NO(82) | 2)
+#define MT8135_PIN_82_MSDC2_DAT0__FUNC_DSP1_ID (MTK_PIN_NO(82) | 4)
+#define MT8135_PIN_82_MSDC2_DAT0__FUNC_PCM1_DI (MTK_PIN_NO(82) | 5)
+#define MT8135_PIN_82_MSDC2_DAT0__FUNC_DPI33_D4 (MTK_PIN_NO(82) | 6)
+
+#define MT8135_PIN_83_MSDC1_DAT0__FUNC_GPIO83 (MTK_PIN_NO(83) | 0)
+#define MT8135_PIN_83_MSDC1_DAT0__FUNC_MSDC1_DAT0 (MTK_PIN_NO(83) | 1)
+#define MT8135_PIN_83_MSDC1_DAT0__FUNC_EINT53 (MTK_PIN_NO(83) | 2)
+#define MT8135_PIN_83_MSDC1_DAT0__FUNC_SCL1 (MTK_PIN_NO(83) | 3)
+#define MT8135_PIN_83_MSDC1_DAT0__FUNC_PWM2 (MTK_PIN_NO(83) | 4)
+#define MT8135_PIN_83_MSDC1_DAT0__FUNC_CLKM1 (MTK_PIN_NO(83) | 5)
+#define MT8135_PIN_83_MSDC1_DAT0__FUNC_TESTB_OUT2 (MTK_PIN_NO(83) | 7)
+
+#define MT8135_PIN_84_MSDC1_DAT1__FUNC_GPIO84 (MTK_PIN_NO(84) | 0)
+#define MT8135_PIN_84_MSDC1_DAT1__FUNC_MSDC1_DAT1 (MTK_PIN_NO(84) | 1)
+#define MT8135_PIN_84_MSDC1_DAT1__FUNC_EINT54 (MTK_PIN_NO(84) | 2)
+#define MT8135_PIN_84_MSDC1_DAT1__FUNC_SDA1 (MTK_PIN_NO(84) | 3)
+#define MT8135_PIN_84_MSDC1_DAT1__FUNC_PWM3 (MTK_PIN_NO(84) | 4)
+#define MT8135_PIN_84_MSDC1_DAT1__FUNC_CLKM2 (MTK_PIN_NO(84) | 5)
+#define MT8135_PIN_84_MSDC1_DAT1__FUNC_TESTB_OUT3 (MTK_PIN_NO(84) | 7)
+
+#define MT8135_PIN_85_MSDC1_CMD__FUNC_GPIO85 (MTK_PIN_NO(85) | 0)
+#define MT8135_PIN_85_MSDC1_CMD__FUNC_MSDC1_CMD (MTK_PIN_NO(85) | 1)
+#define MT8135_PIN_85_MSDC1_CMD__FUNC_EINT52 (MTK_PIN_NO(85) | 2)
+#define MT8135_PIN_85_MSDC1_CMD__FUNC_SDA0 (MTK_PIN_NO(85) | 3)
+#define MT8135_PIN_85_MSDC1_CMD__FUNC_PWM1 (MTK_PIN_NO(85) | 4)
+#define MT8135_PIN_85_MSDC1_CMD__FUNC_CLKM0 (MTK_PIN_NO(85) | 5)
+#define MT8135_PIN_85_MSDC1_CMD__FUNC_TESTB_OUT1 (MTK_PIN_NO(85) | 7)
+
+#define MT8135_PIN_86_MSDC1_CLK__FUNC_GPIO86 (MTK_PIN_NO(86) | 0)
+#define MT8135_PIN_86_MSDC1_CLK__FUNC_MSDC1_CLK (MTK_PIN_NO(86) | 1)
+#define MT8135_PIN_86_MSDC1_CLK__FUNC_EINT51 (MTK_PIN_NO(86) | 2)
+#define MT8135_PIN_86_MSDC1_CLK__FUNC_SCL0 (MTK_PIN_NO(86) | 3)
+#define MT8135_PIN_86_MSDC1_CLK__FUNC_DISP_PWM (MTK_PIN_NO(86) | 4)
+#define MT8135_PIN_86_MSDC1_CLK__FUNC_TESTB_OUT0 (MTK_PIN_NO(86) | 7)
+
+#define MT8135_PIN_87_MSDC1_DAT2__FUNC_GPIO87 (MTK_PIN_NO(87) | 0)
+#define MT8135_PIN_87_MSDC1_DAT2__FUNC_MSDC1_DAT2 (MTK_PIN_NO(87) | 1)
+#define MT8135_PIN_87_MSDC1_DAT2__FUNC_EINT55 (MTK_PIN_NO(87) | 2)
+#define MT8135_PIN_87_MSDC1_DAT2__FUNC_SCL4 (MTK_PIN_NO(87) | 3)
+#define MT8135_PIN_87_MSDC1_DAT2__FUNC_PWM4 (MTK_PIN_NO(87) | 4)
+#define MT8135_PIN_87_MSDC1_DAT2__FUNC_CLKM3 (MTK_PIN_NO(87) | 5)
+#define MT8135_PIN_87_MSDC1_DAT2__FUNC_TESTB_OUT4 (MTK_PIN_NO(87) | 7)
+
+#define MT8135_PIN_88_MSDC1_DAT3__FUNC_GPIO88 (MTK_PIN_NO(88) | 0)
+#define MT8135_PIN_88_MSDC1_DAT3__FUNC_MSDC1_DAT3 (MTK_PIN_NO(88) | 1)
+#define MT8135_PIN_88_MSDC1_DAT3__FUNC_EINT56 (MTK_PIN_NO(88) | 2)
+#define MT8135_PIN_88_MSDC1_DAT3__FUNC_SDA4 (MTK_PIN_NO(88) | 3)
+#define MT8135_PIN_88_MSDC1_DAT3__FUNC_PWM5 (MTK_PIN_NO(88) | 4)
+#define MT8135_PIN_88_MSDC1_DAT3__FUNC_CLKM4 (MTK_PIN_NO(88) | 5)
+#define MT8135_PIN_88_MSDC1_DAT3__FUNC_TESTB_OUT5 (MTK_PIN_NO(88) | 7)
+
+#define MT8135_PIN_89_MSDC4_DAT0__FUNC_GPIO89 (MTK_PIN_NO(89) | 0)
+#define MT8135_PIN_89_MSDC4_DAT0__FUNC_MSDC4_DAT0 (MTK_PIN_NO(89) | 1)
+#define MT8135_PIN_89_MSDC4_DAT0__FUNC_EINT133 (MTK_PIN_NO(89) | 2)
+#define MT8135_PIN_89_MSDC4_DAT0__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(89) | 4)
+#define MT8135_PIN_89_MSDC4_DAT0__FUNC_USB_DRVVBUS (MTK_PIN_NO(89) | 5)
+#define MT8135_PIN_89_MSDC4_DAT0__FUNC_A_FUNC_DIN_9 (MTK_PIN_NO(89) | 6)
+#define MT8135_PIN_89_MSDC4_DAT0__FUNC_LPTE (MTK_PIN_NO(89) | 7)
+
+#define MT8135_PIN_90_MSDC4_DAT1__FUNC_GPIO90 (MTK_PIN_NO(90) | 0)
+#define MT8135_PIN_90_MSDC4_DAT1__FUNC_MSDC4_DAT1 (MTK_PIN_NO(90) | 1)
+#define MT8135_PIN_90_MSDC4_DAT1__FUNC_EINT134 (MTK_PIN_NO(90) | 2)
+#define MT8135_PIN_90_MSDC4_DAT1__FUNC_A_FUNC_DIN_10 (MTK_PIN_NO(90) | 6)
+#define MT8135_PIN_90_MSDC4_DAT1__FUNC_LRSTB_1X (MTK_PIN_NO(90) | 7)
+
+#define MT8135_PIN_91_MSDC4_DAT5__FUNC_GPIO91 (MTK_PIN_NO(91) | 0)
+#define MT8135_PIN_91_MSDC4_DAT5__FUNC_MSDC4_DAT5 (MTK_PIN_NO(91) | 1)
+#define MT8135_PIN_91_MSDC4_DAT5__FUNC_EINT136 (MTK_PIN_NO(91) | 2)
+#define MT8135_PIN_91_MSDC4_DAT5__FUNC_I2SIN_WS (MTK_PIN_NO(91) | 3)
+#define MT8135_PIN_91_MSDC4_DAT5__FUNC_DAC_WS (MTK_PIN_NO(91) | 4)
+#define MT8135_PIN_91_MSDC4_DAT5__FUNC_PCM1_WS (MTK_PIN_NO(91) | 5)
+#define MT8135_PIN_91_MSDC4_DAT5__FUNC_A_FUNC_DIN_11 (MTK_PIN_NO(91) | 6)
+#define MT8135_PIN_91_MSDC4_DAT5__FUNC_SPI1_CSN (MTK_PIN_NO(91) | 7)
+
+#define MT8135_PIN_92_MSDC4_DAT6__FUNC_GPIO92 (MTK_PIN_NO(92) | 0)
+#define MT8135_PIN_92_MSDC4_DAT6__FUNC_MSDC4_DAT6 (MTK_PIN_NO(92) | 1)
+#define MT8135_PIN_92_MSDC4_DAT6__FUNC_EINT137 (MTK_PIN_NO(92) | 2)
+#define MT8135_PIN_92_MSDC4_DAT6__FUNC_I2SOUT_DAT (MTK_PIN_NO(92) | 3)
+#define MT8135_PIN_92_MSDC4_DAT6__FUNC_DAC_DAT_OUT (MTK_PIN_NO(92) | 4)
+#define MT8135_PIN_92_MSDC4_DAT6__FUNC_PCM1_DO (MTK_PIN_NO(92) | 5)
+#define MT8135_PIN_92_MSDC4_DAT6__FUNC_A_FUNC_DIN_12 (MTK_PIN_NO(92) | 6)
+#define MT8135_PIN_92_MSDC4_DAT6__FUNC_SPI1_MO (MTK_PIN_NO(92) | 7)
+
+#define MT8135_PIN_93_MSDC4_DAT7__FUNC_GPIO93 (MTK_PIN_NO(93) | 0)
+#define MT8135_PIN_93_MSDC4_DAT7__FUNC_MSDC4_DAT7 (MTK_PIN_NO(93) | 1)
+#define MT8135_PIN_93_MSDC4_DAT7__FUNC_EINT138 (MTK_PIN_NO(93) | 2)
+#define MT8135_PIN_93_MSDC4_DAT7__FUNC_I2SIN_DAT (MTK_PIN_NO(93) | 3)
+#define MT8135_PIN_93_MSDC4_DAT7__FUNC_PCM1_DI (MTK_PIN_NO(93) | 5)
+#define MT8135_PIN_93_MSDC4_DAT7__FUNC_A_FUNC_DIN_13 (MTK_PIN_NO(93) | 6)
+#define MT8135_PIN_93_MSDC4_DAT7__FUNC_SPI1_MI (MTK_PIN_NO(93) | 7)
+
+#define MT8135_PIN_94_MSDC4_DAT4__FUNC_GPIO94 (MTK_PIN_NO(94) | 0)
+#define MT8135_PIN_94_MSDC4_DAT4__FUNC_MSDC4_DAT4 (MTK_PIN_NO(94) | 1)
+#define MT8135_PIN_94_MSDC4_DAT4__FUNC_EINT135 (MTK_PIN_NO(94) | 2)
+#define MT8135_PIN_94_MSDC4_DAT4__FUNC_I2SIN_CK (MTK_PIN_NO(94) | 3)
+#define MT8135_PIN_94_MSDC4_DAT4__FUNC_DAC_CK (MTK_PIN_NO(94) | 4)
+#define MT8135_PIN_94_MSDC4_DAT4__FUNC_PCM1_CK (MTK_PIN_NO(94) | 5)
+#define MT8135_PIN_94_MSDC4_DAT4__FUNC_A_FUNC_DIN_14 (MTK_PIN_NO(94) | 6)
+#define MT8135_PIN_94_MSDC4_DAT4__FUNC_SPI1_CLK (MTK_PIN_NO(94) | 7)
+
+#define MT8135_PIN_95_MSDC4_DAT2__FUNC_GPIO95 (MTK_PIN_NO(95) | 0)
+#define MT8135_PIN_95_MSDC4_DAT2__FUNC_MSDC4_DAT2 (MTK_PIN_NO(95) | 1)
+#define MT8135_PIN_95_MSDC4_DAT2__FUNC_EINT131 (MTK_PIN_NO(95) | 2)
+#define MT8135_PIN_95_MSDC4_DAT2__FUNC_I2SIN_WS (MTK_PIN_NO(95) | 3)
+#define MT8135_PIN_95_MSDC4_DAT2__FUNC_CM2PDN_2X (MTK_PIN_NO(95) | 4)
+#define MT8135_PIN_95_MSDC4_DAT2__FUNC_DAC_WS (MTK_PIN_NO(95) | 5)
+#define MT8135_PIN_95_MSDC4_DAT2__FUNC_PCM1_WS (MTK_PIN_NO(95) | 6)
+#define MT8135_PIN_95_MSDC4_DAT2__FUNC_LSCE0B_1X (MTK_PIN_NO(95) | 7)
+
+#define MT8135_PIN_96_MSDC4_CLK__FUNC_GPIO96 (MTK_PIN_NO(96) | 0)
+#define MT8135_PIN_96_MSDC4_CLK__FUNC_MSDC4_CLK (MTK_PIN_NO(96) | 1)
+#define MT8135_PIN_96_MSDC4_CLK__FUNC_EINT129 (MTK_PIN_NO(96) | 2)
+#define MT8135_PIN_96_MSDC4_CLK__FUNC_DPI1_CK_2X (MTK_PIN_NO(96) | 3)
+#define MT8135_PIN_96_MSDC4_CLK__FUNC_CM2PCLK_2X (MTK_PIN_NO(96) | 4)
+#define MT8135_PIN_96_MSDC4_CLK__FUNC_PWM4 (MTK_PIN_NO(96) | 5)
+#define MT8135_PIN_96_MSDC4_CLK__FUNC_PCM1_DI (MTK_PIN_NO(96) | 6)
+#define MT8135_PIN_96_MSDC4_CLK__FUNC_LSCK_1X (MTK_PIN_NO(96) | 7)
+
+#define MT8135_PIN_97_MSDC4_DAT3__FUNC_GPIO97 (MTK_PIN_NO(97) | 0)
+#define MT8135_PIN_97_MSDC4_DAT3__FUNC_MSDC4_DAT3 (MTK_PIN_NO(97) | 1)
+#define MT8135_PIN_97_MSDC4_DAT3__FUNC_EINT132 (MTK_PIN_NO(97) | 2)
+#define MT8135_PIN_97_MSDC4_DAT3__FUNC_I2SOUT_DAT (MTK_PIN_NO(97) | 3)
+#define MT8135_PIN_97_MSDC4_DAT3__FUNC_CM2RST_2X (MTK_PIN_NO(97) | 4)
+#define MT8135_PIN_97_MSDC4_DAT3__FUNC_DAC_DAT_OUT (MTK_PIN_NO(97) | 5)
+#define MT8135_PIN_97_MSDC4_DAT3__FUNC_PCM1_DO (MTK_PIN_NO(97) | 6)
+#define MT8135_PIN_97_MSDC4_DAT3__FUNC_LSCE1B_1X (MTK_PIN_NO(97) | 7)
+
+#define MT8135_PIN_98_MSDC4_CMD__FUNC_GPIO98 (MTK_PIN_NO(98) | 0)
+#define MT8135_PIN_98_MSDC4_CMD__FUNC_MSDC4_CMD (MTK_PIN_NO(98) | 1)
+#define MT8135_PIN_98_MSDC4_CMD__FUNC_EINT128 (MTK_PIN_NO(98) | 2)
+#define MT8135_PIN_98_MSDC4_CMD__FUNC_DPI1_DE_2X (MTK_PIN_NO(98) | 3)
+#define MT8135_PIN_98_MSDC4_CMD__FUNC_PWM3 (MTK_PIN_NO(98) | 5)
+#define MT8135_PIN_98_MSDC4_CMD__FUNC_LSDA_1X (MTK_PIN_NO(98) | 7)
+
+#define MT8135_PIN_99_MSDC4_RSTB__FUNC_GPIO99 (MTK_PIN_NO(99) | 0)
+#define MT8135_PIN_99_MSDC4_RSTB__FUNC_MSDC4_RSTB (MTK_PIN_NO(99) | 1)
+#define MT8135_PIN_99_MSDC4_RSTB__FUNC_EINT130 (MTK_PIN_NO(99) | 2)
+#define MT8135_PIN_99_MSDC4_RSTB__FUNC_I2SIN_CK (MTK_PIN_NO(99) | 3)
+#define MT8135_PIN_99_MSDC4_RSTB__FUNC_CM2MCLK_2X (MTK_PIN_NO(99) | 4)
+#define MT8135_PIN_99_MSDC4_RSTB__FUNC_DAC_CK (MTK_PIN_NO(99) | 5)
+#define MT8135_PIN_99_MSDC4_RSTB__FUNC_PCM1_CK (MTK_PIN_NO(99) | 6)
+#define MT8135_PIN_99_MSDC4_RSTB__FUNC_LSA0_1X (MTK_PIN_NO(99) | 7)
+
+#define MT8135_PIN_100_SDA0__FUNC_GPIO100 (MTK_PIN_NO(100) | 0)
+#define MT8135_PIN_100_SDA0__FUNC_SDA0 (MTK_PIN_NO(100) | 1)
+#define MT8135_PIN_100_SDA0__FUNC_EINT91 (MTK_PIN_NO(100) | 2)
+#define MT8135_PIN_100_SDA0__FUNC_CLKM1 (MTK_PIN_NO(100) | 3)
+#define MT8135_PIN_100_SDA0__FUNC_PWM1 (MTK_PIN_NO(100) | 4)
+#define MT8135_PIN_100_SDA0__FUNC_A_FUNC_DIN_15 (MTK_PIN_NO(100) | 7)
+
+#define MT8135_PIN_101_SCL0__FUNC_GPIO101 (MTK_PIN_NO(101) | 0)
+#define MT8135_PIN_101_SCL0__FUNC_SCL0 (MTK_PIN_NO(101) | 1)
+#define MT8135_PIN_101_SCL0__FUNC_EINT90 (MTK_PIN_NO(101) | 2)
+#define MT8135_PIN_101_SCL0__FUNC_CLKM0 (MTK_PIN_NO(101) | 3)
+#define MT8135_PIN_101_SCL0__FUNC_DISP_PWM (MTK_PIN_NO(101) | 4)
+#define MT8135_PIN_101_SCL0__FUNC_A_FUNC_DIN_16 (MTK_PIN_NO(101) | 7)
+
+#define MT8135_PIN_102_EINT10_AUXIN2__FUNC_GPIO102 (MTK_PIN_NO(102) | 0)
+#define MT8135_PIN_102_EINT10_AUXIN2__FUNC_EINT10 (MTK_PIN_NO(102) | 1)
+#define MT8135_PIN_102_EINT10_AUXIN2__FUNC_USB_TEST_IO_16 (MTK_PIN_NO(102) | 5)
+#define MT8135_PIN_102_EINT10_AUXIN2__FUNC_TESTB_OUT16 (MTK_PIN_NO(102) | 6)
+#define MT8135_PIN_102_EINT10_AUXIN2__FUNC_A_FUNC_DIN_17 (MTK_PIN_NO(102) | 7)
+
+#define MT8135_PIN_103_EINT11_AUXIN3__FUNC_GPIO103 (MTK_PIN_NO(103) | 0)
+#define MT8135_PIN_103_EINT11_AUXIN3__FUNC_EINT11 (MTK_PIN_NO(103) | 1)
+#define MT8135_PIN_103_EINT11_AUXIN3__FUNC_USB_TEST_IO_17 (MTK_PIN_NO(103) | 5)
+#define MT8135_PIN_103_EINT11_AUXIN3__FUNC_TESTB_OUT17 (MTK_PIN_NO(103) | 6)
+#define MT8135_PIN_103_EINT11_AUXIN3__FUNC_A_FUNC_DIN_18 (MTK_PIN_NO(103) | 7)
+
+#define MT8135_PIN_104_EINT16_AUXIN4__FUNC_GPIO104 (MTK_PIN_NO(104) | 0)
+#define MT8135_PIN_104_EINT16_AUXIN4__FUNC_EINT16 (MTK_PIN_NO(104) | 1)
+#define MT8135_PIN_104_EINT16_AUXIN4__FUNC_USB_TEST_IO_18 (MTK_PIN_NO(104) | 5)
+#define MT8135_PIN_104_EINT16_AUXIN4__FUNC_TESTB_OUT18 (MTK_PIN_NO(104) | 6)
+#define MT8135_PIN_104_EINT16_AUXIN4__FUNC_A_FUNC_DIN_19 (MTK_PIN_NO(104) | 7)
+
+#define MT8135_PIN_105_I2S_CLK__FUNC_GPIO105 (MTK_PIN_NO(105) | 0)
+#define MT8135_PIN_105_I2S_CLK__FUNC_I2SIN_CK (MTK_PIN_NO(105) | 1)
+#define MT8135_PIN_105_I2S_CLK__FUNC_EINT10 (MTK_PIN_NO(105) | 2)
+#define MT8135_PIN_105_I2S_CLK__FUNC_DAC_CK (MTK_PIN_NO(105) | 3)
+#define MT8135_PIN_105_I2S_CLK__FUNC_PCM1_CK (MTK_PIN_NO(105) | 4)
+#define MT8135_PIN_105_I2S_CLK__FUNC_USB_TEST_IO_19 (MTK_PIN_NO(105) | 5)
+#define MT8135_PIN_105_I2S_CLK__FUNC_TESTB_OUT19 (MTK_PIN_NO(105) | 6)
+#define MT8135_PIN_105_I2S_CLK__FUNC_A_FUNC_DIN_20 (MTK_PIN_NO(105) | 7)
+
+#define MT8135_PIN_106_I2S_WS__FUNC_GPIO106 (MTK_PIN_NO(106) | 0)
+#define MT8135_PIN_106_I2S_WS__FUNC_I2SIN_WS (MTK_PIN_NO(106) | 1)
+#define MT8135_PIN_106_I2S_WS__FUNC_EINT13 (MTK_PIN_NO(106) | 2)
+#define MT8135_PIN_106_I2S_WS__FUNC_DAC_WS (MTK_PIN_NO(106) | 3)
+#define MT8135_PIN_106_I2S_WS__FUNC_PCM1_WS (MTK_PIN_NO(106) | 4)
+#define MT8135_PIN_106_I2S_WS__FUNC_USB_TEST_IO_20 (MTK_PIN_NO(106) | 5)
+#define MT8135_PIN_106_I2S_WS__FUNC_TESTB_OUT20 (MTK_PIN_NO(106) | 6)
+#define MT8135_PIN_106_I2S_WS__FUNC_A_FUNC_DIN_21 (MTK_PIN_NO(106) | 7)
+
+#define MT8135_PIN_107_I2S_DATA_IN__FUNC_GPIO107 (MTK_PIN_NO(107) | 0)
+#define MT8135_PIN_107_I2S_DATA_IN__FUNC_I2SIN_DAT (MTK_PIN_NO(107) | 1)
+#define MT8135_PIN_107_I2S_DATA_IN__FUNC_EINT11 (MTK_PIN_NO(107) | 2)
+#define MT8135_PIN_107_I2S_DATA_IN__FUNC_PCM1_DI (MTK_PIN_NO(107) | 4)
+#define MT8135_PIN_107_I2S_DATA_IN__FUNC_USB_TEST_IO_21 (MTK_PIN_NO(107) | 5)
+#define MT8135_PIN_107_I2S_DATA_IN__FUNC_TESTB_OUT22 (MTK_PIN_NO(107) | 6)
+#define MT8135_PIN_107_I2S_DATA_IN__FUNC_A_FUNC_DIN_22 (MTK_PIN_NO(107) | 7)
+
+#define MT8135_PIN_108_I2S_DATA_OUT__FUNC_GPIO108 (MTK_PIN_NO(108) | 0)
+#define MT8135_PIN_108_I2S_DATA_OUT__FUNC_I2SOUT_DAT (MTK_PIN_NO(108) | 1)
+#define MT8135_PIN_108_I2S_DATA_OUT__FUNC_EINT12 (MTK_PIN_NO(108) | 2)
+#define MT8135_PIN_108_I2S_DATA_OUT__FUNC_DAC_DAT_OUT (MTK_PIN_NO(108) | 3)
+#define MT8135_PIN_108_I2S_DATA_OUT__FUNC_PCM1_DO (MTK_PIN_NO(108) | 4)
+#define MT8135_PIN_108_I2S_DATA_OUT__FUNC_USB_TEST_IO_22 (MTK_PIN_NO(108) | 5)
+#define MT8135_PIN_108_I2S_DATA_OUT__FUNC_TESTB_OUT23 (MTK_PIN_NO(108) | 6)
+#define MT8135_PIN_108_I2S_DATA_OUT__FUNC_A_FUNC_DIN_23 (MTK_PIN_NO(108) | 7)
+
+#define MT8135_PIN_109_EINT5__FUNC_GPIO109 (MTK_PIN_NO(109) | 0)
+#define MT8135_PIN_109_EINT5__FUNC_EINT5 (MTK_PIN_NO(109) | 1)
+#define MT8135_PIN_109_EINT5__FUNC_PWM5 (MTK_PIN_NO(109) | 2)
+#define MT8135_PIN_109_EINT5__FUNC_CLKM3 (MTK_PIN_NO(109) | 3)
+#define MT8135_PIN_109_EINT5__FUNC_GPU_JTRSTB (MTK_PIN_NO(109) | 4)
+#define MT8135_PIN_109_EINT5__FUNC_USB_TEST_IO_23 (MTK_PIN_NO(109) | 5)
+#define MT8135_PIN_109_EINT5__FUNC_TESTB_OUT26 (MTK_PIN_NO(109) | 6)
+#define MT8135_PIN_109_EINT5__FUNC_A_FUNC_DIN_24 (MTK_PIN_NO(109) | 7)
+
+#define MT8135_PIN_110_EINT6__FUNC_GPIO110 (MTK_PIN_NO(110) | 0)
+#define MT8135_PIN_110_EINT6__FUNC_EINT6 (MTK_PIN_NO(110) | 1)
+#define MT8135_PIN_110_EINT6__FUNC_PWM6 (MTK_PIN_NO(110) | 2)
+#define MT8135_PIN_110_EINT6__FUNC_CLKM4 (MTK_PIN_NO(110) | 3)
+#define MT8135_PIN_110_EINT6__FUNC_GPU_JTMS (MTK_PIN_NO(110) | 4)
+#define MT8135_PIN_110_EINT6__FUNC_USB_TEST_IO_24 (MTK_PIN_NO(110) | 5)
+#define MT8135_PIN_110_EINT6__FUNC_TESTB_OUT27 (MTK_PIN_NO(110) | 6)
+#define MT8135_PIN_110_EINT6__FUNC_A_FUNC_DIN_25 (MTK_PIN_NO(110) | 7)
+
+#define MT8135_PIN_111_EINT7__FUNC_GPIO111 (MTK_PIN_NO(111) | 0)
+#define MT8135_PIN_111_EINT7__FUNC_EINT7 (MTK_PIN_NO(111) | 1)
+#define MT8135_PIN_111_EINT7__FUNC_PWM7 (MTK_PIN_NO(111) | 2)
+#define MT8135_PIN_111_EINT7__FUNC_CLKM5 (MTK_PIN_NO(111) | 3)
+#define MT8135_PIN_111_EINT7__FUNC_GPU_JTDO (MTK_PIN_NO(111) | 4)
+#define MT8135_PIN_111_EINT7__FUNC_USB_TEST_IO_25 (MTK_PIN_NO(111) | 5)
+#define MT8135_PIN_111_EINT7__FUNC_TESTB_OUT28 (MTK_PIN_NO(111) | 6)
+#define MT8135_PIN_111_EINT7__FUNC_A_FUNC_DIN_26 (MTK_PIN_NO(111) | 7)
+
+#define MT8135_PIN_112_EINT8__FUNC_GPIO112 (MTK_PIN_NO(112) | 0)
+#define MT8135_PIN_112_EINT8__FUNC_EINT8 (MTK_PIN_NO(112) | 1)
+#define MT8135_PIN_112_EINT8__FUNC_DISP_PWM (MTK_PIN_NO(112) | 2)
+#define MT8135_PIN_112_EINT8__FUNC_CLKM6 (MTK_PIN_NO(112) | 3)
+#define MT8135_PIN_112_EINT8__FUNC_GPU_JTDI (MTK_PIN_NO(112) | 4)
+#define MT8135_PIN_112_EINT8__FUNC_USB_TEST_IO_26 (MTK_PIN_NO(112) | 5)
+#define MT8135_PIN_112_EINT8__FUNC_TESTB_OUT29 (MTK_PIN_NO(112) | 6)
+#define MT8135_PIN_112_EINT8__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(112) | 7)
+
+#define MT8135_PIN_113_EINT9__FUNC_GPIO113 (MTK_PIN_NO(113) | 0)
+#define MT8135_PIN_113_EINT9__FUNC_EINT9 (MTK_PIN_NO(113) | 1)
+#define MT8135_PIN_113_EINT9__FUNC_GPU_JTCK (MTK_PIN_NO(113) | 4)
+#define MT8135_PIN_113_EINT9__FUNC_USB_DRVVBUS (MTK_PIN_NO(113) | 5)
+#define MT8135_PIN_113_EINT9__FUNC_TESTB_OUT30 (MTK_PIN_NO(113) | 6)
+#define MT8135_PIN_113_EINT9__FUNC_A_FUNC_DIN_27 (MTK_PIN_NO(113) | 7)
+
+#define MT8135_PIN_114_LPCE1B__FUNC_GPIO114 (MTK_PIN_NO(114) | 0)
+#define MT8135_PIN_114_LPCE1B__FUNC_LPCE1B (MTK_PIN_NO(114) | 1)
+#define MT8135_PIN_114_LPCE1B__FUNC_EINT127 (MTK_PIN_NO(114) | 2)
+#define MT8135_PIN_114_LPCE1B__FUNC_PWM2 (MTK_PIN_NO(114) | 5)
+#define MT8135_PIN_114_LPCE1B__FUNC_TESTB_OUT14 (MTK_PIN_NO(114) | 6)
+#define MT8135_PIN_114_LPCE1B__FUNC_A_FUNC_DIN_28 (MTK_PIN_NO(114) | 7)
+
+#define MT8135_PIN_115_LPCE0B__FUNC_GPIO115 (MTK_PIN_NO(115) | 0)
+#define MT8135_PIN_115_LPCE0B__FUNC_LPCE0B (MTK_PIN_NO(115) | 1)
+#define MT8135_PIN_115_LPCE0B__FUNC_EINT126 (MTK_PIN_NO(115) | 2)
+#define MT8135_PIN_115_LPCE0B__FUNC_PWM1 (MTK_PIN_NO(115) | 5)
+#define MT8135_PIN_115_LPCE0B__FUNC_TESTB_OUT15 (MTK_PIN_NO(115) | 6)
+#define MT8135_PIN_115_LPCE0B__FUNC_A_FUNC_DIN_29 (MTK_PIN_NO(115) | 7)
+
+#define MT8135_PIN_116_DISP_PWM__FUNC_GPIO116 (MTK_PIN_NO(116) | 0)
+#define MT8135_PIN_116_DISP_PWM__FUNC_DISP_PWM (MTK_PIN_NO(116) | 1)
+#define MT8135_PIN_116_DISP_PWM__FUNC_EINT77 (MTK_PIN_NO(116) | 2)
+#define MT8135_PIN_116_DISP_PWM__FUNC_LSDI (MTK_PIN_NO(116) | 3)
+#define MT8135_PIN_116_DISP_PWM__FUNC_PWM1 (MTK_PIN_NO(116) | 4)
+#define MT8135_PIN_116_DISP_PWM__FUNC_PWM2 (MTK_PIN_NO(116) | 5)
+#define MT8135_PIN_116_DISP_PWM__FUNC_PWM3 (MTK_PIN_NO(116) | 7)
+
+#define MT8135_PIN_117_EINT1__FUNC_GPIO117 (MTK_PIN_NO(117) | 0)
+#define MT8135_PIN_117_EINT1__FUNC_EINT1 (MTK_PIN_NO(117) | 1)
+#define MT8135_PIN_117_EINT1__FUNC_PWM2 (MTK_PIN_NO(117) | 2)
+#define MT8135_PIN_117_EINT1__FUNC_CLKM1 (MTK_PIN_NO(117) | 3)
+#define MT8135_PIN_117_EINT1__FUNC_USB_TEST_IO_13 (MTK_PIN_NO(117) | 5)
+#define MT8135_PIN_117_EINT1__FUNC_USB_SDA (MTK_PIN_NO(117) | 7)
+
+#define MT8135_PIN_118_EINT2__FUNC_GPIO118 (MTK_PIN_NO(118) | 0)
+#define MT8135_PIN_118_EINT2__FUNC_EINT2 (MTK_PIN_NO(118) | 1)
+#define MT8135_PIN_118_EINT2__FUNC_PWM3 (MTK_PIN_NO(118) | 2)
+#define MT8135_PIN_118_EINT2__FUNC_CLKM2 (MTK_PIN_NO(118) | 3)
+#define MT8135_PIN_118_EINT2__FUNC_USB_TEST_IO_14 (MTK_PIN_NO(118) | 5)
+#define MT8135_PIN_118_EINT2__FUNC_SRCLKENAI2 (MTK_PIN_NO(118) | 6)
+#define MT8135_PIN_118_EINT2__FUNC_A_FUNC_DIN_30 (MTK_PIN_NO(118) | 7)
+
+#define MT8135_PIN_119_EINT3__FUNC_GPIO119 (MTK_PIN_NO(119) | 0)
+#define MT8135_PIN_119_EINT3__FUNC_EINT3 (MTK_PIN_NO(119) | 1)
+#define MT8135_PIN_119_EINT3__FUNC_USB_TEST_IO_15 (MTK_PIN_NO(119) | 5)
+#define MT8135_PIN_119_EINT3__FUNC_SRCLKENAI1 (MTK_PIN_NO(119) | 6)
+#define MT8135_PIN_119_EINT3__FUNC_EXT_26M_CK (MTK_PIN_NO(119) | 7)
+
+#define MT8135_PIN_120_EINT4__FUNC_GPIO120 (MTK_PIN_NO(120) | 0)
+#define MT8135_PIN_120_EINT4__FUNC_EINT4 (MTK_PIN_NO(120) | 1)
+#define MT8135_PIN_120_EINT4__FUNC_PWM4 (MTK_PIN_NO(120) | 2)
+#define MT8135_PIN_120_EINT4__FUNC_USB_DRVVBUS (MTK_PIN_NO(120) | 5)
+#define MT8135_PIN_120_EINT4__FUNC_A_FUNC_DIN_31 (MTK_PIN_NO(120) | 7)
+
+#define MT8135_PIN_121_DPIDE__FUNC_GPIO121 (MTK_PIN_NO(121) | 0)
+#define MT8135_PIN_121_DPIDE__FUNC_DPI0_DE (MTK_PIN_NO(121) | 1)
+#define MT8135_PIN_121_DPIDE__FUNC_EINT100 (MTK_PIN_NO(121) | 2)
+#define MT8135_PIN_121_DPIDE__FUNC_I2SOUT_DAT (MTK_PIN_NO(121) | 3)
+#define MT8135_PIN_121_DPIDE__FUNC_DAC_DAT_OUT (MTK_PIN_NO(121) | 4)
+#define MT8135_PIN_121_DPIDE__FUNC_PCM1_DO (MTK_PIN_NO(121) | 5)
+#define MT8135_PIN_121_DPIDE__FUNC_IRDA_TXD (MTK_PIN_NO(121) | 6)
+
+#define MT8135_PIN_122_DPICK__FUNC_GPIO122 (MTK_PIN_NO(122) | 0)
+#define MT8135_PIN_122_DPICK__FUNC_DPI0_CK (MTK_PIN_NO(122) | 1)
+#define MT8135_PIN_122_DPICK__FUNC_EINT101 (MTK_PIN_NO(122) | 2)
+#define MT8135_PIN_122_DPICK__FUNC_I2SIN_DAT (MTK_PIN_NO(122) | 3)
+#define MT8135_PIN_122_DPICK__FUNC_PCM1_DI (MTK_PIN_NO(122) | 5)
+#define MT8135_PIN_122_DPICK__FUNC_IRDA_PDN (MTK_PIN_NO(122) | 6)
+
+#define MT8135_PIN_123_DPIG4__FUNC_GPIO123 (MTK_PIN_NO(123) | 0)
+#define MT8135_PIN_123_DPIG4__FUNC_DPI0_G4 (MTK_PIN_NO(123) | 1)
+#define MT8135_PIN_123_DPIG4__FUNC_EINT114 (MTK_PIN_NO(123) | 2)
+#define MT8135_PIN_123_DPIG4__FUNC_CM2DAT_2X_0 (MTK_PIN_NO(123) | 4)
+#define MT8135_PIN_123_DPIG4__FUNC_DSP2_ID (MTK_PIN_NO(123) | 5)
+
+#define MT8135_PIN_124_DPIG5__FUNC_GPIO124 (MTK_PIN_NO(124) | 0)
+#define MT8135_PIN_124_DPIG5__FUNC_DPI0_G5 (MTK_PIN_NO(124) | 1)
+#define MT8135_PIN_124_DPIG5__FUNC_EINT115 (MTK_PIN_NO(124) | 2)
+#define MT8135_PIN_124_DPIG5__FUNC_CM2DAT_2X_1 (MTK_PIN_NO(124) | 4)
+#define MT8135_PIN_124_DPIG5__FUNC_DSP2_ICK (MTK_PIN_NO(124) | 5)
+
+#define MT8135_PIN_125_DPIR3__FUNC_GPIO125 (MTK_PIN_NO(125) | 0)
+#define MT8135_PIN_125_DPIR3__FUNC_DPI0_R3 (MTK_PIN_NO(125) | 1)
+#define MT8135_PIN_125_DPIR3__FUNC_EINT121 (MTK_PIN_NO(125) | 2)
+#define MT8135_PIN_125_DPIR3__FUNC_CM2DAT_2X_7 (MTK_PIN_NO(125) | 4)
+
+#define MT8135_PIN_126_DPIG1__FUNC_GPIO126 (MTK_PIN_NO(126) | 0)
+#define MT8135_PIN_126_DPIG1__FUNC_DPI0_G1 (MTK_PIN_NO(126) | 1)
+#define MT8135_PIN_126_DPIG1__FUNC_EINT111 (MTK_PIN_NO(126) | 2)
+#define MT8135_PIN_126_DPIG1__FUNC_DSP1_ICK (MTK_PIN_NO(126) | 5)
+
+#define MT8135_PIN_127_DPIVSYNC__FUNC_GPIO127 (MTK_PIN_NO(127) | 0)
+#define MT8135_PIN_127_DPIVSYNC__FUNC_DPI0_VSYNC (MTK_PIN_NO(127) | 1)
+#define MT8135_PIN_127_DPIVSYNC__FUNC_EINT98 (MTK_PIN_NO(127) | 2)
+#define MT8135_PIN_127_DPIVSYNC__FUNC_I2SIN_CK (MTK_PIN_NO(127) | 3)
+#define MT8135_PIN_127_DPIVSYNC__FUNC_DAC_CK (MTK_PIN_NO(127) | 4)
+#define MT8135_PIN_127_DPIVSYNC__FUNC_PCM1_CK (MTK_PIN_NO(127) | 5)
+
+#define MT8135_PIN_128_DPIHSYNC__FUNC_GPIO128 (MTK_PIN_NO(128) | 0)
+#define MT8135_PIN_128_DPIHSYNC__FUNC_DPI0_HSYNC (MTK_PIN_NO(128) | 1)
+#define MT8135_PIN_128_DPIHSYNC__FUNC_EINT99 (MTK_PIN_NO(128) | 2)
+#define MT8135_PIN_128_DPIHSYNC__FUNC_I2SIN_WS (MTK_PIN_NO(128) | 3)
+#define MT8135_PIN_128_DPIHSYNC__FUNC_DAC_WS (MTK_PIN_NO(128) | 4)
+#define MT8135_PIN_128_DPIHSYNC__FUNC_PCM1_WS (MTK_PIN_NO(128) | 5)
+#define MT8135_PIN_128_DPIHSYNC__FUNC_IRDA_RXD (MTK_PIN_NO(128) | 6)
+
+#define MT8135_PIN_129_DPIB0__FUNC_GPIO129 (MTK_PIN_NO(129) | 0)
+#define MT8135_PIN_129_DPIB0__FUNC_DPI0_B0 (MTK_PIN_NO(129) | 1)
+#define MT8135_PIN_129_DPIB0__FUNC_EINT102 (MTK_PIN_NO(129) | 2)
+#define MT8135_PIN_129_DPIB0__FUNC_SCL0 (MTK_PIN_NO(129) | 4)
+#define MT8135_PIN_129_DPIB0__FUNC_DISP_PWM (MTK_PIN_NO(129) | 5)
+
+#define MT8135_PIN_130_DPIB1__FUNC_GPIO130 (MTK_PIN_NO(130) | 0)
+#define MT8135_PIN_130_DPIB1__FUNC_DPI0_B1 (MTK_PIN_NO(130) | 1)
+#define MT8135_PIN_130_DPIB1__FUNC_EINT103 (MTK_PIN_NO(130) | 2)
+#define MT8135_PIN_130_DPIB1__FUNC_CLKM0 (MTK_PIN_NO(130) | 3)
+#define MT8135_PIN_130_DPIB1__FUNC_SDA0 (MTK_PIN_NO(130) | 4)
+#define MT8135_PIN_130_DPIB1__FUNC_PWM1 (MTK_PIN_NO(130) | 5)
+
+#define MT8135_PIN_131_DPIB2__FUNC_GPIO131 (MTK_PIN_NO(131) | 0)
+#define MT8135_PIN_131_DPIB2__FUNC_DPI0_B2 (MTK_PIN_NO(131) | 1)
+#define MT8135_PIN_131_DPIB2__FUNC_EINT104 (MTK_PIN_NO(131) | 2)
+#define MT8135_PIN_131_DPIB2__FUNC_CLKM1 (MTK_PIN_NO(131) | 3)
+#define MT8135_PIN_131_DPIB2__FUNC_SCL1 (MTK_PIN_NO(131) | 4)
+#define MT8135_PIN_131_DPIB2__FUNC_PWM2 (MTK_PIN_NO(131) | 5)
+
+#define MT8135_PIN_132_DPIB3__FUNC_GPIO132 (MTK_PIN_NO(132) | 0)
+#define MT8135_PIN_132_DPIB3__FUNC_DPI0_B3 (MTK_PIN_NO(132) | 1)
+#define MT8135_PIN_132_DPIB3__FUNC_EINT105 (MTK_PIN_NO(132) | 2)
+#define MT8135_PIN_132_DPIB3__FUNC_CLKM2 (MTK_PIN_NO(132) | 3)
+#define MT8135_PIN_132_DPIB3__FUNC_SDA1 (MTK_PIN_NO(132) | 4)
+#define MT8135_PIN_132_DPIB3__FUNC_PWM3 (MTK_PIN_NO(132) | 5)
+
+#define MT8135_PIN_133_DPIB4__FUNC_GPIO133 (MTK_PIN_NO(133) | 0)
+#define MT8135_PIN_133_DPIB4__FUNC_DPI0_B4 (MTK_PIN_NO(133) | 1)
+#define MT8135_PIN_133_DPIB4__FUNC_EINT106 (MTK_PIN_NO(133) | 2)
+#define MT8135_PIN_133_DPIB4__FUNC_CLKM3 (MTK_PIN_NO(133) | 3)
+#define MT8135_PIN_133_DPIB4__FUNC_SCL2 (MTK_PIN_NO(133) | 4)
+#define MT8135_PIN_133_DPIB4__FUNC_PWM4 (MTK_PIN_NO(133) | 5)
+
+#define MT8135_PIN_134_DPIB5__FUNC_GPIO134 (MTK_PIN_NO(134) | 0)
+#define MT8135_PIN_134_DPIB5__FUNC_DPI0_B5 (MTK_PIN_NO(134) | 1)
+#define MT8135_PIN_134_DPIB5__FUNC_EINT107 (MTK_PIN_NO(134) | 2)
+#define MT8135_PIN_134_DPIB5__FUNC_CLKM4 (MTK_PIN_NO(134) | 3)
+#define MT8135_PIN_134_DPIB5__FUNC_SDA2 (MTK_PIN_NO(134) | 4)
+#define MT8135_PIN_134_DPIB5__FUNC_PWM5 (MTK_PIN_NO(134) | 5)
+
+#define MT8135_PIN_135_DPIB6__FUNC_GPIO135 (MTK_PIN_NO(135) | 0)
+#define MT8135_PIN_135_DPIB6__FUNC_DPI0_B6 (MTK_PIN_NO(135) | 1)
+#define MT8135_PIN_135_DPIB6__FUNC_EINT108 (MTK_PIN_NO(135) | 2)
+#define MT8135_PIN_135_DPIB6__FUNC_CLKM5 (MTK_PIN_NO(135) | 3)
+#define MT8135_PIN_135_DPIB6__FUNC_SCL3 (MTK_PIN_NO(135) | 4)
+#define MT8135_PIN_135_DPIB6__FUNC_PWM6 (MTK_PIN_NO(135) | 5)
+
+#define MT8135_PIN_136_DPIB7__FUNC_GPIO136 (MTK_PIN_NO(136) | 0)
+#define MT8135_PIN_136_DPIB7__FUNC_DPI0_B7 (MTK_PIN_NO(136) | 1)
+#define MT8135_PIN_136_DPIB7__FUNC_EINT109 (MTK_PIN_NO(136) | 2)
+#define MT8135_PIN_136_DPIB7__FUNC_CLKM6 (MTK_PIN_NO(136) | 3)
+#define MT8135_PIN_136_DPIB7__FUNC_SDA3 (MTK_PIN_NO(136) | 4)
+#define MT8135_PIN_136_DPIB7__FUNC_PWM7 (MTK_PIN_NO(136) | 5)
+
+#define MT8135_PIN_137_DPIG0__FUNC_GPIO137 (MTK_PIN_NO(137) | 0)
+#define MT8135_PIN_137_DPIG0__FUNC_DPI0_G0 (MTK_PIN_NO(137) | 1)
+#define MT8135_PIN_137_DPIG0__FUNC_EINT110 (MTK_PIN_NO(137) | 2)
+#define MT8135_PIN_137_DPIG0__FUNC_DSP1_ID (MTK_PIN_NO(137) | 5)
+
+#define MT8135_PIN_138_DPIG2__FUNC_GPIO138 (MTK_PIN_NO(138) | 0)
+#define MT8135_PIN_138_DPIG2__FUNC_DPI0_G2 (MTK_PIN_NO(138) | 1)
+#define MT8135_PIN_138_DPIG2__FUNC_EINT112 (MTK_PIN_NO(138) | 2)
+#define MT8135_PIN_138_DPIG2__FUNC_DSP1_IMS (MTK_PIN_NO(138) | 5)
+
+#define MT8135_PIN_139_DPIG3__FUNC_GPIO139 (MTK_PIN_NO(139) | 0)
+#define MT8135_PIN_139_DPIG3__FUNC_DPI0_G3 (MTK_PIN_NO(139) | 1)
+#define MT8135_PIN_139_DPIG3__FUNC_EINT113 (MTK_PIN_NO(139) | 2)
+#define MT8135_PIN_139_DPIG3__FUNC_DSP2_IMS (MTK_PIN_NO(139) | 5)
+
+#define MT8135_PIN_140_DPIG6__FUNC_GPIO140 (MTK_PIN_NO(140) | 0)
+#define MT8135_PIN_140_DPIG6__FUNC_DPI0_G6 (MTK_PIN_NO(140) | 1)
+#define MT8135_PIN_140_DPIG6__FUNC_EINT116 (MTK_PIN_NO(140) | 2)
+#define MT8135_PIN_140_DPIG6__FUNC_CM2DAT_2X_2 (MTK_PIN_NO(140) | 4)
+
+#define MT8135_PIN_141_DPIG7__FUNC_GPIO141 (MTK_PIN_NO(141) | 0)
+#define MT8135_PIN_141_DPIG7__FUNC_DPI0_G7 (MTK_PIN_NO(141) | 1)
+#define MT8135_PIN_141_DPIG7__FUNC_EINT117 (MTK_PIN_NO(141) | 2)
+#define MT8135_PIN_141_DPIG7__FUNC_CM2DAT_2X_3 (MTK_PIN_NO(141) | 4)
+
+#define MT8135_PIN_142_DPIR0__FUNC_GPIO142 (MTK_PIN_NO(142) | 0)
+#define MT8135_PIN_142_DPIR0__FUNC_DPI0_R0 (MTK_PIN_NO(142) | 1)
+#define MT8135_PIN_142_DPIR0__FUNC_EINT118 (MTK_PIN_NO(142) | 2)
+#define MT8135_PIN_142_DPIR0__FUNC_CM2DAT_2X_4 (MTK_PIN_NO(142) | 4)
+
+#define MT8135_PIN_143_DPIR1__FUNC_GPIO143 (MTK_PIN_NO(143) | 0)
+#define MT8135_PIN_143_DPIR1__FUNC_DPI0_R1 (MTK_PIN_NO(143) | 1)
+#define MT8135_PIN_143_DPIR1__FUNC_EINT119 (MTK_PIN_NO(143) | 2)
+#define MT8135_PIN_143_DPIR1__FUNC_CM2DAT_2X_5 (MTK_PIN_NO(143) | 4)
+
+#define MT8135_PIN_144_DPIR2__FUNC_GPIO144 (MTK_PIN_NO(144) | 0)
+#define MT8135_PIN_144_DPIR2__FUNC_DPI0_R2 (MTK_PIN_NO(144) | 1)
+#define MT8135_PIN_144_DPIR2__FUNC_EINT120 (MTK_PIN_NO(144) | 2)
+#define MT8135_PIN_144_DPIR2__FUNC_CM2DAT_2X_6 (MTK_PIN_NO(144) | 4)
+
+#define MT8135_PIN_145_DPIR4__FUNC_GPIO145 (MTK_PIN_NO(145) | 0)
+#define MT8135_PIN_145_DPIR4__FUNC_DPI0_R4 (MTK_PIN_NO(145) | 1)
+#define MT8135_PIN_145_DPIR4__FUNC_EINT122 (MTK_PIN_NO(145) | 2)
+#define MT8135_PIN_145_DPIR4__FUNC_CM2DAT_2X_8 (MTK_PIN_NO(145) | 4)
+
+#define MT8135_PIN_146_DPIR5__FUNC_GPIO146 (MTK_PIN_NO(146) | 0)
+#define MT8135_PIN_146_DPIR5__FUNC_DPI0_R5 (MTK_PIN_NO(146) | 1)
+#define MT8135_PIN_146_DPIR5__FUNC_EINT123 (MTK_PIN_NO(146) | 2)
+#define MT8135_PIN_146_DPIR5__FUNC_CM2DAT_2X_9 (MTK_PIN_NO(146) | 4)
+
+#define MT8135_PIN_147_DPIR6__FUNC_GPIO147 (MTK_PIN_NO(147) | 0)
+#define MT8135_PIN_147_DPIR6__FUNC_DPI0_R6 (MTK_PIN_NO(147) | 1)
+#define MT8135_PIN_147_DPIR6__FUNC_EINT124 (MTK_PIN_NO(147) | 2)
+#define MT8135_PIN_147_DPIR6__FUNC_CM2VSYNC_2X (MTK_PIN_NO(147) | 4)
+
+#define MT8135_PIN_148_DPIR7__FUNC_GPIO148 (MTK_PIN_NO(148) | 0)
+#define MT8135_PIN_148_DPIR7__FUNC_DPI0_R7 (MTK_PIN_NO(148) | 1)
+#define MT8135_PIN_148_DPIR7__FUNC_EINT125 (MTK_PIN_NO(148) | 2)
+#define MT8135_PIN_148_DPIR7__FUNC_CM2HSYNC_2X (MTK_PIN_NO(148) | 4)
+
+#define MT8135_PIN_149_TDN3__FUNC_GPIO149 (MTK_PIN_NO(149) | 0)
+#define MT8135_PIN_149_TDN3__FUNC_EINT36 (MTK_PIN_NO(149) | 2)
+
+#define MT8135_PIN_150_TDP3__FUNC_GPIO150 (MTK_PIN_NO(150) | 0)
+#define MT8135_PIN_150_TDP3__FUNC_EINT35 (MTK_PIN_NO(150) | 2)
+
+#define MT8135_PIN_151_TDN2__FUNC_GPIO151 (MTK_PIN_NO(151) | 0)
+#define MT8135_PIN_151_TDN2__FUNC_EINT169 (MTK_PIN_NO(151) | 2)
+
+#define MT8135_PIN_152_TDP2__FUNC_GPIO152 (MTK_PIN_NO(152) | 0)
+#define MT8135_PIN_152_TDP2__FUNC_EINT168 (MTK_PIN_NO(152) | 2)
+
+#define MT8135_PIN_153_TCN__FUNC_GPIO153 (MTK_PIN_NO(153) | 0)
+#define MT8135_PIN_153_TCN__FUNC_EINT163 (MTK_PIN_NO(153) | 2)
+
+#define MT8135_PIN_154_TCP__FUNC_GPIO154 (MTK_PIN_NO(154) | 0)
+#define MT8135_PIN_154_TCP__FUNC_EINT162 (MTK_PIN_NO(154) | 2)
+
+#define MT8135_PIN_155_TDN1__FUNC_GPIO155 (MTK_PIN_NO(155) | 0)
+#define MT8135_PIN_155_TDN1__FUNC_EINT167 (MTK_PIN_NO(155) | 2)
+
+#define MT8135_PIN_156_TDP1__FUNC_GPIO156 (MTK_PIN_NO(156) | 0)
+#define MT8135_PIN_156_TDP1__FUNC_EINT166 (MTK_PIN_NO(156) | 2)
+
+#define MT8135_PIN_157_TDN0__FUNC_GPIO157 (MTK_PIN_NO(157) | 0)
+#define MT8135_PIN_157_TDN0__FUNC_EINT165 (MTK_PIN_NO(157) | 2)
+
+#define MT8135_PIN_158_TDP0__FUNC_GPIO158 (MTK_PIN_NO(158) | 0)
+#define MT8135_PIN_158_TDP0__FUNC_EINT164 (MTK_PIN_NO(158) | 2)
+
+#define MT8135_PIN_159_RDN3__FUNC_GPIO159 (MTK_PIN_NO(159) | 0)
+#define MT8135_PIN_159_RDN3__FUNC_EINT18 (MTK_PIN_NO(159) | 2)
+
+#define MT8135_PIN_160_RDP3__FUNC_GPIO160 (MTK_PIN_NO(160) | 0)
+#define MT8135_PIN_160_RDP3__FUNC_EINT30 (MTK_PIN_NO(160) | 2)
+
+#define MT8135_PIN_161_RDN2__FUNC_GPIO161 (MTK_PIN_NO(161) | 0)
+#define MT8135_PIN_161_RDN2__FUNC_EINT31 (MTK_PIN_NO(161) | 2)
+
+#define MT8135_PIN_162_RDP2__FUNC_GPIO162 (MTK_PIN_NO(162) | 0)
+#define MT8135_PIN_162_RDP2__FUNC_EINT32 (MTK_PIN_NO(162) | 2)
+
+#define MT8135_PIN_163_RCN__FUNC_GPIO163 (MTK_PIN_NO(163) | 0)
+#define MT8135_PIN_163_RCN__FUNC_EINT33 (MTK_PIN_NO(163) | 2)
+
+#define MT8135_PIN_164_RCP__FUNC_GPIO164 (MTK_PIN_NO(164) | 0)
+#define MT8135_PIN_164_RCP__FUNC_EINT39 (MTK_PIN_NO(164) | 2)
+
+#define MT8135_PIN_165_RDN1__FUNC_GPIO165 (MTK_PIN_NO(165) | 0)
+
+#define MT8135_PIN_166_RDP1__FUNC_GPIO166 (MTK_PIN_NO(166) | 0)
+
+#define MT8135_PIN_167_RDN0__FUNC_GPIO167 (MTK_PIN_NO(167) | 0)
+
+#define MT8135_PIN_168_RDP0__FUNC_GPIO168 (MTK_PIN_NO(168) | 0)
+
+#define MT8135_PIN_169_RDN1_A__FUNC_GPIO169 (MTK_PIN_NO(169) | 0)
+#define MT8135_PIN_169_RDN1_A__FUNC_CMDAT6 (MTK_PIN_NO(169) | 1)
+#define MT8135_PIN_169_RDN1_A__FUNC_EINT175 (MTK_PIN_NO(169) | 2)
+
+#define MT8135_PIN_170_RDP1_A__FUNC_GPIO170 (MTK_PIN_NO(170) | 0)
+#define MT8135_PIN_170_RDP1_A__FUNC_CMDAT7 (MTK_PIN_NO(170) | 1)
+#define MT8135_PIN_170_RDP1_A__FUNC_EINT174 (MTK_PIN_NO(170) | 2)
+
+#define MT8135_PIN_171_RCN_A__FUNC_GPIO171 (MTK_PIN_NO(171) | 0)
+#define MT8135_PIN_171_RCN_A__FUNC_CMDAT8 (MTK_PIN_NO(171) | 1)
+#define MT8135_PIN_171_RCN_A__FUNC_EINT171 (MTK_PIN_NO(171) | 2)
+
+#define MT8135_PIN_172_RCP_A__FUNC_GPIO172 (MTK_PIN_NO(172) | 0)
+#define MT8135_PIN_172_RCP_A__FUNC_CMDAT9 (MTK_PIN_NO(172) | 1)
+#define MT8135_PIN_172_RCP_A__FUNC_EINT170 (MTK_PIN_NO(172) | 2)
+
+#define MT8135_PIN_173_RDN0_A__FUNC_GPIO173 (MTK_PIN_NO(173) | 0)
+#define MT8135_PIN_173_RDN0_A__FUNC_CMHSYNC (MTK_PIN_NO(173) | 1)
+#define MT8135_PIN_173_RDN0_A__FUNC_EINT173 (MTK_PIN_NO(173) | 2)
+
+#define MT8135_PIN_174_RDP0_A__FUNC_GPIO174 (MTK_PIN_NO(174) | 0)
+#define MT8135_PIN_174_RDP0_A__FUNC_CMVSYNC (MTK_PIN_NO(174) | 1)
+#define MT8135_PIN_174_RDP0_A__FUNC_EINT172 (MTK_PIN_NO(174) | 2)
+
+#define MT8135_PIN_175_RDN1_B__FUNC_GPIO175 (MTK_PIN_NO(175) | 0)
+#define MT8135_PIN_175_RDN1_B__FUNC_CMDAT2 (MTK_PIN_NO(175) | 1)
+#define MT8135_PIN_175_RDN1_B__FUNC_EINT181 (MTK_PIN_NO(175) | 2)
+#define MT8135_PIN_175_RDN1_B__FUNC_CMCSD2 (MTK_PIN_NO(175) | 3)
+
+#define MT8135_PIN_176_RDP1_B__FUNC_GPIO176 (MTK_PIN_NO(176) | 0)
+#define MT8135_PIN_176_RDP1_B__FUNC_CMDAT3 (MTK_PIN_NO(176) | 1)
+#define MT8135_PIN_176_RDP1_B__FUNC_EINT180 (MTK_PIN_NO(176) | 2)
+#define MT8135_PIN_176_RDP1_B__FUNC_CMCSD3 (MTK_PIN_NO(176) | 3)
+
+#define MT8135_PIN_177_RCN_B__FUNC_GPIO177 (MTK_PIN_NO(177) | 0)
+#define MT8135_PIN_177_RCN_B__FUNC_CMDAT4 (MTK_PIN_NO(177) | 1)
+#define MT8135_PIN_177_RCN_B__FUNC_EINT177 (MTK_PIN_NO(177) | 2)
+
+#define MT8135_PIN_178_RCP_B__FUNC_GPIO178 (MTK_PIN_NO(178) | 0)
+#define MT8135_PIN_178_RCP_B__FUNC_CMDAT5 (MTK_PIN_NO(178) | 1)
+#define MT8135_PIN_178_RCP_B__FUNC_EINT176 (MTK_PIN_NO(178) | 2)
+
+#define MT8135_PIN_179_RDN0_B__FUNC_GPIO179 (MTK_PIN_NO(179) | 0)
+#define MT8135_PIN_179_RDN0_B__FUNC_CMDAT0 (MTK_PIN_NO(179) | 1)
+#define MT8135_PIN_179_RDN0_B__FUNC_EINT179 (MTK_PIN_NO(179) | 2)
+#define MT8135_PIN_179_RDN0_B__FUNC_CMCSD0 (MTK_PIN_NO(179) | 3)
+
+#define MT8135_PIN_180_RDP0_B__FUNC_GPIO180 (MTK_PIN_NO(180) | 0)
+#define MT8135_PIN_180_RDP0_B__FUNC_CMDAT1 (MTK_PIN_NO(180) | 1)
+#define MT8135_PIN_180_RDP0_B__FUNC_EINT178 (MTK_PIN_NO(180) | 2)
+#define MT8135_PIN_180_RDP0_B__FUNC_CMCSD1 (MTK_PIN_NO(180) | 3)
+
+#define MT8135_PIN_181_CMPCLK__FUNC_GPIO181 (MTK_PIN_NO(181) | 0)
+#define MT8135_PIN_181_CMPCLK__FUNC_CMPCLK (MTK_PIN_NO(181) | 1)
+#define MT8135_PIN_181_CMPCLK__FUNC_EINT182 (MTK_PIN_NO(181) | 2)
+#define MT8135_PIN_181_CMPCLK__FUNC_CMCSK (MTK_PIN_NO(181) | 3)
+#define MT8135_PIN_181_CMPCLK__FUNC_CM2MCLK_4X (MTK_PIN_NO(181) | 4)
+#define MT8135_PIN_181_CMPCLK__FUNC_TS_AUXADC_SEL_3 (MTK_PIN_NO(181) | 5)
+#define MT8135_PIN_181_CMPCLK__FUNC_VENC_TEST_CK (MTK_PIN_NO(181) | 6)
+#define MT8135_PIN_181_CMPCLK__FUNC_TESTA_OUT27 (MTK_PIN_NO(181) | 7)
+
+#define MT8135_PIN_182_CMMCLK__FUNC_GPIO182 (MTK_PIN_NO(182) | 0)
+#define MT8135_PIN_182_CMMCLK__FUNC_CMMCLK (MTK_PIN_NO(182) | 1)
+#define MT8135_PIN_182_CMMCLK__FUNC_EINT183 (MTK_PIN_NO(182) | 2)
+#define MT8135_PIN_182_CMMCLK__FUNC_TS_AUXADC_SEL_2 (MTK_PIN_NO(182) | 5)
+#define MT8135_PIN_182_CMMCLK__FUNC_TESTA_OUT28 (MTK_PIN_NO(182) | 7)
+
+#define MT8135_PIN_183_CMRST__FUNC_GPIO183 (MTK_PIN_NO(183) | 0)
+#define MT8135_PIN_183_CMRST__FUNC_CMRST (MTK_PIN_NO(183) | 1)
+#define MT8135_PIN_183_CMRST__FUNC_EINT185 (MTK_PIN_NO(183) | 2)
+#define MT8135_PIN_183_CMRST__FUNC_TS_AUXADC_SEL_1 (MTK_PIN_NO(183) | 5)
+#define MT8135_PIN_183_CMRST__FUNC_TESTA_OUT30 (MTK_PIN_NO(183) | 7)
+
+#define MT8135_PIN_184_CMPDN__FUNC_GPIO184 (MTK_PIN_NO(184) | 0)
+#define MT8135_PIN_184_CMPDN__FUNC_CMPDN (MTK_PIN_NO(184) | 1)
+#define MT8135_PIN_184_CMPDN__FUNC_EINT184 (MTK_PIN_NO(184) | 2)
+#define MT8135_PIN_184_CMPDN__FUNC_TS_AUXADC_SEL_0 (MTK_PIN_NO(184) | 5)
+#define MT8135_PIN_184_CMPDN__FUNC_TESTA_OUT29 (MTK_PIN_NO(184) | 7)
+
+#define MT8135_PIN_185_CMFLASH__FUNC_GPIO185 (MTK_PIN_NO(185) | 0)
+#define MT8135_PIN_185_CMFLASH__FUNC_CMFLASH (MTK_PIN_NO(185) | 1)
+#define MT8135_PIN_185_CMFLASH__FUNC_EINT186 (MTK_PIN_NO(185) | 2)
+#define MT8135_PIN_185_CMFLASH__FUNC_CM2MCLK_3X (MTK_PIN_NO(185) | 3)
+#define MT8135_PIN_185_CMFLASH__FUNC_MFG_TEST_CK_1 (MTK_PIN_NO(185) | 6)
+#define MT8135_PIN_185_CMFLASH__FUNC_TESTA_OUT31 (MTK_PIN_NO(185) | 7)
+
+#define MT8135_PIN_186_MRG_I2S_PCM_CLK__FUNC_GPIO186 (MTK_PIN_NO(186) | 0)
+#define MT8135_PIN_186_MRG_I2S_PCM_CLK__FUNC_MRG_I2S_P_CLK (MTK_PIN_NO(186) | 1)
+#define MT8135_PIN_186_MRG_I2S_PCM_CLK__FUNC_EINT14 (MTK_PIN_NO(186) | 2)
+#define MT8135_PIN_186_MRG_I2S_PCM_CLK__FUNC_I2SIN_CK (MTK_PIN_NO(186) | 3)
+#define MT8135_PIN_186_MRG_I2S_PCM_CLK__FUNC_PCM0_CK (MTK_PIN_NO(186) | 4)
+#define MT8135_PIN_186_MRG_I2S_PCM_CLK__FUNC_DSP2_ICK (MTK_PIN_NO(186) | 5)
+#define MT8135_PIN_186_MRG_I2S_PCM_CLK__FUNC_IMG_TEST_CK (MTK_PIN_NO(186) | 6)
+#define MT8135_PIN_186_MRG_I2S_PCM_CLK__FUNC_USB_SCL (MTK_PIN_NO(186) | 7)
+
+#define MT8135_PIN_187_MRG_I2S_PCM_SYNC__FUNC_GPIO187 (MTK_PIN_NO(187) | 0)
+#define MT8135_PIN_187_MRG_I2S_PCM_SYNC__FUNC_MRG_I2S_SYNC (MTK_PIN_NO(187) | 1)
+#define MT8135_PIN_187_MRG_I2S_PCM_SYNC__FUNC_EINT16 (MTK_PIN_NO(187) | 2)
+#define MT8135_PIN_187_MRG_I2S_PCM_SYNC__FUNC_I2SIN_WS (MTK_PIN_NO(187) | 3)
+#define MT8135_PIN_187_MRG_I2S_PCM_SYNC__FUNC_PCM0_WS (MTK_PIN_NO(187) | 4)
+#define MT8135_PIN_187_MRG_I2S_PCM_SYNC__FUNC_DISP_TEST_CK (MTK_PIN_NO(187) | 6)
+
+#define MT8135_PIN_188_MRG_I2S_PCM_RX__FUNC_GPIO188 (MTK_PIN_NO(188) | 0)
+#define MT8135_PIN_188_MRG_I2S_PCM_RX__FUNC_MRG_I2S_PCM_RX (MTK_PIN_NO(188) | 1)
+#define MT8135_PIN_188_MRG_I2S_PCM_RX__FUNC_EINT15 (MTK_PIN_NO(188) | 2)
+#define MT8135_PIN_188_MRG_I2S_PCM_RX__FUNC_I2SIN_DAT (MTK_PIN_NO(188) | 3)
+#define MT8135_PIN_188_MRG_I2S_PCM_RX__FUNC_PCM0_DI (MTK_PIN_NO(188) | 4)
+#define MT8135_PIN_188_MRG_I2S_PCM_RX__FUNC_DSP2_ID (MTK_PIN_NO(188) | 5)
+#define MT8135_PIN_188_MRG_I2S_PCM_RX__FUNC_MFG_TEST_CK (MTK_PIN_NO(188) | 6)
+#define MT8135_PIN_188_MRG_I2S_PCM_RX__FUNC_USB_SDA (MTK_PIN_NO(188) | 7)
+
+#define MT8135_PIN_189_MRG_I2S_PCM_TX__FUNC_GPIO189 (MTK_PIN_NO(189) | 0)
+#define MT8135_PIN_189_MRG_I2S_PCM_TX__FUNC_MRG_I2S_PCM_TX (MTK_PIN_NO(189) | 1)
+#define MT8135_PIN_189_MRG_I2S_PCM_TX__FUNC_EINT17 (MTK_PIN_NO(189) | 2)
+#define MT8135_PIN_189_MRG_I2S_PCM_TX__FUNC_I2SOUT_DAT (MTK_PIN_NO(189) | 3)
+#define MT8135_PIN_189_MRG_I2S_PCM_TX__FUNC_PCM0_DO (MTK_PIN_NO(189) | 4)
+#define MT8135_PIN_189_MRG_I2S_PCM_TX__FUNC_VDEC_TEST_CK (MTK_PIN_NO(189) | 6)
+
+#define MT8135_PIN_190_SRCLKENAI__FUNC_GPIO190 (MTK_PIN_NO(190) | 0)
+#define MT8135_PIN_190_SRCLKENAI__FUNC_SRCLKENAI (MTK_PIN_NO(190) | 1)
+
+#define MT8135_PIN_191_URXD3__FUNC_GPIO191 (MTK_PIN_NO(191) | 0)
+#define MT8135_PIN_191_URXD3__FUNC_URXD3 (MTK_PIN_NO(191) | 1)
+#define MT8135_PIN_191_URXD3__FUNC_EINT87 (MTK_PIN_NO(191) | 2)
+#define MT8135_PIN_191_URXD3__FUNC_UTXD3 (MTK_PIN_NO(191) | 3)
+#define MT8135_PIN_191_URXD3__FUNC_TS_AUX_ST (MTK_PIN_NO(191) | 5)
+#define MT8135_PIN_191_URXD3__FUNC_PWM4 (MTK_PIN_NO(191) | 6)
+
+#define MT8135_PIN_192_UTXD3__FUNC_GPIO192 (MTK_PIN_NO(192) | 0)
+#define MT8135_PIN_192_UTXD3__FUNC_UTXD3 (MTK_PIN_NO(192) | 1)
+#define MT8135_PIN_192_UTXD3__FUNC_EINT86 (MTK_PIN_NO(192) | 2)
+#define MT8135_PIN_192_UTXD3__FUNC_URXD3 (MTK_PIN_NO(192) | 3)
+#define MT8135_PIN_192_UTXD3__FUNC_TS_AUX_CS_B (MTK_PIN_NO(192) | 5)
+#define MT8135_PIN_192_UTXD3__FUNC_PWM3 (MTK_PIN_NO(192) | 6)
+
+#define MT8135_PIN_193_SDA2__FUNC_GPIO193 (MTK_PIN_NO(193) | 0)
+#define MT8135_PIN_193_SDA2__FUNC_SDA2 (MTK_PIN_NO(193) | 1)
+#define MT8135_PIN_193_SDA2__FUNC_EINT95 (MTK_PIN_NO(193) | 2)
+#define MT8135_PIN_193_SDA2__FUNC_CLKM5 (MTK_PIN_NO(193) | 3)
+#define MT8135_PIN_193_SDA2__FUNC_PWM5 (MTK_PIN_NO(193) | 4)
+#define MT8135_PIN_193_SDA2__FUNC_TS_AUX_PWDB (MTK_PIN_NO(193) | 5)
+
+#define MT8135_PIN_194_SCL2__FUNC_GPIO194 (MTK_PIN_NO(194) | 0)
+#define MT8135_PIN_194_SCL2__FUNC_SCL2 (MTK_PIN_NO(194) | 1)
+#define MT8135_PIN_194_SCL2__FUNC_EINT94 (MTK_PIN_NO(194) | 2)
+#define MT8135_PIN_194_SCL2__FUNC_CLKM4 (MTK_PIN_NO(194) | 3)
+#define MT8135_PIN_194_SCL2__FUNC_PWM4 (MTK_PIN_NO(194) | 4)
+#define MT8135_PIN_194_SCL2__FUNC_TS_AUXADC_TEST_CK (MTK_PIN_NO(194) | 5)
+
+#define MT8135_PIN_195_SDA1__FUNC_GPIO195 (MTK_PIN_NO(195) | 0)
+#define MT8135_PIN_195_SDA1__FUNC_SDA1 (MTK_PIN_NO(195) | 1)
+#define MT8135_PIN_195_SDA1__FUNC_EINT93 (MTK_PIN_NO(195) | 2)
+#define MT8135_PIN_195_SDA1__FUNC_CLKM3 (MTK_PIN_NO(195) | 3)
+#define MT8135_PIN_195_SDA1__FUNC_PWM3 (MTK_PIN_NO(195) | 4)
+#define MT8135_PIN_195_SDA1__FUNC_TS_AUX_SCLK_PWDB (MTK_PIN_NO(195) | 5)
+
+#define MT8135_PIN_196_SCL1__FUNC_GPIO196 (MTK_PIN_NO(196) | 0)
+#define MT8135_PIN_196_SCL1__FUNC_SCL1 (MTK_PIN_NO(196) | 1)
+#define MT8135_PIN_196_SCL1__FUNC_EINT92 (MTK_PIN_NO(196) | 2)
+#define MT8135_PIN_196_SCL1__FUNC_CLKM2 (MTK_PIN_NO(196) | 3)
+#define MT8135_PIN_196_SCL1__FUNC_PWM2 (MTK_PIN_NO(196) | 4)
+#define MT8135_PIN_196_SCL1__FUNC_TS_AUX_DIN (MTK_PIN_NO(196) | 5)
+
+#define MT8135_PIN_197_MSDC3_DAT2__FUNC_GPIO197 (MTK_PIN_NO(197) | 0)
+#define MT8135_PIN_197_MSDC3_DAT2__FUNC_MSDC3_DAT2 (MTK_PIN_NO(197) | 1)
+#define MT8135_PIN_197_MSDC3_DAT2__FUNC_EINT71 (MTK_PIN_NO(197) | 2)
+#define MT8135_PIN_197_MSDC3_DAT2__FUNC_SCL6 (MTK_PIN_NO(197) | 3)
+#define MT8135_PIN_197_MSDC3_DAT2__FUNC_PWM5 (MTK_PIN_NO(197) | 4)
+#define MT8135_PIN_197_MSDC3_DAT2__FUNC_CLKM4 (MTK_PIN_NO(197) | 5)
+#define MT8135_PIN_197_MSDC3_DAT2__FUNC_MFG_TEST_CK_2 (MTK_PIN_NO(197) | 6)
+
+#define MT8135_PIN_198_MSDC3_DAT3__FUNC_GPIO198 (MTK_PIN_NO(198) | 0)
+#define MT8135_PIN_198_MSDC3_DAT3__FUNC_MSDC3_DAT3 (MTK_PIN_NO(198) | 1)
+#define MT8135_PIN_198_MSDC3_DAT3__FUNC_EINT72 (MTK_PIN_NO(198) | 2)
+#define MT8135_PIN_198_MSDC3_DAT3__FUNC_SDA6 (MTK_PIN_NO(198) | 3)
+#define MT8135_PIN_198_MSDC3_DAT3__FUNC_PWM6 (MTK_PIN_NO(198) | 4)
+#define MT8135_PIN_198_MSDC3_DAT3__FUNC_CLKM5 (MTK_PIN_NO(198) | 5)
+#define MT8135_PIN_198_MSDC3_DAT3__FUNC_MFG_TEST_CK_3 (MTK_PIN_NO(198) | 6)
+
+#define MT8135_PIN_199_MSDC3_CMD__FUNC_GPIO199 (MTK_PIN_NO(199) | 0)
+#define MT8135_PIN_199_MSDC3_CMD__FUNC_MSDC3_CMD (MTK_PIN_NO(199) | 1)
+#define MT8135_PIN_199_MSDC3_CMD__FUNC_EINT68 (MTK_PIN_NO(199) | 2)
+#define MT8135_PIN_199_MSDC3_CMD__FUNC_SDA2 (MTK_PIN_NO(199) | 3)
+#define MT8135_PIN_199_MSDC3_CMD__FUNC_PWM2 (MTK_PIN_NO(199) | 4)
+#define MT8135_PIN_199_MSDC3_CMD__FUNC_CLKM1 (MTK_PIN_NO(199) | 5)
+#define MT8135_PIN_199_MSDC3_CMD__FUNC_MFG_TEST_CK_4 (MTK_PIN_NO(199) | 6)
+
+#define MT8135_PIN_200_MSDC3_CLK__FUNC_GPIO200 (MTK_PIN_NO(200) | 0)
+#define MT8135_PIN_200_MSDC3_CLK__FUNC_MSDC3_CLK (MTK_PIN_NO(200) | 1)
+#define MT8135_PIN_200_MSDC3_CLK__FUNC_EINT67 (MTK_PIN_NO(200) | 2)
+#define MT8135_PIN_200_MSDC3_CLK__FUNC_SCL2 (MTK_PIN_NO(200) | 3)
+#define MT8135_PIN_200_MSDC3_CLK__FUNC_PWM1 (MTK_PIN_NO(200) | 4)
+#define MT8135_PIN_200_MSDC3_CLK__FUNC_CLKM0 (MTK_PIN_NO(200) | 5)
+
+#define MT8135_PIN_201_MSDC3_DAT1__FUNC_GPIO201 (MTK_PIN_NO(201) | 0)
+#define MT8135_PIN_201_MSDC3_DAT1__FUNC_MSDC3_DAT1 (MTK_PIN_NO(201) | 1)
+#define MT8135_PIN_201_MSDC3_DAT1__FUNC_EINT70 (MTK_PIN_NO(201) | 2)
+#define MT8135_PIN_201_MSDC3_DAT1__FUNC_SDA3 (MTK_PIN_NO(201) | 3)
+#define MT8135_PIN_201_MSDC3_DAT1__FUNC_PWM4 (MTK_PIN_NO(201) | 4)
+#define MT8135_PIN_201_MSDC3_DAT1__FUNC_CLKM3 (MTK_PIN_NO(201) | 5)
+
+#define MT8135_PIN_202_MSDC3_DAT0__FUNC_GPIO202 (MTK_PIN_NO(202) | 0)
+#define MT8135_PIN_202_MSDC3_DAT0__FUNC_MSDC3_DAT0 (MTK_PIN_NO(202) | 1)
+#define MT8135_PIN_202_MSDC3_DAT0__FUNC_EINT69 (MTK_PIN_NO(202) | 2)
+#define MT8135_PIN_202_MSDC3_DAT0__FUNC_SCL3 (MTK_PIN_NO(202) | 3)
+#define MT8135_PIN_202_MSDC3_DAT0__FUNC_PWM3 (MTK_PIN_NO(202) | 4)
+#define MT8135_PIN_202_MSDC3_DAT0__FUNC_CLKM2 (MTK_PIN_NO(202) | 5)
+
+#endif /* __DTS_MT8135_PINFUNC_H */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/mxs-pinfunc.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/mxs-pinfunc.h
new file mode 100644
index 0000000000000000000000000000000000000000..c6da987b20cbffaf59958de401cd2e012f8e2b44
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/mxs-pinfunc.h
@@ -0,0 +1,31 @@
+/*
+ * Header providing constants for i.MX28 pinctrl bindings.
+ *
+ * Copyright (C) 2013 Lothar Waßmann <LW@KARO-electronics.de>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#ifndef __DT_BINDINGS_MXS_PINCTRL_H__
+#define __DT_BINDINGS_MXS_PINCTRL_H__
+
+/* fsl,drive-strength property */
+#define MXS_DRIVE_4mA		0
+#define MXS_DRIVE_8mA		1
+#define MXS_DRIVE_12mA		2
+#define MXS_DRIVE_16mA		3
+
+/* fsl,voltage property */
+#define MXS_VOLTAGE_LOW		0
+#define MXS_VOLTAGE_HIGH	1
+
+/* fsl,pull-up property */
+#define MXS_PULL_DISABLE	0
+#define MXS_PULL_ENABLE		1
+
+#endif /* __DT_BINDINGS_MXS_PINCTRL_H__ */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/sama5d2-pinfunc.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/sama5d2-pinfunc.h
new file mode 100644
index 0000000000000000000000000000000000000000..28a2e45752fea34eb2efb576439409c0611d9d90
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/sama5d2-pinfunc.h
@@ -0,0 +1,881 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#define PINMUX_PIN(no, func, ioset) \
+(((no) & 0xffff) | (((func) & 0xf) << 16) | (((ioset) & 0xff) << 20))
+
+#define PIN_PA0				0
+#define PIN_PA0__GPIO			PINMUX_PIN(PIN_PA0, 0, 0)
+#define PIN_PA0__SDMMC0_CK		PINMUX_PIN(PIN_PA0, 1, 1)
+#define PIN_PA0__QSPI0_SCK		PINMUX_PIN(PIN_PA0, 2, 1)
+#define PIN_PA0__D0			PINMUX_PIN(PIN_PA0, 6, 2)
+#define PIN_PA1				1
+#define PIN_PA1__GPIO			PINMUX_PIN(PIN_PA1, 0, 0)
+#define PIN_PA1__SDMMC0_CMD		PINMUX_PIN(PIN_PA1, 1, 1)
+#define PIN_PA1__QSPI0_CS		PINMUX_PIN(PIN_PA1, 2, 1)
+#define PIN_PA1__D1			PINMUX_PIN(PIN_PA1, 6, 2)
+#define PIN_PA2				2
+#define PIN_PA2__GPIO			PINMUX_PIN(PIN_PA2, 0, 0)
+#define PIN_PA2__SDMMC0_DAT0		PINMUX_PIN(PIN_PA2, 1, 1)
+#define PIN_PA2__QSPI0_IO0		PINMUX_PIN(PIN_PA2, 2, 1)
+#define PIN_PA2__D2			PINMUX_PIN(PIN_PA2, 6, 2)
+#define PIN_PA3				3
+#define PIN_PA3__GPIO			PINMUX_PIN(PIN_PA3, 0, 0)
+#define PIN_PA3__SDMMC0_DAT1		PINMUX_PIN(PIN_PA3, 1, 1)
+#define PIN_PA3__QSPI0_IO1		PINMUX_PIN(PIN_PA3, 2, 1)
+#define PIN_PA3__D3			PINMUX_PIN(PIN_PA3, 6, 2)
+#define PIN_PA4				4
+#define PIN_PA4__GPIO			PINMUX_PIN(PIN_PA4, 0, 0)
+#define PIN_PA4__SDMMC0_DAT2		PINMUX_PIN(PIN_PA4, 1, 1)
+#define PIN_PA4__QSPI0_IO2		PINMUX_PIN(PIN_PA4, 2, 1)
+#define PIN_PA4__D4			PINMUX_PIN(PIN_PA4, 6, 2)
+#define PIN_PA5				5
+#define PIN_PA5__GPIO			PINMUX_PIN(PIN_PA5, 0, 0)
+#define PIN_PA5__SDMMC0_DAT3		PINMUX_PIN(PIN_PA5, 1, 1)
+#define PIN_PA5__QSPI0_IO3		PINMUX_PIN(PIN_PA5, 2, 1)
+#define PIN_PA5__D5			PINMUX_PIN(PIN_PA5, 6, 2)
+#define PIN_PA6				6
+#define PIN_PA6__GPIO			PINMUX_PIN(PIN_PA6, 0, 0)
+#define PIN_PA6__SDMMC0_DAT4		PINMUX_PIN(PIN_PA6, 1, 1)
+#define PIN_PA6__QSPI1_SCK		PINMUX_PIN(PIN_PA6, 2, 1)
+#define PIN_PA6__TIOA5			PINMUX_PIN(PIN_PA6, 4, 1)
+#define PIN_PA6__FLEXCOM2_IO0		PINMUX_PIN(PIN_PA6, 5, 1)
+#define PIN_PA6__D6			PINMUX_PIN(PIN_PA6, 6, 2)
+#define PIN_PA7				7
+#define PIN_PA7__GPIO			PINMUX_PIN(PIN_PA7, 0, 0)
+#define PIN_PA7__SDMMC0_DAT5		PINMUX_PIN(PIN_PA7, 1, 1)
+#define PIN_PA7__QSPI1_IO0		PINMUX_PIN(PIN_PA7, 2, 1)
+#define PIN_PA7__TIOB5			PINMUX_PIN(PIN_PA7, 4, 1)
+#define PIN_PA7__FLEXCOM2_IO1		PINMUX_PIN(PIN_PA7, 5, 1)
+#define PIN_PA7__D7			PINMUX_PIN(PIN_PA7, 6, 2)
+#define PIN_PA8				8
+#define PIN_PA8__GPIO			PINMUX_PIN(PIN_PA8, 0, 0)
+#define PIN_PA8__SDMMC0_DAT6		PINMUX_PIN(PIN_PA8, 1, 1)
+#define PIN_PA8__QSPI1_IO1		PINMUX_PIN(PIN_PA8, 2, 1)
+#define PIN_PA8__TCLK5			PINMUX_PIN(PIN_PA8, 4, 1)
+#define PIN_PA8__FLEXCOM2_IO2		PINMUX_PIN(PIN_PA8, 5, 1)
+#define PIN_PA8__NWE_NANDWE		PINMUX_PIN(PIN_PA8, 6, 2)
+#define PIN_PA9				9
+#define PIN_PA9__GPIO			PINMUX_PIN(PIN_PA9, 0, 0)
+#define PIN_PA9__SDMMC0_DAT7		PINMUX_PIN(PIN_PA9, 1, 1)
+#define PIN_PA9__QSPI1_IO2		PINMUX_PIN(PIN_PA9, 2, 1)
+#define PIN_PA9__TIOA4			PINMUX_PIN(PIN_PA9, 4, 1)
+#define PIN_PA9__FLEXCOM2_IO3		PINMUX_PIN(PIN_PA9, 5, 1)
+#define PIN_PA9__NCS3			PINMUX_PIN(PIN_PA9, 6, 2)
+#define PIN_PA10			10
+#define PIN_PA10__GPIO			PINMUX_PIN(PIN_PA10, 0, 0)
+#define PIN_PA10__SDMMC0_RSTN		PINMUX_PIN(PIN_PA10, 1, 1)
+#define PIN_PA10__QSPI1_IO3		PINMUX_PIN(PIN_PA10, 2, 1)
+#define PIN_PA10__TIOB4			PINMUX_PIN(PIN_PA10, 4, 1)
+#define PIN_PA10__FLEXCOM2_IO4		PINMUX_PIN(PIN_PA10, 5, 1)
+#define PIN_PA10__A21_NANDALE		PINMUX_PIN(PIN_PA10, 6, 2)
+#define PIN_PA11			11
+#define PIN_PA11__GPIO			PINMUX_PIN(PIN_PA11, 0, 0)
+#define PIN_PA11__SDMMC0_VDDSEL		PINMUX_PIN(PIN_PA11, 1, 1)
+#define PIN_PA11__QSPI1_CS		PINMUX_PIN(PIN_PA11, 2, 1)
+#define PIN_PA11__TCLK4			PINMUX_PIN(PIN_PA11, 4, 1)
+#define PIN_PA11__A22_NANDCLE		PINMUX_PIN(PIN_PA11, 6, 2)
+#define PIN_PA12			12
+#define PIN_PA12__GPIO			PINMUX_PIN(PIN_PA12, 0, 0)
+#define PIN_PA12__SDMMC0_WP		PINMUX_PIN(PIN_PA12, 1, 1)
+#define PIN_PA12__IRQ			PINMUX_PIN(PIN_PA12, 2, 1)
+#define PIN_PA12__NRD_NANDOE		PINMUX_PIN(PIN_PA12, 6, 2)
+#define PIN_PA13			13
+#define PIN_PA13__GPIO			PINMUX_PIN(PIN_PA13, 0, 0)
+#define PIN_PA13__SDMMC0_CD		PINMUX_PIN(PIN_PA13, 1, 1)
+#define PIN_PA13__FLEXCOM3_IO1		PINMUX_PIN(PIN_PA13, 5, 1)
+#define PIN_PA13__D8			PINMUX_PIN(PIN_PA13, 6, 2)
+#define PIN_PA14			14
+#define PIN_PA14__GPIO			PINMUX_PIN(PIN_PA14, 0, 0)
+#define PIN_PA14__SPI0_SPCK		PINMUX_PIN(PIN_PA14, 1, 1)
+#define PIN_PA14__TK1			PINMUX_PIN(PIN_PA14, 2, 1)
+#define PIN_PA14__QSPI0_SCK		PINMUX_PIN(PIN_PA14, 3, 2)
+#define PIN_PA14__I2SC1_MCK		PINMUX_PIN(PIN_PA14, 4, 2)
+#define PIN_PA14__FLEXCOM3_IO2		PINMUX_PIN(PIN_PA14, 5, 1)
+#define PIN_PA14__D9			PINMUX_PIN(PIN_PA14, 6, 2)
+#define PIN_PA15			15
+#define PIN_PA15__GPIO			PINMUX_PIN(PIN_PA15, 0, 0)
+#define PIN_PA15__SPI0_MOSI		PINMUX_PIN(PIN_PA15, 1, 1)
+#define PIN_PA15__TF1			PINMUX_PIN(PIN_PA15, 2, 1)
+#define PIN_PA15__QSPI0_CS		PINMUX_PIN(PIN_PA15, 3, 2)
+#define PIN_PA15__I2SC1_CK		PINMUX_PIN(PIN_PA15, 4, 2)
+#define PIN_PA15__FLEXCOM3_IO0		PINMUX_PIN(PIN_PA15, 5, 1)
+#define PIN_PA15__D10			PINMUX_PIN(PIN_PA15, 6, 2)
+#define PIN_PA16			16
+#define PIN_PA16__GPIO			PINMUX_PIN(PIN_PA16, 0, 0)
+#define PIN_PA16__SPI0_MISO		PINMUX_PIN(PIN_PA16, 1, 1)
+#define PIN_PA16__TD1			PINMUX_PIN(PIN_PA16, 2, 1)
+#define PIN_PA16__QSPI0_IO0		PINMUX_PIN(PIN_PA16, 3, 2)
+#define PIN_PA16__I2SC1_WS		PINMUX_PIN(PIN_PA16, 4, 2)
+#define PIN_PA16__FLEXCOM3_IO3		PINMUX_PIN(PIN_PA16, 5, 1)
+#define PIN_PA16__D11			PINMUX_PIN(PIN_PA16, 6, 2)
+#define PIN_PA17			17
+#define PIN_PA17__GPIO			PINMUX_PIN(PIN_PA17, 0, 0)
+#define PIN_PA17__SPI0_NPCS0		PINMUX_PIN(PIN_PA17, 1, 1)
+#define PIN_PA17__RD1			PINMUX_PIN(PIN_PA17, 2, 1)
+#define PIN_PA17__QSPI0_IO1		PINMUX_PIN(PIN_PA17, 3, 2)
+#define PIN_PA17__I2SC1_DI0		PINMUX_PIN(PIN_PA17, 4, 2)
+#define PIN_PA17__FLEXCOM3_IO4		PINMUX_PIN(PIN_PA17, 5, 1)
+#define PIN_PA17__D12			PINMUX_PIN(PIN_PA17, 6, 2)
+#define PIN_PA18			18
+#define PIN_PA18__GPIO			PINMUX_PIN(PIN_PA18, 0, 0)
+#define PIN_PA18__SPI0_NPCS1		PINMUX_PIN(PIN_PA18, 1, 1)
+#define PIN_PA18__RK1			PINMUX_PIN(PIN_PA18, 2, 1)
+#define PIN_PA18__QSPI0_IO2		PINMUX_PIN(PIN_PA18, 3, 2)
+#define PIN_PA18__I2SC1_DO0		PINMUX_PIN(PIN_PA18, 4, 2)
+#define PIN_PA18__SDMMC1_DAT0		PINMUX_PIN(PIN_PA18, 5, 1)
+#define PIN_PA18__D13			PINMUX_PIN(PIN_PA18, 6, 2)
+#define PIN_PA19			19
+#define PIN_PA19__GPIO			PINMUX_PIN(PIN_PA19, 0, 0)
+#define PIN_PA19__SPI0_NPCS2		PINMUX_PIN(PIN_PA19, 1, 1)
+#define PIN_PA19__RF1			PINMUX_PIN(PIN_PA19, 2, 1)
+#define PIN_PA19__QSPI0_IO3		PINMUX_PIN(PIN_PA19, 3, 2)
+#define PIN_PA19__TIOA0			PINMUX_PIN(PIN_PA19, 4, 1)
+#define PIN_PA19__SDMMC1_DAT1		PINMUX_PIN(PIN_PA19, 5, 1)
+#define PIN_PA19__D14			PINMUX_PIN(PIN_PA19, 6, 2)
+#define PIN_PA20			20
+#define PIN_PA20__GPIO			PINMUX_PIN(PIN_PA20, 0, 0)
+#define PIN_PA20__SPI0_NPCS3		PINMUX_PIN(PIN_PA20, 1, 1)
+#define PIN_PA20__TIOB0			PINMUX_PIN(PIN_PA20, 4, 1)
+#define PIN_PA20__SDMMC1_DAT2		PINMUX_PIN(PIN_PA20, 5, 1)
+#define PIN_PA20__D15			PINMUX_PIN(PIN_PA20, 6, 2)
+#define PIN_PA21			21
+#define PIN_PA21__GPIO			PINMUX_PIN(PIN_PA21, 0, 0)
+#define PIN_PA21__IRQ			PINMUX_PIN(PIN_PA21, 1, 2)
+#define PIN_PA21__PCK2			PINMUX_PIN(PIN_PA21, 2, 3)
+#define PIN_PA21__TCLK0			PINMUX_PIN(PIN_PA21, 4, 1)
+#define PIN_PA21__SDMMC1_DAT3		PINMUX_PIN(PIN_PA21, 5, 1)
+#define PIN_PA21__NANDRDY		PINMUX_PIN(PIN_PA21, 6, 2)
+#define PIN_PA22			22
+#define PIN_PA22__GPIO			PINMUX_PIN(PIN_PA22, 0, 0)
+#define PIN_PA22__FLEXCOM1_IO2		PINMUX_PIN(PIN_PA22, 1, 1)
+#define PIN_PA22__D0			PINMUX_PIN(PIN_PA22, 2, 1)
+#define PIN_PA22__TCK			PINMUX_PIN(PIN_PA22, 3, 4)
+#define PIN_PA22__SPI1_SPCK		PINMUX_PIN(PIN_PA22, 4, 2)
+#define PIN_PA22__SDMMC1_CK		PINMUX_PIN(PIN_PA22, 5, 1)
+#define PIN_PA22__QSPI0_SCK		PINMUX_PIN(PIN_PA22, 6, 3)
+#define PIN_PA23			23
+#define PIN_PA23__GPIO			PINMUX_PIN(PIN_PA23, 0, 0)
+#define PIN_PA23__FLEXCOM1_IO1		PINMUX_PIN(PIN_PA23, 1, 1)
+#define PIN_PA23__D1			PINMUX_PIN(PIN_PA23, 2, 1)
+#define PIN_PA23__TDI			PINMUX_PIN(PIN_PA23, 3, 4)
+#define PIN_PA23__SPI1_MOSI		PINMUX_PIN(PIN_PA23, 4, 2)
+#define PIN_PA23__QSPI0_CS		PINMUX_PIN(PIN_PA23, 6, 3)
+#define PIN_PA24			24
+#define PIN_PA24__GPIO			PINMUX_PIN(PIN_PA24, 0, 0)
+#define PIN_PA24__FLEXCOM1_IO0		PINMUX_PIN(PIN_PA24, 1, 1)
+#define PIN_PA24__D2			PINMUX_PIN(PIN_PA24, 2, 1)
+#define PIN_PA24__TDO			PINMUX_PIN(PIN_PA24, 3, 4)
+#define PIN_PA24__SPI1_MISO		PINMUX_PIN(PIN_PA24, 4, 2)
+#define PIN_PA24__QSPI0_IO0		PINMUX_PIN(PIN_PA24, 6, 3)
+#define PIN_PA25			25
+#define PIN_PA25__GPIO			PINMUX_PIN(PIN_PA25, 0, 0)
+#define PIN_PA25__FLEXCOM1_IO3		PINMUX_PIN(PIN_PA25, 1, 1)
+#define PIN_PA25__D3			PINMUX_PIN(PIN_PA25, 2, 1)
+#define PIN_PA25__TMS			PINMUX_PIN(PIN_PA25, 3, 4)
+#define PIN_PA25__SPI1_NPCS0		PINMUX_PIN(PIN_PA25, 4, 2)
+#define PIN_PA25__QSPI0_IO1		PINMUX_PIN(PIN_PA25, 6, 3)
+#define PIN_PA26			26
+#define PIN_PA26__GPIO			PINMUX_PIN(PIN_PA26, 0, 0)
+#define PIN_PA26__FLEXCOM1_IO4		PINMUX_PIN(PIN_PA26, 1, 1)
+#define PIN_PA26__D4			PINMUX_PIN(PIN_PA26, 2, 1)
+#define PIN_PA26__NTRST			PINMUX_PIN(PIN_PA26, 3, 4)
+#define PIN_PA26__SPI1_NPCS1		PINMUX_PIN(PIN_PA26, 4, 2)
+#define PIN_PA26__QSPI0_IO2		PINMUX_PIN(PIN_PA26, 6, 3)
+#define PIN_PA27			27
+#define PIN_PA27__GPIO			PINMUX_PIN(PIN_PA27, 0, 0)
+#define PIN_PA27__TIOA1			PINMUX_PIN(PIN_PA27, 1, 2)
+#define PIN_PA27__D5			PINMUX_PIN(PIN_PA27, 2, 1)
+#define PIN_PA27__SPI0_NPCS2		PINMUX_PIN(PIN_PA27, 3, 2)
+#define PIN_PA27__SPI1_NPCS2		PINMUX_PIN(PIN_PA27, 4, 2)
+#define PIN_PA27__SDMMC1_RSTN		PINMUX_PIN(PIN_PA27, 5, 1)
+#define PIN_PA27__QSPI0_IO3		PINMUX_PIN(PIN_PA27, 6, 3)
+#define PIN_PA28			28
+#define PIN_PA28__GPIO			PINMUX_PIN(PIN_PA28, 0, 0)
+#define PIN_PA28__TIOB1			PINMUX_PIN(PIN_PA28, 1, 2)
+#define PIN_PA28__D6			PINMUX_PIN(PIN_PA28, 2, 1)
+#define PIN_PA28__SPI0_NPCS3		PINMUX_PIN(PIN_PA28, 3, 2)
+#define PIN_PA28__SPI1_NPCS3		PINMUX_PIN(PIN_PA28, 4, 2)
+#define PIN_PA28__SDMMC1_CMD		PINMUX_PIN(PIN_PA28, 5, 1)
+#define PIN_PA28__CLASSD_L0		PINMUX_PIN(PIN_PA28, 6, 1)
+#define PIN_PA29			29
+#define PIN_PA29__GPIO			PINMUX_PIN(PIN_PA29, 0, 0)
+#define PIN_PA29__TCLK1			PINMUX_PIN(PIN_PA29, 1, 2)
+#define PIN_PA29__D7			PINMUX_PIN(PIN_PA29, 2, 1)
+#define PIN_PA29__SPI0_NPCS1		PINMUX_PIN(PIN_PA29, 3, 2)
+#define PIN_PA29__SDMMC1_WP		PINMUX_PIN(PIN_PA29, 5, 1)
+#define PIN_PA29__CLASSD_L1		PINMUX_PIN(PIN_PA29, 6, 1)
+#define PIN_PA30			30
+#define PIN_PA30__GPIO			PINMUX_PIN(PIN_PA30, 0, 0)
+#define PIN_PA30__NWE_NANDWE		PINMUX_PIN(PIN_PA30, 2, 1)
+#define PIN_PA30__SPI0_NPCS0		PINMUX_PIN(PIN_PA30, 3, 2)
+#define PIN_PA30__PWMH0			PINMUX_PIN(PIN_PA30, 4, 1)
+#define PIN_PA30__SDMMC1_CD		PINMUX_PIN(PIN_PA30, 5, 1)
+#define PIN_PA30__CLASSD_L2		PINMUX_PIN(PIN_PA30, 6, 1)
+#define PIN_PA31			31
+#define PIN_PA31__GPIO			PINMUX_PIN(PIN_PA31, 0, 0)
+#define PIN_PA31__NCS3			PINMUX_PIN(PIN_PA31, 2, 1)
+#define PIN_PA31__SPI0_MISO		PINMUX_PIN(PIN_PA31, 3, 2)
+#define PIN_PA31__PWML0			PINMUX_PIN(PIN_PA31, 4, 1)
+#define PIN_PA31__CLASSD_L3		PINMUX_PIN(PIN_PA31, 6, 1)
+#define PIN_PB0				32
+#define PIN_PB0__GPIO			PINMUX_PIN(PIN_PB0, 0, 0)
+#define PIN_PB0__A21_NANDALE		PINMUX_PIN(PIN_PB0, 2, 1)
+#define PIN_PB0__SPI0_MOSI		PINMUX_PIN(PIN_PB0, 3, 2)
+#define PIN_PB0__PWMH1			PINMUX_PIN(PIN_PB0, 4, 1)
+#define PIN_PB1				33
+#define PIN_PB1__GPIO			PINMUX_PIN(PIN_PB1, 0, 0)
+#define PIN_PB1__A22_NANDCLE		PINMUX_PIN(PIN_PB1, 2, 1)
+#define PIN_PB1__SPI0_SPCK		PINMUX_PIN(PIN_PB1, 3, 2)
+#define PIN_PB1__PWML1			PINMUX_PIN(PIN_PB1, 4, 1)
+#define PIN_PB1__CLASSD_R0		PINMUX_PIN(PIN_PB1, 6, 1)
+#define PIN_PB2				34
+#define PIN_PB2__GPIO			PINMUX_PIN(PIN_PB2, 0, 0)
+#define PIN_PB2__NRD_NANDOE		PINMUX_PIN(PIN_PB2, 2, 1)
+#define PIN_PB2__PWMFI0			PINMUX_PIN(PIN_PB2, 4, 1)
+#define PIN_PB2__CLASSD_R1		PINMUX_PIN(PIN_PB2, 6, 1)
+#define PIN_PB3				35
+#define PIN_PB3__GPIO			PINMUX_PIN(PIN_PB3, 0, 0)
+#define PIN_PB3__URXD4			PINMUX_PIN(PIN_PB3, 1, 1)
+#define PIN_PB3__D8			PINMUX_PIN(PIN_PB3, 2, 1)
+#define PIN_PB3__IRQ			PINMUX_PIN(PIN_PB3, 3, 3)
+#define PIN_PB3__PWMEXTRG0		PINMUX_PIN(PIN_PB3, 4, 1)
+#define PIN_PB3__CLASSD_R2		PINMUX_PIN(PIN_PB3, 6, 1)
+#define PIN_PB4				36
+#define PIN_PB4__GPIO			PINMUX_PIN(PIN_PB4, 0, 0)
+#define PIN_PB4__UTXD4			PINMUX_PIN(PIN_PB4, 1, 1)
+#define PIN_PB4__D9			PINMUX_PIN(PIN_PB4, 2, 1)
+#define PIN_PB4__FIQ			PINMUX_PIN(PIN_PB4, 3, 4)
+#define PIN_PB4__CLASSD_R3		PINMUX_PIN(PIN_PB4, 6, 1)
+#define PIN_PB5				37
+#define PIN_PB5__GPIO			PINMUX_PIN(PIN_PB5, 0, 0)
+#define PIN_PB5__TCLK2			PINMUX_PIN(PIN_PB5, 1, 1)
+#define PIN_PB5__D10			PINMUX_PIN(PIN_PB5, 2, 1)
+#define PIN_PB5__PWMH2			PINMUX_PIN(PIN_PB5, 3, 1)
+#define PIN_PB5__QSPI1_SCK		PINMUX_PIN(PIN_PB5, 4, 2)
+#define PIN_PB5__GTSUCOMP		PINMUX_PIN(PIN_PB5, 6, 3)
+#define PIN_PB6				38
+#define PIN_PB6__GPIO			PINMUX_PIN(PIN_PB6, 0, 0)
+#define PIN_PB6__TIOA2			PINMUX_PIN(PIN_PB6, 1, 1)
+#define PIN_PB6__D11			PINMUX_PIN(PIN_PB6, 2, 1)
+#define PIN_PB6__PWML2			PINMUX_PIN(PIN_PB6, 3, 1)
+#define PIN_PB6__QSPI1_CS		PINMUX_PIN(PIN_PB6, 4, 2)
+#define PIN_PB6__GTXER			PINMUX_PIN(PIN_PB6, 6, 3)
+#define PIN_PB7				39
+#define PIN_PB7__GPIO			PINMUX_PIN(PIN_PB7, 0, 0)
+#define PIN_PB7__TIOB2			PINMUX_PIN(PIN_PB7, 1, 1)
+#define PIN_PB7__D12			PINMUX_PIN(PIN_PB7, 2, 1)
+#define PIN_PB7__PWMH3			PINMUX_PIN(PIN_PB7, 3, 1)
+#define PIN_PB7__QSPI1_IO0		PINMUX_PIN(PIN_PB7, 4, 2)
+#define PIN_PB7__GRXCK			PINMUX_PIN(PIN_PB7, 6, 3)
+#define PIN_PB8				40
+#define PIN_PB8__GPIO			PINMUX_PIN(PIN_PB8, 0, 0)
+#define PIN_PB8__TCLK3			PINMUX_PIN(PIN_PB8, 1, 1)
+#define PIN_PB8__D13			PINMUX_PIN(PIN_PB8, 2, 1)
+#define PIN_PB8__PWML3			PINMUX_PIN(PIN_PB8, 3, 1)
+#define PIN_PB8__QSPI1_IO1		PINMUX_PIN(PIN_PB8, 4, 2)
+#define PIN_PB8__GCRS			PINMUX_PIN(PIN_PB8, 6, 3)
+#define PIN_PB9				41
+#define PIN_PB9__GPIO			PINMUX_PIN(PIN_PB9, 0, 0)
+#define PIN_PB9__TIOA3			PINMUX_PIN(PIN_PB9, 1, 1)
+#define PIN_PB9__D14			PINMUX_PIN(PIN_PB9, 2, 1)
+#define PIN_PB9__PWMFI1			PINMUX_PIN(PIN_PB9, 3, 1)
+#define PIN_PB9__QSPI1_IO2		PINMUX_PIN(PIN_PB9, 4, 2)
+#define PIN_PB9__GCOL			PINMUX_PIN(PIN_PB9, 6, 3)
+#define PIN_PB10			42
+#define PIN_PB10__GPIO			PINMUX_PIN(PIN_PB10, 0, 0)
+#define PIN_PB10__TIOB3			PINMUX_PIN(PIN_PB10, 1, 1)
+#define PIN_PB10__D15			PINMUX_PIN(PIN_PB10, 2, 1)
+#define PIN_PB10__PWMEXTRG1		PINMUX_PIN(PIN_PB10, 3, 1)
+#define PIN_PB10__QSPI1_IO3		PINMUX_PIN(PIN_PB10, 4, 2)
+#define PIN_PB10__GRX2			PINMUX_PIN(PIN_PB10, 6, 3)
+#define PIN_PB11			43
+#define PIN_PB11__GPIO			PINMUX_PIN(PIN_PB11, 0, 0)
+#define PIN_PB11__LCDDAT0		PINMUX_PIN(PIN_PB11, 1, 1)
+#define PIN_PB11__A0_NBS0		PINMUX_PIN(PIN_PB11, 2, 1)
+#define PIN_PB11__URXD3			PINMUX_PIN(PIN_PB11, 3, 3)
+#define PIN_PB11__PDMIC_DAT		PINMUX_PIN(PIN_PB11, 4, 2)
+#define PIN_PB11__GRX3			PINMUX_PIN(PIN_PB11, 6, 3)
+#define PIN_PB12			44
+#define PIN_PB12__GPIO			PINMUX_PIN(PIN_PB12, 0, 0)
+#define PIN_PB12__LCDDAT1		PINMUX_PIN(PIN_PB12, 1, 1)
+#define PIN_PB12__A1			PINMUX_PIN(PIN_PB12, 2, 1)
+#define PIN_PB12__UTXD3			PINMUX_PIN(PIN_PB12, 3, 3)
+#define PIN_PB12__PDMIC_CLK		PINMUX_PIN(PIN_PB12, 4, 2)
+#define PIN_PB12__GTX2			PINMUX_PIN(PIN_PB12, 6, 3)
+#define PIN_PB13			45
+#define PIN_PB13__GPIO			PINMUX_PIN(PIN_PB13, 0, 0)
+#define PIN_PB13__LCDDAT2		PINMUX_PIN(PIN_PB13, 1, 1)
+#define PIN_PB13__A2			PINMUX_PIN(PIN_PB13, 2, 1)
+#define PIN_PB13__PCK1			PINMUX_PIN(PIN_PB13, 3, 3)
+#define PIN_PB13__GTX3			PINMUX_PIN(PIN_PB13, 6, 3)
+#define PIN_PB14			46
+#define PIN_PB14__GPIO			PINMUX_PIN(PIN_PB14, 0, 0)
+#define PIN_PB14__LCDDAT3		PINMUX_PIN(PIN_PB14, 1, 1)
+#define PIN_PB14__A3			PINMUX_PIN(PIN_PB14, 2, 1)
+#define PIN_PB14__TK1			PINMUX_PIN(PIN_PB14, 3, 2)
+#define PIN_PB14__I2SC1_MCK		PINMUX_PIN(PIN_PB14, 4, 1)
+#define PIN_PB14__QSPI1_SCK		PINMUX_PIN(PIN_PB14, 5, 3)
+#define PIN_PB14__GTXCK			PINMUX_PIN(PIN_PB14, 6, 3)
+#define PIN_PB15			47
+#define PIN_PB15__GPIO			PINMUX_PIN(PIN_PB15, 0, 0)
+#define PIN_PB15__LCDDAT4		PINMUX_PIN(PIN_PB15, 1, 1)
+#define PIN_PB15__A4			PINMUX_PIN(PIN_PB15, 2, 1)
+#define PIN_PB15__TF1			PINMUX_PIN(PIN_PB15, 3, 2)
+#define PIN_PB15__I2SC1_CK		PINMUX_PIN(PIN_PB15, 4, 1)
+#define PIN_PB15__QSPI1_CS		PINMUX_PIN(PIN_PB15, 5, 3)
+#define PIN_PB15__GTXEN			PINMUX_PIN(PIN_PB15, 6, 3)
+#define PIN_PB16			48
+#define PIN_PB16__GPIO			PINMUX_PIN(PIN_PB16, 0, 0)
+#define PIN_PB16__LCDDAT5		PINMUX_PIN(PIN_PB16, 1, 1)
+#define PIN_PB16__A5			PINMUX_PIN(PIN_PB16, 2, 1)
+#define PIN_PB16__TD1			PINMUX_PIN(PIN_PB16, 3, 2)
+#define PIN_PB16__I2SC1_WS		PINMUX_PIN(PIN_PB16, 4, 1)
+#define PIN_PB16__QSPI1_IO0		PINMUX_PIN(PIN_PB16, 5, 3)
+#define PIN_PB16__GRXDV			PINMUX_PIN(PIN_PB16, 6, 3)
+#define PIN_PB17			49
+#define PIN_PB17__GPIO			PINMUX_PIN(PIN_PB17, 0, 0)
+#define PIN_PB17__LCDDAT6		PINMUX_PIN(PIN_PB17, 1, 1)
+#define PIN_PB17__A6			PINMUX_PIN(PIN_PB17, 2, 1)
+#define PIN_PB17__RD1			PINMUX_PIN(PIN_PB17, 3, 2)
+#define PIN_PB17__I2SC1_DI0		PINMUX_PIN(PIN_PB17, 4, 1)
+#define PIN_PB17__QSPI1_IO1		PINMUX_PIN(PIN_PB17, 5, 3)
+#define PIN_PB17__GRXER			PINMUX_PIN(PIN_PB17, 6, 3)
+#define PIN_PB18			50
+#define PIN_PB18__GPIO			PINMUX_PIN(PIN_PB18, 0, 0)
+#define PIN_PB18__LCDDAT7		PINMUX_PIN(PIN_PB18, 1, 1)
+#define PIN_PB18__A7			PINMUX_PIN(PIN_PB18, 2, 1)
+#define PIN_PB18__RK1			PINMUX_PIN(PIN_PB18, 3, 2)
+#define PIN_PB18__I2SC1_DO0		PINMUX_PIN(PIN_PB18, 4, 1)
+#define PIN_PB18__QSPI1_IO2		PINMUX_PIN(PIN_PB18, 5, 3)
+#define PIN_PB18__GRX0			PINMUX_PIN(PIN_PB18, 6, 3)
+#define PIN_PB19			51
+#define PIN_PB19__GPIO			PINMUX_PIN(PIN_PB19, 0, 0)
+#define PIN_PB19__LCDDAT8		PINMUX_PIN(PIN_PB19, 1, 1)
+#define PIN_PB19__A8			PINMUX_PIN(PIN_PB19, 2, 1)
+#define PIN_PB19__RF1			PINMUX_PIN(PIN_PB19, 3, 2)
+#define PIN_PB19__TIOA3			PINMUX_PIN(PIN_PB19, 4, 2)
+#define PIN_PB19__QSPI1_IO3		PINMUX_PIN(PIN_PB19, 5, 3)
+#define PIN_PB19__GRX1			PINMUX_PIN(PIN_PB19, 6, 3)
+#define PIN_PB20			52
+#define PIN_PB20__GPIO			PINMUX_PIN(PIN_PB20, 0, 0)
+#define PIN_PB20__LCDDAT9		PINMUX_PIN(PIN_PB20, 1, 1)
+#define PIN_PB20__A9			PINMUX_PIN(PIN_PB20, 2, 1)
+#define PIN_PB20__TK0			PINMUX_PIN(PIN_PB20, 3, 1)
+#define PIN_PB20__TIOB3			PINMUX_PIN(PIN_PB20, 4, 2)
+#define PIN_PB20__PCK1			PINMUX_PIN(PIN_PB20, 5, 4)
+#define PIN_PB20__GTX0			PINMUX_PIN(PIN_PB20, 6, 3)
+#define PIN_PB21			53
+#define PIN_PB21__GPIO			PINMUX_PIN(PIN_PB21, 0, 0)
+#define PIN_PB21__LCDDAT10		PINMUX_PIN(PIN_PB21, 1, 1)
+#define PIN_PB21__A10			PINMUX_PIN(PIN_PB21, 2, 1)
+#define PIN_PB21__TF0			PINMUX_PIN(PIN_PB21, 3, 1)
+#define PIN_PB21__TCLK3			PINMUX_PIN(PIN_PB21, 4, 2)
+#define PIN_PB21__FLEXCOM3_IO2		PINMUX_PIN(PIN_PB21, 5, 3)
+#define PIN_PB21__GTX1			PINMUX_PIN(PIN_PB21, 6, 3)
+#define PIN_PB22			54
+#define PIN_PB22__GPIO			PINMUX_PIN(PIN_PB22, 0, 0)
+#define PIN_PB22__LCDDAT11		PINMUX_PIN(PIN_PB22, 1, 1)
+#define PIN_PB22__A11			PINMUX_PIN(PIN_PB22, 2, 1)
+#define PIN_PB22__TD0			PINMUX_PIN(PIN_PB22, 3, 1)
+#define PIN_PB22__TIOA2			PINMUX_PIN(PIN_PB22, 4, 2)
+#define PIN_PB22__FLEXCOM3_IO1		PINMUX_PIN(PIN_PB22, 5, 3)
+#define PIN_PB22__GMDC			PINMUX_PIN(PIN_PB22, 6, 3)
+#define PIN_PB23			55
+#define PIN_PB23__GPIO			PINMUX_PIN(PIN_PB23, 0, 0)
+#define PIN_PB23__LCDDAT12		PINMUX_PIN(PIN_PB23, 1, 1)
+#define PIN_PB23__A12			PINMUX_PIN(PIN_PB23, 2, 1)
+#define PIN_PB23__RD0			PINMUX_PIN(PIN_PB23, 3, 1)
+#define PIN_PB23__TIOB2			PINMUX_PIN(PIN_PB23, 4, 2)
+#define PIN_PB23__FLEXCOM3_IO0		PINMUX_PIN(PIN_PB23, 5, 3)
+#define PIN_PB23__GMDIO			PINMUX_PIN(PIN_PB23, 6, 3)
+#define PIN_PB24			56
+#define PIN_PB24__GPIO			PINMUX_PIN(PIN_PB24, 0, 0)
+#define PIN_PB24__LCDDAT13		PINMUX_PIN(PIN_PB24, 1, 1)
+#define PIN_PB24__A13			PINMUX_PIN(PIN_PB24, 2, 1)
+#define PIN_PB24__RK0			PINMUX_PIN(PIN_PB24, 3, 1)
+#define PIN_PB24__TCLK2			PINMUX_PIN(PIN_PB24, 4, 2)
+#define PIN_PB24__FLEXCOM3_IO3		PINMUX_PIN(PIN_PB24, 5, 3)
+#define PIN_PB24__ISC_D10		PINMUX_PIN(PIN_PB24, 6, 3)
+#define PIN_PB25			57
+#define PIN_PB25__GPIO			PINMUX_PIN(PIN_PB25, 0, 0)
+#define PIN_PB25__LCDDAT14		PINMUX_PIN(PIN_PB25, 1, 1)
+#define PIN_PB25__A14			PINMUX_PIN(PIN_PB25, 2, 1)
+#define PIN_PB25__RF0			PINMUX_PIN(PIN_PB25, 3, 1)
+#define PIN_PB25__FLEXCOM3_IO4		PINMUX_PIN(PIN_PB25, 5, 3)
+#define PIN_PB25__ISC_D11		PINMUX_PIN(PIN_PB25, 6, 3)
+#define PIN_PB26			58
+#define PIN_PB26__GPIO			PINMUX_PIN(PIN_PB26, 0, 0)
+#define PIN_PB26__LCDDAT15		PINMUX_PIN(PIN_PB26, 1, 1)
+#define PIN_PB26__A15			PINMUX_PIN(PIN_PB26, 2, 1)
+#define PIN_PB26__URXD0			PINMUX_PIN(PIN_PB26, 3, 1)
+#define PIN_PB26__PDMIC_DAT		PINMUX_PIN(PIN_PB26, 4, 1)
+#define PIN_PB26__ISC_D0		PINMUX_PIN(PIN_PB26, 6, 3)
+#define PIN_PB27			59
+#define PIN_PB27__GPIO			PINMUX_PIN(PIN_PB27, 0, 0)
+#define PIN_PB27__LCDDAT16		PINMUX_PIN(PIN_PB27, 1, 1)
+#define PIN_PB27__A16			PINMUX_PIN(PIN_PB27, 2, 1)
+#define PIN_PB27__UTXD0			PINMUX_PIN(PIN_PB27, 3, 1)
+#define PIN_PB27__PDMIC_CLK		PINMUX_PIN(PIN_PB27, 4, 1)
+#define PIN_PB27__ISC_D1		PINMUX_PIN(PIN_PB27, 6, 3)
+#define PIN_PB28			60
+#define PIN_PB28__GPIO			PINMUX_PIN(PIN_PB28, 0, 0)
+#define PIN_PB28__LCDDAT17		PINMUX_PIN(PIN_PB28, 1, 1)
+#define PIN_PB28__A17			PINMUX_PIN(PIN_PB28, 2, 1)
+#define PIN_PB28__FLEXCOM0_IO0		PINMUX_PIN(PIN_PB28, 3, 1)
+#define PIN_PB28__TIOA5			PINMUX_PIN(PIN_PB28, 4, 2)
+#define PIN_PB28__ISC_D2		PINMUX_PIN(PIN_PB28, 6, 3)
+#define PIN_PB29			61
+#define PIN_PB29__GPIO			PINMUX_PIN(PIN_PB29, 0, 0)
+#define PIN_PB29__LCDDAT18		PINMUX_PIN(PIN_PB29, 1, 1)
+#define PIN_PB29__A18			PINMUX_PIN(PIN_PB29, 2, 1)
+#define PIN_PB29__FLEXCOM0_IO1		PINMUX_PIN(PIN_PB29, 3, 1)
+#define PIN_PB29__TIOB5			PINMUX_PIN(PIN_PB29, 4, 2)
+#define PIN_PB29__ISC_D3		PINMUX_PIN(PIN_PB29, 7, 3)
+#define PIN_PB30			62
+#define PIN_PB30__GPIO			PINMUX_PIN(PIN_PB30, 0, 0)
+#define PIN_PB30__LCDDAT19		PINMUX_PIN(PIN_PB30, 1, 1)
+#define PIN_PB30__A19			PINMUX_PIN(PIN_PB30, 2, 1)
+#define PIN_PB30__FLEXCOM0_IO2		PINMUX_PIN(PIN_PB30, 3, 1)
+#define PIN_PB30__TCLK5			PINMUX_PIN(PIN_PB30, 4, 2)
+#define PIN_PB30__ISC_D4		PINMUX_PIN(PIN_PB30, 6, 3)
+#define PIN_PB31			63
+#define PIN_PB31__GPIO			PINMUX_PIN(PIN_PB31, 0, 0)
+#define PIN_PB31__LCDDAT20		PINMUX_PIN(PIN_PB31, 1, 1)
+#define PIN_PB31__A20			PINMUX_PIN(PIN_PB31, 2, 1)
+#define PIN_PB31__FLEXCOM0_IO3		PINMUX_PIN(PIN_PB31, 3, 1)
+#define PIN_PB31__TWD0			PINMUX_PIN(PIN_PB31, 4, 1)
+#define PIN_PB31__ISC_D5		PINMUX_PIN(PIN_PB31, 6, 3)
+#define PIN_PC0				64
+#define PIN_PC0__GPIO			PINMUX_PIN(PIN_PC0, 0, 0)
+#define PIN_PC0__LCDDAT21		PINMUX_PIN(PIN_PC0, 1, 1)
+#define PIN_PC0__A23			PINMUX_PIN(PIN_PC0, 2, 1)
+#define PIN_PC0__FLEXCOM0_IO4		PINMUX_PIN(PIN_PC0, 3, 1)
+#define PIN_PC0__TWCK0			PINMUX_PIN(PIN_PC0, 4, 1)
+#define PIN_PC0__ISC_D6			PINMUX_PIN(PIN_PC0, 6, 3)
+#define PIN_PC1				65
+#define PIN_PC1__GPIO			PINMUX_PIN(PIN_PC1, 0, 0)
+#define PIN_PC1__LCDDAT22		PINMUX_PIN(PIN_PC1, 1, 1)
+#define PIN_PC1__A24			PINMUX_PIN(PIN_PC1, 2, 1)
+#define PIN_PC1__CANTX0			PINMUX_PIN(PIN_PC1, 3, 1)
+#define PIN_PC1__SPI1_SPCK		PINMUX_PIN(PIN_PC1, 4, 1)
+#define PIN_PC1__I2SC0_CK		PINMUX_PIN(PIN_PC1, 5, 1)
+#define PIN_PC1__ISC_D7			PINMUX_PIN(PIN_PC1, 6, 3)
+#define PIN_PC2				66
+#define PIN_PC2__GPIO			PINMUX_PIN(PIN_PC2, 0, 0)
+#define PIN_PC2__LCDDAT23		PINMUX_PIN(PIN_PC2, 1, 1)
+#define PIN_PC2__A25			PINMUX_PIN(PIN_PC2, 2, 1)
+#define PIN_PC2__CANRX0			PINMUX_PIN(PIN_PC2, 3, 1)
+#define PIN_PC2__SPI1_MOSI		PINMUX_PIN(PIN_PC2, 4, 1)
+#define PIN_PC2__I2SC0_MCK		PINMUX_PIN(PIN_PC2, 5, 1)
+#define PIN_PC2__ISC_D8			PINMUX_PIN(PIN_PC2, 6, 3)
+#define PIN_PC3				67
+#define PIN_PC3__GPIO			PINMUX_PIN(PIN_PC3, 0, 0)
+#define PIN_PC3__LCDPWM			PINMUX_PIN(PIN_PC3, 1, 1)
+#define PIN_PC3__NWAIT			PINMUX_PIN(PIN_PC3, 2, 1)
+#define PIN_PC3__TIOA1			PINMUX_PIN(PIN_PC3, 3, 1)
+#define PIN_PC3__SPI1_MISO		PINMUX_PIN(PIN_PC3, 4, 1)
+#define PIN_PC3__I2SC0_WS		PINMUX_PIN(PIN_PC3, 5, 1)
+#define PIN_PC3__ISC_D9			PINMUX_PIN(PIN_PC3, 6, 3)
+#define PIN_PC4				68
+#define PIN_PC4__GPIO			PINMUX_PIN(PIN_PC4, 0, 0)
+#define PIN_PC4__LCDDISP		PINMUX_PIN(PIN_PC4, 1, 1)
+#define PIN_PC4__NWR1_NBS1		PINMUX_PIN(PIN_PC4, 2, 1)
+#define PIN_PC4__TIOB1			PINMUX_PIN(PIN_PC4, 3, 1)
+#define PIN_PC4__SPI1_NPCS0		PINMUX_PIN(PIN_PC4, 4, 1)
+#define PIN_PC4__I2SC0_DI0		PINMUX_PIN(PIN_PC4, 5, 1)
+#define PIN_PC4__ISC_PCK		PINMUX_PIN(PIN_PC4, 6, 3)
+#define PIN_PC5				69
+#define PIN_PC5__GPIO			PINMUX_PIN(PIN_PC5, 0, 0)
+#define PIN_PC5__LCDVSYNC		PINMUX_PIN(PIN_PC5, 1, 1)
+#define PIN_PC5__NCS0			PINMUX_PIN(PIN_PC5, 2, 1)
+#define PIN_PC5__TCLK1			PINMUX_PIN(PIN_PC5, 3, 1)
+#define PIN_PC5__SPI1_NPCS1		PINMUX_PIN(PIN_PC5, 4, 1)
+#define PIN_PC5__I2SC0_DO0		PINMUX_PIN(PIN_PC5, 5, 1)
+#define PIN_PC5__ISC_VSYNC		PINMUX_PIN(PIN_PC5, 6, 3)
+#define PIN_PC6				70
+#define PIN_PC6__GPIO			PINMUX_PIN(PIN_PC6, 0, 0)
+#define PIN_PC6__LCDHSYNC		PINMUX_PIN(PIN_PC6, 1, 1)
+#define PIN_PC6__NCS1			PINMUX_PIN(PIN_PC6, 2, 1)
+#define PIN_PC6__TWD1			PINMUX_PIN(PIN_PC6, 3, 1)
+#define PIN_PC6__SPI1_NPCS2		PINMUX_PIN(PIN_PC6, 4, 1)
+#define PIN_PC6__ISC_HSYNC		PINMUX_PIN(PIN_PC6, 6, 3)
+#define PIN_PC7				71
+#define PIN_PC7__GPIO			PINMUX_PIN(PIN_PC7, 0, 0)
+#define PIN_PC7__LCDPCK			PINMUX_PIN(PIN_PC7, 1, 1)
+#define PIN_PC7__NCS2			PINMUX_PIN(PIN_PC7, 2, 1)
+#define PIN_PC7__TWCK1			PINMUX_PIN(PIN_PC7, 3, 1)
+#define PIN_PC7__SPI1_NPCS3		PINMUX_PIN(PIN_PC7, 4, 1)
+#define PIN_PC7__URXD1			PINMUX_PIN(PIN_PC7, 5, 2)
+#define PIN_PC7__ISC_MCK		PINMUX_PIN(PIN_PC7, 6, 3)
+#define PIN_PC8				72
+#define PIN_PC8__GPIO			PINMUX_PIN(PIN_PC8, 0, 0)
+#define PIN_PC8__LCDDEN			PINMUX_PIN(PIN_PC8, 1, 1)
+#define PIN_PC8__NANDRDY		PINMUX_PIN(PIN_PC8, 2, 1)
+#define PIN_PC8__FIQ			PINMUX_PIN(PIN_PC8, 3, 1)
+#define PIN_PC8__PCK0			PINMUX_PIN(PIN_PC8, 4, 3)
+#define PIN_PC8__UTXD1			PINMUX_PIN(PIN_PC8, 5, 2)
+#define PIN_PC8__ISC_FIELD		PINMUX_PIN(PIN_PC8, 6, 3)
+#define PIN_PC9				73
+#define PIN_PC9__GPIO			PINMUX_PIN(PIN_PC9, 0, 0)
+#define PIN_PC9__FIQ			PINMUX_PIN(PIN_PC9, 1, 3)
+#define PIN_PC9__GTSUCOMP		PINMUX_PIN(PIN_PC9, 2, 1)
+#define PIN_PC9__ISC_D0			PINMUX_PIN(PIN_PC9, 3, 1)
+#define PIN_PC9__TIOA4			PINMUX_PIN(PIN_PC9, 4, 2)
+#define PIN_PC10			74
+#define PIN_PC10__GPIO			PINMUX_PIN(PIN_PC10, 0, 0)
+#define PIN_PC10__LCDDAT2		PINMUX_PIN(PIN_PC10, 1, 2)
+#define PIN_PC10__GTXCK			PINMUX_PIN(PIN_PC10, 2, 1)
+#define PIN_PC10__ISC_D1		PINMUX_PIN(PIN_PC10, 3, 1)
+#define PIN_PC10__TIOB4			PINMUX_PIN(PIN_PC10, 4, 2)
+#define PIN_PC10__CANTX0		PINMUX_PIN(PIN_PC10, 5, 2)
+#define PIN_PC11			75
+#define PIN_PC11__GPIO			PINMUX_PIN(PIN_PC11, 0, 0)
+#define PIN_PC11__LCDDAT3		PINMUX_PIN(PIN_PC11, 1, 2)
+#define PIN_PC11__GTXEN			PINMUX_PIN(PIN_PC11, 2, 1)
+#define PIN_PC11__ISC_D2		PINMUX_PIN(PIN_PC11, 3, 1)
+#define PIN_PC11__TCLK4			PINMUX_PIN(PIN_PC11, 4, 2)
+#define PIN_PC11__CANRX0		PINMUX_PIN(PIN_PC11, 5, 2)
+#define PIN_PC11__A0_NBS0		PINMUX_PIN(PIN_PC11, 6, 2)
+#define PIN_PC12			76
+#define PIN_PC12__GPIO			PINMUX_PIN(PIN_PC12, 0, 0)
+#define PIN_PC12__LCDDAT4		PINMUX_PIN(PIN_PC12, 1, 2)
+#define PIN_PC12__GRXDV			PINMUX_PIN(PIN_PC12, 2, 1)
+#define PIN_PC12__ISC_D3		PINMUX_PIN(PIN_PC12, 3, 1)
+#define PIN_PC12__URXD3			PINMUX_PIN(PIN_PC12, 4, 1)
+#define PIN_PC12__TK0			PINMUX_PIN(PIN_PC12, 5, 2)
+#define PIN_PC12__A1			PINMUX_PIN(PIN_PC12, 6, 2)
+#define PIN_PC13			77
+#define PIN_PC13__GPIO			PINMUX_PIN(PIN_PC13, 0, 0)
+#define PIN_PC13__LCDDAT5		PINMUX_PIN(PIN_PC13, 1, 2)
+#define PIN_PC13__GRXER			PINMUX_PIN(PIN_PC13, 2, 1)
+#define PIN_PC13__ISC_D4		PINMUX_PIN(PIN_PC13, 3, 1)
+#define PIN_PC13__UTXD3			PINMUX_PIN(PIN_PC13, 4, 1)
+#define PIN_PC13__TF0			PINMUX_PIN(PIN_PC13, 5, 2)
+#define PIN_PC13__A2			PINMUX_PIN(PIN_PC13, 6, 2)
+#define PIN_PC14			78
+#define PIN_PC14__GPIO			PINMUX_PIN(PIN_PC14, 0, 0)
+#define PIN_PC14__LCDDAT6		PINMUX_PIN(PIN_PC14, 1, 2)
+#define PIN_PC14__GRX0			PINMUX_PIN(PIN_PC14, 2, 1)
+#define PIN_PC14__ISC_D5		PINMUX_PIN(PIN_PC14, 3, 1)
+#define PIN_PC14__TD0			PINMUX_PIN(PIN_PC14, 5, 2)
+#define PIN_PC14__A3			PINMUX_PIN(PIN_PC14, 6, 2)
+#define PIN_PC15			79
+#define PIN_PC15__GPIO			PINMUX_PIN(PIN_PC15, 0, 0)
+#define PIN_PC15__LCDDAT7		PINMUX_PIN(PIN_PC15, 1, 2)
+#define PIN_PC15__GRX1			PINMUX_PIN(PIN_PC15, 2, 1)
+#define PIN_PC15__ISC_D6		PINMUX_PIN(PIN_PC15, 3, 1)
+#define PIN_PC15__RD0			PINMUX_PIN(PIN_PC15, 5, 2)
+#define PIN_PC15__A4			PINMUX_PIN(PIN_PC15, 6, 2)
+#define PIN_PC16			80
+#define PIN_PC16__GPIO			PINMUX_PIN(PIN_PC16, 0, 0)
+#define PIN_PC16__LCDDAT10		PINMUX_PIN(PIN_PC16, 1, 2)
+#define PIN_PC16__GTX0			PINMUX_PIN(PIN_PC16, 2, 1)
+#define PIN_PC16__ISC_D7		PINMUX_PIN(PIN_PC16, 3, 1)
+#define PIN_PC16__RK0			PINMUX_PIN(PIN_PC16, 5, 2)
+#define PIN_PC16__A5			PINMUX_PIN(PIN_PC16, 6, 2)
+#define PIN_PC17			81
+#define PIN_PC17__GPIO			PINMUX_PIN(PIN_PC17, 0, 0)
+#define PIN_PC17__LCDDAT11		PINMUX_PIN(PIN_PC17, 1, 2)
+#define PIN_PC17__GTX1			PINMUX_PIN(PIN_PC17, 2, 1)
+#define PIN_PC17__ISC_D8		PINMUX_PIN(PIN_PC17, 3, 1)
+#define PIN_PC17__RF0			PINMUX_PIN(PIN_PC17, 5, 2)
+#define PIN_PC17__A6			PINMUX_PIN(PIN_PC17, 6, 2)
+#define PIN_PC18			82
+#define PIN_PC18__GPIO			PINMUX_PIN(PIN_PC18, 0, 0)
+#define PIN_PC18__LCDDAT12		PINMUX_PIN(PIN_PC18, 1, 2)
+#define PIN_PC18__GMDC			PINMUX_PIN(PIN_PC18, 2, 1)
+#define PIN_PC18__ISC_D9		PINMUX_PIN(PIN_PC18, 3, 1)
+#define PIN_PC18__FLEXCOM3_IO2		PINMUX_PIN(PIN_PC18, 5, 2)
+#define PIN_PC18__A7			PINMUX_PIN(PIN_PC18, 6, 2)
+#define PIN_PC19			83
+#define PIN_PC19__GPIO			PINMUX_PIN(PIN_PC19, 0, 0)
+#define PIN_PC19__LCDDAT13		PINMUX_PIN(PIN_PC19, 1, 2)
+#define PIN_PC19__GMDIO			PINMUX_PIN(PIN_PC19, 2, 1)
+#define PIN_PC19__ISC_D10		PINMUX_PIN(PIN_PC19, 3, 1)
+#define PIN_PC19__FLEXCOM3_IO1		PINMUX_PIN(PIN_PC19, 5, 2)
+#define PIN_PC19__A8			PINMUX_PIN(PIN_PC19, 6, 2)
+#define PIN_PC20			84
+#define PIN_PC20__GPIO			PINMUX_PIN(PIN_PC20, 0, 0)
+#define PIN_PC20__LCDDAT14		PINMUX_PIN(PIN_PC20, 1, 2)
+#define PIN_PC20__GRXCK			PINMUX_PIN(PIN_PC20, 2, 1)
+#define PIN_PC20__ISC_D11		PINMUX_PIN(PIN_PC20, 3, 1)
+#define PIN_PC20__FLEXCOM3_IO0		PINMUX_PIN(PIN_PC20, 5, 2)
+#define PIN_PC20__A9			PINMUX_PIN(PIN_PC20, 6, 2)
+#define PIN_PC21			85
+#define PIN_PC21__GPIO			PINMUX_PIN(PIN_PC21, 0, 0)
+#define PIN_PC21__LCDDAT15		PINMUX_PIN(PIN_PC21, 1, 2)
+#define PIN_PC21__GTXER			PINMUX_PIN(PIN_PC21, 2, 1)
+#define PIN_PC21__ISC_PCK		PINMUX_PIN(PIN_PC21, 3, 1)
+#define PIN_PC21__FLEXCOM3_IO3		PINMUX_PIN(PIN_PC21, 5, 2)
+#define PIN_PC21__A10			PINMUX_PIN(PIN_PC21, 6, 2)
+#define PIN_PC22			86
+#define PIN_PC22__GPIO			PINMUX_PIN(PIN_PC22, 0, 0)
+#define PIN_PC22__LCDDAT18		PINMUX_PIN(PIN_PC22, 1, 2)
+#define PIN_PC22__GCRS			PINMUX_PIN(PIN_PC22, 2, 1)
+#define PIN_PC22__ISC_VSYNC		PINMUX_PIN(PIN_PC22, 3, 1)
+#define PIN_PC22__FLEXCOM3_IO4		PINMUX_PIN(PIN_PC22, 5, 2)
+#define PIN_PC22__A11			PINMUX_PIN(PIN_PC22, 6, 2)
+#define PIN_PC23			87
+#define PIN_PC23__GPIO			PINMUX_PIN(PIN_PC23, 0, 0)
+#define PIN_PC23__LCDDAT19		PINMUX_PIN(PIN_PC23, 1, 2)
+#define PIN_PC23__GCOL			PINMUX_PIN(PIN_PC23, 2, 1)
+#define PIN_PC23__ISC_HSYNC		PINMUX_PIN(PIN_PC23, 3, 1)
+#define PIN_PC23__A12			PINMUX_PIN(PIN_PC23, 6, 2)
+#define PIN_PC24			88
+#define PIN_PC24__GPIO			PINMUX_PIN(PIN_PC24, 0, 0)
+#define PIN_PC24__LCDDAT20		PINMUX_PIN(PIN_PC24, 1, 2)
+#define PIN_PC24__GRX2			PINMUX_PIN(PIN_PC24, 2, 1)
+#define PIN_PC24__ISC_MCK		PINMUX_PIN(PIN_PC24, 3, 1)
+#define PIN_PC24__A13			PINMUX_PIN(PIN_PC24, 6, 2)
+#define PIN_PC25			89
+#define PIN_PC25__GPIO			PINMUX_PIN(PIN_PC25, 0, 0)
+#define PIN_PC25__LCDDAT21		PINMUX_PIN(PIN_PC25, 1, 2)
+#define PIN_PC25__GRX3			PINMUX_PIN(PIN_PC25, 2, 1)
+#define PIN_PC25__ISC_FIELD		PINMUX_PIN(PIN_PC25, 3, 1)
+#define PIN_PC25__A14			PINMUX_PIN(PIN_PC25, 6, 2)
+#define PIN_PC26			90
+#define PIN_PC26__GPIO			PINMUX_PIN(PIN_PC26, 0, 0)
+#define PIN_PC26__LCDDAT22		PINMUX_PIN(PIN_PC26, 1, 2)
+#define PIN_PC26__GTX2			PINMUX_PIN(PIN_PC26, 2, 1)
+#define PIN_PC26__CANTX1		PINMUX_PIN(PIN_PC26, 4, 1)
+#define PIN_PC26__A15			PINMUX_PIN(PIN_PC26, 6, 2)
+#define PIN_PC27			91
+#define PIN_PC27__GPIO			PINMUX_PIN(PIN_PC27, 0, 0)
+#define PIN_PC27__LCDDAT23		PINMUX_PIN(PIN_PC27, 1, 2)
+#define PIN_PC27__GTX3			PINMUX_PIN(PIN_PC27, 2, 1)
+#define PIN_PC27__PCK1			PINMUX_PIN(PIN_PC27, 3, 2)
+#define PIN_PC27__CANRX1		PINMUX_PIN(PIN_PC27, 4, 1)
+#define PIN_PC27__TWD0			PINMUX_PIN(PIN_PC27, 5, 2)
+#define PIN_PC27__A16			PINMUX_PIN(PIN_PC27, 6, 2)
+#define PIN_PC28			92
+#define PIN_PC28__GPIO			PINMUX_PIN(PIN_PC28, 0, 0)
+#define PIN_PC28__LCDPWM		PINMUX_PIN(PIN_PC28, 1, 2)
+#define PIN_PC28__FLEXCOM4_IO0		PINMUX_PIN(PIN_PC28, 2, 1)
+#define PIN_PC28__PCK2			PINMUX_PIN(PIN_PC28, 3, 2)
+#define PIN_PC28__TWCK0			PINMUX_PIN(PIN_PC28, 5, 2)
+#define PIN_PC28__A17			PINMUX_PIN(PIN_PC28, 6, 2)
+#define PIN_PC29			93
+#define PIN_PC29__GPIO			PINMUX_PIN(PIN_PC29, 0, 0)
+#define PIN_PC29__LCDDISP		PINMUX_PIN(PIN_PC29, 1, 2)
+#define PIN_PC29__FLEXCOM4_IO1		PINMUX_PIN(PIN_PC29, 2, 1)
+#define PIN_PC29__A18			PINMUX_PIN(PIN_PC29, 6, 2)
+#define PIN_PC30			94
+#define PIN_PC30__GPIO			PINMUX_PIN(PIN_PC30, 0, 0)
+#define PIN_PC30__LCDVSYNC		PINMUX_PIN(PIN_PC30, 1, 2)
+#define PIN_PC30__FLEXCOM4_IO2		PINMUX_PIN(PIN_PC30, 2, 1)
+#define PIN_PC30__A19			PINMUX_PIN(PIN_PC30, 6, 2)
+#define PIN_PC31			95
+#define PIN_PC31__GPIO			PINMUX_PIN(PIN_PC31, 0, 0)
+#define PIN_PC31__LCDHSYNC		PINMUX_PIN(PIN_PC31, 1, 2)
+#define PIN_PC31__FLEXCOM4_IO3		PINMUX_PIN(PIN_PC31, 2, 1)
+#define PIN_PC31__URXD3			PINMUX_PIN(PIN_PC31, 3, 2)
+#define PIN_PC31__A20			PINMUX_PIN(PIN_PC31, 6, 2)
+#define PIN_PD0				96
+#define PIN_PD0__GPIO			PINMUX_PIN(PIN_PD0, 0, 0)
+#define PIN_PD0__LCDPCK			PINMUX_PIN(PIN_PD0, 1, 2)
+#define PIN_PD0__FLEXCOM4_IO4		PINMUX_PIN(PIN_PD0, 2, 1)
+#define PIN_PD0__UTXD3			PINMUX_PIN(PIN_PD0, 3, 2)
+#define PIN_PD0__GTSUCOMP		PINMUX_PIN(PIN_PD0, 4, 2)
+#define PIN_PD0__A23			PINMUX_PIN(PIN_PD0, 6, 2)
+#define PIN_PD1				97
+#define PIN_PD1__GPIO			PINMUX_PIN(PIN_PD1, 0, 0)
+#define PIN_PD1__LCDDEN			PINMUX_PIN(PIN_PD1, 1, 2)
+#define PIN_PD1__GRXCK			PINMUX_PIN(PIN_PD1, 4, 2)
+#define PIN_PD1__A24			PINMUX_PIN(PIN_PD1, 6, 2)
+#define PIN_PD2				98
+#define PIN_PD2__GPIO			PINMUX_PIN(PIN_PD2, 0, 0)
+#define PIN_PD2__URXD1			PINMUX_PIN(PIN_PD2, 1, 1)
+#define PIN_PD2__GTXER			PINMUX_PIN(PIN_PD2, 4, 2)
+#define PIN_PD2__ISC_MCK		PINMUX_PIN(PIN_PD2, 5, 2)
+#define PIN_PD2__A25			PINMUX_PIN(PIN_PD2, 6, 2)
+#define PIN_PD3				99
+#define PIN_PD3__GPIO			PINMUX_PIN(PIN_PD3, 0, 0)
+#define PIN_PD3__UTXD1			PINMUX_PIN(PIN_PD3, 1, 1)
+#define PIN_PD3__FIQ			PINMUX_PIN(PIN_PD3, 2, 2)
+#define PIN_PD3__GCRS			PINMUX_PIN(PIN_PD3, 4, 2)
+#define PIN_PD3__ISC_D11		PINMUX_PIN(PIN_PD3, 5, 2)
+#define PIN_PD3__NWAIT			PINMUX_PIN(PIN_PD3, 6, 2)
+#define PIN_PD4				100
+#define PIN_PD4__GPIO			PINMUX_PIN(PIN_PD4, 0, 0)
+#define PIN_PD4__TWD1			PINMUX_PIN(PIN_PD4, 1, 2)
+#define PIN_PD4__URXD2			PINMUX_PIN(PIN_PD4, 2, 1)
+#define PIN_PD4__GCOL			PINMUX_PIN(PIN_PD4, 4, 2)
+#define PIN_PD4__ISC_D10		PINMUX_PIN(PIN_PD4, 5, 2)
+#define PIN_PD4__NCS0			PINMUX_PIN(PIN_PD4, 6, 2)
+#define PIN_PD5				101
+#define PIN_PD5__GPIO			PINMUX_PIN(PIN_PD5, 0, 0)
+#define PIN_PD5__TWCK1			PINMUX_PIN(PIN_PD5, 1, 2)
+#define PIN_PD5__UTXD2			PINMUX_PIN(PIN_PD5, 2, 1)
+#define PIN_PD5__GRX2			PINMUX_PIN(PIN_PD5, 4, 2)
+#define PIN_PD5__ISC_D9			PINMUX_PIN(PIN_PD5, 5, 2)
+#define PIN_PD5__NCS1			PINMUX_PIN(PIN_PD5, 6, 2)
+#define PIN_PD6				102
+#define PIN_PD6__GPIO			PINMUX_PIN(PIN_PD6, 0, 0)
+#define PIN_PD6__TCK			PINMUX_PIN(PIN_PD6, 1, 2)
+#define PIN_PD6__PCK1			PINMUX_PIN(PIN_PD6, 2, 1)
+#define PIN_PD6__GRX3			PINMUX_PIN(PIN_PD6, 4, 2)
+#define PIN_PD6__ISC_D8			PINMUX_PIN(PIN_PD6, 5, 2)
+#define PIN_PD6__NCS2			PINMUX_PIN(PIN_PD6, 6, 2)
+#define PIN_PD7				103
+#define PIN_PD7__GPIO			PINMUX_PIN(PIN_PD7, 0, 0)
+#define PIN_PD7__TDI			PINMUX_PIN(PIN_PD7, 1, 2)
+#define PIN_PD7__UTMI_RXVAL		PINMUX_PIN(PIN_PD7, 3, 1)
+#define PIN_PD7__GTX2			PINMUX_PIN(PIN_PD7, 4, 2)
+#define PIN_PD7__ISC_D0			PINMUX_PIN(PIN_PD7, 5, 2)
+#define PIN_PD7__NWR1_NBS1		PINMUX_PIN(PIN_PD7, 6, 2)
+#define PIN_PD8				104
+#define PIN_PD8__GPIO			PINMUX_PIN(PIN_PD8, 0, 0)
+#define PIN_PD8__TDO			PINMUX_PIN(PIN_PD8, 1, 2)
+#define PIN_PD8__UTMI_RXERR		PINMUX_PIN(PIN_PD8, 3, 1)
+#define PIN_PD8__GTX3			PINMUX_PIN(PIN_PD8, 4, 2)
+#define PIN_PD8__ISC_D1			PINMUX_PIN(PIN_PD8, 5, 2)
+#define PIN_PD8__NANDRDY		PINMUX_PIN(PIN_PD8, 6, 2)
+#define PIN_PD9				105
+#define PIN_PD9__GPIO			PINMUX_PIN(PIN_PD9, 0, 0)
+#define PIN_PD9__TMS			PINMUX_PIN(PIN_PD9, 1, 2)
+#define PIN_PD9__UTMI_RXACT		PINMUX_PIN(PIN_PD9, 3, 1)
+#define PIN_PD9__GTXCK			PINMUX_PIN(PIN_PD9, 4, 2)
+#define PIN_PD9__ISC_D2			PINMUX_PIN(PIN_PD9, 5, 2)
+#define PIN_PD10			106
+#define PIN_PD10__GPIO			PINMUX_PIN(PIN_PD10, 0, 0)
+#define PIN_PD10__NTRST			PINMUX_PIN(PIN_PD10, 1, 2)
+#define PIN_PD10__UTMI_HDIS		PINMUX_PIN(PIN_PD10, 3, 1)
+#define PIN_PD10__GTXEN			PINMUX_PIN(PIN_PD10, 4, 2)
+#define PIN_PD10__ISC_D3		PINMUX_PIN(PIN_PD10, 5, 2)
+#define PIN_PD11			107
+#define PIN_PD11__GPIO			PINMUX_PIN(PIN_PD11, 0, 0)
+#define PIN_PD11__TIOA1			PINMUX_PIN(PIN_PD11, 1, 3)
+#define PIN_PD11__PCK2			PINMUX_PIN(PIN_PD11, 2, 2)
+#define PIN_PD11__UTMI_LS0		PINMUX_PIN(PIN_PD11, 3, 1)
+#define PIN_PD11__GRXDV			PINMUX_PIN(PIN_PD11, 4, 2)
+#define PIN_PD11__ISC_D4		PINMUX_PIN(PIN_PD11, 5, 2)
+#define PIN_PD11__ISC_MCK		PINMUX_PIN(PIN_PD11, 7, 4)
+#define PIN_PD12			108
+#define PIN_PD12__GPIO			PINMUX_PIN(PIN_PD12, 0, 0)
+#define PIN_PD12__TIOB1			PINMUX_PIN(PIN_PD12, 1, 3)
+#define PIN_PD12__FLEXCOM4_IO0		PINMUX_PIN(PIN_PD12, 2, 2)
+#define PIN_PD12__UTMI_LS1		PINMUX_PIN(PIN_PD12, 3, 1)
+#define PIN_PD12__GRXER			PINMUX_PIN(PIN_PD12, 4, 2)
+#define PIN_PD12__ISC_D5		PINMUX_PIN(PIN_PD12, 5, 2)
+#define PIN_PD12__ISC_D4		PINMUX_PIN(PIN_PD12, 6, 4)
+#define PIN_PD13			109
+#define PIN_PD13__GPIO			PINMUX_PIN(PIN_PD13, 0, 0)
+#define PIN_PD13__TCLK1			PINMUX_PIN(PIN_PD13, 1, 3)
+#define PIN_PD13__FLEXCOM4_IO1		PINMUX_PIN(PIN_PD13, 2, 2)
+#define PIN_PD13__UTMI_CDRPCSEL0	PINMUX_PIN(PIN_PD13, 3, 1)
+#define PIN_PD13__GRX0			PINMUX_PIN(PIN_PD13, 4, 2)
+#define PIN_PD13__ISC_D6		PINMUX_PIN(PIN_PD13, 5, 2)
+#define PIN_PD13__ISC_D5		PINMUX_PIN(PIN_PD13, 6, 4)
+#define PIN_PD14			110
+#define PIN_PD14__GPIO			PINMUX_PIN(PIN_PD14, 0, 0)
+#define PIN_PD14__TCK			PINMUX_PIN(PIN_PD14, 1, 1)
+#define PIN_PD14__FLEXCOM4_IO2		PINMUX_PIN(PIN_PD14, 2, 2)
+#define PIN_PD14__UTMI_CDRPCSEL1	PINMUX_PIN(PIN_PD14, 3, 1)
+#define PIN_PD14__GRX1			PINMUX_PIN(PIN_PD14, 4, 2)
+#define PIN_PD14__ISC_D7		PINMUX_PIN(PIN_PD14, 5, 2)
+#define PIN_PD14__ISC_D6		PINMUX_PIN(PIN_PD14, 6, 4)
+#define PIN_PD15			111
+#define PIN_PD15__GPIO			PINMUX_PIN(PIN_PD15, 0, 0)
+#define PIN_PD15__TDI			PINMUX_PIN(PIN_PD15, 1, 1)
+#define PIN_PD15__FLEXCOM4_IO3		PINMUX_PIN(PIN_PD15, 2, 2)
+#define PIN_PD15__UTMI_CDRCPDIVEN	PINMUX_PIN(PIN_PD15, 3, 1)
+#define PIN_PD15__GTX0			PINMUX_PIN(PIN_PD15, 4, 2)
+#define PIN_PD15__ISC_PCK		PINMUX_PIN(PIN_PD15, 5, 2)
+#define PIN_PD15__ISC_D7		PINMUX_PIN(PIN_PD15, 6, 4)
+#define PIN_PD16			112
+#define PIN_PD16__GPIO			PINMUX_PIN(PIN_PD16, 0, 0)
+#define PIN_PD16__TDO			PINMUX_PIN(PIN_PD16, 1, 1)
+#define PIN_PD16__FLEXCOM4_IO4		PINMUX_PIN(PIN_PD16, 2, 2)
+#define PIN_PD16__UTMI_CDRBISTEN	PINMUX_PIN(PIN_PD16, 3, 1)
+#define PIN_PD16__GTX1			PINMUX_PIN(PIN_PD16, 4, 2)
+#define PIN_PD16__ISC_VSYNC		PINMUX_PIN(PIN_PD16, 5, 2)
+#define PIN_PD16__ISC_D8		PINMUX_PIN(PIN_PD16, 6, 4)
+#define PIN_PD17			113
+#define PIN_PD17__GPIO			PINMUX_PIN(PIN_PD17, 0, 0)
+#define PIN_PD17__TMS			PINMUX_PIN(PIN_PD17, 1, 1)
+#define PIN_PD17__UTMI_CDRCPSELDIV	PINMUX_PIN(PIN_PD17, 3, 1)
+#define PIN_PD17__GMDC			PINMUX_PIN(PIN_PD17, 4, 2)
+#define PIN_PD17__ISC_HSYNC		PINMUX_PIN(PIN_PD17, 5, 2)
+#define PIN_PD17__ISC_D9		PINMUX_PIN(PIN_PD17, 6, 4)
+#define PIN_PD18			114
+#define PIN_PD18__GPIO			PINMUX_PIN(PIN_PD18, 0, 0)
+#define PIN_PD18__NTRST			PINMUX_PIN(PIN_PD18, 1, 1)
+#define PIN_PD18__GMDIO			PINMUX_PIN(PIN_PD18, 4, 2)
+#define PIN_PD18__ISC_FIELD		PINMUX_PIN(PIN_PD18, 5, 2)
+#define PIN_PD18__ISC_D10		PINMUX_PIN(PIN_PD18, 6, 4)
+#define PIN_PD19			115
+#define PIN_PD19__GPIO			PINMUX_PIN(PIN_PD19, 0, 0)
+#define PIN_PD19__PCK0			PINMUX_PIN(PIN_PD19, 1, 1)
+#define PIN_PD19__TWD1			PINMUX_PIN(PIN_PD19, 2, 3)
+#define PIN_PD19__URXD2			PINMUX_PIN(PIN_PD19, 3, 3)
+#define PIN_PD19__I2SC0_CK		PINMUX_PIN(PIN_PD19, 5, 2)
+#define PIN_PD19__ISC_D11		PINMUX_PIN(PIN_PD19, 6, 4)
+#define PIN_PD20			116
+#define PIN_PD20__GPIO			PINMUX_PIN(PIN_PD20, 0, 0)
+#define PIN_PD20__TIOA2			PINMUX_PIN(PIN_PD20, 1, 3)
+#define PIN_PD20__TWCK1			PINMUX_PIN(PIN_PD20, 2, 3)
+#define PIN_PD20__UTXD2			PINMUX_PIN(PIN_PD20, 3, 3)
+#define PIN_PD20__I2SC0_MCK		PINMUX_PIN(PIN_PD20, 5, 2)
+#define PIN_PD20__ISC_PCK		PINMUX_PIN(PIN_PD20, 6, 4)
+#define PIN_PD21			117
+#define PIN_PD21__GPIO			PINMUX_PIN(PIN_PD21, 0, 0)
+#define PIN_PD21__TIOB2			PINMUX_PIN(PIN_PD21, 1, 3)
+#define PIN_PD21__TWD0			PINMUX_PIN(PIN_PD21, 2, 4)
+#define PIN_PD21__FLEXCOM4_IO0		PINMUX_PIN(PIN_PD21, 3, 3)
+#define PIN_PD21__I2SC0_WS		PINMUX_PIN(PIN_PD21, 5, 2)
+#define PIN_PD21__ISC_VSYNC		PINMUX_PIN(PIN_PD21, 6, 4)
+#define PIN_PD22			118
+#define PIN_PD22__GPIO			PINMUX_PIN(PIN_PD22, 0, 0)
+#define PIN_PD22__TCLK2			PINMUX_PIN(PIN_PD22, 1, 3)
+#define PIN_PD22__TWCK0			PINMUX_PIN(PIN_PD22, 2, 4)
+#define PIN_PD22__FLEXCOM4_IO1		PINMUX_PIN(PIN_PD22, 3, 3)
+#define PIN_PD22__I2SC0_DI0		PINMUX_PIN(PIN_PD22, 5, 2)
+#define PIN_PD22__ISC_HSYNC		PINMUX_PIN(PIN_PD22, 6, 4)
+#define PIN_PD23			119
+#define PIN_PD23__GPIO			PINMUX_PIN(PIN_PD23, 0, 0)
+#define PIN_PD23__URXD2			PINMUX_PIN(PIN_PD23, 1, 2)
+#define PIN_PD23__FLEXCOM4_IO2		PINMUX_PIN(PIN_PD23, 3, 3)
+#define PIN_PD23__I2SC0_DO0		PINMUX_PIN(PIN_PD23, 5, 2)
+#define PIN_PD23__ISC_FIELD		PINMUX_PIN(PIN_PD23, 6, 4)
+#define PIN_PD24			120
+#define PIN_PD24__GPIO			PINMUX_PIN(PIN_PD24, 0, 0)
+#define PIN_PD24__UTXD2			PINMUX_PIN(PIN_PD24, 1, 2)
+#define PIN_PD24__FLEXCOM4_IO3		PINMUX_PIN(PIN_PD24, 3, 3)
+#define PIN_PD25			121
+#define PIN_PD25__GPIO			PINMUX_PIN(PIN_PD25, 0, 0)
+#define PIN_PD25__SPI1_SPCK		PINMUX_PIN(PIN_PD25, 1, 3)
+#define PIN_PD25__FLEXCOM4_IO4		PINMUX_PIN(PIN_PD25, 3, 3)
+#define PIN_PD26			122
+#define PIN_PD26__GPIO			PINMUX_PIN(PIN_PD26, 0, 0)
+#define PIN_PD26__SPI1_MOSI		PINMUX_PIN(PIN_PD26, 1, 3)
+#define PIN_PD26__FLEXCOM2_IO0		PINMUX_PIN(PIN_PD26, 3, 2)
+#define PIN_PD27			123
+#define PIN_PD27__GPIO			PINMUX_PIN(PIN_PD27, 0, 0)
+#define PIN_PD27__SPI1_MISO		PINMUX_PIN(PIN_PD27, 1, 3)
+#define PIN_PD27__TCK			PINMUX_PIN(PIN_PD27, 2, 3)
+#define PIN_PD27__FLEXCOM2_IO1		PINMUX_PIN(PIN_PD27, 3, 2)
+#define PIN_PD28			124
+#define PIN_PD28__GPIO			PINMUX_PIN(PIN_PD28, 0, 0)
+#define PIN_PD28__SPI1_NPCS0		PINMUX_PIN(PIN_PD28, 1, 3)
+#define PIN_PD28__TCI			PINMUX_PIN(PIN_PD28, 2, 3)
+#define PIN_PD28__FLEXCOM2_IO2		PINMUX_PIN(PIN_PD28, 3, 2)
+#define PIN_PD29			125
+#define PIN_PD29__GPIO			PINMUX_PIN(PIN_PD29, 0, 0)
+#define PIN_PD29__SPI1_NPCS1		PINMUX_PIN(PIN_PD29, 1, 3)
+#define PIN_PD29__TDO			PINMUX_PIN(PIN_PD29, 2, 3)
+#define PIN_PD29__FLEXCOM2_IO3		PINMUX_PIN(PIN_PD29, 3, 2)
+#define PIN_PD29__TIOA3			PINMUX_PIN(PIN_PD29, 4, 3)
+#define PIN_PD29__TWD0			PINMUX_PIN(PIN_PD29, 5, 3)
+#define PIN_PD30			126
+#define PIN_PD30__GPIO			PINMUX_PIN(PIN_PD30, 0, 0)
+#define PIN_PD30__SPI1_NPCS2		PINMUX_PIN(PIN_PD30, 1, 3)
+#define PIN_PD30__TMS			PINMUX_PIN(PIN_PD30, 2, 3)
+#define PIN_PD30__FLEXCOM2_IO4		PINMUX_PIN(PIN_PD30, 3, 2)
+#define PIN_PD30__TIOB3			PINMUX_PIN(PIN_PD30, 4, 3)
+#define PIN_PD30__TWCK0			PINMUX_PIN(PIN_PD30, 5, 3)
+#define PIN_PD31			127
+#define PIN_PD31__GPIO			PINMUX_PIN(PIN_PD31, 0, 0)
+#define PIN_PD31__ADTRG			PINMUX_PIN(PIN_PD31, 1, 1)
+#define PIN_PD31__NTRST			PINMUX_PIN(PIN_PD31, 2, 3)
+#define PIN_PD31__IRQ			PINMUX_PIN(PIN_PD31, 3, 4)
+#define PIN_PD31__TCLK3			PINMUX_PIN(PIN_PD31, 4, 3)
+#define PIN_PD31__PCK0			PINMUX_PIN(PIN_PD31, 5, 2)
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/st-pincfg.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/st-pincfg.h
new file mode 100644
index 0000000000000000000000000000000000000000..d80551202292457fc38881a471cddad49c611e02
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/st-pincfg.h
@@ -0,0 +1,72 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef _ST_PINCFG_H_
+#define _ST_PINCFG_H_
+
+/* Alternate functions */
+#define ALT1	1
+#define ALT2	2
+#define ALT3	3
+#define ALT4	4
+#define ALT5	5
+#define ALT6	6
+#define ALT7	7
+
+/* Output enable */
+#define OE			(1 << 27)
+/* Pull Up */
+#define PU			(1 << 26)
+/* Open Drain */
+#define OD			(1 << 25)
+#define RT			(1 << 23)
+#define INVERTCLK		(1 << 22)
+#define CLKNOTDATA		(1 << 21)
+#define DOUBLE_EDGE		(1 << 20)
+#define CLK_A			(0 << 18)
+#define CLK_B			(1 << 18)
+#define CLK_C			(2 << 18)
+#define CLK_D			(3 << 18)
+
+/* User-frendly defines for Pin Direction */
+		/* oe = 0, pu = 0, od = 0 */
+#define IN			(0)
+		/* oe = 0, pu = 1, od = 0 */
+#define IN_PU			(PU)
+		/* oe = 1, pu = 0, od = 0 */
+#define OUT			(OE)
+		/* oe = 1, pu = 0, od = 1 */
+#define BIDIR			(OE | OD)
+		/* oe = 1, pu = 1, od = 1 */
+#define BIDIR_PU		(OE | PU | OD)
+
+/* RETIME_TYPE */
+/*
+ * B Mode
+ * Bypass retime with optional delay parameter
+ */
+#define BYPASS		(0)
+/*
+ * R0, R1, R0D, R1D modes
+ * single-edge data non inverted clock, retime data with clk
+ */
+#define SE_NICLK_IO	(RT)
+/*
+ * RIV0, RIV1, RIV0D, RIV1D modes
+ * single-edge data inverted clock, retime data with clk
+ */
+#define SE_ICLK_IO	(RT | INVERTCLK)
+/*
+ * R0E, R1E, R0ED, R1ED modes
+ * double-edge data, retime data with clk
+ */
+#define DE_IO		(RT | DOUBLE_EDGE)
+/*
+ * CIV0, CIV1 modes with inverted clock
+ * Retiming the clk pins will park clock & reduce the noise within the core.
+ */
+#define ICLK		(RT | CLKNOTDATA | INVERTCLK)
+/*
+ * CLK0, CLK1 modes with non-inverted clock
+ * Retiming the clk pins will park clock & reduce the noise within the core.
+ */
+#define NICLK		(RT | CLKNOTDATA)
+#endif /* _ST_PINCFG_H_ */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/vf610-pinfunc.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/vf610-pinfunc.h
new file mode 100644
index 0000000000000000000000000000000000000000..fcad7132c871f01e98a3a46dd66536f7945eaf75
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/include/vf610-pinfunc.h
@@ -0,0 +1,810 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __DTS_VF610_PINFUNC_H
+#define __DTS_VF610_PINFUNC_H
+
+/*
+ * The pin function ID for VF610 is a tuple of:
+ * <mux_reg input_reg mux_mode input_val>
+ */
+
+#define ALT0	0x0
+#define ALT1	0x1
+#define ALT2	0x2
+#define ALT3	0x3
+#define ALT4	0x4
+#define ALT5	0x5
+#define ALT6	0x6
+#define ALT7	0x7
+
+
+#define VF610_PAD_PTA6__GPIO_0			0x000 0x000 ALT0 0x0
+#define VF610_PAD_PTA6__RMII_CLKOUT		0x000 0x000 ALT1 0x0
+#define VF610_PAD_PTA6__RMII_CLKIN		0x000 0x2F0 ALT2 0x0
+#define VF610_PAD_PTA6__DCU1_TCON11		0x000 0x000 ALT4 0x0
+#define VF610_PAD_PTA6__DCU1_R2			0x000 0x000 ALT7 0x0
+#define VF610_PAD_PTA8__GPIO_1			0x004 0x000 ALT0 0x0
+#define VF610_PAD_PTA8__TCLK			0x004 0x000 ALT1 0x0
+#define VF610_PAD_PTA8__DCU0_R0			0x004 0x000 ALT4 0x0
+#define VF610_PAD_PTA8__MLB_CLK			0x004 0x354 ALT7 0x0
+#define VF610_PAD_PTA9__GPIO_2			0x008 0x000 ALT0 0x0
+#define VF610_PAD_PTA9__TDI			0x008 0x000 ALT1 0x0
+#define VF610_PAD_PTA9__RMII_CLKOUT		0x008 0x000 ALT2 0x0
+#define VF610_PAD_PTA9__RMII_CLKIN		0x008 0x2F0 ALT3 0x1
+#define VF610_PAD_PTA9__DCU0_R1			0x008 0x000 ALT4 0x0
+#define VF610_PAD_PTA9__WDOG_B			0x008 0x000 ALT6 0x0
+#define VF610_PAD_PTA10__GPIO_3			0x00C 0x000 ALT0 0x0
+#define VF610_PAD_PTA10__TDO			0x00C 0x000 ALT1 0x0
+#define VF610_PAD_PTA10__EXT_AUDIO_MCLK		0x00C 0x2EC ALT2 0x0
+#define VF610_PAD_PTA10__DCU0_G0		0x00C 0x000 ALT4 0x0
+#define VF610_PAD_PTA10__ENET_TS_CLKIN		0x00C 0x2F4 ALT6 0x0
+#define VF610_PAD_PTA10__MLB_SIGNAL		0x00C 0x35C ALT7 0x0
+#define VF610_PAD_PTA11__GPIO_4			0x010 0x000 ALT0 0x0
+#define VF610_PAD_PTA11__TMS			0x010 0x000 ALT1 0x0
+#define VF610_PAD_PTA11__DCU0_G1		0x010 0x000 ALT4 0x0
+#define VF610_PAD_PTA11__MLB_DATA		0x010 0x358 ALT7 0x0
+#define VF610_PAD_PTA12__GPIO_5			0x014 0x000 ALT0 0x0
+#define VF610_PAD_PTA12__TRACECK		0x014 0x000 ALT1 0x0
+#define VF610_PAD_PTA12__EXT_AUDIO_MCLK		0x014 0x2EC ALT2 0x1
+#define VF610_PAD_PTA12__VIU_DATA13		0x014 0x000 ALT6 0x0
+#define VF610_PAD_PTA12__I2C0_SCL		0x014 0x33C ALT7 0x0
+#define VF610_PAD_PTA16__GPIO_6			0x018 0x000 ALT0 0x0
+#define VF610_PAD_PTA16__TRACED0		0x018 0x000 ALT1 0x0
+#define VF610_PAD_PTA16__USB0_VBUS_EN		0x018 0x000 ALT2 0x0
+#define VF610_PAD_PTA16__ADC1_SE0		0x018 0x000 ALT3 0x0
+#define VF610_PAD_PTA16__LCD29			0x018 0x000 ALT4 0x0
+#define VF610_PAD_PTA16__SAI2_TX_BCLK		0x018 0x370 ALT5 0x0
+#define VF610_PAD_PTA16__VIU_DATA14		0x018 0x000 ALT6 0x0
+#define VF610_PAD_PTA16__I2C0_SDA		0x018 0x340 ALT7 0x0
+#define VF610_PAD_PTA17__GPIO_7			0x01C 0x000 ALT0 0x0
+#define VF610_PAD_PTA17__TRACED1		0x01C 0x000 ALT1 0x0
+#define VF610_PAD_PTA17__USB0_VBUS_OC		0x01C 0x000 ALT2 0x0
+#define VF610_PAD_PTA17__ADC1_SE1		0x01C 0x000 ALT3 0x0
+#define VF610_PAD_PTA17__LCD30			0x01C 0x000 ALT4 0x0
+#define VF610_PAD_PTA17__USB0_SOF_PULSE		0x01C 0x000 ALT5 0x0
+#define VF610_PAD_PTA17__VIU_DATA15		0x01C 0x000 ALT6 0x0
+#define VF610_PAD_PTA17__I2C1_SCL		0x01C 0x344 ALT7 0x0
+#define VF610_PAD_PTA18__GPIO_8			0x020 0x000 ALT0 0x0
+#define VF610_PAD_PTA18__TRACED2		0x020 0x000 ALT1 0x0
+#define VF610_PAD_PTA18__ADC0_SE0		0x020 0x000 ALT2 0x0
+#define VF610_PAD_PTA18__FTM1_QD_PHA		0x020 0x334 ALT3 0x0
+#define VF610_PAD_PTA18__LCD31			0x020 0x000 ALT4 0x0
+#define VF610_PAD_PTA18__SAI2_TX_DATA		0x020 0x000 ALT5 0x0
+#define VF610_PAD_PTA18__VIU_DATA16		0x020 0x000 ALT6 0x0
+#define VF610_PAD_PTA18__I2C1_SDA		0x020 0x348 ALT7 0x0
+#define VF610_PAD_PTA19__GPIO_9			0x024 0x000 ALT0 0x0
+#define VF610_PAD_PTA19__TRACED3		0x024 0x000 ALT1 0x0
+#define VF610_PAD_PTA19__ADC0_SE1		0x024 0x000 ALT2 0x0
+#define VF610_PAD_PTA19__FTM1_QD_PHB		0x024 0x338 ALT3 0x0
+#define VF610_PAD_PTA19__LCD32			0x024 0x000 ALT4 0x0
+#define VF610_PAD_PTA19__SAI2_TX_SYNC		0x024 0x000 ALT5 0x0
+#define VF610_PAD_PTA19__VIU_DATA17		0x024 0x000 ALT6 0x0
+#define VF610_PAD_PTA19__QSPI1_A_QSCK		0x024 0x374 ALT7 0x0
+#define VF610_PAD_PTA20__GPIO_10		0x028 0x000 ALT0 0x0
+#define VF610_PAD_PTA20__TRACED4		0x028 0x000 ALT1 0x0
+#define VF610_PAD_PTA20__LCD33			0x028 0x000 ALT4 0x0
+#define VF610_PAD_PTA20__UART3_TX		0x028 0x394 ALT6 0x0
+#define VF610_PAD_PTA20__DCU1_HSYNC		0x028 0x000 ALT7 0x0
+#define VF610_PAD_PTA21__GPIO_11		0x02C 0x000 ALT0 0x0
+#define VF610_PAD_PTA21__TRACED5		0x02C 0x000 ALT1 0x0
+#define VF610_PAD_PTA21__SAI2_RX_BCLK		0x02C 0x364 ALT5 0x0
+#define VF610_PAD_PTA21__UART3_RX		0x02C 0x390 ALT6 0x0
+#define VF610_PAD_PTA21__DCU1_VSYNC		0x02C 0x000 ALT7 0x0
+#define VF610_PAD_PTA22__GPIO_12		0x030 0x000 ALT0 0x0
+#define VF610_PAD_PTA22__TRACED6		0x030 0x000 ALT1 0x0
+#define VF610_PAD_PTA22__SAI2_RX_DATA		0x030 0x368 ALT5 0x0
+#define VF610_PAD_PTA22__I2C2_SCL		0x030 0x34C ALT6 0x0
+#define VF610_PAD_PTA22__DCU1_TAG		0x030 0x000 ALT7 0x0
+#define VF610_PAD_PTA23__GPIO_13		0x034 0x000 ALT0 0x0
+#define VF610_PAD_PTA23__TRACED7		0x034 0x000 ALT1 0x0
+#define VF610_PAD_PTA23__SAI2_RX_SYNC		0x034 0x36C ALT5 0x0
+#define VF610_PAD_PTA23__I2C2_SDA		0x034 0x350 ALT6 0x0
+#define VF610_PAD_PTA23__DCU1_DE		0x034 0x000 ALT7 0x0
+#define VF610_PAD_PTA24__GPIO_14		0x038 0x000 ALT0 0x0
+#define VF610_PAD_PTA24__TRACED8		0x038 0x000 ALT1 0x0
+#define VF610_PAD_PTA24__USB1_VBUS_EN		0x038 0x000 ALT2 0x0
+#define VF610_PAD_PTA24__ESDHC1_CLK		0x038 0x000 ALT5 0x0
+#define VF610_PAD_PTA24__DCU1_TCON4		0x038 0x000 ALT6 0x0
+#define VF610_PAD_PTA24__DDR_TEST_PAD_CTRL	0x038 0x000 ALT7 0x0
+#define VF610_PAD_PTA25__GPIO_15		0x03C 0x000 ALT0 0x0
+#define VF610_PAD_PTA25__TRACED9		0x03C 0x000 ALT1 0x0
+#define VF610_PAD_PTA25__USB1_VBUS_OC		0x03C 0x000 ALT2 0x0
+#define VF610_PAD_PTA25__ESDHC1_CMD		0x03C 0x000 ALT5 0x0
+#define VF610_PAD_PTA25__DCU1_TCON5		0x03C 0x000 ALT6 0x0
+#define VF610_PAD_PTA26__GPIO_16		0x040 0x000 ALT0 0x0
+#define VF610_PAD_PTA26__TRACED10		0x040 0x000 ALT1 0x0
+#define VF610_PAD_PTA26__SAI3_TX_BCLK		0x040 0x000 ALT2 0x0
+#define VF610_PAD_PTA26__ESDHC1_DAT0		0x040 0x000 ALT5 0x0
+#define VF610_PAD_PTA26__DCU1_TCON6		0x040 0x000 ALT6 0x0
+#define VF610_PAD_PTA27__GPIO_17		0x044 0x000 ALT0 0x0
+#define VF610_PAD_PTA27__TRACED11		0x044 0x000 ALT1 0x0
+#define VF610_PAD_PTA27__SAI3_RX_BCLK		0x044 0x000 ALT2 0x0
+#define VF610_PAD_PTA27__ESDHC1_DAT1		0x044 0x000 ALT5 0x0
+#define VF610_PAD_PTA27__DCU1_TCON7		0x044 0x000 ALT6 0x0
+#define VF610_PAD_PTA28__GPIO_18		0x048 0x000 ALT0 0x0
+#define VF610_PAD_PTA28__TRACED12		0x048 0x000 ALT1 0x0
+#define VF610_PAD_PTA28__SAI3_RX_DATA		0x048 0x000 ALT2 0x0
+#define VF610_PAD_PTA28__ENET1_1588_TMR0	0x048 0x000 ALT3 0x0
+#define VF610_PAD_PTA28__UART4_TX		0x048 0x000 ALT4 0x0
+#define VF610_PAD_PTA28__ESDHC1_DATA2		0x048 0x000 ALT5 0x0
+#define VF610_PAD_PTA28__DCU1_TCON8		0x048 0x000 ALT6 0x0
+#define VF610_PAD_PTA29__GPIO_19		0x04C 0x000 ALT0 0x0
+#define VF610_PAD_PTA29__TRACED13		0x04C 0x000 ALT1 0x0
+#define VF610_PAD_PTA29__SAI3_TX_DATA		0x04C 0x000 ALT2 0x0
+#define VF610_PAD_PTA29__ENET1_1588_TMR1	0x04C 0x000 ALT3 0x0
+#define VF610_PAD_PTA29__UART4_RX		0x04C 0x000 ALT4 0x0
+#define VF610_PAD_PTA29__ESDHC1_DAT3		0x04C 0x000 ALT5 0x0
+#define VF610_PAD_PTA29__DCU1_TCON9		0x04C 0x000 ALT6 0x0
+#define VF610_PAD_PTA30__GPIO_20		0x050 0x000 ALT0 0x0
+#define VF610_PAD_PTA30__TRACED14		0x050 0x000 ALT1 0x0
+#define VF610_PAD_PTA30__SAI3_RX_SYNC		0x050 0x000 ALT2 0x0
+#define VF610_PAD_PTA30__ENET1_1588_TMR2	0x050 0x000 ALT3 0x0
+#define VF610_PAD_PTA30__UART4_RTS		0x050 0x000 ALT4 0x0
+#define VF610_PAD_PTA30__I2C3_SCL		0x050 0x000 ALT5 0x0
+#define VF610_PAD_PTA30__UART3_TX		0x050 0x394 ALT7 0x1
+#define VF610_PAD_PTA31__GPIO_21		0x054 0x000 ALT0 0x0
+#define VF610_PAD_PTA31__TRACED15		0x054 0x000 ALT1 0x0
+#define VF610_PAD_PTA31__SAI3_TX_SYNC		0x054 0x000 ALT2 0x0
+#define VF610_PAD_PTA31__ENET1_1588_TMR3	0x054 0x000 ALT3 0x0
+#define VF610_PAD_PTA31__UART4_CTS		0x054 0x000 ALT4 0x0
+#define VF610_PAD_PTA31__I2C3_SDA		0x054 0x000 ALT5 0x0
+#define VF610_PAD_PTA31__UART3_RX		0x054 0x390 ALT7 0x1
+#define VF610_PAD_PTB0__GPIO_22			0x058 0x000 ALT0 0x0
+#define VF610_PAD_PTB0__FTM0_CH0		0x058 0x000 ALT1 0x0
+#define VF610_PAD_PTB0__ADC0_SE2		0x058 0x000 ALT2 0x0
+#define VF610_PAD_PTB0__TRACE_CTL		0x058 0x000 ALT3 0x0
+#define VF610_PAD_PTB0__LCD34			0x058 0x000 ALT4 0x0
+#define VF610_PAD_PTB0__SAI2_RX_BCLK		0x058 0x364 ALT5 0x1
+#define VF610_PAD_PTB0__VIU_DATA18		0x058 0x000 ALT6 0x0
+#define VF610_PAD_PTB0__QSPI1_A_QPCS0		0x058 0x000 ALT7 0x0
+#define VF610_PAD_PTB1__GPIO_23			0x05C 0x000 ALT0 0x0
+#define VF610_PAD_PTB1__FTM0_CH1		0x05C 0x000 ALT1 0x0
+#define VF610_PAD_PTB1__ADC0_SE3		0x05C 0x000 ALT2 0x0
+#define VF610_PAD_PTB1__SRC_RCON30		0x05C 0x000 ALT3 0x0
+#define VF610_PAD_PTB1__LCD35			0x05C 0x000 ALT4 0x0
+#define VF610_PAD_PTB1__SAI2_RX_DATA		0x05C 0x368 ALT5 0x1
+#define VF610_PAD_PTB1__VIU_DATA19		0x05C 0x000 ALT6 0x0
+#define VF610_PAD_PTB1__QSPI1_A_DATA3		0x05C 0x000 ALT7 0x0
+#define VF610_PAD_PTB2__GPIO_24			0x060 0x000 ALT0 0x0
+#define VF610_PAD_PTB2__FTM0_CH2		0x060 0x000 ALT1 0x0
+#define VF610_PAD_PTB2__ADC1_SE2		0x060 0x000 ALT2 0x0
+#define VF610_PAD_PTB2__SRC_RCON31		0x060 0x000 ALT3 0x0
+#define VF610_PAD_PTB2__LCD36			0x060 0x000 ALT4 0x0
+#define VF610_PAD_PTB2__SAI2_RX_SYNC		0x060 0x36C ALT5 0x1
+#define VF610_PAD_PTB2__VIDEO_IN0_DATA20	0x060 0x000 ALT6 0x0
+#define VF610_PAD_PTB2__QSPI1_A_DATA2		0x060 0x000 ALT7 0x0
+#define VF610_PAD_PTB3__GPIO_25			0x064 0x000 ALT0 0x0
+#define VF610_PAD_PTB3__FTM0_CH3		0x064 0x000 ALT1 0x0
+#define VF610_PAD_PTB3__ADC1_SE3		0x064 0x000 ALT2 0x0
+#define VF610_PAD_PTB3__PDB_EXTRIG		0x064 0x000 ALT3 0x0
+#define VF610_PAD_PTB3__LCD37			0x064 0x000 ALT4 0x0
+#define VF610_PAD_PTB3__VIU_DATA21		0x064 0x000 ALT6 0x0
+#define VF610_PAD_PTB3__QSPI1_A_DATA1		0x064 0x000 ALT7 0x0
+#define VF610_PAD_PTB4__GPIO_26			0x068 0x000 ALT0 0x0
+#define VF610_PAD_PTB4__FTM0_CH4		0x068 0x000 ALT1 0x0
+#define VF610_PAD_PTB4__UART1_TX		0x068 0x380 ALT2 0x0
+#define VF610_PAD_PTB4__ADC0_SE4		0x068 0x000 ALT3 0x0
+#define VF610_PAD_PTB4__LCD38			0x068 0x000 ALT4 0x0
+#define VF610_PAD_PTB4__VIU_FID			0x068 0x3A8 ALT5 0x0
+#define VF610_PAD_PTB4__VIU_DATA22		0x068 0x000 ALT6 0x0
+#define VF610_PAD_PTB4__QSPI1_A_DATA0		0x068 0x000 ALT7 0x0
+#define VF610_PAD_PTB5__GPIO_27			0x06C 0x000 ALT0 0x0
+#define VF610_PAD_PTB5__FTM0_CH5		0x06C 0x000 ALT1 0x0
+#define VF610_PAD_PTB5__UART1_RX		0x06C 0x37C ALT2 0x0
+#define VF610_PAD_PTB5__ADC1_SE4		0x06C 0x000 ALT3 0x0
+#define VF610_PAD_PTB5__LCD39			0x06C 0x000 ALT4 0x0
+#define VF610_PAD_PTB5__VIU_DE			0x06C 0x3A4 ALT5 0x0
+#define VF610_PAD_PTB5__QSPI1_A_DQS		0x06C 0x000 ALT7 0x0
+#define VF610_PAD_PTB6__GPIO_28			0x070 0x000 ALT0 0x0
+#define VF610_PAD_PTB6__FTM0_CH6		0x070 0x000 ALT1 0x0
+#define VF610_PAD_PTB6__UART1_RTS		0x070 0x000 ALT2 0x0
+#define VF610_PAD_PTB6__QSPI0_QPCS1_A		0x070 0x000 ALT3 0x0
+#define VF610_PAD_PTB6__LCD_LCD40		0x070 0x000 ALT4 0x0
+#define VF610_PAD_PTB6__FB_CLKOUT		0x070 0x000 ALT5 0x0
+#define VF610_PAD_PTB6__VIU_HSYNC		0x070 0x000 ALT6 0x0
+#define VF610_PAD_PTB6__UART2_TX		0x070 0x38C ALT7 0x0
+#define VF610_PAD_PTB7__GPIO_29			0x074 0x000 ALT0 0x0
+#define VF610_PAD_PTB7__FTM0_CH7		0x074 0x000 ALT1 0x0
+#define VF610_PAD_PTB7__UART1_CTS		0x074 0x378 ALT2 0x0
+#define VF610_PAD_PTB7__QSPI0_B_QPCS1		0x074 0x000 ALT3 0x0
+#define VF610_PAD_PTB7__LCD41			0x074 0x000 ALT4 0x0
+#define VF610_PAD_PTB7__VIU_VSYNC		0x074 0x000 ALT6 0x0
+#define VF610_PAD_PTB7__UART2_RX		0x074 0x388 ALT7 0x0
+#define VF610_PAD_PTB8__GPIO_30			0x078 0x000 ALT0 0x0
+#define VF610_PAD_PTB8__FTM1_CH0		0x078 0x32C ALT1 0x0
+#define VF610_PAD_PTB8__FTM1_QD_PHA		0x078 0x334 ALT3 0x1
+#define VF610_PAD_PTB8__VIU_DE			0x078 0x3A4 ALT5 0x1
+#define VF610_PAD_PTB8__DCU1_R6			0x078 0x000 ALT7 0x0
+#define VF610_PAD_PTB9__GPIO_31			0x07C 0x000 ALT0 0x0
+#define VF610_PAD_PTB9__FTM1_CH1		0x07C 0x330 ALT1 0x0
+#define VF610_PAD_PTB9__FTM1_QD_PHB		0x07C 0x338 ALT3 0x1
+#define VF610_PAD_PTB9__DCU1_R7			0x07C 0x000 ALT7 0x0
+#define VF610_PAD_PTB10__GPIO_32		0x080 0x000 ALT0 0x0
+#define VF610_PAD_PTB10__UART0_TX		0x080 0x000 ALT1 0x0
+#define VF610_PAD_PTB10__DCU0_TCON4		0x080 0x000 ALT4 0x0
+#define VF610_PAD_PTB10__VIU_DE			0x080 0x3A4 ALT5 0x2
+#define VF610_PAD_PTB10__CKO1			0x080 0x000 ALT6 0x0
+#define VF610_PAD_PTB10__ENET_TS_CLKIN		0x080 0x2F4 ALT7 0x1
+#define VF610_PAD_PTB11__GPIO_33		0x084 0x000 ALT0 0x0
+#define VF610_PAD_PTB11__UART0_RX		0x084 0x000 ALT1 0x0
+#define VF610_PAD_PTB11__DCU0_TCON5		0x084 0x000 ALT4 0x0
+#define VF610_PAD_PTB11__SNVS_ALARM_OUT_B	0x084 0x000 ALT5 0x0
+#define VF610_PAD_PTB11__CKO2			0x084 0x000 ALT6 0x0
+#define VF610_PAD_PTB11_ENET0_1588_TMR0		0x084 0x304 ALT7 0x0
+#define VF610_PAD_PTB12__GPIO_34		0x088 0x000 ALT0 0x0
+#define VF610_PAD_PTB12__UART0_RTS		0x088 0x000 ALT1 0x0
+#define VF610_PAD_PTB12__DSPI0_CS5		0x088 0x000 ALT3 0x0
+#define VF610_PAD_PTB12__DCU0_TCON6		0x088 0x000 ALT4 0x0
+#define VF610_PAD_PTB12__FB_AD1			0x088 0x000 ALT5 0x0
+#define VF610_PAD_PTB12__NMI			0x088 0x000 ALT6 0x0
+#define VF610_PAD_PTB12__ENET0_1588_TMR1	0x088 0x308 ALT7 0x0
+#define VF610_PAD_PTB13__GPIO_35		0x08C 0x000 ALT0 0x0
+#define VF610_PAD_PTB13__UART0_CTS		0x08C 0x000 ALT1 0x0
+#define VF610_PAD_PTB13__DSPI0_CS4		0x08C 0x000 ALT3 0x0
+#define VF610_PAD_PTB13__DCU0_TCON7		0x08C 0x000 ALT4 0x0
+#define VF610_PAD_PTB13__FB_AD0			0x08C 0x000 ALT5 0x0
+#define VF610_PAD_PTB13__TRACE_CTL		0x08C 0x000 ALT6 0x0
+#define VF610_PAD_PTB14__GPIO_36		0x090 0x000 ALT0 0x0
+#define VF610_PAD_PTB14__CAN0_RX		0x090 0x000 ALT1 0x0
+#define VF610_PAD_PTB14__I2C0_SCL		0x090 0x33C ALT2 0x1
+#define VF610_PAD_PTB14__DCU0_TCON8		0x090 0x000 ALT4 0x0
+#define VF610_PAD_PTB14__DCU1_PCLK		0x090 0x000 ALT7 0x0
+#define VF610_PAD_PTB15__GPIO_37		0x094 0x000 ALT0 0x0
+#define VF610_PAD_PTB15__CAN0_TX		0x094 0x000 ALT1 0x0
+#define VF610_PAD_PTB15__I2C0_SDA		0x094 0x340 ALT2 0x1
+#define VF610_PAD_PTB15__DCU0_TCON9		0x094 0x000 ALT4 0x0
+#define VF610_PAD_PTB15__VIU_PIX_CLK		0x094 0x3AC ALT7 0x0
+#define VF610_PAD_PTB16__GPIO_38		0x098 0x000 ALT0 0x0
+#define VF610_PAD_PTB16__CAN1_RX		0x098 0x000 ALT1 0x0
+#define VF610_PAD_PTB16__I2C1_SCL		0x098 0x344 ALT2 0x1
+#define VF610_PAD_PTB16__DCU0_TCON10		0x098 0x000 ALT4 0x0
+#define VF610_PAD_PTB17__GPIO_39		0x09C 0x000 ALT0 0x0
+#define VF610_PAD_PTB17__CAN1_TX		0x09C 0x000 ALT1 0x0
+#define VF610_PAD_PTB17__I2C1_SDA		0x09C 0x348 ALT2 0x1
+#define VF610_PAD_PTB17__DCU0_TCON11		0x09C 0x000 ALT4 0x0
+#define VF610_PAD_PTB18__GPIO_40		0x0A0 0x000 ALT0 0x0
+#define VF610_PAD_PTB18__DSPI0_CS1		0x0A0 0x000 ALT1 0x0
+#define VF610_PAD_PTB18__EXT_AUDIO_MCLK		0x0A0 0x2EC ALT2 0x2
+#define VF610_PAD_PTB18__VIU_DATA9		0x0A0 0x000 ALT6 0x0
+#define VF610_PAD_PTB19__GPIO_41		0x0A4 0x000 ALT0 0x0
+#define VF610_PAD_PTB19__DSPI0_CS0		0x0A4 0x000 ALT1 0x0
+#define VF610_PAD_PTB19__VIU_DATA10		0x0A4 0x000 ALT6 0x0
+#define VF610_PAD_PTB20__GPIO_42		0x0A8 0x000 ALT0 0x0
+#define VF610_PAD_PTB20__DSPI0_SIN		0x0A8 0x000 ALT1 0x0
+#define VF610_PAD_PTB20__LCD42			0x0A8 0x000 ALT4 0x0
+#define VF610_PAD_PTB20__VIU_DATA11		0x0A8 0x000 ALT6 0x0
+#define VF610_PAD_PTB21__GPIO_43		0x0AC 0x000 ALT0 0x0
+#define VF610_PAD_PTB21__DSPI0_SOUT		0x0AC 0x000 ALT1 0x0
+#define VF610_PAD_PTB21__LCD43			0x0AC 0x000 ALT4 0x0
+#define VF610_PAD_PTB21__VIU_DATA12		0x0AC 0x000 ALT6 0x0
+#define VF610_PAD_PTB21__DCU1_PCLK		0x0AC 0x000 ALT7 0x0
+#define VF610_PAD_PTB22__GPIO_44		0x0B0 0x000 ALT0 0x0
+#define VF610_PAD_PTB22__DSPI0_SCK		0x0B0 0x000 ALT1 0x0
+#define VF610_PAD_PTB22__VLCD			0x0B0 0x000 ALT4 0x0
+#define VF610_PAD_PTB22__VIU_FID		0x0B0 0x3A8 ALT5 0x1
+#define VF610_PAD_PTC0__GPIO_45			0x0B4 0x000 ALT0 0x0
+#define VF610_PAD_PTC0__ENET_RMII0_MDC		0x0B4 0x000 ALT1 0x0
+#define VF610_PAD_PTC0__FTM1_CH0		0x0B4 0x32C ALT2 0x1
+#define VF610_PAD_PTC0__DSPI0_CS3		0x0B4 0x000 ALT3 0x0
+#define VF610_PAD_PTC0__ESAI_SCKT		0x0B4 0x310 ALT4 0x0
+#define VF610_PAD_PTC0__ESDHC0_CLK		0x0B4 0x000 ALT5 0x0
+#define VF610_PAD_PTC0__VIU_DATA0		0x0B4 0x000 ALT6 0x0
+#define VF610_PAD_PTC0__SRC_RCON18		0x0B4 0x398 ALT7 0x0
+#define VF610_PAD_PTC1__GPIO_46			0x0B8 0x000 ALT0 0x0
+#define VF610_PAD_PTC1__ENET_RMII0_MDIO		0x0B8 0x000 ALT1 0x0
+#define VF610_PAD_PTC1__FTM1_CH1		0x0B8 0x330 ALT2 0x1
+#define VF610_PAD_PTC1__DSPI0_CS2		0x0B8 0x000 ALT3 0x0
+#define VF610_PAD_PTC1__ESAI_FST		0x0B8 0x30C ALT4 0x0
+#define VF610_PAD_PTC1__ESDHC0_CMD		0x0B8 0x000 ALT5 0x0
+#define VF610_PAD_PTC1__VIU_DATA1		0x0B8 0x000 ALT6 0x0
+#define VF610_PAD_PTC1__SRC_RCON19		0x0B8 0x39C ALT7 0x0
+#define VF610_PAD_PTC2__GPIO_47			0x0BC 0x000 ALT0 0x0
+#define VF610_PAD_PTC2__ENET_RMII0_CRS		0x0BC 0x000 ALT1 0x0
+#define VF610_PAD_PTC2__UART1_TX		0x0BC 0x380 ALT2 0x1
+#define VF610_PAD_PTC2__ESAI_SDO0		0x0BC 0x314 ALT4 0x0
+#define VF610_PAD_PTC2__ESDHC0_DAT0		0x0BC 0x000 ALT5 0x0
+#define VF610_PAD_PTC2__VIU_DATA2		0x0BC 0x000 ALT6 0x0
+#define VF610_PAD_PTC2__SRC_RCON20		0x0BC 0x3A0 ALT7 0x0
+#define VF610_PAD_PTC3__GPIO_48			0x0C0 0x000 ALT0 0x0
+#define VF610_PAD_PTC3__ENET_RMII0_RXD1		0x0C0 0x000 ALT1 0x0
+#define VF610_PAD_PTC3__UART1_RX		0x0C0 0x37C ALT2 0x1
+#define VF610_PAD_PTC3__ESAI_SDO1		0x0C0 0x318 ALT4 0x0
+#define VF610_PAD_PTC3__ESDHC0_DAT1		0x0C0 0x000 ALT5 0x0
+#define VF610_PAD_PTC3__VIU_DATA3		0x0C0 0x000 ALT6 0x0
+#define VF610_PAD_PTC3__DCU0_R0			0x0C0 0x000 ALT7 0x0
+#define VF610_PAD_PTC4__GPIO_49			0x0C4 0x000 ALT0 0x0
+#define VF610_PAD_PTC4__ENET_RMII0_RXD0		0x0C4 0x000 ALT1 0x0
+#define VF610_PAD_PTC4__UART1_RTS		0x0C4 0x000 ALT2 0x0
+#define VF610_PAD_PTC4__DSPI1_CS1		0x0C4 0x000 ALT3 0x0
+#define VF610_PAD_PTC4__ESAI_SDO2		0x0C4 0x31C ALT4 0x0
+#define VF610_PAD_PTC4__ESDHC0_DAT2		0x0C4 0x000 ALT5 0x0
+#define VF610_PAD_PTC4__VIU_DATA4		0x0C4 0x000 ALT6 0x0
+#define VF610_PAD_PTC4__DCU0_R1			0x0C4 0x000 ALT7 0x0
+#define VF610_PAD_PTC5__GPIO_50			0x0C8 0x000 ALT0 0x0
+#define VF610_PAD_PTC5__ENET_RMII0_RXER		0x0C8 0x000 ALT1 0x0
+#define VF610_PAD_PTC5__UART1_CTS		0x0C8 0x378 ALT2 0x1
+#define VF610_PAD_PTC5__DSPI1_CS0		0x0C8 0x300 ALT3 0x0
+#define VF610_PAD_PTC5__ESAI_SDO3		0x0C8 0x320 ALT4 0x0
+#define VF610_PAD_PTC5__ESDHC0_DAT3		0x0C8 0x000 ALT5 0x0
+#define VF610_PAD_PTC5__VIU_DATA5		0x0C8 0x000 ALT6 0x0
+#define VF610_PAD_PTC5__DCU0_G0			0x0C8 0x000 ALT7 0x0
+#define VF610_PAD_PTC6__GPIO_51			0x0CC 0x000 ALT0 0x0
+#define VF610_PAD_PTC6__ENET_RMII0_TXD1		0x0CC 0x000 ALT1 0x0
+#define VF610_PAD_PTC6__DSPI1_SIN		0x0CC 0x2FC ALT3 0x0
+#define VF610_PAD_PTC6__ESAI_SDI0		0x0CC 0x328 ALT4 0x0
+#define VF610_PAD_PTC6__ESDHC0_WP		0x0CC 0x000 ALT5 0x0
+#define VF610_PAD_PTC6__VIU_DATA6		0x0CC 0x000 ALT6 0x0
+#define VF610_PAD_PTC6__DCU0_G1			0x0CC 0x000 ALT7 0x0
+#define VF610_PAD_PTC7__GPIO_52			0x0D0 0x000 ALT0 0x0
+#define VF610_PAD_PTC7__ENET_RMII0_TXD0		0x0D0 0x000 ALT1 0x0
+#define VF610_PAD_PTC7__DSPI1_SOUT		0x0D0 0x000 ALT3 0x0
+#define VF610_PAD_PTC7__ESAI_SDI1		0x0D0 0x324 ALT4 0x0
+#define VF610_PAD_PTC7__VIU_DATA7		0x0D0 0x000 ALT6 0x0
+#define VF610_PAD_PTC7__DCU0_B0			0x0D0 0x000 ALT7 0x0
+#define VF610_PAD_PTC8__GPIO_53			0x0D4 0x000 ALT0 0x0
+#define VF610_PAD_PTC8__ENET_RMII0_TXEN		0x0D4 0x000 ALT1 0x0
+#define VF610_PAD_PTC8__DSPI1_SCK		0x0D4 0x2F8 ALT3 0x0
+#define VF610_PAD_PTC8__VIU_DATA8		0x0D4 0x000 ALT6 0x0
+#define VF610_PAD_PTC8__DCU0_B1			0x0D4 0x000 ALT7 0x0
+#define VF610_PAD_PTC9__GPIO_54			0x0D8 0x000 ALT0 0x0
+#define VF610_PAD_PTC9__ENET_RMII1_MDC		0x0D8 0x000 ALT1 0x0
+#define VF610_PAD_PTC9__ESAI_SCKT		0x0D8 0x310 ALT3 0x1
+#define VF610_PAD_PTC9__MLB_CLK			0x0D8 0x354 ALT6 0x1
+#define VF610_PAD_PTC9__DEBUG_OUT0		0x0D8 0x000 ALT7 0x0
+#define VF610_PAD_PTC10__GPIO_55		0x0DC 0x000 ALT0 0x0
+#define VF610_PAD_PTC10__ENET_RMII1_MDIO	0x0DC 0x000 ALT1 0x0
+#define VF610_PAD_PTC10__ESAI_FST		0x0DC 0x30C ALT3 0x1
+#define VF610_PAD_PTC10__MLB_SIGNAL		0x0DC 0x35C ALT6 0x1
+#define VF610_PAD_PTC10__DEBUG_OUT1		0x0DC 0x000 ALT7 0x0
+#define VF610_PAD_PTC11__GPIO_56		0x0E0 0x000 ALT0 0x0
+#define VF610_PAD_PTC11__ENET_RMII1_CRS		0x0E0 0x000 ALT1 0x0
+#define VF610_PAD_PTC11__ESAI_SDO0		0x0E0 0x314 ALT3 0x1
+#define VF610_PAD_PTC11__MLB_DATA		0x0E0 0x358 ALT6 0x1
+#define VF610_PAD_PTC11__DEBUG_OUT		0x0E0 0x000 ALT7 0x0
+#define VF610_PAD_PTC12__GPIO_57		0x0E4 0x000 ALT0 0x0
+#define VF610_PAD_PTC12__ENET_RMII1_RXD1	0x0E4 0x000 ALT1 0x0
+#define VF610_PAD_PTC12__ESAI_SDO1		0x0E4 0x318 ALT3 0x1
+#define VF610_PAD_PTC12__SAI2_TX_BCLK		0x0E4 0x370 ALT5 0x1
+#define VF610_PAD_PTC12__DEBUG_OUT3		0x0E4 0x000 ALT7 0x0
+#define VF610_PAD_PTC13__GPIO_58		0x0E8 0x000 ALT0 0x0
+#define VF610_PAD_PTC13__ENET_RMII1_RXD0	0x0E8 0x000 ALT1 0x0
+#define VF610_PAD_PTC13__ESAI_SDO2		0x0E8 0x31C ALT3 0x1
+#define VF610_PAD_PTC13__SAI2_RX_BCLK		0x0E8 0x364 ALT5 0x2
+#define VF610_PAD_PTC13__DEBUG_OUT4		0x0E8 0x000 ALT7 0x0
+#define VF610_PAD_PTC14__GPIO_59		0x0EC 0x000 ALT0 0x0
+#define VF610_PAD_PTC14__ENET_RMII1_RXER	0x0EC 0x000 ALT1 0x0
+#define VF610_PAD_PTC14__ESAI_SDO3		0x0EC 0x320 ALT3 0x1
+#define VF610_PAD_PTC14__UART5_TX		0x0EC 0x000 ALT4 0x0
+#define VF610_PAD_PTC14__SAI2_RX_DATA		0x0EC 0x368 ALT5 0x2
+#define VF610_PAD_PTC14__ADC0_SE6		0x0EC 0x000 ALT6 0x0
+#define VF610_PAD_PTC14__DEBUG_OUT5		0x0EC 0x000 ALT7 0x0
+#define VF610_PAD_PTC15__GPIO_60		0x0F0 0x000 ALT0 0x0
+#define VF610_PAD_PTC15__ENET_RMII1_TXD1	0x0F0 0x000 ALT1 0x0
+#define VF610_PAD_PTC15__ESAI_SDI0		0x0F0 0x328 ALT3 0x1
+#define VF610_PAD_PTC15__UART5_RX		0x0F0 0x000 ALT4 0x0
+#define VF610_PAD_PTC15__SAI2_TX_DATA		0x0F0 0x000 ALT5 0x0
+#define VF610_PAD_PTC15__ADC0_SE7		0x0F0 0x000 ALT6 0x0
+#define VF610_PAD_PTC15__DEBUG_OUT6		0x0F0 0x000 ALT7 0x0
+#define VF610_PAD_PTC16__GPIO_61		0x0F4 0x000 ALT0 0x0
+#define VF610_PAD_PTC16__ENET_RMII1_TXD0	0x0F4 0x000 ALT1 0x0
+#define VF610_PAD_PTC16__ESAI_SDI1		0x0F4 0x324 ALT3 0x1
+#define VF610_PAD_PTC16__UART5_RTS		0x0F4 0x000 ALT4 0x0
+#define VF610_PAD_PTC16__SAI2_RX_SYNC		0x0F4 0x36C ALT5 0x2
+#define VF610_PAD_PTC16__ADC1_SE6		0x0F4 0x000 ALT6 0x0
+#define VF610_PAD_PTC16__DEBUG_OUT7		0x0F4 0x000 ALT7 0x0
+#define VF610_PAD_PTC17__GPIO_62		0x0F8 0x000 ALT0 0x0
+#define VF610_PAD_PTC17__ENET_RMII1_TXEN	0x0F8 0x000 ALT1 0x0
+#define VF610_PAD_PTC17__ADC1_SE7		0x0F8 0x000 ALT3 0x0
+#define VF610_PAD_PTC17__UART5_CTS		0x0F8 0x000 ALT4 0x0
+#define VF610_PAD_PTC17__SAI2_TX_SYNC		0x0F8 0x374 ALT5 0x1
+#define VF610_PAD_PTC17__USB1_SOF_PULSE		0x0F8 0x000 ALT6 0x0
+#define VF610_PAD_PTC17__DEBUG_OUT8		0x0F8 0x000 ALT7 0x0
+#define VF610_PAD_PTD31__GPIO_63		0x0FC 0x000 ALT0 0x0
+#define VF610_PAD_PTD31__FB_AD31		0x0FC 0x000 ALT1 0x0
+#define VF610_PAD_PTD31__NF_IO15		0x0FC 0x000 ALT2 0x0
+#define VF610_PAD_PTD31__FTM3_CH0		0x0FC 0x000 ALT4 0x0
+#define VF610_PAD_PTD31__DSPI2_CS1		0x0FC 0x000 ALT5 0x0
+#define VF610_PAD_PTD31__DEBUG_OUT9		0x0FC 0x000 ALT7 0x0
+#define VF610_PAD_PTD30__GPIO_64		0x100 0x000 ALT0 0x0
+#define VF610_PAD_PTD30__FB_AD30		0x100 0x000 ALT1 0x0
+#define VF610_PAD_PTD30__NF_IO14		0x100 0x000 ALT2 0x0
+#define VF610_PAD_PTD30__FTM3_CH1		0x100 0x000 ALT4 0x0
+#define VF610_PAD_PTD30__DSPI2_CS0		0x100 0x000 ALT5 0x0
+#define VF610_PAD_PTD30__DEBUG_OUT10		0x100 0x000 ALT7 0x0
+#define VF610_PAD_PTD29__GPIO_65		0x104 0x000 ALT0 0x0
+#define VF610_PAD_PTD29__FB_AD29		0x104 0x000 ALT1 0x0
+#define VF610_PAD_PTD29__NF_IO13		0x104 0x000 ALT2 0x0
+#define VF610_PAD_PTD29__FTM3_CH2		0x104 0x000 ALT4 0x0
+#define VF610_PAD_PTD29__DSPI2_SIN		0x104 0x000 ALT5 0x0
+#define VF610_PAD_PTD29__DEBUG_OUT11		0x104 0x000 ALT7 0x0
+#define VF610_PAD_PTD28__GPIO_66	 	0x108 0x000 ALT0 0x0
+#define VF610_PAD_PTD28__FB_AD28		0x108 0x000 ALT1 0x0
+#define VF610_PAD_PTD28__NF_IO12		0x108 0x000 ALT2 0x0
+#define VF610_PAD_PTD28__I2C2_SCL		0x108 0x34C ALT3 0x1
+#define VF610_PAD_PTD28__FTM3_CH3		0x108 0x000 ALT4 0x0
+#define VF610_PAD_PTD28__DSPI2_SOUT		0x108 0x000 ALT5 0x0
+#define VF610_PAD_PTD28__DEBUG_OUT12		0x108 0x000 ALT7 0x0
+#define VF610_PAD_PTD27__GPIO_67		0x10C 0x000 ALT0 0x0
+#define VF610_PAD_PTD27__FB_AD27		0x10C 0x000 ALT1 0x0
+#define VF610_PAD_PTD27__NF_IO11		0x10C 0x000 ALT2 0x0
+#define VF610_PAD_PTD27__I2C2_SDA		0x10C 0x350 ALT3 0x1
+#define VF610_PAD_PTD27__FTM3_CH4		0x10C 0x000 ALT4 0x0
+#define VF610_PAD_PTD27__DSPI2_SCK		0x10C 0x000 ALT5 0x0
+#define VF610_PAD_PTD27__DEBUG_OUT13		0x10C 0x000 ALT7 0x0
+#define VF610_PAD_PTD26__GPIO_68		0x110 0x000 ALT0 0x0
+#define VF610_PAD_PTD26__FB_AD26		0x110 0x000 ALT1 0x0
+#define VF610_PAD_PTD26__NF_IO10		0x110 0x000 ALT2 0x0
+#define VF610_PAD_PTD26__FTM3_CH5		0x110 0x000 ALT4 0x0
+#define VF610_PAD_PTD26__ESDHC1_WP		0x110 0x000 ALT5 0x0
+#define VF610_PAD_PTD26__DEBUG_OUT14		0x110 0x000 ALT7 0x0
+#define VF610_PAD_PTD25__GPIO_69		0x114 0x000 ALT0 0x0
+#define VF610_PAD_PTD25__FB_AD25		0x114 0x000 ALT1 0x0
+#define VF610_PAD_PTD25__NF_IO9			0x114 0x000 ALT2 0x0
+#define VF610_PAD_PTD25__FTM3_CH6		0x114 0x000 ALT4 0x0
+#define VF610_PAD_PTD25__DEBUG_OUT15		0x114 0x000 ALT7 0x0
+#define VF610_PAD_PTD24__GPIO_70		0x118 0x000 ALT0 0x0
+#define VF610_PAD_PTD24__FB_AD24		0x118 0x000 ALT1 0x0
+#define VF610_PAD_PTD24__NF_IO8			0x118 0x000 ALT2 0x0
+#define VF610_PAD_PTD24__FTM3_CH7		0x118 0x000 ALT4 0x0
+#define VF610_PAD_PTD24__DEBUG_OUT16		0x118 0x000 ALT7 0x0
+#define VF610_PAD_PTD23__GPIO_71		0x11C 0x000 ALT0 0x0
+#define VF610_PAD_PTD23__FB_AD23		0x11C 0x000 ALT1 0x0
+#define VF610_PAD_PTD23__NF_IO7			0x11C 0x000 ALT2 0x0
+#define VF610_PAD_PTD23__FTM2_CH0		0x11C 0x000 ALT3 0x0
+#define VF610_PAD_PTD23__ENET0_1588_TMR0	0x11C 0x304 ALT4 0x1
+#define VF610_PAD_PTD23__ESDHC0_DAT4		0x11C 0x000 ALT5 0x0
+#define VF610_PAD_PTD23__UART2_TX		0x11C 0x38C ALT6 0x1
+#define VF610_PAD_PTD23__DCU1_R3		0x11C 0x000 ALT7 0x0
+#define VF610_PAD_PTD22__GPIO_72		0x120 0x000 ALT0 0x0
+#define VF610_PAD_PTD22__FB_AD22		0x120 0x000 ALT1 0x0
+#define VF610_PAD_PTD22__NF_IO6			0x120 0x000 ALT2 0x0
+#define VF610_PAD_PTD22__FTM2_CH1		0x120 0x000 ALT3 0x0
+#define VF610_PAD_PTD22__ENET0_1588_TMR1	0x120 0x308 ALT4 0x1
+#define VF610_PAD_PTD22__ESDHC0_DAT5		0x120 0x000 ALT5 0x0
+#define VF610_PAD_PTD22__UART2_RX		0x120 0x388 ALT6 0x1
+#define VF610_PAD_PTD22__DCU1_R4		0x120 0x000 ALT7 0x0
+#define VF610_PAD_PTD21__GPIO_73		0x124 0x000 ALT0 0x0
+#define VF610_PAD_PTD21__FB_AD21		0x124 0x000 ALT1 0x0
+#define VF610_PAD_PTD21__NF_IO5			0x124 0x000 ALT2 0x0
+#define VF610_PAD_PTD21__ENET0_1588_TMR2	0x124 0x000 ALT4 0x0
+#define VF610_PAD_PTD21__ESDHC0_DAT6		0x124 0x000 ALT5 0x0
+#define VF610_PAD_PTD21__UART2_RTS		0x124 0x000 ALT6 0x0
+#define VF610_PAD_PTD21__DCU1_R5		0x124 0x000 ALT7 0x0
+#define VF610_PAD_PTD20__GPIO_74		0x128 0x000 ALT0 0x0
+#define VF610_PAD_PTD20__FB_AD20		0x128 0x000 ALT1 0x0
+#define VF610_PAD_PTD20__NF_IO4			0x128 0x000 ALT2 0x0
+#define VF610_PAD_PTD20__ENET0_1588_TMR3	0x128 0x000 ALT4 0x0
+#define VF610_PAD_PTD20__ESDHC0_DAT7		0x128 0x000 ALT5 0x0
+#define VF610_PAD_PTD20__UART2_CTS		0x128 0x384 ALT6 0x0
+#define VF610_PAD_PTD20__DCU1_R0		0x128 0x000 ALT7 0x0
+#define VF610_PAD_PTD19__GPIO_75		0x12C 0x000 ALT0 0x0
+#define VF610_PAD_PTD19__FB_AD19		0x12C 0x000 ALT1 0x0
+#define VF610_PAD_PTD19__NF_IO3			0x12C 0x000 ALT2 0x0
+#define VF610_PAD_PTD19__ESAI_SCKR		0x12C 0x000 ALT3 0x0
+#define VF610_PAD_PTD19__I2C0_SCL		0x12C 0x33C ALT4 0x2
+#define VF610_PAD_PTD19__FTM2_QD_PHA		0x12C 0x000 ALT5 0x0
+#define VF610_PAD_PTD19__DCU1_R1		0x12C 0x000 ALT7 0x0
+#define VF610_PAD_PTD18__GPIO_76		0x130 0x000 ALT0 0x0
+#define VF610_PAD_PTD18__FB_AD18		0x130 0x000 ALT1 0x0
+#define VF610_PAD_PTD18__NF_IO2			0x130 0x000 ALT2 0x0
+#define VF610_PAD_PTD18__ESAI_FSR		0x130 0x000 ALT3 0x0
+#define VF610_PAD_PTD18__I2C0_SDA		0x130 0x340 ALT4 0x2
+#define VF610_PAD_PTD18__FTM2_QD_PHB		0x130 0x000 ALT5 0x0
+#define VF610_PAD_PTD18__DCU1_G0		0x130 0x000 ALT7 0x0
+#define VF610_PAD_PTD17__GPIO_77		0x134 0x000 ALT0 0x0
+#define VF610_PAD_PTD17__FB_AD17		0x134 0x000 ALT1 0x0
+#define VF610_PAD_PTD17__NF_IO1			0x134 0x000 ALT2 0x0
+#define VF610_PAD_PTD17__ESAI_HCKR		0x134 0x000 ALT3 0x0
+#define VF610_PAD_PTD17__I2C1_SCL		0x134 0x344 ALT4 0x2
+#define VF610_PAD_PTD17__DCU1_G1		0x134 0x000 ALT7 0x0
+#define VF610_PAD_PTD16__GPIO_78		0x138 0x000 ALT0 0x0
+#define VF610_PAD_PTD16__FB_AD16		0x138 0x000 ALT1 0x0
+#define VF610_PAD_PTD16__NF_IO0			0x138 0x000 ALT2 0x0
+#define VF610_PAD_PTD16__ESAI_HCKT		0x138 0x000 ALT3 0x0
+#define VF610_PAD_PTD16__I2C1_SDA		0x138 0x348 ALT4 0x2
+#define VF610_PAD_PTD16__DCU1_G2		0x138 0x000 ALT7 0x0
+#define VF610_PAD_PTD0__GPIO_79			0x13C 0x000 ALT0 0x0
+#define VF610_PAD_PTD0__QSPI0_A_QSCK		0x13C 0x000 ALT1 0x0
+#define VF610_PAD_PTD0__UART2_TX		0x13C 0x38C ALT2 0x2
+#define VF610_PAD_PTD0__FB_AD15			0x13C 0x000 ALT4 0x0
+#define VF610_PAD_PTD0__SPDIF_EXTCLK		0x13C 0x000 ALT5 0x0
+#define VF610_PAD_PTD0__DEBUG_OUT17		0x13C 0x000 ALT7 0x0
+#define VF610_PAD_PTD1__GPIO_80			0x140 0x000 ALT0 0x0
+#define VF610_PAD_PTD1__QSPI0_A_CS0		0x140 0x000 ALT1 0x0
+#define VF610_PAD_PTD1__UART2_RX		0x140 0x388 ALT2 0x2
+#define VF610_PAD_PTD1__FB_AD14			0x140 0x000 ALT4 0x0
+#define VF610_PAD_PTD1__SPDIF_IN1		0x140 0x000 ALT5 0x0
+#define VF610_PAD_PTD1__DEBUG_OUT18		0x140 0x000 ALT7 0x0
+#define VF610_PAD_PTD2__GPIO_81			0x144 0x000 ALT0 0x0
+#define VF610_PAD_PTD2__QSPI0_A_DATA3		0x144 0x000 ALT1 0x0
+#define VF610_PAD_PTD2__UART2_RTS		0x144 0x000 ALT2 0x0
+#define VF610_PAD_PTD2__DSPI1_CS3		0x144 0x000 ALT3 0x0
+#define VF610_PAD_PTD2__FB_AD13			0x144 0x000 ALT4 0x0
+#define VF610_PAD_PTD2__SPDIF_OUT1		0x144 0x000 ALT5 0x0
+#define VF610_PAD_PTD2__DEBUG_OUT19		0x144 0x000 ALT7 0x0
+#define VF610_PAD_PTD3__GPIO_82			0x148 0x000 ALT0 0x0
+#define VF610_PAD_PTD3__QSPI0_A_DATA2		0x148 0x000 ALT1 0x0
+#define VF610_PAD_PTD3__UART2_CTS		0x148 0x384 ALT2 0x1
+#define VF610_PAD_PTD3__DSPI1_CS2		0x148 0x000 ALT3 0x0
+#define VF610_PAD_PTD3__FB_AD12			0x148 0x000 ALT4 0x0
+#define VF610_PAD_PTD3__SPDIF_PLOCK		0x148 0x000 ALT5 0x0
+#define VF610_PAD_PTD3__DEBUG_OUT20		0x148 0x000 ALT7 0x0
+#define VF610_PAD_PTD4__GPIO_83			0x14C 0x000 ALT0 0x0
+#define VF610_PAD_PTD4__QSPI0_A_DATA1		0x14C 0x000 ALT1 0x0
+#define VF610_PAD_PTD4__DSPI1_CS1		0x14C 0x000 ALT3 0x0
+#define VF610_PAD_PTD4__FB_AD11			0x14C 0x000 ALT4 0x0
+#define VF610_PAD_PTD4__SPDIF_SRCLK		0x14C 0x000 ALT5 0x0
+#define VF610_PAD_PTD4__DEBUG_OUT21		0x14C 0x000 ALT7 0x0
+#define VF610_PAD_PTD5__GPIO_84			0x150 0x000 ALT0 0x0
+#define VF610_PAD_PTD5__QSPI0_A_DATA0		0x150 0x000 ALT1 0x0
+#define VF610_PAD_PTD5__DSPI1_CS0		0x150 0x300 ALT3 0x1
+#define VF610_PAD_PTD5__FB_AD10			0x150 0x000 ALT4 0x0
+#define VF610_PAD_PTD5__DEBUG_OUT22		0x150 0x000 ALT7 0x0
+#define VF610_PAD_PTD6__GPIO_85			0x154 0x000 ALT0 0x0
+#define VF610_PAD_PTD6__QSPI1_A_DQS		0x154 0x000 ALT1 0x0
+#define VF610_PAD_PTD6__DSPI1_SIN		0x154 0x2FC ALT3 0x1
+#define VF610_PAD_PTD6__FB_AD9			0x154 0x000 ALT4 0x0
+#define VF610_PAD_PTD6__DEBUG_OUT23		0x154 0x000 ALT7 0x0
+#define VF610_PAD_PTD7__GPIO_86			0x158 0x000 ALT0 0x0
+#define VF610_PAD_PTD7__QSPI0_B_QSCK		0x158 0x000 ALT1 0x0
+#define VF610_PAD_PTD7__DSPI1_SOUT		0x158 0x000 ALT3 0x0
+#define VF610_PAD_PTD7__FB_AD8			0x158 0x000 ALT4 0x0
+#define VF610_PAD_PTD7__DEBUG_OUT24		0x158 0x000 ALT7 0x0
+#define VF610_PAD_PTD8__GPIO_87			0x15C 0x000 ALT0 0x0
+#define VF610_PAD_PTD8__QSPI0_B_CS0		0x15C 0x000 ALT1 0x0
+#define VF610_PAD_PTD8__FB_CLKOUT		0x15C 0x000 ALT2 0x0
+#define VF610_PAD_PTD8__DSPI1_SCK		0x15C 0x2F8 ALT3 0x1
+#define VF610_PAD_PTD8__FB_AD7			0x15C 0x000 ALT4 0x0
+#define VF610_PAD_PTD8__DEBUG_OUT25		0x15C 0x000 ALT7 0x0
+#define VF610_PAD_PTD9__GPIO_88			0x160 0x000 ALT0 0x0
+#define VF610_PAD_PTD9__QSPI0_B_DATA3		0x160 0x000 ALT1 0x0
+#define VF610_PAD_PTD9__DSPI3_CS1		0x160 0x000 ALT2 0x0
+#define VF610_PAD_PTD9__FB_AD6			0x160 0x000 ALT4 0x0
+#define VF610_PAD_PTD9__SAI1_TX_SYNC		0x160 0x360 ALT6 0x0
+#define VF610_PAD_PTD9__DCU1_B0			0x160 0x000 ALT7 0x0
+#define VF610_PAD_PTD10__GPIO_89		0x164 0x000 ALT0 0x0
+#define VF610_PAD_PTD10__QSPI0_B_DATA2		0x164 0x000 ALT1 0x0
+#define VF610_PAD_PTD10__DSPI3_CS0		0x164 0x000 ALT2 0x0
+#define VF610_PAD_PTD10__FB_AD5			0x164 0x000 ALT4 0x0
+#define VF610_PAD_PTD10__DCU1_B1		0x164 0x000 ALT7 0x0
+#define VF610_PAD_PTD11__GPIO_90		0x168 0x000 ALT0 0x0
+#define VF610_PAD_PTD11__QSPI0_B_DATA1		0x168 0x000 ALT1 0x0
+#define VF610_PAD_PTD11__DSPI3_SIN		0x168 0x000 ALT2 0x0
+#define VF610_PAD_PTD11__FB_AD4			0x168 0x000 ALT4 0x0
+#define VF610_PAD_PTD11__DEBUG_OUT26		0x168 0x000 ALT7 0x0
+#define VF610_PAD_PTD12__GPIO_91		0x16C 0x000 ALT0 0x0
+#define VF610_PAD_PTD12__QSPI0_B_DATA0		0x16C 0x000 ALT1 0x0
+#define VF610_PAD_PTD12__DSPI3_SOUT		0x16C 0x000 ALT2 0x0
+#define VF610_PAD_PTD12__FB_AD3			0x16C 0x000 ALT4 0x0
+#define VF610_PAD_PTD12__DEBUG_OUT27		0x16C 0x000 ALT7 0x0
+#define VF610_PAD_PTD13__GPIO_92		0x170 0x000 ALT0 0x0
+#define VF610_PAD_PTD13__QSPI0_B_DQS		0x170 0x000 ALT1 0x0
+#define VF610_PAD_PTD13__DSPI3_SCK		0x170 0x000 ALT2 0x0
+#define VF610_PAD_PTD13__FB_AD2			0x170 0x000 ALT4 0x0
+#define VF610_PAD_PTD13__DEBUG_OUT28		0x170 0x000 ALT7 0x0
+#define VF610_PAD_PTB23__GPIO_93		0x174 0x000 ALT0 0x0
+#define VF610_PAD_PTB23__SAI0_TX_BCLK		0x174 0x000 ALT1 0x0
+#define VF610_PAD_PTB23__UART1_TX		0x174 0x380 ALT2 0x2
+#define VF610_PAD_PTB23__SRC_RCON18		0x174 0x398 ALT3 0x1
+#define VF610_PAD_PTB23__FB_MUXED_ALE		0x174 0x000 ALT4 0x0
+#define VF610_PAD_PTB23__FB_TS_B		0x174 0x000 ALT5 0x0
+#define VF610_PAD_PTB23__UART3_RTS		0x174 0x000 ALT6 0x0
+#define VF610_PAD_PTB23__DCU1_G3		0x174 0x000 ALT7 0x0
+#define VF610_PAD_PTB24__GPIO_94		0x178 0x000 ALT0 0x0
+#define VF610_PAD_PTB24__SAI0_RX_BCLK		0x178 0x000 ALT1 0x0
+#define VF610_PAD_PTB24__UART1_RX		0x178 0x37C ALT2 0x2
+#define VF610_PAD_PTB24__SRC_RCON19		0x178 0x39C ALT3 0x1
+#define VF610_PAD_PTB24__FB_MUXED_TSIZ0		0x178 0x000 ALT4 0x0
+#define VF610_PAD_PTB24__NF_WE_B		0x178 0x000 ALT5 0x0
+#define VF610_PAD_PTB24__UART3_CTS		0x178 0x000 ALT6 0x0
+#define VF610_PAD_PTB24__DCU1_G4		0x178 0x000 ALT7 0x0
+#define VF610_PAD_PTB25__GPIO_95		0x17C 0x000 ALT0 0x0
+#define VF610_PAD_PTB25__SAI0_RX_DATA		0x17C 0x000 ALT1 0x0
+#define VF610_PAD_PTB25__UART1_RTS		0x17C 0x000 ALT2 0x0
+#define VF610_PAD_PTB25__SRC_RCON20		0x17C 0x3A0 ALT3 0x1
+#define VF610_PAD_PTB25__FB_CS1_B		0x17C 0x000 ALT4 0x0
+#define VF610_PAD_PTB25__NF_CE0_B		0x17C 0x000 ALT5 0x0
+#define VF610_PAD_PTB25__DCU1_G5		0x17C 0x000 ALT7 0x0
+#define VF610_PAD_PTB26__GPIO_96		0x180 0x000 ALT0 0x0
+#define VF610_PAD_PTB26__SAI0_TX_DATA		0x180 0x000 ALT1 0x0
+#define VF610_PAD_PTB26__UART1_CTS		0x180 0x378 ALT2 0x2
+#define VF610_PAD_PTB26__SRC_RCON21		0x180 0x000 ALT3 0x0
+#define VF610_PAD_PTB26__FB_CS0_B		0x180 0x000 ALT4 0x0
+#define VF610_PAD_PTB26__NF_CE1_B		0x180 0x000 ALT5 0x0
+#define VF610_PAD_PTB26__DCU1_G6		0x180 0x000 ALT7 0x0
+#define VF610_PAD_PTB27__GPIO_97		0x184 0x000 ALT0 0x0
+#define VF610_PAD_PTB27__SAI0_RX_SYNC		0x184 0x000 ALT1 0x0
+#define VF610_PAD_PTB27__SRC_RCON22		0x184 0x000 ALT3 0x0
+#define VF610_PAD_PTB27__FB_OE_B		0x184 0x000 ALT4 0x0
+#define VF610_PAD_PTB27__FB_MUXED_TBST_B	0x184 0x000 ALT5 0x0
+#define VF610_PAD_PTB27__NF_RE_B		0x184 0x000 ALT6 0x0
+#define VF610_PAD_PTB27__DCU1_G7		0x184 0x000 ALT7 0x0
+#define VF610_PAD_PTB28__GPIO_98		0x188 0x000 ALT0 0x0
+#define VF610_PAD_PTB28__SAI0_TX_SYNC		0x188 0x000 ALT1 0x0
+#define VF610_PAD_PTB28__SRC_RCON23		0x188 0x000 ALT3 0x0
+#define VF610_PAD_PTB28__FB_RW_B		0x188 0x000 ALT4 0x0
+#define VF610_PAD_PTB28__DCU1_B6		0x188 0x000 ALT7 0x0
+#define VF610_PAD_PTC26__GPIO_99		0x18C 0x000 ALT0 0x0
+#define VF610_PAD_PTC26__SAI1_TX_BCLK		0x18C 0x000 ALT1 0x0
+#define VF610_PAD_PTC26__DSPI0_CS5		0x18C 0x000 ALT2 0x0
+#define VF610_PAD_PTC26__SRC_RCON24		0x18C 0x000 ALT3 0x0
+#define VF610_PAD_PTC26__FB_TA_B		0x18C 0x000 ALT4 0x0
+#define VF610_PAD_PTC26__NF_RB_B		0x18C 0x000 ALT5 0x0
+#define VF610_PAD_PTC26__DCU1_B7		0x18C 0x000 ALT7 0x0
+#define VF610_PAD_PTC27__GPIO_100		0x190 0x000 ALT0 0x0
+#define VF610_PAD_PTC27__SAI1_RX_BCLK		0x190 0x000 ALT1 0x0
+#define VF610_PAD_PTC27__DSPI0_CS4		0x190 0x000 ALT2 0x0
+#define VF610_PAD_PTC27__SRC_RCON25		0x190 0x000 ALT3 0x0
+#define VF610_PAD_PTC27__FB_BE3_B		0x190 0x000 ALT4 0x0
+#define VF610_PAD_PTC27__FB_CS3_B		0x190 0x000 ALT5 0x0
+#define VF610_PAD_PTC27__NF_ALE			0x190 0x000 ALT6 0x0
+#define VF610_PAD_PTC27__DCU1_B2		0x190 0x000 ALT7 0x0
+#define VF610_PAD_PTC28__GPIO_101		0x194 0x000 ALT0 0x0
+#define VF610_PAD_PTC28__SAI1_RX_DATA		0x194 0x000 ALT1 0x0
+#define VF610_PAD_PTC28__DSPI0_CS3		0x194 0x000 ALT2 0x0
+#define VF610_PAD_PTC28__SRC_RCON26		0x194 0x000 ALT3 0x0
+#define VF610_PAD_PTC28__FB_BE2_B		0x194 0x000 ALT4 0x0
+#define VF610_PAD_PTC28__FB_CS2_B		0x194 0x000 ALT5 0x0
+#define VF610_PAD_PTC28__NF_CLE			0x194 0x000 ALT6 0x0
+#define VF610_PAD_PTC28__DCU1_B3		0x194 0x000 ALT7 0x0
+#define VF610_PAD_PTC29__GPIO_102		0x198 0x000 ALT0 0x0
+#define VF610_PAD_PTC29__SAI1_TX_DATA		0x198 0x000 ALT1 0x0
+#define VF610_PAD_PTC29__DSPI0_CS2		0x198 0x000 ALT2 0x0
+#define VF610_PAD_PTC29__SRC_RCON27		0x198 0x000 ALT3 0x0
+#define VF610_PAD_PTC29__FB_BE1_B		0x198 0x000 ALT4 0x0
+#define VF610_PAD_PTC29__FB_MUXED_TSIZE1	0x198 0x000 ALT5 0x0
+#define VF610_PAD_PTC29__DCU1_B4		0x198 0x000 ALT7 0x0
+#define VF610_PAD_PTC30__GPIO_103		0x19C 0x000 ALT0 0x0
+#define VF610_PAD_PTC30__SAI1_RX_SYNC		0x19C 0x000 ALT1 0x0
+#define VF610_PAD_PTC30__DSPI1_CS2		0x19C 0x000 ALT2 0x0
+#define VF610_PAD_PTC30__SRC_RCON28		0x19C 0x000 ALT3 0x0
+#define VF610_PAD_PTC30__FB_MUXED_BE0_B		0x19C 0x000 ALT4 0x0
+#define VF610_PAD_PTC30__FB_TSIZ0		0x19C 0x000 ALT5 0x0
+#define VF610_PAD_PTC30__ADC0_SE5		0x19C 0x000 ALT6 0x0
+#define VF610_PAD_PTC30__DCU1_B5		0x19C 0x000 ALT7 0x0
+#define VF610_PAD_PTC31__GPIO_104		0x1A0 0x000 ALT0 0x0
+#define VF610_PAD_PTC31__SAI1_TX_SYNC		0x1A0 0x360 ALT1 0x1
+#define VF610_PAD_PTC31__SRC_RCON29		0x1A0 0x000 ALT3 0x0
+#define VF610_PAD_PTC31__ADC1_SE5		0x1A0 0x000 ALT6 0x0
+#define VF610_PAD_PTC31__DCU1_B6		0x1A0 0x000 ALT7 0x0
+#define VF610_PAD_PTE0__GPIO_105		0x1A4 0x000 ALT0 0x0
+#define VF610_PAD_PTE0__DCU0_HSYNC		0x1A4 0x000 ALT1 0x0
+#define VF610_PAD_PTE0__SRC_BMODE1		0x1A4 0x000 ALT2 0x0
+#define VF610_PAD_PTE0__LCD0			0x1A4 0x000 ALT4 0x0
+#define VF610_PAD_PTE0__DEBUG_OUT29		0x1A4 0x000 ALT7 0x0
+#define VF610_PAD_PTE1__GPIO_106		0x1A8 0x000 ALT0 0x0
+#define VF610_PAD_PTE1__DCU0_VSYNC		0x1A8 0x000 ALT1 0x0
+#define VF610_PAD_PTE1__SRC_BMODE0		0x1A8 0x000 ALT2 0x0
+#define VF610_PAD_PTE1__LCD1			0x1A8 0x000 ALT4 0x0
+#define VF610_PAD_PTE1__DEBUG_OUT30		0x1A8 0x000 ALT7 0x0
+#define VF610_PAD_PTE2__GPIO_107		0x1AC 0x000 ALT0 0x0
+#define VF610_PAD_PTE2__DCU0_PCLK		0x1AC 0x000 ALT1 0x0
+#define VF610_PAD_PTE2__LCD2			0x1AC 0x000 ALT4 0x0
+#define VF610_PAD_PTE2__DEBUG_OUT31		0x1AC 0x000 ALT7 0x0
+#define VF610_PAD_PTE3__GPIO_108		0x1B0 0x000 ALT0 0x0
+#define VF610_PAD_PTE3__DCU0_TAG		0x1B0 0x000 ALT1 0x0
+#define VF610_PAD_PTE3__LCD3			0x1B0 0x000 ALT4 0x0
+#define VF610_PAD_PTE3__DEBUG_OUT32		0x1B0 0x000 ALT7 0x0
+#define VF610_PAD_PTE4__GPIO_109		0x1B4 0x000 ALT0 0x0
+#define VF610_PAD_PTE4__DCU0_DE			0x1B4 0x000 ALT1 0x0
+#define VF610_PAD_PTE4__LCD4			0x1B4 0x000 ALT4 0x0
+#define VF610_PAD_PTE4__DEBUG_OUT33		0x1B4 0x000 ALT7 0x0
+#define VF610_PAD_PTE5__GPIO_110		0x1B8 0x000 ALT0 0x0
+#define VF610_PAD_PTE5__DCU0_R0			0x1B8 0x000 ALT1 0x0
+#define VF610_PAD_PTE5__LCD5			0x1B8 0x000 ALT4 0x0
+#define VF610_PAD_PTE5__DEBUG_OUT34		0x1B8 0x000 ALT7 0x0
+#define VF610_PAD_PTE6__GPIO_111		0x1BC 0x000 ALT0 0x0
+#define VF610_PAD_PTE6__DCU0_R1			0x1BC 0x000 ALT1 0x0
+#define VF610_PAD_PTE6__LCD6			0x1BC 0x000 ALT4 0x0
+#define VF610_PAD_PTE6__DEBUG_OUT35		0x1BC 0x000 ALT7 0x0
+#define VF610_PAD_PTE7__GPIO_112		0x1C0 0x000 ALT0 0x0
+#define VF610_PAD_PTE7__DCU0_R2			0x1C0 0x000 ALT1 0x0
+#define VF610_PAD_PTE7__SRC_RCON0		0x1C0 0x000 ALT3 0x0
+#define VF610_PAD_PTE7__LCD7			0x1C0 0x000 ALT4 0x0
+#define VF610_PAD_PTE7__DEBUG_OUT36		0x1C0 0x000 ALT7 0x0
+#define VF610_PAD_PTE8__GPIO_113		0x1C4 0x000 ALT0 0x0
+#define VF610_PAD_PTE8__DCU0_R3			0x1C4 0x000 ALT1 0x0
+#define VF610_PAD_PTE8__SRC_RCON1		0x1C4 0x000 ALT3 0x0
+#define VF610_PAD_PTE8__LCD8			0x1C4 0x000 ALT4 0x0
+#define VF610_PAD_PTE8__DEBUG_OUT37		0x1C4 0x000 ALT7 0x0
+#define VF610_PAD_PTE9__GPIO_114		0x1C8 0x000 ALT0 0x0
+#define VF610_PAD_PTE9__DCU0_R4			0x1C8 0x000 ALT1 0x0
+#define VF610_PAD_PTE9__SRC_RCON2		0x1C8 0x000 ALT3 0x0
+#define VF610_PAD_PTE9__LCD9			0x1C8 0x000 ALT4 0x0
+#define VF610_PAD_PTE9__DEBUG_OUT38		0x1C8 0x000 ALT7 0x0
+#define VF610_PAD_PTE10__GPIO_115		0x1CC 0x000 ALT0 0x0
+#define VF610_PAD_PTE10__DCU0_R5		0x1CC 0x000 ALT1 0x0
+#define VF610_PAD_PTE10__SRC_RCON3		0x1CC 0x000 ALT3 0x0
+#define VF610_PAD_PTE10__LCD10			0x1CC 0x000 ALT4 0x0
+#define VF610_PAD_PTE10__DEBUG_OUT39		0x1CC 0x000 ALT7 0x0
+#define VF610_PAD_PTE11__GPIO_116		0x1D0 0x000 ALT0 0x0
+#define VF610_PAD_PTE11__DCU0_R6		0x1D0 0x000 ALT1 0x0
+#define VF610_PAD_PTE11__SRC_RCON4		0x1D0 0x000 ALT3 0x0
+#define VF610_PAD_PTE11__LCD11			0x1D0 0x000 ALT4 0x0
+#define VF610_PAD_PTE11__DEBUG_OUT40		0x1D0 0x000 ALT7 0x0
+#define VF610_PAD_PTE12__GPIO_117		0x1D4 0x000 ALT0 0x0
+#define VF610_PAD_PTE12__DCU0_R7		0x1D4 0x000 ALT1 0x0
+#define VF610_PAD_PTE12__DSPI1_CS3		0x1D4 0x000 ALT2 0x0
+#define VF610_PAD_PTE12__SRC_RCON5		0x1D4 0x000 ALT3 0x0
+#define VF610_PAD_PTE12__LCD12			0x1D4 0x000 ALT4 0x0
+#define VF610_PAD_PTE12__LPT_ALT0		0x1D4 0x000 ALT7 0x0
+#define VF610_PAD_PTE13__GPIO_118		0x1D8 0x000 ALT0 0x0
+#define VF610_PAD_PTE13__DCU0_G0		0x1D8 0x000 ALT1 0x0
+#define VF610_PAD_PTE13__LCD13			0x1D8 0x000 ALT4 0x0
+#define VF610_PAD_PTE13__DEBUG_OUT41		0x1D8 0x000 ALT7 0x0
+#define VF610_PAD_PTE14__GPIO_119		0x1DC 0x000 ALT0 0x0
+#define VF610_PAD_PTE14__DCU0_G1		0x1DC 0x000 ALT1 0x0
+#define VF610_PAD_PTE14__LCD14			0x1DC 0x000 ALT4 0x0
+#define VF610_PAD_PTE14__DEBUG_OUT42		0x1DC 0x000 ALT7 0x0
+#define VF610_PAD_PTE15__GPIO_120		0x1E0 0x000 ALT0 0x0
+#define VF610_PAD_PTE15__DCU0_G2		0x1E0 0x000 ALT1 0x0
+#define VF610_PAD_PTE15__SRC_RCON6		0x1E0 0x000 ALT3 0x0
+#define VF610_PAD_PTE15__LCD15			0x1E0 0x000 ALT4 0x0
+#define VF610_PAD_PTE15__DEBUG_OUT43		0x1E0 0x000 ALT7 0x0
+#define VF610_PAD_PTE16__GPIO_121		0x1E4 0x000 ALT0 0x0
+#define VF610_PAD_PTE16__DCU0_G3		0x1E4 0x000 ALT1 0x0
+#define VF610_PAD_PTE16__SRC_RCON7		0x1E4 0x000 ALT3 0x0
+#define VF610_PAD_PTE16__LCD16			0x1E4 0x000 ALT4 0x0
+#define VF610_PAD_PTE17__GPIO_122		0x1E8 0x000 ALT0 0x0
+#define VF610_PAD_PTE17__DCU0_G4		0x1E8 0x000 ALT1 0x0
+#define VF610_PAD_PTE17__SRC_RCON8		0x1E8 0x000 ALT3 0x0
+#define VF610_PAD_PTE17__LCD17			0x1E8 0x000 ALT4 0x0
+#define VF610_PAD_PTE18__GPIO_123		0x1EC 0x000 ALT0 0x0
+#define VF610_PAD_PTE18__DCU0_G5		0x1EC 0x000 ALT1 0x0
+#define VF610_PAD_PTE18__SRC_RCON9		0x1EC 0x000 ALT3 0x0
+#define VF610_PAD_PTE18__LCD18			0x1EC 0x000 ALT4 0x0
+#define VF610_PAD_PTE19__GPIO_124		0x1F0 0x000 ALT0 0x0
+#define VF610_PAD_PTE19__DCU0_G6		0x1F0 0x000 ALT1 0x0
+#define VF610_PAD_PTE19__SRC_RCON10		0x1F0 0x000 ALT3 0x0
+#define VF610_PAD_PTE19__LCD19			0x1F0 0x000 ALT4 0x0
+#define VF610_PAD_PTE19__I2C0_SCL		0x1F0 0x33C ALT5 0x3
+#define VF610_PAD_PTE20__GPIO_125		0x1F4 0x000 ALT0 0x0
+#define VF610_PAD_PTE20__DCU0_G7		0x1F4 0x000 ALT1 0x0
+#define VF610_PAD_PTE20__SRC_RCON11		0x1F4 0x000 ALT3 0x0
+#define VF610_PAD_PTE20__LCD20			0x1F4 0x000 ALT4 0x0
+#define VF610_PAD_PTE20__I2C0_SDA		0x1F4 0x340 ALT5 0x3
+#define VF610_PAD_PTE20__EWM_IN			0x1F4 0x000 ALT7 0x0
+#define VF610_PAD_PTE21__GPIO_126		0x1F8 0x000 ALT0 0x0
+#define VF610_PAD_PTE21__DCU0_B0		0x1F8 0x000 ALT1 0x0
+#define VF610_PAD_PTE21__LCD21			0x1F8 0x000 ALT4 0x0
+#define VF610_PAD_PTE22__GPIO_127		0x1FC 0x000 ALT0 0x0
+#define VF610_PAD_PTE22__DCU0_B1		0x1FC 0x000 ALT1 0x0
+#define VF610_PAD_PTE22__LCD22			0x1FC 0x000 ALT4 0x0
+#define VF610_PAD_PTE23__GPIO_128		0x200 0x000 ALT0 0x0
+#define VF610_PAD_PTE23__DCU0_B2		0x200 0x000 ALT1 0x0
+#define VF610_PAD_PTE23__SRC_RCON12		0x200 0x000 ALT3 0x0
+#define VF610_PAD_PTE23__LCD23			0x200 0x000 ALT4 0x0
+#define VF610_PAD_PTE24__GPIO_129		0x204 0x000 ALT0 0x0
+#define VF610_PAD_PTE24__DCU0_B3		0x204 0x000 ALT1 0x0
+#define VF610_PAD_PTE24__SRC_RCON13		0x204 0x000 ALT3 0x0
+#define VF610_PAD_PTE24__LCD24			0x204 0x000 ALT4 0x0
+#define VF610_PAD_PTE25__GPIO_130		0x208 0x000 ALT0 0x0
+#define VF610_PAD_PTE25__DCU0_B4		0x208 0x000 ALT1 0x0
+#define VF610_PAD_PTE25__SRC_RCON14		0x208 0x000 ALT3 0x0
+#define VF610_PAD_PTE25__LCD25			0x208 0x000 ALT4 0x0
+#define VF610_PAD_PTE26__GPIO_131		0x20C 0x000 ALT0 0x0
+#define VF610_PAD_PTE26__DCU0_B5		0x20C 0x000 ALT1 0x0
+#define VF610_PAD_PTE26__SRC_RCON15		0x20C 0x000 ALT3 0x0
+#define VF610_PAD_PTE26__LCD26			0x20C 0x000 ALT4 0x0
+#define VF610_PAD_PTE27__GPIO_132		0x210 0x000 ALT0 0x0
+#define VF610_PAD_PTE27__DCU0_B6		0x210 0x000 ALT1 0x0
+#define VF610_PAD_PTE27__SRC_RCON16		0x210 0x000 ALT3 0x0
+#define VF610_PAD_PTE27__LCD27			0x210 0x000 ALT4 0x0
+#define VF610_PAD_PTE27__I2C1_SCL		0x210 0x344 ALT5 0x3
+#define VF610_PAD_PTE28__GPIO_133		0x214 0x000 ALT0 0x0
+#define VF610_PAD_PTE28__DCU0_B7		0x214 0x000 ALT1 0x0
+#define VF610_PAD_PTE28__SRC_RCON17		0x214 0x000 ALT3 0x0
+#define VF610_PAD_PTE28__LCD28			0x214 0x000 ALT4 0x0
+#define VF610_PAD_PTE28__I2C1_SDA		0x214 0x348 ALT5 0x3
+#define VF610_PAD_PTE28__EWM_OUT		0x214 0x000 ALT7 0x0
+#define VF610_PAD_PTA7__GPIO_134		0x218 0x000 ALT0 0x0
+#define VF610_PAD_PTA7__VIU_PIX_CLK		0x218 0x3AC ALT1 0x1
+
+#endif
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/adxl34x/Makefile b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/adxl34x/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..be27a431c728b6492801b71e7bc0114944898134
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/adxl34x/Makefile
@@ -0,0 +1,42 @@
+#
+# Peter Yang <turmary@126.com>
+# Copyright (c) 2019 Seeed Studio
+#
+# MIT License
+#
+
+# no irq version
+_tgt     := adxl34x
+
+_uname_r := $(shell uname -r)
+_BUILD   := /lib/modules/$(_uname_r)/build
+_PWD     := $(shell pwd)
+_DEPMOD  ?= depmod -a
+
+# If KERNELRELEASE is defined, we've been invoked from the
+# kernel build system and can use its language
+ifneq ($(KERNELRELEASE),)
+
+obj-m += ${_tgt}.o
+
+else
+_class  := drivers/input/misc
+
+DEST  := /lib/modules/$(_uname_r)/kernel
+
+all:
+	make -C ${_BUILD} M=$(_PWD) modules
+
+clean:
+	make -C ${_BUILD} M=$(_PWD) clean
+
+install:
+	cp ${_tgt}.ko ${DEST}/${_class}/
+	$(_DEPMOD)
+
+uninstall:
+	rm -f ${DEST}/${_class}/${_tgt}.ko
+	$(_DEPMOD)
+
+.PHONY: all clean install uninstall
+endif
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/adxl34x/README.md b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/adxl34x/README.md
new file mode 100644
index 0000000000000000000000000000000000000000..6ef6608fb40e1920ac23307aec9f1d3e3a811f4f
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/adxl34x/README.md
@@ -0,0 +1,63 @@
+GROVE 3-Axis Digital Accelerometer(+-16g)
+=========================================
+
+  After driver and configuration prepared well,
+  the user could access ```/dev/input/event<N>```,
+  to capture the accelerometer event.
+
+  For more description of ```/dev/input/event<N>```, refer to
+  [input](https://github.com/raspberrypi/linux/blob/rpi-4.14.y/Documentation/input/input.rst).
+
+Usage
+-----
+
+***example:***
+
+  ```bash
+  sudo apt-get install evtest
+
+  evtest
+  # now select the number <N> of event<N>
+  # then move the sensor,
+  #
+  # see the evtest output, unit in 1/256 g.
+
+  Input driver version is 1.0.1
+  Input device ID: bus 0x18 vendor 0x0 product 0x159 version 0x0
+  Input device name: "ADXL34x accelerometer"
+  Supported events:
+  Event type 0 (EV_SYN)
+  Event type 1 (EV_KEY)
+    Event code 330 (BTN_TOUCH)
+  Event type 3 (EV_ABS)
+    Event code 0 (ABS_X)
+      Value      2
+      Min    -4096
+      Max     4096
+      Fuzz       3
+      Flat       3
+    Event code 1 (ABS_Y)
+      Value    -28
+      Min    -4096
+      Max     4096
+      Fuzz       3
+      Flat       3
+    Event code 2 (ABS_Z)
+      Value    254
+      Min    -4096
+      Max     4096
+      Fuzz       3
+      Flat       3
+  Properties:
+  Testing ... (interrupt to exit)
+  Event: time 1552637001.573312, type 3 (EV_ABS), code 0 (ABS_X), value -81
+  Event: time 1552637001.573312, type 3 (EV_ABS), code 1 (ABS_Y), value -114
+  Event: time 1552637001.573312, type 3 (EV_ABS), code 2 (ABS_Z), value 203
+  Event: time 1552637001.573312, -------------- SYN_REPORT ------------
+  Event: time 1552637001.621290, type 3 (EV_ABS), code 0 (ABS_X), value -82
+  Event: time 1552637001.621290, type 3 (EV_ABS), code 1 (ABS_Y), value -116
+  Event: time 1552637001.621290, type 3 (EV_ABS), code 2 (ABS_Z), value 214
+  ```
+
+  If you need customize the I2C-Port..., change it the device tree source.
+
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/adxl34x/adxl34x-i2c.c b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/adxl34x/adxl34x-i2c.c
new file mode 100644
index 0000000000000000000000000000000000000000..a8b0a2eec344e863bd292251095a4e84f3a0b98b
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/adxl34x/adxl34x-i2c.c
@@ -0,0 +1,173 @@
+/*
+ * ADLX345/346 Three-Axis Digital Accelerometers (I2C Interface)
+ *
+ * Enter bugs at http://blackfin.uclinux.org/
+ *
+ * Copyright (C) 2009 Michael Hennerich, Analog Devices Inc.
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <linux/input.h>	/* BUS_I2C */
+#include <linux/i2c.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/types.h>
+#include <linux/pm.h>
+#include "adxl34x.h"
+
+static int adxl34x_smbus_read(struct device *dev, unsigned char reg)
+{
+	struct i2c_client *client = to_i2c_client(dev);
+
+	return i2c_smbus_read_byte_data(client, reg);
+}
+
+static int adxl34x_smbus_write(struct device *dev,
+			       unsigned char reg, unsigned char val)
+{
+	struct i2c_client *client = to_i2c_client(dev);
+
+	return i2c_smbus_write_byte_data(client, reg, val);
+}
+
+static int adxl34x_smbus_read_block(struct device *dev,
+				    unsigned char reg, int count,
+				    void *buf)
+{
+	struct i2c_client *client = to_i2c_client(dev);
+
+	return i2c_smbus_read_i2c_block_data(client, reg, count, buf);
+}
+
+static int adxl34x_i2c_read_block(struct device *dev,
+				  unsigned char reg, int count,
+				  void *buf)
+{
+	struct i2c_client *client = to_i2c_client(dev);
+	int ret;
+
+	ret = i2c_master_send(client, &reg, 1);
+	if (ret < 0)
+		return ret;
+
+	ret = i2c_master_recv(client, buf, count);
+	if (ret < 0)
+		return ret;
+
+	if (ret != count)
+		return -EIO;
+
+	return 0;
+}
+
+static const struct adxl34x_bus_ops adxl34x_smbus_bops = {
+	.bustype	= BUS_I2C,
+	.write		= adxl34x_smbus_write,
+	.read		= adxl34x_smbus_read,
+	.read_block	= adxl34x_smbus_read_block,
+};
+
+static const struct adxl34x_bus_ops adxl34x_i2c_bops = {
+	.bustype	= BUS_I2C,
+	.write		= adxl34x_smbus_write,
+	.read		= adxl34x_smbus_read,
+	.read_block	= adxl34x_i2c_read_block,
+};
+
+static int adxl34x_i2c_probe(struct i2c_client *client,
+				       const struct i2c_device_id *id)
+{
+	struct adxl34x *ac;
+	int error;
+
+	error = i2c_check_functionality(client->adapter,
+			I2C_FUNC_SMBUS_BYTE_DATA);
+	if (!error) {
+		dev_err(&client->dev, "SMBUS Byte Data not Supported\n");
+		return -EIO;
+	}
+
+	ac = adxl34x_probe(&client->dev, client->irq, false,
+			   i2c_check_functionality(client->adapter,
+						   I2C_FUNC_SMBUS_READ_I2C_BLOCK) ?
+				&adxl34x_smbus_bops : &adxl34x_i2c_bops);
+	if (IS_ERR(ac))
+		return PTR_ERR(ac);
+
+	i2c_set_clientdata(client, ac);
+
+	return 0;
+}
+
+static int adxl34x_i2c_remove(struct i2c_client *client)
+{
+	struct adxl34x *ac = i2c_get_clientdata(client);
+
+	return adxl34x_remove(ac);
+}
+
+static int __maybe_unused adxl34x_i2c_suspend(struct device *dev)
+{
+	struct i2c_client *client = to_i2c_client(dev);
+	struct adxl34x *ac = i2c_get_clientdata(client);
+
+	adxl34x_suspend(ac);
+
+	return 0;
+}
+
+static int __maybe_unused adxl34x_i2c_resume(struct device *dev)
+{
+	struct i2c_client *client = to_i2c_client(dev);
+	struct adxl34x *ac = i2c_get_clientdata(client);
+
+	adxl34x_resume(ac);
+
+	return 0;
+}
+
+static SIMPLE_DEV_PM_OPS(adxl34x_i2c_pm, adxl34x_i2c_suspend,
+			 adxl34x_i2c_resume);
+
+static const struct i2c_device_id adxl34x_id[] = {
+	{ "adxl34x", 0 },
+	{ }
+};
+
+MODULE_DEVICE_TABLE(i2c, adxl34x_id);
+
+#ifdef CONFIG_OF
+static const struct of_device_id adxl34x_of_id[] = {
+	/*
+	 * The ADXL346 is backward-compatible with the ADXL345. Differences are
+	 * handled by runtime detection of the device model, there's thus no
+	 * need for listing the "adi,adxl346" compatible value explicitly.
+	 */
+	{ .compatible = "adi,adxl345", },
+	/*
+	 * Deprecated, DT nodes should use one or more of the device-specific
+	 * compatible values "adi,adxl345" and "adi,adxl346".
+	 */
+	{ .compatible = "adi,adxl34x", },
+	{ }
+};
+
+MODULE_DEVICE_TABLE(of, adxl34x_of_id);
+#endif
+
+static struct i2c_driver adxl34x_driver = {
+	.driver = {
+		.name = "adxl34x",
+		.pm = &adxl34x_i2c_pm,
+		.of_match_table = of_match_ptr(adxl34x_of_id),
+	},
+	.probe    = adxl34x_i2c_probe,
+	.remove   = adxl34x_i2c_remove,
+	.id_table = adxl34x_id,
+};
+
+module_i2c_driver(adxl34x_driver);
+
+MODULE_AUTHOR("Michael Hennerich <hennerich@blackfin.uclinux.org>");
+MODULE_DESCRIPTION("ADXL345/346 Three-Axis Digital Accelerometer I2C Bus Driver");
+MODULE_LICENSE("GPL");
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/adxl34x/adxl34x-spi.c b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/adxl34x/adxl34x-spi.c
new file mode 100644
index 0000000000000000000000000000000000000000..3ec03ad88eed35eb59651ada00a003937687419d
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/adxl34x/adxl34x-spi.c
@@ -0,0 +1,133 @@
+/*
+ * ADLX345/346 Three-Axis Digital Accelerometers (SPI Interface)
+ *
+ * Enter bugs at http://blackfin.uclinux.org/
+ *
+ * Copyright (C) 2009 Michael Hennerich, Analog Devices Inc.
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <linux/input.h>	/* BUS_SPI */
+#include <linux/module.h>
+#include <linux/spi/spi.h>
+#include <linux/pm.h>
+#include <linux/types.h>
+#include "adxl34x.h"
+
+#define MAX_SPI_FREQ_HZ		5000000
+#define MAX_FREQ_NO_FIFODELAY	1500000
+#define ADXL34X_CMD_MULTB	(1 << 6)
+#define ADXL34X_CMD_READ	(1 << 7)
+#define ADXL34X_WRITECMD(reg)	(reg & 0x3F)
+#define ADXL34X_READCMD(reg)	(ADXL34X_CMD_READ | (reg & 0x3F))
+#define ADXL34X_READMB_CMD(reg) (ADXL34X_CMD_READ | ADXL34X_CMD_MULTB \
+					| (reg & 0x3F))
+
+static int adxl34x_spi_read(struct device *dev, unsigned char reg)
+{
+	struct spi_device *spi = to_spi_device(dev);
+	unsigned char cmd;
+
+	cmd = ADXL34X_READCMD(reg);
+
+	return spi_w8r8(spi, cmd);
+}
+
+static int adxl34x_spi_write(struct device *dev,
+			     unsigned char reg, unsigned char val)
+{
+	struct spi_device *spi = to_spi_device(dev);
+	unsigned char buf[2];
+
+	buf[0] = ADXL34X_WRITECMD(reg);
+	buf[1] = val;
+
+	return spi_write(spi, buf, sizeof(buf));
+}
+
+static int adxl34x_spi_read_block(struct device *dev,
+				  unsigned char reg, int count,
+				  void *buf)
+{
+	struct spi_device *spi = to_spi_device(dev);
+	ssize_t status;
+
+	reg = ADXL34X_READMB_CMD(reg);
+	status = spi_write_then_read(spi, &reg, 1, buf, count);
+
+	return (status < 0) ? status : 0;
+}
+
+static const struct adxl34x_bus_ops adxl34x_spi_bops = {
+	.bustype	= BUS_SPI,
+	.write		= adxl34x_spi_write,
+	.read		= adxl34x_spi_read,
+	.read_block	= adxl34x_spi_read_block,
+};
+
+static int adxl34x_spi_probe(struct spi_device *spi)
+{
+	struct adxl34x *ac;
+
+	/* don't exceed max specified SPI CLK frequency */
+	if (spi->max_speed_hz > MAX_SPI_FREQ_HZ) {
+		dev_err(&spi->dev, "SPI CLK %d Hz too fast\n", spi->max_speed_hz);
+		return -EINVAL;
+	}
+
+	ac = adxl34x_probe(&spi->dev, spi->irq,
+			   spi->max_speed_hz > MAX_FREQ_NO_FIFODELAY,
+			   &adxl34x_spi_bops);
+
+	if (IS_ERR(ac))
+		return PTR_ERR(ac);
+
+	spi_set_drvdata(spi, ac);
+
+	return 0;
+}
+
+static int adxl34x_spi_remove(struct spi_device *spi)
+{
+	struct adxl34x *ac = spi_get_drvdata(spi);
+
+	return adxl34x_remove(ac);
+}
+
+static int __maybe_unused adxl34x_spi_suspend(struct device *dev)
+{
+	struct spi_device *spi = to_spi_device(dev);
+	struct adxl34x *ac = spi_get_drvdata(spi);
+
+	adxl34x_suspend(ac);
+
+	return 0;
+}
+
+static int __maybe_unused adxl34x_spi_resume(struct device *dev)
+{
+	struct spi_device *spi = to_spi_device(dev);
+	struct adxl34x *ac = spi_get_drvdata(spi);
+
+	adxl34x_resume(ac);
+
+	return 0;
+}
+
+static SIMPLE_DEV_PM_OPS(adxl34x_spi_pm, adxl34x_spi_suspend,
+			 adxl34x_spi_resume);
+
+static struct spi_driver adxl34x_driver = {
+	.driver = {
+		.name = "adxl34x",
+		.pm = &adxl34x_spi_pm,
+	},
+	.probe   = adxl34x_spi_probe,
+	.remove  = adxl34x_spi_remove,
+};
+
+module_spi_driver(adxl34x_driver);
+
+MODULE_AUTHOR("Michael Hennerich <hennerich@blackfin.uclinux.org>");
+MODULE_DESCRIPTION("ADXL345/346 Three-Axis Digital Accelerometer SPI Bus Driver");
+MODULE_LICENSE("GPL");
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/adxl34x/adxl34x.c b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/adxl34x/adxl34x.c
new file mode 100644
index 0000000000000000000000000000000000000000..8405937d5c39cd6c33cfe42747448be8b92245f9
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/adxl34x/adxl34x.c
@@ -0,0 +1,1001 @@
+/*
+ * ADXL345/346 Three-Axis Digital Accelerometers
+ *
+ * Enter bugs at http://blackfin.uclinux.org/
+ *
+ * Copyright (C) 2009 Michael Hennerich, Analog Devices Inc.
+ *
+ * Copyright (c) 2019 Seeed Studio
+ * Peter Yang <turmary@126.com>
+ *   Add polling (no irq) support
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <linux/device.h>
+#include <linux/delay.h>
+#include <linux/input.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/slab.h>
+#include <linux/workqueue.h>
+#include <linux/input/adxl34x.h>
+#include <linux/module.h>
+
+#include "adxl34x.h"
+
+/* ADXL345/6 Register Map */
+#define DEVID		0x00	/* R   Device ID */
+#define THRESH_TAP	0x1D	/* R/W Tap threshold */
+#define OFSX		0x1E	/* R/W X-axis offset */
+#define OFSY		0x1F	/* R/W Y-axis offset */
+#define OFSZ		0x20	/* R/W Z-axis offset */
+#define DUR		0x21	/* R/W Tap duration */
+#define LATENT		0x22	/* R/W Tap latency */
+#define WINDOW		0x23	/* R/W Tap window */
+#define THRESH_ACT	0x24	/* R/W Activity threshold */
+#define THRESH_INACT	0x25	/* R/W Inactivity threshold */
+#define TIME_INACT	0x26	/* R/W Inactivity time */
+#define ACT_INACT_CTL	0x27	/* R/W Axis enable control for activity and */
+				/* inactivity detection */
+#define THRESH_FF	0x28	/* R/W Free-fall threshold */
+#define TIME_FF		0x29	/* R/W Free-fall time */
+#define TAP_AXES	0x2A	/* R/W Axis control for tap/double tap */
+#define ACT_TAP_STATUS	0x2B	/* R   Source of tap/double tap */
+#define BW_RATE		0x2C	/* R/W Data rate and power mode control */
+#define POWER_CTL	0x2D	/* R/W Power saving features control */
+#define INT_ENABLE	0x2E	/* R/W Interrupt enable control */
+#define INT_MAP		0x2F	/* R/W Interrupt mapping control */
+#define INT_SOURCE	0x30	/* R   Source of interrupts */
+#define DATA_FORMAT	0x31	/* R/W Data format control */
+#define DATAX0		0x32	/* R   X-Axis Data 0 */
+#define DATAX1		0x33	/* R   X-Axis Data 1 */
+#define DATAY0		0x34	/* R   Y-Axis Data 0 */
+#define DATAY1		0x35	/* R   Y-Axis Data 1 */
+#define DATAZ0		0x36	/* R   Z-Axis Data 0 */
+#define DATAZ1		0x37	/* R   Z-Axis Data 1 */
+#define FIFO_CTL	0x38	/* R/W FIFO control */
+#define FIFO_STATUS	0x39	/* R   FIFO status */
+#define TAP_SIGN	0x3A	/* R   Sign and source for tap/double tap */
+/* Orientation ADXL346 only */
+#define ORIENT_CONF	0x3B	/* R/W Orientation configuration */
+#define ORIENT		0x3C	/* R   Orientation status */
+
+/* DEVIDs */
+#define ID_ADXL345	0xE5
+#define ID_ADXL346	0xE6
+
+/* INT_ENABLE/INT_MAP/INT_SOURCE Bits */
+#define DATA_READY	(1 << 7)
+#define SINGLE_TAP	(1 << 6)
+#define DOUBLE_TAP	(1 << 5)
+#define ACTIVITY	(1 << 4)
+#define INACTIVITY	(1 << 3)
+#define FREE_FALL	(1 << 2)
+#define WATERMARK	(1 << 1)
+#define OVERRUN		(1 << 0)
+
+/* ACT_INACT_CONTROL Bits */
+#define ACT_ACDC	(1 << 7)
+#define ACT_X_EN	(1 << 6)
+#define ACT_Y_EN	(1 << 5)
+#define ACT_Z_EN	(1 << 4)
+#define INACT_ACDC	(1 << 3)
+#define INACT_X_EN	(1 << 2)
+#define INACT_Y_EN	(1 << 1)
+#define INACT_Z_EN	(1 << 0)
+
+/* TAP_AXES Bits */
+#define SUPPRESS	(1 << 3)
+#define TAP_X_EN	(1 << 2)
+#define TAP_Y_EN	(1 << 1)
+#define TAP_Z_EN	(1 << 0)
+
+/* ACT_TAP_STATUS Bits */
+#define ACT_X_SRC	(1 << 6)
+#define ACT_Y_SRC	(1 << 5)
+#define ACT_Z_SRC	(1 << 4)
+#define ASLEEP		(1 << 3)
+#define TAP_X_SRC	(1 << 2)
+#define TAP_Y_SRC	(1 << 1)
+#define TAP_Z_SRC	(1 << 0)
+
+/* BW_RATE Bits */
+#define LOW_POWER	(1 << 4)
+#define RATE(x)		((x) & 0xF)
+
+/* POWER_CTL Bits */
+#define PCTL_LINK	(1 << 5)
+#define PCTL_AUTO_SLEEP (1 << 4)
+#define PCTL_MEASURE	(1 << 3)
+#define PCTL_SLEEP	(1 << 2)
+#define PCTL_WAKEUP(x)	((x) & 0x3)
+
+/* DATA_FORMAT Bits */
+#define SELF_TEST	(1 << 7)
+#define SPI		(1 << 6)
+#define INT_INVERT	(1 << 5)
+#define FULL_RES	(1 << 3)
+#define JUSTIFY		(1 << 2)
+#define RANGE(x)	((x) & 0x3)
+#define RANGE_PM_2g	0
+#define RANGE_PM_4g	1
+#define RANGE_PM_8g	2
+#define RANGE_PM_16g	3
+
+/*
+ * Maximum value our axis may get in full res mode for the input device
+ * (signed 13 bits)
+ */
+#define ADXL_FULLRES_MAX_VAL 4096
+
+/*
+ * Maximum value our axis may get in fixed res mode for the input device
+ * (signed 10 bits)
+ */
+#define ADXL_FIXEDRES_MAX_VAL 512
+
+/* FIFO_CTL Bits */
+#define FIFO_MODE(x)	(((x) & 0x3) << 6)
+#define FIFO_BYPASS	0
+#define FIFO_FIFO	1
+#define FIFO_STREAM	2
+#define FIFO_TRIGGER	3
+#define TRIGGER		(1 << 5)
+#define SAMPLES(x)	((x) & 0x1F)
+
+/* FIFO_STATUS Bits */
+#define FIFO_TRIG	(1 << 7)
+#define ENTRIES(x)	((x) & 0x3F)
+
+/* TAP_SIGN Bits ADXL346 only */
+#define XSIGN		(1 << 6)
+#define YSIGN		(1 << 5)
+#define ZSIGN		(1 << 4)
+#define XTAP		(1 << 3)
+#define YTAP		(1 << 2)
+#define ZTAP		(1 << 1)
+
+/* ORIENT_CONF ADXL346 only */
+#define ORIENT_DEADZONE(x)	(((x) & 0x7) << 4)
+#define ORIENT_DIVISOR(x)	((x) & 0x7)
+
+/* ORIENT ADXL346 only */
+#define ADXL346_2D_VALID		(1 << 6)
+#define ADXL346_2D_ORIENT(x)		(((x) & 0x30) >> 4)
+#define ADXL346_3D_VALID		(1 << 3)
+#define ADXL346_3D_ORIENT(x)		((x) & 0x7)
+#define ADXL346_2D_PORTRAIT_POS		0	/* +X */
+#define ADXL346_2D_PORTRAIT_NEG		1	/* -X */
+#define ADXL346_2D_LANDSCAPE_POS	2	/* +Y */
+#define ADXL346_2D_LANDSCAPE_NEG	3	/* -Y */
+
+#define ADXL346_3D_FRONT		3	/* +X */
+#define ADXL346_3D_BACK			4	/* -X */
+#define ADXL346_3D_RIGHT		2	/* +Y */
+#define ADXL346_3D_LEFT			5	/* -Y */
+#define ADXL346_3D_TOP			1	/* +Z */
+#define ADXL346_3D_BOTTOM		6	/* -Z */
+
+#undef ADXL_DEBUG
+
+#define ADXL_X_AXIS			0
+#define ADXL_Y_AXIS			1
+#define ADXL_Z_AXIS			2
+
+#define AC_READ(ac, reg)	((ac)->bops->read((ac)->dev, reg))
+#define AC_WRITE(ac, reg, val)	((ac)->bops->write((ac)->dev, reg, val))
+
+struct axis_triple {
+	int x;
+	int y;
+	int z;
+};
+
+struct adxl34x {
+	struct device *dev;
+	struct input_dev *input;
+	struct mutex mutex;	/* reentrant protection for struct */
+	struct adxl34x_platform_data pdata;
+	struct axis_triple swcal;
+	struct axis_triple hwcal;
+	struct axis_triple saved;
+	char phys[32];
+	unsigned orient2d_saved;
+	unsigned orient3d_saved;
+	bool disabled;	/* P: mutex */
+	bool opened;	/* P: mutex */
+	bool suspended;	/* P: mutex */
+	bool fifo_delay;
+	int irq;
+	unsigned model;
+	unsigned int_mask;
+
+	unsigned int_stat;
+	struct work_struct work_irq;
+	bool exit_work;
+
+	const struct adxl34x_bus_ops *bops;
+};
+
+static const struct adxl34x_platform_data adxl34x_default_init = {
+	.tap_threshold = 35,
+	.tap_duration = 3,
+	.tap_latency = 20,
+	.tap_window = 20,
+	.tap_axis_control = ADXL_TAP_X_EN | ADXL_TAP_Y_EN | ADXL_TAP_Z_EN,
+	.act_axis_control = 0xFF,
+	.activity_threshold = 6,
+	.inactivity_threshold = 4,
+	.inactivity_time = 3,
+	.free_fall_threshold = 8,
+	.free_fall_time = 0x20,
+	.data_rate = 8,
+	.data_range = ADXL_FULL_RES,
+
+	.ev_type = EV_ABS,
+	.ev_code_x = ABS_X,	/* EV_REL */
+	.ev_code_y = ABS_Y,	/* EV_REL */
+	.ev_code_z = ABS_Z,	/* EV_REL */
+
+	.ev_code_tap = {BTN_TOUCH, BTN_TOUCH, BTN_TOUCH}, /* EV_KEY {x,y,z} */
+	.power_mode = ADXL_AUTO_SLEEP | ADXL_LINK,
+	.fifo_mode = ADXL_FIFO_STREAM,
+	.watermark = 0,
+};
+
+static void adxl34x_get_triple(struct adxl34x *ac, struct axis_triple *axis)
+{
+	short buf[3];
+
+	ac->bops->read_block(ac->dev, DATAX0, DATAZ1 - DATAX0 + 1, buf);
+
+	mutex_lock(&ac->mutex);
+	ac->saved.x = (s16) le16_to_cpu(buf[0]);
+	axis->x = ac->saved.x;
+
+	ac->saved.y = (s16) le16_to_cpu(buf[1]);
+	axis->y = ac->saved.y;
+
+	ac->saved.z = (s16) le16_to_cpu(buf[2]);
+	axis->z = ac->saved.z;
+	mutex_unlock(&ac->mutex);
+}
+
+static void adxl34x_service_ev_fifo(struct adxl34x *ac)
+{
+	struct adxl34x_platform_data *pdata = &ac->pdata;
+	struct axis_triple axis;
+
+	adxl34x_get_triple(ac, &axis);
+
+	input_event(ac->input, pdata->ev_type, pdata->ev_code_x,
+		    axis.x - ac->swcal.x);
+	input_event(ac->input, pdata->ev_type, pdata->ev_code_y,
+		    axis.y - ac->swcal.y);
+	input_event(ac->input, pdata->ev_type, pdata->ev_code_z,
+		    axis.z - ac->swcal.z);
+}
+
+static void adxl34x_report_key_single(struct input_dev *input, int key)
+{
+	input_report_key(input, key, true);
+	input_sync(input);
+	input_report_key(input, key, false);
+}
+
+static void adxl34x_send_key_events(struct adxl34x *ac,
+		struct adxl34x_platform_data *pdata, int status, int press)
+{
+	int i;
+
+	for (i = ADXL_X_AXIS; i <= ADXL_Z_AXIS; i++) {
+		if (status & (1 << (ADXL_Z_AXIS - i)))
+			input_report_key(ac->input,
+					 pdata->ev_code_tap[i], press);
+	}
+}
+
+static void adxl34x_do_tap(struct adxl34x *ac,
+		struct adxl34x_platform_data *pdata, int status)
+{
+	adxl34x_send_key_events(ac, pdata, status, true);
+	input_sync(ac->input);
+	adxl34x_send_key_events(ac, pdata, status, false);
+}
+
+static irqreturn_t adxl34x_irq(int irq, void *handle)
+{
+	struct adxl34x *ac = handle;
+	struct adxl34x_platform_data *pdata = &ac->pdata;
+	int int_stat, tap_stat, samples, orient, orient_code;
+
+	/*
+	 * ACT_TAP_STATUS should be read before clearing the interrupt
+	 * Avoid reading ACT_TAP_STATUS in case TAP detection is disabled
+	 */
+
+	if (pdata->tap_axis_control & (TAP_X_EN | TAP_Y_EN | TAP_Z_EN))
+		tap_stat = AC_READ(ac, ACT_TAP_STATUS);
+	else
+		tap_stat = 0;
+
+	if (!ac->irq) {
+		int_stat = ac->int_stat;
+	} else {
+		int_stat = AC_READ(ac, INT_SOURCE);
+	}
+
+	if (int_stat & FREE_FALL)
+		adxl34x_report_key_single(ac->input, pdata->ev_code_ff);
+
+	if (int_stat & OVERRUN)
+		dev_dbg(ac->dev, "OVERRUN\n");
+
+	if (int_stat & (SINGLE_TAP | DOUBLE_TAP)) {
+		adxl34x_do_tap(ac, pdata, tap_stat);
+
+		if (int_stat & DOUBLE_TAP)
+			adxl34x_do_tap(ac, pdata, tap_stat);
+	}
+
+	if (pdata->ev_code_act_inactivity) {
+		if (int_stat & ACTIVITY)
+			input_report_key(ac->input,
+					 pdata->ev_code_act_inactivity, 1);
+		if (int_stat & INACTIVITY)
+			input_report_key(ac->input,
+					 pdata->ev_code_act_inactivity, 0);
+	}
+
+	/*
+	 * ORIENTATION SENSING ADXL346 only
+	 */
+	if (pdata->orientation_enable) {
+		orient = AC_READ(ac, ORIENT);
+		if ((pdata->orientation_enable & ADXL_EN_ORIENTATION_2D) &&
+		    (orient & ADXL346_2D_VALID)) {
+
+			orient_code = ADXL346_2D_ORIENT(orient);
+			/* Report orientation only when it changes */
+			if (ac->orient2d_saved != orient_code) {
+				ac->orient2d_saved = orient_code;
+				adxl34x_report_key_single(ac->input,
+					pdata->ev_codes_orient_2d[orient_code]);
+			}
+		}
+
+		if ((pdata->orientation_enable & ADXL_EN_ORIENTATION_3D) &&
+		    (orient & ADXL346_3D_VALID)) {
+
+			orient_code = ADXL346_3D_ORIENT(orient) - 1;
+			/* Report orientation only when it changes */
+			if (ac->orient3d_saved != orient_code) {
+				ac->orient3d_saved = orient_code;
+				adxl34x_report_key_single(ac->input,
+					pdata->ev_codes_orient_3d[orient_code]);
+			}
+		}
+	}
+
+	if (int_stat & (DATA_READY | WATERMARK)) {
+
+		if (pdata->fifo_mode)
+			samples = ENTRIES(AC_READ(ac, FIFO_STATUS)) + 1;
+		else
+			samples = 1;
+
+		for (; samples > 0; samples--) {
+			adxl34x_service_ev_fifo(ac);
+			/*
+			 * To ensure that the FIFO has
+			 * completely popped, there must be at least 5 us between
+			 * the end of reading the data registers, signified by the
+			 * transition to register 0x38 from 0x37 or the CS pin
+			 * going high, and the start of new reads of the FIFO or
+			 * reading the FIFO_STATUS register. For SPI operation at
+			 * 1.5 MHz or lower, the register addressing portion of the
+			 * transmission is sufficient delay to ensure the FIFO has
+			 * completely popped. It is necessary for SPI operation
+			 * greater than 1.5 MHz to de-assert the CS pin to ensure a
+			 * total of 5 us, which is at most 3.4 us at 5 MHz
+			 * operation.
+			 */
+			if (ac->fifo_delay && (samples > 1))
+				udelay(3);
+		}
+	}
+
+	input_sync(ac->input);
+
+	return IRQ_HANDLED;
+}
+
+/* in mHz */
+static unsigned bwrate_table[] = {
+	   100,     200,     390,     780,
+	  1560,    3130,    6250,   12500,
+	 25000,   50000,  100000,  200000,
+	400000,  800000, 1600000, 3200000,
+};
+
+/*
+ * work_cb_irq: scan adxl34x's interrupt.
+ */
+static void work_cb_irq(struct work_struct *work)
+{
+	struct adxl34x *ac = container_of(work, struct adxl34x, work_irq);
+
+	ac->int_stat = AC_READ(ac, INT_SOURCE);
+	if (ac->int_stat) {
+		adxl34x_irq(ac->irq, ac);
+	}
+	if (!ac->exit_work) {
+		unsigned msec;
+
+		msec = 1000000 / bwrate_table[ac->pdata.data_rate];
+		if (msec > 1)
+			--msec;
+		else if (!msec)
+			++msec;
+		msleep(msec);
+		schedule_work(&ac->work_irq);
+	}
+	return;
+}
+
+static void __adxl34x_disable(struct adxl34x *ac)
+{
+	/*
+	 * A '0' places the ADXL34x into standby mode
+	 * with minimum power consumption.
+	 */
+	AC_WRITE(ac, POWER_CTL, 0);
+}
+
+static void __adxl34x_enable(struct adxl34x *ac)
+{
+	AC_WRITE(ac, POWER_CTL, ac->pdata.power_mode | PCTL_MEASURE);
+}
+
+void adxl34x_suspend(struct adxl34x *ac)
+{
+	mutex_lock(&ac->mutex);
+
+	if (!ac->suspended && !ac->disabled && ac->opened)
+		__adxl34x_disable(ac);
+
+	ac->suspended = true;
+
+	mutex_unlock(&ac->mutex);
+}
+EXPORT_SYMBOL_GPL(adxl34x_suspend);
+
+void adxl34x_resume(struct adxl34x *ac)
+{
+	mutex_lock(&ac->mutex);
+
+	if (ac->suspended && !ac->disabled && ac->opened)
+		__adxl34x_enable(ac);
+
+	ac->suspended = false;
+
+	mutex_unlock(&ac->mutex);
+}
+EXPORT_SYMBOL_GPL(adxl34x_resume);
+
+static ssize_t adxl34x_disable_show(struct device *dev,
+				    struct device_attribute *attr, char *buf)
+{
+	struct adxl34x *ac = dev_get_drvdata(dev);
+
+	return sprintf(buf, "%u\n", ac->disabled);
+}
+
+static ssize_t adxl34x_disable_store(struct device *dev,
+				     struct device_attribute *attr,
+				     const char *buf, size_t count)
+{
+	struct adxl34x *ac = dev_get_drvdata(dev);
+	unsigned int val;
+	int error;
+
+	error = kstrtouint(buf, 10, &val);
+	if (error)
+		return error;
+
+	mutex_lock(&ac->mutex);
+
+	if (!ac->suspended && ac->opened) {
+		if (val) {
+			if (!ac->disabled)
+				__adxl34x_disable(ac);
+		} else {
+			if (ac->disabled)
+				__adxl34x_enable(ac);
+		}
+	}
+
+	ac->disabled = !!val;
+
+	mutex_unlock(&ac->mutex);
+
+	return count;
+}
+
+static DEVICE_ATTR(disable, 0664, adxl34x_disable_show, adxl34x_disable_store);
+
+static ssize_t adxl34x_calibrate_show(struct device *dev,
+				      struct device_attribute *attr, char *buf)
+{
+	struct adxl34x *ac = dev_get_drvdata(dev);
+	ssize_t count;
+
+	mutex_lock(&ac->mutex);
+	count = sprintf(buf, "%d,%d,%d\n",
+			ac->hwcal.x * 4 + ac->swcal.x,
+			ac->hwcal.y * 4 + ac->swcal.y,
+			ac->hwcal.z * 4 + ac->swcal.z);
+	mutex_unlock(&ac->mutex);
+
+	return count;
+}
+
+static ssize_t adxl34x_calibrate_store(struct device *dev,
+				       struct device_attribute *attr,
+				       const char *buf, size_t count)
+{
+	struct adxl34x *ac = dev_get_drvdata(dev);
+
+	/*
+	 * Hardware offset calibration has a resolution of 15.6 mg/LSB.
+	 * We use HW calibration and handle the remaining bits in SW. (4mg/LSB)
+	 */
+
+	mutex_lock(&ac->mutex);
+	ac->hwcal.x -= (ac->saved.x / 4);
+	ac->swcal.x = ac->saved.x % 4;
+
+	ac->hwcal.y -= (ac->saved.y / 4);
+	ac->swcal.y = ac->saved.y % 4;
+
+	ac->hwcal.z -= (ac->saved.z / 4);
+	ac->swcal.z = ac->saved.z % 4;
+
+	AC_WRITE(ac, OFSX, (s8) ac->hwcal.x);
+	AC_WRITE(ac, OFSY, (s8) ac->hwcal.y);
+	AC_WRITE(ac, OFSZ, (s8) ac->hwcal.z);
+	mutex_unlock(&ac->mutex);
+
+	return count;
+}
+
+static DEVICE_ATTR(calibrate, 0664,
+		   adxl34x_calibrate_show, adxl34x_calibrate_store);
+
+static ssize_t adxl34x_available_show(struct device *dev,
+				 struct device_attribute *attr, char *buf)
+{
+	struct adxl34x *ac = dev_get_drvdata(dev);
+	ssize_t count = 0;
+	int i;
+
+	mutex_lock(&ac->mutex);
+	for (i = 0; i < ARRAY_SIZE(bwrate_table); i++) {
+		count += sprintf(buf + count, "%u ", bwrate_table[i]);
+	}
+	sprintf(buf + count - 1, "\n");
+	mutex_unlock(&ac->mutex);
+
+	return count;
+}
+
+static DEVICE_ATTR(available_rates, S_IRUGO, adxl34x_available_show, NULL);
+
+
+static ssize_t adxl34x_rate_show(struct device *dev,
+				 struct device_attribute *attr, char *buf)
+{
+	struct adxl34x *ac = dev_get_drvdata(dev);
+
+	return sprintf(buf, "%u mHz\n", bwrate_table[ac->pdata.data_rate]);
+}
+
+static ssize_t adxl34x_rate_store(struct device *dev,
+				  struct device_attribute *attr,
+				  const char *buf, size_t count)
+{
+	struct adxl34x *ac = dev_get_drvdata(dev);
+	unsigned val, rate;
+	int i, error;
+
+	error = kstrtouint(buf, 10, &rate);
+	if (error)
+		return error;
+
+	for (i = 0; i < ARRAY_SIZE(bwrate_table) - 1; i++) {
+		if (bwrate_table[i] >= rate) {
+			break;
+		}
+	}
+	val = i;
+
+	mutex_lock(&ac->mutex);
+
+	ac->pdata.data_rate = RATE(val);
+	AC_WRITE(ac, BW_RATE,
+		 ac->pdata.data_rate |
+			(ac->pdata.low_power_mode ? LOW_POWER : 0));
+
+	mutex_unlock(&ac->mutex);
+
+	return count;
+}
+
+static DEVICE_ATTR(rate, 0664, adxl34x_rate_show, adxl34x_rate_store);
+
+static ssize_t adxl34x_autosleep_show(struct device *dev,
+				 struct device_attribute *attr, char *buf)
+{
+	struct adxl34x *ac = dev_get_drvdata(dev);
+
+	return sprintf(buf, "%u\n",
+		ac->pdata.power_mode & (PCTL_AUTO_SLEEP | PCTL_LINK) ? 1 : 0);
+}
+
+static ssize_t adxl34x_autosleep_store(struct device *dev,
+				  struct device_attribute *attr,
+				  const char *buf, size_t count)
+{
+	struct adxl34x *ac = dev_get_drvdata(dev);
+	unsigned int val;
+	int error;
+
+	error = kstrtouint(buf, 10, &val);
+	if (error)
+		return error;
+
+	mutex_lock(&ac->mutex);
+
+	if (val)
+		ac->pdata.power_mode |= (PCTL_AUTO_SLEEP | PCTL_LINK);
+	else
+		ac->pdata.power_mode &= ~(PCTL_AUTO_SLEEP | PCTL_LINK);
+
+	if (!ac->disabled && !ac->suspended && ac->opened)
+		AC_WRITE(ac, POWER_CTL, ac->pdata.power_mode | PCTL_MEASURE);
+
+	mutex_unlock(&ac->mutex);
+
+	return count;
+}
+
+static DEVICE_ATTR(autosleep, 0664,
+		   adxl34x_autosleep_show, adxl34x_autosleep_store);
+
+static ssize_t adxl34x_position_show(struct device *dev,
+				 struct device_attribute *attr, char *buf)
+{
+	struct adxl34x *ac = dev_get_drvdata(dev);
+	ssize_t count;
+
+	mutex_lock(&ac->mutex);
+	count = sprintf(buf, "(%d, %d, %d)\n",
+			ac->saved.x, ac->saved.y, ac->saved.z);
+	mutex_unlock(&ac->mutex);
+
+	return count;
+}
+
+static DEVICE_ATTR(position, S_IRUGO, adxl34x_position_show, NULL);
+
+#ifdef ADXL_DEBUG
+static ssize_t adxl34x_write_store(struct device *dev,
+				   struct device_attribute *attr,
+				   const char *buf, size_t count)
+{
+	struct adxl34x *ac = dev_get_drvdata(dev);
+	unsigned int val;
+	int error;
+
+	/*
+	 * This allows basic ADXL register write access for debug purposes.
+	 */
+	error = kstrtouint(buf, 16, &val);
+	if (error)
+		return error;
+
+	mutex_lock(&ac->mutex);
+	AC_WRITE(ac, val >> 8, val & 0xFF);
+	mutex_unlock(&ac->mutex);
+
+	return count;
+}
+
+static DEVICE_ATTR(write, 0664, NULL, adxl34x_write_store);
+#endif
+
+static struct attribute *adxl34x_attributes[] = {
+	&dev_attr_disable.attr,
+	&dev_attr_calibrate.attr,
+	&dev_attr_available_rates.attr,
+	&dev_attr_rate.attr,
+	&dev_attr_autosleep.attr,
+	&dev_attr_position.attr,
+#ifdef ADXL_DEBUG
+	&dev_attr_write.attr,
+#endif
+	NULL
+};
+
+static const struct attribute_group adxl34x_attr_group = {
+	.attrs = adxl34x_attributes,
+};
+
+static int adxl34x_input_open(struct input_dev *input)
+{
+	struct adxl34x *ac = input_get_drvdata(input);
+
+	mutex_lock(&ac->mutex);
+
+	if (!ac->suspended && !ac->disabled)
+		__adxl34x_enable(ac);
+
+	ac->opened = true;
+
+	mutex_unlock(&ac->mutex);
+
+	return 0;
+}
+
+static void adxl34x_input_close(struct input_dev *input)
+{
+	struct adxl34x *ac = input_get_drvdata(input);
+
+	mutex_lock(&ac->mutex);
+
+	if (!ac->suspended && !ac->disabled)
+		__adxl34x_disable(ac);
+
+	ac->opened = false;
+
+	mutex_unlock(&ac->mutex);
+}
+
+struct adxl34x *adxl34x_probe(struct device *dev, int irq,
+			      bool fifo_delay_default,
+			      const struct adxl34x_bus_ops *bops)
+{
+	struct adxl34x *ac;
+	struct input_dev *input_dev;
+	const struct adxl34x_platform_data *pdata;
+	int err, range, i;
+	unsigned char revid;
+
+	if (!irq) {
+		dev_info(dev, "no irq, launch a thread to scan irq handler\n");
+	}
+
+	ac = kzalloc(sizeof(*ac), GFP_KERNEL);
+	input_dev = input_allocate_device();
+	if (!ac || !input_dev) {
+		err = -ENOMEM;
+		goto err_free_mem;
+	}
+
+	ac->fifo_delay = fifo_delay_default;
+
+	pdata = dev_get_platdata(dev);
+	if (!pdata) {
+		dev_dbg(dev,
+			"No platform data: Using default initialization\n");
+		pdata = &adxl34x_default_init;
+	}
+
+	ac->pdata = *pdata;
+	pdata = &ac->pdata;
+
+	ac->input = input_dev;
+	ac->dev = dev;
+	ac->irq = irq;
+	ac->bops = bops;
+
+	mutex_init(&ac->mutex);
+
+	input_dev->name = "ADXL34x accelerometer";
+	revid = AC_READ(ac, DEVID);
+
+	switch (revid) {
+	case ID_ADXL345:
+		ac->model = 345;
+		break;
+	case ID_ADXL346:
+		ac->model = 346;
+		break;
+	default:
+		dev_err(dev, "Failed to probe %s\n", input_dev->name);
+		err = -ENODEV;
+		goto err_free_mem;
+	}
+
+	snprintf(ac->phys, sizeof(ac->phys), "%s/input0", dev_name(dev));
+
+	input_dev->phys = ac->phys;
+	input_dev->dev.parent = dev;
+	input_dev->id.product = ac->model;
+	input_dev->id.bustype = bops->bustype;
+	input_dev->open = adxl34x_input_open;
+	input_dev->close = adxl34x_input_close;
+
+	input_set_drvdata(input_dev, ac);
+
+	__set_bit(ac->pdata.ev_type, input_dev->evbit);
+
+	if (ac->pdata.ev_type == EV_REL) {
+		__set_bit(REL_X, input_dev->relbit);
+		__set_bit(REL_Y, input_dev->relbit);
+		__set_bit(REL_Z, input_dev->relbit);
+	} else {
+		/* EV_ABS */
+		__set_bit(ABS_X, input_dev->absbit);
+		__set_bit(ABS_Y, input_dev->absbit);
+		__set_bit(ABS_Z, input_dev->absbit);
+
+		if (pdata->data_range & FULL_RES)
+			range = ADXL_FULLRES_MAX_VAL;	/* Signed 13-bit */
+		else
+			range = ADXL_FIXEDRES_MAX_VAL;	/* Signed 10-bit */
+
+		input_set_abs_params(input_dev, ABS_X, -range, range, 3, 3);
+		input_set_abs_params(input_dev, ABS_Y, -range, range, 3, 3);
+		input_set_abs_params(input_dev, ABS_Z, -range, range, 3, 3);
+	}
+
+	__set_bit(EV_KEY, input_dev->evbit);
+	__set_bit(pdata->ev_code_tap[ADXL_X_AXIS], input_dev->keybit);
+	__set_bit(pdata->ev_code_tap[ADXL_Y_AXIS], input_dev->keybit);
+	__set_bit(pdata->ev_code_tap[ADXL_Z_AXIS], input_dev->keybit);
+
+	if (pdata->ev_code_ff) {
+		ac->int_mask = FREE_FALL;
+		__set_bit(pdata->ev_code_ff, input_dev->keybit);
+	}
+
+	if (pdata->ev_code_act_inactivity)
+		__set_bit(pdata->ev_code_act_inactivity, input_dev->keybit);
+
+	ac->int_mask |= ACTIVITY | INACTIVITY;
+
+	if (pdata->watermark) {
+		ac->int_mask |= WATERMARK;
+		if (!FIFO_MODE(pdata->fifo_mode))
+			ac->pdata.fifo_mode |= FIFO_STREAM;
+	} else {
+		ac->int_mask |= DATA_READY;
+	}
+
+	if (pdata->tap_axis_control & (TAP_X_EN | TAP_Y_EN | TAP_Z_EN))
+		ac->int_mask |= SINGLE_TAP | DOUBLE_TAP;
+
+	if (FIFO_MODE(pdata->fifo_mode) == FIFO_BYPASS)
+		ac->fifo_delay = false;
+
+	AC_WRITE(ac, POWER_CTL, 0);
+
+	if (ac->irq) {
+		err = request_threaded_irq(ac->irq, NULL, adxl34x_irq,
+				   IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
+				   dev_name(dev), ac);
+		if (err) {
+			dev_err(dev, "irq %d busy?\n", ac->irq);
+			goto err_free_mem;
+		}
+	}
+
+	err = sysfs_create_group(&dev->kobj, &adxl34x_attr_group);
+	if (err)
+		goto err_free_irq;
+
+	err = input_register_device(input_dev);
+	if (err)
+		goto err_remove_attr;
+
+	AC_WRITE(ac, OFSX, pdata->x_axis_offset);
+	ac->hwcal.x = pdata->x_axis_offset;
+	AC_WRITE(ac, OFSY, pdata->y_axis_offset);
+	ac->hwcal.y = pdata->y_axis_offset;
+	AC_WRITE(ac, OFSZ, pdata->z_axis_offset);
+	ac->hwcal.z = pdata->z_axis_offset;
+	AC_WRITE(ac, THRESH_TAP, pdata->tap_threshold);
+	AC_WRITE(ac, DUR, pdata->tap_duration);
+	AC_WRITE(ac, LATENT, pdata->tap_latency);
+	AC_WRITE(ac, WINDOW, pdata->tap_window);
+	AC_WRITE(ac, THRESH_ACT, pdata->activity_threshold);
+	AC_WRITE(ac, THRESH_INACT, pdata->inactivity_threshold);
+	AC_WRITE(ac, TIME_INACT, pdata->inactivity_time);
+	AC_WRITE(ac, THRESH_FF, pdata->free_fall_threshold);
+	AC_WRITE(ac, TIME_FF, pdata->free_fall_time);
+	AC_WRITE(ac, TAP_AXES, pdata->tap_axis_control);
+	AC_WRITE(ac, ACT_INACT_CTL, pdata->act_axis_control);
+	AC_WRITE(ac, BW_RATE, RATE(ac->pdata.data_rate) |
+		 (pdata->low_power_mode ? LOW_POWER : 0));
+	AC_WRITE(ac, DATA_FORMAT, pdata->data_range);
+	AC_WRITE(ac, FIFO_CTL, FIFO_MODE(pdata->fifo_mode) |
+			SAMPLES(pdata->watermark));
+
+	if (pdata->use_int2) {
+		/* Map all INTs to INT2 */
+		AC_WRITE(ac, INT_MAP, ac->int_mask | OVERRUN);
+	} else {
+		/* Map all INTs to INT1 */
+		AC_WRITE(ac, INT_MAP, 0);
+	}
+
+	if (ac->model == 346 && ac->pdata.orientation_enable) {
+		AC_WRITE(ac, ORIENT_CONF,
+			ORIENT_DEADZONE(ac->pdata.deadzone_angle) |
+			ORIENT_DIVISOR(ac->pdata.divisor_length));
+
+		ac->orient2d_saved = 1234;
+		ac->orient3d_saved = 1234;
+
+		if (pdata->orientation_enable & ADXL_EN_ORIENTATION_3D)
+			for (i = 0; i < ARRAY_SIZE(pdata->ev_codes_orient_3d); i++)
+				__set_bit(pdata->ev_codes_orient_3d[i],
+					  input_dev->keybit);
+
+		if (pdata->orientation_enable & ADXL_EN_ORIENTATION_2D)
+			for (i = 0; i < ARRAY_SIZE(pdata->ev_codes_orient_2d); i++)
+				__set_bit(pdata->ev_codes_orient_2d[i],
+					  input_dev->keybit);
+	} else {
+		ac->pdata.orientation_enable = 0;
+	}
+
+	AC_WRITE(ac, INT_ENABLE, ac->int_mask | OVERRUN);
+
+	ac->pdata.power_mode &= (PCTL_AUTO_SLEEP | PCTL_LINK);
+
+	if (!ac->irq) {
+		INIT_WORK(&ac->work_irq, work_cb_irq);
+		ac->exit_work = false;
+		schedule_work(&ac->work_irq);
+	}
+
+	return ac;
+
+ err_remove_attr:
+	sysfs_remove_group(&dev->kobj, &adxl34x_attr_group);
+ err_free_irq:
+	if (ac->irq) {
+		free_irq(ac->irq, ac);
+	}
+ err_free_mem:
+	input_free_device(input_dev);
+	kfree(ac);
+	return ERR_PTR(err);
+}
+EXPORT_SYMBOL_GPL(adxl34x_probe);
+
+int adxl34x_remove(struct adxl34x *ac)
+{
+	if (!ac->irq) {
+		ac->exit_work = true;
+		cancel_work_sync(&ac->work_irq);
+	}
+	sysfs_remove_group(&ac->dev->kobj, &adxl34x_attr_group);
+	if (ac->irq) {
+		free_irq(ac->irq, ac);
+	}
+	input_unregister_device(ac->input);
+	dev_dbg(ac->dev, "unregistered accelerometer\n");
+	kfree(ac);
+
+	return 0;
+}
+EXPORT_SYMBOL_GPL(adxl34x_remove);
+
+MODULE_AUTHOR("Michael Hennerich <hennerich@blackfin.uclinux.org>");
+MODULE_AUTHOR("Peter Yang <turmary@126.com>");
+MODULE_DESCRIPTION("ADXL345/346 Three-Axis Digital Accelerometer Driver");
+MODULE_LICENSE("GPL");
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/adxl34x/adxl34x.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/adxl34x/adxl34x.h
new file mode 100644
index 0000000000000000000000000000000000000000..bbbc80fda1643663e7a65817249842dff5d3f9a5
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/adxl34x/adxl34x.h
@@ -0,0 +1,30 @@
+/*
+ * ADXL345/346 Three-Axis Digital Accelerometers (I2C/SPI Interface)
+ *
+ * Enter bugs at http://blackfin.uclinux.org/
+ *
+ * Copyright (C) 2009 Michael Hennerich, Analog Devices Inc.
+ * Licensed under the GPL-2 or later.
+ */
+
+#ifndef _ADXL34X_H_
+#define _ADXL34X_H_
+
+struct device;
+struct adxl34x;
+
+struct adxl34x_bus_ops {
+	u16 bustype;
+	int (*read)(struct device *, unsigned char);
+	int (*read_block)(struct device *, unsigned char, int, void *);
+	int (*write)(struct device *, unsigned char, unsigned char);
+};
+
+void adxl34x_suspend(struct adxl34x *ac);
+void adxl34x_resume(struct adxl34x *ac);
+struct adxl34x *adxl34x_probe(struct device *dev, int irq,
+			      bool fifo_delay_default,
+			      const struct adxl34x_bus_ops *bops);
+int adxl34x_remove(struct adxl34x *ac);
+
+#endif
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/bme280/Makefile b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/bme280/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..3a92174df0e8b1674f57737e30d194be1904e7e7
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/bme280/Makefile
@@ -0,0 +1,40 @@
+#
+# Peter Yang <turmary@126.com>
+# Copyright (c) 2019 Seeed Studio
+#
+# MIT License
+#
+
+_tgt     := bme280
+
+_uname_r := $(shell uname -r)
+_BUILD   := /lib/modules/$(_uname_r)/build
+_PWD     := $(shell pwd)
+_DEPMOD  ?= depmod -a
+
+# If KERNELRELEASE is defined, we've been invoked from the
+# kernel build system and can use its language
+ifneq ($(KERNELRELEASE),)
+obj-m += ${_tgt}.o
+
+else
+_class  := drivers/iio/humidity
+
+DEST  := /lib/modules/$(_uname_r)/kernel
+
+all:
+	make -C ${_BUILD} M=$(_PWD) modules
+
+clean:
+	make -C ${_BUILD} M=$(_PWD) clean
+
+install:
+	cp ${_tgt}.ko ${DEST}/${_class}/
+	$(_DEPMOD)
+
+uninstall:
+	rm -f ${DEST}/${_class}/${_tgt}.ko
+	$(_DEPMOD)
+
+.PHONY: all clean install uninstall
+endif
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/bme280/README.md b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/bme280/README.md
new file mode 100644
index 0000000000000000000000000000000000000000..67a82a8dfc5ba377d4edd8ae036ec97c6b577572
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/bme280/README.md
@@ -0,0 +1,36 @@
+GROVE Temp&Humi&Barometer Sensor (BME280)
+=========================================
+
+  After driver and configuration prepared well,
+  the user could access ```/sys/bus/iio/devices/iio\:device<N>/XXX```,
+  to get the sensor data results.
+
+***
+
+Usage
+-----
+
+***example:***
+
+  ```bash
+  # check the device<N> name, make sure it's hcsr04
+  # where <N> is a number specific to your system.
+
+  $ cat /sys/bus/iio/devices/iio\:device2/name
+  bme280
+    
+  # get the temperature, in milli Celsius.
+  $ cat /sys/bus/iio/devices/iio\:device2/in_temp_input
+  25730
+
+  # get the humidity, in 0.001%
+  $ cat /sys/bus/iio/devices/iio\:device2/in_humidityrelative_input
+  48560
+
+  # get the air pressure, in kPa
+  $ cat /sys/bus/iio/devices/iio\:device2/in_pressure_input
+  101.390152343
+  ```
+
+  If you need customize the I2C-Port..., change it the device tree source.
+
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/bme280/bme280.c b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/bme280/bme280.c
new file mode 100644
index 0000000000000000000000000000000000000000..d771c6a3f55f7a6039723a0dd1c32f7861bded1e
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/bme280/bme280.c
@@ -0,0 +1,518 @@
+/*
+ *  bme280.c - Linux device driver for the bme280 humidity,
+ *  temperature and barometric sensor.
+ *
+ *  This driver uses the I2C bus subsystem and creates a char device when
+ *  probed to allow interaction with user space. For more details on use 
+ *  and implementation please refer to the README file.
+ *  
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *  
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *  
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ * */
+
+#include <linux/module.h> 
+#include <linux/i2c.h>
+#include "bme280.h"
+#include <linux/fs.h>
+#include <linux/uaccess.h>
+#include <linux/cdev.h>
+#include <linux/types.h>
+#include <asm/div64.h>
+
+#define DEVICE_NAME "bme280"
+
+/* 
+ * Structure that holds bme280 calibration data - this data is loaded into
+ * the device at production and it is different for each device, this structure
+ * is populated in the probe function. 
+ * 
+ * */
+struct bme280_calibration_t{
+	unsigned short dig_T1;
+      	signed short dig_T2;
+	signed short dig_T3;
+	unsigned short dig_P1;
+	signed short dig_P2;
+	signed short dig_P3;
+	signed short dig_P4;
+	signed short dig_P5;
+	signed short dig_P6;
+	signed short dig_P7;
+	signed short dig_P8;
+	signed short dig_P9;
+	unsigned char dig_H1;
+	signed short dig_H2;
+	unsigned char dig_H3;
+	signed short dig_H4;
+	signed short dig_H5;
+	signed char dig_H6;	
+};
+
+/* Structure that holds bme280 configuration */
+struct bme280_configuration_t{
+	unsigned char ctrl_hum;
+	unsigned char ctrl_meas;
+	unsigned char config;	
+};
+
+/* Structure that holds configuration and client data for the device */
+struct bme280_data_t{
+	struct i2c_client *client;
+	struct bme280_calibration_t *cal_data;
+	struct bme280_configuration_t *cfg_data;
+};
+
+/* Global variables */
+static struct bme280_calibration_t bme280_calibration;
+static struct bme280_configuration_t bme280_configuration =
+					{
+					.ctrl_hum = CTRL_HUM_OSRS_H(1),
+					.ctrl_meas = CTRL_MEAS_OSRS_T(1) | CTRL_MEAS_OSRS_P(1),
+					.config = 0
+					};
+struct i2c_client *bme280_client = NULL;
+static struct bme280_data_t bme280_data =
+					{
+					.client = NULL,
+					.cal_data = &bme280_calibration,
+					.cfg_data = &bme280_configuration
+					};
+static s32 fine_cal = 0;
+static u8 read_flag = 0;
+static struct cdev bme280_cdev;
+static dev_t device_numbers;
+
+/* 
+ * Performs temperature calibration
+ *
+ *
+ * */
+static void bme280_calibrate_temp(u32 temp, u32 *cal_temp){
+
+	s32 tmp1, tmp2;
+
+	tmp1 = ((((temp >> 3) - ((s32)bme280_calibration.dig_T1 << 1))) * 
+		((s32) bme280_calibration.dig_T2)) >> 11;
+	tmp2 = (((((temp >> 4) - ((s32)bme280_calibration.dig_T1)) * 
+		((temp >> 4) - ((s32)bme280_calibration.dig_T1))) >> 12) *
+		((s32)bme280_calibration.dig_T3)) >> 14;
+	fine_cal = tmp1 + tmp2;
+	
+	*cal_temp = (fine_cal * 5 + 128) >> 8; 
+}
+
+/*
+ * Performs humidity calibration
+ *
+ * */
+static void bme280_calibrate_hum(s32 hum, u32 *cal_hum){
+
+	s32 tmp1;
+
+	tmp1 = (fine_cal - ((s32)76800));
+	tmp1 = ((((hum << 14) - (((s32)bme280_calibration.dig_H4 << 20) -
+		(((s32)bme280_calibration.dig_H5) * tmp1)) +
+		((s32)16384)) >> 15) * (((((((tmp1 * ((s32)bme280_calibration.dig_H6)) >> 10) *
+		(((tmp1 * ((s32)bme280_calibration.dig_H3)) >> 11) + ((s32)32768))) >> 10) + 
+		((s32)2097152)) * ((s32)bme280_calibration.dig_H2) + 8192) >> 14));
+	tmp1 = (tmp1 - (((((tmp1 >> 15) * (tmp1 >> 15)) >> 7) *
+		(( s32)bme280_calibration.dig_H1)) >> 4));
+	tmp1 = (tmp1 < 0 ? 0 : tmp1);
+	tmp1 = (tmp1 > 419430400 ? 419430400 : tmp1);
+	*cal_hum = (u32)(tmp1 >> 12);
+}
+
+/*
+ * Performs pressure calibration
+ *
+ * */
+static void bme280_calibrate_press(u32 press, u32 *cal_press){
+	
+	s64 tmp1, tmp2, tmp3, tmp4;
+
+	tmp1 = fine_cal - 128000;
+	tmp2 = tmp1 * tmp1 * (s64)bme280_calibration.dig_P6;
+	tmp2 = tmp2 + ((tmp1 * (s64)bme280_calibration.dig_P5) << 17);
+	tmp2 = tmp2 + (((s64)bme280_calibration.dig_P4) << 35);
+	tmp1 = ((tmp1 * tmp1 * (s64)bme280_calibration.dig_P3) >> 8) + 
+		((tmp1 * (s64)bme280_calibration.dig_P2) << 12);
+	tmp1 = (((((s64)1) << 47) + tmp1)) * ((s64)bme280_calibration.dig_P1) >> 33;
+	if(tmp1 == 0){
+		*cal_press = 0;
+		return;	/* Avoid exception caused by division by zero */
+	}
+	tmp3 = 1048576 - press;
+	tmp3 = (((tmp3 << 31) - tmp2) * 3125);
+	tmp4 = do_div(tmp3, tmp1);
+	tmp1 = (((s64)bme280_calibration.dig_P9) * (tmp3 >> 13) * (tmp3 >> 13)) >> 25;
+	tmp2 = (((s64)bme280_calibration.dig_P8) * tmp3) >> 19;
+	tmp3 = ((tmp3 + tmp1 + tmp2) >> 8) + (((s64)bme280_calibration.dig_P7) << 4);
+	*cal_press = (u32)tmp3;
+}
+
+/* Helper functions definitions */
+/*
+ * This helper function is used to obtain the calibration
+ * parameters and populate the calibration structure
+ *
+ * parameter | Register address |   bit
+ * ----------|------------------|----------------
+ * dig_T1    |  0x88 and 0x89   | from 0 : 7 to 8: 15
+ * dig_T2    |  0x8A and 0x8B   | from 0 : 7 to 8: 15
+ * dig_T3    |  0x8C and 0x8D   | from 0 : 7 to 8: 15
+ * dig_P1    |  0x8E and 0x8F   | from 0 : 7 to 8: 15
+ * dig_P2    |  0x90 and 0x91   | from 0 : 7 to 8: 15
+ * dig_P3    |  0x92 and 0x93   | from 0 : 7 to 8: 15
+ * dig_P4    |  0x94 and 0x95   | from 0 : 7 to 8: 15
+ * dig_P5    |  0x96 and 0x97   | from 0 : 7 to 8: 15
+ * dig_P6    |  0x98 and 0x99   | from 0 : 7 to 8: 15
+ * dig_P7    |  0x9A and 0x9B   | from 0 : 7 to 8: 15
+ * dig_P8    |  0x9C and 0x9D   | from 0 : 7 to 8: 15
+ * dig_P9    |  0x9E and 0x9F   | from 0 : 7 to 8: 15
+ * dig_H1    |         0xA1     | from 0 to 7
+ * dig_H2    |  0xE1 and 0xE2   | from 0 : 7 to 8: 15
+ * dig_H3    |         0xE3     | from 0 to 7
+ * dig_H4    |0xE4 and 0xE5[3:0]| from 4 : 11 to 0: 3
+ * dig_H5    |0xE5[7:4] and 0xE6| from 0 : 3 to 4: 11
+ * dig_H6    |         0xE7     | from 0 to 7
+ * 
+ * */
+static int bme280_get_calibration(struct bme280_calibration_t *calibration){
+	u8 calib_data_0_25[CALIBRATION_REG_SIZE_0];
+	u8 calib_data_26_41[CALIBRATION_REG_SIZE_26];
+	s32 tmp;
+	u8 i = 0;
+
+	/* 
+	 * Read calibration data, the data is arranged in two chunks
+	 * from 0x88 (calib0) to 0xA1 (calib25) and 
+	 * from 0xE1 (calib26) to 0xF0 (calib41)
+	 * Use read byte instead of emulated block data read because 4.1 
+	 * does not support emulated block read
+	 * */
+	while(i < CALIBRATION_REG_SIZE_0){
+		tmp = i2c_smbus_read_byte_data(bme280_data.client, R_BME280_CALIB00 + i);
+		if(tmp < 0){
+			goto out;
+		}
+		calib_data_0_25[i] = (u8) (tmp & 0xFF);
+		i++;
+	}
+	i = 0;
+	while(i < CALIBRATION_REG_SIZE_26){
+		tmp = i2c_smbus_read_byte_data(bme280_data.client, R_BME280_CALIB26 + i);
+		if(tmp < 0){
+			goto out;
+		}
+		calib_data_26_41[i] = (u8) (tmp & 0xFF);
+		i++;
+	}
+
+	/* Fill calibration structure from obtained parameters */
+	bme280_data.cal_data->dig_T1 = (unsigned short)((calib_data_0_25[1] << 8) | calib_data_0_25[0]);
+	bme280_data.cal_data->dig_T2 = (short) ((calib_data_0_25[3] << 8) | calib_data_0_25[2]);	
+	bme280_data.cal_data->dig_T3 = (short) ((calib_data_0_25[5] << 8) | calib_data_0_25[4]);
+	bme280_data.cal_data->dig_P1 = (unsigned short) ((calib_data_0_25[7] << 8) | calib_data_0_25[6]);
+	bme280_data.cal_data->dig_P2 = (short) ((calib_data_0_25[9] << 8) | calib_data_0_25[8]);
+	bme280_data.cal_data->dig_P3 = (short) ((calib_data_0_25[11] << 8) | calib_data_0_25[10]);
+	bme280_data.cal_data->dig_P4 = (short) ((calib_data_0_25[13] << 8) | calib_data_0_25[12]);
+	bme280_data.cal_data->dig_P5 = (short) ((calib_data_0_25[15] << 8) | calib_data_0_25[14]);
+	bme280_data.cal_data->dig_P6 = (short) ((calib_data_0_25[17] << 8) | calib_data_0_25[16]);
+	bme280_data.cal_data->dig_P7 = (short) ((calib_data_0_25[19] << 8) | calib_data_0_25[18]);
+	bme280_data.cal_data->dig_P8 = (short) ((calib_data_0_25[21] << 8) | calib_data_0_25[20]);
+	bme280_data.cal_data->dig_P9 = (short) ((calib_data_0_25[23] << 8) | calib_data_0_25[22]);
+	bme280_data.cal_data->dig_H1 = calib_data_0_25[24];
+	bme280_data.cal_data->dig_H2 = (short) ((calib_data_26_41[1] << 8) | calib_data_26_41[0]);
+	bme280_data.cal_data->dig_H3 = calib_data_26_41[2];
+	bme280_data.cal_data->dig_H4 = (short) ((calib_data_26_41[4] & 0x0F ) | 
+			(calib_data_26_41[3] << 4));
+	bme280_data.cal_data->dig_H5 = (short) ((calib_data_26_41[5] << 4) | 
+			( (calib_data_26_41[4] & 0xF0) >> 4 ) );
+	bme280_data.cal_data->dig_H6 = (s8) calib_data_26_41[6];
+	
+	return 0;
+out:
+	return tmp;
+}
+
+static int bme280_set_configuration(struct bme280_configuration_t *configuration){
+	int tmp;
+
+	/* Configure CTRL_HUM  */
+	tmp = i2c_smbus_write_byte_data(bme280_data.client, R_BME280_CTRL_HUM, 
+			bme280_data.cfg_data->ctrl_hum);
+	if(tmp < 0){
+		printk(KERN_INFO "%s: Unable to write CTRL_HUM.\n", DEVICE_NAME);
+		goto out;
+	}
+		
+	/* 
+	 * Configure CTRL_MEAS  
+	 * changes to CTRL_HUM become effective only after writing to CTRL_MEAS 
+	 * */
+	tmp = i2c_smbus_write_byte_data(bme280_data.client, R_BME280_CTRL_MEAS,
+			bme280_data.cfg_data->ctrl_meas);
+	if(tmp < 0){
+		printk(KERN_INFO "%s: Unable to write CTRL_MEAS.\n", DEVICE_NAME);
+		goto out;
+	}
+
+	/* Set CONFIG register */
+	tmp = i2c_smbus_write_byte_data(bme280_data.client, R_BME280_CONFIG,
+			bme280_data.cfg_data->config);
+	if(tmp < 0){
+		printk(KERN_INFO "%s: Unable to write CONFIG.\n", DEVICE_NAME);
+		goto out;
+	}
+
+out:
+	return tmp;
+}
+
+
+/* Char device declarations */
+static int bme280_open(struct inode *inode, struct file *filp){
+	read_flag = 0;
+	return 0;
+}
+
+static int bme280_release(struct inode *inode, struct file *filp){
+	read_flag = 0;
+	return 0;
+}
+
+static ssize_t bme280_read(struct file *filp, char *buf, size_t count, loff_t *ppos){
+	int tmp, working_mode;
+	u32 i = 0;
+	u8 press_st[MAX_STRING_SIZE];
+	u8 temp_st[MAX_STRING_SIZE];
+	u8 hum_st[MAX_STRING_SIZE];
+	u8 final_st[MAX_STRING_SIZE * 3];
+	u32 press, temp;
+	u16 hum;
+	s32 cal_temp, cal_hum, cal_press;
+	u8 data_readout[DATA_READOUT_SIZE];
+	
+	/* Check if data was read already */
+	if(read_flag == 1){
+		read_flag = 0;
+		return 0;
+	}
+
+	/* Check working mode */
+	working_mode = i2c_smbus_read_byte_data(bme280_data.client, R_BME280_CTRL_MEAS);
+	if(working_mode < 0){
+		tmp = working_mode;
+		goto out;
+	}
+	
+	/* If in sleep mode we need to do a force read */
+	if((working_mode & 0b11) == 0){
+		tmp = i2c_smbus_write_byte_data(bme280_data.client, R_BME280_CTRL_MEAS, 
+				(working_mode | 0b10));
+		if(tmp < 0){
+			goto out;
+		}
+	}
+
+	/* Check status flag */
+	do{
+		tmp = i2c_smbus_read_byte_data(bme280_data.client, R_BME280_STATUS);
+		if(tmp < 0){
+			goto out;
+		}
+	}while(tmp & STATUS_MEASURING_RUNNING);
+
+	/* 
+	 * Perform raw read, it is adviced to perform a burst read
+	 * from 0xF7 (PRESS_MSB) to 0xFE (HUM_LSB)
+	 * Use read byte instead of emulated block data read because 4.1 
+	 * does not support emulated block read
+	 * */
+	while(i < DATA_READOUT_SIZE){
+		tmp = i2c_smbus_read_byte_data(bme280_data.client, R_BME280_PRESS_MSB + i);
+		if(tmp < 0){
+			goto out;
+		}
+		data_readout[i] =(u8) (tmp & 0xFF);
+		i++;
+	}
+
+	/* Process raw data */
+	press = (data_readout[0] << 12) | (data_readout[1] << 4) | (data_readout[2] >> 4);
+	temp = (data_readout[3] << 12) | (data_readout[4] << 4) | (data_readout[5] >> 4);
+	hum = (data_readout[6] << 8) |  data_readout[7];
+
+	/* Compensate obtained results
+	 *
+	 * Temperature must be compensated first, a value that is required
+	 * by the other parameters is calculated by the temperature 
+	 * calbration routine.
+	 * */
+	bme280_calibrate_temp(temp, &cal_temp);
+	bme280_calibrate_hum(hum, &cal_hum);
+	bme280_calibrate_press(press, &cal_press);
+
+	/* Form string */
+	/* Turn numeric values to strings */
+	tmp = snprintf(press_st, MAX_STRING_SIZE, "%d", cal_press);
+	if(tmp >= MAX_STRING_SIZE){
+		printk(KERN_INFO "%s: Pressure string truncated\n", DEVICE_NAME);
+	}
+	
+	tmp = snprintf(temp_st, MAX_STRING_SIZE, "%d", cal_temp);
+	if(tmp >= MAX_STRING_SIZE){
+		printk(KERN_INFO "%s: Temperature string truncated\n", DEVICE_NAME);
+	}
+	
+	tmp = snprintf(hum_st, MAX_STRING_SIZE, "%d", cal_hum);
+	if(tmp >= MAX_STRING_SIZE){
+		printk(KERN_INFO "%s: Humidity string truncated\n", DEVICE_NAME);
+	}
+
+	/* Create string */
+	strcpy(final_st, "t");
+	strcat(final_st, temp_st);
+	strcat(final_st, "p");
+	strcat(final_st, press_st);
+	strcat(final_st, "h");
+	strcat(final_st, hum_st);
+	strcat(final_st, "\n");
+
+	/* Copy from kernel space to user space */
+	tmp = copy_to_user(buf, final_st, strlen(final_st));
+	read_flag = 1;
+	return strlen(final_st);
+out:
+	return tmp;
+}
+
+static struct file_operations fops = {
+		.owner = THIS_MODULE,
+		.read = bme280_read,
+		.open = bme280_open,
+		.release = bme280_release,
+};
+
+/*
+ * When the device is probed this function performs the following actions:
+ *  -Reads device ID - NOTE: I2C Address should be configured in the device tree (or the method
+ *                     used to register the device)
+ *  -Reads calibration parameters
+ *  -Configures device
+ *  -Registers char device for user space communication
+ * */
+static int bme280_probe(struct i2c_client *client, const struct i2c_device_id *id){
+	
+	int tmp, client_id;
+	struct i2c_adapter *adapter;
+	
+	/* Check if adapter supports the functionality we need */
+	adapter = client->adapter;
+	tmp = i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE | I2C_FUNC_SMBUS_BYTE_DATA);
+	if(!tmp)
+		goto err_out;
+
+	/* Get chip_id */
+	client_id = i2c_smbus_read_byte_data(client, R_BME280_CHIP_ID);
+	if(client_id != BME280_CHIP_ID){
+		printk(KERN_INFO "%s: Client ID (%x) does not match chip ID (%x).\n", 
+			DEVICE_NAME, client_id, BME280_CHIP_ID);
+		goto err_out;
+	}
+	bme280_data.client = client;
+
+	/* Get calibration parameters */
+	bme280_get_calibration(bme280_data.cal_data);
+
+	/* Set configuration */
+	tmp = bme280_set_configuration(bme280_data.cfg_data);
+	if(tmp < 0){
+		printk(KERN_INFO "%s: Unable to configure device.\n", DEVICE_NAME);
+		goto err_out;
+	} 
+
+	/* Register char device */
+	tmp = alloc_chrdev_region(&device_numbers, 0, 1, DEVICE_NAME);
+	if(tmp < 0){
+		printk(KERN_INFO "%s: Unable to register char device.\n", DEVICE_NAME);
+		goto err_out;
+	}
+
+	/* Creating character device (cdev) "object" */
+	cdev_init(&bme280_cdev, &fops);
+	bme280_cdev.owner = THIS_MODULE;
+	bme280_cdev.ops = &fops;
+	tmp = cdev_add(&bme280_cdev, device_numbers, 1);
+	if(tmp){
+		printk(KERN_ALERT "%s: Unable to add cdev, with errno %d.\n", DEVICE_NAME, tmp);
+		goto err_out2;
+	}
+	
+	printk(KERN_INFO "%s: Probe executed successfully.\n", DEVICE_NAME);
+err_out:
+	return tmp;
+err_out2:
+	unregister_chrdev_region(device_numbers, 1);
+	return tmp;
+}
+
+static int bme280_remove(struct i2c_client *client){
+	/* Unregister char device */
+	unregister_chrdev_region(device_numbers, 1);
+	return 0;
+}
+
+static struct i2c_device_id bme280_idtable[] = {
+	{DEVICE_NAME, 0},
+	{ }
+};
+MODULE_DEVICE_TABLE(i2c, bme280_idtable);
+
+static struct i2c_driver bme280_driver = {
+	.driver = {
+		    .name = DEVICE_NAME,
+		    .owner = THIS_MODULE,
+		  },
+	.probe = bme280_probe,
+	.remove = bme280_remove,
+	.id_table = bme280_idtable
+};
+
+/* Module init routine */
+static int __init bme280_init(void){
+	/* Register driver within I2C subsystem */
+	int tmp;
+	tmp = i2c_add_driver(&bme280_driver);
+	if(tmp < 0){
+		printk(KERN_INFO "%s: I2C subsystem registration failed.\n", DEVICE_NAME);
+	}
+	printk(KERN_INFO "%s: Device successfully registered to I2C subsystem.\n", DEVICE_NAME);
+	return tmp;
+}
+
+/* Module exit routine */
+static void __exit bme280_exit(void){
+
+	/* Unregister driver from I2C subsystem */
+	i2c_del_driver(&bme280_driver);
+}
+
+module_init(bme280_init);
+module_exit(bme280_exit);
+
+MODULE_AUTHOR("Manuel Rodriguez <manuel2982@gmail.com>");
+MODULE_DESCRIPTION("Driver for BME280 sensor");
+MODULE_LICENSE("GPL");
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/bme280/bme280.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/bme280/bme280.h
new file mode 100644
index 0000000000000000000000000000000000000000..84e2592396ed8acaef0e5d861f49547fcd81cdfe
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/bme280/bme280.h
@@ -0,0 +1,65 @@
+/*
+ *  bme280.h - Device definitions for the bme280 humidity,
+ *  temperature and barometric sensor.
+ *  
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *  
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *  
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ * */
+
+
+/* BME280 registers - for details please refer to the device DS */
+#define R_BME280_CALIB00		0x88
+#define R_BME280_CALIB25		0xA1
+#define R_BME280_CHIP_ID		0xD0
+#define R_BME280_RESET			0xE0
+#define R_BME280_CALIB26			0xE1
+#define R_BME280_CALIB41			0xF0
+#define R_BME280_CTRL_HUM			0xF2
+#define R_BME280_STATUS				0xF3
+#define R_BME280_CTRL_MEAS		0xF4
+#define R_BME280_CONFIG			0xF5
+#define R_BME280_PRESS_MSB		0xF7
+#define R_BME280_PRESS_LSB		0xF8
+#define R_BME280_PRESS_XLSB			0xF9
+#define R_BME280_TEMP_MSB			0xFA
+#define R_BME280_TEMP_LSB			0xFB
+#define R_BME280_TEMP_XLSB			0xFC
+#define R_BME280_HUM_MSB		0xFD
+#define R_BME280_HUM_LSB		0xFE
+
+/* BME280 definitions */
+#define BME280_CHIP_ID			0x60
+#define BME280_I2C_ADDR			0x77
+
+/* Configuration fields */
+#define CTRL_HUM_OSRS_H(x)		(x)			
+#define CTRL_MEAS_MODE(x)		(x)
+#define CTRL_MEAS_OSRS_P(x)		(x << 2)
+#define CTRL_MEAS_OSRS_T(x)		(x << 5)
+#define	CONFIG_T_SB(x)			(x << 5)
+#define CONFIG_FILTER(x)		(x << 2)
+#define CONFIG_SPI3W_EN(x)		(x)
+#define STATUS_MEASURING_RUNNING	(1 << 3)
+
+/* Data readout size */
+#define DATA_READOUT_SIZE	8
+#if(DATA_READOUT_SIZE > I2C_SMBUS_BLOCK_MAX)
+#error "Data readout is greater than I2C_SMBUS_BLOCK_MAX."
+#endif
+#define MAX_STRING_SIZE		10
+#define CALIBRATION_REG_SIZE_0	26
+#define CALIBRATION_REG_SIZE_26 16
+/* IOCTL Commands definitions */
+
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/dht11/Makefile b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/dht11/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..afa37caa2f3a158936bdacc9419e8044c5192cb9
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/dht11/Makefile
@@ -0,0 +1,33 @@
+
+_uname_r := $(shell uname -r)
+_BUILD   := /lib/modules/$(_uname_r)/build
+_PWD     := $(shell pwd)
+_DEPMOD  ?= depmod -a
+
+# If KERNELRELEASE is defined, we've been invoked from the
+# kernel build system and can use its language
+ifneq ($(KERNELRELEASE),)
+
+obj-m += dht11.o
+
+else
+_class  := drivers/input
+
+DEST  := /lib/modules/$(_uname_r)/kernel
+
+all:
+	make -C ${_BUILD} M=$(_PWD) modules
+
+clean:
+	make -C ${_BUILD} M=$(_PWD) clean
+
+install:
+	cp dht11.ko ${DEST}/${_class}/
+	$(_DEPMOD)
+
+uninstall:
+	rm -f ${DEST}/${_class}/dht11.ko 
+	$(_DEPMOD)
+
+.PHONY: all clean install uninstall
+endif
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/dht11/dht11.c b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/dht11/dht11.c
new file mode 100644
index 0000000000000000000000000000000000000000..792f5ff34223e49dc198cabb1b6a423619c3919b
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/dht11/dht11.c
@@ -0,0 +1,376 @@
+/*
+ * DHT11/DHT22 bit banging GPIO driver
+ *
+ * Copyright (c) Harald Geyer <harald@ccbib.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#include <linux/err.h>
+#include <linux/interrupt.h>
+#include <linux/device.h>
+#include <linux/kernel.h>
+#include <linux/printk.h>
+#include <linux/slab.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/sysfs.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/wait.h>
+#include <linux/bitops.h>
+#include <linux/completion.h>
+#include <linux/mutex.h>
+#include <linux/delay.h>
+#include <linux/gpio.h>
+#include <linux/of_gpio.h>
+#include <linux/timekeeping.h>
+
+#include <linux/iio/iio.h>
+
+#define DRIVER_NAME	"dht11"
+
+#define DHT11_DATA_VALID_TIME	2000000000	/* 2s in ns */
+
+#define DHT11_EDGES_PREAMBLE 2
+#define DHT11_BITS_PER_READ 40
+/*
+ * Note that when reading the sensor actually 84 edges are detected, but
+ * since the last edge is not significant, we only store 83:
+ */
+#define DHT11_EDGES_PER_READ (2 * DHT11_BITS_PER_READ + \
+			      DHT11_EDGES_PREAMBLE + 1)
+
+/*
+ * Data transmission timing:
+ * Data bits are encoded as pulse length (high time) on the data line.
+ * 0-bit: 22-30uS -- typically 26uS (AM2302)
+ * 1-bit: 68-75uS -- typically 70uS (AM2302)
+ * The acutal timings also depend on the properties of the cable, with
+ * longer cables typically making pulses shorter.
+ *
+ * Our decoding depends on the time resolution of the system:
+ * timeres > 34uS ... don't know what a 1-tick pulse is
+ * 34uS > timeres > 30uS ... no problem (30kHz and 32kHz clocks)
+ * 30uS > timeres > 23uS ... don't know what a 2-tick pulse is
+ * timeres < 23uS ... no problem
+ *
+ * Luckily clocks in the 33-44kHz range are quite uncommon, so we can
+ * support most systems if the threshold for decoding a pulse as 1-bit
+ * is chosen carefully. If somebody really wants to support clocks around
+ * 40kHz, where this driver is most unreliable, there are two options.
+ * a) select an implementation using busy loop polling on those systems
+ * b) use the checksum to do some probabilistic decoding
+ */
+#define DHT11_START_TRANSMISSION_MIN	18000	/* us */
+#define DHT11_START_TRANSMISSION_MAX	20000	/* us */
+#define DHT11_MIN_TIMERES	34000	/* ns */
+#define DHT11_THRESHOLD		49000	/* ns */
+#define DHT11_AMBIG_LOW		23000	/* ns */
+#define DHT11_AMBIG_HIGH	30000	/* ns */
+
+struct dht11 {
+	struct device *dev;
+
+	int gpio;
+	int irq;
+
+	struct completion completion;
+	/* The iio sysfs interface doesn't prevent concurrent reads: */
+	struct mutex lock;
+
+	s64 timestamp;
+	int temperature;
+	int humidity;
+
+	/* num_edges: -1 means "no transmission in progress" */
+	int num_edges;
+	struct {
+		s64 ts;
+		int value;
+	} edges[DHT11_EDGES_PER_READ];
+};
+
+#ifdef CONFIG_DYNAMIC_DEBUG
+/*
+ * dht11_edges_print: show the data as actually received by the
+ *                    driver.
+ */
+static void dht11_edges_print(struct dht11 *dht11)
+{
+	int i;
+
+	dev_dbg(dht11->dev, "%d edges detected:\n", dht11->num_edges);
+	for (i = 1; i < dht11->num_edges; ++i) {
+		dev_dbg(dht11->dev, "%d: %lld ns %s\n", i,
+			dht11->edges[i].ts - dht11->edges[i - 1].ts,
+			dht11->edges[i - 1].value ? "high" : "low");
+	}
+}
+#endif /* CONFIG_DYNAMIC_DEBUG */
+
+static unsigned char dht11_decode_byte(char *bits)
+{
+	unsigned char ret = 0;
+	int i;
+
+	for (i = 0; i < 8; ++i) {
+		ret <<= 1;
+		if (bits[i])
+			++ret;
+	}
+
+	return ret;
+}
+
+static int dht11_decode(struct dht11 *dht11, int offset)
+{
+	int i, t;
+	char bits[DHT11_BITS_PER_READ];
+	unsigned char temp_int, temp_dec, hum_int, hum_dec, checksum;
+
+	for (i = 0; i < DHT11_BITS_PER_READ; ++i) {
+		t = dht11->edges[offset + 2 * i + 2].ts -
+		    dht11->edges[offset + 2 * i + 1].ts;
+		if (!dht11->edges[offset + 2 * i + 1].value) {
+			dev_dbg(dht11->dev,
+				"lost synchronisation at edge %d\n",
+				offset + 2 * i + 1);
+			return -EIO;
+		}
+		bits[i] = t > DHT11_THRESHOLD;
+	}
+
+	hum_int = dht11_decode_byte(bits);
+	hum_dec = dht11_decode_byte(&bits[8]);
+	temp_int = dht11_decode_byte(&bits[16]);
+	temp_dec = dht11_decode_byte(&bits[24]);
+	checksum = dht11_decode_byte(&bits[32]);
+
+	if (((hum_int + hum_dec + temp_int + temp_dec) & 0xff) != checksum) {
+		printk("invalid checksum\n");
+		return -EIO;
+	}
+
+	dht11->timestamp = ktime_get_boot_ns();
+#if 1
+	if (hum_int < 4) {	/* DHT22: 100000 = (3*256+232)*100 */
+		dht11->temperature = (((temp_int & 0x7f) << 8) + temp_dec) *
+		    ((temp_int & 0x80) ? -100 : 100);
+		dht11->humidity = ((hum_int << 8) + hum_dec) * 100;
+	} else if (temp_dec == 0 && hum_dec == 0) {	/* DHT11 */
+		dht11->temperature = temp_int * 1000;
+		dht11->humidity = hum_int * 1000;
+	} else {
+		dev_err(dht11->dev,
+			"Don't know how to decode data: %d %d %d %d\n",
+			hum_int, hum_dec, temp_int, temp_dec);
+		return -EIO;
+	}
+#endif
+
+//	dht11->temperature = temp_int;	//(((temp_int & 0x7f) << 8) + temp_dec) *((temp_int & 0x80) ? -100 : 100);
+//	dht11->humidity = hum_int;	//((hum_int << 8) + hum_dec) * 100;
+	return 0;
+}
+
+/*
+ * IRQ handler called on GPIO edges
+ */
+static irqreturn_t dht11_handle_irq(int irq, void *data)
+{
+	struct iio_dev *iio = data;
+	struct dht11 *dht11 = iio_priv(iio);
+	/* TODO: Consider making the handler safe for IRQ sharing */
+	if (dht11->num_edges < DHT11_EDGES_PER_READ && dht11->num_edges >= 0) {
+		dht11->edges[dht11->num_edges].ts = ktime_get_boot_ns();
+		dht11->edges[dht11->num_edges++].value =
+		    gpio_get_value(dht11->gpio);
+
+		if (dht11->num_edges >= DHT11_EDGES_PER_READ)
+			complete(&dht11->completion);
+	}
+
+	return IRQ_HANDLED;
+}
+
+static int dht11_read_raw(struct iio_dev *iio_dev,
+			  const struct iio_chan_spec *chan,
+			  int *val, int *val2, long m)
+{
+	struct dht11 *dht11 = iio_priv(iio_dev);
+	int ret, timeres, offset;
+
+	mutex_lock(&dht11->lock);
+
+	if (dht11->timestamp + DHT11_DATA_VALID_TIME < ktime_get_boot_ns()) {
+		timeres = ktime_get_resolution_ns();
+		dev_dbg(dht11->dev, "current timeresolution: %dns\n", timeres);
+
+		if (timeres > DHT11_MIN_TIMERES) {
+			dev_err(dht11->dev, "timeresolution %dns too low\n",
+				timeres);
+			/* In theory a better clock could become available
+			 * at some point ... and there is no error code
+			 * that really fits better.
+			 */
+			ret = -EAGAIN;
+			goto err;
+		}
+		if (timeres > DHT11_AMBIG_LOW && timeres < DHT11_AMBIG_HIGH)
+			dev_warn(dht11->dev,
+				 "timeresolution: %dns - decoding ambiguous\n",
+				 timeres);
+
+		reinit_completion(&dht11->completion);
+
+		dht11->num_edges = 0;
+		ret = gpio_direction_output(dht11->gpio, 0);
+		if (ret)
+			goto err;
+		usleep_range(DHT11_START_TRANSMISSION_MIN,
+			     DHT11_START_TRANSMISSION_MAX);
+		ret = gpio_direction_input(dht11->gpio);
+//              if (ret)
+//                      goto err;
+
+		ret = request_irq(dht11->irq, dht11_handle_irq,
+				  IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
+				  iio_dev->name, iio_dev);
+		if (ret)
+			goto err;
+
+		ret = wait_for_completion_killable_timeout(&dht11->completion,
+							   HZ);
+
+		free_irq(dht11->irq, iio_dev);
+
+#ifdef CONFIG_DYNAMIC_DEBUG
+		dht11_edges_print(dht11);
+#endif
+
+		if (ret == 0 && dht11->num_edges < DHT11_EDGES_PER_READ - 1) {
+			dev_err(dht11->dev, "Only %d signal edges detected\n",
+				dht11->num_edges);
+			ret = -ETIMEDOUT;
+		}
+		if (ret < 0)
+			goto err;
+#if 0
+		offset = DHT11_EDGES_PREAMBLE +
+		    dht11->num_edges - DHT11_EDGES_PER_READ;
+		printk("%s-%d: offset = %d\n", __func__, __LINE__, offset);
+
+		for (; offset >= 0; --offset)
+#endif
+		{
+			ret = dht11_decode(dht11, 1);
+			//if (!ret)
+			//      break;
+		}
+
+		if (ret)
+			goto err;
+	}
+
+	ret = IIO_VAL_INT;
+	if (chan->type == IIO_TEMP)
+		*val = dht11->temperature;
+	else if (chan->type == IIO_HUMIDITYRELATIVE)
+		*val = dht11->humidity;
+	else
+		ret = -EINVAL;
+	//printk("%s:%d\n",__func__,__LINE__);
+err:
+	dht11->num_edges = -1;
+	mutex_unlock(&dht11->lock);
+	return ret;
+}
+
+static const struct iio_info dht11_iio_info = {
+	.read_raw = dht11_read_raw,
+};
+
+static const struct iio_chan_spec dht11_chan_spec[] = {
+	{.type = IIO_TEMP,
+	 .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED),},
+	{.type = IIO_HUMIDITYRELATIVE,
+	 .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED),}
+};
+
+static const struct of_device_id dht11_dt_ids[] = {
+	{.compatible = "dht11",},
+	{}
+};
+
+MODULE_DEVICE_TABLE(of, dht11_dt_ids);
+
+static int dht11_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct device_node *node = dev->of_node;
+	struct dht11 *dht11;
+	struct iio_dev *iio;
+	int ret;
+
+	iio = devm_iio_device_alloc(dev, sizeof(*dht11));
+	if (!iio) {
+		dev_err(dev, "Failed to allocate IIO device\n");
+		return -ENOMEM;
+	}
+
+	dht11 = iio_priv(iio);
+	dht11->dev = dev;
+
+	ret = of_get_gpio(node, 0);
+	if (ret < 0)
+		return ret;
+	dht11->gpio = ret;
+	ret = devm_gpio_request_one(dev, dht11->gpio, GPIOF_IN, pdev->name);
+	if (ret)
+		return ret;
+
+	dht11->irq = gpio_to_irq(dht11->gpio);
+	if (dht11->irq < 0) {
+		dev_err(dev, "GPIO %d has no interrupt\n", dht11->gpio);
+		return -EINVAL;
+	}
+
+	dht11->timestamp = ktime_get_boot_ns() - DHT11_DATA_VALID_TIME - 1;
+	dht11->num_edges = -1;
+
+	platform_set_drvdata(pdev, iio);
+
+	init_completion(&dht11->completion);
+	mutex_init(&dht11->lock);
+	iio->name = pdev->name;
+	iio->dev.parent = &pdev->dev;
+	iio->info = &dht11_iio_info;
+	iio->modes = INDIO_DIRECT_MODE;
+	iio->channels = dht11_chan_spec;
+	iio->num_channels = ARRAY_SIZE(dht11_chan_spec);
+
+	return devm_iio_device_register(dev, iio);
+}
+
+static struct platform_driver dht11_driver = {
+	.driver = {
+		   .name = DRIVER_NAME,
+		   .of_match_table = dht11_dt_ids,
+		   },
+	.probe = dht11_probe,
+};
+
+module_platform_driver(dht11_driver);
+
+MODULE_AUTHOR("Harald Geyer <harald@ccbib.org>");
+MODULE_DESCRIPTION("DHT11 humidity/temperature sensor driver");
+MODULE_LICENSE("GPL v2");
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/dht11/dht11.c~ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/dht11/dht11.c~
new file mode 100644
index 0000000000000000000000000000000000000000..ac0180de473d78b66586f03832f461896b21c8c2
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/dht11/dht11.c~
@@ -0,0 +1,373 @@
+/*
+ * DHT11/DHT22 bit banging GPIO driver
+ *
+ * Copyright (c) Harald Geyer <harald@ccbib.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#include <linux/err.h>
+#include <linux/interrupt.h>
+#include <linux/device.h>
+#include <linux/kernel.h>
+#include <linux/printk.h>
+#include <linux/slab.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/sysfs.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/wait.h>
+#include <linux/bitops.h>
+#include <linux/completion.h>
+#include <linux/mutex.h>
+#include <linux/delay.h>
+#include <linux/gpio.h>
+#include <linux/of_gpio.h>
+#include <linux/timekeeping.h>
+
+#include <linux/iio/iio.h>
+
+#define DRIVER_NAME	"dht11"
+
+#define DHT11_DATA_VALID_TIME	2000000000  /* 2s in ns */
+
+#define DHT11_EDGES_PREAMBLE 2
+#define DHT11_BITS_PER_READ 40
+/*
+ * Note that when reading the sensor actually 84 edges are detected, but
+ * since the last edge is not significant, we only store 83:
+ */
+#define DHT11_EDGES_PER_READ (2 * DHT11_BITS_PER_READ + \
+			      DHT11_EDGES_PREAMBLE + 1)
+
+/*
+ * Data transmission timing:
+ * Data bits are encoded as pulse length (high time) on the data line.
+ * 0-bit: 22-30uS -- typically 26uS (AM2302)
+ * 1-bit: 68-75uS -- typically 70uS (AM2302)
+ * The acutal timings also depend on the properties of the cable, with
+ * longer cables typically making pulses shorter.
+ *
+ * Our decoding depends on the time resolution of the system:
+ * timeres > 34uS ... don't know what a 1-tick pulse is
+ * 34uS > timeres > 30uS ... no problem (30kHz and 32kHz clocks)
+ * 30uS > timeres > 23uS ... don't know what a 2-tick pulse is
+ * timeres < 23uS ... no problem
+ *
+ * Luckily clocks in the 33-44kHz range are quite uncommon, so we can
+ * support most systems if the threshold for decoding a pulse as 1-bit
+ * is chosen carefully. If somebody really wants to support clocks around
+ * 40kHz, where this driver is most unreliable, there are two options.
+ * a) select an implementation using busy loop polling on those systems
+ * b) use the checksum to do some probabilistic decoding
+ */
+#define DHT11_START_TRANSMISSION_MIN	18000  /* us */
+#define DHT11_START_TRANSMISSION_MAX	20000  /* us */
+#define DHT11_MIN_TIMERES	34000  /* ns */
+#define DHT11_THRESHOLD		49000  /* ns */
+#define DHT11_AMBIG_LOW		23000  /* ns */
+#define DHT11_AMBIG_HIGH	30000  /* ns */
+
+struct dht11 {
+	struct device			*dev;
+
+	int				gpio;
+	int				irq;
+
+	struct completion		completion;
+	/* The iio sysfs interface doesn't prevent concurrent reads: */
+	struct mutex			lock;
+
+	s64				timestamp;
+	int				temperature;
+	int				humidity;
+
+	/* num_edges: -1 means "no transmission in progress" */
+	int				num_edges;
+	struct {s64 ts; int value; }	edges[DHT11_EDGES_PER_READ];
+};
+
+#ifdef CONFIG_DYNAMIC_DEBUG
+/*
+ * dht11_edges_print: show the data as actually received by the
+ *                    driver.
+ */
+static void dht11_edges_print(struct dht11 *dht11)
+{
+	int i;
+
+	dev_dbg(dht11->dev, "%d edges detected:\n", dht11->num_edges);
+	for (i = 1; i < dht11->num_edges; ++i) {
+		dev_dbg(dht11->dev, "%d: %lld ns %s\n", i,
+			dht11->edges[i].ts - dht11->edges[i - 1].ts,
+			dht11->edges[i - 1].value ? "high" : "low");
+	}
+}
+#endif /* CONFIG_DYNAMIC_DEBUG */
+
+static unsigned char dht11_decode_byte(char *bits)
+{
+	unsigned char ret = 0;
+	int i;
+
+	for (i = 0; i < 8; ++i) {
+		ret <<= 1;
+		if (bits[i])
+			++ret;
+	}
+
+	return ret;
+}
+
+static int dht11_decode(struct dht11 *dht11, int offset)
+{
+	int i, t;
+	char bits[DHT11_BITS_PER_READ];
+	unsigned char temp_int, temp_dec, hum_int, hum_dec, checksum;
+
+	for (i = 0; i < DHT11_BITS_PER_READ; ++i) {
+		t = dht11->edges[offset + 2 * i + 2].ts -
+			dht11->edges[offset + 2 * i + 1].ts;
+		if (!dht11->edges[offset + 2 * i + 1].value) {
+			dev_dbg(dht11->dev,
+				"lost synchronisation at edge %d\n",
+				offset + 2 * i + 1);
+			return -EIO;
+		}
+		bits[i] = t > DHT11_THRESHOLD;
+	}
+
+	hum_int = dht11_decode_byte(bits);
+	hum_dec = dht11_decode_byte(&bits[8]);
+	temp_int = dht11_decode_byte(&bits[16]);
+	temp_dec = dht11_decode_byte(&bits[24]);
+	checksum = dht11_decode_byte(&bits[32]);
+
+	if (((hum_int + hum_dec + temp_int + temp_dec) & 0xff) != checksum) {
+		printk("invalid checksum\n");
+		return -EIO;
+	}
+
+	dht11->timestamp = ktime_get_boot_ns();
+#if 0
+	if (hum_int < 4) {  /* DHT22: 100000 = (3*256+232)*100 */
+		dht11->temperature = (((temp_int & 0x7f) << 8) + temp_dec) *
+					((temp_int & 0x80) ? -100 : 100);
+		dht11->humidity = ((hum_int << 8) + hum_dec) * 100;
+	} else if (temp_dec == 0 && hum_dec == 0) {  /* DHT11 */
+		dht11->temperature = temp_int * 1000;
+		dht11->humidity = hum_int * 1000;
+	} else {
+		dev_err(dht11->dev,
+			"Don't know how to decode data: %d %d %d %d\n",
+			hum_int, hum_dec, temp_int, temp_dec);
+		return -EIO;
+	}
+#endif
+	
+	dht11->temperature = temp_int;//(((temp_int & 0x7f) << 8) + temp_dec) *((temp_int & 0x80) ? -100 : 100);
+	dht11->humidity = hum_int;//((hum_int << 8) + hum_dec) * 100;
+	return 0;
+}
+
+/*
+ * IRQ handler called on GPIO edges
+ */
+static irqreturn_t dht11_handle_irq(int irq, void *data)
+{
+	struct iio_dev *iio = data;
+	struct dht11 *dht11 = iio_priv(iio);
+	/* TODO: Consider making the handler safe for IRQ sharing */
+	if (dht11->num_edges < DHT11_EDGES_PER_READ && dht11->num_edges >= 0) {
+		dht11->edges[dht11->num_edges].ts = ktime_get_boot_ns();
+		dht11->edges[dht11->num_edges++].value =
+						gpio_get_value(dht11->gpio);
+
+		if (dht11->num_edges >= DHT11_EDGES_PER_READ)
+			complete(&dht11->completion);
+	}
+
+	return IRQ_HANDLED;
+}
+
+static int dht11_read_raw(struct iio_dev *iio_dev,
+			  const struct iio_chan_spec *chan,
+			int *val, int *val2, long m)
+{
+	struct dht11 *dht11 = iio_priv(iio_dev);
+	int ret, timeres, offset;
+
+	mutex_lock(&dht11->lock);
+	
+	if (dht11->timestamp + DHT11_DATA_VALID_TIME < ktime_get_boot_ns()) {
+		timeres = ktime_get_resolution_ns();
+		dev_dbg(dht11->dev, "current timeresolution: %dns\n", timeres);
+		
+		if (timeres > DHT11_MIN_TIMERES) {
+			dev_err(dht11->dev, "timeresolution %dns too low\n",
+				timeres);
+			/* In theory a better clock could become available
+			 * at some point ... and there is no error code
+			 * that really fits better.
+			 */
+			ret = -EAGAIN;
+			goto err;
+		}
+		if (timeres > DHT11_AMBIG_LOW && timeres < DHT11_AMBIG_HIGH)
+			dev_warn(dht11->dev,
+				 "timeresolution: %dns - decoding ambiguous\n",
+				 timeres);
+
+		reinit_completion(&dht11->completion);
+
+		dht11->num_edges = 0;
+		ret = gpio_direction_output(dht11->gpio, 0);
+		if (ret)
+			goto err;
+		usleep_range(DHT11_START_TRANSMISSION_MIN,
+			     DHT11_START_TRANSMISSION_MAX);
+		ret = gpio_direction_input(dht11->gpio);
+//		if (ret)
+//			goto err;
+
+		ret = request_irq(dht11->irq, dht11_handle_irq,
+				  IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
+				  iio_dev->name, iio_dev);
+		if (ret)
+			goto err;
+
+		ret = wait_for_completion_killable_timeout(&dht11->completion,
+							   HZ);
+
+		free_irq(dht11->irq, iio_dev);
+
+#ifdef CONFIG_DYNAMIC_DEBUG
+		dht11_edges_print(dht11);
+#endif
+
+		if (ret == 0 && dht11->num_edges < DHT11_EDGES_PER_READ - 1) {
+			dev_err(dht11->dev, "Only %d signal edges detected\n",
+				dht11->num_edges);
+			ret = -ETIMEDOUT;
+		}
+		if (ret < 0)
+			goto err;
+#if 0
+		offset = DHT11_EDGES_PREAMBLE +
+				dht11->num_edges - DHT11_EDGES_PER_READ;
+		printk("%s-%d: offset = %d\n",__func__,__LINE__, offset);
+ 
+		
+		for (; offset >= 0; --offset) 
+#endif
+		{
+			ret = dht11_decode(dht11, 1);
+			//if (!ret)
+			//	break;
+		}
+
+		if (ret)
+			goto err;
+	}
+
+	ret = IIO_VAL_INT;
+	if (chan->type == IIO_TEMP)
+		*val = dht11->temperature;
+	else if (chan->type == IIO_HUMIDITYRELATIVE)
+		*val = dht11->humidity;
+	else
+		ret = -EINVAL;
+	//printk("%s:%d\n",__func__,__LINE__);
+err:
+	dht11->num_edges = -1;
+	mutex_unlock(&dht11->lock);
+	return ret;
+}
+
+static const struct iio_info dht11_iio_info = {
+	.read_raw		= dht11_read_raw,
+};
+
+static const struct iio_chan_spec dht11_chan_spec[] = {
+	{ .type = IIO_TEMP,
+		.info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED), },
+	{ .type = IIO_HUMIDITYRELATIVE,
+		.info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED), }
+};
+
+static const struct of_device_id dht11_dt_ids[] = {
+	{ .compatible = "dht11", },
+	{ }
+};
+MODULE_DEVICE_TABLE(of, dht11_dt_ids);
+
+static int dht11_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct device_node *node = dev->of_node;
+	struct dht11 *dht11;
+	struct iio_dev *iio;
+	int ret;
+
+	iio = devm_iio_device_alloc(dev, sizeof(*dht11));
+	if (!iio) {
+		dev_err(dev, "Failed to allocate IIO device\n");
+		return -ENOMEM;
+	}
+
+	dht11 = iio_priv(iio);
+	dht11->dev = dev;
+
+	ret = of_get_gpio(node, 0);
+	if (ret < 0)
+		return ret;
+	dht11->gpio = ret;
+	ret = devm_gpio_request_one(dev, dht11->gpio, GPIOF_IN, pdev->name);
+	if (ret)
+		return ret;
+
+	dht11->irq = gpio_to_irq(dht11->gpio);
+	if (dht11->irq < 0) {
+		dev_err(dev, "GPIO %d has no interrupt\n", dht11->gpio);
+		return -EINVAL;
+	}
+
+	dht11->timestamp = ktime_get_boot_ns() - DHT11_DATA_VALID_TIME - 1;
+	dht11->num_edges = -1;
+
+	platform_set_drvdata(pdev, iio);
+
+	init_completion(&dht11->completion);
+	mutex_init(&dht11->lock);
+	iio->name = pdev->name;
+	iio->dev.parent = &pdev->dev;
+	iio->info = &dht11_iio_info;
+	iio->modes = INDIO_DIRECT_MODE;
+	iio->channels = dht11_chan_spec;
+	iio->num_channels = ARRAY_SIZE(dht11_chan_spec);
+
+	return devm_iio_device_register(dev, iio);
+}
+
+static struct platform_driver dht11_driver = {
+	.driver = {
+		.name	= DRIVER_NAME,
+		.of_match_table = dht11_dt_ids,
+	},
+	.probe  = dht11_probe,
+};
+
+module_platform_driver(dht11_driver);
+
+MODULE_AUTHOR("Harald Geyer <harald@ccbib.org>");
+MODULE_DESCRIPTION("DHT11 humidity/temperature sensor driver");
+MODULE_LICENSE("GPL v2");
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/ds18b20/Makefile b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/ds18b20/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..bd1fbe2db0301148173a8968d78a47a108a97181
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/ds18b20/Makefile
@@ -0,0 +1,45 @@
+#
+# Makefile for the Dallas's 1-wire bus.
+#
+
+#
+#Copyright (C) 2019 Seeed Technology Co,Ltd  - https://www.seeed.cc
+#Author: Baozhu Zuo <zuobaozhu@gmail.com>#
+#This program is free software; you can redistribute it and/or modify
+#it under the terms of the GNU General Public License version 2 as
+#published by the Free Software Foundation.
+#
+# no irq version
+
+_uname_r := $(shell uname -r)
+_BUILD   := /lib/modules/$(_uname_r)/build
+_PWD     := $(shell pwd)
+_DEPMOD  ?= depmod -a
+
+# If KERNELRELEASE is defined, we've been invoked from the
+# kernel build system and can use its language
+ifneq ($(KERNELRELEASE),)
+
+
+obj-m		+= w1-gpio.o
+else
+_class  := drivers/input
+
+DEST  := /lib/modules/$(_uname_r)/kernel
+
+all:
+	make -C ${_BUILD} M=$(_PWD) modules
+
+clean:
+	make -C ${_BUILD} M=$(_PWD) clean
+
+install:
+	cp w1-gpio.ko ${DEST}/${_class}/
+	$(_DEPMOD)
+	@echo w1-gpio.ko >> /etc/modules
+uninstall:
+	rm -f ${DEST}/${_class}/w1-gpio.ko 
+	$(_DEPMOD)
+	
+.PHONY: all clean install uninstall
+endif
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/ds18b20/w1-gpio.c b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/ds18b20/w1-gpio.c
new file mode 100644
index 0000000000000000000000000000000000000000..9908de0820783561a6ea5bbfa61ed6bf9156ea40
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/ds18b20/w1-gpio.c
@@ -0,0 +1,212 @@
+/*
+ * w1-gpio - GPIO w1 bus master driver
+ *
+ * Copyright (C) 2007 Ville Syrjala <syrjala@sci.fi>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation.
+ */
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include <linux/w1-gpio.h>
+#include <linux/gpio/consumer.h>
+#include <linux/of_platform.h>
+#include <linux/err.h>
+#include <linux/of.h>
+#include <linux/delay.h>
+
+#include <linux/w1.h>
+
+static u8 w1_gpio_set_pullup(void *data, int delay)
+{
+	struct w1_gpio_platform_data *pdata = data;
+
+	if (delay) {
+		pdata->pullup_duration = delay;
+	} else {
+		if (pdata->pullup_duration) {
+			/*
+			 * This will OVERRIDE open drain emulation and force-pull
+			 * the line high for some time.
+			 */
+			gpiod_direction_output_raw(pdata->gpiod, 1);
+			msleep(pdata->pullup_duration);
+			/*
+			 * This will simply set the line as input since we are doing
+			 * open drain emulation in the GPIO library.
+			 */
+			gpiod_set_value(pdata->gpiod, 1);
+		}
+		pdata->pullup_duration = 0;
+	}
+
+	return 0;
+}
+
+static void w1_gpio_write_bit(void *data, u8 bit)
+{
+	struct w1_gpio_platform_data *pdata = data;
+
+	gpiod_set_value(pdata->gpiod, bit);
+}
+
+static u8 w1_gpio_read_bit(void *data)
+{
+	u8 val;		
+	struct w1_gpio_platform_data *pdata = data;
+	//printk("cc: %s-%d:\n", __func__, __LINE__);
+	gpiod_direction_input(pdata->gpiod);
+	val = gpiod_get_value(pdata->gpiod) ? 1 : 0;
+	gpiod_direction_output(pdata->gpiod, 1);
+	return val;
+}
+#if defined(CONFIG_OF)
+static const struct of_device_id w1_gpio_dt_ids[] = {
+	{ .compatible = "w1-gpio" },
+	{}
+};
+MODULE_DEVICE_TABLE(of, w1_gpio_dt_ids);
+#endif
+
+static int w1_gpio_probe(struct platform_device *pdev)
+{
+	struct w1_bus_master *master;
+	struct w1_gpio_platform_data *pdata;
+	struct device *dev = &pdev->dev;
+	struct device_node *np = dev->of_node;
+	/* Enforce open drain mode by default */
+	enum gpiod_flags gflags = GPIOD_OUT_LOW_OPEN_DRAIN;
+	int err;
+
+	if (of_have_populated_dt()) {
+		pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
+		if (!pdata)
+			return -ENOMEM;
+
+		/*
+		 * This parameter means that something else than the gpiolib has
+		 * already set the line into open drain mode, so we should just
+		 * driver it high/low like we are in full control of the line and
+		 * open drain will happen transparently.
+		 */
+		if (of_get_property(np, "linux,open-drain", NULL))
+			gflags = GPIOD_OUT_LOW;
+
+		pdev->dev.platform_data = pdata;
+	}
+	pdata = dev_get_platdata(dev);
+
+	if (!pdata) {
+		dev_err(dev, "No configuration data\n");
+		return -ENXIO;
+	}
+
+	master = devm_kzalloc(dev, sizeof(struct w1_bus_master),
+			GFP_KERNEL);
+	if (!master) {
+		dev_err(dev, "Out of memory\n");
+		return -ENOMEM;
+	}
+
+	pdata->gpiod = devm_gpiod_get_index(dev, NULL, 0, gflags);
+	if (IS_ERR(pdata->gpiod)) {
+		dev_err(dev, "gpio_request (pin) failed\n");
+		return PTR_ERR(pdata->gpiod);
+	}
+
+	pdata->pullup_gpiod =
+		devm_gpiod_get_index_optional(dev, NULL, 1, GPIOD_OUT_LOW);
+	if (IS_ERR(pdata->pullup_gpiod)) {
+		dev_err(dev, "gpio_request_one "
+			"(ext_pullup_enable_pin) failed\n");
+		return PTR_ERR(pdata->pullup_gpiod);
+	}
+
+	master->data = pdata;
+	master->read_bit = w1_gpio_read_bit;
+	gpiod_direction_output(pdata->gpiod, 1);
+	master->write_bit = w1_gpio_write_bit;
+
+	/*
+	 * If we are using open drain emulation from the GPIO library,
+	 * we need to use this pullup function that hammers the line
+	 * high using a raw accessor to provide pull-up for the w1
+	 * line.
+	 */
+	if (gflags == GPIOD_OUT_LOW_OPEN_DRAIN)
+		master->set_pullup = w1_gpio_set_pullup;
+
+	err = w1_add_master_device(master);
+	if (err) {
+		dev_err(dev, "w1_add_master device failed\n");
+		return err;
+	}
+
+	if (pdata->enable_external_pullup)
+		pdata->enable_external_pullup(1);
+
+	if (pdata->pullup_gpiod)
+		gpiod_set_value(pdata->pullup_gpiod, 1);
+
+	platform_set_drvdata(pdev, master);
+
+	return 0;
+}
+
+static int w1_gpio_remove(struct platform_device *pdev)
+{
+	struct w1_bus_master *master = platform_get_drvdata(pdev);
+	struct w1_gpio_platform_data *pdata = dev_get_platdata(&pdev->dev);
+
+	if (pdata->enable_external_pullup)
+		pdata->enable_external_pullup(0);
+
+	if (pdata->pullup_gpiod)
+		gpiod_set_value(pdata->pullup_gpiod, 0);
+
+	w1_remove_master_device(master);
+
+	return 0;
+}
+
+static int __maybe_unused w1_gpio_suspend(struct device *dev)
+{
+	struct w1_gpio_platform_data *pdata = dev_get_platdata(dev);
+
+	if (pdata->enable_external_pullup)
+		pdata->enable_external_pullup(0);
+
+	return 0;
+}
+
+static int __maybe_unused w1_gpio_resume(struct device *dev)
+{
+	struct w1_gpio_platform_data *pdata = dev_get_platdata(dev);
+
+	if (pdata->enable_external_pullup)
+		pdata->enable_external_pullup(1);
+
+	return 0;
+}
+
+static SIMPLE_DEV_PM_OPS(w1_gpio_pm_ops, w1_gpio_suspend, w1_gpio_resume);
+
+static struct platform_driver w1_gpio_driver = {
+	.driver = {
+		.name	= "w1-gpio",
+		.pm	= &w1_gpio_pm_ops,
+		.of_match_table = of_match_ptr(w1_gpio_dt_ids),
+	},
+	.probe = w1_gpio_probe,
+	.remove = w1_gpio_remove,
+};
+
+module_platform_driver(w1_gpio_driver);
+
+MODULE_DESCRIPTION("GPIO w1 bus master driver");
+MODULE_AUTHOR("Ville Syrjala <syrjala@sci.fi>");
+MODULE_LICENSE("GPL");
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/e-ink/Makefile b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/e-ink/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..893cd060ecb55c4229a54c0d0d3ae2e6dd82a202
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/e-ink/Makefile
@@ -0,0 +1,42 @@
+#
+# Peter Yang <turmary@126.com>
+# Copyright (c) 2019 Seeed Studio
+#
+# MIT License
+#
+
+# no irq version
+_tgt     := eink-tty
+
+_uname_r := $(shell uname -r)
+_BUILD   := /lib/modules/$(_uname_r)/build
+_PWD     := $(shell pwd)
+_DEPMOD  ?= depmod -a
+
+# If KERNELRELEASE is defined, we've been invoked from the
+# kernel build system and can use its language
+ifneq ($(KERNELRELEASE),)
+
+obj-m += ${_tgt}.o
+
+else
+_class  := drivers/misc
+
+DEST  := /lib/modules/$(_uname_r)/kernel
+
+all:
+	make -C ${_BUILD} M=$(_PWD) modules
+
+clean:
+	make -C ${_BUILD} M=$(_PWD) clean
+
+install:
+	cp ${_tgt}.ko ${DEST}/${_class}/
+	$(_DEPMOD)
+
+uninstall:
+	rm -f ${DEST}/${_class}/${_tgt}.ko
+	$(_DEPMOD)
+
+.PHONY: all clean install uninstall
+endif
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/e-ink/eink-tty.c b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/e-ink/eink-tty.c
new file mode 100644
index 0000000000000000000000000000000000000000..2b5f924d8375af4482c95883a8b334746aa7c99d
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/e-ink/eink-tty.c
@@ -0,0 +1,527 @@
+/*
+ * Triple Color E-Ink Display Driver
+ *
+ * Copyright (C) 2019 Seeed Studio
+ * Peter Yang <turmary@126.com>
+ *
+ * Released under the GPL
+ *
+ */
+
+#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/fs.h>
+#include <linux/device.h>
+#include <linux/errno.h>
+#include <linux/mutex.h>
+#include <linux/of.h>
+#include <linux/slab.h>
+#include <linux/platform_device.h>
+#include <linux/miscdevice.h>
+#include <linux/termios.h>
+#include <linux/delay.h>
+#include <linux/sched.h>
+#include <asm/ioctls.h>
+#include <linux/serial.h>
+#include <linux/poll.h>
+
+#define DEFAULT_BAUDRATE	230400
+#define DEFAULT_TTY		"/dev/ttyS4"
+#define DEFAULT_LINE_LEN	152
+#define DEFAULT_LINES		152
+
+#define EINK_HDR		'a'
+#define EINK_HDR_RSP		'b'
+
+#define EINK_CHK_PROGRESS	0
+#define EINK_TAG_NEXT		"NEXT!"
+#define EINK_TAG_DONE		"DONE!"
+#define EINK_TAG_DBG		0
+#define EINK_TIMEOUT		3000 /* ms */
+
+#define EINK_LINE_DLY		48   /* ms */
+
+#define EINK_POLL_WAIT		0
+
+/*
+ * This driver creates a character device (/dev/eink) which exposes the
+ * Triple Color E-ink Display
+ */
+
+struct eink_dev {
+	/* misc device descriptor */
+	struct miscdevice miscdev;
+
+	/* port (/dev/ttyS1 eg.) & speed (115200 eg.)*/
+	const char* tty_port;
+	u32	baudrate;
+
+	/* locks */
+	struct mutex mutex;
+
+	/* screen x-res & y-res */
+	u32	line_len, num_lines;
+	u32	size;
+
+	/* tty port info */
+	struct file* tty;
+
+	/* bytes left to written of one display data image */
+	int bytes_left;
+};
+#define to_eink_dev(dev)  container_of((dev), struct eink_dev, miscdev)
+static int dev_index = 0;
+
+static long eink_tty_ioctl(struct file *f, unsigned int op,
+				 unsigned long param)
+{
+	if (f->f_op->unlocked_ioctl)
+		return f->f_op->unlocked_ioctl(f, op, param);
+
+	return -ENOTTY;
+}
+
+static int eink_tty_write(struct file *f, unsigned char *buf, int count)
+{
+	loff_t pos = 0;
+	return kernel_write(f, buf, count, &pos);
+}
+
+#if EINK_POLL_WAIT
+static void eink_tty_read_poll_wait(struct file *f, int timeout)
+{
+	struct poll_wqueues table;
+	ktime_t start, now;
+
+	start = ktime_get();
+	poll_initwait(&table);
+	while (1) {
+		long elapsed;
+		int mask;
+
+		mask = f->f_op->poll(f, &table.pt);
+		if (mask & (POLLRDNORM | POLLRDBAND | POLLIN |
+			    POLLHUP | POLLERR)) {
+			break;
+		}
+		now = ktime_get();
+		elapsed = ktime_us_delta(now, start);
+		if (elapsed > timeout)
+			break;
+		set_current_state(TASK_INTERRUPTIBLE);
+		schedule_timeout(((timeout - elapsed) * HZ) / 10000);
+	}
+	poll_freewait(&table);
+}
+#endif
+
+static int eink_tty_read(struct file *f, int timeout)
+{
+	unsigned char ch;
+	int rc;
+	loff_t pos = 0;
+
+	rc = -ETIMEDOUT;
+	if (IS_ERR(f)) {
+		return -EINVAL;
+	}
+
+	#if EINK_POLL_WAIT
+	if (f->f_op->poll) {
+		eink_tty_read_poll_wait(f, timeout);
+
+		if (kernel_read(f, &ch, 1, &pos) == 1)
+			rc = ch;
+	}
+	else
+	#endif
+	{
+		/* Device does not support poll, busy wait */
+		int retries = 0;
+
+		while (1) {
+			if (kernel_read(f, &ch, 1, &pos) == 1) {
+				rc = ch;
+				break;
+			}
+
+			if (++retries > timeout) {
+				break;
+			}
+			usleep_range(800, 1200);
+		}
+	}
+	return rc;
+}
+
+static int eink_tty_block(struct file *f) {
+	mm_segment_t oldfs;
+	int fl;
+
+	oldfs = get_fs();
+
+	/* Set fd block */
+	fl = eink_tty_ioctl(f, F_GETFL, 0);
+	if (fl == -1) {
+		return fl;
+	}
+	fl &= ~O_NONBLOCK;
+
+	set_fs(KERNEL_DS);
+	eink_tty_ioctl(f, F_SETFL, (unsigned)fl);
+	set_fs(oldfs);
+	return 0;
+}
+
+static int eink_tty_setspeed(struct file *f, int speed)
+{
+	struct termios termios;
+	struct serial_struct serial;
+	mm_segment_t oldfs;
+
+	oldfs = get_fs();
+	set_fs(KERNEL_DS);
+
+	/* Set speed */
+	eink_tty_ioctl(f, TCGETS, (unsigned long)&termios);
+	termios.c_iflag = 0;
+	termios.c_oflag = 0;
+	termios.c_lflag = 0;
+	termios.c_cflag = CLOCAL | CS8 | CREAD;
+	termios.c_cc[VMIN] = 1;
+	termios.c_cc[VTIME] = 0;
+
+	switch (speed) {
+	case 2400:
+		termios.c_cflag |= B2400;
+		break;
+	case 4800:
+		termios.c_cflag |= B4800;
+		break;
+	case 9600:
+		termios.c_cflag |= B9600;
+		break;
+	case 19200:
+		termios.c_cflag |= B19200;
+		break;
+	case 38400:
+		termios.c_cflag |= B38400;
+		break;
+	case 57600:
+		termios.c_cflag |= B57600;
+		break;
+	case 115200:
+		termios.c_cflag |= B115200;
+		break;
+	case 230400:
+		termios.c_cflag |= B230400;
+		break;
+	default:
+		termios.c_cflag |= B9600;
+		break;
+	}
+	eink_tty_ioctl(f, TCSETS, (unsigned long)&termios);
+
+	/* Set low latency */
+	eink_tty_ioctl(f, TIOCGSERIAL, (unsigned long)&serial);
+	serial.flags |= ASYNC_LOW_LATENCY;
+	eink_tty_ioctl(f, TIOCSSERIAL, (unsigned long)&serial);
+
+	/* Clear input buffer */
+	eink_tty_ioctl(f, TCFLSH, TCIOFLUSH);
+
+	set_fs(oldfs);
+
+	return 0;
+}
+
+#if EINK_CHK_PROGRESS
+#define LINE_BUF_SZ	20
+#define TIMEOUT_MAX	100
+static int eink_check_progress(struct eink_dev *edev) {
+	static char buf[LINE_BUF_SZ];
+	static int index;
+	int rc;
+	int timeout;
+
+	memset(buf, '\0', sizeof buf);
+	for (timeout = TIMEOUT_MAX; timeout > 0; ) {
+		if ((rc = eink_tty_read(edev->tty, 1)) < 0) {
+			usleep_range(1000, 1000);
+			timeout--;
+			continue;
+		}
+
+		#if EINK_TAG_DBG
+		pr_info("R %c x%02X\n", rc, rc);
+		#endif
+
+		if (rc == '\r' || rc == '\n') {
+			if (!strcmp(buf, EINK_TAG_NEXT) ||
+			    !strcmp(buf, EINK_TAG_DONE)) {
+				#if EINK_TAG_DBG
+				pr_info("next or done\n");
+				#endif
+				break;
+			}
+			index = 0;
+			memset(buf, '\0', sizeof buf);
+		} else if (index < LINE_BUF_SZ - 1) {
+			buf[index++] = rc;
+			buf[index] = '\0';
+		}
+	}
+	if (timeout <= 0) {
+		return -ETIMEDOUT;
+	}
+
+	#if EINK_TAG_DBG
+	pr_info("timeout = %d\n", timeout);
+	#endif
+
+	/* Firmware bug: this time to wait burning flash data */
+	msleep(EINK_LINE_DLY + timeout - TIMEOUT_MAX);
+	return 0;
+}
+#endif
+
+static ssize_t eink_write(struct file *f, const char __user *buf,
+			     size_t len, loff_t *f_pos)
+{
+	struct eink_dev *edev = to_eink_dev(f->private_data);
+	/* 4 lines each time */
+	int each_max = edev->line_len / 8 * 4;
+	int rc = 0;
+	int left;
+
+	for (left = len; left > 0; ) {
+		int line = min(left, each_max);
+
+		if ((rc = eink_tty_write(edev->tty, (u8*)buf, line)) < 0) {
+			break;
+		}
+		buf += rc;
+		left -= rc;
+
+		/* e-ink slow wrtting */
+		#if EINK_CHK_PROGRESS
+		eink_check_progress(edev);
+		#else
+		msleep(EINK_LINE_DLY);
+		#endif
+	}
+	if (len != left) {
+		rc = len - left;
+		edev->bytes_left -= rc;
+	}
+	return rc;
+}
+
+/*
+ * header & response protocol
+ */
+static int eink_send_header(struct file* tty) {
+	int rc, timeout;
+	u8 header = EINK_HDR;
+
+	/* clear receiving buffer, in 1 seconds */
+	timeout = 100;
+	while ((rc = eink_tty_read(tty, 10)) >= 0) {
+		pr_info("recv: 0x%02X\n", rc);
+		if (timeout-- <= 0) {
+			return -EBUSY;
+		}
+	}
+
+	/* it's blocked from now on */
+	eink_tty_block(tty);
+
+	if ((rc = eink_tty_write(tty, &header, sizeof header)) < 0) {
+		pr_info("write e-ink error = %d\n", rc);
+		return -EINVAL;
+	}
+
+	if ((rc = eink_tty_read(tty, EINK_TIMEOUT)) < 0) {
+		pr_info("read e-ink error = %d\n", rc);
+		return rc;
+	}
+
+	if (rc != EINK_HDR_RSP) {
+		pr_info("invalid response = 0x%02x\n", rc);
+		return -ENODEV;
+	}
+
+	return 0;
+}
+
+static int eink_open(struct inode *inode, struct file *f)
+{
+	struct eink_dev *edev = to_eink_dev(f->private_data);
+	struct device* dev = edev->miscdev.this_device;
+	int rc = 0;
+
+	if (!mutex_trylock(&edev->mutex)) {
+		pr_debug("Device Busy\n");
+		return -EBUSY;
+	}
+
+	edev->tty = filp_open(edev->tty_port, O_RDWR | O_NONBLOCK, 0);
+	if (IS_ERR(edev->tty)) {
+		rc = (int)PTR_ERR(edev->tty);
+		dev_err(dev, "file %s open error = %d\n", edev->tty_port, rc);
+		goto fail;
+	}
+
+	/* Set configuration to the tty port */
+	rc = eink_tty_setspeed(edev->tty, edev->baudrate);
+	if (rc) {
+		goto fail;
+	}
+
+	/* header to probe e-ink hardware */
+	rc = eink_send_header(edev->tty);
+	if (rc) {
+		goto fail;
+	}
+
+	edev->bytes_left = edev->size;
+	return 0;
+
+fail:
+	mutex_unlock(&edev->mutex);
+	return rc;
+}
+
+static int eink_release(struct inode *inode, struct file *f)
+{
+	struct eink_dev *edev = to_eink_dev(f->private_data);
+	mutex_unlock(&edev->mutex);
+
+	filp_close(edev->tty, NULL);
+
+	if (edev->bytes_left > 0) {
+		pr_info("incomplete e-ink display data be written\n");
+		return -EINVAL;
+	}
+	return 0;
+}
+
+static const struct file_operations eink_fops = {
+	.owner		= THIS_MODULE,
+	.write		= eink_write,
+	.open		= eink_open,
+	.release	= eink_release
+};
+
+static const struct miscdevice misc_def = {
+	.minor		= MISC_DYNAMIC_MINOR,
+	.name		= "eink",
+	.mode		= S_IWUGO,
+	.fops		= &eink_fops
+};
+
+static int eink_probe(struct platform_device *pdev)
+{
+	struct device_node *np = pdev->dev.of_node;
+	struct device *dev;
+	struct eink_dev *edev;
+	int rc;
+
+	/* Allocate memory for our private structure */
+	edev = kzalloc(sizeof(*edev), GFP_KERNEL);
+	if (!edev) {
+		return -ENOMEM;
+	}
+
+	rc = of_property_read_string(np, "tty-port", &edev->tty_port);
+	if (rc) {
+		edev->tty_port = DEFAULT_TTY;
+		pr_err("tty-port property not found, use default %s\n",
+			edev->tty_port);
+	}
+
+	rc = of_property_read_u32(np, "baudrate", &edev->baudrate);
+	if (rc) {
+		edev->baudrate = DEFAULT_BAUDRATE;
+		pr_err("baudrate property not found, use default %u\n",
+			edev->baudrate);
+	}
+
+	rc = of_property_read_u32(np, "lines-len", &edev->line_len);
+	if (rc) {
+		edev->line_len = DEFAULT_LINE_LEN;
+		pr_err("lines-len property not found, use default %u\n",
+			edev->line_len);
+	}
+
+	rc = of_property_read_u32(np, "num-lines", &edev->num_lines);
+	if (rc) {
+		edev->num_lines = DEFAULT_LINES;
+		pr_err("num-lines property not found, use default %u\n",
+			edev->num_lines);
+	}
+
+	mutex_init(&edev->mutex);
+
+	/* 1 pixel occupy 2 bits */
+	edev->size = edev->line_len * edev->num_lines / 4;
+
+	pr_devel("E-ink of size %u bytes found with %u lines of length %u\n",
+		edev->size, edev->num_lines, edev->line_len);
+
+	edev->miscdev = misc_def;
+	edev->miscdev.name = kasprintf(GFP_KERNEL, "%s%d",
+				misc_def.name, dev_index++);
+	rc = misc_register(&edev->miscdev);
+	if (rc) {
+		pr_err("Failed to register as misc device\n");
+		goto free_eink;
+	}
+
+	/* platform device drvdata */
+	dev_set_drvdata(&pdev->dev, edev);
+
+	/* misc device drvdata */
+	dev = edev->miscdev.this_device;
+	dev_set_drvdata(dev, edev);
+
+	return 0;
+
+free_eink:
+	kfree(edev);
+	return rc;
+}
+
+static int eink_remove(struct platform_device *pdev)
+{
+	struct eink_dev *edev = platform_get_drvdata(pdev);
+	
+	misc_deregister(&edev->miscdev);
+	kfree(edev->miscdev.name);
+	kfree(edev);
+	return 0;
+}
+
+static const struct of_device_id eink_match[] = {
+	{ .compatible = "seeed,eink" },
+	{ },
+};
+
+static struct platform_driver eink_driver = {
+	.driver	= {
+		.name		= "eink",
+		.of_match_table	= eink_match,
+	},
+	.probe	= eink_probe,
+	.remove	= eink_remove,
+};
+
+module_platform_driver(eink_driver);
+
+MODULE_DEVICE_TABLE(of, eink_match);
+MODULE_LICENSE("GPL v2");
+MODULE_DESCRIPTION("Triple Color E-Ink Display Driver");
+MODULE_AUTHOR("Peter Yang <turmary@126.com>");
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/grove-button/README.md b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/grove-button/README.md
new file mode 100644
index 0000000000000000000000000000000000000000..8a34d2f3f95bb0992d6bd02c355aeab4987a84b9
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/grove-button/README.md
@@ -0,0 +1,27 @@
+GROVE GPIO Input device
+=======================
+
+  After driver and configuration prepared well,
+  the user could access ```/dev/input/event<N>```,
+  to capture the GPIO input event.
+
+  For more description of ```/dev/input/event<N>```, refer to
+  [input](https://github.com/raspberrypi/linux/blob/rpi-4.14.y/Documentation/input/input.rst).
+
+Usage
+-----
+
+***example:***
+
+  ```bash
+  sudo apt-get install evtest
+
+  evtest
+  # now select the number <N> of event<N>
+  # then pressing the button(change Grove device output level),
+  # see the evtest output
+  ```
+
+  If you need customize the GPIO-Port/key-code/label..., refer to device tree configuration
+  [grove,button.txt](../../doc/devicetree/bindings/grove,button.txt)
+
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/grove-led/README.md b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/grove-led/README.md
new file mode 100644
index 0000000000000000000000000000000000000000..55f7b978e1c6d352f2027c2b3409020dfb971352
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/grove-led/README.md
@@ -0,0 +1,27 @@
+GROVE GPIO Output device
+========================
+
+  After driver and configuration prepared well,
+  the user could access sysfs path ```/sys/class/leds/<led>/*```,
+  default to ```/sys/class/leds/grove:usr0/```
+
+  The led name `<led>` specified in device tree source (.dts).
+
+  For entries description of `<led>/*`, refer to
+  [sysfs-class-led](https://github.com/raspberrypi/linux/blob/rpi-4.14.y/Documentation/ABI/testing/sysfs-class-led).
+
+Usage
+-----
+
+***example:***
+
+  ```bash
+  # led on
+  echo 1 > /sys/class/leds/grove:usr0/brightness
+  # led off
+  echo 0 > /sys/class/leds/grove:usr0/brightness
+  ```
+
+  If you need customize the GPIO-Port/LED-name/..., refer to device tree configuration
+  [grove,led.txt](../../doc/devicetree/bindings/grove,led.txt)
+
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/gt9xx/Makefile b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/gt9xx/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..507acc0aba6590fd76dcdc392be132d8e177fa4f
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/gt9xx/Makefile
@@ -0,0 +1,34 @@
+
+_uname_r := $(shell uname -r)
+_BUILD   := /lib/modules/$(_uname_r)/build
+_PWD     := $(shell pwd)
+_DEPMOD  ?= depmod -a
+
+# If KERNELRELEASE is defined, we've been invoked from the
+# kernel build system and can use its language
+ifneq ($(KERNELRELEASE),)
+
+touch-gt9xx-objs := gt9xx.o gt9xx_update.o goodix_tool.o
+obj-m += touch-gt9xx.o
+
+else
+_class  := drivers/input
+
+DEST  := /lib/modules/$(_uname_r)/kernel
+
+all:
+	make -C ${_BUILD} M=$(_PWD) modules
+
+clean:
+	make -C ${_BUILD} M=$(_PWD) clean
+
+install:
+	cp touch-gt9xx.ko ${DEST}/${_class}/
+	$(_DEPMOD)
+
+uninstall:
+	rm -f ${DEST}/${_class}/touch-gt9xx.ko 
+	$(_DEPMOD)
+
+.PHONY: all clean install uninstall
+endif
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/gt9xx/goodix_tool.c b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/gt9xx/goodix_tool.c
new file mode 100644
index 0000000000000000000000000000000000000000..b109618b8559949966d4b99d408dc54a7a667533
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/gt9xx/goodix_tool.c
@@ -0,0 +1,518 @@
+/*
+ * Goodix GT9xx touchscreen driver
+ *
+ * Copyright  (C)  2016 - 2017 Goodix. Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be a reference
+ * to you, when you are integrating the GOODiX's CTP IC into your system,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * Version: 2.8.0.1
+ * Release Date: 2017/10/26
+ */
+
+#include "gt9xx.h"
+
+#define DATA_LENGTH_UINT	512
+#define CMD_HEAD_LENGTH		(sizeof(struct st_cmd_head) - sizeof(u8 *))
+static char procname[20] = {0};
+
+#pragma pack(1)
+struct st_cmd_head {
+	u8	wr;		/*write read flag 0:R 1:W 2:PID 3:*/
+	u8	flag;		/*0:no need flag/int 1: need flag 2:need int*/
+	u8	flag_addr[2];	/*flag address*/
+	u8	flag_val;	/*flag val*/
+	u8	flag_relation;	/*flag_val:flag 0:not equal 1:equal 2:> 3:<*/
+	u16	circle;		/*polling cycle*/
+	u8	times;		/*plling times*/
+	u8	retry;		/*I2C retry times*/
+	u16	delay;		/*delay before read or after write*/
+	u16	data_len;	/*data length*/
+	u8	addr_len;	/*address length*/
+	u8	addr[2];	/*address*/
+	u8	res[3];		/*reserved*/
+	u8	*data; };	/*data pointer*/
+#pragma pack()
+struct st_cmd_head cmd_head;
+
+static struct i2c_client *gt_client;
+static struct proc_dir_entry *goodix_proc_entry;
+
+static ssize_t goodix_tool_read(struct file *, char __user *, size_t, loff_t *);
+static ssize_t goodix_tool_write(struct file *, const char __user *, size_t, loff_t *);
+static const struct file_operations gtp_proc_ops = {
+	.owner = THIS_MODULE,
+	.read = goodix_tool_read,
+	.write = goodix_tool_write,
+};
+
+/* static s32 goodix_tool_write(struct file *filp,
+ * const char __user *buff, unsigned long len, void *data);
+ */
+/*static s32 goodix_tool_read( char *page, char
+ **start, off_t off, int count, int *eof, void *data );
+ */
+static s32 (*tool_i2c_read)(u8 *, u16);
+static s32 (*tool_i2c_write)(u8 *, u16);
+
+s32 DATA_LENGTH = (s32)0;
+s8 IC_TYPE[16] = "GT9XX";
+
+static void tool_set_proc_name(char *procname)
+{
+	snprintf(procname, 20, "gmnode"); /* modify for moto */
+}
+
+static s32 tool_i2c_read_no_extra(u8 *buf, u16 len)
+{
+	s32 ret = -1;
+	s32 i = 0;
+	struct goodix_ts_data *ts = i2c_get_clientdata(i2c_connect_client);
+
+	for (i = 0; i < cmd_head.retry; i++) {
+		ret = gtp_i2c_read(ts->client, buf, len + GTP_ADDR_LENGTH);
+		if (ret > 0)
+			break;
+	}
+	return ret;
+}
+
+static s32 tool_i2c_write_no_extra(u8 *buf, u16 len)
+{
+	s32 ret = -1;
+	s32 i = 0;
+	struct goodix_ts_data *ts = i2c_get_clientdata(i2c_connect_client);
+
+	for (i = 0; i < cmd_head.retry; i++) {
+		ret = gtp_i2c_write(ts->client, buf, len);
+		if (ret > 0)
+			break;
+	}
+
+	return ret;
+}
+
+static s32 tool_i2c_read_with_extra(u8 *buf, u16 len)
+{
+	s32 ret = -1;
+	u8 pre[2] = {0x0f, 0xff};
+	u8 end[2] = {0x80, 0x00};
+
+	tool_i2c_write_no_extra(pre, 2);
+	ret = tool_i2c_read_no_extra(buf, len);
+	tool_i2c_write_no_extra(end, 2);
+
+	return ret;
+}
+
+static s32 tool_i2c_write_with_extra(u8 *buf, u16 len)
+{
+	s32 ret = -1;
+	u8 pre[2] = {0x0f, 0xff};
+	u8 end[2] = {0x80, 0x00};
+
+	tool_i2c_write_no_extra(pre, 2);
+	ret = tool_i2c_write_no_extra(buf, len);
+	tool_i2c_write_no_extra(end, 2);
+
+	return ret;
+}
+
+static void register_i2c_func(void)
+{
+	/* if (!strncmp(IC_TYPE, "GT818", 5)
+	 *  || !strncmp(IC_TYPE, "GT816", 5)
+	 *  || !strncmp(IC_TYPE, "GT811", 5)
+	 *  || !strncmp(IC_TYPE, "GT818F", 6)
+	 *  || !strncmp(IC_TYPE, "GT827", 5)
+	 *  || !strncmp(IC_TYPE,"GT828", 5)
+	 *  || !strncmp(IC_TYPE, "GT813", 5))
+	 */
+	if (strncmp(IC_TYPE, "GT8110", 6) &&
+	    strncmp(IC_TYPE, "GT8105", 6) &&
+	    strncmp(IC_TYPE, "GT801", 5) &&
+	    strncmp(IC_TYPE, "GT800", 5) &&
+	    strncmp(IC_TYPE, "GT801PLUS", 9) &&
+	    strncmp(IC_TYPE, "GT811", 5) &&
+	    strncmp(IC_TYPE, "GTxxx", 5) &&
+	    strncmp(IC_TYPE, "GT9XX", 5)) {
+		tool_i2c_read = tool_i2c_read_with_extra;
+		tool_i2c_write = tool_i2c_write_with_extra;
+		dev_dbg(&gt_client->dev, "I2C function: with pre and end cmd!");
+	} else {
+		tool_i2c_read = tool_i2c_read_no_extra;
+		tool_i2c_write = tool_i2c_write_no_extra;
+		dev_info(&gt_client->dev, "I2C function: without pre and end cmd!");
+	}
+}
+
+static void unregister_i2c_func(void)
+{
+	tool_i2c_read = NULL;
+	tool_i2c_write = NULL;
+	dev_info(&gt_client->dev, "I2C function: unregister i2c transfer function!");
+}
+
+s32 init_wr_node(struct i2c_client *client)
+{
+	s32 i;
+
+	gt_client = client;
+	memset(&cmd_head, 0, sizeof(cmd_head));
+	cmd_head.data = NULL;
+
+	i = 3;
+	while ((!cmd_head.data) && i) {
+		cmd_head.data = kzalloc(i * DATA_LENGTH_UINT, GFP_KERNEL);
+		if (NULL != cmd_head.data)
+			break;
+		i--;
+	}
+	if (i) {
+		DATA_LENGTH = i * DATA_LENGTH_UINT + GTP_ADDR_LENGTH;
+		dev_info(&gt_client->dev,
+			 "Applied memory size:%d.", DATA_LENGTH);
+	} else {
+		dev_err(&gt_client->dev, "Apply for memory failed.");
+		return FAIL;
+	}
+
+	cmd_head.addr_len = 2;
+	cmd_head.retry = 5;
+
+	register_i2c_func();
+
+	tool_set_proc_name(procname);
+	goodix_proc_entry = proc_create(procname, 0664, NULL, &gtp_proc_ops);
+	if (goodix_proc_entry == NULL) {
+		dev_err(&gt_client->dev, "Couldn't create proc entry!");
+		return FAIL;
+	}
+
+	dev_info(&gt_client->dev, "Create proc entry success!");
+	return SUCCESS;
+}
+
+void uninit_wr_node(void)
+{
+	kfree(cmd_head.data);
+	cmd_head.data = NULL;
+	unregister_i2c_func();
+	remove_proc_entry(procname, NULL);
+}
+
+static u8 relation(u8 src, u8 dst, u8 rlt)
+{
+	u8 ret = 0;
+
+	switch (rlt) {
+	case 0:
+		ret = (src != dst) ? true : false;
+		break;
+
+	case 1:
+		ret = (src == dst) ? true : false;
+		dev_dbg(&gt_client->dev,
+			"equal:src:0x%02x  dst:0x%02x  ret:%d.",
+			src, dst, (s32)ret);
+		break;
+
+	case 2:
+		ret = (src > dst) ? true : false;
+		break;
+
+	case 3:
+		ret = (src < dst) ? true : false;
+		break;
+
+	case 4:
+		ret = (src & dst) ? true : false;
+		break;
+
+	case 5:
+		ret = (!(src | dst)) ? true : false;
+		break;
+
+	default:
+		ret = false;
+		break;
+	}
+
+	return ret;
+}
+
+/*******************************************************
+ * Function:
+ *	Comfirm function.
+ * Input:
+ *	None.
+ * Output:
+ *	Return write length.
+ ********************************************************/
+static u8 comfirm(void)
+{
+	s32 i = 0;
+	u8 buf[32];
+
+	memcpy(buf, cmd_head.flag_addr, cmd_head.addr_len);
+
+	for (i = 0; i < cmd_head.times; i++) {
+		if (tool_i2c_read(buf, 1) <= 0) {
+			dev_err(&gt_client->dev, "Read flag data failed!");
+			return FAIL;
+		}
+		if (true == relation(buf[GTP_ADDR_LENGTH],
+		 cmd_head.flag_val, cmd_head.flag_relation)) {
+			dev_dbg(&gt_client->dev, "value at flag addr:0x%02x.",
+				buf[GTP_ADDR_LENGTH]);
+			dev_dbg(&gt_client->dev, "flag value:0x%02x.",
+				cmd_head.flag_val);
+			break;
+		}
+
+		msleep(cmd_head.circle);
+	}
+
+	if (i >= cmd_head.times) {
+		dev_err(&gt_client->dev, "Can't get the continue flag!");
+		return FAIL;
+	}
+
+	return SUCCESS;
+}
+
+ssize_t goodix_tool_write(struct file *filp,
+		const char __user *buff, size_t len, loff_t *off)
+{
+	s32 ret = 0;
+	struct goodix_ts_data *ts = i2c_get_clientdata(gt_client);
+
+	ret = copy_from_user(&cmd_head, buff, CMD_HEAD_LENGTH);
+	if (ret) {
+		dev_err(&gt_client->dev, "copy_from_user failed.");
+		return -EPERM;
+	}
+
+	dev_dbg(&gt_client->dev, "[Operation]wr: %02X", cmd_head.wr);
+	dev_dbg(&gt_client->dev,
+		"[Flag]flag: %02X,addr: %02X%02X,value: %02X,relation: %02X",
+		cmd_head.flag, cmd_head.flag_addr[0],
+		cmd_head.flag_addr[1], cmd_head.flag_val,
+		cmd_head.flag_relation);
+	dev_dbg(&gt_client->dev,
+		"[Retry]circle: %d,times: %d,retry: %d, delay: %d",
+		(s32)cmd_head.circle,
+		(s32)cmd_head.times, (s32)cmd_head.retry,
+		(s32)cmd_head.delay);
+	dev_dbg(&gt_client->dev,
+	"[Data]data len: %d,addr len: %d, addr: %02X%02X,buffer len:%d, data[0]: %02X",
+	(s32)cmd_head.data_len,
+	(s32)cmd_head.addr_len, cmd_head.addr[0],
+	cmd_head.addr[1], (s32)len, buff[CMD_HEAD_LENGTH]);
+
+	if (1 == cmd_head.wr) {
+		ret = copy_from_user(&cmd_head.data[GTP_ADDR_LENGTH],
+				&buff[CMD_HEAD_LENGTH], cmd_head.data_len);
+		if (ret) {
+			dev_err(&gt_client->dev, "copy_from_user failed.");
+			return -EPERM;
+		}
+		memcpy(&cmd_head.data[GTP_ADDR_LENGTH - cmd_head.addr_len],
+				cmd_head.addr, cmd_head.addr_len);
+
+		GTP_DEBUG_ARRAY(cmd_head.data, cmd_head.data_len +
+				cmd_head.addr_len);
+		GTP_DEBUG_ARRAY((u8 *)&buff[CMD_HEAD_LENGTH],
+				cmd_head.data_len);
+
+		if (1 == cmd_head.flag) {
+			if (FAIL == comfirm()) {
+				dev_err(&gt_client->dev, "[WRITE]Comfirm fail!");
+				return -EPERM;
+			}
+		} else if (2 == cmd_head.flag) {
+			/*Need interrupt!*/
+		}
+		if (tool_i2c_write(&cmd_head.data[GTP_ADDR_LENGTH -
+				cmd_head.addr_len],
+				cmd_head.data_len + cmd_head.addr_len) <= 0) {
+			dev_err(&gt_client->dev, "[WRITE]Write data failed!");
+			return -EPERM;
+		}
+
+		GTP_DEBUG_ARRAY(&cmd_head.data[GTP_ADDR_LENGTH
+				- cmd_head.addr_len],
+				cmd_head.data_len + cmd_head.addr_len);
+		if (cmd_head.delay)
+			msleep(cmd_head.delay);
+	} else if (3 == cmd_head.wr) {
+		ret = copy_from_user(&cmd_head.data[0],
+			 &buff[CMD_HEAD_LENGTH], cmd_head.data_len);
+		if (ret) {
+			dev_err(&gt_client->dev, "copy_from_user failed.");
+			return -EPERM;
+		}
+		memcpy(IC_TYPE, cmd_head.data, cmd_head.data_len);
+
+		register_i2c_func();
+	} else if (5 == cmd_head.wr) {
+		/*memcpy(IC_TYPE, cmd_head.data, cmd_head.data_len);*/
+	} else if (7 == cmd_head.wr) {/*disable irq!*/
+		gtp_work_control_enable(i2c_get_clientdata(gt_client), false);
+		
+		if (ts->pdata->esd_protect)
+			gtp_esd_off(ts);
+	} else if (9 == cmd_head.wr) {/*enable irq!*/
+		gtp_work_control_enable(i2c_get_clientdata(gt_client), true);
+		
+		if (ts->pdata->esd_protect)
+			gtp_esd_on(ts);
+	} else if (17 == cmd_head.wr) {
+		struct goodix_ts_data *ts = i2c_get_clientdata(gt_client);
+
+		ret = copy_from_user(&cmd_head.data[GTP_ADDR_LENGTH],
+				&buff[CMD_HEAD_LENGTH], cmd_head.data_len);
+		if (ret) {
+			dev_dbg(&gt_client->dev, "copy_from_user failed.");
+			return -EPERM;
+		}
+		if (cmd_head.data[GTP_ADDR_LENGTH]) {
+			dev_info(&gt_client->dev, "gtp enter rawdiff.");
+			set_bit(RAW_DATA_MODE, &ts->flags);
+		} else {
+			clear_bit(RAW_DATA_MODE, &ts->flags);
+			dev_info(&gt_client->dev, "gtp leave rawdiff.");
+		}
+	} else if (19 == cmd_head.wr) {
+		/* add new command: reset guitar */
+		gtp_reset_guitar(gt_client, 20);
+	}
+	else if (11 == cmd_head.wr) {/*Enter update mode!*/
+		if (FAIL == gup_enter_update_mode(gt_client))
+			return -EPERM;
+	} else if (13 == cmd_head.wr) {/*Leave update mode!*/
+		gup_leave_update_mode(gt_client);
+	} else if (15 == cmd_head.wr) {/*Update firmware!*/
+		show_len = 0;
+		total_len = 0;
+		memset(cmd_head.data, 0, cmd_head.data_len + 1);
+		memcpy(cmd_head.data, &buff[CMD_HEAD_LENGTH],
+		       cmd_head.data_len);
+
+		if (FAIL == gup_update_proc((void *)cmd_head.data))
+			return -EPERM;
+	}
+
+	return len;
+}
+
+/*******************************************************
+ * Function:
+ *	Goodix tool read function.
+ * Input:
+ *	standard proc read function param.
+ * Output:
+ *	Return read length.
+ ********************************************************/
+ssize_t goodix_tool_read(struct file *file, char __user *page,
+			 size_t size, loff_t *ppos)
+{
+	s32 ret = 0;
+
+	if (*ppos) {
+		/* ADB call again
+		 * dev_dbg(&gt_client->dev, "[HEAD]wr: %d", cmd_head.wr);
+		 * dev_dbg(&gt_client->dev,
+		 * "[PARAM]size: %d, *ppos: %d", size, (int)*ppos);
+		 * dev_dbg(&gt_client->dev,
+		 * "[TOOL_READ]ADB call again, return it.");
+		 */
+		*ppos = 0;
+		return 0;
+	}
+
+	if (cmd_head.wr % 2) {
+		return -EPERM;
+	} else if (!cmd_head.wr) {
+		u16 len = 0;
+		s16 data_len = 0;
+		u16 loc = 0;
+
+		if (1 == cmd_head.flag) {
+			if (FAIL == comfirm()) {
+				dev_err(&gt_client->dev, "[READ]Comfirm fail!");
+				return -EPERM;
+			}
+		} else if (2 == cmd_head.flag) {
+			/*Need interrupt!*/
+		}
+
+		memcpy(cmd_head.data, cmd_head.addr, cmd_head.addr_len);
+
+		dev_dbg(&gt_client->dev, "[CMD HEAD DATA] ADDR:0x%02x%02x.",
+				cmd_head.data[0], cmd_head.data[1]);
+		dev_dbg(&gt_client->dev, "[CMD HEAD ADDR] ADDR:0x%02x%02x.",
+				cmd_head.addr[0], cmd_head.addr[1]);
+
+		if (cmd_head.delay)
+			msleep(cmd_head.delay);
+
+		data_len = cmd_head.data_len;
+
+		while (data_len > 0) {
+			if (data_len > DATA_LENGTH)
+				len = DATA_LENGTH;
+			else
+				len = data_len;
+			data_len -= len;
+			if (tool_i2c_read(cmd_head.data, len) <= 0) {
+				dev_err(&gt_client->dev, "[READ]Read data failed!");
+				return -EPERM;
+			}
+			/*memcpy(&page[loc],
+			 *&cmd_head.data[GTP_ADDR_LENGTH], len);
+			 */
+			ret = simple_read_from_buffer(&page[loc], size,
+					ppos, &cmd_head.data[GTP_ADDR_LENGTH], len);
+			if (ret < 0)
+				return ret;
+			loc += len;
+
+			GTP_DEBUG_ARRAY(&cmd_head.data[GTP_ADDR_LENGTH], len);
+			GTP_DEBUG_ARRAY(page, len);
+		}
+		return cmd_head.data_len;
+	} else if (2 == cmd_head.wr) {
+		ret = simple_read_from_buffer(page, size,
+				ppos, IC_TYPE, sizeof(IC_TYPE));
+		return ret;
+	} else if (4 == cmd_head.wr) {
+		u8 progress_buf[4];
+
+		progress_buf[0] = show_len >> 8;
+		progress_buf[1] = show_len & 0xff;
+		progress_buf[2] = total_len >> 8;
+		progress_buf[3] = total_len & 0xff;
+
+		ret = simple_read_from_buffer(page, size,
+				ppos, progress_buf, 4);
+		return ret;
+	} else if (6 == cmd_head.wr) {
+		/*Read error code!*/
+	} else if (8 == cmd_head.wr) {	/*Read driver version*/
+		ret = simple_read_from_buffer(page, size, ppos,
+				GTP_DRIVER_VERSION,
+				strlen(GTP_DRIVER_VERSION));
+		return ret;
+	}
+
+	return -EPERM;
+}
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/gt9xx/gt9xx.c b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/gt9xx/gt9xx.c
new file mode 100644
index 0000000000000000000000000000000000000000..e5813b4b1d4bc7a4b1a0a2c89673e5fae922cd71
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/gt9xx/gt9xx.c
@@ -0,0 +1,2474 @@
+/*
+ * Goodix GT9xx touchscreen driver
+ *
+ * Copyright  (C)  2016 - 2017 Goodix. Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be a reference
+ * to you, when you are integrating the GOODiX's CTP IC into your system,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * Version: 2.8.0.1
+ * Release Date: 2017/10/26
+ */
+
+#include <linux/irq.h>
+#include <linux/platform_device.h>
+#include <linux/pinctrl/consumer.h>
+#include <linux/input/mt.h>
+#include "gt9xx.h"
+
+#define GOODIX_VTG_MIN_UV	2600000
+#define GOODIX_VTG_MAX_UV	3300000
+#define GOODIX_I2C_VTG_MIN_UV	1800000
+#define GOODIX_I2C_VTG_MAX_UV	1800000
+
+#define GOODIX_COORDS_ARR_SIZE	4
+#define PROP_NAME_SIZE		24
+#define I2C_MAX_TRANSFER_SIZE   255
+static const char *goodix_ts_name = "goodix-ts";
+static const char *goodix_input_phys = "input/ts";
+struct i2c_client *i2c_connect_client;
+static struct proc_dir_entry *gtp_config_proc;
+
+enum doze {
+	DOZE_DISABLED = 0,
+	DOZE_ENABLED = 1,
+	DOZE_WAKEUP = 2,
+};
+static enum doze doze_status = DOZE_DISABLED;
+
+static int gtp_i2c_test(struct i2c_client *client);
+static int gtp_enter_doze(struct goodix_ts_data *ts);
+
+static int gtp_unregister_powermanager(struct goodix_ts_data *ts);
+static int gtp_register_powermanager(struct goodix_ts_data *ts);
+
+static int gtp_esd_init(struct goodix_ts_data *ts);
+static void gtp_esd_check_func(struct work_struct *);
+static int gtp_init_ext_watchdog(struct i2c_client *client);
+
+/*
+ * return: 2 - ok, < 0 - i2c transfer error
+ */
+int gtp_i2c_read(struct i2c_client *client, u8 *buf, int len)
+{
+	unsigned int transfer_length = 0;
+	unsigned int pos = 0, address = (buf[0] << 8) + buf[1];
+	unsigned char get_buf[64], addr_buf[2];
+	int retry, r = 2;
+	struct i2c_msg msgs[] = {
+		{
+			.addr = client->addr,
+			.flags = !I2C_M_RD,
+			.buf = &addr_buf[0],
+			.len = GTP_ADDR_LENGTH,
+		}, {
+			.addr = client->addr,
+			.flags = I2C_M_RD,
+		}
+	};
+
+	len -= GTP_ADDR_LENGTH;
+	if (likely(len < sizeof(get_buf))) {
+		/* code optimize, use stack memory */
+		msgs[1].buf = &get_buf[0];
+	} else {
+		msgs[1].buf = kzalloc(len > I2C_MAX_TRANSFER_SIZE
+				? I2C_MAX_TRANSFER_SIZE : len, GFP_KERNEL);
+		if (!msgs[1].buf)
+			return -ENOMEM;
+	}
+
+	while (pos != len) {
+		if (unlikely(len - pos > I2C_MAX_TRANSFER_SIZE))
+			transfer_length = I2C_MAX_TRANSFER_SIZE;
+		else
+			transfer_length = len - pos;
+		msgs[0].buf[0] = (address >> 8) & 0xFF;
+		msgs[0].buf[1] = address & 0xFF;
+		msgs[1].len = transfer_length;
+		for (retry = 0; retry < RETRY_MAX_TIMES; retry++) {
+			if (likely(i2c_transfer(client->adapter, msgs, 2) == 2)) {
+				memcpy(&buf[2 + pos], msgs[1].buf, transfer_length);
+				pos += transfer_length;
+				address += transfer_length;
+				break;
+			}
+			dev_info(&client->dev, "I2c read retry[%d]:0x%x\n",
+				 retry + 1, address);
+			udelay(2000);
+		}
+		if (unlikely(retry == RETRY_MAX_TIMES)) {
+			dev_err(&client->dev,
+				"I2c read failed,dev:%02x,reg:%04x,size:%u\n",
+				client->addr, address, len);
+			r = -EAGAIN;
+			goto read_exit;
+		}
+	}
+read_exit:
+	if (len >= sizeof(get_buf))
+		kfree(msgs[1].buf);
+	return r;
+}
+
+/*******************************************************
+ * Function:
+ *	Write data to the i2c slave device.
+ * Input:
+ *	client: i2c device.
+ *	buf[0~1]: write start address.
+ *	buf[2~len-1]: data buffer
+ *	len: GTP_ADDR_LENGTH + write bytes count
+ * Output:
+ *	numbers of i2c_msgs to transfer:
+ *		1: succeed, otherwise: failed
+ *********************************************************/
+int gtp_i2c_write(struct i2c_client *client, u8 *buf, int len)
+
+{
+	unsigned int pos = 0, transfer_length = 0;
+	unsigned int address = (buf[0] << 8) + buf[1];
+	unsigned char put_buf[64];
+	int retry, r = 1;
+	struct i2c_msg msg = {
+			.addr = client->addr,
+			.flags = !I2C_M_RD,
+	};
+
+	if (likely(len < sizeof(put_buf))) {
+		/* code optimize,use stack memory*/
+		msg.buf = &put_buf[0];
+	} else {
+		msg.buf = kmalloc(len > I2C_MAX_TRANSFER_SIZE
+				  ? I2C_MAX_TRANSFER_SIZE : len, GFP_KERNEL);
+		if (!msg.buf)
+			return -ENOMEM;
+	}
+
+	len -= GTP_ADDR_LENGTH;
+	while (pos != len) {
+		if (unlikely(len - pos > I2C_MAX_TRANSFER_SIZE - GTP_ADDR_LENGTH))
+			transfer_length = I2C_MAX_TRANSFER_SIZE - GTP_ADDR_LENGTH;
+		else
+			transfer_length = len - pos;
+		msg.buf[0] = (unsigned char)((address >> 8) & 0xFF);
+		msg.buf[1] = (unsigned char)(address & 0xFF);
+		msg.len = transfer_length + 2;
+		memcpy(&msg.buf[2], &buf[2 + pos], transfer_length);
+		for (retry = 0; retry < RETRY_MAX_TIMES; retry++) {
+			if (likely(i2c_transfer(client->adapter, &msg, 1) == 1)) {
+				pos += transfer_length;
+				address += transfer_length;
+				break;
+			}
+			dev_info(&client->dev, "I2C write retry[%d]\n", retry + 1);
+			udelay(2000);
+		}
+		if (unlikely(retry == RETRY_MAX_TIMES)) {
+			dev_err(&client->dev,
+				"I2c write failed,dev:%02x,reg:%04x,size:%u\n",
+				client->addr, address, len);
+			r = -EAGAIN;
+			goto write_exit;
+		}
+	}
+write_exit:
+	if (len + GTP_ADDR_LENGTH >= sizeof(put_buf))
+		kfree(msg.buf);
+	return r;
+}
+
+/*******************************************************
+ * Function:
+ *	i2c read twice, compare the results
+ * Input:
+ *	client:	i2c device
+ *	addr: operate address
+ *	rxbuf: read data to store, if compare successful
+ *	len: bytes to read
+ * Output:
+ *	FAIL: read failed
+ *	SUCCESS: read successful
+ *********************************************************/
+s32 gtp_i2c_read_dbl_check(struct i2c_client *client,
+			   u16 addr, u8 *rxbuf, int len)
+{
+	u8 buf[16] = {0};
+	u8 confirm_buf[16] = {0};
+	u8 retry = 0;
+
+	if (len + 2 > sizeof(buf)) {
+		dev_warn(&client->dev,
+			 "%s, only support length less then %zu\n",
+			 __func__, sizeof(buf) - 2);
+		return FAIL;
+	}
+	while (retry++ < 3) {
+		memset(buf, 0xAA, 16);
+		buf[0] = (u8)(addr >> 8);
+		buf[1] = (u8)(addr & 0xFF);
+		gtp_i2c_read(client, buf, len + 2);
+
+		memset(confirm_buf, 0xAB, 16);
+		confirm_buf[0] = (u8)(addr >> 8);
+		confirm_buf[1] = (u8)(addr & 0xFF);
+		gtp_i2c_read(client, confirm_buf, len + 2);
+
+		if (!memcmp(buf, confirm_buf, len+2)) {
+			memcpy(rxbuf, confirm_buf+2, len);
+			return SUCCESS;
+		}
+	}
+	dev_err(&client->dev,
+		"I2C read 0x%04X, %d bytes, double check failed!\n",
+		addr, len);
+
+	return FAIL;
+}
+
+/*******************************************************
+ * Function:
+ *      Send config.
+ * Input:
+ *      client: i2c device.
+ * Output:
+ *      result of i2c write operation.
+ *              1: succeed, otherwise
+ *              0: Not executed
+ *		< 0: faild
+ *********************************************************/
+s32 gtp_send_cfg(struct i2c_client *client)
+{
+	s32 ret, i;
+	u8 check_sum;
+	s32 retry = 0;
+	struct goodix_ts_data *ts = i2c_get_clientdata(client);
+	struct goodix_config_data *cfg = &ts->pdata->config;
+
+	if (!cfg->length || !ts->pdata->driver_send_cfg) {
+		dev_info(&ts->client->dev,
+			 "No config data or error occurred in panel_init\n");
+		return 0;
+	}
+
+	check_sum = 0;
+	for (i = GTP_ADDR_LENGTH; i < cfg->length; i++)
+		check_sum += cfg->data[i];
+	cfg->data[cfg->length] = (~check_sum) + 1;
+
+	dev_info(&ts->client->dev, "Driver send config\n");
+	for (retry = 0; retry < RETRY_MAX_TIMES; retry++) {
+		ret = gtp_i2c_write(client, cfg->data,
+			GTP_CONFIG_MAX_LENGTH + GTP_ADDR_LENGTH);
+		if (ret > 0)
+			break;
+	}
+
+	return ret;
+}
+
+/*******************************************************
+ * Function:
+ *	Control enable or disable of work thrad.
+ * Input:
+ *      ts: goodix i2c_client private data
+ *	enbale: enbale var.
+ *********************************************************/
+void gtp_work_control_enable(struct goodix_ts_data *ts, bool enable)
+{
+	if (enable) {
+		set_bit(REPORT_THREAD_ENABLED, &ts->flags);
+		dev_info(&ts->client->dev, "Input report thread enabled!\n");
+	} else {
+		clear_bit(REPORT_THREAD_ENABLED, &ts->flags);
+		dev_info(&ts->client->dev, "Input report thread disabled!\n");
+	}
+}
+
+static int gtp_gesture_handler(struct goodix_ts_data *ts)
+{
+	u8 doze_buf[3] = {GTP_REG_DOZE_BUF >> 8, GTP_REG_DOZE_BUF & 0xFF};
+	int ret;
+
+	ret = gtp_i2c_read(ts->client, doze_buf, 3);
+	if (ret < 0) {
+		dev_err(&ts->client->dev, "Failed read doze buf");
+		return -EINVAL;
+	}
+
+	dev_dbg(&ts->client->dev, "0x814B = 0x%02X", doze_buf[2]);
+	if ((doze_buf[2] == 'a') || (doze_buf[2] == 'b') ||
+	    (doze_buf[2] == 'c') || (doze_buf[2] == 'd') ||
+	    (doze_buf[2] == 'e') || (doze_buf[2] == 'g') ||
+	    (doze_buf[2] == 'h') || (doze_buf[2] == 'm') ||
+	    (doze_buf[2] == 'o') || (doze_buf[2] == 'q') ||
+	    (doze_buf[2] == 's') || (doze_buf[2] == 'v') ||
+	    (doze_buf[2] == 'w') || (doze_buf[2] == 'y') ||
+	    (doze_buf[2] == 'z') || (doze_buf[2] == 0x5E) ||
+	    (doze_buf[2] == 0xAA) || (doze_buf[2] == 0xAB) ||
+	    (doze_buf[2] == 0xBA) || (doze_buf[2] == 0xBB) ||
+	    (doze_buf[2] == 0xCC)) {
+		doze_status = DOZE_WAKEUP;
+		input_report_key(ts->input_dev, KEY_POWER, 1);
+		input_sync(ts->input_dev);
+		input_report_key(ts->input_dev, KEY_POWER, 0);
+		input_sync(ts->input_dev);
+		/*  clear 0x814B */
+		doze_buf[2] = 0x00;
+		gtp_i2c_write(ts->client, doze_buf, 3);
+	} else {
+		/*  clear 0x814B */
+		doze_buf[2] = 0x00;
+		gtp_i2c_write(ts->client, doze_buf, 3);
+		gtp_enter_doze(ts);
+	}
+	return 0;
+}
+
+/*
+ * return touch state register value
+ * pen event id fixed with 9 and set tool type TOOL_PEN
+ *
+ */
+u8 gtp_get_points(struct goodix_ts_data *ts, struct goodix_point_t *points,
+		  u8 *key_value)
+{
+	int ret;
+	int i;
+	u8 *coor_data = NULL;
+	u8 finger_state = 0;
+	u8 touch_num = 0;
+	u8 end_cmd[3] = { GTP_READ_COOR_ADDR >> 8,
+			  GTP_READ_COOR_ADDR & 0xFF, 0 };
+	u8 point_data[2 + 1 + 8 * GTP_MAX_TOUCH_ID + 1] = {
+			GTP_READ_COOR_ADDR >> 8, GTP_READ_COOR_ADDR & 0xFF };
+
+	ret = gtp_i2c_read(ts->client, point_data, 12);
+	if (ret < 0) {
+		dev_err(&ts->client->dev,
+			"I2C transfer error. errno:%d\n ", ret);
+		return 0;
+	}
+
+	finger_state = point_data[GTP_ADDR_LENGTH];
+	if (finger_state == 0x00)
+		return 0;
+
+	touch_num = finger_state & 0x0f;
+	if ((finger_state & MASK_BIT_8) == 0 ||
+	    touch_num > ts->pdata->max_touch_id) {
+		dev_err(&ts->client->dev,
+			"Invalid touch state: 0x%x", finger_state);
+		finger_state = 0;
+		goto exit_get_point;
+	}
+
+	if (touch_num > 1) {
+		u8 buf[8 * GTP_MAX_TOUCH_ID] = {
+					  (GTP_READ_COOR_ADDR + 10) >> 8,
+					  (GTP_READ_COOR_ADDR + 10) & 0xff };
+
+		ret = gtp_i2c_read(ts->client, buf, 2 + 8 * (touch_num - 1));
+		if (ret < 0) {
+			dev_err(&ts->client->dev, "I2C error. %d\n", ret);
+			finger_state = 0;
+			goto exit_get_point;
+		}
+		memcpy(&point_data[12], &buf[2], 8 * (touch_num - 1));
+	}
+
+	/* panel have touch key */
+	//if (ts->pdata->key_nums) {
+		*key_value = point_data[3 + 8 * touch_num];
+
+		/* 0x20_UPKEY 0X10_DOWNKEY 0X40_ALLKEYDOWN */
+	//	*key_value &= 0x0F;
+	//} else {
+	//	*key_value = 0;
+	//}
+
+	memset(points, 0, sizeof(*points) * GTP_MAX_TOUCH_ID);
+	for (i = 0; i < touch_num; i++) {
+		coor_data = &point_data[i * 8 + 3];
+		points[i].id = coor_data[0];
+		points[i].x = coor_data[1] | (coor_data[2] << 8);
+		points[i].y = coor_data[3] | (coor_data[4] << 8);
+		points[i].w = coor_data[5] | (coor_data[6] << 8);
+		/* if pen hover points[].p must set to zero */
+		points[i].p = coor_data[5] | (coor_data[6] << 8);
+
+		if (ts->pdata->swap_x2y)
+			GTP_SWAP(points[i].x, points[i].y);
+
+		/* TODO: Following code only for debug use */
+		points[i].y = ts->pdata->abs_size_y - points[i].y;
+		//dev_info(&ts->client->dev, "[%d][%d %d %d]\n",
+		//	 points[i].id, points[i].x, points[i].y, points[i].p);
+
+		/* pen device coordinate */
+		if (points[i].id & 0x80) {
+			points[i].tool_type = GTP_TOOL_PEN;
+			points[i].id = 10;
+			if (ts->pdata->pen_suppress_finger) {
+				points[0] = points[i];
+				memset(++points, 0, sizeof(*points) * (GTP_MAX_TOUCH_ID - 1));
+				finger_state &= 0xf0;
+				finger_state |= 0x01;
+				break;
+			}
+		} else {
+			points[i].tool_type = GTP_TOOL_FINGER;
+		}
+	}
+
+exit_get_point:
+	if (!test_bit(RAW_DATA_MODE, &ts->flags)) {
+		ret = gtp_i2c_write(ts->client, end_cmd, 3);
+		if (ret < 0)
+			dev_info(&ts->client->dev, "I2C write end_cmd error!");
+	}
+	return finger_state;
+}
+
+void gtp_type_a_report(struct goodix_ts_data *ts, u8 touch_num,
+			struct goodix_point_t *points)
+{
+	int i;
+	u16 cur_touch = 0;
+	static u16 pre_touch;
+	static u8 pre_pen_id;
+
+	if (touch_num)
+		input_report_key(ts->input_dev, BTN_TOUCH, 1);      // 开始一次上报   pengjie 0720
+
+	for (i = 0; i < ts->pdata->max_touch_id; i++) {
+		if (touch_num && i == points->id) {
+			input_report_abs(ts->input_dev, ABS_MT_TRACKING_ID, points->id);
+
+			if (points->tool_type == GTP_TOOL_PEN) {
+				input_report_key(ts->input_dev, BTN_TOOL_PEN, true);
+				pre_pen_id = points->id;
+			} else {
+				input_report_key(ts->input_dev, BTN_TOOL_FINGER, true);
+			}
+            // 加入绝对坐标上报语句    pengjie 0720
+            input_report_abs(ts->input_dev, ABS_X,
+					 points->x);
+			input_report_abs(ts->input_dev, ABS_Y,
+					 points->y);
+
+			input_report_abs(ts->input_dev, ABS_MT_POSITION_X,
+					 points->x);
+			input_report_abs(ts->input_dev, ABS_MT_POSITION_Y,
+					 points->y);
+			input_report_abs(ts->input_dev, ABS_MT_TOUCH_MAJOR,
+					 points->w);
+			input_report_abs(ts->input_dev, ABS_MT_PRESSURE,
+					 points->p);
+			input_mt_sync(ts->input_dev);       // 结束一次上报   pengjie 0720
+
+			cur_touch |= 0x01 << points->id;
+			points++;
+		} else if (pre_touch & 0x01 << i) {
+			if (pre_pen_id == i) {
+				input_report_key(ts->input_dev, BTN_TOOL_PEN, false);
+				/* valid id will < 10, so id to 0xff to indicate a invalid state */
+				pre_pen_id = 0xff;
+			} else {
+				input_report_key(ts->input_dev, BTN_TOOL_FINGER, false);
+			}
+		}
+	}
+
+	pre_touch = cur_touch;
+	if (!pre_touch) {
+		input_mt_sync(ts->input_dev);
+		input_report_key(ts->input_dev, BTN_TOUCH, 0);
+	}
+	input_sync(ts->input_dev);
+}
+
+void gtp_mt_slot_report(struct goodix_ts_data *ts, u8 touch_num,
+			struct goodix_point_t *points)
+{
+	int i;
+	u16 cur_touch = 0;
+	static u16 pre_touch;
+	static u8 pre_pen_id;
+
+	for (i = 0; i < ts->pdata->max_touch_id; i++) {
+		if (touch_num && i == points->id) {
+			input_mt_slot(ts->input_dev, points->id);
+
+			if (points->tool_type == GTP_TOOL_PEN) {
+				input_mt_report_slot_state(ts->input_dev,
+							   MT_TOOL_PEN, true);
+				pre_pen_id = points->id;
+			} else {
+				input_mt_report_slot_state(ts->input_dev,
+							   MT_TOOL_FINGER, true);
+			}
+            // 加入绝对坐标上报语句    pengjie 0720
+			input_report_abs(ts->input_dev, ABS_X,
+					 points->x);
+			input_report_abs(ts->input_dev, ABS_Y,
+					 points->y);            
+
+			input_report_abs(ts->input_dev, ABS_MT_POSITION_X,
+					 points->x);
+			input_report_abs(ts->input_dev, ABS_MT_POSITION_Y,
+					 points->y);
+			input_report_abs(ts->input_dev, ABS_MT_TOUCH_MAJOR,
+					 points->w);
+			input_report_abs(ts->input_dev, ABS_MT_PRESSURE,
+					 points->p);
+
+			cur_touch |= 0x01 << points->id;
+			points++;
+		} else if (pre_touch & 0x01 << i) {
+			input_mt_slot(ts->input_dev, i);
+			if (pre_pen_id == i) {
+				input_mt_report_slot_state(ts->input_dev,
+							   MT_TOOL_PEN, false);
+				/* valid id will < 10, so id to 0xff to indicate a invalid state */
+				pre_pen_id = 0xff;
+			} else
+				input_mt_report_slot_state(ts->input_dev,
+							   MT_TOOL_FINGER, false);
+		}
+	}
+
+	pre_touch = cur_touch;
+	/* report BTN_TOUCH event */
+	input_mt_sync_frame(ts->input_dev);
+	input_sync(ts->input_dev);
+}
+
+/*******************************************************
+ * Function:
+ *	Goodix touchscreen sensor report function
+ * Input:
+ *	ts: goodix tp private data
+ * Output:
+ *	None.
+ *********************************************************/
+static void gtp_work_func(struct goodix_ts_data *ts)
+{
+	u8 point_state = 0;
+	u8 key_value = 0;
+	s32 i = 0;
+	s32 ret = -1;
+	static u8 pre_key;
+	struct goodix_point_t points[GTP_MAX_TOUCH_ID];
+
+	if (test_bit(PANEL_RESETTING, &ts->flags))
+		return;
+	if (!test_bit(REPORT_THREAD_ENABLED, &ts->flags))
+		return;
+
+	/* gesture event */
+	if (ts->pdata->slide_wakeup && test_bit(DOZE_MODE, &ts->flags)) {
+		ret =  gtp_gesture_handler(ts);
+		if (ret)
+			dev_err(&ts->client->dev,
+				"Failed handler gesture event %d\n", ret);
+		return;
+	}
+
+	point_state = gtp_get_points(ts, points, &key_value);
+	if (!point_state) {
+		dev_dbg(&ts->client->dev, "Invalid finger points\n");
+		return;
+	}
+
+	/* touch key event */
+	if (key_value || pre_key) {
+		switch (key_value) {
+		case 0x40:
+			input_report_key(ts->input_dev, BTN_STYLUS, 1);
+			input_report_key(ts->input_dev, BTN_STYLUS2, 1);
+			break;
+		case 0x10:
+			input_report_key(ts->input_dev, BTN_STYLUS, 1);
+			input_report_key(ts->input_dev, BTN_STYLUS2, 0);
+			dev_info(&ts->client->dev, "stylus1 down\n");
+			break;
+		case 0x20:
+			input_report_key(ts->input_dev, BTN_STYLUS, 0);
+			input_report_key(ts->input_dev, BTN_STYLUS2, 1);
+			break;
+		default:
+			input_report_key(ts->input_dev, BTN_STYLUS, 0);
+			input_report_key(ts->input_dev, BTN_STYLUS2, 0);
+			dev_info(&ts->client->dev, "stylus1 up\n");
+			break;
+		}
+
+		for (i = 0; i < ts->pdata->key_nums; i++) {
+			if ((pre_key | key_value) & (0x01 << i))
+				input_report_key(ts->input_dev,
+						 ts->pdata->key_map[i],
+						 key_value & (0x01<<i));
+		}
+		/* key event will suppress finger event */
+		input_sync(ts->input_dev);
+		pre_key = key_value;
+		//return;
+	}
+
+	if (!ts->pdata->type_a_report)
+		gtp_mt_slot_report(ts, point_state & 0x0f, points);
+	else
+		gtp_type_a_report(ts, point_state & 0x0f, points);
+}
+
+/*******************************************************
+ * Function:
+ *	Timer interrupt service routine for polling mode.
+ * Input:
+ *	timer: timer struct pointer
+ * Output:
+ *	Timer work mode.
+ * HRTIMER_NORESTART:
+ *	no restart mode
+ *********************************************************/
+static enum hrtimer_restart gtp_timer_handler(struct hrtimer *timer)
+{
+	struct goodix_ts_data *ts =
+		container_of(timer, struct goodix_ts_data, timer);
+
+	gtp_work_func(ts);
+	hrtimer_start(&ts->timer, ktime_set(0, (GTP_POLL_TIME + 6) * 1000000),
+		      HRTIMER_MODE_REL);
+
+	return HRTIMER_NORESTART;
+}
+
+static irqreturn_t gtp_irq_handler(int irq, void *dev_id)
+{
+	struct goodix_ts_data *ts = dev_id;
+
+	gtp_work_func(ts);
+	return IRQ_HANDLED;
+}
+
+void gtp_int_output(struct goodix_ts_data *ts, int level)
+{
+	if (!ts->pdata->int_sync)
+		return;
+
+	if (level == 0) {
+		if (ts->pinctrl.pinctrl)
+			pinctrl_select_state(ts->pinctrl.pinctrl,
+					     ts->pinctrl.int_out_low);
+		else if (gpio_is_valid(ts->pdata->irq_gpio))
+			gpio_direction_output(ts->pdata->irq_gpio, 0);
+		else
+			dev_err(&ts->client->dev,
+				"Failed set int pin output low\n");
+	} else {
+		if (ts->pinctrl.pinctrl)
+			pinctrl_select_state(ts->pinctrl.pinctrl,
+					     ts->pinctrl.int_out_high);
+		else if (gpio_is_valid(ts->pdata->irq_gpio))
+			gpio_direction_output(ts->pdata->irq_gpio, 1);
+		else
+			dev_err(&ts->client->dev,
+				"Failed set int pin output high\n");
+	}
+}
+
+void gtp_int_sync(struct goodix_ts_data *ts, s32 ms)
+{
+	if (!ts->pdata->int_sync)
+		return;
+
+	if (ts->pinctrl.pinctrl) {
+		gtp_int_output(ts, 0);
+		msleep(ms);
+		pinctrl_select_state(ts->pinctrl.pinctrl,
+				     ts->pinctrl.int_input);
+	} else if (gpio_is_valid(ts->pdata->irq_gpio)) {
+		gpio_direction_output(ts->pdata->irq_gpio, 0);
+		msleep(ms);
+		gpio_direction_input(ts->pdata->irq_gpio);
+	} else {
+		dev_err(&ts->client->dev, "Failed sync int pin\n");
+	}
+}
+
+/*******************************************************
+ * Function:
+ *	Reset chip. Control the reset pin and int-pin(if
+ *	defined),
+ * Input:
+ *	client:	i2c device.
+ *	ms: reset time in millisecond
+ * Output:
+ *	None.
+ *******************************************************/
+void gtp_reset_guitar(struct i2c_client *client, s32 ms)
+{
+	struct goodix_ts_data *ts = i2c_get_clientdata(client);
+
+	dev_info(&client->dev, "Guitar reset");
+	set_bit(PANEL_RESETTING, &ts->flags);
+	if (!gpio_is_valid(ts->pdata->rst_gpio)) {
+		dev_warn(&client->dev, "reset failed no valid reset gpio");
+		return;
+	}
+	/*把gt9157的设备地址被配置为0xBA：
+	1.RST、INT低电平
+	2.至少延时100us
+	3.RST切换为高电平
+	4.至少延时5ms
+	5.INT切换为浮空输入 */
+
+	//拉低RST引脚
+	gpio_direction_output(ts->pdata->rst_gpio, 0);
+	gpio_direction_output(ts->pdata->irq_gpio, 0);
+	//usleep_range(ms*1000, ms*1000 + 100);	/*  T2: > 10ms */
+	mdelay(5);
+	gpio_direction_output(ts->pdata->irq_gpio, 1);
+	//拉高/拉低int引脚，取决于通讯地址
+	//gtp_int_output(ts, client->addr == 0x14);
+	mdelay(5);
+	//usleep_range(2000, 3000);		/*  T3: > 100us (2ms)*/
+	gpio_direction_output(ts->pdata->rst_gpio, 1);
+	
+	usleep_range(6000, 7000);		/*  T4: > 5ms */
+	gpio_direction_input(ts->pdata->irq_gpio);
+
+//	gtp_int_sync(ts, 50);
+	if (ts->pdata->esd_protect)
+		gtp_init_ext_watchdog(client);
+
+	clear_bit(PANEL_RESETTING, &ts->flags);
+
+	usleep_range(500000, 1000000);		/*  T5: > 50ms */   // add for pengjie 0716   复位之后，需要一段时间来等待之后，再次读取信息
+}
+
+/*******************************************************
+ * Function:
+ *	Enter doze mode for sliding wakeup.
+ * Input:
+ *	ts: goodix tp private data
+ * Output:
+ *	1: succeed, otherwise failed
+ *******************************************************/
+static int gtp_enter_doze(struct goodix_ts_data *ts)
+{
+	int ret = -1;
+	int retry = 0;
+	u8 i2c_control_buf[3] = { (u8)(GTP_REG_SLEEP >> 8),
+				  (u8)GTP_REG_SLEEP, 8 };
+
+	if (test_and_set_bit(DOZE_MODE, &ts->flags)) {
+		dev_info(&ts->client->dev, "Already in doze mode\n");
+		return SUCCESS;
+	}
+
+	dev_dbg(&ts->client->dev, "Entering gesture mode.");
+	while (retry++ < 5) {
+		i2c_control_buf[0] = (u8)(GTP_REG_COMMAND_CHECK >> 8);
+		i2c_control_buf[1] = (u8)GTP_REG_COMMAND_CHECK;
+		ret = gtp_i2c_write(ts->client, i2c_control_buf, 3);
+		if (ret < 0) {
+			dev_dbg(&ts->client->dev,
+				"failed to set doze flag into 0x8046, %d\n",
+				retry);
+			continue;
+		}
+		i2c_control_buf[0] = (u8)(GTP_REG_SLEEP >> 8);
+		i2c_control_buf[1] = (u8)GTP_REG_SLEEP;
+		ret = gtp_i2c_write(ts->client, i2c_control_buf, 3);
+		if (ret > 0) {
+			dev_info(&ts->client->dev, "Gesture mode enabled\n");
+			return ret;
+		}
+		usleep_range(10000, 11000);
+	}
+
+	dev_err(&ts->client->dev, "Failed enter doze mode\n");
+	clear_bit(DOZE_MODE, &ts->flags);
+	return ret;
+}
+
+static s8 gtp_enter_sleep(struct goodix_ts_data *ts)
+{
+	s8 ret = -1;
+	s8 retry = 0;
+	u8 i2c_control_buf[3] = { (u8)(GTP_REG_SLEEP >> 8),
+				  (u8)GTP_REG_SLEEP, 5 };
+
+	gtp_int_output(ts, 0);
+	usleep_range(5000, 6000);
+
+	while (retry++ < 5) {
+		ret = gtp_i2c_write(ts->client, i2c_control_buf, 3);
+		if (ret > 0) {
+			dev_info(&ts->client->dev, "Enter sleep mode\n");
+
+			return ret;
+		}
+		usleep_range(10000, 11000);
+	}
+	dev_err(&ts->client->dev, "Failed send sleep cmd\n");
+
+	return ret;
+}
+
+static int gtp_wakeup_sleep(struct goodix_ts_data *ts)
+{
+	u8 retry = 0;
+	int ret = -1;
+
+	while (retry++ < 10) {
+		gtp_int_output(ts, 1);
+		usleep_range(5000, 6000);
+
+		ret = gtp_i2c_test(ts->client);
+		if (!ret) {
+			dev_info(&ts->client->dev, "Success wakeup sleep\n");
+
+			gtp_int_sync(ts, 25);
+			if (ts->pdata->esd_protect)
+				gtp_init_ext_watchdog(ts->client);
+
+			return ret;
+		}
+		gtp_reset_guitar(ts->client, 20);
+	}
+
+	dev_err(&ts->client->dev, "Failed wakeup from sleep mode\n");
+	return -EINVAL;
+}
+
+static int gtp_find_vaild_cfg_data(struct goodix_ts_data *ts)
+{
+	int ret = -1;
+	u8 sensor_id = 0;
+	struct goodix_config_data *cfg = &ts->pdata->config;
+
+	/* if defined CONFIG_OF, parse config data from dtsi
+	 * else parse config data form header file.
+	 */
+	cfg->length = 0;
+
+#ifndef	CONFIG_OF
+	u8 cfg_info_group0[] = CTP_CFG_GROUP0;
+	u8 cfg_info_group1[] = CTP_CFG_GROUP1;
+	u8 cfg_info_group2[] = CTP_CFG_GROUP2;
+	u8 cfg_info_group3[] = CTP_CFG_GROUP3;
+	u8 cfg_info_group4[] = CTP_CFG_GROUP4;
+	u8 cfg_info_group5[] = CTP_CFG_GROUP5;
+
+	u8 *send_cfg_buf[] = { cfg_info_group0, cfg_info_group1,
+			       cfg_info_group2, cfg_info_group3,
+			       cfg_info_group4, cfg_info_group5 };
+	u8 cfg_info_len[] = { CFG_GROUP_LEN(cfg_info_group0),
+			      CFG_GROUP_LEN(cfg_info_group1),
+			      CFG_GROUP_LEN(cfg_info_group2),
+			      CFG_GROUP_LEN(cfg_info_group3),
+			      CFG_GROUP_LEN(cfg_info_group4),
+			      CFG_GROUP_LEN(cfg_info_group5)};
+
+	dev_dbg(&ts->client->dev,
+		"Config Groups\' Lengths: %d, %d, %d, %d, %d, %d",
+		cfg_info_len[0], cfg_info_len[1], cfg_info_len[2],
+		cfg_info_len[3], cfg_info_len[4], cfg_info_len[5]);
+#endif
+
+	/* read sensor id */
+	ret = gtp_i2c_read_dbl_check(ts->client, GTP_REG_SENSOR_ID,
+				     &sensor_id, 1);
+	if (SUCCESS != ret || sensor_id >= 0x06) {
+		dev_err(&ts->client->dev,
+			"Failed get valid sensor_id(0x%02X), No Config Sent\n",
+			sensor_id);
+		return -EINVAL;
+	}
+
+	dev_info(&ts->client->dev, "Sensor_ID: %d", sensor_id);
+	/* parse config data */
+#ifdef CONFIG_OF
+	dev_dbg(&ts->client->dev, "Get config data from device tree\n");
+	ret = gtp_parse_dt_cfg(&ts->client->dev,
+			       &cfg->data[GTP_ADDR_LENGTH],
+			       &cfg->length, sensor_id);
+	if (ret < 0) {
+		dev_err(&ts->client->dev,
+			"Failed to parse config data form device tree\n");
+		cfg->length = 0;
+		return -EPERM;
+	}
+#else
+	dev_dbg(&ts->client->dev, "Get config data from header file\n");
+	if ((!cfg_info_len[1]) && (!cfg_info_len[2]) &&
+	    (!cfg_info_len[3]) && (!cfg_info_len[4]) &&
+	    (!cfg_info_len[5])) {
+		sensor_id = 0;
+	}
+	cfg->length = cfg_info_len[sensor_id];
+	memset(&cfg->data[GTP_ADDR_LENGTH], 0, GTP_CONFIG_MAX_LENGTH);
+	memcpy(&cfg->data[GTP_ADDR_LENGTH], send_cfg_buf[sensor_id],
+			cfg->length);
+#endif
+
+	if (cfg->length < GTP_CONFIG_MIN_LENGTH) {
+		dev_err(&ts->client->dev,
+			"Failed get valid config data with sensor id %d\n",
+			sensor_id);
+		cfg->length = 0;
+		return -EPERM;
+	}
+
+	dev_info(&ts->client->dev, "Config group%d used,length: %d\n",
+		 sensor_id, cfg->length);
+
+	return 0;
+}
+
+/*******************************************************
+ * Function:
+ *	Get valid config data from dts or .h file.
+ *	Read firmware version info and judge firmware
+ *	working state
+ * Input:
+ *	ts: goodix private data
+ * Output:
+ *	Executive outcomes.
+ *		0: succeed, otherwise: failed
+ *******************************************************/
+static s32 gtp_init_panel(struct goodix_ts_data *ts)
+{
+	s32 ret = -1;
+	u8 opr_buf[16] = {0};
+	u8 drv_cfg_version = 0;
+	u8 flash_cfg_version = 0;
+	struct goodix_config_data *cfg = &ts->pdata->config;
+
+	if (!ts->pdata->driver_send_cfg) {
+		dev_info(&ts->client->dev, "Driver set not send config\n");
+		cfg->length = GTP_CONFIG_MAX_LENGTH;
+		ret = gtp_i2c_read(ts->client,
+				   cfg->data, cfg->length +
+				   GTP_ADDR_LENGTH);
+		if (ret < 0)
+			dev_err(&ts->client->dev, "Read origin Config Failed\n");
+
+		return 0;
+	}
+
+	gtp_find_vaild_cfg_data(ts);
+
+	/* check firmware */
+	ret = gtp_i2c_read_dbl_check(ts->client, 0x41E4, opr_buf, 1);
+	if (SUCCESS == ret) {
+		if (opr_buf[0] != 0xBE) {
+			set_bit(FW_ERROR, &ts->flags);
+			dev_err(&ts->client->dev,
+				"Firmware error, no config sent!\n");
+			return -EINVAL;
+		}
+	}
+
+	ret = gtp_i2c_read_dbl_check(ts->client, GTP_REG_CONFIG_DATA,
+				     &opr_buf[0], 1);
+	if (ret == SUCCESS) {
+		dev_dbg(&ts->client->dev,
+			"Config Version: %d; IC Config Version: %d\n",
+			cfg->data[GTP_ADDR_LENGTH], opr_buf[0]);
+		flash_cfg_version = opr_buf[0];
+		drv_cfg_version = cfg->data[GTP_ADDR_LENGTH];
+
+		if (flash_cfg_version < 90 &&
+		    flash_cfg_version > drv_cfg_version)
+			cfg->data[GTP_ADDR_LENGTH] = 0x00;
+	} else {
+		dev_err(&ts->client->dev,
+			"Failed to get ic config version!No config sent\n");
+		return -EPERM;
+	}
+
+	ret = gtp_send_cfg(ts->client);
+	if (ret < 0)
+		dev_err(&ts->client->dev, "Send config error\n");
+	else
+		usleep_range(10000, 11000); /* 10 ms */
+
+	/* restore config version */
+	cfg->data[GTP_ADDR_LENGTH] = drv_cfg_version;
+
+	return 0;
+}
+
+static ssize_t gtp_config_read_proc(struct file *file, char __user *page,
+				    size_t size, loff_t *ppos)
+{
+	int i;
+	char *ptr = page;
+	char temp_data[GTP_CONFIG_MAX_LENGTH + 2] = {
+					(u8)(GTP_REG_CONFIG_DATA >> 8),
+					(u8)GTP_REG_CONFIG_DATA};
+	struct goodix_ts_data *ts = i2c_get_clientdata(i2c_connect_client);
+	struct goodix_config_data *cfg = &ts->pdata->config;
+
+	if (*ppos)
+		return 0;
+
+	ptr += snprintf(ptr, 50, "==== GT9XX config init value====\n");
+
+	for (i = 0 ; i < GTP_CONFIG_MAX_LENGTH ; i++) {
+		ptr += snprintf(ptr, 10, "0x%02X ", cfg->data[i + 2]);
+
+		if (i % 8 == 7)
+			ptr += snprintf(ptr, 10, "\n");
+	}
+
+	ptr += snprintf(ptr, 10, "\n");
+
+	ptr += snprintf(ptr, 50, "==== GT9XX config real value====\n");
+	gtp_i2c_read(i2c_connect_client, temp_data, GTP_CONFIG_MAX_LENGTH + 2);
+	for (i = 0 ; i < GTP_CONFIG_MAX_LENGTH ; i++) {
+		ptr += snprintf(ptr, 10, "0x%02X ", temp_data[i+2]);
+
+		if (i % 8 == 7)
+			ptr += snprintf(ptr, 10, "\n");
+	}
+	*ppos += ptr - page;
+
+	return ptr - page;
+}
+
+static ssize_t gtp_config_write_proc(struct file *filp,
+				     const char __user *buffer,
+				     size_t count, loff_t *off)
+{
+	s32 ret = 0;
+	struct goodix_ts_data *ts = i2c_get_clientdata(i2c_connect_client);
+	struct goodix_config_data *cfg = &ts->pdata->config;
+
+	dev_dbg(&ts->client->dev, "write count %zu\n", count);
+
+	if (count > GTP_CONFIG_MAX_LENGTH) {
+		dev_err(&ts->client->dev, "size not match [%d:%zu]\n",
+				GTP_CONFIG_MAX_LENGTH, count);
+		return -EFAULT;
+	}
+
+	if (copy_from_user(&cfg->data[2], buffer, count)) {
+		dev_err(&ts->client->dev, "Failed copy from user\n");
+		return -EFAULT;
+	}
+
+	ret = gtp_send_cfg(i2c_connect_client);
+
+	if (ret < 0)
+		dev_err(&ts->client->dev, "Failed send config\n");
+
+	return count;
+}
+
+static const struct file_operations config_proc_ops = {
+	.owner = THIS_MODULE,
+	.read = gtp_config_read_proc,
+	.write = gtp_config_write_proc,
+};
+
+static ssize_t gtp_workmode_show(struct device *dev,
+		struct device_attribute *attr, char *buf)
+{
+	struct goodix_ts_data *data = dev_get_drvdata(dev);
+
+	return scnprintf(buf, PAGE_SIZE, "%s\n",
+			 test_bit(SLEEP_MODE, &data->flags)
+			 ? "in_sleep_mode" : "in_work_mode");
+}
+static DEVICE_ATTR(workmode, S_IRUGO, gtp_workmode_show, NULL);
+
+#define FW_NAME_MAX_LEN	80
+static ssize_t gtp_dofwupdate_store(struct device *dev,
+				    struct device_attribute *attr,
+				    const char *buf, size_t count)
+{
+	struct goodix_ts_data *ts = dev_get_drvdata(dev);
+	char update_file_name[FW_NAME_MAX_LEN];
+	int retval;
+
+	if (count > FW_NAME_MAX_LEN) {
+		dev_info(&ts->client->dev, "FW filename is too long\n");
+		retval = -EINVAL;
+		goto exit;
+	}
+
+	strlcpy(update_file_name, buf, count);
+
+	ts->force_update = true;
+	retval = gup_update_proc(update_file_name);
+	if (retval == FAIL)
+		dev_err(&ts->client->dev, "Fail to update GTP firmware.\n");
+	else
+		dev_info(&ts->client->dev, "Update success\n");
+
+	return count;
+
+exit:
+	return retval;
+}
+static DEVICE_ATTR(dofwupdate, (S_IWUSR | S_IWGRP), NULL, gtp_dofwupdate_store);
+
+static ssize_t gtp_productinfo_show(struct device *dev,
+		struct device_attribute *attr, char *buf)
+{
+	struct goodix_ts_data *data = dev_get_drvdata(dev);
+	struct goodix_fw_info *fw_info = &data->fw_info;
+
+	return scnprintf(buf, PAGE_SIZE, "GT%s_%x_%d\n",
+			fw_info->pid, fw_info->version, fw_info->sensor_id);
+}
+static DEVICE_ATTR(productinfo, S_IRUGO, gtp_productinfo_show, NULL);
+
+static ssize_t gtp_drv_irq_store(struct device *dev,
+				 struct device_attribute *attr,
+				 const char *buf, size_t count)
+{
+	unsigned long value = 0;
+	int err = 0;
+	struct goodix_ts_data *data = dev_get_drvdata(dev);
+
+	err = kstrtoul(buf, 10, &value);
+	if (err < 0) {
+		dev_err(dev, "Failed to convert value\n");
+		return -EINVAL;
+	}
+
+	switch (value) {
+	case 0:
+		/* Disable irq */
+		gtp_work_control_enable(data, false);
+		break;
+	case 1:
+		/* Enable irq */
+		gtp_work_control_enable(data, true);
+		break;
+	default:
+		dev_err(dev, "Invalid value\n");
+		return -EINVAL;
+	}
+
+	return count;
+}
+
+static ssize_t gtp_drv_irq_show(struct device *dev,
+		struct device_attribute *attr, char *buf)
+{
+	struct goodix_ts_data *data = dev_get_drvdata(dev);
+
+	return scnprintf(buf, PAGE_SIZE, "%s\n",
+			 test_bit(REPORT_THREAD_ENABLED, &data->flags)
+			 ? "enabled" : "disabled");
+}
+static DEVICE_ATTR(drv_irq, (S_IRUGO | S_IWUSR | S_IWGRP),
+		   gtp_drv_irq_show, gtp_drv_irq_store);
+
+static ssize_t gtp_reset_store(struct device *dev,
+		struct device_attribute *attr, const char *buf, size_t count)
+{
+	struct goodix_ts_data *data = dev_get_drvdata(dev);
+
+	if ('1' != buf[0]) {
+		dev_err(dev, "Invalid argument for reset\n");
+		return -EINVAL;
+	}
+
+	gtp_reset_guitar(data->client, 20);
+
+	return count;
+}
+static DEVICE_ATTR(reset, (S_IWUSR | S_IWGRP), NULL, gtp_reset_store);
+
+static struct attribute *gtp_attrs[] = {
+	&dev_attr_workmode.attr,
+	&dev_attr_productinfo.attr,
+	&dev_attr_dofwupdate.attr,
+	&dev_attr_drv_irq.attr,
+	&dev_attr_reset.attr,
+	NULL
+};
+
+static const struct attribute_group gtp_attr_group = {
+	.attrs = gtp_attrs,
+};
+
+static int gtp_create_file(struct goodix_ts_data *ts)
+{
+	int ret;
+	struct i2c_client *client = ts->client;
+
+	/*  Create proc file system */
+	gtp_config_proc = NULL;
+	gtp_config_proc = proc_create(GT91XX_CONFIG_PROC_FILE, 0664,
+				      NULL, &config_proc_ops);
+	if (gtp_config_proc == NULL)
+		dev_err(&client->dev, "create_proc_entry %s failed\n",
+			GT91XX_CONFIG_PROC_FILE);
+	else
+		dev_info(&client->dev, "create proc entry %s success\n",
+			 GT91XX_CONFIG_PROC_FILE);
+
+	ret = sysfs_create_group(&client->dev.kobj, &gtp_attr_group);
+	if (ret) {
+		dev_err(&client->dev, "Failure create sysfs group %d\n", ret);
+		/*TODO: debug change */
+		goto exit_free_config_proc;
+	}
+	return 0;
+
+exit_free_config_proc:
+	remove_proc_entry(GT91XX_CONFIG_PROC_FILE, gtp_config_proc);
+	return -ENODEV;
+}
+
+s32 gtp_get_fw_info(struct i2c_client *client, struct goodix_fw_info *fw_info)
+{
+	s32 ret = -1;
+	u8 buf[8] = {GTP_REG_VERSION >> 8, GTP_REG_VERSION & 0xff};
+
+	ret = gtp_i2c_read(client, buf, sizeof(buf));
+	if (ret < 0) {
+		dev_err(&client->dev, "Failed read fw_info\n");
+		return ret;
+	}
+
+	fw_info->version = (buf[7] << 8) | buf[6];
+
+	/* product id */
+	memset(fw_info, 0, sizeof(*fw_info));
+	memcpy(fw_info->pid, buf + GTP_ADDR_LENGTH, 4);
+
+	if (buf[5] == 0x00)
+		dev_info(&client->dev, "IC Version: %c%c%c_%02X%02X\n",
+			 buf[2], buf[3], buf[4], buf[7], buf[6]);
+	else
+		dev_info(&client->dev, "IC Version: %c%c%c%c_%02X%02X\n",
+			 buf[2], buf[3], buf[4], buf[5], buf[7], buf[6]);
+
+	/* read sensor id */
+	fw_info->sensor_id = 0xff;
+	ret = gtp_i2c_read_dbl_check(client, GTP_REG_SENSOR_ID,
+				     &fw_info->sensor_id, 1);
+	if (SUCCESS != ret || fw_info->sensor_id >= 0x06) {
+		dev_err(&client->dev,
+			"Failed get valid sensor_id(0x%02X), No Config Sent\n",
+			fw_info->sensor_id);
+
+		fw_info->sensor_id = 0xff;
+	}
+	return ret;
+}
+
+static int gtp_i2c_test(struct i2c_client *client)
+{
+	u8 test[3] = {GTP_REG_CONFIG_DATA >> 8, GTP_REG_CONFIG_DATA & 0xff};
+	u8 retry = 0;
+	int ret = -1;
+
+	while (retry++ < 3) {
+		ret = gtp_i2c_read(client, test, 3);
+		if (ret == 2)
+			return 0;
+
+		dev_err(&client->dev, "GTP i2c test failed time %d\n", retry);
+		usleep_range(10000, 11000); /* 10 ms */
+	}
+
+	return -EAGAIN;
+}
+
+static int gtp_pinctrl_init(struct goodix_ts_data *ts)
+{
+	struct goodix_pinctrl *pinctrl = &ts->pinctrl;
+
+	pinctrl->pinctrl = devm_pinctrl_get(&ts->client->dev);
+	if (IS_ERR_OR_NULL(pinctrl->pinctrl)) {
+		dev_info(&ts->client->dev, "No pinctrl found\n");
+		pinctrl->pinctrl = NULL;
+		return 0;
+	}
+
+	pinctrl->default_sta = pinctrl_lookup_state(pinctrl->pinctrl,
+						    "default");
+	if (IS_ERR_OR_NULL(pinctrl->default_sta)) {
+		dev_err(&ts->client->dev,
+			"Failed get pinctrl state:default state\n");
+		goto exit_pinctrl_init;
+	}
+
+	pinctrl->int_out_high = pinctrl_lookup_state(pinctrl->pinctrl,
+						     "int-output-high");
+	if (IS_ERR_OR_NULL(pinctrl->int_out_high)) {
+		dev_err(&ts->client->dev,
+			"Failed get pinctrl state:output_high\n");
+		goto exit_pinctrl_init;
+	}
+
+	pinctrl->int_out_low = pinctrl_lookup_state(pinctrl->pinctrl,
+						    "int-output-low");
+	if (IS_ERR_OR_NULL(pinctrl->int_out_low)) {
+		dev_err(&ts->client->dev,
+			"Failed get pinctrl state:output_low\n");
+		goto exit_pinctrl_init;
+	}
+
+	pinctrl->int_input = pinctrl_lookup_state(pinctrl->pinctrl,
+						  "int-input");
+	if (IS_ERR_OR_NULL(pinctrl->int_input)) {
+		dev_err(&ts->client->dev,
+			"Failed get pinctrl state:int-input\n");
+		goto exit_pinctrl_init;
+	}
+	dev_info(&ts->client->dev, "Success init pinctrl\n");
+	return 0;
+exit_pinctrl_init:
+	devm_pinctrl_put(pinctrl->pinctrl);
+	pinctrl->pinctrl = NULL;
+	return -EINVAL;
+}
+
+static void gtp_pinctrl_deinit(struct goodix_ts_data *ts)
+{
+	if (ts->pinctrl.pinctrl)
+		devm_pinctrl_put(ts->pinctrl.pinctrl);
+}
+
+static int gtp_request_io_port(struct goodix_ts_data *ts)
+{
+	int ret = 0;
+
+	if (gpio_is_valid(ts->pdata->irq_gpio)) {
+		ret = gpio_request(ts->pdata->irq_gpio, "goodix_ts_int");
+		if (ret < 0) {
+			dev_err(&ts->client->dev,
+				"Failed to request GPIO:%d, ERRNO:%d\n",
+				(s32)ts->pdata->irq_gpio, ret);
+			return -ENODEV;
+		}
+
+		gpio_direction_input(ts->pdata->irq_gpio);
+		dev_info(&ts->client->dev, "Success request irq-gpio\n");
+	}
+
+	if (gpio_is_valid(ts->pdata->rst_gpio)) {
+		ret = gpio_request(ts->pdata->rst_gpio, "goodix_ts_rst");
+		if (ret < 0) {
+			dev_err(&ts->client->dev,
+				"Failed to request GPIO:%d, ERRNO:%d\n",
+				(s32)ts->pdata->rst_gpio, ret);
+
+			if (gpio_is_valid(ts->pdata->irq_gpio))
+				gpio_free(ts->pdata->irq_gpio);
+
+			return -ENODEV;
+		}
+
+		gpio_direction_input(ts->pdata->rst_gpio);
+		dev_info(&ts->client->dev,  "Success request rst-gpio\n");
+	}
+
+	return 0;
+}
+
+/*******************************************************
+ * Function:
+ *	Request interrupt if define irq pin, else use hrtimer
+ *	as interrupt source
+ * Input:
+ * 	ts: private data.
+ * Output:
+ *	Executive outcomes.
+ *		0: succeed, -1: failed.
+ *******************************************************/
+static int gtp_request_irq(struct goodix_ts_data *ts)
+{
+	int ret = -1;
+
+	/* use irq */
+	if (gpio_is_valid(ts->pdata->irq_gpio) || ts->client->irq > 0) {
+		if (gpio_is_valid(ts->pdata->irq_gpio))
+			ts->client->irq = gpio_to_irq(ts->pdata->irq_gpio);
+
+		dev_info(&ts->client->dev, "INT num %d, trigger type:%d\n",
+			 ts->client->irq, ts->pdata->irq_flags);
+		ret = request_threaded_irq(ts->client->irq, NULL,
+				gtp_irq_handler,
+				ts->pdata->irq_flags | IRQF_ONESHOT,
+				ts->client->name,
+				ts);
+		if (ret < 0) {
+			dev_err(&ts->client->dev,
+				"Failed to request irq %d\n", ts->client->irq);
+			return ret;
+		}
+	} else { /* use hrtimer */
+		dev_info(&ts->client->dev, "No hardware irq, use hrtimer\n");
+		hrtimer_init(&ts->timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
+		ts->timer.function = gtp_timer_handler;
+		hrtimer_start(&ts->timer,
+			      ktime_set(0, (GTP_POLL_TIME + 6) * 1000000),
+			      HRTIMER_MODE_REL);
+		set_bit(HRTIMER_USED, &ts->flags);
+		ret = 0;
+	}
+	return ret;
+}
+
+static s8 gtp_request_input_dev(struct goodix_ts_data *ts)
+{
+	s8 ret = -1;
+	u8 index = 0;
+
+	ts->input_dev = input_allocate_device();
+	if (ts->input_dev == NULL) {
+		dev_err(&ts->client->dev, "Failed to allocate input device\n");
+		return -ENOMEM;
+	}
+
+	ts->input_dev->evbit[0] = BIT_MASK(EV_SYN) | BIT_MASK(EV_KEY)
+		| BIT_MASK(EV_ABS);     // 注册相应的事件,同步,按键,绝对坐标
+	if (!ts->pdata->type_a_report) {
+		input_mt_init_slots(ts->input_dev, 16, INPUT_MT_DIRECT);
+		dev_info(&ts->client->dev, "Use slot report protocol\n");
+	} else {
+		__set_bit(INPUT_PROP_DIRECT, ts->input_dev->propbit);
+		__set_bit(BTN_TOUCH, ts->input_dev->keybit);
+		dev_info(&ts->client->dev, "Use type A report protocol\n");
+	}
+
+	input_set_capability(ts->input_dev, EV_KEY, BTN_STYLUS);
+        input_set_capability(ts->input_dev, EV_KEY, BTN_STYLUS2);
+	
+	/* touch key register */
+	for (index = 0; index < ts->pdata->key_nums; index++)
+		input_set_capability(ts->input_dev, EV_KEY,
+				     ts->pdata->key_map[index]);
+
+	if (ts->pdata->slide_wakeup)
+		input_set_capability(ts->input_dev, EV_KEY, KEY_POWER);
+
+	if (ts->pdata->swap_x2y)
+		GTP_SWAP(ts->pdata->abs_size_x, ts->pdata->abs_size_y);
+    // 加入单点触控的    pengjie 0720
+    input_set_abs_params(ts->input_dev, ABS_X, 0,
+			     ts->pdata->abs_size_x, 0, 0);
+	input_set_abs_params(ts->input_dev, ABS_Y, 0,
+			     ts->pdata->abs_size_y, 0, 0);
+	input_set_abs_params(ts->input_dev, ABS_MT_POSITION_X, 0,
+			     ts->pdata->abs_size_x, 0, 0);
+	input_set_abs_params(ts->input_dev, ABS_MT_POSITION_Y, 0,
+			     ts->pdata->abs_size_y, 0, 0);
+	input_set_abs_params(ts->input_dev, ABS_MT_TOUCH_MAJOR, 0,
+			     ts->pdata->max_touch_width, 0, 0);
+	input_set_abs_params(ts->input_dev, ABS_MT_PRESSURE, 0,
+			     ts->pdata->max_touch_pressure, 0, 0);
+	input_set_abs_params(ts->input_dev, ABS_MT_TRACKING_ID, 0,
+			     ts->pdata->max_touch_id, 0, 0);
+	if (!ts->pdata->type_a_report) {
+		input_set_abs_params(ts->input_dev, ABS_MT_TOOL_TYPE,
+				     0, MT_TOOL_MAX, 0, 0);
+	} else {
+		__set_bit(BTN_TOOL_PEN, ts->input_dev->keybit);
+		__set_bit(BTN_TOOL_FINGER, ts->input_dev->keybit);
+	}
+
+	ts->input_dev->name = goodix_ts_name;
+	ts->input_dev->phys = goodix_input_phys;
+	ts->input_dev->id.bustype = BUS_I2C;
+	ts->input_dev->id.vendor = 0xDEAD;
+	ts->input_dev->id.product = 0xBEEF;
+	ts->input_dev->id.version = 10427;
+
+	ret = input_register_device(ts->input_dev);
+	if (ret) {
+		dev_err(&ts->client->dev, "Register %s input device failed\n",
+				ts->input_dev->name);
+		input_free_device(ts->input_dev);
+		return -ENODEV;
+	}
+
+	return 0;
+}
+
+/*
+ * Devices Tree support
+ */
+#ifdef CONFIG_OF
+static void gtp_parse_dt_coords(struct device *dev,
+				struct goodix_ts_platform_data *pdata)
+{
+	struct device_node *np = dev->of_node;
+	int ret;
+
+	ret = of_property_read_u32(np, "touchscreen-max-id",
+				   &pdata->max_touch_id);
+	if (ret || pdata->max_touch_id > GTP_MAX_TOUCH_ID) {
+		dev_info(dev, "Unset touchscreen-max-id, use default\n");
+		pdata->max_touch_id = GTP_MAX_TOUCH_ID;
+	}
+
+	ret = of_property_read_u32(np, "touchscreen-size-x",
+				   &pdata->abs_size_x);
+	if (ret) {
+		dev_info(dev, "Unset touchscreen-size-x, use default\n");
+		pdata->abs_size_x = GTP_DEFAULT_MAX_X;
+	}
+
+	ret = of_property_read_u32(np, "touchscreen-size-y",
+				   &pdata->abs_size_y);
+	if (ret) {
+		dev_info(dev, "Unset touchscreen-size-y, use default\n");
+		pdata->abs_size_y = GTP_DEFAULT_MAX_Y;
+	}
+
+	ret = of_property_read_u32(np, "touchscreen-max-w",
+				   &pdata->max_touch_width);
+	if (ret) {
+		dev_info(dev, "Unset touchscreen-max-w, use default\n");
+		pdata->max_touch_width = GTP_DEFAULT_MAX_WIDTH;
+	}
+
+	ret = of_property_read_u32(np, "touchscreen-max-p",
+				   &pdata->max_touch_pressure);
+	if (ret) {
+		dev_info(dev, "Unset touchscreen-max-p, use default\n");
+		pdata->max_touch_pressure = GTP_DEFAULT_MAX_PRESSURE;
+	}
+	dev_info(dev, "touch input parameters is [id x y w p]<%d %d %d %d %d>\n",
+		 pdata->max_touch_id, pdata->abs_size_x, pdata->abs_size_y,
+		 pdata->max_touch_width, pdata->max_touch_pressure);
+}
+
+static int gtp_parse_dt(struct device *dev,
+			struct goodix_ts_platform_data *pdata)
+{
+	int ret;
+	u32  key_nums;
+	struct property *prop;
+	u32 key_map[MAX_KEY_NUMS];
+	struct device_node *np = dev->of_node;
+
+	gtp_parse_dt_coords(dev, pdata);
+
+
+	ret = of_property_read_u32(np, "irq-flags",
+				   &pdata->irq_flags);
+	if (ret) {
+		dev_info(dev,
+			 "Failed get int-trigger-type from dts,set default\n");
+		pdata->irq_flags = GTP_DEFAULT_INT_TRIGGER;
+	}
+	of_property_read_u32(np, "goodix,int-sync", &pdata->int_sync);
+
+	of_property_read_u32(np, "goodix,driver-send-cfg",
+			     &pdata->driver_send_cfg);
+
+	of_property_read_u32(np, "goodix,swap-x2y", &pdata->swap_x2y);
+
+	of_property_read_u32(np, "goodix,slide-wakeup", &pdata->slide_wakeup);
+
+	of_property_read_u32(np, "goodix,auto-update", &pdata->auto_update);
+
+	of_property_read_u32(np, "goodix,auto-update-cfg",
+			     &pdata->auto_update_cfg);
+
+	of_property_read_u32(np, "goodix,esd-protect", &pdata->esd_protect);
+
+	of_property_read_u32(np, "goodix,type-a-report",
+			     &pdata->type_a_report);
+
+	of_property_read_u32(np, "goodix,create-wr-node",
+			     &pdata->create_wr_node);
+
+	of_property_read_u32(np, "goodix,resume-in-workqueue",
+			     &pdata->resume_in_workqueue);
+
+	of_property_read_u32(np, "goodix,power-off-sleep",
+			     &pdata->power_off_sleep);
+	of_property_read_u32(np, "goodix,pen-suppress-finger",
+			     &pdata->pen_suppress_finger);
+
+	prop = of_find_property(np, "touchscreen-key-map", NULL);
+	if (prop) {
+		key_nums = prop->length / sizeof(key_map[0]);
+		key_nums = key_nums > MAX_KEY_NUMS ? MAX_KEY_NUMS : key_nums;
+
+		ret = of_property_read_u32_array(np,
+				"touchscreen-key-map", key_map,
+				key_nums);
+		if (ret) {
+			dev_err(dev, "Unable to read key codes\n");
+			pdata->key_nums = 0;
+			memset(pdata->key_map, 0,
+			       MAX_KEY_NUMS * sizeof(pdata->key_map[0]));
+		}
+		pdata->key_nums = key_nums;
+		memcpy(pdata->key_map, key_map,
+		       key_nums * sizeof(pdata->key_map[0]));
+		dev_info(dev, "key-map is [%*ph]\n", pdata->key_nums,
+			 pdata->key_map);
+	}
+
+	pdata->irq_gpio = of_get_named_gpio(np, "irq-gpios", 0);
+	if (!gpio_is_valid(pdata->irq_gpio))
+		dev_err(dev, "No valid irq gpio");
+
+	pdata->rst_gpio = of_get_named_gpio(np, "reset-gpios", 0);
+	if (!gpio_is_valid(pdata->rst_gpio))
+		dev_err(dev, "No valid rst gpio");
+
+	return 0;
+}
+
+/*******************************************************
+ * Function:
+ *	parse config data from devices tree.
+ * Input:
+ *	dev: device that this driver attached.
+ *	cfg: pointer of the config array.
+ *	cfg_len: pointer of the config length.
+ *	sid: sensor id.
+ * Output:
+ *	Executive outcomes.
+ *		0-succeed, -1-faileds.
+ *******************************************************/
+int gtp_parse_dt_cfg(struct device *dev, u8 *cfg, int *cfg_len, u8 sid)
+{
+	struct device_node *np = dev->of_node;
+	struct property *prop;
+	char cfg_name[18];
+	int ret;
+
+	snprintf(cfg_name, sizeof(cfg_name), "goodix,cfg-group%d", sid);
+	prop = of_find_property(np, cfg_name, cfg_len);
+	if (!prop || !prop->value || *cfg_len == 0 ||
+	    *cfg_len > GTP_CONFIG_MAX_LENGTH) {
+		*cfg_len = 0;
+		ret = -EPERM;/* failed */
+	} else {
+		memcpy(cfg, prop->value, *cfg_len);
+		ret = 0;
+	}
+
+	return ret;
+}
+
+#endif
+
+static int gtp_power_on(struct goodix_ts_data *ts)
+{
+	int ret = 0;
+
+	if (ts->vdd_ana) {
+		ret = regulator_set_voltage(ts->vdd_ana, GOODIX_VTG_MIN_UV,
+					    GOODIX_VTG_MAX_UV);
+		if (ret) {
+			dev_err(&ts->client->dev,
+				"Regulator set_vtg failed vdd ret=%d\n",
+				ret);
+			goto err_set_vtg_vdd_ana;
+		}
+
+		ret = regulator_enable(ts->vdd_ana);
+		if (ret) {
+			dev_err(&ts->client->dev,
+				"Regulator vdd enable failed ret=%d\n",
+				ret);
+			goto err_enable_vdd_ana;
+		}
+	}
+
+	if (ts->vcc_i2c) {
+		ret = regulator_set_voltage(ts->vcc_i2c, GOODIX_I2C_VTG_MIN_UV,
+					    GOODIX_I2C_VTG_MAX_UV);
+		if (ret) {
+			dev_err(&ts->client->dev,
+				"Regulator set_vtg failed vcc_i2c ret=%d\n",
+				ret);
+			goto err_set_vtg_vcc_i2c;
+		}
+
+		ret = regulator_enable(ts->vcc_i2c);
+		if (ret) {
+			dev_err(&ts->client->dev,
+				"Regulator vcc_i2c enable failed ret=%d\n",
+				ret);
+			goto err_enable_vcc_i2c;
+		}
+	}
+	clear_bit(POWER_OFF_MODE, &ts->flags);
+	return 0;
+
+err_enable_vcc_i2c:
+	if (ts->vcc_i2c)
+		regulator_set_voltage(ts->vcc_i2c, 0, GOODIX_I2C_VTG_MAX_UV);
+err_set_vtg_vcc_i2c:
+	if (ts->vdd_ana)
+		regulator_disable(ts->vdd_ana);
+err_enable_vdd_ana:
+	if (ts->vdd_ana)
+		regulator_set_voltage(ts->vdd_ana, 0, GOODIX_VTG_MAX_UV);
+err_set_vtg_vdd_ana:
+	set_bit(POWER_OFF_MODE, &ts->flags);
+	return ret;
+}
+
+static int gtp_power_off(struct goodix_ts_data *ts)
+{
+	int ret = 0;
+
+	if (ts->vcc_i2c) {
+		set_bit(POWER_OFF_MODE, &ts->flags);
+		ret = regulator_set_voltage(ts->vcc_i2c, 0,
+					    GOODIX_I2C_VTG_MAX_UV);
+		if (ret < 0) {
+			dev_err(&ts->client->dev,
+				"Regulator vcc_i2c set_vtg failed ret=%d\n",
+				ret);
+			goto err_set_vtg_vcc_i2c;
+		}
+		ret = regulator_disable(ts->vcc_i2c);
+		if (ret) {
+			dev_err(&ts->client->dev,
+				"Regulator vcc_i2c disable failed ret=%d\n",
+				ret);
+			goto err_disable_vcc_i2c;
+		}
+	}
+
+	if (ts->vdd_ana) {
+		set_bit(POWER_OFF_MODE, &ts->flags);
+		ret = regulator_set_voltage(ts->vdd_ana, 0, GOODIX_VTG_MAX_UV);
+		if (ret < 0) {
+			dev_err(&ts->client->dev,
+					"Regulator vdd set_vtg failed ret=%d\n",
+					ret);
+			goto err_set_vtg_vdd_ana;
+		}
+		ret = regulator_disable(ts->vdd_ana);
+		if (ret) {
+			dev_err(&ts->client->dev,
+					"Regulator vdd disable failed ret=%d\n",
+					ret);
+			goto err_disable_vdd_ana;
+		}
+	}
+
+	return ret;
+err_disable_vdd_ana:
+	if (ts->vdd_ana)
+		regulator_set_voltage(ts->vdd_ana, GOODIX_VTG_MIN_UV,
+				      GOODIX_VTG_MAX_UV);
+err_set_vtg_vdd_ana:
+	if (ts->vcc_i2c)
+		regulator_enable(ts->vcc_i2c);
+err_disable_vcc_i2c:
+	if (ts->vcc_i2c)
+		regulator_set_voltage(ts->vcc_i2c, GOODIX_I2C_VTG_MIN_UV,
+				      GOODIX_I2C_VTG_MAX_UV);
+err_set_vtg_vcc_i2c:
+	clear_bit(POWER_OFF_MODE, &ts->flags);
+	return ret;
+}
+
+static int gtp_power_init(struct goodix_ts_data *ts)
+{
+	int ret;
+
+	ts->vdd_ana = regulator_get(&ts->client->dev, "vdd_ana");
+	if (IS_ERR(ts->vdd_ana)) {
+		ts->vdd_ana = NULL;
+		ret = PTR_ERR(ts->vdd_ana);
+		dev_info(&ts->client->dev,
+			 "Regulator get failed vdd ret=%d\n", ret);
+	}
+
+	ts->vcc_i2c = regulator_get(&ts->client->dev, "vcc_i2c");
+	if (IS_ERR(ts->vcc_i2c)) {
+		ts->vcc_i2c = NULL;
+		ret = PTR_ERR(ts->vcc_i2c);
+		dev_info(&ts->client->dev,
+			 "Regulator get failed vcc_i2c ret=%d\n", ret);
+	}
+
+	return 0;
+}
+
+static int gtp_power_deinit(struct goodix_ts_data *ts)
+{
+	if (ts->vdd_ana)
+		regulator_put(ts->vdd_ana);
+	if (ts->vcc_i2c)
+		regulator_put(ts->vcc_i2c);
+
+	return 0;
+}
+
+void gtp_shutdown(struct i2c_client *client)
+{
+	struct goodix_ts_data *data = i2c_get_clientdata(client);
+
+	if (!data->init_done)
+		return;
+
+	gtp_work_control_enable(data, false);
+	gtp_power_off(data);
+
+	return;
+}
+
+static int gtp_probe(struct i2c_client *client, const struct i2c_device_id *id)
+{
+	int ret = -1;
+	struct goodix_ts_data *ts;
+	struct goodix_ts_platform_data *pdata;
+
+	/* do NOT remove these logs */
+	dev_info(&client->dev, "GTP Driver Version: %s\n", GTP_DRIVER_VERSION);
+	dev_info(&client->dev, "GTP I2C Address: 0x%02x\n", client->addr);
+
+	i2c_connect_client = client;
+	if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) {
+		dev_err(&client->dev, "Failed check I2C functionality");
+		return -ENODEV;
+	}
+
+	ts = devm_kzalloc(&client->dev, sizeof(*ts), GFP_KERNEL);
+	if (ts == NULL) {
+		dev_err(&client->dev, "Failed alloc ts memory");
+		return -ENOMEM;
+	}
+
+	pdata = devm_kzalloc(&client->dev, sizeof(*pdata), GFP_KERNEL);
+	if (!pdata) {
+		dev_err(&client->dev, "Failed alloc pdata memory\n");
+		devm_kfree(&client->dev, ts);
+		return -EINVAL;
+	}
+
+	ts->init_done = false;
+
+#ifdef CONFIG_OF	/* device tree support */
+	if (client->dev.of_node) {
+		ret = gtp_parse_dt(&client->dev, pdata);
+		if (ret) {
+			dev_err(&client->dev, "Failed parse dts\n");
+			goto exit_free_client_data;
+		}
+	}
+#else			/* use gpio defined in gt9xx.h */
+	pdata->rst_gpio = GTP_RST_PORT;
+	pdata->irq_gpio = GTP_INT_PORT;
+	pdata->slide_wakeup = false;
+	pdata->auto_update = true;
+	pdata->auto_update_cfg = false;
+	pdata->type_a_report = false;
+	pdata->create_wr_node = true;
+	pdata->esd_protect = false;
+#endif
+
+	ts->client = client;
+	ts->pdata = pdata;
+
+	i2c_set_clientdata(client, ts);
+#if 0    // pengjie 0716
+	ret = gtp_power_init(ts);
+	if (ret) {
+		dev_err(&client->dev, "Failed get regulator\n");
+		ret = -EINVAL;
+		goto exit_free_client_data;
+	}
+
+	ret = gtp_power_on(ts);
+	if (ret) {
+		dev_err(&client->dev, "Failed power on device\n");
+		ret = -EINVAL;
+		goto exit_deinit_power;
+	}
+
+	ret = gtp_pinctrl_init(ts);
+	if (ret < 0) {
+		/* if define pinctrl must define the following state
+		 * to let int-pin work normally: default, int_output_high,
+		 * int_output_low, int_input
+		 */
+		dev_err(&client->dev, "Failed get wanted pinctrl state\n");
+		goto exit_deinit_power;
+	}
+
+	ret = gtp_request_io_port(ts);
+	if (ret < 0) {
+		dev_err(&client->dev, "Failed request IO port\n");
+		goto exit_power_off;
+	}
+#endif
+	gtp_reset_guitar(ts->client, 20);    //pengjie 不需要复位
+
+	ret = gtp_i2c_test(client);
+	if (ret) {
+		dev_err(&client->dev, "Failed communicate with IC use I2C\n");
+		goto exit_free_io_port;
+	}
+
+	dev_info(&client->dev, "I2C Addr is %x\n", client->addr);
+
+	ret = gtp_get_fw_info(client, &ts->fw_info);
+	if (ret < 0) {
+		dev_err(&client->dev, "Failed read FW version\n");
+		goto exit_free_io_port;
+	}
+
+	pdata->config.data[0] = GTP_REG_CONFIG_DATA >> 8;
+	pdata->config.data[1] = GTP_REG_CONFIG_DATA & 0xff;
+	ret = gtp_init_panel(ts);
+	if (ret < 0)
+		dev_info(&client->dev, "Panel un-initialize\n");
+
+
+	if (ts->pdata->auto_update) {
+		ret = gup_init_update_proc(ts);
+		if (ret < 0)
+			dev_err(&client->dev, "Failed create update thread\n");
+	}
+
+	ret = gtp_request_input_dev(ts);
+	if (ret < 0) {
+		dev_err(&client->dev, "Failed request input device\n");
+		goto exit_free_io_port;
+	}
+
+	mutex_init(&ts->lock);
+
+	ret = gtp_request_irq(ts);
+	if (ret < 0) {
+		dev_err(&client->dev, "Failed create work thread");
+		goto exit_unreg_input_dev;
+	}
+	gtp_work_control_enable(ts, false);
+	if (ts->pdata->slide_wakeup) {
+		ret = enable_irq_wake(client->irq);
+		if (ret < 0)
+			dev_err(&client->dev, "Failed set irq wake");
+	}
+
+	gtp_register_powermanager(ts);
+
+	ret = gtp_create_file(ts);
+	if (ret) {
+		dev_info(&client->dev, "Failed create attributes file");
+		goto exit_powermanager;
+	}
+
+	if (pdata->create_wr_node)
+		init_wr_node(client);/*TODO judge return value */
+    
+	/*    pengjie 0716
+	gtp_esd_init(ts);
+	if (pdata->esd_protect)
+		gtp_esd_on(ts);
+	*/
+	/* probe init finished */
+	ts->init_done = true;
+	gtp_work_control_enable(ts, true);
+
+	return 0;
+
+exit_powermanager:
+	gtp_unregister_powermanager(ts);
+exit_unreg_input_dev:
+	input_unregister_device(ts->input_dev);
+exit_free_io_port:
+	if (gpio_is_valid(ts->pdata->rst_gpio))
+		gpio_free(ts->pdata->rst_gpio);
+	if (gpio_is_valid(ts->pdata->irq_gpio))
+		gpio_free(ts->pdata->irq_gpio);
+exit_power_off:
+	gtp_power_off(ts);
+	gtp_pinctrl_deinit(ts);
+exit_deinit_power:
+	gtp_power_deinit(ts);
+exit_free_client_data:
+	devm_kfree(&client->dev, pdata);
+	devm_kfree(&client->dev, ts);
+	i2c_set_clientdata(client, NULL);
+
+	return ret;
+}
+
+
+static int gtp_drv_remove(struct i2c_client *client)
+{
+	struct goodix_ts_data *ts = i2c_get_clientdata(client);
+
+	gtp_work_control_enable(ts, false);
+	gtp_unregister_powermanager(ts);
+
+	remove_proc_entry(GT91XX_CONFIG_PROC_FILE, gtp_config_proc);
+
+	sysfs_remove_group(&client->dev.kobj, &gtp_attr_group);
+
+	if (ts->pdata->create_wr_node)
+		uninit_wr_node();
+
+	if (ts->pdata->esd_protect)
+		gtp_esd_off(ts);
+
+	/* TODO: how to judge a irq numbers validity */
+	if (ts->client->irq)
+		free_irq(client->irq, ts);
+	else
+		hrtimer_cancel(&ts->timer);
+
+	if (gpio_is_valid(ts->pdata->rst_gpio))
+		gpio_free(ts->pdata->rst_gpio);
+
+	if (gpio_is_valid(ts->pdata->irq_gpio))
+		gpio_free(ts->pdata->irq_gpio);
+
+	gtp_power_off(ts);
+	gtp_power_deinit(ts);
+	gtp_pinctrl_deinit(ts);
+	dev_info(&client->dev, "goodix ts driver removed");
+	i2c_set_clientdata(client, NULL);
+	input_unregister_device(ts->input_dev);
+	mutex_destroy(&ts->lock);
+
+	devm_kfree(&client->dev, ts->pdata);
+	devm_kfree(&client->dev, ts);
+
+	return 0;
+}
+
+static void gtp_suspend(struct goodix_ts_data *ts)
+{
+	int ret = -1;
+
+	if (test_bit(FW_UPDATE_RUNNING, &ts->flags)) {
+		dev_warn(&ts->client->dev,
+			 "Fw upgrade in progress, can't go to suspend\n");
+		return;
+	}
+
+	if (test_and_set_bit(SLEEP_MODE, &ts->flags)) {
+		dev_info(&ts->client->dev, "Already in suspend state\n");
+		return;
+	}
+
+	dev_info(&ts->client->dev, "Try enter suspend mode\n");
+
+	gtp_esd_off(ts);
+	if (ts->pdata->slide_wakeup) {
+		ret = gtp_enter_doze(ts);
+	} else if (ts->pdata->power_off_sleep) {
+		/*TODO: power off routine */
+		gtp_work_control_enable(ts, false);
+		gtp_power_off(ts);
+		ret = SUCCESS;
+	} else {
+		gtp_work_control_enable(ts, false);
+		ret = gtp_enter_sleep(ts);
+	}
+
+	if (ret < 0)
+		dev_err(&ts->client->dev, "Failed enter suspend\n");
+
+	/*  to avoid waking up while not sleeping */
+	/*	delay 48 + 10ms to ensure reliability */
+	msleep(GTP_58_DLY_MS);
+}
+
+static int gtp_gesture_wakeup(struct goodix_ts_data *ts)
+{
+	int ret;
+	int retry = 10;
+
+	do {
+		gtp_reset_guitar(ts->client, 10);
+		ret = gtp_i2c_test(ts->client);
+		if (!ret)
+			break;
+	} while (--retry);
+
+	if (!retry)
+		ret = -EIO;
+
+	clear_bit(DOZE_MODE, &ts->flags);
+	return ret;
+}
+
+static void gtp_resume(struct goodix_ts_data *ts)
+{
+	int ret = 0;
+
+	if (test_bit(FW_UPDATE_RUNNING, &ts->flags)) {
+		dev_info(&ts->client->dev,
+			 "Fw upgrade in progress, can't do resume\n");
+		return;
+	}
+
+	if (!test_bit(SLEEP_MODE, &ts->flags)) {
+		dev_dbg(&ts->client->dev, "Already in awake state\n");
+		return;
+	}
+
+	dev_info(&ts->client->dev, "Try resume from sleep mode\n");
+
+	gtp_work_control_enable(ts, false);
+
+	if (ts->pdata->slide_wakeup && test_bit(DOZE_MODE, &ts->flags)) {
+		ret = gtp_gesture_wakeup(ts);
+		if (ret)
+			dev_warn(&ts->client->dev, "Failed wake up from gesture mode\n");
+	} else if (ts->pdata->power_off_sleep) {
+		ret = gtp_power_on(ts);
+		if (ret) {
+			dev_warn(&ts->client->dev, "Failed wake up from gesture mode\n");
+		} else {
+			gtp_reset_guitar(ts->client, 20);
+			ret = gtp_i2c_test(ts->client);
+			if (ret)
+				dev_warn(&ts->client->dev,
+					 "I2C communicate failed after power on\n");
+		}
+	} else {
+		ret = gtp_wakeup_sleep(ts);
+		if (ret)
+			dev_warn(&ts->client->dev,
+				 "Failed wakeup from sleep mode\n");
+	}
+
+	if (ret) {
+		dev_warn(&ts->client->dev, "Later resume failed\n");
+	} else {
+		gtp_send_cfg(ts->client);
+		gtp_esd_on(ts);
+	}
+
+	clear_bit(SLEEP_MODE, &ts->flags);
+	gtp_work_control_enable(ts, true);
+}
+
+#if defined(CONFIG_FB)
+static void fb_notify_resume_work(struct work_struct *work)
+{
+	struct goodix_ts_data *ts =
+		container_of(work, struct goodix_ts_data, fb_notify_work);
+	gtp_resume(ts);
+}
+
+/* frame buffer notifier block control the suspend/resume procedure */
+static int gtp_fb_notifier_callback(struct notifier_block *noti,
+				    unsigned long event, void *data)
+{
+	struct fb_event *ev_data = data;
+	struct goodix_ts_data *ts = container_of(noti,
+			struct goodix_ts_data, notifier);
+	int *blank;
+
+	if (ev_data && ev_data->data && event == FB_EVENT_BLANK && ts) {
+		blank = ev_data->data;
+		if (*blank == FB_BLANK_UNBLANK) {
+			dev_dbg(&ts->client->dev, "ts_resume");
+			if (ts->pdata->resume_in_workqueue)
+				schedule_work(&ts->fb_notify_work);
+			else
+				gtp_resume(ts);
+		} else if (*blank == FB_BLANK_POWERDOWN) {
+			dev_dbg(&ts->client->dev, "ts_suspend");
+			if (ts->pdata->resume_in_workqueue)
+				flush_work(&ts->fb_notify_work);
+			gtp_suspend(ts);
+		}
+	}
+
+	return 0;
+}
+
+#elif defined(CONFIG_PM)
+static int gtp_pm_suspend(struct device *dev)
+{
+	struct i2c_client *client = to_i2c_client(dev);
+	struct goodix_ts_data *ts = i2c_get_clientdata(client);
+
+	if (ts) {
+		dev_dbg(&ts->client->dev, "Suspend by i2c pm.");
+		gtp_suspend(ts);
+	}
+
+	return 0;
+}
+static int gtp_pm_resume(struct device *dev)
+{
+	struct i2c_client *client = to_i2c_client(dev);
+	struct goodix_ts_data *ts = i2c_get_clientdata(client);
+
+	if (ts) {
+		dev_dbg(&ts->client->dev, "Resume by i2c pm.");
+		gtp_resume(ts);
+	}
+
+	return 0;
+}
+
+static const struct dev_pm_ops gtp_pm_ops = {
+	.suspend = gtp_pm_suspend,
+	.resume  = gtp_pm_resume,
+};
+
+#elif defined(CONFIG_HAS_EARLYSUSPEND)
+static void gtp_early_suspend(struct early_suspend *h)
+{
+	struct goodix_ts_data *ts = container_of(h,
+			struct goodix_ts_data, early_suspend);
+
+	if (ts) {
+		dev_dbg(&ts->client->dev, "Suspend by earlysuspend module.");
+		gtp_suspend(ts);
+	}
+}
+static void gtp_late_resume(struct early_suspend *h)
+{
+	struct goodix_ts_data *ts = container_of(h,
+			struct goodix_ts_data, early_suspend);
+
+	if (ts) {
+		dev_dbg(&ts->client->dev, "Resume by earlysuspend module.");
+		gtp_resume(ts);
+	}
+}
+#endif
+
+static int gtp_register_powermanager(struct goodix_ts_data *ts)
+{
+	int ret;
+#if defined(CONFIG_FB)
+	INIT_WORK(&ts->fb_notify_work, fb_notify_resume_work);
+	ts->notifier.notifier_call = gtp_fb_notifier_callback;
+	ret = fb_register_client(&ts->notifier);
+	if (ret)
+		dev_err(&ts->client->dev,
+			"Unable to register fb_notifier: %d\n", ret);
+#elif defined(CONFIG_HAS_EARLYSUSPEND)
+	ts->early_suspend.level = EARLY_SUSPEND_LEVEL_BLANK_SCREEN + 1;
+	ts->early_suspend.suspend = goodix_ts_early_suspend;
+	ts->early_suspend.resume = goodix_ts_late_resume;
+	register_early_suspend(&ts->early_suspend);
+#endif
+
+	return ret;
+}
+
+static int gtp_unregister_powermanager(struct goodix_ts_data *ts)
+{
+#if defined(CONFIG_FB)
+		fb_unregister_client(&ts->notifier);
+#elif defined(CONFIG_HAS_EARLYSUSPEND)
+		unregister_early_suspend(&ts->early_suspend);
+#endif
+
+	return 0;
+}
+
+/*******************************************************
+ * Function:
+ *	Initialize external watchdog for esd protect
+ * Input:
+ *	client: i2c device.
+ * Output:
+ *	result of i2c write operation.
+ *		0: succeed, otherwise: failed
+ ********************************************************/
+static int gtp_init_ext_watchdog(struct i2c_client *client)
+{
+	int ret;
+	u8 opr_buffer[3] = { (u8)(GTP_REG_ESD_CHECK >> 8),
+			     (u8)GTP_REG_ESD_CHECK,
+			     (u8)GTP_ESD_CHECK_VALUE };
+
+	dev_dbg(&client->dev, "[Esd]Init external watchdog\n");
+	ret = gtp_i2c_write(client, opr_buffer, 3);
+	if (ret == 1)
+		return 0;
+
+	dev_err(&client->dev, "Failed init ext watchdog\n");
+	return -EINVAL;
+}
+
+static void gtp_esd_check_func(struct work_struct *work)
+{
+	s32 i;
+	s32 ret = -1;
+	u8 esd_buf[5] = { (u8)(GTP_REG_COMMAND >> 8), (u8)GTP_REG_COMMAND };
+	struct delayed_work *dwork = to_delayed_work(work);
+	struct goodix_ts_esd *ts_esd = container_of(dwork, struct goodix_ts_esd,
+						    delayed_work);
+	struct goodix_ts_data *ts = container_of(ts_esd, struct goodix_ts_data,
+						 ts_esd);
+
+	if (test_bit(SLEEP_MODE, &ts->flags) ||
+	    test_bit(FW_UPDATE_RUNNING, &ts->flags)) {
+		dev_dbg(&ts->client->dev,
+			"Esd cancled by power_suspend or fw_update!");
+		return;
+	}
+
+	if (ts_esd->esd_on == false)
+		return;
+
+	for (i = 0; i < 3; i++) {
+		ret = gtp_i2c_read(ts->client, esd_buf, 4);
+		if (ret < 0)
+			continue;
+
+		dev_dbg(&ts->client->dev,
+			"[Esd]0x8040 = 0x%02X, 0x8041 = 0x%02X",
+			esd_buf[2], esd_buf[3]);
+		if (esd_buf[2] == (u8)GTP_ESD_CHECK_VALUE ||
+		    esd_buf[3] != (u8)GTP_ESD_CHECK_VALUE) {
+			gtp_i2c_read(ts->client, esd_buf, 4);
+			if (ret < 0)
+				continue;
+
+			if (esd_buf[2] == (u8)GTP_ESD_CHECK_VALUE ||
+			    esd_buf[3] != (u8)GTP_ESD_CHECK_VALUE) {
+				i = 3;
+				break;
+			}
+		} else {
+			/* IC works normally, Write 0x8040 0xAA, feed the dog */
+			esd_buf[2] = (u8)GTP_ESD_CHECK_VALUE;
+			gtp_i2c_write(ts->client, esd_buf, 3);
+			break;
+		}
+	}
+	if (i >= 3) {
+		dev_err(&ts->client->dev, "IC working abnormally! Reset IC\n");
+		esd_buf[0] = 0x42;
+		esd_buf[1] = 0x26;
+		esd_buf[2] = 0x01;
+		esd_buf[3] = 0x01;
+		esd_buf[4] = 0x01;
+		gtp_i2c_write(ts->client, esd_buf, 5);
+		/* TODO: Is power off really need? */
+		msleep(GTP_50_DLY_MS);
+		gtp_power_off(ts);
+		msleep(GTP_20_DLY_MS);
+		gtp_power_on(ts);
+		msleep(GTP_20_DLY_MS);
+
+		gtp_reset_guitar(ts->client, 50);
+		msleep(GTP_50_DLY_MS);
+		gtp_send_cfg(ts->client);
+	}
+}
+
+static int gtp_esd_init(struct goodix_ts_data *ts)
+{
+	struct goodix_ts_esd *ts_esd = &ts->ts_esd;
+
+	INIT_DELAYED_WORK(&ts_esd->delayed_work, gtp_esd_check_func);
+	mutex_init(&ts_esd->mutex);
+	ts_esd->esd_on = false;
+
+	return 0;
+}
+
+void gtp_esd_on(struct goodix_ts_data *ts)
+{
+	struct goodix_ts_esd *ts_esd = &ts->ts_esd;
+
+	if (!ts->pdata->esd_protect)
+		return;
+	mutex_lock(&ts_esd->mutex);
+	if (ts_esd->esd_on == false) {
+		ts_esd->esd_on = true;
+		schedule_delayed_work(&ts_esd->delayed_work, 2 * HZ);
+		dev_info(&ts->client->dev, "ESD on");
+	}
+	mutex_unlock(&ts_esd->mutex);
+}
+
+void gtp_esd_off(struct goodix_ts_data *ts)
+{
+	struct goodix_ts_esd *ts_esd = &ts->ts_esd;
+
+	if (!ts->pdata->esd_protect)
+		return;
+	mutex_lock(&ts_esd->mutex);
+	if (ts_esd->esd_on == true) {
+		ts_esd->esd_on = false;
+		cancel_delayed_work(&ts_esd->delayed_work);
+		dev_info(&ts->client->dev, "ESD off");
+	}
+	mutex_unlock(&ts_esd->mutex);
+}
+
+#ifdef CONFIG_OF
+static const struct of_device_id gtp_match_table[] = {
+	{.compatible = "goodix,gt928",},
+	{.compatible = "goodix,gt9xx",},
+	{ },
+};
+#endif
+
+static const struct i2c_device_id gtp_device_id[] = {
+	{ GTP_I2C_NAME, 0 },
+	{ }
+};
+
+static struct i2c_driver goodix_ts_driver = {
+	.probe		= gtp_probe,
+	.remove		= gtp_drv_remove,
+	.id_table	= gtp_device_id,
+	.shutdown	= gtp_shutdown,
+	.driver = {
+		.name	  = GTP_I2C_NAME,
+		.owner	  = THIS_MODULE,
+#ifdef CONFIG_OF
+		.of_match_table = gtp_match_table,
+#endif
+#if !defined(CONFIG_FB) && defined(CONFIG_PM)
+		.pm		  = &gtp_pm_ops,
+#endif
+	},
+};
+
+static int __init gtp_init(void)
+{
+	s32 ret;
+
+	pr_info("Goodix touchscreen driver installing....\n");
+	ret = i2c_add_driver(&goodix_ts_driver);
+
+	return ret;
+}
+
+static void __exit gtp_exit(void)
+{
+	pr_info("Goodix touchscreen driver exited\n");
+	i2c_del_driver(&goodix_ts_driver);
+}
+
+module_init(gtp_init);
+module_exit(gtp_exit);
+
+MODULE_DESCRIPTION("Goodix GT9 serials Driver");
+MODULE_LICENSE("GPL");
+
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/gt9xx/gt9xx.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/gt9xx/gt9xx.h
new file mode 100644
index 0000000000000000000000000000000000000000..38e5d03eb4d3d0cc079f1f7c55534cc0c7393c5e
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/gt9xx/gt9xx.h
@@ -0,0 +1,386 @@
+/*
+ * Goodix GT9xx touchscreen driver
+ *
+ * Copyright  (C)  2016 - 2017 Goodix. Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be a reference
+ * to you, when you are integrating the GOODiX's CTP IC into your system,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * Version: 2.8.0.1
+ * Release Date: 2017/10/26
+ */
+
+#ifndef _GOODIX_GT9XX_H_
+#define _GOODIX_GT9XX_H_
+
+#include <linux/kernel.h>
+#include <linux/hrtimer.h>
+#include <linux/i2c.h>
+#include <linux/input.h>
+#include <linux/module.h>
+#include <linux/delay.h>
+#include <linux/i2c.h>
+#include <linux/proc_fs.h>
+#include <linux/string.h>
+#include <linux/uaccess.h>
+#include <linux/vmalloc.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/gpio.h>
+#include <linux/regulator/consumer.h>
+#include <linux/major.h>
+#include <linux/kdev_t.h>
+#ifdef CONFIG_OF
+#include <linux/of_gpio.h>
+#endif
+#ifdef CONFIG_FB
+#include <linux/notifier.h>
+#include <linux/fb.h>
+#endif
+#ifdef CONFIG_HAS_EARLYSUSPEND
+#include <linux/earlysuspend.h>
+#endif
+#include <linux/usb.h>
+#include <linux/power_supply.h>
+
+#define GTP_TOOL_PEN	1
+#define GTP_TOOL_FINGER 2
+
+#define MAX_KEY_NUMS 4
+#define GTP_CONFIG_MAX_LENGTH 240
+#define GTP_ADDR_LENGTH       2
+
+/***************************PART1:ON/OFF define*******************************/
+#define GTP_DEBUG_ON          1
+#define GTP_DEBUG_ARRAY_ON    0
+#define GTP_DEBUG_FUNC_ON     0
+
+struct goodix_point_t {
+	int id;
+	int x;
+	int y;
+	int w;
+	int p;
+	int tool_type;
+};
+
+struct goodix_config_data {
+	int length;
+	u8 data[GTP_CONFIG_MAX_LENGTH + GTP_ADDR_LENGTH];
+};
+
+struct goodix_ts_platform_data {
+	int irq_gpio;
+	int rst_gpio;
+	u32 irq_flags;
+	u32 abs_size_x;
+	u32 abs_size_y;
+	u32 max_touch_id;
+	u32 max_touch_width;
+	u32 max_touch_pressure;
+	u32 key_map[MAX_KEY_NUMS];
+	u32 key_nums;
+	u32 int_sync;
+	u32 driver_send_cfg;
+	u32 swap_x2y;
+	u32 slide_wakeup;
+	u32 auto_update;
+	u32 auto_update_cfg;
+	u32 esd_protect;
+	u32 type_a_report;
+	u32 create_wr_node;
+	u32 power_off_sleep;
+	u32 resume_in_workqueue;
+	u32 pen_suppress_finger;
+	struct goodix_config_data config;
+};
+
+struct goodix_ts_esd {
+	struct delayed_work delayed_work;
+	struct mutex mutex;
+	bool esd_on;
+};
+
+enum {
+	REPORT_THREAD_ENABLED = 0,
+	HRTIMER_USED,
+	FW_ERROR,
+
+	DOZE_MODE,
+	SLEEP_MODE,
+	POWER_OFF_MODE,
+	RAW_DATA_MODE,
+
+	FW_UPDATE_RUNNING,
+	PANEL_RESETTING
+};
+
+struct goodix_pinctrl {
+	struct pinctrl *pinctrl;
+	struct pinctrl_state *default_sta;
+	struct pinctrl_state *int_out_high;
+	struct pinctrl_state *int_out_low;
+	struct pinctrl_state *int_input;
+};
+
+struct goodix_fw_info {
+	u8 pid[6];
+	u16 version;
+	u8 sensor_id;
+};
+
+struct goodix_ts_data {
+	unsigned long flags; /* This member record the device status */
+
+	struct goodix_ts_esd ts_esd;
+	struct i2c_client *client;
+	struct input_dev *input_dev;
+	struct input_dev *pen_dev;
+	struct goodix_ts_platform_data *pdata;
+	/* use pinctrl control int-pin output low or high */
+	struct goodix_pinctrl pinctrl;
+	struct hrtimer timer;
+	struct mutex lock;
+	struct notifier_block ps_notif;
+	struct regulator *vdd_ana;
+	struct regulator *vcc_i2c;
+#if defined(CONFIG_FB)
+	struct notifier_block notifier;
+	struct work_struct fb_notify_work;
+#elif defined(CONFIG_HAS_EARLYSUSPEND)
+	struct early_suspend early_suspend;
+#endif
+	struct goodix_fw_info fw_info;
+	bool force_update;
+	bool init_done;
+};
+
+extern u16 show_len;
+extern u16 total_len;
+
+/************************* PART2:TODO define *******************************/
+/* STEP_1(REQUIRED): Define Configuration Information Group(s)
+ Sensor_ID Map:
+	 sensor_opt1 sensor_opt2 Sensor_ID
+		GND         GND          0
+		VDDIO      GND          1
+		NC           GND          2
+		GND         NC/300K    3
+		VDDIO      NC/300K    4
+		NC           NC/300K    5
+*/
+/* TODO: define your own default or for Sensor_ID == 0 config here.
+	 The predefined one is just a sample config,
+	 which is not suitable for your tp in most cases. */
+#define CTP_CFG_GROUP0 {\
+	0x41, 0xD0, 0x02, 0x00, 0x05, 0x0A, 0x34, \
+	0x00, 0x01, 0x08, 0x28, 0x05, 0x50, 0x32, \
+	0x03, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x00, 0x00, 0x17, 0x19, 0x1E, 0x14, 0x8C, \
+	0x2D, 0x0E, 0x3C, 0x3E, 0x82, 0x0A, 0x82, \
+	0x0A, 0x00, 0x99, 0x33, 0x1D, 0x00, 0x00, \
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x00, 0x2B, 0x19, 0x64, 0x94, 0xC0, 0x02, \
+	0x08, 0x00, 0x00, 0x04,	0xF2, 0x1C, 0x00, \
+	0xB9, 0x26, 0x00, 0x93, 0x32, 0x00, 0x77, \
+	0x42, 0x00, 0x62, 0x57, 0x00, 0x62, 0x00, \
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x00, 0x00, 0x00, 0xFF, 0x65, 0x00, 0x00, \
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x19, 0x46, 0x00, 0x00, 0x00, 0x00, 0x32, \
+	0x1C, 0x1A, 0x18, 0x16, 0x14, 0x12, 0x10, \
+	0x0E, 0x0C, 0x0A, 0x08, 0x06, 0x04, 0x02, \
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x00, 0x00, 0x00, 0x02,	0x04, 0x06, 0x08, \
+	0x0A, 0x0C, 0x0F, 0x10, 0x12, 0x13, 0x14, \
+	0x18, 0x1C, 0x1D, 0x1E, 0x1F, 0x20, 0x21, \
+	0x22, 0x24, 0x26, 0x28, 0x29, 0x2A, 0xFF, \
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+	0x00, 0x00, 0xB8, 0x01\
+}
+
+/* TODO: define your config for Sensor_ID == 1 here, if needed */
+#define CTP_CFG_GROUP1 {\
+}
+
+/* TODO: define your config for Sensor_ID == 2 here, if needed */
+#define CTP_CFG_GROUP2 {\
+}
+
+/* TODO: define your config for Sensor_ID == 3 here, if needed */
+#define CTP_CFG_GROUP3 {\
+}
+/* TODO: define your config for Sensor_ID == 4 here, if needed */
+#define CTP_CFG_GROUP4 {\
+	0x53,0xD0,0x02,0x00,0x05,0x05,0xF5,0xD5,0x21,0x48,0x2D,0x0F,\
+	0x5A,0x41,0x0E,0x05,0x00,0x00,0x32,0x32,0x20,0x00,0x05,0x14,\
+	0x14,0x1A,0x14,0x8B,0x2B,0x0C,0xB5,0xB7,0xEB,0x04,0xFF,0xFE,\
+	0x00,0x22,0x33,0x10,0x3C,0x80,0x00,0x00,0x00,0x1E,0x12,0x41,\
+	0x23,0x12,0x5A,0xAA,0xBE,0x4A,0x55,0x04,0x00,0x14,0x19,0x04,\
+	0x80,0xAB,0x00,0x7F,0xAF,0x64,0x7E,0xB3,0x00,0x7E,0xB7,0x00,\
+	0x7B,0xBB,0x3C,0x7B,0x08,0x30,0x00,0x00,0xF8,0x70,0x50,0xFF,\
+	0xFF,0x17,0x00,0x46,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x1E,\
+	0x08,0x46,0x80,0x08,0x0A,0x00,0xA0,0x00,0x3C,0x28,0x19,0x19,\
+	0x80,0x11,0x00,0x00,0x18,0x16,0x14,0x12,0x10,0x0E,0x0C,0x0A,\
+	0x08,0x06,0x04,0x02,0xFF,0xFF,0x28,0x00,0x32,0x20,0x00,0x06,\
+	0x00,0x00,0x0A,0x06,0x10,0x08,0x0A,0x22,0xEB,0x04,0x26,0x24,\
+	0x22,0x21,0x20,0x1F,0x1E,0x1D,0x1C,0x18,0x16,0x12,0x10,0x0F,\
+	0x0C,0x0A,0x08,0x06,0x04,0x02,0x00,0x13,0xFF,0xFF,0xFF,0xFF,\
+	0x00,0x00,0x00,0x02,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,\
+	0x00,0x00,0x00,0x00,0x28,0x0B,0x0B,0x00,0x00,0x00,0x00,0x00,\
+	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,\
+	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,\
+	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xE6,0x10,0xEF,0x01\
+}
+
+/* TODO: define your config for Sensor_ID == 5 here, if needed */
+#define CTP_CFG_GROUP5 {\
+}
+
+/* STEP_2(REQUIRED): Customize your I/O ports & I/O operations */
+#define GTP_RST_PORT    64 /* EXYNOS4_GPX2(0) */
+#define GTP_INT_PORT    65 /* EXYNOS4_GPX2(1) */
+
+#define GTP_GPIO_AS_INPUT(pin)          (gpio_direction_input(pin))
+#define GTP_GPIO_AS_INT(pin)            (GTP_GPIO_AS_INPUT(pin))
+#define GTP_GPIO_GET_VALUE(pin)         gpio_get_value(pin)
+#define GTP_GPIO_OUTPUT(pin, level)      gpio_direction_output(pin, level)
+#define GTP_GPIO_REQUEST(pin, label)    gpio_request(pin, label)
+#define GTP_GPIO_FREE(pin)              gpio_free(pin)
+
+/* STEP_3(optional): Specify your special config info if needed */
+#define GTP_DEFAULT_MAX_X	 720    /* default coordinate max values */
+#define GTP_DEFAULT_MAX_Y	 1080
+#define GTP_DEFAULT_MAX_WIDTH	 1024
+#define GTP_DEFAULT_MAX_PRESSURE 1024
+#define GTP_DEFAULT_INT_TRIGGER	 1 /* 1 rising, 2 falling */
+#define GTP_MAX_TOUCH_ID	 16
+
+/* STEP_4(optional): If keys are available and reported as keys,
+config your key info here */
+#define GTP_KEY_TAB {KEY_MENU, KEY_HOME, KEY_BACK, KEY_HOMEPAGE, \
+	KEY_F1, KEY_F2, KEY_F3}
+
+/**************************PART3:OTHER define*******************************/
+#define GTP_DRIVER_VERSION	"V2.8.0.1<2017/10/26>"
+#define GTP_I2C_NAME		"goodix-ts"
+#define GT91XX_CONFIG_PROC_FILE	"gt9xx_config"
+#define GTP_POLL_TIME		10
+#define GTP_CONFIG_MIN_LENGTH	186
+#define GTP_ESD_CHECK_VALUE	0xAA
+#define RETRY_MAX_TIMES		5
+#define PEN_TRACK_ID		9
+#define MASK_BIT_8		0x80
+#define FAIL			0
+#define SUCCESS			1
+
+/* Registers define */
+#define GTP_REG_VERSION		0x8140
+#define GTP_REG_ESD_CHECK	0x8141
+#define GTP_REG_SENSOR_ID	0x814A
+#define GTP_REG_DOZE_BUF	0x814B
+#define GTP_READ_COOR_ADDR	0x814E
+#define GTP_REG_SLEEP		0x8040
+#define GTP_REG_COMMAND		0x8040
+#define GTP_REG_COMMAND_CHECK	0x8046
+#define GTP_REG_CONFIG_DATA	0x8047
+
+/* Sleep time define */
+#define GTP_1_DLY_MS		1
+#define GTP_2_DLY_MS		2
+#define GTP_10_DLY_MS		10
+#define GTP_20_DLY_MS		20
+#define GTP_50_DLY_MS		50
+#define GTP_58_DLY_MS		58
+#define GTP_100_DLY_MS		100
+#define GTP_500_DLY_MS		500
+#define GTP_1000_DLY_MS		1000
+#define GTP_3000_DLY_MS		3000
+
+#define RESOLUTION_LOC        3
+#define TRIGGER_LOC           8
+
+#define CFG_GROUP_LEN(p_cfg_grp)  (sizeof(p_cfg_grp) / sizeof(p_cfg_grp[0]))
+/* Log define */
+#define GTP_DEBUG(fmt, arg...) \
+do { \
+	if (GTP_DEBUG_ON) {\
+		pr_info("<<-GTP-DEBUG->> [%d]"fmt"\n", __LINE__, ##arg);\
+	} \
+} while (0)
+#define GTP_DEBUG_ARRAY(array, num) \
+do { \
+	s32 i;\
+	u8 *a = array;\
+	if (GTP_DEBUG_ARRAY_ON) {\
+		pr_warn("<<-GTP-DEBUG-ARRAY->>\n");\
+		for (i = 0; i < (num); i++) {\
+			pr_warn("%02x  ", (a)[i]);\
+			if ((i + 1) % 10 == 0) {\
+				pr_warn("\n");\
+			} \
+		} \
+		pr_warn("\n");\
+	} \
+} while (0)
+#define GTP_DEBUG_FUNC() \
+do {\
+	if (GTP_DEBUG_FUNC_ON) {\
+		pr_warn("<<-GTP-FUNC->>  Func:%s@Line:%d\n", \
+		__func__, __LINE__);\
+	} \
+} while (0)
+#define GTP_SWAP(x, y) \
+do {\
+	typeof(x) z = x;\
+	x = y;\
+	y = z;\
+} while (0)
+
+/******************************End of Part III********************************/
+#ifdef CONFIG_OF
+extern int gtp_parse_dt_cfg(struct device *dev, u8 *cfg, int *cfg_len, u8 sid);
+#endif
+
+extern void gtp_reset_guitar(struct i2c_client *client, s32 ms);
+extern void gtp_int_sync(struct goodix_ts_data *ts, s32 ms);
+extern void gtp_esd_on(struct goodix_ts_data *ts);
+extern void gtp_esd_off(struct goodix_ts_data *ts);
+extern void gtp_work_control_enable(struct goodix_ts_data *ts, bool enable);
+extern u8 gup_init_update_proc(struct goodix_ts_data *);
+extern s32 gtp_send_cfg(struct i2c_client *client);
+extern s32 gup_update_proc(void *dir);
+
+extern s32 init_wr_node(struct i2c_client *);
+extern void uninit_wr_node(void);
+
+/*********** For gt9xx_update Start *********/
+extern struct i2c_client *i2c_connect_client;
+extern void gtp_reset_guitar(struct i2c_client *client, s32 ms);
+extern void gtp_int_output(struct goodix_ts_data *ts, int level);
+extern s32 gtp_send_cfg(struct i2c_client *client);
+extern s32 gtp_get_fw_info(struct i2c_client *, struct goodix_fw_info *fw_info);
+extern s32 gtp_i2c_read_dbl_check(struct i2c_client *, u16, u8 *, int);
+extern int gtp_i2c_read(struct i2c_client *, u8 *, int);
+extern int gtp_i2c_write(struct i2c_client *, u8 *, int);
+extern s32 gtp_fw_startup(struct i2c_client *client);
+/*********** For gt9xx_update End *********/
+
+/*********** For goodix_tool Start *********/
+extern s32 gup_enter_update_mode(struct i2c_client *client);
+extern s32 gup_update_proc(void *dir);
+extern void gup_leave_update_mode(struct i2c_client *client);
+/*********** For goodix_tool End *********/
+
+#endif /* _GOODIX_GT9XX_H_ */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/gt9xx/gt9xx_update.c b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/gt9xx/gt9xx_update.c
new file mode 100644
index 0000000000000000000000000000000000000000..f30f4fc6b5eb38d6e78b71bcd9b7352d62b4f0ca
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/gt9xx/gt9xx_update.c
@@ -0,0 +1,2176 @@
+/*
+ * Goodix GT9xx touchscreen driver
+ *
+ * Copyright  (C)  2016 - 2017 Goodix. Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be a reference
+ * to you, when you are integrating the GOODiX's CTP IC into your system,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * Version: 2.8.0.1
+ * Release Date: 2017/10/26
+ */
+
+#include <linux/kthread.h>
+#include "gt9xx.h"
+
+#include <linux/namei.h>
+#include <linux/mount.h>
+#include <linux/firmware.h>
+#include <linux/ctype.h>
+
+#define GUP_REG_HW_INFO		0x4220
+#define GUP_REG_FW_MSG		0x41E4
+#define GUP_REG_PID_VID		0x8140
+
+#define FIRMWARE_NAME_LEN_MAX		256
+#define GOODIX_FIRMWARE_FILE_NAME	"goodix_firmware.bin"
+#define GOODIX_CONFIG_FILE_NAME		"goodix_config.cfg"
+
+#define FW_HEAD_LENGTH			14
+#define FW_SECTION_LENGTH		0x2000	/*  8K */
+#define FW_DSP_ISP_LENGTH		0x1000	/*  4K */
+#define FW_DSP_LENGTH			0x1000	/*  4K */
+#define FW_BOOT_LENGTH			0x800	/*  2K */
+#define FW_SS51_LENGTH		(4 * FW_SECTION_LENGTH)	/*  32K */
+#define FW_BOOT_ISP_LENGTH		0x800	/*  2k */
+#define FW_GLINK_LENGTH			0x3000	/*  12k */
+#define FW_GWAKE_LENGTH		(4 * FW_SECTION_LENGTH) /*  32k */
+
+#define PACK_SIZE			256
+#define MAX_FRAME_CHECK_TIME		5
+
+
+#define _bRW_MISCTL__SRAM_BANK		0x4048
+#define _bRW_MISCTL__MEM_CD_EN		0x4049
+#define _bRW_MISCTL__CACHE_EN		0x404B
+#define _bRW_MISCTL__TMR0_EN		0x40B0
+#define _rRW_MISCTL__SWRST_B0_		0x4180
+#define _bWO_MISCTL__CPU_SWRST_PULSE	0x4184
+#define _rRW_MISCTL__BOOTCTL_B0_	0x4190
+#define _rRW_MISCTL__BOOT_OPT_B0_	0x4218
+#define _rRW_MISCTL__BOOT_CTL_		0x5094
+
+#pragma pack(1)
+struct st_fw_head {
+	u8	hw_info[4];			 /* hardware info */
+	u8	pid[8];				 /* product id */
+	u16 vid;				 /* version id */
+};
+#pragma pack()
+
+struct st_update_msg {
+	u8 force_update;
+	u8 fw_flag;
+	const u8 *fw_data;
+	struct file *cfg_file;
+	struct st_fw_head ic_fw_msg;
+	u32 fw_total_len;
+	u32 fw_burned_len;
+	const struct firmware *fw;
+} update_msg;
+
+struct st_update_msg update_msg;
+
+u16 show_len;
+u16 total_len;
+
+static u8 gup_burn_fw_gwake_section(struct i2c_client *client,
+				    u8 *fw_section, u16 start_addr,
+				    u32 len, u8 bank_cmd);
+
+static s32 gup_init_panel(struct goodix_ts_data *ts)
+{
+	s32 ret = 0;
+	s32 i = 0;
+	u8 check_sum = 0;
+	u8 opr_buf[16];
+	u8 sensor_id = 0;
+	u8 drv_cfg_version;
+	u8 flash_cfg_version;
+	struct goodix_config_data *cfg = &ts->pdata->config;
+
+	if (cfg->length < GTP_CONFIG_MIN_LENGTH) {
+		dev_err(&ts->client->dev,
+			"No valid config with sensor_ID(%d) ",
+			sensor_id);
+
+		return -EPERM;
+	}
+
+	ret = gtp_i2c_read_dbl_check(ts->client, GTP_REG_CONFIG_DATA,
+				     &opr_buf[0], 1);
+	if (ret == SUCCESS) {
+		dev_dbg(&ts->client->dev,
+			"CFG_GROUP%d Config Version: %d, IC Config Version: %d",
+			sensor_id, cfg->data[GTP_ADDR_LENGTH], opr_buf[0]);
+
+		flash_cfg_version = opr_buf[0];
+		drv_cfg_version = cfg->data[GTP_ADDR_LENGTH];
+
+		if (flash_cfg_version < 90 &&
+		    flash_cfg_version > drv_cfg_version)
+			cfg->data[GTP_ADDR_LENGTH] = 0x00;
+	} else {
+		dev_err(&ts->client->dev,
+			"Failed to get ic config version!No config sent!");
+		return -EPERM;
+	}
+
+	ret = gtp_send_cfg(ts->client);
+	if (ret < 0)
+		dev_err(&ts->client->dev, "Send config error.");
+	else
+		usleep_range(10000, 11000);
+
+	/* restore config vrsion */
+	cfg->data[GTP_ADDR_LENGTH] = drv_cfg_version;
+
+	return 0;
+}
+
+
+static u8 gup_get_ic_msg(struct i2c_client *client, u16 addr, u8 *msg, s32 len)
+{
+	s32 i = 0;
+
+	msg[0] = (addr >> 8) & 0xff;
+	msg[1] = addr & 0xff;
+
+	for (i = 0; i < 5; i++) {
+		if (gtp_i2c_read(client, msg, GTP_ADDR_LENGTH + len) > 0)
+			break;
+	}
+
+	if (i >= 5) {
+		dev_err(&client->dev,
+				"Read data from 0x%02x%02x failed!",
+				msg[0], msg[1]);
+		return FAIL;
+	}
+
+	return SUCCESS;
+}
+
+static u8 gup_set_ic_msg(struct i2c_client *client, u16 addr, u8 val)
+{
+	s32 i = 0;
+	u8 msg[3];
+
+	msg[0] = (addr >> 8) & 0xff;
+	msg[1] = addr & 0xff;
+	msg[2] = val;
+
+	for (i = 0; i < 5; i++) {
+		if (gtp_i2c_write(client, msg, GTP_ADDR_LENGTH + 1) > 0)
+			break;
+	}
+
+	if (i >= 5) {
+		dev_err(&client->dev,
+			"Set data to 0x%02x%02x failed!", msg[0], msg[1]);
+		return FAIL;
+	}
+
+	return SUCCESS;
+}
+
+static u8 gup_get_ic_fw_msg(struct i2c_client *client)
+{
+	s32 ret = -1;
+	u8	retry = 0;
+	u8	buf[16];
+	u8	i;
+
+	/*  step1:get hardware info */
+	ret = gtp_i2c_read_dbl_check(client, GUP_REG_HW_INFO,
+				     &buf[GTP_ADDR_LENGTH], 4);
+	if (FAIL == ret) {
+		dev_err(&client->dev, "[get_ic_fw_msg]get hw_info failed,exit");
+		return FAIL;
+	}
+
+	/*  buf[2~5]: 00 06 90 00
+	 *  hw_info: 00 90 06 00
+	 */
+	for (i = 0; i < 4; i++)
+		update_msg.ic_fw_msg.hw_info[i] = buf[GTP_ADDR_LENGTH + 3 - i];
+		dev_dbg(&client->dev,
+			"IC Hardware info:%02x%02x%02x%02x",
+			update_msg.ic_fw_msg.hw_info[0],
+			update_msg.ic_fw_msg.hw_info[1],
+			update_msg.ic_fw_msg.hw_info[2],
+			update_msg.ic_fw_msg.hw_info[3]);
+	/*  step2:get firmware message */
+	for (retry = 0; retry < 2; retry++) {
+		ret = gup_get_ic_msg(client, GUP_REG_FW_MSG, buf, 1);
+		if (FAIL == ret) {
+			dev_err(&client->dev, "Read firmware message fail.");
+			return ret;
+		}
+
+		update_msg.force_update = buf[GTP_ADDR_LENGTH];
+		if ((0xBE != update_msg.force_update) && (!retry)) {
+			dev_info(&client->dev, "The check sum in ic is error.");
+			dev_info(&client->dev, "The IC will be updated by force.");
+			continue;
+		}
+		break;
+	}
+	dev_dbg(&client->dev,
+		"IC force update flag:0x%x", update_msg.force_update);
+
+	/*  step3:get pid & vid */
+	ret = gtp_i2c_read_dbl_check(client, GUP_REG_PID_VID,
+				     &buf[GTP_ADDR_LENGTH], 6);
+	if (FAIL == ret) {
+		dev_err(&client->dev, "[get_ic_fw_msg]get pid & vid failed,exit");
+		return FAIL;
+	}
+
+	memset(update_msg.ic_fw_msg.pid, 0, sizeof(update_msg.ic_fw_msg.pid));
+	memcpy(update_msg.ic_fw_msg.pid, &buf[GTP_ADDR_LENGTH], 4);
+	dev_dbg(&client->dev, "IC Product id:%s", update_msg.ic_fw_msg.pid);
+
+	/* GT9XX PID MAPPING */
+	/*|-----FLASH-----RAM-----|
+	 *|------918------918-----|
+	 *|------968------968-----|
+	 *|------913------913-----|
+	 *|------913P-----913P----|
+	 *|------927------927-----|
+	 *|------927P-----927P----|
+	 *|------9110-----9110----|
+	 *|------9110P----9111----|*/
+	if (update_msg.ic_fw_msg.pid[0] != 0) {
+		if (!memcmp(update_msg.ic_fw_msg.pid, "9111", 4)) {
+			dev_dbg(&client->dev, "IC Mapping Product id:%s",
+					update_msg.ic_fw_msg.pid);
+			memcpy(update_msg.ic_fw_msg.pid, "9110P", 5);
+		}
+	}
+
+	update_msg.ic_fw_msg.vid = buf[GTP_ADDR_LENGTH+4]
+	+ (buf[GTP_ADDR_LENGTH + 5]<<8);
+	dev_dbg(&client->dev, "IC version id:%04x", update_msg.ic_fw_msg.vid);
+
+	return SUCCESS;
+}
+
+s32 gup_enter_update_mode(struct i2c_client *client)
+{
+	s32 ret = -1;
+	s32 retry = 0;
+	u8 rd_buf[3];
+
+	struct goodix_ts_data *ts = i2c_get_clientdata(client);
+
+	/* step1:RST output low last at least 2ms */
+	if (!gpio_is_valid(ts->pdata->rst_gpio)) {
+		dev_err(&ts->client->dev, "update failed, no rst pin\n");
+		return FAIL;
+	}
+	gpio_direction_output(ts->pdata->rst_gpio, 0);
+	usleep_range(2000, 3000);
+
+	/* step2:select I2C slave addr,INT:0--0xBA;1--0x28. */
+	gtp_int_output(ts, client->addr == 0x14);
+	usleep_range(2000, 3000);
+
+	/* step3:RST output high reset guitar */
+	gpio_direction_output(ts->pdata->rst_gpio, 1);
+
+	/* 20121211 modify start */
+	usleep_range(5000, 6000);
+	while (retry++ < 200) {
+		/* step4:Hold ss51 & dsp */
+		ret = gup_set_ic_msg(client, _rRW_MISCTL__SWRST_B0_, 0x0C);
+		if (ret <= 0) {
+			dev_dbg(&client->dev,
+				"Hold ss51 & dsp I2C error,retry:%d",
+				retry);
+			continue;
+		}
+
+		/* step5:Confirm hold */
+		ret = gup_get_ic_msg(client, _rRW_MISCTL__SWRST_B0_, rd_buf, 1);
+		if (ret <= 0) {
+			dev_dbg(&client->dev,
+				"Hold ss51 & dsp I2C error,retry:%d",
+				retry);
+			continue;
+		}
+		if (0x0C == rd_buf[GTP_ADDR_LENGTH]) {
+			dev_dbg(&client->dev, "Hold ss51 & dsp confirm SUCCESS");
+			break;
+		}
+		dev_dbg(&client->dev,
+			"Hold ss51 & dsp confirm 0x4180 failed,value:%d",
+			rd_buf[GTP_ADDR_LENGTH]);
+	}
+	if (retry >= 200) {
+		dev_err(&client->dev, "Enter update Hold ss51 failed.");
+		return FAIL;
+	}
+
+	/* step6:DSP_CK and DSP_ALU_CK PowerOn */
+	ret = gup_set_ic_msg(client, 0x4010, 0x00);
+
+	/* 20121211 modify end */
+	return ret;
+}
+
+void gup_leave_update_mode(struct i2c_client *client)
+{
+	struct goodix_ts_data *ts = i2c_get_clientdata(client);
+
+	if (ts->pdata->int_sync && ts->pinctrl.pinctrl) {
+		pinctrl_select_state(ts->pinctrl.pinctrl,
+				     ts->pinctrl.int_input);
+	} else if (ts->pdata->int_sync && gpio_is_valid(ts->pdata->irq_gpio))
+		gpio_direction_input(ts->pdata->irq_gpio);
+	dev_dbg(&client->dev, "[leave_update_mode]reset chip.");
+	gtp_reset_guitar(i2c_connect_client, 20);
+}
+
+static u8 gup_enter_update_judge(struct i2c_client *client,
+		struct st_fw_head *fw_head)
+{
+	u16 u16_tmp;
+	s32 i = 0;
+	u32 fw_len = 0;
+	s32 pid_cmp_len = 0;
+
+	u16_tmp = fw_head->vid;
+	fw_head->vid = (u16)(u16_tmp>>8) + (u16)(u16_tmp<<8);
+
+	dev_info(&client->dev, "FILE HARDWARE INFO:%*ph\n", 4,
+		 &fw_head->hw_info[0]);
+	dev_info(&client->dev, "FILE PID:%s\n", fw_head->pid);
+	dev_info(&client->dev, "FILE VID:%04x\n", fw_head->vid);
+
+	dev_info(&client->dev, "IC HARDWARE INFO:%*ph\n", 4,
+		 &update_msg.ic_fw_msg.hw_info[0]);
+	dev_info(&client->dev, "IC PID:%s\n", update_msg.ic_fw_msg.pid);
+	dev_info(&client->dev, "IC VID:%04x\n", update_msg.ic_fw_msg.vid);
+
+	if (!memcmp(fw_head->pid, "9158", 4) &&
+	    !memcmp(update_msg.ic_fw_msg.pid, "915S", 4)) {
+		dev_info(&client->dev, "Update GT915S to GT9158 directly!");
+		return SUCCESS;
+	}
+	/* First two conditions */
+	if (!memcmp(fw_head->hw_info, update_msg.ic_fw_msg.hw_info,
+	sizeof(update_msg.ic_fw_msg.hw_info))) {
+		fw_len = 42 * 1024;
+	} else {
+		fw_len = fw_head->hw_info[3];
+		fw_len += (((u32)fw_head->hw_info[2]) << 8);
+		fw_len += (((u32)fw_head->hw_info[1]) << 16);
+		fw_len += (((u32)fw_head->hw_info[0]) << 24);
+	}
+	if (update_msg.fw_total_len != fw_len) {
+		dev_err(&client->dev,
+			"Inconsistent firmware size, Update aborted!");
+		dev_err(&client->dev,
+			" Default size: %d(%dK), actual size: %d(%dK)",
+			fw_len, fw_len/1024, update_msg.fw_total_len,
+			update_msg.fw_total_len/1024);
+		return FAIL;
+	}
+	dev_info(&client->dev, "Firmware length:%d(%dK)",
+		 update_msg.fw_total_len,
+		 update_msg.fw_total_len/1024);
+
+	if (update_msg.force_update != 0xBE) {
+		dev_info(&client->dev, "FW chksum error,need enter update.");
+		return SUCCESS;
+	}
+
+	/*  20130523 start */
+	if (strlen(update_msg.ic_fw_msg.pid) < 3) {
+		dev_info(&client->dev, "Illegal IC pid, need enter update");
+		return SUCCESS;
+	}
+
+	/* check pid legality */
+	for (i = 0; i < 3; i++) {
+		if (!isdigit(update_msg.ic_fw_msg.pid[i])) {
+			dev_info(&client->dev,
+				 "Illegal IC pid, need enter update");
+			return SUCCESS;
+		}
+	}
+	/*  20130523 end */
+
+	pid_cmp_len = strlen(fw_head->pid);
+	if (pid_cmp_len < strlen(update_msg.ic_fw_msg.pid))
+		pid_cmp_len = strlen(update_msg.ic_fw_msg.pid);
+
+	if ((!memcmp(fw_head->pid, update_msg.ic_fw_msg.pid, pid_cmp_len)) ||
+			(!memcmp(update_msg.ic_fw_msg.pid, "91XX", 4)) ||
+			(!memcmp(fw_head->pid, "91XX", 4))) {
+		if (!memcmp(fw_head->pid, "91XX", 4))
+			dev_dbg(&client->dev,
+				"Force none same pid update mode.");
+		else
+			dev_dbg(&client->dev, "Get the same pid.");
+
+		/* The third condition */
+		if (fw_head->vid != update_msg.ic_fw_msg.vid) {
+			dev_info(&client->dev, "Need enter update.");
+			return SUCCESS;
+		}
+		dev_err(&client->dev, "File VID == Ic VID, update aborted!");
+	} else {
+		dev_err(&client->dev, "File PID != Ic PID, update aborted!");
+	}
+
+	return FAIL;
+}
+
+static u8 ascii2hex(u8 a)
+{
+	s8 value = 0;
+
+	if (a >= '0' && a <= '9')
+		value = a - '0';
+	else if (a >= 'A' && a <= 'F')
+		value = a - 'A' + 0x0A;
+	else if (a >= 'a' && a <= 'f')
+		value = a - 'a' + 0x0A;
+	else
+		value = 0xff;
+
+	return value;
+}
+
+static s8 gup_update_config(struct i2c_client *client,
+			    const struct firmware *fw_cfg)
+{
+	s32 ret = 0;
+	s32 i = 0;
+	s32 file_cfg_len = 0;
+	s32 chip_cfg_len = 0;
+	s32 count = 0;
+	u8 *buf;
+	u8 *file_config;
+
+	struct goodix_ts_data *ts = i2c_get_clientdata(client);
+
+	if (!fw_cfg || !fw_cfg->data) {
+		dev_err(&ts->client->dev,
+			"[update_cfg]No need to upgrade config!");
+		return FAIL;
+	}
+
+	chip_cfg_len = ts->pdata->config.length;
+
+	dev_dbg(&client->dev,
+		"[update_cfg]config file ASCII len:%zu", fw_cfg->size);
+	dev_dbg(&client->dev, "[update_cfg]need config len:%d", chip_cfg_len);
+	if (fw_cfg->size + 5 < chip_cfg_len * 5) {
+		dev_err(&ts->client->dev, "[update_cfg]Config length error");
+		return -EPERM;
+	}
+
+	buf = kzalloc(fw_cfg->size, GFP_KERNEL);
+	if (!buf)
+		return -ENOMEM;
+
+	file_config = kzalloc(chip_cfg_len + GTP_ADDR_LENGTH, GFP_KERNEL);
+	if (!file_config)
+		return -ENOMEM;
+
+	dev_dbg(&client->dev, "[update_cfg]Delete illgal charactor.");
+	for (i = 0, count = 0; i < fw_cfg->size; i++) {
+		if (fw_cfg->data[i] == ' ' ||
+		    fw_cfg->data[i] == '\r' ||
+		    fw_cfg->data[i] == '\n')
+			continue;
+		buf[count++] = fw_cfg->data[i];
+	}
+
+	dev_dbg(&client->dev, "[update_cfg]Ascii to hex.");
+	file_config[0] = GTP_REG_CONFIG_DATA >> 8;
+	file_config[1] = GTP_REG_CONFIG_DATA & 0xff;
+	for (i = 0, file_cfg_len = GTP_ADDR_LENGTH; i < count; i += 5) {
+		if ((buf[i] == '0') && ((buf[i+1] == 'x') ||
+					(buf[i+1] == 'X'))) {
+			u8 high, low;
+
+			high = ascii2hex(buf[i+2]);
+			low = ascii2hex(buf[i+3]);
+
+			if ((high == 0xFF) || (low == 0xFF)) {
+				ret = 0;
+				dev_err(&ts->client->dev,
+					"[update_cfg]Illegal config file.");
+				goto update_cfg_file_failed;
+			}
+			file_config[file_cfg_len++] = (high<<4) + low;
+		} else {
+			ret = 0;
+			dev_err(&ts->client->dev,
+				"[update_cfg]Illegal config file.");
+			goto update_cfg_file_failed;
+		}
+	}
+
+	dev_dbg(&client->dev, "config:");
+	GTP_DEBUG_ARRAY(file_config+2, file_cfg_len);
+
+	i = 0;
+	while (i++ < 5) {
+		ret = gtp_i2c_write(client, file_config, file_cfg_len);
+		if (ret > 0) {
+			dev_info(&client->dev,
+				 "[update_cfg]Send config SUCCESS.");
+			break;
+		}
+		dev_err(&ts->client->dev,
+			"[update_cfg]Send config i2c error.");
+	}
+
+update_cfg_file_failed:
+	kfree(buf);
+	kfree(file_config);
+
+	return ret;
+}
+
+static u8 gup_check_firmware_name(struct i2c_client *client,
+		u8 **path_p)
+{
+	u8 len;
+	u8 *fname;
+
+	if (!(*path_p)) {
+		*path_p = GOODIX_FIRMWARE_FILE_NAME;
+		return 0;
+	}
+
+	len = strnlen(*path_p, FIRMWARE_NAME_LEN_MAX);
+	if (len >= FIRMWARE_NAME_LEN_MAX) {
+		dev_err(&client->dev, "firmware name too long!");
+		return -EINVAL;
+	}
+
+	fname = strrchr(*path_p, '/');
+	if (fname) {
+		fname = fname + 1;
+		*path_p = fname;
+	}
+
+	return 0;
+}
+
+static s32 gup_get_update_config_file(struct i2c_client *client)
+{
+	s32 ret = 0;
+	const struct firmware *fw = NULL;
+
+	ret = request_firmware(&fw, GOODIX_CONFIG_FILE_NAME,
+		&client->dev);
+	if (ret < 0) {
+		dev_info(&client->dev,
+			 "Cannot get config file - %s (%d)\n",
+			 GOODIX_CONFIG_FILE_NAME, ret);
+	} else {
+		dev_dbg(&client->dev, "Update config File: %s",
+			GOODIX_CONFIG_FILE_NAME);
+		ret = gup_update_config(client, fw);
+		if (ret <= 0)
+			dev_err(&client->dev, "Update config failed.");
+		release_firmware(fw);
+	}
+
+	return ret;
+}
+
+static u8 gup_get_update_file(struct i2c_client *client,
+				struct st_fw_head *fw_head, u8 *path)
+{
+	s32 ret = 0;
+	s32 i = 0;
+	s32 fw_checksum = 0;
+	struct goodix_ts_data *ts = i2c_get_clientdata(client);
+
+	if (ts->pdata->auto_update_cfg) {
+		ret = gup_get_update_config_file(client);
+		if (ret < 0) {
+			dev_info(&client->dev, "Cannot get config file");
+			return FAIL;
+		}
+	}
+
+	ret = gup_check_firmware_name(client, &path);
+	if (ret < 0)
+		return FAIL;
+
+	ret = request_firmware(&update_msg.fw, path, &client->dev);
+	if (ret < 0) {
+		dev_err(&client->dev, "Failed get firmware:%d\n", ret);
+		return FAIL;
+	}
+
+	dev_info(&client->dev, "FW File: %s size=%zu",
+		 path, update_msg.fw->size);
+	update_msg.fw_data = update_msg.fw->data;
+	update_msg.fw_total_len = update_msg.fw->size;
+
+	if (update_msg.fw_total_len <
+	    FW_HEAD_LENGTH + FW_SECTION_LENGTH * 4 + FW_DSP_ISP_LENGTH +
+	    FW_DSP_LENGTH + FW_BOOT_LENGTH) {
+		dev_err(&client->dev,
+			"INVALID bin file(size: %d), update aborted.",
+			update_msg.fw_total_len);
+		goto invalied_fw;
+	}
+
+	update_msg.fw_total_len -= FW_HEAD_LENGTH;
+
+	dev_dbg(&client->dev, "Bin firmware actual size: %d(%dK)",
+		update_msg.fw_total_len, update_msg.fw_total_len/1024);
+
+	memcpy(fw_head, update_msg.fw_data, FW_HEAD_LENGTH);
+
+	/* check firmware legality */
+	fw_checksum = 0;
+	for (i = 0; i < update_msg.fw_total_len; i += 2) {
+		u16 temp;
+
+		temp = (update_msg.fw_data[FW_HEAD_LENGTH + i] << 8) +
+			update_msg.fw_data[FW_HEAD_LENGTH + i + 1];
+		fw_checksum += temp;
+	}
+
+	dev_dbg(&client->dev, "firmware checksum:%x", fw_checksum&0xFFFF);
+	if (fw_checksum & 0xFFFF) {
+		dev_err(&client->dev, "Illegal firmware file.");
+		goto invalied_fw;
+	}
+
+	return SUCCESS;
+
+invalied_fw:
+	update_msg.fw_data = NULL;
+	update_msg.fw_total_len = 0;
+	release_firmware(update_msg.fw);
+	return FAIL;
+}
+
+static u8 gup_burn_proc(struct i2c_client *client, u8 *burn_buf,
+		u16 start_addr, u16 total_length)
+{
+	s32 ret = 0;
+	u16 burn_addr = start_addr;
+	u16 frame_length = 0;
+	u16 burn_length = 0;
+	u8 wr_buf[PACK_SIZE + GTP_ADDR_LENGTH];
+	u8 rd_buf[PACK_SIZE + GTP_ADDR_LENGTH];
+	u8 retry = 0;
+
+	dev_dbg(&client->dev, "Begin burn %dk data to addr 0x%x",
+		total_length / 1024, start_addr);
+	while (burn_length < total_length) {
+		dev_dbg(&client->dev,
+			"B/T:%04d/%04d", burn_length, total_length);
+		frame_length = ((total_length - burn_length)
+		> PACK_SIZE) ? PACK_SIZE : (total_length - burn_length);
+		wr_buf[0] = (u8)(burn_addr>>8);
+		rd_buf[0] = wr_buf[0];
+		wr_buf[1] = (u8)burn_addr;
+		rd_buf[1] = wr_buf[1];
+		memcpy(&wr_buf[GTP_ADDR_LENGTH],
+		&burn_buf[burn_length], frame_length);
+
+		for (retry = 0; retry < MAX_FRAME_CHECK_TIME; retry++) {
+			ret = gtp_i2c_write(client,
+			wr_buf, GTP_ADDR_LENGTH + frame_length);
+			if (ret <= 0) {
+				dev_err(&client->dev,
+					"Write frame data i2c error.");
+				continue;
+			}
+			ret = gtp_i2c_read(client, rd_buf,
+					   GTP_ADDR_LENGTH + frame_length);
+			if (ret <= 0) {
+				dev_err(&client->dev,
+					"Read back frame data i2c error.");
+				continue;
+			}
+			if (memcmp(&wr_buf[GTP_ADDR_LENGTH],
+				&rd_buf[GTP_ADDR_LENGTH], frame_length)) {
+				dev_err(&client->dev,
+					"Check frame data fail,not equal.");
+				dev_dbg(&client->dev, "write array:");
+				GTP_DEBUG_ARRAY(&wr_buf[GTP_ADDR_LENGTH],
+				frame_length);
+				dev_dbg(&client->dev, "read array:");
+				GTP_DEBUG_ARRAY(&rd_buf[GTP_ADDR_LENGTH],
+				frame_length);
+				continue;
+			} else {
+				/* dev_dbg(&client->dev,
+				 * "Check frame data success.");
+				 */
+				break;
+			}
+		}
+		if (retry >= MAX_FRAME_CHECK_TIME) {
+			dev_err(&client->dev,
+				"Burn frame data time out,exit.");
+			return FAIL;
+		}
+		burn_length += frame_length;
+		burn_addr += frame_length;
+	}
+
+	return SUCCESS;
+}
+
+static u8 gup_load_section_file(u8 *buf, u32 offset, u16 length, u8 set_or_end)
+{
+	if (!update_msg.fw_data ||
+	    update_msg.fw_total_len < FW_HEAD_LENGTH + offset + length) {
+		pr_err("<<-GTP->> cannot load section data. fw_len=%d read end=%d\n",
+		update_msg.fw_total_len,
+		FW_HEAD_LENGTH + offset + length);
+		return FAIL;
+	}
+
+
+	if (SEEK_SET == set_or_end) {
+		memcpy(buf, &update_msg.fw_data[FW_HEAD_LENGTH + offset],
+		       length);
+	} else {
+		/* seek end */
+		memcpy(buf, &update_msg.fw_data[update_msg.fw_total_len +
+		       FW_HEAD_LENGTH - offset], length);
+	}
+
+	return SUCCESS;
+}
+
+static u8 gup_recall_check(struct i2c_client *client, u8 *chk_src,
+			   u16 start_rd_addr, u16 chk_length)
+{
+	u8 rd_buf[PACK_SIZE + GTP_ADDR_LENGTH];
+	s32 ret = 0;
+	u16 recall_addr = start_rd_addr;
+	u16 recall_length = 0;
+	u16 frame_length = 0;
+
+	while (recall_length < chk_length) {
+		frame_length = ((chk_length - recall_length)
+				> PACK_SIZE) ? PACK_SIZE :
+				(chk_length - recall_length);
+		ret = gup_get_ic_msg(client, recall_addr, rd_buf, frame_length);
+		if (ret <= 0) {
+			dev_err(&client->dev, "recall i2c error,exit");
+			return FAIL;
+		}
+
+		if (memcmp(&rd_buf[GTP_ADDR_LENGTH],
+		&chk_src[recall_length], frame_length)) {
+			dev_err(&client->dev, "Recall frame data fail,not equal.");
+			dev_dbg(&client->dev, "chk_src array:");
+			GTP_DEBUG_ARRAY(&chk_src[recall_length], frame_length);
+			dev_dbg(&client->dev, "recall array:");
+			GTP_DEBUG_ARRAY(&rd_buf[GTP_ADDR_LENGTH], frame_length);
+			return FAIL;
+		}
+
+		recall_length += frame_length;
+		recall_addr += frame_length;
+	}
+	dev_dbg(&client->dev,
+			"Recall check %dk firmware success.",
+			(chk_length/1024));
+
+	return SUCCESS;
+}
+
+static u8 gup_burn_fw_section(struct i2c_client *client, u8 *fw_section,
+			      u16 start_addr, u8 bank_cmd)
+{
+	s32 ret = 0;
+	u8	rd_buf[5];
+
+	/* step1:hold ss51 & dsp */
+	ret = gup_set_ic_msg(client, _rRW_MISCTL__SWRST_B0_, 0x0C);
+	if (ret <= 0) {
+		dev_err(&client->dev, "[burn_fw_section]hold ss51 & dsp fail.");
+		return FAIL;
+	}
+
+	/* step2:set scramble */
+	ret = gup_set_ic_msg(client, _rRW_MISCTL__BOOT_OPT_B0_, 0x00);
+	if (ret <= 0) {
+		dev_err(&client->dev, "[burn_fw_section]set scramble fail.");
+		return FAIL;
+	}
+
+	/* step3:select bank */
+	ret = gup_set_ic_msg(client, _bRW_MISCTL__SRAM_BANK,
+	(bank_cmd >> 4)&0x0F);
+	if (ret <= 0) {
+		dev_err(&client->dev,
+			"[burn_fw_section]select bank %d fail.",
+			(bank_cmd >> 4)&0x0F);
+		return FAIL;
+	}
+
+	/* step4:enable accessing code */
+	ret = gup_set_ic_msg(client, _bRW_MISCTL__MEM_CD_EN, 0x01);
+	if (ret <= 0) {
+		dev_err(&client->dev,
+			"[burn_fw_section]enable accessing code fail.");
+		return FAIL;
+	}
+
+	/* step5:burn 8k fw section */
+	ret = gup_burn_proc(client, fw_section, start_addr, FW_SECTION_LENGTH);
+	if (FAIL == ret) {
+		dev_err(&client->dev,
+			"[burn_fw_section]burn fw_section fail.");
+		return FAIL;
+	}
+
+	/* step6:hold ss51 & release dsp */
+	ret = gup_set_ic_msg(client, _rRW_MISCTL__SWRST_B0_, 0x04);
+	if (ret <= 0) {
+		dev_err(&client->dev,
+			"[burn_fw_section]hold ss51 & release dsp fail.");
+		return FAIL;
+	}
+	/* must delay */
+	usleep_range(1000, 2000);
+
+	/* step7:send burn cmd to move data to flash from sram */
+	ret = gup_set_ic_msg(client, _rRW_MISCTL__BOOT_CTL_, bank_cmd&0x0f);
+	if (ret <= 0) {
+		dev_err(&client->dev, "[burn_fw_section]send burn cmd fail.");
+		return FAIL;
+	}
+	dev_dbg(&client->dev,
+		"[burn_fw_section]Wait for the burn is complete......");
+	do {
+		ret = gup_get_ic_msg(client, _rRW_MISCTL__BOOT_CTL_, rd_buf, 1);
+		if (ret <= 0) {
+			dev_err(&client->dev,
+				"[burn_fw_section]Get burn state fail");
+			return FAIL;
+		}
+		usleep_range(10000, 11000);
+	/* dev_dbg(&client->dev, "[burn_fw_section]Get burn state:%d.",
+	 * rd_buf[GTP_ADDR_LENGTH]);
+	 */
+	} while (rd_buf[GTP_ADDR_LENGTH]);
+
+	/* step8:select bank */
+	ret = gup_set_ic_msg(client,
+			     _bRW_MISCTL__SRAM_BANK, (bank_cmd >> 4) & 0x0F);
+	if (ret <= 0) {
+		dev_err(&client->dev,
+			"[burn_fw_section]select bank %d fail.",
+			(bank_cmd >> 4)&0x0F);
+		return FAIL;
+	}
+
+	/* step9:enable accessing code */
+	ret = gup_set_ic_msg(client, _bRW_MISCTL__MEM_CD_EN, 0x01);
+	if (ret <= 0) {
+		dev_err(&client->dev,
+			"[burn_fw_section]enable accessing code fail.");
+		return FAIL;
+	}
+
+	/* step10:recall 8k fw section */
+	ret = gup_recall_check(client,
+	fw_section, start_addr, FW_SECTION_LENGTH);
+	if (FAIL == ret) {
+		dev_err(&client->dev,
+			"[burn_fw_section]recall check %dk firmware fail.",
+			FW_SECTION_LENGTH / 1024);
+		return FAIL;
+	}
+
+	/* step11:disable accessing code */
+	ret = gup_set_ic_msg(client, _bRW_MISCTL__MEM_CD_EN, 0x00);
+	if (ret <= 0) {
+		dev_err(&client->dev,
+			"[burn_fw_section]disable accessing code fail.");
+		return FAIL;
+	}
+
+	return SUCCESS;
+}
+
+static u8 gup_burn_dsp_isp(struct i2c_client *client)
+{
+	s32 ret = 0;
+	u8 *fw_dsp_isp = NULL;
+	u8	retry = 0;
+
+	dev_info(&client->dev, "[burn_dsp_isp]Begin burn dsp isp---->>");
+
+	/* step1:alloc memory */
+	dev_dbg(&client->dev, "[burn_dsp_isp]step1:alloc memory");
+	while (retry++ < 5) {
+		fw_dsp_isp = kzalloc(FW_DSP_ISP_LENGTH, GFP_KERNEL);
+		if (fw_dsp_isp == NULL) {
+			continue;
+		} else {
+			dev_info(&client->dev,
+				"[burn_dsp_isp]Alloc %dk byte memory success.",
+				FW_DSP_ISP_LENGTH / 1024);
+			break;
+		}
+	}
+	if (retry >= 5) {
+		dev_err(&client->dev, "[burn_dsp_isp]Alloc memory fail,exit.");
+		return FAIL;
+	}
+
+	/* step2:load dsp isp file data */
+	dev_dbg(&client->dev, "[burn_dsp_isp]step2:load dsp isp file data");
+	ret = gup_load_section_file(fw_dsp_isp,
+	FW_DSP_ISP_LENGTH, FW_DSP_ISP_LENGTH, SEEK_END);
+	if (FAIL == ret) {
+		dev_err(&client->dev,
+			"[burn_dsp_isp]load firmware dsp_isp fail.");
+		goto exit_burn_dsp_isp;
+	}
+
+	/* step3:disable wdt,clear cache enable */
+	dev_dbg(&client->dev,
+		"[burn_dsp_isp]step3:disable wdt,clear cache enable");
+	ret = gup_set_ic_msg(client, _bRW_MISCTL__TMR0_EN, 0x00);
+	if (ret <= 0) {
+		dev_err(&client->dev, "[burn_dsp_isp]disable wdt fail.");
+		ret = FAIL;
+		goto exit_burn_dsp_isp;
+	}
+	ret = gup_set_ic_msg(client, _bRW_MISCTL__CACHE_EN, 0x00);
+	if (ret <= 0) {
+		dev_err(&client->dev,
+			"[burn_dsp_isp]clear cache enable fail.");
+		ret = FAIL;
+		goto exit_burn_dsp_isp;
+	}
+
+	/* step4:hold ss51 & dsp */
+	dev_dbg(&client->dev, "[burn_dsp_isp]step4:hold ss51 & dsp");
+	ret = gup_set_ic_msg(client, _rRW_MISCTL__SWRST_B0_, 0x0C);
+	if (ret <= 0) {
+		dev_err(&client->dev, "[burn_dsp_isp]hold ss51 & dsp fail.");
+		ret = FAIL;
+		goto exit_burn_dsp_isp;
+	}
+
+	/* step5:set boot from sram */
+	dev_dbg(&client->dev, "[burn_dsp_isp]step5:set boot from sram");
+	ret = gup_set_ic_msg(client, _rRW_MISCTL__BOOTCTL_B0_, 0x02);
+	if (ret <= 0) {
+		dev_err(&client->dev, "[burn_dsp_isp]set boot from sram fail");
+		ret = FAIL;
+		goto exit_burn_dsp_isp;
+	}
+
+	/* step6:software reboot */
+	dev_dbg(&client->dev, "[burn_dsp_isp]step6:software reboot");
+	ret = gup_set_ic_msg(client, _bWO_MISCTL__CPU_SWRST_PULSE, 0x01);
+	if (ret <= 0) {
+		dev_err(&client->dev, "[burn_dsp_isp]software reboot fail.");
+		ret = FAIL;
+		goto exit_burn_dsp_isp;
+	}
+
+	/* step7:select bank2 */
+	dev_dbg(&client->dev, "[burn_dsp_isp]step7:select bank2");
+	ret = gup_set_ic_msg(client, _bRW_MISCTL__SRAM_BANK, 0x02);
+	if (ret <= 0) {
+		dev_err(&client->dev, "[burn_dsp_isp]select bank2 fail");
+		ret = FAIL;
+		goto exit_burn_dsp_isp;
+	}
+
+	/* step8:enable accessing code */
+	dev_dbg(&client->dev, "[burn_dsp_isp]step8:enable accessing code");
+	ret = gup_set_ic_msg(client, _bRW_MISCTL__MEM_CD_EN, 0x01);
+	if (ret <= 0) {
+		dev_err(&client->dev,
+			"[burn_dsp_isp]enable accessing code fail.");
+		ret = FAIL;
+		goto exit_burn_dsp_isp;
+	}
+
+	/* step9:burn 4k dsp_isp */
+	dev_dbg(&client->dev, "[burn_dsp_isp]step9:burn 4k dsp_isp");
+	ret = gup_burn_proc(client, fw_dsp_isp, 0xC000, FW_DSP_ISP_LENGTH);
+	if (FAIL == ret) {
+		dev_err(&client->dev, "[burn_dsp_isp]burn dsp_isp fail.");
+		goto exit_burn_dsp_isp;
+	}
+
+	/* step10:set scramble */
+	dev_dbg(&client->dev, "[burn_dsp_isp]step10:set scramble");
+	ret = gup_set_ic_msg(client, _rRW_MISCTL__BOOT_OPT_B0_, 0x00);
+	if (ret <= 0) {
+		dev_err(&client->dev, "[burn_dsp_isp]set scramble fail.");
+		ret = FAIL;
+		goto exit_burn_dsp_isp;
+	}
+	update_msg.fw_burned_len += FW_DSP_ISP_LENGTH;
+	dev_dbg(&client->dev, "[burn_dsp_isp]Burned length:%d",
+			update_msg.fw_burned_len);
+	ret = SUCCESS;
+
+exit_burn_dsp_isp:
+	kfree(fw_dsp_isp);
+
+	return ret;
+}
+
+static u8 gup_burn_fw_ss51(struct i2c_client *client)
+{
+	u8 *fw_ss51 = NULL;
+	u8	retry = 0;
+	s32 ret = 0;
+
+	dev_info(&client->dev, "[burn_fw_ss51]Begin burn ss51 firmware---->>");
+
+	/* step1:alloc memory */
+	dev_dbg(&client->dev, "[burn_fw_ss51]step1:alloc memory");
+	while (retry++ < 5) {
+		fw_ss51 = kzalloc(FW_SECTION_LENGTH, GFP_KERNEL);
+		if (fw_ss51 == NULL) {
+			continue;
+		} else {
+			dev_dbg(&client->dev,
+				"[burn_fw_ss51]Alloc %dk byte memory success.",
+				(FW_SECTION_LENGTH / 1024));
+			break;
+		}
+	}
+	if (retry >= 5) {
+		dev_err(&client->dev, "[burn_fw_ss51]Alloc memory fail,exit.");
+		return FAIL;
+	}
+
+	dev_info(&client->dev, "[burn_fw_ss51]Reset first 8K of ss51 to 0xFF.");
+	dev_dbg(&client->dev, "[burn_fw_ss51]step2: reset bank0 0xC000~0xD000");
+	memset(fw_ss51, 0xFF, FW_SECTION_LENGTH);
+
+	/* step3:clear control flag */
+	dev_dbg(&client->dev, "[burn_fw_ss51]step3:clear control flag");
+	ret = gup_set_ic_msg(client, _rRW_MISCTL__BOOT_CTL_, 0x00);
+	if (ret <= 0) {
+		dev_err(&client->dev, "[burn_fw_ss51]clear control flag fail.");
+		ret = FAIL;
+		goto exit_burn_fw_ss51;
+	}
+
+	/* step4:burn ss51 firmware section 1 */
+	dev_dbg(&client->dev,
+		"[burn_fw_ss51]step4:burn ss51 firmware section 1");
+	ret = gup_burn_fw_section(client, fw_ss51, 0xC000, 0x01);
+	if (FAIL == ret) {
+		dev_err(&client->dev,
+			"[burn_fw_ss51]burn ss51 firmware section 1 fail.");
+		goto exit_burn_fw_ss51;
+	}
+
+	/* step5:load ss51 firmware section 2 file data */
+	dev_dbg(&client->dev,
+		"[burn_fw_ss51]step5:load ss51 firmware section 2 file data");
+	ret = gup_load_section_file(fw_ss51,
+	FW_SECTION_LENGTH, FW_SECTION_LENGTH, SEEK_SET);
+	if (FAIL == ret) {
+		dev_err(&client->dev,
+			"[burn_fw_ss51]load ss51 firmware section 2 fail.");
+		goto exit_burn_fw_ss51;
+	}
+
+	/* step6:burn ss51 firmware section 2 */
+	dev_dbg(&client->dev,
+		"[burn_fw_ss51]step6:burn ss51 firmware section 2");
+	ret = gup_burn_fw_section(client, fw_ss51, 0xE000, 0x02);
+	if (FAIL == ret) {
+		dev_err(&client->dev,
+			"[burn_fw_ss51]burn ss51 firmware section 2 fail.");
+		goto exit_burn_fw_ss51;
+	}
+
+	/* step7:load ss51 firmware section 3 file data */
+	dev_dbg(&client->dev,
+		"[burn_fw_ss51]step7:load ss51 firmware section 3 file data");
+	ret = gup_load_section_file(fw_ss51,
+	2 * FW_SECTION_LENGTH, FW_SECTION_LENGTH, SEEK_SET);
+	if (FAIL == ret) {
+		dev_err(&client->dev,
+			"[burn_fw_ss51]load ss51 firmware section 3 fail.");
+		goto exit_burn_fw_ss51;
+	}
+
+	/* step8:burn ss51 firmware section 3 */
+	dev_dbg(&client->dev,
+		"[burn_fw_ss51]step8:burn ss51 firmware section 3");
+	ret = gup_burn_fw_section(client, fw_ss51, 0xC000, 0x13);
+	if (FAIL == ret) {
+		dev_err(&client->dev,
+			"[burn_fw_ss51]burn ss51 firmware section 3 fail.");
+		goto exit_burn_fw_ss51;
+	}
+
+	/* step9:load ss51 firmware section 4 file data */
+	dev_dbg(&client->dev,
+		"[burn_fw_ss51]step9:load ss51 firmware section 4 file data");
+	ret = gup_load_section_file(fw_ss51,
+	3 * FW_SECTION_LENGTH, FW_SECTION_LENGTH, SEEK_SET);
+	if (FAIL == ret) {
+		dev_err(&client->dev,
+			"[burn_fw_ss51]load ss51 firmware section 4 fail.");
+		goto exit_burn_fw_ss51;
+	}
+
+	/* step10:burn ss51 firmware section 4 */
+	dev_dbg(&client->dev,
+		"[burn_fw_ss51]step10:burn ss51 firmware section 4");
+	ret = gup_burn_fw_section(client, fw_ss51, 0xE000, 0x14);
+	if (FAIL == ret) {
+		dev_err(&client->dev,
+			"[burn_fw_ss51]burn ss51 firmware section 4 fail.");
+		goto exit_burn_fw_ss51;
+	}
+
+	update_msg.fw_burned_len += (FW_SECTION_LENGTH*4);
+	dev_dbg(&client->dev, "[burn_fw_ss51]Burned length:%d",
+		update_msg.fw_burned_len);
+	ret = SUCCESS;
+
+exit_burn_fw_ss51:
+	kfree(fw_ss51);
+	return ret;
+}
+
+static u8 gup_burn_fw_dsp(struct i2c_client *client)
+{
+	s32 ret = 0;
+	u8 *fw_dsp = NULL;
+	u8 retry = 0;
+	u8 rd_buf[5];
+
+	dev_info(&client->dev, "[burn_fw_dsp]Begin burn dsp firmware---->>");
+	/* step1:alloc memory */
+	dev_dbg(&client->dev, "[burn_fw_dsp]step1:alloc memory");
+	while (retry++ < 5) {
+		fw_dsp = kzalloc(FW_DSP_LENGTH, GFP_KERNEL);
+		if (fw_dsp == NULL) {
+			continue;
+		} else {
+			dev_dbg(&client->dev,
+				"[burn_fw_dsp]Alloc %dk byte memory success.",
+				FW_SECTION_LENGTH / 1024);
+			break;
+		}
+	}
+	if (retry >= 5) {
+		dev_err(&client->dev, "[burn_fw_dsp]Alloc memory fail,exit.");
+		return FAIL;
+	}
+
+	/* step2:load firmware dsp */
+	dev_dbg(&client->dev, "[burn_fw_dsp]step2:load firmware dsp");
+	ret = gup_load_section_file(fw_dsp,
+	4 * FW_SECTION_LENGTH, FW_DSP_LENGTH, SEEK_SET);
+	if (FAIL == ret) {
+		dev_err(&client->dev, "[burn_fw_dsp]load firmware dsp fail.");
+		goto exit_burn_fw_dsp;
+	}
+
+	/* step3:select bank3 */
+	dev_dbg(&client->dev, "[burn_fw_dsp]step3:select bank3");
+	ret = gup_set_ic_msg(client, _bRW_MISCTL__SRAM_BANK, 0x03);
+	if (ret <= 0) {
+		dev_err(&client->dev, "[burn_fw_dsp]select bank3 fail.");
+		ret = FAIL;
+		goto exit_burn_fw_dsp;
+	}
+
+	/* step4:hold ss51 & dsp */
+	dev_dbg(&client->dev, "[burn_fw_dsp]step4:hold ss51 & dsp");
+	ret = gup_set_ic_msg(client, _rRW_MISCTL__SWRST_B0_, 0x0C);
+	if (ret <= 0) {
+		dev_err(&client->dev, "[burn_fw_dsp]hold ss51 & dsp fail.");
+		ret = FAIL;
+		goto exit_burn_fw_dsp;
+	}
+
+	/* step5:set scramble */
+	dev_dbg(&client->dev, "[burn_fw_dsp]step5:set scramble");
+	ret = gup_set_ic_msg(client, _rRW_MISCTL__BOOT_OPT_B0_, 0x00);
+	if (ret <= 0) {
+		dev_err(&client->dev, "[burn_fw_dsp]set scramble fail.");
+		ret = FAIL;
+		goto exit_burn_fw_dsp;
+	}
+
+	/* step6:release ss51 & dsp */
+	dev_dbg(&client->dev, "[burn_fw_dsp]step6:release ss51 & dsp");
+	ret = gup_set_ic_msg(
+	client, _rRW_MISCTL__SWRST_B0_, 0x04);/* 20121211 */
+	if (ret <= 0) {
+		dev_err(&client->dev, "[burn_fw_dsp]release ss51 & dsp fail.");
+		ret = FAIL;
+		goto exit_burn_fw_dsp;
+	}
+	/* must delay */
+	usleep_range(1000, 1100);
+
+	/* step7:burn 4k dsp firmware */
+	dev_dbg(&client->dev, "[burn_fw_dsp]step7:burn 4k dsp firmware");
+	ret = gup_burn_proc(client, fw_dsp, 0x9000, FW_DSP_LENGTH);
+	if (FAIL == ret) {
+		dev_err(&client->dev, "[burn_fw_dsp]burn fw_section fail.");
+		goto exit_burn_fw_dsp;
+	}
+
+	/* step8:send burn cmd to move data to flash from sram */
+	dev_dbg(&client->dev,
+	"[burn_fw_dsp]step8:send burn cmd to move data to flash from sram");
+	ret = gup_set_ic_msg(client, _rRW_MISCTL__BOOT_CTL_, 0x05);
+	if (ret <= 0) {
+		dev_err(&client->dev, "[burn_fw_dsp]send burn cmd fail.");
+		goto exit_burn_fw_dsp;
+	}
+	dev_dbg(&client->dev, "[burn_fw_dsp]Wait for the burn is complete......");
+	do {
+		ret = gup_get_ic_msg(client, _rRW_MISCTL__BOOT_CTL_, rd_buf, 1);
+		if (ret <= 0) {
+			dev_err(&client->dev, "[burn_fw_dsp]Get burn state fail");
+			goto exit_burn_fw_dsp;
+		}
+		usleep_range(10000, 11000);
+	/* dev_dbg(&client->dev, "[burn_fw_dsp]Get burn state:%d.",
+	rd_buf[GTP_ADDR_LENGTH]); */
+	} while (rd_buf[GTP_ADDR_LENGTH]);
+
+	/* step9:recall check 4k dsp firmware */
+	dev_dbg(&client->dev,
+		"[burn_fw_dsp]step9:recall check 4k dsp firmware");
+	ret = gup_recall_check(client, fw_dsp, 0x9000, FW_DSP_LENGTH);
+	if (FAIL == ret) {
+		dev_err(&client->dev,
+			"[burn_fw_dsp]recall check 4k dsp firmware fail.");
+		goto exit_burn_fw_dsp;
+	}
+
+	update_msg.fw_burned_len += FW_DSP_LENGTH;
+	dev_dbg(&client->dev, "[burn_fw_dsp]Burned length:%d",
+			update_msg.fw_burned_len);
+	ret = SUCCESS;
+
+exit_burn_fw_dsp:
+	kfree(fw_dsp);
+
+	return ret;
+}
+
+static u8 gup_burn_fw_boot(struct i2c_client *client)
+{
+	s32 ret = 0;
+	u8 *fw_boot = NULL;
+	u8	retry = 0;
+	u8	rd_buf[5];
+
+	dev_info(&client->dev,
+		 "[burn_fw_boot]Begin burn bootloader firmware---->>");
+
+	/* step1:Alloc memory */
+	dev_dbg(&client->dev, "[burn_fw_boot]step1:Alloc memory");
+	while (retry++ < 5) {
+		fw_boot = kzalloc(FW_BOOT_LENGTH, GFP_KERNEL);
+		if (fw_boot == NULL) {
+			continue;
+		} else {
+			dev_dbg(&client->dev,
+				"[burn_fw_boot]Alloc %dk byte memory success.",
+				FW_BOOT_LENGTH / 1024);
+			break;
+		}
+	}
+	if (retry >= 5) {
+		dev_err(&client->dev, "[burn_fw_boot]Alloc memory fail,exit.");
+		return FAIL;
+	}
+
+	/* step2:load firmware bootloader */
+	dev_dbg(&client->dev, "[burn_fw_boot]step2:load firmware bootloader");
+	ret = gup_load_section_file(fw_boot,
+	(4 * FW_SECTION_LENGTH + FW_DSP_LENGTH), FW_BOOT_LENGTH, SEEK_SET);
+	if (FAIL == ret) {
+		dev_err(&client->dev,
+			"[burn_fw_boot]load firmware bootcode fail.");
+		goto exit_burn_fw_boot;
+	}
+
+	/* step3:hold ss51 & dsp */
+	dev_dbg(&client->dev, "[burn_fw_boot]step3:hold ss51 & dsp");
+	ret = gup_set_ic_msg(client, _rRW_MISCTL__SWRST_B0_, 0x0C);
+	if (ret <= 0) {
+		dev_err(&client->dev, "[burn_fw_boot]hold ss51 & dsp fail.");
+		ret = FAIL;
+		goto exit_burn_fw_boot;
+	}
+
+	/* step4:set scramble */
+	dev_dbg(&client->dev, "[burn_fw_boot]step4:set scramble");
+	ret = gup_set_ic_msg(client, _rRW_MISCTL__BOOT_OPT_B0_, 0x00);
+	if (ret <= 0) {
+		dev_err(&client->dev, "[burn_fw_boot]set scramble fail.");
+		ret = FAIL;
+		goto exit_burn_fw_boot;
+	}
+
+	/* step5:hold ss51 & release dsp */
+	dev_dbg(&client->dev, "[burn_fw_boot]step5:hold ss51 & release dsp");
+	ret = gup_set_ic_msg(client, _rRW_MISCTL__SWRST_B0_, 0x04);
+	/* 20121211 */
+	if (ret <= 0) {
+		dev_err(&client->dev, "[burn_fw_boot]release ss51 & dsp fail");
+		ret = FAIL;
+		goto exit_burn_fw_boot;
+	}
+	/* must delay */
+	usleep_range(1000, 1100);
+
+	/* step6:select bank3 */
+	dev_dbg(&client->dev, "[burn_fw_boot]step6:select bank3");
+	ret = gup_set_ic_msg(client, _bRW_MISCTL__SRAM_BANK, 0x03);
+	if (ret <= 0) {
+		dev_err(&client->dev, "[burn_fw_boot]select bank3 fail.");
+		ret = FAIL;
+		goto exit_burn_fw_boot;
+	}
+
+	/* step6:burn 2k bootloader firmware */
+	dev_dbg(&client->dev,
+		"[burn_fw_boot]step6:burn 2k bootloader firmware");
+	ret = gup_burn_proc(client, fw_boot, 0x9000, FW_BOOT_LENGTH);
+	if (FAIL == ret) {
+		dev_err(&client->dev, "[burn_fw_boot]burn fw_boot fail.");
+		goto exit_burn_fw_boot;
+	}
+
+	/* step7:send burn cmd to move data to flash from sram */
+	dev_dbg(&client->dev,
+	"[burn_fw_boot]step7:send burn cmd to move data to flash from sram");
+	ret = gup_set_ic_msg(client, _rRW_MISCTL__BOOT_CTL_, 0x06);
+	if (ret <= 0) {
+		dev_err(&client->dev, "[burn_fw_boot]send burn cmd fail.");
+		goto exit_burn_fw_boot;
+	}
+	dev_dbg(&client->dev,
+		"[burn_fw_boot]Wait for the burn is complete......");
+	do {
+		ret = gup_get_ic_msg(client, _rRW_MISCTL__BOOT_CTL_, rd_buf, 1);
+		if (ret <= 0) {
+			dev_err(&client->dev,
+				"[burn_fw_boot]Get burn state fail");
+			goto exit_burn_fw_boot;
+		}
+		usleep_range(10000, 11000);
+	/* dev_dbg(&client->dev, "[burn_fw_boot]Get burn state:%d.",
+	 * rd_buf[GTP_ADDR_LENGTH]);
+	 */
+	} while (rd_buf[GTP_ADDR_LENGTH]);
+
+	/* step8:recall check 2k bootloader firmware */
+	dev_dbg(&client->dev,
+		"[burn_fw_boot]step8:recall check 2k bootloader firmware");
+	ret = gup_recall_check(client, fw_boot, 0x9000, FW_BOOT_LENGTH);
+	if (FAIL == ret) {
+		dev_err(&client->dev,
+			"[burn_fw_boot]recall check 2k bootcode firmware fail");
+		goto exit_burn_fw_boot;
+	}
+
+	update_msg.fw_burned_len += FW_BOOT_LENGTH;
+	dev_dbg(&client->dev, "[burn_fw_boot]Burned length:%d",
+		update_msg.fw_burned_len);
+	ret = SUCCESS;
+
+exit_burn_fw_boot:
+	kfree(fw_boot);
+
+	return ret;
+}
+static u8 gup_burn_fw_boot_isp(struct i2c_client *client)
+{
+	s32 ret = 0;
+	u8 *fw_boot_isp = NULL;
+	u8	retry = 0;
+	u8	rd_buf[5];
+
+	if (update_msg.fw_burned_len >= update_msg.fw_total_len) {
+		dev_dbg(&client->dev, "No need to upgrade the boot_isp code!");
+		return SUCCESS;
+	}
+	dev_info(&client->dev,
+		"[burn_fw_boot_isp]Begin burn boot_isp firmware---->>");
+
+	/* step1:Alloc memory */
+	dev_dbg(&client->dev, "[burn_fw_boot_isp]step1:Alloc memory");
+	while (retry++ < 5) {
+		fw_boot_isp = kzalloc(FW_BOOT_ISP_LENGTH, GFP_KERNEL);
+		if (fw_boot_isp == NULL) {
+			continue;
+		} else {
+			dev_dbg(&client->dev,
+				"[burn_fw_boot_isp]Alloc %dk byte memory success.",
+				(FW_BOOT_ISP_LENGTH/1024));
+			break;
+		}
+	}
+	if (retry >= 5) {
+		dev_err(&client->dev,
+			"[burn_fw_boot_isp]Alloc memory fail,exit.");
+		return FAIL;
+	}
+
+	/* step2:load firmware bootloader */
+	dev_dbg(&client->dev,
+		"[burn_fw_boot_isp]step2:load firmware bootloader isp");
+	/* ret = gup_load_section_file(fw_boot_isp,
+	 * (4*FW_SECTION_LENGTH+FW_DSP_LENGTH +
+	 * FW_BOOT_LENGTH+FW_DSP_ISP_LENGTH), FW_BOOT_ISP_LENGTH, SEEK_SET);
+	 */
+	ret = gup_load_section_file(fw_boot_isp,
+	(update_msg.fw_burned_len - FW_DSP_ISP_LENGTH),
+	FW_BOOT_ISP_LENGTH, SEEK_SET);
+	if (FAIL == ret) {
+		dev_err(&client->dev,
+			"[burn_fw_boot_isp]load firmware boot_isp fail.");
+		goto exit_burn_fw_boot_isp;
+	}
+
+	/* step3:hold ss51 & dsp */
+	dev_dbg(&client->dev, "[burn_fw_boot_isp]step3:hold ss51 & dsp");
+	ret = gup_set_ic_msg(client, _rRW_MISCTL__SWRST_B0_, 0x0C);
+	if (ret <= 0) {
+		dev_err(&client->dev, "[burn_fw_boot_isp]hold ss51 & dsp fail");
+		ret = FAIL;
+		goto exit_burn_fw_boot_isp;
+	}
+
+	/* step4:set scramble */
+	dev_dbg(&client->dev, "[burn_fw_boot_isp]step4:set scramble");
+	ret = gup_set_ic_msg(client, _rRW_MISCTL__BOOT_OPT_B0_, 0x00);
+	if (ret <= 0) {
+		dev_err(&client->dev, "[burn_fw_boot_isp]set scramble fail.");
+		ret = FAIL;
+		goto exit_burn_fw_boot_isp;
+	}
+
+
+	/* step5:hold ss51 & release dsp */
+	dev_dbg(&client->dev,
+		"[burn_fw_boot_isp]step5:hold ss51 & release dsp");
+	ret = gup_set_ic_msg(client, _rRW_MISCTL__SWRST_B0_, 0x04);
+	/* 20121211 */
+	if (ret <= 0) {
+		dev_err(&client->dev,
+			"[burn_fw_boot_isp]release ss51 & dsp fail.");
+		ret = FAIL;
+		goto exit_burn_fw_boot_isp;
+	}
+	/* must delay */
+	usleep_range(1000, 2000);
+
+	/* step6:select bank3 */
+	dev_dbg(&client->dev, "[burn_fw_boot_isp]step6:select bank3");
+	ret = gup_set_ic_msg(client, _bRW_MISCTL__SRAM_BANK, 0x03);
+	if (ret <= 0) {
+		dev_err(&client->dev, "[burn_fw_boot_isp]select bank3 fail.");
+		ret = FAIL;
+		goto exit_burn_fw_boot_isp;
+	}
+
+	/* step7:burn 2k bootload_isp firmware */
+	dev_dbg(&client->dev,
+		"[burn_fw_boot_isp]step7:burn 2k bootloader firmware");
+	ret = gup_burn_proc(client, fw_boot_isp, 0x9000, FW_BOOT_ISP_LENGTH);
+	if (FAIL == ret) {
+		dev_err(&client->dev,
+			"[burn_fw_boot_isp]burn fw_section fail.");
+		goto exit_burn_fw_boot_isp;
+	}
+
+	/* step7:send burn cmd to move data to flash from sram */
+	dev_dbg(&client->dev,
+	"[burn_fw_boot_isp]step8:send burn cmd to move data to flash from sram");
+	ret = gup_set_ic_msg(client, _rRW_MISCTL__BOOT_CTL_, 0x07);
+	if (ret <= 0) {
+		dev_err(&client->dev, "[burn_fw_boot_isp]send burn cmd fail.");
+		goto exit_burn_fw_boot_isp;
+	}
+	dev_dbg(&client->dev,
+		"[burn_fw_boot_isp]Wait for the burn is complete......");
+	do {
+		ret = gup_get_ic_msg(client, _rRW_MISCTL__BOOT_CTL_, rd_buf, 1);
+		if (ret <= 0) {
+			dev_err(&client->dev,
+				"[burn_fw_boot_isp]Get burn state fail");
+			goto exit_burn_fw_boot_isp;
+		}
+		usleep_range(10000, 11000);
+	/* dev_dbg(&client->dev, "[burn_fw_boot_isp]Get
+	 * burn state:%d.", rd_buf[GTP_ADDR_LENGTH]);
+	 */
+	} while (rd_buf[GTP_ADDR_LENGTH]);
+
+	/* step8:recall check 2k bootload_isp firmware */
+	dev_dbg(&client->dev,
+		"[burn_fw_boot_isp]step9:recall check 2k bootloader firmware");
+	ret = gup_recall_check(client, fw_boot_isp, 0x9000, FW_BOOT_ISP_LENGTH);
+	if (FAIL == ret) {
+		dev_err(&client->dev,
+		"[burn_fw_boot_isp]recall check 2k bootcode_isp firmware fail.");
+		goto exit_burn_fw_boot_isp;
+	}
+
+	update_msg.fw_burned_len += FW_BOOT_ISP_LENGTH;
+	dev_dbg(&client->dev,
+		"[burn_fw_boot_isp]Burned length:%d", update_msg.fw_burned_len);
+	ret = SUCCESS;
+
+exit_burn_fw_boot_isp:
+	kfree(fw_boot_isp);
+
+	return ret;
+}
+
+static u8 gup_burn_fw_link(struct i2c_client *client)
+{
+	u8 *fw_link = NULL;
+	u8	retry = 0;
+	s32 ret = 0;
+	u32 offset;
+
+	if (update_msg.fw_burned_len >= update_msg.fw_total_len) {
+		dev_dbg(&client->dev, "No need to upgrade the link code!");
+		return SUCCESS;
+	}
+	dev_info(&client->dev, "[burn_fw_link]Begin burn link firmware---->>");
+
+	/* step1:Alloc memory */
+	dev_dbg(&client->dev, "[burn_fw_link]step1:Alloc memory");
+	while (retry++ < 5) {
+		fw_link = kzalloc(FW_SECTION_LENGTH, GFP_KERNEL);
+		if (fw_link == NULL) {
+			continue;
+		} else {
+			dev_dbg(&client->dev,
+				"[burn_fw_link]Alloc %dk byte memory success.",
+				(FW_SECTION_LENGTH/1024));
+			break;
+		}
+	}
+	if (retry >= 5) {
+		dev_err(&client->dev, "[burn_fw_link]Alloc memory fail,exit.");
+		return FAIL;
+	}
+
+	/* step2:load firmware link section 1 */
+	dev_dbg(&client->dev,
+		"[burn_fw_link]step2:load firmware link section 1");
+	offset = update_msg.fw_burned_len - FW_DSP_ISP_LENGTH;
+	ret = gup_load_section_file(
+	fw_link, offset, FW_SECTION_LENGTH, SEEK_SET);
+	if (FAIL == ret) {
+		dev_err(&client->dev,
+			"[burn_fw_link]load firmware link section 1 fail.");
+		goto exit_burn_fw_link;
+	}
+
+	/* step3:burn link firmware section 1 */
+	dev_dbg(&client->dev,
+		"[burn_fw_link]step3:burn link firmware section 1");
+	ret = gup_burn_fw_gwake_section(
+	client, fw_link, 0x9000, FW_SECTION_LENGTH, 0x38);
+
+	if (FAIL == ret) {
+		dev_err(&client->dev,
+			"[burn_fw_link]burn link firmware section 1 fail.");
+		goto exit_burn_fw_link;
+	}
+
+	/* step4:load link firmware section 2 file data */
+	dev_dbg(&client->dev,
+		"[burn_fw_link]step4:load link firmware section 2 file data");
+	offset += FW_SECTION_LENGTH;
+	ret = gup_load_section_file(
+	fw_link, offset, FW_GLINK_LENGTH - FW_SECTION_LENGTH, SEEK_SET);
+
+	if (FAIL == ret) {
+		dev_err(&client->dev,
+			"[burn_fw_link]load link firmware section 2 fail.");
+		goto exit_burn_fw_link;
+	}
+
+	/* step5:burn link firmware section 2 */
+	dev_dbg(&client->dev,
+		"[burn_fw_link]step4:burn link firmware section 2");
+	ret = gup_burn_fw_gwake_section(client,
+	fw_link, 0x9000, FW_GLINK_LENGTH - FW_SECTION_LENGTH, 0x39);
+
+	if (FAIL == ret) {
+		dev_err(&client->dev,
+			"[burn_fw_link]burn link firmware section 2 fail.");
+		goto exit_burn_fw_link;
+	}
+
+	update_msg.fw_burned_len += FW_GLINK_LENGTH;
+	dev_dbg(&client->dev,
+		"[burn_fw_link]Burned length:%d", update_msg.fw_burned_len);
+	ret = SUCCESS;
+
+exit_burn_fw_link:
+	kfree(fw_link);
+
+	return ret;
+}
+
+static u8 gup_burn_fw_gwake_section(struct i2c_client *client,
+		u8 *fw_section, u16 start_addr, u32 len, u8 bank_cmd)
+{
+	s32 ret = 0;
+	u8	rd_buf[5];
+
+	/* step1:hold ss51 & dsp */
+	ret = gup_set_ic_msg(client, _rRW_MISCTL__SWRST_B0_, 0x0C);
+	if (ret <= 0) {
+		dev_err(&client->dev,
+			"[burn_fw_app_section]hold ss51 & dsp fail.");
+		return FAIL;
+	}
+
+	/* step2:set scramble */
+	ret = gup_set_ic_msg(client, _rRW_MISCTL__BOOT_OPT_B0_, 0x00);
+	if (ret <= 0) {
+		dev_err(&client->dev,
+			"[burn_fw_app_section]set scramble fail.");
+		return FAIL;
+	}
+
+	/* step3:hold ss51 & release dsp */
+	ret = gup_set_ic_msg(client, _rRW_MISCTL__SWRST_B0_, 0x04);
+	if (ret <= 0) {
+		dev_err(&client->dev,
+			"[burn_fw_app_section]hold ss51 & release dsp fail.");
+		return FAIL;
+	}
+	/* must delay */
+	usleep_range(1000, 2000);
+
+	/* step4:select bank */
+	ret = gup_set_ic_msg(
+	client, _bRW_MISCTL__SRAM_BANK, (bank_cmd >> 4)&0x0F);
+	if (ret <= 0) {
+		dev_err(&client->dev,
+			"[burn_fw_section]select bank %d fail.",
+			(bank_cmd >> 4)&0x0F);
+		return FAIL;
+	}
+
+	/* step5:burn fw section */
+	ret = gup_burn_proc(client, fw_section, start_addr, len);
+	if (FAIL == ret) {
+		dev_err(&client->dev,
+			"[burn_fw_app_section]burn fw_section fail.");
+		return FAIL;
+	}
+
+	/* step6:send burn cmd to move data to flash from sram */
+	ret = gup_set_ic_msg(client, _rRW_MISCTL__BOOT_CTL_, bank_cmd&0x0F);
+	if (ret <= 0) {
+		dev_err(&client->dev,
+			"[burn_fw_app_section]send burn cmd fail.");
+		return FAIL;
+	}
+	dev_dbg(&client->dev,
+		"[burn_fw_section]Wait for the burn is complete......");
+	do {
+		ret = gup_get_ic_msg(client, _rRW_MISCTL__BOOT_CTL_, rd_buf, 1);
+		if (ret <= 0) {
+			dev_err(&client->dev,
+				"[burn_fw_app_section]Get burn state fail");
+			return FAIL;
+		}
+		usleep_range(10000, 11000);
+	/* dev_dbg(&client->dev, "[burn_fw_app_section]Get burn state:%d."
+	 * rd_buf[GTP_ADDR_LENGTH]);
+	 */
+	} while (rd_buf[GTP_ADDR_LENGTH]);
+
+	/* step7:recall fw section */
+	ret = gup_recall_check(client, fw_section, start_addr, len);
+	if (FAIL == ret) {
+		dev_err(&client->dev,
+			"[burn_fw_app_section]recall check %dk firmware fail.",
+			len/1024);
+		return FAIL;
+	}
+
+	return SUCCESS;
+}
+
+static u8 gup_burn_fw_gwake(struct i2c_client *client)
+{
+	u8 *fw_gwake = NULL;
+	u8	retry = 0;
+	s32 ret = 0;
+	u16 start_index = 4*FW_SECTION_LENGTH +
+	FW_DSP_LENGTH + FW_BOOT_LENGTH +
+	FW_BOOT_ISP_LENGTH + FW_GLINK_LENGTH;/* 32 + 4 + 2 + 4 = 42K */
+	/* u16 start_index; */
+
+	if (start_index >= update_msg.fw_total_len) {
+		dev_dbg(&client->dev, "No need to upgrade the gwake code!");
+		return SUCCESS;
+	}
+	/* start_index = update_msg.fw_burned_len - FW_DSP_ISP_LENGTH; */
+	dev_info(&client->dev,
+		 "[burn_fw_gwake]Begin burn gwake firmware---->>");
+
+	/* step1:alloc memory */
+	dev_dbg(&client->dev, "[burn_fw_gwake]step1:alloc memory");
+	while (retry++ < 5) {
+		fw_gwake =
+	kzalloc(FW_SECTION_LENGTH, GFP_KERNEL);
+		if (fw_gwake == NULL) {
+			continue;
+		} else {
+			dev_dbg(&client->dev,
+				"[burn_fw_gwake]Alloc %dk byte memory success.",
+				(FW_SECTION_LENGTH/1024));
+			break;
+		}
+	}
+	if (retry >= 5) {
+		dev_err(&client->dev, "[burn_fw_gwake]Alloc memory fail,exit.");
+		return FAIL;
+	}
+
+	/* clear control flag */
+	ret = gup_set_ic_msg(client, _rRW_MISCTL__BOOT_CTL_, 0x00);
+	if (ret <= 0) {
+		dev_err(&client->dev,
+			"[burn_fw_finish]clear control flag fail.");
+		goto exit_burn_fw_gwake;
+	}
+
+	/* step2:load app_code firmware section 1 file data */
+	dev_dbg(&client->dev,
+		"[burn_fw_gwake]step2:load app_code firmware section 1 file data");
+	ret = gup_load_section_file(fw_gwake,
+	start_index, FW_SECTION_LENGTH, SEEK_SET);
+	if (FAIL == ret) {
+		dev_err(&client->dev,
+			"[burn_fw_gwake]load app_code firmware section 1 fail.");
+		goto exit_burn_fw_gwake;
+	}
+
+	/* step3:burn app_code firmware section 1 */
+	dev_dbg(&client->dev,
+		"[burn_fw_gwake]step3:burn app_code firmware section 1");
+	ret = gup_burn_fw_gwake_section(client,
+	fw_gwake, 0x9000, FW_SECTION_LENGTH, 0x3A);
+	if (FAIL == ret) {
+		dev_err(&client->dev,
+			"[burn_fw_gwake]burn app_code firmware section 1 fail.");
+		goto exit_burn_fw_gwake;
+	}
+
+	/* step5:load app_code firmware section 2 file data */
+	dev_dbg(&client->dev,
+		"[burn_fw_gwake]step5:load app_code firmware section 2 file data");
+	ret = gup_load_section_file(
+	fw_gwake, start_index+FW_SECTION_LENGTH, FW_SECTION_LENGTH, SEEK_SET);
+	if (FAIL == ret) {
+		dev_err(&client->dev,
+			"[burn_fw_gwake]load app_code firmware section 2 fail.");
+		goto exit_burn_fw_gwake;
+	}
+
+	/* step6:burn app_code firmware section 2 */
+	dev_dbg(&client->dev,
+		"[burn_fw_gwake]step6:burn app_code firmware section 2");
+	ret = gup_burn_fw_gwake_section(client,
+	fw_gwake, 0x9000, FW_SECTION_LENGTH, 0x3B);
+	if (FAIL == ret) {
+		dev_err(&client->dev,
+			"[burn_fw_gwake]burn app_code firmware section 2 fail.");
+		goto exit_burn_fw_gwake;
+	}
+
+	/* step7:load app_code firmware section 3 file data */
+	dev_dbg(&client->dev,
+		"[burn_fw_gwake]step7:load app_code firmware section 3 file data");
+	ret = gup_load_section_file(
+	fw_gwake, start_index + 2*FW_SECTION_LENGTH,
+	FW_SECTION_LENGTH, SEEK_SET);
+	if (FAIL == ret) {
+		dev_err(&client->dev,
+			"[burn_fw_gwake]load app_code firmware section 3 fail.");
+		goto exit_burn_fw_gwake;
+	}
+
+	/* step8:burn app_code firmware section 3 */
+	dev_dbg(&client->dev,
+		"[burn_fw_gwake]step8:burn app_code firmware section 3");
+	ret = gup_burn_fw_gwake_section(
+	client, fw_gwake, 0x9000, FW_SECTION_LENGTH, 0x3C);
+	if (FAIL == ret) {
+		dev_err(&client->dev,
+			"[burn_fw_gwake]burn app_code firmware section 3 fail.");
+		goto exit_burn_fw_gwake;
+	}
+
+	/* step9:load app_code firmware section 4 file data */
+	dev_dbg(&client->dev,
+		"[burn_fw_gwake]step9:load app_code firmware section 4 file data");
+	ret = gup_load_section_file(fw_gwake,
+	start_index + 3*FW_SECTION_LENGTH, FW_SECTION_LENGTH, SEEK_SET);
+	if (FAIL == ret) {
+		dev_err(&client->dev,
+			"[burn_fw_gwake]load app_code firmware section 4 fail.");
+		goto exit_burn_fw_gwake;
+	}
+
+	/* step10:burn app_code firmware section 4 */
+	dev_dbg(&client->dev,
+		"[burn_fw_gwake]step10:burn app_code firmware section 4");
+	ret = gup_burn_fw_gwake_section(
+	client, fw_gwake, 0x9000, FW_SECTION_LENGTH, 0x3D);
+	if (FAIL == ret) {
+		dev_err(&client->dev,
+			"[burn_fw_gwake]burn app_code firmware section 4 fail.");
+		goto exit_burn_fw_gwake;
+	}
+
+	/* update_msg.fw_burned_len += FW_GWAKE_LENGTH; */
+	dev_dbg(&client->dev,
+		"[burn_fw_gwake]Burned length:%d", update_msg.fw_burned_len);
+	ret = SUCCESS;
+
+exit_burn_fw_gwake:
+	kfree(fw_gwake);
+
+	return ret;
+}
+
+static u8 gup_burn_fw_finish(struct i2c_client *client)
+{
+	u8 *fw_ss51 = NULL;
+	u8	retry = 0;
+	s32 ret = 0;
+
+	dev_info(&client->dev,
+		 "[burn_fw_finish]burn first 8K of ss51 and finish update.");
+	/* step1:alloc memory */
+	dev_dbg(&client->dev, "[burn_fw_finish]step1:alloc memory");
+	while (retry++ < 5) {
+		fw_ss51 = kzalloc(FW_SECTION_LENGTH, GFP_KERNEL);
+		if (fw_ss51 == NULL) {
+			continue;
+		} else {
+			dev_dbg(&client->dev,
+				"[burn_fw_finish]Alloc %dk byte memory success.",
+				(FW_SECTION_LENGTH/1024));
+			break;
+		}
+	}
+	if (retry >= 5) {
+		dev_err(&client->dev,
+			"[burn_fw_finish]Alloc memory fail,exit.");
+		return FAIL;
+	}
+
+	dev_dbg(&client->dev, "[burn_fw_finish]step2: burn ss51 first 8K.");
+	ret = gup_load_section_file(fw_ss51, 0, FW_SECTION_LENGTH, SEEK_SET);
+	if (FAIL == ret) {
+		dev_err(&client->dev,
+			"[burn_fw_finish]load ss51 firmware section 1 fail.");
+		goto exit_burn_fw_finish;
+	}
+
+	dev_dbg(&client->dev, "[burn_fw_finish]step3:clear control flag");
+	ret = gup_set_ic_msg(client, _rRW_MISCTL__BOOT_CTL_, 0x00);
+	if (ret <= 0) {
+		dev_err(&client->dev,
+			"[burn_fw_finish]clear control flag fail.");
+		goto exit_burn_fw_finish;
+	}
+
+	dev_dbg(&client->dev,
+		"[burn_fw_finish]step4:burn ss51 firmware section 1");
+	ret = gup_burn_fw_section(client, fw_ss51, 0xC000, 0x01);
+	if (FAIL == ret) {
+		dev_err(&client->dev,
+			"[burn_fw_finish]burn ss51 firmware section 1 fail.");
+		goto exit_burn_fw_finish;
+	}
+
+	/* step11:enable download DSP code */
+	dev_dbg(&client->dev,
+		"[burn_fw_finish]step5:enable download DSP code ");
+	ret = gup_set_ic_msg(client, _rRW_MISCTL__BOOT_CTL_, 0x99);
+	if (ret <= 0) {
+		dev_err(&client->dev,
+			"[burn_fw_finish]enable download DSP code fail.");
+		goto exit_burn_fw_finish;
+	}
+
+	/* step12:release ss51 & hold dsp */
+	dev_dbg(&client->dev, "[burn_fw_finish]step6:release ss51 & hold dsp");
+	ret = gup_set_ic_msg(client, _rRW_MISCTL__SWRST_B0_, 0x08);
+	if (ret <= 0) {
+		dev_err(&client->dev,
+			"[burn_fw_finish]release ss51 & hold dsp fail.");
+		goto exit_burn_fw_finish;
+	}
+
+	if (fw_ss51 != NULL)
+		kfree(fw_ss51);
+	return SUCCESS;
+
+exit_burn_fw_finish:
+	if (fw_ss51 != NULL)
+		kfree(fw_ss51);
+
+	return FAIL;
+}
+
+/* return 0 can update, else no update condition */
+static int gup_update_condition_check(struct goodix_ts_data *ts)
+{
+	if (test_bit(SLEEP_MODE, &ts->flags)) {
+		dev_info(&ts->client->dev, "Update abort, tp in sleep mode\n");
+		return -EINVAL;
+	}
+
+	return 0;
+}
+s32 gup_update_proc(void *dir)
+{
+	s32 ret = 0;
+	s32 update_ret = FAIL;
+	u8	retry = 0;
+	struct st_fw_head fw_head;
+	struct goodix_ts_data *ts = NULL;
+
+	ts = i2c_get_clientdata(i2c_connect_client);
+
+	dev_dbg(&ts->client->dev, "[update_proc]Begin update ......\n");
+
+	show_len = 1;
+	total_len = 100;
+
+	ret = gup_update_condition_check(ts);
+	if (ret) {
+		dev_warn(&ts->client->dev, "Update start failed\n");
+		return FAIL;
+	}
+
+	if (test_and_set_bit(FW_UPDATE_RUNNING, &ts->flags)) {
+		dev_warn(&ts->client->dev, "FW update may already running\n");
+		return FAIL;
+	}
+
+	if (dir)
+		ts->force_update = true;
+	ret = gup_get_update_file(i2c_connect_client, &fw_head, (u8 *)dir);
+	if (FAIL == ret) {
+		dev_err(&ts->client->dev,
+			"Failed get valied firmware data\n");
+		return FAIL;
+	}
+
+	gtp_work_control_enable(ts, false);
+	gtp_esd_off(ts);
+
+	ret = gup_get_ic_fw_msg(i2c_connect_client);
+	if (FAIL == ret) {
+		dev_err(&ts->client->dev, "[update_proc]get ic message fail.");
+		goto file_fail;
+	}
+
+	if (ts->force_update) {
+		dev_dbg(&ts->client->dev, "Enter force update.");
+	} else {
+		ret = gup_enter_update_judge(i2c_connect_client, &fw_head);
+		if (FAIL == ret) {
+			dev_err(&ts->client->dev,
+				"[update_proc]Doesn't meet update condition\n");
+			goto file_fail;
+		}
+	}
+
+	ret = gup_enter_update_mode(ts->client);
+	if (FAIL == ret) {
+		dev_err(&ts->client->dev,
+			"[update_proc]enter update mode fail.");
+		goto update_fail;
+	}
+
+	while (retry++ < 5) {
+		show_len = 10;
+		total_len = 100;
+		update_msg.fw_burned_len = 0;
+		ret = gup_burn_dsp_isp(i2c_connect_client);
+		if (FAIL == ret) {
+			dev_err(&ts->client->dev,
+				"[update_proc]burn dsp isp fail.");
+			continue;
+		}
+
+		show_len = 20;
+		ret = gup_burn_fw_gwake(i2c_connect_client);
+		if (FAIL == ret) {
+			dev_err(&ts->client->dev,
+				"[update_proc]burn app_code firmware fail.");
+			continue;
+		}
+
+		show_len = 30;
+		ret = gup_burn_fw_ss51(i2c_connect_client);
+		if (FAIL == ret) {
+			dev_err(&ts->client->dev,
+				"[update_proc]burn ss51 firmware fail.");
+			continue;
+		}
+
+		show_len = 40;
+		ret = gup_burn_fw_dsp(i2c_connect_client);
+		if (FAIL == ret) {
+			dev_err(&ts->client->dev,
+				"[update_proc]burn dsp firmware fail.");
+			continue;
+		}
+
+		show_len = 50;
+		ret = gup_burn_fw_boot(i2c_connect_client);
+		if (FAIL == ret) {
+			dev_err(&ts->client->dev,
+				"[update_proc]burn bootloader firmware fail.");
+			continue;
+		}
+		show_len = 60;
+
+		ret = gup_burn_fw_boot_isp(i2c_connect_client);
+		if (FAIL == ret) {
+			dev_err(&ts->client->dev,
+				"[update_proc]burn boot_isp firmware fail.");
+			continue;
+		}
+
+		show_len = 70;
+		ret = gup_burn_fw_link(i2c_connect_client);
+		if (FAIL == ret) {
+			dev_err(&ts->client->dev,
+				"[update_proc]burn link firmware fail.");
+			continue;
+		}
+
+		show_len = 80;
+		ret = gup_burn_fw_finish(i2c_connect_client);
+		if (FAIL == ret) {
+			dev_err(&ts->client->dev,
+				"[update_proc]burn finish fail.");
+			continue;
+		}
+		show_len = 90;
+		dev_info(&ts->client->dev, "[update_proc]UPDATE SUCCESS.");
+		retry = 0;
+		break;
+	}
+
+	if (retry >= 5) {
+		dev_err(&ts->client->dev,
+			"[update_proc]retry timeout,UPDATE FAIL.");
+		update_ret = FAIL;
+	} else {
+		update_ret = SUCCESS;
+	}
+
+update_fail:
+	dev_dbg(&ts->client->dev, "[update_proc]leave update mode.");
+	gup_leave_update_mode(i2c_connect_client);
+
+	msleep(GTP_100_DLY_MS);
+
+	if (SUCCESS == update_ret) {
+		if (test_bit(FW_ERROR, &ts->flags)) {
+			dev_info(&ts->client->dev,
+				"firmware error auto update, resent config!\n");
+			gup_init_panel(ts);
+		} else {
+			dev_dbg(&ts->client->dev, "[update_proc]send config\n");
+			ret = gtp_send_cfg(i2c_connect_client);
+			if (ret < 0)
+				dev_err(&ts->client->dev,
+					"[update_proc]send config fail\n");
+			 else
+				msleep(GTP_100_DLY_MS);
+		}
+	}
+	gtp_get_fw_info(ts->client, &ts->fw_info);
+
+file_fail:
+
+	update_msg.fw_data = NULL;
+	update_msg.fw_total_len = 0;
+	release_firmware(update_msg.fw);
+
+	clear_bit(FW_UPDATE_RUNNING, &ts->flags);
+	gtp_work_control_enable(ts, true);
+	gtp_esd_on(ts);
+	total_len = 100;
+	if (SUCCESS == update_ret) {
+		show_len = 100;
+		clear_bit(FW_ERROR, &ts->flags);
+		return SUCCESS;
+	} else {
+		show_len = 200;
+		return FAIL;
+	}
+}
+
+u8 gup_init_update_proc(struct goodix_ts_data *ts)
+{
+	struct task_struct *thread = NULL;
+
+	dev_info(&ts->client->dev, "Ready to run update thread.");
+
+	thread = kthread_run(gup_update_proc,
+			(void *)NULL, "guitar_update");
+
+	if (IS_ERR(thread)) {
+		dev_err(&ts->client->dev,
+				"Failed to create update thread.\n");
+		return -EPERM;
+	}
+
+	return 0;
+}
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/hcsr04/Makefile b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/hcsr04/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..9abfc308d7f2b0f4196076a3696641bee56ac2e2
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/hcsr04/Makefile
@@ -0,0 +1,40 @@
+#
+# Peter Yang <turmary@126.com>
+# Copyright (c) 2019 Seeed Studio
+#
+# MIT License
+#
+
+_tgt     := hcsr04
+
+_uname_r := $(shell uname -r)
+_BUILD   := /lib/modules/$(_uname_r)/build
+_PWD     := $(shell pwd)
+_DEPMOD  ?= depmod -a
+
+# If KERNELRELEASE is defined, we've been invoked from the
+# kernel build system and can use its language
+ifneq ($(KERNELRELEASE),)
+obj-m += ${_tgt}.o
+
+else
+_class  := drivers/misc
+
+DEST  := /lib/modules/$(_uname_r)/kernel
+
+all:
+	make -C ${_BUILD} M=$(_PWD) modules
+
+clean:
+	make -C ${_BUILD} M=$(_PWD) clean
+
+install:
+	cp ${_tgt}.ko ${DEST}/${_class}/
+	$(_DEPMOD)
+
+uninstall:
+	rm -f ${DEST}/${_class}/${_tgt}.ko
+	$(_DEPMOD)
+
+.PHONY: all clean install uninstall
+endif
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/hcsr04/README.md b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/hcsr04/README.md
new file mode 100644
index 0000000000000000000000000000000000000000..21d0804a7fce4627f21367ab52eb66a425dd11cc
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/hcsr04/README.md
@@ -0,0 +1,29 @@
+GROVE Ultrasonic Ranger (HCSR04)
+================================
+
+  After driver and configuration prepared well,
+  the user could access ```/sys/bus/iio/devices/iio\:device<N>/in_distance_input```,
+  to get distance between the sensor and object.
+
+***
+
+Usage
+-----
+
+***example:***
+
+  ```bash
+  # check the device<N> name, make sure it's hcsr04
+  # where <N> is a number specific to your system.
+
+  $ cat /sys/bus/iio/devices/iio\:device1/name
+  hcsr04_1057@20
+    
+  # get the distance, in unit cm.
+  cat /sys/bus/iio/devices/iio\:device1/in_distance_input
+  2128
+  ```
+
+  If you need customize the GPIO-Port..., refer to device tree document
+  [hcsr04.txt](../../doc/devicetree/bindings/hcsr04.txt)
+
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/hcsr04/hcsr04.c b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/hcsr04/hcsr04.c
new file mode 100644
index 0000000000000000000000000000000000000000..f89bc11a1fdb244bd8cbdc7ec07857b1e94a45ab
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/hcsr04/hcsr04.c
@@ -0,0 +1,405 @@
+/*
+ * Kernel module for HC-SR04 Ultrasonic Range Finder
+ *
+ * Original written by
+ * Copyright (C) 2014 James Ward
+ *
+ * Port to support single signal pin device, iio, and device tree configuration
+ *
+ * Copyright (C) 2019 Seeed Studio
+ * Peter Yang <turmary@126.com>
+ *
+ * Released under the GPL
+ *
+ */
+#include <linux/kobject.h>
+#include <linux/string.h>
+#include <linux/sysfs.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/gpio.h>
+#include <linux/interrupt.h>
+#include <linux/time.h>
+#include <linux/ktime.h>
+#include <linux/delay.h>
+#include <linux/sched.h>
+#include <linux/irq.h>
+#include <linux/platform_device.h>
+#include <linux/of_device.h>
+#include <linux/of_gpio.h>
+#include <linux/iio/iio.h>
+
+#define DEV_NAME	"hcsr04"
+#define DEV_ALERT	KERN_ALERT DEV_NAME ": "
+
+struct hcsr04 {
+	struct device *   dev;
+	int               trig;                /* trigger pin */
+	int               echo;                /* echo pin */
+	int               count;               /* Number of interrupts received */
+	ktime_t           time_stamp[2];       /* Time-stamp of interrupts */
+	/* Declare a wait queue to wait for interrupts */
+	wait_queue_head_t wait;
+	/* Mutex used to prevent simultaneous access */
+	struct mutex      lock;
+	long              distance;
+};
+
+
+/*---------------------------------------------------------------------------*/
+
+/* GPIO pin used for trigger out */
+static int trig_pin = 57;
+module_param(trig_pin, int, S_IRUGO);
+
+/* GPIO pin used for echo in */
+static int echo_pin = 57;
+module_param(echo_pin, int, S_IRUGO);
+
+/* High level pulse width, in us */
+static int pulse = 20;
+module_param(pulse, int, S_IRUGO);
+
+/* Timeout for range finding operation in milliseconds */
+const long TIMEOUT_RANGE_FINDING = 60;
+
+/*---------------------------------------------------------------------------*/
+
+/* Interrupt handler: called on rising/falling edge */
+static irqreturn_t gpio_interrupt_handler( int irq, void *dev_id )
+{
+	struct hcsr04* hc = (struct hcsr04*)dev_id;
+
+	/* Get the kernel time */
+	ktime_t time_stamp = ktime_get();
+
+
+	/* For the first two interrupts received, store the time-stamp */
+	if ( hc->count < 2 )
+		hc->time_stamp[hc->count] = time_stamp;
+
+	/* Count the number of interrupts received */
+	++hc->count;
+
+	/* If we have received two interrupts, wake up */
+	if ( hc->count > 1 )
+		wake_up_interruptible( &hc->wait );
+
+	return IRQ_HANDLED;
+}
+
+/*---------------------------------------------------------------------------*/
+
+/* Measures the range, returning the time period in microseconds, and the
+ * range in millimetres. The return value is 1 for success, and 0 for failure.
+ */
+static int hcsr04_measure_range(
+	struct hcsr04* hc,
+	long *us,	/* out: time in us */
+	long *mm	/* out: range in mm */
+) {
+	/* The speed of sound in mm/s */
+	const long speed_sound_mms = 340270;
+
+	ktime_t elapsed_kt;          /* used to store elapsed time */
+	struct timeval elapsed_tv;   /* elapsed time as timeval */
+	int irq = 0;                 /* the IRQ number */
+	int range_complete = 0;      /* indicates successful range finding */
+
+	/* Acquire the mutex before entering critical section */
+	mutex_lock( &hc->lock );
+
+	/* Initialise variables used by interrupt handler */
+	hc->count = 0;
+	memset( &hc->time_stamp, 0, sizeof(hc->time_stamp) );
+
+	if (hc->echo == hc->trig) {
+		/* make GPIO an output */
+		if ( gpio_direction_output(hc->trig, 0) != 0 ) {
+			printk( DEV_ALERT "Failed to make sig/trig pin %d an output\n", hc->trig );
+			mutex_unlock( &hc->lock );
+			return -1;
+		}
+	}
+
+	/* Transmit trigger pulse, lasting at least 20us */
+	gpio_set_value(hc->trig, 0);
+	udelay(2);
+	gpio_set_value(hc->trig, 1);
+	udelay(pulse);
+	gpio_set_value(hc->trig, 0);
+
+	if (hc->echo == hc->trig) {
+		/* make GPIO an input */
+		if ( gpio_direction_input(hc->echo) ) {
+			printk( DEV_ALERT "Failed to make sig/echo pin %d an input\n", hc->echo );
+			mutex_unlock( &hc->lock );
+			return -1;
+		}
+	}
+
+	/* Request an IRQ for the echo GPIO pin, so that we can measure the rising
+	 * and falling edge of the pulse from the ranger.
+	 */
+	irq = gpio_to_irq( hc->echo );
+	if ( request_irq(
+		irq,
+		gpio_interrupt_handler,
+		IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING | IRQF_SHARED,
+		"hcsr04_irq",
+		hc
+	) ) {
+		/* Release the mutex */
+		mutex_unlock( &hc->lock );
+		return -1;
+	}
+
+	/* Wait until we have received two interrupts (indicating that
+	 * range finding has completed), or we have timed out
+	 */
+	wait_event_interruptible_timeout(
+		hc->wait,
+		hc->count == 2,
+		msecs_to_jiffies(TIMEOUT_RANGE_FINDING)
+	);
+
+	/* Free the interrupt */
+	free_irq( irq, hc );
+
+	/* Have we successfully completed ranging? */
+	range_complete = (hc->count == 2);
+
+	if ( range_complete ) {
+		/* Calculate pulse length */
+		elapsed_kt = ktime_sub( hc->time_stamp[1], hc->time_stamp[0] );
+		elapsed_tv = ktime_to_timeval( elapsed_kt );
+	}
+
+	/* Release the mutex */
+	mutex_unlock( &hc->lock );
+
+	if ( range_complete ) {
+		/* Return the time period in microseconds. We ignore the tv_sec,
+		 * because the maximum delay should be less than 60ms
+		 */
+		if ( us != NULL )
+			*us = elapsed_tv.tv_usec;
+
+		/* Return the distance, based on speed of sound and the elapsed
+		 * time in microseconds.
+		 */
+		if ( mm != NULL )
+			*mm = elapsed_tv.tv_usec * (speed_sound_mms / 10) / 200000/*0*/;
+
+		/* Success */
+		return 1;
+	} else {
+		/* Failure */
+		if ( us != NULL ) *us = 0;
+		if ( mm != NULL ) *mm = 0;
+		return 0;
+	}
+}
+
+/*---------------------------------------------------------------------------*/
+
+static int hcsr04_read_raw(struct iio_dev *iio,
+        const struct iio_chan_spec *chan,
+        int *val, int *val2, long m)
+{
+	struct hcsr04 *hcsr04 = iio_priv(iio);
+	long us = 0;
+	int ret;
+
+	hcsr04_measure_range(hcsr04, &us, &hcsr04->distance);
+
+	ret = IIO_VAL_INT;
+	if (chan->type == IIO_DISTANCE)
+		*val = hcsr04->distance;
+	else
+		ret = -EINVAL;
+
+	return ret;
+}
+
+static const struct iio_info hcsr04_iio_info = {
+	.driver_module		= THIS_MODULE,
+	.read_raw		= hcsr04_read_raw,
+};
+
+static const struct iio_chan_spec hcsr04_chan_spec[] = {
+	{ .type = IIO_DISTANCE,
+		.info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED), },
+};
+
+/*---------------------------------------------------------------------------*/
+
+/* Initialise GPIO */
+static int hcsr04_gpio_init( struct hcsr04* hc )
+{
+	/* check that trigger GPIO is valid */
+	if ( !gpio_is_valid(hc->trig) ){
+		printk( DEV_ALERT "trig GPIO %d is not valid\n", hc->trig );
+		return -EINVAL;
+	}
+
+	/* request the GPIO pin */
+	if ( gpio_request(hc->trig, DEV_NAME) != 0 ) {
+		printk( DEV_ALERT "Unable to request trig GPIO %d\n", hc->trig );
+		return -EINVAL;
+	}
+
+	/* make GPIO an output */
+	if ( gpio_direction_output(hc->trig, 0) != 0 ) {
+		printk( DEV_ALERT "Failed to make trig GPIO %d an output\n", hc->trig );
+		return -EINVAL;
+	}
+
+	/* check if trigger and echo are the same GPIO */
+	if ( hc->trig == hc->echo ) {
+		printk( DEV_ALERT "sig/echo GPIO %d is same as sig/trig\n", hc->echo);
+		return 0;
+	}
+
+	/* check that echo GPIO is valid */
+	if ( !gpio_is_valid(hc->echo) ){
+		printk( DEV_ALERT "echo GPIO %d is not valid\n", hc->echo );
+		return -EINVAL;
+	}
+
+	/* request the GPIO pin */
+	if ( gpio_request(hc->echo, DEV_NAME) != 0 ) {
+		printk( DEV_ALERT "Unable to request echo GPIO %d\n", hc->echo );
+		return -EINVAL;
+	}
+
+	/* make GPIO an input */
+	if ( gpio_direction_input(hc->echo) != 0 ) {
+		printk( DEV_ALERT "Failed to make echo GPIO %d an input\n", hc->echo );
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+/*---------------------------------------------------------------------------*/
+
+/* Free GPIO */
+static void hcsr04_gpio_free( struct hcsr04* hc )
+{
+	gpio_free(hc->trig);
+	if (hc->echo != hc->trig) {
+		gpio_free(hc->echo);
+	}
+	return;
+}
+
+/*---------------------------------------------------------------------------*/
+#ifdef CONFIG_OF
+static const struct of_device_id hcsr04_dt_ids[] = {
+	{ .compatible = DEV_NAME, },
+	{}
+};
+MODULE_DEVICE_TABLE(of, hcsr04_dt_ids);
+#endif
+
+/* device initialisation function */
+static int hcsr04_probe(struct platform_device* pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct hcsr04 *hcsr04;
+	struct iio_dev *iio;
+	int ret = -1;
+	int trig = 0;
+	int echo = 0;
+
+	#ifdef CONFIG_OF
+	struct device_node *node = dev->of_node;
+
+	if (node) {
+		/*
+		 * first  gpio: trigger pin
+		 * second gpio: echo    pin
+		 */
+		ret = of_get_gpio(node, 0);
+		if (ret >= 0) {
+			trig = ret;
+			ret = of_get_gpio(node, 1);
+			if (ret >= 0) {
+				echo = ret;
+			} else {
+				echo = trig;
+			}
+		}
+	}
+	#else
+	trig = trig_pin;
+	echo = echo_pin;
+	#endif
+
+	iio = devm_iio_device_alloc(dev, sizeof(*hcsr04));
+	if (!iio) {
+		dev_err(dev, "Failed to allocate IIO device\n");
+		return -ENOMEM;
+	}
+
+	/* fill hcsr04 structure */
+	hcsr04 = iio_priv(iio);
+	hcsr04->dev = dev;
+	hcsr04->trig = trig;
+	hcsr04->echo = echo;
+	init_waitqueue_head(&hcsr04->wait);
+	mutex_init(&hcsr04->lock);
+
+	platform_set_drvdata(pdev, iio);
+
+	iio->name = pdev->name;
+	iio->dev.parent = &pdev->dev;
+	iio->info = &hcsr04_iio_info;
+	iio->modes = INDIO_DIRECT_MODE;
+	iio->channels = hcsr04_chan_spec;
+	iio->num_channels = ARRAY_SIZE(hcsr04_chan_spec);
+
+	/* Set up the GPIO */
+	if ( hcsr04_gpio_init(hcsr04) < 0 )
+		return -EINVAL;
+
+
+	return devm_iio_device_register(dev, iio);
+}
+
+/*---------------------------------------------------------------------------*/
+
+/* device removing function */
+static int hcsr04_remove(struct platform_device* pdev)
+{
+	struct iio_dev *iio = platform_get_drvdata(pdev);
+	struct hcsr04 *hcsr04 = iio_priv(iio);
+
+	/* Free GPIO */
+	hcsr04_gpio_free(hcsr04);
+
+	iio_device_unregister(iio);
+	return 0;
+}
+
+/*---------------------------------------------------------------------------*/
+
+static struct platform_driver hcsr04_driver = {
+	.driver = {
+		.name  = DEV_NAME,
+		.owner = THIS_MODULE,
+		#ifdef CONFIG_OF
+		.of_match_table = hcsr04_dt_ids,
+		#endif
+	},
+	.probe  = hcsr04_probe,
+	.remove = hcsr04_remove,
+};
+
+module_platform_driver(hcsr04_driver);
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("James Ward");
+MODULE_AUTHOR("Peter Yang <turmary@126.com>");
+
+/*---------------------------------------------------------------------------*/
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/hd44780/Makefile b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/hd44780/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..a786cb2a9ec0ed3e73fbb8b938e55e816e5b6dcf
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/hd44780/Makefile
@@ -0,0 +1,41 @@
+#
+# Peter Yang <turmary@126.com>
+# Copyright (c) 2019 Seeed Studio
+#
+# MIT License
+#
+
+_tgt     := hd44780
+
+_uname_r := $(shell uname -r)
+_BUILD   := /lib/modules/$(_uname_r)/build
+_PWD     := $(shell pwd)
+_DEPMOD  ?= depmod -a
+
+# If KERNELRELEASE is defined, we've been invoked from the
+# kernel build system and can use its language
+ifneq ($(KERNELRELEASE),)
+hd44780-objs := hd44780-i2c.o hd44780-dev.o
+obj-m += ${_tgt}.o
+
+else
+_class  := drivers/misc
+
+DEST  := /lib/modules/$(_uname_r)/kernel
+
+all:
+	make -C ${_BUILD} M=$(_PWD) modules
+
+clean:
+	make -C ${_BUILD} M=$(_PWD) clean
+
+install:
+	cp ${_tgt}.ko ${DEST}/${_class}/
+	$(_DEPMOD)
+
+uninstall:
+	rm -f ${DEST}/${_class}/${_tgt}.ko
+	$(_DEPMOD)
+
+.PHONY: all clean install uninstall
+endif
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/hd44780/README.md b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/hd44780/README.md
new file mode 100644
index 0000000000000000000000000000000000000000..b8caf307a6fff15a8bb9b6730b7dc5b470cb791d
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/hd44780/README.md
@@ -0,0 +1,38 @@
+# jhd1802/hd44780
+
+Acknowledgement:
+https://github.com/gorskima/hd44780-i2c/
+
+<br>
+This is a Linux kernel driver for JHD1802/HD44780 LCDs attached to I2C bus.
+Ideal to use with PocketBeagle and other small devices running Linux where I2C bus is available.
+
+`$ uname -snrmv | tr -d '\n' > /dev/lcd0`
+
+
+### Features
+The main goal was to expose HD44780-based LCDs behind regular Linux device files normally found in `/dev` directory. Thus, writing to the display is as easy as `echo Hello, world! > /dev/lcd0`.
+
+There are no imposed limitations on number of concurrently attached devices. In practice, a single I2C bus allows up to 128 uniquely addressable devices. Furthermore, standard HD44780 LCD to I2C adapters usually use the same, hardcoded I2C address (like 0x3E) and it's not possible to change them.
+
+Multiple LCD geometries are supported (20x4, 16x8[default] and 8x1) and it's trivial to add new ones if needed.
+
+Supported escape sequences:
+* `\r` - carriage return
+* `\n` - line feed (new line)
+
+Supported VT100 terminal control escape sequences:
+* `<ESC>[H` - cursor home
+* `<ESC>[2J` - erase screen
+
+Device attributes exported via sysfs (`/sys/class/hd44780/<device_name>`):
+* `backlight` - controls LCD backlight. Possible values: `0`, `1`
+* `geometry` - sets LCD geometry. Possible values: `20x4`, `16x2`, `8x1`
+* `cursor_blink` - controls cursor blink. Possible values: `0`, `1`
+* `cursor_display` - displays or hides cursor. Possible values: `0`, `1`
+
+### Usage
+1. Insert kernel module: `modprobe hd44780`.
+2. Let the I2C adapter know that there's a new device attached: `echo hd44780 0x27 > /sys/class/i2c-adapter/i2c-1/new_device`.
+You may need to replace the device's I2C address and adapter path with proper values.
+3. At this point a new device should appear (`/dev/lcd0`) and you should be able to write to it.
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/hd44780/hd44780-dev.c b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/hd44780/hd44780-dev.c
new file mode 100644
index 0000000000000000000000000000000000000000..771c44bd817c13d344672245eaa5272fb15961f2
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/hd44780/hd44780-dev.c
@@ -0,0 +1,331 @@
+#include <linux/cdev.h>
+#include <linux/i2c.h>
+#include <linux/delay.h>
+#include <linux/slab.h>
+
+#include "hd44780.h"
+
+#define BL	0x08
+#define E	0x04
+#define RW	0x02
+#define RS	0x01
+#define _DATA	0x40
+#define _CMD	0x80
+
+#define HD44780_CLEAR_DISPLAY	0x01
+#define HD44780_RETURN_HOME	0x02
+#define HD44780_ENTRY_MODE_SET	0x04
+#define HD44780_DISPLAY_CTRL	0x08
+#define HD44780_SHIFT		0x10
+#define HD44780_FUNCTION_SET	0x20
+#define HD44780_CGRAM_ADDR	0x40
+#define HD44780_DDRAM_ADDR	0x80
+
+#define HD44780_DL_8BITS	0x10
+#define HD44780_DL_4BITS	0x00
+#define HD44780_N_2LINES	0x08
+#define HD44780_N_1LINE		0x00
+#define HD44780_5x10DOTS	0x04
+#define HD44780_5x8DOTS		0x00
+
+#define HD44780_D_DISPLAY_ON	0x04
+#define HD44780_D_DISPLAY_OFF	0x00
+#define HD44780_C_CURSOR_ON	0x02
+#define HD44780_C_CURSOR_OFF	0x00
+#define HD44780_B_BLINK_ON	0x01
+#define HD44780_B_BLINK_OFF	0x00
+
+#define HD44780_ID_INCREMENT	0x02
+#define HD44780_ID_DECREMENT	0x00
+#define HD44780_S_SHIFT_ON	0x01
+#define HD44780_S_SHIFT_OFF	0x00
+
+static struct hd44780_geometry hd44780_geometry_20x4 = {
+	.cols = 20,
+	.rows = 4,
+	.start_addrs = {0x00, 0x40, 0x14, 0x54},
+};
+
+static struct hd44780_geometry hd44780_geometry_16x2 = {
+	.cols = 16,
+	.rows = 2,
+	.start_addrs = {0x00, 0x40},
+};
+
+static struct hd44780_geometry hd44780_geometry_8x1 = {
+	.cols = 8,
+	.rows = 1,
+	.start_addrs = {0x00},
+};
+
+struct hd44780_geometry *hd44780_geometries[] = {
+	&hd44780_geometry_20x4,
+	&hd44780_geometry_16x2,
+	&hd44780_geometry_8x1,
+	NULL
+};
+
+/* Defines possible register that we can write to */
+typedef enum { IR, DR } dest_reg;
+
+static void hd44780_write_nibble(struct hd44780 *lcd, dest_reg reg, u8 data)
+{
+	u8 first;
+
+	/*
+	 * First byte, select DATA or CMD
+	 * Second byte, DATA or CMD
+	 */
+	first = (reg == DR)? _DATA: _CMD;
+	i2c_smbus_write_byte_data(lcd->i2c_client, first, data);
+
+	return;
+}
+
+/*
+ * JHD1802 lowlevel functions
+ */
+static void hd44780_write_instruction(struct hd44780 *lcd, u8 data)
+{
+	hd44780_write_nibble(lcd, IR, data);
+	udelay(37);
+}
+
+static void hd44780_write_data(struct hd44780 *lcd, u8 data)
+{
+	hd44780_write_nibble(lcd, DR, data);
+	udelay(37 + 4);
+}
+
+static void hd44780_write_char(struct hd44780 *lcd, char ch)
+{
+	struct hd44780_geometry *geo = lcd->geometry;
+
+	hd44780_write_data(lcd, ch);
+
+	lcd->pos.col++;
+
+	if (lcd->pos.col == geo->cols) {
+		lcd->pos.row = (lcd->pos.row + 1) % geo->rows;
+		lcd->pos.col = 0;
+		hd44780_write_instruction(lcd, HD44780_DDRAM_ADDR | geo->start_addrs[lcd->pos.row]);
+	}
+}
+
+static void hd44780_clear_display(struct hd44780 *lcd)
+{
+	hd44780_write_instruction(lcd, HD44780_CLEAR_DISPLAY);
+
+	/* Wait for 1.64 ms because this one needs more time */
+	udelay(1640);
+
+	/*
+	 * CLEAR_DISPLAY instruction also returns cursor to home,
+	 * so we need to update it locally.
+	 */
+	lcd->pos.row = 0;
+	lcd->pos.col = 0;
+}
+
+static void hd44780_clear_line(struct hd44780 *lcd)
+{
+	struct hd44780_geometry *geo;
+	int start_addr, col;
+
+	geo = lcd->geometry;
+	start_addr = geo->start_addrs[lcd->pos.row];
+
+	hd44780_write_instruction(lcd, HD44780_DDRAM_ADDR | start_addr);
+
+	for (col = 0; col < geo->cols; col++)
+		hd44780_write_data(lcd, ' ');
+
+	hd44780_write_instruction(lcd, HD44780_DDRAM_ADDR | start_addr);
+}
+
+static void hd44780_handle_new_line(struct hd44780 *lcd)
+{
+	struct hd44780_geometry *geo = lcd->geometry;
+
+	lcd->pos.row = (lcd->pos.row + 1) % geo->rows;
+	lcd->pos.col = 0;
+	hd44780_write_instruction(lcd, HD44780_DDRAM_ADDR
+		| geo->start_addrs[lcd->pos.row]);
+	hd44780_clear_line(lcd);
+}
+
+static void hd44780_handle_carriage_return(struct hd44780 *lcd)
+{
+	struct hd44780_geometry *geo = lcd->geometry;
+
+	lcd->pos.col = 0;
+	hd44780_write_instruction(lcd, HD44780_DDRAM_ADDR
+		| geo->start_addrs[lcd->pos.row]);
+}
+
+static void hd44780_leave_esc_seq(struct hd44780 *lcd)
+{
+	memset(lcd->esc_seq_buf.buf, 0, ESC_SEQ_BUF_SIZE);
+	lcd->esc_seq_buf.length = 0;
+	lcd->is_in_esc_seq = false;
+}
+
+static void hd44780_flush_esc_seq(struct hd44780 *lcd)
+{
+	char *buf_to_flush;
+	int buf_length;
+
+	/* Copy and reset current esc seq */
+	buf_to_flush = kmalloc(sizeof(char) * ESC_SEQ_BUF_SIZE, GFP_KERNEL);
+	memcpy(buf_to_flush, lcd->esc_seq_buf.buf, ESC_SEQ_BUF_SIZE);
+	buf_length = lcd->esc_seq_buf.length;
+
+	hd44780_leave_esc_seq(lcd);
+
+	/* Write \e that initiated current esc seq */
+	hd44780_write_char(lcd, '\e');
+
+	/* Flush current esc seq */
+	hd44780_write(lcd, buf_to_flush, buf_length);
+
+	kfree(buf_to_flush);
+}
+
+void hd44780_flush(struct hd44780 *lcd)
+{
+	while (lcd->is_in_esc_seq)
+		hd44780_flush_esc_seq(lcd);
+}
+
+static void hd44780_handle_esc_seq_char(struct hd44780 *lcd, char ch)
+{
+	int prev_row, prev_col;
+
+	lcd->esc_seq_buf.buf[lcd->esc_seq_buf.length++] = ch;
+
+	if (!strcmp(lcd->esc_seq_buf.buf, "[2J")) {
+		prev_row = lcd->pos.row;
+		prev_col = lcd->pos.col;
+
+		hd44780_clear_display(lcd);
+		hd44780_write_instruction(lcd, HD44780_DDRAM_ADDR | (lcd->geometry->start_addrs[prev_row] + prev_col));
+
+		hd44780_leave_esc_seq(lcd);
+	} else if (!strcmp(lcd->esc_seq_buf.buf, "[H")) {
+		hd44780_write_instruction(lcd, HD44780_RETURN_HOME);
+		lcd->pos.row = 0;
+		lcd->pos.col = 0;
+
+		hd44780_leave_esc_seq(lcd);
+	} else if (lcd->esc_seq_buf.length == ESC_SEQ_BUF_SIZE) {
+		hd44780_flush_esc_seq(lcd);
+	}
+}
+
+void hd44780_write(struct hd44780 *lcd, const char *buf, size_t count)
+{
+	size_t i;
+	char ch;
+
+	if (lcd->dirty) {
+		hd44780_clear_display(lcd);
+		lcd->dirty = false;
+	}
+
+	for (i = 0; i < count; i++) {
+		ch = buf[i];
+
+		if (lcd->is_in_esc_seq) {
+			hd44780_handle_esc_seq_char(lcd, ch);
+		} else {
+			switch (ch) {
+			case '\r':
+				hd44780_handle_carriage_return(lcd);
+				break;
+			case '\n':
+				hd44780_handle_new_line(lcd);
+				break;
+			case '\e':
+				lcd->is_in_esc_seq = true;
+				break;
+			default:
+				hd44780_write_char(lcd, ch);
+				break;
+			}
+		}
+	}
+}
+
+void hd44780_print(struct hd44780 *lcd, const char *str)
+{
+	hd44780_write(lcd, str, strlen(str));
+}
+
+void hd44780_set_geometry(struct hd44780 *lcd, struct hd44780_geometry *geo)
+{
+	lcd->geometry = geo;
+
+	if (lcd->is_in_esc_seq)
+		hd44780_leave_esc_seq(lcd);
+
+	hd44780_clear_display(lcd);
+}
+
+void hd44780_set_backlight(struct hd44780 *lcd, bool backlight)
+{
+	lcd->backlight = backlight;
+	/* TODO */
+	hd44780_write_instruction(lcd, backlight ? BL : 0x00);
+}
+
+static void hd44780_update_display_ctrl(struct hd44780 *lcd)
+{
+
+	hd44780_write_instruction(lcd, HD44780_DISPLAY_CTRL
+		| HD44780_D_DISPLAY_ON
+		| (lcd->cursor_display ? HD44780_C_CURSOR_ON
+			: HD44780_C_CURSOR_OFF)
+		| (lcd->cursor_blink ? HD44780_B_BLINK_ON
+			: HD44780_B_BLINK_OFF));
+}
+
+void hd44780_set_cursor_blink(struct hd44780 *lcd, bool cursor_blink)
+{
+	lcd->cursor_blink = cursor_blink;
+	hd44780_update_display_ctrl(lcd);
+}
+
+void hd44780_set_cursor_display(struct hd44780 *lcd, bool cursor_display)
+{
+	lcd->cursor_display= cursor_display;
+	hd44780_update_display_ctrl(lcd);
+}
+
+void hd44780_init_lcd(struct hd44780 *lcd)
+{
+	/* HD44780 requires writing three times to initialize or reset
+	 *   according to the hardware errata on page 45 figure 23 of
+	 *   the Hitachi HD44780 datasheet */
+	hd44780_write_instruction(lcd, HD44780_FUNCTION_SET
+		| HD44780_DL_8BITS);
+	mdelay(5);
+
+	hd44780_write_instruction(lcd, HD44780_FUNCTION_SET
+		| HD44780_DL_8BITS);
+	udelay(100);
+
+	hd44780_write_instruction(lcd, HD44780_FUNCTION_SET
+		| HD44780_DL_8BITS);
+	
+	hd44780_write_instruction(lcd, HD44780_FUNCTION_SET | HD44780_DL_8BITS
+		| HD44780_N_2LINES | HD44780_5x10DOTS);
+
+	hd44780_write_instruction(lcd, HD44780_DISPLAY_CTRL | HD44780_D_DISPLAY_ON
+		| HD44780_C_CURSOR_ON | HD44780_B_BLINK_ON);
+	udelay(100);
+
+	hd44780_clear_display(lcd);
+
+	hd44780_write_instruction(lcd, HD44780_ENTRY_MODE_SET
+		| HD44780_ID_INCREMENT | HD44780_S_SHIFT_OFF);
+}
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/hd44780/hd44780-i2c.c b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/hd44780/hd44780-i2c.c
new file mode 100644
index 0000000000000000000000000000000000000000..ef182e618f2aa03c1beec19df0e5b3ae9bd12341
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/hd44780/hd44780-i2c.c
@@ -0,0 +1,378 @@
+/*
+ * hd44780-i2c.c
+ *
+ * Implements I2C interface for JHD1802/HD44780 LCD.
+ * Driver is based on driver written by gorskima
+ * (https://github.com/gorskima/hd44780-i2c).
+ *
+ * Port to support JHD1802 by Peter Yang <turmary@126.com>
+ * Copyright (C) 2019 Seeed Studio
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ */
+#include <linux/module.h>
+#include <linux/fs.h>
+#include <linux/printk.h>
+#include <linux/device.h>
+#include <linux/i2c.h>
+#include <linux/delay.h>
+#include <linux/cdev.h>
+#include <linux/uaccess.h>
+#include <linux/slab.h>
+#include <linux/list.h>
+
+#include "hd44780.h"
+
+#define CLASS_NAME	"hd44780"
+#define NAME		"hd44780"
+#define NUM_DEVICES	8
+
+static struct class *hd44780_class;
+static dev_t dev_no;
+/* We start with -1 so that first returned minor is 0 */
+static atomic_t next_minor = ATOMIC_INIT(-1);
+
+static LIST_HEAD(hd44780_list);
+static DEFINE_SPINLOCK(hd44780_list_lock);
+
+/* Device attributes */
+
+static ssize_t geometry_show(struct device *dev, struct device_attribute *attr,
+		char *buf)
+{
+	struct hd44780 *lcd;
+	struct hd44780_geometry *geo;
+	
+	lcd = dev_get_drvdata(dev);
+	geo = lcd->geometry;
+
+	return scnprintf(buf, PAGE_SIZE, "%dx%d\n", geo->cols, geo->rows);
+}
+
+static ssize_t geometry_store(struct device *dev,
+		struct device_attribute *attr, const char *buf, size_t count)
+{
+	struct hd44780 *lcd;
+	struct hd44780_geometry *geo;
+	int cols = 0, rows = 0, i;
+
+	sscanf(buf, "%dx%d", &cols, &rows);
+
+	for (i = 0; hd44780_geometries[i] != NULL; i++) {
+		geo = hd44780_geometries[i];
+
+		if (geo->cols == cols && geo->rows == rows) {
+			lcd = dev_get_drvdata(dev);
+
+			mutex_lock(&lcd->lock);
+			hd44780_set_geometry(lcd, geo);
+			mutex_unlock(&lcd->lock);
+
+			break;
+		}
+	}
+
+	return count;
+}
+static DEVICE_ATTR_RW(geometry);
+
+static ssize_t backlight_show(struct device *dev, struct device_attribute *attr,
+		char *buf)
+{
+	struct hd44780 *lcd = dev_get_drvdata(dev);
+
+	return scnprintf(buf, PAGE_SIZE, "%d\n", lcd->backlight);
+}
+
+static ssize_t backlight_store(struct device *dev,
+		struct device_attribute *attr, const char *buf, size_t count)
+{
+	struct hd44780 *lcd = dev_get_drvdata(dev);
+
+	mutex_lock(&lcd->lock);
+	hd44780_set_backlight(lcd, buf[0] == '1');
+	mutex_unlock(&lcd->lock);
+
+	return count;
+}
+static DEVICE_ATTR_RW(backlight);
+
+static ssize_t cursor_blink_show(struct device *dev, struct device_attribute *attr,
+		char *buf)
+{
+	struct hd44780 *lcd = dev_get_drvdata(dev);
+
+	return scnprintf(buf, PAGE_SIZE, "%d\n", lcd->cursor_blink);
+}
+
+static ssize_t cursor_blink_store(struct device *dev,
+		struct device_attribute *attr, const char *buf, size_t count)
+{
+	struct hd44780 *lcd = dev_get_drvdata(dev);
+
+	mutex_lock(&lcd->lock);
+	hd44780_set_cursor_blink(lcd, buf[0] == '1');
+	mutex_unlock(&lcd->lock);
+
+	return count;
+}
+static DEVICE_ATTR_RW(cursor_blink);
+
+static ssize_t cursor_display_show(struct device *dev, struct device_attribute *attr,
+		char *buf)
+{
+	struct hd44780 *lcd = dev_get_drvdata(dev);
+
+	return scnprintf(buf, PAGE_SIZE, "%d\n", lcd->cursor_display);
+}
+
+static ssize_t cursor_display_store(struct device *dev,
+		struct device_attribute *attr, const char *buf, size_t count)
+{
+	struct hd44780 *lcd = dev_get_drvdata(dev);
+
+	mutex_lock(&lcd->lock);
+	hd44780_set_cursor_display(lcd, buf[0] == '1');
+	mutex_unlock(&lcd->lock);
+
+	return count;
+}
+static DEVICE_ATTR_RW(cursor_display);
+
+static struct attribute *hd44780_device_attrs[] = {
+	&dev_attr_geometry.attr,
+	&dev_attr_backlight.attr,
+	&dev_attr_cursor_blink.attr,
+	&dev_attr_cursor_display.attr,
+	NULL
+};
+ATTRIBUTE_GROUPS(hd44780_device);
+
+/* File operations */
+
+static int hd44780_file_open(struct inode *inode, struct file *filp)
+{
+	filp->private_data = container_of(inode->i_cdev, struct hd44780, cdev);
+	return 0;
+}
+
+static int hd44780_file_release(struct inode *inode, struct file *filp)
+{
+	struct hd44780 *lcd = filp->private_data;
+	hd44780_flush(lcd);
+	return 0;
+}
+
+static ssize_t hd44780_file_write(struct file *filp, const char __user *buf, size_t count, loff_t *offp)
+{
+	struct hd44780 *lcd;
+	size_t n;
+
+	lcd = filp->private_data;
+	n = min(count, (size_t)BUF_SIZE);
+
+	// TODO: Consider using an interruptible lock
+	mutex_lock(&lcd->lock);
+
+	// TODO: Support partial writes during errors?
+	if (copy_from_user(lcd->buf, buf, n)) {
+		mutex_unlock(&lcd->lock);
+		return -EFAULT;
+	}
+
+	hd44780_write(lcd, lcd->buf, n);
+
+	mutex_unlock(&lcd->lock);
+
+	return n;
+}
+
+static void hd44780_init(struct hd44780 *lcd, struct hd44780_geometry *geometry,
+		struct i2c_client *i2c_client)
+{
+	lcd->geometry = geometry;
+	lcd->i2c_client = i2c_client;
+	lcd->pos.row = 0;
+	lcd->pos.col = 0;
+	memset(lcd->esc_seq_buf.buf, 0, ESC_SEQ_BUF_SIZE);
+	lcd->esc_seq_buf.length = 0;
+	lcd->is_in_esc_seq = false;
+	lcd->backlight = true;
+	lcd->cursor_blink = true;
+	lcd->cursor_display = true;
+	mutex_init(&lcd->lock);
+}
+
+static struct file_operations fops = {
+	.open = hd44780_file_open,
+	.release = hd44780_file_release,
+	.write = hd44780_file_write,
+};
+
+static int hd44780_probe(struct i2c_client *client, const struct i2c_device_id *id)
+{
+	dev_t devt;
+	struct hd44780 *lcd;
+	struct device *device;
+	int ret, minor;
+
+	minor = atomic_inc_return(&next_minor);
+	devt = MKDEV(MAJOR(dev_no), minor);
+
+	lcd = (struct hd44780 *)kmalloc(sizeof(struct hd44780), GFP_KERNEL);
+	if (!lcd) {
+		return -ENOMEM;
+	}
+
+	/* JHD1802, default resolution 16x2 */
+	hd44780_init(lcd, hd44780_geometries[1], client);
+
+	spin_lock(&hd44780_list_lock);
+	list_add(&lcd->list, &hd44780_list);
+	spin_unlock(&hd44780_list_lock);
+
+	cdev_init(&lcd->cdev, &fops);
+	ret = cdev_add(&lcd->cdev, devt, 1);
+	if (ret) {
+		pr_warn("Can't add cdev\n");
+		goto exit;
+	}
+
+	device = device_create_with_groups(hd44780_class, NULL, devt, NULL,
+		hd44780_device_groups, "lcd%d", MINOR(devt));
+
+	if (IS_ERR(device)) {
+		ret = PTR_ERR(device);
+		pr_warn("Can't create device\n");
+		goto del_exit;
+	}
+
+	dev_set_drvdata(device, lcd);
+	lcd->device = device;
+
+	hd44780_init_lcd(lcd);
+
+	hd44780_print(lcd, "Grove-16x2 LCD\nJHD1802M0");
+	lcd->dirty = true;
+	
+	return 0;
+
+del_exit:
+	cdev_del(&lcd->cdev);
+
+	spin_lock(&hd44780_list_lock);
+	list_del(&lcd->list);
+	spin_unlock(&hd44780_list_lock);
+exit:
+	kfree(lcd);
+
+	return ret;
+}
+
+static struct hd44780 * get_hd44780_by_i2c_client(struct i2c_client *i2c_client)
+{
+	struct hd44780 *lcd;
+
+	spin_lock(&hd44780_list_lock);
+	list_for_each_entry(lcd, &hd44780_list, list) {
+		if (lcd->i2c_client->addr == i2c_client->addr) {
+			spin_unlock(&hd44780_list_lock);
+			return lcd;
+		}
+	}
+	spin_unlock(&hd44780_list_lock);
+
+	return NULL;
+}
+
+
+static int hd44780_remove(struct i2c_client *client)
+{
+	struct hd44780 *lcd;
+	lcd = get_hd44780_by_i2c_client(client);
+	device_destroy(hd44780_class, lcd->device->devt);
+	cdev_del(&lcd->cdev);
+
+	spin_lock(&hd44780_list_lock);
+	list_del(&lcd->list);
+	spin_unlock(&hd44780_list_lock);
+
+	kfree(lcd);
+	
+	return 0;
+}
+
+static const struct i2c_device_id hd44780_id[] = {
+	{ NAME, 0},
+	{ }
+};
+MODULE_DEVICE_TABLE(i2c, hd44780_id);
+
+static struct i2c_driver hd44780_driver = {
+	.driver = {
+		.name	= NAME,
+		.owner	= THIS_MODULE,
+	},
+	.probe = hd44780_probe,
+	.remove = hd44780_remove,
+	.id_table = hd44780_id,
+};
+
+static int __init hd44780_mod_init(void)
+{
+	int ret;
+
+	ret = alloc_chrdev_region(&dev_no, 0, NUM_DEVICES, NAME);
+	if (ret) {
+		pr_warn("Can't allocate chardev region");
+		return ret;
+	}
+
+	hd44780_class = class_create(THIS_MODULE, CLASS_NAME);
+	if (IS_ERR(hd44780_class)) {
+		ret = PTR_ERR(hd44780_class);
+		pr_warn("Can't create %s class\n", CLASS_NAME);
+		goto exit;
+	}
+
+	ret = i2c_add_driver(&hd44780_driver);
+	if (ret) {
+		pr_warn("Can't register I2C driver %s\n", hd44780_driver.driver.name);
+		goto destroy_exit;
+	}
+
+	return 0;
+
+destroy_exit:
+	class_destroy(hd44780_class);
+exit:
+	unregister_chrdev_region(dev_no, NUM_DEVICES);
+
+	return ret;
+}
+module_init(hd44780_mod_init);
+
+static void __exit hd44780_mod_exit(void)
+{
+	i2c_del_driver(&hd44780_driver);
+	class_destroy(hd44780_class);
+	unregister_chrdev_region(dev_no, NUM_DEVICES);
+}
+module_exit(hd44780_mod_exit);
+
+MODULE_AUTHOR("Mariusz Gorski <marius.gorski@gmail.com>");
+MODULE_AUTHOR("Peter Yang <turmary@126.com>");
+MODULE_DESCRIPTION("JHD1802 HD44780 I2C driver");
+MODULE_LICENSE("GPL");
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/hd44780/hd44780.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/hd44780/hd44780.h
new file mode 100644
index 0000000000000000000000000000000000000000..0d0cedc66fbabdbeebce6557bb1b801a4dc36eeb
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/hd44780/hd44780.h
@@ -0,0 +1,52 @@
+#ifndef _HD44780_H_
+#define _HD44780_H_
+
+#define BUF_SIZE		64
+#define ESC_SEQ_BUF_SIZE	4
+
+struct hd44780_geometry {
+	int cols;
+	int rows;
+	int start_addrs[];
+};
+
+struct hd44780 {
+	struct cdev cdev;
+	struct device *device;
+	struct i2c_client *i2c_client;
+	struct hd44780_geometry *geometry;
+
+	/* Current cursor positon on the display */
+	struct {
+		int row;
+		int col;
+	} pos;
+
+	char buf[BUF_SIZE];
+	struct {
+		char buf[ESC_SEQ_BUF_SIZE];
+		int length;
+	} esc_seq_buf;
+	bool is_in_esc_seq;
+
+	bool backlight;
+	bool cursor_blink;
+	bool cursor_display;
+
+	bool dirty;
+
+	struct mutex lock;
+	struct list_head list;
+};
+
+void hd44780_write(struct hd44780 *, const char *, size_t);
+void hd44780_init_lcd(struct hd44780 *);
+void hd44780_print(struct hd44780 *, const char *);
+void hd44780_flush(struct hd44780 *);
+void hd44780_set_geometry(struct hd44780 *, struct hd44780_geometry *);
+void hd44780_set_backlight(struct hd44780 *, bool);
+void hd44780_set_cursor_blink(struct hd44780 *, bool);
+void hd44780_set_cursor_display(struct hd44780 *, bool);
+
+extern struct hd44780_geometry *hd44780_geometries[];
+#endif
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/lis3lv02d/Makefile b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/lis3lv02d/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..2dd0eaa5c66f87761b1b0aa04715e0e56bff42ed
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/lis3lv02d/Makefile
@@ -0,0 +1,47 @@
+#
+# Peter Yang <turmary@126.com>
+# Copyright (c) 2019 Seeed Studio
+#
+# MIT License
+#
+
+_tgt     := lis331dlh-i2c
+
+_uname_r := $(shell uname -r)
+_BUILD   := /lib/modules/$(_uname_r)/build
+_PWD     := $(shell pwd)
+_DEPMOD  ?= depmod -a
+
+# If KERNELRELEASE is defined, we've been invoked from the
+# kernel build system and can use its language
+ifneq ($(KERNELRELEASE),)
+
+# signal_pending compability
+ifneq ($(wildcard $(_BUILD)/include/linux/sched/signal.h),)
+ccflags-y += -DSCHED_SIGNAL_H=1
+endif
+
+lis331dlh-i2c-objs := lis3lv02d.o lis3lv02d_i2c.o
+obj-m += ${_tgt}.o
+
+else
+_class  := drivers/misc
+
+DEST  := /lib/modules/$(_uname_r)/kernel
+
+all:
+	make -C ${_BUILD} M=$(_PWD) modules
+
+clean:
+	make -C ${_BUILD} M=$(_PWD) clean
+
+install:
+	cp ${_tgt}.ko ${DEST}/${_class}/
+	$(_DEPMOD)
+
+uninstall:
+	rm -f ${DEST}/${_class}/${_tgt}.ko
+	$(_DEPMOD)
+
+.PHONY: all clean install uninstall
+endif
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/lis3lv02d/README.md b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/lis3lv02d/README.md
new file mode 100644
index 0000000000000000000000000000000000000000..0b807c5573b432218d496486d5794ef208051cec
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/lis3lv02d/README.md
@@ -0,0 +1,31 @@
+GROVE 3-Axis Digital Accelerometer (+-400g)
+===========================================
+
+  After driver and configuration prepared well,
+  the user could access ```/sys/bus/iio/devices/iio\:device<N>/XXX```,
+  to get the sensor data results.
+
+***
+
+Usage
+-----
+
+***example:***
+
+  ```bash
+  # check the device<N> name, make sure it's hcsr04
+  # where <N> is a number specific to your system.
+
+  $ cat /sys/bus/iio/devices/iio\:device3/name
+  lis331dlh
+    
+  # get the raw data
+  $ cd /sys/bus/iio/devices/iio\:device3/
+  $ cat in_accel_x_raw in_accel_y_raw in_accel_z_raw
+  3
+  10
+  -9
+  ```
+
+  If you need customize the I2C-Port..., change it the device tree source.
+
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/lis3lv02d/lis3lv02d.c b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/lis3lv02d/lis3lv02d.c
new file mode 100644
index 0000000000000000000000000000000000000000..4cdf3971ffb86af9de96e7b28f0e58854580f25a
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/lis3lv02d/lis3lv02d.c
@@ -0,0 +1,1266 @@
+/*
+ *  lis3lv02d.c - ST LIS3LV02DL accelerometer driver
+ *
+ *  Copyright (C) 2007-2008 Yan Burman
+ *  Copyright (C) 2008 Eric Piel
+ *  Copyright (C) 2008-2009 Pavel Machek
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
+
+#include <linux/kernel.h>
+#include <linux/dmi.h>
+#include <linux/module.h>
+#include <linux/types.h>
+#include <linux/platform_device.h>
+#include <linux/interrupt.h>
+#include <linux/input-polldev.h>
+#include <linux/delay.h>
+#include <linux/wait.h>
+#include <linux/poll.h>
+#include <linux/slab.h>
+#include <linux/freezer.h>
+#include <linux/uaccess.h>
+#include <linux/miscdevice.h>
+#include <linux/pm_runtime.h>
+#include <linux/atomic.h>
+#include <linux/of_device.h>
+#ifdef SCHED_SIGNAL_H
+/* linux v4.14 compability */
+#include <linux/sched/signal.h>
+#endif
+#include "lis3lv02d.h"
+
+#define DRIVER_NAME     "lis3lv02d"
+
+/* joystick device poll interval in milliseconds */
+#define MDPS_POLL_INTERVAL 50
+#define MDPS_POLL_MIN	   0
+#define MDPS_POLL_MAX	   2000
+
+#define LIS3_SYSFS_POWERDOWN_DELAY 5000 /* In milliseconds */
+
+#define SELFTEST_OK	       0
+#define SELFTEST_FAIL	       -1
+#define SELFTEST_IRQ	       -2
+
+#define IRQ_LINE0	       0
+#define IRQ_LINE1	       1
+
+/*
+ * The sensor can also generate interrupts (DRDY) but it's pretty pointless
+ * because they are generated even if the data do not change. So it's better
+ * to keep the interrupt for the free-fall event. The values are updated at
+ * 40Hz (at the lowest frequency), but as it can be pretty time consuming on
+ * some low processor, we poll the sensor only at 20Hz... enough for the
+ * joystick.
+ */
+
+#define LIS3_PWRON_DELAY_WAI_12B	(5000)
+#define LIS3_PWRON_DELAY_WAI_8B		(3000)
+
+/*
+ * LIS3LV02D spec says 1024 LSBs corresponds 1 G -> 1LSB is 1000/1024 mG
+ * LIS302D spec says: 18 mG / digit
+ * LIS3_ACCURACY is used to increase accuracy of the intermediate
+ * calculation results.
+ */
+#define LIS3_ACCURACY			1024
+/* Sensitivity values for -2G +2G scale */
+#define LIS3_SENSITIVITY_12B		((LIS3_ACCURACY * 1000) / 1024)
+#define LIS3_SENSITIVITY_8B		(18 * LIS3_ACCURACY)
+
+/*
+ * LIS331DLH spec says 1LSBs corresponds 4G/4096 -> 1LSB is 1000/1024 mG.
+ * Below macros defines sensitivity values for +/-2G. Dataout bits for
+ * +/-2G range is 12 bits so 4 bits adjustment must be done to get 12bit
+ * data from 16bit value. Currently this driver supports only 2G range.
+ */
+#define LIS3DLH_SENSITIVITY_2G		((LIS3_ACCURACY * 1000) / 1024)
+#define SHIFT_ADJ_2G			4
+
+#define LIS3_DEFAULT_FUZZ_12B		3
+#define LIS3_DEFAULT_FLAT_12B		3
+#define LIS3_DEFAULT_FUZZ_8B		1
+#define LIS3_DEFAULT_FLAT_8B		1
+
+struct lis3lv02d lis3_dev = {
+	.misc_wait   = __WAIT_QUEUE_HEAD_INITIALIZER(lis3_dev.misc_wait),
+};
+EXPORT_SYMBOL_GPL(lis3_dev);
+
+/* just like param_set_int() but does sanity-check so that it won't point
+ * over the axis array size
+ */
+static int param_set_axis(const char *val, const struct kernel_param *kp)
+{
+	int ret = param_set_int(val, kp);
+	if (!ret) {
+		int val = *(int *)kp->arg;
+		if (val < 0)
+			val = -val;
+		if (!val || val > 3)
+			return -EINVAL;
+	}
+	return ret;
+}
+
+static const struct kernel_param_ops param_ops_axis = {
+	.set = param_set_axis,
+	.get = param_get_int,
+};
+
+#define param_check_axis(name, p) param_check_int(name, p)
+
+module_param_array_named(axes, lis3_dev.ac.as_array, axis, NULL, 0644);
+MODULE_PARM_DESC(axes, "Axis-mapping for x,y,z directions");
+
+static s16 lis3lv02d_read_8(struct lis3lv02d *lis3, int reg)
+{
+	s8 lo;
+	if (lis3->read(lis3, reg, &lo) < 0)
+		return 0;
+
+	return lo;
+}
+
+static s16 lis3lv02d_read_12(struct lis3lv02d *lis3, int reg)
+{
+	u8 lo, hi;
+
+	lis3->read(lis3, reg - 1, &lo);
+	lis3->read(lis3, reg, &hi);
+	/* In "12 bit right justified" mode, bit 6, bit 7, bit 8 = bit 5 */
+	return (s16)((hi << 8) | lo);
+}
+
+/* 12bits for 2G range, 13 bits for 4G range and 14 bits for 8G range */
+static s16 lis331dlh_read_data(struct lis3lv02d *lis3, int reg)
+{
+	u8 lo, hi;
+	int v;
+
+	lis3->read(lis3, reg - 1, &lo);
+	lis3->read(lis3, reg, &hi);
+	v = (int) ((hi << 8) | lo);
+
+	return (s16) v >> lis3->shift_adj;
+}
+
+/**
+ * lis3lv02d_get_axis - For the given axis, give the value converted
+ * @axis:      1,2,3 - can also be negative
+ * @hw_values: raw values returned by the hardware
+ *
+ * Returns the converted value.
+ */
+static inline int lis3lv02d_get_axis(s8 axis, int hw_values[3])
+{
+	if (axis > 0)
+		return hw_values[axis - 1];
+	else
+		return -hw_values[-axis - 1];
+}
+
+/**
+ * lis3lv02d_get_xyz - Get X, Y and Z axis values from the accelerometer
+ * @lis3: pointer to the device struct
+ * @x:    where to store the X axis value
+ * @y:    where to store the Y axis value
+ * @z:    where to store the Z axis value
+ *
+ * Note that 40Hz input device can eat up about 10% CPU at 800MHZ
+ */
+static void lis3lv02d_get_xyz(struct lis3lv02d *lis3, int *x, int *y, int *z)
+{
+	int position[3];
+	int i;
+
+	if (lis3->blkread) {
+		if (lis3->whoami == WAI_12B) {
+			u16 data[3];
+			lis3->blkread(lis3, OUTX_L, 6, (u8 *)data);
+			for (i = 0; i < 3; i++)
+				position[i] = (s16)le16_to_cpu(data[i]);
+		} else {
+			u8 data[5];
+			/* Data: x, dummy, y, dummy, z */
+			lis3->blkread(lis3, OUTX, 5, data);
+			for (i = 0; i < 3; i++)
+				position[i] = (s8)data[i * 2];
+		}
+	} else {
+		position[0] = lis3->read_data(lis3, OUTX);
+		position[1] = lis3->read_data(lis3, OUTY);
+		position[2] = lis3->read_data(lis3, OUTZ);
+	}
+
+	for (i = 0; i < 3; i++)
+		position[i] = (position[i] * lis3->scale) / LIS3_ACCURACY;
+
+	*x = lis3lv02d_get_axis(lis3->ac.x, position);
+	*y = lis3lv02d_get_axis(lis3->ac.y, position);
+	*z = lis3lv02d_get_axis(lis3->ac.z, position);
+}
+
+/* conversion btw sampling rate and the register values */
+static int lis3_12_rates[4] = {40, 160, 640, 2560};
+static int lis3_8_rates[2] = {100, 400};
+static int lis3_3dc_rates[16] = {0, 1, 10, 25, 50, 100, 200, 400, 1600, 5000};
+static int lis3_3dlh_rates[4] = {50, 100, 400, 1000};
+
+/* ODR is Output Data Rate */
+static int lis3lv02d_get_odr(struct lis3lv02d *lis3)
+{
+	u8 ctrl;
+	int shift;
+
+	lis3->read(lis3, CTRL_REG1, &ctrl);
+	ctrl &= lis3->odr_mask;
+	shift = ffs(lis3->odr_mask) - 1;
+	return lis3->odrs[(ctrl >> shift)];
+}
+
+static int lis3lv02d_get_pwron_wait(struct lis3lv02d *lis3)
+{
+	int div = lis3lv02d_get_odr(lis3);
+
+	if (WARN_ONCE(div == 0, "device returned spurious data"))
+		return -ENXIO;
+
+	/* LIS3 power on delay is quite long */
+	msleep(lis3->pwron_delay / div);
+	return 0;
+}
+
+static int lis3lv02d_set_odr(struct lis3lv02d *lis3, int rate)
+{
+	u8 ctrl;
+	int i, len, shift;
+
+	if (!rate)
+		return -EINVAL;
+
+	lis3->read(lis3, CTRL_REG1, &ctrl);
+	ctrl &= ~lis3->odr_mask;
+	len = 1 << hweight_long(lis3->odr_mask); /* # of possible values */
+	shift = ffs(lis3->odr_mask) - 1;
+
+	for (i = 0; i < len; i++)
+		if (lis3->odrs[i] == rate) {
+			lis3->write(lis3, CTRL_REG1,
+					ctrl | (i << shift));
+			return 0;
+		}
+	return -EINVAL;
+}
+
+static int lis3lv02d_selftest(struct lis3lv02d *lis3, s16 results[3])
+{
+	u8 ctlreg, reg;
+	s16 x, y, z;
+	u8 selftest;
+	int ret;
+	u8 ctrl_reg_data;
+	unsigned char irq_cfg;
+
+	mutex_lock(&lis3->mutex);
+
+	irq_cfg = lis3->irq_cfg;
+	if (lis3->whoami == WAI_8B) {
+		lis3->data_ready_count[IRQ_LINE0] = 0;
+		lis3->data_ready_count[IRQ_LINE1] = 0;
+
+		/* Change interrupt cfg to data ready for selftest */
+		atomic_inc(&lis3->wake_thread);
+		lis3->irq_cfg = LIS3_IRQ1_DATA_READY | LIS3_IRQ2_DATA_READY;
+		lis3->read(lis3, CTRL_REG3, &ctrl_reg_data);
+		lis3->write(lis3, CTRL_REG3, (ctrl_reg_data &
+				~(LIS3_IRQ1_MASK | LIS3_IRQ2_MASK)) |
+				(LIS3_IRQ1_DATA_READY | LIS3_IRQ2_DATA_READY));
+	}
+
+	if ((lis3->whoami == WAI_3DC) || (lis3->whoami == WAI_3DLH)) {
+		ctlreg = CTRL_REG4;
+		selftest = CTRL4_ST0;
+	} else {
+		ctlreg = CTRL_REG1;
+		if (lis3->whoami == WAI_12B)
+			selftest = CTRL1_ST;
+		else
+			selftest = CTRL1_STP;
+	}
+
+	lis3->read(lis3, ctlreg, &reg);
+	lis3->write(lis3, ctlreg, (reg | selftest));
+	ret = lis3lv02d_get_pwron_wait(lis3);
+	if (ret)
+		goto fail;
+
+	/* Read directly to avoid axis remap */
+	x = lis3->read_data(lis3, OUTX);
+	y = lis3->read_data(lis3, OUTY);
+	z = lis3->read_data(lis3, OUTZ);
+
+	/* back to normal settings */
+	lis3->write(lis3, ctlreg, reg);
+	ret = lis3lv02d_get_pwron_wait(lis3);
+	if (ret)
+		goto fail;
+
+	results[0] = x - lis3->read_data(lis3, OUTX);
+	results[1] = y - lis3->read_data(lis3, OUTY);
+	results[2] = z - lis3->read_data(lis3, OUTZ);
+
+	ret = 0;
+
+	if (lis3->whoami == WAI_8B) {
+		/* Restore original interrupt configuration */
+		atomic_dec(&lis3->wake_thread);
+		lis3->write(lis3, CTRL_REG3, ctrl_reg_data);
+		lis3->irq_cfg = irq_cfg;
+
+		if ((irq_cfg & LIS3_IRQ1_MASK) &&
+			lis3->data_ready_count[IRQ_LINE0] < 2) {
+			ret = SELFTEST_IRQ;
+			goto fail;
+		}
+
+		if ((irq_cfg & LIS3_IRQ2_MASK) &&
+			lis3->data_ready_count[IRQ_LINE1] < 2) {
+			ret = SELFTEST_IRQ;
+			goto fail;
+		}
+	}
+
+	if (lis3->pdata) {
+		int i;
+		for (i = 0; i < 3; i++) {
+			/* Check against selftest acceptance limits */
+			if ((results[i] < lis3->pdata->st_min_limits[i]) ||
+			    (results[i] > lis3->pdata->st_max_limits[i])) {
+				ret = SELFTEST_FAIL;
+				goto fail;
+			}
+		}
+	}
+
+	/* test passed */
+fail:
+	mutex_unlock(&lis3->mutex);
+	return ret;
+}
+
+/*
+ * Order of registers in the list affects to order of the restore process.
+ * Perhaps it is a good idea to set interrupt enable register as a last one
+ * after all other configurations
+ */
+static u8 lis3_wai8_regs[] = { FF_WU_CFG_1, FF_WU_THS_1, FF_WU_DURATION_1,
+			       FF_WU_CFG_2, FF_WU_THS_2, FF_WU_DURATION_2,
+			       CLICK_CFG, CLICK_SRC, CLICK_THSY_X, CLICK_THSZ,
+			       CLICK_TIMELIMIT, CLICK_LATENCY, CLICK_WINDOW,
+			       CTRL_REG1, CTRL_REG2, CTRL_REG3};
+
+static u8 lis3_wai12_regs[] = {FF_WU_CFG, FF_WU_THS_L, FF_WU_THS_H,
+			       FF_WU_DURATION, DD_CFG, DD_THSI_L, DD_THSI_H,
+			       DD_THSE_L, DD_THSE_H,
+			       CTRL_REG1, CTRL_REG3, CTRL_REG2};
+
+static inline void lis3_context_save(struct lis3lv02d *lis3)
+{
+	int i;
+	for (i = 0; i < lis3->regs_size; i++)
+		lis3->read(lis3, lis3->regs[i], &lis3->reg_cache[i]);
+	lis3->regs_stored = true;
+}
+
+static inline void lis3_context_restore(struct lis3lv02d *lis3)
+{
+	int i;
+	if (lis3->regs_stored)
+		for (i = 0; i < lis3->regs_size; i++)
+			lis3->write(lis3, lis3->regs[i], lis3->reg_cache[i]);
+}
+
+void lis3lv02d_poweroff(struct lis3lv02d *lis3)
+{
+	if (lis3->reg_ctrl)
+		lis3_context_save(lis3);
+	/* disable X,Y,Z axis and power down */
+	lis3->write(lis3, CTRL_REG1, 0x00);
+	if (lis3->reg_ctrl)
+		lis3->reg_ctrl(lis3, LIS3_REG_OFF);
+}
+EXPORT_SYMBOL_GPL(lis3lv02d_poweroff);
+
+int lis3lv02d_poweron(struct lis3lv02d *lis3)
+{
+	int err;
+	u8 reg;
+
+	lis3->init(lis3);
+
+	/*
+	 * Common configuration
+	 * BDU: (12 bits sensors only) LSB and MSB values are not updated until
+	 *      both have been read. So the value read will always be correct.
+	 * Set BOOT bit to refresh factory tuning values.
+	 */
+	if (lis3->pdata) {
+		lis3->read(lis3, CTRL_REG2, &reg);
+		if (lis3->whoami ==  WAI_12B)
+			reg |= CTRL2_BDU | CTRL2_BOOT;
+		else if (lis3->whoami ==  WAI_3DLH)
+			reg |= CTRL2_BOOT_3DLH;
+		else
+			reg |= CTRL2_BOOT_8B;
+		lis3->write(lis3, CTRL_REG2, reg);
+
+		if (lis3->whoami ==  WAI_3DLH) {
+			lis3->read(lis3, CTRL_REG4, &reg);
+			reg |= CTRL4_BDU;
+			lis3->write(lis3, CTRL_REG4, reg);
+		}
+	}
+
+	err = lis3lv02d_get_pwron_wait(lis3);
+	if (err)
+		return err;
+
+	if (lis3->reg_ctrl)
+		lis3_context_restore(lis3);
+
+	return 0;
+}
+EXPORT_SYMBOL_GPL(lis3lv02d_poweron);
+
+
+static void lis3lv02d_joystick_poll(struct input_polled_dev *pidev)
+{
+	struct lis3lv02d *lis3 = pidev->private;
+	int x, y, z;
+
+	mutex_lock(&lis3->mutex);
+	lis3lv02d_get_xyz(lis3, &x, &y, &z);
+	input_report_abs(pidev->input, ABS_X, x);
+	input_report_abs(pidev->input, ABS_Y, y);
+	input_report_abs(pidev->input, ABS_Z, z);
+	input_sync(pidev->input);
+	mutex_unlock(&lis3->mutex);
+}
+
+static void lis3lv02d_joystick_open(struct input_polled_dev *pidev)
+{
+	struct lis3lv02d *lis3 = pidev->private;
+
+	if (lis3->pm_dev)
+		pm_runtime_get_sync(lis3->pm_dev);
+
+	if (lis3->pdata && lis3->whoami == WAI_8B && lis3->idev)
+		atomic_set(&lis3->wake_thread, 1);
+	/*
+	 * Update coordinates for the case where poll interval is 0 and
+	 * the chip in running purely under interrupt control
+	 */
+	lis3lv02d_joystick_poll(pidev);
+}
+
+static void lis3lv02d_joystick_close(struct input_polled_dev *pidev)
+{
+	struct lis3lv02d *lis3 = pidev->private;
+
+	atomic_set(&lis3->wake_thread, 0);
+	if (lis3->pm_dev)
+		pm_runtime_put(lis3->pm_dev);
+}
+
+static irqreturn_t lis302dl_interrupt(int irq, void *data)
+{
+	struct lis3lv02d *lis3 = data;
+
+	if (!test_bit(0, &lis3->misc_opened))
+		goto out;
+
+	/*
+	 * Be careful: on some HP laptops the bios force DD when on battery and
+	 * the lid is closed. This leads to interrupts as soon as a little move
+	 * is done.
+	 */
+	atomic_inc(&lis3->count);
+
+	wake_up_interruptible(&lis3->misc_wait);
+	kill_fasync(&lis3->async_queue, SIGIO, POLL_IN);
+out:
+	if (atomic_read(&lis3->wake_thread))
+		return IRQ_WAKE_THREAD;
+	return IRQ_HANDLED;
+}
+
+static void lis302dl_interrupt_handle_click(struct lis3lv02d *lis3)
+{
+	struct input_dev *dev = lis3->idev->input;
+	u8 click_src;
+
+	mutex_lock(&lis3->mutex);
+	lis3->read(lis3, CLICK_SRC, &click_src);
+
+	if (click_src & CLICK_SINGLE_X) {
+		input_report_key(dev, lis3->mapped_btns[0], 1);
+		input_report_key(dev, lis3->mapped_btns[0], 0);
+	}
+
+	if (click_src & CLICK_SINGLE_Y) {
+		input_report_key(dev, lis3->mapped_btns[1], 1);
+		input_report_key(dev, lis3->mapped_btns[1], 0);
+	}
+
+	if (click_src & CLICK_SINGLE_Z) {
+		input_report_key(dev, lis3->mapped_btns[2], 1);
+		input_report_key(dev, lis3->mapped_btns[2], 0);
+	}
+	input_sync(dev);
+	mutex_unlock(&lis3->mutex);
+}
+
+static inline void lis302dl_data_ready(struct lis3lv02d *lis3, int index)
+{
+	int dummy;
+
+	/* Dummy read to ack interrupt */
+	lis3lv02d_get_xyz(lis3, &dummy, &dummy, &dummy);
+	lis3->data_ready_count[index]++;
+}
+
+static irqreturn_t lis302dl_interrupt_thread1_8b(int irq, void *data)
+{
+	struct lis3lv02d *lis3 = data;
+	u8 irq_cfg = lis3->irq_cfg & LIS3_IRQ1_MASK;
+
+	if (irq_cfg == LIS3_IRQ1_CLICK)
+		lis302dl_interrupt_handle_click(lis3);
+	else if (unlikely(irq_cfg == LIS3_IRQ1_DATA_READY))
+		lis302dl_data_ready(lis3, IRQ_LINE0);
+	else
+		lis3lv02d_joystick_poll(lis3->idev);
+
+	return IRQ_HANDLED;
+}
+
+static irqreturn_t lis302dl_interrupt_thread2_8b(int irq, void *data)
+{
+	struct lis3lv02d *lis3 = data;
+	u8 irq_cfg = lis3->irq_cfg & LIS3_IRQ2_MASK;
+
+	if (irq_cfg == LIS3_IRQ2_CLICK)
+		lis302dl_interrupt_handle_click(lis3);
+	else if (unlikely(irq_cfg == LIS3_IRQ2_DATA_READY))
+		lis302dl_data_ready(lis3, IRQ_LINE1);
+	else
+		lis3lv02d_joystick_poll(lis3->idev);
+
+	return IRQ_HANDLED;
+}
+
+static int lis3lv02d_misc_open(struct inode *inode, struct file *file)
+{
+	struct lis3lv02d *lis3 = container_of(file->private_data,
+					      struct lis3lv02d, miscdev);
+
+	if (test_and_set_bit(0, &lis3->misc_opened))
+		return -EBUSY; /* already open */
+
+	if (lis3->pm_dev)
+		pm_runtime_get_sync(lis3->pm_dev);
+
+	atomic_set(&lis3->count, 0);
+	return 0;
+}
+
+static int lis3lv02d_misc_release(struct inode *inode, struct file *file)
+{
+	struct lis3lv02d *lis3 = container_of(file->private_data,
+					      struct lis3lv02d, miscdev);
+
+	clear_bit(0, &lis3->misc_opened); /* release the device */
+	if (lis3->pm_dev)
+		pm_runtime_put(lis3->pm_dev);
+	return 0;
+}
+
+static ssize_t lis3lv02d_misc_read(struct file *file, char __user *buf,
+				size_t count, loff_t *pos)
+{
+	struct lis3lv02d *lis3 = container_of(file->private_data,
+					      struct lis3lv02d, miscdev);
+
+	DECLARE_WAITQUEUE(wait, current);
+	u32 data;
+	unsigned char byte_data;
+	ssize_t retval = 1;
+
+	if (count < 1)
+		return -EINVAL;
+
+	add_wait_queue(&lis3->misc_wait, &wait);
+	while (true) {
+		set_current_state(TASK_INTERRUPTIBLE);
+		data = atomic_xchg(&lis3->count, 0);
+		if (data)
+			break;
+
+		if (file->f_flags & O_NONBLOCK) {
+			retval = -EAGAIN;
+			goto out;
+		}
+
+		if (signal_pending(current)) {
+			retval = -ERESTARTSYS;
+			goto out;
+		}
+
+		schedule();
+	}
+
+	if (data < 255)
+		byte_data = data;
+	else
+		byte_data = 255;
+
+	/* make sure we are not going into copy_to_user() with
+	 * TASK_INTERRUPTIBLE state */
+	set_current_state(TASK_RUNNING);
+	if (copy_to_user(buf, &byte_data, sizeof(byte_data)))
+		retval = -EFAULT;
+
+out:
+	__set_current_state(TASK_RUNNING);
+	remove_wait_queue(&lis3->misc_wait, &wait);
+
+	return retval;
+}
+
+static unsigned int lis3lv02d_misc_poll(struct file *file, poll_table *wait)
+{
+	struct lis3lv02d *lis3 = container_of(file->private_data,
+					      struct lis3lv02d, miscdev);
+
+	poll_wait(file, &lis3->misc_wait, wait);
+	if (atomic_read(&lis3->count))
+		return POLLIN | POLLRDNORM;
+	return 0;
+}
+
+static int lis3lv02d_misc_fasync(int fd, struct file *file, int on)
+{
+	struct lis3lv02d *lis3 = container_of(file->private_data,
+					      struct lis3lv02d, miscdev);
+
+	return fasync_helper(fd, file, on, &lis3->async_queue);
+}
+
+static const struct file_operations lis3lv02d_misc_fops = {
+	.owner   = THIS_MODULE,
+	.llseek  = no_llseek,
+	.read    = lis3lv02d_misc_read,
+	.open    = lis3lv02d_misc_open,
+	.release = lis3lv02d_misc_release,
+	.poll    = lis3lv02d_misc_poll,
+	.fasync  = lis3lv02d_misc_fasync,
+};
+
+int lis3lv02d_joystick_enable(struct lis3lv02d *lis3)
+{
+	struct input_dev *input_dev;
+	int err;
+	int max_val, fuzz, flat;
+	int btns[] = {BTN_X, BTN_Y, BTN_Z};
+
+	if (lis3->idev)
+		return -EINVAL;
+
+	lis3->idev = input_allocate_polled_device();
+	if (!lis3->idev)
+		return -ENOMEM;
+
+	lis3->idev->poll = lis3lv02d_joystick_poll;
+	lis3->idev->open = lis3lv02d_joystick_open;
+	lis3->idev->close = lis3lv02d_joystick_close;
+	lis3->idev->poll_interval = MDPS_POLL_INTERVAL;
+	lis3->idev->poll_interval_min = MDPS_POLL_MIN;
+	lis3->idev->poll_interval_max = MDPS_POLL_MAX;
+	lis3->idev->private = lis3;
+	input_dev = lis3->idev->input;
+
+	input_dev->name       = "ST LIS3LV02DL Accelerometer";
+	input_dev->phys       = DRIVER_NAME "/input0";
+	input_dev->id.bustype = BUS_HOST;
+	input_dev->id.vendor  = 0;
+	input_dev->dev.parent = &lis3->pdev->dev;
+
+	set_bit(EV_ABS, input_dev->evbit);
+	max_val = (lis3->mdps_max_val * lis3->scale) / LIS3_ACCURACY;
+	if (lis3->whoami == WAI_12B) {
+		fuzz = LIS3_DEFAULT_FUZZ_12B;
+		flat = LIS3_DEFAULT_FLAT_12B;
+	} else {
+		fuzz = LIS3_DEFAULT_FUZZ_8B;
+		flat = LIS3_DEFAULT_FLAT_8B;
+	}
+	fuzz = (fuzz * lis3->scale) / LIS3_ACCURACY;
+	flat = (flat * lis3->scale) / LIS3_ACCURACY;
+
+	input_set_abs_params(input_dev, ABS_X, -max_val, max_val, fuzz, flat);
+	input_set_abs_params(input_dev, ABS_Y, -max_val, max_val, fuzz, flat);
+	input_set_abs_params(input_dev, ABS_Z, -max_val, max_val, fuzz, flat);
+
+	lis3->mapped_btns[0] = lis3lv02d_get_axis(abs(lis3->ac.x), btns);
+	lis3->mapped_btns[1] = lis3lv02d_get_axis(abs(lis3->ac.y), btns);
+	lis3->mapped_btns[2] = lis3lv02d_get_axis(abs(lis3->ac.z), btns);
+
+	err = input_register_polled_device(lis3->idev);
+	if (err) {
+		input_free_polled_device(lis3->idev);
+		lis3->idev = NULL;
+	}
+
+	return err;
+}
+EXPORT_SYMBOL_GPL(lis3lv02d_joystick_enable);
+
+void lis3lv02d_joystick_disable(struct lis3lv02d *lis3)
+{
+	if (lis3->irq)
+		free_irq(lis3->irq, lis3);
+	if (lis3->pdata && lis3->pdata->irq2)
+		free_irq(lis3->pdata->irq2, lis3);
+
+	if (!lis3->idev)
+		return;
+
+	if (lis3->irq)
+		misc_deregister(&lis3->miscdev);
+	input_unregister_polled_device(lis3->idev);
+	input_free_polled_device(lis3->idev);
+	lis3->idev = NULL;
+}
+EXPORT_SYMBOL_GPL(lis3lv02d_joystick_disable);
+
+/* Sysfs stuff */
+static void lis3lv02d_sysfs_poweron(struct lis3lv02d *lis3)
+{
+	/*
+	 * SYSFS functions are fast visitors so put-call
+	 * immediately after the get-call. However, keep
+	 * chip running for a while and schedule delayed
+	 * suspend. This way periodic sysfs calls doesn't
+	 * suffer from relatively long power up time.
+	 */
+
+	if (lis3->pm_dev) {
+		pm_runtime_get_sync(lis3->pm_dev);
+		pm_runtime_put_noidle(lis3->pm_dev);
+		pm_schedule_suspend(lis3->pm_dev, LIS3_SYSFS_POWERDOWN_DELAY);
+	}
+}
+
+static ssize_t lis3lv02d_selftest_show(struct device *dev,
+				struct device_attribute *attr, char *buf)
+{
+	struct lis3lv02d *lis3 = dev_get_drvdata(dev);
+	s16 values[3];
+
+	static const char ok[] = "OK";
+	static const char fail[] = "FAIL";
+	static const char irq[] = "FAIL_IRQ";
+	const char *res;
+
+	lis3lv02d_sysfs_poweron(lis3);
+	switch (lis3lv02d_selftest(lis3, values)) {
+	case SELFTEST_FAIL:
+		res = fail;
+		break;
+	case SELFTEST_IRQ:
+		res = irq;
+		break;
+	case SELFTEST_OK:
+	default:
+		res = ok;
+		break;
+	}
+	return sprintf(buf, "%s %d %d %d\n", res,
+		values[0], values[1], values[2]);
+}
+
+static ssize_t lis3lv02d_position_show(struct device *dev,
+				struct device_attribute *attr, char *buf)
+{
+	struct lis3lv02d *lis3 = dev_get_drvdata(dev);
+	int x, y, z;
+
+	lis3lv02d_sysfs_poweron(lis3);
+	mutex_lock(&lis3->mutex);
+	lis3lv02d_get_xyz(lis3, &x, &y, &z);
+	mutex_unlock(&lis3->mutex);
+	return sprintf(buf, "(%d,%d,%d)\n", x, y, z);
+}
+
+static ssize_t lis3lv02d_rate_show(struct device *dev,
+			struct device_attribute *attr, char *buf)
+{
+	struct lis3lv02d *lis3 = dev_get_drvdata(dev);
+
+	lis3lv02d_sysfs_poweron(lis3);
+	return sprintf(buf, "%d\n", lis3lv02d_get_odr(lis3));
+}
+
+static ssize_t lis3lv02d_rate_set(struct device *dev,
+				struct device_attribute *attr, const char *buf,
+				size_t count)
+{
+	struct lis3lv02d *lis3 = dev_get_drvdata(dev);
+	unsigned long rate;
+	int ret;
+
+	ret = kstrtoul(buf, 0, &rate);
+	if (ret)
+		return ret;
+
+	lis3lv02d_sysfs_poweron(lis3);
+	if (lis3lv02d_set_odr(lis3, rate))
+		return -EINVAL;
+
+	return count;
+}
+
+static DEVICE_ATTR(selftest, S_IRUSR, lis3lv02d_selftest_show, NULL);
+static DEVICE_ATTR(position, S_IRUGO, lis3lv02d_position_show, NULL);
+static DEVICE_ATTR(rate, S_IRUGO | S_IWUSR, lis3lv02d_rate_show,
+					    lis3lv02d_rate_set);
+
+static struct attribute *lis3lv02d_attributes[] = {
+	&dev_attr_selftest.attr,
+	&dev_attr_position.attr,
+	&dev_attr_rate.attr,
+	NULL
+};
+
+static struct attribute_group lis3lv02d_attribute_group = {
+	.attrs = lis3lv02d_attributes
+};
+
+
+static int lis3lv02d_add_fs(struct lis3lv02d *lis3)
+{
+	lis3->pdev = platform_device_register_simple(DRIVER_NAME, -1, NULL, 0);
+	if (IS_ERR(lis3->pdev))
+		return PTR_ERR(lis3->pdev);
+
+	platform_set_drvdata(lis3->pdev, lis3);
+	return sysfs_create_group(&lis3->pdev->dev.kobj, &lis3lv02d_attribute_group);
+}
+
+int lis3lv02d_remove_fs(struct lis3lv02d *lis3)
+{
+	sysfs_remove_group(&lis3->pdev->dev.kobj, &lis3lv02d_attribute_group);
+	platform_device_unregister(lis3->pdev);
+	if (lis3->pm_dev) {
+		/* Barrier after the sysfs remove */
+		pm_runtime_barrier(lis3->pm_dev);
+
+		/* SYSFS may have left chip running. Turn off if necessary */
+		if (!pm_runtime_suspended(lis3->pm_dev))
+			lis3lv02d_poweroff(lis3);
+
+		pm_runtime_disable(lis3->pm_dev);
+		pm_runtime_set_suspended(lis3->pm_dev);
+	}
+	kfree(lis3->reg_cache);
+	return 0;
+}
+EXPORT_SYMBOL_GPL(lis3lv02d_remove_fs);
+
+static void lis3lv02d_8b_configure(struct lis3lv02d *lis3,
+				struct lis3lv02d_platform_data *p)
+{
+	int err;
+	int ctrl2 = p->hipass_ctrl;
+
+	if (p->click_flags) {
+		lis3->write(lis3, CLICK_CFG, p->click_flags);
+		lis3->write(lis3, CLICK_TIMELIMIT, p->click_time_limit);
+		lis3->write(lis3, CLICK_LATENCY, p->click_latency);
+		lis3->write(lis3, CLICK_WINDOW, p->click_window);
+		lis3->write(lis3, CLICK_THSZ, p->click_thresh_z & 0xf);
+		lis3->write(lis3, CLICK_THSY_X,
+			(p->click_thresh_x & 0xf) |
+			(p->click_thresh_y << 4));
+
+		if (lis3->idev) {
+			struct input_dev *input_dev = lis3->idev->input;
+			input_set_capability(input_dev, EV_KEY, BTN_X);
+			input_set_capability(input_dev, EV_KEY, BTN_Y);
+			input_set_capability(input_dev, EV_KEY, BTN_Z);
+		}
+	}
+
+	if (p->wakeup_flags) {
+		lis3->write(lis3, FF_WU_CFG_1, p->wakeup_flags);
+		lis3->write(lis3, FF_WU_THS_1, p->wakeup_thresh & 0x7f);
+		/* pdata value + 1 to keep this backward compatible*/
+		lis3->write(lis3, FF_WU_DURATION_1, p->duration1 + 1);
+		ctrl2 ^= HP_FF_WU1; /* Xor to keep compatible with old pdata*/
+	}
+
+	if (p->wakeup_flags2) {
+		lis3->write(lis3, FF_WU_CFG_2, p->wakeup_flags2);
+		lis3->write(lis3, FF_WU_THS_2, p->wakeup_thresh2 & 0x7f);
+		/* pdata value + 1 to keep this backward compatible*/
+		lis3->write(lis3, FF_WU_DURATION_2, p->duration2 + 1);
+		ctrl2 ^= HP_FF_WU2; /* Xor to keep compatible with old pdata*/
+	}
+	/* Configure hipass filters */
+	lis3->write(lis3, CTRL_REG2, ctrl2);
+
+	if (p->irq2) {
+		err = request_threaded_irq(p->irq2,
+					NULL,
+					lis302dl_interrupt_thread2_8b,
+					IRQF_TRIGGER_RISING | IRQF_ONESHOT |
+					(p->irq_flags2 & IRQF_TRIGGER_MASK),
+					DRIVER_NAME, lis3);
+		if (err < 0)
+			pr_err("No second IRQ. Limited functionality\n");
+	}
+}
+
+#ifdef CONFIG_OF
+int lis3lv02d_init_dt(struct lis3lv02d *lis3)
+{
+	struct lis3lv02d_platform_data *pdata;
+	struct device_node *np = lis3->of_node;
+	u32 val;
+	s32 sval;
+
+	if (!lis3->of_node)
+		return 0;
+
+	pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
+	if (!pdata)
+		return -ENOMEM;
+
+	if (of_get_property(np, "st,click-single-x", NULL))
+		pdata->click_flags |= LIS3_CLICK_SINGLE_X;
+	if (of_get_property(np, "st,click-double-x", NULL))
+		pdata->click_flags |= LIS3_CLICK_DOUBLE_X;
+
+	if (of_get_property(np, "st,click-single-y", NULL))
+		pdata->click_flags |= LIS3_CLICK_SINGLE_Y;
+	if (of_get_property(np, "st,click-double-y", NULL))
+		pdata->click_flags |= LIS3_CLICK_DOUBLE_Y;
+
+	if (of_get_property(np, "st,click-single-z", NULL))
+		pdata->click_flags |= LIS3_CLICK_SINGLE_Z;
+	if (of_get_property(np, "st,click-double-z", NULL))
+		pdata->click_flags |= LIS3_CLICK_DOUBLE_Z;
+
+	if (!of_property_read_u32(np, "st,click-threshold-x", &val))
+		pdata->click_thresh_x = val;
+	if (!of_property_read_u32(np, "st,click-threshold-y", &val))
+		pdata->click_thresh_y = val;
+	if (!of_property_read_u32(np, "st,click-threshold-z", &val))
+		pdata->click_thresh_z = val;
+
+	if (!of_property_read_u32(np, "st,click-time-limit", &val))
+		pdata->click_time_limit = val;
+	if (!of_property_read_u32(np, "st,click-latency", &val))
+		pdata->click_latency = val;
+	if (!of_property_read_u32(np, "st,click-window", &val))
+		pdata->click_window = val;
+
+	if (of_get_property(np, "st,irq1-disable", NULL))
+		pdata->irq_cfg |= LIS3_IRQ1_DISABLE;
+	if (of_get_property(np, "st,irq1-ff-wu-1", NULL))
+		pdata->irq_cfg |= LIS3_IRQ1_FF_WU_1;
+	if (of_get_property(np, "st,irq1-ff-wu-2", NULL))
+		pdata->irq_cfg |= LIS3_IRQ1_FF_WU_2;
+	if (of_get_property(np, "st,irq1-data-ready", NULL))
+		pdata->irq_cfg |= LIS3_IRQ1_DATA_READY;
+	if (of_get_property(np, "st,irq1-click", NULL))
+		pdata->irq_cfg |= LIS3_IRQ1_CLICK;
+
+	if (of_get_property(np, "st,irq2-disable", NULL))
+		pdata->irq_cfg |= LIS3_IRQ2_DISABLE;
+	if (of_get_property(np, "st,irq2-ff-wu-1", NULL))
+		pdata->irq_cfg |= LIS3_IRQ2_FF_WU_1;
+	if (of_get_property(np, "st,irq2-ff-wu-2", NULL))
+		pdata->irq_cfg |= LIS3_IRQ2_FF_WU_2;
+	if (of_get_property(np, "st,irq2-data-ready", NULL))
+		pdata->irq_cfg |= LIS3_IRQ2_DATA_READY;
+	if (of_get_property(np, "st,irq2-click", NULL))
+		pdata->irq_cfg |= LIS3_IRQ2_CLICK;
+
+	if (of_get_property(np, "st,irq-open-drain", NULL))
+		pdata->irq_cfg |= LIS3_IRQ_OPEN_DRAIN;
+	if (of_get_property(np, "st,irq-active-low", NULL))
+		pdata->irq_cfg |= LIS3_IRQ_ACTIVE_LOW;
+
+	if (!of_property_read_u32(np, "st,wu-duration-1", &val))
+		pdata->duration1 = val;
+	if (!of_property_read_u32(np, "st,wu-duration-2", &val))
+		pdata->duration2 = val;
+
+	if (of_get_property(np, "st,wakeup-x-lo", NULL))
+		pdata->wakeup_flags |= LIS3_WAKEUP_X_LO;
+	if (of_get_property(np, "st,wakeup-x-hi", NULL))
+		pdata->wakeup_flags |= LIS3_WAKEUP_X_HI;
+	if (of_get_property(np, "st,wakeup-y-lo", NULL))
+		pdata->wakeup_flags |= LIS3_WAKEUP_Y_LO;
+	if (of_get_property(np, "st,wakeup-y-hi", NULL))
+		pdata->wakeup_flags |= LIS3_WAKEUP_Y_HI;
+	if (of_get_property(np, "st,wakeup-z-lo", NULL))
+		pdata->wakeup_flags |= LIS3_WAKEUP_Z_LO;
+	if (of_get_property(np, "st,wakeup-z-hi", NULL))
+		pdata->wakeup_flags |= LIS3_WAKEUP_Z_HI;
+	if (of_get_property(np, "st,wakeup-threshold", &val))
+		pdata->wakeup_thresh = val;
+
+	if (of_get_property(np, "st,wakeup2-x-lo", NULL))
+		pdata->wakeup_flags2 |= LIS3_WAKEUP_X_LO;
+	if (of_get_property(np, "st,wakeup2-x-hi", NULL))
+		pdata->wakeup_flags2 |= LIS3_WAKEUP_X_HI;
+	if (of_get_property(np, "st,wakeup2-y-lo", NULL))
+		pdata->wakeup_flags2 |= LIS3_WAKEUP_Y_LO;
+	if (of_get_property(np, "st,wakeup2-y-hi", NULL))
+		pdata->wakeup_flags2 |= LIS3_WAKEUP_Y_HI;
+	if (of_get_property(np, "st,wakeup2-z-lo", NULL))
+		pdata->wakeup_flags2 |= LIS3_WAKEUP_Z_LO;
+	if (of_get_property(np, "st,wakeup2-z-hi", NULL))
+		pdata->wakeup_flags2 |= LIS3_WAKEUP_Z_HI;
+	if (of_get_property(np, "st,wakeup2-threshold", &val))
+		pdata->wakeup_thresh2 = val;
+
+	if (!of_property_read_u32(np, "st,highpass-cutoff-hz", &val)) {
+		switch (val) {
+		case 1:
+			pdata->hipass_ctrl = LIS3_HIPASS_CUTFF_1HZ;
+			break;
+		case 2:
+			pdata->hipass_ctrl = LIS3_HIPASS_CUTFF_2HZ;
+			break;
+		case 4:
+			pdata->hipass_ctrl = LIS3_HIPASS_CUTFF_4HZ;
+			break;
+		case 8:
+			pdata->hipass_ctrl = LIS3_HIPASS_CUTFF_8HZ;
+			break;
+		}
+	}
+
+	if (of_get_property(np, "st,hipass1-disable", NULL))
+		pdata->hipass_ctrl |= LIS3_HIPASS1_DISABLE;
+	if (of_get_property(np, "st,hipass2-disable", NULL))
+		pdata->hipass_ctrl |= LIS3_HIPASS2_DISABLE;
+
+	if (of_property_read_s32(np, "st,axis-x", &sval) == 0)
+		pdata->axis_x = sval;
+	if (of_property_read_s32(np, "st,axis-y", &sval) == 0)
+		pdata->axis_y = sval;
+	if (of_property_read_s32(np, "st,axis-z", &sval) == 0)
+		pdata->axis_z = sval;
+
+	if (of_get_property(np, "st,default-rate", NULL))
+		pdata->default_rate = val;
+
+	if (of_property_read_s32(np, "st,min-limit-x", &sval) == 0)
+		pdata->st_min_limits[0] = sval;
+	if (of_property_read_s32(np, "st,min-limit-y", &sval) == 0)
+		pdata->st_min_limits[1] = sval;
+	if (of_property_read_s32(np, "st,min-limit-z", &sval) == 0)
+		pdata->st_min_limits[2] = sval;
+
+	if (of_property_read_s32(np, "st,max-limit-x", &sval) == 0)
+		pdata->st_max_limits[0] = sval;
+	if (of_property_read_s32(np, "st,max-limit-y", &sval) == 0)
+		pdata->st_max_limits[1] = sval;
+	if (of_property_read_s32(np, "st,max-limit-z", &sval) == 0)
+		pdata->st_max_limits[2] = sval;
+
+
+	lis3->pdata = pdata;
+
+	return 0;
+}
+
+#else
+int lis3lv02d_init_dt(struct lis3lv02d *lis3)
+{
+	return 0;
+}
+#endif
+EXPORT_SYMBOL_GPL(lis3lv02d_init_dt);
+
+/*
+ * Initialise the accelerometer and the various subsystems.
+ * Should be rather independent of the bus system.
+ */
+int lis3lv02d_init_device(struct lis3lv02d *lis3)
+{
+	int err;
+	irq_handler_t thread_fn;
+	int irq_flags = 0;
+
+	lis3->whoami = lis3lv02d_read_8(lis3, WHO_AM_I);
+
+	switch (lis3->whoami) {
+	case WAI_12B:
+		pr_info("12 bits sensor found\n");
+		lis3->read_data = lis3lv02d_read_12;
+		lis3->mdps_max_val = 2048;
+		lis3->pwron_delay = LIS3_PWRON_DELAY_WAI_12B;
+		lis3->odrs = lis3_12_rates;
+		lis3->odr_mask = CTRL1_DF0 | CTRL1_DF1;
+		lis3->scale = LIS3_SENSITIVITY_12B;
+		lis3->regs = lis3_wai12_regs;
+		lis3->regs_size = ARRAY_SIZE(lis3_wai12_regs);
+		break;
+	case WAI_8B:
+		pr_info("8 bits sensor found\n");
+		lis3->read_data = lis3lv02d_read_8;
+		lis3->mdps_max_val = 128;
+		lis3->pwron_delay = LIS3_PWRON_DELAY_WAI_8B;
+		lis3->odrs = lis3_8_rates;
+		lis3->odr_mask = CTRL1_DR;
+		lis3->scale = LIS3_SENSITIVITY_8B;
+		lis3->regs = lis3_wai8_regs;
+		lis3->regs_size = ARRAY_SIZE(lis3_wai8_regs);
+		break;
+	case WAI_3DC:
+		pr_info("8 bits 3DC sensor found\n");
+		lis3->read_data = lis3lv02d_read_8;
+		lis3->mdps_max_val = 128;
+		lis3->pwron_delay = LIS3_PWRON_DELAY_WAI_8B;
+		lis3->odrs = lis3_3dc_rates;
+		lis3->odr_mask = CTRL1_ODR0|CTRL1_ODR1|CTRL1_ODR2|CTRL1_ODR3;
+		lis3->scale = LIS3_SENSITIVITY_8B;
+		break;
+	case WAI_3DLH:
+		pr_info("16 bits lis331dlh sensor found\n");
+		lis3->read_data = lis331dlh_read_data;
+		lis3->mdps_max_val = 2048; /* 12 bits for 2G */
+		lis3->shift_adj = SHIFT_ADJ_2G;
+		lis3->pwron_delay = LIS3_PWRON_DELAY_WAI_8B;
+		lis3->odrs = lis3_3dlh_rates;
+		lis3->odr_mask = CTRL1_DR0 | CTRL1_DR1;
+		lis3->scale = LIS3DLH_SENSITIVITY_2G;
+		break;
+	default:
+		pr_err("unknown sensor type 0x%X\n", lis3->whoami);
+		return -EINVAL;
+	}
+
+	lis3->reg_cache = kzalloc(max(sizeof(lis3_wai8_regs),
+				     sizeof(lis3_wai12_regs)), GFP_KERNEL);
+
+	if (lis3->reg_cache == NULL) {
+		printk(KERN_ERR DRIVER_NAME "out of memory\n");
+		return -ENOMEM;
+	}
+
+	mutex_init(&lis3->mutex);
+	atomic_set(&lis3->wake_thread, 0);
+
+	lis3lv02d_add_fs(lis3);
+	err = lis3lv02d_poweron(lis3);
+	if (err) {
+		lis3lv02d_remove_fs(lis3);
+		return err;
+	}
+
+	if (lis3->pm_dev) {
+		pm_runtime_set_active(lis3->pm_dev);
+		pm_runtime_enable(lis3->pm_dev);
+	}
+
+	if (lis3lv02d_joystick_enable(lis3))
+		pr_err("joystick initialization failed\n");
+
+	/* passing in platform specific data is purely optional and only
+	 * used by the SPI transport layer at the moment */
+	if (lis3->pdata) {
+		struct lis3lv02d_platform_data *p = lis3->pdata;
+
+		if (lis3->whoami == WAI_8B)
+			lis3lv02d_8b_configure(lis3, p);
+
+		irq_flags = p->irq_flags1 & IRQF_TRIGGER_MASK;
+
+		lis3->irq_cfg = p->irq_cfg;
+		if (p->irq_cfg)
+			lis3->write(lis3, CTRL_REG3, p->irq_cfg);
+
+		if (p->default_rate)
+			lis3lv02d_set_odr(lis3, p->default_rate);
+	}
+
+	/* bail if we did not get an IRQ from the bus layer */
+	if (!lis3->irq) {
+		pr_debug("No IRQ. Disabling /dev/freefall\n");
+		goto out;
+	}
+
+	/*
+	 * The sensor can generate interrupts for free-fall and direction
+	 * detection (distinguishable with FF_WU_SRC and DD_SRC) but to keep
+	 * the things simple and _fast_ we activate it only for free-fall, so
+	 * no need to read register (very slow with ACPI). For the same reason,
+	 * we forbid shared interrupts.
+	 *
+	 * IRQF_TRIGGER_RISING seems pointless on HP laptops because the
+	 * io-apic is not configurable (and generates a warning) but I keep it
+	 * in case of support for other hardware.
+	 */
+	if (lis3->pdata && lis3->whoami == WAI_8B)
+		thread_fn = lis302dl_interrupt_thread1_8b;
+	else
+		thread_fn = NULL;
+
+	err = request_threaded_irq(lis3->irq, lis302dl_interrupt,
+				thread_fn,
+				IRQF_TRIGGER_RISING | IRQF_ONESHOT |
+				irq_flags,
+				DRIVER_NAME, lis3);
+
+	if (err < 0) {
+		pr_err("Cannot get IRQ\n");
+		goto out;
+	}
+
+	lis3->miscdev.minor	= MISC_DYNAMIC_MINOR;
+	lis3->miscdev.name	= "freefall";
+	lis3->miscdev.fops	= &lis3lv02d_misc_fops;
+
+	if (misc_register(&lis3->miscdev))
+		pr_err("misc_register failed\n");
+out:
+	return 0;
+}
+EXPORT_SYMBOL_GPL(lis3lv02d_init_device);
+
+MODULE_DESCRIPTION("ST LIS3LV02Dx three-axis digital accelerometer driver");
+MODULE_AUTHOR("Yan Burman, Eric Piel, Pavel Machek");
+MODULE_LICENSE("GPL");
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/lis3lv02d/lis3lv02d.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/lis3lv02d/lis3lv02d.h
new file mode 100644
index 0000000000000000000000000000000000000000..c439c827eea803b887b678bb00b8a42790413af8
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/lis3lv02d/lis3lv02d.h
@@ -0,0 +1,331 @@
+/*
+ *  lis3lv02d.h - ST LIS3LV02DL accelerometer driver
+ *
+ *  Copyright (C) 2007-2008 Yan Burman
+ *  Copyright (C) 2008-2009 Eric Piel
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#include <linux/platform_device.h>
+#include <linux/input-polldev.h>
+#include <linux/regulator/consumer.h>
+#include <linux/miscdevice.h>
+
+/*
+ * This driver tries to support the "digital" accelerometer chips from
+ * STMicroelectronics such as LIS3LV02DL, LIS302DL, LIS3L02DQ, LIS331DL,
+ * LIS331DLH, LIS35DE, or LIS202DL. They are very similar in terms of
+ * programming, with almost the same registers. In addition to differing
+ * on physical properties, they differ on the number of axes (2/3),
+ * precision (8/12 bits), and special features (freefall detection,
+ * click...). Unfortunately, not all the differences can be probed via
+ * a register. They can be connected either via I²C or SPI.
+ */
+
+#include <linux/lis3lv02d.h>
+
+enum lis3_reg {
+	WHO_AM_I	= 0x0F,
+	OFFSET_X	= 0x16,
+	OFFSET_Y	= 0x17,
+	OFFSET_Z	= 0x18,
+	GAIN_X		= 0x19,
+	GAIN_Y		= 0x1A,
+	GAIN_Z		= 0x1B,
+	CTRL_REG1	= 0x20,
+	CTRL_REG2	= 0x21,
+	CTRL_REG3	= 0x22,
+	CTRL_REG4	= 0x23,
+	HP_FILTER_RESET	= 0x23,
+	STATUS_REG	= 0x27,
+	OUTX_L		= 0x28,
+	OUTX_H		= 0x29,
+	OUTX		= 0x29,
+	OUTY_L		= 0x2A,
+	OUTY_H		= 0x2B,
+	OUTY		= 0x2B,
+	OUTZ_L		= 0x2C,
+	OUTZ_H		= 0x2D,
+	OUTZ		= 0x2D,
+};
+
+enum lis302d_reg {
+	FF_WU_CFG_1	= 0x30,
+	FF_WU_SRC_1	= 0x31,
+	FF_WU_THS_1	= 0x32,
+	FF_WU_DURATION_1 = 0x33,
+	FF_WU_CFG_2	= 0x34,
+	FF_WU_SRC_2	= 0x35,
+	FF_WU_THS_2	= 0x36,
+	FF_WU_DURATION_2 = 0x37,
+	CLICK_CFG	= 0x38,
+	CLICK_SRC	= 0x39,
+	CLICK_THSY_X	= 0x3B,
+	CLICK_THSZ	= 0x3C,
+	CLICK_TIMELIMIT	= 0x3D,
+	CLICK_LATENCY	= 0x3E,
+	CLICK_WINDOW	= 0x3F,
+};
+
+enum lis3lv02d_reg {
+	FF_WU_CFG	= 0x30,
+	FF_WU_SRC	= 0x31,
+	FF_WU_ACK	= 0x32,
+	FF_WU_THS_L	= 0x34,
+	FF_WU_THS_H	= 0x35,
+	FF_WU_DURATION	= 0x36,
+	DD_CFG		= 0x38,
+	DD_SRC		= 0x39,
+	DD_ACK		= 0x3A,
+	DD_THSI_L	= 0x3C,
+	DD_THSI_H	= 0x3D,
+	DD_THSE_L	= 0x3E,
+	DD_THSE_H	= 0x3F,
+};
+
+enum lis3_who_am_i {
+	WAI_3DLH	= 0x32,	/* 16 bits: LIS331DLH */
+	WAI_3DC		= 0x33,	/* 8 bits: LIS3DC, HP3DC */
+	WAI_12B		= 0x3A, /* 12 bits: LIS3LV02D[LQ]... */
+	WAI_8B		= 0x3B, /* 8 bits: LIS[23]02D[LQ]... */
+	WAI_6B		= 0x52, /* 6 bits: LIS331DLF - not supported */
+};
+
+enum lis3_type {
+	LIS3LV02D,
+	LIS3DC,
+	HP3DC,
+	LIS2302D,
+	LIS331DLF,
+	LIS331DLH,
+};
+
+enum lis3lv02d_ctrl1_12b {
+	CTRL1_Xen	= 0x01,
+	CTRL1_Yen	= 0x02,
+	CTRL1_Zen	= 0x04,
+	CTRL1_ST	= 0x08,
+	CTRL1_DF0	= 0x10,
+	CTRL1_DF1	= 0x20,
+	CTRL1_PD0	= 0x40,
+	CTRL1_PD1	= 0x80,
+};
+
+/* Delta to ctrl1_12b version */
+enum lis3lv02d_ctrl1_8b {
+	CTRL1_STM	= 0x08,
+	CTRL1_STP	= 0x10,
+	CTRL1_FS	= 0x20,
+	CTRL1_PD	= 0x40,
+	CTRL1_DR	= 0x80,
+};
+
+enum lis3lv02d_ctrl1_3dc {
+	CTRL1_ODR0	= 0x10,
+	CTRL1_ODR1	= 0x20,
+	CTRL1_ODR2	= 0x40,
+	CTRL1_ODR3	= 0x80,
+};
+
+enum lis331dlh_ctrl1 {
+	CTRL1_DR0	= 0x08,
+	CTRL1_DR1	= 0x10,
+	CTRL1_PM0	= 0x20,
+	CTRL1_PM1	= 0x40,
+	CTRL1_PM2	= 0x80,
+};
+
+enum lis331dlh_ctrl2 {
+	CTRL2_HPEN1	= 0x04,
+	CTRL2_HPEN2	= 0x08,
+	CTRL2_FDS_3DLH	= 0x10,
+	CTRL2_BOOT_3DLH	= 0x80,
+};
+
+enum lis331dlh_ctrl4 {
+	CTRL4_STSIGN	= 0x08,
+	CTRL4_BLE	= 0x40,
+	CTRL4_BDU	= 0x80,
+};
+
+enum lis3lv02d_ctrl2 {
+	CTRL2_DAS	= 0x01,
+	CTRL2_SIM	= 0x02,
+	CTRL2_DRDY	= 0x04,
+	CTRL2_IEN	= 0x08,
+	CTRL2_BOOT	= 0x10,
+	CTRL2_BLE	= 0x20,
+	CTRL2_BDU	= 0x40, /* Block Data Update */
+	CTRL2_FS	= 0x80, /* Full Scale selection */
+};
+
+enum lis3lv02d_ctrl4_3dc {
+	CTRL4_SIM	= 0x01,
+	CTRL4_ST0	= 0x02,
+	CTRL4_ST1	= 0x04,
+	CTRL4_FS0	= 0x10,
+	CTRL4_FS1	= 0x20,
+};
+
+enum lis302d_ctrl2 {
+	HP_FF_WU2	= 0x08,
+	HP_FF_WU1	= 0x04,
+	CTRL2_BOOT_8B   = 0x40,
+};
+
+enum lis3lv02d_ctrl3 {
+	CTRL3_CFS0	= 0x01,
+	CTRL3_CFS1	= 0x02,
+	CTRL3_FDS	= 0x10,
+	CTRL3_HPFF	= 0x20,
+	CTRL3_HPDD	= 0x40,
+	CTRL3_ECK	= 0x80,
+};
+
+enum lis3lv02d_status_reg {
+	STATUS_XDA	= 0x01,
+	STATUS_YDA	= 0x02,
+	STATUS_ZDA	= 0x04,
+	STATUS_XYZDA	= 0x08,
+	STATUS_XOR	= 0x10,
+	STATUS_YOR	= 0x20,
+	STATUS_ZOR	= 0x40,
+	STATUS_XYZOR	= 0x80,
+};
+
+enum lis3lv02d_ff_wu_cfg {
+	FF_WU_CFG_XLIE	= 0x01,
+	FF_WU_CFG_XHIE	= 0x02,
+	FF_WU_CFG_YLIE	= 0x04,
+	FF_WU_CFG_YHIE	= 0x08,
+	FF_WU_CFG_ZLIE	= 0x10,
+	FF_WU_CFG_ZHIE	= 0x20,
+	FF_WU_CFG_LIR	= 0x40,
+	FF_WU_CFG_AOI	= 0x80,
+};
+
+enum lis3lv02d_ff_wu_src {
+	FF_WU_SRC_XL	= 0x01,
+	FF_WU_SRC_XH	= 0x02,
+	FF_WU_SRC_YL	= 0x04,
+	FF_WU_SRC_YH	= 0x08,
+	FF_WU_SRC_ZL	= 0x10,
+	FF_WU_SRC_ZH	= 0x20,
+	FF_WU_SRC_IA	= 0x40,
+};
+
+enum lis3lv02d_dd_cfg {
+	DD_CFG_XLIE	= 0x01,
+	DD_CFG_XHIE	= 0x02,
+	DD_CFG_YLIE	= 0x04,
+	DD_CFG_YHIE	= 0x08,
+	DD_CFG_ZLIE	= 0x10,
+	DD_CFG_ZHIE	= 0x20,
+	DD_CFG_LIR	= 0x40,
+	DD_CFG_IEND	= 0x80,
+};
+
+enum lis3lv02d_dd_src {
+	DD_SRC_XL	= 0x01,
+	DD_SRC_XH	= 0x02,
+	DD_SRC_YL	= 0x04,
+	DD_SRC_YH	= 0x08,
+	DD_SRC_ZL	= 0x10,
+	DD_SRC_ZH	= 0x20,
+	DD_SRC_IA	= 0x40,
+};
+
+enum lis3lv02d_click_src_8b {
+	CLICK_SINGLE_X	= 0x01,
+	CLICK_DOUBLE_X	= 0x02,
+	CLICK_SINGLE_Y	= 0x04,
+	CLICK_DOUBLE_Y	= 0x08,
+	CLICK_SINGLE_Z	= 0x10,
+	CLICK_DOUBLE_Z	= 0x20,
+	CLICK_IA	= 0x40,
+};
+
+enum lis3lv02d_reg_state {
+	LIS3_REG_OFF	= 0x00,
+	LIS3_REG_ON	= 0x01,
+};
+
+union axis_conversion {
+	struct {
+		int x, y, z;
+	};
+	int as_array[3];
+
+};
+
+struct lis3lv02d {
+	void			*bus_priv; /* used by the bus layer only */
+	struct device		*pm_dev; /* for pm_runtime purposes */
+	int (*init) (struct lis3lv02d *lis3);
+	int (*write) (struct lis3lv02d *lis3, int reg, u8 val);
+	int (*read) (struct lis3lv02d *lis3, int reg, u8 *ret);
+	int (*blkread) (struct lis3lv02d *lis3, int reg, int len, u8 *ret);
+	int (*reg_ctrl) (struct lis3lv02d *lis3, bool state);
+
+	int                     *odrs;     /* Supported output data rates */
+	u8			*regs;	   /* Regs to store / restore */
+	int			regs_size;
+	u8                      *reg_cache;
+	bool			regs_stored;
+	u8                      odr_mask;  /* ODR bit mask */
+	u8			whoami;    /* indicates measurement precision */
+	s16 (*read_data) (struct lis3lv02d *lis3, int reg);
+	int			mdps_max_val;
+	int			pwron_delay;
+	int                     scale; /*
+					* relationship between 1 LBS and mG
+					* (1/1000th of earth gravity)
+					*/
+
+	struct input_polled_dev	*idev;     /* input device */
+	struct platform_device	*pdev;     /* platform device */
+	struct regulator_bulk_data regulators[2];
+	atomic_t		count;     /* interrupt count after last read */
+	union axis_conversion	ac;        /* hw -> logical axis */
+	int			mapped_btns[3];
+
+	u32			irq;       /* IRQ number */
+	struct fasync_struct	*async_queue; /* queue for the misc device */
+	wait_queue_head_t	misc_wait; /* Wait queue for the misc device */
+	unsigned long		misc_opened; /* bit0: whether the device is open */
+	struct miscdevice	miscdev;
+
+	int                     data_ready_count[2];
+	atomic_t		wake_thread;
+	unsigned char           irq_cfg;
+	unsigned int		shift_adj;
+
+	struct lis3lv02d_platform_data *pdata;	/* for passing board config */
+	struct mutex		mutex;     /* Serialize poll and selftest */
+
+#ifdef CONFIG_OF
+	struct device_node	*of_node;
+#endif
+};
+
+int lis3lv02d_init_device(struct lis3lv02d *lis3);
+int lis3lv02d_joystick_enable(struct lis3lv02d *lis3);
+void lis3lv02d_joystick_disable(struct lis3lv02d *lis3);
+void lis3lv02d_poweroff(struct lis3lv02d *lis3);
+int lis3lv02d_poweron(struct lis3lv02d *lis3);
+int lis3lv02d_remove_fs(struct lis3lv02d *lis3);
+int lis3lv02d_init_dt(struct lis3lv02d *lis3);
+
+extern struct lis3lv02d lis3_dev;
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/lis3lv02d/lis3lv02d_i2c.c b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/lis3lv02d/lis3lv02d_i2c.c
new file mode 100644
index 0000000000000000000000000000000000000000..14b7d539fed6882aa2d82c200afd9c4093a2e351
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/lis3lv02d/lis3lv02d_i2c.c
@@ -0,0 +1,289 @@
+/*
+ * drivers/hwmon/lis3lv02d_i2c.c
+ *
+ * Implements I2C interface for lis3lv02d (STMicroelectronics) accelerometer.
+ * Driver is based on corresponding SPI driver written by Daniel Mack
+ * (lis3lv02d_spi.c (C) 2009 Daniel Mack <daniel@caiaq.de> ).
+ *
+ * Copyright (C) 2009 Nokia Corporation and/or its subsidiary(-ies).
+ *
+ * Contact: Samu Onkalo <samu.p.onkalo@nokia.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/err.h>
+#include <linux/i2c.h>
+#include <linux/pm_runtime.h>
+#include <linux/delay.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
+#include <linux/of_device.h>
+
+#include "lis3lv02d.h"
+
+#define DRV_NAME	"lis3lv02d_i2c"
+
+static const char reg_vdd[]    = "Vdd";
+static const char reg_vdd_io[] = "Vdd_IO";
+
+static int lis3_reg_ctrl(struct lis3lv02d *lis3, bool state)
+{
+	int ret;
+	if (state == LIS3_REG_OFF) {
+		ret = regulator_bulk_disable(ARRAY_SIZE(lis3->regulators),
+					lis3->regulators);
+	} else {
+		ret = regulator_bulk_enable(ARRAY_SIZE(lis3->regulators),
+					lis3->regulators);
+		/* Chip needs time to wakeup. Not mentioned in datasheet */
+		usleep_range(10000, 20000);
+	}
+	return ret;
+}
+
+static inline s32 lis3_i2c_write(struct lis3lv02d *lis3, int reg, u8 value)
+{
+	struct i2c_client *c = lis3->bus_priv;
+	return i2c_smbus_write_byte_data(c, reg, value);
+}
+
+static inline s32 lis3_i2c_read(struct lis3lv02d *lis3, int reg, u8 *v)
+{
+	struct i2c_client *c = lis3->bus_priv;
+	*v = i2c_smbus_read_byte_data(c, reg);
+	return 0;
+}
+
+static inline s32 lis3_i2c_blockread(struct lis3lv02d *lis3, int reg, int len,
+				u8 *v)
+{
+	struct i2c_client *c = lis3->bus_priv;
+	reg |= (1 << 7); /* 7th bit enables address auto incrementation */
+	return i2c_smbus_read_i2c_block_data(c, reg, len, v);
+}
+
+static int lis3_i2c_init(struct lis3lv02d *lis3)
+{
+	u8 reg;
+	int ret;
+
+	lis3_reg_ctrl(lis3, LIS3_REG_ON);
+
+	lis3->read(lis3, WHO_AM_I, &reg);
+	if (reg != lis3->whoami)
+		printk(KERN_ERR "lis3: power on failure\n");
+
+	/* power up the device */
+	ret = lis3->read(lis3, CTRL_REG1, &reg);
+	if (ret < 0)
+		return ret;
+
+	if (lis3->whoami == WAI_3DLH)
+		reg |= CTRL1_PM0 | CTRL1_Xen | CTRL1_Yen | CTRL1_Zen;
+	else
+		reg |= CTRL1_PD0 | CTRL1_Xen | CTRL1_Yen | CTRL1_Zen;
+
+	return lis3->write(lis3, CTRL_REG1, reg);
+}
+
+/* Default axis mapping but it can be overwritten by platform data */
+static union axis_conversion lis3lv02d_axis_map =
+	{ .as_array = { LIS3_DEV_X, LIS3_DEV_Y, LIS3_DEV_Z } };
+
+#ifdef CONFIG_OF
+static const struct of_device_id lis3lv02d_i2c_dt_ids[] = {
+	{ .compatible = "st,lis3lv02d" },
+	{}
+};
+MODULE_DEVICE_TABLE(of, lis3lv02d_i2c_dt_ids);
+#endif
+
+static int lis3lv02d_i2c_probe(struct i2c_client *client,
+					const struct i2c_device_id *id)
+{
+	int ret = 0;
+	struct lis3lv02d_platform_data *pdata = client->dev.platform_data;
+
+#ifdef CONFIG_OF
+	if (of_match_device(lis3lv02d_i2c_dt_ids, &client->dev)) {
+		lis3_dev.of_node = client->dev.of_node;
+		ret = lis3lv02d_init_dt(&lis3_dev);
+		if (ret)
+			return ret;
+		pdata = lis3_dev.pdata;
+	}
+#endif
+
+	if (pdata) {
+		if ((pdata->driver_features & LIS3_USE_BLOCK_READ) &&
+			(i2c_check_functionality(client->adapter,
+						I2C_FUNC_SMBUS_I2C_BLOCK)))
+			lis3_dev.blkread  = lis3_i2c_blockread;
+
+		if (pdata->axis_x)
+			lis3lv02d_axis_map.x = pdata->axis_x;
+
+		if (pdata->axis_y)
+			lis3lv02d_axis_map.y = pdata->axis_y;
+
+		if (pdata->axis_z)
+			lis3lv02d_axis_map.z = pdata->axis_z;
+
+		if (pdata->setup_resources)
+			ret = pdata->setup_resources();
+
+		if (ret)
+			goto fail;
+	}
+
+	lis3_dev.regulators[0].supply = reg_vdd;
+	lis3_dev.regulators[1].supply = reg_vdd_io;
+	ret = regulator_bulk_get(&client->dev,
+				 ARRAY_SIZE(lis3_dev.regulators),
+				 lis3_dev.regulators);
+	if (ret < 0)
+		goto fail;
+
+	lis3_dev.pdata	  = pdata;
+	lis3_dev.bus_priv = client;
+	lis3_dev.init	  = lis3_i2c_init;
+	lis3_dev.read	  = lis3_i2c_read;
+	lis3_dev.write	  = lis3_i2c_write;
+	lis3_dev.irq	  = client->irq;
+	lis3_dev.ac	  = lis3lv02d_axis_map;
+	lis3_dev.pm_dev	  = &client->dev;
+
+	i2c_set_clientdata(client, &lis3_dev);
+
+	/* Provide power over the init call */
+	lis3_reg_ctrl(&lis3_dev, LIS3_REG_ON);
+
+	ret = lis3lv02d_init_device(&lis3_dev);
+
+	lis3_reg_ctrl(&lis3_dev, LIS3_REG_OFF);
+
+	if (ret)
+		goto fail2;
+	return 0;
+
+fail2:
+	regulator_bulk_free(ARRAY_SIZE(lis3_dev.regulators),
+				lis3_dev.regulators);
+fail:
+	if (pdata && pdata->release_resources)
+		pdata->release_resources();
+	return ret;
+}
+
+static int lis3lv02d_i2c_remove(struct i2c_client *client)
+{
+	struct lis3lv02d *lis3 = i2c_get_clientdata(client);
+	struct lis3lv02d_platform_data *pdata = client->dev.platform_data;
+
+	if (pdata && pdata->release_resources)
+		pdata->release_resources();
+
+	lis3lv02d_joystick_disable(lis3);
+	lis3lv02d_remove_fs(&lis3_dev);
+
+	regulator_bulk_free(ARRAY_SIZE(lis3->regulators),
+			    lis3_dev.regulators);
+	return 0;
+}
+
+#ifdef CONFIG_PM_SLEEP
+static int lis3lv02d_i2c_suspend(struct device *dev)
+{
+	struct i2c_client *client = to_i2c_client(dev);
+	struct lis3lv02d *lis3 = i2c_get_clientdata(client);
+
+	if (!lis3->pdata || !lis3->pdata->wakeup_flags)
+		lis3lv02d_poweroff(lis3);
+	return 0;
+}
+
+static int lis3lv02d_i2c_resume(struct device *dev)
+{
+	struct i2c_client *client = to_i2c_client(dev);
+	struct lis3lv02d *lis3 = i2c_get_clientdata(client);
+
+	/*
+	 * pm_runtime documentation says that devices should always
+	 * be powered on at resume. Pm_runtime turns them off after system
+	 * wide resume is complete.
+	 */
+	if (!lis3->pdata || !lis3->pdata->wakeup_flags ||
+		pm_runtime_suspended(dev))
+		lis3lv02d_poweron(lis3);
+
+	return 0;
+}
+#endif /* CONFIG_PM_SLEEP */
+
+#ifdef CONFIG_PM
+static int lis3_i2c_runtime_suspend(struct device *dev)
+{
+	struct i2c_client *client = to_i2c_client(dev);
+	struct lis3lv02d *lis3 = i2c_get_clientdata(client);
+
+	lis3lv02d_poweroff(lis3);
+	return 0;
+}
+
+static int lis3_i2c_runtime_resume(struct device *dev)
+{
+	struct i2c_client *client = to_i2c_client(dev);
+	struct lis3lv02d *lis3 = i2c_get_clientdata(client);
+
+	lis3lv02d_poweron(lis3);
+	return 0;
+}
+#endif /* CONFIG_PM */
+
+static const struct i2c_device_id lis3lv02d_id[] = {
+	{"lis3lv02d", LIS3LV02D},
+	{"lis331dlh", LIS331DLH},
+	{}
+};
+
+MODULE_DEVICE_TABLE(i2c, lis3lv02d_id);
+
+static const struct dev_pm_ops lis3_pm_ops = {
+	SET_SYSTEM_SLEEP_PM_OPS(lis3lv02d_i2c_suspend,
+				lis3lv02d_i2c_resume)
+	SET_RUNTIME_PM_OPS(lis3_i2c_runtime_suspend,
+			   lis3_i2c_runtime_resume,
+			   NULL)
+};
+
+static struct i2c_driver lis3lv02d_i2c_driver = {
+	.driver	 = {
+		.name   = DRV_NAME,
+		.pm     = &lis3_pm_ops,
+		.of_match_table = of_match_ptr(lis3lv02d_i2c_dt_ids),
+	},
+	.probe	= lis3lv02d_i2c_probe,
+	.remove	= lis3lv02d_i2c_remove,
+	.id_table = lis3lv02d_id,
+};
+
+module_i2c_driver(lis3lv02d_i2c_driver);
+
+MODULE_AUTHOR("Nokia Corporation");
+MODULE_DESCRIPTION("lis3lv02d I2C interface");
+MODULE_LICENSE("GPL");
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/lis3lv02d/lis3lv02d_spi.c b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/lis3lv02d/lis3lv02d_spi.c
new file mode 100644
index 0000000000000000000000000000000000000000..e575475123c838e0ed2fe2a1dc51832ea9c2c873
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/lis3lv02d/lis3lv02d_spi.c
@@ -0,0 +1,153 @@
+/*
+ * lis3lv02d_spi - SPI glue layer for lis3lv02d
+ *
+ * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  publishhed by the Free Software Foundation.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/err.h>
+#include <linux/input.h>
+#include <linux/interrupt.h>
+#include <linux/workqueue.h>
+#include <linux/spi/spi.h>
+#include <linux/pm.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
+#include <linux/of_device.h>
+
+#include "lis3lv02d.h"
+
+#define DRV_NAME 	"lis3lv02d_spi"
+#define LIS3_SPI_READ	0x80
+
+static int lis3_spi_read(struct lis3lv02d *lis3, int reg, u8 *v)
+{
+	struct spi_device *spi = lis3->bus_priv;
+	int ret = spi_w8r8(spi, reg | LIS3_SPI_READ);
+	if (ret < 0)
+		return -EINVAL;
+
+	*v = (u8) ret;
+	return 0;
+}
+
+static int lis3_spi_write(struct lis3lv02d *lis3, int reg, u8 val)
+{
+	u8 tmp[2] = { reg, val };
+	struct spi_device *spi = lis3->bus_priv;
+	return spi_write(spi, tmp, sizeof(tmp));
+}
+
+static int lis3_spi_init(struct lis3lv02d *lis3)
+{
+	u8 reg;
+	int ret;
+
+	/* power up the device */
+	ret = lis3->read(lis3, CTRL_REG1, &reg);
+	if (ret < 0)
+		return ret;
+
+	reg |= CTRL1_PD0 | CTRL1_Xen | CTRL1_Yen | CTRL1_Zen;
+	return lis3->write(lis3, CTRL_REG1, reg);
+}
+
+static union axis_conversion lis3lv02d_axis_normal =
+	{ .as_array = { 1, 2, 3 } };
+
+#ifdef CONFIG_OF
+static const struct of_device_id lis302dl_spi_dt_ids[] = {
+	{ .compatible = "st,lis302dl-spi" },
+	{}
+};
+MODULE_DEVICE_TABLE(of, lis302dl_spi_dt_ids);
+#endif
+
+static int lis302dl_spi_probe(struct spi_device *spi)
+{
+	int ret;
+
+	spi->bits_per_word = 8;
+	spi->mode = SPI_MODE_0;
+	ret = spi_setup(spi);
+	if (ret < 0)
+		return ret;
+
+	lis3_dev.bus_priv	= spi;
+	lis3_dev.init		= lis3_spi_init;
+	lis3_dev.read		= lis3_spi_read;
+	lis3_dev.write		= lis3_spi_write;
+	lis3_dev.irq		= spi->irq;
+	lis3_dev.ac		= lis3lv02d_axis_normal;
+	lis3_dev.pdata		= spi->dev.platform_data;
+
+#ifdef CONFIG_OF
+	if (of_match_device(lis302dl_spi_dt_ids, &spi->dev)) {
+		lis3_dev.of_node = spi->dev.of_node;
+		ret = lis3lv02d_init_dt(&lis3_dev);
+		if (ret)
+			return ret;
+	}
+#endif
+	spi_set_drvdata(spi, &lis3_dev);
+
+	return lis3lv02d_init_device(&lis3_dev);
+}
+
+static int lis302dl_spi_remove(struct spi_device *spi)
+{
+	struct lis3lv02d *lis3 = spi_get_drvdata(spi);
+	lis3lv02d_joystick_disable(lis3);
+	lis3lv02d_poweroff(lis3);
+
+	return lis3lv02d_remove_fs(&lis3_dev);
+}
+
+#ifdef CONFIG_PM_SLEEP
+static int lis3lv02d_spi_suspend(struct device *dev)
+{
+	struct spi_device *spi = to_spi_device(dev);
+	struct lis3lv02d *lis3 = spi_get_drvdata(spi);
+
+	if (!lis3->pdata || !lis3->pdata->wakeup_flags)
+		lis3lv02d_poweroff(&lis3_dev);
+
+	return 0;
+}
+
+static int lis3lv02d_spi_resume(struct device *dev)
+{
+	struct spi_device *spi = to_spi_device(dev);
+	struct lis3lv02d *lis3 = spi_get_drvdata(spi);
+
+	if (!lis3->pdata || !lis3->pdata->wakeup_flags)
+		lis3lv02d_poweron(lis3);
+
+	return 0;
+}
+#endif
+
+static SIMPLE_DEV_PM_OPS(lis3lv02d_spi_pm, lis3lv02d_spi_suspend,
+			 lis3lv02d_spi_resume);
+
+static struct spi_driver lis302dl_spi_driver = {
+	.driver	 = {
+		.name   = DRV_NAME,
+		.pm	= &lis3lv02d_spi_pm,
+		.of_match_table = of_match_ptr(lis302dl_spi_dt_ids),
+	},
+	.probe	= lis302dl_spi_probe,
+	.remove	= lis302dl_spi_remove,
+};
+
+module_spi_driver(lis302dl_spi_driver);
+
+MODULE_AUTHOR("Daniel Mack <daniel@caiaq.de>");
+MODULE_DESCRIPTION("lis3lv02d SPI glue layer");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("spi:" DRV_NAME);
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/mcp25xxfd/80-can.rules b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/mcp25xxfd/80-can.rules
new file mode 100644
index 0000000000000000000000000000000000000000..69869e3d30af73ed9cee1c9870175717d2026055
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/mcp25xxfd/80-can.rules
@@ -0,0 +1,2 @@
+ACTION=="add", SUBSYSTEM=="net", DEVPATH=="/devices/platform/soc/*/spi0.0/net/can?", NAME="can0"
+ACTION=="add", SUBSYSTEM=="net", DEVPATH=="/devices/platform/soc/*/spi1.0/net/can?", NAME="can1"
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/mcp25xxfd/Makefile b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/mcp25xxfd/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..b132e45560137522986e871bbb709929c7fac5f9
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/mcp25xxfd/Makefile
@@ -0,0 +1,28 @@
+obj-m				+= mcp25xxfd-can.o
+mcp25xxfd-can-objs                  := mcp25xxfd_base.o
+mcp25xxfd-can-objs                  += mcp25xxfd_can.o
+mcp25xxfd-can-objs                  += mcp25xxfd_can_debugfs.o
+mcp25xxfd-can-objs                  += mcp25xxfd_can_fifo.o
+mcp25xxfd-can-objs                  += mcp25xxfd_can_int.o
+mcp25xxfd-can-objs                  += mcp25xxfd_can_rx.o
+mcp25xxfd-can-objs                  += mcp25xxfd_can_tx.o
+mcp25xxfd-can-objs                  += mcp25xxfd_clock.o
+mcp25xxfd-can-objs                  += mcp25xxfd_cmd.o
+mcp25xxfd-can-objs                  += mcp25xxfd_crc.o
+mcp25xxfd-can-objs                  += mcp25xxfd_debugfs.o
+mcp25xxfd-can-objs                  += mcp25xxfd_ecc.o
+mcp25xxfd-can-objs                  += mcp25xxfd_gpio.o
+mcp25xxfd-can-objs                  += mcp25xxfd_int.o
+
+
+
+
+all:
+	make -C /lib/modules/$(shell uname -r)/build M=$(PWD) modules
+
+clean:
+	make -C /lib/modules/$(shell uname -r)/build M=$(PWD) clean
+
+install:
+	sudo cp mcp25xxfd-can.ko /lib/modules/$(shell uname -r)/kernel/drivers/net/can/spi/
+	sudo depmod -a
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/mcp25xxfd/README.md b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/mcp25xxfd/README.md
new file mode 100644
index 0000000000000000000000000000000000000000..c9a03273f1dc7713156239a555245683dd62e752
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/mcp25xxfd/README.md
@@ -0,0 +1,352 @@
+# CAN-HAT
+
+
+The drivers of [Raspberry pi  CAN HAT](https://www.seeedstudio.com/2-Channel-CAN-BUS-FD-Shield-for-Raspberry-Pi-p-4072.html) for Raspberry Pi.
+
+### Install CAN-HAT
+Get the CAN-HAT  source code. and install all linux kernel drivers
+```bash
+git clone https://github.com/seeed-Studio/pi-hats
+cd pi-hats/CAN-HAT
+sudo ./install.sh 
+sudo reboot
+```
+
+## Raspberry pi  CAN HAT
+
+[![](https://github.com/SeeedDocument/2-Channel-CAN-BUS-FD-Shield-for-Raspberry-Pi/raw/master/img/block.jpg)](https://www.seeedstudio.com/2-Channel-CAN-BUS-FD-Shield-for-Raspberry-Pi-p-4072.html)
+
+
+Check the kernel log to see if MCP2517 was initialized successfully.You will also see can0 and can1 appear in the list of ifconfig results
+
+```bash
+pi@raspberrypi:~ $ dmesg | grep spi
+[    3.725586] mcp25xxfd spi0.0 can0: MCP2517 successfully initialized.
+[    3.757376] mcp25xxfd spi1.0 can1: MCP2517 successfully initialized.
+
+pi@raspberrypi:~/pi-hats/CAN-HAT $ ifconfig -a
+can0: flags=128<NOARP>  mtu 16
+        unspec 00-00-00-00-00-00-00-00-00-00-00-00-00-00-00-00  txqueuelen 10  (UNSPEC)
+        RX packets 0  bytes 0 (0.0 B)
+        RX errors 0  dropped 0  overruns 0  frame 0
+        TX packets 0  bytes 0 (0.0 B)
+        TX errors 0  dropped 0 overruns 0  carrier 0  collisions 0
+
+can1: flags=128<NOARP>  mtu 16
+        unspec 00-00-00-00-00-00-00-00-00-00-00-00-00-00-00-00  txqueuelen 10  (UNSPEC)
+        RX packets 0  bytes 0 (0.0 B)
+        RX errors 0  dropped 0  overruns 0  frame 0
+        TX packets 0  bytes 0 (0.0 B)
+        TX errors 0  dropped 0 overruns 0  carrier 0  collisions 0
+
+eth0: flags=4099<UP,BROADCAST,MULTICAST>  mtu 1500
+        ether b8:27:eb:c7:ed:4f  txqueuelen 1000  (Ethernet)
+        RX packets 0  bytes 0 (0.0 B)
+        RX errors 0  dropped 0  overruns 0  frame 0
+        TX packets 0  bytes 0 (0.0 B)
+        TX errors 0  dropped 0 overruns 0  carrier 0  collisions 0
+
+lo: flags=73<UP,LOOPBACK,RUNNING>  mtu 65536
+        inet 127.0.0.1  netmask 255.0.0.0
+        inet6 ::1  prefixlen 128  scopeid 0x10<host>
+        loop  txqueuelen 1000  (Local Loopback)
+        RX packets 0  bytes 0 (0.0 B)
+        RX errors 0  dropped 0  overruns 0  frame 0
+        TX packets 0  bytes 0 (0.0 B)
+        TX errors 0  dropped 0 overruns 0  carrier 0  collisions 0
+
+wlan0: flags=4163<UP,BROADCAST,RUNNING,MULTICAST>  mtu 1500
+        inet 192.168.250.42  netmask 255.255.255.0  broadcast 192.168.250.255
+        inet6 fe80::3842:7323:7c0d:f6d2  prefixlen 64  scopeid 0x20<link>
+        ether b8:27:eb:92:b8:1a  txqueuelen 1000  (Ethernet)
+        RX packets 2654  bytes 249303 (243.4 KiB)
+        RX errors 0  dropped 0  overruns 0  frame 0
+        TX packets 4433  bytes 4765896 (4.5 MiB)
+        TX errors 0  dropped 0 overruns 0  carrier 0  collisions 0
+
+```
+
+
+
+
+#### Next step
+Set the can fd protocol, and the dbitrate can be set to 8M speed. [Refer to the kernel documentation for more usage](https://www.kernel.org/doc/Documentation/networking/can.txt)
+
+```bash
+sudo ip link set can0 up type can bitrate 1000000   dbitrate 8000000 restart-ms 1000 berr-reporting on fd on
+sudo ip link set can1 up type can bitrate 1000000   dbitrate 8000000 restart-ms 1000 berr-reporting on fd on
+
+sudo ifconfig can0 txqueuelen 65536
+sudo ifconfig can1 txqueuelen 65536
+```
+
+The hardware is wired to can0 and can1 interface.
+
+0_L  <===> 1_L
+
+0_H  <===> 1_H
+
+Open two terminal windows and enter the following commands in the Windows to test can fd protocol.
+```bash
+#send data
+cangen can0 -mv 
+```
+
+```bash
+#dump data
+candump can0 
+```
+#### Communicate with [CAN_BUS_Shield](https://www.seeedstudio.com/CAN-BUS-Shield-V2-p-2921.html)
+![](https://github.com/Seeed-Studio/pi-hats/raw/master/images/can_hat_and_arduinno_hardware.jpg) 
+
+1. CAN_BUS_Shield send and CAN HAT receive
+
+Arduino code:
+```c
+// demo: CAN-BUS Shield, send data
+// loovee@seeed.cc
+
+#include <mcp_can.h>
+#include <SPI.h>
+
+// the cs pin of the version after v1.1 is default to D9
+// v0.9b and v1.0 is default D10
+const int SPI_CS_PIN = 9;
+
+MCP_CAN CAN(SPI_CS_PIN);                                    // Set CS pin
+
+void setup()
+{
+    Serial.begin(115200);
+
+    while (CAN_OK != CAN.begin(CAN_500KBPS))              // init can bus : baudrate = 500k
+    {
+        Serial.println("CAN BUS Shield init fail");
+        Serial.println(" Init CAN BUS Shield again");
+        delay(100);
+    }
+    Serial.println("CAN BUS Shield init ok!");
+}
+
+unsigned char stmp[8] = {0, 0, 0, 0, 0, 0, 0, 0};
+void loop()
+{
+    //send data:  id = 0x00, standrad frame, data len = 8, stmp: data buf
+    stmp[7] = stmp[7]+1;
+    if(stmp[7] == 100)
+    {
+        stmp[7] = 0;
+        stmp[6] = stmp[6] + 1;
+        
+        if(stmp[6] == 100)
+        {
+            stmp[6] = 0;
+            stmp[5] = stmp[6] + 1;
+        }
+    }
+    
+    CAN.sendMsgBuf(0x00, 0, 8, stmp);
+    delay(100);                       // send data per 100ms
+}
+// END FILE
+```
+Respberry pi setting and and use can-util to receive
+```bash
+#set 500k baudrate
+pi@raspberrypi:~ $ sudo ip link set can0 up type can bitrate 500000
+pi@raspberrypi:~ $ ip -details link show can0
+3: can0: <NOARP,UP,LOWER_UP,ECHO> mtu 16 qdisc pfifo_fast state UNKNOWN mode DEFAULT group default qlen 10
+    link/can  promiscuity 0 
+    can state ERROR-ACTIVE (berr-counter tx 0 rx 0) restart-ms 0 
+	  bitrate 500000 sample-point 0.875 
+	  tq 25 prop-seg 34 phase-seg1 35 phase-seg2 10 sjw 1
+	  mcp25xxfd: tseg1 2..256 tseg2 1..128 sjw 1..128 brp 1..256 brp-inc 1
+	  mcp25xxfd: dtseg1 1..32 dtseg2 1..16 dsjw 1..16 dbrp 1..256 dbrp-inc 1
+	  clock 40000000numtxqueues 1 numrxqueues 1 gso_max_size 65536 gso_max_segs 65535 
+#receive
+pi@raspberrypi:~ $ candump can0
+  can0  000   [8]  00 00 00 00 00 00 00 05
+  can0  000   [8]  00 00 00 00 00 00 00 06
+  can0  000   [8]  00 00 00 00 00 00 00 07
+  can0  000   [8]  00 00 00 00 00 00 00 08
+  can0  000   [8]  00 00 00 00 00 00 00 09
+  can0  000   [8]  00 00 00 00 00 00 00 0A
+  can0  000   [8]  00 00 00 00 00 00 00 0B
+  can0  000   [8]  00 00 00 00 00 00 00 0C
+  can0  000   [8]  00 00 00 00 00 00 00 0D
+  can0  000   [8]  00 00 00 00 00 00 00 0E
+  can0  000   [8]  00 00 00 00 00 00 00 0F
+  can0  000   [8]  00 00 00 00 00 00 00 10
+  can0  000   [8]  00 00 00 00 00 00 00 11
+  can0  000   [8]  00 00 00 00 00 00 00 12
+  can0  000   [8]  00 00 00 00 00 00 00 13
+  can0  000   [8]  00 00 00 00 00 00 00 14
+  can0  000   [8]  00 00 00 00 00 00 00 15
+  can0  000   [8]  00 00 00 00 00 00 00 16
+  can0  000   [8]  00 00 00 00 00 00 00 17
+  can0  000   [8]  00 00 00 00 00 00 00 18
+  can0  000   [8]  00 00 00 00 00 00 00 19
+  can0  000   [8]  00 00 00 00 00 00 00 1A
+  can0  000   [8]  00 00 00 00 00 00 00 1B
+  can0  000   [8]  00 00 00 00 00 00 00 1C
+  can0  000   [8]  00 00 00 00 00 00 00 1D
+```
+Respberry pi use python code to receive
+```bash
+# install python-can
+sudo pip3 install python-can
+```
+run following python code
+```python
+import can
+
+can_interface = 'can0'
+bus = can.interface.Bus(can_interface, bustype='socketcan_native')
+while True:
+    message = bus.recv(1.0) # Timeout in seconds.
+    if message is None:
+            print('Timeout occurred, no message.')
+    print(message)
+```
+python code run result
+```bash
+pi@raspberrypi:~ $ python3 can_test.py   
+Timestamp: 1550471771.628215        ID: 0000    S                DLC:  8    00 00 00 00 00 00 0e 63     Channel: can0
+Timestamp: 1550471772.629302        ID: 0000    S                DLC:  8    00 00 00 00 00 00 0f 00     Channel: can0
+Timestamp: 1550471773.630658        ID: 0000    S                DLC:  8    00 00 00 00 00 00 0f 01     Channel: can0
+Timestamp: 1550471774.632018        ID: 0000    S                DLC:  8    00 00 00 00 00 00 0f 02     Channel: can0
+Timestamp: 1550471775.633395        ID: 0000    S                DLC:  8    00 00 00 00 00 00 0f 03     Channel: can0
+Timestamp: 1550471776.634774        ID: 0000    S                DLC:  8    00 00 00 00 00 00 0f 04     Channel: can0
+Timestamp: 1550471777.636135        ID: 0000    S                DLC:  8    00 00 00 00 00 00 0f 05     Channel: can0
+Timestamp: 1550471778.637481        ID: 0000    S                DLC:  8    00 00 00 00 00 00 0f 06     Channel: can0
+Timestamp: 1550471779.638859        ID: 0000    S                DLC:  8    00 00 00 00 00 00 0f 07     Channel: can0
+Timestamp: 1550471780.640222        ID: 0000    S                DLC:  8    00 00 00 00 00 00 0f 08     Channel: can0
+Timestamp: 1550471781.641602        ID: 0000    S                DLC:  8    00 00 00 00 00 00 0f 09     Channel: can0
+Timestamp: 1550471782.642970        ID: 0000    S                DLC:  8    00 00 00 00 00 00 0f 0a     Channel: can0
+
+```
+
+2. CAN_BUS_Shield receive and CAN HAT send
+
+raspberry pi use cangen to send random package 
+```bash
+pi@raspberrypi:~ $ cangen can0 -v 
+  can0  442#14.C4.1A.1A.C2.25.79.25
+  can0  748#4E.C7.8B.0B.6E.B9.15.77
+  can0  1E4#64.D4.62.22.2F.A6.BF
+  can0  1DD#69.6F.61.33.1F.59.E4.7C
+  can0  63D#
+  can0  764#2C.C1.E3
+  can0  68B#11.9C.63.6D.EA.E9.4B
+  can0  329#DA.06.2C.34.6C
+  can0  7DD#2E.F5.E0.2A.26.77.58.38
+  can0  1BE#94.30.6E.2F.A2.7B.E3.1D
+  can0  654#D1.21.A3.58.31.E8.51.5F
+  can0  706#51.41.36.5C.43.8D.AE.5D
+  can0  34A#89.F2.DE.33.AE.52.38.6C
+  can0  6AC#C1.35.83.41.37
+  can0  38C#22.AF
+  can0  208#22.8E.97.58.E5.69.F7.2C
+```
+Arduino receive code:
+```c
+// demo: CAN-BUS Shield, receive data with interrupt mode
+// when in interrupt mode, the data coming can't be too fast, must >20ms, or else you can use check mode
+// loovee, 2014-6-13
+
+#include <SPI.h>
+#include "mcp_can.h"
+
+// the cs pin of the version after v1.1 is default to D9
+// v0.9b and v1.0 is default D10
+const int SPI_CS_PIN = 9;
+
+MCP_CAN CAN(SPI_CS_PIN);                                    // Set CS pin
+
+
+unsigned char flagRecv = 0;
+unsigned char len = 0;
+unsigned char buf[8];
+char str[20];
+
+void setup()
+{
+    Serial.begin(115200);
+
+    while (CAN_OK != CAN.begin(CAN_500KBPS))              // init can bus : baudrate = 500k
+    {
+        Serial.println("CAN BUS Shield init fail");
+        Serial.println(" Init CAN BUS Shield again");
+        delay(100);
+    }
+    Serial.println("CAN BUS Shield init ok!");
+
+    attachInterrupt(0, MCP2515_ISR, FALLING); // start interrupt
+}
+
+void MCP2515_ISR()
+{
+    flagRecv = 1;
+}
+
+void loop()
+{
+    if(flagRecv) 
+    {                                   // check if get data
+
+        flagRecv = 0;                   // clear flag
+
+        // iterate over all pending messages
+        // If either the bus is saturated or the MCU is busy,
+        // both RX buffers may be in use and reading a single
+        // message does not clear the IRQ conditon.
+        while (CAN_MSGAVAIL == CAN.checkReceive()) 
+        {
+            // read data,  len: data length, buf: data buf
+            CAN.readMsgBuf(&len, buf);
+
+            // print the data
+            for(int i = 0; i<len; i++)
+            {
+                Serial.print(buf[i]);Serial.print("\t");
+            }
+            Serial.println();
+        }
+    }
+}
+```
+Arduino receive data
+![](https://github.com/Seeed-Studio/pi-hats/raw/master/images/arduino_receive.png) 
+You alse can use python-can to send data
+```python
+import time
+import can
+
+bustype = 'socketcan_native'
+channel = 'can0'
+
+def producer(id):
+    """:param id: Spam the bus with messages including the data id."""
+    bus = can.interface.Bus(channel=channel, bustype=bustype)
+    for i in range(10):
+        msg = can.Message(arbitration_id=0xc0ffee, data=[id, i, 0, 1, 3, 1, 4, 1], extended_id=False)
+        bus.send(msg)
+    # Issue #3: Need to keep running to ensure the writing threads stay alive. ?
+    time.sleep(1)
+
+producer(10)
+
+```
+### uninstall CAN-HAT
+
+```
+pi@raspberrypi:~/pi-hats/CAN-HAT $ sudo ./uninstall.sh 
+...
+------------------------------------------------------
+Please reboot your raspberry pi to apply all settings
+Thank you!
+------------------------------------------------------
+```
+
+
+Enjoy !
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/mcp25xxfd/mcp25xxfd_base.c b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/mcp25xxfd/mcp25xxfd_base.c
new file mode 100644
index 0000000000000000000000000000000000000000..5db4a5812952f465446e5398e2dc2b135cc7762a
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/mcp25xxfd/mcp25xxfd_base.c
@@ -0,0 +1,281 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/* CAN bus driver for Microchip 25XXFD CAN Controller with SPI Interface
+ *
+ * Copyright 2019 Martin Sperl <kernel@martin.sperl.org>
+ */
+
+#include <linux/interrupt.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+
+#include "mcp25xxfd_can.h"
+#include "mcp25xxfd_clock.h"
+#include "mcp25xxfd_cmd.h"
+#include "mcp25xxfd_debugfs.h"
+#include "mcp25xxfd_ecc.h"
+#include "mcp25xxfd_gpio.h"
+#include "mcp25xxfd_int.h"
+#include "mcp25xxfd_priv.h"
+
+/* Device description and rational:
+ *
+ * The mcp25xxfd is a CanFD controller that also supports can2.0 only
+ * modes.
+ * It is connected via spi to the host and requires at minimum a single
+ * irq line in addition to the SPI lines - it is not mentioned explicitly
+ * in the documentation but in principle SPI 3-wire should be possible.
+ *
+ * The clock connected is typically 4MHz, 20MHz or 40MHz.
+ * When using a 4MHz clock the controller can use an integrated PLL to
+ * get 40MHz.
+ *
+ * The controller itself has 2KB of SRAM for CAN-data.
+ * ECC can get enabled for SRAM.
+ * CRC-16 checksumming of SPI transfers can get implemented
+ *   - some optimization options may not be efficient in such a situation.
+ *   - more SPI bus bandwidth is used for transfer of CRCs and
+ *     transfer length information
+ *
+ * It also contains 2 GPIO pins that can get used either as interrupt lines
+ * or GPIO IN or Out or STANDBY flags.
+ * In addition there is a PIN that allows output of a (divided) clock out
+ * or as a SOF (Start of Can FRAME) interrupt line - e.g for wakeup.
+ */
+
+int mcp25xxfd_base_power_enable(struct regulator *reg, int enable)
+{
+	if (IS_ERR_OR_NULL(reg))
+		return 0;
+
+	if (enable)
+		return regulator_enable(reg);
+	else
+		return regulator_disable(reg);
+}
+
+static const struct of_device_id mcp25xxfd_of_match[] = {
+	{
+		.compatible	= "microchip,mcp2517fd",
+		.data		= (void *)CAN_MCP2517FD,
+	},
+	{ }
+};
+MODULE_DEVICE_TABLE(of, mcp25xxfd_of_match);
+
+static int mcp25xxfd_base_probe(struct spi_device *spi)
+{
+	const struct of_device_id *of_id =
+		of_match_device(mcp25xxfd_of_match, &spi->dev);
+	struct mcp25xxfd_priv *priv;
+	int ret;
+
+	/* as irq_create_fwspec_mapping() can return 0, check for it */
+	if (spi->irq <= 0) {
+		dev_err(&spi->dev, "no valid irq line defined: irq = %i\n",
+			spi->irq);
+		return -EINVAL;
+	}
+
+	priv = devm_kzalloc(&spi->dev, sizeof(*priv), GFP_KERNEL);
+	if (!priv)
+		return -ENOMEM;
+
+	/* cross assigns */
+	spi_set_drvdata(spi, priv);
+	priv->spi = spi;
+
+	/* assign name */
+	snprintf(priv->device_name, sizeof(priv->device_name),
+		 DEVICE_NAME "-%s", dev_name(&priv->spi->dev));
+
+	/* assign model from of or driver_data */
+	if (of_id)
+		priv->model = (enum mcp25xxfd_model)of_id->data;
+	else
+		priv->model = spi_get_device_id(spi)->driver_data;
+
+	mutex_init(&priv->spi_rxtx_lock);
+
+	ret = mcp25xxfd_clock_init(priv);
+	if (ret)
+		goto out_free;
+
+	/* Configure the SPI bus */
+	spi->bits_per_word = 8;
+	ret = spi_setup(spi);
+	if (ret)
+		goto out_clk;
+
+	priv->power = devm_regulator_get_optional(&spi->dev, "vdd");
+	if (PTR_ERR(priv->power) == -EPROBE_DEFER) {
+		ret = -EPROBE_DEFER;
+		goto out_clk;
+	}
+
+	ret = mcp25xxfd_base_power_enable(priv->power, 1);
+	if (ret)
+		goto out_clk;
+
+	/* this will also enable the MCP25XXFD_CLK_USER_CAN clock */
+	ret = mcp25xxfd_clock_probe(priv);
+	if (ret)
+		goto out_probe;
+
+	/* enable the can controller clock */
+	ret = mcp25xxfd_clock_start(priv, MCP25XXFD_CLK_USER_CAN);
+	if (ret)
+		goto out_probe;
+
+	/* try to identify the can-controller - we need the clock here */
+	ret = mcp25xxfd_can_probe(priv);
+	if (ret)
+		goto out_ctlclk;
+
+	/* add debugfs */
+	mcp25xxfd_debugfs_setup(priv);
+
+	/* disable interrupts */
+	ret = mcp25xxfd_int_enable(priv, false);
+	if (ret)
+		goto out_debugfs;
+
+	/* setup ECC for SRAM */
+	ret = mcp25xxfd_ecc_enable(priv);
+	if (ret)
+		goto out_debugfs;
+
+	/* setting up GPIO */
+	ret = mcp25xxfd_gpio_setup(priv);
+	if (ret)
+		goto out_debugfs;
+
+	/* setting up CAN */
+	ret = mcp25xxfd_can_setup(priv);
+	if (ret)
+		goto out_gpio;
+
+	/* and put controller to sleep by stopping the can clock */
+	ret = mcp25xxfd_clock_stop(priv, MCP25XXFD_CLK_USER_CAN);
+	if (ret)
+		goto out_can;
+
+	dev_info(&spi->dev,
+		 "MCP%x successfully initialized.\n", priv->model);
+	return 0;
+
+out_can:
+	mcp25xxfd_can_remove(priv);
+out_gpio:
+	mcp25xxfd_gpio_remove(priv);
+out_debugfs:
+	mcp25xxfd_debugfs_remove(priv);
+out_ctlclk:
+	mcp25xxfd_clock_stop(priv, MCP25XXFD_CLK_USER_CAN);
+out_probe:
+	mcp25xxfd_base_power_enable(priv->power, 0);
+out_clk:
+	mcp25xxfd_clock_release(priv);
+out_free:
+	dev_err(&spi->dev, "Probe failed, err=%d\n", -ret);
+	return ret;
+}
+
+static int mcp25xxfd_base_remove(struct spi_device *spi)
+{
+	struct mcp25xxfd_priv *priv = spi_get_drvdata(spi);
+
+	/* remove can */
+	mcp25xxfd_can_remove(priv);
+
+	/* remove gpio */
+	mcp25xxfd_gpio_remove(priv);
+
+	/* clear all running clocks */
+	mcp25xxfd_clock_stop(priv, priv->clk_user_mask);
+
+	mcp25xxfd_debugfs_remove(priv);
+
+	mcp25xxfd_base_power_enable(priv->power, 0);
+
+	mcp25xxfd_clock_release(priv);
+
+	return 0;
+}
+
+static int __maybe_unused mcp25xxfd_base_suspend(struct device *dev)
+{
+	struct spi_device *spi = to_spi_device(dev);
+	struct mcp25xxfd_priv *priv = spi_get_drvdata(spi);
+
+	mutex_lock(&priv->clk_user_lock);
+	priv->clk_sleep_mask = priv->clk_user_mask;
+	mutex_unlock(&priv->clk_user_lock);
+
+	/* disable interrupts */
+	mcp25xxfd_int_enable(priv, false);
+
+	/* stop the clocks */
+	mcp25xxfd_clock_stop(priv, priv->clk_sleep_mask);
+
+	/* disable power to controller */
+	return mcp25xxfd_base_power_enable(priv->power, 0);
+}
+
+static int __maybe_unused mcp25xxfd_base_resume(struct device *dev)
+{
+	struct spi_device *spi = to_spi_device(dev);
+	struct mcp25xxfd_priv *priv = spi_get_drvdata(spi);
+	int ret = 0;
+
+	/* enable power to controller */
+	mcp25xxfd_base_power_enable(priv->power, 1);
+
+	/* if there is no sleep mask, then there is nothing to wake */
+	if (!priv->clk_sleep_mask)
+		return 0;
+
+	/* start the clocks */
+	ret = mcp25xxfd_clock_start(priv, priv->clk_sleep_mask);
+	if (ret)
+		return 0;
+
+	/* clear the sleep mask */
+	mutex_lock(&priv->clk_user_lock);
+	priv->clk_sleep_mask = 0;
+	mutex_unlock(&priv->clk_user_lock);
+
+	/* enable the interrupts again */
+	return mcp25xxfd_int_enable(priv, true);
+}
+
+static SIMPLE_DEV_PM_OPS(mcp25xxfd_base_pm_ops, mcp25xxfd_base_suspend,
+			 mcp25xxfd_base_resume);
+
+static const struct spi_device_id mcp25xxfd_id_table[] = {
+	{
+		.name		= "mcp2517fd",
+		.driver_data	= (kernel_ulong_t)CAN_MCP2517FD,
+	},
+	{ }
+};
+MODULE_DEVICE_TABLE(spi, mcp25xxfd_id_table);
+
+static struct spi_driver mcp25xxfd_can_driver = {
+	.driver = {
+		.name = DEVICE_NAME,
+		.of_match_table = mcp25xxfd_of_match,
+		.pm = &mcp25xxfd_base_pm_ops,
+	},
+	.id_table = mcp25xxfd_id_table,
+	.probe = mcp25xxfd_base_probe,
+	.remove = mcp25xxfd_base_remove,
+};
+module_spi_driver(mcp25xxfd_can_driver);
+
+MODULE_AUTHOR("Martin Sperl <kernel@martin.sperl.org>");
+MODULE_DESCRIPTION("Microchip 25XXFD CAN driver");
+MODULE_LICENSE("GPL v2");
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/mcp25xxfd/mcp25xxfd_base.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/mcp25xxfd/mcp25xxfd_base.h
new file mode 100644
index 0000000000000000000000000000000000000000..4559ac60645cd68575b0eee1b53508c891daa48e
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/mcp25xxfd/mcp25xxfd_base.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+/* CAN bus driver for Microchip 25XXFD CAN Controller with SPI Interface
+ *
+ * Copyright 2019 Martin Sperl <kernel@martin.sperl.org>
+ */
+#ifndef __MCP25XXFD_BASE_H
+#define __MCP25XXFD_BASE_H
+
+#include <linux/regulator/consumer.h>
+
+int mcp25xxfd_base_power_enable(struct regulator *reg, int enable);
+
+#endif /* __MCP25XXFD_BASE_H */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/mcp25xxfd/mcp25xxfd_can.c b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/mcp25xxfd/mcp25xxfd_can.c
new file mode 100644
index 0000000000000000000000000000000000000000..41944ccd1a04f657464f9ed6680f15979f14b25c
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/mcp25xxfd/mcp25xxfd_can.c
@@ -0,0 +1,685 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/* CAN bus driver for Microchip 25XXFD CAN Controller with SPI Interface
+ *
+ * Copyright 2019 Martin Sperl <kernel@martin.sperl.org>
+ */
+
+/* controller details
+ *
+ *  It has 32 FIFOs (of up to 32 CAN-frames).
+ *
+ * There are 4 Fifo types which can get configured:
+ * * TEF - Transmission Event Fifo - which consumes FIFO 0
+ *   even if it is not configured
+ * * Tansmission Queue - for up to 32 Frames.
+ *   this queue reorders CAN frames to get transmitted following the
+ *   typical CAN dominant/recessive rules on the can bus itself.
+ *   This FIFO is optional.
+ * * TX FIFO: generic TX fifos that can contain arbitrary data
+ *   and which come with a configurable priority for transmission
+ *   It is also possible to have the Controller automatically trigger
+ *   a transfer when a Filter Rule for a RTR frame matches.
+ *   Each of these fifos in principle can get configured for distinct
+ *   dlc sizes (8 thru 64 bytes)
+ * * RX FIFO: generic RX fifo which is filled via filter-rules.
+ *   Each of these fifos in principle can get configured for distinct
+ *   dlc sizes (8 thru 64 bytes)
+ *   Unfortunately there is no filter rule that would allow triggering
+ *   on different frame sizes, so for all practical purposes the
+ *   RX fifos have to be of the same size (unless one wants to experience
+ *   lost data).
+ * When a Can Frame is transmitted from the TX Queue or an individual
+ * TX FIFO then a small TEF Frame can get added to the TEF FIFO queue
+ * to log the Transmission of the frame - this includes ID, Flags
+ * (including a custom identifier/index) and the timestamp (see below).
+ *
+ * The controller provides an optional free running counter with a divider
+ * for timestamping of RX frames as well as for TEF entries.
+ */
+
+#include <linux/can/core.h>
+#include <linux/can/dev.h>
+#include <linux/device.h>
+#include <linux/interrupt.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/regulator/consumer.h>
+#include <linux/spi/spi.h>
+
+#include "mcp25xxfd_base.h"
+#include "mcp25xxfd_can_debugfs.h"
+#include "mcp25xxfd_can_fifo.h"
+#include "mcp25xxfd_can_int.h"
+#include "mcp25xxfd_can_priv.h"
+#include "mcp25xxfd_can_tx.h"
+#include "mcp25xxfd_clock.h"
+#include "mcp25xxfd_cmd.h"
+#include "mcp25xxfd_int.h"
+#include "mcp25xxfd_priv.h"
+#include "mcp25xxfd_regs.h"
+
+#include <uapi/linux/can/netlink.h>
+
+/* module parameters */
+unsigned int bw_sharing_log2bits;
+module_param(bw_sharing_log2bits, uint, 0664);
+MODULE_PARM_DESC(bw_sharing_log2bits,
+		 "Delay between 2 transmissions in number of arbitration bit times\n");
+bool enable_edge_filter;
+module_param(enable_edge_filter, bool, 0664);
+MODULE_PARM_DESC(enable_edge_filter,
+		 "Enable ISO11898-1:2015 edge_filtering");
+unsigned int tdc_mode = 2;
+module_param(tdc_mode, uint, 0664);
+MODULE_PARM_DESC(tdc_mode,
+		 "Transmitter Delay Mode - 0 = disabled, 1 = fixed, 2 = auto\n");
+unsigned int tdc_value;
+module_param(tdc_value, uint, 0664);
+MODULE_PARM_DESC(tdc_value,
+		 "Transmission Delay Value - range: [0:63] SCLK");
+int tdc_offset = 64; /* outside of range to use computed values */
+module_param(tdc_offset, int, 0664);
+MODULE_PARM_DESC(tdc_offset,
+		 "Transmission Delay offset - range: [-64:63] SCLK");
+
+/* everything related to bit timing */
+static
+const struct can_bittiming_const mcp25xxfd_can_nominal_bittiming_const = {
+	.name           = DEVICE_NAME,
+	.tseg1_min      = 2,
+	.tseg1_max      = BIT(MCP25XXFD_CAN_NBTCFG_TSEG1_BITS),
+	.tseg2_min      = 1,
+	.tseg2_max      = BIT(MCP25XXFD_CAN_NBTCFG_TSEG2_BITS),
+	.sjw_max        = BIT(MCP25XXFD_CAN_NBTCFG_SJW_BITS),
+	.brp_min        = 1,
+	.brp_max        = BIT(MCP25XXFD_CAN_NBTCFG_BRP_BITS),
+	.brp_inc        = 1,
+};
+
+static
+const struct can_bittiming_const mcp25xxfd_can_data_bittiming_const = {
+	.name           = DEVICE_NAME,
+	.tseg1_min      = 1,
+	.tseg1_max      = BIT(MCP25XXFD_CAN_DBTCFG_TSEG1_BITS),
+	.tseg2_min      = 1,
+	.tseg2_max      = BIT(MCP25XXFD_CAN_DBTCFG_TSEG2_BITS),
+	.sjw_max        = BIT(MCP25XXFD_CAN_DBTCFG_SJW_BITS),
+	.brp_min        = 1,
+	.brp_max        = BIT(MCP25XXFD_CAN_DBTCFG_BRP_BITS),
+	.brp_inc        = 1,
+};
+
+static int mcp25xxfd_can_do_set_nominal_bittiming(struct net_device *net)
+{
+	struct mcp25xxfd_can_priv *cpriv = netdev_priv(net);
+	struct can_bittiming *bt = &cpriv->can.bittiming;
+
+	int sjw = bt->sjw;
+	int pseg2 = bt->phase_seg2;
+	int pseg1 = bt->phase_seg1;
+	int propseg = bt->prop_seg;
+	int brp = bt->brp;
+
+	int tseg1 = propseg + pseg1;
+	int tseg2 = pseg2;
+
+	/* calculate nominal bit timing */
+	cpriv->regs.nbtcfg = ((sjw - 1) << MCP25XXFD_CAN_NBTCFG_SJW_SHIFT) |
+		((tseg2 - 1) << MCP25XXFD_CAN_NBTCFG_TSEG2_SHIFT) |
+		((tseg1 - 1) << MCP25XXFD_CAN_NBTCFG_TSEG1_SHIFT) |
+		((brp - 1) << MCP25XXFD_CAN_NBTCFG_BRP_SHIFT);
+
+	return mcp25xxfd_cmd_write(cpriv->priv->spi, MCP25XXFD_CAN_NBTCFG,
+				   cpriv->regs.nbtcfg);
+}
+
+static int mcp25xxfd_can_do_set_data_bittiming(struct net_device *net)
+{
+	struct mcp25xxfd_can_priv *cpriv = netdev_priv(net);
+	struct mcp25xxfd_priv *priv = cpriv->priv;
+	struct can_bittiming *bt = &cpriv->can.data_bittiming;
+	struct spi_device *spi = priv->spi;
+
+	int sjw = bt->sjw;
+	int pseg2 = bt->phase_seg2;
+	int pseg1 = bt->phase_seg1;
+	int propseg = bt->prop_seg;
+	int brp = bt->brp;
+
+	int tseg1 = propseg + pseg1;
+	int tseg2 = pseg2;
+
+	int tdco;
+	int ret;
+
+	/* set up Transmitter delay compensation */
+	cpriv->regs.tdc = 0;
+	/* configure TDC mode */
+	if (tdc_mode < 4)
+		cpriv->regs.tdc = tdc_mode << MCP25XXFD_CAN_TDC_TDCMOD_SHIFT;
+	else
+		cpriv->regs.tdc = MCP25XXFD_CAN_TDC_TDCMOD_AUTO <<
+			MCP25XXFD_CAN_TDC_TDCMOD_SHIFT;
+
+	/* configure TDC offsets */
+	if ((tdc_offset >= -64) && tdc_offset < 64)
+		tdco = tdc_offset;
+	else
+		tdco = clamp_t(int, bt->brp * tseg1, -64, 63);
+	cpriv->regs.tdc |= (tdco << MCP25XXFD_CAN_TDC_TDCO_SHIFT) &
+		MCP25XXFD_CAN_TDC_TDCO_MASK;
+
+	/* configure TDC value */
+	if (tdc_value < 64)
+		cpriv->regs.tdc |= tdc_value << MCP25XXFD_CAN_TDC_TDCV_SHIFT;
+
+	/* enable edge filtering */
+	if (enable_edge_filter)
+		cpriv->regs.tdc |= MCP25XXFD_CAN_TDC_EDGFLTEN;
+
+	/* set TDC */
+	ret = mcp25xxfd_cmd_write(spi, MCP25XXFD_CAN_TDC, cpriv->regs.tdc);
+	if (ret)
+		return ret;
+
+	/* calculate data bit timing */
+	cpriv->regs.dbtcfg = ((sjw - 1) << MCP25XXFD_CAN_DBTCFG_SJW_SHIFT) |
+		((tseg2 - 1) << MCP25XXFD_CAN_DBTCFG_TSEG2_SHIFT) |
+		((tseg1 - 1) << MCP25XXFD_CAN_DBTCFG_TSEG1_SHIFT) |
+		((brp - 1) << MCP25XXFD_CAN_DBTCFG_BRP_SHIFT);
+
+	return mcp25xxfd_cmd_write(spi, MCP25XXFD_CAN_DBTCFG,
+				   cpriv->regs.dbtcfg);
+}
+
+int mcp25xxfd_can_get_mode(struct mcp25xxfd_priv *priv, u32 *reg)
+{
+	int ret;
+
+	ret = mcp25xxfd_cmd_read(priv->spi, MCP25XXFD_CAN_CON, reg);
+	if (ret)
+		return ret;
+
+	return (*reg & MCP25XXFD_CAN_CON_OPMOD_MASK) >>
+		MCP25XXFD_CAN_CON_OPMOD_SHIFT;
+}
+
+int mcp25xxfd_can_switch_mode_no_wait(struct mcp25xxfd_priv *priv,
+				      u32 *reg, int mode)
+{
+	u32 dummy;
+	int ret;
+
+	/* get the current mode/register - if reg is NULL
+	 * when the can controller is not setup yet
+	 * typically by calling mcp25xxfd_can_sleep_mode
+	 * (this only happens during initialization phase)
+	 */
+	if (reg) {
+		if (!reg) {
+			ret = mcp25xxfd_can_get_mode(priv, reg);
+			if (ret < 0)
+				return ret;
+		}
+	} else {
+		/* alternatively use dummy */
+		dummy = 0;
+		reg = &dummy;
+	}
+
+	/* compute the effective mode in osc*/
+	*reg &= ~(MCP25XXFD_CAN_CON_REQOP_MASK |
+		  MCP25XXFD_CAN_CON_OPMOD_MASK);
+	*reg |= (mode << MCP25XXFD_CAN_CON_REQOP_SHIFT) |
+		(mode << MCP25XXFD_CAN_CON_OPMOD_SHIFT);
+
+	/* if the opmode is sleep then the oscilator will be disabled
+	 * and also not ready, so fake this change
+	 */
+	if (mode == MCP25XXFD_CAN_CON_MODE_SLEEP)
+		mcp25xxfd_clock_fake_sleep(priv);
+
+	/* request the mode switch */
+	return mcp25xxfd_cmd_write(priv->spi, MCP25XXFD_CAN_CON, *reg);
+}
+
+int mcp25xxfd_can_switch_mode(struct mcp25xxfd_priv *priv, u32 *reg, int mode)
+{
+	int ret, i;
+
+	/* trigger the mode switch itself */
+	ret = mcp25xxfd_can_switch_mode_no_wait(priv, reg, mode);
+	if (ret)
+		return ret;
+
+	/* if we are in now sleep mode then return immediately
+	 * the controller does not respond back!
+	 */
+	if (mode == MCP25XXFD_CAN_CON_MODE_SLEEP)
+		return 0;
+
+	/* wait for it to stabilize/switch mode
+	 * we assume 256 rounds should be enough as this is > 12ms
+	 * at 1MHz Can Bus speed without any extra overhead
+	 *
+	 * The assumption here is that it depends on bus activity
+	 * how long it takes the controller to switch modes
+	 */
+	for (i = 0; i < 256; i++) {
+		/* get the mode */
+		ret = mcp25xxfd_can_get_mode(priv, reg);
+		if (ret < 0)
+			return ret;
+		/* check that we have reached our mode */
+		if (ret == mode)
+			return 0;
+	}
+
+	dev_err(&priv->spi->dev, "Failed to switch to mode %u in time\n",
+		mode);
+	return -ETIMEDOUT;
+}
+
+static int mcp25xxfd_can_probe_modeswitch(struct mcp25xxfd_priv *priv)
+{
+	u32 mode_data;
+	int ret;
+
+	/* so we should be in config mode now, so move to INT_LOOPBACK */
+	ret = mcp25xxfd_can_switch_mode(priv, &mode_data,
+					MCP25XXFD_CAN_CON_MODE_INT_LOOPBACK);
+	if (ret) {
+		dev_err(&priv->spi->dev,
+			"Failed to switch into loopback mode\n");
+		return ret;
+	}
+
+	/* and back into config mode */
+	ret = mcp25xxfd_can_switch_mode(priv, &mode_data,
+					MCP25XXFD_CAN_CON_MODE_CONFIG);
+	if (ret) {
+		dev_err(&priv->spi->dev,
+			"Failed to switch back to config mode\n");
+		return ret;
+	}
+
+	/* so we have checked basic functionality successfully */
+	return 0;
+}
+
+int mcp25xxfd_can_sleep_mode(struct mcp25xxfd_priv *priv)
+{
+	return mcp25xxfd_can_switch_mode(priv, NULL,
+					 MCP25XXFD_CAN_CON_MODE_SLEEP);
+}
+
+int mcp25xxfd_can_probe(struct mcp25xxfd_priv *priv)
+{
+	struct spi_device *spi = priv->spi;
+	u32 mode_data;
+	int mode, ret;
+
+	/* read TXQCON - the TXEN bit should always read as 1 */
+	ret = mcp25xxfd_cmd_read(spi, MCP25XXFD_CAN_TXQCON, &mode_data);
+	if (ret)
+		return ret;
+	if ((mode_data & MCP25XXFD_CAN_TXQCON_TXEN) == 0) {
+		dev_err(&spi->dev,
+			"Register TXQCON does not have bit TXEN set - reads as %08x - this may be a problem with spi bus signal quality - try reducing spi-clock speed if this can get reproduced",
+			mode_data);
+		return -EINVAL;
+	}
+
+	/* try to get the current mode */
+	mode = mcp25xxfd_can_get_mode(priv, &mode_data);
+	if (mode < 0)
+		return mode;
+
+	/* we would expect to be in config mode, as a SPI-reset should
+	 * have moved us into config mode.
+	 * But then the documentation says that SPI-reset may only work
+	 * reliably when already in config mode
+	 */
+
+	/* so if we are in config mode then everything is fine
+	 * and we check that a mode switch works propperly
+	 */
+	if (mode == MCP25XXFD_CAN_CON_MODE_CONFIG)
+		return mcp25xxfd_can_probe_modeswitch(priv);
+
+	/* if the bitfield is 0 then there is something is wrong */
+	if (!mode_data) {
+		dev_err(&spi->dev,
+			"got controller config register reading as 0\n");
+		return -EINVAL;
+	}
+
+	/* any other mode is unexpected */
+	dev_err(&spi->dev,
+		"Found controller in unexpected mode %i - register reads as %08x\n",
+		mode, mode_data);
+
+	/* so try to move to config mode
+	 * if this fails, then everything is lost and the controller
+	 * is not identified
+	 * This action MAY be destructive if a different device is connected
+	 * but note that the first hurdle (oscillator) was already
+	 * successful - so we should be safe...
+	 */
+	ret = mcp25xxfd_can_switch_mode(priv, &mode_data,
+					MCP25XXFD_CAN_CON_MODE_CONFIG);
+	if (ret) {
+		dev_err(&priv->spi->dev,
+			"Mode did not switch to config as expected - could not identify controller - register reads as %08x\n",
+			mode_data);
+		return -EINVAL;
+	}
+	/* check that modeswitch is really working */
+	return mcp25xxfd_can_probe_modeswitch(priv);
+}
+
+static int mcp25xxfd_can_config(struct net_device *net)
+{
+	struct mcp25xxfd_can_priv *cpriv = netdev_priv(net);
+	struct mcp25xxfd_priv *priv = cpriv->priv;
+	struct spi_device *spi = priv->spi;
+	int ret;
+
+	/* setup value of con_register */
+	cpriv->regs.con = MCP25XXFD_CAN_CON_STEF; /* enable TEF, disable TXQ */
+
+	/* transmission bandwidth sharing bits */
+	if (bw_sharing_log2bits > 12)
+		bw_sharing_log2bits = 12;
+	cpriv->regs.con |= bw_sharing_log2bits <<
+		MCP25XXFD_CAN_CON_TXBWS_SHIFT;
+
+	/* non iso FD mode */
+	if (!(cpriv->can.ctrlmode & CAN_CTRLMODE_FD_NON_ISO))
+		cpriv->regs.con |= MCP25XXFD_CAN_CON_ISOCRCEN;
+
+	/* one shot */
+	if (cpriv->can.ctrlmode & CAN_CTRLMODE_ONE_SHOT)
+		cpriv->regs.con |= MCP25XXFD_CAN_CON_RTXAT;
+
+	/* apply it now together with a mode switch */
+	ret = mcp25xxfd_can_switch_mode(cpriv->priv, &cpriv->regs.con,
+					MCP25XXFD_CAN_CON_MODE_CONFIG);
+	if (ret)
+		return 0;
+
+	/* time stamp control register - 1ns resolution */
+	cpriv->regs.tscon = 0;
+	ret = mcp25xxfd_cmd_write(spi, MCP25XXFD_CAN_TBC, 0);
+	if (ret)
+		return ret;
+
+	cpriv->regs.tscon = MCP25XXFD_CAN_TSCON_TBCEN |
+		((cpriv->can.clock.freq / 1000000)
+		 << MCP25XXFD_CAN_TSCON_TBCPRE_SHIFT);
+	ret = mcp25xxfd_cmd_write(spi, MCP25XXFD_CAN_TSCON, cpriv->regs.tscon);
+	if (ret)
+		return ret;
+
+	/* setup fifos */
+	ret = mcp25xxfd_can_fifo_setup(cpriv);
+	if (ret)
+		return ret;
+
+	/* setup can bittiming now - the do_set_bittiming methods
+	 * are not used as they get callled before open
+	 */
+	ret = mcp25xxfd_can_do_set_nominal_bittiming(net);
+	if (ret)
+		return ret;
+	ret = mcp25xxfd_can_do_set_data_bittiming(net);
+	if (ret)
+		return ret;
+
+	return ret;
+}
+
+/* mode setting */
+static int mcp25xxfd_can_do_set_mode(struct net_device *net,
+				     enum can_mode mode)
+{
+	switch (mode) {
+	case CAN_MODE_START:
+		break;
+	default:
+		return -EOPNOTSUPP;
+	}
+
+	return 0;
+}
+
+/* binary error counters */
+static int mcp25xxfd_can_get_berr_counter(const struct net_device *net,
+					  struct can_berr_counter *bec)
+{
+	struct mcp25xxfd_can_priv *cpriv = netdev_priv(net);
+
+	bec->txerr = (cpriv->status.trec & MCP25XXFD_CAN_TREC_TEC_MASK) >>
+		MCP25XXFD_CAN_TREC_TEC_SHIFT;
+	bec->rxerr = (cpriv->status.trec & MCP25XXFD_CAN_TREC_REC_MASK) >>
+		MCP25XXFD_CAN_TREC_REC_SHIFT;
+
+	return 0;
+}
+
+static int mcp25xxfd_can_open(struct net_device *net)
+{
+	struct mcp25xxfd_can_priv *cpriv = netdev_priv(net);
+	struct spi_device *spi = cpriv->priv->spi;
+	int ret;
+
+	ret = open_candev(net);
+	if (ret) {
+		netdev_err(net, "unable to set initial baudrate!\n");
+		return ret;
+	}
+
+	/* clear those statistics */
+	memset(&cpriv->stats, 0, sizeof(cpriv->stats));
+
+	/* request an IRQ but keep disabled for now */
+	ret = request_threaded_irq(spi->irq, NULL, 
+				   mcp25xxfd_can_int,
+				   IRQF_ONESHOT | IRQ_TYPE_EDGE_FALLING,
+				   cpriv->priv->device_name, cpriv);
+	if (ret) {
+		dev_err(&spi->dev, "failed to acquire irq %d - %i\n",
+			spi->irq, ret);
+		goto out_candev;
+	}
+
+	disable_irq(spi->irq);
+	cpriv->irq.allocated = true;
+	cpriv->irq.enabled = false;
+
+	/* enable power to the transceiver */
+	ret = mcp25xxfd_base_power_enable(cpriv->transceiver, 1);
+	if (ret)
+		goto out_irq;
+
+	/* enable clock (so that spi works) */
+	ret = mcp25xxfd_clock_start(cpriv->priv, MCP25XXFD_CLK_USER_CAN);
+	if (ret)
+		goto out_transceiver;
+
+	/* configure controller for reception */
+	ret = mcp25xxfd_can_config(net);
+	if (ret)
+		goto out_canclock;
+
+	/* setting up state */
+	cpriv->can.state = CAN_STATE_ERROR_ACTIVE;
+
+	/* enable interrupts */
+	ret = mcp25xxfd_int_enable(cpriv->priv, true);
+	if (ret)
+		goto out_canconfig;
+
+	/* switch to active mode */
+	ret = mcp25xxfd_can_switch_mode(cpriv->priv, &cpriv->regs.con,
+					(net->mtu == CAN_MTU) ?
+					MCP25XXFD_CAN_CON_MODE_CAN2_0 :
+					MCP25XXFD_CAN_CON_MODE_MIXED);
+	if (ret)
+		goto out_int;
+
+	/* start the tx_queue */
+	mcp25xxfd_can_tx_queue_manage(cpriv,
+				      MCP25XXFD_CAN_TX_QUEUE_STATE_STARTED);
+
+	return 0;
+
+out_int:
+	mcp25xxfd_int_enable(cpriv->priv, false);
+out_canconfig:
+	mcp25xxfd_can_fifo_release(cpriv);
+out_canclock:
+	mcp25xxfd_clock_stop(cpriv->priv, MCP25XXFD_CLK_USER_CAN);
+out_transceiver:
+	mcp25xxfd_base_power_enable(cpriv->transceiver, 0);
+out_irq:
+	free_irq(spi->irq, cpriv);
+	cpriv->irq.allocated = false;
+	cpriv->irq.enabled = false;
+out_candev:
+	close_candev(net);
+	return ret;
+}
+
+static void mcp25xxfd_can_shutdown(struct mcp25xxfd_can_priv *cpriv)
+{
+	/* switch us to CONFIG mode - this disables the controller */
+	mcp25xxfd_can_switch_mode(cpriv->priv, &cpriv->regs.con,
+				  MCP25XXFD_CAN_CON_MODE_CONFIG);
+}
+
+static int mcp25xxfd_can_stop(struct net_device *net)
+{
+	struct mcp25xxfd_can_priv *cpriv = netdev_priv(net);
+	struct mcp25xxfd_priv *priv = cpriv->priv;
+	struct spi_device *spi = priv->spi;
+
+	/* stop transmit queue */
+	mcp25xxfd_can_tx_queue_manage(cpriv,
+				      MCP25XXFD_CAN_TX_QUEUE_STATE_STOPPED);
+
+	/* release fifos and debugfs */
+	mcp25xxfd_can_fifo_release(cpriv);
+
+	/* shutdown the can controller */
+	mcp25xxfd_can_shutdown(cpriv);
+
+	/* disable inerrupts on controller */
+	mcp25xxfd_int_enable(cpriv->priv, false);
+
+	/* stop the clock */
+	mcp25xxfd_clock_stop(cpriv->priv, MCP25XXFD_CLK_USER_CAN);
+
+	/* and disable the transceiver */
+	mcp25xxfd_base_power_enable(cpriv->transceiver, 0);
+
+	/* disable interrupt on host */
+	free_irq(spi->irq, cpriv);
+	cpriv->irq.allocated = false;
+	cpriv->irq.enabled = false;
+
+	/* close the can_decice */
+	close_candev(net);
+
+	return 0;
+}
+
+static const struct net_device_ops mcp25xxfd_netdev_ops = {
+	.ndo_open = mcp25xxfd_can_open,
+	.ndo_stop = mcp25xxfd_can_stop,
+	.ndo_start_xmit = mcp25xxfd_can_tx_start_xmit,
+	.ndo_change_mtu = can_change_mtu,
+};
+
+/* probe and remove */
+int mcp25xxfd_can_setup(struct mcp25xxfd_priv *priv)
+{
+	struct spi_device *spi = priv->spi;
+	struct mcp25xxfd_can_priv *cpriv;
+	struct net_device *net;
+	struct regulator *transceiver;
+	int ret;
+
+	/* get transceiver power regulator*/
+	transceiver = devm_regulator_get_optional(&spi->dev,
+						  "xceiver");
+	if (PTR_ERR(transceiver) == -EPROBE_DEFER)
+		return -EPROBE_DEFER;
+
+	/* allocate can device */
+	net = alloc_candev(sizeof(*cpriv), TX_ECHO_SKB_MAX);
+	if (!net)
+		return -ENOMEM;
+
+	/* and do some cross-asignments */
+	cpriv = netdev_priv(net);
+	cpriv->priv = priv;
+	priv->cpriv = cpriv;
+
+	/* setup network */
+	SET_NETDEV_DEV(net, &spi->dev);
+	net->netdev_ops = &mcp25xxfd_netdev_ops;
+	net->flags |= IFF_ECHO;
+
+	/* assign transceiver */
+	cpriv->transceiver = transceiver;
+
+	/* setup can */
+	cpriv->can.clock.freq = priv->clock_freq;
+	cpriv->can.bittiming_const =
+		&mcp25xxfd_can_nominal_bittiming_const;
+	cpriv->can.data_bittiming_const =
+		&mcp25xxfd_can_data_bittiming_const;
+	/* we are not setting bit-timing methods here as they get
+	 * called by the framework before open so the controller is
+	 * still in sleep mode, which does not help
+	 * things are configured in open instead
+	 */
+	cpriv->can.do_set_mode =
+		mcp25xxfd_can_do_set_mode;
+	cpriv->can.do_get_berr_counter =
+		mcp25xxfd_can_get_berr_counter;
+	cpriv->can.ctrlmode_supported =
+		CAN_CTRLMODE_FD |
+		CAN_CTRLMODE_FD_NON_ISO |
+		CAN_CTRLMODE_LOOPBACK |
+		CAN_CTRLMODE_LISTENONLY |
+		CAN_CTRLMODE_BERR_REPORTING |
+		CAN_CTRLMODE_ONE_SHOT;
+
+	ret = register_candev(net);
+	if (ret) {
+		dev_err(&spi->dev, "Failed to register can device\n");
+		goto out;
+	}
+
+	mcp25xxfd_can_debugfs_setup(cpriv);
+
+	return 0;
+out:
+	free_candev(net);
+	priv->cpriv = NULL;
+
+	return ret;
+}
+
+void mcp25xxfd_can_remove(struct mcp25xxfd_priv *priv)
+{
+	if (priv->cpriv) {
+		unregister_candev(priv->cpriv->can.dev);
+		free_candev(priv->cpriv->can.dev);
+		priv->cpriv = NULL;
+	}
+}
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/mcp25xxfd/mcp25xxfd_can.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/mcp25xxfd/mcp25xxfd_can.h
new file mode 100644
index 0000000000000000000000000000000000000000..b480220d4ccd9e3a29a56d6d6bbb7fd6f8663aba
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/mcp25xxfd/mcp25xxfd_can.h
@@ -0,0 +1,56 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+/* CAN bus driver for Microchip 25XXFD CAN Controller with SPI Interface
+ *
+ * Copyright 2019 Martin Sperl <kernel@martin.sperl.org>
+ */
+
+#ifndef __MCP25XXFD_CAN_H
+#define __MCP25XXFD_CAN_H
+
+#include "mcp25xxfd_can_debugfs.h"
+#include "mcp25xxfd_can_priv.h"
+#include "mcp25xxfd_priv.h"
+#include "mcp25xxfd_regs.h"
+
+/* get the optimal controller target mode */
+static inline
+int mcp25xxfd_can_targetmode(struct mcp25xxfd_can_priv *cpriv)
+{
+	return (cpriv->can.dev->mtu == CAN_MTU) ?
+		MCP25XXFD_CAN_CON_MODE_CAN2_0 : MCP25XXFD_CAN_CON_MODE_MIXED;
+}
+
+static inline
+void mcp25xxfd_can_queue_frame(struct mcp25xxfd_can_priv *cpriv,
+			       s32 fifo, u16 ts, bool is_rx)
+{
+	int idx = cpriv->fifos.submit_queue_count;
+
+	cpriv->fifos.submit_queue[idx].fifo = fifo;
+	cpriv->fifos.submit_queue[idx].ts = ts;
+	cpriv->fifos.submit_queue[idx].is_rx = is_rx;
+
+	MCP25XXFD_DEBUGFS_INCR(cpriv->fifos.submit_queue_count);
+}
+
+/* get the current controller mode */
+int mcp25xxfd_can_get_mode(struct mcp25xxfd_priv *priv, u32 *reg);
+
+/* to put us to sleep fully we need the CAN controller to enter sleep mode */
+int mcp25xxfd_can_sleep_mode(struct mcp25xxfd_priv *priv);
+
+/* switch controller mode */
+int mcp25xxfd_can_switch_mode_no_wait(struct mcp25xxfd_priv *priv,
+				      u32 *reg, int mode);
+int mcp25xxfd_can_switch_mode(struct mcp25xxfd_priv *priv,
+			      u32 *reg, int mode);
+
+/* probe the can controller */
+int mcp25xxfd_can_probe(struct mcp25xxfd_priv *priv);
+
+/* setup and the can controller net interface */
+int mcp25xxfd_can_setup(struct mcp25xxfd_priv *priv);
+void mcp25xxfd_can_remove(struct mcp25xxfd_priv *priv);
+
+#endif /* __MCP25XXFD_CAN_H */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/mcp25xxfd/mcp25xxfd_can_debugfs.c b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/mcp25xxfd/mcp25xxfd_can_debugfs.c
new file mode 100644
index 0000000000000000000000000000000000000000..d2caf82a6b3e5f8f4ae4fbdf1dd6b609fbcdf1e3
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/mcp25xxfd/mcp25xxfd_can_debugfs.c
@@ -0,0 +1,235 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/* CAN bus driver for Microchip 25XXFD CAN Controller with SPI Interface
+ *
+ * Copyright 2019 Martin Sperl <kernel@martin.sperl.org>
+ */
+
+#ifdef CONFIG_DEBUG_FS
+
+#include <linux/dcache.h>
+#include <linux/debugfs.h>
+#include "mcp25xxfd_can_priv.h"
+#include "mcp25xxfd_can_tx.h"
+
+static void mcp25xxfd_can_debugfs_regs(struct mcp25xxfd_can_priv *cpriv,
+				       struct dentry *root)
+{
+	struct dentry *dir = debugfs_create_dir("regs", root);
+
+	debugfs_create_x32("con",    0444, dir, &cpriv->regs.con);
+	debugfs_create_x32("tdc",    0444, dir, &cpriv->regs.tdc);
+	debugfs_create_x32("tscon",  0444, dir, &cpriv->regs.tscon);
+	debugfs_create_x32("tefcon", 0444, dir, &cpriv->regs.tscon);
+	debugfs_create_x32("nbtcfg", 0444, dir, &cpriv->regs.nbtcfg);
+	debugfs_create_x32("dbtcfg", 0444, dir, &cpriv->regs.dbtcfg);
+}
+
+static void mcp25xxfd_can_debugfs_status(struct mcp25xxfd_can_priv *cpriv,
+					 struct dentry *root)
+{
+	struct dentry *dir = debugfs_create_dir("status", root);
+
+	debugfs_create_x32("intf",    0444, dir, &cpriv->status.intf);
+	debugfs_create_x32("rx_if",   0444, dir, &cpriv->status.rxif);
+	debugfs_create_x32("tx_if",   0444, dir, &cpriv->status.txif);
+	debugfs_create_x32("rx_ovif", 0444, dir, &cpriv->status.rxovif);
+	debugfs_create_x32("tx_atif", 0444, dir, &cpriv->status.txatif);
+	debugfs_create_x32("tx_req",  0444, dir, &cpriv->status.txreq);
+	debugfs_create_x32("trec",    0444, dir, &cpriv->status.trec);
+}
+
+static void mcp25xxfd_can_debugfs_stats(struct mcp25xxfd_can_priv *cpriv,
+					struct dentry *root)
+{
+	struct dentry *dir = debugfs_create_dir("stats", root);
+	char name[32];
+	u64 *data;
+	int i;
+
+# define DEBUGFS_CREATE(name, var) debugfs_create_u64(name, 0444, dir, \
+						      &cpriv->stats.var)
+	DEBUGFS_CREATE("irq_calls",		 irq_calls);
+	DEBUGFS_CREATE("irq_loops",		 irq_loops);
+	DEBUGFS_CREATE("irq_thread_rescheduled", irq_thread_rescheduled);
+
+	DEBUGFS_CREATE("int_system_error",	 int_serr_count);
+	DEBUGFS_CREATE("int_system_error_tx",	 int_serr_tx_count);
+	DEBUGFS_CREATE("int_system_error_rx",	 int_serr_rx_count);
+	DEBUGFS_CREATE("int_mode_switch",	 int_mod_count);
+	DEBUGFS_CREATE("int_rx",		 int_rx_count);
+	DEBUGFS_CREATE("int_tx_attempt",	 int_txat_count);
+	DEBUGFS_CREATE("int_tef",		 int_tef_count);
+	DEBUGFS_CREATE("int_rx_overflow",	 int_rxov_count);
+	DEBUGFS_CREATE("int_ecc_error",		 int_ecc_count);
+	DEBUGFS_CREATE("int_rx_invalid_message", int_ivm_count);
+	DEBUGFS_CREATE("int_crcerror",		 int_cerr_count);
+
+	DEBUGFS_CREATE("tef_reads",		 tef_reads);
+	DEBUGFS_CREATE("tef_conservative_reads", tef_conservative_reads);
+	DEBUGFS_CREATE("tef_optimized_reads",	 tef_optimized_reads);
+	DEBUGFS_CREATE("tef_read_splits",	 tef_read_splits);
+
+	for (i = 0; i < MCP25XXFD_CAN_TEF_READ_BINS - 1; i++) {
+		snprintf(name, sizeof(name),
+			 "tef_optimized_reads_%i", i + 1);
+		data = &cpriv->stats.tef_optimized_read_sizes[i];
+		debugfs_create_u64(name, 0444, dir, data);
+	}
+	snprintf(name, sizeof(name), "tef_optimized_reads_%i+", i + 1);
+	debugfs_create_u64(name, 0444, dir,
+			   &cpriv->stats.tef_optimized_read_sizes[i]);
+
+	DEBUGFS_CREATE("tx_frames_fd",		 tx_fd_count);
+	DEBUGFS_CREATE("tx_frames_brs",		 tx_brs_count);
+
+	DEBUGFS_CREATE("rx_reads",		 rx_reads);
+	DEBUGFS_CREATE("rx_reads_prefetched_too_few",
+		       rx_reads_prefetched_too_few);
+	DEBUGFS_CREATE("rx_reads_prefetched_too_few_bytes",
+		       rx_reads_prefetched_too_few_bytes);
+	DEBUGFS_CREATE("rx_reads_prefetched_too_many",
+		       rx_reads_prefetched_too_many);
+	DEBUGFS_CREATE("rx_reads_prefetched_too_many_bytes",
+		       rx_reads_prefetched_too_many_bytes);
+	DEBUGFS_CREATE("rx_single_reads",	 rx_single_reads);
+	DEBUGFS_CREATE("rx_bulk_reads",		 rx_bulk_reads);
+
+	for (i = 0; i < MCP25XXFD_CAN_RX_BULK_READ_BINS - 1; i++) {
+		snprintf(name, sizeof(name), "rx_bulk_reads_%i", i + 1);
+		data = &cpriv->stats.rx_bulk_read_sizes[i];
+		debugfs_create_u64(name, 0444, dir, data);
+	}
+	snprintf(name, sizeof(name), "rx_bulk_reads_%i+", i + 1);
+	debugfs_create_u64(name, 0444, dir,
+			   &cpriv->stats.rx_bulk_read_sizes[i]);
+
+	if (cpriv->can.dev->mtu == CANFD_MTU)
+		debugfs_create_u32("rx_reads_prefetch_predicted_len", 0444,
+				   dir, &cpriv->rx_history.predicted_len);
+#undef DEBUGFS_CREATE
+}
+
+static void mcp25xxfd_can_debugfs_tef(struct mcp25xxfd_can_priv *cpriv,
+				      struct dentry *root)
+{
+	struct dentry *dir = debugfs_create_dir("tef", root);
+
+	debugfs_create_u32("count", 0444, dir, &cpriv->fifos.tef.count);
+	debugfs_create_u32("size",  0444, dir, &cpriv->fifos.tef.size);
+}
+
+static void mcp25xxfd_can_debugfs_fifo_info(struct mcp25xxfd_fifo_info *info,
+					    int index, struct dentry *root)
+{
+	struct dentry *dir;
+	char name[4];
+
+	snprintf(name, sizeof(name), "%02i", index);
+	dir = debugfs_create_dir(name, root);
+
+	debugfs_create_u32("is_rx",     0444, dir, &info->is_rx);
+	debugfs_create_x32("offset",    0444, dir, &info->offset);
+	debugfs_create_u32("priority",  0444, dir, &info->priority);
+
+	debugfs_create_u64("use_count", 0444, dir, &info->use_count);
+}
+
+static void mcp25xxfd_can_debugfs_fifos(struct mcp25xxfd_can_priv *cpriv,
+					struct dentry *root)
+{
+	struct dentry *dir = debugfs_create_dir("fifos", root);
+	int i;
+
+	/* now present all fifos - there is no fifo 0 */
+	for (i = 1; i < 32; i++)
+		mcp25xxfd_can_debugfs_fifo_info(&cpriv->fifos.info[i], i, dir);
+}
+
+static void mcp25xxfd_can_debugfs_rxtx_fifos(struct mcp25xxfd_fifo *d,
+					     struct dentry *root)
+{
+	int i, f;
+	char name[4];
+	char link[32];
+
+	debugfs_create_u32("count", 0444, root, &d->count);
+	debugfs_create_u32("size",  0444, root, &d->size);
+	debugfs_create_u32("start", 0444, root, &d->start);
+
+	for (f = d->start, i = 0; i < d->count; f++, i++) {
+		snprintf(name, sizeof(name), "%02i", i);
+		snprintf(link, sizeof(link), "../fifos/%02i", f);
+
+		debugfs_create_symlink(name, root, link);
+	}
+}
+
+static void mcp25xxfd_can_debugfs_rx_fifos(struct mcp25xxfd_can_priv *cpriv,
+					   struct dentry *root)
+{
+	struct dentry *dir = debugfs_create_dir("rx_fifos", root);
+
+	mcp25xxfd_can_debugfs_rxtx_fifos(&cpriv->fifos.rx, dir);
+}
+
+static void mcp25xxfd_can_debugfs_tx_fifos(struct mcp25xxfd_can_priv *cpriv,
+					   struct dentry *root)
+{
+	struct dentry *dir = debugfs_create_dir("tx_fifos", root);
+
+	mcp25xxfd_can_debugfs_rxtx_fifos(&cpriv->fifos.rx, dir);
+}
+
+static void mcp25xxfd_can_debugfs_tx_queue(struct mcp25xxfd_can_priv *cpriv,
+					   struct dentry *root)
+{
+	struct mcp25xxfd_tx_spi_message_queue *queue = cpriv->fifos.tx_queue;
+	struct dentry *dir;
+
+	if (!queue)
+		return;
+
+	dir = debugfs_create_dir("tx_queue", root);
+
+	debugfs_create_u32("state", 0444, dir, &queue->state);
+	debugfs_create_x32("fifos_idle", 0444, dir, &queue->idle);
+	debugfs_create_x32("fifos_in_fill_fifo_transfer",
+			   0444, dir, &queue->in_fill_fifo_transfer);
+	debugfs_create_x32("fifos_in_trigger_fifo_transfer",
+			   0444, dir, &queue->in_trigger_fifo_transfer);
+	debugfs_create_x32("fifos_in_can_transfer",
+			   0444, dir, &queue->in_can_transfer);
+	debugfs_create_x32("fifos_transferred",
+			   0444, dir, &queue->transferred);
+}
+
+void mcp25xxfd_can_debugfs_remove(struct mcp25xxfd_can_priv *cpriv)
+{
+	debugfs_remove_recursive(cpriv->debugfs_dir);
+	cpriv->debugfs_dir = NULL;
+}
+
+void mcp25xxfd_can_debugfs_setup(struct mcp25xxfd_can_priv *cpriv)
+{
+	struct dentry *root;
+
+	/* remove first as we get called during probe and also
+	 * when the can_device is configured/removed
+	 */
+	mcp25xxfd_can_debugfs_remove(cpriv);
+
+	root = debugfs_create_dir("can", cpriv->priv->debugfs_dir);
+	cpriv->debugfs_dir = root;
+
+	mcp25xxfd_can_debugfs_regs(cpriv, root);
+	mcp25xxfd_can_debugfs_stats(cpriv, root);
+	mcp25xxfd_can_debugfs_status(cpriv, root);
+	mcp25xxfd_can_debugfs_tef(cpriv, root);
+	mcp25xxfd_can_debugfs_fifos(cpriv, root);
+	mcp25xxfd_can_debugfs_rx_fifos(cpriv, root);
+	mcp25xxfd_can_debugfs_tx_fifos(cpriv, root);
+	mcp25xxfd_can_debugfs_tx_queue(cpriv, root);
+}
+
+#endif
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/mcp25xxfd/mcp25xxfd_can_debugfs.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/mcp25xxfd/mcp25xxfd_can_debugfs.h
new file mode 100644
index 0000000000000000000000000000000000000000..7c6a255c94004e9232cf602cfd24ba210ba0db80
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/mcp25xxfd/mcp25xxfd_can_debugfs.h
@@ -0,0 +1,44 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+/* CAN bus driver for Microchip 25XXFD CAN Controller with SPI Interface
+ *
+ * Copyright 2019 Martin Sperl <kernel@martin.sperl.org>
+ */
+
+#ifndef __MCP25XXFD_CAN_DEBUGFS_H
+#define __MCP25XXFD_CAN_DEBUGFS_H
+
+#ifdef CONFIG_DEBUG_FS
+
+#include <linux/debugfs.h>
+#include "mcp25xxfd_can_priv.h"
+
+#define MCP25XXFD_DEBUGFS_INCR(counter) ((counter)++)
+#define MCP25XXFD_DEBUGFS_ADD(counter, val) ((counter) += (val))
+#define MCP25XXFD_DEBUGFS_STATS_INCR(cpriv, counter)		\
+	(((cpriv)->stats.counter)++)
+#define MCP25XXFD_DEBUGFS_STATS_ADD(cpriv, counter, val)	\
+	(((cpriv)->stats.counter) += (val))
+
+void mcp25xxfd_can_debugfs_setup(struct mcp25xxfd_can_priv *cpriv);
+void mcp25xxfd_can_debugfs_remove(struct mcp25xxfd_can_priv *cpriv);
+
+#else /* CONFIG_DEBUG_FS */
+
+#define MCP25XXFD_DEBUGFS_INCR(counter)
+#define MCP25XXFD_DEBUGFS_ADD(counter, val)
+#define MCP25XXFD_DEBUGFS_STATS_INCR(cpriv, counter)
+#define MCP25XXFD_DEBUGFS_STATS_ADD(cpriv, counter, val)
+
+static inline
+void mcp25xxfd_can_debugfs_setup(struct mcp25xxfd_can_priv *cpriv)
+{
+}
+
+static inline
+void mcp25xxfd_can_debugfs_remove(struct mcp25xxfd_can_priv *cpriv)
+{
+}
+
+#endif /* CONFIG_DEBUG_FS */
+#endif /* __MCP25XXFD_CAN_DEBUGFS_H */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/mcp25xxfd/mcp25xxfd_can_fifo.c b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/mcp25xxfd/mcp25xxfd_can_fifo.c
new file mode 100644
index 0000000000000000000000000000000000000000..bf94120f260962e7107748196871fae58d969425
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/mcp25xxfd/mcp25xxfd_can_fifo.c
@@ -0,0 +1,347 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/* CAN bus driver for Microchip 25XXFD CAN Controller with SPI Interface
+ *
+ * Copyright 2019 Martin Sperl <kernel@martin.sperl.org>
+ */
+
+/* here we define and configure the fifo layout */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/spi/spi.h>
+
+#include "mcp25xxfd_can.h"
+#include "mcp25xxfd_can_priv.h"
+#include "mcp25xxfd_can_tx.h"
+#include "mcp25xxfd_cmd.h"
+
+/* some controller parameters are currently not configurable via netlink
+ * so we allow to control them via module parameters (that can changed
+ * in /sys if needed) - theses are only needed during setup if the can_device
+ */
+unsigned int tx_fifos;
+module_param(tx_fifos, uint, 0664);
+MODULE_PARM_DESC(tx_fifos, "Number of tx-fifos to configure\n");
+
+bool three_shot;
+module_param(three_shot, bool, 0664);
+MODULE_PARM_DESC(three_shot, "Use 3 shots when one-shot is requested");
+
+static int mcp25xxfd_can_fifo_get_address(struct mcp25xxfd_can_priv *cpriv)
+{
+	int fifo, ret;
+
+	/* we need to move out of config mode to force address computation */
+	ret = mcp25xxfd_can_switch_mode(cpriv->priv, &cpriv->regs.con,
+					MCP25XXFD_CAN_CON_MODE_INT_LOOPBACK);
+	if (ret)
+		return ret;
+
+	/* and get back into config mode */
+	ret = mcp25xxfd_can_switch_mode(cpriv->priv, &cpriv->regs.con,
+					MCP25XXFD_CAN_CON_MODE_CONFIG);
+	if (ret)
+		return ret;
+
+	/* read address and config back in */
+	for (fifo = 1; fifo < 32; fifo++) {
+		ret = mcp25xxfd_cmd_read(cpriv->priv->spi,
+					 MCP25XXFD_CAN_FIFOUA(fifo),
+					 &cpriv->fifos.info[fifo].offset);
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+}
+
+static int mcp25xxfd_can_fifo_setup_config(struct mcp25xxfd_can_priv *cpriv,
+					   struct mcp25xxfd_fifo *desc,
+					   u32 flags, u32 flags_last)
+{
+	u32 val;
+	int i, p, f, c, ret;
+
+	/* now setup the fifos themselves */
+	for (i = 0, f = desc->start, c = desc->count, p = 31;
+	     c > 0; i++, f++, p--, c--) {
+		/* select the effective value */
+		val = (c > 1) ? flags : flags_last;
+
+		/* are we in tx mode */
+		if (flags & MCP25XXFD_CAN_FIFOCON_TXEN) {
+			cpriv->fifos.info[f].is_rx = false;
+			cpriv->fifos.info[f].priority = p;
+			val |= (p << MCP25XXFD_CAN_FIFOCON_TXPRI_SHIFT);
+		} else {
+			cpriv->fifos.info[f].is_rx = true;
+		}
+
+		/* write the config to the controller in one go */
+		ret = mcp25xxfd_cmd_write(cpriv->priv->spi,
+					  MCP25XXFD_CAN_FIFOCON(f), val);
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+}
+
+static int mcp25xxfd_can_fifo_setup_tx(struct mcp25xxfd_can_priv *cpriv)
+{
+	u32 tx_flags = MCP25XXFD_CAN_FIFOCON_FRESET |     /* reset FIFO */
+		MCP25XXFD_CAN_FIFOCON_TXEN |              /* a tx FIFO */
+		MCP25XXFD_CAN_FIFOCON_TXATIE |            /* state in txatif */
+		(cpriv->fifos.payload_mode <<
+		 MCP25XXFD_CAN_FIFOCON_PLSIZE_SHIFT) |    /* paylod size */
+		(0 << MCP25XXFD_CAN_FIFOCON_FSIZE_SHIFT); /* 1 FIFO deep */
+
+	/* handle oneshot/three-shot */
+	if (cpriv->can.ctrlmode & CAN_CTRLMODE_ONE_SHOT)
+		if (three_shot)
+			tx_flags |= MCP25XXFD_CAN_FIFOCON_TXAT_THREE_SHOT <<
+				MCP25XXFD_CAN_FIFOCON_TXAT_SHIFT;
+		else
+			tx_flags |= MCP25XXFD_CAN_FIFOCON_TXAT_ONE_SHOT <<
+				MCP25XXFD_CAN_FIFOCON_TXAT_SHIFT;
+	else
+		tx_flags |= MCP25XXFD_CAN_FIFOCON_TXAT_UNLIMITED <<
+			MCP25XXFD_CAN_FIFOCON_TXAT_SHIFT;
+
+	return mcp25xxfd_can_fifo_setup_config(cpriv, &cpriv->fifos.tx,
+					       tx_flags, tx_flags);
+}
+
+static int mcp25xxfd_can_fifo_setup_rx(struct mcp25xxfd_can_priv *cpriv)
+{
+	u32 rx_flags = MCP25XXFD_CAN_FIFOCON_FRESET |     /* reset FIFO */
+		MCP25XXFD_CAN_FIFOCON_RXTSEN |            /* RX timestamps */
+		MCP25XXFD_CAN_FIFOCON_TFERFFIE |          /* FIFO Full */
+		MCP25XXFD_CAN_FIFOCON_TFHRFHIE |          /* FIFO Half Full*/
+		MCP25XXFD_CAN_FIFOCON_TFNRFNIE |          /* FIFO not empty */
+		(cpriv->fifos.payload_mode <<
+		 MCP25XXFD_CAN_FIFOCON_PLSIZE_SHIFT) |
+		(0 << MCP25XXFD_CAN_FIFOCON_FSIZE_SHIFT); /* 1 FIFO deep */
+	/* enable overflow int on last fifo */
+	u32 rx_flags_last = rx_flags | MCP25XXFD_CAN_FIFOCON_RXOVIE;
+
+	return mcp25xxfd_can_fifo_setup_config(cpriv, &cpriv->fifos.rx,
+					       rx_flags, rx_flags_last);
+}
+
+static int mcp25xxfd_can_fifo_setup_rxfilter(struct mcp25xxfd_can_priv *cpriv)
+{
+	u8 filter_con[32];
+	int c, f;
+
+	/* clear the filters and filter mappings for all filters */
+	memset(filter_con, 0, sizeof(filter_con));
+
+	/* and now set up the rx filters */
+	for (c = 0, f = cpriv->fifos.rx.start; c < cpriv->fifos.rx.count;
+	     c++, f++) {
+		/* set up filter config - we can use the mask of filter 0 */
+		filter_con[c] = MCP25XXFD_CAN_FIFOCON_FLTEN(0) |
+			(f << MCP25XXFD_CAN_FILCON_SHIFT(0));
+	}
+
+	/* and set up filter control */
+	return mcp25xxfd_cmd_write_regs(cpriv->priv->spi,
+					MCP25XXFD_CAN_FLTCON(0),
+					(u32 *)filter_con, sizeof(filter_con));
+}
+
+static int mcp25xxfd_can_fifo_compute(struct mcp25xxfd_can_priv *cpriv)
+{
+	int tef_memory_used, tx_memory_used, rx_memory_available;
+
+	/* default settings as per MTU/CANFD */
+	switch (cpriv->can.dev->mtu) {
+	case CAN_MTU:
+		/* mtu is 8 */
+		cpriv->fifos.payload_size = 8;
+		cpriv->fifos.payload_mode = MCP25XXFD_CAN_TXQCON_PLSIZE_8;
+
+		/* 7 tx fifos */
+		cpriv->fifos.tx.count = 7;
+
+		break;
+	case CANFD_MTU:
+		/* wish there was a way to have hw filters
+		 * that can separate based on length ...
+		 */
+		/* MTU is 64 */
+		cpriv->fifos.payload_size = 64;
+		cpriv->fifos.payload_mode = MCP25XXFD_CAN_TXQCON_PLSIZE_64;
+
+		/* 7 tx fifos */
+		cpriv->fifos.tx.count = 7;
+
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	/* compute effective sizes */
+	cpriv->fifos.tef.size = sizeof(struct mcp25xxfd_can_obj_tef);
+	cpriv->fifos.tx.size = sizeof(struct mcp25xxfd_can_obj_tx) +
+		cpriv->fifos.payload_size;
+	cpriv->fifos.rx.size = sizeof(struct mcp25xxfd_can_obj_rx) +
+		cpriv->fifos.payload_size;
+
+	/* if defined as a module parameter modify the number of tx_fifos */
+	if (tx_fifos) {
+		netdev_info(cpriv->can.dev,
+			    "Using %i tx-fifos as per module parameter\n",
+			    tx_fifos);
+		cpriv->fifos.tx.count = tx_fifos;
+	}
+
+	/* there can be at the most 30 tx fifos (TEF and at least 1 RX fifo */
+	if (cpriv->fifos.tx.count > 30) {
+		netdev_err(cpriv->can.dev,
+			   "There is an absolute maximum of 30 tx-fifos\n");
+		return -EINVAL;
+	}
+
+	/* set tef fifos to the number of tx fifos */
+	cpriv->fifos.tef.count = cpriv->fifos.tx.count;
+
+	/* compute size of the tx fifos and TEF */
+	tx_memory_used = cpriv->fifos.tx.count * cpriv->fifos.tx.size;
+	tef_memory_used = cpriv->fifos.tef.count * cpriv->fifos.tef.size;
+
+	/* calculate evailable memory for RX_fifos */
+	rx_memory_available = MCP25XXFD_SRAM_SIZE - tx_memory_used -
+		tef_memory_used;
+
+	/* we need at least one RX Frame */
+	if (rx_memory_available < cpriv->fifos.rx.size) {
+		netdev_err(cpriv->can.dev,
+			   "Configured %i tx-fifos exceeds available memory already\n",
+			   cpriv->fifos.tx.count);
+		return -EINVAL;
+	}
+
+	/* calculate possible amount of RX fifos */
+	cpriv->fifos.rx.count = rx_memory_available / cpriv->fifos.rx.size;
+
+	/* so now calculate effective number of rx-fifos
+	 * there are only 31 fifos available in total,
+	 * so we need to limit ourselves
+	 */
+	if (cpriv->fifos.rx.count + cpriv->fifos.tx.count > 31)
+		cpriv->fifos.rx.count = 31 - cpriv->fifos.tx.count;
+
+	/* define the layout now that we have gotten everything */
+	cpriv->fifos.tx.start = 1;
+	cpriv->fifos.rx.start = cpriv->fifos.tx.start + cpriv->fifos.tx.count;
+
+	return 0;
+}
+
+static int mcp25xxfd_can_fifo_clear_regs(struct mcp25xxfd_can_priv *cpriv,
+					 u32 start, u32 end)
+{
+	size_t len = end - start;
+	u8 *data = kzalloc(len, GFP_KERNEL);
+	int ret;
+
+	if (!data)
+		return -ENOMEM;
+
+	ret = mcp25xxfd_cmd_write_regs(cpriv->priv->spi,
+				       start, (u32 *)data, len);
+
+	kfree(data);
+
+	return ret;
+}
+
+static int mcp25xxfd_can_fifo_clear(struct mcp25xxfd_can_priv *cpriv)
+{
+	int ret;
+
+	memset(&cpriv->fifos.info, 0, sizeof(cpriv->fifos.info));
+	memset(&cpriv->fifos.tx, 0, sizeof(cpriv->fifos.tx));
+	memset(&cpriv->fifos.rx, 0, sizeof(cpriv->fifos.rx));
+
+	/* clear FIFO config */
+	ret = mcp25xxfd_can_fifo_clear_regs(cpriv, MCP25XXFD_CAN_FIFOCON(1),
+					    MCP25XXFD_CAN_FIFOCON(32));
+	if (ret)
+		return ret;
+
+	/* clear the filter mask - match any frame with every filter */
+	return mcp25xxfd_can_fifo_clear_regs(cpriv, MCP25XXFD_CAN_FLTCON(0),
+					     MCP25XXFD_CAN_FLTCON(32));
+}
+
+int mcp25xxfd_can_fifo_setup(struct mcp25xxfd_can_priv *cpriv)
+{
+	int ret;
+
+	/* clear fifo config */
+	ret = mcp25xxfd_can_fifo_clear(cpriv);
+	if (ret)
+		return ret;
+
+	/* compute fifos counts */
+	ret = mcp25xxfd_can_fifo_compute(cpriv);
+	if (ret)
+		return ret;
+
+	/* configure TEF */
+	if (cpriv->fifos.tef.count)
+		cpriv->regs.tefcon =
+			MCP25XXFD_CAN_TEFCON_FRESET |
+			MCP25XXFD_CAN_TEFCON_TEFNEIE |
+			MCP25XXFD_CAN_TEFCON_TEFTSEN |
+			((cpriv->fifos.tef.count - 1) <<
+			 MCP25XXFD_CAN_TEFCON_FSIZE_SHIFT);
+	else
+		cpriv->regs.tefcon = 0;
+	ret = mcp25xxfd_cmd_write(cpriv->priv->spi, MCP25XXFD_CAN_TEFCON,
+				  cpriv->regs.tefcon);
+	if (ret)
+		return ret;
+
+	/* TXQueue disabled */
+	ret = mcp25xxfd_cmd_write(cpriv->priv->spi, MCP25XXFD_CAN_TXQCON, 0);
+	if (ret)
+		return ret;
+
+	/* configure FIFOS themselves */
+	ret = mcp25xxfd_can_fifo_setup_tx(cpriv);
+	if (ret)
+		return ret;
+	ret = mcp25xxfd_can_fifo_setup_rx(cpriv);
+	if (ret)
+		return ret;
+	ret = mcp25xxfd_can_fifo_setup_rxfilter(cpriv);
+	if (ret)
+		return ret;
+
+	/* get fifo addresses */
+	ret = mcp25xxfd_can_fifo_get_address(cpriv);
+	if (ret)
+		return ret;
+
+	/* setup tx_fifo_queue */
+	ret = mcp25xxfd_can_tx_queue_alloc(cpriv);
+	if (ret)
+		return ret;
+
+	/* add the can info to debugfs */
+	mcp25xxfd_can_debugfs_setup(cpriv);
+
+	return 0;
+}
+
+void mcp25xxfd_can_fifo_release(struct mcp25xxfd_can_priv *cpriv)
+{
+	mcp25xxfd_can_tx_queue_free(cpriv);
+	mcp25xxfd_can_fifo_clear(cpriv);
+	mcp25xxfd_can_debugfs_remove(cpriv);
+}
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/mcp25xxfd/mcp25xxfd_can_fifo.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/mcp25xxfd/mcp25xxfd_can_fifo.h
new file mode 100644
index 0000000000000000000000000000000000000000..ed2daa05220a16020fe61d45ad56e553e6ee1c78
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/mcp25xxfd/mcp25xxfd_can_fifo.h
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+/* CAN bus driver for Microchip 25XXFD CAN Controller with SPI Interface
+ *
+ * Copyright 2019 Martin Sperl <kernel@martin.sperl.org>
+ */
+
+#ifndef __MCP25XXFD_CAN_FIFO_H
+#define __MCP25XXFD_CAN_FIFO_H
+
+#include "mcp25xxfd_can_priv.h"
+
+int mcp25xxfd_can_fifo_setup(struct mcp25xxfd_can_priv *cpriv);
+void mcp25xxfd_can_fifo_release(struct mcp25xxfd_can_priv *cpriv);
+
+#endif /* __MCP25XXFD_CAN_FIFO_H */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/mcp25xxfd/mcp25xxfd_can_id.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/mcp25xxfd/mcp25xxfd_can_id.h
new file mode 100644
index 0000000000000000000000000000000000000000..00a6c6639bd5d6cf6340fbb8c7ee98d60e78c3dd
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/mcp25xxfd/mcp25xxfd_can_id.h
@@ -0,0 +1,69 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+/* CAN bus driver for Microchip 25XXFD CAN Controller with SPI Interface
+ *
+ * Copyright 2019 Martin Sperl <kernel@martin.sperl.org>
+ */
+
+#ifndef __MCP25XXFD_CAN_IF_H
+#define __MCP25XXFD_CAN_IF_H
+
+#include <uapi/linux/can.h>
+
+#include "mcp25xxfd_can_id.h"
+#include "mcp25xxfd_regs.h"
+
+/* ideally these would be defined in uapi/linux/can.h */
+#define MCP25XXFD_CAN_EFF_SID_SHIFT	(CAN_EFF_ID_BITS - CAN_SFF_ID_BITS)
+#define MCP25XXFD_CAN_EFF_SID_BITS	CAN_SFF_ID_BITS
+#define MCP25XXFD_CAN_EFF_SID_MASK					\
+	GENMASK(MCP25XXFD_CAN_EFF_SID_SHIFT + MCP25XXFD_CAN_EFF_SID_BITS - 1, \
+		MCP25XXFD_CAN_EFF_SID_SHIFT)
+#define MCP25XXFD_CAN_EFF_EID_SHIFT	0
+#define MCP25XXFD_CAN_EFF_EID_BITS	MCP25XXFD_CAN_EFF_SID_SHIFT
+#define MCP25XXFD_CAN_EFF_EID_MASK					\
+	GENMASK(MCP25XXFD_CAN_EFF_EID_SHIFT + MCP25XXFD_CAN_EFF_EID_BITS - 1, \
+		MCP25XXFD_CAN_EFF_EID_SHIFT)
+
+static inline
+void mcp25xxfd_can_id_from_mcp25xxfd(u32 mcp_id, u32 mcp_flags, u32 *can_id)
+{
+	u32 sid = (mcp_id & MCP25XXFD_CAN_OBJ_ID_SID_MASK) >>
+		MCP25XXFD_CAN_OBJ_ID_SID_SHIFT;
+	u32 eid = (mcp_id & MCP25XXFD_CAN_OBJ_ID_EID_MASK) >>
+		MCP25XXFD_CAN_OBJ_ID_EID_SHIFT;
+
+	/* select normal or extended ids */
+	if (mcp_flags & MCP25XXFD_CAN_OBJ_FLAGS_IDE) {
+		*can_id = (eid << MCP25XXFD_CAN_EFF_EID_SHIFT) |
+			(sid << MCP25XXFD_CAN_EFF_SID_SHIFT) |
+			CAN_EFF_FLAG;
+	} else {
+		*can_id = sid << MCP25XXFD_CAN_EFF_EID_SHIFT;
+	}
+	/* handle rtr */
+	*can_id |= (mcp_flags & MCP25XXFD_CAN_OBJ_FLAGS_RTR) ? CAN_RTR_FLAG : 0;
+}
+
+static inline
+void mcp25xxfd_can_id_to_mcp25xxfd(u32 can_id, u32 *id, u32 *flags)
+{
+	/* depending on can_id flag compute extended or standard ids */
+	if (can_id & CAN_EFF_FLAG) {
+		int sid = (can_id & MCP25XXFD_CAN_EFF_SID_MASK) >>
+			MCP25XXFD_CAN_EFF_SID_SHIFT;
+		int eid = (can_id & MCP25XXFD_CAN_EFF_EID_MASK) >>
+			MCP25XXFD_CAN_EFF_EID_SHIFT;
+		*id = (eid << MCP25XXFD_CAN_OBJ_ID_EID_SHIFT) |
+			(sid << MCP25XXFD_CAN_OBJ_ID_SID_SHIFT);
+		*flags = MCP25XXFD_CAN_OBJ_FLAGS_IDE;
+	} else {
+		*id = can_id & CAN_SFF_MASK;
+		*flags = 0;
+	}
+
+	/* Handle RTR */
+	*flags |= (can_id & CAN_RTR_FLAG) ? MCP25XXFD_CAN_OBJ_FLAGS_RTR : 0;
+}
+
+#endif /* __MCP25XXFD_CAN_IF_H */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/mcp25xxfd/mcp25xxfd_can_int.c b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/mcp25xxfd/mcp25xxfd_can_int.c
new file mode 100644
index 0000000000000000000000000000000000000000..84f9c8273ce79c57ce91cd79dfbda0af7561c501
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/mcp25xxfd/mcp25xxfd_can_int.c
@@ -0,0 +1,705 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/* CAN bus driver for Microchip 25XXFD CAN Controller with SPI Interface
+ *
+ * Copyright 2019 Martin Sperl <kernel@martin.sperl.org>
+ */
+
+#include <linux/can/core.h>
+#include <linux/can/dev.h>
+#include <linux/device.h>
+#include <linux/interrupt.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/net.h>
+#include <linux/netdevice.h>
+#include <linux/sched.h>
+#include <linux/slab.h>
+#include <linux/sort.h>
+
+#include "mcp25xxfd_regs.h"
+#include "mcp25xxfd_can.h"
+#include "mcp25xxfd_can_debugfs.h"
+#include "mcp25xxfd_can_priv.h"
+#include "mcp25xxfd_can_rx.h"
+#include "mcp25xxfd_can_tx.h"
+#include "mcp25xxfd_cmd.h"
+#include "mcp25xxfd_ecc.h"
+
+unsigned int reschedule_int_thread_after = 4;
+module_param(reschedule_int_thread_after, uint, 0664);
+MODULE_PARM_DESC(reschedule_int_thread_after,
+		 "Reschedule the interrupt thread after this many loops\n");
+
+static void mcp25xxfd_can_int_send_error_skb(struct mcp25xxfd_can_priv *cpriv)
+{
+	struct net_device *net = cpriv->can.dev;
+	struct sk_buff *skb;
+	struct can_frame *frame;
+
+	/* allocate error frame */
+	skb = alloc_can_err_skb(net, &frame);
+	if (!skb) {
+		netdev_err(net, "cannot allocate error skb\n");
+		return;
+	}
+
+	/* setup can error frame data */
+	frame->can_id |= cpriv->error_frame.id;
+	memcpy(frame->data, cpriv->error_frame.data, sizeof(frame->data));
+
+	/* and submit it */
+	netif_receive_skb(skb);
+}
+
+static int mcp25xxfd_can_int_compare_obj_ts(const void *a, const void *b)
+{
+	s32 ats = ((struct mcp25xxfd_obj_ts *)a)->ts;
+	s32 bts = ((struct mcp25xxfd_obj_ts *)b)->ts;
+
+	if (ats < bts)
+		return -1;
+	if (ats > bts)
+		return 1;
+	return 0;
+}
+
+static int mcp25xxfd_can_int_submit_frames(struct mcp25xxfd_can_priv *cpriv)
+{
+	struct mcp25xxfd_obj_ts *queue = cpriv->fifos.submit_queue;
+	int count = cpriv->fifos.submit_queue_count;
+	int i, fifo;
+	int ret;
+
+	/* skip processing if the queue count is 0 */
+	if (count == 0)
+		goto out;
+
+	/* sort the fifos (rx and tx - actually TEF) by receive timestamp */
+	sort(queue, count, sizeof(*queue),
+	     mcp25xxfd_can_int_compare_obj_ts, NULL);
+
+	/* now submit the fifos  */
+	for (i = 0; i < count; i++) {
+		fifo = queue[i].fifo;
+		ret = (queue[i].is_rx) ?
+			mcp25xxfd_can_rx_submit_frame(cpriv, fifo) :
+			mcp25xxfd_can_tx_submit_frame(cpriv, fifo);
+		if (ret)
+			return ret;
+	}
+
+	/* if we have received or transmitted something
+	 * and the IVMIE is disabled, then enable it
+	 * this is mostly to avoid unnecessary interrupts during a
+	 * disconnected CAN BUS
+	 */
+	if (!(cpriv->status.intf | MCP25XXFD_CAN_INT_IVMIE)) {
+		cpriv->status.intf |= MCP25XXFD_CAN_INT_IVMIE;
+		ret = mcp25xxfd_cmd_write_mask(cpriv->priv->spi,
+					       MCP25XXFD_CAN_INT,
+					       cpriv->status.intf,
+					       MCP25XXFD_CAN_INT_IVMIE);
+		if (ret)
+			return ret;
+	}
+
+out:
+	/* enable tx_queue if necessary */
+	mcp25xxfd_can_tx_queue_restart(cpriv);
+
+	return 0;
+}
+
+static int mcp25xxfd_can_int_clear_int_flags(struct mcp25xxfd_can_priv *cpriv)
+{
+	u32 clearable_irq_active = cpriv->status.intf &
+		MCP25XXFD_CAN_INT_IF_CLEAR_MASK;
+	u32 clear_irq = cpriv->status.intf & (~MCP25XXFD_CAN_INT_IF_CLEAR_MASK);
+
+	/* if no clearable flags are set then skip the whole transfer */
+	if (!clearable_irq_active)
+		return 0;
+
+	return mcp25xxfd_cmd_write_mask(cpriv->priv->spi, MCP25XXFD_CAN_INT,
+					clear_irq, clearable_irq_active);
+}
+
+static
+int mcp25xxfd_can_int_handle_serrif_txmab(struct mcp25xxfd_can_priv *cpriv)
+{
+	int mode = mcp25xxfd_can_targetmode(cpriv);
+
+	cpriv->can.dev->stats.tx_fifo_errors++;
+	cpriv->can.dev->stats.tx_errors++;
+	MCP25XXFD_DEBUGFS_STATS_INCR(cpriv, int_serr_tx_count);
+
+	/* data7 contains custom mcp25xxfd error flags */
+	cpriv->error_frame.data[7] |= MCP25XXFD_CAN_ERR_DATA7_MCP25XXFD_SERR_TX;
+
+	/* and switch back into the correct mode */
+	return mcp25xxfd_can_switch_mode_no_wait(cpriv->priv,
+						 &cpriv->regs.con, mode);
+}
+
+static
+int mcp25xxfd_can_int_handle_serrif_rxmab(struct mcp25xxfd_can_priv *cpriv)
+{
+	cpriv->can.dev->stats.rx_dropped++;
+	cpriv->can.dev->stats.rx_errors++;
+	MCP25XXFD_DEBUGFS_STATS_INCR(cpriv, int_serr_rx_count);
+
+	/* data7 contains custom mcp25xxfd error flags */
+	cpriv->error_frame.data[7] |= MCP25XXFD_CAN_ERR_DATA7_MCP25XXFD_SERR_RX;
+
+	return 0;
+}
+
+static int mcp25xxfd_can_int_handle_serrif(struct mcp25xxfd_can_priv *cpriv)
+{
+	if (!(cpriv->status.intf & MCP25XXFD_CAN_INT_SERRIF))
+		return 0;
+
+	/* increment statistics counter now */
+	MCP25XXFD_DEBUGFS_STATS_INCR(cpriv, int_serr_count);
+
+	/* interrupt flags have been cleared already */
+
+	/* Errors here are:
+	 * * Bus Bandwidth Error: when a RX Message Assembly Buffer
+	 *   is still full when the next message has already arrived
+	 *   the recived message shall be ignored
+	 * * TX MAB Underflow: when a TX Message is invalid
+	 *   due to ECC errors or TXMAB underflow
+	 *   in this situatioon the system will transition to
+	 *   Restricted or Listen Only mode
+	 */
+
+	cpriv->error_frame.id |= CAN_ERR_CRTL;
+	cpriv->error_frame.data[1] |= CAN_ERR_CRTL_UNSPEC;
+
+	/* a mode change + invalid message would indicate
+	 * TX MAB Underflow
+	 */
+	if ((cpriv->status.intf & MCP25XXFD_CAN_INT_MODIF) &&
+	    (cpriv->status.intf & MCP25XXFD_CAN_INT_IVMIF)) {
+		return mcp25xxfd_can_int_handle_serrif_txmab(cpriv);
+	}
+
+	/* for RX there is only the RXIF an indicator
+	 * - surprizingly RX-MAB does not change mode or anything
+	 */
+	if (cpriv->status.intf & MCP25XXFD_CAN_INT_RXIF)
+		return mcp25xxfd_can_int_handle_serrif_rxmab(cpriv);
+
+	/* the final case */
+	dev_warn_ratelimited(&cpriv->priv->spi->dev,
+			     "unidentified system interrupt - intf =  %08x\n",
+			     cpriv->status.intf);
+
+	return 0;
+}
+
+static int mcp25xxfd_can_int_handle_modif(struct mcp25xxfd_can_priv *cpriv)
+{
+	struct spi_device *spi = cpriv->priv->spi;
+	int mode;
+	int ret;
+
+	/* Note that this irq does not get triggered in all situations
+	 * for example SERRIF will move to RESTICTED or LISTENONLY
+	 * but MODIF will not be raised!
+	 */
+
+	if (!(cpriv->status.intf & MCP25XXFD_CAN_INT_MODIF))
+		return 0;
+	MCP25XXFD_DEBUGFS_STATS_INCR(cpriv, int_mod_count);
+
+	/* get the current mode */
+	ret = mcp25xxfd_can_get_mode(cpriv->priv, &mode);
+	if (ret)
+		return ret;
+	mode = ret;
+
+	/* switches to the same mode as before are ignored
+	 * - this typically happens if the driver is shortly
+	 *   switching to a different mode and then returning to the
+	 *   original mode
+	 */
+	if (mode == cpriv->mode)
+		return 0;
+
+	/* if we are restricted, then return to "normal" mode */
+	if (mode == MCP25XXFD_CAN_CON_MODE_RESTRICTED) {
+		cpriv->mode = mode;
+		mode = mcp25xxfd_can_targetmode(cpriv);
+		return mcp25xxfd_can_switch_mode_no_wait(cpriv->priv,
+							 &cpriv->regs.con,
+							 mode);
+	}
+
+	/* the controller itself will transition to sleep, so we ignore it */
+	if (mode == MCP25XXFD_CAN_CON_MODE_SLEEP) {
+		cpriv->mode = mode;
+		return 0;
+	}
+
+	/* these we need to handle correctly, so warn and give context */
+	dev_warn(&spi->dev,
+		 "Controller unexpectedly switched from mode %u to %u\n",
+		 cpriv->mode, mode);
+
+	/* assign the mode as current */
+	cpriv->mode = mode;
+
+	return 0;
+}
+
+static int mcp25xxfd_can_int_handle_eccif(struct mcp25xxfd_can_priv *cpriv)
+{
+	if (!(cpriv->status.intf & MCP25XXFD_CAN_INT_ECCIF))
+		return 0;
+
+	MCP25XXFD_DEBUGFS_STATS_INCR(cpriv, int_ecc_count);
+
+	/* and prepare ERROR FRAME */
+	cpriv->error_frame.id |= CAN_ERR_CRTL;
+	cpriv->error_frame.data[1] |= CAN_ERR_CRTL_UNSPEC;
+	/* data7 contains custom mcp25xxfd error flags */
+	cpriv->error_frame.data[7] |= MCP25XXFD_CAN_ERR_DATA7_MCP25XXFD_ECC;
+
+	/* delegate to interrupt cleaning */
+	return mcp25xxfd_ecc_clear_int(cpriv->priv);
+}
+
+static void mcp25xxfd_can_int_handle_ivmif_tx(struct mcp25xxfd_can_priv *cpriv,
+					      u32 *mask)
+{
+	/* check if it is really a known tx error */
+	if ((cpriv->bus.bdiag[1] &
+	     (MCP25XXFD_CAN_BDIAG1_DBIT1ERR |
+	      MCP25XXFD_CAN_BDIAG1_DBIT0ERR |
+	      MCP25XXFD_CAN_BDIAG1_NACKERR |
+	      MCP25XXFD_CAN_BDIAG1_NBIT1ERR |
+	      MCP25XXFD_CAN_BDIAG1_NBIT0ERR
+		     )) == 0)
+		return;
+
+	/* mark it as a protocol error */
+	cpriv->error_frame.id |= CAN_ERR_PROT;
+
+	/* and update statistics */
+	cpriv->can.dev->stats.tx_errors++;
+
+	/* and handle all the known cases */
+	if (cpriv->bus.bdiag[1] & MCP25XXFD_CAN_BDIAG1_NACKERR) {
+		/* TX-Frame not acknowledged - connected to CAN-bus? */
+		*mask |= MCP25XXFD_CAN_BDIAG1_NACKERR;
+		cpriv->error_frame.data[2] |= CAN_ERR_PROT_TX;
+		cpriv->can.dev->stats.tx_aborted_errors++;
+	}
+	if (cpriv->bus.bdiag[1] & MCP25XXFD_CAN_BDIAG1_NBIT1ERR) {
+		/* TX-Frame CAN-BUS Level is unexpectedly dominant */
+		*mask |= MCP25XXFD_CAN_BDIAG1_NBIT1ERR;
+		cpriv->can.dev->stats.tx_carrier_errors++;
+		cpriv->error_frame.data[2] |= CAN_ERR_PROT_BIT1;
+	}
+	if (cpriv->bus.bdiag[1] & MCP25XXFD_CAN_BDIAG1_NBIT0ERR) {
+		/* TX-Frame CAN-BUS Level is unexpectedly recessive */
+		*mask |= MCP25XXFD_CAN_BDIAG1_NBIT0ERR;
+		cpriv->can.dev->stats.tx_carrier_errors++;
+		cpriv->error_frame.data[2] |= CAN_ERR_PROT_BIT0;
+	}
+	if (cpriv->bus.bdiag[1] & MCP25XXFD_CAN_BDIAG1_DBIT1ERR) {
+		/* TX-Frame CAN-BUS Level is unexpectedly dominant
+		 * during data phase
+		 */
+		*mask |= MCP25XXFD_CAN_BDIAG1_DBIT1ERR;
+		cpriv->can.dev->stats.tx_carrier_errors++;
+		cpriv->error_frame.data[2] |= CAN_ERR_PROT_BIT1;
+	}
+	if (cpriv->bus.bdiag[1] & MCP25XXFD_CAN_BDIAG1_DBIT0ERR) {
+		/* TX-Frame CAN-BUS Level is unexpectedly recessive
+		 * during data phase
+		 */
+		*mask |= MCP25XXFD_CAN_BDIAG1_DBIT0ERR;
+		cpriv->can.dev->stats.tx_carrier_errors++;
+		cpriv->error_frame.data[2] |= CAN_ERR_PROT_BIT0;
+	}
+}
+
+static void mcp25xxfd_can_int_handle_ivmif_rx(struct mcp25xxfd_can_priv *cpriv,
+					      u32 *mask)
+{
+	/* check if it is really a known tx error */
+	if ((cpriv->bus.bdiag[1] &
+	     (MCP25XXFD_CAN_BDIAG1_DCRCERR |
+	      MCP25XXFD_CAN_BDIAG1_DSTUFERR |
+	      MCP25XXFD_CAN_BDIAG1_DFORMERR |
+	      MCP25XXFD_CAN_BDIAG1_NCRCERR |
+	      MCP25XXFD_CAN_BDIAG1_NSTUFERR |
+	      MCP25XXFD_CAN_BDIAG1_NFORMERR
+		     )) == 0)
+		return;
+
+	/* mark it as a protocol error */
+	cpriv->error_frame.id |= CAN_ERR_PROT;
+
+	/* and update statistics */
+	cpriv->can.dev->stats.rx_errors++;
+
+	/* handle the cases */
+	if (cpriv->bus.bdiag[1] & MCP25XXFD_CAN_BDIAG1_DCRCERR) {
+		/* RX-Frame with bad CRC during data phase */
+		*mask |= MCP25XXFD_CAN_BDIAG1_DCRCERR;
+		cpriv->can.dev->stats.rx_crc_errors++;
+		cpriv->error_frame.data[3] |= CAN_ERR_PROT_LOC_CRC_SEQ;
+	}
+	if (cpriv->bus.bdiag[1] & MCP25XXFD_CAN_BDIAG1_DSTUFERR) {
+		/* RX-Frame with bad stuffing during data phase */
+		*mask |= MCP25XXFD_CAN_BDIAG1_DSTUFERR;
+		cpriv->can.dev->stats.rx_frame_errors++;
+		cpriv->error_frame.data[2] |= CAN_ERR_PROT_STUFF;
+	}
+	if (cpriv->bus.bdiag[1] & MCP25XXFD_CAN_BDIAG1_DFORMERR) {
+		/* RX-Frame with bad format during data phase */
+		*mask |= MCP25XXFD_CAN_BDIAG1_DFORMERR;
+		cpriv->can.dev->stats.rx_frame_errors++;
+		cpriv->error_frame.data[2] |= CAN_ERR_PROT_FORM;
+	}
+	if (cpriv->bus.bdiag[1] & MCP25XXFD_CAN_BDIAG1_NCRCERR) {
+		/* RX-Frame with bad CRC during data phase */
+		*mask |= MCP25XXFD_CAN_BDIAG1_NCRCERR;
+		cpriv->can.dev->stats.rx_crc_errors++;
+		cpriv->error_frame.data[3] |= CAN_ERR_PROT_LOC_CRC_SEQ;
+	}
+	if (cpriv->bus.bdiag[1] & MCP25XXFD_CAN_BDIAG1_NSTUFERR) {
+		/* RX-Frame with bad stuffing during data phase */
+		*mask |= MCP25XXFD_CAN_BDIAG1_NSTUFERR;
+		cpriv->can.dev->stats.rx_frame_errors++;
+		cpriv->error_frame.data[2] |= CAN_ERR_PROT_STUFF;
+	}
+	if (cpriv->bus.bdiag[1] & MCP25XXFD_CAN_BDIAG1_NFORMERR) {
+		/* RX-Frame with bad format during data phase */
+		*mask |= MCP25XXFD_CAN_BDIAG1_NFORMERR;
+		cpriv->can.dev->stats.rx_frame_errors++;
+		cpriv->error_frame.data[2] |= CAN_ERR_PROT_FORM;
+	}
+}
+
+static int mcp25xxfd_can_int_handle_ivmif(struct mcp25xxfd_can_priv *cpriv)
+{
+	struct spi_device *spi = cpriv->priv->spi;
+	u32 mask, bdiag1;
+	int ret;
+
+	if (!(cpriv->status.intf & MCP25XXFD_CAN_INT_IVMIF))
+		return 0;
+
+	MCP25XXFD_DEBUGFS_STATS_INCR(cpriv, int_ivm_count);
+
+	/* if we have a systemerror as well,
+	 * then ignore it as they correlate
+	 */
+	if (cpriv->status.intf & MCP25XXFD_CAN_INT_SERRIF)
+		return 0;
+
+	/* read bus diagnostics */
+	ret = mcp25xxfd_cmd_read_regs(spi, MCP25XXFD_CAN_BDIAG0,
+				      cpriv->bus.bdiag,
+				      sizeof(cpriv->bus.bdiag));
+	if (ret)
+		return ret;
+
+	/* clear the masks of bits to clear */
+	mask = 0;
+
+	/* check rx and tx errors */
+	mcp25xxfd_can_int_handle_ivmif_tx(cpriv, &mask);
+	mcp25xxfd_can_int_handle_ivmif_rx(cpriv, &mask);
+
+	/* clear flags if we have bits masked */
+	if (!mask) {
+		/* the unsupported case, where we are not
+		 * clearing any registers
+		 */
+		dev_warn_once(&spi->dev,
+			      "found IVMIF situation not supported by driver - bdiag = [0x%08x, 0x%08x]",
+			      cpriv->bus.bdiag[0], cpriv->bus.bdiag[1]);
+		return -EINVAL;
+	}
+
+	/* clear the bits in bdiag1 */
+	bdiag1 = cpriv->bus.bdiag[1] & (~mask);
+	/* and write it */
+	ret = mcp25xxfd_cmd_write_mask(spi, MCP25XXFD_CAN_BDIAG1, bdiag1, mask);
+	if (ret)
+		return ret;
+
+	/* and clear the interrupt flag until we have received or transmited */
+	cpriv->status.intf &= ~(MCP25XXFD_CAN_INT_IVMIE);
+	return mcp25xxfd_cmd_write_mask(spi, MCP25XXFD_CAN_INT,
+					cpriv->status.intf,
+					MCP25XXFD_CAN_INT_IVMIE);
+}
+
+static int mcp25xxfd_can_int_handle_cerrif(struct mcp25xxfd_can_priv *cpriv)
+{
+	if (!(cpriv->status.intf & MCP25XXFD_CAN_INT_CERRIF))
+		return 0;
+
+	/* this interrupt exists primarilly to counter possible
+	 * bus off situations more detailed information
+	 * can be found and controlled in the TREC register
+	 */
+
+	MCP25XXFD_DEBUGFS_STATS_INCR(cpriv, int_cerr_count);
+
+	netdev_warn(cpriv->can.dev, "CAN Bus error experienced");
+
+	return 0;
+}
+
+static int mcp25xxfd_can_int_error_counters(struct mcp25xxfd_can_priv *cpriv)
+{
+	if (cpriv->status.trec & MCP25XXFD_CAN_TREC_TXWARN) {
+		cpriv->bus.new_state = CAN_STATE_ERROR_WARNING;
+		cpriv->error_frame.id |= CAN_ERR_CRTL;
+		cpriv->error_frame.data[1] |= CAN_ERR_CRTL_TX_WARNING;
+	}
+	if (cpriv->status.trec & MCP25XXFD_CAN_TREC_RXWARN) {
+		cpriv->bus.new_state = CAN_STATE_ERROR_WARNING;
+		cpriv->error_frame.id |= CAN_ERR_CRTL;
+		cpriv->error_frame.data[1] |= CAN_ERR_CRTL_RX_WARNING;
+	}
+	if (cpriv->status.trec & MCP25XXFD_CAN_TREC_TXBP) {
+		cpriv->bus.new_state = CAN_STATE_ERROR_PASSIVE;
+		cpriv->error_frame.id |= CAN_ERR_CRTL;
+		cpriv->error_frame.data[1] |= CAN_ERR_CRTL_TX_PASSIVE;
+	}
+	if (cpriv->status.trec & MCP25XXFD_CAN_TREC_RXBP) {
+		cpriv->bus.new_state = CAN_STATE_ERROR_PASSIVE;
+		cpriv->error_frame.id |= CAN_ERR_CRTL;
+		cpriv->error_frame.data[1] |= CAN_ERR_CRTL_RX_PASSIVE;
+	}
+	if (cpriv->status.trec & MCP25XXFD_CAN_TREC_TXBO) {
+		cpriv->bus.new_state = CAN_STATE_BUS_OFF;
+		cpriv->error_frame.id |= CAN_ERR_BUSOFF;
+	}
+
+	return 0;
+}
+
+static int mcp25xxfd_can_int_error_handling(struct mcp25xxfd_can_priv *cpriv)
+{
+	/* based on the last state state check the new state */
+	switch (cpriv->can.state) {
+	case CAN_STATE_ERROR_ACTIVE:
+		if (cpriv->bus.new_state >= CAN_STATE_ERROR_WARNING &&
+		    cpriv->bus.new_state <= CAN_STATE_BUS_OFF)
+			cpriv->can.can_stats.error_warning++;
+		/* fallthrough */
+	case CAN_STATE_ERROR_WARNING:
+		if (cpriv->bus.new_state >= CAN_STATE_ERROR_PASSIVE &&
+		    cpriv->bus.new_state <= CAN_STATE_BUS_OFF)
+			cpriv->can.can_stats.error_passive++;
+		break;
+	default:
+		break;
+	}
+	cpriv->can.state = cpriv->bus.new_state;
+
+	/* and send error packet */
+	if (cpriv->error_frame.id)
+		mcp25xxfd_can_int_send_error_skb(cpriv);
+
+	/* handle BUS OFF */
+	if (cpriv->can.state == CAN_STATE_BUS_OFF) {
+		if (cpriv->can.restart_ms == 0) {
+			cpriv->can.can_stats.bus_off++;
+			can_bus_off(cpriv->can.dev);
+		}
+	} else {
+		/* restart the tx queue if needed */
+		mcp25xxfd_can_tx_queue_restart(cpriv);
+	}
+
+	return 0;
+}
+
+static int mcp25xxfd_can_int_handle_status(struct mcp25xxfd_can_priv *cpriv)
+{
+	int ret;
+
+	/* clear all the interrupts asap - we have them on file allready */
+	ret = mcp25xxfd_can_int_clear_int_flags(cpriv);
+	if (ret)
+		return ret;
+
+	/* set up new state and error frame for this loop */
+	cpriv->bus.new_state = cpriv->bus.state;
+	memset(&cpriv->error_frame, 0, sizeof(cpriv->error_frame));
+
+	/* setup the process queue by clearing the counter */
+	cpriv->fifos.submit_queue_count = 0;
+
+	/* handle interrupts */
+
+	/* system error interrupt needs to get handled first
+	 * to get us out of restricted mode
+	 */
+	ret = mcp25xxfd_can_int_handle_serrif(cpriv);
+	if (ret)
+		return ret;
+
+	/* mode change interrupt */
+	ret = mcp25xxfd_can_int_handle_modif(cpriv);
+	if (ret)
+		return ret;
+
+	/* handle the rx */
+	ret = mcp25xxfd_can_rx_handle_int_rxif(cpriv);
+	if (ret)
+		return ret;
+	/* handle aborted TX FIFOs */
+	ret = mcp25xxfd_can_tx_handle_int_txatif(cpriv);
+	if (ret)
+		return ret;
+
+	/* handle the TEF */
+	ret = mcp25xxfd_can_tx_handle_int_tefif(cpriv);
+	if (ret)
+		return ret;
+
+	/* handle error interrupt flags */
+	ret = mcp25xxfd_can_rx_handle_int_rxovif(cpriv);
+	if (ret)
+		return ret;
+
+	/* sram ECC error interrupt */
+	ret = mcp25xxfd_can_int_handle_eccif(cpriv);
+	if (ret)
+		return ret;
+
+	/* message format interrupt */
+	ret = mcp25xxfd_can_int_handle_ivmif(cpriv);
+	if (ret)
+		return ret;
+
+	/* handle bus errors in more detail */
+	ret = mcp25xxfd_can_int_handle_cerrif(cpriv);
+	if (ret)
+		return ret;
+
+	/* error counter handling */
+	ret = mcp25xxfd_can_int_error_counters(cpriv);
+	if (ret)
+		return ret;
+
+	/* error counter handling */
+	ret = mcp25xxfd_can_int_error_handling(cpriv);
+	if (ret)
+		return ret;
+
+	/* and submit can frames to network stack */
+	ret = mcp25xxfd_can_int_submit_frames(cpriv);
+
+	return ret;
+}
+
+irqreturn_t mcp25xxfd_can_int(int irq, void *dev_id)
+{
+	struct mcp25xxfd_can_priv *cpriv = dev_id;
+	int loops, ret;
+
+	/* count interrupt calls */
+	MCP25XXFD_DEBUGFS_STATS_INCR(cpriv, irq_calls);
+
+	/* loop forever unless we need to exit */
+	for (loops = 0; true; loops++) {
+		/* count irq loops */
+		MCP25XXFD_DEBUGFS_STATS_INCR(cpriv, irq_loops);
+
+		/* read interrupt status flags in bulk */
+		ret = mcp25xxfd_cmd_read_regs(cpriv->priv->spi,
+					      MCP25XXFD_CAN_INT,
+					      &cpriv->status.intf,
+					      sizeof(cpriv->status));
+		if (ret)
+			return ret;
+
+		/* only act if the IE mask configured has active IF bits
+		 * otherwise the Interrupt line should be deasserted already
+		 * so we can exit the loop
+		 */
+		if (((cpriv->status.intf >> MCP25XXFD_CAN_INT_IE_SHIFT) &
+		       cpriv->status.intf) == 0)
+			break;
+
+		/* handle the status */
+		ret = mcp25xxfd_can_int_handle_status(cpriv);
+		if (ret)
+			return ret;
+
+		/* allow voluntarily rescheduling every so often to avoid
+		 * long CS lows at the end of a transfer on low power CPUs
+		 * avoiding SERR happening
+		 */
+		if (loops % reschedule_int_thread_after == 0) {
+			MCP25XXFD_DEBUGFS_STATS_INCR(cpriv,
+						     irq_thread_rescheduled);
+			cond_resched();
+		}
+	}
+
+	return IRQ_HANDLED;
+}
+
+int mcp25xxfd_can_int_clear(struct mcp25xxfd_priv *priv)
+{
+	return mcp25xxfd_cmd_write_mask(priv->spi, MCP25XXFD_CAN_INT, 0,
+					MCP25XXFD_CAN_INT_IF_MASK);
+}
+
+int mcp25xxfd_can_int_enable(struct mcp25xxfd_priv *priv, bool enable)
+{
+	struct mcp25xxfd_can_priv *cpriv = priv->cpriv;
+	const u32 mask = MCP25XXFD_CAN_INT_TEFIE |
+		MCP25XXFD_CAN_INT_RXIE |
+		MCP25XXFD_CAN_INT_MODIE |
+		MCP25XXFD_CAN_INT_SERRIE |
+		MCP25XXFD_CAN_INT_IVMIE |
+		MCP25XXFD_CAN_INT_CERRIE |
+		MCP25XXFD_CAN_INT_RXOVIE |
+		MCP25XXFD_CAN_INT_ECCIE;
+	u32 value = cpriv ? cpriv->status.intf : 0;
+	int ret;
+
+	/* apply mask and */
+	value &= ~(MCP25XXFD_CAN_INT_IE_MASK);
+	if (enable)
+		value |= mask;
+
+	/* and write to int register */
+	ret = mcp25xxfd_cmd_write_mask(priv->spi, MCP25XXFD_CAN_INT,
+				       value, mask);
+	if (ret)
+		return ret;
+	if (!cpriv)
+		return 0;
+
+	cpriv->status.intf = value;
+
+	/* enable/disable interrupt handler */
+	if (cpriv->irq.allocated) {
+		if (enable && !cpriv->irq.enabled)
+			enable_irq(cpriv->priv->spi->irq);
+		if (!enable && cpriv->irq.enabled)
+			disable_irq(cpriv->priv->spi->irq);
+		cpriv->irq.enabled = enable;
+	} else {
+		cpriv->irq.enabled = false;
+	}
+
+	return 0;
+}
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/mcp25xxfd/mcp25xxfd_can_int.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/mcp25xxfd/mcp25xxfd_can_int.h
new file mode 100644
index 0000000000000000000000000000000000000000..cc2ad992c307ba8b3badadfc9beea1ef33ce60b4
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/mcp25xxfd/mcp25xxfd_can_int.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+/* CAN bus driver for Microchip 25XXFD CAN Controller with SPI Interface
+ *
+ * Copyright 2019 Martin Sperl <kernel@martin.sperl.org>
+ */
+#ifndef __MCP25XXFD_CAN_INT_H
+#define __MCP25XXFD_CAN_INT_H
+
+#include "mcp25xxfd_priv.h"
+
+int mcp25xxfd_can_int_clear(struct mcp25xxfd_priv *priv);
+int mcp25xxfd_can_int_enable(struct mcp25xxfd_priv *priv, bool enable);
+
+irqreturn_t mcp25xxfd_can_int(int irq, void *dev_id);
+
+#endif /* __MCP25XXFD_CAN_INT_H */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/mcp25xxfd/mcp25xxfd_can_priv.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/mcp25xxfd/mcp25xxfd_can_priv.h
new file mode 100644
index 0000000000000000000000000000000000000000..eeb9c88c7e97d848f0594587d743e16cc30ed1f8
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/mcp25xxfd/mcp25xxfd_can_priv.h
@@ -0,0 +1,203 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+/* CAN bus driver for Microchip 25XXFD CAN Controller with SPI Interface
+ *
+ * Copyright 2019 Martin Sperl <kernel@martin.sperl.org>
+ */
+
+#ifndef __MCP25XXFD_CAN_PRIV_H
+#define __MCP25XXFD_CAN_PRIV_H
+
+#include <linux/can/dev.h>
+#include <linux/dcache.h>
+
+#include "mcp25xxfd_priv.h"
+
+#define TX_ECHO_SKB_MAX	32
+
+/* information on each fifo type */
+struct mcp25xxfd_fifo {
+	u32 count;
+	u32 start;
+	u32 size;
+#ifdef CONFIG_DEBUG_FS
+	u64 dlc_usage[16];
+	u64 fd_count;
+#endif /* CONFIG_DEBUG_FS */
+};
+
+/* used for sorting incoming messages */
+struct mcp25xxfd_obj_ts {
+	s32 ts; /* using signed to handle rollover correctly when sorting */
+	u16 fifo;
+	s16 is_rx;
+};
+
+/* general info on each fifo */
+struct mcp25xxfd_fifo_info {
+	u32 is_rx;
+	u32 offset;
+	u32 priority;
+#ifdef CONFIG_DEBUG_FS
+	u64 use_count;
+#endif /* CONFIG_DEBUG_FS */
+};
+
+struct mcp25xxfd_can_priv {
+	/* can_priv has to be the first one to be usable with alloc_candev
+	 * which expects struct can_priv to be right at the start of the
+	 * priv structure
+	 */
+	struct can_priv can;
+	struct mcp25xxfd_priv *priv;
+	struct regulator *transceiver;
+
+	/* the can mode currently active */
+	int mode;
+
+	/* interrupt state */
+	struct {
+		int enabled;
+		int allocated;
+	} irq;
+
+	/* can config registers */
+	struct {
+		u32 con;
+		u32 tdc;
+		u32 tscon;
+		u32 tefcon;
+		u32 nbtcfg;
+		u32 dbtcfg;
+	} regs;
+
+	/* can status registers (mostly) - read in one go
+	 * bdiag0 and bdiag1 are optional, but when
+	 * berr counters are requested on a regular basis
+	 * during high CAN-bus load this would trigger the fact
+	 * that spi_sync would get queued for execution in the
+	 * spi thread and the spi handler would not get
+	 * called inline in the interrupt thread without any
+	 * context switches or wakeups...
+	 */
+	struct {
+		u32 intf;
+		/* ASSERT(CAN_INT + 4 == CAN_RXIF) */
+		u32 rxif;
+		/* ASSERT(CAN_RXIF + 4 == CAN_TXIF) */
+		u32 txif;
+		/* ASSERT(CAN_TXIF + 4 == CAN_RXOVIF) */
+		u32 rxovif;
+		/* ASSERT(CAN_RXOVIF + 4 == CAN_TXATIF) */
+		u32 txatif;
+		/* ASSERT(CAN_TXATIF + 4 == CAN_TXREQ) */
+		u32 txreq;
+		/* ASSERT(CAN_TXREQ + 4 == CAN_TREC) */
+		u32 trec;
+	} status;
+
+	/* information of fifo setup */
+	struct {
+		/* define payload size and mode */
+		u32 payload_size;
+		u32 payload_mode;
+
+		/* infos on fifo layout */
+
+		/* TEF */
+		struct {
+			u32 count;
+			u32 size;
+			u32 index;
+		} tef;
+
+		/* info on each fifo */
+		struct mcp25xxfd_fifo_info info[32];
+
+		/* extra info on rx/tx fifo groups */
+		struct mcp25xxfd_fifo tx;
+		struct mcp25xxfd_fifo rx;
+
+		/* queue of can frames that need to get submitted
+		 * to the network stack during an interrupt loop in one go
+		 * (this gets sorted by timestamp before submission
+		 * and contains both rx frames as well tx frames that have
+		 * gone over the CAN bus successfully
+		 */
+		struct mcp25xxfd_obj_ts submit_queue[32];
+		int  submit_queue_count;
+
+		/* the tx queue of spi messages */
+		struct mcp25xxfd_tx_spi_message_queue *tx_queue;
+	} fifos;
+
+	/* statistics exposed via debugfs */
+#ifdef CONFIG_DEBUG_FS
+	struct dentry *debugfs_dir;
+
+	struct {
+		u64 irq_calls;
+		u64 irq_loops;
+		u64 irq_thread_rescheduled;
+
+		u64 int_serr_count;
+		u64 int_serr_rx_count;
+		u64 int_serr_tx_count;
+		u64 int_mod_count;
+		u64 int_rx_count;
+		u64 int_txat_count;
+		u64 int_tef_count;
+		u64 int_rxov_count;
+		u64 int_ecc_count;
+		u64 int_ivm_count;
+		u64 int_cerr_count;
+
+		u64 tx_fd_count;
+		u64 tx_brs_count;
+
+		u64 tef_reads;
+		u64 tef_read_splits;
+		u64 tef_conservative_reads;
+		u64 tef_optimized_reads;
+#define MCP25XXFD_CAN_TEF_READ_BINS 8
+		u64 tef_optimized_read_sizes[MCP25XXFD_CAN_TEF_READ_BINS];
+
+		u64 rx_reads;
+		u64 rx_reads_prefetched_too_few;
+		u64 rx_reads_prefetched_too_few_bytes;
+		u64 rx_reads_prefetched_too_many;
+		u64 rx_reads_prefetched_too_many_bytes;
+		u64 rx_single_reads;
+		u64 rx_bulk_reads;
+#define MCP25XXFD_CAN_RX_BULK_READ_BINS 8
+		u64 rx_bulk_read_sizes[MCP25XXFD_CAN_RX_BULK_READ_BINS];
+	} stats;
+#endif /* CONFIG_DEBUG_FS */
+
+	/* history of rx-dlc */
+	struct {
+#define MCP25XXFD_CAN_RX_DLC_HISTORY_SIZE 32
+		u8 dlc[MCP25XXFD_CAN_RX_DLC_HISTORY_SIZE];
+		u8 brs[MCP25XXFD_CAN_RX_DLC_HISTORY_SIZE];
+		u8 index;
+		u32 predicted_len;
+	} rx_history;
+
+	/* bus state */
+	struct {
+		u32 state;
+		u32 new_state;
+		u32 bdiag[2];
+	} bus;
+
+	/* can error messages */
+	struct {
+		u32 id;
+		u8  data[8];
+	} error_frame;
+
+	/* a copy of mcp25xxfd-sram in ram */
+	u8 sram[MCP25XXFD_SRAM_SIZE];
+};
+
+#endif /* __MCP25XXFD_CAN_PRIV_H */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/mcp25xxfd/mcp25xxfd_can_rx.c b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/mcp25xxfd/mcp25xxfd_can_rx.c
new file mode 100644
index 0000000000000000000000000000000000000000..55d027cd30496fb1cc3abd9495f1cecea57f50b1
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/mcp25xxfd/mcp25xxfd_can_rx.c
@@ -0,0 +1,521 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/* CAN bus driver for Microchip 25XXFD CAN Controller with SPI Interface
+ *
+ * Copyright 2019 Martin Sperl <kernel@martin.sperl.org>
+ *
+ * Based on Microchip MCP251x CAN controller driver written by
+ * David Vrabel, Copyright 2006 Arcom Control Systems Ltd.
+ */
+
+#include <linux/can/core.h>
+#include <linux/can/dev.h>
+#include <linux/device.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/netdevice.h>
+#include <linux/skbuff.h>
+#include <linux/slab.h>
+#include <linux/spi/spi.h>
+
+#include "mcp25xxfd_cmd.h"
+#include "mcp25xxfd_can.h"
+#include "mcp25xxfd_can_debugfs.h"
+#include "mcp25xxfd_can_id.h"
+#include "mcp25xxfd_can_priv.h"
+#include "mcp25xxfd_can_rx.h"
+
+/* module parameters */
+unsigned int rx_prefetch_bytes = -1;
+module_param(rx_prefetch_bytes, uint, 0664);
+MODULE_PARM_DESC(rx_prefetch_bytes,
+		 "number of bytes to blindly prefetch when reading a rx-fifo");
+
+static struct sk_buff *
+mcp25xxfd_can_rx_submit_normal_frame(struct mcp25xxfd_can_priv *cpriv,
+				     u32 id, u32 dlc, u8 **data)
+{
+	struct can_frame *frame;
+	struct sk_buff *skb;
+
+	/* allocate frame */
+	skb = alloc_can_skb(cpriv->can.dev, &frame);
+	if (!skb)
+		return NULL;
+
+	/* set id, dlc and flags */
+	frame->can_id = id;
+	frame->can_dlc = dlc;
+
+	/* and set the pointer to data */
+	*data = frame->data;
+
+	return skb;
+}
+
+/* it is almost identical except for the type of the frame... */
+static struct sk_buff *
+mcp25xxfd_can_rx_submit_fd_frame(struct mcp25xxfd_can_priv *cpriv,
+				 u32 id, u32 flags, u32 len, u8 **data)
+{
+	struct canfd_frame *frame;
+	struct sk_buff *skb;
+
+	/* allocate frame */
+	skb = alloc_canfd_skb(cpriv->can.dev, &frame);
+	if (!skb)
+		return NULL;
+
+	/* set id, dlc and flags */
+	frame->can_id = id;
+	frame->len = len;
+	frame->flags |= flags;
+
+	/* and set the pointer to data */
+	*data = frame->data;
+
+	return skb;
+}
+
+int mcp25xxfd_can_rx_submit_frame(struct mcp25xxfd_can_priv *cpriv, int fifo)
+{
+	struct net_device *net = cpriv->can.dev;
+	int addr = cpriv->fifos.info[fifo].offset;
+	struct mcp25xxfd_can_obj_rx *rx =
+		(struct mcp25xxfd_can_obj_rx *)(cpriv->sram + addr);
+	u8 *data = NULL;
+	struct sk_buff *skb;
+	u32 id, dlc, len, flags;
+
+	/* compute the can_id */
+	mcp25xxfd_can_id_from_mcp25xxfd(rx->id, rx->flags, &id);
+
+	/* and dlc */
+	dlc = (rx->flags & MCP25XXFD_CAN_OBJ_FLAGS_DLC_MASK) >>
+		MCP25XXFD_CAN_OBJ_FLAGS_DLC_SHIFT;
+	len = can_dlc2len(dlc);
+
+	/* update stats */
+	net->stats.rx_packets++;
+	net->stats.rx_bytes += len;
+	cpriv->fifos.rx.dlc_usage[dlc]++;
+	if (rx->flags & MCP25XXFD_CAN_OBJ_FLAGS_FDF)
+		MCP25XXFD_DEBUGFS_INCR(cpriv->fifos.rx.fd_count);
+
+	/* add to rx_history */
+	cpriv->rx_history.dlc[cpriv->rx_history.index] = dlc;
+	cpriv->rx_history.brs[cpriv->rx_history.index] =
+		(rx->flags & MCP25XXFD_CAN_OBJ_FLAGS_BRS) ? CANFD_BRS : 0;
+	cpriv->rx_history.index++;
+	if (cpriv->rx_history.index >= MCP25XXFD_CAN_RX_DLC_HISTORY_SIZE)
+		cpriv->rx_history.index = 0;
+
+	/* allocate the skb buffer */
+	if (rx->flags & MCP25XXFD_CAN_OBJ_FLAGS_FDF) {
+		flags = 0;
+		flags |= (rx->flags & MCP25XXFD_CAN_OBJ_FLAGS_BRS) ?
+			CANFD_BRS : 0;
+		flags |= (rx->flags & MCP25XXFD_CAN_OBJ_FLAGS_ESI) ?
+			CANFD_ESI : 0;
+		skb = mcp25xxfd_can_rx_submit_fd_frame(cpriv, id, flags,
+						       len, &data);
+	} else {
+		skb = mcp25xxfd_can_rx_submit_normal_frame(cpriv, id,
+							   len, &data);
+	}
+	if (!skb) {
+		netdev_err(net, "cannot allocate RX skb\n");
+		net->stats.rx_dropped++;
+		return -ENOMEM;
+	}
+
+	/* copy the payload data */
+	memcpy(data, rx->data, len);
+
+	/* and submit the frame */
+	netif_rx_ni(skb);
+
+	return 0;
+}
+
+static int mcp25xxfd_can_rx_read_frame(struct mcp25xxfd_can_priv *cpriv,
+				       int fifo, int prefetch_bytes, bool read)
+{
+	struct spi_device *spi = cpriv->priv->spi;
+	struct net_device *net = cpriv->can.dev;
+	int addr = cpriv->fifos.info[fifo].offset;
+	struct mcp25xxfd_can_obj_rx *rx =
+		(struct mcp25xxfd_can_obj_rx *)(cpriv->sram + addr);
+	int dlc;
+	int len, ret;
+
+	/* we read the header plus prefetch_bytes */
+	if (read) {
+		cpriv->stats.rx_single_reads++;
+		ret = mcp25xxfd_cmd_readn(spi, MCP25XXFD_SRAM_ADDR(addr),
+					  rx, sizeof(*rx) + prefetch_bytes);
+		if (ret)
+			return ret;
+	}
+
+	/* transpose the headers to CPU format*/
+	rx->id = le32_to_cpu(rx->id);
+	rx->flags = le32_to_cpu(rx->flags);
+	rx->ts = le32_to_cpu(rx->ts);
+
+	/* compute len */
+	dlc = (rx->flags & MCP25XXFD_CAN_OBJ_FLAGS_DLC_MASK) >>
+		MCP25XXFD_CAN_OBJ_FLAGS_DLC_SHIFT;
+	len = can_dlc2len(min_t(int, dlc, (net->mtu == CANFD_MTU) ? 15 : 8));
+
+	/* read the remaining data for canfd frames */
+	if (read && len > prefetch_bytes) {
+		/* update stats */
+		MCP25XXFD_DEBUGFS_STATS_INCR(cpriv,
+					     rx_reads_prefetched_too_few);
+		MCP25XXFD_DEBUGFS_STATS_ADD(cpriv,
+					    rx_reads_prefetched_too_few_bytes,
+					    len - prefetch_bytes);
+		/* here the extra portion reading data after prefetch */
+		ret = mcp25xxfd_cmd_readn(spi,
+					  MCP25XXFD_SRAM_ADDR(addr) +
+					  sizeof(*rx) + prefetch_bytes,
+					  &rx->data[prefetch_bytes],
+					  len - prefetch_bytes);
+		if (ret)
+			return ret;
+	}
+
+	/* update stats */
+	cpriv->stats.rx_reads++;
+	if (len < prefetch_bytes) {
+		MCP25XXFD_DEBUGFS_STATS_INCR(cpriv,
+					     rx_reads_prefetched_too_many);
+		MCP25XXFD_DEBUGFS_STATS_ADD(cpriv,
+					    rx_reads_prefetched_too_many,
+					    prefetch_bytes - len);
+	}
+
+	/* clear the rest of the buffer - just to be safe */
+	memset(rx->data + len, 0, ((net->mtu == CANFD_MTU) ? 64 : 8) - len);
+
+	/* increment the statistics counter */
+	MCP25XXFD_DEBUGFS_INCR(cpriv->fifos.info[fifo].use_count);
+
+	/* add the fifo to the process queues */
+	mcp25xxfd_can_queue_frame(cpriv, fifo, rx->ts, true);
+
+	/* and clear the interrupt flag for that fifo */
+	return mcp25xxfd_cmd_write_mask(spi, MCP25XXFD_CAN_FIFOCON(fifo),
+					MCP25XXFD_CAN_FIFOCON_FRESET,
+					MCP25XXFD_CAN_FIFOCON_FRESET);
+}
+
+static int mcp25xxfd_can_read_rx_frame_bulk(struct mcp25xxfd_can_priv *cpriv,
+					    int fstart,
+					    int fend)
+{
+	struct net_device *net = cpriv->can.dev;
+	int count = abs(fend - fstart) + 1;
+	int flowest = min_t(int, fstart, fend);
+	int addr = cpriv->fifos.info[flowest].offset;
+	struct mcp25xxfd_can_obj_rx *rx =
+		(struct mcp25xxfd_can_obj_rx *)(cpriv->sram + addr);
+	int len = (sizeof(*rx) + ((net->mtu == CANFD_MTU) ? 64 : 8)) * count;
+	int fifo, i, ret;
+
+	/* update stats */
+	MCP25XXFD_DEBUGFS_STATS_INCR(cpriv, rx_bulk_reads);
+	i = min_t(int, MCP25XXFD_CAN_RX_BULK_READ_BINS - 1, count - 1);
+	MCP25XXFD_DEBUGFS_STATS_INCR(cpriv, rx_bulk_read_sizes[i]);
+
+	/* we read the header plus read_min data bytes */
+	ret = mcp25xxfd_cmd_readn(cpriv->priv->spi, MCP25XXFD_SRAM_ADDR(addr),
+				  rx, len);
+	if (ret)
+		return ret;
+
+	/* now process all of them - no need to read... */
+	for (fifo = fstart; count > 0; fifo ++, count--) {
+		ret = mcp25xxfd_can_rx_read_frame(cpriv, fifo, 8, false);
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+}
+
+/* predict dlc size based on historic behaviour */
+static int mcp25xxfd_can_rx_predict_prefetch(struct mcp25xxfd_can_priv *cpriv)
+{
+	int dlc, i, top;
+	u8 histo[16];
+
+	/* if we have a prfecth set then use that one */
+	if (rx_prefetch_bytes != -1)
+		return min_t(int, rx_prefetch_bytes,
+			     (cpriv->can.dev->mtu == CANFD_MTU) ? 64 : 8);
+
+	/* memset */
+	memset(histo, 0, sizeof(histo));
+
+	/* for all others compute the histogram */
+	for (i = 0; i < MCP25XXFD_CAN_RX_DLC_HISTORY_SIZE; i++)
+		histo[cpriv->rx_history.dlc[i]]++;
+
+	/* and now find the highest fit */
+	for (i = (cpriv->can.dev->mtu == CANFD_MTU) ? 15 : 8, dlc = 8, top = 0;
+	      i >= 0; i--) {
+		if (top < histo[i]) {
+			top = histo[i];
+			dlc = i;
+		}
+	}
+
+	/* compute length from dlc */
+	cpriv->rx_history.predicted_len = can_dlc2len(dlc);
+
+	/* return the predicted length */
+	return cpriv->rx_history.predicted_len;
+}
+
+/* at least in can2.0 mode we can read multiple RX-fifos in one go
+ * in case they are ajactent to each other and thus we can reduce
+ * the number of spi messages produced and this improves spi-bus
+ * usage efficiency.
+ * In canFD mode this may also be possible, but would need some
+ * statistics to decide if it is worth reading a full 64 bytes
+ * in one go.
+ * But those statistics can get used to predict how many bytes
+ * to read together with the can header (which is fixed to 8 at
+ * this very moment.
+ *
+ * notes on the rational here:
+ * * Reading just the CAN header info takes:
+ *   * bytes read
+ *     *  2 bytes command+address
+ *     * 12 bytes data (id, flags, timestamp)
+ *   * so that is at the very least 112 SCK (= 14 byte * 8 SCK/1 byte)
+ *     - on a Raspberry pi 3 for such short requests actually
+ *       126 SCK (=14 byte * 9 SCK/1 byte)
+ *   * some SPI framework overhead which is observed to be 5-10 us
+ *     on a raspberry pi 3 (time between SCK and stop SCK start)
+ *   * with an effective 17.85 MHz SPI clock on a RPI it takes in total:
+ *     it takes 12us = 6us + 6us
+ * * now reading 8 bytes of CAN data (can2.0) takes:
+ *   * bytes read
+ *     *  2 bytes command+address
+ *     *  8 bytes data
+ *   * so that is at the very least 80 SCK (= 10 byte * 8 SCK/1 byte)
+ *     - on a Raspberry pi 3 for such short requests actually
+ *       90 SCK (= 10 byte * 9 SCK/1 byte)
+ *   * some SPI framework overhead which is observed to be 5-10 us
+ *     on a raspberry pi 3 (time between SCK and stop SCK start)
+ *   * with an effective 17.85 MHz SPI clock on a RPI it takes in total:
+ *     it takes 11us = 5.0us + 6us
+ * * now reading CAN header plus 8 bytes of CAN data (can2.0) takes:
+ *   * bytes read
+ *     *  2 bytes command+address
+ *     * 20 bytes data
+ *   * so that is at the very least 176 SCK (= 22 byte * 8 SCK/1 byte)
+ *     - on a Raspberry pi 3 for such short requests actually
+ *       198 SCK (= 22 byte * 9 SCK/1 byte)
+ *   * some SPI framework overhead which is observed to be 5-10 us
+ *     on a raspberry pi 3 (time between SCK and stop SCK start)
+ *   * with an effective 17.85 MHz SPI clock on a RPI it takes in total:
+ *     it takes 17.1us = 11.1us + 6us
+ *   * this is faster than the 2 individual SPI transfers for header
+ *     and data which is in total 23us
+ *     * this is even true for the case where we only have a single
+ *       data byte (DLC=1) - the time here is 19.5us on a RPI3
+ *     * the only time where we are less efficient is for the DLC=0 case.
+ *       but the assumption here is that this is a rare case
+ * To put it into perspective here the full table for a RPI3:
+ * LE 2m  pr0 pr1 pr2 pr3 pr4 pr5  pr6  pr7  pr8 pr12 pr16 pr20 pr24 pr32 pr48
+ *                                                                         pr64
+ *  0  7.1 7.1
+ *  1 14.6    7.6 8.1 8.6 9.1 9.6 10.1 10.6 11.1 13.1
+ *  2 15.1        8.1 8.6 9.1 9.6 10.1 10.6 11.1 13.1
+ *  3 15.6            8.6 9.1 9.6 10.1 10.6 11.1 13.1 15.1
+ *  4 16.1                9.1 9.6 10.1 10.6 11.1 13.1 15.1
+ *  5 16.6                    9.6 10.1 10.6 11.1 13.1 15.1
+ *  6 17.1                        10.1 10.6 11.1 13.1 15.1
+ *  7 17.6                             10.6 11.1 13.1 15.1 17.1
+ *  8 18.1                                  11.1 13.1 15.1 17.1
+ * 12 20.1                                       13.1 15.1 17.1 19.2
+ * 16 22.1                                            15.1 17.1 19.2
+ * 20 24.1                                                 17.1 19.2 23.2
+ * 24 26.2                                                      19.2 23.2
+ * 32 30.2                                                           23.2
+ * 48 38.3                                                                31.3
+ * 64 46.3                                                                 39.3
+ * (Parameters: SPI Clock=17.8MHz, SCK/byte=9, overhead=6us)
+ * Legend:
+ *   LE = length,
+ *   2m    = 2 SPI messages (header+data - except for LEN=0, only header)
+ *  prX/pX = prefecth length times (only shown when < 2m and Len >= Prefetch)
+ *
+ * The diagonal schows the "optimal" time when the size of the Can frame would
+ * be known ahead of time - i.e if it would be possible to define RX reception
+ * filters based on can DLC values
+ *
+ * So for any Can frame except for LEN=0 the prefetch data solution is
+ * better for prefetch of data=12 for CanFD.
+ *
+ * Here another table showing the optimal prefetch limits for SPI speeds
+ * vs overhead_us at 8 or 9 SCLK/byte
+ *
+ * MHZ  2us@8   2us@9   4us@8   4us@9   6us@8   6us@9   8us@8   8us@9
+ * 10.0 8b***   8b***   8b      8b*     12b**   8b*     12b     12b*
+ * 12.5 8b**    8b***   12b***  8b      12b     12b*    16b*    16b**
+ * 15.0 8b**    8b**    12b**   12b***  16b**   12b     20b**   16b
+ * 17.5 8b*     8b*     12b*    12b**   16b     16b**   20b     20b**
+ * 20.0 8b      8b*     16b***  12b*    20b**   16b     24b*    20b
+ * (a * signifies not a full match, but for any length > count(*))
+ *
+ * So 8 bytes prefetch seems to be a very good tradeoff for can frame
+ * except for DLC/LEN=0 frames.
+ * The question here is mainly: how many frames do we have with DLC=0
+ * vs all others.
+ *
+ * With some statistics of recent CAN frames this may be set dynamically
+ * in the future.
+ *
+ * For this to work efficiently we would also need an estimate on
+ * the SPI framework overhead, which is a function of the spi-bus-driver
+ * implementation details, CPU type and speed as well as system load.
+ * Also the effective SPI-clock speed is needed as well as the
+ * number of spi clock cycles it takes for a single byte to get transferred
+ * The bcm283x SOC for example pauses the SPI clock one cycle after
+ * every byte it sends unless the data is fed to the controller by DMA.
+ * (but for short transfers DMA mapping is very expensive and not worth
+ * the effort. PIO and - in some situations - polling is used instead to
+ * reduce the number of interrupts and the need for thread scheduling as
+ * much as possible)
+ *
+ * This also means that for can2.0 only configured interfaces
+ * reading multiple rx fifos is a realistic option of optimization
+ */
+
+static int mcp25xxfd_can_rx_read_single_frames(struct mcp25xxfd_can_priv *cpriv,
+					       int prefetch)
+{
+	int i, f, ret;
+
+	/* loop all frames */
+	for (i = 0, f = cpriv->fifos.rx.start; i < cpriv->fifos.rx.count;
+	     i++, f++) {
+		if (cpriv->status.rxif & BIT(f)) {
+			/* read the frame */
+			ret = mcp25xxfd_can_rx_read_frame(cpriv, f,
+							  prefetch, true);
+			if (ret)
+				return ret;
+		}
+	}
+
+	return 0;
+}
+
+static int mcp25xxfd_can_rx_read_bulk_frames(struct mcp25xxfd_can_priv *cpriv)
+{
+	int i, start, end;
+	int ret;
+
+	/* iterate over fifos trying to find fifos next to each other */
+	for (i = 0, start = cpriv->fifos.rx.start, end = start;
+	     i < cpriv->fifos.rx.count; i++, end++, start = end) {
+		/* if bit is not set then continue */
+		if (!(cpriv->status.rxif & BIT(start)))
+			continue;
+		/* find the last fifo with a bit set in sequence */
+		for (end = start; cpriv->status.rxif & BIT(end + 1); end++)
+			;
+		/* and now read those fifos in bulk */
+		ret = mcp25xxfd_can_read_rx_frame_bulk(cpriv, start, end);
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+}
+
+static int mcp25xxfd_can_rx_read_fd_frames(struct mcp25xxfd_can_priv *cpriv)
+{
+	int i, count_dlc15, count_brs, prefetch;
+
+	/* get a prediction on prefetch */
+	prefetch = mcp25xxfd_can_rx_predict_prefetch(cpriv);
+
+	/* if the prefetch is < 64 then just read single */
+	if (prefetch < 64)
+		return mcp25xxfd_can_rx_read_single_frames(cpriv, prefetch);
+
+	/* check if we have mostly brs frames of those DLC=15 frames */
+	for (i = 0, count_brs = 0, count_dlc15 = 0;
+	     i < MCP25XXFD_CAN_RX_DLC_HISTORY_SIZE; i++)
+		if (cpriv->rx_history.dlc[i] == 15) {
+			count_dlc15++;
+			if (cpriv->rx_history.brs[i])
+				count_brs++;
+		}
+
+	/* if we have at least 33% brs frames then run bulk */
+	if (count_brs * 3 >= count_dlc15 )
+		return mcp25xxfd_can_rx_read_bulk_frames(cpriv);
+	else
+		return mcp25xxfd_can_rx_read_single_frames(cpriv, prefetch);
+}
+
+static int mcp25xxfd_can_rx_read_frames(struct mcp25xxfd_can_priv *cpriv)
+{
+	if (cpriv->can.dev->mtu == CANFD_MTU)
+		return mcp25xxfd_can_rx_read_fd_frames(cpriv);
+	else
+		return mcp25xxfd_can_rx_read_bulk_frames(cpriv);
+}
+
+int mcp25xxfd_can_rx_handle_int_rxif(struct mcp25xxfd_can_priv *cpriv)
+{
+	if (!cpriv->status.rxif)
+		return 0;
+
+	MCP25XXFD_DEBUGFS_STATS_INCR(cpriv, int_rx_count);
+
+	/* read all the fifos */
+	return mcp25xxfd_can_rx_read_frames(cpriv);
+}
+
+int mcp25xxfd_can_rx_handle_int_rxovif(struct mcp25xxfd_can_priv *cpriv)
+{
+	u32 mask = MCP25XXFD_CAN_FIFOSTA_RXOVIF;
+	int ret, i, reg;
+
+	if (!cpriv->status.rxovif)
+		return 0;
+
+	MCP25XXFD_DEBUGFS_STATS_INCR(cpriv, int_rxov_count);
+
+	/* clear all fifos that have an overflow bit set */
+	for (i = 0; i < 32; i++) {
+		if (cpriv->status.rxovif & BIT(i)) {
+			/* clear fifo status */
+			reg = MCP25XXFD_CAN_FIFOSTA(i);
+			ret = mcp25xxfd_cmd_write_mask(cpriv->priv->spi,
+						       reg, 0, mask);
+			if (ret)
+				return ret;
+
+			/* update statistics */
+			cpriv->can.dev->stats.rx_over_errors++;
+			cpriv->can.dev->stats.rx_errors++;
+
+			/* and prepare ERROR FRAME */
+			cpriv->error_frame.id |= CAN_ERR_CRTL;
+			cpriv->error_frame.data[1] |=
+				CAN_ERR_CRTL_RX_OVERFLOW;
+		}
+	}
+
+	return 0;
+}
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/mcp25xxfd/mcp25xxfd_can_rx.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/mcp25xxfd/mcp25xxfd_can_rx.h
new file mode 100644
index 0000000000000000000000000000000000000000..71953e2f3615dc827267c67c092a3a7eb4cc11ad
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/mcp25xxfd/mcp25xxfd_can_rx.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+/* CAN bus driver for Microchip 25XXFD CAN Controller with SPI Interface
+ *
+ * Copyright 2019 Martin Sperl <kernel@martin.sperl.org>
+ */
+
+#ifndef __MCP25XXFD_CAN_RX_H
+#define __MCP25XXFD_CAN_RX_H
+
+#include "mcp25xxfd_priv.h"
+
+int mcp25xxfd_can_rx_submit_frame(struct mcp25xxfd_can_priv *cpriv, int fifo);
+
+int mcp25xxfd_can_rx_handle_int_rxif(struct mcp25xxfd_can_priv *cpriv);
+int mcp25xxfd_can_rx_handle_int_rxovif(struct mcp25xxfd_can_priv *cpriv);
+
+#endif /* __MCP25XXFD_CAN_RX_H */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/mcp25xxfd/mcp25xxfd_can_tx.c b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/mcp25xxfd/mcp25xxfd_can_tx.c
new file mode 100644
index 0000000000000000000000000000000000000000..13cb898247feb657c46c2ae5a4c7a51f6d41e992
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/mcp25xxfd/mcp25xxfd_can_tx.c
@@ -0,0 +1,794 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/* CAN bus driver for Microchip 25XXFD CAN Controller with SPI Interface
+ *
+ * Copyright 2019 Martin Sperl <kernel@martin.sperl.org>
+ *
+ * Based on Microchip MCP251x CAN controller driver written by
+ * David Vrabel, Copyright 2006 Arcom Control Systems Ltd.
+ */
+
+#include <linux/can/core.h>
+#include <linux/can/dev.h>
+#include <linux/device.h>
+#include <linux/kernel.h>
+#include <linux/list.h>
+#include <linux/netdevice.h>
+#include <linux/slab.h>
+#include <linux/spi/spi.h>
+
+#include "mcp25xxfd_can.h"
+#include "mcp25xxfd_can_id.h"
+#include "mcp25xxfd_can_tx.h"
+#include "mcp25xxfd_cmd.h"
+#include "mcp25xxfd_regs.h"
+
+/* mostly bit manipulations to move between stages */
+static struct mcp25xxfd_tx_spi_message *
+mcp25xxfd_can_tx_queue_first_spi_message(struct mcp25xxfd_tx_spi_message_queue *
+					 queue, u32 *bitmap)
+{
+	u32 first = ffs(*bitmap);
+
+	if (!first)
+		return NULL;
+
+	return queue->fifo2message[first - 1];
+}
+
+static void mcp25xxfd_can_tx_queue_remove_spi_message(u32 *bitmap, int fifo)
+{
+	*bitmap &= ~BIT(fifo);
+}
+
+static void mcp25xxfd_can_tx_queue_add_spi_message(u32 *bitmap, int fifo)
+{
+	*bitmap |= BIT(fifo);
+}
+
+static void mcp25xxfd_can_tx_queue_move_spi_message(u32 *src, u32 *dest,
+						    int fifo)
+{
+	mcp25xxfd_can_tx_queue_remove_spi_message(src, fifo);
+	mcp25xxfd_can_tx_queue_add_spi_message(dest, fifo);
+}
+
+static void mcp25xxfd_can_tx_spi_message_fill_fifo_complete(void *context)
+{
+	struct mcp25xxfd_tx_spi_message *msg = context;
+	struct mcp25xxfd_can_priv *cpriv = msg->cpriv;
+	struct mcp25xxfd_tx_spi_message_queue *q = cpriv->fifos.tx_queue;
+	unsigned long flags;
+
+	/* reset transfer length to without data (DLC = 0) */
+	msg->fill_fifo.xfer.len = sizeof(msg->fill_fifo.data.cmd) +
+		sizeof(msg->fill_fifo.data.header);
+
+	/* we need to hold this lock to protect us from
+	 * concurrent access by start_xmit
+	 */
+	spin_lock_irqsave(&cpriv->fifos.tx_queue->lock, flags);
+
+	/* move to in_trigger_fifo_transfer */
+	mcp25xxfd_can_tx_queue_move_spi_message(&q->in_fill_fifo_transfer,
+						&q->in_trigger_fifo_transfer,
+						msg->fifo);
+
+	spin_unlock_irqrestore(&cpriv->fifos.tx_queue->lock, flags);
+}
+
+static void mcp25xxfd_can_tx_spi_message_trigger_fifo_complete(void *context)
+{
+	struct mcp25xxfd_tx_spi_message *msg = context;
+	struct mcp25xxfd_can_priv *cpriv = msg->cpriv;
+	struct mcp25xxfd_tx_spi_message_queue *q = cpriv->fifos.tx_queue;
+	unsigned long flags;
+
+	/* we need to hold this lock to protect us from
+	 * concurrent access by the interrupt thread
+	 */
+	spin_lock_irqsave(&cpriv->fifos.tx_queue->lock, flags);
+
+	/* move to can_transfer */
+	mcp25xxfd_can_tx_queue_move_spi_message(&q->in_trigger_fifo_transfer,
+						&q->in_can_transfer,
+						msg->fifo);
+
+	spin_unlock_irqrestore(&cpriv->fifos.tx_queue->lock, flags);
+}
+
+static
+void mcp25xxfd_can_tx_message_init(struct mcp25xxfd_can_priv *cpriv,
+				   struct mcp25xxfd_tx_spi_message *msg,
+				   int fifo)
+{
+	const u32 trigger = MCP25XXFD_CAN_FIFOCON_TXREQ |
+		MCP25XXFD_CAN_FIFOCON_UINC;
+	const int first_byte = mcp25xxfd_cmd_first_byte(trigger);
+	u32 addr;
+
+	/* and initialize the structure */
+	msg->cpriv = cpriv;
+	msg->fifo = fifo;
+
+	/* init fill_fifo */
+	spi_message_init(&msg->fill_fifo.msg);
+	msg->fill_fifo.msg.complete =
+		mcp25xxfd_can_tx_spi_message_fill_fifo_complete;
+	msg->fill_fifo.msg.context = msg;
+
+	msg->fill_fifo.xfer.speed_hz = cpriv->priv->spi_use_speed_hz;
+	msg->fill_fifo.xfer.tx_buf = msg->fill_fifo.data.cmd;
+	msg->fill_fifo.xfer.len = sizeof(msg->fill_fifo.data.cmd) +
+		sizeof(msg->fill_fifo.data.header);
+	spi_message_add_tail(&msg->fill_fifo.xfer, &msg->fill_fifo.msg);
+
+	addr = MCP25XXFD_SRAM_ADDR(cpriv->fifos.info[fifo].offset);
+	mcp25xxfd_cmd_calc(MCP25XXFD_INSTRUCTION_WRITE, addr,
+			   msg->fill_fifo.data.cmd);
+
+	/* init trigger_fifo */
+	spi_message_init(&msg->trigger_fifo.msg);
+	msg->trigger_fifo.msg.complete =
+		mcp25xxfd_can_tx_spi_message_trigger_fifo_complete;
+	msg->trigger_fifo.msg.context = msg;
+
+	msg->trigger_fifo.xfer.speed_hz = cpriv->priv->spi_use_speed_hz;
+	msg->trigger_fifo.xfer.tx_buf = msg->trigger_fifo.data.cmd;
+	msg->trigger_fifo.xfer.len = sizeof(msg->trigger_fifo.data.cmd) +
+		sizeof(msg->trigger_fifo.data.data);
+	spi_message_add_tail(&msg->trigger_fifo.xfer, &msg->trigger_fifo.msg);
+
+	mcp25xxfd_cmd_calc(MCP25XXFD_INSTRUCTION_WRITE,
+			   MCP25XXFD_CAN_FIFOCON(fifo) + first_byte,
+			   msg->trigger_fifo.data.cmd);
+	msg->trigger_fifo.data.data = trigger >> (8 * first_byte);
+
+	/* and add to idle tx transfers */
+	mcp25xxfd_can_tx_queue_add_spi_message(&cpriv->fifos.tx_queue->idle,
+					       fifo);
+}
+
+static
+void mcp25xxfd_can_tx_queue_manage_nolock(struct mcp25xxfd_can_priv *cpriv,
+					  int state)
+{
+	struct net_device *net = cpriv->can.dev;
+
+	/* skip early */
+	if (state == cpriv->fifos.tx_queue->state)
+		return;
+
+	/* start/stop netif_queue if necessary */
+	switch (cpriv->fifos.tx_queue->state) {
+	case MCP25XXFD_CAN_TX_QUEUE_STATE_RUNABLE:
+		switch (state) {
+		case MCP25XXFD_CAN_TX_QUEUE_STATE_RESTART:
+		case MCP25XXFD_CAN_TX_QUEUE_STATE_STARTED:
+			netif_wake_queue(net);
+			cpriv->fifos.tx_queue->state =
+				MCP25XXFD_CAN_TX_QUEUE_STATE_STARTED;
+			break;
+		}
+		break;
+	case MCP25XXFD_CAN_TX_QUEUE_STATE_STOPPED:
+		switch (state) {
+		case MCP25XXFD_CAN_TX_QUEUE_STATE_STARTED:
+			netif_wake_queue(net);
+			cpriv->fifos.tx_queue->state = state;
+			break;
+		}
+		break;
+	case MCP25XXFD_CAN_TX_QUEUE_STATE_STARTED:
+		switch (state) {
+		case MCP25XXFD_CAN_TX_QUEUE_STATE_RUNABLE:
+		case MCP25XXFD_CAN_TX_QUEUE_STATE_STOPPED:
+			netif_stop_queue(net);
+			cpriv->fifos.tx_queue->state = state;
+			break;
+		}
+		break;
+	default:
+		WARN(true, "Unsupported tx_queue state: %i\n",
+		     cpriv->fifos.tx_queue->state);
+		break;
+	}
+}
+
+void mcp25xxfd_can_tx_queue_manage(struct mcp25xxfd_can_priv *cpriv, int state)
+{
+	unsigned long flags;
+
+	spin_lock_irqsave(&cpriv->fifos.tx_queue->lock, flags);
+
+	mcp25xxfd_can_tx_queue_manage_nolock(cpriv, state);
+
+	spin_unlock_irqrestore(&cpriv->fifos.tx_queue->lock, flags);
+}
+
+void mcp25xxfd_can_tx_queue_restart(struct mcp25xxfd_can_priv *cpriv)
+{
+	u32 state = MCP25XXFD_CAN_TX_QUEUE_STATE_RESTART;
+	unsigned long flags;
+	u32 mask;
+
+	spin_lock_irqsave(&cpriv->fifos.tx_queue->lock, flags);
+
+	/* only move if there is nothing pending or idle */
+	mask = cpriv->fifos.tx_queue->idle |
+		cpriv->fifos.tx_queue->in_fill_fifo_transfer |
+		cpriv->fifos.tx_queue->in_trigger_fifo_transfer |
+		cpriv->fifos.tx_queue->in_can_transfer;
+	if (mask)
+		goto out;
+
+	/* move all items from transferred to idle */
+	cpriv->fifos.tx_queue->idle |= cpriv->fifos.tx_queue->transferred;
+	cpriv->fifos.tx_queue->transferred = 0;
+
+	/* and enable queue */
+	mcp25xxfd_can_tx_queue_manage_nolock(cpriv, state);
+out:
+	spin_unlock_irqrestore(&cpriv->fifos.tx_queue->lock, flags);
+}
+
+static
+int mcp25xxfd_can_tx_tef_read(struct mcp25xxfd_can_priv *cpriv,
+			      int start, int count)
+{
+	u32 tef_offset = start * cpriv->fifos.tef.size;
+	struct mcp25xxfd_can_obj_tef *tef =
+		(struct mcp25xxfd_can_obj_tef *)(cpriv->sram + tef_offset);
+	int last, read, ret;
+
+	/* compute how many we can read in one go */
+	last = start + count;
+	read = (last > cpriv->fifos.tef.count) ?
+		(cpriv->fifos.tef.count - start) :
+		count;
+
+	/* and read it */
+	ret = mcp25xxfd_cmd_read_regs(cpriv->priv->spi,
+				      MCP25XXFD_SRAM_ADDR(tef_offset),
+				      &tef->id, sizeof(*tef) * read);
+	if (ret)
+		return ret;
+
+	/* and read a second part on wrap */
+	if (read != count) {
+		/* update stats */
+		MCP25XXFD_DEBUGFS_STATS_INCR(cpriv, tef_read_splits);
+		/* compute the addresses  */
+		read = count - read;
+		tef = (struct mcp25xxfd_can_obj_tef *)(cpriv->sram);
+		/* and read again */
+		ret = mcp25xxfd_cmd_read_regs(cpriv->priv->spi,
+					      MCP25XXFD_SRAM_ADDR(0),
+					      &tef->id,
+					      sizeof(*tef) * read);
+	}
+
+	return ret;
+}
+
+static
+int mcp25xxfd_can_tx_handle_int_tefif_fifo(struct mcp25xxfd_can_priv *cpriv,
+					   bool read_data)
+{
+	u32 tef_offset = cpriv->fifos.tef.index * cpriv->fifos.tef.size;
+	struct mcp25xxfd_can_obj_tef *tef =
+		(struct mcp25xxfd_can_obj_tef *)(cpriv->sram + tef_offset);
+	int fifo, ret;
+	unsigned long flags;
+
+	/* read the next TEF entry to get the transmit timestamp and fifo */
+	if (read_data) {
+		ret = mcp25xxfd_can_tx_tef_read(cpriv,
+						cpriv->fifos.tef.index, 1);
+		if (ret)
+			return ret;
+	}
+
+	/* get the fifo from tef */
+	fifo = (tef->flags & MCP25XXFD_CAN_OBJ_FLAGS_SEQ_MASK) >>
+		MCP25XXFD_CAN_OBJ_FLAGS_SEQ_SHIFT;
+
+	/* check that the fifo is valid */
+	spin_lock_irqsave(&cpriv->fifos.tx_queue->lock, flags);
+	if ((cpriv->fifos.tx_queue->in_can_transfer & BIT(fifo)) == 0)
+		netdev_err(cpriv->can.dev,
+			   "tefif: fifo %i not pending - tef data: id: %08x flags: %08x, ts: %08x - this may be a problem with spi signal quality- try reducing spi-clock speed if this can get reproduced",
+			   fifo, tef->id, tef->flags, tef->ts);
+	spin_unlock_irqrestore(&cpriv->fifos.tx_queue->lock, flags);
+
+	/* update stats */
+	MCP25XXFD_DEBUGFS_STATS_INCR(cpriv, tef_reads);
+
+	/* now we can schedule the fifo for echo submission */
+	mcp25xxfd_can_queue_frame(cpriv, fifo, tef->ts, false);
+
+	/* increment the tef index with wraparround */
+	cpriv->fifos.tef.index++;
+	if (cpriv->fifos.tef.index >= cpriv->fifos.tef.count)
+		cpriv->fifos.tef.index = 0;
+
+	/* finally just increment the TEF pointer */
+	return mcp25xxfd_cmd_write_mask(cpriv->priv->spi, MCP25XXFD_CAN_TEFCON,
+					MCP25XXFD_CAN_TEFCON_UINC,
+					MCP25XXFD_CAN_TEFCON_UINC);
+}
+
+/* reading TEF entries can be made even more efficient by reading
+ * multiple TEF entries in one go.
+ * Under the assumption that we have count(TEF) >= count(TX_FIFO)
+ * we can even release TEFs early (before we read them)
+ * (and potentially restarting the transmit-queue early aswell)
+ */
+
+static int
+mcp25xxfd_can_tx_handle_int_tefif_conservative(struct mcp25xxfd_can_priv *cpriv)
+{
+	u32 tefsta;
+	int ret;
+
+	/* read the TEF status */
+	ret = mcp25xxfd_cmd_read_mask(cpriv->priv->spi, MCP25XXFD_CAN_TEFSTA,
+				      &tefsta, MCP25XXFD_CAN_TEFSTA_TEFNEIF);
+	if (ret)
+		return ret;
+
+	/* read the tef in an inefficient loop */
+	while (tefsta & MCP25XXFD_CAN_TEFSTA_TEFNEIF) {
+		/* read one tef */
+		ret = mcp25xxfd_can_tx_handle_int_tefif_fifo(cpriv, true);
+		if (ret)
+			return ret;
+
+		MCP25XXFD_DEBUGFS_STATS_INCR(cpriv, tef_conservative_reads);
+
+		/* read the TEF status */
+		ret = mcp25xxfd_cmd_read_mask(cpriv->priv->spi,
+					      MCP25XXFD_CAN_TEFSTA, &tefsta,
+					      MCP25XXFD_CAN_TEFSTA_TEFNEIF);
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+}
+
+static int
+mcp25xxfd_can_tx_handle_int_tefif_optimized(struct mcp25xxfd_can_priv *cpriv,
+					    u32 finished)
+{
+	int i, fifo, count, ret;
+
+	/* count the number of fifos that have terminated */
+	for (i = 0, fifo = cpriv->fifos.tx.start, count = 0;
+	     i < cpriv->fifos.tx.count; i++, fifo++)
+		if (finished & BIT(fifo))
+			count++;
+
+	/* read them in one go if possible
+	 * we also assume that we have count(TEF) >= count(TX-FIFOS)
+	 * this may require 2 reads when we wrap arround
+	 * (that is unless count(TEF) == count(TX-FIFOS))
+	 */
+	ret = mcp25xxfd_can_tx_tef_read(cpriv, cpriv->fifos.tef.index, count);
+	if (ret)
+		return ret;
+
+	/* update stats */
+	MCP25XXFD_DEBUGFS_STATS_INCR(cpriv, tef_optimized_reads);
+	i = min_t(int, MCP25XXFD_CAN_TEF_READ_BINS - 1, count - 1);
+	MCP25XXFD_DEBUGFS_STATS_INCR(cpriv, tef_optimized_read_sizes[i]);
+
+	/* now iterate those */
+	for (i = 0, fifo = cpriv->fifos.tx.start; i < cpriv->fifos.tx.count;
+	     i++, fifo++) {
+		if (finished & BIT(fifo)) {
+			ret = mcp25xxfd_can_tx_handle_int_tefif_fifo(cpriv,
+								     false);
+			if (ret)
+				return ret;
+		}
+	}
+
+	return 0;
+}
+
+int mcp25xxfd_can_tx_handle_int_tefif(struct mcp25xxfd_can_priv *cpriv)
+{
+	unsigned long flags;
+	u32 finished;
+
+	if (!(cpriv->status.intf & MCP25XXFD_CAN_INT_TEFIF))
+		return 0;
+
+	MCP25XXFD_DEBUGFS_STATS_INCR(cpriv, int_tef_count);
+
+	spin_lock_irqsave(&cpriv->fifos.tx_queue->lock, flags);
+
+	/* compute finished fifos and clear them immediately */
+	finished = (cpriv->fifos.tx_queue->in_can_transfer ^
+		    cpriv->status.txreq) &
+		cpriv->fifos.tx_queue->in_can_transfer;
+
+	spin_unlock_irqrestore(&cpriv->fifos.tx_queue->lock, flags);
+
+	/* run in optimized mode if possible */
+	if (finished)
+		return mcp25xxfd_can_tx_handle_int_tefif_optimized(cpriv,
+								   finished);
+	/* otherwise play it safe */
+	netdev_warn(cpriv->can.dev,
+		    "Something is wrong - we got a TEF interrupt but we were not able to detect a finished fifo\n");
+	return mcp25xxfd_can_tx_handle_int_tefif_conservative(cpriv);
+}
+
+static
+void mcp25xxfd_can_tx_fill_fifo_common(struct mcp25xxfd_can_priv *cpriv,
+				       struct mcp25xxfd_tx_spi_message *smsg,
+				       struct mcp25xxfd_can_obj_tx *tx,
+				       int dlc, u8 *data)
+{
+	int len = can_dlc2len(dlc);
+
+	/* update statistics */
+	MCP25XXFD_DEBUGFS_INCR(cpriv->fifos.tx.dlc_usage[dlc]);
+	MCP25XXFD_DEBUGFS_INCR(cpriv->fifos.info[smsg->fifo].use_count);
+
+	/* add fifo number as seq */
+	tx->flags |= smsg->fifo << MCP25XXFD_CAN_OBJ_FLAGS_SEQ_SHIFT;
+
+	/* copy data to tx->data for future reference */
+	memcpy(tx->data, data, len);
+
+	/* transform header to controller format */
+	mcp25xxfd_cmd_convert_from_cpu(&tx->id, sizeof(*tx) / sizeof(u32));
+
+	/* copy header + data to final location - we are not aligned */
+	memcpy(smsg->fill_fifo.data.header, &tx->id, sizeof(*tx) + len);
+
+	/* transfers to sram should be a multiple of 4 and be zero padded */
+	for (; len & 3; len++)
+		*(smsg->fill_fifo.data.header + sizeof(*tx) + len) = 0;
+
+	/* convert it back to CPU format */
+	mcp25xxfd_cmd_convert_to_cpu(&tx->id, sizeof(*tx) / sizeof(u32));
+
+	/* set up size of transfer */
+	smsg->fill_fifo.xfer.len = sizeof(smsg->fill_fifo.data.cmd) +
+		sizeof(smsg->fill_fifo.data.header) + len;
+}
+
+static
+void mcp25xxfd_can_tx_fill_fifo_fd(struct mcp25xxfd_can_priv *cpriv,
+				   struct canfd_frame *frame,
+				   struct mcp25xxfd_tx_spi_message *smsg,
+				   struct mcp25xxfd_can_obj_tx *tx)
+{
+	int dlc = can_len2dlc(frame->len);
+
+	/* update some statistics */
+	MCP25XXFD_DEBUGFS_STATS_INCR(cpriv, tx_fd_count);
+
+	/* compute can id */
+	mcp25xxfd_can_id_to_mcp25xxfd(frame->can_id, &tx->id, &tx->flags);
+
+	/* setup flags */
+	tx->flags |= dlc << MCP25XXFD_CAN_OBJ_FLAGS_DLC_SHIFT;
+	tx->flags |= (frame->can_id & CAN_EFF_FLAG) ?
+		MCP25XXFD_CAN_OBJ_FLAGS_IDE : 0;
+	tx->flags |= (frame->can_id & CAN_RTR_FLAG) ?
+		MCP25XXFD_CAN_OBJ_FLAGS_RTR : 0;
+	if (frame->flags & CANFD_BRS) {
+		tx->flags |= MCP25XXFD_CAN_OBJ_FLAGS_BRS;
+		MCP25XXFD_DEBUGFS_STATS_INCR(cpriv, tx_brs_count);
+	}
+	tx->flags |= (frame->flags & CANFD_ESI) ?
+		MCP25XXFD_CAN_OBJ_FLAGS_ESI : 0;
+	tx->flags |= MCP25XXFD_CAN_OBJ_FLAGS_FDF;
+
+	/* and do common processing */
+	mcp25xxfd_can_tx_fill_fifo_common(cpriv, smsg, tx, dlc, frame->data);
+}
+
+static
+void mcp25xxfd_can_tx_fill_fifo(struct mcp25xxfd_can_priv *cpriv,
+				struct can_frame *frame,
+				struct mcp25xxfd_tx_spi_message *smsg,
+				struct mcp25xxfd_can_obj_tx *tx)
+{
+	/* set frame to valid dlc */
+	if (frame->can_dlc > 8)
+		frame->can_dlc = 8;
+
+	/* compute can id */
+	mcp25xxfd_can_id_to_mcp25xxfd(frame->can_id, &tx->id, &tx->flags);
+
+	/* setup flags */
+	tx->flags |= frame->can_dlc << MCP25XXFD_CAN_OBJ_FLAGS_DLC_SHIFT;
+	tx->flags |= (frame->can_id & CAN_EFF_FLAG) ?
+		MCP25XXFD_CAN_OBJ_FLAGS_IDE : 0;
+	tx->flags |= (frame->can_id & CAN_RTR_FLAG) ?
+		MCP25XXFD_CAN_OBJ_FLAGS_RTR : 0;
+
+	/* and do common processing */
+	mcp25xxfd_can_tx_fill_fifo_common(cpriv, smsg, tx, frame->can_dlc,
+					  frame->data);
+}
+
+static struct mcp25xxfd_tx_spi_message *
+mcp25xxfd_can_tx_queue_get_next_fifo(struct mcp25xxfd_can_priv *cpriv)
+{
+	u32 state = MCP25XXFD_CAN_TX_QUEUE_STATE_RUNABLE;
+	struct mcp25xxfd_tx_spi_message_queue *q = cpriv->fifos.tx_queue;
+	struct mcp25xxfd_tx_spi_message *smsg;
+	unsigned long flags;
+
+	/* we need to hold this lock to protect us against
+	 * concurrent modifications of cpriv->fifos.tx_queue->idle
+	 * in the interrupt thread
+	 */
+	spin_lock_irqsave(&q->lock, flags);
+
+	/* get the first entry from idle */
+	smsg = mcp25xxfd_can_tx_queue_first_spi_message(q, &q->idle);
+	if (!smsg)
+		goto out_busy;
+
+	/* and move the fifo to next stage */
+	mcp25xxfd_can_tx_queue_move_spi_message(&q->idle,
+						&q->in_fill_fifo_transfer,
+						smsg->fifo);
+
+	/* if queue is empty then stop the network queue immediately */
+	if (!q->idle)
+		mcp25xxfd_can_tx_queue_manage_nolock(cpriv, state);
+out_busy:
+	spin_unlock_irqrestore(&q->lock, flags);
+
+	return smsg;
+}
+
+/* submit the can message to the can-bus */
+netdev_tx_t mcp25xxfd_can_tx_start_xmit(struct sk_buff *skb,
+					struct net_device *net)
+{
+	u32 state = MCP25XXFD_CAN_TX_QUEUE_STATE_STOPPED;
+	struct mcp25xxfd_can_priv *cpriv = netdev_priv(net);
+	struct mcp25xxfd_tx_spi_message_queue *q = cpriv->fifos.tx_queue;
+	struct mcp25xxfd_priv *priv = cpriv->priv;
+	struct spi_device *spi = priv->spi;
+	struct mcp25xxfd_tx_spi_message *smsg;
+	struct mcp25xxfd_can_obj_tx *tx;
+	unsigned long flags;
+	int ret;
+
+	/* invalid skb we can ignore */
+	if (can_dropped_invalid_skb(net, skb))
+		return NETDEV_TX_OK;
+
+	/* acquire lock on spi so that we are are not risking
+	 * some reordering of spi messages when we are running
+	 * start_xmit in multiple threads (on multiple cores)
+	 */
+	spin_lock_irqsave(&q->spi_lock, flags);
+
+	/* get the fifo message structure to process now */
+	smsg = mcp25xxfd_can_tx_queue_get_next_fifo(cpriv);
+	if (!smsg)
+		goto out_busy;
+
+	/* compute the fifo in sram */
+	tx = (struct mcp25xxfd_can_obj_tx *)
+		(cpriv->sram + cpriv->fifos.info[smsg->fifo].offset);
+
+	/* fill in message from skb->data depending on can2.0 or canfd */
+	if (can_is_canfd_skb(skb))
+		mcp25xxfd_can_tx_fill_fifo_fd(cpriv,
+					      (struct canfd_frame *)skb->data,
+					      smsg, tx);
+	else
+		mcp25xxfd_can_tx_fill_fifo(cpriv,
+					   (struct can_frame *)skb->data,
+					   smsg, tx);
+
+	/* submit the two messages asyncronously
+	 * the reason why we separate transfers into two spi_messages is:
+	 *  * because the spi framework (currently) does add a 10us delay
+	 *    between 2 spi_transfers in a single spi_message when
+	 *    change_cs is set - 2 consecutive spi messages show a shorter
+	 *    cs disable phase increasing bus utilization
+	 *    (code reduction with a fix in spi core would be aprox.50 lines)
+	 *  * this allows the interrupt handler to start spi messages earlier
+	 *    so reducing latencies a bit and to allow for better concurrency
+	 *  * this separation - in the future - may get used to fill fifos
+	 *    early and reduce the delay on "rollover"
+	 */
+	ret = spi_async(spi, &smsg->fill_fifo.msg);
+	if (ret)
+		goto out_async_failed;
+	ret = spi_async(spi, &smsg->trigger_fifo.msg);
+	if (ret)
+		goto out_async_failed;
+
+	/* unlock the spi bus */
+	spin_unlock_irqrestore(&q->spi_lock, flags);
+
+	/* keep it for reference until the message really got transmitted */
+	can_put_echo_skb(skb, net, smsg->fifo);
+
+	return NETDEV_TX_OK;
+out_async_failed:
+	netdev_err(net, "spi_async submission of fifo %i failed - %i\n",
+		   smsg->fifo, ret);
+
+out_busy:
+	/* stop the queue */
+	mcp25xxfd_can_tx_queue_manage_nolock(cpriv, state);
+
+	spin_unlock_irqrestore(&q->spi_lock, flags);
+
+	return NETDEV_TX_BUSY;
+}
+
+/* submit the fifo back to the network stack */
+int mcp25xxfd_can_tx_submit_frame(struct mcp25xxfd_can_priv *cpriv, int fifo)
+{
+	struct mcp25xxfd_tx_spi_message_queue *q = cpriv->fifos.tx_queue;
+	struct mcp25xxfd_can_obj_tx *tx = (struct mcp25xxfd_can_obj_tx *)
+		(cpriv->sram + cpriv->fifos.info[fifo].offset);
+	int dlc = (tx->flags & MCP25XXFD_CAN_OBJ_FLAGS_DLC_MASK) >>
+		MCP25XXFD_CAN_OBJ_FLAGS_DLC_SHIFT;
+	unsigned long flags;
+
+	/* update counters */
+	cpriv->can.dev->stats.tx_packets++;
+	cpriv->can.dev->stats.tx_bytes += can_dlc2len(dlc);
+	MCP25XXFD_DEBUGFS_INCR(cpriv->fifos.tx.dlc_usage[dlc]);
+	if (tx->flags & MCP25XXFD_CAN_OBJ_FLAGS_FDF)
+		MCP25XXFD_DEBUGFS_STATS_INCR(cpriv, tx_fd_count);
+	if (tx->flags & MCP25XXFD_CAN_OBJ_FLAGS_BRS)
+		MCP25XXFD_DEBUGFS_STATS_INCR(cpriv, tx_brs_count);
+
+	spin_lock_irqsave(&cpriv->fifos.tx_queue->lock, flags);
+
+	/* release the echo buffer */
+	can_get_echo_skb(cpriv->can.dev, fifo);
+
+	/* move from in_can_transfer to transferred */
+	mcp25xxfd_can_tx_queue_move_spi_message(&q->in_can_transfer,
+						&q->transferred, fifo);
+
+	spin_unlock_irqrestore(&cpriv->fifos.tx_queue->lock, flags);
+
+	return 0;
+}
+
+/* interrupt handler */
+int mcp25xxfd_can_tx_handle_int_txatif_fifo(struct mcp25xxfd_can_priv *cpriv,
+					    int fifo)
+{
+	struct mcp25xxfd_tx_spi_message_queue *q = cpriv->fifos.tx_queue;
+	u32 val;
+	unsigned long flags;
+	int ret;
+
+	/* read fifo status */
+	ret = mcp25xxfd_cmd_read(cpriv->priv->spi,
+				 MCP25XXFD_CAN_FIFOSTA(fifo), &val);
+	if (ret)
+		return ret;
+
+	/* clear the relevant interrupt flags */
+	ret = mcp25xxfd_cmd_write_mask(cpriv->priv->spi,
+				       MCP25XXFD_CAN_FIFOSTA(fifo), 0,
+				       MCP25XXFD_CAN_FIFOSTA_TXABT |
+				       MCP25XXFD_CAN_FIFOSTA_TXLARB |
+				       MCP25XXFD_CAN_FIFOSTA_TXERR |
+				       MCP25XXFD_CAN_FIFOSTA_TXATIF);
+	if (ret)
+		return ret;
+
+	spin_lock_irqsave(&q->lock, flags);
+	/* for specific cases we probably could trigger a retransmit
+	 * instead of an abort.
+	 */
+
+	/* and we release it from the echo_skb buffer
+	 * NOTE: this is one place where packet delivery will not
+	 * be ordered, as we do not have any timing information
+	 * when this occurred
+	 */
+	can_get_echo_skb(cpriv->can.dev, fifo);
+
+	mcp25xxfd_can_tx_queue_move_spi_message(&q->in_can_transfer,
+						&q->transferred, fifo);
+
+	spin_unlock_irqrestore(&q->lock, flags);
+
+	/* but we need to run a bit of cleanup */
+	cpriv->status.txif &= ~BIT(fifo);
+	cpriv->can.dev->stats.tx_aborted_errors++;
+
+	/* handle all the known cases accordingly - ignoring FIFO full */
+	val &= MCP25XXFD_CAN_FIFOSTA_TXABT |
+		MCP25XXFD_CAN_FIFOSTA_TXLARB |
+		MCP25XXFD_CAN_FIFOSTA_TXERR;
+	switch (val) {
+	case MCP25XXFD_CAN_FIFOSTA_TXERR:
+		/* this indicates a possible bus error */
+		break;
+	default:
+		dev_warn_ratelimited(&cpriv->priv->spi->dev,
+				     "Unknown TX-Fifo abort condition: %08x - stopping tx-queue\n",
+				     val);
+		break;
+	}
+
+	return 0;
+}
+
+int mcp25xxfd_can_tx_handle_int_txatif(struct mcp25xxfd_can_priv *cpriv)
+{
+	int i, f, ret;
+
+	/* if txatif is unset, then there are no
+	 * can frames that have been transmitted
+	 * and need to get reingested into the network stack
+	 */
+	if (!cpriv->status.txatif)
+		return 0;
+	MCP25XXFD_DEBUGFS_STATS_INCR(cpriv, int_txat_count);
+
+	/* process all the fifos with that flag set */
+	for (i = 0, f = cpriv->fifos.tx.start; i < cpriv->fifos.tx.count;
+	     i++, f++) {
+		if (cpriv->status.txatif & BIT(f)) {
+			ret = mcp25xxfd_can_tx_handle_int_txatif_fifo(cpriv, f);
+			if (ret)
+				return ret;
+		}
+	}
+
+	return 0;
+}
+
+int mcp25xxfd_can_tx_queue_alloc(struct mcp25xxfd_can_priv *cpriv)
+{
+	struct mcp25xxfd_tx_spi_message *msg;
+	size_t size = sizeof(struct mcp25xxfd_tx_spi_message_queue) +
+		cpriv->fifos.tx.count * sizeof(*msg);
+	int i, f;
+
+	/* allocate the fifos as an array */
+	cpriv->fifos.tx_queue = kzalloc(size, GFP_KERNEL);
+	if (!cpriv->fifos.tx_queue)
+		return -ENOMEM;
+
+	/* initialize the tx_queue structure */
+	spin_lock_init(&cpriv->fifos.tx_queue->lock);
+	spin_lock_init(&cpriv->fifos.tx_queue->spi_lock);
+
+	/* initialize the individual spi_message structures */
+	for (i = 0, f = cpriv->fifos.tx.start; i < cpriv->fifos.tx.count;
+	     i++, f++) {
+		msg = &cpriv->fifos.tx_queue->message[i];
+		cpriv->fifos.tx_queue->fifo2message[f] = msg;
+		mcp25xxfd_can_tx_message_init(cpriv, msg, f);
+	}
+
+	return 0;
+}
+
+void mcp25xxfd_can_tx_queue_free(struct mcp25xxfd_can_priv *cpriv)
+{
+	/* eventually we may need to wait here
+	 * for all transfers to have finished
+	 */
+
+	kfree(cpriv->fifos.tx_queue);
+	cpriv->fifos.tx_queue = NULL;
+}
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/mcp25xxfd/mcp25xxfd_can_tx.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/mcp25xxfd/mcp25xxfd_can_tx.h
new file mode 100644
index 0000000000000000000000000000000000000000..1947b3420d585fc5fc87952f2c20ef2d655fc26c
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/mcp25xxfd/mcp25xxfd_can_tx.h
@@ -0,0 +1,86 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+/* CAN bus driver for Microchip 25XXFD CAN Controller with SPI Interface
+ *
+ * Copyright 2019 Martin Sperl <kernel@martin.sperl.org>
+ */
+
+#ifndef __MCP25XXFD_CAN_TX_H
+#define __MCP25XXFD_CAN_TX_H
+
+#include <linux/spinlock.h>
+#include <linux/spi/spi.h>
+
+#include "mcp25xxfd_can_priv.h"
+
+/* structure of a spi message that is prepared and can get submitted quickly */
+struct mcp25xxfd_tx_spi_message {
+	/* the network device this is related to */
+	struct mcp25xxfd_can_priv *cpriv;
+	/* the fifo this fills */
+	u32 fifo;
+	/* the xfer to fill in the fifo data */
+	struct {
+		struct spi_message msg;
+		struct spi_transfer xfer;
+		struct {
+			u8 cmd[2];
+			u8 header[sizeof(struct mcp25xxfd_can_obj_tx)];
+			u8 data[64];
+		} data;
+	} fill_fifo;
+	/* the xfer to enable transmission on the can bus */
+	struct {
+		struct spi_message msg;
+		struct spi_transfer xfer;
+		struct {
+			u8 cmd[2];
+			u8 data;
+		} data;
+	} trigger_fifo;
+};
+
+struct mcp25xxfd_tx_spi_message_queue {
+	/* spinlock protecting the bitmaps
+	 * as well as state and the skb_echo_* functions
+	 */
+	spinlock_t lock;
+	/* bitmap of which fifo is in which stage */
+	u32 idle;
+	u32 in_fill_fifo_transfer;
+	u32 in_trigger_fifo_transfer;
+	u32 in_can_transfer;
+	u32 transferred;
+
+	/* the queue state as seen per controller */
+	int state;
+#define MCP25XXFD_CAN_TX_QUEUE_STATE_STOPPED 0
+#define MCP25XXFD_CAN_TX_QUEUE_STATE_STARTED 1
+#define MCP25XXFD_CAN_TX_QUEUE_STATE_RUNABLE 2
+#define MCP25XXFD_CAN_TX_QUEUE_STATE_RESTART 3
+
+	/* spinlock protecting spi submission order */
+	spinlock_t spi_lock;
+
+	/* map each fifo to a mcp25xxfd_tx_spi_message */
+	struct mcp25xxfd_tx_spi_message *fifo2message[32];
+
+	/* the individual messages */
+	struct mcp25xxfd_tx_spi_message message[];
+};
+
+int mcp25xxfd_can_tx_submit_frame(struct mcp25xxfd_can_priv *cpriv, int fifo);
+void mcp25xxfd_can_tx_queue_restart(struct mcp25xxfd_can_priv *cpriv);
+
+int mcp25xxfd_can_tx_handle_int_txatif(struct mcp25xxfd_can_priv *cpriv);
+int mcp25xxfd_can_tx_handle_int_tefif(struct mcp25xxfd_can_priv *cpriv);
+
+netdev_tx_t mcp25xxfd_can_tx_start_xmit(struct sk_buff *skb,
+					struct net_device *net);
+
+void mcp25xxfd_can_tx_queue_manage(struct mcp25xxfd_can_priv *cpriv, int state);
+
+int mcp25xxfd_can_tx_queue_alloc(struct mcp25xxfd_can_priv *cpriv);
+void mcp25xxfd_can_tx_queue_free(struct mcp25xxfd_can_priv *cpriv);
+
+#endif /* __MCP25XXFD_CAN_TX_H */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/mcp25xxfd/mcp25xxfd_clock.c b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/mcp25xxfd/mcp25xxfd_clock.c
new file mode 100644
index 0000000000000000000000000000000000000000..aee482e7c02aec1a8a6259d9c67bc4e87b040fe0
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/mcp25xxfd/mcp25xxfd_clock.c
@@ -0,0 +1,485 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/* CAN bus driver for Microchip 25XXFD CAN Controller with SPI Interface
+ *
+ * Copyright 2019 Martin Sperl <kernel@martin.sperl.org>
+ */
+
+/* Known hardware issues and workarounds in this driver:
+ *
+ * * There is one situation where the controller will require a full POR
+ *   (total power off) to recover from a bad Clock configuration.
+ *   This happens when the wrong clock is configured in the device tree
+ *   (say 4MHz are configured, while 40MHz is the actual clock frequency
+ *   of the HW).
+ *   In such a situation the driver tries to enable the PLL, which will
+ *   never synchronize and the controller becomes unresponsive to further
+ *   spi requests until a full POR.
+ *
+ *   Mitigation:
+ *     none as of now
+ *
+ *   Possible implementation of a mitigation/sanity check:
+ *     during initialization:
+ *       * try to identify the HW at 1MHz:
+ *         on success:
+ *           * controller is identified
+ *         on failure:
+ *           * controller is absent - fail
+ *       * force controller clock to run with disabled PLL
+ *       * try to identify the HW at 2MHz:
+ *         on success:
+ *           * controller clock is >= 4 MHz
+ *           * this may be 4MHz
+ *         on failure:
+ *           * controller clock is < 4 MHz
+ *       * try to identify the HW at 2.5MHz:
+ *         on success:
+ *           * controller clock is >= 5 MHz
+ *           * this may not be 4MHz
+ *         on failure:
+ *           * controller clock is 4 MHz
+ *           * enable PLL
+ *           * exit successfully (or run last test for verification purposes)
+ *       * try to identify the HW at <dt-clock/2> MHz:
+ *         on success:
+ *           * controller clock is >= <dt-clock/2> MHz
+ *              (it could be higher though)
+ *         on failure:
+ *           * the controller is not running at the
+ *             clock rate configured in the DT
+ *           * if PLL is enabled warn about requirements of POR
+ *           * fail
+ *
+ *   Side-effects:
+ *     * longer initialization time
+ *
+ *   Possible issues with mitigation:
+ *     * possibly miss-identification because the SPI block may work
+ *       "somewhat" at frequencies > < clock / 2 + delta f>
+ *       this may be especially true for the situation where we test if
+ *       2.5MHz SPI-Clock works.
+ *     * also SPI HW-clock dividers may do a round down to fixed frequencies
+ *       which is not properly reported and may result in false positives
+ *       because a frequency lower than expected is used.
+ *
+ *   This is the reason why only simple testing is enabled at the risk of
+ *   the need for a POR.
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/jiffies.h>
+#include <linux/kernel.h>
+#include <linux/mutex.h>
+#include <linux/of.h>
+#include <linux/spi/spi.h>
+
+#include "mcp25xxfd_can.h"
+#include "mcp25xxfd_cmd.h"
+#include "mcp25xxfd_priv.h"
+
+/* the PLL may take some time to synchronize - use 1 second as timeout */
+#define MCP25XXFD_OSC_POLLING_JIFFIES	(HZ)
+
+static u32 _mcp25xxfd_clkout_mask(struct mcp25xxfd_priv *priv)
+{
+	u32 val = 0;
+
+	if (priv->config.clock_div2)
+		val |= MCP25XXFD_OSC_SCLKDIV;
+
+	switch (priv->config.clock_odiv) {
+	case 0:
+		break;
+	case 1:
+		val |= MCP25XXFD_OSC_CLKODIV_1 << MCP25XXFD_OSC_CLKODIV_SHIFT;
+		break;
+	case 2:
+		val |= MCP25XXFD_OSC_CLKODIV_2 << MCP25XXFD_OSC_CLKODIV_SHIFT;
+		break;
+	case 4:
+		val |= MCP25XXFD_OSC_CLKODIV_4 << MCP25XXFD_OSC_CLKODIV_SHIFT;
+		break;
+	case 10:
+		val |= MCP25XXFD_OSC_CLKODIV_10 << MCP25XXFD_OSC_CLKODIV_SHIFT;
+		break;
+	default:
+		/* this should never happen but is error-handled
+		 * by the dt-parsing
+		 */
+		break;
+	}
+
+	return val;
+}
+
+static int _mcp25xxfd_waitfor_osc(struct mcp25xxfd_priv *priv,
+				  u32 waitfor, u32 mask)
+{
+	unsigned long timeout;
+	int ret;
+
+	/* wait for synced pll/osc/sclk */
+	timeout = jiffies + MCP25XXFD_OSC_POLLING_JIFFIES;
+	while (time_before_eq(jiffies, timeout)) {
+		ret = mcp25xxfd_cmd_read(priv->spi, MCP25XXFD_OSC,
+					 &priv->regs.osc);
+		if (ret)
+			return ret;
+		/* check for expected bits to be set/unset */
+		if ((priv->regs.osc & mask) == waitfor)
+			return 0;
+	}
+
+	return -ETIMEDOUT;
+}
+
+static int _mcp25xxfd_clock_configure_osc(struct mcp25xxfd_priv *priv,
+					  u32 value, u32 waitfor, u32 mask)
+{
+	int ret;
+
+	/* write the osc value to the controller - waking it if necessary */
+	ret = mcp25xxfd_cmd_write(priv->spi, MCP25XXFD_OSC, value);
+	if (ret)
+		return ret;
+
+	/* wait for the clock to stabelize */
+	ret = _mcp25xxfd_waitfor_osc(priv, waitfor, mask);
+
+	/* on timeout try again setting the register */
+	if (ret == -ETIMEDOUT) {
+		/* write the clock to the controller */
+		ret = mcp25xxfd_cmd_write(priv->spi, MCP25XXFD_OSC, value);
+		if (ret)
+			return ret;
+
+		/* wait for the clock to stabelize */
+		ret = _mcp25xxfd_waitfor_osc(priv, waitfor, mask);
+	}
+
+	/* handle timeout special - report the fact */
+	if (ret == -ETIMEDOUT)
+		dev_err(&priv->spi->dev,
+			"Clock did not switch within the timeout period\n");
+
+	return ret;
+}
+
+static int _mcp25xxfd_clock_start(struct mcp25xxfd_priv *priv)
+{
+	u32 value = _mcp25xxfd_clkout_mask(priv);
+	u32 waitfor = MCP25XXFD_OSC_OSCRDY;
+	u32 mask = waitfor | MCP25XXFD_OSC_OSCDIS | MCP25XXFD_OSC_PLLRDY |
+		MCP25XXFD_OSC_PLLEN;
+
+	/* enable PLL as well - set expectations */
+	if (priv->config.clock_pll) {
+		value   |= MCP25XXFD_OSC_PLLEN;
+		waitfor |= MCP25XXFD_OSC_PLLRDY | MCP25XXFD_OSC_PLLEN;
+	}
+
+	/* set the oscilator now */
+	return _mcp25xxfd_clock_configure_osc(priv, value, waitfor, mask);
+}
+
+static int _mcp25xxfd_clock_stop(struct mcp25xxfd_priv *priv)
+{
+	u32 value = _mcp25xxfd_clkout_mask(priv);
+	u32 waitfor = 0;
+	u32 mask = MCP25XXFD_OSC_OSCDIS | MCP25XXFD_OSC_PLLRDY |
+		MCP25XXFD_OSC_PLLEN;
+	int ret;
+
+	ret = _mcp25xxfd_clock_configure_osc(priv, value, waitfor, mask);
+	if (ret)
+		return ret;
+
+	/* finally switch the controller mode to sleep
+	 * by this time the controller should be in config mode already
+	 * this way we wake to config mode again
+	 */
+	return mcp25xxfd_can_sleep_mode(priv);
+}
+
+int mcp25xxfd_clock_start(struct mcp25xxfd_priv *priv, int requestor_mask)
+{
+	int ret = 0;
+
+	/* without a clock there is nothing we can do... */
+	if (IS_ERR(priv->clk))
+		return PTR_ERR(priv->clk);
+
+	mutex_lock(&priv->clk_user_lock);
+
+	/* if clock is already started, then skip */
+	if (priv->clk_user_mask & requestor_mask)
+		goto out;
+
+	/* enable the clock on the host side*/
+	ret = clk_prepare_enable(priv->clk);
+	if (ret)
+		goto out;
+
+	/* enable the clock on the controller side */
+	ret = _mcp25xxfd_clock_start(priv);
+	if (ret)
+		goto out;
+
+	/* mark the clock for the specific component as started */
+	priv->clk_user_mask |= requestor_mask;
+
+	/* and now we use the normal spi speed */
+	priv->spi_use_speed_hz = priv->spi_normal_speed_hz;
+
+out:
+	mutex_unlock(&priv->clk_user_lock);
+
+	return ret;
+}
+
+int mcp25xxfd_clock_stop(struct mcp25xxfd_priv *priv, int requestor_mask)
+{
+	int ret;
+
+	/* without a clock there is nothing we can do... */
+	if (IS_ERR(priv->clk))
+		return PTR_ERR(priv->clk);
+
+	mutex_lock(&priv->clk_user_lock);
+
+	/* if the mask is empty then skip, as the clock is stopped */
+	if (!priv->clk_user_mask)
+		goto out;
+
+	/* clear the clock mask */
+	priv->clk_user_mask &= ~requestor_mask;
+
+	/* if the mask is not empty then skip, as the clock is needed */
+	if (priv->clk_user_mask)
+		goto out;
+
+	/* and now we use the setup spi speed */
+	priv->spi_use_speed_hz = priv->spi_setup_speed_hz;
+
+	/* stop the clock on the controller */
+	ret = _mcp25xxfd_clock_stop(priv);
+
+	/* and we stop the clock on the host*/
+	if (!IS_ERR(priv->clk))
+		clk_disable_unprepare(priv->clk);
+out:
+	mutex_unlock(&priv->clk_user_lock);
+
+	return 0;
+}
+
+static int _mcp25xxfd_clock_probe(struct mcp25xxfd_priv *priv)
+{
+	int ret;
+
+	/* Wait for oscillator startup timer after power up */
+	mdelay(MCP25XXFD_OST_DELAY_MS);
+
+	/* send a "blind" reset, hoping we are in Config mode */
+	mcp25xxfd_cmd_reset(priv->spi);
+
+	/* Wait for oscillator startup again */
+	mdelay(MCP25XXFD_OST_DELAY_MS);
+
+	/* check clock register that the clock is ready or disabled */
+	ret = mcp25xxfd_cmd_read(priv->spi, MCP25XXFD_OSC,
+				 &priv->regs.osc);
+	if (ret)
+		return ret;
+
+	/* there can only be one... */
+	switch (priv->regs.osc &
+		(MCP25XXFD_OSC_OSCRDY | MCP25XXFD_OSC_OSCDIS)) {
+	case MCP25XXFD_OSC_OSCRDY: /* either the clock is ready */
+		break;
+	case MCP25XXFD_OSC_OSCDIS: /* or the clock is disabled */
+		break;
+	default:
+		/* otherwise there is no valid device (or in strange state)
+		 *
+		 * if PLL is enabled but not ready, then there may be
+		 * something "fishy"
+		 * this happened during driver development
+		 * (enabling pll, when when on wrong clock), so best warn
+		 * about such a possibility
+		 */
+		if ((priv->regs.osc &
+		     (MCP25XXFD_OSC_PLLEN | MCP25XXFD_OSC_PLLRDY))
+		    == MCP25XXFD_OSC_PLLEN)
+			dev_err(&priv->spi->dev,
+				"mcp25xxfd may be in a strange state - a power disconnect may be required\n");
+
+		return -ENODEV;
+	}
+
+	return 0;
+}
+
+int mcp25xxfd_clock_probe(struct mcp25xxfd_priv *priv)
+{
+	int ret;
+
+	/* this will also enable the MCP25XXFD_CLK_USER_CAN clock */
+	ret = _mcp25xxfd_clock_probe(priv);
+
+	/* on error retry a second time */
+	if (ret == -ENODEV) {
+		ret = _mcp25xxfd_clock_probe(priv);
+		if (!ret)
+			dev_info(&priv->spi->dev,
+				 "found device only during retry\n");
+	}
+	if (ret) {
+		if (ret == -ENODEV)
+			dev_err(&priv->spi->dev,
+				"Cannot initialize MCP%x. Wrong wiring? (oscilator register reads as %08x)\n",
+				priv->model, priv->regs.osc);
+	}
+
+	return ret;
+}
+
+void mcp25xxfd_clock_release(struct mcp25xxfd_priv *priv)
+{
+	if (!IS_ERR_OR_NULL(priv->clk))
+		clk_disable_unprepare(priv->clk);
+}
+
+#ifdef CONFIG_OF_DYNAMIC
+static int mcp25xxfd_clock_of_parse(struct mcp25xxfd_priv *priv)
+{
+	struct spi_device *spi = priv->spi;
+	const struct device_node *np = spi->dev.of_node;
+	u32 val;
+	int ret;
+
+	priv->config.clock_div2 = false;
+	priv->config.clock_div2 =
+		of_property_read_bool(np, "microchip,clock-div2");
+
+	priv->config.clock_odiv = 10;
+	ret = of_property_read_u32_index(np, "microchip,clock-out-div",
+					 0, &val);
+	if (!ret) {
+		switch (val) {
+		case 0:
+		case 1:
+		case 2:
+		case 4:
+		case 10:
+			priv->config.clock_odiv = val;
+			break;
+		default:
+			dev_err(&spi->dev,
+				"Invalid value in device tree for microchip,clock_out_div: %u - valid values: 0, 1, 2, 4, 10\n",
+				val);
+			return -EINVAL;
+		}
+	}
+
+	return 0;
+}
+#else
+static int mcp25xxfd_clock_of_parse(struct mcp25xxfd_priv *priv)
+{
+	return 0;
+}
+#endif
+
+int mcp25xxfd_clock_init(struct mcp25xxfd_priv *priv)
+{
+	struct spi_device *spi = priv->spi;
+	struct clk *clk;
+	int ret, freq;
+
+	mutex_init(&priv->clk_user_lock);
+
+	priv->config.clock_div2 = false;
+	priv->config.clock_odiv = 10;
+
+	ret = mcp25xxfd_clock_of_parse(priv);
+	if (ret)
+		return ret;
+
+	/* get clock */
+	clk = devm_clk_get(&spi->dev, NULL);
+	if (IS_ERR(clk))
+		return PTR_ERR(clk);
+
+	freq = clk_get_rate(clk);
+	if (freq < MCP25XXFD_MIN_CLOCK_FREQUENCY ||
+	    freq > MCP25XXFD_MAX_CLOCK_FREQUENCY) {
+		dev_err(&spi->dev,
+			"Clock frequency %i is not in range [%i:%i]\n",
+			freq,
+			MCP25XXFD_MIN_CLOCK_FREQUENCY,
+			MCP25XXFD_MAX_CLOCK_FREQUENCY);
+		return -ERANGE;
+	}
+
+	/* enable the clock and mark as enabled */
+	ret = clk_prepare_enable(clk);
+	if (ret)
+		return ret;
+	priv->clk = clk;
+
+	/* if we have a clock that is <= 4MHz, enable the pll */
+	priv->config.clock_pll =
+		(freq <= MCP25XXFD_AUTO_PLL_MAX_CLOCK_FREQUENCY);
+
+	/* decide on the effective clock rate */
+	priv->clock_freq = freq;
+	if (priv->config.clock_pll)
+		priv->clock_freq *= MCP25XXFD_PLL_MULTIPLIER;
+	if (priv->config.clock_div2)
+		priv->clock_freq /= MCP25XXFD_SCLK_DIVIDER;
+
+	/* calculate the clock frequencies to use
+	 *
+	 * setup clock speed is at most 1/4 the input clock speed
+	 * the reason for the factor of 4 is that there is
+	 * a clock divider in the controller that MAY be enabled in some
+	 * circumstances so we may find a controller with that enabled
+	 * during probe phase
+	 */
+	priv->spi_setup_speed_hz = freq / 4;
+
+	/* normal operation clock speeds */
+	priv->spi_normal_speed_hz = priv->clock_freq / 2;
+	if (priv->config.clock_div2) {
+		priv->spi_setup_speed_hz /= MCP25XXFD_SCLK_DIVIDER;
+		priv->spi_normal_speed_hz /= MCP25XXFD_SCLK_DIVIDER;
+	}
+
+	/* set limit on speed */
+	if (spi->max_speed_hz) {
+		priv->spi_setup_speed_hz = min_t(int,
+						 priv->spi_setup_speed_hz,
+						 spi->max_speed_hz);
+		priv->spi_normal_speed_hz = min_t(int,
+						  priv->spi_normal_speed_hz,
+						  spi->max_speed_hz);
+	}
+
+	/* use setup speed by default
+	 * - this is switched when clock is enabled/disabled
+	 */
+	priv->spi_use_speed_hz = priv->spi_setup_speed_hz;
+
+	return 0;
+}
+
+void mcp25xxfd_clock_fake_sleep(struct mcp25xxfd_priv *priv)
+{
+	priv->regs.osc &= ~(MCP25XXFD_OSC_OSCRDY |
+			    MCP25XXFD_OSC_PLLRDY |
+			    MCP25XXFD_OSC_SCLKRDY);
+	priv->regs.osc |= MCP25XXFD_OSC_OSCDIS;
+}
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/mcp25xxfd/mcp25xxfd_clock.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/mcp25xxfd/mcp25xxfd_clock.h
new file mode 100644
index 0000000000000000000000000000000000000000..049e95cfa9ad5f555d92895756ec848a12735db0
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/mcp25xxfd/mcp25xxfd_clock.h
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+/* CAN bus driver for Microchip 25XXFD CAN Controller with SPI Interface
+ *
+ * Copyright 2019 Martin Sperl <kernel@martin.sperl.org>
+ */
+
+#ifndef __MCP25XXFD_CLOCK_H
+#define __MCP25XXFD_CLOCK_H
+
+#include "mcp25xxfd_priv.h"
+
+#define MCP25XXFD_CLK_USER_CAN BIT(0)
+#define MCP25XXFD_CLK_USER_GPIO0 BIT(1)
+#define MCP25XXFD_CLK_USER_GPIO1 BIT(2)
+#define MCP25XXFD_CLK_USER_CLKOUT BIT(3)
+
+/* shared (internal) clock control */
+int mcp25xxfd_clock_init(struct mcp25xxfd_priv *priv);
+int mcp25xxfd_clock_probe(struct mcp25xxfd_priv *priv);
+void mcp25xxfd_clock_release(struct mcp25xxfd_priv *priv);
+
+int mcp25xxfd_clock_stop(struct mcp25xxfd_priv *priv, int requestor_mask);
+int mcp25xxfd_clock_start(struct mcp25xxfd_priv *priv, int requestor_mask);
+
+void mcp25xxfd_clock_fake_sleep(struct mcp25xxfd_priv *priv);
+
+#endif /* __MCP25XXFD_CLOCK_H */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/mcp25xxfd/mcp25xxfd_cmd.c b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/mcp25xxfd/mcp25xxfd_cmd.c
new file mode 100644
index 0000000000000000000000000000000000000000..0332189b4f07a22883ea00e9cf5c7a0a11d981e5
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/mcp25xxfd/mcp25xxfd_cmd.c
@@ -0,0 +1,312 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/* CAN bus driver for Microchip 25XXFD CAN Controller with SPI Interface
+ *
+ * Copyright 2019 Martin Sperl <kernel@martin.sperl.org>
+ */
+
+#include <linux/mutex.h>
+#include <linux/slab.h>
+#include <linux/spi/spi.h>
+
+#include "mcp25xxfd_cmd.h"
+#include "mcp25xxfd_priv.h"
+
+/* SPI helper */
+
+/* wrapper arround spi_sync, that sets speed_hz */
+static int mcp25xxfd_cmd_sync_transfer(struct spi_device *spi,
+				       struct spi_transfer *xfer,
+				       unsigned int xfers)
+{
+	struct mcp25xxfd_priv *priv = spi_get_drvdata(spi);
+	int i;
+
+	for (i = 0; i < xfers; i++)
+		xfer[i].speed_hz = priv->spi_use_speed_hz;
+
+	return spi_sync_transfer(spi, xfer, xfers);
+}
+
+/* simple spi_write wrapper with speed_hz
+ * WARINING: tx_buf needs to be on heap!
+ */
+static int mcp25xxfd_cmd_sync_write(struct spi_device *spi,
+				    const void *tx_buf,
+				    unsigned int tx_len)
+{
+	struct spi_transfer xfer;
+
+	memset(&xfer, 0, sizeof(xfer));
+	xfer.tx_buf = tx_buf;
+	xfer.len = tx_len;
+
+	return mcp25xxfd_cmd_sync_transfer(spi, &xfer, 1);
+}
+
+/* alloc buffer */
+static int mcp25xxfd_cmd_alloc_buf(struct spi_device *spi,
+				   size_t len,
+				   u8 **tx, u8 **rx)
+{
+	struct mcp25xxfd_priv *priv = spi_get_drvdata(spi);
+
+	/* allocate from heap in case the size is to big
+	 * or the preallocated buffer is already used (i.e locked)
+	 */
+	if (len > sizeof(priv->spi_tx) ||
+	    !mutex_trylock(&priv->spi_rxtx_lock)) {
+		/* allocate tx+rx in one allocation if rx is requested */
+		*tx = kzalloc(rx ? 2 * len : len, GFP_KERNEL);
+		if (!*tx)
+			return -ENOMEM;
+		if (rx)
+			*rx = *tx + len;
+	} else {
+		/* use the preallocated buffers instead */
+		*tx = priv->spi_tx;
+		memset(priv->spi_tx, 0, sizeof(priv->spi_tx));
+		if (rx) {
+			*rx = priv->spi_rx;
+			memset(priv->spi_rx, 0, sizeof(priv->spi_rx));
+		}
+	}
+
+	return 0;
+}
+
+static void mcp25xxfd_cmd_release_buf(struct spi_device *spi, u8 *tx, u8 *rx)
+{
+	struct mcp25xxfd_priv *priv = spi_get_drvdata(spi);
+
+	if (tx == priv->spi_tx)
+		mutex_unlock(&priv->spi_rxtx_lock);
+	else
+		kfree(tx);
+}
+
+/* an optimization of spi_write_then_read that merges the transfers
+ * this also makes sure that the data is ALWAYS on heap
+ */
+static int mcp25xxfd_cmd_write_then_read(struct spi_device *spi,
+					 const void *tx_buf,
+					 unsigned int tx_len,
+					 void *rx_buf,
+					 unsigned int rx_len)
+{
+	struct spi_transfer xfer[2];
+	u8 *spi_tx, *spi_rx;
+	int xfers;
+	int ret;
+
+	/* get pointer to buffers */
+	ret = mcp25xxfd_cmd_alloc_buf(spi, tx_len + rx_len, &spi_tx, &spi_rx);
+	if (ret)
+		return ret;
+
+	/* clear the xfers */
+	memset(xfer, 0, sizeof(xfer));
+
+	/* special handling for half-duplex */
+	if (spi->master->flags & SPI_MASTER_HALF_DUPLEX) {
+		xfers = 2;
+		xfer[0].tx_buf = spi_tx;
+		xfer[0].len = tx_len;
+		/* the offset for rx_buf needs to get aligned */
+		xfer[1].rx_buf = spi_rx + tx_len;
+		xfer[1].len = rx_len;
+	} else {
+		xfers = 1;
+		xfer[0].len = tx_len + rx_len;
+		xfer[0].tx_buf = spi_tx;
+		xfer[0].rx_buf = spi_rx;
+	}
+
+	/* copy data - especially to avoid buffers from stack */
+	memcpy(spi_tx, tx_buf, tx_len);
+
+	/* do the transfer */
+	ret = mcp25xxfd_cmd_sync_transfer(spi, xfer, xfers);
+	if (ret)
+		goto out;
+
+	/* copy result back */
+	memcpy(rx_buf, xfer[0].rx_buf + tx_len, rx_len);
+
+out:
+	mcp25xxfd_cmd_release_buf(spi, spi_tx, spi_rx);
+
+	return ret;
+}
+
+static int mcp25xxfd_cmd_write_then_write(struct spi_device *spi,
+					  const void *tx_buf,
+					  unsigned int tx_len,
+					  const void *tx2_buf,
+					  unsigned int tx2_len)
+{
+	struct spi_transfer xfer;
+	u8 *spi_tx;
+	int ret;
+
+	/* get pointer to buffers */
+	ret = mcp25xxfd_cmd_alloc_buf(spi, tx_len + tx2_len, &spi_tx, NULL);
+	if (ret)
+		return ret;
+
+	/* setup xfer */
+	memset(&xfer, 0, sizeof(xfer));
+	xfer.len = tx_len + tx2_len;
+	xfer.tx_buf = spi_tx;
+
+	/* copy data to correct location in buffer */
+	memcpy(spi_tx, tx_buf, tx_len);
+	memcpy(spi_tx + tx_len, tx2_buf, tx2_len);
+
+	/* run the transfer */
+	ret = mcp25xxfd_cmd_sync_transfer(spi, &xfer, 1);
+
+	mcp25xxfd_cmd_release_buf(spi, spi_tx, NULL);
+
+	return ret;
+}
+
+/* mcp25xxfd spi command/protocol helper */
+
+/* read multiple bytes, transform some registers */
+int mcp25xxfd_cmd_readn(struct spi_device *spi, u32 reg,
+			void *data, int n)
+{
+	u8 cmd[2];
+	int ret;
+
+	mcp25xxfd_cmd_calc(MCP25XXFD_INSTRUCTION_READ, reg, cmd);
+
+	ret = mcp25xxfd_cmd_write_then_read(spi, &cmd, 2, data, n);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
+/* read a register, but we are only interrested in a few bytes */
+int mcp25xxfd_cmd_read_mask(struct spi_device *spi, u32 reg,
+			    u32 *data, u32 mask)
+{
+	int first_byte, last_byte, len_byte;
+	int ret;
+
+	/* check that at least one bit is set */
+	if (!mask)
+		return -EINVAL;
+
+	/* calculate first and last byte used */
+	first_byte = mcp25xxfd_cmd_first_byte(mask);
+	last_byte = mcp25xxfd_cmd_last_byte(mask);
+	len_byte = last_byte - first_byte + 1;
+
+	/* do a partial read */
+	*data = 0;
+	ret = mcp25xxfd_cmd_readn(spi, reg + first_byte,
+				  ((void *)data + first_byte), len_byte);
+	if (ret)
+		return ret;
+
+	mcp25xxfd_cmd_convert_to_cpu(data, 1);
+
+	return 0;
+}
+
+int mcp25xxfd_cmd_writen(struct spi_device *spi, u32 reg,
+			 void *data, int n)
+{
+	u8 cmd[2];
+	int ret;
+
+	mcp25xxfd_cmd_calc(MCP25XXFD_INSTRUCTION_WRITE, reg, cmd);
+
+	ret = mcp25xxfd_cmd_write_then_write(spi, &cmd, 2, data, n);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
+/* read a register, but we are only interrested in a few bytes */
+int mcp25xxfd_cmd_write_mask(struct spi_device *spi, u32 reg,
+			     u32 data, u32 mask)
+{
+	int first_byte, last_byte, len_byte;
+	u8 cmd[2];
+
+	/* check that at least one bit is set */
+	if (!mask)
+		return -EINVAL;
+
+	/* calculate first and last byte used */
+	first_byte = mcp25xxfd_cmd_first_byte(mask);
+	last_byte = mcp25xxfd_cmd_last_byte(mask);
+	len_byte = last_byte - first_byte + 1;
+
+	/* prepare buffer */
+	mcp25xxfd_cmd_calc(MCP25XXFD_INSTRUCTION_WRITE,
+			   reg + first_byte, cmd);
+
+	mcp25xxfd_cmd_convert_from_cpu(&data, 1);
+
+	return mcp25xxfd_cmd_write_then_write(spi,
+					      cmd, sizeof(cmd),
+					      ((void *)&data + first_byte),
+					      len_byte);
+}
+
+int mcp25xxfd_cmd_write_regs(struct spi_device *spi, u32 reg,
+			     u32 *data, u32 bytes)
+{
+	int ret;
+
+	/* first transpose to controller format */
+	mcp25xxfd_cmd_convert_from_cpu(data, bytes / sizeof(bytes));
+
+	/* now write it */
+	ret = mcp25xxfd_cmd_writen(spi, reg, data, bytes);
+
+	/* and convert it back to cpu format even if it fails */
+	mcp25xxfd_cmd_convert_to_cpu(data, bytes / sizeof(bytes));
+
+	return ret;
+}
+
+int mcp25xxfd_cmd_read_regs(struct spi_device *spi, u32 reg,
+			    u32 *data, u32 bytes)
+{
+	int ret;
+
+	/* read it */
+	ret = mcp25xxfd_cmd_readn(spi, reg, data, bytes);
+
+	/* and convert it to cpu format */
+	mcp25xxfd_cmd_convert_to_cpu((u32 *)data, bytes / sizeof(bytes));
+
+	return ret;
+}
+
+int mcp25xxfd_cmd_reset(struct spi_device *spi)
+{
+	u8 *cmd;
+	int ret;
+
+	/* allocate 2 bytes on heap, as we use sync_write */
+	cmd = kzalloc(2, GFP_KERNEL);
+	if (!cmd)
+		return -ENOMEM;
+
+	mcp25xxfd_cmd_calc(MCP25XXFD_INSTRUCTION_RESET, 0, cmd);
+
+	/* write the reset command */
+	ret = mcp25xxfd_cmd_sync_write(spi, cmd, 2);
+
+	kfree(cmd);
+
+	return ret;
+}
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/mcp25xxfd/mcp25xxfd_cmd.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/mcp25xxfd/mcp25xxfd_cmd.h
new file mode 100644
index 0000000000000000000000000000000000000000..de61db093a8e0197eb3e2a0ddd1265c6da6b9f05
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/mcp25xxfd/mcp25xxfd_cmd.h
@@ -0,0 +1,104 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+/* CAN bus driver for Microchip 25XXFD CAN Controller with SPI Interface
+ *
+ * Copyright 2019 Martin Sperl <kernel@martin.sperl.org>
+ */
+
+#ifndef __MCP25XXFD_CMD_H
+#define __MCP25XXFD_CMD_H
+
+#include <linux/byteorder/generic.h>
+#include <linux/spi/spi.h>
+#include <linux/version.h>
+
+/* SPI commands */
+#define MCP25XXFD_INSTRUCTION_RESET		0x0000
+#define MCP25XXFD_INSTRUCTION_READ		0x3000
+#define MCP25XXFD_INSTRUCTION_WRITE		0x2000
+#define MCP25XXFD_INSTRUCTION_READ_CRC		0xB000
+#define MCP25XXFD_INSTRUCTION_WRITE_CRC		0xA000
+#define MCP25XXFD_INSTRUCTION_WRITE_SAVE	0xC000
+
+#define MCP25XXFD_ADDRESS_MASK			0x0fff
+#if LINUX_VERSION_CODE < KERNEL_VERSION(4,18,0)
+/* XXX: this stuff can be optimized */
+static inline void le32_to_cpu_array(u32 *buf, unsigned int words)
+{
+	while (words--) {
+		__le32_to_cpus(buf);
+		buf++;
+	}
+}
+
+static inline void cpu_to_le32_array(u32 *buf, unsigned int words)
+{
+	while (words--) {
+		__cpu_to_le32s(buf);
+		buf++;
+	}
+}
+
+#endif
+
+static inline void mcp25xxfd_cmd_convert_to_cpu(u32 *data, int n)
+{
+	le32_to_cpu_array(data, n);
+}
+
+static inline void mcp25xxfd_cmd_convert_from_cpu(u32 *data, int n)
+{
+	cpu_to_le32_array(data, n);
+}
+
+static inline void mcp25xxfd_cmd_calc(u16 cmd, u16 addr, u8 *data)
+{
+	cmd = cmd | (addr & MCP25XXFD_ADDRESS_MASK);
+
+	data[0] = (cmd >> 8) & 0xff;
+	data[1] = (cmd >> 0) & 0xff;
+}
+
+static inline int mcp25xxfd_cmd_first_byte(u32 mask)
+{
+	return (mask & 0x0000ffff) ?
+		((mask & 0x000000ff) ? 0 : 1) :
+		((mask & 0x00ff0000) ? 2 : 3);
+}
+
+static inline int mcp25xxfd_cmd_last_byte(u32 mask)
+{
+	return (mask & 0xffff0000) ?
+		((mask & 0xff000000) ? 3 : 2) :
+		((mask & 0x0000ff00) ? 1 : 0);
+}
+
+int mcp25xxfd_cmd_readn(struct spi_device *spi, u32 reg,
+			void *data, int n);
+int mcp25xxfd_cmd_read_mask(struct spi_device *spi, u32 reg,
+			    u32 *data, u32 mask);
+static inline int mcp25xxfd_cmd_read(struct spi_device *spi, u32 reg,
+				     u32 *data)
+{
+	return mcp25xxfd_cmd_read_mask(spi, reg, data, -1);
+}
+
+int mcp25xxfd_cmd_read_regs(struct spi_device *spi, u32 reg,
+			    u32 *data, u32 bytes);
+
+int mcp25xxfd_cmd_writen(struct spi_device *spi, u32 reg,
+			 void *data, int n);
+int mcp25xxfd_cmd_write_mask(struct spi_device *spi, u32 reg,
+			     u32 data, u32 mask);
+static inline int mcp25xxfd_cmd_write(struct spi_device *spi, u32 reg,
+				      u32 data)
+{
+	return mcp25xxfd_cmd_write_mask(spi, reg, data, -1);
+}
+
+int mcp25xxfd_cmd_write_regs(struct spi_device *spi, u32 reg,
+			     u32 *data, u32 bytes);
+
+int mcp25xxfd_cmd_reset(struct spi_device *spi);
+
+#endif /* __MCP25XXFD_CMD_H */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/mcp25xxfd/mcp25xxfd_crc.c b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/mcp25xxfd/mcp25xxfd_crc.c
new file mode 100644
index 0000000000000000000000000000000000000000..b893d800944810babf12f5d82c0057464e126357
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/mcp25xxfd/mcp25xxfd_crc.c
@@ -0,0 +1,31 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/* CAN bus driver for Microchip 25XXFD CAN Controller with SPI Interface
+ *
+ * Copyright 2019 Martin Sperl <kernel@martin.sperl.org>
+ */
+
+#include <linux/kernel.h>
+#include <linux/spi/spi.h>
+#include "mcp25xxfd_cmd.h"
+#include "mcp25xxfd_crc.h"
+#include "mcp25xxfd_regs.h"
+#include "mcp25xxfd_priv.h"
+
+int mcp25xxfd_crc_enable_int(struct mcp25xxfd_priv *priv, bool enable)
+{
+	u32 mask = MCP25XXFD_CRC_CRCERRIE | MCP25XXFD_CRC_FERRIE;
+
+	priv->regs.crc &= ~mask;
+	priv->regs.crc |= enable ? mask : 0;
+
+	return mcp25xxfd_cmd_write_mask(priv->spi, MCP25XXFD_CRC,
+					priv->regs.crc, mask);
+}
+
+int mcp25xxfd_crc_clear_int(struct mcp25xxfd_priv *priv)
+{
+	return mcp25xxfd_cmd_write_mask(priv->spi, MCP25XXFD_CRC, 0,
+					MCP25XXFD_CRC_CRCERRIF |
+					MCP25XXFD_CRC_FERRIF);
+}
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/mcp25xxfd/mcp25xxfd_crc.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/mcp25xxfd/mcp25xxfd_crc.h
new file mode 100644
index 0000000000000000000000000000000000000000..6e42fe0fad0f21a4bb8c65c423cd90837d449624
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/mcp25xxfd/mcp25xxfd_crc.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+/* CAN bus driver for Microchip 25XXFD CAN Controller with SPI Interface
+ *
+ * Copyright 2019 Martin Sperl <kernel@martin.sperl.org>
+ */
+#ifndef __MCP25XXFD_CRC_H
+#define __MCP25XXFD_CRC_H
+
+#include "mcp25xxfd_priv.h"
+
+int mcp25xxfd_crc_enable_int(struct mcp25xxfd_priv *priv, bool enable);
+int mcp25xxfd_crc_clear_int(struct mcp25xxfd_priv *priv);
+
+#endif /* __MCP25XXFD_CRC_H */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/mcp25xxfd/mcp25xxfd_debugfs.c b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/mcp25xxfd/mcp25xxfd_debugfs.c
new file mode 100644
index 0000000000000000000000000000000000000000..92ee4d737f847a7103ba045cac775499952bf516
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/mcp25xxfd/mcp25xxfd_debugfs.c
@@ -0,0 +1,110 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/* CAN bus driver for Microchip 25XXFD CAN Controller with SPI Interface
+ *
+ * Copyright 2019 Martin Sperl <kernel@martin.sperl.org>
+ */
+
+#ifdef CONFIG_DEBUG_FS
+
+#include <linux/debugfs.h>
+#include <linux/kernel.h>
+#include <linux/seq_file.h>
+
+#include "mcp25xxfd_cmd.h"
+#include "mcp25xxfd_debugfs.h"
+#include "mcp25xxfd_priv.h"
+
+static int mcp25xxfd_debugfs_dump_regs_range(struct seq_file *file,
+					     u32 start, u32 end)
+{
+	struct spi_device *spi = file->private;
+	u32 data[32];
+	int bytes = end - start + sizeof(*data);
+	int i, l, count, ret;
+
+	for (count =  bytes / sizeof(*data); count > 0; count -= 32) {
+		/* read up to 32 registers in one go */
+		l = min(count, 32);
+		ret = mcp25xxfd_cmd_read_regs(spi, start,
+					      data, l * sizeof(*data));
+		if (ret)
+			return ret;
+		/* dump those read registers */
+		for (i = 0; i < l; i++, start += sizeof(*data))
+			seq_printf(file, "Reg 0x%03x = 0x%08x\n",
+				   start, data[i]);
+	}
+
+	return 0;
+}
+
+static int mcp25xxfd_debugfs_dump_regs(struct seq_file *file, void *offset)
+{
+	return mcp25xxfd_debugfs_dump_regs_range(file, MCP25XXFD_OSC,
+						 MCP25XXFD_ECCSTAT);
+}
+
+static int mcp25xxfd_debugfs_dump_can_regs(struct seq_file *file,
+					   void *offset)
+{
+	return mcp25xxfd_debugfs_dump_regs_range(file, MCP25XXFD_CAN_CON,
+						 MCP25XXFD_CAN_TXQUA);
+}
+
+static int mcp25xxfd_debugfs_dump_can_all_regs(struct seq_file *file,
+					       void *offset)
+{
+	return mcp25xxfd_debugfs_dump_regs_range(file, MCP25XXFD_CAN_CON,
+						 MCP25XXFD_CAN_FLTMASK(31));
+}
+
+static void mcp25xxfd_debugfs_mod_setup(struct mcp25xxfd_priv *priv)
+{
+	struct dentry *root, *regs;
+
+	/* the base directory */
+	priv->debugfs_dir = debugfs_create_dir(priv->device_name, NULL);
+	root = priv->debugfs_dir;
+
+	/* expose some parameters related to clocks */
+	debugfs_create_u32("spi_setup_speed_hz", 0444, root,
+			   &priv->spi_setup_speed_hz);
+	debugfs_create_u32("spi_normal_speed_hz", 0444, root,
+			   &priv->spi_normal_speed_hz);
+	debugfs_create_u32("spi_use_speed_hz", 0444, root,
+			   &priv->spi_use_speed_hz);
+	debugfs_create_u32("clk_user_mask", 0444, root, &priv->clk_user_mask);
+
+	/* expose the system registers */
+	priv->debugfs_regs_dir = debugfs_create_dir("regs", root);
+	regs = priv->debugfs_regs_dir;
+	debugfs_create_x32("osc", 0444, regs, &priv->regs.osc);
+	debugfs_create_x32("iocon", 0444, regs, &priv->regs.iocon);
+	debugfs_create_x32("crc", 0444, regs, &priv->regs.crc);
+	debugfs_create_x32("ecccon", 0444, regs, &priv->regs.ecccon);
+
+	/* dump the controller registers themselves */
+	debugfs_create_devm_seqfile(&priv->spi->dev, "regs_live_dump",
+				    root, mcp25xxfd_debugfs_dump_regs);
+	/* and the essential can registers */
+	debugfs_create_devm_seqfile(&priv->spi->dev, "can_regs_live_dump",
+				    root, mcp25xxfd_debugfs_dump_can_regs);
+	/* and the complete can registers */
+	debugfs_create_devm_seqfile(&priv->spi->dev,
+				    "can_regs_all_live_dump", root,
+				    mcp25xxfd_debugfs_dump_can_all_regs);
+}
+
+void mcp25xxfd_debugfs_setup(struct mcp25xxfd_priv *priv)
+{
+	mcp25xxfd_debugfs_mod_setup(priv);
+}
+
+void mcp25xxfd_debugfs_remove(struct mcp25xxfd_priv *priv)
+{
+	debugfs_remove_recursive(priv->debugfs_dir);
+	priv->debugfs_dir = NULL;
+}
+
+#endif /* CONFIG_DEBUG_FS */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/mcp25xxfd/mcp25xxfd_debugfs.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/mcp25xxfd/mcp25xxfd_debugfs.h
new file mode 100644
index 0000000000000000000000000000000000000000..800672442ffbe2bf84817cd93d273fd7c71733ce
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/mcp25xxfd/mcp25xxfd_debugfs.h
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+/* CAN bus driver for Microchip 25XXFD CAN Controller with SPI Interface
+ *
+ * Copyright 2019 Martin Sperl <kernel@martin.sperl.org>
+ */
+
+#ifndef __MCP25XXFD_DEBUGFS_H
+#define __MCP25XXFD_DEBUGFS_H
+
+#include "mcp25xxfd_priv.h"
+
+#ifdef CONFIG_DEBUG_FS
+
+void mcp25xxfd_debugfs_setup(struct mcp25xxfd_priv *priv);
+void mcp25xxfd_debugfs_remove(struct mcp25xxfd_priv *priv);
+
+#else
+
+static inline void mcp25xxfd_debugfs_setup(struct mcp25xxfd_priv *priv)
+{
+	return 0;
+}
+
+static inline void mcp25xxfd_debugfs_remove(struct mcp25xxfd_priv *priv)
+{
+}
+
+#endif /* CONFIG_DEBUG_FS */
+#endif /* __MCP25XXFD_DEBUGFS_H */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/mcp25xxfd/mcp25xxfd_ecc.c b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/mcp25xxfd/mcp25xxfd_ecc.c
new file mode 100644
index 0000000000000000000000000000000000000000..526f345d0a17f984c5774c44355d339dd59734c6
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/mcp25xxfd/mcp25xxfd_ecc.c
@@ -0,0 +1,75 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/* CAN bus driver for Microchip 25XXFD CAN Controller with SPI Interface
+ *
+ * Copyright 2019 Martin Sperl <kernel@martin.sperl.org>
+ */
+
+#include <linux/kernel.h>
+#include <linux/spi/spi.h>
+#include "mcp25xxfd_cmd.h"
+#include "mcp25xxfd_ecc.h"
+#include "mcp25xxfd_priv.h"
+#include "mcp25xxfd_regs.h"
+
+int mcp25xxfd_ecc_clear_int(struct mcp25xxfd_priv *priv)
+{
+	u32 val, addr;
+	int ret;
+
+	/* first report the error address */
+	ret = mcp25xxfd_cmd_read(priv->spi, MCP25XXFD_ECCSTAT, &val);
+	if (ret)
+		return ret;
+
+	/* if no flags are set then nothing to do */
+	if (!(val & (MCP25XXFD_ECCSTAT_SECIF | MCP25XXFD_ECCSTAT_DEDIF)))
+		return 0;
+
+	addr = (val & MCP25XXFD_ECCSTAT_ERRADDR_MASK) >>
+		MCP25XXFD_ECCSTAT_ERRADDR_SHIFT;
+
+	dev_err_ratelimited(&priv->spi->dev, "ECC %s bit error at %03x\n",
+			    (val & MCP25XXFD_ECCSTAT_DEDIF) ?
+			    "double" : "single",
+			    addr);
+
+	/* and clear the error */
+	return mcp25xxfd_cmd_write_mask(priv->spi, MCP25XXFD_ECCSTAT, 0,
+					MCP25XXFD_ECCSTAT_SECIF |
+					MCP25XXFD_ECCSTAT_DEDIF);
+}
+
+int mcp25xxfd_ecc_enable_int(struct mcp25xxfd_priv *priv, bool enable)
+{
+	u32 mask = MCP25XXFD_ECCCON_SECIE | MCP25XXFD_ECCCON_DEDIE;
+
+	priv->regs.ecccon &= ~mask;
+	priv->regs.ecccon |= MCP25XXFD_ECCCON_ECCEN | (enable ? mask : 0);
+
+	return mcp25xxfd_cmd_write_mask(priv->spi, MCP25XXFD_ECCCON,
+					priv->regs.ecccon,
+					MCP25XXFD_ECCCON_ECCEN | mask);
+}
+
+int mcp25xxfd_ecc_enable(struct mcp25xxfd_priv *priv)
+{
+	u8 buffer[256];
+	int i, ret;
+
+	/* set up RAM ECC - enable interrupts sets it as well */
+	ret = mcp25xxfd_ecc_enable_int(priv, false);
+	if (ret)
+		return ret;
+
+	/* and clear SRAM so that no reads fails from now on */
+	memset(buffer, 0, sizeof(buffer));
+	for (i = 0; i < MCP25XXFD_SRAM_SIZE; i += sizeof(buffer)) {
+		ret = mcp25xxfd_cmd_writen(priv->spi, MCP25XXFD_SRAM_ADDR(i),
+					   buffer, sizeof(buffer));
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+}
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/mcp25xxfd/mcp25xxfd_ecc.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/mcp25xxfd/mcp25xxfd_ecc.h
new file mode 100644
index 0000000000000000000000000000000000000000..117f58c65a46ce6fafe8c13fd730af57a4eb7277
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/mcp25xxfd/mcp25xxfd_ecc.h
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+/* CAN bus driver for Microchip 25XXFD CAN Controller with SPI Interface
+ *
+ * Copyright 2019 Martin Sperl <kernel@martin.sperl.org>
+ */
+#ifndef __MCP25XXFD_ECC_H
+#define __MCP25XXFD_ECC_H
+
+#include "mcp25xxfd_priv.h"
+
+int mcp25xxfd_ecc_clear_int(struct mcp25xxfd_priv *priv);
+int mcp25xxfd_ecc_enable_int(struct mcp25xxfd_priv *priv, bool enable);
+int mcp25xxfd_ecc_enable(struct mcp25xxfd_priv *priv);
+
+#endif /* __MCP25XXFD_ECC_H */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/mcp25xxfd/mcp25xxfd_gpio.c b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/mcp25xxfd/mcp25xxfd_gpio.c
new file mode 100644
index 0000000000000000000000000000000000000000..69eb9c6ef176fb7f7a93834e7c4f21042450879b
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/mcp25xxfd/mcp25xxfd_gpio.c
@@ -0,0 +1,194 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/* CAN bus driver for Microchip 25XXFD CAN Controller with SPI Interface
+ *
+ * Copyright 2019 Martin Sperl <kernel@martin.sperl.org>
+ *
+ * Based on Microchip MCP251x CAN controller driver written by
+ * David Vrabel, Copyright 2006 Arcom Control Systems Ltd.
+ */
+
+#include <linux/gpio/driver.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/slab.h>
+
+#include "mcp25xxfd_clock.h"
+#include "mcp25xxfd_cmd.h"
+#include "mcp25xxfd_priv.h"
+
+/* GPIO component */
+#ifdef CONFIG_GPIOLIB
+
+enum mcp25xxfd_gpio_pins {
+	MCP25XXFD_GPIO_GPIO0 = 0,
+	MCP25XXFD_GPIO_GPIO1 = 1,
+};
+
+static int mcp25xxfd_gpio_request(struct gpio_chip *chip,
+				  unsigned int offset)
+{
+	struct mcp25xxfd_priv *priv = gpiochip_get_data(chip);
+	int clock_requestor = offset ?
+		MCP25XXFD_CLK_USER_GPIO1 : MCP25XXFD_CLK_USER_GPIO0;
+
+	/* only handle gpio 0/1 */
+	if (offset > 1)
+		return -EINVAL;
+
+	mcp25xxfd_clock_start(priv, clock_requestor);
+
+	return 0;
+}
+
+static void mcp25xxfd_gpio_free(struct gpio_chip *chip,
+				unsigned int offset)
+{
+	struct mcp25xxfd_priv *priv = gpiochip_get_data(chip);
+	int clock_requestor = offset ?
+		MCP25XXFD_CLK_USER_GPIO1 : MCP25XXFD_CLK_USER_GPIO0;
+
+	/* only handle gpio 0/1 */
+	if (offset > 1)
+		return;
+
+	mcp25xxfd_clock_stop(priv, clock_requestor);
+}
+
+static int mcp25xxfd_gpio_get(struct gpio_chip *chip, unsigned int offset)
+{
+	struct mcp25xxfd_priv *priv = gpiochip_get_data(chip);
+	u32 mask = (offset) ? MCP25XXFD_IOCON_GPIO1 : MCP25XXFD_IOCON_GPIO0;
+	int ret;
+
+	/* only handle gpio 0/1 */
+	if (offset > 1)
+		return -EINVAL;
+
+	/* read the relevant gpio Latch */
+	ret = mcp25xxfd_cmd_read_mask(priv->spi, MCP25XXFD_IOCON,
+				      &priv->regs.iocon, mask);
+	if (ret)
+		return ret;
+
+	/* return the match */
+	return priv->regs.iocon & mask;
+}
+
+static void mcp25xxfd_gpio_set(struct gpio_chip *chip, unsigned int offset,
+			       int value)
+{
+	struct mcp25xxfd_priv *priv = gpiochip_get_data(chip);
+	u32 mask = (offset) ? MCP25XXFD_IOCON_LAT1 : MCP25XXFD_IOCON_LAT0;
+
+	/* only handle gpio 0/1 */
+	if (offset > 1)
+		return;
+
+	/* update in memory representation with the corresponding value */
+	if (value)
+		priv->regs.iocon |= mask;
+	else
+		priv->regs.iocon &= ~mask;
+
+	mcp25xxfd_cmd_write_mask(priv->spi, MCP25XXFD_IOCON,
+				 priv->regs.iocon, mask);
+}
+
+static int mcp25xxfd_gpio_direction_input(struct gpio_chip *chip,
+					  unsigned int offset)
+{
+	struct mcp25xxfd_priv *priv = gpiochip_get_data(chip);
+	u32 mask_tri = (offset) ?
+		MCP25XXFD_IOCON_TRIS1 : MCP25XXFD_IOCON_TRIS0;
+	u32 mask_stby = (offset) ?
+		0 : MCP25XXFD_IOCON_XSTBYEN;
+	u32 mask_pm = (offset) ?
+		MCP25XXFD_IOCON_PM1 : MCP25XXFD_IOCON_PM0;
+
+	/* only handle gpio 0/1 */
+	if (offset > 1)
+		return -EINVAL;
+
+	/* set the mask */
+	priv->regs.iocon |= mask_tri | mask_pm;
+
+	/* clear stby */
+	priv->regs.iocon &= ~mask_stby;
+
+	return mcp25xxfd_cmd_write_mask(priv->spi, MCP25XXFD_IOCON,
+					priv->regs.iocon,
+					mask_tri | mask_stby | mask_pm);
+}
+
+static int mcp25xxfd_gpio_direction_output(struct gpio_chip *chip,
+					   unsigned int offset, int value)
+{
+	struct mcp25xxfd_priv *priv = gpiochip_get_data(chip);
+	u32 mask_tri = (offset) ?
+		MCP25XXFD_IOCON_TRIS1 : MCP25XXFD_IOCON_TRIS0;
+	u32 mask_lat = (offset) ?
+		MCP25XXFD_IOCON_LAT1 : MCP25XXFD_IOCON_LAT0;
+	u32 mask_pm = (offset) ?
+		MCP25XXFD_IOCON_PM1 : MCP25XXFD_IOCON_PM0;
+	u32 mask_stby = (offset) ?
+		0 : MCP25XXFD_IOCON_XSTBYEN;
+
+	/* only handle gpio 0/1 */
+	if (offset > 1)
+		return -EINVAL;
+
+	/* clear the tristate bit and also clear stby */
+	priv->regs.iocon &= ~(mask_tri | mask_stby);
+
+	/* set GPIO mode */
+	priv->regs.iocon |= mask_pm;
+
+	/* set the value */
+	if (value)
+		priv->regs.iocon |= mask_lat;
+	else
+		priv->regs.iocon &= ~mask_lat;
+
+	return mcp25xxfd_cmd_write_mask(priv->spi, MCP25XXFD_IOCON,
+					priv->regs.iocon,
+					mask_tri | mask_lat |
+					mask_pm | mask_stby);
+}
+
+int mcp25xxfd_gpio_setup(struct mcp25xxfd_priv *priv)
+{
+	struct gpio_chip *gpio = &priv->gpio;
+
+	/* gpiochip only handles GPIO0 and GPIO1 */
+	gpio->owner                = THIS_MODULE;
+	gpio->parent               = &priv->spi->dev;
+	gpio->label                = dev_name(&priv->spi->dev);
+	gpio->direction_input      = mcp25xxfd_gpio_direction_input;
+	gpio->get                  = mcp25xxfd_gpio_get;
+	gpio->direction_output     = mcp25xxfd_gpio_direction_output;
+	gpio->set                  = mcp25xxfd_gpio_set;
+	gpio->request              = mcp25xxfd_gpio_request;
+	gpio->free                 = mcp25xxfd_gpio_free;
+	gpio->base                 = -1;
+	gpio->ngpio                = 2;
+	gpio->can_sleep            = 1;
+
+	return gpiochip_add_data(gpio, priv);
+}
+
+void mcp25xxfd_gpio_remove(struct mcp25xxfd_priv *priv)
+{
+	gpiochip_remove(&priv->gpio);
+}
+
+#else
+int mcp25xxfd_gpio_setup(struct mcp25xxfd_priv *priv)
+{
+	return 0;
+}
+
+void mcp25xxfd_gpio_remove(struct mcp25xxfd_priv *priv)
+{
+}
+#endif
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/mcp25xxfd/mcp25xxfd_gpio.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/mcp25xxfd/mcp25xxfd_gpio.h
new file mode 100644
index 0000000000000000000000000000000000000000..46740e8abc458e6433f757dab8ac65c976c8269c
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/mcp25xxfd/mcp25xxfd_gpio.h
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+/* CAN bus driver for Microchip 25XXFD CAN Controller with SPI Interface
+ *
+ * Copyright 2019 Martin Sperl <kernel@martin.sperl.org>
+ */
+#ifndef __MCP25XXFD_GPIO_H
+#define __MCP25XXFD_GPIO_H
+
+#include "mcp25xxfd_priv.h"
+
+/* gpiolib support */
+int mcp25xxfd_gpio_setup(struct mcp25xxfd_priv *priv);
+void mcp25xxfd_gpio_remove(struct mcp25xxfd_priv *priv);
+
+#endif /* __MCP25XXFD_GPIO_H */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/mcp25xxfd/mcp25xxfd_int.c b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/mcp25xxfd/mcp25xxfd_int.c
new file mode 100644
index 0000000000000000000000000000000000000000..cca9c996b542d8347144a78b261ba48061235400
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/mcp25xxfd/mcp25xxfd_int.c
@@ -0,0 +1,73 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/* CAN bus driver for Microchip 25XXFD CAN Controller with SPI Interface
+ *
+ * Copyright 2019 Martin Sperl <kernel@martin.sperl.org>
+ */
+
+#include <linux/kernel.h>
+#include <linux/spi/spi.h>
+
+#include "mcp25xxfd_can_int.h"
+#include "mcp25xxfd_crc.h"
+#include "mcp25xxfd_ecc.h"
+#include "mcp25xxfd_int.h"
+#include "mcp25xxfd_priv.h"
+
+int mcp25xxfd_int_clear(struct mcp25xxfd_priv *priv)
+{
+	int ret;
+
+	ret = mcp25xxfd_ecc_clear_int(priv);
+	if (ret)
+		return ret;
+	ret = mcp25xxfd_crc_clear_int(priv);
+	if (ret)
+		return ret;
+	ret = mcp25xxfd_can_int_clear(priv);
+
+	return ret;
+}
+
+int mcp25xxfd_int_enable(struct mcp25xxfd_priv *priv, bool enable)
+{
+	/* error handling only on enable for this function */
+	int ret = 0;
+
+	/* if we enable clear interrupt flags first */
+	if (enable) {
+		ret = mcp25xxfd_int_clear(priv);
+		if (ret)
+			goto out;
+	}
+
+	ret = mcp25xxfd_crc_enable_int(priv, enable);
+	if (ret)
+		goto out;
+
+	ret = mcp25xxfd_ecc_enable(priv);
+	if (ret)
+		goto out_crc;
+
+	ret = mcp25xxfd_ecc_enable_int(priv, enable);
+	if (ret)
+		goto out_crc;
+
+	ret = mcp25xxfd_can_int_enable(priv, enable);
+	if (ret)
+		goto out_ecc;
+
+	/* if we disable interrupts clear interrupt flags last */
+	if (!enable)
+		mcp25xxfd_int_clear(priv);
+
+	return 0;
+
+out_ecc:
+	mcp25xxfd_ecc_enable_int(priv, false);
+
+out_crc:
+	mcp25xxfd_crc_enable_int(priv, false);
+out:
+	return ret;
+}
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/mcp25xxfd/mcp25xxfd_int.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/mcp25xxfd/mcp25xxfd_int.h
new file mode 100644
index 0000000000000000000000000000000000000000..4daf0182d1afff873780229f21d62c00956a4402
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/mcp25xxfd/mcp25xxfd_int.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+/* CAN bus driver for Microchip 25XXFD CAN Controller with SPI Interface
+ *
+ * Copyright 2019 Martin Sperl <kernel@martin.sperl.org>
+ */
+#ifndef __MCP25XXFD_INT_H
+#define __MCP25XXFD_INT_H
+
+#include "mcp25xxfd_priv.h"
+
+int mcp25xxfd_int_clear(struct mcp25xxfd_priv *priv);
+int mcp25xxfd_int_enable(struct mcp25xxfd_priv *priv, bool enable);
+
+#endif /* __MCP25XXFD_INT_H */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/mcp25xxfd/mcp25xxfd_priv.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/mcp25xxfd/mcp25xxfd_priv.h
new file mode 100644
index 0000000000000000000000000000000000000000..e95a8eef70d87ceca593d755ca1688ad7dfed70e
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/mcp25xxfd/mcp25xxfd_priv.h
@@ -0,0 +1,83 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+/* CAN bus driver for Microchip 25XXFD CAN Controller with SPI Interface
+ *
+ * Copyright 2019 Martin Sperl <kernel@martin.sperl.org>
+ */
+#ifndef __MCP25XXFD_PRIV_H
+#define __MCP25XXFD_PRIV_H
+
+#include <linux/clk.h>
+#include <linux/debugfs.h>
+#include <linux/gpio/driver.h>
+#include <linux/mutex.h>
+#include <linux/regulator/consumer.h>
+#include <linux/spi/spi.h>
+
+#include "mcp25xxfd_regs.h"
+
+/* some defines for the driver */
+#define DEVICE_NAME "mcp25xxfd"
+
+enum mcp25xxfd_model {
+	CAN_MCP2517FD	= 0x2517,
+};
+
+struct mcp25xxfd_can_priv;
+struct mcp25xxfd_priv {
+	struct spi_device *spi;
+	struct clk *clk;
+	struct gpio_chip gpio;
+	struct mcp25xxfd_can_priv *cpriv;
+
+	/* the actual model of the mcp25xxfd */
+	enum mcp25xxfd_model model;
+
+	/* full device name used for debugfs ant interrupts */
+	char device_name[32];
+
+	/* everything clock related */
+	int clock_freq;
+	struct {
+		/* clock configuration */
+		int clock_pll;
+		int clock_div2;
+		int clock_odiv;
+	} config;
+
+	/* lock for enabling/disabling the clock */
+	struct mutex clk_user_lock;
+	u32 clk_user_mask;
+	u32 clk_sleep_mask;
+
+	/* power related */
+	struct regulator *power;
+
+	/* the distinct spi_speeds to use for spi communication */
+	u32 spi_setup_speed_hz;
+	u32 spi_normal_speed_hz;
+	u32 spi_use_speed_hz;
+
+	/* spi-tx/rx buffers for efficient transfers
+	 * used during setup and irq
+	 */
+	struct mutex spi_rxtx_lock; /* protects use of spi_tx/rx */
+	u8 spi_tx[MCP25XXFD_SRAM_SIZE];
+	u8 spi_rx[MCP25XXFD_SRAM_SIZE];
+
+	/* configuration registers */
+	struct {
+		u32 osc;
+		u32 iocon;
+		u32 crc;
+		u32 ecccon;
+	} regs;
+
+	/* debugfs related */
+#if defined(CONFIG_DEBUG_FS)
+	struct dentry *debugfs_dir;
+	struct dentry *debugfs_regs_dir;
+#endif
+};
+
+#endif /* __MCP25XXFD_PRIV_H */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/mcp25xxfd/mcp25xxfd_regs.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/mcp25xxfd/mcp25xxfd_regs.h
new file mode 100644
index 0000000000000000000000000000000000000000..222527439c70dcfc5e8f7a5804eec81a92d0cb86
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/mcp25xxfd/mcp25xxfd_regs.h
@@ -0,0 +1,661 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+/* CAN bus driver for Microchip 25XXFD CAN Controller with SPI Interface
+ *
+ * Copyright 2019 Martin Sperl <kernel@martin.sperl.org>
+ */
+
+#ifndef __MCP25XXFD_REGS_H
+#define __MCP25XXFD_REGS_H
+
+#include <linux/bitops.h>
+
+/* some constants derived from the datasheets */
+#define MCP25XXFD_OST_DELAY_MS		3
+#define MCP25XXFD_MIN_CLOCK_FREQUENCY	1000000
+#define MCP25XXFD_MAX_CLOCK_FREQUENCY	40000000
+#define MCP25XXFD_PLL_MULTIPLIER	10
+#define MCP25XXFD_AUTO_PLL_MAX_CLOCK_FREQUENCY				\
+	(MCP25XXFD_MAX_CLOCK_FREQUENCY / MCP25XXFD_PLL_MULTIPLIER)
+#define MCP25XXFD_SCLK_DIVIDER		2
+
+/* GPIO, clock, ecc related register definitions of Controller itself */
+#define MCP25XXFD_SFR_BASE(x)			(0xE00 + (x))
+#define MCP25XXFD_OSC				MCP25XXFD_SFR_BASE(0x00)
+#  define MCP25XXFD_OSC_PLLEN			BIT(0)
+#  define MCP25XXFD_OSC_OSCDIS			BIT(2)
+#  define MCP25XXFD_OSC_SCLKDIV			BIT(4)
+#  define MCP25XXFD_OSC_CLKODIV_BITS		2
+#  define MCP25XXFD_OSC_CLKODIV_SHIFT		5
+#  define MCP25XXFD_OSC_CLKODIV_MASK					\
+	GENMASK(MCP25XXFD_OSC_CLKODIV_SHIFT				\
+		+ MCP25XXFD_OSC_CLKODIV_BITS - 1,			\
+		MCP25XXFD_OSC_CLKODIV_SHIFT)
+#  define MCP25XXFD_OSC_CLKODIV_10		3
+#  define MCP25XXFD_OSC_CLKODIV_4		2
+#  define MCP25XXFD_OSC_CLKODIV_2		1
+#  define MCP25XXFD_OSC_CLKODIV_1		0
+#  define MCP25XXFD_OSC_PLLRDY			BIT(8)
+#  define MCP25XXFD_OSC_OSCRDY			BIT(10)
+#  define MCP25XXFD_OSC_SCLKRDY			BIT(12)
+#define MCP25XXFD_IOCON				MCP25XXFD_SFR_BASE(0x04)
+#  define MCP25XXFD_IOCON_TRIS0			BIT(0)
+#  define MCP25XXFD_IOCON_TRIS1			BIT(1)
+#  define MCP25XXFD_IOCON_XSTBYEN		BIT(6)
+#  define MCP25XXFD_IOCON_LAT0			BIT(8)
+#  define MCP25XXFD_IOCON_LAT1			BIT(9)
+#  define MCP25XXFD_IOCON_GPIO0			BIT(16)
+#  define MCP25XXFD_IOCON_GPIO1			BIT(17)
+#  define MCP25XXFD_IOCON_PM0			BIT(24)
+#  define MCP25XXFD_IOCON_PM1			BIT(25)
+#  define MCP25XXFD_IOCON_TXCANOD		BIT(28)
+#  define MCP25XXFD_IOCON_SOF			BIT(29)
+#  define MCP25XXFD_IOCON_INTOD			BIT(30)
+#define MCP25XXFD_CRC				MCP25XXFD_SFR_BASE(0x08)
+#  define MCP25XXFD_CRC_MASK			GENMASK(15, 0)
+#  define MCP25XXFD_CRC_CRCERRIE		BIT(16)
+#  define MCP25XXFD_CRC_FERRIE			BIT(17)
+#  define MCP25XXFD_CRC_CRCERRIF		BIT(24)
+#  define MCP25XXFD_CRC_FERRIF			BIT(25)
+#define MCP25XXFD_ECCCON			MCP25XXFD_SFR_BASE(0x0C)
+#  define MCP25XXFD_ECCCON_ECCEN		BIT(0)
+#  define MCP25XXFD_ECCCON_SECIE		BIT(1)
+#  define MCP25XXFD_ECCCON_DEDIE		BIT(2)
+#  define MCP25XXFD_ECCCON_PARITY_BITS		6
+#  define MCP25XXFD_ECCCON_PARITY_SHIFT		8
+#  define MCP25XXFD_ECCCON_PARITY_MASK					\
+	GENMASK(MCP25XXFD_ECCCON_PARITY_SHIFT				\
+		+ MCP25XXFD_ECCCON_PARITY_BITS - 1,			\
+		MCP25XXFD_ECCCON_PARITY_SHIFT)
+#define MCP25XXFD_ECCSTAT			MCP25XXFD_SFR_BASE(0x10)
+#  define MCP25XXFD_ECCSTAT_SECIF		BIT(1)
+#  define MCP25XXFD_ECCSTAT_DEDIF		BIT(2)
+#  define MCP25XXFD_ECCSTAT_ERRADDR_SHIFT	8
+#  define MCP25XXFD_ECCSTAT_ERRADDR_MASK				\
+	GENMASK(MCP25XXFD_ECCSTAT_ERRADDR_SHIFT + 11,			\
+		MCP25XXFD_ECCSTAT_ERRADDR_SHIFT)
+
+/* CAN related register definitions of Controller CAN block */
+#define MCP25XXFD_CAN_SFR_BASE(x)		(0x000 + (x))
+#define MCP25XXFD_CAN_CON						\
+	MCP25XXFD_CAN_SFR_BASE(0x00)
+#  define MCP25XXFD_CAN_CON_DNCNT_BITS		5
+#  define MCP25XXFD_CAN_CON_DNCNT_SHIFT		0
+#  define MCP25XXFD_CAN_CON_DNCNT_MASK					\
+	GENMASK(MCP25XXFD_CAN_CON_DNCNT_SHIFT +				\
+		MCP25XXFD_CAN_CON_DNCNT_BITS - 1,			\
+		MCP25XXFD_CAN_CON_DNCNT_SHIFT)
+#  define MCP25XXFD_CAN_CON_ISOCRCEN		BIT(5)
+#  define MCP25XXFD_CAN_CON_PXEDIS		BIT(6)
+#  define MCP25XXFD_CAN_CON_WAKFIL		BIT(8)
+#  define MCP25XXFD_CAN_CON_WFT_BITS		2
+#  define MCP25XXFD_CAN_CON_WFT_SHIFT		9
+#  define MCP25XXFD_CAN_CON_WFT_MASK					\
+	GENMASK(MCP25XXFD_CAN_CON_WFT_SHIFT +				\
+		MCP25XXFD_CAN_CON_WFT_BITS - 1,				\
+		MCP25XXFD_CAN_CON_WFT_SHIFT)
+#  define MCP25XXFD_CAN_CON_BUSY		BIT(11)
+#  define MCP25XXFD_CAN_CON_BRSDIS		BIT(12)
+#  define MCP25XXFD_CAN_CON_RTXAT		BIT(16)
+#  define MCP25XXFD_CAN_CON_ESIGM		BIT(17)
+#  define MCP25XXFD_CAN_CON_SERR2LOM		BIT(18)
+#  define MCP25XXFD_CAN_CON_STEF		BIT(19)
+#  define MCP25XXFD_CAN_CON_TXQEN		BIT(20)
+#  define MCP25XXFD_CAN_CON_OPMODE_BITS		3
+#  define MCP25XXFD_CAN_CON_OPMOD_SHIFT		21
+#  define MCP25XXFD_CAN_CON_OPMOD_MASK					\
+	GENMASK(MCP25XXFD_CAN_CON_OPMOD_SHIFT +				\
+		MCP25XXFD_CAN_CON_OPMODE_BITS - 1,			\
+		MCP25XXFD_CAN_CON_OPMOD_SHIFT)
+#  define MCP25XXFD_CAN_CON_REQOP_BITS		3
+#  define MCP25XXFD_CAN_CON_REQOP_SHIFT		24
+#  define MCP25XXFD_CAN_CON_REQOP_MASK					\
+	GENMASK(MCP25XXFD_CAN_CON_REQOP_SHIFT +				\
+		MCP25XXFD_CAN_CON_REQOP_BITS - 1,			\
+		MCP25XXFD_CAN_CON_REQOP_SHIFT)
+#    define MCP25XXFD_CAN_CON_MODE_MIXED	0
+#    define MCP25XXFD_CAN_CON_MODE_SLEEP	1
+#    define MCP25XXFD_CAN_CON_MODE_INT_LOOPBACK	2
+#    define MCP25XXFD_CAN_CON_MODE_LISTENONLY	3
+#    define MCP25XXFD_CAN_CON_MODE_CONFIG	4
+#    define MCP25XXFD_CAN_CON_MODE_EXT_LOOPBACK	5
+#    define MCP25XXFD_CAN_CON_MODE_CAN2_0	6
+#    define MCP25XXFD_CAN_CON_MODE_RESTRICTED	7
+#  define MCP25XXFD_CAN_CON_ABAT		BIT(27)
+#  define MCP25XXFD_CAN_CON_TXBWS_BITS		3
+#  define MCP25XXFD_CAN_CON_TXBWS_SHIFT		28
+#  define MCP25XXFD_CAN_CON_TXBWS_MASK					\
+	GENMASK(MCP25XXFD_CAN_CON_TXBWS_SHIFT +				\
+		MCP25XXFD_CAN_CON_TXBWS_BITS - 1,			\
+		MCP25XXFD_CAN_CON_TXBWS_SHIFT)
+#  define MCP25XXFD_CAN_CON_DEFAULT					\
+	(MCP25XXFD_CAN_CON_ISOCRCEN |					\
+	 MCP25XXFD_CAN_CON_PXEDIS |					\
+	 MCP25XXFD_CAN_CON_WAKFIL |					\
+	 (3 << MCP25XXFD_CAN_CON_WFT_SHIFT) |				\
+	 MCP25XXFD_CAN_CON_STEF |					\
+	 MCP25XXFD_CAN_CON_TXQEN |					\
+	 (MCP25XXFD_CAN_CON_MODE_CONFIG << MCP25XXFD_CAN_CON_OPMOD_SHIFT) | \
+	 (MCP25XXFD_CAN_CON_MODE_CONFIG << MCP25XXFD_CAN_CON_REQOP_SHIFT))
+#  define MCP25XXFD_CAN_CON_DEFAULT_MASK				\
+	(MCP25XXFD_CAN_CON_DNCNT_MASK |					\
+	 MCP25XXFD_CAN_CON_ISOCRCEN |					\
+	 MCP25XXFD_CAN_CON_PXEDIS |					\
+	 MCP25XXFD_CAN_CON_WAKFIL |					\
+	 MCP25XXFD_CAN_CON_WFT_MASK |					\
+	 MCP25XXFD_CAN_CON_BRSDIS |					\
+	 MCP25XXFD_CAN_CON_RTXAT |					\
+	 MCP25XXFD_CAN_CON_ESIGM |					\
+	 MCP25XXFD_CAN_CON_SERR2LOM |					\
+	 MCP25XXFD_CAN_CON_STEF |					\
+	 MCP25XXFD_CAN_CON_TXQEN |					\
+	 MCP25XXFD_CAN_CON_OPMOD_MASK |					\
+	 MCP25XXFD_CAN_CON_REQOP_MASK |					\
+	 MCP25XXFD_CAN_CON_ABAT |					\
+	 MCP25XXFD_CAN_CON_TXBWS_MASK)
+#define MCP25XXFD_CAN_NBTCFG			MCP25XXFD_CAN_SFR_BASE(0x04)
+#  define MCP25XXFD_CAN_NBTCFG_SJW_BITS		7
+#  define MCP25XXFD_CAN_NBTCFG_SJW_SHIFT	0
+#  define MCP25XXFD_CAN_NBTCFG_SJW_MASK					\
+	GENMASK(MCP25XXFD_CAN_NBTCFG_SJW_SHIFT +			\
+		MCP25XXFD_CAN_NBTCFG_SJW_BITS - 1,			\
+		MCP25XXFD_CAN_NBTCFG_SJW_SHIFT)
+#  define MCP25XXFD_CAN_NBTCFG_TSEG2_BITS	7
+#  define MCP25XXFD_CAN_NBTCFG_TSEG2_SHIFT	8
+#  define MCP25XXFD_CAN_NBTCFG_TSEG2_MASK				\
+	GENMASK(MCP25XXFD_CAN_NBTCFG_TSEG2_SHIFT +			\
+		MCP25XXFD_CAN_NBTCFG_TSEG2_BITS - 1,			\
+		MCP25XXFD_CAN_NBTCFG_TSEG2_SHIFT)
+#  define MCP25XXFD_CAN_NBTCFG_TSEG1_BITS	8
+#  define MCP25XXFD_CAN_NBTCFG_TSEG1_SHIFT	16
+#  define MCP25XXFD_CAN_NBTCFG_TSEG1_MASK				\
+	GENMASK(MCP25XXFD_CAN_NBTCFG_TSEG1_SHIFT +			\
+		MCP25XXFD_CAN_NBTCFG_TSEG1_BITS - 1,			\
+		MCP25XXFD_CAN_NBTCFG_TSEG1_SHIFT)
+#  define MCP25XXFD_CAN_NBTCFG_BRP_BITS		8
+#  define MCP25XXFD_CAN_NBTCFG_BRP_SHIFT	24
+#  define MCP25XXFD_CAN_NBTCFG_BRP_MASK					\
+	GENMASK(MCP25XXFD_CAN_NBTCFG_BRP_SHIFT +			\
+		MCP25XXFD_CAN_NBTCFG_BRP_BITS - 1,			\
+		MCP25XXFD_CAN_NBTCFG_BRP_SHIFT)
+#define MCP25XXFD_CAN_DBTCFG			MCP25XXFD_CAN_SFR_BASE(0x08)
+#  define MCP25XXFD_CAN_DBTCFG_SJW_BITS		4
+#  define MCP25XXFD_CAN_DBTCFG_SJW_SHIFT	0
+#  define MCP25XXFD_CAN_DBTCFG_SJW_MASK					\
+	GENMASK(MCP25XXFD_CAN_DBTCFG_SJW_SHIFT +			\
+		MCP25XXFD_CAN_DBTCFG_SJW_BITS - 1,			\
+		MCP25XXFD_CAN_DBTCFG_SJW_SHIFT)
+#  define MCP25XXFD_CAN_DBTCFG_TSEG2_BITS	4
+#  define MCP25XXFD_CAN_DBTCFG_TSEG2_SHIFT	8
+#  define MCP25XXFD_CAN_DBTCFG_TSEG2_MASK				\
+	GENMASK(MCP25XXFD_CAN_DBTCFG_TSEG2_SHIFT +			\
+		MCP25XXFD_CAN_DBTCFG_TSEG2_BITS - 1,			\
+		MCP25XXFD_CAN_DBTCFG_TSEG2_SHIFT)
+#  define MCP25XXFD_CAN_DBTCFG_TSEG1_BITS	5
+#  define MCP25XXFD_CAN_DBTCFG_TSEG1_SHIFT	16
+#  define MCP25XXFD_CAN_DBTCFG_TSEG1_MASK				\
+	GENMASK(MCP25XXFD_CAN_DBTCFG_TSEG1_SHIFT +			\
+		MCP25XXFD_CAN_DBTCFG_TSEG1_BITS - 1,			\
+		MCP25XXFD_CAN_DBTCFG_TSEG1_SHIFT)
+#  define MCP25XXFD_CAN_DBTCFG_BRP_BITS		8
+#  define MCP25XXFD_CAN_DBTCFG_BRP_SHIFT	24
+#  define MCP25XXFD_CAN_DBTCFG_BRP_MASK					\
+	GENMASK(MCP25XXFD_CAN_DBTCFG_BRP_SHIFT +			\
+		MCP25XXFD_CAN_DBTCFG_BRP_BITS - 1,			\
+		MCP25XXFD_CAN_DBTCFG_BRP_SHIFT)
+#define MCP25XXFD_CAN_TDC			MCP25XXFD_CAN_SFR_BASE(0x0C)
+#  define MCP25XXFD_CAN_TDC_TDCV_BITS		5
+#  define MCP25XXFD_CAN_TDC_TDCV_SHIFT		0
+#  define MCP25XXFD_CAN_TDC_TDCV_MASK					\
+	GENMASK(MCP25XXFD_CAN_TDC_TDCV_SHIFT +				\
+		MCP25XXFD_CAN_TDC_TDCV_BITS - 1,			\
+		MCP25XXFD_CAN_TDC_TDCV_SHIFT)
+#  define MCP25XXFD_CAN_TDC_TDCO_BITS		5
+#  define MCP25XXFD_CAN_TDC_TDCO_SHIFT		8
+#  define MCP25XXFD_CAN_TDC_TDCO_MASK					\
+	GENMASK(MCP25XXFD_CAN_TDC_TDCO_SHIFT +				\
+		MCP25XXFD_CAN_TDC_TDCO_BITS - 1,			\
+		MCP25XXFD_CAN_TDC_TDCO_SHIFT)
+#  define MCP25XXFD_CAN_TDC_TDCMOD_BITS		2
+#  define MCP25XXFD_CAN_TDC_TDCMOD_SHIFT	16
+#  define MCP25XXFD_CAN_TDC_TDCMOD_MASK					\
+	GENMASK(MCP25XXFD_CAN_TDC_TDCMOD_SHIFT +			\
+		MCP25XXFD_CAN_TDC_TDCMOD_BITS - 1,			\
+		MCP25XXFD_CAN_TDC_TDCMOD_SHIFT)
+#  define MCP25XXFD_CAN_TDC_TDCMOD_DISABLED	0
+#  define MCP25XXFD_CAN_TDC_TDCMOD_MANUAL	1
+#  define MCP25XXFD_CAN_TDC_TDCMOD_AUTO		2
+#  define MCP25XXFD_CAN_TDC_SID11EN		BIT(24)
+#  define MCP25XXFD_CAN_TDC_EDGFLTEN		BIT(25)
+#define MCP25XXFD_CAN_TBC			MCP25XXFD_CAN_SFR_BASE(0x10)
+#define MCP25XXFD_CAN_TSCON			MCP25XXFD_CAN_SFR_BASE(0x14)
+#  define MCP25XXFD_CAN_TSCON_TBCPRE_BITS	10
+#  define MCP25XXFD_CAN_TSCON_TBCPRE_SHIFT	0
+#  define MCP25XXFD_CAN_TSCON_TBCPRE_MASK				\
+	GENMASK(MCP25XXFD_CAN_TSCON_TBCPRE_SHIFT +			\
+		MCP25XXFD_CAN_TSCON_TBCPRE_BITS - 1,			\
+		MCP25XXFD_CAN_TSCON_TBCPRE_SHIFT)
+#  define MCP25XXFD_CAN_TSCON_TBCEN		BIT(16)
+#  define MCP25XXFD_CAN_TSCON_TSEOF		BIT(17)
+#  define MCP25XXFD_CAN_TSCON_TSRES		BIT(18)
+#define MCP25XXFD_CAN_VEC			MCP25XXFD_CAN_SFR_BASE(0x18)
+#  define MCP25XXFD_CAN_VEC_ICODE_BITS		7
+#  define MCP25XXFD_CAN_VEC_ICODE_SHIFT		0
+#  define MCP25XXFD_CAN_VEC_ICODE_MASK					\
+	GENMASK(MCP25XXFD_CAN_VEC_ICODE_SHIFT +				\
+		MCP25XXFD_CAN_VEC_ICODE_BITS - 1,			\
+		MCP25XXFD_CAN_VEC_ICODE_SHIFT)
+#  define MCP25XXFD_CAN_VEC_FILHIT_BITS		5
+#  define MCP25XXFD_CAN_VEC_FILHIT_SHIFT	8
+#  define MCP25XXFD_CAN_VEC_FILHIT_MASK					\
+	GENMASK(MCP25XXFD_CAN_VEC_FILHIT_SHIFT +			\
+		MCP25XXFD_CAN_VEC_FILHIT_BITS - 1,			\
+		MCP25XXFD_CAN_VEC_FILHIT_SHIFT)
+#  define MCP25XXFD_CAN_VEC_TXCODE_BITS		7
+#  define MCP25XXFD_CAN_VEC_TXCODE_SHIFT	16
+#  define MCP25XXFD_CAN_VEC_TXCODE_MASK					\
+	GENMASK(MCP25XXFD_CAN_VEC_TXCODE_SHIFT +			\
+		MCP25XXFD_CAN_VEC_TXCODE_BITS - 1,			\
+		MCP25XXFD_CAN_VEC_TXCODE_SHIFT)
+#  define MCP25XXFD_CAN_VEC_RXCODE_BITS		7
+#  define MCP25XXFD_CAN_VEC_RXCODE_SHIFT	24
+#  define MCP25XXFD_CAN_VEC_RXCODE_MASK					\
+	GENMASK(MCP25XXFD_CAN_VEC_RXCODE_SHIFT +			\
+		MCP25XXFD_CAN_VEC_RXCODE_BITS - 1,			\
+		MCP25XXFD_CAN_VEC_RXCODE_SHIFT)
+#define MCP25XXFD_CAN_INT			MCP25XXFD_CAN_SFR_BASE(0x1C)
+#  define MCP25XXFD_CAN_INT_IF_SHIFT		0
+#  define MCP25XXFD_CAN_INT_TXIF		BIT(0)
+#  define MCP25XXFD_CAN_INT_RXIF		BIT(1)
+#  define MCP25XXFD_CAN_INT_TBCIF		BIT(2)
+#  define MCP25XXFD_CAN_INT_MODIF		BIT(3)
+#  define MCP25XXFD_CAN_INT_TEFIF		BIT(4)
+#  define MCP25XXFD_CAN_INT_ECCIF		BIT(8)
+#  define MCP25XXFD_CAN_INT_SPICRCIF		BIT(9)
+#  define MCP25XXFD_CAN_INT_TXATIF		BIT(10)
+#  define MCP25XXFD_CAN_INT_RXOVIF		BIT(11)
+#  define MCP25XXFD_CAN_INT_SERRIF		BIT(12)
+#  define MCP25XXFD_CAN_INT_CERRIF		BIT(13)
+#  define MCP25XXFD_CAN_INT_WAKIF		BIT(14)
+#  define MCP25XXFD_CAN_INT_IVMIF		BIT(15)
+#  define MCP25XXFD_CAN_INT_IF_MASK					\
+	(MCP25XXFD_CAN_INT_TXIF |					\
+	 MCP25XXFD_CAN_INT_RXIF |					\
+	 MCP25XXFD_CAN_INT_TBCIF |					\
+	 MCP25XXFD_CAN_INT_MODIF |					\
+	 MCP25XXFD_CAN_INT_TEFIF |					\
+	 MCP25XXFD_CAN_INT_ECCIF |					\
+	 MCP25XXFD_CAN_INT_SPICRCIF |					\
+	 MCP25XXFD_CAN_INT_TXATIF |					\
+	 MCP25XXFD_CAN_INT_RXOVIF |					\
+	 MCP25XXFD_CAN_INT_CERRIF |					\
+	 MCP25XXFD_CAN_INT_SERRIF |					\
+	 MCP25XXFD_CAN_INT_WAKIF |					\
+	 MCP25XXFD_CAN_INT_IVMIF)
+#  define MCP25XXFD_CAN_INT_IF_CLEAR_MASK				\
+	(MCP25XXFD_CAN_INT_TBCIF  |					\
+	 MCP25XXFD_CAN_INT_MODIF  |					\
+	 MCP25XXFD_CAN_INT_CERRIF |					\
+	 MCP25XXFD_CAN_INT_SERRIF |					\
+	 MCP25XXFD_CAN_INT_WAKIF |					\
+	 MCP25XXFD_CAN_INT_IVMIF)
+#  define MCP25XXFD_CAN_INT_IE_SHIFT		16
+#  define MCP25XXFD_CAN_INT_TXIE					\
+	(MCP25XXFD_CAN_INT_TXIF << MCP25XXFD_CAN_INT_IE_SHIFT)
+#  define MCP25XXFD_CAN_INT_RXIE					\
+	(MCP25XXFD_CAN_INT_RXIF << MCP25XXFD_CAN_INT_IE_SHIFT)
+#  define MCP25XXFD_CAN_INT_TBCIE					\
+	(MCP25XXFD_CAN_INT_TBCIF << MCP25XXFD_CAN_INT_IE_SHIFT)
+#  define MCP25XXFD_CAN_INT_MODIE					\
+	(MCP25XXFD_CAN_INT_MODIF << MCP25XXFD_CAN_INT_IE_SHIFT)
+#  define MCP25XXFD_CAN_INT_TEFIE					\
+	(MCP25XXFD_CAN_INT_TEFIF << MCP25XXFD_CAN_INT_IE_SHIFT)
+#  define MCP25XXFD_CAN_INT_ECCIE					\
+	(MCP25XXFD_CAN_INT_ECCIF << MCP25XXFD_CAN_INT_IE_SHIFT)
+#  define MCP25XXFD_CAN_INT_SPICRCIE					\
+	(MCP25XXFD_CAN_INT_SPICRCIF << MCP25XXFD_CAN_INT_IE_SHIFT)
+#  define MCP25XXFD_CAN_INT_TXATIE					\
+	(MCP25XXFD_CAN_INT_TXATIF << MCP25XXFD_CAN_INT_IE_SHIFT)
+#  define MCP25XXFD_CAN_INT_RXOVIE					\
+	(MCP25XXFD_CAN_INT_RXOVIF << MCP25XXFD_CAN_INT_IE_SHIFT)
+#  define MCP25XXFD_CAN_INT_CERRIE					\
+	(MCP25XXFD_CAN_INT_CERRIF << MCP25XXFD_CAN_INT_IE_SHIFT)
+#  define MCP25XXFD_CAN_INT_SERRIE					\
+	(MCP25XXFD_CAN_INT_SERRIF << MCP25XXFD_CAN_INT_IE_SHIFT)
+#  define MCP25XXFD_CAN_INT_WAKIE					\
+	(MCP25XXFD_CAN_INT_WAKIF << MCP25XXFD_CAN_INT_IE_SHIFT)
+#  define MCP25XXFD_CAN_INT_IVMIE					\
+	(MCP25XXFD_CAN_INT_IVMIF << MCP25XXFD_CAN_INT_IE_SHIFT)
+#  define MCP25XXFD_CAN_INT_IE_MASK					\
+	(MCP25XXFD_CAN_INT_TXIE |					\
+	 MCP25XXFD_CAN_INT_RXIE |					\
+	 MCP25XXFD_CAN_INT_TBCIE |					\
+	 MCP25XXFD_CAN_INT_MODIE |					\
+	 MCP25XXFD_CAN_INT_TEFIE |					\
+	 MCP25XXFD_CAN_INT_ECCIE |					\
+	 MCP25XXFD_CAN_INT_SPICRCIE |					\
+	 MCP25XXFD_CAN_INT_TXATIE |					\
+	 MCP25XXFD_CAN_INT_RXOVIE |					\
+	 MCP25XXFD_CAN_INT_CERRIE |					\
+	 MCP25XXFD_CAN_INT_SERRIE |					\
+	 MCP25XXFD_CAN_INT_WAKIE |					\
+	 MCP25XXFD_CAN_INT_IVMIE)
+#define MCP25XXFD_CAN_RXIF			MCP25XXFD_CAN_SFR_BASE(0x20)
+#define MCP25XXFD_CAN_TXIF			MCP25XXFD_CAN_SFR_BASE(0x24)
+#define MCP25XXFD_CAN_RXOVIF			MCP25XXFD_CAN_SFR_BASE(0x28)
+#define MCP25XXFD_CAN_TXATIF			MCP25XXFD_CAN_SFR_BASE(0x2C)
+#define MCP25XXFD_CAN_TXREQ			MCP25XXFD_CAN_SFR_BASE(0x30)
+#define MCP25XXFD_CAN_TREC			MCP25XXFD_CAN_SFR_BASE(0x34)
+#  define MCP25XXFD_CAN_TREC_REC_BITS		8
+#  define MCP25XXFD_CAN_TREC_REC_SHIFT		0
+#  define MCP25XXFD_CAN_TREC_REC_MASK					\
+	GENMASK(MCP25XXFD_CAN_TREC_REC_SHIFT +				\
+		MCP25XXFD_CAN_TREC_REC_BITS - 1,			\
+		MCP25XXFD_CAN_TREC_REC_SHIFT)
+#  define MCP25XXFD_CAN_TREC_TEC_BITS		8
+#  define MCP25XXFD_CAN_TREC_TEC_SHIFT		8
+#  define MCP25XXFD_CAN_TREC_TEC_MASK					\
+	GENMASK(MCP25XXFD_CAN_TREC_TEC_SHIFT +				\
+		MCP25XXFD_CAN_TREC_TEC_BITS - 1,			\
+		MCP25XXFD_CAN_TREC_TEC_SHIFT)
+#  define MCP25XXFD_CAN_TREC_EWARN		BIT(16)
+#  define MCP25XXFD_CAN_TREC_RXWARN		BIT(17)
+#  define MCP25XXFD_CAN_TREC_TXWARN		BIT(18)
+#  define MCP25XXFD_CAN_TREC_RXBP		BIT(19)
+#  define MCP25XXFD_CAN_TREC_TXBP		BIT(20)
+#  define MCP25XXFD_CAN_TREC_TXBO		BIT(21)
+#define MCP25XXFD_CAN_BDIAG0			MCP25XXFD_CAN_SFR_BASE(0x38)
+#  define MCP25XXFD_CAN_BDIAG0_NRERRCNT_BITS	8
+#  define MCP25XXFD_CAN_BDIAG0_NRERRCNT_SHIFT	0
+#  define MCP25XXFD_CAN_BDIAG0_NRERRCNT_MASK				\
+	GENMASK(MCP25XXFD_CAN_BDIAG0_NRERRCNT_SHIFT +			\
+		MCP25XXFD_CAN_BDIAG0_NRERRCNT_BITS - 1,			\
+		MCP25XXFD_CAN_BDIAG0_NRERRCNT_SHIFT)
+#  define MCP25XXFD_CAN_BDIAG0_NTERRCNT_BITS	8
+#  define MCP25XXFD_CAN_BDIAG0_NTERRCNT_SHIFT	8
+#  define MCP25XXFD_CAN_BDIAG0_NTERRCNT_MASK				\
+	GENMASK(MCP25XXFD_CAN_BDIAG0_NTERRCNT_SHIFT +			\
+		MCP25XXFD_CAN_BDIAG0_NTERRCNT_BITS - 1,			\
+		MCP25XXFD_CAN_BDIAG0_NTERRCNT_SHIFT)
+#  define MCP25XXFD_CAN_BDIAG0_DRERRCNT_BITS	8
+#  define MCP25XXFD_CAN_BDIAG0_DRERRCNT_SHIFT	16
+#  define MCP25XXFD_CAN_BDIAG0_DRERRCNT_MASK				\
+	GENMASK(MCP25XXFD_CAN_BDIAG0_DRERRCNT_SHIFT +			\
+		MCP25XXFD_CAN_BDIAG0_DRERRCNT_BITS - 1,			\
+		MCP25XXFD_CAN_BDIAG0_DRERRCNT_SHIFT)
+#  define MCP25XXFD_CAN_BDIAG0_DTERRCNT_BITS	8
+#  define MCP25XXFD_CAN_BDIAG0_DTERRCNT_SHIFT	24
+#  define MCP25XXFD_CAN_BDIAG0_DTERRCNT_MASK				\
+	GENMASK(MCP25XXFD_CAN_BDIAG0_DTERRCNT_SHIFT +			\
+		MCP25XXFD_CAN_BDIAG0_DTERRCNT_BITS - 1,			\
+		MCP25XXFD_CAN_BDIAG0_DTERRCNT_SHIFT)
+#define MCP25XXFD_CAN_BDIAG1			MCP25XXFD_CAN_SFR_BASE(0x3C)
+#  define MCP25XXFD_CAN_BDIAG1_EFMSGCNT_BITS	16
+#  define MCP25XXFD_CAN_BDIAG1_EFMSGCNT_SHIFT	0
+#  define MCP25XXFD_CAN_BDIAG1_EFMSGCNT_MASK				\
+	GENMASK(MCP25XXFD_CAN_BDIAG1_EFMSGCNT_SHIFT +			\
+		MCP25XXFD_CAN_BDIAG1_EFMSGCNT_BITS - 1,			\
+		MCP25XXFD_CAN_BDIAG1_EFMSGCNT_SHIFT)
+#  define MCP25XXFD_CAN_BDIAG1_NBIT0ERR		BIT(16)
+#  define MCP25XXFD_CAN_BDIAG1_NBIT1ERR		BIT(17)
+#  define MCP25XXFD_CAN_BDIAG1_NACKERR		BIT(18)
+#  define MCP25XXFD_CAN_BDIAG1_NSTUFERR		BIT(19)
+#  define MCP25XXFD_CAN_BDIAG1_NFORMERR		BIT(20)
+#  define MCP25XXFD_CAN_BDIAG1_NCRCERR		BIT(21)
+#  define MCP25XXFD_CAN_BDIAG1_TXBOERR		BIT(23)
+#  define MCP25XXFD_CAN_BDIAG1_DBIT0ERR		BIT(24)
+#  define MCP25XXFD_CAN_BDIAG1_DBIT1ERR		BIT(25)
+#  define MCP25XXFD_CAN_BDIAG1_DFORMERR		BIT(27)
+#  define MCP25XXFD_CAN_BDIAG1_DSTUFERR		BIT(28)
+#  define MCP25XXFD_CAN_BDIAG1_DCRCERR		BIT(29)
+#  define MCP25XXFD_CAN_BDIAG1_ESI		BIT(30)
+#  define MCP25XXFD_CAN_BDIAG1_DLCMM		BIT(31)
+#define MCP25XXFD_CAN_TEFCON			MCP25XXFD_CAN_SFR_BASE(0x40)
+#  define MCP25XXFD_CAN_TEFCON_TEFNEIE		BIT(0)
+#  define MCP25XXFD_CAN_TEFCON_TEFHIE		BIT(1)
+#  define MCP25XXFD_CAN_TEFCON_TEFFIE		BIT(2)
+#  define MCP25XXFD_CAN_TEFCON_TEFOVIE		BIT(3)
+#  define MCP25XXFD_CAN_TEFCON_TEFTSEN		BIT(5)
+#  define MCP25XXFD_CAN_TEFCON_UINC		BIT(8)
+#  define MCP25XXFD_CAN_TEFCON_FRESET		BIT(10)
+#  define MCP25XXFD_CAN_TEFCON_FSIZE_BITS	5
+#  define MCP25XXFD_CAN_TEFCON_FSIZE_SHIFT	24
+#  define MCP25XXFD_CAN_TEFCON_FSIZE_MASK				\
+	GENMASK(MCP25XXFD_CAN_TEFCON_FSIZE_SHIFT +			\
+		MCP25XXFD_CAN_TEFCON_FSIZE_BITS - 1,			\
+		MCP25XXFD_CAN_TEFCON_FSIZE_SHIFT)
+#define MCP25XXFD_CAN_TEFSTA			MCP25XXFD_CAN_SFR_BASE(0x44)
+#  define MCP25XXFD_CAN_TEFSTA_TEFNEIF		BIT(0)
+#  define MCP25XXFD_CAN_TEFSTA_TEFHIF		BIT(1)
+#  define MCP25XXFD_CAN_TEFSTA_TEFFIF		BIT(2)
+#  define MCP25XXFD_CAN_TEFSTA_TEVOVIF		BIT(3)
+#define MCP25XXFD_CAN_TEFUA			MCP25XXFD_CAN_SFR_BASE(0x48)
+#define MCP25XXFD_CAN_RESERVED			MCP25XXFD_CAN_SFR_BASE(0x4C)
+#define MCP25XXFD_CAN_TXQCON			MCP25XXFD_CAN_SFR_BASE(0x50)
+#  define MCP25XXFD_CAN_TXQCON_TXQNIE		BIT(0)
+#  define MCP25XXFD_CAN_TXQCON_TXQEIE		BIT(2)
+#  define MCP25XXFD_CAN_TXQCON_TXATIE		BIT(4)
+#  define MCP25XXFD_CAN_TXQCON_TXEN		BIT(7)
+#  define MCP25XXFD_CAN_TXQCON_UINC		BIT(8)
+#  define MCP25XXFD_CAN_TXQCON_TXREQ		BIT(9)
+#  define MCP25XXFD_CAN_TXQCON_FRESET		BIT(10)
+#  define MCP25XXFD_CAN_TXQCON_TXPRI_BITS	5
+#  define MCP25XXFD_CAN_TXQCON_TXPRI_SHIFT	16
+#  define MCP25XXFD_CAN_TXQCON_TXPRI_MASK				\
+	GENMASK(MCP25XXFD_CAN_TXQCON_TXPRI_SHIFT +			\
+		MCP25XXFD_CAN_TXQCON_TXPRI_BITS - 1,			\
+		MCP25XXFD_CAN_TXQCON_TXPRI_SHIFT)
+#  define MCP25XXFD_CAN_TXQCON_TXAT_BITS	2
+#  define MCP25XXFD_CAN_TXQCON_TXAT_SHIFT	21
+#  define MCP25XXFD_CAN_TXQCON_TXAT_MASK				\
+	GENMASK(MCP25XXFD_CAN_TXQCON_TXAT_SHIFT +			\
+		#MCP25XXFD_CAN_TXQCON_TXAT_BITS - 1,			\
+		MCP25XXFD_CAN_TXQCON_TXAT_SHIFT)
+#  define MCP25XXFD_CAN_TXQCON_FSIZE_BITS	5
+#  define MCP25XXFD_CAN_TXQCON_FSIZE_SHIFT	24
+#  define MCP25XXFD_CAN_TXQCON_FSIZE_MASK				\
+	GENMASK(MCP25XXFD_CAN_TXQCON_FSIZE_SHIFT +			\
+		MCP25XXFD_CAN_TXQCON_FSIZE_BITS - 1,			\
+		MCP25XXFD_CAN_TXQCON_FSIZE_SHIFT)
+#  define MCP25XXFD_CAN_TXQCON_PLSIZE_BITS	3
+#  define MCP25XXFD_CAN_TXQCON_PLSIZE_SHIFT	29
+#  define MCP25XXFD_CAN_TXQCON_PLSIZE_MASK				\
+	GENMASK(MCP25XXFD_CAN_TXQCON_PLSIZE_SHIFT +			\
+		MCP25XXFD_CAN_TXQCON_PLSIZE_BITS - 1,			\
+		MCP25XXFD_CAN_TXQCON_PLSIZE_SHIFT)
+#    define MCP25XXFD_CAN_TXQCON_PLSIZE_8	0
+#    define MCP25XXFD_CAN_TXQCON_PLSIZE_12	1
+#    define MCP25XXFD_CAN_TXQCON_PLSIZE_16	2
+#    define MCP25XXFD_CAN_TXQCON_PLSIZE_20	3
+#    define MCP25XXFD_CAN_TXQCON_PLSIZE_24	4
+#    define MCP25XXFD_CAN_TXQCON_PLSIZE_32	5
+#    define MCP25XXFD_CAN_TXQCON_PLSIZE_48	6
+#    define MCP25XXFD_CAN_TXQCON_PLSIZE_64	7
+
+#define MCP25XXFD_CAN_TXQSTA			MCP25XXFD_CAN_SFR_BASE(0x54)
+#  define MCP25XXFD_CAN_TXQSTA_TXQNIF		BIT(0)
+#  define MCP25XXFD_CAN_TXQSTA_TXQEIF		BIT(2)
+#  define MCP25XXFD_CAN_TXQSTA_TXATIF		BIT(4)
+#  define MCP25XXFD_CAN_TXQSTA_TXERR		BIT(5)
+#  define MCP25XXFD_CAN_TXQSTA_TXLARB		BIT(6)
+#  define MCP25XXFD_CAN_TXQSTA_TXABT		BIT(7)
+#  define MCP25XXFD_CAN_TXQSTA_TXQCI_BITS	5
+#  define MCP25XXFD_CAN_TXQSTA_TXQCI_SHIFT	8
+#  define MCP25XXFD_CAN_TXQSTA_TXQCI_MASK				\
+	GENMASK(MCP25XXFD_CAN_TXQSTA_TXQCI_SHIFT +			\
+		MCP25XXFD_CAN_TXQSTA_TXQCI_BITS - 1,			\
+		MCP25XXFD_CAN_TXQSTA_TXQCI_SHIFT)
+
+#define MCP25XXFD_CAN_TXQUA			MCP25XXFD_CAN_SFR_BASE(0x58)
+#define MCP25XXFD_CAN_FIFOCON(x)					\
+	MCP25XXFD_CAN_SFR_BASE(0x5C + 12 * ((x) - 1))
+#define MCP25XXFD_CAN_FIFOCON_TFNRFNIE		BIT(0)
+#define MCP25XXFD_CAN_FIFOCON_TFHRFHIE		BIT(1)
+#define MCP25XXFD_CAN_FIFOCON_TFERFFIE		BIT(2)
+#define MCP25XXFD_CAN_FIFOCON_RXOVIE		BIT(3)
+#define MCP25XXFD_CAN_FIFOCON_TXATIE		BIT(4)
+#define MCP25XXFD_CAN_FIFOCON_RXTSEN		BIT(5)
+#define MCP25XXFD_CAN_FIFOCON_RTREN		BIT(6)
+#define MCP25XXFD_CAN_FIFOCON_TXEN		BIT(7)
+#define MCP25XXFD_CAN_FIFOCON_UINC		BIT(8)
+#define MCP25XXFD_CAN_FIFOCON_TXREQ		BIT(9)
+#define MCP25XXFD_CAN_FIFOCON_FRESET		BIT(10)
+#  define MCP25XXFD_CAN_FIFOCON_TXPRI_BITS	5
+#  define MCP25XXFD_CAN_FIFOCON_TXPRI_SHIFT	16
+#  define MCP25XXFD_CAN_FIFOCON_TXPRI_MASK				\
+	GENMASK(MCP25XXFD_CAN_FIFOCON_TXPRI_SHIFT +			\
+		MCP25XXFD_CAN_FIFOCON_TXPRI_BITS - 1,			\
+		MCP25XXFD_CAN_FIFOCON_TXPRI_SHIFT)
+#  define MCP25XXFD_CAN_FIFOCON_TXAT_BITS	2
+#  define MCP25XXFD_CAN_FIFOCON_TXAT_SHIFT	21
+#  define MCP25XXFD_CAN_FIFOCON_TXAT_MASK				\
+	GENMASK(MCP25XXFD_CAN_FIFOCON_TXAT_SHIFT +			\
+		MCP25XXFD_CAN_FIFOCON_TXAT_BITS - 1,			\
+		MCP25XXFD_CAN_FIFOCON_TXAT_SHIFT)
+#  define MCP25XXFD_CAN_FIFOCON_TXAT_ONE_SHOT	0
+#  define MCP25XXFD_CAN_FIFOCON_TXAT_THREE_SHOT	1
+#  define MCP25XXFD_CAN_FIFOCON_TXAT_UNLIMITED	2
+#  define MCP25XXFD_CAN_FIFOCON_FSIZE_BITS	5
+#  define MCP25XXFD_CAN_FIFOCON_FSIZE_SHIFT	24
+#  define MCP25XXFD_CAN_FIFOCON_FSIZE_MASK				\
+	GENMASK(MCP25XXFD_CAN_FIFOCON_FSIZE_SHIFT +			\
+		MCP25XXFD_CAN_FIFOCON_FSIZE_BITS - 1,			\
+		MCP25XXFD_CAN_FIFOCON_FSIZE_SHIFT)
+#  define MCP25XXFD_CAN_FIFOCON_PLSIZE_BITS	3
+#  define MCP25XXFD_CAN_FIFOCON_PLSIZE_SHIFT	29
+#  define MCP25XXFD_CAN_FIFOCON_PLSIZE_MASK				\
+	GENMASK(MCP25XXFD_CAN_FIFOCON_PLSIZE_SHIFT +			\
+		MCP25XXFD_CAN_FIFOCON_PLSIZE_BITS - 1,			\
+		MCP25XXFD_CAN_FIFOCON_PLSIZE_SHIFT)
+#define MCP25XXFD_CAN_FIFOSTA(x)					\
+	MCP25XXFD_CAN_SFR_BASE(0x60 + 12 * ((x) - 1))
+#  define MCP25XXFD_CAN_FIFOSTA_TFNRFNIF	BIT(0)
+#  define MCP25XXFD_CAN_FIFOSTA_TFHRFHIF	BIT(1)
+#  define MCP25XXFD_CAN_FIFOSTA_TFERFFIF	BIT(2)
+#  define MCP25XXFD_CAN_FIFOSTA_RXOVIF		BIT(3)
+#  define MCP25XXFD_CAN_FIFOSTA_TXATIF		BIT(4)
+#  define MCP25XXFD_CAN_FIFOSTA_TXERR		BIT(5)
+#  define MCP25XXFD_CAN_FIFOSTA_TXLARB		BIT(6)
+#  define MCP25XXFD_CAN_FIFOSTA_TXABT		BIT(7)
+#  define MCP25XXFD_CAN_FIFOSTA_FIFOCI_BITS	5
+#  define MCP25XXFD_CAN_FIFOSTA_FIFOCI_SHIFT	8
+#  define MCP25XXFD_CAN_FIFOSTA_FIFOCI_MASK				\
+	GENMASK(MCP25XXFD_CAN_FIFOSTA_FIFOCI_SHIFT +			\
+		MCP25XXFD_CAN_FIFOSTA_FIFOCI_BITS - 1,			\
+		MCP25XXFD_CAN_FIFOSTA_FIFOCI_SHIFT)
+#define MCP25XXFD_CAN_FIFOUA(x)						\
+	MCP25XXFD_CAN_SFR_BASE(0x64 + 12 * ((x) - 1))
+#define MCP25XXFD_CAN_FLTCON(x)						\
+	MCP25XXFD_CAN_SFR_BASE(0x1D0 + ((x) & 0x1c))
+#  define MCP25XXFD_CAN_FILCON_SHIFT(x)		(((x) & 3) * 8)
+#  define MCP25XXFD_CAN_FILCON_BITS(x)		MCP25XXFD_CAN_FILCON_BITS_
+#  define MCP25XXFD_CAN_FILCON_BITS_		4
+	/* avoid macro reuse warning, so do not use GENMASK as above */
+#  define MCP25XXFD_CAN_FILCON_MASK(x)					\
+	(GENMASK(MCP25XXFD_CAN_FILCON_BITS_ - 1, 0) <<			\
+	 MCP25XXFD_CAN_FILCON_SHIFT(x))
+#  define MCP25XXFD_CAN_FIFOCON_FLTEN(x)				\
+	BIT(7 + MCP25XXFD_CAN_FILCON_SHIFT(x))
+#define MCP25XXFD_CAN_FLTOBJ(x)						\
+	MCP25XXFD_CAN_SFR_BASE(0x1F0 + 8 * (x))
+#  define MCP25XXFD_CAN_FILOBJ_SID_BITS		11
+#  define MCP25XXFD_CAN_FILOBJ_SID_SHIFT	0
+#  define MCP25XXFD_CAN_FILOBJ_SID_MASK					\
+	GENMASK(MCP25XXFD_CAN_FILOBJ_SID_SHIFT +			\
+		MCP25XXFD_CAN_FILOBJ_SID_BITS - 1,			\
+		MCP25XXFD_CAN_FILOBJ_SID_SHIFT)
+#  define MCP25XXFD_CAN_FILOBJ_EID_BITS		18
+#  define MCP25XXFD_CAN_FILOBJ_EID_SHIFT	12
+#  define MCP25XXFD_CAN_FILOBJ_EID_MASK					\
+	GENMASK(MCP25XXFD_CAN_FILOBJ_EID_SHIFT +			\
+		MCP25XXFD_CAN_FILOBJ_EID_BITS - 1,			\
+		MCP25XXFD_CAN_FILOBJ_EID_SHIFT)
+#  define MCP25XXFD_CAN_FILOBJ_SID11		BIT(29)
+#  define MCP25XXFD_CAN_FILOBJ_EXIDE		BIT(30)
+#define MCP25XXFD_CAN_FLTMASK(x)					\
+	MCP25XXFD_CAN_SFR_BASE(0x1F4 + 8 * (x))
+#  define MCP25XXFD_CAN_FILMASK_MSID_BITS	11
+#  define MCP25XXFD_CAN_FILMASK_MSID_SHIFT	0
+#  define MCP25XXFD_CAN_FILMASK_MSID_MASK				\
+	GENMASK(MCP25XXFD_CAN_FILMASK_MSID_SHIFT +			\
+		MCP25XXFD_CAN_FILMASK_MSID_BITS - 1,			\
+		MCP25XXFD_CAN_FILMASK_MSID_SHIFT)
+#  define MCP25XXFD_CAN_FILMASK_MEID_BITS	18
+#  define MCP25XXFD_CAN_FILMASK_MEID_SHIFT	12
+#  define MCP25XXFD_CAN_FILMASK_MEID_MASK				\
+	GENMASK(MCP25XXFD_CAN_FILMASK_MEID_SHIFT +			\
+		MCP25XXFD_CAN_FILMASK_MEID_BITS - 1,			\
+		MCP25XXFD_CAN_FILMASK_MEID_SHIFT)
+#  define MCP25XXFD_CAN_FILMASK_MSID11		BIT(29)
+#  define MCP25XXFD_CAN_FILMASK_MIDE		BIT(30)
+
+/* the FIFO Objects in SRAM */
+#define MCP25XXFD_SRAM_SIZE 2048
+#define MCP25XXFD_SRAM_ADDR(x) (0x400 + (x))
+
+/* memory structure in sram for tx fifos */
+struct mcp25xxfd_can_obj_tx {
+	u32 id;
+	u32 flags;
+	u8 data[];
+};
+
+/* memory structure in sram for rx fifos */
+struct mcp25xxfd_can_obj_rx {
+	u32 id;
+	u32 flags;
+	u32 ts;
+	u8 data[];
+};
+
+/* memory structure in sram for tef fifos */
+struct mcp25xxfd_can_obj_tef {
+	u32 id;
+	u32 flags;
+	u32 ts;
+};
+
+#define MCP25XXFD_CAN_OBJ_ID_SID_BITS		11
+#define MCP25XXFD_CAN_OBJ_ID_SID_SHIFT		0
+#define MCP25XXFD_CAN_OBJ_ID_SID_MASK					\
+	GENMASK(MCP25XXFD_CAN_OBJ_ID_SID_SHIFT +			\
+		MCP25XXFD_CAN_OBJ_ID_SID_BITS - 1,			\
+		MCP25XXFD_CAN_OBJ_ID_SID_SHIFT)
+#define MCP25XXFD_CAN_OBJ_ID_EID_BITS		18
+#define MCP25XXFD_CAN_OBJ_ID_EID_SHIFT		11
+#define MCP25XXFD_CAN_OBJ_ID_EID_MASK					\
+	GENMASK(MCP25XXFD_CAN_OBJ_ID_EID_SHIFT +			\
+		MCP25XXFD_CAN_OBJ_ID_EID_BITS - 1,			\
+		MCP25XXFD_CAN_OBJ_ID_EID_SHIFT)
+#define MCP25XXFD_CAN_OBJ_ID_SID_BIT11		BIT(29)
+
+#define MCP25XXFD_CAN_OBJ_FLAGS_DLC_BITS	4
+#define MCP25XXFD_CAN_OBJ_FLAGS_DLC_SHIFT	0
+#define MCP25XXFD_CAN_OBJ_FLAGS_DLC_MASK				\
+	GENMASK(MCP25XXFD_CAN_OBJ_FLAGS_DLC_SHIFT +			\
+		MCP25XXFD_CAN_OBJ_FLAGS_DLC_BITS - 1,			\
+		MCP25XXFD_CAN_OBJ_FLAGS_DLC_SHIFT)
+#define MCP25XXFD_CAN_OBJ_FLAGS_IDE		BIT(4)
+#define MCP25XXFD_CAN_OBJ_FLAGS_RTR		BIT(5)
+#define MCP25XXFD_CAN_OBJ_FLAGS_BRS		BIT(6)
+#define MCP25XXFD_CAN_OBJ_FLAGS_FDF		BIT(7)
+#define MCP25XXFD_CAN_OBJ_FLAGS_ESI		BIT(8)
+#define MCP25XXFD_CAN_OBJ_FLAGS_SEQ_BITS	7
+#define MCP25XXFD_CAN_OBJ_FLAGS_SEQ_SHIFT	9
+#define MCP25XXFD_CAN_OBJ_FLAGS_SEQ_MASK				\
+	GENMASK(MCP25XXFD_CAN_OBJ_FLAGS_SEQ_SHIFT +			\
+		MCP25XXFD_CAN_OBJ_FLAGS_SEQ_BITS - 1,			\
+		MCP25XXFD_CAN_OBJ_FLAGS_SEQ_SHIFT)
+#define MCP25XXFD_CAN_OBJ_FLAGS_FILHIT_BITS	11
+#define MCP25XXFD_CAN_OBJ_FLAGS_FILHIT_SHIFT	5
+#define MCP25XXFD_CAN_OBJ_FLAGS_FILHIT_MASK				\
+	GENMASK(MCP25XXFD_CAN_FLAGS_FILHIT_SHIFT +			\
+		MCP25XXFD_CAN_FLAGS_FILHIT_BITS - 1,			\
+		MCP25XXFD_CAN_FLAGS_FILHIT_SHIFT)
+
+/* custom status error */
+#define MCP25XXFD_CAN_ERR_DATA7_MCP25XXFD_SERR_RX BIT(0)
+#define MCP25XXFD_CAN_ERR_DATA7_MCP25XXFD_SERR_TX BIT(1)
+#define MCP25XXFD_CAN_ERR_DATA7_MCP25XXFD_ECC	  BIT(2)
+
+#endif /* __MCP25XXFD_REGS_H */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/ov5640/Makefile b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/ov5640/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..b77f3c0da3635f5be2608b819f6d66bdf3ab2f77
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/ov5640/Makefile
@@ -0,0 +1,34 @@
+
+_uname_r := $(shell uname -r)
+_BUILD   := /lib/modules/$(_uname_r)/build
+_PWD     := $(shell pwd)
+_DEPMOD  ?= depmod -a
+
+# If KERNELRELEASE is defined, we've been invoked from the
+# kernel build system and can use its language
+ifneq ($(KERNELRELEASE),)
+
+#snd-soc-imx-wm8960-objs := imx-wm8960.o
+obj-m += ov5640_v2.o
+
+else
+_class  := drivers/i2c
+
+DEST  := /lib/modules/$(_uname_r)/kernel
+
+all:
+	make -C ${_BUILD} M=$(_PWD) modules
+
+clean:
+	make -C ${_BUILD} M=$(_PWD) clean
+
+install:
+	cp ov5640_v2.ko ${DEST}/${_class}/
+	$(_DEPMOD)
+	echo ov5640_v2.ko >> /etc/modules
+uninstall:
+	rm -f ${DEST}/${_class}/ov5640_v2.ko 
+	$(_DEPMOD)
+
+.PHONY: all clean install uninstall
+endif
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/ov5640/ov5640_v2.c b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/ov5640/ov5640_v2.c
new file mode 100644
index 0000000000000000000000000000000000000000..5b90325284f6048b2749cabef34c70760392ef35
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/ov5640/ov5640_v2.c
@@ -0,0 +1,1911 @@
+/*
+ * Copyright (C) 2012-2015 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/device.h>
+#include <linux/i2c.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/of_gpio.h>
+#include <linux/pinctrl/consumer.h>
+#include <linux/regulator/consumer.h>
+#include <linux/v4l2-mediabus.h>
+#include <media/v4l2-device.h>
+#include <media/v4l2-ctrls.h>
+
+#define OV5640_VOLTAGE_ANALOG               2800000
+#define OV5640_VOLTAGE_DIGITAL_CORE         1500000
+#define OV5640_VOLTAGE_DIGITAL_IO           1800000
+
+#define MIN_FPS 15
+#define MAX_FPS 30
+#define DEFAULT_FPS 30
+
+#define OV5640_XCLK_MIN 6000000
+#define OV5640_XCLK_MAX 24000000
+
+#define OV5640_CHIP_ID_HIGH_BYTE        0x300A
+#define OV5640_CHIP_ID_LOW_BYTE         0x300B
+
+enum ov5640_mode {
+	ov5640_mode_MIN = 0,
+	ov5640_mode_VGA_640_480 = 0,
+	ov5640_mode_QVGA_320_240 = 1,
+	ov5640_mode_NTSC_720_480 = 2,
+	ov5640_mode_PAL_720_576 = 3,
+	ov5640_mode_720P_1280_720 = 4,
+	ov5640_mode_1080P_1920_1080 = 5,
+	ov5640_mode_QSXGA_2592_1944 = 6,
+	ov5640_mode_QCIF_176_144 = 7,
+	ov5640_mode_XGA_1024_768 = 8,
+	ov5640_mode_MAX = 8
+};
+
+enum ov5640_frame_rate {
+	ov5640_15_fps,
+	ov5640_30_fps
+};
+
+static int ov5640_framerates[] = {
+	[ov5640_15_fps] = 15,
+	[ov5640_30_fps] = 30,
+};
+
+struct ov5640_datafmt {
+	u32	code;
+	enum v4l2_colorspace		colorspace;
+};
+
+struct reg_value {
+	u16 u16RegAddr;
+	u8 u8Val;
+	u8 u8Mask;
+	u32 u32Delay_ms;
+};
+
+struct ov5640_mode_info {
+	enum ov5640_mode mode;
+	u32 width;
+	u32 height;
+	struct reg_value *init_data_ptr;
+	u32 init_data_size;
+};
+
+struct ov5640 {
+	struct v4l2_subdev		subdev;
+	struct i2c_client *i2c_client;
+	struct v4l2_pix_format pix;
+	const struct ov5640_datafmt	*fmt;
+	struct v4l2_captureparm streamcap;
+	bool on;
+
+	/* control settings */
+	int brightness;
+	int hue;
+	int contrast;
+	int saturation;
+	int red;
+	int green;
+	int blue;
+	int ae_mode;
+
+	u32 mclk;
+	u8 mclk_source;
+	struct clk *sensor_clk;
+	int csi;
+
+	void (*io_init)(void);
+};
+
+/*!
+ * Maintains the information on the current state of the sesor.
+ */
+static struct ov5640 ov5640_data;
+static int pwn_gpio, rst_gpio;
+static int prev_sysclk;
+static int AE_Target = 52, night_mode;
+static int prev_HTS;
+static int AE_high, AE_low;
+
+static struct reg_value ov5640_global_init_setting[] = {
+	{0x3008, 0x42, 0, 0},
+	{0x3103, 0x03, 0, 0}, {0x3017, 0xff, 0, 0}, {0x3018, 0xff, 0, 0},
+	{0x3034, 0x1a, 0, 0}, {0x3037, 0x13, 0, 0}, {0x3108, 0x01, 0, 0},
+	{0x3630, 0x36, 0, 0}, {0x3631, 0x0e, 0, 0}, {0x3632, 0xe2, 0, 0},
+	{0x3633, 0x12, 0, 0}, {0x3621, 0xe0, 0, 0}, {0x3704, 0xa0, 0, 0},
+	{0x3703, 0x5a, 0, 0}, {0x3715, 0x78, 0, 0}, {0x3717, 0x01, 0, 0},
+	{0x370b, 0x60, 0, 0}, {0x3705, 0x1a, 0, 0}, {0x3905, 0x02, 0, 0},
+	{0x3906, 0x10, 0, 0}, {0x3901, 0x0a, 0, 0}, {0x3731, 0x12, 0, 0},
+	{0x3600, 0x08, 0, 0}, {0x3601, 0x33, 0, 0}, {0x302d, 0x60, 0, 0},
+	{0x3620, 0x52, 0, 0}, {0x371b, 0x20, 0, 0}, {0x471c, 0x50, 0, 0},
+	{0x3a13, 0x43, 0, 0}, {0x3a18, 0x00, 0, 0}, {0x3a19, 0x7c, 0, 0},
+	{0x3635, 0x13, 0, 0}, {0x3636, 0x03, 0, 0}, {0x3634, 0x40, 0, 0},
+	{0x3622, 0x01, 0, 0}, {0x3c01, 0x34, 0, 0}, {0x3c04, 0x28, 0, 0},
+	{0x3c05, 0x98, 0, 0}, {0x3c06, 0x00, 0, 0}, {0x3c07, 0x07, 0, 0},
+	{0x3c08, 0x00, 0, 0}, {0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0},
+	{0x3c0b, 0x40, 0, 0}, {0x3810, 0x00, 0, 0}, {0x3811, 0x10, 0, 0},
+	{0x3812, 0x00, 0, 0}, {0x3708, 0x64, 0, 0}, {0x4001, 0x02, 0, 0},
+	{0x4005, 0x1a, 0, 0}, {0x3000, 0x00, 0, 0}, {0x3004, 0xff, 0, 0},
+	{0x300e, 0x58, 0, 0}, {0x302e, 0x00, 0, 0}, {0x4300, 0x30, 0, 0},
+	{0x501f, 0x00, 0, 0}, {0x440e, 0x00, 0, 0}, {0x5000, 0xa7, 0, 0},
+	{0x3008, 0x02, 0, 0},
+};
+
+static struct reg_value ov5640_init_setting_30fps_VGA[] = {
+	{0x3008, 0x42, 0, 0},
+	{0x3103, 0x03, 0, 0}, {0x3017, 0xff, 0, 0}, {0x3018, 0xff, 0, 0},
+	{0x3034, 0x1a, 0, 0}, {0x3035, 0x11, 0, 0}, {0x3036, 0x46, 0, 0},
+	{0x3037, 0x13, 0, 0}, {0x3108, 0x01, 0, 0}, {0x3630, 0x36, 0, 0},
+	{0x3631, 0x0e, 0, 0}, {0x3632, 0xe2, 0, 0}, {0x3633, 0x12, 0, 0},
+	{0x3621, 0xe0, 0, 0}, {0x3704, 0xa0, 0, 0}, {0x3703, 0x5a, 0, 0},
+	{0x3715, 0x78, 0, 0}, {0x3717, 0x01, 0, 0}, {0x370b, 0x60, 0, 0},
+	{0x3705, 0x1a, 0, 0}, {0x3905, 0x02, 0, 0}, {0x3906, 0x10, 0, 0},
+	{0x3901, 0x0a, 0, 0}, {0x3731, 0x12, 0, 0}, {0x3600, 0x08, 0, 0},
+	{0x3601, 0x33, 0, 0}, {0x302d, 0x60, 0, 0}, {0x3620, 0x52, 0, 0},
+	{0x371b, 0x20, 0, 0}, {0x471c, 0x50, 0, 0}, {0x3a13, 0x43, 0, 0},
+	{0x3a18, 0x00, 0, 0}, {0x3a19, 0xf8, 0, 0}, {0x3635, 0x13, 0, 0},
+	{0x3636, 0x03, 0, 0}, {0x3634, 0x40, 0, 0}, {0x3622, 0x01, 0, 0},
+	{0x3c01, 0x34, 0, 0}, {0x3c04, 0x28, 0, 0}, {0x3c05, 0x98, 0, 0},
+	{0x3c06, 0x00, 0, 0}, {0x3c07, 0x08, 0, 0}, {0x3c08, 0x00, 0, 0},
+	{0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0},
+	{0x3820, 0x41, 0, 0}, {0x3821, 0x07, 0, 0}, {0x3814, 0x31, 0, 0},
+	{0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0},
+	{0x3802, 0x00, 0, 0}, {0x3803, 0x04, 0, 0}, {0x3804, 0x0a, 0, 0},
+	{0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0}, {0x3807, 0x9b, 0, 0},
+	{0x3808, 0x02, 0, 0}, {0x3809, 0x80, 0, 0}, {0x380a, 0x01, 0, 0},
+	{0x380b, 0xe0, 0, 0}, {0x380c, 0x07, 0, 0}, {0x380d, 0x68, 0, 0},
+	{0x380e, 0x03, 0, 0}, {0x380f, 0xd8, 0, 0}, {0x3810, 0x00, 0, 0},
+	{0x3811, 0x10, 0, 0}, {0x3812, 0x00, 0, 0}, {0x3813, 0x06, 0, 0},
+	{0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0}, {0x3708, 0x64, 0, 0},
+	{0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x03, 0, 0},
+	{0x3a03, 0xd8, 0, 0}, {0x3a08, 0x01, 0, 0}, {0x3a09, 0x27, 0, 0},
+	{0x3a0a, 0x00, 0, 0}, {0x3a0b, 0xf6, 0, 0}, {0x3a0e, 0x03, 0, 0},
+	{0x3a0d, 0x04, 0, 0}, {0x3a14, 0x03, 0, 0}, {0x3a15, 0xd8, 0, 0},
+	{0x4001, 0x02, 0, 0}, {0x4004, 0x02, 0, 0}, {0x3000, 0x00, 0, 0},
+	{0x3002, 0x1c, 0, 0}, {0x3004, 0xff, 0, 0}, {0x3006, 0xc3, 0, 0},
+	{0x300e, 0x58, 0, 0}, {0x302e, 0x00, 0, 0}, {0x4300, 0x30, 0, 0},
+	{0x501f, 0x00, 0, 0}, {0x4713, 0x03, 0, 0}, {0x4407, 0x04, 0, 0},
+	{0x440e, 0x00, 0, 0}, {0x460b, 0x35, 0, 0}, {0x460c, 0x22, 0, 0},
+	{0x4837, 0x22, 0, 0}, {0x3824, 0x02, 0, 0}, {0x5000, 0xa7, 0, 0},
+	{0x5001, 0xa3, 0, 0}, {0x5180, 0xff, 0, 0}, {0x5181, 0xf2, 0, 0},
+	{0x5182, 0x00, 0, 0}, {0x5183, 0x14, 0, 0}, {0x5184, 0x25, 0, 0},
+	{0x5185, 0x24, 0, 0}, {0x5186, 0x09, 0, 0}, {0x5187, 0x09, 0, 0},
+	{0x5188, 0x09, 0, 0}, {0x5189, 0x88, 0, 0}, {0x518a, 0x54, 0, 0},
+	{0x518b, 0xee, 0, 0}, {0x518c, 0xb2, 0, 0}, {0x518d, 0x50, 0, 0},
+	{0x518e, 0x34, 0, 0}, {0x518f, 0x6b, 0, 0}, {0x5190, 0x46, 0, 0},
+	{0x5191, 0xf8, 0, 0}, {0x5192, 0x04, 0, 0}, {0x5193, 0x70, 0, 0},
+	{0x5194, 0xf0, 0, 0}, {0x5195, 0xf0, 0, 0}, {0x5196, 0x03, 0, 0},
+	{0x5197, 0x01, 0, 0}, {0x5198, 0x04, 0, 0}, {0x5199, 0x6c, 0, 0},
+	{0x519a, 0x04, 0, 0}, {0x519b, 0x00, 0, 0}, {0x519c, 0x09, 0, 0},
+	{0x519d, 0x2b, 0, 0}, {0x519e, 0x38, 0, 0}, {0x5381, 0x1e, 0, 0},
+	{0x5382, 0x5b, 0, 0}, {0x5383, 0x08, 0, 0}, {0x5384, 0x0a, 0, 0},
+	{0x5385, 0x7e, 0, 0}, {0x5386, 0x88, 0, 0}, {0x5387, 0x7c, 0, 0},
+	{0x5388, 0x6c, 0, 0}, {0x5389, 0x10, 0, 0}, {0x538a, 0x01, 0, 0},
+	{0x538b, 0x98, 0, 0}, {0x5300, 0x08, 0, 0}, {0x5301, 0x30, 0, 0},
+	{0x5302, 0x10, 0, 0}, {0x5303, 0x00, 0, 0}, {0x5304, 0x08, 0, 0},
+	{0x5305, 0x30, 0, 0}, {0x5306, 0x08, 0, 0}, {0x5307, 0x16, 0, 0},
+	{0x5309, 0x08, 0, 0}, {0x530a, 0x30, 0, 0}, {0x530b, 0x04, 0, 0},
+	{0x530c, 0x06, 0, 0}, {0x5480, 0x01, 0, 0}, {0x5481, 0x08, 0, 0},
+	{0x5482, 0x14, 0, 0}, {0x5483, 0x28, 0, 0}, {0x5484, 0x51, 0, 0},
+	{0x5485, 0x65, 0, 0}, {0x5486, 0x71, 0, 0}, {0x5487, 0x7d, 0, 0},
+	{0x5488, 0x87, 0, 0}, {0x5489, 0x91, 0, 0}, {0x548a, 0x9a, 0, 0},
+	{0x548b, 0xaa, 0, 0}, {0x548c, 0xb8, 0, 0}, {0x548d, 0xcd, 0, 0},
+	{0x548e, 0xdd, 0, 0}, {0x548f, 0xea, 0, 0}, {0x5490, 0x1d, 0, 0},
+	{0x5580, 0x02, 0, 0}, {0x5583, 0x40, 0, 0}, {0x5584, 0x10, 0, 0},
+	{0x5589, 0x10, 0, 0}, {0x558a, 0x00, 0, 0}, {0x558b, 0xf8, 0, 0},
+	{0x5800, 0x23, 0, 0}, {0x5801, 0x14, 0, 0}, {0x5802, 0x0f, 0, 0},
+	{0x5803, 0x0f, 0, 0}, {0x5804, 0x12, 0, 0}, {0x5805, 0x26, 0, 0},
+	{0x5806, 0x0c, 0, 0}, {0x5807, 0x08, 0, 0}, {0x5808, 0x05, 0, 0},
+	{0x5809, 0x05, 0, 0}, {0x580a, 0x08, 0, 0}, {0x580b, 0x0d, 0, 0},
+	{0x580c, 0x08, 0, 0}, {0x580d, 0x03, 0, 0}, {0x580e, 0x00, 0, 0},
+	{0x580f, 0x00, 0, 0}, {0x5810, 0x03, 0, 0}, {0x5811, 0x09, 0, 0},
+	{0x5812, 0x07, 0, 0}, {0x5813, 0x03, 0, 0}, {0x5814, 0x00, 0, 0},
+	{0x5815, 0x01, 0, 0}, {0x5816, 0x03, 0, 0}, {0x5817, 0x08, 0, 0},
+	{0x5818, 0x0d, 0, 0}, {0x5819, 0x08, 0, 0}, {0x581a, 0x05, 0, 0},
+	{0x581b, 0x06, 0, 0}, {0x581c, 0x08, 0, 0}, {0x581d, 0x0e, 0, 0},
+	{0x581e, 0x29, 0, 0}, {0x581f, 0x17, 0, 0}, {0x5820, 0x11, 0, 0},
+	{0x5821, 0x11, 0, 0}, {0x5822, 0x15, 0, 0}, {0x5823, 0x28, 0, 0},
+	{0x5824, 0x46, 0, 0}, {0x5825, 0x26, 0, 0}, {0x5826, 0x08, 0, 0},
+	{0x5827, 0x26, 0, 0}, {0x5828, 0x64, 0, 0}, {0x5829, 0x26, 0, 0},
+	{0x582a, 0x24, 0, 0}, {0x582b, 0x22, 0, 0}, {0x582c, 0x24, 0, 0},
+	{0x582d, 0x24, 0, 0}, {0x582e, 0x06, 0, 0}, {0x582f, 0x22, 0, 0},
+	{0x5830, 0x40, 0, 0}, {0x5831, 0x42, 0, 0}, {0x5832, 0x24, 0, 0},
+	{0x5833, 0x26, 0, 0}, {0x5834, 0x24, 0, 0}, {0x5835, 0x22, 0, 0},
+	{0x5836, 0x22, 0, 0}, {0x5837, 0x26, 0, 0}, {0x5838, 0x44, 0, 0},
+	{0x5839, 0x24, 0, 0}, {0x583a, 0x26, 0, 0}, {0x583b, 0x28, 0, 0},
+	{0x583c, 0x42, 0, 0}, {0x583d, 0xce, 0, 0}, {0x5025, 0x00, 0, 0},
+	{0x3a0f, 0x30, 0, 0}, {0x3a10, 0x28, 0, 0}, {0x3a1b, 0x30, 0, 0},
+	{0x3a1e, 0x26, 0, 0}, {0x3a11, 0x60, 0, 0}, {0x3a1f, 0x14, 0, 0},
+	{0x3008, 0x02, 0, 0}, {0x3034, 0x1a, 0, 0}, {0x3035, 0x11, 0, 0},
+	{0x3036, 0x46, 0, 0}, {0x3037, 0x13, 0, 0},
+};
+
+static struct reg_value ov5640_setting_30fps_VGA_640_480[] = {
+	{0x3c07, 0x08, 0, 0}, {0x3820, 0x41, 0, 0}, {0x3821, 0x07, 0, 0},
+	{0x3814, 0x31, 0, 0}, {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0},
+	{0x3801, 0x00, 0, 0}, {0x3802, 0x00, 0, 0}, {0x3803, 0x04, 0, 0},
+	{0x3804, 0x0a, 0, 0}, {0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0},
+	{0x3807, 0x9b, 0, 0}, {0x3808, 0x02, 0, 0}, {0x3809, 0x80, 0, 0},
+	{0x380a, 0x01, 0, 0}, {0x380b, 0xe0, 0, 0}, {0x380c, 0x07, 0, 0},
+	{0x380d, 0x68, 0, 0}, {0x380e, 0x03, 0, 0}, {0x380f, 0xd8, 0, 0},
+	{0x3813, 0x06, 0, 0}, {0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0},
+	{0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x0b, 0, 0},
+	{0x3a03, 0x88, 0, 0}, {0x3a14, 0x0b, 0, 0}, {0x3a15, 0x88, 0, 0},
+	{0x4004, 0x02, 0, 0}, {0x3002, 0x1c, 0, 0}, {0x3006, 0xc3, 0, 0},
+	{0x4713, 0x03, 0, 0}, {0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0},
+	{0x460c, 0x22, 0, 0}, {0x4837, 0x22, 0, 0}, {0x3824, 0x02, 0, 0},
+	{0x5001, 0xa3, 0, 0}, {0x3034, 0x1a, 0, 0}, {0x3035, 0x11, 0, 0},
+	{0x3036, 0x46, 0, 0}, {0x3037, 0x13, 0, 0}, {0x3503, 0x00, 0, 0},
+};
+
+static struct reg_value ov5640_setting_15fps_VGA_640_480[] = {
+	//{0x3c07, 0x08, 0, 0}, {0x3820, 0x41, 0, 0}, {0x3821, 0x07, 0, 0},
+	{0x3c07, 0x08, 0, 0}, {0x3820, 0x46, 0, 0}, {0x3821, 0x07, 0, 0},
+	{0x3814, 0x31, 0, 0}, {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0},
+	{0x3801, 0x00, 0, 0}, {0x3802, 0x00, 0, 0}, {0x3803, 0x04, 0, 0},
+	{0x3804, 0x0a, 0, 0}, {0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0},
+	{0x3807, 0x9b, 0, 0}, {0x3808, 0x02, 0, 0}, {0x3809, 0x80, 0, 0},
+	{0x380a, 0x01, 0, 0}, {0x380b, 0xe0, 0, 0}, {0x380c, 0x07, 0, 0},
+	{0x380d, 0x68, 0, 0}, {0x380e, 0x03, 0, 0}, {0x380f, 0xd8, 0, 0},
+	{0x3813, 0x06, 0, 0}, {0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0},
+	{0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x0b, 0, 0},
+	{0x3a03, 0x88, 0, 0}, {0x3a14, 0x0b, 0, 0}, {0x3a15, 0x88, 0, 0},
+	{0x4004, 0x02, 0, 0}, {0x3002, 0x1c, 0, 0}, {0x3006, 0xc3, 0, 0},
+	{0x4713, 0x03, 0, 0}, {0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0},
+	{0x460c, 0x22, 0, 0}, {0x4837, 0x22, 0, 0}, {0x3824, 0x02, 0, 0},
+	{0x5001, 0xa3, 0, 0}, {0x3034, 0x1a, 0, 0}, {0x3035, 0x21, 0, 0},
+	{0x3036, 0x46, 0, 0}, {0x3037, 0x13, 0, 0}, {0x3503, 0x00, 0, 0},
+};
+
+static struct reg_value ov5640_setting_30fps_QVGA_320_240[] = {	
+	//{0x3c07, 0x08, 0, 0}, {0x3820, 0x41, 0, 0}, {0x3821, 0x07, 0, 0},
+	{0x3c07, 0x08, 0, 0}, {0x3820, 0x46, 0, 0}, {0x3821, 0x07, 0, 0},
+	{0x3814, 0x31, 0, 0}, {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0},
+	{0x3801, 0x00, 0, 0}, {0x3802, 0x00, 0, 0}, {0x3803, 0x04, 0, 0},
+	{0x3804, 0x0a, 0, 0}, {0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0},
+	{0x3807, 0x9b, 0, 0}, {0x3808, 0x01, 0, 0}, {0x3809, 0x40, 0, 0},
+	{0x380a, 0x00, 0, 0}, {0x380b, 0xf0, 0, 0}, {0x380c, 0x07, 0, 0},
+	{0x380d, 0x68, 0, 0}, {0x380e, 0x03, 0, 0}, {0x380f, 0xd8, 0, 0},
+	{0x3813, 0x06, 0, 0}, {0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0},
+	{0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x0b, 0, 0},
+	{0x3a03, 0x88, 0, 0}, {0x3a14, 0x0b, 0, 0}, {0x3a15, 0x88, 0, 0},
+	{0x4004, 0x02, 0, 0}, {0x3002, 0x1c, 0, 0}, {0x3006, 0xc3, 0, 0},
+	{0x4713, 0x03, 0, 0}, {0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0},
+	{0x460c, 0x22, 0, 0}, {0x4837, 0x22, 0, 0}, {0x3824, 0x02, 0, 0},
+	{0x5001, 0xa3, 0, 0}, {0x3034, 0x1a, 0, 0}, {0x3035, 0x11, 0, 0},
+	{0x3036, 0x46, 0, 0}, {0x3037, 0x13, 0, 0},
+};
+
+static struct reg_value ov5640_setting_15fps_QVGA_320_240[] = {
+	//{0x3c07, 0x08, 0, 0}, {0x3820, 0x41, 0, 0}, {0x3821, 0x07, 0, 0},
+	{0x3c07, 0x08, 0, 0}, {0x3820, 0x46, 0, 0}, {0x3821, 0x07, 0, 0}, 
+	{0x3814, 0x31, 0, 0}, {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0},
+	{0x3801, 0x00, 0, 0}, {0x3802, 0x00, 0, 0}, {0x3803, 0x04, 0, 0},
+	{0x3804, 0x0a, 0, 0}, {0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0},
+	{0x3807, 0x9b, 0, 0}, {0x3808, 0x01, 0, 0}, {0x3809, 0x40, 0, 0},
+	{0x380a, 0x00, 0, 0}, {0x380b, 0xf0, 0, 0}, {0x380c, 0x07, 0, 0},
+	{0x380d, 0x68, 0, 0}, {0x380e, 0x03, 0, 0}, {0x380f, 0xd8, 0, 0},
+	{0x3813, 0x06, 0, 0}, {0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0},
+	{0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x0b, 0, 0},
+	{0x3a03, 0x88, 0, 0}, {0x3a14, 0x0b, 0, 0}, {0x3a15, 0x88, 0, 0},
+	{0x4004, 0x02, 0, 0}, {0x3002, 0x1c, 0, 0}, {0x3006, 0xc3, 0, 0},
+	{0x4713, 0x03, 0, 0}, {0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0},
+	{0x460c, 0x22, 0, 0}, {0x4837, 0x22, 0, 0}, {0x3824, 0x02, 0, 0},
+	{0x5001, 0xa3, 0, 0}, {0x3034, 0x1a, 0, 0}, {0x3035, 0x21, 0, 0},
+	{0x3036, 0x46, 0, 0}, {0x3037, 0x13, 0, 0},
+};
+
+static struct reg_value ov5640_setting_30fps_NTSC_720_480[] = {
+	{0x3c07, 0x08, 0, 0}, {0x3820, 0x41, 0, 0}, {0x3821, 0x07, 0, 0},
+	{0x3814, 0x31, 0, 0}, {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0},
+	{0x3801, 0x00, 0, 0}, {0x3802, 0x00, 0, 0}, {0x3803, 0x04, 0, 0},
+	{0x3804, 0x0a, 0, 0}, {0x3805, 0x3f, 0, 0}, {0x3806, 0x06, 0, 0},
+	{0x3807, 0xd4, 0, 0}, {0x3808, 0x02, 0, 0}, {0x3809, 0xd0, 0, 0},
+	{0x380a, 0x01, 0, 0}, {0x380b, 0xe0, 0, 0}, {0x380c, 0x07, 0, 0},
+	{0x380d, 0x68, 0, 0}, {0x380e, 0x03, 0, 0}, {0x380f, 0xd8, 0, 0},
+	{0x3813, 0x06, 0, 0}, {0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0},
+	{0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x0b, 0, 0},
+	{0x3a03, 0x88, 0, 0}, {0x3a14, 0x0b, 0, 0}, {0x3a15, 0x88, 0, 0},
+	{0x4004, 0x02, 0, 0}, {0x3002, 0x1c, 0, 0}, {0x3006, 0xc3, 0, 0},
+	{0x4713, 0x03, 0, 0}, {0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0},
+	{0x460c, 0x22, 0, 0}, {0x4837, 0x22, 0, 0}, {0x3824, 0x02, 0, 0},
+	{0x5001, 0xa3, 0, 0}, {0x3034, 0x1a, 0, 0}, {0x3035, 0x11, 0, 0},
+	{0x3036, 0x46, 0, 0}, {0x3037, 0x13, 0, 0},
+};
+
+static struct reg_value ov5640_setting_15fps_NTSC_720_480[] = {
+	{0x3c07, 0x08, 0, 0}, {0x3820, 0x41, 0, 0}, {0x3821, 0x07, 0, 0},
+	{0x3814, 0x31, 0, 0}, {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0},
+	{0x3801, 0x00, 0, 0}, {0x3802, 0x00, 0, 0}, {0x3803, 0x04, 0, 0},
+	{0x3804, 0x0a, 0, 0}, {0x3805, 0x3f, 0, 0}, {0x3806, 0x06, 0, 0},
+	{0x3807, 0xd4, 0, 0}, {0x3808, 0x02, 0, 0}, {0x3809, 0xd0, 0, 0},
+	{0x380a, 0x01, 0, 0}, {0x380b, 0xe0, 0, 0}, {0x380c, 0x07, 0, 0},
+	{0x380d, 0x68, 0, 0}, {0x380e, 0x03, 0, 0}, {0x380f, 0xd8, 0, 0},
+	{0x3813, 0x06, 0, 0}, {0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0},
+	{0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x0b, 0, 0},
+	{0x3a03, 0x88, 0, 0}, {0x3a14, 0x0b, 0, 0}, {0x3a15, 0x88, 0, 0},
+	{0x4004, 0x02, 0, 0}, {0x3002, 0x1c, 0, 0}, {0x3006, 0xc3, 0, 0},
+	{0x4713, 0x03, 0, 0}, {0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0},
+	{0x460c, 0x22, 0, 0}, {0x4837, 0x22, 0, 0}, {0x3824, 0x02, 0, 0},
+	{0x5001, 0xa3, 0, 0}, {0x3034, 0x1a, 0, 0}, {0x3035, 0x21, 0, 0},
+	{0x3036, 0x46, 0, 0}, {0x3037, 0x13, 0, 0},
+};
+
+static struct reg_value ov5640_setting_30fps_PAL_720_576[] = {
+	{0x3c07, 0x08, 0, 0}, {0x3820, 0x41, 0, 0}, {0x3821, 0x07, 0, 0},
+	{0x3814, 0x31, 0, 0}, {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0},
+	{0x3801, 0x60, 0, 0}, {0x3802, 0x00, 0, 0}, {0x3803, 0x04, 0, 0},
+	{0x3804, 0x09, 0, 0}, {0x3805, 0x7e, 0, 0}, {0x3806, 0x07, 0, 0},
+	{0x3807, 0x9b, 0, 0}, {0x3808, 0x02, 0, 0}, {0x3809, 0xd0, 0, 0},
+	{0x380a, 0x02, 0, 0}, {0x380b, 0x40, 0, 0}, {0x380c, 0x07, 0, 0},
+	{0x380d, 0x68, 0, 0}, {0x380e, 0x03, 0, 0}, {0x380f, 0xd8, 0, 0},
+	{0x3813, 0x06, 0, 0}, {0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0},
+	{0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x0b, 0, 0},
+	{0x3a03, 0x88, 0, 0}, {0x3a14, 0x0b, 0, 0}, {0x3a15, 0x88, 0, 0},
+	{0x4004, 0x02, 0, 0}, {0x3002, 0x1c, 0, 0}, {0x3006, 0xc3, 0, 0},
+	{0x4713, 0x03, 0, 0}, {0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0},
+	{0x460c, 0x22, 0, 0}, {0x4837, 0x22, 0, 0}, {0x3824, 0x02, 0, 0},
+	{0x5001, 0xa3, 0, 0}, {0x3034, 0x1a, 0, 0}, {0x3035, 0x11, 0, 0},
+	{0x3036, 0x46, 0, 0}, {0x3037, 0x13, 0, 0},
+};
+
+static struct reg_value ov5640_setting_15fps_PAL_720_576[] = {
+	{0x3c07, 0x08, 0, 0}, {0x3820, 0x41, 0, 0}, {0x3821, 0x07, 0, 0},
+	{0x3814, 0x31, 0, 0}, {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0},
+	{0x3801, 0x60, 0, 0}, {0x3802, 0x00, 0, 0}, {0x3803, 0x04, 0, 0},
+	{0x3804, 0x09, 0, 0}, {0x3805, 0x7e, 0, 0}, {0x3806, 0x07, 0, 0},
+	{0x3807, 0x9b, 0, 0}, {0x3808, 0x02, 0, 0}, {0x3809, 0xd0, 0, 0},
+	{0x380a, 0x02, 0, 0}, {0x380b, 0x40, 0, 0}, {0x380c, 0x07, 0, 0},
+	{0x380d, 0x68, 0, 0}, {0x380e, 0x03, 0, 0}, {0x380f, 0xd8, 0, 0},
+	{0x3813, 0x06, 0, 0}, {0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0},
+	{0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x0b, 0, 0},
+	{0x3a03, 0x88, 0, 0}, {0x3a14, 0x0b, 0, 0}, {0x3a15, 0x88, 0, 0},
+	{0x4004, 0x02, 0, 0}, {0x3002, 0x1c, 0, 0}, {0x3006, 0xc3, 0, 0},
+	{0x4713, 0x03, 0, 0}, {0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0},
+	{0x460c, 0x22, 0, 0}, {0x4837, 0x22, 0, 0}, {0x3824, 0x02, 0, 0},
+	{0x5001, 0xa3, 0, 0}, {0x3034, 0x1a, 0, 0}, {0x3035, 0x21, 0, 0},
+	{0x3036, 0x46, 0, 0}, {0x3037, 0x13, 0, 0},
+};
+
+static struct reg_value ov5640_setting_30fps_720P_1280_720[] = {
+	{0x3035, 0x21, 0, 0}, {0x3036, 0x69, 0, 0}, {0x3c07, 0x07, 0, 0},
+	{0x3820, 0x41, 0, 0}, {0x3821, 0x07, 0, 0}, {0x3814, 0x31, 0, 0},
+	{0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0},
+	{0x3802, 0x00, 0, 0}, {0x3803, 0xfa, 0, 0}, {0x3804, 0x0a, 0, 0},
+	{0x3805, 0x3f, 0, 0}, {0x3806, 0x06, 0, 0}, {0x3807, 0xa9, 0, 0},
+	{0x3808, 0x05, 0, 0}, {0x3809, 0x00, 0, 0}, {0x380a, 0x02, 0, 0},
+	{0x380b, 0xd0, 0, 0}, {0x380c, 0x07, 0, 0}, {0x380d, 0x64, 0, 0},
+	{0x380e, 0x02, 0, 0}, {0x380f, 0xe4, 0, 0}, {0x3813, 0x04, 0, 0},
+	{0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0}, {0x3709, 0x52, 0, 0},
+	{0x370c, 0x03, 0, 0}, {0x3a02, 0x02, 0, 0}, {0x3a03, 0xe0, 0, 0},
+	{0x3a14, 0x02, 0, 0}, {0x3a15, 0xe0, 0, 0}, {0x4004, 0x02, 0, 0},
+	{0x3002, 0x1c, 0, 0}, {0x3006, 0xc3, 0, 0}, {0x4713, 0x03, 0, 0},
+	{0x4407, 0x04, 0, 0}, {0x460b, 0x37, 0, 0}, {0x460c, 0x20, 0, 0},
+	{0x4837, 0x16, 0, 0}, {0x3824, 0x04, 0, 0}, {0x5001, 0x83, 0, 0},
+	{0x3503, 0x00, 0, 0},
+};
+
+static struct reg_value ov5640_setting_15fps_720P_1280_720[] = {
+	{0x3035, 0x41, 0, 0}, {0x3036, 0x69, 0, 0}, {0x3c07, 0x07, 0, 0},
+	{0x3820, 0x41, 0, 0}, {0x3821, 0x07, 0, 0}, {0x3814, 0x31, 0, 0},
+	{0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0},
+	{0x3802, 0x00, 0, 0}, {0x3803, 0xfa, 0, 0}, {0x3804, 0x0a, 0, 0},
+	{0x3805, 0x3f, 0, 0}, {0x3806, 0x06, 0, 0}, {0x3807, 0xa9, 0, 0},
+	{0x3808, 0x05, 0, 0}, {0x3809, 0x00, 0, 0}, {0x380a, 0x02, 0, 0},
+	{0x380b, 0xd0, 0, 0}, {0x380c, 0x07, 0, 0}, {0x380d, 0x64, 0, 0},
+	{0x380e, 0x02, 0, 0}, {0x380f, 0xe4, 0, 0}, {0x3813, 0x04, 0, 0},
+	{0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0}, {0x3709, 0x52, 0, 0},
+	{0x370c, 0x03, 0, 0}, {0x3a02, 0x02, 0, 0}, {0x3a03, 0xe0, 0, 0},
+	{0x3a14, 0x02, 0, 0}, {0x3a15, 0xe0, 0, 0}, {0x4004, 0x02, 0, 0},
+	{0x3002, 0x1c, 0, 0}, {0x3006, 0xc3, 0, 0}, {0x4713, 0x03, 0, 0},
+	{0x4407, 0x04, 0, 0}, {0x460b, 0x37, 0, 0}, {0x460c, 0x20, 0, 0},
+	{0x4837, 0x16, 0, 0}, {0x3824, 0x04, 0, 0}, {0x5001, 0x83, 0, 0},
+	{0x3503, 0x00, 0, 0},
+};
+
+static struct reg_value ov5640_setting_30fps_QCIF_176_144[] = {
+	{0x3c07, 0x08, 0, 0}, {0x3820, 0x41, 0, 0}, {0x3821, 0x07, 0, 0},
+	{0x3814, 0x31, 0, 0}, {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0},
+	{0x3801, 0x00, 0, 0}, {0x3802, 0x00, 0, 0}, {0x3803, 0x04, 0, 0},
+	{0x3804, 0x0a, 0, 0}, {0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0},
+	{0x3807, 0x9b, 0, 0}, {0x3808, 0x00, 0, 0}, {0x3809, 0xb0, 0, 0},
+	{0x380a, 0x00, 0, 0}, {0x380b, 0x90, 0, 0}, {0x380c, 0x07, 0, 0},
+	{0x380d, 0x68, 0, 0}, {0x380e, 0x03, 0, 0}, {0x380f, 0xd8, 0, 0},
+	{0x3813, 0x06, 0, 0}, {0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0},
+	{0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x0b, 0, 0},
+	{0x3a03, 0x88, 0, 0}, {0x3a14, 0x0b, 0, 0}, {0x3a15, 0x88, 0, 0},
+	{0x4004, 0x02, 0, 0}, {0x3002, 0x1c, 0, 0}, {0x3006, 0xc3, 0, 0},
+	{0x4713, 0x03, 0, 0}, {0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0},
+	{0x460c, 0x22, 0, 0}, {0x4837, 0x22, 0, 0}, {0x3824, 0x02, 0, 0},
+	{0x5001, 0xa3, 0, 0}, {0x3034, 0x1a, 0, 0}, {0x3035, 0x11, 0, 0},
+	{0x3036, 0x46, 0, 0}, {0x3037, 0x13, 0, 0},
+};
+
+static struct reg_value ov5640_setting_15fps_QCIF_176_144[] = {
+	{0x3c07, 0x08, 0, 0}, {0x3820, 0x41, 0, 0}, {0x3821, 0x07, 0, 0},
+	{0x3814, 0x31, 0, 0}, {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0},
+	{0x3801, 0x00, 0, 0}, {0x3802, 0x00, 0, 0}, {0x3803, 0x04, 0, 0},
+	{0x3804, 0x0a, 0, 0}, {0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0},
+	{0x3807, 0x9b, 0, 0}, {0x3808, 0x00, 0, 0}, {0x3809, 0xb0, 0, 0},
+	{0x380a, 0x00, 0, 0}, {0x380b, 0x90, 0, 0}, {0x380c, 0x07, 0, 0},
+	{0x380d, 0x68, 0, 0}, {0x380e, 0x03, 0, 0}, {0x380f, 0xd8, 0, 0},
+	{0x3813, 0x06, 0, 0}, {0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0},
+	{0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x0b, 0, 0},
+	{0x3a03, 0x88, 0, 0}, {0x3a14, 0x0b, 0, 0}, {0x3a15, 0x88, 0, 0},
+	{0x4004, 0x02, 0, 0}, {0x3002, 0x1c, 0, 0}, {0x3006, 0xc3, 0, 0},
+	{0x4713, 0x03, 0, 0}, {0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0},
+	{0x460c, 0x22, 0, 0}, {0x4837, 0x22, 0, 0}, {0x3824, 0x02, 0, 0},
+	{0x5001, 0xa3, 0, 0}, {0x3034, 0x1a, 0, 0}, {0x3035, 0x21, 0, 0},
+	{0x3036, 0x46, 0, 0}, {0x3037, 0x13, 0, 0},
+};
+
+static struct reg_value ov5640_setting_30fps_XGA_1024_768[] = {
+	{0x3c07, 0x08, 0, 0}, {0x3820, 0x41, 0, 0}, {0x3821, 0x07, 0, 0},
+	{0x3814, 0x31, 0, 0}, {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0},
+	{0x3801, 0x00, 0, 0}, {0x3802, 0x00, 0, 0}, {0x3803, 0x04, 0, 0},
+	{0x3804, 0x0a, 0, 0}, {0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0},
+	{0x3807, 0x9b, 0, 0}, {0x3808, 0x04, 0, 0}, {0x3809, 0x00, 0, 0},
+	{0x380a, 0x03, 0, 0}, {0x380b, 0x00, 0, 0}, {0x380c, 0x07, 0, 0},
+	{0x380d, 0x68, 0, 0}, {0x380e, 0x03, 0, 0}, {0x380f, 0xd8, 0, 0},
+	{0x3813, 0x06, 0, 0}, {0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0},
+	{0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x0b, 0, 0},
+	{0x3a03, 0x88, 0, 0}, {0x3a14, 0x0b, 0, 0}, {0x3a15, 0x88, 0, 0},
+	{0x4004, 0x02, 0, 0}, {0x3002, 0x1c, 0, 0}, {0x3006, 0xc3, 0, 0},
+	{0x4713, 0x03, 0, 0}, {0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0},
+	{0x460c, 0x20, 0, 0}, {0x4837, 0x22, 0, 0}, {0x3824, 0x01, 0, 0},
+	{0x5001, 0xa3, 0, 0}, {0x3034, 0x1a, 0, 0}, {0x3035, 0x21, 0, 0},
+	{0x3036, 0x69, 0, 0}, {0x3037, 0x13, 0, 0},
+};
+
+static struct reg_value ov5640_setting_15fps_XGA_1024_768[] = {
+	{0x3c07, 0x08, 0, 0}, {0x3820, 0x41, 0, 0}, {0x3821, 0x07, 0, 0},
+	{0x3814, 0x31, 0, 0}, {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0},
+	{0x3801, 0x00, 0, 0}, {0x3802, 0x00, 0, 0}, {0x3803, 0x04, 0, 0},
+	{0x3804, 0x0a, 0, 0}, {0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0},
+	{0x3807, 0x9b, 0, 0}, {0x3808, 0x04, 0, 0}, {0x3809, 0x00, 0, 0},
+	{0x380a, 0x03, 0, 0}, {0x380b, 0x00, 0, 0}, {0x380c, 0x07, 0, 0},
+	{0x380d, 0x68, 0, 0}, {0x380e, 0x03, 0, 0}, {0x380f, 0xd8, 0, 0},
+	{0x3813, 0x06, 0, 0}, {0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0},
+	{0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x0b, 0, 0},
+	{0x3a03, 0x88, 0, 0}, {0x3a14, 0x0b, 0, 0}, {0x3a15, 0x88, 0, 0},
+	{0x4004, 0x02, 0, 0}, {0x3002, 0x1c, 0, 0}, {0x3006, 0xc3, 0, 0},
+	{0x4713, 0x03, 0, 0}, {0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0},
+	{0x460c, 0x20, 0, 0}, {0x4837, 0x22, 0, 0}, {0x3824, 0x01, 0, 0},
+	{0x5001, 0xa3, 0, 0}, {0x3034, 0x1a, 0, 0}, {0x3035, 0x21, 0, 0},
+	{0x3036, 0x46, 0, 0}, {0x3037, 0x13, 0, 0},
+};
+
+
+static struct reg_value ov5640_setting_15fps_1080P_1920_1080[] = {
+	{0x3c07, 0x07, 0, 0}, {0x3820, 0x40, 0, 0}, {0x3821, 0x06, 0, 0},
+	{0x3814, 0x11, 0, 0}, {0x3815, 0x11, 0, 0}, {0x3800, 0x00, 0, 0},
+	{0x3801, 0x00, 0, 0}, {0x3802, 0x00, 0, 0}, {0x3803, 0xee, 0, 0},
+	{0x3804, 0x0a, 0, 0}, {0x3805, 0x3f, 0, 0}, {0x3806, 0x05, 0, 0},
+	{0x3807, 0xc3, 0, 0}, {0x3808, 0x07, 0, 0}, {0x3809, 0x80, 0, 0},
+	{0x380a, 0x04, 0, 0}, {0x380b, 0x38, 0, 0}, {0x380c, 0x0b, 0, 0},
+	{0x380d, 0x1c, 0, 0}, {0x380e, 0x07, 0, 0}, {0x380f, 0xb0, 0, 0},
+	{0x3813, 0x04, 0, 0}, {0x3618, 0x04, 0, 0}, {0x3612, 0x2b, 0, 0},
+	{0x3709, 0x12, 0, 0}, {0x370c, 0x00, 0, 0}, {0x3a02, 0x07, 0, 0},
+	{0x3a03, 0xae, 0, 0}, {0x3a14, 0x07, 0, 0}, {0x3a15, 0xae, 0, 0},
+	{0x4004, 0x06, 0, 0}, {0x3002, 0x1c, 0, 0}, {0x3006, 0xc3, 0, 0},
+	{0x4713, 0x02, 0, 0}, {0x4407, 0x0c, 0, 0}, {0x460b, 0x37, 0, 0},
+	{0x460c, 0x20, 0, 0}, {0x4837, 0x2c, 0, 0}, {0x3824, 0x01, 0, 0},
+	{0x5001, 0x83, 0, 0}, {0x3034, 0x1a, 0, 0}, {0x3035, 0x21, 0, 0},
+	{0x3036, 0x69, 0, 0}, {0x3037, 0x13, 0, 0},
+};
+
+static struct reg_value ov5640_setting_15fps_QSXGA_2592_1944[] = {
+	{0x3c07, 0x07, 0, 0}, {0x3820, 0x40, 0, 0}, {0x3821, 0x06, 0, 0},
+	{0x3814, 0x11, 0, 0}, {0x3815, 0x11, 0, 0}, {0x3800, 0x00, 0, 0},
+	{0x3801, 0x00, 0, 0}, {0x3802, 0x00, 0, 0}, {0x3803, 0x00, 0, 0},
+	{0x3804, 0x0a, 0, 0}, {0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0},
+	{0x3807, 0x9f, 0, 0}, {0x3808, 0x0a, 0, 0}, {0x3809, 0x20, 0, 0},
+	{0x380a, 0x07, 0, 0}, {0x380b, 0x98, 0, 0}, {0x380c, 0x0b, 0, 0},
+	{0x380d, 0x1c, 0, 0}, {0x380e, 0x07, 0, 0}, {0x380f, 0xb0, 0, 0},
+	{0x3813, 0x04, 0, 0}, {0x3618, 0x04, 0, 0}, {0x3612, 0x2b, 0, 0},
+	{0x3709, 0x12, 0, 0}, {0x370c, 0x00, 0, 0}, {0x3a02, 0x07, 0, 0},
+	{0x3a03, 0xae, 0, 0}, {0x3a14, 0x07, 0, 0}, {0x3a15, 0xae, 0, 0},
+	{0x4004, 0x06, 0, 0}, {0x3002, 0x1c, 0, 0}, {0x3006, 0xc3, 0, 0},
+	{0x4713, 0x02, 0, 0}, {0x4407, 0x0c, 0, 0}, {0x460b, 0x37, 0, 0},
+	{0x460c, 0x20, 0, 0}, {0x4837, 0x2c, 0, 0}, {0x3824, 0x01, 0, 0},
+	{0x5001, 0x83, 0, 0}, {0x3034, 0x1a, 0, 0}, {0x3035, 0x21, 0, 0},
+	{0x3036, 0x69, 0, 0}, {0x3037, 0x13, 0, 0},
+};
+
+static struct ov5640_mode_info ov5640_mode_info_data[2][ov5640_mode_MAX + 1] = {
+	{
+		{ov5640_mode_VGA_640_480,      640,  480,
+		ov5640_setting_15fps_VGA_640_480,
+		ARRAY_SIZE(ov5640_setting_15fps_VGA_640_480)},
+		{ov5640_mode_QVGA_320_240,     320,  240,
+		ov5640_setting_15fps_QVGA_320_240,
+		ARRAY_SIZE(ov5640_setting_15fps_QVGA_320_240)},
+		{ov5640_mode_NTSC_720_480,     720,  480,
+		ov5640_setting_15fps_NTSC_720_480,
+		ARRAY_SIZE(ov5640_setting_15fps_NTSC_720_480)},
+		{ov5640_mode_PAL_720_576,      720,  576,
+		ov5640_setting_15fps_PAL_720_576,
+		ARRAY_SIZE(ov5640_setting_15fps_PAL_720_576)},
+		{ov5640_mode_720P_1280_720,   1280,  720,
+		ov5640_setting_15fps_720P_1280_720,
+		ARRAY_SIZE(ov5640_setting_15fps_720P_1280_720)},
+		{ov5640_mode_1080P_1920_1080, 1920, 1080,
+		ov5640_setting_15fps_1080P_1920_1080,
+		ARRAY_SIZE(ov5640_setting_15fps_1080P_1920_1080)},
+		{ov5640_mode_QSXGA_2592_1944, 2592, 1944,
+		ov5640_setting_15fps_QSXGA_2592_1944,
+		ARRAY_SIZE(ov5640_setting_15fps_QSXGA_2592_1944)},
+		{ov5640_mode_QCIF_176_144,     176,  144,
+		ov5640_setting_15fps_QCIF_176_144,
+		ARRAY_SIZE(ov5640_setting_15fps_QCIF_176_144)},
+		{ov5640_mode_XGA_1024_768,    1024,  768,
+		ov5640_setting_15fps_XGA_1024_768,
+		ARRAY_SIZE(ov5640_setting_15fps_XGA_1024_768)},
+	},
+	{
+		{ov5640_mode_VGA_640_480,      640,  480,
+		ov5640_setting_30fps_VGA_640_480,
+		ARRAY_SIZE(ov5640_setting_30fps_VGA_640_480)},
+		{ov5640_mode_QVGA_320_240,     320,  240,
+		ov5640_setting_30fps_QVGA_320_240,
+		ARRAY_SIZE(ov5640_setting_30fps_QVGA_320_240)},
+		{ov5640_mode_NTSC_720_480,     720,  480,
+		ov5640_setting_30fps_NTSC_720_480,
+		ARRAY_SIZE(ov5640_setting_30fps_NTSC_720_480)},
+		{ov5640_mode_PAL_720_576,      720,  576,
+		ov5640_setting_30fps_PAL_720_576,
+		ARRAY_SIZE(ov5640_setting_30fps_PAL_720_576)},
+		{ov5640_mode_720P_1280_720,   1280,  720,
+		ov5640_setting_30fps_720P_1280_720,
+		ARRAY_SIZE(ov5640_setting_30fps_720P_1280_720)},
+		{ov5640_mode_1080P_1920_1080, 0, 0, NULL, 0},
+		{ov5640_mode_QSXGA_2592_1944, 0, 0, NULL, 0},
+		{ov5640_mode_QCIF_176_144,     176,  144,
+		ov5640_setting_30fps_QCIF_176_144,
+		ARRAY_SIZE(ov5640_setting_30fps_QCIF_176_144)},
+		{ov5640_mode_XGA_1024_768,    1024,  768,
+		ov5640_setting_30fps_XGA_1024_768,
+		ARRAY_SIZE(ov5640_setting_30fps_XGA_1024_768)},
+	},
+};
+
+static struct regulator *io_regulator;
+static struct regulator *core_regulator;
+static struct regulator *analog_regulator;
+
+static int ov5640_probe(struct i2c_client *adapter,
+				const struct i2c_device_id *device_id);
+static int ov5640_remove(struct i2c_client *client);
+
+static s32 ov5640_read_reg(u16 reg, u8 *val);
+static s32 ov5640_write_reg(u16 reg, u8 val);
+
+#ifdef CONFIG_OF
+static const struct of_device_id ov5640_of_match[] = {
+	{ .compatible = "ovti,ov5640",
+	},
+	{ /* sentinel */ }
+};
+
+MODULE_DEVICE_TABLE(of, ov5640_of_match);
+#endif
+
+static const struct i2c_device_id ov5640_id[] = {
+	{"ov5640", 0},
+	{},
+};
+
+MODULE_DEVICE_TABLE(i2c, ov5640_id);
+
+static struct i2c_driver ov5640_i2c_driver = {
+	.driver = {
+		  .owner = THIS_MODULE,
+		  .name  = "ov5640",
+#ifdef CONFIG_OF
+		  .of_match_table = of_match_ptr(ov5640_of_match),
+#endif
+		  },
+	.probe  = ov5640_probe,
+	.remove = ov5640_remove,
+	.id_table = ov5640_id,
+};
+
+static const struct ov5640_datafmt ov5640_colour_fmts[] = {
+	{MEDIA_BUS_FMT_YUYV8_2X8, V4L2_COLORSPACE_JPEG},
+};
+
+static struct ov5640 *to_ov5640(const struct i2c_client *client)
+{
+	return container_of(i2c_get_clientdata(client), struct ov5640, subdev);
+}
+
+/* Find a data format by a pixel code in an array */
+static const struct ov5640_datafmt
+			*ov5640_find_datafmt(u32 code)
+{
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(ov5640_colour_fmts); i++)
+		if (ov5640_colour_fmts[i].code == code)
+			return ov5640_colour_fmts + i;
+
+	return NULL;
+}
+
+static inline void ov5640_power_down(int enable)
+{
+	gpio_set_value_cansleep(pwn_gpio, enable);
+
+	msleep(2);
+}
+
+static inline void ov5640_reset(void)
+{
+	/* camera reset */
+	gpio_set_value_cansleep(rst_gpio, 1);
+
+	/* camera power down */
+	gpio_set_value_cansleep(pwn_gpio, 1);
+	msleep(5);
+	gpio_set_value_cansleep(pwn_gpio, 0);
+	msleep(5);
+	gpio_set_value_cansleep(rst_gpio, 0);
+	msleep(1);
+	gpio_set_value_cansleep(rst_gpio, 1);
+	msleep(5);
+	gpio_set_value_cansleep(pwn_gpio, 1);
+}
+
+static int ov5640_regulator_enable(struct device *dev)
+{
+	int ret = 0;
+
+	io_regulator = devm_regulator_get(dev, "DOVDD");
+	if (!IS_ERR(io_regulator)) {
+		regulator_set_voltage(io_regulator,
+				      OV5640_VOLTAGE_DIGITAL_IO,
+				      OV5640_VOLTAGE_DIGITAL_IO);
+		ret = regulator_enable(io_regulator);
+		if (ret) {
+			dev_err(dev, "set io voltage failed\n");
+			return ret;
+		} else {
+			dev_dbg(dev, "set io voltage ok\n");
+		}
+	} else {
+		io_regulator = NULL;
+		dev_warn(dev, "cannot get io voltage\n");
+	}
+
+	core_regulator = devm_regulator_get(dev, "DVDD");
+	if (!IS_ERR(core_regulator)) {
+		regulator_set_voltage(core_regulator,
+				      OV5640_VOLTAGE_DIGITAL_CORE,
+				      OV5640_VOLTAGE_DIGITAL_CORE);
+		ret = regulator_enable(core_regulator);
+		if (ret) {
+			dev_err(dev, "set core voltage failed\n");
+			return ret;
+		} else {
+			dev_dbg(dev, "set core voltage ok\n");
+		}
+	} else {
+		core_regulator = NULL;
+		dev_warn(dev, "cannot get core voltage\n");
+	}
+
+	analog_regulator = devm_regulator_get(dev, "AVDD");
+	if (!IS_ERR(analog_regulator)) {
+		regulator_set_voltage(analog_regulator,
+				      OV5640_VOLTAGE_ANALOG,
+				      OV5640_VOLTAGE_ANALOG);
+		ret = regulator_enable(analog_regulator);
+		if (ret) {
+			dev_err(dev, "set analog voltage failed\n");
+			return ret;
+		} else {
+			dev_dbg(dev, "set analog voltage ok\n");
+		}
+	} else {
+		analog_regulator = NULL;
+		dev_warn(dev, "cannot get analog voltage\n");
+	}
+
+	return ret;
+}
+
+static s32 ov5640_write_reg(u16 reg, u8 val)
+{
+	u8 au8Buf[3] = {0};
+
+	au8Buf[0] = reg >> 8;
+	au8Buf[1] = reg & 0xff;
+	au8Buf[2] = val;
+
+	if (i2c_master_send(ov5640_data.i2c_client, au8Buf, 3) < 0) {
+		pr_err("%s:write reg error:reg=%x,val=%x\n",
+			__func__, reg, val);
+		return -1;
+	}
+
+	return 0;
+}
+
+static s32 ov5640_read_reg(u16 reg, u8 *val)
+{
+	u8 au8RegBuf[2] = {0};
+	u8 u8RdVal = 0;
+
+	au8RegBuf[0] = reg >> 8;
+	au8RegBuf[1] = reg & 0xff;
+
+	if (2 != i2c_master_send(ov5640_data.i2c_client, au8RegBuf, 2)) {
+		pr_err("%s:write reg error:reg=%x\n",
+				__func__, reg);
+		return -1;
+	}
+
+	if (1 != i2c_master_recv(ov5640_data.i2c_client, &u8RdVal, 1)) {
+		pr_err("%s:read reg error:reg=%x,val=%x\n",
+				__func__, reg, u8RdVal);
+		return -1;
+	}
+
+	*val = u8RdVal;
+
+	return u8RdVal;
+}
+
+#ifdef CONFIG_VIDEO_ADV_DEBUG
+static int ov5640_get_register(struct v4l2_subdev *sd,
+					struct v4l2_dbg_register *reg)
+{
+	struct i2c_client *client = v4l2_get_subdevdata(sd);
+	int ret;
+	u8 val;
+
+	if (reg->reg & ~0xffff)
+		return -EINVAL;
+
+	reg->size = 1;
+
+	ret = ov5640_read_reg(reg->reg, &val);
+	if (!ret)
+		reg->val = (__u64)val;
+
+	return ret;
+}
+
+static int ov5640_set_register(struct v4l2_subdev *sd,
+					const struct v4l2_dbg_register *reg)
+{
+	struct i2c_client *client = v4l2_get_subdevdata(sd);
+
+	if (reg->reg & ~0xffff || reg->val & ~0xff)
+		return -EINVAL;
+
+	return ov5640_write_reg(reg->reg, reg->val);
+}
+#endif
+
+static void ov5640_soft_reset(void)
+{
+	/* sysclk from pad */
+	ov5640_write_reg(0x3103, 0x11);
+
+	/* software reset */
+	ov5640_write_reg(0x3008, 0x82);
+
+	/* delay at least 5ms */
+	msleep(10);
+}
+
+/* set sensor driver capability
+ * 0x302c[7:6] - strength
+	00     - 1x
+	01     - 2x
+	10     - 3x
+	11     - 4x
+ */
+static int ov5640_driver_capability(int strength)
+{
+	u8 temp = 0;
+
+	if (strength > 4 || strength < 1) {
+		pr_err("The valid driver capability of ov5640 is 1x~4x\n");
+		return -EINVAL;
+	}
+
+	ov5640_read_reg(0x302c, &temp);
+
+	temp &= ~0xc0;	/* clear [7:6] */
+	temp |= ((strength - 1) << 6);	/* set [7:6] */
+
+	ov5640_write_reg(0x302c, temp);
+
+	return 0;
+}
+
+/* calculate sysclk */
+static int ov5640_get_sysclk(void)
+{
+	int xvclk = ov5640_data.mclk / 10000;
+	int sysclk;
+	int temp1, temp2;
+	int Multiplier, PreDiv, VCO, SysDiv, Pll_rdiv, Bit_div2x, sclk_rdiv;
+	int sclk_rdiv_map[] = {1, 2, 4, 8};
+	u8 regval = 0;
+
+	temp1 = ov5640_read_reg(0x3034, &regval);
+	temp2 = temp1 & 0x0f;
+	if (temp2 == 8 || temp2 == 10) {
+		Bit_div2x = temp2 / 2;
+	} else {
+		pr_err("ov5640: unsupported bit mode %d\n", temp2);
+		return -1;
+	}
+
+	temp1 = ov5640_read_reg(0x3035, &regval);
+	SysDiv = temp1 >> 4;
+	if (SysDiv == 0)
+		SysDiv = 16;
+
+	temp1 = ov5640_read_reg(0x3036, &regval);
+	Multiplier = temp1;
+	temp1 = ov5640_read_reg(0x3037, &regval);
+	PreDiv = temp1 & 0x0f;
+	Pll_rdiv = ((temp1 >> 4) & 0x01) + 1;
+
+	temp1 = ov5640_read_reg(0x3108, &regval);
+	temp2 = temp1 & 0x03;
+
+	sclk_rdiv = sclk_rdiv_map[temp2];
+	VCO = xvclk * Multiplier / PreDiv;
+	sysclk = VCO / SysDiv / Pll_rdiv * 2 / Bit_div2x / sclk_rdiv;
+
+	return sysclk;
+}
+
+/* read HTS from register settings */
+static int ov5640_get_HTS(void)
+{
+	int HTS;
+	u8 temp = 0;
+
+	HTS = ov5640_read_reg(0x380c, &temp);
+	HTS = (HTS<<8) + ov5640_read_reg(0x380d, &temp);
+	return HTS;
+}
+
+/* read VTS from register settings */
+static int ov5640_get_VTS(void)
+{
+	int VTS;
+	u8 temp = 0;
+
+	VTS = ov5640_read_reg(0x380e, &temp);
+	VTS = (VTS<<8) + ov5640_read_reg(0x380f, &temp);
+
+	return VTS;
+}
+
+/* write VTS to registers */
+static int ov5640_set_VTS(int VTS)
+{
+	int temp;
+
+	temp = VTS & 0xff;
+	ov5640_write_reg(0x380f, temp);
+
+	temp = VTS>>8;
+	ov5640_write_reg(0x380e, temp);
+	return 0;
+}
+
+/* read shutter, in number of line period */
+static int ov5640_get_shutter(void)
+{
+	int shutter;
+	u8 regval;
+
+	shutter = (ov5640_read_reg(0x03500, &regval) & 0x0f);
+
+	shutter = (shutter<<8) + ov5640_read_reg(0x3501, &regval);
+	shutter = (shutter<<4) + (ov5640_read_reg(0x3502, &regval)>>4);
+
+	return shutter;
+}
+
+/* write shutter, in number of line period */
+static int ov5640_set_shutter(int shutter)
+{
+	int temp;
+
+	shutter = shutter & 0xffff;
+	temp = shutter & 0x0f;
+	temp = temp<<4;
+	ov5640_write_reg(0x3502, temp);
+
+	temp = shutter & 0xfff;
+	temp = temp>>4;
+	ov5640_write_reg(0x3501, temp);
+
+	temp = shutter>>12;
+	ov5640_write_reg(0x3500, temp);
+
+	return 0;
+}
+
+/* read gain, 16 = 1x */
+static int ov5640_get_gain16(void)
+{
+	int gain16;
+	u8 regval;
+
+	gain16 = ov5640_read_reg(0x350a, &regval) & 0x03;
+	gain16 = (gain16<<8) + ov5640_read_reg(0x350b, &regval);
+
+	return gain16;
+}
+
+/* write gain, 16 = 1x */
+static int ov5640_set_gain16(int gain16)
+{
+	int temp;
+
+	gain16 = gain16 & 0x3ff;
+	temp = gain16 & 0xff;
+
+	ov5640_write_reg(0x350b, temp);
+	temp = gain16>>8;
+
+	ov5640_write_reg(0x350a, temp);
+	return 0;
+}
+
+/* get banding filter value */
+static int ov5640_get_light_freq(void)
+{
+	int temp, temp1, light_frequency;
+	u8 regval;
+
+	temp = ov5640_read_reg(0x3c01, &regval);
+	if (temp & 0x80) {
+		/* manual */
+		temp1 = ov5640_read_reg(0x3c00, &regval);
+		if (temp1 & 0x04) {
+			/* 50Hz */
+			light_frequency = 50;
+		} else {
+			/* 60Hz */
+			light_frequency = 60;
+		}
+	} else {
+		/* auto */
+		temp1 = ov5640_read_reg(0x3c0c, &regval);
+		if (temp1 & 0x01) {
+			/* 50Hz */
+			light_frequency = 50;
+		} else {
+			/* 60Hz */
+			light_frequency = 60;
+		}
+	}
+
+	return light_frequency;
+}
+
+static void ov5640_set_bandingfilter(void)
+{
+	int prev_VTS;
+	int band_step60, max_band60, band_step50, max_band50;
+
+	/* read preview PCLK */
+	prev_sysclk = ov5640_get_sysclk();
+
+	/* read preview HTS */
+	prev_HTS = ov5640_get_HTS();
+
+	/* read preview VTS */
+	prev_VTS = ov5640_get_VTS();
+
+	/* calculate banding filter */
+	/* 60Hz */
+	band_step60 = prev_sysclk * 100/prev_HTS * 100/120;
+	ov5640_write_reg(0x3a0a, (band_step60 >> 8));
+	ov5640_write_reg(0x3a0b, (band_step60 & 0xff));
+
+	max_band60 = (int)((prev_VTS-4)/band_step60);
+	ov5640_write_reg(0x3a0d, max_band60);
+
+	/* 50Hz */
+	band_step50 = prev_sysclk * 100/prev_HTS;
+	ov5640_write_reg(0x3a08, (band_step50 >> 8));
+	ov5640_write_reg(0x3a09, (band_step50 & 0xff));
+
+	max_band50 = (int)((prev_VTS-4)/band_step50);
+	ov5640_write_reg(0x3a0e, max_band50);
+}
+
+/* stable in high */
+static int ov5640_set_AE_target(int target)
+{
+	int fast_high, fast_low;
+
+	AE_low = target * 23 / 25; /* 0.92 */
+	AE_high = target * 27 / 25; /* 1.08 */
+	fast_high = AE_high << 1;
+
+	if (fast_high > 255)
+		fast_high = 255;
+	fast_low = AE_low >> 1;
+
+	ov5640_write_reg(0x3a0f, AE_high);
+	ov5640_write_reg(0x3a10, AE_low);
+	ov5640_write_reg(0x3a1b, AE_high);
+	ov5640_write_reg(0x3a1e, AE_low);
+	ov5640_write_reg(0x3a11, fast_high);
+	ov5640_write_reg(0x3a1f, fast_low);
+
+	return 0;
+}
+
+/* enable = 0 to turn off night mode
+   enable = 1 to turn on night mode */
+static int ov5640_set_night_mode(int enable)
+{
+	u8 mode;
+
+	ov5640_read_reg(0x3a00, &mode);
+
+	if (enable) {
+		/* night mode on */
+		mode |= 0x04;
+		ov5640_write_reg(0x3a00, mode);
+	} else {
+		/* night mode off */
+		mode &= 0xfb;
+		ov5640_write_reg(0x3a00, mode);
+	}
+
+	return 0;
+}
+
+/* enable = 0 to turn off AEC/AGC
+   enable = 1 to turn on AEC/AGC */
+static void ov5640_turn_on_AE_AG(int enable)
+{
+	u8 ae_ag_ctrl;
+
+	ov5640_read_reg(0x3503, &ae_ag_ctrl);
+	if (enable) {
+		/* turn on auto AE/AG */
+		ae_ag_ctrl = ae_ag_ctrl & ~(0x03);
+	} else {
+		/* turn off AE/AG */
+		ae_ag_ctrl = ae_ag_ctrl | 0x03;
+	}
+	ov5640_write_reg(0x3503, ae_ag_ctrl);
+}
+
+/* download ov5640 settings to sensor through i2c */
+static int ov5640_download_firmware(struct reg_value *pModeSetting, s32 ArySize)
+{
+	register u32 Delay_ms = 0;
+	register u16 RegAddr = 0;
+	register u8 Mask = 0;
+	register u8 Val = 0;
+	u8 RegVal = 0;
+	int i, retval = 0;
+
+	for (i = 0; i < ArySize; ++i, ++pModeSetting) {
+		Delay_ms = pModeSetting->u32Delay_ms;
+		RegAddr = pModeSetting->u16RegAddr;
+		Val = pModeSetting->u8Val;
+		Mask = pModeSetting->u8Mask;
+
+		if (Mask) {
+			retval = ov5640_read_reg(RegAddr, &RegVal);
+			if (retval < 0)
+				goto err;
+
+			RegVal &= ~(u8)Mask;
+			Val &= Mask;
+			Val |= RegVal;
+		}
+
+		retval = ov5640_write_reg(RegAddr, Val);
+		if (retval < 0)
+			goto err;
+
+		if (Delay_ms)
+			msleep(Delay_ms);
+	}
+err:
+	return retval;
+}
+
+static int ov5640_init_mode(void)
+{
+	struct reg_value *pModeSetting = NULL;
+	int ArySize = 0, retval = 0;
+
+	ov5640_soft_reset();
+
+	pModeSetting = ov5640_global_init_setting;
+	ArySize = ARRAY_SIZE(ov5640_global_init_setting);
+	retval = ov5640_download_firmware(pModeSetting, ArySize);
+	if (retval < 0)
+		goto err;
+
+	pModeSetting = ov5640_init_setting_30fps_VGA;
+	ArySize = ARRAY_SIZE(ov5640_init_setting_30fps_VGA);
+	retval = ov5640_download_firmware(pModeSetting, ArySize);
+	if (retval < 0)
+		goto err;
+
+	/* change driver capability to 2x according to validation board.
+	 * if the image is not stable, please increase the driver strength.
+	 */
+	ov5640_driver_capability(2);
+	ov5640_set_bandingfilter();
+	ov5640_set_AE_target(AE_Target);
+	ov5640_set_night_mode(night_mode);
+
+	/* skip 9 vysnc: start capture at 10th vsync */
+	msleep(300);
+
+	/* turn off night mode */
+	night_mode = 0;
+	ov5640_data.pix.width = 640;
+	ov5640_data.pix.height = 480;
+err:
+	return retval;
+}
+
+/* change to or back to subsampling mode set the mode directly
+ * image size below 1280 * 960 is subsampling mode */
+static int ov5640_change_mode_direct(enum ov5640_frame_rate frame_rate,
+			    enum ov5640_mode mode)
+{
+	struct reg_value *pModeSetting = NULL;
+	s32 ArySize = 0;
+	int retval = 0;
+
+	if (mode > ov5640_mode_MAX || mode < ov5640_mode_MIN) {
+		pr_err("Wrong ov5640 mode detected!\n");
+		return -1;
+	}
+
+	pModeSetting = ov5640_mode_info_data[frame_rate][mode].init_data_ptr;
+	ArySize =
+		ov5640_mode_info_data[frame_rate][mode].init_data_size;
+
+	ov5640_data.pix.width = ov5640_mode_info_data[frame_rate][mode].width;
+	ov5640_data.pix.height = ov5640_mode_info_data[frame_rate][mode].height;
+
+	if (ov5640_data.pix.width == 0 || ov5640_data.pix.height == 0 ||
+	    pModeSetting == NULL || ArySize == 0)
+		return -EINVAL;
+
+	/* set ov5640 to subsampling mode */
+	retval = ov5640_download_firmware(pModeSetting, ArySize);
+
+	/* turn on AE AG for subsampling mode, in case the firmware didn't */
+	ov5640_turn_on_AE_AG(1);
+
+	/* calculate banding filter */
+	ov5640_set_bandingfilter();
+
+	/* set AE target */
+	ov5640_set_AE_target(AE_Target);
+
+	/* update night mode setting */
+	ov5640_set_night_mode(night_mode);
+
+	/* skip 9 vysnc: start capture at 10th vsync */
+	if (mode == ov5640_mode_XGA_1024_768 && frame_rate == ov5640_30_fps) {
+		pr_warning("ov5640: actual frame rate of XGA is 22.5fps\n");
+		/* 1/22.5 * 9*/
+		msleep(400);
+		return retval;
+	}
+
+	if (frame_rate == ov5640_15_fps) {
+		/* 1/15 * 9*/
+		msleep(600);
+	} else if (frame_rate == ov5640_30_fps) {
+		/* 1/30 * 9*/
+		msleep(300);
+	}
+
+	return retval;
+}
+
+/* change to scaling mode go through exposure calucation
+ * image size above 1280 * 960 is scaling mode */
+static int ov5640_change_mode_exposure_calc(enum ov5640_frame_rate frame_rate,
+			    enum ov5640_mode mode)
+{
+	int prev_shutter, prev_gain16, average;
+	int cap_shutter, cap_gain16;
+	int cap_sysclk, cap_HTS, cap_VTS;
+	int light_freq, cap_bandfilt, cap_maxband;
+	long cap_gain16_shutter;
+	u8 temp;
+	struct reg_value *pModeSetting = NULL;
+	s32 ArySize = 0;
+	int retval = 0;
+
+	/* check if the input mode and frame rate is valid */
+	pModeSetting =
+		ov5640_mode_info_data[frame_rate][mode].init_data_ptr;
+	ArySize =
+		ov5640_mode_info_data[frame_rate][mode].init_data_size;
+
+	ov5640_data.pix.width =
+		ov5640_mode_info_data[frame_rate][mode].width;
+	ov5640_data.pix.height =
+		ov5640_mode_info_data[frame_rate][mode].height;
+
+	if (ov5640_data.pix.width == 0 || ov5640_data.pix.height == 0 ||
+		pModeSetting == NULL || ArySize == 0)
+		return -EINVAL;
+
+	/* read preview shutter */
+	prev_shutter = ov5640_get_shutter();
+
+	/* read preview gain */
+	prev_gain16 = ov5640_get_gain16();
+
+	/* get average */
+	average = ov5640_read_reg(0x56a1, &temp);
+
+	/* turn off night mode for capture */
+	ov5640_set_night_mode(0);
+
+	/* turn off overlay */
+	ov5640_write_reg(0x3022, 0x06);
+
+	/* Write capture setting */
+	retval = ov5640_download_firmware(pModeSetting, ArySize);
+	if (retval < 0)
+		goto err;
+
+	/* turn off AE AG when capture image. */
+	ov5640_turn_on_AE_AG(0);
+
+	/* read capture VTS */
+	cap_VTS = ov5640_get_VTS();
+	cap_HTS = ov5640_get_HTS();
+	cap_sysclk = ov5640_get_sysclk();
+
+	/* calculate capture banding filter */
+	light_freq = ov5640_get_light_freq();
+	if (light_freq == 60) {
+		/* 60Hz */
+		cap_bandfilt = cap_sysclk * 100 / cap_HTS * 100 / 120;
+	} else {
+		/* 50Hz */
+		cap_bandfilt = cap_sysclk * 100 / cap_HTS;
+	}
+	cap_maxband = (int)((cap_VTS - 4)/cap_bandfilt);
+	/* calculate capture shutter/gain16 */
+	if (average > AE_low && average < AE_high) {
+		/* in stable range */
+		cap_gain16_shutter =
+			prev_gain16 * prev_shutter * cap_sysclk/prev_sysclk *
+			prev_HTS/cap_HTS * AE_Target / average;
+	} else {
+		cap_gain16_shutter =
+			prev_gain16 * prev_shutter * cap_sysclk/prev_sysclk *
+			prev_HTS/cap_HTS;
+	}
+
+	/* gain to shutter */
+	if (cap_gain16_shutter < (cap_bandfilt * 16)) {
+		/* shutter < 1/100 */
+		cap_shutter = cap_gain16_shutter/16;
+		if (cap_shutter < 1)
+			cap_shutter = 1;
+		cap_gain16 = cap_gain16_shutter/cap_shutter;
+		if (cap_gain16 < 16)
+			cap_gain16 = 16;
+	} else {
+		if (cap_gain16_shutter > (cap_bandfilt*cap_maxband*16)) {
+			/* exposure reach max */
+			cap_shutter = cap_bandfilt*cap_maxband;
+			cap_gain16 = cap_gain16_shutter / cap_shutter;
+		} else {
+			/* 1/100 < cap_shutter =< max, cap_shutter = n/100 */
+			cap_shutter =
+				((int)(cap_gain16_shutter/16/cap_bandfilt))
+				* cap_bandfilt;
+			cap_gain16 = cap_gain16_shutter / cap_shutter;
+		}
+	}
+
+	/* write capture gain */
+	ov5640_set_gain16(cap_gain16);
+
+	/* write capture shutter */
+	if (cap_shutter > (cap_VTS - 4)) {
+		cap_VTS = cap_shutter + 4;
+		ov5640_set_VTS(cap_VTS);
+	}
+
+	ov5640_set_shutter(cap_shutter);
+
+	/* skip 2 vysnc: start capture at 3rd vsync
+	 * frame rate of QSXGA and 1080P is 7.5fps: 1/7.5 * 2
+	 */
+	pr_warning("ov5640: the actual frame rate of %s is 7.5fps\n",
+		mode == ov5640_mode_1080P_1920_1080 ? "1080P" : "QSXGA");
+	msleep(267);
+err:
+	return retval;
+}
+
+static int ov5640_change_mode(enum ov5640_frame_rate frame_rate,
+			    enum ov5640_mode mode)
+{
+	int retval = 0;
+
+	if (mode > ov5640_mode_MAX || mode < ov5640_mode_MIN) {
+		pr_err("Wrong ov5640 mode detected!\n");
+		return -1;
+	}
+
+	if (mode == ov5640_mode_1080P_1920_1080 ||
+			mode == ov5640_mode_QSXGA_2592_1944) {
+		/* change to scaling mode go through exposure calucation
+		 * image size above 1280 * 960 is scaling mode */
+		retval = ov5640_change_mode_exposure_calc(frame_rate, mode);
+	} else {
+		/* change back to subsampling modem download firmware directly
+		 * image size below 1280 * 960 is subsampling mode */
+		retval = ov5640_change_mode_direct(frame_rate, mode);
+	}
+
+	return retval;
+}
+
+/*!
+ * ov5640_s_power - V4L2 sensor interface handler for VIDIOC_S_POWER ioctl
+ * @s: pointer to standard V4L2 device structure
+ * @on: indicates power mode (on or off)
+ *
+ * Turns the power on or off, depending on the value of on and returns the
+ * appropriate error code.
+ */
+static int ov5640_s_power(struct v4l2_subdev *sd, int on)
+{
+	struct i2c_client *client = v4l2_get_subdevdata(sd);
+	struct ov5640 *sensor = to_ov5640(client);
+
+	if (on)
+		clk_enable(ov5640_data.sensor_clk);
+	else
+		clk_disable(ov5640_data.sensor_clk);
+
+	sensor->on = on;
+
+	return 0;
+}
+
+/*!
+ * ov5640_g_parm - V4L2 sensor interface handler for VIDIOC_G_PARM ioctl
+ * @s: pointer to standard V4L2 sub device structure
+ * @a: pointer to standard V4L2 VIDIOC_G_PARM ioctl structure
+ *
+ * Returns the sensor's video CAPTURE parameters.
+ */
+static int ov5640_g_parm(struct v4l2_subdev *sd, struct v4l2_streamparm *a)
+{
+	struct i2c_client *client = v4l2_get_subdevdata(sd);
+	struct ov5640 *sensor = to_ov5640(client);
+	struct v4l2_captureparm *cparm = &a->parm.capture;
+	int ret = 0;
+
+	switch (a->type) {
+	/* This is the only case currently handled. */
+	case V4L2_BUF_TYPE_VIDEO_CAPTURE:
+		memset(a, 0, sizeof(*a));
+		a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
+		cparm->capability = sensor->streamcap.capability;
+		cparm->timeperframe = sensor->streamcap.timeperframe;
+		cparm->capturemode = sensor->streamcap.capturemode;
+		ret = 0;
+		break;
+
+	/* These are all the possible cases. */
+	case V4L2_BUF_TYPE_VIDEO_OUTPUT:
+	case V4L2_BUF_TYPE_VIDEO_OVERLAY:
+	case V4L2_BUF_TYPE_VBI_CAPTURE:
+	case V4L2_BUF_TYPE_VBI_OUTPUT:
+	case V4L2_BUF_TYPE_SLICED_VBI_CAPTURE:
+	case V4L2_BUF_TYPE_SLICED_VBI_OUTPUT:
+		ret = -EINVAL;
+		break;
+
+	default:
+		pr_debug("   type is unknown - %d\n", a->type);
+		ret = -EINVAL;
+		break;
+	}
+
+	return ret;
+}
+
+/*!
+ * ov5460_s_parm - V4L2 sensor interface handler for VIDIOC_S_PARM ioctl
+ * @s: pointer to standard V4L2 sub device structure
+ * @a: pointer to standard V4L2 VIDIOC_S_PARM ioctl structure
+ *
+ * Configures the sensor to use the input parameters, if possible.  If
+ * not possible, reverts to the old parameters and returns the
+ * appropriate error code.
+ */
+static int ov5640_s_parm(struct v4l2_subdev *sd, struct v4l2_streamparm *a)
+{
+	struct i2c_client *client = v4l2_get_subdevdata(sd);
+	struct ov5640 *sensor = to_ov5640(client);
+	struct v4l2_fract *timeperframe = &a->parm.capture.timeperframe;
+	u32 tgt_fps;	/* target frames per secound */
+	enum ov5640_frame_rate frame_rate;
+	int ret = 0;
+
+	switch (a->type) {
+	/* This is the only case currently handled. */
+	case V4L2_BUF_TYPE_VIDEO_CAPTURE:
+		/* Check that the new frame rate is allowed. */
+		if ((timeperframe->numerator == 0) ||
+		    (timeperframe->denominator == 0)) {
+			timeperframe->denominator = DEFAULT_FPS;
+			timeperframe->numerator = 1;
+		}
+
+		tgt_fps = timeperframe->denominator /
+			  timeperframe->numerator;
+
+		if (tgt_fps > MAX_FPS) {
+			timeperframe->denominator = MAX_FPS;
+			timeperframe->numerator = 1;
+		} else if (tgt_fps < MIN_FPS) {
+			timeperframe->denominator = MIN_FPS;
+			timeperframe->numerator = 1;
+		}
+
+		/* Actual frame rate we use */
+		tgt_fps = timeperframe->denominator /
+			  timeperframe->numerator;
+
+		if (tgt_fps == 15)
+			frame_rate = ov5640_15_fps;
+		else if (tgt_fps == 30)
+			frame_rate = ov5640_30_fps;
+		else {
+			pr_err(" The camera frame rate is not supported!\n");
+			goto error;
+		}
+
+		ret = ov5640_change_mode(frame_rate,
+				a->parm.capture.capturemode);
+		if (ret < 0)
+			goto error;
+
+		sensor->streamcap.timeperframe = *timeperframe;
+		sensor->streamcap.capturemode = a->parm.capture.capturemode;
+
+		break;
+
+	/* These are all the possible cases. */
+	case V4L2_BUF_TYPE_VIDEO_OUTPUT:
+	case V4L2_BUF_TYPE_VIDEO_OVERLAY:
+	case V4L2_BUF_TYPE_VBI_CAPTURE:
+	case V4L2_BUF_TYPE_VBI_OUTPUT:
+	case V4L2_BUF_TYPE_SLICED_VBI_CAPTURE:
+	case V4L2_BUF_TYPE_SLICED_VBI_OUTPUT:
+		pr_debug("   type is not " \
+			"V4L2_BUF_TYPE_VIDEO_CAPTURE but %d\n",
+			a->type);
+		ret = -EINVAL;
+		break;
+
+	default:
+		pr_debug("   type is unknown - %d\n", a->type);
+		ret = -EINVAL;
+		break;
+	}
+
+error:
+	return ret;
+}
+
+static int ov5640_set_fmt(struct v4l2_subdev *sd,
+			  struct v4l2_subdev_pad_config *cfg,
+			  struct v4l2_subdev_format *format)
+{
+	struct v4l2_mbus_framefmt *mf = &format->format;
+	const struct ov5640_datafmt *fmt = ov5640_find_datafmt(mf->code);
+	struct i2c_client *client = v4l2_get_subdevdata(sd);
+	struct ov5640 *sensor = to_ov5640(client);
+
+	if (format->pad)
+		return -EINVAL;
+
+	if (!fmt) {
+		mf->code	= ov5640_colour_fmts[0].code;
+		mf->colorspace	= ov5640_colour_fmts[0].colorspace;
+	}
+
+	mf->field	= V4L2_FIELD_NONE;
+
+	if (format->which == V4L2_SUBDEV_FORMAT_TRY)
+		return 0;
+
+	sensor->fmt = fmt;
+
+	return 0;
+}
+
+static int ov5640_get_fmt(struct v4l2_subdev *sd,
+			  struct v4l2_subdev_pad_config *cfg,
+			  struct v4l2_subdev_format *format)
+{
+	struct v4l2_mbus_framefmt *mf = &format->format;
+	struct i2c_client *client = v4l2_get_subdevdata(sd);
+	struct ov5640 *sensor = to_ov5640(client);
+	const struct ov5640_datafmt *fmt = sensor->fmt;
+
+	if (format->pad)
+		return -EINVAL;
+
+	mf->code	= fmt->code;
+	mf->colorspace	= fmt->colorspace;
+	mf->field	= V4L2_FIELD_NONE;
+
+	return 0;
+}
+
+static int ov5640_enum_code(struct v4l2_subdev *sd,
+			    struct v4l2_subdev_pad_config *cfg,
+			    struct v4l2_subdev_mbus_code_enum *code)
+{
+	if (code->pad || code->index >= ARRAY_SIZE(ov5640_colour_fmts))
+		return -EINVAL;
+
+	code->code = ov5640_colour_fmts[code->index].code;
+	return 0;
+}
+
+/*!
+ * ov5640_enum_framesizes - V4L2 sensor interface handler for
+ *			   VIDIOC_ENUM_FRAMESIZES ioctl
+ * @s: pointer to standard V4L2 device structure
+ * @fsize: standard V4L2 VIDIOC_ENUM_FRAMESIZES ioctl structure
+ *
+ * Return 0 if successful, otherwise -EINVAL.
+ */
+static int ov5640_enum_framesizes(struct v4l2_subdev *sd,
+			       struct v4l2_subdev_pad_config *cfg,
+			       struct v4l2_subdev_frame_size_enum *fse)
+{
+	if (fse->index > ov5640_mode_MAX)
+		return -EINVAL;
+
+	fse->max_width =
+			max(ov5640_mode_info_data[0][fse->index].width,
+			    ov5640_mode_info_data[1][fse->index].width);
+	fse->min_width = fse->max_width;
+	fse->max_height =
+			max(ov5640_mode_info_data[0][fse->index].height,
+			    ov5640_mode_info_data[1][fse->index].height);
+	fse->min_height = fse->max_height;
+	return 0;
+}
+
+/*!
+ * ov5640_enum_frameintervals - V4L2 sensor interface handler for
+ *			       VIDIOC_ENUM_FRAMEINTERVALS ioctl
+ * @s: pointer to standard V4L2 device structure
+ * @fival: standard V4L2 VIDIOC_ENUM_FRAMEINTERVALS ioctl structure
+ *
+ * Return 0 if successful, otherwise -EINVAL.
+ */
+static int ov5640_enum_frameintervals(struct v4l2_subdev *sd,
+		struct v4l2_subdev_pad_config *cfg,
+		struct v4l2_subdev_frame_interval_enum *fie)
+{
+	int i, j, count;
+
+	if (fie->index < 0 || fie->index > ov5640_mode_MAX)
+		return -EINVAL;
+
+	if (fie->width == 0 || fie->height == 0 ||
+	    fie->code == 0) {
+		pr_warning("Please assign pixel format, width and height.\n");
+		return -EINVAL;
+	}
+
+	fie->interval.numerator = 1;
+
+	count = 0;
+	for (i = 0; i < ARRAY_SIZE(ov5640_mode_info_data); i++) {
+		for (j = 0; j < (ov5640_mode_MAX + 1); j++) {
+			if (fie->width == ov5640_mode_info_data[i][j].width
+			 && fie->height == ov5640_mode_info_data[i][j].height
+			 && ov5640_mode_info_data[i][j].init_data_ptr != NULL) {
+				count++;
+			}
+			if (fie->index == (count - 1)) {
+				fie->interval.denominator =
+						ov5640_framerates[i];
+				return 0;
+			}
+		}
+	}
+
+	return -EINVAL;
+}
+
+static int ov5640_set_clk_rate(void)
+{
+	u32 tgt_xclk;	/* target xclk */
+	int ret;
+
+	/* mclk */
+	tgt_xclk = ov5640_data.mclk;
+	tgt_xclk = min(tgt_xclk, (u32)OV5640_XCLK_MAX);
+	tgt_xclk = max(tgt_xclk, (u32)OV5640_XCLK_MIN);
+	ov5640_data.mclk = tgt_xclk;
+
+	pr_debug("   Setting mclk to %d MHz\n", tgt_xclk / 1000000);
+	ret = clk_set_rate(ov5640_data.sensor_clk, ov5640_data.mclk);
+	if (ret < 0)
+		pr_debug("set rate filed, rate=%d\n", ov5640_data.mclk);
+	return ret;
+}
+
+/*!
+ * dev_init - V4L2 sensor init
+ * @s: pointer to standard V4L2 device structure
+ *
+ */
+static int init_device(void)
+{
+	u32 tgt_xclk;	/* target xclk */
+	u32 tgt_fps;	/* target frames per secound */
+	enum ov5640_frame_rate frame_rate;
+	int ret;
+
+	ov5640_data.on = true;
+
+	/* mclk */
+	tgt_xclk = ov5640_data.mclk;
+
+	/* Default camera frame rate is set in probe */
+	tgt_fps = ov5640_data.streamcap.timeperframe.denominator /
+		  ov5640_data.streamcap.timeperframe.numerator;
+
+	if (tgt_fps == 15)
+		frame_rate = ov5640_15_fps;
+	else if (tgt_fps == 30)
+		frame_rate = ov5640_30_fps;
+	else
+		return -EINVAL; /* Only support 15fps or 30fps now. */
+
+	ret = ov5640_init_mode();
+
+	return ret;
+}
+
+static struct v4l2_subdev_video_ops ov5640_subdev_video_ops = {
+	.g_parm = ov5640_g_parm,
+	.s_parm = ov5640_s_parm,
+};
+
+static const struct v4l2_subdev_pad_ops ov5640_subdev_pad_ops = {
+	.enum_frame_size       = ov5640_enum_framesizes,
+	.enum_frame_interval   = ov5640_enum_frameintervals,
+	.enum_mbus_code        = ov5640_enum_code,
+	.set_fmt               = ov5640_set_fmt,
+	.get_fmt               = ov5640_get_fmt,
+};
+
+static struct v4l2_subdev_core_ops ov5640_subdev_core_ops = {
+	.s_power	= ov5640_s_power,
+#ifdef CONFIG_VIDEO_ADV_DEBUG
+	.g_register	= ov5640_get_register,
+	.s_register	= ov5640_set_register,
+#endif
+};
+
+static struct v4l2_subdev_ops ov5640_subdev_ops = {
+	.core	= &ov5640_subdev_core_ops,
+	.video	= &ov5640_subdev_video_ops,
+	.pad	= &ov5640_subdev_pad_ops,
+};
+
+/*!
+ * ov5640 I2C probe function
+ *
+ * @param adapter            struct i2c_adapter *
+ * @return  Error code indicating success or failure
+ */
+static int ov5640_probe(struct i2c_client *client,
+			const struct i2c_device_id *id)
+{
+	struct pinctrl *pinctrl;
+	struct device *dev = &client->dev;
+	int retval;
+	u8 chip_id_high, chip_id_low;
+
+	/* ov5640 pinctrl */
+	pinctrl = devm_pinctrl_get_select_default(dev);
+	if (IS_ERR(pinctrl)) {
+		dev_err(dev, "setup pinctrl failed\n");
+		return PTR_ERR(pinctrl);
+	}
+
+	/* request power down pin */
+	pwn_gpio = of_get_named_gpio(dev->of_node, "pwn-gpios", 0);
+	if (!gpio_is_valid(pwn_gpio)) {
+		dev_err(dev, "no sensor pwdn pin available\n");
+		return -ENODEV;
+	}
+	retval = devm_gpio_request_one(dev, pwn_gpio, GPIOF_OUT_INIT_HIGH,
+					"ov5640_pwdn");
+	if (retval < 0)
+		return retval;
+
+	/* request reset pin */
+	rst_gpio = of_get_named_gpio(dev->of_node, "rst-gpios", 0);
+	if (!gpio_is_valid(rst_gpio)) {
+		dev_err(dev, "no sensor reset pin available\n");
+		return -EINVAL;
+	}
+	retval = devm_gpio_request_one(dev, rst_gpio, GPIOF_OUT_INIT_HIGH,
+					"ov5640_reset");
+	if (retval < 0)
+		return retval;
+
+	/* Set initial values for the sensor struct. */
+	memset(&ov5640_data, 0, sizeof(ov5640_data));
+	ov5640_data.sensor_clk = devm_clk_get(dev, "csi_mclk");
+	if (IS_ERR(ov5640_data.sensor_clk)) {
+		dev_err(dev, "get mclk failed\n");
+		return PTR_ERR(ov5640_data.sensor_clk);
+	}
+
+	retval = of_property_read_u32(dev->of_node, "mclk",
+					&ov5640_data.mclk);
+	if (retval) {
+		dev_err(dev, "mclk frequency is invalid\n");
+		return retval;
+	}
+
+	retval = of_property_read_u32(dev->of_node, "mclk_source",
+					(u32 *) &(ov5640_data.mclk_source));
+	if (retval) {
+		dev_err(dev, "mclk_source invalid\n");
+		return retval;
+	}
+
+	retval = of_property_read_u32(dev->of_node, "csi_id",
+					&(ov5640_data.csi));
+	if (retval) {
+		dev_err(dev, "csi_id invalid\n");
+		return retval;
+	}
+
+	/* Set mclk rate before clk on */
+	ov5640_set_clk_rate();
+
+	clk_prepare_enable(ov5640_data.sensor_clk);
+
+	ov5640_data.io_init = ov5640_reset;
+	ov5640_data.i2c_client = client;
+	ov5640_data.pix.pixelformat = V4L2_PIX_FMT_YUYV;
+	ov5640_data.pix.width = 640;
+	ov5640_data.pix.height = 480;
+	ov5640_data.streamcap.capability = V4L2_MODE_HIGHQUALITY |
+					   V4L2_CAP_TIMEPERFRAME;
+	ov5640_data.streamcap.capturemode = 0;
+	ov5640_data.streamcap.timeperframe.denominator = DEFAULT_FPS;
+	ov5640_data.streamcap.timeperframe.numerator = 1;
+
+	ov5640_regulator_enable(&client->dev);
+
+	ov5640_reset();
+
+	ov5640_power_down(0);
+
+	retval = ov5640_read_reg(OV5640_CHIP_ID_HIGH_BYTE, &chip_id_high);
+	if (retval < 0 || chip_id_high != 0x56) {
+		clk_disable_unprepare(ov5640_data.sensor_clk);
+		pr_warning("camera ov5640 is not found\n");
+		return -ENODEV;
+	}
+	retval = ov5640_read_reg(OV5640_CHIP_ID_LOW_BYTE, &chip_id_low);
+	if (retval < 0 || chip_id_low != 0x40) {
+		clk_disable_unprepare(ov5640_data.sensor_clk);
+		pr_warning("camera ov5640 is not found\n");
+		return -ENODEV;
+	}
+
+	retval = init_device();
+	if (retval < 0) {
+		clk_disable_unprepare(ov5640_data.sensor_clk);
+		pr_warning("camera ov5640 init failed\n");
+		ov5640_power_down(1);
+		return retval;
+	}
+
+	clk_disable(ov5640_data.sensor_clk);
+
+	v4l2_i2c_subdev_init(&ov5640_data.subdev, client, &ov5640_subdev_ops);
+
+	retval = v4l2_async_register_subdev(&ov5640_data.subdev);
+	if (retval < 0)
+		dev_err(&client->dev,
+					"%s--Async register failed, ret=%d\n", __func__, retval);
+
+	pr_info("camera ov5640, is found\n");
+	return retval;
+}
+
+/*!
+ * ov5640 I2C detach function
+ *
+ * @param client            struct i2c_client *
+ * @return  Error code indicating success or failure
+ */
+static int ov5640_remove(struct i2c_client *client)
+{
+	struct v4l2_subdev *sd = i2c_get_clientdata(client);
+
+	v4l2_async_unregister_subdev(sd);
+
+	clk_unprepare(ov5640_data.sensor_clk);
+
+	ov5640_power_down(1);
+
+	if (analog_regulator)
+		regulator_disable(analog_regulator);
+
+	if (core_regulator)
+		regulator_disable(core_regulator);
+
+	if (io_regulator)
+		regulator_disable(io_regulator);
+
+	return 0;
+}
+
+module_i2c_driver(ov5640_i2c_driver);
+
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_DESCRIPTION("OV5640 Camera Driver");
+MODULE_LICENSE("GPL");
+MODULE_VERSION("1.0");
+MODULE_ALIAS("CSI");
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/p9813/Makefile b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/p9813/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..c8e7b9698e591401c9047229cb24bb2097aa3260
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/p9813/Makefile
@@ -0,0 +1,41 @@
+#
+# Peter Yang <turmary@126.com>
+# Copyright (c) 2019 Seeed Studio
+#
+# MIT License
+#
+
+_tgt     := p9813
+
+_uname_r := $(shell uname -r)
+_BUILD   := /lib/modules/$(_uname_r)/build
+_PWD     := $(shell pwd)
+_DEPMOD  ?= depmod -a
+
+# If KERNELRELEASE is defined, we've been invoked from the
+# kernel build system and can use its language
+ifneq ($(KERNELRELEASE),)
+
+obj-m += ${_tgt}.o
+
+else
+_class  := drivers/misc
+
+DEST  := /lib/modules/$(_uname_r)/kernel
+
+all:
+	make -C ${_BUILD} M=$(_PWD) modules
+
+clean:
+	make -C ${_BUILD} M=$(_PWD) clean
+
+install:
+	cp ${_tgt}.ko ${DEST}/${_class}/
+	$(_DEPMOD)
+
+uninstall:
+	rm -f ${DEST}/${_class}/${_tgt}.ko
+	$(_DEPMOD)
+
+.PHONY: all clean install uninstall
+endif
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/p9813/README.md b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/p9813/README.md
new file mode 100644
index 0000000000000000000000000000000000000000..a7a5d956d28da0786437b49766f8e71a05b6bb23
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/p9813/README.md
@@ -0,0 +1,42 @@
+GROVE Chainable RGB LED (P9813)
+===============================
+
+  After driver and configuration prepared well,
+  the user could access ```/dev/p981x<N>```,
+  to operate the chained RGB LEDs.
+
+***
+
+Usage
+-----
+
+***commands***
+
+```
+N chain-length
+D led-index red green blue
+  led-index be in [0, chain-length)
+  red/green/blue be in [0, 255(0xFF)]
+```
+
+***example:***
+
+  ```bash
+  # check the device name
+  ls -l /dev/p981x*
+  # where <N> is a number start from 0,1...
+
+  # specify the chain length (how many LEDs chained)
+  # here is 2 leds chained.
+  $ echo "N 2" > /dev/p981x0
+    
+  # set LED 0 to RED
+  $ echo "D 0 0xFF 0 0" > /dev/p981x0
+
+  # set LED 1 to GREEN
+  $ echo "D 1 0 0xFF 0" > /dev/p981x0
+  ```
+
+  If you need customize the GPIO-Port..., refer to device tree document
+  [p9813.txt](../../doc/devicetree/bindings/p9813.txt)
+
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/p9813/p9813.c b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/p9813/p9813.c
new file mode 100644
index 0000000000000000000000000000000000000000..c68386e5a2b2fcc38950105a4cfce1fa98863e7a
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/p9813/p9813.c
@@ -0,0 +1,364 @@
+/*
+ * Chainable RGB LED (P9813) Driver
+ *
+ * Copyright (C) 2019 Seeed Studio
+ * Peter Yang <turmary@126.com>
+ *
+ * Released under the GPLv2
+ *
+ */
+
+#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/fs.h>
+#include <linux/device.h>
+#include <linux/errno.h>
+#include <linux/mutex.h>
+#include <linux/slab.h>
+#include <linux/delay.h>
+#include <linux/sched.h>
+#include <linux/poll.h>
+#include <linux/platform_device.h>
+#include <linux/miscdevice.h>
+#include <linux/of.h>
+#include <linux/of_gpio.h>
+#include <linux/of_device.h>
+
+#define DEV_NAME "p981x"
+
+/* FCLK <= 15MHz */
+#define P981X_PULSE_DLY		50    /* ns */
+
+#define P981X_LINE_LEN		64   /* chars */
+
+/*
+ * This driver creates a character device (/dev/p981xN) which exposes the
+ * Chainable RGB LED (P9813)
+ */
+
+struct p981x_dev {
+	/* misc device descriptor */
+	struct miscdevice miscdev;
+
+	/* pins */
+	int     pin_clk;
+	int     pin_data;
+
+	/* locks */
+	struct mutex mutex;
+
+	/* LEDs count */
+	int	count;
+	/* LEDs data buffer */
+	u32*    buffer;
+
+	/* command line index */
+	int     index;
+	/* command line data */
+	char    line[P981X_LINE_LEN + 1];
+};
+#define to_p981x_dev(dev)  container_of((dev), struct p981x_dev, miscdev)
+static int dev_index = 0;
+
+
+static int p981x_send_byte(struct p981x_dev *ppd, u8 b) {
+	int i;
+
+	for (i = 0; i < 8; i++) {
+		/* DATA LEVEL */
+		gpio_set_value(ppd->pin_data, !!(b & 0x80UL));
+
+		/* ONE PULSE CLOCK */
+		gpio_set_value(ppd->pin_clk, 0);
+		ndelay(P981X_PULSE_DLY);
+		gpio_set_value(ppd->pin_clk, 1);
+		ndelay(P981X_PULSE_DLY);
+		b <<= 1;
+	}
+	return 0;
+}
+
+static int p981x_send_u32(struct p981x_dev *ppd, u32 word) {
+	int i;
+
+	for (i = 3; i >= 0; i--) {
+		p981x_send_byte(ppd, ((u8*)&word)[i]);
+	}
+	return 0;
+}
+
+static int p981x_send_frame(struct p981x_dev *ppd) {
+	int i;
+
+	/* Send data frame prefix (32x "0") */
+	p981x_send_u32(ppd, 0x0UL);
+
+	/* Send color data for each one of the leds */
+	for (i = 0; i < ppd->count && ppd->buffer; i++) {
+		p981x_send_u32(ppd, ppd->buffer[i]);
+	}
+
+	/* Terminate data frame (32x "0") */
+	p981x_send_u32(ppd, 0x0UL);
+	return 0;
+}
+
+static u32 p981x_color(u8 red, u8 green, u8 blue) {
+	u32 color;
+
+	color  = 0xC0000000UL;
+	color |= (~blue  & 0xC0UL) << 22;
+	color |= (~green & 0xC0UL) << 20;
+	color |= (~red   & 0xC0UL) << 18;
+	color |= blue  << 16;
+	color |= green << 8;
+	color |= red   << 0;
+	return color;
+}
+
+static int p981x_cmds(struct p981x_dev *ppd) {
+	char* endp;
+	char* cp;
+	int i, rc;
+	#define COLOR_CNT	4
+	int color[COLOR_CNT];
+
+	switch (ppd->line[0]) {
+	case 'N':
+		rc = sscanf(&ppd->line[1], "%d", &ppd->count);
+		if (ppd->buffer) {
+			kfree(ppd->buffer);
+			ppd->buffer = NULL;
+		}
+		if (ppd->count > 0) {
+			ppd->buffer = kmalloc(sizeof(u32) * ppd->count, GFP_KERNEL);
+		}
+		break;
+
+	case 'D':
+		endp = &ppd->line[1];
+		for (i = 0; i < COLOR_CNT && (cp = strsep(&endp, " \t")) != NULL; ) {
+			long long ll;
+
+			/* format: led-index red green blue */
+			if (! *cp) {
+				continue;
+			}
+			rc = kstrtoll(cp, 0, &ll);
+			if (rc < 0) {
+				break;
+			}
+			color[i++] = ll;
+
+			pr_debug("color%d = 0x%02X (%d)\n", i - 1, (u8)ll, (u8)ll);
+		}
+		if (i >= COLOR_CNT) {
+			rc = color[0];
+			if (0 <= rc && rc < ppd->count && ppd->buffer) {
+				ppd->buffer[rc] =
+					p981x_color(color[1], color[2], color[3]);
+			}
+		}
+		break;
+	}
+
+	ppd->index = 0;
+	return 0;
+}
+
+static ssize_t p981x_write(struct file *f, const char __user *buf,
+			     size_t len, loff_t *f_pos)
+{
+	struct p981x_dev *ppd = to_p981x_dev(f->private_data);
+	size_t i;
+	char ch;
+
+	for (i = 0; i < len; i++) {
+		if (copy_from_user(&ch, buf + i, 1)) {
+			return -EFAULT;
+		}
+
+		switch (ch) {
+		case '\r':
+		case '\n':
+		case '\0':
+			ch = '\0';
+			break;
+		default:
+			break;
+		}
+		if ( ! ppd->index && (ch == ' ' || ch == '\t')) {
+			/* skip prefix space */
+			continue;
+		}
+		ppd->line[ppd->index++] = ch;
+		if (ppd->index >= P981X_LINE_LEN || !ch) {
+			p981x_cmds(ppd);
+		}
+	}
+
+	/* Update display */
+	p981x_send_frame(ppd);
+
+	return len;
+}
+
+static int p981x_open(struct inode *inode, struct file *f)
+{
+	struct p981x_dev *ppd = to_p981x_dev(f->private_data);
+	/* struct device* dev = ppd->miscdev.this_device; */
+
+	if (!mutex_trylock(&ppd->mutex)) {
+		pr_debug("Device Busy\n");
+		return -EBUSY;
+	}
+	return 0;
+}
+
+static int p981x_release(struct inode *inode, struct file *f)
+{
+	struct p981x_dev *ppd = to_p981x_dev(f->private_data);
+
+	mutex_unlock(&ppd->mutex);
+	return 0;
+}
+
+static const struct file_operations p981x_fops = {
+	.owner		= THIS_MODULE,
+	.write		= p981x_write,
+	.open		= p981x_open,
+	.release	= p981x_release
+};
+
+static const struct miscdevice misc_def = {
+	.minor		= MISC_DYNAMIC_MINOR,
+	.name		= DEV_NAME,
+	.mode		= S_IWUGO,
+	.fops		= &p981x_fops
+};
+
+/* Initialise GPIO */
+static int p981x_gpio_init(int gpio)
+{
+	/* check that GPIO is valid */
+	if ( !gpio_is_valid(gpio) ){
+		pr_err("GPIO %d is not valid\n", gpio );
+		return -EINVAL;
+	}
+
+	/* request the GPIO pin */
+	if ( gpio_request(gpio, DEV_NAME) != 0 ) {
+		pr_err("Unable to request GPIO %d\n", gpio );
+		return -EINVAL;
+	}
+
+	/* make GPIO an output */
+	if ( gpio_direction_output(gpio, 0) != 0 ) {
+		pr_err("Failed to make GPIO %d as output\n", gpio );
+		return -EINVAL;
+	}
+	return 0;
+}
+
+static int p981x_probe(struct platform_device *pdev)
+{
+	struct device_node *np = pdev->dev.of_node;
+	struct device *dev;
+	struct p981x_dev *ppd;
+	int rc;
+
+	/* Allocate memory for our private structure */
+	ppd = kzalloc(sizeof(*ppd), GFP_KERNEL);
+	if (!ppd) {
+		return -ENOMEM;
+	}
+
+	if (np) {
+		/*
+		 * first  gpio: clock pin
+		 * second gpio: data  pin
+		 */
+		ppd->pin_clk  = of_get_gpio(np, 0);
+		ppd->pin_data = of_get_gpio(np, 1);
+	} else {
+		ppd->pin_clk = ppd->pin_data = -1;
+	}
+
+	if (ppd->pin_clk < 0 || ppd->pin_data < 0) {
+		pr_err("Failed to get clock & data gpio in device tree\n");
+		rc = -EINVAL;
+		goto free_p981x;
+	}
+	if (p981x_gpio_init(ppd->pin_clk) || p981x_gpio_init(ppd->pin_data)) {
+		rc = -EINVAL;
+		goto free_p981x;
+	}
+
+	mutex_init(&ppd->mutex);
+
+	ppd->miscdev = misc_def;
+	ppd->miscdev.name = kasprintf(GFP_KERNEL, "%s%d",
+				misc_def.name, dev_index++);
+	rc = misc_register(&ppd->miscdev);
+	if (rc) {
+		pr_err("Failed to register as misc device %s\n", misc_def.name);
+		goto free_p981x;
+	}
+
+	/* platform device drvdata */
+	dev_set_drvdata(&pdev->dev, ppd);
+
+	/* misc device drvdata */
+	dev = ppd->miscdev.this_device;
+	dev_set_drvdata(dev, ppd);
+
+	pr_info("device %s registered, using clock:%d data:%d\n",
+		ppd->miscdev.name, ppd->pin_clk, ppd->pin_data);
+	return 0;
+
+free_p981x:
+	kfree(ppd);
+	return rc;
+}
+
+static int p981x_remove(struct platform_device *pdev)
+{
+	struct p981x_dev *ppd = platform_get_drvdata(pdev);
+
+	gpio_free(ppd->pin_clk);
+	gpio_free(ppd->pin_data);
+
+	if (ppd->buffer) {
+		kfree(ppd->buffer);
+		ppd->buffer = NULL;
+	}
+
+	misc_deregister(&ppd->miscdev);
+	kfree(ppd->miscdev.name);
+	kfree(ppd);
+	return 0;
+}
+
+static const struct of_device_id p981x_match[] = {
+	{ .compatible = "dms," DEV_NAME },
+	{ },
+};
+
+static struct platform_driver p981x_driver = {
+	.driver	= {
+		.name		= DEV_NAME,
+		.of_match_table	= p981x_match,
+	},
+	.probe	= p981x_probe,
+	.remove	= p981x_remove,
+};
+
+module_platform_driver(p981x_driver);
+
+MODULE_DEVICE_TABLE(of, p981x_match);
+MODULE_LICENSE("GPL v2");
+MODULE_DESCRIPTION("Chainable RGB LED (P9813) Driver");
+MODULE_AUTHOR("Peter Yang <turmary@126.com>");
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/seeed-voicecard/LICENSE b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/seeed-voicecard/LICENSE
new file mode 100644
index 0000000000000000000000000000000000000000..9cecc1d4669ee8af2ca727a5d8cde10cd8b2d7cc
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/seeed-voicecard/LICENSE
@@ -0,0 +1,674 @@
+                    GNU GENERAL PUBLIC LICENSE
+                       Version 3, 29 June 2007
+
+ Copyright (C) 2007 Free Software Foundation, Inc. <http://fsf.org/>
+ Everyone is permitted to copy and distribute verbatim copies
+ of this license document, but changing it is not allowed.
+
+                            Preamble
+
+  The GNU General Public License is a free, copyleft license for
+software and other kinds of works.
+
+  The licenses for most software and other practical works are designed
+to take away your freedom to share and change the works.  By contrast,
+the GNU General Public License is intended to guarantee your freedom to
+share and change all versions of a program--to make sure it remains free
+software for all its users.  We, the Free Software Foundation, use the
+GNU General Public License for most of our software; it applies also to
+any other work released this way by its authors.  You can apply it to
+your programs, too.
+
+  When we speak of free software, we are referring to freedom, not
+price.  Our General Public Licenses are designed to make sure that you
+have the freedom to distribute copies of free software (and charge for
+them if you wish), that you receive source code or can get it if you
+want it, that you can change the software or use pieces of it in new
+free programs, and that you know you can do these things.
+
+  To protect your rights, we need to prevent others from denying you
+these rights or asking you to surrender the rights.  Therefore, you have
+certain responsibilities if you distribute copies of the software, or if
+you modify it: responsibilities to respect the freedom of others.
+
+  For example, if you distribute copies of such a program, whether
+gratis or for a fee, you must pass on to the recipients the same
+freedoms that you received.  You must make sure that they, too, receive
+or can get the source code.  And you must show them these terms so they
+know their rights.
+
+  Developers that use the GNU GPL protect your rights with two steps:
+(1) assert copyright on the software, and (2) offer you this License
+giving you legal permission to copy, distribute and/or modify it.
+
+  For the developers' and authors' protection, the GPL clearly explains
+that there is no warranty for this free software.  For both users' and
+authors' sake, the GPL requires that modified versions be marked as
+changed, so that their problems will not be attributed erroneously to
+authors of previous versions.
+
+  Some devices are designed to deny users access to install or run
+modified versions of the software inside them, although the manufacturer
+can do so.  This is fundamentally incompatible with the aim of
+protecting users' freedom to change the software.  The systematic
+pattern of such abuse occurs in the area of products for individuals to
+use, which is precisely where it is most unacceptable.  Therefore, we
+have designed this version of the GPL to prohibit the practice for those
+products.  If such problems arise substantially in other domains, we
+stand ready to extend this provision to those domains in future versions
+of the GPL, as needed to protect the freedom of users.
+
+  Finally, every program is threatened constantly by software patents.
+States should not allow patents to restrict development and use of
+software on general-purpose computers, but in those that do, we wish to
+avoid the special danger that patents applied to a free program could
+make it effectively proprietary.  To prevent this, the GPL assures that
+patents cannot be used to render the program non-free.
+
+  The precise terms and conditions for copying, distribution and
+modification follow.
+
+                       TERMS AND CONDITIONS
+
+  0. Definitions.
+
+  "This License" refers to version 3 of the GNU General Public License.
+
+  "Copyright" also means copyright-like laws that apply to other kinds of
+works, such as semiconductor masks.
+
+  "The Program" refers to any copyrightable work licensed under this
+License.  Each licensee is addressed as "you".  "Licensees" and
+"recipients" may be individuals or organizations.
+
+  To "modify" a work means to copy from or adapt all or part of the work
+in a fashion requiring copyright permission, other than the making of an
+exact copy.  The resulting work is called a "modified version" of the
+earlier work or a work "based on" the earlier work.
+
+  A "covered work" means either the unmodified Program or a work based
+on the Program.
+
+  To "propagate" a work means to do anything with it that, without
+permission, would make you directly or secondarily liable for
+infringement under applicable copyright law, except executing it on a
+computer or modifying a private copy.  Propagation includes copying,
+distribution (with or without modification), making available to the
+public, and in some countries other activities as well.
+
+  To "convey" a work means any kind of propagation that enables other
+parties to make or receive copies.  Mere interaction with a user through
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+
+  An interactive user interface displays "Appropriate Legal Notices"
+to the extent that it includes a convenient and prominently visible
+feature that (1) displays an appropriate copyright notice, and (2)
+tells the user that there is no warranty for the work (except to the
+extent that warranties are provided), that licensees may convey the
+work under this License, and how to view a copy of this License.  If
+the interface presents a list of user commands or options, such as a
+menu, a prominent item in the list meets this criterion.
+
+  1. Source Code.
+
+  The "source code" for a work means the preferred form of the work
+for making modifications to it.  "Object code" means any non-source
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diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/seeed-voicecard/Makefile b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/seeed-voicecard/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..b9de7f42b4e5496ee332827bfbc54ed9e6211243
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/seeed-voicecard/Makefile
@@ -0,0 +1,52 @@
+#
+# Peter Yang <turmary@126.com>
+# Copyright (c) 2019 Seeed Studio
+#
+# MIT License
+#
+
+uname_r=$(shell uname -r)
+
+# If KERNELRELEASE is defined, we've been invoked from the
+# kernel build system and can use its language
+ifneq ($(KERNELRELEASE),)
+# $(warning KERNELVERSION=$(KERNELVERSION))
+
+snd-soc-wm8960-objs := wm8960.o
+snd-soc-ac108-objs := ac108.o ac101.o
+snd-soc-seeed-voicecard-objs := seeed-voicecard.o
+
+
+obj-m += snd-soc-wm8960.o
+obj-m += snd-soc-ac108.o
+obj-m += snd-soc-seeed-voicecard.o
+
+ifdef DEBUG
+ifneq ($(DEBUG),0)
+	ccflags-y += -DDEBUG -DAC101_DEBG
+endif
+endif
+
+
+
+else
+
+DEST := /lib/modules/$(uname_r)/kernel
+
+all:
+	make -C /lib/modules/$(uname_r)/build M=$(PWD) modules
+
+clean:
+	make -C /lib/modules/$(uname_r)/build M=$(PWD) clean
+
+install:
+	sudo cp snd-soc-ac108.ko ${DEST}/sound/soc/codecs/
+	sudo cp snd-soc-wm8960.ko ${DEST}/sound/soc/codecs/
+	sudo cp snd-soc-seeed-voicecard.ko ${DEST}/sound/soc/bcm/
+	sudo depmod -a
+
+
+.PHONY: all clean install
+
+endif
+
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/seeed-voicecard/README.md b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/seeed-voicecard/README.md
new file mode 100644
index 0000000000000000000000000000000000000000..159a33cbf88fe4e3dfaecdb8d020791a4c84b39a
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/seeed-voicecard/README.md
@@ -0,0 +1,267 @@
+# seeed-voicecard
+
+[![Join the chat at https://gitter.im/seeed-voicecard/Lobby](https://badges.gitter.im/seeed-voicecard/Lobby.svg)](https://gitter.im/seeed-voicecard/Lobby?utm_source=badge&utm_medium=badge&utm_campaign=pr-badge&utm_content=badge)
+
+The drivers of [ReSpeaker Mic Hat](https://www.seeedstudio.com/ReSpeaker-2-Mics-Pi-HAT-p-2874.html),[ReSpeaker 4 Mic Array](https://www.seeedstudio.com/ReSpeaker-4-Mic-Array-for-Raspberry-Pi-p-2941.html),[6-Mics Circular Array Kit](), and [4-Mics Linear Array Kit]() for Raspberry Pi.
+
+### Install seeed-voicecard
+Get the seeed voice card source code. and install all linux kernel drivers
+```bash
+git clone https://github.com/respeaker/seeed-voicecard
+cd seeed-voicecard
+sudo ./install.sh 
+sudo reboot
+```
+
+## ReSpeaker Mic Hat
+
+[![](https://github.com/SeeedDocument/MIC_HATv1.0_for_raspberrypi/blob/master/img/mic_hatv1.0.png?raw=true)](https://www.seeedstudio.com/ReSpeaker-2-Mics-Pi-HAT-p-2874.html)
+
+While the upstream wm8960 codec is not currently supported by current Pi kernel builds, upstream wm8960 has some bugs, we had fixed it. we must it build manually.
+
+Check that the sound card name matches the source code seeed-voicecard.
+
+```bash
+#for ReSpeaker 2-mic
+pi@raspberrypi:~/seeed-voicecard $ aplay -l
+**** List of PLAYBACK Hardware Devices ****
+card 0: ALSA [bcm2835 ALSA], device 0: bcm2835 ALSA [bcm2835 ALSA]
+  Subdevices: 8/8
+  Subdevice #0: subdevice #0
+  Subdevice #1: subdevice #1
+  Subdevice #2: subdevice #2
+  Subdevice #3: subdevice #3
+  Subdevice #4: subdevice #4
+  Subdevice #5: subdevice #5
+  Subdevice #6: subdevice #6
+  Subdevice #7: subdevice #7
+card 0: ALSA [bcm2835 ALSA], device 1: bcm2835 ALSA [bcm2835 IEC958/HDMI]
+  Subdevices: 1/1
+  Subdevice #0: subdevice #0
+card 1: seeed2micvoicec [seeed-2mic-voicecard], device 0: bcm2835-i2s-wm8960-hifi wm8960-hifi-0 []
+  Subdevices: 1/1
+  Subdevice #0: subdevice #0
+pi@raspberrypi:~/seeed-voicecard $ arecord -l
+**** List of CAPTURE Hardware Devices ****
+card 1: seeed2micvoicec [seeed-2mic-voicecard], device 0: bcm2835-i2s-wm8960-hifi wm8960-hifi-0 []
+  Subdevices: 1/1
+  Subdevice #0: subdevice #0
+pi@raspberrypi:~/seeed-voicecard $ 
+```
+If you want to change the alsa settings, You can use `sudo alsactl --file=/etc/voicecard/wm8960_asound.state  store` to save it.
+
+
+
+#### Next step
+Go to https://github.com/respeaker/mic_hat to build voice enabled projects with Google Assistant SDK or Alexa Voice Service.
+
+## ReSpeaker 4 Mic Array
+
+[![](https://github.com/SeeedDocument/ReSpeaker-4-Mic-Array-for-Raspberry-Pi/blob/master/img/features.png?raw=true)](https://www.seeedstudio.com/ReSpeaker-4-Mic-Array-for-Raspberry-Pi-p-2941.html)
+
+The 4 Mic Array uses ac108 which includes 4 ADCs, we also write ac108 rapberry pi linux kernel driver.
+
+Check that the sound card name matches the source code seeed-voicecard.
+
+```bash
+#for ReSpeaker 4 Mic Array
+pi@raspberrypi:~ $ arecord -L
+null
+    Discard all samples (playback) or generate zero samples (capture)
+playback
+capture
+dmixed
+array
+ac108
+default:CARD=seeed4micvoicec
+    seeed-4mic-voicecard, 
+    Default Audio Device
+sysdefault:CARD=seeed4micvoicec
+    seeed-4mic-voicecard, 
+    Default Audio Device
+dmix:CARD=seeed4micvoicec,DEV=0
+    seeed-4mic-voicecard, 
+    Direct sample mixing device
+dsnoop:CARD=seeed4micvoicec,DEV=0
+    seeed-4mic-voicecard, 
+    Direct sample snooping device
+hw:CARD=seeed4micvoicec,DEV=0
+    seeed-4mic-voicecard, 
+    Direct hardware device without any conversions
+plughw:CARD=seeed4micvoicec,DEV=0
+    seeed-4mic-voicecard, 
+    Hardware device with all software conversions
+pi@raspberrypi:~ $ 
+```
+If you want to change the alsa settings, You can use `sudo alsactl --file=/etc/voicecard/ac108_asound.state  store` to save it.
+
+## 6-Mics Circular Array Kit
+
+[![](https://user-images.githubusercontent.com/3901856/37268348-6adef768-2600-11e8-8861-588b1c3ea142.png)]()
+
+The 6 Mics Circular Array Kit uses ac108 x 2 / ac101 x 1 / micphones x 6, includes 8 ADCs and 2 DACs.
+
+The driver is implemented with 8 input channels & 8 output channels.
+>**The first 6 input channel are MIC recording data,  
+the rest 2 input channel are echo channel of playback  
+The first 2 output channel are playing data, the rest 6 output channel are dummy**
+
+
+Check that the sound card name matches the source code seeed-voicecard.
+```bash
+#for 6 Mic Circular Array
+pi@raspberrypi:~ $ arecord -L
+null
+    Discard all samples (playback) or generate zero samples (capture)
+default
+playback
+dmixed
+ac108
+multiapps
+ac101
+sysdefault:CARD=seeed8micvoicec
+    seeed-8mic-voicecard,
+    Default Audio Device
+dmix:CARD=seeed8micvoicec,DEV=0
+    seeed-8mic-voicecard,
+    Direct sample mixing device
+dsnoop:CARD=seeed8micvoicec,DEV=0
+    seeed-8mic-voicecard,
+    Direct sample snooping device
+hw:CARD=seeed8micvoicec,DEV=0
+    seeed-8mic-voicecard,
+    Direct hardware device without any conversions
+plughw:CARD=seeed8micvoicec,DEV=0
+    seeed-8mic-voicecard,
+    Hardware device with all software conversions
+    
+pi@raspberrypi:~ $ aplay -L
+null
+    Discard all samples (playback) or generate zero samples (capture)
+default
+playback
+dmixed
+ac108
+multiapps
+ac101
+sysdefault:CARD=ALSA
+    bcm2835 ALSA, bcm2835 ALSA
+    Default Audio Device
+dmix:CARD=ALSA,DEV=0
+    bcm2835 ALSA, bcm2835 ALSA
+    Direct sample mixing device
+dmix:CARD=ALSA,DEV=1
+    bcm2835 ALSA, bcm2835 IEC958/HDMI
+    Direct sample mixing device
+dsnoop:CARD=ALSA,DEV=0
+    bcm2835 ALSA, bcm2835 ALSA
+    Direct sample snooping device
+dsnoop:CARD=ALSA,DEV=1
+    bcm2835 ALSA, bcm2835 IEC958/HDMI
+    Direct sample snooping device
+hw:CARD=ALSA,DEV=0
+    bcm2835 ALSA, bcm2835 ALSA
+    Direct hardware device without any conversions
+hw:CARD=ALSA,DEV=1
+    bcm2835 ALSA, bcm2835 IEC958/HDMI
+    Direct hardware device without any conversions
+plughw:CARD=ALSA,DEV=0
+    bcm2835 ALSA, bcm2835 ALSA
+    Hardware device with all software conversions
+plughw:CARD=ALSA,DEV=1
+    bcm2835 ALSA, bcm2835 IEC958/HDMI
+    Hardware device with all software conversions
+sysdefault:CARD=seeed8micvoicec
+    seeed-8mic-voicecard,
+    Default Audio Device
+dmix:CARD=seeed8micvoicec,DEV=0
+    seeed-8mic-voicecard,
+    Direct sample mixing device
+dsnoop:CARD=seeed8micvoicec,DEV=0
+    seeed-8mic-voicecard,
+    Direct sample snooping device
+hw:CARD=seeed8micvoicec,DEV=0
+    seeed-8mic-voicecard,
+    Direct hardware device without any conversions
+plughw:CARD=seeed8micvoicec,DEV=0
+    seeed-8mic-voicecard,
+    Hardware device with all software conversions
+```
+
+## 4-Mics Linear Array Kit
+
+[![](https://user-images.githubusercontent.com/3901856/37194106-a0ccebce-23a7-11e8-88c5-ec611e44ec49.png)]()
+
+In contrast to 6-Mics Circular Array Kit for Raspberry Pi,
+the difference is only first 4 input channels are valid capture data.
+
+### Usage:
+```bash
+#for ReSpeaker 2-mic
+#It will capture sound an playback on hw:1
+arecord -f cd -Dhw:1 | aplay -Dhw:1
+```
+
+```bash
+#for ReSpeaker 4-mic
+#It will capture sound on AC108 and save as a.wav
+arecord -Dac108 -f S32_LE -r 16000 -c 4 a.wav
+```
+
+```bash
+#for 6-Mics Circular Array Kit and 4-Mics Linear Array Kit
+#It will capture sound on AC108 and save as a.wav
+arecord -Dac108 -f S32_LE -r 16000 -c 8 a.wav
+#Take care of that the captured mic audio is on the first 6 channels
+
+#It will play a mono channel sound file mono_to_play.wav
+#The file to play must be mono channel or else the speaker output nothing.
+aplay -D plughw:1,0 mono_to_play.wav
+
+#Doing capture && playback the same time
+arecord -D hw:1,0 -f S32_LE -r 16000 -c 8 to_be_record.wav &
+#mono_to_play.wav is a mono channel wave file to play
+aplay -D plughw:1,0 -r 16000 mono_to_play.wav
+```
+**Note: Limit for developer using 6-Mics Circular Array Kit(or 4-Mics Linear Array Kit) doing capture & playback the same time:  
+1. capture must be start first, or else the capture channels will possibly be disorder.  
+2. playback output channels must fill with 8 same channels data or 4 same stereo channels data, or else the speaker or headphone will output nothing possibly.**
+
+### Coherence
+
+Estimate the magnitude squared coherence using Welch’s method.
+![4-mics-linear-array-kit coherence](https://user-images.githubusercontent.com/3901856/37277486-beb1dd96-261f-11e8-898b-84405bfc7cea.png)  
+Note: 'CO 1-2' means the coherence between channel 1 and channel 2.
+
+```bash
+# How to get the coherence of the captured audio(a.wav for example).
+sudo apt install python-numpy python-scipy python-matplotlib
+python tools/coherence.py a.wav
+
+# Requirement of the input audio file:
+- format: WAV(Microsoft) signed 16-bit PCM
+- channels: >=2
+```
+
+### uninstall seeed-voicecard
+If you want to upgrade the driver , you need uninstall the driver first.
+
+```
+pi@raspberrypi:~/seeed-voicecard $ sudo ./uninstall.sh 
+...
+------------------------------------------------------
+Please reboot your raspberry pi to apply all settings
+Thank you!
+------------------------------------------------------
+```
+
+
+
+
+Enjoy !
+
+### FAQ
+
+When you encounter any installation and use problems when you start your ReSpeaker Pi hat, please use the following image for testing. We have installed seeed-voicecard based on the latest PI image, which can be used by burning it directly on SD. If this still cannot solve your problem, you can ask in the issue. We will try our best to solve your problem.
+
+<p style="text-align:center"><a href="https://v2.fangcloud.com/share/7395fd138a1cab496fd4792fe5" target="_blank"><img src="https://github.com/SeeedDocument/Respeaker_V2/raw/master/img/efangyun.png" width="200" height="40"  border=0 /></a></p>
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/seeed-voicecard/ac101.c b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/seeed-voicecard/ac101.c
new file mode 100644
index 0000000000000000000000000000000000000000..a4bcd62f668b305f14256a1c49ebb24abf63159e
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/seeed-voicecard/ac101.c
@@ -0,0 +1,1693 @@
+/*
+ * ac101.c
+ *
+ * (C) Copyright 2017-2018
+ * Seeed Technology Co., Ltd. <www.seeedstudio.com>
+ *
+ * PeterYang <linsheng.yang@seeed.cc>
+ *
+ * (C) Copyright 2014-2017
+ * Reuuimlla Technology Co., Ltd. <www.reuuimllatech.com>
+ *
+ * huangxin <huangxin@Reuuimllatech.com>
+ * liushaohua <liushaohua@allwinnertech.com>
+ *
+ * X-Powers AC101 codec driver
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ */
+
+/* #undef AC101_DEBG
+ * use 'make DEBUG=1' to enable debugging
+ */
+#include <linux/module.h>
+#include <sound/pcm.h>
+#include <sound/pcm_params.h>
+#include <sound/soc.h>
+#include <sound/soc-dapm.h>
+#include <sound/tlv.h>
+#include <linux/i2c.h>
+#include <linux/irq.h>
+#include <linux/workqueue.h>
+#include <linux/clk.h>
+#include <linux/gpio/consumer.h>
+#include <linux/regmap.h>
+#include <linux/input.h>
+#include <linux/delay.h>
+#include "ac101_regs.h"
+#include "ac10x.h"
+
+/*
+ * *** To sync channels ***
+ *
+ * 1. disable clock in codec   hw_params()
+ * 2. clear   fifo  in bcm2835 hw_params()
+ * 3. clear   fifo  in bcm2385 prepare()
+ * 4. enable  RX    in bcm2835 trigger()
+ * 5. enable  clock in machine trigger()
+ */
+
+/*Default initialize configuration*/
+static bool speaker_double_used = 1;
+static int double_speaker_val	= 0x1B;
+static int single_speaker_val	= 0x19;
+static int headset_val		= 0x3B;
+static int mainmic_val		= 0x4;
+static int headsetmic_val	= 0x4;
+static bool dmic_used		= 0;
+static int adc_digital_val	= 0xb0b0;
+static bool drc_used		= false;
+
+#define AC101_RATES  (SNDRV_PCM_RATE_8000_96000 &		\
+		~(SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_64000 | \
+		SNDRV_PCM_RATE_88200))
+#define AC101_FORMATS (/*SNDRV_PCM_FMTBIT_S16_LE | \
+			SNDRV_PCM_FMTBIT_S24_LE |*/	\
+			SNDRV_PCM_FMTBIT_S32_LE	| \
+			0)
+
+static struct ac10x_priv* static_ac10x;
+
+
+int ac101_read(struct snd_soc_codec *codec, unsigned reg) {
+	struct ac10x_priv *ac10x = snd_soc_codec_get_drvdata(codec);
+	int r, v = 0;
+
+	if ((r = regmap_read(ac10x->regmap101, reg, &v)) < 0) {
+		dev_err(codec->dev, "read reg %02X fail\n",
+			 reg);
+		return r;
+	}
+	return v;
+}
+
+int ac101_write(struct snd_soc_codec *codec, unsigned reg, unsigned val) {
+	struct ac10x_priv *ac10x = snd_soc_codec_get_drvdata(codec);
+	int v;
+
+	v = regmap_write(ac10x->regmap101, reg, val);
+	return v;
+}
+
+int ac101_update_bits(struct snd_soc_codec *codec, unsigned reg,
+			unsigned mask, unsigned value
+) {
+	struct ac10x_priv *ac10x = snd_soc_codec_get_drvdata(codec);
+	int v;
+
+	v = regmap_update_bits(ac10x->regmap101, reg, mask, value);
+	return v;
+}
+
+
+
+#ifdef CONFIG_AC101_SWITCH_DETECT
+/******************************************************************************/
+/********************************switch****************************************/
+/******************************************************************************/
+#define KEY_HEADSETHOOK         226		/* key define */
+#define HEADSET_FILTER_CNT	(10)
+
+/*
+ * switch_hw_config:config the 53 codec register
+ */
+static void switch_hw_config(struct snd_soc_codec *codec)
+{
+	int r;
+
+	AC101_DBG();
+
+	/*HMIC/MMIC BIAS voltage level select:2.5v*/
+	ac101_update_bits(codec, OMIXER_BST1_CTRL, (0xf<<BIASVOLTAGE), (0xf<<BIASVOLTAGE));
+	/*debounce when Key down or keyup*/
+	ac101_update_bits(codec, HMIC_CTRL1, (0xf<<HMIC_M), (0x0<<HMIC_M));
+	/*debounce when earphone plugin or pullout*/
+	ac101_update_bits(codec, HMIC_CTRL1, (0xf<<HMIC_N), (0x0<<HMIC_N));
+	/*Down Sample Setting Select: Downby 4,32Hz*/
+	ac101_update_bits(codec, HMIC_CTRL2, (0x3<<HMIC_SAMPLE_SELECT), (0x02<<HMIC_SAMPLE_SELECT));
+	/*Hmic_th2 for detecting Keydown or Keyup.*/
+	ac101_update_bits(codec, HMIC_CTRL2, (0x1f<<HMIC_TH2), (0x8<<HMIC_TH2));
+	/*Hmic_th1[4:0],detecting eraphone plugin or pullout*/
+	ac101_update_bits(codec, HMIC_CTRL2, (0x1f<<HMIC_TH1), (0x1<<HMIC_TH1));
+	/*Headset microphone BIAS working mode: when HBIASEN = 1 */
+	ac101_update_bits(codec, ADC_APC_CTRL, (0x1<<HBIASMOD), (0x1<<HBIASMOD));
+	/*Headset microphone BIAS Enable*/
+	ac101_update_bits(codec, ADC_APC_CTRL, (0x1<<HBIASEN), (0x1<<HBIASEN));
+	/*Headset microphone BIAS Current sensor & ADC Enable*/
+	ac101_update_bits(codec, ADC_APC_CTRL, (0x1<<HBIASADCEN), (0x1<<HBIASADCEN));
+	/*Earphone Plugin/out Irq Enable*/
+	ac101_update_bits(codec, HMIC_CTRL1, (0x1<<HMIC_PULLOUT_IRQ), (0x1<<HMIC_PULLOUT_IRQ));
+	ac101_update_bits(codec, HMIC_CTRL1, (0x1<<HMIC_PLUGIN_IRQ), (0x1<<HMIC_PLUGIN_IRQ));
+
+	/*Hmic KeyUp/key down Irq Enable*/
+	ac101_update_bits(codec, HMIC_CTRL1, (0x1<<HMIC_KEYDOWN_IRQ), (0x1<<HMIC_KEYDOWN_IRQ));
+	ac101_update_bits(codec, HMIC_CTRL1, (0x1<<HMIC_KEYUP_IRQ), (0x1<<HMIC_KEYUP_IRQ));
+
+	/*headphone calibration clock frequency select*/
+	ac101_update_bits(codec, SPKOUT_CTRL, (0x7<<HPCALICKS), (0x7<<HPCALICKS));
+
+	/*clear hmic interrupt */
+	r = HMIC_PEND_ALL;
+	ac101_write(codec, HMIC_STS, r);
+
+	return;
+}
+
+/*
+ * switch_status_update: update the switch state.
+ */
+static void switch_status_update(struct ac10x_priv *ac10x)
+{
+	AC101_DBG("ac10x->state:%d\n", ac10x->state);
+
+        input_report_switch(ac10x->inpdev, SW_HEADPHONE_INSERT, ac10x->state);
+        input_sync(ac10x->inpdev);
+        return;
+}
+
+/*
+ * work_cb_clear_irq: clear audiocodec pending and Record the interrupt.
+ */
+static void work_cb_clear_irq(struct work_struct *work)
+{
+	int reg_val = 0;
+	struct ac10x_priv *ac10x = container_of(work, struct ac10x_priv, work_clear_irq);
+	struct snd_soc_codec *codec = ac10x->codec;
+
+	ac10x->irq_cntr++;
+
+	reg_val = ac101_read(codec, HMIC_STS);
+	if (BIT(HMIC_PULLOUT_PEND) & reg_val) {
+		ac10x->pullout_cntr++;
+		AC101_DBG("ac10x->pullout_cntr: %d\n", ac10x->pullout_cntr);
+	}
+
+	reg_val |= HMIC_PEND_ALL;
+	ac101_write(codec, HMIC_STS, reg_val);
+
+	reg_val = ac101_read(codec, HMIC_STS);
+	if ((reg_val & HMIC_PEND_ALL) != 0){
+		reg_val |= HMIC_PEND_ALL;
+		ac101_write(codec, HMIC_STS, reg_val);
+	}
+
+	if (cancel_work_sync(&ac10x->work_switch) != 0) {
+		ac10x->irq_cntr--;
+	}
+
+	if (0 == schedule_work(&ac10x->work_switch)) {
+		ac10x->irq_cntr--;
+		AC101_DBG("[work_cb_clear_irq] add work struct failed!\n");
+	}
+}
+
+enum {
+	HBIAS_LEVEL_1 = 0x02,
+	HBIAS_LEVEL_2 = 0x0B,
+	HBIAS_LEVEL_3 = 0x13,
+	HBIAS_LEVEL_4 = 0x17,
+	HBIAS_LEVEL_5 = 0x19,
+};
+
+static int __ac101_get_hmic_data(struct snd_soc_codec *codec) {
+	#ifdef AC101_DEBG
+	static long counter;
+	#endif
+	int r, d;
+
+	d = GET_HMIC_DATA(ac101_read(codec, HMIC_STS));
+
+	r = 0x1 << HMIC_DATA_PEND;
+	ac101_write(codec, HMIC_STS, r);
+
+	/* prevent i2c accessing too frequently */
+	usleep_range(1500, 3000);
+
+	AC101_DBG("HMIC_DATA(%3ld): %02X\n", counter++, d);
+	return d;
+}
+
+/*
+ * work_cb_earphone_switch: judge the status of the headphone
+ */
+static void work_cb_earphone_switch(struct work_struct *work)
+{
+	struct ac10x_priv *ac10x = container_of(work, struct ac10x_priv, work_switch);
+	struct snd_soc_codec *codec = ac10x->codec;
+
+	static int hook_flag1 = 0, hook_flag2 = 0;
+	static int KEY_VOLUME_FLAG = 0;
+
+	unsigned filter_buf = 0;
+	int filt_index = 0;
+	int t = 0;
+
+	ac10x->irq_cntr--;
+
+	/* read HMIC_DATA */
+	t = __ac101_get_hmic_data(codec);
+
+	if ((t >= HBIAS_LEVEL_2) && (ac10x->mode == FOUR_HEADPHONE_PLUGIN)) {
+		t = __ac101_get_hmic_data(codec);
+
+		if (t >= HBIAS_LEVEL_5){
+			msleep(150);
+			t = __ac101_get_hmic_data(codec);
+			if (((t < HBIAS_LEVEL_2 && t >= HBIAS_LEVEL_1 - 1) || t >= HBIAS_LEVEL_5)
+			&& (ac10x->pullout_cntr == 0)) {
+				input_report_key(ac10x->inpdev, KEY_HEADSETHOOK, 1);
+				input_sync(ac10x->inpdev);
+
+				AC101_DBG("KEY_HEADSETHOOK1\n");
+
+				if (hook_flag1 != hook_flag2)
+					hook_flag1 = hook_flag2 = 0;
+				hook_flag1++;
+			}
+			if (ac10x->pullout_cntr)
+				ac10x->pullout_cntr--;
+		} else if (t >= HBIAS_LEVEL_4) {
+			msleep(80);
+			t = __ac101_get_hmic_data(codec);
+			if (t < HBIAS_LEVEL_5 && t >= HBIAS_LEVEL_4 && (ac10x->pullout_cntr == 0)) {
+				KEY_VOLUME_FLAG = 1;
+				input_report_key(ac10x->inpdev, KEY_VOLUMEUP, 1);
+				input_sync(ac10x->inpdev);
+				input_report_key(ac10x->inpdev, KEY_VOLUMEUP, 0);
+				input_sync(ac10x->inpdev);
+
+				AC101_DBG("HMIC_DATA: %d KEY_VOLUMEUP\n", t);
+			}
+			if (ac10x->pullout_cntr)
+				ac10x->pullout_cntr--;
+		} else if (t >= HBIAS_LEVEL_3){
+			msleep(80);
+			t = __ac101_get_hmic_data(codec);
+			if (t < HBIAS_LEVEL_4 && t >= HBIAS_LEVEL_3  && (ac10x->pullout_cntr == 0)){
+				KEY_VOLUME_FLAG = 1;
+				input_report_key(ac10x->inpdev, KEY_VOLUMEDOWN, 1);
+				input_sync(ac10x->inpdev);
+				input_report_key(ac10x->inpdev, KEY_VOLUMEDOWN, 0);
+				input_sync(ac10x->inpdev);
+				AC101_DBG("KEY_VOLUMEDOWN\n");
+			}
+			if (ac10x->pullout_cntr)
+				ac10x->pullout_cntr--;
+		}
+	} else if ((t < HBIAS_LEVEL_2 && t >= HBIAS_LEVEL_1) && (ac10x->mode == FOUR_HEADPHONE_PLUGIN)) {
+		t = __ac101_get_hmic_data(codec);
+		if (t < HBIAS_LEVEL_2 && t >= HBIAS_LEVEL_1) {
+			if (KEY_VOLUME_FLAG) {
+				KEY_VOLUME_FLAG = 0;
+			}
+			if (hook_flag1 == (++hook_flag2)) {
+				hook_flag1 = hook_flag2 = 0;
+				input_report_key(ac10x->inpdev, KEY_HEADSETHOOK, 0);
+				input_sync(ac10x->inpdev);
+
+				AC101_DBG("KEY_HEADSETHOOK0\n");
+			}
+		}
+	} else {
+		while (ac10x->irq_cntr == 0 && ac10x->irq != 0) {
+			msleep(20);
+
+			t = __ac101_get_hmic_data(codec);
+
+			if (filt_index <= HEADSET_FILTER_CNT) {
+				if (filt_index++ == 0) {
+					filter_buf = t;
+				} else if (filter_buf != t) {
+					filt_index = 0;
+				}
+				continue;
+			}
+
+			filt_index = 0;
+			if (filter_buf >= HBIAS_LEVEL_2) {
+				ac10x->mode = THREE_HEADPHONE_PLUGIN;
+				ac10x->state = 2;
+			} else if (filter_buf >= HBIAS_LEVEL_1 - 1) {
+				ac10x->mode = FOUR_HEADPHONE_PLUGIN;
+				ac10x->state = 1;
+			} else {
+				ac10x->mode = HEADPHONE_IDLE;
+				ac10x->state = 0;
+			}
+			switch_status_update(ac10x);
+			ac10x->pullout_cntr = 0;
+			break;
+		}
+	}
+}
+
+/*
+ * audio_hmic_irq:  the interrupt handlers
+ */
+static irqreturn_t audio_hmic_irq(int irq, void *para)
+{
+	struct ac10x_priv *ac10x = (struct ac10x_priv *)para;
+	if (ac10x == NULL) {
+		return -EINVAL;
+	}
+
+	if (0 == schedule_work(&ac10x->work_clear_irq)){
+		AC101_DBG("[audio_hmic_irq] work already in queue_codec_irq, adding failed!\n");
+	}
+	return IRQ_HANDLED;
+}
+
+static int ac101_switch_probe(struct ac10x_priv *ac10x) {
+	struct i2c_client *i2c = ac10x->i2c101;
+	long ret;
+
+	ac10x->gpiod_irq = devm_gpiod_get_optional(&i2c->dev, "switch-irq", GPIOD_IN);
+	if (IS_ERR(ac10x->gpiod_irq)) {
+		ac10x->gpiod_irq = NULL;
+		dev_err(&i2c->dev, "failed get switch-irq in device tree\n");
+		goto _err_irq;
+	}
+
+	gpiod_direction_input(ac10x->gpiod_irq);
+
+	ac10x->irq = gpiod_to_irq(ac10x->gpiod_irq);
+	if (IS_ERR_VALUE(ac10x->irq)) {
+		pr_info("[ac101] map gpio to irq failed, errno = %ld\n", ac10x->irq);
+		ac10x->irq = 0;
+		goto _err_irq;
+	}
+
+	/* request irq, set irq type to falling edge trigger */
+	ret = devm_request_irq(ac10x->codec->dev, ac10x->irq, audio_hmic_irq, IRQF_TRIGGER_FALLING, "SWTICH_EINT", ac10x);
+	if (IS_ERR_VALUE(ret)) {
+		pr_info("[ac101] request virq %ld failed, errno = %ld\n", ac10x->irq, ret);
+		goto _err_irq;
+	}
+
+	ac10x->mode = HEADPHONE_IDLE;
+	ac10x->state = -1;
+
+	/*use for judge the state of switch*/
+	INIT_WORK(&ac10x->work_switch, work_cb_earphone_switch);
+	INIT_WORK(&ac10x->work_clear_irq, work_cb_clear_irq);
+
+	/********************create input device************************/
+	ac10x->inpdev = devm_input_allocate_device(ac10x->codec->dev);
+	if (!ac10x->inpdev) {
+		AC101_DBG("input_allocate_device: not enough memory for input device\n");
+		ret = -ENOMEM;
+		goto _err_input_allocate_device;
+	}
+
+	ac10x->inpdev->name          = "seed-voicecard-headset";
+	ac10x->inpdev->phys          = dev_name(ac10x->codec->dev);
+	ac10x->inpdev->id.bustype    = BUS_I2C;
+	ac10x->inpdev->dev.parent    = ac10x->codec->dev;
+	input_set_drvdata(ac10x->inpdev, ac10x->codec);
+
+	ac10x->inpdev->evbit[0] = BIT_MASK(EV_KEY) | BIT(EV_SW);
+
+	set_bit(KEY_HEADSETHOOK, ac10x->inpdev->keybit);
+	set_bit(KEY_VOLUMEUP,    ac10x->inpdev->keybit);
+	set_bit(KEY_VOLUMEDOWN,  ac10x->inpdev->keybit);
+	input_set_capability(ac10x->inpdev, EV_SW, SW_HEADPHONE_INSERT);
+
+	ret = input_register_device(ac10x->inpdev);
+	if (ret) {
+		AC101_DBG("input_register_device: input_register_device failed\n");
+		goto _err_input_register_device;
+	}
+
+	/* the first headset state checking */
+	switch_hw_config(ac10x->codec);
+	ac10x->irq_cntr = 1;
+	schedule_work(&ac10x->work_switch);
+
+	return 0;
+
+_err_input_register_device:
+_err_input_allocate_device:
+
+	if (ac10x->irq) {
+		devm_free_irq(&i2c->dev, ac10x->irq, ac10x);
+		ac10x->irq = 0;
+	}
+_err_irq:
+	return ret;
+}
+/******************************************************************************/
+/********************************switch****************************************/
+/******************************************************************************/
+#endif
+
+
+
+void drc_config(struct snd_soc_codec *codec)
+{
+	int reg_val;
+	reg_val = ac101_read(codec, 0xa3);
+	reg_val &= ~(0x7ff<<0);
+	reg_val |= 1<<0;
+	ac101_write(codec, 0xa3, reg_val);
+	ac101_write(codec, 0xa4, 0x2baf);
+
+	reg_val = ac101_read(codec, 0xa5);
+	reg_val &= ~(0x7ff<<0);
+	reg_val |= 1<<0;
+	ac101_write(codec, 0xa5, reg_val);
+	ac101_write(codec, 0xa6, 0x2baf);
+
+	reg_val = ac101_read(codec, 0xa7);
+	reg_val &= ~(0x7ff<<0);
+	ac101_write(codec, 0xa7, reg_val);
+	ac101_write(codec, 0xa8, 0x44a);
+
+	reg_val = ac101_read(codec, 0xa9);
+	reg_val &= ~(0x7ff<<0);
+	ac101_write(codec, 0xa9, reg_val);
+	ac101_write(codec, 0xaa, 0x1e06);
+
+	reg_val = ac101_read(codec, 0xab);
+	reg_val &= ~(0x7ff<<0);
+	reg_val |= (0x352<<0);
+	ac101_write(codec, 0xab, reg_val);
+	ac101_write(codec, 0xac, 0x6910);
+
+	reg_val = ac101_read(codec, 0xad);
+	reg_val &= ~(0x7ff<<0);
+	reg_val |= (0x77a<<0);
+	ac101_write(codec, 0xad, reg_val);
+	ac101_write(codec, 0xae, 0xaaaa);
+
+	reg_val = ac101_read(codec, 0xaf);
+	reg_val &= ~(0x7ff<<0);
+	reg_val |= (0x2de<<0);
+	ac101_write(codec, 0xaf, reg_val);
+	ac101_write(codec, 0xb0, 0xc982);
+
+	ac101_write(codec, 0x16, 0x9f9f);
+
+}
+
+void drc_enable(struct snd_soc_codec *codec,bool on)
+{
+	int reg_val;
+	if (on) {
+		ac101_write(codec, 0xb5, 0xA080);
+		reg_val = ac101_read(codec, MOD_CLK_ENA);
+		reg_val |= (0x1<<6);
+		ac101_write(codec, MOD_CLK_ENA, reg_val);
+		reg_val = ac101_read(codec, MOD_RST_CTRL);
+		reg_val |= (0x1<<6);
+		ac101_write(codec, MOD_RST_CTRL, reg_val);
+
+		reg_val = ac101_read(codec, 0xa0);
+		reg_val |= (0x7<<0);
+		ac101_write(codec, 0xa0, reg_val);
+	} else {
+		ac101_write(codec, 0xb5, 0x0);
+		reg_val = ac101_read(codec, MOD_CLK_ENA);
+		reg_val &= ~(0x1<<6);
+		ac101_write(codec, MOD_CLK_ENA, reg_val);
+		reg_val = ac101_read(codec, MOD_RST_CTRL);
+		reg_val &= ~(0x1<<6);
+		ac101_write(codec, MOD_RST_CTRL, reg_val);
+
+		reg_val = ac101_read(codec, 0xa0);
+		reg_val &= ~(0x7<<0);
+		ac101_write(codec, 0xa0, reg_val);
+	}
+}
+
+void set_configuration(struct snd_soc_codec *codec)
+{
+	if (speaker_double_used) {
+		ac101_update_bits(codec, SPKOUT_CTRL, (0x1f<<SPK_VOL), (double_speaker_val<<SPK_VOL));
+	} else {
+		ac101_update_bits(codec, SPKOUT_CTRL, (0x1f<<SPK_VOL), (single_speaker_val<<SPK_VOL));
+	}
+	ac101_update_bits(codec, HPOUT_CTRL, (0x3f<<HP_VOL), (headset_val<<HP_VOL));
+	ac101_update_bits(codec, ADC_SRCBST_CTRL, (0x7<<ADC_MIC1G), (mainmic_val<<ADC_MIC1G));
+	ac101_update_bits(codec, ADC_SRCBST_CTRL, (0x7<<ADC_MIC2G), (headsetmic_val<<ADC_MIC2G));
+	if (dmic_used) {
+		ac101_write(codec, ADC_VOL_CTRL, adc_digital_val);
+	}
+	if (drc_used) {
+		drc_config(codec);
+	}
+	/*headphone calibration clock frequency select*/
+	ac101_update_bits(codec, SPKOUT_CTRL, (0x7<<HPCALICKS), (0x7<<HPCALICKS));
+
+	/* I2S1 DAC Timeslot 0 data <- I2S1 DAC channel 0 */
+	// "AIF1IN0L Mux" <= "AIF1DACL"
+	// "AIF1IN0R Mux" <= "AIF1DACR"
+	ac101_update_bits(codec, AIF1_DACDAT_CTRL, 0x3 << AIF1_DA0L_SRC, 0x0 << AIF1_DA0L_SRC);
+	ac101_update_bits(codec, AIF1_DACDAT_CTRL, 0x3 << AIF1_DA0R_SRC, 0x0 << AIF1_DA0R_SRC);
+	/* Timeslot 0 Left & Right Channel enable */
+	ac101_update_bits(codec, AIF1_DACDAT_CTRL, 0x3 << AIF1_DA0R_ENA, 0x3 << AIF1_DA0R_ENA);
+
+	/* DAC Digital Mixer Source Select <- I2S1 DA0 */
+	// "DACL Mixer"	+= "AIF1IN0L Mux"
+	// "DACR Mixer" += "AIF1IN0R Mux"
+	ac101_update_bits(codec, DAC_MXR_SRC, 0xF << DACL_MXR_ADCL, 0x8 << DACL_MXR_ADCL);
+	ac101_update_bits(codec, DAC_MXR_SRC, 0xF << DACR_MXR_ADCR, 0x8 << DACR_MXR_ADCR);
+	/* Internal DAC Analog Left & Right Channel enable */
+	ac101_update_bits(codec, OMIXER_DACA_CTRL, 0x3 << DACALEN, 0x3 << DACALEN);
+
+	/* Output Mixer Source Select */
+	// "Left Output Mixer"  += "DACL Mixer"
+	// "Right Output Mixer" += "DACR Mixer"
+	ac101_update_bits(codec, OMIXER_SR, 0x1 << LMIXMUTEDACL, 0x1 << LMIXMUTEDACL);
+	ac101_update_bits(codec, OMIXER_SR, 0x1 << RMIXMUTEDACR, 0x1 << RMIXMUTEDACR);
+	/* Left & Right Analog Output Mixer enable */
+	ac101_update_bits(codec, OMIXER_DACA_CTRL, 0x3 << LMIXEN, 0x3 << LMIXEN);
+
+	/* Headphone Ouput Control */ 
+	// "HP_R Mux" <= "DACR Mixer"
+	// "HP_L Mux" <= "DACL Mixer"
+	ac101_update_bits(codec, HPOUT_CTRL, 0x1 << LHPS, 0x0 << LHPS);
+	ac101_update_bits(codec, HPOUT_CTRL, 0x1 << RHPS, 0x0 << RHPS);
+
+	/* Speaker Output Control */
+	// "SPK_L Mux" <= "SPK_LR Adder"
+	// "SPK_R Mux" <= "SPK_LR Adder"
+	ac101_update_bits(codec, SPKOUT_CTRL, (0x1 << LSPKS) | (0x1 << RSPKS), (0x1 << LSPKS) | (0x1 << RSPKS));
+	/* Enable Left & Right Speaker */
+	ac101_update_bits(codec, SPKOUT_CTRL, (0x1 << LSPK_EN) | (0x1 << RSPK_EN), (0x1 << LSPK_EN) | (0x1 << RSPK_EN));
+	return;
+}
+
+static int late_enable_dac(struct snd_soc_codec* codec, int event) {
+	struct ac10x_priv *ac10x = snd_soc_codec_get_drvdata(codec);
+
+	mutex_lock(&ac10x->dac_mutex);
+	switch (event) {
+	case SND_SOC_DAPM_PRE_PMU:
+		AC101_DBG();
+		if (ac10x->dac_enable == 0){
+			/*enable dac module clk*/
+			ac101_update_bits(codec, MOD_CLK_ENA, (0x1<<MOD_CLK_DAC_DIG), (0x1<<MOD_CLK_DAC_DIG));
+			ac101_update_bits(codec, MOD_RST_CTRL, (0x1<<MOD_RESET_DAC_DIG), (0x1<<MOD_RESET_DAC_DIG));
+			ac101_update_bits(codec, DAC_DIG_CTRL, (0x1<<ENDA), (0x1<<ENDA));
+			ac101_update_bits(codec, DAC_DIG_CTRL, (0x1<<ENHPF),(0x1<<ENHPF));
+		}
+		ac10x->dac_enable++;
+		break;
+	case SND_SOC_DAPM_POST_PMD:
+		if (ac10x->dac_enable != 0){
+			ac10x->dac_enable = 0;
+
+			ac101_update_bits(codec, DAC_DIG_CTRL, (0x1<<ENHPF),(0x0<<ENHPF));
+			ac101_update_bits(codec, DAC_DIG_CTRL, (0x1<<ENDA), (0x0<<ENDA));
+			/*disable dac module clk*/
+			ac101_update_bits(codec, MOD_CLK_ENA, (0x1<<MOD_CLK_DAC_DIG), (0x0<<MOD_CLK_DAC_DIG));
+			ac101_update_bits(codec, MOD_RST_CTRL, (0x1<<MOD_RESET_DAC_DIG), (0x0<<MOD_RESET_DAC_DIG));
+		}
+		break;
+	}
+	mutex_unlock(&ac10x->dac_mutex);
+	return 0;
+}
+
+static int ac101_headphone_event(struct snd_soc_codec* codec, int event) {
+	switch (event) {
+	case SND_SOC_DAPM_POST_PMU:
+		/*open*/
+		AC101_DBG("post:open\n");
+		ac101_update_bits(codec, OMIXER_DACA_CTRL, (0xf<<HPOUTPUTENABLE), (0xf<<HPOUTPUTENABLE));
+		msleep(10);
+		ac101_update_bits(codec, HPOUT_CTRL, (0x1<<HPPA_EN), (0x1<<HPPA_EN));
+		ac101_update_bits(codec, HPOUT_CTRL, (0x3<<LHPPA_MUTE), (0x3<<LHPPA_MUTE));
+		break;
+	case SND_SOC_DAPM_PRE_PMD:
+		/*close*/
+		AC101_DBG("pre:close\n");
+		ac101_update_bits(codec, HPOUT_CTRL, (0x3<<LHPPA_MUTE), (0x0<<LHPPA_MUTE));
+		msleep(10);
+		ac101_update_bits(codec, OMIXER_DACA_CTRL, (0xf<<HPOUTPUTENABLE), (0x0<<HPOUTPUTENABLE));
+		ac101_update_bits(codec, HPOUT_CTRL, (0x1<<HPPA_EN), (0x0<<HPPA_EN));
+		break;
+	}
+	return 0;
+}
+
+static int ac101_sysclk_started(void) {
+	int reg_val;
+
+	reg_val = ac101_read(static_ac10x->codec, SYSCLK_CTRL);
+	return (reg_val & (0x1<<SYSCLK_ENA));
+}
+
+static int ac101_aif1clk(struct snd_soc_codec* codec, int event, int quick) {
+	struct ac10x_priv *ac10x = snd_soc_codec_get_drvdata(codec);
+	int ret = 0;
+
+	switch (event) {
+	case SND_SOC_DAPM_PRE_PMU:
+		if (ac10x->aif1_clken == 0){
+			ret = ac101_update_bits(codec, SYSCLK_CTRL, (0x1<<AIF1CLK_ENA), (0x1<<AIF1CLK_ENA));
+			if(!quick || _MASTER_MULTI_CODEC != _MASTER_AC101) {
+				/* enable aif1clk & sysclk */
+				ret = ret || ac101_update_bits(codec, MOD_CLK_ENA, (0x1<<MOD_CLK_AIF1), (0x1<<MOD_CLK_AIF1));
+				ret = ret || ac101_update_bits(codec, MOD_RST_CTRL, (0x1<<MOD_RESET_AIF1), (0x1<<MOD_RESET_AIF1));
+			}
+			ret = ret || ac101_update_bits(codec, SYSCLK_CTRL, (0x1<<SYSCLK_ENA), (0x1<<SYSCLK_ENA));
+
+			if (ret) {
+				AC101_DBG("start sysclk failed\n");
+			} else {
+				AC101_DBG("hw sysclk enable\n");
+				ac10x->aif1_clken++;
+			}
+		}
+		break;
+	case SND_SOC_DAPM_POST_PMD:
+		if (ac10x->aif1_clken != 0) {
+			/* disable aif1clk & sysclk */
+			ret = ac101_update_bits(codec, SYSCLK_CTRL, (0x1<<AIF1CLK_ENA),(0x0<<AIF1CLK_ENA));
+			ret = ret || ac101_update_bits(codec, MOD_CLK_ENA, (0x1<<MOD_CLK_AIF1), (0x0<<MOD_CLK_AIF1));
+			ret = ret || ac101_update_bits(codec, MOD_RST_CTRL, (0x1<<MOD_RESET_AIF1), (0x0<<MOD_RESET_AIF1));
+			ret = ret || ac101_update_bits(codec, SYSCLK_CTRL, (0x1<<SYSCLK_ENA), (0x0<<SYSCLK_ENA));
+
+			if (ret) {
+				AC101_DBG("stop sysclk failed\n");
+			} else {
+				AC101_DBG("hw sysclk disable\n");
+				ac10x->aif1_clken = 0;
+			}
+			break;
+		}
+	}
+
+	AC101_DBG("event=%d pre_up/%d post_down/%d\n", event, SND_SOC_DAPM_PRE_PMU, SND_SOC_DAPM_POST_PMD);
+
+	return ret;
+}
+
+/**
+ * snd_ac101_get_volsw - single mixer get callback
+ * @kcontrol: mixer control
+ * @ucontrol: control element information
+ *
+ * Callback to get the value of a single mixer control, or a double mixer
+ * control that spans 2 registers.
+ *
+ * Returns 0 for success.
+ */
+static int snd_ac101_get_volsw(struct snd_kcontrol *kcontrol,
+	struct snd_ctl_elem_value *ucontrol
+){
+	struct soc_mixer_control *mc =
+		(struct soc_mixer_control *)kcontrol->private_value;
+	unsigned int val, mask = (1 << fls(mc->max)) - 1;
+	unsigned int invert = mc->invert;
+	int ret;
+
+	if ((ret = ac101_read(static_ac10x->codec, mc->reg)) < 0)
+		return ret;
+
+	val = (ret >> mc->shift) & mask;
+	ucontrol->value.integer.value[0] = val - mc->min;
+	if (invert) {
+		ucontrol->value.integer.value[0] =
+			mc->max - ucontrol->value.integer.value[0];
+	}
+
+	if (snd_soc_volsw_is_stereo(mc)) {
+		val = (ret >> mc->rshift) & mask;
+		ucontrol->value.integer.value[1] = val - mc->min;
+		if (invert) {
+			ucontrol->value.integer.value[1] =
+				mc->max - ucontrol->value.integer.value[1];
+		}
+	}
+	return 0;
+}
+
+/**
+ * snd_ac101_put_volsw - single mixer put callback
+ * @kcontrol: mixer control
+ * @ucontrol: control element information
+ *
+ * Callback to set the value of a single mixer control, or a double mixer
+ * control that spans 2 registers.
+ *
+ * Returns 0 for success.
+ */
+static int snd_ac101_put_volsw(struct snd_kcontrol *kcontrol,
+	struct snd_ctl_elem_value *ucontrol
+){
+	struct soc_mixer_control *mc =
+		(struct soc_mixer_control *)kcontrol->private_value;
+	unsigned int sign_bit = mc->sign_bit;
+	unsigned int val, mask = (1 << fls(mc->max)) - 1;
+	unsigned int invert = mc->invert;
+	int ret;
+
+	if (sign_bit)
+		mask = BIT(sign_bit + 1) - 1;
+
+	val = ((ucontrol->value.integer.value[0] + mc->min) & mask);
+	if (invert) {
+		val = mc->max - val;
+	}
+
+	ret = ac101_update_bits(static_ac10x->codec, mc->reg, mask << mc->shift, val << mc->shift);
+
+	if (! snd_soc_volsw_is_stereo(mc)) {
+		return ret;
+	}
+	val = ((ucontrol->value.integer.value[1] + mc->min) & mask);
+	if (invert) {
+		val = mc->max - val;
+	}
+
+	ret = ac101_update_bits(static_ac10x->codec, mc->reg, mask << mc->rshift, val << mc->rshift);
+	return ret;
+}
+
+
+static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -11925, 75, 0);
+static const DECLARE_TLV_DB_SCALE(dac_mix_vol_tlv, -600, 600, 0);
+static const DECLARE_TLV_DB_SCALE(dig_vol_tlv, -7308, 116, 0);
+static const DECLARE_TLV_DB_SCALE(speaker_vol_tlv, -4800, 150, 0);
+static const DECLARE_TLV_DB_SCALE(headphone_vol_tlv, -6300, 100, 0);
+
+static struct snd_kcontrol_new ac101_controls[] = {
+	/*DAC*/
+	SOC_DOUBLE_TLV("DAC volume", DAC_VOL_CTRL, DAC_VOL_L, DAC_VOL_R, 0xff, 0, dac_vol_tlv),
+	SOC_DOUBLE_TLV("DAC mixer gain", DAC_MXR_GAIN, DACL_MXR_GAIN, DACR_MXR_GAIN, 0xf, 0, dac_mix_vol_tlv),
+	SOC_SINGLE_TLV("digital volume", DAC_DBG_CTRL, DVC, 0x3f, 1, dig_vol_tlv),
+	SOC_SINGLE_TLV("speaker volume", SPKOUT_CTRL, SPK_VOL, 0x1f, 0, speaker_vol_tlv),
+	SOC_SINGLE_TLV("headphone volume", HPOUT_CTRL, HP_VOL, 0x3f, 0, headphone_vol_tlv),
+};
+
+/* PLL divisors */
+struct pll_div {
+	unsigned int pll_in;
+	unsigned int pll_out;
+	int m;
+	int n_i;
+	int n_f;
+};
+
+struct aif1_fs {
+	unsigned samp_rate;
+	int bclk_div;
+	int srbit;
+	#define _SERIES_24_576K		0
+	#define _SERIES_22_579K		1
+	int series;
+};
+
+struct kv_map {
+	int val;
+	int bit;
+};
+
+/*
+ * Note : pll code from original tdm/i2s driver.
+ * freq_out = freq_in * N/(M*(2k+1)) , k=1,N=N_i+N_f,N_f=factor*0.2;
+ * 		N_i[0,1023], N_f_factor[0,7], m[1,64]=REG_VAL[1-63,0]
+ */
+static const struct pll_div codec_pll_div[] = {
+	{128000,   _FREQ_22_579K,  1, 529, 1},
+	{192000,   _FREQ_22_579K,  1, 352, 4},
+	{256000,   _FREQ_22_579K,  1, 264, 3},
+	{384000,   _FREQ_22_579K,  1, 176, 2}, /*((176+2*0.2)*6000000)/(38*(2*1+1))*/
+	{1411200,  _FREQ_22_579K,  1,  48, 0},
+	{2822400,  _FREQ_22_579K,  1,  24, 0}, /* accurate, 11025 * 256 */
+	{5644800,  _FREQ_22_579K,  1,  12, 0}, /* accurate, 22050 * 256 */
+	{6000000,  _FREQ_22_579K, 38, 429, 0}, /*((429+0*0.2)*6000000)/(38*(2*1+1))*/
+	{11289600, _FREQ_22_579K,  1,   6, 0}, /* accurate, 44100 * 256 */
+	{13000000, _FREQ_22_579K, 19,  99, 0},
+	{19200000, _FREQ_22_579K, 25,  88, 1},
+	{24000000, _FREQ_22_579K, 63, 177, 4}, /* 22577778 Hz */
+
+	{128000,   _FREQ_24_576K,  1, 576, 0},
+	{192000,   _FREQ_24_576K,  1, 384, 0},
+	{256000,   _FREQ_24_576K,  1, 288, 0},
+	{384000,   _FREQ_24_576K,  1, 192, 0},
+	{2048000,  _FREQ_24_576K,  1,  36, 0}, /* accurate,  8000 * 256 */
+	{3072000,  _FREQ_24_576K,  1,  24, 0}, /* accurate, 12000 * 256 */
+	{4096000,  _FREQ_24_576K,  1,  18, 0}, /* accurate, 16000 * 256 */
+	{6000000,  _FREQ_24_576K, 25, 307, 1},
+	{6144000,  _FREQ_24_576K,  4,  48, 0}, /* accurate, 24000 * 256 */
+	{12288000, _FREQ_24_576K,  8,  48, 0}, /* accurate, 48000 * 256 */
+	{13000000, _FREQ_24_576K, 42, 238, 1},
+	{19200000, _FREQ_24_576K, 25,  96, 0},
+	{24000000, _FREQ_24_576K, 25,  76, 4}, /* accurate */
+
+	{_FREQ_22_579K, _FREQ_22_579K,  8,  24, 0}, /* accurate, 88200 * 256 */
+	{_FREQ_24_576K, _FREQ_24_576K,  8,  24, 0}, /* accurate, 96000 * 256 */
+};
+
+static const struct aif1_fs codec_aif1_fs[] = {
+	{8000, 12, 0},
+	{11025, 8, 1, _SERIES_22_579K},
+	{12000, 8, 2},
+	{16000, 6, 3},
+	{22050, 4, 4, _SERIES_22_579K},
+	{24000, 4, 5},
+	/* {32000, 3, 6}, dividing by 3 is not support */
+	{44100, 2, 7, _SERIES_22_579K},
+	{48000, 2, 8},
+	{96000, 1, 9},
+};
+
+static const struct kv_map codec_aif1_lrck[] = {
+	{16, 0},
+	{32, 1},
+	{64, 2},
+	{128, 3},
+	{256, 4},
+};
+
+static const struct kv_map codec_aif1_wsize[] = {
+	{8, 0},
+	{16, 1},
+	{20, 2},
+	{24, 3},
+	{32, 3},
+};
+
+static const unsigned ac101_bclkdivs[] = {
+	  1,   2,   4,   6,
+	  8,  12,  16,  24,
+	 32,  48,  64,  96,
+	128, 192,   0,   0,
+};
+
+static int ac101_aif_play(struct ac10x_priv* ac10x) {
+	struct snd_soc_codec * codec = ac10x->codec;
+
+	late_enable_dac(codec, SND_SOC_DAPM_PRE_PMU);
+	ac101_headphone_event(codec, SND_SOC_DAPM_POST_PMU);
+	if (drc_used) {
+		drc_enable(codec, 1);
+	}
+
+	/* Enable Left & Right Speaker */
+	ac101_update_bits(codec, SPKOUT_CTRL, (0x1 << LSPK_EN) | (0x1 << RSPK_EN), (0x1 << LSPK_EN) | (0x1 << RSPK_EN));
+	if (ac10x->gpiod_spk_amp_gate) {
+		gpiod_set_value(ac10x->gpiod_spk_amp_gate, 1);
+	}
+	return 0;
+}
+
+static void ac10x_work_aif_play(struct work_struct *work) {
+	struct ac10x_priv *ac10x = container_of(work, struct ac10x_priv, dlywork.work);
+
+	ac101_aif_play(ac10x);
+	return;
+}
+
+int ac101_aif_mute(struct snd_soc_dai *codec_dai, int mute)
+{
+	struct snd_soc_codec *codec = codec_dai->codec;
+	struct ac10x_priv *ac10x = snd_soc_codec_get_drvdata(codec);
+
+	AC101_DBG("mute=%d\n",  mute);
+
+	ac101_write(codec, DAC_VOL_CTRL, mute? 0: 0xA0A0);
+
+	if (!mute) {
+		#if _MASTER_MULTI_CODEC != _MASTER_AC101
+		/* enable global clock */
+		ac10x->aif1_clken = 0;
+		ac101_aif1clk(codec, SND_SOC_DAPM_PRE_PMU, 0);
+		ac101_aif_play(ac10x);
+		#else
+		schedule_delayed_work(&ac10x->dlywork, msecs_to_jiffies(50));
+		#endif
+	} else {
+		#if _MASTER_MULTI_CODEC == _MASTER_AC101
+		cancel_delayed_work_sync(&ac10x->dlywork);
+		#endif
+
+		if (ac10x->gpiod_spk_amp_gate) {
+			gpiod_set_value(ac10x->gpiod_spk_amp_gate, 0);
+		}
+		/* Disable Left & Right Speaker */
+		ac101_update_bits(codec, SPKOUT_CTRL, (0x1 << LSPK_EN) | (0x1 << RSPK_EN), (0x0 << LSPK_EN) | (0x0 << RSPK_EN));
+		if (drc_used) {
+			drc_enable(codec, 0);
+		}
+		ac101_headphone_event(codec, SND_SOC_DAPM_PRE_PMD);
+		late_enable_dac(codec, SND_SOC_DAPM_POST_PMD);
+
+		#if _MASTER_MULTI_CODEC != _MASTER_AC101
+		ac10x->aif1_clken = 1;
+		ac101_aif1clk(codec, SND_SOC_DAPM_POST_PMD, 0);
+		#endif
+	}
+	return 0;
+}
+
+void ac101_aif_shutdown(struct snd_pcm_substream *substream, struct snd_soc_dai *codec_dai)
+{
+	struct snd_soc_codec *codec = codec_dai->codec;
+	struct ac10x_priv *ac10x = snd_soc_codec_get_drvdata(codec);
+
+	AC101_DBG("stream = %s, play: %d, capt: %d, active: %d\n", 
+		snd_pcm_stream_str(substream),
+		codec_dai->playback_active, codec_dai->capture_active,
+		codec_dai->active);
+
+	if (!codec_dai->active) {
+		ac10x->aif1_clken = 1;
+		ac101_aif1clk(codec, SND_SOC_DAPM_POST_PMD, 0);
+	} else {
+		ac101_aif1clk(codec, SND_SOC_DAPM_PRE_PMU, 0);
+	}
+}
+
+static int ac101_set_pll(struct snd_soc_dai *codec_dai, int pll_id, int source,
+			unsigned int freq_in, unsigned int freq_out)
+{
+	struct snd_soc_codec *codec = codec_dai->codec;
+	int i, m, n_i, n_f;
+
+	AC101_DBG("pll_id:%d\n",  pll_id);
+
+	/* clear volatile reserved bits*/
+	ac101_update_bits(codec, SYSCLK_CTRL, 0xFF & ~(0x1 << SYSCLK_ENA), 0x0);
+
+	/* select aif1 clk srouce from mclk1 */
+	ac101_update_bits(codec, SYSCLK_CTRL, (0x3<<AIF1CLK_SRC), (0x0<<AIF1CLK_SRC));
+	/* disable pll */
+	ac101_update_bits(codec, PLL_CTRL2, (0x1<<PLL_EN), (0<<PLL_EN));
+
+	if (!freq_out)
+		return 0;
+	if ((freq_in < 128000) || (freq_in > _FREQ_24_576K)) {
+		return -EINVAL;
+	} else if ((freq_in == _FREQ_24_576K) || (freq_in == _FREQ_22_579K)) {
+		if (pll_id == AC101_MCLK1) {
+			/*select aif1 clk source from mclk1*/
+			ac101_update_bits(codec, SYSCLK_CTRL, (0x3<<AIF1CLK_SRC), (0x0<<AIF1CLK_SRC));
+			return 0;
+		}
+	}
+
+	switch (pll_id) {
+	case AC101_MCLK1:
+		/*pll source from MCLK1*/
+		ac101_update_bits(codec, SYSCLK_CTRL, (0x3<<PLLCLK_SRC), (0x0<<PLLCLK_SRC));
+		break;
+	case AC101_BCLK1:
+		/*pll source from BCLK1*/
+		ac101_update_bits(codec, SYSCLK_CTRL, (0x3<<PLLCLK_SRC), (0x2<<PLLCLK_SRC));
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	/* freq_out = freq_in * n/(m*(2k+1)) , k=1,N=N_i+N_f */
+	for (i = m = n_i = n_f = 0; i < ARRAY_SIZE(codec_pll_div); i++) {
+		if ((codec_pll_div[i].pll_in == freq_in) && (codec_pll_div[i].pll_out == freq_out)) {
+			m   = codec_pll_div[i].m;
+			n_i = codec_pll_div[i].n_i;
+			n_f = codec_pll_div[i].n_f;
+			break;
+		}
+	}
+	/* config pll m */
+	if (m  == 64) m = 0;
+	ac101_update_bits(codec, PLL_CTRL1, (0x3f<<PLL_POSTDIV_M), (m<<PLL_POSTDIV_M));
+	/* config pll n */
+	ac101_update_bits(codec, PLL_CTRL2, (0x3ff<<PLL_PREDIV_NI), (n_i<<PLL_PREDIV_NI));
+	ac101_update_bits(codec, PLL_CTRL2, (0x7<<PLL_POSTDIV_NF), (n_f<<PLL_POSTDIV_NF));
+	/* enable pll */
+	ac101_update_bits(codec, PLL_CTRL2, (0x1<<PLL_EN), (1<<PLL_EN));
+	ac101_update_bits(codec, SYSCLK_CTRL, (0x1<<PLLCLK_ENA),  (0x1<<PLLCLK_ENA));
+	ac101_update_bits(codec, SYSCLK_CTRL, (0x3<<AIF1CLK_SRC), (0x3<<AIF1CLK_SRC));
+
+	return 0;
+}
+
+int ac101_hw_params(struct snd_pcm_substream *substream,
+	struct snd_pcm_hw_params *params,
+	struct snd_soc_dai *codec_dai)
+{
+	int i = 0;
+	int AIF_CLK_CTRL = AIF1_CLK_CTRL;
+	int aif1_word_size = 24;
+	int aif1_slot_size = 32;
+	int aif1_lrck_div;
+	struct snd_soc_codec *codec = codec_dai->codec;
+	struct ac10x_priv *ac10x = snd_soc_codec_get_drvdata(codec);
+	int reg_val, freq_out;
+	unsigned channels;
+
+	AC101_DBG("+++\n");
+
+	if (_MASTER_MULTI_CODEC == _MASTER_AC101 && ac101_sysclk_started()) {
+		/* not configure hw_param twice if stream is playback, tell the caller it's started */
+		if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+			return 1;
+		}
+	}
+
+	/* get channels count & slot size */
+	channels = params_channels(params);
+
+	switch (params_format(params)) {
+	case SNDRV_PCM_FORMAT_S24_LE:
+	case SNDRV_PCM_FORMAT_S32_LE:
+		aif1_slot_size = 32;
+		break;
+	case SNDRV_PCM_FORMAT_S16_LE:
+	default:
+		aif1_slot_size = 16;
+		break;
+	}
+
+	/* set LRCK/BCLK ratio */
+	aif1_lrck_div = aif1_slot_size * channels;
+	for (i = 0; i < ARRAY_SIZE(codec_aif1_lrck); i++) {
+		if (codec_aif1_lrck[i].val == aif1_lrck_div) {
+			break;
+		}
+	}
+	ac101_update_bits(codec, AIF_CLK_CTRL, (0x7<<AIF1_LRCK_DIV), codec_aif1_lrck[i].bit<<AIF1_LRCK_DIV);
+
+	/* set PLL output freq */
+	freq_out = _FREQ_24_576K;
+	for (i = 0; i < ARRAY_SIZE(codec_aif1_fs); i++) {
+		if (codec_aif1_fs[i].samp_rate == params_rate(params)) {
+			if (codec_dai->capture_active && dmic_used && codec_aif1_fs[i].samp_rate == 44100) {
+				ac101_update_bits(codec, AIF_SR_CTRL, (0xf<<AIF1_FS), (0x4<<AIF1_FS));
+			} else {
+				ac101_update_bits(codec, AIF_SR_CTRL, (0xf<<AIF1_FS), ((codec_aif1_fs[i].srbit)<<AIF1_FS));
+			}
+			if (codec_aif1_fs[i].series == _SERIES_22_579K)
+				freq_out = _FREQ_22_579K;
+			break;
+		}
+	}
+
+	/* set I2S word size */
+	for (i = 0; i < ARRAY_SIZE(codec_aif1_wsize); i++) {
+		if (codec_aif1_wsize[i].val == aif1_word_size) {
+			break;
+		}
+	}
+	ac101_update_bits(codec, AIF_CLK_CTRL, (0x3<<AIF1_WORK_SIZ), ((codec_aif1_wsize[i].bit)<<AIF1_WORK_SIZ));
+
+	/* set TDM slot size */
+	if ((reg_val = codec_aif1_wsize[i].bit) > 2) reg_val = 2;
+	ac101_update_bits(codec, AIF1_ADCDAT_CTRL, 0x3 << AIF1_SLOT_SIZ, reg_val << AIF1_SLOT_SIZ);
+
+	/* setting pll if it's master mode */
+	reg_val = ac101_read(codec, AIF_CLK_CTRL);
+	if ((reg_val & (0x1 << AIF1_MSTR_MOD)) == 0) {
+		unsigned bclkdiv;
+
+		ac101_set_pll(codec_dai, AC101_MCLK1, 0, ac10x->sysclk, freq_out);
+
+		bclkdiv = freq_out / (aif1_lrck_div * params_rate(params));
+		for (i = 0; i < ARRAY_SIZE(ac101_bclkdivs) - 1; i++) {
+			if (ac101_bclkdivs[i] >= bclkdiv) {
+				break;
+			}
+		}
+		ac101_update_bits(codec, AIF_CLK_CTRL, (0xf<<AIF1_BCLK_DIV), i<<AIF1_BCLK_DIV);
+	} else {
+		/* set pll clock source to BCLK if slave mode */
+		ac101_set_pll(codec_dai, AC101_BCLK1, 0, aif1_lrck_div * params_rate(params), freq_out);
+	}
+
+	#if _MASTER_MULTI_CODEC == _MASTER_AC101
+	/* Master mode, to clear cpu_dai fifos, disable output bclk & lrck */
+	ac101_aif1clk(codec, SND_SOC_DAPM_POST_PMD, 0);
+	#endif
+
+	AC101_DBG("rate: %d , channels: %d , samp_res: %d",
+		params_rate(params), channels, aif1_slot_size);
+
+	AC101_DBG("---\n");
+	return 0;
+}
+
+int ac101_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
+{
+	int reg_val;
+	int AIF_CLK_CTRL = AIF1_CLK_CTRL;
+	struct snd_soc_codec *codec = codec_dai->codec;
+
+	AC101_DBG();
+
+	/*
+	 * 	master or slave selection
+	 *	0 = Master mode
+	 *	1 = Slave mode
+	 */
+	reg_val = ac101_read(codec, AIF_CLK_CTRL);
+	reg_val &= ~(0x1<<AIF1_MSTR_MOD);
+	switch(fmt & SND_SOC_DAIFMT_MASTER_MASK) {
+	case SND_SOC_DAIFMT_CBM_CFM:   /* codec clk & frm master, ap is slave*/
+		#if _MASTER_MULTI_CODEC == _MASTER_AC101
+		pr_warn("AC101 as Master\n");
+		reg_val |= (0x0<<AIF1_MSTR_MOD);
+		break;
+		#else
+		pr_warn("AC108 as Master\n");
+		#endif
+	case SND_SOC_DAIFMT_CBS_CFS:   /* codec clk & frm slave, ap is master*/
+		pr_warn("AC101 as Slave\n");
+		reg_val |= (0x1<<AIF1_MSTR_MOD);
+		break;
+	default:
+		pr_err("unknwon master/slave format\n");
+		return -EINVAL;
+	}
+
+	/*
+	 * Enable TDM mode
+	 */
+	reg_val |=  (0x1 << AIF1_TDMM_ENA);
+	ac101_write(codec, AIF_CLK_CTRL, reg_val);
+
+	/* i2s mode selection */
+	reg_val = ac101_read(codec, AIF_CLK_CTRL);
+	reg_val&=~(3<<AIF1_DATA_FMT);
+	switch(fmt & SND_SOC_DAIFMT_FORMAT_MASK){
+	case SND_SOC_DAIFMT_I2S:        /* I2S1 mode */
+		reg_val |= (0x0<<AIF1_DATA_FMT);
+		break;
+	case SND_SOC_DAIFMT_RIGHT_J:    /* Right Justified mode */
+		reg_val |= (0x2<<AIF1_DATA_FMT);
+		break;
+	case SND_SOC_DAIFMT_LEFT_J:     /* Left Justified mode */
+		reg_val |= (0x1<<AIF1_DATA_FMT);
+		break;
+	case SND_SOC_DAIFMT_DSP_A:      /* L reg_val msb after FRM LRC */
+		reg_val |= (0x3<<AIF1_DATA_FMT);
+		break;
+	case SND_SOC_DAIFMT_DSP_B:
+		/* TODO: data offset set to 0 */
+		reg_val |= (0x3<<AIF1_DATA_FMT);
+		break;
+	default:
+		pr_err("%s, line:%d\n", __func__, __LINE__);
+		return -EINVAL;
+	}
+	ac101_write(codec, AIF_CLK_CTRL, reg_val);
+
+	/* DAI signal inversions */
+	reg_val = ac101_read(codec, AIF_CLK_CTRL);
+	switch(fmt & SND_SOC_DAIFMT_INV_MASK){
+	case SND_SOC_DAIFMT_NB_NF:     /* normal bit clock + nor frame */
+		reg_val &= ~(0x1<<AIF1_LRCK_INV);
+		reg_val &= ~(0x1<<AIF1_BCLK_INV);
+		break;
+	case SND_SOC_DAIFMT_NB_IF:     /* normal bclk + inv frm */
+		reg_val |= (0x1<<AIF1_LRCK_INV);
+		reg_val &= ~(0x1<<AIF1_BCLK_INV);
+		break;
+	case SND_SOC_DAIFMT_IB_NF:     /* invert bclk + nor frm */
+		reg_val &= ~(0x1<<AIF1_LRCK_INV);
+		reg_val |= (0x1<<AIF1_BCLK_INV);
+		break;
+	case SND_SOC_DAIFMT_IB_IF:     /* invert bclk + inv frm */
+		reg_val |= (0x1<<AIF1_LRCK_INV);
+		reg_val |= (0x1<<AIF1_BCLK_INV);
+		break;
+	}
+	ac101_write(codec, AIF_CLK_CTRL, reg_val);
+
+	return 0;
+}
+
+int ac101_audio_startup(struct snd_pcm_substream *substream,
+	struct snd_soc_dai *codec_dai)
+{
+	// struct snd_soc_codec *codec = codec_dai->codec;
+
+	AC101_DBG("\n\n\n");
+
+	if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
+	}
+	return 0;
+}
+
+#if _MASTER_MULTI_CODEC == _MASTER_AC101
+static int ac101_set_clock(int y_start_n_stop) {
+	int r;
+
+	if (y_start_n_stop) {
+		/* enable global clock */
+		r = ac101_aif1clk(static_ac10x->codec, SND_SOC_DAPM_PRE_PMU, 1);
+	} else {
+		/* disable global clock */
+		static_ac10x->aif1_clken = 1;
+		r = ac101_aif1clk(static_ac10x->codec, SND_SOC_DAPM_POST_PMD, 0);
+	}
+	return r;
+}
+#endif
+
+int ac101_trigger(struct snd_pcm_substream *substream, int cmd,
+	 	  struct snd_soc_dai *dai)
+{
+	struct snd_soc_codec *codec = dai->codec;
+	struct ac10x_priv *ac10x = snd_soc_codec_get_drvdata(codec);
+	int ret = 0;
+
+	AC101_DBG("stream=%s  cmd=%d\n",
+		snd_pcm_stream_str(substream),
+		cmd);
+
+	switch (cmd) {
+	case SNDRV_PCM_TRIGGER_START:
+	case SNDRV_PCM_TRIGGER_RESUME:
+	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
+		#if _MASTER_MULTI_CODEC == _MASTER_AC101
+		if (ac10x->aif1_clken == 0){
+			/*
+			 * enable aif1clk, it' here due to reduce time between 'AC108 Sysclk Enable' and 'AC101 Sysclk Enable'
+			 * Or else the two AC108 chips lost the sync.
+			 */
+			ret = 0;
+			ret = ret || ac101_update_bits(codec, MOD_CLK_ENA, (0x1<<MOD_CLK_AIF1), (0x1<<MOD_CLK_AIF1));
+			ret = ret || ac101_update_bits(codec, MOD_RST_CTRL, (0x1<<MOD_RESET_AIF1), (0x1<<MOD_RESET_AIF1));
+		}
+		#endif
+		break;
+	case SNDRV_PCM_TRIGGER_STOP:
+	case SNDRV_PCM_TRIGGER_SUSPEND:
+	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
+		break;
+	default:
+		ret = -EINVAL;
+	}
+	return ret;
+}
+
+#if 0
+static int ac101_set_dai_sysclk(struct snd_soc_dai *codec_dai,
+				  int clk_id, unsigned int freq, int dir)
+{
+	struct snd_soc_codec *codec = codec_dai->codec;
+	struct ac10x_priv *ac10x = snd_soc_codec_get_drvdata(codec);
+
+	AC101_DBG("id=%d freq=%d, dir=%d\n", 
+		clk_id, freq, dir);
+
+	ac10x->sysclk = freq;
+
+	return 0;
+}
+
+static const struct snd_soc_dai_ops ac101_aif1_dai_ops = {
+	//.startup	= ac101_audio_startup,
+	//.shutdown	= ac101_aif_shutdown,
+	//.set_sysclk	= ac101_set_dai_sysclk,
+	//.set_pll	= ac101_set_pll,
+	//.set_fmt	= ac101_set_dai_fmt,
+	//.hw_params	= ac101_hw_params,
+	//.trigger	= ac101_trigger,
+	//.digital_mute	= ac101_aif_mute,
+};
+
+static struct snd_soc_dai_driver ac101_dai[] = {
+	{
+		.name = "ac10x-aif1",
+		.id = AIF1_CLK,
+		.playback = {
+			.stream_name = "Playback",
+			.channels_min = 1,
+			.channels_max = 8,
+			.rates = AC101_RATES,
+			.formats = AC101_FORMATS,
+		},
+		#if 0
+		.capture = {
+			.stream_name = "Capture",
+			.channels_min = 1,
+			.channels_max = 8,
+			.rates = AC101_RATES,
+			.formats = AC101_FORMATS,
+		},
+		#endif
+		.ops = &ac101_aif1_dai_ops,
+	}
+};
+#endif
+
+static void codec_resume_work(struct work_struct *work)
+{
+	struct ac10x_priv *ac10x = container_of(work, struct ac10x_priv, codec_resume);
+	struct snd_soc_codec *codec = ac10x->codec;
+
+	AC101_DBG("+++\n");
+
+	set_configuration(codec);
+	if (drc_used) {
+		drc_config(codec);
+	}
+	/*enable this bit to prevent leakage from ldoin*/
+	ac101_update_bits(codec, ADDA_TUNE3, (0x1<<OSCEN), (0x1<<OSCEN));
+
+	AC101_DBG("---\n");
+	return;
+}
+
+int ac101_set_bias_level(struct snd_soc_codec *codec, enum snd_soc_bias_level level)
+{
+	switch (level) {
+	case SND_SOC_BIAS_ON:
+		AC101_DBG("SND_SOC_BIAS_ON\n");
+		break;
+	case SND_SOC_BIAS_PREPARE:
+		AC101_DBG("SND_SOC_BIAS_PREPARE\n");
+		break;
+	case SND_SOC_BIAS_STANDBY:
+		AC101_DBG("SND_SOC_BIAS_STANDBY\n");
+		#ifdef CONFIG_AC101_SWITCH_DETECT
+		switch_hw_config(codec);
+		#endif
+		break;
+	case SND_SOC_BIAS_OFF:
+		#ifdef CONFIG_AC101_SWITCH_DETECT
+		ac101_update_bits(codec, ADC_APC_CTRL, (0x1<<HBIASEN), (0<<HBIASEN));
+		ac101_update_bits(codec, ADC_APC_CTRL, (0x1<<HBIASADCEN), (0<<HBIASADCEN));
+		#endif
+		ac101_update_bits(codec, OMIXER_DACA_CTRL, (0xf<<HPOUTPUTENABLE), (0<<HPOUTPUTENABLE));
+		ac101_update_bits(codec, ADDA_TUNE3, (0x1<<OSCEN), (0<<OSCEN));
+		AC101_DBG("SND_SOC_BIAS_OFF\n");
+		break;
+	}
+	snd_soc_codec_get_dapm(codec)->bias_level = level;
+	return 0;
+}
+
+int ac101_codec_probe(struct snd_soc_codec *codec)
+{
+	int ret = 0;
+	struct ac10x_priv *ac10x;
+
+	ac10x = dev_get_drvdata(codec->dev);
+	if (ac10x == NULL) {
+		AC101_DBG("not set client data!\n");
+		return -ENOMEM;
+	}
+	ac10x->codec = codec;
+
+	INIT_DELAYED_WORK(&ac10x->dlywork, ac10x_work_aif_play);
+	INIT_WORK(&ac10x->codec_resume, codec_resume_work);
+	ac10x->dac_enable = 0;
+	ac10x->aif1_clken = 0;
+	mutex_init(&ac10x->dac_mutex);
+
+	#if _MASTER_MULTI_CODEC == _MASTER_AC101
+	seeed_voice_card_register_set_clock(SNDRV_PCM_STREAM_PLAYBACK, ac101_set_clock);
+	#endif
+
+	set_configuration(ac10x->codec);
+
+	/*enable this bit to prevent leakage from ldoin*/
+	ac101_update_bits(codec, ADDA_TUNE3, (0x1<<OSCEN), (0x1<<OSCEN));
+	ac101_write(codec, DAC_VOL_CTRL, 0);
+
+	/* customized get/put inteface */
+	for (ret = 0; ret < ARRAY_SIZE(ac101_controls); ret++) {
+		struct snd_kcontrol_new* skn = &ac101_controls[ret];
+
+		skn->get = snd_ac101_get_volsw;
+		skn->put = snd_ac101_put_volsw;
+	}
+	ret = snd_soc_add_codec_controls(codec, ac101_controls,	ARRAY_SIZE(ac101_controls));
+	if (ret) {
+		pr_err("[ac10x] Failed to register audio mode control, "
+				"will continue without it.\n");
+	}
+
+	#ifdef CONFIG_AC101_SWITCH_DETECT
+	ret = ac101_switch_probe(ac10x);
+	if (ret) {
+		// not care the switch return value
+	}
+	#endif
+
+	return 0;
+}
+
+/* power down chip */
+int ac101_codec_remove(struct snd_soc_codec *codec)
+{
+	#ifdef CONFIG_AC101_SWITCH_DETECT
+	struct ac10x_priv *ac10x = snd_soc_codec_get_drvdata(codec);
+
+	if (ac10x->irq) {
+		devm_free_irq(codec->dev, ac10x->irq, ac10x);
+		ac10x->irq = 0;
+	}
+
+	if (cancel_work_sync(&ac10x->work_switch) != 0) {
+	}
+
+	if (cancel_work_sync(&ac10x->work_clear_irq) != 0) {
+	}
+
+	if (ac10x->inpdev) {
+		input_unregister_device(ac10x->inpdev);
+		ac10x->inpdev = NULL;
+	}
+	#endif
+
+	return 0;
+}
+
+int ac101_codec_suspend(struct snd_soc_codec *codec)
+{
+	struct ac10x_priv *ac10x = snd_soc_codec_get_drvdata(codec);
+
+	AC101_DBG("[codec]:suspend\n");
+	regcache_cache_only(ac10x->regmap101, true);
+	return 0;
+}
+
+int ac101_codec_resume(struct snd_soc_codec *codec)
+{
+	struct ac10x_priv *ac10x = snd_soc_codec_get_drvdata(codec);
+	int ret;
+
+	AC101_DBG("[codec]:resume");
+
+	/* Sync reg_cache with the hardware */
+	regcache_cache_only(ac10x->regmap101, false);
+	ret = regcache_sync(ac10x->regmap101);
+	if (ret != 0) {
+		dev_err(codec->dev, "Failed to sync register cache: %d\n", ret);
+		regcache_cache_only(ac10x->regmap101, true);
+		return ret;
+	}
+
+	#ifdef CONFIG_AC101_SWITCH_DETECT
+	ac10x->mode = HEADPHONE_IDLE;
+	ac10x->state = -1;
+	#endif
+
+	ac101_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
+	schedule_work(&ac10x->codec_resume);
+	return 0;
+}
+
+/***************************************************************************/
+static ssize_t ac101_debug_store(struct device *dev,
+	struct device_attribute *attr, const char *buf, size_t count)
+{
+	struct ac10x_priv *ac10x = dev_get_drvdata(dev);
+	int val = 0, flag = 0;
+	u16 value_w, value_r;
+	u8 reg, num, i=0;
+
+	val = simple_strtol(buf, NULL, 16);
+	flag = (val >> 24) & 0xF;
+	if (flag) {
+		reg = (val >> 16) & 0xFF;
+		value_w =  val & 0xFFFF;
+		ac101_write(ac10x->codec, reg, value_w);
+		printk("write 0x%x to reg:0x%x\n", value_w, reg);
+	} else {
+		reg = (val >> 8) & 0xFF;
+		num = val & 0xff;
+		printk("\n");
+		printk("read:start add:0x%x,count:0x%x\n", reg, num);
+
+		regcache_cache_bypass(ac10x->regmap101, true);
+		do {
+			value_r = ac101_read(ac10x->codec, reg);
+			printk("0x%x: 0x%04x ", reg++, value_r);
+			if (++i % 4 == 0 || i == num)
+				printk("\n");
+		} while (i < num);
+		regcache_cache_bypass(ac10x->regmap101, false);
+	}
+	return count;
+}
+static ssize_t ac101_debug_show(struct device *dev,
+	struct device_attribute *attr, char *buf)
+{
+	printk("echo flag|reg|val > ac10x\n");
+	printk("eg read star addres=0x06,count 0x10:echo 0610 >ac10x\n");
+	printk("eg write value:0x13fe to address:0x06 :echo 10613fe > ac10x\n");
+	return 0;
+}
+static DEVICE_ATTR(ac10x, 0644, ac101_debug_show, ac101_debug_store);
+
+static struct attribute *audio_debug_attrs[] = {
+	&dev_attr_ac10x.attr,
+	NULL,
+};
+
+static struct attribute_group audio_debug_attr_group = {
+	.name   = "ac101_debug",
+	.attrs  = audio_debug_attrs,
+};
+/***************************************************************************/
+
+/************************************************************/
+static bool ac101_volatile_reg(struct device *dev, unsigned int reg)
+{
+	switch (reg) {
+	case PLL_CTRL2:
+	case HMIC_STS:
+		return true;
+	}
+	return false;
+}
+
+static const struct regmap_config ac101_regmap = {
+	.reg_bits = 8,
+	.val_bits = 16,
+	.reg_stride = 1,
+	.max_register = 0xB5,
+	.cache_type = REGCACHE_FLAT,
+	.volatile_reg = ac101_volatile_reg,
+};
+
+/* Sync reg_cache from the hardware */
+int ac10x_fill_regcache(struct device* dev, struct regmap* map) {
+	int r, i, n;
+	int v;
+
+	n = regmap_get_max_register(map);
+	for (i = 0; i < n; i++) {
+		regcache_cache_bypass(map, true);
+		r = regmap_read(map, i, &v);
+		if (r) {
+			dev_err(dev, "failed to read register %d\n", i);
+			continue;
+		}
+		regcache_cache_bypass(map, false);
+
+		regcache_cache_only(map, true);
+		r = regmap_write(map, i, v);
+		regcache_cache_only(map, false);
+	}
+	regcache_cache_bypass(map, false);
+	regcache_cache_only(map, false);
+
+	return 0;
+}
+
+int ac101_probe(struct i2c_client *i2c, const struct i2c_device_id *id)
+{
+	struct ac10x_priv *ac10x = i2c_get_clientdata(i2c);
+	int ret = 0;
+	unsigned v = 0;
+
+	AC101_DBG();
+
+	static_ac10x = ac10x;
+
+	ac10x->regmap101 = devm_regmap_init_i2c(i2c, &ac101_regmap);
+	if (IS_ERR(ac10x->regmap101)) {
+		ret = PTR_ERR(ac10x->regmap101);
+		dev_err(&i2c->dev, "Fail to initialize I/O: %d\n", ret);
+		return ret;
+	}
+
+	/* Chip reset */
+	regcache_cache_only(ac10x->regmap101, false);
+	ret = regmap_write(ac10x->regmap101, CHIP_AUDIO_RST, 0);
+	msleep(50);
+
+	/* sync regcache for FLAT type */
+	ac10x_fill_regcache(&i2c->dev, ac10x->regmap101);
+
+	ret = regmap_read(ac10x->regmap101, CHIP_AUDIO_RST, &v);
+	if (ret < 0) {
+		dev_err(&i2c->dev, "failed to read vendor ID: %d\n", ret);
+		return ret;
+	}
+
+	if (v != AC101_CHIP_ID) {
+		dev_err(&i2c->dev, "chip is not AC101 (%X)\n", v);
+		dev_err(&i2c->dev, "Expected %X\n", AC101_CHIP_ID);
+		return -ENODEV;
+	}
+
+	ret = sysfs_create_group(&i2c->dev.kobj, &audio_debug_attr_group);
+	if (ret) {
+		pr_err("failed to create attr group\n");
+	}
+
+	ac10x->gpiod_spk_amp_gate = devm_gpiod_get_optional(&i2c->dev, "spk-amp-switch", GPIOD_OUT_LOW);
+	if (IS_ERR(ac10x->gpiod_spk_amp_gate)) {
+		ac10x->gpiod_spk_amp_gate = NULL;
+		dev_err(&i2c->dev, "failed get spk-amp-switch in device tree\n");
+	}
+
+	return 0;
+}
+
+void ac101_shutdown(struct i2c_client *i2c)
+{
+	struct ac10x_priv *ac10x = i2c_get_clientdata(i2c);
+	struct snd_soc_codec *codec = ac10x->codec;
+	int reg_val;
+
+	if (codec == NULL) {
+		pr_err(": no sound card.\n");
+		return;
+	}
+
+	/*set headphone volume to 0*/
+	reg_val = ac101_read(codec, HPOUT_CTRL);
+	reg_val &= ~(0x3f<<HP_VOL);
+	ac101_write(codec, HPOUT_CTRL, reg_val);
+
+	/*disable pa*/
+	reg_val = ac101_read(codec, HPOUT_CTRL);
+	reg_val &= ~(0x1<<HPPA_EN);
+	ac101_write(codec, HPOUT_CTRL, reg_val);
+
+	/*hardware xzh support*/
+	reg_val = ac101_read(codec, OMIXER_DACA_CTRL);
+	reg_val &= ~(0xf<<HPOUTPUTENABLE);
+	ac101_write(codec, OMIXER_DACA_CTRL, reg_val);
+
+	/*unmute l/r headphone pa*/
+	reg_val = ac101_read(codec, HPOUT_CTRL);
+	reg_val &= ~((0x1<<RHPPA_MUTE)|(0x1<<LHPPA_MUTE));
+	ac101_write(codec, HPOUT_CTRL, reg_val);
+	return;
+}
+
+int ac101_remove(struct i2c_client *i2c)
+{
+	sysfs_remove_group(&i2c->dev.kobj, &audio_debug_attr_group);
+	return 0;
+}
+
+MODULE_DESCRIPTION("ASoC ac10x driver");
+MODULE_AUTHOR("huangxin,liushaohua");
+MODULE_AUTHOR("PeterYang<linsheng.yang@seeed.cc>");
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/seeed-voicecard/ac101_regs.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/seeed-voicecard/ac101_regs.h
new file mode 100644
index 0000000000000000000000000000000000000000..8be570ea319f76c9148f2fe875022dece660b1dd
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/seeed-voicecard/ac101_regs.h
@@ -0,0 +1,432 @@
+/*
+ * ac101_regs.h
+ *
+ * (C) Copyright 2017-2018
+ * Seeed Technology Co., Ltd. <www.seeedstudio.com>
+ *
+ * PeterYang <linsheng.yang@seeed.cc>
+ *
+ * (C) Copyright 2010-2017
+ * Reuuimlla Technology Co., Ltd. <www.reuuimllatech.com>
+ * huangxin <huangxin@reuuimllatech.com>
+ *
+ * some simple description for this code
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ */
+#ifndef __AC101_REGS_H__
+#define __AC101_REGS_H__
+
+/*pll source*/
+#define AC101_MCLK1 1
+#define AC101_MCLK2 2
+#define AC101_BCLK1 3
+#define AC101_BCLK2 4
+
+#define AIF1_CLK 1
+#define AIF2_CLK 2
+
+#define	CHIP_AUDIO_RST		0x0
+#define PLL_CTRL1		0x1
+#define PLL_CTRL2		0x2
+#define SYSCLK_CTRL		0x3
+#define MOD_CLK_ENA		0x4
+#define MOD_RST_CTRL		0x5
+#define AIF_SR_CTRL		0x6
+
+#define AIF1_CLK_CTRL		0x10
+#define AIF1_ADCDAT_CTRL	0x11
+#define AIF1_DACDAT_CTRL	0x12
+#define AIF1_MXR_SRC		0x13
+#define AIF1_VOL_CTRL1		0x14
+#define AIF1_VOL_CTRL2		0x15
+#define AIF1_VOL_CTRL3		0x16
+#define AIF1_VOL_CTRL4		0x17
+#define AIF1_MXR_GAIN		0x18
+#define AIF1_RXD_CTRL		0x19
+#define ADC_DIG_CTRL		0x40
+#define ADC_VOL_CTRL		0x41
+#define ADC_DBG_CTRL		0x42
+
+#define HMIC_CTRL1			0x44
+#define HMIC_CTRL2			0x45
+#define HMIC_STS			0x46
+
+#define DAC_DIG_CTRL		0x48
+#define DAC_VOL_CTRL		0x49
+#define DAC_DBG_CTRL		0x4a
+#define DAC_MXR_SRC			0x4c
+#define DAC_MXR_GAIN		0x4d
+
+#define ADC_APC_CTRL		0x50
+#define ADC_SRC				0x51
+#define ADC_SRCBST_CTRL		0x52
+#define OMIXER_DACA_CTRL	0x53
+#define OMIXER_SR			0x54
+#define OMIXER_BST1_CTRL	0x55
+#define HPOUT_CTRL			0x56
+#define ESPKOUT_CTRL		0x57
+#define SPKOUT_CTRL			0x58
+#define LOUT_CTRL			0x59
+#define ADDA_TUNE1			0x5a
+#define ADDA_TUNE2			0x5b
+#define ADDA_TUNE3			0x5c
+#define HPOUT_STR			0x5d
+
+/*CHIP_AUDIO_RST*/
+#define AC101_CHIP_ID			0x0101
+
+/*PLL_CTRL1*/
+#define DPLL_DAC_BIAS		14
+#define PLL_POSTDIV_M		8
+#define CLOSE_LOOP		6
+#define INT			0
+
+/*PLL_CTRL2*/
+#define PLL_EN			15
+#define PLL_LOCK_STATUS		14
+#define PLL_PREDIV_NI		4
+#define PLL_POSTDIV_NF		0
+
+/*SYSCLK_CTRL*/
+#define PLLCLK_ENA			15
+#define PLLCLK_SRC			12
+#define AIF1CLK_ENA			11
+#define AIF1CLK_SRC			8
+#define AIF2CLK_ENA			7
+#define AIF2CLK_SRC			4
+#define SYSCLK_ENA			3
+#define SYSCLK_SRC			0
+
+/*MOD_CLK_ENA*/
+#define MOD_CLK_AIF1		15
+#define MOD_CLK_AIF2		14
+#define MOD_CLK_AIF3		13
+#define MOD_CLK_SRC1		11
+#define MOD_CLK_SRC2		10
+#define MOD_CLK_HPF_AGC		7
+#define MOD_CLK_HPF_DRC		6
+#define MOD_CLK_ADC_DIG		3
+#define MOD_CLK_DAC_DIG		2
+
+/*MOD_RST_CTRL*/
+#define MOD_RESET_CTL		0
+#define MOD_RESET_AIF1		15
+#define MOD_RESET_AIF2		14
+#define MOD_RESET_AIF3		13
+#define MOD_RESET_SRC1		11
+#define MOD_RESET_SRC2		10
+#define MOD_RESET_HPF_AGC	7
+#define MOD_RESET_HPF_DRC	6
+#define MOD_RESET_ADC_DIG	3
+#define MOD_RESET_DAC_DIG	2
+
+/*AIF_SR_CTRL*/
+#define AIF1_FS				12	//AIF1 Sample Rate
+#define AIF2_FS				8	//AIF2 Sample Rate
+#define SRC1_ENA			3
+#define SRC1_SRC			2
+#define SRC2_ENA			1
+#define SRC2_SRC			0
+
+/*AIF1LCK_CTRL*/
+#define AIF1_MSTR_MOD		15
+#define AIF1_BCLK_INV		14
+#define AIF1_LRCK_INV		13
+#define AIF1_BCLK_DIV		9
+#define AIF1_LRCK_DIV		6
+#define AIF1_WORK_SIZ		4
+#define AIF1_DATA_FMT		2
+#define DSP_MONO_PCM		1
+#define AIF1_TDMM_ENA		0
+
+/*AIF1_ADCDAT_CTRL*/
+#define AIF1_AD0L_ENA		15
+#define AIF1_AD0R_ENA		14
+#define AIF1_AD1L_ENA		13
+#define AIF1_AD1R_ENA		12
+#define AIF1_AD0L_SRC		10
+#define AIF1_AD0R_SRC		8
+#define AIF1_AD1L_SRC		6
+#define AIF1_AD1R_SRC		4
+#define AIF1_ADCP_ENA		3
+#define AIF1_ADUL_ENA		2
+#define AIF1_SLOT_SIZ		0
+
+/*AIF1_DACDAT_CTRL*/
+#define AIF1_DA0L_ENA		15
+#define AIF1_DA0R_ENA		14
+#define AIF1_DA1L_ENA		13
+#define AIF1_DA1R_ENA		12
+#define AIF1_DA0L_SRC		10
+#define AIF1_DA0R_SRC		8
+#define AIF1_DA1L_SRC		6
+#define AIF1_DA1R_SRC		4
+#define AIF1_DACP_ENA		3
+#define AIF1_DAUL_ENA		2
+#define AIF1_SLOT_SIZ		0
+
+/*AIF1_MXR_SRC*/
+#define AIF1_AD0L_AIF1_DA0L_MXR		15
+#define AIF1_AD0L_AIF2_DACL_MXR		14
+#define AIF1_AD0L_ADCL_MXR		13
+#define AIF1_AD0L_AIF2_DACR_MXR		12
+#define AIF1_AD0R_AIF1_DA0R_MXR		11
+#define AIF1_AD0R_AIF2_DACR_MXR		10
+#define AIF1_AD0R_ADCR_MXR		9
+#define AIF1_AD0R_AIF2_DACL_MXR		8
+#define AIF1_AD1L_AIF2_DACL_MXR		7
+#define AIF1_AD1L_ADCL_MXR		6
+#define AIF1_AD1L_MXR_SRC	6
+#define AIF1_AD1R_AIF2_DACR_MXR		3
+#define AIF1_AD1R_ADCR_MXR		2
+#define AIF1_AD1R_MXR_SRC	2
+
+/*AIF1_VOL_CTRL1*/
+#define AIF1_AD0L_VOL		8
+#define AIF1_AD0R_VOL		0
+
+/*AIF1_VOL_CTRL2*/
+#define AIF1_AD1L_VOL		8
+#define AIF1_AD1R_VOL		0
+
+/*AIF1_VOL_CTRL3*/
+#define AIF1_DA0L_VOL		8
+#define AIF1_DA0R_VOL		0
+
+/*AIF1_VOL_CTRL4*/
+#define AIF1_DA1L_VOL		8
+#define AIF1_DA1R_VOL 		0
+
+/*AIF1_MXR_GAIN*/
+#define AIF1_AD0L_MXR_GAIN	12
+#define AIF1_AD0R_MXR_GAIN	8
+#define AIF1_AD1L_MXR_GAIN	6
+#define AIF1_AD1R_MXR_GAIN	2
+
+/*AIF1_RXD_CTRL*/
+#define AIF1_N_DATA_DISCARD	8
+
+/*ADC_DIG_CTRL*/
+#define ENAD				15
+#define ENDM				14
+#define ADFIR32				13
+#define ADOUT_DTS			2
+#define ADOUT_DLY			1
+
+/*ADC_VOL_CTRL*/
+#define ADC_VOL_L			8
+#define ADC_VOL_R			0
+
+/*ADC_DBG_CTRL*/
+#define ADSW				15
+#define DMIC_CLK_PIN_CTRL 	12
+
+/*HMIC_CTRL1*/
+#define HMIC_M				12
+#define HMIC_N				8
+#define HMIC_DATA_IRQ_MODE	7
+#define HMIC_TH1_HYSTERESIS	5
+#define HMIC_PULLOUT_IRQ	4
+#define HMIC_PLUGIN_IRQ		3
+#define HMIC_KEYUP_IRQ		2
+#define HMIC_KEYDOWN_IRQ	1
+#define HMIC_DATA_IRQ_EN	0
+
+/*HMIC_CTRL2*/
+#define HMIC_SAMPLE_SELECT	14
+#define HMIC_TH2_HYSTERESIS	13
+#define HMIC_TH2			8
+#define HMIC_SF				6
+#define KEYUP_CLEAR			5
+#define HMIC_TH1			0
+
+/*HMIC_STS*/
+#define HMIC_DATA			8
+#define GET_HMIC_DATA(r)		(((r) >> HMIC_DATA) & 0x1F)
+#define HMIC_PULLOUT_PEND	4
+#define HMIC_PLUGIN_PEND	3
+#define HMIC_KEYUP_PEND		2
+#define HMKC_KEYDOWN_PEND	1
+#define HMIC_DATA_PEND		0
+#define HMIC_PEND_ALL		(0x1F)
+
+/*DAC_DIG_CTRL*/
+#define ENDA				15
+#define ENHPF				14
+#define DAFIR32				13
+#define MODQU				8
+
+/*DAC_VOL_CTRL*/
+#define DAC_VOL_L			8
+#define DAC_VOL_R			0
+
+/*DAC_DBG_CTRL*/
+#define DASW				15
+#define ENDWA_N				14
+#define DAC_MOD_DBG			13
+#define DAC_PTN_SEL			6
+#define DVC				0
+
+/*DAC_MXR_SRC*/
+#define DACL_MXR_AIF1_DA0L		15
+#define DACL_MXR_AIF1_DA1L		14
+#define DACL_MXR_AIF2_DACL		13
+#define DACL_MXR_ADCL			12
+#define DACL_MXR_SRC			12
+#define DACR_MXR_AIF1_DA0R		11
+#define DACR_MXR_AIF1_DA1R		10
+#define DACR_MXR_AIF2_DACR		9
+#define DACR_MXR_ADCR			8
+#define DACR_MXR_SRC		8
+
+/*DAC_MXR_GAIN*/
+#define DACL_MXR_GAIN		12
+#define DACR_MXR_GAIN		8
+
+/*ADC_APC_CTRL*/
+#define ADCREN				15
+#define ADCRG				12
+#define ADCLEN				11
+#define ADCLG				8
+#define MBIASEN				7
+#define MMIC_BIAS_CHOP_EN		6
+#define MMIC_BIAS_CHOP_CKS		4
+#define HBIASMOD			2
+#define HBIASEN				1
+#define HBIASADCEN			0
+
+/*ADC_SRC*/
+#define RADCMIXMUTEMIC1BOOST	  (13)
+#define RADCMIXMUTEMIC2BOOST	  (12)
+#define RADCMIXMUTELINEINLR		  (11)
+#define RADCMIXMUTELINEINR		  (10)
+#define RADCMIXMUTEAUXINR		  (9)
+#define RADCMIXMUTEROUTPUT		  (8)
+#define RADCMIXMUTELOUTPUT		  (7)
+#define LADCMIXMUTEMIC1BOOST	  (6)
+#define LADCMIXMUTEMIC2BOOST	  (5)
+#define LADCMIXMUTELINEINLR		  (4)
+#define LADCMIXMUTELINEINL		  (3)
+#define LADCMIXMUTEAUXINL		  (2)
+#define LADCMIXMUTELOUTPUT		  (1)
+#define LADCMIXMUTEROUTPUT		  (0)
+
+
+/*ADC_SRCBST_CTRL*/
+#define MIC1AMPEN			15
+#define ADC_MIC1G			12
+#define MIC2AMPEN			11
+#define ADC_MIC2G			8
+#define MIC2SLT				7
+#define LINEIN_PREG			4
+#define AUXI_PREG			0
+
+/*OMIXER_DACA_CTRL*/
+#define DACAREN				15
+#define DACALEN				14
+#define RMIXEN				13
+#define LMIXEN				12
+#define HPOUTPUTENABLE			8
+
+/*OMIXER_SR*/
+#define RMIXMUTEMIC1BOOST		  (13)
+#define RMIXMUTEMIC2BOOST		  (12)
+#define RMIXMUTELINEINLR		  (11)
+#define RMIXMUTELINEINR			  (10)
+#define RMIXMUTEAUXINR			  (9)
+#define RMIXMUTEDACR			  (8)
+#define RMIXMUTEDACL			  (7)
+#define LMIXMUTEMIC1BOOST		  (6)
+#define LMIXMUTEMIC2BOOST		  (5)
+#define LMIXMUTELINEINLR		  (4)
+#define LMIXMUTELINEINL			  (3)
+#define LMIXMUTEAUXINL			  (2)
+#define LMIXMUTEDACL			  (1)
+#define LMIXMUTEDACR			  (0)
+
+/*OMIXER_BST1_CTRL*/
+#define BIASVOLTAGE			12
+#define AXG				9
+#define OMIXER_MIC1G			6
+#define OMIXER_MIC2G			3
+#define LINEING				0
+
+/*HPOUT_CTRL*/
+#define RHPS				15
+#define LHPS				14
+#define RHPPA_MUTE			13
+#define LHPPA_MUTE			12
+#define HPPA_EN				11
+#define HP_VOL				4
+#define HPPA_DEL			2
+#define HPPA_IS				0
+
+/*ESPKOUT_CTRL*/
+#define EAR_RAMP_TIME		11
+#define	ESPA_OUT_CURRENT	9
+#define ESPSR				7
+#define ESPPA_MUTE			6
+#define ESPPA_EN			5
+#define ESP_VOL				0
+
+/*SPKOUT_CTRL*/
+#define HPCALICKS			13
+#define RSPKS				12
+#define RSPKINVEN			11
+#define RSPK_EN				9
+#define LSPKS				8
+#define LSPKINVEN			7
+#define LSPK_EN				5
+#define SPK_VOL				0
+
+/*LOUT_CTRL*/
+#define LINEOUTG			5
+#define LINEOUTEN			4
+#define LINEOUTS0			3
+#define LINEOUTS1			2
+#define LINEOUTS2			1
+#define LINEOUTS3			0
+
+/*ADDA_TUNE1*/
+#define CURRENT_TEST_SELECT	14
+#define BIHE_CTRL			12
+#define DITHER				11
+#define DITHER_CLK			9
+#define ZERO_CROSSOVER_EN	8
+#define ZERO_CROSSOVER_TIME 7
+#define EAR_SPEED_SELECT	6
+#define REF_CHOPPEN_CKS		4
+#define OPMIC_BIAS_CUR		0
+
+/*ADDA_TUNE2*/
+#define OPDAC_BIAS_CUR		14
+#define OPDRV_BIAS_CUR		12
+#define OPMIX_BIAS_CUR		10
+#define OPEAR_BIAS_CUR		8
+#define OPVR_BIAS_CUR		6
+#define OPAAF_BIAS_CUR		4
+#define OPADC1_BIAS_CUR		2
+#define OPADC2_BIAS_CUR		0
+
+/*ADDA_TUNE3*/
+#define LDOEN				15
+#define LDO_SEL				12
+#define BIASCALIVERIFY			11
+#define BIASMODE			10
+#define BIASCALIDATA			9
+#define OSCS				1
+#define OSCEN				0
+
+/*HPOUT_STR*/
+#define HPVL_SOFT_MOD		14
+#define	HPVL_STEP_CTRL		8
+#define  DACA_CHND_ENA		7
+#define HPPA_MXRD_ENA		6
+#define HPVL_CTRL_OUT		0
+
+#endif//__AC101_REGS_H__
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/seeed-voicecard/ac108.c b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/seeed-voicecard/ac108.c
new file mode 100644
index 0000000000000000000000000000000000000000..cd20547f789755140f5fbdb35353e84a0858087d
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/seeed-voicecard/ac108.c
@@ -0,0 +1,1548 @@
+/*
+ * ac10x.c  --  ac10x ALSA SoC Audio driver
+ *
+ *
+ * Author: Baozhu Zuo<zuobaozhu@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/* #undef DEBUG
+ * use 'make DEBUG=1' to enable debugging
+ */
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/pm.h>
+#include <linux/clk.h>
+#include <linux/i2c.h>
+#include <linux/slab.h>
+#include <linux/workqueue.h>
+#include <linux/regmap.h>
+#include <linux/gpio/consumer.h>
+#include <sound/core.h>
+#include <sound/pcm.h>
+#include <sound/pcm_params.h>
+#include <sound/soc.h>
+#include <sound/initval.h>
+#include <sound/tlv.h>
+#include "ac108.h"
+#include "ac10x.h"
+
+#define _USE_CAPTURE	1
+#define _MASTER_INDEX	0
+
+/**
+ * TODO: 
+ * 1, add PM API:  ac108_suspend,ac108_resume 
+ * 2,0x65-0x6a 
+ * 3,0x76-0x79 high 4bit 
+ */
+struct pll_div {
+	unsigned int freq_in;
+	unsigned int freq_out;
+	unsigned int m1;
+	unsigned int m2;
+	unsigned int n;
+	unsigned int k1;
+	unsigned int k2;
+};
+
+static struct ac10x_priv *ac10x;
+
+struct real_val_to_reg_val {
+	unsigned int real_val;
+	unsigned int reg_val;
+};
+
+static const struct real_val_to_reg_val ac108_sample_rate[] = {
+	{ 8000,  0 },
+	{ 11025, 1 },
+	{ 12000, 2 },
+	{ 16000, 3 },
+	{ 22050, 4 },
+	{ 24000, 5 },
+	{ 32000, 6 },
+	{ 44100, 7 },
+	{ 48000, 8 },
+	{ 96000, 9 },
+};
+
+/* Sample resolution */
+static const struct real_val_to_reg_val ac108_samp_res[] = {
+	{ 8,  1 },
+	{ 12, 2 },
+	{ 16, 3 },
+	{ 20, 4 },
+	{ 24, 5 },
+	{ 28, 6 },
+	{ 32, 7 },
+};
+
+static const unsigned ac108_bclkdivs[] = {
+	 0,   1,   2,   4,
+	 6,   8,  12,  16,
+	24,  32,  48,  64,
+	96, 128, 176, 192,
+};
+
+/* FOUT =(FIN * N) / [(M1+1) * (M2+1)*(K1+1)*(K2+1)] ;	M1[0,31],  M2[0,1],  N[0,1023],  K1[0,31],  K2[0,1] */
+static const struct pll_div ac108_pll_div_list[] = {
+	{ 400000,   _FREQ_24_576K, 0,  0, 614, 4, 1 },
+	{ 512000,   _FREQ_24_576K, 0,  0, 960, 9, 1 }, //_FREQ_24_576K/48
+	{ 768000,   _FREQ_24_576K, 0,  0, 640, 9, 1 }, //_FREQ_24_576K/32
+	{ 800000,   _FREQ_24_576K, 0,  0, 614, 9, 1 },
+	{ 1024000,  _FREQ_24_576K, 0,  0, 480, 9, 1 }, //_FREQ_24_576K/24
+	{ 1600000,  _FREQ_24_576K, 0,  0, 307, 9, 1 },
+	{ 2048000,  _FREQ_24_576K, 0,  0, 240, 9, 1 }, /* accurate,  8000 * 256 */
+	{ 3072000,  _FREQ_24_576K, 0,  0, 160, 9, 1 }, /* accurate, 12000 * 256 */
+	{ 4096000,  _FREQ_24_576K, 2,  0, 360, 9, 1 }, /* accurate, 16000 * 256 */
+	{ 6000000,  _FREQ_24_576K, 4,  0, 410, 9, 1 },
+	{ 12000000, _FREQ_24_576K, 9,  0, 410, 9, 1 },
+	{ 13000000, _FREQ_24_576K, 8,  0, 340, 9, 1 },
+	{ 15360000, _FREQ_24_576K, 12, 0, 415, 9, 1 },
+	{ 16000000, _FREQ_24_576K, 12, 0, 400, 9, 1 },
+	{ 19200000, _FREQ_24_576K, 15, 0, 410, 9, 1 },
+	{ 19680000, _FREQ_24_576K, 15, 0, 400, 9, 1 },
+	{ 24000000, _FREQ_24_576K, 4,  0, 128,24, 0 }, // accurate, 24M -> 24.576M */
+
+	{ 400000,   _FREQ_22_579K, 0,  0, 566, 4, 1 },
+	{ 512000,   _FREQ_22_579K, 0,  0, 880, 9, 1 },
+	{ 768000,   _FREQ_22_579K, 0,  0, 587, 9, 1 },
+	{ 800000,   _FREQ_22_579K, 0,  0, 567, 9, 1 },
+	{ 1024000,  _FREQ_22_579K, 0,  0, 440, 9, 1 },
+	{ 1600000,  _FREQ_22_579K, 1,  0, 567, 9, 1 },
+	{ 2048000,  _FREQ_22_579K, 0,  0, 220, 9, 1 },
+	{ 3072000,  _FREQ_22_579K, 0,  0, 148, 9, 1 },
+	{ 4096000,  _FREQ_22_579K, 2,  0, 330, 9, 1 },
+	{ 6000000,  _FREQ_22_579K, 2,  0, 227, 9, 1 },
+	{ 12000000, _FREQ_22_579K, 8,  0, 340, 9, 1 },
+	{ 13000000, _FREQ_22_579K, 9,  0, 350, 9, 1 },
+	{ 15360000, _FREQ_22_579K, 10, 0, 325, 9, 1 },
+	{ 16000000, _FREQ_22_579K, 11, 0, 340, 9, 1 },
+	{ 19200000, _FREQ_22_579K, 13, 0, 330, 9, 1 },
+	{ 19680000, _FREQ_22_579K, 14, 0, 345, 9, 1 },
+	{ 24000000, _FREQ_22_579K, 24, 0, 588,24, 0 }, // accurate, 24M -> 22.5792M */
+
+
+	{ _FREQ_24_576K / 1,   _FREQ_24_576K, 9,  0, 200, 9, 1 }, //_FREQ_24_576K
+	{ _FREQ_24_576K / 2,   _FREQ_24_576K, 9,  0, 400, 9, 1 }, /*12288000,accurate, 48000 * 256 */
+	{ _FREQ_24_576K / 4,   _FREQ_24_576K, 4,  0, 400, 9, 1 }, /*6144000, accurate, 24000 * 256 */
+	{ _FREQ_24_576K / 16,  _FREQ_24_576K, 0,  0, 320, 9, 1 }, //1536000
+	{ _FREQ_24_576K / 64,  _FREQ_24_576K, 0,  0, 640, 4, 1 }, //384000
+	{ _FREQ_24_576K / 96,  _FREQ_24_576K, 0,  0, 960, 4, 1 }, //256000
+	{ _FREQ_24_576K / 128, _FREQ_24_576K, 0,  0, 512, 1, 1 }, //192000
+	{ _FREQ_24_576K / 176, _FREQ_24_576K, 0,  0, 880, 4, 0 }, //140000
+	{ _FREQ_24_576K / 192, _FREQ_24_576K, 0,  0, 960, 4, 0 }, //128000
+
+	{ _FREQ_22_579K / 1,   _FREQ_22_579K, 9,  0, 200, 9, 1 }, //_FREQ_22_579K
+	{ _FREQ_22_579K / 2,   _FREQ_22_579K, 9,  0, 400, 9, 1 }, /*11289600,accurate, 44100 * 256 */
+	{ _FREQ_22_579K / 4,   _FREQ_22_579K, 4,  0, 400, 9, 1 }, /*5644800, accurate, 22050 * 256 */
+	{ _FREQ_22_579K / 16,  _FREQ_22_579K, 0,  0, 320, 9, 1 }, //1411200
+	{ _FREQ_22_579K / 64,  _FREQ_22_579K, 0,  0, 640, 4, 1 }, //352800
+	{ _FREQ_22_579K / 96,  _FREQ_22_579K, 0,  0, 960, 4, 1 }, //235200
+	{ _FREQ_22_579K / 128, _FREQ_22_579K, 0,  0, 512, 1, 1 }, //176400
+	{ _FREQ_22_579K / 176, _FREQ_22_579K, 0,  0, 880, 4, 0 }, //128290
+	{ _FREQ_22_579K / 192, _FREQ_22_579K, 0,  0, 960, 4, 0 }, //117600
+
+	{ _FREQ_22_579K / 6,   _FREQ_22_579K, 2,  0, 360, 9, 1 }, //3763200
+	{ _FREQ_22_579K / 8,   _FREQ_22_579K, 0,  0, 160, 9, 1 }, /*2822400, accurate, 11025 * 256 */
+	{ _FREQ_22_579K / 12,  _FREQ_22_579K, 0,  0, 240, 9, 1 }, //1881600
+	{ _FREQ_22_579K / 24,  _FREQ_22_579K, 0,  0, 480, 9, 1 }, //940800
+	{ _FREQ_22_579K / 32,  _FREQ_22_579K, 0,  0, 640, 9, 1 }, //705600
+	{ _FREQ_22_579K / 48,  _FREQ_22_579K, 0,  0, 960, 9, 1 }, //470400
+};
+
+
+/* AC108 definition */
+#define AC108_CHANNELS_MAX		8		/* range[1, 16] */
+#define AC108_RATES			(SNDRV_PCM_RATE_8000_96000 &		\
+					~(SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_64000 | \
+					SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000))
+#define AC108_FORMATS			(/*SNDRV_PCM_FMTBIT_S16_LE | \
+					SNDRV_PCM_FMTBIT_S20_3LE |   \
+					SNDRV_PCM_FMTBIT_S24_LE |*/  \
+					SNDRV_PCM_FMTBIT_S32_LE)
+
+static const DECLARE_TLV_DB_SCALE(tlv_adc_pga_gain, 0, 100, 0);
+static const DECLARE_TLV_DB_SCALE(tlv_ch_digital_vol, -11925,75,0);
+
+int ac10x_read(u8 reg, u8* rt_val, struct regmap* i2cm) {
+	int r, v = 0;
+
+	if ((r = regmap_read(i2cm, reg, &v)) < 0) {
+		pr_err("ac10x_read error->[REG-0x%02x]\n", reg);
+	} else {
+		*rt_val = v;
+	}
+	return r;
+}
+
+int ac10x_write(u8 reg, u8 val, struct regmap* i2cm) {
+	int r;
+
+	if ((r = regmap_write(i2cm, reg, val)) < 0) {
+		pr_err("ac10x_write error->[REG-0x%02x,val-0x%02x]\n", reg, val);
+	}
+	return r;
+}
+
+int ac10x_update_bits(u8 reg, u8 mask, u8 val, struct regmap* i2cm) {
+	int r;
+
+	if ((r = regmap_update_bits(i2cm, reg, mask, val)) < 0) {
+		pr_err("%s() error->[REG-0x%02x,val-0x%02x]\n", __func__, reg, val);
+	}
+	return r;
+}
+
+/**
+ * snd_ac108_get_volsw - single mixer get callback
+ * @kcontrol: mixer control
+ * @ucontrol: control element information
+ *
+ * Callback to get the value of a single mixer control, or a double mixer
+ * control that spans 2 registers.
+ *
+ * Returns 0 for success.
+ */
+static int snd_ac108_get_volsw(struct snd_kcontrol *kcontrol,
+	struct snd_ctl_elem_value *ucontrol
+){
+	struct soc_mixer_control *mc =
+		(struct soc_mixer_control *)kcontrol->private_value;
+	unsigned int mask = (1 << fls(mc->max)) - 1;
+	unsigned int invert = mc->invert;
+	int ret, chip = mc->autodisable;
+	u8 val;
+
+	if ((ret = ac10x_read(mc->reg, &val, ac10x->i2cmap[chip])) < 0)
+		return ret;
+
+	val = ((val >> mc->shift) & mask) - mc->min;
+	if (invert) {
+		val = mc->max - val;
+	}
+	ucontrol->value.integer.value[0] = val;
+	return 0;
+}
+
+/**
+ * snd_ac108_put_volsw - single mixer put callback
+ * @kcontrol: mixer control
+ * @ucontrol: control element information
+ *
+ * Callback to set the value of a single mixer control, or a double mixer
+ * control that spans 2 registers.
+ *
+ * Returns 0 for success.
+ */
+static int snd_ac108_put_volsw(struct snd_kcontrol *kcontrol,
+	struct snd_ctl_elem_value *ucontrol
+){
+	struct soc_mixer_control *mc =
+		(struct soc_mixer_control *)kcontrol->private_value;
+	unsigned int sign_bit = mc->sign_bit;
+	unsigned int val, mask = (1 << fls(mc->max)) - 1;
+	unsigned int invert = mc->invert;
+	int ret, chip = mc->autodisable;
+
+	if (sign_bit)
+		mask = BIT(sign_bit + 1) - 1;
+
+	val = ((ucontrol->value.integer.value[0] + mc->min) & mask);
+	if (invert) {
+		val = mc->max - val;
+	}
+
+	mask = mask << mc->shift;
+	val = val << mc->shift;
+
+	ret = ac10x_update_bits(mc->reg, mask, val, ac10x->i2cmap[chip]);
+	return ret;
+}
+
+#define SOC_AC108_SINGLE_TLV(xname, reg, shift, max, invert, chip, tlv_array) \
+{	.iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
+	.access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
+		 SNDRV_CTL_ELEM_ACCESS_READWRITE,\
+	.tlv.p = (tlv_array), \
+	.info = snd_soc_info_volsw, .get = snd_ac108_get_volsw,\
+	.put = snd_ac108_put_volsw, \
+	.private_value = SOC_SINGLE_VALUE(reg, shift, max, invert, chip) }
+
+/* single ac108 */
+static const struct snd_kcontrol_new ac108_snd_controls[] = {
+	/* ### chip 0 ### */
+	/*0x70: ADC1 Digital Channel Volume Control Register*/
+	SOC_AC108_SINGLE_TLV("CH1 digital volume", ADC1_DVOL_CTRL, 0, 0xff, 0, 0, tlv_ch_digital_vol),
+	/*0x71: ADC2 Digital Channel Volume Control Register*/
+	SOC_AC108_SINGLE_TLV("CH2 digital volume", ADC2_DVOL_CTRL, 0, 0xff, 0, 0, tlv_ch_digital_vol),
+	/*0x72: ADC3 Digital Channel Volume Control Register*/
+	SOC_AC108_SINGLE_TLV("CH3 digital volume", ADC3_DVOL_CTRL, 0, 0xff, 0, 0, tlv_ch_digital_vol),
+	/*0x73: ADC4 Digital Channel Volume Control Register*/
+	SOC_AC108_SINGLE_TLV("CH4 digital volume", ADC4_DVOL_CTRL, 0, 0xff, 0, 0, tlv_ch_digital_vol),
+
+	/*0x90: Analog PGA1 Control Register*/
+	SOC_AC108_SINGLE_TLV("ADC1 PGA gain", ANA_PGA1_CTRL, ADC1_ANALOG_PGA, 0x1f, 0, 0, tlv_adc_pga_gain),
+	/*0x91: Analog PGA2 Control Register*/
+	SOC_AC108_SINGLE_TLV("ADC2 PGA gain", ANA_PGA2_CTRL, ADC2_ANALOG_PGA, 0x1f, 0, 0, tlv_adc_pga_gain),
+	/*0x92: Analog PGA3 Control Register*/
+	SOC_AC108_SINGLE_TLV("ADC3 PGA gain", ANA_PGA3_CTRL, ADC3_ANALOG_PGA, 0x1f, 0, 0, tlv_adc_pga_gain),
+	/*0x93: Analog PGA4 Control Register*/
+	SOC_AC108_SINGLE_TLV("ADC4 PGA gain", ANA_PGA4_CTRL, ADC4_ANALOG_PGA, 0x1f, 0, 0, tlv_adc_pga_gain),
+};
+/* multiple ac108s */
+static const struct snd_kcontrol_new ac108tdm_snd_controls[] = {
+	/* ### chip 1 ### */
+	/*0x70: ADC1 Digital Channel Volume Control Register*/
+	SOC_AC108_SINGLE_TLV("CH1 digital volume", ADC1_DVOL_CTRL, 0, 0xff, 0, 1, tlv_ch_digital_vol),
+	/*0x71: ADC2 Digital Channel Volume Control Register*/
+	SOC_AC108_SINGLE_TLV("CH2 digital volume", ADC2_DVOL_CTRL, 0, 0xff, 0, 1, tlv_ch_digital_vol),
+	/*0x72: ADC3 Digital Channel Volume Control Register*/
+	SOC_AC108_SINGLE_TLV("CH3 digital volume", ADC3_DVOL_CTRL, 0, 0xff, 0, 1, tlv_ch_digital_vol),
+	/*0x73: ADC4 Digital Channel Volume Control Register*/
+	SOC_AC108_SINGLE_TLV("CH4 digital volume", ADC4_DVOL_CTRL, 0, 0xff, 0, 1, tlv_ch_digital_vol),
+
+	/*0x90: Analog PGA1 Control Register*/
+	SOC_AC108_SINGLE_TLV("ADC1 PGA gain", ANA_PGA1_CTRL, ADC1_ANALOG_PGA, 0x1f, 0, 1, tlv_adc_pga_gain),
+	/*0x91: Analog PGA2 Control Register*/
+	SOC_AC108_SINGLE_TLV("ADC2 PGA gain", ANA_PGA2_CTRL, ADC2_ANALOG_PGA, 0x1f, 0, 1, tlv_adc_pga_gain),
+	/*0x92: Analog PGA3 Control Register*/
+	SOC_AC108_SINGLE_TLV("ADC3 PGA gain", ANA_PGA3_CTRL, ADC3_ANALOG_PGA, 0x1f, 0, 1, tlv_adc_pga_gain),
+	/*0x93: Analog PGA4 Control Register*/
+	SOC_AC108_SINGLE_TLV("ADC4 PGA gain", ANA_PGA4_CTRL, ADC4_ANALOG_PGA, 0x1f, 0, 1, tlv_adc_pga_gain),
+
+	/* ### chip 0 ### */
+	/*0x70: ADC1 Digital Channel Volume Control Register*/
+	SOC_AC108_SINGLE_TLV("CH5 digital volume", ADC1_DVOL_CTRL, 0, 0xff, 0, 0, tlv_ch_digital_vol),
+	/*0x71: ADC2 Digital Channel Volume Control Register*/
+	SOC_AC108_SINGLE_TLV("CH6 digital volume", ADC2_DVOL_CTRL, 0, 0xff, 0, 0, tlv_ch_digital_vol),
+	/*0x72: ADC3 Digital Channel Volume Control Register*/
+	SOC_AC108_SINGLE_TLV("CH7 digital volume", ADC3_DVOL_CTRL, 0, 0xff, 0, 0, tlv_ch_digital_vol),
+	/*0x73: ADC4 Digital Channel Volume Control Register*/
+	SOC_AC108_SINGLE_TLV("CH8 digital volume", ADC4_DVOL_CTRL, 0, 0xff, 0, 0, tlv_ch_digital_vol),
+
+	/*0x90: Analog PGA1 Control Register*/
+	SOC_AC108_SINGLE_TLV("ADC5 PGA gain", ANA_PGA1_CTRL, ADC1_ANALOG_PGA, 0x1f, 0, 0, tlv_adc_pga_gain),
+	/*0x91: Analog PGA2 Control Register*/
+	SOC_AC108_SINGLE_TLV("ADC6 PGA gain", ANA_PGA2_CTRL, ADC2_ANALOG_PGA, 0x1f, 0, 0, tlv_adc_pga_gain),
+	/*0x92: Analog PGA3 Control Register*/
+	SOC_AC108_SINGLE_TLV("ADC7 PGA gain", ANA_PGA3_CTRL, ADC3_ANALOG_PGA, 0x1f, 0, 0, tlv_adc_pga_gain),
+	/*0x93: Analog PGA4 Control Register*/
+	SOC_AC108_SINGLE_TLV("ADC8 PGA gain", ANA_PGA4_CTRL, ADC4_ANALOG_PGA, 0x1f, 0, 0, tlv_adc_pga_gain),
+};
+
+
+static const struct snd_soc_dapm_widget ac108_dapm_widgets[] = {
+	//input widgets
+	SND_SOC_DAPM_INPUT("MIC1P"),
+	SND_SOC_DAPM_INPUT("MIC1N"),
+
+	SND_SOC_DAPM_INPUT("MIC2P"),
+	SND_SOC_DAPM_INPUT("MIC2N"),
+
+	SND_SOC_DAPM_INPUT("MIC3P"),
+	SND_SOC_DAPM_INPUT("MIC3N"),
+
+	SND_SOC_DAPM_INPUT("MIC4P"),
+	SND_SOC_DAPM_INPUT("MIC4N"),
+
+	SND_SOC_DAPM_INPUT("DMIC1"),
+	SND_SOC_DAPM_INPUT("DMIC2"),
+
+	/*0xa0: ADC1 Analog Control 1 Register*/
+	/*0xa1-0xa6:use the defualt value*/
+	SND_SOC_DAPM_AIF_IN("Channel 1 AAF", "Capture", 0, ANA_ADC1_CTRL1, ADC1_DSM_ENABLE, 1),
+	SND_SOC_DAPM_SUPPLY("Channel 1 EN", ANA_ADC1_CTRL1, ADC1_PGA_ENABLE, 1, NULL, 0),
+	SND_SOC_DAPM_MICBIAS("MIC1BIAS", ANA_ADC1_CTRL1, ADC1_MICBIAS_EN, 1),
+
+	/*0xa7: ADC2 Analog Control 1 Register*/
+	/*0xa8-0xad:use the defualt value*/
+	SND_SOC_DAPM_AIF_IN("Channel 2 AAF", "Capture", 0, ANA_ADC2_CTRL1, ADC2_DSM_ENABLE, 1),
+	SND_SOC_DAPM_SUPPLY("Channel 2 EN", ANA_ADC2_CTRL1, ADC2_PGA_ENABLE, 1, NULL, 0),
+	SND_SOC_DAPM_MICBIAS("MIC2BIAS", ANA_ADC2_CTRL1, ADC2_MICBIAS_EN, 1),
+
+	/*0xae: ADC3 Analog Control 1 Register*/
+	/*0xaf-0xb4:use the defualt value*/
+	SND_SOC_DAPM_AIF_IN("Channel 3 AAF", "Capture", 0, ANA_ADC3_CTRL1, ADC3_DSM_ENABLE, 1),
+	SND_SOC_DAPM_SUPPLY("Channel 3 EN", ANA_ADC3_CTRL1, ADC3_PGA_ENABLE, 1, NULL, 0),
+	SND_SOC_DAPM_MICBIAS("MIC3BIAS", ANA_ADC3_CTRL1, ADC3_MICBIAS_EN, 1),
+
+	/*0xb5: ADC4 Analog Control 1 Register*/
+	/*0xb6-0xbb:use the defualt value*/
+	SND_SOC_DAPM_AIF_IN("Channel 4 AAF", "Capture", 0, ANA_ADC4_CTRL1, ADC4_DSM_ENABLE, 1),
+	SND_SOC_DAPM_SUPPLY("Channel 4 EN", ANA_ADC4_CTRL1, ADC4_PGA_ENABLE, 1, NULL, 0),
+	SND_SOC_DAPM_MICBIAS("MIC4BIAS", ANA_ADC4_CTRL1, ADC4_MICBIAS_EN, 1),
+
+
+	/*0x61: ADC Digital Part Enable Register*/
+	SND_SOC_DAPM_SUPPLY("ADC EN", ADC_DIG_EN, 4,  1, NULL, 0),
+	SND_SOC_DAPM_ADC("ADC1", "Capture", ADC_DIG_EN, 0,  1),
+	SND_SOC_DAPM_ADC("ADC2", "Capture", ADC_DIG_EN, 1,  1),
+	SND_SOC_DAPM_ADC("ADC3", "Capture", ADC_DIG_EN, 2,  1),
+	SND_SOC_DAPM_ADC("ADC4", "Capture", ADC_DIG_EN, 3,  1),
+
+	SND_SOC_DAPM_SUPPLY("ADC1 CLK", ANA_ADC4_CTRL7, ADC1_CLK_GATING, 1, NULL, 0),
+	SND_SOC_DAPM_SUPPLY("ADC2 CLK", ANA_ADC4_CTRL7, ADC2_CLK_GATING, 1, NULL, 0),
+	SND_SOC_DAPM_SUPPLY("ADC3 CLK", ANA_ADC4_CTRL7, ADC3_CLK_GATING, 1, NULL, 0),
+	SND_SOC_DAPM_SUPPLY("ADC4 CLK", ANA_ADC4_CTRL7, ADC4_CLK_GATING, 1, NULL, 0),
+
+	SND_SOC_DAPM_SUPPLY("DSM EN", ANA_ADC4_CTRL6, DSM_DEMOFF, 1, NULL, 0),
+
+	/*0x62:Digital MIC Enable Register*/
+	SND_SOC_DAPM_MICBIAS("DMIC1 enable", DMIC_EN, 0, 0),
+	SND_SOC_DAPM_MICBIAS("DMIC2 enable", DMIC_EN, 1, 0),
+};
+
+static const struct snd_soc_dapm_route ac108_dapm_routes[] = {
+
+	{ "ADC1", NULL, "Channel 1 AAF" },
+	{ "ADC2", NULL, "Channel 2 AAF" },
+	{ "ADC3", NULL, "Channel 3 AAF" },
+	{ "ADC4", NULL, "Channel 4 AAF" },
+
+	{ "Channel 1 AAF", NULL, "MIC1BIAS" },
+	{ "Channel 2 AAF", NULL, "MIC2BIAS" },
+	{ "Channel 3 AAF", NULL, "MIC3BIAS" },
+	{ "Channel 4 AAF", NULL, "MIC4BIAS" },
+
+	{ "MIC1BIAS", NULL, "ADC1 CLK" },
+	{ "MIC2BIAS", NULL, "ADC2 CLK" },
+	{ "MIC3BIAS", NULL, "ADC3 CLK" },
+	{ "MIC4BIAS", NULL, "ADC4 CLK" },
+
+
+	{ "ADC1 CLK", NULL, "DSM EN" },
+	{ "ADC2 CLK", NULL, "DSM EN" },
+	{ "ADC3 CLK", NULL, "DSM EN" },
+	{ "ADC4 CLK", NULL, "DSM EN" },
+
+
+	{ "DSM EN", NULL, "ADC EN" },
+
+	{ "Channel 1 EN", NULL, "DSM EN" },
+	{ "Channel 2 EN", NULL, "DSM EN" },
+	{ "Channel 3 EN", NULL, "DSM EN" },
+	{ "Channel 4 EN", NULL, "DSM EN" },
+
+
+	{ "MIC1P", NULL, "Channel 1 EN" },
+	{ "MIC1N", NULL, "Channel 1 EN" },
+
+	{ "MIC2P", NULL, "Channel 2 EN" },
+	{ "MIC2N", NULL, "Channel 2 EN" },
+
+	{ "MIC3P", NULL, "Channel 3 EN" },
+	{ "MIC3N", NULL, "Channel 3 EN" },
+
+	{ "MIC4P", NULL, "Channel 4 EN" },
+	{ "MIC4N", NULL, "Channel 4 EN" },
+
+};
+
+static int ac108_multi_write(u8 reg, u8 val, struct ac10x_priv *ac10x) {
+	u8 i;
+	for (i = 0; i < ac10x->codec_cnt; i++) {
+		ac10x_write(reg, val, ac10x->i2cmap[i]);
+	}
+	return 0;
+}
+
+static int ac108_multi_update_bits(u8 reg, u8 mask, u8 val, struct ac10x_priv *ac10x) {
+	int r = 0;
+	u8 i;
+
+	for (i = 0; i < ac10x->codec_cnt; i++) {
+		r |= ac10x_update_bits(reg, mask, val, ac10x->i2cmap[i]);
+	}
+	return r;
+}
+
+static unsigned int ac108_codec_read(struct snd_soc_codec *codec, unsigned int reg) {
+	unsigned char val_r;
+	struct ac10x_priv *ac10x = dev_get_drvdata(codec->dev);
+	/*read one chip is fine*/
+	ac10x_read(reg, &val_r, ac10x->i2cmap[_MASTER_INDEX]);
+	return val_r;
+}
+
+static int ac108_codec_write(struct snd_soc_codec *codec, unsigned int reg, unsigned int val) {
+	struct ac10x_priv *ac10x = dev_get_drvdata(codec->dev);
+	ac108_multi_write(reg, val, ac10x);
+	return 0;
+}
+
+/**
+ * The Power management related registers are Reg01h~Reg09h
+ * 0x01-0x05,0x08,use the default value
+ * @author baozhu (17-6-21)
+ * 
+ * @param ac10x 
+ */
+static void ac108_configure_power(struct ac10x_priv *ac10x) {
+	/**
+	 * 0x06:Enable Analog LDO
+	 */
+	ac108_multi_update_bits(PWR_CTRL6, 0x01 << LDO33ANA_ENABLE, 0x01 << LDO33ANA_ENABLE, ac10x);
+	/**
+	 * 0x07: 
+	 * Control VREF output and micbias voltage ? 
+	 * REF faststart disable, enable Enable VREF (needed for Analog 
+	 * LDO and MICBIAS) 
+	 */
+	ac108_multi_update_bits(PWR_CTRL7, 0x1f << VREF_SEL | 0x01 << VREF_FASTSTART_ENABLE | 0x01 << VREF_ENABLE,
+					   0x13 << VREF_SEL | 0x00 << VREF_FASTSTART_ENABLE | 0x01 << VREF_ENABLE, ac10x);
+	/**
+	 * 0x09: 
+	 * Disable fast-start circuit on VREFP 
+	 * VREFP_RESCTRL=00=1 MOhm 
+	 * IGEN_TRIM=100=+25% 
+	 * Enable VREFP (needed by all audio input channels) 
+	 */
+	ac108_multi_update_bits(PWR_CTRL9, 0x01 << VREFP_FASTSTART_ENABLE | 0x03 << VREFP_RESCTRL | 0x07 << IGEN_TRIM | 0x01 << VREFP_ENABLE,
+					   0x00 << VREFP_FASTSTART_ENABLE | 0x00 << VREFP_RESCTRL | 0x04 << IGEN_TRIM | 0x01 << VREFP_ENABLE,
+					   ac10x);
+}
+
+/**
+ * The clock management related registers are Reg20h~Reg25h
+ * The PLL management related registers are Reg10h~Reg18h.
+ * @author baozhu (17-6-20)
+ * 
+ * @param ac10x 
+ * @param rate : sample rate
+ * 
+ * @return int : fail or success
+ */
+static int ac108_config_pll(struct ac10x_priv *ac10x, unsigned rate, unsigned lrck_ratio) {
+	unsigned int i = 0;
+	struct pll_div ac108_pll_div = { 0 };
+
+	if (ac10x->clk_id == SYSCLK_SRC_PLL) {
+		unsigned pll_src, pll_freq_in;
+
+		if (lrck_ratio == 0) {
+			/* PLL clock source from MCLK */
+			pll_freq_in = ac10x->sysclk;
+			pll_src = 0x0;
+		} else {
+			/* PLL clock source from BCLK */
+			pll_freq_in = rate * lrck_ratio;
+			pll_src = 0x1;
+		}
+
+		/* FOUT =(FIN * N) / [(M1+1) * (M2+1)*(K1+1)*(K2+1)] */
+		for (i = 0; i < ARRAY_SIZE(ac108_pll_div_list); i++) {
+			if (ac108_pll_div_list[i].freq_in == pll_freq_in && ac108_pll_div_list[i].freq_out % rate == 0) {
+				ac108_pll_div = ac108_pll_div_list[i];
+				dev_dbg(&ac10x->i2c[_MASTER_INDEX]->dev, "AC108 PLL freq_in match:%u, freq_out:%u\n\n",
+								ac108_pll_div.freq_in, ac108_pll_div.freq_out);
+				break;
+			}
+		}
+		/* 0x11,0x12,0x13,0x14: Config PLL DIV param M1/M2/N/K1/K2 */
+		ac108_multi_update_bits(PLL_CTRL5, 0x1f << PLL_POSTDIV1 | 0x01 << PLL_POSTDIV2,
+						   ac108_pll_div.k1 << PLL_POSTDIV1 | ac108_pll_div.k2 << PLL_POSTDIV2, ac10x);
+		ac108_multi_update_bits(PLL_CTRL4, 0xff << PLL_LOOPDIV_LSB, (unsigned char)ac108_pll_div.n << PLL_LOOPDIV_LSB, ac10x);
+		ac108_multi_update_bits(PLL_CTRL3, 0x03 << PLL_LOOPDIV_MSB, (ac108_pll_div.n >> 8) << PLL_LOOPDIV_MSB, ac10x);
+		ac108_multi_update_bits(PLL_CTRL2, 0x1f << PLL_PREDIV1 | 0x01 << PLL_PREDIV2,
+						    ac108_pll_div.m1 << PLL_PREDIV1 | ac108_pll_div.m2 << PLL_PREDIV2, ac10x);
+
+		/*0x18: PLL clk lock enable*/
+		ac108_multi_update_bits(PLL_LOCK_CTRL, 0x1 << PLL_LOCK_EN, 0x1 << PLL_LOCK_EN, ac10x);
+
+		/**
+		 * 0x20: enable pll, pll source from mclk/bclk, sysclk source from pll, enable sysclk
+		 */
+		ac108_multi_update_bits(SYSCLK_CTRL, 0x01 << PLLCLK_EN | 0x03  << PLLCLK_SRC | 0x01 << SYSCLK_SRC | 0x01 << SYSCLK_EN,
+						     0x01 << PLLCLK_EN |pll_src<< PLLCLK_SRC | 0x01 << SYSCLK_SRC | 0x01 << SYSCLK_EN, ac10x);
+		ac10x->mclk = ac108_pll_div.freq_out;
+	}
+	if (ac10x->clk_id == SYSCLK_SRC_MCLK) {
+		/**
+		 *0x20: sysclk source from mclk, enable sysclk
+		 */
+		ac108_multi_update_bits(SYSCLK_CTRL, 0x01 << PLLCLK_EN | 0x01 << SYSCLK_SRC | 0x01 << SYSCLK_EN,
+						     0x00 << PLLCLK_EN | 0x00 << SYSCLK_SRC | 0x01 << SYSCLK_EN, ac10x);
+		ac10x->mclk = ac10x->sysclk;
+	}
+
+	return 0;
+}
+
+/*
+ * support no more than 16 slots.
+ */
+static int ac108_multi_chips_slots(struct ac10x_priv *ac, int slots) {
+	int i;
+
+	/*
+	 * codec0 enable slots 2,3,0,1 when 1 codec
+	 *
+	 * codec0 enable slots 6,7,0,1 when 2 codec
+	 * codec1 enable slots 2,3,4,5
+	 *
+	 * ...
+	 */
+	for (i = 0; i < ac->codec_cnt; i++) {
+		/* rotate map, due to channels rotated by CPU_DAI */
+		const unsigned vec_mask[] = {
+			0x3 << 6 | 0x3,	// slots 6,7,0,1
+			0xF << 2,	// slots 2,3,4,5
+			0,
+			0,
+		};
+		const unsigned vec_maps[] = {
+			/*
+			 * chip 0,
+			 * mic 0 sample -> slot 6
+			 * mic 1 sample -> slot 7
+			 * mic 2 sample -> slot 0
+			 * mic 3 sample -> slot 1
+			 */
+			0x0 << 12 | 0x1 << 14 | 0x2 << 0 | 0x3 << 2,
+			/*
+			 * chip 1,
+			 * mic 0 sample -> slot 2
+			 * mic 1 sample -> slot 3
+			 * mic 2 sample -> slot 4
+			 * mic 3 sample -> slot 5
+			 */
+			0x0 << 4  | 0x1 << 6  | 0x2 << 8 | 0x3 << 10,
+			0,
+			0,
+		};
+		unsigned vec;
+
+		/* 0x38-0x3A I2S_TX1_CTRLx */
+		if (ac->codec_cnt == 1) {
+			vec = 0xFUL;
+		} else {
+			vec = vec_mask[i];
+		}
+		ac10x_write(I2S_TX1_CTRL1, slots - 1, ac->i2cmap[i]);
+		ac10x_write(I2S_TX1_CTRL2, (vec >> 0) & 0xFF, ac->i2cmap[i]);
+		ac10x_write(I2S_TX1_CTRL3, (vec >> 8) & 0xFF, ac->i2cmap[i]);
+
+		/* 0x3C-0x3F I2S_TX1_CHMP_CTRLx */
+		if (ac->codec_cnt == 1) {
+			vec = (0x2 << 0 | 0x3 << 2 | 0x0 << 4 | 0x1 << 6);
+		} else if (ac->codec_cnt == 2) {
+			vec = vec_maps[i];
+		}
+
+		ac10x_write(I2S_TX1_CHMP_CTRL1, (vec >>  0) & 0xFF, ac->i2cmap[i]);
+		ac10x_write(I2S_TX1_CHMP_CTRL2, (vec >>  8) & 0xFF, ac->i2cmap[i]);
+		ac10x_write(I2S_TX1_CHMP_CTRL3, (vec >> 16) & 0xFF, ac->i2cmap[i]);
+		ac10x_write(I2S_TX1_CHMP_CTRL4, (vec >> 24) & 0xFF, ac->i2cmap[i]);
+	}
+	return 0;
+}
+
+static int ac108_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) {
+	unsigned int i, channels, samp_res, rate;
+	struct snd_soc_codec *codec = dai->codec;
+	struct ac10x_priv *ac10x = snd_soc_codec_get_drvdata(codec);
+	unsigned bclkdiv;
+	int ret = 0;
+	u8 v;
+
+	dev_dbg(dai->dev, "%s() stream=%s play:%d capt:%d +++\n", __func__,
+			snd_pcm_stream_str(substream),
+			dai->playback_active, dai->capture_active);
+
+	if (ac10x->i2c101) {
+		ret = ac101_hw_params(substream, params, dai);
+		if (ret > 0) {
+			dev_dbg(dai->dev, "%s() L%d returned\n", __func__, __LINE__);
+			/* not configure hw_param twice */
+			return 0;
+		}
+	}
+
+	if ((substream->stream == SNDRV_PCM_STREAM_CAPTURE && dai->playback_active)
+	 || (substream->stream == SNDRV_PCM_STREAM_PLAYBACK && dai->capture_active)) {
+		/* not configure hw_param twice */
+		/* return 0; */
+	}
+
+	channels = params_channels(params);
+
+	/* Master mode, to clear cpu_dai fifos, output bclk without lrck */
+	ac10x_read(I2S_CTRL, &v, ac10x->i2cmap[_MASTER_INDEX]);
+	if (v & (0x01 << BCLK_IOEN)) {
+		ac10x_update_bits(I2S_CTRL, 0x1 << LRCK_IOEN, 0x0 << LRCK_IOEN, ac10x->i2cmap[_MASTER_INDEX]);
+	}
+
+	switch (params_format(params)) {
+	case SNDRV_PCM_FORMAT_S8:
+		samp_res = 0;
+		break;
+	case SNDRV_PCM_FORMAT_S16_LE:
+		samp_res = 2;
+		break;
+	case SNDRV_PCM_FORMAT_S20_3LE:
+		samp_res = 3;
+		break;
+	case SNDRV_PCM_FORMAT_S24_LE:
+		samp_res = 4;
+		break;
+	case SNDRV_PCM_FORMAT_S32_LE:
+		samp_res = 6;
+		break;
+	default:
+		pr_err("AC108 don't supported the sample resolution: %u\n", params_format(params));
+		return -EINVAL;
+	}
+
+	for (i = 0; i < ARRAY_SIZE(ac108_sample_rate); i++) {
+		if (ac108_sample_rate[i].real_val == params_rate(params) / (ac10x->data_protocol + 1UL)) {
+			rate = i;
+			break;
+		}
+	}
+	if (i >= ARRAY_SIZE(ac108_sample_rate)) {
+		return -EINVAL;
+	}
+
+	if (channels == 8 && ac108_sample_rate[rate].real_val == 96000) {
+		/* 24.576M bit clock is not support by ac108 */
+		return -EINVAL;
+	}
+
+	dev_dbg(dai->dev, "rate: %d , channels: %d , samp_res: %d",
+			ac108_sample_rate[rate].real_val,
+			channels,
+			ac108_samp_res[samp_res].real_val);
+
+	/**
+	 * 0x33: 
+	 *  The 8-Low bit of LRCK period value. It is used to program
+	 *  the number of BCLKs per channel of sample frame. This value
+	 *  is interpreted as follow:
+	 *  The 8-Low bit of LRCK period value. It is used to program
+	 *  the number of BCLKs per channel of sample frame. This value
+	 *  is interpreted as follow: PCM mode: Number of BCLKs within
+	 *  (Left + Right) channel width I2S / Left-Justified /
+	 *  Right-Justified mode: Number of BCLKs within each individual
+	 *  channel width (Left or Right) N+1
+	 *  For example:
+	 *  n = 7: 8 BCLK width
+	 *  …
+	 *  n = 1023: 1024 BCLKs width
+	 *  0X32[0:1]:
+	 *  The 2-High bit of LRCK period value. 
+	 */
+	if (ac10x->i2s_mode != PCM_FORMAT) {
+		if (ac10x->data_protocol) {
+			ac108_multi_write(I2S_LRCK_CTRL2, ac108_samp_res[samp_res].real_val - 1, ac10x);
+			/*encoding mode, the max LRCK period value < 32,so the 2-High bit is zero*/
+			ac108_multi_update_bits(I2S_LRCK_CTRL1, 0x03 << 0, 0x00, ac10x);
+		} else {
+			/*TDM mode or normal mode*/
+			ac108_multi_update_bits(I2S_LRCK_CTRL1, 0x03 << 0, 0x00, ac10x);
+		}
+
+	} else {
+		unsigned div;
+
+		/*TDM mode or normal mode*/
+		div = ac108_samp_res[samp_res].real_val * channels - 1;
+		ac108_multi_write(I2S_LRCK_CTRL2, (div & 0xFF), ac10x);
+		ac108_multi_update_bits(I2S_LRCK_CTRL1, 0x03 << 0, (div >> 8) << 0, ac10x);
+	}
+
+	/**
+	 * 0x35: 
+	 * TX Encoding mode will add  4bits to mark channel number 
+	 * TODO: need a chat to explain this 
+	 */
+	ac108_multi_update_bits(I2S_FMT_CTRL2, 0x07 << SAMPLE_RESOLUTION | 0x07 << SLOT_WIDTH_SEL,
+						ac108_samp_res[samp_res].reg_val << SAMPLE_RESOLUTION
+ 						  | ac108_samp_res[samp_res].reg_val << SLOT_WIDTH_SEL, ac10x);
+
+	/**
+	 * 0x60: 
+	 * ADC Sample Rate synchronised with I2S1 clock zone 
+	 */
+	ac108_multi_update_bits(ADC_SPRC, 0x0f << ADC_FS_I2S1, ac108_sample_rate[rate].reg_val << ADC_FS_I2S1, ac10x);
+	ac108_multi_write(HPF_EN, 0x0F, ac10x);
+
+	if (ac10x->i2c101 && _MASTER_MULTI_CODEC == _MASTER_AC101) {
+		ac108_config_pll(ac10x, ac108_sample_rate[rate].real_val, ac108_samp_res[samp_res].real_val * channels);
+	} else {
+		ac108_config_pll(ac10x, ac108_sample_rate[rate].real_val, 0);
+	}
+
+	/*
+	 * master mode only
+	 */
+	bclkdiv = ac10x->mclk / (ac108_sample_rate[rate].real_val * channels * ac108_samp_res[samp_res].real_val);
+	for (i = 0; i < ARRAY_SIZE(ac108_bclkdivs) - 1; i++) {
+		if (ac108_bclkdivs[i] >= bclkdiv) {
+			break;
+		}
+	}
+	ac108_multi_update_bits(I2S_BCLK_CTRL, 0x0F << BCLKDIV, i << BCLKDIV, ac10x);
+
+	/*
+	 * slots allocation for each chip
+	 */
+	ac108_multi_chips_slots(ac10x, channels);
+
+	/*0x21: Module clock enable<I2S, ADC digital, MIC offset Calibration, ADC analog>*/
+	ac108_multi_write(MOD_CLK_EN, 1 << I2S | 1 << ADC_DIGITAL | 1 << MIC_OFFSET_CALIBRATION | 1 << ADC_ANALOG, ac10x);
+	/*0x22: Module reset de-asserted<I2S, ADC digital, MIC offset Calibration, ADC analog>*/
+	ac108_multi_write(MOD_RST_CTRL, 1 << I2S | 1 << ADC_DIGITAL | 1 << MIC_OFFSET_CALIBRATION | 1 << ADC_ANALOG, ac10x);
+
+
+	dev_dbg(dai->dev, "%s() stream=%s ---\n", __func__,
+			snd_pcm_stream_str(substream));
+
+	return 0;
+}
+
+static int ac108_set_sysclk(struct snd_soc_dai *dai, int clk_id, unsigned int freq, int dir) {
+
+	struct ac10x_priv *ac10x = snd_soc_dai_get_drvdata(dai);
+
+	freq = 24000000;
+	clk_id = SYSCLK_SRC_PLL;
+
+	pr_info("%s  :%d\n", __FUNCTION__, freq);
+
+	switch (clk_id) {
+	case SYSCLK_SRC_MCLK:
+		ac108_multi_update_bits(SYSCLK_CTRL, 0x1 << SYSCLK_SRC, SYSCLK_SRC_MCLK << SYSCLK_SRC, ac10x);
+		break;
+	case SYSCLK_SRC_PLL:
+		ac108_multi_update_bits(SYSCLK_CTRL, 0x1 << SYSCLK_SRC, SYSCLK_SRC_PLL << SYSCLK_SRC, ac10x);
+		break;
+	default:
+		return -EINVAL;
+	}
+	ac10x->sysclk = freq;
+	ac10x->clk_id = clk_id;
+
+	return 0;
+}
+
+/**
+ *  The i2s format management related registers are Reg
+ *  30h~Reg36h
+ *  33h,35h will be set in ac108_hw_params, It's BCLK width and
+ *  Sample Resolution.
+ * @author baozhu (17-6-20)
+ * 
+ * @param dai 
+ * @param fmt 
+ * 
+ * @return int 
+ */
+static int ac108_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) {
+	unsigned char tx_offset, lrck_polarity, brck_polarity;
+	struct ac10x_priv *ac10x = dev_get_drvdata(dai->dev);
+
+	dev_dbg(dai->dev, "%s\n", __FUNCTION__);
+
+	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
+	case SND_SOC_DAIFMT_CBM_CFM:    /*AC108 Master*/
+		if (! ac10x->i2c101 || _MASTER_MULTI_CODEC == _MASTER_AC108) {
+			dev_dbg(dai->dev, "AC108 set to work as Master\n");
+			/**
+			 * 0x30:chip is master mode ,BCLK & LRCK output
+			 */
+			ac108_multi_update_bits(I2S_CTRL, 0x03 << LRCK_IOEN | 0x03 << SDO1_EN | 0x1 << TXEN | 0x1 << GEN,
+							  0x00 << LRCK_IOEN | 0x03 << SDO1_EN | 0x1 << TXEN | 0x1 << GEN, ac10x);
+			/* multi_chips: only one chip set as Master, and the others also need to set as Slave */
+			ac10x_update_bits(I2S_CTRL, 0x3 << LRCK_IOEN, 0x01 << BCLK_IOEN, ac10x->i2cmap[_MASTER_INDEX]);
+			break;
+		} else {
+			/* TODO: Both cpu_dai and codec_dai(AC108) be set as slave in DTS */
+			dev_dbg(dai->dev, "used as slave when AC101 is master\n");
+		}
+	case SND_SOC_DAIFMT_CBS_CFS:    /*AC108 Slave*/
+		dev_dbg(dai->dev, "AC108 set to work as Slave\n");
+		/**
+		 * 0x30:chip is slave mode, BCLK & LRCK input,enable SDO1_EN and 
+		 *  SDO2_EN, Transmitter Block Enable, Globe Enable
+		 */
+		ac108_multi_update_bits(I2S_CTRL, 0x03 << LRCK_IOEN | 0x03 << SDO1_EN | 0x1 << TXEN | 0x1 << GEN,
+						  0x00 << LRCK_IOEN | 0x03 << SDO1_EN | 0x0 << TXEN | 0x0 << GEN, ac10x);
+		break;
+	default:
+		pr_err("AC108 Master/Slave mode config error:%u\n\n", (fmt & SND_SOC_DAIFMT_MASTER_MASK) >> 12);
+		return -EINVAL;
+	}
+
+	/*AC108 config I2S/LJ/RJ/PCM format*/
+	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
+	case SND_SOC_DAIFMT_I2S:
+		dev_dbg(dai->dev, "AC108 config I2S format\n");
+		ac10x->i2s_mode = LEFT_JUSTIFIED_FORMAT;
+		tx_offset = 1;
+		break;
+	case SND_SOC_DAIFMT_RIGHT_J:
+		dev_dbg(dai->dev, "AC108 config RIGHT-JUSTIFIED format\n");
+		ac10x->i2s_mode = RIGHT_JUSTIFIED_FORMAT;
+		tx_offset = 0;
+		break;
+	case SND_SOC_DAIFMT_LEFT_J:
+		dev_dbg(dai->dev, "AC108 config LEFT-JUSTIFIED format\n");
+		ac10x->i2s_mode = LEFT_JUSTIFIED_FORMAT;
+		tx_offset = 0;
+		break;
+	case SND_SOC_DAIFMT_DSP_A:
+		dev_dbg(dai->dev, "AC108 config PCM-A format\n");
+		ac10x->i2s_mode = PCM_FORMAT;
+		tx_offset = 1;
+		break;
+	case SND_SOC_DAIFMT_DSP_B:
+		dev_dbg(dai->dev, "AC108 config PCM-B format\n");
+		ac10x->i2s_mode = PCM_FORMAT;
+		tx_offset = 0;
+		break;
+	default:
+		pr_err("AC108 I2S format config error:%u\n\n", fmt & SND_SOC_DAIFMT_FORMAT_MASK);
+		return -EINVAL;
+	}
+
+	/*AC108 config BCLK&LRCK polarity*/
+	switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
+	case SND_SOC_DAIFMT_NB_NF:
+		dev_dbg(dai->dev, "AC108 config BCLK&LRCK polarity: BCLK_normal,LRCK_normal\n");
+		brck_polarity = BCLK_NORMAL_DRIVE_N_SAMPLE_P;
+		lrck_polarity = LRCK_LEFT_HIGH_RIGHT_LOW;
+		break;
+	case SND_SOC_DAIFMT_NB_IF:
+		dev_dbg(dai->dev, "AC108 config BCLK&LRCK polarity: BCLK_normal,LRCK_invert\n");
+		brck_polarity = BCLK_NORMAL_DRIVE_N_SAMPLE_P;
+		lrck_polarity = LRCK_LEFT_LOW_RIGHT_HIGH;
+		break;
+	case SND_SOC_DAIFMT_IB_NF:
+		dev_dbg(dai->dev, "AC108 config BCLK&LRCK polarity: BCLK_invert,LRCK_normal\n");
+		brck_polarity = BCLK_INVERT_DRIVE_P_SAMPLE_N;
+		lrck_polarity = LRCK_LEFT_HIGH_RIGHT_LOW;
+		break;
+	case SND_SOC_DAIFMT_IB_IF:
+		dev_dbg(dai->dev, "AC108 config BCLK&LRCK polarity: BCLK_invert,LRCK_invert\n");
+		brck_polarity = BCLK_INVERT_DRIVE_P_SAMPLE_N;
+		lrck_polarity = LRCK_LEFT_LOW_RIGHT_HIGH;
+		break;
+	default:
+		pr_err("AC108 config BCLK/LRCLK polarity error:%u\n\n", (fmt & SND_SOC_DAIFMT_INV_MASK) >> 8);
+		return -EINVAL;
+	}
+
+	ac108_configure_power(ac10x);
+
+	/**
+	 *0x31: 0: normal mode, negative edge drive and positive edge sample
+		1: invert mode, positive edge drive and negative edge sample
+	 */
+	ac108_multi_update_bits(I2S_BCLK_CTRL,  0x01 << BCLK_POLARITY, brck_polarity << BCLK_POLARITY, ac10x);
+	/**
+	 * 0x32: same as 0x31
+	 */
+	ac108_multi_update_bits(I2S_LRCK_CTRL1, 0x01 << LRCK_POLARITY, lrck_polarity << LRCK_POLARITY, ac10x);
+	/**
+	 * 0x34:Encoding Mode Selection,Mode 
+	 * Selection,data is offset by 1 BCLKs to LRCK 
+	 * normal mode for the last half cycle of BCLK in the slot ?
+	 * turn to hi-z state (TDM) when not transferring slot ?
+	 */
+	ac108_multi_update_bits(I2S_FMT_CTRL1,	0x01 << ENCD_SEL | 0x03 << MODE_SEL | 0x01 << TX2_OFFSET |
+						0x01 << TX1_OFFSET | 0x01 << TX_SLOT_HIZ | 0x01 << TX_STATE,
+								  ac10x->data_protocol << ENCD_SEL 	|
+								  ac10x->i2s_mode << MODE_SEL 		|
+								  tx_offset << TX2_OFFSET 			|
+								  tx_offset << TX1_OFFSET 			|
+								  0x00 << TX_SLOT_HIZ 				|
+								  0x01 << TX_STATE, ac10x);
+
+	/**
+	 * 0x60: 
+	 * MSB / LSB First Select: This driver only support MSB First Select . 
+	 * OUT2_MUTE,OUT1_MUTE shoule be set in widget. 
+	 * LRCK = 1 BCLK width 
+	 * Linear PCM 
+	 *  
+	 * TODO:pcm mode, bit[0:1] and bit[2] is special
+	 */
+	ac108_multi_update_bits(I2S_FMT_CTRL3,	0x01 << TX_MLS | 0x03 << SEXT  | 0x01 << LRCK_WIDTH | 0x03 << TX_PDM,
+						0x00 << TX_MLS | 0x03 << SEXT  | 0x00 << LRCK_WIDTH | 0x00 << TX_PDM, ac10x);
+
+	ac108_multi_write(HPF_EN, 0x00, ac10x);
+
+	if (ac10x->i2c101) {
+		return ac101_set_dai_fmt(dai, fmt);
+	}
+	return 0;
+}
+
+/*
+ * due to miss channels order in cpu_dai, we meed defer the clock starting.
+ */
+static int ac108_set_clock(int y_start_n_stop) {
+	u8 reg;
+	int ret = 0;
+
+	dev_dbg(ac10x->codec->dev, "%s() L%d cmd:%d\n", __func__, __LINE__, y_start_n_stop);
+
+	/* spin_lock move to machine trigger */
+
+	if (y_start_n_stop && ac10x->sysclk_en == 0) {
+		/* enable lrck clock */
+		ac10x_read(I2S_CTRL, &reg, ac10x->i2cmap[_MASTER_INDEX]);
+		if (reg & (0x01 << BCLK_IOEN)) {
+			ret = ret || ac10x_update_bits(I2S_CTRL, 0x03 << LRCK_IOEN, 0x03 << LRCK_IOEN, ac10x->i2cmap[_MASTER_INDEX]);
+		}
+
+		/*0x10: PLL Common voltage enable, PLL enable */
+		ret = ret || ac108_multi_update_bits(PLL_CTRL1, 0x01 << PLL_EN | 0x01 << PLL_COM_EN,
+						   0x01 << PLL_EN | 0x01 << PLL_COM_EN, ac10x);
+		/* enable global clock */
+		ret = ret || ac108_multi_update_bits(I2S_CTRL, 0x1 << TXEN | 0x1 << GEN, 0x1 << TXEN | 0x1 << GEN, ac10x);
+
+		ac10x->sysclk_en = 1UL;
+	} else if (!y_start_n_stop && ac10x->sysclk_en != 0) {
+		/* disable global clock */
+		ret = ret || ac108_multi_update_bits(I2S_CTRL, 0x1 << TXEN | 0x1 << GEN, 0x0 << TXEN | 0x0 << GEN, ac10x);
+
+		/*0x10: PLL Common voltage disable, PLL disable */
+		ret = ret || ac108_multi_update_bits(PLL_CTRL1, 0x01 << PLL_EN | 0x01 << PLL_COM_EN,
+						   0x00 << PLL_EN | 0x00 << PLL_COM_EN, ac10x);
+
+		/* disable lrck clock if it's enabled */
+		ac10x_read(I2S_CTRL, &reg, ac10x->i2cmap[_MASTER_INDEX]);
+		if (reg & (0x01 << LRCK_IOEN)) {
+			ret = ret || ac10x_update_bits(I2S_CTRL, 0x03 << LRCK_IOEN, 0x01 << BCLK_IOEN, ac10x->i2cmap[_MASTER_INDEX]);
+		}
+		if (!ret) {
+			ac10x->sysclk_en = 0UL;
+		}
+	}
+
+	return ret;
+}
+
+static int ac108_prepare(struct snd_pcm_substream *substream,
+					struct snd_soc_dai *dai)
+{
+	dev_dbg(dai->dev, "%s() stream=%s\n",
+		__func__,
+		snd_pcm_stream_str(substream));
+	
+	return 0;
+}
+
+static int ac108_trigger(struct snd_pcm_substream *substream, int cmd,
+			     struct snd_soc_dai *dai)
+{
+	struct snd_soc_codec *codec = dai->codec;
+	struct ac10x_priv *ac10x = snd_soc_codec_get_drvdata(codec);
+	unsigned long flags;
+	int ret = 0;
+	u8 r;
+
+	dev_dbg(dai->dev, "%s() stream=%s  cmd=%d\n",
+		__FUNCTION__,
+		snd_pcm_stream_str(substream),
+		cmd);
+
+	spin_lock_irqsave(&ac10x->lock, flags);
+
+	if (ac10x->i2c101 && _MASTER_MULTI_CODEC == _MASTER_AC101) {
+		ac101_trigger(substream, cmd, dai);
+		if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+		       goto __ret;
+		}
+	}
+
+	switch (cmd) {
+	case SNDRV_PCM_TRIGGER_START:
+	case SNDRV_PCM_TRIGGER_RESUME:
+	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
+		/* disable global clock if lrck disabled */
+		ac10x_read(I2S_CTRL, &r, ac10x->i2cmap[_MASTER_INDEX]);
+		if ((r & (0x01 << BCLK_IOEN)) && (r & (0x01 << LRCK_IOEN)) == 0) {
+			/* disable global clock */
+			ac108_multi_update_bits(I2S_CTRL, 0x1 << TXEN | 0x1 << GEN, 0x0 << TXEN | 0x0 << GEN, ac10x);
+		}
+
+		/* delayed clock starting, move to machine trigger() */
+		break;
+	case SNDRV_PCM_TRIGGER_STOP:
+	case SNDRV_PCM_TRIGGER_SUSPEND:
+	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
+		break;
+	default:
+		ret = -EINVAL;
+	}
+
+__ret:
+	spin_unlock_irqrestore(&ac10x->lock, flags);
+
+	return ret;
+}
+
+int ac108_audio_startup(struct snd_pcm_substream *substream,
+	struct snd_soc_dai *dai
+) {
+	struct snd_soc_codec *codec = dai->codec;
+	struct ac10x_priv *ac10x = snd_soc_codec_get_drvdata(codec);
+
+	if (ac10x->i2c101) {
+		return ac101_audio_startup(substream, dai);
+	}
+	return 0;
+}
+
+void ac108_aif_shutdown(struct snd_pcm_substream *substream,
+	struct snd_soc_dai *dai
+) {
+	struct snd_soc_codec *codec = dai->codec;
+	struct ac10x_priv *ac10x = snd_soc_codec_get_drvdata(codec);
+
+	if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
+		/*0x21: Module clock disable <I2S, ADC digital, MIC offset Calibration, ADC analog>*/
+		ac108_multi_write(MOD_CLK_EN, 0x0, ac10x);
+		/*0x22: Module reset asserted <I2S, ADC digital, MIC offset Calibration, ADC analog>*/
+		ac108_multi_write(MOD_RST_CTRL, 0x0, ac10x);
+	}
+
+	if (ac10x->i2c101) {
+		ac101_aif_shutdown(substream, dai);
+	}
+}
+
+int ac108_aif_mute(struct snd_soc_dai *dai, int mute) {
+	struct snd_soc_codec *codec = dai->codec;
+	struct ac10x_priv *ac10x = snd_soc_codec_get_drvdata(codec);
+
+	if (ac10x->i2c101) {
+		return ac101_aif_mute(dai, mute);
+	}
+	return 0;	
+}
+
+static const struct snd_soc_dai_ops ac108_dai_ops = {
+	.startup	= ac108_audio_startup,
+	.shutdown	= ac108_aif_shutdown,
+
+	/*DAI clocking configuration*/
+	.set_sysclk	= ac108_set_sysclk,
+
+	/*ALSA PCM audio operations*/
+	.hw_params	= ac108_hw_params,
+	.prepare	= ac108_prepare,
+	.trigger	= ac108_trigger,
+	.digital_mute	= ac108_aif_mute,
+
+	/*DAI format configuration*/
+	.set_fmt	= ac108_set_fmt,
+
+	// .hw_free = ac108_hw_free,
+};
+
+static  struct snd_soc_dai_driver ac108_dai0 = {
+	.name = "ac10x-codec0",
+	#if _USE_CAPTURE
+	.playback = {
+		.stream_name = "Playback",
+		.channels_min = 1,
+		.channels_max = AC108_CHANNELS_MAX,
+		.rates = AC108_RATES,
+		.formats = AC108_FORMATS,
+	},
+	#endif
+	.capture = {
+		.stream_name = "Capture",
+		.channels_min = 1,
+		.channels_max = AC108_CHANNELS_MAX,
+		.rates = AC108_RATES,
+		.formats = AC108_FORMATS,
+	},
+	.ops = &ac108_dai_ops,
+};
+
+static  struct snd_soc_dai_driver ac108_dai1 = {
+	.name = "ac10x-codec1",
+	#if _USE_CAPTURE
+	.playback = {
+		.stream_name = "Playback",
+		.channels_min = 1,
+		.channels_max = AC108_CHANNELS_MAX,
+		.rates = AC108_RATES,
+		.formats = AC108_FORMATS,
+	},
+	#endif
+	.capture = {
+		.stream_name = "Capture",
+		.channels_min = 1,
+		.channels_max = AC108_CHANNELS_MAX,
+		.rates = AC108_RATES,
+		.formats = AC108_FORMATS,
+	},
+	.ops = &ac108_dai_ops,
+};
+
+static  struct snd_soc_dai_driver *ac108_dai[] = {
+	&ac108_dai0,
+	&ac108_dai1,
+};
+
+static int ac108_add_widgets(struct snd_soc_codec *codec) {
+	struct ac10x_priv *ac10x = snd_soc_codec_get_drvdata(codec);
+	struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
+	const struct snd_kcontrol_new* snd_kcntl = ac108_snd_controls;
+	int ctrl_cnt = ARRAY_SIZE(ac108_snd_controls);
+
+	/* only register controls correspond to exist chips */
+	if (ac10x->tdm_chips_cnt >= 2) {
+		snd_kcntl = ac108tdm_snd_controls;
+		ctrl_cnt = ARRAY_SIZE(ac108tdm_snd_controls);
+	}
+	snd_soc_add_codec_controls(codec, snd_kcntl, ctrl_cnt);
+
+	snd_soc_dapm_new_controls(dapm, ac108_dapm_widgets,ARRAY_SIZE(ac108_dapm_widgets));
+	snd_soc_dapm_add_routes(dapm, ac108_dapm_routes, ARRAY_SIZE(ac108_dapm_routes));
+
+	return 0;
+}
+
+static int ac108_codec_probe(struct snd_soc_codec *codec) {
+	spin_lock_init(&ac10x->lock);
+
+	ac10x->codec = codec;
+	dev_set_drvdata(codec->dev, ac10x);
+	ac108_add_widgets(codec);
+
+	if (ac10x->i2c101) {
+		ac101_codec_probe(codec);
+	}
+
+	return 0;
+}
+
+static int ac108_set_bias_level(struct snd_soc_codec *codec, enum snd_soc_bias_level level) {
+	struct ac10x_priv *ac10x = snd_soc_codec_get_drvdata(codec);
+
+	dev_dbg(codec->dev, "AC108 level:%d\n", level);
+
+	switch (level) {
+	case SND_SOC_BIAS_ON:
+		ac108_multi_update_bits(ANA_ADC1_CTRL1, 0x01 << ADC1_MICBIAS_EN,  0x01 << ADC1_MICBIAS_EN, ac10x);
+		ac108_multi_update_bits(ANA_ADC2_CTRL1, 0x01 << ADC2_MICBIAS_EN,  0x01 << ADC2_MICBIAS_EN, ac10x);
+		ac108_multi_update_bits(ANA_ADC3_CTRL1, 0x01 << ADC3_MICBIAS_EN,  0x01 << ADC3_MICBIAS_EN, ac10x);
+		ac108_multi_update_bits(ANA_ADC4_CTRL1, 0x01 << ADC4_MICBIAS_EN,  0x01 << ADC4_MICBIAS_EN, ac10x);
+		break;
+
+	case SND_SOC_BIAS_PREPARE:
+		/* Put the MICBIASes into regulating mode */
+		break;
+
+	case SND_SOC_BIAS_STANDBY:
+		break;
+
+	case SND_SOC_BIAS_OFF:
+		ac108_multi_update_bits(ANA_ADC1_CTRL1, 0x01 << ADC1_MICBIAS_EN,  0x00 << ADC1_MICBIAS_EN, ac10x);
+		ac108_multi_update_bits(ANA_ADC2_CTRL1, 0x01 << ADC2_MICBIAS_EN,  0x00 << ADC2_MICBIAS_EN, ac10x);
+		ac108_multi_update_bits(ANA_ADC3_CTRL1, 0x01 << ADC3_MICBIAS_EN,  0x00 << ADC3_MICBIAS_EN, ac10x);
+		ac108_multi_update_bits(ANA_ADC4_CTRL1, 0x01 << ADC4_MICBIAS_EN,  0x00 << ADC4_MICBIAS_EN, ac10x);
+		break;
+	}
+
+	if (ac10x->i2c101) {
+		ac101_set_bias_level(codec, level);
+	}
+	return 0;
+}
+
+int ac108_codec_remove(struct snd_soc_codec *codec) {
+	struct ac10x_priv *ac10x = snd_soc_codec_get_drvdata(codec);
+
+	if (! ac10x->i2c101) {
+		return 0;
+	}
+	return ac101_codec_remove(codec);
+}
+#if __NO_SND_SOC_CODEC_DRV
+void ac108_codec_remove_void(struct snd_soc_codec *codec) {
+	ac108_codec_remove(codec);
+}
+#define ac108_codec_remove ac108_codec_remove_void
+#endif
+
+int ac108_codec_suspend(struct snd_soc_codec *codec) {
+	struct ac10x_priv *ac10x = snd_soc_codec_get_drvdata(codec);
+	int i;
+
+	for (i = 0; i < ac10x->codec_cnt; i++) {
+		regcache_cache_only(ac10x->i2cmap[i], true);
+	}
+
+	if (! ac10x->i2c101) {
+		return 0;
+	}
+	return ac101_codec_suspend(codec);
+}
+
+int ac108_codec_resume(struct snd_soc_codec *codec) {
+	struct ac10x_priv *ac10x = snd_soc_codec_get_drvdata(codec);
+	int i, ret;
+
+	/* Sync reg_cache with the hardware */
+	for (i = 0; i < ac10x->codec_cnt; i++) {
+		regcache_cache_only(ac10x->i2cmap[i], false);
+		ret = regcache_sync(ac10x->i2cmap[i]);
+		if (ret != 0) {
+			dev_err(codec->dev, "Failed to sync i2cmap%d register cache: %d\n", i, ret);
+			regcache_cache_only(ac10x->i2cmap[i], true);
+		}
+	}
+
+	if (! ac10x->i2c101) {
+		return 0;
+	}
+	return ac101_codec_resume(codec);
+}
+
+static struct snd_soc_codec_driver ac10x_soc_codec_driver = {
+	.probe 		= ac108_codec_probe,
+	.remove 	= ac108_codec_remove,
+	.suspend 	= ac108_codec_suspend,
+	.resume 	= ac108_codec_resume,
+	.set_bias_level = ac108_set_bias_level,
+	.read		= ac108_codec_read,
+	.write		= ac108_codec_write,
+};
+
+static ssize_t ac108_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) {
+	int val = 0, flag = 0;
+	u8 i = 0, reg, num, value_w, value_r[4];
+
+	val = simple_strtol(buf, NULL, 16);
+	flag = (val >> 16) & 0xF;
+
+	if (flag) {
+		reg = (val >> 8) & 0xFF;
+		value_w = val & 0xFF;
+		ac108_multi_write(reg, value_w, ac10x);
+		printk("Write 0x%02x to REG:0x%02x\n", value_w, reg);
+	} else {
+		int k;
+
+		reg = (val >> 8) & 0xFF;
+		num = val & 0xff;
+		printk("\nRead: start REG:0x%02x,count:0x%02x\n", reg, num);
+
+		for (k = 0; k < ac10x->codec_cnt; k++) {
+			regcache_cache_bypass(ac10x->i2cmap[k], true);
+		}
+		do {
+
+			memset(value_r, 0, sizeof value_r);
+
+			for (k = 0; k < ac10x->codec_cnt; k++) {
+				ac10x_read(reg, &value_r[k], ac10x->i2cmap[k]);
+			}
+			if (ac10x->codec_cnt >= 2) {
+				printk("REG[0x%02x]: 0x%02x 0x%02x", reg, value_r[0], value_r[1]);
+			} else {
+				printk("REG[0x%02x]: 0x%02x", reg, value_r[0]);
+			}
+			reg++;
+
+			if ((++i == num) || (i % 4 == 0)) {
+				printk("\n");
+			}
+		} while (i < num);
+		for (k = 0; k < ac10x->codec_cnt; k++) {
+			regcache_cache_bypass(ac10x->i2cmap[k], false);
+		}
+	}
+
+	return count;
+}
+
+static ssize_t ac108_show(struct device *dev, struct device_attribute *attr, char *buf) {
+#if 1
+	printk("echo flag|reg|val > ac108\n");
+	printk("eg read star addres=0x06,count 0x10:echo 0610 >ac108\n");
+	printk("eg write value:0xfe to address:0x06 :echo 106fe > ac108\n");
+	return 0;
+#else
+	return snprintf(buf, PAGE_SIZE,"echo flag|reg|val > ac108\n"
+					"eg read star addres=0x06,count 0x10:echo 0610 >ac108\n"
+					"eg write value:0xfe to address:0x06 :echo 106fe > ac108\n");
+#endif
+}
+
+static DEVICE_ATTR(ac108, 0644, ac108_show, ac108_store);
+static struct attribute *ac108_debug_attrs[] = {
+	&dev_attr_ac108.attr,
+	NULL,
+};
+static struct attribute_group ac108_debug_attr_group = {
+	.name   = "ac108_debug",
+	.attrs  = ac108_debug_attrs,
+};
+
+static const struct regmap_config ac108_regmap = {
+	.reg_bits = 8,
+	.val_bits = 8,
+	.reg_stride = 1,
+	.max_register = 0xDF,
+	.cache_type = REGCACHE_FLAT,
+};
+static int ac108_i2c_probe(struct i2c_client *i2c, const struct i2c_device_id *i2c_id) {
+	struct device_node *np = i2c->dev.of_node;
+	unsigned int val = 0;
+	int ret = 0, index;
+
+	if (ac10x == NULL) {
+		ac10x = kzalloc(sizeof(struct ac10x_priv), GFP_KERNEL);
+		if (ac10x == NULL) {
+			dev_err(&i2c->dev, "Unable to allocate ac10x private data\n");
+			return -ENOMEM;
+		}
+	}
+
+	index = (int)i2c_id->driver_data;
+	if (index == AC101_I2C_ID) {
+		ac10x->i2c101 = i2c;
+		i2c_set_clientdata(i2c, ac10x);
+		ret = ac101_probe(i2c, i2c_id);
+		if (ret) {
+			ac10x->i2c101 = NULL;
+			return ret;
+		}
+		goto __ret;
+	}
+
+	ret = of_property_read_u32(np, "data-protocol", &val);
+	if (ret) {
+		pr_err("Please set data-protocol.\n");
+		return -EINVAL;
+	}
+	ac10x->data_protocol = val;
+
+	if (of_property_read_u32(np, "tdm-chips-count", &val)) val = 1;
+	ac10x->tdm_chips_cnt = val;
+
+	pr_err(" ac10x i2c_id number: %d\n", index);
+	pr_err(" ac10x data protocol: %d\n", ac10x->data_protocol);
+
+	ac10x->i2c[index] = i2c;
+	ac10x->i2cmap[index] = devm_regmap_init_i2c(i2c, &ac108_regmap);
+	if (IS_ERR(ac10x->i2cmap[index])) {
+		ret = PTR_ERR(ac10x->i2cmap[index]);
+		dev_err(&i2c->dev, "Fail to initialize i2cmap%d I/O: %d\n", index, ret);
+		return ret;
+	}
+
+	/*
+	 * Writing this register with 0x12 
+	 * will resets all register to their default state.
+	 */
+	regcache_cache_only(ac10x->i2cmap[index], false);
+	ret = regmap_write(ac10x->i2cmap[index], CHIP_RST, CHIP_RST_VAL);
+	msleep(1);
+
+	/* sync regcache for FLAT type */
+	ac10x_fill_regcache(&i2c->dev, ac10x->i2cmap[index]);
+
+	ac10x->codec_cnt++;
+	pr_err(" ac10x codec count  : %d\n", ac10x->codec_cnt);
+
+	ret = sysfs_create_group(&i2c->dev.kobj, &ac108_debug_attr_group);
+	if (ret) {
+		pr_err("failed to create attr group\n");
+	}
+
+__ret:
+	/* It's time to bind codec to i2c[_MASTER_INDEX] when all i2c are ready */
+	if ((ac10x->codec_cnt != 0 && ac10x->tdm_chips_cnt < 2)
+	|| (ac10x->i2c[0] && ac10x->i2c[1] && ac10x->i2c101)) {
+		seeed_voice_card_register_set_clock(SNDRV_PCM_STREAM_CAPTURE, ac108_set_clock);
+		/* no playback stream */
+		if (! ac10x->i2c101) {
+			memset(&ac108_dai[_MASTER_INDEX]->playback, '\0', sizeof ac108_dai[_MASTER_INDEX]->playback);
+		}
+		ret = snd_soc_register_codec(&ac10x->i2c[_MASTER_INDEX]->dev, &ac10x_soc_codec_driver,
+						ac108_dai[_MASTER_INDEX], 1);
+		if (ret < 0) {
+			dev_err(&i2c->dev, "Failed to register ac10x codec: %d\n", ret);
+		}
+	}
+	return ret;
+}
+
+static int ac108_i2c_remove(struct i2c_client *i2c) {
+	if (ac10x->codec != NULL) {
+		snd_soc_unregister_codec(&ac10x->i2c[_MASTER_INDEX]->dev);
+		ac10x->codec = NULL;
+	}
+	if (i2c == ac10x->i2c101) {
+		ac101_remove(ac10x->i2c101);
+		ac10x->i2c101 = NULL;
+		goto __ret;
+	}
+
+	if (i2c == ac10x->i2c[0]) {
+		ac10x->i2c[0] = NULL;
+	}
+	if (i2c == ac10x->i2c[1]) {
+		ac10x->i2c[1] = NULL;
+	}
+
+	sysfs_remove_group(&i2c->dev.kobj, &ac108_debug_attr_group);
+
+__ret:
+	if (!ac10x->i2c[0] && !ac10x->i2c[1] && !ac10x->i2c101) {
+		kfree(ac10x);
+		ac10x = NULL;
+	}
+	return 0;
+}
+
+static const struct i2c_device_id ac108_i2c_id[] = {
+	{ "ac108_0", 0 },
+	{ "ac108_1", 1 },
+	{ "ac108_2", 2 },
+	{ "ac108_3", 3 },
+	{ "ac101", AC101_I2C_ID },
+	{ }
+};
+MODULE_DEVICE_TABLE(i2c, ac108_i2c_id);
+
+static const struct of_device_id ac108_of_match[] = {
+	{ .compatible = "x-power,ac108_0", },
+	{ .compatible = "x-power,ac108_1", },
+	{ .compatible = "x-power,ac108_2", },
+	{ .compatible = "x-power,ac108_3", },
+	{ .compatible = "x-power,ac101",   },
+	{ }
+};
+MODULE_DEVICE_TABLE(of, ac108_of_match);
+
+static struct i2c_driver ac108_i2c_driver = {
+	.driver = {
+		.name = "ac10x-codec",
+		.of_match_table = ac108_of_match,
+	},
+	.probe =    ac108_i2c_probe,
+	.remove =   ac108_i2c_remove,
+	.id_table = ac108_i2c_id,
+};
+
+module_i2c_driver(ac108_i2c_driver);
+
+MODULE_DESCRIPTION("ASoC AC108 driver");
+MODULE_AUTHOR("Baozhu Zuo<zuobaozhu@gmail.com>");
+MODULE_LICENSE("GPL");
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/seeed-voicecard/ac108.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/seeed-voicecard/ac108.h
new file mode 100644
index 0000000000000000000000000000000000000000..d40edfc485811690a1fdb1961213cbbb03a943e5
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/seeed-voicecard/ac108.h
@@ -0,0 +1,774 @@
+/*
+ * ac108.h --  ac108 ALSA Soc Audio driver
+ *
+ * Author: panjunwen
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef _AC108_H
+#define _AC108_H
+
+
+/*** AC108 Codec Register Define***/
+
+//Chip Reset
+#define CHIP_RST			0x00
+#define CHIP_RST_VAL		0x12
+
+//Power Control
+#define PWR_CTRL1			0x01
+#define PWR_CTRL2			0x02
+#define PWR_CTRL3			0x03
+#define PWR_CTRL4			0x04
+#define PWR_CTRL5			0x05
+#define PWR_CTRL6			0x06
+#define PWR_CTRL7			0x07
+#define PWR_CTRL8			0x08
+#define PWR_CTRL9			0x09
+
+//PLL Configure Control
+#define PLL_CTRL1			0x10
+#define PLL_CTRL2			0x11
+#define PLL_CTRL3			0x12
+#define PLL_CTRL4			0x13
+#define PLL_CTRL5			0x14
+#define PLL_CTRL6			0x16
+#define PLL_CTRL7			0x17
+#define PLL_LOCK_CTRL		0x18
+
+//System Clock Control
+#define SYSCLK_CTRL			0x20
+#define MOD_CLK_EN			0x21
+#define MOD_RST_CTRL		0x22
+#define DSM_CLK_CTRL		0x25
+
+//I2S Common Control
+#define I2S_CTRL			0x30
+#define I2S_BCLK_CTRL		0x31
+#define I2S_LRCK_CTRL1		0x32
+#define I2S_LRCK_CTRL2		0x33
+#define I2S_FMT_CTRL1		0x34
+#define I2S_FMT_CTRL2		0x35
+#define I2S_FMT_CTRL3		0x36
+
+//I2S TX1 Control
+#define I2S_TX1_CTRL1		0x38
+#define I2S_TX1_CTRL2		0x39
+#define I2S_TX1_CTRL3		0x3A
+#define I2S_TX1_CHMP_CTRL1	0x3C
+#define I2S_TX1_CHMP_CTRL2	0x3D
+#define I2S_TX1_CHMP_CTRL3	0x3E
+#define I2S_TX1_CHMP_CTRL4	0x3F
+
+//I2S TX2 Control
+#define I2S_TX2_CTRL1		0x40
+#define I2S_TX2_CTRL2		0x41
+#define I2S_TX2_CTRL3		0x42
+#define I2S_TX2_CHMP_CTRL1	0x44
+#define I2S_TX2_CHMP_CTRL2	0x45
+#define I2S_TX2_CHMP_CTRL3	0x46
+#define I2S_TX2_CHMP_CTRL4	0x47
+
+//I2S RX1 Control
+#define I2S_RX1_CTRL1		0x50
+#define I2S_RX1_CHMP_CTRL1	0x54
+#define I2S_RX1_CHMP_CTRL2	0x55
+#define I2S_RX1_CHMP_CTRL3	0x56
+#define I2S_RX1_CHMP_CTRL4	0x57
+
+//I2S Loopback Debug
+#define I2S_LPB_DEBUG		0x58
+
+//ADC Common Control
+#define ADC_SPRC			0x60
+#define ADC_DIG_EN			0x61
+#define DMIC_EN				0x62
+#define ADC_DSR				0x63
+#define ADC_FIR				0x64
+#define ADC_DDT_CTRL		0x65
+
+//HPF Control
+#define HPF_EN				0x66
+#define HPF_COEF_REGH1		0x67
+#define HPF_COEF_REGH2		0x68
+#define HPF_COEF_REGL1		0x69
+#define HPF_COEF_REGL2		0x6A
+#define HPF_GAIN_REGH1		0x6B
+#define HPF_GAIN_REGH2		0x6C
+#define HPF_GAIN_REGL1		0x6D
+#define HPF_GAIN_REGL2		0x6E
+
+//ADC Digital Channel Volume Control
+#define ADC1_DVOL_CTRL		0x70
+#define ADC2_DVOL_CTRL		0x71
+#define ADC3_DVOL_CTRL		0x72
+#define ADC4_DVOL_CTRL		0x73
+
+//ADC Digital Mixer Source and Gain Control
+#define ADC1_DMIX_SRC		0x76
+#define ADC2_DMIX_SRC		0x77
+#define ADC3_DMIX_SRC		0x78
+#define ADC4_DMIX_SRC		0x79
+
+//ADC Digital Debug Control
+#define ADC_DIG_DEBUG		0x7F
+
+//I2S Pad Drive Control
+#define I2S_DAT_PADDRV_CTRL	0x80
+#define I2S_CLK_PADDRV_CTRL	0x81
+
+//Analog PGA Control
+#define ANA_PGA1_CTRL		0x90
+#define ANA_PGA2_CTRL		0x91
+#define ANA_PGA3_CTRL		0x92
+#define ANA_PGA4_CTRL		0x93
+
+//MIC Offset Control
+#define MIC_OFFSET_CTRL1	0x96
+#define MIC_OFFSET_CTRL2	0x97
+#define MIC1_OFFSET_STATU1	0x98
+#define MIC1_OFFSET_STATU2	0x99
+#define MIC2_OFFSET_STATU1	0x9A
+#define MIC2_OFFSET_STATU2	0x9B
+#define MIC3_OFFSET_STATU1	0x9C
+#define MIC3_OFFSET_STATU2	0x9D
+#define MIC4_OFFSET_STATU1	0x9E
+#define MIC4_OFFSET_STATU2	0x9F
+
+//ADC1 Analog Control
+#define ANA_ADC1_CTRL1		0xA0
+#define ANA_ADC1_CTRL2		0xA1
+#define ANA_ADC1_CTRL3		0xA2
+#define ANA_ADC1_CTRL4		0xA3
+#define ANA_ADC1_CTRL5		0xA4
+#define ANA_ADC1_CTRL6		0xA5
+#define ANA_ADC1_CTRL7		0xA6
+
+//ADC2 Analog Control
+#define ANA_ADC2_CTRL1		0xA7
+#define ANA_ADC2_CTRL2		0xA8
+#define ANA_ADC2_CTRL3		0xA9
+#define ANA_ADC2_CTRL4		0xAA
+#define ANA_ADC2_CTRL5		0xAB
+#define ANA_ADC2_CTRL6		0xAC
+#define ANA_ADC2_CTRL7		0xAD
+
+//ADC3 Analog Control
+#define ANA_ADC3_CTRL1		0xAE
+#define ANA_ADC3_CTRL2		0xAF
+#define ANA_ADC3_CTRL3		0xB0
+#define ANA_ADC3_CTRL4		0xB1
+#define ANA_ADC3_CTRL5		0xB2
+#define ANA_ADC3_CTRL6		0xB3
+#define ANA_ADC3_CTRL7		0xB4
+
+//ADC4 Analog Control
+#define ANA_ADC4_CTRL1		0xB5
+#define ANA_ADC4_CTRL2		0xB6
+#define ANA_ADC4_CTRL3		0xB7
+#define ANA_ADC4_CTRL4		0xB8
+#define ANA_ADC4_CTRL5		0xB9
+#define ANA_ADC4_CTRL6		0xBA
+#define ANA_ADC4_CTRL7		0xBB
+
+//GPIO Configure
+#define GPIO_CFG1			0xC0
+#define GPIO_CFG2			0xC1
+#define GPIO_DAT			0xC2
+#define GPIO_DRV			0xC3
+#define GPIO_PULL			0xC4
+#define GPIO_INT_CFG		0xC5
+#define GPIO_INT_EN			0xC6
+#define GPIO_INT_STATUS		0xC7
+
+//Misc
+#define BGTC_DAT			0xD1
+#define BGVC_DAT			0xD2
+#define PRNG_CLK_CTRL		0xDF
+
+
+
+/*** AC108 Codec Register Bit Define***/
+
+/*PWR_CTRL1*/
+#define CP12_CTRL				4
+#define CP12_SENSE_SELECT		3
+
+/*PWR_CTRL2*/
+#define CP12_SENSE_FILT			6
+#define CP12_COMP_FF_EN			3
+#define CP12_FORCE_ENABLE		2
+#define CP12_FORCE_RSTB			1
+
+/*PWR_CTRL3*/
+#define LDO33DIG_CTRL			0
+
+/*PWR_CTRL6*/
+#define LDO33ANA_2XHDRM			2
+#define LDO33ANA_ENABLE			0
+
+/*PWR_CTRL7*/
+#define VREF_SEL				3
+#define VREF_FASTSTART_ENABLE	1
+#define VREF_ENABLE				0
+
+/*PWR_CTRL9*/
+#define VREFP_FASTSTART_ENABLE	7
+#define VREFP_RESCTRL			5
+#define VREFP_LPMODE			4
+#define IGEN_TRIM				1
+#define VREFP_ENABLE			0
+
+
+/*PLL_CTRL1*/
+#define PLL_IBIAS				4
+#define PLL_NDET				3
+#define PLL_LOCKED_STATUS		2
+#define PLL_COM_EN				1
+#define PLL_EN					0
+
+/*PLL_CTRL2*/
+#define PLL_PREDIV2				5
+#define PLL_PREDIV1				0
+
+/*PLL_CTRL3*/
+#define PLL_LOOPDIV_MSB			0
+
+/*PLL_CTRL4*/
+#define PLL_LOOPDIV_LSB			0
+
+/*PLL_CTRL5*/
+#define PLL_POSTDIV2			5
+#define PLL_POSTDIV1			0
+
+/*PLL_CTRL6*/
+#define PLL_LDO					6
+#define PLL_CP					0
+
+/*PLL_CTRL7*/
+#define PLL_CAP					6
+#define PLL_RES					4
+#define PLL_TEST_EN				0
+
+/*PLL_LOCK_CTRL*/
+#define LOCK_LEVEL1				2
+#define LOCK_LEVEL2				1
+#define PLL_LOCK_EN				0
+
+
+/*SYSCLK_CTRL*/
+#define PLLCLK_EN				7
+#define PLLCLK_SRC				4
+#define SYSCLK_SRC				3
+#define SYSCLK_EN				0
+
+/*MOD_CLK_EN & MOD_RST_CTRL*/
+#define I2S						7
+#define ADC_DIGITAL				4
+#define MIC_OFFSET_CALIBRATION	1
+#define ADC_ANALOG				0
+
+/*DSM_CLK_CTRL*/
+#define MIC_OFFSET_DIV			4
+#define DSM_CLK_SEL				0
+
+
+/*I2S_CTRL*/
+#define BCLK_IOEN				7
+#define LRCK_IOEN				6
+#define SDO2_EN					5
+#define SDO1_EN					4
+#define TXEN					2
+#define RXEN					1
+#define GEN						0
+
+/*I2S_BCLK_CTRL*/
+#define EDGE_TRANSFER			5
+#define BCLK_POLARITY			4
+#define BCLKDIV					0
+
+/*I2S_LRCK_CTRL1*/
+#define LRCK_POLARITY			4
+#define LRCK_PERIODH			0
+
+/*I2S_LRCK_CTRL2*/
+#define LRCK_PERIODL			0
+
+/*I2S_FMT_CTRL1*/
+#define ENCD_SEL				6
+#define MODE_SEL				4
+#define TX2_OFFSET				3
+#define TX1_OFFSET				2
+#define TX_SLOT_HIZ				1
+#define TX_STATE				0
+
+/*I2S_FMT_CTRL2*/
+#define SLOT_WIDTH_SEL			4
+#define SAMPLE_RESOLUTION		0
+
+/*I2S_FMT_CTRL3*/
+#define TX_MLS					7
+#define SEXT					5
+#define OUT2_MUTE				4
+#define OUT1_MUTE				3
+#define LRCK_WIDTH				2
+#define TX_PDM					0
+
+
+/*I2S_TX1_CTRL1*/
+#define TX1_CHSEL				0
+
+/*I2S_TX1_CTRL2*/
+#define TX1_CH8_EN				7
+#define TX1_CH7_EN				6
+#define TX1_CH6_EN				5
+#define TX1_CH5_EN				4
+#define TX1_CH4_EN				3
+#define TX1_CH3_EN				2
+#define TX1_CH2_EN				1
+#define TX1_CH1_EN				0
+
+/*I2S_TX1_CTRL3*/
+#define TX1_CH16_EN				7
+#define TX1_CH15_EN				6
+#define TX1_CH14_EN				5
+#define TX1_CH13_EN				4
+#define TX1_CH12_EN				3
+#define TX1_CH11_EN				2
+#define TX1_CH10_EN				1
+#define TX1_CH9_EN				0
+
+/*I2S_TX1_CHMP_CTRL1*/
+#define TX1_CH4_MAP				6
+#define TX1_CH3_MAP				4
+#define TX1_CH2_MAP				2
+#define TX1_CH1_MAP				0
+
+/*I2S_TX1_CHMP_CTRL2*/
+#define TX1_CH8_MAP				6
+#define TX1_CH7_MAP				4
+#define TX1_CH6_MAP				2
+#define TX1_CH5_MAP				0
+
+/*I2S_TX1_CHMP_CTRL3*/
+#define TX1_CH12_MAP			6
+#define TX1_CH11_MAP			4
+#define TX1_CH10_MAP			2
+#define TX1_CH9_MAP				0
+
+/*I2S_TX1_CHMP_CTRL4*/
+#define TX1_CH16_MAP			6
+#define TX1_CH15_MAP			4
+#define TX1_CH14_MAP			2
+#define TX1_CH13_MAP			0
+
+
+/*I2S_TX2_CTRL1*/
+#define TX2_CHSEL				0
+
+/*I2S_TX2_CHMP_CTRL1*/
+#define TX2_CH4_MAP				6
+#define TX2_CH3_MAP				4
+#define TX2_CH2_MAP				2
+#define TX2_CH1_MAP				0
+
+/*I2S_TX2_CHMP_CTRL2*/
+#define TX2_CH8_MAP				6
+#define TX2_CH7_MAP				4
+#define TX2_CH6_MAP				2
+#define TX2_CH5_MAP				0
+
+/*I2S_TX2_CHMP_CTRL3*/
+#define TX2_CH12_MAP			6
+#define TX2_CH11_MAP			4
+#define TX2_CH10_MAP			2
+#define TX2_CH9_MAP				0
+
+/*I2S_TX2_CHMP_CTRL4*/
+#define TX2_CH16_MAP			6
+#define TX2_CH15_MAP			4
+#define TX2_CH14_MAP			2
+#define TX2_CH13_MAP			0
+
+
+/*I2S_RX1_CTRL1*/
+#define RX1_CHSEL				0
+
+/*I2S_RX1_CHMP_CTRL1*/
+#define RX1_CH4_MAP				6
+#define RX1_CH3_MAP				4
+#define RX1_CH2_MAP				2
+#define RX1_CH1_MAP				0
+
+/*I2S_RX1_CHMP_CTRL2*/
+#define RX1_CH8_MAP				6
+#define RX1_CH7_MAP				4
+#define RX1_CH6_MAP				2
+#define RX1_CH5_MAP				0
+
+/*I2S_RX1_CHMP_CTRL3*/
+#define RX1_CH12_MAP			6
+#define RX1_CH11_MAP			4
+#define RX1_CH10_MAP			2
+#define RX1_CH9_MAP				0
+
+/*I2S_RX1_CHMP_CTRL4*/
+#define RX1_CH16_MAP			6
+#define RX1_CH15_MAP			4
+#define RX1_CH14_MAP			2
+#define RX1_CH13_MAP			0
+
+
+/*I2S_LPB_DEBUG*/
+#define I2S_LPB_DEBUG_EN		0
+
+
+/*ADC_SPRC*/
+#define ADC_FS_I2S1				0
+
+/*ADC_DIG_EN*/
+#define DG_EN					4
+#define ENAD4					3
+#define ENAD3					2
+#define ENAD2					1
+#define ENAD1					0
+
+/*DMIC_EN*/
+#define DMIC2_EN				1
+#define DMIC1_EN				0
+
+/*ADC_DSR*/
+#define DIG_ADC4_SRS			6
+#define DIG_ADC3_SRS			4
+#define DIG_ADC2_SRS			2
+#define DIG_ADC1_SRS			0
+
+/*ADC_DDT_CTRL*/
+#define ADOUT_DLY_EN			2
+#define ADOUT_DTS				0
+
+
+/*HPF_EN*/
+#define DIG_ADC4_HPF_EN			3
+#define DIG_ADC3_HPF_EN			2
+#define DIG_ADC2_HPF_EN			1
+#define DIG_ADC1_HPF_EN			0
+
+
+/*ADC1_DMIX_SRC*/
+#define ADC1_ADC4_DMXL_GC		7
+#define ADC1_ADC3_DMXL_GC		6
+#define ADC1_ADC2_DMXL_GC		5
+#define ADC1_ADC1_DMXL_GC		4
+#define ADC1_ADC4_DMXL_SRC		3
+#define ADC1_ADC3_DMXL_SRC		2
+#define ADC1_ADC2_DMXL_SRC		1
+#define ADC1_ADC1_DMXL_SRC		0
+
+/*ADC2_DMIX_SRC*/
+#define ADC2_ADC4_DMXL_GC		7
+#define ADC2_ADC3_DMXL_GC		6
+#define ADC2_ADC2_DMXL_GC		5
+#define ADC2_ADC1_DMXL_GC		4
+#define ADC2_ADC4_DMXL_SRC		3
+#define ADC2_ADC3_DMXL_SRC		2
+#define ADC2_ADC2_DMXL_SRC		1
+#define ADC2_ADC1_DMXL_SRC		0
+
+/*ADC3_DMIX_SRC*/
+#define ADC3_ADC4_DMXL_GC		7
+#define ADC3_ADC3_DMXL_GC		6
+#define ADC3_ADC2_DMXL_GC		5
+#define ADC3_ADC1_DMXL_GC		4
+#define ADC3_ADC4_DMXL_SRC		3
+#define ADC3_ADC3_DMXL_SRC		2
+#define ADC3_ADC2_DMXL_SRC		1
+#define ADC3_ADC1_DMXL_SRC		0
+
+/*ADC4_DMIX_SRC*/
+#define ADC4_ADC4_DMXL_GC		7
+#define ADC4_ADC3_DMXL_GC		6
+#define ADC4_ADC2_DMXL_GC		5
+#define ADC4_ADC1_DMXL_GC		4
+#define ADC4_ADC4_DMXL_SRC		3
+#define ADC4_ADC3_DMXL_SRC		2
+#define ADC4_ADC2_DMXL_SRC		1
+#define ADC4_ADC1_DMXL_SRC		0
+
+
+/*ADC_DIG_DEBUG*/
+#define ADC_PTN_SEL				0
+
+
+/*I2S_DAT_PADDRV_CTRL*/
+#define TX2_DAT_DRV				4
+#define TX1_DAT_DRV				0
+
+/*I2S_CLK_PADDRV_CTRL*/
+#define LRCK_DRV				4
+#define BCLK_DRV				0
+
+
+/*ANA_PGA1_CTRL*/
+#define ADC1_ANALOG_PGA			1
+#define ADC1_ANALOG_PGA_STEP	0
+
+/*ANA_PGA2_CTRL*/
+#define ADC2_ANALOG_PGA			1
+#define ADC2_ANALOG_PGA_STEP	0
+
+/*ANA_PGA3_CTRL*/
+#define ADC3_ANALOG_PGA			1
+#define ADC3_ANALOG_PGA_STEP	0
+
+/*ANA_PGA4_CTRL*/
+#define ADC4_ANALOG_PGA			1
+#define ADC4_ANALOG_PGA_STEP	0
+
+
+/*MIC_OFFSET_CTRL1*/
+#define MIC_OFFSET_CAL_EN4		3
+#define MIC_OFFSET_CAL_EN3		2
+#define MIC_OFFSET_CAL_EN2		1
+#define MIC_OFFSET_CAL_EN1		0
+
+/*MIC_OFFSET_CTRL2*/
+#define MIC_OFFSET_CAL_GAIN		3
+#define MIC_OFFSET_CAL_CHANNEL	1
+#define MIC_OFFSET_CAL_EN_ONCE	0
+
+/*MIC1_OFFSET_STATU1*/
+#define MIC1_OFFSET_CAL_DONE	7
+#define MIC1_OFFSET_CAL_RUN_STA	6
+#define MIC1_OFFSET_MSB			0
+
+/*MIC1_OFFSET_STATU2*/
+#define MIC1_OFFSET_LSB			0
+
+/*MIC2_OFFSET_STATU1*/
+#define MIC2_OFFSET_CAL_DONE	7
+#define MIC2_OFFSET_CAL_RUN_STA	6
+#define MIC2_OFFSET_MSB			0
+
+/*MIC2_OFFSET_STATU2*/
+#define MIC2_OFFSET_LSB			0
+
+/*MIC3_OFFSET_STATU1*/
+#define MIC3_OFFSET_CAL_DONE	7
+#define MIC3_OFFSET_CAL_RUN_STA	6
+#define MIC3_OFFSET_MSB			0
+
+/*MIC3_OFFSET_STATU2*/
+#define MIC3_OFFSET_LSB			0
+
+/*MIC4_OFFSET_STATU1*/
+#define MIC4_OFFSET_CAL_DONE	7
+#define MIC4_OFFSET_CAL_RUN_STA	6
+#define MIC4_OFFSET_MSB			0
+
+/*MIC4_OFFSET_STATU2*/
+#define MIC4_OFFSET_LSB			0
+
+
+/*ANA_ADC1_CTRL1*/
+#define ADC1_PGA_BYPASS			7
+#define ADC1_PGA_BYP_RCM		6
+#define ADC1_PGA_CTRL_RCM		4
+#define ADC1_PGA_MUTE			3
+#define ADC1_DSM_ENABLE			2
+#define ADC1_PGA_ENABLE			1
+#define ADC1_MICBIAS_EN			0
+
+/*ANA_ADC1_CTRL3*/
+#define ADC1_ANA_CAL_EN			5
+#define ADC1_SEL_OUT_EDGE		3
+#define ADC1_DSM_DISABLE		2
+#define ADC1_VREFP_DISABLE		1
+#define ADC1_AAF_DISABLE		0
+
+/*ANA_ADC1_CTRL6*/
+#define PGA_CTRL_TC				6
+#define PGA_CTRL_RC				4
+#define PGA_CTRL_I_LIN			2
+#define PGA_CTRL_I_IN			0
+
+/*ANA_ADC1_CTRL7*/
+#define PGA_CTRL_HI_Z			7
+#define PGA_CTRL_SHORT_RF		6
+#define PGA_CTRL_VCM_VG			4
+#define PGA_CTRL_VCM_IN			0
+
+
+/*ANA_ADC2_CTRL1*/
+#define ADC2_PGA_BYPASS			7
+#define ADC2_PGA_BYP_RCM		6
+#define ADC2_PGA_CTRL_RCM		4
+#define ADC2_PGA_MUTE			3
+#define ADC2_DSM_ENABLE			2
+#define ADC2_PGA_ENABLE			1
+#define ADC2_MICBIAS_EN			0
+
+/*ANA_ADC2_CTRL3*/
+#define ADC2_ANA_CAL_EN			5
+#define ADC2_SEL_OUT_EDGE		3
+#define ADC2_DSM_DISABLE		2
+#define ADC2_VREFP_DISABLE		1
+#define ADC2_AAF_DISABLE		0
+
+/*ANA_ADC2_CTRL6*/
+#define PGA_CTRL_IBOOST			7
+#define PGA_CTRL_IQCTRL			6
+#define PGA_CTRL_OABIAS			4
+#define PGA_CTRL_CMLP_DIS		3
+#define PGA_CTRL_PDB_RIN		2
+#define PGA_CTRL_PEAKDET		0
+
+/*ANA_ADC2_CTRL7*/
+#define AAF_LPMODE_EN			7
+#define AAF_STG2_IB_SEL			4
+#define AAFDSM_IB_DIV2			3
+#define AAF_STG1_IB_SEL			0
+
+
+/*ANA_ADC3_CTRL1*/
+#define ADC3_PGA_BYPASS			7
+#define ADC3_PGA_BYP_RCM		6
+#define ADC3_PGA_CTRL_RCM		4
+#define ADC3_PGA_MUTE			3
+#define ADC3_DSM_ENABLE			2
+#define ADC3_PGA_ENABLE			1
+#define ADC3_MICBIAS_EN			0
+
+/*ANA_ADC3_CTRL3*/
+#define ADC3_ANA_CAL_EN			5
+#define ADC3_INVERT_CLK			4
+#define ADC3_SEL_OUT_EDGE		3
+#define ADC3_DSM_DISABLE		2
+#define ADC3_VREFP_DISABLE		1
+#define ADC3_AAF_DISABLE		0
+
+/*ANA_ADC3_CTRL7*/
+#define DSM_COMP_IB_SEL			6
+#define DSM_OTA_CTRL			4
+#define DSM_LPMODE				3
+#define DSM_OTA_IB_SEL			0
+
+
+/*ANA_ADC4_CTRL1*/
+#define ADC4_PGA_BYPASS			7
+#define ADC4_PGA_BYP_RCM		6
+#define ADC4_PGA_CTRL_RCM		4
+#define ADC4_PGA_MUTE			3
+#define ADC4_DSM_ENABLE			2
+#define ADC4_PGA_ENABLE			1
+#define ADC4_MICBIAS_EN			0
+
+/*ANA_ADC4_CTRL3*/
+#define ADC4_ANA_CAL_EN			5
+#define ADC4_SEL_OUT_EDGE		3
+#define ADC4_DSM_DISABLE		2
+#define ADC4_VREFP_DISABLE		1
+#define ADC4_AAF_DISABLE		0
+
+/*ANA_ADC4_CTRL6*/
+#define DSM_DEMOFF				5
+#define DSM_EN_DITHER			4
+#define DSM_VREFP_LPMODE		2
+#define DSM_VREFP_OUTCTRL		0
+
+/*ANA_ADC4_CTRL7*/
+#define CK8M_EN					5
+#define OSC_EN					4
+#define ADC4_CLK_GATING			3
+#define ADC3_CLK_GATING			2
+#define ADC2_CLK_GATING			1
+#define ADC1_CLK_GATING			0
+
+
+/*GPIO_CFG1*/
+#define GPIO2_SELECT			4
+#define GPIO1_SELECT			0
+
+/*GPIO_CFG2*/
+#define GPIO4_SELECT			4
+#define GPIO3_SELECT			0
+
+/*GPIO_DAT*///order???
+#define GPIO4_DAT				3
+#define GPIO3_DAT				2
+#define GPIO2_DAT				1
+#define GPIO1_DAT				0
+
+/*GPIO_DRV*/
+#define GPIO4_DRV				6
+#define GPIO3_DRV				4
+#define GPIO2_DRV				2
+#define GPIO1_DRV				0
+
+/*GPIO_PULL*/
+#define GPIO4_PULL				6
+#define GPIO3_PULL				4
+#define GPIO2_PULL				2
+#define GPIO1_PULL				0
+
+/*GPIO_INT_CFG*/
+#define GPIO4_EINT_CFG			6
+#define GPIO3_EINT_CFG			4
+#define GPIO2_EINT_CFG			2
+#define GPIO1_EINT_CFG			0
+
+/*GPIO_INT_EN*///order???
+#define GPIO4_EINT_EN			3
+#define GPIO3_EINT_EN			2
+#define GPIO2_EINT_EN			1
+#define GPIO1_EINT_EN			0
+
+/*GPIO_INT_STATUS*///order???
+#define GPIO4_EINT_STA			3
+#define GPIO3_EINT_STA			2
+#define GPIO2_EINT_STA			1
+#define GPIO1_EINT_STA			0
+
+
+/*PRNG_CLK_CTRL*/
+#define PRNG_CLK_EN				1
+#define PRNG_CLK_POS			0
+
+
+
+/*** Some Config Value ***/
+
+//[SYSCLK_CTRL]: PLLCLK_SRC
+#define PLLCLK_SRC_MCLK			0
+#define PLLCLK_SRC_BCLK			1
+#define PLLCLK_SRC_GPIO2		2
+#define PLLCLK_SRC_GPIO3		3
+
+//[SYSCLK_CTRL]: SYSCLK_SRC
+#define SYSCLK_SRC_MCLK			0
+#define SYSCLK_SRC_PLL			1
+
+//I2S BCLK POLARITY Control
+#define BCLK_NORMAL_DRIVE_N_SAMPLE_P	0
+#define BCLK_INVERT_DRIVE_P_SAMPLE_N	1
+
+//I2S LRCK POLARITY Control
+#define	LRCK_LEFT_LOW_RIGHT_HIGH		0
+#define LRCK_LEFT_HIGH_RIGHT_LOW		1
+
+//I2S Format Selection
+#define PCM_FORMAT						0
+#define LEFT_JUSTIFIED_FORMAT			1
+#define RIGHT_JUSTIFIED_FORMAT			2
+
+
+//I2S data protocol types
+
+#define IS_ENCODING_MODE		 0
+
+#endif
+
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/seeed-voicecard/ac108_6mic.state b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/seeed-voicecard/ac108_6mic.state
new file mode 100644
index 0000000000000000000000000000000000000000..bdbe64a899489e7371c9306312a3254b3f25d95c
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/seeed-voicecard/ac108_6mic.state
@@ -0,0 +1,367 @@
+state.ALSA {
+	control.1 {
+		iface MIXER
+		name 'PCM Playback Volume'
+		value 400
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '-10239 - 400'
+			dbmin -9999999
+			dbmax 400
+			dbvalue.0 400
+		}
+	}
+	control.2 {
+		iface MIXER
+		name 'PCM Playback Switch'
+		value true
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.3 {
+		iface MIXER
+		name 'PCM Playback Route'
+		value 1
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 2'
+		}
+	}
+	control.4 {
+		iface PCM
+		name 'IEC958 Playback Default'
+		value '0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000'
+		comment {
+			access 'read write'
+			type IEC958
+			count 1
+		}
+	}
+	control.5 {
+		iface PCM
+		name 'IEC958 Playback Con Mask'
+		value '0200000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000'
+		comment {
+			access read
+			type IEC958
+			count 1
+		}
+	}
+	control.6 {
+		iface PCM
+		name 'IEC958 Playback PCM Stream'
+		value '0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000'
+		comment {
+			access 'read write inactive'
+			type IEC958
+			count 1
+		}
+	}
+}
+state.seeed8micvoicec {
+	control.1 {
+		iface MIXER
+		name 'CH1 digital volume'
+		value 208
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 255'
+			dbmin -11925
+			dbmax 7200
+			dbvalue.0 3675
+		}
+	}
+	control.2 {
+		iface MIXER
+		name 'CH2 digital volume'
+		value 208
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 255'
+			dbmin -11925
+			dbmax 7200
+			dbvalue.0 3675
+		}
+	}
+	control.3 {
+		iface MIXER
+		name 'CH3 digital volume'
+		value 208
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 255'
+			dbmin -11925
+			dbmax 7200
+			dbvalue.0 3675
+		}
+	}
+	control.4 {
+		iface MIXER
+		name 'CH4 digital volume'
+		value 208
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 255'
+			dbmin -11925
+			dbmax 7200
+			dbvalue.0 3675
+		}
+	}
+	control.5 {
+		iface MIXER
+		name 'ADC1 PGA gain'
+		value 0
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 31'
+			dbmin 0
+			dbmax 3100
+			dbvalue.0 0
+		}
+	}
+	control.6 {
+		iface MIXER
+		name 'ADC2 PGA gain'
+		value 0
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 31'
+			dbmin 0
+			dbmax 3100
+			dbvalue.0 0
+		}
+	}
+	control.7 {
+		iface MIXER
+		name 'ADC3 PGA gain'
+		value 0
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 31'
+			dbmin 0
+			dbmax 3100
+			dbvalue.0 0
+		}
+	}
+	control.8 {
+		iface MIXER
+		name 'ADC4 PGA gain'
+		value 0
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 31'
+			dbmin 0
+			dbmax 3100
+			dbvalue.0 0
+		}
+	}
+	control.9 {
+		iface MIXER
+		name 'CH5 digital volume'
+		value 208
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 255'
+			dbmin -11925
+			dbmax 7200
+			dbvalue.0 3675
+		}
+	}
+	control.10 {
+		iface MIXER
+		name 'CH6 digital volume'
+		value 208
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 255'
+			dbmin -11925
+			dbmax 7200
+			dbvalue.0 3675
+		}
+	}
+	control.11 {
+		iface MIXER
+		name 'CH7 digital volume'
+		value 198
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 255'
+			dbmin -11925
+			dbmax 7200
+			dbvalue.0 2925
+		}
+	}
+	control.12 {
+		iface MIXER
+		name 'CH8 digital volume'
+		value 198
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 255'
+			dbmin -11925
+			dbmax 7200
+			dbvalue.0 2925
+		}
+	}
+	control.13 {
+		iface MIXER
+		name 'ADC5 PGA gain'
+		value 0
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 31'
+			dbmin 0
+			dbmax 3100
+			dbvalue.0 0
+		}
+	}
+	control.14 {
+		iface MIXER
+		name 'ADC6 PGA gain'
+		value 0
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 31'
+			dbmin 0
+			dbmax 3100
+			dbvalue.0 0
+		}
+	}
+	control.15 {
+		iface MIXER
+		name 'ADC7 PGA gain'
+		value 0
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 31'
+			dbmin 0
+			dbmax 3100
+			dbvalue.0 0
+		}
+	}
+	control.16 {
+		iface MIXER
+		name 'ADC8 PGA gain'
+		value 0
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 31'
+			dbmin 0
+			dbmax 3100
+			dbvalue.0 0
+		}
+	}
+	control.17 {
+		iface MIXER
+		name 'DAC volume'
+		value.0 0
+		value.1 0
+		comment {
+			access 'read write'
+			type INTEGER
+			count 2
+			range '0 - 255'
+			dbmin -11925
+			dbmax 7200
+			dbvalue.0 -11925
+			dbvalue.1 -11925
+		}
+	}
+	control.18 {
+		iface MIXER
+		name 'DAC mixer gain'
+		value.0 0
+		value.1 0
+		comment {
+			access 'read write'
+			type INTEGER
+			count 2
+			range '0 - 15'
+			dbmin -600
+			dbmax 8400
+			dbvalue.0 -600
+			dbvalue.1 -600
+		}
+	}
+	control.19 {
+		iface MIXER
+		name 'digital volume'
+		value 51
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 63'
+			dbmin -7308
+			dbmax 0
+			dbvalue.0 -1392
+		}
+	}
+	control.20 {
+		iface MIXER
+		name 'speaker volume'
+		value 25
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 31'
+			dbmin -4800
+			dbmax -150
+			dbvalue.0 -1050
+		}
+	}
+	control.21 {
+		iface MIXER
+		name 'headphone volume'
+		value 52
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 63'
+			dbmin -6300
+			dbmax 0
+			dbvalue.0 -1100
+		}
+	}
+}
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/seeed-voicecard/ac108_asound.state b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/seeed-voicecard/ac108_asound.state
new file mode 100644
index 0000000000000000000000000000000000000000..103bfb487980ec71bc34b81c07c547f234b6eae4
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/seeed-voicecard/ac108_asound.state
@@ -0,0 +1,181 @@
+state.ALSA {
+	control.1 {
+		iface MIXER
+		name 'PCM Playback Volume'
+		value 400
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '-10239 - 400'
+			dbmin -9999999
+			dbmax 400
+			dbvalue.0 400
+		}
+	}
+	control.2 {
+		iface MIXER
+		name 'PCM Playback Switch'
+		value true
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.3 {
+		iface MIXER
+		name 'PCM Playback Route'
+		value 0
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 2'
+		}
+	}
+	control.4 {
+		iface PCM
+		name 'IEC958 Playback Default'
+		value '0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000'
+		comment {
+			access 'read write'
+			type IEC958
+			count 1
+		}
+	}
+	control.5 {
+		iface PCM
+		name 'IEC958 Playback Con Mask'
+		value '0200000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000'
+		comment {
+			access read
+			type IEC958
+			count 1
+		}
+	}
+	control.6 {
+		iface PCM
+		name 'IEC958 Playback PCM Stream'
+		value '0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000'
+		comment {
+			access 'read write inactive'
+			type IEC958
+			count 1
+		}
+	}
+}
+state.seeed4micvoicec {
+	control.1 {
+		iface MIXER
+		name 'CH1 digital volume'
+		value 222
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 255'
+			dbmin -11925
+			dbmax 7200
+			dbvalue.0 4725
+		}
+	}
+	control.2 {
+		iface MIXER
+		name 'CH2 digital volume'
+		value 222
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 255'
+			dbmin -11925
+			dbmax 7200
+			dbvalue.0 4725
+		}
+	}
+	control.3 {
+		iface MIXER
+		name 'CH3 digital volume'
+		value 222
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 255'
+			dbmin -11925
+			dbmax 7200
+			dbvalue.0 4725
+		}
+	}
+	control.4 {
+		iface MIXER
+		name 'CH4 digital volume'
+		value 222
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 255'
+			dbmin -11925
+			dbmax 7200
+			dbvalue.0 4725
+		}
+	}
+	control.5 {
+		iface MIXER
+		name 'ADC1 PGA gain'
+		value 0
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 31'
+			dbmin 0
+			dbmax 3100
+			dbvalue.0 0
+		}
+	}
+	control.6 {
+		iface MIXER
+		name 'ADC2 PGA gain'
+		value 0
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 31'
+			dbmin 0
+			dbmax 3100
+			dbvalue.0 0
+		}
+	}
+	control.7 {
+		iface MIXER
+		name 'ADC3 PGA gain'
+		value 0
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 31'
+			dbmin 0
+			dbmax 3100
+			dbvalue.0 0
+		}
+	}
+	control.8 {
+		iface MIXER
+		name 'ADC4 PGA gain'
+		value 0
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 31'
+			dbmin 0
+			dbmax 3100
+			dbvalue.0 0
+		}
+	}
+}
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/seeed-voicecard/ac108_plugin/Makefile b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/seeed-voicecard/ac108_plugin/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..2a32ae9b5438bceb69617474c4abd22258ac51ec
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/seeed-voicecard/ac108_plugin/Makefile
@@ -0,0 +1,58 @@
+
+# Quiet (set to @ for a quite compile)
+Q	?= @
+#Q	?=
+
+# Build Tools
+CC 	:= gcc
+CFLAGS += -I. -Wall -funroll-loops -ffast-math -fPIC -DPIC -O0 -g
+LD := gcc
+LDFLAGS += -Wall -shared -lasound
+
+SND_PCM_OBJECTS = pcm_ac108.o ac108_help.o
+SND_PCM_LIBS =
+SND_PCM_BIN = libasound_module_pcm_ac108.so
+
+#SND_CTL_OBJECTS = ctl_ac108.o ladspa_utils.o
+#SND_CTL_LIBS =
+#SND_CTL_BIN = libasound_module_ctl_ac108.so
+
+MULTIARCH:=$(shell gcc --print-multiarch)
+LIBDIR = lib/$(MULTIARCH)
+
+.PHONY: all clean dep load_default
+
+all: Makefile $(SND_PCM_BIN) $(SND_CTL_BIN)
+
+dep:
+	@echo DEP $@
+	$(Q)for i in *.c; do $(CC) -MM $(CFLAGS) "$${i}" ; done > makefile.dep
+
+-include makefile.dep
+
+$(SND_PCM_BIN): $(SND_PCM_OBJECTS)
+	@echo LD $@
+	$(Q)$(LD) $(LDFLAGS) $(SND_PCM_LIBS) $(SND_PCM_OBJECTS) -o $(SND_PCM_BIN)
+
+#$(SND_CTL_BIN): $(SND_CTL_OBJECTS)
+#	@echo LD $@
+#	$(Q)$(LD) $(LDFLAGS) $(SND_CTL_LIBS) $(SND_CTL_OBJECTS) -o $(SND_CTL_BIN)
+
+%.o: %.c
+	@echo GCC $<
+	$(Q)$(CC) -c $(CFLAGS) $(CPPFLAGS) $<
+
+clean:
+	@echo Cleaning...
+	$(Q)rm -vf *.o *.so
+
+install: all
+	@echo Installing...
+	$(Q)mkdir -p ${DESTDIR}/usr/$(LIBDIR)/alsa-lib/
+	$(Q)install -m 644 $(SND_PCM_BIN) ${DESTDIR}/usr/$(LIBDIR)/alsa-lib/
+	#$(Q)install -m 644 $(SND_CTL_BIN) ${DESTDIR}/usr/$(LIBDIR)/alsa-lib/
+
+uninstall:
+	@echo Un-installing...
+	$(Q)rm ${DESTDIR}/usr/lib/alsa-lib/$(SND_PCM_BIN)
+	#$(Q)rm ${DESTDIR}/usr/lib/alsa-lib/$(SND_CTL_BIN)
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/seeed-voicecard/ac108_plugin/README.md b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/seeed-voicecard/ac108_plugin/README.md
new file mode 100644
index 0000000000000000000000000000000000000000..38137b208d64c5d2928be52cacee889b10cd87aa
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/seeed-voicecard/ac108_plugin/README.md
@@ -0,0 +1,5 @@
+#seeed-4mic-voicecard alsa plugin
+```
+sudo apt install libasound2-dev
+make && sudo make install
+```
\ No newline at end of file
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/seeed-voicecard/ac108_plugin/ac108_help.c b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/seeed-voicecard/ac108_plugin/ac108_help.c
new file mode 100644
index 0000000000000000000000000000000000000000..cb5fd810b631e227df899611adb279e6800f5a03
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/seeed-voicecard/ac108_plugin/ac108_help.c
@@ -0,0 +1,77 @@
+#include "ac108_help.h"
+
+void generate_sine(const snd_pcm_channel_area_t *areas, 
+			  snd_pcm_uframes_t offset,
+			  int count, double *_phase)
+{
+	 snd_pcm_format_t format = SND_PCM_FORMAT_S32;	/* sample format */
+	 unsigned int rate = 16000;			/* stream rate */
+	 unsigned int channels = 4;			/* count of channels */
+	 unsigned int buffer_time = 500000;		/* ring buffer length in us */
+	 unsigned int period_time = 100000;		/* period time in us */
+	 double freq = 160;				/* sinusoidal wave frequency in Hz */
+	 int verbose = 0;					/* verbose flag */
+	 int resample = 1;				/* enable alsa-lib resampling */
+	 int period_event = 0;				/* produce poll event after each period */
+		
+	static double max_phase = 2. * M_PI;
+	double phase = *_phase;
+	double step = max_phase*freq/(double)rate;
+	unsigned char *samples[channels];
+	int steps[channels];
+	unsigned int chn;
+	int format_bits = snd_pcm_format_width(format);
+	unsigned int maxval = (1 << (format_bits - 1)) - 1;
+	int bps = format_bits / 8;  /* bytes per sample */
+	int phys_bps = snd_pcm_format_physical_width(format) / 8;
+	int big_endian = snd_pcm_format_big_endian(format) == 1;
+	int to_unsigned = snd_pcm_format_unsigned(format) == 1;
+	int is_float = (format == SND_PCM_FORMAT_FLOAT_LE ||
+			format == SND_PCM_FORMAT_FLOAT_BE);
+
+	/* verify and prepare the contents of areas */
+	for (chn = 0; chn < channels; chn++) {
+		if ((areas[chn].first % 8) != 0) {
+			printf("areas[%i].first == %i, aborting...\n", chn, areas[chn].first);
+			exit(EXIT_FAILURE);
+		}
+		samples[chn] = /*(signed short *)*/(((unsigned char *)areas[chn].addr) + (areas[chn].first / 8));
+		if ((areas[chn].step % 16) != 0) {
+			printf("areas[%i].step == %i, aborting...\n", chn, areas[chn].step);
+			exit(EXIT_FAILURE);
+		}
+		steps[chn] = areas[chn].step / 8;
+		samples[chn] += offset * steps[chn];
+	}
+	/* fill the channel areas */
+	while (count-- > 0) {
+		union {
+			float f;
+			int i;
+		} fval;
+		int res, i;
+		if (is_float) {
+			fval.f = sin(phase);
+			res = fval.i;
+		} else
+			res = sin(phase) * maxval;
+		if (to_unsigned)
+			res ^= 1U << (format_bits - 1);
+		for (chn = 0; chn < channels; chn++) {
+			/* Generate data in native endian format */
+			if (big_endian) {
+				for (i = 0; i < bps; i++)
+					*(samples[chn] + phys_bps - 1 - i) = (res >> i * 8) & 0xff;
+			} else {
+				for (i = 0; i < bps; i++)
+					*(samples[chn] + i) = (res >>  i * 8) & 0xff;
+			}
+			samples[chn] += steps[chn];
+		}
+		phase += step;
+		if (phase >= max_phase)
+			phase -= max_phase;
+	}
+	*_phase = phase;
+}
+
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/seeed-voicecard/ac108_plugin/ac108_help.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/seeed-voicecard/ac108_plugin/ac108_help.h
new file mode 100644
index 0000000000000000000000000000000000000000..97adb84c8b77c5994077ad2159aaa1d8e6bb7759
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/seeed-voicecard/ac108_plugin/ac108_help.h
@@ -0,0 +1,11 @@
+#include <stdio.h>
+#include <string.h>
+#include <unistd.h>
+#include <alsa/asoundlib.h>
+#include <alsa/pcm_external.h>
+#include <alsa/pcm_plugin.h>
+#include <math.h>
+
+void generate_sine(const snd_pcm_channel_area_t *areas,        
+                          snd_pcm_uframes_t offset,
+                          int count, double *_phase);
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/seeed-voicecard/ac108_plugin/libasound_module_pcm_ac108.so b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/seeed-voicecard/ac108_plugin/libasound_module_pcm_ac108.so
new file mode 100644
index 0000000000000000000000000000000000000000..ca8ca04d6a121767c1a26c3c00f3f38825cffb3f
Binary files /dev/null and b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/seeed-voicecard/ac108_plugin/libasound_module_pcm_ac108.so differ
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/seeed-voicecard/ac108_plugin/pcm_ac108.c b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/seeed-voicecard/ac108_plugin/pcm_ac108.c
new file mode 100644
index 0000000000000000000000000000000000000000..9ade62aa7a18f14d46c1c34b0852c1dc4333d671
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/seeed-voicecard/ac108_plugin/pcm_ac108.c
@@ -0,0 +1,536 @@
+//https://github.com/HazouPH/android_device_motorola_smi-plus/blob/48029b4afc307c73181b108a5b0155b9f20856ca/smi-modules/alsa-lib_module_voice/pcm_voice.c
+#include <stdio.h>
+#include <string.h>
+#include <unistd.h>
+#include <alsa/asoundlib.h>
+#include <alsa/pcm_external.h>
+#include <alsa/pcm_plugin.h>
+#include "ac108_help.h"
+#include <math.h>
+
+#define ARRAY_SIZE(ary)	(sizeof(ary)/sizeof(ary[0]))
+#define  AC108_FRAME_SIZE 40960
+struct ac108_t {
+	snd_pcm_ioplug_t io;
+	snd_pcm_t *pcm;
+	snd_pcm_hw_params_t *hw_params;
+	unsigned int last_size;
+	unsigned int ptr;
+	unsigned int        latency;         // Delay in usec
+	unsigned int        bufferSize;      // Size of sample buffer
+};
+static unsigned char capture_buf[AC108_FRAME_SIZE];
+/* set up the fixed parameters of pcm PCM hw_parmas */
+static int ac108_slave_hw_params_half(struct ac108_t *capture, unsigned int rate,snd_pcm_format_t format) {
+	int err;
+    snd_pcm_uframes_t bufferSize = capture->bufferSize;
+    unsigned int latency = capture->latency;
+
+    unsigned int buffer_time = 0;
+    unsigned int period_time = 0;
+	if ((err = snd_pcm_hw_params_malloc(&capture->hw_params)) < 0) return err;
+
+	if ((err = snd_pcm_hw_params_any(capture->pcm, capture->hw_params)) < 0) {
+		SNDERR("Cannot get pcm hw_params");
+		goto out;
+	}
+	if ((err = snd_pcm_hw_params_set_access(capture->pcm, capture->hw_params,
+											SND_PCM_ACCESS_RW_INTERLEAVED)) < 0) {
+		SNDERR("Cannot set pcm access RW_INTERLEAVED");
+		goto out;
+	}
+	if ((err = snd_pcm_hw_params_set_channels(capture->pcm, capture->hw_params, 2)) < 0) {
+		SNDERR("Cannot set pcm channels 2");
+		goto out;
+	}
+	if ((err = snd_pcm_hw_params_set_format(capture->pcm, capture->hw_params,
+											format)) < 0) {
+		SNDERR("Cannot set pcm format");
+		goto out;
+	}
+	if ((err = snd_pcm_hw_params_set_rate(capture->pcm, capture->hw_params, rate, 0)) < 0) {
+		SNDERR("Cannot set pcm rate %d", rate);
+		goto out;
+	}
+
+    err = snd_pcm_hw_params_get_buffer_time_max(capture->hw_params,
+            &buffer_time, 0);
+    if (buffer_time > 80000)
+        buffer_time = 80000;
+    period_time = buffer_time / 4;
+
+    err = snd_pcm_hw_params_set_period_time_near(capture->pcm, capture->hw_params,
+            &period_time, 0);
+    if (err < 0) {
+        SNDERR("Unable to set_period_time_near");
+        goto out;
+    }
+    err = snd_pcm_hw_params_set_buffer_time_near(capture->pcm, capture->hw_params,
+            &buffer_time, 0);
+    if (err < 0) {
+        SNDERR("Unable to set_buffer_time_near");
+        goto out;
+    }
+
+    capture->bufferSize = bufferSize;
+    capture->latency = latency;
+
+	return 0;
+
+out:
+	free(capture->hw_params);
+	capture->hw_params = NULL;
+	return err;
+}
+
+/*
+ * start and stop callbacks - just trigger pcm PCM
+ */
+static int ac108_start(snd_pcm_ioplug_t *io) {
+	struct ac108_t *capture = io->private_data;
+    if(!capture->pcm) {
+		SNDERR( "pcm is lost\n");
+	}	
+
+	return snd_pcm_start(capture->pcm);
+}
+
+static int ac108_stop(snd_pcm_ioplug_t *io) {
+	struct ac108_t *capture = io->private_data;
+
+	return snd_pcm_drop(capture->pcm);
+}
+/*
+ * pointer callback
+ *
+ * Calculate the current position from the delay of pcm PCM
+ */
+static snd_pcm_sframes_t ac108_pointer(snd_pcm_ioplug_t *io) {
+
+	struct ac108_t *capture = io->private_data;
+	int  size;
+	
+	assert(capture);
+
+
+	size = snd_pcm_avail(capture->pcm);
+	if (size < 0) 
+		return size;
+
+	size = size/2;
+
+	if (size > capture->last_size) {
+			capture->ptr += size - capture->last_size;
+			capture->ptr %= io->buffer_size;
+	}
+
+	//fprintf(stderr, "%s :%d %d %d %d %d %d\n", __func__,capture->ptr ,capture->last_size,size,  io->buffer_size,io->appl_ptr, io->hw_ptr);
+	capture->last_size = size;
+	
+	return capture->ptr;
+}
+
+/*
+ * transfer callback
+ */
+static snd_pcm_sframes_t ac108_transfer(snd_pcm_ioplug_t *io,
+										const snd_pcm_channel_area_t *dst_areas,
+										snd_pcm_uframes_t dst_offset,
+										snd_pcm_uframes_t size) {
+	struct ac108_t *capture = io->private_data;
+	int chn;
+	unsigned char *dst_samples[io->channels];
+	int dst_steps[io->channels];
+	int bps = snd_pcm_format_width(io->format) / 8;  /* bytes per sample */
+	int i;
+	int count = 0;	
+	int err = 0;
+	unsigned char *src_buf;
+	unsigned char src_data[4][4];
+
+	
+	memset(capture_buf,0,AC108_FRAME_SIZE);
+
+	if(snd_pcm_avail(capture->pcm) > size*2){
+		if ((err = snd_pcm_readi (capture->pcm, capture_buf, size*2)) != size*2) {
+			SNDERR("read from audio interface failed %ld %d  %s!\n",size,err,snd_strerror (err));
+			exit(EXIT_FAILURE);
+			size = 0 ;
+		}
+	}else{
+		size = 0;
+	}
+#if 1	
+	/* verify and prepare the contents of areas */
+	for (chn = 0; chn < io->channels; chn++) {
+		if ((dst_areas[chn].first % 8) != 0) {
+			SNDERR("dst_areas[%i].first == %i, aborting...\n", chn, dst_areas[chn].first);
+			exit(EXIT_FAILURE);
+		}
+		dst_samples[chn] = /*(signed short *)*/(((unsigned char *)dst_areas[chn].addr) + (dst_areas[chn].first / 8));
+		if ((dst_areas[chn].step % 16) != 0) {
+			SNDERR("dst_areas[%i].step == %i, aborting...\n", chn, dst_areas[chn].step);
+			exit(EXIT_FAILURE);
+		}
+		dst_steps[chn] = dst_areas[chn].step / 8;
+		dst_samples[chn] += dst_offset * dst_steps[chn];
+	}
+#endif	
+	//  for(i = 0; i < size*2*bps;i++){
+	// 	fprintf(stderr,"%x ",capture_buf[i]);
+	// 	if(i%4 == 0)
+	// 		fprintf(stderr,"\n");
+	// }
+
+	//generate_sine(dst_areas, dst_offset,size, &count);
+	src_buf = capture_buf;
+#if 1
+	while(count < size){
+		for(chn = 0; chn < 4; chn++){
+			for (i = 0; i < bps; i++){
+				src_data[chn][i] = src_buf[i];
+			}
+			src_buf += bps ;						
+		}
+
+		for(chn = 0; chn < io->channels; chn++){
+			for (i = 0; i < bps; i++){
+				*(dst_samples[chn] + i) = src_data[chn][i];
+				//fprintf(stderr,"%x ",*(dst_samples[chn] + i));
+			}
+			//fprintf(stderr,"\n");
+			dst_samples[chn] += dst_steps[chn];	
+		}
+		count++;
+	}
+
+#endif
+
+	capture->last_size -= size;
+	
+	return size;
+}
+
+/*
+ * poll-related callbacks - just pass to pcm PCM
+ */
+static int ac108_poll_descriptors_count(snd_pcm_ioplug_t *io) {
+	struct ac108_t *capture = io->private_data;
+
+	return snd_pcm_poll_descriptors_count(capture->pcm);
+}
+
+static int ac108_poll_descriptors(snd_pcm_ioplug_t *io, struct pollfd *pfd,
+								  unsigned int space) {
+	struct ac108_t *capture = io->private_data;
+
+	return snd_pcm_poll_descriptors(capture->pcm, pfd, space);
+}
+
+static int ac108_poll_revents(snd_pcm_ioplug_t *io, struct pollfd *pfd,
+							  unsigned int nfds, unsigned short *revents) {
+	struct ac108_t *capture = io->private_data;
+
+	return snd_pcm_poll_descriptors_revents(capture->pcm, pfd, nfds, revents);
+}
+
+/*
+ * close callback
+ */
+static int ac108_close(snd_pcm_ioplug_t *io) {
+	struct ac108_t *capture = io->private_data;
+	if (capture->pcm)  
+		snd_pcm_close(capture->pcm);
+
+	return 0;
+}
+
+static int setSoftwareParams(struct ac108_t *capture) {
+	snd_pcm_sw_params_t *softwareParams;
+	int err;
+
+	snd_pcm_uframes_t bufferSize = 0;
+	snd_pcm_uframes_t periodSize = 0;
+	snd_pcm_uframes_t startThreshold, stopThreshold;
+	snd_pcm_sw_params_alloca(&softwareParams);
+
+	// Get the current software parameters
+	err = snd_pcm_sw_params_current(capture->pcm, softwareParams);
+	if (err < 0) {
+		SNDERR("Unable to get software parameters: %s", snd_strerror(err));
+		goto done;
+	}
+
+	// Configure ALSA to start the transfer when the buffer is almost full.
+	snd_pcm_get_params(capture->pcm, &bufferSize, &periodSize);
+
+
+	startThreshold = 1;
+	stopThreshold = bufferSize;
+
+
+	err = snd_pcm_sw_params_set_start_threshold(capture->pcm, softwareParams,
+												startThreshold);
+	if (err < 0) {
+		SNDERR("Unable to set start threshold to %lu frames: %s",
+				startThreshold, snd_strerror(err));
+		goto done;
+	}
+
+	err = snd_pcm_sw_params_set_stop_threshold(capture->pcm, softwareParams,
+											   stopThreshold);
+	if (err < 0) {
+		SNDERR("Unable to set stop threshold to %lu frames: %s",
+				stopThreshold, snd_strerror(err));
+		goto done;
+	}
+	// Allow the transfer to start when at least periodSize samples can be
+	// processed.
+	err = snd_pcm_sw_params_set_avail_min(capture->pcm, softwareParams,
+										  periodSize);
+	if (err < 0) {
+		SNDERR("Unable to configure available minimum to %lu: %s",
+				periodSize, snd_strerror(err));
+		goto done;
+	}
+
+	// Commit the software parameters back to the device.
+	err = snd_pcm_sw_params(capture->pcm, softwareParams);
+	if (err < 0) 
+		SNDERR("Unable to configure software parameters: %s",snd_strerror(err));
+
+
+
+	return 0;
+done:
+	snd_pcm_sw_params_free(softwareParams);
+
+	return err;
+}
+/*
+ * hw_params callback
+ *
+ * Set up pcm PCM according to the current parameters
+ */
+static int ac108_hw_params(snd_pcm_ioplug_t *io, snd_pcm_hw_params_t *params) {
+	struct ac108_t *capture = io->private_data;
+	snd_pcm_uframes_t period_size;
+	snd_pcm_uframes_t buffer_size;
+	int err;
+	if (!capture->hw_params) {
+		err = ac108_slave_hw_params_half(capture, 2*io->rate,io->format);
+		if (err < 0) {
+			SNDERR("ac108_slave_hw_params_half error\n");
+			return err;
+		}
+	}
+	period_size = io->period_size;
+	if ((err = snd_pcm_hw_params_set_period_size_near(capture->pcm, capture->hw_params,
+													  &period_size, NULL)) < 0) {
+		SNDERR("Cannot set pcm period size %ld", period_size);
+		return err;
+	}
+	buffer_size = io->buffer_size;
+	if ((err = snd_pcm_hw_params_set_buffer_size_near(capture->pcm, capture->hw_params,
+													  &buffer_size)) < 0) {
+		SNDERR("Cannot set pcm buffer size %ld", buffer_size);
+		return err;
+	}
+	if ((err = snd_pcm_hw_params(capture->pcm, capture->hw_params)) < 0) {
+		SNDERR("Cannot set pcm hw_params");
+		return err;
+	}
+	setSoftwareParams(capture);
+	return 0;
+}
+/*
+ * hw_free callback
+ */
+static int ac108_hw_free(snd_pcm_ioplug_t *io) {
+	struct ac108_t *capture = io->private_data;
+	free(capture->hw_params);
+	capture->hw_params = NULL;
+	
+	return snd_pcm_hw_free(capture->pcm);
+
+}
+
+
+static int ac108_prepare(snd_pcm_ioplug_t *io) {
+	struct ac108_t *capture = io->private_data;
+	capture->ptr = 0;
+	capture->last_size =0;
+	return snd_pcm_prepare(capture->pcm);
+}
+static int ac108_drain(snd_pcm_ioplug_t *io) {
+	struct ac108_t *capture = io->private_data;
+	
+	return snd_pcm_drain(capture->pcm);
+}
+#if 0
+static int ac108_sw_params(snd_pcm_ioplug_t *io, snd_pcm_sw_params_t *params) {
+	return 0;
+}
+#endif 
+static int ac108_delay(snd_pcm_ioplug_t * io, snd_pcm_sframes_t * delayp){
+
+	return 0;
+}
+/*
+ * callback table
+ */
+static snd_pcm_ioplug_callback_t a108_ops = {
+	.start = ac108_start,
+	.stop = ac108_stop,
+	.pointer = ac108_pointer,
+	.transfer = ac108_transfer,
+	.poll_descriptors_count = ac108_poll_descriptors_count,
+	.poll_descriptors = ac108_poll_descriptors,
+	.poll_revents = ac108_poll_revents,
+	.close = ac108_close,
+	.hw_params = ac108_hw_params,
+	.hw_free = ac108_hw_free,
+//	.sw_params = ac108_sw_params,
+	.prepare = ac108_prepare,
+	.drain = ac108_drain,
+	.delay = ac108_delay,
+};
+
+
+static int ac108_set_hw_constraint(struct ac108_t  *capture) {
+	static unsigned int accesses[] = {
+		SND_PCM_ACCESS_RW_INTERLEAVED 
+	};
+	unsigned int formats[] = { SND_PCM_FORMAT_S32,
+							   SND_PCM_FORMAT_S16 };
+
+	unsigned int  rates[] = {
+		8000,
+		16000,
+		32000,
+		44100,
+		48000,
+		96000
+	};
+	int err;
+
+
+	err = snd_pcm_ioplug_set_param_list(&capture->io,
+										SND_PCM_IOPLUG_HW_ACCESS,
+										ARRAY_SIZE(accesses),
+										accesses);
+	if (err < 0){
+		SNDERR("ioplug cannot set ac108 hw access");
+		return err;
+	} 
+
+	if ((err = snd_pcm_ioplug_set_param_list(&capture->io, SND_PCM_IOPLUG_HW_FORMAT,
+											 ARRAY_SIZE(formats), formats)) < 0 ||
+		(err = snd_pcm_ioplug_set_param_minmax(&capture->io, SND_PCM_IOPLUG_HW_CHANNELS,
+											   1, 4)) < 0 ||
+		(err = snd_pcm_ioplug_set_param_list(&capture->io, SND_PCM_IOPLUG_HW_RATE,
+												ARRAY_SIZE(rates), rates)) < 0) 
+												{
+		SNDERR("ioplug cannot set ac108 format channel rate!");											
+		return err;
+	}
+	err = snd_pcm_ioplug_set_param_minmax(&capture->io,SND_PCM_IOPLUG_HW_BUFFER_BYTES,
+										  1, 4 * 1024 * 1024);
+	if (err < 0){ 
+		SNDERR("ioplug cannot set ac108 hw buffer bytes");		
+		return err;
+	}
+
+	err = snd_pcm_ioplug_set_param_minmax(&capture->io,SND_PCM_IOPLUG_HW_PERIOD_BYTES,
+										  128, 2 * 1024 * 1024);
+	if (err < 0) {
+		SNDERR("ioplug cannot set ac108 hw period bytes");		
+		return err;
+	}
+
+	err = snd_pcm_ioplug_set_param_minmax(&capture->io, SND_PCM_IOPLUG_HW_PERIODS,3, 1024);
+	if (err < 0) {
+		SNDERR("ioplug cannot set ac108 hw periods");		
+		return err;
+	}									  
+	return 0;
+}
+
+/*
+ * Main entry point
+ */
+SND_PCM_PLUGIN_DEFINE_FUNC(ac108) {
+	snd_config_iterator_t i, next;
+	int err;
+	const char *pcm_string = NULL;
+	struct ac108_t *capture;
+	int channels;
+	if (stream != SND_PCM_STREAM_CAPTURE) {
+		SNDERR("a108 is only for capture");
+		return -EINVAL;
+	}
+
+	snd_config_for_each(i, next, conf) {
+		snd_config_t *n = snd_config_iterator_entry(i);
+		const char *id;
+		if (snd_config_get_id(n, &id) < 0) continue;
+		if (strcmp(id, "comment") == 0 || strcmp(id, "type") == 0 || strcmp(id, "hint") == 0) continue;
+
+		if (strcmp(id, "slavepcm") == 0) {
+			if (snd_config_get_string(n, &pcm_string) < 0) {
+				SNDERR("ac108 slavepcm must be a string");
+				return -EINVAL;
+			}
+			continue;
+		}
+
+		if (strcmp(id, "channels") == 0) {
+			long val;
+			if (snd_config_get_integer(n, &val) < 0) {
+				SNDERR("Invalid type for %s", id);
+				return -EINVAL;
+			}
+			channels = val;
+			if (channels != 2 && channels != 4 && channels != 6) {
+				SNDERR("channels must be 2, 4 or 6");
+				return -EINVAL;
+			}
+			continue;
+		}
+	}
+
+
+	capture = calloc(1, sizeof(*capture));
+	if (!capture) {
+		SNDERR("cannot allocate");
+		return -ENOMEM;
+	}
+	err = snd_pcm_open(&capture->pcm, pcm_string, stream, mode);
+	if (err < 0) goto error;
+
+
+	
+	//SND_PCM_NONBLOCK
+	capture->io.version = SND_PCM_IOPLUG_VERSION;
+	capture->io.name = "AC108 decode Plugin";
+	capture->io.mmap_rw = 0;
+	capture->io.callback = &a108_ops;
+	capture->io.private_data = capture;
+
+	err = snd_pcm_ioplug_create(&capture->io, name, stream, mode);
+	if (err < 0) goto error;
+
+	if ((err = ac108_set_hw_constraint(capture)) < 0) {
+		snd_pcm_ioplug_delete(&capture->io);
+		return err;
+	}
+	*pcmp = capture->io.pcm;
+	return 0;
+	
+error:
+	if (capture->pcm) snd_pcm_close(capture->pcm);
+	free(capture);
+	return err;
+}
+
+SND_PCM_PLUGIN_SYMBOL(ac108);
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/seeed-voicecard/ac10x.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/seeed-voicecard/ac10x.h
new file mode 100644
index 0000000000000000000000000000000000000000..9b83807d7be23b22c9725c799f93f84386005c8f
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/seeed-voicecard/ac10x.h
@@ -0,0 +1,126 @@
+/*
+ * ac10x.h
+ *
+ * (C) Copyright 2017-2018
+ * Seeed Technology Co., Ltd. <www.seeedstudio.com>
+ *
+ * PeterYang <linsheng.yang@seeed.cc>
+ *
+ * (C) Copyright 2010-2017
+ * Reuuimlla Technology Co., Ltd. <www.reuuimllatech.com>
+ * huangxin <huangxin@reuuimllatech.com>
+ *
+ * some simple description for this code
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ */
+#ifndef __AC10X_H__
+#define __AC10X_H__
+
+#define AC101_I2C_ID		4
+#define _MASTER_AC108		0
+#define _MASTER_AC101		1
+#define _MASTER_MULTI_CODEC	_MASTER_AC101
+
+/* enable headset detecting & headset button pressing */
+#define CONFIG_AC101_SWITCH_DETECT
+
+/* obsolete */
+#define CONFIG_AC10X_TRIG_LOCK	0
+
+
+#ifdef AC101_DEBG
+    #define AC101_DBG(format,args...)  printk("[AC101] %s() L%d " format, __func__, __LINE__, ##args)
+#else
+    #define AC101_DBG(...)
+#endif
+
+
+#include "sound-compatible-4.18.h"
+
+#ifdef CONFIG_AC101_SWITCH_DETECT
+enum headphone_mode_u {
+	HEADPHONE_IDLE,
+	FOUR_HEADPHONE_PLUGIN,
+	THREE_HEADPHONE_PLUGIN,
+};
+#endif
+
+struct ac10x_priv {
+	struct i2c_client *i2c[4];
+	struct regmap* i2cmap[4];
+	int codec_cnt;
+	unsigned sysclk;
+#define _FREQ_24_576K		24576000
+#define _FREQ_22_579K		22579200
+	unsigned mclk;	/* master clock or aif_clock/aclk */
+	int clk_id;
+	unsigned char i2s_mode;
+	unsigned char data_protocol;
+	struct delayed_work dlywork;
+	int tdm_chips_cnt;
+	int sysclk_en;
+
+	/* member for ac101 .begin */
+	struct snd_soc_codec *codec;
+	struct i2c_client *i2c101;
+	struct regmap* regmap101;
+
+	struct mutex dac_mutex;
+	u8 dac_enable;
+	spinlock_t lock;
+	u8 aif1_clken;
+
+	struct work_struct codec_resume;
+	struct gpio_desc* gpiod_spk_amp_gate;
+
+	#ifdef CONFIG_AC101_SWITCH_DETECT
+	struct gpio_desc* gpiod_irq;
+	long irq;
+	volatile int irq_cntr;
+	volatile int pullout_cntr;
+	volatile int state;
+
+	enum headphone_mode_u mode;
+	struct work_struct work_switch;
+	struct work_struct work_clear_irq;
+
+	struct input_dev* inpdev;
+	#endif
+	/* member for ac101 .end */
+};
+
+
+/* AC101 DAI operations */
+int ac101_audio_startup(struct snd_pcm_substream *substream, struct snd_soc_dai *codec_dai);
+void ac101_aif_shutdown(struct snd_pcm_substream *substream, struct snd_soc_dai *codec_dai);
+int ac101_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt);
+int ac101_hw_params(struct snd_pcm_substream *substream,
+	struct snd_pcm_hw_params *params,
+	struct snd_soc_dai *codec_dai);
+int ac101_trigger(struct snd_pcm_substream *substream, int cmd,
+	 	  struct snd_soc_dai *dai);
+int ac101_aif_mute(struct snd_soc_dai *codec_dai, int mute);
+
+/* codec driver specific */
+int ac101_codec_probe(struct snd_soc_codec *codec);
+int ac101_codec_remove(struct snd_soc_codec *codec);
+int ac101_codec_suspend(struct snd_soc_codec *codec);
+int ac101_codec_resume(struct snd_soc_codec *codec);
+int ac101_set_bias_level(struct snd_soc_codec *codec, enum snd_soc_bias_level level);
+
+/* i2c device specific */
+int ac101_probe(struct i2c_client *i2c, const struct i2c_device_id *id);
+void ac101_shutdown(struct i2c_client *i2c);
+int ac101_remove(struct i2c_client *i2c);
+
+/* seeed voice card export */
+int seeed_voice_card_register_set_clock(int stream, int (*set_clock)(int));
+
+int ac10x_fill_regcache(struct device* dev, struct regmap* map);
+
+#endif//__AC10X_H__
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/seeed-voicecard/asound_2mic.conf b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/seeed-voicecard/asound_2mic.conf
new file mode 100644
index 0000000000000000000000000000000000000000..2e26f0dbe55e52e4b93f4c7f1ad080d5ff0c673d
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/seeed-voicecard/asound_2mic.conf
@@ -0,0 +1,38 @@
+# The IPC key of dmix or dsnoop plugin must be unique
+# If 555555 or 666666 is used by other processes, use another one
+
+
+# use samplerate to resample as speexdsp resample is bad
+defaults.pcm.rate_converter "samplerate"
+
+pcm.!default {
+    type asym
+    playback.pcm "playback"
+    capture.pcm "capture"
+}
+
+pcm.playback {
+    type plug
+    slave.pcm "dmixed"
+}
+
+pcm.capture {
+    type plug
+    slave.pcm "array"
+}
+
+pcm.dmixed {
+    type dmix
+    slave.pcm "hw:seeed2micvoicec"
+    ipc_key 555555 
+}
+
+pcm.array {
+    type dsnoop
+    slave {
+        pcm "hw:seeed2micvoicec"
+        channels 2
+    }
+    ipc_key 666666
+}
+
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/seeed-voicecard/asound_4mic.conf b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/seeed-voicecard/asound_4mic.conf
new file mode 100644
index 0000000000000000000000000000000000000000..12d2ab8e8df6f92468c70bc4d3e40170b21f2412
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/seeed-voicecard/asound_4mic.conf
@@ -0,0 +1,33 @@
+# The IPC key of dmix or dsnoop plugin must be unique
+# If 555555 or 666666 is used by other processes, use another one
+
+# use samplerate to resample as speexdsp resample is bad
+defaults.pcm.rate_converter "samplerate"
+
+pcm.!default {
+    type asym
+    playback.pcm "playback"
+    capture.pcm "ac108"
+}
+
+pcm.playback {
+    type plug
+    slave.pcm "hw:ALSA"
+}
+
+# pcm.dmixed {
+#     type dmix
+#     slave.pcm "hw:0,0"
+#     ipc_key 555555 
+# }
+
+pcm.ac108 {
+    type plug
+    slave.pcm "hw:seeed4micvoicec"
+}
+
+# pcm.multiapps {
+#     type dsnoop
+#     ac108-slavepcm "hw:1,0"
+#     ipc_key 666666
+# }
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/seeed-voicecard/asound_6mic.conf b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/seeed-voicecard/asound_6mic.conf
new file mode 100644
index 0000000000000000000000000000000000000000..c064c56036f34ee2d5ce8a72cdd45e06804dfba4
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/seeed-voicecard/asound_6mic.conf
@@ -0,0 +1,90 @@
+# The IPC key of dmix or dsnoop plugin must be unique
+# If 555555 or 666666 is used by other processes, use another one
+
+# use samplerate to resample as speexdsp resample is broken
+defaults.pcm.rate_converter "samplerate"
+
+pcm.!default {
+    type asym
+    playback.pcm "dmixer"
+    capture.pcm "ac108"
+}
+
+
+pcm.ac108 {
+    type plug
+    slave {
+        rate 48000
+        format S32_LE
+        pcm "hw:seeed8micvoicec"
+    }
+}
+
+# pcm.multiapps {
+#     type plug
+#     slave.pcm {
+#         type dsnoop
+#         slave {
+#             rate 48000
+#             format S32_LE
+#             pcm "hw:seeed8micvoicec"
+#         }
+#         ipc_key 666666
+#     }
+# }
+
+pcm.dmixer {
+    type plug
+    slave {
+        pcm {
+            type dmix
+            ipc_key 555555
+            slave {	
+                pcm "hw:seeed8micvoicec"
+                format S32_LE
+                channels 8
+            }
+            bindings {
+                0 0
+                1 1
+                2 2
+                3 3
+                4 4
+                5 5
+                6 6
+                7 7
+            }
+        }
+        channels 8
+        format S32_LE
+        rate 48000
+    }
+    ttable.0.0 1
+    ttable.1.1 1
+    ttable.0.2 1
+    ttable.1.3 1
+    ttable.0.4 1
+    ttable.1.5 1
+    ttable.0.6 1
+    ttable.1.7 1
+}
+
+pcm.ac101 {
+    type plug
+    slave {
+        pcm "hw:seeed8micvoicec"
+        channels 8
+        format S32_LE
+        rate 48000
+    }
+    ttable.0.0 1
+    ttable.1.1 1
+    ttable.0.2 1
+    ttable.1.3 1
+    ttable.0.4 1
+    ttable.1.5 1
+    ttable.0.6 1
+    ttable.1.7 1
+}
+
+
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/seeed-voicecard/builddtbo.sh b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/seeed-voicecard/builddtbo.sh
new file mode 100644
index 0000000000000000000000000000000000000000..e98800f143b396ccaf07f31d8a7a0e86043c191d
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/seeed-voicecard/builddtbo.sh
@@ -0,0 +1,9 @@
+#dtoverlay -r seeed-2mic-voicecard
+DTC_FLAGS="-b 0 -Wno-unit_address_vs_reg -I dts -O dtb"
+
+dtc -@ $DTC_FLAGS -o seeed-2mic-voicecard.dtbo seeed-2mic-voicecard-overlay.dts
+dtc -@ $DTC_FLAGS -o seeed-4mic-voicecard.dtbo seeed-4mic-voicecard-overlay.dts
+dtc -@ $DTC_FLAGS -o seeed-8mic-voicecard.dtbo seeed-8mic-voicecard-overlay.dts
+
+# cp *.dtbo /boot/overlays
+# dtoverlay seeed-2mic-voicecard
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/seeed-voicecard/default.pa b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/seeed-voicecard/default.pa
new file mode 100644
index 0000000000000000000000000000000000000000..ed20f402ac9b58bc27a5b7332dce6e2f53cc3958
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/seeed-voicecard/default.pa
@@ -0,0 +1,140 @@
+#!/usr/bin/pulseaudio -nF
+#
+# This file is part of PulseAudio.
+#
+# PulseAudio is free software; you can redistribute it and/or modify it
+# under the terms of the GNU Lesser General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# PulseAudio is distributed in the hope that it will be useful, but
+# WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+# General Public License for more details.
+#
+# You should have received a copy of the GNU Lesser General Public License
+# along with PulseAudio; if not, see <http://www.gnu.org/licenses/>.
+
+# This startup script is used only if PulseAudio is started per-user
+# (i.e. not in system mode)
+
+.fail
+
+### Automatically restore the volume of streams and devices
+load-module module-device-restore
+load-module module-stream-restore
+load-module module-card-restore
+
+### Automatically augment property information from .desktop files
+### stored in /usr/share/application
+load-module module-augment-properties
+
+### Should be after module-*-restore but before module-*-detect
+load-module module-switch-on-port-available
+
+### Load audio drivers statically
+### (it's probably better to not load these drivers manually, but instead
+### use module-udev-detect -- see below -- for doing this automatically)
+load-module module-alsa-sink device=hw:0,0
+load-module module-alsa-source device=hw:0,0
+#load-module module-oss device="/dev/dsp" sink_name=output source_name=input
+#load-module module-oss-mmap device="/dev/dsp" sink_name=output source_name=input
+#load-module module-null-sink
+#load-module module-pipe-sink
+
+### Automatically load driver modules depending on the hardware available
+#.ifexists module-udev-detect.so
+#load-module module-udev-detect
+#.else
+### Use the static hardware detection module (for systems that lack udev support)
+#load-module module-detect
+#.endif
+
+### Automatically connect sink and source if JACK server is present
+.ifexists module-jackdbus-detect.so
+.nofail
+load-module module-jackdbus-detect channels=2
+.fail
+.endif
+
+### Automatically load driver modules for Bluetooth hardware
+.ifexists module-bluetooth-policy.so
+load-module module-bluetooth-policy
+.endif
+
+.ifexists module-bluetooth-discover.so
+load-module module-bluetooth-discover
+.endif
+
+### Load several protocols
+.ifexists module-esound-protocol-unix.so
+load-module module-esound-protocol-unix
+.endif
+load-module module-native-protocol-unix
+
+### Network access (may be configured with paprefs, so leave this commented
+### here if you plan to use paprefs)
+#load-module module-esound-protocol-tcp
+#load-module module-native-protocol-tcp
+#load-module module-zeroconf-publish
+
+### Load the RTP receiver module (also configured via paprefs, see above)
+#load-module module-rtp-recv
+
+### Load the RTP sender module (also configured via paprefs, see above)
+#load-module module-null-sink sink_name=rtp format=s16be channels=2 rate=44100 sink_properties="device.description='RTP Multicast Sink'"
+#load-module module-rtp-send source=rtp.monitor
+
+### Load additional modules from GConf settings. This can be configured with the paprefs tool.
+### Please keep in mind that the modules configured by paprefs might conflict with manually
+### loaded modules.
+.ifexists module-gconf.so
+.nofail
+load-module module-gconf
+.fail
+.endif
+
+### Automatically restore the default sink/source when changed by the user
+### during runtime
+### NOTE: This should be loaded as early as possible so that subsequent modules
+### that look up the default sink/source get the right value
+load-module module-default-device-restore
+
+### Automatically move streams to the default sink if the sink they are
+### connected to dies, similar for sources
+load-module module-rescue-streams
+
+### Make sure we always have a sink around, even if it is a null sink.
+load-module module-always-sink
+
+### Honour intended role device property
+load-module module-intended-roles
+
+### Automatically suspend sinks/sources that become idle for too long
+load-module module-suspend-on-idle
+
+### If autoexit on idle is enabled we want to make sure we only quit
+### when no local session needs us anymore.
+.ifexists module-console-kit.so
+load-module module-console-kit
+.endif
+.ifexists module-systemd-login.so
+load-module module-systemd-login
+.endif
+
+### Enable positioned event sounds
+load-module module-position-event-sounds
+
+### Cork music/video streams when a phone stream is active
+load-module module-role-cork
+
+### Modules to allow autoloading of filters (such as echo cancellation)
+### on demand. module-filter-heuristics tries to determine what filters
+### make sense, and module-filter-apply does the heavy-lifting of
+### loading modules and rerouting streams.
+load-module module-filter-heuristics
+load-module module-filter-apply
+
+### Make some devices default
+#set-default-sink output
+#set-default-source input
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/seeed-voicecard/dkms.conf b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/seeed-voicecard/dkms.conf
new file mode 100644
index 0000000000000000000000000000000000000000..6087358fdd7ed819e2ab6ccdaaaeacc8c23592e7
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/seeed-voicecard/dkms.conf
@@ -0,0 +1,9 @@
+PACKAGE_NAME="seeed-voicecard"
+PACKAGE_VERSION="0.3"
+BUILT_MODULE_NAME[0]="snd-soc-wm8960"
+BUILT_MODULE_NAME[1]="snd-soc-ac108"
+BUILT_MODULE_NAME[2]="snd-soc-seeed-voicecard"
+DEST_MODULE_LOCATION[0]="/kernel/sound/soc/codecs"
+DEST_MODULE_LOCATION[1]="/kernel/sound/soc/codecs"
+DEST_MODULE_LOCATION[2]="/kernel/sound/soc/bcm"
+AUTOINSTALL="yes"
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/seeed-voicecard/pulseaudio/91-seeedvoicecard.rules b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/seeed-voicecard/pulseaudio/91-seeedvoicecard.rules
new file mode 100644
index 0000000000000000000000000000000000000000..8b41dd160f2d4c664acfdaa0a9fd13378f1e58f1
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/seeed-voicecard/pulseaudio/91-seeedvoicecard.rules
@@ -0,0 +1,8 @@
+SUBSYSTEM!="sound", GOTO="seeedvoicecard_end"
+ACTION!="change", GOTO="seeedvoicecard_end"
+KERNEL!="card*", GOTO="seeedvoicecard_end"
+
+ATTR{id}=="seeed4micvoicec",ENV{PULSE_PROFILE_SET}="seeed-voicecard-4mic.conf"
+ATTR{id}=="seeed8micvoicec",ENV{PULSE_PROFILE_SET}="seeed-voicecard-8mic.conf"
+
+LABEL="seeedvoicecard_end"
\ No newline at end of file
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/seeed-voicecard/pulseaudio/README.md b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/seeed-voicecard/pulseaudio/README.md
new file mode 100644
index 0000000000000000000000000000000000000000..11e6f45e62de73d3a572a36d4ddf8ca04c1a813f
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/seeed-voicecard/pulseaudio/README.md
@@ -0,0 +1,251 @@
+# PulseAudio Configuration for seeed-voicecard
+
+Follow this guide if you want to use your seeed-voicecard as a default source/sink of pulseaudio.
+
+### Prerequisites
+
+1. Download PulseAudio
+```
+sudo apt install -y pulseaudio
+```
+
+2. PulseAudio Profiles
+```
+cd seeed-voicecard/pulseaudio
+sudo cp pulse_config_4mic/seeed-voicecard.conf /usr/share/pulseaudio/alsa-mixer/profile-sets/seeed-voicecard-4mic.conf
+sudo cp pulse_config_6mic/seeed-voicecard.conf /usr/share/pulseaudio/alsa-mixer/profile-sets/seeed-voicecard-8mic.conf
+```
+
+3. Add `udev` Rules
+
+During the system start, when the card "seeed4micvoicec" is detected, the PULSE_PROFILE_SET variable will be set in the udev database, and PulseAudio will be forced to use `seeed-voicecard-4mic.conf`. Similarly, if the card "seeed8micvoicec" is detected, PulseAudio will be forced to use `seeed-voicecard-8mic.conf`.
+
+```
+sudo cp 91-seeedvoicecard.rules /etc/udev/rules.d/91-seeedvoicecard.rules
+```
+
+### ReSpeaker 4 Mic Array
+
+<!--
+1. Download pulseaudio
+```
+sudo apt install pulseaudio
+```
+
+2. First, you need to write [a profile for pulse](https://www.freedesktop.org/wiki/Software/PulseAudio/Backends/ALSA/Profiles/)
+```
+cd seeed-voicecard
+cd pulseaudio
+cd pulse_config_4mic
+sudo cp seeed-voicecard.conf /usr/share/pulseaudio/alsa-mixer/profile-sets/
+```
+
+3. Edit `udev rules`
+
+    During the system start, when the card "seeed4micvoicec" is detected, the PULSE_PROFILE_SET variable will be set in the udev database, and PulseAudio will be forced to use `seeed-voicecard.conf`.
+
+    ```
+    # have a look at /lib/udev/rules.d/90-pulseaudio.rules
+    sudo vim /lib/udev/rules.d/90-pulseaudio.rules
+    # add the following lines at about line 87(behind the setting for some laptops and before the line GOTO="pulseaudio_end")
+    # Seeed Voicecard
+    ATTR{id}=="seeed4micvoicec",ATTR{number}=="1",ENV{PULSE_PROFILE_SET}="seeed-voicecard.conf"
+    ```
+    ![](./udev_rules_4mic.png)
+
+    The value of `ATTR{number}` can be found with:
+
+    ```
+    udevadm info -a -p /sys/class/sound/card0/
+    # or udevadm info -a -p /sys/class/sound/card1/
+    ```
+
+    For example, in Raspberry Pi, we can find `ATTR{id}=="seeed4micvoicec"` and `ATTR{number}=="1"` with command `udevadm info -a -p /sys/class/sound/card1/`:
+
+    ```
+    pi@raspberrypi:~ $ udevadm info -a -p  /sys/class/sound/card1/
+
+    Udevadm info starts with the device specified by the devpath and then
+    walks up the chain of parent devices. It prints for every device
+    found, all possible attributes in the udev rules key format.
+    A rule to match, can be composed by the attributes of the device
+    and the attributes from one single parent device.
+
+    looking at device '/devices/platform/soc/soc:sound/sound/card1':
+        KERNEL=="card1"
+        SUBSYSTEM=="sound"
+        DRIVER==""
+        ATTR{id}=="seeed4micvoicec"
+        ATTR{number}=="1"
+
+    looking at parent device '/devices/platform/soc/soc:sound':
+        KERNELS=="soc:sound"
+        SUBSYSTEMS=="platform"
+        DRIVERS=="seeed-voicecard"
+        ATTRS{driver_override}=="(null)"
+
+    looking at parent device '/devices/platform/soc':
+        KERNELS=="soc"
+        SUBSYSTEMS=="platform"
+        DRIVERS==""
+        ATTRS{driver_override}=="(null)"
+
+    looking at parent device '/devices/platform':
+        KERNELS=="platform"
+        SUBSYSTEMS==""
+        DRIVERS==""
+    ``` -->
+
+1. config `default.pa` and `daemon.conf`
+```
+sudo cp pulse_config_4mic/default.pa /etc/pulse/
+sudo cp pulse_config_4mic/daemon.conf /etc/pulse/
+```
+
+2. reboot raspberry pi and check
+```
+sudo reboot
+pulseaudio --start  # start pulse at first
+pactl info  # check the setting
+
+Server String: /run/user/1000/pulse/native
+Library Protocol Version: 32
+Server Protocol Version: 32
+Is Local: yes
+Client Index: 18
+Tile Size: 65496
+User Name: pi
+Host Name: raspberrypi
+Server Name: pulseaudio
+Server Version: 10.0
+Default Sample Specification: s16le 4ch 96000Hz
+Default Channel Map: front-left,front-center,front-right,rear-center
+Default Sink: alsa_output.platform-soc_audio.analog-stereo
+Default Source: alsa_input.platform-soc_sound.seeed-source
+Cookie: 3b12:70b3
+```
+
+### 6-Mics Circular Array Kit and 4-Mics Linear Array
+
+<!--
+1. Download pulseaudio
+```
+sudo apt install pulseaudio
+```
+
+2. First, you need to write [a profile for pulse](https://www.freedesktop.org/wiki/Software/PulseAudio/Backends/ALSA/Profiles/)
+```
+cd seeed-voicecard
+cd pulseaudio
+cd pulse_config_6mic
+sudo cp seeed-voicecard.conf /usr/share/pulseaudio/alsa-mixer/profile-sets/
+```
+
+3. Edit `udev rules`
+
+    During the system start, when the card "seeed8micvoicec" is detected, the PULSE_PROFILE_SET variable will be set in the udev database, and PulseAudio will be forced to use `seeed-voicecard.conf`.
+
+    ```
+    # have a look at /lib/udev/rules.d/90-pulseaudio.rules
+    sudo vim /lib/udev/rules.d/90-pulseaudio.rules
+    # add the following lines at about line 87(behind the setting for some laptops and before the line GOTO="pulseaudio_end")
+    # Seeed Voicecard
+    ATTR{id}=="seeed8micvoicec",ATTR{number}=="1",ENV{PULSE_PROFILE_SET}="seeed-voicecard.conf"
+    ```
+    ![](./udev_rules_6mic.png)
+
+    The value of `ATTR{number}` can be found with:
+
+    ```
+    udevadm info -a -p /sys/class/sound/card0/
+    # or udevadm info -a -p /sys/class/sound/card1/
+    ```
+
+    For example, in Raspberry Pi, we can find `ATTR{id}=="seeed8micvoicec"` and `ATTR{number}=="1"` with command `udevadm info -a -p /sys/class/sound/card1/`:
+
+    ```
+    pi@raspberrypi:~ $ udevadm info -a -p  /sys/class/sound/card1/
+
+    Udevadm info starts with the device specified by the devpath and then
+    walks up the chain of parent devices. It prints for every device
+    found, all possible attributes in the udev rules key format.
+    A rule to match, can be composed by the attributes of the device
+    and the attributes from one single parent device.
+
+    looking at device '/devices/platform/soc/soc:sound/sound/card1':
+        KERNEL=="card1"
+        SUBSYSTEM=="sound"
+        DRIVER==""
+        ATTR{id}=="seeed8micvoicec"
+        ATTR{number}=="1"
+
+    looking at parent device '/devices/platform/soc/soc:sound':
+        KERNELS=="soc:sound"
+        SUBSYSTEMS=="platform"
+        DRIVERS=="seeed-voicecard"
+        ATTRS{driver_override}=="(null)"
+
+    looking at parent device '/devices/platform/soc':
+        KERNELS=="soc"
+        SUBSYSTEMS=="platform"
+        DRIVERS==""
+        ATTRS{driver_override}=="(null)"
+
+    looking at parent device '/devices/platform':
+        KERNELS=="platform"
+        SUBSYSTEMS==""
+        DRIVERS==""
+    ``` -->
+
+1. config `default.pa` and `daemon.conf`
+```
+sudo cp pulse_config_6mic/default.pa /etc/pulse/
+sudo cp pulse_config_6mic/daemon.conf /etc/pulse/
+```
+
+2. reboot raspberry pi and check
+```
+sudo reboot
+pulseaudio --start  # start pulse at first
+pactl info  # check the setting
+
+# The output should be like this
+# You could see the default sink is seeed-2ch and default source is seeed-8ch
+pi@raspberrypi:~ $ pactl info
+Server String: /run/user/1000/pulse/native
+Library Protocol Version: 32
+Server Protocol Version: 32
+Is Local: yes
+Client Index: 6
+Tile Size: 65496
+User Name: pi
+Host Name: raspberrypi
+Server Name: pulseaudio
+Server Version: 10.0
+Default Sample Specification: s32le 8ch 96000Hz
+Default Channel Map: front-left,front-left-of-center,front-center,front-right,front-right-of-center,rear-center,aux0,aux1
+Default Sink: alsa_output.platform-soc_sound.seeed-2ch
+Default Source: alsa_input.platform-soc_sound.seeed-8ch
+Cookie: 3523:e5af
+```
+
+### FAQ
+
+1. Default Sink/Source not right
+
+    Make sure there is no any other daemon or using the audio device. Then check profile and udev rules.
+
+    `pacmd list-sinks` and `pacmd list-sources` can be used to show the avaiable sinks/sources, after pulseaudio is started.
+
+2. Can't start PulseAudio
+
+    Check `default.pa` and `daemon.conf`
+
+3. How to get PulseAudio started automatically
+
+    Normally the PulseAudio server is started automatically. If you want to disable it, you can set `autospawn = no` in `~/.config/pulse/client.conf` or `/etc/pulse/client.conf`.
+    [Click this for more details](https://www.freedesktop.org/wiki/Software/PulseAudio/Documentation/User/Running/).
+
+4. Why the default sample rate is 96000? What if my audio's sample rate is not the same as the default?
+
+    For the other sample rate audio, PulseAudio will resample it into 96K, which means that if your audio's sample rate is lower than 96K, it will get smoothing.
\ No newline at end of file
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/seeed-voicecard/pulseaudio/pulse_config_4mic/daemon.conf b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/seeed-voicecard/pulseaudio/pulse_config_4mic/daemon.conf
new file mode 100644
index 0000000000000000000000000000000000000000..d9c5b939c7c99fa2139b6821e29436e3cb58be31
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/seeed-voicecard/pulseaudio/pulse_config_4mic/daemon.conf
@@ -0,0 +1,87 @@
+# This file is part of PulseAudio.
+#
+# PulseAudio is free software; you can redistribute it and/or modify
+# it under the terms of the GNU Lesser General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# PulseAudio is distributed in the hope that it will be useful, but
+# WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+# General Public License for more details.
+#
+# You should have received a copy of the GNU Lesser General Public License
+# along with PulseAudio; if not, see <http://www.gnu.org/licenses/>.
+
+## Configuration file for the PulseAudio daemon. See pulse-daemon.conf(5) for
+## more information. Default values are commented out.  Use either ; or # for
+## commenting.
+
+; daemonize = no
+; fail = yes
+; allow-module-loading = yes
+; allow-exit = yes
+; use-pid-file = yes
+; system-instance = no
+; local-server-type = user
+; enable-shm = yes
+; enable-memfd = yes
+; shm-size-bytes = 0 # setting this 0 will use the system-default, usually 64 MiB
+; lock-memory = no
+; cpu-limit = no
+
+; high-priority = yes
+; nice-level = -11
+
+; realtime-scheduling = yes
+; realtime-priority = 5
+
+; exit-idle-time = 20
+; scache-idle-time = 20
+
+; dl-search-path = (depends on architecture)
+
+; load-default-script-file = yes
+; default-script-file = /etc/pulse/default.pa
+
+; log-target = auto
+; log-level = notice
+; log-meta = no
+; log-time = no
+; log-backtrace = 0
+
+; resample-method = speex-float-1
+; enable-remixing = yes
+; enable-lfe-remixing = no
+; lfe-crossover-freq = 0
+
+; flat-volumes = yes
+
+; rlimit-fsize = -1
+; rlimit-data = -1
+; rlimit-stack = -1
+; rlimit-core = -1
+; rlimit-as = -1
+; rlimit-rss = -1
+; rlimit-nproc = -1
+; rlimit-nofile = 256
+; rlimit-memlock = -1
+; rlimit-locks = -1
+; rlimit-sigpending = -1
+; rlimit-msgqueue = -1
+; rlimit-nice = 31
+; rlimit-rtprio = 9
+; rlimit-rttime = 200000
+
+default-sample-format = s16le
+default-sample-rate = 96000
+; alternate-sample-rate = 48000
+default-sample-channels = 4
+; default-channel-map = front-left,front-right
+
+; default-fragments = 4
+; default-fragment-size-msec = 25
+
+; enable-deferred-volume = yes
+; deferred-volume-safety-margin-usec = 8000
+; deferred-volume-extra-delay-usec = 0
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/seeed-voicecard/pulseaudio/pulse_config_4mic/default.pa b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/seeed-voicecard/pulseaudio/pulse_config_4mic/default.pa
new file mode 100644
index 0000000000000000000000000000000000000000..12915f5a9bb674c377e1840651d6ad0ba819bb38
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/seeed-voicecard/pulseaudio/pulse_config_4mic/default.pa
@@ -0,0 +1,144 @@
+#!/usr/bin/pulseaudio -nF
+#
+# This file is part of PulseAudio.
+#
+# PulseAudio is free software; you can redistribute it and/or modify it
+# under the terms of the GNU Lesser General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# PulseAudio is distributed in the hope that it will be useful, but
+# WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+# General Public License for more details.
+#
+# You should have received a copy of the GNU Lesser General Public License
+# along with PulseAudio; if not, see <http://www.gnu.org/licenses/>.
+
+# This startup script is used only if PulseAudio is started per-user
+# (i.e. not in system mode)
+
+.fail
+
+### Automatically restore the volume of streams and devices
+load-module module-device-restore
+load-module module-stream-restore
+load-module module-card-restore
+
+### Automatically augment property information from .desktop files
+### stored in /usr/share/application
+load-module module-augment-properties
+
+### Should be after module-*-restore but before module-*-detect
+load-module module-switch-on-port-available
+
+### Load audio drivers statically
+### (it's probably better to not load these drivers manually, but instead
+### use module-udev-detect -- see below -- for doing this automatically)
+#load-module module-alsa-sink device="hw:1,0" channels=8 rate=48000 format=s32le
+#load-module module-alsa-source device="hw:1,0" channels=8 rate=48000 format=s32le
+#load-module module-oss device="/dev/dsp" sink_name=output source_name=input
+#load-module module-oss-mmap device="/dev/dsp" sink_name=output source_name=input
+#load-module module-null-sink
+#load-module module-pipe-sink
+
+### Automatically load driver modules depending on the hardware available
+.ifexists module-udev-detect.so
+load-module module-udev-detect 
+#channels=8 rate=48000 format=s32le
+.else
+### Use the static hardware detection module (for systems that lack udev support)
+load-module module-detect
+.endif
+
+### Automatically connect sink and source if JACK server is present
+.ifexists module-jackdbus-detect.so
+.nofail
+load-module module-jackdbus-detect channels=2
+.fail
+.endif
+
+### Automatically load driver modules for Bluetooth hardware
+.ifexists module-bluetooth-policy.so
+load-module module-bluetooth-policy
+.endif
+
+.ifexists module-bluetooth-discover.so
+load-module module-bluetooth-discover
+.endif
+
+### Load several protocols
+.ifexists module-esound-protocol-unix.so
+load-module module-esound-protocol-unix
+.endif
+load-module module-native-protocol-unix
+
+### Network access (may be configured with paprefs, so leave this commented
+### here if you plan to use paprefs)
+#load-module module-esound-protocol-tcp
+#load-module module-native-protocol-tcp
+#load-module module-zeroconf-publish
+
+### Load the RTP receiver module (also configured via paprefs, see above)
+#load-module module-rtp-recv
+
+### Load the RTP sender module (also configured via paprefs, see above)
+#load-module module-null-sink sink_name=rtp format=s16be channels=2 rate=44100 sink_properties="device.description='RTP Multicast Sink'"
+#load-module module-rtp-send source=rtp.monitor
+
+### Load additional modules from GConf settings. This can be configured with the paprefs tool.
+### Please keep in mind that the modules configured by paprefs might conflict with manually
+### loaded modules.
+.ifexists module-gconf.so
+.nofail
+load-module module-gconf
+.fail
+.endif
+
+### Automatically restore the default sink/source when changed by the user
+### during runtime
+### NOTE: This should be loaded as early as possible so that subsequent modules
+### that look up the default sink/source get the right value
+load-module module-default-device-restore
+
+### Automatically move streams to the default sink if the sink they are
+### connected to dies, similar for sources
+load-module module-rescue-streams
+
+### Make sure we always have a sink around, even if it is a null sink.
+load-module module-always-sink
+
+### Honour intended role device property
+load-module module-intended-roles
+
+### Automatically suspend sinks/sources that become idle for too long
+load-module module-suspend-on-idle
+
+### If autoexit on idle is enabled we want to make sure we only quit
+### when no local session needs us anymore.
+.ifexists module-console-kit.so
+load-module module-console-kit
+.endif
+.ifexists module-systemd-login.so
+load-module module-systemd-login
+.endif
+
+### Enable positioned event sounds
+load-module module-position-event-sounds
+
+### Cork music/video streams when a phone stream is active
+load-module module-role-cork
+
+### Modules to allow autoloading of filters (such as echo cancellation)
+### on demand. module-filter-heuristics tries to determine what filters
+### make sense, and module-filter-apply does the heavy-lifting of
+### loading modules and rerouting streams.
+load-module module-filter-heuristics
+load-module module-filter-apply
+
+### Make some devices default
+#set-default-sink output
+#set-default-source input
+set-default-source alsa_input.platform-soc_sound.seeed-source
+set-default-sink alsa_output.platform-soc_sound.seeed-sink
+
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/seeed-voicecard/pulseaudio/pulse_config_4mic/seeed-voicecard.conf b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/seeed-voicecard/pulseaudio/pulse_config_4mic/seeed-voicecard.conf
new file mode 100644
index 0000000000000000000000000000000000000000..1c35e17131382969f2546e3259d4da82551fdb0b
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/seeed-voicecard/pulseaudio/pulse_config_4mic/seeed-voicecard.conf
@@ -0,0 +1,17 @@
+# /usr/share/pulseaudio/alsa-mixer/profile-sets/seeed-voicecard.conf
+
+[General]
+auto-profiles = no
+[Mapping seeed-source]
+device-strings = hw:%f
+channel-map = front-left,front-right,rear-left,rear-right
+exact-channels = false
+fallback = yes
+paths-input = seeed-source
+priority = 3
+direction = input
+
+[Profile input:seeed-source]
+input-mappings = seeed-source
+priority = 5
+skip-probe = yes
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/seeed-voicecard/pulseaudio/pulse_config_6mic/daemon.conf b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/seeed-voicecard/pulseaudio/pulse_config_6mic/daemon.conf
new file mode 100644
index 0000000000000000000000000000000000000000..89a7c9f3102c3e34e711a678c73bb29809d7e0aa
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/seeed-voicecard/pulseaudio/pulse_config_6mic/daemon.conf
@@ -0,0 +1,87 @@
+# This file is part of PulseAudio.
+#
+# PulseAudio is free software; you can redistribute it and/or modify
+# it under the terms of the GNU Lesser General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# PulseAudio is distributed in the hope that it will be useful, but
+# WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+# General Public License for more details.
+#
+# You should have received a copy of the GNU Lesser General Public License
+# along with PulseAudio; if not, see <http://www.gnu.org/licenses/>.
+
+## Configuration file for the PulseAudio daemon. See pulse-daemon.conf(5) for
+## more information. Default values are commented out.  Use either ; or # for
+## commenting.
+
+; daemonize = no
+; fail = yes
+; allow-module-loading = yes
+; allow-exit = yes
+; use-pid-file = yes
+; system-instance = no
+; local-server-type = user
+; enable-shm = yes
+; enable-memfd = yes
+; shm-size-bytes = 0 # setting this 0 will use the system-default, usually 64 MiB
+; lock-memory = no
+; cpu-limit = no
+
+; high-priority = yes
+; nice-level = -11
+
+; realtime-scheduling = yes
+; realtime-priority = 5
+
+; exit-idle-time = 20
+; scache-idle-time = 20
+
+; dl-search-path = (depends on architecture)
+
+; load-default-script-file = yes
+; default-script-file = /etc/pulse/default.pa
+
+; log-target = auto
+; log-level = notice
+; log-meta = no
+; log-time = no
+; log-backtrace = 0
+
+; resample-method = speex-float-1
+; enable-remixing = yes
+; enable-lfe-remixing = no
+; lfe-crossover-freq = 0
+
+; flat-volumes = yes
+
+; rlimit-fsize = -1
+; rlimit-data = -1
+; rlimit-stack = -1
+; rlimit-core = -1
+; rlimit-as = -1
+; rlimit-rss = -1
+; rlimit-nproc = -1
+; rlimit-nofile = 256
+; rlimit-memlock = -1
+; rlimit-locks = -1
+; rlimit-sigpending = -1
+; rlimit-msgqueue = -1
+; rlimit-nice = 31
+; rlimit-rtprio = 9
+; rlimit-rttime = 200000
+
+default-sample-format = s32le
+default-sample-rate = 96000
+; alternate-sample-rate = 48000
+default-sample-channels = 8
+; default-channel-map = front-left,front-right
+
+; default-fragments = 4
+; default-fragment-size-msec = 25
+
+; enable-deferred-volume = yes
+; deferred-volume-safety-margin-usec = 8000
+; deferred-volume-extra-delay-usec = 0
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/seeed-voicecard/pulseaudio/pulse_config_6mic/default.pa b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/seeed-voicecard/pulseaudio/pulse_config_6mic/default.pa
new file mode 100644
index 0000000000000000000000000000000000000000..aed78bda859ef916e44b89873c983a65e284cecc
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/seeed-voicecard/pulseaudio/pulse_config_6mic/default.pa
@@ -0,0 +1,143 @@
+#!/usr/bin/pulseaudio -nF
+#
+# This file is part of PulseAudio.
+#
+# PulseAudio is free software; you can redistribute it and/or modify it
+# under the terms of the GNU Lesser General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# PulseAudio is distributed in the hope that it will be useful, but
+# WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+# General Public License for more details.
+#
+# You should have received a copy of the GNU Lesser General Public License
+# along with PulseAudio; if not, see <http://www.gnu.org/licenses/>.
+
+# This startup script is used only if PulseAudio is started per-user
+# (i.e. not in system mode)
+
+.fail
+
+### Automatically restore the volume of streams and devices
+load-module module-device-restore
+load-module module-stream-restore
+load-module module-card-restore
+
+### Automatically augment property information from .desktop files
+### stored in /usr/share/application
+load-module module-augment-properties
+
+### Should be after module-*-restore but before module-*-detect
+load-module module-switch-on-port-available
+
+### Load audio drivers statically
+### (it's probably better to not load these drivers manually, but instead
+### use module-udev-detect -- see below -- for doing this automatically)
+#load-module module-alsa-sink device="hw:1,0" channels=8 rate=48000 format=s32le
+#load-module module-alsa-source device="hw:1,0" channels=8 rate=48000 format=s32le
+#load-module module-oss device="/dev/dsp" sink_name=output source_name=input
+#load-module module-oss-mmap device="/dev/dsp" sink_name=output source_name=input
+#load-module module-null-sink
+#load-module module-pipe-sink
+
+### Automatically load driver modules depending on the hardware available
+.ifexists module-udev-detect.so
+load-module module-udev-detect 
+#channels=8 rate=48000 format=s32le
+.else
+### Use the static hardware detection module (for systems that lack udev support)
+load-module module-detect
+.endif
+
+### Automatically connect sink and source if JACK server is present
+.ifexists module-jackdbus-detect.so
+.nofail
+load-module module-jackdbus-detect channels=2
+.fail
+.endif
+
+### Automatically load driver modules for Bluetooth hardware
+.ifexists module-bluetooth-policy.so
+load-module module-bluetooth-policy
+.endif
+
+.ifexists module-bluetooth-discover.so
+load-module module-bluetooth-discover
+.endif
+
+### Load several protocols
+.ifexists module-esound-protocol-unix.so
+load-module module-esound-protocol-unix
+.endif
+load-module module-native-protocol-unix
+
+### Network access (may be configured with paprefs, so leave this commented
+### here if you plan to use paprefs)
+#load-module module-esound-protocol-tcp
+#load-module module-native-protocol-tcp
+#load-module module-zeroconf-publish
+
+### Load the RTP receiver module (also configured via paprefs, see above)
+#load-module module-rtp-recv
+
+### Load the RTP sender module (also configured via paprefs, see above)
+#load-module module-null-sink sink_name=rtp format=s16be channels=2 rate=44100 sink_properties="device.description='RTP Multicast Sink'"
+#load-module module-rtp-send source=rtp.monitor
+
+### Load additional modules from GConf settings. This can be configured with the paprefs tool.
+### Please keep in mind that the modules configured by paprefs might conflict with manually
+### loaded modules.
+.ifexists module-gconf.so
+.nofail
+load-module module-gconf
+.fail
+.endif
+
+### Automatically restore the default sink/source when changed by the user
+### during runtime
+### NOTE: This should be loaded as early as possible so that subsequent modules
+### that look up the default sink/source get the right value
+load-module module-default-device-restore
+
+### Automatically move streams to the default sink if the sink they are
+### connected to dies, similar for sources
+load-module module-rescue-streams
+
+### Make sure we always have a sink around, even if it is a null sink.
+load-module module-always-sink
+
+### Honour intended role device property
+load-module module-intended-roles
+
+### Automatically suspend sinks/sources that become idle for too long
+load-module module-suspend-on-idle
+
+### If autoexit on idle is enabled we want to make sure we only quit
+### when no local session needs us anymore.
+.ifexists module-console-kit.so
+load-module module-console-kit
+.endif
+.ifexists module-systemd-login.so
+load-module module-systemd-login
+.endif
+
+### Enable positioned event sounds
+load-module module-position-event-sounds
+
+### Cork music/video streams when a phone stream is active
+load-module module-role-cork
+
+### Modules to allow autoloading of filters (such as echo cancellation)
+### on demand. module-filter-heuristics tries to determine what filters
+### make sense, and module-filter-apply does the heavy-lifting of
+### loading modules and rerouting streams.
+load-module module-filter-heuristics
+load-module module-filter-apply
+
+### Make some devices default
+#set-default-sink output
+#set-default-source input
+set-default-source alsa_input.platform-soc_sound.seeed-8ch
+set-default-sink alsa_output.platform-soc_sound.seeed-2ch
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/seeed-voicecard/pulseaudio/pulse_config_6mic/seeed-voicecard.conf b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/seeed-voicecard/pulseaudio/pulse_config_6mic/seeed-voicecard.conf
new file mode 100644
index 0000000000000000000000000000000000000000..282a646540cd2e928e46ef4abfe051456f9657b1
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/seeed-voicecard/pulseaudio/pulse_config_6mic/seeed-voicecard.conf
@@ -0,0 +1,34 @@
+# /usr/share/pulseaudio/alsa-mixer/profile-sets/seeed-voiced.conf
+
+[General]
+auto-profiles = no
+[Mapping seeed-8ch]
+device-strings = hw:%f
+channel-map = front-left,front-right,rear-left,rear-right,front-center,lfe,side-left,side-right
+exact-channels = false
+fallback = yes
+paths-input = seeed-8ch
+priority = 3
+direction = input
+[Mapping seeed-2ch]
+device-strings = hw:%f
+channel-map = front-left,front-right,rear-left,rear-right,front-center,lfe,side-left,side-right
+exact-channels = false
+exact-channels = false
+fallback = yes
+paths-output = seeed-2ch
+direction = output
+priority = 2
+[Profile output:seeed-2ch+input:seeed-8ch]
+output-mappings = seeed-2ch
+input-mappings = seeed-8ch
+priority = 100
+skip-probe = yes
+[Profile output:seeed-2ch]
+output-mappings = seeed-2ch
+priority = 4
+skip-probe = yes
+[Profile input:seeed-8ch]
+input-mappings = seeed-8ch
+priority = 5
+skip-probe = yes
\ No newline at end of file
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/seeed-voicecard/pulseaudio/udev_rules_4mic.png b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/seeed-voicecard/pulseaudio/udev_rules_4mic.png
new file mode 100644
index 0000000000000000000000000000000000000000..dd585ec7294823af63b25376a813ba302daa6426
Binary files /dev/null and b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/seeed-voicecard/pulseaudio/udev_rules_4mic.png differ
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/seeed-voicecard/pulseaudio/udev_rules_6mic.png b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/seeed-voicecard/pulseaudio/udev_rules_6mic.png
new file mode 100644
index 0000000000000000000000000000000000000000..ec2d81f8b62708734bd05e9e2092be4cc9f64843
Binary files /dev/null and b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/seeed-voicecard/pulseaudio/udev_rules_6mic.png differ
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/seeed-voicecard/seeed-voicecard b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/seeed-voicecard/seeed-voicecard
new file mode 100644
index 0000000000000000000000000000000000000000..047474e42838f5e0ab4cd051cdf2dbac995f09ac
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/seeed-voicecard/seeed-voicecard
@@ -0,0 +1,147 @@
+#!/bin/bash
+#
+# Copyright (c) 2018 Baozhu Zuo <zuobaozhu@gmail.com>
+#
+# Permission is hereby granted, free of charge, to any person obtaining a copy
+# of this software and associated documentation files (the "Software"), to deal
+# in the Software without restriction, including without limitation the rights
+# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+# copies of the Software, and to permit persons to whom the Software is
+# furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+# THE SOFTWARE.
+
+set -x
+exec 1>/var/log/$(basename $0).log 2>&1
+#enable i2c interface
+dtparam i2c_arm=on
+modprobe i2c-dev
+
+#enable spi interface
+dtparam spi=on
+
+_VER_RUN=
+function get_kernel_version() {
+    local ZIMAGE IMG_OFFSET
+
+    _VER_RUN=""
+    [ -z "$_VER_RUN" ] && {
+        ZIMAGE=/boot/kernel.img
+        IMG_OFFSET=$(LC_ALL=C grep -abo $'\x1f\x8b\x08\x00' $ZIMAGE | head -n 1 | cut -d ':' -f 1)
+        _VER_RUN=$(dd if=$ZIMAGE obs=64K ibs=4 skip=$(( IMG_OFFSET / 4)) | zcat | grep -a -m1 "Linux version" | strings | awk '{ print $3; }')
+    }
+    echo "$_VER_RUN"
+    return 0
+}
+
+CONFIG=/boot/config.txt
+get_overlay() {
+    ov=$1
+    if grep -q -E "^dtoverlay=$ov" $CONFIG; then
+      echo 0
+    else
+      echo 1
+    fi
+}
+
+do_overlay() {
+    ov=$1
+    RET=$2
+    DEFAULT=--defaultno
+    CURRENT=0
+    if [ $(get_overlay $ov) -eq 0 ]; then
+        DEFAULT=
+        CURRENT=1
+    fi
+    if [ $RET -eq $CURRENT ]; then
+        ASK_TO_REBOOT=1
+    fi
+    if [ $RET -eq 0 ]; then
+        sed $CONFIG -i -e "s/^#dtoverlay=$ov/dtoverlay=$ov/"
+        if ! grep -q -E "^dtoverlay=$ov" $CONFIG; then
+            printf "dtoverlay=$ov\n" >> $CONFIG
+        fi
+        STATUS=enabled
+    elif [ $RET -eq 1 ]; then
+        sed $CONFIG -i -e "s/^dtoverlay=$ov/#dtoverlay=$ov/"
+        STATUS=disabled
+    else
+        return $RET
+    fi
+}
+
+
+is_1a=$(i2cdetect -y  1 0x1a 0x1a | egrep "(1a|UU)" | awk '{print $2}')
+is_35=$(i2cdetect -y  1 0x35 0x35 | egrep "(35|UU)" | awk '{print $2}')
+is_3b=$(i2cdetect -y  1 0x3b 0x3b | egrep "(3b|UU)" | awk '{print $2}')
+
+RPI_HATS="seeed-2mic-voicecard seeed-4mic-voicecard seeed-8mic-voicecard"
+overlay=""
+
+if [ "x${is_1a}" != "x" ] && [ "x${is_35}" == "x" ] ; then
+    echo "install 2mic"
+    overlay=seeed-2mic-voicecard
+    asound_conf=/etc/voicecard/asound_2mic.conf
+    asound_state=/etc/voicecard/wm8960_asound.state
+fi
+
+if [ "x${is_3b}" != "x" ] && [ "x${is_35}" == "x" ] ; then
+    echo "install 4mic"
+    overlay=seeed-4mic-voicecard
+    asound_conf=/etc/voicecard/asound_4mic.conf
+    asound_state=/etc/voicecard/ac108_asound.state
+fi
+
+if [ "x${is_3b}" != "x" ] && [ "x${is_35}" != "x" ] ; then
+    echo "install 6mic"
+    overlay=seeed-8mic-voicecard
+    asound_conf=/etc/voicecard/asound_6mic.conf
+    asound_state=/etc/voicecard/ac108_6mic.state
+fi
+
+if [ "$overlay" ]; then
+    echo Install $overlay ...
+
+    # Remove old configuration
+    rm /etc/asound.conf
+    rm /var/lib/alsa/asound.state
+
+    kernel_ver=$(get_kernel_version)
+    # echo kernel_ver=$kernel_ver
+
+    # TODO: dynamic dtoverlay Bug of v4.19.x
+    #       no DT node phandle inserted.
+    if [[ "$kernel_ver" =~ ^4\.19.*$ ]]; then
+        for i in $RPI_HATS; do
+            if [ "$i" == "$overlay" ]; then
+                do_overlay $overlay 0
+            else
+                echo Uninstall $i ...
+                do_overlay $i 1
+            fi
+        done
+    fi
+    #make sure the driver loads correctly
+    dtoverlay $overlay || true
+
+
+    echo "create $overlay asound configure file"
+    ln -s $asound_conf /etc/asound.conf
+    echo "create $overlay asound status file"
+    ln -s $asound_state /var/lib/alsa/asound.state
+fi
+
+alsactl restore
+
+#Fore 3.5mm ('headphone') jack
+amixer cset numid=3 1 
+
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/seeed-voicecard/seeed-voicecard.c b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/seeed-voicecard/seeed-voicecard.c
new file mode 100644
index 0000000000000000000000000000000000000000..f08fbd8728306b32eb1576228907513c73febebb
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/seeed-voicecard/seeed-voicecard.c
@@ -0,0 +1,652 @@
+/*
+ * SEEED voice card
+ *
+ * (C) Copyright 2017-2018
+ * Seeed Technology Co., Ltd. <www.seeedstudio.com>
+ *
+ * base on ASoC simple sound card support
+ *
+ * Copyright (C) 2012 Renesas Solutions Corp.
+ * Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/* #undef DEBUG */
+#include <linux/version.h>
+#include <linux/clk.h>
+#include <linux/device.h>
+#include <linux/gpio.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_gpio.h>
+#include <linux/platform_device.h>
+#include <linux/string.h>
+#include <sound/soc.h>
+#include <sound/soc-dai.h>
+#include <sound/simple_card_utils.h>
+#include "ac10x.h"
+
+/*
+ * single codec:
+ *	0 - allow multi codec
+ *	1 - yes
+ */
+#define _SINGLE_CODEC		1
+
+struct seeed_card_data {
+	struct snd_soc_card snd_card;
+	struct seeed_dai_props {
+		struct asoc_simple_dai cpu_dai;
+		struct asoc_simple_dai codec_dai;
+		unsigned int mclk_fs;
+	} *dai_props;
+	unsigned int mclk_fs;
+	unsigned channels_playback_default;
+	unsigned channels_playback_override;
+	unsigned channels_capture_default;
+	unsigned channels_capture_override;
+	struct snd_soc_dai_link *dai_link;
+	#if CONFIG_AC10X_TRIG_LOCK
+	spinlock_t lock;
+	#endif
+	struct work_struct work_codec_clk;
+	#define TRY_STOP_MAX	3
+	int try_stop;
+};
+
+struct seeed_card_info {
+	const char *name;
+	const char *card;
+	const char *codec;
+	const char *platform;
+
+	unsigned int daifmt;
+	struct asoc_simple_dai cpu_dai;
+	struct asoc_simple_dai codec_dai;
+};
+
+#define seeed_priv_to_dev(priv) ((priv)->snd_card.dev)
+#define seeed_priv_to_link(priv, i) ((priv)->snd_card.dai_link + (i))
+#define seeed_priv_to_props(priv, i) ((priv)->dai_props + (i))
+
+#define DAI	"sound-dai"
+#define CELL	"#sound-dai-cells"
+#define PREFIX	"seeed-voice-card,"
+
+static int seeed_voice_card_startup(struct snd_pcm_substream *substream)
+{
+	struct snd_soc_pcm_runtime *rtd = substream->private_data;
+	struct seeed_card_data *priv =	snd_soc_card_get_drvdata(rtd->card);
+	struct seeed_dai_props *dai_props =
+		seeed_priv_to_props(priv, rtd->num);
+	int ret;
+
+	ret = clk_prepare_enable(dai_props->cpu_dai.clk);
+	if (ret)
+		return ret;
+
+	ret = clk_prepare_enable(dai_props->codec_dai.clk);
+	if (ret)
+		clk_disable_unprepare(dai_props->cpu_dai.clk);
+
+	if (rtd->cpu_dai->driver->playback.channels_min) {
+		priv->channels_playback_default = rtd->cpu_dai->driver->playback.channels_min;
+	}
+	if (rtd->cpu_dai->driver->capture.channels_min) {
+		priv->channels_capture_default = rtd->cpu_dai->driver->capture.channels_min;
+	}
+	rtd->cpu_dai->driver->playback.channels_min = priv->channels_playback_override;
+	rtd->cpu_dai->driver->playback.channels_max = priv->channels_playback_override;
+	rtd->cpu_dai->driver->capture.channels_min = priv->channels_capture_override;
+	rtd->cpu_dai->driver->capture.channels_max = priv->channels_capture_override;
+
+	return ret;
+}
+
+static void seeed_voice_card_shutdown(struct snd_pcm_substream *substream)
+{
+	struct snd_soc_pcm_runtime *rtd = substream->private_data;
+	struct seeed_card_data *priv =	snd_soc_card_get_drvdata(rtd->card);
+	struct seeed_dai_props *dai_props =
+		seeed_priv_to_props(priv, rtd->num);
+
+	rtd->cpu_dai->driver->playback.channels_min = priv->channels_playback_default;
+	rtd->cpu_dai->driver->playback.channels_max = priv->channels_playback_default;
+	rtd->cpu_dai->driver->capture.channels_min = priv->channels_capture_default;
+	rtd->cpu_dai->driver->capture.channels_max = priv->channels_capture_default;
+
+	clk_disable_unprepare(dai_props->cpu_dai.clk);
+
+	clk_disable_unprepare(dai_props->codec_dai.clk);
+}
+
+static int seeed_voice_card_hw_params(struct snd_pcm_substream *substream,
+				      struct snd_pcm_hw_params *params)
+{
+	struct snd_soc_pcm_runtime *rtd = substream->private_data;
+	struct snd_soc_dai *codec_dai = rtd->codec_dai;
+	struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
+	struct seeed_card_data *priv = snd_soc_card_get_drvdata(rtd->card);
+	struct seeed_dai_props *dai_props =
+		seeed_priv_to_props(priv, rtd->num);
+	unsigned int mclk, mclk_fs = 0;
+	int ret = 0;
+
+	if (priv->mclk_fs)
+		mclk_fs = priv->mclk_fs;
+	else if (dai_props->mclk_fs)
+		mclk_fs = dai_props->mclk_fs;
+
+	if (mclk_fs) {
+		mclk = params_rate(params) * mclk_fs;
+		ret = snd_soc_dai_set_sysclk(codec_dai, 0, mclk,
+					     SND_SOC_CLOCK_IN);
+		if (ret && ret != -ENOTSUPP)
+			goto err;
+
+		ret = snd_soc_dai_set_sysclk(cpu_dai, 0, mclk,
+					     SND_SOC_CLOCK_OUT);
+		if (ret && ret != -ENOTSUPP)
+			goto err;
+	}
+	return 0;
+err:
+	return ret;
+}
+
+#define _SET_CLOCK_CNT		2
+static int (* _set_clock[_SET_CLOCK_CNT])(int y_start_n_stop);
+
+int seeed_voice_card_register_set_clock(int stream, int (*set_clock)(int)) {
+	if (! _set_clock[stream]) {
+		_set_clock[stream] = set_clock;
+	}
+	return 0;
+}
+EXPORT_SYMBOL(seeed_voice_card_register_set_clock);
+
+/*
+ * work_cb_codec_clk: clear audio codec inner clock.
+ */
+static void work_cb_codec_clk(struct work_struct *work)
+{
+	struct seeed_card_data *priv = container_of(work, struct seeed_card_data, work_codec_clk);
+	int r = 0;
+
+	if (_set_clock[SNDRV_PCM_STREAM_CAPTURE]) {
+		r = r || _set_clock[SNDRV_PCM_STREAM_CAPTURE](0);
+	}
+	if (_set_clock[SNDRV_PCM_STREAM_PLAYBACK]) {
+		r = r || _set_clock[SNDRV_PCM_STREAM_PLAYBACK](0);
+	}
+
+	if (r && priv->try_stop++ < TRY_STOP_MAX) {
+		if (0 != schedule_work(&priv->work_codec_clk)) {}
+	}
+	return;
+}
+
+static int seeed_voice_card_trigger(struct snd_pcm_substream *substream, int cmd)
+{
+	struct snd_soc_pcm_runtime *rtd = substream->private_data;
+	struct snd_soc_dai *dai = rtd->codec_dai;
+	struct seeed_card_data *priv = snd_soc_card_get_drvdata(rtd->card);
+	#if CONFIG_AC10X_TRIG_LOCK
+	unsigned long flags;
+	#endif
+	int ret = 0;
+
+	dev_dbg(rtd->card->dev, "%s() stream=%s  cmd=%d play:%d, capt:%d\n",
+		__FUNCTION__, snd_pcm_stream_str(substream), cmd,
+		dai->playback_active, dai->capture_active);
+
+	switch (cmd) {
+	case SNDRV_PCM_TRIGGER_START:
+	case SNDRV_PCM_TRIGGER_RESUME:
+	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
+		if (cancel_work_sync(&priv->work_codec_clk) != 0) {}
+		#if CONFIG_AC10X_TRIG_LOCK
+		/* I know it will degrades performance, but I have no choice */
+		spin_lock_irqsave(&priv->lock, flags);
+		#endif
+		if (_set_clock[SNDRV_PCM_STREAM_CAPTURE]) _set_clock[SNDRV_PCM_STREAM_CAPTURE](1);
+		if (_set_clock[SNDRV_PCM_STREAM_PLAYBACK]) _set_clock[SNDRV_PCM_STREAM_PLAYBACK](1);
+		#if CONFIG_AC10X_TRIG_LOCK
+		spin_unlock_irqrestore(&priv->lock, flags);
+		#endif
+		break;
+
+	case SNDRV_PCM_TRIGGER_STOP:
+	case SNDRV_PCM_TRIGGER_SUSPEND:
+	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
+		/* capture channel resync, if overrun */
+		if (dai->capture_active && substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+			break;
+		}
+
+		/* interrupt environment */
+		if (in_irq() || in_nmi() || in_serving_softirq()) {
+			priv->try_stop = 0;
+			if (0 != schedule_work(&priv->work_codec_clk)) {
+			}
+		} else {
+			if (_set_clock[SNDRV_PCM_STREAM_CAPTURE]) _set_clock[SNDRV_PCM_STREAM_CAPTURE](0);
+			if (_set_clock[SNDRV_PCM_STREAM_PLAYBACK]) _set_clock[SNDRV_PCM_STREAM_PLAYBACK](0);
+		}
+		break;
+	default:
+		ret = -EINVAL;
+	}
+
+	return ret;
+}
+
+static struct snd_soc_ops seeed_voice_card_ops = {
+	.startup = seeed_voice_card_startup,
+	.shutdown = seeed_voice_card_shutdown,
+	.hw_params = seeed_voice_card_hw_params,
+	.trigger = seeed_voice_card_trigger,
+};
+
+static int seeed_voice_card_dai_init(struct snd_soc_pcm_runtime *rtd)
+{
+	struct seeed_card_data *priv =	snd_soc_card_get_drvdata(rtd->card);
+	struct snd_soc_dai *codec = rtd->codec_dai;
+	struct snd_soc_dai *cpu = rtd->cpu_dai;
+	struct seeed_dai_props *dai_props =
+		seeed_priv_to_props(priv, rtd->num);
+	int ret;
+
+	ret = asoc_simple_card_init_dai(codec, &dai_props->codec_dai);
+	if (ret < 0)
+		return ret;
+
+	ret = asoc_simple_card_init_dai(cpu, &dai_props->cpu_dai);
+	if (ret < 0)
+		return ret;
+
+	return 0;
+}
+
+static int seeed_voice_card_dai_link_of(struct device_node *node,
+					struct seeed_card_data *priv,
+					int idx,
+					bool is_top_level_node)
+{
+	struct device *dev = seeed_priv_to_dev(priv);
+	struct snd_soc_dai_link *dai_link = seeed_priv_to_link(priv, idx);
+	struct seeed_dai_props *dai_props = seeed_priv_to_props(priv, idx);
+	struct asoc_simple_dai *cpu_dai = &dai_props->cpu_dai;
+	struct asoc_simple_dai *codec_dai = &dai_props->codec_dai;
+	struct device_node *cpu = NULL;
+	struct device_node *plat = NULL;
+	struct device_node *codec = NULL;
+	char prop[128];
+	char *prefix = "";
+	int ret, single_cpu;
+
+	/* For single DAI link & old style of DT node */
+	if (is_top_level_node)
+		prefix = PREFIX;
+
+	snprintf(prop, sizeof(prop), "%scpu", prefix);
+	cpu = of_get_child_by_name(node, prop);
+
+	if (!cpu) {
+		ret = -EINVAL;
+		dev_err(dev, "%s: Can't find %s DT node\n", __func__, prop);
+		goto dai_link_of_err;
+	}
+
+	snprintf(prop, sizeof(prop), "%splat", prefix);
+	plat = of_get_child_by_name(node, prop);
+
+	snprintf(prop, sizeof(prop), "%scodec", prefix);
+	codec = of_get_child_by_name(node, prop);
+
+	if (!codec) {
+		ret = -EINVAL;
+		dev_err(dev, "%s: Can't find %s DT node\n", __func__, prop);
+		goto dai_link_of_err;
+	}
+
+	ret = asoc_simple_card_parse_daifmt(dev, node, codec,
+					    prefix, &dai_link->dai_fmt);
+	if (ret < 0)
+		goto dai_link_of_err;
+
+	of_property_read_u32(node, "mclk-fs", &dai_props->mclk_fs);
+
+	ret = asoc_simple_card_parse_cpu(cpu, dai_link,
+					 DAI, CELL, &single_cpu);
+	if (ret < 0)
+		goto dai_link_of_err;
+
+	#if _SINGLE_CODEC
+	ret = asoc_simple_card_parse_codec(codec, dai_link, DAI, CELL);
+	if (ret < 0)
+		goto dai_link_of_err;
+	#else
+	ret = snd_soc_of_get_dai_link_codecs(dev, codec, dai_link);
+	if (ret < 0) {
+		dev_err(dev, "parse codec info error %d\n", ret);
+		goto dai_link_of_err;
+	}
+	dev_dbg(dev, "dai_link num_codecs = %d\n", dai_link->num_codecs);
+	#endif
+
+	ret = asoc_simple_card_parse_platform(plat, dai_link, DAI, CELL);
+	if (ret < 0)
+		goto dai_link_of_err;
+
+	ret = snd_soc_of_parse_tdm_slot(cpu,	&cpu_dai->tx_slot_mask,
+						&cpu_dai->rx_slot_mask,
+						&cpu_dai->slots,
+						&cpu_dai->slot_width);
+	dev_dbg(dev, "cpu_dai : slot,width,tx,rx = %d,%d,%d,%d\n", 
+			cpu_dai->slots, cpu_dai->slot_width,
+			cpu_dai->tx_slot_mask, cpu_dai->rx_slot_mask
+			);
+	if (ret < 0)
+		goto dai_link_of_err;
+
+	ret = snd_soc_of_parse_tdm_slot(codec,	&codec_dai->tx_slot_mask,
+						&codec_dai->rx_slot_mask,
+						&codec_dai->slots,
+						&codec_dai->slot_width);
+	if (ret < 0)
+		goto dai_link_of_err;
+
+	#if LINUX_VERSION_CODE <= KERNEL_VERSION(4,10,0)
+	ret = asoc_simple_card_parse_clk_cpu(cpu, dai_link, cpu_dai);
+	#else
+	ret = asoc_simple_card_parse_clk_cpu(dev, cpu, dai_link, cpu_dai);
+	#endif
+	if (ret < 0)
+		goto dai_link_of_err;
+
+	#if LINUX_VERSION_CODE <= KERNEL_VERSION(4,10,0)
+	ret = asoc_simple_card_parse_clk_codec(codec, dai_link, codec_dai);
+	#else
+	ret = asoc_simple_card_parse_clk_codec(dev, codec, dai_link, codec_dai);
+	#endif
+	if (ret < 0)
+		goto dai_link_of_err;
+
+	#if _SINGLE_CODEC
+	ret = asoc_simple_card_canonicalize_dailink(dai_link);
+	if (ret < 0)
+		goto dai_link_of_err;
+	#endif
+
+	ret = asoc_simple_card_set_dailink_name(dev, dai_link,
+						"%s-%s",
+						dai_link->cpu_dai_name,
+						#if _SINGLE_CODEC
+						dai_link->codec_dai_name
+						#else
+						dai_link->codecs[0].dai_name
+						#endif
+	);
+	if (ret < 0)
+		goto dai_link_of_err;
+
+	dai_link->ops = &seeed_voice_card_ops;
+	dai_link->init = seeed_voice_card_dai_init;
+
+	dev_dbg(dev, "\tname : %s\n", dai_link->stream_name);
+	dev_dbg(dev, "\tformat : %04x\n", dai_link->dai_fmt);
+	dev_dbg(dev, "\tcpu : %s / %d\n",
+		dai_link->cpu_dai_name,
+		dai_props->cpu_dai.sysclk);
+	dev_dbg(dev, "\tcodec : %s / %d\n",
+		#if _SINGLE_CODEC
+		dai_link->codec_dai_name,
+		#else
+		dai_link->codecs[0].dai_name,
+		#endif
+		dai_props->codec_dai.sysclk);
+
+	asoc_simple_card_canonicalize_cpu(dai_link, single_cpu);
+
+dai_link_of_err:
+	of_node_put(cpu);
+	of_node_put(codec);
+
+	return ret;
+}
+
+static int seeed_voice_card_parse_aux_devs(struct device_node *node,
+					   struct seeed_card_data *priv)
+{
+	struct device *dev = seeed_priv_to_dev(priv);
+	struct device_node *aux_node;
+	int i, n, len;
+
+	if (!of_find_property(node, PREFIX "aux-devs", &len))
+		return 0;		/* Ok to have no aux-devs */
+
+	n = len / sizeof(__be32);
+	if (n <= 0)
+		return -EINVAL;
+
+	priv->snd_card.aux_dev = devm_kzalloc(dev,
+			n * sizeof(*priv->snd_card.aux_dev), GFP_KERNEL);
+	if (!priv->snd_card.aux_dev)
+		return -ENOMEM;
+
+	for (i = 0; i < n; i++) {
+		aux_node = of_parse_phandle(node, PREFIX "aux-devs", i);
+		if (!aux_node)
+			return -EINVAL;
+		priv->snd_card.aux_dev[i].codec_of_node = aux_node;
+	}
+
+	priv->snd_card.num_aux_devs = n;
+	return 0;
+}
+
+static int seeed_voice_card_parse_of(struct device_node *node,
+				     struct seeed_card_data *priv)
+{
+	struct device *dev = seeed_priv_to_dev(priv);
+	struct device_node *dai_link;
+	int ret;
+
+	if (!node)
+		return -EINVAL;
+
+	dai_link = of_get_child_by_name(node, PREFIX "dai-link");
+
+	/* The off-codec widgets */
+	if (of_property_read_bool(node, PREFIX "widgets")) {
+		ret = snd_soc_of_parse_audio_simple_widgets(&priv->snd_card,
+					PREFIX "widgets");
+		if (ret)
+			goto card_parse_end;
+	}
+
+	/* DAPM routes */
+	if (of_property_read_bool(node, PREFIX "routing")) {
+		ret = snd_soc_of_parse_audio_routing(&priv->snd_card,
+					PREFIX "routing");
+		if (ret)
+			goto card_parse_end;
+	}
+
+	/* Factor to mclk, used in hw_params() */
+	of_property_read_u32(node, PREFIX "mclk-fs", &priv->mclk_fs);
+
+	/* Single/Muti DAI link(s) & New style of DT node */
+	if (dai_link) {
+		struct device_node *np = NULL;
+		int i = 0;
+
+		for_each_child_of_node(node, np) {
+			dev_dbg(dev, "\tlink %d:\n", i);
+			ret = seeed_voice_card_dai_link_of(np, priv,
+							   i, false);
+			if (ret < 0) {
+				of_node_put(np);
+				goto card_parse_end;
+			}
+			i++;
+		}
+	} else {
+		/* For single DAI link & old style of DT node */
+		ret = seeed_voice_card_dai_link_of(node, priv, 0, true);
+		if (ret < 0)
+			goto card_parse_end;
+	}
+
+	ret = asoc_simple_card_parse_card_name(&priv->snd_card, PREFIX);
+	if (ret < 0)
+		goto card_parse_end;
+
+	ret = seeed_voice_card_parse_aux_devs(node, priv);
+
+	priv->channels_playback_default  = 0;
+	priv->channels_playback_override = 2;
+	priv->channels_capture_default   = 0;
+	priv->channels_capture_override  = 2;
+	of_property_read_u32(node, PREFIX "channels-playback-default",
+				    &priv->channels_playback_default);
+	of_property_read_u32(node, PREFIX "channels-playback-override",
+				    &priv->channels_playback_override);
+	of_property_read_u32(node, PREFIX "channels-capture-default",
+				    &priv->channels_capture_default);
+	of_property_read_u32(node, PREFIX "channels-capture-override",
+				    &priv->channels_capture_override);
+
+card_parse_end:
+	of_node_put(dai_link);
+
+	return ret;
+}
+
+static int seeed_voice_card_probe(struct platform_device *pdev)
+{
+	struct seeed_card_data *priv;
+	struct snd_soc_dai_link *dai_link;
+	struct seeed_dai_props *dai_props;
+	struct device_node *np = pdev->dev.of_node;
+	struct device *dev = &pdev->dev;
+	int num, ret;
+
+	/* Get the number of DAI links */
+	if (np && of_get_child_by_name(np, PREFIX "dai-link"))
+		num = of_get_child_count(np);
+	else
+		num = 1;
+
+	/* Allocate the private data and the DAI link array */
+	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+	if (!priv)
+		return -ENOMEM;
+
+	dai_props = devm_kzalloc(dev, sizeof(*dai_props) * num, GFP_KERNEL);
+	dai_link  = devm_kzalloc(dev, sizeof(*dai_link)  * num, GFP_KERNEL);
+	if (!dai_props || !dai_link)
+		return -ENOMEM;
+
+	priv->dai_props			= dai_props;
+	priv->dai_link			= dai_link;
+
+	/* Init snd_soc_card */
+	priv->snd_card.owner		= THIS_MODULE;
+	priv->snd_card.dev		= dev;
+	priv->snd_card.dai_link		= priv->dai_link;
+	priv->snd_card.num_links	= num;
+
+	if (np && of_device_is_available(np)) {
+		ret = seeed_voice_card_parse_of(np, priv);
+		if (ret < 0) {
+			if (ret != -EPROBE_DEFER)
+				dev_err(dev, "parse error %d\n", ret);
+			goto err;
+		}
+	} else {
+		struct seeed_card_info *cinfo;
+
+		cinfo = dev->platform_data;
+		if (!cinfo) {
+			dev_err(dev, "no info for seeed-voice-card\n");
+			return -EINVAL;
+		}
+
+		if (!cinfo->name ||
+		    !cinfo->codec_dai.name ||
+		    !cinfo->codec ||
+		    !cinfo->platform ||
+		    !cinfo->cpu_dai.name) {
+			dev_err(dev, "insufficient seeed_voice_card_info settings\n");
+			return -EINVAL;
+		}
+
+		priv->snd_card.name	= (cinfo->card) ? cinfo->card : cinfo->name;
+		dai_link->name		= cinfo->name;
+		dai_link->stream_name	= cinfo->name;
+		dai_link->platform_name	= cinfo->platform;
+		dai_link->codec_name	= cinfo->codec;
+		dai_link->cpu_dai_name	= cinfo->cpu_dai.name;
+		dai_link->codec_dai_name = cinfo->codec_dai.name;
+		dai_link->dai_fmt	= cinfo->daifmt;
+		dai_link->init		= seeed_voice_card_dai_init;
+		memcpy(&priv->dai_props->cpu_dai, &cinfo->cpu_dai,
+					sizeof(priv->dai_props->cpu_dai));
+		memcpy(&priv->dai_props->codec_dai, &cinfo->codec_dai,
+					sizeof(priv->dai_props->codec_dai));
+	}
+
+	snd_soc_card_set_drvdata(&priv->snd_card, priv);
+
+	#if CONFIG_AC10X_TRIG_LOCK
+	spin_lock_init(&priv->lock);
+	#endif
+
+	INIT_WORK(&priv->work_codec_clk, work_cb_codec_clk);
+
+	ret = devm_snd_soc_register_card(&pdev->dev, &priv->snd_card);
+	if (ret >= 0)
+		return ret;
+
+err:
+	asoc_simple_card_clean_reference(&priv->snd_card);
+
+	return ret;
+}
+
+static int seeed_voice_card_remove(struct platform_device *pdev)
+{
+	struct snd_soc_card *card = platform_get_drvdata(pdev);
+	struct seeed_card_data *priv = snd_soc_card_get_drvdata(card);
+
+	if (cancel_work_sync(&priv->work_codec_clk) != 0) {
+	}
+	return asoc_simple_card_clean_reference(card);
+}
+
+static const struct of_device_id seeed_voice_of_match[] = {
+	{ .compatible = "seeed-voicecard", },
+	{},
+};
+MODULE_DEVICE_TABLE(of, seeed_voice_of_match);
+
+static struct platform_driver seeed_voice_card = {
+	.driver = {
+		.name = "seeed-voicecard",
+		.pm = &snd_soc_pm_ops,
+		.of_match_table = seeed_voice_of_match,
+	},
+	.probe = seeed_voice_card_probe,
+	.remove = seeed_voice_card_remove,
+};
+
+module_platform_driver(seeed_voice_card);
+
+MODULE_ALIAS("platform:seeed-voice-card");
+MODULE_LICENSE("GPL v2");
+MODULE_DESCRIPTION("ASoC SEEED Voice Card");
+MODULE_AUTHOR("PeterYang<linsheng.yang@seeed.cc>");
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/seeed-voicecard/seeed-voicecard.service b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/seeed-voicecard/seeed-voicecard.service
new file mode 100644
index 0000000000000000000000000000000000000000..298fac664fcc320a777263cb62b26d4c2ac42012
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/seeed-voicecard/seeed-voicecard.service
@@ -0,0 +1,12 @@
+[Unit]
+Description=Seeed Voicecard service
+After=alsa-restore.service
+ 
+[Service]
+Type=oneshot
+RemainAfterExit=yes
+ExecStart=/usr/bin/seeed-voicecard
+User=root
+ 
+[Install]
+WantedBy=sysinit.target
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/seeed-voicecard/sound-compatible-4.18.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/seeed-voicecard/sound-compatible-4.18.h
new file mode 100644
index 0000000000000000000000000000000000000000..dc5a787e5a2e6d60083b83a9b3aac4aefa7f08bd
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/seeed-voicecard/sound-compatible-4.18.h
@@ -0,0 +1,35 @@
+/*
+ * (C) Copyright 2017-2018
+ * Seeed Technology Co., Ltd. <www.seeedstudio.com>
+ *
+ * PeterYang <linsheng.yang@seeed.cc>
+ */
+#ifndef __SOUND_COMPATIBLE_4_18_H__
+#define __SOUND_COMPATIBLE_4_18_H__
+
+#include <linux/version.h>
+
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(4,18,0)
+#define __NO_SND_SOC_CODEC_DRV     1
+#else
+#define __NO_SND_SOC_CODEC_DRV     0
+#endif
+
+#if __NO_SND_SOC_CODEC_DRV
+#define codec                      component
+#define snd_soc_codec              snd_soc_component
+#define snd_soc_codec_driver       snd_soc_component_driver
+#define snd_soc_codec_get_drvdata  snd_soc_component_get_drvdata
+#define snd_soc_codec_get_dapm     snd_soc_component_get_dapm
+#define snd_soc_codec_get_bias_level snd_soc_component_get_bias_level
+#define snd_soc_kcontrol_codec     snd_soc_kcontrol_component
+#define snd_soc_read               snd_soc_component_read32
+#define snd_soc_register_codec     snd_soc_register_component
+#define snd_soc_unregister_codec   snd_soc_unregister_component
+#define snd_soc_update_bits        snd_soc_component_update_bits
+#define snd_soc_write              snd_soc_component_write
+#define snd_soc_add_codec_controls snd_soc_add_component_controls
+#endif
+
+#endif//__SOUND_COMPATIBLE_4_18_H__
+
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/seeed-voicecard/tools/coherence.py b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/seeed-voicecard/tools/coherence.py
new file mode 100644
index 0000000000000000000000000000000000000000..665d2286aaf8a928bcc5352591ce5326d92e9136
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/seeed-voicecard/tools/coherence.py
@@ -0,0 +1,44 @@
+"""
+Estimate the magnitude squared coherence estimate,
+
+- requirements
+    sudo apt install python-numpy python-scipy python-matplotlib
+"""
+
+
+import sys
+import wave
+import numpy as np
+from scipy import signal
+import matplotlib.pyplot as plt
+
+if len(sys.argv) < 2:
+    print('Usage: python {} audio.wav'.format(sys.argv[0]))
+    sys.exit(1)
+
+wav = wave.open(sys.argv[1], 'rb')
+channels = wav.getnchannels()
+frames = wav.readframes(wav.getnframes())
+fs = wav.getframerate()
+wav.close()
+
+print("channels: %d" % channels)
+print("rate    : %d" % fs)
+print("frames  : %d" % wav.getnframes())
+
+array = np.fromstring(frames, dtype='int16')
+
+ch0 = array[0::channels]
+
+fig, ax = plt.subplots()
+
+for ch in range(1, channels):
+    f, c = signal.coherence(ch0, array[ch::channels], fs, nperseg=1024)
+    ax.semilogy(f, c, label="CO 1-%d" % (ch + 1))
+
+legend = ax.legend(loc='lower right', shadow=True, fontsize='small')
+
+plt.xlabel('frequency [Hz]')
+plt.ylabel('Coherence')
+plt.show()
+
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/seeed-voicecard/tools/phase_test.py b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/seeed-voicecard/tools/phase_test.py
new file mode 100644
index 0000000000000000000000000000000000000000..a099f2bde89b03baaa501d6ea91086daae8885ce
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/seeed-voicecard/tools/phase_test.py
@@ -0,0 +1,83 @@
+import sys
+import wave
+import numpy as np
+
+
+if len(sys.argv) != 2:
+    print('Usage: {} multi.wav'.format(sys.argv[0]))
+    sys.exit(1)
+
+
+multi = wave.open(sys.argv[1], 'rb')
+rate = multi.getframerate()
+channels = multi.getnchannels()
+
+if channels <= 1:
+    sys.exit(1)
+
+N = rate 
+
+window = np.hanning(N)
+
+interp = 4*8
+max_offset = int(rate * 0.1 / 340 * interp)
+
+def gcc_phat(sig, refsig, fs=1, max_tau=None, interp=16):
+    '''
+    This function computes the offset between the signal sig and the reference signal refsig
+    using the Generalized Cross Correlation - Phase Transform (GCC-PHAT)method.
+    '''
+    
+    # make sure the length for the FFT is larger or equal than len(sig) + len(refsig)
+    n = sig.shape[0] + refsig.shape[0]
+
+    # Generalized Cross Correlation Phase Transform
+    SIG = np.fft.rfft(sig, n=n)
+    REFSIG = np.fft.rfft(refsig, n=n)
+    R = SIG * np.conj(REFSIG)
+    #R /= np.abs(R)
+
+    cc = np.fft.irfft(R, n=(interp * n))
+
+    max_shift = int(interp * n / 2)
+    if max_tau:
+        max_shift = np.minimum(int(interp * fs * max_tau), max_shift)
+
+    cc = np.concatenate((cc[-max_shift:], cc[:max_shift+1]))
+
+    # find max cross correlation index
+    shift = np.argmax(np.abs(cc)) - max_shift
+
+    tau = shift / float(interp * fs)
+    
+    return tau, cc
+
+
+print(multi.getsampwidth())
+
+while True:
+    data = multi.readframes(N)
+
+    if len(data) != multi.getsampwidth() * N * channels:
+        print("done")
+        break
+
+    if multi.getsampwidth() == 2:
+        data = np.fromstring(data, dtype='int16')
+    else:
+        data = np.fromstring(data, dtype='int32')
+    ref_buf = data[0::channels]
+
+    offsets = []
+    for ch in range(1, channels):
+        sig_buf = data[ch::channels]
+        tau, _ = gcc_phat(sig_buf * window, ref_buf * window, fs=1, max_tau=max_offset, interp=interp)
+        # tau, _ = gcc_phat(sig_buf, ref_buf, fs=rate, max_tau=1)
+
+        offsets.append(tau)
+
+    print(offsets)
+
+print(multi.getframerate())
+
+multi.close()
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/seeed-voicecard/wm8960.c b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/seeed-voicecard/wm8960.c
new file mode 100644
index 0000000000000000000000000000000000000000..f26f59b777110b093353bb464ebf8e62a8e5d7e6
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/seeed-voicecard/wm8960.c
@@ -0,0 +1,1414 @@
+/*
+ * wm8960.c  --  WM8960 ALSA SoC Audio driver
+ *
+ * Copyright 2007-11 Wolfson Microelectronics, plc
+ *
+ * Author: Liam Girdwood
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/pm.h>
+#include <linux/clk.h>
+#include <linux/i2c.h>
+#include <linux/slab.h>
+#include <sound/core.h>
+#include <sound/pcm.h>
+#include <sound/pcm_params.h>
+#include <sound/soc.h>
+#include <sound/initval.h>
+#include <sound/tlv.h>
+#include <sound/wm8960.h>
+#include "sound-compatible-4.18.h"
+
+#include "wm8960.h"
+
+/* R25 - Power 1 */
+#define WM8960_VMID_MASK 0x180
+#define WM8960_VREF      0x40
+
+/* R26 - Power 2 */
+#define WM8960_PWR2_LOUT1	0x40
+#define WM8960_PWR2_ROUT1	0x20
+#define WM8960_PWR2_OUT3	0x02
+
+/* R28 - Anti-pop 1 */
+#define WM8960_POBCTRL   0x80
+#define WM8960_BUFDCOPEN 0x10
+#define WM8960_BUFIOEN   0x08
+#define WM8960_SOFT_ST   0x04
+#define WM8960_HPSTBY    0x01
+
+/* R29 - Anti-pop 2 */
+#define WM8960_DISOP     0x40
+#define WM8960_DRES_MASK 0x30
+
+static bool is_pll_freq_available(unsigned int source, unsigned int target);
+static int wm8960_set_pll(struct snd_soc_codec *codec,
+		unsigned int freq_in, unsigned int freq_out);
+/*
+ * wm8960 register cache
+ * We can't read the WM8960 register space when we are
+ * using 2 wire for device control, so we cache them instead.
+ */
+static const struct reg_default wm8960_reg_defaults[] = {
+	{  0x0, 0x00a7 },
+	{  0x1, 0x00a7 },
+	{  0x2, 0x0000 },
+	{  0x3, 0x0000 },
+	{  0x4, 0x0000 },
+	{  0x5, 0x0008 },
+	{  0x6, 0x0000 },
+	{  0x7, 0x000a },
+	{  0x8, 0x01c0 },
+	{  0x9, 0x0000 },
+	{  0xa, 0x00ff },
+	{  0xb, 0x00ff },
+
+	{ 0x10, 0x0000 },
+	{ 0x11, 0x007b },
+	{ 0x12, 0x0100 },
+	{ 0x13, 0x0032 },
+	{ 0x14, 0x0000 },
+	{ 0x15, 0x00c3 },
+	{ 0x16, 0x00c3 },
+	{ 0x17, 0x01c0 },
+	{ 0x18, 0x0000 },
+	{ 0x19, 0x0000 },
+	{ 0x1a, 0x0000 },
+	{ 0x1b, 0x0000 },
+	{ 0x1c, 0x0000 },
+	{ 0x1d, 0x0000 },
+
+	{ 0x20, 0x0100 },
+	{ 0x21, 0x0100 },
+	{ 0x22, 0x0050 },
+
+	{ 0x25, 0x0050 },
+	{ 0x26, 0x0000 },
+	{ 0x27, 0x0000 },
+	{ 0x28, 0x0000 },
+	{ 0x29, 0x0000 },
+	{ 0x2a, 0x0040 },
+	{ 0x2b, 0x0000 },
+	{ 0x2c, 0x0000 },
+	{ 0x2d, 0x0050 },
+	{ 0x2e, 0x0050 },
+	{ 0x2f, 0x0000 },
+	{ 0x30, 0x0002 },
+	{ 0x31, 0x0037 },
+
+	{ 0x33, 0x0080 },
+	{ 0x34, 0x0008 },
+	{ 0x35, 0x0031 },
+	{ 0x36, 0x0026 },
+	{ 0x37, 0x00e9 },
+};
+
+static bool wm8960_volatile(struct device *dev, unsigned int reg)
+{
+	switch (reg) {
+	case WM8960_RESET:
+		return true;
+	default:
+		return false;
+	}
+}
+
+struct wm8960_priv {
+	struct clk *mclk;
+	struct regmap *regmap;
+	int (*set_bias_level)(struct snd_soc_codec *,
+			      enum snd_soc_bias_level level);
+	struct snd_soc_dapm_widget *lout1;
+	struct snd_soc_dapm_widget *rout1;
+	struct snd_soc_dapm_widget *out3;
+	bool deemph;
+	int lrclk;
+	int bclk;
+	int sysclk;
+	int clk_id;
+	int freq_in;
+	bool is_stream_in_use[2];
+	struct wm8960_data pdata;
+};
+
+#define wm8960_reset(c)	regmap_write(c, WM8960_RESET, 0)
+
+/* enumerated controls */
+static const char *wm8960_polarity[] = {"No Inversion", "Left Inverted",
+	"Right Inverted", "Stereo Inversion"};
+static const char *wm8960_3d_upper_cutoff[] = {"High", "Low"};
+static const char *wm8960_3d_lower_cutoff[] = {"Low", "High"};
+static const char *wm8960_alcfunc[] = {"Off", "Right", "Left", "Stereo"};
+static const char *wm8960_alcmode[] = {"ALC", "Limiter"};
+static const char *wm8960_adc_data_output_sel[] = {
+	"Left Data = Left ADC;  Right Data = Right ADC",
+	"Left Data = Left ADC;  Right Data = Left ADC",
+	"Left Data = Right ADC; Right Data = Right ADC",
+	"Left Data = Right ADC; Right Data = Left ADC",
+};
+static const char *wm8960_dmonomix[] = {"Stereo", "Mono"};
+
+static const struct soc_enum wm8960_enum[] = {
+	SOC_ENUM_SINGLE(WM8960_DACCTL1, 5, 4, wm8960_polarity),
+	SOC_ENUM_SINGLE(WM8960_DACCTL2, 5, 4, wm8960_polarity),
+	SOC_ENUM_SINGLE(WM8960_3D, 6, 2, wm8960_3d_upper_cutoff),
+	SOC_ENUM_SINGLE(WM8960_3D, 5, 2, wm8960_3d_lower_cutoff),
+	SOC_ENUM_SINGLE(WM8960_ALC1, 7, 4, wm8960_alcfunc),
+	SOC_ENUM_SINGLE(WM8960_ALC3, 8, 2, wm8960_alcmode),
+	SOC_ENUM_SINGLE(WM8960_ADDCTL1, 2, 4, wm8960_adc_data_output_sel),
+	SOC_ENUM_SINGLE(WM8960_ADDCTL1, 4, 2, wm8960_dmonomix),
+};
+
+static const int deemph_settings[] = { 0, 32000, 44100, 48000 };
+
+static int wm8960_set_deemph(struct snd_soc_codec *codec)
+{
+	struct wm8960_priv *wm8960 = snd_soc_codec_get_drvdata(codec);
+	int val, i, best;
+
+	/* If we're using deemphasis select the nearest available sample
+	 * rate.
+	 */
+	if (wm8960->deemph) {
+		best = 1;
+		for (i = 2; i < ARRAY_SIZE(deemph_settings); i++) {
+			if (abs(deemph_settings[i] - wm8960->lrclk) <
+			    abs(deemph_settings[best] - wm8960->lrclk))
+				best = i;
+		}
+
+		val = best << 1;
+	} else {
+		val = 0;
+	}
+
+	dev_dbg(codec->dev, "Set deemphasis %d\n", val);
+
+	return snd_soc_update_bits(codec, WM8960_DACCTL1,
+				   0x6, val);
+}
+
+static int wm8960_get_deemph(struct snd_kcontrol *kcontrol,
+			     struct snd_ctl_elem_value *ucontrol)
+{
+	struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
+	struct wm8960_priv *wm8960 = snd_soc_codec_get_drvdata(codec);
+
+	ucontrol->value.integer.value[0] = wm8960->deemph;
+	return 0;
+}
+
+static int wm8960_put_deemph(struct snd_kcontrol *kcontrol,
+			     struct snd_ctl_elem_value *ucontrol)
+{
+	struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
+	struct wm8960_priv *wm8960 = snd_soc_codec_get_drvdata(codec);
+	unsigned int deemph = ucontrol->value.integer.value[0];
+
+	if (deemph > 1)
+		return -EINVAL;
+
+	wm8960->deemph = deemph;
+
+	return wm8960_set_deemph(codec);
+}
+
+static const DECLARE_TLV_DB_SCALE(adc_tlv, -9750, 50, 1);
+static const DECLARE_TLV_DB_SCALE(inpga_tlv, -1725, 75, 0);
+static const DECLARE_TLV_DB_SCALE(dac_tlv, -12750, 50, 1);
+static const DECLARE_TLV_DB_SCALE(bypass_tlv, -2100, 300, 0);
+static const DECLARE_TLV_DB_SCALE(out_tlv, -12100, 100, 1);
+static const DECLARE_TLV_DB_SCALE(lineinboost_tlv, -1500, 300, 1);
+static const DECLARE_TLV_DB_RANGE(micboost_tlv,
+	0, 1, TLV_DB_SCALE_ITEM(0, 1300, 0),
+	2, 3, TLV_DB_SCALE_ITEM(2000, 900, 0),
+);
+		
+
+static const struct snd_kcontrol_new wm8960_snd_controls[] = {
+SOC_DOUBLE_R_TLV("Capture Volume", WM8960_LINVOL, WM8960_RINVOL,
+		 0, 63, 0, inpga_tlv),
+SOC_DOUBLE_R("Capture Volume ZC Switch", WM8960_LINVOL, WM8960_RINVOL,
+	6, 1, 0),
+SOC_DOUBLE_R("Capture Switch", WM8960_LINVOL, WM8960_RINVOL,
+	7, 1, 1),
+
+SOC_SINGLE_TLV("Left Input Boost Mixer LINPUT3 Volume",
+	       WM8960_INBMIX1, 4, 7, 0, lineinboost_tlv),
+SOC_SINGLE_TLV("Left Input Boost Mixer LINPUT2 Volume",
+	       WM8960_INBMIX1, 1, 7, 0, lineinboost_tlv),
+SOC_SINGLE_TLV("Right Input Boost Mixer RINPUT3 Volume",
+	       WM8960_INBMIX2, 4, 7, 0, lineinboost_tlv),
+SOC_SINGLE_TLV("Right Input Boost Mixer RINPUT2 Volume",
+	       WM8960_INBMIX2, 1, 7, 0, lineinboost_tlv),
+SOC_SINGLE_TLV("Right Input Boost Mixer RINPUT1 Volume",
+		WM8960_RINPATH, 4, 3, 0, micboost_tlv),
+SOC_SINGLE_TLV("Left Input Boost Mixer LINPUT1 Volume",
+		WM8960_LINPATH, 4, 3, 0, micboost_tlv),
+
+SOC_DOUBLE_R_TLV("Playback Volume", WM8960_LDAC, WM8960_RDAC,
+		 0, 255, 0, dac_tlv),
+
+SOC_DOUBLE_R_TLV("Headphone Playback Volume", WM8960_LOUT1, WM8960_ROUT1,
+		 0, 127, 0, out_tlv),
+SOC_DOUBLE_R("Headphone Playback ZC Switch", WM8960_LOUT1, WM8960_ROUT1,
+	7, 1, 0),
+
+SOC_DOUBLE_R_TLV("Speaker Playback Volume", WM8960_LOUT2, WM8960_ROUT2,
+		 0, 127, 0, out_tlv),
+SOC_DOUBLE_R("Speaker Playback ZC Switch", WM8960_LOUT2, WM8960_ROUT2,
+	7, 1, 0),
+SOC_SINGLE("Speaker DC Volume", WM8960_CLASSD3, 3, 5, 0),
+SOC_SINGLE("Speaker AC Volume", WM8960_CLASSD3, 0, 5, 0),
+
+SOC_SINGLE("PCM Playback -6dB Switch", WM8960_DACCTL1, 7, 1, 0),
+SOC_ENUM("ADC Polarity", wm8960_enum[0]),
+SOC_SINGLE("ADC High Pass Filter Switch", WM8960_DACCTL1, 0, 1, 0),
+
+SOC_ENUM("DAC Polarity", wm8960_enum[1]),
+SOC_SINGLE_BOOL_EXT("DAC Deemphasis Switch", 0,
+		    wm8960_get_deemph, wm8960_put_deemph),
+
+SOC_ENUM("3D Filter Upper Cut-Off", wm8960_enum[2]),
+SOC_ENUM("3D Filter Lower Cut-Off", wm8960_enum[3]),
+SOC_SINGLE("3D Volume", WM8960_3D, 1, 15, 0),
+SOC_SINGLE("3D Switch", WM8960_3D, 0, 1, 0),
+
+SOC_ENUM("ALC Function", wm8960_enum[4]),
+SOC_SINGLE("ALC Max Gain", WM8960_ALC1, 4, 7, 0),
+SOC_SINGLE("ALC Target", WM8960_ALC1, 0, 15, 1),
+SOC_SINGLE("ALC Min Gain", WM8960_ALC2, 4, 7, 0),
+SOC_SINGLE("ALC Hold Time", WM8960_ALC2, 0, 15, 0),
+SOC_ENUM("ALC Mode", wm8960_enum[5]),
+SOC_SINGLE("ALC Decay", WM8960_ALC3, 4, 15, 0),
+SOC_SINGLE("ALC Attack", WM8960_ALC3, 0, 15, 0),
+
+SOC_SINGLE("Noise Gate Threshold", WM8960_NOISEG, 3, 31, 0),
+SOC_SINGLE("Noise Gate Switch", WM8960_NOISEG, 0, 1, 0),
+
+SOC_DOUBLE_R_TLV("ADC PCM Capture Volume", WM8960_LADC, WM8960_RADC,
+	0, 255, 0, adc_tlv),
+
+SOC_SINGLE_TLV("Left Output Mixer Boost Bypass Volume",
+	       WM8960_BYPASS1, 4, 7, 1, bypass_tlv),
+SOC_SINGLE_TLV("Left Output Mixer LINPUT3 Volume",
+	       WM8960_LOUTMIX, 4, 7, 1, bypass_tlv),
+SOC_SINGLE_TLV("Right Output Mixer Boost Bypass Volume",
+	       WM8960_BYPASS2, 4, 7, 1, bypass_tlv),
+SOC_SINGLE_TLV("Right Output Mixer RINPUT3 Volume",
+	       WM8960_ROUTMIX, 4, 7, 1, bypass_tlv),
+
+SOC_ENUM("ADC Data Output Select", wm8960_enum[6]),
+SOC_ENUM("DAC Mono Mix", wm8960_enum[7]),
+};
+
+static const struct snd_kcontrol_new wm8960_lin_boost[] = {
+SOC_DAPM_SINGLE("LINPUT2 Switch", WM8960_LINPATH, 6, 1, 0),
+SOC_DAPM_SINGLE("LINPUT3 Switch", WM8960_LINPATH, 7, 1, 0),
+SOC_DAPM_SINGLE("LINPUT1 Switch", WM8960_LINPATH, 8, 1, 0),
+};
+
+static const struct snd_kcontrol_new wm8960_lin[] = {
+SOC_DAPM_SINGLE("Boost Switch", WM8960_LINPATH, 3, 1, 0),
+};
+
+static const struct snd_kcontrol_new wm8960_rin_boost[] = {
+SOC_DAPM_SINGLE("RINPUT2 Switch", WM8960_RINPATH, 6, 1, 0),
+SOC_DAPM_SINGLE("RINPUT3 Switch", WM8960_RINPATH, 7, 1, 0),
+SOC_DAPM_SINGLE("RINPUT1 Switch", WM8960_RINPATH, 8, 1, 0),
+};
+
+static const struct snd_kcontrol_new wm8960_rin[] = {
+SOC_DAPM_SINGLE("Boost Switch", WM8960_RINPATH, 3, 1, 0),
+};
+
+static const struct snd_kcontrol_new wm8960_loutput_mixer[] = {
+SOC_DAPM_SINGLE("PCM Playback Switch", WM8960_LOUTMIX, 8, 1, 0),
+SOC_DAPM_SINGLE("LINPUT3 Switch", WM8960_LOUTMIX, 7, 1, 0),
+SOC_DAPM_SINGLE("Boost Bypass Switch", WM8960_BYPASS1, 7, 1, 0),
+};
+
+static const struct snd_kcontrol_new wm8960_routput_mixer[] = {
+SOC_DAPM_SINGLE("PCM Playback Switch", WM8960_ROUTMIX, 8, 1, 0),
+SOC_DAPM_SINGLE("RINPUT3 Switch", WM8960_ROUTMIX, 7, 1, 0),
+SOC_DAPM_SINGLE("Boost Bypass Switch", WM8960_BYPASS2, 7, 1, 0),
+};
+
+static const struct snd_kcontrol_new wm8960_mono_out[] = {
+SOC_DAPM_SINGLE("Left Switch", WM8960_MONOMIX1, 7, 1, 0),
+SOC_DAPM_SINGLE("Right Switch", WM8960_MONOMIX2, 7, 1, 0),
+};
+
+static const struct snd_soc_dapm_widget wm8960_dapm_widgets[] = {
+SND_SOC_DAPM_INPUT("LINPUT1"),
+SND_SOC_DAPM_INPUT("RINPUT1"),
+SND_SOC_DAPM_INPUT("LINPUT2"),
+SND_SOC_DAPM_INPUT("RINPUT2"),
+SND_SOC_DAPM_INPUT("LINPUT3"),
+SND_SOC_DAPM_INPUT("RINPUT3"),
+
+SND_SOC_DAPM_SUPPLY("MICB", WM8960_POWER1, 1, 0, NULL, 0),
+
+SND_SOC_DAPM_MIXER("Left Boost Mixer", WM8960_POWER1, 5, 0,
+		   wm8960_lin_boost, ARRAY_SIZE(wm8960_lin_boost)),
+SND_SOC_DAPM_MIXER("Right Boost Mixer", WM8960_POWER1, 4, 0,
+		   wm8960_rin_boost, ARRAY_SIZE(wm8960_rin_boost)),
+
+SND_SOC_DAPM_MIXER("Left Input Mixer", WM8960_POWER3, 5, 0,
+		   wm8960_lin, ARRAY_SIZE(wm8960_lin)),
+SND_SOC_DAPM_MIXER("Right Input Mixer", WM8960_POWER3, 4, 0,
+		   wm8960_rin, ARRAY_SIZE(wm8960_rin)),
+
+SND_SOC_DAPM_ADC("Left ADC", "Capture", WM8960_POWER1, 3, 0),
+SND_SOC_DAPM_ADC("Right ADC", "Capture", WM8960_POWER1, 2, 0),
+
+SND_SOC_DAPM_DAC("Left DAC", "Playback", WM8960_POWER2, 8, 0),
+SND_SOC_DAPM_DAC("Right DAC", "Playback", WM8960_POWER2, 7, 0),
+
+SND_SOC_DAPM_MIXER("Left Output Mixer", WM8960_POWER3, 3, 0,
+	&wm8960_loutput_mixer[0],
+	ARRAY_SIZE(wm8960_loutput_mixer)),
+SND_SOC_DAPM_MIXER("Right Output Mixer", WM8960_POWER3, 2, 0,
+	&wm8960_routput_mixer[0],
+	ARRAY_SIZE(wm8960_routput_mixer)),
+
+SND_SOC_DAPM_PGA("LOUT1 PGA", WM8960_POWER2, 6, 0, NULL, 0),
+SND_SOC_DAPM_PGA("ROUT1 PGA", WM8960_POWER2, 5, 0, NULL, 0),
+
+SND_SOC_DAPM_PGA("Left Speaker PGA", WM8960_POWER2, 4, 0, NULL, 0),
+SND_SOC_DAPM_PGA("Right Speaker PGA", WM8960_POWER2, 3, 0, NULL, 0),
+
+SND_SOC_DAPM_PGA("Right Speaker Output", WM8960_CLASSD1, 7, 0, NULL, 0),
+SND_SOC_DAPM_PGA("Left Speaker Output", WM8960_CLASSD1, 6, 0, NULL, 0),
+
+SND_SOC_DAPM_OUTPUT("SPK_LP"),
+SND_SOC_DAPM_OUTPUT("SPK_LN"),
+SND_SOC_DAPM_OUTPUT("HP_L"),
+SND_SOC_DAPM_OUTPUT("HP_R"),
+SND_SOC_DAPM_OUTPUT("SPK_RP"),
+SND_SOC_DAPM_OUTPUT("SPK_RN"),
+SND_SOC_DAPM_OUTPUT("OUT3"),
+};
+
+static const struct snd_soc_dapm_widget wm8960_dapm_widgets_out3[] = {
+SND_SOC_DAPM_MIXER("Mono Output Mixer", WM8960_POWER2, 1, 0,
+	&wm8960_mono_out[0],
+	ARRAY_SIZE(wm8960_mono_out)),
+};
+
+/* Represent OUT3 as a PGA so that it gets turned on with LOUT1/ROUT1 */
+static const struct snd_soc_dapm_widget wm8960_dapm_widgets_capless[] = {
+SND_SOC_DAPM_PGA("OUT3 VMID", WM8960_POWER2, 1, 0, NULL, 0),
+};
+
+static const struct snd_soc_dapm_route audio_paths[] = {
+	{ "Left Boost Mixer", NULL , "MICB"},
+	{ "Left Boost Mixer", "LINPUT1 Switch", "LINPUT1" },
+	{ "Left Boost Mixer", "LINPUT2 Switch", "LINPUT2" },
+	{ "Left Boost Mixer", "LINPUT3 Switch", "LINPUT3" },
+
+	{ "Left Input Mixer", "Boost Switch", "Left Boost Mixer" },
+	{ "Left Input Mixer", "Boost Switch", "LINPUT1" },  /* Really Boost Switch */
+	{ "Left Input Mixer", NULL, "LINPUT2" },
+	{ "Left Input Mixer", NULL, "LINPUT3" },
+
+	{ "Right Boost Mixer", NULL , "MICB"},
+	{ "Right Boost Mixer", "RINPUT1 Switch", "RINPUT1" },
+	{ "Right Boost Mixer", "RINPUT2 Switch", "RINPUT2" },
+	{ "Right Boost Mixer", "RINPUT3 Switch", "RINPUT3" },
+
+	{ "Right Input Mixer", "Boost Switch", "Right Boost Mixer" },
+	{ "Right Input Mixer", "Boost Switch", "RINPUT1" },  /* Really Boost Switch */
+	{ "Right Input Mixer", NULL, "RINPUT2" },
+	{ "Right Input Mixer", NULL, "RINPUT3" },
+
+	{ "Left ADC", NULL, "Left Input Mixer" },
+	{ "Right ADC", NULL, "Right Input Mixer" },
+
+	{ "Left Output Mixer", "LINPUT3 Switch", "LINPUT3" },
+	{ "Left Output Mixer", "Boost Bypass Switch", "Left Boost Mixer" }, 
+	{ "Left Output Mixer", "PCM Playback Switch", "Left DAC" },
+
+	{ "Right Output Mixer", "RINPUT3 Switch", "RINPUT3" },
+	{ "Right Output Mixer", "Boost Bypass Switch", "Right Boost Mixer" },
+	{ "Right Output Mixer", "PCM Playback Switch", "Right DAC" },
+
+	{ "LOUT1 PGA", NULL, "Left Output Mixer" },
+	{ "ROUT1 PGA", NULL, "Right Output Mixer" },
+
+	{ "HP_L", NULL, "LOUT1 PGA" },
+	{ "HP_R", NULL, "ROUT1 PGA" },
+
+	{ "Left Speaker PGA", NULL, "Left Output Mixer" },
+	{ "Right Speaker PGA", NULL, "Right Output Mixer" },
+
+	{ "Left Speaker Output", NULL, "Left Speaker PGA" },
+	{ "Right Speaker Output", NULL, "Right Speaker PGA" },
+
+	{ "SPK_LN", NULL, "Left Speaker Output" },
+	{ "SPK_LP", NULL, "Left Speaker Output" },
+	{ "SPK_RN", NULL, "Right Speaker Output" },
+	{ "SPK_RP", NULL, "Right Speaker Output" },
+};
+
+static const struct snd_soc_dapm_route audio_paths_out3[] = {
+	{ "Mono Output Mixer", "Left Switch", "Left Output Mixer" },
+	{ "Mono Output Mixer", "Right Switch", "Right Output Mixer" },
+
+	{ "OUT3", NULL, "Mono Output Mixer", }
+};
+
+static const struct snd_soc_dapm_route audio_paths_capless[] = {
+	{ "HP_L", NULL, "OUT3 VMID" },
+	{ "HP_R", NULL, "OUT3 VMID" },
+
+	{ "OUT3 VMID", NULL, "Left Output Mixer" },
+	{ "OUT3 VMID", NULL, "Right Output Mixer" },
+};
+
+static int wm8960_add_widgets(struct snd_soc_codec *codec)
+{
+	struct wm8960_priv *wm8960 = snd_soc_codec_get_drvdata(codec);
+	struct wm8960_data *pdata = &wm8960->pdata;
+	struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
+	struct snd_soc_dapm_widget *w;
+
+	snd_soc_dapm_new_controls(dapm, wm8960_dapm_widgets,
+				  ARRAY_SIZE(wm8960_dapm_widgets));
+
+	snd_soc_dapm_add_routes(dapm, audio_paths, ARRAY_SIZE(audio_paths));
+
+	/* In capless mode OUT3 is used to provide VMID for the
+	 * headphone outputs, otherwise it is used as a mono mixer.
+	 */
+	if (pdata && pdata->capless) {
+		snd_soc_dapm_new_controls(dapm, wm8960_dapm_widgets_capless,
+					  ARRAY_SIZE(wm8960_dapm_widgets_capless));
+
+		snd_soc_dapm_add_routes(dapm, audio_paths_capless,
+					ARRAY_SIZE(audio_paths_capless));
+	} else {
+		snd_soc_dapm_new_controls(dapm, wm8960_dapm_widgets_out3,
+					  ARRAY_SIZE(wm8960_dapm_widgets_out3));
+
+		snd_soc_dapm_add_routes(dapm, audio_paths_out3,
+					ARRAY_SIZE(audio_paths_out3));
+	}
+
+	/* We need to power up the headphone output stage out of
+	 * sequence for capless mode.  To save scanning the widget
+	 * list each time to find the desired power state do so now
+	 * and save the result.
+	 */
+	#if __NO_SND_SOC_CODEC_DRV
+	list_for_each_entry(w, &codec->card->widgets, list) {
+	#else
+	list_for_each_entry(w, &codec->component.card->widgets, list) {
+	#endif
+		if (w->dapm != dapm)
+			continue;
+		if (strcmp(w->name, "LOUT1 PGA") == 0)
+			wm8960->lout1 = w;
+		if (strcmp(w->name, "ROUT1 PGA") == 0)
+			wm8960->rout1 = w;
+		if (strcmp(w->name, "OUT3 VMID") == 0)
+			wm8960->out3 = w;
+	}
+	
+	return 0;
+}
+
+static int wm8960_set_dai_fmt(struct snd_soc_dai *codec_dai,
+		unsigned int fmt)
+{
+	struct snd_soc_codec *codec = codec_dai->codec;
+	u16 iface = 0;
+
+	/* set master/slave audio interface */
+	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
+	case SND_SOC_DAIFMT_CBM_CFM:
+		iface |= 0x0040;
+		break;
+	case SND_SOC_DAIFMT_CBS_CFS:
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	/* interface format */
+	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
+	case SND_SOC_DAIFMT_I2S:
+		iface |= 0x0002;
+		break;
+	case SND_SOC_DAIFMT_RIGHT_J:
+		break;
+	case SND_SOC_DAIFMT_LEFT_J:
+		iface |= 0x0001;
+		break;
+	case SND_SOC_DAIFMT_DSP_A:
+		iface |= 0x0003;
+		break;
+	case SND_SOC_DAIFMT_DSP_B:
+		iface |= 0x0013;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	/* clock inversion */
+	switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
+	case SND_SOC_DAIFMT_NB_NF:
+		break;
+	case SND_SOC_DAIFMT_IB_IF:
+		iface |= 0x0090;
+		break;
+	case SND_SOC_DAIFMT_IB_NF:
+		iface |= 0x0080;
+		break;
+	case SND_SOC_DAIFMT_NB_IF:
+		iface |= 0x0010;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	/* set iface */
+	snd_soc_write(codec, WM8960_IFACE1, iface);
+	return 0;
+}
+
+static struct {
+	int rate;
+	unsigned int val;
+} alc_rates[] = {
+	{ 48000, 0 },
+	{ 44100, 0 },
+	{ 32000, 1 },
+	{ 22050, 2 },
+	{ 24000, 2 },
+	{ 16000, 3 },
+	{ 11025, 4 },
+	{ 12000, 4 },
+	{  8000, 5 },
+};
+
+/* -1 for reserved value */
+static const int sysclk_divs[] = { 1, -1, 2, -1 };
+
+/* Multiply 256 for internal 256 div */
+static const int dac_divs[] = { 256, 384, 512, 768, 1024, 1408, 1536 };
+
+/* Multiply 10 to eliminate decimials */
+static const int bclk_divs[] = {
+	10, 15, 20, 30, 40, 55, 60, 80, 110,
+	120, 160, 220, 240, 320, 320, 320
+};
+
+static int wm8960_configure_clocking(struct snd_soc_codec *codec)
+{
+	struct wm8960_priv *wm8960 = snd_soc_codec_get_drvdata(codec);
+	int sysclk, bclk, lrclk, freq_out, freq_in;
+	u16 iface1 = snd_soc_read(codec, WM8960_IFACE1);
+	int i, j, k;
+
+	if (!(iface1 & (1<<6))) {
+		dev_dbg(codec->dev,
+			"Codec is slave mode, no need to configure clock\n");
+		//return 0;
+	}
+
+	if (wm8960->clk_id != WM8960_SYSCLK_MCLK && !wm8960->freq_in) {
+		dev_err(codec->dev, "No MCLK configured\n");
+		return -EINVAL;
+	}
+
+	freq_in = wm8960->freq_in;
+	bclk = wm8960->bclk;
+	lrclk = wm8960->lrclk;
+
+	//printk("clk_id %d freq_in: %d bclk: %d  lrclk: %d\n",wm8960->clk_id ,freq_in, bclk,lrclk);
+
+	/*
+	 * If it's sysclk auto mode, check if the MCLK can provide sysclk or
+	 * not. If MCLK can provide sysclk, using MCLK to provide sysclk
+	 * directly. Otherwise, auto select a available pll out frequency
+	 * and set PLL.
+	 */
+	if (wm8960->clk_id == WM8960_SYSCLK_AUTO) {
+		/* disable the PLL and using MCLK to provide sysclk */
+		wm8960_set_pll(codec, 0, 0);
+		freq_out = freq_in;
+	} else if (wm8960->sysclk) {
+		freq_out = wm8960->sysclk;
+	} else {
+		dev_err(codec->dev, "No SYSCLK configured\n");
+		return -EINVAL;
+	}
+
+	if (wm8960->clk_id != WM8960_SYSCLK_PLL) {
+		/* check if the sysclk frequency is available. */
+		for (i = 0; i < ARRAY_SIZE(sysclk_divs); ++i) {
+			if (sysclk_divs[i] == -1)
+				continue;
+			sysclk = freq_out / sysclk_divs[i];
+			for (j = 0; j < ARRAY_SIZE(dac_divs); ++j) {
+				if (sysclk != dac_divs[j] * lrclk)
+					continue;
+				for (k = 0; k < ARRAY_SIZE(bclk_divs); ++k)
+					if (sysclk == bclk * bclk_divs[k] / 10)
+						break;
+				if (k != ARRAY_SIZE(bclk_divs))
+					break;
+			}
+			if (j != ARRAY_SIZE(dac_divs))
+				break;
+		}
+
+		if (i != ARRAY_SIZE(sysclk_divs)) {
+			goto configure_clock;
+		} else if (wm8960->clk_id != WM8960_SYSCLK_AUTO) {
+			dev_err(codec->dev, "failed to configure clock\n");
+			return -EINVAL;
+		}
+	}
+	/* get a available pll out frequency and set pll */
+	for (i = 0; i < ARRAY_SIZE(sysclk_divs); ++i) {
+		if (sysclk_divs[i] == -1)
+			continue;
+		for (j = 0; j < ARRAY_SIZE(dac_divs); ++j) {
+			sysclk = lrclk * dac_divs[j];
+			freq_out = sysclk * sysclk_divs[i];
+
+			for (k = 0; k < ARRAY_SIZE(bclk_divs); ++k) {
+				if (sysclk == bclk * bclk_divs[k] / 10 &&
+				    is_pll_freq_available(freq_in, freq_out)) {
+					wm8960_set_pll(codec,
+						       freq_in, freq_out);
+					break;
+				} else {
+					continue;
+				}
+			}
+			if (k != ARRAY_SIZE(bclk_divs))
+				break;
+		}
+		if (j != ARRAY_SIZE(dac_divs))
+			break;
+	}
+
+	if (i == ARRAY_SIZE(sysclk_divs)) {
+		dev_err(codec->dev, "failed to configure clock\n");
+		return -EINVAL;
+	}
+
+configure_clock:
+	/* configure sysclk clock */
+	snd_soc_update_bits(codec, WM8960_CLOCK1, 3 << 1, i << 1);
+
+	/* configure frame clock */
+	snd_soc_update_bits(codec, WM8960_CLOCK1, 0x7 << 3, j << 3);
+	snd_soc_update_bits(codec, WM8960_CLOCK1, 0x7 << 6, j << 6);
+
+	/* configure bit clock */
+	snd_soc_update_bits(codec, WM8960_CLOCK2, 0xf, k);
+
+	return 0;
+}
+
+static int wm8960_hw_params(struct snd_pcm_substream *substream,
+			    struct snd_pcm_hw_params *params,
+			    struct snd_soc_dai *dai)
+{
+	struct snd_soc_codec *codec = dai->codec;
+	struct wm8960_priv *wm8960 = snd_soc_codec_get_drvdata(codec);
+	u16 iface = snd_soc_read(codec, WM8960_IFACE1) & 0xfff3;
+	bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
+	int i;
+
+	wm8960->bclk = snd_soc_params_to_bclk(params);
+	if (params_channels(params) == 1)
+		wm8960->bclk *= 2;
+
+	/* bit size */
+	switch (params_width(params)) {
+	case 16:
+		break;
+	case 20:
+		iface |= 0x0004;
+		break;
+	case 24:
+		iface |= 0x0008;
+		break;
+	case 32:
+		/* right justify mode does not support 32 word length */
+		if ((iface & 0x3) != 0) {
+			iface |= 0x000c;
+			break;
+		}
+	default:
+		dev_err(codec->dev, "unsupported width %d\n",
+			params_width(params));
+		return -EINVAL;
+	}
+
+	wm8960->lrclk = params_rate(params);
+	/* Update filters for the new rate */
+	if (tx) {
+		wm8960_set_deemph(codec);
+	} else {
+		for (i = 0; i < ARRAY_SIZE(alc_rates); i++)
+			if (alc_rates[i].rate == params_rate(params))
+				snd_soc_update_bits(codec,
+						    WM8960_ADDCTL3, 0x7,
+						    alc_rates[i].val);
+	}
+
+	/* set iface */
+	snd_soc_write(codec, WM8960_IFACE1, iface);
+
+	wm8960->is_stream_in_use[tx] = true;
+
+	if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_ON &&
+	    !wm8960->is_stream_in_use[!tx])
+		return wm8960_configure_clocking(codec);
+
+	return 0;
+}
+
+static int wm8960_hw_free(struct snd_pcm_substream *substream,
+		struct snd_soc_dai *dai)
+{
+	struct snd_soc_codec *codec = dai->codec;
+	struct wm8960_priv *wm8960 = snd_soc_codec_get_drvdata(codec);
+	bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
+
+	wm8960->is_stream_in_use[tx] = false;
+
+	return 0;
+}
+
+static int wm8960_mute(struct snd_soc_dai *dai, int mute)
+{
+	struct snd_soc_codec *codec = dai->codec;
+
+	if (mute)
+		snd_soc_update_bits(codec, WM8960_DACCTL1, 0x8, 0x8);
+	else
+		snd_soc_update_bits(codec, WM8960_DACCTL1, 0x8, 0);
+	return 0;
+}
+
+static int wm8960_set_bias_level_out3(struct snd_soc_codec *codec,
+				      enum snd_soc_bias_level level)
+{
+	struct wm8960_priv *wm8960 = snd_soc_codec_get_drvdata(codec);
+	u16 pm2 = snd_soc_read(codec, WM8960_POWER2);
+	int ret;
+
+	switch (level) {
+	case SND_SOC_BIAS_ON:
+		break;
+
+	case SND_SOC_BIAS_PREPARE:
+		switch (snd_soc_codec_get_bias_level(codec)) {
+		case SND_SOC_BIAS_STANDBY:
+			if (!IS_ERR(wm8960->mclk)) {
+				ret = clk_prepare_enable(wm8960->mclk);
+				if (ret) {
+					dev_err(codec->dev,
+						"Failed to enable MCLK: %d\n",
+						ret);
+					return ret;
+				}
+			}
+
+			ret = wm8960_configure_clocking(codec);
+			if (ret)
+				return ret;
+
+			/* Set VMID to 2x50k */
+			snd_soc_update_bits(codec, WM8960_POWER1, 0x180, 0x80);
+			break;
+
+		case SND_SOC_BIAS_ON:
+			/*
+			 * If it's sysclk auto mode, and the pll is enabled,
+			 * disable the pll
+			 */
+			if (wm8960->clk_id == WM8960_SYSCLK_AUTO && (pm2 & 0x1))
+				wm8960_set_pll(codec, 0, 0);
+
+			if (!IS_ERR(wm8960->mclk))
+				clk_disable_unprepare(wm8960->mclk);
+			break;
+
+		default:
+			break;
+		}
+
+		break;
+
+	case SND_SOC_BIAS_STANDBY:
+		if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_OFF) {
+			regcache_sync(wm8960->regmap);
+
+			/* Enable anti-pop features */
+			snd_soc_write(codec, WM8960_APOP1,
+				      WM8960_POBCTRL | WM8960_SOFT_ST |
+				      WM8960_BUFDCOPEN | WM8960_BUFIOEN);
+
+			/* Enable & ramp VMID at 2x50k */
+			snd_soc_update_bits(codec, WM8960_POWER1, 0x80, 0x80);
+			msleep(100);
+
+			/* Enable VREF */
+			snd_soc_update_bits(codec, WM8960_POWER1, WM8960_VREF,
+					    WM8960_VREF);
+
+			/* Disable anti-pop features */
+			snd_soc_write(codec, WM8960_APOP1, WM8960_BUFIOEN);
+		}
+
+		/* Set VMID to 2x250k */
+		snd_soc_update_bits(codec, WM8960_POWER1, 0x180, 0x100);
+		break;
+
+	case SND_SOC_BIAS_OFF:
+		/* Enable anti-pop features */
+		snd_soc_write(codec, WM8960_APOP1,
+			     WM8960_POBCTRL | WM8960_SOFT_ST |
+			     WM8960_BUFDCOPEN | WM8960_BUFIOEN);
+
+		/* Disable VMID and VREF, let them discharge */
+		snd_soc_write(codec, WM8960_POWER1, 0);
+		msleep(600);
+		break;
+	}
+
+	return 0;
+}
+
+static int wm8960_set_bias_level_capless(struct snd_soc_codec *codec,
+					 enum snd_soc_bias_level level)
+{
+	struct wm8960_priv *wm8960 = snd_soc_codec_get_drvdata(codec);
+	u16 pm2 = snd_soc_read(codec, WM8960_POWER2);
+	int reg, ret;
+
+	switch (level) {
+	case SND_SOC_BIAS_ON:
+		break;
+
+	case SND_SOC_BIAS_PREPARE:
+		switch (snd_soc_codec_get_bias_level(codec)) {
+		case SND_SOC_BIAS_STANDBY:
+			/* Enable anti pop mode */
+			snd_soc_update_bits(codec, WM8960_APOP1,
+					    WM8960_POBCTRL | WM8960_SOFT_ST |
+					    WM8960_BUFDCOPEN,
+					    WM8960_POBCTRL | WM8960_SOFT_ST |
+					    WM8960_BUFDCOPEN);
+
+			/* Enable LOUT1, ROUT1 and OUT3 if they're enabled */
+			reg = 0;
+			if (wm8960->lout1 && wm8960->lout1->power)
+				reg |= WM8960_PWR2_LOUT1;
+			if (wm8960->rout1 && wm8960->rout1->power)
+				reg |= WM8960_PWR2_ROUT1;
+			if (wm8960->out3 && wm8960->out3->power)
+				reg |= WM8960_PWR2_OUT3;
+			snd_soc_update_bits(codec, WM8960_POWER2,
+					    WM8960_PWR2_LOUT1 |
+					    WM8960_PWR2_ROUT1 |
+					    WM8960_PWR2_OUT3, reg);
+
+			/* Enable VMID at 2*50k */
+			snd_soc_update_bits(codec, WM8960_POWER1,
+					    WM8960_VMID_MASK, 0x80);
+
+			/* Ramp */
+			msleep(100);
+
+			/* Enable VREF */
+			snd_soc_update_bits(codec, WM8960_POWER1,
+					    WM8960_VREF, WM8960_VREF);
+
+			msleep(100);
+
+			if (!IS_ERR(wm8960->mclk)) {
+				ret = clk_prepare_enable(wm8960->mclk);
+				if (ret) {
+					dev_err(codec->dev,
+						"Failed to enable MCLK: %d\n",
+						ret);
+					return ret;
+				}
+			}
+
+			ret = wm8960_configure_clocking(codec);
+			if (ret)
+				return ret;
+
+			break;
+
+		case SND_SOC_BIAS_ON:
+			/*
+			 * If it's sysclk auto mode, and the pll is enabled,
+			 * disable the pll
+			 */
+			if (wm8960->clk_id == WM8960_SYSCLK_AUTO && (pm2 & 0x1))
+				wm8960_set_pll(codec, 0, 0);
+
+			if (!IS_ERR(wm8960->mclk))
+				clk_disable_unprepare(wm8960->mclk);
+
+			/* Enable anti-pop mode */
+			snd_soc_update_bits(codec, WM8960_APOP1,
+					    WM8960_POBCTRL | WM8960_SOFT_ST |
+					    WM8960_BUFDCOPEN,
+					    WM8960_POBCTRL | WM8960_SOFT_ST |
+					    WM8960_BUFDCOPEN);
+
+			/* Disable VMID and VREF */
+			snd_soc_update_bits(codec, WM8960_POWER1,
+					    WM8960_VREF | WM8960_VMID_MASK, 0);
+			break;
+
+		case SND_SOC_BIAS_OFF:
+			regcache_sync(wm8960->regmap);
+			break;
+		default:
+			break;
+		}
+		break;
+
+	case SND_SOC_BIAS_STANDBY:
+		switch (snd_soc_codec_get_bias_level(codec)) {
+		case SND_SOC_BIAS_PREPARE:
+			/* Disable HP discharge */
+			snd_soc_update_bits(codec, WM8960_APOP2,
+					    WM8960_DISOP | WM8960_DRES_MASK,
+					    0);
+
+			/* Disable anti-pop features */
+			snd_soc_update_bits(codec, WM8960_APOP1,
+					    WM8960_POBCTRL | WM8960_SOFT_ST |
+					    WM8960_BUFDCOPEN,
+					    WM8960_POBCTRL | WM8960_SOFT_ST |
+					    WM8960_BUFDCOPEN);
+			break;
+
+		default:
+			break;
+		}
+		break;
+
+	case SND_SOC_BIAS_OFF:
+		break;
+	}
+
+	return 0;
+}
+
+/* PLL divisors */
+struct _pll_div {
+	u32 pre_div:1;
+	u32 n:4;
+	u32 k:24;
+};
+
+static bool is_pll_freq_available(unsigned int source, unsigned int target)
+{
+	unsigned int Ndiv;
+
+	if (source == 0 || target == 0)
+		return false;
+
+	/* Scale up target to PLL operating frequency */
+	target *= 4;
+	Ndiv = target / source;
+
+	if (Ndiv < 6) {
+		source >>= 1;
+		Ndiv = target / source;
+	}
+
+	if ((Ndiv < 6) || (Ndiv > 12))
+		return false;
+
+	return true;
+}
+
+/* The size in bits of the pll divide multiplied by 10
+ * to allow rounding later */
+#define FIXED_PLL_SIZE ((1 << 24) * 10)
+
+static int pll_factors(unsigned int source, unsigned int target,
+		       struct _pll_div *pll_div)
+{
+	unsigned long long Kpart;
+	unsigned int K, Ndiv, Nmod;
+
+	pr_debug("WM8960 PLL: setting %dHz->%dHz\n", source, target);
+
+	/* Scale up target to PLL operating frequency */
+	target *= 4;
+
+	Ndiv = target / source;
+	if (Ndiv < 6) {
+		source >>= 1;
+		pll_div->pre_div = 1;
+		Ndiv = target / source;
+	} else
+		pll_div->pre_div = 0;
+
+	if ((Ndiv < 6) || (Ndiv > 12)) {
+		pr_err("WM8960 PLL: Unsupported N=%d\n", Ndiv);
+		return -EINVAL;
+	}
+
+	pll_div->n = Ndiv;
+	Nmod = target % source;
+	Kpart = FIXED_PLL_SIZE * (long long)Nmod;
+
+	do_div(Kpart, source);
+
+	K = Kpart & 0xFFFFFFFF;
+
+	/* Check if we need to round */
+	if ((K % 10) >= 5)
+		K += 5;
+
+	/* Move down to proper range now rounding is done */
+	K /= 10;
+
+	pll_div->k = K;
+
+	pr_debug("WM8960 PLL: N=%x K=%x pre_div=%d\n",
+		 pll_div->n, pll_div->k, pll_div->pre_div);
+
+	return 0;
+}
+
+static int wm8960_set_pll(struct snd_soc_codec *codec,
+		unsigned int freq_in, unsigned int freq_out)
+{
+	u16 reg;
+	static struct _pll_div pll_div;
+	int ret;
+
+	if (freq_in && freq_out) {
+		ret = pll_factors(freq_in, freq_out, &pll_div);
+		if (ret != 0)
+			return ret;
+	}
+
+	/* Disable the PLL: even if we are changing the frequency the
+	 * PLL needs to be disabled while we do so. */
+	snd_soc_update_bits(codec, WM8960_CLOCK1, 0x1, 0);
+	snd_soc_update_bits(codec, WM8960_POWER2, 0x1, 0);
+
+	if (!freq_in || !freq_out)
+		return 0;
+
+	reg = snd_soc_read(codec, WM8960_PLL1) & ~0x3f;
+	reg |= pll_div.pre_div << 4;
+	reg |= pll_div.n;
+
+	if (pll_div.k) {
+		reg |= 0x20;
+
+		snd_soc_write(codec, WM8960_PLL2, (pll_div.k >> 16) & 0xff);
+		snd_soc_write(codec, WM8960_PLL3, (pll_div.k >> 8) & 0xff);
+		snd_soc_write(codec, WM8960_PLL4, pll_div.k & 0xff);
+	}
+	snd_soc_write(codec, WM8960_PLL1, reg);
+
+	/* Turn it on */
+	snd_soc_update_bits(codec, WM8960_POWER2, 0x1, 0x1);
+	msleep(250);
+	snd_soc_update_bits(codec, WM8960_CLOCK1, 0x1, 0x1);
+
+	return 0;
+}
+
+static int wm8960_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id,
+		int source, unsigned int freq_in, unsigned int freq_out)
+{
+
+	struct snd_soc_codec *codec = codec_dai->codec;
+	struct wm8960_priv *wm8960 = snd_soc_codec_get_drvdata(codec);
+
+	wm8960->freq_in = freq_in;
+
+	if (pll_id == WM8960_SYSCLK_AUTO)
+		return 0;
+	return wm8960_set_pll(codec, freq_in, freq_out);
+}
+
+static int wm8960_set_dai_clkdiv(struct snd_soc_dai *codec_dai,
+		int div_id, int div)
+{
+	struct snd_soc_codec *codec = codec_dai->codec;
+	u16 reg;
+
+
+	switch (div_id) {
+	case WM8960_SYSCLKDIV:
+		reg = snd_soc_read(codec, WM8960_CLOCK1) & 0x1f9;
+		snd_soc_write(codec, WM8960_CLOCK1, reg | div);
+		break;
+	case WM8960_DACDIV:
+		reg = snd_soc_read(codec, WM8960_CLOCK1) & 0x1c7;
+		snd_soc_write(codec, WM8960_CLOCK1, reg | div);
+		break;
+	case WM8960_OPCLKDIV:
+		reg = snd_soc_read(codec, WM8960_PLL1) & 0x03f;
+		snd_soc_write(codec, WM8960_PLL1, reg | div);
+		break;
+	case WM8960_DCLKDIV:
+		reg = snd_soc_read(codec, WM8960_CLOCK2) & 0x03f;
+		snd_soc_write(codec, WM8960_CLOCK2, reg | div);
+		break;
+	case WM8960_TOCLKSEL:
+		reg = snd_soc_read(codec, WM8960_ADDCTL1) & 0x1fd;
+		snd_soc_write(codec, WM8960_ADDCTL1, reg | div);
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static int wm8960_set_bias_level(struct snd_soc_codec *codec,
+				 enum snd_soc_bias_level level)
+{
+	struct wm8960_priv *wm8960 = snd_soc_codec_get_drvdata(codec);
+
+	return wm8960->set_bias_level(codec, level);
+}
+
+static int wm8960_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id,
+					unsigned int freq, int dir)
+{
+
+	struct snd_soc_codec *codec = dai->codec;
+	struct wm8960_priv *wm8960 = snd_soc_codec_get_drvdata(codec);
+	clk_id = WM8960_SYSCLK_PLL;
+
+	switch (clk_id) {
+	case WM8960_SYSCLK_MCLK:
+		snd_soc_update_bits(codec, WM8960_CLOCK1,
+					0x1, WM8960_SYSCLK_MCLK);
+		break;
+	case WM8960_SYSCLK_PLL:
+		snd_soc_update_bits(codec, WM8960_CLOCK1,
+					0x1, WM8960_SYSCLK_PLL);
+		break;
+	case WM8960_SYSCLK_AUTO:
+		break;
+	default:
+		return -EINVAL;
+	}
+	wm8960->freq_in = 24000000;
+	wm8960->sysclk = freq;
+	wm8960->clk_id = clk_id;
+
+	return 0;
+}
+
+#define WM8960_RATES SNDRV_PCM_RATE_8000_48000
+
+#define WM8960_FORMATS \
+	(SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
+	SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
+
+static const struct snd_soc_dai_ops wm8960_dai_ops = {
+	.hw_params = wm8960_hw_params,
+	.hw_free = wm8960_hw_free,
+	.digital_mute = wm8960_mute,
+	.set_fmt = wm8960_set_dai_fmt,
+	.set_clkdiv = wm8960_set_dai_clkdiv,
+	.set_pll = wm8960_set_dai_pll,
+	.set_sysclk = wm8960_set_dai_sysclk,
+};
+
+static struct snd_soc_dai_driver wm8960_dai = {
+	.name = "wm8960-hifi",
+	.playback = {
+		.stream_name = "Playback",
+		.channels_min = 1,
+		.channels_max = 2,
+		.rates = WM8960_RATES,
+		.formats = WM8960_FORMATS,},
+	.capture = {
+		.stream_name = "Capture",
+		.channels_min = 1,
+		.channels_max = 2,
+		.rates = WM8960_RATES,
+		.formats = WM8960_FORMATS,},
+	.ops = &wm8960_dai_ops,
+	.symmetric_rates = 1,
+};
+
+static int wm8960_probe(struct snd_soc_codec *codec)
+{
+	struct wm8960_priv *wm8960 = snd_soc_codec_get_drvdata(codec);
+	struct wm8960_data *pdata = &wm8960->pdata;
+
+	if (pdata->capless)
+		wm8960->set_bias_level = wm8960_set_bias_level_capless;
+	else
+		wm8960->set_bias_level = wm8960_set_bias_level_out3;
+
+	snd_soc_add_codec_controls(codec, wm8960_snd_controls,
+				     ARRAY_SIZE(wm8960_snd_controls));
+	wm8960_add_widgets(codec);
+
+	return 0;
+}
+
+static const struct snd_soc_codec_driver soc_codec_dev_wm8960 = {
+	.probe =	wm8960_probe,
+	.set_bias_level = wm8960_set_bias_level,
+	.suspend_bias_off	= true,
+	#if __NO_SND_SOC_CODEC_DRV
+	.idle_bias_on		= 1,
+	.use_pmdown_time	= 1,
+	.endianness		= 1,
+	.non_legacy_dai_naming	= 1,
+	#endif
+};
+
+static const struct regmap_config wm8960_regmap = {
+	.reg_bits = 7,
+	.val_bits = 9,
+	.max_register = WM8960_PLL4,
+
+	.reg_defaults = wm8960_reg_defaults,
+	.num_reg_defaults = ARRAY_SIZE(wm8960_reg_defaults),
+	.cache_type = REGCACHE_RBTREE,
+
+	.volatile_reg = wm8960_volatile,
+};
+
+static void wm8960_set_pdata_from_of(struct i2c_client *i2c,
+				struct wm8960_data *pdata)
+{
+	const struct device_node *np = i2c->dev.of_node;
+
+	if (of_property_read_bool(np, "wlf,capless"))
+		pdata->capless = true;
+
+	if (of_property_read_bool(np, "wlf,shared-lrclk"))
+		pdata->shared_lrclk = true;
+}
+
+static int wm8960_i2c_probe(struct i2c_client *i2c,
+			    const struct i2c_device_id *id)
+{
+	struct wm8960_data *pdata = dev_get_platdata(&i2c->dev);
+	struct wm8960_priv *wm8960;
+	int ret;
+
+	wm8960 = devm_kzalloc(&i2c->dev, sizeof(struct wm8960_priv),
+			      GFP_KERNEL);
+	if (wm8960 == NULL)
+		return -ENOMEM;
+
+	wm8960->clk_id = WM8960_SYSCLK_PLL;
+
+	wm8960->mclk = devm_clk_get(&i2c->dev, "mclk");
+
+	if (IS_ERR(wm8960->mclk)) {
+		if (PTR_ERR(wm8960->mclk) == -EPROBE_DEFER)
+			return -EPROBE_DEFER;
+	}
+
+	wm8960->regmap = devm_regmap_init_i2c(i2c, &wm8960_regmap);
+	if (IS_ERR(wm8960->regmap))
+		return PTR_ERR(wm8960->regmap);
+
+	if (pdata)
+		memcpy(&wm8960->pdata, pdata, sizeof(struct wm8960_data));
+	else if (i2c->dev.of_node)
+		wm8960_set_pdata_from_of(i2c, &wm8960->pdata);
+
+	ret = wm8960_reset(wm8960->regmap);
+	if (ret != 0) {
+		dev_err(&i2c->dev, "Failed to issue reset\n");
+		return ret;
+	}
+
+	if (wm8960->pdata.shared_lrclk) {
+		ret = regmap_update_bits(wm8960->regmap, WM8960_ADDCTL2,
+					 0x4, 0x4);
+		if (ret != 0) {
+			dev_err(&i2c->dev, "Failed to enable LRCM: %d\n",
+				ret);
+			return ret;
+		}
+	}
+
+	/* Latch the update bits */
+	regmap_update_bits(wm8960->regmap, WM8960_LINVOL, 0x100, 0x100);
+	regmap_update_bits(wm8960->regmap, WM8960_RINVOL, 0x100, 0x100);
+	regmap_update_bits(wm8960->regmap, WM8960_LADC, 0x100, 0x100);
+	regmap_update_bits(wm8960->regmap, WM8960_RADC, 0x100, 0x100);
+	regmap_update_bits(wm8960->regmap, WM8960_LDAC, 0x100, 0x100);
+	regmap_update_bits(wm8960->regmap, WM8960_RDAC, 0x100, 0x100);
+	regmap_update_bits(wm8960->regmap, WM8960_LOUT1, 0x100, 0x100);
+	regmap_update_bits(wm8960->regmap, WM8960_ROUT1, 0x100, 0x100);
+	regmap_update_bits(wm8960->regmap, WM8960_LOUT2, 0x100, 0x100);
+	regmap_update_bits(wm8960->regmap, WM8960_ROUT2, 0x100, 0x100);
+
+	i2c_set_clientdata(i2c, wm8960);
+
+	ret = snd_soc_register_codec(&i2c->dev,
+			&soc_codec_dev_wm8960, &wm8960_dai, 1);
+
+	return ret;
+}
+
+static int wm8960_i2c_remove(struct i2c_client *client)
+{
+	snd_soc_unregister_codec(&client->dev);
+	return 0;
+}
+
+static const struct i2c_device_id wm8960_i2c_id[] = {
+	{ "wm8960", 0 },
+	{ }
+};
+MODULE_DEVICE_TABLE(i2c, wm8960_i2c_id);
+
+static const struct of_device_id wm8960_of_match[] = {
+       { .compatible = "wlf,wm8960", },
+       { }
+};
+MODULE_DEVICE_TABLE(of, wm8960_of_match);
+
+static struct i2c_driver wm8960_i2c_driver = {
+	.driver = {
+		.name = "wm8960",
+		.of_match_table = wm8960_of_match,
+	},
+	.probe =    wm8960_i2c_probe,
+	.remove =   wm8960_i2c_remove,
+	.id_table = wm8960_i2c_id,
+};
+
+module_i2c_driver(wm8960_i2c_driver);
+
+MODULE_DESCRIPTION("ASoC WM8960 driver");
+MODULE_AUTHOR("Liam Girdwood");
+MODULE_LICENSE("GPL");
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/seeed-voicecard/wm8960.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/seeed-voicecard/wm8960.h
new file mode 100644
index 0000000000000000000000000000000000000000..ab3220d3411d26ef8dfe0fafdc213a5728fbfd41
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/seeed-voicecard/wm8960.h
@@ -0,0 +1,114 @@
+/*
+ * wm8960.h  --  WM8960 Soc Audio driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef _WM8960_H
+#define _WM8960_H
+
+/* WM8960 register space */
+
+
+#define WM8960_CACHEREGNUM 	56
+
+#define WM8960_LINVOL		0x0
+#define WM8960_RINVOL		0x1
+#define WM8960_LOUT1		0x2
+#define WM8960_ROUT1		0x3
+#define WM8960_CLOCK1		0x4
+#define WM8960_DACCTL1		0x5
+#define WM8960_DACCTL2		0x6
+#define WM8960_IFACE1		0x7
+#define WM8960_CLOCK2		0x8
+#define WM8960_IFACE2		0x9
+#define WM8960_LDAC		0xa
+#define WM8960_RDAC		0xb
+
+#define WM8960_RESET		0xf
+#define WM8960_3D		0x10
+#define WM8960_ALC1		0x11
+#define WM8960_ALC2		0x12
+#define WM8960_ALC3		0x13
+#define WM8960_NOISEG		0x14
+#define WM8960_LADC		0x15
+#define WM8960_RADC		0x16
+#define WM8960_ADDCTL1		0x17
+#define WM8960_ADDCTL2		0x18
+#define WM8960_POWER1		0x19
+#define WM8960_POWER2		0x1a
+#define WM8960_ADDCTL3		0x1b
+#define WM8960_APOP1		0x1c
+#define WM8960_APOP2		0x1d
+
+#define WM8960_LINPATH		0x20
+#define WM8960_RINPATH		0x21
+#define WM8960_LOUTMIX		0x22
+
+#define WM8960_ROUTMIX		0x25
+#define WM8960_MONOMIX1		0x26
+#define WM8960_MONOMIX2		0x27
+#define WM8960_LOUT2		0x28
+#define WM8960_ROUT2		0x29
+#define WM8960_MONO		0x2a
+#define WM8960_INBMIX1		0x2b
+#define WM8960_INBMIX2		0x2c
+#define WM8960_BYPASS1		0x2d
+#define WM8960_BYPASS2		0x2e
+#define WM8960_POWER3		0x2f
+#define WM8960_ADDCTL4		0x30
+#define WM8960_CLASSD1		0x31
+
+#define WM8960_CLASSD3		0x33
+#define WM8960_PLL1		0x34
+#define WM8960_PLL2		0x35
+#define WM8960_PLL3		0x36
+#define WM8960_PLL4		0x37
+
+
+/*
+ * WM8960 Clock dividers
+ */
+#define WM8960_SYSCLKDIV 		0
+#define WM8960_DACDIV			1
+#define WM8960_OPCLKDIV			2
+#define WM8960_DCLKDIV			3
+#define WM8960_TOCLKSEL			4
+
+#define WM8960_SYSCLK_DIV_1		(0 << 1)
+#define WM8960_SYSCLK_DIV_2		(2 << 1)
+
+#define WM8960_SYSCLK_MCLK		(0 << 0)
+#define WM8960_SYSCLK_PLL		(1 << 0)
+#define WM8960_SYSCLK_AUTO		(2 << 0)
+
+#define WM8960_DAC_DIV_1		(0 << 3)
+#define WM8960_DAC_DIV_1_5		(1 << 3)
+#define WM8960_DAC_DIV_2		(2 << 3)
+#define WM8960_DAC_DIV_3		(3 << 3)
+#define WM8960_DAC_DIV_4		(4 << 3)
+#define WM8960_DAC_DIV_5_5		(5 << 3)
+#define WM8960_DAC_DIV_6		(6 << 3)
+
+#define WM8960_DCLK_DIV_1_5		(0 << 6)
+#define WM8960_DCLK_DIV_2		(1 << 6)
+#define WM8960_DCLK_DIV_3		(2 << 6)
+#define WM8960_DCLK_DIV_4		(3 << 6)
+#define WM8960_DCLK_DIV_6		(4 << 6)
+#define WM8960_DCLK_DIV_8		(5 << 6)
+#define WM8960_DCLK_DIV_12		(6 << 6)
+#define WM8960_DCLK_DIV_16		(7 << 6)
+
+#define WM8960_TOCLK_F19		(0 << 1)
+#define WM8960_TOCLK_F21		(1 << 1)
+
+#define WM8960_OPCLK_DIV_1		(0 << 0)
+#define WM8960_OPCLK_DIV_2		(1 << 0)
+#define WM8960_OPCLK_DIV_3		(2 << 0)
+#define WM8960_OPCLK_DIV_4		(3 << 0)
+#define WM8960_OPCLK_DIV_5_5		(4 << 0)
+#define WM8960_OPCLK_DIV_6		(5 << 0)
+
+#endif
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/seeed-voicecard/wm8960_asound.state b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/seeed-voicecard/wm8960_asound.state
new file mode 100644
index 0000000000000000000000000000000000000000..079806b53169da77eee1aac16170f86c3caa0372
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/seeed-voicecard/wm8960_asound.state
@@ -0,0 +1,758 @@
+state.ALSA {
+	control.1 {
+		iface MIXER
+		name 'PCM Playback Volume'
+		value -1994
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '-10239 - 400'
+			dbmin -9999999
+			dbmax 400
+			dbvalue.0 -1994
+		}
+	}
+	control.2 {
+		iface MIXER
+		name 'PCM Playback Switch'
+		value true
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.3 {
+		iface MIXER
+		name 'PCM Playback Route'
+		value 0
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 2'
+		}
+	}
+	control.4 {
+		iface PCM
+		name 'IEC958 Playback Default'
+		value '0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000'
+		comment {
+			access 'read write'
+			type IEC958
+			count 1
+		}
+	}
+	control.5 {
+		iface PCM
+		name 'IEC958 Playback Con Mask'
+		value '0200000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000'
+		comment {
+			access read
+			type IEC958
+			count 1
+		}
+	}
+	control.6 {
+		iface PCM
+		name 'IEC958 Playback PCM Stream'
+		value '0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000'
+		comment {
+			access 'read write inactive'
+			type IEC958
+			count 1
+		}
+	}
+}
+state.seeed2micvoicec {
+	control.1 {
+		iface MIXER
+		name 'Capture Volume'
+		value.0 39
+		value.1 39
+		comment {
+			access 'read write'
+			type INTEGER
+			count 2
+			range '0 - 63'
+			dbmin -1725
+			dbmax 3000
+			dbvalue.0 1200
+			dbvalue.1 1200
+		}
+	}
+	control.2 {
+		iface MIXER
+		name 'Capture Volume ZC Switch'
+		value.0 0
+		value.1 0
+		comment {
+			access 'read write'
+			type INTEGER
+			count 2
+			range '0 - 1'
+		}
+	}
+	control.3 {
+		iface MIXER
+		name 'Capture Switch'
+		value.0 true
+		value.1 true
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 2
+		}
+	}
+	control.4 {
+		iface MIXER
+		name 'Left Input Boost Mixer LINPUT3 Volume'
+		value 0
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 7'
+			dbmin -9999999
+			dbmax 600
+			dbvalue.0 -9999999
+		}
+	}
+	control.5 {
+		iface MIXER
+		name 'Left Input Boost Mixer LINPUT2 Volume'
+		value 0
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 7'
+			dbmin -9999999
+			dbmax 600
+			dbvalue.0 -9999999
+		}
+	}
+	control.6 {
+		iface MIXER
+		name 'Right Input Boost Mixer RINPUT3 Volume'
+		value 0
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 7'
+			dbmin -9999999
+			dbmax 600
+			dbvalue.0 -9999999
+		}
+	}
+	control.7 {
+		iface MIXER
+		name 'Right Input Boost Mixer RINPUT2 Volume'
+		value 0
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 7'
+			dbmin -9999999
+			dbmax 600
+			dbvalue.0 -9999999
+		}
+	}
+	control.8 {
+		iface MIXER
+		name 'Right Input Boost Mixer RINPUT1 Volume'
+		value 3
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 3'
+			dbmin 0
+			dbmax 2900
+			dbvalue.0 2900
+		}
+	}
+	control.9 {
+		iface MIXER
+		name 'Left Input Boost Mixer LINPUT1 Volume'
+		value 3
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 3'
+			dbmin 0
+			dbmax 2900
+			dbvalue.0 2900
+		}
+	}
+	control.10 {
+		iface MIXER
+		name 'Playback Volume'
+		value.0 255
+		value.1 255
+		comment {
+			access 'read write'
+			type INTEGER
+			count 2
+			range '0 - 255'
+			dbmin -9999999
+			dbmax 0
+			dbvalue.0 0
+			dbvalue.1 0
+		}
+	}
+	control.11 {
+		iface MIXER
+		name 'Headphone Playback Volume'
+		value.0 127
+		value.1 127
+		comment {
+			access 'read write'
+			type INTEGER
+			count 2
+			range '0 - 127'
+			dbmin -9999999
+			dbmax 600
+			dbvalue.0 600
+			dbvalue.1 600
+		}
+	}
+	control.12 {
+		iface MIXER
+		name 'Headphone Playback ZC Switch'
+		value.0 false
+		value.1 false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 2
+		}
+	}
+	control.13 {
+		iface MIXER
+		name 'Speaker Playback Volume'
+		value.0 127
+		value.1 127
+		comment {
+			access 'read write'
+			type INTEGER
+			count 2
+			range '0 - 127'
+			dbmin -9999999
+			dbmax 600
+			dbvalue.0 600
+			dbvalue.1 600
+		}
+	}
+	control.14 {
+		iface MIXER
+		name 'Speaker Playback ZC Switch'
+		value.0 false
+		value.1 false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 2
+		}
+	}
+	control.15 {
+		iface MIXER
+		name 'Speaker DC Volume'
+		value 4
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 5'
+		}
+	}
+	control.16 {
+		iface MIXER
+		name 'Speaker AC Volume'
+		value 5
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 5'
+		}
+	}
+	control.17 {
+		iface MIXER
+		name 'PCM Playback -6dB Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.18 {
+		iface MIXER
+		name 'ADC Polarity'
+		value 'No Inversion'
+		comment {
+			access 'read write'
+			type ENUMERATED
+			count 1
+			item.0 'No Inversion'
+			item.1 'Left Inverted'
+			item.2 'Right Inverted'
+			item.3 'Stereo Inversion'
+		}
+	}
+	control.19 {
+		iface MIXER
+		name 'ADC High Pass Filter Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.20 {
+		iface MIXER
+		name 'DAC Polarity'
+		value 'No Inversion'
+		comment {
+			access 'read write'
+			type ENUMERATED
+			count 1
+			item.0 'No Inversion'
+			item.1 'Left Inverted'
+			item.2 'Right Inverted'
+			item.3 'Stereo Inversion'
+		}
+	}
+	control.21 {
+		iface MIXER
+		name 'DAC Deemphasis Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.22 {
+		iface MIXER
+		name '3D Filter Upper Cut-Off'
+		value High
+		comment {
+			access 'read write'
+			type ENUMERATED
+			count 1
+			item.0 High
+			item.1 Low
+		}
+	}
+	control.23 {
+		iface MIXER
+		name '3D Filter Lower Cut-Off'
+		value Low
+		comment {
+			access 'read write'
+			type ENUMERATED
+			count 1
+			item.0 Low
+			item.1 High
+		}
+	}
+	control.24 {
+		iface MIXER
+		name '3D Volume'
+		value 0
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 15'
+		}
+	}
+	control.25 {
+		iface MIXER
+		name '3D Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.26 {
+		iface MIXER
+		name 'ALC Function'
+		value Off
+		comment {
+			access 'read write'
+			type ENUMERATED
+			count 1
+			item.0 Off
+			item.1 Right
+			item.2 Left
+			item.3 Stereo
+		}
+	}
+	control.27 {
+		iface MIXER
+		name 'ALC Max Gain'
+		value 7
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 7'
+		}
+	}
+	control.28 {
+		iface MIXER
+		name 'ALC Target'
+		value 4
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 15'
+		}
+	}
+	control.29 {
+		iface MIXER
+		name 'ALC Min Gain'
+		value 0
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 7'
+		}
+	}
+	control.30 {
+		iface MIXER
+		name 'ALC Hold Time'
+		value 0
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 15'
+		}
+	}
+	control.31 {
+		iface MIXER
+		name 'ALC Mode'
+		value ALC
+		comment {
+			access 'read write'
+			type ENUMERATED
+			count 1
+			item.0 ALC
+			item.1 Limiter
+		}
+	}
+	control.32 {
+		iface MIXER
+		name 'ALC Decay'
+		value 3
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 15'
+		}
+	}
+	control.33 {
+		iface MIXER
+		name 'ALC Attack'
+		value 2
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 15'
+		}
+	}
+	control.34 {
+		iface MIXER
+		name 'Noise Gate Threshold'
+		value 0
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 31'
+		}
+	}
+	control.35 {
+		iface MIXER
+		name 'Noise Gate Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.36 {
+		iface MIXER
+		name 'ADC PCM Capture Volume'
+		value.0 195
+		value.1 195
+		comment {
+			access 'read write'
+			type INTEGER
+			count 2
+			range '0 - 255'
+			dbmin -9999999
+			dbmax 3000
+			dbvalue.0 0
+			dbvalue.1 0
+		}
+	}
+	control.37 {
+		iface MIXER
+		name 'Left Output Mixer Boost Bypass Volume'
+		value 0
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 7'
+			dbmin -2100
+			dbmax 0
+			dbvalue.0 -2100
+		}
+	}
+	control.38 {
+		iface MIXER
+		name 'Left Output Mixer LINPUT3 Volume'
+		value 0
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 7'
+			dbmin -2100
+			dbmax 0
+			dbvalue.0 -2100
+		}
+	}
+	control.39 {
+		iface MIXER
+		name 'Right Output Mixer Boost Bypass Volume'
+		value 5
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 7'
+			dbmin -2100
+			dbmax 0
+			dbvalue.0 -600
+		}
+	}
+	control.40 {
+		iface MIXER
+		name 'Right Output Mixer RINPUT3 Volume'
+		value 2
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 7'
+			dbmin -2100
+			dbmax 0
+			dbvalue.0 -1500
+		}
+	}
+	control.41 {
+		iface MIXER
+		name 'ADC Data Output Select'
+		value 'Left Data = Left ADC;  Right Data = Right ADC'
+		comment {
+			access 'read write'
+			type ENUMERATED
+			count 1
+			item.0 'Left Data = Left ADC;  Right Data = Right ADC'
+			item.1 'Left Data = Left ADC;  Right Data = Left ADC'
+			item.2 'Left Data = Right ADC; Right Data = Right ADC'
+			item.3 'Left Data = Right ADC; Right Data = Left ADC'
+		}
+	}
+	control.42 {
+		iface MIXER
+		name 'DAC Mono Mix'
+		value Stereo
+		comment {
+			access 'read write'
+			type ENUMERATED
+			count 1
+			item.0 Stereo
+			item.1 Mono
+		}
+	}
+	control.43 {
+		iface MIXER
+		name 'Left Boost Mixer LINPUT2 Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.44 {
+		iface MIXER
+		name 'Left Boost Mixer LINPUT3 Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.45 {
+		iface MIXER
+		name 'Left Boost Mixer LINPUT1 Switch'
+		value true
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.46 {
+		iface MIXER
+		name 'Right Boost Mixer RINPUT2 Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.47 {
+		iface MIXER
+		name 'Right Boost Mixer RINPUT3 Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.48 {
+		iface MIXER
+		name 'Right Boost Mixer RINPUT1 Switch'
+		value true
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.49 {
+		iface MIXER
+		name 'Left Input Mixer Boost Switch'
+		value true
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.50 {
+		iface MIXER
+		name 'Right Input Mixer Boost Switch'
+		value true
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.51 {
+		iface MIXER
+		name 'Left Output Mixer PCM Playback Switch'
+		value true
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.52 {
+		iface MIXER
+		name 'Left Output Mixer LINPUT3 Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.53 {
+		iface MIXER
+		name 'Left Output Mixer Boost Bypass Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.54 {
+		iface MIXER
+		name 'Right Output Mixer PCM Playback Switch'
+		value true
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.55 {
+		iface MIXER
+		name 'Right Output Mixer RINPUT3 Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.56 {
+		iface MIXER
+		name 'Right Output Mixer Boost Bypass Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.57 {
+		iface MIXER
+		name 'Mono Output Mixer Left Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.58 {
+		iface MIXER
+		name 'Mono Output Mixer Right Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+}
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/sht3x/Makefile b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/sht3x/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..be3eec6ce047fc075b749fafa17d189563c5e5c2
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/sht3x/Makefile
@@ -0,0 +1,46 @@
+#
+# Peter Yang <turmary@126.com>
+# Copyright (c) 2019 Seeed Studio
+#
+# MIT License
+#
+
+_tgt     := sht3x
+
+_uname_r := $(shell uname -r)
+_BUILD   := /lib/modules/$(_uname_r)/build
+_PWD     := $(shell pwd)
+_DEPMOD  ?= depmod -a
+
+# If KERNELRELEASE is defined, we've been invoked from the
+# kernel build system and can use its language
+ifneq ($(KERNELRELEASE),)
+
+# signal_pending compability
+ifneq ($(wildcard $(_BUILD)/include/linux/sched/signal.h),)
+ccflags-y += -DSCHED_SIGNAL_H=1
+endif
+
+obj-m += ${_tgt}.o
+
+else
+_class  := drivers/misc
+
+DEST  := /lib/modules/$(_uname_r)/kernel
+
+all:
+	make -C ${_BUILD} M=$(_PWD) modules
+
+clean:
+	make -C ${_BUILD} M=$(_PWD) clean
+
+install:
+	cp ${_tgt}.ko ${DEST}/${_class}/
+	$(_DEPMOD)
+
+uninstall:
+	rm -f ${DEST}/${_class}/${_tgt}.ko
+	$(_DEPMOD)
+
+.PHONY: all clean install uninstall
+endif
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/sht3x/README.md b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/sht3x/README.md
new file mode 100644
index 0000000000000000000000000000000000000000..9039602b180e93e981b0a54a47cf699ddae0bdfc
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/sht3x/README.md
@@ -0,0 +1,25 @@
+## Grove Temperature sensor SHT31
+
+### Introduction of sensor
+SHT3x-DIS is the next generation of Sensirion’s temperature and humidity sensors. It builds on a new CMOSens® sensor chip that is at the heart of Sensirion’s new humidity and temperature platform.   
+
+
+
+## Usage: 
+* Get sht31's data by instruction below:
+
+        sudo cat /dev/sht3x_dev<0~n>
+        The number <0~n> depends on how many sht3x devices attached,default is 0.
+
+* The console will print msg below:
+
+        temperature = 23.68℃
+        humidity = 69.15%
+        temperature = 23.65℃
+        humidity = 69.5%
+        ..
+  User can test the sensor with warming it.
+
+***
+
+
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/sht3x/sht3x.c b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/sht3x/sht3x.c
new file mode 100644
index 0000000000000000000000000000000000000000..6a9e58cba457c32ea29a53cbf296c1ed02ba61a9
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/sht3x/sht3x.c
@@ -0,0 +1,326 @@
+/*
+ * sht3x.c
+ * Library for sht3x temperature sensor.
+ *
+ * Copyright (c) 2018 seeed technology inc.
+ * The MIT License (MIT)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/i2c.h>
+#include <linux/err.h>
+#include <linux/slab.h>
+#include <linux/uaccess.h>
+#include <linux/kthread.h>
+#include <linux/timer.h>
+#include <linux/delay.h>
+#include <linux/string.h>
+#include <linux/kdev_t.h>
+#include <linux/sysfs.h>
+
+/**************************************************************************************************************/
+/**************************************************************************************************************/
+
+
+
+#define  MAX_NAME_LEN   30
+#define AMPLIFICAT_NUM   100
+
+
+static int dev_cnt = -1;
+struct sht3x_dev *sht3x_info_buf[256];
+
+
+struct sht3x_dev
+{
+	int major;
+	struct class *sht3x_cls;
+	struct device *sht3x_dev;
+	char class_name[MAX_NAME_LEN];
+	char device_name[MAX_NAME_LEN];
+	struct i2c_client *client;
+	int32_t humidity;
+	int32_t temperature;
+};
+
+
+/*********************************************sht3x api***********************************************************/
+
+static uint8_t sht3x_crc8(const uint8_t *data, int len)
+{
+	int i,j;
+	const uint8_t POLYNOMIAL=0x31;
+	uint8_t crc=0xFF;
+
+
+	for (  j = len; j; --j ) {
+	crc ^= *data++;
+
+		for ( i = 8; i; --i ) {
+			crc = ( crc & 0x80 )
+				? (crc << 1) ^ POLYNOMIAL
+				: (crc << 1);
+		}
+	}
+	return crc;
+}
+
+
+
+static int32_t sht3x_read_temperature(struct i2c_client *client)
+{
+	uint8_t pdata = 0x00;
+	uint8_t rdata[6] = {0};
+	struct sht3x_dev *sht3x_info = NULL;
+	sht3x_info = i2c_get_clientdata(client);
+	if(i2c_smbus_write_i2c_block_data(client,0x24,1,&pdata)){
+		printk(KERN_ALERT "Smbus send bytes failed\n");
+		
+		return -1;
+	}
+	msleep(20);
+	if(i2c_smbus_read_i2c_block_data(client,0x00,6,rdata) < 0){
+		printk(KERN_ALERT "Smbus read bytes failed\n");
+		return -1;
+	}
+	if((rdata[2] != sht3x_crc8(rdata,2)) || (rdata[5] != sht3x_crc8(&rdata[3],2)) ){
+		printk(KERN_ALERT "Crc failed!\n");
+		return -2;
+	}
+
+	sht3x_info->temperature = rdata[0] * 256 + rdata[1];
+	sht3x_info->temperature = -45 * AMPLIFICAT_NUM + (175 * sht3x_info->temperature *AMPLIFICAT_NUM / 65535);
+	sht3x_info->humidity = AMPLIFICAT_NUM * (rdata[3]* 256 + rdata[4]) * AMPLIFICAT_NUM / 65535;
+	// printk(KERN_INFO "read temperature = %d\n",sht3x_info->temperature);
+	// printk(KERN_INFO "read humidity = %d\n",sht3x_info->humidity);	
+	return 0;
+}
+
+
+
+/***************************************************** sysfs interface *****************************************/
+/***************************************************** sysfs interface *****************************************/
+/***************************************************** sysfs interface *****************************************/
+
+static ssize_t sht3x_temperature_show(struct kobject* kobjs,struct kobj_attribute *attr,char *buf)
+{
+	struct i2c_client *client = NULL;
+	uint8_t dis_buf[50] = {0};
+
+	client = sht3x_info_buf[dev_cnt]->client;
+
+	if(sht3x_read_temperature(client)){
+		sprintf(dis_buf,"Read sensor failed\n");
+		return 0;
+	}
+
+	else {
+		return sprintf(buf,"temperature = %d.%d℃ \nhumidity = %d.%d%% \n\n",
+			sht3x_info_buf[dev_cnt]->temperature / AMPLIFICAT_NUM,
+			sht3x_info_buf[dev_cnt]->temperature % AMPLIFICAT_NUM,
+			sht3x_info_buf[dev_cnt]->humidity / AMPLIFICAT_NUM,
+			sht3x_info_buf[dev_cnt]->humidity % AMPLIFICAT_NUM);
+	}
+	return 0;
+}
+static struct kobj_attribute status_attr = __ATTR_RO(sht3x_temperature);
+
+
+/*************************************************** file operations ********************************************/
+/*************************************************** file operations ********************************************/
+/*************************************************** file operations ********************************************/
+static int sht3x_i2c_open(struct inode *node, struct file *file)
+{
+	return 0;
+}
+
+static ssize_t sht3x_i2c_read(struct file *file,char *buf, size_t len,loff_t *offset)
+{
+	struct i2c_client *client = NULL;
+	uint32_t buf_len = 0;
+	uint8_t dis_buf[50] = {0};
+
+	client = sht3x_info_buf[dev_cnt]->client;
+
+	if(sht3x_read_temperature(client)){
+		sprintf(dis_buf,"Read sensor failed\n");
+	}
+
+	else {
+		sprintf(dis_buf,"temperature = %d.%d℃ \nhumidity = %d.%d%% \n\n",
+		sht3x_info_buf[dev_cnt]->temperature / AMPLIFICAT_NUM,
+		sht3x_info_buf[dev_cnt]->temperature % AMPLIFICAT_NUM,
+		sht3x_info_buf[dev_cnt]->humidity / AMPLIFICAT_NUM,
+		sht3x_info_buf[dev_cnt]->humidity % AMPLIFICAT_NUM);
+	}
+	buf_len = strlen(dis_buf);
+	if(copy_to_user(buf,dis_buf,strlen(dis_buf))){
+		printk(KERN_INFO "copy to user failed\n");
+		return -ENOMEM;
+	}
+	return buf_len;
+}
+
+
+static struct file_operations file_oprts = {
+	.open = sht3x_i2c_open,
+	.read = sht3x_i2c_read,
+};
+
+
+
+static void sht3x_dev_init(struct sht3x_dev *sht3x_info)
+{
+	sprintf(sht3x_info->class_name,"%s%d","sht3x_cls",dev_cnt);
+	sprintf(sht3x_info->device_name,"%s%d","sht3x_dev",dev_cnt);
+}
+
+
+static int sht3x_drv_probe(struct i2c_client *client, const struct i2c_device_id *id)
+{
+	struct sht3x_dev *sht3x_info = NULL;
+	// printk(KERN_INFO "Probe!\n");
+
+	if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) {
+		dev_err(&client->dev, "i2c_check_functionality error\n");
+		return -EIO;
+	}
+
+	sht3x_info = kmalloc(sizeof(*sht3x_info),GFP_KERNEL);    
+	if(NULL == sht3x_info){
+		return -ENOMEM;
+	}
+
+	sht3x_info_buf[++dev_cnt] = sht3x_info;
+
+	sht3x_dev_init(sht3x_info);
+
+	sht3x_info->client = client;
+	i2c_set_clientdata(client,sht3x_info);
+	// dev_set_drvdata(&client->dev,sht3x_info);
+
+	sht3x_read_temperature(client);
+
+
+	if(sysfs_create_file(&sht3x_info->client->dev.kobj, &status_attr.attr) < 0){
+		printk(KERN_ALERT "Fail to create sys file\n");
+		kfree(sht3x_info);
+		return -ENOMEM;
+    	}
+
+	sht3x_info->major = register_chrdev(0,sht3x_info->device_name,&file_oprts);
+	if(sht3x_info->major < 0 ){
+		
+		sysfs_remove_file(&sht3x_info->client->dev.kobj, &status_attr.attr);
+		printk(KERN_ALERT "Register failed!!\r\n");
+		kfree(sht3x_info);
+		return sht3x_info->major;
+	}
+	// printk(KERN_ALERT "Registe success,sht3x_info->major number = %d\r\n",sht3x_info->major);
+
+	sht3x_info->sht3x_cls = class_create(THIS_MODULE,sht3x_info->class_name);
+	if(IS_ERR(sht3x_info->sht3x_cls)){
+		unregister_chrdev(sht3x_info->major,sht3x_info->device_name);
+		sysfs_remove_file(&sht3x_info->client->dev.kobj, &status_attr.attr);
+		kfree(sht3x_info);
+		return PTR_ERR(sht3x_info->sht3x_cls);
+	}
+
+	sht3x_info->sht3x_dev = device_create(sht3x_info->sht3x_cls,NULL,MKDEV(sht3x_info->major,0),NULL,sht3x_info->device_name);
+	if(IS_ERR(sht3x_info->sht3x_dev)){
+		
+		sysfs_remove_file(&sht3x_info->client->dev.kobj, &status_attr.attr);
+		class_destroy(sht3x_info->sht3x_cls);
+		unregister_chrdev(sht3x_info->major,sht3x_info->device_name);
+		kfree(sht3x_info);
+		return PTR_ERR(sht3x_info->sht3x_dev);
+	}
+    	// printk(KERN_ALERT "sht3x_i2c device init success!!\r\n");
+    
+    	return 0;
+}
+
+static int sht3x_drv_remove(struct i2c_client *client)
+{
+	struct sht3x_dev *sht3x_info = NULL;
+	sht3x_info = i2c_get_clientdata(client);
+
+	sysfs_remove_file(&sht3x_info->client->dev.kobj, &status_attr.attr);
+	device_destroy(sht3x_info->sht3x_cls,MKDEV(sht3x_info->major,0));
+	class_unregister(sht3x_info->sht3x_cls);
+	class_destroy(sht3x_info->sht3x_cls);
+	unregister_chrdev(sht3x_info->major,sht3x_info->device_name);
+	kfree(sht3x_info);
+    	return 0;
+}
+
+
+static const struct i2c_device_id sht3x_drv_id_table[] = {
+	{"sht3x",0},
+	{},
+};
+
+static const struct of_device_id sht3x_match_table[] = {
+	{.compatible = "sensirion,sht3x"},
+	{},
+};
+
+
+static struct i2c_driver sht3x_drv = {
+	.driver = {
+		.name = "sht3x",
+		.owner = THIS_MODULE,
+		.of_match_table = of_match_ptr(sht3x_match_table),
+	},
+	.probe = sht3x_drv_probe,
+	.remove = sht3x_drv_remove,
+	.id_table = sht3x_drv_id_table,
+};
+
+MODULE_DEVICE_TABLE(of,sht3x_match_table);
+
+
+int drv_init(void)
+{
+	int ret = 0;
+	ret  = i2c_add_driver(&sht3x_drv);
+	if(ret){
+		printk(KERN_ALERT "add driver failed!!!\n");
+		return -ENODEV;
+	}
+	return 0;
+}
+
+
+void drv_exit(void)
+{
+	i2c_del_driver(&sht3x_drv);
+	return ;
+}
+
+
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("This module is for Seeed sht3x ranging sensor.");
+MODULE_AUTHOR("Downey");
+
+module_init(drv_init);
+module_exit(drv_exit);
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/sii902x/Makefile b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/sii902x/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..5af89555b80106be4e41dc56b4456e2a856d7451
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/sii902x/Makefile
@@ -0,0 +1,35 @@
+
+
+_uname_r := $(shell uname -r)
+_BUILD   := /lib/modules/$(_uname_r)/build
+_PWD     := $(shell pwd)
+_DEPMOD  ?= depmod -a
+
+# If KERNELRELEASE is defined, we've been invoked from the
+# kernel build system and can use its language
+ifneq ($(KERNELRELEASE),)
+
+
+obj-m += mxsfb_sii902x.o
+
+else
+_class  := drivers/input
+
+DEST  := /lib/modules/$(_uname_r)/kernel
+
+all:
+	make -C ${_BUILD} M=$(_PWD) modules
+
+clean:
+	make -C ${_BUILD} M=$(_PWD) clean
+
+install:
+	cp mxsfb_sii902x.ko ${DEST}/${_class}/
+	$(_DEPMOD)
+
+uninstall:
+	rm -f ${DEST}/${_class}/mxsfb_sii902x.ko 
+	$(_DEPMOD)
+
+.PHONY: all clean install uninstall
+endif
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/sii902x/mxsfb_sii902x.c b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/sii902x/mxsfb_sii902x.c
new file mode 100644
index 0000000000000000000000000000000000000000..97c46b6dc0e677e3d175c5ea0a677f1774bc39bf
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/sii902x/mxsfb_sii902x.c
@@ -0,0 +1,527 @@
+/*
+ * Copyright (C) 2010-2015 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @defgroup Framebuffer Framebuffer Driver for Sii902x.
+ */
+
+/*!
+ * @file mxsfb_sii902x.c
+ *
+ * @brief  Frame buffer driver for SII902x
+ *
+ * @ingroup Framebuffer
+ */
+
+/*!
+ * Include files
+ */
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/console.h>
+#include <linux/delay.h>
+#include <linux/errno.h>
+#include <linux/fb.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/regulator/consumer.h>
+#include <linux/i2c.h>
+#include <linux/fsl_devices.h>
+#include <linux/interrupt.h>
+#include <linux/reset.h>
+#include <asm/mach-types.h>
+#include <video/mxc_edid.h>
+
+#define SII_EDID_LEN	512
+#define DRV_NAME "sii902x"
+
+struct sii902x_data {
+	struct i2c_client *client;
+	struct delayed_work det_work;
+	struct fb_info *fbi;
+	struct mxc_edid_cfg edid_cfg;
+	u8 cable_plugin;
+	u8 edid[SII_EDID_LEN];
+	bool dft_mode_set;
+	const char *mode_str;
+	int bits_per_pixel;
+} sii902x;
+
+static void sii902x_poweron(void);
+static void sii902x_poweroff(void);
+
+#ifdef DEBUG
+static void dump_fb_videomode(struct fb_videomode *m)
+{
+	pr_debug("fb_videomode = %d %d %d %d %d %d %d %d %d %d %d %d %d\n",
+		m->refresh, m->xres, m->yres, m->pixclock, m->left_margin,
+		m->right_margin, m->upper_margin, m->lower_margin,
+		m->hsync_len, m->vsync_len, m->sync, m->vmode, m->flag);
+}
+#else
+static void dump_fb_videomode(struct fb_videomode *m)
+{}
+#endif
+
+static __attribute__ ((unused)) void dump_regs(u8 reg, int len)
+{
+	u8 buf[50];
+	int i;
+
+	i2c_smbus_read_i2c_block_data(sii902x.client, reg, len, buf);
+	for (i = 0; i < len; i++)
+		dev_dbg(&sii902x.client->dev, "reg[0x%02X]: 0x%02X\n",
+				i+reg, buf[i]);
+}
+
+static ssize_t sii902x_show_name(struct device *dev,
+		struct device_attribute *attr, char *buf)
+{
+	strcpy(buf, sii902x.fbi->fix.id);
+	sprintf(buf+strlen(buf), "\n");
+
+	return strlen(buf);
+}
+
+static DEVICE_ATTR(fb_name, S_IRUGO, sii902x_show_name, NULL);
+
+static ssize_t sii902x_show_state(struct device *dev,
+		struct device_attribute *attr, char *buf)
+{
+	if (sii902x.cable_plugin == 0)
+		strcpy(buf, "plugout\n");
+	else
+		strcpy(buf, "plugin\n");
+
+	return strlen(buf);
+}
+
+static DEVICE_ATTR(cable_state, S_IRUGO, sii902x_show_state, NULL);
+
+static ssize_t sii902x_show_edid(struct device *dev,
+		struct device_attribute *attr, char *buf)
+{
+	int i, j, len = 0;
+
+	for (j = 0; j < SII_EDID_LEN/16; j++) {
+		for (i = 0; i < 16; i++)
+			len += sprintf(buf+len, "0x%02X ",
+					sii902x.edid[j*16 + i]);
+		len += sprintf(buf+len, "\n");
+	}
+
+	return len;
+}
+
+static DEVICE_ATTR(edid, S_IRUGO, sii902x_show_edid, NULL);
+
+static void sii902x_setup(struct fb_info *fbi)
+{
+	u16 data[4];
+	u32 refresh;
+	u8 *tmp;
+	int i;
+
+	dev_dbg(&sii902x.client->dev, "Sii902x: setup..\n");
+
+	/* Power up */
+	i2c_smbus_write_byte_data(sii902x.client, 0x1E, 0x00);
+
+	/* set TPI video mode */
+	data[0] = PICOS2KHZ(fbi->var.pixclock) / 10;
+	data[2] = fbi->var.hsync_len + fbi->var.left_margin +
+		  fbi->var.xres + fbi->var.right_margin;
+	data[3] = fbi->var.vsync_len + fbi->var.upper_margin +
+		  fbi->var.yres + fbi->var.lower_margin;
+	refresh = data[2] * data[3];
+	refresh = (PICOS2KHZ(fbi->var.pixclock) * 1000) / refresh;
+	data[1] = refresh * 100;
+	tmp = (u8 *)data;
+	for (i = 0; i < 8; i++)
+		i2c_smbus_write_byte_data(sii902x.client, i, tmp[i]);
+
+	/* input bus/pixel: full pixel wide (24bit), rising edge */
+	i2c_smbus_write_byte_data(sii902x.client, 0x08, 0x70);
+	/* Set input format to RGB */
+	i2c_smbus_write_byte_data(sii902x.client, 0x09, 0x00);
+	/* set output format to RGB */
+	i2c_smbus_write_byte_data(sii902x.client, 0x0A, 0x00);
+}
+
+static void sii902x_audio_setup(void)
+{
+	/* audio setup */
+	i2c_smbus_write_byte_data(sii902x.client, 0x25, 0x00);
+	i2c_smbus_write_byte_data(sii902x.client, 0x26, 0x40);
+	i2c_smbus_write_byte_data(sii902x.client, 0x27, 0x00);
+}
+
+#ifdef CONFIG_FB_MODE_HELPERS
+static int sii902x_read_edid(struct fb_info *fbi)
+{
+	int old, dat, ret, cnt = 100;
+	unsigned short addr = 0x50;
+
+	dev_dbg(&sii902x.client->dev, "%s\n", __func__);
+
+	old = i2c_smbus_read_byte_data(sii902x.client, 0x1A);
+
+	i2c_smbus_write_byte_data(sii902x.client, 0x1A, old | 0x4);
+	do {
+		cnt--;
+		msleep(10);
+		dat = i2c_smbus_read_byte_data(sii902x.client, 0x1A);
+	} while ((!(dat & 0x2)) && cnt);
+
+	if (!cnt) {
+		ret = -1;
+		goto done;
+	}
+
+	i2c_smbus_write_byte_data(sii902x.client, 0x1A, old | 0x06);
+
+	/* edid reading */
+	ret = mxc_edid_read(sii902x.client->adapter, addr,
+				sii902x.edid, &sii902x.edid_cfg, fbi);
+
+	cnt = 100;
+	do {
+		cnt--;
+		i2c_smbus_write_byte_data(sii902x.client, 0x1A, old & ~0x6);
+		msleep(10);
+		dat = i2c_smbus_read_byte_data(sii902x.client, 0x1A);
+	} while ((dat & 0x6) && cnt);
+
+	if (!cnt)
+		ret = -1;
+
+done:
+
+	i2c_smbus_write_byte_data(sii902x.client, 0x1A, old);
+	return ret;
+}
+#else
+static int sii902x_read_edid(struct fb_info *fbi)
+{
+	return -1;
+}
+#endif
+
+static void sii902x_cable_connected(void)
+{
+	int i;
+	const struct fb_videomode *mode;
+	struct fb_videomode m;
+
+	if (sii902x_read_edid(sii902x.fbi) < 0)
+		dev_err(&sii902x.client->dev,
+			"Sii902x: read edid fail\n");
+	else {
+		if (sii902x.fbi->monspecs.modedb_len > 0) {
+
+			fb_destroy_modelist(&sii902x.fbi->modelist);
+
+			for (i = 0; i < sii902x.fbi->monspecs.modedb_len; i++) {
+
+				mode = &sii902x.fbi->monspecs.modedb[i];
+
+				if (!(mode->vmode & FB_VMODE_INTERLACED)) {
+					dev_dbg(&sii902x.client->dev, "Added mode %d:", i);
+					dev_dbg(&sii902x.client->dev,
+						"xres = %d, yres = %d, freq = %d, vmode = %d, flag = %d\n",
+						mode->xres, mode->yres, mode->refresh,
+						mode->vmode, mode->flag);
+
+					fb_add_videomode(mode, &sii902x.fbi->modelist);
+				}
+			}
+
+			/* Set the default mode only once. */
+			if (!sii902x.dft_mode_set &&
+					sii902x.mode_str && sii902x.bits_per_pixel) {
+
+				dev_dbg(&sii902x.client->dev, "%s: setting to default=%s bpp=%d\n",
+						__func__, sii902x.mode_str, sii902x.bits_per_pixel);
+
+				fb_find_mode(&sii902x.fbi->var, sii902x.fbi,
+						sii902x.mode_str, NULL, 0, NULL,
+						sii902x.bits_per_pixel);
+
+				sii902x.dft_mode_set = true;
+			}
+
+			fb_var_to_videomode(&m, &sii902x.fbi->var);
+			dump_fb_videomode(&m);
+
+			mode = fb_find_nearest_mode(&m,
+					&sii902x.fbi->modelist);
+
+			/* update fbi mode  */
+			sii902x.fbi->mode = (struct fb_videomode *)mode;
+
+			fb_videomode_to_var(&sii902x.fbi->var, mode);
+
+			sii902x.fbi->var.activate |= FB_ACTIVATE_FORCE;
+			console_lock();
+			sii902x.fbi->flags |= FBINFO_MISC_USEREVENT;
+			fb_set_var(sii902x.fbi, &sii902x.fbi->var);
+			sii902x.fbi->flags &= ~FBINFO_MISC_USEREVENT;
+			console_unlock();
+		}
+		/* Power on sii902x */
+		sii902x_poweron();
+	}
+}
+
+static void det_worker(struct work_struct *work)
+{
+	int dat;
+	char event_string[16];
+	char *envp[] = { event_string, NULL };
+
+	dev_dbg(&sii902x.client->dev, "%s\n", __func__);
+
+	dat = i2c_smbus_read_byte_data(sii902x.client, 0x3D);
+
+	/* cable connection state */
+	if (dat & 0x4) {
+		sii902x.cable_plugin = 1;
+		dev_dbg(&sii902x.client->dev, "EVENT=plugin\n");
+		sprintf(event_string, "EVENT=plugin");
+		sii902x_cable_connected();
+	} else {
+		sii902x.cable_plugin = 0;
+		dev_dbg(&sii902x.client->dev, "EVENT=plugout\n");
+		sprintf(event_string, "EVENT=plugout");
+		/* Power off sii902x */
+		sii902x_poweroff();
+	}
+	kobject_uevent_env(&sii902x.client->dev.kobj, KOBJ_CHANGE, envp);
+
+	i2c_smbus_write_byte_data(sii902x.client, 0x3D, dat);
+
+	dev_dbg(&sii902x.client->dev, "exit %s\n", __func__);
+
+}
+
+static irqreturn_t sii902x_detect_handler(int irq, void *data)
+{
+	if (sii902x.fbi)
+		schedule_delayed_work(&(sii902x.det_work), msecs_to_jiffies(50));
+
+	return IRQ_HANDLED;
+}
+
+static int sii902x_fb_event(struct notifier_block *nb, unsigned long val, void *v)
+{
+	struct fb_event *event = v;
+	struct fb_info *fbi = event->info;
+
+	dev_dbg(&sii902x.client->dev, "%s event=0x%lx\n", __func__, val);
+
+	switch (val) {
+	case FB_EVENT_FB_REGISTERED:
+		if (sii902x.fbi == NULL)
+			sii902x.fbi = fbi;
+		/* Manually trigger a plugin/plugout interrupter to check cable state */
+		schedule_delayed_work(&(sii902x.det_work), msecs_to_jiffies(50));
+
+		fb_show_logo(fbi, 0);
+
+		break;
+	case FB_EVENT_MODE_CHANGE:
+		sii902x_setup(fbi);
+		break;
+	case FB_EVENT_BLANK:
+		if (*((int *)event->data) == FB_BLANK_UNBLANK) {
+			dev_dbg(&sii902x.client->dev, "FB_BLANK_UNBLANK\n");
+			sii902x_poweron();
+		} else {
+			dev_dbg(&sii902x.client->dev, "FB_BLANK_BLANK\n");
+			sii902x_poweroff();
+		}
+		break;
+	}
+	return 0;
+}
+
+static struct notifier_block nb = {
+	.notifier_call = sii902x_fb_event,
+};
+
+static int mxsfb_get_of_property(void)
+{
+	struct device_node *np = sii902x.client->dev.of_node;
+	const char *mode_str;
+	int bits_per_pixel, ret;
+
+	ret = of_property_read_string(np, "mode_str", &mode_str);
+	if (ret < 0) {
+		dev_warn(&sii902x.client->dev, "get of property mode_str fail\n");
+		return ret;
+	}
+	ret = of_property_read_u32(np, "bits-per-pixel", &bits_per_pixel);
+	if (ret) {
+		dev_warn(&sii902x.client->dev, "get of property bpp fail\n");
+		return ret;
+	}
+
+	sii902x.mode_str = mode_str;
+	sii902x.bits_per_pixel = bits_per_pixel;
+
+	return ret;
+}
+
+static int sii902x_probe(struct i2c_client *client,
+		const struct i2c_device_id *id)
+{
+	int i, dat, ret;
+	struct fb_info edid_fbi;
+
+	memset(&sii902x, 0, sizeof(sii902x));
+
+	sii902x.client = client;
+
+	dev_dbg(&sii902x.client->dev, "%s\n", __func__);;
+
+	/* Reset sii902x */
+	ret = device_reset(&sii902x.client->dev);
+	if (ret)
+		dev_warn(&sii902x.client->dev, "No reset pin found\n");
+
+	/* Set 902x in hardware TPI mode on and jump out of D3 state */
+	if (i2c_smbus_write_byte_data(sii902x.client, 0xc7, 0x00) < 0) {
+		dev_err(&sii902x.client->dev,
+			"Sii902x: cound not find device\n");
+		return -ENODEV;
+	}
+
+	/* read device ID */
+	for (i = 10; i > 0; i--) {
+		dat = i2c_smbus_read_byte_data(sii902x.client, 0x1B);
+		printk(KERN_DEBUG "Sii902x: read id = 0x%02X", dat);
+		if (dat == 0xb0) {
+			dat = i2c_smbus_read_byte_data(sii902x.client, 0x1C);
+			printk(KERN_DEBUG "-0x%02X", dat);
+			dat = i2c_smbus_read_byte_data(sii902x.client, 0x1D);
+			printk(KERN_DEBUG "-0x%02X", dat);
+			dat = i2c_smbus_read_byte_data(sii902x.client, 0x30);
+			printk(KERN_DEBUG "-0x%02X\n", dat);
+			break;
+		}
+	}
+	if (i == 0) {
+		dev_err(&sii902x.client->dev,
+			"Sii902x: cound not find device\n");
+		return -ENODEV;
+	}
+
+	/* enable hmdi audio */
+	sii902x_audio_setup();
+
+	/* try to read edid */
+	ret = sii902x_read_edid(&edid_fbi);
+	if (ret < 0)
+		dev_warn(&sii902x.client->dev, "Can not read edid\n");
+
+	if (sii902x.client->irq) {
+		ret = request_irq(sii902x.client->irq, sii902x_detect_handler,
+				IRQF_TRIGGER_FALLING,
+				"SII902x_det", &sii902x);
+		if (ret < 0)
+			dev_warn(&sii902x.client->dev,
+				"Sii902x: cound not request det irq %d\n",
+				sii902x.client->irq);
+		else {
+			/*enable cable hot plug irq*/
+			i2c_smbus_write_byte_data(sii902x.client, 0x3c, 0x01);
+			INIT_DELAYED_WORK(&(sii902x.det_work), det_worker);
+		}
+		ret = device_create_file(&sii902x.client->dev, &dev_attr_fb_name);
+		if (ret < 0)
+			dev_warn(&sii902x.client->dev,
+				"Sii902x: cound not create sys node for fb name\n");
+		ret = device_create_file(&sii902x.client->dev, &dev_attr_cable_state);
+		if (ret < 0)
+			dev_warn(&sii902x.client->dev,
+				"Sii902x: cound not create sys node for cable state\n");
+		ret = device_create_file(&sii902x.client->dev, &dev_attr_edid);
+		if (ret < 0)
+			dev_warn(&sii902x.client->dev,
+				"Sii902x: cound not create sys node for edid\n");
+
+	}
+
+	mxsfb_get_of_property();
+	fb_register_client(&nb);
+
+	return 0;
+}
+
+static int sii902x_remove(struct i2c_client *client)
+{
+	fb_unregister_client(&nb);
+	sii902x_poweroff();
+
+	return 0;
+}
+
+static void sii902x_poweron(void)
+{
+	/* Turn on DVI or HDMI */
+	if (sii902x.edid_cfg.hdmi_cap)
+		i2c_smbus_write_byte_data(sii902x.client, 0x1A, 0x01);
+	else
+		i2c_smbus_write_byte_data(sii902x.client, 0x1A, 0x00);
+	return;
+}
+
+static void sii902x_poweroff(void)
+{
+	/* disable tmds before changing resolution */
+	if (sii902x.edid_cfg.hdmi_cap)
+		i2c_smbus_write_byte_data(sii902x.client, 0x1A, 0x11);
+	else
+		i2c_smbus_write_byte_data(sii902x.client, 0x1A, 0x10);
+
+	return;
+}
+
+static const struct i2c_device_id sii902x_id[] = {
+	{ DRV_NAME, 0},
+	{ },
+};
+MODULE_DEVICE_TABLE(i2c, sii902x_id);
+
+static const struct of_device_id sii902x_dt_ids[] = {
+	{ .compatible = "SiI,sii902x", },
+	{ /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, sii902x_dt_ids);
+
+static struct i2c_driver sii902x_driver = {
+	.driver = {
+		.name = DRV_NAME,
+		.owner = THIS_MODULE,
+		.of_match_table = sii902x_dt_ids,
+	},
+	.probe		= sii902x_probe,
+	.remove		= sii902x_remove,
+	.id_table	= sii902x_id,
+};
+
+module_i2c_driver(sii902x_driver);
+
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_DESCRIPTION("SII902x DVI/HDMI driver");
+MODULE_LICENSE("GPL");
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/vl53l0x/Makefile b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/vl53l0x/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..7ca0a990d62c20c173c2e21ea21a52c3d3af7b7d
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/vl53l0x/Makefile
@@ -0,0 +1,46 @@
+#
+# Peter Yang <turmary@126.com>
+# Copyright (c) 2019 Seeed Studio
+#
+# MIT License
+#
+
+_tgt     := vl53l0x
+
+_uname_r := $(shell uname -r)
+_BUILD   := /lib/modules/$(_uname_r)/build
+_PWD     := $(shell pwd)
+_DEPMOD  ?= depmod -a
+
+# If KERNELRELEASE is defined, we've been invoked from the
+# kernel build system and can use its language
+ifneq ($(KERNELRELEASE),)
+
+# signal_pending compability
+ifneq ($(wildcard $(_BUILD)/include/linux/sched/signal.h),)
+ccflags-y += -DSCHED_SIGNAL_H=1
+endif
+
+obj-m += ${_tgt}.o
+
+else
+_class  := drivers/misc
+
+DEST  := /lib/modules/$(_uname_r)/kernel
+
+all:
+	make -C ${_BUILD} M=$(_PWD) modules
+
+clean:
+	make -C ${_BUILD} M=$(_PWD) clean
+
+install:
+	cp ${_tgt}.ko ${DEST}/${_class}/
+	$(_DEPMOD)
+
+uninstall:
+	rm -f ${DEST}/${_class}/${_tgt}.ko
+	$(_DEPMOD)
+
+.PHONY: all clean install uninstall
+endif
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/vl53l0x/Readme.md b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/vl53l0x/Readme.md
new file mode 100644
index 0000000000000000000000000000000000000000..ecb5213e4feed4a37cd36ebda2d29bbb9cf46b18
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/vl53l0x/Readme.md
@@ -0,0 +1,23 @@
+# Grove Ranging sensor VL53L0X
+#####    --World’s smallest Time-of-Flight ranging and gesture detection sensor  
+---------------------------------------------
+
+## Introduction:  
+ 
+>The VL53L0X is a new generation Time-of-Flight(ToF) laser-ranging module housed in the smallest package on the market today,providing accurate distance measurement whatever the target reflectances unlike conventional technologies.  
+
+***
+
+## Usage: 
+* Get VL53L0X's data by instruction below:
+
+        sudo cat /dev/vl53l0x_dev
+
+* The console will print msg below:
+
+        Object Distance = 37 mm
+        Object Distance = 38 mm
+        Object Distance = 45 mm
+  User can test the sensor with moving it.
+
+***
\ No newline at end of file
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/vl53l0x/vl53l0x.c b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/vl53l0x/vl53l0x.c
new file mode 100644
index 0000000000000000000000000000000000000000..0ba55db7df0949d9be0ba149fe76ea202d5a7804
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/vl53l0x/vl53l0x.c
@@ -0,0 +1,9112 @@
+/*
+ * vl53l0x.c
+ * Library for ranging sensor.
+ *
+ * Copyright (c) 2018 seeed technology inc.
+ * The MIT License (MIT)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/i2c.h>
+#include <linux/err.h>
+#include <linux/slab.h>
+#include <linux/uaccess.h>
+#include <linux/kthread.h>
+#include <linux/timer.h>
+#include <linux/delay.h>
+#include <linux/string.h>
+#include <linux/kdev_t.h>
+#include <linux/sysfs.h>
+
+
+/**************************************************************************************************************/
+/**************************************************************************************************************/
+/***************************************************driver*****************************************************/
+
+
+struct i2c_client *vl53l0x_client;
+typedef unsigned long long uint64_t;
+typedef unsigned int uint32_t;
+typedef int int32_t;
+typedef unsigned short uint16_t;
+typedef short int16_t;
+typedef unsigned char uint8_t;
+typedef signed char int8_t;
+typedef uint32_t FixPoint1616_t;
+typedef uint8_t VL53L0X_DeviceError;
+typedef uint8_t VL53L0X_GpioFunctionality;
+typedef int8_t  VL53L0X_Error;
+typedef uint8_t VL53L0X_DeviceModes;
+typedef uint8_t VL53L0X_PowerModes;
+typedef uint8_t VL53L0X_State;
+typedef uint8_t VL53L0X_InterruptPolarity;
+typedef uint8_t VL53L0X_VcselPeriod;
+
+#define LOG_FUNCTION_START(fmt, ...) \
+	_LOG_FUNCTION_START(TRACE_MODULE_API, fmt, ##__VA_ARGS__)
+#define LOG_FUNCTION_END(status, ...) \
+	_LOG_FUNCTION_END(TRACE_MODULE_API, status, ##__VA_ARGS__)
+#define LOG_FUNCTION_END_FMT(status, fmt, ...) \
+	_LOG_FUNCTION_END_FMT(TRACE_MODULE_API, status, fmt, ##__VA_ARGS__)
+
+#define VL53L0X_CHECKENABLE_SIGMA_FINAL_RANGE           0
+#define VL53L0X_CHECKENABLE_SIGNAL_RATE_FINAL_RANGE     1
+#define VL53L0X_CHECKENABLE_SIGNAL_REF_CLIP             2
+#define VL53L0X_CHECKENABLE_RANGE_IGNORE_THRESHOLD      3
+#define VL53L0X_CHECKENABLE_SIGNAL_RATE_MSRC            4
+#define VL53L0X_CHECKENABLE_SIGNAL_RATE_PRE_RANGE       5
+
+#define VL53L0X_CHECKENABLE_NUMBER_OF_CHECKS            6
+#define VERSION_REQUIRED_MAJOR 1
+#define VERSION_REQUIRED_MINOR 0
+#define VERSION_REQUIRED_BUILD 1
+#define REF_ARRAY_SPAD_0  0
+#define REF_ARRAY_SPAD_5  5
+#define REF_ARRAY_SPAD_10 10
+
+#define I2C_BUFFER_CONFIG 1
+#define VL53L0X_MAX_I2C_XFER_SIZE   64 /* Maximum buffer size to be used in i2c */
+
+#if I2C_BUFFER_CONFIG == 0
+	uint8_t i2c_global_buffer[VL53L0X_MAX_I2C_XFER_SIZE];
+	#define DECL_I2C_BUFFER
+	#define VL53L0X_GetLocalBuffer(Dev, n_byte)  i2c_global_buffer
+
+#elif I2C_BUFFER_CONFIG == 1
+	#define DECL_I2C_BUFFER  uint8_t LocBuffer[VL53L0X_MAX_I2C_XFER_SIZE];
+	#define VL53L0X_GetLocalBuffer(Dev, n_byte)  LocBuffer
+#elif I2C_BUFFER_CONFIG == 2
+	/* user define buffer type declare DECL_I2C_BUFFER  as access  via VL53L0X_GetLocalBuffer */
+	#define DECL_I2C_BUFFER
+#else
+	#error "invalid I2C_BUFFER_CONFIG "
+#endif
+
+
+#define VL53L0X_I2C_USER_VAR         /* none but could be for a flag var to get/pass to mutex interruptible  return flags and try again */
+#define VL53L0X_GetI2CAccess(Dev)    /* todo mutex acquire */
+#define VL53L0X_DoneI2CAcces(Dev)    /* todo mutex release */
+
+#define VL53L0X10_SPECIFICATION_VER_MAJOR   1
+/** PAL SPECIFICATION minor version */
+#define VL53L0X10_SPECIFICATION_VER_MINOR   2
+/** PAL SPECIFICATION sub version */
+#define VL53L0X10_SPECIFICATION_VER_SUB	   7
+/** PAL SPECIFICATION sub version */
+#define VL53L0X10_SPECIFICATION_VER_REVISION 1440
+
+/** VL53L0X PAL IMPLEMENTATION major version */
+#define VL53L0X10_IMPLEMENTATION_VER_MAJOR	1
+/** VL53L0X PAL IMPLEMENTATION minor version */
+#define VL53L0X10_IMPLEMENTATION_VER_MINOR	0
+/** VL53L0X PAL IMPLEMENTATION sub version */
+#define VL53L0X10_IMPLEMENTATION_VER_SUB		9
+/** VL53L0X PAL IMPLEMENTATION sub version */
+#define VL53L0X10_IMPLEMENTATION_VER_REVISION	3673
+
+/** PAL SPECIFICATION major version */
+#define VL53L0X_SPECIFICATION_VER_MAJOR	 1
+/** PAL SPECIFICATION minor version */
+#define VL53L0X_SPECIFICATION_VER_MINOR	 2
+/** PAL SPECIFICATION sub version */
+#define VL53L0X_SPECIFICATION_VER_SUB	 7
+/** PAL SPECIFICATION sub version */
+#define VL53L0X_SPECIFICATION_VER_REVISION 1440
+
+/** VL53L0X PAL IMPLEMENTATION major version */
+#define VL53L0X_IMPLEMENTATION_VER_MAJOR	  1
+/** VL53L0X PAL IMPLEMENTATION minor version */
+#define VL53L0X_IMPLEMENTATION_VER_MINOR	  0
+/** VL53L0X PAL IMPLEMENTATION sub version */
+#define VL53L0X_IMPLEMENTATION_VER_SUB	  1
+/** VL53L0X PAL IMPLEMENTATION sub version */
+#define VL53L0X_IMPLEMENTATION_VER_REVISION	  4606
+#define VL53L0X_DEFAULT_MAX_LOOP 200
+#define VL53L0X_MAX_STRING_LENGTH 32
+
+#define VL53L0X_HISTOGRAM_BUFFER_SIZE 24
+
+/** @brief Defines the parameters of the Get Version Functions
+ */
+typedef struct {
+	uint32_t	 revision; /*!< revision number */
+	uint8_t		 major;	   /*!< major number */
+	uint8_t		 minor;	   /*!< minor number */
+	uint8_t		 build;	   /*!< build number */
+} VL53L0X_Version_t;
+
+/** @brief Defines the parameters of the Get Device Info Functions
+ */
+typedef struct {
+	char Name[VL53L0X_MAX_STRING_LENGTH];
+	char Type[VL53L0X_MAX_STRING_LENGTH];
+	char ProductId[VL53L0X_MAX_STRING_LENGTH];
+	uint8_t ProductType;
+	uint8_t ProductRevisionMajor;
+	uint8_t ProductRevisionMinor;
+} VL53L0X_DeviceInfo_t;
+
+
+/** @defgroup VL53L0X_define_Error_group Error and Warning code returned by API
+ *	The following DEFINE are used to identify the PAL ERROR
+ *	@{
+ */
+
+#define VL53L0X_ERROR_NONE		((VL53L0X_Error)	0)
+#define VL53L0X_ERROR_CALIBRATION_WARNING	((VL53L0X_Error) -1)
+#define VL53L0X_ERROR_MIN_CLIPPED			((VL53L0X_Error) -2)
+	/*!< Warning parameter passed was clipped to min before to be applied */
+
+#define VL53L0X_ERROR_UNDEFINED				((VL53L0X_Error) -3)
+	/*!< Unqualified error */
+#define VL53L0X_ERROR_INVALID_PARAMS			((VL53L0X_Error) -4)
+	/*!< Parameter passed is invalid or out of range */
+#define VL53L0X_ERROR_NOT_SUPPORTED			((VL53L0X_Error) -5)
+	/*!< Function is not supported in current mode or configuration */
+#define VL53L0X_ERROR_RANGE_ERROR			((VL53L0X_Error) -6)
+	/*!< Device report a ranging error interrupt status */
+#define VL53L0X_ERROR_TIME_OUT				((VL53L0X_Error) -7)
+	/*!< Aborted due to time out */
+#define VL53L0X_ERROR_MODE_NOT_SUPPORTED			((VL53L0X_Error) -8)
+	/*!< Asked mode is not supported by the device */
+#define VL53L0X_ERROR_BUFFER_TOO_SMALL			((VL53L0X_Error) -9)
+	/*!< ... */
+#define VL53L0X_ERROR_GPIO_NOT_EXISTING			((VL53L0X_Error) -10)
+	/*!< User tried to setup a non-existing GPIO pin */
+#define VL53L0X_ERROR_GPIO_FUNCTIONALITY_NOT_SUPPORTED  ((VL53L0X_Error) -11)
+	/*!< unsupported GPIO functionality */
+#define VL53L0X_ERROR_INTERRUPT_NOT_CLEARED		((VL53L0X_Error) -12)
+	/*!< Error during interrupt clear */
+#define VL53L0X_ERROR_CONTROL_INTERFACE			((VL53L0X_Error) -20)
+	/*!< error reported from IO functions */
+#define VL53L0X_ERROR_INVALID_COMMAND			((VL53L0X_Error) -30)
+	/*!< The command is not allowed in the current device state
+	 *	(power down) */
+#define VL53L0X_ERROR_DIVISION_BY_ZERO			((VL53L0X_Error) -40)
+	/*!< In the function a division by zero occurs */
+#define VL53L0X_ERROR_REF_SPAD_INIT			((VL53L0X_Error) -50)
+	/*!< Error during reference SPAD initialization */
+#define VL53L0X_ERROR_NOT_IMPLEMENTED			((VL53L0X_Error) -99)
+	/*!< Tells requested functionality has not been implemented yet or
+	 * not compatible with the device */
+/** @} VL53L0X_define_Error_group */
+
+
+
+#define VL53L0X_DEVICEMODE_SINGLE_RANGING	((VL53L0X_DeviceModes)  0)
+#define VL53L0X_DEVICEMODE_CONTINUOUS_RANGING	((VL53L0X_DeviceModes)  1)
+#define VL53L0X_DEVICEMODE_SINGLE_HISTOGRAM	((VL53L0X_DeviceModes)  2)
+#define VL53L0X_DEVICEMODE_CONTINUOUS_TIMED_RANGING ((VL53L0X_DeviceModes) 3)
+#define VL53L0X_DEVICEMODE_SINGLE_ALS		((VL53L0X_DeviceModes) 10)
+#define VL53L0X_DEVICEMODE_GPIO_DRIVE		((VL53L0X_DeviceModes) 20)
+#define VL53L0X_DEVICEMODE_GPIO_OSC		((VL53L0X_DeviceModes) 21)
+
+/** @defgroup VL53L0X_define_HistogramModes_group Defines Histogram modes
+ *	Defines all possible Histogram modes for the device
+ *	@{
+ */
+typedef uint8_t VL53L0X_HistogramModes;
+
+#define VL53L0X_HISTOGRAMMODE_DISABLED		((VL53L0X_HistogramModes) 0)
+	/*!< Histogram Disabled */
+#define VL53L0X_HISTOGRAMMODE_REFERENCE_ONLY	((VL53L0X_HistogramModes) 1)
+	/*!< Histogram Reference array only */
+#define VL53L0X_HISTOGRAMMODE_RETURN_ONLY	((VL53L0X_HistogramModes) 2)
+	/*!< Histogram Return array only */
+#define VL53L0X_HISTOGRAMMODE_BOTH		((VL53L0X_HistogramModes) 3)
+	/*!< Histogram both Reference and Return Arrays */
+	/* ... Modes to be added depending on device */
+/** @} VL53L0X_define_HistogramModes_group */
+
+#define VL53L0X_POWERMODE_STANDBY_LEVEL1 ((VL53L0X_PowerModes) 0)
+	/*!< Standby level 1 */
+#define VL53L0X_POWERMODE_STANDBY_LEVEL2 ((VL53L0X_PowerModes) 1)
+	/*!< Standby level 2 */
+#define VL53L0X_POWERMODE_IDLE_LEVEL1	((VL53L0X_PowerModes) 2)
+	/*!< Idle level 1 */
+#define VL53L0X_POWERMODE_IDLE_LEVEL2	((VL53L0X_PowerModes) 3)
+	/*!< Idle level 2 */
+
+/** @} VL53L0X_define_PowerModes_group */
+
+/** @brief Defines all parameters for the device
+ */
+typedef struct {
+	VL53L0X_DeviceModes DeviceMode;
+	/*!< Defines type of measurement to be done for the next measure */
+	VL53L0X_HistogramModes HistogramMode;
+	/*!< Defines type of histogram measurement to be done for the next
+	 *	measure */
+	uint32_t MeasurementTimingBudgetMicroSeconds;
+	/*!< Defines the allowed total time for a single measurement */
+	uint32_t InterMeasurementPeriodMilliSeconds;
+	/*!< Defines time between two consecutive measurements (between two
+	 *	measurement starts). If set to 0 means back-to-back mode */
+	uint8_t XTalkCompensationEnable;
+	/*!< Tells if Crosstalk compensation shall be enable or not	 */
+	uint16_t XTalkCompensationRangeMilliMeter;
+	/*!< CrossTalk compensation range in millimeter	 */
+	FixPoint1616_t XTalkCompensationRateMegaCps;
+	/*!< CrossTalk compensation rate in Mega counts per seconds.
+	 *	Expressed in 16.16 fixed point format.	*/
+	int32_t RangeOffsetMicroMeters;
+	/*!< Range offset adjustment (mm).	*/
+
+	uint8_t LimitChecksEnable[VL53L0X_CHECKENABLE_NUMBER_OF_CHECKS];
+	/*!< This Array store all the Limit Check enable for this device. */
+	uint8_t LimitChecksStatus[VL53L0X_CHECKENABLE_NUMBER_OF_CHECKS];
+	/*!< This Array store all the Status of the check linked to last
+	* measurement. */
+	FixPoint1616_t LimitChecksValue[VL53L0X_CHECKENABLE_NUMBER_OF_CHECKS];
+	/*!< This Array store all the Limit Check value for this device */
+
+	uint8_t WrapAroundCheckEnable;
+	/*!< Tells if Wrap Around Check shall be enable or not */
+} VL53L0X_DeviceParameters_t;
+
+
+/** @defgroup VL53L0X_define_State_group Defines the current status of the device
+ *	Defines the current status of the device
+ *	@{
+ */
+
+#define VL53L0X_STATE_POWERDOWN		 ((VL53L0X_State)  0)
+	/*!< Device is in HW reset	*/
+#define VL53L0X_STATE_WAIT_STATICINIT ((VL53L0X_State)  1)
+	/*!< Device is initialized and wait for static initialization  */
+#define VL53L0X_STATE_STANDBY		 ((VL53L0X_State)  2)
+	/*!< Device is in Low power Standby mode   */
+#define VL53L0X_STATE_IDLE			 ((VL53L0X_State)  3)
+	/*!< Device has been initialized and ready to do measurements  */
+#define VL53L0X_STATE_RUNNING		 ((VL53L0X_State)  4)
+	/*!< Device is performing measurement */
+#define VL53L0X_STATE_UNKNOWN		 ((VL53L0X_State)  98)
+	/*!< Device is in unknown state and need to be rebooted	 */
+#define VL53L0X_STATE_ERROR			 ((VL53L0X_State)  99)
+	/*!< Device is in error state and need to be rebooted  */
+
+
+/** @brief Structure containing the Dmax computation parameters and data
+ */
+typedef struct {
+	int32_t AmbTuningWindowFactor_K;
+	int32_t RetSignalAt0mm;
+} VL53L0X_DMaxData_t;
+
+/**
+ * @struct VL53L0X_RangeData_t
+ * @brief Range measurement data.
+ */
+typedef struct {
+	uint32_t TimeStamp;		/*!< 32-bit time stamp. */
+	uint32_t MeasurementTimeUsec;
+
+	uint16_t RangeMilliMeter;	/*!< range distance in millimeter. */
+	uint16_t RangeDMaxMilliMeter;
+	FixPoint1616_t SignalRateRtnMegaCps;
+	FixPoint1616_t AmbientRateRtnMegaCps;
+	uint16_t EffectiveSpadRtnCount;
+	uint8_t ZoneId;
+	uint8_t RangeFractionalPart;
+	uint8_t RangeStatus;
+} VL53L0X_RangingMeasurementData_t;
+
+
+
+/**
+ * @struct VL53L0X_HistogramData_t
+ * @brief Histogram measurement data.
+ */
+typedef struct {
+	/* Histogram Measurement data */
+	uint32_t HistogramData[VL53L0X_HISTOGRAM_BUFFER_SIZE];
+	/*!< Histogram data */
+	uint8_t HistogramType; /*!< Indicate the types of histogram data :
+	Return only, Reference only, both Return and Reference */
+	uint8_t FirstBin; /*!< First Bin value */
+	uint8_t BufferSize; /*!< Buffer Size - Set by the user.*/
+	uint8_t NumberOfBins;
+	/*!< Number of bins filled by the histogram measurement */
+
+	VL53L0X_DeviceError ErrorStatus;
+	/*!< Error status of the current measurement. \n
+	see @a ::VL53L0X_DeviceError @a VL53L0X_GetStatusErrorString() */
+} VL53L0X_HistogramMeasurementData_t;
+
+#define VL53L0X_REF_SPAD_BUFFER_SIZE 6
+
+/**
+ * @struct VL53L0X_SpadData_t
+ * @brief Spad Configuration Data.
+ */
+typedef struct {
+	uint8_t RefSpadEnables[VL53L0X_REF_SPAD_BUFFER_SIZE];
+	/*!< Reference Spad Enables */
+	uint8_t RefGoodSpadMap[VL53L0X_REF_SPAD_BUFFER_SIZE];
+	/*!< Reference Spad Good Spad Map */
+} VL53L0X_SpadData_t;
+
+typedef struct {
+	FixPoint1616_t OscFrequencyMHz; /* Frequency used */
+
+	uint16_t LastEncodedTimeout;
+	/* last encoded Time out used for timing budget*/
+
+	VL53L0X_GpioFunctionality Pin0GpioFunctionality;
+	/* store the functionality of the GPIO: pin0 */
+
+	uint32_t FinalRangeTimeoutMicroSecs;
+	 /*!< Execution time of the final range*/
+	uint8_t FinalRangeVcselPulsePeriod;
+	 /*!< Vcsel pulse period (pll clocks) for the final range measurement*/
+	uint32_t PreRangeTimeoutMicroSecs;
+	 /*!< Execution time of the final range*/
+	uint8_t PreRangeVcselPulsePeriod;
+	 /*!< Vcsel pulse period (pll clocks) for the pre-range measurement*/
+
+	uint16_t SigmaEstRefArray;
+	 /*!< Reference array sigma value in 1/100th of [mm] e.g. 100 = 1mm */
+	uint16_t SigmaEstEffPulseWidth;
+	 /*!< Effective Pulse width for sigma estimate in 1/100th
+	  * of ns e.g. 900 = 9.0ns */
+	uint16_t SigmaEstEffAmbWidth;
+	 /*!< Effective Ambient width for sigma estimate in 1/100th of ns
+	  * e.g. 500 = 5.0ns */
+
+
+	uint8_t ReadDataFromDeviceDone; /* Indicate if read from device has
+	been done (==1) or not (==0) */
+	uint8_t ModuleId; /* Module ID */
+	uint8_t Revision; /* test Revision */
+	char ProductId[VL53L0X_MAX_STRING_LENGTH];
+		/* Product Identifier String  */
+	uint8_t ReferenceSpadCount; /* used for ref spad management */
+	uint8_t ReferenceSpadType;	/* used for ref spad management */
+	uint8_t RefSpadsInitialised; /* reports if ref spads are initialised. */
+	uint32_t PartUIDUpper; /*!< Unique Part ID Upper */
+	uint32_t PartUIDLower; /*!< Unique Part ID Lower */
+	FixPoint1616_t SignalRateMeasFixed400mm; /*!< Peek Signal rate
+	at 400 mm*/
+
+} VL53L0X_DeviceSpecificParameters_t;
+
+/**
+ * @struct VL53L0X_DevData_t
+ *
+ * @brief VL53L0X PAL device ST private data structure \n
+ * End user should never access any of these field directly
+ *
+ * These must never access directly but only via macro
+ */
+typedef struct {
+	VL53L0X_DMaxData_t DMaxData;
+	/*!< Dmax Data */
+	int32_t	 Part2PartOffsetNVMMicroMeter;
+	/*!< backed up NVM value */
+	int32_t	 Part2PartOffsetAdjustmentNVMMicroMeter;
+	/*!< backed up NVM value representing additional offset adjustment */
+	VL53L0X_DeviceParameters_t CurrentParameters;
+	/*!< Current Device Parameter */
+	VL53L0X_RangingMeasurementData_t LastRangeMeasure;
+	/*!< Ranging Data */
+	VL53L0X_HistogramMeasurementData_t LastHistogramMeasure;
+	/*!< Histogram Data */
+	VL53L0X_DeviceSpecificParameters_t DeviceSpecificParameters;
+	/*!< Parameters specific to the device */
+	VL53L0X_SpadData_t SpadData;
+	/*!< Spad Data */
+	uint8_t SequenceConfig;
+	/*!< Internal value for the sequence config */
+	uint8_t RangeFractionalEnable;
+	/*!< Enable/Disable fractional part of ranging data */
+	VL53L0X_State PalState;
+	/*!< Current state of the PAL for this device */
+	VL53L0X_PowerModes PowerMode;
+	/*!< Current Power Mode	 */
+	uint16_t SigmaEstRefArray;
+	/*!< Reference array sigma value in 1/100th of [mm] e.g. 100 = 1mm */
+	uint16_t SigmaEstEffPulseWidth;
+	/*!< Effective Pulse width for sigma estimate in 1/100th
+	* of ns e.g. 900 = 9.0ns */
+	uint16_t SigmaEstEffAmbWidth;
+	/*!< Effective Ambient width for sigma estimate in 1/100th of ns
+	* e.g. 500 = 5.0ns */
+	uint8_t StopVariable;
+	/*!< StopVariable used during the stop sequence */
+	uint16_t targetRefRate;
+	/*!< Target Ambient Rate for Ref spad management */
+	FixPoint1616_t SigmaEstimate;
+	/*!< Sigma Estimate - based on ambient & VCSEL rates and
+	* signal_total_events */
+	FixPoint1616_t SignalEstimate;
+	/*!< Signal Estimate - based on ambient & VCSEL rates and cross talk */
+	FixPoint1616_t LastSignalRefMcps;
+	/*!< Latest Signal ref in Mcps */
+	uint8_t *pTuningSettingsPointer;
+	/*!< Pointer for Tuning Settings table */
+	uint8_t UseInternalTuningSettings;
+	/*!< Indicate if we use	 Tuning Settings table */
+	uint16_t LinearityCorrectiveGain;
+	/*!< Linearity Corrective Gain value in x1000 */
+	uint16_t DmaxCalRangeMilliMeter;
+	/*!< Dmax Calibration Range millimeter */
+	FixPoint1616_t DmaxCalSignalRateRtnMegaCps;
+	/*!< Dmax Calibration Signal Rate Return MegaCps */
+
+} VL53L0X_DevData_t;
+
+
+/** @defgroup VL53L0X_define_InterruptPolarity_group Defines the Polarity
+ * of the Interrupt
+ *	Defines the Polarity of the Interrupt
+ *	@{
+ */
+
+#define VL53L0X_INTERRUPTPOLARITY_LOW	   ((VL53L0X_InterruptPolarity)	0)
+/*!< Set active low polarity best setup for falling edge. */
+#define VL53L0X_INTERRUPTPOLARITY_HIGH	   ((VL53L0X_InterruptPolarity)	1)
+/*!< Set active high polarity best setup for rising edge. */
+
+/** @defgroup VL53L0X_define_VcselPeriod_group Vcsel Period Defines
+ *	Defines the range measurement for which to access the vcsel period.
+ *	@{
+ */
+
+
+#define VL53L0X_VCSEL_PERIOD_PRE_RANGE	((VL53L0X_VcselPeriod) 0)
+/*!<Identifies the pre-range vcsel period. */
+#define VL53L0X_VCSEL_PERIOD_FINAL_RANGE ((VL53L0X_VcselPeriod) 1)
+/*!<Identifies the final range vcsel period. */
+
+/** @} VL53L0X_define_VcselPeriod_group */
+
+/** @defgroup VL53L0X_define_SchedulerSequence_group Defines the steps
+ * carried out by the scheduler during a range measurement.
+ *	@{
+ *	Defines the states of all the steps in the scheduler
+ *	i.e. enabled/disabled.
+ */
+typedef struct {
+	uint8_t		 TccOn;	   /*!<Reports if Target Centre Check On  */
+	uint8_t		 MsrcOn;	   /*!<Reports if MSRC On  */
+	uint8_t		 DssOn;		   /*!<Reports if DSS On  */
+	uint8_t		 PreRangeOn;   /*!<Reports if Pre-Range On	*/
+	uint8_t		 FinalRangeOn; /*!<Reports if Final-Range On  */
+} VL53L0X_SchedulerSequenceSteps_t;
+
+/** @} VL53L0X_define_SchedulerSequence_group */
+
+/** @defgroup VL53L0X_define_SequenceStepId_group Defines the Polarity
+ *	of the Interrupt
+ *	Defines the the sequence steps performed during ranging..
+ *	@{
+ */
+typedef uint8_t VL53L0X_SequenceStepId;
+
+#define	 VL53L0X_SEQUENCESTEP_TCC		 ((VL53L0X_VcselPeriod) 0)
+/*!<Target CentreCheck identifier. */
+#define	 VL53L0X_SEQUENCESTEP_DSS		 ((VL53L0X_VcselPeriod) 1)
+/*!<Dynamic Spad Selection function Identifier. */
+#define	 VL53L0X_SEQUENCESTEP_MSRC		 ((VL53L0X_VcselPeriod) 2)
+/*!<Minimum Signal Rate Check function Identifier. */
+#define	 VL53L0X_SEQUENCESTEP_PRE_RANGE	 ((VL53L0X_VcselPeriod) 3)
+/*!<Pre-Range check Identifier. */
+#define	 VL53L0X_SEQUENCESTEP_FINAL_RANGE ((VL53L0X_VcselPeriod) 4)
+/*!<Final Range Check Identifier. */
+
+#define	 VL53L0X_SEQUENCESTEP_NUMBER_OF_CHECKS			 5
+/*!<Number of Sequence Step Managed by the API. */
+
+/** @} VL53L0X_define_SequenceStepId_group */
+
+
+/* MACRO Definitions */
+/** @defgroup VL53L0X_define_GeneralMacro_group General Macro Defines
+ *	General Macro Defines
+ *	@{
+ */
+
+/* Defines */
+#define VL53L0X_SETPARAMETERFIELD(Dev, field, value) \
+	PALDevDataSet(Dev, CurrentParameters.field, value)
+
+#define VL53L0X_GETPARAMETERFIELD(Dev, field, variable) \
+	variable = PALDevDataGet(Dev, CurrentParameters).field
+
+
+#define VL53L0X_SETARRAYPARAMETERFIELD(Dev, field, index, value) \
+	PALDevDataSet(Dev, CurrentParameters.field[index], value)
+
+#define VL53L0X_GETARRAYPARAMETERFIELD(Dev, field, index, variable) \
+	variable = PALDevDataGet(Dev, CurrentParameters).field[index]
+
+
+#define VL53L0X_SETDEVICESPECIFICPARAMETER(Dev, field, value) \
+		PALDevDataSet(Dev, DeviceSpecificParameters.field, value)
+
+#define VL53L0X_GETDEVICESPECIFICPARAMETER(Dev, field) \
+		PALDevDataGet(Dev, DeviceSpecificParameters).field
+
+
+#define VL53L0X_FIXPOINT1616TOFIXPOINT97(Value) \
+	(uint16_t)((Value>>9)&0xFFFF)
+#define VL53L0X_FIXPOINT97TOFIXPOINT1616(Value) \
+	(FixPoint1616_t)(Value<<9)
+
+#define VL53L0X_FIXPOINT1616TOFIXPOINT88(Value) \
+	(uint16_t)((Value>>8)&0xFFFF)
+#define VL53L0X_FIXPOINT88TOFIXPOINT1616(Value) \
+	(FixPoint1616_t)(Value<<8)
+
+#define VL53L0X_FIXPOINT1616TOFIXPOINT412(Value) \
+	(uint16_t)((Value>>4)&0xFFFF)
+#define VL53L0X_FIXPOINT412TOFIXPOINT1616(Value) \
+	(FixPoint1616_t)(Value<<4)
+
+#define VL53L0X_FIXPOINT1616TOFIXPOINT313(Value) \
+	(uint16_t)((Value>>3)&0xFFFF)
+#define VL53L0X_FIXPOINT313TOFIXPOINT1616(Value) \
+	(FixPoint1616_t)(Value<<3)
+
+#define VL53L0X_FIXPOINT1616TOFIXPOINT08(Value) \
+	(uint8_t)((Value>>8)&0x00FF)
+#define VL53L0X_FIXPOINT08TOFIXPOINT1616(Value) \
+	(FixPoint1616_t)(Value<<8)
+
+#define VL53L0X_FIXPOINT1616TOFIXPOINT53(Value) \
+	(uint8_t)((Value>>13)&0x00FF)
+#define VL53L0X_FIXPOINT53TOFIXPOINT1616(Value) \
+	(FixPoint1616_t)(Value<<13)
+
+#define VL53L0X_FIXPOINT1616TOFIXPOINT102(Value) \
+	(uint16_t)((Value>>14)&0x0FFF)
+#define VL53L0X_FIXPOINT102TOFIXPOINT1616(Value) \
+	(FixPoint1616_t)(Value<<12)
+
+#define VL53L0X_MAKEUINT16(lsb, msb) (uint16_t)((((uint16_t)msb)<<8) + \
+		(uint16_t)lsb)
+
+
+typedef struct {
+    VL53L0X_DevData_t Data;               /*!< embed ST Ewok Dev  data as "Data"*/
+
+    /*!< user specific field */
+    uint8_t   I2cDevAddr;                /*!< i2c device address user specific field */
+    uint8_t   comms_type;                /*!< Type of comms : VL53L0X_COMMS_I2C or VL53L0X_COMMS_SPI */
+    uint16_t  comms_speed_khz;           /*!< Comms speed [kHz] : typically 400kHz for I2C           */
+
+} VL53L0X_Dev_t;
+
+
+typedef VL53L0X_Dev_t* VL53L0X_DEV;
+
+#define PALDevDataGet(Dev, field) (Dev->Data.field)
+#define PALDevDataSet(Dev, field, data) (Dev->Data.field)=(data)
+
+#ifdef USE_EMPTY_STRING
+	#define  VL53L0X_STRING_DEVICE_INFO_NAME                             ""
+	#define  VL53L0X_STRING_DEVICE_INFO_NAME_TS0                         ""
+	#define  VL53L0X_STRING_DEVICE_INFO_NAME_TS1                         ""
+	#define  VL53L0X_STRING_DEVICE_INFO_NAME_TS2                         ""
+	#define  VL53L0X_STRING_DEVICE_INFO_NAME_ES1                         ""
+	#define  VL53L0X_STRING_DEVICE_INFO_TYPE                             ""
+
+	/* PAL ERROR strings */
+	#define  VL53L0X_STRING_ERROR_NONE                                   ""
+	#define  VL53L0X_STRING_ERROR_CALIBRATION_WARNING                    ""
+	#define  VL53L0X_STRING_ERROR_MIN_CLIPPED                            ""
+	#define  VL53L0X_STRING_ERROR_UNDEFINED                              ""
+	#define  VL53L0X_STRING_ERROR_INVALID_PARAMS                         ""
+	#define  VL53L0X_STRING_ERROR_NOT_SUPPORTED                          ""
+	#define  VL53L0X_STRING_ERROR_RANGE_ERROR                            ""
+	#define  VL53L0X_STRING_ERROR_TIME_OUT                               ""
+	#define  VL53L0X_STRING_ERROR_MODE_NOT_SUPPORTED                     ""
+	#define  VL53L0X_STRING_ERROR_BUFFER_TOO_SMALL                       ""
+	#define  VL53L0X_STRING_ERROR_GPIO_NOT_EXISTING                      ""
+	#define  VL53L0X_STRING_ERROR_GPIO_FUNCTIONALITY_NOT_SUPPORTED       ""
+	#define  VL53L0X_STRING_ERROR_CONTROL_INTERFACE                      ""
+	#define  VL53L0X_STRING_ERROR_INVALID_COMMAND                        ""
+	#define  VL53L0X_STRING_ERROR_DIVISION_BY_ZERO                       ""
+	#define  VL53L0X_STRING_ERROR_REF_SPAD_INIT                          ""
+	#define  VL53L0X_STRING_ERROR_NOT_IMPLEMENTED                        ""
+
+	#define  VL53L0X_STRING_UNKNOW_ERROR_CODE                            ""
+
+
+
+	/* Range Status */
+	#define  VL53L0X_STRING_RANGESTATUS_NONE                             ""
+	#define  VL53L0X_STRING_RANGESTATUS_RANGEVALID                       ""
+	#define  VL53L0X_STRING_RANGESTATUS_SIGMA                            ""
+	#define  VL53L0X_STRING_RANGESTATUS_SIGNAL                           ""
+	#define  VL53L0X_STRING_RANGESTATUS_MINRANGE                         ""
+	#define  VL53L0X_STRING_RANGESTATUS_PHASE                            ""
+	#define  VL53L0X_STRING_RANGESTATUS_HW                               ""
+
+
+	/* Range Status */
+	#define  VL53L0X_STRING_STATE_POWERDOWN                              ""
+	#define  VL53L0X_STRING_STATE_WAIT_STATICINIT                        ""
+	#define  VL53L0X_STRING_STATE_STANDBY                                ""
+	#define  VL53L0X_STRING_STATE_IDLE                                   ""
+	#define  VL53L0X_STRING_STATE_RUNNING                                ""
+	#define  VL53L0X_STRING_STATE_UNKNOWN                                ""
+	#define  VL53L0X_STRING_STATE_ERROR                                  ""
+
+
+	/* Device Specific */
+	#define  VL53L0X_STRING_DEVICEERROR_NONE                             ""
+	#define  VL53L0X_STRING_DEVICEERROR_VCSELCONTINUITYTESTFAILURE       ""
+	#define  VL53L0X_STRING_DEVICEERROR_VCSELWATCHDOGTESTFAILURE         ""
+	#define  VL53L0X_STRING_DEVICEERROR_NOVHVVALUEFOUND                  ""
+	#define  VL53L0X_STRING_DEVICEERROR_MSRCNOTARGET                     ""
+	#define  VL53L0X_STRING_DEVICEERROR_SNRCHECK                         ""
+	#define  VL53L0X_STRING_DEVICEERROR_RANGEPHASECHECK                  ""
+	#define  VL53L0X_STRING_DEVICEERROR_SIGMATHRESHOLDCHECK              ""
+	#define  VL53L0X_STRING_DEVICEERROR_TCC                              ""
+	#define  VL53L0X_STRING_DEVICEERROR_PHASECONSISTENCY                 ""
+	#define  VL53L0X_STRING_DEVICEERROR_MINCLIP                          ""
+	#define  VL53L0X_STRING_DEVICEERROR_RANGECOMPLETE                    ""
+	#define  VL53L0X_STRING_DEVICEERROR_ALGOUNDERFLOW                    ""
+	#define  VL53L0X_STRING_DEVICEERROR_ALGOOVERFLOW                     ""
+	#define  VL53L0X_STRING_DEVICEERROR_RANGEIGNORETHRESHOLD             ""
+	#define  VL53L0X_STRING_DEVICEERROR_UNKNOWN                          ""
+
+	/* Check Enable */
+	#define  VL53L0X_STRING_CHECKENABLE_SIGMA_FINAL_RANGE                ""
+	#define  VL53L0X_STRING_CHECKENABLE_SIGNAL_RATE_FINAL_RANGE          ""
+	#define  VL53L0X_STRING_CHECKENABLE_SIGNAL_REF_CLIP                  ""
+	#define  VL53L0X_STRING_CHECKENABLE_RANGE_IGNORE_THRESHOLD           ""
+
+	/* Sequence Step */
+	#define  VL53L0X_STRING_SEQUENCESTEP_TCC                             ""
+	#define  VL53L0X_STRING_SEQUENCESTEP_DSS                             ""
+	#define  VL53L0X_STRING_SEQUENCESTEP_MSRC                            ""
+	#define  VL53L0X_STRING_SEQUENCESTEP_PRE_RANGE                       ""
+	#define  VL53L0X_STRING_SEQUENCESTEP_FINAL_RANGE                     ""
+#else
+	#define  VL53L0X_STRING_DEVICE_INFO_NAME          "VL53L0X cut1.0"
+	#define  VL53L0X_STRING_DEVICE_INFO_NAME_TS0      "VL53L0X TS0"
+	#define  VL53L0X_STRING_DEVICE_INFO_NAME_TS1      "VL53L0X TS1"
+	#define  VL53L0X_STRING_DEVICE_INFO_NAME_TS2      "VL53L0X TS2"
+	#define  VL53L0X_STRING_DEVICE_INFO_NAME_ES1      "VL53L0X ES1 or later"
+	#define  VL53L0X_STRING_DEVICE_INFO_TYPE          "VL53L0X"
+
+	/* PAL ERROR strings */
+	#define  VL53L0X_STRING_ERROR_NONE \
+			"No Error"
+	#define  VL53L0X_STRING_ERROR_CALIBRATION_WARNING \
+			"Calibration Warning Error"
+	#define  VL53L0X_STRING_ERROR_MIN_CLIPPED \
+			"Min clipped error"
+	#define  VL53L0X_STRING_ERROR_UNDEFINED \
+			"Undefined error"
+	#define  VL53L0X_STRING_ERROR_INVALID_PARAMS \
+			"Invalid parameters error"
+	#define  VL53L0X_STRING_ERROR_NOT_SUPPORTED \
+			"Not supported error"
+	#define  VL53L0X_STRING_ERROR_RANGE_ERROR \
+			"Range error"
+	#define  VL53L0X_STRING_ERROR_TIME_OUT \
+			"Time out error"
+	#define  VL53L0X_STRING_ERROR_MODE_NOT_SUPPORTED \
+			"Mode not supported error"
+	#define  VL53L0X_STRING_ERROR_BUFFER_TOO_SMALL \
+			"Buffer too small"
+	#define  VL53L0X_STRING_ERROR_GPIO_NOT_EXISTING \
+			"GPIO not existing"
+	#define  VL53L0X_STRING_ERROR_GPIO_FUNCTIONALITY_NOT_SUPPORTED \
+			"GPIO funct not supported"
+	#define  VL53L0X_STRING_ERROR_INTERRUPT_NOT_CLEARED \
+			"Interrupt not Cleared"
+	#define  VL53L0X_STRING_ERROR_CONTROL_INTERFACE \
+			"Control Interface Error"
+	#define  VL53L0X_STRING_ERROR_INVALID_COMMAND \
+			"Invalid Command Error"
+	#define  VL53L0X_STRING_ERROR_DIVISION_BY_ZERO \
+			"Division by zero Error"
+	#define  VL53L0X_STRING_ERROR_REF_SPAD_INIT \
+			"Reference Spad Init Error"
+	#define  VL53L0X_STRING_ERROR_NOT_IMPLEMENTED \
+			"Not implemented error"
+
+	#define  VL53L0X_STRING_UNKNOW_ERROR_CODE \
+			"Unknown Error Code"
+
+
+
+	/* Range Status */
+	#define  VL53L0X_STRING_RANGESTATUS_NONE                 "No Update"
+	#define  VL53L0X_STRING_RANGESTATUS_RANGEVALID           "Range Valid"
+	#define  VL53L0X_STRING_RANGESTATUS_SIGMA                "Sigma Fail"
+	#define  VL53L0X_STRING_RANGESTATUS_SIGNAL               "Signal Fail"
+	#define  VL53L0X_STRING_RANGESTATUS_MINRANGE             "Min Range Fail"
+	#define  VL53L0X_STRING_RANGESTATUS_PHASE                "Phase Fail"
+	#define  VL53L0X_STRING_RANGESTATUS_HW                   "Hardware Fail"
+
+
+	/* Range Status */
+	#define  VL53L0X_STRING_STATE_POWERDOWN               "POWERDOWN State"
+	#define  VL53L0X_STRING_STATE_WAIT_STATICINIT \
+			"Wait for staticinit State"
+	#define  VL53L0X_STRING_STATE_STANDBY                 "STANDBY State"
+	#define  VL53L0X_STRING_STATE_IDLE                    "IDLE State"
+	#define  VL53L0X_STRING_STATE_RUNNING                 "RUNNING State"
+	#define  VL53L0X_STRING_STATE_UNKNOWN                 "UNKNOWN State"
+	#define  VL53L0X_STRING_STATE_ERROR                   "ERROR State"
+
+
+	/* Device Specific */
+	#define  VL53L0X_STRING_DEVICEERROR_NONE                   "No Update"
+	#define  VL53L0X_STRING_DEVICEERROR_VCSELCONTINUITYTESTFAILURE \
+			"VCSEL Continuity Test Failure"
+	#define  VL53L0X_STRING_DEVICEERROR_VCSELWATCHDOGTESTFAILURE \
+			"VCSEL Watchdog Test Failure"
+	#define  VL53L0X_STRING_DEVICEERROR_NOVHVVALUEFOUND \
+			"No VHV Value found"
+	#define  VL53L0X_STRING_DEVICEERROR_MSRCNOTARGET \
+			"MSRC No Target Error"
+	#define  VL53L0X_STRING_DEVICEERROR_SNRCHECK \
+			"SNR Check Exit"
+	#define  VL53L0X_STRING_DEVICEERROR_RANGEPHASECHECK \
+			"Range Phase Check Error"
+	#define  VL53L0X_STRING_DEVICEERROR_SIGMATHRESHOLDCHECK \
+			"Sigma Threshold Check Error"
+	#define  VL53L0X_STRING_DEVICEERROR_TCC \
+			"TCC Error"
+	#define  VL53L0X_STRING_DEVICEERROR_PHASECONSISTENCY \
+			"Phase Consistency Error"
+	#define  VL53L0X_STRING_DEVICEERROR_MINCLIP \
+			"Min Clip Error"
+	#define  VL53L0X_STRING_DEVICEERROR_RANGECOMPLETE \
+			"Range Complete"
+	#define  VL53L0X_STRING_DEVICEERROR_ALGOUNDERFLOW \
+			"Range Algo Underflow Error"
+	#define  VL53L0X_STRING_DEVICEERROR_ALGOOVERFLOW \
+			"Range Algo Overlow Error"
+	#define  VL53L0X_STRING_DEVICEERROR_RANGEIGNORETHRESHOLD \
+			"Range Ignore Threshold Error"
+	#define  VL53L0X_STRING_DEVICEERROR_UNKNOWN \
+			"Unknown error code"
+
+	/* Check Enable */
+	#define  VL53L0X_STRING_CHECKENABLE_SIGMA_FINAL_RANGE \
+			"SIGMA FINAL RANGE"
+	#define  VL53L0X_STRING_CHECKENABLE_SIGNAL_RATE_FINAL_RANGE \
+			"SIGNAL RATE FINAL RANGE"
+	#define  VL53L0X_STRING_CHECKENABLE_SIGNAL_REF_CLIP \
+			"SIGNAL REF CLIP"
+	#define  VL53L0X_STRING_CHECKENABLE_RANGE_IGNORE_THRESHOLD \
+			"RANGE IGNORE THRESHOLD"
+	#define  VL53L0X_STRING_CHECKENABLE_SIGNAL_RATE_MSRC \
+			"SIGNAL RATE MSRC"
+	#define  VL53L0X_STRING_CHECKENABLE_SIGNAL_RATE_PRE_RANGE \
+			"SIGNAL RATE PRE RANGE"
+
+	/* Sequence Step */
+	#define  VL53L0X_STRING_SEQUENCESTEP_TCC                   "TCC"
+	#define  VL53L0X_STRING_SEQUENCESTEP_DSS                   "DSS"
+	#define  VL53L0X_STRING_SEQUENCESTEP_MSRC                  "MSRC"
+	#define  VL53L0X_STRING_SEQUENCESTEP_PRE_RANGE             "PRE RANGE"
+	#define  VL53L0X_STRING_SEQUENCESTEP_FINAL_RANGE           "FINAL RANGE"
+#endif /* USE_EMPTY_STRING */
+
+
+
+
+#define VL53L0X_DEVICEERROR_NONE                        ((VL53L0X_DeviceError) 0)
+	/*!< 0  NoError  */
+#define VL53L0X_DEVICEERROR_VCSELCONTINUITYTESTFAILURE  ((VL53L0X_DeviceError) 1)
+#define VL53L0X_DEVICEERROR_VCSELWATCHDOGTESTFAILURE    ((VL53L0X_DeviceError) 2)
+#define VL53L0X_DEVICEERROR_NOVHVVALUEFOUND             ((VL53L0X_DeviceError) 3)
+#define VL53L0X_DEVICEERROR_MSRCNOTARGET                ((VL53L0X_DeviceError) 4)
+#define VL53L0X_DEVICEERROR_SNRCHECK                    ((VL53L0X_DeviceError) 5)
+#define VL53L0X_DEVICEERROR_RANGEPHASECHECK             ((VL53L0X_DeviceError) 6)
+#define VL53L0X_DEVICEERROR_SIGMATHRESHOLDCHECK         ((VL53L0X_DeviceError) 7)
+#define VL53L0X_DEVICEERROR_TCC                         ((VL53L0X_DeviceError) 8)
+#define VL53L0X_DEVICEERROR_PHASECONSISTENCY            ((VL53L0X_DeviceError) 9)
+#define VL53L0X_DEVICEERROR_MINCLIP                     ((VL53L0X_DeviceError) 10)
+#define VL53L0X_DEVICEERROR_RANGECOMPLETE               ((VL53L0X_DeviceError) 11)
+#define VL53L0X_DEVICEERROR_ALGOUNDERFLOW               ((VL53L0X_DeviceError) 12)
+#define VL53L0X_DEVICEERROR_ALGOOVERFLOW                ((VL53L0X_DeviceError) 13)
+#define VL53L0X_DEVICEERROR_RANGEIGNORETHRESHOLD        ((VL53L0X_DeviceError) 14)
+
+/** @defgroup VL53L0X_GpioFunctionality_group Gpio Functionality
+ *  @brief Defines the different functionalities for the device GPIO(s)
+ *  @{
+ */
+
+#define VL53L0X_GPIOFUNCTIONALITY_OFF                     \
+	((VL53L0X_GpioFunctionality)  0) /*!< NO Interrupt  */
+#define VL53L0X_GPIOFUNCTIONALITY_THRESHOLD_CROSSED_LOW   \
+	((VL53L0X_GpioFunctionality)  1) /*!< Level Low (value < thresh_low)  */
+#define VL53L0X_GPIOFUNCTIONALITY_THRESHOLD_CROSSED_HIGH   \
+	((VL53L0X_GpioFunctionality)  2) /*!< Level High (value > thresh_high) */
+#define VL53L0X_GPIOFUNCTIONALITY_THRESHOLD_CROSSED_OUT    \
+	((VL53L0X_GpioFunctionality)  3)
+	/*!< Out Of Window (value < thresh_low OR value > thresh_high)  */
+#define VL53L0X_GPIOFUNCTIONALITY_NEW_MEASURE_READY        \
+	((VL53L0X_GpioFunctionality)  4) /*!< New Sample Ready  */
+
+/* Device register map */
+
+/** @defgroup VL53L0X_DefineRegisters_group Define Registers
+ *  @brief List of all the defined registers
+ *  @{
+ */
+#define VL53L0X_REG_SYSRANGE_START                        0x000
+	/** mask existing bit in #VL53L0X_REG_SYSRANGE_START*/
+	#define VL53L0X_REG_SYSRANGE_MODE_MASK          0x0F
+	/** bit 0 in #VL53L0X_REG_SYSRANGE_START write 1 toggle state in
+	 * continuous mode and arm next shot in single shot mode */
+	#define VL53L0X_REG_SYSRANGE_MODE_START_STOP    0x01
+	/** bit 1 write 0 in #VL53L0X_REG_SYSRANGE_START set single shot mode */
+	#define VL53L0X_REG_SYSRANGE_MODE_SINGLESHOT    0x00
+	/** bit 1 write 1 in #VL53L0X_REG_SYSRANGE_START set back-to-back
+	 *  operation mode */
+	#define VL53L0X_REG_SYSRANGE_MODE_BACKTOBACK    0x02
+	/** bit 2 write 1 in #VL53L0X_REG_SYSRANGE_START set timed operation
+	 *  mode */
+	#define VL53L0X_REG_SYSRANGE_MODE_TIMED         0x04
+	/** bit 3 write 1 in #VL53L0X_REG_SYSRANGE_START set histogram operation
+	 *  mode */
+	#define VL53L0X_REG_SYSRANGE_MODE_HISTOGRAM     0x08
+
+
+#define VL53L0X_REG_SYSTEM_THRESH_HIGH               0x000C
+#define VL53L0X_REG_SYSTEM_THRESH_LOW                0x000E
+
+
+#define VL53L0X_REG_SYSTEM_SEQUENCE_CONFIG		0x0001
+#define VL53L0X_REG_SYSTEM_RANGE_CONFIG			0x0009
+#define VL53L0X_REG_SYSTEM_INTERMEASUREMENT_PERIOD	0x0004
+
+
+#define VL53L0X_REG_SYSTEM_INTERRUPT_CONFIG_GPIO               0x000A
+	#define VL53L0X_REG_SYSTEM_INTERRUPT_GPIO_DISABLED	0x00
+	#define VL53L0X_REG_SYSTEM_INTERRUPT_GPIO_LEVEL_LOW	0x01
+	#define VL53L0X_REG_SYSTEM_INTERRUPT_GPIO_LEVEL_HIGH	0x02
+	#define VL53L0X_REG_SYSTEM_INTERRUPT_GPIO_OUT_OF_WINDOW	0x03
+	#define VL53L0X_REG_SYSTEM_INTERRUPT_GPIO_NEW_SAMPLE_READY	0x04
+
+#define VL53L0X_REG_GPIO_HV_MUX_ACTIVE_HIGH          0x0084
+
+
+#define VL53L0X_REG_SYSTEM_INTERRUPT_CLEAR           0x000B
+
+/* Result registers */
+#define VL53L0X_REG_RESULT_INTERRUPT_STATUS          0x0013
+#define VL53L0X_REG_RESULT_RANGE_STATUS              0x0014
+
+#define VL53L0X_REG_RESULT_CORE_PAGE  1
+#define VL53L0X_REG_RESULT_CORE_AMBIENT_WINDOW_EVENTS_RTN   0x00BC
+#define VL53L0X_REG_RESULT_CORE_RANGING_TOTAL_EVENTS_RTN    0x00C0
+#define VL53L0X_REG_RESULT_CORE_AMBIENT_WINDOW_EVENTS_REF   0x00D0
+#define VL53L0X_REG_RESULT_CORE_RANGING_TOTAL_EVENTS_REF    0x00D4
+#define VL53L0X_REG_RESULT_PEAK_SIGNAL_RATE_REF             0x00B6
+
+/* Algo register */
+
+#define VL53L0X_REG_ALGO_PART_TO_PART_RANGE_OFFSET_MM       0x0028
+
+#define VL53L0X_REG_I2C_SLAVE_DEVICE_ADDRESS                0x008a
+
+/* Check Limit registers */
+#define VL53L0X_REG_MSRC_CONFIG_CONTROL                     0x0060
+
+#define VL53L0X_REG_PRE_RANGE_CONFIG_MIN_SNR                      0X0027
+#define VL53L0X_REG_PRE_RANGE_CONFIG_VALID_PHASE_LOW              0x0056
+#define VL53L0X_REG_PRE_RANGE_CONFIG_VALID_PHASE_HIGH             0x0057
+#define VL53L0X_REG_PRE_RANGE_MIN_COUNT_RATE_RTN_LIMIT            0x0064
+
+#define VL53L0X_REG_FINAL_RANGE_CONFIG_MIN_SNR                    0X0067
+#define VL53L0X_REG_FINAL_RANGE_CONFIG_VALID_PHASE_LOW            0x0047
+#define VL53L0X_REG_FINAL_RANGE_CONFIG_VALID_PHASE_HIGH           0x0048
+#define VL53L0X_REG_FINAL_RANGE_CONFIG_MIN_COUNT_RATE_RTN_LIMIT   0x0044
+
+
+#define VL53L0X_REG_PRE_RANGE_CONFIG_SIGMA_THRESH_HI              0X0061
+#define VL53L0X_REG_PRE_RANGE_CONFIG_SIGMA_THRESH_LO              0X0062
+
+/* PRE RANGE registers */
+#define VL53L0X_REG_PRE_RANGE_CONFIG_VCSEL_PERIOD                 0x0050
+#define VL53L0X_REG_PRE_RANGE_CONFIG_TIMEOUT_MACROP_HI            0x0051
+#define VL53L0X_REG_PRE_RANGE_CONFIG_TIMEOUT_MACROP_LO            0x0052
+
+#define VL53L0X_REG_SYSTEM_HISTOGRAM_BIN                          0x0081
+#define VL53L0X_REG_HISTOGRAM_CONFIG_INITIAL_PHASE_SELECT         0x0033
+#define VL53L0X_REG_HISTOGRAM_CONFIG_READOUT_CTRL                 0x0055
+
+#define VL53L0X_REG_FINAL_RANGE_CONFIG_VCSEL_PERIOD               0x0070
+#define VL53L0X_REG_FINAL_RANGE_CONFIG_TIMEOUT_MACROP_HI          0x0071
+#define VL53L0X_REG_FINAL_RANGE_CONFIG_TIMEOUT_MACROP_LO          0x0072
+#define VL53L0X_REG_CROSSTALK_COMPENSATION_PEAK_RATE_MCPS         0x0020
+
+#define VL53L0X_REG_MSRC_CONFIG_TIMEOUT_MACROP                    0x0046
+
+
+#define VL53L0X_REG_SOFT_RESET_GO2_SOFT_RESET_N	                 0x00bf
+#define VL53L0X_REG_IDENTIFICATION_MODEL_ID                       0x00c0
+#define VL53L0X_REG_IDENTIFICATION_REVISION_ID                    0x00c2
+
+#define VL53L0X_REG_OSC_CALIBRATE_VAL                             0x00f8
+
+
+#define VL53L0X_SIGMA_ESTIMATE_MAX_VALUE                          65535
+/* equivalent to a range sigma of 655.35mm */
+
+#define VL53L0X_REG_GLOBAL_CONFIG_VCSEL_WIDTH          0x032
+#define VL53L0X_REG_GLOBAL_CONFIG_SPAD_ENABLES_REF_0   0x0B0
+#define VL53L0X_REG_GLOBAL_CONFIG_SPAD_ENABLES_REF_1   0x0B1
+#define VL53L0X_REG_GLOBAL_CONFIG_SPAD_ENABLES_REF_2   0x0B2
+#define VL53L0X_REG_GLOBAL_CONFIG_SPAD_ENABLES_REF_3   0x0B3
+#define VL53L0X_REG_GLOBAL_CONFIG_SPAD_ENABLES_REF_4   0x0B4
+#define VL53L0X_REG_GLOBAL_CONFIG_SPAD_ENABLES_REF_5   0x0B5
+
+#define VL53L0X_REG_GLOBAL_CONFIG_REF_EN_START_SELECT   0xB6
+#define VL53L0X_REG_DYNAMIC_SPAD_NUM_REQUESTED_REF_SPAD 0x4E /* 0x14E */
+#define VL53L0X_REG_DYNAMIC_SPAD_REF_EN_START_OFFSET    0x4F /* 0x14F */
+#define VL53L0X_REG_POWER_MANAGEMENT_GO1_POWER_FORCE    0x80
+
+/*
+ * Speed of light in um per 1E-10 Seconds
+ */
+
+#define VL53L0X_SPEED_OF_LIGHT_IN_AIR 2997
+
+#define VL53L0X_REG_VHV_CONFIG_PAD_SCL_SDA__EXTSUP_HV     0x0089
+
+#define VL53L0X_REG_ALGO_PHASECAL_LIM                         0x0030 /* 0x130 */
+#define VL53L0X_REG_ALGO_PHASECAL_CONFIG_TIMEOUT              0x0030
+
+enum {
+	TRACE_LEVEL_NONE,
+	TRACE_LEVEL_ERRORS,
+	TRACE_LEVEL_WARNING,
+	TRACE_LEVEL_INFO,
+	TRACE_LEVEL_DEBUG,
+	TRACE_LEVEL_ALL,
+	TRACE_LEVEL_IGNORE
+};
+
+enum {
+	TRACE_FUNCTION_NONE = 0,
+	TRACE_FUNCTION_I2C  = 1,
+	TRACE_FUNCTION_ALL  = 0x7fffffff //all bits except sign
+};
+
+enum {
+	TRACE_MODULE_NONE              = 0x0,
+	TRACE_MODULE_API               = 0x1,
+	TRACE_MODULE_PLATFORM          = 0x2,
+	TRACE_MODULE_ALL               = 0x7fffffff //all bits except sign
+};
+
+#ifdef VL53L0X_LOG_ENABLE
+
+extern uint32_t _trace_level;
+
+int32_t VL53L0X_trace_config(char *filename, uint32_t modules, uint32_t level, uint32_t functions);
+
+void trace_print_module_function(uint32_t module, uint32_t level, uint32_t function, const char *format, ...);
+
+#define LOG_GET_TIME() (int)clock()
+
+#define _LOG_FUNCTION_START(module, fmt, ... ) \
+        trace_print_module_function(module, _trace_level, TRACE_FUNCTION_ALL, "%ld <START> %s "fmt"\n", LOG_GET_TIME(), __FUNCTION__, ##__VA_ARGS__);
+
+#define _LOG_FUNCTION_END(module, status, ... )\
+        trace_print_module_function(module, _trace_level, TRACE_FUNCTION_ALL, "%ld <END> %s %d\n", LOG_GET_TIME(), __FUNCTION__, (int)status, ##__VA_ARGS__)
+
+#define _LOG_FUNCTION_END_FMT(module, status, fmt, ... )\
+        trace_print_module_function(module, _trace_level, TRACE_FUNCTION_ALL, "%ld <END> %s %d "fmt"\n", LOG_GET_TIME(),  __FUNCTION__, (int)status,##__VA_ARGS__)
+
+
+#else /* VL53L0X_LOG_ENABLE no logging */
+    #define VL53L0X_ErrLog(...) (void)0
+    #define _LOG_FUNCTION_START(module, fmt, ... ) (void)0
+    #define _LOG_FUNCTION_END(module, status, ... ) (void)0
+    #define _LOG_FUNCTION_END_FMT(module, status, fmt, ... ) (void)0
+#endif /* else */
+
+#define VL53L0X_COPYSTRING(str, ...) strcpy(str, ##__VA_ARGS__)
+
+
+uint8_t DefaultTuningSettings[] = {
+
+	/* update 02/11/2015_v36 */
+	0x01, 0xFF, 0x01,
+	0x01, 0x00, 0x00,
+
+	0x01, 0xFF, 0x00,
+	0x01, 0x09, 0x00,
+	0x01, 0x10, 0x00,
+	0x01, 0x11, 0x00,
+
+	0x01, 0x24, 0x01,
+	0x01, 0x25, 0xff,
+	0x01, 0x75, 0x00,
+
+	0x01, 0xFF, 0x01,
+	0x01, 0x4e, 0x2c,
+	0x01, 0x48, 0x00,
+	0x01, 0x30, 0x20,
+
+	0x01, 0xFF, 0x00,
+	0x01, 0x30, 0x09, /* mja changed from 0x64. */
+	0x01, 0x54, 0x00,
+	0x01, 0x31, 0x04,
+	0x01, 0x32, 0x03,
+	0x01, 0x40, 0x83,
+	0x01, 0x46, 0x25,
+	0x01, 0x60, 0x00,
+	0x01, 0x27, 0x00,
+	0x01, 0x50, 0x06,
+	0x01, 0x51, 0x00,
+	0x01, 0x52, 0x96,
+	0x01, 0x56, 0x08,
+	0x01, 0x57, 0x30,
+	0x01, 0x61, 0x00,
+	0x01, 0x62, 0x00,
+	0x01, 0x64, 0x00,
+	0x01, 0x65, 0x00,
+	0x01, 0x66, 0xa0,
+
+	0x01, 0xFF, 0x01,
+	0x01, 0x22, 0x32,
+	0x01, 0x47, 0x14,
+	0x01, 0x49, 0xff,
+	0x01, 0x4a, 0x00,
+
+	0x01, 0xFF, 0x00,
+	0x01, 0x7a, 0x0a,
+	0x01, 0x7b, 0x00,
+	0x01, 0x78, 0x21,
+
+	0x01, 0xFF, 0x01,
+	0x01, 0x23, 0x34,
+	0x01, 0x42, 0x00,
+	0x01, 0x44, 0xff,
+	0x01, 0x45, 0x26,
+	0x01, 0x46, 0x05,
+	0x01, 0x40, 0x40,
+	0x01, 0x0E, 0x06,
+	0x01, 0x20, 0x1a,
+	0x01, 0x43, 0x40,
+
+	0x01, 0xFF, 0x00,
+	0x01, 0x34, 0x03,
+	0x01, 0x35, 0x44,
+
+	0x01, 0xFF, 0x01,
+	0x01, 0x31, 0x04,
+	0x01, 0x4b, 0x09,
+	0x01, 0x4c, 0x05,
+	0x01, 0x4d, 0x04,
+
+
+	0x01, 0xFF, 0x00,
+	0x01, 0x44, 0x00,
+	0x01, 0x45, 0x20,
+	0x01, 0x47, 0x08,
+	0x01, 0x48, 0x28,
+	0x01, 0x67, 0x00,
+	0x01, 0x70, 0x04,
+	0x01, 0x71, 0x01,
+	0x01, 0x72, 0xfe,
+	0x01, 0x76, 0x00,
+	0x01, 0x77, 0x00,
+
+	0x01, 0xFF, 0x01,
+	0x01, 0x0d, 0x01,
+
+	0x01, 0xFF, 0x00,
+	0x01, 0x80, 0x01,
+	0x01, 0x01, 0xF8,
+
+	0x01, 0xFF, 0x01,
+	0x01, 0x8e, 0x01,
+	0x01, 0x00, 0x01,
+	0x01, 0xFF, 0x00,
+	0x01, 0x80, 0x00,
+
+	0x00, 0x00, 0x00
+};
+
+uint8_t InterruptThresholdSettings[] = {
+
+	/* Start of Interrupt Threshold Settings */
+	0x1, 0xff, 0x00,
+	0x1, 0x80, 0x01,
+	0x1, 0xff, 0x01,
+	0x1, 0x00, 0x00,
+	0x1, 0xff, 0x01,
+	0x1, 0x4f, 0x02,
+	0x1, 0xFF, 0x0E,
+	0x1, 0x00, 0x03,
+	0x1, 0x01, 0x84,
+	0x1, 0x02, 0x0A,
+	0x1, 0x03, 0x03,
+	0x1, 0x04, 0x08,
+	0x1, 0x05, 0xC8,
+	0x1, 0x06, 0x03,
+	0x1, 0x07, 0x8D,
+	0x1, 0x08, 0x08,
+	0x1, 0x09, 0xC6,
+	0x1, 0x0A, 0x01,
+	0x1, 0x0B, 0x02,
+	0x1, 0x0C, 0x00,
+	0x1, 0x0D, 0xD5,
+	0x1, 0x0E, 0x18,
+	0x1, 0x0F, 0x12,
+	0x1, 0x10, 0x01,
+	0x1, 0x11, 0x82,
+	0x1, 0x12, 0x00,
+	0x1, 0x13, 0xD5,
+	0x1, 0x14, 0x18,
+	0x1, 0x15, 0x13,
+	0x1, 0x16, 0x03,
+	0x1, 0x17, 0x86,
+	0x1, 0x18, 0x0A,
+	0x1, 0x19, 0x09,
+	0x1, 0x1A, 0x08,
+	0x1, 0x1B, 0xC2,
+	0x1, 0x1C, 0x03,
+	0x1, 0x1D, 0x8F,
+	0x1, 0x1E, 0x0A,
+	0x1, 0x1F, 0x06,
+	0x1, 0x20, 0x01,
+	0x1, 0x21, 0x02,
+	0x1, 0x22, 0x00,
+	0x1, 0x23, 0xD5,
+	0x1, 0x24, 0x18,
+	0x1, 0x25, 0x22,
+	0x1, 0x26, 0x01,
+	0x1, 0x27, 0x82,
+	0x1, 0x28, 0x00,
+	0x1, 0x29, 0xD5,
+	0x1, 0x2A, 0x18,
+	0x1, 0x2B, 0x0B,
+	0x1, 0x2C, 0x28,
+	0x1, 0x2D, 0x78,
+	0x1, 0x2E, 0x28,
+	0x1, 0x2F, 0x91,
+	0x1, 0x30, 0x00,
+	0x1, 0x31, 0x0B,
+	0x1, 0x32, 0x00,
+	0x1, 0x33, 0x0B,
+	0x1, 0x34, 0x00,
+	0x1, 0x35, 0xA1,
+	0x1, 0x36, 0x00,
+	0x1, 0x37, 0xA0,
+	0x1, 0x38, 0x00,
+	0x1, 0x39, 0x04,
+	0x1, 0x3A, 0x28,
+	0x1, 0x3B, 0x30,
+	0x1, 0x3C, 0x0C,
+	0x1, 0x3D, 0x04,
+	0x1, 0x3E, 0x0F,
+	0x1, 0x3F, 0x79,
+	0x1, 0x40, 0x28,
+	0x1, 0x41, 0x1E,
+	0x1, 0x42, 0x2F,
+	0x1, 0x43, 0x87,
+	0x1, 0x44, 0x00,
+	0x1, 0x45, 0x0B,
+	0x1, 0x46, 0x00,
+	0x1, 0x47, 0x0B,
+	0x1, 0x48, 0x00,
+	0x1, 0x49, 0xA7,
+	0x1, 0x4A, 0x00,
+	0x1, 0x4B, 0xA6,
+	0x1, 0x4C, 0x00,
+	0x1, 0x4D, 0x04,
+	0x1, 0x4E, 0x01,
+	0x1, 0x4F, 0x00,
+	0x1, 0x50, 0x00,
+	0x1, 0x51, 0x80,
+	0x1, 0x52, 0x09,
+	0x1, 0x53, 0x08,
+	0x1, 0x54, 0x01,
+	0x1, 0x55, 0x00,
+	0x1, 0x56, 0x0F,
+	0x1, 0x57, 0x79,
+	0x1, 0x58, 0x09,
+	0x1, 0x59, 0x05,
+	0x1, 0x5A, 0x00,
+	0x1, 0x5B, 0x60,
+	0x1, 0x5C, 0x05,
+	0x1, 0x5D, 0xD1,
+	0x1, 0x5E, 0x0C,
+	0x1, 0x5F, 0x3C,
+	0x1, 0x60, 0x00,
+	0x1, 0x61, 0xD0,
+	0x1, 0x62, 0x0B,
+	0x1, 0x63, 0x03,
+	0x1, 0x64, 0x28,
+	0x1, 0x65, 0x10,
+	0x1, 0x66, 0x2A,
+	0x1, 0x67, 0x39,
+	0x1, 0x68, 0x0B,
+	0x1, 0x69, 0x02,
+	0x1, 0x6A, 0x28,
+	0x1, 0x6B, 0x10,
+	0x1, 0x6C, 0x2A,
+	0x1, 0x6D, 0x61,
+	0x1, 0x6E, 0x0C,
+	0x1, 0x6F, 0x00,
+	0x1, 0x70, 0x0F,
+	0x1, 0x71, 0x79,
+	0x1, 0x72, 0x00,
+	0x1, 0x73, 0x0B,
+	0x1, 0x74, 0x00,
+	0x1, 0x75, 0x0B,
+	0x1, 0x76, 0x00,
+	0x1, 0x77, 0xA1,
+	0x1, 0x78, 0x00,
+	0x1, 0x79, 0xA0,
+	0x1, 0x7A, 0x00,
+	0x1, 0x7B, 0x04,
+	0x1, 0xFF, 0x04,
+	0x1, 0x79, 0x1D,
+	0x1, 0x7B, 0x27,
+	0x1, 0x96, 0x0E,
+	0x1, 0x97, 0xFE,
+	0x1, 0x98, 0x03,
+	0x1, 0x99, 0xEF,
+	0x1, 0x9A, 0x02,
+	0x1, 0x9B, 0x44,
+	0x1, 0x73, 0x07,
+	0x1, 0x70, 0x01,
+	0x1, 0xff, 0x01,
+	0x1, 0x00, 0x01,
+	0x1, 0xff, 0x00,
+	0x00, 0x00, 0x00
+};
+
+
+#ifdef _MSC_VER
+#   ifdef VL53L0X_API_EXPORTS
+#       define VL53L0X_API  __declspec(dllexport)
+#   else
+#       define VL53L0X_API
+#   endif
+#else
+#   define VL53L0X_API
+#endif
+
+VL53L0X_Error VL53L0X_get_device_info(VL53L0X_DEV Dev,
+			VL53L0X_DeviceInfo_t *pVL53L0X_DeviceInfo);
+VL53L0X_Error VL53L0X_get_device_error_string(VL53L0X_DeviceError ErrorCode,
+		char *pDeviceErrorString);
+VL53L0X_Error VL53L0X_get_range_status_string(uint8_t RangeStatus,
+		char *pRangeStatusString);
+VL53L0X_Error VL53L0X_get_pal_error_string(VL53L0X_Error PalErrorCode,
+		char *pPalErrorString);
+VL53L0X_Error VL53L0X_get_pal_state_string(VL53L0X_State PalStateCode,
+		char *pPalStateString);
+VL53L0X_Error VL53L0X_get_sequence_steps_info(
+		VL53L0X_SequenceStepId SequenceStepId,
+		char *pSequenceStepsString);
+VL53L0X_Error VL53L0X_get_limit_check_info(VL53L0X_DEV Dev, uint16_t LimitCheckId,
+	char *pLimitCheckString);
+VL53L0X_API VL53L0X_Error VL53L0X_GetVersion(VL53L0X_Version_t *pVersion);
+
+VL53L0X_API VL53L0X_Error VL53L0X_GetPalSpecVersion(
+	VL53L0X_Version_t *pPalSpecVersion);
+VL53L0X_API VL53L0X_Error VL53L0X_GetProductRevision(VL53L0X_DEV Dev,
+	uint8_t *pProductRevisionMajor, uint8_t *pProductRevisionMinor);
+VL53L0X_API VL53L0X_Error VL53L0X_GetDeviceInfo(VL53L0X_DEV Dev,
+	VL53L0X_DeviceInfo_t *pVL53L0X_DeviceInfo);
+VL53L0X_API VL53L0X_Error VL53L0X_GetDeviceErrorStatus(VL53L0X_DEV Dev,
+	VL53L0X_DeviceError *pDeviceErrorStatus);
+VL53L0X_API VL53L0X_Error VL53L0X_GetRangeStatusString(uint8_t RangeStatus,
+	char *pRangeStatusString);
+VL53L0X_API VL53L0X_Error VL53L0X_GetDeviceErrorString(
+	VL53L0X_DeviceError ErrorCode, char *pDeviceErrorString);
+VL53L0X_API VL53L0X_Error VL53L0X_GetPalErrorString(VL53L0X_Error PalErrorCode,
+	char *pPalErrorString);
+VL53L0X_API VL53L0X_Error VL53L0X_GetPalStateString(VL53L0X_State PalStateCode,
+	char *pPalStateString);
+VL53L0X_API VL53L0X_Error VL53L0X_GetPalState(VL53L0X_DEV Dev,
+	VL53L0X_State *pPalState);
+VL53L0X_API VL53L0X_Error VL53L0X_SetPowerMode(VL53L0X_DEV Dev,
+	VL53L0X_PowerModes PowerMode);
+VL53L0X_API VL53L0X_Error VL53L0X_GetPowerMode(VL53L0X_DEV Dev,
+	VL53L0X_PowerModes *pPowerMode);
+VL53L0X_API VL53L0X_Error VL53L0X_SetOffsetCalibrationDataMicroMeter(
+	VL53L0X_DEV Dev, int32_t OffsetCalibrationDataMicroMeter);
+VL53L0X_API VL53L0X_Error VL53L0X_GetOffsetCalibrationDataMicroMeter(
+	VL53L0X_DEV Dev, int32_t *pOffsetCalibrationDataMicroMeter);
+VL53L0X_API VL53L0X_Error VL53L0X_SetLinearityCorrectiveGain(VL53L0X_DEV Dev,
+	int16_t LinearityCorrectiveGain);
+VL53L0X_API VL53L0X_Error VL53L0X_GetLinearityCorrectiveGain(VL53L0X_DEV Dev,
+	uint16_t *pLinearityCorrectiveGain);
+VL53L0X_API VL53L0X_Error VL53L0X_SetGroupParamHold(VL53L0X_DEV Dev,
+	uint8_t GroupParamHold);
+VL53L0X_API VL53L0X_Error VL53L0X_GetUpperLimitMilliMeter(VL53L0X_DEV Dev,
+	uint16_t *pUpperLimitMilliMeter);
+VL53L0X_Error VL53L0X_GetTotalSignalRate(VL53L0X_DEV Dev,
+	FixPoint1616_t *pTotalSignalRate);
+VL53L0X_API VL53L0X_Error VL53L0X_SetDeviceAddress(VL53L0X_DEV Dev,
+	uint8_t DeviceAddress);
+VL53L0X_API VL53L0X_Error VL53L0X_DataInit(VL53L0X_DEV Dev);
+VL53L0X_API VL53L0X_Error VL53L0X_SetTuningSettingBuffer(VL53L0X_DEV Dev,
+	uint8_t *pTuningSettingBuffer, uint8_t UseInternalTuningSettings);
+VL53L0X_API VL53L0X_Error VL53L0X_GetTuningSettingBuffer(VL53L0X_DEV Dev,
+	uint8_t **ppTuningSettingBuffer, uint8_t *pUseInternalTuningSettings);
+VL53L0X_API VL53L0X_Error VL53L0X_StaticInit(VL53L0X_DEV Dev);
+VL53L0X_API VL53L0X_Error VL53L0X_WaitDeviceBooted(VL53L0X_DEV Dev);
+VL53L0X_API VL53L0X_Error VL53L0X_ResetDevice(VL53L0X_DEV Dev);
+VL53L0X_API VL53L0X_Error VL53L0X_SetDeviceParameters(VL53L0X_DEV Dev,
+	const VL53L0X_DeviceParameters_t *pDeviceParameters);
+VL53L0X_API VL53L0X_Error VL53L0X_GetDeviceParameters(VL53L0X_DEV Dev,
+	VL53L0X_DeviceParameters_t *pDeviceParameters);
+VL53L0X_API VL53L0X_Error VL53L0X_SetDeviceMode(VL53L0X_DEV Dev,
+	VL53L0X_DeviceModes DeviceMode);
+VL53L0X_API VL53L0X_Error VL53L0X_GetDeviceMode(VL53L0X_DEV Dev,
+	VL53L0X_DeviceModes *pDeviceMode);
+VL53L0X_API VL53L0X_Error VL53L0X_SetRangeFractionEnable(VL53L0X_DEV Dev,
+	uint8_t Enable);
+VL53L0X_API VL53L0X_Error VL53L0X_GetFractionEnable(VL53L0X_DEV Dev,
+	uint8_t *pEnable);
+VL53L0X_API VL53L0X_Error VL53L0X_SetHistogramMode(VL53L0X_DEV Dev,
+	VL53L0X_HistogramModes HistogramMode);
+VL53L0X_API VL53L0X_Error VL53L0X_GetHistogramMode(VL53L0X_DEV Dev,
+	VL53L0X_HistogramModes *pHistogramMode);
+VL53L0X_API VL53L0X_Error VL53L0X_SetMeasurementTimingBudgetMicroSeconds(
+	VL53L0X_DEV Dev, uint32_t MeasurementTimingBudgetMicroSeconds);
+VL53L0X_API VL53L0X_Error VL53L0X_GetMeasurementTimingBudgetMicroSeconds(
+	VL53L0X_DEV Dev, uint32_t *pMeasurementTimingBudgetMicroSeconds);
+VL53L0X_API VL53L0X_Error VL53L0X_GetVcselPulsePeriod(VL53L0X_DEV Dev,
+	VL53L0X_VcselPeriod VcselPeriodType, uint8_t *pVCSELPulsePeriod);
+VL53L0X_API VL53L0X_Error VL53L0X_SetVcselPulsePeriod(VL53L0X_DEV Dev,
+	VL53L0X_VcselPeriod VcselPeriodType, uint8_t VCSELPulsePeriod);
+VL53L0X_API VL53L0X_Error VL53L0X_SetSequenceStepEnable(VL53L0X_DEV Dev,
+	VL53L0X_SequenceStepId SequenceStepId, uint8_t SequenceStepEnabled);
+VL53L0X_API VL53L0X_Error VL53L0X_GetSequenceStepEnable(VL53L0X_DEV Dev,
+	VL53L0X_SequenceStepId SequenceStepId, uint8_t *pSequenceStepEnabled);
+VL53L0X_API VL53L0X_Error VL53L0X_GetSequenceStepEnables(VL53L0X_DEV Dev,
+	VL53L0X_SchedulerSequenceSteps_t *pSchedulerSequenceSteps);
+VL53L0X_API VL53L0X_Error VL53L0X_SetSequenceStepTimeout(VL53L0X_DEV Dev,
+	VL53L0X_SequenceStepId SequenceStepId, FixPoint1616_t TimeOutMilliSecs);
+VL53L0X_API VL53L0X_Error VL53L0X_GetSequenceStepTimeout(VL53L0X_DEV Dev,
+	VL53L0X_SequenceStepId SequenceStepId,
+	FixPoint1616_t *pTimeOutMilliSecs);
+VL53L0X_API VL53L0X_Error VL53L0X_GetNumberOfSequenceSteps(VL53L0X_DEV Dev,
+	uint8_t *pNumberOfSequenceSteps);
+VL53L0X_API VL53L0X_Error VL53L0X_GetSequenceStepsInfo(
+	VL53L0X_SequenceStepId SequenceStepId, char *pSequenceStepsString);
+VL53L0X_API VL53L0X_Error VL53L0X_SetInterMeasurementPeriodMilliSeconds(
+	VL53L0X_DEV Dev, uint32_t InterMeasurementPeriodMilliSeconds);
+VL53L0X_API VL53L0X_Error VL53L0X_GetInterMeasurementPeriodMilliSeconds(
+	VL53L0X_DEV Dev, uint32_t *pInterMeasurementPeriodMilliSeconds);
+VL53L0X_API VL53L0X_Error VL53L0X_SetXTalkCompensationEnable(VL53L0X_DEV Dev,
+	uint8_t XTalkCompensationEnable);
+VL53L0X_API VL53L0X_Error VL53L0X_GetXTalkCompensationEnable(VL53L0X_DEV Dev,
+	uint8_t *pXTalkCompensationEnable);
+VL53L0X_API VL53L0X_Error VL53L0X_SetXTalkCompensationRateMegaCps(VL53L0X_DEV Dev,
+	FixPoint1616_t XTalkCompensationRateMegaCps);
+VL53L0X_API VL53L0X_Error VL53L0X_GetXTalkCompensationRateMegaCps(VL53L0X_DEV Dev,
+	FixPoint1616_t *pXTalkCompensationRateMegaCps);
+VL53L0X_API VL53L0X_Error VL53L0X_SetRefCalibration(VL53L0X_DEV Dev,
+	uint8_t VhvSettings, uint8_t PhaseCal);
+VL53L0X_API VL53L0X_Error VL53L0X_GetRefCalibration(VL53L0X_DEV Dev,
+	uint8_t *pVhvSettings, uint8_t *pPhaseCal);
+VL53L0X_API VL53L0X_Error VL53L0X_GetNumberOfLimitCheck(
+	uint16_t *pNumberOfLimitCheck);
+VL53L0X_API VL53L0X_Error VL53L0X_GetLimitCheckInfo(VL53L0X_DEV Dev,
+	uint16_t LimitCheckId, char *pLimitCheckString);
+VL53L0X_API VL53L0X_Error VL53L0X_GetLimitCheckStatus(VL53L0X_DEV Dev,
+	uint16_t LimitCheckId, uint8_t *pLimitCheckStatus);
+VL53L0X_API VL53L0X_Error VL53L0X_SetLimitCheckEnable(VL53L0X_DEV Dev,
+	uint16_t LimitCheckId, uint8_t LimitCheckEnable);
+VL53L0X_API VL53L0X_Error VL53L0X_GetLimitCheckEnable(VL53L0X_DEV Dev,
+	uint16_t LimitCheckId, uint8_t *pLimitCheckEnable);
+VL53L0X_API VL53L0X_Error VL53L0X_SetLimitCheckValue(VL53L0X_DEV Dev,
+	uint16_t LimitCheckId, FixPoint1616_t LimitCheckValue);
+VL53L0X_API VL53L0X_Error VL53L0X_GetLimitCheckValue(VL53L0X_DEV Dev,
+	uint16_t LimitCheckId, FixPoint1616_t *pLimitCheckValue);
+VL53L0X_API VL53L0X_Error VL53L0X_GetLimitCheckCurrent(VL53L0X_DEV Dev,
+	uint16_t LimitCheckId, FixPoint1616_t *pLimitCheckCurrent);
+VL53L0X_API VL53L0X_Error VL53L0X_SetWrapAroundCheckEnable(VL53L0X_DEV Dev,
+		uint8_t WrapAroundCheckEnable);
+VL53L0X_API VL53L0X_Error VL53L0X_GetWrapAroundCheckEnable(VL53L0X_DEV Dev,
+		uint8_t *pWrapAroundCheckEnable);
+VL53L0X_API VL53L0X_Error VL53L0X_SetDmaxCalParameters(VL53L0X_DEV Dev,
+		uint16_t RangeMilliMeter, FixPoint1616_t SignalRateRtnMegaCps);
+VL53L0X_API VL53L0X_Error VL53L0X_GetDmaxCalParameters(VL53L0X_DEV Dev,
+	uint16_t *pRangeMilliMeter, FixPoint1616_t *pSignalRateRtnMegaCps);
+VL53L0X_API VL53L0X_Error VL53L0X_PerformSingleMeasurement(VL53L0X_DEV Dev);
+VL53L0X_API VL53L0X_Error VL53L0X_PerformRefCalibration(VL53L0X_DEV Dev,
+	uint8_t *pVhvSettings, uint8_t *pPhaseCal);
+VL53L0X_API VL53L0X_Error VL53L0X_PerformXTalkMeasurement(VL53L0X_DEV Dev,
+	uint32_t TimeoutMs, FixPoint1616_t *pXtalkPerSpad,
+	uint8_t *pAmbientTooHigh);
+VL53L0X_API VL53L0X_Error VL53L0X_PerformXTalkCalibration(VL53L0X_DEV Dev,
+	FixPoint1616_t XTalkCalDistance,
+	FixPoint1616_t *pXTalkCompensationRateMegaCps);
+VL53L0X_API VL53L0X_Error VL53L0X_PerformOffsetCalibration(VL53L0X_DEV Dev,
+	FixPoint1616_t CalDistanceMilliMeter, int32_t *pOffsetMicroMeter);
+VL53L0X_API VL53L0X_Error VL53L0X_StartMeasurement(VL53L0X_DEV Dev);
+VL53L0X_API VL53L0X_Error VL53L0X_StopMeasurement(VL53L0X_DEV Dev);
+VL53L0X_API VL53L0X_Error VL53L0X_GetMeasurementDataReady(VL53L0X_DEV Dev,
+	uint8_t *pMeasurementDataReady);
+VL53L0X_API VL53L0X_Error VL53L0X_WaitDeviceReadyForNewMeasurement(VL53L0X_DEV Dev,
+	uint32_t MaxLoop);
+VL53L0X_API VL53L0X_Error VL53L0X_GetMeasurementRefSignal(VL53L0X_DEV Dev,
+	FixPoint1616_t *pMeasurementRefSignal);
+VL53L0X_API VL53L0X_Error VL53L0X_GetRangingMeasurementData(VL53L0X_DEV Dev,
+	VL53L0X_RangingMeasurementData_t *pRangingMeasurementData);
+VL53L0X_API VL53L0X_Error VL53L0X_GetHistogramMeasurementData(VL53L0X_DEV Dev,
+	VL53L0X_HistogramMeasurementData_t *pHistogramMeasurementData);
+VL53L0X_API VL53L0X_Error VL53L0X_PerformSingleRangingMeasurement(VL53L0X_DEV Dev,
+	VL53L0X_RangingMeasurementData_t *pRangingMeasurementData);
+VL53L0X_API VL53L0X_Error VL53L0X_PerformSingleHistogramMeasurement(VL53L0X_DEV Dev,
+	VL53L0X_HistogramMeasurementData_t *pHistogramMeasurementData);
+VL53L0X_API VL53L0X_Error VL53L0X_SetNumberOfROIZones(VL53L0X_DEV Dev,
+	uint8_t NumberOfROIZones);
+VL53L0X_API VL53L0X_Error VL53L0X_GetNumberOfROIZones(VL53L0X_DEV Dev,
+	uint8_t *pNumberOfROIZones);
+VL53L0X_API VL53L0X_Error VL53L0X_GetMaxNumberOfROIZones(VL53L0X_DEV Dev,
+	uint8_t *pMaxNumberOfROIZones);
+VL53L0X_API VL53L0X_Error VL53L0X_SetGpioConfig(VL53L0X_DEV Dev, uint8_t Pin,
+	VL53L0X_DeviceModes DeviceMode, VL53L0X_GpioFunctionality Functionality,
+	VL53L0X_InterruptPolarity Polarity);
+VL53L0X_API VL53L0X_Error VL53L0X_GetGpioConfig(VL53L0X_DEV Dev, uint8_t Pin,
+	VL53L0X_DeviceModes *pDeviceMode,
+	VL53L0X_GpioFunctionality *pFunctionality,
+	VL53L0X_InterruptPolarity *pPolarity);
+VL53L0X_API VL53L0X_Error VL53L0X_SetInterruptThresholds(VL53L0X_DEV Dev,
+	VL53L0X_DeviceModes DeviceMode, FixPoint1616_t ThresholdLow,
+	FixPoint1616_t ThresholdHigh);
+VL53L0X_API VL53L0X_Error VL53L0X_GetInterruptThresholds(VL53L0X_DEV Dev,
+	VL53L0X_DeviceModes DeviceMode, FixPoint1616_t *pThresholdLow,
+	FixPoint1616_t *pThresholdHigh);
+VL53L0X_API VL53L0X_Error VL53L0X_GetStopCompletedStatus(VL53L0X_DEV Dev,
+	uint32_t *pStopStatus);
+VL53L0X_API VL53L0X_Error VL53L0X_ClearInterruptMask(VL53L0X_DEV Dev,
+	uint32_t InterruptMask);
+VL53L0X_API VL53L0X_Error VL53L0X_GetInterruptMaskStatus(VL53L0X_DEV Dev,
+	uint32_t *pInterruptMaskStatus);
+VL53L0X_API VL53L0X_Error VL53L0X_EnableInterruptMask(VL53L0X_DEV Dev,
+	uint32_t InterruptMask);
+VL53L0X_API VL53L0X_Error VL53L0X_SetSpadAmbientDamperThreshold(VL53L0X_DEV Dev,
+	uint16_t SpadAmbientDamperThreshold);
+VL53L0X_API VL53L0X_Error VL53L0X_GetSpadAmbientDamperThreshold(VL53L0X_DEV Dev,
+	uint16_t *pSpadAmbientDamperThreshold);
+VL53L0X_API VL53L0X_Error VL53L0X_SetSpadAmbientDamperFactor(VL53L0X_DEV Dev,
+	uint16_t SpadAmbientDamperFactor);
+VL53L0X_API VL53L0X_Error VL53L0X_GetSpadAmbientDamperFactor(VL53L0X_DEV Dev,
+	uint16_t *pSpadAmbientDamperFactor);
+VL53L0X_API VL53L0X_Error VL53L0X_PerformRefSpadManagement(VL53L0X_DEV Dev,
+	uint32_t *refSpadCount, uint8_t *isApertureSpads);
+VL53L0X_API VL53L0X_Error VL53L0X_SetReferenceSpads(VL53L0X_DEV Dev,
+	uint32_t refSpadCount, uint8_t isApertureSpads);
+VL53L0X_API VL53L0X_Error VL53L0X_GetReferenceSpads(VL53L0X_DEV Dev,
+	uint32_t *refSpadCount, uint8_t *isApertureSpads);
+VL53L0X_Error VL53L0X_perform_phase_calibration(VL53L0X_DEV Dev,
+	uint8_t *pPhaseCal, const uint8_t get_data_enable,
+	const uint8_t restore_config);
+VL53L0X_Error VL53L0X_perform_ref_calibration(VL53L0X_DEV Dev,
+	uint8_t *pVhvSettings, uint8_t *pPhaseCal, uint8_t get_data_enable);
+VL53L0X_Error VL53L0X_set_offset_calibration_data_micro_meter(VL53L0X_DEV Dev,
+		int32_t OffsetCalibrationDataMicroMeter);
+VL53L0X_Error VL53L0X_perform_ref_spad_management(VL53L0X_DEV Dev,
+				uint32_t *refSpadCount,
+				uint8_t *isApertureSpads);
+VL53L0X_Error VL53L0X_set_reference_spads(VL53L0X_DEV Dev,
+				 uint32_t count, uint8_t isApertureSpads);
+VL53L0X_Error VL53L0X_get_offset_calibration_data_micro_meter(VL53L0X_DEV Dev,
+		int32_t *pOffsetCalibrationDataMicroMeter);
+VL53L0X_Error VL53L0X_set_ref_calibration(VL53L0X_DEV Dev,
+		uint8_t VhvSettings, uint8_t PhaseCal);
+VL53L0X_Error VL53L0X_get_ref_calibration(VL53L0X_DEV Dev,
+		uint8_t *pVhvSettings, uint8_t *pPhaseCal);
+VL53L0X_Error VL53L0X_perform_xtalk_calibration(VL53L0X_DEV Dev,
+			FixPoint1616_t XTalkCalDistance,
+			FixPoint1616_t *pXTalkCompensationRateMegaCps);
+VL53L0X_Error VL53L0X_get_reference_spads(VL53L0X_DEV Dev,
+			uint32_t *pSpadCount, uint8_t *pIsApertureSpads);
+VL53L0X_Error VL53L0X_perform_offset_calibration(VL53L0X_DEV Dev,
+			FixPoint1616_t CalDistanceMilliMeter,
+			int32_t *pOffsetMicroMeter);
+uint32_t refArrayQuadrants[4] = {REF_ARRAY_SPAD_10, REF_ARRAY_SPAD_5,
+		REF_ARRAY_SPAD_0, REF_ARRAY_SPAD_5 };
+VL53L0X_Error VL53L0X_LockSequenceAccess(VL53L0X_DEV Dev);
+VL53L0X_Error VL53L0X_UnlockSequenceAccess(VL53L0X_DEV Dev);
+VL53L0X_Error VL53L0X_WriteMulti(VL53L0X_DEV Dev, uint8_t index, uint8_t *pdata, uint32_t count);
+VL53L0X_Error VL53L0X_ReadMulti(VL53L0X_DEV Dev, uint8_t index, uint8_t *pdata, uint32_t count);
+VL53L0X_Error VL53L0X_WrByte(VL53L0X_DEV Dev, uint8_t index, uint8_t data);
+VL53L0X_Error VL53L0X_WrWord(VL53L0X_DEV Dev, uint8_t index, uint16_t data);
+VL53L0X_Error VL53L0X_WrDWord(VL53L0X_DEV Dev, uint8_t index, uint32_t data);
+VL53L0X_Error VL53L0X_RdByte(VL53L0X_DEV Dev, uint8_t index, uint8_t *data);
+VL53L0X_Error VL53L0X_RdWord(VL53L0X_DEV Dev, uint8_t index, uint16_t *data);
+VL53L0X_Error VL53L0X_RdDWord(VL53L0X_DEV Dev, uint8_t index, uint32_t *data);
+VL53L0X_Error VL53L0X_UpdateByte(VL53L0X_DEV Dev, uint8_t index, uint8_t AndData, uint8_t OrData);
+VL53L0X_Error VL53L0X_PollingDelay(VL53L0X_DEV Dev); /* usually best implemented as a real function */
+VL53L0X_Error VL53L0X_reverse_bytes(uint8_t *data, uint32_t size);
+VL53L0X_Error VL53L0X_measurement_poll_for_completion(VL53L0X_DEV Dev);
+uint8_t VL53L0X_encode_vcsel_period(uint8_t vcsel_period_pclks);
+uint8_t VL53L0X_decode_vcsel_period(uint8_t vcsel_period_reg);
+uint32_t VL53L0X_isqrt(uint32_t num);
+uint32_t VL53L0X_quadrature_sum(uint32_t a, uint32_t b);
+VL53L0X_Error VL53L0X_get_info_from_device(VL53L0X_DEV Dev, uint8_t option);
+VL53L0X_Error VL53L0X_set_vcsel_pulse_period(VL53L0X_DEV Dev,
+	VL53L0X_VcselPeriod VcselPeriodType, uint8_t VCSELPulsePeriodPCLK);
+VL53L0X_Error VL53L0X_get_vcsel_pulse_period(VL53L0X_DEV Dev,
+	VL53L0X_VcselPeriod VcselPeriodType, uint8_t *pVCSELPulsePeriodPCLK);
+uint32_t VL53L0X_decode_timeout(uint16_t encoded_timeout);
+VL53L0X_Error get_sequence_step_timeout(VL53L0X_DEV Dev,
+			VL53L0X_SequenceStepId SequenceStepId,
+			uint32_t *pTimeOutMicroSecs);
+VL53L0X_Error set_sequence_step_timeout(VL53L0X_DEV Dev,
+			VL53L0X_SequenceStepId SequenceStepId,
+			uint32_t TimeOutMicroSecs);
+VL53L0X_Error VL53L0X_set_measurement_timing_budget_micro_seconds(VL53L0X_DEV Dev,
+	uint32_t MeasurementTimingBudgetMicroSeconds);
+VL53L0X_Error VL53L0X_get_measurement_timing_budget_micro_seconds(VL53L0X_DEV Dev,
+		uint32_t *pMeasurementTimingBudgetMicroSeconds);
+VL53L0X_Error VL53L0X_load_tuning_settings(VL53L0X_DEV Dev,
+		uint8_t *pTuningSettingBuffer);
+VL53L0X_Error VL53L0X_calc_sigma_estimate(VL53L0X_DEV Dev,
+		VL53L0X_RangingMeasurementData_t *pRangingMeasurementData,
+		FixPoint1616_t *pSigmaEstimate, uint32_t *pDmax_mm);
+VL53L0X_Error VL53L0X_get_total_xtalk_rate(VL53L0X_DEV Dev,
+	VL53L0X_RangingMeasurementData_t *pRangingMeasurementData,
+	FixPoint1616_t *ptotal_xtalk_rate_mcps);
+VL53L0X_Error VL53L0X_get_total_signal_rate(VL53L0X_DEV Dev,
+	VL53L0X_RangingMeasurementData_t *pRangingMeasurementData,
+	FixPoint1616_t *ptotal_signal_rate_mcps);
+VL53L0X_Error VL53L0X_get_pal_range_status(VL53L0X_DEV Dev,
+		 uint8_t DeviceRangeStatus,
+		 FixPoint1616_t SignalRate,
+		 uint16_t EffectiveSpadRtnCount,
+		 VL53L0X_RangingMeasurementData_t *pRangingMeasurementData,
+		 uint8_t *pPalRangeStatus);
+uint32_t VL53L0X_calc_timeout_mclks(VL53L0X_DEV Dev,
+	uint32_t timeout_period_us, uint8_t vcsel_period_pclks);
+uint16_t VL53L0X_encode_timeout(uint32_t timeout_macro_clks);
+
+
+int VL53L0X_i2c_init(void);
+int VL53L0X_write_multi(uint8_t deviceAddress, uint8_t index, uint8_t *pdata, uint32_t count);
+int VL53L0X_read_multi(uint8_t deviceAddress, uint8_t index, uint8_t *pdata, uint32_t count);
+int VL53L0X_write_byte(uint8_t deviceAddress, uint8_t index, uint8_t data);
+int VL53L0X_write_word(uint8_t deviceAddress, uint8_t index, uint16_t data);
+int VL53L0X_write_dword(uint8_t deviceAddress, uint8_t index, uint32_t data);
+int VL53L0X_read_byte(uint8_t deviceAddress, uint8_t index, uint8_t *data);
+int VL53L0X_read_word(uint8_t deviceAddress, uint8_t index, uint16_t *data);
+int VL53L0X_read_dword(uint8_t deviceAddress, uint8_t index, uint32_t *data);
+
+/***************************************************i2c comms******************************************************/
+/**************************************************************************************************************/
+/**************************************************************************************************************/
+
+int VL53L0X_i2c_init(void) 
+{
+	printk(KERN_INFO "init i2c,i2c addr = %d\n",vl53l0x_client->addr);
+	return VL53L0X_ERROR_NONE;
+}
+
+int VL53L0X_write_multi(uint8_t deviceAddress, uint8_t index, uint8_t *pdata, uint32_t count) 
+{
+	deviceAddress = deviceAddress;
+	if(i2c_smbus_write_i2c_block_data(vl53l0x_client,index,count,pdata)){
+		printk(KERN_ALERT "Smbus send bytes failed\n");
+	}
+	return VL53L0X_ERROR_NONE;
+}
+
+int VL53L0X_write_byte(uint8_t deviceAddress, uint8_t index, uint8_t data) 
+{
+	// return VL53L0X_write_multi(deviceAddress, index, &data, 1);
+	if(i2c_smbus_write_byte_data(vl53l0x_client,index,data)){
+		printk(KERN_ALERT "Smbus send byte failed\n");
+	}
+	return VL53L0X_ERROR_NONE;
+}
+
+int VL53L0X_write_word(uint8_t deviceAddress, uint8_t index, uint16_t data) 
+{
+
+	uint8_t buff[2];
+	buff[1] = data & 0xFF;
+	buff[0] = data >> 8;
+	return VL53L0X_write_multi(deviceAddress, index, buff, 2);
+}
+
+int VL53L0X_write_dword(uint8_t deviceAddress, uint8_t index, uint32_t data) 
+{
+	uint8_t buff[4];
+
+	buff[3] = data & 0xFF;
+	buff[2] = data >> 8;
+	buff[1] = data >> 16;
+	buff[0] = data >> 24;
+
+	return VL53L0X_write_multi(deviceAddress, index, buff, 4);
+}
+
+int VL53L0X_read_multi(uint8_t deviceAddress, uint8_t index, uint8_t *pdata, uint32_t count) 
+{
+	if(i2c_smbus_read_i2c_block_data(vl53l0x_client,index,count,pdata) < 0 ){
+		printk(KERN_ALERT "Smbus read mutil failed\n");
+		return VL53L0X_ERROR_UNDEFINED;
+	}
+	return VL53L0X_ERROR_NONE;
+}
+
+int VL53L0X_read_byte(uint8_t deviceAddress, uint8_t index, uint8_t *data) 
+{
+	return VL53L0X_read_multi(0, index, data, 1);
+	// uint8_t read_data = 0;
+	// read_data = i2c_smbus_read_byte_data(vl53l0x_client,index);
+	// if(read_data < 0){
+	//   printk(KERN_ALERT "Smbus read byte failed\n");
+	// }
+	// *data = read_data ;
+	// return VL53L0X_ERROR_NONE;
+}
+
+int VL53L0X_read_word(uint8_t deviceAddress, uint8_t index, uint16_t *data) 
+{
+	uint8_t buff[2];
+	int r = VL53L0X_read_multi(deviceAddress, index, buff, 2);
+
+	uint16_t tmp;
+	tmp = buff[0];
+	tmp <<= 8;
+	tmp |= buff[1];
+	*data = tmp;
+	return r;
+}
+
+int VL53L0X_read_dword(uint8_t deviceAddress, uint8_t index, uint32_t *data) 
+{
+	uint8_t buff[4];
+	int r = VL53L0X_read_multi(deviceAddress, index, buff, 4);
+
+	uint32_t tmp;
+	tmp = buff[0];
+	tmp <<= 8;
+	tmp |= buff[1];
+	tmp <<= 8;
+	tmp |= buff[2];
+	tmp <<= 8;
+	tmp |= buff[3];
+	*data = tmp;
+
+	return r;
+}
+
+/**************************************************************************************************************/
+/**************************************************platform****************************************************/
+/**************************************************************************************************************/
+/**************************************************************************************************************/
+
+VL53L0X_Error VL53L0X_LockSequenceAccess(VL53L0X_DEV Dev)
+{
+	VL53L0X_Error Status = VL53L0X_ERROR_NONE;
+
+	return Status;
+}
+
+VL53L0X_Error VL53L0X_UnlockSequenceAccess(VL53L0X_DEV Dev)
+{
+	VL53L0X_Error Status = VL53L0X_ERROR_NONE;
+
+	return Status;
+}
+
+// the ranging_sensor_comms.dll will take care of the page selection
+VL53L0X_Error VL53L0X_WriteMulti(VL53L0X_DEV Dev, uint8_t index, uint8_t *pdata, uint32_t count){
+
+	VL53L0X_Error Status = VL53L0X_ERROR_NONE;
+	int32_t status_int = 0;
+	uint8_t deviceAddress;
+
+	if (count>=VL53L0X_MAX_I2C_XFER_SIZE){
+		Status = VL53L0X_ERROR_INVALID_PARAMS;
+	}
+
+	deviceAddress = Dev->I2cDevAddr;
+	status_int = VL53L0X_write_multi(deviceAddress, index, pdata, count);
+	if (status_int != 0)
+		Status = VL53L0X_ERROR_CONTROL_INTERFACE;
+	return Status;
+}
+
+// the ranging_sensor_comms.dll will take care of the page selection
+VL53L0X_Error VL53L0X_ReadMulti(VL53L0X_DEV Dev, uint8_t index, uint8_t *pdata, uint32_t count)
+{
+	VL53L0X_I2C_USER_VAR
+	VL53L0X_Error Status = VL53L0X_ERROR_NONE;
+	int32_t status_int;
+	uint8_t deviceAddress;
+
+	if (count>=VL53L0X_MAX_I2C_XFER_SIZE){
+		Status = VL53L0X_ERROR_INVALID_PARAMS;
+	}
+	deviceAddress = Dev->I2cDevAddr;
+	status_int = VL53L0X_read_multi(deviceAddress, index, pdata, count);
+
+	if (status_int != 0)
+		Status = VL53L0X_ERROR_CONTROL_INTERFACE;
+	return Status;
+}
+
+
+VL53L0X_Error VL53L0X_WrByte(VL53L0X_DEV Dev, uint8_t index, uint8_t data)
+{
+	VL53L0X_Error Status = VL53L0X_ERROR_NONE;
+	int32_t status_int;
+	uint8_t deviceAddress;
+
+	deviceAddress = Dev->I2cDevAddr;
+
+	status_int = VL53L0X_write_byte(deviceAddress, index, data);
+
+	if (status_int != 0)
+		Status = VL53L0X_ERROR_CONTROL_INTERFACE;
+
+	return Status;
+}
+
+VL53L0X_Error VL53L0X_WrWord(VL53L0X_DEV Dev, uint8_t index, uint16_t data)
+{
+	VL53L0X_Error Status = VL53L0X_ERROR_NONE;
+	int32_t status_int;
+	uint8_t deviceAddress;
+
+	deviceAddress = Dev->I2cDevAddr;
+
+	status_int = VL53L0X_write_word(deviceAddress, index, data);
+
+	if (status_int != 0)
+		Status = VL53L0X_ERROR_CONTROL_INTERFACE;
+
+	return Status;
+}
+
+VL53L0X_Error VL53L0X_WrDWord(VL53L0X_DEV Dev, uint8_t index, uint32_t data)
+{
+	VL53L0X_Error Status = VL53L0X_ERROR_NONE;
+	int32_t status_int;
+	uint8_t deviceAddress;
+
+	deviceAddress = Dev->I2cDevAddr;
+
+	status_int = VL53L0X_write_dword(deviceAddress, index, data);
+
+	if (status_int != 0)
+		Status = VL53L0X_ERROR_CONTROL_INTERFACE;
+
+	return Status;
+}
+
+VL53L0X_Error VL53L0X_UpdateByte(VL53L0X_DEV Dev, uint8_t index, uint8_t AndData, uint8_t OrData)
+{
+	VL53L0X_Error Status = VL53L0X_ERROR_NONE;
+	int32_t status_int;
+	uint8_t deviceAddress;
+	uint8_t data;
+
+	deviceAddress = Dev->I2cDevAddr;
+	status_int = VL53L0X_read_byte(deviceAddress, index, &data);
+
+	if (status_int != 0)
+	Status = VL53L0X_ERROR_CONTROL_INTERFACE;
+
+	if (Status == VL53L0X_ERROR_NONE) {
+		data = (data & AndData) | OrData;
+		status_int = VL53L0X_write_byte(deviceAddress, index, data);
+
+		if (status_int != 0)
+			Status = VL53L0X_ERROR_CONTROL_INTERFACE;
+	}
+	return Status;
+}
+
+VL53L0X_Error VL53L0X_RdByte(VL53L0X_DEV Dev, uint8_t index, uint8_t *data)
+{
+	VL53L0X_Error Status = VL53L0X_ERROR_NONE;
+	int32_t status_int;
+	uint8_t deviceAddress;
+
+	deviceAddress = Dev->I2cDevAddr;
+
+	status_int = VL53L0X_read_byte(deviceAddress, index, data);
+
+	if (status_int != 0)
+		Status = VL53L0X_ERROR_CONTROL_INTERFACE;
+
+	return Status;
+}
+
+VL53L0X_Error VL53L0X_RdWord(VL53L0X_DEV Dev, uint8_t index, uint16_t *data)
+{
+	VL53L0X_Error Status = VL53L0X_ERROR_NONE;
+	int32_t status_int;
+	uint8_t deviceAddress;
+
+	deviceAddress = Dev->I2cDevAddr;
+
+	status_int = VL53L0X_read_word(deviceAddress, index, data);
+
+	if (status_int != 0)
+		Status = VL53L0X_ERROR_CONTROL_INTERFACE;
+
+	return Status;
+}
+
+VL53L0X_Error  VL53L0X_RdDWord(VL53L0X_DEV Dev, uint8_t index, uint32_t *data)
+{
+	VL53L0X_Error Status = VL53L0X_ERROR_NONE;
+	int32_t status_int;
+	uint8_t deviceAddress;
+
+	deviceAddress = Dev->I2cDevAddr;
+
+	status_int = VL53L0X_read_dword(deviceAddress, index, data);
+
+	if (status_int != 0)
+		Status = VL53L0X_ERROR_CONTROL_INTERFACE;
+
+	return Status;
+}
+
+#define VL53L0X_POLLINGDELAY_LOOPNB  250
+VL53L0X_Error VL53L0X_PollingDelay(VL53L0X_DEV Dev)
+{
+	VL53L0X_Error status = VL53L0X_ERROR_NONE;
+	volatile uint32_t i;
+	LOG_FUNCTION_START("");
+
+	for(i=0;i<VL53L0X_POLLINGDELAY_LOOPNB;i++){
+		asm("nop");
+	}
+
+	LOG_FUNCTION_END(status);
+	return status;
+}
+
+
+/**************************************************api_strings*************************************************/
+/**************************************************************************************************************/
+/**************************************************************************************************************/
+
+VL53L0X_Error VL53L0X_check_part_used(VL53L0X_DEV Dev,
+		uint8_t *Revision,
+		VL53L0X_DeviceInfo_t *pVL53L0X_DeviceInfo)
+{
+	VL53L0X_Error Status = VL53L0X_ERROR_NONE;
+	uint8_t ModuleIdInt;
+	char *ProductId_tmp;
+
+	LOG_FUNCTION_START("");
+
+	Status = VL53L0X_get_info_from_device(Dev, 2);
+
+	if (Status == VL53L0X_ERROR_NONE) {
+		ModuleIdInt = VL53L0X_GETDEVICESPECIFICPARAMETER(Dev, ModuleId);
+
+	if (ModuleIdInt == 0) {
+		*Revision = 0;
+		VL53L0X_COPYSTRING(pVL53L0X_DeviceInfo->ProductId, "");
+	} else {
+		*Revision = VL53L0X_GETDEVICESPECIFICPARAMETER(Dev, Revision);
+		ProductId_tmp = VL53L0X_GETDEVICESPECIFICPARAMETER(Dev,
+			ProductId);
+		VL53L0X_COPYSTRING(pVL53L0X_DeviceInfo->ProductId, ProductId_tmp);
+	}
+	}
+
+	LOG_FUNCTION_END(Status);
+	return Status;
+}
+
+
+VL53L0X_Error VL53L0X_get_device_info(VL53L0X_DEV Dev,
+				VL53L0X_DeviceInfo_t *pVL53L0X_DeviceInfo)
+{
+	VL53L0X_Error Status = VL53L0X_ERROR_NONE;
+	uint8_t revision_id;
+	uint8_t Revision;
+
+	Status = VL53L0X_check_part_used(Dev, &Revision, pVL53L0X_DeviceInfo);
+	if (Status == VL53L0X_ERROR_NONE) {
+		if (Revision == 0) {
+			VL53L0X_COPYSTRING(pVL53L0X_DeviceInfo->Name,
+					VL53L0X_STRING_DEVICE_INFO_NAME_TS0);
+		} else if ((Revision <= 34) && (Revision != 32)) {
+			VL53L0X_COPYSTRING(pVL53L0X_DeviceInfo->Name,
+					VL53L0X_STRING_DEVICE_INFO_NAME_TS1);
+		} else if (Revision < 39) {
+			VL53L0X_COPYSTRING(pVL53L0X_DeviceInfo->Name,
+					VL53L0X_STRING_DEVICE_INFO_NAME_TS2);
+		} else {
+			VL53L0X_COPYSTRING(pVL53L0X_DeviceInfo->Name,
+					VL53L0X_STRING_DEVICE_INFO_NAME_ES1);
+		}
+
+		VL53L0X_COPYSTRING(pVL53L0X_DeviceInfo->Type,
+				VL53L0X_STRING_DEVICE_INFO_TYPE);
+
+	}
+
+	if (Status == VL53L0X_ERROR_NONE) {
+		Status = VL53L0X_RdByte(Dev, VL53L0X_REG_IDENTIFICATION_MODEL_ID,
+				&pVL53L0X_DeviceInfo->ProductType);
+	}
+	if (Status == VL53L0X_ERROR_NONE) {
+		Status = VL53L0X_RdByte(Dev,
+			VL53L0X_REG_IDENTIFICATION_REVISION_ID,
+				&revision_id);
+		pVL53L0X_DeviceInfo->ProductRevisionMajor = 1;
+		pVL53L0X_DeviceInfo->ProductRevisionMinor =
+					(revision_id & 0xF0) >> 4;
+	}
+
+	return Status;
+}
+
+
+VL53L0X_Error VL53L0X_get_device_error_string(VL53L0X_DeviceError ErrorCode,
+		char *pDeviceErrorString)
+{
+	VL53L0X_Error Status = VL53L0X_ERROR_NONE;
+
+	LOG_FUNCTION_START("");
+
+	switch (ErrorCode) {
+	case VL53L0X_DEVICEERROR_NONE:
+		VL53L0X_COPYSTRING(pDeviceErrorString,
+			VL53L0X_STRING_DEVICEERROR_NONE);
+	break;
+	case VL53L0X_DEVICEERROR_VCSELCONTINUITYTESTFAILURE:
+		VL53L0X_COPYSTRING(pDeviceErrorString,
+			VL53L0X_STRING_DEVICEERROR_VCSELCONTINUITYTESTFAILURE);
+	break;
+	case VL53L0X_DEVICEERROR_VCSELWATCHDOGTESTFAILURE:
+		VL53L0X_COPYSTRING(pDeviceErrorString,
+			VL53L0X_STRING_DEVICEERROR_VCSELWATCHDOGTESTFAILURE);
+	break;
+	case VL53L0X_DEVICEERROR_NOVHVVALUEFOUND:
+		VL53L0X_COPYSTRING(pDeviceErrorString,
+			VL53L0X_STRING_DEVICEERROR_NOVHVVALUEFOUND);
+	break;
+	case VL53L0X_DEVICEERROR_MSRCNOTARGET:
+		VL53L0X_COPYSTRING(pDeviceErrorString,
+			VL53L0X_STRING_DEVICEERROR_MSRCNOTARGET);
+	break;
+	case VL53L0X_DEVICEERROR_SNRCHECK:
+		VL53L0X_COPYSTRING(pDeviceErrorString,
+			VL53L0X_STRING_DEVICEERROR_SNRCHECK);
+	break;
+	case VL53L0X_DEVICEERROR_RANGEPHASECHECK:
+		VL53L0X_COPYSTRING(pDeviceErrorString,
+			VL53L0X_STRING_DEVICEERROR_RANGEPHASECHECK);
+	break;
+	case VL53L0X_DEVICEERROR_SIGMATHRESHOLDCHECK:
+		VL53L0X_COPYSTRING(pDeviceErrorString,
+			VL53L0X_STRING_DEVICEERROR_SIGMATHRESHOLDCHECK);
+	break;
+	case VL53L0X_DEVICEERROR_TCC:
+		VL53L0X_COPYSTRING(pDeviceErrorString,
+			VL53L0X_STRING_DEVICEERROR_TCC);
+	break;
+	case VL53L0X_DEVICEERROR_PHASECONSISTENCY:
+		VL53L0X_COPYSTRING(pDeviceErrorString,
+			VL53L0X_STRING_DEVICEERROR_PHASECONSISTENCY);
+	break;
+	case VL53L0X_DEVICEERROR_MINCLIP:
+		VL53L0X_COPYSTRING(pDeviceErrorString,
+			VL53L0X_STRING_DEVICEERROR_MINCLIP);
+	break;
+	case VL53L0X_DEVICEERROR_RANGECOMPLETE:
+		VL53L0X_COPYSTRING(pDeviceErrorString,
+			VL53L0X_STRING_DEVICEERROR_RANGECOMPLETE);
+	break;
+	case VL53L0X_DEVICEERROR_ALGOUNDERFLOW:
+		VL53L0X_COPYSTRING(pDeviceErrorString,
+			VL53L0X_STRING_DEVICEERROR_ALGOUNDERFLOW);
+	break;
+	case VL53L0X_DEVICEERROR_ALGOOVERFLOW:
+		VL53L0X_COPYSTRING(pDeviceErrorString,
+			VL53L0X_STRING_DEVICEERROR_ALGOOVERFLOW);
+	break;
+	case VL53L0X_DEVICEERROR_RANGEIGNORETHRESHOLD:
+		VL53L0X_COPYSTRING(pDeviceErrorString,
+			VL53L0X_STRING_DEVICEERROR_RANGEIGNORETHRESHOLD);
+	break;
+
+	default:
+		VL53L0X_COPYSTRING(pDeviceErrorString,
+			VL53L0X_STRING_UNKNOW_ERROR_CODE);
+
+	}
+
+	LOG_FUNCTION_END(Status);
+	return Status;
+}
+
+VL53L0X_Error VL53L0X_get_range_status_string(uint8_t RangeStatus,
+		char *pRangeStatusString)
+{
+	VL53L0X_Error Status = VL53L0X_ERROR_NONE;
+
+	LOG_FUNCTION_START("");
+
+	switch (RangeStatus) {
+	case 0:
+		VL53L0X_COPYSTRING(pRangeStatusString,
+			VL53L0X_STRING_RANGESTATUS_RANGEVALID);
+	break;
+	case 1:
+		VL53L0X_COPYSTRING(pRangeStatusString,
+			VL53L0X_STRING_RANGESTATUS_SIGMA);
+	break;
+	case 2:
+		VL53L0X_COPYSTRING(pRangeStatusString,
+			VL53L0X_STRING_RANGESTATUS_SIGNAL);
+	break;
+	case 3:
+		VL53L0X_COPYSTRING(pRangeStatusString,
+			VL53L0X_STRING_RANGESTATUS_MINRANGE);
+	break;
+	case 4:
+		VL53L0X_COPYSTRING(pRangeStatusString,
+			VL53L0X_STRING_RANGESTATUS_PHASE);
+	break;
+	case 5:
+		VL53L0X_COPYSTRING(pRangeStatusString,
+			VL53L0X_STRING_RANGESTATUS_HW);
+	break;
+
+	default: /**/
+		VL53L0X_COPYSTRING(pRangeStatusString,
+				VL53L0X_STRING_RANGESTATUS_NONE);
+	}
+
+	LOG_FUNCTION_END(Status);
+	return Status;
+}
+
+VL53L0X_Error VL53L0X_get_pal_error_string(VL53L0X_Error PalErrorCode,
+		char *pPalErrorString)
+{
+	VL53L0X_Error Status = VL53L0X_ERROR_NONE;
+
+	LOG_FUNCTION_START("");
+
+	switch (PalErrorCode) {
+	case VL53L0X_ERROR_NONE:
+		VL53L0X_COPYSTRING(pPalErrorString,
+			VL53L0X_STRING_ERROR_NONE);
+	break;
+	case VL53L0X_ERROR_CALIBRATION_WARNING:
+		VL53L0X_COPYSTRING(pPalErrorString,
+			VL53L0X_STRING_ERROR_CALIBRATION_WARNING);
+	break;
+	case VL53L0X_ERROR_MIN_CLIPPED:
+		VL53L0X_COPYSTRING(pPalErrorString,
+			VL53L0X_STRING_ERROR_MIN_CLIPPED);
+	break;
+	case VL53L0X_ERROR_UNDEFINED:
+		VL53L0X_COPYSTRING(pPalErrorString,
+			VL53L0X_STRING_ERROR_UNDEFINED);
+	break;
+	case VL53L0X_ERROR_INVALID_PARAMS:
+		VL53L0X_COPYSTRING(pPalErrorString,
+			VL53L0X_STRING_ERROR_INVALID_PARAMS);
+	break;
+	case VL53L0X_ERROR_NOT_SUPPORTED:
+		VL53L0X_COPYSTRING(pPalErrorString,
+			VL53L0X_STRING_ERROR_NOT_SUPPORTED);
+	break;
+	case VL53L0X_ERROR_INTERRUPT_NOT_CLEARED:
+		VL53L0X_COPYSTRING(pPalErrorString,
+			VL53L0X_STRING_ERROR_INTERRUPT_NOT_CLEARED);
+	break;
+	case VL53L0X_ERROR_RANGE_ERROR:
+		VL53L0X_COPYSTRING(pPalErrorString,
+			VL53L0X_STRING_ERROR_RANGE_ERROR);
+	break;
+	case VL53L0X_ERROR_TIME_OUT:
+		VL53L0X_COPYSTRING(pPalErrorString,
+			VL53L0X_STRING_ERROR_TIME_OUT);
+	break;
+	case VL53L0X_ERROR_MODE_NOT_SUPPORTED:
+		VL53L0X_COPYSTRING(pPalErrorString,
+			VL53L0X_STRING_ERROR_MODE_NOT_SUPPORTED);
+	break;
+	case VL53L0X_ERROR_BUFFER_TOO_SMALL:
+		VL53L0X_COPYSTRING(pPalErrorString,
+			VL53L0X_STRING_ERROR_BUFFER_TOO_SMALL);
+	break;
+	case VL53L0X_ERROR_GPIO_NOT_EXISTING:
+		VL53L0X_COPYSTRING(pPalErrorString,
+			VL53L0X_STRING_ERROR_GPIO_NOT_EXISTING);
+	break;
+	case VL53L0X_ERROR_GPIO_FUNCTIONALITY_NOT_SUPPORTED:
+		VL53L0X_COPYSTRING(pPalErrorString,
+			VL53L0X_STRING_ERROR_GPIO_FUNCTIONALITY_NOT_SUPPORTED);
+	break;
+	case VL53L0X_ERROR_CONTROL_INTERFACE:
+		VL53L0X_COPYSTRING(pPalErrorString,
+			VL53L0X_STRING_ERROR_CONTROL_INTERFACE);
+	break;
+	case VL53L0X_ERROR_INVALID_COMMAND:
+		VL53L0X_COPYSTRING(pPalErrorString,
+			VL53L0X_STRING_ERROR_INVALID_COMMAND);
+	break;
+	case VL53L0X_ERROR_DIVISION_BY_ZERO:
+		VL53L0X_COPYSTRING(pPalErrorString,
+			VL53L0X_STRING_ERROR_DIVISION_BY_ZERO);
+	break;
+	case VL53L0X_ERROR_REF_SPAD_INIT:
+		VL53L0X_COPYSTRING(pPalErrorString,
+			VL53L0X_STRING_ERROR_REF_SPAD_INIT);
+	break;
+	case VL53L0X_ERROR_NOT_IMPLEMENTED:
+		VL53L0X_COPYSTRING(pPalErrorString,
+			VL53L0X_STRING_ERROR_NOT_IMPLEMENTED);
+	break;
+
+	default:
+		VL53L0X_COPYSTRING(pPalErrorString,
+				VL53L0X_STRING_UNKNOW_ERROR_CODE);
+	}
+
+	LOG_FUNCTION_END(Status);
+	return Status;
+}
+
+VL53L0X_Error VL53L0X_get_pal_state_string(VL53L0X_State PalStateCode,
+		char *pPalStateString)
+{
+	VL53L0X_Error Status = VL53L0X_ERROR_NONE;
+
+	LOG_FUNCTION_START("");
+
+	switch (PalStateCode) {
+	case VL53L0X_STATE_POWERDOWN:
+		VL53L0X_COPYSTRING(pPalStateString,
+			VL53L0X_STRING_STATE_POWERDOWN);
+	break;
+	case VL53L0X_STATE_WAIT_STATICINIT:
+		VL53L0X_COPYSTRING(pPalStateString,
+			VL53L0X_STRING_STATE_WAIT_STATICINIT);
+	break;
+	case VL53L0X_STATE_STANDBY:
+		VL53L0X_COPYSTRING(pPalStateString,
+			VL53L0X_STRING_STATE_STANDBY);
+	break;
+	case VL53L0X_STATE_IDLE:
+		VL53L0X_COPYSTRING(pPalStateString,
+			VL53L0X_STRING_STATE_IDLE);
+	break;
+	case VL53L0X_STATE_RUNNING:
+		VL53L0X_COPYSTRING(pPalStateString,
+			VL53L0X_STRING_STATE_RUNNING);
+	break;
+	case VL53L0X_STATE_UNKNOWN:
+		VL53L0X_COPYSTRING(pPalStateString,
+			VL53L0X_STRING_STATE_UNKNOWN);
+	break;
+	case VL53L0X_STATE_ERROR:
+		VL53L0X_COPYSTRING(pPalStateString,
+			VL53L0X_STRING_STATE_ERROR);
+	break;
+
+	default:
+		VL53L0X_COPYSTRING(pPalStateString,
+			VL53L0X_STRING_STATE_UNKNOWN);
+	}
+
+	LOG_FUNCTION_END(Status);
+	return Status;
+}
+
+VL53L0X_Error VL53L0X_get_sequence_steps_info(
+		VL53L0X_SequenceStepId SequenceStepId,
+		char *pSequenceStepsString)
+{
+	VL53L0X_Error Status = VL53L0X_ERROR_NONE;
+	LOG_FUNCTION_START("");
+
+	switch (SequenceStepId) {
+	case VL53L0X_SEQUENCESTEP_TCC:
+		VL53L0X_COPYSTRING(pSequenceStepsString,
+			VL53L0X_STRING_SEQUENCESTEP_TCC);
+	break;
+	case VL53L0X_SEQUENCESTEP_DSS:
+		VL53L0X_COPYSTRING(pSequenceStepsString,
+			VL53L0X_STRING_SEQUENCESTEP_DSS);
+	break;
+	case VL53L0X_SEQUENCESTEP_MSRC:
+		VL53L0X_COPYSTRING(pSequenceStepsString,
+			VL53L0X_STRING_SEQUENCESTEP_MSRC);
+	break;
+	case VL53L0X_SEQUENCESTEP_PRE_RANGE:
+		VL53L0X_COPYSTRING(pSequenceStepsString,
+			VL53L0X_STRING_SEQUENCESTEP_PRE_RANGE);
+	break;
+	case VL53L0X_SEQUENCESTEP_FINAL_RANGE:
+		VL53L0X_COPYSTRING(pSequenceStepsString,
+			VL53L0X_STRING_SEQUENCESTEP_FINAL_RANGE);
+	break;
+
+	default:
+		Status = VL53L0X_ERROR_INVALID_PARAMS;
+	}
+
+	LOG_FUNCTION_END(Status);
+
+	return Status;
+}
+
+
+VL53L0X_Error VL53L0X_get_limit_check_info(VL53L0X_DEV Dev, uint16_t LimitCheckId,
+	char *pLimitCheckString)
+{
+	VL53L0X_Error Status = VL53L0X_ERROR_NONE;
+
+	LOG_FUNCTION_START("");
+
+	switch (LimitCheckId) {
+	case VL53L0X_CHECKENABLE_SIGMA_FINAL_RANGE:
+		VL53L0X_COPYSTRING(pLimitCheckString,
+			VL53L0X_STRING_CHECKENABLE_SIGMA_FINAL_RANGE);
+	break;
+	case VL53L0X_CHECKENABLE_SIGNAL_RATE_FINAL_RANGE:
+		VL53L0X_COPYSTRING(pLimitCheckString,
+			VL53L0X_STRING_CHECKENABLE_SIGNAL_RATE_FINAL_RANGE);
+	break;
+	case VL53L0X_CHECKENABLE_SIGNAL_REF_CLIP:
+		VL53L0X_COPYSTRING(pLimitCheckString,
+			VL53L0X_STRING_CHECKENABLE_SIGNAL_REF_CLIP);
+	break;
+	case VL53L0X_CHECKENABLE_RANGE_IGNORE_THRESHOLD:
+		VL53L0X_COPYSTRING(pLimitCheckString,
+			VL53L0X_STRING_CHECKENABLE_RANGE_IGNORE_THRESHOLD);
+	break;
+
+	case VL53L0X_CHECKENABLE_SIGNAL_RATE_MSRC:
+		VL53L0X_COPYSTRING(pLimitCheckString,
+			VL53L0X_STRING_CHECKENABLE_SIGNAL_RATE_MSRC);
+	break;
+
+	case VL53L0X_CHECKENABLE_SIGNAL_RATE_PRE_RANGE:
+		VL53L0X_COPYSTRING(pLimitCheckString,
+			VL53L0X_STRING_CHECKENABLE_SIGNAL_RATE_PRE_RANGE);
+	break;
+
+	default:
+		VL53L0X_COPYSTRING(pLimitCheckString,
+			VL53L0X_STRING_UNKNOW_ERROR_CODE);
+
+	}
+
+	LOG_FUNCTION_END(Status);
+	return Status;
+}
+
+
+
+/******************************************************api_core***************************************************/
+/******************************************************api_core***************************************************/
+/******************************************************api_core***************************************************/
+
+VL53L0X_Error VL53L0X_reverse_bytes(uint8_t *data, uint32_t size)
+{
+	VL53L0X_Error Status = VL53L0X_ERROR_NONE;
+	uint8_t tempData;
+	uint32_t mirrorIndex;
+	uint32_t middle = size/2;
+	uint32_t index;
+
+	for (index = 0; index < middle; index++) {
+		mirrorIndex		 = size - index - 1;
+		tempData		 = data[index];
+		data[index]		 = data[mirrorIndex];
+		data[mirrorIndex] = tempData;
+	}
+	return Status;
+}
+
+VL53L0X_Error VL53L0X_measurement_poll_for_completion(VL53L0X_DEV Dev)
+{
+	VL53L0X_Error Status = VL53L0X_ERROR_NONE;
+	uint8_t NewDataReady = 0;
+	uint32_t LoopNb;
+
+	LOG_FUNCTION_START("");
+
+	LoopNb = 0;
+
+	do {
+		Status = VL53L0X_GetMeasurementDataReady(Dev, &NewDataReady);
+		if (Status != 0)
+			break; /* the error is set */
+
+		if (NewDataReady == 1)
+			break; /* done note that status == 0 */
+
+		LoopNb++;
+		if (LoopNb >= VL53L0X_DEFAULT_MAX_LOOP) {
+			Status = VL53L0X_ERROR_TIME_OUT;
+			break;
+		}
+
+		VL53L0X_PollingDelay(Dev);
+	} while (1);
+
+	LOG_FUNCTION_END(Status);
+
+	return Status;
+}
+
+
+uint8_t VL53L0X_decode_vcsel_period(uint8_t vcsel_period_reg)
+{
+	/*!
+	 * Converts the encoded VCSEL period register value into the real
+	 * period in PLL clocks
+	 */
+
+	uint8_t vcsel_period_pclks = 0;
+
+	vcsel_period_pclks = (vcsel_period_reg + 1) << 1;
+
+	return vcsel_period_pclks;
+}
+
+uint8_t VL53L0X_encode_vcsel_period(uint8_t vcsel_period_pclks)
+{
+	/*!
+	 * Converts the encoded VCSEL period register value into the real period
+	 * in PLL clocks
+	 */
+
+	uint8_t vcsel_period_reg = 0;
+
+	vcsel_period_reg = (vcsel_period_pclks >> 1) - 1;
+
+	return vcsel_period_reg;
+}
+
+
+uint32_t VL53L0X_isqrt(uint32_t num)
+{
+	/*
+	 * Implements an integer square root
+	 *
+	 * From: http://en.wikipedia.org/wiki/Methods_of_computing_square_roots
+	 */
+
+	uint32_t  res = 0;
+	uint32_t  bit = 1 << 30;
+	/* The second-to-top bit is set:
+	 *	1 << 14 for 16-bits, 1 << 30 for 32 bits */
+
+	 /* "bit" starts at the highest power of four <= the argument. */
+	while (bit > num)
+		bit >>= 2;
+
+
+	while (bit != 0) {
+		if (num >= res + bit) {
+			num -= res + bit;
+			res = (res >> 1) + bit;
+		} else
+			res >>= 1;
+
+		bit >>= 2;
+	}
+
+	return res;
+}
+
+
+uint32_t VL53L0X_quadrature_sum(uint32_t a, uint32_t b)
+{
+	/*
+	 * Implements a quadrature sum
+	 *
+	 * rea = sqrt(a^2 + b^2)
+	 *
+	 * Trap overflow case max input value is 65535 (16-bit value)
+	 * as internal calc are 32-bit wide
+	 *
+	 * If overflow then seta output to maximum
+	 */
+	uint32_t  res = 0;
+
+	if (a > 65535 || b > 65535)
+		res = 65535;
+	else
+		res = VL53L0X_isqrt(a * a + b * b);
+
+	return res;
+}
+
+
+VL53L0X_Error VL53L0X_device_read_strobe(VL53L0X_DEV Dev)
+{
+	VL53L0X_Error Status = VL53L0X_ERROR_NONE;
+	uint8_t strobe;
+	uint32_t LoopNb;
+	LOG_FUNCTION_START("");
+
+	Status |= VL53L0X_WrByte(Dev, 0x83, 0x00);
+
+	/* polling
+	 * use timeout to avoid deadlock*/
+	if (Status == VL53L0X_ERROR_NONE) {
+		LoopNb = 0;
+		do {
+			Status = VL53L0X_RdByte(Dev, 0x83, &strobe);
+			if ((strobe != 0x00) || Status != VL53L0X_ERROR_NONE)
+					break;
+
+			LoopNb = LoopNb + 1;
+		} while (LoopNb < VL53L0X_DEFAULT_MAX_LOOP);
+
+		if (LoopNb >= VL53L0X_DEFAULT_MAX_LOOP)
+			Status = VL53L0X_ERROR_TIME_OUT;
+
+	}
+
+	Status |= VL53L0X_WrByte(Dev, 0x83, 0x01);
+
+	LOG_FUNCTION_END(Status);
+	return Status;
+
+}
+
+VL53L0X_Error VL53L0X_get_info_from_device(VL53L0X_DEV Dev, uint8_t option)
+{
+
+	VL53L0X_Error Status = VL53L0X_ERROR_NONE;
+	uint8_t byte;
+	uint32_t TmpDWord;
+	uint8_t ModuleId;
+	uint8_t Revision;
+	uint8_t ReferenceSpadCount = 0;
+	uint8_t ReferenceSpadType = 0;
+	uint32_t PartUIDUpper = 0;
+	uint32_t PartUIDLower = 0;
+	uint32_t OffsetFixed1104_mm = 0;
+	int16_t OffsetMicroMeters = 0;
+	uint32_t DistMeasTgtFixed1104_mm = 400 << 4;
+	uint32_t DistMeasFixed1104_400_mm = 0;
+	uint32_t SignalRateMeasFixed1104_400_mm = 0;
+	char ProductId[19];
+	char *ProductId_tmp;
+	uint8_t ReadDataFromDeviceDone;
+	FixPoint1616_t SignalRateMeasFixed400mmFix = 0;
+	uint8_t NvmRefGoodSpadMap[VL53L0X_REF_SPAD_BUFFER_SIZE];
+	int i;
+
+
+	LOG_FUNCTION_START("");
+
+	ReadDataFromDeviceDone = VL53L0X_GETDEVICESPECIFICPARAMETER(Dev,
+			ReadDataFromDeviceDone);
+
+	/* This access is done only once after that a GetDeviceInfo or
+	 * datainit is done*/
+	if (ReadDataFromDeviceDone != 7) {
+
+		Status |= VL53L0X_WrByte(Dev, 0x80, 0x01);
+		Status |= VL53L0X_WrByte(Dev, 0xFF, 0x01);
+		Status |= VL53L0X_WrByte(Dev, 0x00, 0x00);
+
+		Status |= VL53L0X_WrByte(Dev, 0xFF, 0x06);
+		Status |= VL53L0X_RdByte(Dev, 0x83, &byte);
+		Status |= VL53L0X_WrByte(Dev, 0x83, byte|4);
+		Status |= VL53L0X_WrByte(Dev, 0xFF, 0x07);
+		Status |= VL53L0X_WrByte(Dev, 0x81, 0x01);
+
+		Status |= VL53L0X_PollingDelay(Dev);
+
+		Status |= VL53L0X_WrByte(Dev, 0x80, 0x01);
+
+		if (((option & 1) == 1) &&
+			((ReadDataFromDeviceDone & 1) == 0)) {
+			Status |= VL53L0X_WrByte(Dev, 0x94, 0x6b);
+			Status |= VL53L0X_device_read_strobe(Dev);
+			Status |= VL53L0X_RdDWord(Dev, 0x90, &TmpDWord);
+
+			ReferenceSpadCount = (uint8_t)((TmpDWord >> 8) & 0x07f);
+			ReferenceSpadType  = (uint8_t)((TmpDWord >> 15) & 0x01);
+
+			Status |= VL53L0X_WrByte(Dev, 0x94, 0x24);
+			Status |= VL53L0X_device_read_strobe(Dev);
+			Status |= VL53L0X_RdDWord(Dev, 0x90, &TmpDWord);
+
+
+			NvmRefGoodSpadMap[0] = (uint8_t)((TmpDWord >> 24)
+				& 0xff);
+			NvmRefGoodSpadMap[1] = (uint8_t)((TmpDWord >> 16)
+				& 0xff);
+			NvmRefGoodSpadMap[2] = (uint8_t)((TmpDWord >> 8)
+				& 0xff);
+			NvmRefGoodSpadMap[3] = (uint8_t)(TmpDWord & 0xff);
+
+			Status |= VL53L0X_WrByte(Dev, 0x94, 0x25);
+			Status |= VL53L0X_device_read_strobe(Dev);
+			Status |= VL53L0X_RdDWord(Dev, 0x90, &TmpDWord);
+
+			NvmRefGoodSpadMap[4] = (uint8_t)((TmpDWord >> 24)
+				& 0xff);
+			NvmRefGoodSpadMap[5] = (uint8_t)((TmpDWord >> 16)
+				& 0xff);
+		}
+
+		if (((option & 2) == 2) &&
+			((ReadDataFromDeviceDone & 2) == 0)) {
+
+			Status |= VL53L0X_WrByte(Dev, 0x94, 0x02);
+			Status |= VL53L0X_device_read_strobe(Dev);
+			Status |= VL53L0X_RdByte(Dev, 0x90, &ModuleId);
+
+			Status |= VL53L0X_WrByte(Dev, 0x94, 0x7B);
+			Status |= VL53L0X_device_read_strobe(Dev);
+			Status |= VL53L0X_RdByte(Dev, 0x90, &Revision);
+
+			Status |= VL53L0X_WrByte(Dev, 0x94, 0x77);
+			Status |= VL53L0X_device_read_strobe(Dev);
+			Status |= VL53L0X_RdDWord(Dev, 0x90, &TmpDWord);
+
+			ProductId[0] = (char)((TmpDWord >> 25) & 0x07f);
+			ProductId[1] = (char)((TmpDWord >> 18) & 0x07f);
+			ProductId[2] = (char)((TmpDWord >> 11) & 0x07f);
+			ProductId[3] = (char)((TmpDWord >> 4) & 0x07f);
+
+			byte = (uint8_t)((TmpDWord & 0x00f) << 3);
+
+			Status |= VL53L0X_WrByte(Dev, 0x94, 0x78);
+			Status |= VL53L0X_device_read_strobe(Dev);
+			Status |= VL53L0X_RdDWord(Dev, 0x90, &TmpDWord);
+
+			ProductId[4] = (char)(byte +
+					((TmpDWord >> 29) & 0x07f));
+			ProductId[5] = (char)((TmpDWord >> 22) & 0x07f);
+			ProductId[6] = (char)((TmpDWord >> 15) & 0x07f);
+			ProductId[7] = (char)((TmpDWord >> 8) & 0x07f);
+			ProductId[8] = (char)((TmpDWord >> 1) & 0x07f);
+
+			byte = (uint8_t)((TmpDWord & 0x001) << 6);
+
+			Status |= VL53L0X_WrByte(Dev, 0x94, 0x79);
+
+			Status |= VL53L0X_device_read_strobe(Dev);
+
+			Status |= VL53L0X_RdDWord(Dev, 0x90, &TmpDWord);
+
+			ProductId[9] = (char)(byte +
+					((TmpDWord >> 26) & 0x07f));
+			ProductId[10] = (char)((TmpDWord >> 19) & 0x07f);
+			ProductId[11] = (char)((TmpDWord >> 12) & 0x07f);
+			ProductId[12] = (char)((TmpDWord >> 5) & 0x07f);
+
+			byte = (uint8_t)((TmpDWord & 0x01f) << 2);
+
+			Status |= VL53L0X_WrByte(Dev, 0x94, 0x7A);
+
+			Status |= VL53L0X_device_read_strobe(Dev);
+
+			Status |= VL53L0X_RdDWord(Dev, 0x90, &TmpDWord);
+
+			ProductId[13] = (char)(byte +
+					((TmpDWord >> 30) & 0x07f));
+			ProductId[14] = (char)((TmpDWord >> 23) & 0x07f);
+			ProductId[15] = (char)((TmpDWord >> 16) & 0x07f);
+			ProductId[16] = (char)((TmpDWord >> 9) & 0x07f);
+			ProductId[17] = (char)((TmpDWord >> 2) & 0x07f);
+			ProductId[18] = '\0';
+
+		}
+
+		if (((option & 4) == 4) &&
+			((ReadDataFromDeviceDone & 4) == 0)) {
+
+			Status |= VL53L0X_WrByte(Dev, 0x94, 0x7B);
+			Status |= VL53L0X_device_read_strobe(Dev);
+			Status |= VL53L0X_RdDWord(Dev, 0x90, &PartUIDUpper);
+
+			Status |= VL53L0X_WrByte(Dev, 0x94, 0x7C);
+			Status |= VL53L0X_device_read_strobe(Dev);
+			Status |= VL53L0X_RdDWord(Dev, 0x90, &PartUIDLower);
+
+			Status |= VL53L0X_WrByte(Dev, 0x94, 0x73);
+			Status |= VL53L0X_device_read_strobe(Dev);
+			Status |= VL53L0X_RdDWord(Dev, 0x90, &TmpDWord);
+
+			SignalRateMeasFixed1104_400_mm = (TmpDWord &
+				0x0000000ff) << 8;
+
+			Status |= VL53L0X_WrByte(Dev, 0x94, 0x74);
+			Status |= VL53L0X_device_read_strobe(Dev);
+			Status |= VL53L0X_RdDWord(Dev, 0x90, &TmpDWord);
+
+			SignalRateMeasFixed1104_400_mm |= ((TmpDWord &
+				0xff000000) >> 24);
+
+			Status |= VL53L0X_WrByte(Dev, 0x94, 0x75);
+			Status |= VL53L0X_device_read_strobe(Dev);
+			Status |= VL53L0X_RdDWord(Dev, 0x90, &TmpDWord);
+
+			DistMeasFixed1104_400_mm = (TmpDWord & 0x0000000ff)
+							<< 8;
+
+			Status |= VL53L0X_WrByte(Dev, 0x94, 0x76);
+			Status |= VL53L0X_device_read_strobe(Dev);
+			Status |= VL53L0X_RdDWord(Dev, 0x90, &TmpDWord);
+
+			DistMeasFixed1104_400_mm |= ((TmpDWord & 0xff000000)
+							>> 24);
+		}
+
+		Status |= VL53L0X_WrByte(Dev, 0x81, 0x00);
+		Status |= VL53L0X_WrByte(Dev, 0xFF, 0x06);
+		Status |= VL53L0X_RdByte(Dev, 0x83, &byte);
+		Status |= VL53L0X_WrByte(Dev, 0x83, byte&0xfb);
+		Status |= VL53L0X_WrByte(Dev, 0xFF, 0x01);
+		Status |= VL53L0X_WrByte(Dev, 0x00, 0x01);
+
+		Status |= VL53L0X_WrByte(Dev, 0xFF, 0x00);
+		Status |= VL53L0X_WrByte(Dev, 0x80, 0x00);
+	}
+
+	if ((Status == VL53L0X_ERROR_NONE) &&
+		(ReadDataFromDeviceDone != 7)) {
+		/* Assign to variable if status is ok */
+		if (((option & 1) == 1) &&
+			((ReadDataFromDeviceDone & 1) == 0)) {
+			VL53L0X_SETDEVICESPECIFICPARAMETER(Dev,
+				ReferenceSpadCount, ReferenceSpadCount);
+
+			VL53L0X_SETDEVICESPECIFICPARAMETER(Dev,
+				ReferenceSpadType, ReferenceSpadType);
+
+			for (i = 0; i < VL53L0X_REF_SPAD_BUFFER_SIZE; i++) {
+				Dev->Data.SpadData.RefGoodSpadMap[i] =
+					NvmRefGoodSpadMap[i];
+			}
+		}
+
+		if (((option & 2) == 2) &&
+			((ReadDataFromDeviceDone & 2) == 0)) {
+			VL53L0X_SETDEVICESPECIFICPARAMETER(Dev,
+					ModuleId, ModuleId);
+
+			VL53L0X_SETDEVICESPECIFICPARAMETER(Dev,
+					Revision, Revision);
+
+			ProductId_tmp = VL53L0X_GETDEVICESPECIFICPARAMETER(Dev,
+					ProductId);
+			VL53L0X_COPYSTRING(ProductId_tmp, ProductId);
+
+		}
+
+		if (((option & 4) == 4) &&
+			((ReadDataFromDeviceDone & 4) == 0)) {
+			VL53L0X_SETDEVICESPECIFICPARAMETER(Dev,
+						PartUIDUpper, PartUIDUpper);
+
+			VL53L0X_SETDEVICESPECIFICPARAMETER(Dev,
+						PartUIDLower, PartUIDLower);
+
+			SignalRateMeasFixed400mmFix =
+				VL53L0X_FIXPOINT97TOFIXPOINT1616(
+					SignalRateMeasFixed1104_400_mm);
+
+			VL53L0X_SETDEVICESPECIFICPARAMETER(Dev,
+				SignalRateMeasFixed400mm,
+				SignalRateMeasFixed400mmFix);
+
+			OffsetMicroMeters = 0;
+			if (DistMeasFixed1104_400_mm != 0) {
+					OffsetFixed1104_mm =
+						DistMeasFixed1104_400_mm -
+						DistMeasTgtFixed1104_mm;
+					OffsetMicroMeters = (OffsetFixed1104_mm
+						* 1000) >> 4;
+					OffsetMicroMeters *= -1;
+			}
+
+			PALDevDataSet(Dev,
+				Part2PartOffsetAdjustmentNVMMicroMeter,
+				OffsetMicroMeters);
+		}
+		byte = (uint8_t)(ReadDataFromDeviceDone|option);
+		VL53L0X_SETDEVICESPECIFICPARAMETER(Dev, ReadDataFromDeviceDone,
+				byte);
+	}
+
+	LOG_FUNCTION_END(Status);
+	return Status;
+}
+
+
+uint32_t VL53L0X_calc_macro_period_ps(VL53L0X_DEV Dev, uint8_t vcsel_period_pclks)
+{
+	uint64_t PLL_period_ps;
+	uint32_t macro_period_vclks;
+	uint32_t macro_period_ps;
+
+	LOG_FUNCTION_START("");
+
+	/* The above calculation will produce rounding errors,
+	   therefore set fixed value
+	*/
+	PLL_period_ps = 1655;
+
+	macro_period_vclks = 2304;
+	macro_period_ps = (uint32_t)(macro_period_vclks
+			* vcsel_period_pclks * PLL_period_ps);
+
+	LOG_FUNCTION_END("");
+	return macro_period_ps;
+}
+
+uint16_t VL53L0X_encode_timeout(uint32_t timeout_macro_clks)
+{
+	/*!
+	 * Encode timeout in macro periods in (LSByte * 2^MSByte) + 1 format
+	 */
+
+	uint16_t encoded_timeout = 0;
+	uint32_t ls_byte = 0;
+	uint16_t ms_byte = 0;
+
+	if (timeout_macro_clks > 0) {
+		ls_byte = timeout_macro_clks - 1;
+
+		while ((ls_byte & 0xFFFFFF00) > 0) {
+			ls_byte = ls_byte >> 1;
+			ms_byte++;
+		}
+
+		encoded_timeout = (ms_byte << 8)
+				+ (uint16_t) (ls_byte & 0x000000FF);
+	}
+
+	return encoded_timeout;
+
+}
+
+uint32_t VL53L0X_decode_timeout(uint16_t encoded_timeout)
+{
+	/*!
+	 * Decode 16-bit timeout register value - format (LSByte * 2^MSByte) + 1
+	 */
+
+	uint32_t timeout_macro_clks = 0;
+
+	timeout_macro_clks = ((uint32_t) (encoded_timeout & 0x00FF)
+			<< (uint32_t) ((encoded_timeout & 0xFF00) >> 8)) + 1;
+
+	return timeout_macro_clks;
+}
+
+
+/* To convert ms into register value */
+uint32_t VL53L0X_calc_timeout_mclks(VL53L0X_DEV Dev,
+		uint32_t timeout_period_us,
+		uint8_t vcsel_period_pclks)
+{
+	uint32_t macro_period_ps;
+	uint32_t macro_period_ns;
+	uint32_t timeout_period_mclks = 0;
+
+	macro_period_ps = VL53L0X_calc_macro_period_ps(Dev, vcsel_period_pclks);
+	macro_period_ns = (macro_period_ps + 500) / 1000;
+
+	timeout_period_mclks =
+		(uint32_t) (((timeout_period_us * 1000)
+		+ (macro_period_ns / 2)) / macro_period_ns);
+
+	return timeout_period_mclks;
+}
+
+/* To convert register value into us */
+uint32_t VL53L0X_calc_timeout_us(VL53L0X_DEV Dev,
+		uint16_t timeout_period_mclks,
+		uint8_t vcsel_period_pclks)
+{
+	uint32_t macro_period_ps;
+	uint32_t macro_period_ns;
+	uint32_t actual_timeout_period_us = 0;
+
+	macro_period_ps = VL53L0X_calc_macro_period_ps(Dev, vcsel_period_pclks);
+	macro_period_ns = (macro_period_ps + 500) / 1000;
+
+	actual_timeout_period_us =
+		((timeout_period_mclks * macro_period_ns)
+		+ (macro_period_ns / 2)) / 1000;
+
+	return actual_timeout_period_us;
+}
+
+
+VL53L0X_Error get_sequence_step_timeout(VL53L0X_DEV Dev,
+				VL53L0X_SequenceStepId SequenceStepId,
+				uint32_t *pTimeOutMicroSecs)
+{
+	VL53L0X_Error Status = VL53L0X_ERROR_NONE;
+	uint8_t CurrentVCSELPulsePeriodPClk;
+	uint8_t EncodedTimeOutByte = 0;
+	uint32_t TimeoutMicroSeconds = 0;
+	uint16_t PreRangeEncodedTimeOut = 0;
+	uint16_t MsrcTimeOutMClks;
+	uint16_t PreRangeTimeOutMClks;
+	uint16_t FinalRangeTimeOutMClks = 0;
+	uint16_t FinalRangeEncodedTimeOut;
+	VL53L0X_SchedulerSequenceSteps_t SchedulerSequenceSteps;
+
+	if ((SequenceStepId == VL53L0X_SEQUENCESTEP_TCC)	 ||
+		(SequenceStepId == VL53L0X_SEQUENCESTEP_DSS)	 ||
+		(SequenceStepId == VL53L0X_SEQUENCESTEP_MSRC)) {
+
+		Status = VL53L0X_GetVcselPulsePeriod(Dev,
+					VL53L0X_VCSEL_PERIOD_PRE_RANGE,
+					&CurrentVCSELPulsePeriodPClk);
+		if (Status == VL53L0X_ERROR_NONE) {
+			Status = VL53L0X_RdByte(Dev,
+					VL53L0X_REG_MSRC_CONFIG_TIMEOUT_MACROP,
+					&EncodedTimeOutByte);
+		}
+		MsrcTimeOutMClks = VL53L0X_decode_timeout(EncodedTimeOutByte);
+
+		TimeoutMicroSeconds = VL53L0X_calc_timeout_us(Dev,
+						MsrcTimeOutMClks,
+						CurrentVCSELPulsePeriodPClk);
+	} else if (SequenceStepId == VL53L0X_SEQUENCESTEP_PRE_RANGE) {
+		/* Retrieve PRE-RANGE VCSEL Period */
+		Status = VL53L0X_GetVcselPulsePeriod(Dev,
+						VL53L0X_VCSEL_PERIOD_PRE_RANGE,
+						&CurrentVCSELPulsePeriodPClk);
+
+		/* Retrieve PRE-RANGE Timeout in Macro periods (MCLKS) */
+		if (Status == VL53L0X_ERROR_NONE) {
+
+			/* Retrieve PRE-RANGE VCSEL Period */
+			Status = VL53L0X_GetVcselPulsePeriod(Dev,
+					VL53L0X_VCSEL_PERIOD_PRE_RANGE,
+					&CurrentVCSELPulsePeriodPClk);
+
+			if (Status == VL53L0X_ERROR_NONE) {
+				Status = VL53L0X_RdWord(Dev,
+				VL53L0X_REG_PRE_RANGE_CONFIG_TIMEOUT_MACROP_HI,
+				&PreRangeEncodedTimeOut);
+			}
+
+			PreRangeTimeOutMClks = VL53L0X_decode_timeout(
+					PreRangeEncodedTimeOut);
+
+			TimeoutMicroSeconds = VL53L0X_calc_timeout_us(Dev,
+					PreRangeTimeOutMClks,
+					CurrentVCSELPulsePeriodPClk);
+		}
+	} else if (SequenceStepId == VL53L0X_SEQUENCESTEP_FINAL_RANGE) {
+
+		VL53L0X_GetSequenceStepEnables(Dev, &SchedulerSequenceSteps);
+		PreRangeTimeOutMClks = 0;
+
+		if (SchedulerSequenceSteps.PreRangeOn) {
+			/* Retrieve PRE-RANGE VCSEL Period */
+			Status = VL53L0X_GetVcselPulsePeriod(Dev,
+				VL53L0X_VCSEL_PERIOD_PRE_RANGE,
+				&CurrentVCSELPulsePeriodPClk);
+
+			/* Retrieve PRE-RANGE Timeout in Macro periods
+			 * (MCLKS) */
+			if (Status == VL53L0X_ERROR_NONE) {
+				Status = VL53L0X_RdWord(Dev,
+				VL53L0X_REG_PRE_RANGE_CONFIG_TIMEOUT_MACROP_HI,
+				&PreRangeEncodedTimeOut);
+				PreRangeTimeOutMClks = VL53L0X_decode_timeout(
+						PreRangeEncodedTimeOut);
+			}
+		}
+
+		if (Status == VL53L0X_ERROR_NONE) {
+			/* Retrieve FINAL-RANGE VCSEL Period */
+			Status = VL53L0X_GetVcselPulsePeriod(Dev,
+					VL53L0X_VCSEL_PERIOD_FINAL_RANGE,
+					&CurrentVCSELPulsePeriodPClk);
+		}
+
+		/* Retrieve FINAL-RANGE Timeout in Macro periods (MCLKS) */
+		if (Status == VL53L0X_ERROR_NONE) {
+			Status = VL53L0X_RdWord(Dev,
+				VL53L0X_REG_FINAL_RANGE_CONFIG_TIMEOUT_MACROP_HI,
+				&FinalRangeEncodedTimeOut);
+			FinalRangeTimeOutMClks = VL53L0X_decode_timeout(
+					FinalRangeEncodedTimeOut);
+		}
+
+		FinalRangeTimeOutMClks -= PreRangeTimeOutMClks;
+		TimeoutMicroSeconds = VL53L0X_calc_timeout_us(Dev,
+						FinalRangeTimeOutMClks,
+						CurrentVCSELPulsePeriodPClk);
+	}
+
+	*pTimeOutMicroSecs = TimeoutMicroSeconds;
+
+	return Status;
+}
+
+
+VL53L0X_Error set_sequence_step_timeout(VL53L0X_DEV Dev,
+					VL53L0X_SequenceStepId SequenceStepId,
+					uint32_t TimeOutMicroSecs)
+{
+	VL53L0X_Error Status = VL53L0X_ERROR_NONE;
+	uint8_t CurrentVCSELPulsePeriodPClk;
+	uint8_t MsrcEncodedTimeOut;
+	uint16_t PreRangeEncodedTimeOut;
+	uint16_t PreRangeTimeOutMClks;
+	uint16_t MsrcRangeTimeOutMClks;
+	uint16_t FinalRangeTimeOutMClks;
+	uint16_t FinalRangeEncodedTimeOut;
+	VL53L0X_SchedulerSequenceSteps_t SchedulerSequenceSteps;
+
+	if ((SequenceStepId == VL53L0X_SEQUENCESTEP_TCC)	 ||
+		(SequenceStepId == VL53L0X_SEQUENCESTEP_DSS)	 ||
+		(SequenceStepId == VL53L0X_SEQUENCESTEP_MSRC)) {
+
+		Status = VL53L0X_GetVcselPulsePeriod(Dev,
+					VL53L0X_VCSEL_PERIOD_PRE_RANGE,
+					&CurrentVCSELPulsePeriodPClk);
+
+		if (Status == VL53L0X_ERROR_NONE) {
+			MsrcRangeTimeOutMClks = VL53L0X_calc_timeout_mclks(Dev,
+					TimeOutMicroSecs,
+					(uint8_t)CurrentVCSELPulsePeriodPClk);
+
+			if (MsrcRangeTimeOutMClks > 256)
+				MsrcEncodedTimeOut = 255;
+			else
+				MsrcEncodedTimeOut =
+					(uint8_t)MsrcRangeTimeOutMClks - 1;
+
+			VL53L0X_SETDEVICESPECIFICPARAMETER(Dev,
+				LastEncodedTimeout,
+				MsrcEncodedTimeOut);
+		}
+
+		if (Status == VL53L0X_ERROR_NONE) {
+			Status = VL53L0X_WrByte(Dev,
+				VL53L0X_REG_MSRC_CONFIG_TIMEOUT_MACROP,
+				MsrcEncodedTimeOut);
+		}
+	} else {
+
+		if (SequenceStepId == VL53L0X_SEQUENCESTEP_PRE_RANGE) {
+
+			if (Status == VL53L0X_ERROR_NONE) {
+				Status = VL53L0X_GetVcselPulsePeriod(Dev,
+						VL53L0X_VCSEL_PERIOD_PRE_RANGE,
+						&CurrentVCSELPulsePeriodPClk);
+				PreRangeTimeOutMClks =
+					VL53L0X_calc_timeout_mclks(Dev,
+					TimeOutMicroSecs,
+					(uint8_t)CurrentVCSELPulsePeriodPClk);
+				PreRangeEncodedTimeOut = VL53L0X_encode_timeout(
+					PreRangeTimeOutMClks);
+
+				VL53L0X_SETDEVICESPECIFICPARAMETER(Dev,
+					LastEncodedTimeout,
+					PreRangeEncodedTimeOut);
+			}
+
+			if (Status == VL53L0X_ERROR_NONE) {
+				Status = VL53L0X_WrWord(Dev,
+				VL53L0X_REG_PRE_RANGE_CONFIG_TIMEOUT_MACROP_HI,
+				PreRangeEncodedTimeOut);
+			}
+
+			if (Status == VL53L0X_ERROR_NONE) {
+				VL53L0X_SETDEVICESPECIFICPARAMETER(
+					Dev,
+					PreRangeTimeoutMicroSecs,
+					TimeOutMicroSecs);
+			}
+		} else if (SequenceStepId == VL53L0X_SEQUENCESTEP_FINAL_RANGE) {
+
+			/* For the final range timeout, the pre-range timeout
+			 * must be added. To do this both final and pre-range
+			 * timeouts must be expressed in macro periods MClks
+			 * because they have different vcsel periods.
+			 */
+
+			VL53L0X_GetSequenceStepEnables(Dev,
+					&SchedulerSequenceSteps);
+			PreRangeTimeOutMClks = 0;
+			if (SchedulerSequenceSteps.PreRangeOn) {
+
+				/* Retrieve PRE-RANGE VCSEL Period */
+				Status = VL53L0X_GetVcselPulsePeriod(Dev,
+					VL53L0X_VCSEL_PERIOD_PRE_RANGE,
+					&CurrentVCSELPulsePeriodPClk);
+
+				/* Retrieve PRE-RANGE Timeout in Macro periods
+				 * (MCLKS) */
+				if (Status == VL53L0X_ERROR_NONE) {
+					Status = VL53L0X_RdWord(Dev, 0x51,
+						&PreRangeEncodedTimeOut);
+					PreRangeTimeOutMClks =
+						VL53L0X_decode_timeout(
+							PreRangeEncodedTimeOut);
+				}
+			}
+
+			/* Calculate FINAL RANGE Timeout in Macro Periods
+			 * (MCLKS) and add PRE-RANGE value
+			 */
+			if (Status == VL53L0X_ERROR_NONE) {
+
+				Status = VL53L0X_GetVcselPulsePeriod(Dev,
+						VL53L0X_VCSEL_PERIOD_FINAL_RANGE,
+						&CurrentVCSELPulsePeriodPClk);
+			}
+			if (Status == VL53L0X_ERROR_NONE) {
+
+				FinalRangeTimeOutMClks =
+					VL53L0X_calc_timeout_mclks(Dev,
+					TimeOutMicroSecs,
+					(uint8_t) CurrentVCSELPulsePeriodPClk);
+
+				FinalRangeTimeOutMClks += PreRangeTimeOutMClks;
+
+				FinalRangeEncodedTimeOut =
+				VL53L0X_encode_timeout(FinalRangeTimeOutMClks);
+
+				if (Status == VL53L0X_ERROR_NONE) {
+					Status = VL53L0X_WrWord(Dev, 0x71,
+					FinalRangeEncodedTimeOut);
+				}
+
+				if (Status == VL53L0X_ERROR_NONE) {
+					VL53L0X_SETDEVICESPECIFICPARAMETER(
+						Dev,
+						FinalRangeTimeoutMicroSecs,
+						TimeOutMicroSecs);
+				}
+			}
+		} else
+			Status = VL53L0X_ERROR_INVALID_PARAMS;
+
+	}
+	return Status;
+}
+
+VL53L0X_Error VL53L0X_set_vcsel_pulse_period(VL53L0X_DEV Dev,
+	VL53L0X_VcselPeriod VcselPeriodType, uint8_t VCSELPulsePeriodPCLK)
+{
+	VL53L0X_Error Status = VL53L0X_ERROR_NONE;
+	uint8_t vcsel_period_reg;
+	uint8_t MinPreVcselPeriodPCLK = 12;
+	uint8_t MaxPreVcselPeriodPCLK = 18;
+	uint8_t MinFinalVcselPeriodPCLK = 8;
+	uint8_t MaxFinalVcselPeriodPCLK = 14;
+	uint32_t MeasurementTimingBudgetMicroSeconds;
+	uint32_t FinalRangeTimeoutMicroSeconds;
+	uint32_t PreRangeTimeoutMicroSeconds;
+	uint32_t MsrcTimeoutMicroSeconds;
+	uint8_t PhaseCalInt = 0;
+
+	/* Check if valid clock period requested */
+
+	if ((VCSELPulsePeriodPCLK % 2) != 0) {
+		/* Value must be an even number */
+		Status = VL53L0X_ERROR_INVALID_PARAMS;
+	} else if (VcselPeriodType == VL53L0X_VCSEL_PERIOD_PRE_RANGE &&
+		(VCSELPulsePeriodPCLK < MinPreVcselPeriodPCLK ||
+		VCSELPulsePeriodPCLK > MaxPreVcselPeriodPCLK)) {
+		Status = VL53L0X_ERROR_INVALID_PARAMS;
+	} else if (VcselPeriodType == VL53L0X_VCSEL_PERIOD_FINAL_RANGE &&
+		(VCSELPulsePeriodPCLK < MinFinalVcselPeriodPCLK ||
+		 VCSELPulsePeriodPCLK > MaxFinalVcselPeriodPCLK)) {
+
+		Status = VL53L0X_ERROR_INVALID_PARAMS;
+	}
+
+	/* Apply specific settings for the requested clock period */
+
+	if (Status != VL53L0X_ERROR_NONE)
+		return Status;
+
+
+	if (VcselPeriodType == VL53L0X_VCSEL_PERIOD_PRE_RANGE) {
+
+		/* Set phase check limits */
+		if (VCSELPulsePeriodPCLK == 12) {
+
+			Status = VL53L0X_WrByte(Dev,
+				VL53L0X_REG_PRE_RANGE_CONFIG_VALID_PHASE_HIGH,
+				0x18);
+			Status = VL53L0X_WrByte(Dev,
+				VL53L0X_REG_PRE_RANGE_CONFIG_VALID_PHASE_LOW,
+				0x08);
+		} else if (VCSELPulsePeriodPCLK == 14) {
+
+			Status = VL53L0X_WrByte(Dev,
+				VL53L0X_REG_PRE_RANGE_CONFIG_VALID_PHASE_HIGH,
+				0x30);
+			Status = VL53L0X_WrByte(Dev,
+				VL53L0X_REG_PRE_RANGE_CONFIG_VALID_PHASE_LOW,
+				0x08);
+		} else if (VCSELPulsePeriodPCLK == 16) {
+
+			Status = VL53L0X_WrByte(Dev,
+				VL53L0X_REG_PRE_RANGE_CONFIG_VALID_PHASE_HIGH,
+				0x40);
+			Status = VL53L0X_WrByte(Dev,
+				VL53L0X_REG_PRE_RANGE_CONFIG_VALID_PHASE_LOW,
+				0x08);
+		} else if (VCSELPulsePeriodPCLK == 18) {
+
+			Status = VL53L0X_WrByte(Dev,
+				VL53L0X_REG_PRE_RANGE_CONFIG_VALID_PHASE_HIGH,
+				0x50);
+			Status = VL53L0X_WrByte(Dev,
+				VL53L0X_REG_PRE_RANGE_CONFIG_VALID_PHASE_LOW,
+				0x08);
+		}
+	} else if (VcselPeriodType == VL53L0X_VCSEL_PERIOD_FINAL_RANGE) {
+
+		if (VCSELPulsePeriodPCLK == 8) {
+
+			Status = VL53L0X_WrByte(Dev,
+				VL53L0X_REG_FINAL_RANGE_CONFIG_VALID_PHASE_HIGH,
+				0x10);
+			Status = VL53L0X_WrByte(Dev,
+				VL53L0X_REG_FINAL_RANGE_CONFIG_VALID_PHASE_LOW,
+				0x08);
+
+			Status |= VL53L0X_WrByte(Dev,
+				VL53L0X_REG_GLOBAL_CONFIG_VCSEL_WIDTH, 0x02);
+			Status |= VL53L0X_WrByte(Dev,
+				VL53L0X_REG_ALGO_PHASECAL_CONFIG_TIMEOUT, 0x0C);
+
+			Status |= VL53L0X_WrByte(Dev, 0xff, 0x01);
+			Status |= VL53L0X_WrByte(Dev,
+				VL53L0X_REG_ALGO_PHASECAL_LIM,
+				0x30);
+			Status |= VL53L0X_WrByte(Dev, 0xff, 0x00);
+		} else if (VCSELPulsePeriodPCLK == 10) {
+
+			Status = VL53L0X_WrByte(Dev,
+				VL53L0X_REG_FINAL_RANGE_CONFIG_VALID_PHASE_HIGH,
+				0x28);
+			Status = VL53L0X_WrByte(Dev,
+				VL53L0X_REG_FINAL_RANGE_CONFIG_VALID_PHASE_LOW,
+				0x08);
+
+			Status |= VL53L0X_WrByte(Dev,
+				VL53L0X_REG_GLOBAL_CONFIG_VCSEL_WIDTH, 0x03);
+			Status |= VL53L0X_WrByte(Dev,
+				VL53L0X_REG_ALGO_PHASECAL_CONFIG_TIMEOUT, 0x09);
+
+			Status |= VL53L0X_WrByte(Dev, 0xff, 0x01);
+			Status |= VL53L0X_WrByte(Dev,
+				VL53L0X_REG_ALGO_PHASECAL_LIM,
+				0x20);
+			Status |= VL53L0X_WrByte(Dev, 0xff, 0x00);
+		} else if (VCSELPulsePeriodPCLK == 12) {
+
+			Status = VL53L0X_WrByte(Dev,
+				VL53L0X_REG_FINAL_RANGE_CONFIG_VALID_PHASE_HIGH,
+				0x38);
+			Status = VL53L0X_WrByte(Dev,
+				VL53L0X_REG_FINAL_RANGE_CONFIG_VALID_PHASE_LOW,
+				0x08);
+
+			Status |= VL53L0X_WrByte(Dev,
+				VL53L0X_REG_GLOBAL_CONFIG_VCSEL_WIDTH, 0x03);
+			Status |= VL53L0X_WrByte(Dev,
+				VL53L0X_REG_ALGO_PHASECAL_CONFIG_TIMEOUT, 0x08);
+
+			Status |= VL53L0X_WrByte(Dev, 0xff, 0x01);
+			Status |= VL53L0X_WrByte(Dev,
+				VL53L0X_REG_ALGO_PHASECAL_LIM,
+				0x20);
+			Status |= VL53L0X_WrByte(Dev, 0xff, 0x00);
+		} else if (VCSELPulsePeriodPCLK == 14) {
+
+			Status = VL53L0X_WrByte(Dev,
+				VL53L0X_REG_FINAL_RANGE_CONFIG_VALID_PHASE_HIGH,
+				0x048);
+			Status = VL53L0X_WrByte(Dev,
+				VL53L0X_REG_FINAL_RANGE_CONFIG_VALID_PHASE_LOW,
+				0x08);
+
+			Status |= VL53L0X_WrByte(Dev,
+				VL53L0X_REG_GLOBAL_CONFIG_VCSEL_WIDTH, 0x03);
+			Status |= VL53L0X_WrByte(Dev,
+				VL53L0X_REG_ALGO_PHASECAL_CONFIG_TIMEOUT, 0x07);
+
+			Status |= VL53L0X_WrByte(Dev, 0xff, 0x01);
+			Status |= VL53L0X_WrByte(Dev,
+				VL53L0X_REG_ALGO_PHASECAL_LIM,
+				0x20);
+			Status |= VL53L0X_WrByte(Dev, 0xff, 0x00);
+		}
+	}
+
+
+	/* Re-calculate and apply timeouts, in macro periods */
+
+	if (Status == VL53L0X_ERROR_NONE) {
+		vcsel_period_reg = VL53L0X_encode_vcsel_period((uint8_t)
+			VCSELPulsePeriodPCLK);
+
+		/* When the VCSEL period for the pre or final range is changed,
+		* the corresponding timeout must be read from the device using
+		* the current VCSEL period, then the new VCSEL period can be
+		* applied. The timeout then must be written back to the device
+		* using the new VCSEL period.
+		*
+		* For the MSRC timeout, the same applies - this timeout being
+		* dependant on the pre-range vcsel period.
+		*/
+		switch (VcselPeriodType) {
+		case VL53L0X_VCSEL_PERIOD_PRE_RANGE:
+			Status = get_sequence_step_timeout(Dev,
+				VL53L0X_SEQUENCESTEP_PRE_RANGE,
+				&PreRangeTimeoutMicroSeconds);
+
+			if (Status == VL53L0X_ERROR_NONE)
+				Status = get_sequence_step_timeout(Dev,
+					VL53L0X_SEQUENCESTEP_MSRC,
+					&MsrcTimeoutMicroSeconds);
+
+			if (Status == VL53L0X_ERROR_NONE)
+				Status = VL53L0X_WrByte(Dev,
+				VL53L0X_REG_PRE_RANGE_CONFIG_VCSEL_PERIOD,
+					vcsel_period_reg);
+
+
+			if (Status == VL53L0X_ERROR_NONE)
+				Status = set_sequence_step_timeout(Dev,
+					VL53L0X_SEQUENCESTEP_PRE_RANGE,
+					PreRangeTimeoutMicroSeconds);
+
+
+			if (Status == VL53L0X_ERROR_NONE)
+				Status = set_sequence_step_timeout(Dev,
+					VL53L0X_SEQUENCESTEP_MSRC,
+					MsrcTimeoutMicroSeconds);
+
+			VL53L0X_SETDEVICESPECIFICPARAMETER(
+				Dev,
+				PreRangeVcselPulsePeriod,
+				VCSELPulsePeriodPCLK);
+			break;
+		case VL53L0X_VCSEL_PERIOD_FINAL_RANGE:
+			Status = get_sequence_step_timeout(Dev,
+				VL53L0X_SEQUENCESTEP_FINAL_RANGE,
+				&FinalRangeTimeoutMicroSeconds);
+
+			if (Status == VL53L0X_ERROR_NONE)
+				Status = VL53L0X_WrByte(Dev,
+				VL53L0X_REG_FINAL_RANGE_CONFIG_VCSEL_PERIOD,
+					vcsel_period_reg);
+
+
+			if (Status == VL53L0X_ERROR_NONE)
+				Status = set_sequence_step_timeout(Dev,
+					VL53L0X_SEQUENCESTEP_FINAL_RANGE,
+					FinalRangeTimeoutMicroSeconds);
+
+			VL53L0X_SETDEVICESPECIFICPARAMETER(
+				Dev,
+				FinalRangeVcselPulsePeriod,
+				VCSELPulsePeriodPCLK);
+			break;
+		default:
+			Status = VL53L0X_ERROR_INVALID_PARAMS;
+		}
+	}
+
+	/* Finally, the timing budget must be re-applied */
+	if (Status == VL53L0X_ERROR_NONE) {
+		VL53L0X_GETPARAMETERFIELD(Dev,
+			MeasurementTimingBudgetMicroSeconds,
+			MeasurementTimingBudgetMicroSeconds);
+
+		Status = VL53L0X_SetMeasurementTimingBudgetMicroSeconds(Dev,
+				MeasurementTimingBudgetMicroSeconds);
+	}
+
+	/* Perform the phase calibration. This is needed after changing on
+	 * vcsel period.
+	 * get_data_enable = 0, restore_config = 1 */
+	if (Status == VL53L0X_ERROR_NONE)
+		Status = VL53L0X_perform_phase_calibration(
+			Dev, &PhaseCalInt, 0, 1);
+
+	return Status;
+}
+
+VL53L0X_Error VL53L0X_get_vcsel_pulse_period(VL53L0X_DEV Dev,
+	VL53L0X_VcselPeriod VcselPeriodType, uint8_t *pVCSELPulsePeriodPCLK)
+{
+	VL53L0X_Error Status = VL53L0X_ERROR_NONE;
+	uint8_t vcsel_period_reg;
+
+	switch (VcselPeriodType) {
+	case VL53L0X_VCSEL_PERIOD_PRE_RANGE:
+		Status = VL53L0X_RdByte(Dev,
+			VL53L0X_REG_PRE_RANGE_CONFIG_VCSEL_PERIOD,
+			&vcsel_period_reg);
+	break;
+	case VL53L0X_VCSEL_PERIOD_FINAL_RANGE:
+		Status = VL53L0X_RdByte(Dev,
+			VL53L0X_REG_FINAL_RANGE_CONFIG_VCSEL_PERIOD,
+			&vcsel_period_reg);
+	break;
+	default:
+		Status = VL53L0X_ERROR_INVALID_PARAMS;
+	}
+
+	if (Status == VL53L0X_ERROR_NONE)
+		*pVCSELPulsePeriodPCLK =
+			VL53L0X_decode_vcsel_period(vcsel_period_reg);
+
+	return Status;
+}
+
+
+
+VL53L0X_Error VL53L0X_set_measurement_timing_budget_micro_seconds(VL53L0X_DEV Dev,
+		uint32_t MeasurementTimingBudgetMicroSeconds)
+{
+	VL53L0X_Error Status = VL53L0X_ERROR_NONE;
+	uint32_t FinalRangeTimingBudgetMicroSeconds;
+	VL53L0X_SchedulerSequenceSteps_t SchedulerSequenceSteps;
+	uint32_t MsrcDccTccTimeoutMicroSeconds	= 2000;
+	uint32_t StartOverheadMicroSeconds		= 1320;
+	uint32_t EndOverheadMicroSeconds		= 960;
+	uint32_t MsrcOverheadMicroSeconds		= 660;
+	uint32_t TccOverheadMicroSeconds		= 590;
+	uint32_t DssOverheadMicroSeconds		= 690;
+	uint32_t PreRangeOverheadMicroSeconds	= 660;
+	uint32_t FinalRangeOverheadMicroSeconds = 550;
+	uint32_t PreRangeTimeoutMicroSeconds	= 0;
+	uint32_t cMinTimingBudgetMicroSeconds	= 20000;
+	uint32_t SubTimeout = 0;
+
+	LOG_FUNCTION_START("");
+
+	if (MeasurementTimingBudgetMicroSeconds
+			< cMinTimingBudgetMicroSeconds) {
+		Status = VL53L0X_ERROR_INVALID_PARAMS;
+		return Status;
+	}
+
+	FinalRangeTimingBudgetMicroSeconds =
+		MeasurementTimingBudgetMicroSeconds -
+		(StartOverheadMicroSeconds + EndOverheadMicroSeconds);
+
+	Status = VL53L0X_GetSequenceStepEnables(Dev, &SchedulerSequenceSteps);
+
+	if (Status == VL53L0X_ERROR_NONE &&
+		(SchedulerSequenceSteps.TccOn  ||
+		SchedulerSequenceSteps.MsrcOn ||
+		SchedulerSequenceSteps.DssOn)) {
+
+		/* TCC, MSRC and DSS all share the same timeout */
+		Status = get_sequence_step_timeout(Dev,
+					VL53L0X_SEQUENCESTEP_MSRC,
+					&MsrcDccTccTimeoutMicroSeconds);
+
+		/* Subtract the TCC, MSRC and DSS timeouts if they are
+		 * enabled. */
+
+		if (Status != VL53L0X_ERROR_NONE)
+			return Status;
+
+		/* TCC */
+		if (SchedulerSequenceSteps.TccOn) {
+
+			SubTimeout = MsrcDccTccTimeoutMicroSeconds
+				+ TccOverheadMicroSeconds;
+
+			if (SubTimeout <
+				FinalRangeTimingBudgetMicroSeconds) {
+				FinalRangeTimingBudgetMicroSeconds -=
+							SubTimeout;
+			} else {
+				/* Requested timeout too big. */
+				Status = VL53L0X_ERROR_INVALID_PARAMS;
+			}
+		}
+
+		if (Status != VL53L0X_ERROR_NONE) {
+			LOG_FUNCTION_END(Status);
+			return Status;
+		}
+
+		/* DSS */
+		if (SchedulerSequenceSteps.DssOn) {
+
+			SubTimeout = 2 * (MsrcDccTccTimeoutMicroSeconds +
+				DssOverheadMicroSeconds);
+
+			if (SubTimeout < FinalRangeTimingBudgetMicroSeconds) {
+				FinalRangeTimingBudgetMicroSeconds
+							-= SubTimeout;
+			} else {
+				/* Requested timeout too big. */
+				Status = VL53L0X_ERROR_INVALID_PARAMS;
+			}
+		} else if (SchedulerSequenceSteps.MsrcOn) {
+			/* MSRC */
+			SubTimeout = MsrcDccTccTimeoutMicroSeconds +
+						MsrcOverheadMicroSeconds;
+
+			if (SubTimeout < FinalRangeTimingBudgetMicroSeconds) {
+				FinalRangeTimingBudgetMicroSeconds
+							-= SubTimeout;
+			} else {
+				/* Requested timeout too big. */
+				Status = VL53L0X_ERROR_INVALID_PARAMS;
+			}
+		}
+
+	}
+
+	if (Status != VL53L0X_ERROR_NONE) {
+		LOG_FUNCTION_END(Status);
+		return Status;
+	}
+
+	if (SchedulerSequenceSteps.PreRangeOn) {
+
+		/* Subtract the Pre-range timeout if enabled. */
+
+		Status = get_sequence_step_timeout(Dev,
+				VL53L0X_SEQUENCESTEP_PRE_RANGE,
+				&PreRangeTimeoutMicroSeconds);
+
+		SubTimeout = PreRangeTimeoutMicroSeconds +
+				PreRangeOverheadMicroSeconds;
+
+		if (SubTimeout < FinalRangeTimingBudgetMicroSeconds) {
+			FinalRangeTimingBudgetMicroSeconds -= SubTimeout;
+		} else {
+			/* Requested timeout too big. */
+			Status = VL53L0X_ERROR_INVALID_PARAMS;
+		}
+	}
+
+
+	if (Status == VL53L0X_ERROR_NONE &&
+		SchedulerSequenceSteps.FinalRangeOn) {
+
+		FinalRangeTimingBudgetMicroSeconds -=
+				FinalRangeOverheadMicroSeconds;
+
+		/* Final Range Timeout
+		* Note that the final range timeout is determined by the timing
+		* budget and the sum of all other timeouts within the sequence.
+		* If there is no room for the final range timeout, then an error
+		* will be set. Otherwise the remaining time will be applied to
+		* the final range.
+		*/
+		Status = set_sequence_step_timeout(Dev,
+			   VL53L0X_SEQUENCESTEP_FINAL_RANGE,
+			   FinalRangeTimingBudgetMicroSeconds);
+
+		VL53L0X_SETPARAMETERFIELD(Dev,
+			   MeasurementTimingBudgetMicroSeconds,
+			   MeasurementTimingBudgetMicroSeconds);
+	}
+
+	LOG_FUNCTION_END(Status);
+
+	return Status;
+}
+
+VL53L0X_Error VL53L0X_get_measurement_timing_budget_micro_seconds(VL53L0X_DEV Dev,
+		uint32_t *pMeasurementTimingBudgetMicroSeconds)
+{
+	VL53L0X_Error Status = VL53L0X_ERROR_NONE;
+	VL53L0X_SchedulerSequenceSteps_t SchedulerSequenceSteps;
+	uint32_t FinalRangeTimeoutMicroSeconds;
+	uint32_t MsrcDccTccTimeoutMicroSeconds	= 2000;
+	uint32_t StartOverheadMicroSeconds		= 1910;
+	uint32_t EndOverheadMicroSeconds		= 960;
+	uint32_t MsrcOverheadMicroSeconds		= 660;
+	uint32_t TccOverheadMicroSeconds		= 590;
+	uint32_t DssOverheadMicroSeconds		= 690;
+	uint32_t PreRangeOverheadMicroSeconds	= 660;
+	uint32_t FinalRangeOverheadMicroSeconds = 550;
+	uint32_t PreRangeTimeoutMicroSeconds	= 0;
+
+	LOG_FUNCTION_START("");
+
+	/* Start and end overhead times always present */
+	*pMeasurementTimingBudgetMicroSeconds
+		= StartOverheadMicroSeconds + EndOverheadMicroSeconds;
+
+	Status = VL53L0X_GetSequenceStepEnables(Dev, &SchedulerSequenceSteps);
+
+	if (Status != VL53L0X_ERROR_NONE) {
+		LOG_FUNCTION_END(Status);
+		return Status;
+	}
+
+
+	if (SchedulerSequenceSteps.TccOn  ||
+		SchedulerSequenceSteps.MsrcOn ||
+		SchedulerSequenceSteps.DssOn) {
+
+		Status = get_sequence_step_timeout(Dev,
+				VL53L0X_SEQUENCESTEP_MSRC,
+				&MsrcDccTccTimeoutMicroSeconds);
+
+		if (Status == VL53L0X_ERROR_NONE) {
+			if (SchedulerSequenceSteps.TccOn) {
+				*pMeasurementTimingBudgetMicroSeconds +=
+					MsrcDccTccTimeoutMicroSeconds +
+					TccOverheadMicroSeconds;
+			}
+
+			if (SchedulerSequenceSteps.DssOn) {
+				*pMeasurementTimingBudgetMicroSeconds +=
+				2 * (MsrcDccTccTimeoutMicroSeconds +
+					DssOverheadMicroSeconds);
+			} else if (SchedulerSequenceSteps.MsrcOn) {
+				*pMeasurementTimingBudgetMicroSeconds +=
+					MsrcDccTccTimeoutMicroSeconds +
+					MsrcOverheadMicroSeconds;
+			}
+		}
+	}
+
+	if (Status == VL53L0X_ERROR_NONE) {
+		if (SchedulerSequenceSteps.PreRangeOn) {
+			Status = get_sequence_step_timeout(Dev,
+				VL53L0X_SEQUENCESTEP_PRE_RANGE,
+				&PreRangeTimeoutMicroSeconds);
+			*pMeasurementTimingBudgetMicroSeconds +=
+				PreRangeTimeoutMicroSeconds +
+				PreRangeOverheadMicroSeconds;
+		}
+	}
+
+	if (Status == VL53L0X_ERROR_NONE) {
+		if (SchedulerSequenceSteps.FinalRangeOn) {
+			Status = get_sequence_step_timeout(Dev,
+					VL53L0X_SEQUENCESTEP_FINAL_RANGE,
+					&FinalRangeTimeoutMicroSeconds);
+			*pMeasurementTimingBudgetMicroSeconds +=
+				(FinalRangeTimeoutMicroSeconds +
+				FinalRangeOverheadMicroSeconds);
+		}
+	}
+
+	if (Status == VL53L0X_ERROR_NONE) {
+		VL53L0X_SETPARAMETERFIELD(Dev,
+			MeasurementTimingBudgetMicroSeconds,
+			*pMeasurementTimingBudgetMicroSeconds);
+	}
+
+	LOG_FUNCTION_END(Status);
+	return Status;
+}
+
+
+
+VL53L0X_Error VL53L0X_load_tuning_settings(VL53L0X_DEV Dev,
+		uint8_t *pTuningSettingBuffer)
+{
+	VL53L0X_Error Status = VL53L0X_ERROR_NONE;
+	int i;
+	int Index;
+	uint8_t msb;
+	uint8_t lsb;
+	uint8_t SelectParam;
+	uint8_t NumberOfWrites;
+	uint8_t Address;
+	uint8_t localBuffer[4]; /* max */
+	uint16_t Temp16;
+
+	LOG_FUNCTION_START("");
+
+	Index = 0;
+
+	while ((*(pTuningSettingBuffer + Index) != 0) &&
+			(Status == VL53L0X_ERROR_NONE)) {
+		NumberOfWrites = *(pTuningSettingBuffer + Index);
+		Index++;
+		if (NumberOfWrites == 0xFF) {
+			/* internal parameters */
+			SelectParam = *(pTuningSettingBuffer + Index);
+			Index++;
+			switch (SelectParam) {
+			case 0: /* uint16_t SigmaEstRefArray -> 2 bytes */
+				msb = *(pTuningSettingBuffer + Index);
+				Index++;
+				lsb = *(pTuningSettingBuffer + Index);
+				Index++;
+				Temp16 = VL53L0X_MAKEUINT16(lsb, msb);
+				PALDevDataSet(Dev, SigmaEstRefArray, Temp16);
+				break;
+			case 1: /* uint16_t SigmaEstEffPulseWidth -> 2 bytes */
+				msb = *(pTuningSettingBuffer + Index);
+				Index++;
+				lsb = *(pTuningSettingBuffer + Index);
+				Index++;
+				Temp16 = VL53L0X_MAKEUINT16(lsb, msb);
+				PALDevDataSet(Dev, SigmaEstEffPulseWidth,
+					Temp16);
+				break;
+			case 2: /* uint16_t SigmaEstEffAmbWidth -> 2 bytes */
+				msb = *(pTuningSettingBuffer + Index);
+				Index++;
+				lsb = *(pTuningSettingBuffer + Index);
+				Index++;
+				Temp16 = VL53L0X_MAKEUINT16(lsb, msb);
+				PALDevDataSet(Dev, SigmaEstEffAmbWidth, Temp16);
+				break;
+			case 3: /* uint16_t targetRefRate -> 2 bytes */
+				msb = *(pTuningSettingBuffer + Index);
+				Index++;
+				lsb = *(pTuningSettingBuffer + Index);
+				Index++;
+				Temp16 = VL53L0X_MAKEUINT16(lsb, msb);
+				PALDevDataSet(Dev, targetRefRate, Temp16);
+				break;
+			default: /* invalid parameter */
+				Status = VL53L0X_ERROR_INVALID_PARAMS;
+			}
+
+		} else if (NumberOfWrites <= 4) {
+			Address = *(pTuningSettingBuffer + Index);
+			Index++;
+
+			for (i = 0; i < NumberOfWrites; i++) {
+				localBuffer[i] = *(pTuningSettingBuffer +
+							Index);
+				Index++;
+			}
+
+			Status = VL53L0X_WriteMulti(Dev, Address, localBuffer,
+					NumberOfWrites);
+
+		} else {
+			Status = VL53L0X_ERROR_INVALID_PARAMS;
+		}
+	}
+
+	LOG_FUNCTION_END(Status);
+	return Status;
+}
+
+VL53L0X_Error VL53L0X_get_total_xtalk_rate(VL53L0X_DEV Dev,
+	VL53L0X_RangingMeasurementData_t *pRangingMeasurementData,
+	FixPoint1616_t *ptotal_xtalk_rate_mcps)
+{
+	VL53L0X_Error Status = VL53L0X_ERROR_NONE;
+
+	uint8_t xtalkCompEnable;
+	FixPoint1616_t totalXtalkMegaCps;
+	FixPoint1616_t xtalkPerSpadMegaCps;
+
+	*ptotal_xtalk_rate_mcps = 0;
+
+	Status = VL53L0X_GetXTalkCompensationEnable(Dev, &xtalkCompEnable);
+	if (Status == VL53L0X_ERROR_NONE) {
+
+		if (xtalkCompEnable) {
+
+			VL53L0X_GETPARAMETERFIELD(
+				Dev,
+				XTalkCompensationRateMegaCps,
+				xtalkPerSpadMegaCps);
+
+			/* FixPoint1616 * FixPoint 8:8 = FixPoint0824 */
+			totalXtalkMegaCps =
+				pRangingMeasurementData->EffectiveSpadRtnCount *
+				xtalkPerSpadMegaCps;
+
+			/* FixPoint0824 >> 8 = FixPoint1616 */
+			*ptotal_xtalk_rate_mcps =
+				(totalXtalkMegaCps + 0x80) >> 8;
+		}
+	}
+
+	return Status;
+}
+
+VL53L0X_Error VL53L0X_get_total_signal_rate(VL53L0X_DEV Dev,
+	VL53L0X_RangingMeasurementData_t *pRangingMeasurementData,
+	FixPoint1616_t *ptotal_signal_rate_mcps)
+{
+	VL53L0X_Error Status = VL53L0X_ERROR_NONE;
+	FixPoint1616_t totalXtalkMegaCps;
+
+	LOG_FUNCTION_START("");
+
+	*ptotal_signal_rate_mcps =
+		pRangingMeasurementData->SignalRateRtnMegaCps;
+
+	Status = VL53L0X_get_total_xtalk_rate(
+		Dev, pRangingMeasurementData, &totalXtalkMegaCps);
+
+	if (Status == VL53L0X_ERROR_NONE)
+		*ptotal_signal_rate_mcps += totalXtalkMegaCps;
+
+	return Status;
+}
+
+VL53L0X_Error VL53L0X_calc_dmax(
+	VL53L0X_DEV Dev,
+	FixPoint1616_t totalSignalRate_mcps,
+	FixPoint1616_t totalCorrSignalRate_mcps,
+	FixPoint1616_t pwMult,
+	uint32_t sigmaEstimateP1,
+	FixPoint1616_t sigmaEstimateP2,
+	uint32_t peakVcselDuration_us,
+	uint32_t *pdmax_mm)
+{
+	const uint32_t cSigmaLimit		= 18;
+	const FixPoint1616_t cSignalLimit	= 0x4000; /* 0.25 */
+	const FixPoint1616_t cSigmaEstRef	= 0x00000042; /* 0.001 */
+	const uint32_t cAmbEffWidthSigmaEst_ns = 6;
+	const uint32_t cAmbEffWidthDMax_ns	   = 7;
+	uint32_t dmaxCalRange_mm;
+	FixPoint1616_t dmaxCalSignalRateRtn_mcps;
+	FixPoint1616_t minSignalNeeded;
+	FixPoint1616_t minSignalNeeded_p1;
+	FixPoint1616_t minSignalNeeded_p2;
+	FixPoint1616_t minSignalNeeded_p3;
+	FixPoint1616_t minSignalNeeded_p4;
+	FixPoint1616_t sigmaLimitTmp;
+	FixPoint1616_t sigmaEstSqTmp;
+	FixPoint1616_t signalLimitTmp;
+	FixPoint1616_t SignalAt0mm;
+	FixPoint1616_t dmaxDark;
+	FixPoint1616_t dmaxAmbient;
+	FixPoint1616_t dmaxDarkTmp;
+	FixPoint1616_t sigmaEstP2Tmp;
+	uint32_t signalRateTemp_mcps;
+
+	VL53L0X_Error Status = VL53L0X_ERROR_NONE;
+
+	LOG_FUNCTION_START("");
+
+	dmaxCalRange_mm =
+		PALDevDataGet(Dev, DmaxCalRangeMilliMeter);
+
+	dmaxCalSignalRateRtn_mcps =
+		PALDevDataGet(Dev, DmaxCalSignalRateRtnMegaCps);
+
+	/* uint32 * FixPoint1616 = FixPoint1616 */
+	SignalAt0mm = dmaxCalRange_mm * dmaxCalSignalRateRtn_mcps;
+
+	/* FixPoint1616 >> 8 = FixPoint2408 */
+	SignalAt0mm = (SignalAt0mm + 0x80) >> 8;
+	SignalAt0mm *= dmaxCalRange_mm;
+
+	minSignalNeeded_p1 = 0;
+	if (totalCorrSignalRate_mcps > 0) {
+
+		/* Shift by 10 bits to increase resolution prior to the
+		 * division */
+		signalRateTemp_mcps = totalSignalRate_mcps << 10;
+
+		/* Add rounding value prior to division */
+		minSignalNeeded_p1 = signalRateTemp_mcps +
+			(totalCorrSignalRate_mcps/2);
+
+		/* FixPoint0626/FixPoint1616 = FixPoint2210 */
+		minSignalNeeded_p1 /= totalCorrSignalRate_mcps;
+
+		/* Apply a factored version of the speed of light.
+		 Correction to be applied at the end */
+		minSignalNeeded_p1 *= 3;
+
+		/* FixPoint2210 * FixPoint2210 = FixPoint1220 */
+		minSignalNeeded_p1 *= minSignalNeeded_p1;
+
+		/* FixPoint1220 >> 16 = FixPoint2804 */
+		minSignalNeeded_p1 = (minSignalNeeded_p1 + 0x8000) >> 16;
+	}
+
+	minSignalNeeded_p2 = pwMult * sigmaEstimateP1;
+
+	/* FixPoint1616 >> 16 =	 uint32 */
+	minSignalNeeded_p2 = (minSignalNeeded_p2 + 0x8000) >> 16;
+
+	/* uint32 * uint32	=  uint32 */
+	minSignalNeeded_p2 *= minSignalNeeded_p2;
+
+	/* Check sigmaEstimateP2
+	 * If this value is too high there is not enough signal rate
+	 * to calculate dmax value so set a suitable value to ensure
+	 * a very small dmax.
+	 */
+	sigmaEstP2Tmp = (sigmaEstimateP2 + 0x8000) >> 16;
+	sigmaEstP2Tmp = (sigmaEstP2Tmp + cAmbEffWidthSigmaEst_ns/2)/
+		cAmbEffWidthSigmaEst_ns;
+	sigmaEstP2Tmp *= cAmbEffWidthDMax_ns;
+
+	if (sigmaEstP2Tmp > 0xffff) {
+		minSignalNeeded_p3 = 0xfff00000;
+	} else {
+
+		/* DMAX uses a different ambient width from sigma, so apply
+		 * correction.
+		 * Perform division before multiplication to prevent overflow.
+		 */
+		sigmaEstimateP2 = (sigmaEstimateP2 + cAmbEffWidthSigmaEst_ns/2)/
+			cAmbEffWidthSigmaEst_ns;
+		sigmaEstimateP2 *= cAmbEffWidthDMax_ns;
+
+		/* FixPoint1616 >> 16 = uint32 */
+		minSignalNeeded_p3 = (sigmaEstimateP2 + 0x8000) >> 16;
+
+		minSignalNeeded_p3 *= minSignalNeeded_p3;
+
+	}
+
+	/* FixPoint1814 / uint32 = FixPoint1814 */
+	sigmaLimitTmp = ((cSigmaLimit << 14) + 500) / 1000;
+
+	/* FixPoint1814 * FixPoint1814 = FixPoint3628 := FixPoint0428 */
+	sigmaLimitTmp *= sigmaLimitTmp;
+
+	/* FixPoint1616 * FixPoint1616 = FixPoint3232 */
+	sigmaEstSqTmp = cSigmaEstRef * cSigmaEstRef;
+
+	/* FixPoint3232 >> 4 = FixPoint0428 */
+	sigmaEstSqTmp = (sigmaEstSqTmp + 0x08) >> 4;
+
+	/* FixPoint0428 - FixPoint0428	= FixPoint0428 */
+	sigmaLimitTmp -=  sigmaEstSqTmp;
+
+	/* uint32_t * FixPoint0428 = FixPoint0428 */
+	minSignalNeeded_p4 = 4 * 12 * sigmaLimitTmp;
+
+	/* FixPoint0428 >> 14 = FixPoint1814 */
+	minSignalNeeded_p4 = (minSignalNeeded_p4 + 0x2000) >> 14;
+
+	/* uint32 + uint32 = uint32 */
+	minSignalNeeded = (minSignalNeeded_p2 + minSignalNeeded_p3);
+
+	/* uint32 / uint32 = uint32 */
+	minSignalNeeded += (peakVcselDuration_us/2);
+	minSignalNeeded /= peakVcselDuration_us;
+
+	/* uint32 << 14 = FixPoint1814 */
+	minSignalNeeded <<= 14;
+
+	/* FixPoint1814 / FixPoint1814 = uint32 */
+	minSignalNeeded += (minSignalNeeded_p4/2);
+	minSignalNeeded /= minSignalNeeded_p4;
+
+	/* FixPoint3200 * FixPoint2804 := FixPoint2804*/
+	minSignalNeeded *= minSignalNeeded_p1;
+
+	/* Apply correction by dividing by 1000000.
+	 * This assumes 10E16 on the numerator of the equation
+	 * and 10E-22 on the denominator.
+	 * We do this because 32bit fix point calculation can't
+	 * handle the larger and smaller elements of this equation,
+	 * i.e. speed of light and pulse widths.
+	 */
+	minSignalNeeded = (minSignalNeeded + 500) / 1000;
+	minSignalNeeded <<= 4;
+
+	minSignalNeeded = (minSignalNeeded + 500) / 1000;
+
+	/* FixPoint1616 >> 8 = FixPoint2408 */
+	signalLimitTmp = (cSignalLimit + 0x80) >> 8;
+
+	/* FixPoint2408/FixPoint2408 = uint32 */
+	if (signalLimitTmp != 0)
+		dmaxDarkTmp = (SignalAt0mm + (signalLimitTmp / 2))
+			/ signalLimitTmp;
+	else
+		dmaxDarkTmp = 0;
+
+	dmaxDark = VL53L0X_isqrt(dmaxDarkTmp);
+
+	/* FixPoint2408/FixPoint2408 = uint32 */
+	if (minSignalNeeded != 0)
+		dmaxAmbient = (SignalAt0mm + minSignalNeeded/2)
+			/ minSignalNeeded;
+	else
+		dmaxAmbient = 0;
+
+	dmaxAmbient = VL53L0X_isqrt(dmaxAmbient);
+
+	*pdmax_mm = dmaxDark;
+	if (dmaxDark > dmaxAmbient)
+		*pdmax_mm = dmaxAmbient;
+
+	LOG_FUNCTION_END(Status);
+
+	return Status;
+}
+
+
+VL53L0X_Error VL53L0X_calc_sigma_estimate(VL53L0X_DEV Dev,
+	VL53L0X_RangingMeasurementData_t *pRangingMeasurementData,
+	FixPoint1616_t *pSigmaEstimate,
+	uint32_t *pDmax_mm)
+{
+	/* Expressed in 100ths of a ns, i.e. centi-ns */
+	const uint32_t cPulseEffectiveWidth_centi_ns   = 800;
+	/* Expressed in 100ths of a ns, i.e. centi-ns */
+	const uint32_t cAmbientEffectiveWidth_centi_ns = 600;
+	const FixPoint1616_t cSigmaEstRef	= 0x00000042; /* 0.001 */
+	const uint32_t cVcselPulseWidth_ps	= 4700; /* pico secs */
+	const FixPoint1616_t cSigmaEstMax	= 0x028F87AE;
+	const FixPoint1616_t cSigmaEstRtnMax	= 0xF000;
+	const FixPoint1616_t cAmbToSignalRatioMax = 0xF0000000/
+		cAmbientEffectiveWidth_centi_ns;
+	/* Time Of Flight per mm (6.6 pico secs) */
+	const FixPoint1616_t cTOF_per_mm_ps		= 0x0006999A;
+	const uint32_t c16BitRoundingParam		= 0x00008000;
+	const FixPoint1616_t cMaxXTalk_kcps		= 0x00320000;
+	const uint32_t cPllPeriod_ps			= 1655;
+
+	uint32_t vcselTotalEventsRtn;
+	uint32_t finalRangeTimeoutMicroSecs;
+	uint32_t preRangeTimeoutMicroSecs;
+	FixPoint1616_t sigmaEstimateP1;
+	FixPoint1616_t sigmaEstimateP2;
+	FixPoint1616_t sigmaEstimateP3;
+	FixPoint1616_t deltaT_ps;
+	FixPoint1616_t pwMult;
+	FixPoint1616_t sigmaEstRtn;
+	FixPoint1616_t sigmaEstimate;
+	FixPoint1616_t xTalkCorrection;
+	FixPoint1616_t ambientRate_kcps;
+	FixPoint1616_t peakSignalRate_kcps;
+	FixPoint1616_t xTalkCompRate_mcps;
+	uint32_t xTalkCompRate_kcps;
+	VL53L0X_Error Status = VL53L0X_ERROR_NONE;
+	FixPoint1616_t diff1_mcps;
+	FixPoint1616_t diff2_mcps;
+	FixPoint1616_t sqr1;
+	FixPoint1616_t sqr2;
+	FixPoint1616_t sqrSum;
+	FixPoint1616_t sqrtResult_centi_ns;
+	FixPoint1616_t sqrtResult;
+	FixPoint1616_t totalSignalRate_mcps;
+	FixPoint1616_t correctedSignalRate_mcps;
+	uint32_t vcselWidth;
+	uint32_t finalRangeMacroPCLKS;
+	uint32_t preRangeMacroPCLKS;
+	uint32_t peakVcselDuration_us;
+	uint8_t finalRangeVcselPCLKS;
+	uint8_t preRangeVcselPCLKS;
+	/*! \addtogroup calc_sigma_estimate
+	 * @{
+	 *
+	 * Estimates the range sigma based on the
+	 *
+	 *	- vcsel_rate_kcps
+	 *	- ambient_rate_kcps
+	 *	- signal_total_events
+	 *	- xtalk_rate
+	 *
+	 * and the following parameters
+	 *
+	 *	- SigmaEstRefArray
+	 *	- SigmaEstEffPulseWidth
+	 *	- SigmaEstEffAmbWidth
+	 */
+
+	LOG_FUNCTION_START("");
+
+	VL53L0X_GETPARAMETERFIELD(Dev, XTalkCompensationRateMegaCps,
+			xTalkCompRate_mcps);
+
+	/*
+	 * We work in kcps rather than mcps as this helps keep within the
+	 * confines of the 32 Fix1616 type.
+	 */
+
+	ambientRate_kcps =
+		(pRangingMeasurementData->AmbientRateRtnMegaCps * 1000) >> 16;
+
+	correctedSignalRate_mcps =
+		pRangingMeasurementData->SignalRateRtnMegaCps;
+
+
+	Status = VL53L0X_get_total_signal_rate(
+		Dev, pRangingMeasurementData, &totalSignalRate_mcps);
+	Status = VL53L0X_get_total_xtalk_rate(
+		Dev, pRangingMeasurementData, &xTalkCompRate_mcps);
+
+
+	/* Signal rate measurement provided by device is the
+	 * peak signal rate, not average.
+	 */
+	peakSignalRate_kcps = (totalSignalRate_mcps * 1000);
+	peakSignalRate_kcps = (peakSignalRate_kcps + 0x8000) >> 16;
+
+	xTalkCompRate_kcps = xTalkCompRate_mcps * 1000;
+
+	if (xTalkCompRate_kcps > cMaxXTalk_kcps)
+		xTalkCompRate_kcps = cMaxXTalk_kcps;
+
+	if (Status == VL53L0X_ERROR_NONE) {
+
+		/* Calculate final range macro periods */
+		finalRangeTimeoutMicroSecs = VL53L0X_GETDEVICESPECIFICPARAMETER(
+			Dev, FinalRangeTimeoutMicroSecs);
+
+		finalRangeVcselPCLKS = VL53L0X_GETDEVICESPECIFICPARAMETER(
+			Dev, FinalRangeVcselPulsePeriod);
+
+		finalRangeMacroPCLKS = VL53L0X_calc_timeout_mclks(
+			Dev, finalRangeTimeoutMicroSecs, finalRangeVcselPCLKS);
+
+		/* Calculate pre-range macro periods */
+		preRangeTimeoutMicroSecs = VL53L0X_GETDEVICESPECIFICPARAMETER(
+			Dev, PreRangeTimeoutMicroSecs);
+
+		preRangeVcselPCLKS = VL53L0X_GETDEVICESPECIFICPARAMETER(
+			Dev, PreRangeVcselPulsePeriod);
+
+		preRangeMacroPCLKS = VL53L0X_calc_timeout_mclks(
+			Dev, preRangeTimeoutMicroSecs, preRangeVcselPCLKS);
+
+		vcselWidth = 3;
+		if (finalRangeVcselPCLKS == 8)
+			vcselWidth = 2;
+
+
+		peakVcselDuration_us = vcselWidth * 2048 *
+			(preRangeMacroPCLKS + finalRangeMacroPCLKS);
+		peakVcselDuration_us = (peakVcselDuration_us + 500)/1000;
+		peakVcselDuration_us *= cPllPeriod_ps;
+		peakVcselDuration_us = (peakVcselDuration_us + 500)/1000;
+
+		/* Fix1616 >> 8 = Fix2408 */
+		totalSignalRate_mcps = (totalSignalRate_mcps + 0x80) >> 8;
+
+		/* Fix2408 * uint32 = Fix2408 */
+		vcselTotalEventsRtn = totalSignalRate_mcps *
+			peakVcselDuration_us;
+
+		/* Fix2408 >> 8 = uint32 */
+		vcselTotalEventsRtn = (vcselTotalEventsRtn + 0x80) >> 8;
+
+		/* Fix2408 << 8 = Fix1616 = */
+		totalSignalRate_mcps <<= 8;
+	}
+
+	if (Status != VL53L0X_ERROR_NONE) {
+		LOG_FUNCTION_END(Status);
+		return Status;
+	}
+
+	if (peakSignalRate_kcps == 0) {
+		*pSigmaEstimate = cSigmaEstMax;
+		PALDevDataSet(Dev, SigmaEstimate, cSigmaEstMax);
+		*pDmax_mm = 0;
+	} else {
+		if (vcselTotalEventsRtn < 1)
+			vcselTotalEventsRtn = 1;
+
+		/*
+		 * Calculate individual components of the main equation -
+		 * replicating the equation implemented in the script
+		 * OpenAll_Ewok_ranging_data.jsl.
+		 *
+		 * sigmaEstimateP1 represents the effective pulse width, which
+		 * is a tuning parameter, rather than a real value.
+		 *
+		 * sigmaEstimateP2 represents the ambient/signal rate ratio
+		 * expressed as a multiple of the effective ambient width
+		 * (tuning parameter).
+		 *
+		 * sigmaEstimateP3 provides the signal event component, with the
+		 * knowledge that
+		 *	- Noise of a square pulse is 1/sqrt(12) of the pulse
+		 *	 width.
+		 *	- at 0Lux, sigma is proportional to
+		 *	  effectiveVcselPulseWidth/sqrt(12 * signalTotalEvents)
+		 *
+		 * deltaT_ps represents the time of flight in pico secs for the
+		 * current range measurement, using the "TOF per mm" constant
+		 * (in ps).
+		 */
+
+		sigmaEstimateP1 = cPulseEffectiveWidth_centi_ns;
+
+		/* ((FixPoint1616 << 16)* uint32)/uint32 = FixPoint1616 */
+		sigmaEstimateP2 = (ambientRate_kcps << 16)/peakSignalRate_kcps;
+		if (sigmaEstimateP2 > cAmbToSignalRatioMax) {
+			/* Clip to prevent overflow. Will ensure safe
+			 * max result. */
+			sigmaEstimateP2 = cAmbToSignalRatioMax;
+		}
+		sigmaEstimateP2 *= cAmbientEffectiveWidth_centi_ns;
+
+		sigmaEstimateP3 = 2 * VL53L0X_isqrt(vcselTotalEventsRtn * 12);
+
+		/* uint32 * FixPoint1616 = FixPoint1616 */
+		deltaT_ps = pRangingMeasurementData->RangeMilliMeter *
+					cTOF_per_mm_ps;
+
+		/*
+		 * vcselRate - xtalkCompRate
+		 * (uint32 << 16) - FixPoint1616 = FixPoint1616.
+		 * Divide result by 1000 to convert to mcps.
+		 * 500 is added to ensure rounding when integer division
+		 * truncates.
+		 */
+		diff1_mcps = (((peakSignalRate_kcps << 16) -
+			xTalkCompRate_kcps) + 500)/1000;
+
+		/* vcselRate + xtalkCompRate */
+		diff2_mcps = (((peakSignalRate_kcps << 16) +
+			xTalkCompRate_kcps) + 500)/1000;
+
+		/* Shift by 8 bits to increase resolution prior to the
+		 * division */
+		diff1_mcps <<= 8;
+
+		/* FixPoint0824/FixPoint1616 = FixPoint2408 */
+		xTalkCorrection	 = diff1_mcps/diff2_mcps;
+		if(xTalkCorrection < 0){
+			xTalkCorrection = -xTalkCorrection;
+		}
+
+		/* FixPoint2408 << 8 = FixPoint1616 */
+		xTalkCorrection <<= 8;
+
+		/* FixPoint1616/uint32 = FixPoint1616 */
+		pwMult = deltaT_ps/cVcselPulseWidth_ps; /* smaller than 1.0f */
+
+		/*
+		 * FixPoint1616 * FixPoint1616 = FixPoint3232, however both
+		 * values are small enough such that32 bits will not be
+		 * exceeded.
+		 */
+		pwMult *= ((1 << 16) - xTalkCorrection);
+
+		/* (FixPoint3232 >> 16) = FixPoint1616 */
+		pwMult =  (pwMult + c16BitRoundingParam) >> 16;
+
+		/* FixPoint1616 + FixPoint1616 = FixPoint1616 */
+		pwMult += (1 << 16);
+
+		/*
+		 * At this point the value will be 1.xx, therefore if we square
+		 * the value this will exceed 32 bits. To address this perform
+		 * a single shift to the right before the multiplication.
+		 */
+		pwMult >>= 1;
+		/* FixPoint1715 * FixPoint1715 = FixPoint3430 */
+		pwMult = pwMult * pwMult;
+
+		/* (FixPoint3430 >> 14) = Fix1616 */
+		pwMult >>= 14;
+
+		/* FixPoint1616 * uint32 = FixPoint1616 */
+		sqr1 = pwMult * sigmaEstimateP1;
+
+		/* (FixPoint1616 >> 16) = FixPoint3200 */
+		sqr1 = (sqr1 + 0x8000) >> 16;
+
+		/* FixPoint3200 * FixPoint3200 = FixPoint6400 */
+		sqr1 *= sqr1;
+
+		sqr2 = sigmaEstimateP2;
+
+		/* (FixPoint1616 >> 16) = FixPoint3200 */
+		sqr2 = (sqr2 + 0x8000) >> 16;
+
+		/* FixPoint3200 * FixPoint3200 = FixPoint6400 */
+		sqr2 *= sqr2;
+
+		/* FixPoint64000 + FixPoint6400 = FixPoint6400 */
+		sqrSum = sqr1 + sqr2;
+
+		/* SQRT(FixPoin6400) = FixPoint3200 */
+		sqrtResult_centi_ns = VL53L0X_isqrt(sqrSum);
+
+		/* (FixPoint3200 << 16) = FixPoint1616 */
+		sqrtResult_centi_ns <<= 16;
+
+		/*
+		 * Note that the Speed Of Light is expressed in um per 1E-10
+		 * seconds (2997) Therefore to get mm/ns we have to divide by
+		 * 10000
+		 */
+		sigmaEstRtn = (((sqrtResult_centi_ns+50)/100) /
+				sigmaEstimateP3);
+		sigmaEstRtn		 *= VL53L0X_SPEED_OF_LIGHT_IN_AIR;
+
+		/* Add 5000 before dividing by 10000 to ensure rounding. */
+		sigmaEstRtn		 += 5000;
+		sigmaEstRtn		 /= 10000;
+
+		if (sigmaEstRtn > cSigmaEstRtnMax) {
+			/* Clip to prevent overflow. Will ensure safe
+			 * max result. */
+			sigmaEstRtn = cSigmaEstRtnMax;
+		}
+
+		/* FixPoint1616 * FixPoint1616 = FixPoint3232 */
+		sqr1 = sigmaEstRtn * sigmaEstRtn;
+		/* FixPoint1616 * FixPoint1616 = FixPoint3232 */
+		sqr2 = cSigmaEstRef * cSigmaEstRef;
+
+		/* sqrt(FixPoint3232) = FixPoint1616 */
+		sqrtResult = VL53L0X_isqrt((sqr1 + sqr2));
+		/*
+		 * Note that the Shift by 4 bits increases resolution prior to
+		 * the sqrt, therefore the result must be shifted by 2 bits to
+		 * the right to revert back to the FixPoint1616 format.
+		 */
+
+		sigmaEstimate	 = 1000 * sqrtResult;
+
+		if ((peakSignalRate_kcps < 1) || (vcselTotalEventsRtn < 1) ||
+				(sigmaEstimate > cSigmaEstMax)) {
+				sigmaEstimate = cSigmaEstMax;
+		}
+
+		*pSigmaEstimate = (uint32_t)(sigmaEstimate);
+		PALDevDataSet(Dev, SigmaEstimate, *pSigmaEstimate);
+		Status = VL53L0X_calc_dmax(
+			Dev,
+			totalSignalRate_mcps,
+			correctedSignalRate_mcps,
+			pwMult,
+			sigmaEstimateP1,
+			sigmaEstimateP2,
+			peakVcselDuration_us,
+			pDmax_mm);
+	}
+
+	LOG_FUNCTION_END(Status);
+	return Status;
+}
+
+VL53L0X_Error VL53L0X_get_pal_range_status(VL53L0X_DEV Dev,
+		uint8_t DeviceRangeStatus,
+		FixPoint1616_t SignalRate,
+		uint16_t EffectiveSpadRtnCount,
+		VL53L0X_RangingMeasurementData_t *pRangingMeasurementData,
+		uint8_t *pPalRangeStatus)
+{
+	VL53L0X_Error Status = VL53L0X_ERROR_NONE;
+	uint8_t NoneFlag;
+	uint8_t SigmaLimitflag = 0;
+	uint8_t SignalRefClipflag = 0;
+	uint8_t RangeIgnoreThresholdflag = 0;
+	uint8_t SigmaLimitCheckEnable = 0;
+	uint8_t SignalRateFinalRangeLimitCheckEnable = 0;
+	uint8_t SignalRefClipLimitCheckEnable = 0;
+	uint8_t RangeIgnoreThresholdLimitCheckEnable = 0;
+	FixPoint1616_t SigmaEstimate;
+	FixPoint1616_t SigmaLimitValue;
+	FixPoint1616_t SignalRefClipValue;
+	FixPoint1616_t RangeIgnoreThresholdValue;
+	FixPoint1616_t SignalRatePerSpad;
+	uint8_t DeviceRangeStatusInternal = 0;
+	uint16_t tmpWord = 0;
+	uint8_t Temp8;
+	uint32_t Dmax_mm = 0;
+	FixPoint1616_t LastSignalRefMcps;
+
+	LOG_FUNCTION_START("");
+
+
+	/*
+	 * VL53L0X has a good ranging when the value of the
+	 * DeviceRangeStatus = 11. This function will replace the value 0 with
+	 * the value 11 in the DeviceRangeStatus.
+	 * In addition, the SigmaEstimator is not included in the VL53L0X
+	 * DeviceRangeStatus, this will be added in the PalRangeStatus.
+	 */
+
+	DeviceRangeStatusInternal = ((DeviceRangeStatus & 0x78) >> 3);
+
+	if (DeviceRangeStatusInternal == 0 ||
+		DeviceRangeStatusInternal == 5 ||
+		DeviceRangeStatusInternal == 7 ||
+		DeviceRangeStatusInternal == 12 ||
+		DeviceRangeStatusInternal == 13 ||
+		DeviceRangeStatusInternal == 14 ||
+		DeviceRangeStatusInternal == 15
+			) {
+		NoneFlag = 1;
+	} else {
+		NoneFlag = 0;
+	}
+
+	/* LastSignalRefMcps */
+	if (Status == VL53L0X_ERROR_NONE)
+		Status = VL53L0X_WrByte(Dev, 0xFF, 0x01);
+
+	if (Status == VL53L0X_ERROR_NONE)
+		Status = VL53L0X_RdWord(Dev,
+			VL53L0X_REG_RESULT_PEAK_SIGNAL_RATE_REF,
+			&tmpWord);
+
+	LastSignalRefMcps = VL53L0X_FIXPOINT97TOFIXPOINT1616(tmpWord);
+
+	if (Status == VL53L0X_ERROR_NONE)
+		Status = VL53L0X_WrByte(Dev, 0xFF, 0x00);
+
+	PALDevDataSet(Dev, LastSignalRefMcps, LastSignalRefMcps);
+
+	/*
+	 * Check if Sigma limit is enabled, if yes then do comparison with limit
+	 * value and put the result back into pPalRangeStatus.
+	 */
+	if (Status == VL53L0X_ERROR_NONE)
+		Status =  VL53L0X_GetLimitCheckEnable(Dev,
+			VL53L0X_CHECKENABLE_SIGMA_FINAL_RANGE,
+			&SigmaLimitCheckEnable);
+
+	if ((SigmaLimitCheckEnable != 0) && (Status == VL53L0X_ERROR_NONE)) {
+		/*
+		* compute the Sigma and check with limit
+		*/
+		Status = VL53L0X_calc_sigma_estimate(
+			Dev,
+			pRangingMeasurementData,
+			&SigmaEstimate,
+			&Dmax_mm);
+		if (Status == VL53L0X_ERROR_NONE)
+			pRangingMeasurementData->RangeDMaxMilliMeter = Dmax_mm;
+
+		if (Status == VL53L0X_ERROR_NONE) {
+			Status = VL53L0X_GetLimitCheckValue(Dev,
+				VL53L0X_CHECKENABLE_SIGMA_FINAL_RANGE,
+				&SigmaLimitValue);
+
+			if ((SigmaLimitValue > 0) &&
+				(SigmaEstimate > SigmaLimitValue))
+					/* Limit Fail */
+					SigmaLimitflag = 1;
+		}
+	}
+
+	/*
+	 * Check if Signal ref clip limit is enabled, if yes then do comparison
+	 * with limit value and put the result back into pPalRangeStatus.
+	 */
+	if (Status == VL53L0X_ERROR_NONE)
+		Status =  VL53L0X_GetLimitCheckEnable(Dev,
+				VL53L0X_CHECKENABLE_SIGNAL_REF_CLIP,
+				&SignalRefClipLimitCheckEnable);
+
+	if ((SignalRefClipLimitCheckEnable != 0) &&
+			(Status == VL53L0X_ERROR_NONE)) {
+
+		Status = VL53L0X_GetLimitCheckValue(Dev,
+				VL53L0X_CHECKENABLE_SIGNAL_REF_CLIP,
+				&SignalRefClipValue);
+
+		if ((SignalRefClipValue > 0) &&
+				(LastSignalRefMcps > SignalRefClipValue)) {
+			/* Limit Fail */
+			SignalRefClipflag = 1;
+		}
+	}
+
+	/*
+	 * Check if Signal ref clip limit is enabled, if yes then do comparison
+	 * with limit value and put the result back into pPalRangeStatus.
+	 * EffectiveSpadRtnCount has a format 8.8
+	 * If (Return signal rate < (1.5 x Xtalk x number of Spads)) : FAIL
+	 */
+	if (Status == VL53L0X_ERROR_NONE)
+		Status =  VL53L0X_GetLimitCheckEnable(Dev,
+				VL53L0X_CHECKENABLE_RANGE_IGNORE_THRESHOLD,
+				&RangeIgnoreThresholdLimitCheckEnable);
+
+	if ((RangeIgnoreThresholdLimitCheckEnable != 0) &&
+			(Status == VL53L0X_ERROR_NONE)) {
+
+		/* Compute the signal rate per spad */
+		if (EffectiveSpadRtnCount == 0) {
+			SignalRatePerSpad = 0;
+		} else {
+			SignalRatePerSpad = (FixPoint1616_t)((256 * SignalRate)
+				/ EffectiveSpadRtnCount);
+		}
+
+		Status = VL53L0X_GetLimitCheckValue(Dev,
+				VL53L0X_CHECKENABLE_RANGE_IGNORE_THRESHOLD,
+				&RangeIgnoreThresholdValue);
+
+		if ((RangeIgnoreThresholdValue > 0) &&
+			(SignalRatePerSpad < RangeIgnoreThresholdValue)) {
+			/* Limit Fail add 2^6 to range status */
+			RangeIgnoreThresholdflag = 1;
+		}
+	}
+
+	if (Status == VL53L0X_ERROR_NONE) {
+		if (NoneFlag == 1) {
+			*pPalRangeStatus = 255;	 /* NONE */
+		} else if (DeviceRangeStatusInternal == 1 ||
+					DeviceRangeStatusInternal == 2 ||
+					DeviceRangeStatusInternal == 3) {
+			*pPalRangeStatus = 5; /* HW fail */
+		} else if (DeviceRangeStatusInternal == 6 ||
+					DeviceRangeStatusInternal == 9) {
+			*pPalRangeStatus = 4;  /* Phase fail */
+		} else if (DeviceRangeStatusInternal == 8 ||
+					DeviceRangeStatusInternal == 10 ||
+					SignalRefClipflag == 1) {
+			*pPalRangeStatus = 3;  /* Min range */
+		} else if (DeviceRangeStatusInternal == 4 ||
+					RangeIgnoreThresholdflag == 1) {
+			*pPalRangeStatus = 2;  /* Signal Fail */
+		} else if (SigmaLimitflag == 1) {
+			*pPalRangeStatus = 1;  /* Sigma	 Fail */
+		} else {
+			*pPalRangeStatus = 0; /* Range Valid */
+		}
+	}
+
+	/* DMAX only relevant during range error */
+	if (*pPalRangeStatus == 0)
+		pRangingMeasurementData->RangeDMaxMilliMeter = 0;
+
+	/* fill the Limit Check Status */
+
+	Status =  VL53L0X_GetLimitCheckEnable(Dev,
+			VL53L0X_CHECKENABLE_SIGNAL_RATE_FINAL_RANGE,
+			&SignalRateFinalRangeLimitCheckEnable);
+
+	if (Status == VL53L0X_ERROR_NONE) {
+		if ((SigmaLimitCheckEnable == 0) || (SigmaLimitflag == 1))
+			Temp8 = 1;
+		else
+			Temp8 = 0;
+		VL53L0X_SETARRAYPARAMETERFIELD(Dev, LimitChecksStatus,
+				VL53L0X_CHECKENABLE_SIGMA_FINAL_RANGE, Temp8);
+
+		if ((DeviceRangeStatusInternal == 4) ||
+				(SignalRateFinalRangeLimitCheckEnable == 0))
+			Temp8 = 1;
+		else
+			Temp8 = 0;
+		VL53L0X_SETARRAYPARAMETERFIELD(Dev, LimitChecksStatus,
+				VL53L0X_CHECKENABLE_SIGNAL_RATE_FINAL_RANGE,
+				Temp8);
+
+		if ((SignalRefClipLimitCheckEnable == 0) ||
+					(SignalRefClipflag == 1))
+			Temp8 = 1;
+		else
+			Temp8 = 0;
+
+		VL53L0X_SETARRAYPARAMETERFIELD(Dev, LimitChecksStatus,
+				VL53L0X_CHECKENABLE_SIGNAL_REF_CLIP, Temp8);
+
+		if ((RangeIgnoreThresholdLimitCheckEnable == 0) ||
+				(RangeIgnoreThresholdflag == 1))
+			Temp8 = 1;
+		else
+			Temp8 = 0;
+
+		VL53L0X_SETARRAYPARAMETERFIELD(Dev, LimitChecksStatus,
+				VL53L0X_CHECKENABLE_RANGE_IGNORE_THRESHOLD,
+				Temp8);
+	}
+
+	LOG_FUNCTION_END(Status);
+	return Status;
+
+}
+
+/**************************************************api*************************************************/
+/**************************************************************************************************************/
+/**************************************************************************************************************/
+
+
+VL53L0X_Error VL53L0X_GetVersion(VL53L0X_Version_t *pVersion)
+{
+	VL53L0X_Error Status = VL53L0X_ERROR_NONE;
+	LOG_FUNCTION_START("");
+
+	pVersion->major = VL53L0X_IMPLEMENTATION_VER_MAJOR;
+	pVersion->minor = VL53L0X_IMPLEMENTATION_VER_MINOR;
+	pVersion->build = VL53L0X_IMPLEMENTATION_VER_SUB;
+
+	pVersion->revision = VL53L0X_IMPLEMENTATION_VER_REVISION;
+
+	LOG_FUNCTION_END(Status);
+	return Status;
+}
+
+VL53L0X_Error VL53L0X_GetPalSpecVersion(VL53L0X_Version_t *pPalSpecVersion)
+{
+	VL53L0X_Error Status = VL53L0X_ERROR_NONE;
+
+	LOG_FUNCTION_START("");
+
+	pPalSpecVersion->major = VL53L0X_SPECIFICATION_VER_MAJOR;
+	pPalSpecVersion->minor = VL53L0X_SPECIFICATION_VER_MINOR;
+	pPalSpecVersion->build = VL53L0X_SPECIFICATION_VER_SUB;
+
+	pPalSpecVersion->revision = VL53L0X_SPECIFICATION_VER_REVISION;
+
+	LOG_FUNCTION_END(Status);
+	return Status;
+}
+
+VL53L0X_Error VL53L0X_GetProductRevision(VL53L0X_DEV Dev,
+	uint8_t *pProductRevisionMajor, uint8_t *pProductRevisionMinor)
+{
+	VL53L0X_Error Status = VL53L0X_ERROR_NONE;
+	uint8_t revision_id;
+
+	LOG_FUNCTION_START("");
+
+	Status = VL53L0X_RdByte(Dev, VL53L0X_REG_IDENTIFICATION_REVISION_ID,
+		&revision_id);
+	*pProductRevisionMajor = 1;
+	*pProductRevisionMinor = (revision_id & 0xF0) >> 4;
+
+	LOG_FUNCTION_END(Status);
+	return Status;
+
+}
+
+VL53L0X_Error VL53L0X_GetDeviceInfo(VL53L0X_DEV Dev,
+	VL53L0X_DeviceInfo_t *pVL53L0X_DeviceInfo)
+{
+	VL53L0X_Error Status = VL53L0X_ERROR_NONE;
+	LOG_FUNCTION_START("");
+
+	Status = VL53L0X_get_device_info(Dev, pVL53L0X_DeviceInfo);
+
+	LOG_FUNCTION_END(Status);
+	return Status;
+}
+
+VL53L0X_Error VL53L0X_GetDeviceErrorStatus(VL53L0X_DEV Dev,
+	VL53L0X_DeviceError *pDeviceErrorStatus)
+{
+	VL53L0X_Error Status = VL53L0X_ERROR_NONE;
+	uint8_t RangeStatus;
+
+	LOG_FUNCTION_START("");
+
+	Status = VL53L0X_RdByte(Dev, VL53L0X_REG_RESULT_RANGE_STATUS,
+		&RangeStatus);
+
+	*pDeviceErrorStatus = (VL53L0X_DeviceError)((RangeStatus & 0x78) >> 3);
+
+	LOG_FUNCTION_END(Status);
+	return Status;
+}
+
+
+VL53L0X_Error VL53L0X_GetDeviceErrorString(VL53L0X_DeviceError ErrorCode,
+	char *pDeviceErrorString)
+{
+	VL53L0X_Error Status = VL53L0X_ERROR_NONE;
+
+	LOG_FUNCTION_START("");
+
+	Status = VL53L0X_get_device_error_string(ErrorCode, pDeviceErrorString);
+
+	LOG_FUNCTION_END(Status);
+	return Status;
+}
+
+VL53L0X_Error VL53L0X_GetRangeStatusString(uint8_t RangeStatus,
+	char *pRangeStatusString)
+{
+	VL53L0X_Error Status = VL53L0X_ERROR_NONE;
+	LOG_FUNCTION_START("");
+
+	Status = VL53L0X_get_range_status_string(RangeStatus,
+		pRangeStatusString);
+
+	LOG_FUNCTION_END(Status);
+	return Status;
+}
+
+VL53L0X_Error VL53L0X_GetPalErrorString(VL53L0X_Error PalErrorCode,
+	char *pPalErrorString)
+{
+	VL53L0X_Error Status = VL53L0X_ERROR_NONE;
+	LOG_FUNCTION_START("");
+
+	Status = VL53L0X_get_pal_error_string(PalErrorCode, pPalErrorString);
+
+	LOG_FUNCTION_END(Status);
+	return Status;
+}
+
+VL53L0X_Error VL53L0X_GetPalStateString(VL53L0X_State PalStateCode,
+	char *pPalStateString)
+{
+	VL53L0X_Error Status = VL53L0X_ERROR_NONE;
+	LOG_FUNCTION_START("");
+
+	Status = VL53L0X_get_pal_state_string(PalStateCode, pPalStateString);
+
+	LOG_FUNCTION_END(Status);
+	return Status;
+}
+
+VL53L0X_Error VL53L0X_GetPalState(VL53L0X_DEV Dev, VL53L0X_State *pPalState)
+{
+	VL53L0X_Error Status = VL53L0X_ERROR_NONE;
+	LOG_FUNCTION_START("");
+
+	*pPalState = PALDevDataGet(Dev, PalState);
+
+	LOG_FUNCTION_END(Status);
+	return Status;
+}
+
+VL53L0X_Error VL53L0X_SetPowerMode(VL53L0X_DEV Dev, VL53L0X_PowerModes PowerMode)
+{
+	VL53L0X_Error Status = VL53L0X_ERROR_NONE;
+	LOG_FUNCTION_START("");
+
+	/* Only level1 of Power mode exists */
+	if ((PowerMode != VL53L0X_POWERMODE_STANDBY_LEVEL1)
+		&& (PowerMode != VL53L0X_POWERMODE_IDLE_LEVEL1)) {
+		Status = VL53L0X_ERROR_MODE_NOT_SUPPORTED;
+	} else if (PowerMode == VL53L0X_POWERMODE_STANDBY_LEVEL1) {
+		/* set the standby level1 of power mode */
+		Status = VL53L0X_WrByte(Dev, 0x80, 0x00);
+		if (Status == VL53L0X_ERROR_NONE) {
+			/* Set PAL State to standby */
+			PALDevDataSet(Dev, PalState, VL53L0X_STATE_STANDBY);
+			PALDevDataSet(Dev, PowerMode,
+				VL53L0X_POWERMODE_STANDBY_LEVEL1);
+		}
+
+	} else {
+		/* VL53L0X_POWERMODE_IDLE_LEVEL1 */
+		Status = VL53L0X_WrByte(Dev, 0x80, 0x00);
+		if (Status == VL53L0X_ERROR_NONE)
+			Status = VL53L0X_StaticInit(Dev);
+
+		if (Status == VL53L0X_ERROR_NONE)
+			PALDevDataSet(Dev, PowerMode,
+				VL53L0X_POWERMODE_IDLE_LEVEL1);
+
+	}
+
+	LOG_FUNCTION_END(Status);
+	return Status;
+}
+
+VL53L0X_Error VL53L0X_GetPowerMode(VL53L0X_DEV Dev, VL53L0X_PowerModes *pPowerMode)
+{
+	VL53L0X_Error Status = VL53L0X_ERROR_NONE;
+	uint8_t Byte;
+	LOG_FUNCTION_START("");
+
+	/* Only level1 of Power mode exists */
+	Status = VL53L0X_RdByte(Dev, 0x80, &Byte);
+
+	if (Status == VL53L0X_ERROR_NONE) {
+		if (Byte == 1) {
+			PALDevDataSet(Dev, PowerMode,
+				VL53L0X_POWERMODE_IDLE_LEVEL1);
+		} else {
+			PALDevDataSet(Dev, PowerMode,
+				VL53L0X_POWERMODE_STANDBY_LEVEL1);
+		}
+	}
+
+	LOG_FUNCTION_END(Status);
+	return Status;
+}
+
+VL53L0X_Error VL53L0X_SetOffsetCalibrationDataMicroMeter(VL53L0X_DEV Dev,
+	int32_t OffsetCalibrationDataMicroMeter)
+{
+	VL53L0X_Error Status = VL53L0X_ERROR_NONE;
+	LOG_FUNCTION_START("");
+
+	Status = VL53L0X_set_offset_calibration_data_micro_meter(Dev,
+		OffsetCalibrationDataMicroMeter);
+
+	LOG_FUNCTION_END(Status);
+	return Status;
+}
+
+VL53L0X_Error VL53L0X_GetOffsetCalibrationDataMicroMeter(VL53L0X_DEV Dev,
+	int32_t *pOffsetCalibrationDataMicroMeter)
+{
+	VL53L0X_Error Status = VL53L0X_ERROR_NONE;
+	LOG_FUNCTION_START("");
+
+	Status = VL53L0X_get_offset_calibration_data_micro_meter(Dev,
+		pOffsetCalibrationDataMicroMeter);
+
+	LOG_FUNCTION_END(Status);
+	return Status;
+}
+
+VL53L0X_Error VL53L0X_SetLinearityCorrectiveGain(VL53L0X_DEV Dev,
+	int16_t LinearityCorrectiveGain)
+{
+	VL53L0X_Error Status = VL53L0X_ERROR_NONE;
+	LOG_FUNCTION_START("");
+
+	if ((LinearityCorrectiveGain < 0) || (LinearityCorrectiveGain > 1000))
+		Status = VL53L0X_ERROR_INVALID_PARAMS;
+	else {
+		PALDevDataSet(Dev, LinearityCorrectiveGain,
+			LinearityCorrectiveGain);
+
+		if (LinearityCorrectiveGain != 1000) {
+			/* Disable FW Xtalk */
+			Status = VL53L0X_WrWord(Dev,
+			VL53L0X_REG_CROSSTALK_COMPENSATION_PEAK_RATE_MCPS, 0);
+		}
+	}
+
+	LOG_FUNCTION_END(Status);
+	return Status;
+}
+
+VL53L0X_Error VL53L0X_GetLinearityCorrectiveGain(VL53L0X_DEV Dev,
+	uint16_t *pLinearityCorrectiveGain)
+{
+	VL53L0X_Error Status = VL53L0X_ERROR_NONE;
+	LOG_FUNCTION_START("");
+
+	*pLinearityCorrectiveGain = PALDevDataGet(Dev, LinearityCorrectiveGain);
+
+	LOG_FUNCTION_END(Status);
+	return Status;
+}
+
+VL53L0X_Error VL53L0X_SetGroupParamHold(VL53L0X_DEV Dev, uint8_t GroupParamHold)
+{
+	VL53L0X_Error Status = VL53L0X_ERROR_NOT_IMPLEMENTED;
+	LOG_FUNCTION_START("");
+
+	/* not implemented on VL53L0X */
+
+	LOG_FUNCTION_END(Status);
+	return Status;
+}
+
+VL53L0X_Error VL53L0X_GetUpperLimitMilliMeter(VL53L0X_DEV Dev,
+	uint16_t *pUpperLimitMilliMeter)
+{
+	VL53L0X_Error Status = VL53L0X_ERROR_NOT_IMPLEMENTED;
+	LOG_FUNCTION_START("");
+
+	/* not implemented on VL53L0X */
+
+	LOG_FUNCTION_END(Status);
+	return Status;
+}
+
+VL53L0X_Error VL53L0X_GetTotalSignalRate(VL53L0X_DEV Dev,
+	FixPoint1616_t *pTotalSignalRate)
+{
+	VL53L0X_Error Status = VL53L0X_ERROR_NONE;
+	VL53L0X_RangingMeasurementData_t LastRangeDataBuffer;
+
+	LOG_FUNCTION_START("");
+
+	LastRangeDataBuffer = PALDevDataGet(Dev, LastRangeMeasure);
+
+	Status = VL53L0X_get_total_signal_rate(
+		Dev, &LastRangeDataBuffer, pTotalSignalRate);
+
+	LOG_FUNCTION_END(Status);
+	return Status;
+}
+
+/* End Group PAL General Functions */
+
+/* Group PAL Init Functions */
+VL53L0X_Error VL53L0X_SetDeviceAddress(VL53L0X_DEV Dev, uint8_t DeviceAddress)
+{
+	VL53L0X_Error Status = VL53L0X_ERROR_NONE;
+	LOG_FUNCTION_START("");
+
+	Status = VL53L0X_WrByte(Dev, VL53L0X_REG_I2C_SLAVE_DEVICE_ADDRESS,
+		DeviceAddress / 2);
+
+	LOG_FUNCTION_END(Status);
+	return Status;
+}
+
+#define USE_I2C_2V8
+
+VL53L0X_Error VL53L0X_DataInit(VL53L0X_DEV Dev)
+{
+	uint8_t b = 0;
+	VL53L0X_Error Status = VL53L0X_ERROR_NONE;
+	VL53L0X_DeviceParameters_t CurrentParameters;
+	int i;
+	uint8_t StopVariable;
+
+	LOG_FUNCTION_START("");
+
+	/* by default the I2C is running at 1V8 if you want to change it you
+	 * need to include this define at compilation level. */
+#ifdef USE_I2C_2V8
+	Status = VL53L0X_UpdateByte(Dev,
+		VL53L0X_REG_VHV_CONFIG_PAD_SCL_SDA__EXTSUP_HV,
+		0xFE,
+		0x01);
+#endif
+
+	/* Set I2C standard mode */
+	if (Status == VL53L0X_ERROR_NONE)
+		Status = VL53L0X_WrByte(Dev, 0x88, 0x00);
+
+	/* read WHO_AM_I */
+	
+	Status = VL53L0X_RdByte(Dev, 0xC0, &b);
+	   
+	/* read WHO_AM_I */
+
+	VL53L0X_SETDEVICESPECIFICPARAMETER(Dev, ReadDataFromDeviceDone, 0);
+
+#ifdef USE_IQC_STATION
+	if (Status == VL53L0X_ERROR_NONE)
+		Status = VL53L0X_apply_offset_adjustment(Dev);
+#endif
+
+	/* Default value is 1000 for Linearity Corrective Gain */
+	PALDevDataSet(Dev, LinearityCorrectiveGain, 1000);
+
+	/* Dmax default Parameter */
+	PALDevDataSet(Dev, DmaxCalRangeMilliMeter, 400);
+	PALDevDataSet(Dev, DmaxCalSignalRateRtnMegaCps,
+		(FixPoint1616_t)((0x00016B85))); /* 1.42 No Cover Glass*/
+
+	/* Set Default static parameters
+	 *set first temporary values 9.44MHz * 65536 = 618660 */
+	VL53L0X_SETDEVICESPECIFICPARAMETER(Dev, OscFrequencyMHz, 618660);
+
+	/* Set Default XTalkCompensationRateMegaCps to 0  */
+	VL53L0X_SETPARAMETERFIELD(Dev, XTalkCompensationRateMegaCps, 0);
+
+	/* Get default parameters */
+	Status = VL53L0X_GetDeviceParameters(Dev, &CurrentParameters);
+
+	if (Status == VL53L0X_ERROR_NONE) {
+		/* initialize PAL values */
+		CurrentParameters.DeviceMode = VL53L0X_DEVICEMODE_SINGLE_RANGING;
+		CurrentParameters.HistogramMode = VL53L0X_HISTOGRAMMODE_DISABLED;
+		PALDevDataSet(Dev, CurrentParameters, CurrentParameters);
+	}
+
+	/* Sigma estimator variable */
+	PALDevDataSet(Dev, SigmaEstRefArray, 100);
+	PALDevDataSet(Dev, SigmaEstEffPulseWidth, 900);
+	PALDevDataSet(Dev, SigmaEstEffAmbWidth, 500);
+	PALDevDataSet(Dev, targetRefRate, 0x0A00); /* 20 MCPS in 9:7 format */
+
+	/* Use internal default settings */
+	PALDevDataSet(Dev, UseInternalTuningSettings, 1);
+
+	Status |= VL53L0X_WrByte(Dev, 0x80, 0x01);
+	Status |= VL53L0X_WrByte(Dev, 0xFF, 0x01);
+	Status |= VL53L0X_WrByte(Dev, 0x00, 0x00);
+	Status |= VL53L0X_RdByte(Dev, 0x91, &StopVariable);
+	PALDevDataSet(Dev, StopVariable, StopVariable);
+	Status |= VL53L0X_WrByte(Dev, 0x00, 0x01);
+	Status |= VL53L0X_WrByte(Dev, 0xFF, 0x00);
+	Status |= VL53L0X_WrByte(Dev, 0x80, 0x00);
+
+	/* Enable all check */
+	for (i = 0; i < VL53L0X_CHECKENABLE_NUMBER_OF_CHECKS; i++) {
+		if (Status == VL53L0X_ERROR_NONE)
+			Status |= VL53L0X_SetLimitCheckEnable(Dev, i, 1);
+		else
+			break;
+
+	}
+
+	/* Disable the following checks */
+	if (Status == VL53L0X_ERROR_NONE)
+		Status = VL53L0X_SetLimitCheckEnable(Dev,
+			VL53L0X_CHECKENABLE_SIGNAL_REF_CLIP, 0);
+
+	if (Status == VL53L0X_ERROR_NONE)
+		Status = VL53L0X_SetLimitCheckEnable(Dev,
+			VL53L0X_CHECKENABLE_RANGE_IGNORE_THRESHOLD, 0);
+
+	if (Status == VL53L0X_ERROR_NONE)
+		Status = VL53L0X_SetLimitCheckEnable(Dev,
+			VL53L0X_CHECKENABLE_SIGNAL_RATE_MSRC, 0);
+
+	if (Status == VL53L0X_ERROR_NONE)
+		Status = VL53L0X_SetLimitCheckEnable(Dev,
+			VL53L0X_CHECKENABLE_SIGNAL_RATE_PRE_RANGE, 0);
+
+	/* Limit default values */
+	if (Status == VL53L0X_ERROR_NONE) {
+		Status = VL53L0X_SetLimitCheckValue(Dev,
+			VL53L0X_CHECKENABLE_SIGMA_FINAL_RANGE,
+				(FixPoint1616_t)(18 * 65536));
+	}
+	if (Status == VL53L0X_ERROR_NONE) {
+		Status = VL53L0X_SetLimitCheckValue(Dev,
+			VL53L0X_CHECKENABLE_SIGNAL_RATE_FINAL_RANGE,
+				(FixPoint1616_t)(25 * 65536 / 100));
+				/* 0.25 * 65536 */
+	}
+
+	if (Status == VL53L0X_ERROR_NONE) {
+		Status = VL53L0X_SetLimitCheckValue(Dev,
+			VL53L0X_CHECKENABLE_SIGNAL_REF_CLIP,
+				(FixPoint1616_t)(35 * 65536));
+	}
+
+	if (Status == VL53L0X_ERROR_NONE) {
+		Status = VL53L0X_SetLimitCheckValue(Dev,
+			VL53L0X_CHECKENABLE_RANGE_IGNORE_THRESHOLD,
+				(FixPoint1616_t)(0 * 65536));
+	}
+
+	if (Status == VL53L0X_ERROR_NONE) {
+
+		PALDevDataSet(Dev, SequenceConfig, 0xFF);
+		Status = VL53L0X_WrByte(Dev, VL53L0X_REG_SYSTEM_SEQUENCE_CONFIG,
+			0xFF);
+
+		/* Set PAL state to tell that we are waiting for call to
+		 * VL53L0X_StaticInit */
+		PALDevDataSet(Dev, PalState, VL53L0X_STATE_WAIT_STATICINIT);
+	}
+
+	if (Status == VL53L0X_ERROR_NONE)
+		VL53L0X_SETDEVICESPECIFICPARAMETER(Dev, RefSpadsInitialised, 0);
+
+	LOG_FUNCTION_END(Status);
+	return Status;
+}
+
+VL53L0X_Error VL53L0X_SetTuningSettingBuffer(VL53L0X_DEV Dev,
+	uint8_t *pTuningSettingBuffer, uint8_t UseInternalTuningSettings)
+{
+	VL53L0X_Error Status = VL53L0X_ERROR_NONE;
+
+	LOG_FUNCTION_START("");
+
+	if (UseInternalTuningSettings == 1) {
+		/* Force use internal settings */
+		PALDevDataSet(Dev, UseInternalTuningSettings, 1);
+	} else {
+
+		/* check that the first byte is not 0 */
+		if (*pTuningSettingBuffer != 0) {
+			PALDevDataSet(Dev, pTuningSettingsPointer,
+				pTuningSettingBuffer);
+			PALDevDataSet(Dev, UseInternalTuningSettings, 0);
+
+		} else {
+			Status = VL53L0X_ERROR_INVALID_PARAMS;
+		}
+	}
+
+	LOG_FUNCTION_END(Status);
+	return Status;
+}
+
+VL53L0X_Error VL53L0X_GetTuningSettingBuffer(VL53L0X_DEV Dev,
+	uint8_t **ppTuningSettingBuffer, uint8_t *pUseInternalTuningSettings)
+{
+	VL53L0X_Error Status = VL53L0X_ERROR_NONE;
+
+	LOG_FUNCTION_START("");
+
+	*ppTuningSettingBuffer = PALDevDataGet(Dev, pTuningSettingsPointer);
+	*pUseInternalTuningSettings = PALDevDataGet(Dev,
+		UseInternalTuningSettings);
+
+	LOG_FUNCTION_END(Status);
+	return Status;
+}
+
+VL53L0X_Error VL53L0X_StaticInit(VL53L0X_DEV Dev)
+{
+	VL53L0X_Error Status = VL53L0X_ERROR_NONE;
+	VL53L0X_DeviceParameters_t CurrentParameters = {0};
+	uint8_t *pTuningSettingBuffer;
+	uint16_t tempword = 0;
+	uint8_t tempbyte = 0;
+	uint8_t UseInternalTuningSettings = 0;
+	uint32_t count = 0;
+	uint8_t isApertureSpads = 0;
+	uint32_t refSpadCount = 0;
+	uint8_t ApertureSpads = 0;
+	uint8_t vcselPulsePeriodPCLK;
+	FixPoint1616_t seqTimeoutMilliSecs;
+
+	LOG_FUNCTION_START("");
+
+	Status = VL53L0X_get_info_from_device(Dev, 1);
+
+	/* set the ref spad from NVM */
+	count	= (uint32_t)VL53L0X_GETDEVICESPECIFICPARAMETER(Dev,
+		ReferenceSpadCount);
+	ApertureSpads = VL53L0X_GETDEVICESPECIFICPARAMETER(Dev,
+		ReferenceSpadType);
+
+	/* NVM value invalid */
+	if ((ApertureSpads > 1) ||
+		((ApertureSpads == 1) && (count > 32)) ||
+		((ApertureSpads == 0) && (count > 12)))
+		{
+			Status = VL53L0X_perform_ref_spad_management(Dev, &refSpadCount,
+			&isApertureSpads);
+		}
+		
+	else
+	{
+		Status = VL53L0X_set_reference_spads(Dev, count, ApertureSpads);
+	}
+		
+	/* Initialize tuning settings buffer to prevent compiler warning. */
+	pTuningSettingBuffer = DefaultTuningSettings;
+
+	if (Status == VL53L0X_ERROR_NONE) {
+		UseInternalTuningSettings = PALDevDataGet(Dev,
+			UseInternalTuningSettings);
+
+		if (UseInternalTuningSettings == 0)
+			pTuningSettingBuffer = PALDevDataGet(Dev,
+				pTuningSettingsPointer);
+		else
+			pTuningSettingBuffer = DefaultTuningSettings;
+
+	}
+
+	if (Status == VL53L0X_ERROR_NONE)
+		Status = VL53L0X_load_tuning_settings(Dev, pTuningSettingBuffer);
+
+	/* Set interrupt config to new sample ready */
+	if (Status == VL53L0X_ERROR_NONE) {
+		Status = VL53L0X_SetGpioConfig(Dev, 0, 0,
+		VL53L0X_REG_SYSTEM_INTERRUPT_GPIO_NEW_SAMPLE_READY,
+		VL53L0X_INTERRUPTPOLARITY_LOW);
+	}
+
+	if (Status == VL53L0X_ERROR_NONE) {
+		Status = VL53L0X_WrByte(Dev, 0xFF, 0x01);
+		Status |= VL53L0X_RdWord(Dev, 0x84, &tempword);
+		Status |= VL53L0X_WrByte(Dev, 0xFF, 0x00);
+	}
+
+	if (Status == VL53L0X_ERROR_NONE) {
+		VL53L0X_SETDEVICESPECIFICPARAMETER(Dev, OscFrequencyMHz,
+			VL53L0X_FIXPOINT412TOFIXPOINT1616(tempword));
+	}
+	/* After static init, some device parameters may be changed,
+	 * so update them */
+	if (Status == VL53L0X_ERROR_NONE)
+		Status = VL53L0X_GetDeviceParameters(Dev, &CurrentParameters);
+
+
+	if (Status == VL53L0X_ERROR_NONE) {
+		Status = VL53L0X_GetFractionEnable(Dev, &tempbyte);
+		if (Status == VL53L0X_ERROR_NONE)
+			PALDevDataSet(Dev, RangeFractionalEnable, tempbyte);
+
+	}
+
+	if (Status == VL53L0X_ERROR_NONE)
+		PALDevDataSet(Dev, CurrentParameters, CurrentParameters);
+
+	/* read the sequence config and save it */
+	if (Status == VL53L0X_ERROR_NONE) {
+		Status = VL53L0X_RdByte(Dev,
+		VL53L0X_REG_SYSTEM_SEQUENCE_CONFIG, &tempbyte);
+		if (Status == VL53L0X_ERROR_NONE)
+			PALDevDataSet(Dev, SequenceConfig, tempbyte);
+
+	}
+
+	/* Disable MSRC and TCC by default */
+	if (Status == VL53L0X_ERROR_NONE)
+		Status = VL53L0X_SetSequenceStepEnable(Dev,
+					VL53L0X_SEQUENCESTEP_TCC, 0);
+
+
+	if (Status == VL53L0X_ERROR_NONE)
+		Status = VL53L0X_SetSequenceStepEnable(Dev,
+		VL53L0X_SEQUENCESTEP_MSRC, 0);
+
+
+	/* Set PAL State to standby */
+	if (Status == VL53L0X_ERROR_NONE)
+		PALDevDataSet(Dev, PalState, VL53L0X_STATE_IDLE);
+
+
+
+	/* Store pre-range vcsel period */
+	if (Status == VL53L0X_ERROR_NONE) {
+		Status = VL53L0X_GetVcselPulsePeriod(
+			Dev,
+			VL53L0X_VCSEL_PERIOD_PRE_RANGE,
+			&vcselPulsePeriodPCLK);
+	}
+
+	if (Status == VL53L0X_ERROR_NONE) {
+			VL53L0X_SETDEVICESPECIFICPARAMETER(
+				Dev,
+				PreRangeVcselPulsePeriod,
+				vcselPulsePeriodPCLK);
+	}
+	/* Store final-range vcsel period */
+	if (Status == VL53L0X_ERROR_NONE) {
+		Status = VL53L0X_GetVcselPulsePeriod(
+			Dev,
+			VL53L0X_VCSEL_PERIOD_FINAL_RANGE,
+			&vcselPulsePeriodPCLK);
+	}
+
+	if (Status == VL53L0X_ERROR_NONE) {
+			VL53L0X_SETDEVICESPECIFICPARAMETER(
+				Dev,
+				FinalRangeVcselPulsePeriod,
+				vcselPulsePeriodPCLK);
+	}
+
+	/* Store pre-range timeout */
+	if (Status == VL53L0X_ERROR_NONE) {
+		Status = VL53L0X_GetSequenceStepTimeout(
+			Dev,
+			VL53L0X_SEQUENCESTEP_PRE_RANGE,
+			&seqTimeoutMilliSecs);
+	}
+	if (Status == VL53L0X_ERROR_NONE) {
+		VL53L0X_SETDEVICESPECIFICPARAMETER(
+			Dev,
+			PreRangeTimeoutMicroSecs,
+			seqTimeoutMilliSecs);
+	}
+
+	/* Store final-range timeout */
+	if (Status == VL53L0X_ERROR_NONE) {
+		Status = VL53L0X_GetSequenceStepTimeout(
+			Dev,
+			VL53L0X_SEQUENCESTEP_FINAL_RANGE,
+			&seqTimeoutMilliSecs);
+	}
+	if (Status == VL53L0X_ERROR_NONE) {
+		VL53L0X_SETDEVICESPECIFICPARAMETER(
+			Dev,
+			FinalRangeTimeoutMicroSecs,
+			seqTimeoutMilliSecs);
+	}
+	LOG_FUNCTION_END(Status);
+	return Status;
+}
+
+VL53L0X_Error VL53L0X_WaitDeviceBooted(VL53L0X_DEV Dev)
+{
+	VL53L0X_Error Status = VL53L0X_ERROR_NOT_IMPLEMENTED;
+	LOG_FUNCTION_START("");
+
+	/* not implemented on VL53L0X */
+
+	LOG_FUNCTION_END(Status);
+	return Status;
+}
+
+VL53L0X_Error VL53L0X_ResetDevice(VL53L0X_DEV Dev)
+{
+	VL53L0X_Error Status = VL53L0X_ERROR_NONE;
+	uint8_t Byte;
+	LOG_FUNCTION_START("");
+
+	/* Set reset bit */
+	Status = VL53L0X_WrByte(Dev, VL53L0X_REG_SOFT_RESET_GO2_SOFT_RESET_N,
+		0x00);
+
+	/* Wait for some time */
+	if (Status == VL53L0X_ERROR_NONE) {
+		do {
+			Status = VL53L0X_RdByte(Dev,
+			VL53L0X_REG_IDENTIFICATION_MODEL_ID, &Byte);
+		} while (Byte != 0x00);
+	}
+
+	/* Release reset */
+	Status = VL53L0X_WrByte(Dev, VL53L0X_REG_SOFT_RESET_GO2_SOFT_RESET_N,
+		0x01);
+
+	/* Wait until correct boot-up of the device */
+	if (Status == VL53L0X_ERROR_NONE) {
+		do {
+			Status = VL53L0X_RdByte(Dev,
+			VL53L0X_REG_IDENTIFICATION_MODEL_ID, &Byte);
+		} while (Byte == 0x00);
+	}
+
+	/* Set PAL State to VL53L0X_STATE_POWERDOWN */
+	if (Status == VL53L0X_ERROR_NONE)
+		PALDevDataSet(Dev, PalState, VL53L0X_STATE_POWERDOWN);
+
+
+	LOG_FUNCTION_END(Status);
+	return Status;
+}
+/* End Group PAL Init Functions */
+
+/* Group PAL Parameters Functions */
+VL53L0X_Error VL53L0X_SetDeviceParameters(VL53L0X_DEV Dev,
+	const VL53L0X_DeviceParameters_t *pDeviceParameters)
+{
+	VL53L0X_Error Status = VL53L0X_ERROR_NONE;
+	int i;
+	LOG_FUNCTION_START("");
+	Status = VL53L0X_SetDeviceMode(Dev, pDeviceParameters->DeviceMode);
+
+	if (Status == VL53L0X_ERROR_NONE)
+		Status = VL53L0X_SetInterMeasurementPeriodMilliSeconds(Dev,
+			pDeviceParameters->InterMeasurementPeriodMilliSeconds);
+
+
+	if (Status == VL53L0X_ERROR_NONE)
+		Status = VL53L0X_SetXTalkCompensationRateMegaCps(Dev,
+			pDeviceParameters->XTalkCompensationRateMegaCps);
+
+
+	if (Status == VL53L0X_ERROR_NONE)
+		Status = VL53L0X_SetOffsetCalibrationDataMicroMeter(Dev,
+			pDeviceParameters->RangeOffsetMicroMeters);
+
+
+	for (i = 0; i < VL53L0X_CHECKENABLE_NUMBER_OF_CHECKS; i++) {
+		if (Status == VL53L0X_ERROR_NONE)
+			Status |= VL53L0X_SetLimitCheckEnable(Dev, i,
+				pDeviceParameters->LimitChecksEnable[i]);
+		else
+			break;
+
+		if (Status == VL53L0X_ERROR_NONE)
+			Status |= VL53L0X_SetLimitCheckValue(Dev, i,
+				pDeviceParameters->LimitChecksValue[i]);
+		else
+			break;
+
+	}
+
+	if (Status == VL53L0X_ERROR_NONE)
+		Status = VL53L0X_SetWrapAroundCheckEnable(Dev,
+			pDeviceParameters->WrapAroundCheckEnable);
+
+	if (Status == VL53L0X_ERROR_NONE)
+		Status = VL53L0X_SetMeasurementTimingBudgetMicroSeconds(Dev,
+			pDeviceParameters->MeasurementTimingBudgetMicroSeconds);
+
+
+	LOG_FUNCTION_END(Status);
+	return Status;
+}
+
+VL53L0X_Error VL53L0X_GetDeviceParameters(VL53L0X_DEV Dev,
+	VL53L0X_DeviceParameters_t *pDeviceParameters)
+{
+	VL53L0X_Error Status = VL53L0X_ERROR_NONE;
+	int i;
+
+	LOG_FUNCTION_START("");
+
+	Status = VL53L0X_GetDeviceMode(Dev, &(pDeviceParameters->DeviceMode));
+
+	if (Status == VL53L0X_ERROR_NONE)
+		Status = VL53L0X_GetInterMeasurementPeriodMilliSeconds(Dev,
+		&(pDeviceParameters->InterMeasurementPeriodMilliSeconds));
+
+
+	if (Status == VL53L0X_ERROR_NONE)
+		pDeviceParameters->XTalkCompensationEnable = 0;
+
+	if (Status == VL53L0X_ERROR_NONE)
+		Status = VL53L0X_GetXTalkCompensationRateMegaCps(Dev,
+			&(pDeviceParameters->XTalkCompensationRateMegaCps));
+
+
+	if (Status == VL53L0X_ERROR_NONE)
+		Status = VL53L0X_GetOffsetCalibrationDataMicroMeter(Dev,
+			&(pDeviceParameters->RangeOffsetMicroMeters));
+
+
+	if (Status == VL53L0X_ERROR_NONE) {
+		for (i = 0; i < VL53L0X_CHECKENABLE_NUMBER_OF_CHECKS; i++) {
+			/* get first the values, then the enables.
+			 * VL53L0X_GetLimitCheckValue will modify the enable
+			 * flags
+			 */
+			if (Status == VL53L0X_ERROR_NONE) {
+				Status |= VL53L0X_GetLimitCheckValue(Dev, i,
+				&(pDeviceParameters->LimitChecksValue[i]));
+			} else {
+				break;
+			}
+			if (Status == VL53L0X_ERROR_NONE) {
+				Status |= VL53L0X_GetLimitCheckEnable(Dev, i,
+				&(pDeviceParameters->LimitChecksEnable[i]));
+			} else {
+				break;
+			}
+		}
+	}
+
+	if (Status == VL53L0X_ERROR_NONE) {
+		Status = VL53L0X_GetWrapAroundCheckEnable(Dev,
+			&(pDeviceParameters->WrapAroundCheckEnable));
+	}
+
+	/* Need to be done at the end as it uses VCSELPulsePeriod */
+	if (Status == VL53L0X_ERROR_NONE) {
+		Status = VL53L0X_GetMeasurementTimingBudgetMicroSeconds(Dev,
+		&(pDeviceParameters->MeasurementTimingBudgetMicroSeconds));
+	}
+
+	LOG_FUNCTION_END(Status);
+	return Status;
+}
+
+VL53L0X_Error VL53L0X_SetDeviceMode(VL53L0X_DEV Dev, VL53L0X_DeviceModes DeviceMode)
+{
+	VL53L0X_Error Status = VL53L0X_ERROR_NONE;
+
+	LOG_FUNCTION_START("%d", (int)DeviceMode);
+
+	switch (DeviceMode) {
+	case VL53L0X_DEVICEMODE_SINGLE_RANGING:
+	case VL53L0X_DEVICEMODE_CONTINUOUS_RANGING:
+	case VL53L0X_DEVICEMODE_CONTINUOUS_TIMED_RANGING:
+	case VL53L0X_DEVICEMODE_GPIO_DRIVE:
+	case VL53L0X_DEVICEMODE_GPIO_OSC:
+		/* Supported modes */
+		VL53L0X_SETPARAMETERFIELD(Dev, DeviceMode, DeviceMode);
+		break;
+	default:
+		/* Unsupported mode */
+		Status = VL53L0X_ERROR_MODE_NOT_SUPPORTED;
+	}
+
+	LOG_FUNCTION_END(Status);
+	return Status;
+}
+
+VL53L0X_Error VL53L0X_GetDeviceMode(VL53L0X_DEV Dev,
+	VL53L0X_DeviceModes *pDeviceMode)
+{
+	VL53L0X_Error Status = VL53L0X_ERROR_NONE;
+	LOG_FUNCTION_START("");
+
+	VL53L0X_GETPARAMETERFIELD(Dev, DeviceMode, *pDeviceMode);
+
+	LOG_FUNCTION_END(Status);
+	return Status;
+}
+
+VL53L0X_Error VL53L0X_SetRangeFractionEnable(VL53L0X_DEV Dev,	uint8_t Enable)
+{
+	VL53L0X_Error Status = VL53L0X_ERROR_NONE;
+
+	LOG_FUNCTION_START("%d", (int)Enable);
+
+	Status = VL53L0X_WrByte(Dev, VL53L0X_REG_SYSTEM_RANGE_CONFIG, Enable);
+
+	if (Status == VL53L0X_ERROR_NONE)
+		PALDevDataSet(Dev, RangeFractionalEnable, Enable);
+
+	LOG_FUNCTION_END(Status);
+	return Status;
+}
+
+VL53L0X_Error VL53L0X_GetFractionEnable(VL53L0X_DEV Dev, uint8_t *pEnabled)
+{
+	VL53L0X_Error Status = VL53L0X_ERROR_NONE;
+	LOG_FUNCTION_START("");
+
+	Status = VL53L0X_RdByte(Dev, VL53L0X_REG_SYSTEM_RANGE_CONFIG, pEnabled);
+
+	if (Status == VL53L0X_ERROR_NONE)
+		*pEnabled = (*pEnabled & 1);
+
+	LOG_FUNCTION_END(Status);
+	return Status;
+}
+
+VL53L0X_Error VL53L0X_SetHistogramMode(VL53L0X_DEV Dev,
+	VL53L0X_HistogramModes HistogramMode)
+{
+	VL53L0X_Error Status = VL53L0X_ERROR_NOT_IMPLEMENTED;
+	LOG_FUNCTION_START("");
+
+	/* not implemented on VL53L0X */
+
+	LOG_FUNCTION_END(Status);
+	return Status;
+}
+
+VL53L0X_Error VL53L0X_GetHistogramMode(VL53L0X_DEV Dev,
+	VL53L0X_HistogramModes *pHistogramMode)
+{
+	VL53L0X_Error Status = VL53L0X_ERROR_NOT_IMPLEMENTED;
+	LOG_FUNCTION_START("");
+
+	/* not implemented on VL53L0X */
+
+	LOG_FUNCTION_END(Status);
+	return Status;
+}
+
+VL53L0X_Error VL53L0X_SetMeasurementTimingBudgetMicroSeconds(VL53L0X_DEV Dev,
+	uint32_t MeasurementTimingBudgetMicroSeconds)
+{
+	VL53L0X_Error Status = VL53L0X_ERROR_NONE;
+	LOG_FUNCTION_START("");
+
+	Status = VL53L0X_set_measurement_timing_budget_micro_seconds(Dev,
+		MeasurementTimingBudgetMicroSeconds);
+
+	LOG_FUNCTION_END(Status);
+
+	return Status;
+}
+
+VL53L0X_Error VL53L0X_GetMeasurementTimingBudgetMicroSeconds(VL53L0X_DEV Dev,
+	uint32_t *pMeasurementTimingBudgetMicroSeconds)
+{
+	VL53L0X_Error Status = VL53L0X_ERROR_NONE;
+	LOG_FUNCTION_START("");
+
+	Status = VL53L0X_get_measurement_timing_budget_micro_seconds(Dev,
+		pMeasurementTimingBudgetMicroSeconds);
+
+	LOG_FUNCTION_END(Status);
+	return Status;
+}
+
+VL53L0X_Error VL53L0X_SetVcselPulsePeriod(VL53L0X_DEV Dev,
+	VL53L0X_VcselPeriod VcselPeriodType, uint8_t VCSELPulsePeriodPCLK)
+{
+	VL53L0X_Error Status = VL53L0X_ERROR_NONE;
+	LOG_FUNCTION_START("");
+
+	Status = VL53L0X_set_vcsel_pulse_period(Dev, VcselPeriodType,
+		VCSELPulsePeriodPCLK);
+
+	LOG_FUNCTION_END(Status);
+	return Status;
+}
+
+VL53L0X_Error VL53L0X_GetVcselPulsePeriod(VL53L0X_DEV Dev,
+	VL53L0X_VcselPeriod VcselPeriodType, uint8_t *pVCSELPulsePeriodPCLK)
+{
+	VL53L0X_Error Status = VL53L0X_ERROR_NONE;
+	LOG_FUNCTION_START("");
+
+	Status = VL53L0X_get_vcsel_pulse_period(Dev, VcselPeriodType,
+		pVCSELPulsePeriodPCLK);
+
+	LOG_FUNCTION_END(Status);
+	return Status;
+}
+
+VL53L0X_Error VL53L0X_SetSequenceStepEnable(VL53L0X_DEV Dev,
+	VL53L0X_SequenceStepId SequenceStepId, uint8_t SequenceStepEnabled)
+{
+	VL53L0X_Error Status = VL53L0X_ERROR_NONE;
+	uint8_t SequenceConfig = 0;
+	uint8_t SequenceConfigNew = 0;
+	uint32_t MeasurementTimingBudgetMicroSeconds;
+	LOG_FUNCTION_START("");
+
+	Status = VL53L0X_RdByte(Dev, VL53L0X_REG_SYSTEM_SEQUENCE_CONFIG,
+		&SequenceConfig);
+
+	SequenceConfigNew = SequenceConfig;
+
+	if (Status == VL53L0X_ERROR_NONE) {
+		if (SequenceStepEnabled == 1) {
+
+			/* Enable requested sequence step
+			 */
+			switch (SequenceStepId) {
+			case VL53L0X_SEQUENCESTEP_TCC:
+				SequenceConfigNew |= 0x10;
+				break;
+			case VL53L0X_SEQUENCESTEP_DSS:
+				SequenceConfigNew |= 0x28;
+				break;
+			case VL53L0X_SEQUENCESTEP_MSRC:
+				SequenceConfigNew |= 0x04;
+				break;
+			case VL53L0X_SEQUENCESTEP_PRE_RANGE:
+				SequenceConfigNew |= 0x40;
+				break;
+			case VL53L0X_SEQUENCESTEP_FINAL_RANGE:
+				SequenceConfigNew |= 0x80;
+				break;
+			default:
+				Status = VL53L0X_ERROR_INVALID_PARAMS;
+			}
+		} else {
+			/* Disable requested sequence step
+			 */
+			switch (SequenceStepId) {
+			case VL53L0X_SEQUENCESTEP_TCC:
+				SequenceConfigNew &= 0xef;
+				break;
+			case VL53L0X_SEQUENCESTEP_DSS:
+				SequenceConfigNew &= 0xd7;
+				break;
+			case VL53L0X_SEQUENCESTEP_MSRC:
+				SequenceConfigNew &= 0xfb;
+				break;
+			case VL53L0X_SEQUENCESTEP_PRE_RANGE:
+				SequenceConfigNew &= 0xbf;
+				break;
+			case VL53L0X_SEQUENCESTEP_FINAL_RANGE:
+				SequenceConfigNew &= 0x7f;
+				break;
+			default:
+				Status = VL53L0X_ERROR_INVALID_PARAMS;
+			}
+		}
+	}
+
+	if (SequenceConfigNew != SequenceConfig) {
+		/* Apply New Setting */
+		if (Status == VL53L0X_ERROR_NONE) {
+			Status = VL53L0X_WrByte(Dev,
+			VL53L0X_REG_SYSTEM_SEQUENCE_CONFIG, SequenceConfigNew);
+		}
+		if (Status == VL53L0X_ERROR_NONE)
+			PALDevDataSet(Dev, SequenceConfig, SequenceConfigNew);
+
+
+		/* Recalculate timing budget */
+		if (Status == VL53L0X_ERROR_NONE) {
+			VL53L0X_GETPARAMETERFIELD(Dev,
+				MeasurementTimingBudgetMicroSeconds,
+				MeasurementTimingBudgetMicroSeconds);
+
+			VL53L0X_SetMeasurementTimingBudgetMicroSeconds(Dev,
+				MeasurementTimingBudgetMicroSeconds);
+		}
+	}
+
+	LOG_FUNCTION_END(Status);
+
+	return Status;
+}
+
+VL53L0X_Error sequence_step_enabled(VL53L0X_DEV Dev,
+	VL53L0X_SequenceStepId SequenceStepId, uint8_t SequenceConfig,
+	uint8_t *pSequenceStepEnabled)
+{
+	VL53L0X_Error Status = VL53L0X_ERROR_NONE;
+	*pSequenceStepEnabled = 0;
+	LOG_FUNCTION_START("");
+
+	switch (SequenceStepId) {
+	case VL53L0X_SEQUENCESTEP_TCC:
+		*pSequenceStepEnabled = (SequenceConfig & 0x10) >> 4;
+		break;
+	case VL53L0X_SEQUENCESTEP_DSS:
+		*pSequenceStepEnabled = (SequenceConfig & 0x08) >> 3;
+		break;
+	case VL53L0X_SEQUENCESTEP_MSRC:
+		*pSequenceStepEnabled = (SequenceConfig & 0x04) >> 2;
+		break;
+	case VL53L0X_SEQUENCESTEP_PRE_RANGE:
+		*pSequenceStepEnabled = (SequenceConfig & 0x40) >> 6;
+		break;
+	case VL53L0X_SEQUENCESTEP_FINAL_RANGE:
+		*pSequenceStepEnabled = (SequenceConfig & 0x80) >> 7;
+		break;
+	default:
+		Status = VL53L0X_ERROR_INVALID_PARAMS;
+	}
+
+	LOG_FUNCTION_END(Status);
+	return Status;
+}
+
+VL53L0X_Error VL53L0X_GetSequenceStepEnable(VL53L0X_DEV Dev,
+	VL53L0X_SequenceStepId SequenceStepId, uint8_t *pSequenceStepEnabled)
+{
+	VL53L0X_Error Status = VL53L0X_ERROR_NONE;
+	uint8_t SequenceConfig = 0;
+	LOG_FUNCTION_START("");
+
+	Status = VL53L0X_RdByte(Dev, VL53L0X_REG_SYSTEM_SEQUENCE_CONFIG,
+		&SequenceConfig);
+
+	if (Status == VL53L0X_ERROR_NONE) {
+		Status = sequence_step_enabled(Dev, SequenceStepId,
+			SequenceConfig, pSequenceStepEnabled);
+	}
+
+	LOG_FUNCTION_END(Status);
+	return Status;
+}
+
+VL53L0X_Error VL53L0X_GetSequenceStepEnables(VL53L0X_DEV Dev,
+	VL53L0X_SchedulerSequenceSteps_t *pSchedulerSequenceSteps)
+{
+	VL53L0X_Error Status = VL53L0X_ERROR_NONE;
+	uint8_t SequenceConfig = 0;
+	LOG_FUNCTION_START("");
+
+	Status = VL53L0X_RdByte(Dev, VL53L0X_REG_SYSTEM_SEQUENCE_CONFIG,
+		&SequenceConfig);
+
+	if (Status == VL53L0X_ERROR_NONE) {
+		Status = sequence_step_enabled(Dev,
+		VL53L0X_SEQUENCESTEP_TCC, SequenceConfig,
+			&pSchedulerSequenceSteps->TccOn);
+	}
+	if (Status == VL53L0X_ERROR_NONE) {
+		Status = sequence_step_enabled(Dev,
+		VL53L0X_SEQUENCESTEP_DSS, SequenceConfig,
+			&pSchedulerSequenceSteps->DssOn);
+	}
+	if (Status == VL53L0X_ERROR_NONE) {
+		Status = sequence_step_enabled(Dev,
+		VL53L0X_SEQUENCESTEP_MSRC, SequenceConfig,
+			&pSchedulerSequenceSteps->MsrcOn);
+	}
+	if (Status == VL53L0X_ERROR_NONE) {
+		Status = sequence_step_enabled(Dev,
+		VL53L0X_SEQUENCESTEP_PRE_RANGE, SequenceConfig,
+			&pSchedulerSequenceSteps->PreRangeOn);
+	}
+	if (Status == VL53L0X_ERROR_NONE) {
+		Status = sequence_step_enabled(Dev,
+		VL53L0X_SEQUENCESTEP_FINAL_RANGE, SequenceConfig,
+			&pSchedulerSequenceSteps->FinalRangeOn);
+	}
+
+	LOG_FUNCTION_END(Status);
+	return Status;
+}
+
+VL53L0X_Error VL53L0X_GetNumberOfSequenceSteps(VL53L0X_DEV Dev,
+	uint8_t *pNumberOfSequenceSteps)
+{
+	VL53L0X_Error Status = VL53L0X_ERROR_NONE;
+	LOG_FUNCTION_START("");
+
+	*pNumberOfSequenceSteps = VL53L0X_SEQUENCESTEP_NUMBER_OF_CHECKS;
+
+	LOG_FUNCTION_END(Status);
+	return Status;
+}
+
+VL53L0X_Error VL53L0X_GetSequenceStepsInfo(VL53L0X_SequenceStepId SequenceStepId,
+	char *pSequenceStepsString)
+{
+	VL53L0X_Error Status = VL53L0X_ERROR_NONE;
+	LOG_FUNCTION_START("");
+
+	Status = VL53L0X_get_sequence_steps_info(
+			SequenceStepId,
+			pSequenceStepsString);
+
+	LOG_FUNCTION_END(Status);
+
+	return Status;
+}
+
+VL53L0X_Error VL53L0X_SetSequenceStepTimeout(VL53L0X_DEV Dev,
+	VL53L0X_SequenceStepId SequenceStepId, FixPoint1616_t TimeOutMilliSecs)
+{
+	VL53L0X_Error Status = VL53L0X_ERROR_NONE;
+	VL53L0X_Error Status1 = VL53L0X_ERROR_NONE;
+	uint32_t TimeoutMicroSeconds = ((TimeOutMilliSecs * 1000) + 0x8000)
+		>> 16;
+	uint32_t MeasurementTimingBudgetMicroSeconds;
+	FixPoint1616_t OldTimeOutMicroSeconds;
+
+	LOG_FUNCTION_START("");
+
+	/* Read back the current value in case we need to revert back to this.
+	 */
+	Status = get_sequence_step_timeout(Dev, SequenceStepId,
+		&OldTimeOutMicroSeconds);
+
+	if (Status == VL53L0X_ERROR_NONE) {
+		Status = set_sequence_step_timeout(Dev, SequenceStepId,
+			TimeoutMicroSeconds);
+	}
+
+	if (Status == VL53L0X_ERROR_NONE) {
+		VL53L0X_GETPARAMETERFIELD(Dev,
+			MeasurementTimingBudgetMicroSeconds,
+			MeasurementTimingBudgetMicroSeconds);
+
+		/* At this point we don't know if the requested value is valid,
+		 therefore proceed to update the entire timing budget and
+		 if this fails, revert back to the previous value.
+		 */
+		Status = VL53L0X_SetMeasurementTimingBudgetMicroSeconds(Dev,
+			MeasurementTimingBudgetMicroSeconds);
+
+		if (Status != VL53L0X_ERROR_NONE) {
+			Status1 = set_sequence_step_timeout(Dev, SequenceStepId,
+				OldTimeOutMicroSeconds);
+
+			if (Status1 == VL53L0X_ERROR_NONE) {
+				Status1 =
+				VL53L0X_SetMeasurementTimingBudgetMicroSeconds(
+					Dev,
+					MeasurementTimingBudgetMicroSeconds);
+			}
+
+			Status = Status1;
+		}
+	}
+
+	LOG_FUNCTION_END(Status);
+
+	return Status;
+}
+
+VL53L0X_Error VL53L0X_GetSequenceStepTimeout(VL53L0X_DEV Dev,
+	VL53L0X_SequenceStepId SequenceStepId, FixPoint1616_t *pTimeOutMilliSecs)
+{
+	VL53L0X_Error Status = VL53L0X_ERROR_NONE;
+	uint32_t TimeoutMicroSeconds;
+	uint32_t WholeNumber_ms = 0;
+	uint32_t Fraction_ms = 0;
+	LOG_FUNCTION_START("");
+
+	Status = get_sequence_step_timeout(Dev, SequenceStepId,
+		&TimeoutMicroSeconds);
+	if (Status == VL53L0X_ERROR_NONE) {
+		WholeNumber_ms = TimeoutMicroSeconds / 1000;
+		Fraction_ms = TimeoutMicroSeconds - (WholeNumber_ms * 1000);
+		*pTimeOutMilliSecs = (WholeNumber_ms << 16)
+			+ (((Fraction_ms * 0xffff) + 500) / 1000);
+	}
+
+	LOG_FUNCTION_END(Status);
+	return Status;
+}
+
+VL53L0X_Error VL53L0X_SetInterMeasurementPeriodMilliSeconds(VL53L0X_DEV Dev,
+	uint32_t InterMeasurementPeriodMilliSeconds)
+{
+	VL53L0X_Error Status = VL53L0X_ERROR_NONE;
+	uint16_t osc_calibrate_val;
+	uint32_t IMPeriodMilliSeconds;
+
+	LOG_FUNCTION_START("");
+
+	Status = VL53L0X_RdWord(Dev, VL53L0X_REG_OSC_CALIBRATE_VAL,
+		&osc_calibrate_val);
+
+	if (Status == VL53L0X_ERROR_NONE) {
+		if (osc_calibrate_val != 0) {
+			IMPeriodMilliSeconds =
+				InterMeasurementPeriodMilliSeconds
+					* osc_calibrate_val;
+		} else {
+			IMPeriodMilliSeconds =
+				InterMeasurementPeriodMilliSeconds;
+		}
+		Status = VL53L0X_WrDWord(Dev,
+		VL53L0X_REG_SYSTEM_INTERMEASUREMENT_PERIOD,
+			IMPeriodMilliSeconds);
+	}
+
+	if (Status == VL53L0X_ERROR_NONE) {
+		VL53L0X_SETPARAMETERFIELD(Dev,
+			InterMeasurementPeriodMilliSeconds,
+			InterMeasurementPeriodMilliSeconds);
+	}
+
+	LOG_FUNCTION_END(Status);
+	return Status;
+}
+
+VL53L0X_Error VL53L0X_GetInterMeasurementPeriodMilliSeconds(VL53L0X_DEV Dev,
+	uint32_t *pInterMeasurementPeriodMilliSeconds)
+{
+	VL53L0X_Error Status = VL53L0X_ERROR_NONE;
+	uint16_t osc_calibrate_val;
+	uint32_t IMPeriodMilliSeconds;
+
+	LOG_FUNCTION_START("");
+
+	Status = VL53L0X_RdWord(Dev, VL53L0X_REG_OSC_CALIBRATE_VAL,
+		&osc_calibrate_val);
+
+	if (Status == VL53L0X_ERROR_NONE) {
+		Status = VL53L0X_RdDWord(Dev,
+		VL53L0X_REG_SYSTEM_INTERMEASUREMENT_PERIOD,
+			&IMPeriodMilliSeconds);
+	}
+
+	if (Status == VL53L0X_ERROR_NONE) {
+		if (osc_calibrate_val != 0) {
+			*pInterMeasurementPeriodMilliSeconds =
+				IMPeriodMilliSeconds / osc_calibrate_val;
+		}
+		VL53L0X_SETPARAMETERFIELD(Dev,
+			InterMeasurementPeriodMilliSeconds,
+			*pInterMeasurementPeriodMilliSeconds);
+	}
+
+	LOG_FUNCTION_END(Status);
+	return Status;
+}
+
+VL53L0X_Error VL53L0X_SetXTalkCompensationEnable(VL53L0X_DEV Dev,
+	uint8_t XTalkCompensationEnable)
+{
+	VL53L0X_Error Status = VL53L0X_ERROR_NONE;
+	FixPoint1616_t TempFix1616;
+	uint16_t LinearityCorrectiveGain;
+
+	LOG_FUNCTION_START("");
+
+	LinearityCorrectiveGain = PALDevDataGet(Dev, LinearityCorrectiveGain);
+
+	if ((XTalkCompensationEnable == 0)
+		|| (LinearityCorrectiveGain != 1000)) {
+		TempFix1616 = 0;
+	} else {
+		VL53L0X_GETPARAMETERFIELD(Dev, XTalkCompensationRateMegaCps,
+			TempFix1616);
+	}
+
+	/* the following register has a format 3.13 */
+	Status = VL53L0X_WrWord(Dev,
+	VL53L0X_REG_CROSSTALK_COMPENSATION_PEAK_RATE_MCPS,
+		VL53L0X_FIXPOINT1616TOFIXPOINT313(TempFix1616));
+
+	if (Status == VL53L0X_ERROR_NONE) {
+		if (XTalkCompensationEnable == 0) {
+			VL53L0X_SETPARAMETERFIELD(Dev, XTalkCompensationEnable,
+				0);
+		} else {
+			VL53L0X_SETPARAMETERFIELD(Dev, XTalkCompensationEnable,
+				1);
+		}
+	}
+
+	LOG_FUNCTION_END(Status);
+	return Status;
+}
+
+VL53L0X_Error VL53L0X_GetXTalkCompensationEnable(VL53L0X_DEV Dev,
+	uint8_t *pXTalkCompensationEnable)
+{
+	VL53L0X_Error Status = VL53L0X_ERROR_NONE;
+	uint8_t Temp8;
+	LOG_FUNCTION_START("");
+
+	VL53L0X_GETPARAMETERFIELD(Dev, XTalkCompensationEnable, Temp8);
+	*pXTalkCompensationEnable = Temp8;
+
+	LOG_FUNCTION_END(Status);
+	return Status;
+}
+
+VL53L0X_Error VL53L0X_SetXTalkCompensationRateMegaCps(VL53L0X_DEV Dev,
+	FixPoint1616_t XTalkCompensationRateMegaCps)
+{
+	VL53L0X_Error Status = VL53L0X_ERROR_NONE;
+	uint8_t Temp8;
+	uint16_t LinearityCorrectiveGain;
+	uint16_t data;
+	LOG_FUNCTION_START("");
+
+	VL53L0X_GETPARAMETERFIELD(Dev, XTalkCompensationEnable, Temp8);
+	LinearityCorrectiveGain = PALDevDataGet(Dev, LinearityCorrectiveGain);
+
+	if (Temp8 == 0) { /* disabled write only internal value */
+		VL53L0X_SETPARAMETERFIELD(Dev, XTalkCompensationRateMegaCps,
+			XTalkCompensationRateMegaCps);
+	} else {
+		/* the following register has a format 3.13 */
+		if (LinearityCorrectiveGain == 1000) {
+			data = VL53L0X_FIXPOINT1616TOFIXPOINT313(
+				XTalkCompensationRateMegaCps);
+		} else {
+			data = 0;
+		}
+
+		Status = VL53L0X_WrWord(Dev,
+		VL53L0X_REG_CROSSTALK_COMPENSATION_PEAK_RATE_MCPS, data);
+
+		if (Status == VL53L0X_ERROR_NONE) {
+			VL53L0X_SETPARAMETERFIELD(Dev,
+				XTalkCompensationRateMegaCps,
+				XTalkCompensationRateMegaCps);
+		}
+	}
+
+	LOG_FUNCTION_END(Status);
+	return Status;
+}
+
+VL53L0X_Error VL53L0X_GetXTalkCompensationRateMegaCps(VL53L0X_DEV Dev,
+	FixPoint1616_t *pXTalkCompensationRateMegaCps)
+{
+	VL53L0X_Error Status = VL53L0X_ERROR_NONE;
+	uint16_t Value;
+	FixPoint1616_t TempFix1616;
+
+	LOG_FUNCTION_START("");
+
+	Status = VL53L0X_RdWord(Dev,
+	VL53L0X_REG_CROSSTALK_COMPENSATION_PEAK_RATE_MCPS, (uint16_t *)&Value);
+	if (Status == VL53L0X_ERROR_NONE) {
+		if (Value == 0) {
+			/* the Xtalk is disabled return value from memory */
+			VL53L0X_GETPARAMETERFIELD(Dev,
+				XTalkCompensationRateMegaCps, TempFix1616);
+			*pXTalkCompensationRateMegaCps = TempFix1616;
+			VL53L0X_SETPARAMETERFIELD(Dev, XTalkCompensationEnable,
+				0);
+		} else {
+			TempFix1616 = VL53L0X_FIXPOINT313TOFIXPOINT1616(Value);
+			*pXTalkCompensationRateMegaCps = TempFix1616;
+			VL53L0X_SETPARAMETERFIELD(Dev,
+				XTalkCompensationRateMegaCps, TempFix1616);
+			VL53L0X_SETPARAMETERFIELD(Dev, XTalkCompensationEnable,
+				1);
+		}
+	}
+
+	LOG_FUNCTION_END(Status);
+	return Status;
+}
+
+VL53L0X_Error VL53L0X_SetRefCalibration(VL53L0X_DEV Dev, uint8_t VhvSettings,
+	uint8_t PhaseCal)
+{
+	VL53L0X_Error Status = VL53L0X_ERROR_NONE;
+	LOG_FUNCTION_START("");
+
+	Status = VL53L0X_set_ref_calibration(Dev, VhvSettings, PhaseCal);
+
+	LOG_FUNCTION_END(Status);
+	return Status;
+}
+
+VL53L0X_Error VL53L0X_GetRefCalibration(VL53L0X_DEV Dev, uint8_t *pVhvSettings,
+	uint8_t *pPhaseCal)
+{
+	VL53L0X_Error Status = VL53L0X_ERROR_NONE;
+	LOG_FUNCTION_START("");
+
+	Status = VL53L0X_get_ref_calibration(Dev, pVhvSettings, pPhaseCal);
+
+	LOG_FUNCTION_END(Status);
+	return Status;
+}
+
+/*
+ * CHECK LIMIT FUNCTIONS
+ */
+
+VL53L0X_Error VL53L0X_GetNumberOfLimitCheck(uint16_t *pNumberOfLimitCheck)
+{
+	VL53L0X_Error Status = VL53L0X_ERROR_NONE;
+	LOG_FUNCTION_START("");
+
+	*pNumberOfLimitCheck = VL53L0X_CHECKENABLE_NUMBER_OF_CHECKS;
+
+	LOG_FUNCTION_END(Status);
+	return Status;
+}
+
+VL53L0X_Error VL53L0X_GetLimitCheckInfo(VL53L0X_DEV Dev, uint16_t LimitCheckId,
+	char *pLimitCheckString)
+{
+	VL53L0X_Error Status = VL53L0X_ERROR_NONE;
+
+	LOG_FUNCTION_START("");
+
+	Status = VL53L0X_get_limit_check_info(Dev, LimitCheckId,
+		pLimitCheckString);
+
+	LOG_FUNCTION_END(Status);
+	return Status;
+}
+
+VL53L0X_Error VL53L0X_GetLimitCheckStatus(VL53L0X_DEV Dev, uint16_t LimitCheckId,
+	uint8_t *pLimitCheckStatus)
+{
+	VL53L0X_Error Status = VL53L0X_ERROR_NONE;
+	uint8_t Temp8;
+
+	LOG_FUNCTION_START("");
+
+	if (LimitCheckId >= VL53L0X_CHECKENABLE_NUMBER_OF_CHECKS) {
+		Status = VL53L0X_ERROR_INVALID_PARAMS;
+	} else {
+
+		VL53L0X_GETARRAYPARAMETERFIELD(Dev, LimitChecksStatus,
+			LimitCheckId, Temp8);
+
+		*pLimitCheckStatus = Temp8;
+
+	}
+
+	LOG_FUNCTION_END(Status);
+	return Status;
+}
+
+VL53L0X_Error VL53L0X_SetLimitCheckEnable(VL53L0X_DEV Dev, uint16_t LimitCheckId,
+	uint8_t LimitCheckEnable)
+{
+	VL53L0X_Error Status = VL53L0X_ERROR_NONE;
+	FixPoint1616_t TempFix1616 = 0;
+	uint8_t LimitCheckEnableInt = 0;
+	uint8_t LimitCheckDisable = 0;
+	uint8_t Temp8;
+
+	LOG_FUNCTION_START("");
+
+	if (LimitCheckId >= VL53L0X_CHECKENABLE_NUMBER_OF_CHECKS) {
+		Status = VL53L0X_ERROR_INVALID_PARAMS;
+	} else {
+		if (LimitCheckEnable == 0) {
+			TempFix1616 = 0;
+			LimitCheckEnableInt = 0;
+			LimitCheckDisable = 1;
+
+		} else {
+			VL53L0X_GETARRAYPARAMETERFIELD(Dev, LimitChecksValue,
+				LimitCheckId, TempFix1616);
+			LimitCheckDisable = 0;
+			/* this to be sure to have either 0 or 1 */
+			LimitCheckEnableInt = 1;
+		}
+
+		switch (LimitCheckId) {
+
+		case VL53L0X_CHECKENABLE_SIGMA_FINAL_RANGE:
+			/* internal computation: */
+			VL53L0X_SETARRAYPARAMETERFIELD(Dev, LimitChecksEnable,
+				VL53L0X_CHECKENABLE_SIGMA_FINAL_RANGE,
+				LimitCheckEnableInt);
+
+			break;
+
+		case VL53L0X_CHECKENABLE_SIGNAL_RATE_FINAL_RANGE:
+
+			Status = VL53L0X_WrWord(Dev,
+			VL53L0X_REG_FINAL_RANGE_CONFIG_MIN_COUNT_RATE_RTN_LIMIT,
+				VL53L0X_FIXPOINT1616TOFIXPOINT97(TempFix1616));
+
+			break;
+
+		case VL53L0X_CHECKENABLE_SIGNAL_REF_CLIP:
+
+			/* internal computation: */
+			VL53L0X_SETARRAYPARAMETERFIELD(Dev, LimitChecksEnable,
+				VL53L0X_CHECKENABLE_SIGNAL_REF_CLIP,
+				LimitCheckEnableInt);
+
+			break;
+
+		case VL53L0X_CHECKENABLE_RANGE_IGNORE_THRESHOLD:
+
+			/* internal computation: */
+			VL53L0X_SETARRAYPARAMETERFIELD(Dev, LimitChecksEnable,
+				VL53L0X_CHECKENABLE_RANGE_IGNORE_THRESHOLD,
+				LimitCheckEnableInt);
+
+			break;
+
+		case VL53L0X_CHECKENABLE_SIGNAL_RATE_MSRC:
+
+			Temp8 = (uint8_t)(LimitCheckDisable << 1);
+			Status = VL53L0X_UpdateByte(Dev,
+				VL53L0X_REG_MSRC_CONFIG_CONTROL,
+				0xFE, Temp8);
+
+			break;
+
+		case VL53L0X_CHECKENABLE_SIGNAL_RATE_PRE_RANGE:
+
+			Temp8 = (uint8_t)(LimitCheckDisable << 4);
+			Status = VL53L0X_UpdateByte(Dev,
+				VL53L0X_REG_MSRC_CONFIG_CONTROL,
+				0xEF, Temp8);
+
+			break;
+
+
+		default:
+			Status = VL53L0X_ERROR_INVALID_PARAMS;
+
+		}
+
+	}
+
+	if (Status == VL53L0X_ERROR_NONE) {
+		if (LimitCheckEnable == 0) {
+			VL53L0X_SETARRAYPARAMETERFIELD(Dev, LimitChecksEnable,
+				LimitCheckId, 0);
+		} else {
+			VL53L0X_SETARRAYPARAMETERFIELD(Dev, LimitChecksEnable,
+				LimitCheckId, 1);
+		}
+	}
+
+	LOG_FUNCTION_END(Status);
+	return Status;
+}
+
+VL53L0X_Error VL53L0X_GetLimitCheckEnable(VL53L0X_DEV Dev, uint16_t LimitCheckId,
+	uint8_t *pLimitCheckEnable)
+{
+	VL53L0X_Error Status = VL53L0X_ERROR_NONE;
+	uint8_t Temp8;
+
+	LOG_FUNCTION_START("");
+
+	if (LimitCheckId >= VL53L0X_CHECKENABLE_NUMBER_OF_CHECKS) {
+		Status = VL53L0X_ERROR_INVALID_PARAMS;
+		*pLimitCheckEnable = 0;
+	} else {
+		VL53L0X_GETARRAYPARAMETERFIELD(Dev, LimitChecksEnable,
+			LimitCheckId, Temp8);
+		*pLimitCheckEnable = Temp8;
+	}
+
+	LOG_FUNCTION_END(Status);
+	return Status;
+}
+
+VL53L0X_Error VL53L0X_SetLimitCheckValue(VL53L0X_DEV Dev, uint16_t LimitCheckId,
+	FixPoint1616_t LimitCheckValue)
+{
+	VL53L0X_Error Status = VL53L0X_ERROR_NONE;
+	uint8_t Temp8;
+
+	LOG_FUNCTION_START("");
+
+	VL53L0X_GETARRAYPARAMETERFIELD(Dev, LimitChecksEnable, LimitCheckId,
+		Temp8);
+
+	if (Temp8 == 0) { /* disabled write only internal value */
+		VL53L0X_SETARRAYPARAMETERFIELD(Dev, LimitChecksValue,
+			LimitCheckId, LimitCheckValue);
+	} else {
+
+		switch (LimitCheckId) {
+
+		case VL53L0X_CHECKENABLE_SIGMA_FINAL_RANGE:
+			/* internal computation: */
+			VL53L0X_SETARRAYPARAMETERFIELD(Dev, LimitChecksValue,
+				VL53L0X_CHECKENABLE_SIGMA_FINAL_RANGE,
+				LimitCheckValue);
+			break;
+
+		case VL53L0X_CHECKENABLE_SIGNAL_RATE_FINAL_RANGE:
+
+			Status = VL53L0X_WrWord(Dev,
+			VL53L0X_REG_FINAL_RANGE_CONFIG_MIN_COUNT_RATE_RTN_LIMIT,
+				VL53L0X_FIXPOINT1616TOFIXPOINT97(
+					LimitCheckValue));
+
+			break;
+
+		case VL53L0X_CHECKENABLE_SIGNAL_REF_CLIP:
+
+			/* internal computation: */
+			VL53L0X_SETARRAYPARAMETERFIELD(Dev, LimitChecksValue,
+				VL53L0X_CHECKENABLE_SIGNAL_REF_CLIP,
+				LimitCheckValue);
+
+			break;
+
+		case VL53L0X_CHECKENABLE_RANGE_IGNORE_THRESHOLD:
+
+			/* internal computation: */
+			VL53L0X_SETARRAYPARAMETERFIELD(Dev, LimitChecksValue,
+				VL53L0X_CHECKENABLE_RANGE_IGNORE_THRESHOLD,
+				LimitCheckValue);
+
+			break;
+
+		case VL53L0X_CHECKENABLE_SIGNAL_RATE_MSRC:
+		case VL53L0X_CHECKENABLE_SIGNAL_RATE_PRE_RANGE:
+
+			Status = VL53L0X_WrWord(Dev,
+				VL53L0X_REG_PRE_RANGE_MIN_COUNT_RATE_RTN_LIMIT,
+				VL53L0X_FIXPOINT1616TOFIXPOINT97(
+					LimitCheckValue));
+
+			break;
+
+		default:
+			Status = VL53L0X_ERROR_INVALID_PARAMS;
+
+		}
+
+		if (Status == VL53L0X_ERROR_NONE) {
+			VL53L0X_SETARRAYPARAMETERFIELD(Dev, LimitChecksValue,
+				LimitCheckId, LimitCheckValue);
+		}
+	}
+
+	LOG_FUNCTION_END(Status);
+	return Status;
+}
+
+VL53L0X_Error VL53L0X_GetLimitCheckValue(VL53L0X_DEV Dev, uint16_t LimitCheckId,
+	FixPoint1616_t *pLimitCheckValue)
+{
+	VL53L0X_Error Status = VL53L0X_ERROR_NONE;
+	uint8_t EnableZeroValue = 0;
+	uint16_t Temp16;
+	FixPoint1616_t TempFix1616;
+
+	LOG_FUNCTION_START("");
+
+	switch (LimitCheckId) {
+
+	case VL53L0X_CHECKENABLE_SIGMA_FINAL_RANGE:
+		/* internal computation: */
+		VL53L0X_GETARRAYPARAMETERFIELD(Dev, LimitChecksValue,
+			VL53L0X_CHECKENABLE_SIGMA_FINAL_RANGE, TempFix1616);
+		EnableZeroValue = 0;
+		break;
+
+	case VL53L0X_CHECKENABLE_SIGNAL_RATE_FINAL_RANGE:
+		Status = VL53L0X_RdWord(Dev,
+		VL53L0X_REG_FINAL_RANGE_CONFIG_MIN_COUNT_RATE_RTN_LIMIT,
+			&Temp16);
+		if (Status == VL53L0X_ERROR_NONE)
+			TempFix1616 = VL53L0X_FIXPOINT97TOFIXPOINT1616(Temp16);
+
+
+		EnableZeroValue = 1;
+		break;
+
+	case VL53L0X_CHECKENABLE_SIGNAL_REF_CLIP:
+		/* internal computation: */
+		VL53L0X_GETARRAYPARAMETERFIELD(Dev, LimitChecksValue,
+			VL53L0X_CHECKENABLE_SIGNAL_REF_CLIP, TempFix1616);
+		EnableZeroValue = 0;
+		break;
+
+	case VL53L0X_CHECKENABLE_RANGE_IGNORE_THRESHOLD:
+		/* internal computation: */
+		VL53L0X_GETARRAYPARAMETERFIELD(Dev, LimitChecksValue,
+			VL53L0X_CHECKENABLE_RANGE_IGNORE_THRESHOLD, TempFix1616);
+		EnableZeroValue = 0;
+		break;
+
+	case VL53L0X_CHECKENABLE_SIGNAL_RATE_MSRC:
+	case VL53L0X_CHECKENABLE_SIGNAL_RATE_PRE_RANGE:
+		Status = VL53L0X_RdWord(Dev,
+			VL53L0X_REG_PRE_RANGE_MIN_COUNT_RATE_RTN_LIMIT,
+			&Temp16);
+		if (Status == VL53L0X_ERROR_NONE)
+			TempFix1616 = VL53L0X_FIXPOINT97TOFIXPOINT1616(Temp16);
+
+
+		EnableZeroValue = 0;
+		break;
+
+	default:
+		Status = VL53L0X_ERROR_INVALID_PARAMS;
+
+	}
+
+	if (Status == VL53L0X_ERROR_NONE) {
+
+		if (EnableZeroValue == 1) {
+
+			if (TempFix1616 == 0) {
+				/* disabled: return value from memory */
+				VL53L0X_GETARRAYPARAMETERFIELD(Dev,
+					LimitChecksValue, LimitCheckId,
+					TempFix1616);
+				*pLimitCheckValue = TempFix1616;
+				VL53L0X_SETARRAYPARAMETERFIELD(Dev,
+					LimitChecksEnable, LimitCheckId, 0);
+			} else {
+				*pLimitCheckValue = TempFix1616;
+				VL53L0X_SETARRAYPARAMETERFIELD(Dev,
+					LimitChecksValue, LimitCheckId,
+					TempFix1616);
+				VL53L0X_SETARRAYPARAMETERFIELD(Dev,
+					LimitChecksEnable, LimitCheckId, 1);
+			}
+		} else {
+			*pLimitCheckValue = TempFix1616;
+		}
+	}
+
+	LOG_FUNCTION_END(Status);
+	return Status;
+
+}
+
+VL53L0X_Error VL53L0X_GetLimitCheckCurrent(VL53L0X_DEV Dev, uint16_t LimitCheckId,
+	FixPoint1616_t *pLimitCheckCurrent)
+{
+	VL53L0X_Error Status = VL53L0X_ERROR_NONE;
+	VL53L0X_RangingMeasurementData_t LastRangeDataBuffer;
+
+	LOG_FUNCTION_START("");
+
+	if (LimitCheckId >= VL53L0X_CHECKENABLE_NUMBER_OF_CHECKS) {
+		Status = VL53L0X_ERROR_INVALID_PARAMS;
+	} else {
+		switch (LimitCheckId) {
+		case VL53L0X_CHECKENABLE_SIGMA_FINAL_RANGE:
+			/* Need to run a ranging to have the latest values */
+			*pLimitCheckCurrent = PALDevDataGet(Dev, SigmaEstimate);
+
+			break;
+
+		case VL53L0X_CHECKENABLE_SIGNAL_RATE_FINAL_RANGE:
+			/* Need to run a ranging to have the latest values */
+			LastRangeDataBuffer = PALDevDataGet(Dev,
+				LastRangeMeasure);
+			*pLimitCheckCurrent =
+				LastRangeDataBuffer.SignalRateRtnMegaCps;
+
+			break;
+
+		case VL53L0X_CHECKENABLE_SIGNAL_REF_CLIP:
+			/* Need to run a ranging to have the latest values */
+			*pLimitCheckCurrent = PALDevDataGet(Dev,
+				LastSignalRefMcps);
+
+			break;
+
+		case VL53L0X_CHECKENABLE_RANGE_IGNORE_THRESHOLD:
+			/* Need to run a ranging to have the latest values */
+			LastRangeDataBuffer = PALDevDataGet(Dev,
+				LastRangeMeasure);
+			*pLimitCheckCurrent =
+				LastRangeDataBuffer.SignalRateRtnMegaCps;
+
+			break;
+
+		case VL53L0X_CHECKENABLE_SIGNAL_RATE_MSRC:
+			/* Need to run a ranging to have the latest values */
+			LastRangeDataBuffer = PALDevDataGet(Dev,
+				LastRangeMeasure);
+			*pLimitCheckCurrent =
+				LastRangeDataBuffer.SignalRateRtnMegaCps;
+
+			break;
+
+		case VL53L0X_CHECKENABLE_SIGNAL_RATE_PRE_RANGE:
+			/* Need to run a ranging to have the latest values */
+			LastRangeDataBuffer = PALDevDataGet(Dev,
+				LastRangeMeasure);
+			*pLimitCheckCurrent =
+				LastRangeDataBuffer.SignalRateRtnMegaCps;
+
+			break;
+
+		default:
+			Status = VL53L0X_ERROR_INVALID_PARAMS;
+		}
+	}
+
+	LOG_FUNCTION_END(Status);
+	return Status;
+
+}
+
+/*
+ * WRAPAROUND Check
+ */
+VL53L0X_Error VL53L0X_SetWrapAroundCheckEnable(VL53L0X_DEV Dev,
+	uint8_t WrapAroundCheckEnable)
+{
+	VL53L0X_Error Status = VL53L0X_ERROR_NONE;
+	uint8_t Byte;
+	uint8_t WrapAroundCheckEnableInt;
+
+	LOG_FUNCTION_START("");
+
+	Status = VL53L0X_RdByte(Dev, VL53L0X_REG_SYSTEM_SEQUENCE_CONFIG, &Byte);
+	if (WrapAroundCheckEnable == 0) {
+		/* Disable wraparound */
+		Byte = Byte & 0x7F;
+		WrapAroundCheckEnableInt = 0;
+	} else {
+		/*Enable wraparound */
+		Byte = Byte | 0x80;
+		WrapAroundCheckEnableInt = 1;
+	}
+
+	Status = VL53L0X_WrByte(Dev, VL53L0X_REG_SYSTEM_SEQUENCE_CONFIG, Byte);
+
+	if (Status == VL53L0X_ERROR_NONE) {
+		PALDevDataSet(Dev, SequenceConfig, Byte);
+		VL53L0X_SETPARAMETERFIELD(Dev, WrapAroundCheckEnable,
+			WrapAroundCheckEnableInt);
+	}
+
+	LOG_FUNCTION_END(Status);
+	return Status;
+}
+
+VL53L0X_Error VL53L0X_GetWrapAroundCheckEnable(VL53L0X_DEV Dev,
+	uint8_t *pWrapAroundCheckEnable)
+{
+	VL53L0X_Error Status = VL53L0X_ERROR_NONE;
+	uint8_t data;
+
+	LOG_FUNCTION_START("");
+
+	Status = VL53L0X_RdByte(Dev, VL53L0X_REG_SYSTEM_SEQUENCE_CONFIG, &data);
+	if (Status == VL53L0X_ERROR_NONE) {
+		PALDevDataSet(Dev, SequenceConfig, data);
+		if (data & (0x01 << 7))
+			*pWrapAroundCheckEnable = 0x01;
+		else
+			*pWrapAroundCheckEnable = 0x00;
+	}
+	if (Status == VL53L0X_ERROR_NONE) {
+		VL53L0X_SETPARAMETERFIELD(Dev, WrapAroundCheckEnable,
+			*pWrapAroundCheckEnable);
+	}
+
+	LOG_FUNCTION_END(Status);
+	return Status;
+}
+
+VL53L0X_Error VL53L0X_SetDmaxCalParameters(VL53L0X_DEV Dev,
+	uint16_t RangeMilliMeter, FixPoint1616_t SignalRateRtnMegaCps)
+{
+	VL53L0X_Error Status = VL53L0X_ERROR_NONE;
+	FixPoint1616_t SignalRateRtnMegaCpsTemp = 0;
+
+	LOG_FUNCTION_START("");
+
+	/* Check if one of input parameter is zero, in that case the
+	 * value are get from NVM */
+	if ((RangeMilliMeter == 0) || (SignalRateRtnMegaCps == 0)) {
+		/* NVM parameters */
+		/* Run VL53L0X_get_info_from_device wit option 4 to get
+		 * signal rate at 400 mm if the value have been already
+		 * get this function will return with no access to device */
+		VL53L0X_get_info_from_device(Dev, 4);
+
+		SignalRateRtnMegaCpsTemp = VL53L0X_GETDEVICESPECIFICPARAMETER(
+			Dev, SignalRateMeasFixed400mm);
+
+		PALDevDataSet(Dev, DmaxCalRangeMilliMeter, 400);
+		PALDevDataSet(Dev, DmaxCalSignalRateRtnMegaCps,
+			SignalRateRtnMegaCpsTemp);
+	} else {
+		/* User parameters */
+		PALDevDataSet(Dev, DmaxCalRangeMilliMeter, RangeMilliMeter);
+		PALDevDataSet(Dev, DmaxCalSignalRateRtnMegaCps,
+			SignalRateRtnMegaCps);
+	}
+
+	LOG_FUNCTION_END(Status);
+	return Status;
+}
+
+VL53L0X_Error VL53L0X_GetDmaxCalParameters(VL53L0X_DEV Dev,
+	uint16_t *pRangeMilliMeter, FixPoint1616_t *pSignalRateRtnMegaCps)
+{
+	VL53L0X_Error Status = VL53L0X_ERROR_NONE;
+
+	LOG_FUNCTION_START("");
+
+	*pRangeMilliMeter = PALDevDataGet(Dev, DmaxCalRangeMilliMeter);
+	*pSignalRateRtnMegaCps = PALDevDataGet(Dev,
+		DmaxCalSignalRateRtnMegaCps);
+
+	LOG_FUNCTION_END(Status);
+	return Status;
+}
+
+/* End Group PAL Parameters Functions */
+
+/* Group PAL Measurement Functions */
+VL53L0X_Error VL53L0X_PerformSingleMeasurement(VL53L0X_DEV Dev)
+{
+	VL53L0X_Error Status = VL53L0X_ERROR_NONE;
+	VL53L0X_DeviceModes DeviceMode;
+
+	LOG_FUNCTION_START("");
+
+	/* Get Current DeviceMode */
+	Status = VL53L0X_GetDeviceMode(Dev, &DeviceMode);
+
+	/* Start immediately to run a single ranging measurement in case of
+	 * single ranging or single histogram */
+	if (Status == VL53L0X_ERROR_NONE
+		&& DeviceMode == VL53L0X_DEVICEMODE_SINGLE_RANGING)
+		Status = VL53L0X_StartMeasurement(Dev);
+
+
+	if (Status == VL53L0X_ERROR_NONE)
+		Status = VL53L0X_measurement_poll_for_completion(Dev);
+
+
+	/* Change PAL State in case of single ranging or single histogram */
+	if (Status == VL53L0X_ERROR_NONE
+		&& DeviceMode == VL53L0X_DEVICEMODE_SINGLE_RANGING)
+		PALDevDataSet(Dev, PalState, VL53L0X_STATE_IDLE);
+
+
+	LOG_FUNCTION_END(Status);
+	return Status;
+}
+
+VL53L0X_Error VL53L0X_PerformSingleHistogramMeasurement(VL53L0X_DEV Dev,
+	VL53L0X_HistogramMeasurementData_t *pHistogramMeasurementData)
+{
+	VL53L0X_Error Status = VL53L0X_ERROR_NOT_IMPLEMENTED;
+	LOG_FUNCTION_START("");
+
+	/* not implemented on VL53L0X */
+
+	LOG_FUNCTION_END(Status);
+	return Status;
+}
+
+VL53L0X_Error VL53L0X_PerformRefCalibration(VL53L0X_DEV Dev, uint8_t *pVhvSettings,
+	uint8_t *pPhaseCal)
+{
+	VL53L0X_Error Status = VL53L0X_ERROR_NONE;
+	LOG_FUNCTION_START("");
+
+	Status = VL53L0X_perform_ref_calibration(Dev, pVhvSettings,
+		pPhaseCal, 1);
+
+	LOG_FUNCTION_END(Status);
+	return Status;
+}
+
+VL53L0X_Error VL53L0X_PerformXTalkMeasurement(VL53L0X_DEV Dev,
+	uint32_t TimeoutMs, FixPoint1616_t *pXtalkPerSpad,
+	uint8_t *pAmbientTooHigh)
+{
+	VL53L0X_Error Status = VL53L0X_ERROR_NOT_IMPLEMENTED;
+	LOG_FUNCTION_START("");
+
+	/* not implemented on VL53L0X */
+
+	LOG_FUNCTION_END(Status);
+	return Status;
+}
+
+VL53L0X_Error VL53L0X_PerformXTalkCalibration(VL53L0X_DEV Dev,
+	FixPoint1616_t XTalkCalDistance,
+	FixPoint1616_t *pXTalkCompensationRateMegaCps)
+{
+	VL53L0X_Error Status = VL53L0X_ERROR_NONE;
+	LOG_FUNCTION_START("");
+
+	Status = VL53L0X_perform_xtalk_calibration(Dev, XTalkCalDistance,
+		pXTalkCompensationRateMegaCps);
+
+	LOG_FUNCTION_END(Status);
+	return Status;
+}
+
+VL53L0X_Error VL53L0X_PerformOffsetCalibration(VL53L0X_DEV Dev,
+	FixPoint1616_t CalDistanceMilliMeter, int32_t *pOffsetMicroMeter)
+{
+	VL53L0X_Error Status = VL53L0X_ERROR_NONE;
+	LOG_FUNCTION_START("");
+
+	Status = VL53L0X_perform_offset_calibration(Dev, CalDistanceMilliMeter,
+		pOffsetMicroMeter);
+
+	LOG_FUNCTION_END(Status);
+	return Status;
+}
+
+VL53L0X_Error VL53L0X_CheckAndLoadInterruptSettings(VL53L0X_DEV Dev,
+	uint8_t StartNotStopFlag)
+{
+	uint8_t InterruptConfig;
+	FixPoint1616_t ThresholdLow;
+	FixPoint1616_t ThresholdHigh;
+	VL53L0X_Error Status = VL53L0X_ERROR_NONE;
+
+	InterruptConfig = VL53L0X_GETDEVICESPECIFICPARAMETER(Dev,
+		Pin0GpioFunctionality);
+
+	if ((InterruptConfig ==
+		VL53L0X_GPIOFUNCTIONALITY_THRESHOLD_CROSSED_LOW) ||
+		(InterruptConfig ==
+		VL53L0X_GPIOFUNCTIONALITY_THRESHOLD_CROSSED_HIGH) ||
+		(InterruptConfig ==
+		VL53L0X_GPIOFUNCTIONALITY_THRESHOLD_CROSSED_OUT)) {
+
+		Status = VL53L0X_GetInterruptThresholds(Dev,
+			VL53L0X_DEVICEMODE_CONTINUOUS_RANGING,
+			&ThresholdLow, &ThresholdHigh);
+
+		if (((ThresholdLow > 255*65536) ||
+			(ThresholdHigh > 255*65536)) &&
+			(Status == VL53L0X_ERROR_NONE)) {
+
+			if (StartNotStopFlag != 0) {
+				Status = VL53L0X_load_tuning_settings(Dev,
+					InterruptThresholdSettings);
+			} else {
+				Status |= VL53L0X_WrByte(Dev, 0xFF, 0x04);
+				Status |= VL53L0X_WrByte(Dev, 0x70, 0x00);
+				Status |= VL53L0X_WrByte(Dev, 0xFF, 0x00);
+				Status |= VL53L0X_WrByte(Dev, 0x80, 0x00);
+			}
+
+		}
+
+
+	}
+
+	return Status;
+
+}
+
+
+VL53L0X_Error VL53L0X_StartMeasurement(VL53L0X_DEV Dev)
+{
+	VL53L0X_Error Status = VL53L0X_ERROR_NONE;
+	VL53L0X_DeviceModes DeviceMode;
+	uint8_t Byte;
+	uint8_t StartStopByte = VL53L0X_REG_SYSRANGE_MODE_START_STOP;
+	uint32_t LoopNb;
+	LOG_FUNCTION_START("");
+
+	/* Get Current DeviceMode */
+	VL53L0X_GetDeviceMode(Dev, &DeviceMode);
+
+	Status = VL53L0X_WrByte(Dev, 0x80, 0x01);
+	Status = VL53L0X_WrByte(Dev, 0xFF, 0x01);
+	Status = VL53L0X_WrByte(Dev, 0x00, 0x00);
+	Status = VL53L0X_WrByte(Dev, 0x91, PALDevDataGet(Dev, StopVariable));
+	Status = VL53L0X_WrByte(Dev, 0x00, 0x01);
+	Status = VL53L0X_WrByte(Dev, 0xFF, 0x00);
+	Status = VL53L0X_WrByte(Dev, 0x80, 0x00);
+
+	switch (DeviceMode) {
+	case VL53L0X_DEVICEMODE_SINGLE_RANGING:
+		Status = VL53L0X_WrByte(Dev, VL53L0X_REG_SYSRANGE_START, 0x01);
+
+		Byte = StartStopByte;
+		if (Status == VL53L0X_ERROR_NONE) {
+			/* Wait until start bit has been cleared */
+			LoopNb = 0;
+			do {
+				if (LoopNb > 0)
+					Status = VL53L0X_RdByte(Dev,
+					VL53L0X_REG_SYSRANGE_START, &Byte);
+				LoopNb = LoopNb + 1;
+			} while (((Byte & StartStopByte) == StartStopByte)
+				&& (Status == VL53L0X_ERROR_NONE)
+				&& (LoopNb < VL53L0X_DEFAULT_MAX_LOOP));
+
+			if (LoopNb >= VL53L0X_DEFAULT_MAX_LOOP)
+				Status = VL53L0X_ERROR_TIME_OUT;
+
+		}
+
+		break;
+	case VL53L0X_DEVICEMODE_CONTINUOUS_RANGING:
+		/* Back-to-back mode */
+
+		/* Check if need to apply interrupt settings */
+		if (Status == VL53L0X_ERROR_NONE)
+			Status = VL53L0X_CheckAndLoadInterruptSettings(Dev, 1);
+
+		Status = VL53L0X_WrByte(Dev,
+		VL53L0X_REG_SYSRANGE_START,
+		VL53L0X_REG_SYSRANGE_MODE_BACKTOBACK);
+		if (Status == VL53L0X_ERROR_NONE) {
+			/* Set PAL State to Running */
+			PALDevDataSet(Dev, PalState, VL53L0X_STATE_RUNNING);
+		}
+		break;
+	case VL53L0X_DEVICEMODE_CONTINUOUS_TIMED_RANGING:
+		/* Continuous mode */
+		/* Check if need to apply interrupt settings */
+		if (Status == VL53L0X_ERROR_NONE)
+			Status = VL53L0X_CheckAndLoadInterruptSettings(Dev, 1);
+
+		Status = VL53L0X_WrByte(Dev,
+		VL53L0X_REG_SYSRANGE_START,
+		VL53L0X_REG_SYSRANGE_MODE_TIMED);
+
+		if (Status == VL53L0X_ERROR_NONE) {
+			/* Set PAL State to Running */
+			PALDevDataSet(Dev, PalState, VL53L0X_STATE_RUNNING);
+		}
+		break;
+	default:
+		/* Selected mode not supported */
+		Status = VL53L0X_ERROR_MODE_NOT_SUPPORTED;
+	}
+
+
+	LOG_FUNCTION_END(Status);
+	return Status;
+}
+
+VL53L0X_Error VL53L0X_StopMeasurement(VL53L0X_DEV Dev)
+{
+	VL53L0X_Error Status = VL53L0X_ERROR_NONE;
+	LOG_FUNCTION_START("");
+
+	Status = VL53L0X_WrByte(Dev, VL53L0X_REG_SYSRANGE_START,
+	VL53L0X_REG_SYSRANGE_MODE_SINGLESHOT);
+
+	Status = VL53L0X_WrByte(Dev, 0xFF, 0x01);
+	Status = VL53L0X_WrByte(Dev, 0x00, 0x00);
+	Status = VL53L0X_WrByte(Dev, 0x91, 0x00);
+	Status = VL53L0X_WrByte(Dev, 0x00, 0x01);
+	Status = VL53L0X_WrByte(Dev, 0xFF, 0x00);
+
+	if (Status == VL53L0X_ERROR_NONE) {
+		/* Set PAL State to Idle */
+		PALDevDataSet(Dev, PalState, VL53L0X_STATE_IDLE);
+	}
+
+	/* Check if need to apply interrupt settings */
+	if (Status == VL53L0X_ERROR_NONE)
+		Status = VL53L0X_CheckAndLoadInterruptSettings(Dev, 0);
+
+	LOG_FUNCTION_END(Status);
+	return Status;
+}
+
+VL53L0X_Error VL53L0X_GetMeasurementDataReady(VL53L0X_DEV Dev,
+	uint8_t *pMeasurementDataReady)
+{
+	VL53L0X_Error Status = VL53L0X_ERROR_NONE;
+	uint8_t SysRangeStatusRegister;
+	uint8_t InterruptConfig;
+	uint32_t InterruptMask;
+	LOG_FUNCTION_START("");
+
+	InterruptConfig = VL53L0X_GETDEVICESPECIFICPARAMETER(Dev,
+		Pin0GpioFunctionality);
+
+	if (InterruptConfig ==
+		VL53L0X_REG_SYSTEM_INTERRUPT_GPIO_NEW_SAMPLE_READY) {
+		Status = VL53L0X_GetInterruptMaskStatus(Dev, &InterruptMask);
+		if (InterruptMask ==
+		VL53L0X_REG_SYSTEM_INTERRUPT_GPIO_NEW_SAMPLE_READY)
+			*pMeasurementDataReady = 1;
+		else
+			*pMeasurementDataReady = 0;
+	} else {
+		Status = VL53L0X_RdByte(Dev, VL53L0X_REG_RESULT_RANGE_STATUS,
+			&SysRangeStatusRegister);
+		if (Status == VL53L0X_ERROR_NONE) {
+			if (SysRangeStatusRegister & 0x01)
+				*pMeasurementDataReady = 1;
+			else
+				*pMeasurementDataReady = 0;
+		}
+	}
+
+	LOG_FUNCTION_END(Status);
+	return Status;
+}
+
+VL53L0X_Error VL53L0X_WaitDeviceReadyForNewMeasurement(VL53L0X_DEV Dev,
+	uint32_t MaxLoop)
+{
+	VL53L0X_Error Status = VL53L0X_ERROR_NOT_IMPLEMENTED;
+	LOG_FUNCTION_START("");
+
+	/* not implemented for VL53L0X */
+
+	LOG_FUNCTION_END(Status);
+	return Status;
+}
+
+
+VL53L0X_Error VL53L0X_GetRangingMeasurementData(VL53L0X_DEV Dev,
+	VL53L0X_RangingMeasurementData_t *pRangingMeasurementData)
+{
+	VL53L0X_Error Status = VL53L0X_ERROR_NONE;
+	uint8_t DeviceRangeStatus;
+	uint8_t RangeFractionalEnable;
+	uint8_t PalRangeStatus;
+	uint8_t XTalkCompensationEnable;
+	uint16_t AmbientRate;
+	FixPoint1616_t SignalRate;
+	uint16_t XTalkCompensationRateMegaCps;
+	uint16_t EffectiveSpadRtnCount;
+	uint16_t tmpuint16;
+	uint16_t XtalkRangeMilliMeter;
+	uint16_t LinearityCorrectiveGain;
+	uint8_t localBuffer[12];
+	VL53L0X_RangingMeasurementData_t LastRangeDataBuffer;
+
+	LOG_FUNCTION_START("");
+
+	/*
+	 * use multi read even if some registers are not useful, result will
+	 * be more efficient
+	 * start reading at 0x14 dec20
+	 * end reading at 0x21 dec33 total 14 bytes to read
+	 */
+	Status = VL53L0X_ReadMulti(Dev, 0x14, localBuffer, 12);
+
+	if (Status == VL53L0X_ERROR_NONE) {
+
+		pRangingMeasurementData->ZoneId = 0; /* Only one zone */
+		pRangingMeasurementData->TimeStamp = 0; /* Not Implemented */
+
+		tmpuint16 = VL53L0X_MAKEUINT16(localBuffer[11], localBuffer[10]);
+		/* cut1.1 if SYSTEM__RANGE_CONFIG if 1 range is 2bits fractional
+		 *(format 11.2) else no fractional
+		 */
+
+		pRangingMeasurementData->MeasurementTimeUsec = 0;
+
+		SignalRate = VL53L0X_FIXPOINT97TOFIXPOINT1616(
+			VL53L0X_MAKEUINT16(localBuffer[7], localBuffer[6]));
+		/* peak_signal_count_rate_rtn_mcps */
+		pRangingMeasurementData->SignalRateRtnMegaCps = SignalRate;
+
+		AmbientRate = VL53L0X_MAKEUINT16(localBuffer[9], localBuffer[8]);
+		pRangingMeasurementData->AmbientRateRtnMegaCps =
+			VL53L0X_FIXPOINT97TOFIXPOINT1616(AmbientRate);
+
+		EffectiveSpadRtnCount = VL53L0X_MAKEUINT16(localBuffer[3],
+			localBuffer[2]);
+		/* EffectiveSpadRtnCount is 8.8 format */
+		pRangingMeasurementData->EffectiveSpadRtnCount =
+			EffectiveSpadRtnCount;
+
+		DeviceRangeStatus = localBuffer[0];
+
+		/* Get Linearity Corrective Gain */
+		LinearityCorrectiveGain = PALDevDataGet(Dev,
+			LinearityCorrectiveGain);
+
+		/* Get ranging configuration */
+		RangeFractionalEnable = PALDevDataGet(Dev,
+			RangeFractionalEnable);
+
+		if (LinearityCorrectiveGain != 1000) {
+
+			tmpuint16 = (uint16_t)((LinearityCorrectiveGain
+				* tmpuint16 + 500) / 1000);
+
+			/* Implement Xtalk */
+			VL53L0X_GETPARAMETERFIELD(Dev,
+				XTalkCompensationRateMegaCps,
+				XTalkCompensationRateMegaCps);
+			VL53L0X_GETPARAMETERFIELD(Dev, XTalkCompensationEnable,
+				XTalkCompensationEnable);
+
+			if (XTalkCompensationEnable) {
+
+				if ((SignalRate
+					- ((XTalkCompensationRateMegaCps
+					* EffectiveSpadRtnCount) >> 8))
+					<= 0) {
+					if (RangeFractionalEnable)
+						XtalkRangeMilliMeter = 8888;
+					else
+						XtalkRangeMilliMeter = 8888
+							<< 2;
+				} else {
+					XtalkRangeMilliMeter =
+					(tmpuint16 * SignalRate)
+						/ (SignalRate
+						- ((XTalkCompensationRateMegaCps
+						* EffectiveSpadRtnCount)
+						>> 8));
+				}
+
+				tmpuint16 = XtalkRangeMilliMeter;
+			}
+
+		}
+
+		if (RangeFractionalEnable) {
+			pRangingMeasurementData->RangeMilliMeter =
+				(uint16_t)((tmpuint16) >> 2);
+			pRangingMeasurementData->RangeFractionalPart =
+				(uint8_t)((tmpuint16 & 0x03) << 6);
+		} else {
+			pRangingMeasurementData->RangeMilliMeter = tmpuint16;
+			pRangingMeasurementData->RangeFractionalPart = 0;
+		}
+
+		/*
+		 * For a standard definition of RangeStatus, this should
+		 * return 0 in case of good result after a ranging
+		 * The range status depends on the device so call a device
+		 * specific function to obtain the right Status.
+		 */
+		Status |= VL53L0X_get_pal_range_status(Dev, DeviceRangeStatus,
+			SignalRate, EffectiveSpadRtnCount,
+			pRangingMeasurementData, &PalRangeStatus);
+
+		if (Status == VL53L0X_ERROR_NONE)
+			pRangingMeasurementData->RangeStatus = PalRangeStatus;
+
+	}
+
+	if (Status == VL53L0X_ERROR_NONE) {
+		/* Copy last read data into Dev buffer */
+		LastRangeDataBuffer = PALDevDataGet(Dev, LastRangeMeasure);
+
+		LastRangeDataBuffer.RangeMilliMeter =
+			pRangingMeasurementData->RangeMilliMeter;
+		LastRangeDataBuffer.RangeFractionalPart =
+			pRangingMeasurementData->RangeFractionalPart;
+		LastRangeDataBuffer.RangeDMaxMilliMeter =
+			pRangingMeasurementData->RangeDMaxMilliMeter;
+		LastRangeDataBuffer.MeasurementTimeUsec =
+			pRangingMeasurementData->MeasurementTimeUsec;
+		LastRangeDataBuffer.SignalRateRtnMegaCps =
+			pRangingMeasurementData->SignalRateRtnMegaCps;
+		LastRangeDataBuffer.AmbientRateRtnMegaCps =
+			pRangingMeasurementData->AmbientRateRtnMegaCps;
+		LastRangeDataBuffer.EffectiveSpadRtnCount =
+			pRangingMeasurementData->EffectiveSpadRtnCount;
+		LastRangeDataBuffer.RangeStatus =
+			pRangingMeasurementData->RangeStatus;
+
+		PALDevDataSet(Dev, LastRangeMeasure, LastRangeDataBuffer);
+	}
+
+	LOG_FUNCTION_END(Status);
+	return Status;
+}
+
+VL53L0X_Error VL53L0X_GetMeasurementRefSignal(VL53L0X_DEV Dev,
+	FixPoint1616_t *pMeasurementRefSignal)
+{
+	VL53L0X_Error Status = VL53L0X_ERROR_NONE;
+	LOG_FUNCTION_START("");
+
+	*pMeasurementRefSignal = PALDevDataGet(Dev, LastSignalRefMcps);
+
+	LOG_FUNCTION_END(Status);
+	return Status;
+
+}
+
+VL53L0X_Error VL53L0X_GetHistogramMeasurementData(VL53L0X_DEV Dev,
+	VL53L0X_HistogramMeasurementData_t *pHistogramMeasurementData)
+{
+	VL53L0X_Error Status = VL53L0X_ERROR_NOT_IMPLEMENTED;
+	LOG_FUNCTION_START("");
+
+	LOG_FUNCTION_END(Status);
+	return Status;
+}
+
+VL53L0X_Error VL53L0X_PerformSingleRangingMeasurement(VL53L0X_DEV Dev,
+	VL53L0X_RangingMeasurementData_t *pRangingMeasurementData)
+{
+	VL53L0X_Error Status = VL53L0X_ERROR_NONE;
+
+	LOG_FUNCTION_START("");
+
+	/* This function will do a complete single ranging
+	 * Here we fix the mode! */
+	Status = VL53L0X_SetDeviceMode(Dev, VL53L0X_DEVICEMODE_SINGLE_RANGING);
+
+	if (Status == VL53L0X_ERROR_NONE)
+		Status = VL53L0X_PerformSingleMeasurement(Dev);
+
+	if (Status == VL53L0X_ERROR_NONE)
+		Status = VL53L0X_GetRangingMeasurementData(Dev,
+			pRangingMeasurementData);
+
+
+	if (Status == VL53L0X_ERROR_NONE)
+		Status = VL53L0X_ClearInterruptMask(Dev, 0);
+
+
+	LOG_FUNCTION_END(Status);
+	return Status;
+}
+
+VL53L0X_Error VL53L0X_SetNumberOfROIZones(VL53L0X_DEV Dev,
+	uint8_t NumberOfROIZones)
+{
+	VL53L0X_Error Status = VL53L0X_ERROR_NONE;
+
+	LOG_FUNCTION_START("");
+
+	if (NumberOfROIZones != 1)
+		Status = VL53L0X_ERROR_INVALID_PARAMS;
+
+
+	LOG_FUNCTION_END(Status);
+	return Status;
+}
+
+VL53L0X_Error VL53L0X_GetNumberOfROIZones(VL53L0X_DEV Dev,
+	uint8_t *pNumberOfROIZones)
+{
+	VL53L0X_Error Status = VL53L0X_ERROR_NONE;
+
+	LOG_FUNCTION_START("");
+
+	*pNumberOfROIZones = 1;
+
+	LOG_FUNCTION_END(Status);
+	return Status;
+}
+
+VL53L0X_Error VL53L0X_GetMaxNumberOfROIZones(VL53L0X_DEV Dev,
+	uint8_t *pMaxNumberOfROIZones)
+{
+	VL53L0X_Error Status = VL53L0X_ERROR_NONE;
+
+	LOG_FUNCTION_START("");
+
+	*pMaxNumberOfROIZones = 1;
+
+	LOG_FUNCTION_END(Status);
+	return Status;
+}
+
+/* End Group PAL Measurement Functions */
+
+VL53L0X_Error VL53L0X_SetGpioConfig(VL53L0X_DEV Dev, uint8_t Pin,
+	VL53L0X_DeviceModes DeviceMode, VL53L0X_GpioFunctionality Functionality,
+	VL53L0X_InterruptPolarity Polarity)
+{
+	VL53L0X_Error Status = VL53L0X_ERROR_NONE;
+	uint8_t data;
+
+	LOG_FUNCTION_START("");
+
+	if (Pin != 0) {
+		Status = VL53L0X_ERROR_GPIO_NOT_EXISTING;
+	} else if (DeviceMode == VL53L0X_DEVICEMODE_GPIO_DRIVE) {
+		if (Polarity == VL53L0X_INTERRUPTPOLARITY_LOW)
+			data = 0x10;
+		else
+			data = 1;
+
+		Status = VL53L0X_WrByte(Dev,
+		VL53L0X_REG_GPIO_HV_MUX_ACTIVE_HIGH, data);
+
+	} else if (DeviceMode == VL53L0X_DEVICEMODE_GPIO_OSC) {
+
+		Status |= VL53L0X_WrByte(Dev, 0xff, 0x01);
+		Status |= VL53L0X_WrByte(Dev, 0x00, 0x00);
+
+		Status |= VL53L0X_WrByte(Dev, 0xff, 0x00);
+		Status |= VL53L0X_WrByte(Dev, 0x80, 0x01);
+		Status |= VL53L0X_WrByte(Dev, 0x85, 0x02);
+
+		Status |= VL53L0X_WrByte(Dev, 0xff, 0x04);
+		Status |= VL53L0X_WrByte(Dev, 0xcd, 0x00);
+		Status |= VL53L0X_WrByte(Dev, 0xcc, 0x11);
+
+		Status |= VL53L0X_WrByte(Dev, 0xff, 0x07);
+		Status |= VL53L0X_WrByte(Dev, 0xbe, 0x00);
+
+		Status |= VL53L0X_WrByte(Dev, 0xff, 0x06);
+		Status |= VL53L0X_WrByte(Dev, 0xcc, 0x09);
+
+		Status |= VL53L0X_WrByte(Dev, 0xff, 0x00);
+		Status |= VL53L0X_WrByte(Dev, 0xff, 0x01);
+		Status |= VL53L0X_WrByte(Dev, 0x00, 0x00);
+
+	} else {
+
+		if (Status == VL53L0X_ERROR_NONE) {
+			switch (Functionality) {
+			case VL53L0X_GPIOFUNCTIONALITY_OFF:
+				data = 0x00;
+				break;
+			case VL53L0X_GPIOFUNCTIONALITY_THRESHOLD_CROSSED_LOW:
+				data = 0x01;
+				break;
+			case VL53L0X_GPIOFUNCTIONALITY_THRESHOLD_CROSSED_HIGH:
+				data = 0x02;
+				break;
+			case VL53L0X_GPIOFUNCTIONALITY_THRESHOLD_CROSSED_OUT:
+				data = 0x03;
+				break;
+			case VL53L0X_GPIOFUNCTIONALITY_NEW_MEASURE_READY:
+				data = 0x04;
+				break;
+			default:
+				Status =
+				VL53L0X_ERROR_GPIO_FUNCTIONALITY_NOT_SUPPORTED;
+			}
+		}
+
+		if (Status == VL53L0X_ERROR_NONE)
+			Status = VL53L0X_WrByte(Dev,
+			VL53L0X_REG_SYSTEM_INTERRUPT_CONFIG_GPIO, data);
+
+		if (Status == VL53L0X_ERROR_NONE) {
+			if (Polarity == VL53L0X_INTERRUPTPOLARITY_LOW)
+				data = 0;
+			else
+				data = (uint8_t)(1 << 4);
+
+			Status = VL53L0X_UpdateByte(Dev,
+			VL53L0X_REG_GPIO_HV_MUX_ACTIVE_HIGH, 0xEF, data);
+		}
+
+		if (Status == VL53L0X_ERROR_NONE)
+			VL53L0X_SETDEVICESPECIFICPARAMETER(Dev,
+				Pin0GpioFunctionality, Functionality);
+
+		if (Status == VL53L0X_ERROR_NONE)
+			Status = VL53L0X_ClearInterruptMask(Dev, 0);
+
+	}
+
+	LOG_FUNCTION_END(Status);
+	return Status;
+}
+
+VL53L0X_Error VL53L0X_GetGpioConfig(VL53L0X_DEV Dev, uint8_t Pin,
+	VL53L0X_DeviceModes *pDeviceMode,
+	VL53L0X_GpioFunctionality *pFunctionality,
+	VL53L0X_InterruptPolarity *pPolarity)
+{
+	VL53L0X_Error Status = VL53L0X_ERROR_NONE;
+	VL53L0X_GpioFunctionality GpioFunctionality;
+	uint8_t data;
+
+	LOG_FUNCTION_START("");
+
+	/* pDeviceMode not managed by Ewok it return the current mode */
+
+	Status = VL53L0X_GetDeviceMode(Dev, pDeviceMode);
+
+	if (Status == VL53L0X_ERROR_NONE) {
+		if (Pin != 0) {
+			Status = VL53L0X_ERROR_GPIO_NOT_EXISTING;
+		} else {
+			Status = VL53L0X_RdByte(Dev,
+			VL53L0X_REG_SYSTEM_INTERRUPT_CONFIG_GPIO, &data);
+		}
+	}
+
+	if (Status == VL53L0X_ERROR_NONE) {
+		switch (data & 0x07) {
+		case 0x00:
+			GpioFunctionality = VL53L0X_GPIOFUNCTIONALITY_OFF;
+			break;
+		case 0x01:
+			GpioFunctionality =
+			VL53L0X_GPIOFUNCTIONALITY_THRESHOLD_CROSSED_LOW;
+			break;
+		case 0x02:
+			GpioFunctionality =
+			VL53L0X_GPIOFUNCTIONALITY_THRESHOLD_CROSSED_HIGH;
+			break;
+		case 0x03:
+			GpioFunctionality =
+			VL53L0X_GPIOFUNCTIONALITY_THRESHOLD_CROSSED_OUT;
+			break;
+		case 0x04:
+			GpioFunctionality =
+			VL53L0X_GPIOFUNCTIONALITY_NEW_MEASURE_READY;
+			break;
+		default:
+			Status = VL53L0X_ERROR_GPIO_FUNCTIONALITY_NOT_SUPPORTED;
+		}
+	}
+
+	if (Status == VL53L0X_ERROR_NONE)
+		Status = VL53L0X_RdByte(Dev, VL53L0X_REG_GPIO_HV_MUX_ACTIVE_HIGH,
+			&data);
+
+	if (Status == VL53L0X_ERROR_NONE) {
+		if ((data & (uint8_t)(1 << 4)) == 0)
+			*pPolarity = VL53L0X_INTERRUPTPOLARITY_LOW;
+		else
+			*pPolarity = VL53L0X_INTERRUPTPOLARITY_HIGH;
+	}
+
+	if (Status == VL53L0X_ERROR_NONE) {
+		*pFunctionality = GpioFunctionality;
+		VL53L0X_SETDEVICESPECIFICPARAMETER(Dev, Pin0GpioFunctionality,
+			GpioFunctionality);
+	}
+
+	LOG_FUNCTION_END(Status);
+	return Status;
+}
+
+VL53L0X_Error VL53L0X_SetInterruptThresholds(VL53L0X_DEV Dev,
+	VL53L0X_DeviceModes DeviceMode, FixPoint1616_t ThresholdLow,
+	FixPoint1616_t ThresholdHigh)
+{
+	VL53L0X_Error Status = VL53L0X_ERROR_NONE;
+	uint16_t Threshold16;
+	LOG_FUNCTION_START("");
+
+	/* no dependency on DeviceMode for Ewok */
+	/* Need to divide by 2 because the FW will apply a x2 */
+	Threshold16 = (uint16_t)((ThresholdLow >> 17) & 0x00fff);
+	Status = VL53L0X_WrWord(Dev, VL53L0X_REG_SYSTEM_THRESH_LOW, Threshold16);
+
+	if (Status == VL53L0X_ERROR_NONE) {
+		/* Need to divide by 2 because the FW will apply a x2 */
+		Threshold16 = (uint16_t)((ThresholdHigh >> 17) & 0x00fff);
+		Status = VL53L0X_WrWord(Dev, VL53L0X_REG_SYSTEM_THRESH_HIGH,
+			Threshold16);
+	}
+
+	LOG_FUNCTION_END(Status);
+	return Status;
+}
+
+VL53L0X_Error VL53L0X_GetInterruptThresholds(VL53L0X_DEV Dev,
+	VL53L0X_DeviceModes DeviceMode, FixPoint1616_t *pThresholdLow,
+	FixPoint1616_t *pThresholdHigh)
+{
+	VL53L0X_Error Status = VL53L0X_ERROR_NONE;
+	uint16_t Threshold16;
+	LOG_FUNCTION_START("");
+
+	/* no dependency on DeviceMode for Ewok */
+
+	Status = VL53L0X_RdWord(Dev, VL53L0X_REG_SYSTEM_THRESH_LOW, &Threshold16);
+	/* Need to multiply by 2 because the FW will apply a x2 */
+	*pThresholdLow = (FixPoint1616_t)((0x00fff & Threshold16) << 17);
+
+	if (Status == VL53L0X_ERROR_NONE) {
+		Status = VL53L0X_RdWord(Dev, VL53L0X_REG_SYSTEM_THRESH_HIGH,
+			&Threshold16);
+		/* Need to multiply by 2 because the FW will apply a x2 */
+		*pThresholdHigh =
+			(FixPoint1616_t)((0x00fff & Threshold16) << 17);
+	}
+
+	LOG_FUNCTION_END(Status);
+	return Status;
+}
+
+VL53L0X_Error VL53L0X_GetStopCompletedStatus(VL53L0X_DEV Dev,
+	uint32_t *pStopStatus)
+{
+	VL53L0X_Error Status = VL53L0X_ERROR_NONE;
+	uint8_t Byte = 0;
+	LOG_FUNCTION_START("");
+
+	Status = VL53L0X_WrByte(Dev, 0xFF, 0x01);
+
+	if (Status == VL53L0X_ERROR_NONE)
+		Status = VL53L0X_RdByte(Dev, 0x04, &Byte);
+
+	if (Status == VL53L0X_ERROR_NONE)
+		Status = VL53L0X_WrByte(Dev, 0xFF, 0x0);
+
+	*pStopStatus = Byte;
+	
+	if (Byte == 0) {
+		Status = VL53L0X_WrByte(Dev, 0x80, 0x01);
+		Status = VL53L0X_WrByte(Dev, 0xFF, 0x01);
+		Status = VL53L0X_WrByte(Dev, 0x00, 0x00);
+		Status = VL53L0X_WrByte(Dev, 0x91,
+			PALDevDataGet(Dev, StopVariable));
+		Status = VL53L0X_WrByte(Dev, 0x00, 0x01);
+		Status = VL53L0X_WrByte(Dev, 0xFF, 0x00);
+		Status = VL53L0X_WrByte(Dev, 0x80, 0x00);
+	}
+
+	LOG_FUNCTION_END(Status);
+	return Status;
+}
+
+/* Group PAL Interrupt Functions */
+VL53L0X_Error VL53L0X_ClearInterruptMask(VL53L0X_DEV Dev, uint32_t InterruptMask)
+{
+	VL53L0X_Error Status = VL53L0X_ERROR_NONE;
+	uint8_t LoopCount;
+	uint8_t Byte;
+	LOG_FUNCTION_START("");
+
+	/* clear bit 0 range interrupt, bit 1 error interrupt */
+	LoopCount = 0;
+	do {
+		Status = VL53L0X_WrByte(Dev,
+			VL53L0X_REG_SYSTEM_INTERRUPT_CLEAR, 0x01);
+		Status |= VL53L0X_WrByte(Dev,
+			VL53L0X_REG_SYSTEM_INTERRUPT_CLEAR, 0x00);
+		Status |= VL53L0X_RdByte(Dev,
+			VL53L0X_REG_RESULT_INTERRUPT_STATUS, &Byte);
+		LoopCount++;
+	} while (((Byte & 0x07) != 0x00)
+			&& (LoopCount < 3)
+			&& (Status == VL53L0X_ERROR_NONE));
+
+
+	if (LoopCount >= 3)
+		Status = VL53L0X_ERROR_INTERRUPT_NOT_CLEARED;
+
+	LOG_FUNCTION_END(Status);
+	return Status;
+}
+
+VL53L0X_Error VL53L0X_GetInterruptMaskStatus(VL53L0X_DEV Dev,
+	uint32_t *pInterruptMaskStatus)
+{
+	VL53L0X_Error Status = VL53L0X_ERROR_NONE;
+	uint8_t Byte;
+	LOG_FUNCTION_START("");
+
+	Status = VL53L0X_RdByte(Dev, VL53L0X_REG_RESULT_INTERRUPT_STATUS, &Byte);
+	*pInterruptMaskStatus = Byte & 0x07;
+
+	if (Byte & 0x18)
+		Status = VL53L0X_ERROR_RANGE_ERROR;
+
+	LOG_FUNCTION_END(Status);
+	return Status;
+}
+
+VL53L0X_Error VL53L0X_EnableInterruptMask(VL53L0X_DEV Dev, uint32_t InterruptMask)
+{
+	VL53L0X_Error Status = VL53L0X_ERROR_NOT_IMPLEMENTED;
+	LOG_FUNCTION_START("");
+
+	/* not implemented for VL53L0X */
+
+	LOG_FUNCTION_END(Status);
+	return Status;
+}
+
+/* End Group PAL Interrupt Functions */
+
+/* Group SPAD functions */
+
+VL53L0X_Error VL53L0X_SetSpadAmbientDamperThreshold(VL53L0X_DEV Dev,
+	uint16_t SpadAmbientDamperThreshold)
+{
+	VL53L0X_Error Status = VL53L0X_ERROR_NONE;
+	LOG_FUNCTION_START("");
+
+	Status = VL53L0X_WrByte(Dev, 0xFF, 0x01);
+	Status |= VL53L0X_WrWord(Dev, 0x40, SpadAmbientDamperThreshold);
+	Status |= VL53L0X_WrByte(Dev, 0xFF, 0x00);
+
+	LOG_FUNCTION_END(Status);
+	return Status;
+}
+
+VL53L0X_Error VL53L0X_GetSpadAmbientDamperThreshold(VL53L0X_DEV Dev,
+	uint16_t *pSpadAmbientDamperThreshold)
+{
+	VL53L0X_Error Status = VL53L0X_ERROR_NONE;
+	LOG_FUNCTION_START("");
+
+	Status = VL53L0X_WrByte(Dev, 0xFF, 0x01);
+	Status |= VL53L0X_RdWord(Dev, 0x40, pSpadAmbientDamperThreshold);
+	Status |= VL53L0X_WrByte(Dev, 0xFF, 0x00);
+
+	LOG_FUNCTION_END(Status);
+	return Status;
+}
+
+VL53L0X_Error VL53L0X_SetSpadAmbientDamperFactor(VL53L0X_DEV Dev,
+	uint16_t SpadAmbientDamperFactor)
+{
+	VL53L0X_Error Status = VL53L0X_ERROR_NONE;
+	uint8_t Byte;
+	LOG_FUNCTION_START("");
+
+	Byte = (uint8_t)(SpadAmbientDamperFactor & 0x00FF);
+
+	Status = VL53L0X_WrByte(Dev, 0xFF, 0x01);
+	Status |= VL53L0X_WrByte(Dev, 0x42, Byte);
+	Status |= VL53L0X_WrByte(Dev, 0xFF, 0x00);
+
+	LOG_FUNCTION_END(Status);
+	return Status;
+}
+
+VL53L0X_Error VL53L0X_GetSpadAmbientDamperFactor(VL53L0X_DEV Dev,
+	uint16_t *pSpadAmbientDamperFactor)
+{
+	VL53L0X_Error Status = VL53L0X_ERROR_NONE;
+	uint8_t Byte;
+	LOG_FUNCTION_START("");
+
+	Status = VL53L0X_WrByte(Dev, 0xFF, 0x01);
+	Status |= VL53L0X_RdByte(Dev, 0x42, &Byte);
+	Status |= VL53L0X_WrByte(Dev, 0xFF, 0x00);
+	*pSpadAmbientDamperFactor = (uint16_t)Byte;
+
+	LOG_FUNCTION_END(Status);
+	return Status;
+}
+
+/* END Group SPAD functions */
+
+/*****************************************************************************
+ * Internal functions
+ *****************************************************************************/
+
+VL53L0X_Error VL53L0X_SetReferenceSpads(VL53L0X_DEV Dev, uint32_t count,
+	uint8_t isApertureSpads)
+{
+	VL53L0X_Error Status = VL53L0X_ERROR_NONE;
+	LOG_FUNCTION_START("");
+
+	Status = VL53L0X_set_reference_spads(Dev, count, isApertureSpads);
+
+	LOG_FUNCTION_END(Status);
+
+	return Status;
+}
+
+VL53L0X_Error VL53L0X_GetReferenceSpads(VL53L0X_DEV Dev, uint32_t *pSpadCount,
+	uint8_t *pIsApertureSpads)
+{
+	VL53L0X_Error Status = VL53L0X_ERROR_NONE;
+	LOG_FUNCTION_START("");
+
+	Status = VL53L0X_get_reference_spads(Dev, pSpadCount, pIsApertureSpads);
+
+	LOG_FUNCTION_END(Status);
+
+	return Status;
+}
+
+VL53L0X_Error VL53L0X_PerformRefSpadManagement(VL53L0X_DEV Dev,
+	uint32_t *refSpadCount, uint8_t *isApertureSpads)
+{
+	VL53L0X_Error Status = VL53L0X_ERROR_NONE;
+	LOG_FUNCTION_START("");
+
+	Status = VL53L0X_perform_ref_spad_management(Dev, refSpadCount,
+		isApertureSpads);
+
+	LOG_FUNCTION_END(Status);
+
+	return Status;
+}
+
+/******************************************************calibration*******************************************************/
+/******************************************************calibration*******************************************************/
+/******************************************************calibration*******************************************************/
+
+
+
+
+VL53L0X_Error VL53L0X_perform_xtalk_calibration(VL53L0X_DEV Dev,
+			FixPoint1616_t XTalkCalDistance,
+			FixPoint1616_t *pXTalkCompensationRateMegaCps)
+{
+	VL53L0X_Error Status = VL53L0X_ERROR_NONE;
+	uint16_t sum_ranging = 0;
+	uint16_t sum_spads = 0;
+	FixPoint1616_t sum_signalRate = 0;
+	FixPoint1616_t total_count = 0;
+	uint8_t xtalk_meas = 0;
+	VL53L0X_RangingMeasurementData_t RangingMeasurementData;
+	FixPoint1616_t xTalkStoredMeanSignalRate;
+	FixPoint1616_t xTalkStoredMeanRange;
+	FixPoint1616_t xTalkStoredMeanRtnSpads;
+	uint32_t signalXTalkTotalPerSpad;
+	uint32_t xTalkStoredMeanRtnSpadsAsInt;
+	uint32_t xTalkCalDistanceAsInt;
+	FixPoint1616_t XTalkCompensationRateMegaCps;
+
+	if (XTalkCalDistance <= 0)
+		Status = VL53L0X_ERROR_INVALID_PARAMS;
+
+	/* Disable the XTalk compensation */
+	if (Status == VL53L0X_ERROR_NONE)
+		Status = VL53L0X_SetXTalkCompensationEnable(Dev, 0);
+
+	/* Disable the RIT */
+	if (Status == VL53L0X_ERROR_NONE) {
+		Status = VL53L0X_SetLimitCheckEnable(Dev,
+				VL53L0X_CHECKENABLE_RANGE_IGNORE_THRESHOLD, 0);
+	}
+
+	/* Perform 50 measurements and compute the averages */
+	if (Status == VL53L0X_ERROR_NONE) {
+		sum_ranging = 0;
+		sum_spads = 0;
+		sum_signalRate = 0;
+		total_count = 0;
+		for (xtalk_meas = 0; xtalk_meas < 50; xtalk_meas++) {
+			Status = VL53L0X_PerformSingleRangingMeasurement(Dev,
+				&RangingMeasurementData);
+
+			if (Status != VL53L0X_ERROR_NONE)
+				break;
+
+			/* The range is valid when RangeStatus = 0 */
+			if (RangingMeasurementData.RangeStatus == 0) {
+				sum_ranging = sum_ranging +
+					RangingMeasurementData.RangeMilliMeter;
+				sum_signalRate = sum_signalRate +
+				RangingMeasurementData.SignalRateRtnMegaCps;
+				sum_spads = sum_spads +
+				RangingMeasurementData.EffectiveSpadRtnCount
+					/ 256;
+				total_count = total_count + 1;
+			}
+		}
+
+		/* no valid values found */
+		if (total_count == 0)
+			Status = VL53L0X_ERROR_RANGE_ERROR;
+
+	}
+
+
+	if (Status == VL53L0X_ERROR_NONE) {
+		/* FixPoint1616_t / uint16_t = FixPoint1616_t */
+		xTalkStoredMeanSignalRate = sum_signalRate / total_count;
+		xTalkStoredMeanRange = (FixPoint1616_t)((uint32_t)(
+			sum_ranging << 16) / total_count);
+		xTalkStoredMeanRtnSpads = (FixPoint1616_t)((uint32_t)(
+			sum_spads << 16) / total_count);
+
+		/* Round Mean Spads to Whole Number.
+		 * Typically the calculated mean SPAD count is a whole number
+		 * or very close to a whole
+		 * number, therefore any truncation will not result in a
+		 * significant loss in accuracy.
+		 * Also, for a grey target at a typical distance of around
+		 * 400mm, around 220 SPADs will
+		 * be enabled, therefore, any truncation will result in a loss
+		 * of accuracy of less than
+		 * 0.5%.
+		 */
+		xTalkStoredMeanRtnSpadsAsInt = (xTalkStoredMeanRtnSpads +
+			0x8000) >> 16;
+
+		/* Round Cal Distance to Whole Number.
+		 * Note that the cal distance is in mm, therefore no resolution
+		 * is lost.*/
+		 xTalkCalDistanceAsInt = (XTalkCalDistance + 0x8000) >> 16;
+
+		if (xTalkStoredMeanRtnSpadsAsInt == 0 ||
+		   xTalkCalDistanceAsInt == 0 ||
+		   xTalkStoredMeanRange >= XTalkCalDistance) {
+			XTalkCompensationRateMegaCps = 0;
+		} else {
+			/* Round Cal Distance to Whole Number.
+			   Note that the cal distance is in mm, therefore no
+			   resolution is lost.*/
+			xTalkCalDistanceAsInt = (XTalkCalDistance +
+				0x8000) >> 16;
+
+			/* Apply division by mean spad count early in the
+			 * calculation to keep the numbers small.
+			 * This ensures we can maintain a 32bit calculation.
+			 * Fixed1616 / int := Fixed1616 */
+			signalXTalkTotalPerSpad = (xTalkStoredMeanSignalRate) /
+				xTalkStoredMeanRtnSpadsAsInt;
+
+			/* Complete the calculation for total Signal XTalk per
+			 * SPAD
+			 * Fixed1616 * (Fixed1616 - Fixed1616/int) :=
+			 * (2^16 * Fixed1616)
+			 */
+			signalXTalkTotalPerSpad *= ((1 << 16) -
+				(xTalkStoredMeanRange / xTalkCalDistanceAsInt));
+
+			/* Round from 2^16 * Fixed1616, to Fixed1616. */
+			XTalkCompensationRateMegaCps = (signalXTalkTotalPerSpad
+				+ 0x8000) >> 16;
+		}
+
+		*pXTalkCompensationRateMegaCps = XTalkCompensationRateMegaCps;
+
+		/* Enable the XTalk compensation */
+		if (Status == VL53L0X_ERROR_NONE)
+			Status = VL53L0X_SetXTalkCompensationEnable(Dev, 1);
+
+		/* Enable the XTalk compensation */
+		if (Status == VL53L0X_ERROR_NONE)
+			Status = VL53L0X_SetXTalkCompensationRateMegaCps(Dev,
+					XTalkCompensationRateMegaCps);
+
+	}
+
+	return Status;
+}
+
+VL53L0X_Error VL53L0X_perform_offset_calibration(VL53L0X_DEV Dev,
+			FixPoint1616_t CalDistanceMilliMeter,
+			int32_t *pOffsetMicroMeter)
+{
+	VL53L0X_Error Status = VL53L0X_ERROR_NONE;
+	uint16_t sum_ranging = 0;
+	FixPoint1616_t total_count = 0;
+	VL53L0X_RangingMeasurementData_t RangingMeasurementData;
+	FixPoint1616_t StoredMeanRange;
+	uint32_t StoredMeanRangeAsInt;
+	uint32_t CalDistanceAsInt_mm;
+	uint8_t SequenceStepEnabled;
+	int meas = 0;
+
+	if (CalDistanceMilliMeter <= 0)
+		Status = VL53L0X_ERROR_INVALID_PARAMS;
+
+	if (Status == VL53L0X_ERROR_NONE)
+		Status = VL53L0X_SetOffsetCalibrationDataMicroMeter(Dev, 0);
+
+
+	/* Get the value of the TCC */
+	if (Status == VL53L0X_ERROR_NONE)
+		Status = VL53L0X_GetSequenceStepEnable(Dev,
+				VL53L0X_SEQUENCESTEP_TCC, &SequenceStepEnabled);
+
+
+	/* Disable the TCC */
+	if (Status == VL53L0X_ERROR_NONE)
+		Status = VL53L0X_SetSequenceStepEnable(Dev,
+				VL53L0X_SEQUENCESTEP_TCC, 0);
+
+
+	/* Disable the RIT */
+	if (Status == VL53L0X_ERROR_NONE)
+		Status = VL53L0X_SetLimitCheckEnable(Dev,
+				VL53L0X_CHECKENABLE_RANGE_IGNORE_THRESHOLD, 0);
+
+	/* Perform 50 measurements and compute the averages */
+	if (Status == VL53L0X_ERROR_NONE) {
+		sum_ranging = 0;
+		total_count = 0;
+		for (meas = 0; meas < 50; meas++) {
+			Status = VL53L0X_PerformSingleRangingMeasurement(Dev,
+					&RangingMeasurementData);
+
+			if (Status != VL53L0X_ERROR_NONE)
+				break;
+
+			/* The range is valid when RangeStatus = 0 */
+			if (RangingMeasurementData.RangeStatus == 0) {
+				sum_ranging = sum_ranging +
+					RangingMeasurementData.RangeMilliMeter;
+				total_count = total_count + 1;
+			}
+		}
+
+		/* no valid values found */
+		if (total_count == 0)
+			Status = VL53L0X_ERROR_RANGE_ERROR;
+	}
+
+
+	if (Status == VL53L0X_ERROR_NONE) {
+		/* FixPoint1616_t / uint16_t = FixPoint1616_t */
+		StoredMeanRange = (FixPoint1616_t)((uint32_t)(sum_ranging << 16)
+			/ total_count);
+
+		StoredMeanRangeAsInt = (StoredMeanRange + 0x8000) >> 16;
+
+		/* Round Cal Distance to Whole Number.
+		 * Note that the cal distance is in mm, therefore no resolution
+		 * is lost.*/
+		 CalDistanceAsInt_mm = (CalDistanceMilliMeter + 0x8000) >> 16;
+
+		 *pOffsetMicroMeter = (CalDistanceAsInt_mm -
+				 StoredMeanRangeAsInt) * 1000;
+
+		/* Apply the calculated offset */
+		if (Status == VL53L0X_ERROR_NONE) {
+			VL53L0X_SETPARAMETERFIELD(Dev, RangeOffsetMicroMeters,
+					*pOffsetMicroMeter);
+			Status = VL53L0X_SetOffsetCalibrationDataMicroMeter(Dev,
+					*pOffsetMicroMeter);
+		}
+
+	}
+
+	/* Restore the TCC */
+	if (Status == VL53L0X_ERROR_NONE) {
+		if (SequenceStepEnabled != 0)
+			Status = VL53L0X_SetSequenceStepEnable(Dev,
+					VL53L0X_SEQUENCESTEP_TCC, 1);
+	}
+
+	return Status;
+}
+
+
+VL53L0X_Error VL53L0X_set_offset_calibration_data_micro_meter(VL53L0X_DEV Dev,
+		int32_t OffsetCalibrationDataMicroMeter)
+{
+	VL53L0X_Error Status = VL53L0X_ERROR_NONE;
+	int32_t cMaxOffsetMicroMeter = 511000;
+	int32_t cMinOffsetMicroMeter = -512000;
+	int16_t cOffsetRange = 4096;
+	uint32_t encodedOffsetVal;
+
+	LOG_FUNCTION_START("");
+
+	if (OffsetCalibrationDataMicroMeter > cMaxOffsetMicroMeter)
+		OffsetCalibrationDataMicroMeter = cMaxOffsetMicroMeter;
+	else if (OffsetCalibrationDataMicroMeter < cMinOffsetMicroMeter)
+		OffsetCalibrationDataMicroMeter = cMinOffsetMicroMeter;
+
+	/* The offset register is 10.2 format and units are mm
+	 * therefore conversion is applied by a division of
+	 * 250.
+	 */
+	if (OffsetCalibrationDataMicroMeter >= 0) {
+		encodedOffsetVal =
+			OffsetCalibrationDataMicroMeter/250;
+	} else {
+		encodedOffsetVal =
+			cOffsetRange +
+			OffsetCalibrationDataMicroMeter/250;
+	}
+
+	Status = VL53L0X_WrWord(Dev,
+		VL53L0X_REG_ALGO_PART_TO_PART_RANGE_OFFSET_MM,
+		encodedOffsetVal);
+
+	LOG_FUNCTION_END(Status);
+	return Status;
+}
+
+VL53L0X_Error VL53L0X_get_offset_calibration_data_micro_meter(VL53L0X_DEV Dev,
+		int32_t *pOffsetCalibrationDataMicroMeter)
+{
+	VL53L0X_Error Status = VL53L0X_ERROR_NONE;
+	uint16_t RangeOffsetRegister;
+	int16_t cMaxOffset = 2047;
+	int16_t cOffsetRange = 4096;
+
+	/* Note that offset has 10.2 format */
+
+	Status = VL53L0X_RdWord(Dev,
+				VL53L0X_REG_ALGO_PART_TO_PART_RANGE_OFFSET_MM,
+				&RangeOffsetRegister);
+
+	if (Status == VL53L0X_ERROR_NONE) {
+		RangeOffsetRegister = (RangeOffsetRegister & 0x0fff);
+
+		/* Apply 12 bit 2's compliment conversion */
+		if (RangeOffsetRegister > cMaxOffset)
+			*pOffsetCalibrationDataMicroMeter =
+				(int16_t)(RangeOffsetRegister - cOffsetRange)
+					* 250;
+		else
+			*pOffsetCalibrationDataMicroMeter =
+				(int16_t)RangeOffsetRegister * 250;
+
+	}
+
+	return Status;
+}
+
+
+VL53L0X_Error VL53L0X_apply_offset_adjustment(VL53L0X_DEV Dev)
+{
+	VL53L0X_Error Status = VL53L0X_ERROR_NONE;
+	int32_t CorrectedOffsetMicroMeters;
+	int32_t CurrentOffsetMicroMeters;
+
+	/* if we run on this function we can read all the NVM info
+	 * used by the API */
+	Status = VL53L0X_get_info_from_device(Dev, 7);
+
+	/* Read back current device offset */
+	if (Status == VL53L0X_ERROR_NONE) {
+		Status = VL53L0X_GetOffsetCalibrationDataMicroMeter(Dev,
+					&CurrentOffsetMicroMeters);
+	}
+
+	/* Apply Offset Adjustment derived from 400mm measurements */
+	if (Status == VL53L0X_ERROR_NONE) {
+
+		/* Store initial device offset */
+		PALDevDataSet(Dev, Part2PartOffsetNVMMicroMeter,
+			CurrentOffsetMicroMeters);
+
+		CorrectedOffsetMicroMeters = CurrentOffsetMicroMeters +
+			(int32_t)PALDevDataGet(Dev,
+				Part2PartOffsetAdjustmentNVMMicroMeter);
+
+		Status = VL53L0X_SetOffsetCalibrationDataMicroMeter(Dev,
+					CorrectedOffsetMicroMeters);
+
+		/* store current, adjusted offset */
+		if (Status == VL53L0X_ERROR_NONE) {
+			VL53L0X_SETPARAMETERFIELD(Dev, RangeOffsetMicroMeters,
+					CorrectedOffsetMicroMeters);
+		}
+	}
+
+	return Status;
+}
+
+void get_next_good_spad(uint8_t goodSpadArray[], uint32_t size,
+			uint32_t curr, int32_t *next)
+{
+	uint32_t startIndex;
+	uint32_t fineOffset;
+	uint32_t cSpadsPerByte = 8;
+	uint32_t coarseIndex;
+	uint32_t fineIndex;
+	uint8_t dataByte;
+	uint8_t success = 0;
+
+	/*
+	 * Starting with the current good spad, loop through the array to find
+	 * the next. i.e. the next bit set in the sequence.
+	 *
+	 * The coarse index is the byte index of the array and the fine index is
+	 * the index of the bit within each byte.
+	 */
+
+	*next = -1;
+
+	startIndex = curr / cSpadsPerByte;
+	fineOffset = curr % cSpadsPerByte;
+
+	for (coarseIndex = startIndex; ((coarseIndex < size) && !success);
+				coarseIndex++) {
+		fineIndex = 0;
+		dataByte = goodSpadArray[coarseIndex];
+
+		if (coarseIndex == startIndex) {
+			/* locate the bit position of the provided current
+			 * spad bit before iterating */
+			dataByte >>= fineOffset;
+			fineIndex = fineOffset;
+		}
+
+		while (fineIndex < cSpadsPerByte) {
+			if ((dataByte & 0x1) == 1) {
+				success = 1;
+				*next = coarseIndex * cSpadsPerByte + fineIndex;
+				break;
+			}
+			dataByte >>= 1;
+			fineIndex++;
+		}
+	}
+}
+
+
+uint8_t is_aperture(uint32_t spadIndex)
+{
+	/*
+	 * This function reports if a given spad index is an aperture SPAD by
+	 * deriving the quadrant.
+	 */
+	uint32_t quadrant;
+	uint8_t isAperture = 1;
+	quadrant = spadIndex >> 6;
+	if (refArrayQuadrants[quadrant] == REF_ARRAY_SPAD_0)
+		isAperture = 0;
+
+	return isAperture;
+}
+
+
+VL53L0X_Error enable_spad_bit(uint8_t spadArray[], uint32_t size,
+	uint32_t spadIndex)
+{
+	VL53L0X_Error status = VL53L0X_ERROR_NONE;
+	uint32_t cSpadsPerByte = 8;
+	uint32_t coarseIndex;
+	uint32_t fineIndex;
+
+	coarseIndex = spadIndex / cSpadsPerByte;
+	fineIndex = spadIndex % cSpadsPerByte;
+	if (coarseIndex >= size)
+		status = VL53L0X_ERROR_REF_SPAD_INIT;
+	else
+		spadArray[coarseIndex] |= (1 << fineIndex);
+
+	return status;
+}
+
+VL53L0X_Error count_enabled_spads(uint8_t spadArray[],
+		uint32_t byteCount, uint32_t maxSpads,
+		uint32_t *pTotalSpadsEnabled, uint8_t *pIsAperture)
+{
+	VL53L0X_Error status = VL53L0X_ERROR_NONE;
+	uint32_t cSpadsPerByte = 8;
+	uint32_t lastByte;
+	uint32_t lastBit;
+	uint32_t byteIndex = 0;
+	uint32_t bitIndex = 0;
+	uint8_t tempByte;
+	uint8_t spadTypeIdentified = 0;
+
+	/* The entire array will not be used for spads, therefore the last
+	 * byte and last bit is determined from the max spads value.
+	 */
+
+	lastByte = maxSpads / cSpadsPerByte;
+	lastBit = maxSpads % cSpadsPerByte;
+
+	/* Check that the max spads value does not exceed the array bounds. */
+	if (lastByte >= byteCount)
+		status = VL53L0X_ERROR_REF_SPAD_INIT;
+
+	*pTotalSpadsEnabled = 0;
+
+	/* Count the bits enabled in the whole bytes */
+	for (byteIndex = 0; byteIndex <= (lastByte - 1); byteIndex++) {
+		tempByte = spadArray[byteIndex];
+
+		for (bitIndex = 0; bitIndex <= cSpadsPerByte; bitIndex++) {
+			if ((tempByte & 0x01) == 1) {
+				(*pTotalSpadsEnabled)++;
+
+				if (!spadTypeIdentified) {
+					*pIsAperture = 1;
+					if ((byteIndex < 2) && (bitIndex < 4))
+							*pIsAperture = 0;
+					spadTypeIdentified = 1;
+				}
+			}
+			tempByte >>= 1;
+		}
+	}
+
+	/* Count the number of bits enabled in the last byte accounting
+	 * for the fact that not all bits in the byte may be used.
+	 */
+	tempByte = spadArray[lastByte];
+
+	for (bitIndex = 0; bitIndex <= lastBit; bitIndex++) {
+		if ((tempByte & 0x01) == 1)
+			(*pTotalSpadsEnabled)++;
+	}
+
+	return status;
+}
+
+VL53L0X_Error set_ref_spad_map(VL53L0X_DEV Dev, uint8_t *refSpadArray)
+{
+	VL53L0X_Error status = VL53L0X_WriteMulti(Dev,
+				VL53L0X_REG_GLOBAL_CONFIG_SPAD_ENABLES_REF_0,
+				refSpadArray, 6);
+	return status;
+}
+
+VL53L0X_Error get_ref_spad_map(VL53L0X_DEV Dev, uint8_t *refSpadArray)
+{
+	VL53L0X_Error status = VL53L0X_ReadMulti(Dev,
+				VL53L0X_REG_GLOBAL_CONFIG_SPAD_ENABLES_REF_0,
+				refSpadArray,
+				6);
+	return status;
+}
+
+VL53L0X_Error enable_ref_spads(VL53L0X_DEV Dev,
+				uint8_t apertureSpads,
+				uint8_t goodSpadArray[],
+				uint8_t spadArray[],
+				uint32_t size,
+				uint32_t start,
+				uint32_t offset,
+				uint32_t spadCount,
+				uint32_t *lastSpad)
+{
+	VL53L0X_Error status = VL53L0X_ERROR_NONE;
+	uint32_t index;
+	uint32_t i;
+	int32_t nextGoodSpad = offset;
+	uint32_t currentSpad;
+	uint8_t checkSpadArray[6];
+	/*
+	 * This function takes in a spad array which may or may not have SPADS
+	 * already enabled and appends from a given offset a requested number
+	 * of new SPAD enables. The 'good spad map' is applied to
+	 * determine the next SPADs to enable.
+	 *
+	 * This function applies to only aperture or only non-aperture spads.
+	 * Checks are performed to ensure this.
+	 */
+
+	currentSpad = offset;
+	for (index = 0; index < spadCount; index++) {
+		get_next_good_spad(goodSpadArray, size, currentSpad,
+			&nextGoodSpad);
+
+		if (nextGoodSpad == -1) {
+			status = VL53L0X_ERROR_REF_SPAD_INIT;
+			break;
+		}
+
+		/* Confirm that the next good SPAD is non-aperture */
+		if (is_aperture(start + nextGoodSpad) != apertureSpads) {
+			/* if we can't get the required number of good aperture
+			 * spads from the current quadrant then this is an error
+			 */
+			status = VL53L0X_ERROR_REF_SPAD_INIT;
+			break;
+		}
+		currentSpad = (uint32_t)nextGoodSpad;
+		enable_spad_bit(spadArray, size, currentSpad);
+		currentSpad++;
+	}
+	*lastSpad = currentSpad;
+
+	if (status == VL53L0X_ERROR_NONE)
+		status = set_ref_spad_map(Dev, spadArray);
+
+	if (status == VL53L0X_ERROR_NONE) {
+		status = get_ref_spad_map(Dev, checkSpadArray);
+
+		i = 0;
+
+		/* Compare spad maps. If not equal report error. */
+		while (i < size) {
+			if (spadArray[i] != checkSpadArray[i]) {
+				status = VL53L0X_ERROR_REF_SPAD_INIT;
+				break;
+			}
+			i++;
+		}
+	}
+	// status = VL53L0X_ERROR_NONE;
+	return status;
+}
+
+
+VL53L0X_Error perform_ref_signal_measurement(VL53L0X_DEV Dev,
+		uint16_t *refSignalRate)
+{
+	VL53L0X_Error status = VL53L0X_ERROR_NONE;
+	VL53L0X_RangingMeasurementData_t rangingMeasurementData;
+
+	uint8_t SequenceConfig = 0;
+
+	/* store the value of the sequence config,
+	 * this will be reset before the end of the function
+	 */
+
+	SequenceConfig = PALDevDataGet(Dev, SequenceConfig);
+
+	/*
+	 * This function performs a reference signal rate measurement.
+	 */
+	if (status == VL53L0X_ERROR_NONE)
+		status = VL53L0X_WrByte(Dev,
+			VL53L0X_REG_SYSTEM_SEQUENCE_CONFIG, 0xC0);
+
+	if (status == VL53L0X_ERROR_NONE)
+		status = VL53L0X_PerformSingleRangingMeasurement(Dev,
+				&rangingMeasurementData);
+
+	if (status == VL53L0X_ERROR_NONE)
+		status = VL53L0X_WrByte(Dev, 0xFF, 0x01);
+
+	if (status == VL53L0X_ERROR_NONE)
+		status = VL53L0X_RdWord(Dev,
+			VL53L0X_REG_RESULT_PEAK_SIGNAL_RATE_REF,
+			refSignalRate);
+
+	if (status == VL53L0X_ERROR_NONE)
+		status = VL53L0X_WrByte(Dev, 0xFF, 0x00);
+
+	if (status == VL53L0X_ERROR_NONE) {
+		/* restore the previous Sequence Config */
+		status = VL53L0X_WrByte(Dev, VL53L0X_REG_SYSTEM_SEQUENCE_CONFIG,
+				SequenceConfig);
+		if (status == VL53L0X_ERROR_NONE)
+			PALDevDataSet(Dev, SequenceConfig, SequenceConfig);
+	}
+
+	return status;
+}
+
+VL53L0X_Error VL53L0X_perform_ref_spad_management(VL53L0X_DEV Dev,
+				uint32_t *refSpadCount,
+				uint8_t *isApertureSpads)
+{
+	VL53L0X_Error Status = VL53L0X_ERROR_NONE;
+	uint8_t lastSpadArray[6];
+	uint8_t startSelect = 0xB4;
+	uint32_t minimumSpadCount = 3;
+	uint32_t maxSpadCount = 44;
+	uint32_t currentSpadIndex = 0;
+	uint32_t lastSpadIndex = 0;
+	int32_t nextGoodSpad = 0;
+	uint16_t targetRefRate = 0x0A00; /* 20 MCPS in 9:7 format */
+	uint16_t peakSignalRateRef;
+	uint32_t needAptSpads = 0;
+	uint32_t index = 0;
+	uint32_t spadArraySize = 6;
+	uint32_t signalRateDiff = 0;
+	uint32_t lastSignalRateDiff = 0;
+	uint8_t complete = 0;
+	uint8_t VhvSettings = 0;
+	uint8_t PhaseCal = 0;
+	uint32_t refSpadCount_int = 0;
+	uint8_t	 isApertureSpads_int = 0;
+
+	/*
+	 * The reference SPAD initialization procedure determines the minimum
+	 * amount of reference spads to be enables to achieve a target reference
+	 * signal rate and should be performed once during initialization.
+	 *
+	 * Either aperture or non-aperture spads are applied but never both.
+	 * Firstly non-aperture spads are set, begining with 5 spads, and
+	 * increased one spad at a time until the closest measurement to the
+	 * target rate is achieved.
+	 *
+	 * If the target rate is exceeded when 5 non-aperture spads are enabled,
+	 * initialization is performed instead with aperture spads.
+	 *
+	 * When setting spads, a 'Good Spad Map' is applied.
+	 *
+	 * This procedure operates within a SPAD window of interest of a maximum
+	 * 44 spads.
+	 * The start point is currently fixed to 180, which lies towards the end
+	 * of the non-aperture quadrant and runs in to the adjacent aperture
+	 * quadrant.
+	 */
+
+
+	targetRefRate = PALDevDataGet(Dev, targetRefRate);
+
+	/*
+	 * Initialize Spad arrays.
+	 * Currently the good spad map is initialised to 'All good'.
+	 * This is a short term implementation. The good spad map will be
+	 * provided as an input.
+	 * Note that there are 6 bytes. Only the first 44 bits will be used to
+	 * represent spads.
+	 */
+	for (index = 0; index < spadArraySize; index++)
+		Dev->Data.SpadData.RefSpadEnables[index] = 0;
+
+
+	Status = VL53L0X_WrByte(Dev, 0xFF, 0x01);
+
+	if (Status == VL53L0X_ERROR_NONE)
+		Status = VL53L0X_WrByte(Dev,
+			VL53L0X_REG_DYNAMIC_SPAD_REF_EN_START_OFFSET, 0x00);
+
+	if (Status == VL53L0X_ERROR_NONE)
+		Status = VL53L0X_WrByte(Dev,
+			VL53L0X_REG_DYNAMIC_SPAD_NUM_REQUESTED_REF_SPAD, 0x2C);
+
+	if (Status == VL53L0X_ERROR_NONE)
+		Status = VL53L0X_WrByte(Dev, 0xFF, 0x00);
+
+	if (Status == VL53L0X_ERROR_NONE)
+		Status = VL53L0X_WrByte(Dev,
+			VL53L0X_REG_GLOBAL_CONFIG_REF_EN_START_SELECT,
+			startSelect);
+
+
+	if (Status == VL53L0X_ERROR_NONE)
+		Status = VL53L0X_WrByte(Dev,
+				VL53L0X_REG_POWER_MANAGEMENT_GO1_POWER_FORCE, 0);
+
+	/* Perform ref calibration */
+	if (Status == VL53L0X_ERROR_NONE)
+		Status = VL53L0X_perform_ref_calibration(Dev, &VhvSettings,
+			&PhaseCal, 0);
+
+	if (Status == VL53L0X_ERROR_NONE) {
+		/* Enable Minimum NON-APERTURE Spads */
+		currentSpadIndex = 0;
+		lastSpadIndex = currentSpadIndex;
+		needAptSpads = 0;
+		Status = enable_ref_spads(Dev,
+					needAptSpads,
+					Dev->Data.SpadData.RefGoodSpadMap,
+					Dev->Data.SpadData.RefSpadEnables,
+					spadArraySize,
+					startSelect,
+					currentSpadIndex,
+					minimumSpadCount,
+					&lastSpadIndex);
+	}
+
+	if (Status == VL53L0X_ERROR_NONE) {
+		currentSpadIndex = lastSpadIndex;
+
+		Status = perform_ref_signal_measurement(Dev,
+			&peakSignalRateRef);
+		if ((Status == VL53L0X_ERROR_NONE) &&
+			(peakSignalRateRef > targetRefRate)) {
+			/* Signal rate measurement too high,
+			 * switch to APERTURE SPADs */
+
+			for (index = 0; index < spadArraySize; index++)
+				Dev->Data.SpadData.RefSpadEnables[index] = 0;
+
+
+			/* Increment to the first APERTURE spad */
+			while ((is_aperture(startSelect + currentSpadIndex)
+				== 0) && (currentSpadIndex < maxSpadCount)) {
+				currentSpadIndex++;
+			}
+
+			needAptSpads = 1;
+
+			Status = enable_ref_spads(Dev,
+					needAptSpads,
+					Dev->Data.SpadData.RefGoodSpadMap,
+					Dev->Data.SpadData.RefSpadEnables,
+					spadArraySize,
+					startSelect,
+					currentSpadIndex,
+					minimumSpadCount,
+					&lastSpadIndex);
+
+			if (Status == VL53L0X_ERROR_NONE) {
+				currentSpadIndex = lastSpadIndex;
+				Status = perform_ref_signal_measurement(Dev,
+						&peakSignalRateRef);
+
+				if ((Status == VL53L0X_ERROR_NONE) &&
+					(peakSignalRateRef > targetRefRate)) {
+					/* Signal rate still too high after
+					 * setting the minimum number of
+					 * APERTURE spads. Can do no more
+					 * therefore set the min number of
+					 * aperture spads as the result.
+					 */
+					isApertureSpads_int = 1;
+					refSpadCount_int = minimumSpadCount;
+				}
+			}
+		} else {
+			needAptSpads = 0;
+		}
+	}
+
+	if ((Status == VL53L0X_ERROR_NONE) &&
+		(peakSignalRateRef < targetRefRate)) {
+		/* At this point, the minimum number of either aperture
+		 * or non-aperture spads have been set. Proceed to add
+		 * spads and perform measurements until the target
+		 * reference is reached.
+		 */
+		isApertureSpads_int = needAptSpads;
+		refSpadCount_int	= minimumSpadCount;
+
+		memcpy(lastSpadArray, Dev->Data.SpadData.RefSpadEnables,
+				spadArraySize);
+		if(peakSignalRateRef > targetRefRate)
+		{
+			signalRateDiff = peakSignalRateRef - targetRefRate;
+		}
+		else
+		{
+			signalRateDiff = targetRefRate - peakSignalRateRef ;
+		}
+		//lastSignalRateDiff = abs(peakSignalRateRef -targetRefRate);
+		complete = 0;
+
+		while (!complete) {
+			get_next_good_spad(
+				Dev->Data.SpadData.RefGoodSpadMap,
+				spadArraySize, currentSpadIndex,
+				&nextGoodSpad);
+
+			if (nextGoodSpad == -1) {
+				Status = VL53L0X_ERROR_REF_SPAD_INIT;
+				break;
+			}
+
+			(refSpadCount_int)++;
+
+			/* Cannot combine Aperture and Non-Aperture spads, so
+			 * ensure the current spad is of the correct type.
+			 */
+			if (is_aperture((uint32_t)startSelect + nextGoodSpad) !=
+					needAptSpads) {
+				Status = VL53L0X_ERROR_REF_SPAD_INIT;
+				break;
+			}
+
+			currentSpadIndex = nextGoodSpad;
+			Status = enable_spad_bit(
+					Dev->Data.SpadData.RefSpadEnables,
+					spadArraySize, currentSpadIndex);
+
+			if (Status == VL53L0X_ERROR_NONE) {
+				currentSpadIndex++;
+				/* Proceed to apply the additional spad and
+				 * perform measurement. */
+				Status = set_ref_spad_map(Dev,
+					Dev->Data.SpadData.RefSpadEnables);
+			}
+
+			if (Status != VL53L0X_ERROR_NONE)
+				break;
+
+			Status = perform_ref_signal_measurement(Dev,
+					&peakSignalRateRef);
+
+			if (Status != VL53L0X_ERROR_NONE)
+				break;
+			if(peakSignalRateRef > targetRefRate)
+			{
+				signalRateDiff = peakSignalRateRef - targetRefRate;
+			}
+			else
+			{
+				signalRateDiff = targetRefRate - peakSignalRateRef ;
+			}
+			
+
+			if (peakSignalRateRef > targetRefRate) {
+				/* Select the spad map that provides the
+				 * measurement closest to the target rate,
+				 * either above or below it.
+				 */
+				if (signalRateDiff > lastSignalRateDiff) {
+					/* Previous spad map produced a closer
+					 * measurement, so choose this. */
+					Status = set_ref_spad_map(Dev,
+							lastSpadArray);
+					memcpy(
+					Dev->Data.SpadData.RefSpadEnables,
+					lastSpadArray, spadArraySize);
+
+					(refSpadCount_int)--;
+				}
+				complete = 1;
+			} else {
+				/* Continue to add spads */
+				lastSignalRateDiff = signalRateDiff;
+				memcpy(lastSpadArray,
+					Dev->Data.SpadData.RefSpadEnables,
+					spadArraySize);
+			}
+
+		} /* while */
+	}
+
+	if (Status == VL53L0X_ERROR_NONE) {
+		*refSpadCount = refSpadCount_int;
+		*isApertureSpads = isApertureSpads_int;
+
+		VL53L0X_SETDEVICESPECIFICPARAMETER(Dev, RefSpadsInitialised, 1);
+		VL53L0X_SETDEVICESPECIFICPARAMETER(Dev,
+			ReferenceSpadCount, (uint8_t)(*refSpadCount));
+		VL53L0X_SETDEVICESPECIFICPARAMETER(Dev,
+			ReferenceSpadType, *isApertureSpads);
+	}
+
+	return Status;
+}
+
+VL53L0X_Error VL53L0X_set_reference_spads(VL53L0X_DEV Dev,
+				 uint32_t count, uint8_t isApertureSpads)
+{
+	VL53L0X_Error Status = VL53L0X_ERROR_NONE;
+	uint32_t currentSpadIndex = 0;
+	uint8_t startSelect = 0xB4;
+	uint32_t spadArraySize = 6;
+	uint32_t maxSpadCount = 44;
+	uint32_t lastSpadIndex;
+	uint32_t index;
+
+	/*
+	 * This function applies a requested number of reference spads, either
+	 * aperture or
+	 * non-aperture, as requested.
+	 * The good spad map will be applied.
+	 */
+
+	Status = VL53L0X_WrByte(Dev, 0xFF, 0x01);
+
+	if (Status == VL53L0X_ERROR_NONE)
+		Status = VL53L0X_WrByte(Dev,
+			VL53L0X_REG_DYNAMIC_SPAD_REF_EN_START_OFFSET, 0x00);
+
+	if (Status == VL53L0X_ERROR_NONE)
+		Status = VL53L0X_WrByte(Dev,
+			VL53L0X_REG_DYNAMIC_SPAD_NUM_REQUESTED_REF_SPAD, 0x2C);
+
+	if (Status == VL53L0X_ERROR_NONE)
+		Status = VL53L0X_WrByte(Dev, 0xFF, 0x00);
+
+	if (Status == VL53L0X_ERROR_NONE)
+		Status = VL53L0X_WrByte(Dev,
+			VL53L0X_REG_GLOBAL_CONFIG_REF_EN_START_SELECT,
+			startSelect);
+
+	for (index = 0; index < spadArraySize; index++)
+		Dev->Data.SpadData.RefSpadEnables[index] = 0;
+
+	if (isApertureSpads) {
+		/* Increment to the first APERTURE spad */
+		while ((is_aperture(startSelect + currentSpadIndex) == 0) &&
+			  (currentSpadIndex < maxSpadCount)) {
+			currentSpadIndex++;
+		}
+	}
+	Status = enable_ref_spads(Dev,
+				isApertureSpads,
+				Dev->Data.SpadData.RefGoodSpadMap,
+				Dev->Data.SpadData.RefSpadEnables,
+				spadArraySize,
+				startSelect,
+				currentSpadIndex,
+				count,
+				&lastSpadIndex);
+	if (Status == VL53L0X_ERROR_NONE) {
+		VL53L0X_SETDEVICESPECIFICPARAMETER(Dev, RefSpadsInitialised, 1);
+		VL53L0X_SETDEVICESPECIFICPARAMETER(Dev,
+			ReferenceSpadCount, (uint8_t)(count));
+		VL53L0X_SETDEVICESPECIFICPARAMETER(Dev,
+			ReferenceSpadType, isApertureSpads);
+	}
+
+	return Status;
+}
+
+VL53L0X_Error VL53L0X_get_reference_spads(VL53L0X_DEV Dev,
+			uint32_t *pSpadCount, uint8_t *pIsApertureSpads)
+{
+	VL53L0X_Error Status = VL53L0X_ERROR_NONE;
+	uint8_t refSpadsInitialised;
+	uint8_t refSpadArray[6];
+	uint32_t cMaxSpadCount = 44;
+	uint32_t cSpadArraySize = 6;
+	uint32_t spadsEnabled;
+	uint8_t isApertureSpads = 0;
+
+	refSpadsInitialised = VL53L0X_GETDEVICESPECIFICPARAMETER(Dev,
+					RefSpadsInitialised);
+
+	if (refSpadsInitialised == 1) {
+
+		*pSpadCount = (uint32_t)VL53L0X_GETDEVICESPECIFICPARAMETER(Dev,
+			ReferenceSpadCount);
+		*pIsApertureSpads = VL53L0X_GETDEVICESPECIFICPARAMETER(Dev,
+			ReferenceSpadType);
+	} else {
+
+		/* obtain spad info from device.*/
+		Status = get_ref_spad_map(Dev, refSpadArray);
+
+		if (Status == VL53L0X_ERROR_NONE) {
+			/* count enabled spads within spad map array and
+			 * determine if Aperture or Non-Aperture.
+			 */
+			Status = count_enabled_spads(refSpadArray,
+							cSpadArraySize,
+							cMaxSpadCount,
+							&spadsEnabled,
+							&isApertureSpads);
+
+			if (Status == VL53L0X_ERROR_NONE) {
+
+				*pSpadCount = spadsEnabled;
+				*pIsApertureSpads = isApertureSpads;
+
+				VL53L0X_SETDEVICESPECIFICPARAMETER(Dev,
+					RefSpadsInitialised, 1);
+				VL53L0X_SETDEVICESPECIFICPARAMETER(Dev,
+					ReferenceSpadCount,
+					(uint8_t)spadsEnabled);
+				VL53L0X_SETDEVICESPECIFICPARAMETER(Dev,
+					ReferenceSpadType, isApertureSpads);
+			}
+		}
+	}
+
+	return Status;
+}
+
+
+VL53L0X_Error VL53L0X_perform_single_ref_calibration(VL53L0X_DEV Dev,
+		uint8_t vhv_init_byte)
+{
+	VL53L0X_Error Status = VL53L0X_ERROR_NONE;
+
+	if (Status == VL53L0X_ERROR_NONE)
+		Status = VL53L0X_WrByte(Dev, VL53L0X_REG_SYSRANGE_START,
+				VL53L0X_REG_SYSRANGE_MODE_START_STOP |
+				vhv_init_byte);
+
+	if (Status == VL53L0X_ERROR_NONE)
+		Status = VL53L0X_measurement_poll_for_completion(Dev);
+
+	if (Status == VL53L0X_ERROR_NONE)
+		Status = VL53L0X_ClearInterruptMask(Dev, 0);
+
+	if (Status == VL53L0X_ERROR_NONE)
+		Status = VL53L0X_WrByte(Dev, VL53L0X_REG_SYSRANGE_START, 0x00);
+
+	return Status;
+}
+
+
+VL53L0X_Error VL53L0X_ref_calibration_io(VL53L0X_DEV Dev, uint8_t read_not_write,
+	uint8_t VhvSettings, uint8_t PhaseCal,
+	uint8_t *pVhvSettings, uint8_t *pPhaseCal,
+	const uint8_t vhv_enable, const uint8_t phase_enable)
+{
+	VL53L0X_Error Status = VL53L0X_ERROR_NONE;
+	uint8_t PhaseCalint = 0;
+
+	/* Read VHV from device */
+	Status |= VL53L0X_WrByte(Dev, 0xFF, 0x01);
+	Status |= VL53L0X_WrByte(Dev, 0x00, 0x00);
+	Status |= VL53L0X_WrByte(Dev, 0xFF, 0x00);
+
+	if (read_not_write) {
+		if (vhv_enable)
+			Status |= VL53L0X_RdByte(Dev, 0xCB, pVhvSettings);
+		if (phase_enable)
+			Status |= VL53L0X_RdByte(Dev, 0xEE, &PhaseCalint);
+	} else {
+		if (vhv_enable)
+			Status |= VL53L0X_WrByte(Dev, 0xCB, VhvSettings);
+		if (phase_enable)
+			Status |= VL53L0X_UpdateByte(Dev, 0xEE, 0x80, PhaseCal);
+	}
+
+	Status |= VL53L0X_WrByte(Dev, 0xFF, 0x01);
+	Status |= VL53L0X_WrByte(Dev, 0x00, 0x01);
+	Status |= VL53L0X_WrByte(Dev, 0xFF, 0x00);
+
+	*pPhaseCal = (uint8_t)(PhaseCalint&0xEF);
+
+	return Status;
+}
+
+
+VL53L0X_Error VL53L0X_perform_vhv_calibration(VL53L0X_DEV Dev,
+	uint8_t *pVhvSettings, const uint8_t get_data_enable,
+	const uint8_t restore_config)
+{
+	VL53L0X_Error Status = VL53L0X_ERROR_NONE;
+	uint8_t SequenceConfig = 0;
+	uint8_t VhvSettings = 0;
+	uint8_t PhaseCal = 0;
+	uint8_t PhaseCalInt = 0;
+
+	/* store the value of the sequence config,
+	 * this will be reset before the end of the function
+	 */
+
+	if (restore_config)
+		SequenceConfig = PALDevDataGet(Dev, SequenceConfig);
+
+	/* Run VHV */
+	Status = VL53L0X_WrByte(Dev, VL53L0X_REG_SYSTEM_SEQUENCE_CONFIG, 0x01);
+
+	if (Status == VL53L0X_ERROR_NONE)
+		Status = VL53L0X_perform_single_ref_calibration(Dev, 0x40);
+
+	/* Read VHV from device */
+	if ((Status == VL53L0X_ERROR_NONE) && (get_data_enable == 1)) {
+		Status = VL53L0X_ref_calibration_io(Dev, 1,
+			VhvSettings, PhaseCal, /* Not used here */
+			pVhvSettings, &PhaseCalInt,
+			1, 0);
+	} else
+		*pVhvSettings = 0;
+
+
+	if ((Status == VL53L0X_ERROR_NONE) && restore_config) {
+		/* restore the previous Sequence Config */
+		Status = VL53L0X_WrByte(Dev, VL53L0X_REG_SYSTEM_SEQUENCE_CONFIG,
+				SequenceConfig);
+		if (Status == VL53L0X_ERROR_NONE)
+			PALDevDataSet(Dev, SequenceConfig, SequenceConfig);
+
+	}
+
+	return Status;
+}
+
+VL53L0X_Error VL53L0X_perform_phase_calibration(VL53L0X_DEV Dev,
+	uint8_t *pPhaseCal, const uint8_t get_data_enable,
+	const uint8_t restore_config)
+{
+	VL53L0X_Error Status = VL53L0X_ERROR_NONE;
+	uint8_t SequenceConfig = 0;
+	uint8_t VhvSettings = 0;
+	uint8_t PhaseCal = 0;
+	uint8_t VhvSettingsint;
+
+	/* store the value of the sequence config,
+	 * this will be reset before the end of the function
+	 */
+
+	if (restore_config)
+		SequenceConfig = PALDevDataGet(Dev, SequenceConfig);
+
+	/* Run PhaseCal */
+	Status = VL53L0X_WrByte(Dev, VL53L0X_REG_SYSTEM_SEQUENCE_CONFIG, 0x02);
+
+	if (Status == VL53L0X_ERROR_NONE)
+		Status = VL53L0X_perform_single_ref_calibration(Dev, 0x0);
+
+	/* Read PhaseCal from device */
+	if ((Status == VL53L0X_ERROR_NONE) && (get_data_enable == 1)) {
+		Status = VL53L0X_ref_calibration_io(Dev, 1,
+			VhvSettings, PhaseCal, /* Not used here */
+			&VhvSettingsint, pPhaseCal,
+			0, 1);
+	} else
+		*pPhaseCal = 0;
+
+
+	if ((Status == VL53L0X_ERROR_NONE) && restore_config) {
+		/* restore the previous Sequence Config */
+		Status = VL53L0X_WrByte(Dev, VL53L0X_REG_SYSTEM_SEQUENCE_CONFIG,
+				SequenceConfig);
+		if (Status == VL53L0X_ERROR_NONE)
+			PALDevDataSet(Dev, SequenceConfig, SequenceConfig);
+
+	}
+
+	return Status;
+}
+
+VL53L0X_Error VL53L0X_perform_ref_calibration(VL53L0X_DEV Dev,
+	uint8_t *pVhvSettings, uint8_t *pPhaseCal, uint8_t get_data_enable)
+{
+	VL53L0X_Error Status = VL53L0X_ERROR_NONE;
+	uint8_t SequenceConfig = 0;
+
+	/* store the value of the sequence config,
+	 * this will be reset before the end of the function
+	 */
+
+	SequenceConfig = PALDevDataGet(Dev, SequenceConfig);
+
+	/* In the following function we don't save the config to optimize
+	 * writes on device. Config is saved and restored only once. */
+	Status = VL53L0X_perform_vhv_calibration(
+			Dev, pVhvSettings, get_data_enable, 0);
+
+
+	if (Status == VL53L0X_ERROR_NONE)
+		Status = VL53L0X_perform_phase_calibration(
+			Dev, pPhaseCal, get_data_enable, 0);
+
+
+	if (Status == VL53L0X_ERROR_NONE) {
+		/* restore the previous Sequence Config */
+		Status = VL53L0X_WrByte(Dev, VL53L0X_REG_SYSTEM_SEQUENCE_CONFIG,
+				SequenceConfig);
+		if (Status == VL53L0X_ERROR_NONE)
+			PALDevDataSet(Dev, SequenceConfig, SequenceConfig);
+
+	}
+
+	return Status;
+}
+
+VL53L0X_Error VL53L0X_set_ref_calibration(VL53L0X_DEV Dev,
+		uint8_t VhvSettings, uint8_t PhaseCal)
+{
+	VL53L0X_Error Status = VL53L0X_ERROR_NONE;
+	uint8_t pVhvSettings;
+	uint8_t pPhaseCal;
+
+	Status = VL53L0X_ref_calibration_io(Dev, 0,
+		VhvSettings, PhaseCal,
+		&pVhvSettings, &pPhaseCal,
+		1, 1);
+
+	return Status;
+}
+
+VL53L0X_Error VL53L0X_get_ref_calibration(VL53L0X_DEV Dev,
+		uint8_t *pVhvSettings, uint8_t *pPhaseCal)
+{
+	VL53L0X_Error Status = VL53L0X_ERROR_NONE;
+	uint8_t VhvSettings = 0;
+	uint8_t PhaseCal = 0;
+
+	Status = VL53L0X_ref_calibration_io(Dev, 1,
+		VhvSettings, PhaseCal,
+		pVhvSettings, pPhaseCal,
+		1, 1);
+
+	return Status;
+}
+
+
+
+
+/**************************************************************************************************************/
+/**************************************************************************************************************/
+/**************************************************************************************************************/
+static VL53L0X_Dev_t MyDevice = {
+	.I2cDevAddr = 0x29,
+	.comms_type = 1,
+	.comms_speed_khz = 400,
+};
+
+static VL53L0X_Dev_t *pMyDevice = &MyDevice;
+static VL53L0X_Version_t version;
+static VL53L0X_Version_t* pVersion = &version;
+
+static VL53L0X_Error check_version(void)
+{
+	VL53L0X_Error Status = VL53L0X_ERROR_NONE;
+	int32_t status_int;
+
+	status_int = VL53L0X_GetVersion(pVersion);
+	if (status_int != 0){
+		Status = VL53L0X_ERROR_CONTROL_INTERFACE;
+		return Status;
+	}
+    
+	if( pVersion->major != VERSION_REQUIRED_MAJOR ||
+		pVersion->minor != VERSION_REQUIRED_MINOR ||	
+		pVersion->build != VERSION_REQUIRED_BUILD ){
+		}
+	return Status;
+}
+
+static VL53L0X_Error VL53L0X_calibration_oprt(void)
+{
+	uint32_t refSpadCount;
+	uint8_t isApertureSpads;
+	uint8_t VhvSettings;
+	uint8_t PhaseCal;
+	VL53L0X_Error Status = VL53L0X_ERROR_NONE;
+
+	Status = VL53L0X_PerformRefSpadManagement(pMyDevice,
+		&refSpadCount, &isApertureSpads); 
+	if(VL53L0X_ERROR_NONE!=Status) return Status;
+	Status = VL53L0X_PerformRefCalibration(pMyDevice,
+		&VhvSettings, &PhaseCal); 
+	if(VL53L0X_ERROR_NONE!=Status) return Status;
+
+	return Status;
+}
+
+static VL53L0X_Error VL53L0X_set_limit_param(void)
+{
+	VL53L0X_Error Status = VL53L0X_ERROR_NONE;
+	Status = VL53L0X_SetLimitCheckEnable(pMyDevice,
+		VL53L0X_CHECKENABLE_SIGMA_FINAL_RANGE, 1);
+	if(VL53L0X_ERROR_NONE!=Status) return Status;
+
+	Status = VL53L0X_SetLimitCheckEnable(pMyDevice,
+		VL53L0X_CHECKENABLE_SIGNAL_RATE_FINAL_RANGE, 1);
+	if(VL53L0X_ERROR_NONE!=Status) return Status;        
+
+	Status = VL53L0X_SetLimitCheckEnable(pMyDevice,
+		VL53L0X_CHECKENABLE_RANGE_IGNORE_THRESHOLD, 1);
+	if(VL53L0X_ERROR_NONE!=Status) return Status;
+
+	Status = VL53L0X_SetLimitCheckValue(pMyDevice,
+		VL53L0X_CHECKENABLE_RANGE_IGNORE_THRESHOLD,
+		(FixPoint1616_t)(2261));
+	if(VL53L0X_ERROR_NONE!=Status) return Status;
+
+	return Status;
+}
+
+
+static int32_t common_init(void)
+{
+	VL53L0X_Error Status = VL53L0X_ERROR_NONE;
+
+	Status=check_version();
+	if(VL53L0X_ERROR_NONE!=Status) return Status;
+	Status = VL53L0X_DataInit(&MyDevice); 
+	if(VL53L0X_ERROR_NONE!=Status) return Status;
+
+	Status = VL53L0X_StaticInit(pMyDevice); 
+	if(VL53L0X_ERROR_NONE!=Status) return Status;
+
+	Status=VL53L0X_calibration_oprt();
+	if(VL53L0X_ERROR_NONE!=Status) return Status;
+	Status = VL53L0X_SetDeviceMode(pMyDevice, VL53L0X_DEVICEMODE_SINGLE_RANGING); // Setup in single ranging mode
+	if(VL53L0X_ERROR_NONE!=Status) return Status;
+	Status = VL53L0X_set_limit_param();
+	if(VL53L0X_ERROR_NONE!=Status) return Status;
+	Status = VL53L0X_SetDeviceMode(pMyDevice, VL53L0X_DEVICEMODE_CONTINUOUS_RANGING);
+	if(VL53L0X_ERROR_NONE!=Status) return Status;
+	return Status;
+}
+
+
+VL53L0X_Error VL53L0X_single_ranging_init(void)
+{
+	VL53L0X_Error Status = VL53L0X_ERROR_NONE;
+	Status = VL53L0X_SetDeviceMode(pMyDevice, VL53L0X_DEVICEMODE_SINGLE_RANGING); // Setup in single ranging mode
+	if(VL53L0X_ERROR_NONE!=Status) return Status;
+
+	Status = VL53L0X_SetLimitCheckEnable(pMyDevice,
+		VL53L0X_CHECKENABLE_SIGMA_FINAL_RANGE, 1);
+	if(VL53L0X_ERROR_NONE!=Status) return Status;
+
+	Status = VL53L0X_SetLimitCheckEnable(pMyDevice,
+		VL53L0X_CHECKENABLE_SIGNAL_RATE_FINAL_RANGE, 1);
+	if(VL53L0X_ERROR_NONE!=Status) return Status;        
+
+	Status = VL53L0X_SetLimitCheckEnable(pMyDevice,
+		VL53L0X_CHECKENABLE_RANGE_IGNORE_THRESHOLD, 1);
+	if(VL53L0X_ERROR_NONE!=Status) return Status;
+
+	Status = VL53L0X_SetLimitCheckValue(pMyDevice,
+		VL53L0X_CHECKENABLE_RANGE_IGNORE_THRESHOLD,
+		(FixPoint1616_t)2261);
+	if(VL53L0X_ERROR_NONE!=Status) return Status;
+
+	return Status;
+}
+
+
+static VL53L0X_Error PerformSingleRangingMeasurement(VL53L0X_RangingMeasurementData_t* RangingMeasurementData)
+{
+	VL53L0X_Error Status = VL53L0X_ERROR_NONE;
+	if(Status == VL53L0X_ERROR_NONE){
+	Status = VL53L0X_PerformSingleRangingMeasurement(pMyDevice,
+			RangingMeasurementData);
+	return Status;
+    }
+	return Status;
+}
+
+static uint32_t read_distance(void)
+{
+	VL53L0X_RangingMeasurementData_t RangingMeasurementData;
+	VL53L0X_Error Status = VL53L0X_ERROR_NONE;
+	memset(&RangingMeasurementData,0,sizeof(VL53L0X_RangingMeasurementData_t));
+	Status = PerformSingleRangingMeasurement(&RangingMeasurementData);
+	if(VL53L0X_ERROR_NONE == Status){
+	return RangingMeasurementData.RangeMilliMeter;
+	}
+	else{
+		return -1;
+	}
+}
+
+/**************************************************************************************************************/
+
+static ssize_t vl53l0x_distance_show(struct kobject* kobjs,struct kobj_attribute *attr,char *buf)
+{
+	uint32_t distance = 0;
+	distance = read_distance();
+	return sprintf(buf,"The distance = %d\n",distance);
+}
+static struct kobj_attribute status_attr = __ATTR_RO(vl53l0x_distance);
+
+
+/**************************************************************************************************************/
+/**************************************************************************************************************/
+/**************************************************************************************************************/
+
+
+static const struct i2c_device_id vl53l0x_drv_id_table[] = {
+	{"vl53l0x",0},
+	{},
+};
+
+
+static int major;
+static struct class *vl53l0x_i2c_cls;
+static struct device *vl53l0x_i2c_dev;
+static const char* CLASS_NAME = "vl53l0x_cls";
+static const char* DEVICE_NAME = "vl53l0x_dev";
+
+
+
+static int vl53l0x_i2c_open(struct inode *node, struct file *file)
+{
+	return 0;
+}
+
+static ssize_t vl53l0x_i2c_read(struct file *file,char *buf, size_t len,loff_t *offset)
+{
+	int cnt = 0;
+	uint32_t buf_len = 0;
+	uint32_t distance = 0;
+	uint8_t dis_buf[50] = {0};
+	distance = read_distance();
+	if(distance < 0){
+		sprintf(dis_buf,"Read sensor failed\n");
+	}
+	else if(distance >= 2000){
+		sprintf(dis_buf,"Object Distance out of range\n");
+	}
+	else{
+		sprintf(dis_buf,"Object Distance = %d mm\n",distance);
+	}
+	buf_len = strlen(dis_buf);
+	cnt = copy_to_user(buf,dis_buf,strlen(dis_buf));
+	if(cnt){
+		printk(KERN_INFO "copy to user failed\n");
+		return -ENOMEM;
+	}
+	return buf_len;
+}
+
+
+static struct file_operations file_oprts = {
+	.open = vl53l0x_i2c_open,
+	.read = vl53l0x_i2c_read,
+};
+
+
+static int vl53l0x_drv_probe(struct i2c_client *client, const struct i2c_device_id *id)
+{
+	VL53L0X_Error Status = VL53L0X_ERROR_NONE;
+	vl53l0x_client = client;
+
+	Status = common_init();
+	if(VL53L0X_ERROR_NONE != Status){
+		printk(KERN_ALERT "Init sensor failed!\n");
+		return -ENODEV;
+	}
+	Status = VL53L0X_single_ranging_init();
+	if(VL53L0X_ERROR_NONE != Status){
+		printk(KERN_ALERT "single ranging init failed!\n");
+		return -ENODEV;
+    	}
+
+	if(sysfs_create_file(&vl53l0x_client->dev.kobj, &status_attr.attr) < 0){
+		printk(KERN_ALERT "Fail to create sys file\n");
+		return -ENOMEM;
+    	}
+
+	major = register_chrdev(0,DEVICE_NAME,&file_oprts);
+	if(major < 0 ){
+		sysfs_remove_file(&vl53l0x_client->dev.kobj, &status_attr.attr);
+		printk(KERN_ALERT "Register failed!!\r\n");
+		return major;
+	}
+	printk(KERN_ALERT "Registe success,major number = %d\r\n",major);
+
+	vl53l0x_i2c_cls = class_create(THIS_MODULE,CLASS_NAME);
+	if(IS_ERR(vl53l0x_i2c_cls)){
+		sysfs_remove_file(&vl53l0x_client->dev.kobj, &status_attr.attr);
+		unregister_chrdev(major,DEVICE_NAME);
+		return PTR_ERR(vl53l0x_i2c_cls);
+	}
+
+	vl53l0x_i2c_dev = device_create(vl53l0x_i2c_cls,NULL,MKDEV(major,0),NULL,DEVICE_NAME);
+	if(IS_ERR(vl53l0x_i2c_dev)){
+		sysfs_remove_file(&vl53l0x_client->dev.kobj, &status_attr.attr);
+		class_destroy(vl53l0x_i2c_cls);
+		unregister_chrdev(major,DEVICE_NAME);
+		return PTR_ERR(vl53l0x_i2c_dev);
+	}
+    	printk(KERN_ALERT "vl53l0x_i2c device init success!!\r\n");
+    
+
+    	return 0;
+}
+
+static int vl53l0x_drv_remove(struct i2c_client *client)
+{
+	sysfs_remove_file(&vl53l0x_client->dev.kobj, &status_attr.attr);
+	device_destroy(vl53l0x_i2c_cls,MKDEV(major,0));
+	class_unregister(vl53l0x_i2c_cls);
+	class_destroy(vl53l0x_i2c_cls);
+	unregister_chrdev(major,DEVICE_NAME);
+
+    	return 0;
+}
+
+
+
+static const struct of_device_id vl53l0x_match_table[] = {
+	{.compatible = "st,vl53l0x"},
+	{},
+};
+
+static struct i2c_driver vl53l0x_drv = {
+	.driver = {
+		.name = "vl53l0x",
+		.owner = THIS_MODULE,
+		.of_match_table = of_match_ptr(vl53l0x_match_table),
+	},
+	.probe = vl53l0x_drv_probe,
+	.remove = vl53l0x_drv_remove,
+	.id_table = vl53l0x_drv_id_table,
+};
+
+MODULE_DEVICE_TABLE(of,vl53l0x_match_table);
+
+
+int drv_init(void)
+{
+	int ret = 0;
+	ret  = i2c_add_driver(&vl53l0x_drv);
+	if(ret){
+		printk(KERN_ALERT "add driver failed!!!\n");
+		return -ENODEV;
+	}
+	return 0;
+}
+
+
+void drv_exit(void)
+{
+	i2c_del_driver(&vl53l0x_drv);
+	return ;
+}
+
+
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("This module is for Seeed vl53l0x ranging sensor.");
+MODULE_AUTHOR("Downey");
+
+module_init(drv_init);
+module_exit(drv_exit);
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/wm8960/Makefile b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/wm8960/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..41c5e3d37075fb32a0b9fdd046705280bf8f8572
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/wm8960/Makefile
@@ -0,0 +1,35 @@
+
+
+_uname_r := $(shell uname -r)
+_BUILD   := /lib/modules/$(_uname_r)/build
+_PWD     := $(shell pwd)
+_DEPMOD  ?= depmod -a
+
+# If KERNELRELEASE is defined, we've been invoked from the
+# kernel build system and can use its language
+ifneq ($(KERNELRELEASE),)
+
+snd-soc-imx-wm8960-objs := imx-wm8960.o
+obj-m += imx-wm8960.o
+
+else
+_class  := drivers/input
+
+DEST  := /lib/modules/$(_uname_r)/kernel
+
+all:
+	make -C ${_BUILD} M=$(_PWD) modules
+
+clean:
+	make -C ${_BUILD} M=$(_PWD) clean
+
+install:
+	cp imx-wm8960.ko ${DEST}/${_class}/
+	$(_DEPMOD)
+
+uninstall:
+	rm -f ${DEST}/${_class}/imx-wm8960.ko 
+	$(_DEPMOD)
+
+.PHONY: all clean install uninstall
+endif
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/wm8960/README.md b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/wm8960/README.md
new file mode 100644
index 0000000000000000000000000000000000000000..eff3ca9e1c0d0167c1655bb60f9536c583c7f190
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/wm8960/README.md
@@ -0,0 +1,21 @@
+## 安装alsa工具
+```bash
+sudo apt install alsa-utils
+```
+## 配置声卡
+
+```bash
+alsactl restore -f asound.state
+```
+
+若配置声卡失败，则会出现
+```bash
+pcm_write:2053:write error: Input/output error
+
+```
+## 播放音乐测试
+```
+aplay -D plughw:0,0 demo.wav
+```
+aplay只可以测试wav格式的音乐文件
+
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/wm8960/asound.state b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/wm8960/asound.state
new file mode 100644
index 0000000000000000000000000000000000000000..7d06420f3484f5aed84fc70cec72294040aa370c
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/wm8960/asound.state
@@ -0,0 +1,5548 @@
+state.wm8962audio {
+	control.1 {
+		iface MIXER
+		name 'Input Mixer Switch'
+		value.0 true
+		value.1 true
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 2
+		}
+	}
+	control.2 {
+		iface MIXER
+		name 'MIXINL IN2L Volume'
+		value 5
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 7'
+			dbmin -1500
+			dbmax 600
+			dbvalue.0 0
+		}
+	}
+	control.3 {
+		iface MIXER
+		name 'MIXINL PGA Volume'
+		value 0
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 7'
+			dbmin 0
+			dbmax 3000
+			dbvalue.0 0
+		}
+	}
+	control.4 {
+		iface MIXER
+		name 'MIXINL IN3L Volume'
+		value 5
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 7'
+			dbmin -1500
+			dbmax 600
+			dbvalue.0 0
+		}
+	}
+	control.5 {
+		iface MIXER
+		name 'MIXINR IN2R Volume'
+		value 5
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 7'
+			dbmin -1500
+			dbmax 600
+			dbvalue.0 0
+		}
+	}
+	control.6 {
+		iface MIXER
+		name 'MIXINR PGA Volume'
+		value 0
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 7'
+			dbmin 0
+			dbmax 3000
+			dbvalue.0 0
+		}
+	}
+	control.7 {
+		iface MIXER
+		name 'MIXINR IN3R Volume'
+		value 7
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 7'
+			dbmin -1500
+			dbmax 600
+			dbvalue.0 600
+		}
+	}
+	control.8 {
+		iface MIXER
+		name 'Digital Capture Volume'
+		value.0 108
+		value.1 108
+		comment {
+			access 'read write'
+			type INTEGER
+			count 2
+			range '0 - 127'
+			dbmin -9999999
+			dbmax 2325
+			dbvalue.0 900
+			dbvalue.1 900
+		}
+	}
+	control.9 {
+		iface MIXER
+		name 'Capture Volume'
+		value.0 40
+		value.1 40
+		comment {
+			access 'read write'
+			type INTEGER
+			count 2
+			range '0 - 63'
+			dbmin -2325
+			dbmax 2400
+			dbvalue.0 675
+			dbvalue.1 675
+		}
+	}
+	control.10 {
+		iface MIXER
+		name 'Capture Switch'
+		value.0 true
+		value.1 true
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 2
+		}
+	}
+	control.11 {
+		iface MIXER
+		name 'Capture ZC Switch'
+		value.0 true
+		value.1 true
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 2
+		}
+	}
+	control.12 {
+		iface MIXER
+		name 'Capture HPF Switch'
+		value true
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.13 {
+		iface MIXER
+		name 'Capture HPF Mode'
+		value Hi-fi
+		comment {
+			access 'read write'
+			type ENUMERATED
+			count 1
+			item.0 Hi-fi
+			item.1 Application
+		}
+	}
+	control.14 {
+		iface MIXER
+		name 'Capture HPF Cutoff'
+		value 0
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 7'
+		}
+	}
+	control.15 {
+		iface MIXER
+		name 'Capture LHPF Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.16 {
+		iface MIXER
+		name 'Capture LHPF Mode'
+		value LPF
+		comment {
+			access 'read write'
+			type ENUMERATED
+			count 1
+			item.0 LPF
+			item.1 HPF
+		}
+	}
+	control.17 {
+		iface MIXER
+		name 'Sidetone Volume'
+		value.0 0
+		value.1 0
+		comment {
+			access 'read write'
+			type INTEGER
+			count 2
+			range '0 - 12'
+			dbmin -3600
+			dbmax 0
+			dbvalue.0 -3600
+			dbvalue.1 -3600
+		}
+	}
+	control.18 {
+		iface MIXER
+		name 'Digital Playback Volume'
+		value.0 96
+		value.1 96
+		comment {
+			access 'read write'
+			type INTEGER
+			count 2
+			range '0 - 127'
+			dbmin -9999999
+			dbmax 2325
+			dbvalue.0 0
+			dbvalue.1 0
+		}
+	}
+	control.19 {
+		iface MIXER
+		name 'DAC High Performance Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.20 {
+		iface MIXER
+		name 'DAC L/R Swap Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.21 {
+		iface MIXER
+		name 'ADC L/R Swap Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.22 {
+		iface MIXER
+		name 'ADC High Performance Switch'
+		value true
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.23 {
+		iface MIXER
+		name 'Beep Volume'
+		value 0
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 15'
+			dbmin -9999999
+			dbmax -600
+			dbvalue.0 -9999999
+		}
+	}
+	control.24 {
+		iface MIXER
+		name 'Headphone Volume'
+		value.0 93
+		value.1 93
+		comment {
+			access 'read write'
+			type INTEGER
+			count 2
+			range '0 - 127'
+			dbmin -9999999
+			dbmax 600
+			dbvalue.0 -2800
+			dbvalue.1 -2800
+		}
+	}
+	control.25 {
+		iface MIXER
+		name 'Headphone Switch'
+		value.0 true
+		value.1 true
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 2
+		}
+	}
+	control.26 {
+		iface MIXER
+		name 'Headphone ZC Switch'
+		value.0 false
+		value.1 false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 2
+		}
+	}
+	control.27 {
+		iface MIXER
+		name 'Headphone Aux Volume'
+		value.0 7
+		value.1 7
+		comment {
+			access 'read write'
+			type INTEGER
+			count 2
+			range '0 - 7'
+			dbmin -700
+			dbmax 0
+			dbvalue.0 0
+			dbvalue.1 0
+		}
+	}
+	control.28 {
+		iface MIXER
+		name 'Headphone Mixer Switch'
+		value.0 false
+		value.1 false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 2
+		}
+	}
+	control.29 {
+		iface MIXER
+		name 'HPMIXL IN4L Volume'
+		value 7
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 7'
+			dbmin -1500
+			dbmax 600
+			dbvalue.0 600
+		}
+	}
+	control.30 {
+		iface MIXER
+		name 'HPMIXL IN4R Volume'
+		value 7
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 7'
+			dbmin -1500
+			dbmax 600
+			dbvalue.0 600
+		}
+	}
+	control.31 {
+		iface MIXER
+		name 'HPMIXL MIXINL Volume'
+		value 1
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 1'
+			dbmin -600
+			dbmax 0
+			dbvalue.0 0
+		}
+	}
+	control.32 {
+		iface MIXER
+		name 'HPMIXL MIXINR Volume'
+		value 1
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 1'
+			dbmin -600
+			dbmax 0
+			dbvalue.0 0
+		}
+	}
+	control.33 {
+		iface MIXER
+		name 'HPMIXR IN4L Volume'
+		value 7
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 7'
+			dbmin -1500
+			dbmax 600
+			dbvalue.0 600
+		}
+	}
+	control.34 {
+		iface MIXER
+		name 'HPMIXR IN4R Volume'
+		value 7
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 7'
+			dbmin -1500
+			dbmax 600
+			dbvalue.0 600
+		}
+	}
+	control.35 {
+		iface MIXER
+		name 'HPMIXR MIXINL Volume'
+		value 1
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 1'
+			dbmin -600
+			dbmax 0
+			dbvalue.0 0
+		}
+	}
+	control.36 {
+		iface MIXER
+		name 'HPMIXR MIXINR Volume'
+		value 1
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 1'
+			dbmin -600
+			dbmax 0
+			dbvalue.0 0
+		}
+	}
+	control.37 {
+		iface MIXER
+		name 'Speaker Boost Volume'
+		value 3
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 7'
+			dbmin 0
+			dbmax 1200
+			dbvalue.0 450
+		}
+	}
+	control.38 {
+		iface MIXER
+		name 'EQ Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.39 {
+		iface MIXER
+		name 'EQ1 Volume'
+		value.0 12
+		value.1 12
+		comment {
+			access 'read write'
+			type INTEGER
+			count 2
+			range '0 - 31'
+			dbmin -1200
+			dbmax 1900
+			dbvalue.0 0
+			dbvalue.1 0
+		}
+	}
+	control.40 {
+		iface MIXER
+		name 'EQ2 Volume'
+		value.0 12
+		value.1 12
+		comment {
+			access 'read write'
+			type INTEGER
+			count 2
+			range '0 - 31'
+			dbmin -1200
+			dbmax 1900
+			dbvalue.0 0
+			dbvalue.1 0
+		}
+	}
+	control.41 {
+		iface MIXER
+		name 'EQ3 Volume'
+		value.0 12
+		value.1 12
+		comment {
+			access 'read write'
+			type INTEGER
+			count 2
+			range '0 - 31'
+			dbmin -1200
+			dbmax 1900
+			dbvalue.0 0
+			dbvalue.1 0
+		}
+	}
+	control.42 {
+		iface MIXER
+		name 'EQ4 Volume'
+		value.0 12
+		value.1 12
+		comment {
+			access 'read write'
+			type INTEGER
+			count 2
+			range '0 - 31'
+			dbmin -1200
+			dbmax 1900
+			dbvalue.0 0
+			dbvalue.1 0
+		}
+	}
+	control.43 {
+		iface MIXER
+		name 'EQ5 Volume'
+		value.0 12
+		value.1 12
+		comment {
+			access 'read write'
+			type INTEGER
+			count 2
+			range '0 - 31'
+			dbmin -1200
+			dbmax 1900
+			dbvalue.0 0
+			dbvalue.1 0
+		}
+	}
+	control.44 {
+		iface MIXER
+		name 'EQL Coefficients'
+		value '0fca040000d81eb5f1450b7501c51c58f3730a540558168ef82907ad1103056405594000'
+		comment {
+			access 'read write'
+			type BYTES
+			count 36
+		}
+	}
+	control.45 {
+		iface MIXER
+		name 'EQR Coefficients'
+		value '0fca040000d81eb5f1450b7501c51c58f3730a540558168ef82907ad1103056405594000'
+		comment {
+			access 'read write'
+			type BYTES
+			count 36
+		}
+	}
+	control.46 {
+		iface MIXER
+		name '3D Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.47 {
+		iface MIXER
+		name '3D Coefficients'
+		value '0040000000000000'
+		comment {
+			access 'read write'
+			type BYTES
+			count 8
+		}
+	}
+	control.48 {
+		iface MIXER
+		name 'DF1 Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.49 {
+		iface MIXER
+		name 'DF1 Coefficients'
+		value '0000000000000000000000000000'
+		comment {
+			access 'read write'
+			type BYTES
+			count 14
+		}
+	}
+	control.50 {
+		iface MIXER
+		name 'DRC Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.51 {
+		iface MIXER
+		name 'DRC Coefficients'
+		value '000c0925000000000000'
+		comment {
+			access 'read write'
+			type BYTES
+			count 10
+		}
+	}
+	control.52 {
+		iface MIXER
+		name 'VSS Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.53 {
+		iface MIXER
+		name 'VSS Coefficients'
+		value '008c020000350700003a4100008b7d00003a4100008cfee800780000003fb260002d18180020000000f1834000fb830000eeaec000fbac4000f17f8000f43b4000f5fb0000ea10c000fcc58000e275c00004b48000d4f9800004914000d8a48000023dc000cf7a8000dc060000f2dac000baf340000a7940001c068000fd2d00001ce840000ddc4000fc9d000009558000fe7e80000eab4000f99880000987c000fd2c400009480000035f400000870000fae4c000000b400004e18000011f4000f8b00000fbcbc00004f3800007df4000ff070000efd70000fbaf4000108a80001107c000e0080000d276000020cf400030234000fd69c0002835000006330000d9f6c000f33340000f420000040c8000fb3f8000f757c0000354000000c6c0000312c000fd8580'
+		comment {
+			access 'read write'
+			type BYTES
+			count 296
+		}
+	}
+	control.54 {
+		iface MIXER
+		name 'HPF1 Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.55 {
+		iface MIXER
+		name 'HPF2 Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.56 {
+		iface MIXER
+		name 'HPF Coefficients'
+		value '0000'
+		comment {
+			access 'read write'
+			type BYTES
+			count 2
+		}
+	}
+	control.57 {
+		iface MIXER
+		name 'HD Bass Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.58 {
+		iface MIXER
+		name 'HD Bass Coefficients'
+		value '0002bd12007c586c00538121003f8bd80032f52d0065ac8c006be08700721483007214830043352500066a4a0043607900080000000100000059999a'
+		comment {
+			access 'read write'
+			type BYTES
+			count 60
+		}
+	}
+	control.59 {
+		iface MIXER
+		name 'ALC Switch'
+		value.0 false
+		value.1 false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 2
+		}
+	}
+	control.60 {
+		iface MIXER
+		name ALC1
+		value '007b'
+		comment {
+			access 'read write'
+			type BYTES
+			count 2
+		}
+	}
+	control.61 {
+		iface MIXER
+		name ALC2
+		value '0000'
+		comment {
+			access 'read write'
+			type BYTES
+			count 2
+		}
+	}
+	control.62 {
+		iface MIXER
+		name ALC3
+		value '1c32'
+		comment {
+			access 'read write'
+			type BYTES
+			count 2
+		}
+	}
+	control.63 {
+		iface MIXER
+		name 'Noise Gate'
+		value '3200'
+		comment {
+			access 'read write'
+			type BYTES
+			count 2
+		}
+	}
+	control.64 {
+		iface MIXER
+		name 'Speaker Volume'
+		value.0 114
+		value.1 114
+		comment {
+			access 'read write'
+			type INTEGER
+			count 2
+			range '0 - 127'
+			dbmin -9999999
+			dbmax 600
+			dbvalue.0 -700
+			dbvalue.1 -700
+		}
+	}
+	control.65 {
+		iface MIXER
+		name 'Speaker Switch'
+		value.0 true
+		value.1 true
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 2
+		}
+	}
+	control.66 {
+		iface MIXER
+		name 'Speaker ZC Switch'
+		value.0 false
+		value.1 false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 2
+		}
+	}
+	control.67 {
+		iface MIXER
+		name 'Speaker Mixer Switch'
+		value.0 false
+		value.1 false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 2
+		}
+	}
+	control.68 {
+		iface MIXER
+		name 'SPKOUTL Mixer IN4L Volume'
+		value 7
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 7'
+			dbmin -1500
+			dbmax 600
+			dbvalue.0 600
+		}
+	}
+	control.69 {
+		iface MIXER
+		name 'SPKOUTL Mixer IN4R Volume'
+		value 7
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 7'
+			dbmin -1500
+			dbmax 600
+			dbvalue.0 600
+		}
+	}
+	control.70 {
+		iface MIXER
+		name 'SPKOUTL Mixer MIXINL Volume'
+		value 1
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 1'
+			dbmin -600
+			dbmax 0
+			dbvalue.0 0
+		}
+	}
+	control.71 {
+		iface MIXER
+		name 'SPKOUTL Mixer MIXINR Volume'
+		value 1
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 1'
+			dbmin -600
+			dbmax 0
+			dbvalue.0 0
+		}
+	}
+	control.72 {
+		iface MIXER
+		name 'SPKOUTL Mixer DACL Volume'
+		value 0
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 1'
+			dbmin -600
+			dbmax 0
+			dbvalue.0 -600
+		}
+	}
+	control.73 {
+		iface MIXER
+		name 'SPKOUTL Mixer DACR Volume'
+		value 0
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 1'
+			dbmin -600
+			dbmax 0
+			dbvalue.0 -600
+		}
+	}
+	control.74 {
+		iface MIXER
+		name 'SPKOUTR Mixer IN4L Volume'
+		value 7
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 7'
+			dbmin -1500
+			dbmax 600
+			dbvalue.0 600
+		}
+	}
+	control.75 {
+		iface MIXER
+		name 'SPKOUTR Mixer IN4R Volume'
+		value 7
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 7'
+			dbmin -1500
+			dbmax 600
+			dbvalue.0 600
+		}
+	}
+	control.76 {
+		iface MIXER
+		name 'SPKOUTR Mixer MIXINL Volume'
+		value 1
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 1'
+			dbmin -600
+			dbmax 0
+			dbvalue.0 0
+		}
+	}
+	control.77 {
+		iface MIXER
+		name 'SPKOUTR Mixer MIXINR Volume'
+		value 1
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 1'
+			dbmin -600
+			dbmax 0
+			dbvalue.0 0
+		}
+	}
+	control.78 {
+		iface MIXER
+		name 'SPKOUTR Mixer DACL Volume'
+		value 0
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 1'
+			dbmin -600
+			dbmax 0
+			dbvalue.0 -600
+		}
+	}
+	control.79 {
+		iface MIXER
+		name 'SPKOUTR Mixer DACR Volume'
+		value 0
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 1'
+			dbmin -600
+			dbmax 0
+			dbvalue.0 -600
+		}
+	}
+	control.80 {
+		iface MIXER
+		name 'SPKOUTR PGA'
+		value DAC
+		comment {
+			access 'read write'
+			type ENUMERATED
+			count 1
+			item.0 DAC
+			item.1 Mixer
+		}
+	}
+	control.81 {
+		iface MIXER
+		name 'SPKOUTL PGA'
+		value DAC
+		comment {
+			access 'read write'
+			type ENUMERATED
+			count 1
+			item.0 DAC
+			item.1 Mixer
+		}
+	}
+	control.82 {
+		iface MIXER
+		name 'SPKOUTR Mixer DACL Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.83 {
+		iface MIXER
+		name 'SPKOUTR Mixer DACR Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.84 {
+		iface MIXER
+		name 'SPKOUTR Mixer MIXINL Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.85 {
+		iface MIXER
+		name 'SPKOUTR Mixer MIXINR Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.86 {
+		iface MIXER
+		name 'SPKOUTR Mixer IN4L Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.87 {
+		iface MIXER
+		name 'SPKOUTR Mixer IN4R Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.88 {
+		iface MIXER
+		name 'SPKOUTL Mixer DACL Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.89 {
+		iface MIXER
+		name 'SPKOUTL Mixer DACR Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.90 {
+		iface MIXER
+		name 'SPKOUTL Mixer MIXINL Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.91 {
+		iface MIXER
+		name 'SPKOUTL Mixer MIXINR Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.92 {
+		iface MIXER
+		name 'SPKOUTL Mixer IN4L Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.93 {
+		iface MIXER
+		name 'SPKOUTL Mixer IN4R Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.94 {
+		iface MIXER
+		name 'HPOUTR PGA'
+		value DAC
+		comment {
+			access 'read write'
+			type ENUMERATED
+			count 1
+			item.0 DAC
+			item.1 Mixer
+		}
+	}
+	control.95 {
+		iface MIXER
+		name 'HPOUTL PGA'
+		value DAC
+		comment {
+			access 'read write'
+			type ENUMERATED
+			count 1
+			item.0 DAC
+			item.1 Mixer
+		}
+	}
+	control.96 {
+		iface MIXER
+		name 'HPMIXR DACL Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.97 {
+		iface MIXER
+		name 'HPMIXR DACR Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.98 {
+		iface MIXER
+		name 'HPMIXR MIXINL Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.99 {
+		iface MIXER
+		name 'HPMIXR MIXINR Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.100 {
+		iface MIXER
+		name 'HPMIXR IN4L Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.101 {
+		iface MIXER
+		name 'HPMIXR IN4R Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.102 {
+		iface MIXER
+		name 'HPMIXL DACL Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.103 {
+		iface MIXER
+		name 'HPMIXL DACR Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.104 {
+		iface MIXER
+		name 'HPMIXL MIXINL Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.105 {
+		iface MIXER
+		name 'HPMIXL MIXINR Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.106 {
+		iface MIXER
+		name 'HPMIXL IN4L Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.107 {
+		iface MIXER
+		name 'HPMIXL IN4R Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.108 {
+		iface MIXER
+		name STR
+		value None
+		comment {
+			access 'read write'
+			type ENUMERATED
+			count 1
+			item.0 None
+			item.1 Left
+			item.2 Right
+		}
+	}
+	control.109 {
+		iface MIXER
+		name STL
+		value None
+		comment {
+			access 'read write'
+			type ENUMERATED
+			count 1
+			item.0 None
+			item.1 Left
+			item.2 Right
+		}
+	}
+	control.110 {
+		iface MIXER
+		name 'MIXINR IN2R Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.111 {
+		iface MIXER
+		name 'MIXINR IN3R Switch'
+		value true
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.112 {
+		iface MIXER
+		name 'MIXINR PGA Switch'
+		value true
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.113 {
+		iface MIXER
+		name 'MIXINL IN2L Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.114 {
+		iface MIXER
+		name 'MIXINL IN3L Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.115 {
+		iface MIXER
+		name 'MIXINL PGA Switch'
+		value true
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.116 {
+		iface MIXER
+		name 'INPGAR IN1R Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.117 {
+		iface MIXER
+		name 'INPGAR IN2R Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.118 {
+		iface MIXER
+		name 'INPGAR IN3R Switch'
+		value true
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.119 {
+		iface MIXER
+		name 'INPGAR IN4R Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.120 {
+		iface MIXER
+		name 'INPGAL IN1L Switch'
+		value true
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.121 {
+		iface MIXER
+		name 'INPGAL IN2L Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.122 {
+		iface MIXER
+		name 'INPGAL IN3L Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.123 {
+		iface MIXER
+		name 'INPGAL IN4L Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.124 {
+		iface CARD
+		name 'Headphone Jack'
+		value true
+		comment {
+			access read
+			type BOOLEAN
+			count 1
+		}
+	}
+}
+state.wm8960audio {
+	control.1 {
+		iface MIXER
+		name 'Capture Volume'
+		value.0 35
+		value.1 35
+		comment {
+			access 'read write'
+			type INTEGER
+			count 2
+			range '0 - 63'
+			dbmin -1725
+			dbmax 3000
+			dbvalue.0 900
+			dbvalue.1 900
+		}
+	}
+	control.2 {
+		iface MIXER
+		name 'Capture Volume ZC Switch'
+		value.0 0
+		value.1 0
+		comment {
+			access 'read write'
+			type INTEGER
+			count 2
+			range '0 - 1'
+		}
+	}
+	control.3 {
+		iface MIXER
+		name 'Capture Switch'
+		value.0 true
+		value.1 true
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 2
+		}
+	}
+	control.4 {
+		iface MIXER
+		name 'Left Input Boost Mixer LINPUT3 Volume'
+		value 0
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 7'
+			dbmin -9999999
+			dbmax 600
+			dbvalue.0 -9999999
+		}
+	}
+	control.5 {
+		iface MIXER
+		name 'Left Input Boost Mixer LINPUT2 Volume'
+		value 0
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 7'
+			dbmin -9999999
+			dbmax 600
+			dbvalue.0 -9999999
+		}
+	}
+	control.6 {
+		iface MIXER
+		name 'Right Input Boost Mixer RINPUT3 Volume'
+		value 0
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 7'
+			dbmin -9999999
+			dbmax 600
+			dbvalue.0 -9999999
+		}
+	}
+	control.7 {
+		iface MIXER
+		name 'Right Input Boost Mixer RINPUT2 Volume'
+		value 0
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 7'
+			dbmin -9999999
+			dbmax 600
+			dbvalue.0 -9999999
+		}
+	}
+	control.8 {
+		iface MIXER
+		name 'Right Input Boost Mixer RINPUT1 Volume'
+		value 0
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 3'
+			dbmin 0
+			dbmax 2900
+			dbvalue.0 0
+		}
+	}
+	control.9 {
+		iface MIXER
+		name 'Left Input Boost Mixer LINPUT1 Volume'
+		value 0
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 3'
+			dbmin 0
+			dbmax 2900
+			dbvalue.0 0
+		}
+	}
+	control.10 {
+		iface MIXER
+		name 'Playback Volume'
+		value.0 235
+		value.1 235
+		comment {
+			access 'read write'
+			type INTEGER
+			count 2
+			range '0 - 255'
+			dbmin -9999999
+			dbmax 0
+			dbvalue.0 -1000
+			dbvalue.1 -1000
+		}
+	}
+	control.11 {
+		iface MIXER
+		name 'Headphone Playback Volume'
+		value.0 101
+		value.1 101
+		comment {
+			access 'read write'
+			type INTEGER
+			count 2
+			range '0 - 127'
+			dbmin -9999999
+			dbmax 600
+			dbvalue.0 -2000
+			dbvalue.1 -2000
+		}
+	}
+	control.12 {
+		iface MIXER
+		name 'Headphone Playback ZC Switch'
+		value.0 false
+		value.1 false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 2
+		}
+	}
+	control.13 {
+		iface MIXER
+		name 'Speaker Playback Volume'
+		value.0 110
+		value.1 110
+		comment {
+			access 'read write'
+			type INTEGER
+			count 2
+			range '0 - 127'
+			dbmin -9999999
+			dbmax 600
+			dbvalue.0 -1100
+			dbvalue.1 -1100
+		}
+	}
+	control.14 {
+		iface MIXER
+		name 'Speaker Playback ZC Switch'
+		value.0 false
+		value.1 false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 2
+		}
+	}
+	control.15 {
+		iface MIXER
+		name 'Speaker DC Volume'
+		value 0
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 5'
+		}
+	}
+	control.16 {
+		iface MIXER
+		name 'Speaker AC Volume'
+		value 0
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 5'
+		}
+	}
+	control.17 {
+		iface MIXER
+		name 'PCM Playback -6dB Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.18 {
+		iface MIXER
+		name 'ADC Polarity'
+		value 'No Inversion'
+		comment {
+			access 'read write'
+			type ENUMERATED
+			count 1
+			item.0 'No Inversion'
+			item.1 'Left Inverted'
+			item.2 'Right Inverted'
+			item.3 'Stereo Inversion'
+		}
+	}
+	control.19 {
+		iface MIXER
+		name 'ADC High Pass Filter Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.20 {
+		iface MIXER
+		name 'DAC Polarity'
+		value 'No Inversion'
+		comment {
+			access 'read write'
+			type ENUMERATED
+			count 1
+			item.0 'No Inversion'
+			item.1 'Left Inverted'
+			item.2 'Right Inverted'
+			item.3 'Stereo Inversion'
+		}
+	}
+	control.21 {
+		iface MIXER
+		name 'DAC Deemphasis Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.22 {
+		iface MIXER
+		name '3D Filter Upper Cut-Off'
+		value High
+		comment {
+			access 'read write'
+			type ENUMERATED
+			count 1
+			item.0 High
+			item.1 Low
+		}
+	}
+	control.23 {
+		iface MIXER
+		name '3D Filter Lower Cut-Off'
+		value Low
+		comment {
+			access 'read write'
+			type ENUMERATED
+			count 1
+			item.0 Low
+			item.1 High
+		}
+	}
+	control.24 {
+		iface MIXER
+		name '3D Volume'
+		value 0
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 15'
+		}
+	}
+	control.25 {
+		iface MIXER
+		name '3D Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.26 {
+		iface MIXER
+		name 'ALC Function'
+		value Off
+		comment {
+			access 'read write'
+			type ENUMERATED
+			count 1
+			item.0 Off
+			item.1 Right
+			item.2 Left
+			item.3 Stereo
+		}
+	}
+	control.27 {
+		iface MIXER
+		name 'ALC Max Gain'
+		value 7
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 7'
+		}
+	}
+	control.28 {
+		iface MIXER
+		name 'ALC Target'
+		value 4
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 15'
+		}
+	}
+	control.29 {
+		iface MIXER
+		name 'ALC Min Gain'
+		value 0
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 7'
+		}
+	}
+	control.30 {
+		iface MIXER
+		name 'ALC Hold Time'
+		value 0
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 15'
+		}
+	}
+	control.31 {
+		iface MIXER
+		name 'ALC Mode'
+		value ALC
+		comment {
+			access 'read write'
+			type ENUMERATED
+			count 1
+			item.0 ALC
+			item.1 Limiter
+		}
+	}
+	control.32 {
+		iface MIXER
+		name 'ALC Decay'
+		value 3
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 15'
+		}
+	}
+	control.33 {
+		iface MIXER
+		name 'ALC Attack'
+		value 2
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 15'
+		}
+	}
+	control.34 {
+		iface MIXER
+		name 'Noise Gate Threshold'
+		value 0
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 31'
+		}
+	}
+	control.35 {
+		iface MIXER
+		name 'Noise Gate Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.36 {
+		iface MIXER
+		name 'ADC PCM Capture Volume'
+		value.0 195
+		value.1 195
+		comment {
+			access 'read write'
+			type INTEGER
+			count 2
+			range '0 - 255'
+			dbmin -9999999
+			dbmax 3000
+			dbvalue.0 0
+			dbvalue.1 0
+		}
+	}
+	control.37 {
+		iface MIXER
+		name 'Left Output Mixer Boost Bypass Volume'
+		value 2
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 7'
+			dbmin -2100
+			dbmax 0
+			dbvalue.0 -1500
+		}
+	}
+	control.38 {
+		iface MIXER
+		name 'Left Output Mixer LINPUT3 Volume'
+		value 2
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 7'
+			dbmin -2100
+			dbmax 0
+			dbvalue.0 -1500
+		}
+	}
+	control.39 {
+		iface MIXER
+		name 'Right Output Mixer Boost Bypass Volume'
+		value 2
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 7'
+			dbmin -2100
+			dbmax 0
+			dbvalue.0 -1500
+		}
+	}
+	control.40 {
+		iface MIXER
+		name 'Right Output Mixer RINPUT3 Volume'
+		value 2
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 7'
+			dbmin -2100
+			dbmax 0
+			dbvalue.0 -1500
+		}
+	}
+	control.41 {
+		iface MIXER
+		name 'ADC Data Output Select'
+		value 'Left Data = Left ADC;  Right Data = Left ADC'
+		comment {
+			access 'read write'
+			type ENUMERATED
+			count 1
+			item.0 'Left Data = Left ADC;  Right Data = Right ADC'
+			item.1 'Left Data = Left ADC;  Right Data = Left ADC'
+			item.2 'Left Data = Right ADC; Right Data = Right ADC'
+			item.3 'Left Data = Right ADC; Right Data = Left ADC'
+		}
+	}
+	control.42 {
+		iface MIXER
+		name 'DAC Mono Mix'
+		value Stereo
+		comment {
+			access 'read write'
+			type ENUMERATED
+			count 1
+			item.0 Stereo
+			item.1 Mono
+		}
+	}
+	control.43 {
+		iface MIXER
+		name 'Left Boost Mixer LINPUT2 Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.44 {
+		iface MIXER
+		name 'Left Boost Mixer LINPUT3 Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.45 {
+		iface MIXER
+		name 'Left Boost Mixer LINPUT1 Switch'
+		value true
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.46 {
+		iface MIXER
+		name 'Right Boost Mixer RINPUT2 Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.47 {
+		iface MIXER
+		name 'Right Boost Mixer RINPUT3 Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.48 {
+		iface MIXER
+		name 'Right Boost Mixer RINPUT1 Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.49 {
+		iface MIXER
+		name 'Left Input Mixer Boost Switch'
+		value true
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.50 {
+		iface MIXER
+		name 'Right Input Mixer Boost Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.51 {
+		iface MIXER
+		name 'Left Output Mixer PCM Playback Switch'
+		value true
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.52 {
+		iface MIXER
+		name 'Left Output Mixer LINPUT3 Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.53 {
+		iface MIXER
+		name 'Left Output Mixer Boost Bypass Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.54 {
+		iface MIXER
+		name 'Right Output Mixer PCM Playback Switch'
+		value true
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.55 {
+		iface MIXER
+		name 'Right Output Mixer RINPUT3 Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.56 {
+		iface MIXER
+		name 'Right Output Mixer Boost Bypass Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.57 {
+		iface MIXER
+		name 'Mono Output Mixer Left Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.58 {
+		iface MIXER
+		name 'Mono Output Mixer Right Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+}
+state.wm8958audio {
+	control.1 {
+		iface MIXER
+		name 'AIF1.1 DRC'
+		value '00980845000000000000'
+		comment {
+			access 'read write'
+			type BYTES
+			count 10
+		}
+	}
+	control.2 {
+		iface MIXER
+		name 'AIF1.2 DRC'
+		value '00980845000000000000'
+		comment {
+			access 'read write'
+			type BYTES
+			count 10
+		}
+	}
+	control.3 {
+		iface MIXER
+		name 'AIF2 DRC'
+		value '00980845000000000000'
+		comment {
+			access 'read write'
+			type BYTES
+			count 10
+		}
+	}
+	control.4 {
+		iface MIXER
+		name 'AIF1DAC1 EQ1 Volume'
+		value 12
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 31'
+			dbmin -1200
+			dbmax 1900
+			dbvalue.0 0
+		}
+	}
+	control.5 {
+		iface MIXER
+		name 'AIF1DAC1 EQ2 Volume'
+		value 12
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 31'
+			dbmin -1200
+			dbmax 1900
+			dbvalue.0 0
+		}
+	}
+	control.6 {
+		iface MIXER
+		name 'AIF1DAC1 EQ3 Volume'
+		value 12
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 31'
+			dbmin -1200
+			dbmax 1900
+			dbvalue.0 0
+		}
+	}
+	control.7 {
+		iface MIXER
+		name 'AIF1DAC1 EQ4 Volume'
+		value 12
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 31'
+			dbmin -1200
+			dbmax 1900
+			dbvalue.0 0
+		}
+	}
+	control.8 {
+		iface MIXER
+		name 'AIF1DAC1 EQ5 Volume'
+		value 12
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 31'
+			dbmin -1200
+			dbmax 1900
+			dbvalue.0 0
+		}
+	}
+	control.9 {
+		iface MIXER
+		name 'AIF1DAC2 EQ1 Volume'
+		value 12
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 31'
+			dbmin -1200
+			dbmax 1900
+			dbvalue.0 0
+		}
+	}
+	control.10 {
+		iface MIXER
+		name 'AIF1DAC2 EQ2 Volume'
+		value 12
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 31'
+			dbmin -1200
+			dbmax 1900
+			dbvalue.0 0
+		}
+	}
+	control.11 {
+		iface MIXER
+		name 'AIF1DAC2 EQ3 Volume'
+		value 12
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 31'
+			dbmin -1200
+			dbmax 1900
+			dbvalue.0 0
+		}
+	}
+	control.12 {
+		iface MIXER
+		name 'AIF1DAC2 EQ4 Volume'
+		value 12
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 31'
+			dbmin -1200
+			dbmax 1900
+			dbvalue.0 0
+		}
+	}
+	control.13 {
+		iface MIXER
+		name 'AIF1DAC2 EQ5 Volume'
+		value 12
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 31'
+			dbmin -1200
+			dbmax 1900
+			dbvalue.0 0
+		}
+	}
+	control.14 {
+		iface MIXER
+		name 'AIF2 EQ1 Volume'
+		value 12
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 31'
+			dbmin -1200
+			dbmax 1900
+			dbvalue.0 0
+		}
+	}
+	control.15 {
+		iface MIXER
+		name 'AIF2 EQ2 Volume'
+		value 12
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 31'
+			dbmin -1200
+			dbmax 1900
+			dbvalue.0 0
+		}
+	}
+	control.16 {
+		iface MIXER
+		name 'AIF2 EQ3 Volume'
+		value 12
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 31'
+			dbmin -1200
+			dbmax 1900
+			dbvalue.0 0
+		}
+	}
+	control.17 {
+		iface MIXER
+		name 'AIF2 EQ4 Volume'
+		value 12
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 31'
+			dbmin -1200
+			dbmax 1900
+			dbvalue.0 0
+		}
+	}
+	control.18 {
+		iface MIXER
+		name 'AIF2 EQ5 Volume'
+		value 12
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 31'
+			dbmin -1200
+			dbmax 1900
+			dbvalue.0 0
+		}
+	}
+	control.19 {
+		iface MIXER
+		name 'IN1L Volume'
+		value 11
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 31'
+			dbmin -1650
+			dbmax 3000
+			dbvalue.0 0
+		}
+	}
+	control.20 {
+		iface MIXER
+		name 'IN1L Switch'
+		value true
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.21 {
+		iface MIXER
+		name 'IN1L ZC Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.22 {
+		iface MIXER
+		name 'IN1R Volume'
+		value 11
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 31'
+			dbmin -1650
+			dbmax 3000
+			dbvalue.0 0
+		}
+	}
+	control.23 {
+		iface MIXER
+		name 'IN1R Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.24 {
+		iface MIXER
+		name 'IN1R ZC Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.25 {
+		iface MIXER
+		name 'IN2L Volume'
+		value 11
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 31'
+			dbmin -1650
+			dbmax 3000
+			dbvalue.0 0
+		}
+	}
+	control.26 {
+		iface MIXER
+		name 'IN2L Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.27 {
+		iface MIXER
+		name 'IN2L ZC Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.28 {
+		iface MIXER
+		name 'IN2R Volume'
+		value 11
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 31'
+			dbmin -1650
+			dbmax 3000
+			dbvalue.0 0
+		}
+	}
+	control.29 {
+		iface MIXER
+		name 'IN2R Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.30 {
+		iface MIXER
+		name 'IN2R ZC Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.31 {
+		iface MIXER
+		name 'MIXINL IN2L Volume'
+		value 0
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 1'
+			dbmin 0
+			dbmax 3000
+			dbvalue.0 0
+		}
+	}
+	control.32 {
+		iface MIXER
+		name 'MIXINL IN1L Volume'
+		value 0
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 1'
+			dbmin 0
+			dbmax 3000
+			dbvalue.0 0
+		}
+	}
+	control.33 {
+		iface MIXER
+		name 'MIXINL Output Record Volume'
+		value 0
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 7'
+			dbmin -9999999
+			dbmax 600
+			dbvalue.0 -9999999
+		}
+	}
+	control.34 {
+		iface MIXER
+		name 'MIXINL IN1LP Volume'
+		value 0
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 7'
+			dbmin -9999999
+			dbmax 600
+			dbvalue.0 -9999999
+		}
+	}
+	control.35 {
+		iface MIXER
+		name 'MIXINL Direct Voice Volume'
+		value 0
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 6'
+			dbmin -9999999
+			dbmax 300
+			dbvalue.0 -9999999
+		}
+	}
+	control.36 {
+		iface MIXER
+		name 'MIXINR IN2R Volume'
+		value 0
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 1'
+			dbmin 0
+			dbmax 3000
+			dbvalue.0 0
+		}
+	}
+	control.37 {
+		iface MIXER
+		name 'MIXINR IN1R Volume'
+		value 0
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 1'
+			dbmin 0
+			dbmax 3000
+			dbvalue.0 0
+		}
+	}
+	control.38 {
+		iface MIXER
+		name 'MIXINR Output Record Volume'
+		value 0
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 7'
+			dbmin -9999999
+			dbmax 600
+			dbvalue.0 -9999999
+		}
+	}
+	control.39 {
+		iface MIXER
+		name 'MIXINR IN1RP Volume'
+		value 0
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 7'
+			dbmin -9999999
+			dbmax 600
+			dbvalue.0 -9999999
+		}
+	}
+	control.40 {
+		iface MIXER
+		name 'MIXINR Direct Voice Volume'
+		value 0
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 6'
+			dbmin -9999999
+			dbmax 300
+			dbvalue.0 -9999999
+		}
+	}
+	control.41 {
+		iface MIXER
+		name 'Left Output Mixer IN2RN Volume'
+		value 7
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 7'
+			dbmin -2100
+			dbmax 0
+			dbvalue.0 0
+		}
+	}
+	control.42 {
+		iface MIXER
+		name 'Left Output Mixer IN2LN Volume'
+		value 7
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 7'
+			dbmin -2100
+			dbmax 0
+			dbvalue.0 0
+		}
+	}
+	control.43 {
+		iface MIXER
+		name 'Left Output Mixer IN2LP Volume'
+		value 7
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 7'
+			dbmin -2100
+			dbmax 0
+			dbvalue.0 0
+		}
+	}
+	control.44 {
+		iface MIXER
+		name 'Left Output Mixer IN1L Volume'
+		value 7
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 7'
+			dbmin -2100
+			dbmax 0
+			dbvalue.0 0
+		}
+	}
+	control.45 {
+		iface MIXER
+		name 'Left Output Mixer IN1R Volume'
+		value 7
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 7'
+			dbmin -2100
+			dbmax 0
+			dbvalue.0 0
+		}
+	}
+	control.46 {
+		iface MIXER
+		name 'Left Output Mixer Right Input Volume'
+		value 7
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 7'
+			dbmin -2100
+			dbmax 0
+			dbvalue.0 0
+		}
+	}
+	control.47 {
+		iface MIXER
+		name 'Left Output Mixer Left Input Volume'
+		value 7
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 7'
+			dbmin -2100
+			dbmax 0
+			dbvalue.0 0
+		}
+	}
+	control.48 {
+		iface MIXER
+		name 'Left Output Mixer DAC Volume'
+		value 7
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 7'
+			dbmin -2100
+			dbmax 0
+			dbvalue.0 0
+		}
+	}
+	control.49 {
+		iface MIXER
+		name 'Right Output Mixer IN2LN Volume'
+		value 7
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 7'
+			dbmin -2100
+			dbmax 0
+			dbvalue.0 0
+		}
+	}
+	control.50 {
+		iface MIXER
+		name 'Right Output Mixer IN2RN Volume'
+		value 7
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 7'
+			dbmin -2100
+			dbmax 0
+			dbvalue.0 0
+		}
+	}
+	control.51 {
+		iface MIXER
+		name 'Right Output Mixer IN1L Volume'
+		value 7
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 7'
+			dbmin -2100
+			dbmax 0
+			dbvalue.0 0
+		}
+	}
+	control.52 {
+		iface MIXER
+		name 'Right Output Mixer IN1R Volume'
+		value 7
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 7'
+			dbmin -2100
+			dbmax 0
+			dbvalue.0 0
+		}
+	}
+	control.53 {
+		iface MIXER
+		name 'Right Output Mixer IN2RP Volume'
+		value 7
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 7'
+			dbmin -2100
+			dbmax 0
+			dbvalue.0 0
+		}
+	}
+	control.54 {
+		iface MIXER
+		name 'Right Output Mixer Left Input Volume'
+		value 7
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 7'
+			dbmin -2100
+			dbmax 0
+			dbvalue.0 0
+		}
+	}
+	control.55 {
+		iface MIXER
+		name 'Right Output Mixer Right Input Volume'
+		value 7
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 7'
+			dbmin -2100
+			dbmax 0
+			dbvalue.0 0
+		}
+	}
+	control.56 {
+		iface MIXER
+		name 'Right Output Mixer DAC Volume'
+		value 7
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 7'
+			dbmin -2100
+			dbmax 0
+			dbvalue.0 0
+		}
+	}
+	control.57 {
+		iface MIXER
+		name 'Output Volume'
+		value.0 57
+		value.1 57
+		comment {
+			access 'read write'
+			type INTEGER
+			count 2
+			range '0 - 63'
+			dbmin -5700
+			dbmax 600
+			dbvalue.0 0
+			dbvalue.1 0
+		}
+	}
+	control.58 {
+		iface MIXER
+		name 'Output Switch'
+		value.0 true
+		value.1 true
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 2
+		}
+	}
+	control.59 {
+		iface MIXER
+		name 'Output ZC Switch'
+		value.0 true
+		value.1 true
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 2
+		}
+	}
+	control.60 {
+		iface MIXER
+		name 'Earpiece Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.61 {
+		iface MIXER
+		name 'Earpiece Volume'
+		value 1
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 1'
+			dbmin -600
+			dbmax 0
+			dbvalue.0 0
+		}
+	}
+	control.62 {
+		iface MIXER
+		name 'SPKL Input Volume'
+		value 1
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 1'
+			dbmin -300
+			dbmax 0
+			dbvalue.0 0
+		}
+	}
+	control.63 {
+		iface MIXER
+		name 'SPKL IN1LP Volume'
+		value 1
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 1'
+			dbmin -300
+			dbmax 0
+			dbvalue.0 0
+		}
+	}
+	control.64 {
+		iface MIXER
+		name 'SPKL Output Volume'
+		value 1
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 1'
+			dbmin -300
+			dbmax 0
+			dbvalue.0 0
+		}
+	}
+	control.65 {
+		iface MIXER
+		name 'SPKR Input Volume'
+		value 1
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 1'
+			dbmin -300
+			dbmax 0
+			dbvalue.0 0
+		}
+	}
+	control.66 {
+		iface MIXER
+		name 'SPKR IN1RP Volume'
+		value 1
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 1'
+			dbmin -300
+			dbmax 0
+			dbvalue.0 0
+		}
+	}
+	control.67 {
+		iface MIXER
+		name 'SPKR Output Volume'
+		value 1
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 1'
+			dbmin -300
+			dbmax 0
+			dbvalue.0 0
+		}
+	}
+	control.68 {
+		iface MIXER
+		name 'Speaker Mixer Volume'
+		value.0 3
+		value.1 3
+		comment {
+			access 'read write'
+			type INTEGER
+			count 2
+			range '0 - 3'
+			dbmin -9999999
+			dbmax 0
+			dbvalue.0 0
+			dbvalue.1 0
+		}
+	}
+	control.69 {
+		iface MIXER
+		name 'Speaker Volume'
+		value.0 60
+		value.1 60
+		comment {
+			access 'read write'
+			type INTEGER
+			count 2
+			range '0 - 63'
+			dbmin -5700
+			dbmax 600
+			dbvalue.0 300
+			dbvalue.1 300
+		}
+	}
+	control.70 {
+		iface MIXER
+		name 'Speaker Switch'
+		value.0 true
+		value.1 true
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 2
+		}
+	}
+	control.71 {
+		iface MIXER
+		name 'Speaker ZC Switch'
+		value.0 false
+		value.1 false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 2
+		}
+	}
+	control.72 {
+		iface MIXER
+		name 'Speaker Boost Volume'
+		value.0 0
+		value.1 0
+		comment {
+			access 'read write'
+			type INTEGER
+			count 2
+			range '0 - 7'
+			dbmin 0
+			dbmax 1200
+			dbvalue.0 0
+			dbvalue.1 0
+		}
+	}
+	control.73 {
+		iface MIXER
+		name 'Speaker Reference'
+		value SPKVDD/2
+		comment {
+			access 'read write'
+			type ENUMERATED
+			count 1
+			item.0 SPKVDD/2
+			item.1 VMID
+		}
+	}
+	control.74 {
+		iface MIXER
+		name 'Speaker Mode'
+		value 'Class D'
+		comment {
+			access 'read write'
+			type ENUMERATED
+			count 1
+			item.0 'Class D'
+			item.1 'Class AB'
+		}
+	}
+	control.75 {
+		iface MIXER
+		name 'Headphone Volume'
+		value.0 25
+		value.1 25
+		comment {
+			access 'read write'
+			type INTEGER
+			count 2
+			range '0 - 63'
+			dbmin -5700
+			dbmax 600
+			dbvalue.0 -3200
+			dbvalue.1 -3200
+		}
+	}
+	control.76 {
+		iface MIXER
+		name 'Headphone Switch'
+		value.0 true
+		value.1 true
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 2
+		}
+	}
+	control.77 {
+		iface MIXER
+		name 'Headphone ZC Switch'
+		value.0 true
+		value.1 true
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 2
+		}
+	}
+	control.78 {
+		iface MIXER
+		name 'LINEOUT1N Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.79 {
+		iface MIXER
+		name 'LINEOUT1P Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.80 {
+		iface MIXER
+		name 'LINEOUT1 Volume'
+		value 1
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 1'
+			dbmin -600
+			dbmax 0
+			dbvalue.0 0
+		}
+	}
+	control.81 {
+		iface MIXER
+		name 'LINEOUT2N Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.82 {
+		iface MIXER
+		name 'LINEOUT2P Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.83 {
+		iface MIXER
+		name 'LINEOUT2 Volume'
+		value 1
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 1'
+			dbmin -600
+			dbmax 0
+			dbvalue.0 0
+		}
+	}
+	control.84 {
+		iface MIXER
+		name 'AIF1ADC1 Volume'
+		value.0 96
+		value.1 96
+		comment {
+			access 'read write'
+			type INTEGER
+			count 2
+			range '0 - 119'
+			dbmin -9999999
+			dbmax 1725
+			dbvalue.0 0
+			dbvalue.1 0
+		}
+	}
+	control.85 {
+		iface MIXER
+		name 'AIF1ADC2 Volume'
+		value.0 96
+		value.1 96
+		comment {
+			access 'read write'
+			type INTEGER
+			count 2
+			range '0 - 119'
+			dbmin -9999999
+			dbmax 1725
+			dbvalue.0 0
+			dbvalue.1 0
+		}
+	}
+	control.86 {
+		iface MIXER
+		name 'AIF2ADC Volume'
+		value.0 96
+		value.1 96
+		comment {
+			access 'read write'
+			type INTEGER
+			count 2
+			range '0 - 119'
+			dbmin -9999999
+			dbmax 1725
+			dbvalue.0 0
+			dbvalue.1 0
+		}
+	}
+	control.87 {
+		iface MIXER
+		name 'AIF1ADCL Source'
+		value Left
+		comment {
+			access 'read write'
+			type ENUMERATED
+			count 1
+			item.0 Left
+			item.1 Right
+		}
+	}
+	control.88 {
+		iface MIXER
+		name 'AIF1ADCR Source'
+		value Left
+		comment {
+			access 'read write'
+			type ENUMERATED
+			count 1
+			item.0 Left
+			item.1 Right
+		}
+	}
+	control.89 {
+		iface MIXER
+		name 'AIF2ADCL Source'
+		value Left
+		comment {
+			access 'read write'
+			type ENUMERATED
+			count 1
+			item.0 Left
+			item.1 Right
+		}
+	}
+	control.90 {
+		iface MIXER
+		name 'AIF2ADCR Source'
+		value Right
+		comment {
+			access 'read write'
+			type ENUMERATED
+			count 1
+			item.0 Left
+			item.1 Right
+		}
+	}
+	control.91 {
+		iface MIXER
+		name 'AIF1DACL Source'
+		value Left
+		comment {
+			access 'read write'
+			type ENUMERATED
+			count 1
+			item.0 Left
+			item.1 Right
+		}
+	}
+	control.92 {
+		iface MIXER
+		name 'AIF1DACR Source'
+		value Right
+		comment {
+			access 'read write'
+			type ENUMERATED
+			count 1
+			item.0 Left
+			item.1 Right
+		}
+	}
+	control.93 {
+		iface MIXER
+		name 'AIF2DACL Source'
+		value Left
+		comment {
+			access 'read write'
+			type ENUMERATED
+			count 1
+			item.0 Left
+			item.1 Right
+		}
+	}
+	control.94 {
+		iface MIXER
+		name 'AIF2DACR Source'
+		value Right
+		comment {
+			access 'read write'
+			type ENUMERATED
+			count 1
+			item.0 Left
+			item.1 Right
+		}
+	}
+	control.95 {
+		iface MIXER
+		name 'AIF1DAC1 Volume'
+		value.0 96
+		value.1 96
+		comment {
+			access 'read write'
+			type INTEGER
+			count 2
+			range '0 - 96'
+			dbmin -9999999
+			dbmax 0
+			dbvalue.0 0
+			dbvalue.1 0
+		}
+	}
+	control.96 {
+		iface MIXER
+		name 'AIF1DAC2 Volume'
+		value.0 96
+		value.1 96
+		comment {
+			access 'read write'
+			type INTEGER
+			count 2
+			range '0 - 96'
+			dbmin -9999999
+			dbmax 0
+			dbvalue.0 0
+			dbvalue.1 0
+		}
+	}
+	control.97 {
+		iface MIXER
+		name 'AIF2DAC Volume'
+		value.0 96
+		value.1 96
+		comment {
+			access 'read write'
+			type INTEGER
+			count 2
+			range '0 - 96'
+			dbmin -9999999
+			dbmax 0
+			dbvalue.0 0
+			dbvalue.1 0
+		}
+	}
+	control.98 {
+		iface MIXER
+		name 'AIF1 Boost Volume'
+		value 0
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 3'
+			dbmin 0
+			dbmax 1800
+			dbvalue.0 0
+		}
+	}
+	control.99 {
+		iface MIXER
+		name 'AIF2 Boost Volume'
+		value 0
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 3'
+			dbmin 0
+			dbmax 1800
+			dbvalue.0 0
+		}
+	}
+	control.100 {
+		iface MIXER
+		name 'AIF1DAC1 EQ Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.101 {
+		iface MIXER
+		name 'AIF1DAC2 EQ Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.102 {
+		iface MIXER
+		name 'AIF2 EQ Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.103 {
+		iface MIXER
+		name 'AIF1DAC1 DRC Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.104 {
+		iface MIXER
+		name 'AIF1ADC1L DRC Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.105 {
+		iface MIXER
+		name 'AIF1ADC1R DRC Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.106 {
+		iface MIXER
+		name 'AIF1DAC2 DRC Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.107 {
+		iface MIXER
+		name 'AIF1ADC2L DRC Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.108 {
+		iface MIXER
+		name 'AIF1ADC2R DRC Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.109 {
+		iface MIXER
+		name 'AIF2DAC DRC Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.110 {
+		iface MIXER
+		name 'AIF2ADCL DRC Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.111 {
+		iface MIXER
+		name 'AIF2ADCR DRC Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.112 {
+		iface MIXER
+		name 'DAC1 Right Sidetone Volume'
+		value 0
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 12'
+			dbmin -3600
+			dbmax 0
+			dbvalue.0 -3600
+		}
+	}
+	control.113 {
+		iface MIXER
+		name 'DAC1 Left Sidetone Volume'
+		value 0
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 12'
+			dbmin -3600
+			dbmax 0
+			dbvalue.0 -3600
+		}
+	}
+	control.114 {
+		iface MIXER
+		name 'DAC2 Right Sidetone Volume'
+		value 0
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 12'
+			dbmin -3600
+			dbmax 0
+			dbvalue.0 -3600
+		}
+	}
+	control.115 {
+		iface MIXER
+		name 'DAC2 Left Sidetone Volume'
+		value 0
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 12'
+			dbmin -3600
+			dbmax 0
+			dbvalue.0 -3600
+		}
+	}
+	control.116 {
+		iface MIXER
+		name 'Sidetone HPF Mux'
+		value '2.7kHz'
+		comment {
+			access 'read write'
+			type ENUMERATED
+			count 1
+			item.0 '2.7kHz'
+			item.1 '1.35kHz'
+			item.2 '675Hz'
+			item.3 '370Hz'
+			item.4 '180Hz'
+			item.5 '90Hz'
+			item.6 '45Hz'
+		}
+	}
+	control.117 {
+		iface MIXER
+		name 'Sidetone HPF Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.118 {
+		iface MIXER
+		name 'AIF1ADC1 HPF Mode'
+		value HiFi
+		comment {
+			access 'read write'
+			type ENUMERATED
+			count 1
+			item.0 HiFi
+			item.1 'Voice 1'
+			item.2 'Voice 2'
+			item.3 'Voice 3'
+		}
+	}
+	control.119 {
+		iface MIXER
+		name 'AIF1ADC1 HPF Switch'
+		value.0 false
+		value.1 false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 2
+		}
+	}
+	control.120 {
+		iface MIXER
+		name 'AIF1ADC2 HPF Mode'
+		value HiFi
+		comment {
+			access 'read write'
+			type ENUMERATED
+			count 1
+			item.0 HiFi
+			item.1 'Voice 1'
+			item.2 'Voice 2'
+			item.3 'Voice 3'
+		}
+	}
+	control.121 {
+		iface MIXER
+		name 'AIF1ADC2 HPF Switch'
+		value.0 false
+		value.1 false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 2
+		}
+	}
+	control.122 {
+		iface MIXER
+		name 'AIF2ADC HPF Mode'
+		value HiFi
+		comment {
+			access 'read write'
+			type ENUMERATED
+			count 1
+			item.0 HiFi
+			item.1 'Voice 1'
+			item.2 'Voice 2'
+			item.3 'Voice 3'
+		}
+	}
+	control.123 {
+		iface MIXER
+		name 'AIF2ADC HPF Switch'
+		value.0 false
+		value.1 false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 2
+		}
+	}
+	control.124 {
+		iface MIXER
+		name 'ADC OSR'
+		value 'High Performance'
+		comment {
+			access 'read write'
+			type ENUMERATED
+			count 1
+			item.0 'Low Power'
+			item.1 'High Performance'
+		}
+	}
+	control.125 {
+		iface MIXER
+		name 'DAC OSR'
+		value 'Low Power'
+		comment {
+			access 'read write'
+			type ENUMERATED
+			count 1
+			item.0 'Low Power'
+			item.1 'High Performance'
+		}
+	}
+	control.126 {
+		iface MIXER
+		name 'DAC1 Volume'
+		value.0 96
+		value.1 96
+		comment {
+			access 'read write'
+			type INTEGER
+			count 2
+			range '0 - 96'
+			dbmin -9999999
+			dbmax 0
+			dbvalue.0 0
+			dbvalue.1 0
+		}
+	}
+	control.127 {
+		iface MIXER
+		name 'DAC1 Switch'
+		value.0 true
+		value.1 true
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 2
+		}
+	}
+	control.128 {
+		iface MIXER
+		name 'DAC2 Volume'
+		value.0 96
+		value.1 96
+		comment {
+			access 'read write'
+			type INTEGER
+			count 2
+			range '0 - 96'
+			dbmin -9999999
+			dbmax 0
+			dbvalue.0 0
+			dbvalue.1 0
+		}
+	}
+	control.129 {
+		iface MIXER
+		name 'DAC2 Switch'
+		value.0 false
+		value.1 false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 2
+		}
+	}
+	control.130 {
+		iface MIXER
+		name 'SPKL DAC2 Volume'
+		value 1
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 1'
+			dbmin -300
+			dbmax 0
+			dbvalue.0 0
+		}
+	}
+	control.131 {
+		iface MIXER
+		name 'SPKL DAC1 Volume'
+		value 1
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 1'
+			dbmin -300
+			dbmax 0
+			dbvalue.0 0
+		}
+	}
+	control.132 {
+		iface MIXER
+		name 'SPKR DAC2 Volume'
+		value 1
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 1'
+			dbmin -300
+			dbmax 0
+			dbvalue.0 0
+		}
+	}
+	control.133 {
+		iface MIXER
+		name 'SPKR DAC1 Volume'
+		value 1
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 1'
+			dbmin -300
+			dbmax 0
+			dbvalue.0 0
+		}
+	}
+	control.134 {
+		iface MIXER
+		name 'AIF1DAC1 3D Stereo Volume'
+		value 0
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 15'
+			dbmin -1600
+			dbmax 1145
+			dbvalue.0 -1600
+		}
+	}
+	control.135 {
+		iface MIXER
+		name 'AIF1DAC1 3D Stereo Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.136 {
+		iface MIXER
+		name 'AIF1DAC2 3D Stereo Volume'
+		value 0
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 15'
+			dbmin -1600
+			dbmax 1145
+			dbvalue.0 -1600
+		}
+	}
+	control.137 {
+		iface MIXER
+		name 'AIF1DAC2 3D Stereo Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.138 {
+		iface MIXER
+		name 'AIF2DAC 3D Stereo Volume'
+		value 0
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 15'
+			dbmin -1600
+			dbmax 1145
+			dbvalue.0 -1600
+		}
+	}
+	control.139 {
+		iface MIXER
+		name 'AIF2DAC 3D Stereo Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.140 {
+		iface MIXER
+		name 'AIF3 Boost Volume'
+		value 0
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 3'
+			dbmin 0
+			dbmax 1800
+			dbvalue.0 0
+		}
+	}
+	control.141 {
+		iface MIXER
+		name 'AIF1DAC1 Noise Gate Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.142 {
+		iface MIXER
+		name 'AIF1DAC1 Noise Gate Hold Time'
+		value '30ms'
+		comment {
+			access 'read write'
+			type ENUMERATED
+			count 1
+			item.0 '30ms'
+			item.1 '125ms'
+			item.2 '250ms'
+			item.3 '500ms'
+		}
+	}
+	control.143 {
+		iface MIXER
+		name 'AIF1DAC1 Noise Gate Threshold Volume'
+		value 3
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 7'
+			dbmin -10200
+			dbmax -6000
+			dbvalue.0 -8400
+		}
+	}
+	control.144 {
+		iface MIXER
+		name 'AIF1DAC2 Noise Gate Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.145 {
+		iface MIXER
+		name 'AIF1DAC2 Noise Gate Hold Time'
+		value '30ms'
+		comment {
+			access 'read write'
+			type ENUMERATED
+			count 1
+			item.0 '30ms'
+			item.1 '125ms'
+			item.2 '250ms'
+			item.3 '500ms'
+		}
+	}
+	control.146 {
+		iface MIXER
+		name 'AIF1DAC2 Noise Gate Threshold Volume'
+		value 3
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 7'
+			dbmin -10200
+			dbmax -6000
+			dbvalue.0 -8400
+		}
+	}
+	control.147 {
+		iface MIXER
+		name 'AIF2DAC Noise Gate Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.148 {
+		iface MIXER
+		name 'AIF2DAC Noise Gate Hold Time'
+		value '30ms'
+		comment {
+			access 'read write'
+			type ENUMERATED
+			count 1
+			item.0 '30ms'
+			item.1 '125ms'
+			item.2 '250ms'
+			item.3 '500ms'
+		}
+	}
+	control.149 {
+		iface MIXER
+		name 'AIF2DAC Noise Gate Threshold Volume'
+		value 3
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 7'
+			dbmin -10200
+			dbmax -6000
+			dbvalue.0 -8400
+		}
+	}
+	control.150 {
+		iface MIXER
+		name 'AIF1DAC1 MBC Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.151 {
+		iface MIXER
+		name 'AIF1DAC2 MBC Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.152 {
+		iface MIXER
+		name 'AIF2DAC MBC Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.153 {
+		iface MIXER
+		name 'AIF1DAC1 VSS Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.154 {
+		iface MIXER
+		name 'AIF1DAC2 VSS Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.155 {
+		iface MIXER
+		name 'AIF2DAC VSS Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.156 {
+		iface MIXER
+		name 'AIF1DAC1 HPF1 Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.157 {
+		iface MIXER
+		name 'AIF1DAC2 HPF1 Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.158 {
+		iface MIXER
+		name 'AIF2DAC HPF1 Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.159 {
+		iface MIXER
+		name 'AIF1DAC1 HPF2 Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.160 {
+		iface MIXER
+		name 'AIF1DAC2 HPF2 Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.161 {
+		iface MIXER
+		name 'AIF2DAC HPF2 Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.162 {
+		iface MIXER
+		name 'AIF1DAC1 Enhanced EQ Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.163 {
+		iface MIXER
+		name 'AIF1DAC2 Enhanced EQ Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.164 {
+		iface MIXER
+		name 'AIF2DAC Enhanced EQ Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.165 {
+		iface MIXER
+		name 'ADCR Mux'
+		value ADC
+		comment {
+			access 'read write'
+			type ENUMERATED
+			count 1
+			item.0 ADC
+			item.1 DMIC
+		}
+	}
+	control.166 {
+		iface MIXER
+		name 'ADCL Mux'
+		value ADC
+		comment {
+			access 'read write'
+			type ENUMERATED
+			count 1
+			item.0 ADC
+			item.1 DMIC
+		}
+	}
+	control.167 {
+		iface MIXER
+		name 'Right Headphone Mux'
+		value DAC
+		comment {
+			access 'read write'
+			type ENUMERATED
+			count 1
+			item.0 Mixer
+			item.1 DAC
+		}
+	}
+	control.168 {
+		iface MIXER
+		name 'Left Headphone Mux'
+		value DAC
+		comment {
+			access 'read write'
+			type ENUMERATED
+			count 1
+			item.0 Mixer
+			item.1 DAC
+		}
+	}
+	control.169 {
+		iface MIXER
+		name 'SPKR DAC2 Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.170 {
+		iface MIXER
+		name 'SPKR Input Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.171 {
+		iface MIXER
+		name 'SPKR IN1RP Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.172 {
+		iface MIXER
+		name 'SPKR Output Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.173 {
+		iface MIXER
+		name 'SPKR DAC1 Switch'
+		value true
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.174 {
+		iface MIXER
+		name 'SPKL DAC2 Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.175 {
+		iface MIXER
+		name 'SPKL Input Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.176 {
+		iface MIXER
+		name 'SPKL IN1LP Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.177 {
+		iface MIXER
+		name 'SPKL Output Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.178 {
+		iface MIXER
+		name 'SPKL DAC1 Switch'
+		value true
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.179 {
+		iface MIXER
+		name 'AIF3ADC Mux'
+		value AIF1ADCDAT
+		comment {
+			access 'read write'
+			type ENUMERATED
+			count 1
+			item.0 AIF1ADCDAT
+			item.1 AIF2ADCDAT
+			item.2 AIF2DACDAT
+			item.3 'Mono PCM'
+		}
+	}
+	control.180 {
+		iface MIXER
+		name 'AIF2DACR Mux'
+		value AIF2
+		comment {
+			access 'read write'
+			type ENUMERATED
+			count 1
+			item.0 AIF2
+			item.1 AIF3
+		}
+	}
+	control.181 {
+		iface MIXER
+		name 'AIF2DACL Mux'
+		value AIF2
+		comment {
+			access 'read write'
+			type ENUMERATED
+			count 1
+			item.0 AIF2
+			item.1 AIF3
+		}
+	}
+	control.182 {
+		iface MIXER
+		name 'Mono PCM Out Mux'
+		value None
+		comment {
+			access 'read write'
+			type ENUMERATED
+			count 1
+			item.0 None
+			item.1 AIF2ADCL
+			item.2 AIF2ADCR
+		}
+	}
+	control.183 {
+		iface MIXER
+		name 'AIF2 Loopback'
+		value None
+		comment {
+			access 'read write'
+			type ENUMERATED
+			count 1
+			item.0 None
+			item.1 ADCDAT
+		}
+	}
+	control.184 {
+		iface MIXER
+		name 'AIF1 Loopback'
+		value None
+		comment {
+			access 'read write'
+			type ENUMERATED
+			count 1
+			item.0 None
+			item.1 ADCDAT
+		}
+	}
+	control.185 {
+		iface MIXER
+		name 'AIF2ADC Mux'
+		value AIF2ADCDAT
+		comment {
+			access 'read write'
+			type ENUMERATED
+			count 1
+			item.0 AIF2ADCDAT
+			item.1 AIF3DACDAT
+		}
+	}
+	control.186 {
+		iface MIXER
+		name 'AIF2DAC Mux'
+		value AIF2DACDAT
+		comment {
+			access 'read write'
+			type ENUMERATED
+			count 1
+			item.0 AIF2DACDAT
+			item.1 AIF3DACDAT
+		}
+	}
+	control.187 {
+		iface MIXER
+		name 'AIF1DAC Mux'
+		value AIF1DACDAT
+		comment {
+			access 'read write'
+			type ENUMERATED
+			count 1
+			item.0 AIF1DACDAT
+			item.1 AIF3DACDAT
+		}
+	}
+	control.188 {
+		iface MIXER
+		name 'DAC1R Mixer Right Sidetone Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.189 {
+		iface MIXER
+		name 'DAC1R Mixer Left Sidetone Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.190 {
+		iface MIXER
+		name 'DAC1R Mixer AIF2 Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.191 {
+		iface MIXER
+		name 'DAC1R Mixer AIF1.2 Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.192 {
+		iface MIXER
+		name 'DAC1R Mixer AIF1.1 Switch'
+		value true
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.193 {
+		iface MIXER
+		name 'DAC1L Mixer Right Sidetone Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.194 {
+		iface MIXER
+		name 'DAC1L Mixer Left Sidetone Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.195 {
+		iface MIXER
+		name 'DAC1L Mixer AIF2 Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.196 {
+		iface MIXER
+		name 'DAC1L Mixer AIF1.2 Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.197 {
+		iface MIXER
+		name 'DAC1L Mixer AIF1.1 Switch'
+		value true
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.198 {
+		iface MIXER
+		name 'Right Sidetone'
+		value ADC/DMIC1
+		comment {
+			access 'read write'
+			type ENUMERATED
+			count 1
+			item.0 ADC/DMIC1
+			item.1 DMIC2
+		}
+	}
+	control.199 {
+		iface MIXER
+		name 'Left Sidetone'
+		value ADC/DMIC1
+		comment {
+			access 'read write'
+			type ENUMERATED
+			count 1
+			item.0 ADC/DMIC1
+			item.1 DMIC2
+		}
+	}
+	control.200 {
+		iface MIXER
+		name 'AIF2DAC2R Mixer Right Sidetone Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.201 {
+		iface MIXER
+		name 'AIF2DAC2R Mixer Left Sidetone Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.202 {
+		iface MIXER
+		name 'AIF2DAC2R Mixer AIF2 Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.203 {
+		iface MIXER
+		name 'AIF2DAC2R Mixer AIF1.2 Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.204 {
+		iface MIXER
+		name 'AIF2DAC2R Mixer AIF1.1 Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.205 {
+		iface MIXER
+		name 'AIF2DAC2L Mixer Right Sidetone Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.206 {
+		iface MIXER
+		name 'AIF2DAC2L Mixer Left Sidetone Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.207 {
+		iface MIXER
+		name 'AIF2DAC2L Mixer AIF2 Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.208 {
+		iface MIXER
+		name 'AIF2DAC2L Mixer AIF1.2 Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.209 {
+		iface MIXER
+		name 'AIF2DAC2L Mixer AIF1.1 Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.210 {
+		iface MIXER
+		name 'AIF1ADC2R Mixer DMIC Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.211 {
+		iface MIXER
+		name 'AIF1ADC2R Mixer AIF2 Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.212 {
+		iface MIXER
+		name 'AIF1ADC2L Mixer DMIC Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.213 {
+		iface MIXER
+		name 'AIF1ADC2L Mixer AIF2 Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.214 {
+		iface MIXER
+		name 'AIF1ADC1R Mixer ADC/DMIC Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.215 {
+		iface MIXER
+		name 'AIF1ADC1R Mixer AIF2 Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.216 {
+		iface MIXER
+		name 'AIF1ADC1L Mixer ADC/DMIC Switch'
+		value true
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.217 {
+		iface MIXER
+		name 'AIF1ADC1L Mixer AIF2 Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.218 {
+		iface MIXER
+		name 'LINEOUT2P Mixer Right Output Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.219 {
+		iface MIXER
+		name 'LINEOUT2N Mixer Left Output Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.220 {
+		iface MIXER
+		name 'LINEOUT2N Mixer Right Output Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.221 {
+		iface MIXER
+		name 'LINEOUT1P Mixer Left Output Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.222 {
+		iface MIXER
+		name 'LINEOUT1N Mixer Left Output Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.223 {
+		iface MIXER
+		name 'LINEOUT1N Mixer Right Output Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.224 {
+		iface MIXER
+		name 'SPKR Boost Direct Voice Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.225 {
+		iface MIXER
+		name 'SPKR Boost SPKL Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.226 {
+		iface MIXER
+		name 'SPKR Boost SPKR Switch'
+		value true
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.227 {
+		iface MIXER
+		name 'SPKL Boost Direct Voice Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.228 {
+		iface MIXER
+		name 'SPKL Boost SPKL Switch'
+		value true
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.229 {
+		iface MIXER
+		name 'SPKL Boost SPKR Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.230 {
+		iface MIXER
+		name 'Earpiece Mixer Direct Voice Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.231 {
+		iface MIXER
+		name 'Earpiece Mixer Left Output Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.232 {
+		iface MIXER
+		name 'Earpiece Mixer Right Output Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.233 {
+		iface MIXER
+		name 'Right Output Mixer Left Input Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.234 {
+		iface MIXER
+		name 'Right Output Mixer Right Input Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.235 {
+		iface MIXER
+		name 'Right Output Mixer IN2LN Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.236 {
+		iface MIXER
+		name 'Right Output Mixer IN2RN Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.237 {
+		iface MIXER
+		name 'Right Output Mixer IN1L Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.238 {
+		iface MIXER
+		name 'Right Output Mixer IN1R Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.239 {
+		iface MIXER
+		name 'Right Output Mixer IN2RP Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.240 {
+		iface MIXER
+		name 'Right Output Mixer DAC Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.241 {
+		iface MIXER
+		name 'Left Output Mixer Right Input Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.242 {
+		iface MIXER
+		name 'Left Output Mixer Left Input Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.243 {
+		iface MIXER
+		name 'Left Output Mixer IN2RN Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.244 {
+		iface MIXER
+		name 'Left Output Mixer IN2LN Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.245 {
+		iface MIXER
+		name 'Left Output Mixer IN2LP Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.246 {
+		iface MIXER
+		name 'Left Output Mixer IN1R Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.247 {
+		iface MIXER
+		name 'Left Output Mixer IN1L Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.248 {
+		iface MIXER
+		name 'Left Output Mixer DAC Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.249 {
+		iface MIXER
+		name 'MIXINR IN2R Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.250 {
+		iface MIXER
+		name 'MIXINR IN1R Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.251 {
+		iface MIXER
+		name 'MIXINL IN2L Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.252 {
+		iface MIXER
+		name 'MIXINL IN1L Switch'
+		value true
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.253 {
+		iface MIXER
+		name 'IN2R PGA IN2RP Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.254 {
+		iface MIXER
+		name 'IN2R PGA IN2RN Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.255 {
+		iface MIXER
+		name 'IN2L PGA IN2LP Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.256 {
+		iface MIXER
+		name 'IN2L PGA IN2LN Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.257 {
+		iface MIXER
+		name 'IN1R PGA IN1RP Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.258 {
+		iface MIXER
+		name 'IN1R PGA IN1RN Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.259 {
+		iface MIXER
+		name 'IN1L PGA IN1LP Switch'
+		value true
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.260 {
+		iface MIXER
+		name 'IN1L PGA IN1LN Switch'
+		value true
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.261 {
+		iface CARD
+		name 'Headphone Jack'
+		value true
+		comment {
+			access read
+			type BOOLEAN
+			count 1
+		}
+	}
+}
+state.cs42888audio {
+	control.1 {
+		iface MIXER
+		name 'DAC1 Playback Volume'
+		value.0 255
+		value.1 255
+		comment {
+			access 'read write'
+			type INTEGER
+			count 2
+			range '0 - 255'
+			dbmin -9999999
+			dbmax 0
+			dbvalue.0 0
+			dbvalue.1 0
+		}
+	}
+	control.2 {
+		iface MIXER
+		name 'DAC2 Playback Volume'
+		value.0 255
+		value.1 255
+		comment {
+			access 'read write'
+			type INTEGER
+			count 2
+			range '0 - 255'
+			dbmin -9999999
+			dbmax 0
+			dbvalue.0 0
+			dbvalue.1 0
+		}
+	}
+	control.3 {
+		iface MIXER
+		name 'DAC3 Playback Volume'
+		value.0 255
+		value.1 255
+		comment {
+			access 'read write'
+			type INTEGER
+			count 2
+			range '0 - 255'
+			dbmin -9999999
+			dbmax 0
+			dbvalue.0 0
+			dbvalue.1 0
+		}
+	}
+	control.4 {
+		iface MIXER
+		name 'DAC4 Playback Volume'
+		value.0 255
+		value.1 255
+		comment {
+			access 'read write'
+			type INTEGER
+			count 2
+			range '0 - 255'
+			dbmin -9999999
+			dbmax 0
+			dbvalue.0 0
+			dbvalue.1 0
+		}
+	}
+	control.5 {
+		iface MIXER
+		name 'ADC1 Capture Volume'
+		value.0 128
+		value.1 128
+		comment {
+			access 'read write'
+			type INTEGER
+			count 2
+			range '0 - 176'
+			dbmin -6400
+			dbmax 2400
+			dbvalue.0 0
+			dbvalue.1 0
+		}
+	}
+	control.6 {
+		iface MIXER
+		name 'ADC2 Capture Volume'
+		value.0 128
+		value.1 128
+		comment {
+			access 'read write'
+			type INTEGER
+			count 2
+			range '0 - 176'
+			dbmin -6400
+			dbmax 2400
+			dbvalue.0 0
+			dbvalue.1 0
+		}
+	}
+	control.7 {
+		iface MIXER
+		name 'DAC1 Invert Switch'
+		value.0 false
+		value.1 false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 2
+		}
+	}
+	control.8 {
+		iface MIXER
+		name 'DAC2 Invert Switch'
+		value.0 false
+		value.1 false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 2
+		}
+	}
+	control.9 {
+		iface MIXER
+		name 'DAC3 Invert Switch'
+		value.0 false
+		value.1 false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 2
+		}
+	}
+	control.10 {
+		iface MIXER
+		name 'DAC4 Invert Switch'
+		value.0 false
+		value.1 false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 2
+		}
+	}
+	control.11 {
+		iface MIXER
+		name 'ADC1 Invert Switch'
+		value.0 false
+		value.1 false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 2
+		}
+	}
+	control.12 {
+		iface MIXER
+		name 'ADC2 Invert Switch'
+		value.0 false
+		value.1 false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 2
+		}
+	}
+	control.13 {
+		iface MIXER
+		name 'ADC High-Pass Filter Switch'
+		value true
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.14 {
+		iface MIXER
+		name 'DAC De-emphasis Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.15 {
+		iface MIXER
+		name 'ADC1 Single Ended Mode Switch'
+		value Differential
+		comment {
+			access 'read write'
+			type ENUMERATED
+			count 1
+			item.0 Differential
+			item.1 Single-Ended
+		}
+	}
+	control.16 {
+		iface MIXER
+		name 'ADC2 Single Ended Mode Switch'
+		value Differential
+		comment {
+			access 'read write'
+			type ENUMERATED
+			count 1
+			item.0 Differential
+			item.1 Single-Ended
+		}
+	}
+	control.17 {
+		iface MIXER
+		name 'DAC Single Volume Control Switch'
+		value 0
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 1'
+		}
+	}
+	control.18 {
+		iface MIXER
+		name 'DAC Soft Ramp & Zero Cross Control Switch'
+		value 'Immediate Change'
+		comment {
+			access 'read write'
+			type ENUMERATED
+			count 1
+			item.0 'Immediate Change'
+			item.1 'Zero Cross'
+			item.2 'Soft Ramp'
+			item.3 'Soft Ramp on Zero Cross'
+		}
+	}
+	control.19 {
+		iface MIXER
+		name 'DAC Auto Mute Switch'
+		value true
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.20 {
+		iface MIXER
+		name 'Mute ADC Serial Port Switch'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.21 {
+		iface MIXER
+		name 'ADC Single Volume Control Switch'
+		value 0
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 1'
+		}
+	}
+	control.22 {
+		iface MIXER
+		name 'ADC Soft Ramp & Zero Cross Control Switch'
+		value 'Immediate Change'
+		comment {
+			access 'read write'
+			type ENUMERATED
+			count 1
+			item.0 'Immediate Change'
+			item.1 'Zero Cross'
+			item.2 'Soft Ramp'
+			item.3 'Soft Ramp on Zero Cross'
+		}
+	}
+}
+state.imxhdmisoc {
+	control.1 {
+		iface MIXER
+		name 'IEC958 Playback Default'
+		value '0400020200000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000'
+		comment {
+			access 'read write volatile'
+			type IEC958
+			count 1
+		}
+	}
+	control.2 {
+		iface MIXER
+		name 'HDMI Support Channels'
+		value 2
+		comment {
+			access 'read volatile'
+			type INTEGER
+			count 1
+			range '0 - 0'
+		}
+	}
+	control.3 {
+		iface MIXER
+		name 'HDMI Support Rates'
+		value.0 32000
+		value.1 44100
+		value.2 48000
+		comment {
+			access 'read volatile'
+			type INTEGER
+			count 3
+			range '0 - 0'
+		}
+	}
+	control.4 {
+		iface MIXER
+		name 'HDMI Support Formats'
+		value 16
+		comment {
+			access 'read volatile'
+			type INTEGER
+			count 1
+			range '0 - 0'
+		}
+	}
+}
+state.sii902xaudio {
+	control {
+	}
+}
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/wm8960/fsl_sai.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/wm8960/fsl_sai.h
new file mode 100644
index 0000000000000000000000000000000000000000..d700c84c5e9ee9d28520d4dfe8b31ff7ed4844a4
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/wm8960/fsl_sai.h
@@ -0,0 +1,292 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright 2012-2016 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __FSL_SAI_H
+#define __FSL_SAI_H
+
+#include <linux/pm_qos.h>
+#include <sound/dmaengine_pcm.h>
+
+#define FSL_SAI_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
+			 SNDRV_PCM_FMTBIT_S24_LE |\
+			 SNDRV_PCM_FMTBIT_S32_LE |\
+			 SNDRV_PCM_FMTBIT_DSD_U8 |\
+			 SNDRV_PCM_FMTBIT_DSD_U16_LE |\
+			 SNDRV_PCM_FMTBIT_DSD_U32_LE)
+
+/* SAI Register Map Register */
+#define FSL_SAI_VERID	0x00 /* SAI Version ID Register */
+#define FSL_SAI_PARAM	0x04 /* SAI Parameter Register */
+#define FSL_SAI_TCSR(offset) (0x00 + offset) /* SAI Transmit Control */
+#define FSL_SAI_TCR1(offset) (0x04 + offset) /* SAI Transmit Configuration 1 */
+#define FSL_SAI_TCR2(offset) (0x08 + offset) /* SAI Transmit Configuration 2 */
+#define FSL_SAI_TCR3(offset) (0x0c + offset) /* SAI Transmit Configuration 3 */
+#define FSL_SAI_TCR4(offset) (0x10 + offset) /* SAI Transmit Configuration 4 */
+#define FSL_SAI_TCR5(offset) (0x14 + offset) /* SAI Transmit Configuration 5 */
+#define FSL_SAI_TDR0    0x20 /* SAI Transmit Data */
+#define FSL_SAI_TDR1    0x24 /* SAI Transmit Data */
+#define FSL_SAI_TDR2    0x28 /* SAI Transmit Data */
+#define FSL_SAI_TDR3    0x2C /* SAI Transmit Data */
+#define FSL_SAI_TDR4    0x30 /* SAI Transmit Data */
+#define FSL_SAI_TDR5    0x34 /* SAI Transmit Data */
+#define FSL_SAI_TDR6    0x38 /* SAI Transmit Data */
+#define FSL_SAI_TDR7    0x3C /* SAI Transmit Data */
+#define FSL_SAI_TFR0    0x40 /* SAI Transmit FIFO */
+#define FSL_SAI_TFR1    0x44 /* SAI Transmit FIFO */
+#define FSL_SAI_TFR2    0x48 /* SAI Transmit FIFO */
+#define FSL_SAI_TFR3    0x4C /* SAI Transmit FIFO */
+#define FSL_SAI_TFR4    0x50 /* SAI Transmit FIFO */
+#define FSL_SAI_TFR5    0x54 /* SAI Transmit FIFO */
+#define FSL_SAI_TFR6    0x58 /* SAI Transmit FIFO */
+#define FSL_SAI_TFR7    0x5C /* SAI Transmit FIFO */
+#define FSL_SAI_TMR	0x60 /* SAI Transmit Mask */
+#define FSL_SAI_TTCTL	0x70 /* SAI Transmit Timestamp Control Register */
+#define FSL_SAI_TTCTN	0x74 /* SAI Transmit Timestamp Counter Register */
+#define FSL_SAI_TBCTN	0x78 /* SAI Transmit Bit Counter Register */
+#define FSL_SAI_TTCAP	0x7C /* SAI Transmit Timestamp Capture */
+
+#define FSL_SAI_RCSR(offset) (0x80 + offset) /* SAI Receive Control */
+#define FSL_SAI_RCR1(offset) (0x84 + offset) /* SAI Receive Configuration 1 */
+#define FSL_SAI_RCR2(offset) (0x88 + offset) /* SAI Receive Configuration 2 */
+#define FSL_SAI_RCR3(offset) (0x8c + offset) /* SAI Receive Configuration 3 */
+#define FSL_SAI_RCR4(offset) (0x90 + offset) /* SAI Receive Configuration 4 */
+#define FSL_SAI_RCR5(offset) (0x94 + offset) /* SAI Receive Configuration 5 */
+#define FSL_SAI_RDR0    0xa0 /* SAI Receive Data */
+#define FSL_SAI_RDR1    0xa4 /* SAI Receive Data */
+#define FSL_SAI_RDR2    0xa8 /* SAI Receive Data */
+#define FSL_SAI_RDR3    0xac /* SAI Receive Data */
+#define FSL_SAI_RDR4    0xb0 /* SAI Receive Data */
+#define FSL_SAI_RDR5    0xb4 /* SAI Receive Data */
+#define FSL_SAI_RDR6    0xb8 /* SAI Receive Data */
+#define FSL_SAI_RDR7    0xbc /* SAI Receive Data */
+#define FSL_SAI_RFR0    0xc0 /* SAI Receive FIFO */
+#define FSL_SAI_RFR1    0xc4 /* SAI Receive FIFO */
+#define FSL_SAI_RFR2    0xc8 /* SAI Receive FIFO */
+#define FSL_SAI_RFR3    0xcc /* SAI Receive FIFO */
+#define FSL_SAI_RFR4    0xd0 /* SAI Receive FIFO */
+#define FSL_SAI_RFR5    0xd4 /* SAI Receive FIFO */
+#define FSL_SAI_RFR6    0xd8 /* SAI Receive FIFO */
+#define FSL_SAI_RFR7    0xdc /* SAI Receive FIFO */
+#define FSL_SAI_RMR	0xe0 /* SAI Receive Mask */
+#define FSL_SAI_RTCTL	0xf0 /* SAI Receive Timestamp Control Register */
+#define FSL_SAI_RTCTN	0xf4 /* SAI Receive Timestamp Counter Register */
+#define FSL_SAI_RBCTN	0xf8 /* SAI Receive Bit Counter Register */
+#define FSL_SAI_RTCAP	0xfc /* SAI Receive Timestamp Capture */
+
+#define FSL_SAI_MCTL	0x100 /* SAI MCLK Control Register */
+#define FSL_SAI_MDIV	0x104 /* SAI MCLK Divide Register */
+
+#define FSL_SAI_xCSR(tx, off)	(tx ? FSL_SAI_TCSR(off) : FSL_SAI_RCSR(off))
+#define FSL_SAI_xCR1(tx, off)	(tx ? FSL_SAI_TCR1(off) : FSL_SAI_RCR1(off))
+#define FSL_SAI_xCR2(tx, off)	(tx ? FSL_SAI_TCR2(off) : FSL_SAI_RCR2(off))
+#define FSL_SAI_xCR3(tx, off)	(tx ? FSL_SAI_TCR3(off) : FSL_SAI_RCR3(off))
+#define FSL_SAI_xCR4(tx, off)	(tx ? FSL_SAI_TCR4(off) : FSL_SAI_RCR4(off))
+#define FSL_SAI_xCR5(tx, off)	(tx ? FSL_SAI_TCR5(off) : FSL_SAI_RCR5(off))
+#define FSL_SAI_xDR(tx)		(tx ? FSL_SAI_TDR : FSL_SAI_RDR)
+#define FSL_SAI_xFR(tx)		(tx ? FSL_SAI_TFR : FSL_SAI_RFR)
+#define FSL_SAI_xMR(tx)		(tx ? FSL_SAI_TMR : FSL_SAI_RMR)
+
+/* SAI Transmit/Receive Control Register */
+#define FSL_SAI_CSR_TERE	BIT(31)
+#define FSL_SAI_CSR_SE		BIT(30)
+#define FSL_SAI_CSR_FR		BIT(25)
+#define FSL_SAI_CSR_SR		BIT(24)
+#define FSL_SAI_CSR_xF_SHIFT	16
+#define FSL_SAI_CSR_xF_W_SHIFT	18
+#define FSL_SAI_CSR_xF_MASK	(0x1f << FSL_SAI_CSR_xF_SHIFT)
+#define FSL_SAI_CSR_xF_W_MASK	(0x7 << FSL_SAI_CSR_xF_W_SHIFT)
+#define FSL_SAI_CSR_WSF		BIT(20)
+#define FSL_SAI_CSR_SEF		BIT(19)
+#define FSL_SAI_CSR_FEF		BIT(18)
+#define FSL_SAI_CSR_FWF		BIT(17)
+#define FSL_SAI_CSR_FRF		BIT(16)
+#define FSL_SAI_CSR_xIE_SHIFT	8
+#define FSL_SAI_CSR_xIE_MASK	(0x1f << FSL_SAI_CSR_xIE_SHIFT)
+#define FSL_SAI_CSR_WSIE	BIT(12)
+#define FSL_SAI_CSR_SEIE	BIT(11)
+#define FSL_SAI_CSR_FEIE	BIT(10)
+#define FSL_SAI_CSR_FWIE	BIT(9)
+#define FSL_SAI_CSR_FRIE	BIT(8)
+#define FSL_SAI_CSR_FRDE	BIT(0)
+
+/* SAI Transmit and Receive Configuration 1 Register */
+#define FSL_SAI_CR1_RFW_MASK	0x1f
+
+/* SAI Transmit and Receive Configuration 2 Register */
+#define FSL_SAI_CR2_SYNC	BIT(30)
+#define FSL_SAI_CR2_MSEL_MASK	(0x3 << 26)
+#define FSL_SAI_CR2_MSEL_BUS	0
+#define FSL_SAI_CR2_MSEL_MCLK1	BIT(26)
+#define FSL_SAI_CR2_MSEL_MCLK2	BIT(27)
+#define FSL_SAI_CR2_MSEL_MCLK3	(BIT(26) | BIT(27))
+#define FSL_SAI_CR2_MSEL(ID)	((ID) << 26)
+#define FSL_SAI_CR2_BCP		BIT(25)
+#define FSL_SAI_CR2_BCD_MSTR	BIT(24)
+#define FSL_SAI_CR2_BYP		BIT(23) /* BCLK bypass */
+#define FSL_SAI_CR2_DIV_MASK	0xff
+
+/* SAI Transmit and Receive Configuration 3 Register */
+#define FSL_SAI_CR3_TRCE_MASK	(0xff << 16)
+#define FSL_SAI_CR3_TRCE(x)	(x << 16)
+#define FSL_SAI_CR3_WDFL(x)	(x)
+#define FSL_SAI_CR3_WDFL_MASK	0x1f
+
+/* SAI Transmit and Receive Configuration 4 Register */
+
+#define FSL_SAI_CR4_FCONT	BIT(28)
+#define FSL_SAI_CR4_FCOMB_SHIFT BIT(26)
+#define FSL_SAI_CR4_FCOMB_SOFT  BIT(27)
+#define FSL_SAI_CR4_FCOMB_MASK  (0x3 << 26)
+#define FSL_SAI_CR4_FPACK_8     (0x2 << 24)
+#define FSL_SAI_CR4_FPACK_16    (0x3 << 24)
+#define FSL_SAI_CR4_FRSZ(x)	(((x) - 1) << 16)
+#define FSL_SAI_CR4_FRSZ_MASK	(0x1f << 16)
+#define FSL_SAI_CR4_SYWD(x)	(((x) - 1) << 8)
+#define FSL_SAI_CR4_SYWD_MASK	(0x1f << 8)
+#define FSL_SAI_CR4_CHMOD	(1 << 5)
+#define FSL_SAI_CR4_CHMOD_MASK	(1 << 5)
+#define FSL_SAI_CR4_MF		BIT(4)
+#define FSL_SAI_CR4_FSE		BIT(3)
+#define FSL_SAI_CR4_FSP		BIT(1)
+#define FSL_SAI_CR4_FSD_MSTR	BIT(0)
+
+/* SAI Transmit and Receive Configuration 5 Register */
+#define FSL_SAI_CR5_WNW(x)	(((x) - 1) << 24)
+#define FSL_SAI_CR5_WNW_MASK	(0x1f << 24)
+#define FSL_SAI_CR5_W0W(x)	(((x) - 1) << 16)
+#define FSL_SAI_CR5_W0W_MASK	(0x1f << 16)
+#define FSL_SAI_CR5_FBT(x)	((x) << 8)
+#define FSL_SAI_CR5_FBT_MASK	(0x1f << 8)
+
+/* SAI MCLK Control Register */
+#define FSL_SAI_MCTL_MCLK_EN	BIT(30)	/* MCLK Enable */
+#define FSL_SAI_MCTL_MSEL_MASK	(0x3 << 24)
+#define FSL_SAI_MCTL_MSEL(ID)   ((ID) << 24)
+#define FSL_SAI_MCTL_MSEL_BUS	0
+#define FSL_SAI_MCTL_MSEL_MCLK1	BIT(24)
+#define FSL_SAI_MCTL_MSEL_MCLK2	BIT(25)
+#define FSL_SAI_MCTL_MSEL_MCLK3	(BIT(24) | BIT(25))
+#define FSL_SAI_MCTL_DIV_EN	BIT(23)
+#define FSL_SAI_MCTL_DIV_MASK	0xFF
+
+/* SAI VERID Register */
+#define FSL_SAI_VER_ID_SHIFT	16
+#define FSL_SAI_VER_ID_MASK	(0xFFFF << FSL_SAI_VER_ID_SHIFT)
+#define FSL_SAI_VER_EFIFO_EN	BIT(0)
+#define FSL_SAI_VER_TSTMP_EN	BIT(1)
+
+/* SAI PARAM Register */
+#define FSL_SAI_PAR_SPF_SHIFT	16
+#define FSL_SAI_PAR_SPF_MASK	(0x0F << FSL_SAI_PAR_SPF_SHIFT)
+#define FSL_SAI_PAR_WPF_SHIFT	8
+#define FSL_SAI_PAR_WPF_MASK	(0x0F << FSL_SAI_PAR_WPF_SHIFT)
+#define FSL_SAI_PAR_DLN_MASK	(0x0F)
+
+/* SAI MCLK Divide Register */
+#define FSL_SAI_MDIV_MASK	0xFFFFF
+
+/* SAI type */
+#define FSL_SAI_DMA		BIT(0)
+#define FSL_SAI_USE_AC97	BIT(1)
+#define FSL_SAI_NET		BIT(2)
+#define FSL_SAI_TRA_SYN		BIT(3)
+#define FSL_SAI_REC_SYN		BIT(4)
+#define FSL_SAI_USE_I2S_SLAVE	BIT(5)
+
+#define FSL_FMT_TRANSMITTER	0
+#define FSL_FMT_RECEIVER	1
+
+/* SAI clock sources */
+#define FSL_SAI_CLK_BUS		0
+#define FSL_SAI_CLK_MAST1	1
+#define FSL_SAI_CLK_MAST2	2
+#define FSL_SAI_CLK_MAST3	3
+
+#define FSL_SAI_MCLK_MAX	4
+
+/* SAI data transfer numbers per DMA request */
+#define FSL_SAI_MAXBURST_TX 6
+#define FSL_SAI_MAXBURST_RX 6
+
+#define SAI_FLAG_PMQOS   BIT(0)
+
+struct fsl_sai_soc_data {
+	unsigned int fifo_depth;
+	unsigned int fifos;
+	unsigned int dataline;
+	unsigned int flags;
+	unsigned char reg_offset;
+	bool imx;
+	/* True for EDMA because it needs period size multiple of maxburst */
+	bool constrain_period_size;
+};
+
+struct fsl_sai_verid {
+	u32 id;
+	bool timestamp_en;
+	bool extfifo_en;
+	bool loaded;
+};
+
+struct fsl_sai_param {
+	u32 spf; /* max slots per frame */
+	u32 wpf; /* words in fifo */
+	u32 dln; /* number of datalines implemented */
+};
+
+struct fsl_sai_dl_cfg {
+	unsigned int pins;
+	unsigned int mask[2];
+	unsigned int offset[2];
+};
+
+struct fsl_sai {
+	struct platform_device *pdev;
+	struct regmap *regmap;
+	struct clk *bus_clk;
+	struct clk *mclk_clk[FSL_SAI_MCLK_MAX];
+	struct clk *pll8k_clk;
+	struct clk *pll11k_clk;
+
+	bool slave_mode[2];
+	bool is_lsb_first;
+	bool is_dsp_mode;
+	bool is_multi_lane;
+	bool synchronous[2];
+	bool is_stream_opened[2];
+	bool is_dsd;
+
+	int pcm_dl_cfg_cnt;
+	int dsd_dl_cfg_cnt;
+	struct fsl_sai_dl_cfg *pcm_dl_cfg;
+	struct fsl_sai_dl_cfg *dsd_dl_cfg;
+
+	unsigned int masterflag[2];
+
+	unsigned int mclk_id[2];
+	unsigned int mclk_streams;
+	unsigned int slots;
+	unsigned int slot_width;
+	unsigned int bitclk_ratio;
+
+	struct snd_dmaengine_dai_dma_data dma_params_rx;
+	struct snd_dmaengine_dai_dma_data dma_params_tx;
+	const struct fsl_sai_soc_data *soc;
+	struct pm_qos_request pm_qos_req;
+	struct pinctrl *pinctrl;
+	struct pinctrl_state *pins_state;
+
+	struct fsl_sai_verid verid;
+	struct fsl_sai_param param;
+};
+
+#define TX 1
+#define RX 0
+
+#endif /* __FSL_SAI_H */
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/wm8960/imx-wm8960.c b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/wm8960/imx-wm8960.c
new file mode 100644
index 0000000000000000000000000000000000000000..33e96911318b2e9a037e3a122625377bf0937321
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/wm8960/imx-wm8960.c
@@ -0,0 +1,695 @@
+/*
+ * Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/module.h>
+#include <linux/of_platform.h>
+#include <linux/i2c.h>
+#include <linux/of_gpio.h>
+#include <linux/slab.h>
+#include <linux/gpio.h>
+#include <linux/clk.h>
+#include <sound/soc.h>
+#include <sound/jack.h>
+#include <sound/control.h>
+#include <sound/pcm_params.h>
+#include <sound/soc-dapm.h>
+#include <linux/pinctrl/consumer.h>
+#include <linux/mfd/syscon.h>
+#include "wm8960.h"
+#include "fsl_sai.h"
+
+struct imx_wm8960_data {
+	struct snd_soc_card card;
+	struct clk *codec_clk;
+	unsigned int clk_frequency;
+	bool is_codec_master;
+	bool is_codec_rpmsg;
+	bool is_stream_in_use[2];
+	bool is_stream_opened[2];
+	struct regmap *gpr;
+	unsigned int hp_det[2];
+	u32 asrc_rate;
+	u32 asrc_format;
+};
+
+struct imx_priv {
+	enum of_gpio_flags hp_active_low;
+	enum of_gpio_flags mic_active_low;
+	bool is_headset_jack;
+	struct platform_device *pdev;
+	struct platform_device *asrc_pdev;
+};
+
+static struct imx_priv card_priv;
+
+static struct snd_soc_jack imx_hp_jack;
+static struct snd_soc_jack_pin imx_hp_jack_pin = {
+	.pin = "Headphone Jack",
+	.mask = SND_JACK_HEADPHONE,
+};
+static struct snd_soc_jack_gpio imx_hp_jack_gpio = {
+	.name = "headphone detect",
+	.report = SND_JACK_HEADPHONE,
+	.debounce_time = 250,
+	.invert = 0,
+};
+
+static struct snd_soc_jack imx_mic_jack;
+static struct snd_soc_jack_pin imx_mic_jack_pins = {
+	.pin = "Mic Jack",
+	.mask = SND_JACK_MICROPHONE,
+};
+static struct snd_soc_jack_gpio imx_mic_jack_gpio = {
+	.name = "mic detect",
+	.report = SND_JACK_MICROPHONE,
+	.debounce_time = 250,
+	.invert = 0,
+};
+
+static int hp_jack_status_check(void *data)
+{
+	struct imx_priv *priv = &card_priv;
+	struct snd_soc_jack *jack = data;
+	struct snd_soc_dapm_context *dapm = &jack->card->dapm;
+	int hp_status, ret;
+
+	hp_status = gpio_get_value(imx_hp_jack_gpio.gpio);
+
+	if (hp_status != priv->hp_active_low) {
+		snd_soc_dapm_disable_pin(dapm, "Ext Spk");
+		if (priv->is_headset_jack) {
+			snd_soc_dapm_enable_pin(dapm, "Mic Jack");
+			snd_soc_dapm_disable_pin(dapm, "Main MIC");
+		}
+		ret = imx_hp_jack_gpio.report;
+	} else {
+		snd_soc_dapm_enable_pin(dapm, "Ext Spk");
+		if (priv->is_headset_jack) {
+			snd_soc_dapm_disable_pin(dapm, "Mic Jack");
+			snd_soc_dapm_enable_pin(dapm, "Main MIC");
+		}
+		ret = 0;
+	}
+
+	return ret;
+}
+
+static int mic_jack_status_check(void *data)
+{
+	struct imx_priv *priv = &card_priv;
+	struct snd_soc_jack *jack = data;
+	struct snd_soc_dapm_context *dapm = &jack->card->dapm;
+	int mic_status, ret;
+
+	mic_status = gpio_get_value(imx_mic_jack_gpio.gpio);
+
+	if (mic_status != priv->mic_active_low) {
+		snd_soc_dapm_disable_pin(dapm, "Main MIC");
+		ret = imx_mic_jack_gpio.report;
+	} else {
+		snd_soc_dapm_enable_pin(dapm, "Main MIC");
+		ret = 0;
+	}
+
+	return ret;
+}
+
+static const struct snd_soc_dapm_widget imx_wm8960_dapm_widgets[] = {
+	SND_SOC_DAPM_HP("Headphone Jack", NULL),
+	SND_SOC_DAPM_SPK("Ext Spk", NULL),
+	SND_SOC_DAPM_MIC("Mic Jack", NULL),
+	SND_SOC_DAPM_MIC("Main MIC", NULL),
+};
+
+static int imx_wm8960_jack_init(struct snd_soc_card *card,
+		struct snd_soc_jack *jack, struct snd_soc_jack_pin *pin,
+		struct snd_soc_jack_gpio *gpio)
+{
+	int ret;
+
+	ret = snd_soc_card_jack_new(card, pin->pin, pin->mask, jack, pin, 1);
+	if (ret)
+		return ret;
+
+	ret = snd_soc_jack_add_gpios(jack, 1, gpio);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
+static ssize_t headphone_show(struct device_driver *dev, char *buf)
+{
+	struct imx_priv *priv = &card_priv;
+	int hp_status;
+
+	/* Check if headphone is plugged in */
+	hp_status = gpio_get_value(imx_hp_jack_gpio.gpio);
+
+	if (hp_status != priv->hp_active_low)
+		strcpy(buf, "Headphone\n");
+	else
+		strcpy(buf, "Speaker\n");
+
+	return strlen(buf);
+}
+
+static ssize_t micphone_show(struct device_driver *dev, char *buf)
+{
+	struct imx_priv *priv = &card_priv;
+	int mic_status;
+
+	/* Check if headphone is plugged in */
+	mic_status = gpio_get_value(imx_mic_jack_gpio.gpio);
+
+	if (mic_status != priv->mic_active_low)
+		strcpy(buf, "Mic Jack\n");
+	else
+		strcpy(buf, "Main MIC\n");
+
+	return strlen(buf);
+}
+static DRIVER_ATTR_RO(headphone);
+static DRIVER_ATTR_RO(micphone);
+
+static int imx_hifi_hw_params(struct snd_pcm_substream *substream,
+				     struct snd_pcm_hw_params *params)
+{
+	struct snd_soc_pcm_runtime *rtd = substream->private_data;
+	struct snd_soc_dai *codec_dai = rtd->codec_dai;
+	struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
+	struct snd_soc_card *card = rtd->card;
+	struct imx_wm8960_data *data = snd_soc_card_get_drvdata(card);
+	bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
+	struct device *dev = card->dev;
+	unsigned int sample_rate = params_rate(params);
+	unsigned int pll_out;
+	unsigned int fmt;
+	int ret = 0;
+
+	data->is_stream_in_use[tx] = true;
+
+	if (data->is_stream_in_use[!tx])
+		return 0;
+
+	if (data->is_codec_master)
+		fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
+			SND_SOC_DAIFMT_CBM_CFM;
+	else
+		fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
+			SND_SOC_DAIFMT_CBS_CFS;
+
+	/* set cpu DAI configuration */
+	ret = snd_soc_dai_set_fmt(cpu_dai, fmt);
+	if (ret) {
+		dev_err(dev, "failed to set cpu dai fmt: %d\n", ret);
+		return ret;
+	}
+	/* set codec DAI configuration */
+	ret = snd_soc_dai_set_fmt(codec_dai, fmt);
+	if (ret) {
+		dev_err(dev, "failed to set codec dai fmt: %d\n", ret);
+		return ret;
+	}
+
+	if (!data->is_codec_master) {
+		ret = snd_soc_dai_set_tdm_slot(cpu_dai, 0, 0, 2,
+					       params_physical_width(params));
+		if (ret) {
+			dev_err(dev, "failed to set cpu dai tdm slot: %d\n", ret);
+			return ret;
+		}
+
+		ret = snd_soc_dai_set_sysclk(cpu_dai, 0, 0, SND_SOC_CLOCK_OUT);
+		if (ret) {
+			dev_err(dev, "failed to set cpu sysclk: %d\n", ret);
+			return ret;
+		}
+		return 0;
+	} else {
+		ret = snd_soc_dai_set_sysclk(cpu_dai, 0, 0, SND_SOC_CLOCK_IN);
+		if (ret) {
+			dev_err(dev, "failed to set cpu sysclk: %d\n", ret);
+			return ret;
+		}
+	}
+
+	data->clk_frequency = clk_get_rate(data->codec_clk);
+
+	/* Set codec pll */
+	if (params_width(params) == 24)
+		pll_out = sample_rate * 768;
+	else
+		pll_out = sample_rate * 512;
+
+	ret = snd_soc_dai_set_pll(codec_dai, WM8960_SYSCLK_AUTO, 0, data->clk_frequency, pll_out);
+	if (ret)
+		return ret;
+	ret = snd_soc_dai_set_sysclk(codec_dai, WM8960_SYSCLK_AUTO, pll_out, 0);
+
+	return ret;
+}
+
+static int imx_hifi_hw_free(struct snd_pcm_substream *substream)
+{
+	struct snd_soc_pcm_runtime *rtd = substream->private_data;
+	struct snd_soc_dai *codec_dai = rtd->codec_dai;
+	struct snd_soc_card *card = rtd->card;
+	struct imx_wm8960_data *data = snd_soc_card_get_drvdata(card);
+	bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
+	struct device *dev = card->dev;
+	int ret;
+
+	data->is_stream_in_use[tx] = false;
+
+	if (data->is_codec_master && !data->is_stream_in_use[!tx]) {
+		ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_CBS_CFS |
+				SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF);
+		if (ret)
+			dev_warn(dev, "failed to set codec dai fmt: %d\n", ret);
+	}
+
+	return 0;
+}
+
+static u32 imx_wm8960_rates[] = { 8000, 16000, 32000, 48000 };
+static struct snd_pcm_hw_constraint_list imx_wm8960_rate_constraints = {
+	.count = ARRAY_SIZE(imx_wm8960_rates),
+	.list = imx_wm8960_rates,
+};
+
+static int imx_hifi_startup(struct snd_pcm_substream *substream)
+{
+	struct snd_soc_pcm_runtime *rtd = substream->private_data;
+	struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
+	struct snd_soc_card *card = rtd->card;
+	struct imx_wm8960_data *data = snd_soc_card_get_drvdata(card);
+	bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
+	struct fsl_sai *sai = dev_get_drvdata(cpu_dai->dev);
+	int ret = 0;
+
+	data->is_stream_opened[tx] = true;
+	if (data->is_stream_opened[tx] != sai->is_stream_opened[tx] ||
+	    data->is_stream_opened[!tx] != sai->is_stream_opened[!tx]) {
+		data->is_stream_opened[tx] = false;
+		return -EBUSY;
+	}
+
+	if (!data->is_codec_master) {
+		ret = snd_pcm_hw_constraint_list(substream->runtime, 0,
+				SNDRV_PCM_HW_PARAM_RATE, &imx_wm8960_rate_constraints);
+		if (ret)
+			return ret;
+	}
+	ret = clk_prepare_enable(data->codec_clk);
+	if (ret) {
+		dev_err(card->dev, "Failed to enable MCLK: %d\n", ret);
+		return ret;
+	}
+	return ret;
+}
+
+static void imx_hifi_shutdown(struct snd_pcm_substream *substream)
+{
+	struct snd_soc_pcm_runtime *rtd = substream->private_data;
+	struct snd_soc_card *card = rtd->card;
+	struct imx_wm8960_data *data = snd_soc_card_get_drvdata(card);
+	bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
+
+	data->is_stream_opened[tx] = false;
+}
+
+static struct snd_soc_ops imx_hifi_ops = {
+	.hw_params = imx_hifi_hw_params,
+	.hw_free = imx_hifi_hw_free,
+	.startup   = imx_hifi_startup,
+	.shutdown  = imx_hifi_shutdown,
+};
+
+static int imx_wm8960_late_probe(struct snd_soc_card *card)
+{
+	struct snd_soc_pcm_runtime *rtd = list_first_entry(
+		&card->rtd_list, struct snd_soc_pcm_runtime, list);
+	struct snd_soc_dai *codec_dai = rtd->codec_dai;
+	struct snd_soc_component *component = codec_dai->component;
+	struct imx_wm8960_data *data = snd_soc_card_get_drvdata(card);
+
+	/*
+	 * codec ADCLRC pin configured as GPIO, DACLRC pin is used as a frame
+	 * clock for ADCs and DACs
+	 */
+	snd_soc_component_update_bits(component, WM8960_IFACE2, 1<<6, 1<<6);
+
+	/* GPIO1 used as headphone detect output */
+	snd_soc_component_update_bits(component, WM8960_ADDCTL4, 7<<4, 3<<4);
+
+	/* Enable headphone jack detect */
+	snd_soc_component_update_bits(component, WM8960_ADDCTL2, 1<<6, 1<<6);
+	snd_soc_component_update_bits(component, WM8960_ADDCTL2, 1<<5,
+				      data->hp_det[1]<<5);
+	snd_soc_component_update_bits(component, WM8960_ADDCTL4, 3<<2,
+				      data->hp_det[0]<<2);
+	snd_soc_component_update_bits(component, WM8960_ADDCTL1, 3, 3);
+
+	return 0;
+}
+
+static int be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd,
+			struct snd_pcm_hw_params *params)
+{
+	struct snd_soc_card *card = rtd->card;
+	struct imx_wm8960_data *data = snd_soc_card_get_drvdata(card);
+	struct imx_priv *priv = &card_priv;
+	struct snd_interval *rate;
+	struct snd_mask *mask;
+
+	if (!priv->asrc_pdev)
+		return -EINVAL;
+
+	rate = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
+	rate->max = rate->min = data->asrc_rate;
+
+	mask = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT);
+	snd_mask_none(mask);
+	snd_mask_set(mask, data->asrc_format);
+
+	return 0;
+}
+
+static struct snd_soc_dai_link imx_wm8960_dai[] = {
+	{
+		.name = "HiFi",
+		.stream_name = "HiFi",
+		.codec_dai_name = "wm8960-hifi",
+		.ops = &imx_hifi_ops,
+	},
+	{
+		.name = "HiFi-ASRC-FE",
+		.stream_name = "HiFi-ASRC-FE",
+		.codec_name = "snd-soc-dummy",
+		.codec_dai_name = "snd-soc-dummy-dai",
+		.dynamic = 1,
+		.ignore_pmdown_time = 1,
+		.dpcm_playback = 1,
+		.dpcm_capture = 1,
+		.dpcm_merged_chan = 1,
+	},
+	{
+		.name = "HiFi-ASRC-BE",
+		.stream_name = "HiFi-ASRC-BE",
+		.codec_dai_name = "wm8960-hifi",
+		.platform_name = "snd-soc-dummy",
+		.no_pcm = 1,
+		.ignore_pmdown_time = 1,
+		.dpcm_playback = 1,
+		.dpcm_capture = 1,
+		.ops = &imx_hifi_ops,
+		.be_hw_params_fixup = be_hw_params_fixup,
+	},
+};
+
+static int of_parse_gpr(struct platform_device *pdev,
+			struct imx_wm8960_data *data)
+{
+	int ret;
+	struct of_phandle_args args;
+
+	if (of_device_is_compatible(pdev->dev.of_node,
+				    "fsl,imx7d-evk-wm8960"))
+		return 0;
+
+	ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node,
+					       "gpr", 3, 0, &args);
+	if (ret) {
+		dev_warn(&pdev->dev, "failed to get gpr property\n");
+		return ret;
+	}
+
+	data->gpr = syscon_node_to_regmap(args.np);
+	if (IS_ERR(data->gpr)) {
+		ret = PTR_ERR(data->gpr);
+		dev_err(&pdev->dev, "failed to get gpr regmap\n");
+		return ret;
+	}
+
+	regmap_update_bits(data->gpr, args.args[0], args.args[1],
+			   args.args[2]);
+
+	return 0;
+}
+
+static int imx_wm8960_probe(struct platform_device *pdev)
+{
+	struct device_node *cpu_np = NULL, *codec_np = NULL;
+	struct platform_device *cpu_pdev;
+	struct imx_priv *priv = &card_priv;
+	struct imx_wm8960_data *data;
+	struct platform_device *asrc_pdev = NULL;
+	struct device_node *asrc_np;
+	u32 width;
+	int ret;
+
+	priv->pdev = pdev;
+	dev_warn(&pdev->dev, "caicai\n");
+	data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
+	if (!data) {
+		ret = -ENOMEM;
+		goto fail;
+	}
+
+	if (of_property_read_bool(pdev->dev.of_node, "codec-rpmsg"))
+		data->is_codec_rpmsg = true;
+
+	cpu_np = of_parse_phandle(pdev->dev.of_node, "cpu-dai", 0);
+	if (!cpu_np) {
+		dev_err(&pdev->dev, "cpu dai phandle missing or invalid\n");
+		ret = -EINVAL;
+		goto fail;
+	}
+
+	cpu_pdev = of_find_device_by_node(cpu_np);
+	if (!cpu_pdev) {
+		dev_err(&pdev->dev, "failed to find SAI platform device\n");
+		ret = -EINVAL;
+		goto fail;
+	}
+
+	codec_np = of_parse_phandle(pdev->dev.of_node, "audio-codec", 0);
+	if (!codec_np) {
+		dev_err(&pdev->dev, "phandle missing or invalid\n");
+		ret = -EINVAL;
+		goto fail;
+	}
+
+	if (data->is_codec_rpmsg) {
+		struct platform_device *codec_dev;
+
+		codec_dev = of_find_device_by_node(codec_np);
+		if (!codec_dev || !codec_dev->dev.driver) {
+			dev_err(&pdev->dev, "failed to find codec platform device\n");
+			ret = -EINVAL;
+			goto fail;
+		}
+
+		data->codec_clk = devm_clk_get(&codec_dev->dev, "mclk");
+		if (IS_ERR(data->codec_clk)) {
+			ret = PTR_ERR(data->codec_clk);
+			dev_err(&pdev->dev, "failed to get codec clk: %d\n", ret);
+			goto fail;
+		}
+	} else {
+		struct i2c_client *codec_dev;
+
+		codec_dev = of_find_i2c_device_by_node(codec_np);
+		if (!codec_dev || !codec_dev->dev.driver) {
+			dev_err(&pdev->dev, "failed to find codec platform device\n");
+			ret = -EINVAL;
+			goto fail;
+		}
+
+		data->codec_clk = devm_clk_get(&codec_dev->dev, "mclk");
+		if (IS_ERR(data->codec_clk)) {
+			ret = PTR_ERR(data->codec_clk);
+			dev_err(&pdev->dev, "failed to get codec clk: %d\n", ret);
+			goto fail;
+		}
+	}
+
+	if (of_property_read_bool(pdev->dev.of_node, "codec-master"))
+		data->is_codec_master = true;
+
+	ret = of_parse_gpr(pdev, data);
+	if (ret)
+		goto fail;
+
+	of_property_read_u32_array(pdev->dev.of_node, "hp-det", data->hp_det, 2);
+
+	asrc_np = of_parse_phandle(pdev->dev.of_node, "asrc-controller", 0);
+	if (asrc_np) {
+		asrc_pdev = of_find_device_by_node(asrc_np);
+		priv->asrc_pdev = asrc_pdev;
+	}
+
+	data->card.dai_link = imx_wm8960_dai;
+
+	if (data->is_codec_rpmsg) {
+		imx_wm8960_dai[0].codec_name     = "rpmsg-audio-codec-wm8960";
+		imx_wm8960_dai[0].codec_dai_name = "rpmsg-wm8960-hifi";
+	} else
+		imx_wm8960_dai[0].codec_of_node	= codec_np;
+
+	imx_wm8960_dai[0].cpu_dai_name = dev_name(&cpu_pdev->dev);
+	imx_wm8960_dai[0].platform_of_node = cpu_np;
+
+	if (!asrc_pdev) {
+		data->card.num_links = 1;
+	} else {
+		imx_wm8960_dai[1].cpu_of_node = asrc_np;
+		imx_wm8960_dai[1].platform_of_node = asrc_np;
+		if (data->is_codec_rpmsg) {
+			imx_wm8960_dai[2].codec_name     = "rpmsg-audio-codec-wm8960";
+			imx_wm8960_dai[2].codec_dai_name = "rpmsg-wm8960-hifi";
+		} else
+			imx_wm8960_dai[2].codec_of_node	= codec_np;
+		imx_wm8960_dai[2].cpu_dai_name = dev_name(&cpu_pdev->dev);
+		data->card.num_links = 3;
+
+		ret = of_property_read_u32(asrc_np, "fsl,asrc-rate",
+				&data->asrc_rate);
+		if (ret) {
+			dev_err(&pdev->dev, "failed to get output rate\n");
+			ret = -EINVAL;
+			goto fail;
+		}
+
+		ret = of_property_read_u32(asrc_np, "fsl,asrc-width", &width);
+		if (ret) {
+			dev_err(&pdev->dev, "failed to get output rate\n");
+			ret = -EINVAL;
+			goto fail;
+		}
+
+		if (width == 24)
+			data->asrc_format = SNDRV_PCM_FORMAT_S24_LE;
+		else
+			data->asrc_format = SNDRV_PCM_FORMAT_S16_LE;
+	}
+
+	data->card.dev = &pdev->dev;
+	data->card.owner = THIS_MODULE;
+	ret = snd_soc_of_parse_card_name(&data->card, "model");
+	if (ret)
+		goto fail;
+	data->card.dapm_widgets = imx_wm8960_dapm_widgets;
+	data->card.num_dapm_widgets = ARRAY_SIZE(imx_wm8960_dapm_widgets);
+
+	ret = snd_soc_of_parse_audio_routing(&data->card, "audio-routing");
+	if (ret)
+		goto fail;
+
+	data->card.late_probe = imx_wm8960_late_probe;
+
+	platform_set_drvdata(pdev, &data->card);
+	snd_soc_card_set_drvdata(&data->card, data);
+	ret = devm_snd_soc_register_card(&pdev->dev, &data->card);
+	if (ret) {
+		dev_err(&pdev->dev, "snd_soc_register_card failed (%d)\n", ret);
+		goto fail;
+	}
+
+	imx_hp_jack_gpio.gpio = of_get_named_gpio_flags(pdev->dev.of_node,
+			"hp-det-gpios", 0, &priv->hp_active_low);
+
+	imx_mic_jack_gpio.gpio = of_get_named_gpio_flags(pdev->dev.of_node,
+			"mic-det-gpios", 0, &priv->mic_active_low);
+
+	if (gpio_is_valid(imx_hp_jack_gpio.gpio) &&
+	    gpio_is_valid(imx_mic_jack_gpio.gpio) &&
+	    imx_hp_jack_gpio.gpio == imx_mic_jack_gpio.gpio)
+		priv->is_headset_jack = true;
+
+	if (gpio_is_valid(imx_hp_jack_gpio.gpio)) {
+		if (priv->is_headset_jack) {
+			imx_hp_jack_pin.mask |= SND_JACK_MICROPHONE;
+			imx_hp_jack_gpio.report |= SND_JACK_MICROPHONE;
+		}
+
+		imx_hp_jack_gpio.jack_status_check = hp_jack_status_check;
+		imx_hp_jack_gpio.data = &imx_hp_jack;
+		ret = imx_wm8960_jack_init(&data->card, &imx_hp_jack,
+					   &imx_hp_jack_pin, &imx_hp_jack_gpio);
+		if (ret) {
+			dev_warn(&pdev->dev, "hp jack init failed (%d)\n", ret);
+			goto out;
+		}
+
+		ret = driver_create_file(pdev->dev.driver, &driver_attr_headphone);
+		if (ret)
+			dev_warn(&pdev->dev, "create hp attr failed (%d)\n", ret);
+	}
+
+	if (gpio_is_valid(imx_mic_jack_gpio.gpio)) {
+		if (!priv->is_headset_jack) {
+			imx_mic_jack_gpio.jack_status_check = mic_jack_status_check;
+			imx_mic_jack_gpio.data = &imx_mic_jack;
+			ret = imx_wm8960_jack_init(&data->card, &imx_mic_jack,
+					&imx_mic_jack_pins, &imx_mic_jack_gpio);
+			if (ret) {
+				dev_warn(&pdev->dev, "mic jack init failed (%d)\n", ret);
+				goto out;
+			}
+		}
+		ret = driver_create_file(pdev->dev.driver, &driver_attr_micphone);
+		if (ret)
+			dev_warn(&pdev->dev, "create mic attr failed (%d)\n", ret);
+	}
+
+out:
+	ret = 0;
+fail:
+	if (cpu_np)
+		of_node_put(cpu_np);
+	if (codec_np)
+		of_node_put(codec_np);
+
+	return ret;
+}
+
+static int imx_wm8960_remove(struct platform_device *pdev)
+{
+	driver_remove_file(pdev->dev.driver, &driver_attr_micphone);
+	driver_remove_file(pdev->dev.driver, &driver_attr_headphone);
+
+	return 0;
+}
+
+static const struct of_device_id imx_wm8960_dt_ids[] = {
+	{ .compatible = "fsl,imx-audio-wm8960", },
+	{ .compatible = "fsl,imx7d-evk-wm8960"  },
+	{ /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, imx_wm8960_dt_ids);
+
+static struct platform_driver imx_wm8960_driver = {
+	.driver = {
+		.name = "imx-wm8960",
+		.pm = &snd_soc_pm_ops,
+		.of_match_table = imx_wm8960_dt_ids,
+	},
+	.probe = imx_wm8960_probe,
+	.remove = imx_wm8960_remove,
+};
+module_platform_driver(imx_wm8960_driver);
+
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_DESCRIPTION("Freescale i.MX WM8960 ASoC machine driver");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("platform:imx-wm8960");
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/wm8960/wm8960.h b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/wm8960/wm8960.h
new file mode 100644
index 0000000000000000000000000000000000000000..ab3220d3411d26ef8dfe0fafdc213a5728fbfd41
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/modules/wm8960/wm8960.h
@@ -0,0 +1,114 @@
+/*
+ * wm8960.h  --  WM8960 Soc Audio driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef _WM8960_H
+#define _WM8960_H
+
+/* WM8960 register space */
+
+
+#define WM8960_CACHEREGNUM 	56
+
+#define WM8960_LINVOL		0x0
+#define WM8960_RINVOL		0x1
+#define WM8960_LOUT1		0x2
+#define WM8960_ROUT1		0x3
+#define WM8960_CLOCK1		0x4
+#define WM8960_DACCTL1		0x5
+#define WM8960_DACCTL2		0x6
+#define WM8960_IFACE1		0x7
+#define WM8960_CLOCK2		0x8
+#define WM8960_IFACE2		0x9
+#define WM8960_LDAC		0xa
+#define WM8960_RDAC		0xb
+
+#define WM8960_RESET		0xf
+#define WM8960_3D		0x10
+#define WM8960_ALC1		0x11
+#define WM8960_ALC2		0x12
+#define WM8960_ALC3		0x13
+#define WM8960_NOISEG		0x14
+#define WM8960_LADC		0x15
+#define WM8960_RADC		0x16
+#define WM8960_ADDCTL1		0x17
+#define WM8960_ADDCTL2		0x18
+#define WM8960_POWER1		0x19
+#define WM8960_POWER2		0x1a
+#define WM8960_ADDCTL3		0x1b
+#define WM8960_APOP1		0x1c
+#define WM8960_APOP2		0x1d
+
+#define WM8960_LINPATH		0x20
+#define WM8960_RINPATH		0x21
+#define WM8960_LOUTMIX		0x22
+
+#define WM8960_ROUTMIX		0x25
+#define WM8960_MONOMIX1		0x26
+#define WM8960_MONOMIX2		0x27
+#define WM8960_LOUT2		0x28
+#define WM8960_ROUT2		0x29
+#define WM8960_MONO		0x2a
+#define WM8960_INBMIX1		0x2b
+#define WM8960_INBMIX2		0x2c
+#define WM8960_BYPASS1		0x2d
+#define WM8960_BYPASS2		0x2e
+#define WM8960_POWER3		0x2f
+#define WM8960_ADDCTL4		0x30
+#define WM8960_CLASSD1		0x31
+
+#define WM8960_CLASSD3		0x33
+#define WM8960_PLL1		0x34
+#define WM8960_PLL2		0x35
+#define WM8960_PLL3		0x36
+#define WM8960_PLL4		0x37
+
+
+/*
+ * WM8960 Clock dividers
+ */
+#define WM8960_SYSCLKDIV 		0
+#define WM8960_DACDIV			1
+#define WM8960_OPCLKDIV			2
+#define WM8960_DCLKDIV			3
+#define WM8960_TOCLKSEL			4
+
+#define WM8960_SYSCLK_DIV_1		(0 << 1)
+#define WM8960_SYSCLK_DIV_2		(2 << 1)
+
+#define WM8960_SYSCLK_MCLK		(0 << 0)
+#define WM8960_SYSCLK_PLL		(1 << 0)
+#define WM8960_SYSCLK_AUTO		(2 << 0)
+
+#define WM8960_DAC_DIV_1		(0 << 3)
+#define WM8960_DAC_DIV_1_5		(1 << 3)
+#define WM8960_DAC_DIV_2		(2 << 3)
+#define WM8960_DAC_DIV_3		(3 << 3)
+#define WM8960_DAC_DIV_4		(4 << 3)
+#define WM8960_DAC_DIV_5_5		(5 << 3)
+#define WM8960_DAC_DIV_6		(6 << 3)
+
+#define WM8960_DCLK_DIV_1_5		(0 << 6)
+#define WM8960_DCLK_DIV_2		(1 << 6)
+#define WM8960_DCLK_DIV_3		(2 << 6)
+#define WM8960_DCLK_DIV_4		(3 << 6)
+#define WM8960_DCLK_DIV_6		(4 << 6)
+#define WM8960_DCLK_DIV_8		(5 << 6)
+#define WM8960_DCLK_DIV_12		(6 << 6)
+#define WM8960_DCLK_DIV_16		(7 << 6)
+
+#define WM8960_TOCLK_F19		(0 << 1)
+#define WM8960_TOCLK_F21		(1 << 1)
+
+#define WM8960_OPCLK_DIV_1		(0 << 0)
+#define WM8960_OPCLK_DIV_2		(1 << 0)
+#define WM8960_OPCLK_DIV_3		(2 << 0)
+#define WM8960_OPCLK_DIV_4		(3 << 0)
+#define WM8960_OPCLK_DIV_5_5		(4 << 0)
+#define WM8960_OPCLK_DIV_6		(5 << 0)
+
+#endif
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/overlays/ebf/imx-fire-rgb-led-overlay.dts b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/overlays/ebf/imx-fire-rgb-led-overlay.dts
new file mode 100644
index 0000000000000000000000000000000000000000..3d8eb8b6b56abf9129003d12a2e03017ccc2861e
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/overlays/ebf/imx-fire-rgb-led-overlay.dts
@@ -0,0 +1,62 @@
+/*
+ * Copyright (C) 2019 - All Rights Reserved by 
+ * filename : imx-fire-led-overlay.dts
+ * brief : Device Tree overlay for EBF6ull led device
+ * author : embedfire
+ * date : 2019-11-15 
+ * version : A001
+ */
+ /dts-v1/;
+ /plugin/;
+#include "imx6ul-pinfunc.h"
+#include "dt-bindings/gpio/gpio.h"
+ / {
+        fragment@0 {
+            target-path = "/";
+            __overlay__ {
+                rgb_led{
+                	#address-cells = <1>;
+                	#size-cells = <1>;
+                	compatible = "fire,rgb_led";
+                	/*红灯节点*/
+                	ranges;
+                	rgb_led_red@0x020C406C{
+                		compatible = "fire,rgb_led_red";
+                		reg = <0x020C406C 0x00000004
+                		       0x020E006C 0x00000004
+                		       0x020E02F8 0x00000004
+                			   0x0209C000 0x00000004
+                		       0x0209C004 0x00000004>;
+                		status = "okay";
+                	};
+
+
+                	/*绿灯节点*/
+                	rgb_led_green@0x020C4074{
+                		compatible = "fire,rgb_led_green";
+                		reg = <0x020C4074 0x00000004
+                		       0x020E01E0 0x00000004
+                		       0x020E046C 0x00000004
+                			   0x020A8000 0x00000004
+                		       0x020A8004 0x00000004>;
+                		status = "okay";
+                	};
+
+					/*蓝灯节点*/
+                	rgb_led_blue@0x020C4074{
+                		compatible = "fire,rgb_led_blue";
+                		reg = <0x020C4074 0x00000004
+                		       0x020E01DC 0x00000004
+                		       0x020E0468 0x00000004
+                			   0x020A8000 0x00000004
+                		       0x020A8004 0x00000004>;
+                		status = "okay";
+                	};
+                	
+                };
+            };
+        };
+ };
+
+
+
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/scripts/Kbuild.include b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/scripts/Kbuild.include
new file mode 100644
index 0000000000000000000000000000000000000000..978416dd31ca0efeacfd938e961b241aca7633af
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/scripts/Kbuild.include
@@ -0,0 +1,278 @@
+####
+# kbuild: Generic definitions
+
+# Convenient variables
+comma   := ,
+squote  := '
+empty   :=
+space   := $(empty) $(empty)
+
+###
+# Name of target with a '.' as filename prefix. foo/bar.o => foo/.bar.o
+dot-target = $(dir $@).$(notdir $@)
+
+###
+# The temporary file to save gcc -MD generated dependencies must not
+# contain a comma
+depfile = $(subst $(comma),_,$(dot-target).d)
+
+###
+# filename of target with directory and extension stripped
+basetarget = $(basename $(notdir $@))
+
+###
+# filename of first prerequisite with directory and extension stripped
+baseprereq = $(basename $(notdir $<))
+
+###
+# Escape single quote for use in echo statements
+escsq = $(subst $(squote),'\$(squote)',$1)
+
+###
+# Easy method for doing a status message
+       kecho := :
+ quiet_kecho := echo
+silent_kecho := :
+kecho := $($(quiet)kecho)
+
+###
+# filechk is used to check if the content of a generated file is updated.
+# Sample usage:
+# define filechk_sample
+#	echo $KERNELRELEASE
+# endef
+# version.h : Makefile
+#	$(call filechk,sample)
+# The rule defined shall write to stdout the content of the new file.
+# The existing file will be compared with the new one.
+# - If no file exist it is created
+# - If the content differ the new file is used
+# - If they are equal no change, and no timestamp update
+# - stdin is piped in from the first prerequisite ($<) so one has
+#   to specify a valid file as first prerequisite (often the kbuild file)
+define filechk
+	$(Q)set -e;				\
+	$(kecho) '  CHK     $@';		\
+	mkdir -p $(dir $@);			\
+	$(filechk_$(1)) < $< > $@.tmp;		\
+	if [ -r $@ ] && cmp -s $@ $@.tmp; then	\
+		rm -f $@.tmp;			\
+	else					\
+		$(kecho) '  UPD     $@';	\
+		mv -f $@.tmp $@;		\
+	fi
+endef
+
+######
+# gcc support functions
+# See documentation in Documentation/kbuild/makefiles.txt
+
+# cc-cross-prefix
+# Usage: CROSS_COMPILE := $(call cc-cross-prefix, m68k-linux-gnu- m68k-linux-)
+# Return first prefix where a prefix$(CC) is found in PATH.
+# If no $(CC) found in PATH with listed prefixes return nothing
+cc-cross-prefix =  \
+	$(word 1, $(foreach c,$(1),                                   \
+		$(shell set -e;                                       \
+		if (which $(strip $(c))$(CC)) > /dev/null 2>&1 ; then \
+			echo $(c);                                    \
+		fi)))
+
+# output directory for tests below
+TMPOUT := $(if $(KBUILD_EXTMOD),$(firstword $(KBUILD_EXTMOD))/)
+
+# try-run
+# Usage: option = $(call try-run, $(CC)...-o "$$TMP",option-ok,otherwise)
+# Exit code chooses option. "$$TMP" is can be used as temporary file and
+# is automatically cleaned up.
+try-run = $(shell set -e;		\
+	TMP="$(TMPOUT).$$$$.tmp";	\
+	TMPO="$(TMPOUT).$$$$.o";	\
+	if ($(1)) >/dev/null 2>&1;	\
+	then echo "$(2)";		\
+	else echo "$(3)";		\
+	fi;				\
+	rm -f "$$TMP" "$$TMPO")
+
+# as-option
+# Usage: cflags-y += $(call as-option,-Wa$(comma)-isa=foo,)
+
+as-option = $(call try-run,\
+	$(CC) $(KBUILD_CFLAGS) $(1) -c -x assembler /dev/null -o "$$TMP",$(1),$(2))
+
+# as-instr
+# Usage: cflags-y += $(call as-instr,instr,option1,option2)
+
+as-instr = $(call try-run,\
+	printf "%b\n" "$(1)" | $(CC) $(KBUILD_AFLAGS) -c -x assembler -o "$$TMP" -,$(2),$(3))
+
+# cc-option
+# Usage: cflags-y += $(call cc-option,-march=winchip-c6,-march=i586)
+
+cc-option = $(call try-run,\
+	$(CC) $(KBUILD_CPPFLAGS) $(KBUILD_CFLAGS) $(1) -c -x c /dev/null -o "$$TMP",$(1),$(2))
+
+# cc-option-yn
+# Usage: flag := $(call cc-option-yn,-march=winchip-c6)
+cc-option-yn = $(call try-run,\
+	$(CC) $(KBUILD_CPPFLAGS) $(KBUILD_CFLAGS) $(1) -c -x c /dev/null -o "$$TMP",y,n)
+
+# cc-option-align
+# Prefix align with either -falign or -malign
+cc-option-align = $(subst -functions=0,,\
+	$(call cc-option,-falign-functions=0,-malign-functions=0))
+
+# cc-disable-warning
+# Usage: cflags-y += $(call cc-disable-warning,unused-but-set-variable)
+cc-disable-warning = $(call try-run,\
+	$(CC) $(KBUILD_CPPFLAGS) $(KBUILD_CFLAGS) -W$(strip $(1)) -c -x c /dev/null -o "$$TMP",-Wno-$(strip $(1)))
+
+# cc-version
+# Usage gcc-ver := $(call cc-version)
+cc-version = $(shell $(CONFIG_SHELL) $(srctree)/scripts/gcc-version.sh $(CC))
+
+# cc-fullversion
+# Usage gcc-ver := $(call cc-fullversion)
+cc-fullversion = $(shell $(CONFIG_SHELL) \
+	$(srctree)/scripts/gcc-version.sh -p $(CC))
+
+# cc-ifversion
+# Usage:  EXTRA_CFLAGS += $(call cc-ifversion, -lt, 0402, -O1)
+cc-ifversion = $(shell [ $(call cc-version, $(CC)) $(1) $(2) ] && echo $(3))
+
+# cc-ldoption
+# Usage: ldflags += $(call cc-ldoption, -Wl$(comma)--hash-style=both)
+cc-ldoption = $(call try-run,\
+	$(CC) $(1) -nostdlib -x c /dev/null -o "$$TMP",$(1),$(2))
+
+# ld-option
+# Usage: LDFLAGS += $(call ld-option, -X)
+ld-option = $(call try-run,\
+	$(CC) /dev/null -c -o "$$TMPO" ; $(LD) $(1) "$$TMPO" -o "$$TMP",$(1),$(2))
+
+# ar-option
+# Usage: KBUILD_ARFLAGS := $(call ar-option,D)
+# Important: no spaces around options
+ar-option = $(call try-run, $(AR) rc$(1) "$$TMP",$(1),$(2))
+
+######
+
+###
+# Shorthand for $(Q)$(MAKE) -f scripts/Makefile.build obj=
+# Usage:
+# $(Q)$(MAKE) $(build)=dir
+build := -f $(if $(KBUILD_SRC),$(srctree)/)scripts/Makefile.build obj
+
+###
+# Shorthand for $(Q)$(MAKE) -f scripts/Makefile.modbuiltin obj=
+# Usage:
+# $(Q)$(MAKE) $(modbuiltin)=dir
+modbuiltin := -f $(if $(KBUILD_SRC),$(srctree)/)scripts/Makefile.modbuiltin obj
+
+# Prefix -I with $(srctree) if it is not an absolute path.
+# skip if -I has no parameter
+addtree = $(if $(patsubst -I%,%,$(1)), \
+$(if $(filter-out -I/%,$(1)),$(patsubst -I%,-I$(srctree)/%,$(1))) $(1))
+
+# Find all -I options and call addtree
+flags = $(foreach o,$($(1)),$(if $(filter -I%,$(o)),$(call addtree,$(o)),$(o)))
+
+# echo command.
+# Short version is used, if $(quiet) equals `quiet_', otherwise full one.
+echo-cmd = $(if $($(quiet)cmd_$(1)),\
+	echo '  $(call escsq,$($(quiet)cmd_$(1)))$(echo-why)';)
+
+# printing commands
+cmd = @$(echo-cmd) $(cmd_$(1))
+
+# Add $(obj)/ for paths that are not absolute
+objectify = $(foreach o,$(1),$(if $(filter /%,$(o)),$(o),$(obj)/$(o)))
+
+###
+# if_changed      - execute command if any prerequisite is newer than
+#                   target, or command line has changed
+# if_changed_dep  - as if_changed, but uses fixdep to reveal dependencies
+#                   including used config symbols
+# if_changed_rule - as if_changed but execute rule instead
+# See Documentation/kbuild/makefiles.txt for more info
+
+ifneq ($(KBUILD_NOCMDDEP),1)
+# Check if both arguments has same arguments. Result is empty string if equal.
+# User may override this check using make KBUILD_NOCMDDEP=1
+arg-check = $(strip $(filter-out $(cmd_$(1)), $(cmd_$@)) \
+                    $(filter-out $(cmd_$@),   $(cmd_$(1))) )
+else
+arg-check = $(if $(strip $(cmd_$@)),,1)
+endif
+
+# >'< substitution is for echo to work,
+# >$< substitution to preserve $ when reloading .cmd file
+# note: when using inline perl scripts [perl -e '...$$t=1;...']
+# in $(cmd_xxx) double $$ your perl vars
+make-cmd = $(subst \\,\\\\,$(subst \#,\\\#,$(subst $$,$$$$,$(call escsq,$(cmd_$(1))))))
+
+# Find any prerequisites that is newer than target or that does not exist.
+# PHONY targets skipped in both cases.
+any-prereq = $(filter-out $(PHONY),$?) $(filter-out $(PHONY) $(wildcard $^),$^)
+
+# Execute command if command has changed or prerequisite(s) are updated.
+#
+if_changed = $(if $(strip $(any-prereq) $(arg-check)),                       \
+	@set -e;                                                             \
+	$(echo-cmd) $(cmd_$(1));                                             \
+	echo 'cmd_$@ := $(make-cmd)' > $(dot-target).cmd)
+
+# Execute the command and also postprocess generated .d dependencies file.
+if_changed_dep = $(if $(strip $(any-prereq) $(arg-check) ),                  \
+	@set -e;                                                             \
+	$(echo-cmd) $(cmd_$(1));                                             \
+	scripts/basic/fixdep $(depfile) $@ '$(make-cmd)' > $(dot-target).tmp;\
+	rm -f $(depfile);                                                    \
+	mv -f $(dot-target).tmp $(dot-target).cmd)
+
+# Usage: $(call if_changed_rule,foo)
+# Will check if $(cmd_foo) or any of the prerequisites changed,
+# and if so will execute $(rule_foo).
+if_changed_rule = $(if $(strip $(any-prereq) $(arg-check) ),                 \
+	@set -e;                                                             \
+	$(rule_$(1)))
+
+###
+# why - tell why a a target got build
+#       enabled by make V=2
+#       Output (listed in the order they are checked):
+#          (1) - due to target is PHONY
+#          (2) - due to target missing
+#          (3) - due to: file1.h file2.h
+#          (4) - due to command line change
+#          (5) - due to missing .cmd file
+#          (6) - due to target not in $(targets)
+# (1) PHONY targets are always build
+# (2) No target, so we better build it
+# (3) Prerequisite is newer than target
+# (4) The command line stored in the file named dir/.target.cmd
+#     differed from actual command line. This happens when compiler
+#     options changes
+# (5) No dir/.target.cmd file (used to store command line)
+# (6) No dir/.target.cmd file and target not listed in $(targets)
+#     This is a good hint that there is a bug in the kbuild file
+ifeq ($(KBUILD_VERBOSE),2)
+why =                                                                        \
+    $(if $(filter $@, $(PHONY)),- due to target is PHONY,                    \
+        $(if $(wildcard $@),                                                 \
+            $(if $(strip $(any-prereq)),- due to: $(any-prereq),             \
+                $(if $(arg-check),                                           \
+                    $(if $(cmd_$@),- due to command line change,             \
+                        $(if $(filter $@, $(targets)),                       \
+                            - due to missing .cmd file,                      \
+                            - due to $(notdir $@) not in $$(targets)         \
+                         )                                                   \
+                     )                                                       \
+                 )                                                           \
+             ),                                                              \
+             - due to target missing                                         \
+         )                                                                   \
+     )
+
+echo-why = $(call escsq, $(strip $(why)))
+endif
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/scripts/basic/fixdep b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/scripts/basic/fixdep
new file mode 100644
index 0000000000000000000000000000000000000000..cc412bec06c3cdec88a73fa135b0eef854cd138b
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/scripts/basic/fixdep
@@ -0,0 +1,27 @@
+#!/bin/sh
+
+# Simplfied version of Linux scripts/basic/fixdep. We don't need
+# CONFIG tracking etc for this usecase.
+
+
+# Fixdep's interface is described:
+
+# It is invoked as
+#
+#   fixdep <depfile> <target> <cmdline>
+#
+# and will read the dependency file <depfile>
+#
+# The transformed dependency snipped is written to stdout.
+#
+# It first generates a line
+#
+#   cmd_<target> = <cmdline>
+#
+# and then basically copies the .<target>.d file to stdout, in the
+# process filtering out the dependency on autoconf.h and adding
+# dependencies on include/config/my/option.h for every
+# CONFIG_MY_OPTION encountered in any of the prequisites.
+
+echo cmd_$2 = $3
+cat $1
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/scripts/cronjob b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/scripts/cronjob
new file mode 100644
index 0000000000000000000000000000000000000000..ccdbc0607e1b03715fb15fc0fb8e1af054b4edb9
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/scripts/cronjob
@@ -0,0 +1,124 @@
+#!/bin/bash
+
+set -e
+
+cd $(dirname $0)/..
+
+UPSTREAM_GIT="git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git"
+
+BRANCHES="master filter-state upstream/master upstream/dts"
+
+if [ ! -f scripts/filter.sh ] ; then
+    echo "`pwd`: does not appear to be a device-tree.git" 1>&2
+    exit 1
+fi
+
+if [ -z "$LATEST_VERSION" ] ; then
+    FINGER_BANNER="https://www.kernel.org/finger_banner"
+    LATEST_VERSION=$(wget --quiet -O - "$FINGER_BANNER" |\
+        sed -n -e '0,/^The latest mainline version of the Linux kernel is:\s*\(.*\)$/s//\1/p')
+fi
+
+if [ -z "$LATEST_VERSION" ] ; then
+    echo "Unable to determine latest version" 1>&2
+    exit 1
+fi
+
+echo "Latest Version: v$LATEST_VERSION"
+if ! git show-ref --quiet --verify refs/tags/v${LATEST_VERSION} ; then
+    echo "Latest version is new"
+fi
+if ! git show-ref --quiet --verify refs/tags/v${LATEST_VERSION}-dts ; then
+    echo "Latest version is unmerged"
+fi
+echo
+
+echo "Current State:"
+for branch in $BRANCHES ; do
+    REF=$(git show-ref --verify refs/heads/${branch})
+    if [ $? -ne 0 ] ; then
+	echo "Tree is missing required branch ${branch}, aborting" 1>&2
+	exit 1
+    fi
+    echo "  ${REF}"
+done
+echo
+
+trap '
+if [ -n "$FILTER_OUTPUT" ] ; then
+    echo "---------------------------------------------------------------------"
+    echo "Filter Output:"
+    echo "---------------------------------------------------------------------"
+    echo "$FILTER_OUTPUT"
+    echo
+fi
+if [ -n "$MERGE_OUTPUT" ] ; then
+    echo "---------------------------------------------------------------------"
+    echo "Merge Output:"
+    echo "---------------------------------------------------------------------"
+    echo "$MERGE_OUTPUT"
+    echo
+fi
+' EXIT
+
+FILTER_OUTPUT=`(
+set -e
+echo "Switching to master branch"
+git checkout master
+
+echo "Fetching $UPSTREAM_GIT master"
+git fetch --tags "$UPSTREAM_GIT" master
+echo
+
+echo "Filtering"
+./scripts/filter.sh
+echo
+) 2>&1 `
+
+#git push --dry-run origin filter-state upstream/dts upstream/master
+#git push --dry-run origin --tags
+#echo
+
+DATE=$(date +%Y%m%d)
+TESTBRANCH=test-${DATE}
+MERGE_OUTPUT=`(
+set -e
+git checkout -b ${TESTBRANCH} origin/master
+git merge --no-edit upstream/dts
+) 2>&1 `
+REF=$(git show-ref --verify refs/heads/${TESTBRANCH})
+echo "Testing: ${REF}"
+if git log ${TESTBRANCH} -- MAINTAINERS | grep --quiet . ; then
+    echo "Filter branch has upstream-only content (MAINTAINERS file)"
+    exit 1
+fi
+
+make clean -s
+TEST_OUTPUT=`make -k -s 2>&1 || true`
+if [ -z "${TEST_OUTPUT}" ]; then
+    echo "Success!"
+else
+    echo "---------------------------------------------------------------------"
+    echo "Test Output:"
+    echo "---------------------------------------------------------------------"
+    echo "$TEST_OUTPUT"
+fi
+echo
+
+echo "Switching back to master branch"
+git checkout master
+
+echo "Recording refs/tests/${DATE}"
+git update-ref refs/tests/${DATE} ${TESTBRANCH}
+
+echo "Removing ${TESTBRANCH}"
+git branch -D "${TESTBRANCH}"
+
+echo "Final State:"
+for branch in ${BRANCHES} ; do
+    REF=$(git show-ref --verify refs/heads/${branch})
+    echo "  ${REF}"
+done
+echo
+
+exit 0
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/scripts/filter.sh b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/scripts/filter.sh
new file mode 100644
index 0000000000000000000000000000000000000000..e1f6bac298843fa6f2d6d86214fffe1919df8221
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/scripts/filter.sh
@@ -0,0 +1,38 @@
+#!/bin/sh
+
+# git branch -D upstream/rewritten-prev upstream/master upstream/rewritten filter-state      
+
+set -e
+
+export SCRIPTS=$(dirname $(readlink -f $0))
+
+UPSTREAM_MASTER=upstream/master
+UPSTREAM_REWRITTEN=upstream/dts
+
+LAST=$(git show-ref -s refs/heads/$UPSTREAM_MASTER||true)
+if [ -n "$LAST" ] ; then
+    RANGE="$LAST..$UPSTREAM_REWRITTEN"
+else
+    # This must be a new conversion...
+    RANGE="$UPSTREAM_REWRITTEN"
+fi
+
+FETCH_HEAD=$(git rev-parse FETCH_HEAD)
+if [ "$LAST" = "$FETCH_HEAD" ] ; then
+	echo "Nothing new in FETCH_HEAD: $FETCH_HEAD"
+	exit 0
+fi
+
+rm -f .git/refs/original/refs/heads/${UPSTREAM_REWRITTEN}
+
+git branch -f $UPSTREAM_REWRITTEN FETCH_HEAD
+
+git filter-branch --force \
+	--index-filter ${SCRIPTS}/index-filter.sh \
+	--msg-filter 'cat && /bin/echo -e "\n[ upstream commit: $GIT_COMMIT ]"' \
+	--tag-name-filter 'while read t ; do /bin/echo -n $t-dts-raw ; done' \
+	--parent-filter 'sed "s/-p //g" | xargs -r git show-branch --independent | sed "s/\</-p /g"' \
+	--prune-empty --state-branch refs/heads/filter-state \
+	-- $RANGE
+
+git branch -f $UPSTREAM_MASTER FETCH_HEAD
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/scripts/index-filter.sh b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/scripts/index-filter.sh
new file mode 100644
index 0000000000000000000000000000000000000000..9610855020babb0db6e631da1f892dc60000cdd8
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/scripts/index-filter.sh
@@ -0,0 +1,14 @@
+#!/bin/bash
+
+set -e
+set -o pipefail
+
+${SCRIPTS}/rewrite-index.pl | GIT_INDEX_FILE=$GIT_INDEX_FILE.new git update-index --index-info
+
+if [ -f "$GIT_INDEX_FILE.new" ] ; then
+    mv "$GIT_INDEX_FILE.new" "$GIT_INDEX_FILE"
+else
+    rm "$GIT_INDEX_FILE"
+fi
+
+exit 0
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/scripts/merge-new-release.sh b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/scripts/merge-new-release.sh
new file mode 100644
index 0000000000000000000000000000000000000000..a2763c69bb1a787359bcb5b685d34cd06f0a9aa9
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/scripts/merge-new-release.sh
@@ -0,0 +1,48 @@
+#!/bin/bash
+
+case $1 in
+    v*-dts) ;;
+    '')
+	echo >&2 "No version given"
+	exit 1
+	;;
+    *)
+	echo >&2 "Unexpected version: $1"
+	exit 1
+	;;
+esac
+
+v=$1
+
+set -e
+
+# Use the date of Linus' originally tagged commit for the merge. This might
+# differ from what the commit that the rewritten tag points to, since the
+# orignal commit may have been discarded.
+export GIT_AUTHOR_DATE=$(git log -1 --format=%ad "${v%-dts}")
+if [ ! "${GIT_AUTHOR_DATE}" ] ; then
+    echo >&2 "Unable to determine commit date for merge"
+    exit 1
+fi
+if [ "${v}" = "v2.6.12-rc2-dts" ] ; then
+    auh="--allow-unrelated-histories"
+fi
+git merge $auh --no-edit "${v}-raw"
+git clean -fdqx
+# Use the date of Linus' original tag for the tag.
+case "${v%-dts}" in
+    v2.6.12*|v2.6.13-rc[123])
+        # Commits from v2.6.12-rc2..v2.6.13-rc3 lacked the date. So use the commit's
+        # date.
+        export GIT_COMMITTER_DATE="${GIT_AUTHOR_DATE}"
+        ;;
+    *)
+        export GIT_COMMITTER_DATE="$(git for-each-ref --format='%(taggerdate)' "refs/tags/${v%-dts}")"
+        ;;
+esac
+if [ ! "${GIT_COMMITTER_DATE}" ] ; then
+    echo >&2 "Unable to determine date for tag"
+    exit 1
+fi
+git tag -s -m "Tagging ${v}" -u 695A46C6 "${v}"
+make -k -j12 -s
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/scripts/pull.sh b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/scripts/pull.sh
new file mode 100644
index 0000000000000000000000000000000000000000..810c8ab42ad4f0809c18ceeeffdd3c427c093d4a
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/scripts/pull.sh
@@ -0,0 +1,7 @@
+#!/bin/bash
+
+git pull --no-edit git@github.com:beagleboard/bb.org-overlays.git master
+git pull --no-edit git@github.com:beagleboard/bb.org-overlays.git master --tags
+git pull --no-edit git@github.com:RobertCNelson/bb.org-overlays.git master
+git pull --no-edit git@github.com:RobertCNelson/bb.org-overlays.git master --tags
+
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/scripts/rewrite-index.pl b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/scripts/rewrite-index.pl
new file mode 100644
index 0000000000000000000000000000000000000000..ef89839ab1e025490c03d294d0e620eea95fb560
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/scripts/rewrite-index.pl
@@ -0,0 +1,72 @@
+#!/usr/bin/perl
+use strict;
+use warnings;
+use IPC::Open2;
+my $pid;
+
+open(my $lsfiles, "-|", "git ls-files -s") or die "fork lsfiles: $!";
+
+while (<$lsfiles>) {
+    if ($_ =~ m/^120000 ([0-9a-f]{40}) (.*)\t(.*)/) {
+	my ($obj, $stage, $path) = ($1,$2,$3);
+	if (!defined $pid) {
+	    $pid = open2(*Rderef, *Wderef, "git cat-file --batch-check='deref-ok %(objectname)' --follow-symlinks")
+		or die "open git cat-file: $!";
+	}
+	print Wderef "$ENV{GIT_COMMIT}:$path\n" or die "write Wderef: $!";
+	my $deref = <Rderef>;
+	if ($deref =~ m/^deref-ok ([0-9a-f]{40})$/) {
+	    $_ = "100644 $1 $stage\t$path\n"
+	} elsif ($deref =~ /^dangling /) {
+	    # Skip next line
+	    my $dummy = <Rderef>;
+	} else {
+	    die "Failed to parse symlink $ENV{GIT_COMMIT}:$path $deref";
+	}
+    }
+
+    my $m = 0;
+
+    # Keep the copyright. Also ensures we never have a completely empty commit.
+    $m++ if m/\tCOPYING$/;
+
+    # A few architectures have dts files at non standard paths. Massage those into
+    # a standard arch/ARCH/boot/dts first.
+
+    # symlink: arch/microblaze/boot/dts/system.dts -> ../../platform/generic/system.dts
+    next if m,\tarch/microblaze/boot/dts/system.dts$,;
+    $m++ if s,\tarch/microblaze/platform/generic/(system.dts)$,\tarch/microblaze/boot/dts/$1,;
+
+    # arch/mips/lantiq/dts/easy50712.dts
+    # arch/mips/lantiq/dts/danube.dtsi
+    # arch/mips/netlogic/dts/xlp_evp.dts
+    # arch/mips/ralink/dts/rt3050.dtsi
+    # arch/mips/ralink/dts/rt3052_eval.dts
+    $m++ if s,\tarch/mips/([^/]*)/dts/(.*\.dts.?)$,\tarch/mips/boot/dts/$2,;
+
+    # arch/mips/cavium-octeon/octeon_68xx.dts
+    # arch/mips/cavium-octeon/octeon_3xxx.dts
+    # arch/mips/mti-sead3/sead3.dts
+    $m++ if s,\tarch/mips/([^/]*)/([^/]*\.dts.?)$,\tarch/mips/boot/dts/$2,;
+
+    # arch/x86/platform/ce4100/falconfalls.dts
+    $m++ if s,\tarch/x86/platform/ce4100/falconfalls.dts,\tarch/x86/boot/dts/falconfalls.dts,;
+
+    # test cases
+    $m++ if s,\tdrivers/of/testcase-data/,\ttestcase-data/,;
+
+    # Now rewrite generic DTS paths
+    $m++ if s,\tarch/([^/]*)/boot/dts/(.*\.dts.?)$,\tsrc/$1/$2,;
+    $m++ if s,\tarch/([^/]*)/boot/dts/(.*\.h)$,\tsrc/$1/$2,;
+
+    # Also rewrite the DTS include paths for dtc+cpp support
+    $m++ if s,\tarch/([^/]*)/include/dts/,\tsrc/$1/include/,;
+    $m++ if s,\tinclude/dt-bindings/,\tinclude/dt-bindings/,;
+
+    # Rewrite the bindings subdirectory
+    $m++ if s,\tDocumentation/devicetree/bindings/,\tBindings/,;
+
+    print if $m > 0;
+}
+kill $pid if $pid;
+exit 0;
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/tools/beaglebone-universal-io/LICENSE b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/tools/beaglebone-universal-io/LICENSE
new file mode 100644
index 0000000000000000000000000000000000000000..d7f105139782ab695d86613e343916f7372f4ac0
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/tools/beaglebone-universal-io/LICENSE
@@ -0,0 +1,339 @@
+GNU GENERAL PUBLIC LICENSE
+                       Version 2, June 1991
+
+ Copyright (C) 1989, 1991 Free Software Foundation, Inc., <http://fsf.org/>
+ 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
+ Everyone is permitted to copy and distribute verbatim copies
+ of this license document, but changing it is not allowed.
+
+                            Preamble
+
+  The licenses for most software are designed to take away your
+freedom to share and change it.  By contrast, the GNU General Public
+License is intended to guarantee your freedom to share and change free
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+General Public License applies to most of the Free Software
+Foundation's software and to any other program whose authors commit to
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+
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+
+These requirements apply to the modified work as a whole.  If
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+distribute the same sections as part of a whole which is a work based
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+
+  6. Each time you redistribute the Program (or any work based on the
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+
+This section is intended to make thoroughly clear what is believed to
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+
+  8. If the distribution and/or use of the Program is restricted in
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+  9. The Free Software Foundation may publish revised and/or new versions
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+
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+Foundation.
+
+  10. If you wish to incorporate parts of the Program into other free
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+
+                            NO WARRANTY
+
+  11. BECAUSE THE PROGRAM IS LICENSED FREE OF CHARGE, THERE IS NO WARRANTY
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+  12. IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING
+WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MAY MODIFY AND/OR
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+YOU OR THIRD PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER
+PROGRAMS), EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGES.
+
+                     END OF TERMS AND CONDITIONS
+
+            How to Apply These Terms to Your New Programs
+
+  If you develop a new program, and you want it to be of the greatest
+possible use to the public, the best way to achieve this is to make it
+free software which everyone can redistribute and change under these terms.
+
+  To do so, attach the following notices to the program.  It is safest
+to attach them to the start of each source file to most effectively
+convey the exclusion of warranty; and each file should have at least
+the "copyright" line and a pointer to where the full notice is found.
+
+    {description}
+    Copyright (C) {year}  {fullname}
+
+    This program is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 2 of the License, or
+    (at your option) any later version.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License along
+    with this program; if not, write to the Free Software Foundation, Inc.,
+    51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+
+Also add information on how to contact you by electronic and paper mail.
+
+If the program is interactive, make it output a short notice like this
+when it starts in an interactive mode:
+
+    Gnomovision version 69, Copyright (C) year name of author
+    Gnomovision comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
+    This is free software, and you are welcome to redistribute it
+    under certain conditions; type `show c' for details.
+
+The hypothetical commands `show w' and `show c' should show the appropriate
+parts of the General Public License.  Of course, the commands you use may
+be called something other than `show w' and `show c'; they could even be
+mouse-clicks or menu items--whatever suits your program.
+
+You should also get your employer (if you work as a programmer) or your
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+
+  Yoyodyne, Inc., hereby disclaims all copyright interest in the program
+  `Gnomovision' (which makes passes at compilers) written by James Hacker.
+
+  {signature of Ty Coon}, 1 April 1989
+  Ty Coon, President of Vice
+
+This General Public License does not permit incorporating your program into
+proprietary programs.  If your program is a subroutine library, you may
+consider it more useful to permit linking proprietary applications with the
+library.  If this is what you want to do, use the GNU Lesser General
+Public License instead of this License.
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/tools/beaglebone-universal-io/README.md b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/tools/beaglebone-universal-io/README.md
new file mode 100644
index 0000000000000000000000000000000000000000..d3b97b5855bf6f1c2067f04de41783fa3375034c
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/tools/beaglebone-universal-io/README.md
@@ -0,0 +1,139 @@
+# beaglebone-universal-io
+
+## Overview
+
+Device tree overlay and support scripts for using most available
+hardware I/O on the BeagleBone without editing dts files or rebuilding
+the kernel.
+
+This project is a series of four overlay files, designed to work with
+the BeagleBone Black:
+
+  * cape-universal  Exports all pins not used by HDMIN and eMMC (including audio)
+  * cape-universaln Exports all pins not used by HDMI and eMMC (no audio pins are exported)
+  * cape-unversalh  Exports all pins not used by eMMC
+  * cape-unversala  Exports all pins
+  * cape-univ-emmc  Exports pins used by eMMC, load if eMMC is disabled
+  * cape-univ-hdmi  Exports pins used by HDMI video, load if HDMI is disabled
+  * cape-univ-audio Exports pins used by HDMI audio
+
+
+## Usage
+
+If using a 3.14 or newer kernel, make sure your device tree inclues the
+pinmux helper entries required for the pins you want to use.  If you're
+using an RCN built kernel (if you don't know, you probably are), these
+should be present by default.
+
+If using a 3.8.13 kernel with capemgr, load the overlay as usual
+
+    echo cape-universaln > /sys/devices/bone_capemgr.*/slots
+    
+From kernel 4.1 the slots file lives in a new home
+
+    echo cape-universaln > /sys/devices/platform/bone_capemgr/slots
+
+At this point, the various devices are loaded and all gpio have been
+exported.  All pins currently default to gpio inputs, with pull up or
+pull down resistors set the same as when the AM335x comes out of reset.
+This behavior may change, however.  If the BeagleBone begins shipping
+with some I/O pins configured by default at boot, this overlay will
+likely change to match.
+
+The provided config-pin utility is intended to assist with  setting up
+the various pin modes and querying the current pin state.
+
+```
+# Configure a pin for a specific mode
+config-pin P8.07 timer
+
+# Configure a pin as gpio output and setting the state
+config-pin P8.07 hi
+config-pin P8.07 low
+
+# Configure a pin as a gpio input
+config-pin P8.07 in
+
+# List the valid modes for a specific pin
+config-pin -l P8.07
+
+# Query the status of a pin (note the appropriate universal cape
+# must be loaded for this to work)
+config-pin -q P8.07
+
+# Complete usage details
+config-pin -h
+```
+
+## GUI 
+
+You can find a Qt based graphical user interface for the
+beaglebone-universal-io here: https://github.com/strahlex/BBIOConfig
+
+
+## Details
+
+If you wish to setup the pins manually, or to know what is happening
+behind the curtain, keep reading.
+
+To control the gpio pins, you may use the sysfs interface.  Each
+exported gpio pin has an entry under /sys/class/gpio/gpioNN, where NN
+represents the kernel gpio number for that pin.  If you have forgotten
+the BeagleBone pin to kernel gpio number mapping, you may refer to the
+list created for you in the status file of the device tree overlay:
+
+    root@arm:~# cat /sys/devices/ocp.*/cape-universal.*/status
+     0 P9_92                    114 IN  0
+     1 P9_42                      7 IN  0
+     2 P9_91                    116 IN  0
+     3 P9_41                     20 IN  0
+     4 P9_31                    110 IN  0
+     5 P9_30                    112 IN  0
+     ...
+
+Pin multiplexing is controled via files in /sys/devices/ocp.*/, where
+each exported I/O pin has a pinmux control directory.  The directory is
+named using the actual BeagleBone pin header number, so P8_ or P9_ 
+followed by the pin number, the suffix _pinmux, and an instance number
+(that is subject to change).  So a typical full path to the pinmux
+control directory for P8 pin 7 might be:
+
+    /sys/devices/ocp.3/P8_07_pinmux.13/
+
+However since the instance numbers are subject to change, you are
+advised to use shell wildcards for the instance values when referencing
+these paths:
+
+    /sys/devices/ocp.*/P8_07_pinmux.*/
+
+Each pinmux directory contains a state file, which you can read to
+determine the current pinmux setting of the pin:
+
+    root@arm:~# cat /sys/devices/ocp.*/P8_07_pinmux.*/state
+    default
+
+Or you can write to change the pinmux setting for the pin:
+
+    root@arm:~# echo timer > /sys/devices/ocp.*/P8_07_pinmux.*/state
+    root@arm:~# cat /sys/devices/ocp.*/P8_07_pinmux.*/state
+    timer
+
+Each pin has a default state and a gpio state.  Currently the default
+state for all pins is gpio with pull-up/down resistor set to the reset
+default value, but this could change.  If the BeagleBone begins shipping
+with a default I/O setup that enables some special functions, this
+overlay will likely change to match.  Most pins have other functions
+available besides gpio, see the list below for valid settings.
+
+For a list of valid pinmux states for each pin, use the config-pin
+utility:
+
+    config-pin -l <pin>
+
+You will need to reference the AM335x data sheet and Technical Reference
+Manual from TI to determine how to setup pin multiplexing for the
+various special functions.  I find the following reference quite
+helpful, particularly the spreadsheet file:
+
+https://github.com/selsinork/beaglebone-black-pinmux
+
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/tools/convert-to-am33xx_iopad.sh b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/tools/convert-to-am33xx_iopad.sh
new file mode 100644
index 0000000000000000000000000000000000000000..a7bdbe69e153d26d81f8bb062d165d264306690b
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/tools/convert-to-am33xx_iopad.sh
@@ -0,0 +1,37 @@
+#!/bin/bash -e
+
+#cape-univ*-00A0.dts
+
+#sed -i -e 's:_pin {:_pin { pinctrl-single,pins = <:g' src/arm/cape-univ*-00A0.dts
+#sed -i -e 's:				pinctrl-single,pins = <0x0:				AM33XX_IOPAD(0x08:g' src/arm/cape-univ*-00A0.dts
+#sed -i -e 's:				pinctrl-single,pins = <0x1:				AM33XX_IOPAD(0x09:g' src/arm/cape-univ*-00A0.dts
+
+sed -i -e 's:  0x00>; };:, PIN_OUTPUT_PULLDOWN | MUX_MODE0) >; };:g' src/arm/cape-univ*-00A0.dts
+sed -i -e 's:  0x01>; };:, PIN_OUTPUT_PULLDOWN | MUX_MODE1) >; };:g' src/arm/cape-univ*-00A0.dts
+sed -i -e 's:  0x02>; };:, PIN_OUTPUT_PULLDOWN | MUX_MODE2) >; };:g' src/arm/cape-univ*-00A0.dts
+sed -i -e 's:  0x03>; };:, PIN_OUTPUT_PULLDOWN | MUX_MODE3) >; };:g' src/arm/cape-univ*-00A0.dts
+sed -i -e 's:  0x04>; };:, PIN_OUTPUT_PULLDOWN | MUX_MODE4) >; };:g' src/arm/cape-univ*-00A0.dts
+sed -i -e 's:  0x05>; };:, PIN_OUTPUT_PULLDOWN | MUX_MODE5) >; };:g' src/arm/cape-univ*-00A0.dts
+sed -i -e 's:  0x06>; };:, PIN_OUTPUT_PULLDOWN | MUX_MODE6) >; };:g' src/arm/cape-univ*-00A0.dts
+sed -i -e 's:  0x07>; };:, PIN_OUTPUT_PULLDOWN | MUX_MODE7) >; };:g' src/arm/cape-univ*-00A0.dts
+
+sed -i -e 's:  0x20>; };:, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE0) >; };:g' src/arm/cape-univ*-00A0.dts
+sed -i -e 's:  0x21>; };:, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE1) >; };:g' src/arm/cape-univ*-00A0.dts
+sed -i -e 's:  0x22>; };:, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE2) >; };:g' src/arm/cape-univ*-00A0.dts
+sed -i -e 's:  0x23>; };:, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE3) >; };:g' src/arm/cape-univ*-00A0.dts
+sed -i -e 's:  0x24>; };:, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE4) >; };:g' src/arm/cape-univ*-00A0.dts
+sed -i -e 's:  0x25>; };:, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE5) >; };:g' src/arm/cape-univ*-00A0.dts
+sed -i -e 's:  0x26>; };:, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE6) >; };:g' src/arm/cape-univ*-00A0.dts
+sed -i -e 's:  0x27>; };:, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };:g' src/arm/cape-univ*-00A0.dts
+
+sed -i -e 's:  0x2F>; };:, PIN_OUTPUT | INPUT_EN | MUX_MODE7) >; };:g' src/arm/cape-univ*-00A0.dts
+
+sed -i -e 's:  0x30>; };:, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE0) >; };:g' src/arm/cape-univ*-00A0.dts
+sed -i -e 's:  0x31>; };:, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE1) >; };:g' src/arm/cape-univ*-00A0.dts
+sed -i -e 's:  0x32>; };:, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE2) >; };:g' src/arm/cape-univ*-00A0.dts
+sed -i -e 's:  0x33>; };:, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE3) >; };:g' src/arm/cape-univ*-00A0.dts
+sed -i -e 's:  0x34>; };:, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE4) >; };:g' src/arm/cape-univ*-00A0.dts
+sed -i -e 's:  0x35>; };:, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE5) >; };:g' src/arm/cape-univ*-00A0.dts
+sed -i -e 's:  0x36>; };:, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE6) >; };:g' src/arm/cape-univ*-00A0.dts
+sed -i -e 's:  0x37>; };:, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };:g' src/arm/cape-univ*-00A0.dts
+
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/tools/dtbo b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/tools/dtbo
new file mode 100644
index 0000000000000000000000000000000000000000..f8bcd59f227b1dcb540b6807b2445cfe3273e0b4
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/tools/dtbo
@@ -0,0 +1,15 @@
+#!/bin/sh -e
+# Copy the *.dtbo's into the initramfs
+ 
+if [ "$1" = "prereqs" ]; then exit 0; fi
+ 
+. /usr/share/initramfs-tools/hook-functions
+ 
+if [ -d /lib/firmware/ ] ; then
+    unset check
+    check=$(ls /lib/firmware/ | grep dtbo | head -n 1)
+    if [ ! "x${check}" = "x" ] ; then
+        mkdir -p $DESTDIR/lib/firmware/
+        cp -a /lib/firmware/*.dtbo $DESTDIR/lib/firmware/
+    fi
+fi
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/tools/mainline-dtc-testing.sh b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/tools/mainline-dtc-testing.sh
new file mode 100644
index 0000000000000000000000000000000000000000..0cb07f8fa81f78abdc771e8ff17c1a78d5964f24
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/tools/mainline-dtc-testing.sh
@@ -0,0 +1,48 @@
+#!/bin/sh -e
+
+check_dpkg () {
+	LC_ALL=C dpkg --list | awk '{print $2}' | grep "^${pkg}" >/dev/null || deb_pkgs="${deb_pkgs}${pkg} "
+}
+
+unset deb_pkgs
+pkg="bison"
+check_dpkg
+pkg="build-essential"
+check_dpkg
+pkg="flex"
+check_dpkg
+pkg="git-core"
+check_dpkg
+
+if [ "${deb_pkgs}" ] ; then
+	echo "Installing: ${deb_pkgs}"
+	sudo apt-get update
+	sudo apt-get -y install ${deb_pkgs}
+	sudo apt-get clean
+fi
+
+git_sha="origin/master"
+project="dtc"
+server="https://git.kernel.org/pub/scm/utils/dtc"
+
+if [ ! -f ${HOME}/git/${project}/.git/config ] ; then
+	git clone ${server}/${project}.git ${HOME}/git/${project}/
+fi
+
+if [ ! -f ${HOME}/git/${project}/.git/config ] ; then
+	rm -rf ${HOME}/git/${project}/ || true
+	echo "error: git failure, try re-runing"
+	exit
+fi
+
+cd ${HOME}/git/${project}/
+make clean
+git checkout master -f
+git pull || true
+
+make clean
+make PREFIX=/usr/local/ CC=gcc CROSS_COMPILE= all
+echo "Installing into: /usr/local/bin/"
+sudo make PREFIX=/usr/local/ install
+sudo ln -sf /usr/local/bin/dtc /usr/bin/dtc-v1.4.2-git
+echo "dtc: `/usr/bin/dtc-v1.4.2-git --version`"
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/tools/pinmux-generator/.gitignore b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/tools/pinmux-generator/.gitignore
new file mode 100644
index 0000000000000000000000000000000000000000..a00dc02217504ce687a34f2a5b15f78890609793
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/tools/pinmux-generator/.gitignore
@@ -0,0 +1 @@
+AM335x.json
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/tools/pinmux-generator/BeagleBone_Black.dts b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/tools/pinmux-generator/BeagleBone_Black.dts
new file mode 100644
index 0000000000000000000000000000000000000000..0ef6e7a524a5c6c2df998f106bc30b61d3ec9e73
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/tools/pinmux-generator/BeagleBone_Black.dts
@@ -0,0 +1,2712 @@
+
+/************************/
+/* P8 Header */
+/************************/
+
+/* P8_01                GND */
+
+/* P8_02                GND */
+
+
+/* P8_03 (ZCZ ball R9) emmc */
+P8_03_default_pin: pinmux_P8_03_default_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0818, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* gpmc_ad6.gpio1_6 */
+P8_03_gpio_pin: pinmux_P8_03_gpio_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0818, PIN_OUTPUT | INPUT_EN | MUX_MODE7) >; };		/* gpmc_ad6.gpio1_6 */
+P8_03_gpio_pu_pin: pinmux_P8_03_gpio_pu_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0818, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };	/* gpmc_ad6.gpio1_6 */
+P8_03_gpio_pd_pin: pinmux_P8_03_gpio_pd_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0818, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* gpmc_ad6.gpio1_6 */
+P8_03_gpio_input_pin: pinmux_P8_03_gpio_input_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0818, PIN_INPUT | MUX_MODE7) >; };			/* gpmc_ad6.gpio1_6 */
+
+/* P8_04 (ZCZ ball T9) emmc */
+P8_04_default_pin: pinmux_P8_04_default_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x081c, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* gpmc_ad7.gpio1_7 */
+P8_04_gpio_pin: pinmux_P8_04_gpio_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x081c, PIN_OUTPUT | INPUT_EN | MUX_MODE7) >; };		/* gpmc_ad7.gpio1_7 */
+P8_04_gpio_pu_pin: pinmux_P8_04_gpio_pu_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x081c, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };	/* gpmc_ad7.gpio1_7 */
+P8_04_gpio_pd_pin: pinmux_P8_04_gpio_pd_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x081c, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* gpmc_ad7.gpio1_7 */
+P8_04_gpio_input_pin: pinmux_P8_04_gpio_input_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x081c, PIN_INPUT | MUX_MODE7) >; };			/* gpmc_ad7.gpio1_7 */
+
+/* P8_05 (ZCZ ball R8) emmc */
+P8_05_default_pin: pinmux_P8_05_default_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0808, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* gpmc_ad2.gpio1_2 */
+P8_05_gpio_pin: pinmux_P8_05_gpio_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0808, PIN_OUTPUT | INPUT_EN | MUX_MODE7) >; };		/* gpmc_ad2.gpio1_2 */
+P8_05_gpio_pu_pin: pinmux_P8_05_gpio_pu_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0808, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };	/* gpmc_ad2.gpio1_2 */
+P8_05_gpio_pd_pin: pinmux_P8_05_gpio_pd_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0808, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* gpmc_ad2.gpio1_2 */
+P8_05_gpio_input_pin: pinmux_P8_05_gpio_input_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0808, PIN_INPUT | MUX_MODE7) >; };			/* gpmc_ad2.gpio1_2 */
+
+/* P8_06 (ZCZ ball T8) emmc */
+P8_06_default_pin: pinmux_P8_06_default_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x080c, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* gpmc_ad3.gpio1_3 */
+P8_06_gpio_pin: pinmux_P8_06_gpio_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x080c, PIN_OUTPUT | INPUT_EN | MUX_MODE7) >; };		/* gpmc_ad3.gpio1_3 */
+P8_06_gpio_pu_pin: pinmux_P8_06_gpio_pu_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x080c, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };	/* gpmc_ad3.gpio1_3 */
+P8_06_gpio_pd_pin: pinmux_P8_06_gpio_pd_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x080c, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* gpmc_ad3.gpio1_3 */
+P8_06_gpio_input_pin: pinmux_P8_06_gpio_input_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x080c, PIN_INPUT | MUX_MODE7) >; };			/* gpmc_ad3.gpio1_3 */
+
+/* P8_07 (ZCZ ball R7) gpio2_2 */
+P8_07_default_pin: pinmux_P8_07_default_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0890, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };	/* gpmc_advn_ale.gpio2_2 */
+P8_07_gpio_pin: pinmux_P8_07_gpio_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0890, PIN_OUTPUT | INPUT_EN | MUX_MODE7) >; };		/* gpmc_advn_ale.gpio2_2 */
+P8_07_gpio_pu_pin: pinmux_P8_07_gpio_pu_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0890, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };	/* gpmc_advn_ale.gpio2_2 */
+P8_07_gpio_pd_pin: pinmux_P8_07_gpio_pd_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0890, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* gpmc_advn_ale.gpio2_2 */
+P8_07_gpio_input_pin: pinmux_P8_07_gpio_input_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0890, PIN_INPUT | MUX_MODE7) >; };			/* gpmc_advn_ale.gpio2_2 */
+P8_07_timer_pin: pinmux_P8_07_timer_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0890, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE2) >; };	/* gpmc_advn_ale.timer4 */
+
+/* P8_08 (ZCZ ball T7) gpio2_3 */
+P8_08_default_pin: pinmux_P8_08_default_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0894, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };	/* gpmc_oen_ren.gpio2_3 */
+P8_08_gpio_pin: pinmux_P8_08_gpio_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0894, PIN_OUTPUT | INPUT_EN | MUX_MODE7) >; };		/* gpmc_oen_ren.gpio2_3 */
+P8_08_gpio_pu_pin: pinmux_P8_08_gpio_pu_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0894, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };	/* gpmc_oen_ren.gpio2_3 */
+P8_08_gpio_pd_pin: pinmux_P8_08_gpio_pd_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0894, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* gpmc_oen_ren.gpio2_3 */
+P8_08_gpio_input_pin: pinmux_P8_08_gpio_input_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0894, PIN_INPUT | MUX_MODE7) >; };			/* gpmc_oen_ren.gpio2_3 */
+P8_08_timer_pin: pinmux_P8_08_timer_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0894, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE2) >; };	/* gpmc_oen_ren.timer7 */
+
+/* P8_09 (ZCZ ball T6) gpio2_5 */
+P8_09_default_pin: pinmux_P8_09_default_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x089c, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };	/* gpmc_be0n_cle.gpio2_5 */
+P8_09_gpio_pin: pinmux_P8_09_gpio_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x089c, PIN_OUTPUT | INPUT_EN | MUX_MODE7) >; };		/* gpmc_be0n_cle.gpio2_5 */
+P8_09_gpio_pu_pin: pinmux_P8_09_gpio_pu_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x089c, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };	/* gpmc_be0n_cle.gpio2_5 */
+P8_09_gpio_pd_pin: pinmux_P8_09_gpio_pd_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x089c, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* gpmc_be0n_cle.gpio2_5 */
+P8_09_gpio_input_pin: pinmux_P8_09_gpio_input_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x089c, PIN_INPUT | MUX_MODE7) >; };			/* gpmc_be0n_cle.gpio2_5 */
+P8_09_timer_pin: pinmux_P8_09_timer_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x089c, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE2) >; };	/* gpmc_be0n_cle.timer5 */
+
+/* P8_10 (ZCZ ball U6) gpio2_4 */
+P8_10_default_pin: pinmux_P8_10_default_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0898, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };	/* gpmc_wen.gpio2_4 */
+P8_10_gpio_pin: pinmux_P8_10_gpio_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0898, PIN_OUTPUT | INPUT_EN | MUX_MODE7) >; };		/* gpmc_wen.gpio2_4 */
+P8_10_gpio_pu_pin: pinmux_P8_10_gpio_pu_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0898, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };	/* gpmc_wen.gpio2_4 */
+P8_10_gpio_pd_pin: pinmux_P8_10_gpio_pd_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0898, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* gpmc_wen.gpio2_4 */
+P8_10_gpio_input_pin: pinmux_P8_10_gpio_input_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0898, PIN_INPUT | MUX_MODE7) >; };			/* gpmc_wen.gpio2_4 */
+P8_10_timer_pin: pinmux_P8_10_timer_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0898, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE2) >; };	/* gpmc_wen.timer6 */
+
+/* P8_11 (ZCZ ball R12) gpio1_13 */
+P8_11_default_pin: pinmux_P8_11_default_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0834, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* gpmc_ad13.gpio1_13 */
+P8_11_gpio_pin: pinmux_P8_11_gpio_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0834, PIN_OUTPUT | INPUT_EN | MUX_MODE7) >; };		/* gpmc_ad13.gpio1_13 */
+P8_11_gpio_pu_pin: pinmux_P8_11_gpio_pu_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0834, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };	/* gpmc_ad13.gpio1_13 */
+P8_11_gpio_pd_pin: pinmux_P8_11_gpio_pd_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0834, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* gpmc_ad13.gpio1_13 */
+P8_11_gpio_input_pin: pinmux_P8_11_gpio_input_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0834, PIN_INPUT | MUX_MODE7) >; };			/* gpmc_ad13.gpio1_13 */
+P8_11_qep_pin: pinmux_P8_11_qep_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0834, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE4) >; };	/* gpmc_ad13.eqep2b_in */
+P8_11_pruout_pin: pinmux_P8_11_pruout_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0834, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE6) >; };	/* gpmc_ad13.pru0_out15 */
+
+/* P8_12 (ZCZ ball T12) gpio1_12 */
+P8_12_default_pin: pinmux_P8_12_default_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0830, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* gpmc_ad12.gpio1_12 */
+P8_12_gpio_pin: pinmux_P8_12_gpio_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0830, PIN_OUTPUT | INPUT_EN | MUX_MODE7) >; };		/* gpmc_ad12.gpio1_12 */
+P8_12_gpio_pu_pin: pinmux_P8_12_gpio_pu_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0830, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };	/* gpmc_ad12.gpio1_12 */
+P8_12_gpio_pd_pin: pinmux_P8_12_gpio_pd_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0830, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* gpmc_ad12.gpio1_12 */
+P8_12_gpio_input_pin: pinmux_P8_12_gpio_input_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0830, PIN_INPUT | MUX_MODE7) >; };			/* gpmc_ad12.gpio1_12 */
+P8_12_qep_pin: pinmux_P8_12_qep_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0830, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE4) >; };	/* gpmc_ad12.eqep2a_in */
+P8_12_pruout_pin: pinmux_P8_12_pruout_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0830, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE6) >; };	/* gpmc_ad12.pru0_out14 */
+
+/* P8_13 (ZCZ ball T10) gpio0_23 */
+P8_13_default_pin: pinmux_P8_13_default_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0824, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* gpmc_ad9.gpio0_23 */
+P8_13_gpio_pin: pinmux_P8_13_gpio_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0824, PIN_OUTPUT | INPUT_EN | MUX_MODE7) >; };		/* gpmc_ad9.gpio0_23 */
+P8_13_gpio_pu_pin: pinmux_P8_13_gpio_pu_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0824, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };	/* gpmc_ad9.gpio0_23 */
+P8_13_gpio_pd_pin: pinmux_P8_13_gpio_pd_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0824, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* gpmc_ad9.gpio0_23 */
+P8_13_gpio_input_pin: pinmux_P8_13_gpio_input_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0824, PIN_INPUT | MUX_MODE7) >; };			/* gpmc_ad9.gpio0_23 */
+P8_13_pwm_pin: pinmux_P8_13_pwm_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0824, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE4) >; };	/* gpmc_ad9.ehrpwm2b */
+
+/* P8_14 (ZCZ ball T11) gpio0_26 */
+P8_14_default_pin: pinmux_P8_14_default_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0828, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* gpmc_ad10.gpio0_26 */
+P8_14_gpio_pin: pinmux_P8_14_gpio_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0828, PIN_OUTPUT | INPUT_EN | MUX_MODE7) >; };		/* gpmc_ad10.gpio0_26 */
+P8_14_gpio_pu_pin: pinmux_P8_14_gpio_pu_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0828, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };	/* gpmc_ad10.gpio0_26 */
+P8_14_gpio_pd_pin: pinmux_P8_14_gpio_pd_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0828, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* gpmc_ad10.gpio0_26 */
+P8_14_gpio_input_pin: pinmux_P8_14_gpio_input_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0828, PIN_INPUT | MUX_MODE7) >; };			/* gpmc_ad10.gpio0_26 */
+P8_14_pwm_pin: pinmux_P8_14_pwm_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0828, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE4) >; };	/* gpmc_ad10.ehrpwm2_tripzone_input */
+
+/* P8_15 (ZCZ ball U13) gpio1_15 */
+P8_15_default_pin: pinmux_P8_15_default_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x083c, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* gpmc_ad15.gpio1_15 */
+P8_15_gpio_pin: pinmux_P8_15_gpio_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x083c, PIN_OUTPUT | INPUT_EN | MUX_MODE7) >; };		/* gpmc_ad15.gpio1_15 */
+P8_15_gpio_pu_pin: pinmux_P8_15_gpio_pu_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x083c, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };	/* gpmc_ad15.gpio1_15 */
+P8_15_gpio_pd_pin: pinmux_P8_15_gpio_pd_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x083c, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* gpmc_ad15.gpio1_15 */
+P8_15_gpio_input_pin: pinmux_P8_15_gpio_input_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x083c, PIN_INPUT | MUX_MODE7) >; };			/* gpmc_ad15.gpio1_15 */
+P8_15_qep_pin: pinmux_P8_15_qep_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x083c, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE4) >; };	/* gpmc_ad15.eqep2_strobe */
+P8_15_pru_ecap_pin: pinmux_P8_15_pru_ecap_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x083c, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE5) >; };	/* gpmc_ad15.pr1_ecap0_ecap_capin_apwm_o */
+P8_15_pruin_pin: pinmux_P8_15_pruin_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x083c, PIN_INPUT | MUX_MODE6) >; };			/* gpmc_ad15.pru0_in15 */
+
+/* P8_16 (ZCZ ball V13) gpio1_14 */
+P8_16_default_pin: pinmux_P8_16_default_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0838, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* gpmc_ad14.gpio1_14 */
+P8_16_gpio_pin: pinmux_P8_16_gpio_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0838, PIN_OUTPUT | INPUT_EN | MUX_MODE7) >; };		/* gpmc_ad14.gpio1_14 */
+P8_16_gpio_pu_pin: pinmux_P8_16_gpio_pu_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0838, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };	/* gpmc_ad14.gpio1_14 */
+P8_16_gpio_pd_pin: pinmux_P8_16_gpio_pd_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0838, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* gpmc_ad14.gpio1_14 */
+P8_16_gpio_input_pin: pinmux_P8_16_gpio_input_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0838, PIN_INPUT | MUX_MODE7) >; };			/* gpmc_ad14.gpio1_14 */
+P8_16_qep_pin: pinmux_P8_16_qep_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0838, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE4) >; };	/* gpmc_ad14.eqep2_index */
+P8_16_pruin_pin: pinmux_P8_16_pruin_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0838, PIN_INPUT | MUX_MODE6) >; };			/* gpmc_ad14.pru0_in14 */
+
+/* P8_17 (ZCZ ball U12) gpio0_27 */
+P8_17_default_pin: pinmux_P8_17_default_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x082c, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* gpmc_ad11.gpio0_27 */
+P8_17_gpio_pin: pinmux_P8_17_gpio_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x082c, PIN_OUTPUT | INPUT_EN | MUX_MODE7) >; };		/* gpmc_ad11.gpio0_27 */
+P8_17_gpio_pu_pin: pinmux_P8_17_gpio_pu_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x082c, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };	/* gpmc_ad11.gpio0_27 */
+P8_17_gpio_pd_pin: pinmux_P8_17_gpio_pd_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x082c, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* gpmc_ad11.gpio0_27 */
+P8_17_gpio_input_pin: pinmux_P8_17_gpio_input_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x082c, PIN_INPUT | MUX_MODE7) >; };			/* gpmc_ad11.gpio0_27 */
+P8_17_pwm_pin: pinmux_P8_17_pwm_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x082c, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE4) >; };	/* gpmc_ad11.ehrpwm0_synco */
+
+/* P8_18 (ZCZ ball V12) gpio2_1 */
+P8_18_default_pin: pinmux_P8_18_default_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x088c, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* gpmc_clk.gpio2_1 */
+P8_18_gpio_pin: pinmux_P8_18_gpio_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x088c, PIN_OUTPUT | INPUT_EN | MUX_MODE7) >; };		/* gpmc_clk.gpio2_1 */
+P8_18_gpio_pu_pin: pinmux_P8_18_gpio_pu_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x088c, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };	/* gpmc_clk.gpio2_1 */
+P8_18_gpio_pd_pin: pinmux_P8_18_gpio_pd_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x088c, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* gpmc_clk.gpio2_1 */
+P8_18_gpio_input_pin: pinmux_P8_18_gpio_input_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x088c, PIN_INPUT | MUX_MODE7) >; };			/* gpmc_clk.gpio2_1 */
+
+/* P8_19 (ZCZ ball U10) gpio0_22 */
+P8_19_default_pin: pinmux_P8_19_default_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0820, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* gpmc_ad8.gpio0_22 */
+P8_19_gpio_pin: pinmux_P8_19_gpio_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0820, PIN_OUTPUT | INPUT_EN | MUX_MODE7) >; };		/* gpmc_ad8.gpio0_22 */
+P8_19_gpio_pu_pin: pinmux_P8_19_gpio_pu_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0820, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };	/* gpmc_ad8.gpio0_22 */
+P8_19_gpio_pd_pin: pinmux_P8_19_gpio_pd_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0820, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* gpmc_ad8.gpio0_22 */
+P8_19_gpio_input_pin: pinmux_P8_19_gpio_input_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0820, PIN_INPUT | MUX_MODE7) >; };			/* gpmc_ad8.gpio0_22 */
+P8_19_pwm_pin: pinmux_P8_19_pwm_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0820, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE4) >; };	/* gpmc_ad8.ehrpwm2a */
+
+/* P8_20 (ZCZ ball V9) emmc */
+P8_20_default_pin: pinmux_P8_20_default_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0884, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* gpmc_csn2.gpio1_31 */
+P8_20_gpio_pin: pinmux_P8_20_gpio_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0884, PIN_OUTPUT | INPUT_EN | MUX_MODE7) >; };		/* gpmc_csn2.gpio1_31 */
+P8_20_gpio_pu_pin: pinmux_P8_20_gpio_pu_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0884, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };	/* gpmc_csn2.gpio1_31 */
+P8_20_gpio_pd_pin: pinmux_P8_20_gpio_pd_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0884, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* gpmc_csn2.gpio1_31 */
+P8_20_gpio_input_pin: pinmux_P8_20_gpio_input_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0884, PIN_INPUT | MUX_MODE7) >; };			/* gpmc_csn2.gpio1_31 */
+P8_20_pruout_pin: pinmux_P8_20_pruout_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0884, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE5) >; };	/* gpmc_csn2.pru1_out13 */
+P8_20_pruin_pin: pinmux_P8_20_pruin_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0884, PIN_INPUT | MUX_MODE6) >; };			/* gpmc_csn2.pru1_in13 */
+
+/* P8_21 (ZCZ ball U9) emmc */
+P8_21_default_pin: pinmux_P8_21_default_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0880, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* gpmc_csn1.gpio1_30 */
+P8_21_gpio_pin: pinmux_P8_21_gpio_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0880, PIN_OUTPUT | INPUT_EN | MUX_MODE7) >; };		/* gpmc_csn1.gpio1_30 */
+P8_21_gpio_pu_pin: pinmux_P8_21_gpio_pu_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0880, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };	/* gpmc_csn1.gpio1_30 */
+P8_21_gpio_pd_pin: pinmux_P8_21_gpio_pd_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0880, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* gpmc_csn1.gpio1_30 */
+P8_21_gpio_input_pin: pinmux_P8_21_gpio_input_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0880, PIN_INPUT | MUX_MODE7) >; };			/* gpmc_csn1.gpio1_30 */
+P8_21_pruout_pin: pinmux_P8_21_pruout_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0880, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE5) >; };	/* gpmc_csn1.pru1_out12 */
+P8_21_pruin_pin: pinmux_P8_21_pruin_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0880, PIN_INPUT | MUX_MODE6) >; };			/* gpmc_csn1.pru1_in12 */
+
+/* P8_22 (ZCZ ball V8) emmc */
+P8_22_default_pin: pinmux_P8_22_default_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0814, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* gpmc_ad5.gpio1_5 */
+P8_22_gpio_pin: pinmux_P8_22_gpio_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0814, PIN_OUTPUT | INPUT_EN | MUX_MODE7) >; };		/* gpmc_ad5.gpio1_5 */
+P8_22_gpio_pu_pin: pinmux_P8_22_gpio_pu_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0814, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };	/* gpmc_ad5.gpio1_5 */
+P8_22_gpio_pd_pin: pinmux_P8_22_gpio_pd_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0814, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* gpmc_ad5.gpio1_5 */
+P8_22_gpio_input_pin: pinmux_P8_22_gpio_input_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0814, PIN_INPUT | MUX_MODE7) >; };			/* gpmc_ad5.gpio1_5 */
+
+/* P8_23 (ZCZ ball U8) emmc */
+P8_23_default_pin: pinmux_P8_23_default_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0810, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* gpmc_ad4.gpio1_4 */
+P8_23_gpio_pin: pinmux_P8_23_gpio_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0810, PIN_OUTPUT | INPUT_EN | MUX_MODE7) >; };		/* gpmc_ad4.gpio1_4 */
+P8_23_gpio_pu_pin: pinmux_P8_23_gpio_pu_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0810, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };	/* gpmc_ad4.gpio1_4 */
+P8_23_gpio_pd_pin: pinmux_P8_23_gpio_pd_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0810, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* gpmc_ad4.gpio1_4 */
+P8_23_gpio_input_pin: pinmux_P8_23_gpio_input_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0810, PIN_INPUT | MUX_MODE7) >; };			/* gpmc_ad4.gpio1_4 */
+
+/* P8_24 (ZCZ ball V7) emmc */
+P8_24_default_pin: pinmux_P8_24_default_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0804, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* gpmc_ad1.gpio1_1 */
+P8_24_gpio_pin: pinmux_P8_24_gpio_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0804, PIN_OUTPUT | INPUT_EN | MUX_MODE7) >; };		/* gpmc_ad1.gpio1_1 */
+P8_24_gpio_pu_pin: pinmux_P8_24_gpio_pu_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0804, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };	/* gpmc_ad1.gpio1_1 */
+P8_24_gpio_pd_pin: pinmux_P8_24_gpio_pd_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0804, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* gpmc_ad1.gpio1_1 */
+P8_24_gpio_input_pin: pinmux_P8_24_gpio_input_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0804, PIN_INPUT | MUX_MODE7) >; };			/* gpmc_ad1.gpio1_1 */
+
+/* P8_25 (ZCZ ball U7) emmc */
+P8_25_default_pin: pinmux_P8_25_default_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0800, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* gpmc_ad0.gpio1_0 */
+P8_25_gpio_pin: pinmux_P8_25_gpio_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0800, PIN_OUTPUT | INPUT_EN | MUX_MODE7) >; };		/* gpmc_ad0.gpio1_0 */
+P8_25_gpio_pu_pin: pinmux_P8_25_gpio_pu_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0800, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };	/* gpmc_ad0.gpio1_0 */
+P8_25_gpio_pd_pin: pinmux_P8_25_gpio_pd_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0800, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* gpmc_ad0.gpio1_0 */
+P8_25_gpio_input_pin: pinmux_P8_25_gpio_input_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0800, PIN_INPUT | MUX_MODE7) >; };			/* gpmc_ad0.gpio1_0 */
+
+/* P8_26 (ZCZ ball V6) gpio1_29 */
+P8_26_default_pin: pinmux_P8_26_default_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x087c, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };	/* gpmc_csn0.gpio1_29 */
+P8_26_gpio_pin: pinmux_P8_26_gpio_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x087c, PIN_OUTPUT | INPUT_EN | MUX_MODE7) >; };		/* gpmc_csn0.gpio1_29 */
+P8_26_gpio_pu_pin: pinmux_P8_26_gpio_pu_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x087c, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };	/* gpmc_csn0.gpio1_29 */
+P8_26_gpio_pd_pin: pinmux_P8_26_gpio_pd_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x087c, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* gpmc_csn0.gpio1_29 */
+P8_26_gpio_input_pin: pinmux_P8_26_gpio_input_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x087c, PIN_INPUT | MUX_MODE7) >; };			/* gpmc_csn0.gpio1_29 */
+
+/* P8_27 (ZCZ ball U5) hdmi */
+P8_27_default_pin: pinmux_P8_27_default_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08e0, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* lcd_vsync.gpio2_22 */
+P8_27_gpio_pin: pinmux_P8_27_gpio_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08e0, PIN_OUTPUT | INPUT_EN | MUX_MODE7) >; };		/* lcd_vsync.gpio2_22 */
+P8_27_gpio_pu_pin: pinmux_P8_27_gpio_pu_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08e0, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };	/* lcd_vsync.gpio2_22 */
+P8_27_gpio_pd_pin: pinmux_P8_27_gpio_pd_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08e0, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* lcd_vsync.gpio2_22 */
+P8_27_gpio_input_pin: pinmux_P8_27_gpio_input_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08e0, PIN_INPUT | MUX_MODE7) >; };			/* lcd_vsync.gpio2_22 */
+P8_27_pruout_pin: pinmux_P8_27_pruout_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08e0, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE5) >; };	/* lcd_vsync.pru1_out8 */
+P8_27_pruin_pin: pinmux_P8_27_pruin_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08e0, PIN_INPUT | MUX_MODE6) >; };			/* lcd_vsync.pru1_in8 */
+
+/* P8_28 (ZCZ ball V5) hdmi */
+P8_28_default_pin: pinmux_P8_28_default_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08e8, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* lcd_pclk.gpio2_24 */
+P8_28_gpio_pin: pinmux_P8_28_gpio_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08e8, PIN_OUTPUT | INPUT_EN | MUX_MODE7) >; };		/* lcd_pclk.gpio2_24 */
+P8_28_gpio_pu_pin: pinmux_P8_28_gpio_pu_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08e8, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };	/* lcd_pclk.gpio2_24 */
+P8_28_gpio_pd_pin: pinmux_P8_28_gpio_pd_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08e8, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* lcd_pclk.gpio2_24 */
+P8_28_gpio_input_pin: pinmux_P8_28_gpio_input_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08e8, PIN_INPUT | MUX_MODE7) >; };			/* lcd_pclk.gpio2_24 */
+P8_28_pruout_pin: pinmux_P8_28_pruout_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08e8, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE5) >; };	/* lcd_pclk.pru1_out10 */
+P8_28_pruin_pin: pinmux_P8_28_pruin_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08e8, PIN_INPUT | MUX_MODE6) >; };			/* lcd_pclk.pru1_in10 */
+
+/* P8_29 (ZCZ ball R5) hdmi */
+P8_29_default_pin: pinmux_P8_29_default_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08e4, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* lcd_hsync.gpio2_23 */
+P8_29_gpio_pin: pinmux_P8_29_gpio_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08e4, PIN_OUTPUT | INPUT_EN | MUX_MODE7) >; };		/* lcd_hsync.gpio2_23 */
+P8_29_gpio_pu_pin: pinmux_P8_29_gpio_pu_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08e4, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };	/* lcd_hsync.gpio2_23 */
+P8_29_gpio_pd_pin: pinmux_P8_29_gpio_pd_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08e4, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* lcd_hsync.gpio2_23 */
+P8_29_gpio_input_pin: pinmux_P8_29_gpio_input_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08e4, PIN_INPUT | MUX_MODE7) >; };			/* lcd_hsync.gpio2_23 */
+P8_29_pruout_pin: pinmux_P8_29_pruout_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08e4, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE5) >; };	/* lcd_hsync.pru1_out9 */
+P8_29_pruin_pin: pinmux_P8_29_pruin_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08e4, PIN_INPUT | MUX_MODE6) >; };			/* lcd_hsync.pru1_in9 */
+
+/* P8_30 (ZCZ ball R6) hdmi */
+P8_30_default_pin: pinmux_P8_30_default_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08ec, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* lcd_ac_bias_en.gpio2_25 */
+P8_30_gpio_pin: pinmux_P8_30_gpio_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08ec, PIN_OUTPUT | INPUT_EN | MUX_MODE7) >; };		/* lcd_ac_bias_en.gpio2_25 */
+P8_30_gpio_pu_pin: pinmux_P8_30_gpio_pu_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08ec, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };	/* lcd_ac_bias_en.gpio2_25 */
+P8_30_gpio_pd_pin: pinmux_P8_30_gpio_pd_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08ec, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* lcd_ac_bias_en.gpio2_25 */
+P8_30_gpio_input_pin: pinmux_P8_30_gpio_input_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08ec, PIN_INPUT | MUX_MODE7) >; };			/* lcd_ac_bias_en.gpio2_25 */
+P8_30_pruout_pin: pinmux_P8_30_pruout_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08ec, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE5) >; };	/* lcd_ac_bias_en.pru1_out11 */
+P8_30_pruin_pin: pinmux_P8_30_pruin_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08ec, PIN_INPUT | MUX_MODE6) >; };			/* lcd_ac_bias_en.pru1_in11 */
+
+/* P8_31 (ZCZ ball V4) hdmi */
+P8_31_default_pin: pinmux_P8_31_default_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08d8, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* lcd_data14.gpio0_10 */
+P8_31_gpio_pin: pinmux_P8_31_gpio_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08d8, PIN_OUTPUT | INPUT_EN | MUX_MODE7) >; };		/* lcd_data14.gpio0_10 */
+P8_31_gpio_pu_pin: pinmux_P8_31_gpio_pu_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08d8, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };	/* lcd_data14.gpio0_10 */
+P8_31_gpio_pd_pin: pinmux_P8_31_gpio_pd_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08d8, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* lcd_data14.gpio0_10 */
+P8_31_gpio_input_pin: pinmux_P8_31_gpio_input_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08d8, PIN_INPUT | MUX_MODE7) >; };			/* lcd_data14.gpio0_10 */
+P8_31_qep_pin: pinmux_P8_31_qep_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08d8, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE2) >; };	/* lcd_data14.eqep1_index */
+P8_31_uart_pin: pinmux_P8_31_uart_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08d8, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE4) >; };	/* lcd_data14.uart5_rxd */
+
+/* P8_32 (ZCZ ball T5) hdmi */
+P8_32_default_pin: pinmux_P8_32_default_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08dc, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* lcd_data15.gpio0_11 */
+P8_32_gpio_pin: pinmux_P8_32_gpio_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08dc, PIN_OUTPUT | INPUT_EN | MUX_MODE7) >; };		/* lcd_data15.gpio0_11 */
+P8_32_gpio_pu_pin: pinmux_P8_32_gpio_pu_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08dc, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };	/* lcd_data15.gpio0_11 */
+P8_32_gpio_pd_pin: pinmux_P8_32_gpio_pd_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08dc, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* lcd_data15.gpio0_11 */
+P8_32_gpio_input_pin: pinmux_P8_32_gpio_input_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08dc, PIN_INPUT | MUX_MODE7) >; };			/* lcd_data15.gpio0_11 */
+P8_32_qep_pin: pinmux_P8_32_qep_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08dc, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE2) >; };	/* lcd_data15.eqep1_strobe */
+
+/* P8_33 (ZCZ ball V3) hdmi */
+P8_33_default_pin: pinmux_P8_33_default_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08d4, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* lcd_data13.gpio0_9 */
+P8_33_gpio_pin: pinmux_P8_33_gpio_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08d4, PIN_OUTPUT | INPUT_EN | MUX_MODE7) >; };		/* lcd_data13.gpio0_9 */
+P8_33_gpio_pu_pin: pinmux_P8_33_gpio_pu_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08d4, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };	/* lcd_data13.gpio0_9 */
+P8_33_gpio_pd_pin: pinmux_P8_33_gpio_pd_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08d4, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* lcd_data13.gpio0_9 */
+P8_33_gpio_input_pin: pinmux_P8_33_gpio_input_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08d4, PIN_INPUT | MUX_MODE7) >; };			/* lcd_data13.gpio0_9 */
+P8_33_qep_pin: pinmux_P8_33_qep_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08d4, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE2) >; };	/* lcd_data13.eqep1b_in */
+
+/* P8_34 (ZCZ ball U4) hdmi */
+P8_34_default_pin: pinmux_P8_34_default_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08cc, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* lcd_data11.gpio2_17 */
+P8_34_gpio_pin: pinmux_P8_34_gpio_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08cc, PIN_OUTPUT | INPUT_EN | MUX_MODE7) >; };		/* lcd_data11.gpio2_17 */
+P8_34_gpio_pu_pin: pinmux_P8_34_gpio_pu_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08cc, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };	/* lcd_data11.gpio2_17 */
+P8_34_gpio_pd_pin: pinmux_P8_34_gpio_pd_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08cc, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* lcd_data11.gpio2_17 */
+P8_34_gpio_input_pin: pinmux_P8_34_gpio_input_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08cc, PIN_INPUT | MUX_MODE7) >; };			/* lcd_data11.gpio2_17 */
+P8_34_pwm_pin: pinmux_P8_34_pwm_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08cc, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE2) >; };	/* lcd_data11.ehrpwm1b */
+
+/* P8_35 (ZCZ ball V2) hdmi */
+P8_35_default_pin: pinmux_P8_35_default_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08d0, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* lcd_data12.gpio0_8 */
+P8_35_gpio_pin: pinmux_P8_35_gpio_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08d0, PIN_OUTPUT | INPUT_EN | MUX_MODE7) >; };		/* lcd_data12.gpio0_8 */
+P8_35_gpio_pu_pin: pinmux_P8_35_gpio_pu_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08d0, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };	/* lcd_data12.gpio0_8 */
+P8_35_gpio_pd_pin: pinmux_P8_35_gpio_pd_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08d0, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* lcd_data12.gpio0_8 */
+P8_35_gpio_input_pin: pinmux_P8_35_gpio_input_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08d0, PIN_INPUT | MUX_MODE7) >; };			/* lcd_data12.gpio0_8 */
+P8_35_qep_pin: pinmux_P8_35_qep_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08d0, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE2) >; };	/* lcd_data12.eqep1a_in */
+
+/* P8_36 (ZCZ ball U3) hdmi */
+P8_36_default_pin: pinmux_P8_36_default_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08c8, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* lcd_data10.gpio2_16 */
+P8_36_gpio_pin: pinmux_P8_36_gpio_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08c8, PIN_OUTPUT | INPUT_EN | MUX_MODE7) >; };		/* lcd_data10.gpio2_16 */
+P8_36_gpio_pu_pin: pinmux_P8_36_gpio_pu_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08c8, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };	/* lcd_data10.gpio2_16 */
+P8_36_gpio_pd_pin: pinmux_P8_36_gpio_pd_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08c8, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* lcd_data10.gpio2_16 */
+P8_36_gpio_input_pin: pinmux_P8_36_gpio_input_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08c8, PIN_INPUT | MUX_MODE7) >; };			/* lcd_data10.gpio2_16 */
+P8_36_pwm_pin: pinmux_P8_36_pwm_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08c8, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE2) >; };	/* lcd_data10.ehrpwm1a */
+
+/* P8_37 (ZCZ ball U1) hdmi */
+P8_37_default_pin: pinmux_P8_37_default_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08c0, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* lcd_data8.gpio2_14 */
+P8_37_gpio_pin: pinmux_P8_37_gpio_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08c0, PIN_OUTPUT | INPUT_EN | MUX_MODE7) >; };		/* lcd_data8.gpio2_14 */
+P8_37_gpio_pu_pin: pinmux_P8_37_gpio_pu_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08c0, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };	/* lcd_data8.gpio2_14 */
+P8_37_gpio_pd_pin: pinmux_P8_37_gpio_pd_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08c0, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* lcd_data8.gpio2_14 */
+P8_37_gpio_input_pin: pinmux_P8_37_gpio_input_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08c0, PIN_INPUT | MUX_MODE7) >; };			/* lcd_data8.gpio2_14 */
+P8_37_pwm_pin: pinmux_P8_37_pwm_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08c0, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE2) >; };	/* lcd_data8.ehrpwm1_tripzone_input */
+P8_37_uart_pin: pinmux_P8_37_uart_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08c0, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE4) >; };	/* lcd_data8.uart5_txd */
+
+/* P8_38 (ZCZ ball U2) hdmi */
+P8_38_default_pin: pinmux_P8_38_default_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08c4, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* lcd_data9.gpio2_15 */
+P8_38_gpio_pin: pinmux_P8_38_gpio_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08c4, PIN_OUTPUT | INPUT_EN | MUX_MODE7) >; };		/* lcd_data9.gpio2_15 */
+P8_38_gpio_pu_pin: pinmux_P8_38_gpio_pu_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08c4, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };	/* lcd_data9.gpio2_15 */
+P8_38_gpio_pd_pin: pinmux_P8_38_gpio_pd_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08c4, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* lcd_data9.gpio2_15 */
+P8_38_gpio_input_pin: pinmux_P8_38_gpio_input_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08c4, PIN_INPUT | MUX_MODE7) >; };			/* lcd_data9.gpio2_15 */
+P8_38_pwm_pin: pinmux_P8_38_pwm_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08c4, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE2) >; };	/* lcd_data9.ehrpwm0_synco */
+P8_38_uart_pin: pinmux_P8_38_uart_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08c4, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE4) >; };	/* lcd_data9.uart5_rxd */
+
+/* P8_39 (ZCZ ball T3) hdmi */
+P8_39_default_pin: pinmux_P8_39_default_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08b8, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* lcd_data6.gpio2_12 */
+P8_39_gpio_pin: pinmux_P8_39_gpio_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08b8, PIN_OUTPUT | INPUT_EN | MUX_MODE7) >; };		/* lcd_data6.gpio2_12 */
+P8_39_gpio_pu_pin: pinmux_P8_39_gpio_pu_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08b8, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };	/* lcd_data6.gpio2_12 */
+P8_39_gpio_pd_pin: pinmux_P8_39_gpio_pd_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08b8, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* lcd_data6.gpio2_12 */
+P8_39_gpio_input_pin: pinmux_P8_39_gpio_input_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08b8, PIN_INPUT | MUX_MODE7) >; };			/* lcd_data6.gpio2_12 */
+P8_39_qep_pin: pinmux_P8_39_qep_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08b8, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE3) >; };	/* lcd_data6.eqep2_index */
+P8_39_pruout_pin: pinmux_P8_39_pruout_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08b8, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE5) >; };	/* lcd_data6.pru1_out6 */
+P8_39_pruin_pin: pinmux_P8_39_pruin_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08b8, PIN_INPUT | MUX_MODE6) >; };			/* lcd_data6.pru1_in6 */
+
+/* P8_40 (ZCZ ball T4) hdmi */
+P8_40_default_pin: pinmux_P8_40_default_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08bc, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* lcd_data7.gpio2_13 */
+P8_40_gpio_pin: pinmux_P8_40_gpio_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08bc, PIN_OUTPUT | INPUT_EN | MUX_MODE7) >; };		/* lcd_data7.gpio2_13 */
+P8_40_gpio_pu_pin: pinmux_P8_40_gpio_pu_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08bc, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };	/* lcd_data7.gpio2_13 */
+P8_40_gpio_pd_pin: pinmux_P8_40_gpio_pd_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08bc, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* lcd_data7.gpio2_13 */
+P8_40_gpio_input_pin: pinmux_P8_40_gpio_input_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08bc, PIN_INPUT | MUX_MODE7) >; };			/* lcd_data7.gpio2_13 */
+P8_40_qep_pin: pinmux_P8_40_qep_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08bc, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE3) >; };	/* lcd_data7.eqep2_strobe */
+P8_40_pruout_pin: pinmux_P8_40_pruout_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08bc, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE5) >; };	/* lcd_data7.pru1_out7 */
+P8_40_pruin_pin: pinmux_P8_40_pruin_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08bc, PIN_INPUT | MUX_MODE6) >; };			/* lcd_data7.pru1_in7 */
+
+/* P8_41 (ZCZ ball T1) hdmi */
+P8_41_default_pin: pinmux_P8_41_default_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08b0, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* lcd_data4.gpio2_10 */
+P8_41_gpio_pin: pinmux_P8_41_gpio_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08b0, PIN_OUTPUT | INPUT_EN | MUX_MODE7) >; };		/* lcd_data4.gpio2_10 */
+P8_41_gpio_pu_pin: pinmux_P8_41_gpio_pu_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08b0, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };	/* lcd_data4.gpio2_10 */
+P8_41_gpio_pd_pin: pinmux_P8_41_gpio_pd_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08b0, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* lcd_data4.gpio2_10 */
+P8_41_gpio_input_pin: pinmux_P8_41_gpio_input_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08b0, PIN_INPUT | MUX_MODE7) >; };			/* lcd_data4.gpio2_10 */
+P8_41_qep_pin: pinmux_P8_41_qep_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08b0, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE3) >; };	/* lcd_data4.eqep2a_in */
+P8_41_pruout_pin: pinmux_P8_41_pruout_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08b0, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE5) >; };	/* lcd_data4.pru1_out4 */
+P8_41_pruin_pin: pinmux_P8_41_pruin_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08b0, PIN_INPUT | MUX_MODE6) >; };			/* lcd_data4.pru1_in4 */
+
+/* P8_42 (ZCZ ball T2) hdmi */
+P8_42_default_pin: pinmux_P8_42_default_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08b4, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* lcd_data5.gpio2_11 */
+P8_42_gpio_pin: pinmux_P8_42_gpio_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08b4, PIN_OUTPUT | INPUT_EN | MUX_MODE7) >; };		/* lcd_data5.gpio2_11 */
+P8_42_gpio_pu_pin: pinmux_P8_42_gpio_pu_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08b4, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };	/* lcd_data5.gpio2_11 */
+P8_42_gpio_pd_pin: pinmux_P8_42_gpio_pd_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08b4, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* lcd_data5.gpio2_11 */
+P8_42_gpio_input_pin: pinmux_P8_42_gpio_input_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08b4, PIN_INPUT | MUX_MODE7) >; };			/* lcd_data5.gpio2_11 */
+P8_42_qep_pin: pinmux_P8_42_qep_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08b4, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE3) >; };	/* lcd_data5.eqep2b_in */
+P8_42_pruout_pin: pinmux_P8_42_pruout_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08b4, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE5) >; };	/* lcd_data5.pru1_out5 */
+P8_42_pruin_pin: pinmux_P8_42_pruin_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08b4, PIN_INPUT | MUX_MODE6) >; };			/* lcd_data5.pru1_in5 */
+
+/* P8_43 (ZCZ ball R3) hdmi */
+P8_43_default_pin: pinmux_P8_43_default_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08a8, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* lcd_data2.gpio2_8 */
+P8_43_gpio_pin: pinmux_P8_43_gpio_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08a8, PIN_OUTPUT | INPUT_EN | MUX_MODE7) >; };		/* lcd_data2.gpio2_8 */
+P8_43_gpio_pu_pin: pinmux_P8_43_gpio_pu_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08a8, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };	/* lcd_data2.gpio2_8 */
+P8_43_gpio_pd_pin: pinmux_P8_43_gpio_pd_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08a8, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* lcd_data2.gpio2_8 */
+P8_43_gpio_input_pin: pinmux_P8_43_gpio_input_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08a8, PIN_INPUT | MUX_MODE7) >; };			/* lcd_data2.gpio2_8 */
+P8_43_pwm_pin: pinmux_P8_43_pwm_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08a8, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE3) >; };	/* lcd_data2.ehrpwm2_tripzone_input */
+P8_43_pruout_pin: pinmux_P8_43_pruout_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08a8, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE5) >; };	/* lcd_data2.pru1_out2 */
+P8_43_pruin_pin: pinmux_P8_43_pruin_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08a8, PIN_INPUT | MUX_MODE6) >; };			/* lcd_data2.pru1_in2 */
+
+/* P8_44 (ZCZ ball R4) hdmi */
+P8_44_default_pin: pinmux_P8_44_default_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08ac, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* lcd_data3.gpio2_9 */
+P8_44_gpio_pin: pinmux_P8_44_gpio_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08ac, PIN_OUTPUT | INPUT_EN | MUX_MODE7) >; };		/* lcd_data3.gpio2_9 */
+P8_44_gpio_pu_pin: pinmux_P8_44_gpio_pu_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08ac, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };	/* lcd_data3.gpio2_9 */
+P8_44_gpio_pd_pin: pinmux_P8_44_gpio_pd_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08ac, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* lcd_data3.gpio2_9 */
+P8_44_gpio_input_pin: pinmux_P8_44_gpio_input_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08ac, PIN_INPUT | MUX_MODE7) >; };			/* lcd_data3.gpio2_9 */
+P8_44_pwm_pin: pinmux_P8_44_pwm_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08ac, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE3) >; };	/* lcd_data3.ehrpwm0_synco */
+P8_44_pruout_pin: pinmux_P8_44_pruout_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08ac, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE5) >; };	/* lcd_data3.pru1_out3 */
+P8_44_pruin_pin: pinmux_P8_44_pruin_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08ac, PIN_INPUT | MUX_MODE6) >; };			/* lcd_data3.pru1_in3 */
+
+/* P8_45 (ZCZ ball R1) hdmi */
+P8_45_default_pin: pinmux_P8_45_default_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08a0, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* lcd_data0.gpio2_6 */
+P8_45_gpio_pin: pinmux_P8_45_gpio_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08a0, PIN_OUTPUT | INPUT_EN | MUX_MODE7) >; };		/* lcd_data0.gpio2_6 */
+P8_45_gpio_pu_pin: pinmux_P8_45_gpio_pu_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08a0, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };	/* lcd_data0.gpio2_6 */
+P8_45_gpio_pd_pin: pinmux_P8_45_gpio_pd_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08a0, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* lcd_data0.gpio2_6 */
+P8_45_gpio_input_pin: pinmux_P8_45_gpio_input_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08a0, PIN_INPUT | MUX_MODE7) >; };			/* lcd_data0.gpio2_6 */
+P8_45_pwm_pin: pinmux_P8_45_pwm_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08a0, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE3) >; };	/* lcd_data0.ehrpwm2a */
+P8_45_pruout_pin: pinmux_P8_45_pruout_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08a0, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE5) >; };	/* lcd_data0.pru1_out0 */
+P8_45_pruin_pin: pinmux_P8_45_pruin_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08a0, PIN_INPUT | MUX_MODE6) >; };			/* lcd_data0.pru1_in0 */
+
+/* P8_46 (ZCZ ball R2) hdmi */
+P8_46_default_pin: pinmux_P8_46_default_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08a4, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* lcd_data1.gpio2_7 */
+P8_46_gpio_pin: pinmux_P8_46_gpio_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08a4, PIN_OUTPUT | INPUT_EN | MUX_MODE7) >; };		/* lcd_data1.gpio2_7 */
+P8_46_gpio_pu_pin: pinmux_P8_46_gpio_pu_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08a4, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };	/* lcd_data1.gpio2_7 */
+P8_46_gpio_pd_pin: pinmux_P8_46_gpio_pd_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08a4, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* lcd_data1.gpio2_7 */
+P8_46_gpio_input_pin: pinmux_P8_46_gpio_input_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08a4, PIN_INPUT | MUX_MODE7) >; };			/* lcd_data1.gpio2_7 */
+P8_46_pwm_pin: pinmux_P8_46_pwm_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08a4, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE3) >; };	/* lcd_data1.ehrpwm2b */
+P8_46_pruout_pin: pinmux_P8_46_pruout_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08a4, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE5) >; };	/* lcd_data1.pru1_out1 */
+P8_46_pruin_pin: pinmux_P8_46_pruin_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08a4, PIN_INPUT | MUX_MODE6) >; };			/* lcd_data1.pru1_in1 */
+
+/************************/
+/* P9 Header */
+/************************/
+
+/* P9_01                GND */
+
+/* P9_02                GND */
+
+/* P9_03                3V3 */
+
+/* P9_04                3V3 */
+
+/* P9_05                VDD_5V */
+
+/* P9_06                VDD_5V */
+
+/* P9_07                SYS_5V */
+
+/* P9_08                SYS_5V */
+
+/* P9_09                PWR_BUT */
+
+/* P9_10                RSTn */
+
+/* P9_11 (ZCZ ball T17) gpio0_30 */
+P9_11_default_pin: pinmux_P9_11_default_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0870, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };	/* gpmc_wait0.gpio0_30 */
+P9_11_gpio_pin: pinmux_P9_11_gpio_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0870, PIN_OUTPUT | INPUT_EN | MUX_MODE7) >; };		/* gpmc_wait0.gpio0_30 */
+P9_11_gpio_pu_pin: pinmux_P9_11_gpio_pu_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0870, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };	/* gpmc_wait0.gpio0_30 */
+P9_11_gpio_pd_pin: pinmux_P9_11_gpio_pd_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0870, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* gpmc_wait0.gpio0_30 */
+P9_11_gpio_input_pin: pinmux_P9_11_gpio_input_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0870, PIN_INPUT | MUX_MODE7) >; };			/* gpmc_wait0.gpio0_30 */
+P9_11_uart_pin: pinmux_P9_11_uart_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0870, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE6) >; };	/* gpmc_wait0.uart4_rxd */
+
+/* P9_12 (ZCZ ball U18) gpio1_28 */
+P9_12_default_pin: pinmux_P9_12_default_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0878, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };	/* gpmc_be1n.gpio1_28 */
+P9_12_gpio_pin: pinmux_P9_12_gpio_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0878, PIN_OUTPUT | INPUT_EN | MUX_MODE7) >; };		/* gpmc_be1n.gpio1_28 */
+P9_12_gpio_pu_pin: pinmux_P9_12_gpio_pu_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0878, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };	/* gpmc_be1n.gpio1_28 */
+P9_12_gpio_pd_pin: pinmux_P9_12_gpio_pd_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0878, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* gpmc_be1n.gpio1_28 */
+P9_12_gpio_input_pin: pinmux_P9_12_gpio_input_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0878, PIN_INPUT | MUX_MODE7) >; };			/* gpmc_be1n.gpio1_28 */
+
+/* P9_13 (ZCZ ball U17) gpio0_31 */
+P9_13_default_pin: pinmux_P9_13_default_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0874, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };	/* gpmc_wpn.gpio0_31 */
+P9_13_gpio_pin: pinmux_P9_13_gpio_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0874, PIN_OUTPUT | INPUT_EN | MUX_MODE7) >; };		/* gpmc_wpn.gpio0_31 */
+P9_13_gpio_pu_pin: pinmux_P9_13_gpio_pu_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0874, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };	/* gpmc_wpn.gpio0_31 */
+P9_13_gpio_pd_pin: pinmux_P9_13_gpio_pd_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0874, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* gpmc_wpn.gpio0_31 */
+P9_13_gpio_input_pin: pinmux_P9_13_gpio_input_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0874, PIN_INPUT | MUX_MODE7) >; };			/* gpmc_wpn.gpio0_31 */
+P9_13_uart_pin: pinmux_P9_13_uart_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0874, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE6) >; };	/* gpmc_wpn.uart4_txd */
+
+/* P9_14 (ZCZ ball U14) gpio1_18 */
+P9_14_default_pin: pinmux_P9_14_default_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0848, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* gpmc_a2.gpio1_18 */
+P9_14_gpio_pin: pinmux_P9_14_gpio_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0848, PIN_OUTPUT | INPUT_EN | MUX_MODE7) >; };		/* gpmc_a2.gpio1_18 */
+P9_14_gpio_pu_pin: pinmux_P9_14_gpio_pu_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0848, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };	/* gpmc_a2.gpio1_18 */
+P9_14_gpio_pd_pin: pinmux_P9_14_gpio_pd_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0848, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* gpmc_a2.gpio1_18 */
+P9_14_gpio_input_pin: pinmux_P9_14_gpio_input_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0848, PIN_INPUT | MUX_MODE7) >; };			/* gpmc_a2.gpio1_18 */
+P9_14_pwm_pin: pinmux_P9_14_pwm_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0848, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE6) >; };	/* gpmc_a2.ehrpwm1a */
+
+/* P9_15 (ZCZ ball R13) gpio1_16 */
+P9_15_default_pin: pinmux_P9_15_default_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0840, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* gpmc_a0.gpio1_16 */
+P9_15_gpio_pin: pinmux_P9_15_gpio_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0840, PIN_OUTPUT | INPUT_EN | MUX_MODE7) >; };		/* gpmc_a0.gpio1_16 */
+P9_15_gpio_pu_pin: pinmux_P9_15_gpio_pu_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0840, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };	/* gpmc_a0.gpio1_16 */
+P9_15_gpio_pd_pin: pinmux_P9_15_gpio_pd_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0840, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* gpmc_a0.gpio1_16 */
+P9_15_gpio_input_pin: pinmux_P9_15_gpio_input_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0840, PIN_INPUT | MUX_MODE7) >; };			/* gpmc_a0.gpio1_16 */
+P9_15_pwm_pin: pinmux_P9_15_pwm_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0840, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE6) >; };	/* gpmc_a0.ehrpwm1_tripzone_input */
+
+/* P9_16 (ZCZ ball T14) gpio1_19 */
+P9_16_default_pin: pinmux_P9_16_default_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x084c, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* gpmc_a3.gpio1_19 */
+P9_16_gpio_pin: pinmux_P9_16_gpio_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x084c, PIN_OUTPUT | INPUT_EN | MUX_MODE7) >; };		/* gpmc_a3.gpio1_19 */
+P9_16_gpio_pu_pin: pinmux_P9_16_gpio_pu_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x084c, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };	/* gpmc_a3.gpio1_19 */
+P9_16_gpio_pd_pin: pinmux_P9_16_gpio_pd_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x084c, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* gpmc_a3.gpio1_19 */
+P9_16_gpio_input_pin: pinmux_P9_16_gpio_input_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x084c, PIN_INPUT | MUX_MODE7) >; };			/* gpmc_a3.gpio1_19 */
+P9_16_pwm_pin: pinmux_P9_16_pwm_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x084c, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE6) >; };	/* gpmc_a3.ehrpwm1b */
+
+/* P9_17 (ZCZ ball A16) gpio0_5 */
+P9_17_default_pin: pinmux_P9_17_default_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x095c, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };	/* spi0_cs0.gpio0_5 */
+P9_17_gpio_pin: pinmux_P9_17_gpio_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x095c, PIN_OUTPUT | INPUT_EN | MUX_MODE7) >; };		/* spi0_cs0.gpio0_5 */
+P9_17_gpio_pu_pin: pinmux_P9_17_gpio_pu_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x095c, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };	/* spi0_cs0.gpio0_5 */
+P9_17_gpio_pd_pin: pinmux_P9_17_gpio_pd_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x095c, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* spi0_cs0.gpio0_5 */
+P9_17_gpio_input_pin: pinmux_P9_17_gpio_input_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x095c, PIN_INPUT | MUX_MODE7) >; };			/* spi0_cs0.gpio0_5 */
+P9_17_spi_cs_pin: pinmux_P9_17_spi_cs_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x095c, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE0) >; };	/* spi0_cs0.spi0_cs0 */
+P9_17_i2c_pin: pinmux_P9_17_i2c_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x095c, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE2) >; };	/* spi0_cs0.i2c1_scl */
+P9_17_pwm_pin: pinmux_P9_17_pwm_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x095c, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE3) >; };	/* spi0_cs0.ehrpwm0_synci */
+P9_17_pru_uart_pin: pinmux_P9_17_pru_uart_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x095c, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE4) >; };	/* spi0_cs0.pr1_uart0_txd */
+
+/* P9_18 (ZCZ ball B16) gpio0_4 */
+P9_18_default_pin: pinmux_P9_18_default_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0958, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };	/* spi0_d1.gpio0_4 */
+P9_18_gpio_pin: pinmux_P9_18_gpio_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0958, PIN_OUTPUT | INPUT_EN | MUX_MODE7) >; };		/* spi0_d1.gpio0_4 */
+P9_18_gpio_pu_pin: pinmux_P9_18_gpio_pu_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0958, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };	/* spi0_d1.gpio0_4 */
+P9_18_gpio_pd_pin: pinmux_P9_18_gpio_pd_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0958, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* spi0_d1.gpio0_4 */
+P9_18_gpio_input_pin: pinmux_P9_18_gpio_input_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0958, PIN_INPUT | MUX_MODE7) >; };			/* spi0_d1.gpio0_4 */
+P9_18_spi_pin: pinmux_P9_18_spi_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0958, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE0) >; };	/* spi0_d1.spi0_d1 */
+P9_18_i2c_pin: pinmux_P9_18_i2c_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0958, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE2) >; };	/* spi0_d1.i2c1_sda */
+P9_18_pwm_pin: pinmux_P9_18_pwm_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0958, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE3) >; };	/* spi0_d1.ehrpwm0_tripzone_input */
+P9_18_pru_uart_pin: pinmux_P9_18_pru_uart_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0958, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE4) >; };	/* spi0_d1.pr1_uart0_rxd */
+
+/* P9_19 (ZCZ ball D17) i2c2_scl */
+P9_19_default_pin: pinmux_P9_19_default_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x097c, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE3) >; };	/* uart1_rtsn.i2c2_scl */
+P9_19_gpio_pin: pinmux_P9_19_gpio_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x097c, PIN_OUTPUT | INPUT_EN | MUX_MODE7) >; };		/* uart1_rtsn.gpio0_13 */
+P9_19_gpio_pu_pin: pinmux_P9_19_gpio_pu_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x097c, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };	/* uart1_rtsn.gpio0_13 */
+P9_19_gpio_pd_pin: pinmux_P9_19_gpio_pd_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x097c, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* uart1_rtsn.gpio0_13 */
+P9_19_gpio_input_pin: pinmux_P9_19_gpio_input_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x097c, PIN_INPUT | MUX_MODE7) >; };			/* uart1_rtsn.gpio0_13 */
+P9_19_timer_pin: pinmux_P9_19_timer_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x097c, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE1) >; };	/* uart1_rtsn.timer5 */
+P9_19_can_pin: pinmux_P9_19_can_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x097c, PIN_INPUT_PULLUP | MUX_MODE2) >; };		/* uart1_rtsn.dcan0_rx */
+P9_19_i2c_pin: pinmux_P9_19_i2c_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x097c, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE3) >; };	/* uart1_rtsn.i2c2_scl */
+P9_19_spi_cs_pin: pinmux_P9_19_spi_cs_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x097c, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE4) >; };	/* uart1_rtsn.spi1_cs1 */
+P9_19_pru_uart_pin: pinmux_P9_19_pru_uart_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x097c, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE5) >; };	/* uart1_rtsn.pr1_uart0_rts_n */
+
+/* P9_20 (ZCZ ball D18) i2c2_sda */
+P9_20_default_pin: pinmux_P9_20_default_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0978, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE3) >; };	/* uart1_ctsn.i2c2_sda */
+P9_20_gpio_pin: pinmux_P9_20_gpio_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0978, PIN_OUTPUT | INPUT_EN | MUX_MODE7) >; };		/* uart1_ctsn.gpio0_12 */
+P9_20_gpio_pu_pin: pinmux_P9_20_gpio_pu_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0978, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };	/* uart1_ctsn.gpio0_12 */
+P9_20_gpio_pd_pin: pinmux_P9_20_gpio_pd_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0978, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* uart1_ctsn.gpio0_12 */
+P9_20_gpio_input_pin: pinmux_P9_20_gpio_input_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0978, PIN_INPUT | MUX_MODE7) >; };			/* uart1_ctsn.gpio0_12 */
+P9_20_timer_pin: pinmux_P9_20_timer_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0978, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE1) >; };	/* uart1_ctsn.timer6 */
+P9_20_can_pin: pinmux_P9_20_can_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0978, PIN_OUTPUT_PULLUP | MUX_MODE2) >; };		/* uart1_ctsn.dcan0_tx */
+P9_20_i2c_pin: pinmux_P9_20_i2c_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0978, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE3) >; };	/* uart1_ctsn.i2c2_sda */
+P9_20_spi_cs_pin: pinmux_P9_20_spi_cs_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0978, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE4) >; };	/* uart1_ctsn.spi1_cs0 */
+P9_20_pru_uart_pin: pinmux_P9_20_pru_uart_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0978, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE5) >; };	/* uart1_ctsn.pr1_uart0_cts_n */
+
+/* P9_21 (ZCZ ball B17) gpio0_3 */
+P9_21_default_pin: pinmux_P9_21_default_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0954, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };	/* spi0_d0.gpio0_3 */
+P9_21_gpio_pin: pinmux_P9_21_gpio_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0954, PIN_OUTPUT | INPUT_EN | MUX_MODE7) >; };		/* spi0_d0.gpio0_3 */
+P9_21_gpio_pu_pin: pinmux_P9_21_gpio_pu_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0954, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };	/* spi0_d0.gpio0_3 */
+P9_21_gpio_pd_pin: pinmux_P9_21_gpio_pd_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0954, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* spi0_d0.gpio0_3 */
+P9_21_gpio_input_pin: pinmux_P9_21_gpio_input_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0954, PIN_INPUT | MUX_MODE7) >; };			/* spi0_d0.gpio0_3 */
+P9_21_spi_pin: pinmux_P9_21_spi_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0954, PIN_INPUT_PULLUP | MUX_MODE0) >; };		/* spi0_d0.spi0_d0 */
+P9_21_uart_pin: pinmux_P9_21_uart_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0954, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE1) >; };	/* spi0_d0.uart2_txd */
+P9_21_i2c_pin: pinmux_P9_21_i2c_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0954, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE2) >; };	/* spi0_d0.i2c2_scl */
+P9_21_pwm_pin: pinmux_P9_21_pwm_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0954, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE3) >; };	/* spi0_d0.ehrpwm0b */
+P9_21_pru_uart_pin: pinmux_P9_21_pru_uart_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0954, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE4) >; };	/* spi0_d0.pr1_uart0_rts_n */
+
+/* P9_22 (ZCZ ball A17) gpio0_2 */
+P9_22_default_pin: pinmux_P9_22_default_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0950, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };	/* spi0_sclk.gpio0_2 */
+P9_22_gpio_pin: pinmux_P9_22_gpio_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0950, PIN_OUTPUT | INPUT_EN | MUX_MODE7) >; };		/* spi0_sclk.gpio0_2 */
+P9_22_gpio_pu_pin: pinmux_P9_22_gpio_pu_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0950, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };	/* spi0_sclk.gpio0_2 */
+P9_22_gpio_pd_pin: pinmux_P9_22_gpio_pd_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0950, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* spi0_sclk.gpio0_2 */
+P9_22_gpio_input_pin: pinmux_P9_22_gpio_input_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0950, PIN_INPUT | MUX_MODE7) >; };			/* spi0_sclk.gpio0_2 */
+P9_22_spi_sclk_pin: pinmux_P9_22_spi_sclk_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0950, PIN_INPUT_PULLUP | MUX_MODE0) >; };		/* spi0_sclk.spi0_sclk */
+P9_22_uart_pin: pinmux_P9_22_uart_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0950, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE1) >; };	/* spi0_sclk.uart2_rxd */
+P9_22_i2c_pin: pinmux_P9_22_i2c_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0950, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE2) >; };	/* spi0_sclk.i2c2_sda */
+P9_22_pwm_pin: pinmux_P9_22_pwm_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0950, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE3) >; };	/* spi0_sclk.ehrpwm0a */
+P9_22_pru_uart_pin: pinmux_P9_22_pru_uart_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0950, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE4) >; };	/* spi0_sclk.pr1_uart0_cts_n */
+
+/* P9_23 (ZCZ ball V14) gpio1_17 */
+P9_23_default_pin: pinmux_P9_23_default_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0844, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* gpmc_a1.gpio1_17 */
+P9_23_gpio_pin: pinmux_P9_23_gpio_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0844, PIN_OUTPUT | INPUT_EN | MUX_MODE7) >; };		/* gpmc_a1.gpio1_17 */
+P9_23_gpio_pu_pin: pinmux_P9_23_gpio_pu_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0844, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };	/* gpmc_a1.gpio1_17 */
+P9_23_gpio_pd_pin: pinmux_P9_23_gpio_pd_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0844, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* gpmc_a1.gpio1_17 */
+P9_23_gpio_input_pin: pinmux_P9_23_gpio_input_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0844, PIN_INPUT | MUX_MODE7) >; };			/* gpmc_a1.gpio1_17 */
+P9_23_pwm_pin: pinmux_P9_23_pwm_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0844, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE6) >; };	/* gpmc_a1.ehrpwm0_synco */
+
+/* P9_24 (ZCZ ball D15) gpio0_15 */
+P9_24_default_pin: pinmux_P9_24_default_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0984, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };	/* uart1_txd.gpio0_15 */
+P9_24_gpio_pin: pinmux_P9_24_gpio_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0984, PIN_OUTPUT | INPUT_EN | MUX_MODE7) >; };		/* uart1_txd.gpio0_15 */
+P9_24_gpio_pu_pin: pinmux_P9_24_gpio_pu_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0984, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };	/* uart1_txd.gpio0_15 */
+P9_24_gpio_pd_pin: pinmux_P9_24_gpio_pd_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0984, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* uart1_txd.gpio0_15 */
+P9_24_gpio_input_pin: pinmux_P9_24_gpio_input_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0984, PIN_INPUT | MUX_MODE7) >; };			/* uart1_txd.gpio0_15 */
+P9_24_uart_pin: pinmux_P9_24_uart_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0984, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE0) >; };	/* uart1_txd.uart1_txd */
+P9_24_can_pin: pinmux_P9_24_can_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0984, PIN_INPUT_PULLUP | MUX_MODE2) >; };		/* uart1_txd.dcan1_rx */
+P9_24_i2c_pin: pinmux_P9_24_i2c_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0984, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE3) >; };	/* uart1_txd.i2c1_scl */
+P9_24_pru_uart_pin: pinmux_P9_24_pru_uart_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0984, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE5) >; };	/* uart1_txd.pr1_uart0_txd */
+P9_24_pruin_pin: pinmux_P9_24_pruin_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0984, PIN_INPUT | MUX_MODE6) >; };			/* uart1_txd.pru0_in16 */
+
+/* P9_25 (ZCZ ball A14) audio */
+P9_25_default_pin: pinmux_P9_25_default_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x09ac, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* mcasp0_ahclkx.gpio3_21 */
+P9_25_gpio_pin: pinmux_P9_25_gpio_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x09ac, PIN_OUTPUT | INPUT_EN | MUX_MODE7) >; };		/* mcasp0_ahclkx.gpio3_21 */
+P9_25_gpio_pu_pin: pinmux_P9_25_gpio_pu_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x09ac, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };	/* mcasp0_ahclkx.gpio3_21 */
+P9_25_gpio_pd_pin: pinmux_P9_25_gpio_pd_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x09ac, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* mcasp0_ahclkx.gpio3_21 */
+P9_25_gpio_input_pin: pinmux_P9_25_gpio_input_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x09ac, PIN_INPUT | MUX_MODE7) >; };			/* mcasp0_ahclkx.gpio3_21 */
+P9_25_qep_pin: pinmux_P9_25_qep_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x09ac, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE1) >; };	/* mcasp0_ahclkx.eqep0_strobe */
+P9_25_pruout_pin: pinmux_P9_25_pruout_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x09ac, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE5) >; };	/* mcasp0_ahclkx.pru0_out7 */
+P9_25_pruin_pin: pinmux_P9_25_pruin_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x09ac, PIN_INPUT | MUX_MODE6) >; };			/* mcasp0_ahclkx.pru0_in7 */
+
+/* P9_26 (ZCZ ball D16) gpio0_14 */
+P9_26_default_pin: pinmux_P9_26_default_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0980, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };	/* uart1_rxd.gpio0_14 */
+P9_26_gpio_pin: pinmux_P9_26_gpio_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0980, PIN_OUTPUT | INPUT_EN | MUX_MODE7) >; };		/* uart1_rxd.gpio0_14 */
+P9_26_gpio_pu_pin: pinmux_P9_26_gpio_pu_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0980, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };	/* uart1_rxd.gpio0_14 */
+P9_26_gpio_pd_pin: pinmux_P9_26_gpio_pd_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0980, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* uart1_rxd.gpio0_14 */
+P9_26_gpio_input_pin: pinmux_P9_26_gpio_input_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0980, PIN_INPUT | MUX_MODE7) >; };			/* uart1_rxd.gpio0_14 */
+P9_26_uart_pin: pinmux_P9_26_uart_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0980, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE0) >; };	/* uart1_rxd.uart1_rxd */
+P9_26_can_pin: pinmux_P9_26_can_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0980, PIN_OUTPUT_PULLUP | MUX_MODE2) >; };		/* uart1_rxd.dcan1_tx */
+P9_26_i2c_pin: pinmux_P9_26_i2c_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0980, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE3) >; };	/* uart1_rxd.i2c1_sda */
+P9_26_pru_uart_pin: pinmux_P9_26_pru_uart_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0980, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE5) >; };	/* uart1_rxd.pr1_uart0_rxd */
+P9_26_pruin_pin: pinmux_P9_26_pruin_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0980, PIN_INPUT | MUX_MODE6) >; };			/* uart1_rxd.pru1_in16 */
+
+/* P9_27 (ZCZ ball C13) gpio3_19 */
+P9_27_default_pin: pinmux_P9_27_default_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x09a4, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* mcasp0_fsr.gpio3_19 */
+P9_27_gpio_pin: pinmux_P9_27_gpio_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x09a4, PIN_OUTPUT | INPUT_EN | MUX_MODE7) >; };		/* mcasp0_fsr.gpio3_19 */
+P9_27_gpio_pu_pin: pinmux_P9_27_gpio_pu_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x09a4, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };	/* mcasp0_fsr.gpio3_19 */
+P9_27_gpio_pd_pin: pinmux_P9_27_gpio_pd_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x09a4, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* mcasp0_fsr.gpio3_19 */
+P9_27_gpio_input_pin: pinmux_P9_27_gpio_input_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x09a4, PIN_INPUT | MUX_MODE7) >; };			/* mcasp0_fsr.gpio3_19 */
+P9_27_qep_pin: pinmux_P9_27_qep_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x09a4, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE1) >; };	/* mcasp0_fsr.eqep0b_in */
+P9_27_pruout_pin: pinmux_P9_27_pruout_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x09a4, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE5) >; };	/* mcasp0_fsr.pru0_out5 */
+P9_27_pruin_pin: pinmux_P9_27_pruin_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x09a4, PIN_INPUT | MUX_MODE6) >; };			/* mcasp0_fsr.pru0_in5 */
+
+/* P9_28 (ZCZ ball C12) audio */
+P9_28_default_pin: pinmux_P9_28_default_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x099c, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* mcasp0_ahclkr.gpio3_17 */
+P9_28_gpio_pin: pinmux_P9_28_gpio_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x099c, PIN_OUTPUT | INPUT_EN | MUX_MODE7) >; };		/* mcasp0_ahclkr.gpio3_17 */
+P9_28_gpio_pu_pin: pinmux_P9_28_gpio_pu_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x099c, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };	/* mcasp0_ahclkr.gpio3_17 */
+P9_28_gpio_pd_pin: pinmux_P9_28_gpio_pd_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x099c, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* mcasp0_ahclkr.gpio3_17 */
+P9_28_gpio_input_pin: pinmux_P9_28_gpio_input_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x099c, PIN_INPUT | MUX_MODE7) >; };			/* mcasp0_ahclkr.gpio3_17 */
+P9_28_pwm_pin: pinmux_P9_28_pwm_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x099c, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE1) >; };	/* mcasp0_ahclkr.ehrpwm0_synci */
+P9_28_spi_cs_pin: pinmux_P9_28_spi_cs_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x099c, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE3) >; };	/* mcasp0_ahclkr.spi1_cs0 */
+P9_28_pwm2_pin: pinmux_P9_28_pwm2_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x099c, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE4) >; };	/* mcasp0_ahclkr.ecap2_in_pwm2_out */
+P9_28_pruout_pin: pinmux_P9_28_pruout_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x099c, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE5) >; };	/* mcasp0_ahclkr.pru0_out3 */
+P9_28_pruin_pin: pinmux_P9_28_pruin_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x099c, PIN_INPUT | MUX_MODE6) >; };			/* mcasp0_ahclkr.pru0_in3 */
+
+/* P9_29 (ZCZ ball B13) audio */
+P9_29_default_pin: pinmux_P9_29_default_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0994, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* mcasp0_fsx.gpio3_15 */
+P9_29_gpio_pin: pinmux_P9_29_gpio_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0994, PIN_OUTPUT | INPUT_EN | MUX_MODE7) >; };		/* mcasp0_fsx.gpio3_15 */
+P9_29_gpio_pu_pin: pinmux_P9_29_gpio_pu_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0994, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };	/* mcasp0_fsx.gpio3_15 */
+P9_29_gpio_pd_pin: pinmux_P9_29_gpio_pd_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0994, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* mcasp0_fsx.gpio3_15 */
+P9_29_gpio_input_pin: pinmux_P9_29_gpio_input_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0994, PIN_INPUT | MUX_MODE7) >; };			/* mcasp0_fsx.gpio3_15 */
+P9_29_pwm_pin: pinmux_P9_29_pwm_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0994, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE1) >; };	/* mcasp0_fsx.ehrpwm0b */
+P9_29_spi_pin: pinmux_P9_29_spi_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0994, PIN_INPUT_PULLUP | MUX_MODE3) >; };		/* mcasp0_fsx.spi1_d0 */
+P9_29_pruout_pin: pinmux_P9_29_pruout_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0994, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE5) >; };	/* mcasp0_fsx.pru0_out1 */
+P9_29_pruin_pin: pinmux_P9_29_pruin_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0994, PIN_INPUT | MUX_MODE6) >; };			/* mcasp0_fsx.pru0_in1 */
+
+/* P9_30 (ZCZ ball D12) gpio3_16 */
+P9_30_default_pin: pinmux_P9_30_default_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0998, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* mcasp0_axr0.gpio3_16 */
+P9_30_gpio_pin: pinmux_P9_30_gpio_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0998, PIN_OUTPUT | INPUT_EN | MUX_MODE7) >; };		/* mcasp0_axr0.gpio3_16 */
+P9_30_gpio_pu_pin: pinmux_P9_30_gpio_pu_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0998, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };	/* mcasp0_axr0.gpio3_16 */
+P9_30_gpio_pd_pin: pinmux_P9_30_gpio_pd_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0998, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* mcasp0_axr0.gpio3_16 */
+P9_30_gpio_input_pin: pinmux_P9_30_gpio_input_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0998, PIN_INPUT | MUX_MODE7) >; };			/* mcasp0_axr0.gpio3_16 */
+P9_30_pwm_pin: pinmux_P9_30_pwm_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0998, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE1) >; };	/* mcasp0_axr0.ehrpwm0_tripzone_input */
+P9_30_spi_pin: pinmux_P9_30_spi_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0998, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE3) >; };	/* mcasp0_axr0.spi1_d1 */
+P9_30_pruout_pin: pinmux_P9_30_pruout_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0998, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE5) >; };	/* mcasp0_axr0.pru0_out2 */
+P9_30_pruin_pin: pinmux_P9_30_pruin_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0998, PIN_INPUT | MUX_MODE6) >; };			/* mcasp0_axr0.pru0_in2 */
+
+/* P9_31 (ZCZ ball A13) audio */
+P9_31_default_pin: pinmux_P9_31_default_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0990, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* mcasp0_aclkx.gpio3_14 */
+P9_31_gpio_pin: pinmux_P9_31_gpio_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0990, PIN_OUTPUT | INPUT_EN | MUX_MODE7) >; };		/* mcasp0_aclkx.gpio3_14 */
+P9_31_gpio_pu_pin: pinmux_P9_31_gpio_pu_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0990, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };	/* mcasp0_aclkx.gpio3_14 */
+P9_31_gpio_pd_pin: pinmux_P9_31_gpio_pd_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0990, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* mcasp0_aclkx.gpio3_14 */
+P9_31_gpio_input_pin: pinmux_P9_31_gpio_input_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0990, PIN_INPUT | MUX_MODE7) >; };			/* mcasp0_aclkx.gpio3_14 */
+P9_31_pwm_pin: pinmux_P9_31_pwm_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0990, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE1) >; };	/* mcasp0_aclkx.ehrpwm0a */
+P9_31_spi_sclk_pin: pinmux_P9_31_spi_sclk_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0990, PIN_INPUT_PULLUP | MUX_MODE3) >; };		/* mcasp0_aclkx.spi1_sclk */
+P9_31_pruout_pin: pinmux_P9_31_pruout_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0990, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE5) >; };	/* mcasp0_aclkx.pru0_out0 */
+P9_31_pruin_pin: pinmux_P9_31_pruin_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0990, PIN_INPUT | MUX_MODE6) >; };			/* mcasp0_aclkx.pru0_in0 */
+
+/* P9_32                VADC */
+
+/* P9_33 (ZCZ ball C8)  AIN4         */
+
+/* P9_34                AGND */
+
+/* P9_35 (ZCZ ball A8)  AIN6         */
+
+/* P9_36 (ZCZ ball B8)  AIN5         */
+
+/* P9_37 (ZCZ ball B7)  AIN2         */
+
+/* P9_38 (ZCZ ball A7)  AIN3         */
+
+/* P9_39 (ZCZ ball B6)  AIN0         */
+
+/* P9_40 (ZCZ ball C7)  AIN1         */
+
+/* P9_41 (ZCZ ball D14) gpio0_20 */
+P9_41_default_pin: pinmux_P9_41_default_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x09b4, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* xdma_event_intr1.gpio0_20 */
+P9_41_gpio_pin: pinmux_P9_41_gpio_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x09b4, PIN_OUTPUT | INPUT_EN | MUX_MODE7) >; };		/* xdma_event_intr1.gpio0_20 */
+P9_41_gpio_pu_pin: pinmux_P9_41_gpio_pu_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x09b4, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };	/* xdma_event_intr1.gpio0_20 */
+P9_41_gpio_pd_pin: pinmux_P9_41_gpio_pd_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x09b4, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* xdma_event_intr1.gpio0_20 */
+P9_41_gpio_input_pin: pinmux_P9_41_gpio_input_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x09b4, PIN_INPUT | MUX_MODE7) >; };			/* xdma_event_intr1.gpio0_20 */
+P9_41_timer_pin: pinmux_P9_41_timer_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x09b4, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE4) >; };	/* xdma_event_intr1.timer7 */
+P9_41_pruin_pin: pinmux_P9_41_pruin_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x09b4, PIN_INPUT | MUX_MODE5) >; };			/* xdma_event_intr1.pru0_in16 */
+
+/* P9_41.1 */
+/* P9_91 (ZCZ ball D13) gpio3_20 */
+P9_91_default_pin: pinmux_P9_91_default_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x09a8, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* mcasp0_axr1.gpio3_20 */
+P9_91_gpio_pin: pinmux_P9_91_gpio_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x09a8, PIN_OUTPUT | INPUT_EN | MUX_MODE7) >; };		/* mcasp0_axr1.gpio3_20 */
+P9_91_gpio_pu_pin: pinmux_P9_91_gpio_pu_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x09a8, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };	/* mcasp0_axr1.gpio3_20 */
+P9_91_gpio_pd_pin: pinmux_P9_91_gpio_pd_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x09a8, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* mcasp0_axr1.gpio3_20 */
+P9_91_gpio_input_pin: pinmux_P9_91_gpio_input_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x09a8, PIN_INPUT | MUX_MODE7) >; };			/* mcasp0_axr1.gpio3_20 */
+P9_91_qep_pin: pinmux_P9_91_qep_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x09a8, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE1) >; };	/* mcasp0_axr1.eqep0_index */
+P9_91_pruout_pin: pinmux_P9_91_pruout_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x09a8, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE5) >; };	/* mcasp0_axr1.pru0_out6 */
+P9_91_pruin_pin: pinmux_P9_91_pruin_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x09a8, PIN_INPUT | MUX_MODE6) >; };			/* mcasp0_axr1.pru0_in6 */
+
+/* P9_42 (ZCZ ball C18) gpio0_7 */
+P9_42_default_pin: pinmux_P9_42_default_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0964, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* eCAP0_in_PWM0_out.gpio0_7 */
+P9_42_gpio_pin: pinmux_P9_42_gpio_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0964, PIN_OUTPUT | INPUT_EN | MUX_MODE7) >; };		/* eCAP0_in_PWM0_out.gpio0_7 */
+P9_42_gpio_pu_pin: pinmux_P9_42_gpio_pu_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0964, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };	/* eCAP0_in_PWM0_out.gpio0_7 */
+P9_42_gpio_pd_pin: pinmux_P9_42_gpio_pd_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0964, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* eCAP0_in_PWM0_out.gpio0_7 */
+P9_42_gpio_input_pin: pinmux_P9_42_gpio_input_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0964, PIN_INPUT | MUX_MODE7) >; };			/* eCAP0_in_PWM0_out.gpio0_7 */
+P9_42_pwm_pin: pinmux_P9_42_pwm_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0964, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE0) >; };	/* eCAP0_in_PWM0_out.ecap0_in_pwm0_out */
+P9_42_uart_pin: pinmux_P9_42_uart_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0964, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE1) >; };	/* eCAP0_in_PWM0_out.uart3_txd */
+P9_42_spi_cs_pin: pinmux_P9_42_spi_cs_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0964, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE2) >; };	/* eCAP0_in_PWM0_out.spi1_cs1 */
+P9_42_pru_ecap_pin: pinmux_P9_42_pru_ecap_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0964, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE3) >; };	/* eCAP0_in_PWM0_out.pr1_ecap0_ecap_capin_apwm_o */
+P9_42_spi_sclk_pin: pinmux_P9_42_spi_sclk_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0964, PIN_INPUT_PULLUP | MUX_MODE4) >; };		/* eCAP0_in_PWM0_out.spi1_sclk */
+
+/* P9_42.1 */
+/* P9_92 (ZCZ ball B12) gpio3_18 */
+P9_92_default_pin: pinmux_P9_92_default_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x09a0, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* mcasp0_aclkr.gpio3_18 */
+P9_92_gpio_pin: pinmux_P9_92_gpio_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x09a0, PIN_OUTPUT | INPUT_EN | MUX_MODE7) >; };		/* mcasp0_aclkr.gpio3_18 */
+P9_92_gpio_pu_pin: pinmux_P9_92_gpio_pu_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x09a0, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };	/* mcasp0_aclkr.gpio3_18 */
+P9_92_gpio_pd_pin: pinmux_P9_92_gpio_pd_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x09a0, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* mcasp0_aclkr.gpio3_18 */
+P9_92_gpio_input_pin: pinmux_P9_92_gpio_input_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x09a0, PIN_INPUT | MUX_MODE7) >; };			/* mcasp0_aclkr.gpio3_18 */
+P9_92_qep_pin: pinmux_P9_92_qep_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x09a0, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE1) >; };	/* mcasp0_aclkr.eqep0a_in */
+P9_92_pruout_pin: pinmux_P9_92_pruout_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x09a0, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE5) >; };	/* mcasp0_aclkr.pru0_out4 */
+P9_92_pruin_pin: pinmux_P9_92_pruin_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x09a0, PIN_INPUT | MUX_MODE6) >; };			/* mcasp0_aclkr.pru0_in4 */
+
+/* P9_43                GND */
+
+/* P9_44                GND */
+
+/* P9_45                GND */
+
+/* P9_46                GND */
+
+/************************/
+/* Special */
+/************************/
+
+
+
+/************************/
+/* P8 Header */
+/************************/
+
+/* P8_01                GND */
+
+/* P8_02                GND */
+
+
+/* P8_03 (ZCZ ball R9) emmc */
+P8_03_pinmux {
+	compatible = "bone-pinmux-helper";
+	status = "okay";
+	pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input";
+	pinctrl-0 = <&P8_03_default_pin>;
+	pinctrl-1 = <&P8_03_gpio_pin>;
+	pinctrl-2 = <&P8_03_gpio_pu_pin>;
+	pinctrl-3 = <&P8_03_gpio_pd_pin>;
+	pinctrl-4 = <&P8_03_gpio_input_pin>;
+};
+
+/* P8_04 (ZCZ ball T9) emmc */
+P8_04_pinmux {
+	compatible = "bone-pinmux-helper";
+	status = "okay";
+	pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input";
+	pinctrl-0 = <&P8_04_default_pin>;
+	pinctrl-1 = <&P8_04_gpio_pin>;
+	pinctrl-2 = <&P8_04_gpio_pu_pin>;
+	pinctrl-3 = <&P8_04_gpio_pd_pin>;
+	pinctrl-4 = <&P8_04_gpio_input_pin>;
+};
+
+/* P8_05 (ZCZ ball R8) emmc */
+P8_05_pinmux {
+	compatible = "bone-pinmux-helper";
+	status = "okay";
+	pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input";
+	pinctrl-0 = <&P8_05_default_pin>;
+	pinctrl-1 = <&P8_05_gpio_pin>;
+	pinctrl-2 = <&P8_05_gpio_pu_pin>;
+	pinctrl-3 = <&P8_05_gpio_pd_pin>;
+	pinctrl-4 = <&P8_05_gpio_input_pin>;
+};
+
+/* P8_06 (ZCZ ball T8) emmc */
+P8_06_pinmux {
+	compatible = "bone-pinmux-helper";
+	status = "okay";
+	pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input";
+	pinctrl-0 = <&P8_06_default_pin>;
+	pinctrl-1 = <&P8_06_gpio_pin>;
+	pinctrl-2 = <&P8_06_gpio_pu_pin>;
+	pinctrl-3 = <&P8_06_gpio_pd_pin>;
+	pinctrl-4 = <&P8_06_gpio_input_pin>;
+};
+
+/* P8_07 (ZCZ ball R7) */
+P8_07_pinmux {
+	compatible = "bone-pinmux-helper";
+	status = "okay";
+	pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input", "timer";
+	pinctrl-0 = <&P8_07_default_pin>;
+	pinctrl-1 = <&P8_07_gpio_pin>;
+	pinctrl-2 = <&P8_07_gpio_pu_pin>;
+	pinctrl-3 = <&P8_07_gpio_pd_pin>;
+	pinctrl-4 = <&P8_07_gpio_input_pin>;
+	pinctrl-5 = <&P8_07_timer_pin>;
+};
+
+/* P8_08 (ZCZ ball T7) */
+P8_08_pinmux {
+	compatible = "bone-pinmux-helper";
+	status = "okay";
+	pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input", "timer";
+	pinctrl-0 = <&P8_08_default_pin>;
+	pinctrl-1 = <&P8_08_gpio_pin>;
+	pinctrl-2 = <&P8_08_gpio_pu_pin>;
+	pinctrl-3 = <&P8_08_gpio_pd_pin>;
+	pinctrl-4 = <&P8_08_gpio_input_pin>;
+	pinctrl-5 = <&P8_08_timer_pin>;
+};
+
+/* P8_09 (ZCZ ball T6) */
+P8_09_pinmux {
+	compatible = "bone-pinmux-helper";
+	status = "okay";
+	pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input", "timer";
+	pinctrl-0 = <&P8_09_default_pin>;
+	pinctrl-1 = <&P8_09_gpio_pin>;
+	pinctrl-2 = <&P8_09_gpio_pu_pin>;
+	pinctrl-3 = <&P8_09_gpio_pd_pin>;
+	pinctrl-4 = <&P8_09_gpio_input_pin>;
+	pinctrl-5 = <&P8_09_timer_pin>;
+};
+
+/* P8_10 (ZCZ ball U6) */
+P8_10_pinmux {
+	compatible = "bone-pinmux-helper";
+	status = "okay";
+	pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input", "timer";
+	pinctrl-0 = <&P8_10_default_pin>;
+	pinctrl-1 = <&P8_10_gpio_pin>;
+	pinctrl-2 = <&P8_10_gpio_pu_pin>;
+	pinctrl-3 = <&P8_10_gpio_pd_pin>;
+	pinctrl-4 = <&P8_10_gpio_input_pin>;
+	pinctrl-5 = <&P8_10_timer_pin>;
+};
+
+/* P8_11 (ZCZ ball R12) */
+P8_11_pinmux {
+	compatible = "bone-pinmux-helper";
+	status = "okay";
+	pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input", "qep", "pruout";
+	pinctrl-0 = <&P8_11_default_pin>;
+	pinctrl-1 = <&P8_11_gpio_pin>;
+	pinctrl-2 = <&P8_11_gpio_pu_pin>;
+	pinctrl-3 = <&P8_11_gpio_pd_pin>;
+	pinctrl-4 = <&P8_11_gpio_input_pin>;
+	pinctrl-5 = <&P8_11_qep_pin>;
+	pinctrl-6 = <&P8_11_pruout_pin>;
+};
+
+/* P8_12 (ZCZ ball T12) */
+P8_12_pinmux {
+	compatible = "bone-pinmux-helper";
+	status = "okay";
+	pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input", "qep", "pruout";
+	pinctrl-0 = <&P8_12_default_pin>;
+	pinctrl-1 = <&P8_12_gpio_pin>;
+	pinctrl-2 = <&P8_12_gpio_pu_pin>;
+	pinctrl-3 = <&P8_12_gpio_pd_pin>;
+	pinctrl-4 = <&P8_12_gpio_input_pin>;
+	pinctrl-5 = <&P8_12_qep_pin>;
+	pinctrl-6 = <&P8_12_pruout_pin>;
+};
+
+/* P8_13 (ZCZ ball T10) */
+P8_13_pinmux {
+	compatible = "bone-pinmux-helper";
+	status = "okay";
+	pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input", "pwm";
+	pinctrl-0 = <&P8_13_default_pin>;
+	pinctrl-1 = <&P8_13_gpio_pin>;
+	pinctrl-2 = <&P8_13_gpio_pu_pin>;
+	pinctrl-3 = <&P8_13_gpio_pd_pin>;
+	pinctrl-4 = <&P8_13_gpio_input_pin>;
+	pinctrl-5 = <&P8_13_pwm_pin>;
+};
+
+/* P8_14 (ZCZ ball T11) */
+P8_14_pinmux {
+	compatible = "bone-pinmux-helper";
+	status = "okay";
+	pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input", "pwm";
+	pinctrl-0 = <&P8_14_default_pin>;
+	pinctrl-1 = <&P8_14_gpio_pin>;
+	pinctrl-2 = <&P8_14_gpio_pu_pin>;
+	pinctrl-3 = <&P8_14_gpio_pd_pin>;
+	pinctrl-4 = <&P8_14_gpio_input_pin>;
+	pinctrl-5 = <&P8_14_pwm_pin>;
+};
+
+/* P8_15 (ZCZ ball U13) */
+P8_15_pinmux {
+	compatible = "bone-pinmux-helper";
+	status = "okay";
+	pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input", "qep", "pru_ecap", "pruin";
+	pinctrl-0 = <&P8_15_default_pin>;
+	pinctrl-1 = <&P8_15_gpio_pin>;
+	pinctrl-2 = <&P8_15_gpio_pu_pin>;
+	pinctrl-3 = <&P8_15_gpio_pd_pin>;
+	pinctrl-4 = <&P8_15_gpio_input_pin>;
+	pinctrl-5 = <&P8_15_qep_pin>;
+	pinctrl-6 = <&P8_15_pru_ecap_pin>;
+	pinctrl-7 = <&P8_15_pruin_pin>;
+};
+
+/* P8_16 (ZCZ ball V13) */
+P8_16_pinmux {
+	compatible = "bone-pinmux-helper";
+	status = "okay";
+	pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input", "qep", "pruin";
+	pinctrl-0 = <&P8_16_default_pin>;
+	pinctrl-1 = <&P8_16_gpio_pin>;
+	pinctrl-2 = <&P8_16_gpio_pu_pin>;
+	pinctrl-3 = <&P8_16_gpio_pd_pin>;
+	pinctrl-4 = <&P8_16_gpio_input_pin>;
+	pinctrl-5 = <&P8_16_qep_pin>;
+	pinctrl-6 = <&P8_16_pruin_pin>;
+};
+
+/* P8_17 (ZCZ ball U12) */
+P8_17_pinmux {
+	compatible = "bone-pinmux-helper";
+	status = "okay";
+	pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input", "pwm";
+	pinctrl-0 = <&P8_17_default_pin>;
+	pinctrl-1 = <&P8_17_gpio_pin>;
+	pinctrl-2 = <&P8_17_gpio_pu_pin>;
+	pinctrl-3 = <&P8_17_gpio_pd_pin>;
+	pinctrl-4 = <&P8_17_gpio_input_pin>;
+	pinctrl-5 = <&P8_17_pwm_pin>;
+};
+
+/* P8_18 (ZCZ ball V12) */
+P8_18_pinmux {
+	compatible = "bone-pinmux-helper";
+	status = "okay";
+	pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input";
+	pinctrl-0 = <&P8_18_default_pin>;
+	pinctrl-1 = <&P8_18_gpio_pin>;
+	pinctrl-2 = <&P8_18_gpio_pu_pin>;
+	pinctrl-3 = <&P8_18_gpio_pd_pin>;
+	pinctrl-4 = <&P8_18_gpio_input_pin>;
+};
+
+/* P8_19 (ZCZ ball U10) */
+P8_19_pinmux {
+	compatible = "bone-pinmux-helper";
+	status = "okay";
+	pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input", "pwm";
+	pinctrl-0 = <&P8_19_default_pin>;
+	pinctrl-1 = <&P8_19_gpio_pin>;
+	pinctrl-2 = <&P8_19_gpio_pu_pin>;
+	pinctrl-3 = <&P8_19_gpio_pd_pin>;
+	pinctrl-4 = <&P8_19_gpio_input_pin>;
+	pinctrl-5 = <&P8_19_pwm_pin>;
+};
+
+/* P8_20 (ZCZ ball V9) emmc */
+P8_20_pinmux {
+	compatible = "bone-pinmux-helper";
+	status = "okay";
+	pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input", "pruout", "pruin";
+	pinctrl-0 = <&P8_20_default_pin>;
+	pinctrl-1 = <&P8_20_gpio_pin>;
+	pinctrl-2 = <&P8_20_gpio_pu_pin>;
+	pinctrl-3 = <&P8_20_gpio_pd_pin>;
+	pinctrl-4 = <&P8_20_gpio_input_pin>;
+	pinctrl-5 = <&P8_20_pruout_pin>;
+	pinctrl-6 = <&P8_20_pruin_pin>;
+};
+
+/* P8_21 (ZCZ ball U9) emmc */
+P8_21_pinmux {
+	compatible = "bone-pinmux-helper";
+	status = "okay";
+	pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input", "pruout", "pruin";
+	pinctrl-0 = <&P8_21_default_pin>;
+	pinctrl-1 = <&P8_21_gpio_pin>;
+	pinctrl-2 = <&P8_21_gpio_pu_pin>;
+	pinctrl-3 = <&P8_21_gpio_pd_pin>;
+	pinctrl-4 = <&P8_21_gpio_input_pin>;
+	pinctrl-5 = <&P8_21_pruout_pin>;
+	pinctrl-6 = <&P8_21_pruin_pin>;
+};
+
+/* P8_22 (ZCZ ball V8) emmc */
+P8_22_pinmux {
+	compatible = "bone-pinmux-helper";
+	status = "okay";
+	pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input";
+	pinctrl-0 = <&P8_22_default_pin>;
+	pinctrl-1 = <&P8_22_gpio_pin>;
+	pinctrl-2 = <&P8_22_gpio_pu_pin>;
+	pinctrl-3 = <&P8_22_gpio_pd_pin>;
+	pinctrl-4 = <&P8_22_gpio_input_pin>;
+};
+
+/* P8_23 (ZCZ ball U8) emmc */
+P8_23_pinmux {
+	compatible = "bone-pinmux-helper";
+	status = "okay";
+	pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input";
+	pinctrl-0 = <&P8_23_default_pin>;
+	pinctrl-1 = <&P8_23_gpio_pin>;
+	pinctrl-2 = <&P8_23_gpio_pu_pin>;
+	pinctrl-3 = <&P8_23_gpio_pd_pin>;
+	pinctrl-4 = <&P8_23_gpio_input_pin>;
+};
+
+/* P8_24 (ZCZ ball V7) emmc */
+P8_24_pinmux {
+	compatible = "bone-pinmux-helper";
+	status = "okay";
+	pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input";
+	pinctrl-0 = <&P8_24_default_pin>;
+	pinctrl-1 = <&P8_24_gpio_pin>;
+	pinctrl-2 = <&P8_24_gpio_pu_pin>;
+	pinctrl-3 = <&P8_24_gpio_pd_pin>;
+	pinctrl-4 = <&P8_24_gpio_input_pin>;
+};
+
+/* P8_25 (ZCZ ball U7) emmc */
+P8_25_pinmux {
+	compatible = "bone-pinmux-helper";
+	status = "okay";
+	pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input";
+	pinctrl-0 = <&P8_25_default_pin>;
+	pinctrl-1 = <&P8_25_gpio_pin>;
+	pinctrl-2 = <&P8_25_gpio_pu_pin>;
+	pinctrl-3 = <&P8_25_gpio_pd_pin>;
+	pinctrl-4 = <&P8_25_gpio_input_pin>;
+};
+
+/* P8_26 (ZCZ ball V6) */
+P8_26_pinmux {
+	compatible = "bone-pinmux-helper";
+	status = "okay";
+	pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input";
+	pinctrl-0 = <&P8_26_default_pin>;
+	pinctrl-1 = <&P8_26_gpio_pin>;
+	pinctrl-2 = <&P8_26_gpio_pu_pin>;
+	pinctrl-3 = <&P8_26_gpio_pd_pin>;
+	pinctrl-4 = <&P8_26_gpio_input_pin>;
+};
+
+/* P8_27 (ZCZ ball U5) hdmi */
+P8_27_pinmux {
+	compatible = "bone-pinmux-helper";
+	status = "okay";
+	pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input", "pruout", "pruin";
+	pinctrl-0 = <&P8_27_default_pin>;
+	pinctrl-1 = <&P8_27_gpio_pin>;
+	pinctrl-2 = <&P8_27_gpio_pu_pin>;
+	pinctrl-3 = <&P8_27_gpio_pd_pin>;
+	pinctrl-4 = <&P8_27_gpio_input_pin>;
+	pinctrl-5 = <&P8_27_pruout_pin>;
+	pinctrl-6 = <&P8_27_pruin_pin>;
+};
+
+/* P8_28 (ZCZ ball V5) hdmi */
+P8_28_pinmux {
+	compatible = "bone-pinmux-helper";
+	status = "okay";
+	pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input", "pruout", "pruin";
+	pinctrl-0 = <&P8_28_default_pin>;
+	pinctrl-1 = <&P8_28_gpio_pin>;
+	pinctrl-2 = <&P8_28_gpio_pu_pin>;
+	pinctrl-3 = <&P8_28_gpio_pd_pin>;
+	pinctrl-4 = <&P8_28_gpio_input_pin>;
+	pinctrl-5 = <&P8_28_pruout_pin>;
+	pinctrl-6 = <&P8_28_pruin_pin>;
+};
+
+/* P8_29 (ZCZ ball R5) hdmi */
+P8_29_pinmux {
+	compatible = "bone-pinmux-helper";
+	status = "okay";
+	pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input", "pruout", "pruin";
+	pinctrl-0 = <&P8_29_default_pin>;
+	pinctrl-1 = <&P8_29_gpio_pin>;
+	pinctrl-2 = <&P8_29_gpio_pu_pin>;
+	pinctrl-3 = <&P8_29_gpio_pd_pin>;
+	pinctrl-4 = <&P8_29_gpio_input_pin>;
+	pinctrl-5 = <&P8_29_pruout_pin>;
+	pinctrl-6 = <&P8_29_pruin_pin>;
+};
+
+/* P8_30 (ZCZ ball R6) hdmi */
+P8_30_pinmux {
+	compatible = "bone-pinmux-helper";
+	status = "okay";
+	pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input", "pruout", "pruin";
+	pinctrl-0 = <&P8_30_default_pin>;
+	pinctrl-1 = <&P8_30_gpio_pin>;
+	pinctrl-2 = <&P8_30_gpio_pu_pin>;
+	pinctrl-3 = <&P8_30_gpio_pd_pin>;
+	pinctrl-4 = <&P8_30_gpio_input_pin>;
+	pinctrl-5 = <&P8_30_pruout_pin>;
+	pinctrl-6 = <&P8_30_pruin_pin>;
+};
+
+/* P8_31 (ZCZ ball V4) hdmi */
+P8_31_pinmux {
+	compatible = "bone-pinmux-helper";
+	status = "okay";
+	pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input", "uart", "qep";
+	pinctrl-0 = <&P8_31_default_pin>;
+	pinctrl-1 = <&P8_31_gpio_pin>;
+	pinctrl-2 = <&P8_31_gpio_pu_pin>;
+	pinctrl-3 = <&P8_31_gpio_pd_pin>;
+	pinctrl-4 = <&P8_31_gpio_input_pin>;
+	pinctrl-5 = <&P8_31_uart_pin>;
+	pinctrl-6 = <&P8_31_qep_pin>;
+};
+
+/* P8_32 (ZCZ ball T5) hdmi */
+P8_32_pinmux {
+	compatible = "bone-pinmux-helper";
+	status = "okay";
+	pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input", "qep";
+	pinctrl-0 = <&P8_32_default_pin>;
+	pinctrl-1 = <&P8_32_gpio_pin>;
+	pinctrl-2 = <&P8_32_gpio_pu_pin>;
+	pinctrl-3 = <&P8_32_gpio_pd_pin>;
+	pinctrl-4 = <&P8_32_gpio_input_pin>;
+	pinctrl-5 = <&P8_32_qep_pin>;
+};
+
+/* P8_33 (ZCZ ball V3) hdmi */
+P8_33_pinmux {
+	compatible = "bone-pinmux-helper";
+	status = "okay";
+	pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input", "qep";
+	pinctrl-0 = <&P8_33_default_pin>;
+	pinctrl-1 = <&P8_33_gpio_pin>;
+	pinctrl-2 = <&P8_33_gpio_pu_pin>;
+	pinctrl-3 = <&P8_33_gpio_pd_pin>;
+	pinctrl-4 = <&P8_33_gpio_input_pin>;
+	pinctrl-5 = <&P8_33_qep_pin>;
+};
+
+/* P8_34 (ZCZ ball U4) hdmi */
+P8_34_pinmux {
+	compatible = "bone-pinmux-helper";
+	status = "okay";
+	pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input", "pwm";
+	pinctrl-0 = <&P8_34_default_pin>;
+	pinctrl-1 = <&P8_34_gpio_pin>;
+	pinctrl-2 = <&P8_34_gpio_pu_pin>;
+	pinctrl-3 = <&P8_34_gpio_pd_pin>;
+	pinctrl-4 = <&P8_34_gpio_input_pin>;
+	pinctrl-5 = <&P8_34_pwm_pin>;
+};
+
+/* P8_35 (ZCZ ball V2) hdmi */
+P8_35_pinmux {
+	compatible = "bone-pinmux-helper";
+	status = "okay";
+	pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input", "qep";
+	pinctrl-0 = <&P8_35_default_pin>;
+	pinctrl-1 = <&P8_35_gpio_pin>;
+	pinctrl-2 = <&P8_35_gpio_pu_pin>;
+	pinctrl-3 = <&P8_35_gpio_pd_pin>;
+	pinctrl-4 = <&P8_35_gpio_input_pin>;
+	pinctrl-5 = <&P8_35_qep_pin>;
+};
+
+/* P8_36 (ZCZ ball U3) hdmi */
+P8_36_pinmux {
+	compatible = "bone-pinmux-helper";
+	status = "okay";
+	pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input", "pwm";
+	pinctrl-0 = <&P8_36_default_pin>;
+	pinctrl-1 = <&P8_36_gpio_pin>;
+	pinctrl-2 = <&P8_36_gpio_pu_pin>;
+	pinctrl-3 = <&P8_36_gpio_pd_pin>;
+	pinctrl-4 = <&P8_36_gpio_input_pin>;
+	pinctrl-5 = <&P8_36_pwm_pin>;
+};
+
+/* P8_37 (ZCZ ball U1) hdmi */
+P8_37_pinmux {
+	compatible = "bone-pinmux-helper";
+	status = "okay";
+	pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input", "uart", "pwm";
+	pinctrl-0 = <&P8_37_default_pin>;
+	pinctrl-1 = <&P8_37_gpio_pin>;
+	pinctrl-2 = <&P8_37_gpio_pu_pin>;
+	pinctrl-3 = <&P8_37_gpio_pd_pin>;
+	pinctrl-4 = <&P8_37_gpio_input_pin>;
+	pinctrl-5 = <&P8_37_uart_pin>;
+	pinctrl-6 = <&P8_37_pwm_pin>;
+};
+
+/* P8_38 (ZCZ ball U2) hdmi */
+P8_38_pinmux {
+	compatible = "bone-pinmux-helper";
+	status = "okay";
+	pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input", "uart", "pwm";
+	pinctrl-0 = <&P8_38_default_pin>;
+	pinctrl-1 = <&P8_38_gpio_pin>;
+	pinctrl-2 = <&P8_38_gpio_pu_pin>;
+	pinctrl-3 = <&P8_38_gpio_pd_pin>;
+	pinctrl-4 = <&P8_38_gpio_input_pin>;
+	pinctrl-5 = <&P8_38_uart_pin>;
+	pinctrl-6 = <&P8_38_pwm_pin>;
+};
+
+/* P8_39 (ZCZ ball T3) hdmi */
+P8_39_pinmux {
+	compatible = "bone-pinmux-helper";
+	status = "okay";
+	pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input", "qep", "pruout", "pruin";
+	pinctrl-0 = <&P8_39_default_pin>;
+	pinctrl-1 = <&P8_39_gpio_pin>;
+	pinctrl-2 = <&P8_39_gpio_pu_pin>;
+	pinctrl-3 = <&P8_39_gpio_pd_pin>;
+	pinctrl-4 = <&P8_39_gpio_input_pin>;
+	pinctrl-5 = <&P8_39_qep_pin>;
+	pinctrl-6 = <&P8_39_pruout_pin>;
+	pinctrl-7 = <&P8_39_pruin_pin>;
+};
+
+/* P8_40 (ZCZ ball T4) hdmi */
+P8_40_pinmux {
+	compatible = "bone-pinmux-helper";
+	status = "okay";
+	pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input", "qep", "pruout", "pruin";
+	pinctrl-0 = <&P8_40_default_pin>;
+	pinctrl-1 = <&P8_40_gpio_pin>;
+	pinctrl-2 = <&P8_40_gpio_pu_pin>;
+	pinctrl-3 = <&P8_40_gpio_pd_pin>;
+	pinctrl-4 = <&P8_40_gpio_input_pin>;
+	pinctrl-5 = <&P8_40_qep_pin>;
+	pinctrl-6 = <&P8_40_pruout_pin>;
+	pinctrl-7 = <&P8_40_pruin_pin>;
+};
+
+/* P8_41 (ZCZ ball T1) hdmi */
+P8_41_pinmux {
+	compatible = "bone-pinmux-helper";
+	status = "okay";
+	pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input", "qep", "pruout", "pruin";
+	pinctrl-0 = <&P8_41_default_pin>;
+	pinctrl-1 = <&P8_41_gpio_pin>;
+	pinctrl-2 = <&P8_41_gpio_pu_pin>;
+	pinctrl-3 = <&P8_41_gpio_pd_pin>;
+	pinctrl-4 = <&P8_41_gpio_input_pin>;
+	pinctrl-5 = <&P8_41_qep_pin>;
+	pinctrl-6 = <&P8_41_pruout_pin>;
+	pinctrl-7 = <&P8_41_pruin_pin>;
+};
+
+/* P8_42 (ZCZ ball T2) hdmi */
+P8_42_pinmux {
+	compatible = "bone-pinmux-helper";
+	status = "okay";
+	pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input", "qep", "pruout", "pruin";
+	pinctrl-0 = <&P8_42_default_pin>;
+	pinctrl-1 = <&P8_42_gpio_pin>;
+	pinctrl-2 = <&P8_42_gpio_pu_pin>;
+	pinctrl-3 = <&P8_42_gpio_pd_pin>;
+	pinctrl-4 = <&P8_42_gpio_input_pin>;
+	pinctrl-5 = <&P8_42_qep_pin>;
+	pinctrl-6 = <&P8_42_pruout_pin>;
+	pinctrl-7 = <&P8_42_pruin_pin>;
+};
+
+/* P8_43 (ZCZ ball R3) hdmi */
+P8_43_pinmux {
+	compatible = "bone-pinmux-helper";
+	status = "okay";
+	pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input", "pwm", "pruout", "pruin";
+	pinctrl-0 = <&P8_43_default_pin>;
+	pinctrl-1 = <&P8_43_gpio_pin>;
+	pinctrl-2 = <&P8_43_gpio_pu_pin>;
+	pinctrl-3 = <&P8_43_gpio_pd_pin>;
+	pinctrl-4 = <&P8_43_gpio_input_pin>;
+	pinctrl-5 = <&P8_43_pwm_pin>;
+	pinctrl-6 = <&P8_43_pruout_pin>;
+	pinctrl-7 = <&P8_43_pruin_pin>;
+};
+
+/* P8_44 (ZCZ ball R4) hdmi */
+P8_44_pinmux {
+	compatible = "bone-pinmux-helper";
+	status = "okay";
+	pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input", "pwm", "pruout", "pruin";
+	pinctrl-0 = <&P8_44_default_pin>;
+	pinctrl-1 = <&P8_44_gpio_pin>;
+	pinctrl-2 = <&P8_44_gpio_pu_pin>;
+	pinctrl-3 = <&P8_44_gpio_pd_pin>;
+	pinctrl-4 = <&P8_44_gpio_input_pin>;
+	pinctrl-5 = <&P8_44_pwm_pin>;
+	pinctrl-6 = <&P8_44_pruout_pin>;
+	pinctrl-7 = <&P8_44_pruin_pin>;
+};
+
+/* P8_45 (ZCZ ball R1) hdmi */
+P8_45_pinmux {
+	compatible = "bone-pinmux-helper";
+	status = "okay";
+	pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input", "pwm", "pruout", "pruin";
+	pinctrl-0 = <&P8_45_default_pin>;
+	pinctrl-1 = <&P8_45_gpio_pin>;
+	pinctrl-2 = <&P8_45_gpio_pu_pin>;
+	pinctrl-3 = <&P8_45_gpio_pd_pin>;
+	pinctrl-4 = <&P8_45_gpio_input_pin>;
+	pinctrl-5 = <&P8_45_pwm_pin>;
+	pinctrl-6 = <&P8_45_pruout_pin>;
+	pinctrl-7 = <&P8_45_pruin_pin>;
+};
+
+/* P8_46 (ZCZ ball R2) hdmi */
+P8_46_pinmux {
+	compatible = "bone-pinmux-helper";
+	status = "okay";
+	pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input", "pwm", "pruout", "pruin";
+	pinctrl-0 = <&P8_46_default_pin>;
+	pinctrl-1 = <&P8_46_gpio_pin>;
+	pinctrl-2 = <&P8_46_gpio_pu_pin>;
+	pinctrl-3 = <&P8_46_gpio_pd_pin>;
+	pinctrl-4 = <&P8_46_gpio_input_pin>;
+	pinctrl-5 = <&P8_46_pwm_pin>;
+	pinctrl-6 = <&P8_46_pruout_pin>;
+	pinctrl-7 = <&P8_46_pruin_pin>;
+};
+
+/************************/
+/* P9 Header */
+/************************/
+
+/* P9_01                GND */
+
+/* P9_02                GND */
+
+/* P9_03                3V3 */
+
+/* P9_04                3V3 */
+
+/* P9_05                VDD_5V */
+
+/* P9_06                VDD_5V */
+
+/* P9_07                SYS_5V */
+
+/* P9_08                SYS_5V */
+
+/* P9_09                PWR_BUT */
+
+/* P9_10                RSTn */
+
+/* P9_11 (ZCZ ball T17) */
+P9_11_pinmux {
+	compatible = "bone-pinmux-helper";
+	status = "okay";
+	pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input", "uart";
+	pinctrl-0 = <&P9_11_default_pin>;
+	pinctrl-1 = <&P9_11_gpio_pin>;
+	pinctrl-2 = <&P9_11_gpio_pu_pin>;
+	pinctrl-3 = <&P9_11_gpio_pd_pin>;
+	pinctrl-4 = <&P9_11_gpio_input_pin>;
+	pinctrl-5 = <&P9_11_uart_pin>;
+};
+
+/* P9_12 (ZCZ ball U18) */
+P9_12_pinmux {
+	compatible = "bone-pinmux-helper";
+	status = "okay";
+	pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input";
+	pinctrl-0 = <&P9_12_default_pin>;
+	pinctrl-1 = <&P9_12_gpio_pin>;
+	pinctrl-2 = <&P9_12_gpio_pu_pin>;
+	pinctrl-3 = <&P9_12_gpio_pd_pin>;
+	pinctrl-4 = <&P9_12_gpio_input_pin>;
+};
+
+/* P9_13 (ZCZ ball U17) */
+P9_13_pinmux {
+	compatible = "bone-pinmux-helper";
+	status = "okay";
+	pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input", "uart";
+	pinctrl-0 = <&P9_13_default_pin>;
+	pinctrl-1 = <&P9_13_gpio_pin>;
+	pinctrl-2 = <&P9_13_gpio_pu_pin>;
+	pinctrl-3 = <&P9_13_gpio_pd_pin>;
+	pinctrl-4 = <&P9_13_gpio_input_pin>;
+	pinctrl-5 = <&P9_13_uart_pin>;
+};
+
+/* P9_14 (ZCZ ball U14) */
+P9_14_pinmux {
+	compatible = "bone-pinmux-helper";
+	status = "okay";
+	pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input", "pwm";
+	pinctrl-0 = <&P9_14_default_pin>;
+	pinctrl-1 = <&P9_14_gpio_pin>;
+	pinctrl-2 = <&P9_14_gpio_pu_pin>;
+	pinctrl-3 = <&P9_14_gpio_pd_pin>;
+	pinctrl-4 = <&P9_14_gpio_input_pin>;
+	pinctrl-5 = <&P9_14_pwm_pin>;
+};
+
+/* P9_15 (ZCZ ball R13) */
+P9_15_pinmux {
+	compatible = "bone-pinmux-helper";
+	status = "okay";
+	pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input", "pwm";
+	pinctrl-0 = <&P9_15_default_pin>;
+	pinctrl-1 = <&P9_15_gpio_pin>;
+	pinctrl-2 = <&P9_15_gpio_pu_pin>;
+	pinctrl-3 = <&P9_15_gpio_pd_pin>;
+	pinctrl-4 = <&P9_15_gpio_input_pin>;
+	pinctrl-5 = <&P9_15_pwm_pin>;
+};
+
+/* P9_16 (ZCZ ball T14) */
+P9_16_pinmux {
+	compatible = "bone-pinmux-helper";
+	status = "okay";
+	pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input", "pwm";
+	pinctrl-0 = <&P9_16_default_pin>;
+	pinctrl-1 = <&P9_16_gpio_pin>;
+	pinctrl-2 = <&P9_16_gpio_pu_pin>;
+	pinctrl-3 = <&P9_16_gpio_pd_pin>;
+	pinctrl-4 = <&P9_16_gpio_input_pin>;
+	pinctrl-5 = <&P9_16_pwm_pin>;
+};
+
+/* P9_17 (ZCZ ball A16) */
+P9_17_pinmux {
+	compatible = "bone-pinmux-helper";
+	status = "okay";
+	pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input", "spi_cs", "i2c", "pwm", "pru_uart";
+	pinctrl-0 = <&P9_17_default_pin>;
+	pinctrl-1 = <&P9_17_gpio_pin>;
+	pinctrl-2 = <&P9_17_gpio_pu_pin>;
+	pinctrl-3 = <&P9_17_gpio_pd_pin>;
+	pinctrl-4 = <&P9_17_gpio_input_pin>;
+	pinctrl-5 = <&P9_17_spi_cs_pin>;
+	pinctrl-6 = <&P9_17_i2c_pin>;
+	pinctrl-7 = <&P9_17_pwm_pin>;
+	pinctrl-8 = <&P9_17_pru_uart_pin>;
+};
+
+/* P9_18 (ZCZ ball B16) */
+P9_18_pinmux {
+	compatible = "bone-pinmux-helper";
+	status = "okay";
+	pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input", "spi", "i2c", "pwm", "pru_uart";
+	pinctrl-0 = <&P9_18_default_pin>;
+	pinctrl-1 = <&P9_18_gpio_pin>;
+	pinctrl-2 = <&P9_18_gpio_pu_pin>;
+	pinctrl-3 = <&P9_18_gpio_pd_pin>;
+	pinctrl-4 = <&P9_18_gpio_input_pin>;
+	pinctrl-5 = <&P9_18_spi_pin>;
+	pinctrl-6 = <&P9_18_i2c_pin>;
+	pinctrl-7 = <&P9_18_pwm_pin>;
+	pinctrl-8 = <&P9_18_pru_uart_pin>;
+};
+
+/* P9_19 (ZCZ ball D17) i2c */
+P9_19_pinmux {
+	compatible = "bone-pinmux-helper";
+	status = "okay";
+	pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input", "spi_cs", "can", "i2c", "pru_uart", "timer";
+	pinctrl-0 = <&P9_19_default_pin>;
+	pinctrl-1 = <&P9_19_gpio_pin>;
+	pinctrl-2 = <&P9_19_gpio_pu_pin>;
+	pinctrl-3 = <&P9_19_gpio_pd_pin>;
+	pinctrl-4 = <&P9_19_gpio_input_pin>;
+	pinctrl-5 = <&P9_19_spi_cs_pin>;
+	pinctrl-6 = <&P9_19_can_pin>;
+	pinctrl-7 = <&P9_19_i2c_pin>;
+	pinctrl-8 = <&P9_19_pru_uart_pin>;
+	pinctrl-9 = <&P9_19_timer_pin>;
+};
+
+/* P9_20 (ZCZ ball D18) i2c */
+P9_20_pinmux {
+	compatible = "bone-pinmux-helper";
+	status = "okay";
+	pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input", "spi_cs", "can", "i2c", "pru_uart", "timer";
+	pinctrl-0 = <&P9_20_default_pin>;
+	pinctrl-1 = <&P9_20_gpio_pin>;
+	pinctrl-2 = <&P9_20_gpio_pu_pin>;
+	pinctrl-3 = <&P9_20_gpio_pd_pin>;
+	pinctrl-4 = <&P9_20_gpio_input_pin>;
+	pinctrl-5 = <&P9_20_spi_cs_pin>;
+	pinctrl-6 = <&P9_20_can_pin>;
+	pinctrl-7 = <&P9_20_i2c_pin>;
+	pinctrl-8 = <&P9_20_pru_uart_pin>;
+	pinctrl-9 = <&P9_20_timer_pin>;
+};
+
+/* P9_21 (ZCZ ball B17) */
+P9_21_pinmux {
+	compatible = "bone-pinmux-helper";
+	status = "okay";
+	pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input", "spi", "uart", "i2c", "pwm", "pru_uart";
+	pinctrl-0 = <&P9_21_default_pin>;
+	pinctrl-1 = <&P9_21_gpio_pin>;
+	pinctrl-2 = <&P9_21_gpio_pu_pin>;
+	pinctrl-3 = <&P9_21_gpio_pd_pin>;
+	pinctrl-4 = <&P9_21_gpio_input_pin>;
+	pinctrl-5 = <&P9_21_spi_pin>;
+	pinctrl-6 = <&P9_21_uart_pin>;
+	pinctrl-7 = <&P9_21_i2c_pin>;
+	pinctrl-8 = <&P9_21_pwm_pin>;
+	pinctrl-9 = <&P9_21_pru_uart_pin>;
+};
+
+/* P9_22 (ZCZ ball A17) */
+P9_22_pinmux {
+	compatible = "bone-pinmux-helper";
+	status = "okay";
+	pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input", "spi_sclk", "uart", "i2c", "pwm", "pru_uart";
+	pinctrl-0 = <&P9_22_default_pin>;
+	pinctrl-1 = <&P9_22_gpio_pin>;
+	pinctrl-2 = <&P9_22_gpio_pu_pin>;
+	pinctrl-3 = <&P9_22_gpio_pd_pin>;
+	pinctrl-4 = <&P9_22_gpio_input_pin>;
+	pinctrl-5 = <&P9_22_spi_sclk_pin>;
+	pinctrl-6 = <&P9_22_uart_pin>;
+	pinctrl-7 = <&P9_22_i2c_pin>;
+	pinctrl-8 = <&P9_22_pwm_pin>;
+	pinctrl-9 = <&P9_22_pru_uart_pin>;
+};
+
+/* P9_23 (ZCZ ball V14) */
+P9_23_pinmux {
+	compatible = "bone-pinmux-helper";
+	status = "okay";
+	pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input", "pwm";
+	pinctrl-0 = <&P9_23_default_pin>;
+	pinctrl-1 = <&P9_23_gpio_pin>;
+	pinctrl-2 = <&P9_23_gpio_pu_pin>;
+	pinctrl-3 = <&P9_23_gpio_pd_pin>;
+	pinctrl-4 = <&P9_23_gpio_input_pin>;
+	pinctrl-5 = <&P9_23_pwm_pin>;
+};
+
+/* P9_24 (ZCZ ball D15) */
+P9_24_pinmux {
+	compatible = "bone-pinmux-helper";
+	status = "okay";
+	pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input", "uart", "can", "i2c", "pru_uart", "pruin";
+	pinctrl-0 = <&P9_24_default_pin>;
+	pinctrl-1 = <&P9_24_gpio_pin>;
+	pinctrl-2 = <&P9_24_gpio_pu_pin>;
+	pinctrl-3 = <&P9_24_gpio_pd_pin>;
+	pinctrl-4 = <&P9_24_gpio_input_pin>;
+	pinctrl-5 = <&P9_24_uart_pin>;
+	pinctrl-6 = <&P9_24_can_pin>;
+	pinctrl-7 = <&P9_24_i2c_pin>;
+	pinctrl-8 = <&P9_24_pru_uart_pin>;
+	pinctrl-9 = <&P9_24_pruin_pin>;
+};
+
+/* P9_25 (ZCZ ball A14) audio */
+P9_25_pinmux {
+	compatible = "bone-pinmux-helper";
+	status = "okay";
+	pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input", "qep", "pruout", "pruin";
+	pinctrl-0 = <&P9_25_default_pin>;
+	pinctrl-1 = <&P9_25_gpio_pin>;
+	pinctrl-2 = <&P9_25_gpio_pu_pin>;
+	pinctrl-3 = <&P9_25_gpio_pd_pin>;
+	pinctrl-4 = <&P9_25_gpio_input_pin>;
+	pinctrl-5 = <&P9_25_qep_pin>;
+	pinctrl-6 = <&P9_25_pruout_pin>;
+	pinctrl-7 = <&P9_25_pruin_pin>;
+};
+
+/* P9_26 (ZCZ ball D16) */
+P9_26_pinmux {
+	compatible = "bone-pinmux-helper";
+	status = "okay";
+	pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input", "uart", "can", "i2c", "pru_uart", "pruin";
+	pinctrl-0 = <&P9_26_default_pin>;
+	pinctrl-1 = <&P9_26_gpio_pin>;
+	pinctrl-2 = <&P9_26_gpio_pu_pin>;
+	pinctrl-3 = <&P9_26_gpio_pd_pin>;
+	pinctrl-4 = <&P9_26_gpio_input_pin>;
+	pinctrl-5 = <&P9_26_uart_pin>;
+	pinctrl-6 = <&P9_26_can_pin>;
+	pinctrl-7 = <&P9_26_i2c_pin>;
+	pinctrl-8 = <&P9_26_pru_uart_pin>;
+	pinctrl-9 = <&P9_26_pruin_pin>;
+};
+
+/* P9_27 (ZCZ ball C13) */
+P9_27_pinmux {
+	compatible = "bone-pinmux-helper";
+	status = "okay";
+	pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input", "qep", "pruout", "pruin";
+	pinctrl-0 = <&P9_27_default_pin>;
+	pinctrl-1 = <&P9_27_gpio_pin>;
+	pinctrl-2 = <&P9_27_gpio_pu_pin>;
+	pinctrl-3 = <&P9_27_gpio_pd_pin>;
+	pinctrl-4 = <&P9_27_gpio_input_pin>;
+	pinctrl-5 = <&P9_27_qep_pin>;
+	pinctrl-6 = <&P9_27_pruout_pin>;
+	pinctrl-7 = <&P9_27_pruin_pin>;
+};
+
+/* P9_28 (ZCZ ball C12) audio */
+P9_28_pinmux {
+	compatible = "bone-pinmux-helper";
+	status = "okay";
+	pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input", "spi_cs", "pwm", "pwm2", "pruout", "pruin";
+	pinctrl-0 = <&P9_28_default_pin>;
+	pinctrl-1 = <&P9_28_gpio_pin>;
+	pinctrl-2 = <&P9_28_gpio_pu_pin>;
+	pinctrl-3 = <&P9_28_gpio_pd_pin>;
+	pinctrl-4 = <&P9_28_gpio_input_pin>;
+	pinctrl-5 = <&P9_28_spi_cs_pin>;
+	pinctrl-6 = <&P9_28_pwm_pin>;
+	pinctrl-7 = <&P9_28_pwm2_pin>;
+	pinctrl-8 = <&P9_28_pruout_pin>;
+	pinctrl-9 = <&P9_28_pruin_pin>;
+};
+
+/* P9_29 (ZCZ ball B13) audio */
+P9_29_pinmux {
+	compatible = "bone-pinmux-helper";
+	status = "okay";
+	pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input", "spi", "pwm", "pruout", "pruin";
+	pinctrl-0 = <&P9_29_default_pin>;
+	pinctrl-1 = <&P9_29_gpio_pin>;
+	pinctrl-2 = <&P9_29_gpio_pu_pin>;
+	pinctrl-3 = <&P9_29_gpio_pd_pin>;
+	pinctrl-4 = <&P9_29_gpio_input_pin>;
+	pinctrl-5 = <&P9_29_spi_pin>;
+	pinctrl-6 = <&P9_29_pwm_pin>;
+	pinctrl-7 = <&P9_29_pruout_pin>;
+	pinctrl-8 = <&P9_29_pruin_pin>;
+};
+
+/* P9_30 (ZCZ ball D12) */
+P9_30_pinmux {
+	compatible = "bone-pinmux-helper";
+	status = "okay";
+	pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input", "spi", "pwm", "pruout", "pruin";
+	pinctrl-0 = <&P9_30_default_pin>;
+	pinctrl-1 = <&P9_30_gpio_pin>;
+	pinctrl-2 = <&P9_30_gpio_pu_pin>;
+	pinctrl-3 = <&P9_30_gpio_pd_pin>;
+	pinctrl-4 = <&P9_30_gpio_input_pin>;
+	pinctrl-5 = <&P9_30_spi_pin>;
+	pinctrl-6 = <&P9_30_pwm_pin>;
+	pinctrl-7 = <&P9_30_pruout_pin>;
+	pinctrl-8 = <&P9_30_pruin_pin>;
+};
+
+/* P9_31 (ZCZ ball A13) audio */
+P9_31_pinmux {
+	compatible = "bone-pinmux-helper";
+	status = "okay";
+	pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input", "spi_sclk", "pwm", "pruout", "pruin";
+	pinctrl-0 = <&P9_31_default_pin>;
+	pinctrl-1 = <&P9_31_gpio_pin>;
+	pinctrl-2 = <&P9_31_gpio_pu_pin>;
+	pinctrl-3 = <&P9_31_gpio_pd_pin>;
+	pinctrl-4 = <&P9_31_gpio_input_pin>;
+	pinctrl-5 = <&P9_31_spi_sclk_pin>;
+	pinctrl-6 = <&P9_31_pwm_pin>;
+	pinctrl-7 = <&P9_31_pruout_pin>;
+	pinctrl-8 = <&P9_31_pruin_pin>;
+};
+
+/* P9_32                VADC */
+
+/* P9_33 (ZCZ ball C8)  AIN4         */
+
+/* P9_34                AGND */
+
+/* P9_35 (ZCZ ball A8)  AIN6         */
+
+/* P9_36 (ZCZ ball B8)  AIN5         */
+
+/* P9_37 (ZCZ ball B7)  AIN2         */
+
+/* P9_38 (ZCZ ball A7)  AIN3         */
+
+/* P9_39 (ZCZ ball B6)  AIN0         */
+
+/* P9_40 (ZCZ ball C7)  AIN1         */
+
+/* P9_41 (ZCZ ball D14) */
+P9_41_pinmux {
+	compatible = "bone-pinmux-helper";
+	status = "okay";
+	pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input", "timer", "pruin";
+	pinctrl-0 = <&P9_41_default_pin>;
+	pinctrl-1 = <&P9_41_gpio_pin>;
+	pinctrl-2 = <&P9_41_gpio_pu_pin>;
+	pinctrl-3 = <&P9_41_gpio_pd_pin>;
+	pinctrl-4 = <&P9_41_gpio_input_pin>;
+	pinctrl-5 = <&P9_41_timer_pin>;
+	pinctrl-6 = <&P9_41_pruin_pin>;
+};
+
+/* P9_41.1 */
+/* P9_91 (ZCZ ball D13) */
+P9_91_pinmux {
+	compatible = "bone-pinmux-helper";
+	status = "okay";
+	pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input", "qep", "pruout", "pruin";
+	pinctrl-0 = <&P9_91_default_pin>;
+	pinctrl-1 = <&P9_91_gpio_pin>;
+	pinctrl-2 = <&P9_91_gpio_pu_pin>;
+	pinctrl-3 = <&P9_91_gpio_pd_pin>;
+	pinctrl-4 = <&P9_91_gpio_input_pin>;
+	pinctrl-5 = <&P9_91_qep_pin>;
+	pinctrl-6 = <&P9_91_pruout_pin>;
+	pinctrl-7 = <&P9_91_pruin_pin>;
+};
+
+/* P9_42 (ZCZ ball C18) */
+P9_42_pinmux {
+	compatible = "bone-pinmux-helper";
+	status = "okay";
+	pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input", "spi_cs", "spi_sclk", "uart", "pwm", "pru_ecap";
+	pinctrl-0 = <&P9_42_default_pin>;
+	pinctrl-1 = <&P9_42_gpio_pin>;
+	pinctrl-2 = <&P9_42_gpio_pu_pin>;
+	pinctrl-3 = <&P9_42_gpio_pd_pin>;
+	pinctrl-4 = <&P9_42_gpio_input_pin>;
+	pinctrl-5 = <&P9_42_spi_cs_pin>;
+	pinctrl-6 = <&P9_42_spi_sclk_pin>;
+	pinctrl-7 = <&P9_42_uart_pin>;
+	pinctrl-8 = <&P9_42_pwm_pin>;
+	pinctrl-9 = <&P9_42_pru_ecap_pin>;
+};
+
+/* P9_42.1 */
+/* P9_92 (ZCZ ball B12) */
+P9_92_pinmux {
+	compatible = "bone-pinmux-helper";
+	status = "okay";
+	pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input", "qep", "pruout", "pruin";
+	pinctrl-0 = <&P9_92_default_pin>;
+	pinctrl-1 = <&P9_92_gpio_pin>;
+	pinctrl-2 = <&P9_92_gpio_pu_pin>;
+	pinctrl-3 = <&P9_92_gpio_pd_pin>;
+	pinctrl-4 = <&P9_92_gpio_input_pin>;
+	pinctrl-5 = <&P9_92_qep_pin>;
+	pinctrl-6 = <&P9_92_pruout_pin>;
+	pinctrl-7 = <&P9_92_pruin_pin>;
+};
+
+/* P9_43                GND */
+
+/* P9_44                GND */
+
+/* P9_45                GND */
+
+/* P9_46                GND */
+
+/************************/
+/* Special */
+/************************/
+
+
+cape-universal {
+	compatible = "gpio-of-helper";
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <>;
+
+	P8_03 {
+		gpio-name = "P8_03";
+		gpio = <&gpio1 6 0>;
+		input;
+		dir-changeable;
+	};
+
+	P8_04 {
+		gpio-name = "P8_04";
+		gpio = <&gpio1 7 0>;
+		input;
+		dir-changeable;
+	};
+
+	P8_05 {
+		gpio-name = "P8_05";
+		gpio = <&gpio1 2 0>;
+		input;
+		dir-changeable;
+	};
+
+	P8_06 {
+		gpio-name = "P8_06";
+		gpio = <&gpio1 3 0>;
+		input;
+		dir-changeable;
+	};
+
+	P8_07 {
+		gpio-name = "P8_07";
+		gpio = <&gpio2 2 0>;
+		input;
+		dir-changeable;
+	};
+
+	P8_08 {
+		gpio-name = "P8_08";
+		gpio = <&gpio2 3 0>;
+		input;
+		dir-changeable;
+	};
+
+	P8_09 {
+		gpio-name = "P8_09";
+		gpio = <&gpio2 5 0>;
+		input;
+		dir-changeable;
+	};
+
+	P8_10 {
+		gpio-name = "P8_10";
+		gpio = <&gpio2 4 0>;
+		input;
+		dir-changeable;
+	};
+
+	P8_11 {
+		gpio-name = "P8_11";
+		gpio = <&gpio1 13 0>;
+		input;
+		dir-changeable;
+	};
+
+	P8_12 {
+		gpio-name = "P8_12";
+		gpio = <&gpio1 12 0>;
+		input;
+		dir-changeable;
+	};
+
+	P8_13 {
+		gpio-name = "P8_13";
+		gpio = <&gpio0 23 0>;
+		input;
+		dir-changeable;
+	};
+
+	P8_14 {
+		gpio-name = "P8_14";
+		gpio = <&gpio0 26 0>;
+		input;
+		dir-changeable;
+	};
+
+	P8_15 {
+		gpio-name = "P8_15";
+		gpio = <&gpio1 15 0>;
+		input;
+		dir-changeable;
+	};
+
+	P8_16 {
+		gpio-name = "P8_16";
+		gpio = <&gpio1 14 0>;
+		input;
+		dir-changeable;
+	};
+
+	P8_17 {
+		gpio-name = "P8_17";
+		gpio = <&gpio0 27 0>;
+		input;
+		dir-changeable;
+	};
+
+	P8_18 {
+		gpio-name = "P8_18";
+		gpio = <&gpio2 1 0>;
+		input;
+		dir-changeable;
+	};
+
+	P8_19 {
+		gpio-name = "P8_19";
+		gpio = <&gpio0 22 0>;
+		input;
+		dir-changeable;
+	};
+
+	P8_20 {
+		gpio-name = "P8_20";
+		gpio = <&gpio1 31 0>;
+		input;
+		dir-changeable;
+	};
+
+	P8_21 {
+		gpio-name = "P8_21";
+		gpio = <&gpio1 30 0>;
+		input;
+		dir-changeable;
+	};
+
+	P8_22 {
+		gpio-name = "P8_22";
+		gpio = <&gpio1 5 0>;
+		input;
+		dir-changeable;
+	};
+
+	P8_23 {
+		gpio-name = "P8_23";
+		gpio = <&gpio1 4 0>;
+		input;
+		dir-changeable;
+	};
+
+	P8_24 {
+		gpio-name = "P8_24";
+		gpio = <&gpio1 1 0>;
+		input;
+		dir-changeable;
+	};
+
+	P8_25 {
+		gpio-name = "P8_25";
+		gpio = <&gpio1 0 0>;
+		input;
+		dir-changeable;
+	};
+
+	P8_26 {
+		gpio-name = "P8_26";
+		gpio = <&gpio1 29 0>;
+		input;
+		dir-changeable;
+	};
+
+	P8_27 {
+		gpio-name = "P8_27";
+		gpio = <&gpio2 22 0>;
+		input;
+		dir-changeable;
+	};
+
+	P8_28 {
+		gpio-name = "P8_28";
+		gpio = <&gpio2 24 0>;
+		input;
+		dir-changeable;
+	};
+
+	P8_29 {
+		gpio-name = "P8_29";
+		gpio = <&gpio2 23 0>;
+		input;
+		dir-changeable;
+	};
+
+	P8_30 {
+		gpio-name = "P8_30";
+		gpio = <&gpio2 25 0>;
+		input;
+		dir-changeable;
+	};
+
+	P8_31 {
+		gpio-name = "P8_31";
+		gpio = <&gpio0 10 0>;
+		input;
+		dir-changeable;
+	};
+
+	P8_32 {
+		gpio-name = "P8_32";
+		gpio = <&gpio0 11 0>;
+		input;
+		dir-changeable;
+	};
+
+	P8_33 {
+		gpio-name = "P8_33";
+		gpio = <&gpio0 9 0>;
+		input;
+		dir-changeable;
+	};
+
+	P8_34 {
+		gpio-name = "P8_34";
+		gpio = <&gpio2 17 0>;
+		input;
+		dir-changeable;
+	};
+
+	P8_35 {
+		gpio-name = "P8_35";
+		gpio = <&gpio0 8 0>;
+		input;
+		dir-changeable;
+	};
+
+	P8_36 {
+		gpio-name = "P8_36";
+		gpio = <&gpio2 16 0>;
+		input;
+		dir-changeable;
+	};
+
+	P8_37 {
+		gpio-name = "P8_37";
+		gpio = <&gpio2 14 0>;
+		input;
+		dir-changeable;
+	};
+
+	P8_38 {
+		gpio-name = "P8_38";
+		gpio = <&gpio2 15 0>;
+		input;
+		dir-changeable;
+	};
+
+	P8_39 {
+		gpio-name = "P8_39";
+		gpio = <&gpio2 12 0>;
+		input;
+		dir-changeable;
+	};
+
+	P8_40 {
+		gpio-name = "P8_40";
+		gpio = <&gpio2 13 0>;
+		input;
+		dir-changeable;
+	};
+
+	P8_41 {
+		gpio-name = "P8_41";
+		gpio = <&gpio2 10 0>;
+		input;
+		dir-changeable;
+	};
+
+	P8_42 {
+		gpio-name = "P8_42";
+		gpio = <&gpio2 11 0>;
+		input;
+		dir-changeable;
+	};
+
+	P8_43 {
+		gpio-name = "P8_43";
+		gpio = <&gpio2 8 0>;
+		input;
+		dir-changeable;
+	};
+
+	P8_44 {
+		gpio-name = "P8_44";
+		gpio = <&gpio2 9 0>;
+		input;
+		dir-changeable;
+	};
+
+	P8_45 {
+		gpio-name = "P8_45";
+		gpio = <&gpio2 6 0>;
+		input;
+		dir-changeable;
+	};
+
+	P8_46 {
+		gpio-name = "P8_46";
+		gpio = <&gpio2 7 0>;
+		input;
+		dir-changeable;
+	};
+
+	P9_11 {
+		gpio-name = "P9_11";
+		gpio = <&gpio0 30 0>;
+		input;
+		dir-changeable;
+	};
+
+	P9_12 {
+		gpio-name = "P9_12";
+		gpio = <&gpio1 28 0>;
+		input;
+		dir-changeable;
+	};
+
+	P9_13 {
+		gpio-name = "P9_13";
+		gpio = <&gpio0 31 0>;
+		input;
+		dir-changeable;
+	};
+
+	P9_14 {
+		gpio-name = "P9_14";
+		gpio = <&gpio1 18 0>;
+		input;
+		dir-changeable;
+	};
+
+	P9_15 {
+		gpio-name = "P9_15";
+		gpio = <&gpio1 16 0>;
+		input;
+		dir-changeable;
+	};
+
+	P9_16 {
+		gpio-name = "P9_16";
+		gpio = <&gpio1 19 0>;
+		input;
+		dir-changeable;
+	};
+
+	P9_17 {
+		gpio-name = "P9_17";
+		gpio = <&gpio0 5 0>;
+		input;
+		dir-changeable;
+	};
+
+	P9_18 {
+		gpio-name = "P9_18";
+		gpio = <&gpio0 4 0>;
+		input;
+		dir-changeable;
+	};
+
+	P9_19 {
+		gpio-name = "P9_19";
+		gpio = <&gpio0 13 0>;
+		input;
+		dir-changeable;
+	};
+
+	P9_20 {
+		gpio-name = "P9_20";
+		gpio = <&gpio0 12 0>;
+		input;
+		dir-changeable;
+	};
+
+	P9_21 {
+		gpio-name = "P9_21";
+		gpio = <&gpio0 3 0>;
+		input;
+		dir-changeable;
+	};
+
+	P9_22 {
+		gpio-name = "P9_22";
+		gpio = <&gpio0 2 0>;
+		input;
+		dir-changeable;
+	};
+
+	P9_23 {
+		gpio-name = "P9_23";
+		gpio = <&gpio1 17 0>;
+		input;
+		dir-changeable;
+	};
+
+	P9_24 {
+		gpio-name = "P9_24";
+		gpio = <&gpio0 15 0>;
+		input;
+		dir-changeable;
+	};
+
+	P9_25 {
+		gpio-name = "P9_25";
+		gpio = <&gpio3 21 0>;
+		input;
+		dir-changeable;
+	};
+
+	P9_26 {
+		gpio-name = "P9_26";
+		gpio = <&gpio0 14 0>;
+		input;
+		dir-changeable;
+	};
+
+	P9_27 {
+		gpio-name = "P9_27";
+		gpio = <&gpio3 19 0>;
+		input;
+		dir-changeable;
+	};
+
+	P9_28 {
+		gpio-name = "P9_28";
+		gpio = <&gpio3 17 0>;
+		input;
+		dir-changeable;
+	};
+
+	P9_29 {
+		gpio-name = "P9_29";
+		gpio = <&gpio3 15 0>;
+		input;
+		dir-changeable;
+	};
+
+	P9_30 {
+		gpio-name = "P9_30";
+		gpio = <&gpio3 16 0>;
+		input;
+		dir-changeable;
+	};
+
+	P9_31 {
+		gpio-name = "P9_31";
+		gpio = <&gpio3 14 0>;
+		input;
+		dir-changeable;
+	};
+
+	P9_41 {
+		gpio-name = "P9_41";
+		gpio = <&gpio0 20 0>;
+		input;
+		dir-changeable;
+	};
+
+	P9_91 {
+		gpio-name = "P9_91";
+		gpio = <&gpio3 20 0>;
+		input;
+		dir-changeable;
+	};
+
+	P9_42 {
+		gpio-name = "P9_42";
+		gpio = <&gpio0 7 0>;
+		input;
+		dir-changeable;
+	};
+
+	P9_92 {
+		gpio-name = "P9_92";
+		gpio = <&gpio3 18 0>;
+		input;
+		dir-changeable;
+	};
+
+};
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/tools/pinmux-generator/BeagleBone_Black.sh b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/tools/pinmux-generator/BeagleBone_Black.sh
new file mode 100644
index 0000000000000000000000000000000000000000..693881a1002b80b15a8176574f74609edc41e719
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/tools/pinmux-generator/BeagleBone_Black.sh
@@ -0,0 +1,208 @@
+#!/bin/bash
+
+source $(dirname "$0")/lib/pinmux.sh
+
+file="BeagleBone_Black"
+
+generate_timer="enable"
+generate_spi="enable"
+
+echo "" > ${file}.dts
+echo "" >${file}-pinmux.dts
+echo "" >${file}-gpio.dts
+echo "" >${file}_config-pin.txt
+
+#BeagleBone Black
+gpio_index="7"
+
+#pcbpin="P9_42" ; ball="C18" ; find_ball
+#exit 2
+
+msg="/************************/" ; echo_both
+msg="/* P8 Header */" ; echo_both
+msg="/************************/" ; echo_both
+msg="" ; echo_both
+
+pcbpin="P8_01" ; label_pin="gnd" ; label_info="GND" ; echo_label
+pcbpin="P8_02" ; label_pin="gnd" ; label_info="GND" ; echo_label
+
+msg="" ; echo_both
+
+gpio_index="2"
+pcbpin="P8_03" ; ball="R9" ; default_mode="7" ; cp_default="emmc" ; use_name="emmc" ; cp_default="emmc" ; find_ball
+pcbpin="P8_04" ; ball="T9" ; default_mode="7" ; cp_default="emmc" ; use_name="emmc" ; cp_default="emmc" ; find_ball
+pcbpin="P8_05" ; ball="R8" ; default_mode="7" ; cp_default="emmc" ; use_name="emmc" ; cp_default="emmc" ; find_ball
+pcbpin="P8_06" ; ball="T8" ; default_mode="7" ; cp_default="emmc" ; use_name="emmc" ; cp_default="emmc" ; find_ball
+pcbpin="P8_07" ; ball="R7" ; default_mode="7" ; find_ball
+pcbpin="P8_08" ; ball="T7" ; default_mode="7" ; find_ball
+pcbpin="P8_09" ; ball="T6" ; default_mode="7" ; find_ball
+pcbpin="P8_10" ; ball="U6" ; default_mode="7" ; find_ball
+gpio_index="7"
+
+pcbpin="P8_11" ; ball="R12" ; default_mode="7" ; find_ball
+pcbpin="P8_12" ; ball="T12" ; default_mode="7" ; find_ball
+
+gpio_index="6"
+pcbpin="P8_13" ; ball="T10" ; default_mode="7" ; find_ball
+pcbpin="P8_14" ; ball="T11" ; default_mode="7" ; find_ball
+gpio_index="7"
+
+pcbpin="P8_15" ; ball="U13" ; default_mode="7" ; find_ball
+pcbpin="P8_16" ; ball="V13" ; default_mode="7" ; find_ball
+
+gpio_index="6"
+pcbpin="P8_17" ; ball="U12" ; default_mode="7" ; find_ball
+gpio_index="7"
+
+pcbpin="P8_18" ; ball="V12" ; default_mode="7" ; find_ball
+
+gpio_index="6"
+pcbpin="P8_19" ; ball="U10" ; default_mode="7" ; find_ball
+gpio_index="7"
+
+pcbpin="P8_20" ; ball="V9" ; default_mode="7" ; cp_default="emmc" ; use_name="emmc" ; cp_default="emmc" ; find_ball
+pcbpin="P8_21" ; ball="U9" ; default_mode="7" ; cp_default="emmc" ; use_name="emmc" ; cp_default="emmc" ; find_ball
+
+gpio_index="2"
+pcbpin="P8_22" ; ball="V8" ; default_mode="7" ; cp_default="emmc" ; use_name="emmc" ; cp_default="emmc" ; find_ball
+pcbpin="P8_23" ; ball="U8" ; default_mode="7" ; cp_default="emmc" ; use_name="emmc" ; cp_default="emmc" ; find_ball
+pcbpin="P8_24" ; ball="V7" ; default_mode="7" ; cp_default="emmc" ; use_name="emmc" ; cp_default="emmc" ; find_ball
+pcbpin="P8_25" ; ball="U7" ; default_mode="7" ; cp_default="emmc" ; use_name="emmc" ; cp_default="emmc" ; find_ball
+gpio_index="7"
+
+gpio_index="1"
+pcbpin="P8_26" ; ball="V6" ; default_mode="7" ; find_ball
+gpio_index="7"
+
+pcbpin="P8_27" ; ball="U5" ; default_mode="7" ; cp_default="hdmi" ; use_name="hdmi" ; default_name="hdmi" ; find_ball
+pcbpin="P8_28" ; ball="V5" ; default_mode="7" ; cp_default="hdmi" ; use_name="hdmi" ; default_name="hdmi" ; find_ball
+pcbpin="P8_29" ; ball="R5" ; default_mode="7" ; cp_default="hdmi" ; use_name="hdmi" ; default_name="hdmi" ; find_ball
+pcbpin="P8_30" ; ball="R6" ; default_mode="7" ; cp_default="hdmi" ; use_name="hdmi" ; default_name="hdmi" ; find_ball
+pcbpin="P8_31" ; ball="V4" ; default_mode="7" ; cp_default="hdmi" ; use_name="hdmi" ; default_name="hdmi" ; find_ball
+
+gpio_index="6"
+pcbpin="P8_32" ; ball="T5" ; default_mode="7" ; cp_default="hdmi" ; use_name="hdmi" ; default_name="hdmi" ; find_ball
+pcbpin="P8_33" ; ball="V3" ; default_mode="7" ; cp_default="hdmi" ; use_name="hdmi" ; default_name="hdmi" ; find_ball
+pcbpin="P8_34" ; ball="U4" ; default_mode="7" ; cp_default="hdmi" ; use_name="hdmi" ; default_name="hdmi" ; find_ball
+pcbpin="P8_35" ; ball="V2" ; default_mode="7" ; cp_default="hdmi" ; use_name="hdmi" ; default_name="hdmi" ; find_ball
+pcbpin="P8_36" ; ball="U3" ; default_mode="7" ; cp_default="hdmi" ; use_name="hdmi" ; default_name="hdmi" ; find_ball
+gpio_index="7"
+
+pcbpin="P8_37" ; ball="U1" ; default_mode="7" ; cp_default="hdmi" ; use_name="hdmi" ; default_name="hdmi" ; find_ball
+pcbpin="P8_38" ; ball="U2" ; default_mode="7" ; cp_default="hdmi" ; use_name="hdmi" ; default_name="hdmi" ; find_ball
+pcbpin="P8_39" ; ball="T3" ; default_mode="7" ; cp_default="hdmi" ; use_name="hdmi" ; default_name="hdmi" ; find_ball
+pcbpin="P8_40" ; ball="T4" ; default_mode="7" ; cp_default="hdmi" ; use_name="hdmi" ; default_name="hdmi" ; find_ball
+
+gpio_index="6"
+pcbpin="P8_41" ; ball="T1" ; default_mode="7" ; cp_default="hdmi" ; use_name="hdmi" ; default_name="hdmi" ; find_ball
+pcbpin="P8_42" ; ball="T2" ; default_mode="7" ; cp_default="hdmi" ; use_name="hdmi" ; default_name="hdmi" ; find_ball
+pcbpin="P8_43" ; ball="R3" ; default_mode="7" ; cp_default="hdmi" ; use_name="hdmi" ; default_name="hdmi" ; find_ball
+pcbpin="P8_44" ; ball="R4" ; default_mode="7" ; cp_default="hdmi" ; use_name="hdmi" ; default_name="hdmi" ; find_ball
+pcbpin="P8_45" ; ball="R1" ; default_mode="7" ; cp_default="hdmi" ; use_name="hdmi" ; default_name="hdmi" ; find_ball
+pcbpin="P8_46" ; ball="R2" ; default_mode="7" ; cp_default="hdmi" ; use_name="hdmi" ; default_name="hdmi" ; find_ball
+gpio_index="7"
+
+msg="/************************/" ; echo_both
+msg="/* P9 Header */" ; echo_both
+msg="/************************/" ; echo_both ; msg="" ; echo_both
+
+pcbpin="P9_01" ; label_pin="gnd" ; label_info="GND" ; echo_label
+pcbpin="P9_02" ; label_pin="gnd" ; label_info="GND" ; echo_label
+
+pcbpin="P9_03" ; label_pin="power" ; label_info="3V3" ; echo_label
+pcbpin="P9_04" ; label_pin="power" ; label_info="3V3" ; echo_label
+
+pcbpin="P9_05" ; label_pin="power" ; label_info="VDD_5V" ; echo_label
+pcbpin="P9_06" ; label_pin="power" ; label_info="VDD_5V" ; echo_label
+
+pcbpin="P9_07" ; label_pin="power" ; label_info="SYS_5V" ; echo_label
+pcbpin="P9_08" ; label_pin="power" ; label_info="SYS_5V" ; echo_label
+
+pcbpin="P9_09" ; label_pin="system" ; label_info="PWR_BUT" ; echo_label
+pcbpin="P9_10" ; label_pin="system" ; label_info="RSTn" ; echo_label
+
+pcbpin="P9_11" ; ball="T17" ; default_mode="7" ; find_ball
+pcbpin="P9_12" ; ball="U18" ; default_mode="7" ; find_ball
+pcbpin="P9_13" ; ball="U17" ; default_mode="7" ; find_ball
+pcbpin="P9_14" ; ball="U14" ; default_mode="7" ; find_ball
+pcbpin="P9_15" ; ball="R13" ; default_mode="7" ; find_ball
+pcbpin="P9_16" ; ball="T14" ; default_mode="7" ; find_ball
+pcbpin="P9_17" ; ball="A16" ; default_mode="7" ; find_ball
+pcbpin="P9_18" ; ball="B16" ; default_mode="7" ; find_ball
+
+pcbpin="P9_19" ; ball="D17" ; default_mode="3" ; cp_default="i2c" ; find_ball
+pcbpin="P9_20" ; ball="D18" ; default_mode="3" ; cp_default="i2c" ; find_ball
+
+pcbpin="P9_21" ; ball="B17" ; default_mode="7" ; find_ball
+pcbpin="P9_22" ; ball="A17" ; default_mode="7" ; find_ball
+pcbpin="P9_23" ; ball="V14" ; default_mode="7" ; find_ball
+
+gpio_index="6"
+pcbpin="P9_24" ; ball="D15" ; default_mode="7" ; find_ball
+gpio_index="7"
+
+pcbpin="P9_25" ; ball="A14" ; default_mode="7" ; cp_default="audio" ; use_name="audio" ; default_name="audio" ; find_ball
+
+gpio_index="6"
+pcbpin="P9_26" ; ball="D16" ; default_mode="7" ; find_ball
+gpio_index="7"
+
+pcbpin="P9_27" ; ball="C13" ; default_mode="7" ; find_ball
+pcbpin="P9_28" ; ball="C12" ; default_mode="7" ; cp_default="audio" ; use_name="audio" ; default_name="audio" ; find_ball
+
+gpio_index="6"
+pcbpin="P9_29" ; ball="B13" ; default_mode="7" ; cp_default="audio" ; use_name="audio" ; default_name="audio" ; find_ball
+pcbpin="P9_30" ; ball="D12" ; default_mode="7" ; find_ball
+pcbpin="P9_31" ; ball="A13" ; default_mode="7" ; cp_default="audio" ; use_name="audio" ; default_name="audio" ; find_ball
+gpio_index="7"
+
+pcbpin="P9_32" ; label_pin="power" ; label_info="VADC" ; echo_label
+pcbpin="P9_33" ; ball="C8" label_pin="adc" ; label_info="AIN4" ; echo_label_analog
+pcbpin="P9_34" ; label_pin="gnd" ; label_info="AGND" ; echo_label
+pcbpin="P9_35" ; ball="A8" label_pin="adc" ; label_info="AIN6" ; echo_label_analog
+pcbpin="P9_36" ; ball="B8" label_pin="adc" ; label_info="AIN5" ; echo_label_analog
+pcbpin="P9_37" ; ball="B7" label_pin="adc" ; label_info="AIN2" ; echo_label_analog
+pcbpin="P9_38" ; ball="A7" label_pin="adc" ; label_info="AIN3" ; echo_label_analog
+pcbpin="P9_39" ; ball="B6" label_pin="adc" ; label_info="AIN0" ; echo_label_analog
+pcbpin="P9_40" ; ball="C7" label_pin="adc" ; label_info="AIN1" ; echo_label_analog
+
+gpio_index="6"
+pcbpin="P9_41" ; ball="D14" ; default_mode="7" ; find_ball
+msg="/* P9_41.1 */" ; echo_both
+
+pcbpin="P9_91" ; ball="D13" ; default_mode="7" ; find_ball
+gpio_index="7"
+
+pcbpin="P9_42" ; ball="C18" ; default_mode="7" ; find_ball
+msg="/* P9_42.1 */" ; echo_both
+pcbpin="P9_92" ; ball="B12" ; default_mode="7" ; find_ball
+
+pcbpin="P9_43" ; label_pin="gnd" ; label_info="GND" ; echo_label
+pcbpin="P9_44" ; label_pin="gnd" ; label_info="GND" ; echo_label
+pcbpin="P9_45" ; label_pin="gnd" ; label_info="GND" ; echo_label
+pcbpin="P9_46" ; label_pin="gnd" ; label_info="GND" ; echo_label
+
+msg="/************************/" ; echo_both
+msg="/* Special */" ; echo_both
+msg="/************************/" ; echo_both ; msg="" ; echo_both
+
+#gpio_index="6"
+#pcbpin="A15" ; ball="A15" ; default_mode="3" ; find_ball
+#gpio_index="7"
+
+msg="" ; echo_both
+
+cat ${file}-pinmux.dts >> ${file}.dts
+
+echo "cape-universal {" >> ${file}.dts
+echo "	compatible = \"gpio-of-helper\";" >> ${file}.dts
+echo "	status = \"okay\";" >> ${file}.dts
+echo "	pinctrl-names = \"default\";" >> ${file}.dts
+echo "	pinctrl-0 = <>;" >> ${file}.dts
+
+cat ${file}-gpio.dts >> ${file}.dts
+
+echo "};" >> ${file}.dts
+
+rm -rf ${file}-pinmux.dts || true
+rm -rf ${file}-gpio.dts || true
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/tools/pinmux-generator/BeagleBone_Black_config-pin.txt b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/tools/pinmux-generator/BeagleBone_Black_config-pin.txt
new file mode 100644
index 0000000000000000000000000000000000000000..14ffc9881fdd9a49504c34dd58df275022d753aa
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/tools/pinmux-generator/BeagleBone_Black_config-pin.txt
@@ -0,0 +1,584 @@
+
+P8_01_PIN="gnd"
+P8_01_INFO="GND"
+P8_01_CAPE=""
+
+P8_02_PIN="gnd"
+P8_02_INFO="GND"
+P8_02_CAPE=""
+
+P8_03_PRU="70"
+P8_03_GPIO="38"
+P8_03_PIN="emmc"
+P8_03_PINMUX="default gpio gpio_pu gpio_pd gpio_input"
+P8_03_INFO="gpio1_6 default gpio1_6 gpio1_6 gpio1_6 gpio1_6"
+P8_03_CAPE=""
+
+P8_04_PRU="71"
+P8_04_GPIO="39"
+P8_04_PIN="emmc"
+P8_04_PINMUX="default gpio gpio_pu gpio_pd gpio_input"
+P8_04_INFO="gpio1_7 default gpio1_7 gpio1_7 gpio1_7 gpio1_7"
+P8_04_CAPE=""
+
+P8_05_PRU="66"
+P8_05_GPIO="34"
+P8_05_PIN="emmc"
+P8_05_PINMUX="default gpio gpio_pu gpio_pd gpio_input"
+P8_05_INFO="gpio1_2 default gpio1_2 gpio1_2 gpio1_2 gpio1_2"
+P8_05_CAPE=""
+
+P8_06_PRU="67"
+P8_06_GPIO="35"
+P8_06_PIN="emmc"
+P8_06_PINMUX="default gpio gpio_pu gpio_pd gpio_input"
+P8_06_INFO="gpio1_3 default gpio1_3 gpio1_3 gpio1_3 gpio1_3"
+P8_06_CAPE=""
+
+P8_07_PRU="98"
+P8_07_GPIO="66"
+P8_07_PIN="gpio"
+P8_07_PINMUX="default gpio gpio_pu gpio_pd gpio_input timer"
+P8_07_INFO="gpio2_2 default gpio2_2 gpio2_2 gpio2_2 gpio2_2 timer4"
+P8_07_CAPE=""
+
+P8_08_PRU="99"
+P8_08_GPIO="67"
+P8_08_PIN="gpio"
+P8_08_PINMUX="default gpio gpio_pu gpio_pd gpio_input timer"
+P8_08_INFO="gpio2_3 default gpio2_3 gpio2_3 gpio2_3 gpio2_3 timer7"
+P8_08_CAPE=""
+
+P8_09_PRU="101"
+P8_09_GPIO="69"
+P8_09_PIN="gpio"
+P8_09_PINMUX="default gpio gpio_pu gpio_pd gpio_input timer"
+P8_09_INFO="gpio2_5 default gpio2_5 gpio2_5 gpio2_5 gpio2_5 timer5"
+P8_09_CAPE=""
+
+P8_10_PRU="100"
+P8_10_GPIO="68"
+P8_10_PIN="gpio"
+P8_10_PINMUX="default gpio gpio_pu gpio_pd gpio_input timer"
+P8_10_INFO="gpio2_4 default gpio2_4 gpio2_4 gpio2_4 gpio2_4 timer6"
+P8_10_CAPE=""
+
+P8_11_PRU="77"
+P8_11_GPIO="45"
+P8_11_PIN="gpio"
+P8_11_PINMUX="default gpio gpio_pu gpio_pd gpio_input qep pruout"
+P8_11_INFO="gpio1_13 default gpio1_13 gpio1_13 gpio1_13 gpio1_13 eqep2b_in pru0_out15"
+P8_11_CAPE=""
+
+P8_12_PRU="76"
+P8_12_GPIO="44"
+P8_12_PIN="gpio"
+P8_12_PINMUX="default gpio gpio_pu gpio_pd gpio_input qep pruout"
+P8_12_INFO="gpio1_12 default gpio1_12 gpio1_12 gpio1_12 gpio1_12 eqep2a_in pru0_out14"
+P8_12_CAPE=""
+
+P8_13_PRU="55"
+P8_13_GPIO="23"
+P8_13_PIN="gpio"
+P8_13_PINMUX="default gpio gpio_pu gpio_pd gpio_input pwm"
+P8_13_INFO="gpio0_23 default gpio0_23 gpio0_23 gpio0_23 gpio0_23 ehrpwm2b"
+P8_13_CAPE=""
+
+P8_14_PRU="58"
+P8_14_GPIO="26"
+P8_14_PIN="gpio"
+P8_14_PINMUX="default gpio gpio_pu gpio_pd gpio_input pwm"
+P8_14_INFO="gpio0_26 default gpio0_26 gpio0_26 gpio0_26 gpio0_26 ehrpwm2_tripzone_input"
+P8_14_CAPE=""
+
+P8_15_PRU="79"
+P8_15_GPIO="47"
+P8_15_PIN="gpio"
+P8_15_PINMUX="default gpio gpio_pu gpio_pd gpio_input qep pru_ecap pruin"
+P8_15_INFO="gpio1_15 default gpio1_15 gpio1_15 gpio1_15 gpio1_15 eqep2_strobe pru_ecap pru0_in15"
+P8_15_CAPE=""
+
+P8_16_PRU="78"
+P8_16_GPIO="46"
+P8_16_PIN="gpio"
+P8_16_PINMUX="default gpio gpio_pu gpio_pd gpio_input qep pruin"
+P8_16_INFO="gpio1_14 default gpio1_14 gpio1_14 gpio1_14 gpio1_14 eqep2_index pru0_in14"
+P8_16_CAPE=""
+
+P8_17_PRU="59"
+P8_17_GPIO="27"
+P8_17_PIN="gpio"
+P8_17_PINMUX="default gpio gpio_pu gpio_pd gpio_input pwm"
+P8_17_INFO="gpio0_27 default gpio0_27 gpio0_27 gpio0_27 gpio0_27 ehrpwm0_synco"
+P8_17_CAPE=""
+
+P8_18_PRU="97"
+P8_18_GPIO="65"
+P8_18_PIN="gpio"
+P8_18_PINMUX="default gpio gpio_pu gpio_pd gpio_input"
+P8_18_INFO="gpio2_1 default gpio2_1 gpio2_1 gpio2_1 gpio2_1"
+P8_18_CAPE=""
+
+P8_19_PRU="54"
+P8_19_GPIO="22"
+P8_19_PIN="gpio"
+P8_19_PINMUX="default gpio gpio_pu gpio_pd gpio_input pwm"
+P8_19_INFO="gpio0_22 default gpio0_22 gpio0_22 gpio0_22 gpio0_22 ehrpwm2a"
+P8_19_CAPE=""
+
+P8_20_PRU="95"
+P8_20_GPIO="63"
+P8_20_PIN="emmc"
+P8_20_PINMUX="default gpio gpio_pu gpio_pd gpio_input pruout pruin"
+P8_20_INFO="gpio1_31 default gpio1_31 gpio1_31 gpio1_31 gpio1_31 pru1_out13 pru1_in13"
+P8_20_CAPE=""
+
+P8_21_PRU="94"
+P8_21_GPIO="62"
+P8_21_PIN="emmc"
+P8_21_PINMUX="default gpio gpio_pu gpio_pd gpio_input pruout pruin"
+P8_21_INFO="gpio1_30 default gpio1_30 gpio1_30 gpio1_30 gpio1_30 pru1_out12 pru1_in12"
+P8_21_CAPE=""
+
+P8_22_PRU="69"
+P8_22_GPIO="37"
+P8_22_PIN="emmc"
+P8_22_PINMUX="default gpio gpio_pu gpio_pd gpio_input"
+P8_22_INFO="gpio1_5 default gpio1_5 gpio1_5 gpio1_5 gpio1_5"
+P8_22_CAPE=""
+
+P8_23_PRU="68"
+P8_23_GPIO="36"
+P8_23_PIN="emmc"
+P8_23_PINMUX="default gpio gpio_pu gpio_pd gpio_input"
+P8_23_INFO="gpio1_4 default gpio1_4 gpio1_4 gpio1_4 gpio1_4"
+P8_23_CAPE=""
+
+P8_24_PRU="65"
+P8_24_GPIO="33"
+P8_24_PIN="emmc"
+P8_24_PINMUX="default gpio gpio_pu gpio_pd gpio_input"
+P8_24_INFO="gpio1_1 default gpio1_1 gpio1_1 gpio1_1 gpio1_1"
+P8_24_CAPE=""
+
+P8_25_PRU="64"
+P8_25_GPIO="32"
+P8_25_PIN="emmc"
+P8_25_PINMUX="default gpio gpio_pu gpio_pd gpio_input"
+P8_25_INFO="gpio1_0 default gpio1_0 gpio1_0 gpio1_0 gpio1_0"
+P8_25_CAPE=""
+
+P8_26_PRU="93"
+P8_26_GPIO="61"
+P8_26_PIN="gpio"
+P8_26_PINMUX="default gpio gpio_pu gpio_pd gpio_input"
+P8_26_INFO="gpio1_29 default gpio1_29 gpio1_29 gpio1_29 gpio1_29"
+P8_26_CAPE=""
+
+P8_27_PRU="118"
+P8_27_GPIO="86"
+P8_27_PIN="hdmi"
+P8_27_PINMUX="default gpio gpio_pu gpio_pd gpio_input pruout pruin"
+P8_27_INFO="gpio2_22 default gpio2_22 gpio2_22 gpio2_22 gpio2_22 pru1_out8 pru1_in8"
+P8_27_CAPE=""
+
+P8_28_PRU="120"
+P8_28_GPIO="88"
+P8_28_PIN="hdmi"
+P8_28_PINMUX="default gpio gpio_pu gpio_pd gpio_input pruout pruin"
+P8_28_INFO="gpio2_24 default gpio2_24 gpio2_24 gpio2_24 gpio2_24 pru1_out10 pru1_in10"
+P8_28_CAPE=""
+
+P8_29_PRU="119"
+P8_29_GPIO="87"
+P8_29_PIN="hdmi"
+P8_29_PINMUX="default gpio gpio_pu gpio_pd gpio_input pruout pruin"
+P8_29_INFO="gpio2_23 default gpio2_23 gpio2_23 gpio2_23 gpio2_23 pru1_out9 pru1_in9"
+P8_29_CAPE=""
+
+P8_30_PRU="121"
+P8_30_GPIO="89"
+P8_30_PIN="hdmi"
+P8_30_PINMUX="default gpio gpio_pu gpio_pd gpio_input pruout pruin"
+P8_30_INFO="gpio2_25 default gpio2_25 gpio2_25 gpio2_25 gpio2_25 pru1_out11 pru1_in11"
+P8_30_CAPE=""
+
+P8_31_PRU="42"
+P8_31_GPIO="10"
+P8_31_PIN="hdmi"
+P8_31_PINMUX="default gpio gpio_pu gpio_pd gpio_input uart qep"
+P8_31_INFO="gpio0_10 default gpio0_10 gpio0_10 gpio0_10 gpio0_10 uart5_rxd eqep1_index"
+P8_31_CAPE=""
+
+P8_32_PRU="43"
+P8_32_GPIO="11"
+P8_32_PIN="hdmi"
+P8_32_PINMUX="default gpio gpio_pu gpio_pd gpio_input qep"
+P8_32_INFO="gpio0_11 default gpio0_11 gpio0_11 gpio0_11 gpio0_11 eqep1_strobe"
+P8_32_CAPE=""
+
+P8_33_PRU="41"
+P8_33_GPIO="9"
+P8_33_PIN="hdmi"
+P8_33_PINMUX="default gpio gpio_pu gpio_pd gpio_input qep"
+P8_33_INFO="gpio0_9 default gpio0_9 gpio0_9 gpio0_9 gpio0_9 eqep1b_in"
+P8_33_CAPE=""
+
+P8_34_PRU="113"
+P8_34_GPIO="81"
+P8_34_PIN="hdmi"
+P8_34_PINMUX="default gpio gpio_pu gpio_pd gpio_input pwm"
+P8_34_INFO="gpio2_17 default gpio2_17 gpio2_17 gpio2_17 gpio2_17 ehrpwm1b"
+P8_34_CAPE=""
+
+P8_35_PRU="40"
+P8_35_GPIO="8"
+P8_35_PIN="hdmi"
+P8_35_PINMUX="default gpio gpio_pu gpio_pd gpio_input qep"
+P8_35_INFO="gpio0_8 default gpio0_8 gpio0_8 gpio0_8 gpio0_8 eqep1a_in"
+P8_35_CAPE=""
+
+P8_36_PRU="112"
+P8_36_GPIO="80"
+P8_36_PIN="hdmi"
+P8_36_PINMUX="default gpio gpio_pu gpio_pd gpio_input pwm"
+P8_36_INFO="gpio2_16 default gpio2_16 gpio2_16 gpio2_16 gpio2_16 ehrpwm1a"
+P8_36_CAPE=""
+
+P8_37_PRU="110"
+P8_37_GPIO="78"
+P8_37_PIN="hdmi"
+P8_37_PINMUX="default gpio gpio_pu gpio_pd gpio_input uart pwm"
+P8_37_INFO="gpio2_14 default gpio2_14 gpio2_14 gpio2_14 gpio2_14 uart5_txd ehrpwm1_tripzone_input"
+P8_37_CAPE=""
+
+P8_38_PRU="111"
+P8_38_GPIO="79"
+P8_38_PIN="hdmi"
+P8_38_PINMUX="default gpio gpio_pu gpio_pd gpio_input uart pwm"
+P8_38_INFO="gpio2_15 default gpio2_15 gpio2_15 gpio2_15 gpio2_15 uart5_rxd ehrpwm0_synco"
+P8_38_CAPE=""
+
+P8_39_PRU="108"
+P8_39_GPIO="76"
+P8_39_PIN="hdmi"
+P8_39_PINMUX="default gpio gpio_pu gpio_pd gpio_input qep pruout pruin"
+P8_39_INFO="gpio2_12 default gpio2_12 gpio2_12 gpio2_12 gpio2_12 eqep2_index pru1_out6 pru1_in6"
+P8_39_CAPE=""
+
+P8_40_PRU="109"
+P8_40_GPIO="77"
+P8_40_PIN="hdmi"
+P8_40_PINMUX="default gpio gpio_pu gpio_pd gpio_input qep pruout pruin"
+P8_40_INFO="gpio2_13 default gpio2_13 gpio2_13 gpio2_13 gpio2_13 eqep2_strobe pru1_out7 pru1_in7"
+P8_40_CAPE=""
+
+P8_41_PRU="106"
+P8_41_GPIO="74"
+P8_41_PIN="hdmi"
+P8_41_PINMUX="default gpio gpio_pu gpio_pd gpio_input qep pruout pruin"
+P8_41_INFO="gpio2_10 default gpio2_10 gpio2_10 gpio2_10 gpio2_10 eqep2a_in pru1_out4 pru1_in4"
+P8_41_CAPE=""
+
+P8_42_PRU="107"
+P8_42_GPIO="75"
+P8_42_PIN="hdmi"
+P8_42_PINMUX="default gpio gpio_pu gpio_pd gpio_input qep pruout pruin"
+P8_42_INFO="gpio2_11 default gpio2_11 gpio2_11 gpio2_11 gpio2_11 eqep2b_in pru1_out5 pru1_in5"
+P8_42_CAPE=""
+
+P8_43_PRU="104"
+P8_43_GPIO="72"
+P8_43_PIN="hdmi"
+P8_43_PINMUX="default gpio gpio_pu gpio_pd gpio_input pwm pruout pruin"
+P8_43_INFO="gpio2_8 default gpio2_8 gpio2_8 gpio2_8 gpio2_8 ehrpwm2_tripzone_input pru1_out2 pru1_in2"
+P8_43_CAPE=""
+
+P8_44_PRU="105"
+P8_44_GPIO="73"
+P8_44_PIN="hdmi"
+P8_44_PINMUX="default gpio gpio_pu gpio_pd gpio_input pwm pruout pruin"
+P8_44_INFO="gpio2_9 default gpio2_9 gpio2_9 gpio2_9 gpio2_9 ehrpwm0_synco pru1_out3 pru1_in3"
+P8_44_CAPE=""
+
+P8_45_PRU="102"
+P8_45_GPIO="70"
+P8_45_PIN="hdmi"
+P8_45_PINMUX="default gpio gpio_pu gpio_pd gpio_input pwm pruout pruin"
+P8_45_INFO="gpio2_6 default gpio2_6 gpio2_6 gpio2_6 gpio2_6 ehrpwm2a pru1_out0 pru1_in0"
+P8_45_CAPE=""
+
+P8_46_PRU="103"
+P8_46_GPIO="71"
+P8_46_PIN="hdmi"
+P8_46_PINMUX="default gpio gpio_pu gpio_pd gpio_input pwm pruout pruin"
+P8_46_INFO="gpio2_7 default gpio2_7 gpio2_7 gpio2_7 gpio2_7 ehrpwm2b pru1_out1 pru1_in1"
+P8_46_CAPE=""
+
+P9_01_PIN="gnd"
+P9_01_INFO="GND"
+P9_01_CAPE=""
+
+P9_02_PIN="gnd"
+P9_02_INFO="GND"
+P9_02_CAPE=""
+
+P9_03_PIN="power"
+P9_03_INFO="3V3"
+P9_03_CAPE=""
+
+P9_04_PIN="power"
+P9_04_INFO="3V3"
+P9_04_CAPE=""
+
+P9_05_PIN="power"
+P9_05_INFO="VDD_5V"
+P9_05_CAPE=""
+
+P9_06_PIN="power"
+P9_06_INFO="VDD_5V"
+P9_06_CAPE=""
+
+P9_07_PIN="power"
+P9_07_INFO="SYS_5V"
+P9_07_CAPE=""
+
+P9_08_PIN="power"
+P9_08_INFO="SYS_5V"
+P9_08_CAPE=""
+
+P9_09_PIN="system"
+P9_09_INFO="PWR_BUT"
+P9_09_CAPE=""
+
+P9_10_PIN="system"
+P9_10_INFO="RSTn"
+P9_10_CAPE=""
+
+P9_11_PRU="62"
+P9_11_GPIO="30"
+P9_11_PIN="gpio"
+P9_11_PINMUX="default gpio gpio_pu gpio_pd gpio_input uart"
+P9_11_INFO="gpio0_30 default gpio0_30 gpio0_30 gpio0_30 gpio0_30 uart4_rxd"
+P9_11_CAPE=""
+
+P9_12_PRU="92"
+P9_12_GPIO="60"
+P9_12_PIN="gpio"
+P9_12_PINMUX="default gpio gpio_pu gpio_pd gpio_input"
+P9_12_INFO="gpio1_28 default gpio1_28 gpio1_28 gpio1_28 gpio1_28"
+P9_12_CAPE=""
+
+P9_13_PRU="63"
+P9_13_GPIO="31"
+P9_13_PIN="gpio"
+P9_13_PINMUX="default gpio gpio_pu gpio_pd gpio_input uart"
+P9_13_INFO="gpio0_31 default gpio0_31 gpio0_31 gpio0_31 gpio0_31 uart4_txd"
+P9_13_CAPE=""
+
+P9_14_PRU="82"
+P9_14_GPIO="50"
+P9_14_PIN="gpio"
+P9_14_PINMUX="default gpio gpio_pu gpio_pd gpio_input pwm"
+P9_14_INFO="gpio1_18 default gpio1_18 gpio1_18 gpio1_18 gpio1_18 ehrpwm1a"
+P9_14_CAPE=""
+
+P9_15_PRU="80"
+P9_15_GPIO="48"
+P9_15_PIN="gpio"
+P9_15_PINMUX="default gpio gpio_pu gpio_pd gpio_input pwm"
+P9_15_INFO="gpio1_16 default gpio1_16 gpio1_16 gpio1_16 gpio1_16 ehrpwm1_tripzone_input"
+P9_15_CAPE=""
+
+P9_16_PRU="83"
+P9_16_GPIO="51"
+P9_16_PIN="gpio"
+P9_16_PINMUX="default gpio gpio_pu gpio_pd gpio_input pwm"
+P9_16_INFO="gpio1_19 default gpio1_19 gpio1_19 gpio1_19 gpio1_19 ehrpwm1b"
+P9_16_CAPE=""
+
+P9_17_PRU="37"
+P9_17_GPIO="5"
+P9_17_PIN="gpio"
+P9_17_PINMUX="default gpio gpio_pu gpio_pd gpio_input spi_cs i2c pwm pru_uart"
+P9_17_INFO="gpio0_5 default gpio0_5 gpio0_5 gpio0_5 gpio0_5 spi0_cs0 i2c1_scl ehrpwm0_synci pru_uart"
+P9_17_CAPE=""
+
+P9_18_PRU="36"
+P9_18_GPIO="4"
+P9_18_PIN="gpio"
+P9_18_PINMUX="default gpio gpio_pu gpio_pd gpio_input spi i2c pwm pru_uart"
+P9_18_INFO="gpio0_4 default gpio0_4 gpio0_4 gpio0_4 gpio0_4 spi0_d1 i2c1_sda ehrpwm0_tripzone_input pru_uart"
+P9_18_CAPE=""
+
+P9_19_PRU="45"
+P9_19_GPIO="13"
+P9_19_PIN="i2c"
+P9_19_PINMUX="default gpio gpio_pu gpio_pd gpio_input spi_cs can i2c pru_uart timer"
+P9_19_INFO="i2c2_scl default gpio0_13 gpio0_13 gpio0_13 gpio0_13 spi1_cs1 dcan0_rx i2c2_scl pru_uart timer5"
+P9_19_CAPE=""
+
+P9_20_PRU="44"
+P9_20_GPIO="12"
+P9_20_PIN="i2c"
+P9_20_PINMUX="default gpio gpio_pu gpio_pd gpio_input spi_cs can i2c pru_uart timer"
+P9_20_INFO="i2c2_sda default gpio0_12 gpio0_12 gpio0_12 gpio0_12 spi1_cs0 dcan0_tx i2c2_sda pru_uart timer6"
+P9_20_CAPE=""
+
+P9_21_PRU="35"
+P9_21_GPIO="3"
+P9_21_PIN="gpio"
+P9_21_PINMUX="default gpio gpio_pu gpio_pd gpio_input spi uart i2c pwm pru_uart"
+P9_21_INFO="gpio0_3 default gpio0_3 gpio0_3 gpio0_3 gpio0_3 spi0_d0 uart2_txd i2c2_scl ehrpwm0b pru_uart"
+P9_21_CAPE=""
+
+P9_22_PRU="34"
+P9_22_GPIO="2"
+P9_22_PIN="gpio"
+P9_22_PINMUX="default gpio gpio_pu gpio_pd gpio_input spi_sclk uart i2c pwm pru_uart"
+P9_22_INFO="gpio0_2 default gpio0_2 gpio0_2 gpio0_2 gpio0_2 spi0_sclk uart2_rxd i2c2_sda ehrpwm0a pru_uart"
+P9_22_CAPE=""
+
+P9_23_PRU="81"
+P9_23_GPIO="49"
+P9_23_PIN="gpio"
+P9_23_PINMUX="default gpio gpio_pu gpio_pd gpio_input pwm"
+P9_23_INFO="gpio1_17 default gpio1_17 gpio1_17 gpio1_17 gpio1_17 ehrpwm0_synco"
+P9_23_CAPE=""
+
+P9_24_PRU="47"
+P9_24_GPIO="15"
+P9_24_PIN="gpio"
+P9_24_PINMUX="default gpio gpio_pu gpio_pd gpio_input uart can i2c pru_uart pruin"
+P9_24_INFO="gpio0_15 default gpio0_15 gpio0_15 gpio0_15 gpio0_15 uart1_txd dcan1_rx i2c1_scl pru_uart pru0_in16"
+P9_24_CAPE=""
+
+P9_25_PRU="149"
+P9_25_GPIO="117"
+P9_25_PIN="audio"
+P9_25_PINMUX="default gpio gpio_pu gpio_pd gpio_input qep pruout pruin"
+P9_25_INFO="gpio3_21 default gpio3_21 gpio3_21 gpio3_21 gpio3_21 eqep0_strobe pru0_out7 pru0_in7"
+P9_25_CAPE=""
+
+P9_26_PRU="46"
+P9_26_GPIO="14"
+P9_26_PIN="gpio"
+P9_26_PINMUX="default gpio gpio_pu gpio_pd gpio_input uart can i2c pru_uart pruin"
+P9_26_INFO="gpio0_14 default gpio0_14 gpio0_14 gpio0_14 gpio0_14 uart1_rxd dcan1_tx i2c1_sda pru_uart pru1_in16"
+P9_26_CAPE=""
+
+P9_27_PRU="147"
+P9_27_GPIO="115"
+P9_27_PIN="gpio"
+P9_27_PINMUX="default gpio gpio_pu gpio_pd gpio_input qep pruout pruin"
+P9_27_INFO="gpio3_19 default gpio3_19 gpio3_19 gpio3_19 gpio3_19 eqep0b_in pru0_out5 pru0_in5"
+P9_27_CAPE=""
+
+P9_28_PRU="145"
+P9_28_GPIO="113"
+P9_28_PIN="audio"
+P9_28_PINMUX="default gpio gpio_pu gpio_pd gpio_input spi_cs pwm pwm2 pruout pruin"
+P9_28_INFO="gpio3_17 default gpio3_17 gpio3_17 gpio3_17 gpio3_17 spi1_cs0 ehrpwm0_synci ecap2_in_pwm2_out pru0_out3 pru0_in3"
+P9_28_CAPE=""
+
+P9_29_PRU="143"
+P9_29_GPIO="111"
+P9_29_PIN="audio"
+P9_29_PINMUX="default gpio gpio_pu gpio_pd gpio_input spi pwm pruout pruin"
+P9_29_INFO="gpio3_15 default gpio3_15 gpio3_15 gpio3_15 gpio3_15 spi1_d0 ehrpwm0b pru0_out1 pru0_in1"
+P9_29_CAPE=""
+
+P9_30_PRU="144"
+P9_30_GPIO="112"
+P9_30_PIN="gpio"
+P9_30_PINMUX="default gpio gpio_pu gpio_pd gpio_input spi pwm pruout pruin"
+P9_30_INFO="gpio3_16 default gpio3_16 gpio3_16 gpio3_16 gpio3_16 spi1_d1 ehrpwm0_tripzone_input pru0_out2 pru0_in2"
+P9_30_CAPE=""
+
+P9_31_PRU="142"
+P9_31_GPIO="110"
+P9_31_PIN="audio"
+P9_31_PINMUX="default gpio gpio_pu gpio_pd gpio_input spi_sclk pwm pruout pruin"
+P9_31_INFO="gpio3_14 default gpio3_14 gpio3_14 gpio3_14 gpio3_14 spi1_sclk ehrpwm0a pru0_out0 pru0_in0"
+P9_31_CAPE=""
+
+P9_32_PIN="power"
+P9_32_INFO="VADC"
+P9_32_CAPE=""
+
+P9_33_PIN="adc"
+P9_33_INFO="AIN4"
+P9_33_CAPE=""
+
+P9_34_PIN="gnd"
+P9_34_INFO="AGND"
+P9_34_CAPE=""
+
+P9_35_PIN="adc"
+P9_35_INFO="AIN6"
+P9_35_CAPE=""
+
+P9_36_PIN="adc"
+P9_36_INFO="AIN5"
+P9_36_CAPE=""
+
+P9_37_PIN="adc"
+P9_37_INFO="AIN2"
+P9_37_CAPE=""
+
+P9_38_PIN="adc"
+P9_38_INFO="AIN3"
+P9_38_CAPE=""
+
+P9_39_PIN="adc"
+P9_39_INFO="AIN0"
+P9_39_CAPE=""
+
+P9_40_PIN="adc"
+P9_40_INFO="AIN1"
+P9_40_CAPE=""
+
+P9_41_PRU="52"
+P9_41_GPIO="20"
+P9_41_PIN="gpio"
+P9_41_PINMUX="default gpio gpio_pu gpio_pd gpio_input timer pruin"
+P9_41_INFO="gpio0_20 default gpio0_20 gpio0_20 gpio0_20 gpio0_20 timer7 pru0_in16"
+P9_41_CAPE=""
+
+P9_91_PRU="148"
+P9_91_GPIO="116"
+P9_91_PIN="gpio"
+P9_91_PINMUX="default gpio gpio_pu gpio_pd gpio_input qep pruout pruin"
+P9_91_INFO="gpio3_20 default gpio3_20 gpio3_20 gpio3_20 gpio3_20 eqep0_index pru0_out6 pru0_in6"
+P9_91_CAPE=""
+
+P9_42_PRU="39"
+P9_42_GPIO="7"
+P9_42_PIN="gpio"
+P9_42_PINMUX="default gpio gpio_pu gpio_pd gpio_input spi_cs spi_sclk uart pwm pru_ecap"
+P9_42_INFO="gpio0_7 default gpio0_7 gpio0_7 gpio0_7 gpio0_7 spi1_cs1 spi1_sclk uart3_txd ecap0_in_pwm0_out pru_ecap"
+P9_42_CAPE=""
+
+P9_92_PRU="146"
+P9_92_GPIO="114"
+P9_92_PIN="gpio"
+P9_92_PINMUX="default gpio gpio_pu gpio_pd gpio_input qep pruout pruin"
+P9_92_INFO="gpio3_18 default gpio3_18 gpio3_18 gpio3_18 gpio3_18 eqep0a_in pru0_out4 pru0_in4"
+P9_92_CAPE=""
+
+P9_43_PIN="gnd"
+P9_43_INFO="GND"
+P9_43_CAPE=""
+
+P9_44_PIN="gnd"
+P9_44_INFO="GND"
+P9_44_CAPE=""
+
+P9_45_PIN="gnd"
+P9_45_INFO="GND"
+P9_45_CAPE=""
+
+P9_46_PIN="gnd"
+P9_46_INFO="GND"
+P9_46_CAPE=""
+
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/tools/pinmux-generator/BeagleBone_Black_i2c_can.dts b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/tools/pinmux-generator/BeagleBone_Black_i2c_can.dts
new file mode 100644
index 0000000000000000000000000000000000000000..99447212e97eb702869a5496a703b46d6be56aca
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/tools/pinmux-generator/BeagleBone_Black_i2c_can.dts
@@ -0,0 +1,103 @@
+
+/* P9_19 (ZCZ ball D17) i2c2_scl */
+P9_19_default_pin: pinmux_P9_19_default_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x097c, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE3) >; };	/* uart1_rtsn.i2c2_scl */
+P9_19_gpio_pin: pinmux_P9_19_gpio_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x097c, PIN_OUTPUT | INPUT_EN | MUX_MODE7) >; };		/* uart1_rtsn.gpio0_13 */
+P9_19_gpio_pu_pin: pinmux_P9_19_gpio_pu_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x097c, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };	/* uart1_rtsn.gpio0_13 */
+P9_19_gpio_pd_pin: pinmux_P9_19_gpio_pd_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x097c, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* uart1_rtsn.gpio0_13 */
+P9_19_gpio_input_pin: pinmux_P9_19_gpio_input_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x097c, PIN_INPUT | MUX_MODE7) >; };			/* uart1_rtsn.gpio0_13 */
+P9_19_timer_pin: pinmux_P9_19_timer_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x097c, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE1) >; };	/* uart1_rtsn.timer5 */
+P9_19_can_pin: pinmux_P9_19_can_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x097c, PIN_INPUT_PULLUP | MUX_MODE2) >; };		/* uart1_rtsn.dcan0_rx */
+P9_19_i2c_pin: pinmux_P9_19_i2c_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x097c, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE3) >; };	/* uart1_rtsn.i2c2_scl */
+P9_19_spi_cs_pin: pinmux_P9_19_spi_cs_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x097c, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE4) >; };	/* uart1_rtsn.spi1_cs1 */
+P9_19_pru_uart_pin: pinmux_P9_19_pru_uart_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x097c, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE5) >; };	/* uart1_rtsn.pr1_uart0_rts_n */
+
+/* P9_20 (ZCZ ball D18) i2c2_sda */
+P9_20_default_pin: pinmux_P9_20_default_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0978, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE3) >; };	/* uart1_ctsn.i2c2_sda */
+P9_20_gpio_pin: pinmux_P9_20_gpio_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0978, PIN_OUTPUT | INPUT_EN | MUX_MODE7) >; };		/* uart1_ctsn.gpio0_12 */
+P9_20_gpio_pu_pin: pinmux_P9_20_gpio_pu_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0978, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };	/* uart1_ctsn.gpio0_12 */
+P9_20_gpio_pd_pin: pinmux_P9_20_gpio_pd_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0978, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* uart1_ctsn.gpio0_12 */
+P9_20_gpio_input_pin: pinmux_P9_20_gpio_input_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0978, PIN_INPUT | MUX_MODE7) >; };			/* uart1_ctsn.gpio0_12 */
+P9_20_timer_pin: pinmux_P9_20_timer_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0978, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE1) >; };	/* uart1_ctsn.timer6 */
+P9_20_can_pin: pinmux_P9_20_can_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0978, PIN_OUTPUT_PULLUP | MUX_MODE2) >; };		/* uart1_ctsn.dcan0_tx */
+P9_20_i2c_pin: pinmux_P9_20_i2c_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0978, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE3) >; };	/* uart1_ctsn.i2c2_sda */
+P9_20_spi_cs_pin: pinmux_P9_20_spi_cs_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0978, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE4) >; };	/* uart1_ctsn.spi1_cs0 */
+P9_20_pru_uart_pin: pinmux_P9_20_pru_uart_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0978, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE5) >; };	/* uart1_ctsn.pr1_uart0_cts_n */
+
+
+
+/* P9_19 (ZCZ ball D17) i2c */
+P9_19_pinmux {
+	compatible = "bone-pinmux-helper";
+	status = "okay";
+	pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input", "spi_cs", "can", "i2c", "pru_uart", "timer";
+	pinctrl-0 = <&P9_19_default_pin>;
+	pinctrl-1 = <&P9_19_gpio_pin>;
+	pinctrl-2 = <&P9_19_gpio_pu_pin>;
+	pinctrl-3 = <&P9_19_gpio_pd_pin>;
+	pinctrl-4 = <&P9_19_gpio_input_pin>;
+	pinctrl-5 = <&P9_19_spi_cs_pin>;
+	pinctrl-6 = <&P9_19_can_pin>;
+	pinctrl-7 = <&P9_19_i2c_pin>;
+	pinctrl-8 = <&P9_19_pru_uart_pin>;
+	pinctrl-9 = <&P9_19_timer_pin>;
+};
+
+/* P9_20 (ZCZ ball D18) i2c */
+P9_20_pinmux {
+	compatible = "bone-pinmux-helper";
+	status = "okay";
+	pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input", "spi_cs", "can", "i2c", "pru_uart", "timer";
+	pinctrl-0 = <&P9_20_default_pin>;
+	pinctrl-1 = <&P9_20_gpio_pin>;
+	pinctrl-2 = <&P9_20_gpio_pu_pin>;
+	pinctrl-3 = <&P9_20_gpio_pd_pin>;
+	pinctrl-4 = <&P9_20_gpio_input_pin>;
+	pinctrl-5 = <&P9_20_spi_cs_pin>;
+	pinctrl-6 = <&P9_20_can_pin>;
+	pinctrl-7 = <&P9_20_i2c_pin>;
+	pinctrl-8 = <&P9_20_pru_uart_pin>;
+	pinctrl-9 = <&P9_20_timer_pin>;
+};
+
+
+cape-universal {
+	compatible = "gpio-of-helper";
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <>;
+
+	P9_19 {
+		gpio-name = "P9_19";
+		gpio = <&gpio0 13 0>;
+		input;
+		dir-changeable;
+	};
+
+	P9_20 {
+		gpio-name = "P9_20";
+		gpio = <&gpio0 12 0>;
+		input;
+		dir-changeable;
+	};
+
+};
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/tools/pinmux-generator/BeagleBone_Black_i2c_can.sh b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/tools/pinmux-generator/BeagleBone_Black_i2c_can.sh
new file mode 100644
index 0000000000000000000000000000000000000000..bfd05731359da4d0e6f451e9f011268eaa44b7d7
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/tools/pinmux-generator/BeagleBone_Black_i2c_can.sh
@@ -0,0 +1,35 @@
+#!/bin/bash
+
+source $(dirname "$0")/lib/pinmux.sh
+
+file="BeagleBone_Black_i2c_can"
+
+echo "" > ${file}.dts
+echo "" >${file}-pinmux.dts
+echo "" >${file}-gpio.dts
+echo "" >${file}_config-pin.txt
+
+#BeagleBone Black
+
+#PocketBeagle
+gpio_index="7"
+
+pcbpin="P9_19" ; ball="D17" ; default_mode="3" ; cp_default="i2c" ; find_ball
+pcbpin="P9_20" ; ball="D18" ; default_mode="3" ; cp_default="i2c" ; find_ball
+
+msg="" ; echo_both
+
+cat ${file}-pinmux.dts >> ${file}.dts
+
+echo "cape-universal {" >> ${file}.dts
+echo "	compatible = \"gpio-of-helper\";" >> ${file}.dts
+echo "	status = \"okay\";" >> ${file}.dts
+echo "	pinctrl-names = \"default\";" >> ${file}.dts
+echo "	pinctrl-0 = <>;" >> ${file}.dts
+
+cat ${file}-gpio.dts >> ${file}.dts
+
+echo "};" >> ${file}.dts
+
+rm -rf ${file}-pinmux.dts || true
+rm -rf ${file}-gpio.dts || true
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/tools/pinmux-generator/BeagleBone_Black_i2c_can_config-pin.txt b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/tools/pinmux-generator/BeagleBone_Black_i2c_can_config-pin.txt
new file mode 100644
index 0000000000000000000000000000000000000000..4a3a9d03f0f9da92e8f98240ab4ffae98a72c657
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/tools/pinmux-generator/BeagleBone_Black_i2c_can_config-pin.txt
@@ -0,0 +1,15 @@
+
+P9_19_PRU="45"
+P9_19_GPIO="13"
+P9_19_PIN="i2c"
+P9_19_PINMUX="default gpio gpio_pu gpio_pd gpio_input spi_cs can i2c pru_uart timer"
+P9_19_INFO="i2c2_scl default gpio0_13 gpio0_13 gpio0_13 gpio0_13 spi1_cs1 dcan0_rx i2c2_scl pru_uart timer5"
+P9_19_CAPE=""
+
+P9_20_PRU="44"
+P9_20_GPIO="12"
+P9_20_PIN="i2c"
+P9_20_PINMUX="default gpio gpio_pu gpio_pd gpio_input spi_cs can i2c pru_uart timer"
+P9_20_INFO="i2c2_sda default gpio0_12 gpio0_12 gpio0_12 gpio0_12 spi1_cs0 dcan0_tx i2c2_sda pru_uart timer6"
+P9_20_CAPE=""
+
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/tools/pinmux-generator/BeagleBone_Blue.dts b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/tools/pinmux-generator/BeagleBone_Blue.dts
new file mode 100644
index 0000000000000000000000000000000000000000..6b03b6a9d352eb8105c6275bc201cf721614bff5
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/tools/pinmux-generator/BeagleBone_Blue.dts
@@ -0,0 +1,1202 @@
+
+/* E1_3 (ZCZ ball B12) eqep0a_in */
+E1_3_default_pin: pinmux_E1_3_default_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x09a0, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE1) >; };	/* mcasp0_aclkr.eqep0a_in */
+E1_3_gpio_pin: pinmux_E1_3_gpio_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x09a0, PIN_OUTPUT | INPUT_EN | MUX_MODE7) >; };		/* mcasp0_aclkr.gpio3_18 */
+E1_3_gpio_pu_pin: pinmux_E1_3_gpio_pu_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x09a0, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };	/* mcasp0_aclkr.gpio3_18 */
+E1_3_gpio_pd_pin: pinmux_E1_3_gpio_pd_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x09a0, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* mcasp0_aclkr.gpio3_18 */
+E1_3_gpio_input_pin: pinmux_E1_3_gpio_input_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x09a0, PIN_INPUT | MUX_MODE7) >; };			/* mcasp0_aclkr.gpio3_18 */
+E1_3_qep_pin: pinmux_E1_3_qep_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x09a0, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE1) >; };	/* mcasp0_aclkr.eqep0a_in */
+E1_3_pruout_pin: pinmux_E1_3_pruout_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x09a0, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE5) >; };	/* mcasp0_aclkr.pru0_out4 */
+E1_3_pruin_pin: pinmux_E1_3_pruin_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x09a0, PIN_INPUT | MUX_MODE6) >; };			/* mcasp0_aclkr.pru0_in4 */
+
+/* E1_4 (ZCZ ball C13) eqep0b_in */
+E1_4_default_pin: pinmux_E1_4_default_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x09a4, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE1) >; };	/* mcasp0_fsr.eqep0b_in */
+E1_4_gpio_pin: pinmux_E1_4_gpio_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x09a4, PIN_OUTPUT | INPUT_EN | MUX_MODE7) >; };		/* mcasp0_fsr.gpio3_19 */
+E1_4_gpio_pu_pin: pinmux_E1_4_gpio_pu_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x09a4, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };	/* mcasp0_fsr.gpio3_19 */
+E1_4_gpio_pd_pin: pinmux_E1_4_gpio_pd_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x09a4, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* mcasp0_fsr.gpio3_19 */
+E1_4_gpio_input_pin: pinmux_E1_4_gpio_input_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x09a4, PIN_INPUT | MUX_MODE7) >; };			/* mcasp0_fsr.gpio3_19 */
+E1_4_qep_pin: pinmux_E1_4_qep_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x09a4, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE1) >; };	/* mcasp0_fsr.eqep0b_in */
+E1_4_pruout_pin: pinmux_E1_4_pruout_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x09a4, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE5) >; };	/* mcasp0_fsr.pru0_out5 */
+E1_4_pruin_pin: pinmux_E1_4_pruin_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x09a4, PIN_INPUT | MUX_MODE6) >; };			/* mcasp0_fsr.pru0_in5 */
+
+/* E2_3 (ZCZ ball V2) eqep1a_in */
+E2_3_default_pin: pinmux_E2_3_default_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08d0, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE2) >; };	/* lcd_data12.eqep1a_in */
+E2_3_gpio_pin: pinmux_E2_3_gpio_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08d0, PIN_OUTPUT | INPUT_EN | MUX_MODE7) >; };		/* lcd_data12.gpio0_8 */
+E2_3_gpio_pu_pin: pinmux_E2_3_gpio_pu_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08d0, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };	/* lcd_data12.gpio0_8 */
+E2_3_gpio_pd_pin: pinmux_E2_3_gpio_pd_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08d0, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* lcd_data12.gpio0_8 */
+E2_3_gpio_input_pin: pinmux_E2_3_gpio_input_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08d0, PIN_INPUT | MUX_MODE7) >; };			/* lcd_data12.gpio0_8 */
+E2_3_qep_pin: pinmux_E2_3_qep_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08d0, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE2) >; };	/* lcd_data12.eqep1a_in */
+
+/* E2_4 (ZCZ ball V3) eqep1b_in */
+E2_4_default_pin: pinmux_E2_4_default_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08d4, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE2) >; };	/* lcd_data13.eqep1b_in */
+E2_4_gpio_pin: pinmux_E2_4_gpio_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08d4, PIN_OUTPUT | INPUT_EN | MUX_MODE7) >; };		/* lcd_data13.gpio0_9 */
+E2_4_gpio_pu_pin: pinmux_E2_4_gpio_pu_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08d4, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };	/* lcd_data13.gpio0_9 */
+E2_4_gpio_pd_pin: pinmux_E2_4_gpio_pd_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08d4, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* lcd_data13.gpio0_9 */
+E2_4_gpio_input_pin: pinmux_E2_4_gpio_input_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08d4, PIN_INPUT | MUX_MODE7) >; };			/* lcd_data13.gpio0_9 */
+E2_4_qep_pin: pinmux_E2_4_qep_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08d4, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE2) >; };	/* lcd_data13.eqep1b_in */
+
+/* E3_3 (ZCZ ball T12) eqep2a_in */
+E3_3_default_pin: pinmux_E3_3_default_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0830, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE4) >; };	/* gpmc_ad12.eqep2a_in */
+E3_3_gpio_pin: pinmux_E3_3_gpio_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0830, PIN_OUTPUT | INPUT_EN | MUX_MODE7) >; };		/* gpmc_ad12.gpio1_12 */
+E3_3_gpio_pu_pin: pinmux_E3_3_gpio_pu_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0830, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };	/* gpmc_ad12.gpio1_12 */
+E3_3_gpio_pd_pin: pinmux_E3_3_gpio_pd_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0830, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* gpmc_ad12.gpio1_12 */
+E3_3_gpio_input_pin: pinmux_E3_3_gpio_input_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0830, PIN_INPUT | MUX_MODE7) >; };			/* gpmc_ad12.gpio1_12 */
+E3_3_qep_pin: pinmux_E3_3_qep_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0830, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE4) >; };	/* gpmc_ad12.eqep2a_in */
+E3_3_pruout_pin: pinmux_E3_3_pruout_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0830, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE6) >; };	/* gpmc_ad12.pru0_out14 */
+
+/* E3_4 (ZCZ ball R12) eqep2b_in */
+E3_4_default_pin: pinmux_E3_4_default_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0834, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE4) >; };	/* gpmc_ad13.eqep2b_in */
+E3_4_gpio_pin: pinmux_E3_4_gpio_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0834, PIN_OUTPUT | INPUT_EN | MUX_MODE7) >; };		/* gpmc_ad13.gpio1_13 */
+E3_4_gpio_pu_pin: pinmux_E3_4_gpio_pu_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0834, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };	/* gpmc_ad13.gpio1_13 */
+E3_4_gpio_pd_pin: pinmux_E3_4_gpio_pd_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0834, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* gpmc_ad13.gpio1_13 */
+E3_4_gpio_input_pin: pinmux_E3_4_gpio_input_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0834, PIN_INPUT | MUX_MODE7) >; };			/* gpmc_ad13.gpio1_13 */
+E3_4_qep_pin: pinmux_E3_4_qep_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0834, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE4) >; };	/* gpmc_ad13.eqep2b_in */
+E3_4_pruout_pin: pinmux_E3_4_pruout_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0834, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE6) >; };	/* gpmc_ad13.pru0_out15 */
+
+/* E4_3 (ZCZ ball V13) pru0_in14 */
+E4_3_default_pin: pinmux_E4_3_default_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0838, PIN_INPUT | MUX_MODE6) >; };			/* gpmc_ad14.pru0_in14 */
+E4_3_gpio_pin: pinmux_E4_3_gpio_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0838, PIN_OUTPUT | INPUT_EN | MUX_MODE7) >; };		/* gpmc_ad14.gpio1_14 */
+E4_3_gpio_pu_pin: pinmux_E4_3_gpio_pu_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0838, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };	/* gpmc_ad14.gpio1_14 */
+E4_3_gpio_pd_pin: pinmux_E4_3_gpio_pd_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0838, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* gpmc_ad14.gpio1_14 */
+E4_3_gpio_input_pin: pinmux_E4_3_gpio_input_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0838, PIN_INPUT | MUX_MODE7) >; };			/* gpmc_ad14.gpio1_14 */
+E4_3_qep_pin: pinmux_E4_3_qep_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0838, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE4) >; };	/* gpmc_ad14.eqep2_index */
+E4_3_pruin_pin: pinmux_E4_3_pruin_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0838, PIN_INPUT | MUX_MODE6) >; };			/* gpmc_ad14.pru0_in14 */
+
+/* E4_4 (ZCZ ball U13) pru0_in15 */
+E4_4_default_pin: pinmux_E4_4_default_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x083c, PIN_INPUT | MUX_MODE6) >; };			/* gpmc_ad15.pru0_in15 */
+E4_4_gpio_pin: pinmux_E4_4_gpio_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x083c, PIN_OUTPUT | INPUT_EN | MUX_MODE7) >; };		/* gpmc_ad15.gpio1_15 */
+E4_4_gpio_pu_pin: pinmux_E4_4_gpio_pu_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x083c, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };	/* gpmc_ad15.gpio1_15 */
+E4_4_gpio_pd_pin: pinmux_E4_4_gpio_pd_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x083c, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* gpmc_ad15.gpio1_15 */
+E4_4_gpio_input_pin: pinmux_E4_4_gpio_input_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x083c, PIN_INPUT | MUX_MODE7) >; };			/* gpmc_ad15.gpio1_15 */
+E4_4_qep_pin: pinmux_E4_4_qep_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x083c, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE4) >; };	/* gpmc_ad15.eqep2_strobe */
+E4_4_pru_ecap_pin: pinmux_E4_4_pru_ecap_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x083c, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE5) >; };	/* gpmc_ad15.pr1_ecap0_ecap_capin_apwm_o */
+E4_4_pruin_pin: pinmux_E4_4_pruin_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x083c, PIN_INPUT | MUX_MODE6) >; };			/* gpmc_ad15.pru0_in15 */
+
+/* UT0_3 (ZCZ ball E15) uart0_rxd */
+UT0_3_default_pin: pinmux_UT0_3_default_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0970, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE0) >; };	/* uart0_rxd.uart0_rxd */
+UT0_3_gpio_pin: pinmux_UT0_3_gpio_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0970, PIN_OUTPUT | INPUT_EN | MUX_MODE7) >; };		/* uart0_rxd.gpio1_10 */
+UT0_3_gpio_pu_pin: pinmux_UT0_3_gpio_pu_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0970, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };	/* uart0_rxd.gpio1_10 */
+UT0_3_gpio_pd_pin: pinmux_UT0_3_gpio_pd_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0970, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* uart0_rxd.gpio1_10 */
+UT0_3_gpio_input_pin: pinmux_UT0_3_gpio_input_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0970, PIN_INPUT | MUX_MODE7) >; };			/* uart0_rxd.gpio1_10 */
+UT0_3_uart_pin: pinmux_UT0_3_uart_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0970, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE0) >; };	/* uart0_rxd.uart0_rxd */
+UT0_3_spi_cs_pin: pinmux_UT0_3_spi_cs_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0970, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE1) >; };	/* uart0_rxd.spi1_cs0 */
+UT0_3_can_pin: pinmux_UT0_3_can_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0970, PIN_OUTPUT_PULLUP | MUX_MODE2) >; };		/* uart0_rxd.dcan0_tx */
+UT0_3_i2c_pin: pinmux_UT0_3_i2c_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0970, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE3) >; };	/* uart0_rxd.i2c2_sda */
+UT0_3_pruout_pin: pinmux_UT0_3_pruout_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0970, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE5) >; };	/* uart0_rxd.pru1_out14 */
+UT0_3_pruin_pin: pinmux_UT0_3_pruin_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0970, PIN_INPUT | MUX_MODE6) >; };			/* uart0_rxd.pru1_in14 */
+
+/* UT0_4 (ZCZ ball E16) uart0_txd */
+UT0_4_default_pin: pinmux_UT0_4_default_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0974, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE0) >; };	/* uart0_txd.uart0_txd */
+UT0_4_gpio_pin: pinmux_UT0_4_gpio_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0974, PIN_OUTPUT | INPUT_EN | MUX_MODE7) >; };		/* uart0_txd.gpio1_11 */
+UT0_4_gpio_pu_pin: pinmux_UT0_4_gpio_pu_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0974, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };	/* uart0_txd.gpio1_11 */
+UT0_4_gpio_pd_pin: pinmux_UT0_4_gpio_pd_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0974, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* uart0_txd.gpio1_11 */
+UT0_4_gpio_input_pin: pinmux_UT0_4_gpio_input_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0974, PIN_INPUT | MUX_MODE7) >; };			/* uart0_txd.gpio1_11 */
+UT0_4_uart_pin: pinmux_UT0_4_uart_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0974, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE0) >; };	/* uart0_txd.uart0_txd */
+UT0_4_spi_cs_pin: pinmux_UT0_4_spi_cs_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0974, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE1) >; };	/* uart0_txd.spi1_cs1 */
+UT0_4_can_pin: pinmux_UT0_4_can_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0974, PIN_INPUT_PULLUP | MUX_MODE2) >; };		/* uart0_txd.dcan0_rx */
+UT0_4_i2c_pin: pinmux_UT0_4_i2c_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0974, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE3) >; };	/* uart0_txd.i2c2_scl */
+UT0_4_pruout_pin: pinmux_UT0_4_pruout_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0974, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE5) >; };	/* uart0_txd.pru1_out15 */
+UT0_4_pruin_pin: pinmux_UT0_4_pruin_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0974, PIN_INPUT | MUX_MODE6) >; };			/* uart0_txd.pru1_in15 */
+
+/* UT1_3 (ZCZ ball D16) uart1_rxd */
+UT1_3_default_pin: pinmux_UT1_3_default_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0980, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE0) >; };	/* uart1_rxd.uart1_rxd */
+UT1_3_gpio_pin: pinmux_UT1_3_gpio_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0980, PIN_OUTPUT | INPUT_EN | MUX_MODE7) >; };		/* uart1_rxd.gpio0_14 */
+UT1_3_gpio_pu_pin: pinmux_UT1_3_gpio_pu_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0980, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };	/* uart1_rxd.gpio0_14 */
+UT1_3_gpio_pd_pin: pinmux_UT1_3_gpio_pd_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0980, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* uart1_rxd.gpio0_14 */
+UT1_3_gpio_input_pin: pinmux_UT1_3_gpio_input_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0980, PIN_INPUT | MUX_MODE7) >; };			/* uart1_rxd.gpio0_14 */
+UT1_3_uart_pin: pinmux_UT1_3_uart_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0980, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE0) >; };	/* uart1_rxd.uart1_rxd */
+UT1_3_can_pin: pinmux_UT1_3_can_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0980, PIN_OUTPUT_PULLUP | MUX_MODE2) >; };		/* uart1_rxd.dcan1_tx */
+UT1_3_i2c_pin: pinmux_UT1_3_i2c_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0980, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE3) >; };	/* uart1_rxd.i2c1_sda */
+UT1_3_pru_uart_pin: pinmux_UT1_3_pru_uart_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0980, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE5) >; };	/* uart1_rxd.pr1_uart0_rxd */
+UT1_3_pruin_pin: pinmux_UT1_3_pruin_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0980, PIN_INPUT | MUX_MODE6) >; };			/* uart1_rxd.pru1_in16 */
+
+/* UT1_4 (ZCZ ball D15) uart1_txd */
+UT1_4_default_pin: pinmux_UT1_4_default_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0984, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE0) >; };	/* uart1_txd.uart1_txd */
+UT1_4_gpio_pin: pinmux_UT1_4_gpio_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0984, PIN_OUTPUT | INPUT_EN | MUX_MODE7) >; };		/* uart1_txd.gpio0_15 */
+UT1_4_gpio_pu_pin: pinmux_UT1_4_gpio_pu_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0984, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };	/* uart1_txd.gpio0_15 */
+UT1_4_gpio_pd_pin: pinmux_UT1_4_gpio_pd_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0984, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* uart1_txd.gpio0_15 */
+UT1_4_gpio_input_pin: pinmux_UT1_4_gpio_input_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0984, PIN_INPUT | MUX_MODE7) >; };			/* uart1_txd.gpio0_15 */
+UT1_4_uart_pin: pinmux_UT1_4_uart_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0984, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE0) >; };	/* uart1_txd.uart1_txd */
+UT1_4_can_pin: pinmux_UT1_4_can_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0984, PIN_INPUT_PULLUP | MUX_MODE2) >; };		/* uart1_txd.dcan1_rx */
+UT1_4_i2c_pin: pinmux_UT1_4_i2c_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0984, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE3) >; };	/* uart1_txd.i2c1_scl */
+UT1_4_pru_uart_pin: pinmux_UT1_4_pru_uart_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0984, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE5) >; };	/* uart1_txd.pr1_uart0_txd */
+UT1_4_pruin_pin: pinmux_UT1_4_pruin_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0984, PIN_INPUT | MUX_MODE6) >; };			/* uart1_txd.pru0_in16 */
+
+/* UT5_3 (ZCZ ball U2) uart5_rxd */
+UT5_3_default_pin: pinmux_UT5_3_default_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08c4, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE4) >; };	/* lcd_data9.uart5_rxd */
+UT5_3_gpio_pin: pinmux_UT5_3_gpio_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08c4, PIN_OUTPUT | INPUT_EN | MUX_MODE7) >; };		/* lcd_data9.gpio2_15 */
+UT5_3_gpio_pu_pin: pinmux_UT5_3_gpio_pu_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08c4, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };	/* lcd_data9.gpio2_15 */
+UT5_3_gpio_pd_pin: pinmux_UT5_3_gpio_pd_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08c4, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* lcd_data9.gpio2_15 */
+UT5_3_gpio_input_pin: pinmux_UT5_3_gpio_input_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08c4, PIN_INPUT | MUX_MODE7) >; };			/* lcd_data9.gpio2_15 */
+UT5_3_pwm_pin: pinmux_UT5_3_pwm_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08c4, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE2) >; };	/* lcd_data9.ehrpwm0_synco */
+UT5_3_uart_pin: pinmux_UT5_3_uart_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08c4, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE4) >; };	/* lcd_data9.uart5_rxd */
+
+/* UT5_4 (ZCZ ball U1) uart5_txd */
+UT5_4_default_pin: pinmux_UT5_4_default_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08c0, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE4) >; };	/* lcd_data8.uart5_txd */
+UT5_4_gpio_pin: pinmux_UT5_4_gpio_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08c0, PIN_OUTPUT | INPUT_EN | MUX_MODE7) >; };		/* lcd_data8.gpio2_14 */
+UT5_4_gpio_pu_pin: pinmux_UT5_4_gpio_pu_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08c0, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };	/* lcd_data8.gpio2_14 */
+UT5_4_gpio_pd_pin: pinmux_UT5_4_gpio_pd_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08c0, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* lcd_data8.gpio2_14 */
+UT5_4_gpio_input_pin: pinmux_UT5_4_gpio_input_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08c0, PIN_INPUT | MUX_MODE7) >; };			/* lcd_data8.gpio2_14 */
+UT5_4_pwm_pin: pinmux_UT5_4_pwm_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08c0, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE2) >; };	/* lcd_data8.ehrpwm1_tripzone_input */
+UT5_4_uart_pin: pinmux_UT5_4_uart_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08c0, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE4) >; };	/* lcd_data8.uart5_txd */
+
+/* DSM2_3 (ZCZ ball T17) uart4_rxd */
+DSM2_3_default_pin: pinmux_DSM2_3_default_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0870, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE6) >; };	/* gpmc_wait0.uart4_rxd */
+DSM2_3_gpio_pin: pinmux_DSM2_3_gpio_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0870, PIN_OUTPUT | INPUT_EN | MUX_MODE7) >; };		/* gpmc_wait0.gpio0_30 */
+DSM2_3_gpio_pu_pin: pinmux_DSM2_3_gpio_pu_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0870, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };	/* gpmc_wait0.gpio0_30 */
+DSM2_3_gpio_pd_pin: pinmux_DSM2_3_gpio_pd_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0870, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* gpmc_wait0.gpio0_30 */
+DSM2_3_gpio_input_pin: pinmux_DSM2_3_gpio_input_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0870, PIN_INPUT | MUX_MODE7) >; };			/* gpmc_wait0.gpio0_30 */
+DSM2_3_uart_pin: pinmux_DSM2_3_uart_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0870, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE6) >; };	/* gpmc_wait0.uart4_rxd */
+
+/* GP0_3 (ZCZ ball U16) gpio1_25 */
+GP0_3_default_pin: pinmux_GP0_3_default_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0864, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* gpmc_a9.gpio1_25 */
+GP0_3_gpio_pin: pinmux_GP0_3_gpio_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0864, PIN_OUTPUT | INPUT_EN | MUX_MODE7) >; };		/* gpmc_a9.gpio1_25 */
+GP0_3_gpio_pu_pin: pinmux_GP0_3_gpio_pu_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0864, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };	/* gpmc_a9.gpio1_25 */
+GP0_3_gpio_pd_pin: pinmux_GP0_3_gpio_pd_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0864, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* gpmc_a9.gpio1_25 */
+GP0_3_gpio_input_pin: pinmux_GP0_3_gpio_input_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0864, PIN_INPUT | MUX_MODE7) >; };			/* gpmc_a9.gpio1_25 */
+
+/* GP0_4 (ZCZ ball V14) gpio1_17 */
+GP0_4_default_pin: pinmux_GP0_4_default_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0844, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* gpmc_a1.gpio1_17 */
+GP0_4_gpio_pin: pinmux_GP0_4_gpio_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0844, PIN_OUTPUT | INPUT_EN | MUX_MODE7) >; };		/* gpmc_a1.gpio1_17 */
+GP0_4_gpio_pu_pin: pinmux_GP0_4_gpio_pu_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0844, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };	/* gpmc_a1.gpio1_17 */
+GP0_4_gpio_pd_pin: pinmux_GP0_4_gpio_pd_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0844, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* gpmc_a1.gpio1_17 */
+GP0_4_gpio_input_pin: pinmux_GP0_4_gpio_input_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0844, PIN_INPUT | MUX_MODE7) >; };			/* gpmc_a1.gpio1_17 */
+GP0_4_pwm_pin: pinmux_GP0_4_pwm_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0844, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE6) >; };	/* gpmc_a1.ehrpwm0_synco */
+
+/* GP0_5 (ZCZ ball D13) gpio3_20 */
+GP0_5_default_pin: pinmux_GP0_5_default_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x09a8, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* mcasp0_axr1.gpio3_20 */
+GP0_5_gpio_pin: pinmux_GP0_5_gpio_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x09a8, PIN_OUTPUT | INPUT_EN | MUX_MODE7) >; };		/* mcasp0_axr1.gpio3_20 */
+GP0_5_gpio_pu_pin: pinmux_GP0_5_gpio_pu_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x09a8, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };	/* mcasp0_axr1.gpio3_20 */
+GP0_5_gpio_pd_pin: pinmux_GP0_5_gpio_pd_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x09a8, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* mcasp0_axr1.gpio3_20 */
+GP0_5_gpio_input_pin: pinmux_GP0_5_gpio_input_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x09a8, PIN_INPUT | MUX_MODE7) >; };			/* mcasp0_axr1.gpio3_20 */
+GP0_5_qep_pin: pinmux_GP0_5_qep_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x09a8, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE1) >; };	/* mcasp0_axr1.eqep0_index */
+GP0_5_pruout_pin: pinmux_GP0_5_pruout_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x09a8, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE5) >; };	/* mcasp0_axr1.pru0_out6 */
+GP0_5_pruin_pin: pinmux_GP0_5_pruin_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x09a8, PIN_INPUT | MUX_MODE6) >; };			/* mcasp0_axr1.pru0_in6 */
+
+/* GP0_6 (ZCZ ball C12) gpio3_17 */
+GP0_6_default_pin: pinmux_GP0_6_default_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x099c, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* mcasp0_ahclkr.gpio3_17 */
+GP0_6_gpio_pin: pinmux_GP0_6_gpio_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x099c, PIN_OUTPUT | INPUT_EN | MUX_MODE7) >; };		/* mcasp0_ahclkr.gpio3_17 */
+GP0_6_gpio_pu_pin: pinmux_GP0_6_gpio_pu_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x099c, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };	/* mcasp0_ahclkr.gpio3_17 */
+GP0_6_gpio_pd_pin: pinmux_GP0_6_gpio_pd_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x099c, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* mcasp0_ahclkr.gpio3_17 */
+GP0_6_gpio_input_pin: pinmux_GP0_6_gpio_input_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x099c, PIN_INPUT | MUX_MODE7) >; };			/* mcasp0_ahclkr.gpio3_17 */
+GP0_6_pwm_pin: pinmux_GP0_6_pwm_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x099c, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE1) >; };	/* mcasp0_ahclkr.ehrpwm0_synci */
+GP0_6_spi_cs_pin: pinmux_GP0_6_spi_cs_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x099c, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE3) >; };	/* mcasp0_ahclkr.spi1_cs0 */
+GP0_6_pruout_pin: pinmux_GP0_6_pruout_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x099c, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE5) >; };	/* mcasp0_ahclkr.pru0_out3 */
+GP0_6_pruin_pin: pinmux_GP0_6_pruin_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x099c, PIN_INPUT | MUX_MODE6) >; };			/* mcasp0_ahclkr.pru0_in3 */
+
+/* GP1_3 (ZCZ ball J15) gpio3_2 */
+GP1_3_default_pin: pinmux_GP1_3_default_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0910, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* gmii1_rxer.gpio3_2 */
+GP1_3_gpio_pin: pinmux_GP1_3_gpio_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0910, PIN_OUTPUT | INPUT_EN | MUX_MODE7) >; };		/* gmii1_rxer.gpio3_2 */
+GP1_3_gpio_pu_pin: pinmux_GP1_3_gpio_pu_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0910, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };	/* gmii1_rxer.gpio3_2 */
+GP1_3_gpio_pd_pin: pinmux_GP1_3_gpio_pd_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0910, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* gmii1_rxer.gpio3_2 */
+GP1_3_gpio_input_pin: pinmux_GP1_3_gpio_input_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0910, PIN_INPUT | MUX_MODE7) >; };			/* gmii1_rxer.gpio3_2 */
+GP1_3_spi_pin: pinmux_GP1_3_spi_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0910, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE2) >; };	/* gmii1_rxer.spi1_d1 */
+GP1_3_i2c_pin: pinmux_GP1_3_i2c_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0910, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE3) >; };	/* gmii1_rxer.i2c1_scl */
+GP1_3_uart_pin: pinmux_GP1_3_uart_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0910, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE6) >; };	/* gmii1_rxer.uart2_txd */
+
+/* GP1_4 (ZCZ ball H17) gpio3_1 */
+GP1_4_default_pin: pinmux_GP1_4_default_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x090c, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* gmii1_crs.gpio3_1 */
+GP1_4_gpio_pin: pinmux_GP1_4_gpio_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x090c, PIN_OUTPUT | INPUT_EN | MUX_MODE7) >; };		/* gmii1_crs.gpio3_1 */
+GP1_4_gpio_pu_pin: pinmux_GP1_4_gpio_pu_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x090c, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };	/* gmii1_crs.gpio3_1 */
+GP1_4_gpio_pd_pin: pinmux_GP1_4_gpio_pd_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x090c, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* gmii1_crs.gpio3_1 */
+GP1_4_gpio_input_pin: pinmux_GP1_4_gpio_input_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x090c, PIN_INPUT | MUX_MODE7) >; };			/* gmii1_crs.gpio3_1 */
+GP1_4_spi_pin: pinmux_GP1_4_spi_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x090c, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE2) >; };	/* gmii1_crs.spi1_d0 */
+GP1_4_i2c_pin: pinmux_GP1_4_i2c_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x090c, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE3) >; };	/* gmii1_crs.i2c1_sda */
+GP1_4_uart_pin: pinmux_GP1_4_uart_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x090c, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE6) >; };	/* gmii1_crs.uart2_rxd */
+
+/* GP1_5 (ZCZ ball R7) gpio2_2 */
+GP1_5_default_pin: pinmux_GP1_5_default_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0890, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };	/* gpmc_advn_ale.gpio2_2 */
+GP1_5_gpio_pin: pinmux_GP1_5_gpio_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0890, PIN_OUTPUT | INPUT_EN | MUX_MODE7) >; };		/* gpmc_advn_ale.gpio2_2 */
+GP1_5_gpio_pu_pin: pinmux_GP1_5_gpio_pu_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0890, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };	/* gpmc_advn_ale.gpio2_2 */
+GP1_5_gpio_pd_pin: pinmux_GP1_5_gpio_pd_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0890, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* gpmc_advn_ale.gpio2_2 */
+GP1_5_gpio_input_pin: pinmux_GP1_5_gpio_input_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0890, PIN_INPUT | MUX_MODE7) >; };			/* gpmc_advn_ale.gpio2_2 */
+
+/* GP1_6 (ZCZ ball T7) gpio2_3 */
+GP1_6_default_pin: pinmux_GP1_6_default_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0894, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };	/* gpmc_oen_ren.gpio2_3 */
+GP1_6_gpio_pin: pinmux_GP1_6_gpio_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0894, PIN_OUTPUT | INPUT_EN | MUX_MODE7) >; };		/* gpmc_oen_ren.gpio2_3 */
+GP1_6_gpio_pu_pin: pinmux_GP1_6_gpio_pu_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0894, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };	/* gpmc_oen_ren.gpio2_3 */
+GP1_6_gpio_pd_pin: pinmux_GP1_6_gpio_pd_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0894, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* gpmc_oen_ren.gpio2_3 */
+GP1_6_gpio_input_pin: pinmux_GP1_6_gpio_input_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0894, PIN_INPUT | MUX_MODE7) >; };			/* gpmc_oen_ren.gpio2_3 */
+
+/* GPS_3 (ZCZ ball A17) uart2_rxd */
+GPS_3_default_pin: pinmux_GPS_3_default_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0950, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE1) >; };	/* spi0_sclk.uart2_rxd */
+GPS_3_gpio_pin: pinmux_GPS_3_gpio_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0950, PIN_OUTPUT | INPUT_EN | MUX_MODE7) >; };		/* spi0_sclk.gpio0_2 */
+GPS_3_gpio_pu_pin: pinmux_GPS_3_gpio_pu_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0950, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };	/* spi0_sclk.gpio0_2 */
+GPS_3_gpio_pd_pin: pinmux_GPS_3_gpio_pd_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0950, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* spi0_sclk.gpio0_2 */
+GPS_3_gpio_input_pin: pinmux_GPS_3_gpio_input_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0950, PIN_INPUT | MUX_MODE7) >; };			/* spi0_sclk.gpio0_2 */
+GPS_3_spi_sclk_pin: pinmux_GPS_3_spi_sclk_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0950, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE0) >; };	/* spi0_sclk.spi0_sclk */
+GPS_3_uart_pin: pinmux_GPS_3_uart_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0950, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE1) >; };	/* spi0_sclk.uart2_rxd */
+GPS_3_i2c_pin: pinmux_GPS_3_i2c_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0950, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE2) >; };	/* spi0_sclk.i2c2_sda */
+GPS_3_pwm_pin: pinmux_GPS_3_pwm_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0950, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE3) >; };	/* spi0_sclk.ehrpwm0a */
+GPS_3_pru_uart_pin: pinmux_GPS_3_pru_uart_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0950, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE4) >; };	/* spi0_sclk.pr1_uart0_cts_n */
+
+/* GPS_4 (ZCZ ball B17) uart2_txd */
+GPS_4_default_pin: pinmux_GPS_4_default_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0954, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE1) >; };	/* spi0_d0.uart2_txd */
+GPS_4_gpio_pin: pinmux_GPS_4_gpio_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0954, PIN_OUTPUT | INPUT_EN | MUX_MODE7) >; };		/* spi0_d0.gpio0_3 */
+GPS_4_gpio_pu_pin: pinmux_GPS_4_gpio_pu_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0954, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };	/* spi0_d0.gpio0_3 */
+GPS_4_gpio_pd_pin: pinmux_GPS_4_gpio_pd_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0954, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* spi0_d0.gpio0_3 */
+GPS_4_gpio_input_pin: pinmux_GPS_4_gpio_input_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0954, PIN_INPUT | MUX_MODE7) >; };			/* spi0_d0.gpio0_3 */
+GPS_4_spi_pin: pinmux_GPS_4_spi_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0954, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE0) >; };	/* spi0_d0.spi0_d0 */
+GPS_4_uart_pin: pinmux_GPS_4_uart_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0954, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE1) >; };	/* spi0_d0.uart2_txd */
+GPS_4_i2c_pin: pinmux_GPS_4_i2c_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0954, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE2) >; };	/* spi0_d0.i2c2_scl */
+GPS_4_pwm_pin: pinmux_GPS_4_pwm_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0954, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE3) >; };	/* spi0_d0.ehrpwm0b */
+GPS_4_pru_uart_pin: pinmux_GPS_4_pru_uart_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0954, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE4) >; };	/* spi0_d0.pr1_uart0_rts_n */
+
+/* SPI1_3 (ZCZ ball D12) spi1_d1 */
+SPI1_3_default_pin: pinmux_SPI1_3_default_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0998, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE3) >; };	/* mcasp0_axr0.spi1_d1 */
+SPI1_3_gpio_pin: pinmux_SPI1_3_gpio_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0998, PIN_OUTPUT | INPUT_EN | MUX_MODE7) >; };		/* mcasp0_axr0.gpio3_16 */
+SPI1_3_gpio_pu_pin: pinmux_SPI1_3_gpio_pu_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0998, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };	/* mcasp0_axr0.gpio3_16 */
+SPI1_3_gpio_pd_pin: pinmux_SPI1_3_gpio_pd_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0998, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* mcasp0_axr0.gpio3_16 */
+SPI1_3_gpio_input_pin: pinmux_SPI1_3_gpio_input_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0998, PIN_INPUT | MUX_MODE7) >; };			/* mcasp0_axr0.gpio3_16 */
+SPI1_3_pwm_pin: pinmux_SPI1_3_pwm_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0998, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE1) >; };	/* mcasp0_axr0.ehrpwm0_tripzone_input */
+SPI1_3_spi_pin: pinmux_SPI1_3_spi_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0998, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE3) >; };	/* mcasp0_axr0.spi1_d1 */
+SPI1_3_pruout_pin: pinmux_SPI1_3_pruout_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0998, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE5) >; };	/* mcasp0_axr0.pru0_out2 */
+SPI1_3_pruin_pin: pinmux_SPI1_3_pruin_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0998, PIN_INPUT | MUX_MODE6) >; };			/* mcasp0_axr0.pru0_in2 */
+
+/* SPI1_4 (ZCZ ball B13) spi1_d0 */
+SPI1_4_default_pin: pinmux_SPI1_4_default_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0994, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE3) >; };	/* mcasp0_fsx.spi1_d0 */
+SPI1_4_gpio_pin: pinmux_SPI1_4_gpio_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0994, PIN_OUTPUT | INPUT_EN | MUX_MODE7) >; };		/* mcasp0_fsx.gpio3_15 */
+SPI1_4_gpio_pu_pin: pinmux_SPI1_4_gpio_pu_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0994, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };	/* mcasp0_fsx.gpio3_15 */
+SPI1_4_gpio_pd_pin: pinmux_SPI1_4_gpio_pd_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0994, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* mcasp0_fsx.gpio3_15 */
+SPI1_4_gpio_input_pin: pinmux_SPI1_4_gpio_input_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0994, PIN_INPUT | MUX_MODE7) >; };			/* mcasp0_fsx.gpio3_15 */
+SPI1_4_pwm_pin: pinmux_SPI1_4_pwm_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0994, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE1) >; };	/* mcasp0_fsx.ehrpwm0b */
+SPI1_4_spi_pin: pinmux_SPI1_4_spi_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0994, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE3) >; };	/* mcasp0_fsx.spi1_d0 */
+SPI1_4_pruout_pin: pinmux_SPI1_4_pruout_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0994, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE5) >; };	/* mcasp0_fsx.pru0_out1 */
+SPI1_4_pruin_pin: pinmux_SPI1_4_pruin_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0994, PIN_INPUT | MUX_MODE6) >; };			/* mcasp0_fsx.pru0_in1 */
+
+/* SPI1_5 (ZCZ ball A13) spi1_sclk */
+SPI1_5_default_pin: pinmux_SPI1_5_default_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0990, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE3) >; };	/* mcasp0_aclkx.spi1_sclk */
+SPI1_5_gpio_pin: pinmux_SPI1_5_gpio_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0990, PIN_OUTPUT | INPUT_EN | MUX_MODE7) >; };		/* mcasp0_aclkx.gpio3_14 */
+SPI1_5_gpio_pu_pin: pinmux_SPI1_5_gpio_pu_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0990, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };	/* mcasp0_aclkx.gpio3_14 */
+SPI1_5_gpio_pd_pin: pinmux_SPI1_5_gpio_pd_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0990, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* mcasp0_aclkx.gpio3_14 */
+SPI1_5_gpio_input_pin: pinmux_SPI1_5_gpio_input_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0990, PIN_INPUT | MUX_MODE7) >; };			/* mcasp0_aclkx.gpio3_14 */
+SPI1_5_pwm_pin: pinmux_SPI1_5_pwm_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0990, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE1) >; };	/* mcasp0_aclkx.ehrpwm0a */
+SPI1_5_spi_sclk_pin: pinmux_SPI1_5_spi_sclk_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0990, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE3) >; };	/* mcasp0_aclkx.spi1_sclk */
+SPI1_5_pruout_pin: pinmux_SPI1_5_pruout_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0990, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE5) >; };	/* mcasp0_aclkx.pru0_out0 */
+SPI1_5_pruin_pin: pinmux_SPI1_5_pruin_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0990, PIN_INPUT | MUX_MODE6) >; };			/* mcasp0_aclkx.pru0_in0 */
+
+/* S1.1_6 (ZCZ ball H18) spi1_cs0 */
+S1.1_6_default_pin: pinmux_S1.1_6_default_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0944, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE2) >; };	/* rmii1_refclk.spi1_cs0 */
+S1.1_6_gpio_pin: pinmux_S1.1_6_gpio_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0944, PIN_OUTPUT | INPUT_EN | MUX_MODE7) >; };		/* rmii1_refclk.gpio0_29 */
+S1.1_6_gpio_pu_pin: pinmux_S1.1_6_gpio_pu_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0944, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };	/* rmii1_refclk.gpio0_29 */
+S1.1_6_gpio_pd_pin: pinmux_S1.1_6_gpio_pd_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0944, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* rmii1_refclk.gpio0_29 */
+S1.1_6_gpio_input_pin: pinmux_S1.1_6_gpio_input_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0944, PIN_INPUT | MUX_MODE7) >; };			/* rmii1_refclk.gpio0_29 */
+S1.1_6_spi_cs_pin: pinmux_S1.1_6_spi_cs_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0944, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE2) >; };	/* rmii1_refclk.spi1_cs0 */
+S1.1_6_uart_pin: pinmux_S1.1_6_uart_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0944, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE3) >; };	/* rmii1_refclk.uart5_txd */
+
+/* S1.2_6 (ZCZ ball C18) spi1_cs1 */
+S1.2_6_default_pin: pinmux_S1.2_6_default_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0964, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE2) >; };	/* eCAP0_in_PWM0_out.spi1_cs1 */
+S1.2_6_gpio_pin: pinmux_S1.2_6_gpio_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0964, PIN_OUTPUT | INPUT_EN | MUX_MODE7) >; };		/* eCAP0_in_PWM0_out.gpio0_7 */
+S1.2_6_gpio_pu_pin: pinmux_S1.2_6_gpio_pu_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0964, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };	/* eCAP0_in_PWM0_out.gpio0_7 */
+S1.2_6_gpio_pd_pin: pinmux_S1.2_6_gpio_pd_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0964, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* eCAP0_in_PWM0_out.gpio0_7 */
+S1.2_6_gpio_input_pin: pinmux_S1.2_6_gpio_input_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0964, PIN_INPUT | MUX_MODE7) >; };			/* eCAP0_in_PWM0_out.gpio0_7 */
+S1.2_6_pwm_pin: pinmux_S1.2_6_pwm_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0964, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE0) >; };	/* eCAP0_in_PWM0_out.ecap0_in_pwm0_out */
+S1.2_6_uart_pin: pinmux_S1.2_6_uart_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0964, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE1) >; };	/* eCAP0_in_PWM0_out.uart3_txd */
+S1.2_6_spi_cs_pin: pinmux_S1.2_6_spi_cs_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0964, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE2) >; };	/* eCAP0_in_PWM0_out.spi1_cs1 */
+S1.2_6_pru_ecap_pin: pinmux_S1.2_6_pru_ecap_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0964, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE3) >; };	/* eCAP0_in_PWM0_out.pr1_ecap0_ecap_capin_apwm_o */
+S1.2_6_spi_sclk_pin: pinmux_S1.2_6_spi_sclk_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0964, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE4) >; };	/* eCAP0_in_PWM0_out.spi1_sclk */
+
+
+
+/* E1_3 (ZCZ ball B12) qep */
+E1_3_pinmux {
+	compatible = "bone-pinmux-helper";
+	status = "okay";
+	pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input", "qep", "pruout", "pruin";
+	pinctrl-0 = <&E1_3_default_pin>;
+	pinctrl-1 = <&E1_3_gpio_pin>;
+	pinctrl-2 = <&E1_3_gpio_pu_pin>;
+	pinctrl-3 = <&E1_3_gpio_pd_pin>;
+	pinctrl-4 = <&E1_3_gpio_input_pin>;
+	pinctrl-5 = <&E1_3_qep_pin>;
+	pinctrl-6 = <&E1_3_pruout_pin>;
+	pinctrl-7 = <&E1_3_pruin_pin>;
+};
+
+/* E1_4 (ZCZ ball C13) qep */
+E1_4_pinmux {
+	compatible = "bone-pinmux-helper";
+	status = "okay";
+	pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input", "qep", "pruout", "pruin";
+	pinctrl-0 = <&E1_4_default_pin>;
+	pinctrl-1 = <&E1_4_gpio_pin>;
+	pinctrl-2 = <&E1_4_gpio_pu_pin>;
+	pinctrl-3 = <&E1_4_gpio_pd_pin>;
+	pinctrl-4 = <&E1_4_gpio_input_pin>;
+	pinctrl-5 = <&E1_4_qep_pin>;
+	pinctrl-6 = <&E1_4_pruout_pin>;
+	pinctrl-7 = <&E1_4_pruin_pin>;
+};
+
+/* E2_3 (ZCZ ball V2) qep */
+E2_3_pinmux {
+	compatible = "bone-pinmux-helper";
+	status = "okay";
+	pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input", "qep";
+	pinctrl-0 = <&E2_3_default_pin>;
+	pinctrl-1 = <&E2_3_gpio_pin>;
+	pinctrl-2 = <&E2_3_gpio_pu_pin>;
+	pinctrl-3 = <&E2_3_gpio_pd_pin>;
+	pinctrl-4 = <&E2_3_gpio_input_pin>;
+	pinctrl-5 = <&E2_3_qep_pin>;
+};
+
+/* E2_4 (ZCZ ball V3) qep */
+E2_4_pinmux {
+	compatible = "bone-pinmux-helper";
+	status = "okay";
+	pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input", "qep";
+	pinctrl-0 = <&E2_4_default_pin>;
+	pinctrl-1 = <&E2_4_gpio_pin>;
+	pinctrl-2 = <&E2_4_gpio_pu_pin>;
+	pinctrl-3 = <&E2_4_gpio_pd_pin>;
+	pinctrl-4 = <&E2_4_gpio_input_pin>;
+	pinctrl-5 = <&E2_4_qep_pin>;
+};
+
+/* E3_3 (ZCZ ball T12) qep */
+E3_3_pinmux {
+	compatible = "bone-pinmux-helper";
+	status = "okay";
+	pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input", "qep", "pruout";
+	pinctrl-0 = <&E3_3_default_pin>;
+	pinctrl-1 = <&E3_3_gpio_pin>;
+	pinctrl-2 = <&E3_3_gpio_pu_pin>;
+	pinctrl-3 = <&E3_3_gpio_pd_pin>;
+	pinctrl-4 = <&E3_3_gpio_input_pin>;
+	pinctrl-5 = <&E3_3_qep_pin>;
+	pinctrl-6 = <&E3_3_pruout_pin>;
+};
+
+/* E3_4 (ZCZ ball R12) qep */
+E3_4_pinmux {
+	compatible = "bone-pinmux-helper";
+	status = "okay";
+	pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input", "qep", "pruout";
+	pinctrl-0 = <&E3_4_default_pin>;
+	pinctrl-1 = <&E3_4_gpio_pin>;
+	pinctrl-2 = <&E3_4_gpio_pu_pin>;
+	pinctrl-3 = <&E3_4_gpio_pd_pin>;
+	pinctrl-4 = <&E3_4_gpio_input_pin>;
+	pinctrl-5 = <&E3_4_qep_pin>;
+	pinctrl-6 = <&E3_4_pruout_pin>;
+};
+
+/* E4_3 (ZCZ ball V13) pruin */
+E4_3_pinmux {
+	compatible = "bone-pinmux-helper";
+	status = "okay";
+	pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input", "qep", "pruin";
+	pinctrl-0 = <&E4_3_default_pin>;
+	pinctrl-1 = <&E4_3_gpio_pin>;
+	pinctrl-2 = <&E4_3_gpio_pu_pin>;
+	pinctrl-3 = <&E4_3_gpio_pd_pin>;
+	pinctrl-4 = <&E4_3_gpio_input_pin>;
+	pinctrl-5 = <&E4_3_qep_pin>;
+	pinctrl-6 = <&E4_3_pruin_pin>;
+};
+
+/* E4_4 (ZCZ ball U13) pruin */
+E4_4_pinmux {
+	compatible = "bone-pinmux-helper";
+	status = "okay";
+	pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input", "qep", "pru_ecap", "pruin";
+	pinctrl-0 = <&E4_4_default_pin>;
+	pinctrl-1 = <&E4_4_gpio_pin>;
+	pinctrl-2 = <&E4_4_gpio_pu_pin>;
+	pinctrl-3 = <&E4_4_gpio_pd_pin>;
+	pinctrl-4 = <&E4_4_gpio_input_pin>;
+	pinctrl-5 = <&E4_4_qep_pin>;
+	pinctrl-6 = <&E4_4_pru_ecap_pin>;
+	pinctrl-7 = <&E4_4_pruin_pin>;
+};
+
+/* UT0_3 (ZCZ ball E15) uart */
+UT0_3_pinmux {
+	compatible = "bone-pinmux-helper";
+	status = "okay";
+	pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input", "spi_cs", "uart", "can", "i2c", "pruout", "pruin";
+	pinctrl-0 = <&UT0_3_default_pin>;
+	pinctrl-1 = <&UT0_3_gpio_pin>;
+	pinctrl-2 = <&UT0_3_gpio_pu_pin>;
+	pinctrl-3 = <&UT0_3_gpio_pd_pin>;
+	pinctrl-4 = <&UT0_3_gpio_input_pin>;
+	pinctrl-5 = <&UT0_3_spi_cs_pin>;
+	pinctrl-6 = <&UT0_3_uart_pin>;
+	pinctrl-7 = <&UT0_3_can_pin>;
+	pinctrl-8 = <&UT0_3_i2c_pin>;
+	pinctrl-9 = <&UT0_3_pruout_pin>;
+	pinctrl-10 = <&UT0_3_pruin_pin>;
+};
+
+/* UT0_4 (ZCZ ball E16) uart */
+UT0_4_pinmux {
+	compatible = "bone-pinmux-helper";
+	status = "okay";
+	pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input", "spi_cs", "uart", "can", "i2c", "pruout", "pruin";
+	pinctrl-0 = <&UT0_4_default_pin>;
+	pinctrl-1 = <&UT0_4_gpio_pin>;
+	pinctrl-2 = <&UT0_4_gpio_pu_pin>;
+	pinctrl-3 = <&UT0_4_gpio_pd_pin>;
+	pinctrl-4 = <&UT0_4_gpio_input_pin>;
+	pinctrl-5 = <&UT0_4_spi_cs_pin>;
+	pinctrl-6 = <&UT0_4_uart_pin>;
+	pinctrl-7 = <&UT0_4_can_pin>;
+	pinctrl-8 = <&UT0_4_i2c_pin>;
+	pinctrl-9 = <&UT0_4_pruout_pin>;
+	pinctrl-10 = <&UT0_4_pruin_pin>;
+};
+
+/* UT1_3 (ZCZ ball D16) uart */
+UT1_3_pinmux {
+	compatible = "bone-pinmux-helper";
+	status = "okay";
+	pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input", "uart", "can", "i2c", "pru_uart", "pruin";
+	pinctrl-0 = <&UT1_3_default_pin>;
+	pinctrl-1 = <&UT1_3_gpio_pin>;
+	pinctrl-2 = <&UT1_3_gpio_pu_pin>;
+	pinctrl-3 = <&UT1_3_gpio_pd_pin>;
+	pinctrl-4 = <&UT1_3_gpio_input_pin>;
+	pinctrl-5 = <&UT1_3_uart_pin>;
+	pinctrl-6 = <&UT1_3_can_pin>;
+	pinctrl-7 = <&UT1_3_i2c_pin>;
+	pinctrl-8 = <&UT1_3_pru_uart_pin>;
+	pinctrl-9 = <&UT1_3_pruin_pin>;
+};
+
+/* UT1_4 (ZCZ ball D15) uart */
+UT1_4_pinmux {
+	compatible = "bone-pinmux-helper";
+	status = "okay";
+	pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input", "uart", "can", "i2c", "pru_uart", "pruin";
+	pinctrl-0 = <&UT1_4_default_pin>;
+	pinctrl-1 = <&UT1_4_gpio_pin>;
+	pinctrl-2 = <&UT1_4_gpio_pu_pin>;
+	pinctrl-3 = <&UT1_4_gpio_pd_pin>;
+	pinctrl-4 = <&UT1_4_gpio_input_pin>;
+	pinctrl-5 = <&UT1_4_uart_pin>;
+	pinctrl-6 = <&UT1_4_can_pin>;
+	pinctrl-7 = <&UT1_4_i2c_pin>;
+	pinctrl-8 = <&UT1_4_pru_uart_pin>;
+	pinctrl-9 = <&UT1_4_pruin_pin>;
+};
+
+/* UT5_3 (ZCZ ball U2) uart */
+UT5_3_pinmux {
+	compatible = "bone-pinmux-helper";
+	status = "okay";
+	pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input", "uart", "pwm";
+	pinctrl-0 = <&UT5_3_default_pin>;
+	pinctrl-1 = <&UT5_3_gpio_pin>;
+	pinctrl-2 = <&UT5_3_gpio_pu_pin>;
+	pinctrl-3 = <&UT5_3_gpio_pd_pin>;
+	pinctrl-4 = <&UT5_3_gpio_input_pin>;
+	pinctrl-5 = <&UT5_3_uart_pin>;
+	pinctrl-6 = <&UT5_3_pwm_pin>;
+};
+
+/* UT5_4 (ZCZ ball U1) uart */
+UT5_4_pinmux {
+	compatible = "bone-pinmux-helper";
+	status = "okay";
+	pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input", "uart", "pwm";
+	pinctrl-0 = <&UT5_4_default_pin>;
+	pinctrl-1 = <&UT5_4_gpio_pin>;
+	pinctrl-2 = <&UT5_4_gpio_pu_pin>;
+	pinctrl-3 = <&UT5_4_gpio_pd_pin>;
+	pinctrl-4 = <&UT5_4_gpio_input_pin>;
+	pinctrl-5 = <&UT5_4_uart_pin>;
+	pinctrl-6 = <&UT5_4_pwm_pin>;
+};
+
+/* DSM2_3 (ZCZ ball T17) uart */
+DSM2_3_pinmux {
+	compatible = "bone-pinmux-helper";
+	status = "okay";
+	pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input", "uart";
+	pinctrl-0 = <&DSM2_3_default_pin>;
+	pinctrl-1 = <&DSM2_3_gpio_pin>;
+	pinctrl-2 = <&DSM2_3_gpio_pu_pin>;
+	pinctrl-3 = <&DSM2_3_gpio_pd_pin>;
+	pinctrl-4 = <&DSM2_3_gpio_input_pin>;
+	pinctrl-5 = <&DSM2_3_uart_pin>;
+};
+
+/* GP0_3 (ZCZ ball U16) */
+GP0_3_pinmux {
+	compatible = "bone-pinmux-helper";
+	status = "okay";
+	pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input";
+	pinctrl-0 = <&GP0_3_default_pin>;
+	pinctrl-1 = <&GP0_3_gpio_pin>;
+	pinctrl-2 = <&GP0_3_gpio_pu_pin>;
+	pinctrl-3 = <&GP0_3_gpio_pd_pin>;
+	pinctrl-4 = <&GP0_3_gpio_input_pin>;
+};
+
+/* GP0_4 (ZCZ ball V14) */
+GP0_4_pinmux {
+	compatible = "bone-pinmux-helper";
+	status = "okay";
+	pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input", "pwm";
+	pinctrl-0 = <&GP0_4_default_pin>;
+	pinctrl-1 = <&GP0_4_gpio_pin>;
+	pinctrl-2 = <&GP0_4_gpio_pu_pin>;
+	pinctrl-3 = <&GP0_4_gpio_pd_pin>;
+	pinctrl-4 = <&GP0_4_gpio_input_pin>;
+	pinctrl-5 = <&GP0_4_pwm_pin>;
+};
+
+/* GP0_5 (ZCZ ball D13) */
+GP0_5_pinmux {
+	compatible = "bone-pinmux-helper";
+	status = "okay";
+	pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input", "qep", "pruout", "pruin";
+	pinctrl-0 = <&GP0_5_default_pin>;
+	pinctrl-1 = <&GP0_5_gpio_pin>;
+	pinctrl-2 = <&GP0_5_gpio_pu_pin>;
+	pinctrl-3 = <&GP0_5_gpio_pd_pin>;
+	pinctrl-4 = <&GP0_5_gpio_input_pin>;
+	pinctrl-5 = <&GP0_5_qep_pin>;
+	pinctrl-6 = <&GP0_5_pruout_pin>;
+	pinctrl-7 = <&GP0_5_pruin_pin>;
+};
+
+/* GP0_6 (ZCZ ball C12) */
+GP0_6_pinmux {
+	compatible = "bone-pinmux-helper";
+	status = "okay";
+	pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input", "spi_cs", "pwm", "pruout", "pruin";
+	pinctrl-0 = <&GP0_6_default_pin>;
+	pinctrl-1 = <&GP0_6_gpio_pin>;
+	pinctrl-2 = <&GP0_6_gpio_pu_pin>;
+	pinctrl-3 = <&GP0_6_gpio_pd_pin>;
+	pinctrl-4 = <&GP0_6_gpio_input_pin>;
+	pinctrl-5 = <&GP0_6_spi_cs_pin>;
+	pinctrl-6 = <&GP0_6_pwm_pin>;
+	pinctrl-7 = <&GP0_6_pruout_pin>;
+	pinctrl-8 = <&GP0_6_pruin_pin>;
+};
+
+/* GP1_3 (ZCZ ball J15) */
+GP1_3_pinmux {
+	compatible = "bone-pinmux-helper";
+	status = "okay";
+	pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input", "spi", "uart", "i2c";
+	pinctrl-0 = <&GP1_3_default_pin>;
+	pinctrl-1 = <&GP1_3_gpio_pin>;
+	pinctrl-2 = <&GP1_3_gpio_pu_pin>;
+	pinctrl-3 = <&GP1_3_gpio_pd_pin>;
+	pinctrl-4 = <&GP1_3_gpio_input_pin>;
+	pinctrl-5 = <&GP1_3_spi_pin>;
+	pinctrl-6 = <&GP1_3_uart_pin>;
+	pinctrl-7 = <&GP1_3_i2c_pin>;
+};
+
+/* GP1_4 (ZCZ ball H17) */
+GP1_4_pinmux {
+	compatible = "bone-pinmux-helper";
+	status = "okay";
+	pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input", "spi", "uart", "i2c";
+	pinctrl-0 = <&GP1_4_default_pin>;
+	pinctrl-1 = <&GP1_4_gpio_pin>;
+	pinctrl-2 = <&GP1_4_gpio_pu_pin>;
+	pinctrl-3 = <&GP1_4_gpio_pd_pin>;
+	pinctrl-4 = <&GP1_4_gpio_input_pin>;
+	pinctrl-5 = <&GP1_4_spi_pin>;
+	pinctrl-6 = <&GP1_4_uart_pin>;
+	pinctrl-7 = <&GP1_4_i2c_pin>;
+};
+
+/* GP1_5 (ZCZ ball R7) */
+GP1_5_pinmux {
+	compatible = "bone-pinmux-helper";
+	status = "okay";
+	pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input";
+	pinctrl-0 = <&GP1_5_default_pin>;
+	pinctrl-1 = <&GP1_5_gpio_pin>;
+	pinctrl-2 = <&GP1_5_gpio_pu_pin>;
+	pinctrl-3 = <&GP1_5_gpio_pd_pin>;
+	pinctrl-4 = <&GP1_5_gpio_input_pin>;
+};
+
+/* GP1_6 (ZCZ ball T7) */
+GP1_6_pinmux {
+	compatible = "bone-pinmux-helper";
+	status = "okay";
+	pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input";
+	pinctrl-0 = <&GP1_6_default_pin>;
+	pinctrl-1 = <&GP1_6_gpio_pin>;
+	pinctrl-2 = <&GP1_6_gpio_pu_pin>;
+	pinctrl-3 = <&GP1_6_gpio_pd_pin>;
+	pinctrl-4 = <&GP1_6_gpio_input_pin>;
+};
+
+/* GPS_3 (ZCZ ball A17) uart */
+GPS_3_pinmux {
+	compatible = "bone-pinmux-helper";
+	status = "okay";
+	pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input", "spi_sclk", "uart", "i2c", "pwm", "pru_uart";
+	pinctrl-0 = <&GPS_3_default_pin>;
+	pinctrl-1 = <&GPS_3_gpio_pin>;
+	pinctrl-2 = <&GPS_3_gpio_pu_pin>;
+	pinctrl-3 = <&GPS_3_gpio_pd_pin>;
+	pinctrl-4 = <&GPS_3_gpio_input_pin>;
+	pinctrl-5 = <&GPS_3_spi_sclk_pin>;
+	pinctrl-6 = <&GPS_3_uart_pin>;
+	pinctrl-7 = <&GPS_3_i2c_pin>;
+	pinctrl-8 = <&GPS_3_pwm_pin>;
+	pinctrl-9 = <&GPS_3_pru_uart_pin>;
+};
+
+/* GPS_4 (ZCZ ball B17) uart */
+GPS_4_pinmux {
+	compatible = "bone-pinmux-helper";
+	status = "okay";
+	pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input", "spi", "uart", "i2c", "pwm", "pru_uart";
+	pinctrl-0 = <&GPS_4_default_pin>;
+	pinctrl-1 = <&GPS_4_gpio_pin>;
+	pinctrl-2 = <&GPS_4_gpio_pu_pin>;
+	pinctrl-3 = <&GPS_4_gpio_pd_pin>;
+	pinctrl-4 = <&GPS_4_gpio_input_pin>;
+	pinctrl-5 = <&GPS_4_spi_pin>;
+	pinctrl-6 = <&GPS_4_uart_pin>;
+	pinctrl-7 = <&GPS_4_i2c_pin>;
+	pinctrl-8 = <&GPS_4_pwm_pin>;
+	pinctrl-9 = <&GPS_4_pru_uart_pin>;
+};
+
+/* SPI1_3 (ZCZ ball D12) spi */
+SPI1_3_pinmux {
+	compatible = "bone-pinmux-helper";
+	status = "okay";
+	pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input", "spi", "pwm", "pruout", "pruin";
+	pinctrl-0 = <&SPI1_3_default_pin>;
+	pinctrl-1 = <&SPI1_3_gpio_pin>;
+	pinctrl-2 = <&SPI1_3_gpio_pu_pin>;
+	pinctrl-3 = <&SPI1_3_gpio_pd_pin>;
+	pinctrl-4 = <&SPI1_3_gpio_input_pin>;
+	pinctrl-5 = <&SPI1_3_spi_pin>;
+	pinctrl-6 = <&SPI1_3_pwm_pin>;
+	pinctrl-7 = <&SPI1_3_pruout_pin>;
+	pinctrl-8 = <&SPI1_3_pruin_pin>;
+};
+
+/* SPI1_4 (ZCZ ball B13) spi */
+SPI1_4_pinmux {
+	compatible = "bone-pinmux-helper";
+	status = "okay";
+	pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input", "spi", "pwm", "pruout", "pruin";
+	pinctrl-0 = <&SPI1_4_default_pin>;
+	pinctrl-1 = <&SPI1_4_gpio_pin>;
+	pinctrl-2 = <&SPI1_4_gpio_pu_pin>;
+	pinctrl-3 = <&SPI1_4_gpio_pd_pin>;
+	pinctrl-4 = <&SPI1_4_gpio_input_pin>;
+	pinctrl-5 = <&SPI1_4_spi_pin>;
+	pinctrl-6 = <&SPI1_4_pwm_pin>;
+	pinctrl-7 = <&SPI1_4_pruout_pin>;
+	pinctrl-8 = <&SPI1_4_pruin_pin>;
+};
+
+/* SPI1_5 (ZCZ ball A13) spi_sclk */
+SPI1_5_pinmux {
+	compatible = "bone-pinmux-helper";
+	status = "okay";
+	pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input", "spi_sclk", "pwm", "pruout", "pruin";
+	pinctrl-0 = <&SPI1_5_default_pin>;
+	pinctrl-1 = <&SPI1_5_gpio_pin>;
+	pinctrl-2 = <&SPI1_5_gpio_pu_pin>;
+	pinctrl-3 = <&SPI1_5_gpio_pd_pin>;
+	pinctrl-4 = <&SPI1_5_gpio_input_pin>;
+	pinctrl-5 = <&SPI1_5_spi_sclk_pin>;
+	pinctrl-6 = <&SPI1_5_pwm_pin>;
+	pinctrl-7 = <&SPI1_5_pruout_pin>;
+	pinctrl-8 = <&SPI1_5_pruin_pin>;
+};
+
+/* S1.1_6 (ZCZ ball H18) spi_cs */
+S1.1_6_pinmux {
+	compatible = "bone-pinmux-helper";
+	status = "okay";
+	pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input", "spi_cs", "uart";
+	pinctrl-0 = <&S1.1_6_default_pin>;
+	pinctrl-1 = <&S1.1_6_gpio_pin>;
+	pinctrl-2 = <&S1.1_6_gpio_pu_pin>;
+	pinctrl-3 = <&S1.1_6_gpio_pd_pin>;
+	pinctrl-4 = <&S1.1_6_gpio_input_pin>;
+	pinctrl-5 = <&S1.1_6_spi_cs_pin>;
+	pinctrl-6 = <&S1.1_6_uart_pin>;
+};
+
+/* S1.2_6 (ZCZ ball C18) spi_cs */
+S1.2_6_pinmux {
+	compatible = "bone-pinmux-helper";
+	status = "okay";
+	pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input", "spi_cs", "spi_sclk", "uart", "pwm", "pru_ecap";
+	pinctrl-0 = <&S1.2_6_default_pin>;
+	pinctrl-1 = <&S1.2_6_gpio_pin>;
+	pinctrl-2 = <&S1.2_6_gpio_pu_pin>;
+	pinctrl-3 = <&S1.2_6_gpio_pd_pin>;
+	pinctrl-4 = <&S1.2_6_gpio_input_pin>;
+	pinctrl-5 = <&S1.2_6_spi_cs_pin>;
+	pinctrl-6 = <&S1.2_6_spi_sclk_pin>;
+	pinctrl-7 = <&S1.2_6_uart_pin>;
+	pinctrl-8 = <&S1.2_6_pwm_pin>;
+	pinctrl-9 = <&S1.2_6_pru_ecap_pin>;
+};
+
+
+cape-universal {
+	compatible = "gpio-of-helper";
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <>;
+
+	E1_3 {
+		gpio-name = "E1_3";
+		gpio = <&gpio3 18 0>;
+		input;
+		dir-changeable;
+	};
+
+	E1_4 {
+		gpio-name = "E1_4";
+		gpio = <&gpio3 19 0>;
+		input;
+		dir-changeable;
+	};
+
+	E2_3 {
+		gpio-name = "E2_3";
+		gpio = <&gpio0 8 0>;
+		input;
+		dir-changeable;
+	};
+
+	E2_4 {
+		gpio-name = "E2_4";
+		gpio = <&gpio0 9 0>;
+		input;
+		dir-changeable;
+	};
+
+	E3_3 {
+		gpio-name = "E3_3";
+		gpio = <&gpio1 12 0>;
+		input;
+		dir-changeable;
+	};
+
+	E3_4 {
+		gpio-name = "E3_4";
+		gpio = <&gpio1 13 0>;
+		input;
+		dir-changeable;
+	};
+
+	E4_3 {
+		gpio-name = "E4_3";
+		gpio = <&gpio1 14 0>;
+		input;
+		dir-changeable;
+	};
+
+	E4_4 {
+		gpio-name = "E4_4";
+		gpio = <&gpio1 15 0>;
+		input;
+		dir-changeable;
+	};
+
+	UT0_3 {
+		gpio-name = "UT0_3";
+		gpio = <&gpio1 10 0>;
+		input;
+		dir-changeable;
+	};
+
+	UT0_4 {
+		gpio-name = "UT0_4";
+		gpio = <&gpio1 11 0>;
+		input;
+		dir-changeable;
+	};
+
+	UT1_3 {
+		gpio-name = "UT1_3";
+		gpio = <&gpio0 14 0>;
+		input;
+		dir-changeable;
+	};
+
+	UT1_4 {
+		gpio-name = "UT1_4";
+		gpio = <&gpio0 15 0>;
+		input;
+		dir-changeable;
+	};
+
+	UT5_3 {
+		gpio-name = "UT5_3";
+		gpio = <&gpio2 15 0>;
+		input;
+		dir-changeable;
+	};
+
+	UT5_4 {
+		gpio-name = "UT5_4";
+		gpio = <&gpio2 14 0>;
+		input;
+		dir-changeable;
+	};
+
+	DSM2_3 {
+		gpio-name = "DSM2_3";
+		gpio = <&gpio0 30 0>;
+		input;
+		dir-changeable;
+	};
+
+	GP0_3 {
+		gpio-name = "GP0_3";
+		gpio = <&gpio1 25 0>;
+		input;
+		dir-changeable;
+	};
+
+	GP0_4 {
+		gpio-name = "GP0_4";
+		gpio = <&gpio1 17 0>;
+		input;
+		dir-changeable;
+	};
+
+	GP0_5 {
+		gpio-name = "GP0_5";
+		gpio = <&gpio3 20 0>;
+		input;
+		dir-changeable;
+	};
+
+	GP0_6 {
+		gpio-name = "GP0_6";
+		gpio = <&gpio3 17 0>;
+		input;
+		dir-changeable;
+	};
+
+	GP1_3 {
+		gpio-name = "GP1_3";
+		gpio = <&gpio3 2 0>;
+		input;
+		dir-changeable;
+	};
+
+	GP1_4 {
+		gpio-name = "GP1_4";
+		gpio = <&gpio3 1 0>;
+		input;
+		dir-changeable;
+	};
+
+	GP1_5 {
+		gpio-name = "GP1_5";
+		gpio = <&gpio2 2 0>;
+		input;
+		dir-changeable;
+	};
+
+	GP1_6 {
+		gpio-name = "GP1_6";
+		gpio = <&gpio2 3 0>;
+		input;
+		dir-changeable;
+	};
+
+	GPS_3 {
+		gpio-name = "GPS_3";
+		gpio = <&gpio0 2 0>;
+		input;
+		dir-changeable;
+	};
+
+	GPS_4 {
+		gpio-name = "GPS_4";
+		gpio = <&gpio0 3 0>;
+		input;
+		dir-changeable;
+	};
+
+	SPI1_3 {
+		gpio-name = "SPI1_3";
+		gpio = <&gpio3 16 0>;
+		input;
+		dir-changeable;
+	};
+
+	SPI1_4 {
+		gpio-name = "SPI1_4";
+		gpio = <&gpio3 15 0>;
+		input;
+		dir-changeable;
+	};
+
+	SPI1_5 {
+		gpio-name = "SPI1_5";
+		gpio = <&gpio3 14 0>;
+		input;
+		dir-changeable;
+	};
+
+	S1.1_6 {
+		gpio-name = "S1.1_6";
+		gpio = <&gpio0 29 0>;
+		input;
+		dir-changeable;
+	};
+
+	S1.2_6 {
+		gpio-name = "S1.2_6";
+		gpio = <&gpio0 7 0>;
+		input;
+		dir-changeable;
+	};
+
+};
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/tools/pinmux-generator/BeagleBone_Blue.sh b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/tools/pinmux-generator/BeagleBone_Blue.sh
new file mode 100644
index 0000000000000000000000000000000000000000..facf8b40d1f81d766528d890f9458bea7685abc4
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/tools/pinmux-generator/BeagleBone_Blue.sh
@@ -0,0 +1,147 @@
+#!/bin/bash
+
+#https://github.com/beagleboard/beaglebone-blue/blob/master/BeagleBone_Blue_sch.pdf
+
+source $(dirname "$0")/lib/pinmux.sh
+
+file="BeagleBone_Blue"
+
+echo "" > ${file}.dts
+echo "" >${file}-pinmux.dts
+echo "" >${file}-gpio.dts
+echo "" >${file}_config-pin.txt
+
+disable_timer="enable"
+
+#BeagleBone Blue
+gpio_index="7"
+
+#E1
+#EQEP_0A
+pcbpin="E1_3" ; ball="B12" ; default_mode="1" ; cp_default="qep" ; find_ball
+#EQEP_0B
+pcbpin="E1_4" ; ball="C13" ; default_mode="1" ; cp_default="qep" ; find_ball
+
+#E2
+#EQEP_1A V2
+gpio_index="6"
+pcbpin="E2_3" ; ball="V2" ; default_mode="2" ; cp_default="qep" ; find_ball
+gpio_index="7"
+
+#EQEP_1B V3
+gpio_index="6"
+pcbpin="E2_4" ; ball="V3" ; default_mode="2" ; cp_default="qep" ; find_ball
+gpio_index="7"
+
+#E3
+#EQEP_1A T12
+pcbpin="E3_3" ; ball="T12" ; default_mode="4" ; cp_default="qep" ; find_ball
+#EQEP_1B R12
+pcbpin="E3_4" ; ball="R12" ; default_mode="4" ; cp_default="qep" ; find_ball
+
+#E4
+#pruin V13
+pcbpin="E4_3" ; ball="V13" ; default_mode="6" ; cp_default="pruin" ; find_ball
+#pruin U13
+pcbpin="E4_4" ; ball="U13" ; default_mode="6" ; cp_default="pruin" ; find_ball
+
+#UT0
+#UART0_RX
+pcbpin="UT0_3" ; ball="E15" ; default_mode="0" ; cp_default="uart" ; find_ball
+#UART0_TX
+pcbpin="UT0_4" ; ball="E16" ; default_mode="0" ; cp_default="uart" ; find_ball
+
+#UT1
+#UART1_RX
+gpio_index="6"
+pcbpin="UT1_3" ; ball="D16" ; default_mode="0" ; cp_default="uart" ; find_ball
+gpio_index="7"
+
+#UART1_TX
+gpio_index="6"
+pcbpin="UT1_4" ; ball="D15" ; default_mode="0" ; cp_default="uart" ; find_ball
+gpio_index="7"
+
+#UT5
+#UART5_RX
+pcbpin="UT5_3" ; ball="U2" ; default_mode="4" ; cp_default="uart" ; find_ball
+#UART5_TX
+pcbpin="UT5_4" ; ball="U1" ; default_mode="4" ; cp_default="uart" ; find_ball
+
+#CAN has to be on...
+
+#DSM2
+#UART4_RX
+pcbpin="DSM2_3" ; ball="T17" ; default_mode="6" ; cp_default="uart" ; find_ball
+
+#i2c has to be on...
+
+#GP0
+gpio_index="6"
+pcbpin="GP0_3" ; ball="U16" ; default_mode="7" ; find_ball
+gpio_index="7"
+
+pcbpin="GP0_4" ; ball="V14" ; default_mode="7" ; find_ball
+
+gpio_index="6"
+pcbpin="GP0_5" ; ball="D13" ; default_mode="7" ; find_ball
+gpio_index="7"
+
+pcbpin="GP0_6" ; ball="C12" ; default_mode="7" ; find_ball
+
+#GP1
+pcbpin="GP1_3" ; ball="J15" ; default_mode="7" ; find_ball
+
+pcbpin="GP1_4" ; ball="H17" ; default_mode="7" ; find_ball
+
+gpio_index="2"
+pcbpin="GP1_5" ; ball="R7" ; default_mode="7" ; find_ball
+gpio_index="7"
+
+gpio_index="2"
+pcbpin="GP1_6" ; ball="T7" ; default_mode="7" ; find_ball
+gpio_index="7"
+
+#ADC
+
+#GPS
+pcbpin="GPS_3" ; ball="A17" ; default_mode="1" ; cp_default="uart" ; find_ball
+pcbpin="GPS_4" ; ball="B17" ; default_mode="1" ; cp_default="uart" ; find_ball
+
+#SPI1
+#SPI1_MOSI
+gpio_index="6"
+pcbpin="SPI1_3" ; ball="D12" ; default_mode="3" ; cp_default="spi" ; find_ball
+gpio_index="7"
+
+#SPI1_MISO
+gpio_index="6"
+pcbpin="SPI1_4" ; ball="B13" ; default_mode="3" ; cp_default="spi" ; find_ball
+gpio_index="7"
+
+#SPI1_SCK
+gpio_index="6"
+pcbpin="SPI1_5" ; ball="A13" ; default_mode="3" ; cp_default="spi_sclk" ; find_ball
+gpio_index="7"
+
+#SPI1_SS1
+pcbpin="S1.1_6" ; ball="H18" ; default_mode="2" ; cp_default="spi_cs" ; find_ball
+#SPI1_SS2
+pcbpin="S1.2_6" ; ball="C18" ; default_mode="2" ; cp_default="spi_cs" ; find_ball
+
+msg="" ; echo_both
+
+cat ${file}-pinmux.dts >> ${file}.dts
+
+echo "cape-universal {" >> ${file}.dts
+echo "	compatible = \"gpio-of-helper\";" >> ${file}.dts
+echo "	status = \"okay\";" >> ${file}.dts
+echo "	pinctrl-names = \"default\";" >> ${file}.dts
+echo "	pinctrl-0 = <>;" >> ${file}.dts
+
+cat ${file}-gpio.dts >> ${file}.dts
+
+echo "};" >> ${file}.dts
+
+rm -rf ${file}-pinmux.dts || true
+rm -rf ${file}-gpio.dts || true
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/tools/pinmux-generator/BeagleBone_Blue_config-pin.txt b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/tools/pinmux-generator/BeagleBone_Blue_config-pin.txt
new file mode 100644
index 0000000000000000000000000000000000000000..4920a604b7f755cb3cd0b3352586ae8d23c75ab6
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/tools/pinmux-generator/BeagleBone_Blue_config-pin.txt
@@ -0,0 +1,211 @@
+
+E1_3_PRU="146"
+E1_3_GPIO="114"
+E1_3_PIN="qep"
+E1_3_PINMUX="default gpio gpio_pu gpio_pd gpio_input qep pruout pruin"
+E1_3_INFO="eqep0a_in default gpio3_18 gpio3_18 gpio3_18 gpio3_18 eqep0a_in pru0_out4 pru0_in4"
+E1_3_CAPE=""
+
+E1_4_PRU="147"
+E1_4_GPIO="115"
+E1_4_PIN="qep"
+E1_4_PINMUX="default gpio gpio_pu gpio_pd gpio_input qep pruout pruin"
+E1_4_INFO="eqep0b_in default gpio3_19 gpio3_19 gpio3_19 gpio3_19 eqep0b_in pru0_out5 pru0_in5"
+E1_4_CAPE=""
+
+E2_3_PRU="40"
+E2_3_GPIO="8"
+E2_3_PIN="qep"
+E2_3_PINMUX="default gpio gpio_pu gpio_pd gpio_input qep"
+E2_3_INFO="eqep1a_in default gpio0_8 gpio0_8 gpio0_8 gpio0_8 eqep1a_in"
+E2_3_CAPE=""
+
+E2_4_PRU="41"
+E2_4_GPIO="9"
+E2_4_PIN="qep"
+E2_4_PINMUX="default gpio gpio_pu gpio_pd gpio_input qep"
+E2_4_INFO="eqep1b_in default gpio0_9 gpio0_9 gpio0_9 gpio0_9 eqep1b_in"
+E2_4_CAPE=""
+
+E3_3_PRU="76"
+E3_3_GPIO="44"
+E3_3_PIN="qep"
+E3_3_PINMUX="default gpio gpio_pu gpio_pd gpio_input qep pruout"
+E3_3_INFO="eqep2a_in default gpio1_12 gpio1_12 gpio1_12 gpio1_12 eqep2a_in pru0_out14"
+E3_3_CAPE=""
+
+E3_4_PRU="77"
+E3_4_GPIO="45"
+E3_4_PIN="qep"
+E3_4_PINMUX="default gpio gpio_pu gpio_pd gpio_input qep pruout"
+E3_4_INFO="eqep2b_in default gpio1_13 gpio1_13 gpio1_13 gpio1_13 eqep2b_in pru0_out15"
+E3_4_CAPE=""
+
+E4_3_PRU="78"
+E4_3_GPIO="46"
+E4_3_PIN="pruin"
+E4_3_PINMUX="default gpio gpio_pu gpio_pd gpio_input qep pruin"
+E4_3_INFO="pru0_in14 default gpio1_14 gpio1_14 gpio1_14 gpio1_14 eqep2_index pru0_in14"
+E4_3_CAPE=""
+
+E4_4_PRU="79"
+E4_4_GPIO="47"
+E4_4_PIN="pruin"
+E4_4_PINMUX="default gpio gpio_pu gpio_pd gpio_input qep pru_ecap pruin"
+E4_4_INFO="pru0_in15 default gpio1_15 gpio1_15 gpio1_15 gpio1_15 eqep2_strobe pru_ecap pru0_in15"
+E4_4_CAPE=""
+
+UT0_3_PRU="74"
+UT0_3_GPIO="42"
+UT0_3_PIN="uart"
+UT0_3_PINMUX="default gpio gpio_pu gpio_pd gpio_input spi_cs uart can i2c pruout pruin"
+UT0_3_INFO="uart0_rxd default gpio1_10 gpio1_10 gpio1_10 gpio1_10 spi1_cs0 uart0_rxd dcan0_tx i2c2_sda pru1_out14 pru1_in14"
+UT0_3_CAPE=""
+
+UT0_4_PRU="75"
+UT0_4_GPIO="43"
+UT0_4_PIN="uart"
+UT0_4_PINMUX="default gpio gpio_pu gpio_pd gpio_input spi_cs uart can i2c pruout pruin"
+UT0_4_INFO="uart0_txd default gpio1_11 gpio1_11 gpio1_11 gpio1_11 spi1_cs1 uart0_txd dcan0_rx i2c2_scl pru1_out15 pru1_in15"
+UT0_4_CAPE=""
+
+UT1_3_PRU="46"
+UT1_3_GPIO="14"
+UT1_3_PIN="uart"
+UT1_3_PINMUX="default gpio gpio_pu gpio_pd gpio_input uart can i2c pru_uart pruin"
+UT1_3_INFO="uart1_rxd default gpio0_14 gpio0_14 gpio0_14 gpio0_14 uart1_rxd dcan1_tx i2c1_sda pru_uart pru1_in16"
+UT1_3_CAPE=""
+
+UT1_4_PRU="47"
+UT1_4_GPIO="15"
+UT1_4_PIN="uart"
+UT1_4_PINMUX="default gpio gpio_pu gpio_pd gpio_input uart can i2c pru_uart pruin"
+UT1_4_INFO="uart1_txd default gpio0_15 gpio0_15 gpio0_15 gpio0_15 uart1_txd dcan1_rx i2c1_scl pru_uart pru0_in16"
+UT1_4_CAPE=""
+
+UT5_3_PRU="111"
+UT5_3_GPIO="79"
+UT5_3_PIN="uart"
+UT5_3_PINMUX="default gpio gpio_pu gpio_pd gpio_input uart pwm"
+UT5_3_INFO="uart5_rxd default gpio2_15 gpio2_15 gpio2_15 gpio2_15 uart5_rxd ehrpwm0_synco"
+UT5_3_CAPE=""
+
+UT5_4_PRU="110"
+UT5_4_GPIO="78"
+UT5_4_PIN="uart"
+UT5_4_PINMUX="default gpio gpio_pu gpio_pd gpio_input uart pwm"
+UT5_4_INFO="uart5_txd default gpio2_14 gpio2_14 gpio2_14 gpio2_14 uart5_txd ehrpwm1_tripzone_input"
+UT5_4_CAPE=""
+
+DSM2_3_PRU="62"
+DSM2_3_GPIO="30"
+DSM2_3_PIN="uart"
+DSM2_3_PINMUX="default gpio gpio_pu gpio_pd gpio_input uart"
+DSM2_3_INFO="uart4_rxd default gpio0_30 gpio0_30 gpio0_30 gpio0_30 uart4_rxd"
+DSM2_3_CAPE=""
+
+GP0_3_PRU="89"
+GP0_3_GPIO="57"
+GP0_3_PIN="gpio"
+GP0_3_PINMUX="default gpio gpio_pu gpio_pd gpio_input"
+GP0_3_INFO="gpio1_25 default gpio1_25 gpio1_25 gpio1_25 gpio1_25"
+GP0_3_CAPE=""
+
+GP0_4_PRU="81"
+GP0_4_GPIO="49"
+GP0_4_PIN="gpio"
+GP0_4_PINMUX="default gpio gpio_pu gpio_pd gpio_input pwm"
+GP0_4_INFO="gpio1_17 default gpio1_17 gpio1_17 gpio1_17 gpio1_17 ehrpwm0_synco"
+GP0_4_CAPE=""
+
+GP0_5_PRU="148"
+GP0_5_GPIO="116"
+GP0_5_PIN="gpio"
+GP0_5_PINMUX="default gpio gpio_pu gpio_pd gpio_input qep pruout pruin"
+GP0_5_INFO="gpio3_20 default gpio3_20 gpio3_20 gpio3_20 gpio3_20 eqep0_index pru0_out6 pru0_in6"
+GP0_5_CAPE=""
+
+GP0_6_PRU="145"
+GP0_6_GPIO="113"
+GP0_6_PIN="gpio"
+GP0_6_PINMUX="default gpio gpio_pu gpio_pd gpio_input spi_cs pwm pruout pruin"
+GP0_6_INFO="gpio3_17 default gpio3_17 gpio3_17 gpio3_17 gpio3_17 spi1_cs0 ehrpwm0_synci pru0_out3 pru0_in3"
+GP0_6_CAPE=""
+
+GP1_3_PRU="130"
+GP1_3_GPIO="98"
+GP1_3_PIN="gpio"
+GP1_3_PINMUX="default gpio gpio_pu gpio_pd gpio_input spi uart i2c"
+GP1_3_INFO="gpio3_2 default gpio3_2 gpio3_2 gpio3_2 gpio3_2 spi1_d1 uart2_txd i2c1_scl"
+GP1_3_CAPE=""
+
+GP1_4_PRU="129"
+GP1_4_GPIO="97"
+GP1_4_PIN="gpio"
+GP1_4_PINMUX="default gpio gpio_pu gpio_pd gpio_input spi uart i2c"
+GP1_4_INFO="gpio3_1 default gpio3_1 gpio3_1 gpio3_1 gpio3_1 spi1_d0 uart2_rxd i2c1_sda"
+GP1_4_CAPE=""
+
+GP1_5_PRU="98"
+GP1_5_GPIO="66"
+GP1_5_PIN="gpio"
+GP1_5_PINMUX="default gpio gpio_pu gpio_pd gpio_input"
+GP1_5_INFO="gpio2_2 default gpio2_2 gpio2_2 gpio2_2 gpio2_2"
+GP1_5_CAPE=""
+
+GP1_6_PRU="99"
+GP1_6_GPIO="67"
+GP1_6_PIN="gpio"
+GP1_6_PINMUX="default gpio gpio_pu gpio_pd gpio_input"
+GP1_6_INFO="gpio2_3 default gpio2_3 gpio2_3 gpio2_3 gpio2_3"
+GP1_6_CAPE=""
+
+GPS_3_PRU="34"
+GPS_3_GPIO="2"
+GPS_3_PIN="uart"
+GPS_3_PINMUX="default gpio gpio_pu gpio_pd gpio_input spi_sclk uart i2c pwm pru_uart"
+GPS_3_INFO="uart2_rxd default gpio0_2 gpio0_2 gpio0_2 gpio0_2 spi0_sclk uart2_rxd i2c2_sda ehrpwm0a pru_uart"
+GPS_3_CAPE=""
+
+GPS_4_PRU="35"
+GPS_4_GPIO="3"
+GPS_4_PIN="uart"
+GPS_4_PINMUX="default gpio gpio_pu gpio_pd gpio_input spi uart i2c pwm pru_uart"
+GPS_4_INFO="uart2_txd default gpio0_3 gpio0_3 gpio0_3 gpio0_3 spi0_d0 uart2_txd i2c2_scl ehrpwm0b pru_uart"
+GPS_4_CAPE=""
+
+SPI1_3_PRU="144"
+SPI1_3_GPIO="112"
+SPI1_3_PIN="spi"
+SPI1_3_PINMUX="default gpio gpio_pu gpio_pd gpio_input spi pwm pruout pruin"
+SPI1_3_INFO="spi1_d1 default gpio3_16 gpio3_16 gpio3_16 gpio3_16 spi1_d1 ehrpwm0_tripzone_input pru0_out2 pru0_in2"
+SPI1_3_CAPE=""
+
+SPI1_4_PRU="143"
+SPI1_4_GPIO="111"
+SPI1_4_PIN="spi"
+SPI1_4_PINMUX="default gpio gpio_pu gpio_pd gpio_input spi pwm pruout pruin"
+SPI1_4_INFO="spi1_d0 default gpio3_15 gpio3_15 gpio3_15 gpio3_15 spi1_d0 ehrpwm0b pru0_out1 pru0_in1"
+SPI1_4_CAPE=""
+
+SPI1_5_PRU="142"
+SPI1_5_GPIO="110"
+SPI1_5_PIN="spi_sclk"
+SPI1_5_PINMUX="default gpio gpio_pu gpio_pd gpio_input spi_sclk pwm pruout pruin"
+SPI1_5_INFO="spi1_sclk default gpio3_14 gpio3_14 gpio3_14 gpio3_14 spi1_sclk ehrpwm0a pru0_out0 pru0_in0"
+SPI1_5_CAPE=""
+
+S1.1_6_PRU="61"
+S1.1_6_GPIO="29"
+S1.1_6_PIN="spi_cs"
+S1.1_6_PINMUX="default gpio gpio_pu gpio_pd gpio_input spi_cs uart"
+S1.1_6_INFO="spi1_cs0 default gpio0_29 gpio0_29 gpio0_29 gpio0_29 spi1_cs0 uart5_txd"
+S1.1_6_CAPE=""
+
+S1.2_6_PRU="39"
+S1.2_6_GPIO="7"
+S1.2_6_PIN="spi_cs"
+S1.2_6_PINMUX="default gpio gpio_pu gpio_pd gpio_input spi_cs spi_sclk uart pwm pru_ecap"
+S1.2_6_INFO="spi1_cs1 default gpio0_7 gpio0_7 gpio0_7 gpio0_7 spi1_cs1 spi1_sclk uart3_txd ecap0_in_pwm0_out pru_ecap"
+S1.2_6_CAPE=""
+
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/tools/pinmux-generator/PocketBeagle.dts b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/tools/pinmux-generator/PocketBeagle.dts
new file mode 100644
index 0000000000000000000000000000000000000000..dd4b0313f247760b719e7c30438827aee6114126
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/tools/pinmux-generator/PocketBeagle.dts
@@ -0,0 +1,1854 @@
+
+/************************/
+/* P1 Header */
+/************************/
+
+/* P1_01                VIN-AC */
+
+/* P1_02 (ZCZ ball R5) gpio2_23 */
+P1_02_default_pin: pinmux_P1_02_default_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08e4, PIN_INPUT | MUX_MODE7) >; };			/* lcd_hsync.gpio2_23 */
+P1_02_gpio_pin: pinmux_P1_02_gpio_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08e4, PIN_OUTPUT | INPUT_EN | MUX_MODE7) >; };		/* lcd_hsync.gpio2_23 */
+P1_02_gpio_pu_pin: pinmux_P1_02_gpio_pu_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08e4, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };	/* lcd_hsync.gpio2_23 */
+P1_02_gpio_pd_pin: pinmux_P1_02_gpio_pd_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08e4, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* lcd_hsync.gpio2_23 */
+P1_02_gpio_input_pin: pinmux_P1_02_gpio_input_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08e4, PIN_INPUT | MUX_MODE7) >; };			/* lcd_hsync.gpio2_23 */
+P1_02_pruout_pin: pinmux_P1_02_pruout_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08e4, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE5) >; };	/* lcd_hsync.pru1_out9 */
+P1_02_pruin_pin: pinmux_P1_02_pruin_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08e4, PIN_INPUT | MUX_MODE6) >; };			/* lcd_hsync.pru1_in9 */
+
+/* P1_03 (ZCZ ball F15)  usb1_vbus_out         */
+
+/* P1_04 (ZCZ ball R6) gpio2_25 */
+P1_04_default_pin: pinmux_P1_04_default_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08ec, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* lcd_ac_bias_en.gpio2_25 */
+P1_04_gpio_pin: pinmux_P1_04_gpio_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08ec, PIN_OUTPUT | INPUT_EN | MUX_MODE7) >; };		/* lcd_ac_bias_en.gpio2_25 */
+P1_04_gpio_pu_pin: pinmux_P1_04_gpio_pu_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08ec, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };	/* lcd_ac_bias_en.gpio2_25 */
+P1_04_gpio_pd_pin: pinmux_P1_04_gpio_pd_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08ec, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* lcd_ac_bias_en.gpio2_25 */
+P1_04_gpio_input_pin: pinmux_P1_04_gpio_input_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08ec, PIN_INPUT | MUX_MODE7) >; };			/* lcd_ac_bias_en.gpio2_25 */
+P1_04_pruout_pin: pinmux_P1_04_pruout_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08ec, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE5) >; };	/* lcd_ac_bias_en.pru1_out11 */
+P1_04_pruin_pin: pinmux_P1_04_pruin_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08ec, PIN_INPUT | MUX_MODE6) >; };			/* lcd_ac_bias_en.pru1_in11 */
+
+/* P1_05 (ZCZ ball T18)  usb1_vbus_in         */
+
+/* P1_06 (ZCZ ball A16) spi0_cs0 */
+P1_06_default_pin: pinmux_P1_06_default_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x095c, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE0) >; };	/* spi0_cs0.spi0_cs0 */
+P1_06_gpio_pin: pinmux_P1_06_gpio_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x095c, PIN_OUTPUT | INPUT_EN | MUX_MODE7) >; };		/* spi0_cs0.gpio0_5 */
+P1_06_gpio_pu_pin: pinmux_P1_06_gpio_pu_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x095c, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };	/* spi0_cs0.gpio0_5 */
+P1_06_gpio_pd_pin: pinmux_P1_06_gpio_pd_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x095c, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* spi0_cs0.gpio0_5 */
+P1_06_gpio_input_pin: pinmux_P1_06_gpio_input_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x095c, PIN_INPUT | MUX_MODE7) >; };			/* spi0_cs0.gpio0_5 */
+P1_06_spi_cs_pin: pinmux_P1_06_spi_cs_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x095c, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE0) >; };	/* spi0_cs0.spi0_cs0 */
+P1_06_i2c_pin: pinmux_P1_06_i2c_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x095c, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE2) >; };	/* spi0_cs0.i2c1_scl */
+P1_06_pwm_pin: pinmux_P1_06_pwm_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x095c, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE3) >; };	/* spi0_cs0.ehrpwm0_synci */
+P1_06_pru_uart_pin: pinmux_P1_06_pru_uart_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x095c, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE4) >; };	/* spi0_cs0.pr1_uart0_txd */
+
+/* P1_07                VIN-USB */
+
+/* P1_08 (ZCZ ball A17) spi0_sclk */
+P1_08_default_pin: pinmux_P1_08_default_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0950, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE0) >; };	/* spi0_sclk.spi0_sclk */
+P1_08_gpio_pin: pinmux_P1_08_gpio_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0950, PIN_OUTPUT | INPUT_EN | MUX_MODE7) >; };		/* spi0_sclk.gpio0_2 */
+P1_08_gpio_pu_pin: pinmux_P1_08_gpio_pu_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0950, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };	/* spi0_sclk.gpio0_2 */
+P1_08_gpio_pd_pin: pinmux_P1_08_gpio_pd_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0950, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* spi0_sclk.gpio0_2 */
+P1_08_gpio_input_pin: pinmux_P1_08_gpio_input_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0950, PIN_INPUT | MUX_MODE7) >; };			/* spi0_sclk.gpio0_2 */
+P1_08_spi_sclk_pin: pinmux_P1_08_spi_sclk_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0950, PIN_INPUT_PULLUP | MUX_MODE0) >; };		/* spi0_sclk.spi0_sclk */
+P1_08_uart_pin: pinmux_P1_08_uart_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0950, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE1) >; };	/* spi0_sclk.uart2_rxd */
+P1_08_i2c_pin: pinmux_P1_08_i2c_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0950, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE2) >; };	/* spi0_sclk.i2c2_sda */
+P1_08_pwm_pin: pinmux_P1_08_pwm_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0950, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE3) >; };	/* spi0_sclk.ehrpwm0a */
+P1_08_pru_uart_pin: pinmux_P1_08_pru_uart_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0950, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE4) >; };	/* spi0_sclk.pr1_uart0_cts_n */
+
+/* P1_09 (ZCZ ball R18)  USB1-DN         */
+
+/* P1_10 (ZCZ ball B17) spi0_d0 */
+P1_10_default_pin: pinmux_P1_10_default_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0954, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE0) >; };	/* spi0_d0.spi0_d0 */
+P1_10_gpio_pin: pinmux_P1_10_gpio_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0954, PIN_OUTPUT | INPUT_EN | MUX_MODE7) >; };		/* spi0_d0.gpio0_3 */
+P1_10_gpio_pu_pin: pinmux_P1_10_gpio_pu_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0954, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };	/* spi0_d0.gpio0_3 */
+P1_10_gpio_pd_pin: pinmux_P1_10_gpio_pd_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0954, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* spi0_d0.gpio0_3 */
+P1_10_gpio_input_pin: pinmux_P1_10_gpio_input_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0954, PIN_INPUT | MUX_MODE7) >; };			/* spi0_d0.gpio0_3 */
+P1_10_spi_pin: pinmux_P1_10_spi_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0954, PIN_INPUT_PULLUP | MUX_MODE0) >; };		/* spi0_d0.spi0_d0 */
+P1_10_uart_pin: pinmux_P1_10_uart_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0954, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE1) >; };	/* spi0_d0.uart2_txd */
+P1_10_i2c_pin: pinmux_P1_10_i2c_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0954, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE2) >; };	/* spi0_d0.i2c2_scl */
+P1_10_pwm_pin: pinmux_P1_10_pwm_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0954, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE3) >; };	/* spi0_d0.ehrpwm0b */
+P1_10_pru_uart_pin: pinmux_P1_10_pru_uart_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0954, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE4) >; };	/* spi0_d0.pr1_uart0_rts_n */
+
+/* P1_11 (ZCZ ball R17)  USB1-DP         */
+
+/* P1_12 (ZCZ ball B16) spi0_d1 */
+P1_12_default_pin: pinmux_P1_12_default_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0958, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE0) >; };	/* spi0_d1.spi0_d1 */
+P1_12_gpio_pin: pinmux_P1_12_gpio_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0958, PIN_OUTPUT | INPUT_EN | MUX_MODE7) >; };		/* spi0_d1.gpio0_4 */
+P1_12_gpio_pu_pin: pinmux_P1_12_gpio_pu_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0958, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };	/* spi0_d1.gpio0_4 */
+P1_12_gpio_pd_pin: pinmux_P1_12_gpio_pd_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0958, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* spi0_d1.gpio0_4 */
+P1_12_gpio_input_pin: pinmux_P1_12_gpio_input_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0958, PIN_INPUT | MUX_MODE7) >; };			/* spi0_d1.gpio0_4 */
+P1_12_spi_pin: pinmux_P1_12_spi_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0958, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE0) >; };	/* spi0_d1.spi0_d1 */
+P1_12_i2c_pin: pinmux_P1_12_i2c_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0958, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE2) >; };	/* spi0_d1.i2c1_sda */
+P1_12_pwm_pin: pinmux_P1_12_pwm_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0958, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE3) >; };	/* spi0_d1.ehrpwm0_tripzone_input */
+P1_12_pru_uart_pin: pinmux_P1_12_pru_uart_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0958, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE4) >; };	/* spi0_d1.pr1_uart0_rxd */
+
+/* P1_13 (ZCZ ball P17)  USB1-ID         */
+
+/* P1_14                VOUT-3.3V */
+
+/* P1_15                GND */
+
+/* P1_16                GND */
+
+/* P1_17 (ZCZ ball A9)  VREFN         */
+
+/* P1_18 (ZCZ ball B9)  VREFP         */
+
+/* P1_19 (ZCZ ball B6)  AIN0         */
+
+/* P1_20 (ZCZ ball D14) gpio0_20 */
+P1_20_default_pin: pinmux_P1_20_default_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x09b4, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* xdma_event_intr1.gpio0_20 */
+P1_20_gpio_pin: pinmux_P1_20_gpio_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x09b4, PIN_OUTPUT | INPUT_EN | MUX_MODE7) >; };		/* xdma_event_intr1.gpio0_20 */
+P1_20_gpio_pu_pin: pinmux_P1_20_gpio_pu_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x09b4, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };	/* xdma_event_intr1.gpio0_20 */
+P1_20_gpio_pd_pin: pinmux_P1_20_gpio_pd_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x09b4, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* xdma_event_intr1.gpio0_20 */
+P1_20_gpio_input_pin: pinmux_P1_20_gpio_input_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x09b4, PIN_INPUT | MUX_MODE7) >; };			/* xdma_event_intr1.gpio0_20 */
+P1_20_pruin_pin: pinmux_P1_20_pruin_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x09b4, PIN_INPUT | MUX_MODE5) >; };			/* xdma_event_intr1.pru0_in16 */
+
+/* P1_21 (ZCZ ball C7)  AIN1         */
+
+/* P1_22                GND */
+
+/* P1_23 (ZCZ ball B7)  AIN2         */
+
+/* P1_24                VOUT-5V */
+
+/* P1_25 (ZCZ ball A7)  AIN3         */
+
+/* P1_26 (ZCZ ball D18) i2c2_sda */
+P1_26_default_pin: pinmux_P1_26_default_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0978, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE3) >; };	/* uart1_ctsn.i2c2_sda */
+P1_26_gpio_pin: pinmux_P1_26_gpio_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0978, PIN_OUTPUT | INPUT_EN | MUX_MODE7) >; };		/* uart1_ctsn.gpio0_12 */
+P1_26_gpio_pu_pin: pinmux_P1_26_gpio_pu_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0978, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };	/* uart1_ctsn.gpio0_12 */
+P1_26_gpio_pd_pin: pinmux_P1_26_gpio_pd_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0978, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* uart1_ctsn.gpio0_12 */
+P1_26_gpio_input_pin: pinmux_P1_26_gpio_input_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0978, PIN_INPUT | MUX_MODE7) >; };			/* uart1_ctsn.gpio0_12 */
+P1_26_can_pin: pinmux_P1_26_can_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0978, PIN_OUTPUT_PULLUP | MUX_MODE2) >; };		/* uart1_ctsn.dcan0_tx */
+P1_26_i2c_pin: pinmux_P1_26_i2c_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0978, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE3) >; };	/* uart1_ctsn.i2c2_sda */
+P1_26_spi_cs_pin: pinmux_P1_26_spi_cs_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0978, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE4) >; };	/* uart1_ctsn.spi1_cs0 */
+P1_26_pru_uart_pin: pinmux_P1_26_pru_uart_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0978, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE5) >; };	/* uart1_ctsn.pr1_uart0_cts_n */
+
+/* P1_27 (ZCZ ball C8)  AIN4         */
+
+/* P1_28 (ZCZ ball D17) i2c2_scl */
+P1_28_default_pin: pinmux_P1_28_default_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x097c, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE3) >; };	/* uart1_rtsn.i2c2_scl */
+P1_28_gpio_pin: pinmux_P1_28_gpio_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x097c, PIN_OUTPUT | INPUT_EN | MUX_MODE7) >; };		/* uart1_rtsn.gpio0_13 */
+P1_28_gpio_pu_pin: pinmux_P1_28_gpio_pu_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x097c, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };	/* uart1_rtsn.gpio0_13 */
+P1_28_gpio_pd_pin: pinmux_P1_28_gpio_pd_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x097c, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* uart1_rtsn.gpio0_13 */
+P1_28_gpio_input_pin: pinmux_P1_28_gpio_input_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x097c, PIN_INPUT | MUX_MODE7) >; };			/* uart1_rtsn.gpio0_13 */
+P1_28_can_pin: pinmux_P1_28_can_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x097c, PIN_INPUT_PULLUP | MUX_MODE2) >; };		/* uart1_rtsn.dcan0_rx */
+P1_28_i2c_pin: pinmux_P1_28_i2c_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x097c, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE3) >; };	/* uart1_rtsn.i2c2_scl */
+P1_28_spi_cs_pin: pinmux_P1_28_spi_cs_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x097c, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE4) >; };	/* uart1_rtsn.spi1_cs1 */
+P1_28_pru_uart_pin: pinmux_P1_28_pru_uart_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x097c, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE5) >; };	/* uart1_rtsn.pr1_uart0_rts_n */
+
+/* P1_29 (ZCZ ball A14) pru0_in7 */
+P1_29_default_pin: pinmux_P1_29_default_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x09ac, PIN_INPUT | MUX_MODE6) >; };			/* mcasp0_ahclkx.pru0_in7 */
+P1_29_gpio_pin: pinmux_P1_29_gpio_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x09ac, PIN_OUTPUT | INPUT_EN | MUX_MODE7) >; };		/* mcasp0_ahclkx.gpio3_21 */
+P1_29_gpio_pu_pin: pinmux_P1_29_gpio_pu_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x09ac, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };	/* mcasp0_ahclkx.gpio3_21 */
+P1_29_gpio_pd_pin: pinmux_P1_29_gpio_pd_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x09ac, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* mcasp0_ahclkx.gpio3_21 */
+P1_29_gpio_input_pin: pinmux_P1_29_gpio_input_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x09ac, PIN_INPUT | MUX_MODE7) >; };			/* mcasp0_ahclkx.gpio3_21 */
+P1_29_qep_pin: pinmux_P1_29_qep_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x09ac, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE1) >; };	/* mcasp0_ahclkx.eqep0_strobe */
+P1_29_pruout_pin: pinmux_P1_29_pruout_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x09ac, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE5) >; };	/* mcasp0_ahclkx.pru0_out7 */
+P1_29_pruin_pin: pinmux_P1_29_pruin_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x09ac, PIN_INPUT | MUX_MODE6) >; };			/* mcasp0_ahclkx.pru0_in7 */
+
+/* P1_30 (ZCZ ball E16) uart0_txd */
+P1_30_default_pin: pinmux_P1_30_default_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0974, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE0) >; };	/* uart0_txd.uart0_txd */
+P1_30_gpio_pin: pinmux_P1_30_gpio_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0974, PIN_OUTPUT | INPUT_EN | MUX_MODE7) >; };		/* uart0_txd.gpio1_11 */
+P1_30_gpio_pu_pin: pinmux_P1_30_gpio_pu_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0974, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };	/* uart0_txd.gpio1_11 */
+P1_30_gpio_pd_pin: pinmux_P1_30_gpio_pd_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0974, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* uart0_txd.gpio1_11 */
+P1_30_gpio_input_pin: pinmux_P1_30_gpio_input_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0974, PIN_INPUT | MUX_MODE7) >; };			/* uart0_txd.gpio1_11 */
+P1_30_uart_pin: pinmux_P1_30_uart_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0974, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE0) >; };	/* uart0_txd.uart0_txd */
+P1_30_spi_cs_pin: pinmux_P1_30_spi_cs_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0974, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE1) >; };	/* uart0_txd.spi1_cs1 */
+P1_30_can_pin: pinmux_P1_30_can_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0974, PIN_INPUT_PULLUP | MUX_MODE2) >; };		/* uart0_txd.dcan0_rx */
+P1_30_i2c_pin: pinmux_P1_30_i2c_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0974, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE3) >; };	/* uart0_txd.i2c2_scl */
+P1_30_pruout_pin: pinmux_P1_30_pruout_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0974, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE5) >; };	/* uart0_txd.pru1_out15 */
+P1_30_pruin_pin: pinmux_P1_30_pruin_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0974, PIN_INPUT | MUX_MODE6) >; };			/* uart0_txd.pru1_in15 */
+
+/* P1_31 (ZCZ ball B12) pru0_in4 */
+P1_31_default_pin: pinmux_P1_31_default_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x09a0, PIN_INPUT | MUX_MODE6) >; };			/* mcasp0_aclkr.pru0_in4 */
+P1_31_gpio_pin: pinmux_P1_31_gpio_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x09a0, PIN_OUTPUT | INPUT_EN | MUX_MODE7) >; };		/* mcasp0_aclkr.gpio3_18 */
+P1_31_gpio_pu_pin: pinmux_P1_31_gpio_pu_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x09a0, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };	/* mcasp0_aclkr.gpio3_18 */
+P1_31_gpio_pd_pin: pinmux_P1_31_gpio_pd_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x09a0, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* mcasp0_aclkr.gpio3_18 */
+P1_31_gpio_input_pin: pinmux_P1_31_gpio_input_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x09a0, PIN_INPUT | MUX_MODE7) >; };			/* mcasp0_aclkr.gpio3_18 */
+P1_31_qep_pin: pinmux_P1_31_qep_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x09a0, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE1) >; };	/* mcasp0_aclkr.eqep0a_in */
+P1_31_pruout_pin: pinmux_P1_31_pruout_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x09a0, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE5) >; };	/* mcasp0_aclkr.pru0_out4 */
+P1_31_pruin_pin: pinmux_P1_31_pruin_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x09a0, PIN_INPUT | MUX_MODE6) >; };			/* mcasp0_aclkr.pru0_in4 */
+
+/* P1_32 (ZCZ ball E15) uart0_rxd */
+P1_32_default_pin: pinmux_P1_32_default_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0970, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE0) >; };	/* uart0_rxd.uart0_rxd */
+P1_32_gpio_pin: pinmux_P1_32_gpio_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0970, PIN_OUTPUT | INPUT_EN | MUX_MODE7) >; };		/* uart0_rxd.gpio1_10 */
+P1_32_gpio_pu_pin: pinmux_P1_32_gpio_pu_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0970, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };	/* uart0_rxd.gpio1_10 */
+P1_32_gpio_pd_pin: pinmux_P1_32_gpio_pd_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0970, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* uart0_rxd.gpio1_10 */
+P1_32_gpio_input_pin: pinmux_P1_32_gpio_input_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0970, PIN_INPUT | MUX_MODE7) >; };			/* uart0_rxd.gpio1_10 */
+P1_32_uart_pin: pinmux_P1_32_uart_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0970, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE0) >; };	/* uart0_rxd.uart0_rxd */
+P1_32_spi_cs_pin: pinmux_P1_32_spi_cs_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0970, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE1) >; };	/* uart0_rxd.spi1_cs0 */
+P1_32_can_pin: pinmux_P1_32_can_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0970, PIN_OUTPUT_PULLUP | MUX_MODE2) >; };		/* uart0_rxd.dcan0_tx */
+P1_32_i2c_pin: pinmux_P1_32_i2c_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0970, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE3) >; };	/* uart0_rxd.i2c2_sda */
+P1_32_pruout_pin: pinmux_P1_32_pruout_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0970, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE5) >; };	/* uart0_rxd.pru1_out14 */
+P1_32_pruin_pin: pinmux_P1_32_pruin_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0970, PIN_INPUT | MUX_MODE6) >; };			/* uart0_rxd.pru1_in14 */
+
+/* P1_33 (ZCZ ball B13) pru0_in1 */
+P1_33_default_pin: pinmux_P1_33_default_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0994, PIN_INPUT | MUX_MODE6) >; };			/* mcasp0_fsx.pru0_in1 */
+P1_33_gpio_pin: pinmux_P1_33_gpio_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0994, PIN_OUTPUT | INPUT_EN | MUX_MODE7) >; };		/* mcasp0_fsx.gpio3_15 */
+P1_33_gpio_pu_pin: pinmux_P1_33_gpio_pu_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0994, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };	/* mcasp0_fsx.gpio3_15 */
+P1_33_gpio_pd_pin: pinmux_P1_33_gpio_pd_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0994, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* mcasp0_fsx.gpio3_15 */
+P1_33_gpio_input_pin: pinmux_P1_33_gpio_input_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0994, PIN_INPUT | MUX_MODE7) >; };			/* mcasp0_fsx.gpio3_15 */
+P1_33_pwm_pin: pinmux_P1_33_pwm_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0994, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE1) >; };	/* mcasp0_fsx.ehrpwm0b */
+P1_33_spi_pin: pinmux_P1_33_spi_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0994, PIN_INPUT_PULLUP | MUX_MODE3) >; };		/* mcasp0_fsx.spi1_d0 */
+P1_33_pruout_pin: pinmux_P1_33_pruout_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0994, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE5) >; };	/* mcasp0_fsx.pru0_out1 */
+P1_33_pruin_pin: pinmux_P1_33_pruin_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0994, PIN_INPUT | MUX_MODE6) >; };			/* mcasp0_fsx.pru0_in1 */
+
+/* P1_34 (ZCZ ball T11) gpio0_26 */
+P1_34_default_pin: pinmux_P1_34_default_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0828, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* gpmc_ad10.gpio0_26 */
+P1_34_gpio_pin: pinmux_P1_34_gpio_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0828, PIN_OUTPUT | INPUT_EN | MUX_MODE7) >; };		/* gpmc_ad10.gpio0_26 */
+P1_34_gpio_pu_pin: pinmux_P1_34_gpio_pu_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0828, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };	/* gpmc_ad10.gpio0_26 */
+P1_34_gpio_pd_pin: pinmux_P1_34_gpio_pd_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0828, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* gpmc_ad10.gpio0_26 */
+P1_34_gpio_input_pin: pinmux_P1_34_gpio_input_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0828, PIN_INPUT | MUX_MODE7) >; };			/* gpmc_ad10.gpio0_26 */
+P1_34_pwm_pin: pinmux_P1_34_pwm_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0828, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE4) >; };	/* gpmc_ad10.ehrpwm2_tripzone_input */
+
+/* P1_35 (ZCZ ball V5) pru1_in10 */
+P1_35_default_pin: pinmux_P1_35_default_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08e8, PIN_INPUT | MUX_MODE6) >; };			/* lcd_pclk.pru1_in10 */
+P1_35_gpio_pin: pinmux_P1_35_gpio_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08e8, PIN_OUTPUT | INPUT_EN | MUX_MODE7) >; };		/* lcd_pclk.gpio2_24 */
+P1_35_gpio_pu_pin: pinmux_P1_35_gpio_pu_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08e8, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };	/* lcd_pclk.gpio2_24 */
+P1_35_gpio_pd_pin: pinmux_P1_35_gpio_pd_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08e8, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* lcd_pclk.gpio2_24 */
+P1_35_gpio_input_pin: pinmux_P1_35_gpio_input_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08e8, PIN_INPUT | MUX_MODE7) >; };			/* lcd_pclk.gpio2_24 */
+P1_35_pruout_pin: pinmux_P1_35_pruout_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08e8, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE5) >; };	/* lcd_pclk.pru1_out10 */
+P1_35_pruin_pin: pinmux_P1_35_pruin_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08e8, PIN_INPUT | MUX_MODE6) >; };			/* lcd_pclk.pru1_in10 */
+
+/* P1_36 (ZCZ ball A13) ehrpwm0a */
+P1_36_default_pin: pinmux_P1_36_default_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0990, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE1) >; };	/* mcasp0_aclkx.ehrpwm0a */
+P1_36_gpio_pin: pinmux_P1_36_gpio_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0990, PIN_OUTPUT | INPUT_EN | MUX_MODE7) >; };		/* mcasp0_aclkx.gpio3_14 */
+P1_36_gpio_pu_pin: pinmux_P1_36_gpio_pu_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0990, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };	/* mcasp0_aclkx.gpio3_14 */
+P1_36_gpio_pd_pin: pinmux_P1_36_gpio_pd_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0990, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* mcasp0_aclkx.gpio3_14 */
+P1_36_gpio_input_pin: pinmux_P1_36_gpio_input_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0990, PIN_INPUT | MUX_MODE7) >; };			/* mcasp0_aclkx.gpio3_14 */
+P1_36_pwm_pin: pinmux_P1_36_pwm_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0990, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE1) >; };	/* mcasp0_aclkx.ehrpwm0a */
+P1_36_spi_sclk_pin: pinmux_P1_36_spi_sclk_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0990, PIN_INPUT_PULLUP | MUX_MODE3) >; };		/* mcasp0_aclkx.spi1_sclk */
+P1_36_pruout_pin: pinmux_P1_36_pruout_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0990, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE5) >; };	/* mcasp0_aclkx.pru0_out0 */
+P1_36_pruin_pin: pinmux_P1_36_pruin_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0990, PIN_INPUT | MUX_MODE6) >; };			/* mcasp0_aclkx.pru0_in0 */
+
+
+/************************/
+/* P2 Header */
+/************************/
+
+/* P2_01 (ZCZ ball U14) ehrpwm1a */
+P2_01_default_pin: pinmux_P2_01_default_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0848, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE6) >; };	/* gpmc_a2.ehrpwm1a */
+P2_01_gpio_pin: pinmux_P2_01_gpio_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0848, PIN_OUTPUT | INPUT_EN | MUX_MODE7) >; };		/* gpmc_a2.gpio1_18 */
+P2_01_gpio_pu_pin: pinmux_P2_01_gpio_pu_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0848, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };	/* gpmc_a2.gpio1_18 */
+P2_01_gpio_pd_pin: pinmux_P2_01_gpio_pd_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0848, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* gpmc_a2.gpio1_18 */
+P2_01_gpio_input_pin: pinmux_P2_01_gpio_input_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0848, PIN_INPUT | MUX_MODE7) >; };			/* gpmc_a2.gpio1_18 */
+P2_01_pwm_pin: pinmux_P2_01_pwm_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0848, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE6) >; };	/* gpmc_a2.ehrpwm1a */
+
+/* P2_02 (ZCZ ball V17) gpio1_27 */
+P2_02_default_pin: pinmux_P2_02_default_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x086c, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* gpmc_a11.gpio1_27 */
+P2_02_gpio_pin: pinmux_P2_02_gpio_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x086c, PIN_OUTPUT | INPUT_EN | MUX_MODE7) >; };		/* gpmc_a11.gpio1_27 */
+P2_02_gpio_pu_pin: pinmux_P2_02_gpio_pu_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x086c, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };	/* gpmc_a11.gpio1_27 */
+P2_02_gpio_pd_pin: pinmux_P2_02_gpio_pd_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x086c, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* gpmc_a11.gpio1_27 */
+P2_02_gpio_input_pin: pinmux_P2_02_gpio_input_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x086c, PIN_INPUT | MUX_MODE7) >; };			/* gpmc_a11.gpio1_27 */
+
+/* P2_03 (ZCZ ball T10) gpio0_23 */
+P2_03_default_pin: pinmux_P2_03_default_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0824, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* gpmc_ad9.gpio0_23 */
+P2_03_gpio_pin: pinmux_P2_03_gpio_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0824, PIN_OUTPUT | INPUT_EN | MUX_MODE7) >; };		/* gpmc_ad9.gpio0_23 */
+P2_03_gpio_pu_pin: pinmux_P2_03_gpio_pu_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0824, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };	/* gpmc_ad9.gpio0_23 */
+P2_03_gpio_pd_pin: pinmux_P2_03_gpio_pd_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0824, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* gpmc_ad9.gpio0_23 */
+P2_03_gpio_input_pin: pinmux_P2_03_gpio_input_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0824, PIN_INPUT | MUX_MODE7) >; };			/* gpmc_ad9.gpio0_23 */
+P2_03_pwm_pin: pinmux_P2_03_pwm_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0824, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE4) >; };	/* gpmc_ad9.ehrpwm2b */
+
+/* P2_04 (ZCZ ball T16) gpio1_26 */
+P2_04_default_pin: pinmux_P2_04_default_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0868, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* gpmc_a10.gpio1_26 */
+P2_04_gpio_pin: pinmux_P2_04_gpio_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0868, PIN_OUTPUT | INPUT_EN | MUX_MODE7) >; };		/* gpmc_a10.gpio1_26 */
+P2_04_gpio_pu_pin: pinmux_P2_04_gpio_pu_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0868, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };	/* gpmc_a10.gpio1_26 */
+P2_04_gpio_pd_pin: pinmux_P2_04_gpio_pd_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0868, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* gpmc_a10.gpio1_26 */
+P2_04_gpio_input_pin: pinmux_P2_04_gpio_input_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0868, PIN_INPUT | MUX_MODE7) >; };			/* gpmc_a10.gpio1_26 */
+
+/* P2_05 (ZCZ ball T17) uart4_rxd */
+P2_05_default_pin: pinmux_P2_05_default_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0870, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE6) >; };	/* gpmc_wait0.uart4_rxd */
+P2_05_gpio_pin: pinmux_P2_05_gpio_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0870, PIN_OUTPUT | INPUT_EN | MUX_MODE7) >; };		/* gpmc_wait0.gpio0_30 */
+P2_05_gpio_pu_pin: pinmux_P2_05_gpio_pu_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0870, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };	/* gpmc_wait0.gpio0_30 */
+P2_05_gpio_pd_pin: pinmux_P2_05_gpio_pd_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0870, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* gpmc_wait0.gpio0_30 */
+P2_05_gpio_input_pin: pinmux_P2_05_gpio_input_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0870, PIN_INPUT | MUX_MODE7) >; };			/* gpmc_wait0.gpio0_30 */
+P2_05_uart_pin: pinmux_P2_05_uart_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0870, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE6) >; };	/* gpmc_wait0.uart4_rxd */
+
+/* P2_06 (ZCZ ball U16) gpio1_25 */
+P2_06_default_pin: pinmux_P2_06_default_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0864, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* gpmc_a9.gpio1_25 */
+P2_06_gpio_pin: pinmux_P2_06_gpio_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0864, PIN_OUTPUT | INPUT_EN | MUX_MODE7) >; };		/* gpmc_a9.gpio1_25 */
+P2_06_gpio_pu_pin: pinmux_P2_06_gpio_pu_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0864, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };	/* gpmc_a9.gpio1_25 */
+P2_06_gpio_pd_pin: pinmux_P2_06_gpio_pd_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0864, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* gpmc_a9.gpio1_25 */
+P2_06_gpio_input_pin: pinmux_P2_06_gpio_input_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0864, PIN_INPUT | MUX_MODE7) >; };			/* gpmc_a9.gpio1_25 */
+
+/* P2_07 (ZCZ ball U17) uart4_txd */
+P2_07_default_pin: pinmux_P2_07_default_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0874, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE6) >; };	/* gpmc_wpn.uart4_txd */
+P2_07_gpio_pin: pinmux_P2_07_gpio_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0874, PIN_OUTPUT | INPUT_EN | MUX_MODE7) >; };		/* gpmc_wpn.gpio0_31 */
+P2_07_gpio_pu_pin: pinmux_P2_07_gpio_pu_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0874, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };	/* gpmc_wpn.gpio0_31 */
+P2_07_gpio_pd_pin: pinmux_P2_07_gpio_pd_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0874, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* gpmc_wpn.gpio0_31 */
+P2_07_gpio_input_pin: pinmux_P2_07_gpio_input_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0874, PIN_INPUT | MUX_MODE7) >; };			/* gpmc_wpn.gpio0_31 */
+P2_07_uart_pin: pinmux_P2_07_uart_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0874, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE6) >; };	/* gpmc_wpn.uart4_txd */
+
+/* P2_08 (ZCZ ball U18) gpio1_28 */
+P2_08_default_pin: pinmux_P2_08_default_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0878, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };	/* gpmc_be1n.gpio1_28 */
+P2_08_gpio_pin: pinmux_P2_08_gpio_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0878, PIN_OUTPUT | INPUT_EN | MUX_MODE7) >; };		/* gpmc_be1n.gpio1_28 */
+P2_08_gpio_pu_pin: pinmux_P2_08_gpio_pu_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0878, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };	/* gpmc_be1n.gpio1_28 */
+P2_08_gpio_pd_pin: pinmux_P2_08_gpio_pd_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0878, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* gpmc_be1n.gpio1_28 */
+P2_08_gpio_input_pin: pinmux_P2_08_gpio_input_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0878, PIN_INPUT | MUX_MODE7) >; };			/* gpmc_be1n.gpio1_28 */
+
+/* P2_09 (ZCZ ball D15) i2c1_scl */
+P2_09_default_pin: pinmux_P2_09_default_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0984, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE3) >; };	/* uart1_txd.i2c1_scl */
+P2_09_gpio_pin: pinmux_P2_09_gpio_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0984, PIN_OUTPUT | INPUT_EN | MUX_MODE7) >; };		/* uart1_txd.gpio0_15 */
+P2_09_gpio_pu_pin: pinmux_P2_09_gpio_pu_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0984, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };	/* uart1_txd.gpio0_15 */
+P2_09_gpio_pd_pin: pinmux_P2_09_gpio_pd_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0984, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* uart1_txd.gpio0_15 */
+P2_09_gpio_input_pin: pinmux_P2_09_gpio_input_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0984, PIN_INPUT | MUX_MODE7) >; };			/* uart1_txd.gpio0_15 */
+P2_09_uart_pin: pinmux_P2_09_uart_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0984, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE0) >; };	/* uart1_txd.uart1_txd */
+P2_09_can_pin: pinmux_P2_09_can_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0984, PIN_INPUT_PULLUP | MUX_MODE2) >; };		/* uart1_txd.dcan1_rx */
+P2_09_i2c_pin: pinmux_P2_09_i2c_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0984, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE3) >; };	/* uart1_txd.i2c1_scl */
+P2_09_pru_uart_pin: pinmux_P2_09_pru_uart_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0984, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE5) >; };	/* uart1_txd.pr1_uart0_txd */
+P2_09_pruin_pin: pinmux_P2_09_pruin_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0984, PIN_INPUT | MUX_MODE6) >; };			/* uart1_txd.pru0_in16 */
+
+/* P2_10 (ZCZ ball R14) gpio1_20 */
+P2_10_default_pin: pinmux_P2_10_default_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0850, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* gpmc_a4.gpio1_20 */
+P2_10_gpio_pin: pinmux_P2_10_gpio_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0850, PIN_OUTPUT | INPUT_EN | MUX_MODE7) >; };		/* gpmc_a4.gpio1_20 */
+P2_10_gpio_pu_pin: pinmux_P2_10_gpio_pu_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0850, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };	/* gpmc_a4.gpio1_20 */
+P2_10_gpio_pd_pin: pinmux_P2_10_gpio_pd_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0850, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* gpmc_a4.gpio1_20 */
+P2_10_gpio_input_pin: pinmux_P2_10_gpio_input_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0850, PIN_INPUT | MUX_MODE7) >; };			/* gpmc_a4.gpio1_20 */
+P2_10_qep_pin: pinmux_P2_10_qep_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0850, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE6) >; };	/* gpmc_a4.eqep1a_in */
+
+/* P2_11 (ZCZ ball D16) i2c1_sda */
+P2_11_default_pin: pinmux_P2_11_default_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0980, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE3) >; };	/* uart1_rxd.i2c1_sda */
+P2_11_gpio_pin: pinmux_P2_11_gpio_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0980, PIN_OUTPUT | INPUT_EN | MUX_MODE7) >; };		/* uart1_rxd.gpio0_14 */
+P2_11_gpio_pu_pin: pinmux_P2_11_gpio_pu_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0980, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };	/* uart1_rxd.gpio0_14 */
+P2_11_gpio_pd_pin: pinmux_P2_11_gpio_pd_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0980, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* uart1_rxd.gpio0_14 */
+P2_11_gpio_input_pin: pinmux_P2_11_gpio_input_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0980, PIN_INPUT | MUX_MODE7) >; };			/* uart1_rxd.gpio0_14 */
+P2_11_uart_pin: pinmux_P2_11_uart_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0980, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE0) >; };	/* uart1_rxd.uart1_rxd */
+P2_11_can_pin: pinmux_P2_11_can_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0980, PIN_OUTPUT_PULLUP | MUX_MODE2) >; };		/* uart1_rxd.dcan1_tx */
+P2_11_i2c_pin: pinmux_P2_11_i2c_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0980, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE3) >; };	/* uart1_rxd.i2c1_sda */
+P2_11_pru_uart_pin: pinmux_P2_11_pru_uart_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0980, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE5) >; };	/* uart1_rxd.pr1_uart0_rxd */
+P2_11_pruin_pin: pinmux_P2_11_pruin_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0980, PIN_INPUT | MUX_MODE6) >; };			/* uart1_rxd.pru1_in16 */
+
+/* P2_12                POWER_BUTTON */
+
+/* P2_13                VOUT-5V */
+
+/* P2_14                BAT-VIN */
+
+/* P2_15                GND */
+
+/* P2_16                BAT-TEMP */
+
+/* P2_17 (ZCZ ball V12) gpio2_1 */
+P2_17_default_pin: pinmux_P2_17_default_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x088c, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* gpmc_clk.gpio2_1 */
+P2_17_gpio_pin: pinmux_P2_17_gpio_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x088c, PIN_OUTPUT | INPUT_EN | MUX_MODE7) >; };		/* gpmc_clk.gpio2_1 */
+P2_17_gpio_pu_pin: pinmux_P2_17_gpio_pu_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x088c, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };	/* gpmc_clk.gpio2_1 */
+P2_17_gpio_pd_pin: pinmux_P2_17_gpio_pd_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x088c, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* gpmc_clk.gpio2_1 */
+P2_17_gpio_input_pin: pinmux_P2_17_gpio_input_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x088c, PIN_INPUT | MUX_MODE7) >; };			/* gpmc_clk.gpio2_1 */
+
+/* P2_18 (ZCZ ball U13) gpio1_15 */
+P2_18_default_pin: pinmux_P2_18_default_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x083c, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* gpmc_ad15.gpio1_15 */
+P2_18_gpio_pin: pinmux_P2_18_gpio_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x083c, PIN_OUTPUT | INPUT_EN | MUX_MODE7) >; };		/* gpmc_ad15.gpio1_15 */
+P2_18_gpio_pu_pin: pinmux_P2_18_gpio_pu_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x083c, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };	/* gpmc_ad15.gpio1_15 */
+P2_18_gpio_pd_pin: pinmux_P2_18_gpio_pd_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x083c, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* gpmc_ad15.gpio1_15 */
+P2_18_gpio_input_pin: pinmux_P2_18_gpio_input_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x083c, PIN_INPUT | MUX_MODE7) >; };			/* gpmc_ad15.gpio1_15 */
+P2_18_qep_pin: pinmux_P2_18_qep_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x083c, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE4) >; };	/* gpmc_ad15.eqep2_strobe */
+P2_18_pru_ecap_pin: pinmux_P2_18_pru_ecap_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x083c, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE5) >; };	/* gpmc_ad15.pr1_ecap0_ecap_capin_apwm_o */
+P2_18_pruin_pin: pinmux_P2_18_pruin_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x083c, PIN_INPUT | MUX_MODE6) >; };			/* gpmc_ad15.pru0_in15 */
+
+/* P2_19 (ZCZ ball U12) gpio0_27 */
+P2_19_default_pin: pinmux_P2_19_default_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x082c, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* gpmc_ad11.gpio0_27 */
+P2_19_gpio_pin: pinmux_P2_19_gpio_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x082c, PIN_OUTPUT | INPUT_EN | MUX_MODE7) >; };		/* gpmc_ad11.gpio0_27 */
+P2_19_gpio_pu_pin: pinmux_P2_19_gpio_pu_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x082c, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };	/* gpmc_ad11.gpio0_27 */
+P2_19_gpio_pd_pin: pinmux_P2_19_gpio_pd_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x082c, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* gpmc_ad11.gpio0_27 */
+P2_19_gpio_input_pin: pinmux_P2_19_gpio_input_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x082c, PIN_INPUT | MUX_MODE7) >; };			/* gpmc_ad11.gpio0_27 */
+P2_19_pwm_pin: pinmux_P2_19_pwm_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x082c, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE4) >; };	/* gpmc_ad11.ehrpwm0_synco */
+
+/* P2_20 (ZCZ ball T13) gpio2_0 */
+P2_20_default_pin: pinmux_P2_20_default_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0888, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };	/* gpmc_csn3.gpio2_0 */
+P2_20_gpio_pin: pinmux_P2_20_gpio_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0888, PIN_OUTPUT | INPUT_EN | MUX_MODE7) >; };		/* gpmc_csn3.gpio2_0 */
+P2_20_gpio_pu_pin: pinmux_P2_20_gpio_pu_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0888, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };	/* gpmc_csn3.gpio2_0 */
+P2_20_gpio_pd_pin: pinmux_P2_20_gpio_pd_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0888, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* gpmc_csn3.gpio2_0 */
+P2_20_gpio_input_pin: pinmux_P2_20_gpio_input_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0888, PIN_INPUT | MUX_MODE7) >; };			/* gpmc_csn3.gpio2_0 */
+
+/* P2_21                GND */
+
+/* P2_22 (ZCZ ball V13) gpio1_14 */
+P2_22_default_pin: pinmux_P2_22_default_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0838, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* gpmc_ad14.gpio1_14 */
+P2_22_gpio_pin: pinmux_P2_22_gpio_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0838, PIN_OUTPUT | INPUT_EN | MUX_MODE7) >; };		/* gpmc_ad14.gpio1_14 */
+P2_22_gpio_pu_pin: pinmux_P2_22_gpio_pu_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0838, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };	/* gpmc_ad14.gpio1_14 */
+P2_22_gpio_pd_pin: pinmux_P2_22_gpio_pd_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0838, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* gpmc_ad14.gpio1_14 */
+P2_22_gpio_input_pin: pinmux_P2_22_gpio_input_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0838, PIN_INPUT | MUX_MODE7) >; };			/* gpmc_ad14.gpio1_14 */
+P2_22_qep_pin: pinmux_P2_22_qep_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0838, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE4) >; };	/* gpmc_ad14.eqep2_index */
+P2_22_pruin_pin: pinmux_P2_22_pruin_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0838, PIN_INPUT | MUX_MODE6) >; };			/* gpmc_ad14.pru0_in14 */
+
+/* P2_23                VOUT-3.3V */
+
+/* P2_24 (ZCZ ball T12) gpio1_12 */
+P2_24_default_pin: pinmux_P2_24_default_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0830, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* gpmc_ad12.gpio1_12 */
+P2_24_gpio_pin: pinmux_P2_24_gpio_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0830, PIN_OUTPUT | INPUT_EN | MUX_MODE7) >; };		/* gpmc_ad12.gpio1_12 */
+P2_24_gpio_pu_pin: pinmux_P2_24_gpio_pu_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0830, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };	/* gpmc_ad12.gpio1_12 */
+P2_24_gpio_pd_pin: pinmux_P2_24_gpio_pd_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0830, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* gpmc_ad12.gpio1_12 */
+P2_24_gpio_input_pin: pinmux_P2_24_gpio_input_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0830, PIN_INPUT | MUX_MODE7) >; };			/* gpmc_ad12.gpio1_12 */
+P2_24_qep_pin: pinmux_P2_24_qep_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0830, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE4) >; };	/* gpmc_ad12.eqep2a_in */
+P2_24_pruout_pin: pinmux_P2_24_pruout_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0830, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE6) >; };	/* gpmc_ad12.pru0_out14 */
+
+/* P2_25 (ZCZ ball E17) spi1_d1 */
+P2_25_default_pin: pinmux_P2_25_default_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x096c, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE4) >; };	/* uart0_rtsn.spi1_d1 */
+P2_25_gpio_pin: pinmux_P2_25_gpio_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x096c, PIN_OUTPUT | INPUT_EN | MUX_MODE7) >; };		/* uart0_rtsn.gpio1_9 */
+P2_25_gpio_pu_pin: pinmux_P2_25_gpio_pu_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x096c, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };	/* uart0_rtsn.gpio1_9 */
+P2_25_gpio_pd_pin: pinmux_P2_25_gpio_pd_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x096c, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* uart0_rtsn.gpio1_9 */
+P2_25_gpio_input_pin: pinmux_P2_25_gpio_input_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x096c, PIN_INPUT | MUX_MODE7) >; };			/* uart0_rtsn.gpio1_9 */
+P2_25_uart_pin: pinmux_P2_25_uart_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x096c, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE1) >; };	/* uart0_rtsn.uart4_txd */
+P2_25_can_pin: pinmux_P2_25_can_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x096c, PIN_INPUT_PULLUP | MUX_MODE2) >; };		/* uart0_rtsn.dcan1_rx */
+P2_25_i2c_pin: pinmux_P2_25_i2c_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x096c, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE3) >; };	/* uart0_rtsn.i2c1_scl */
+P2_25_spi_pin: pinmux_P2_25_spi_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x096c, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE4) >; };	/* uart0_rtsn.spi1_d1 */
+P2_25_spi_cs_pin: pinmux_P2_25_spi_cs_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x096c, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE5) >; };	/* uart0_rtsn.spi1_cs0 */
+
+/* P2_26                RESET# */
+
+/* P2_27 (ZCZ ball E18) spi1_d0 */
+P2_27_default_pin: pinmux_P2_27_default_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0968, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE4) >; };	/* uart0_ctsn.spi1_d0 */
+P2_27_gpio_pin: pinmux_P2_27_gpio_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0968, PIN_OUTPUT | INPUT_EN | MUX_MODE7) >; };		/* uart0_ctsn.gpio1_8 */
+P2_27_gpio_pu_pin: pinmux_P2_27_gpio_pu_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0968, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };	/* uart0_ctsn.gpio1_8 */
+P2_27_gpio_pd_pin: pinmux_P2_27_gpio_pd_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0968, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* uart0_ctsn.gpio1_8 */
+P2_27_gpio_input_pin: pinmux_P2_27_gpio_input_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0968, PIN_INPUT | MUX_MODE7) >; };			/* uart0_ctsn.gpio1_8 */
+P2_27_uart_pin: pinmux_P2_27_uart_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0968, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE1) >; };	/* uart0_ctsn.uart4_rxd */
+P2_27_can_pin: pinmux_P2_27_can_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0968, PIN_OUTPUT_PULLUP | MUX_MODE2) >; };		/* uart0_ctsn.dcan1_tx */
+P2_27_i2c_pin: pinmux_P2_27_i2c_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0968, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE3) >; };	/* uart0_ctsn.i2c1_sda */
+P2_27_spi_pin: pinmux_P2_27_spi_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0968, PIN_INPUT_PULLUP | MUX_MODE4) >; };		/* uart0_ctsn.spi1_d0 */
+
+/* P2_28 (ZCZ ball D13) pru0_in6 */
+P2_28_default_pin: pinmux_P2_28_default_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x09a8, PIN_INPUT | MUX_MODE6) >; };			/* mcasp0_axr1.pru0_in6 */
+P2_28_gpio_pin: pinmux_P2_28_gpio_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x09a8, PIN_OUTPUT | INPUT_EN | MUX_MODE7) >; };		/* mcasp0_axr1.gpio3_20 */
+P2_28_gpio_pu_pin: pinmux_P2_28_gpio_pu_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x09a8, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };	/* mcasp0_axr1.gpio3_20 */
+P2_28_gpio_pd_pin: pinmux_P2_28_gpio_pd_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x09a8, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* mcasp0_axr1.gpio3_20 */
+P2_28_gpio_input_pin: pinmux_P2_28_gpio_input_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x09a8, PIN_INPUT | MUX_MODE7) >; };			/* mcasp0_axr1.gpio3_20 */
+P2_28_qep_pin: pinmux_P2_28_qep_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x09a8, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE1) >; };	/* mcasp0_axr1.eqep0_index */
+P2_28_pruout_pin: pinmux_P2_28_pruout_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x09a8, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE5) >; };	/* mcasp0_axr1.pru0_out6 */
+P2_28_pruin_pin: pinmux_P2_28_pruin_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x09a8, PIN_INPUT | MUX_MODE6) >; };			/* mcasp0_axr1.pru0_in6 */
+
+/* P2_29 (ZCZ ball C18) spi1_sclk */
+P2_29_default_pin: pinmux_P2_29_default_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0964, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE4) >; };	/* eCAP0_in_PWM0_out.spi1_sclk */
+P2_29_gpio_pin: pinmux_P2_29_gpio_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0964, PIN_OUTPUT | INPUT_EN | MUX_MODE7) >; };		/* eCAP0_in_PWM0_out.gpio0_7 */
+P2_29_gpio_pu_pin: pinmux_P2_29_gpio_pu_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0964, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };	/* eCAP0_in_PWM0_out.gpio0_7 */
+P2_29_gpio_pd_pin: pinmux_P2_29_gpio_pd_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0964, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* eCAP0_in_PWM0_out.gpio0_7 */
+P2_29_gpio_input_pin: pinmux_P2_29_gpio_input_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0964, PIN_INPUT | MUX_MODE7) >; };			/* eCAP0_in_PWM0_out.gpio0_7 */
+P2_29_pwm_pin: pinmux_P2_29_pwm_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0964, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE0) >; };	/* eCAP0_in_PWM0_out.ecap0_in_pwm0_out */
+P2_29_uart_pin: pinmux_P2_29_uart_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0964, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE1) >; };	/* eCAP0_in_PWM0_out.uart3_txd */
+P2_29_spi_cs_pin: pinmux_P2_29_spi_cs_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0964, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE2) >; };	/* eCAP0_in_PWM0_out.spi1_cs1 */
+P2_29_pru_ecap_pin: pinmux_P2_29_pru_ecap_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0964, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE3) >; };	/* eCAP0_in_PWM0_out.pr1_ecap0_ecap_capin_apwm_o */
+P2_29_spi_sclk_pin: pinmux_P2_29_spi_sclk_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0964, PIN_INPUT_PULLUP | MUX_MODE4) >; };		/* eCAP0_in_PWM0_out.spi1_sclk */
+
+/* P2_30 (ZCZ ball C12) pru0_in3 */
+P2_30_default_pin: pinmux_P2_30_default_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x099c, PIN_INPUT | MUX_MODE6) >; };			/* mcasp0_ahclkr.pru0_in3 */
+P2_30_gpio_pin: pinmux_P2_30_gpio_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x099c, PIN_OUTPUT | INPUT_EN | MUX_MODE7) >; };		/* mcasp0_ahclkr.gpio3_17 */
+P2_30_gpio_pu_pin: pinmux_P2_30_gpio_pu_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x099c, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };	/* mcasp0_ahclkr.gpio3_17 */
+P2_30_gpio_pd_pin: pinmux_P2_30_gpio_pd_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x099c, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* mcasp0_ahclkr.gpio3_17 */
+P2_30_gpio_input_pin: pinmux_P2_30_gpio_input_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x099c, PIN_INPUT | MUX_MODE7) >; };			/* mcasp0_ahclkr.gpio3_17 */
+P2_30_pwm_pin: pinmux_P2_30_pwm_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x099c, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE1) >; };	/* mcasp0_ahclkr.ehrpwm0_synci */
+P2_30_spi_cs_pin: pinmux_P2_30_spi_cs_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x099c, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE3) >; };	/* mcasp0_ahclkr.spi1_cs0 */
+P2_30_pruout_pin: pinmux_P2_30_pruout_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x099c, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE5) >; };	/* mcasp0_ahclkr.pru0_out3 */
+P2_30_pruin_pin: pinmux_P2_30_pruin_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x099c, PIN_INPUT | MUX_MODE6) >; };			/* mcasp0_ahclkr.pru0_in3 */
+
+/* P2_31 (ZCZ ball A15) spi1_cs1 */
+P2_31_default_pin: pinmux_P2_31_default_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x09b0, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE4) >; };	/* xdma_event_intr0.spi1_cs1 */
+P2_31_gpio_pin: pinmux_P2_31_gpio_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x09b0, PIN_OUTPUT | INPUT_EN | MUX_MODE7) >; };		/* xdma_event_intr0.gpio0_19 */
+P2_31_gpio_pu_pin: pinmux_P2_31_gpio_pu_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x09b0, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };	/* xdma_event_intr0.gpio0_19 */
+P2_31_gpio_pd_pin: pinmux_P2_31_gpio_pd_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x09b0, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* xdma_event_intr0.gpio0_19 */
+P2_31_gpio_input_pin: pinmux_P2_31_gpio_input_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x09b0, PIN_INPUT | MUX_MODE7) >; };			/* xdma_event_intr0.gpio0_19 */
+P2_31_spi_cs_pin: pinmux_P2_31_spi_cs_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x09b0, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE4) >; };	/* xdma_event_intr0.spi1_cs1 */
+P2_31_pruin_pin: pinmux_P2_31_pruin_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x09b0, PIN_INPUT | MUX_MODE5) >; };			/* xdma_event_intr0.pru1_in16 */
+
+/* P2_32 (ZCZ ball D12) pru0_in2 */
+P2_32_default_pin: pinmux_P2_32_default_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0998, PIN_INPUT | MUX_MODE6) >; };			/* mcasp0_axr0.pru0_in2 */
+P2_32_gpio_pin: pinmux_P2_32_gpio_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0998, PIN_OUTPUT | INPUT_EN | MUX_MODE7) >; };		/* mcasp0_axr0.gpio3_16 */
+P2_32_gpio_pu_pin: pinmux_P2_32_gpio_pu_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0998, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };	/* mcasp0_axr0.gpio3_16 */
+P2_32_gpio_pd_pin: pinmux_P2_32_gpio_pd_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0998, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* mcasp0_axr0.gpio3_16 */
+P2_32_gpio_input_pin: pinmux_P2_32_gpio_input_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0998, PIN_INPUT | MUX_MODE7) >; };			/* mcasp0_axr0.gpio3_16 */
+P2_32_pwm_pin: pinmux_P2_32_pwm_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0998, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE1) >; };	/* mcasp0_axr0.ehrpwm0_tripzone_input */
+P2_32_spi_pin: pinmux_P2_32_spi_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0998, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE3) >; };	/* mcasp0_axr0.spi1_d1 */
+P2_32_pruout_pin: pinmux_P2_32_pruout_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0998, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE5) >; };	/* mcasp0_axr0.pru0_out2 */
+P2_32_pruin_pin: pinmux_P2_32_pruin_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0998, PIN_INPUT | MUX_MODE6) >; };			/* mcasp0_axr0.pru0_in2 */
+
+/* P2_33 (ZCZ ball R12) gpio1_13 */
+P2_33_default_pin: pinmux_P2_33_default_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0834, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* gpmc_ad13.gpio1_13 */
+P2_33_gpio_pin: pinmux_P2_33_gpio_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0834, PIN_OUTPUT | INPUT_EN | MUX_MODE7) >; };		/* gpmc_ad13.gpio1_13 */
+P2_33_gpio_pu_pin: pinmux_P2_33_gpio_pu_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0834, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };	/* gpmc_ad13.gpio1_13 */
+P2_33_gpio_pd_pin: pinmux_P2_33_gpio_pd_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0834, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* gpmc_ad13.gpio1_13 */
+P2_33_gpio_input_pin: pinmux_P2_33_gpio_input_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0834, PIN_INPUT | MUX_MODE7) >; };			/* gpmc_ad13.gpio1_13 */
+P2_33_qep_pin: pinmux_P2_33_qep_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0834, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE4) >; };	/* gpmc_ad13.eqep2b_in */
+P2_33_pruout_pin: pinmux_P2_33_pruout_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x0834, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE6) >; };	/* gpmc_ad13.pru0_out15 */
+
+/* P2_34 (ZCZ ball C13) pru0_in5 */
+P2_34_default_pin: pinmux_P2_34_default_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x09a4, PIN_INPUT | MUX_MODE6) >; };			/* mcasp0_fsr.pru0_in5 */
+P2_34_gpio_pin: pinmux_P2_34_gpio_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x09a4, PIN_OUTPUT | INPUT_EN | MUX_MODE7) >; };		/* mcasp0_fsr.gpio3_19 */
+P2_34_gpio_pu_pin: pinmux_P2_34_gpio_pu_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x09a4, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };	/* mcasp0_fsr.gpio3_19 */
+P2_34_gpio_pd_pin: pinmux_P2_34_gpio_pd_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x09a4, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* mcasp0_fsr.gpio3_19 */
+P2_34_gpio_input_pin: pinmux_P2_34_gpio_input_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x09a4, PIN_INPUT | MUX_MODE7) >; };			/* mcasp0_fsr.gpio3_19 */
+P2_34_qep_pin: pinmux_P2_34_qep_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x09a4, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE1) >; };	/* mcasp0_fsr.eqep0b_in */
+P2_34_pruout_pin: pinmux_P2_34_pruout_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x09a4, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE5) >; };	/* mcasp0_fsr.pru0_out5 */
+P2_34_pruin_pin: pinmux_P2_34_pruin_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x09a4, PIN_INPUT | MUX_MODE6) >; };			/* mcasp0_fsr.pru0_in5 */
+
+/* P2_35 (ZCZ ball U5) gpio2_22 */
+P2_35_default_pin: pinmux_P2_35_default_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08e0, PIN_INPUT | MUX_MODE7) >; };			/* lcd_vsync.gpio2_22 */
+P2_35_gpio_pin: pinmux_P2_35_gpio_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08e0, PIN_OUTPUT | INPUT_EN | MUX_MODE7) >; };		/* lcd_vsync.gpio2_22 */
+P2_35_gpio_pu_pin: pinmux_P2_35_gpio_pu_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08e0, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) >; };	/* lcd_vsync.gpio2_22 */
+P2_35_gpio_pd_pin: pinmux_P2_35_gpio_pd_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08e0, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7) >; };	/* lcd_vsync.gpio2_22 */
+P2_35_gpio_input_pin: pinmux_P2_35_gpio_input_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08e0, PIN_INPUT | MUX_MODE7) >; };			/* lcd_vsync.gpio2_22 */
+P2_35_pruout_pin: pinmux_P2_35_pruout_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08e0, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE5) >; };	/* lcd_vsync.pru1_out8 */
+P2_35_pruin_pin: pinmux_P2_35_pruin_pin { pinctrl-single,pins = <
+	AM33XX_IOPAD(0x08e0, PIN_INPUT | MUX_MODE6) >; };			/* lcd_vsync.pru1_in8 */
+
+/* P2_36 (ZCZ ball C9)  AIN7         */
+
+
+/************************/
+/* P1 Header */
+/************************/
+
+/* P1_01                VIN-AC */
+
+/* P1_02 (ZCZ ball R5) gpio_input */
+P1_02_pinmux {
+	compatible = "bone-pinmux-helper";
+	status = "okay";
+	pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input", "pruout", "pruin";
+	pinctrl-0 = <&P1_02_default_pin>;
+	pinctrl-1 = <&P1_02_gpio_pin>;
+	pinctrl-2 = <&P1_02_gpio_pu_pin>;
+	pinctrl-3 = <&P1_02_gpio_pd_pin>;
+	pinctrl-4 = <&P1_02_gpio_input_pin>;
+	pinctrl-5 = <&P1_02_pruout_pin>;
+	pinctrl-6 = <&P1_02_pruin_pin>;
+};
+
+/* P1_03 (ZCZ ball F15)  usb1_vbus_out         */
+
+/* P1_04 (ZCZ ball R6) */
+P1_04_pinmux {
+	compatible = "bone-pinmux-helper";
+	status = "okay";
+	pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input", "pruout", "pruin";
+	pinctrl-0 = <&P1_04_default_pin>;
+	pinctrl-1 = <&P1_04_gpio_pin>;
+	pinctrl-2 = <&P1_04_gpio_pu_pin>;
+	pinctrl-3 = <&P1_04_gpio_pd_pin>;
+	pinctrl-4 = <&P1_04_gpio_input_pin>;
+	pinctrl-5 = <&P1_04_pruout_pin>;
+	pinctrl-6 = <&P1_04_pruin_pin>;
+};
+
+/* P1_05 (ZCZ ball T18)  usb1_vbus_in         */
+
+/* P1_06 (ZCZ ball A16) spi_cs */
+P1_06_pinmux {
+	compatible = "bone-pinmux-helper";
+	status = "okay";
+	pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input", "spi_cs", "i2c", "pwm", "pru_uart";
+	pinctrl-0 = <&P1_06_default_pin>;
+	pinctrl-1 = <&P1_06_gpio_pin>;
+	pinctrl-2 = <&P1_06_gpio_pu_pin>;
+	pinctrl-3 = <&P1_06_gpio_pd_pin>;
+	pinctrl-4 = <&P1_06_gpio_input_pin>;
+	pinctrl-5 = <&P1_06_spi_cs_pin>;
+	pinctrl-6 = <&P1_06_i2c_pin>;
+	pinctrl-7 = <&P1_06_pwm_pin>;
+	pinctrl-8 = <&P1_06_pru_uart_pin>;
+};
+
+/* P1_07                VIN-USB */
+
+/* P1_08 (ZCZ ball A17) spi_sclk */
+P1_08_pinmux {
+	compatible = "bone-pinmux-helper";
+	status = "okay";
+	pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input", "spi_sclk", "uart", "i2c", "pwm", "pru_uart";
+	pinctrl-0 = <&P1_08_default_pin>;
+	pinctrl-1 = <&P1_08_gpio_pin>;
+	pinctrl-2 = <&P1_08_gpio_pu_pin>;
+	pinctrl-3 = <&P1_08_gpio_pd_pin>;
+	pinctrl-4 = <&P1_08_gpio_input_pin>;
+	pinctrl-5 = <&P1_08_spi_sclk_pin>;
+	pinctrl-6 = <&P1_08_uart_pin>;
+	pinctrl-7 = <&P1_08_i2c_pin>;
+	pinctrl-8 = <&P1_08_pwm_pin>;
+	pinctrl-9 = <&P1_08_pru_uart_pin>;
+};
+
+/* P1_09 (ZCZ ball R18)  USB1-DN         */
+
+/* P1_10 (ZCZ ball B17) spi */
+P1_10_pinmux {
+	compatible = "bone-pinmux-helper";
+	status = "okay";
+	pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input", "spi", "uart", "i2c", "pwm", "pru_uart";
+	pinctrl-0 = <&P1_10_default_pin>;
+	pinctrl-1 = <&P1_10_gpio_pin>;
+	pinctrl-2 = <&P1_10_gpio_pu_pin>;
+	pinctrl-3 = <&P1_10_gpio_pd_pin>;
+	pinctrl-4 = <&P1_10_gpio_input_pin>;
+	pinctrl-5 = <&P1_10_spi_pin>;
+	pinctrl-6 = <&P1_10_uart_pin>;
+	pinctrl-7 = <&P1_10_i2c_pin>;
+	pinctrl-8 = <&P1_10_pwm_pin>;
+	pinctrl-9 = <&P1_10_pru_uart_pin>;
+};
+
+/* P1_11 (ZCZ ball R17)  USB1-DP         */
+
+/* P1_12 (ZCZ ball B16) spi */
+P1_12_pinmux {
+	compatible = "bone-pinmux-helper";
+	status = "okay";
+	pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input", "spi", "i2c", "pwm", "pru_uart";
+	pinctrl-0 = <&P1_12_default_pin>;
+	pinctrl-1 = <&P1_12_gpio_pin>;
+	pinctrl-2 = <&P1_12_gpio_pu_pin>;
+	pinctrl-3 = <&P1_12_gpio_pd_pin>;
+	pinctrl-4 = <&P1_12_gpio_input_pin>;
+	pinctrl-5 = <&P1_12_spi_pin>;
+	pinctrl-6 = <&P1_12_i2c_pin>;
+	pinctrl-7 = <&P1_12_pwm_pin>;
+	pinctrl-8 = <&P1_12_pru_uart_pin>;
+};
+
+/* P1_13 (ZCZ ball P17)  USB1-ID         */
+
+/* P1_14                VOUT-3.3V */
+
+/* P1_15                GND */
+
+/* P1_16                GND */
+
+/* P1_17 (ZCZ ball A9)  VREFN         */
+
+/* P1_18 (ZCZ ball B9)  VREFP         */
+
+/* P1_19 (ZCZ ball B6)  AIN0         */
+
+/* P1_20 (ZCZ ball D14) */
+P1_20_pinmux {
+	compatible = "bone-pinmux-helper";
+	status = "okay";
+	pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input", "pruin";
+	pinctrl-0 = <&P1_20_default_pin>;
+	pinctrl-1 = <&P1_20_gpio_pin>;
+	pinctrl-2 = <&P1_20_gpio_pu_pin>;
+	pinctrl-3 = <&P1_20_gpio_pd_pin>;
+	pinctrl-4 = <&P1_20_gpio_input_pin>;
+	pinctrl-5 = <&P1_20_pruin_pin>;
+};
+
+/* P1_21 (ZCZ ball C7)  AIN1         */
+
+/* P1_22                GND */
+
+/* P1_23 (ZCZ ball B7)  AIN2         */
+
+/* P1_24                VOUT-5V */
+
+/* P1_25 (ZCZ ball A7)  AIN3         */
+
+/* P1_26 (ZCZ ball D18) i2c */
+P1_26_pinmux {
+	compatible = "bone-pinmux-helper";
+	status = "okay";
+	pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input", "spi_cs", "can", "i2c", "pru_uart";
+	pinctrl-0 = <&P1_26_default_pin>;
+	pinctrl-1 = <&P1_26_gpio_pin>;
+	pinctrl-2 = <&P1_26_gpio_pu_pin>;
+	pinctrl-3 = <&P1_26_gpio_pd_pin>;
+	pinctrl-4 = <&P1_26_gpio_input_pin>;
+	pinctrl-5 = <&P1_26_spi_cs_pin>;
+	pinctrl-6 = <&P1_26_can_pin>;
+	pinctrl-7 = <&P1_26_i2c_pin>;
+	pinctrl-8 = <&P1_26_pru_uart_pin>;
+};
+
+/* P1_27 (ZCZ ball C8)  AIN4         */
+
+/* P1_28 (ZCZ ball D17) i2c */
+P1_28_pinmux {
+	compatible = "bone-pinmux-helper";
+	status = "okay";
+	pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input", "spi_cs", "can", "i2c", "pru_uart";
+	pinctrl-0 = <&P1_28_default_pin>;
+	pinctrl-1 = <&P1_28_gpio_pin>;
+	pinctrl-2 = <&P1_28_gpio_pu_pin>;
+	pinctrl-3 = <&P1_28_gpio_pd_pin>;
+	pinctrl-4 = <&P1_28_gpio_input_pin>;
+	pinctrl-5 = <&P1_28_spi_cs_pin>;
+	pinctrl-6 = <&P1_28_can_pin>;
+	pinctrl-7 = <&P1_28_i2c_pin>;
+	pinctrl-8 = <&P1_28_pru_uart_pin>;
+};
+
+/* P1_29 (ZCZ ball A14) pruin */
+P1_29_pinmux {
+	compatible = "bone-pinmux-helper";
+	status = "okay";
+	pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input", "qep", "pruout", "pruin";
+	pinctrl-0 = <&P1_29_default_pin>;
+	pinctrl-1 = <&P1_29_gpio_pin>;
+	pinctrl-2 = <&P1_29_gpio_pu_pin>;
+	pinctrl-3 = <&P1_29_gpio_pd_pin>;
+	pinctrl-4 = <&P1_29_gpio_input_pin>;
+	pinctrl-5 = <&P1_29_qep_pin>;
+	pinctrl-6 = <&P1_29_pruout_pin>;
+	pinctrl-7 = <&P1_29_pruin_pin>;
+};
+
+/* P1_30 (ZCZ ball E16) uart */
+P1_30_pinmux {
+	compatible = "bone-pinmux-helper";
+	status = "okay";
+	pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input", "spi_cs", "uart", "can", "i2c", "pruout", "pruin";
+	pinctrl-0 = <&P1_30_default_pin>;
+	pinctrl-1 = <&P1_30_gpio_pin>;
+	pinctrl-2 = <&P1_30_gpio_pu_pin>;
+	pinctrl-3 = <&P1_30_gpio_pd_pin>;
+	pinctrl-4 = <&P1_30_gpio_input_pin>;
+	pinctrl-5 = <&P1_30_spi_cs_pin>;
+	pinctrl-6 = <&P1_30_uart_pin>;
+	pinctrl-7 = <&P1_30_can_pin>;
+	pinctrl-8 = <&P1_30_i2c_pin>;
+	pinctrl-9 = <&P1_30_pruout_pin>;
+	pinctrl-10 = <&P1_30_pruin_pin>;
+};
+
+/* P1_31 (ZCZ ball B12) pruin */
+P1_31_pinmux {
+	compatible = "bone-pinmux-helper";
+	status = "okay";
+	pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input", "qep", "pruout", "pruin";
+	pinctrl-0 = <&P1_31_default_pin>;
+	pinctrl-1 = <&P1_31_gpio_pin>;
+	pinctrl-2 = <&P1_31_gpio_pu_pin>;
+	pinctrl-3 = <&P1_31_gpio_pd_pin>;
+	pinctrl-4 = <&P1_31_gpio_input_pin>;
+	pinctrl-5 = <&P1_31_qep_pin>;
+	pinctrl-6 = <&P1_31_pruout_pin>;
+	pinctrl-7 = <&P1_31_pruin_pin>;
+};
+
+/* P1_32 (ZCZ ball E15) uart */
+P1_32_pinmux {
+	compatible = "bone-pinmux-helper";
+	status = "okay";
+	pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input", "spi_cs", "uart", "can", "i2c", "pruout", "pruin";
+	pinctrl-0 = <&P1_32_default_pin>;
+	pinctrl-1 = <&P1_32_gpio_pin>;
+	pinctrl-2 = <&P1_32_gpio_pu_pin>;
+	pinctrl-3 = <&P1_32_gpio_pd_pin>;
+	pinctrl-4 = <&P1_32_gpio_input_pin>;
+	pinctrl-5 = <&P1_32_spi_cs_pin>;
+	pinctrl-6 = <&P1_32_uart_pin>;
+	pinctrl-7 = <&P1_32_can_pin>;
+	pinctrl-8 = <&P1_32_i2c_pin>;
+	pinctrl-9 = <&P1_32_pruout_pin>;
+	pinctrl-10 = <&P1_32_pruin_pin>;
+};
+
+/* P1_33 (ZCZ ball B13) pruin */
+P1_33_pinmux {
+	compatible = "bone-pinmux-helper";
+	status = "okay";
+	pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input", "spi", "pwm", "pruout", "pruin";
+	pinctrl-0 = <&P1_33_default_pin>;
+	pinctrl-1 = <&P1_33_gpio_pin>;
+	pinctrl-2 = <&P1_33_gpio_pu_pin>;
+	pinctrl-3 = <&P1_33_gpio_pd_pin>;
+	pinctrl-4 = <&P1_33_gpio_input_pin>;
+	pinctrl-5 = <&P1_33_spi_pin>;
+	pinctrl-6 = <&P1_33_pwm_pin>;
+	pinctrl-7 = <&P1_33_pruout_pin>;
+	pinctrl-8 = <&P1_33_pruin_pin>;
+};
+
+/* P1_34 (ZCZ ball T11) */
+P1_34_pinmux {
+	compatible = "bone-pinmux-helper";
+	status = "okay";
+	pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input", "pwm";
+	pinctrl-0 = <&P1_34_default_pin>;
+	pinctrl-1 = <&P1_34_gpio_pin>;
+	pinctrl-2 = <&P1_34_gpio_pu_pin>;
+	pinctrl-3 = <&P1_34_gpio_pd_pin>;
+	pinctrl-4 = <&P1_34_gpio_input_pin>;
+	pinctrl-5 = <&P1_34_pwm_pin>;
+};
+
+/* P1_35 (ZCZ ball V5) pruin */
+P1_35_pinmux {
+	compatible = "bone-pinmux-helper";
+	status = "okay";
+	pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input", "pruout", "pruin";
+	pinctrl-0 = <&P1_35_default_pin>;
+	pinctrl-1 = <&P1_35_gpio_pin>;
+	pinctrl-2 = <&P1_35_gpio_pu_pin>;
+	pinctrl-3 = <&P1_35_gpio_pd_pin>;
+	pinctrl-4 = <&P1_35_gpio_input_pin>;
+	pinctrl-5 = <&P1_35_pruout_pin>;
+	pinctrl-6 = <&P1_35_pruin_pin>;
+};
+
+/* P1_36 (ZCZ ball A13) pwm */
+P1_36_pinmux {
+	compatible = "bone-pinmux-helper";
+	status = "okay";
+	pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input", "spi_sclk", "pwm", "pruout", "pruin";
+	pinctrl-0 = <&P1_36_default_pin>;
+	pinctrl-1 = <&P1_36_gpio_pin>;
+	pinctrl-2 = <&P1_36_gpio_pu_pin>;
+	pinctrl-3 = <&P1_36_gpio_pd_pin>;
+	pinctrl-4 = <&P1_36_gpio_input_pin>;
+	pinctrl-5 = <&P1_36_spi_sclk_pin>;
+	pinctrl-6 = <&P1_36_pwm_pin>;
+	pinctrl-7 = <&P1_36_pruout_pin>;
+	pinctrl-8 = <&P1_36_pruin_pin>;
+};
+
+
+/************************/
+/* P2 Header */
+/************************/
+
+/* P2_01 (ZCZ ball U14) pwm */
+P2_01_pinmux {
+	compatible = "bone-pinmux-helper";
+	status = "okay";
+	pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input", "pwm";
+	pinctrl-0 = <&P2_01_default_pin>;
+	pinctrl-1 = <&P2_01_gpio_pin>;
+	pinctrl-2 = <&P2_01_gpio_pu_pin>;
+	pinctrl-3 = <&P2_01_gpio_pd_pin>;
+	pinctrl-4 = <&P2_01_gpio_input_pin>;
+	pinctrl-5 = <&P2_01_pwm_pin>;
+};
+
+/* P2_02 (ZCZ ball V17) */
+P2_02_pinmux {
+	compatible = "bone-pinmux-helper";
+	status = "okay";
+	pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input";
+	pinctrl-0 = <&P2_02_default_pin>;
+	pinctrl-1 = <&P2_02_gpio_pin>;
+	pinctrl-2 = <&P2_02_gpio_pu_pin>;
+	pinctrl-3 = <&P2_02_gpio_pd_pin>;
+	pinctrl-4 = <&P2_02_gpio_input_pin>;
+};
+
+/* P2_03 (ZCZ ball T10) */
+P2_03_pinmux {
+	compatible = "bone-pinmux-helper";
+	status = "okay";
+	pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input", "pwm";
+	pinctrl-0 = <&P2_03_default_pin>;
+	pinctrl-1 = <&P2_03_gpio_pin>;
+	pinctrl-2 = <&P2_03_gpio_pu_pin>;
+	pinctrl-3 = <&P2_03_gpio_pd_pin>;
+	pinctrl-4 = <&P2_03_gpio_input_pin>;
+	pinctrl-5 = <&P2_03_pwm_pin>;
+};
+
+/* P2_04 (ZCZ ball T16) */
+P2_04_pinmux {
+	compatible = "bone-pinmux-helper";
+	status = "okay";
+	pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input";
+	pinctrl-0 = <&P2_04_default_pin>;
+	pinctrl-1 = <&P2_04_gpio_pin>;
+	pinctrl-2 = <&P2_04_gpio_pu_pin>;
+	pinctrl-3 = <&P2_04_gpio_pd_pin>;
+	pinctrl-4 = <&P2_04_gpio_input_pin>;
+};
+
+/* P2_05 (ZCZ ball T17) uart */
+P2_05_pinmux {
+	compatible = "bone-pinmux-helper";
+	status = "okay";
+	pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input", "uart";
+	pinctrl-0 = <&P2_05_default_pin>;
+	pinctrl-1 = <&P2_05_gpio_pin>;
+	pinctrl-2 = <&P2_05_gpio_pu_pin>;
+	pinctrl-3 = <&P2_05_gpio_pd_pin>;
+	pinctrl-4 = <&P2_05_gpio_input_pin>;
+	pinctrl-5 = <&P2_05_uart_pin>;
+};
+
+/* P2_06 (ZCZ ball U16) */
+P2_06_pinmux {
+	compatible = "bone-pinmux-helper";
+	status = "okay";
+	pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input";
+	pinctrl-0 = <&P2_06_default_pin>;
+	pinctrl-1 = <&P2_06_gpio_pin>;
+	pinctrl-2 = <&P2_06_gpio_pu_pin>;
+	pinctrl-3 = <&P2_06_gpio_pd_pin>;
+	pinctrl-4 = <&P2_06_gpio_input_pin>;
+};
+
+/* P2_07 (ZCZ ball U17) uart */
+P2_07_pinmux {
+	compatible = "bone-pinmux-helper";
+	status = "okay";
+	pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input", "uart";
+	pinctrl-0 = <&P2_07_default_pin>;
+	pinctrl-1 = <&P2_07_gpio_pin>;
+	pinctrl-2 = <&P2_07_gpio_pu_pin>;
+	pinctrl-3 = <&P2_07_gpio_pd_pin>;
+	pinctrl-4 = <&P2_07_gpio_input_pin>;
+	pinctrl-5 = <&P2_07_uart_pin>;
+};
+
+/* P2_08 (ZCZ ball U18) */
+P2_08_pinmux {
+	compatible = "bone-pinmux-helper";
+	status = "okay";
+	pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input";
+	pinctrl-0 = <&P2_08_default_pin>;
+	pinctrl-1 = <&P2_08_gpio_pin>;
+	pinctrl-2 = <&P2_08_gpio_pu_pin>;
+	pinctrl-3 = <&P2_08_gpio_pd_pin>;
+	pinctrl-4 = <&P2_08_gpio_input_pin>;
+};
+
+/* P2_09 (ZCZ ball D15) i2c */
+P2_09_pinmux {
+	compatible = "bone-pinmux-helper";
+	status = "okay";
+	pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input", "uart", "can", "i2c", "pru_uart", "pruin";
+	pinctrl-0 = <&P2_09_default_pin>;
+	pinctrl-1 = <&P2_09_gpio_pin>;
+	pinctrl-2 = <&P2_09_gpio_pu_pin>;
+	pinctrl-3 = <&P2_09_gpio_pd_pin>;
+	pinctrl-4 = <&P2_09_gpio_input_pin>;
+	pinctrl-5 = <&P2_09_uart_pin>;
+	pinctrl-6 = <&P2_09_can_pin>;
+	pinctrl-7 = <&P2_09_i2c_pin>;
+	pinctrl-8 = <&P2_09_pru_uart_pin>;
+	pinctrl-9 = <&P2_09_pruin_pin>;
+};
+
+/* P2_10 (ZCZ ball R14) */
+P2_10_pinmux {
+	compatible = "bone-pinmux-helper";
+	status = "okay";
+	pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input", "qep";
+	pinctrl-0 = <&P2_10_default_pin>;
+	pinctrl-1 = <&P2_10_gpio_pin>;
+	pinctrl-2 = <&P2_10_gpio_pu_pin>;
+	pinctrl-3 = <&P2_10_gpio_pd_pin>;
+	pinctrl-4 = <&P2_10_gpio_input_pin>;
+	pinctrl-5 = <&P2_10_qep_pin>;
+};
+
+/* P2_11 (ZCZ ball D16) i2c */
+P2_11_pinmux {
+	compatible = "bone-pinmux-helper";
+	status = "okay";
+	pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input", "uart", "can", "i2c", "pru_uart", "pruin";
+	pinctrl-0 = <&P2_11_default_pin>;
+	pinctrl-1 = <&P2_11_gpio_pin>;
+	pinctrl-2 = <&P2_11_gpio_pu_pin>;
+	pinctrl-3 = <&P2_11_gpio_pd_pin>;
+	pinctrl-4 = <&P2_11_gpio_input_pin>;
+	pinctrl-5 = <&P2_11_uart_pin>;
+	pinctrl-6 = <&P2_11_can_pin>;
+	pinctrl-7 = <&P2_11_i2c_pin>;
+	pinctrl-8 = <&P2_11_pru_uart_pin>;
+	pinctrl-9 = <&P2_11_pruin_pin>;
+};
+
+/* P2_12                POWER_BUTTON */
+
+/* P2_13                VOUT-5V */
+
+/* P2_14                BAT-VIN */
+
+/* P2_15                GND */
+
+/* P2_16                BAT-TEMP */
+
+/* P2_17 (ZCZ ball V12) */
+P2_17_pinmux {
+	compatible = "bone-pinmux-helper";
+	status = "okay";
+	pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input";
+	pinctrl-0 = <&P2_17_default_pin>;
+	pinctrl-1 = <&P2_17_gpio_pin>;
+	pinctrl-2 = <&P2_17_gpio_pu_pin>;
+	pinctrl-3 = <&P2_17_gpio_pd_pin>;
+	pinctrl-4 = <&P2_17_gpio_input_pin>;
+};
+
+/* P2_18 (ZCZ ball U13) */
+P2_18_pinmux {
+	compatible = "bone-pinmux-helper";
+	status = "okay";
+	pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input", "qep", "pru_ecap", "pruin";
+	pinctrl-0 = <&P2_18_default_pin>;
+	pinctrl-1 = <&P2_18_gpio_pin>;
+	pinctrl-2 = <&P2_18_gpio_pu_pin>;
+	pinctrl-3 = <&P2_18_gpio_pd_pin>;
+	pinctrl-4 = <&P2_18_gpio_input_pin>;
+	pinctrl-5 = <&P2_18_qep_pin>;
+	pinctrl-6 = <&P2_18_pru_ecap_pin>;
+	pinctrl-7 = <&P2_18_pruin_pin>;
+};
+
+/* P2_19 (ZCZ ball U12) */
+P2_19_pinmux {
+	compatible = "bone-pinmux-helper";
+	status = "okay";
+	pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input", "pwm";
+	pinctrl-0 = <&P2_19_default_pin>;
+	pinctrl-1 = <&P2_19_gpio_pin>;
+	pinctrl-2 = <&P2_19_gpio_pu_pin>;
+	pinctrl-3 = <&P2_19_gpio_pd_pin>;
+	pinctrl-4 = <&P2_19_gpio_input_pin>;
+	pinctrl-5 = <&P2_19_pwm_pin>;
+};
+
+/* P2_20 (ZCZ ball T13) */
+P2_20_pinmux {
+	compatible = "bone-pinmux-helper";
+	status = "okay";
+	pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input";
+	pinctrl-0 = <&P2_20_default_pin>;
+	pinctrl-1 = <&P2_20_gpio_pin>;
+	pinctrl-2 = <&P2_20_gpio_pu_pin>;
+	pinctrl-3 = <&P2_20_gpio_pd_pin>;
+	pinctrl-4 = <&P2_20_gpio_input_pin>;
+};
+
+/* P2_21                GND */
+
+/* P2_22 (ZCZ ball V13) */
+P2_22_pinmux {
+	compatible = "bone-pinmux-helper";
+	status = "okay";
+	pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input", "qep", "pruin";
+	pinctrl-0 = <&P2_22_default_pin>;
+	pinctrl-1 = <&P2_22_gpio_pin>;
+	pinctrl-2 = <&P2_22_gpio_pu_pin>;
+	pinctrl-3 = <&P2_22_gpio_pd_pin>;
+	pinctrl-4 = <&P2_22_gpio_input_pin>;
+	pinctrl-5 = <&P2_22_qep_pin>;
+	pinctrl-6 = <&P2_22_pruin_pin>;
+};
+
+/* P2_23                VOUT-3.3V */
+
+/* P2_24 (ZCZ ball T12) */
+P2_24_pinmux {
+	compatible = "bone-pinmux-helper";
+	status = "okay";
+	pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input", "qep", "pruout";
+	pinctrl-0 = <&P2_24_default_pin>;
+	pinctrl-1 = <&P2_24_gpio_pin>;
+	pinctrl-2 = <&P2_24_gpio_pu_pin>;
+	pinctrl-3 = <&P2_24_gpio_pd_pin>;
+	pinctrl-4 = <&P2_24_gpio_input_pin>;
+	pinctrl-5 = <&P2_24_qep_pin>;
+	pinctrl-6 = <&P2_24_pruout_pin>;
+};
+
+/* P2_25 (ZCZ ball E17) spi */
+P2_25_pinmux {
+	compatible = "bone-pinmux-helper";
+	status = "okay";
+	pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input", "spi", "spi_cs", "uart", "can", "i2c";
+	pinctrl-0 = <&P2_25_default_pin>;
+	pinctrl-1 = <&P2_25_gpio_pin>;
+	pinctrl-2 = <&P2_25_gpio_pu_pin>;
+	pinctrl-3 = <&P2_25_gpio_pd_pin>;
+	pinctrl-4 = <&P2_25_gpio_input_pin>;
+	pinctrl-5 = <&P2_25_spi_pin>;
+	pinctrl-6 = <&P2_25_spi_cs_pin>;
+	pinctrl-7 = <&P2_25_uart_pin>;
+	pinctrl-8 = <&P2_25_can_pin>;
+	pinctrl-9 = <&P2_25_i2c_pin>;
+};
+
+/* P2_26                RESET# */
+
+/* P2_27 (ZCZ ball E18) spi */
+P2_27_pinmux {
+	compatible = "bone-pinmux-helper";
+	status = "okay";
+	pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input", "spi", "uart", "can", "i2c";
+	pinctrl-0 = <&P2_27_default_pin>;
+	pinctrl-1 = <&P2_27_gpio_pin>;
+	pinctrl-2 = <&P2_27_gpio_pu_pin>;
+	pinctrl-3 = <&P2_27_gpio_pd_pin>;
+	pinctrl-4 = <&P2_27_gpio_input_pin>;
+	pinctrl-5 = <&P2_27_spi_pin>;
+	pinctrl-6 = <&P2_27_uart_pin>;
+	pinctrl-7 = <&P2_27_can_pin>;
+	pinctrl-8 = <&P2_27_i2c_pin>;
+};
+
+/* P2_28 (ZCZ ball D13) pruin */
+P2_28_pinmux {
+	compatible = "bone-pinmux-helper";
+	status = "okay";
+	pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input", "qep", "pruout", "pruin";
+	pinctrl-0 = <&P2_28_default_pin>;
+	pinctrl-1 = <&P2_28_gpio_pin>;
+	pinctrl-2 = <&P2_28_gpio_pu_pin>;
+	pinctrl-3 = <&P2_28_gpio_pd_pin>;
+	pinctrl-4 = <&P2_28_gpio_input_pin>;
+	pinctrl-5 = <&P2_28_qep_pin>;
+	pinctrl-6 = <&P2_28_pruout_pin>;
+	pinctrl-7 = <&P2_28_pruin_pin>;
+};
+
+/* P2_29 (ZCZ ball C18) spi_sclk */
+P2_29_pinmux {
+	compatible = "bone-pinmux-helper";
+	status = "okay";
+	pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input", "spi_cs", "spi_sclk", "uart", "pwm", "pru_ecap";
+	pinctrl-0 = <&P2_29_default_pin>;
+	pinctrl-1 = <&P2_29_gpio_pin>;
+	pinctrl-2 = <&P2_29_gpio_pu_pin>;
+	pinctrl-3 = <&P2_29_gpio_pd_pin>;
+	pinctrl-4 = <&P2_29_gpio_input_pin>;
+	pinctrl-5 = <&P2_29_spi_cs_pin>;
+	pinctrl-6 = <&P2_29_spi_sclk_pin>;
+	pinctrl-7 = <&P2_29_uart_pin>;
+	pinctrl-8 = <&P2_29_pwm_pin>;
+	pinctrl-9 = <&P2_29_pru_ecap_pin>;
+};
+
+/* P2_30 (ZCZ ball C12) pruin */
+P2_30_pinmux {
+	compatible = "bone-pinmux-helper";
+	status = "okay";
+	pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input", "spi_cs", "pwm", "pruout", "pruin";
+	pinctrl-0 = <&P2_30_default_pin>;
+	pinctrl-1 = <&P2_30_gpio_pin>;
+	pinctrl-2 = <&P2_30_gpio_pu_pin>;
+	pinctrl-3 = <&P2_30_gpio_pd_pin>;
+	pinctrl-4 = <&P2_30_gpio_input_pin>;
+	pinctrl-5 = <&P2_30_spi_cs_pin>;
+	pinctrl-6 = <&P2_30_pwm_pin>;
+	pinctrl-7 = <&P2_30_pruout_pin>;
+	pinctrl-8 = <&P2_30_pruin_pin>;
+};
+
+/* P2_31 (ZCZ ball A15) spi_cs */
+P2_31_pinmux {
+	compatible = "bone-pinmux-helper";
+	status = "okay";
+	pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input", "spi_cs", "pruin";
+	pinctrl-0 = <&P2_31_default_pin>;
+	pinctrl-1 = <&P2_31_gpio_pin>;
+	pinctrl-2 = <&P2_31_gpio_pu_pin>;
+	pinctrl-3 = <&P2_31_gpio_pd_pin>;
+	pinctrl-4 = <&P2_31_gpio_input_pin>;
+	pinctrl-5 = <&P2_31_spi_cs_pin>;
+	pinctrl-6 = <&P2_31_pruin_pin>;
+};
+
+/* P2_32 (ZCZ ball D12) pruin */
+P2_32_pinmux {
+	compatible = "bone-pinmux-helper";
+	status = "okay";
+	pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input", "spi", "pwm", "pruout", "pruin";
+	pinctrl-0 = <&P2_32_default_pin>;
+	pinctrl-1 = <&P2_32_gpio_pin>;
+	pinctrl-2 = <&P2_32_gpio_pu_pin>;
+	pinctrl-3 = <&P2_32_gpio_pd_pin>;
+	pinctrl-4 = <&P2_32_gpio_input_pin>;
+	pinctrl-5 = <&P2_32_spi_pin>;
+	pinctrl-6 = <&P2_32_pwm_pin>;
+	pinctrl-7 = <&P2_32_pruout_pin>;
+	pinctrl-8 = <&P2_32_pruin_pin>;
+};
+
+/* P2_33 (ZCZ ball R12) */
+P2_33_pinmux {
+	compatible = "bone-pinmux-helper";
+	status = "okay";
+	pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input", "qep", "pruout";
+	pinctrl-0 = <&P2_33_default_pin>;
+	pinctrl-1 = <&P2_33_gpio_pin>;
+	pinctrl-2 = <&P2_33_gpio_pu_pin>;
+	pinctrl-3 = <&P2_33_gpio_pd_pin>;
+	pinctrl-4 = <&P2_33_gpio_input_pin>;
+	pinctrl-5 = <&P2_33_qep_pin>;
+	pinctrl-6 = <&P2_33_pruout_pin>;
+};
+
+/* P2_34 (ZCZ ball C13) pruin */
+P2_34_pinmux {
+	compatible = "bone-pinmux-helper";
+	status = "okay";
+	pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input", "qep", "pruout", "pruin";
+	pinctrl-0 = <&P2_34_default_pin>;
+	pinctrl-1 = <&P2_34_gpio_pin>;
+	pinctrl-2 = <&P2_34_gpio_pu_pin>;
+	pinctrl-3 = <&P2_34_gpio_pd_pin>;
+	pinctrl-4 = <&P2_34_gpio_input_pin>;
+	pinctrl-5 = <&P2_34_qep_pin>;
+	pinctrl-6 = <&P2_34_pruout_pin>;
+	pinctrl-7 = <&P2_34_pruin_pin>;
+};
+
+/* P2_35 (ZCZ ball U5) gpio_input */
+P2_35_pinmux {
+	compatible = "bone-pinmux-helper";
+	status = "okay";
+	pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "gpio_input", "pruout", "pruin";
+	pinctrl-0 = <&P2_35_default_pin>;
+	pinctrl-1 = <&P2_35_gpio_pin>;
+	pinctrl-2 = <&P2_35_gpio_pu_pin>;
+	pinctrl-3 = <&P2_35_gpio_pd_pin>;
+	pinctrl-4 = <&P2_35_gpio_input_pin>;
+	pinctrl-5 = <&P2_35_pruout_pin>;
+	pinctrl-6 = <&P2_35_pruin_pin>;
+};
+
+/* P2_36 (ZCZ ball C9)  AIN7         */
+
+cape-universal {
+	compatible = "gpio-of-helper";
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <>;
+
+	P1_02 {
+		gpio-name = "P1_02";
+		gpio = <&gpio2 23 0>;
+		input;
+		dir-changeable;
+	};
+
+	P1_04 {
+		gpio-name = "P1_04";
+		gpio = <&gpio2 25 0>;
+		input;
+		dir-changeable;
+	};
+
+	P1_06 {
+		gpio-name = "P1_06";
+		gpio = <&gpio0 5 0>;
+		input;
+		dir-changeable;
+	};
+
+	P1_08 {
+		gpio-name = "P1_08";
+		gpio = <&gpio0 2 0>;
+		input;
+		dir-changeable;
+	};
+
+	P1_10 {
+		gpio-name = "P1_10";
+		gpio = <&gpio0 3 0>;
+		input;
+		dir-changeable;
+	};
+
+	P1_12 {
+		gpio-name = "P1_12";
+		gpio = <&gpio0 4 0>;
+		input;
+		dir-changeable;
+	};
+
+	P1_20 {
+		gpio-name = "P1_20";
+		gpio = <&gpio0 20 0>;
+		input;
+		dir-changeable;
+	};
+
+	P1_26 {
+		gpio-name = "P1_26";
+		gpio = <&gpio0 12 0>;
+		input;
+		dir-changeable;
+	};
+
+	P1_28 {
+		gpio-name = "P1_28";
+		gpio = <&gpio0 13 0>;
+		input;
+		dir-changeable;
+	};
+
+	P1_29 {
+		gpio-name = "P1_29";
+		gpio = <&gpio3 21 0>;
+		input;
+		dir-changeable;
+	};
+
+	P1_30 {
+		gpio-name = "P1_30";
+		gpio = <&gpio1 11 0>;
+		input;
+		dir-changeable;
+	};
+
+	P1_31 {
+		gpio-name = "P1_31";
+		gpio = <&gpio3 18 0>;
+		input;
+		dir-changeable;
+	};
+
+	P1_32 {
+		gpio-name = "P1_32";
+		gpio = <&gpio1 10 0>;
+		input;
+		dir-changeable;
+	};
+
+	P1_33 {
+		gpio-name = "P1_33";
+		gpio = <&gpio3 15 0>;
+		input;
+		dir-changeable;
+	};
+
+	P1_34 {
+		gpio-name = "P1_34";
+		gpio = <&gpio0 26 0>;
+		input;
+		dir-changeable;
+	};
+
+	P1_35 {
+		gpio-name = "P1_35";
+		gpio = <&gpio2 24 0>;
+		input;
+		dir-changeable;
+	};
+
+	P1_36 {
+		gpio-name = "P1_36";
+		gpio = <&gpio3 14 0>;
+		input;
+		dir-changeable;
+	};
+
+	P2_01 {
+		gpio-name = "P2_01";
+		gpio = <&gpio1 18 0>;
+		input;
+		dir-changeable;
+	};
+
+	P2_02 {
+		gpio-name = "P2_02";
+		gpio = <&gpio1 27 0>;
+		input;
+		dir-changeable;
+	};
+
+	P2_03 {
+		gpio-name = "P2_03";
+		gpio = <&gpio0 23 0>;
+		input;
+		dir-changeable;
+	};
+
+	P2_04 {
+		gpio-name = "P2_04";
+		gpio = <&gpio1 26 0>;
+		input;
+		dir-changeable;
+	};
+
+	P2_05 {
+		gpio-name = "P2_05";
+		gpio = <&gpio0 30 0>;
+		input;
+		dir-changeable;
+	};
+
+	P2_06 {
+		gpio-name = "P2_06";
+		gpio = <&gpio1 25 0>;
+		input;
+		dir-changeable;
+	};
+
+	P2_07 {
+		gpio-name = "P2_07";
+		gpio = <&gpio0 31 0>;
+		input;
+		dir-changeable;
+	};
+
+	P2_08 {
+		gpio-name = "P2_08";
+		gpio = <&gpio1 28 0>;
+		input;
+		dir-changeable;
+	};
+
+	P2_09 {
+		gpio-name = "P2_09";
+		gpio = <&gpio0 15 0>;
+		input;
+		dir-changeable;
+	};
+
+	P2_10 {
+		gpio-name = "P2_10";
+		gpio = <&gpio1 20 0>;
+		input;
+		dir-changeable;
+	};
+
+	P2_11 {
+		gpio-name = "P2_11";
+		gpio = <&gpio0 14 0>;
+		input;
+		dir-changeable;
+	};
+
+	P2_17 {
+		gpio-name = "P2_17";
+		gpio = <&gpio2 1 0>;
+		input;
+		dir-changeable;
+	};
+
+	P2_18 {
+		gpio-name = "P2_18";
+		gpio = <&gpio1 15 0>;
+		input;
+		dir-changeable;
+	};
+
+	P2_19 {
+		gpio-name = "P2_19";
+		gpio = <&gpio0 27 0>;
+		input;
+		dir-changeable;
+	};
+
+	P2_20 {
+		gpio-name = "P2_20";
+		gpio = <&gpio2 0 0>;
+		input;
+		dir-changeable;
+	};
+
+	P2_22 {
+		gpio-name = "P2_22";
+		gpio = <&gpio1 14 0>;
+		input;
+		dir-changeable;
+	};
+
+	P2_24 {
+		gpio-name = "P2_24";
+		gpio = <&gpio1 12 0>;
+		input;
+		dir-changeable;
+	};
+
+	P2_25 {
+		gpio-name = "P2_25";
+		gpio = <&gpio1 9 0>;
+		input;
+		dir-changeable;
+	};
+
+	P2_27 {
+		gpio-name = "P2_27";
+		gpio = <&gpio1 8 0>;
+		input;
+		dir-changeable;
+	};
+
+	P2_28 {
+		gpio-name = "P2_28";
+		gpio = <&gpio3 20 0>;
+		input;
+		dir-changeable;
+	};
+
+	P2_29 {
+		gpio-name = "P2_29";
+		gpio = <&gpio0 7 0>;
+		input;
+		dir-changeable;
+	};
+
+	P2_30 {
+		gpio-name = "P2_30";
+		gpio = <&gpio3 17 0>;
+		input;
+		dir-changeable;
+	};
+
+	P2_31 {
+		gpio-name = "P2_31";
+		gpio = <&gpio0 19 0>;
+		input;
+		dir-changeable;
+	};
+
+	P2_32 {
+		gpio-name = "P2_32";
+		gpio = <&gpio3 16 0>;
+		input;
+		dir-changeable;
+	};
+
+	P2_33 {
+		gpio-name = "P2_33";
+		gpio = <&gpio1 13 0>;
+		input;
+		dir-changeable;
+	};
+
+	P2_34 {
+		gpio-name = "P2_34";
+		gpio = <&gpio3 19 0>;
+		input;
+		dir-changeable;
+	};
+
+	P2_35 {
+		gpio-name = "P2_35";
+		gpio = <&gpio2 22 0>;
+		input;
+		dir-changeable;
+	};
+
+};
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/tools/pinmux-generator/PocketBeagle.sh b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/tools/pinmux-generator/PocketBeagle.sh
new file mode 100644
index 0000000000000000000000000000000000000000..6b41613a657f4cc92d96df0fc03af23c4d96baf0
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/tools/pinmux-generator/PocketBeagle.sh
@@ -0,0 +1,209 @@
+#!/bin/bash
+
+source $(dirname "$0")/lib/pinmux.sh
+
+file="PocketBeagle"
+
+echo "" > ${file}.dts
+echo "" >${file}-pinmux.dts
+echo "" >${file}-gpio.dts
+echo "" >${file}_config-pin.txt
+
+disable_timer="enable"
+
+#PocketBeagle
+gpio_index="7"
+
+msg="/************************/" ; echo_both
+msg="/* P1 Header */" ; echo_both
+msg="/************************/" ; echo_both
+msg="" ; echo_both
+
+pcbpin="P1_01" ; label_pin="power" ; label_info="VIN-AC" ; echo_label
+
+pcbpin="P1_02" ; ball="R5" ; default_mode="7" ; cp_default="gpio_input" ; find_ball
+
+pcbpin="P1_03" ; ball="F15" label_pin="system" ; label_info="usb1_vbus_out" ; echo_label_analog
+
+pcbpin="P1_04" ; ball="R6" ; default_mode="7" ; find_ball
+
+pcbpin="P1_05" ; ball="T18" label_pin="system" ; label_info="usb1_vbus_in" ; echo_label_analog
+
+pcbpin="P1_06" ; ball="A16" ; default_mode="0" ; cp_default="spi_cs" ; find_ball
+
+pcbpin="P1_07" ; label_pin="system" ; label_info="VIN-USB" ; echo_label
+
+pcbpin="P1_08" ; ball="A17" ; default_mode="0" ; cp_default="spi_sclk" ; find_ball
+
+pcbpin="P1_09" ; ball="R18" label_pin="system" ; label_info="USB1-DN" ; echo_label_analog
+
+pcbpin="P1_10" ; ball="B17" ; default_mode="0" ; cp_default="spi" ; find_ball
+
+pcbpin="P1_11" ; ball="R17" label_pin="system" ; label_info="USB1-DP" ; echo_label_analog
+
+pcbpin="P1_12" ; ball="B16" ; default_mode="0" ; cp_default="spi" ; find_ball
+
+pcbpin="P1_13" ; ball="P17" label_pin="system" ; label_info="USB1-ID" ; echo_label_analog
+
+pcbpin="P1_14" ; label_pin="power" ; label_info="VOUT-3.3V" ; echo_label
+
+pcbpin="P1_15" ; label_pin="gnd" ; label_info="GND" ; echo_label
+
+pcbpin="P1_16" ; label_pin="gnd" ; label_info="GND" ; echo_label
+
+pcbpin="P1_17" ; ball="A9" label_pin="power" ; label_info="VREFN" ; echo_label_analog
+
+pcbpin="P1_18" ; ball="B9" label_pin="power" ; label_info="VREFP" ; echo_label_analog
+
+pcbpin="P1_19" ; ball="B6" label_pin="adc" ; label_info="AIN0" ; echo_label_analog
+
+gpio_index="6"
+pcbpin="P1_20" ; ball="D14" ; default_mode="7" ; find_ball
+gpio_index="7"
+
+pcbpin="P1_21" ; ball="C7" label_pin="adc" ; label_info="AIN1" ; echo_label_analog
+
+pcbpin="P1_22" ; label_pin="gnd" ; label_info="GND" ; echo_label
+
+pcbpin="P1_23" ; ball="B7" label_pin="adc" ; label_info="AIN2" ; echo_label_analog
+
+pcbpin="P1_24" ; label_pin="power" ; label_info="VOUT-5V" ; echo_label
+
+pcbpin="P1_25" ; ball="A7" label_pin="adc" ; label_info="AIN3" ; echo_label_analog
+
+pcbpin="P1_26" ; ball="D18" ; default_mode="3" ; cp_default="i2c" ; find_ball
+
+pcbpin="P1_27" ; ball="C8" label_pin="adc" ; label_info="AIN4" ; echo_label_analog
+
+pcbpin="P1_28" ; ball="D17" ; default_mode="3" ; cp_default="i2c" ; find_ball
+
+pcbpin="P1_29" ; ball="A14" ; default_mode="6" ; cp_default="pruin" ; find_ball
+
+pcbpin="P1_30" ; ball="E16" ; default_mode="0" ; cp_default="uart" ; find_ball
+
+pcbpin="P1_31" ; ball="B12" ; default_mode="6" ; cp_default="pruin" ; find_ball
+
+pcbpin="P1_32" ; ball="E15" ; default_mode="0" ; cp_default="uart" ; find_ball
+
+gpio_index="6"
+pcbpin="P1_33" ; ball="B13" ; default_mode="6" ; cp_default="pruin" ; find_ball
+gpio_index="7"
+
+gpio_index="6"
+pcbpin="P1_34" ; ball="T11" ; default_mode="7" ; find_ball
+gpio_index="7"
+
+pcbpin="P1_35" ; ball="V5" ; default_mode="6" ; cp_default="pruin" ; find_ball
+
+gpio_index="6"
+pcbpin="P1_36" ; ball="A13" ; default_mode="1" ; cp_default="pwm" ; find_ball
+gpio_index="7"
+
+msg="" ; echo_both
+
+msg="/************************/" ; echo_both
+msg="/* P2 Header */" ; echo_both
+msg="/************************/" ; echo_both
+msg="" ; echo_both
+
+pcbpin="P2_01" ; ball="U14" ; default_mode="6" ; cp_default="pwm" ; find_ball
+
+default_mode="7" ; pcbpin="P2_02" ; ball="V17" ; find_ball
+
+gpio_index="6"
+pcbpin="P2_03" ; ball="T10" ; default_mode="7" ; find_ball
+gpio_index="7"
+
+pcbpin="P2_04" ; ball="T16" ; default_mode="7" ; find_ball
+
+pcbpin="P2_05" ; ball="T17" ; default_mode="6" ; cp_default="uart" ; find_ball
+
+gpio_index="6"
+pcbpin="P2_06" ; ball="U16" ; default_mode="7" ; find_ball
+gpio_index="7"
+
+pcbpin="P2_07" ; ball="U17" ; default_mode="6" ; cp_default="uart" ; find_ball
+
+default_mode="7" ; pcbpin="P2_08" ; ball="U18" ; find_ball
+
+gpio_index="6"
+pcbpin="P2_09" ; ball="D15" ; default_mode="3" ; cp_default="i2c" ; find_ball
+gpio_index="7"
+
+default_mode="7" ; pcbpin="P2_10" ; ball="R14" ; find_ball
+
+gpio_index="6"
+pcbpin="P2_11" ; ball="D16" ; default_mode="3" ; cp_default="i2c" ; find_ball
+gpio_index="7"
+
+pcbpin="P2_12" ; label_pin="system" ; label_info="POWER_BUTTON" ; echo_label
+
+pcbpin="P2_13" ; label_pin="power" ; label_info="VOUT-5V" ; echo_label
+
+pcbpin="P2_14" ; label_pin="power" ; label_info="BAT-VIN" ; echo_label
+
+pcbpin="P2_15" ; label_pin="gnd" ; label_info="GND" ; echo_label
+
+pcbpin="P2_16" ; label_pin="power" ; label_info="BAT-TEMP" ; echo_label
+
+pcbpin="P2_17" ; ball="V12" ; default_mode="7" ; find_ball
+pcbpin="P2_18" ; ball="U13" ; default_mode="7" ; find_ball
+
+gpio_index="6"
+pcbpin="P2_19" ; ball="U12" ; default_mode="7" ; find_ball
+gpio_index="7"
+
+gpio_index="6"
+pcbpin="P2_20" ; ball="T13" ; default_mode="7" ; find_ball
+gpio_index="7"
+
+pcbpin="P2_21" ; label_pin="gnd" ; label_info="GND" ; echo_label
+
+pcbpin="P2_22" ; ball="V13" ; default_mode="7" ; find_ball
+
+pcbpin="P2_23" ; label_pin="power" ; label_info="VOUT-3.3V" ; echo_label
+
+pcbpin="P2_24" ; ball="T12" ; default_mode="7" ; find_ball
+
+pcbpin="P2_25" ; ball="E17" ; default_mode="4" ; cp_default="spi" ; find_ball
+
+pcbpin="P2_26" ; label_pin="system" ; label_info="RESET#" ; echo_label
+
+pcbpin="P2_27" ; ball="E18" ; default_mode="4" ; cp_default="spi" ; find_ball
+
+gpio_index="6"
+pcbpin="P2_28" ; ball="D13" ; default_mode="6" ; cp_default="pruin" ; find_ball
+gpio_index="7"
+
+pcbpin="P2_29" ; ball="C18" ; default_mode="4" ; cp_default="spi_sclk" ; find_ball
+
+pcbpin="P2_30" ; ball="C12" ; default_mode="6" ; cp_default="pruin" ; find_ball
+
+gpio_index="6"
+pcbpin="P2_31" ; ball="A15" ; default_mode="4" ; cp_default="spi_cs" ; find_ball
+gpio_index="7"
+
+gpio_index="6"
+pcbpin="P2_32" ; ball="D12" ; default_mode="6" ; cp_default="pruin" ; find_ball
+gpio_index="7"
+
+pcbpin="P2_33" ; ball="R12" ; default_mode="7" ; find_ball
+pcbpin="P2_34" ; ball="C13" ; default_mode="6" ; cp_default="pruin" ; find_ball
+pcbpin="P2_35" ; ball="U5" ; default_mode="7" ; cp_default="gpio_input" ; find_ball
+
+pcbpin="P2_36" ; ball="C9" label_pin="adc" ; label_info="AIN7" ; echo_label_analog
+
+cat ${file}-pinmux.dts >> ${file}.dts
+
+echo "cape-universal {" >> ${file}.dts
+echo "	compatible = \"gpio-of-helper\";" >> ${file}.dts
+echo "	status = \"okay\";" >> ${file}.dts
+echo "	pinctrl-names = \"default\";" >> ${file}.dts
+echo "	pinctrl-0 = <>;" >> ${file}.dts
+
+cat ${file}-gpio.dts >> ${file}.dts
+
+echo "};" >> ${file}.dts
+
+rm -rf ${file}-pinmux.dts || true
+rm -rf ${file}-gpio.dts || true
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/tools/pinmux-generator/PocketBeagle_config-pin.txt b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/tools/pinmux-generator/PocketBeagle_config-pin.txt
new file mode 100644
index 0000000000000000000000000000000000000000..2579bc2560b5463833c6ad837bed5756d1912e2e
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/tools/pinmux-generator/PocketBeagle_config-pin.txt
@@ -0,0 +1,421 @@
+
+P1_01_PIN="power"
+P1_01_INFO="VIN-AC"
+P1_01_CAPE=""
+
+P1_02_PRU="119"
+P1_02_GPIO="87"
+P1_02_PIN="gpio_input"
+P1_02_PINMUX="default gpio gpio_pu gpio_pd gpio_input pruout pruin"
+P1_02_INFO="gpio2_23 default gpio2_23 gpio2_23 gpio2_23 gpio2_23 pru1_out9 pru1_in9"
+P1_02_CAPE=""
+
+P1_03_PIN="system"
+P1_03_INFO="usb1_vbus_out"
+P1_03_CAPE=""
+
+P1_04_PRU="121"
+P1_04_GPIO="89"
+P1_04_PIN="gpio"
+P1_04_PINMUX="default gpio gpio_pu gpio_pd gpio_input pruout pruin"
+P1_04_INFO="gpio2_25 default gpio2_25 gpio2_25 gpio2_25 gpio2_25 pru1_out11 pru1_in11"
+P1_04_CAPE=""
+
+P1_05_PIN="system"
+P1_05_INFO="usb1_vbus_in"
+P1_05_CAPE=""
+
+P1_06_PRU="37"
+P1_06_GPIO="5"
+P1_06_PIN="spi_cs"
+P1_06_PINMUX="default gpio gpio_pu gpio_pd gpio_input spi_cs i2c pwm pru_uart"
+P1_06_INFO="spi0_cs0 default gpio0_5 gpio0_5 gpio0_5 gpio0_5 spi0_cs0 i2c1_scl ehrpwm0_synci pru_uart"
+P1_06_CAPE=""
+
+P1_07_PIN="system"
+P1_07_INFO="VIN-USB"
+P1_07_CAPE=""
+
+P1_08_PRU="34"
+P1_08_GPIO="2"
+P1_08_PIN="spi_sclk"
+P1_08_PINMUX="default gpio gpio_pu gpio_pd gpio_input spi_sclk uart i2c pwm pru_uart"
+P1_08_INFO="spi0_sclk default gpio0_2 gpio0_2 gpio0_2 gpio0_2 spi0_sclk uart2_rxd i2c2_sda ehrpwm0a pru_uart"
+P1_08_CAPE=""
+
+P1_09_PIN="system"
+P1_09_INFO="USB1-DN"
+P1_09_CAPE=""
+
+P1_10_PRU="35"
+P1_10_GPIO="3"
+P1_10_PIN="spi"
+P1_10_PINMUX="default gpio gpio_pu gpio_pd gpio_input spi uart i2c pwm pru_uart"
+P1_10_INFO="spi0_d0 default gpio0_3 gpio0_3 gpio0_3 gpio0_3 spi0_d0 uart2_txd i2c2_scl ehrpwm0b pru_uart"
+P1_10_CAPE=""
+
+P1_11_PIN="system"
+P1_11_INFO="USB1-DP"
+P1_11_CAPE=""
+
+P1_12_PRU="36"
+P1_12_GPIO="4"
+P1_12_PIN="spi"
+P1_12_PINMUX="default gpio gpio_pu gpio_pd gpio_input spi i2c pwm pru_uart"
+P1_12_INFO="spi0_d1 default gpio0_4 gpio0_4 gpio0_4 gpio0_4 spi0_d1 i2c1_sda ehrpwm0_tripzone_input pru_uart"
+P1_12_CAPE=""
+
+P1_13_PIN="system"
+P1_13_INFO="USB1-ID"
+P1_13_CAPE=""
+
+P1_14_PIN="power"
+P1_14_INFO="VOUT-3.3V"
+P1_14_CAPE=""
+
+P1_15_PIN="gnd"
+P1_15_INFO="GND"
+P1_15_CAPE=""
+
+P1_16_PIN="gnd"
+P1_16_INFO="GND"
+P1_16_CAPE=""
+
+P1_17_PIN="power"
+P1_17_INFO="VREFN"
+P1_17_CAPE=""
+
+P1_18_PIN="power"
+P1_18_INFO="VREFP"
+P1_18_CAPE=""
+
+P1_19_PIN="adc"
+P1_19_INFO="AIN0"
+P1_19_CAPE=""
+
+P1_20_PRU="52"
+P1_20_GPIO="20"
+P1_20_PIN="gpio"
+P1_20_PINMUX="default gpio gpio_pu gpio_pd gpio_input pruin"
+P1_20_INFO="gpio0_20 default gpio0_20 gpio0_20 gpio0_20 gpio0_20 pru0_in16"
+P1_20_CAPE=""
+
+P1_21_PIN="adc"
+P1_21_INFO="AIN1"
+P1_21_CAPE=""
+
+P1_22_PIN="gnd"
+P1_22_INFO="GND"
+P1_22_CAPE=""
+
+P1_23_PIN="adc"
+P1_23_INFO="AIN2"
+P1_23_CAPE=""
+
+P1_24_PIN="power"
+P1_24_INFO="VOUT-5V"
+P1_24_CAPE=""
+
+P1_25_PIN="adc"
+P1_25_INFO="AIN3"
+P1_25_CAPE=""
+
+P1_26_PRU="44"
+P1_26_GPIO="12"
+P1_26_PIN="i2c"
+P1_26_PINMUX="default gpio gpio_pu gpio_pd gpio_input spi_cs can i2c pru_uart"
+P1_26_INFO="i2c2_sda default gpio0_12 gpio0_12 gpio0_12 gpio0_12 spi1_cs0 dcan0_tx i2c2_sda pru_uart"
+P1_26_CAPE=""
+
+P1_27_PIN="adc"
+P1_27_INFO="AIN4"
+P1_27_CAPE=""
+
+P1_28_PRU="45"
+P1_28_GPIO="13"
+P1_28_PIN="i2c"
+P1_28_PINMUX="default gpio gpio_pu gpio_pd gpio_input spi_cs can i2c pru_uart"
+P1_28_INFO="i2c2_scl default gpio0_13 gpio0_13 gpio0_13 gpio0_13 spi1_cs1 dcan0_rx i2c2_scl pru_uart"
+P1_28_CAPE=""
+
+P1_29_PRU="149"
+P1_29_GPIO="117"
+P1_29_PIN="pruin"
+P1_29_PINMUX="default gpio gpio_pu gpio_pd gpio_input qep pruout pruin"
+P1_29_INFO="pru0_in7 default gpio3_21 gpio3_21 gpio3_21 gpio3_21 eqep0_strobe pru0_out7 pru0_in7"
+P1_29_CAPE=""
+
+P1_30_PRU="75"
+P1_30_GPIO="43"
+P1_30_PIN="uart"
+P1_30_PINMUX="default gpio gpio_pu gpio_pd gpio_input spi_cs uart can i2c pruout pruin"
+P1_30_INFO="uart0_txd default gpio1_11 gpio1_11 gpio1_11 gpio1_11 spi1_cs1 uart0_txd dcan0_rx i2c2_scl pru1_out15 pru1_in15"
+P1_30_CAPE=""
+
+P1_31_PRU="146"
+P1_31_GPIO="114"
+P1_31_PIN="pruin"
+P1_31_PINMUX="default gpio gpio_pu gpio_pd gpio_input qep pruout pruin"
+P1_31_INFO="pru0_in4 default gpio3_18 gpio3_18 gpio3_18 gpio3_18 eqep0a_in pru0_out4 pru0_in4"
+P1_31_CAPE=""
+
+P1_32_PRU="74"
+P1_32_GPIO="42"
+P1_32_PIN="uart"
+P1_32_PINMUX="default gpio gpio_pu gpio_pd gpio_input spi_cs uart can i2c pruout pruin"
+P1_32_INFO="uart0_rxd default gpio1_10 gpio1_10 gpio1_10 gpio1_10 spi1_cs0 uart0_rxd dcan0_tx i2c2_sda pru1_out14 pru1_in14"
+P1_32_CAPE=""
+
+P1_33_PRU="143"
+P1_33_GPIO="111"
+P1_33_PIN="pruin"
+P1_33_PINMUX="default gpio gpio_pu gpio_pd gpio_input spi pwm pruout pruin"
+P1_33_INFO="pru0_in1 default gpio3_15 gpio3_15 gpio3_15 gpio3_15 spi1_d0 ehrpwm0b pru0_out1 pru0_in1"
+P1_33_CAPE=""
+
+P1_34_PRU="58"
+P1_34_GPIO="26"
+P1_34_PIN="gpio"
+P1_34_PINMUX="default gpio gpio_pu gpio_pd gpio_input pwm"
+P1_34_INFO="gpio0_26 default gpio0_26 gpio0_26 gpio0_26 gpio0_26 ehrpwm2_tripzone_input"
+P1_34_CAPE=""
+
+P1_35_PRU="120"
+P1_35_GPIO="88"
+P1_35_PIN="pruin"
+P1_35_PINMUX="default gpio gpio_pu gpio_pd gpio_input pruout pruin"
+P1_35_INFO="pru1_in10 default gpio2_24 gpio2_24 gpio2_24 gpio2_24 pru1_out10 pru1_in10"
+P1_35_CAPE=""
+
+P1_36_PRU="142"
+P1_36_GPIO="110"
+P1_36_PIN="pwm"
+P1_36_PINMUX="default gpio gpio_pu gpio_pd gpio_input spi_sclk pwm pruout pruin"
+P1_36_INFO="ehrpwm0a default gpio3_14 gpio3_14 gpio3_14 gpio3_14 spi1_sclk ehrpwm0a pru0_out0 pru0_in0"
+P1_36_CAPE=""
+
+P2_01_PRU="82"
+P2_01_GPIO="50"
+P2_01_PIN="pwm"
+P2_01_PINMUX="default gpio gpio_pu gpio_pd gpio_input pwm"
+P2_01_INFO="ehrpwm1a default gpio1_18 gpio1_18 gpio1_18 gpio1_18 ehrpwm1a"
+P2_01_CAPE=""
+
+P2_02_PRU="91"
+P2_02_GPIO="59"
+P2_02_PIN="gpio"
+P2_02_PINMUX="default gpio gpio_pu gpio_pd gpio_input"
+P2_02_INFO="gpio1_27 default gpio1_27 gpio1_27 gpio1_27 gpio1_27"
+P2_02_CAPE=""
+
+P2_03_PRU="55"
+P2_03_GPIO="23"
+P2_03_PIN="gpio"
+P2_03_PINMUX="default gpio gpio_pu gpio_pd gpio_input pwm"
+P2_03_INFO="gpio0_23 default gpio0_23 gpio0_23 gpio0_23 gpio0_23 ehrpwm2b"
+P2_03_CAPE=""
+
+P2_04_PRU="90"
+P2_04_GPIO="58"
+P2_04_PIN="gpio"
+P2_04_PINMUX="default gpio gpio_pu gpio_pd gpio_input"
+P2_04_INFO="gpio1_26 default gpio1_26 gpio1_26 gpio1_26 gpio1_26"
+P2_04_CAPE=""
+
+P2_05_PRU="62"
+P2_05_GPIO="30"
+P2_05_PIN="uart"
+P2_05_PINMUX="default gpio gpio_pu gpio_pd gpio_input uart"
+P2_05_INFO="uart4_rxd default gpio0_30 gpio0_30 gpio0_30 gpio0_30 uart4_rxd"
+P2_05_CAPE=""
+
+P2_06_PRU="89"
+P2_06_GPIO="57"
+P2_06_PIN="gpio"
+P2_06_PINMUX="default gpio gpio_pu gpio_pd gpio_input"
+P2_06_INFO="gpio1_25 default gpio1_25 gpio1_25 gpio1_25 gpio1_25"
+P2_06_CAPE=""
+
+P2_07_PRU="63"
+P2_07_GPIO="31"
+P2_07_PIN="uart"
+P2_07_PINMUX="default gpio gpio_pu gpio_pd gpio_input uart"
+P2_07_INFO="uart4_txd default gpio0_31 gpio0_31 gpio0_31 gpio0_31 uart4_txd"
+P2_07_CAPE=""
+
+P2_08_PRU="92"
+P2_08_GPIO="60"
+P2_08_PIN="gpio"
+P2_08_PINMUX="default gpio gpio_pu gpio_pd gpio_input"
+P2_08_INFO="gpio1_28 default gpio1_28 gpio1_28 gpio1_28 gpio1_28"
+P2_08_CAPE=""
+
+P2_09_PRU="47"
+P2_09_GPIO="15"
+P2_09_PIN="i2c"
+P2_09_PINMUX="default gpio gpio_pu gpio_pd gpio_input uart can i2c pru_uart pruin"
+P2_09_INFO="i2c1_scl default gpio0_15 gpio0_15 gpio0_15 gpio0_15 uart1_txd dcan1_rx i2c1_scl pru_uart pru0_in16"
+P2_09_CAPE=""
+
+P2_10_PRU="84"
+P2_10_GPIO="52"
+P2_10_PIN="gpio"
+P2_10_PINMUX="default gpio gpio_pu gpio_pd gpio_input qep"
+P2_10_INFO="gpio1_20 default gpio1_20 gpio1_20 gpio1_20 gpio1_20 eqep1a_in"
+P2_10_CAPE=""
+
+P2_11_PRU="46"
+P2_11_GPIO="14"
+P2_11_PIN="i2c"
+P2_11_PINMUX="default gpio gpio_pu gpio_pd gpio_input uart can i2c pru_uart pruin"
+P2_11_INFO="i2c1_sda default gpio0_14 gpio0_14 gpio0_14 gpio0_14 uart1_rxd dcan1_tx i2c1_sda pru_uart pru1_in16"
+P2_11_CAPE=""
+
+P2_12_PIN="system"
+P2_12_INFO="POWER_BUTTON"
+P2_12_CAPE=""
+
+P2_13_PIN="power"
+P2_13_INFO="VOUT-5V"
+P2_13_CAPE=""
+
+P2_14_PIN="power"
+P2_14_INFO="BAT-VIN"
+P2_14_CAPE=""
+
+P2_15_PIN="gnd"
+P2_15_INFO="GND"
+P2_15_CAPE=""
+
+P2_16_PIN="power"
+P2_16_INFO="BAT-TEMP"
+P2_16_CAPE=""
+
+P2_17_PRU="97"
+P2_17_GPIO="65"
+P2_17_PIN="gpio"
+P2_17_PINMUX="default gpio gpio_pu gpio_pd gpio_input"
+P2_17_INFO="gpio2_1 default gpio2_1 gpio2_1 gpio2_1 gpio2_1"
+P2_17_CAPE=""
+
+P2_18_PRU="79"
+P2_18_GPIO="47"
+P2_18_PIN="gpio"
+P2_18_PINMUX="default gpio gpio_pu gpio_pd gpio_input qep pru_ecap pruin"
+P2_18_INFO="gpio1_15 default gpio1_15 gpio1_15 gpio1_15 gpio1_15 eqep2_strobe pru_ecap pru0_in15"
+P2_18_CAPE=""
+
+P2_19_PRU="59"
+P2_19_GPIO="27"
+P2_19_PIN="gpio"
+P2_19_PINMUX="default gpio gpio_pu gpio_pd gpio_input pwm"
+P2_19_INFO="gpio0_27 default gpio0_27 gpio0_27 gpio0_27 gpio0_27 ehrpwm0_synco"
+P2_19_CAPE=""
+
+P2_20_PRU="96"
+P2_20_GPIO="64"
+P2_20_PIN="gpio"
+P2_20_PINMUX="default gpio gpio_pu gpio_pd gpio_input"
+P2_20_INFO="gpio2_0 default gpio2_0 gpio2_0 gpio2_0 gpio2_0"
+P2_20_CAPE=""
+
+P2_21_PIN="gnd"
+P2_21_INFO="GND"
+P2_21_CAPE=""
+
+P2_22_PRU="78"
+P2_22_GPIO="46"
+P2_22_PIN="gpio"
+P2_22_PINMUX="default gpio gpio_pu gpio_pd gpio_input qep pruin"
+P2_22_INFO="gpio1_14 default gpio1_14 gpio1_14 gpio1_14 gpio1_14 eqep2_index pru0_in14"
+P2_22_CAPE=""
+
+P2_23_PIN="power"
+P2_23_INFO="VOUT-3.3V"
+P2_23_CAPE=""
+
+P2_24_PRU="76"
+P2_24_GPIO="44"
+P2_24_PIN="gpio"
+P2_24_PINMUX="default gpio gpio_pu gpio_pd gpio_input qep pruout"
+P2_24_INFO="gpio1_12 default gpio1_12 gpio1_12 gpio1_12 gpio1_12 eqep2a_in pru0_out14"
+P2_24_CAPE=""
+
+P2_25_PRU="73"
+P2_25_GPIO="41"
+P2_25_PIN="spi"
+P2_25_PINMUX="default gpio gpio_pu gpio_pd gpio_input spi spi_cs uart can i2c"
+P2_25_INFO="spi1_d1 default gpio1_9 gpio1_9 gpio1_9 gpio1_9 spi1_d1 spi1_cs0 uart4_txd dcan1_rx i2c1_scl"
+P2_25_CAPE=""
+
+P2_26_PIN="system"
+P2_26_INFO="RESET#"
+P2_26_CAPE=""
+
+P2_27_PRU="72"
+P2_27_GPIO="40"
+P2_27_PIN="spi"
+P2_27_PINMUX="default gpio gpio_pu gpio_pd gpio_input spi uart can i2c"
+P2_27_INFO="spi1_d0 default gpio1_8 gpio1_8 gpio1_8 gpio1_8 spi1_d0 uart4_rxd dcan1_tx i2c1_sda"
+P2_27_CAPE=""
+
+P2_28_PRU="148"
+P2_28_GPIO="116"
+P2_28_PIN="pruin"
+P2_28_PINMUX="default gpio gpio_pu gpio_pd gpio_input qep pruout pruin"
+P2_28_INFO="pru0_in6 default gpio3_20 gpio3_20 gpio3_20 gpio3_20 eqep0_index pru0_out6 pru0_in6"
+P2_28_CAPE=""
+
+P2_29_PRU="39"
+P2_29_GPIO="7"
+P2_29_PIN="spi_sclk"
+P2_29_PINMUX="default gpio gpio_pu gpio_pd gpio_input spi_cs spi_sclk uart pwm pru_ecap"
+P2_29_INFO="spi1_sclk default gpio0_7 gpio0_7 gpio0_7 gpio0_7 spi1_cs1 spi1_sclk uart3_txd ecap0_in_pwm0_out pru_ecap"
+P2_29_CAPE=""
+
+P2_30_PRU="145"
+P2_30_GPIO="113"
+P2_30_PIN="pruin"
+P2_30_PINMUX="default gpio gpio_pu gpio_pd gpio_input spi_cs pwm pruout pruin"
+P2_30_INFO="pru0_in3 default gpio3_17 gpio3_17 gpio3_17 gpio3_17 spi1_cs0 ehrpwm0_synci pru0_out3 pru0_in3"
+P2_30_CAPE=""
+
+P2_31_PRU="51"
+P2_31_GPIO="19"
+P2_31_PIN="spi_cs"
+P2_31_PINMUX="default gpio gpio_pu gpio_pd gpio_input spi_cs pruin"
+P2_31_INFO="spi1_cs1 default gpio0_19 gpio0_19 gpio0_19 gpio0_19 spi1_cs1 pru1_in16"
+P2_31_CAPE=""
+
+P2_32_PRU="144"
+P2_32_GPIO="112"
+P2_32_PIN="pruin"
+P2_32_PINMUX="default gpio gpio_pu gpio_pd gpio_input spi pwm pruout pruin"
+P2_32_INFO="pru0_in2 default gpio3_16 gpio3_16 gpio3_16 gpio3_16 spi1_d1 ehrpwm0_tripzone_input pru0_out2 pru0_in2"
+P2_32_CAPE=""
+
+P2_33_PRU="77"
+P2_33_GPIO="45"
+P2_33_PIN="gpio"
+P2_33_PINMUX="default gpio gpio_pu gpio_pd gpio_input qep pruout"
+P2_33_INFO="gpio1_13 default gpio1_13 gpio1_13 gpio1_13 gpio1_13 eqep2b_in pru0_out15"
+P2_33_CAPE=""
+
+P2_34_PRU="147"
+P2_34_GPIO="115"
+P2_34_PIN="pruin"
+P2_34_PINMUX="default gpio gpio_pu gpio_pd gpio_input qep pruout pruin"
+P2_34_INFO="pru0_in5 default gpio3_19 gpio3_19 gpio3_19 gpio3_19 eqep0b_in pru0_out5 pru0_in5"
+P2_34_CAPE=""
+
+P2_35_PRU="118"
+P2_35_GPIO="86"
+P2_35_PIN="gpio_input"
+P2_35_PINMUX="default gpio gpio_pu gpio_pd gpio_input pruout pruin"
+P2_35_INFO="gpio2_22 default gpio2_22 gpio2_22 gpio2_22 gpio2_22 pru1_out8 pru1_in8"
+P2_35_CAPE=""
+
+P2_36_PIN="adc"
+P2_36_INFO="AIN7"
+P2_36_CAPE=""
+
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/tools/pinmux-generator/lib/pinmux.sh b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/tools/pinmux-generator/lib/pinmux.sh
new file mode 100644
index 0000000000000000000000000000000000000000..68bd40c9101080a65a7240e739c79d1d7ff969c7
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/tools/pinmux-generator/lib/pinmux.sh
@@ -0,0 +1,666 @@
+#!/bin/bash
+
+#cat AM335x.json | jq '.devicePins'
+#cat AM335x.json | jq '.useCases'
+#cat AM335x.json | jq '.packages .ID_0 .packagePin[202] .devicePinID'
+
+echo_both () {
+#	echo "$msg"
+	echo "$msg" >> ${file}.dts
+	echo "$msg" >> ${file}-pinmux.dts
+}
+
+echo_label () {
+	msg="/* ${pcbpin}                ${label_info} */" ; echo_both ; msg="" ; echo_both
+	echo "${pcbpin}_PIN=\"${label_pin}\"" >>${file}_config-pin.txt
+	echo "${pcbpin}_INFO=\"${label_info}\"" >>${file}_config-pin.txt
+	echo "${pcbpin}_CAPE=\"\"" >>${file}_config-pin.txt
+	echo "" >>${file}_config-pin.txt
+}
+
+echo_label_analog () {
+	msg="/* ${pcbpin} (ZCZ ball ${ball})  ${label_info}         */" ; echo_both ; msg="" ; echo_both
+	echo "${pcbpin}_PIN=\"${label_pin}\"" >>${file}_config-pin.txt
+	echo "${pcbpin}_INFO=\"${label_info}\"" >>${file}_config-pin.txt
+	echo "${pcbpin}_CAPE=\"\"" >>${file}_config-pin.txt
+	echo "" >>${file}_config-pin.txt
+}
+
+echo_pinmux () {
+	if [ "x${cp_default}" = "x" ] ; then
+		echo "/* ${pcbpin} (ZCZ ball ${found_ball}) */" >> ${file}-pinmux.dts
+	else
+		echo "/* ${pcbpin} (ZCZ ball ${found_ball}) ${cp_default} */" >> ${file}-pinmux.dts
+		unset default_name
+	fi
+	echo "${pcbpin}_pinmux {" >> ${file}-pinmux.dts
+	echo "	compatible = \"bone-pinmux-helper\";" >> ${file}-pinmux.dts
+	echo "	status = \"okay\";" >> ${file}-pinmux.dts
+	list="\"default\", \"gpio\", \"gpio_pu\", \"gpio_pd\", \"gpio_input\""
+	cp_pinmux="default gpio gpio_pu gpio_pd gpio_input"
+	if [ "x${cp_info_default}" = "x" ] ; then
+		cp_info="${gpio_name} default ${gpio_name} ${gpio_name} ${gpio_name} ${gpio_name}"
+	else
+		cp_info="${cp_info_default} default ${gpio_name} ${gpio_name} ${gpio_name} ${gpio_name}"
+		unset cp_info_default
+	fi
+	if [ "x${got_spi_pin}" = "xenable" ] ; then
+		list="${list}, \"spi\""
+		cp_pinmux="${cp_pinmux} spi"
+		cp_info="${cp_info} ${spi_name}"
+	fi
+	if [ "x${got_spi_cs_pin}" = "xenable" ] ; then
+		list="${list}, \"spi_cs\""
+		cp_pinmux="${cp_pinmux} spi_cs"
+		cp_info="${cp_info} ${spi_cs_name}"
+	fi
+	if [ "x${got_spi_sclk_pin}" = "xenable" ] ; then
+		list="${list}, \"spi_sclk\""
+		cp_pinmux="${cp_pinmux} spi_sclk"
+		cp_info="${cp_info} ${spi_sclk_name}"
+	fi
+	if [ "x${got_uart_pin}" = "xenable" ] ; then
+		list="${list}, \"uart\""
+		cp_pinmux="${cp_pinmux} uart"
+		cp_info="${cp_info} ${uart_name}"
+	fi
+	if [ "x${got_can_pin}" = "xenable" ] ; then
+		list="${list}, \"can\""
+		cp_pinmux="${cp_pinmux} can"
+		cp_info="${cp_info} ${can_name}"
+	fi
+	if [ "x${got_i2c_pin}" = "xenable" ] ; then
+		list="${list}, \"i2c\""
+		cp_pinmux="${cp_pinmux} i2c"
+		cp_info="${cp_info} ${i2c_name}"
+	fi
+	if [ "x${got_eqep_pin}" = "xenable" ] ; then
+		list="${list}, \"qep\""
+		cp_pinmux="${cp_pinmux} qep"
+		cp_info="${cp_info} ${eqep_name}"
+	fi
+	if [ "x${got_pwm_pin}" = "xenable" ] ; then
+		list="${list}, \"pwm\""
+		cp_pinmux="${cp_pinmux} pwm"
+		cp_info="${cp_info} ${pwm_name}"
+	fi
+	if [ "x${got_pwm2_pin}" = "xenable" ] ; then
+		list="${list}, \"pwm2\""
+		cp_pinmux="${cp_pinmux} pwm2"
+		cp_info="${cp_info} ${pwm2_name}"
+	fi
+	if [ "x${got_pru_uart_pin}" = "xenable" ] ; then
+		list="${list}, \"pru_uart\""
+		cp_pinmux="${cp_pinmux} pru_uart"
+		cp_info="${cp_info} pru_uart"
+	fi
+	if [ "x${got_timer_pin}" = "xenable" ] ; then
+		list="${list}, \"timer\""
+		cp_pinmux="${cp_pinmux} timer"
+		cp_info="${cp_info} ${timer_name}"
+	fi
+	if [ "x${got_pru_ecap_pin}" = "xenable" ] ; then
+		list="${list}, \"pru_ecap\""
+		cp_pinmux="${cp_pinmux} pru_ecap"
+		cp_info="${cp_info} pru_ecap"
+	fi
+	if [ "x${got_pruout_pin}" = "xenable" ] ; then
+		list="${list}, \"pruout\""
+		cp_pinmux="${cp_pinmux} pruout"
+		cp_info="${cp_info} ${pruout_name}"
+	fi
+	if [ "x${got_pruin_pin}" = "xenable" ] ; then
+		list="${list}, \"pruin\""
+		cp_pinmux="${cp_pinmux} pruin"
+		cp_info="${cp_info} ${pruin_name}"
+	fi
+
+	echo "${pcbpin}_PRU=\"${cp_pru_gpio_number}\"" >> ${file}_config-pin.txt
+	echo "${pcbpin}_GPIO=\"${cp_gpio_number}\"" >> ${file}_config-pin.txt
+
+	if [ "x${cp_default}" = "x" ] ; then
+		echo "${pcbpin}_PIN=\"gpio\"" >> ${file}_config-pin.txt
+	else
+		echo "${pcbpin}_PIN=\"${cp_default}\"" >> ${file}_config-pin.txt
+		unset cp_default
+	fi
+
+	echo "${pcbpin}_PINMUX=\"${cp_pinmux}\"" >> ${file}_config-pin.txt
+	echo "${pcbpin}_INFO=\"${cp_info}\"" >> ${file}_config-pin.txt
+	echo "${pcbpin}_CAPE=\"\"" >> ${file}_config-pin.txt
+	echo "" >> ${file}_config-pin.txt
+
+	echo "	pinctrl-names = ${list};" >> ${file}-pinmux.dts
+	echo "	pinctrl-0 = <&${pcbpin}_default_pin>;" >> ${file}-pinmux.dts
+	echo "	pinctrl-1 = <&${pcbpin}_gpio_pin>;" >> ${file}-pinmux.dts
+	echo "	pinctrl-2 = <&${pcbpin}_gpio_pu_pin>;" >> ${file}-pinmux.dts
+	echo "	pinctrl-3 = <&${pcbpin}_gpio_pd_pin>;" >> ${file}-pinmux.dts
+	echo "	pinctrl-4 = <&${pcbpin}_gpio_input_pin>;" >> ${file}-pinmux.dts
+	index=5
+	if [ "x${got_spi_pin}" = "xenable" ] ; then
+		echo "	pinctrl-${index} = <&${pcbpin}_spi_pin>;" >> ${file}-pinmux.dts
+		index=$((index + 1))
+	fi
+	if [ "x${got_spi_cs_pin}" = "xenable" ] ; then
+		echo "	pinctrl-${index} = <&${pcbpin}_spi_cs_pin>;" >> ${file}-pinmux.dts
+		index=$((index + 1))
+	fi
+	if [ "x${got_spi_sclk_pin}" = "xenable" ] ; then
+		echo "	pinctrl-${index} = <&${pcbpin}_spi_sclk_pin>;" >> ${file}-pinmux.dts
+		index=$((index + 1))
+	fi
+	if [ "x${got_uart_pin}" = "xenable" ] ; then
+		echo "	pinctrl-${index} = <&${pcbpin}_uart_pin>;" >> ${file}-pinmux.dts
+		index=$((index + 1))
+	fi
+	if [ "x${got_can_pin}" = "xenable" ] ; then
+		echo "	pinctrl-${index} = <&${pcbpin}_can_pin>;" >> ${file}-pinmux.dts
+		index=$((index + 1))
+	fi
+	if [ "x${got_i2c_pin}" = "xenable" ] ; then
+		echo "	pinctrl-${index} = <&${pcbpin}_i2c_pin>;" >> ${file}-pinmux.dts
+		index=$((index + 1))
+	fi
+	if [ "x${got_eqep_pin}" = "xenable" ] ; then
+		echo "	pinctrl-${index} = <&${pcbpin}_qep_pin>;" >> ${file}-pinmux.dts
+		index=$((index + 1))
+	fi
+	if [ "x${got_pwm_pin}" = "xenable" ] ; then
+		echo "	pinctrl-${index} = <&${pcbpin}_pwm_pin>;" >> ${file}-pinmux.dts
+		index=$((index + 1))
+	fi
+	if [ "x${got_pwm2_pin}" = "xenable" ] ; then
+		echo "	pinctrl-${index} = <&${pcbpin}_pwm2_pin>;" >> ${file}-pinmux.dts
+		index=$((index + 1))
+	fi
+	if [ "x${got_pru_uart_pin}" = "xenable" ] ; then
+		echo "	pinctrl-${index} = <&${pcbpin}_pru_uart_pin>;" >> ${file}-pinmux.dts
+		index=$((index + 1))
+	fi
+	if [ "x${got_pru_ecap_pin}" = "xenable" ] ; then
+		echo "	pinctrl-${index} = <&${pcbpin}_pru_ecap_pin>;" >> ${file}-pinmux.dts
+		index=$((index + 1))
+	fi
+	if [ "x${got_timer_pin}" = "xenable" ] ; then
+		echo "	pinctrl-${index} = <&${pcbpin}_timer_pin>;" >> ${file}-pinmux.dts
+		index=$((index + 1))
+	fi
+	if [ "x${got_pruout_pin}" = "xenable" ] ; then
+		echo "	pinctrl-${index} = <&${pcbpin}_pruout_pin>;" >> ${file}-pinmux.dts
+		index=$((index + 1))
+	fi
+	if [ "x${got_pruin_pin}" = "xenable" ] ; then
+		echo "	pinctrl-${index} = <&${pcbpin}_pruin_pin>;" >> ${file}-pinmux.dts
+		index=$((index + 1))
+	fi
+
+	echo "};" >> ${file}-pinmux.dts
+	echo "" >> ${file}-pinmux.dts
+}
+
+echo_gpio () {
+	echo "	${pcbpin} {" >> ${file}-gpio.dts
+	echo "		gpio-name = \"${pcbpin}\";" >> ${file}-gpio.dts
+	echo "		gpio = <&${gpio_pinmux} 0>;" >> ${file}-gpio.dts
+	echo "		input;" >> ${file}-gpio.dts
+	echo "		dir-changeable;" >> ${file}-gpio.dts
+	echo "	};" >> ${file}-gpio.dts
+	echo "">> ${file}-gpio.dts
+}
+
+get_json_pkg () {
+	###Offline: http://processors.wiki.ti.com/index.php/TI_PinMux_Tool
+	pinmux_version="4.0.1526"
+	if [ -d ./tmp/ ] ; then
+		rm -rf ./tmp/ || true
+	fi
+	wget -c http://software-dl.ti.com/ccs/esd/pinmux/pinmux-${pinmux_version}-setup.run
+	chmod +x pinmux-${pinmux_version}-setup.run
+	mkdir tmp
+	./pinmux-${pinmux_version}-setup.run --unattendedmodeui none --mode unattended --prefix ./tmp
+	cp -v tmp/pinmux/deviceData/AM335x/AM335x.json ./
+	rm -rf ./tmp/ || true
+	rm -rf pinmux-${pinmux_version}-setup.run || true
+	rm -rf pinmux_${pinmux_version}.log || true
+}
+
+get_name_mode () {
+	#cat AM335x.json | jq '.pinCommonInfos .'${found_devicePinID}' .pinModeInfo['$number'] .signalName' | sed 's/\"//g' | sed 's/\[/_/g' | sed 's/\]//g' || true
+
+	name=$(cat AM335x.json | jq '.pinCommonInfos .'${found_devicePinID}' .pinModeInfo['$number'] .signalName' | sed 's/\"//g' | sed 's/\[/_/g' | sed 's/\]//g' | awk '{print tolower($0)}' || true)
+	mode=$(cat AM335x.json | jq '.pinCommonInfos .'${found_devicePinID}' .pinModeInfo['$number'] .mode' | sed 's/\"//g' | awk '{print tolower($0)}' || true)
+	ioDir=$(cat AM335x.json | jq '.pinCommonInfos .'${found_devicePinID}' .pinModeInfo['$number'] .ioDir' | sed 's/\"//g' || true)
+}
+
+find_ball () {
+	echo "##################"
+	echo "${pcbpin}"
+	#Use "ball" to get devicePinID & powerDomainID
+
+	#cat AM335x.json | jq '.packages .ID_0 .packagePin[0]'
+	#{
+	#  "devicePinID": "ID_1690",
+	#  "ball": "R13",
+	#  "powerDomainID": "ID_1691"
+	#}
+
+	for number in {0..202}
+	do
+		compare=$(cat AM335x.json | jq '.packages .ID_0 .packagePin['$number'] .ball' | sed 's/\"//g' || true)
+		if [ "x${compare}" = "x${ball}" ] ; then
+			#echo "debug-${ball}-----------------------------------------"
+			#cat AM335x.json | jq '.packages .ID_0 .packagePin['$number']'
+			#echo "debug-${ball}-----------------------------------------"
+			found_devicePinID=$(cat AM335x.json | jq '.packages .ID_0 .packagePin['$number'] .devicePinID' | sed 's/\"//g' || true)
+			found_ball=$(cat AM335x.json | jq '.packages .ID_0 .packagePin['$number'] .ball' | sed 's/\"//g' || true)
+			found_powerDomainID=$(cat AM335x.json | jq '.packages .ID_0 .packagePin['$number'] .powerDomainID' | sed 's/\"//g' || true)
+			echo "devicePinID=${found_devicePinID},ball=${found_ball},powerDomainID=${found_powerDomainID}"
+			break;
+		fi
+	done
+
+	#Using devicePinID find name
+
+	#cat AM335x.json | jq '.devicePins .ID_1985'
+	#{
+	#  "type": "DevicePin",
+	#  "name": "lcd_hsync",
+	#  "description": "",
+	#  "devicePinType": "Default",
+	#  "id": "ID_1985"
+	#}
+
+	#echo "debug-${ball}-----------------------------------------"
+	#cat AM335x.json | jq '.devicePins .'${found_devicePinID}''
+	#echo "debug-${ball}-----------------------------------------"
+	PinID=$(cat AM335x.json | jq '.devicePins .'${found_devicePinID}' .name' | sed 's/\"//g' || true)
+	echo "name=${PinID}"
+
+	#Using devicePinID find controlRegisterOffset
+
+	#cat AM335x.json | jq '.pinCommonInfos .ID_1985'
+	#{
+	#  "type": "PinCommonInfo",
+	#  "devicePinID": "ID_1985",
+	#  "controlRegisterOffset": "0x08e4",
+	#  "pupdStateDuringHHV": "OFF",
+	#  "pupdStateAfterHHV": "PD",
+
+	#echo "debug-${ball}-----------------------------------------"
+	#cat AM335x.json | jq '.pinCommonInfos .'${found_devicePinID}''
+	#echo "debug-${ball}-----------------------------------------"
+	cro=$(cat AM335x.json | jq '.pinCommonInfos .'${found_devicePinID}' .controlRegisterOffset' | sed 's/\"//g' || true)
+	echo "controlRegisterOffset=${cro}"
+
+	unset pupdStateDuringHHV
+	pupdStateDuringHHV=$(cat AM335x.json | jq '.pinCommonInfos .'${found_devicePinID}' .pupdStateDuringHHV' | sed 's/\"//g' || true)
+	echo "pupdStateDuringHHV=${pupdStateDuringHHV}"
+
+	unset pupdStateAfterHHV
+	pupdStateAfterHHV=$(cat AM335x.json | jq '.pinCommonInfos .'${found_devicePinID}' .pupdStateAfterHHV' | sed 's/\"//g' || true)
+	echo "pupdStateAfterHHV=${pupdStateAfterHHV}"
+
+	#  "pinModeInfo": [
+	#    {
+	#      "peripheralPinID": "ID_1986",
+	#      "mode": "0",
+	#      "interfaceName": "LCDC",
+	#      "signalName": "lcd_hsync",
+	#      "ioDir": "O"
+	#    },
+	#    {
+	#      "peripheralPinID": "ID_1775",
+	#      "mode": "1",
+	#      "interfaceName": "GPMC",
+	#      "signalName": "gpmc_a9",
+	#      "ioDir": "O"
+	#    },
+	#    {
+	#      "peripheralPinID": "ID_1715",
+	#      "mode": "2",
+	#      "interfaceName": "GPMC",
+	#      "signalName": "gpmc_a2",
+	#      "ioDir": "O"
+	#    },
+	#    {
+	#      "peripheralPinID": "ID_1987",
+	#      "mode": "3",
+	#      "interfaceName": "ECAT_PRUSS1",
+	#      "signalName": "pr1_edio_data_in3",
+	#      "ioDir": "I"
+	#    },
+	#    {
+	#      "peripheralPinID": "ID_1988",
+	#      "mode": "4",
+	#      "interfaceName": "ECAT_PRUSS1",
+	#      "signalName": "pr1_edio_data_out3",
+	#      "ioDir": "O"
+	#    },
+	#    {
+	#      "peripheralPinID": "ID_1989",
+	#      "mode": "5",
+	#      "interfaceName": "PRU1_PRUSS1",
+	#      "signalName": "pr1_pru1_pru_r30[9]",
+	#      "ioDir": "O"
+	#    },
+	#    {
+	#      "peripheralPinID": "ID_1990",
+	#      "mode": "6",
+	#      "interfaceName": "PRU1_PRUSS1",
+	#      "signalName": "pr1_pru1_pru_r31[9]",
+	#      "ioDir": "I"
+	#    },
+	#    {
+	#      "peripheralPinID": "ID_1991",
+	#      "mode": "7",
+	#      "interfaceName": "GPIO2",
+	#      "signalName": "gpio2[23]",
+	#      "ioDir": "IO"
+	#    }
+	#  ]
+	#}
+
+	for number in {0..7}
+	do
+		cat AM335x.json | jq '.pinCommonInfos .'${found_devicePinID}' .pinModeInfo['$number'] .interfaceName'
+		compare=$(cat AM335x.json | jq '.pinCommonInfos .'${found_devicePinID}' .pinModeInfo['$number'] .interfaceName' | sed 's/\"//g' || true)
+		get_name_mode
+		echo ${pcbpin}:${ball}:${name}:${mode}:${ioDir}:${number}
+
+#		if [ ! "x${name}" = "xnull" ] ; then
+#			echo "/* ${pcbpin}:${ball}:${name}:${mode}:${ioDir} */" >> ${file}.dts
+#		fi
+
+		if [ "x${mode}" = "x${default_mode}" ] ; then
+			echo default_mode=index=${number}
+			default_index=${number}
+		fi
+	done
+
+	unset cp_info_default
+	number=${default_index}
+	get_name_mode
+	echo ${pcbpin}:${ball}:${name}:${mode}:${ioDir}:${number}
+
+	case "${cp_default}" in
+	pruin)
+		pruin_tmp=$(echo ${name} | sed 's/pr1_//g' | sed 's/pru_r31_/in/g')
+		name=${pruin_tmp}
+		;;
+	esac
+
+	if [ ! "x${use_name}" = "x" ] ; then
+		echo "/* ${pcbpin} (ZCZ ball ${found_ball}) ${use_name} */" >> ${file}.dts
+		unset use_name
+	else
+		echo "/* ${pcbpin} (ZCZ ball ${found_ball}) ${name} */" >> ${file}.dts
+	fi
+	cp_info_default=${name}
+
+	dtabs=1
+	echo cp_default=${cp_default}
+	case "${cp_default}" in
+	gpio_input|pruin)
+		dtabs=3
+		pinsetting="PIN_INPUT"
+		;;
+	pwm|pwm2)
+		pinsetting="PIN_OUTPUT_PULLDOWN | INPUT_EN"
+		;;
+	uart|i2c|spi|spi_cs|spi_sclk)
+		pinsetting="PIN_OUTPUT_PULLUP | INPUT_EN"
+		;;
+	emmc|hdmi|audio|qep)
+		pinsetting="PIN_OUTPUT_PULLDOWN | INPUT_EN"
+		;;
+	*)
+		if [ ! "x$cp_default" = "x" ] ; then
+			exit 2
+		fi
+		case "${pupdStateAfterHHV}" in
+		PU)
+			pinsetting="PIN_OUTPUT_PULLUP | INPUT_EN"
+		;;
+		PD)
+			pinsetting="PIN_OUTPUT_PULLDOWN | INPUT_EN"
+		;;
+		*)
+			echo "pupdStateAfterHHV was not defined [${pupdStateAfterHHV}]"
+			exit 2
+		;;
+
+		esac
+		;;
+	esac
+
+	echo "${pcbpin}_default_pin: pinmux_${pcbpin}_default_pin { pinctrl-single,pins = <" >> ${file}.dts
+	if [ "x${dtabs}" = "x1" ] ; then
+		echo "	AM33XX_IOPAD(${cro}, ${pinsetting} | MUX_MODE${mode}) >; };	/* ${PinID}.${name} */" >> ${file}.dts
+	fi
+	if [ "x${dtabs}" = "x2" ] ; then
+		echo "	AM33XX_IOPAD(${cro}, ${pinsetting} | MUX_MODE${mode}) >; };		/* ${PinID}.${name} */" >> ${file}.dts
+	fi
+	if [ "x${dtabs}" = "x3" ] ; then
+		echo "	AM33XX_IOPAD(${cro}, ${pinsetting} | MUX_MODE${mode}) >; };			/* ${PinID}.${name} */" >> ${file}.dts
+	fi
+
+	number=${gpio_index}
+	get_name_mode
+
+	echo "${pcbpin}_gpio_pin: pinmux_${pcbpin}_gpio_pin { pinctrl-single,pins = <" >> ${file}.dts
+	echo "	AM33XX_IOPAD(${cro}, PIN_OUTPUT | INPUT_EN | MUX_MODE${mode}) >; };		/* ${PinID}.${name} */" >> ${file}.dts
+	echo "${pcbpin}_gpio_pu_pin: pinmux_${pcbpin}_gpio_pu_pin { pinctrl-single,pins = <" >> ${file}.dts
+	echo "	AM33XX_IOPAD(${cro}, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE${mode}) >; };	/* ${PinID}.${name} */" >> ${file}.dts
+	echo "${pcbpin}_gpio_pd_pin: pinmux_${pcbpin}_gpio_pd_pin { pinctrl-single,pins = <" >> ${file}.dts
+	echo "	AM33XX_IOPAD(${cro}, PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE${mode}) >; };	/* ${PinID}.${name} */" >> ${file}.dts
+	echo "${pcbpin}_gpio_input_pin: pinmux_${pcbpin}_gpio_input_pin { pinctrl-single,pins = <" >> ${file}.dts
+	echo "	AM33XX_IOPAD(${cro}, PIN_INPUT | MUX_MODE${mode}) >; };			/* ${PinID}.${name} */" >> ${file}.dts
+
+	gpio_mul=$(echo ${name} | awk -F'_' '{print $1}' | awk -F'gpio' '{print $2}' || true)
+	gpio_add=$(echo ${name} | awk -F'_' '{print $2}' || true)
+	cp_gpio_number=$(echo "${gpio_mul} * 32" | bc)
+	cp_gpio_number=$(echo "${cp_gpio_number} + ${gpio_add}" | bc)
+	cp_pru_gpio_number=$(echo "${cp_gpio_number} + 32" | bc)
+
+	gpio_name=${name}
+	gpio_pinmux=$(echo ${gpio_name} | sed 's/_/ /g')
+
+	unset got_can_pin
+	unset got_eqep_pin
+	unset got_pwm_pin
+	unset got_pwm2_pin
+	unset got_i2c_pin
+	unset got_pru_ecap_pin
+	unset got_pru_uart_pin
+	unset got_pruout_pin
+	unset got_pruin_pin
+	unset got_spi_pin
+	unset got_spi_cs_pin
+	unset got_spi_sclk_pin
+	unset got_timer_pin
+	unset got_uart_pin
+
+	for number in {0..7}
+	do
+		cat AM335x.json | jq '.pinCommonInfos .'${found_devicePinID}' .pinModeInfo['$number'] .interfaceName'
+		compare=$(cat AM335x.json | jq '.pinCommonInfos .'${found_devicePinID}' .pinModeInfo['$number'] .interfaceName' | sed 's/\"//g' || true)
+		get_name_mode
+		if [ ! "x${name}" = "xnull" ] ; then
+			echo ${name}
+
+			unset valid_pin_mode
+
+			tabs=1
+			case "${name}" in 
+			dcan*_rx)
+				can_name=${name}
+				valid_pin_mode="can"
+				pinsetting="PIN_INPUT_PULLUP"
+				got_can_pin="enable"
+				tabs=2
+				;;
+			dcan*_tx)
+				can_name=${name}
+				valid_pin_mode="can"
+				pinsetting="PIN_OUTPUT_PULLUP"
+				got_can_pin="enable"
+				tabs=2
+				;;
+			eqep*)
+				valid_pin_mode="qep"
+				eqep_name=${name}
+				pinsetting="PIN_OUTPUT_PULLUP | INPUT_EN"
+				got_eqep_pin="enable"
+				;;
+			ehrpwm*|ecap0_in_pwm0_out)
+				valid_pin_mode="pwm"
+				pwm_name=${name}
+				pinsetting="PIN_OUTPUT_PULLDOWN | INPUT_EN"
+				got_pwm_pin="enable"
+				;;
+			ecap2_in_pwm2_out)
+				#ignore PocketBeagle...
+				if [ ! "x${file}" = "xPocketBeagle" ] ; then
+				if [ ! "x${file}" = "xBeagleBone_Blue" ] ; then
+					valid_pin_mode="pwm2"
+					pwm2_name=${name}
+					pinsetting="PIN_OUTPUT_PULLDOWN | INPUT_EN"
+					got_pwm2_pin="enable"
+				fi
+				fi
+				;;
+			i2c*_sda|i2c*_scl)
+				valid_pin_mode="i2c"
+				i2c_name=${name}
+				pinsetting="PIN_OUTPUT_PULLUP | INPUT_EN"
+				got_i2c_pin="enable"
+				;;
+			pr1_ecap0*)
+				valid_pin_mode="pru_ecap"
+				pinsetting="PIN_OUTPUT_PULLDOWN | INPUT_EN"
+				got_pru_ecap_pin="enable"
+				;;
+			pr1_uart0*)
+				valid_pin_mode="pru_uart"
+				pinsetting="PIN_OUTPUT_PULLUP | INPUT_EN"
+				got_pru_uart_pin="enable"
+				;;
+			pr1_pru*_pru_r30*)
+				valid_pin_mode="pruout"
+				pruout_name=$(echo ${name} | sed 's/pr1_//g' | sed 's/pru_r30_/out/g')
+				name=${pruout_name}
+				pinsetting="PIN_OUTPUT_PULLDOWN | INPUT_EN"
+				got_pruout_pin="enable"
+				;;
+			pr1_pru*_pru_r31*)
+				valid_pin_mode="pruin"
+				pruin_name=$(echo ${name} | sed 's/pr1_//g' | sed 's/pru_r31_/in/g')
+				name=${pruin_name}
+				pinsetting="PIN_INPUT"
+				got_pruin_pin="enable"
+				tabs=3
+				;;
+			spi0_d0|spi1_d0)
+				valid_pin_mode="spi"
+				spi_name=${name}
+				pinsetting="PIN_INPUT_PULLUP"
+				got_spi_pin="enable"
+				tabs=2
+				;;
+			spi0_d1|spi1_d1)
+				valid_pin_mode="spi"
+				spi_name=${name}
+				pinsetting="PIN_OUTPUT_PULLUP | INPUT_EN"
+				got_spi_pin="enable"
+				;;
+			spi0_cs*|spi1_cs*)
+				valid_pin_mode="spi_cs"
+				spi_cs_name=${name}
+				pinsetting="PIN_OUTPUT_PULLUP | INPUT_EN"
+				got_spi_cs_pin="enable"
+				;;
+			spi*_sclk)
+				# See: https://www.ti.com/lit/ug/spruh73p/spruh73p.pdf page 4855
+				# (1) This output signal is also used as a re-timing input. The associated CONF_<module>_<pin>_RXACTIVE bit for the output clock
+				# must be set to 1 to enable the clock input back to the module.
+				valid_pin_mode="spi_sclk"
+				spi_sclk_name=${name}
+				pinsetting="PIN_INPUT_PULLUP"
+				got_spi_sclk_pin="enable"
+				tabs=2
+				;;
+			timer*)
+				if [ "x${disable_timer}" = "x" ] ; then
+					valid_pin_mode="timer"
+					timer_name=${name}
+					pinsetting="PIN_OUTPUT_PULLUP | INPUT_EN"
+					got_timer_pin="enable"
+				fi
+				;;
+			uart*_rxd|uart*_txd)
+				valid_pin_mode="uart"
+				uart_name=${name}
+				pinsetting="PIN_OUTPUT_PULLUP | INPUT_EN"
+				got_uart_pin="enable"
+				;;
+			esac
+
+			if [ ! "x${valid_pin_mode}" = "x" ] ; then
+				echo "${pcbpin}_${valid_pin_mode}_pin: pinmux_${pcbpin}_${valid_pin_mode}_pin { pinctrl-single,pins = <" >> ${file}.dts
+				if [ "x${tabs}" = "x1" ] ; then
+					echo "	AM33XX_IOPAD(${cro}, ${pinsetting} | MUX_MODE${mode}) >; };	/* ${PinID}.${name} */" >> ${file}.dts
+				fi
+				if [ "x${tabs}" = "x2" ] ; then
+					echo "	AM33XX_IOPAD(${cro}, ${pinsetting} | MUX_MODE${mode}) >; };		/* ${PinID}.${name} */" >> ${file}.dts
+				fi
+				if [ "x${tabs}" = "x3" ] ; then
+					echo "	AM33XX_IOPAD(${cro}, ${pinsetting} | MUX_MODE${mode}) >; };			/* ${PinID}.${name} */" >> ${file}.dts
+				fi
+			fi
+		fi
+	done
+
+echo "" >> ${file}.dts
+echo_pinmux
+echo_gpio
+
+#0x05 = 0000 0101
+#0x26 = 0010 0110
+#0x27 = 0010 0111
+#0x2F = 0010 1111
+#0x30 = 0011 0000
+#0x32 = 0011 0010
+#0x37 = 0011 0111
+
+#0x05 : PIN_OUTPUT_PULLDOWN | MUX_MODE5
+#0x24 : PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE4
+#0x26 : PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE6
+#0x27 : PIN_OUTPUT_PULLDOWN | INPUT_EN | MUX_MODE7
+#0x2F : PIN_OUTPUT | INPUT_EN | MUX_MODE7
+#0x30 : PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE0
+#0x32 : PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE2
+#0x37 : PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7
+
+#			P9_17_default_pin: pinmux_P9_17_default_pin {
+#				pinctrl-single,pins = <0x15c  0x37>; };	/* Mode 7, Pull-Up, RxActive */
+#			P9_17_gpio_pin: pinmux_P9_17_gpio_pin {
+#				pinctrl-single,pins = <0x15c  0x2F>; };	/* Mode 7, RxActive */
+#			P9_17_gpio_pu_pin: pinmux_P9_17_gpio_pu_pin {
+#				pinctrl-single,pins = <0x15c  0x37>; };	/* Mode 7, Pull-Up, RxActive */
+#			P9_17_gpio_pd_pin: pinmux_P9_17_gpio_pd_pin {
+#				pinctrl-single,pins = <0x15c  0x27>; };	/* Mode 7, Pull-Down, RxActive */
+#			P9_17_spi_pin: pinmux_P9_17_spi_pin {
+#				pinctrl-single,pins = <0x15c  0x30>; };	/* Mode 0, Pull-Up, RxActive */
+#			P9_17_i2c_pin: pinmux_P9_17_i2c_pin {
+#				pinctrl-single,pins = <0x15c  0x32>; };	/* Mode 2, Pull-Up, RxActive */
+#			P9_17_pwm_pin: pinmux_P9_17_pwm_pin {
+#				pinctrl-single,pins = <0x15c  0x33>; };	/* Mode 3, Pull-Up, RxActive */
+#			P9_17_pru_uart_pin: pinmux_P9_17_pru_uart_pin {
+#				pinctrl-single,pins = <0x15c  0x34>; };	/* Mode 4, Pull-Up, RxActive */
+
+	echo "##################"
+}
+
+if [ ! -f AM335x.json ] ; then
+	get_json_pkg
+fi
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/tools/pinmux-generator/readme.md b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/tools/pinmux-generator/readme.md
new file mode 100644
index 0000000000000000000000000000000000000000..b28f602334b4ca18cd1be6600a37601547e0268f
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/tools/pinmux-generator/readme.md
@@ -0,0 +1 @@
+needs: jq installed
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/tools/pmunts_muntsos/COPYING b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/tools/pmunts_muntsos/COPYING
new file mode 100644
index 0000000000000000000000000000000000000000..131100a92bf0f929e985bf3366207c8b815c914f
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/tools/pmunts_muntsos/COPYING
@@ -0,0 +1,24 @@
+Original works herein are copyrighted as follows:
+
+Copyright (C)2010-2019, Philip Munts, President, Munts AM Corp.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice,
+  this list of conditions and the following disclaimer.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
+
+Redistributed works herein are copyrighted and/or licensed by their
+respective authors.
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/tools/pmunts_muntsos/COPYING.preface b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/tools/pmunts_muntsos/COPYING.preface
new file mode 100644
index 0000000000000000000000000000000000000000..4f169d5ff3dc7ae86de14c7e26e924c9ef2a03c4
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/tools/pmunts_muntsos/COPYING.preface
@@ -0,0 +1,18 @@
+MuntsOS Embedded Linux Microcontroller Kernel Image
+---------------------------------------------------
+
+This Linux kernel image is built from many software components that
+are downloaded at build time.  The makefiles and everything you would
+need to reproduce this kernel image are available at:
+
+http://git.munts.com/muntsos
+
+Since many of the components that comprise this kernel image are GPL
+licensed, this image itself is therefore also licensed under the GPL.
+
+It is the opinion of the author that, under prevailing copyright law,
+a program calling functions in a shared library is not a derivative
+work of that library.
+
+The copyright and license information for all of the components that
+comprise this kernel image are included below.
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/tools/pmunts_muntsos/README.MD b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/tools/pmunts_muntsos/README.MD
new file mode 100644
index 0000000000000000000000000000000000000000..8d277a65a24759dc0801fb8303588760559598ef
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/tools/pmunts_muntsos/README.MD
@@ -0,0 +1 @@
+These files are from: MuntsOS Embedded Linux: https://github.com/pmunts/muntsos
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/tools/pmunts_muntsos/config-pin.c b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/tools/pmunts_muntsos/config-pin.c
new file mode 100644
index 0000000000000000000000000000000000000000..23d78134f46255c7ef66504705b702a5ca7a9b57
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/tools/pmunts_muntsos/config-pin.c
@@ -0,0 +1,248 @@
+// BeagleBone GPIO Pin Configurator
+// Compatible with the config-pin script available elsewhere
+
+// Copyright (C)2018, Philip Munts, President, Munts AM Corp.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+//
+// * Redistributions of source code must retain the above copyright notice,
+//   this list of conditions and the following disclaimer.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+
+#include <ctype.h>
+#include <errno.h>
+#include <fcntl.h>
+#include <stdbool.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <unistd.h>
+
+#include <sys/param.h>
+
+#define NAMES		"/sys/firmware/devicetree/base/ocp/%s_pinmux/pinctrl-names"
+#define STATE		"/sys/devices/platform/ocp/ocp:%s_pinmux/state"
+#define DELIMITERS	" \t\r\n"
+
+static void fixup_pin_name(char *s)
+{
+  for (; *s != 0; s++)
+  {
+    unsigned char c = *s;
+
+    if ((c >= 'a') && (c <= 'z'))
+      *s = toupper(c);
+    else if (c == '.')
+      *s = '_';
+  }
+}
+
+static void ListModes(char *pin)
+{
+  char filename[MAXPATHLEN];
+  int nf;
+  char buf[256];
+  ssize_t len;
+  int i;
+
+  // Sanitize the pin name parameter
+
+  fixup_pin_name(pin);
+
+  // Open the modes list file
+
+  memset(filename, 0, sizeof(filename));
+  snprintf(filename, sizeof(filename), NAMES, pin);
+
+  nf = open(filename, O_RDONLY);
+  if (nf < 1)
+  {
+    fprintf(stderr, "ERROR: open() for %s failed, %s\n", filename,
+      strerror(errno));
+    exit(1);
+  }
+
+  // Read the modes list file
+
+  len = read(nf, buf, sizeof(buf));
+  if (len < 0)
+  {
+    fprintf(stderr, "ERROR: read() from %s failed, %s\n", filename,
+      strerror(errno));
+    exit(1);
+  }
+
+  // Display the available modes
+
+  printf("\nAvailable modes for %s are:", pin);
+
+  for (i = 0; i < len; i++)
+  {
+    putchar(' ');
+    printf(buf + i);
+    i += strlen(buf + i);
+  }
+
+  puts("\n");
+  fflush(stdout);
+
+  // Close the modes list file
+
+  close(nf);
+}
+
+static void QueryMode(char *pin)
+{
+  char filename[MAXPATHLEN];
+  int sf;
+  char buf[256];
+  ssize_t len;
+
+  // Sanitize the pin name parameter
+
+  fixup_pin_name(pin);
+
+  memset(filename, 0, sizeof(filename));
+  snprintf(filename, sizeof(filename), STATE, pin);
+
+  // Open the current mode file
+
+  sf = open(filename, O_RDONLY);
+  if (sf < 1)
+  {
+    fprintf(stderr, "ERROR: open() for %s failed, %s\n", filename,
+      strerror(errno));
+    exit(1);
+  }
+
+  // Read the current mode file
+
+  len = read(sf, buf, sizeof(buf));
+  if (len < 0)
+  {
+    fprintf(stderr, "ERROR: read() from %s failed, %s\n", filename,
+      strerror(errno));
+    exit(1);
+  }
+
+  // Display the current mode
+
+  printf("\nCurrent mode for %s is:     %s\n", pin, buf);
+
+  // Close the current mode file
+
+  close(sf);
+}
+
+static void ConfigureMode(char *pin, char *mode, bool quiet)
+{
+  char filename[MAXPATHLEN];
+  int sf;
+  ssize_t len;
+
+  // Sanitize the pin name parameter
+
+  fixup_pin_name(pin);
+
+  memset(filename, 0, sizeof(filename));
+  snprintf(filename, sizeof(filename), STATE, pin);
+
+  // Open the current mode file
+
+  sf = open(filename, O_WRONLY);
+  if (sf < 1)
+  {
+    fprintf(stderr, "ERROR: open() for %s failed, %s\n", filename,
+      strerror(errno));
+    exit(1);
+  }
+
+  // Read the current mode file
+
+  len = write(sf, mode, strlen(mode));
+  if (len < 0)
+  {
+    fprintf(stderr, "ERROR: write() to %s failed, %s\n", filename,
+      strerror(errno));
+    exit(1);
+  }
+
+  // Display the current mode
+
+  if (!quiet) printf("\nCurrent mode for %s is:     %s\n\n", pin, mode);
+
+  // Close the current mode file
+
+  close(sf);
+}
+
+static void ConfigFile(char *filename)
+{
+  FILE *cf;
+  char buf[256];
+  char *pin, *mode;
+
+  // Open the specified configuration file
+
+  cf = fopen(filename, "r");
+  if (cf == NULL)
+  {
+    fprintf(stderr, "ERROR: fopen() for %s failed, %s\n", filename,
+      strerror(errno));
+    exit(1);
+  }
+
+  // Read the configuration file
+
+  while (fgets(buf, sizeof(buf), cf) != NULL)
+  {
+    pin = strtok(buf, DELIMITERS);
+    if (pin == NULL) continue;
+    if (pin[0] == '#') continue;
+
+    mode = strtok(NULL, DELIMITERS);
+    if (mode == NULL) continue;
+
+    ConfigureMode(pin, mode, true);
+  }
+
+  // Close the configuration file
+
+  fclose(cf);
+}
+
+int main(int argc, char *argv[])
+{
+  if (argc != 3)
+  {
+    fprintf(stderr, "\nGPIO Pin Configurator\n\n");
+    fprintf(stderr, "Usage: config-pin -c <filename>\n");
+    fprintf(stderr, "       config-pin -l <pin>\n");
+    fprintf(stderr, "       config-pin -q <pin>\n");
+    fprintf(stderr, "       config-pin <pin> <mode>\n\n");
+    exit(1);
+  }
+
+  if (!strcasecmp(argv[1], "-c"))
+    ConfigFile(argv[2]);
+  else if (!strcasecmp(argv[1], "-l"))
+    ListModes(argv[2]);
+  else if (!strcasecmp(argv[1], "-q"))
+    QueryMode(argv[2]);
+  else
+    ConfigureMode(argv[1], argv[2], false);
+
+  exit(0);
+}
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/tools/pmunts_muntsos/grab_latest.sh b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/tools/pmunts_muntsos/grab_latest.sh
new file mode 100644
index 0000000000000000000000000000000000000000..74b44d246b1cbc80ea4f2927d65834d6838aea33
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/tools/pmunts_muntsos/grab_latest.sh
@@ -0,0 +1,9 @@
+#!/bin/sh
+
+rm COPYING
+rm COPYING.preface
+rm config-pin.c
+
+wget https://raw.githubusercontent.com/pmunts/muntsos/master/COPYING
+wget https://raw.githubusercontent.com/pmunts/muntsos/master/bootkernel/initramfs/COPYING.preface
+wget https://raw.githubusercontent.com/pmunts/muntsos/master/bootkernel/initramfs/config-pin.c
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/usage/can/README.md b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/usage/can/README.md
new file mode 100644
index 0000000000000000000000000000000000000000..bb795f4ff4ddb03f92cfb988305ca60b3a2021bf
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/usage/can/README.md
@@ -0,0 +1,38 @@
+#
+## 安装
+```bash
+sudo apt-get install can-utils
+```
+
+
+#copy 'cansend' & 'candump' & 'ip.iproute'
+cp /mnt/b/usr/bin/cansend /usr/bin/
+cp /mnt/b/usr/bin/candump /usr/bin/
+cp /mnt/b/sbin/ip.iproute2 /sbin/
+
+
+cd /sbin/
+ln -sf ip.iproute2 ip
+
+
+##  使用方法
+设置波特率是1M，启动can
+```bash
+
+ip link set can0 type can bitrate 1000000;ip link set can0 up
+
+ip link set can1 type can bitrate 1000000;ip link set can1 up
+```
+
+
+
+发送数据
+关于cansend的用法，可以通过参数h。
+```
+cansend can0 123#abcdabcd
+```
+
+#接收数据
+```bash
+candump can0
+```
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/usage/ecspi3/README.md b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/usage/ecspi3/README.md
new file mode 100644
index 0000000000000000000000000000000000000000..4341a5d112d0304700572896766cf8f79f9401fc
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/usage/ecspi3/README.md
@@ -0,0 +1,13 @@
+# ecspi测试笔记
+
+## 编译
+```bash
+arm-linux-gnueabihf-gcc spidev_test.c -o spidev_test
+```
+
+
+## 运行
+短接板子上的MOSI和MISO：针对pro板子的IO编号为IO1.22和IO1.23
+```bash
+./spidev_test -v -D /dev/spidev2.0 -p "123a"
+```
\ No newline at end of file
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/usage/ecspi3/spidev_test.c b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/usage/ecspi3/spidev_test.c
new file mode 100644
index 0000000000000000000000000000000000000000..8c590cd1171a99c2ff7d38fb1cf7879b052acc3a
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/usage/ecspi3/spidev_test.c
@@ -0,0 +1,483 @@
+/*
+ * SPI testing utility (using spidev driver)
+ *
+ * Copyright (c) 2007  MontaVista Software, Inc.
+ * Copyright (c) 2007  Anton Vorontsov <avorontsov@ru.mvista.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License.
+ *
+ * Cross-compile with cross-gcc -I/path/to/cross-kernel/include
+ */
+
+#include <stdint.h>
+#include <unistd.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <getopt.h>
+#include <fcntl.h>
+#include <time.h>
+#include <sys/ioctl.h>
+#include <linux/ioctl.h>
+#include <sys/stat.h>
+#include <linux/types.h>
+#include <linux/spi/spidev.h>
+
+#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0]))
+
+static void pabort(const char *s)
+{
+	perror(s);
+	abort();
+}
+
+static const char *device = "/dev/spidev1.1";
+static uint32_t mode;
+static uint8_t bits = 8;
+static char *input_file;
+static char *output_file;
+static uint32_t speed = 500000;
+static uint16_t delay;
+static int verbose;
+static int transfer_size;
+static int iterations;
+static int interval = 5; /* interval in seconds for showing transfer rate */
+
+uint8_t default_tx[] = {
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0x40, 0x00, 0x00, 0x00, 0x00, 0x95,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xF0, 0x0D,
+};
+
+uint8_t default_rx[ARRAY_SIZE(default_tx)] = {0, };
+char *input_tx;
+
+static void hex_dump(const void *src, size_t length, size_t line_size,
+		     char *prefix)
+{
+	int i = 0;
+	const unsigned char *address = src;
+	const unsigned char *line = address;
+	unsigned char c;
+
+	printf("%s | ", prefix);
+	while (length-- > 0) {
+		printf("%02X ", *address++);
+		if (!(++i % line_size) || (length == 0 && i % line_size)) {
+			if (length == 0) {
+				while (i++ % line_size)
+					printf("__ ");
+			}
+			printf(" | ");  /* right close */
+			while (line < address) {
+				c = *line++;
+				printf("%c", (c < 33 || c == 255) ? 0x2E : c);
+			}
+			printf("\n");
+			if (length > 0)
+				printf("%s | ", prefix);
+		}
+	}
+}
+
+/*
+ *  Unescape - process hexadecimal escape character
+ *      converts shell input "\x23" -> 0x23
+ */
+static int unescape(char *_dst, char *_src, size_t len)
+{
+	int ret = 0;
+	int match;
+	char *src = _src;
+	char *dst = _dst;
+	unsigned int ch;
+
+	while (*src) {
+		if (*src == '\\' && *(src+1) == 'x') {
+			match = sscanf(src + 2, "%2x", &ch);
+			if (!match)
+				pabort("malformed input string");
+
+			src += 4;
+			*dst++ = (unsigned char)ch;
+		} else {
+			*dst++ = *src++;
+		}
+		ret++;
+	}
+	return ret;
+}
+
+static void transfer(int fd, uint8_t const *tx, uint8_t const *rx, size_t len)
+{
+	int ret;
+	int out_fd;
+	struct spi_ioc_transfer tr = {
+		.tx_buf = (unsigned long)tx,
+		.rx_buf = (unsigned long)rx,
+		.len = len,
+		.delay_usecs = delay,
+		.speed_hz = speed,
+		.bits_per_word = bits,
+	};
+
+	if (mode & SPI_TX_QUAD)
+		tr.tx_nbits = 4;
+	else if (mode & SPI_TX_DUAL)
+		tr.tx_nbits = 2;
+	if (mode & SPI_RX_QUAD)
+		tr.rx_nbits = 4;
+	else if (mode & SPI_RX_DUAL)
+		tr.rx_nbits = 2;
+	if (!(mode & SPI_LOOP)) {
+		if (mode & (SPI_TX_QUAD | SPI_TX_DUAL))
+			tr.rx_buf = 0;
+		else if (mode & (SPI_RX_QUAD | SPI_RX_DUAL))
+			tr.tx_buf = 0;
+	}
+
+	ret = ioctl(fd, SPI_IOC_MESSAGE(1), &tr);
+	if (ret < 1)
+		pabort("can't send spi message");
+
+	if (verbose)
+		hex_dump(tx, len, 32, "TX");
+
+	if (output_file) {
+		out_fd = open(output_file, O_WRONLY | O_CREAT | O_TRUNC, 0666);
+		if (out_fd < 0)
+			pabort("could not open output file");
+
+		ret = write(out_fd, rx, len);
+		if (ret != len)
+			pabort("not all bytes written to output file");
+
+		close(out_fd);
+	}
+
+	if (verbose)
+		hex_dump(rx, len, 32, "RX");
+}
+
+static void print_usage(const char *prog)
+{
+	printf("Usage: %s [-DsbdlHOLC3vpNR24SI]\n", prog);
+	puts("  -D --device   device to use (default /dev/spidev1.1)\n"
+	     "  -s --speed    max speed (Hz)\n"
+	     "  -d --delay    delay (usec)\n"
+	     "  -b --bpw      bits per word\n"
+	     "  -i --input    input data from a file (e.g. \"test.bin\")\n"
+	     "  -o --output   output data to a file (e.g. \"results.bin\")\n"
+	     "  -l --loop     loopback\n"
+	     "  -H --cpha     clock phase\n"
+	     "  -O --cpol     clock polarity\n"
+	     "  -L --lsb      least significant bit first\n"
+	     "  -C --cs-high  chip select active high\n"
+	     "  -3 --3wire    SI/SO signals shared\n"
+	     "  -v --verbose  Verbose (show tx buffer)\n"
+	     "  -p            Send data (e.g. \"1234\\xde\\xad\")\n"
+	     "  -N --no-cs    no chip select\n"
+	     "  -R --ready    slave pulls low to pause\n"
+	     "  -2 --dual     dual transfer\n"
+	     "  -4 --quad     quad transfer\n"
+	     "  -S --size     transfer size\n"
+	     "  -I --iter     iterations\n");
+	exit(1);
+}
+
+static void parse_opts(int argc, char *argv[])
+{
+	while (1) {
+		static const struct option lopts[] = {
+			{ "device",  1, 0, 'D' },
+			{ "speed",   1, 0, 's' },
+			{ "delay",   1, 0, 'd' },
+			{ "bpw",     1, 0, 'b' },
+			{ "input",   1, 0, 'i' },
+			{ "output",  1, 0, 'o' },
+			{ "loop",    0, 0, 'l' },
+			{ "cpha",    0, 0, 'H' },
+			{ "cpol",    0, 0, 'O' },
+			{ "lsb",     0, 0, 'L' },
+			{ "cs-high", 0, 0, 'C' },
+			{ "3wire",   0, 0, '3' },
+			{ "no-cs",   0, 0, 'N' },
+			{ "ready",   0, 0, 'R' },
+			{ "dual",    0, 0, '2' },
+			{ "verbose", 0, 0, 'v' },
+			{ "quad",    0, 0, '4' },
+			{ "size",    1, 0, 'S' },
+			{ "iter",    1, 0, 'I' },
+			{ NULL, 0, 0, 0 },
+		};
+		int c;
+
+		c = getopt_long(argc, argv, "D:s:d:b:i:o:lHOLC3NR24p:vS:I:",
+				lopts, NULL);
+
+		if (c == -1)
+			break;
+
+		switch (c) {
+		case 'D':
+			device = optarg;
+			break;
+		case 's':
+			speed = atoi(optarg);
+			break;
+		case 'd':
+			delay = atoi(optarg);
+			break;
+		case 'b':
+			bits = atoi(optarg);
+			break;
+		case 'i':
+			input_file = optarg;
+			break;
+		case 'o':
+			output_file = optarg;
+			break;
+		case 'l':
+			mode |= SPI_LOOP;
+			break;
+		case 'H':
+			mode |= SPI_CPHA;
+			break;
+		case 'O':
+			mode |= SPI_CPOL;
+			break;
+		case 'L':
+			mode |= SPI_LSB_FIRST;
+			break;
+		case 'C':
+			mode |= SPI_CS_HIGH;
+			break;
+		case '3':
+			mode |= SPI_3WIRE;
+			break;
+		case 'N':
+			mode |= SPI_NO_CS;
+			break;
+		case 'v':
+			verbose = 1;
+			break;
+		case 'R':
+			mode |= SPI_READY;
+			break;
+		case 'p':
+			input_tx = optarg;
+			break;
+		case '2':
+			mode |= SPI_TX_DUAL;
+			break;
+		case '4':
+			mode |= SPI_TX_QUAD;
+			break;
+		case 'S':
+			transfer_size = atoi(optarg);
+			break;
+		case 'I':
+			iterations = atoi(optarg);
+			break;
+		default:
+			print_usage(argv[0]);
+			break;
+		}
+	}
+	if (mode & SPI_LOOP) {
+		if (mode & SPI_TX_DUAL)
+			mode |= SPI_RX_DUAL;
+		if (mode & SPI_TX_QUAD)
+			mode |= SPI_RX_QUAD;
+	}
+}
+
+static void transfer_escaped_string(int fd, char *str)
+{
+	size_t size = strlen(str);
+	uint8_t *tx;
+	uint8_t *rx;
+
+	tx = malloc(size);
+	if (!tx)
+		pabort("can't allocate tx buffer");
+
+	rx = malloc(size);
+	if (!rx)
+		pabort("can't allocate rx buffer");
+
+	size = unescape((char *)tx, str, size);
+	transfer(fd, tx, rx, size);
+	free(rx);
+	free(tx);
+}
+
+static void transfer_file(int fd, char *filename)
+{
+	ssize_t bytes;
+	struct stat sb;
+	int tx_fd;
+	uint8_t *tx;
+	uint8_t *rx;
+
+	if (stat(filename, &sb) == -1)
+		pabort("can't stat input file");
+
+	tx_fd = open(filename, O_RDONLY);
+	if (tx_fd < 0)
+		pabort("can't open input file");
+
+	tx = malloc(sb.st_size);
+	if (!tx)
+		pabort("can't allocate tx buffer");
+
+	rx = malloc(sb.st_size);
+	if (!rx)
+		pabort("can't allocate rx buffer");
+
+	bytes = read(tx_fd, tx, sb.st_size);
+	if (bytes != sb.st_size)
+		pabort("failed to read input file");
+
+	transfer(fd, tx, rx, sb.st_size);
+	free(rx);
+	free(tx);
+	close(tx_fd);
+}
+
+static uint64_t _read_count;
+static uint64_t _write_count;
+
+static void show_transfer_rate(void)
+{
+	static uint64_t prev_read_count, prev_write_count;
+	double rx_rate, tx_rate;
+
+	rx_rate = ((_read_count - prev_read_count) * 8) / (interval*1000.0);
+	tx_rate = ((_write_count - prev_write_count) * 8) / (interval*1000.0);
+
+	printf("rate: tx %.1fkbps, rx %.1fkbps\n", rx_rate, tx_rate);
+
+	prev_read_count = _read_count;
+	prev_write_count = _write_count;
+}
+
+static void transfer_buf(int fd, int len)
+{
+	uint8_t *tx;
+	uint8_t *rx;
+	int i;
+
+	tx = malloc(len);
+	if (!tx)
+		pabort("can't allocate tx buffer");
+	for (i = 0; i < len; i++)
+		tx[i] = random();
+
+	rx = malloc(len);
+	if (!rx)
+		pabort("can't allocate rx buffer");
+
+	transfer(fd, tx, rx, len);
+
+	_write_count += len;
+	_read_count += len;
+
+	if (mode & SPI_LOOP) {
+		if (memcmp(tx, rx, len)) {
+			fprintf(stderr, "transfer error !\n");
+			hex_dump(tx, len, 32, "TX");
+			hex_dump(rx, len, 32, "RX");
+			exit(1);
+		}
+	}
+
+	free(rx);
+	free(tx);
+}
+
+int main(int argc, char *argv[])
+{
+	int ret = 0;
+	int fd;
+
+	parse_opts(argc, argv);
+
+	fd = open(device, O_RDWR);
+	if (fd < 0)
+		pabort("can't open device");
+
+	/*
+	 * spi mode
+	 */
+	ret = ioctl(fd, SPI_IOC_WR_MODE32, &mode);
+	if (ret == -1)
+		pabort("can't set spi mode");
+
+	ret = ioctl(fd, SPI_IOC_RD_MODE32, &mode);
+	if (ret == -1)
+		pabort("can't get spi mode");
+
+	/*
+	 * bits per word
+	 */
+	ret = ioctl(fd, SPI_IOC_WR_BITS_PER_WORD, &bits);
+	if (ret == -1)
+		pabort("can't set bits per word");
+
+	ret = ioctl(fd, SPI_IOC_RD_BITS_PER_WORD, &bits);
+	if (ret == -1)
+		pabort("can't get bits per word");
+
+	/*
+	 * max speed hz
+	 */
+	ret = ioctl(fd, SPI_IOC_WR_MAX_SPEED_HZ, &speed);
+	if (ret == -1)
+		pabort("can't set max speed hz");
+
+	ret = ioctl(fd, SPI_IOC_RD_MAX_SPEED_HZ, &speed);
+	if (ret == -1)
+		pabort("can't get max speed hz");
+
+	printf("spi mode: 0x%x\n", mode);
+	printf("bits per word: %d\n", bits);
+	printf("max speed: %d Hz (%d KHz)\n", speed, speed/1000);
+
+	if (input_tx && input_file)
+		pabort("only one of -p and --input may be selected");
+
+	if (input_tx)
+		transfer_escaped_string(fd, input_tx);
+	else if (input_file)
+		transfer_file(fd, input_file);
+	else if (transfer_size) {
+		struct timespec last_stat;
+
+		clock_gettime(CLOCK_MONOTONIC, &last_stat);
+
+		while (iterations-- > 0) {
+			struct timespec current;
+
+			transfer_buf(fd, transfer_size);
+
+			clock_gettime(CLOCK_MONOTONIC, &current);
+			if (current.tv_sec - last_stat.tv_sec > interval) {
+				show_transfer_rate();
+				last_stat = current;
+			}
+		}
+		printf("total: tx %.1fKB, rx %.1fKB\n",
+		       _write_count/1024.0, _read_count/1024.0);
+	} else
+		transfer(fd, default_tx, default_rx, sizeof(default_tx));
+
+	close(fd);
+
+	return ret;
+}
diff --git a/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/usage/tsc/README.md b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/usage/tsc/README.md
new file mode 100644
index 0000000000000000000000000000000000000000..dee5639c486db16c50e139d4c76e6e986e74ccfe
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master/usage/tsc/README.md
@@ -0,0 +1,6 @@
+# Touch 
+## Hard Concent
+ynlr -> Y- -> GPIO1_IO1
+ypll -> Y+ -> GPIO1_IO2
+xnur -> X- -> GPIO1_IO3
+xpul -> X+ -. GPIO1_IO4
diff --git a/base_code/linux_driver/dynamic_device_tree/imx-fire-rgb-led-overlay.dts b/base_code/linux_driver/dynamic_device_tree/imx-fire-rgb-led-overlay.dts
new file mode 100644
index 0000000000000000000000000000000000000000..3d8eb8b6b56abf9129003d12a2e03017ccc2861e
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/imx-fire-rgb-led-overlay.dts
@@ -0,0 +1,62 @@
+/*
+ * Copyright (C) 2019 - All Rights Reserved by 
+ * filename : imx-fire-led-overlay.dts
+ * brief : Device Tree overlay for EBF6ull led device
+ * author : embedfire
+ * date : 2019-11-15 
+ * version : A001
+ */
+ /dts-v1/;
+ /plugin/;
+#include "imx6ul-pinfunc.h"
+#include "dt-bindings/gpio/gpio.h"
+ / {
+        fragment@0 {
+            target-path = "/";
+            __overlay__ {
+                rgb_led{
+                	#address-cells = <1>;
+                	#size-cells = <1>;
+                	compatible = "fire,rgb_led";
+                	/*红灯节点*/
+                	ranges;
+                	rgb_led_red@0x020C406C{
+                		compatible = "fire,rgb_led_red";
+                		reg = <0x020C406C 0x00000004
+                		       0x020E006C 0x00000004
+                		       0x020E02F8 0x00000004
+                			   0x0209C000 0x00000004
+                		       0x0209C004 0x00000004>;
+                		status = "okay";
+                	};
+
+
+                	/*绿灯节点*/
+                	rgb_led_green@0x020C4074{
+                		compatible = "fire,rgb_led_green";
+                		reg = <0x020C4074 0x00000004
+                		       0x020E01E0 0x00000004
+                		       0x020E046C 0x00000004
+                			   0x020A8000 0x00000004
+                		       0x020A8004 0x00000004>;
+                		status = "okay";
+                	};
+
+					/*蓝灯节点*/
+                	rgb_led_blue@0x020C4074{
+                		compatible = "fire,rgb_led_blue";
+                		reg = <0x020C4074 0x00000004
+                		       0x020E01DC 0x00000004
+                		       0x020E0468 0x00000004
+                			   0x020A8000 0x00000004
+                		       0x020A8004 0x00000004>;
+                		status = "okay";
+                	};
+                	
+                };
+            };
+        };
+ };
+
+
+
diff --git a/base_code/linux_driver/dynamic_device_tree/overlay_rgb_led/Makefile b/base_code/linux_driver/dynamic_device_tree/overlay_rgb_led/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..9fa8c7664a9c5ff6bf9c0471d46eb8321fa40102
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/overlay_rgb_led/Makefile
@@ -0,0 +1,10 @@
+KERNEL_DIR = /home/new_kernel2/ebf-buster-linux
+
+obj-m := rgb_led.o
+
+all:
+	$(MAKE) -C $(KERNEL_DIR) M=$(CURDIR) modules
+	
+.PHONY:clean
+clean:
+	$(MAKE) -C $(KERNEL_DIR) M=$(CURDIR) clean
diff --git a/base_code/linux_driver/dynamic_device_tree/overlay_rgb_led/rgb_led.c b/base_code/linux_driver/dynamic_device_tree/overlay_rgb_led/rgb_led.c
new file mode 100644
index 0000000000000000000000000000000000000000..86832ccaaeec7b5238f9b5650e924b77c596a26c
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/overlay_rgb_led/rgb_led.c
@@ -0,0 +1,375 @@
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/fs.h>
+#include <linux/cdev.h>
+#include <linux/uaccess.h>
+
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/delay.h>
+#include <linux/ide.h>
+#include <linux/errno.h>
+#include <linux/gpio.h>
+#include <asm/mach/map.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_gpio.h>
+#include <asm/io.h>
+#include <linux/device.h>
+
+#include <linux/platform_device.h>
+
+/*------------------字符设备内容----------------------*/
+#define DEV_NAME "rgb_led"
+#define DEV_CNT (1)
+
+/*定义 led 资源结构体，保存获取得到的节点信息以及转换后的虚拟寄存器地址*/
+struct led_resource
+{
+	struct device_node *device_node; //rgb_led_red的设备树节点
+	void __iomem *virtual_CCM_CCGR;
+	void __iomem *virtual_IOMUXC_SW_MUX_CTL_PAD;
+	void __iomem *virtual_IOMUXC_SW_PAD_CTL_PAD;
+	void __iomem *virtual_DR;
+	void __iomem *virtual_GDIR;
+};
+
+static dev_t led_devno;					 //定义字符设备的设备号
+static struct cdev led_chr_dev;			 //定义字符设备结构体chr_dev
+struct class *class_led;				 //保存创建的类
+struct device *device;					 // 保存创建的设备
+struct device_node *rgb_led_device_node; //rgb_led的设备树节点结构体
+
+/*定义 R G B 三个灯的led_resource 结构体，保存获取得到的节点信息*/
+struct led_resource led_red;
+struct led_resource led_green;
+struct led_resource led_blue;
+
+/*字符设备操作函数集，open函数*/
+static int led_chr_dev_open(struct inode *inode, struct file *filp)
+{
+	printk("\n open form driver \n");
+	return 0;
+}
+
+/*字符设备操作函数集，write函数*/
+static ssize_t led_chr_dev_write(struct file *filp, const char __user *buf, size_t cnt, loff_t *offt)
+{
+
+	unsigned int register_data = 0; //暂存读取得到的寄存器数据
+	unsigned char write_data; //用于保存接收到的数据
+
+	int error = copy_from_user(&write_data, buf, cnt);
+	if (error < 0)
+	{
+		return -1;
+	}
+
+	/*设置 GPIO1_04 输出电平*/
+	if (write_data & 0x04)
+	{
+		register_data = readl(led_red.virtual_DR);
+		register_data &= ~(0x01 << 4);
+		writel(register_data, led_red.virtual_DR); // GPIO1_04引脚输出低电平，红灯亮
+	}
+	else
+	{
+		register_data = readl(led_red.virtual_DR);
+		register_data |= (0x01 << 4);
+		writel(register_data, led_red.virtual_DR); // GPIO1_04引脚输出高电平，红灯灭
+	}
+
+	/*设置 GPIO4_20 输出电平*/
+	if (write_data & 0x02)
+	{
+		register_data = readl(led_green.virtual_DR);
+		register_data &= ~(0x01 << 20);
+		writel(register_data, led_green.virtual_DR); // GPIO4_20引脚输出低电平，绿灯亮
+	}
+	else
+	{
+		register_data = readl(led_green.virtual_DR);
+		register_data |= (0x01 << 20);
+		writel(register_data, led_green.virtual_DR); // GPIO4_20引脚输出高电平，绿灯灭
+	}
+
+	/*设置 GPIO4_19 输出电平*/
+	if (write_data & 0x01)
+	{
+		register_data = readl(led_blue.virtual_DR);
+		register_data &= ~(0x01 << 19);
+		writel(register_data, led_blue.virtual_DR); //GPIO4_19引脚输出低电平，蓝灯亮
+	}
+	else
+	{
+		register_data = readl(led_blue.virtual_DR);
+		register_data |= (0x01 << 19);
+		writel(register_data, led_blue.virtual_DR); //GPIO4_19引脚输出高电平，蓝灯灭
+	}
+
+	return 0;
+}
+
+/*字符设备操作函数集*/
+static struct file_operations led_chr_dev_fops =
+	{
+		.owner = THIS_MODULE,
+		.open = led_chr_dev_open,
+		.write = led_chr_dev_write,
+};
+
+/*----------------平台驱动函数集-----------------*/
+static int led_probe(struct platform_device *pdv)
+{
+
+	int ret = -1; //保存错误状态码
+	unsigned int register_data = 0;
+
+	printk(KERN_EMERG "\t  match successed  \n");
+
+	/*获取rgb_led的设备树节点*/
+	rgb_led_device_node = of_find_node_by_path("/rgb_led");
+	if (rgb_led_device_node == NULL)
+	{
+		printk(KERN_ERR "\t  get rgb_led failed!  \n");
+		return -1;
+	}
+
+	/*获取rgb_led节点的红灯子节点*/
+	led_red.device_node = of_find_node_by_name(rgb_led_device_node,"rgb_led_red");
+	if (led_red.device_node == NULL)
+	{
+		printk(KERN_ERR "\n get rgb_led_red_device_node failed ! \n");
+		return -1;
+	}
+
+
+	/*获取 reg 属性并转化为虚拟地址*/
+	led_red.virtual_CCM_CCGR = of_iomap(led_red.device_node, 0);
+	led_red.virtual_IOMUXC_SW_MUX_CTL_PAD = of_iomap(led_red.device_node, 1);
+	led_red.virtual_IOMUXC_SW_PAD_CTL_PAD = of_iomap(led_red.device_node, 2);
+	led_red.virtual_DR = of_iomap(led_red.device_node, 3);
+	led_red.virtual_GDIR = of_iomap(led_red.device_node, 4);
+
+	/*初始化红灯*/
+	register_data = readl(led_red.virtual_CCM_CCGR);
+	register_data |= (0x03 << 26);
+	writel(register_data, led_red.virtual_CCM_CCGR); //开启时钟
+
+	register_data = readl(led_red.virtual_IOMUXC_SW_MUX_CTL_PAD);
+	register_data &= ~(0xf << 0);
+	register_data |= (0x05 << 0);
+	writel(register_data, led_red.virtual_IOMUXC_SW_MUX_CTL_PAD); //设置复用功能
+
+	register_data = readl(led_red.virtual_IOMUXC_SW_PAD_CTL_PAD);
+	register_data = (0x10B0);
+	writel(register_data, led_red.virtual_IOMUXC_SW_PAD_CTL_PAD); //设置PAD 属性
+
+	register_data = readl(led_red.virtual_GDIR);
+	register_data |= (0x01 << 4);
+	writel(register_data, led_red.virtual_GDIR); //设置GPIO1_04 为输出模式
+
+	register_data = readl(led_red.virtual_DR);
+	register_data |= (0x01 << 4);
+	writel(register_data, led_red.virtual_DR); //设置 GPIO1_04 默认输出高电平
+
+
+
+
+
+
+	/*获取rgb_led节点的绿灯子节点*/
+	led_green.device_node = of_find_node_by_name(rgb_led_device_node,"rgb_led_green");
+	if (led_green.device_node == NULL)
+	{
+		printk(KERN_ERR "\n get rgb_led_green_device_node failed ! \n");
+		return -1;
+	}
+
+	/*获取 reg 属性并转化为虚拟地址*/
+	led_green.virtual_CCM_CCGR = of_iomap(led_green.device_node, 0);
+	led_green.virtual_IOMUXC_SW_MUX_CTL_PAD = of_iomap(led_green.device_node, 1);
+	led_green.virtual_IOMUXC_SW_PAD_CTL_PAD = of_iomap(led_green.device_node, 2);
+	led_green.virtual_DR = of_iomap(led_green.device_node, 3);
+	led_green.virtual_GDIR = of_iomap(led_green.device_node, 4);
+
+	/*初始化绿灯*/
+	register_data = readl(led_green.virtual_CCM_CCGR);
+	register_data |= (0x03 << 12);
+	writel(register_data, led_green.virtual_CCM_CCGR); //开启时钟
+
+	register_data = readl(led_green.virtual_IOMUXC_SW_MUX_CTL_PAD);
+	register_data &= ~(0xf << 0);
+	register_data |= (0x05 << 0);
+	writel(register_data, led_green.virtual_IOMUXC_SW_MUX_CTL_PAD); //设置复用功能
+
+	register_data = readl(led_green.virtual_IOMUXC_SW_PAD_CTL_PAD);
+	register_data = (0x10B0);
+	writel(register_data, led_green.virtual_IOMUXC_SW_PAD_CTL_PAD); //设置PAD 属性
+
+	register_data = readl(led_green.virtual_GDIR);
+	register_data |= (0x01 << 20);
+	writel(register_data, led_green.virtual_GDIR); //设置GPIO4_IO20 为输出模式
+
+	register_data = readl(led_green.virtual_DR);
+	register_data |= (0x01 << 20);
+	writel(register_data, led_green.virtual_DR); //设置 GPIO4_IO20 默认输出高电平
+
+
+
+
+
+
+	/*获取rgb_led节点的蓝灯子节点*/
+	led_blue.device_node = of_find_node_by_name(rgb_led_device_node,"rgb_led_blue");
+	if (led_blue.device_node == NULL)
+	{
+		printk(KERN_ERR "\n get rgb_led_blue_device_node failed ! \n");
+		return -1;
+	}
+
+	/*获取 reg 属性并转化为虚拟地址*/
+	led_blue.virtual_CCM_CCGR = of_iomap(led_blue.device_node, 0);
+	led_blue.virtual_IOMUXC_SW_MUX_CTL_PAD = of_iomap(led_blue.device_node, 1);
+	led_blue.virtual_IOMUXC_SW_PAD_CTL_PAD = of_iomap(led_blue.device_node, 2);
+	led_blue.virtual_DR = of_iomap(led_blue.device_node, 3);
+	led_blue.virtual_GDIR = of_iomap(led_blue.device_node, 4);
+
+	/*初始化蓝灯*/
+	register_data = readl(led_blue.virtual_CCM_CCGR);
+	register_data |= (0x03 << 12);
+	writel(register_data, led_blue.virtual_CCM_CCGR); //开启时钟
+
+	register_data = readl(led_blue.virtual_IOMUXC_SW_MUX_CTL_PAD);
+	register_data &= ~(0xf << 0);
+	register_data |= (0x05 << 0);
+	writel(register_data, led_blue.virtual_IOMUXC_SW_MUX_CTL_PAD); //设置复用功能
+
+	register_data = readl(led_blue.virtual_IOMUXC_SW_PAD_CTL_PAD);
+	register_data = (0x10B0);
+	writel(register_data, led_blue.virtual_IOMUXC_SW_PAD_CTL_PAD); //设置PAD 属性
+
+	register_data = readl(led_blue.virtual_GDIR);
+	register_data |= (0x01 << 19);
+	writel(register_data, led_blue.virtual_GDIR); //设置GPIO4_IO19 为输出模式
+
+	register_data = readl(led_blue.virtual_DR);
+	register_data |= (0x01 << 19);
+	writel(register_data, led_blue.virtual_DR); //设置 GPIO4_IO19 默认输出高电平
+
+
+
+
+
+
+
+
+	/*---------------------注册 字符设备部分-----------------*/
+
+	//第一步
+	//采用动态分配的方式，获取设备编号，次设备号为0，
+	//设备名称为rgb-leds，可通过命令cat  /proc/devices查看
+	//DEV_CNT为1，当前只申请一个设备编号
+	ret = alloc_chrdev_region(&led_devno, 0, DEV_CNT, DEV_NAME);
+	if (ret < 0)
+	{
+		printk("fail to alloc led_devno\n");
+		goto alloc_err;
+	}
+	//第二步
+	//关联字符设备结构体cdev与文件操作结构体file_operations
+	led_chr_dev.owner = THIS_MODULE;
+	cdev_init(&led_chr_dev, &led_chr_dev_fops);
+	//第三步
+	//添加设备至cdev_map散列表中
+	ret = cdev_add(&led_chr_dev, led_devno, DEV_CNT);
+	if (ret < 0)
+	{
+		printk("fail to add cdev\n");
+		goto add_err;
+	}
+
+	//第四步
+	/*创建类 */
+	class_led = class_create(THIS_MODULE, DEV_NAME);
+
+	/*创建设备*/
+	device = device_create(class_led, NULL, led_devno, NULL, DEV_NAME);
+
+	return 0;
+
+add_err:
+	//添加设备失败时，需要注销设备号
+	unregister_chrdev_region(led_devno, DEV_CNT);
+	printk("\n error! \n");
+alloc_err:
+
+	return -1;
+}
+
+static const struct of_device_id rgb_led[] = {
+	{.compatible = "fire,rgb_led"},
+	{/* sentinel */}};
+
+/*定义平台设备结构体*/
+struct platform_driver led_platform_driver = {
+	.probe = led_probe,
+	.driver = {
+		.name = "rgb-leds-platform",
+		.owner = THIS_MODULE,
+		.of_match_table = rgb_led,
+	}};
+
+/*
+*驱动初始化函数
+*/
+static int __init led_platform_driver_init(void)
+{
+	int DriverState;
+	DriverState = platform_driver_register(&led_platform_driver);
+	printk(KERN_EMERG "\tDriverState is %d\n", DriverState);
+	return 0;
+}
+
+/*
+*驱动注销函数
+*/
+static void __exit led_platform_driver_exit(void)
+{
+	/*取消物理地址映射到虚拟地址*/
+	iounmap(led_green.virtual_CCM_CCGR);
+	iounmap(led_green.virtual_IOMUXC_SW_MUX_CTL_PAD);
+	iounmap(led_green.virtual_IOMUXC_SW_PAD_CTL_PAD);
+	iounmap(led_green.virtual_DR);
+	iounmap(led_green.virtual_GDIR);
+
+	iounmap(led_red.virtual_CCM_CCGR);
+	iounmap(led_red.virtual_IOMUXC_SW_MUX_CTL_PAD);
+	iounmap(led_red.virtual_IOMUXC_SW_PAD_CTL_PAD);
+	iounmap(led_red.virtual_DR);
+	iounmap(led_red.virtual_GDIR);
+
+	iounmap(led_blue.virtual_CCM_CCGR);
+	iounmap(led_blue.virtual_IOMUXC_SW_MUX_CTL_PAD);
+	iounmap(led_blue.virtual_IOMUXC_SW_PAD_CTL_PAD);
+	iounmap(led_blue.virtual_DR);
+	iounmap(led_blue.virtual_GDIR);
+
+	/*删除设备*/
+	device_destroy(class_led, led_devno);		  //清除设备
+	class_destroy(class_led);					  //清除类
+	cdev_del(&led_chr_dev);						  //清除设备号
+	unregister_chrdev_region(led_devno, DEV_CNT); //取消注册字符设备
+
+	/*注销字符设备*/
+	platform_driver_unregister(&led_platform_driver);
+
+	printk(KERN_EMERG "HELLO WORLD exit!\n");
+}
+
+module_init(led_platform_driver_init);
+module_exit(led_platform_driver_exit);
+
+MODULE_LICENSE("GPL");
+
+/**/
diff --git a/base_code/linux_driver/dynamic_device_tree/overlay_rgb_led/test_app.c b/base_code/linux_driver/dynamic_device_tree/overlay_rgb_led/test_app.c
new file mode 100644
index 0000000000000000000000000000000000000000..53075daa2b76d56d1120b215bebc71d23cd9864d
--- /dev/null
+++ b/base_code/linux_driver/dynamic_device_tree/overlay_rgb_led/test_app.c
@@ -0,0 +1,45 @@
+#include <stdio.h>
+#include <unistd.h>
+#include <fcntl.h>
+#include <string.h>
+int main(int argc, char *argv[])
+{
+
+    printf("led_tiny test\n");
+    /*判断输入的命令是否合法*/
+    if(argc != 2)
+    {
+        printf(" commend error ! \n");
+        return -1;
+    }
+
+    /*打开文件*/
+    int fd = open("/dev/rgb_led", O_RDWR);
+    if(fd < 0)
+    {
+		printf("open file : %s failed !\n", argv[0]);
+		return -1;
+	}
+
+    unsigned char commend = atoi(argv[1]);  //将受到的命令值转化为数字;
+
+    /*判断命令的有效性*/
+
+    /*写入命令*/
+    int error = write(fd,&commend,sizeof(commend));
+    if(error < 0)
+    {
+        printf("write file error! \n");
+        close(fd);
+        /*判断是否关闭成功*/
+    }
+
+    /*关闭文件*/
+    error = close(fd);
+    if(error < 0)
+    {
+        printf("close file error! \n");
+    }
+    
+    return 0;
+}
\ No newline at end of file
diff --git a/base_code/linux_driver/gpio_subsystem_rgb_led/Makefile b/base_code/linux_driver/gpio_subsystem_rgb_led/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..335331157b0bc98d9720c8f2f620c1dc2efb11cf
--- /dev/null
+++ b/base_code/linux_driver/gpio_subsystem_rgb_led/Makefile
@@ -0,0 +1,10 @@
+KERNEL_DIR = /home/fire2/ebf-buster-linux
+
+obj-m := rgb-leds.o
+
+all:
+	$(MAKE) -C $(KERNEL_DIR) M=$(CURDIR) modules
+	
+.PHONY:clean
+clean:
+	$(MAKE) -C $(KERNEL_DIR) M=$(CURDIR) clean
diff --git a/base_code/linux_driver/gpio_subsystem_rgb_led/rgb-leds.c b/base_code/linux_driver/gpio_subsystem_rgb_led/rgb-leds.c
new file mode 100644
index 0000000000000000000000000000000000000000..82c3980829ebe7bdbe8c82935cca64d859446cf2
--- /dev/null
+++ b/base_code/linux_driver/gpio_subsystem_rgb_led/rgb-leds.c
@@ -0,0 +1,230 @@
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/fs.h>
+#include <linux/cdev.h>
+#include <linux/uaccess.h>
+
+
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/delay.h>
+#include <linux/ide.h>
+#include <linux/errno.h>
+#include <linux/gpio.h>
+#include <asm/mach/map.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_gpio.h>
+#include <asm/io.h>
+#include <linux/device.h>
+
+#include <linux/platform_device.h>
+
+
+
+
+/*------------------字符设备内容----------------------*/
+#define DEV_NAME            "rgb-leds"
+#define DEV_CNT                 (1)
+
+//定义字符设备的设备号
+static dev_t led_devno;
+//定义字符设备结构体chr_dev
+static struct cdev led_chr_dev;
+
+
+struct class *class_led;	//保存创建的类
+struct device *device;	    // 保存创建的设备
+struct device_node	*rgb_led_device_node; //RGB led的设备树节点
+
+int rgb_led_red;			   // 保存获取得到的红灯引脚编号
+int rgb_led_green;			   // 保存获取得到的绿灯引脚编号
+int rgb_led_blue;			   // 保存获取得到的蓝灯引脚编号
+
+
+
+/*字符设备操作函数集，open函数*/
+static int led_chr_dev_open(struct inode *inode, struct file *filp)
+{
+	printk("\n open form driver \n");
+    return 0;
+}
+
+/*字符设备操作函数集，write函数*/
+static ssize_t led_chr_dev_write(struct file *filp, const char __user *buf, size_t cnt, loff_t *offt)
+{
+
+	
+	unsigned char write_data; //用于保存接收到的数据
+
+	int error = copy_from_user(&write_data, buf, cnt);
+	if(error < 0) {
+		return -1;
+	}
+
+    /*设置 GPIO1_04 输出电平*/
+	if(write_data & 0x04)
+	{
+		gpio_direction_output(rgb_led_red, 0);  // GPIO1_04引脚输出低电平，红灯亮
+	}
+	else
+	{
+		gpio_direction_output(rgb_led_red, 1);    // GPIO1_04引脚输出高电平，红灯灭
+	}
+
+
+    /*设置 GPIO4_20 输出电平*/
+	if(write_data & 0x02)
+	{
+		gpio_direction_output(rgb_led_green, 0);  // GPIO4_20引脚输出低电平，绿灯亮
+	}
+	else
+	{
+		gpio_direction_output(rgb_led_green, 1);    // GPIO4_20引脚输出高电平，绿灯灭
+	}
+
+
+    /*设置 GPIO4_19 输出电平*/
+	if(write_data & 0x01)
+	{
+		gpio_direction_output(rgb_led_blue, 0);  // GPIO4_19引脚输出低电平，蓝灯亮
+	}
+	else
+	{
+		gpio_direction_output(rgb_led_blue, 1);    // GPIO4_19引脚输出高电平，蓝灯灭
+	}
+
+	return 0;
+}
+
+
+/*字符设备操作函数集*/
+static struct file_operations  led_chr_dev_fops = 
+{
+	.owner = THIS_MODULE,
+    .open = led_chr_dev_open,
+	.write = led_chr_dev_write,
+};
+
+
+
+/*----------------平台驱动函数集-----------------*/
+static int led_probe(struct platform_device *pdv)
+{
+	
+	int ret = 0;  //用于保存申请设备号的结果
+    
+	printk(KERN_EMERG "\t  match successed  \n");
+
+    /*获取RGB的设备树节点*/
+    rgb_led_device_node = of_find_node_by_path("/rgb_led");
+    if(rgb_led_device_node == NULL)
+    {
+        printk(KERN_EMERG "\t  get rgb_led failed!  \n");
+    }
+
+    rgb_led_red = of_get_named_gpio(rgb_led_device_node, "rgb_led_red", 0);
+    rgb_led_green = of_get_named_gpio(rgb_led_device_node, "rgb_led_green", 0);
+    rgb_led_blue = of_get_named_gpio(rgb_led_device_node, "rgb_led_blue", 0);
+
+    printk("rgb_led_red = %d,\n rgb_led_green = %d,\n rgb_led_blue = %d,\n", rgb_led_red,\
+    rgb_led_green,rgb_led_blue);
+
+    gpio_direction_output(rgb_led_red, 1);
+    gpio_direction_output(rgb_led_green, 1);
+    gpio_direction_output(rgb_led_blue, 1);
+
+
+	/*---------------------注册 字符设备部分-----------------*/
+
+	//第一步
+    //采用动态分配的方式，获取设备编号，次设备号为0，
+    //设备名称为rgb-leds，可通过命令cat  /proc/devices查看
+    //DEV_CNT为1，当前只申请一个设备编号
+    ret = alloc_chrdev_region(&led_devno, 0, DEV_CNT, DEV_NAME);
+    if(ret < 0){
+        printk("fail to alloc led_devno\n");
+        goto alloc_err;
+    }
+    //第二步
+    //关联字符设备结构体cdev与文件操作结构体file_operations
+	led_chr_dev.owner = THIS_MODULE;
+    cdev_init(&led_chr_dev, &led_chr_dev_fops);
+    //第三步
+    //添加设备至cdev_map散列表中
+    ret = cdev_add(&led_chr_dev, led_devno, DEV_CNT);
+    if(ret < 0)
+    {
+        printk("fail to add cdev\n");
+        goto add_err;
+    }
+
+	//第四步
+	/*创建类 */
+	class_led = class_create(THIS_MODULE, DEV_NAME);
+
+	/*创建设备*/
+	device = device_create(class_led, NULL, led_devno, NULL, DEV_NAME);
+
+	return 0;
+
+add_err:
+    //添加设备失败时，需要注销设备号
+    unregister_chrdev_region(led_devno, DEV_CNT);
+	printk("\n error! \n");
+alloc_err:
+
+	return -1;
+
+}
+
+
+
+
+static const struct of_device_id rgb_led[] = {
+{ .compatible = "fire,rgb-led"},
+  { /* sentinel */ }
+};
+
+/*定义平台设备结构体*/
+struct platform_driver led_platform_driver = {
+	.probe = led_probe,
+	.driver = {
+		.name = "rgb-leds-platform",
+		.owner = THIS_MODULE,
+		.of_match_table = rgb_led,
+	}
+};
+
+
+
+/*
+*驱动初始化函数
+*/
+static int __init led_platform_driver_init(void)
+{
+	int DriverState;
+	
+	DriverState = platform_driver_register(&led_platform_driver);
+	
+	printk(KERN_EMERG "\tDriverState is %d\n",DriverState);
+	return 0;
+}
+
+
+/*
+*驱动注销函数
+*/
+static void __exit led_platform_driver_exit(void)
+{
+	printk(KERN_EMERG "HELLO WORLD exit!\n");
+	
+	platform_driver_unregister(&led_platform_driver);	
+}
+
+
+module_init(led_platform_driver_init);
+module_exit(led_platform_driver_exit);
+
+MODULE_LICENSE("GPL");
+
diff --git a/base_code/linux_driver/gpio_subsystem_rgb_led/rgb_leds_app.c b/base_code/linux_driver/gpio_subsystem_rgb_led/rgb_leds_app.c
new file mode 100644
index 0000000000000000000000000000000000000000..9aca9a7b33d48e829d3664420721db5ac568d7a7
--- /dev/null
+++ b/base_code/linux_driver/gpio_subsystem_rgb_led/rgb_leds_app.c
@@ -0,0 +1,45 @@
+#include <stdio.h>
+#include <unistd.h>
+#include <fcntl.h>
+#include <string.h>
+int main(int argc, char *argv[])
+{
+
+    printf("led_tiny test\n");
+    /*判断输入的命令是否合法*/
+    if(argc != 2)
+    {
+        printf(" commend error ! \n");
+        return -1;
+    }
+
+    /*打开文件*/
+    int fd = open("/dev/rgb-leds", O_RDWR);
+    if(fd < 0)
+    {
+		printf("open file : %s failed !\n", argv[0]);
+		return -1;
+	}
+
+    unsigned char commend = atoi(argv[1]);  //将受到的命令值转化为数字;
+
+    /*判断命令的有效性*/
+
+    /*写入命令*/
+    int error = write(fd,&commend,sizeof(commend));
+    if(error < 0)
+    {
+        printf("write file error! \n");
+        close(fd);
+        /*判断是否关闭成功*/
+    }
+
+    /*关闭文件*/
+    error = close(fd);
+    if(error < 0)
+    {
+        printf("close file error! \n");
+    }
+    
+    return 0;
+}
\ No newline at end of file
diff --git a/base_code/linux_driver/hello_world/Makefile b/base_code/linux_driver/hello_world/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..ad7b31b3bd3607500bb4057548ef0bf97eca9aa7
--- /dev/null
+++ b/base_code/linux_driver/hello_world/Makefile
@@ -0,0 +1,6 @@
+KERNEL_DIR=/home/embedfire/module/linux-imx
+obj-m := hello_world.o
+all:
+	$(MAKE) -C $(KERNEL_DIR) M=$(CURDIR) modules
+clean:
+	$(MAKE) -C $(KERNEL_DIR) M=$(CURDIR) clean	
diff --git a/base_code/linux_driver/hello_world/hello_world.c b/base_code/linux_driver/hello_world/hello_world.c
new file mode 100644
index 0000000000000000000000000000000000000000..23fce5ee183134afae78acfe95faf03dee56bb06
--- /dev/null
+++ b/base_code/linux_driver/hello_world/hello_world.c
@@ -0,0 +1,31 @@
+#include <linux/init.h>
+#include <linux/module.h>
+
+//默认不输出调试信息
+//权限有限制
+bool debug_on = 0;
+module_param(debug_on, bool, S_IRUSR);
+
+
+static int __init hello_init(void)
+{
+    if(debug_on)
+        printk(KERN_ERR "[ DEBUG ] debug info output\n");
+    printk("Hello World Module Init\n");
+    return 0;
+}
+module_init(hello_init);
+
+
+static void __exit hello_exit(void)
+{
+    printk("Hello World Module Exit\n");
+}
+module_exit(hello_exit);
+
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("embedfire");
+MODULE_DESCRIPTION("hello world module");
+MODULE_ALIAS("test_module");
+
diff --git a/base_code/linux_driver/hello_world/helloworld.ko b/base_code/linux_driver/hello_world/helloworld.ko
new file mode 100644
index 0000000000000000000000000000000000000000..1fd880c9f505686a6ce1e19a7f3df5bc5550bb8e
Binary files /dev/null and b/base_code/linux_driver/hello_world/helloworld.ko differ
diff --git a/base_code/linux_driver/led_cdev/Makefile b/base_code/linux_driver/led_cdev/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..b1fe0e28a7969d061a6f8355cf96101ae844787f
--- /dev/null
+++ b/base_code/linux_driver/led_cdev/Makefile
@@ -0,0 +1,16 @@
+
+obj-m := led_cdev.o
+
+
+NATIVE ?= true
+
+
+ifeq ($(NATIVE), false)
+	KERNEL_DIR = /home/embedfire/linux4.19
+else
+	KERNEL_DIR = /lib/modules/$(shell uname -r)/build
+endif
+
+all:modules
+modules clean:
+	$(MAKE) -C $(KERNEL_DIR) M=$(shell pwd) $@
diff --git a/base_code/linux_driver/led_cdev/led_cdev.c b/base_code/linux_driver/led_cdev/led_cdev.c
new file mode 100644
index 0000000000000000000000000000000000000000..a4a92d6e4fa7c5b2a45ac18bc3a1bcd7d836a1d9
--- /dev/null
+++ b/base_code/linux_driver/led_cdev/led_cdev.c
@@ -0,0 +1,174 @@
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/cdev.h>
+#include <linux/fs.h>
+#include <linux/uaccess.h>
+#include <linux/io.h>
+
+#define DEV_NAME            "led_chrdev"
+#define DEV_CNT                 (3)
+
+static dev_t devno;
+struct class *led_chrdev_class;
+
+struct led_chrdev {
+	struct cdev dev;
+	unsigned int __iomem *va_dr;
+	unsigned int __iomem *va_gdir;
+	unsigned int __iomem *va_iomuxc_mux;
+	unsigned int __iomem *va_ccm_ccgrx;
+	unsigned int __iomem *va_iomux_pad;
+
+	unsigned long pa_dr;
+	unsigned long pa_gdir;
+	unsigned long pa_iomuxc_mux;
+	unsigned long pa_ccm_ccgrx;
+	unsigned long pa_iomux_pad;
+
+	unsigned int led_pin;
+	unsigned int clock_offset;
+};
+
+static int led_chrdev_open(struct inode *inode, struct file *filp)
+{
+
+	unsigned int val = 0;
+	struct led_chrdev *led_cdev =
+	    (struct led_chrdev *)container_of(inode->i_cdev, struct led_chrdev,
+					      dev);
+	filp->private_data =
+	    container_of(inode->i_cdev, struct led_chrdev, dev);
+
+	printk("open\n");
+
+	led_cdev->va_dr = ioremap(led_cdev->pa_dr, 4);
+	led_cdev->va_gdir = ioremap(led_cdev->pa_gdir, 4);
+	led_cdev->va_iomuxc_mux = ioremap(led_cdev->pa_iomuxc_mux, 4);
+	led_cdev->va_ccm_ccgrx = ioremap(led_cdev->pa_ccm_ccgrx, 4);
+	led_cdev->va_iomux_pad = ioremap(led_cdev->pa_iomux_pad, 4);
+
+	val = ioread32(led_cdev->va_ccm_ccgrx);
+	val &= ~(3 << led_cdev->clock_offset);
+	val |= (3 << led_cdev->clock_offset);
+	iowrite32(val, led_cdev->va_ccm_ccgrx);
+
+	iowrite32(5, led_cdev->va_iomuxc_mux);
+
+	iowrite32(0x1F838, led_cdev->va_iomux_pad);
+
+	val = ioread32(led_cdev->va_gdir);
+	val &= ~(1 << led_cdev->led_pin);
+	val |= (1 << led_cdev->led_pin);
+	iowrite32(val, led_cdev->va_gdir);
+
+	val = ioread32(led_cdev->va_dr);
+	val |= (0x01 << led_cdev->led_pin);
+	iowrite32(val, led_cdev->va_dr);
+
+	return 0;
+}
+
+static int led_chrdev_release(struct inode *inode, struct file *filp)
+{
+	struct led_chrdev *led_cdev =
+	    (struct led_chrdev *)container_of(inode->i_cdev, struct led_chrdev,
+					      dev);
+	iounmap(led_cdev->va_dr);
+	iounmap(led_cdev->va_gdir);
+	iounmap(led_cdev->va_iomuxc_mux);
+	iounmap(led_cdev->va_ccm_ccgrx);
+	iounmap(led_cdev->va_iomux_pad);
+	return 0;
+}
+
+static ssize_t led_chrdev_write(struct file *filp, const char __user * buf,
+				size_t count, loff_t * ppos)
+{
+	unsigned long val = 0;
+	unsigned long ret = 0;
+
+	int tmp = count;
+
+	kstrtoul_from_user(buf, tmp, 10, &ret);
+	struct led_chrdev *led_cdev = (struct led_chrdev *)filp->private_data;
+
+	val = ioread32(led_cdev->va_dr);
+	if (ret == 0)
+		val &= ~(0x01 << led_cdev->led_pin);
+	else
+		val |= (0x01 << led_cdev->led_pin);
+
+	iowrite32(val, led_cdev->va_dr);
+	*ppos += tmp;
+	return tmp;
+}
+
+static struct file_operations led_chrdev_fops = {
+	.owner = THIS_MODULE,
+	.open = led_chrdev_open,
+	.release = led_chrdev_release,
+	.write = led_chrdev_write,
+};
+
+static struct led_chrdev led_cdev[DEV_CNT] = {
+	{.pa_dr = 0x0209C000,.pa_gdir = 0x0209C004,.pa_iomuxc_mux =
+	 0x20E006C,.pa_ccm_ccgrx = 0x20C406C,.pa_iomux_pad =
+	 0x20E02F8,.led_pin = 4,.clock_offset = 26},
+	{.pa_dr = 0x20A8000,.pa_gdir = 0x20A8004,.pa_iomuxc_mux =
+	 0x20E01E0,.pa_ccm_ccgrx = 0x20C4074,.pa_iomux_pad =
+	 0x20E046C,.led_pin = 20,.clock_offset = 12},
+	{.pa_dr = 0x20A8000,.pa_gdir = 0x20A8004,.pa_iomuxc_mux =
+	 0x20E01DC,.pa_ccm_ccgrx = 0x20C4074,.pa_iomux_pad =
+	 0x20E0468,.led_pin = 19,.clock_offset = 12},
+};
+
+static __init int led_chrdev_init(void)
+{
+	int i = 0;
+	dev_t cur_dev;
+	printk("led chrdev init\n");
+
+	alloc_chrdev_region(&devno, 0, DEV_CNT, DEV_NAME);
+
+	led_chrdev_class = class_create(THIS_MODULE, "led_chrdev");
+
+	for (; i < DEV_CNT; i++) {
+		cdev_init(&led_cdev[i].dev, &led_chrdev_fops);
+		led_cdev[i].dev.owner = THIS_MODULE;
+
+		cur_dev = MKDEV(MAJOR(devno), MINOR(devno) + i);
+
+		cdev_add(&led_cdev[i].dev, cur_dev, 1);
+
+		device_create(led_chrdev_class, NULL, cur_dev, NULL,
+			      DEV_NAME "%d", i);
+	}
+
+	return 0;
+}
+
+module_init(led_chrdev_init);
+
+static __exit void led_chrdev_exit(void)
+{
+	int i;
+	dev_t cur_dev;
+	printk("led chrdev exit\n");
+
+	for (i = 0; i < DEV_CNT; i++) {
+		cur_dev = MKDEV(MAJOR(devno), MINOR(devno) + i);
+
+		device_destroy(led_chrdev_class, cur_dev);
+
+		cdev_del(&led_cdev[i].dev);
+
+	}
+	unregister_chrdev_region(devno, DEV_CNT);
+	class_destroy(led_chrdev_class);
+
+}
+
+module_exit(led_chrdev_exit);
+
+MODULE_AUTHOR("embedfire");
+MODULE_LICENSE("GPL");
diff --git a/base_code/linux_driver/linux_device_model/Makefile b/base_code/linux_driver/linux_device_model/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..2aec56af906848ed17e580c7aecb1cc61b61232b
--- /dev/null
+++ b/base_code/linux_driver/linux_device_model/Makefile
@@ -0,0 +1,18 @@
+
+NATIVE ?= true
+
+
+ifeq ($(NATIVE), false)
+	KERNEL_DIR = /home/embedfire/linux4.19
+else
+	KERNEL_DIR = /lib/modules/$(shell uname -r)/build
+endif
+
+
+
+
+obj-m := xdev.o xbus.o xdrv.o
+
+all:modules
+modules clean:
+	$(MAKE) -C $(KERNEL_DIR) M=$(shell pwd) $@
diff --git a/base_code/linux_driver/linux_device_model/xbus.c b/base_code/linux_driver/linux_device_model/xbus.c
new file mode 100644
index 0000000000000000000000000000000000000000..75ce6642b9c1063d426ab9b4c1bb61c702ef2aa7
--- /dev/null
+++ b/base_code/linux_driver/linux_device_model/xbus.c
@@ -0,0 +1,55 @@
+#include <linux/init.h>
+#include <linux/module.h>
+
+#include <linux/device.h>
+
+int xbus_match(struct device *dev, struct device_driver *drv)
+{
+
+	printk("%s-%s\n", __FILE__, __func__);
+	if (!strncmp(dev_name(dev), drv->name, strlen(drv->name))) {
+		printk("dev & drv match\n");
+		return 1;
+	}
+	return 0;
+
+}
+
+static char *bus_name = "xbus";
+
+ssize_t xbus_test_show(struct bus_type *bus, char *buf)
+{
+	return sprintf(buf, "%s\n", bus_name);
+}
+
+BUS_ATTR(xbus_test, S_IRUSR, xbus_test_show, NULL);
+
+static struct bus_type xbus = {
+	.name = "xbus",
+	.match = xbus_match,
+};
+
+EXPORT_SYMBOL(xbus);
+
+static __init int xbus_init(void)
+{
+	printk("xbus init\n");
+
+	bus_register(&xbus);
+	bus_create_file(&xbus, &bus_attr_xbus_test);
+	return 0;
+}
+
+module_init(xbus_init);
+
+static __exit void xbus_exit(void)
+{
+	printk("xbus exit\n");
+	bus_remove_file(&xbus, &bus_attr_xbus_test);
+	bus_unregister(&xbus);
+}
+
+module_exit(xbus_exit);
+
+MODULE_AUTHOR("embedfire");
+MODULE_LICENSE("GPL");
diff --git a/base_code/linux_driver/linux_device_model/xdev.c b/base_code/linux_driver/linux_device_model/xdev.c
new file mode 100644
index 0000000000000000000000000000000000000000..1ab33b3b56d17386b56121d7e7c0e8f73e9965f1
--- /dev/null
+++ b/base_code/linux_driver/linux_device_model/xdev.c
@@ -0,0 +1,54 @@
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/device.h>
+
+extern struct bus_type xbus;
+
+void xdev_release(struct device *dev)
+{
+	printk("%s-%s\n", __FILE__, __func__);
+}
+
+unsigned long id = 0;
+ssize_t xdev_id_show(struct device *dev, struct device_attribute *attr,
+		     char *buf)
+{
+	return sprintf(buf, "%d\n", id);
+}
+
+ssize_t xdev_id_store(struct device * dev, struct device_attribute * attr,
+		      const char *buf, size_t count)
+{
+	kstrtoul(buf, 10, &id);
+	return count;
+}
+
+DEVICE_ATTR(xdev_id, S_IRUSR | S_IWUSR, xdev_id_show, xdev_id_store);
+
+static struct device xdev = {
+	.init_name = "xdev",
+	.bus = &xbus,
+	.release = xdev_release,
+};
+
+static __init int xdev_init(void)
+{
+	printk("xdev init\n");
+	device_register(&xdev);
+	device_create_file(&xdev, &dev_attr_xdev_id);
+	return 0;
+}
+
+module_init(xdev_init);
+
+static __exit void xdev_exit(void)
+{
+	printk("xdev exit\n");
+	device_remove_file(&xdev, &dev_attr_xdev_id);
+	device_unregister(&xdev);
+}
+
+module_exit(xdev_exit);
+
+MODULE_AUTHOR("embedfire");
+MODULE_LICENSE("GPL");
diff --git a/base_code/linux_driver/linux_device_model/xdrv.c b/base_code/linux_driver/linux_device_model/xdrv.c
new file mode 100644
index 0000000000000000000000000000000000000000..1c449a1e6d8f83c64b931326b838dbed288f16b1
--- /dev/null
+++ b/base_code/linux_driver/linux_device_model/xdrv.c
@@ -0,0 +1,56 @@
+#include <linux/init.h>
+#include <linux/module.h>
+
+#include <linux/device.h>
+
+extern struct bus_type xbus;
+
+char *name = "xdrv";
+
+ssize_t drvname_show(struct device_driver *drv, char *buf)
+{
+	return sprintf(buf, "%s\n", name);
+}
+
+DRIVER_ATTR_RO(drvname);
+
+int xdrv_probe(struct device *dev)
+{
+	printk("%s-%s\n", __FILE__, __func__);
+	return 0;
+}
+
+int xdrv_remove(struct device *dev)
+{
+	printk("%s-%s\n", __FILE__, __func__);
+	return 0;
+}
+
+static struct device_driver xdrv = {
+	.name = "xdev",
+	.bus = &xbus,
+	.probe = xdrv_probe,
+	.remove = xdrv_remove,
+};
+
+static __init int xdrv_init(void)
+{
+	printk("xdrv init\n");
+	driver_register(&xdrv);
+	driver_create_file(&xdrv, &driver_attr_drvname);
+	return 0;
+}
+
+module_init(xdrv_init);
+
+static __exit void xdrv_exit(void)
+{
+	printk("xdrv exit\n");
+	driver_remove_file(&xdrv, &driver_attr_drvname);
+	driver_unregister(&xdrv);
+}
+
+module_exit(xdrv_exit);
+
+MODULE_AUTHOR("embedfire");
+MODULE_LICENSE("GPL");
diff --git a/base_code/linux_driver/of_function_test/imx6ull-seeed-npi.dts b/base_code/linux_driver/of_function_test/imx6ull-seeed-npi.dts
new file mode 100644
index 0000000000000000000000000000000000000000..76fa2e0f650df99d63969c2adf24f8314cd49d01
--- /dev/null
+++ b/base_code/linux_driver/of_function_test/imx6ull-seeed-npi.dts
@@ -0,0 +1,420 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/input/input.h>
+#include "imx6ull.dtsi"
+
+/ {
+	model = "Seeed i.MX6 ULL NPi Board";
+	compatible = "fsl,imx6ull-14x14-evk", "fsl,imx6ull";
+
+	aliases {
+		pwm0 = &pwm1;
+		pwm1 = &pwm2;
+		pwm2 = &pwm3;
+		pwm3 = &pwm4;
+	};
+
+	chosen {
+		stdout-path = &uart1;
+	};
+
+	memory {
+		reg = <0x80000000 0x20000000>;
+	};
+
+	reserved-memory {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		linux,cma {
+			compatible = "shared-dma-pool";
+			reusable;
+			size = <0x14000000>;
+			linux,cma-default;
+		};
+	};
+
+	regulators {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+
+		reg_sd1_vmmc: regulator@1 {
+			compatible = "regulator-fixed";
+			regulator-name = "VSD_3V3";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+			gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
+			off-on-delay = <20000>;
+			enable-active-high;
+		};
+
+		reg_gpio_dvfs: regulator-gpio {
+			compatible = "regulator-gpio";
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_dvfs>;
+			regulator-min-microvolt = <1300000>;
+			regulator-max-microvolt = <1400000>;
+			regulator-name = "gpio_dvfs";
+			regulator-type = "voltage";
+			gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>;
+			states = <1300000 0x1 1400000 0x0>;
+		};
+	};
+
+    /* External sound card */
+    sound: sound {
+        status = "disabled";
+    };
+
+	/*添加led节点*/
+	led{
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		rgb_led_red@0x0209C000{
+			compatible = "fire,rgb_led_red";
+			reg = <0x0209C000 0x00000020>;
+			status = "okay";
+		};
+	};
+};
+
+
+
+
+&cpu0 {
+	dc-supply = <&reg_gpio_dvfs>;
+	clock-frequency = <800000000>;
+};
+
+&clks {
+	assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
+	assigned-clock-rates = <786432000>;
+};
+
+
+&fec1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_enet1>;
+	phy-mode = "rmii";
+	phy-handle = <&ethphy0>;
+	status = "okay";
+};
+
+&fec2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_enet2>;
+	phy-mode = "rmii";
+	phy-handle = <&ethphy1>;
+	status = "okay";
+
+	mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ethphy0: ethernet-phy@2 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <2>;
+			micrel,led-mode = <1>;
+			clocks = <&clks IMX6UL_CLK_ENET_REF>;
+			clock-names = "rmii-ref";
+		};
+
+		ethphy1: ethernet-phy@1 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <1>;
+			micrel,led-mode = <1>;
+			clocks = <&clks IMX6UL_CLK_ENET2_REF>;
+			clock-names = "rmii-ref";
+		};
+	};
+};
+
+
+&gpc {
+	fsl,cpu_pupscr_sw2iso = <0xf>;
+	fsl,cpu_pupscr_sw = <0x0>;
+	fsl,cpu_pdnscr_iso2sw = <0x1>;
+	fsl,cpu_pdnscr_iso = <0x1>;
+	fsl,ldo-bypass = <0>; /* DCDC, ldo-enable */
+};
+
+
+&iomuxc {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_hog_1>;
+
+	pinctrl_rgb_led:rgb_led{
+			fsl,pins = <
+				MX6UL_PAD_GPIO1_IO04__GPIO1_IO04	0x000010B1 /* remote control   add by pan  20200307*/
+				MX6UL_PAD_CSI_HSYNC__GPIO4_IO20	    0x000010B1 /* remote control   add by pan  20200307*/
+				MX6UL_PAD_CSI_VSYNC__GPIO4_IO19	    0x000010B1 /* remote control   add by pan  20200307*/
+			>;
+		};
+
+	pinctrl_gpmi_nand: gpmi-nand {
+			fsl,pins = <
+				MX6UL_PAD_NAND_CLE__RAWNAND_CLE         0xb0b1
+				MX6UL_PAD_NAND_ALE__RAWNAND_ALE         0xb0b1
+				MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B       0xb0b1
+				MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0xb000
+				MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B     0xb0b1
+				MX6UL_PAD_NAND_CE1_B__RAWNAND_CE1_B     0xb0b1
+				MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B       0xb0b1
+				MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B       0xb0b1
+				MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00   0xb0b1
+				MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01   0xb0b1
+				MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02   0xb0b1
+				MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03   0xb0b1
+				MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04   0xb0b1
+				MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05   0xb0b1
+				MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06   0xb0b1
+				MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07   0xb0b1
+			>;
+		};
+
+	pinctrl_hog_1: hoggrp-1 {
+		fsl,pins = <
+			MX6UL_PAD_UART1_RTS_B__GPIO1_IO19	0x17059 /* SD1 CD */
+			MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT	0x17059 /* SD1 VSELECT */
+			MX6UL_PAD_GPIO1_IO09__GPIO1_IO09        0x17059 /* SD1 RESET */
+		>;
+	};
+
+	pinctrl_enet1: enet1grp {
+		fsl,pins = <
+			MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN	0x1b0b0
+			MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER	0x1b0b0
+			MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00	0x1b0b0
+			MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01	0x1b0b0
+			MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN	0x1b0b0
+			MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00	0x1b0b0
+			MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01	0x1b0b0
+			MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1	0x4001b031
+		>;
+	};
+
+	pinctrl_enet2: enet2grp {
+		fsl,pins = <
+			MX6UL_PAD_GPIO1_IO07__ENET2_MDC		0x1b0b0
+			MX6UL_PAD_GPIO1_IO06__ENET2_MDIO	0x1b0b0
+			MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN	0x1b0b0
+			MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER	0x1b0b0
+			MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00	0x1b0b0
+			MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01	0x1b0b0
+			MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN	0x1b0b0
+			MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00	0x1b0b0
+			MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01	0x1b0b0
+			MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2	0x4001b031
+		>;
+	};
+
+	pinctrl_uart1: uart1grp {
+		fsl,pins = <
+			MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
+			MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
+		>;
+	};
+
+
+	pinctrl_usb_otg1_id: usbotg1idgrp {
+		fsl,pins = <
+			MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID	0x17059
+		>;
+	};
+
+        pinctrl_dvfs: dvfsgrp {
+                fsl,pins = <
+                        MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03      0x79
+                >;
+        };
+
+	pinctrl_usdhc1: usdhc1grp {
+		fsl,pins = <
+			MX6UL_PAD_SD1_CMD__USDHC1_CMD     0x17059
+			MX6UL_PAD_SD1_CLK__USDHC1_CLK     0x10071
+			MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
+			MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
+			MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
+			MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
+		>;
+	};
+
+	pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
+		fsl,pins = <
+			MX6UL_PAD_SD1_CMD__USDHC1_CMD     0x170b9
+			MX6UL_PAD_SD1_CLK__USDHC1_CLK     0x100b9
+			MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
+			MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
+			MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
+			MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9
+		>;
+	};
+
+	pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
+		fsl,pins = <
+			MX6UL_PAD_SD1_CMD__USDHC1_CMD     0x170f9
+			MX6UL_PAD_SD1_CLK__USDHC1_CLK     0x100f9
+			MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9
+			MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9
+			MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9
+			MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9
+		>;
+	};
+
+	pinctrl_usdhc2: usdhc2grp {
+		fsl,pins = <
+			MX6UL_PAD_NAND_RE_B__USDHC2_CLK     0x10069
+			MX6UL_PAD_NAND_WE_B__USDHC2_CMD     0x17059
+			MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
+			MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
+			MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
+			MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
+		>;
+	};
+
+	pinctrl_usdhc2_8bit: usdhc2grp_8bit {
+		fsl,pins = <
+			MX6UL_PAD_NAND_RE_B__USDHC2_CLK     0x10069
+			MX6UL_PAD_NAND_WE_B__USDHC2_CMD     0x17059
+			MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
+			MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
+			MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
+			MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
+			MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17059
+			MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17059
+			MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17059
+			MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17059
+		>;
+	};
+
+	pinctrl_usdhc2_8bit_100mhz: usdhc2grp_8bit_100mhz {
+		fsl,pins = <
+			MX6UL_PAD_NAND_RE_B__USDHC2_CLK     0x100b9
+			MX6UL_PAD_NAND_WE_B__USDHC2_CMD     0x170b9
+			MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170b9
+			MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170b9
+			MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170b9
+			MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170b9
+			MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170b9
+			MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170b9
+			MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170b9
+			MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170b9
+		>;
+	};
+
+	pinctrl_usdhc2_8bit_200mhz: usdhc2grp_8bit_200mhz {
+		fsl,pins = <
+			MX6UL_PAD_NAND_RE_B__USDHC2_CLK     0x100f9
+			MX6UL_PAD_NAND_WE_B__USDHC2_CMD     0x170f9
+			MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9
+			MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9
+			MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9
+			MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9
+			MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170f9
+			MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170f9
+			MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170f9
+			MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170f9
+		>;
+	};
+
+};
+
+&iomuxc_snvs {
+	pinctrl-names = "default_snvs";
+	pinctrl-0 = <&pinctrl_hog_2>;
+	pinctrl_hog_2: hoggrp-2 {
+		fsl,pins = <
+			MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00      0x80000000
+		>;
+	};
+};
+
+
+&snvs_pwrkey {
+	status = "disabled";
+};
+
+&pxp {
+	status = "okay";
+};
+
+
+&uart1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart1>;
+	status = "okay";
+};
+
+
+&usbotg1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usb_otg1_id>;
+	dr_mode = "otg";
+	srp-disable;
+	hnp-disable;
+	adp-disable;
+	status = "okay";
+};
+
+&usbotg2 {
+	dr_mode = "host";
+	disable-over-current;
+	status = "okay";
+};
+
+&usbphy1 {
+	fsl,tx-d-cal = <106>;
+};
+
+&usbphy2 {
+	fsl,tx-d-cal = <106>;
+};
+
+&usdhc1 {
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc1>;
+	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
+	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
+	no-1-8-v;
+	/*cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;*/
+	keep-power-in-suspend;
+	/*non-removable;*/
+	enable-sdio-wakeup;
+	vmmc-supply = <&reg_sd1_vmmc>;
+	status = "okay";
+};
+
+&usdhc2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usdhc2_8bit>;
+	non-removable;
+	status = "okay";
+};
+
+&gpmi {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_gpmi_nand>;
+	status = "okay";
+	//nand-on-flash-bbt;
+
+	partition@0 {
+			label = "uboot";
+			reg = <0x00000000 0x00800000>;
+		};
+		partition@1 {
+			label = "rootfs";
+			reg = <0x00800000 0x1F800000>;
+		};
+};
diff --git a/base_code/linux_driver/of_function_test/of_function/Makefile b/base_code/linux_driver/of_function_test/of_function/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..ca96200a4d9d24281b90d5448ed1f06ec955bd67
--- /dev/null
+++ b/base_code/linux_driver/of_function_test/of_function/Makefile
@@ -0,0 +1,10 @@
+KERNEL_DIR = /home/fire2/ebf-buster-linux
+
+obj-m := of_function_test.o
+
+all:
+	$(MAKE) -C $(KERNEL_DIR) M=$(CURDIR) modules
+	
+.PHONY:clean
+clean:
+	$(MAKE) -C $(KERNEL_DIR) M=$(CURDIR) clean
diff --git a/base_code/linux_driver/of_function_test/of_function/app_test.c b/base_code/linux_driver/of_function_test/of_function/app_test.c
new file mode 100644
index 0000000000000000000000000000000000000000..332a81f41c447add1679ba8d569e14e9c4cf2697
--- /dev/null
+++ b/base_code/linux_driver/of_function_test/of_function/app_test.c
@@ -0,0 +1,16 @@
+#include <stdio.h>
+#include <unistd.h>
+#include <fcntl.h>
+#include <string.h>
+int main(void)
+{
+    printf("led_tiny test\n");
+ 
+    //打开文件
+    int fd = open("/dev/of_test", O_RDWR);
+
+    //关闭文件
+    close(fd);
+    printf("tiny led test finished !\n");
+    return 0;
+}
\ No newline at end of file
diff --git a/base_code/linux_driver/of_function_test/of_function/of_function_test.c b/base_code/linux_driver/of_function_test/of_function/of_function_test.c
new file mode 100644
index 0000000000000000000000000000000000000000..587cfc61ca444bdfeb1722c50fc696bda93c96b3
--- /dev/null
+++ b/base_code/linux_driver/of_function_test/of_function/of_function_test.c
@@ -0,0 +1,176 @@
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/fs.h>
+#include <linux/cdev.h>
+#include <linux/uaccess.h>
+
+
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/delay.h>
+#include <linux/ide.h>
+#include <linux/errno.h>
+#include <linux/gpio.h>
+#include <asm/mach/map.h>
+#include <asm/io.h>
+
+#include <linux/of.h>
+#include <linux/of_address.h>
+
+
+#define DEV_NAME            "of_test"
+#define DEV_CNT                 (1)
+//定义字符设备的设备号
+static dev_t led_devno;
+//定义字符设备结构体chr_dev
+static struct cdev led_chr_dev;
+//创建类
+struct class *led_chrdev_class;
+
+
+struct device_node	*led_device_node; //led的设备树节点
+struct device_node  *rgb_led_red_device_node; //rgb_led_red 红灯节点
+struct property     *rgb_led_red_property;    //定义属性结构体指针
+int size = 0 ;
+unsigned int out_values[18];  //保存读取得到的REG 属性值
+
+/*.open 函数*/
+static int led_chr_dev_open(struct inode *inode, struct file *filp)
+{
+    int error_status = -1;
+
+    printk("\n open form device \n");
+
+    /*of 测试函数*/
+    led_device_node = of_find_node_by_path("/led");
+    if(led_device_node == NULL)
+    {
+        printk(KERN_EMERG "\n get led_device_node failed ! \n");
+        return -1;
+    }
+    /*根据 led_device_node 设备节点结构体输出节点的基本信息*/
+    printk(KERN_EMERG "name: %s",led_device_node->name); //输出节点名
+    printk(KERN_EMERG "child name: %s",led_device_node->child->name);  //输出子节点的节点名
+
+
+    /*获取 rgb_led_red_device_node 的子节点*/ 
+    rgb_led_red_device_node = of_get_next_child(led_device_node,NULL); 
+    if(rgb_led_red_device_node == NULL)
+    {
+        printk(KERN_EMERG "\n get rgb_led_red_device_node failed ! \n");
+        return -1;
+    }
+    printk(KERN_EMERG "name: %s",rgb_led_red_device_node->name); //输出节点名
+    printk(KERN_EMERG "parent name: %s",rgb_led_red_device_node->parent->name);  //输出父节点的节点名
+
+
+    /*获取 rgb_led_red_device_node 节点  的"compatible" 属性 */ 
+    rgb_led_red_property = of_find_property(rgb_led_red_device_node,"compatible",&size);
+    if(rgb_led_red_property == NULL)
+    {
+        printk(KERN_EMERG "\n get rgb_led_red_property failed ! \n");
+        return -1;
+    }
+    printk(KERN_EMERG "size = : %d",size);                      //实际读取得到的长度
+    printk(KERN_EMERG "name: %s",rgb_led_red_property->name);   //输出属性名
+    printk(KERN_EMERG "length: %d",rgb_led_red_property->length);        //输出属性长度
+    printk(KERN_EMERG "value : %s",(char*)rgb_led_red_property->value);  //属性值
+
+
+    /*获取 reg 地址属性*/
+    error_status = of_property_read_u32_array(rgb_led_red_device_node,"reg",out_values, 2);
+    if(error_status != 0)
+    {
+        printk(KERN_EMERG "\n get out_values failed ! \n");
+        return -1;
+    }
+    printk(KERN_EMERG"0x%08X ", out_values[0]);
+    printk(KERN_EMERG"0x%08X ", out_values[1]);
+
+    return 0;
+}
+
+/*.release 函数*/
+static int led_chr_dev_release(struct inode *inode, struct file *filp)
+{
+    printk("\nrelease\n");
+    return 0;
+}
+
+
+/*字符设备操作函数集*/
+static struct file_operations  led_chr_dev_fops = 
+{
+    .owner = THIS_MODULE,
+    .open = led_chr_dev_open,
+    .release = led_chr_dev_release,
+};
+
+
+
+/*
+*驱动初始化函数
+*/
+static int __init led_chrdev_init(void)
+{
+    int ret = 0;
+    printk("led chrdev init\n");
+    //第一步
+    //采用动态分配的方式，获取设备编号，次设备号为0，
+    //设备名称为EmbedCharDev，可通过命令cat  /proc/devices查看
+    //DEV_CNT为1，当前只申请一个设备编号
+    ret = alloc_chrdev_region(&led_devno, 0, DEV_CNT, DEV_NAME);
+    if(ret < 0){
+        printk("fail to alloc led_devno\n");
+        goto alloc_err;
+    }
+
+    led_chrdev_class = class_create(THIS_MODULE, "led_chrdev");
+    //第二步
+    //关联字符设备结构体cdev与文件操作结构体file_operations
+    cdev_init(&led_chr_dev, &led_chr_dev_fops);
+    //第三步
+    //添加设备至cdev_map散列表中
+    ret = cdev_add(&led_chr_dev, led_devno, DEV_CNT);
+    if(ret < 0)
+    {
+        printk("fail to add cdev\n");
+        goto add_err;
+    }
+
+    //创建设备
+    device_create(led_chrdev_class, NULL, led_devno, NULL,
+			      DEV_NAME);
+    return 0;
+
+add_err:
+    //添加设备失败时，需要注销设备号
+    unregister_chrdev_region(led_devno, DEV_CNT);
+alloc_err:
+    return ret;
+}
+
+
+
+
+
+/*
+*驱动注销函数
+*/
+
+static void __exit led_chrdev_exit(void)
+{
+    printk("chrdev exit\n");
+   
+    device_destroy(led_chrdev_class, led_devno);   //清除设备
+    cdev_del(&led_chr_dev);                        //清除设备号
+    unregister_chrdev_region(led_devno, DEV_CNT);  //取消注册字符设备
+    class_destroy(led_chrdev_class);               //清除类
+}
+
+
+module_init(led_chrdev_init);
+module_exit(led_chrdev_exit);
+
+MODULE_LICENSE("GPL");
+
diff --git a/base_code/linux_driver/platform_driver/Makefile b/base_code/linux_driver/platform_driver/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..7b0540131c9f67755b8c115f075be6e0cff36d8e
--- /dev/null
+++ b/base_code/linux_driver/platform_driver/Makefile
@@ -0,0 +1,19 @@
+
+
+NATIVE ?= true
+
+
+ifeq ($(NATIVE), false)
+	KERNEL_DIR = /home/embedfire/linux4.19
+else
+	KERNEL_DIR = /lib/modules/$(shell uname -r)/build
+endif
+
+obj-m := led_pdev.o led_pdrv.o
+
+all:modules
+modules clean:
+	$(MAKE) -C $(KERNEL_DIR) M=$(shell pwd) $@
+
+
+
diff --git a/base_code/linux_driver/platform_driver/led_pdev.c b/base_code/linux_driver/platform_driver/led_pdev.c
new file mode 100644
index 0000000000000000000000000000000000000000..8b454e16975768bf79674aa964abe514c4d11585
--- /dev/null
+++ b/base_code/linux_driver/platform_driver/led_pdev.c
@@ -0,0 +1,111 @@
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+
+#define CCM_CCGR1 															0x20C406C	//时钟控制寄存器
+#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO04 				0x20E006C	//GPIO1_04复用功能选择寄存器
+#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO04 				0x20E02F8	//PAD属性设置寄存器
+#define GPIO1_GDIR 															0x0209C004	//GPIO方向设置寄存器（输入或输出）
+#define GPIO1_DR 																0x0209C000	//GPIO输出状态寄存器
+
+#define CCM_CCGR3 															0x020C4074
+#define GPIO4_GDIR 															0x020A8004
+#define GPIO4_DR 																0x020A8000
+
+#define IOMUXC_SW_MUX_CTL_PAD_GPIO4_IO020 			0x020E01E0
+#define IOMUXC_SW_PAD_CTL_PAD_GPIO4_IO020 			0x020E046C
+
+#define IOMUXC_SW_MUX_CTL_PAD_GPIO4_IO019 			0x020E01DC
+#define IOMUXC_SW_PAD_CTL_PAD_GPIO4_IO019 			0x020E0468
+
+static struct resource rled_resource[] = {
+	[0] = DEFINE_RES_MEM(GPIO1_DR, 4),
+	[1] = DEFINE_RES_MEM(GPIO1_GDIR, 4),
+	[2] = DEFINE_RES_MEM(IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO04, 4),
+	[3] = DEFINE_RES_MEM(CCM_CCGR1, 4),
+	[4] = DEFINE_RES_MEM(IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO04, 4),
+};
+
+static struct resource gled_resource[] = {
+	[0] = DEFINE_RES_MEM(GPIO4_DR, 4),
+	[1] = DEFINE_RES_MEM(GPIO4_GDIR, 4),
+	[2] = DEFINE_RES_MEM(IOMUXC_SW_MUX_CTL_PAD_GPIO4_IO020, 4),
+	[3] = DEFINE_RES_MEM(CCM_CCGR3, 4),
+	[4] = DEFINE_RES_MEM(IOMUXC_SW_PAD_CTL_PAD_GPIO4_IO020, 4),
+};
+
+static struct resource bled_resource[] = {
+	[0] = DEFINE_RES_MEM(GPIO4_DR, 4),
+	[1] = DEFINE_RES_MEM(GPIO4_GDIR, 4),
+	[2] = DEFINE_RES_MEM(IOMUXC_SW_MUX_CTL_PAD_GPIO4_IO019, 4),
+	[3] = DEFINE_RES_MEM(CCM_CCGR3, 4),
+	[4] = DEFINE_RES_MEM(IOMUXC_SW_PAD_CTL_PAD_GPIO4_IO019, 4),
+};
+/* not used */ 
+static void led_release(struct device *dev)
+{
+
+}
+
+/* led hardware information */
+unsigned int rled_hwinfo[2] = { 4, 26 };
+unsigned int gled_hwinfo[2] = { 20, 12 };
+unsigned int bled_hwinfo[2] = { 19, 12 };
+
+/* red led device */ 
+static struct platform_device rled_pdev = {
+	.name = "led_pdev",
+	.id = 0,
+	.num_resources = ARRAY_SIZE(rled_resource),
+	.resource = rled_resource,
+	.dev = {
+		.release = led_release,
+		.platform_data = rled_hwinfo,
+		},
+};
+/* green led device */ 
+static struct platform_device gled_pdev = {
+	.name = "led_pdev",
+	.id = 1,
+	.num_resources = ARRAY_SIZE(gled_resource),
+	.resource = gled_resource,
+	.dev = {
+		.release = led_release,
+		.platform_data = gled_hwinfo,
+		},
+};
+/* blue led device */ 
+static struct platform_device bled_pdev = {
+	.name = "led_pdev",
+	.id = 2,
+	.num_resources = ARRAY_SIZE(bled_resource),
+	.resource = bled_resource,
+	.dev = {
+		.release = led_release,
+		.platform_data = bled_hwinfo,
+		},
+};
+
+static __init int led_pdev_init(void)
+{
+	printk("pdev init\n");
+	platform_device_register(&rled_pdev);
+	platform_device_register(&gled_pdev);
+	platform_device_register(&bled_pdev);
+	return 0;
+}
+
+module_init(led_pdev_init);
+
+static __exit void led_pdev_exit(void)
+{
+	printk("pdev exit\n");
+	platform_device_unregister(&rled_pdev);
+	platform_device_unregister(&gled_pdev);
+	platform_device_unregister(&bled_pdev);
+}
+
+module_exit(led_pdev_exit);
+
+MODULE_AUTHOR("embedfire");
+MODULE_LICENSE("GPL");
diff --git a/base_code/linux_driver/platform_driver/led_pdrv.c b/base_code/linux_driver/platform_driver/led_pdrv.c
new file mode 100644
index 0000000000000000000000000000000000000000..21e4351c707c6792b278bd9ee80c6a24b69c2dba
--- /dev/null
+++ b/base_code/linux_driver/platform_driver/led_pdrv.c
@@ -0,0 +1,234 @@
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/mod_devicetable.h>
+#include <linux/io.h>
+#include <linux/cdev.h>
+#include <linux/fs.h>
+
+#define DEV_MAJOR 243
+#define DEV_NAME  "led"
+
+static struct class *my_led_class;
+
+struct led_data {
+	unsigned int led_pin;
+	unsigned int clk_regshift;
+
+	unsigned int __iomem *va_dr;
+	unsigned int __iomem *va_gdir;
+	unsigned int __iomem *va_iomuxc_mux;
+	unsigned int __iomem *va_ccm_ccgrx;
+	unsigned int __iomem *va_iomux_pad;	
+
+	struct cdev led_cdev;
+
+};
+
+static int led_cdev_open(struct inode *inode, struct file *filp)
+{
+	printk("%s\n", __func__);
+	
+	struct led_data *cur_led = container_of(inode->i_cdev, struct led_data, led_cdev);
+	unsigned int val = 0;
+
+	val = readl(cur_led->va_ccm_ccgrx);
+	val &= ~(3 << cur_led->clk_regshift);
+	val |= (3 << cur_led->clk_regshift);
+	writel(val, cur_led->va_ccm_ccgrx);
+
+	writel(5, cur_led->va_iomuxc_mux);
+
+	writel(0x1F838, cur_led->va_iomux_pad);
+
+	val = readl(cur_led->va_gdir);
+	val &= ~(1 << cur_led->led_pin);
+	val |= (1 << cur_led->led_pin);
+	writel(val, cur_led->va_gdir);
+
+	val = readl(cur_led->va_dr);
+	val |= (0x01 << cur_led->led_pin);
+	writel(val, cur_led->va_dr);
+
+	filp->private_data = cur_led;
+
+	return 0;
+}
+
+
+static int led_cdev_release(struct inode *inode, struct file *filp)
+{
+	return 0;
+}
+
+static ssize_t led_cdev_write(struct file *filp, const char __user * buf,
+			      size_t count, loff_t * ppos)
+{
+	unsigned long val = 0;
+	unsigned long ret = 0;
+
+	int tmp = count;
+
+	struct led_data *cur_led = (struct led_data *)filp->private_data;
+
+	kstrtoul_from_user(buf, tmp, 10, &ret);
+
+	val = readl(cur_led->va_dr);
+	if (ret == 0)
+		val &= ~(0x01 << cur_led->led_pin);
+	else
+		val |= (0x01 << cur_led->led_pin);
+
+	writel(val, cur_led->va_dr);
+	*ppos += tmp;
+
+	return tmp;
+}
+
+static struct file_operations led_cdev_fops = {
+	.open = led_cdev_open,
+	.release = led_cdev_release,
+	.write = led_cdev_write,
+};
+
+
+
+static int led_pdrv_probe(struct platform_device *pdev)
+{
+	struct led_data *cur_led;
+	unsigned int *led_hwinfo;
+	
+	struct resource *mem_dr;
+	struct resource *mem_gdir;
+	struct resource *mem_iomuxc_mux;
+	struct resource *mem_ccm_ccgrx;
+	struct resource *mem_iomux_pad; 	
+
+	dev_t cur_dev;
+
+	int ret = 0;
+	
+	printk("led platform driver probe\n");
+
+	cur_led = devm_kzalloc(&pdev->dev, sizeof(struct led_data), GFP_KERNEL);
+	if(!cur_led)
+		return -ENOMEM;
+	led_hwinfo = devm_kzalloc(&pdev->dev, sizeof(unsigned int)*2, GFP_KERNEL);
+	if(!led_hwinfo)
+		return -ENOMEM;
+
+	/* get the pin for led and the reg's shift */
+	led_hwinfo = dev_get_platdata(&pdev->dev);
+
+	cur_led->led_pin = led_hwinfo[0];
+	cur_led->clk_regshift = led_hwinfo[1];
+	/* get platform resource */
+	mem_dr = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	mem_gdir = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+	mem_iomuxc_mux = platform_get_resource(pdev, IORESOURCE_MEM, 2);
+	mem_ccm_ccgrx = platform_get_resource(pdev, IORESOURCE_MEM, 3);
+	mem_iomux_pad = platform_get_resource(pdev, IORESOURCE_MEM, 4);
+
+	cur_led->va_dr =
+	    devm_ioremap(&pdev->dev, mem_dr->start, resource_size(mem_dr));
+	cur_led->va_gdir =
+	    devm_ioremap(&pdev->dev, mem_gdir->start, resource_size(mem_gdir));
+	cur_led->va_iomuxc_mux =
+	    devm_ioremap(&pdev->dev, mem_iomuxc_mux->start,
+			 resource_size(mem_iomuxc_mux));
+	cur_led->va_ccm_ccgrx =
+	    devm_ioremap(&pdev->dev, mem_ccm_ccgrx->start,
+			 resource_size(mem_ccm_ccgrx));
+	cur_led->va_iomux_pad =
+	    devm_ioremap(&pdev->dev, mem_iomux_pad->start,
+			 resource_size(mem_iomux_pad));
+
+	cur_dev = MKDEV(DEV_MAJOR, pdev->id);
+
+	register_chrdev_region(cur_dev, 1, "led_cdev");
+
+	cdev_init(&cur_led->led_cdev, &led_cdev_fops);
+
+	ret = cdev_add(&cur_led->led_cdev, cur_dev, 1);
+	if(ret < 0)
+	{
+		printk("fail to add cdev\n");
+		goto add_err;
+	}
+	
+	device_create(my_led_class, NULL, cur_dev, NULL, DEV_NAME "%d", pdev->id);
+
+	/* save as drvdata */ 
+	platform_set_drvdata(pdev, cur_led);
+
+	return 0;
+
+add_err:
+	unregister_chrdev_region(cur_dev, 1);
+	return ret;
+}
+
+
+static int led_pdrv_remove(struct platform_device *pdev)
+{
+	dev_t cur_dev; 
+	struct led_data *cur_data = platform_get_drvdata(pdev);
+
+
+	printk("led platform driver remove\n");
+
+	cur_dev = MKDEV(DEV_MAJOR, pdev->id);
+
+	cdev_del(&cur_data->led_cdev);
+
+	device_destroy(my_led_class, cur_dev);
+
+	unregister_chrdev_region(cur_dev, 1);
+
+	return 0;
+}
+
+static struct platform_device_id led_pdev_ids[] = {
+	{.name = "led_pdev"},
+	{}
+};
+
+MODULE_DEVICE_TABLE(platform, led_pdev_ids);
+
+static struct platform_driver led_pdrv = {
+	
+	.probe = led_pdrv_probe,
+	.remove = led_pdrv_remove,
+	.driver.name = "led_pdev",
+	.id_table = led_pdev_ids,
+};
+
+
+
+static __init int led_pdrv_init(void)
+{
+	printk("led platform driver init\n");
+
+	my_led_class = class_create(THIS_MODULE, "my_leds");
+	
+	platform_driver_register(&led_pdrv);
+
+	return 0;
+}
+module_init(led_pdrv_init);
+
+
+static __exit void led_pdrv_exit(void)
+{
+	printk("led platform driver exit\n");	
+
+	platform_driver_unregister(&led_pdrv);
+
+	class_destroy(my_led_class);
+
+}
+module_exit(led_pdrv_exit);
+
+MODULE_AUTHOR("Embedfire");
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("the example for platform driver");
diff --git a/base_code/linux_env/pyqt5_demo.py b/base_code/linux_env/pyqt5_demo.py
new file mode 100644
index 0000000000000000000000000000000000000000..5f8c5e4690c4267d1d4b71f05d157033ff207101
--- /dev/null
+++ b/base_code/linux_env/pyqt5_demo.py
@@ -0,0 +1,46 @@
+import sys
+from PyQt5.QtWidgets import QWidget,QLCDNumber,QSlider,QVBoxLayout,QApplication
+from PyQt5.QtCore import Qt
+
+class WinForm(QWidget):
+    def __init__(self):
+        super().__init__()   
+        self.initUI()
+
+    def initUI(self):
+        #1 先创建滑块和 LCD 部件
+        lcd = QLCDNumber(self)
+        slider = QSlider(Qt.Horizontal, self)
+        
+        slider.setMaximum(1000)
+        lcd.display(666)
+        slider.setValue(666)
+
+        #2 通过QVboxLayout来设置布局
+        vBox = QVBoxLayout()
+        vBox.addWidget(lcd)
+        vBox.addWidget(slider)
+
+        self.setLayout(vBox)
+        #3 valueChanged()是Qslider的一个信号函数，只要slider的值发生改变，它就会发射一个信号，然后通过connect连接信号的接收部件，也就是lcd。
+        slider.valueChanged.connect(lcd.display)
+       
+        slider.setMinimumWidth(200) 
+        slider.setFixedHeight(60)
+        
+        style = "QSlider::groove:horizontal {border:1px solid #999999;height:10px;" \
+                            "background-color:#666666;margin:2px 0;}" \
+                            "QSlider::handle:horizontal {background-color:#ff0000;border:1px solid #797979;" \
+                            "width:50px;margin:-20px;border-radius:25px;}" \
+                            
+        slider.setStyleSheet(style);
+        
+        #self.setGeometry(0,0,800,480)
+        self.setWindowTitle("拖动滑块LCD显示")
+
+if __name__ == '__main__':
+    app = QApplication(sys.argv)
+    form = WinForm()
+    form.resize(800, 480)
+    form.show()                      
+    sys.exit(app.exec_())
diff --git a/base_code/linux_env/run.sh b/base_code/linux_env/run.sh
new file mode 100755
index 0000000000000000000000000000000000000000..d376f40af05a878528f213ae6c99cb14b58e9459
--- /dev/null
+++ b/base_code/linux_env/run.sh
@@ -0,0 +1,33 @@
+#! /bin/sh
+
+type devscan
+
+if [ $? -eq 0 ]; then
+    eventx=$(devscan "goodix-ts")
+    echo "eventx=$eventx"
+    if [ "$eventx " != " " ]; then
+        if [ ! -f "/etc/pointercal" ]; then
+            type ts_calibrate
+            if [ $? -eq 0 ]; then
+                ts_calibrate
+            fi
+        fi
+    else 
+        echo "eventx is null"
+    fi
+else
+    echo "please install devscan"
+    echo
+    echo "sudo apt-get install devscan"
+    exit
+fi
+
+export TSLIB_TSDEVICE=/dev/input/$eventx
+export QT_QPA_PLATFORM=linuxfb:fb=/dev/fb0
+export TSLIB_CONFFILE=/etc/ts.conf
+export TSLIB_CALIBFILE=/etc/pointercal
+export QT_QPA_GENERIC_PLUGINS=tslib:/dev/input/$eventx
+export QT_QPA_EVDEV_TOUCHSCREEN_PARAMETERS=/dev/input/$eventx
+
+echo "start pyqt pyqt5_demo..."
+python3 pyqt5_demo.py
diff --git a/base_code/linux_env/serial_demo.py b/base_code/linux_env/serial_demo.py
new file mode 100644
index 0000000000000000000000000000000000000000..d67e2d1551d3486318ee2b3dce1b3a3542e3e54b
--- /dev/null
+++ b/base_code/linux_env/serial_demo.py
@@ -0,0 +1,26 @@
+import serial
+from time import sleep
+
+def recv(serial):
+    while True:
+        data = serial.read_all()
+        if data != b'' :
+            break
+        
+    return data.decode()
+
+
+if __name__ == '__main__':
+    serial = serial.Serial('/dev/tty10', 115200)  # /dev/ttymxc2
+    if serial.isOpen() :
+        print("open success")
+    else :
+        print("open failed")
+
+    while True:
+        data =recv(serial)
+        if data != '' :
+            print("receive:",data)
+            serial.write(data.encode()) # 数据回显
+
+
diff --git a/base_code/linux_env/weather.py b/base_code/linux_env/weather.py
new file mode 100644
index 0000000000000000000000000000000000000000..2d865294daa01200c4b953c4f99bab4e3d00337d
--- /dev/null
+++ b/base_code/linux_env/weather.py
@@ -0,0 +1,46 @@
+import json, requests
+
+#输入地点
+weather_place = "东莞"
+
+#日期
+date = []
+#最高温与最低温
+high_temp = []
+low_temp = []
+#天气
+weather = []
+
+# 请求天气信息
+weather_url = "http://wthrcdn.etouch.cn/weather_mini?city=%s" % (weather_place)
+
+response = requests.get(weather_url)
+try:
+    response.raise_for_status()
+except:
+    print("请求信息出错")
+    
+#将json文件格式导入成python的格式
+weather_data = json.loads(response.text)
+
+# 打印原始数据
+# print(weather_data)
+ 
+w = weather_data['data']
+
+print("地点：%s" % w['city'])
+
+#进行五天的天气遍历，并格式化输出
+for i in range(len(w['forecast'])):
+    date.append(w['forecast'][i]['date'])
+    high_temp.append(w['forecast'][i]['high'])
+    low_temp.append(w['forecast'][i]['low'])
+    weather.append(w['forecast'][i]['type'])
+    
+    #输出
+    print("日期：" + date[i])
+    print("\t温度：最" + low_temp[i] + "\t最" + high_temp[i])
+    print("\t天气：" + weather[i] + "\n")
+    
+print("\n今日着装：" + w['ganmao'])
+print("当前温度：" + w['wendu'])
diff --git a/base_code/linux_iot/http_client/Makefile b/base_code/linux_iot/http_client/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..d5e1c224258e4f6534bfc20c32fae3d9b33f004c
--- /dev/null
+++ b/base_code/linux_iot/http_client/Makefile
@@ -0,0 +1,25 @@
+CC=gcc
+SRC = $(wildcard *.c */*.c)
+OBJS = $(patsubst %.c, %.o, $(SRC))
+DEP_FILES := $(patsubst %, .%.d,$(OBJS))
+DEP_FILES := $(wildcard $(DEP_FILES))
+FLAG = -g -Werror -I. -Iinclude -lpthread
+TARGET = targets
+
+$(TARGET):$(OBJS)
+	$(CC) -o $@ $^ $(FLAG)
+
+ifneq ($(DEP_FILES),)
+include $(DEP_FILES)
+endif
+
+%.o:%.c
+	$(CC) -o $@ -c $(FLAG) $< -g -MD -MF .$@.d
+
+clean:
+	rm -rf $(TARGET) $(OBJS)
+
+distclean:
+	rm -rf $(DEP_FILES)
+
+.PHONY:clean
diff --git a/base_code/linux_iot/http_client/httpclient.c b/base_code/linux_iot/http_client/httpclient.c
new file mode 100644
index 0000000000000000000000000000000000000000..c42646a19ae1e60f999a8e87a009d129540b5817
--- /dev/null
+++ b/base_code/linux_iot/http_client/httpclient.c
@@ -0,0 +1,225 @@
+/******* http客户端程序 httpclient.c ************/
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <sys/socket.h>
+#include <errno.h>
+#include <unistd.h>
+#include <netdb.h>
+#include <ctype.h>
+
+/********************************************
+功能：搜索字符串右边起的第一个匹配字符
+********************************************/
+char *right_strchr(char * s, char x)
+{
+    int i = strlen(s);
+    if (!(*s)) 
+        return 0;
+    while (s[i-1]) {
+        if (strchr(s + (i - 1), x)) {
+            return (s + (i - 1));
+        } else {
+            i--;
+        }
+    }
+    return 0;
+}
+
+/********************************************
+功能：把字符串转换为全小写
+********************************************/
+void str_to_lower(char * s)
+{
+    while (s && *s) {
+        *s=tolower(*s);
+        s++;
+    }
+}
+
+/**************************************************************
+功能：从字符串src中分析出网站地址和端口，并得到用户要下载的文件
+***************************************************************/
+void get_connect_info(char * src, char * host, char * file, int * port)
+{
+    char *p1;
+    char *p2;
+
+    memset(host, 0, sizeof(host));
+    memset(file, 0, sizeof(file));
+
+    *port = 0;
+
+    if (!(*src)) 
+        return;
+
+    p1 = src;
+
+    if (!strncmp(p1, "http://", strlen("http://"))) 
+        p1 = src + strlen("http://");
+    else if (!strncmp(p1, "https://", strlen("https://"))) 
+        p1 = src + strlen("https://");
+    
+    p2 = strchr(p1, '/');
+
+    if (p2) {
+        memcpy(host, p1, strlen(p1) - strlen(p2));
+        if (p2+1) {
+            memcpy(file, p2 + 1, strlen(p2) - 1);
+            file[strlen(p2) - 1] = 0;
+        }
+    } else {
+        memcpy(host, p1, strlen(p1));
+    }
+    
+    if (p2) 
+        host[strlen(p1) - strlen(p2)] = 0;
+    else 
+        host[strlen(p1)] = 0;
+    
+    p1 = strchr(host, ':');
+
+    if (p1) 
+        *port = atoi(p1 + 1);
+    else 
+        *port = 80;     /* 只支持http协议 */
+}
+
+
+int main(int argc, char *argv[])
+{
+    int sockfd;
+    char buffer[1024];
+    struct sockaddr_in server_addr;
+    struct hostent *host;
+    int port,nbytes;
+    char host_addr[256];
+    char host_file[1024];
+    char local_file[256];
+    FILE * fp;
+    char request[1024];
+    int send, totalsend;
+    int i = 0;
+    char * pt;
+
+    if (argc!=2) {
+        fprintf(stderr,"Usage:%s host-address\a\n",argv[0]);
+        exit(1);
+    }
+
+    str_to_lower(argv[1]);/*将参数转换为全小写*/
+
+    get_connect_info(argv[1], host_addr, host_file, &port);  /*分析网址、端口、文件名等*/
+
+    // printf("host:%s\n", host_addr);
+    // printf("hostfile:%s\n", host_file);
+    // printf("port:%d\n\n", port);
+
+    if ((host=gethostbyname(host_addr))==NULL) { /*取得主机IP地址*/
+        fprintf(stderr,"Gethostname error, %s\n", strerror(errno));
+        exit(1);
+    }
+
+    /* 客户程序开始建立 sockfd描述符 */
+    if ((sockfd=socket(AF_INET,SOCK_STREAM,0))==-1) { /*建立SOCKET连接*/
+        fprintf(stderr,"Socket Error:%s\a\n",strerror(errno));
+        exit(1);
+    }
+
+    /* 客户程序填充服务端的资料 */
+    bzero(&server_addr,sizeof(server_addr));
+    server_addr.sin_family=AF_INET;
+    server_addr.sin_port=htons(port);
+    server_addr.sin_addr=*((struct in_addr *)host->h_addr);
+
+    /* 客户程序发起连接请求 */
+    if (connect(sockfd,(struct sockaddr *)(&server_addr),sizeof(struct sockaddr))==-1) { /*连接网站*/
+        fprintf(stderr,"Connect Error:%s\a\n",strerror(errno));
+        exit(1);
+    }
+
+    /*准备 request 报文，将要发送给主机*/
+    sprintf(request, "GET /%s HTTP/1.1\r\n"
+                     "Accept: */*\r\n"
+                     "Accept-Language: zh-cn\r\n"
+                     "User-Agent: Mozilla/5.0\r\n"
+                     "Host: %s:%d\r\n"
+                     "Connection: Close\r\n\r\n", host_file, host_addr, port);
+
+    /* 打印请求报文 */
+    printf("%s", request);
+
+    /*取得真实的文件名*/
+    if (host_file && *host_file) 
+        pt = right_strchr(host_file, '/');
+    else 
+        pt = 0;
+
+    memset(local_file, 0, sizeof(local_file));
+
+    if (pt && *pt) {
+        if ((pt + 1) && *(pt+1)) 
+            strcpy(local_file, pt + 1);
+        else
+            memcpy(local_file, host_file, strlen(host_file) - 1);
+
+    } else if (host_file && *host_file) {
+        strcpy(local_file, host_file);
+        
+    } else {
+        strcpy(local_file, "index.html");
+    }
+
+    // printf("local filename to write:%s\n\n", local_file);
+
+    /*发送http请求request*/
+    send = 0;
+    totalsend = 0;
+    nbytes=strlen(request);
+
+    while (totalsend < nbytes) {
+        send = write(sockfd, request + totalsend, nbytes - totalsend);
+        if (send==-1) {
+            printf("send error!%s\n", strerror(errno));
+            exit(0);
+        }
+
+        totalsend += send;
+        // printf("%d bytes send OK!\n", totalsend);
+    }
+
+    fp = fopen(local_file, "w");
+    if (!fp) {
+        printf("create file error! %s\n", strerror(errno));
+        return 0;
+    }
+
+    /* 连接成功了，接收http响应，response */
+    while ((nbytes = read(sockfd, buffer, 1)) == 1) {
+
+        /* 报文首部与主体之间有 \r\n\r\n */
+        if (i < 4) {
+
+            if (buffer[0] == '\r' || buffer[0] == '\n')
+                i++;
+            else 
+                i = 0;
+            /* 打印响应头部 */
+            printf("%c", buffer[0]);
+        } else {
+            printf("%c", buffer[0]);
+            fwrite(buffer, 1, 1, fp);/*将http主体信息写入文件*/
+            i++;
+            if (i%1024 == 0) 
+                fflush(fp); /*每1K时存盘一次*/
+        }
+    }
+
+    fclose(fp);
+    /* 结束通讯 */
+    close(sockfd);
+    exit(0);
+}
+
+
+ 
\ No newline at end of file
diff --git a/base_code/linux_iot/http_control_led/Makefile b/base_code/linux_iot/http_control_led/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..d5e1c224258e4f6534bfc20c32fae3d9b33f004c
--- /dev/null
+++ b/base_code/linux_iot/http_control_led/Makefile
@@ -0,0 +1,25 @@
+CC=gcc
+SRC = $(wildcard *.c */*.c)
+OBJS = $(patsubst %.c, %.o, $(SRC))
+DEP_FILES := $(patsubst %, .%.d,$(OBJS))
+DEP_FILES := $(wildcard $(DEP_FILES))
+FLAG = -g -Werror -I. -Iinclude -lpthread
+TARGET = targets
+
+$(TARGET):$(OBJS)
+	$(CC) -o $@ $^ $(FLAG)
+
+ifneq ($(DEP_FILES),)
+include $(DEP_FILES)
+endif
+
+%.o:%.c
+	$(CC) -o $@ -c $(FLAG) $< -g -MD -MF .$@.d
+
+clean:
+	rm -rf $(TARGET) $(OBJS)
+
+distclean:
+	rm -rf $(DEP_FILES)
+
+.PHONY:clean
diff --git a/base_code/linux_iot/http_control_led/http_control_led.c b/base_code/linux_iot/http_control_led/http_control_led.c
new file mode 100644
index 0000000000000000000000000000000000000000..1bfad55bf60bf518dc83080742e60f3e1ab2d071
--- /dev/null
+++ b/base_code/linux_iot/http_control_led/http_control_led.c
@@ -0,0 +1,165 @@
+#include <stdio.h>
+#include <netinet/in.h>
+#include <sys/socket.h> // socket
+#include <sys/types.h>  // 基本数据类型
+#include <unistd.h> // read write
+#include <string.h>
+#include <stdlib.h>
+#include <fcntl.h> // open close
+#include <sys/shm.h>
+#include <netinet/in.h>
+#include <arpa/inet.h>
+#include <signal.h>
+#include <sys/stat.h>
+
+
+#define PORT        8888
+#define SERVER      "0.0.0.0"
+#define BACKLOG     20
+#define BUFF_SIZE   (1024 * 500)
+
+#define LED_ON      "./led_on.html"
+#define LED_OFF     "./led_off.html"
+
+int sockfd;
+char *http_res_tmpl = "HTTP/1.1 200 OK\r\n"
+        "Server: Cleey's Server V1.0\r\n"
+        "Accept-Ranges: bytes\r\n"
+        "Content-Length: %d\r\n"
+        "Connection: close\r\n"
+        "Content-Type: %s\r\n\r\n";
+  
+int http_str_nmatch(const char *str1, const char *str2, int n)
+{
+    int i = 0;
+    int c1, c2;
+    do {
+        c1 = *str1++;
+        c2 = *str2++;
+        i++;
+    } while(((c1 == c2) && c1) && (i < n));
+
+    return c1 - c2;
+}
+
+void http_send(int sock_client, char *str) 
+{
+    char header[BUFF_SIZE], body[BUFF_SIZE];
+
+    int len = strlen(str);
+
+    sprintf(header, http_res_tmpl, len,"text/html");
+
+    len = sprintf(body,"%s%s", header, str);
+
+    send(sock_client, body, len, 0);
+}
+
+void handle_signal(int sign) 
+{
+    fputs("\nSIGNAL INTERRUPT \nBye Cleey! \nSAFE EXIT\n",stdout);
+    close(sockfd);
+    exit(0);
+}
+
+
+int read_file(char *filename, int *len, char **data)
+{
+    int file = open(filename, O_RDONLY);
+    if ( file == -1 )
+        return -1;
+
+    int i = 0;
+    while ( 1 )
+    {
+        *data = realloc(*data, (BUFF_SIZE * (i + 1)));
+        if ( data == NULL )
+        {
+            close( file );
+            return -1;
+        }
+
+        int cur_len = read(file, *data+(BUFF_SIZE * i), BUFF_SIZE);
+        if ( cur_len == 0 )
+            break;
+        else
+            *len += cur_len;
+
+        i++;
+    }
+
+    close( file );
+
+    return 0;
+}
+
+int main(void)
+{
+    signal(SIGINT,handle_signal);
+    int len = 0;
+    char *pdata = NULL;
+    int count = 0; // 计数
+    // 定义 socket
+    sockfd = socket(AF_INET,SOCK_STREAM,0);
+    // 定义 sockaddr_in
+    struct sockaddr_in skaddr;
+    skaddr.sin_family = AF_INET;            // ipv4
+    skaddr.sin_port   = htons(PORT);
+    skaddr.sin_addr.s_addr = inet_addr(SERVER);
+    // bind，绑定 socket 和 sockaddr_in
+    if (bind(sockfd,(struct sockaddr *)&skaddr,sizeof(skaddr)) == -1 ) {
+        perror("bind error");
+        exit(1);
+    }
+
+    // listen，开始添加端口
+    if (listen(sockfd, BACKLOG) == -1 ) {
+        perror("listen error");
+        exit(1);
+    }
+
+    // 客户端信息
+    char buff[BUFF_SIZE];
+    struct sockaddr_in claddr;
+    socklen_t length = sizeof(claddr);
+
+    while(1) {
+        int sock_client = accept(sockfd,(struct sockaddr *)&claddr, &length);
+        if (sock_client <0) {
+            perror("accept error");
+            exit(1);
+        }
+
+        memset(buff,0,sizeof(buff));
+
+        int len = recv(sock_client, buff, sizeof(buff), 0);
+
+        if (http_str_nmatch(buff, "GET /", 5) == 0) {
+
+            read_file(LED_ON, &len, &pdata);
+            http_send(sock_client, pdata);
+
+        } else if (http_str_nmatch(buff, "POST /on", 8) == 0) {
+
+            read_file(LED_ON, &len, &pdata);
+            http_send(sock_client, pdata);
+
+            printf("led on\n");
+
+        } else if (http_str_nmatch(buff, "POST /off", 8) == 0) {
+
+            read_file(LED_OFF, &len, &pdata);
+            http_send(sock_client, pdata);
+
+            printf("led off\n");
+        } else {
+            http_send(sock_client,"Hello World!");
+        }
+
+        // fputs(buff,stdout);
+        close(sock_client);
+    }
+    fputs("Bye Cleey",stdout);
+    close(sockfd);
+    return 0;
+}
diff --git a/base_code/linux_iot/http_control_led/led_off.html b/base_code/linux_iot/http_control_led/led_off.html
new file mode 100644
index 0000000000000000000000000000000000000000..5d824e04d1d3cc77fa9fa042501526810a0e4eb3
--- /dev/null
+++ b/base_code/linux_iot/http_control_led/led_off.html
@@ -0,0 +1,18 @@
+</html>
+    <head><title>HTTP LED Control</title></head> 
+    <center> 
+        <p> 
+        <font size="6">LED<font style = "color:red">�ѹر�</font> 
+        <form method=post action="on" name="ledform"> 
+        <input type="submit" value="��" style="width:80px;height:30px;"></form> 
+    </center> 
+
+    <head><title>Congrats!</title></head>
+    <body><h2 align="center">Welcome to Fire HTTP Server!</h2>
+        <p align="center">This is a small test page : http control led.</p>
+        <p align="center"><a href="https://www.firebbs.cn/forum.php/"> <font size="6"> Ұ������� </font> </a></p>
+        <a href="https://www.firebbs.cn/forum.php/">
+        <img src="https://www.firebbs.cn/data/attachment/portal/201806/05/163015rhz7mbgbt0zfujzh.jpg"/></a>
+    </body>
+
+</html>
\ No newline at end of file
diff --git a/base_code/linux_iot/http_control_led/led_on.html b/base_code/linux_iot/http_control_led/led_on.html
new file mode 100644
index 0000000000000000000000000000000000000000..5b807eb2dc5b50e5fc2d2e8aafd8f782f4c1edc4
--- /dev/null
+++ b/base_code/linux_iot/http_control_led/led_on.html
@@ -0,0 +1,18 @@
+</html>
+    <head><title>HTTP LED Control</title></head> 
+    <center> 
+        <p> 
+        <font size="6">LED<font style = "color:red">�Ѵ�</font> 
+        <form method=post action="off" name="ledform"> 
+        <input type="submit" value="�ر�" style="width:80px;height:30px;"></form> 
+    </center> 
+
+    <head><title>Congrats!</title></head>
+    <body><h2 align="center">Welcome to Fire HTTP Server!</h2>
+        <p align="center">This is a small test page : http control led.</p>
+        <p align="center"><a href="https://www.firebbs.cn/forum.php/"> <font size="6"> Ұ������� </font> </a></p>
+        <a href="https://www.firebbs.cn/forum.php/">
+        <img src="https://www.firebbs.cn/data/attachment/portal/201806/05/163015rhz7mbgbt0zfujzh.jpg"/></a>
+    </body>
+
+</html>
\ No newline at end of file
diff --git a/base_code/linux_iot/http_server/Makefile b/base_code/linux_iot/http_server/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..d5e1c224258e4f6534bfc20c32fae3d9b33f004c
--- /dev/null
+++ b/base_code/linux_iot/http_server/Makefile
@@ -0,0 +1,25 @@
+CC=gcc
+SRC = $(wildcard *.c */*.c)
+OBJS = $(patsubst %.c, %.o, $(SRC))
+DEP_FILES := $(patsubst %, .%.d,$(OBJS))
+DEP_FILES := $(wildcard $(DEP_FILES))
+FLAG = -g -Werror -I. -Iinclude -lpthread
+TARGET = targets
+
+$(TARGET):$(OBJS)
+	$(CC) -o $@ $^ $(FLAG)
+
+ifneq ($(DEP_FILES),)
+include $(DEP_FILES)
+endif
+
+%.o:%.c
+	$(CC) -o $@ -c $(FLAG) $< -g -MD -MF .$@.d
+
+clean:
+	rm -rf $(TARGET) $(OBJS)
+
+distclean:
+	rm -rf $(DEP_FILES)
+
+.PHONY:clean
diff --git a/base_code/linux_iot/http_server/httpserver.c b/base_code/linux_iot/http_server/httpserver.c
new file mode 100644
index 0000000000000000000000000000000000000000..3c9e8274075be9ec21786fb54acdbe1c2abdd366
--- /dev/null
+++ b/base_code/linux_iot/http_server/httpserver.c
@@ -0,0 +1,169 @@
+#include <stdio.h>
+#include <netinet/in.h>
+#include <sys/socket.h> // socket
+#include <sys/types.h>  // 基本数据类型
+#include <unistd.h> // read write
+#include <string.h>
+#include <stdlib.h>
+#include <fcntl.h> // open close
+#include <sys/shm.h>
+#include <netinet/in.h>
+#include <arpa/inet.h>
+#include <signal.h>
+#include <sys/stat.h>
+
+
+#define PORT        8888
+#define SERVER      "0.0.0.0"
+#define BACKLOG     20
+#define BUFF_SIZE   (1024 * 50)
+
+#define INDEX_FILE  "./index.html"
+
+int sockfd;
+
+// 发送给客户端的信息
+char *http_res_tmpl = "HTTP/1.1 200 OK\r\n"
+        "Server: Cleey's Server V1.0\r\n"
+        "Accept-Ranges: bytes\r\n"
+        "Content-Length: %d\r\n"
+        "Connection: close\r\n"
+        "Content-Type: %s\r\n\r\n";
+
+// 字符串的匹配，用于匹配http请求报文的内容
+int http_str_nmatch(const char *str1, const char *str2, int n)
+{
+    int i = 0;
+    int c1, c2;
+    do {
+        c1 = *str1++;
+        c2 = *str2++;
+        i++;
+    } while(((c1 == c2) && c1) && (i < n));
+
+    return c1 - c2;
+}
+
+// http 发送数据
+void http_send(int sock_client, char *str) 
+{
+    char header[BUFF_SIZE], body[BUFF_SIZE];
+
+    int len = strlen(str);
+
+    sprintf(header, http_res_tmpl, len,"text/html");
+
+    len = sprintf(body,"%s%s", header, str);
+
+    send(sock_client, body, len, 0);
+}
+
+void handle_signal(int sign) 
+{
+    fputs("\nSIGNAL INTERRUPT \nBye Cleey! \nSAFE EXIT\n",stdout);
+    close(sockfd);
+    exit(0);
+}
+
+// 根据指定的文件名读取文件的内容
+int read_file(char *filename, int *len, char **data)
+{
+    int file = open(filename, O_RDONLY);
+    if ( file == -1 )
+        return -1;
+
+    int i = 0;
+    while ( 1 )
+    {
+        // 分配内存空间
+        *data = realloc(*data, (BUFF_SIZE * (i + 1)));
+        if ( data == NULL )
+        {
+            close( file );
+            return -1;
+        }
+
+        // 读取文件内容
+        int cur_len = read(file, *data+(BUFF_SIZE * i), BUFF_SIZE);
+        if ( cur_len == 0 )
+            break;
+        else
+            *len += cur_len;
+
+        i++;
+    }
+
+    close( file );
+
+    return 0;
+}
+
+int main(void)
+{
+    signal(SIGINT,handle_signal);
+    int len = 0;
+    char *pdata = NULL;
+    int count = 0; // 计数
+
+    // 申请 socket
+    sockfd = socket(AF_INET,SOCK_STREAM,0);
+
+    // 定义 sockaddr_in
+    struct sockaddr_in skaddr;
+    skaddr.sin_family = AF_INET;            // ipv4
+    skaddr.sin_port   = htons(PORT);
+    skaddr.sin_addr.s_addr = inet_addr(SERVER);
+
+    // bind，绑定 socket 和 sockaddr_in
+    if (bind(sockfd,(struct sockaddr *)&skaddr,sizeof(skaddr)) == -1 ) {
+        perror("bind error");
+        exit(1);
+    }
+
+    // listen监听端口号
+    if (listen(sockfd, BACKLOG) == -1 ) {
+        perror("listen error");
+        exit(1);
+    }
+
+    // 客户端信息
+    char buff[BUFF_SIZE];
+    struct sockaddr_in claddr;
+    socklen_t length = sizeof(claddr);
+
+    while(1) {
+        // 出来连接
+        int sock_client = accept(sockfd,(struct sockaddr *)&claddr, &length);
+        if (sock_client <0) {
+            perror("accept error");
+            exit(1);
+        }
+
+        memset(buff,0,sizeof(buff));
+
+        // 接收来自客户端的请求
+        int len = recv(sock_client, buff, sizeof(buff), 0);
+
+        // 匹配是否为get方法
+        if (http_str_nmatch(buff, "GET /index", 10) == 0) {
+
+            read_file(INDEX_FILE, &len, &pdata);
+            http_send(sock_client, pdata);
+
+        } else if (http_str_nmatch(buff, "GET /", 5) == 0) {
+
+            read_file(INDEX_FILE, &len, &pdata);
+            http_send(sock_client, pdata);
+        } else {
+
+            http_send(sock_client,"Hello World!");
+        }
+
+        // 关闭连接
+        close(sock_client);
+    }
+
+    fputs("Bye Cleey",stdout);
+    close(sockfd);
+    return 0;
+}
diff --git a/base_code/linux_iot/http_server/index.html b/base_code/linux_iot/http_server/index.html
new file mode 100644
index 0000000000000000000000000000000000000000..86a3e7a3a274c92055517d05490c6a97aee05452
--- /dev/null
+++ b/base_code/linux_iot/http_server/index.html
@@ -0,0 +1,43 @@
+<!doctype html>
+<html>
+<head>
+    <meta charset="utf-8">
+    <title>富强、民主、和谐</title>
+    <style>
+        .container {
+            width: 60%;
+            margin: 10% auto 0;
+            background-color: #f0f0f0;
+            padding: 2% 5%;
+            border-radius: 10px
+        }
+        ul {
+            padding-left: 20px;
+        }
+
+            ul li {
+                line-height: 2.3
+            }
+        a {
+            color: #20a53a
+        }
+    </style>
+</head>
+<body>
+    <div class="container">
+        <h1>祝祖国70周年生日快乐</h1>
+        <h3>爱祖国，为祖国的前途而奋斗，是时代赋予我们的神圣职责</h3>
+        <ul>
+          <li>我是中国人民的儿子。我深情地爱着我的祖国和人民。</li>
+          <li>谁不爱自己的母亲，用那滚烫的赤子心灵。谁不爱自己的母亲，用那滚烫的赤子心灵。
+              亲爱的祖国，慈祥的母亲，长江黄河欢腾着，欢腾着深情，我们对您的深情。</li>
+          <li>我游览了白山黑水，看到了祖国的繁荣和富足。登上南沙群岛的珊瑚礁啊！我感受到了祖国幅员的广袤。
+              在八百里秦川，我听到了祖国儿女气势奔雷的心声。那一阵阵响入云天的威风锣鼓，那一声声惊天动地的浑厚呐喊。</li>
+          <li>“苟利国家生死以，岂因祸福避趋之”，我们现在就应该脚踏实地的从身边平凡的小事做起，不断陶冶爱国之心，增强爱国之智，将来为我们的祖国贡献力量！<br>
+              爱国，是一种坚定的民族精神，是一种振兴中华的责任感。我们青少年要用这种强大的精神力量去描绘祖国未来的宏图，将一片丹心献给祖过。让我们一起向着“心系祖国，健康成长”的目标前进吧！<br>
+              爱国，是至高无上的品德、是民族的灵魂。亲爱的同学们，为了学校的荣誉、为了我们肩上的重任，为了中华民族的腾飞，让我们努力学习，做一个无愧于人民的具有爱国主义情怀的万里学子吧！<br>
+              爱国是一个人对自己祖国的一种诚挚的热爱和深厚的情感，是一个人最原始的感情之一。但作为一个涉世不深的我，一直认为爱国是高不可攀也是比较渺茫的事。最近，我读了《民族英雄郑成功》一书，对爱国之情有了深刻的感悟。</li>
+        </ul>
+    </div>
+</body>
+</html>
\ No newline at end of file
diff --git a/base_code/system_programing/.gitignore b/base_code/system_programing/.gitignore
new file mode 100644
index 0000000000000000000000000000000000000000..7a944b6ac6c6a9ca54f4be3d9e159330b690f6a9
--- /dev/null
+++ b/base_code/system_programing/.gitignore
@@ -0,0 +1,6 @@
+/.vscode
+
+# all .o / .a / .d file 
+*.o
+*.a
+*.d
\ No newline at end of file
diff --git a/base_code/system_programing/LICENSE b/base_code/system_programing/LICENSE
new file mode 100644
index 0000000000000000000000000000000000000000..d8df2af4b96636f22ff70ac971d7a85d57932a3e
--- /dev/null
+++ b/base_code/system_programing/LICENSE
@@ -0,0 +1,29 @@
+BSD 3-Clause License
+
+Copyright (c) 2019, 杰杰
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+1. Redistributions of source code must retain the above copyright notice, this
+   list of conditions and the following disclaimer.
+
+2. Redistributions in binary form must reproduce the above copyright notice,
+   this list of conditions and the following disclaimer in the documentation
+   and/or other materials provided with the distribution.
+
+3. Neither the name of the copyright holder nor the names of its
+   contributors may be used to endorse or promote products derived from
+   this software without specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
diff --git a/base_code/system_programing/README.md b/base_code/system_programing/README.md
new file mode 100644
index 0000000000000000000000000000000000000000..9710a62b002bf0546adb2bb76db99ed1ff88e923
--- /dev/null
+++ b/base_code/system_programing/README.md
@@ -0,0 +1,5 @@
+# i.mx6ul_board
+This is an linux demo code for the i.mx6ul development board.
+
+Makefile uses static linking, if you do not use static linking:
+  change `FLAG = -g -Werror -I. -Iinclude -static` to `FLAG = -g -Werror -I. -Iinclude`
\ No newline at end of file
diff --git a/base_code/system_programing/alarm/Makefile b/base_code/system_programing/alarm/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..650ff5a5d9f8815fc27b343d6d7e8aa392d39925
--- /dev/null
+++ b/base_code/system_programing/alarm/Makefile
@@ -0,0 +1,78 @@
+
+#生成可执行文件的名称
+Target = system_demo
+ARCH ?= x86
+#编译器CC
+#根据传入的参数ARCH，确定使用的编译器
+#默认使用gcc编译器
+#make ARCH=arm 时使用ARM-GCC编译器
+ifeq ($(ARCH), x86)
+	CC = gcc
+else
+	CC = arm-linux-gnueabihf-gcc
+endif
+#存放中间文件的路径
+build_dir = build_$(ARCH)
+#存放源文件的文件夹
+src_dir =  sources
+#存放头文件的文件夹
+inc_dir = includes .
+
+#源文件
+sources = $(foreach dir,$(src_dir),$(wildcard $(dir)/*.c))
+#目标文件（*.o）
+objects = $(patsubst %.c,$(build_dir)/%.o,$(notdir $(sources)))
+#头文件
+includes = $(foreach dir,$(inc_dir),$(wildcard $(dir)/*.h))
+
+#目标依赖文件
+DEP_FILES := $(patsubst %, .%.d,$(objects))
+DEP_FILES := $(wildcard $(DEP_FILES))
+
+#判断依赖文件是否存在
+ifneq ($(DEP_FILES),)
+#如果存在依赖文件，需要导入依赖文件
+include $(DEP_FILES)
+endif
+
+#编译参数
+#指定头文件的路径
+CFLAGS = $(patsubst %, -I%, $(inc_dir)) -MD -MF $(@D)/.$(@F).d
+
+#链接过程
+$(build_dir)/$(Target) : $(objects)  | create_build
+	$(CC) $^ -o $@
+
+#编译工程
+#编译src文件夹中的源文件，并将生成的目标文件放在objs文件夹中
+$(build_dir)/%.o : $(src_dir)/%.c $(includes) | create_build
+	$(CC) -c $(CFLAGS) $< -o $@
+
+
+#以下为伪目标，调用方式：make 伪目标
+#clean：用于Clean Project
+#check：用于检查某个变量的值
+.PHONY:clean cleanall check create_build
+#按架构删除
+clean:
+	rm -rf $(build_dir)
+
+#全部删除
+cleanall:
+	rm -rf build_x86 build_arm
+
+#命令前带"@",表示不在终端上输出执行的命令
+#这个目标主要是用来调试Makefile时输出一些内容
+check:
+	@echo $(CFLAGS)
+	@echo $(CURDIR)
+	@echo $(src_dir)
+	@echo $(sources)
+	@echo $(objects)
+
+
+#创建一个新目录create，用于存放过程文件
+create_build:
+	@mkdir -p $(build_dir)
+
+
diff --git a/base_code/system_programing/alarm/sources/alarm.c b/base_code/system_programing/alarm/sources/alarm.c
new file mode 100644
index 0000000000000000000000000000000000000000..7beb38870eeb8e50311a5c1410f683e8ea055333
--- /dev/null
+++ b/base_code/system_programing/alarm/sources/alarm.c
@@ -0,0 +1,43 @@
+#include <stdio.h>
+#include <unistd.h>
+#include <stdlib.h>
+#include <signal.h>
+
+
+// int main() 
+// { 
+//     printf("\nthis is an alarm test function\n\n");
+// 	alarm(5);
+// 	sleep(20); 
+// 	printf("end!\n"); 
+// 	return 0; 
+// }
+
+
+int main() 
+{
+    unsigned int seconds;
+
+    printf("\nthis is an alarm test function\n\n");
+
+	seconds = alarm(20);
+
+    printf("last alarm seconds remaining is %d! \n\n", seconds);
+
+    printf("process sleep 5 seconds\n\n");
+	sleep(5); 
+
+    printf("sleep woke up, reset alarm!\n\n");
+
+    seconds = alarm(5);
+
+    printf("last alarm seconds remaining is %d! \n\n", seconds);
+
+    sleep(20); 
+
+	printf("end!\n"); 
+
+	return 0; 
+}
+
+
diff --git a/base_code/system_programing/exec/Makefile b/base_code/system_programing/exec/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..363731c0c365aa43035905ed2a42cdb4ad70fd54
--- /dev/null
+++ b/base_code/system_programing/exec/Makefile
@@ -0,0 +1,78 @@
+
+#生成可执行文件的名称
+Target = exec_demo
+ARCH ?= x86
+#编译器CC
+#根据传入的参数ARCH，确定使用的编译器
+#默认使用gcc编译器
+#make ARCH=arm 时使用ARM-GCC编译器
+ifeq ($(ARCH), x86)
+	CC = gcc
+else
+	CC = arm-linux-gnueabihf-gcc
+endif
+#存放中间文件的路径
+build_dir = build_$(ARCH)
+#存放源文件的文件夹
+src_dir =  sources
+#存放头文件的文件夹
+inc_dir = includes .
+
+#源文件
+sources = $(foreach dir,$(src_dir),$(wildcard $(dir)/*.c))
+#目标文件（*.o）
+objects = $(patsubst %.c,$(build_dir)/%.o,$(notdir $(sources)))
+#头文件
+includes = $(foreach dir,$(inc_dir),$(wildcard $(dir)/*.h))
+
+#目标依赖文件
+DEP_FILES := $(patsubst %, .%.d,$(objects))
+DEP_FILES := $(wildcard $(DEP_FILES))
+
+#判断依赖文件是否存在
+ifneq ($(DEP_FILES),)
+#如果存在依赖文件，需要导入依赖文件
+include $(DEP_FILES)
+endif
+
+#编译参数
+#指定头文件的路径
+CFLAGS = $(patsubst %, -I%, $(inc_dir)) -MD -MF $(@D)/.$(@F).d
+
+#链接过程
+$(build_dir)/$(Target) : $(objects)  | create_build
+	$(CC) $^ -o $@
+
+#编译工程
+#编译src文件夹中的源文件，并将生成的目标文件放在objs文件夹中
+$(build_dir)/%.o : $(src_dir)/%.c $(includes) | create_build
+	$(CC) -c $(CFLAGS) $< -o $@
+
+
+#以下为伪目标，调用方式：make 伪目标
+#clean：用于Clean Project
+#check：用于检查某个变量的值
+.PHONY:clean cleanall check create_build
+#按架构删除
+clean:
+	rm -rf $(build_dir)
+
+#全部删除
+cleanall:
+	rm -rf build_x86 build_arm
+
+#命令前带"@",表示不在终端上输出执行的命令
+#这个目标主要是用来调试Makefile时输出一些内容
+check:
+	@echo $(CFLAGS)
+	@echo $(CURDIR)
+	@echo $(src_dir)
+	@echo $(sources)
+	@echo $(objects)
+
+
+#创建一个新目录create，用于存放过程文件
+create_build:
+	@mkdir -p $(build_dir)
+
+
diff --git a/base_code/system_programing/exec/sources/exce.c b/base_code/system_programing/exec/sources/exce.c
new file mode 100644
index 0000000000000000000000000000000000000000..0f50d316287fbfdb0d2f81e81dc3d5455628bbad
--- /dev/null
+++ b/base_code/system_programing/exec/sources/exce.c
@@ -0,0 +1,159 @@
+/** exec 函数族 */
+
+/**
+ * exec 函数族就提供了一个在进程中启动另一个程序执行的方法。它可以根据指定的文件名或
+ * 目录名找到可执行文件，并用它来取代原调用进程的数据段、代码段和堆栈段，在执行完之后，原调用进
+ * 程的内容除了进程号外，其他全部被新的进程替换了。另外，这里的可执行文件既可以是二进制文件，也
+ * 可以是 Linux 下任何可执行的脚本文件。
+ * 
+ * 在 Linux 中使用 exec 函数族主要有两种情况。
+ *    当进程认为自己不能再为系统和用户做出任何贡献时， 就可以调用 exec 函数族中的任意一个函数让自己重生。
+ *    如果一个进程想执行另一个程序，那么它就可以调用 fork()函数新建一个进程，然后调用 exec 函
+ *     数族中的任意一个函数，这样看起来就像通过执行应用程序而产生了一个新进程（这种情况非常普遍）。 
+ * 
+ */
+
+/**
+ * ************************** exec 函数族成员函数语法 *****************************
+ * 所需头文件 #include <unistd.h>
+ * 函数原型
+ * int execl(const char *path, const char *arg, ...)
+ * int execv(const char *path, char *const argv[])
+ * int execle(const char *path, const char *arg, ..., char *const envp[])
+ * int execve(const char *path, char *const argv[], char *const envp[])
+ * int execlp(const char *file, const char *arg, ...)
+ * int execvp(const char *file, char *const argv[])
+ * 函数返回值 -1：出错 
+ */
+
+
+#include <unistd.h>
+#include <stdio.h>
+#include <stdlib.h>
+
+#define     EXECL   1
+#define     EXECLP  0
+#define     EXECLE  0
+#define     EXECV   0
+#define     EXECVP  0
+#define     EXECVE  0
+
+#if ((EXECL | EXECLP | EXECLE | EXECV | EXECVP | EXECVE) == 0)
+#error "must choose a function to compile!"
+#endif
+
+#if ((EXECL & EXECLP) || (EXECL & EXECLE) || (EXECL & EXECV) || (EXECL & EXECVP) || (EXECL & EXECVE) || \
+    (EXECLP & EXECLE) || (EXECLP & EXECV) || (EXECLP & EXECVP) || (EXECLP & EXECVE) || \
+    (EXECLE & EXECV) || (EXECLE & EXECVP) || (EXECLE & EXECVE) || \
+    (EXECV & EXECVP) || (EXECV & EXECVE) || \
+    (EXECVP & EXECVE))
+#error "have and can only choose one of the functions to compile"
+#endif
+
+
+#if EXECL
+int main(void)
+{
+    int err;
+
+    printf("this is a execl function test demo!\n\n");
+
+    err = execl("/bin/ls", "ls", "-la", NULL);
+
+    if (err < 0) {
+        printf("execl fail!\n\n");
+    }
+    
+    printf("Done!\n\n");
+}
+#endif
+
+#if EXECLP
+int main(void)
+{
+    int err;
+
+    printf("this is a execlp function test demo!\n\n");
+
+    err = execlp("ls", "ls", "-la", NULL);
+
+    if (err < 0) {
+        printf("execlp fail!\n\n");
+    }
+}
+#endif
+
+#if EXECLE
+int main(void)
+{
+    int err;
+    char *envp[] = {
+        "/bin", NULL
+    };
+
+    printf("this is a execle function test demo!\n\n");
+
+    err = execle("/bin/ls", "ls", "-la", NULL, envp);
+
+    if (err < 0) {
+        printf("execle fail!\n\n");
+    }
+}
+#endif
+
+#if EXECV
+int main(void)
+{
+    int err;
+    char *argv[] = {
+        "ls", "-la", NULL
+    };
+
+    printf("this is a execv function test demo!\n\n");
+
+    err = execv("/bin/ls", argv);
+
+    if (err < 0) {
+        printf("execv fail!\n\n");
+    }
+}
+#endif
+
+#if EXECVP
+int main(void)
+{
+    int err;
+    char *argv[] = {
+        "ls", "-la", NULL
+    };
+
+    printf("this is a execvp function test demo!\n\n");
+
+    err = execvp("ls", argv);
+
+    if (err < 0) {
+        printf("execvp fail!\n\n");
+    }
+}
+#endif
+
+#if EXECVE
+int main(void)
+{
+    int err;
+    char *argv[] = {
+        "ls", "-la", NULL
+    };
+    char *envp[] = {
+        "/bin", NULL
+    };
+
+    printf("this is a execve function test demo!\n\n");
+
+    err = execve("/bin/ls", argv, envp);
+
+    if (err < 0) {
+        printf("execve fail!\n\n");
+    }
+}
+#endif
\ No newline at end of file
diff --git a/base_code/system_programing/fifo/Makefile b/base_code/system_programing/fifo/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..c88f8362abdc339f558044d7f20f3bd6ba980aed
--- /dev/null
+++ b/base_code/system_programing/fifo/Makefile
@@ -0,0 +1,78 @@
+
+#生成可执行文件的名称
+Target = fifo_demo
+ARCH ?= x86
+#编译器CC
+#根据传入的参数ARCH，确定使用的编译器
+#默认使用gcc编译器
+#make ARCH=arm 时使用ARM-GCC编译器
+ifeq ($(ARCH), x86)
+	CC = gcc
+else
+	CC = arm-linux-gnueabihf-gcc
+endif
+#存放中间文件的路径
+build_dir = build_$(ARCH)
+#存放源文件的文件夹
+src_dir =  sources
+#存放头文件的文件夹
+inc_dir = includes .
+
+#源文件
+sources = $(foreach dir,$(src_dir),$(wildcard $(dir)/*.c))
+#目标文件（*.o）
+objects = $(patsubst %.c,$(build_dir)/%.o,$(notdir $(sources)))
+#头文件
+includes = $(foreach dir,$(inc_dir),$(wildcard $(dir)/*.h))
+
+#目标依赖文件
+DEP_FILES := $(patsubst %, .%.d,$(objects))
+DEP_FILES := $(wildcard $(DEP_FILES))
+
+#判断依赖文件是否存在
+ifneq ($(DEP_FILES),)
+#如果存在依赖文件，需要导入依赖文件
+include $(DEP_FILES)
+endif
+
+#编译参数
+#指定头文件的路径
+CFLAGS = $(patsubst %, -I%, $(inc_dir)) -MD -MF $(@D)/.$(@F).d
+
+#链接过程
+$(build_dir)/$(Target) : $(objects)  | create_build
+	$(CC) $^ -o $@
+
+#编译工程
+#编译src文件夹中的源文件，并将生成的目标文件放在objs文件夹中
+$(build_dir)/%.o : $(src_dir)/%.c $(includes) | create_build
+	$(CC) -c $(CFLAGS) $< -o $@
+
+
+#以下为伪目标，调用方式：make 伪目标
+#clean：用于Clean Project
+#check：用于检查某个变量的值
+.PHONY:clean cleanall check create_build
+#按架构删除
+clean:
+	rm -rf $(build_dir)
+
+#全部删除
+cleanall:
+	rm -rf build_x86 build_arm
+
+#命令前带"@",表示不在终端上输出执行的命令
+#这个目标主要是用来调试Makefile时输出一些内容
+check:
+	@echo $(CFLAGS)
+	@echo $(CURDIR)
+	@echo $(src_dir)
+	@echo $(sources)
+	@echo $(objects)
+
+
+#创建一个新目录create，用于存放过程文件
+create_build:
+	@mkdir -p $(build_dir)
+
+
diff --git a/base_code/system_programing/fifo/sources/fifo.c b/base_code/system_programing/fifo/sources/fifo.c
new file mode 100644
index 0000000000000000000000000000000000000000..6d7cac903dbc2cf58e6c58a85bf176e425483278
--- /dev/null
+++ b/base_code/system_programing/fifo/sources/fifo.c
@@ -0,0 +1,150 @@
+/**fifo.c */
+
+/**
+ * 无名管道，它只能用于具有亲缘关系的进程之间，这就大大地限制了管道的使用。有名管道的出现突破了这种限制， 它可以使互不相关的两个进程实现彼此通信。 
+ * 该管道可以通过路径名来指出，并且在文件系统中是可见的。在建立了管道之后，两个进程就可以把它当作普通文件一样进行读写操作，使用非常方便。
+ * 不过 FIFO 是严格地遵循先进先出规则的，对管道及 FIFO 的读总是从开始处返回数据，对它们的写则把数据添加到末尾，它们不支持如 lseek()等文件定位操作。
+ * 有名管道的创建可以使用函数 mkfifo()，该函数类似文件中的 open()操作，可以指定管道的路径和打开的模式
+ * 
+ * 在创建管道成功之后，就可以使用 open()、 read()和 write()这些函数了。与普通文件的开发设置一样，对于为读而打开的管道可在 open()中设置 O_RDONLY，
+ * 对于为写而打开的管道可在 open()中设置 O_WRONLY，在这里与普通文件不同的是阻塞问题。由于普通文件的读写时不会出现阻塞问题，而在管道的读写中却有阻塞的可能，
+ * 这里的非阻塞标志可以在 open()函数中设定为 O_NONBLOCK。下面分别对阻塞打开和非阻塞打开的读写进行讨论。
+ * （1）对于读进程。
+ *       若该管道是阻塞打开，且当前 FIFO 内没有数据，则对读进程而言将一直阻塞到有数据写入。
+ *       若该管道是非阻塞打开，则不论 FIFO 内是否有数据，读进程都会立即执行读操作。即如果 FIFO内没有数据，则读函数将立刻返回 0。
+ * （2）对于写进程。
+ *       若该管道是阻塞打开，则写操作将一直阻塞到数据可以被写入。
+ *       若该管道是非阻塞打开而不能写入全部数据，则读操作进行部分写入或者调用失败
+ * 
+ * 函数原型 int mkfifo(const char *filename,mode_t mode)
+ * 函数传入值 filename：要创建的管道名字(包含路径)
+ * 函数传入值 mode：
+ *       O_RDONLY：读管道
+ *       O_WRONLY：写管道
+ *       O_RDWR：读写管道
+ *       O_NONBLOCK：非阻塞
+ *       O_CREAT：如果该文件不存在，那么就创建一个新的文件，并用第三个参数为其设置权限
+ *       O_EXCL：如果使用 O_CREAT 时文件存在，那么可返回错误消息。这一参数可测试文件是否存在
+ * 函数返回值：
+ *       0：成功
+ *       EACCESS：参数 filename 所指定的目录路径无可执行的权限
+ *       EEXIST：参数 filename 所指定的文件已存在
+ *       ENAMETOOLONG：参数 filename 的路径名称太长
+ *       ENOENT：参数 filename 包含的目录不存在
+ *       ENOSPC：文件系统的剩余空间不足
+ *       ENOTDIR：参数 filename 路径中的目录存在但却非真正的目录
+ *       EROFS：参数 filename 指定的文件存在于只读文件系统内
+ */
+#include <sys/wait.h>
+#include <sys/types.h>
+#include <sys/stat.h>
+#include <unistd.h>
+#include <errno.h>
+#include <fcntl.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <limits.h>
+#include <string.h>
+
+
+#define MYFIFO "myfifo"    /* 有名管道文件名*/
+
+#define MAX_BUFFER_SIZE PIPE_BUF /* 4096 定义在于 limits.h 中*/
+
+
+void fifo_read(void)
+{
+    char buff[MAX_BUFFER_SIZE];
+    int fd;
+    int nread;
+
+    printf("***************** read fifo ************************\n");
+    /* 判断有名管道是否已存在，若尚未创建，则以相应的权限创建*/
+    if (access(MYFIFO, F_OK) == -1)
+    {
+        if ((mkfifo(MYFIFO, 0666) < 0) && (errno != EEXIST))
+        {
+            printf("Cannot create fifo file\n");
+            exit(1);
+        }
+    }
+
+    /* 以只读阻塞方式打开有名管道 */
+    fd = open(MYFIFO, O_RDONLY);
+    if (fd == -1)
+    {
+        printf("Open fifo file error\n");
+        exit(1);
+    }
+
+    memset(buff, 0, sizeof(buff));
+
+    if ((nread = read(fd, buff, MAX_BUFFER_SIZE)) > 0)
+    {
+        printf("Read '%s' from FIFO\n", buff);
+    }
+
+   printf("***************** close fifo ************************\n");
+
+    close(fd);
+
+    exit(0);
+}
+
+
+void write_fifo(void)
+{
+    int fd;
+    char buff[] = "this is a fifo test demo";
+    int nwrite;
+
+    sleep(2);   //等待子进程先运行
+
+    /* 以只写阻塞方式打开 FIFO 管道 */
+    fd = open(MYFIFO, O_WRONLY | O_CREAT, 0644);
+    if (fd == -1)
+    {
+        printf("Open fifo file error\n");
+        exit(1);
+    }
+
+    printf("Write '%s' to FIFO\n", buff);
+    /*向管道中写入字符串*/
+    nwrite = write(fd, buff, MAX_BUFFER_SIZE);
+    
+    if(wait(NULL))  //等待子进程退出
+    {
+        close(fd);
+        exit(0);
+    }
+
+}
+
+
+int main()
+{
+    pid_t result;
+    /*调用 fork()函数*/
+    result = fork();
+
+    /*通过 result 的值来判断 fork()函数的返回情况，首先进行出错处理*/
+    if(result == -1)
+    {
+        printf("Fork error\n");
+    }
+
+
+    else if (result == 0) /*返回值为 0 代表子进程*/
+    {
+        fifo_read();
+    }
+
+    else /*返回值大于 0 代表父进程*/
+    {
+        write_fifo();
+    }
+
+    return result;
+}
+
+
diff --git a/base_code/system_programing/file/Makefile b/base_code/system_programing/file/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..fdccb9556a544cdbc81571e62c33300cf86bcd28
--- /dev/null
+++ b/base_code/system_programing/file/Makefile
@@ -0,0 +1,78 @@
+
+#生成可执行文件的名称
+Target = file_demo
+ARCH ?= x86
+#编译器CC
+#根据传入的参数ARCH，确定使用的编译器
+#默认使用gcc编译器
+#make ARCH=arm 时使用ARM-GCC编译器
+ifeq ($(ARCH), x86)
+	CC = gcc
+else
+	CC = arm-linux-gnueabihf-gcc
+endif
+#存放中间文件的路径
+build_dir = build_$(ARCH)
+#存放源文件的文件夹
+src_dir =  sources
+#存放头文件的文件夹
+inc_dir = includes .
+
+#源文件
+sources = $(foreach dir,$(src_dir),$(wildcard $(dir)/*.c))
+#目标文件（*.o）
+objects = $(patsubst %.c,$(build_dir)/%.o,$(notdir $(sources)))
+#头文件
+includes = $(foreach dir,$(inc_dir),$(wildcard $(dir)/*.h))
+
+#目标依赖文件
+DEP_FILES := $(patsubst %, .%.d,$(objects))
+DEP_FILES := $(wildcard $(DEP_FILES))
+
+#判断依赖文件是否存在
+ifneq ($(DEP_FILES),)
+#如果存在依赖文件，需要导入依赖文件
+include $(DEP_FILES)
+endif
+
+#编译参数
+#指定头文件的路径
+CFLAGS = $(patsubst %, -I%, $(inc_dir)) -MD -MF $(@D)/.$(@F).d
+
+#链接过程
+$(build_dir)/$(Target) : $(objects)  | create_build
+	$(CC) $^ -o $@
+
+#编译工程
+#编译src文件夹中的源文件，并将生成的目标文件放在objs文件夹中
+$(build_dir)/%.o : $(src_dir)/%.c $(includes) | create_build
+	$(CC) -c $(CFLAGS) $< -o $@
+
+
+#以下为伪目标，调用方式：make 伪目标
+#clean：用于Clean Project
+#check：用于检查某个变量的值
+.PHONY:clean cleanall check create_build
+#按架构删除
+clean:
+	rm -rf $(build_dir)
+
+#全部删除
+cleanall:
+	rm -rf build_x86 build_arm
+
+#命令前带"@",表示不在终端上输出执行的命令
+#这个目标主要是用来调试Makefile时输出一些内容
+check:
+	@echo $(CFLAGS)
+	@echo $(CURDIR)
+	@echo $(src_dir)
+	@echo $(sources)
+	@echo $(objects)
+
+
+#创建一个新目录create，用于存放过程文件
+create_build:
+	@mkdir -p $(build_dir)
+
+
diff --git a/base_code/system_programing/file/sources/dest_file b/base_code/system_programing/file/sources/dest_file
new file mode 100644
index 0000000000000000000000000000000000000000..61e018eff1562451c616968657c409b0ba44098e
--- /dev/null
+++ b/base_code/system_programing/file/sources/dest_file
@@ -0,0 +1,17 @@
+蔡杰，一个梦想成为物联网全栈开发工
+程师的应届毕业生，从大三暑假参加工作至
+今（2018.07-2019.06），有扎实的专业基
+础，在校期间多次参加电子专业相关比赛，
+并且担任信息工程学院单片机协会会长一
+职，管理单片机协会实验室，带领师弟师妹
+学习单片机相关知识，经常逛论坛、看博客、
+写文章，乐亍分享与交流，在 21ic 中国电
+子网、意法半导体 stm32 中文社区、融创
+芯城等论坛担任版主。 热衷亍技术，眼界开
+阔，对编程软件方面技术有浓厚的兴趣，既
+能独立完成任务也能与团队配合完成任务。
+
+电话：130 6856 5173
+邮箱：jiejietop@gmail.com
+博客：https://blog.csdn.net/jiejiemcu
+GitHub：https://github.com/jiejieTop
diff --git a/base_code/system_programing/file/sources/file.c b/base_code/system_programing/file/sources/file.c
new file mode 100644
index 0000000000000000000000000000000000000000..cf63ba3b798aaf270f1409269bedfa860433e694
--- /dev/null
+++ b/base_code/system_programing/file/sources/file.c
@@ -0,0 +1,82 @@
+/* copy_file.c */
+#include <unistd.h>
+#include <sys/types.h>
+#include <sys/stat.h>
+#include <fcntl.h>
+#include <stdlib.h>
+#include <stdio.h>
+
+#define BUFFER_SIZE 1024 /* 每次读写缓存大小，影响运行效率*/
+
+#define SRC_FILE_NAME "src_file" /* 源文件名 */
+
+#define DEST_FILE_NAME "dest_file" /* 目标文件名文件名 */
+
+#define OFFSET 	10240 /* 复制的数据大小 */
+
+
+int main(void)
+{
+	int src_file, dest_file;	/* 文件描述符 */
+	
+	unsigned char buff[BUFFER_SIZE];
+	
+	int real_read_len;
+	
+	printf("open src_file with read only\n");
+	/* 以只读方式打开源文件 */
+	src_file = open(SRC_FILE_NAME, O_RDONLY);
+	
+	printf("open dest_file with write only\n");
+	/* 以只写方式打开目标文件，若此文件不存在则创建该文件, 访问权限值为 644 */
+	dest_file = open(DEST_FILE_NAME, O_WRONLY|O_CREAT, S_IRUSR|S_IWUSR|S_IRGRP|S_IROTH);
+	
+	if (src_file < 0 || dest_file < 0)
+	{
+		printf("Open file error\n");
+		exit(1);
+	}
+	
+	printf("move pointer to file end\n");
+	/* 将源文件的读写指针移到最后 10KB 的起始位置*/
+	lseek(src_file, -OFFSET, SEEK_END);
+	
+	/* 读取源文件的最后 10KB 数据并写到目标文件中，每次读写 1KB */
+	while ((real_read_len = read(src_file, buff, sizeof(buff))) > 0)
+	{
+		printf("write data to dest_file\n");
+		write(dest_file, buff, real_read_len);
+	}
+	
+	/** 同步文件 */
+	if(fsync(dest_file) == 0)
+	{
+		printf("wait all data write to the dest_file\n");
+		close(dest_file);
+		close(src_file);
+	}
+
+	/** 开始读取目标文件 */
+	printf("start read dest_file\n");
+	printf("*****************************************\n");
+
+	dest_file = open(DEST_FILE_NAME, O_RDONLY);
+	if(dest_file < 0)
+	{
+		printf("open dest_file fail\n");
+		exit(1);
+	}
+
+	/* 将目标文件的读写指针移到开始 */
+	lseek(dest_file, 0, SEEK_SET);
+
+	/** 读取数据并且打印出来 */
+	while ((real_read_len = read(src_file, buff, sizeof(buff))) > 0)
+	{
+		printf("%s",buff);
+	}
+
+	printf("*****************************************\n");
+
+	return 0;
+}
\ No newline at end of file
diff --git a/base_code/system_programing/file/sources/log b/base_code/system_programing/file/sources/log
new file mode 100644
index 0000000000000000000000000000000000000000..9536958ee3f0904b5992ca881f0db8a4c36e1f0f
--- /dev/null
+++ b/base_code/system_programing/file/sources/log
@@ -0,0 +1,25 @@
+open src_file with read only
+open dest_file with write only
+move pointer to file end
+write data to dest_file
+wait all data write to the dest_file
+start read dest_file
+*****************************************
+蔡杰，一个梦想成为物联网全栈开发工
+程师的应届毕业生，从大三暑假参加工作至
+今（2018.07-2019.06），有扎实的专业基
+础，在校期间多次参加电子专业相关比赛，
+并且担任信息工程学院单片机协会会长一
+职，管理单片机协会实验室，带领师弟师妹
+学习单片机相关知识，经常逛论坛、看博客、
+写文章，乐亍分享与交流，在 21ic 中国电
+子网、意法半导体 stm32 中文社区、融创
+芯城等论坛担任版主。 热衷亍技术，眼界开
+阔，对编程软件方面技术有浓厚的兴趣，既
+能独立完成任务也能与团队配合完成任务。
+
+电话：130 6856 5173
+邮箱：jiejietop@gmail.com
+博客：https://blog.csdn.net/jiejiemcu
+GitHub：https://github.com/jiejieTop
+*****************************************
diff --git a/base_code/system_programing/file/sources/src_file b/base_code/system_programing/file/sources/src_file
new file mode 100644
index 0000000000000000000000000000000000000000..61e018eff1562451c616968657c409b0ba44098e
--- /dev/null
+++ b/base_code/system_programing/file/sources/src_file
@@ -0,0 +1,17 @@
+蔡杰，一个梦想成为物联网全栈开发工
+程师的应届毕业生，从大三暑假参加工作至
+今（2018.07-2019.06），有扎实的专业基
+础，在校期间多次参加电子专业相关比赛，
+并且担任信息工程学院单片机协会会长一
+职，管理单片机协会实验室，带领师弟师妹
+学习单片机相关知识，经常逛论坛、看博客、
+写文章，乐亍分享与交流，在 21ic 中国电
+子网、意法半导体 stm32 中文社区、融创
+芯城等论坛担任版主。 热衷亍技术，眼界开
+阔，对编程软件方面技术有浓厚的兴趣，既
+能独立完成任务也能与团队配合完成任务。
+
+电话：130 6856 5173
+邮箱：jiejietop@gmail.com
+博客：https://blog.csdn.net/jiejiemcu
+GitHub：https://github.com/jiejieTop
diff --git a/base_code/system_programing/file_lock/Makefile b/base_code/system_programing/file_lock/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..5a52f310a4d9ffdbd258b1a650fbf65c41f734d4
--- /dev/null
+++ b/base_code/system_programing/file_lock/Makefile
@@ -0,0 +1,78 @@
+
+#生成可执行文件的名称
+Target = file_lock_demo
+ARCH ?= x86
+#编译器CC
+#根据传入的参数ARCH，确定使用的编译器
+#默认使用gcc编译器
+#make ARCH=arm 时使用ARM-GCC编译器
+ifeq ($(ARCH), x86)
+	CC = gcc
+else
+	CC = arm-linux-gnueabihf-gcc
+endif
+#存放中间文件的路径
+build_dir = build_$(ARCH)
+#存放源文件的文件夹
+src_dir =  sources
+#存放头文件的文件夹
+inc_dir = includes .
+
+#源文件
+sources = $(foreach dir,$(src_dir),$(wildcard $(dir)/*.c))
+#目标文件（*.o）
+objects = $(patsubst %.c,$(build_dir)/%.o,$(notdir $(sources)))
+#头文件
+includes = $(foreach dir,$(inc_dir),$(wildcard $(dir)/*.h))
+
+#目标依赖文件
+DEP_FILES := $(patsubst %, .%.d,$(objects))
+DEP_FILES := $(wildcard $(DEP_FILES))
+
+#判断依赖文件是否存在
+ifneq ($(DEP_FILES),)
+#如果存在依赖文件，需要导入依赖文件
+include $(DEP_FILES)
+endif
+
+#编译参数
+#指定头文件的路径
+CFLAGS = $(patsubst %, -I%, $(inc_dir)) -MD -MF $(@D)/.$(@F).d
+
+#链接过程
+$(build_dir)/$(Target) : $(objects)  | create_build
+	$(CC) $^ -o $@
+
+#编译工程
+#编译src文件夹中的源文件，并将生成的目标文件放在objs文件夹中
+$(build_dir)/%.o : $(src_dir)/%.c $(includes) | create_build
+	$(CC) -c $(CFLAGS) $< -o $@
+
+
+#以下为伪目标，调用方式：make 伪目标
+#clean：用于Clean Project
+#check：用于检查某个变量的值
+.PHONY:clean cleanall check create_build
+#按架构删除
+clean:
+	rm -rf $(build_dir)
+
+#全部删除
+cleanall:
+	rm -rf build_x86 build_arm
+
+#命令前带"@",表示不在终端上输出执行的命令
+#这个目标主要是用来调试Makefile时输出一些内容
+check:
+	@echo $(CFLAGS)
+	@echo $(CURDIR)
+	@echo $(src_dir)
+	@echo $(sources)
+	@echo $(objects)
+
+
+#创建一个新目录create，用于存放过程文件
+create_build:
+	@mkdir -p $(build_dir)
+
+
diff --git a/base_code/system_programing/file_lock/sources/file_lock.c b/base_code/system_programing/file_lock/sources/file_lock.c
new file mode 100644
index 0000000000000000000000000000000000000000..153089367bd708fa300de04c8d44ae6d0e7d3dd5
--- /dev/null
+++ b/base_code/system_programing/file_lock/sources/file_lock.c
@@ -0,0 +1,179 @@
+#include <sys/types.h>
+#include <unistd.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <fcntl.h>
+
+int lock_set(int fd, int type);
+
+int main(void)
+{
+    int fd;
+    pid_t result;
+
+    fd = open("hello", O_RDWR | O_CREAT, 0644);
+    if (fd < 0)
+    {
+        printf("open file error!\n");
+        exit(1);
+    }
+
+    result = fork();
+
+    if(result == -1)
+    {
+        perror("fork");
+        exit(1);
+    }
+
+    else if(result == 0)    /** 这是一个子进程 */
+    {
+        printf("this is a  chiad process,pid is %d!\n",getpid());
+
+        lock_set(fd, F_WRLCK);      /** 给文件上锁 */
+
+        printf("chiad sleep!\n\n");
+        
+        sleep(2);       /** 休眠2S */
+
+        lock_set(fd, F_UNLCK);  /** 解锁 */
+
+        close(fd);
+    }
+
+    else    /** 返回值大于0是父进程 */
+    {
+        printf("this is a  father process,pid is %d!\n",getpid());
+        
+        lock_set(fd, F_WRLCK);      /** 给文件上锁 */
+
+        printf("father wait a keyboard enter to unlock file!\n\n");
+
+        getchar();
+
+        lock_set(fd, F_UNLCK);  /** 解锁 */     
+
+        close(fd);
+    }
+
+    return 0;
+}
+
+
+int lock_set(int fd, int type)
+{
+    struct flock old_lock, lock;
+
+    lock.l_whence = SEEK_SET;
+    lock.l_start = 0;
+    lock.l_len = 0;
+    lock.l_type = type;
+    lock.l_pid = -1;
+
+    /* 判断文件是否可以上锁 */
+    fcntl(fd, F_GETLK, &lock);
+
+    if (lock.l_type != F_UNLCK)
+    {
+        /* 判断文件不能上锁的原因 */
+        if (lock.l_type == F_RDLCK) /* 该文件已有读取锁 */
+        {
+            printf("Read lock already set by %d\n", lock.l_pid);
+        }
+
+        else if (lock.l_type == F_WRLCK) /* 该文件已有写入锁 */
+        {
+            printf("Write lock already set by %d\n", lock.l_pid);
+        }
+    }
+
+    /* l_type 可能已被 F_GETLK 修改过 */
+    lock.l_type = type;
+
+    /* 根据不同的 type 值进行阻塞式上锁或解锁 */
+    if ((fcntl(fd, F_SETLKW, &lock)) < 0)
+    {
+        printf("Lock failed:type = %d\n", lock.l_type);
+        return 1;
+    }
+
+    switch(lock.l_type)
+    {
+        case F_RDLCK:
+        {
+            printf("Read lock set by %d\n", getpid());break;
+        }
+            
+        case F_WRLCK:
+        {
+            printf("Write lock set by %d\n", getpid());break;
+        }
+            
+        case F_UNLCK:
+        {
+            printf("Release lock by %d\n", getpid());
+            return 1;   break;
+        }
+        
+        default:
+            break;
+    }/* end of switch */
+
+    return 0;
+}
+
+
+
+
+
+
+
+
+// int main(void)
+// {
+//     int fd;
+
+//     pid_t result;
+//     /*调用 fork()函数*/
+
+//     fd = open("hello", O_RDWR | O_CREAT, 0644);
+//     if (fd < 0)
+//     {
+//         printf("open file error!\n");
+//         exit(1);
+//     }
+
+//     result = fork();
+//     /*通过 result 的值来判断 fork()函数的返回情况，首先进行出错处理*/
+//     if(result == -1)
+//     {
+//         printf("Fork error\n");
+//     }
+//     else if (result == 0) /*返回值为 0 代表子进程*/
+//     {
+//         printf("The returned value is %d\nIn child process!!\nMy PID is %d\n",result,getpid());
+
+//         printf("this is child\n");
+
+//         lock_set(fd, F_WRLCK);  /** 给文件上锁 */
+
+//         getchar();
+
+//         lock_set(fd, F_UNLCK);  /** 解锁 */     
+
+//     }
+
+//     else /*返回值大于 0 代表父进程*/
+//     {
+//         printf("The returned value is %d\nIn father process!!\nMy PID is %d\n",result,getpid());
+
+//         printf("this is father\n");
+
+//         lock_set(fd, F_WRLCK);  /** 给文件上锁 */
+
+//         sleep(1);
+
+//         lock_set(fd, F_UNLCK);  /** 解锁 */  
+//     }
+//     return result;
+// }
\ No newline at end of file
diff --git a/base_code/system_programing/fork/Makefile b/base_code/system_programing/fork/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..a8143dc3585ba6a947dbc4f44c3cc25ba53d2de1
--- /dev/null
+++ b/base_code/system_programing/fork/Makefile
@@ -0,0 +1,78 @@
+
+#生成可执行文件的名称
+Target = fork_demo
+ARCH ?= x86
+#编译器CC
+#根据传入的参数ARCH，确定使用的编译器
+#默认使用gcc编译器
+#make ARCH=arm 时使用ARM-GCC编译器
+ifeq ($(ARCH), x86)
+	CC = gcc
+else
+	CC = arm-linux-gnueabihf-gcc
+endif
+#存放中间文件的路径
+build_dir = build_$(ARCH)
+#存放源文件的文件夹
+src_dir =  sources
+#存放头文件的文件夹
+inc_dir = includes .
+
+#源文件
+sources = $(foreach dir,$(src_dir),$(wildcard $(dir)/*.c))
+#目标文件（*.o）
+objects = $(patsubst %.c,$(build_dir)/%.o,$(notdir $(sources)))
+#头文件
+includes = $(foreach dir,$(inc_dir),$(wildcard $(dir)/*.h))
+
+#目标依赖文件
+DEP_FILES := $(patsubst %, .%.d,$(objects))
+DEP_FILES := $(wildcard $(DEP_FILES))
+
+#判断依赖文件是否存在
+ifneq ($(DEP_FILES),)
+#如果存在依赖文件，需要导入依赖文件
+include $(DEP_FILES)
+endif
+
+#编译参数
+#指定头文件的路径
+CFLAGS = $(patsubst %, -I%, $(inc_dir)) -MD -MF $(@D)/.$(@F).d
+
+#链接过程
+$(build_dir)/$(Target) : $(objects)  | create_build
+	$(CC) $^ -o $@
+
+#编译工程
+#编译src文件夹中的源文件，并将生成的目标文件放在objs文件夹中
+$(build_dir)/%.o : $(src_dir)/%.c $(includes) | create_build
+	$(CC) -c $(CFLAGS) $< -o $@
+
+
+#以下为伪目标，调用方式：make 伪目标
+#clean：用于Clean Project
+#check：用于检查某个变量的值
+.PHONY:clean cleanall check create_build
+#按架构删除
+clean:
+	rm -rf $(build_dir)
+
+#全部删除
+cleanall:
+	rm -rf build_x86 build_arm
+
+#命令前带"@",表示不在终端上输出执行的命令
+#这个目标主要是用来调试Makefile时输出一些内容
+check:
+	@echo $(CFLAGS)
+	@echo $(CURDIR)
+	@echo $(src_dir)
+	@echo $(sources)
+	@echo $(objects)
+
+
+#创建一个新目录create，用于存放过程文件
+create_build:
+	@mkdir -p $(build_dir)
+
+
diff --git a/base_code/system_programing/fork/sources/fork.c b/base_code/system_programing/fork/sources/fork.c
new file mode 100644
index 0000000000000000000000000000000000000000..bb9f58f024ee677f2ae7c68dfbf5bc049d5035d7
--- /dev/null
+++ b/base_code/system_programing/fork/sources/fork.c
@@ -0,0 +1,50 @@
+/* fork.c */
+
+/** 
+ * fork()函数用于从已存在的进程中创建一个新进程。新进程称为子进程，而原进程称为父进程。使用fork()
+ * 函数得到的子进程是父进程的一个复制品，它从父进程处继承了整个进程的地址空间，包括进程上下文、
+ * 代码段、进程堆栈、内存信息、打开的文件描述符、信号控制设定、进程优先级、进程组号、当前工作目
+ * 录、根目录、资源限制和控制终端等，而子进程所独有的只有它的进程号、资源使用和计时器等。 
+ * 因为子进程几乎是父进程的完全复制，所以父子两个进程会运行同一个程序。
+ * 
+ * 在父进程中执行 fork()函数时，父进程会复制出一个子进程，而且父子进程的代码从fork()函数的
+ * 返回开始分别在两个地址空间中同时运行。从而两个进程分别获得其所属fork()的返回值，其中在父进程
+ * 中的返回值是子进程的进程号，而在子进程中返回 0 
+ */
+
+#include <sys/types.h>
+#include <unistd.h>
+#include <stdio.h>
+#include <stdlib.h>
+int main(void)
+{
+    pid_t result;
+
+    printf("This is a fork demo!\n\n");
+
+    /*调用 fork()函数*/
+    result = fork();
+
+    /*通过 result 的值来判断 fork()函数的返回情况，首先进行出错处理*/
+    if(result == -1) {
+        printf("Fork error\n");
+    }
+
+    /*返回值为 0 代表子进程*/
+    else if (result == 0) {
+        printf("The returned value is %d, In child process!! My PID is %d\n\n", result, getpid());
+
+    }
+
+    /*返回值大于 0 代表父进程*/
+    else {
+        printf("The returned value is %d, In father process!! My PID is %d\n\n", result, getpid());
+    }
+
+    return result;
+}
+
+
+
+
+
diff --git a/base_code/system_programing/input/Makefile b/base_code/system_programing/input/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..0a8afc1aecbb7def7d1d6e26c2d49835141a397e
--- /dev/null
+++ b/base_code/system_programing/input/Makefile
@@ -0,0 +1,78 @@
+
+#生成可执行文件的名称
+Target = input_demo
+ARCH ?= x86
+#编译器CC
+#根据传入的参数ARCH，确定使用的编译器
+#默认使用gcc编译器
+#make ARCH=arm 时使用ARM-GCC编译器
+ifeq ($(ARCH), x86)
+	CC = gcc
+else
+	CC = arm-linux-gnueabihf-gcc
+endif
+#存放中间文件的路径
+build_dir = build_$(ARCH)
+#存放源文件的文件夹
+src_dir =  sources
+#存放头文件的文件夹
+inc_dir = includes .
+
+#源文件
+sources = $(foreach dir,$(src_dir),$(wildcard $(dir)/*.c))
+#目标文件（*.o）
+objects = $(patsubst %.c,$(build_dir)/%.o,$(notdir $(sources)))
+#头文件
+includes = $(foreach dir,$(inc_dir),$(wildcard $(dir)/*.h))
+
+#目标依赖文件
+DEP_FILES := $(patsubst %, .%.d,$(objects))
+DEP_FILES := $(wildcard $(DEP_FILES))
+
+#判断依赖文件是否存在
+ifneq ($(DEP_FILES),)
+#如果存在依赖文件，需要导入依赖文件
+include $(DEP_FILES)
+endif
+
+#编译参数
+#指定头文件的路径
+CFLAGS = $(patsubst %, -I%, $(inc_dir)) -MD -MF $(@D)/.$(@F).d
+
+#链接过程
+$(build_dir)/$(Target) : $(objects)  | create_build
+	$(CC) $^ -o $@
+
+#编译工程
+#编译src文件夹中的源文件，并将生成的目标文件放在objs文件夹中
+$(build_dir)/%.o : $(src_dir)/%.c $(includes) | create_build
+	$(CC) -c $(CFLAGS) $< -o $@
+
+
+#以下为伪目标，调用方式：make 伪目标
+#clean：用于Clean Project
+#check：用于检查某个变量的值
+.PHONY:clean cleanall check create_build
+#按架构删除
+clean:
+	rm -rf $(build_dir)
+
+#全部删除
+cleanall:
+	rm -rf build_x86 build_arm
+
+#命令前带"@",表示不在终端上输出执行的命令
+#这个目标主要是用来调试Makefile时输出一些内容
+check:
+	@echo $(CFLAGS)
+	@echo $(CURDIR)
+	@echo $(src_dir)
+	@echo $(sources)
+	@echo $(objects)
+
+
+#创建一个新目录create，用于存放过程文件
+create_build:
+	@mkdir -p $(build_dir)
+
+
diff --git a/base_code/system_programing/input/sources/input.c b/base_code/system_programing/input/sources/input.c
new file mode 100644
index 0000000000000000000000000000000000000000..e06abe000d6cd38fdcd40d7882734ff72cd31b51
--- /dev/null
+++ b/base_code/system_programing/input/sources/input.c
@@ -0,0 +1,108 @@
+
+#include <sys/types.h>
+#include <unistd.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#define DEVICES_NUM 10
+#define MAX_LENTH 256
+#define INPUT_FILE "/proc/bus/input/devices"
+#define NAME_LEN 40
+#define HANDLER_LEN 7
+
+typedef struct usb_dev {
+    char name[NAME_LEN];
+    char handler[HANDLER_LEN];
+} usb_dev_t;
+
+typedef struct usb_dev_handler {
+    char handler[HANDLER_LEN];
+} usb_dev_handler_t;
+
+int usb_dev_search(char *path);
+int usb_dev_parsing(char *str, usb_dev_handler_t *handler);
+
+usb_dev_t usb_devices[DEVICES_NUM];
+usb_dev_handler_t handler[2];
+
+int main(void)
+{
+    int line;
+    printf("%ld\n",sizeof(usb_devices));
+    memset(usb_devices,0,sizeof(usb_devices));
+    memset(handler,0,sizeof(handler));
+    line = usb_dev_search(INPUT_FILE);
+    printf("line : %d\n", line);
+    usb_dev_parsing("HDA", handler);
+    // printf("%s\n", usb_dev_parsing("HDA Intel Front Headphone"));
+    exit(0);
+}
+ 
+int usb_dev_search(char *path)
+{
+    int num = 0;
+    int usb_dev_num = 0;
+    char *start;
+    char buffer[MAX_LENTH];
+    
+    memset(usb_devices,0,sizeof(usb_devices));
+
+    FILE *pf = fopen(path,"r");
+    if (pf == NULL) {
+        printf("%s file open file\n", path);
+    }
+
+    while ((fgets(buffer, MAX_LENTH, pf) != NULL)) {
+        if ((start = strstr(buffer, "Name=")) != NULL) {
+            if(strlen(usb_devices[usb_dev_num].name) == 0) {
+                memcpy(usb_devices[usb_dev_num].name, start+5, NAME_LEN-1);
+                usb_devices[usb_dev_num].handler[NAME_LEN-1] = '\0';
+                printf("usb_devices[%d].name = %s", usb_dev_num, usb_devices[usb_dev_num].name);
+            }
+        }
+
+        if ((start = strstr(buffer, "Handlers=")) != NULL) {
+            if ((start = strstr(buffer, "event")) != NULL) {
+                if(strlen(usb_devices[usb_dev_num].handler) == 0) {
+                    memcpy(usb_devices[usb_dev_num].handler, start, HANDLER_LEN-1);
+                    usb_devices[usb_dev_num].handler[HANDLER_LEN-1] = '\0';
+                    printf("usb_devices[%d].handler = %s\n", usb_dev_num, usb_devices[usb_dev_num].handler);
+                }
+            }
+        }
+        if((strlen(usb_devices[usb_dev_num].name) != 0) && (strlen(usb_devices[usb_dev_num].handler) != 0)) {
+            usb_dev_num++;
+            if (usb_dev_num > DEVICES_NUM) {
+                printf("usb_dev_num > DEVICES_NUM");
+                goto ret;
+            }
+        }
+        num++;
+    }
+
+ret:
+    printf("close %s\n", INPUT_FILE);
+    fclose(pf);
+    return num;
+}
+
+int usb_dev_parsing(char *str, usb_dev_handler_t *handler)
+{
+    int i = 0;
+    int h = 0;
+    for (i = 0; i < DEVICES_NUM; i++) {
+        printf("%s", usb_devices[i].name);
+        if (strstr(usb_devices[i].name, str) != NULL) {
+            printf("%s\n", usb_devices[i].handler);
+            // return usb_devices[i].handler;
+            memcpy(handler[h].handler, usb_devices[i].handler,sizeof(usb_devices[i].handler));
+            printf("handler[%d].handler = %s, len: %ld\n", h, handler[h].handler, sizeof(usb_devices[i].handler));
+            h++;
+            if(h >= 2)
+                return h;
+        }
+    }
+    return h;
+}
+
diff --git a/base_code/system_programing/kill/Makefile b/base_code/system_programing/kill/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..80373206380fe298a93a306cce35ae283ec8dda5
--- /dev/null
+++ b/base_code/system_programing/kill/Makefile
@@ -0,0 +1,78 @@
+
+#生成可执行文件的名称
+Target = kill_demo
+ARCH ?= x86
+#编译器CC
+#根据传入的参数ARCH，确定使用的编译器
+#默认使用gcc编译器
+#make ARCH=arm 时使用ARM-GCC编译器
+ifeq ($(ARCH), x86)
+	CC = gcc
+else
+	CC = arm-linux-gnueabihf-gcc
+endif
+#存放中间文件的路径
+build_dir = build_$(ARCH)
+#存放源文件的文件夹
+src_dir =  sources
+#存放头文件的文件夹
+inc_dir = includes .
+
+#源文件
+sources = $(foreach dir,$(src_dir),$(wildcard $(dir)/*.c))
+#目标文件（*.o）
+objects = $(patsubst %.c,$(build_dir)/%.o,$(notdir $(sources)))
+#头文件
+includes = $(foreach dir,$(inc_dir),$(wildcard $(dir)/*.h))
+
+#目标依赖文件
+DEP_FILES := $(patsubst %, .%.d,$(objects))
+DEP_FILES := $(wildcard $(DEP_FILES))
+
+#判断依赖文件是否存在
+ifneq ($(DEP_FILES),)
+#如果存在依赖文件，需要导入依赖文件
+include $(DEP_FILES)
+endif
+
+#编译参数
+#指定头文件的路径
+CFLAGS = $(patsubst %, -I%, $(inc_dir)) -MD -MF $(@D)/.$(@F).d
+
+#链接过程
+$(build_dir)/$(Target) : $(objects)  | create_build
+	$(CC) $^ -o $@
+
+#编译工程
+#编译src文件夹中的源文件，并将生成的目标文件放在objs文件夹中
+$(build_dir)/%.o : $(src_dir)/%.c $(includes) | create_build
+	$(CC) -c $(CFLAGS) $< -o $@
+
+
+#以下为伪目标，调用方式：make 伪目标
+#clean：用于Clean Project
+#check：用于检查某个变量的值
+.PHONY:clean cleanall check create_build
+#按架构删除
+clean:
+	rm -rf $(build_dir)
+
+#全部删除
+cleanall:
+	rm -rf build_x86 build_arm
+
+#命令前带"@",表示不在终端上输出执行的命令
+#这个目标主要是用来调试Makefile时输出一些内容
+check:
+	@echo $(CFLAGS)
+	@echo $(CURDIR)
+	@echo $(src_dir)
+	@echo $(sources)
+	@echo $(objects)
+
+
+#创建一个新目录create，用于存放过程文件
+create_build:
+	@mkdir -p $(build_dir)
+
+
diff --git a/base_code/system_programing/kill/sources/kill.c b/base_code/system_programing/kill/sources/kill.c
new file mode 100644
index 0000000000000000000000000000000000000000..ebfc07ac4045f6eaa5ee8ca5551999351c24d9cf
--- /dev/null
+++ b/base_code/system_programing/kill/sources/kill.c
@@ -0,0 +1,56 @@
+/*
+ * @Author: jiejie
+ * @Github: https://github.com/jiejieTop
+ * @Date: 2020-02-10 16:51:42
+ * @LastEditTime: 2020-02-10 16:57:00
+ * @Description: the code belongs to jiejie, please keep the author information and source code according to the license.
+ */
+/** signal.c */
+
+#include <unistd.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <signal.h>
+#include <sys/types.h>
+#include <sys/wait.h>
+
+int main(void)
+{
+    pid_t pid;
+
+    int ret;
+
+    /* 创建一子进程 */
+    if ((pid = fork()) < 0) {
+        printf("Fork error\n");
+        exit(1);
+    }
+
+    if (pid == 0) {
+        /* 在子进程中使用 raise()函数发出 SIGSTOP 信号,使子进程暂停 */
+        printf("Child(pid : %d) is waiting for any signal\n\n", getpid());
+
+        /** 子进程停在这里 */
+        raise(SIGSTOP);
+
+        exit(0);
+    }
+
+    else {
+        /** 等待一下，等子进程先执行 */
+        sleep(1);
+
+        /* 在父进程中收集子进程发出的信号(不阻塞)，并调用 kill()函数进行相应的操作 */
+        if ((waitpid(pid, NULL, WNOHANG)) == 0) {
+            /** 子进程还没退出，返回为0，就发送SIGKILL信号杀死子进程 */
+            if ((ret = kill(pid, SIGKILL)) == 0) {
+                printf("Parent kill %d\n\n",pid);
+            }
+        }
+
+        /** 一直阻塞直到子进程退出（杀死） */
+        waitpid(pid, NULL, 0);
+
+        exit(0);
+    }
+}
diff --git a/base_code/system_programing/msg/msg_recv/Makefile b/base_code/system_programing/msg/msg_recv/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..cd1aa7664641ba0e8790605b8f78e8c9a9973607
--- /dev/null
+++ b/base_code/system_programing/msg/msg_recv/Makefile
@@ -0,0 +1,78 @@
+
+#生成可执行文件的名称
+Target = msg_recv_demo
+ARCH ?= x86
+#编译器CC
+#根据传入的参数ARCH，确定使用的编译器
+#默认使用gcc编译器
+#make ARCH=arm 时使用ARM-GCC编译器
+ifeq ($(ARCH), x86)
+	CC = gcc
+else
+	CC = arm-linux-gnueabihf-gcc
+endif
+#存放中间文件的路径
+build_dir = build_$(ARCH)
+#存放源文件的文件夹
+src_dir =  sources
+#存放头文件的文件夹
+inc_dir = includes .
+
+#源文件
+sources = $(foreach dir,$(src_dir),$(wildcard $(dir)/*.c))
+#目标文件（*.o）
+objects = $(patsubst %.c,$(build_dir)/%.o,$(notdir $(sources)))
+#头文件
+includes = $(foreach dir,$(inc_dir),$(wildcard $(dir)/*.h))
+
+#目标依赖文件
+DEP_FILES := $(patsubst %, .%.d,$(objects))
+DEP_FILES := $(wildcard $(DEP_FILES))
+
+#判断依赖文件是否存在
+ifneq ($(DEP_FILES),)
+#如果存在依赖文件，需要导入依赖文件
+include $(DEP_FILES)
+endif
+
+#编译参数
+#指定头文件的路径
+CFLAGS = $(patsubst %, -I%, $(inc_dir)) -MD -MF $(@D)/.$(@F).d
+
+#链接过程
+$(build_dir)/$(Target) : $(objects)  | create_build
+	$(CC) $^ -o $@
+
+#编译工程
+#编译src文件夹中的源文件，并将生成的目标文件放在objs文件夹中
+$(build_dir)/%.o : $(src_dir)/%.c $(includes) | create_build
+	$(CC) -c $(CFLAGS) $< -o $@
+
+
+#以下为伪目标，调用方式：make 伪目标
+#clean：用于Clean Project
+#check：用于检查某个变量的值
+.PHONY:clean cleanall check create_build
+#按架构删除
+clean:
+	rm -rf $(build_dir)
+
+#全部删除
+cleanall:
+	rm -rf build_x86 build_arm
+
+#命令前带"@",表示不在终端上输出执行的命令
+#这个目标主要是用来调试Makefile时输出一些内容
+check:
+	@echo $(CFLAGS)
+	@echo $(CURDIR)
+	@echo $(src_dir)
+	@echo $(sources)
+	@echo $(objects)
+
+
+#创建一个新目录create，用于存放过程文件
+create_build:
+	@mkdir -p $(build_dir)
+
+
diff --git a/base_code/system_programing/msg/msg_recv/sources/msg.c b/base_code/system_programing/msg/msg_recv/sources/msg.c
new file mode 100644
index 0000000000000000000000000000000000000000..ba13239ab3490ff207be74e539c20fd3c32cdaa4
--- /dev/null
+++ b/base_code/system_programing/msg/msg_recv/sources/msg.c
@@ -0,0 +1,64 @@
+/*
+ * @Author: jiejie
+ * @Github: https://github.com/jiejieTop
+ * @Date: 2020-02-10 16:51:42
+ * @LastEditTime: 2020-02-10 16:57:21
+ * @Description: the code belongs to jiejie, please keep the author information and source code according to the license.
+ */
+/** msg.c */
+
+#include <sys/types.h>
+#include <sys/ipc.h>
+#include <sys/msg.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <unistd.h>
+#include <string.h>
+
+#define BUFFER_SIZE 512
+
+struct message
+{
+    long msg_type;
+    char msg_text[BUFFER_SIZE];
+};
+
+int main()
+{
+    int qid;
+    struct message msg;
+
+    /*创建消息队列*/
+    if ((qid = msgget((key_t)1234, IPC_CREAT|0666)) == -1)
+    {
+        perror("msgget");
+        exit(1);
+    }
+
+    printf("Open queue %d\n", qid);
+
+    do
+    {
+        /*读取消息队列*/
+        memset(msg.msg_text, 0, BUFFER_SIZE);
+
+        if (msgrcv(qid, (void*)&msg, BUFFER_SIZE, 0, 0) < 0)
+        {
+            perror("msgrcv");
+            exit(1);
+        }
+
+        printf("The message from process %ld : %s", msg.msg_type, msg.msg_text);
+
+    } while(strncmp(msg.msg_text, "quit", 4));
+
+    /*从系统内核中移走消息队列 */
+    if ((msgctl(qid, IPC_RMID, NULL)) < 0)
+    {
+        perror("msgctl");
+        exit(1);
+    }
+
+    exit(0);
+
+}
diff --git a/base_code/system_programing/msg/msg_send/Makefile b/base_code/system_programing/msg/msg_send/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..650ff5a5d9f8815fc27b343d6d7e8aa392d39925
--- /dev/null
+++ b/base_code/system_programing/msg/msg_send/Makefile
@@ -0,0 +1,78 @@
+
+#生成可执行文件的名称
+Target = system_demo
+ARCH ?= x86
+#编译器CC
+#根据传入的参数ARCH，确定使用的编译器
+#默认使用gcc编译器
+#make ARCH=arm 时使用ARM-GCC编译器
+ifeq ($(ARCH), x86)
+	CC = gcc
+else
+	CC = arm-linux-gnueabihf-gcc
+endif
+#存放中间文件的路径
+build_dir = build_$(ARCH)
+#存放源文件的文件夹
+src_dir =  sources
+#存放头文件的文件夹
+inc_dir = includes .
+
+#源文件
+sources = $(foreach dir,$(src_dir),$(wildcard $(dir)/*.c))
+#目标文件（*.o）
+objects = $(patsubst %.c,$(build_dir)/%.o,$(notdir $(sources)))
+#头文件
+includes = $(foreach dir,$(inc_dir),$(wildcard $(dir)/*.h))
+
+#目标依赖文件
+DEP_FILES := $(patsubst %, .%.d,$(objects))
+DEP_FILES := $(wildcard $(DEP_FILES))
+
+#判断依赖文件是否存在
+ifneq ($(DEP_FILES),)
+#如果存在依赖文件，需要导入依赖文件
+include $(DEP_FILES)
+endif
+
+#编译参数
+#指定头文件的路径
+CFLAGS = $(patsubst %, -I%, $(inc_dir)) -MD -MF $(@D)/.$(@F).d
+
+#链接过程
+$(build_dir)/$(Target) : $(objects)  | create_build
+	$(CC) $^ -o $@
+
+#编译工程
+#编译src文件夹中的源文件，并将生成的目标文件放在objs文件夹中
+$(build_dir)/%.o : $(src_dir)/%.c $(includes) | create_build
+	$(CC) -c $(CFLAGS) $< -o $@
+
+
+#以下为伪目标，调用方式：make 伪目标
+#clean：用于Clean Project
+#check：用于检查某个变量的值
+.PHONY:clean cleanall check create_build
+#按架构删除
+clean:
+	rm -rf $(build_dir)
+
+#全部删除
+cleanall:
+	rm -rf build_x86 build_arm
+
+#命令前带"@",表示不在终端上输出执行的命令
+#这个目标主要是用来调试Makefile时输出一些内容
+check:
+	@echo $(CFLAGS)
+	@echo $(CURDIR)
+	@echo $(src_dir)
+	@echo $(sources)
+	@echo $(objects)
+
+
+#创建一个新目录create，用于存放过程文件
+create_build:
+	@mkdir -p $(build_dir)
+
+
diff --git a/base_code/system_programing/msg/msg_send/sources/msg.c b/base_code/system_programing/msg/msg_send/sources/msg.c
new file mode 100644
index 0000000000000000000000000000000000000000..90674c1b89cc378ab3a87253ad4aa16fd44f4241
--- /dev/null
+++ b/base_code/system_programing/msg/msg_send/sources/msg.c
@@ -0,0 +1,65 @@
+/*
+ * @Author: jiejie
+ * @Github: https://github.com/jiejieTop
+ * @Date: 2020-02-10 16:51:42
+ * @LastEditTime: 2020-02-10 16:57:30
+ * @Description: the code belongs to jiejie, please keep the author information and source code according to the license.
+ */
+/** msg.c */
+
+#include <sys/types.h>
+#include <sys/ipc.h>
+#include <sys/msg.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <unistd.h>
+#include <string.h>
+
+
+#define BUFFER_SIZE 512
+
+struct message
+{
+    long msg_type;
+    char msg_text[BUFFER_SIZE];
+};
+int main()
+{
+    int qid;
+    struct message msg;
+
+    /*创建消息队列*/
+    if ((qid = msgget((key_t)1234, IPC_CREAT|0666)) == -1)
+    {
+        perror("msgget");
+        exit(1);
+    }
+
+    printf("Open queue %d\n",qid);
+
+    while(1)
+    {
+        printf("Enter some message to the queue:");
+        if ((fgets(msg.msg_text, BUFFER_SIZE, stdin)) == NULL)
+        {
+            puts("no message");
+            exit(1);
+        }
+        
+        msg.msg_type = getpid();
+
+        /*添加消息到消息队列*/
+        if ((msgsnd(qid, &msg, strlen(msg.msg_text), 0)) < 0)
+        {
+            perror("message posted");
+            exit(1);
+        }
+
+        if (strncmp(msg.msg_text, "quit", 4) == 0)
+        {
+            break;
+        }
+    }
+
+    exit(0);
+}
diff --git a/base_code/system_programing/mutex/Makefile b/base_code/system_programing/mutex/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..66bb5628e82eaf82c3eefe3be82bd372f365b0ca
--- /dev/null
+++ b/base_code/system_programing/mutex/Makefile
@@ -0,0 +1,79 @@
+
+#生成可执行文件的名称
+Target = mutex_demo
+ARCH ?= x86
+#编译器CC
+#根据传入的参数ARCH，确定使用的编译器
+#默认使用gcc编译器
+#make ARCH=arm 时使用ARM-GCC编译器
+ifeq ($(ARCH), x86)
+	CC = gcc
+else
+	CC = arm-linux-gnueabihf-gcc
+endif
+#存放中间文件的路径
+build_dir = build_$(ARCH)
+#存放源文件的文件夹
+src_dir =  sources
+#存放头文件的文件夹
+inc_dir = includes .
+
+#源文件
+sources = $(foreach dir,$(src_dir),$(wildcard $(dir)/*.c))
+#目标文件（*.o）
+objects = $(patsubst %.c,$(build_dir)/%.o,$(notdir $(sources)))
+#头文件
+includes = $(foreach dir,$(inc_dir),$(wildcard $(dir)/*.h))
+
+#目标依赖文件
+DEP_FILES := $(patsubst %, .%.d,$(objects))
+DEP_FILES := $(wildcard $(DEP_FILES))
+
+#判断依赖文件是否存在
+ifneq ($(DEP_FILES),)
+#如果存在依赖文件，需要导入依赖文件
+include $(DEP_FILES)
+endif
+
+#编译参数
+#指定头文件的路径
+CFLAGS = $(patsubst %, -I%, $(inc_dir)) -MD -MF $(@D)/.$(@F).d
+LINK = -lpthread
+
+#链接过程
+$(build_dir)/$(Target) : $(objects)  | create_build
+	$(CC) $^ ${LINK} -o $@
+
+#编译工程
+#编译src文件夹中的源文件，并将生成的目标文件放在objs文件夹中
+$(build_dir)/%.o : $(src_dir)/%.c $(includes) | create_build
+	$(CC) -c $(CFLAGS) $< -o $@
+
+
+#以下为伪目标，调用方式：make 伪目标
+#clean：用于Clean Project
+#check：用于检查某个变量的值
+.PHONY:clean cleanall check create_build
+#按架构删除
+clean:
+	rm -rf $(build_dir)
+
+#全部删除
+cleanall:
+	rm -rf build_x86 build_arm
+
+#命令前带"@",表示不在终端上输出执行的命令
+#这个目标主要是用来调试Makefile时输出一些内容
+check:
+	@echo $(CFLAGS)
+	@echo $(CURDIR)
+	@echo $(src_dir)
+	@echo $(sources)
+	@echo $(objects)
+
+
+#创建一个新目录create，用于存放过程文件
+create_build:
+	@mkdir -p $(build_dir)
+
+
diff --git a/base_code/system_programing/mutex/sources/mutex.c b/base_code/system_programing/mutex/sources/mutex.c
new file mode 100644
index 0000000000000000000000000000000000000000..c5c43878f05bce61d5a40ab830b02927e35e0de2
--- /dev/null
+++ b/base_code/system_programing/mutex/sources/mutex.c
@@ -0,0 +1,110 @@
+/** mutex */
+
+/**
+ * 互斥锁是用一种简单的加锁方法来控制对共享资源的原子操作。这个互斥锁只有两种状态，也就是上锁和解锁，
+ * 可以把互斥锁看作某种意义上的全局变量。在同一时刻只能有一个线程掌握某个互斥锁，拥有上锁状态的线程能
+ * 够对共享资源进行操作。 若其他线程希望上锁一个已经被上锁的互斥锁， 则该线程就会挂起，直到上锁的线程
+ * 释放掉互斥锁为止。 可以说， 这把互斥锁保证让每个线程对共享资源按顺序进行原子操作。
+ *  互斥锁初始化： pthread_mutex_init()
+ *  互斥锁上锁： pthread_mutex_lock()
+ *  互斥锁判断上锁： pthread_mutex_trylock()
+ *  互斥锁接锁： pthread_mutex_unlock()
+ *  消除互斥锁： pthread_mutex_destroy()
+ * 
+ * 函数原型 int pthread_mutex_init(pthread_mutex_t *mutex, const pthread_mutexattr_t *mutexattr)
+ * 函数传入值 mutex：互斥锁
+ * Mutexattr：
+ *  PTHREAD_MUTEX_INITIALIZER：创建快速互斥锁
+ *  PTHREAD_RECURSIVE_MUTEX_INITIALIZER_NP：创建递归互斥锁
+ *  PTHREAD_ERRORCHECK_MUTEX_INITIALIZER_NP： 创建检错互斥锁
+ * 函数返回值
+ *  成功： 0
+ *  出错：返回错误码
+ * 
+ * 函数原型
+ * int pthread_mutex_lock(pthread_mutex_t *mutex,)
+ * int pthread_mutex_trylock(pthread_mutex_t *mutex,)
+ * int pthread_mutex_unlock(pthread_mutex_t *mutex,)
+ * int pthread_mutex_destroy(pthread_mutex_t *mutex,)
+ * 函数传入值 mutex：互斥锁
+ * 函数返回值
+ *  成功： 0
+ *  出错：-1
+ * 
+ */
+
+#include <unistd.h>
+#include <fcntl.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <pthread.h>
+
+#define THREAD_NUMBER 3 /* 线程数 */
+#define sleep_TIME_LEVELS 4.0 /*小任务之间的最大时间间隔*/
+
+pthread_mutex_t mutex;
+
+void *thrd_func(void *arg)
+{
+    int num = (unsigned long long)arg; /** sizeof(void*) == 8 and sizeof(int) == 4 (64 bits) */
+    int sleep_time = 0;
+    int res;
+
+    /* 互斥锁上锁 */
+    res = pthread_mutex_lock(&mutex);
+    if (res)
+    {
+        printf("Thread %d lock failed\n", num);
+
+        /* 互斥锁解锁 */
+        pthread_mutex_unlock(&mutex);
+
+        pthread_exit(NULL);
+    }
+
+    printf("Thread %d is hold mutex\n", num);
+
+    sleep_time = (int)(rand() * sleep_TIME_LEVELS/(RAND_MAX)) + 1;
+    printf("\tThread %d: sleep %d S\n",num, sleep_time);
+    sleep(sleep_time);
+
+    printf("Thread %d freed mutex\n\n", num);
+
+    /* 互斥锁解锁 */
+    pthread_mutex_unlock(&mutex);
+
+    pthread_exit(NULL);
+}
+
+
+int main(void)
+{
+    pthread_t thread[THREAD_NUMBER];
+    int num = 0, res;
+
+    srand(time(NULL));
+
+    /* 互斥锁初始化 */
+    pthread_mutex_init(&mutex, NULL);
+    for (num = 0; num < THREAD_NUMBER; num++)
+    {
+        res = pthread_create(&thread[num], NULL, thrd_func, (void*)(unsigned long long)num);
+        if (res != 0)
+        {
+            printf("Create thread %d failed\n", num);
+            exit(res);
+        }
+    }
+
+
+    for (num = 0; num < THREAD_NUMBER; num++)
+    {
+        pthread_join(thread[num], NULL);
+    }
+
+    pthread_mutex_destroy(&mutex);
+    
+    return 0;
+}
+
+
diff --git a/base_code/system_programing/pipe/Makefile b/base_code/system_programing/pipe/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..95218a4602eb1384f9f961a84f0856ce32507d2b
--- /dev/null
+++ b/base_code/system_programing/pipe/Makefile
@@ -0,0 +1,78 @@
+
+#生成可执行文件的名称
+Target = pipe_demo
+ARCH ?= x86
+#编译器CC
+#根据传入的参数ARCH，确定使用的编译器
+#默认使用gcc编译器
+#make ARCH=arm 时使用ARM-GCC编译器
+ifeq ($(ARCH), x86)
+	CC = gcc
+else
+	CC = arm-linux-gnueabihf-gcc
+endif
+#存放中间文件的路径
+build_dir = build_$(ARCH)
+#存放源文件的文件夹
+src_dir =  sources
+#存放头文件的文件夹
+inc_dir = includes .
+
+#源文件
+sources = $(foreach dir,$(src_dir),$(wildcard $(dir)/*.c))
+#目标文件（*.o）
+objects = $(patsubst %.c,$(build_dir)/%.o,$(notdir $(sources)))
+#头文件
+includes = $(foreach dir,$(inc_dir),$(wildcard $(dir)/*.h))
+
+#目标依赖文件
+DEP_FILES := $(patsubst %, .%.d,$(objects))
+DEP_FILES := $(wildcard $(DEP_FILES))
+
+#判断依赖文件是否存在
+ifneq ($(DEP_FILES),)
+#如果存在依赖文件，需要导入依赖文件
+include $(DEP_FILES)
+endif
+
+#编译参数
+#指定头文件的路径
+CFLAGS = $(patsubst %, -I%, $(inc_dir)) -MD -MF $(@D)/.$(@F).d
+
+#链接过程
+$(build_dir)/$(Target) : $(objects)  | create_build
+	$(CC) $^ -o $@
+
+#编译工程
+#编译src文件夹中的源文件，并将生成的目标文件放在objs文件夹中
+$(build_dir)/%.o : $(src_dir)/%.c $(includes) | create_build
+	$(CC) -c $(CFLAGS) $< -o $@
+
+
+#以下为伪目标，调用方式：make 伪目标
+#clean：用于Clean Project
+#check：用于检查某个变量的值
+.PHONY:clean cleanall check create_build
+#按架构删除
+clean:
+	rm -rf $(build_dir)
+
+#全部删除
+cleanall:
+	rm -rf build_x86 build_arm
+
+#命令前带"@",表示不在终端上输出执行的命令
+#这个目标主要是用来调试Makefile时输出一些内容
+check:
+	@echo $(CFLAGS)
+	@echo $(CURDIR)
+	@echo $(src_dir)
+	@echo $(sources)
+	@echo $(objects)
+
+
+#创建一个新目录create，用于存放过程文件
+create_build:
+	@mkdir -p $(build_dir)
+
+
diff --git a/base_code/system_programing/pipe/sources/pipe.c b/base_code/system_programing/pipe/sources/pipe.c
new file mode 100644
index 0000000000000000000000000000000000000000..bf78c2079b43ad0d82e25541c5cbe84ea0a45d3e
--- /dev/null
+++ b/base_code/system_programing/pipe/sources/pipe.c
@@ -0,0 +1,110 @@
+/** pipe.c */
+
+/**
+ * ps –ef | grep ntp
+ * 
+ * 进程 ps -ef              进程 grep ntp
+ *          |              |
+ *          |---- pipe ----|
+ * 
+ * 管道是 Linux 中进程间通信的一种方式。这里所说的管道主要指无名管道，它具有如下特点:
+ *   它只能用于具有亲缘关系的进程之间的通信（也就是父子进程或者兄弟进程之间）。
+ *   它是一个半双工的通信模式，具有固定的读端和写端。
+ *   管道也可以看成是一种特殊的文件，对于它的读写也可以使用普通的 read()和 write()等函数。
+ *    但是它不是普通的文件，并不属于其他任何文件系统，并且只存在于内核的内存空间中。
+ * 
+ * 管道是基于文件描述符的通信方式，当一个管道建立时，它会创建两个文件描述符 fds[0]和 fds[1]，
+ * 其中 fds[0]固定用于读管道，而 fd[1]固定用于写管道，这样就构成了一个半双工的通道。
+ * 管道关闭时只需将这两个文件描述符关闭即可，可使用普通的 close()函数逐个关闭各个文件描述符。
+ * 
+ *           用户进程
+ *  fd[0]               fd[1]
+ *    |                   |
+ *    读                  写
+ *    |--------管道--------|
+ * 
+ *     父进程                 子进程
+ *  fd[0]fd[1]            fd[0]fd[1] 
+ *      |                     |
+ *     读写                   读写
+ *      |---------管道---------|
+ * 
+ * 函数原型：int pipe(int fd[2])
+ * 
+ */
+
+/**
+ * 注意点：
+ *   只有在管道的读端存在时，向管道写入数据才有意义。否则，向管道写入数据的进程将收到内核传来的 SIGPIPE 信号（通常为 Broken pipe 错误）。
+ *   向管道写入数据时， Linux 将不保证写入的原子性，管道缓冲区一有空闲区域，写进程就会试图向管道写入数据。如果读进程不读取管道缓冲区中的数据，那么写操作将会一直阻塞。
+ *   父子进程在运行时，它们的先后次序并不能保证，建议使用进程之间的同步与互斥机制之后。
+ */
+
+#include <unistd.h>
+#include <sys/types.h>
+#include <sys/wait.h>
+#include <errno.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#define MAX_DATA_LEN 256
+#define DELAY_TIME 1
+
+int main()
+{
+    pid_t pid;
+    int pipe_fd[2];
+    char buf[MAX_DATA_LEN];
+    const char data[] = "Pipe Test Program";
+    int real_read, real_write;
+
+    memset((void*)buf, 0, sizeof(buf));
+
+    /* 创建管道 */
+    if (pipe(pipe_fd) < 0)
+    {
+        printf("pipe create error\n");
+        exit(1);
+    }
+
+    /* 创建一子进程 */
+    if ((pid = fork()) == 0)
+    {
+        /* 子进程关闭写描述符，并通过使子进程暂停 3s 等待父进程已关闭相应的读描述符 */
+        close(pipe_fd[1]);
+        sleep(DELAY_TIME * 3);
+
+        /* 子进程读取管道内容 */
+        if ((real_read = read(pipe_fd[0], buf, MAX_DATA_LEN)) > 0)
+        {
+            printf("%d bytes read from the pipe is '%s'\n", real_read, buf);
+        }
+
+        /* 关闭子进程读描述符 */
+        close(pipe_fd[0]);
+
+        exit(0);
+    }
+    
+    else if (pid > 0)
+    {
+        /* 父进程关闭读描述符，并通过使父进程暂停 1s 等待子进程已关闭相应的写描述符 */
+        close(pipe_fd[0]);
+
+        sleep(DELAY_TIME);
+        
+        if((real_write = write(pipe_fd[1], data, strlen(data))) != -1)
+        {
+            printf("Parent write %d bytes : '%s'\n", real_write, data);
+        }
+        
+        /*关闭父进程写描述符*/
+        close(pipe_fd[1]);
+
+        /*收集子进程退出信息*/
+        waitpid(pid, NULL, 0);
+
+        exit(0);
+    }
+}
diff --git a/base_code/system_programing/posix_sem/Makefile b/base_code/system_programing/posix_sem/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..1ba8c5d72d6c6d9399dcc89a471e31bc4a942bad
--- /dev/null
+++ b/base_code/system_programing/posix_sem/Makefile
@@ -0,0 +1,79 @@
+
+#生成可执行文件的名称
+Target = posix_sem_demo
+ARCH ?= x86
+#编译器CC
+#根据传入的参数ARCH，确定使用的编译器
+#默认使用gcc编译器
+#make ARCH=arm 时使用ARM-GCC编译器
+ifeq ($(ARCH), x86)
+	CC = gcc
+else
+	CC = arm-linux-gnueabihf-gcc
+endif
+#存放中间文件的路径
+build_dir = build_$(ARCH)
+#存放源文件的文件夹
+src_dir =  sources
+#存放头文件的文件夹
+inc_dir = includes .
+
+#源文件
+sources = $(foreach dir,$(src_dir),$(wildcard $(dir)/*.c))
+#目标文件（*.o）
+objects = $(patsubst %.c,$(build_dir)/%.o,$(notdir $(sources)))
+#头文件
+includes = $(foreach dir,$(inc_dir),$(wildcard $(dir)/*.h))
+
+#目标依赖文件
+DEP_FILES := $(patsubst %, .%.d,$(objects))
+DEP_FILES := $(wildcard $(DEP_FILES))
+
+#判断依赖文件是否存在
+ifneq ($(DEP_FILES),)
+#如果存在依赖文件，需要导入依赖文件
+include $(DEP_FILES)
+endif
+
+#编译参数
+#指定头文件的路径
+CFLAGS = $(patsubst %, -I%, $(inc_dir)) -MD -MF $(@D)/.$(@F).d
+LINK = -lpthread
+
+#链接过程
+$(build_dir)/$(Target) : $(objects)  | create_build
+	$(CC) $^ ${LINK} -o $@
+
+#编译工程
+#编译src文件夹中的源文件，并将生成的目标文件放在objs文件夹中
+$(build_dir)/%.o : $(src_dir)/%.c $(includes) | create_build
+	$(CC) -c $(CFLAGS) $< -o $@
+
+
+#以下为伪目标，调用方式：make 伪目标
+#clean：用于Clean Project
+#check：用于检查某个变量的值
+.PHONY:clean cleanall check create_build
+#按架构删除
+clean:
+	rm -rf $(build_dir)
+
+#全部删除
+cleanall:
+	rm -rf build_x86 build_arm
+
+#命令前带"@",表示不在终端上输出执行的命令
+#这个目标主要是用来调试Makefile时输出一些内容
+check:
+	@echo $(CFLAGS)
+	@echo $(CURDIR)
+	@echo $(src_dir)
+	@echo $(sources)
+	@echo $(objects)
+
+
+#创建一个新目录create，用于存放过程文件
+create_build:
+	@mkdir -p $(build_dir)
+
+
diff --git a/base_code/system_programing/posix_sem/sources/posix_sem.c b/base_code/system_programing/posix_sem/sources/posix_sem.c
new file mode 100644
index 0000000000000000000000000000000000000000..d5b11142089cc02ff3e15fe7d7b7ba49318505b1
--- /dev/null
+++ b/base_code/system_programing/posix_sem/sources/posix_sem.c
@@ -0,0 +1,104 @@
+/** thread_sem.c */
+
+/**
+ *  sem_init()用于创建一个信号量，并初始化它的值。
+ *  sem_wait()和 sem_trywait()都相当于 P 操作，在信号量大于零时它们都能将信号量的值减一，两
+ * 者的区别在于若信号量小于零时， sem_wait()将会阻塞进程，而 sem_trywait()则会立即返回。
+ *  sem_post()相当于 V 操作，它将信号量的值加一同时发出信号来唤醒等待的进程。
+ *  sem_getvalue()用于得到信号量的值。
+ *  sem_destroy()用于删除信号量。
+ * 
+ * 函数原型 int sem_init(sem_t *sem,int pshared,unsigned int value)
+ * 函数传入值
+ *  sem：信号量指针
+ *  pshared：决定信号量能否在几个进程间共享。由于目前 Linux 还没有实现进程间共享信号量，
+ *  所以这个值只能够取 0，就表示这个信号量是当前进程的局部信号量
+ *  value：信号量初始化值
+ * 函数返回值
+ *  成功： 0
+ *  出错： -1 
+ * 
+ */
+
+#include <unistd.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <pthread.h>
+#include <semaphore.h>
+
+#define THREAD_NUMBER 3 /* 线程数 */
+#define REPEAT_NUMBER 3 /* 每个线程中的小任务数 */
+#define DELAY_TIME_LEVELS 3.0 /*小任务之间的最大时间间隔*/
+
+sem_t sem[THREAD_NUMBER];
+
+void *thread_func(void *arg)
+{
+    int num = (unsigned long long)arg;
+    int delay_time = 0;
+    int count = 0;
+
+    /* 进行 P 操作 */
+    sem_wait(&sem[num]);
+
+    printf("Thread %d is starting\n", num);
+    for (count = 0; count < REPEAT_NUMBER; count++)
+    {
+        delay_time = (int)(rand() * DELAY_TIME_LEVELS/(RAND_MAX)) + 1;
+        sleep(delay_time);
+        printf("\tThread %d: job %d delay = %d\n",num, count, delay_time);
+    }
+
+    printf("Thread %d finished\n", num);
+    pthread_exit(NULL);
+}
+
+
+
+int main(void)
+{
+    pthread_t thread[THREAD_NUMBER];
+    int no = 0, res;
+    void * thread_ret;
+    srand(time(NULL));
+
+    for (no = 0; no < THREAD_NUMBER; no++)
+    {
+        sem_init(&sem[no], 0, 0);
+        res = pthread_create(&thread[no], NULL, thread_func, (void*)(unsigned long long)no);
+
+        if (res != 0)
+        {
+            printf("Create thread %d failed\n", no);
+            exit(res);
+        }
+    }
+
+    printf("Create treads success\n Waiting for threads to finish...\n");
+
+    /* 对最后创建的线程的信号量进行 V 操作 */
+    sem_post(&sem[THREAD_NUMBER - 1]);
+    for (no = THREAD_NUMBER - 1; no >= 0; no--)
+    {
+        res = pthread_join(thread[no], &thread_ret);
+        if (!res)
+        {
+            printf("Thread %d joined\n", no);
+        }
+        else
+        {
+            printf("Thread %d join failed\n", no);
+        }
+
+        /* 进行 V 操作 */
+        sem_post(&sem[(no + THREAD_NUMBER - 1) % THREAD_NUMBER]);
+    }
+
+    for (no = 0; no < THREAD_NUMBER; no++)
+    {
+        /* 删除信号量 */
+        sem_destroy(&sem[no]);
+    }
+
+    return 0;
+}
diff --git a/base_code/system_programing/posix_sem1/Makefile b/base_code/system_programing/posix_sem1/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..b0fb5dde46d24fd21df00a54ec768d73221405ba
--- /dev/null
+++ b/base_code/system_programing/posix_sem1/Makefile
@@ -0,0 +1,79 @@
+
+#生成可执行文件的名称
+Target = posix_sem1_demo
+ARCH ?= x86
+#编译器CC
+#根据传入的参数ARCH，确定使用的编译器
+#默认使用gcc编译器
+#make ARCH=arm 时使用ARM-GCC编译器
+ifeq ($(ARCH), x86)
+	CC = gcc
+else
+	CC = arm-linux-gnueabihf-gcc
+endif
+#存放中间文件的路径
+build_dir = build_$(ARCH)
+#存放源文件的文件夹
+src_dir =  sources
+#存放头文件的文件夹
+inc_dir = includes .
+
+#源文件
+sources = $(foreach dir,$(src_dir),$(wildcard $(dir)/*.c))
+#目标文件（*.o）
+objects = $(patsubst %.c,$(build_dir)/%.o,$(notdir $(sources)))
+#头文件
+includes = $(foreach dir,$(inc_dir),$(wildcard $(dir)/*.h))
+
+#目标依赖文件
+DEP_FILES := $(patsubst %, .%.d,$(objects))
+DEP_FILES := $(wildcard $(DEP_FILES))
+
+#判断依赖文件是否存在
+ifneq ($(DEP_FILES),)
+#如果存在依赖文件，需要导入依赖文件
+include $(DEP_FILES)
+endif
+
+#编译参数
+#指定头文件的路径
+CFLAGS = $(patsubst %, -I%, $(inc_dir)) -MD -MF $(@D)/.$(@F).d
+LINK = -lpthread
+
+#链接过程
+$(build_dir)/$(Target) : $(objects)  | create_build
+	$(CC) $^ ${LINK} -o $@
+
+#编译工程
+#编译src文件夹中的源文件，并将生成的目标文件放在objs文件夹中
+$(build_dir)/%.o : $(src_dir)/%.c $(includes) | create_build
+	$(CC) -c $(CFLAGS) $< -o $@
+
+
+#以下为伪目标，调用方式：make 伪目标
+#clean：用于Clean Project
+#check：用于检查某个变量的值
+.PHONY:clean cleanall check create_build
+#按架构删除
+clean:
+	rm -rf $(build_dir)
+
+#全部删除
+cleanall:
+	rm -rf build_x86 build_arm
+
+#命令前带"@",表示不在终端上输出执行的命令
+#这个目标主要是用来调试Makefile时输出一些内容
+check:
+	@echo $(CFLAGS)
+	@echo $(CURDIR)
+	@echo $(src_dir)
+	@echo $(sources)
+	@echo $(objects)
+
+
+#创建一个新目录create，用于存放过程文件
+create_build:
+	@mkdir -p $(build_dir)
+
+
diff --git a/base_code/system_programing/posix_sem1/sources/posix_sem.c b/base_code/system_programing/posix_sem1/sources/posix_sem.c
new file mode 100644
index 0000000000000000000000000000000000000000..62aee6a17c4eb10362e6859309d7b4fb13beb389
--- /dev/null
+++ b/base_code/system_programing/posix_sem1/sources/posix_sem.c
@@ -0,0 +1,72 @@
+#include <unistd.h>
+#include <stdio.h>
+#include <pthread.h>
+#include <semaphore.h>
+#include <stdlib.h>
+#include <stdio.h>
+#include <sys/types.h>
+#include <fcntl.h>
+#include <sys/wait.h>
+
+int main(int argc, char **argv)
+{
+    int pid;
+    sem_t *sem;
+    const char sem_name[] = "my_sem_test";
+
+    pid = fork();
+
+    if (pid < 0) {
+        printf("error in the fork!\n");
+    } else if (pid == 0) {
+        
+        sem = sem_open(sem_name, O_CREAT, 0644, 1);
+
+        if (sem == SEM_FAILED) {
+            printf("unable to create semaphore...\n");
+
+            sem_unlink(sem_name);
+
+            exit(-1);
+        }
+
+        sem_wait(sem);
+
+        for (int i = 0; i < 3; ++i) {
+
+            printf("childe process run: %d\n", i);
+            sleep(1);
+        }
+
+    sem_post(sem);
+
+    } else {
+
+        sem = sem_open(sem_name, O_CREAT, 0644, 1);
+        
+        if (sem == SEM_FAILED) {
+            printf("unable to create semaphore...\n");
+
+            sem_unlink(sem_name);
+
+            exit(-1);
+        }
+
+        sem_wait(sem);
+
+        for (int i = 0; i < 3; ++i) {
+
+            printf("parent process run: %d\n", i);
+            sleep(1);
+        }
+
+        sem_post(sem);
+
+        wait(NULL);
+    }
+
+    sem_close(sem);
+    sem_unlink(sem_name);
+
+    return 0;
+}
diff --git a/base_code/system_programing/process/Makefile b/base_code/system_programing/process/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..a353998491b7d1aff0ffca0e920568a8ea3a678a
--- /dev/null
+++ b/base_code/system_programing/process/Makefile
@@ -0,0 +1,78 @@
+
+#生成可执行文件的名称
+Target = process_demo
+ARCH ?= x86
+#编译器CC
+#根据传入的参数ARCH，确定使用的编译器
+#默认使用gcc编译器
+#make ARCH=arm 时使用ARM-GCC编译器
+ifeq ($(ARCH), x86)
+	CC = gcc
+else
+	CC = arm-linux-gnueabihf-gcc
+endif
+#存放中间文件的路径
+build_dir = build_$(ARCH)
+#存放源文件的文件夹
+src_dir =  sources
+#存放头文件的文件夹
+inc_dir = includes .
+
+#源文件
+sources = $(foreach dir,$(src_dir),$(wildcard $(dir)/*.c))
+#目标文件（*.o）
+objects = $(patsubst %.c,$(build_dir)/%.o,$(notdir $(sources)))
+#头文件
+includes = $(foreach dir,$(inc_dir),$(wildcard $(dir)/*.h))
+
+#目标依赖文件
+DEP_FILES := $(patsubst %, .%.d,$(objects))
+DEP_FILES := $(wildcard $(DEP_FILES))
+
+#判断依赖文件是否存在
+ifneq ($(DEP_FILES),)
+#如果存在依赖文件，需要导入依赖文件
+include $(DEP_FILES)
+endif
+
+#编译参数
+#指定头文件的路径
+CFLAGS = $(patsubst %, -I%, $(inc_dir)) -MD -MF $(@D)/.$(@F).d
+
+#链接过程
+$(build_dir)/$(Target) : $(objects)  | create_build
+	$(CC) $^ -o $@
+
+#编译工程
+#编译src文件夹中的源文件，并将生成的目标文件放在objs文件夹中
+$(build_dir)/%.o : $(src_dir)/%.c $(includes) | create_build
+	$(CC) -c $(CFLAGS) $< -o $@
+
+
+#以下为伪目标，调用方式：make 伪目标
+#clean：用于Clean Project
+#check：用于检查某个变量的值
+.PHONY:clean cleanall check create_build
+#按架构删除
+clean:
+	rm -rf $(build_dir)
+
+#全部删除
+cleanall:
+	rm -rf build_x86 build_arm
+
+#命令前带"@",表示不在终端上输出执行的命令
+#这个目标主要是用来调试Makefile时输出一些内容
+check:
+	@echo $(CFLAGS)
+	@echo $(CURDIR)
+	@echo $(src_dir)
+	@echo $(sources)
+	@echo $(objects)
+
+
+#创建一个新目录create，用于存放过程文件
+create_build:
+	@mkdir -p $(build_dir)
+
+
diff --git a/base_code/system_programing/process/sources/process.c b/base_code/system_programing/process/sources/process.c
new file mode 100644
index 0000000000000000000000000000000000000000..0faca5a8c69323852b25c4e4b54264bd36b5d065
--- /dev/null
+++ b/base_code/system_programing/process/sources/process.c
@@ -0,0 +1,38 @@
+/* process.c */
+
+#include <sys/types.h>
+#include <unistd.h>
+#include <stdio.h>
+#include <stdlib.h>
+int main(void)
+{
+    pid_t result;
+
+    printf("This is a fork demo!\n\n");
+
+    /*调用 fork()函数*/
+    result = fork();
+
+    /*通过 result 的值来判断 fork()函数的返回情况，首先进行出错处理*/
+    if(result == -1) {
+        printf("Fork error\n");
+    }
+
+    /*返回值为 0 代表子进程*/
+    else if (result == 0) {
+        printf("The returned value is %d, In child process!! My PID is %d\n\n", result, getpid());
+
+    }
+
+    /*返回值大于 0 代表父进程*/
+    else {
+        printf("The returned value is %d, In father process!! My PID is %d\n\n", result, getpid());
+    }
+
+    return result;
+}
+
+
+
+
+
diff --git a/base_code/system_programing/shm_read/Makefile b/base_code/system_programing/shm_read/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..0815646d6fcaee0cfbef879070026780ac39a047
--- /dev/null
+++ b/base_code/system_programing/shm_read/Makefile
@@ -0,0 +1,78 @@
+
+#生成可执行文件的名称
+Target = shm_read_demo
+ARCH ?= x86
+#编译器CC
+#根据传入的参数ARCH，确定使用的编译器
+#默认使用gcc编译器
+#make ARCH=arm 时使用ARM-GCC编译器
+ifeq ($(ARCH), x86)
+	CC = gcc
+else
+	CC = arm-linux-gnueabihf-gcc
+endif
+#存放中间文件的路径
+build_dir = build_$(ARCH)
+#存放源文件的文件夹
+src_dir =  sources
+#存放头文件的文件夹
+inc_dir = includes .
+
+#源文件
+sources = $(foreach dir,$(src_dir),$(wildcard $(dir)/*.c))
+#目标文件（*.o）
+objects = $(patsubst %.c,$(build_dir)/%.o,$(notdir $(sources)))
+#头文件
+includes = $(foreach dir,$(inc_dir),$(wildcard $(dir)/*.h))
+
+#目标依赖文件
+DEP_FILES := $(patsubst %, .%.d,$(objects))
+DEP_FILES := $(wildcard $(DEP_FILES))
+
+#判断依赖文件是否存在
+ifneq ($(DEP_FILES),)
+#如果存在依赖文件，需要导入依赖文件
+include $(DEP_FILES)
+endif
+
+#编译参数
+#指定头文件的路径
+CFLAGS = $(patsubst %, -I%, $(inc_dir)) -MD -MF $(@D)/.$(@F).d
+
+#链接过程
+$(build_dir)/$(Target) : $(objects)  | create_build
+	$(CC) $^ -o $@
+
+#编译工程
+#编译src文件夹中的源文件，并将生成的目标文件放在objs文件夹中
+$(build_dir)/%.o : $(src_dir)/%.c $(includes) | create_build
+	$(CC) -c $(CFLAGS) $< -o $@
+
+
+#以下为伪目标，调用方式：make 伪目标
+#clean：用于Clean Project
+#check：用于检查某个变量的值
+.PHONY:clean cleanall check create_build
+#按架构删除
+clean:
+	rm -rf $(build_dir)
+
+#全部删除
+cleanall:
+	rm -rf build_x86 build_arm
+
+#命令前带"@",表示不在终端上输出执行的命令
+#这个目标主要是用来调试Makefile时输出一些内容
+check:
+	@echo $(CFLAGS)
+	@echo $(CURDIR)
+	@echo $(src_dir)
+	@echo $(sources)
+	@echo $(objects)
+
+
+#创建一个新目录create，用于存放过程文件
+create_build:
+	@mkdir -p $(build_dir)
+
+
diff --git a/base_code/system_programing/shm_read/includes/sem.h b/base_code/system_programing/shm_read/includes/sem.h
new file mode 100644
index 0000000000000000000000000000000000000000..68d14a932427dc480b3ac4d280192094f276c4d1
--- /dev/null
+++ b/base_code/system_programing/shm_read/includes/sem.h
@@ -0,0 +1,21 @@
+#ifndef _SEM_H_
+#define _SEM_H_
+
+
+union semun
+{
+    int val;
+    struct semid_ds *buf;
+    unsigned short *array;
+};
+
+int init_sem(int sem_id, int init_value);
+int del_sem(int sem_id);
+int sem_p(int sem_id);
+int sem_v(int sem_id);
+
+
+
+
+#endif
+
diff --git a/base_code/system_programing/shm_read/sources/sem.c b/base_code/system_programing/shm_read/sources/sem.c
new file mode 100644
index 0000000000000000000000000000000000000000..da194197ca3965aa051828b239b7f34a16911dcf
--- /dev/null
+++ b/base_code/system_programing/shm_read/sources/sem.c
@@ -0,0 +1,71 @@
+#include <sys/sem.h>
+#include <sys/ipc.h>
+#include <unistd.h>
+#include <stdlib.h>
+#include <stdio.h>
+#include <string.h>
+#include <sys/shm.h>
+#include <sys/stat.h>
+#include <fcntl.h>
+#include <errno.h>
+
+#include "sem.h"
+
+
+/* 信号量初始化（赋值）函数*/
+int init_sem(int sem_id, int init_value)
+{
+    union semun sem_union;
+    sem_union.val = init_value; /* init_value 为初始值 */
+
+    if (semctl(sem_id, 0, SETVAL, sem_union) == -1)
+    {
+        perror("Initialize semaphore");
+        return -1;
+    }
+
+    return 0;
+}
+
+/* 从系统中删除信号量的函数 */
+int del_sem(int sem_id)
+{
+    union semun sem_union;
+    if (semctl(sem_id, 0, IPC_RMID, sem_union) == -1)
+    {
+        perror("Delete semaphore");
+        return -1;
+    }
+}
+
+/* P 操作函数 */
+int sem_p(int sem_id)
+{
+    struct sembuf sem_b;
+    sem_b.sem_num = 0; /* 单个信号量的编号应该为 0 */
+    sem_b.sem_op = -1; /* 表示 P 操作 */
+    sem_b.sem_flg = SEM_UNDO; /* 系统自动释放将会在系统中残留的信号量*/
+
+    if (semop(sem_id, &sem_b, 1) == -1)
+    {
+        perror("P operation");
+        return -1;
+    }
+    return 0;
+}
+
+/* V 操作函数*/
+int sem_v(int sem_id)
+{
+    struct sembuf sem_b;
+    sem_b.sem_num = 0; /* 单个信号量的编号应该为 0 */
+    sem_b.sem_op = 1; /* 表示 V 操作 */
+    sem_b.sem_flg = SEM_UNDO; /* 系统自动释放将会在系统中残留的信号量*/
+
+    if (semop(sem_id, &sem_b, 1) == -1)
+    {
+        perror("V operation");
+        return -1;
+    }
+    return 0;
+}
diff --git a/base_code/system_programing/shm_read/sources/shm_read.c b/base_code/system_programing/shm_read/sources/shm_read.c
new file mode 100644
index 0000000000000000000000000000000000000000..0efff23fee5d34c45bd85aaab8248ea4035dab4f
--- /dev/null
+++ b/base_code/system_programing/shm_read/sources/shm_read.c
@@ -0,0 +1,80 @@
+#include <sys/types.h>
+#include <sys/shm.h>
+#include <sys/sem.h>
+#include <sys/ipc.h>
+#include <unistd.h>
+#include <stdlib.h>
+#include <stdio.h>
+#include <string.h>
+#include <sys/stat.h>
+#include <fcntl.h>
+#include <errno.h>
+
+#include "sem.h"
+
+int main(void)
+{
+	int running = 1;//程序是否继续运行的标志
+	char *shm = NULL;//分配的共享内存的原始首地址
+	int shmid;//共享内存标识符
+    int semid;//信号量标识符
+
+	//创建共享内存
+	shmid = shmget((key_t)1234, 4096, 0666 | IPC_CREAT);
+	if(shmid == -1)
+	{
+		fprintf(stderr, "shmget failed\n");
+		exit(EXIT_FAILURE);
+	}
+
+	//将共享内存连接到当前进程的地址空间
+	shm = shmat(shmid, 0, 0);
+	if(shm == (void*)-1)
+	{
+		fprintf(stderr, "shmat failed\n");
+		exit(EXIT_FAILURE);
+	}
+	printf("\nMemory attached at %p\n", shm);
+
+	/** 打开信号量，不存在则创建 */
+    semid = semget((key_t)6666, 1, 0666|IPC_CREAT); /* 创建一个信号量*/
+
+	if(semid == -1)
+	{
+		printf("sem open fail\n");
+		exit(EXIT_FAILURE); 
+	}
+
+	init_sem(semid, 0);
+
+	while(running)//读取共享内存中的数据
+	{
+		/** 等待心信号量 */
+		if(sem_p(semid) == 0)
+		{
+			printf("You wrote: %s", shm);
+			sleep(rand() % 3);
+			
+			//输入了end，退出循环（程序）
+			if(strncmp(shm, "end", 3) == 0)
+				running = 0;
+		}
+	}
+
+	del_sem(semid);	/** 删除信号量 */
+
+	//把共享内存从当前进程中分离
+	if(shmdt(shm) == -1)
+	{
+		fprintf(stderr, "shmdt failed\n");
+		exit(EXIT_FAILURE);
+	}
+	
+	//删除共享内存
+	if(shmctl(shmid, IPC_RMID, 0) == -1)
+	{
+		fprintf(stderr, "shmctl(IPC_RMID) failed\n");
+		exit(EXIT_FAILURE);
+	}
+	exit(EXIT_SUCCESS);
+}
\ No newline at end of file
diff --git a/base_code/system_programing/shm_write/Makefile b/base_code/system_programing/shm_write/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..68757e0fa83d3077712f82677465b2a2741cc70c
--- /dev/null
+++ b/base_code/system_programing/shm_write/Makefile
@@ -0,0 +1,78 @@
+
+#生成可执行文件的名称
+Target = shm_write_demo
+ARCH ?= x86
+#编译器CC
+#根据传入的参数ARCH，确定使用的编译器
+#默认使用gcc编译器
+#make ARCH=arm 时使用ARM-GCC编译器
+ifeq ($(ARCH), x86)
+	CC = gcc
+else
+	CC = arm-linux-gnueabihf-gcc
+endif
+#存放中间文件的路径
+build_dir = build_$(ARCH)
+#存放源文件的文件夹
+src_dir =  sources
+#存放头文件的文件夹
+inc_dir = includes .
+
+#源文件
+sources = $(foreach dir,$(src_dir),$(wildcard $(dir)/*.c))
+#目标文件（*.o）
+objects = $(patsubst %.c,$(build_dir)/%.o,$(notdir $(sources)))
+#头文件
+includes = $(foreach dir,$(inc_dir),$(wildcard $(dir)/*.h))
+
+#目标依赖文件
+DEP_FILES := $(patsubst %, .%.d,$(objects))
+DEP_FILES := $(wildcard $(DEP_FILES))
+
+#判断依赖文件是否存在
+ifneq ($(DEP_FILES),)
+#如果存在依赖文件，需要导入依赖文件
+include $(DEP_FILES)
+endif
+
+#编译参数
+#指定头文件的路径
+CFLAGS = $(patsubst %, -I%, $(inc_dir)) -MD -MF $(@D)/.$(@F).d
+
+#链接过程
+$(build_dir)/$(Target) : $(objects)  | create_build
+	$(CC) $^ -o $@
+
+#编译工程
+#编译src文件夹中的源文件，并将生成的目标文件放在objs文件夹中
+$(build_dir)/%.o : $(src_dir)/%.c $(includes) | create_build
+	$(CC) -c $(CFLAGS) $< -o $@
+
+
+#以下为伪目标，调用方式：make 伪目标
+#clean：用于Clean Project
+#check：用于检查某个变量的值
+.PHONY:clean cleanall check create_build
+#按架构删除
+clean:
+	rm -rf $(build_dir)
+
+#全部删除
+cleanall:
+	rm -rf build_x86 build_arm
+
+#命令前带"@",表示不在终端上输出执行的命令
+#这个目标主要是用来调试Makefile时输出一些内容
+check:
+	@echo $(CFLAGS)
+	@echo $(CURDIR)
+	@echo $(src_dir)
+	@echo $(sources)
+	@echo $(objects)
+
+
+#创建一个新目录create，用于存放过程文件
+create_build:
+	@mkdir -p $(build_dir)
+
+
diff --git a/base_code/system_programing/shm_write/includes/sem.h b/base_code/system_programing/shm_write/includes/sem.h
new file mode 100644
index 0000000000000000000000000000000000000000..68d14a932427dc480b3ac4d280192094f276c4d1
--- /dev/null
+++ b/base_code/system_programing/shm_write/includes/sem.h
@@ -0,0 +1,21 @@
+#ifndef _SEM_H_
+#define _SEM_H_
+
+
+union semun
+{
+    int val;
+    struct semid_ds *buf;
+    unsigned short *array;
+};
+
+int init_sem(int sem_id, int init_value);
+int del_sem(int sem_id);
+int sem_p(int sem_id);
+int sem_v(int sem_id);
+
+
+
+
+#endif
+
diff --git a/base_code/system_programing/shm_write/sources/sem.c b/base_code/system_programing/shm_write/sources/sem.c
new file mode 100644
index 0000000000000000000000000000000000000000..b2d2b6e9fc51cee6edb3e5b1aa2c9d46f59c3d08
--- /dev/null
+++ b/base_code/system_programing/shm_write/sources/sem.c
@@ -0,0 +1,190 @@
+/** sem.c */
+
+/**
+ * 多进程编程中需要关注进程间的同步及互斥问题。同步是指多个进程为了完成同一个任务相互协作运行，而互斥是指不同的进程为了争夺有限的系统资源（硬件或软件资源）而相互竞争运行。
+ * 信号量是用来解决进程间同步与互斥问题的一种进程间通信机制，它是一个特殊的变量，变量的值代表着关联资源的可用数量。 若等于 0 则意味着目前没有可用的资源。
+ * 根据信号量的值可以将信号量分为二值信号量和计数信号量：
+ *   二值信号量： 信号量只有 0 和 1 两种值。 若资源被锁住，信号量值为 0，若资源可用则信号量值为 1；
+ *   计数信号量： 信号量可在 0 到一个大于 1 的数（最大 32767） 之间取值。该计数表示可用资源的个数。
+ * 信号量只能进行两个原子操作： P 操作： V 操作。
+ *   P 操作：如果有可用的资源（信号量值>0），则占用一个资源（将信号量值减 1）；如果没有可用的资源（信号量值=0），则进程被阻塞直到系统将资源分配给该进程（进入信号量的等待队列，等到资源后再唤醒该进程）
+ *   V 操作：如果在该信号量的等待队列中有进程在等待资源，则唤醒一个阻塞进程；如果没有进程等待它，则释放一个资源（给信号量值加 1）
+ * 
+ * POSIX 提供两类信号量： 有名信号量和基于内存的信号量（也称无名信号量）。有名信号量可以让不同的进程通过信号量的名字获取到信号量，
+ * 而基于内存的信号量只能放置在进程间共享内存区域中。有名信号量与基于内存的信号量的初始化和销毁方式不同。
+ * 
+ * 创建或打开有名信号量：
+ * sem_t *sem_open(const char *name, int oflag);
+ * sem_t *sem_open(const char *name, int oflag,mode_t mode, unsigned int value);
+ * 信号量的类型为 sem_t， 该结构里记录着当前共享资源的数目。 sem_open()函数成功返回指向信号量的指针，失败返回 SEM_FAILED
+ * 函数参数如下：
+ *  参数 name 为信号量的名字，两个不同的进程可以通过传递相同的名字打开同一个信号量；
+ *  oflag 可以是以下标志的或值：
+ *   O_CREAT：如果name指定的信号量不存在则创建，此时必须给出 mode和value值；
+ *   O_EXCL：如果 name 指定的信号量存在，而 oflag 指定为 O_CREAT | O_EXCL，则 sem_open()函数返回错误。
+ *  mode 为信号量的权限位，类似于 open()函数；
+ *  value 为信号量的初始化值。
+ * 
+ * 关闭有名信号量,成功返回 0，失败返回-1:
+ * int sem_close(sem_t *sem); 
+ * 
+ * 删除有名信号量：
+ * int sem_unlink(const char *name); 
+ * 
+ * 
+ * 初始化基于内存信号量：
+ * int sem_init(sem_t *sem, int pshared, unsigned int value);
+ * 函数成功返回 0，失败返回-1；
+ * 参数 sem 为需要初始化的信号量的指针； pshared 值如果为 0 表示该信号量只能在线程内部使用，否则为进程间使用。
+ * 在进程间使用时，该信号量需要放在共享内存处； value 为信号量的初始化值，代表的资源数。
+ * 
+ * 销毁基于内存信号量：
+ * int sem_destroy(sem_t *sem);
+ * 该函数只能销毁由 sem_init()初始化的信号量，函数成功返回 0，否则返回-1。参数 sem 指出需要销毁的信号量。
+ */
+
+
+/**
+ * 信号量的 P 操作由 sem_wait()函数来完成:
+ * int sem_wait(sem_t *sem);
+ * 如果信号量的值大于 0， sem_wait()函数将信号量值减 1 并立即返回，代表着获取到资源，如果信号量值等于 0 则调用进程（线程）将进入睡眠状态，直到该值变为大于 0 时再将它减 1 后才返回。
+ * 函数成功返回 0，否则返回-1；参数 sem 为需要操作的信号量。
+ * 
+ * 信号量的 V 操作有 sem_post()函数来完成:
+ * int sem_post(sem_t *sem);
+ * 当一个进程（线程） 使用完某个信号量时，它应该调用 sem_post()来告诉系统申请的资源已经使用完毕。 sem_post()函数与 sem_wait()函数的功能正好相反，
+ * 它把所指定的信号量的值加 1，然后唤醒正在等待该信号量的任意进程（线程） 。
+ * 函数成功返回 0，否则返回-1；参数 sem 为需要操作的信号量。
+ */
+/** 通过信号量同步源码见共享内存章节(以上信号量接口是POSIX接口) */
+
+
+/**
+ * 头文件：
+ * #include <sys/ipc.h>
+ * #include <sys/sem.h>
+ * 
+ * 在 Linux 系统中，使用信号量通常分为以下几个步骤：
+ * （1）创建信号量或获得在系统已存在的信号量，此时需要调用 semget()函数。不同进程通过使用同一个信号量键值来获得同一个信号量。
+ * （2）初始化信号量，此时使用 semctl()函数的 SETVAL 操作。当使用二值信号量时，通常将信号量初始化为 1。
+ * （3）进行信号量的 PV 操作，此时调用 semop()函数。这一步是实现进程之间的同步和互斥的核心工作部分。
+ * （4）如果不需要信号量，则从系统中删除它，此时使用 semctl()函数的 IPC_RMID 操作。此时需要注意，在程序中不应该出现对已经被删除的信号量的操作。
+ * 
+ * 函数原型 int semget(key_t key, int nsems, int semflg)
+ * 参数:
+ *  key：信号量的键值，多个进程可以通过它访问同一个信号量，其中有个特殊值 IPC_PRIVATE。它用于创建当前进程的私有信号量
+ *  nsems：需要创建的信号量数目，通常取值为 1
+ *  semflg：同 open()函数的权限位，也可以用八进制表示法，其中使用IPC_CREAT 标志创建新的信号量，即使该信号量已经存在具有同一个键值的信号量
+ *          已在系统中存在），也不会出错。如果同时使用 IPC_EXCL 标志可以创建一个新的唯一的信号量，此时如果该信号量已经存在，该函数会返回出错
+ * 返回
+ *  成功：信号量标识符，在信号量的其他函数中都会使用该值
+ *  出错：-1
+ * 
+ * 函数原型 int semctl(int semid, int semnum, int cmd, union semun arg)
+ * 函数传入值：
+ * semid： semget()函数返回的信号量标识符
+ * semnum：信号量编号，当使用信号量集时才会被用到。通常取值为 0，就是使用单个信号量（也是第一个信号量）
+ * cmd：指定对信号量的各种操作，当使用单个信号量（而不是信号量集）时，常用的有以下几种：
+ *  IPC_STAT：获得该信号量（或者信号量集合）的 semid_ds 结构，并存放在由第 4 个参数 arg 的 buf 指向的 semid_ds 结构中。 semid_ds 是在系统中描述信号量的数据结构。
+ *  IPC_SETVAL：将信号量值设置为 arg 的 val 值
+ *  IPC_GETVAL：返回信号量的当前值
+ *  IPC_RMID：从系统中，删除信号量（或者信号量集）
+ * arg：是 union semnn 结构，该结构可能在某些系统中并不给出定义，此时必须由程序员自己定义
+ * union semun
+ * {
+ *  int val;
+ *  struct semid_ds *buf;
+ *  unsigned short *array;
+ * }
+ * 函数返回值
+ *  成功：根据 cmd 值的不同而返回不同的值
+ *    IPC_STAT、 IPC_SETVAL、 IPC_RMID：返回 0
+ *    IPC_GETVAL：返回信号量的当前值
+ *  出错： -1
+ * 
+ * 函数原型 int semop(int semid, struct sembuf *sops, size_t nsops)
+ * 函数传入值
+ * semid： semget()函数返回的信号量标识符
+ * sops：指向信号量操作数组，一个数组包括以下成员：
+ * struct sembuf
+ * {
+ *  short sem_num;  信号量编号，使用单个信号量时，通常取值为 0
+ *  short sem_op;   信号量操作：取值为-1 则表示 P 操作，取值为+1 则表示 V 操作
+ *  short sem_flg;  通常设置为 SEM_UNDO。这样在进程没释放信号量而退出时，系统自动释放该进程中未释放的信号量
+ * }
+ * nsops：操作数组 sops 中的操作个数（元素数目），通常取值为 1（一个操作）
+ * 函数返回值 成功：信号量标识符，在信号量的其他函数中都会使用该值
+ */
+
+
+#include <sys/sem.h>
+#include <sys/ipc.h>
+#include <unistd.h>
+#include <stdlib.h>
+#include <stdio.h>
+#include <string.h>
+#include <sys/shm.h>
+#include <sys/stat.h>
+#include <fcntl.h>
+#include <errno.h>
+
+#include "sem.h"
+
+
+/* 信号量初始化（赋值）函数*/
+int init_sem(int sem_id, int init_value)
+{
+    union semun sem_union;
+    sem_union.val = init_value; /* init_value 为初始值 */
+
+    if (semctl(sem_id, 0, SETVAL, sem_union) == -1)
+    {
+        perror("Initialize semaphore");
+        return -1;
+    }
+
+    return 0;
+}
+
+/* 从系统中删除信号量的函数 */
+int del_sem(int sem_id)
+{
+    union semun sem_union;
+    if (semctl(sem_id, 0, IPC_RMID, sem_union) == -1)
+    {
+        perror("Delete semaphore");
+        return -1;
+    }
+}
+
+/* P 操作函数 */
+int sem_p(int sem_id)
+{
+    struct sembuf sem_b;
+    sem_b.sem_num = 0; /* 单个信号量的编号应该为 0 */
+    sem_b.sem_op = -1; /* 表示 P 操作 */
+    sem_b.sem_flg = SEM_UNDO; /* 系统自动释放将会在系统中残留的信号量*/
+
+    if (semop(sem_id, &sem_b, 1) == -1)
+    {
+        perror("P operation");
+        return -1;
+    }
+    return 0;
+}
+
+/* V 操作函数*/
+int sem_v(int sem_id)
+{
+    struct sembuf sem_b;
+    sem_b.sem_num = 0; /* 单个信号量的编号应该为 0 */
+    sem_b.sem_op = 1; /* 表示 V 操作 */
+    sem_b.sem_flg = SEM_UNDO; /* 系统自动释放将会在系统中残留的信号量*/
+
+    if (semop(sem_id, &sem_b, 1) == -1)
+    {
+        perror("V operation");
+        return -1;
+    }
+    return 0;
+}
diff --git a/base_code/system_programing/shm_write/sources/shm_write.c b/base_code/system_programing/shm_write/sources/shm_write.c
new file mode 100644
index 0000000000000000000000000000000000000000..ccc241d7972fdbc4dad7a31019270156a49ebd52
--- /dev/null
+++ b/base_code/system_programing/shm_write/sources/shm_write.c
@@ -0,0 +1,74 @@
+#include <sys/types.h>
+#include <sys/shm.h>
+#include <sys/sem.h>
+#include <sys/ipc.h>
+#include <unistd.h>
+#include <stdlib.h>
+#include <stdio.h>
+#include <string.h>
+#include <sys/stat.h>
+#include <fcntl.h>
+#include <errno.h>
+
+#include "sem.h"
+
+
+int main()
+{
+	int running = 1;
+	void *shm = NULL;
+	struct shared_use_st *shared = NULL;
+	char buffer[BUFSIZ + 1];//用于保存输入的文本
+	int shmid;
+	int semid;;//信号量标识符
+
+	//创建共享内存
+	shmid = shmget((key_t)1234, 4096, 0644 | IPC_CREAT);
+	if(shmid == -1)
+	{
+		fprintf(stderr, "shmget failed\n");
+		exit(EXIT_FAILURE);
+	}
+	//将共享内存连接到当前进程的地址空间
+	shm = shmat(shmid, (void*)0, 0);
+	if(shm == (void*)-1)
+	{
+		fprintf(stderr, "shmat failed\n");
+		exit(EXIT_FAILURE);
+	}
+	printf("Memory attached at %p\n", shm);
+
+	/** 打开信号量，不存在则创建 */
+    semid = semget((key_t)6666, 1, 0666|IPC_CREAT);
+
+	if(semid == -1)
+	{
+		printf("sem open fail\n");
+		exit(EXIT_FAILURE); 
+	}
+
+
+
+	while(running)//向共享内存中写数据
+	{
+		//向共享内存中写入数据
+		printf("Enter some text: ");
+		fgets(buffer, BUFSIZ, stdin);
+		strncpy(shm, buffer, 4096);
+
+		sem_v(semid);/* 释放信号量 */
+
+		//输入了end，退出循环（程序）
+		if(strncmp(buffer, "end", 3) == 0)
+			running = 0;
+	}
+
+	//把共享内存从当前进程中分离
+	if(shmdt(shm) == -1)
+	{
+		fprintf(stderr, "shmdt failed\n");
+		exit(EXIT_FAILURE);
+	}
+	sleep(2);
+	exit(EXIT_SUCCESS);
+}
\ No newline at end of file
diff --git a/base_code/system_programing/sigaction/Makefile b/base_code/system_programing/sigaction/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..e8b42515bd9120538ee5f97747b1f00be723b1cb
--- /dev/null
+++ b/base_code/system_programing/sigaction/Makefile
@@ -0,0 +1,78 @@
+
+#生成可执行文件的名称
+Target = sigaction_demo
+ARCH ?= x86
+#编译器CC
+#根据传入的参数ARCH，确定使用的编译器
+#默认使用gcc编译器
+#make ARCH=arm 时使用ARM-GCC编译器
+ifeq ($(ARCH), x86)
+	CC = gcc
+else
+	CC = arm-linux-gnueabihf-gcc
+endif
+#存放中间文件的路径
+build_dir = build_$(ARCH)
+#存放源文件的文件夹
+src_dir =  sources
+#存放头文件的文件夹
+inc_dir = includes .
+
+#源文件
+sources = $(foreach dir,$(src_dir),$(wildcard $(dir)/*.c))
+#目标文件（*.o）
+objects = $(patsubst %.c,$(build_dir)/%.o,$(notdir $(sources)))
+#头文件
+includes = $(foreach dir,$(inc_dir),$(wildcard $(dir)/*.h))
+
+#目标依赖文件
+DEP_FILES := $(patsubst %, .%.d,$(objects))
+DEP_FILES := $(wildcard $(DEP_FILES))
+
+#判断依赖文件是否存在
+ifneq ($(DEP_FILES),)
+#如果存在依赖文件，需要导入依赖文件
+include $(DEP_FILES)
+endif
+
+#编译参数
+#指定头文件的路径
+CFLAGS = $(patsubst %, -I%, $(inc_dir)) -MD -MF $(@D)/.$(@F).d
+
+#链接过程
+$(build_dir)/$(Target) : $(objects)  | create_build
+	$(CC) $^ -o $@
+
+#编译工程
+#编译src文件夹中的源文件，并将生成的目标文件放在objs文件夹中
+$(build_dir)/%.o : $(src_dir)/%.c $(includes) | create_build
+	$(CC) -c $(CFLAGS) $< -o $@
+
+
+#以下为伪目标，调用方式：make 伪目标
+#clean：用于Clean Project
+#check：用于检查某个变量的值
+.PHONY:clean cleanall check create_build
+#按架构删除
+clean:
+	rm -rf $(build_dir)
+
+#全部删除
+cleanall:
+	rm -rf build_x86 build_arm
+
+#命令前带"@",表示不在终端上输出执行的命令
+#这个目标主要是用来调试Makefile时输出一些内容
+check:
+	@echo $(CFLAGS)
+	@echo $(CURDIR)
+	@echo $(src_dir)
+	@echo $(sources)
+	@echo $(objects)
+
+
+#创建一个新目录create，用于存放过程文件
+create_build:
+	@mkdir -p $(build_dir)
+
+
diff --git a/base_code/system_programing/sigaction/sources/sigaction.c b/base_code/system_programing/sigaction/sources/sigaction.c
new file mode 100644
index 0000000000000000000000000000000000000000..19a84f853c035c9e8e6ceee4532683ab7242d2a9
--- /dev/null
+++ b/base_code/system_programing/sigaction/sources/sigaction.c
@@ -0,0 +1,136 @@
+/** signal.c */
+
+/**
+ * 一个进程可以决定在该进程中需要对哪些信号进行什么样的处理。例如，一个进程可以选择忽略某些信号而只处理其他一些信号，
+ * 另外，一个进程还可以选择如何处理信号。总之，这些都是与特定的进程相联系的。因此，首先就要建立进程与其信号之间的对
+ * 应关系，这就是信号的处理。
+ * 
+ * 如果进程要处理某一信号，那么就要在进程中安装该信号。安装信号主要用来确定信号值及进程针对该信号值的动作之间的映射关系，
+ * 即进程将要处理哪个信号；该信号被传递给进程时，将执行何种操作。
+ * 
+ * linux主要有两个函数实现信号的安装：signal()、sigaction()。其中signal()在可靠信号系统调用的基础上实现, 是库函数。
+ * 它只有两个参数，不支持信号传递信息，主要是用于前32种非实时信号的安装；
+ * 而sigaction()是较新的函数（由两个系统调用实现：sys_signal以及sys_rt_sigaction），有三个参数，支持信号传递信息，主要用来与 
+ * sigqueue() 系统调用配合使用，当然，sigaction()同样支持非实时信号的安装。sigaction()优于signal()主要体现在支持信号带有参数。
+ * 
+ * 常见信号的含义及其默认操作：
+ * 信 号 名                     含 义                               默 认 操 作
+ * 
+ * SIGHUP       该信号在用户终端连接（正常或非正常）结束时发出，              终止
+ *              通常是在终端的控 制进程结束时，通知同一会话内的      
+ *              各个作业与控制终端不再关联 
+ * 
+ * SIGINT       该信号在用户键入 INTR 字符（通常是 Ctrl-C）时发出，         终止
+ *              终端驱动程序发送此信号并送到前台进程中的每一个进程            
+ * 
+ * SIGQUIT      该信号和 SIGINT 类似，                                  终止
+ *              但由 QUIT 字符（通常是 Ctrl-\）来控制                     
+ * 
+ * SIGILL       该信号在一个进程企图执行一条非法指令时（可执行文件本          终止
+ *              身出现错误，或者试图执行数据段、堆栈溢出时）发出 
+ * 
+ * SIGFPE       该信号在发生致命的算术运算错误时发出。这里不仅包括浮点        终止  
+ *              运算错误，还包括溢出及除数为 0 等其他所有的算术错误         
+ * 
+ * SIGKILL      该信号用来立即结束程序的运行，                            终止
+ *              并且不能被阻塞、处理或忽略
+ * 
+ * SIGALRM      该信号当一个定时器到时的时候发出                          终止
+ * 
+ * SIGSTOP      该信号用于暂停一个进程，且不能被阻塞、处理或忽略            暂停进程
+ * 
+ * SIGTSTP      该信号用于交互停止进程，用户键入 SUSP 字符时              停止进程
+ *              （通常是 Ctrl+Z）发出这个信号                       
+ * 
+ * SIGCHLD      子进程改变状态时，父进程会收到这个信号                     忽略
+ * 
+ * SIGABORT      进程异常终止时发出
+ */
+
+/** 
+ * Linux 系统为大部分信号定义了缺省处理方法，当信号的缺省处理方法不满足需求时，可通过 sigaction()函数进行改变
+ * 
+ * 函数原型: int sigaction(int signum, const struct sigaction *act, struct sigaction *oldact)
+ * 
+ * signum：信号代码，可以为除 SIGKILL 及 SIGSTOP 外的任何一个特定有效的信号
+ * act：指向结构 sigaction 的一个实例的指针，指定对特定信号的处理
+ * oldact：保存原来对相应信号的处理
+ * 
+ * struct sigaction {
+ *  void (*sa_handler)(int);
+ *  void (*sa_sigaction)(int, siginfo_t *, void *);
+ *  sigset_t sa_mask;
+ *  int sa_flags;
+ *  void (*sa_restorer)(void);
+ * };
+ * 
+ *   sa_handler 是一个函数指针， 用来指定信号发生时调用的处理函数；
+ *   sa_sigaction 则是另外一个信号处理函数，它有三个参数，可以获得关于信号的更
+ * 详细的信息； 当 sa_flags 成员的值包含了 SA_SIGINFO 标志时，系统将使用
+ * sa_sigaction 函数作为信号的处理函数，否则将使用 sa_handler；
+ *   sa_mask 成员用来指定在信号处理函数执行期间需要被屏蔽的信号，特别是当某个
+ * 信号正被处理时，它本身会被自动地放入进程的信号掩码，因此在信号处理函数执
+ * 行期间， 这个信号都不会再度发生。可以使用 sigemptyset()、 sigaddset()、 sigdelset()
+ * 分别对这个信号集进行清空、增加和删除被屏蔽信号的操作；
+ *   sa_flags 成员用于指定信号处理的行为，它可以是以下值的"按位或" 组合：
+ *       SA_RESTART：使被信号打断的系统调用自动重新发起；
+ *       SA_NOCLDSTOP：使父进程在它的子进程暂停或继续运行时不会收到SIGCHLD 信号；
+ *       SA_NOCLDWAIT：使父进程在它的子进程退出时不会收到 SIGCHLD 信号，这时子进程如果退出也不会成为僵尸进程；
+ *       SA_NODEFER：使对信号的屏蔽无效，即在信号处理函数的执行期间仍能发出这个信号；
+ *       SA_RESETHAND：信号被处理后重新设置处理方式到默认值；
+ *       SA_SIGINFO：使用 sa_sigaction 成员而不是 sa_handler 作为信号处理函数。
+ *   re_restorer 成员则是一个已经废弃的数据域，不要使用。
+ *  
+ * retern:
+ *   成功：以前的信号处理配置
+ *   出错：-1
+ * 
+*/
+
+#include <unistd.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <signal.h>
+#include <sys/types.h>
+#include <sys/wait.h>
+
+
+/** 信号处理函数 */
+void signal_handler(int sig)
+{
+    printf("\nthis signal numble is %d \n",sig);
+
+    if (sig == SIGINT) {
+        printf("I have get SIGINT!\n\n");
+        printf("The signal is automatically restored to the default handler!\n\n");
+        /** 信号自动恢复为默认处理函数 */
+    }
+
+}
+
+int main(void)
+{
+    struct sigaction act;
+
+    printf("this is sigaction function test demo!\n\n");
+
+    /** 设置信号处理的回调函数 */
+    act.sa_handler = signal_handler;
+    
+    /* 清空屏蔽信号集 */
+    sigemptyset(&act.sa_mask); 
+
+    /** 在处理完信号后恢复默认信号处理 */
+    act.sa_flags = SA_RESETHAND;
+
+    sigaction(SIGINT, &act, NULL);
+
+    while (1)
+    {
+        printf("waiting for the SIGINT signal , please enter \"ctrl + c\"...\n\n");
+        sleep(1);
+    }
+    
+    exit(0);
+}
+
diff --git a/base_code/system_programing/signal/Makefile b/base_code/system_programing/signal/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..c7c674c1185c8b537cdb0c9d2138b196b7f87c09
--- /dev/null
+++ b/base_code/system_programing/signal/Makefile
@@ -0,0 +1,78 @@
+
+#生成可执行文件的名称
+Target = signal_demo
+ARCH ?= x86
+#编译器CC
+#根据传入的参数ARCH，确定使用的编译器
+#默认使用gcc编译器
+#make ARCH=arm 时使用ARM-GCC编译器
+ifeq ($(ARCH), x86)
+	CC = gcc
+else
+	CC = arm-linux-gnueabihf-gcc
+endif
+#存放中间文件的路径
+build_dir = build_$(ARCH)
+#存放源文件的文件夹
+src_dir =  sources
+#存放头文件的文件夹
+inc_dir = includes .
+
+#源文件
+sources = $(foreach dir,$(src_dir),$(wildcard $(dir)/*.c))
+#目标文件（*.o）
+objects = $(patsubst %.c,$(build_dir)/%.o,$(notdir $(sources)))
+#头文件
+includes = $(foreach dir,$(inc_dir),$(wildcard $(dir)/*.h))
+
+#目标依赖文件
+DEP_FILES := $(patsubst %, .%.d,$(objects))
+DEP_FILES := $(wildcard $(DEP_FILES))
+
+#判断依赖文件是否存在
+ifneq ($(DEP_FILES),)
+#如果存在依赖文件，需要导入依赖文件
+include $(DEP_FILES)
+endif
+
+#编译参数
+#指定头文件的路径
+CFLAGS = $(patsubst %, -I%, $(inc_dir)) -MD -MF $(@D)/.$(@F).d
+
+#链接过程
+$(build_dir)/$(Target) : $(objects)  | create_build
+	$(CC) $^ -o $@
+
+#编译工程
+#编译src文件夹中的源文件，并将生成的目标文件放在objs文件夹中
+$(build_dir)/%.o : $(src_dir)/%.c $(includes) | create_build
+	$(CC) -c $(CFLAGS) $< -o $@
+
+
+#以下为伪目标，调用方式：make 伪目标
+#clean：用于Clean Project
+#check：用于检查某个变量的值
+.PHONY:clean cleanall check create_build
+#按架构删除
+clean:
+	rm -rf $(build_dir)
+
+#全部删除
+cleanall:
+	rm -rf build_x86 build_arm
+
+#命令前带"@",表示不在终端上输出执行的命令
+#这个目标主要是用来调试Makefile时输出一些内容
+check:
+	@echo $(CFLAGS)
+	@echo $(CURDIR)
+	@echo $(src_dir)
+	@echo $(sources)
+	@echo $(objects)
+
+
+#创建一个新目录create，用于存放过程文件
+create_build:
+	@mkdir -p $(build_dir)
+
+
diff --git a/base_code/system_programing/signal/sources/signal.c b/base_code/system_programing/signal/sources/signal.c
new file mode 100644
index 0000000000000000000000000000000000000000..0f439c904d18bf6bd91a4c98ff5ec7cbd2e61fcf
--- /dev/null
+++ b/base_code/system_programing/signal/sources/signal.c
@@ -0,0 +1,176 @@
+/** signal.c */
+
+/**
+ * 一个进程可以决定在该进程中需要对哪些信号进行什么样的处理。例如，一个进程可以选择忽略某些信号而只处理其他一些信号，
+ * 另外，一个进程还可以选择如何处理信号。总之，这些都是与特定的进程相联系的。因此，首先就要建立进程与其信号之间的对
+ * 应关系，这就是信号的处理。
+ * 
+ * 如果进程要处理某一信号，那么就要在进程中安装该信号。安装信号主要用来确定信号值及进程针对该信号值的动作之间的映射关系，
+ * 即进程将要处理哪个信号；该信号被传递给进程时，将执行何种操作。
+ * 
+ * linux主要有两个函数实现信号的安装：signal()、sigaction()。其中signal()在可靠信号系统调用的基础上实现, 是库函数。
+ * 它只有两个参数，不支持信号传递信息，主要是用于前32种非实时信号的安装；
+ * 而sigaction()是较新的函数（由两个系统调用实现：sys_signal以及sys_rt_sigaction），有三个参数，支持信号传递信息，主要用来与 
+ * sigqueue() 系统调用配合使用，当然，sigaction()同样支持非实时信号的安装。sigaction()优于signal()主要体现在支持信号带有参数。
+ * 
+ * 常见信号的含义及其默认操作：
+ * 信 号 名                     含 义                               默 认 操 作
+ * 
+ * SIGHUP       该信号在用户终端连接（正常或非正常）结束时发出，              终止
+ *              通常是在终端的控 制进程结束时，通知同一会话内的      
+ *              各个作业与控制终端不再关联 
+ * 
+ * SIGINT       该信号在用户键入 INTR 字符（通常是 Ctrl-C）时发出，         终止
+ *              终端驱动程序发送此信号并送到前台进程中的每一个进程            
+ * 
+ * SIGQUIT      该信号和 SIGINT 类似，                                  终止
+ *              但由 QUIT 字符（通常是 Ctrl-\）来控制                     
+ * 
+ * SIGILL       该信号在一个进程企图执行一条非法指令时（可执行文件本          终止
+ *              身出现错误，或者试图执行数据段、堆栈溢出时）发出 
+ * 
+ * SIGFPE       该信号在发生致命的算术运算错误时发出。这里不仅包括浮点        终止  
+ *              运算错误，还包括溢出及除数为 0 等其他所有的算术错误         
+ * 
+ * SIGKILL      该信号用来立即结束程序的运行，                            终止
+ *              并且不能被阻塞、处理或忽略
+ * 
+ * SIGALRM      该信号当一个定时器到时的时候发出                          终止
+ * 
+ * SIGSTOP      该信号用于暂停一个进程，且不能被阻塞、处理或忽略            暂停进程
+ * 
+ * SIGTSTP      该信号用于交互停止进程，用户键入 SUSP 字符时              停止进程
+ *              （通常是 Ctrl+Z）发出这个信号                       
+ * 
+ * SIGCHLD      子进程改变状态时，父进程会收到这个信号                     忽略
+ * 
+ * SIGABORT      进程异常终止时发出
+ */
+
+/**
+ * 函数原型: void (*signal(int signum, void (*handler))(int)))(int); 
+ * 如果该函数原型不容易理解的话，可以参考下面的分解方式来理解： 
+ * typedef void (*sighandler_t)(int)； 
+ * sighandler_t signal(int signum, sighandler_t handler)); 
+ * 
+ * signum：指定信号代码
+ * handler：
+ *   SIG_IGN：忽略该信号
+ *   SIG_DFL：采用系统默认方式处理信号
+ *   自定义的信号处理函数指针
+ * 
+ * retern:
+ *   成功：以前的信号处理配置
+ *   出错：-1
+ * 
+ */
+
+/** 
+ * Linux 系统为大部分信号定义了缺省处理方法，当信号的缺省处理方法不满足需求时，可通过 sigaction()函数进行改变
+ * 
+ * 函数原型: int sigaction(int signum, const struct sigaction *act, struct sigaction *oldact)
+ * 
+ * signum：信号代码，可以为除 SIGKILL 及 SIGSTOP 外的任何一个特定有效的信号
+ * act：指向结构 sigaction 的一个实例的指针，指定对特定信号的处理
+ * oldact：保存原来对相应信号的处理
+ * 
+ * struct sigaction {
+ *  void (*sa_handler)(int);
+ *  void (*sa_sigaction)(int, siginfo_t *, void *);
+ *  sigset_t sa_mask;
+ *  int sa_flags;
+ *  void (*sa_restorer)(void);
+ * };
+ * 
+ *   sa_handler 是一个函数指针， 用来指定信号发生时调用的处理函数；
+ *   sa_sigaction 则是另外一个信号处理函数，它有三个参数，可以获得关于信号的更
+ * 详细的信息； 当 sa_flags 成员的值包含了 SA_SIGINFO 标志时，系统将使用
+ * sa_sigaction 函数作为信号的处理函数，否则将使用 sa_handler；
+ *   sa_mask 成员用来指定在信号处理函数执行期间需要被屏蔽的信号，特别是当某个
+ * 信号正被处理时，它本身会被自动地放入进程的信号掩码，因此在信号处理函数执
+ * 行期间， 这个信号都不会再度发生。可以使用 sigemptyset()、 sigaddset()、 sigdelset()
+ * 分别对这个信号集进行清空、增加和删除被屏蔽信号的操作；
+ *   sa_flags 成员用于指定信号处理的行为，它可以是以下值的"按位或" 组合：
+ *       SA_RESTART：使被信号打断的系统调用自动重新发起；
+ *       SA_NOCLDSTOP：使父进程在它的子进程暂停或继续运行时不会收到SIGCHLD 信号；
+ *       SA_NOCLDWAIT：使父进程在它的子进程退出时不会收到 SIGCHLD 信号，这时子进程如果退出也不会成为僵尸进程；
+ *       SA_NODEFER：使对信号的屏蔽无效，即在信号处理函数的执行期间仍能发出这个信号；
+ *       SA_RESETHAND：信号被处理后重新设置处理方式到默认值；
+ *       SA_SIGINFO：使用 sa_sigaction 成员而不是 sa_handler 作为信号处理函数。
+ *   re_restorer 成员则是一个已经废弃的数据域，不要使用。
+ *  
+ * retern:
+ *   成功：以前的信号处理配置
+ *   出错：-1
+ * 
+*/
+
+#include <unistd.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <signal.h>
+#include <sys/types.h>
+#include <sys/wait.h>
+
+
+
+
+// int main(void)
+// {
+//     struct sigaction act;
+
+//     /** 设置信号处理的回调函数 */
+//     act.sa_handler = signal_handler;
+    
+//     /* 清空屏蔽信号集 */
+//     sigemptyset(&act.sa_mask); 
+
+//     /** 在处理完信号后恢复默认信号处理 */
+//     act.sa_flags = SA_RESETHAND;
+
+//     sigaction(SIGINT, &act, NULL);
+
+//     while (1)
+//     {
+//         printf("waiting for the SIGINT signal to occur\n");
+//         sleep(1);
+//     }
+    
+//     exit(0);
+// }
+#include <unistd.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <signal.h>
+#include <sys/types.h>
+#include <sys/wait.h>
+
+/** 信号处理函数 */
+void signal_handler(int sig)
+{
+    printf("\nthis signal numble is %d \n",sig);
+
+    if (sig == SIGINT) {
+        printf("I have get SIGINT!\n\n");
+        printf("The signal has been restored to the default processing mode!\n\n");
+        /** 恢复信号为默认情况 */
+        signal(SIGINT, SIG_DFL);
+    }
+
+}
+
+int main(void)
+{
+    printf("\nthis is an alarm test function\n\n");
+
+    /** 设置信号处理的回调函数 */
+    signal(SIGINT, signal_handler);
+
+    while (1) {
+        printf("waiting for the SIGINT signal , please enter \"ctrl + c\"...\n");
+        sleep(1);
+    }
+
+    exit(0);
+}
+ 
diff --git a/base_code/system_programing/stream_pipe/Makefile b/base_code/system_programing/stream_pipe/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..2c1492aae096c2dc6be07662aee4fb221e3bb585
--- /dev/null
+++ b/base_code/system_programing/stream_pipe/Makefile
@@ -0,0 +1,78 @@
+
+#生成可执行文件的名称
+Target = stream_pipe_demo
+ARCH ?= x86
+#编译器CC
+#根据传入的参数ARCH，确定使用的编译器
+#默认使用gcc编译器
+#make ARCH=arm 时使用ARM-GCC编译器
+ifeq ($(ARCH), x86)
+	CC = gcc
+else
+	CC = arm-linux-gnueabihf-gcc
+endif
+#存放中间文件的路径
+build_dir = build_$(ARCH)
+#存放源文件的文件夹
+src_dir =  sources
+#存放头文件的文件夹
+inc_dir = includes .
+
+#源文件
+sources = $(foreach dir,$(src_dir),$(wildcard $(dir)/*.c))
+#目标文件（*.o）
+objects = $(patsubst %.c,$(build_dir)/%.o,$(notdir $(sources)))
+#头文件
+includes = $(foreach dir,$(inc_dir),$(wildcard $(dir)/*.h))
+
+#目标依赖文件
+DEP_FILES := $(patsubst %, .%.d,$(objects))
+DEP_FILES := $(wildcard $(DEP_FILES))
+
+#判断依赖文件是否存在
+ifneq ($(DEP_FILES),)
+#如果存在依赖文件，需要导入依赖文件
+include $(DEP_FILES)
+endif
+
+#编译参数
+#指定头文件的路径
+CFLAGS = $(patsubst %, -I%, $(inc_dir)) -MD -MF $(@D)/.$(@F).d
+
+#链接过程
+$(build_dir)/$(Target) : $(objects)  | create_build
+	$(CC) $^ -o $@
+
+#编译工程
+#编译src文件夹中的源文件，并将生成的目标文件放在objs文件夹中
+$(build_dir)/%.o : $(src_dir)/%.c $(includes) | create_build
+	$(CC) -c $(CFLAGS) $< -o $@
+
+
+#以下为伪目标，调用方式：make 伪目标
+#clean：用于Clean Project
+#check：用于检查某个变量的值
+.PHONY:clean cleanall check create_build
+#按架构删除
+clean:
+	rm -rf $(build_dir)
+
+#全部删除
+cleanall:
+	rm -rf build_x86 build_arm
+
+#命令前带"@",表示不在终端上输出执行的命令
+#这个目标主要是用来调试Makefile时输出一些内容
+check:
+	@echo $(CFLAGS)
+	@echo $(CURDIR)
+	@echo $(src_dir)
+	@echo $(sources)
+	@echo $(objects)
+
+
+#创建一个新目录create，用于存放过程文件
+create_build:
+	@mkdir -p $(build_dir)
+
+
diff --git a/base_code/system_programing/stream_pipe/sources/stream_pipe.c b/base_code/system_programing/stream_pipe/sources/stream_pipe.c
new file mode 100644
index 0000000000000000000000000000000000000000..d78ae6fb90527eeb5a3055f7d2e586587f0f1735
--- /dev/null
+++ b/base_code/system_programing/stream_pipe/sources/stream_pipe.c
@@ -0,0 +1,69 @@
+/** stream_pipe.c */
+
+/**
+ * 与 Linux 的文件操作中有基于文件流的标准 I/O 操作一样，管道的操作也支持基于文件流的模式。这种基
+ * 于文件流的管道主要是用来创建一个连接到另一个进程的管道，这里的"另一个进程"也就是一个可以进
+ * 行一定操作的可执行文件，例如，用户执行"ls -l"或者自己编写的程序"./pipe"等。由于这一类操作很
+ * 常用，因此标准流管道就将一系列的创建过程合并到一个函数 popen()中完成。它所完成的工作有以下几步:
+ *   创建一个管道。
+ *   fork()一个子进程。
+ *   在父子进程中关闭不需要的文件描述符。
+ *   执行 exec 函数族调用。
+ *   执行函数中所指定的命令。
+ * 
+ * 这个函数的使用可以大大减少代码的编写量，但同时也有一些不利之处，例如，它不如前面管道创建的函
+ * 数那样灵活多样，并且用 popen()创建的管道必须使用标准 I/O 函数进行操作，但不能使用前面的 read()、
+ * write()一类不带缓冲的 I/O 函数。
+ * 与之相对应，关闭用 popen()创建的流管道必须使用函数 pclose()来关闭该管道流。该函数关闭标准 I/O 流，
+ * 并等待命令执行结束
+ */
+
+/**
+ * 函数原型：FILE *popen(const char *command, const char *type)
+ * 
+ * 函数传入值：
+ *  command：指向的是一个以 null 结束符结尾的字符串，这个字符串包含一个 shell 命令，并被送到/bin/sh 以-c 参数执行，即由 shell 来执行
+ *  type：
+ *      "r"：文件指针连接到 command 的标准输出，即该命令的结果产生输出
+ *      "w"：文件指针连接到 command 的标准输入，即该命令的结果产生输入
+ * 
+ * 函数返回值：
+ *  成功：文件流指针
+ *  出错： -1
+ */
+
+/**
+ * 函数原型 int pclose(FILE *stream)
+ * 函数传入值 stream：要关闭的文件流
+ * 函数返回值
+ *  成功：返回由 popen()所执行的进程的退出码
+ *  出错： -1
+ */
+
+#include <stdio.h>
+#include <unistd.h>
+#include <stdlib.h>
+#include <fcntl.h>
+#define BUFSIZE 1024
+int main()
+{
+    FILE *fp;
+    char *cmd = "ps -ef";
+    char buf[BUFSIZE];
+    
+    /*调用 popen()函数执行相应的命令*/
+    if ((fp = popen(cmd, "r")) == NULL)
+    {
+        printf("Popen error\n");
+        exit(1);
+    }
+
+    while ((fgets(buf, BUFSIZE, fp)) != NULL)
+    {
+        printf("%s",buf);       //打印命令输出的信息
+    }
+
+    pclose(fp);
+    
+    exit(0);
+}
\ No newline at end of file
diff --git a/base_code/system_programing/system/Makefile b/base_code/system_programing/system/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..650ff5a5d9f8815fc27b343d6d7e8aa392d39925
--- /dev/null
+++ b/base_code/system_programing/system/Makefile
@@ -0,0 +1,78 @@
+
+#生成可执行文件的名称
+Target = system_demo
+ARCH ?= x86
+#编译器CC
+#根据传入的参数ARCH，确定使用的编译器
+#默认使用gcc编译器
+#make ARCH=arm 时使用ARM-GCC编译器
+ifeq ($(ARCH), x86)
+	CC = gcc
+else
+	CC = arm-linux-gnueabihf-gcc
+endif
+#存放中间文件的路径
+build_dir = build_$(ARCH)
+#存放源文件的文件夹
+src_dir =  sources
+#存放头文件的文件夹
+inc_dir = includes .
+
+#源文件
+sources = $(foreach dir,$(src_dir),$(wildcard $(dir)/*.c))
+#目标文件（*.o）
+objects = $(patsubst %.c,$(build_dir)/%.o,$(notdir $(sources)))
+#头文件
+includes = $(foreach dir,$(inc_dir),$(wildcard $(dir)/*.h))
+
+#目标依赖文件
+DEP_FILES := $(patsubst %, .%.d,$(objects))
+DEP_FILES := $(wildcard $(DEP_FILES))
+
+#判断依赖文件是否存在
+ifneq ($(DEP_FILES),)
+#如果存在依赖文件，需要导入依赖文件
+include $(DEP_FILES)
+endif
+
+#编译参数
+#指定头文件的路径
+CFLAGS = $(patsubst %, -I%, $(inc_dir)) -MD -MF $(@D)/.$(@F).d
+
+#链接过程
+$(build_dir)/$(Target) : $(objects)  | create_build
+	$(CC) $^ -o $@
+
+#编译工程
+#编译src文件夹中的源文件，并将生成的目标文件放在objs文件夹中
+$(build_dir)/%.o : $(src_dir)/%.c $(includes) | create_build
+	$(CC) -c $(CFLAGS) $< -o $@
+
+
+#以下为伪目标，调用方式：make 伪目标
+#clean：用于Clean Project
+#check：用于检查某个变量的值
+.PHONY:clean cleanall check create_build
+#按架构删除
+clean:
+	rm -rf $(build_dir)
+
+#全部删除
+cleanall:
+	rm -rf build_x86 build_arm
+
+#命令前带"@",表示不在终端上输出执行的命令
+#这个目标主要是用来调试Makefile时输出一些内容
+check:
+	@echo $(CFLAGS)
+	@echo $(CURDIR)
+	@echo $(src_dir)
+	@echo $(sources)
+	@echo $(objects)
+
+
+#创建一个新目录create，用于存放过程文件
+create_build:
+	@mkdir -p $(build_dir)
+
+
diff --git a/base_code/system_programing/system/sources/system.c b/base_code/system_programing/system/sources/system.c
new file mode 100644
index 0000000000000000000000000000000000000000..7175af924ad1b5eb16c7b48532e745359b5e46a3
--- /dev/null
+++ b/base_code/system_programing/system/sources/system.c
@@ -0,0 +1,30 @@
+/* system.c */
+
+/** 
+ * 这个 system()函数是C 标准库中提供的，它主要是提供了一种调用其它程序的简单方法。读者可以利用 system()函数调用一些应用程序，
+ * 它产生的结果与从 shell 中执行这个程序基本相似。事实上， system()启动了一个运行着/bin/sh的子进程，然后将命令交由它执行。
+ */
+
+#include <sys/types.h>
+#include <unistd.h>
+#include <stdio.h>
+#include <stdlib.h>
+
+int main(void)
+{
+    pid_t result;
+
+    printf("This is a system demo!\n\n");
+
+    /*调用 system()函数*/
+    result = system("ls -l");
+
+    printf("Done!\n\n");
+
+    return result;
+}
+
+
+
+
+
diff --git a/base_code/system_programing/systemV_sem/Makefile b/base_code/system_programing/systemV_sem/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..65d6e70b6784d7b2c36ef6a51917076090f86091
--- /dev/null
+++ b/base_code/system_programing/systemV_sem/Makefile
@@ -0,0 +1,78 @@
+
+#生成可执行文件的名称
+Target = systemV_sem_demo
+ARCH ?= x86
+#编译器CC
+#根据传入的参数ARCH，确定使用的编译器
+#默认使用gcc编译器
+#make ARCH=arm 时使用ARM-GCC编译器
+ifeq ($(ARCH), x86)
+	CC = gcc
+else
+	CC = arm-linux-gnueabihf-gcc
+endif
+#存放中间文件的路径
+build_dir = build_$(ARCH)
+#存放源文件的文件夹
+src_dir =  sources
+#存放头文件的文件夹
+inc_dir = includes .
+
+#源文件
+sources = $(foreach dir,$(src_dir),$(wildcard $(dir)/*.c))
+#目标文件（*.o）
+objects = $(patsubst %.c,$(build_dir)/%.o,$(notdir $(sources)))
+#头文件
+includes = $(foreach dir,$(inc_dir),$(wildcard $(dir)/*.h))
+
+#目标依赖文件
+DEP_FILES := $(patsubst %, .%.d,$(objects))
+DEP_FILES := $(wildcard $(DEP_FILES))
+
+#判断依赖文件是否存在
+ifneq ($(DEP_FILES),)
+#如果存在依赖文件，需要导入依赖文件
+include $(DEP_FILES)
+endif
+
+#编译参数
+#指定头文件的路径
+CFLAGS = $(patsubst %, -I%, $(inc_dir)) -MD -MF $(@D)/.$(@F).d
+
+#链接过程
+$(build_dir)/$(Target) : $(objects)  | create_build
+	$(CC) $^ -o $@
+
+#编译工程
+#编译src文件夹中的源文件，并将生成的目标文件放在objs文件夹中
+$(build_dir)/%.o : $(src_dir)/%.c $(includes) | create_build
+	$(CC) -c $(CFLAGS) $< -o $@
+
+
+#以下为伪目标，调用方式：make 伪目标
+#clean：用于Clean Project
+#check：用于检查某个变量的值
+.PHONY:clean cleanall check create_build
+#按架构删除
+clean:
+	rm -rf $(build_dir)
+
+#全部删除
+cleanall:
+	rm -rf build_x86 build_arm
+
+#命令前带"@",表示不在终端上输出执行的命令
+#这个目标主要是用来调试Makefile时输出一些内容
+check:
+	@echo $(CFLAGS)
+	@echo $(CURDIR)
+	@echo $(src_dir)
+	@echo $(sources)
+	@echo $(objects)
+
+
+#创建一个新目录create，用于存放过程文件
+create_build:
+	@mkdir -p $(build_dir)
+
+
diff --git a/base_code/system_programing/systemV_sem/includes/sem.h b/base_code/system_programing/systemV_sem/includes/sem.h
new file mode 100644
index 0000000000000000000000000000000000000000..ec6c784b9645d437f08043c666ee48e80fdf8b66
--- /dev/null
+++ b/base_code/system_programing/systemV_sem/includes/sem.h
@@ -0,0 +1,18 @@
+#ifndef _SEM_H_
+#define _SEM_H_
+
+
+union semun
+{
+    int val;
+    struct semid_ds *buf;
+    unsigned short *array;
+};
+
+extern int init_sem(int sem_id, int init_value);
+extern int del_sem(int sem_id);
+extern int sem_p(int sem_id);
+extern int sem_v(int sem_id);
+
+#endif
+
diff --git a/base_code/system_programing/systemV_sem/sources/sem.c b/base_code/system_programing/systemV_sem/sources/sem.c
new file mode 100644
index 0000000000000000000000000000000000000000..7f388d7923f2a243342b0da62ca0660d9f42059d
--- /dev/null
+++ b/base_code/system_programing/systemV_sem/sources/sem.c
@@ -0,0 +1,79 @@
+/*
+ * @Author: jiejie
+ * @Github: https://github.com/jiejieTop
+ * @Date: 2020-02-10 16:51:42
+ * @LastEditTime: 2020-02-10 17:34:41
+ * @Description: the code belongs to jiejie, please keep the author information and source code according to the license.
+ */
+
+#include <sys/sem.h>
+#include <sys/ipc.h>
+#include <unistd.h>
+#include <stdlib.h>
+#include <stdio.h>
+#include <string.h>
+#include <sys/shm.h>
+#include <sys/stat.h>
+#include <fcntl.h>
+#include <errno.h>
+
+#include "sem.h"
+
+
+/* 信号量初始化（赋值）函数*/
+int init_sem(int sem_id, int init_value)
+{
+    union semun sem_union;
+    sem_union.val = init_value; /* init_value 为初始值 */
+
+    if (semctl(sem_id, 0, SETVAL, sem_union) == -1)
+    {
+        perror("Initialize semaphore");
+        return -1;
+    }
+
+    return 0;
+}
+
+/* 从系统中删除信号量的函数 */
+int del_sem(int sem_id)
+{
+    union semun sem_union;
+    if (semctl(sem_id, 0, IPC_RMID, sem_union) == -1)
+    {
+        perror("Delete semaphore");
+        return -1;
+    }
+}
+
+/* P 操作函数 */
+int sem_p(int sem_id)
+{
+    struct sembuf sops;
+    sops.sem_num = 0; /* 单个信号量的编号应该为 0 */
+    sops.sem_op = -1; /* 表示 P 操作 */
+    sops.sem_flg = SEM_UNDO; /* 系统自动释放将会在系统中残留的信号量*/
+
+    if (semop(sem_id, &sops, 1) == -1)
+    {
+        perror("P operation");
+        return -1;
+    }
+    return 0;
+}
+
+/* V 操作函数*/
+int sem_v(int sem_id)
+{
+    struct sembuf sops;
+    sops.sem_num = 0; /* 单个信号量的编号应该为 0 */
+    sops.sem_op = 1; /* 表示 V 操作 */
+    sops.sem_flg = SEM_UNDO; /* 系统自动释放将会在系统中残留的信号量*/
+
+    if (semop(sem_id, &sops, 1) == -1)
+    {
+        perror("V operation");
+        return -1;
+    }
+    return 0;
+}
diff --git a/base_code/system_programing/systemV_sem/sources/test.c b/base_code/system_programing/systemV_sem/sources/test.c
new file mode 100644
index 0000000000000000000000000000000000000000..8943418e8ac7d420d49af3216b1ccdc030f07e2c
--- /dev/null
+++ b/base_code/system_programing/systemV_sem/sources/test.c
@@ -0,0 +1,53 @@
+
+#include <sys/types.h>
+#include <sys/shm.h>
+#include <sys/sem.h>
+#include <sys/ipc.h>
+#include <unistd.h>
+#include <stdlib.h>
+#include <stdio.h>
+#include <string.h>
+#include <sys/stat.h>
+#include <fcntl.h>
+#include <errno.h>
+
+#include "sem.h"
+
+#define DELAY_TIME 3 /* 为了突出演示效果，等待几秒钟， */
+
+int main(void)
+{
+    pid_t result;
+    int sem_id;
+
+    sem_id = semget((key_t)6666, 1, 0666 | IPC_CREAT); /* 创建一个信号量*/
+
+    init_sem(sem_id, 0);
+
+    /*调用 fork()函数*/
+    result = fork();
+    if(result == -1)
+    {
+        perror("Fork\n");
+    }
+    else if (result == 0) /*返回值为 0 代表子进程*/
+    {
+        printf("Child process will wait for some seconds...\n");
+        sleep(DELAY_TIME);
+        printf("The returned value is %d in the child process(PID = %d)\n",result, getpid());
+
+        sem_v(sem_id);
+    }
+
+    else /*返回值大于 0 代表父进程*/
+    {
+        sem_p(sem_id);
+        printf("The returned value is %d in the father process(PID = %d)\n",result, getpid());
+
+        sem_v(sem_id);
+
+        del_sem(sem_id);
+    }
+
+    exit(0);
+}
diff --git a/base_code/system_programing/tcp_client/Makefile b/base_code/system_programing/tcp_client/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..4928f9f4f2e52b141840561d7b36aff816869cff
--- /dev/null
+++ b/base_code/system_programing/tcp_client/Makefile
@@ -0,0 +1,78 @@
+
+#生成可执行文件的名称
+Target = tcp_client_demo
+ARCH ?= x86
+#编译器CC
+#根据传入的参数ARCH，确定使用的编译器
+#默认使用gcc编译器
+#make ARCH=arm 时使用ARM-GCC编译器
+ifeq ($(ARCH), x86)
+	CC = gcc
+else
+	CC = arm-linux-gnueabihf-gcc
+endif
+#存放中间文件的路径
+build_dir = build_$(ARCH)
+#存放源文件的文件夹
+src_dir =  sources
+#存放头文件的文件夹
+inc_dir = includes .
+
+#源文件
+sources = $(foreach dir,$(src_dir),$(wildcard $(dir)/*.c))
+#目标文件（*.o）
+objects = $(patsubst %.c,$(build_dir)/%.o,$(notdir $(sources)))
+#头文件
+includes = $(foreach dir,$(inc_dir),$(wildcard $(dir)/*.h))
+
+#目标依赖文件
+DEP_FILES := $(patsubst %, .%.d,$(objects))
+DEP_FILES := $(wildcard $(DEP_FILES))
+
+#判断依赖文件是否存在
+ifneq ($(DEP_FILES),)
+#如果存在依赖文件，需要导入依赖文件
+include $(DEP_FILES)
+endif
+
+#编译参数
+#指定头文件的路径
+CFLAGS = $(patsubst %, -I%, $(inc_dir)) -MD -MF $(@D)/.$(@F).d
+
+#链接过程
+$(build_dir)/$(Target) : $(objects)  | create_build
+	$(CC) $^ -o $@
+
+#编译工程
+#编译src文件夹中的源文件，并将生成的目标文件放在objs文件夹中
+$(build_dir)/%.o : $(src_dir)/%.c $(includes) | create_build
+	$(CC) -c $(CFLAGS) $< -o $@
+
+
+#以下为伪目标，调用方式：make 伪目标
+#clean：用于Clean Project
+#check：用于检查某个变量的值
+.PHONY:clean cleanall check create_build
+#按架构删除
+clean:
+	rm -rf $(build_dir)
+
+#全部删除
+cleanall:
+	rm -rf build_x86 build_arm
+
+#命令前带"@",表示不在终端上输出执行的命令
+#这个目标主要是用来调试Makefile时输出一些内容
+check:
+	@echo $(CFLAGS)
+	@echo $(CURDIR)
+	@echo $(src_dir)
+	@echo $(sources)
+	@echo $(objects)
+
+
+#创建一个新目录create，用于存放过程文件
+create_build:
+	@mkdir -p $(build_dir)
+
+
diff --git a/base_code/system_programing/tcp_client/sources/tcp_client.c b/base_code/system_programing/tcp_client/sources/tcp_client.c
new file mode 100644
index 0000000000000000000000000000000000000000..0767ad61e75a952e43146abeafc0bde608e7d5cb
--- /dev/null
+++ b/base_code/system_programing/tcp_client/sources/tcp_client.c
@@ -0,0 +1,60 @@
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <unistd.h>
+#include <errno.h>
+#include <sys/types.h>
+#include <sys/socket.h>
+#include <netinet/in.h>
+#include <arpa/inet.h>
+#include <netdb.h>
+
+#define HOST "192.168.0.217"        // 根据你服务器的IP地址修改
+#define PORT 6666                   // 根据你服务器进程绑定的端口号修改
+#define BUFFER_SIZ (4 * 1024)           // 4k的数据区域
+
+
+int main(void)
+{
+    int sockfd, ret;
+    struct sockaddr_in server;
+    char buffer[BUFFER_SIZ];        //用于保存输入的文本
+    
+	memset(buffer, 0, BUFFER_SIZ);
+
+    // 创建套接字描述符
+    if ((sockfd = socket(AF_INET, SOCK_STREAM, 0)) == -1) {
+        printf("create an endpoint for communication fail!\n");
+        exit(1);
+    } 
+
+    bzero(&server, sizeof(server));
+	server.sin_family = AF_INET;
+	server.sin_port = htons(PORT);
+	server.sin_addr.s_addr = inet_addr(HOST);
+
+    // 建立TCP连接
+    if (connect(sockfd, (struct sockaddr *)&server, sizeof(struct sockaddr)) == -1) {
+        printf("connect server fail...\n");
+        close(sockfd);
+        exit(1);
+    } 
+
+    printf("connect server success...\n");
+
+    while (1) {
+
+		printf("please enter some text: ");
+		fgets(buffer, BUFFER_SIZ, stdin);
+
+        //输入了exit，退出循环（程序）
+		if(strncmp(buffer, "exit", 4) == 0)
+			break;
+
+        write(sockfd, buffer, strlen(buffer));
+    }
+
+    close(sockfd);
+    exit(0);
+}
+
diff --git a/base_code/system_programing/tcp_server/Makefile b/base_code/system_programing/tcp_server/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..568710988a684db84be16465a17431d2e7033c78
--- /dev/null
+++ b/base_code/system_programing/tcp_server/Makefile
@@ -0,0 +1,78 @@
+
+#生成可执行文件的名称
+Target = tcp_server_demo
+ARCH ?= x86
+#编译器CC
+#根据传入的参数ARCH，确定使用的编译器
+#默认使用gcc编译器
+#make ARCH=arm 时使用ARM-GCC编译器
+ifeq ($(ARCH), x86)
+	CC = gcc
+else
+	CC = arm-linux-gnueabihf-gcc
+endif
+#存放中间文件的路径
+build_dir = build_$(ARCH)
+#存放源文件的文件夹
+src_dir =  sources
+#存放头文件的文件夹
+inc_dir = includes .
+
+#源文件
+sources = $(foreach dir,$(src_dir),$(wildcard $(dir)/*.c))
+#目标文件（*.o）
+objects = $(patsubst %.c,$(build_dir)/%.o,$(notdir $(sources)))
+#头文件
+includes = $(foreach dir,$(inc_dir),$(wildcard $(dir)/*.h))
+
+#目标依赖文件
+DEP_FILES := $(patsubst %, .%.d,$(objects))
+DEP_FILES := $(wildcard $(DEP_FILES))
+
+#判断依赖文件是否存在
+ifneq ($(DEP_FILES),)
+#如果存在依赖文件，需要导入依赖文件
+include $(DEP_FILES)
+endif
+
+#编译参数
+#指定头文件的路径
+CFLAGS = $(patsubst %, -I%, $(inc_dir)) -MD -MF $(@D)/.$(@F).d
+
+#链接过程
+$(build_dir)/$(Target) : $(objects)  | create_build
+	$(CC) $^ -o $@
+
+#编译工程
+#编译src文件夹中的源文件，并将生成的目标文件放在objs文件夹中
+$(build_dir)/%.o : $(src_dir)/%.c $(includes) | create_build
+	$(CC) -c $(CFLAGS) $< -o $@
+
+
+#以下为伪目标，调用方式：make 伪目标
+#clean：用于Clean Project
+#check：用于检查某个变量的值
+.PHONY:clean cleanall check create_build
+#按架构删除
+clean:
+	rm -rf $(build_dir)
+
+#全部删除
+cleanall:
+	rm -rf build_x86 build_arm
+
+#命令前带"@",表示不在终端上输出执行的命令
+#这个目标主要是用来调试Makefile时输出一些内容
+check:
+	@echo $(CFLAGS)
+	@echo $(CURDIR)
+	@echo $(src_dir)
+	@echo $(sources)
+	@echo $(objects)
+
+
+#创建一个新目录create，用于存放过程文件
+create_build:
+	@mkdir -p $(build_dir)
+
+
diff --git a/base_code/system_programing/tcp_server/sources/tcp_server.c b/base_code/system_programing/tcp_server/sources/tcp_server.c
new file mode 100644
index 0000000000000000000000000000000000000000..d5b1ab080dd2cde2645849ff6fb48932e3ae1718
--- /dev/null
+++ b/base_code/system_programing/tcp_server/sources/tcp_server.c
@@ -0,0 +1,89 @@
+#include <stdio.h>
+#include <netdb.h>
+#include <unistd.h>
+#include <netinet/in.h>
+#include <stdlib.h>
+#include <string.h>
+#include <sys/socket.h>
+#include <sys/types.h>
+
+#define MAX 10*1024
+#define PORT 6666
+
+// Driver function
+int main()
+{
+    char buff[MAX];
+    int n;
+    int sockfd, connfd, len;
+    struct sockaddr_in server, client;
+
+    // socket create and verification
+    sockfd = socket(AF_INET, SOCK_STREAM, 0);
+    if (sockfd == -1) {
+        printf("socket creation failed...\n");
+        exit(0);
+    }
+
+    printf("socket successfully created..\n");
+    bzero(&server, sizeof(server));
+
+    // assign IP, PORT
+    server.sin_family = AF_INET;
+    server.sin_addr.s_addr = htonl(INADDR_ANY);
+    server.sin_port = htons(PORT);
+
+    // binding newly created socket to given IP and verification
+    if ((bind(sockfd, (struct sockaddr*)&server, sizeof(server))) != 0) {
+        printf("socket bind failed...\n");
+        exit(0);
+    }
+    
+    printf("socket successfully binded..\n");
+
+    // now server is ready to listen and verification
+    if ((listen(sockfd, 5)) != 0) {
+        printf("Listen failed...\n");
+        exit(0);
+    }
+
+    printf("server listening...\n");
+    
+    len = sizeof(client);
+
+    // accept the data packet from client and verification
+    connfd = accept(sockfd, (struct sockaddr*)&client, &len);
+    if (connfd < 0) {
+        printf("server acccept failed...\n");
+        exit(0);
+    }
+
+    printf("server acccept the client...\n");
+
+    // infinite loop for chat
+    while(1) {
+        bzero(buff, MAX);
+
+        // read the messtruct sockaddrge from client and copy it in buffer
+        if (read(connfd, buff, sizeof(buff)) <= 0) {
+            printf("client close...\n");
+            close(connfd);
+            break;
+        }
+
+        // print buffer which contains the client contents
+        printf("from client: %s\n", buff);
+
+        // if msg contains "Exit" then server exit and chat ended.
+        if (strncmp("exit", buff, 4) == 0) {
+            printf("server exit...\n");
+            close(connfd);
+            break;
+        }
+    }
+
+    // After chatting close the socket
+    close(sockfd);
+    exit(0);
+}
+
diff --git a/base_code/system_programing/thread/Makefile b/base_code/system_programing/thread/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..4eae31cd612ba2425630de4718455dc2b4766d52
--- /dev/null
+++ b/base_code/system_programing/thread/Makefile
@@ -0,0 +1,79 @@
+
+#生成可执行文件的名称
+Target = thread_demo
+ARCH ?= x86
+#编译器CC
+#根据传入的参数ARCH，确定使用的编译器
+#默认使用gcc编译器
+#make ARCH=arm 时使用ARM-GCC编译器
+ifeq ($(ARCH), x86)
+	CC = gcc
+else
+	CC = arm-linux-gnueabihf-gcc
+endif
+#存放中间文件的路径
+build_dir = build_$(ARCH)
+#存放源文件的文件夹
+src_dir =  sources
+#存放头文件的文件夹
+inc_dir = includes .
+
+#源文件
+sources = $(foreach dir,$(src_dir),$(wildcard $(dir)/*.c))
+#目标文件（*.o）
+objects = $(patsubst %.c,$(build_dir)/%.o,$(notdir $(sources)))
+#头文件
+includes = $(foreach dir,$(inc_dir),$(wildcard $(dir)/*.h))
+
+#目标依赖文件
+DEP_FILES := $(patsubst %, .%.d,$(objects))
+DEP_FILES := $(wildcard $(DEP_FILES))
+
+#判断依赖文件是否存在
+ifneq ($(DEP_FILES),)
+#如果存在依赖文件，需要导入依赖文件
+include $(DEP_FILES)
+endif
+
+#编译参数
+#指定头文件的路径
+CFLAGS = $(patsubst %, -I%, $(inc_dir)) -MD -MF $(@D)/.$(@F).d
+LINK = -lpthread
+
+#链接过程
+$(build_dir)/$(Target) : $(objects)  | create_build
+	$(CC) $^ ${LINK} -o $@
+
+#编译工程
+#编译src文件夹中的源文件，并将生成的目标文件放在objs文件夹中
+$(build_dir)/%.o : $(src_dir)/%.c $(includes) | create_build
+	$(CC) -c $(CFLAGS) $< -o $@
+
+
+#以下为伪目标，调用方式：make 伪目标
+#clean：用于Clean Project
+#check：用于检查某个变量的值
+.PHONY:clean cleanall check create_build
+#按架构删除
+clean:
+	rm -rf $(build_dir)
+
+#全部删除
+cleanall:
+	rm -rf build_x86 build_arm
+
+#命令前带"@",表示不在终端上输出执行的命令
+#这个目标主要是用来调试Makefile时输出一些内容
+check:
+	@echo $(CFLAGS)
+	@echo $(CURDIR)
+	@echo $(src_dir)
+	@echo $(sources)
+	@echo $(objects)
+
+
+#创建一个新目录create，用于存放过程文件
+create_build:
+	@mkdir -p $(build_dir)
+
+
diff --git a/base_code/system_programing/thread/sources/thread.c b/base_code/system_programing/thread/sources/thread.c
new file mode 100644
index 0000000000000000000000000000000000000000..3abb3df4729452900ed11c0ddfd7c7aa43262b59
--- /dev/null
+++ b/base_code/system_programing/thread/sources/thread.c
@@ -0,0 +1,102 @@
+/**
+ * 线程按照其调度者可以分为用户级线程和核心级线程两种。
+ * （1）用户级线程。
+ * 用户级线程主要解决的是上下文切换的问题，它的调度算法和调度过程全部由用户自行选择决定，在运行
+ * 时不需要特定的内核支持。在这里，操作系统往往会提供一个用户空间的线程库，该线程库提供了线程的
+ * 创建、调度和撤销等功能，而内核仍然仅对进程进行管理。如果一个进程中的某一个线程调用了一个阻塞
+ * 的系统调用函数，那么该进程包括该进程中的其他所有线程也同时被阻塞。这种用户级线程的主要缺点是
+ * 在一个进程中的多个线程的调度中无法发挥多处理器的优势。
+ * （2）轻量级进程。
+ * 轻量级进程是内核支持的用户线程，是内核线程的一种抽象对象。每个线程拥有一个或多个轻量级线程，
+ * 而每个轻量级线程分别被绑定在一个内核线程上。
+ * （3）内核线程。
+ * 这种线程允许不同进程中的线程按照同一相对优先调度方法进行调度，这样就可以发挥多处理器的并发优势。
+ * 现在大多数系统都采用用户级线程与核心级线程并存的方法。一个用户级线程可以对应一个或几个核心级
+ * 线程，也就是"一对一"或"多对一"模型。这样既可满足多处理机系统的需要，也可以最大限度地减少
+ * 调度开销。
+ * 使用线程机制大大加快上下文切换速度而且节省很多资源。但是因为在用户态和内核态均要实现调度管
+ * 理，所以会增加实现的复杂度和引起优先级翻转的可能性。一个多线程程序的同步设计与调试也会增加程
+ * 序实现的难度。
+ */
+
+/**
+ * 函数原型 int pthread_create ((pthread_t *thread, pthread_attr_t *attr,void *(*start_routine)(void *), void *arg))
+ * 函数传入值
+ *  thread：线程标识符
+ *  attr：线程属性设置，通常取为 NULL
+ *  start_routine：线程函数的起始地址，是一个以指向 void 的指针作为参数和返回值的函数指针
+ *  arg：传递给 start_routine 的参数
+ * 函数返回值
+ *  成功： 0
+ *  出错：返回错误码
+ * 
+ * 函数原型 void pthread_exit(void *retval)
+ * 函数传入值 
+ *  retval：线程结束时的返回值，可由其他函数如 pthread_join()来获取
+ * 
+ * 函数原型 int pthread_join ((pthread_t th, void **thread_return))
+ * 函数传入值
+ *  th：等待线程的标识符
+ *  thread_return：用户定义的指针，用来存储被等待线程结束时的返回值（不为 NULL 时）
+ * 函数返回值
+ *  成功： 0
+ *  出错：返回错误码
+ * 
+ * 函数原型 int pthread_cancel((pthread_t th)
+ * 函数传入值 th：要取消的线程的标识符
+ * 函数返回值
+ *  成功： 0
+ *  出错：返回错误码
+ * 
+ */
+
+
+#include <unistd.h>
+#include <fcntl.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <pthread.h>
+
+void *test_thread(void *arg)
+{
+    int num = (unsigned long long)arg; /** sizeof(void*) == 8 and sizeof(int) == 4 (64 bits) */
+
+    printf("arg is %d\n", num);
+
+    pthread_exit(NULL);
+}
+
+
+int main(void)
+{
+    pthread_t thread;
+    void *thread_return;
+    int arg = 520;
+    int res;
+
+    printf("start create thread\n");
+
+    res = pthread_create(&thread, NULL, test_thread, (void*)(unsigned long long)(arg));
+    if(res != 0)
+    {
+        printf("create thread fail\n");
+        exit(res);
+    }
+
+    printf("create treads success\n");
+    printf("waiting for threads to finish...\n");
+
+
+    res = pthread_join(thread, &thread_return);
+    if(res != 0)
+    {
+        printf("thread exit fail\n");
+        exit(res);
+    }
+
+    printf("thread exit ok\n");
+
+    return 0;
+}
+
+
diff --git a/base_code/system_programing/thread_attr/Makefile b/base_code/system_programing/thread_attr/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..abe2b8bea5bcd029c7af02340422660ccd5a5673
--- /dev/null
+++ b/base_code/system_programing/thread_attr/Makefile
@@ -0,0 +1,79 @@
+
+#生成可执行文件的名称
+Target = thread_attr_demo
+ARCH ?= x86
+#编译器CC
+#根据传入的参数ARCH，确定使用的编译器
+#默认使用gcc编译器
+#make ARCH=arm 时使用ARM-GCC编译器
+ifeq ($(ARCH), x86)
+	CC = gcc
+else
+	CC = arm-linux-gnueabihf-gcc
+endif
+#存放中间文件的路径
+build_dir = build_$(ARCH)
+#存放源文件的文件夹
+src_dir =  sources
+#存放头文件的文件夹
+inc_dir = includes .
+
+#源文件
+sources = $(foreach dir,$(src_dir),$(wildcard $(dir)/*.c))
+#目标文件（*.o）
+objects = $(patsubst %.c,$(build_dir)/%.o,$(notdir $(sources)))
+#头文件
+includes = $(foreach dir,$(inc_dir),$(wildcard $(dir)/*.h))
+
+#目标依赖文件
+DEP_FILES := $(patsubst %, .%.d,$(objects))
+DEP_FILES := $(wildcard $(DEP_FILES))
+
+#判断依赖文件是否存在
+ifneq ($(DEP_FILES),)
+#如果存在依赖文件，需要导入依赖文件
+include $(DEP_FILES)
+endif
+
+#编译参数
+#指定头文件的路径
+CFLAGS = $(patsubst %, -I%, $(inc_dir)) -MD -MF $(@D)/.$(@F).d
+LINK = -lpthread
+
+#链接过程
+$(build_dir)/$(Target) : $(objects)  | create_build
+	$(CC) $^ ${LINK} -o $@
+
+#编译工程
+#编译src文件夹中的源文件，并将生成的目标文件放在objs文件夹中
+$(build_dir)/%.o : $(src_dir)/%.c $(includes) | create_build
+	$(CC) -c $(CFLAGS) $< -o $@
+
+
+#以下为伪目标，调用方式：make 伪目标
+#clean：用于Clean Project
+#check：用于检查某个变量的值
+.PHONY:clean cleanall check create_build
+#按架构删除
+clean:
+	rm -rf $(build_dir)
+
+#全部删除
+cleanall:
+	rm -rf build_x86 build_arm
+
+#命令前带"@",表示不在终端上输出执行的命令
+#这个目标主要是用来调试Makefile时输出一些内容
+check:
+	@echo $(CFLAGS)
+	@echo $(CURDIR)
+	@echo $(src_dir)
+	@echo $(sources)
+	@echo $(objects)
+
+
+#创建一个新目录create，用于存放过程文件
+create_build:
+	@mkdir -p $(build_dir)
+
+
diff --git a/base_code/system_programing/thread_attr/sources/thread_attr.c b/base_code/system_programing/thread_attr/sources/thread_attr.c
new file mode 100644
index 0000000000000000000000000000000000000000..fc352f011212ddd6900a8efbe600464a1070cd81
--- /dev/null
+++ b/base_code/system_programing/thread_attr/sources/thread_attr.c
@@ -0,0 +1,123 @@
+/** thread_attr.c */
+
+/**
+ * 函数原型 int pthread_attr_init(pthread_attr_t *attr)
+ * 函数传入值 attr：线程属性结构指针
+ * 函数返回值
+ *  成功： 0
+ *  出错：返回错误码
+ * 
+ * 函数原型 int pthread_attr_setscope(pthread_attr_t *attr, int scope)
+ * 函数传入值 attr：线程属性结构指针
+ * cope
+ *  PTHREAD_SCOPE_SYSTEM：绑定
+ *  PTHREAD_SCOPE_PROCESS：非绑定
+ * 函数返回值
+ *  成功： 0
+ *  出错： -1
+ * 
+ * 函数原型 int pthread_attr_setscope(pthread_attr_t *attr, int detachstate)
+ * 函数传入值
+ *  attr：线程属性
+ *  detachstate:
+ *   PTHREAD_CREATE_DETACHED：分离
+ *   PTHREAD _CREATE_JOINABLE：非分离
+ * 函数返回值
+ *  成功： 0
+ *  出错：返回错误码
+ * 
+ * 函数原型 int pthread_attr_getschedparam (pthread_attr_t *attr, struct sched_param *param)
+ * 函数传入值
+ *  attr：线程属性结构指针
+ *  param：线程优先级
+ * 函数返回值
+ *  成功： 0
+ *  出错：返回错误码
+ * 
+ * 
+ * 函数原型 int pthread_attr_setschedparam (pthread_attr_t *attr, struct sched_param *param)
+ * 函数传入值
+ *  attr：线程属性结构指针
+ *  param：线程优先级
+ * 函数返回值
+ *  成功： 0
+ *  出错：返回错误码
+ * 
+ */
+
+#include <unistd.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <pthread.h>
+
+#define REPEAT_NUMBER 3 /* 线程中的小任务数 */
+#define DELAY_TIME_LEVELS 10.0 /* 小任务之间的最大时间间隔 */
+int finish_flag = 0;
+
+void *thrd_func(void *arg)
+{
+    int delay_time = 0;
+    int count = 0;
+    printf("Thread is starting\n");
+    for (count = 0; count < REPEAT_NUMBER; count++)
+    {
+        delay_time = (int)(rand() * DELAY_TIME_LEVELS/(RAND_MAX)) + 1;
+        sleep(delay_time);
+        printf("\tThread : job %d delay = %d\n", count, delay_time);
+    }
+
+    printf("Thread finished\n");
+    finish_flag = 1;
+    pthread_exit(NULL);
+}
+
+
+int main(void)
+{
+    pthread_t thread;
+    pthread_attr_t attr;
+    int no = 0, res;
+    void * thrd_ret;
+
+    srand(time(NULL));
+
+    /* 初始化线程属性对象 */
+    res = pthread_attr_init(&attr);
+    if (res != 0)
+    {
+        printf("Create attribute failed\n");
+        exit(res);
+    }
+
+    /* 设置线程绑定属性 */
+    res = pthread_attr_setscope(&attr, PTHREAD_SCOPE_SYSTEM);
+
+    /* 设置线程分离属性 */
+    res = pthread_attr_setdetachstate(&attr, PTHREAD_CREATE_DETACHED);
+    if (res != 0)
+    {
+        printf("Setting attribute failed\n");
+        exit(res);
+    }
+
+    res = pthread_create(&thread, &attr, thrd_func, NULL);
+    if (res != 0)
+    {
+        printf("Create thread failed\n");
+        exit(res);
+    }
+
+    /* 释放线程属性对象 */
+    pthread_attr_destroy(&attr);
+
+    printf("Create tread success\n");
+    while(!finish_flag)
+    {
+        printf("Waiting for thread to finish...\n");
+        sleep(1);
+    }
+
+    return 0;
+}
+
+
diff --git a/base_code/system_programing/vfork/Makefile b/base_code/system_programing/vfork/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..c3e29930b4c7862a1fe5d8fde76a308df95c459e
--- /dev/null
+++ b/base_code/system_programing/vfork/Makefile
@@ -0,0 +1,78 @@
+
+#生成可执行文件的名称
+Target = vfork_demo
+ARCH ?= x86
+#编译器CC
+#根据传入的参数ARCH，确定使用的编译器
+#默认使用gcc编译器
+#make ARCH=arm 时使用ARM-GCC编译器
+ifeq ($(ARCH), x86)
+	CC = gcc
+else
+	CC = arm-linux-gnueabihf-gcc
+endif
+#存放中间文件的路径
+build_dir = build_$(ARCH)
+#存放源文件的文件夹
+src_dir =  sources
+#存放头文件的文件夹
+inc_dir = includes .
+
+#源文件
+sources = $(foreach dir,$(src_dir),$(wildcard $(dir)/*.c))
+#目标文件（*.o）
+objects = $(patsubst %.c,$(build_dir)/%.o,$(notdir $(sources)))
+#头文件
+includes = $(foreach dir,$(inc_dir),$(wildcard $(dir)/*.h))
+
+#目标依赖文件
+DEP_FILES := $(patsubst %, .%.d,$(objects))
+DEP_FILES := $(wildcard $(DEP_FILES))
+
+#判断依赖文件是否存在
+ifneq ($(DEP_FILES),)
+#如果存在依赖文件，需要导入依赖文件
+include $(DEP_FILES)
+endif
+
+#编译参数
+#指定头文件的路径
+CFLAGS = $(patsubst %, -I%, $(inc_dir)) -MD -MF $(@D)/.$(@F).d
+
+#链接过程
+$(build_dir)/$(Target) : $(objects)  | create_build
+	$(CC) $^ -o $@
+
+#编译工程
+#编译src文件夹中的源文件，并将生成的目标文件放在objs文件夹中
+$(build_dir)/%.o : $(src_dir)/%.c $(includes) | create_build
+	$(CC) -c $(CFLAGS) $< -o $@
+
+
+#以下为伪目标，调用方式：make 伪目标
+#clean：用于Clean Project
+#check：用于检查某个变量的值
+.PHONY:clean cleanall check create_build
+#按架构删除
+clean:
+	rm -rf $(build_dir)
+
+#全部删除
+cleanall:
+	rm -rf build_x86 build_arm
+
+#命令前带"@",表示不在终端上输出执行的命令
+#这个目标主要是用来调试Makefile时输出一些内容
+check:
+	@echo $(CFLAGS)
+	@echo $(CURDIR)
+	@echo $(src_dir)
+	@echo $(sources)
+	@echo $(objects)
+
+
+#创建一个新目录create，用于存放过程文件
+create_build:
+	@mkdir -p $(build_dir)
+
+
diff --git a/base_code/system_programing/vfork/sources/vfork.c b/base_code/system_programing/vfork/sources/vfork.c
new file mode 100644
index 0000000000000000000000000000000000000000..05213a12ad18d896fdad99f921432c746268fece
--- /dev/null
+++ b/base_code/system_programing/vfork/sources/vfork.c
@@ -0,0 +1,35 @@
+/*
+ * @Author: jiejie
+ * @Github: https://github.com/jiejieTop
+ * @Date: 2020-02-10 16:51:42
+ * @LastEditTime: 2020-02-10 17:32:31
+ * @Description: the code belongs to jiejie, please keep the author information and source code according to the license.
+ */
+/* vfork.c */
+
+
+#include <sys/types.h>
+#include <unistd.h>
+#include <stdio.h>
+#include <stdlib.h>
+int main(void)
+{
+    pid_t result;
+    /*调用 fork()函数*/
+    result = vfork();
+    /*通过 result 的值来判断 fork()函数的返回情况，首先进行出错处理*/
+    if(result == -1)
+    {
+        printf("Fork error\n");
+    }
+    else if (result == 0) /*返回值为 0 代表子进程*/
+    {
+        printf("The returned value is %d\nIn child process!!\nMy PID is %d\n\n",result,getpid());
+
+    }
+    else /*返回值大于 0 代表父进程*/
+    {
+        printf("The returned value is %d\nIn father process!!\nMy PID is %d\n\n",result,getpid());
+    }
+    exit(1);
+}
diff --git a/base_code/system_programing/wait/Makefile b/base_code/system_programing/wait/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..9a31b174e7089d1487931c2870c177ecd55eb501
--- /dev/null
+++ b/base_code/system_programing/wait/Makefile
@@ -0,0 +1,78 @@
+
+#生成可执行文件的名称
+Target = wait_demo
+ARCH ?= x86
+#编译器CC
+#根据传入的参数ARCH，确定使用的编译器
+#默认使用gcc编译器
+#make ARCH=arm 时使用ARM-GCC编译器
+ifeq ($(ARCH), x86)
+	CC = gcc
+else
+	CC = arm-linux-gnueabihf-gcc
+endif
+#存放中间文件的路径
+build_dir = build_$(ARCH)
+#存放源文件的文件夹
+src_dir =  sources
+#存放头文件的文件夹
+inc_dir = includes .
+
+#源文件
+sources = $(foreach dir,$(src_dir),$(wildcard $(dir)/*.c))
+#目标文件（*.o）
+objects = $(patsubst %.c,$(build_dir)/%.o,$(notdir $(sources)))
+#头文件
+includes = $(foreach dir,$(inc_dir),$(wildcard $(dir)/*.h))
+
+#目标依赖文件
+DEP_FILES := $(patsubst %, .%.d,$(objects))
+DEP_FILES := $(wildcard $(DEP_FILES))
+
+#判断依赖文件是否存在
+ifneq ($(DEP_FILES),)
+#如果存在依赖文件，需要导入依赖文件
+include $(DEP_FILES)
+endif
+
+#编译参数
+#指定头文件的路径
+CFLAGS = $(patsubst %, -I%, $(inc_dir)) -MD -MF $(@D)/.$(@F).d
+
+#链接过程
+$(build_dir)/$(Target) : $(objects)  | create_build
+	$(CC) $^ -o $@
+
+#编译工程
+#编译src文件夹中的源文件，并将生成的目标文件放在objs文件夹中
+$(build_dir)/%.o : $(src_dir)/%.c $(includes) | create_build
+	$(CC) -c $(CFLAGS) $< -o $@
+
+
+#以下为伪目标，调用方式：make 伪目标
+#clean：用于Clean Project
+#check：用于检查某个变量的值
+.PHONY:clean cleanall check create_build
+#按架构删除
+clean:
+	rm -rf $(build_dir)
+
+#全部删除
+cleanall:
+	rm -rf build_x86 build_arm
+
+#命令前带"@",表示不在终端上输出执行的命令
+#这个目标主要是用来调试Makefile时输出一些内容
+check:
+	@echo $(CFLAGS)
+	@echo $(CURDIR)
+	@echo $(src_dir)
+	@echo $(sources)
+	@echo $(objects)
+
+
+#创建一个新目录create，用于存放过程文件
+create_build:
+	@mkdir -p $(build_dir)
+
+
diff --git a/base_code/system_programing/wait/sources/wait.c b/base_code/system_programing/wait/sources/wait.c
new file mode 100644
index 0000000000000000000000000000000000000000..ec108f823ad3c3fe83a2549bc6170dd99109f71d
--- /dev/null
+++ b/base_code/system_programing/wait/sources/wait.c
@@ -0,0 +1,142 @@
+/** wait.c */
+/**
+ * pid_t waitpid(pid_t pid, int *status, int options)
+ * 
+ * pid：
+ *  pid > 0：只等待进程 ID 等于 pid 的子进程，不管已经有其他子进程运行结束退出了，只要指定的子进程还没有结束， waitpid()就会一直等下去
+ *  pid = -1：等待任何一个子进程退出，此时和 wait()作用一样
+ *  pid = 0：等待其组 ID 等于调用进程的组 ID 的任一子进程
+ *  pid < -1：等待其组 ID 等于 pid 的绝对值的任一子进程
+ * 
+ * status: 是一个整型指针，是该子进程退出时的状态， status 若不为空，则通过它可以获得子进程的结束状态
+ * 另外，子进程的结束状态可由 Linux 中一些特定的宏来测定
+ * 
+ * options:
+ *  WNOHANG：若由 pid 指定的子进程不立即可用，则 waitpid()不阻塞，此时返回值为 0
+ *  WUNTRACED：若实现某支持作业控制，则由 pid 指定的任一子进程状态已暂停，且其状态自暂停以来还未报告过，则返回其状态
+ *  0：同 wait()，阻塞父进程，等待子进程退出
+ * 
+ * 返回
+ *  正常：已经结束运行的子进程的进程号
+ *  使用选项 WNOHANG 且没有子进程退出： 0
+ *  调用出错： -1
+ */
+
+
+/** 
+ * demo 说明：
+ * 使用 fork()创建一个子进程，然后让其子进程暂停 5s（使用了 sleep()函数）。接下来对原有的父进程使用 waitpid()函数，并使用参数
+ * WNOHANG 使该父进程不会阻塞。若有子进程退出，则 waitpid()返回子进程号；若没有子进程退出，则waitpid()返回 0，并且父进程每隔一秒循环判断一次。
+ */
+
+
+#include <sys/types.h>
+#include <sys/wait.h>
+#include <unistd.h>
+#include <stdio.h>
+#include <stdlib.h>
+
+#define     WAIT   0
+#define     WAITPID  1
+
+#if ((WAIT | WAITPID) == 0)
+#error "must choose a function to compile!"
+#endif
+
+#if (WAIT & WAITPID)
+#error "have and can only choose one of the functions to compile"
+#endif
+
+
+#if WAIT
+
+int main()
+{
+    pid_t pid, child_pid;
+    int status;
+
+    pid = fork();
+
+    if (pid < 0) {
+        printf("Error fork\n");
+    }
+    /*子进程*/
+    else if (pid == 0) {
+
+        printf("I am a child process!, my pid is %d!\n\n",getpid());
+
+        /*子进程暂停 3s*/
+        sleep(3);
+
+        printf("I am about to quit the process!\n\n");
+
+        /*子进程正常退出*/
+        exit(0);
+    }
+    /*父进程*/
+    else {
+
+        /*调用 wait，父进程阻塞*/
+        child_pid = wait(&status);
+
+        /*若发现子进程退出，打印出相应情况*/
+        if (child_pid == pid) {
+            printf("Get exit child process id: %d\n",child_pid);
+            printf("Get child exit status: %d\n\n",status);
+        } else {
+            printf("Some error occured.\n\n");
+        }
+
+        exit(0);
+    }
+}
+
+#endif
+
+#if WAITPID
+
+int main()
+{
+    pid_t pid, child_pid;
+    int status;
+
+    pid = fork();
+
+    if (pid < 0) {
+        printf("Error fork\n");
+    }
+    /*子进程*/
+    else if (pid == 0) {
+
+        printf("I am a child process!, my pid is %d!\n\n",getpid());
+
+        /*子进程暂停 3s*/
+        sleep(3);
+
+        printf("I am about to quit the process!\n\n");
+        /*子进程正常退出*/
+        exit(0);
+    }
+    /*父进程*/
+    else {
+
+        /*调用 waitpid，且父进程不阻塞*/
+        child_pid = waitpid(pid, &status, WUNTRACED);
+
+        /*若发现子进程退出，打印出相应情况*/
+        if (child_pid == pid) {
+            printf("Get exit child process id: %d\n",child_pid);
+            printf("Get child exit status: %d\n\n",status);
+        } else {
+            printf("Some error occured.\n");
+        }
+
+        exit(0);
+    }
+}
+
+#endif
+
+
+
+
diff --git a/base_code/system_programing/wait/targets b/base_code/system_programing/wait/targets
new file mode 100644
index 0000000000000000000000000000000000000000..a404781031d6a6806c41ccc648590ec204ae6559
Binary files /dev/null and b/base_code/system_programing/wait/targets differ
diff --git a/base_code/system_programing/wait/wait.c b/base_code/system_programing/wait/wait.c
new file mode 100644
index 0000000000000000000000000000000000000000..c82d5e20b078223ebac470d982e17a79bc65f7ee
--- /dev/null
+++ b/base_code/system_programing/wait/wait.c
@@ -0,0 +1,142 @@
+/** wait.c */
+/**
+ * pid_t waitpid(pid_t pid, int *status, int options)
+ * 
+ * pid：
+ *  pid > 0：只等待进程 ID 等于 pid 的子进程，不管已经有其他子进程运行结束退出了，只要指定的子进程还没有结束， waitpid()就会一直等下去
+ *  pid = -1：等待任何一个子进程退出，此时和 wait()作用一样
+ *  pid = 0：等待其组 ID 等于调用进程的组 ID 的任一子进程
+ *  pid < -1：等待其组 ID 等于 pid 的绝对值的任一子进程
+ * 
+ * status: 是一个整型指针，是该子进程退出时的状态， status 若不为空，则通过它可以获得子进程的结束状态
+ * 另外，子进程的结束状态可由 Linux 中一些特定的宏来测定
+ * 
+ * options:
+ *  WNOHANG：若由 pid 指定的子进程不立即可用，则 waitpid()不阻塞，此时返回值为 0
+ *  WUNTRACED：若实现某支持作业控制，则由 pid 指定的任一子进程状态已暂停，且其状态自暂停以来还未报告过，则返回其状态
+ *  0：同 wait()，阻塞父进程，等待子进程退出
+ * 
+ * 返回
+ *  正常：已经结束运行的子进程的进程号
+ *  使用选项 WNOHANG 且没有子进程退出： 0
+ *  调用出错： -1
+ */
+
+
+/** 
+ * demo 说明：
+ * 使用 fork()创建一个子进程，然后让其子进程暂停 5s（使用了 sleep()函数）。接下来对原有的父进程使用 waitpid()函数，并使用参数
+ * WNOHANG 使该父进程不会阻塞。若有子进程退出，则 waitpid()返回子进程号；若没有子进程退出，则waitpid()返回 0，并且父进程每隔一秒循环判断一次。
+ */
+
+
+#include <sys/types.h>
+#include <sys/wait.h>
+#include <unistd.h>
+#include <stdio.h>
+#include <stdlib.h>
+
+#define     WAIT   0
+#define     WAITPID  1
+
+#if ((WAIT | WAITPID) == 0)
+#error "must choose a function to compile!"
+#endif
+
+#if (WAIT & WAITPID)
+#error "have and can only choose one of the functions to compile"
+#endif
+
+
+#if WAIT
+
+int main()
+{
+    pid_t pid, child_pid;
+    int status;
+
+    pid = fork();
+
+    if (pid < 0) {
+        printf("Error fork\n");
+    }
+    /*子进程*/
+    else if (pid == 0) {
+
+        printf("I am a child process!, my pid is %d!\n\n",getpid());
+
+        /*子进程暂停 3s*/
+        sleep(3);
+
+        printf("I am about to quit the process!\n\n");
+
+        /*子进程正常退出*/
+        exit(0);
+    }
+    /*父进程*/
+    else {
+
+        /*调用 wait，父进程阻塞*/
+        child_pid = wait(&status);
+
+        /*若发现子进程退出，打印出相应情况*/
+        if (child_pid == pid) {
+            printf("Get exit child process id: %d\n",child_pid);
+            printf("Get child exit status: %d\n\n",status);
+        } else {
+            printf("Some error occured.\n\n");
+        }
+
+        exit(0);
+    }
+}
+
+#endif
+
+#if WAITPID
+
+int main()
+{
+    pid_t pid, child_pid;
+    int status;
+
+    pid = fork();
+
+    if (pid < 0) {
+        printf("Error fork\n");
+    }
+    /*子进程*/
+    else if (pid == 0) {
+
+        printf("I am a child process!, my pid is %d!\n\n",getpid());
+
+        /*子进程暂停 3s*/
+        sleep(3);
+
+        printf("I am about to quit the process!\n\n");
+        /*子进程正常退出*/
+        exit(0);
+    }
+    /*父进程*/
+    else {
+
+        /*调用 waitpid，且父进程不阻塞*/
+        child_pid = waitpid(pid, &status, WUNTRACED);
+
+        /*若发现子进程退出，打印出相应情况*/
+        if (child_pid == pid) {
+            printf("Get exit child process id: %d\n",child_pid);
+            printf("Get child exit status: %d\n\n",status);
+        } else {
+            printf("Some error occured.\n");
+        }
+
+        exit(0);
+    }
+}
+
+#endif
+
+
+
+
diff --git a/documentation/appendix/bit_operation.rest b/documentation/appendix/bit_operation.rest
index 5ad595afc6256f7a504d5e8868c72198bbbb676b..822b2808f261ff79cdfddd1e92073363eac9566b 100644
--- a/documentation/appendix/bit_operation.rest
+++ b/documentation/appendix/bit_operation.rest
@@ -32,7 +32,7 @@
 
 10 //假如a中原来的值为二进制数： a = 1001 1111 b
 
-11 //所得的数与a作”位与&”运算，a = (1001 1111 b)&(1111 1011 b),
+11 //所得的数与a作"位与&"运算，a = (1001 1111 b)&(1111 1011 b),
 
 12 //经过运算后，a的值 a=1001 1011 b
 
@@ -67,7 +67,7 @@
 
 11 //假如a中原来的值为二进制数： a = 1001 1111 b
 
-12 //所得的数与a作”位与&”运算，a = (1001 1111 b)&(1111 0011 b),
+12 //所得的数与a作"位与&"运算，a = (1001 1111 b)&(1111 0011 b),
 
 13 //经过运算后，a的值 a=1001 0011 b
 
@@ -79,7 +79,7 @@
 
 17 //括号中的(2)为每组的位数，每组有2个二进制位;若分成4个一组，此处即为4
 
-18 //括号中的(3)是组内所有位都为1时的值;若分成4个一组，此处即为二进制数“1111 b”
+18 //括号中的(3)是组内所有位都为1时的值;若分成4个一组，此处即为二进制数"1111 b"
 
 19
 
@@ -96,7 +96,7 @@
 
 1 //a = 1000 0011 b
 
-2 //此时对清零后的第2组bit4、bit5设置成二进制数“01 b ”
+2 //此时对清零后的第2组bit4、bit5设置成二进制数"01 b "
 
 3
 
diff --git a/documentation/bare_metal/asemble_led.rst b/documentation/bare_metal/asemble_led.rst
index 8f22f34cc028df9e62d8d374b526500f033e0a3d..9ba95725953e9b74311e47be2414b915b1eb86e1 100644
--- a/documentation/bare_metal/asemble_led.rst
+++ b/documentation/bare_metal/asemble_led.rst
@@ -3,9 +3,6 @@
 汇编点亮LED灯
 --------------------------------------------------------------------
 
-本章节内容处于开发笔记状态，还待整理至最终版的教程。
-
-本章节内容处于开发笔记状态，还待整理至最终版的教程。
 
 从本章开始我们正式开启基于i.MX6ULL的裸机开发，本章将会带领大家用用汇编语言从零开始写一个点亮LED程序。可能部分读者会担心自己的汇编基础不好或者不会汇编，这都没关系，因为我们只用到了一些或者可以说是几个常用的汇编指令。
 
@@ -17,6 +14,11 @@
 
 -  掌握交叉编译器的使用方法。
 
+配套源码以及下载工具:
+-  路径：~/embed_linux_tutorial/base_code/bare_metal/led_s
+-  野火裸机下载工具download_tool（路径：~/embed_linux_tutorial/base_code/bare_metal/download-tool/download-tool.tar.bz2）。
+
+
 GPIO简介
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
@@ -188,7 +190,7 @@ IOMUXC_SW_MUX_CTL_PAD_XXXX引脚模式寄存器
 可以看到，该寄存器主要有两个配置域，分别是SION和MUX_MODE，其中SION用于设置引脚在输出模式下同时开启输入通道。重点是MUX_MODE的配置，它使用4个寄存器位表示可选的ALT0~ALT7这8个模式，如ALT2模式就是用于usb外设的USB_OTG1_PWR信号；若配置为ALT5则引脚会
 用作普通的GPIO功能，用于输出高、低电平。 这也是本章所需要的。
 
-IOMUXC_SW\_ PAD_CTL_PAD_XXXX引脚属性寄存器
+IOMUXC_SW_PAD_CTL_PAD_XXXX引脚属性寄存器
 
 
 类似地，以GPIO1_IO04引脚中PAD寄存器在参考手册中的描述如下。
@@ -338,13 +340,13 @@ xternal Signals and Pin Multiplexing搜索引脚名，以CSI_HSYNC为例，如
 
 从中可以看出CSI_HSYNC对应的GPIO引脚为GPIO4_IO20。
 
-第二种，在官方写好的文件中查找，我们打开“fsl_iomuxc.h”文件（可以打开IAR工程找到该文件也可以在工程目录下直接搜索）。直接在“fsl_iomuxc.h”文件中搜索得到的LED灯对应的引脚CSI_HSYNC（或CSI_VSYNC）得到如下所示的结果（以CSI_HSYNC为例）。
+第二种，在官方写好的文件中查找，我们打开"fsl_iomuxc.h"文件（可以打开IAR工程找到该文件也可以在工程目录下直接搜索）。直接在"fsl_iomuxc.h"文件中搜索得到的LED灯对应的引脚CSI_HSYNC（或CSI_VSYNC）得到如下所示的结果（以CSI_HSYNC为例）。
 
 .. image:: media/asembl014.png
    :align: center
 
 
-从图中不难看出这就是我们要找的引脚，每个宏定义分“三段”，以宏IOMUXC_CSI_HSYNC_I2C2_SCL为例，IOMUXC代表这是一个引脚复用宏定义，CSI_HSYNC代表原理图上实际的芯片引脚名，I2C2_SCL代表引脚的复用功能。一个引脚有多个复用功能，本章要把CSI_HSYNC用作GP
+从图中不难看出这就是我们要找的引脚，每个宏定义分"三段"，以宏IOMUXC_CSI_HSYNC_I2C2_SCL为例，IOMUXC代表这是一个引脚复用宏定义，CSI_HSYNC代表原理图上实际的芯片引脚名，I2C2_SCL代表引脚的复用功能。一个引脚有多个复用功能，本章要把CSI_HSYNC用作GP
 IO控制LED灯，所以本实验要选择IOMUXC_CSI_HSYNC_GPIO4_IO20
 宏定义引脚CSI_HSYNC复用为GPIO4_IO20，具体怎么使用程序中再详细介绍。
 
@@ -367,9 +369,9 @@ B灯   CSI_VSYNC    CSI_VSYNC  GPIO4_IO19
 创建源码文件
 ''''''''''''''''''''''''''''''''''''''''''''''''''
 
-编写软件之前首先要规划好软件的存储位置，本教程按照章节放置程序，例如本章的程序会放在“/home/pan/section4/led”，其中“pan”是我登录使用的用户名。“section4”代表第四部分的代码，“led_s”代表汇编语言编写的led程序。
+编写软件之前首先要规划好软件的存储位置，本教程按照章节放置程序，例如本章的程序会放在"/home/pan/section4/led"，其中"pan"是我登录使用的用户名。"section4"代表第四部分的代码，"led_s"代表汇编语言编写的led程序。
 
-我们在“led_s”文件夹下创建led.S文件用于存放led汇编驱动代码。创建完成后转到图形界面使用VScode软件打开led.S文件即可。
+我们在"led_s"文件夹下创建led.S文件用于存放led汇编驱动代码。创建完成后转到图形界面使用VScode软件打开led.S文件即可。
 
 源码讲解
 ''''''''''''''''''''''''
@@ -466,7 +468,7 @@ B灯   CSI_VSYNC    CSI_VSYNC  GPIO4_IO19
 
 整个源码按照功能分成了十部分，集合代码各部分指令讲解如下:
 
--  第一部分，.text 定义代码段。.align 2 设置字节对齐。.global \_start 生命全局标号_start。
+-  第一部分，.text 定义代码段。.align 2 设置字节对齐。.global _start 生命全局标号_start。
 
 -  第二部分，_start: 定义标号_start: ，它位于汇编的最前面，说以会首先被执行。
 
@@ -476,16 +478,16 @@ B灯   CSI_VSYNC    CSI_VSYNC  GPIO4_IO19
 -  第三部分，通过修改PC15寄存器（系统控制寄存器）关闭I Cache 、D Cache、MMU等等
    我们暂时用不到的功能，如果开启可能会影响我们裸机运行，为避免不必要的麻烦暂时关闭这些功能。
 
--  第四部分，执行“bl”跳转指令，代码将跳转到函数“light_led”执行。回顾我们之前讲的跳转指
-   令，“bl”指令是“可返回”跳转，跳转之前的执行地址保存在lr（连接寄存器）中。“light_led” 函数实现位于第六到十二部分。
+-  第四部分，执行"bl"跳转指令，代码将跳转到函数"light_led"执行。回顾我们之前讲的跳转指
+   令，"bl"指令是"可返回"跳转，跳转之前的执行地址保存在lr（连接寄存器）中。"light_led" 函数实现位于第六到十二部分。
 
--  第五部分，light_led函数返回后就会执行标号loop处的代码，而标号loop处只有一条指令“b loop”，这个指
+-  第五部分，light_led函数返回后就会执行标号loop处的代码，而标号loop处只有一条指令"b loop"，这个指
    令是代码再次跳转到loop标号处，所以这是一个死循环
 
 -  第六部分，定义我们用到的寄存器地址，这些寄存器在讲解GPIO时已经介绍，这里不再赘述。
 
 -  第七部分，开启GPIO1的时钟。第七部分到第十一部分非常相似，都是向寄存器内写数据，差别是要
-   写的寄存器以及写入的值不同。写入的寄存器地址可以查表得到，我们重点说明一下要写入的值。这部分是设置的时钟控制寄存器“CCM_CCGR1”，直接在《IMX6ULRM》搜索它可以找到如下所示的表格。
+   写的寄存器以及写入的值不同。写入的寄存器地址可以查表得到，我们重点说明一下要写入的值。这部分是设置的时钟控制寄存器"CCM_CCGR1"，直接在《IMX6ULRM》搜索它可以找到如下所示的表格。
 
 .. image:: media/asembl015.png
    :align: center
@@ -510,7 +512,7 @@ CCM_CCGR1[26:27]的值 时钟状态描述
    我们将CCM_CCGR1[26:27]设置为11（二进制）即可。仔细观察可以发现发现CCM_CCGR1寄存器默认全为1，即默认开启了时钟。为了程序规范我们再次使用代码开启时钟。将CCM_CCGR1寄存器设置全为1。
 
 -  第八部分，设置引脚复用功能为GPIO。这里设置的是GPIO1_04的引脚复用寄存器，我们直接
-   搜索“IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO04”可以找到如下所示的寄存器。
+   搜索"IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO04"可以找到如下所示的寄存器。
 
 ..
 
@@ -523,14 +525,14 @@ CCM_CCGR1[26:27]的值 时钟状态描述
 从上图可知IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO04[MUX_MODE]=0101(B)时GPIO1_04复用功能是GPIO。所以在程序中我们将0x5写入该寄存即可。
 
 -  第九部分，设置引脚的PAD属性。同样的方法，在《IMX6ULRM》搜索寄存器定义，然后确定
-   需要写入的值即可。这里设置的是引脚pad属性寄存器“IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO04”
+   需要写入的值即可。这里设置的是引脚pad属性寄存器"IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO04"
 
 -  第十部分，设置GPIO为输出模式。
 
 -  第十一部分，设置GPIO输出电平为低电平。
 
--  第十二部分，从light_led函数返回。在第四部分说到，我们使用“bl”指令跳转到light_led函数执
-   行，“bl”指令是“可返回”的跳转指令，返回地址保存在“LR”（连接寄存器）里，这里使用“mov”指令将“lr”寄存器的值写入“pc”寄存器即可。
+-  第十二部分，从light_led函数返回。在第四部分说到，我们使用"bl"指令跳转到light_led函数执
+   行，"bl"指令是"可返回"的跳转指令，返回地址保存在"LR"（连接寄存器）里，这里使用"mov"指令将"lr"寄存器的值写入"pc"寄存器即可。
 
 编译下载
 ''''''''''''''''''''''''''''''''
@@ -555,7 +557,7 @@ makefile 以及连接器脚本帮助我们完成这部分工作。
 
 -  led.S，要编译的源文件。
 
--  -o，指定输出文件的文件名，不加“-o led.o”默认会输出led.o。
+-  -o，指定输出文件的文件名，不加"-o led.o"默认会输出led.o。
 
 ..
 
@@ -600,16 +602,16 @@ makefile 以及连接器脚本帮助我们完成这部分工作。
 为二进制文件添加头并烧写到SD卡
 
 
- 在上一章我们详细讲解了如何将二进制文件烧写到SD卡（烧写工具自动实现为二进制文件添加头）。这里简单说明下载步骤。
+ 在编译下载官方SDK程序到开发板章节我们详细讲解了如何将二进制文件烧写到SD卡（烧写工具自动实现为二进制文件添加头）。这里简单说明下载步骤。
 
 -  将一张空SD卡（烧写一定会破坏SD卡中原有数据！！！烧写前请保存好SD卡中的数据），接入电脑后在虚拟机的右下角状态栏找到对应的SD卡。将其链接到虚拟机。
 
--  进入烧写工具目录，执行“./mkimage.sh <烧写文件路径>”命令,例如要烧写的led.bin位
-   于home目录下，则烧写命令为“./mkimage.sh /home/led.bin”。
+-  进入烧写工具目录，执行"./mkimage.sh <烧写文件路径>"命令,例如要烧写的led.bin位
+   于home目录下，则烧写命令为"./mkimage.sh /home/led.bin"。
 
 -  执行上一步后会列出linux下可烧写的磁盘，选择你插入的SD卡即可。这一步非常危险！！！一定要确
    定选择的是你插入的SD卡！！，如果选错很可能破坏你电脑磁盘内容，造成数据损坏！！！。确定磁盘后
-   SD卡以“sd”开头，选择    “sd”后面的字符即可。例如要少些的sd卡是“sdb”则输入“b”即可。
+   SD卡以"sd"开头，选择    "sd"后面的字符即可。例如要少些的sd卡是"sdb"则输入"b"即可。
 
 实验现象
 ''''''''''''''''''''''''''''''''
diff --git a/documentation/bare_metal/beautify_led.rst b/documentation/bare_metal/beautify_led.rst
index 362fcf46b83c5a63b54c3bb7c9ddf5fa76cbd916..de8ad0d0eb9fdafeb139b2c2e78251f9efe1c55a 100644
--- a/documentation/bare_metal/beautify_led.rst
+++ b/documentation/bare_metal/beautify_led.rst
@@ -3,11 +3,11 @@
 完善LED程序
 ------------------------------------------
 
-本章节内容处于开发笔记状态，还待整理至最终版的教程。
 
-本章节内容处于开发笔记状态，还待整理至最终版的教程。
 
-在上两章我们分别使用汇编语言和C语言实现了点亮LED灯。仔细分析代码不难发现我们仅仅操作了一个GPIO就需要自己查找、定义那么多寄存器。这样做的缺点很明显，易错、费时、代码可读性差。NXP官方SDK中已经将所有的寄存器以及所有可用引脚的复用功能定义好了，本章将简单介绍这些内容并把它们添加到我们的程序
+在上两章我们分别使用汇编语言和C语言实现了点亮LED灯。仔细分析代码不难发现我们仅仅操作了一个GPIO就需要自己查找、定义
+那么多寄存器。这样做的缺点很明显，易错、费时、代码可读性差。NXP官方SDK中已经将所有的寄存器以及所有可用引脚的复用
+功能定义好了，本章将简单介绍这些内容并把它们添加到我们的程序
 。
 
 本章主要内容：
@@ -19,6 +19,12 @@
 -  使用官方定义的寄存器、引脚设置函数实现RGB灯程序。
 
 
+配套源码以及下载工具:
+-  路径：~/embed_linux_tutorial/base_code/bare_metal/led_rgb_c
+-  野火裸机下载工具download_tool（路
+   径：~/embed_linux_tutorial/base_code/bare_metal/download-tool/download-tool.tar.bz2）。
+
+
 
 
 
@@ -31,8 +37,8 @@
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 
 在官方SD
-K的“SDK_2.2_MCIM6ULL_EBF6ULL\devices\MCIMX6Y2”目
-录下，头文件“MCIMX6Y2.h”保存了i.MX 6U芯
+K的"SDK_2.2_MCIM6ULL_EBF6ULL\devices\MCIMX6Y2"目
+录下，头文件"MCIMX6Y2.h"保存了i.MX 6U芯
 片几乎所有的寄存器定义以及中断编号的定义，本章我们只关心寄存器的定义，有关中断以及中断编号将会在中断章节
 详细介绍。部分寄存器定义如下所示。
 
@@ -62,7 +68,7 @@ K的“SDK_2.2_MCIM6ULL_EBF6ULL\devices\MCIMX6Y2”目
 
 
 
-这里只列GPIO1相关寄存器的部分截图。其他寄存器定义与此类似。添加这些定义之后我们就可以直接使用“GPIO1->DR”语句操作GPIO1的DR寄存器。操作方法与STM32非常相似。
+这里只列GPIO1相关寄存器的部分截图。其他寄存器定义与此类似。添加这些定义之后我们就可以直接使用"GPIO1->DR"语句操作GPIO1的DR寄存器。操作方法与STM32非常相似。
 
 引脚复用和引脚属性定义文件
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
@@ -141,12 +147,12 @@ K的“SDK_2.2_MCIM6ULL_EBF6ULL\devices\MCIMX6Y2”目
 
 这里只截取了一小部分代码，结合代码各部分说明如下：
 
--  第一部分，定义引脚的复用功能。这里只列出了“GPIO1_IO00”引脚的复用功能，其他引脚类似
-   。每个引脚对应多个宏定义代表引脚的不同的复用功能，以宏“IOMUXC_GPIO1_IO00_I2C2_SCL”为例，它表示“GPIO1_IO00”引脚复用为“I2C2”的“SCL”引脚。这些宏定义将会用作
+-  第一部分，定义引脚的复用功能。这里只列出了"GPIO1_IO00"引脚的复用功能，其他引脚类似
+   。每个引脚对应多个宏定义代表引脚的不同的复用功能，以宏"IOMUXC_GPIO1_IO00_I2C2_SCL"为例，它表示"GPIO1_IO00"引脚复用为"I2C2"的"SCL"引脚。这些宏定义将会用作
    第二部分和第三部分的函数入口参数。
 
--  第二部分，引脚复用功能设置函数。函数“IOMUXC_SetPinMux”拥有6个入口
-   参数，但是前五个是通过第一部分的宏定义自动完成设置的。而第6个入口参数“inputOnfiled”用于设置是否开启读回引脚电平功能。
+-  第二部分，引脚复用功能设置函数。函数"IOMUXC_SetPinMux"拥有6个入口
+   参数，但是前五个是通过第一部分的宏定义自动完成设置的。而第6个入口参数"inputOnfiled"用于设置是否开启读回引脚电平功能。
 
 -  第三部分，引脚PAD属性设置函数。与第二部分相同，函数共有6个入口参数，其中前五
    个是通过第一部分的宏定义自动完成设置的。而第6个参数用于设置PAD属性，根据之前讲解每个引脚拥有一个32位PAD
@@ -158,7 +164,7 @@ K的“SDK_2.2_MCIM6ULL_EBF6ULL\devices\MCIMX6Y2”目
 宏定义实现PAD属性设置
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 
-通常情况下一个引脚要设置8中PAD属性，而这些属性只能通过数字指定。为简化PAD属性设置我们编写了一个PAD属性配置文件“pad_config.h”，这里使用宏定义了引脚可选的PAD属性值，并且通过宏定义的名字很容易知道宏代表的属性值。如下所示。
+通常情况下一个引脚要设置8中PAD属性，而这些属性只能通过数字指定。为简化PAD属性设置我们编写了一个PAD属性配置文件"pad_config.h"，这里使用宏定义了引脚可选的PAD属性值，并且通过宏定义的名字很容易知道宏代表的属性值。如下所示。
 
 
 .. code-block:: c
@@ -186,7 +192,7 @@ K的“SDK_2.2_MCIM6ULL_EBF6ULL\devices\MCIMX6Y2”目
 
 
 
-这里只列出了文件“pad_config.h”部分代码，其他部分类似，结合代码各部分简单说明如下：
+这里只列出了文件"pad_config.h"部分代码，其他部分类似，结合代码各部分简单说明如下：
 
 -  第一部分，定义引脚带宽。从宏定义名可知带宽可设置为50M、100M、200M。
 
@@ -308,13 +314,13 @@ RGB灯代码实现
 
 代码很容易理解，这里只做简单的说明。
 
--  第一部分，添加头文件，文件“MCIMX6Y2.h”和“fsl_iomuxc.h”来
-   自SDK。文件“pad_config.h”是自己编写的文件，在其他工程中可直接使用。
+-  第一部分，添加头文件，文件"MCIMX6Y2.h"和"fsl_iomuxc.h"来
+   自SDK。文件"pad_config.h"是自己编写的文件，在其他工程中可直接使用。
 
 -  第二部分，定义LED灯相关引脚以及复用功能。
 
--  第三部分，定义引脚的PAD属性。PAD属性宏定义保存在“pad_config.h”文件中，这
-   里使用“|”运算符将所有属性设置“合并”在一起，后面将作为函数参数。
+-  第三部分，定义引脚的PAD属性。PAD属性宏定义保存在"pad_config.h"文件中，这
+   里使用"|"运算符将所有属性设置"合并"在一起，后面将作为函数参数。
 
 -  第四部分，简单的延时函数。
 
@@ -332,12 +338,12 @@ RGB灯代码实现
 打开本章配套例程，在 文件夹下执行make命令，makefile工具便会自动完成程序
 的编译、链接、格式转换等工作。正常情况下我们可以在当前目录看到生成的一些中间文件以及我们期待的.bin文件。
 
-在46.2.5 烧写到SD卡章节我们详细讲解了如何将二进制文件烧写到SD卡（烧写工具自动实现为二进制文件添加头）。这里再次说明下载步骤。
+在编译下载官方SDK程序到开发板章节我们详细讲解了如何将二进制文件烧写到SD卡（烧写工具自动实现为二进制文件添加头）。这里再次说明下载步骤。
 
 -  将一张空SD卡（烧写一定会破坏SD卡中原有数据！！！烧写前请保存好SD卡中的数据），接入电脑后在虚拟机的右下角状态栏找到对应的SD卡。将其链接到虚拟机。
 
--  进入烧写工具目录，执行“./mkimage.sh <烧写文件路径>”命令,例如要烧写
-   的led.bin位于home目录下，则烧写命令为“./mkimage.sh /home/led.bin”。
+-  进入烧写工具目录，执行"./mkimage.sh <烧写文件路径>"命令,例如要烧写
+   的led.bin位于home目录下，则烧写命令为"./mkimage.sh /home/led.bin"。
 
 -  执行上一步后会列出linux下可烧写的磁盘，选择你插入的SD卡即可。这一步非
-   常危险！！！一定要确定选择的是你插入的SD卡！！，如果选错很可能破坏你电脑磁盘内容，造成数据损坏！！！。确定磁盘后SD卡以“sd”开头，选择“sd”后面的字符即可。例如要烧写的sd卡是“sdb”则输入“b”即可。
+   常危险！！！一定要确定选择的是你插入的SD卡！！，如果选错很可能破坏你电脑磁盘内容，造成数据损坏！！！。确定磁盘后SD卡以"sd"开头，选择"sd"后面的字符即可。例如要烧写的sd卡是"sdb"则输入"b"即可。
diff --git a/documentation/bare_metal/before_developing.rst b/documentation/bare_metal/before_developing.rst
index 884f98d11fe17b25cd25a3104e368dc64fe55904..a4c886eb40cc18608f7f51b67366e3ee6f503b24 100644
--- a/documentation/bare_metal/before_developing.rst
+++ b/documentation/bare_metal/before_developing.rst
@@ -35,18 +35,18 @@ i.MX 6U外设寄存器以及内存被映射到4G的地址空间，如下所示
 标号①，DDR映射区域。DDR作为i.MX 6U的主内存区域，它被映射在0x8000 0000地址处，最大空间为2G，实际可用大小与选择的DDR芯片容量有关。
 
 标号②，QSPI1映射区域，i.MX 6U可以外接串行norflash，norflahs映射到0x6000
-000起始地址处。norflash，支持“本地执行”作用类似于STM32的内部FLASH。NXP的跨界处理器RT1050系列
+000起始地址处。norflash，支持"本地执行"作用类似于STM32的内部FLASH。NXP的跨界处理器RT1050系列
 就是用这个外部norflah存储代码。因为开发板已经使用了容量更大的EMMC或nand flash作为主存储器，所以配套开发板并没有外接norFlash
 
 标号③，EIM外扩存储器映射区域。i.MX 6U可以通过EIM总线外扩存储器，我们这里没有用到，不做过多介绍。
 
 标号④，启动引导程序（Boot ROM）内存映射区域，它位于芯片内部。启动引导程序（Boot ROM）位于起始
-地址0x0000 0000 处。我们知道芯片上电后（或硬件复位）会自动从“0”地址处开始执行。和容易得出，这里
+地址0x0000 0000 处。我们知道芯片上电后（或硬件复位）会自动从"0"地址处开始执行。和容易得出，这里
 就是保存的启动引导代码。有关启动引导程序（Boot
 ROM）是如何工作的，我们将在下一小节详细介绍。
 
 从上图我们可以知道i.MX 6U支持将多种存储器映射到4G的地址空间，我们只使用了DDR作为i.MX 6U的主内
-存区域，起始地址为0x8000 0000 ，大小由实际使用的DDR芯片决定。启动引导程序（Boot ROM）位于“0”地址处，大小为96Kb。
+存区域，起始地址为0x8000 0000 ，大小由实际使用的DDR芯片决定。启动引导程序（Boot ROM）位于"0"地址处，大小为96Kb。
 
 i.MX6UL的启动流程
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
@@ -57,7 +57,7 @@ i.MX6UL支持多种启动方式，而具体硬件平台支持的启动方式与
 Reference Manual》第八章System Boot。
 
 i.MX6UL完整的启动流程如下图所示，，完成启动任务的代码位于0x0000 0000 其实地
-址处的Boot ROM。本小节将以“上电到程序运行”这条主线讲解i.MX6UL启动流程。
+址处的Boot ROM。本小节将以"上电到程序运行"这条主线讲解i.MX6UL启动流程。
 
 .. image:: media/before004.png
    :align: center
@@ -72,7 +72,7 @@ i.MX6UL完整的启动流程如下图所示，，完成启动任务的代码位
 ''''''''''''''''''''''''''''''''''''''''
 
 系统上电或硬件复位后，CPU从0x0000 0000 地址开始
-执行Boot ROM代码（以下简称为“Boot ROM代码”）。Boot ROM代码首先会检查CPU的ID。这一步官方手册中也没有过多介绍，我们默认检测通过。
+执行Boot ROM代码（以下简称为"Boot ROM代码"）。Boot ROM代码首先会检查CPU的ID。这一步官方手册中也没有过多介绍，我们默认检测通过。
 
 检查复位状态。
 '''''''''''''''''''''''''''''''''''
@@ -83,9 +83,9 @@ i.MX6UL完整的启动流程如下图所示，，完成启动任务的代码位
 ''''''''''''''''''''''''''''''''''''
 
 在开发阶段我们可以通过设置i.MX6UL启动相关引脚的电平状态来改
-变芯片的启动方式。BOOT_MODE[1:0] = 10B ，i.MX6UL将会从“内部”启动，所谓“内部”是
-相对于“Serial Download”来说的，“内部”可以认为是i.MX6UL支持的启动存储设备，例如emmc
-、nandflash、SD card、norFlash等等。具体从那种“内部”设备启动，由BOOT_CFG1[7:4]决定，如下表所示。
+变芯片的启动方式。BOOT_MODE[1:0] = 10B ，i.MX6UL将会从"内部"启动，所谓"内部"是
+相对于"Serial Download"来说的，"内部"可以认为是i.MX6UL支持的启动存储设备，例如emmc
+、nandflash、SD card、norFlash等等。具体从那种"内部"设备启动，由BOOT_CFG1[7:4]决定，如下表所示。
 
 表 内部启动方式选择
 
@@ -172,9 +172,9 @@ System     11111 PL1      Always                   Both
 -  User 用户模式，用户模式是相对于Linux系统来说的，有Linux的情况下Linxu应用
    程序运行在User模式，i.MX 6U特权等级从低到高
    被分为3个等级（PL0~PL2），用户模
-   式属于PL0。用户模式下的执行有时被描述为“无特权执行”对系统来说User是安全的，User程序不会破坏系统。
+   式属于PL0。用户模式下的执行有时被描述为"无特权执行"对系统来说User是安全的，User程序不会破坏系统。
 
--  FIQ快速中断模式，当发生FIQ中断后CPU就会进入FIQ模式，FIQ即“快速中断”，再中断章节我们将会详细介绍。
+-  FIQ快速中断模式，当发生FIQ中断后CPU就会进入FIQ模式，FIQ即"快速中断"，再中断章节我们将会详细介绍。
 
 -  IRQ中断模式，当发生IRQ中断后CPU会进入中断模式，在中断章节我们将会详细介绍。
 
@@ -184,7 +184,7 @@ System     11111 PL1      Always                   Both
 
 -  Monitor mode监听模式，就像后台服务，这个模式主要用来安全扩展模式，只用于安全
 
--  Abort mode 终止模式，CPU读取数据错误或者预取错误发生时将会进入终止模式。终止模式可以认为系统“挂了”。
+-  Abort mode 终止模式，CPU读取数据错误或者预取错误发生时将会进入终止模式。终止模式可以认为系统"挂了"。
 
 -  Hyp mode 超级的监视模式，它主要用于一些虚拟化的扩展。
 
@@ -195,7 +195,7 @@ System     11111 PL1      Always                   Both
 ARM内核寄存器
 ''''''''''''''''''''''''''''''''''''''''''''''''''''''''
 
-学过STM32或其他单片机的朋友对“寄存器”肯定不陌生，但是我们接触的大多是“外设寄存器”外设寄存器本质是单片机（处理器）地址空间中的一块内存区域，CPU不能直接在内存中进行数据运算。与外设寄存器不同，内核寄存器并没有“地址”的概念，每款CPU的内核寄存是固定的，这些有限的内核寄存器根据功能分为多种
+学过STM32或其他单片机的朋友对"寄存器"肯定不陌生，但是我们接触的大多是"外设寄存器"外设寄存器本质是单片机（处理器）地址空间中的一块内存区域，CPU不能直接在内存中进行数据运算。与外设寄存器不同，内核寄存器并没有"地址"的概念，每款CPU的内核寄存是固定的，这些有限的内核寄存器根据功能分为多种
 类型，我们这小节带领大家认识ARM内核寄存器。
 
 i.MX 6内核寄存器分类
@@ -231,7 +231,7 @@ i.MX 6内核寄存器介绍
    数之前CPU自动将当前执行位置保存在LR链接
    寄存器中，子函数返回后接着LR寄存器指定的地址处执行。LR链接寄存器又被称为R14寄存器。
 
--  PC 程序计数寄存器，程序计数寄存器可理解为“程序的执行位置”，当执行ARM指
+-  PC 程序计数寄存器，程序计数寄存器可理解为"程序的执行位置"，当执行ARM指
    令时，PC寄存器保存当前执行位置加8，即下一条指定的地址。当执行Thumb指
    令时，PC寄存器保存当前执行位置加4，即下一条指定的地址。
 
@@ -262,7 +262,7 @@ i.MX 6内核寄存器介绍
 
 M[4:0]模式位：
 
-此字段保存处理器的当前模式，处理器工作模式请参考表 47‑3，M[4:0]字段对应表 47‑3第二列的“编码”，通过该位我们就可以知道处理器的当前工作模式。
+此字段保存处理器的当前模式，处理器工作模式请参考表 47‑3，M[4:0]字段对应表 47‑3第二列的"编码"，通过该位我们就可以知道处理器的当前工作模式。
 
 T[5]和J[24]指令状态位：
 
@@ -286,9 +286,9 @@ E[9]，字节顺序位：
 
 该位用于设置字节序，E[9] = 1B 为大端格式，E[9] = 0B 为小端格式。
 
-注：“大端”是指“高位”数据放在低地址处，“低位”数据放在高地址处，例如数据0x5566
-保存在0x8000起始地址处，如果是大端格式则地址0x8000 保存的是“0x55”地址0x8001保存的是“0x66”。小端格
-式正好相反，0x8000 保存的是“0x66” 址0x8001保存的是“0x55”。
+注："大端"是指"高位"数据放在低地址处，"低位"数据放在高地址处，例如数据0x5566
+保存在0x8000起始地址处，如果是大端格式则地址0x8000 保存的是"0x55"地址0x8001保存的是"0x66"。小端格
+式正好相反，0x8000 保存的是"0x66" 址0x8001保存的是"0x55"。
 
 (2) APSR（Application Program Status Register），与SPSR、CPSR类似，APSR保存CPU
 执行状态，不同的是APSR权限受到限制，只有CPSR（或SPSR）的部分功能，如下所示。
@@ -301,7 +301,7 @@ E[9]，字节顺序位：
 
 
 
-从上图可以看出，相比CPSR寄存器，这里的某些字段变为“Reserved”即这些字段已经不可访问了。
+从上图可以看出，相比CPSR寄存器，这里的某些字段变为"Reserved"即这些字段已经不可访问了。
 
 ARM内核寄存器相关内容暂时介绍到这里，其他内容使用到时再详细介绍。
 
diff --git a/documentation/bare_metal/building_sdk_demo.rst b/documentation/bare_metal/building_sdk_demo.rst
index ad9b3f1b6bf998858e51dca5e6a703c557a7326a..b1e9a06bbd6e49c4057ee42520a238345b1d544b 100644
--- a/documentation/bare_metal/building_sdk_demo.rst
+++ b/documentation/bare_metal/building_sdk_demo.rst
@@ -3,14 +3,11 @@
 编译下载官方SDK程序到开发板
 ---------------------------------------------------------------------------
 
-本章节内容处于开发笔记状态，还待整理至最终版的教程。
 
-本章节内容处于开发笔记状态，还待整理至最终版的教程。
+上一章我们简单讲解了SDK的目录结构，这一章进入主题——如何下载官方SDK程序到你手中的开发板。需要再次说明的是SDK是适配NXP官方评估板的，我们的开发板与官方SDK不完全兼容，言外之意大部分还是兼容的，尤其是设置为SD卡启动时，相似度更高。本章也将会带领大家在linux下编译官方SDK中的"he
+llo world"工程，并烧写到SD卡，最终放在我们的开发板上运行。
 
-上一章我们简单讲解了SDK的目录结构，这一章进入主题——如何下载官方SDK程序到你手中的开发板。需要再次说明的是SDK是适配NXP官方评估板的，我们的开发板与官方SDK不完全兼容，言外之意大部分还是兼容的，尤其是设置为SD卡启动时，相似度更高。本章也将会带领大家在linux下编译官方SDK中的“he
-llo world”工程，并烧写到SD卡，最终放在我们的开发板上运行。
-
-本章重点不是讲解“hello wordl”程序如何实现，而是
+本章重点不是讲解"hello wordl"程序如何实现，而是
 如何在linux下编译SDK工程，并放到你手中的开发板运行，直白的说就是编译环
 境的搭建以及编译、烧写操作流程。
 
@@ -20,6 +17,14 @@ llo world”工程，并烧写到SD卡，最终放在我们的开发板上运行
 
 -  掌握SDK程序编译、烧写流程，能够烧写SDK例程到开发板。
 
+配套源码以及工具:
+
+-  NXP 官方SDK（路径：~/embed_linux_tutorial/base_code/bare_metal/sdk_nxp）。
+-  野火裸机下载工具download_tool（路径：~/embed_linux_tutorial/base_code/bare_metal/download-tool/download-tool.tar.bz2）。
+
+
+
+
 SDK程序编译、烧写流程分析
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
@@ -33,7 +38,7 @@ SDK程序编译、烧写流程分析
 
 
 
-由于我们要在linux下编译、下载，所以我们需要选择armgcc版本工程。打开“armgcc”文件夹如下所示。
+由于我们要在linux下编译、下载，所以我们需要选择armgcc版本工程。打开"armgcc"文件夹如下所示。
 
 .. image:: media/buildi003.png
    :align: center
@@ -82,10 +87,10 @@ SDK程序编译、烧写流程分析
 获取官方SDK文件
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 
-官方SDK提供了Windows版本和Linux版本，两者在功能上并没有什么差别，但编码上稍有不同，比如Linux下键盘的“Enter”是“\n”,而Windows下键盘的“Enter”键是“\r\n”。为避免编码带来问题，我们选用Linux下的SDK。SDK可以参照上一章从NXP官网直接下载，也可以
+官方SDK提供了Windows版本和Linux版本，两者在功能上并没有什么差别，但编码上稍有不同，比如Linux下键盘的"Enter"是"\n",而Windows下键盘的"Enter"键是"\r\n"。为避免编码带来问题，我们选用Linux下的SDK。SDK可以参照上一章从NXP官网直接下载，也可以
 直接使用我们下载好的Linux版的SDK。
 
-使用共享文件夹将“SDK_2.2_MCIM6ULL_RFP_Linux.run” 拷贝到Linux下，存放位置
+使用共享文件夹将"SDK_2.2_MCIM6ULL_RFP_Linux.run" 拷贝到Linux下，存放位置
 自定。然后运行.run文件生成SDK linux下的源文件命令如下。
 
 .. code-block:: c
@@ -93,7 +98,7 @@ SDK程序编译、烧写流程分析
 
     sudo ./ SDK_2.2_MCIM6ULL_RFP_Linux.run
 
-注：运行SDK_xxx_xxx.run时可能会出现输入SDK_xxx_xxx.run时“tab”键无法自动补齐，并且手动输入完整文件名也不能运行。原因大多是当前用户没有SDK_xxx_xxx.run文件的执行权限。修改SDK_xxx_xxx.run文件的执行权限即可。
+注：运行SDK_xxx_xxx.run时可能会出现输入SDK_xxx_xxx.run时"tab"键无法自动补齐，并且手动输入完整文件名也不能运行。原因大多是当前用户没有SDK_xxx_xxx.run文件的执行权限。修改SDK_xxx_xxx.run文件的执行权限即可。
 
 SDK_xxx_xxx.run运行后会弹出图形化的界面，不过鼠标无法对界面上的选项进行操作，只能通过键盘上的方向键选择。例如在路径选择界面如下所示。
 
@@ -103,8 +108,8 @@ SDK_xxx_xxx.run运行后会弹出图形化的界面，不过鼠标无法对界
 
 
 
-我们通过“上下”方向键选择生成的SDK文件保存位置。“左右”方
-向键选择“Select”或“Abort Installation”。需要说明的是图 46‑3中选项1表示生成的SDK保存在
+我们通过"上下"方向键选择生成的SDK文件保存位置。"左右"方
+向键选择"Select"或"Abort Installation"。需要说明的是图 46‑3中选项1表示生成的SDK保存在
 你当前登录的用户文件夹下，不同用户路径不同。
 
 SDK_xxx_xxx.run运行结束后会在我们制定的目录生成Linux下的SDK。
@@ -113,7 +118,7 @@ SDK_xxx_xxx.run运行结束后会在我们制定的目录生成Linux下的SDK。
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 
 Linux下的SDK生成后，进入工程文
-件，“SDK_2.2_MCIM6ULL \\boards\evkmcimx6ull\demo_apps\hello_world\armgcc”运
+件，"SDK_2.2_MCIM6ULL \\boards\evkmcimx6ull\demo_apps\hello_world\armgcc"运
 行build_ddr_release.sh脚本，命令如下：
 
 .. code-block:: c
@@ -121,7 +126,7 @@ Linux下的SDK生成后，进入工程文
 
     ./build_ddr_release.sh
 
-build_ddr_release.sh用于生成*.bin文件，运行成功后会在当前文件夹下生成“ddr_release”文件夹，在文件夹中存在一个sdk20-app.bin文件，将sdk20-app.bin放到SD卡程序并不能直接运行，根据存储设备不同还要在sdk20-app.bin添加相应的头文件
+build_ddr_release.sh用于生成*.bin文件，运行成功后会在当前文件夹下生成"ddr_release"文件夹，在文件夹中存在一个sdk20-app.bin文件，将sdk20-app.bin放到SD卡程序并不能直接运行，根据存储设备不同还要在sdk20-app.bin添加相应的头文件
 然后才能在开发板上运行。
 
 注：运行build_ddr_release.sh常见错误如下所示。
@@ -133,16 +138,23 @@ build_ddr_release.sh用于生成*.bin文件，运行成功后会在当前文件
 
 从错误提示不难看出，错误原因是没
 有添加ARMGCC_DIR环境变量，根据之前讲解添加环境变量
-命令“export ARMGCC_DIR=/usr”只在当前端口有效，所以在当前端口再次执行命令“export
-ARMGCC_DIR=/usr”添加环境变量即可(不建议将环境变量添加到系统环境变量中，因为该环境变量只有编译官方SDK程序才用的到，后面章节主要是自己写程序)。
+命令"export ARMGCC_DIR=/usr"只在当前端口有效，所以在当前端口再次执行命令"export
+ARMGCC_DIR=/usr"添加环境变量即可(不建议将环境变量添加到系统环境变量中，因为该环境变量只有编译官方SDK程序才用的到，后面章节主要是自己写程序)。
 
 烧写到SD卡
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 
-上一步生成的.bin文件并不能直接放到开发板上执行，因为缺少必要的头文件。在SDK中“SDK_2.2_MCIM6ULL\tools\imgutil”下readme.txt文件介绍了添加头文件的步骤，如果使用官方介绍步骤比较繁琐，我们提供了“embedfire_download”烧写工具。下面将基于该
-烧写工具讲解添加头文件以及烧写步骤。
+配套源码以及工具:
+
+
+
+上一步生成的.bin文件并不能直接放到开发板上执行，因为缺少必要的头
+文件。在SDK中“SDK_2.2_MCIM6ULL\tools\imgutil”下readme.txt文件介绍了添加
+头文件的步骤，如果使用官方介绍步骤比较繁琐，我们提供了“embedfire_download”烧写工具(路
+径：~/embed_linux_tutorial/base_code/bare_metal/download-tool/download-tool.tar.bz2)。下面将
+基于该烧写工具讲解添加头文件以及烧写步骤。
 
-“embedfire_download”烧写工具集成了添加头文件和烧写到SD卡等步骤。详细介绍如下：
+"embedfire_download"烧写工具集成了添加头文件和烧写到SD卡等步骤。详细介绍如下：
 
 硬件要求：
 
@@ -187,14 +199,14 @@ ARMGCC_DIR=/usr”添加环境变量即可(不建议将环境变量添加到系
 
 选错设备，可能导致电脑数据被破坏！！！！
 
-我们可以比较SD卡接入和拔出时设备列表的差异确定那个是SD卡设备。确定那个是插入的SD卡设备后输入设备ID即可，在我的电脑上SD卡是“sdb”所以输入“b”即可。
+我们可以比较SD卡接入和拔出时设备列表的差异确定那个是SD卡设备。确定那个是插入的SD卡设备后输入设备ID即可，在我的电脑上SD卡是"sdb"所以输入"b"即可。
 
 实验现象
 
 
 将开发板的启动选择开关设置为SD卡启动，使用串口调试助手链接
 开发板的串口1，将SD卡插入开发板，启动后正常情况下可以在串口调试助手
-中看到开发板发出的“hello world”.
+中看到开发板发出的"hello world".
 
 .. |buildi002| image:: media/buildi002.png
    :width: 5.76806in
diff --git a/documentation/bare_metal/ccm.rst b/documentation/bare_metal/ccm.rst
index 672b34c3809d2ec0f3758e3ac8a6e41e3f99eb31..6a413c8379c5d0b080fecd3be12afc19c04e089e 100644
--- a/documentation/bare_metal/ccm.rst
+++ b/documentation/bare_metal/ccm.rst
@@ -10,6 +10,14 @@
 本章我们主要讲解时钟部分，芯片内部的各个设备都在时钟的驱动下运行，了解整个芯片的时钟树、时钟配置，那么对i.MX 6U的一切时钟的来龙去脉都会了如指掌。
 
 时钟控制模块（CCM）的主要作用
+
+配套源码以及下载工具:
+-  路径：~/embed_linux_tutorial/base_code/bare_metal/clock_init
+-  野火裸机下载工具download_tool（路
+   径：~/embed_linux_tutorial/base_code/bare_metal/download-tool/download-tool.tar.bz2）。
+
+
+
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
 i.MX 6U的时钟系统由时钟控制模块CCM进行控制，其主要功能如下：
@@ -117,7 +125,7 @@ ARM PLL(PLL 1)只有一个控制寄存器CCM_ANALOG_PLL_ARMn，
  的外部时
  钟。CCM_ANALOG_PLL_ARMn[DIV_SELECT]位选
  择锁相环分频值(DIV_SELECT)。取值范围为54到108。输出频率计
- 算公式为 ARM_PLL = Fin \* DIV_SELECT/2.0。如果选
+ 算公式为 ARM_PLL = Fin * DIV_SELECT/2.0。如果选
  择24MHz参
  考
  时钟作为时钟输入，DIV_SELECT选
@@ -155,7 +163,7 @@ PLL输出时钟和PFD输出时钟经选择和分频后将作为内核或外设
 时钟选择器（CLOCK
 SWITCHER）输出了多个频率不同的PLL时钟和PFD时钟。每个外设时钟通过MUX模块连接到多个PLL时钟输出，每个MUX实际是一个寄存器，用于选择时钟源。时钟分频也是一个寄存器位。总之就是通过配置对应的寄存器为外设选择时钟源并设置时钟频率。具体是那些寄存器？在图中标记的很清楚，根据图中标注可以很容易、灵活的配置时钟。
 
-下面以“ARM_CLK_ROOT”时钟为例讲解，时钟配置步骤。“ARM_CLK_ROOT”时钟是CPU时钟，也就是我们常说的主频。修改该时钟之前首先要将CPU时钟切换到另外一个可用的时钟，修改完成后再切换回来。具体下所示。（图片太大
+下面以"ARM_CLK_ROOT"时钟为例讲解，时钟配置步骤。"ARM_CLK_ROOT"时钟是CPU时钟，也就是我们常说的主频。修改该时钟之前首先要将CPU时钟切换到另外一个可用的时钟，修改完成后再切换回来。具体下所示。（图片太大
 ，图片中的字看不清楚，请查阅《IMX6ULRM》18.5.1 Clock Generation P631页）
 
 .. image:: media/CCM007.png
@@ -165,7 +173,7 @@ SWITCHER）输出了多个频率不同的PLL时钟和PFD时钟。每个外设时
 
 上图中，标号①与标号②处是CCSR时钟选择寄存器的两个配置位，用于设置时钟源。这里假设要将CPU时钟修改为792MHz。步骤如下：（具体代码在讲解代码时会介绍）
 
-(1) 配置CCSR寄存器，将 “ARM_CLK_ROOT”时钟切换到osc_clk（24MHz）
+(1) 配置CCSR寄存器，将 "ARM_CLK_ROOT"时钟切换到osc_clk（24MHz）
 
 ..
 
@@ -202,14 +210,14 @@ PLL1输出时钟设置方法已经在55.3 时钟树简介，第一小节介绍
 
 
 
-从上8可以看出，从PLL1到“ARM_CLK_ROOT”还要
+从上8可以看出，从PLL1到"ARM_CLK_ROOT"还要
 经过CACRR[ARM_PODF] 时钟分频寄存器。 进过上一步PLL1的输出时
 钟被设置为792MHz，所以这里设置CACRR[ARM_PODF] = 0，不分频。
 
 设置系统时钟实验
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
-系统时钟设置实验代码由“interrupt_init”代码修改得到，本章也只讲解新增部分代码，完整请参考本章配套源码。
+系统时钟设置实验代码由"interrupt_init"代码修改得到，本章也只讲解新增部分代码，完整请参考本章配套源码。
 
 
 硬件设计
@@ -224,10 +232,10 @@ PLL1输出时钟设置方法已经在55.3 时钟树简介，第一小节介绍
    9. ..
       rubric:: 添加源文件并修改makefile :name: 添加源文件并修改makefile
 
-拷贝“~/section5/interrupt_init”程序，并重命名为“~/section5/clock_init”。分别在“~/section5/clock_init/device”、“~/section5/clock_init/include”文件夹下添加clock.c、clock.h。添加
+拷贝"~/section5/interrupt_init"程序，并重命名为"~/section5/clock_init"。分别在"~/section5/clock_init/device"、"~/section5/clock_init/include"文件夹下添加clock.c、clock.h。添加
 了新的源文件，当然要将其添加到makefile 中。
 
-打开“~/section5/clock_init/ device”目录下的“makefile”文件，将clock.o添加到最终目标的依赖中，代码如下所示。
+打开"~/section5/clock_init/ device"目录下的"makefile"文件，将clock.o添加到最终目标的依赖中，代码如下所示。
 
 .. code-block:: c
    :caption: 修改makefile
@@ -510,20 +518,20 @@ PLL2的PFD输出大致分为三部分，第一，禁用PLL2的PFD输出。第二
 下载验证
 ''''''''''''''''''''''''
 
-程序编写完成后，在“/section5/ clock_init” 文件夹
+程序编写完成后，在"/section5/ clock_init" 文件夹
 下执行make命令，makefile工具便会自动完成程序的编译、链接、格式转
 换等工作。正常情况下我们可以在当前目录看到生成的一些中间文件以及我们期待的.bin文件。
 
-在46.2.5 烧写到SD卡章节我们详细讲解了如何将二进制文件烧写到SD卡（烧写工具自动实现为二进制文件添加头）。这里再次说明下载步骤。
+在编译下载官方SDK程序到开发板章节我们详细讲解了如何将二进制文件烧写到SD卡（烧写工具自动实现为二进制文件添加头）。这里再次说明下载步骤。
 
 -  将一张空SD卡（烧写一定会破坏SD卡中原有数据！！！烧写前请保存好SD卡中的数据），接入电脑后在虚拟机的右下角状态栏找到对应的SD卡。将其链接到虚拟机。
 
--  进入烧写工具目录，执行“./mkimage.sh <烧写文件路径>”命令,例如要
-   烧写的led.bin位于home目录下，则烧写命令为“./mkimage.sh /home/led.bin”。
+-  进入烧写工具目录，执行"./mkimage.sh <烧写文件路径>"命令,例如要
+   烧写的led.bin位于home目录下，则烧写命令为"./mkimage.sh /home/led.bin"。
 
 -  执行上一步后会列出linux下可烧写的磁盘，选择你插入的SD卡即可。这一步
    非常危险！！！一定要确定选择的是你插入的SD卡！！，如果选错很可能破坏你电脑
-   磁盘内容，造成数据损坏！！！。确定磁盘后SD卡以“sd”开头，选择“sd”后面的字符即可。例如要烧写的sd卡是“sdb”则输入“b”即可。
+   磁盘内容，造成数据损坏！！！。确定磁盘后SD卡以"sd"开头，选择"sd"后面的字符即可。例如要烧写的sd卡是"sdb"则输入"b"即可。
 
 烧写完成，首先将开发板启动方式设置为SD卡启动，将SD卡插入开发板卡槽。接通电源正常可以看到RGB灯闪烁，修改CPU时钟再次下载可以看到RGB灯闪烁频率加快。
 
diff --git a/documentation/bare_metal/ddr.rst b/documentation/bare_metal/ddr.rst
index 4c9097ac6ab7a36ed41ed958f8101022ae981b62..7be0d5c5efa1fd0cdb92c3af190bb7ed4689adbe 100644
--- a/documentation/bare_metal/ddr.rst
+++ b/documentation/bare_metal/ddr.rst
@@ -11,11 +11,17 @@ DDR测试
 
 特别说明，本书内容是以i.MX 6U系列控制器资源讲解。
 
+
+配套源码以及下载工具:
+-  路径：~/embed_linux_tutorial/base_code/bare_metal/DDR_test
+-  野火裸机下载工具download_tool（路径：~/embed_linux_tutorial/base_code/bare_metal/download-tool/download-tool.tar.bz2）。
+
+
 常用RAM存储设备简介
 ~~~~~~~~~~~
 
-RAM是“Random Access Memory”的缩写，被译为随
-机存储器。所谓“随机存取”，指的是当存储器中的消息被读取或写入时，所需要的
+RAM是"Random Access Memory"的缩写，被译为随
+机存储器。所谓"随机存取"，指的是当存储器中的消息被读取或写入时，所需要的
 时间与这段信息所在的位置无关。这个词的由来是因为早期计算机曾使用磁鼓作为存储器，磁鼓
 是顺序读写设备，而RAM可随读取其内部任意地址的数据，时间都是相同的，因此
 得名。实际上现在RAM已经专门用于指代作为计算机内存的易失性半导体存储器。
@@ -25,7 +31,7 @@ RAM是“Random Access Memory”的缩写，被译为随
 DRAM
 ^^^^
 
-动态随机存储器DRAM的存储单元以电容的电荷来表示数据，有电荷代表1，无电荷代表0，如下图所示。但时间一长，代表1的电容会放电，代表0的电容会吸收电荷，因此它需要定期刷新操作，这就是“动态(Dynamic)”一词所形容的特性。刷新操作会对电容进行检查，若电量大于满电量的1/2，则认为其代表1，并把电容充满电；若电量小于1/2，则认为其代表0，并把电容放电，藉此来保证数据的正确性。
+动态随机存储器DRAM的存储单元以电容的电荷来表示数据，有电荷代表1，无电荷代表0，如下图所示。但时间一长，代表1的电容会放电，代表0的电容会吸收电荷，因此它需要定期刷新操作，这就是"动态(Dynamic)"一词所形容的特性。刷新操作会对电容进行检查，若电量大于满电量的1/2，则认为其代表1，并把电容充满电；若电量小于1/2，则认为其代表0，并把电容放电，藉此来保证数据的正确性。
 
 
 .. image:: media/ddr002.jpeg
@@ -61,7 +67,7 @@ SDRAM在时钟的上升沿及下降沿各表示一个数据，也就是说在1
 SRAM
 ''''
 
-静态随机存储器SRAM的存储单元以锁存器来存储数据，见下图。这种电路结构不需要定时刷新充电，就能保持状态(当然，如果断电了，数据还是会丢失的)，所以这种存储器被称为“静态(Static)”RAM。
+静态随机存储器SRAM的存储单元以锁存器来存储数据，见下图。这种电路结构不需要定时刷新充电，就能保持状态(当然，如果断电了，数据还是会丢失的)，所以这种存储器被称为"静态(Static)"RAM。
 
 .. image:: media/ddr004.jpeg
    :align: center
@@ -98,7 +104,7 @@ DDR结构框图简介
 
 i.MX 6U 芯片可以通过MMDC接口外接DDR内存芯片，在程序
 中DDR作为主内存。DDR与STM32中常用的SDRAM非常相似，读者可先阅读
-野火stm32教程的SDRAM介绍会更容易理解DDR。本小节以发板使用的“MT41K256M16”DDR3L芯
+野火stm32教程的SDRAM介绍会更容易理解DDR。本小节以发板使用的"MT41K256M16"DDR3L芯
 片为例讲解DDR，其他型号DDR类似。MT41
 K256M16芯片原理框图如下图所示。
 
@@ -138,10 +144,10 @@ DDR引脚说明如下：
 控制逻辑
 
 
-标号①处的DDR内部的“控制逻辑”，它指挥着整个系统的
+标号①处的DDR内部的"控制逻辑"，它指挥着整个系统的
 运行，外部可通过CS、WE、CAS、RAS以及地址线来向控制逻
-辑输入命令，命令经过“命令器译码器”（Command Decoder）译码，并
-将控制参数保存到“模式寄存器中”（Mode Register），控制逻辑依此运行。
+辑输入命令，命令经过"命令器译码器"（Command Decoder）译码，并
+将控制参数保存到"模式寄存器中"（Mode Register），控制逻辑依此运行。
 
 地址控制
 
@@ -173,7 +179,7 @@ DDR的性能参数很多，具体可参考你使用的DDR芯片数据手册，
 DDR数据读延迟-RL、CL和AL
 
 
-读延时RL是指从“发出读信号”到数据线上输出有效数据这段时间等于CL+ AL。读延时时序图如下所示。
+读延时RL是指从"发出读信号"到数据线上输出有效数据这段时间等于CL+ AL。读延时时序图如下所示。
 
 .. image:: media/ddr007.png
    :align: center
@@ -193,14 +199,14 @@ DDR数据读延迟-RL、CL和AL
 在SDRAM中同步时钟只有CLK，无论数据和命令都只在同步时钟的上升沿进行采样。DDR的同步时钟有两个CK#和CK。两个时钟信号互补输出。命令在CK时钟的上升沿被采样，而数据在CK#与CK的交点处采样。
 
 -  标号②，RL、AL、CL。RL是之前说
-   过的“读延迟”。CL是CAS latency缩写。在SDRAM中被称为
+   过的"读延迟"。CL是CAS latency缩写。在SDRAM中被称为
    潜伏期，等于BL。在DDR3中RL = AL + CL 。AL是POSTED CAS ADDITIVE latency，的缩写，这里
    译为附加潜伏期。在MT41K256M16中AL =
    0,CL - 1, 或CL – 2。在这里取AL = 0，所以这里RL = CL，我们重点关系CL。
 
 ..
 
-   CL被称为“潜伏期”,DDR和SDRAM一样，通过电容存储的电荷(电压)来表示高、低电平，而这个电容不但要定期刷新而且驱动能力很弱，需要放大之后才能将高、低电平输出到数据线，电容的高低电平被放大输出到数据线的过程被称为“读潜伏期”，单位是同步时钟的时钟周期数。CL值是可以设置的，但不能超过系统允许的
+   CL被称为"潜伏期",DDR和SDRAM一样，通过电容存储的电荷(电压)来表示高、低电平，而这个电容不但要定期刷新而且驱动能力很弱，需要放大之后才能将高、低电平输出到数据线，电容的高低电平被放大输出到数据线的过程被称为"读潜伏期"，单位是同步时钟的时钟周期数。CL值是可以设置的，但不能超过系统允许的
    范围。CL的大小直接影响DDR的读、写速度，是DDR的一个重要参数。
 
 行地址与列地址时间间隔- tRCD
@@ -279,7 +285,7 @@ RAM_ZQPAD       ZQ signal                    DRAM_ZQPAD       No Muxing O
 \
 =============== ============================ ================ ========= =========
 
-表 57 2摘自《IMX6ULRM》（参考手册）Table 33-2。表中“RAM_DATA[31:0]”显示
+表 57 2摘自《IMX6ULRM》（参考手册）Table 33-2。表中"RAM_DATA[31:0]"显示
 数据线有32条，不清楚为什么是32条，写这部分时没有找到具体说明。查看MMDC外部
 引脚更简单的方法是在《IMX6ULRM》（参考手册）Chapter 4 External Signals
 and Pin Multiplexing章节查找，MMDC接口的部分引脚如下图所示，（这里只截取了部分引脚，完整内容请查阅《IMX6ULRM》（参考手册））
@@ -324,7 +330,7 @@ DDR测试不用我们手动编写测试程序，NXP官方提供了完备的测
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 
 
-测试软件以及配置文件可以从官网下载然后按照本教程修改配置文件也可以直接使用教程附带的测试软件以及适配本教程配套开发板的测试文件，位于“~\section5\DDR_test”目录。官网下载地址\ https://community.nxp.com/docs/DOC-102005\ 。
+测试软件以及配置文件可以从官网下载然后按照本教程修改配置文件也可以直接使用教程附带的测试软件以及适配本教程配套开发板的测试文件，位于"~\section5\DDR_test"目录。官网下载地址\ https://community.nxp.com/docs/DOC-102005\ 。
 
 打开下载地址，如下图所示。
 
@@ -370,7 +376,7 @@ DDR测试不用我们手动编写测试程序，NXP官方提供了完备的测
 配置文件说明
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 
-打开“I.MX6UL_DDR3_Script_Aid_V0.02.xlsx”文件，如下图所示。
+打开"I.MX6UL_DDR3_Script_Aid_V0.02.xlsx"文件，如下图所示。
 
 .. image:: media/ddr020.png
    :align: center
@@ -403,7 +409,7 @@ DDR测试不用我们手动编写测试程序，NXP官方提供了完备的测
 
 -  Memory type：DDR类型，这里只能通过下拉框选择，根据你使用的DDR芯片选择即可，我们选择DDR3-1600。
 
--  DRAM density (Gb)：芯片容量，单位是Gb，我们的DDR容量是512M字节 \* 8 = 4Gb。容量根据实际容量选择即可。
+-  DRAM density (Gb)：芯片容量，单位是Gb，我们的DDR容量是512M字节 * 8 = 4Gb。容量根据实际容量选择即可。
 
 -  DRAM Bus Width：数据宽度，16位。
 
@@ -460,7 +466,7 @@ DDR测试不用我们手动编写测试程序，NXP官方提供了完备的测
 
 
 新建一个.inc文件，名字自定，但最好不要用中文。这里将新建的文
-件保存在“\section5\DDR_test”路径下，并命名为RealVies.inc。使用VS code 打
+件保存在"\section5\DDR_test"路径下，并命名为RealVies.inc。使用VS code 打
 开RealVies.inc文件（也可使用其他工具打开）。复制原配置文件中的全部内容到新建的RealVies.inc文件，保存即可。后面测试DDR测试软件会使用到该配置文件
 
 测试软件的使用
@@ -524,7 +530,7 @@ DDR测试不用我们手动编写测试程序，NXP官方提供了完备的测
 
 如果校准成功软件会输出成功提示信息，如上图标号①所示。标号②处是校准后得到的6个寄存器的值，我们需要用这些寄存器的值替换校准文件中的值。
 
-例如我们使用的配置文件为“\section5\DDR_test\\RealView.inc”,使
+例如我们使用的配置文件为"\section5\DDR_test\\RealView.inc",使
 用VS code 打开后直接搜索寄存器地址，例如修改MMDC_MPWLDECTRL0寄存器，则直
 接搜索0x021b080c，找到后直接使用校准后的值0x00050003
 替换现有值即可。特别提醒，默认情况下，RealView.inc配置文件中找不到MMDC_MPWLDECTRL1和MPDGCTRL1，这两个寄存器直接忽略即可。修改完成后保存即可。
@@ -532,9 +538,9 @@ DDR测试不用我们手动编写测试程序，NXP官方提供了完备的测
 DDR性能测试
 
 
-上一步我们完成了DDR的校准，获得了校准后的寄存器数据，并将校准数据添加到了“\section5\DDR_test\RealView.inc”文件，这小节将使用校准后的数据测试DDR的性能，测试范围从400MHz到600MHz。测试完成后将会得到DDR稳定运行的最高频率。
+上一步我们完成了DDR的校准，获得了校准后的寄存器数据，并将校准数据添加到了"\section5\DDR_test\RealView.inc"文件，这小节将使用校准后的数据测试DDR的性能，测试范围从400MHz到600MHz。测试完成后将会得到DDR稳定运行的最高频率。
 
-首先打开DDR测试软件并添加修改后的配置文件“\section5\DDR_test\RealView.inc”，点击Download等待下载完成，如下图所示。
+首先打开DDR测试软件并添加修改后的配置文件"\section5\DDR_test\RealView.inc"，点击Download等待下载完成，如下图所示。
 
 
 .. image:: media/ddr029.png
@@ -542,7 +548,7 @@ DDR性能测试
    :alt: 未找到图片
 
 
-下载完成后会输出配置信息如上图标号②所示，并且标号④处的“Stress Test”按钮
+下载完成后会输出配置信息如上图标号②所示，并且标号④处的"Stress Test"按钮
 从灰色转为可用。开始测试之前要在标号③处填写测试范围，我们将Start Freq s设置
 为400M，将End Freq 设置为600M。设置完成后点击标号④处的Stress Test即可。
 
diff --git a/documentation/bare_metal/elcdif.rst b/documentation/bare_metal/elcdif.rst
index f200f0e79181940e0d5d7aa3b191d66face7a570..c894f1849264adc884982886ada24a816b2dd39e 100644
--- a/documentation/bare_metal/elcdif.rst
+++ b/documentation/bare_metal/elcdif.rst
@@ -5,6 +5,12 @@ eLCDIF—液晶显示
 
 本章参考资料：《IMX6ULRM》（参考手册）Chapter 32​: Enhanced LCD Interface (eLCDIF)
 
+
+配套源码以及下载工具:
+-  路径：~/embed_linux_tutorial/base_code/bare_metal/elcdif
+-  野火裸机下载工具download_tool（路径：~/embed_linux_tutorial/base_code/bare_metal/download-tool/download-tool.tar.bz2）。
+
+
 显示器简介
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
@@ -16,7 +22,7 @@ eLCDIF—液晶显示
 液晶显示器，简称LCD(Liquid Crystal Display)，相对于上一代CRT显
 示器(阴极射线管显示器)，LCD显示器具有功耗低、体积小、承载的信息量大及不伤眼的优点，因而它成为了现在的主流
 电子显示设备，其中包括电视、电脑显示器、手机屏幕及各种嵌入式设备的显示器。下图是液晶电视与CRT电视的外观对比，很明显液晶
-电视更薄，“时尚”是液晶电视给人的第一印象，而CRT 电视则感觉很“笨重”。
+电视更薄，"时尚"是液晶电视给人的第一印象，而CRT 电视则感觉很"笨重"。
 
 .. image:: media/LCD002.jpeg
    :align: center
@@ -50,7 +56,7 @@ LED点阵显示器不存在以上液晶显示器的问题，LED点阵彩色显
 
 
 新一代的OLED显示器与LED点阵彩色显示器的原理类似，但由于它采用的
-像素单元是“有机发光二极管”(Organic Light Emitting Diode)，所以像素密度比
+像素单元是"有机发光二极管"(Organic Light Emitting Diode)，所以像素密度比
 普通LED点阵显示器高得多，如下图所示。
 
 
@@ -84,13 +90,13 @@ OLED显示器不需要背光源、对比度高、轻薄、视角广及响应速
 
 ..
 
-   一些嵌入式设备的显示器常常以“行像素值x列像素值”表示屏幕的分辨率。如分辨率800x480表示该显示器的每一行有800个像素点，每一列有480个像素点，也可理解为有800列，480行。
+   一些嵌入式设备的显示器常常以"行像素值x列像素值"表示屏幕的分辨率。如分辨率800x480表示该显示器的每一行有800个像素点，每一列有480个像素点，也可理解为有800列，480行。
 
 -  色彩深度
 
 ..
 
-   色彩深度指显示器的每个像素点能表示多少种颜色，一般用“位”(bit)来表示。如单色屏的每个像素点能表示亮或灭两种状态(即实际上能显示2种颜色)，用1个数据位就可以表示像素点的所有状态，所以它的色彩深度为1bit，其它常见的显示屏色深为16bit、24bit。
+   色彩深度指显示器的每个像素点能表示多少种颜色，一般用"位"(bit)来表示。如单色屏的每个像素点能表示亮或灭两种状态(即实际上能显示2种颜色)，用1个数据位就可以表示像素点的所有状态，所以它的色彩深度为1bit，其它常见的显示屏色深为16bit、24bit。
 
 -  显示器尺寸
 
@@ -116,8 +122,8 @@ OLED显示器不需要背光源、对比度高、轻薄、视角广及响应速
 
 
 
-这个完整的显示屏由液晶显示面板、电容触摸面板以及PCB底板构成。图中的触摸面板带有触摸控制芯片，该芯片处理触摸信号并通过引出的信号线与外部器件通讯面板中间是透明的，它贴在液晶面板上面，一起构成屏幕的主体，触摸面板与液晶面板引出的排线连接到PCB底板上，根据实际需要，PCB底板上可能会带有“液晶控制器
-芯片”。
+这个完整的显示屏由液晶显示面板、电容触摸面板以及PCB底板构成。图中的触摸面板带有触摸控制芯片，该芯片处理触摸信号并通过引出的信号线与外部器件通讯面板中间是透明的，它贴在液晶面板上面，一起构成屏幕的主体，触摸面板与液晶面板引出的排线连接到PCB底板上，根据实际需要，PCB底板上可能会带有"液晶控制器
+芯片"。
 
 因为控制液晶面板需要比较多的资源，所以大部分低级微控制器都不能直接控制液晶面板，需要额外配套一个专用液晶控制器来处理显示过程，外部微控制器只要把它希望显示的数据直接交给液晶控制器即可。例如STM32F103\407系列的微控制器不带液晶控制器功能，所以必须要有额外液晶控制器芯片进行处理。
 
@@ -151,7 +157,7 @@ DE       数据使能信号
 
    RGB信号线各有8根，分别用于表示液晶屏一个像素点的红、绿、蓝颜色分量。使用
    红绿蓝颜色分量来表示颜色是一种通用的做法，打开Windows系统自带的画板调色工具，可看到
-   颜色的红绿蓝分量值，见下图。常见的颜色表示会在“RGB”后面附带各个颜色分量值的数据位数，如RGB565
+   颜色的红绿蓝分量值，见下图。常见的颜色表示会在"RGB"后面附带各个颜色分量值的数据位数，如RGB565
    表示红绿蓝的数据线数分别为5、6、5根，一共为16个数据位，可表示2\ :sup:`16`\ 种颜色；而这个液晶屏的
    种颜色分量的数据线都有8根，所以它支持RGB888格式，一共24位数据线，可表示的颜色为2\
    :sup:`24`\ 种。
@@ -182,8 +188,8 @@ DE       数据使能信号
 ..
 
    垂直同步信号VSYNC(Vertical Sync)用于表示液晶屏一帧像素数据
-   的传输结束，每传输完成一帧像素数据时，VSYNC会发生电平跳变。其中“帧”是图像的
-   单位，一幅图像称为一帧，在液晶屏中，一帧指一个完整屏液晶像素点。人们常常用“帧/秒”来表示液晶屏的
+   的传输结束，每传输完成一帧像素数据时，VSYNC会发生电平跳变。其中"帧"是图像的
+   单位，一幅图像称为一帧，在液晶屏中，一帧指一个完整屏液晶像素点。人们常常用"帧/秒"来表示液晶屏的
    刷新特性，即液晶屏每秒可以显示多少帧图像，
    如液晶屏以60帧/秒的速率运行时，VSYNC每秒钟电平会跳变60次。
 
@@ -230,7 +236,7 @@ VSW (vertical sync width)    表示垂直同步信号的宽度，单位为行
 HSW (horizontal sync width)  表示水平同步信号的宽度，单位为同步时钟CLK的个数
 ============================ =============================================================
 
-在这些时间参数控制的区域，数据使能信号线“DE”都为低电平，RGB数据线的信号无效，当“DE”为高电平时，RGB数据线表示的数据有效，这时传输的数据会直接影响液晶屏的显示区域。
+在这些时间参数控制的区域，数据使能信号线"DE"都为低电平，RGB数据线的信号无效，当"DE"为高电平时，RGB数据线表示的数据有效，这时传输的数据会直接影响液晶屏的显示区域。
 
 显存
 ^^
@@ -245,7 +251,7 @@ IMX6U系列芯片内部自带一个增强型液晶接口
 外设eLCDIF（Enhanced LCD Interface），配合使用DDR作为显存，可直接控制液晶面
 板，无需额外增加液晶控制器芯片。IMX6U的eLCDIF液晶控制器最高支持1366x768分辨率的屏幕；可支
 持多种颜色格式，包括RGB888、RGB5
-65、ARGB8888等(其中的“A”是指透明像素)。还可配合像
+65、ARGB8888等(其中的"A"是指透明像素)。还可配合像
 素渲染流水线PXP（Pixel Pipeline）进行复杂的图像处理，如格式转换、缩放、翻转以及图层
 混合等操作，使IMX6U有非常出色的图形显示性能。
 
@@ -323,7 +329,7 @@ eLCDIF的液晶接口有两个总线接口，System Bus总线，用于向eLCDIF
 
 其中控制总线的寄存器可以配置显存地址、输入像素数据的格式、输出的数据信号线宽度、各个控制信号的有效极性以及控制时序中的VSW、VBP等参数，还能配置使用DMA传输。
 
-使用寄存器初始化好eLCDIF的后，它会从“LFIFO”和“TXFIFO”中获取数据进行转换处理（格式转换、移位等操作）并传输出去。当FIFO中的数据量低于一定程度时，它会向系统总线（System
+使用寄存器初始化好eLCDIF的后，它会从"LFIFO"和"TXFIFO"中获取数据进行转换处理（格式转换、移位等操作）并传输出去。当FIFO中的数据量低于一定程度时，它会向系统总线（System
 Bus）发起请求，系统总线会把显存地址的数据搬运至FIFO中。FIFO还可以配置阈值，低于该阈值时系统总线会提高获取数据的优先级。
 
 eLCDIF正常运行后，数据从显存到液晶屏全程不需要内核的干预，程序控制时我们只要把像素数据写入到显存即可。
@@ -371,11 +377,11 @@ DISPLAY CLOCK（pix_clk）
 eLCDIF—液晶显示实验
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
-本小节讲解如何使用eLCDIF外设控制型号为“STD800480”的5寸液晶
+本小节讲解如何使用eLCDIF外设控制型号为"STD800480"的5寸液晶
 屏，见图 58‑13，该液晶屏的分辨率为800x480，支持RGB888格式，不过由于RT1052部分液晶信
 号数据线与以太网的共用，所以在硬件上本开发板采用了RGB565的连接方式控制液晶屏。
 
-学习本小节内容时，请打开配套的“eLCDIF—液晶显示英文”工程配合阅读。
+学习本小节内容时，请打开配套的"eLCDIF—液晶显示英文"工程配合阅读。
 
 本教程同样适用于配套的7寸屏，它的分辨率和时序参数与5寸屏相同，驱动程序完全一样。
 
@@ -446,12 +452,12 @@ eLCDIF—液晶显示实验
 添加源文件并修改makefile
 ''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''
 
-首先复制“~\section5\\
-uart”代码并更名为“~\section5\elcdf”。在“~\section5\elcdf\device”文件夹下添加elcdf.c文件，在“~\section5\elcdf\include”文件夹下添加elcdf.h文件。elcdf相关代码将会放到elcdf.c和elcdf.h文件内。
+首先复制"~\section5\\
+uart"代码并更名为"~\section5\elcdf"。在"~\section5\elcdf\device"文件夹下添加elcdf.c文件，在"~\section5\elcdf\include"文件夹下添加elcdf.h文件。elcdf相关代码将会放到elcdf.c和elcdf.h文件内。
 
 添加了源文件，所以要修改makefile ，将源文件编译进
-程序。打开“~\section5\\ elcdf \\device”目录下的makefile文件，在最终
-目标依赖项中添加“elcdf.o”如下所示。
+程序。打开"~\section5\\ elcdf \\device"目录下的makefile文件，在最终
+目标依赖项中添加"elcdf.o"如下所示。
 
 
 
@@ -641,12 +647,12 @@ CCM_ANALOG_PLL_VIDEO_DENOM [POST_DIV_SELECT]寄存器值 CCM_ANALOG_MISC2[VIDEO_
 出前的最后一次分频的分频系数。方便书写这里记为
 
 PLL5的输出频率计算公
-式为 PLL5 = OSC24M \* (DIV_SELECT + (denominator / numerator)) / postDivider。
+式为 PLL5 = OSC24M * (DIV_SELECT + (denominator / numerator)) / postDivider。
 
 第一部分代码从上到下依次
 设置numerator = 0、numerator = 0、CCM_ANALOG_PLL_VIDEO_DENOM [POST_DIV_SELECT] = 2、
 CCM_ANALOG_MISC2[VIDEO_DIV] = 3、DIV_SELECT = 0x1F
-，最终得到的PLL5输出频率为PLL5 = 24 \* (0x1F + 0) / 8 = 93MHz。
+，最终得到的PLL5输出频率为PLL5 = 24 * (0x1F + 0) / 8 = 93MHz。
 
 -  第二部分，设置从PLL5输出到elcdf根时钟所经过的时钟选择寄存器和时钟分频寄存器，时钟选择与时钟分频如下图所示。
 
@@ -798,11 +804,11 @@ elcdf初始化代码大致分为了五部分，但是各部分之间并没有明
 
 -  第三部分，第三部分与第四部分都是设置与显示屏相关的配置参数。代码第34和35行设置显示
    屏的分辨率。修改时最高修改分辨率对应的宏定义，以为其他地方还会用到分辨率。代码第38到43行使能RGB模
-   式并设置VSYNC信号周期的单位（行同步信号数或pix_clk时钟周期数）以及VSYNC信号脉宽的单位（同上），RGB接口应当设置单位为“行同步信号周期数”。代
+   式并设置VSYNC信号周期的单位（行同步信号数或pix_clk时钟周期数）以及VSYNC信号脉宽的单位（同上），RGB接口应当设置单位为"行同步信号周期数"。代
    码第45到54用于设置VSYNC有效电平以及数据采集的边缘。实际应用中我们很少修改这部分内容。
 
 -  第四部分，设置显示屏相关配置参数。代码第59行，设置传输一帧
-   所用的的时间单位是传输“一行”像素所用的时间，或者说是行同步信号周期。代码第62行，设置VSYNC信号宽度，代码第64行，设
+   所用的的时间单位是传输"一行"像素所用的时间，或者说是行同步信号周期。代码第62行，设置VSYNC信号宽度，代码第64行，设
    置HSYNC（行同步信号周期），单位为同步时钟CLK的个数。代码第66和67行分别设置行同步信号之后等待的时间（单
    位为同步时钟CLK的个数） 、列同步信号之后等待时间（单位为行同步信号周期）。如图 58‑8所示。
 
@@ -909,19 +915,19 @@ elcdf初始化代码大致分为了五部分，但是各部分之间并没有明
 下载验证
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 
-程序编写完成后，在“/section5/ elcdif” 文件夹下执行make命令，makefile工具便会自
+程序编写完成后，在“elcdif” 文件夹下执行make命令，makefile工具便会自
 动完成程序的编译、链接、格式转换等工作。正常情况下我们可以在当前目录看到生成的一些中间文件以及我们期待的.bin文件。
 
-在46.2.5 烧写到SD卡章节我们详细讲解了如何将二进制文件烧写到SD卡（烧写工具自动实现为二进制文件添加头）。这里再次说明下载步骤。
+在编译下载官方SDK程序到开发板章节我们详细讲解了如何将二进制文件烧写到SD卡（烧写工具自动实现为二进制文件添加头）。这里再次说明下载步骤。
 
 -  将一张空SD卡（烧写一定会破坏SD卡中原有数据！！！烧写前请保存好SD卡中的数据），接入电脑后在虚拟机的右下角状态栏找到对应的SD卡。将其链接到虚拟机。
 
--  进入烧写工具目录，执行“./mkimage.sh <烧写文件路径>”命令,例如要烧写
-   的led.bin位于home目录下，则烧写命令为“./mkimage.sh /home/led.bin”。
+-  进入烧写工具目录，执行"./mkimage.sh <烧写文件路径>"命令,例如要烧写
+   的led.bin位于home目录下，则烧写命令为"./mkimage.sh /home/led.bin"。
 
 -  执行上一步后会列出linux下可烧写的磁盘，选择你
    插入的SD卡即可。这一步非常危险！！！一定要确定选择的是你插入的SD卡！！，如果选错很可能破
-   坏你电脑磁盘内容，造成数据损坏！！！。确定磁盘后SD卡以“sd”开头，选择“sd”后面的字符即可。例如要烧写的sd卡是“sdb”则输入“b”即可。
+   坏你电脑磁盘内容，造成数据损坏！！！。确定磁盘后SD卡以"sd"开头，选择"sd"后面的字符即可。例如要烧写的sd卡是"sdb"则输入"b"即可。
 
 烧写完成，首先将开发板启动方式设置为SD卡启动，将SD卡插入开发板卡槽。上电后显示屏右下角会显示一个蓝色方块，并不断向左上角移动。如果显示不正常显示请断电后重新插拔显示屏连接线，确保接触良好。
 
diff --git a/documentation/bare_metal/gcc_led.rst b/documentation/bare_metal/gcc_led.rst
index 2b1449efff1e1acea96f8a175fbdb687b420ffe7..586222a62f363b392a64bfc640f4db51b3384d5e 100644
--- a/documentation/bare_metal/gcc_led.rst
+++ b/documentation/bare_metal/gcc_led.rst
@@ -3,9 +3,6 @@
 LED灯进阶——C语言实现
 ------------------------------------------------------------------------------
 
-本章节内容处于开发笔记状态，还待整理至最终版的教程。
-
-本章节内容处于开发笔记状态，还待整理至最终版的教程。
 
 在第48章 汇编点亮LED灯章节我们在led.S文件里使用纯汇编语
 言操作i.MX 6U的寄存器点亮了LED灯。主要存在两个问题，第一，汇编语言编
@@ -17,6 +14,12 @@ LED灯进阶——C语言实现
 
 -  使用makefile工具和连接脚本管理工程。
 
+配套源码以及下载工具:
+-  路径：~/embed_linux_tutorial/base_code/bare_metal/led_c
+-  野火裸机下载工具download_tool（路径：~/embed_linux_tutorial/base_code/bare_metal/download-tool/download-tool.tar.bz2）。
+
+
+
 软件设计
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
@@ -31,13 +34,13 @@ LED灯进阶——C语言实现
 点亮LED——汇编部分
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 
-LED灯源码程序包含两部分内容，第一部分在汇编文件中设置“栈地址”并执行跳转命令跳转到main函数执行C代码。第二部分在C 文件中点亮led灯。
+LED灯源码程序包含两部分内容，第一部分在汇编文件中设置"栈地址"并执行跳转命令跳转到main函数执行C代码。第二部分在C 文件中点亮led灯。
 
-注：根据之前讲解本教程将第四部分（裸机驱动）相关代码放在了“/home/section4”文件夹并且每一的程序有各自独立的文件夹。如果你存放代码路径不同，转化到自己对应的路径即可。
+注：根据之前讲解本教程将第四部分（裸机驱动）相关代码放在了"/home/section4"文件夹并且每一的程序有各自独立的文件夹。如果你存放代码路径不同，转化到自己对应的路径即可。
 
-首先在“/home/section4”文件夹下创建目录led_c文件，用于存放本章代码。将“汇编点亮led灯的源码led.S复制到”led_c目录下，并更名为start.S。
+首先在"/home/section4"文件夹下创建目录led_c文件，用于存放本章代码。将"汇编点亮led灯的源码led.S复制到"led_c目录下，并更名为start.S。
 
-在start.S的基础上增加“栈”设置和执行跳转指令，如下所示。
+在start.S的基础上增加"栈"设置和执行跳转指令，如下所示。
 
 
 .. code-block:: asm
@@ -73,18 +76,18 @@ LED灯源码程序包含两部分内容，第一部分在汇编文件中设置
          b loop
 
 
-代码总共分为三部分，第一、三部分与“汇编点亮led灯”完全相同，下面重点说明第二部分代码。
+代码总共分为三部分，第一、三部分与"汇编点亮led灯"完全相同，下面重点说明第二部分代码。
 
 -  ldr sp, =0x84000000指令，用于设置栈指针。野火i.MX 6ULL开发
    板标配528M的DDR内存，裸机开发用不了这么多。程序中我们将栈地址设
    置到DDR的64M地址处。这个值也可以根据需要自行定义。
 
--  b main 指令，只用跳转指令跳转到main函数中执行。指令“b”是“无返回”的跳转指令正常情况下，不会执行第三部分代码。
+-  b main 指令，只用跳转指令跳转到main函数中执行。指令"b"是"无返回"的跳转指令正常情况下，不会执行第三部分代码。
 
 点亮LED灯——C语言部分
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 
-C源码非常简单，只需把“汇编点亮led灯”例程中有关GPIO寄存器操作换成C语言即可，源码如下所示。
+C源码非常简单，只需把"汇编点亮led灯"例程中有关GPIO寄存器操作换成C语言即可，源码如下所示。
 
 .. code-block:: c
    :caption: 语言实现点亮LED灯
@@ -116,10 +119,10 @@ C源码非常简单，只需把“汇编点亮led灯”例程中有关GPIO寄存
 结合代码，各部分讲解如下：
 
 -  第一部分，定义GPIO相关寄存器。这部分内容与
-   “汇编点亮LED灯”中定义的寄存器相同，只不过这里使用（volatile unsigned long*）将地址强制转化为指针。
+   "汇编点亮LED灯"中定义的寄存器相同，只不过这里使用（volatile unsigned long*）将地址强制转化为指针。
 
 -  第二部分，向寄存器中写入值。在第一部分代码中我们将寄存器地址强制转换为指针，这里
-   使用使用“*”号再次“寻址”。“*(CCM_CCGR1) = 0xFFFFFFFF;”代码表
+   使用使用"*"号再次"寻址"。"*(CCM_CCGR1) = 0xFFFFFFFF;"代码表
    示将0xFFFFFFFF写入指针CCM_CCGR1所指定的地址中。其他寄存器类似。
 
 编写链接脚本
@@ -130,15 +133,15 @@ C源码非常简单，只需把“汇编点亮led灯”例程中有关GPIO寄存
 
 我们知道写好的代码（无论是汇编还是C语言）都要经过编译、汇编、链接等步骤生成二进
 制文件或者可供下载的文件。在编译阶编译器会对每个源文件进行语法检查并生成对应的汇编语言，汇编是
-将汇编文件转化为机器码。在上一章我们使用“arm-none-eabi-gcc -g -c led.S -o
-led.o”命令完成了源码的编译、汇编工作，生成了.o文件。编译和汇编是针对单个源文件，也就编译完成后一个源文件（.c，.S或.s）对应一个.o文件。程序链接阶段就会将这些.o链接成一个文件。
+将汇编文件转化为机器码。在上一章我们使用"arm-none-eabi-gcc -g -c led.S -o
+led.o"命令完成了源码的编译、汇编工作，生成了.o文件。编译和汇编是针对单个源文件，也就编译完成后一个源文件（.c，.S或.s）对应一个.o文件。程序链接阶段就会将这些.o链接成一个文件。
 
 链接脚本的作用就是告诉编译器怎么链接这些文件，比如那个文件放在最前面，程序的代码段、数据段、bss段分别放在什么位置等等。
 
 链接脚本介绍
 
 
-链接器脚本主要由SECTIONS、段、“.”运算符以及变量组成，一个简单的链接脚本如下所示。我们将基于它讲解连接脚本的基本用法。
+链接器脚本主要由SECTIONS、段、"."运算符以及变量组成，一个简单的链接脚本如下所示。我们将基于它讲解连接脚本的基本用法。
 
 
 
@@ -173,24 +176,24 @@ led.o”命令完成了源码的编译、汇编工作，生成了.o文件。编
 结合代码各部分讲解如下：
 
 -  标号（1）,ENTRY(_start) 用于指定程序的入口，ENTRY( )是设置入
-   口地址的命令，“_start”是程序的入口，本章的led程序的入口地址位于start.S的“_start”标号处。
+   口地址的命令，"_start"是程序的入口，本章的led程序的入口地址位于start.S的"_start"标号处。
 
 -  标号（2），定义SECTIONS。SECTIONS可以理解为是一块区域，我们在这块区域排布我们的代码，链接时链接器就会按照这里的指示链接我们的代码。
 
--  标号（3），“.”运算符代表当前
-   位置。我们在SECTION的最开始使用“.= 0x80000000”就是将链接起始地址设置为0x80000000。
+-  标号（3），"."运算符代表当前
+   位置。我们在SECTION的最开始使用".= 0x80000000"就是将链接起始地址设置为0x80000000。
 
 -  标号（4），设置字节对齐。这里同样
-   用到了“.”运算符，它表示从当前位置开始执行四字节对齐。假设当前
+   用到了"."运算符，它表示从当前位置开始执行四字节对齐。假设当前
    位置为0x80000001，执行该命令后当前地址将会空出三个字节转到0x80000004地址处。
 
--  标号（5），定义代码段。“.text :”用于定义代码段，固定的语法要求，我们按照要求写即可。在“{}”中指定那些内容放在代码段。
+-  标号（5），定义代码段。".text :"用于定义代码段，固定的语法要求，我们按照要求写即可。在"{}"中指定那些内容放在代码段。
 
 -  标号（6），将start.o中的代码放到代码段的最前面。start.S是启动代码应当
    首先被执行，所以通常情况下要把它放到代码段的最前面，其他源文件的代码按照系统默认的排放顺
-   序即可，如标号（7）所示，通配符“*”在这里表示其他剩余所有的.o文件。
+   序即可，如标号（7）所示，通配符"*"在这里表示其他剩余所有的.o文件。
 
--  标号（8），设置数据段。同设置代码段类似，首先设置字节对齐，然后定义代码段。在代码段里使用“*”通配符，将所有源文件中的代码添加到这个代码段中。
+-  标号（8），设置数据段。同设置代码段类似，首先设置字节对齐，然后定义代码段。在代码段里使用"*"通配符，将所有源文件中的代码添加到这个代码段中。
 
 -  标号（9），设置BSS段。设置方法与设置数据段完全相同
 
@@ -199,7 +202,7 @@ led.o”命令完成了源码的编译、汇编工作，生成了.o文件。编
 编写makefile文件
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 
-在“在汇编点亮LED灯”章节，我们程序编写完成后需要依次输入编译、链接、格式转换
+在"在汇编点亮LED灯"章节，我们程序编写完成后需要依次输入编译、链接、格式转换
 命令才能最终生成二进制文件。这种编译方式效率低、容易出错。本 小节讲解裸机下的makefile的编写。
 
 点亮LED灯程序的makefile比较简单，仅实现了最基本的功能，后面使用到复杂功能是我们再进行修改，源码如下所示。
@@ -227,17 +230,17 @@ makefile文件很简短，因为是第一个裸机makefile，下面将详细分
 
 -  标号（1），添加最终目标以及依赖文件。
 
--  标号（2），添加链接命令。参数“_Tled.lds”表示使用led.lds链接脚本链接程序。参数“$^”代表所有的依赖文件。“-o”指定输出文件名。
+-  标号（2），添加链接命令。参数"_Tled.lds"表示使用led.lds链接脚本链接程序。参数"$^"代表所有的依赖文件。"-o"指定输出文件名。
 
--  标号（3），添加格式转换命令。与“汇编点亮LED灯”相同，“-O binary”指定输
-   出二进制文件。“-S”选项，不从源文件中复制重定位信息和符号信息。“-g”选项，不从源文件中复制可调试信息。
+-  标号（3），添加格式转换命令。与"汇编点亮LED灯"相同，"-O binary"指定输
+   出二进制文件。"-S"选项，不从源文件中复制重定位信息和符号信息。"-g"选项，不从源文件中复制可调试信息。
 
--  标号（4），添加汇编文件编译命令。与“汇编点亮LED灯”编译命令大致相同，这里使用“$^”替代要编译的源文件。
+-  标号（4），添加汇编文件编译命令。与"汇编点亮LED灯"编译命令大致相同，这里使用"$^"替代要编译的源文件。
 
 -  标号（5），添加编译C文件的命令。编译C文件与编译汇编文件命令相同这里不再介绍。
 
--  标号（6），添加清理命令。“.PHONY”定义了伪目标“clean”。伪目标一般没
-   有依赖，并且“clean”伪目标一般放在Makefile文件的末尾。“clean”为目标用于删除make生成的文件。
+-  标号（6），添加清理命令。".PHONY"定义了伪目标"clean"。伪目标一般没
+   有依赖，并且"clean"伪目标一般放在Makefile文件的末尾。"clean"为目标用于删除make生成的文件。
 
 编译下载
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
@@ -246,15 +249,15 @@ makefile编写完成后程序的编译就变得非常简单，我们只需要在
 执行make命令，makefile工具便会自动完成程序的编译、链接、格式转换等工作。正常情况
 下我们可以在当前目录看到生成的一些中间文件以及我们期待的.bin文件。
 
-在46.2.5 烧写到SD卡章节我们详细讲解了如何将二进制文件烧写到SD卡（烧写工具自动实现为二进制文件添加头）。这里再次说明下载步骤。
+在编译下载官方SDK程序到开发板章节我们详细讲解了如何将二进制文件烧写到SD卡（烧写工具自动实现为二进制文件添加头）。这里再次说明下载步骤。
 
 -  将一张空SD卡（烧写一定会破坏SD卡中原有数据！！！烧写前请保存好SD卡中的数据），接入电脑后在虚拟机的右下角状态栏找到对应的SD卡。将其链接到虚拟机。
 
--  进入烧写工具目录，执行“./mkimage.sh <烧写文件路径>”命令,例如要
-   烧写的led.bin位于home目录下，则烧写命令为“./mkimage.sh /home/led.bin”。
+-  进入烧写工具目录，执行"./mkimage.sh <烧写文件路径>"命令,例如要
+   烧写的led.bin位于home目录下，则烧写命令为"./mkimage.sh /home/led.bin"。
 
 -  执行上一步后会列出linux下可烧写的磁盘，选择你插入的SD卡即可。这一步
-   非常危险！！！一定要确定选择的是你插入的SD卡！！，如果选错很可能破坏你电脑磁盘内容，造成数据损坏！！！。确定磁盘后SD卡以“sd”开头，选择“sd”后面的字符即可。例如要烧写的sd卡是“sdb”则输入“b”即可。
+   非常危险！！！一定要确定选择的是你插入的SD卡！！，如果选错很可能破坏你电脑磁盘内容，造成数据损坏！！！。确定磁盘后SD卡以"sd"开头，选择"sd"后面的字符即可。例如要烧写的sd卡是"sdb"则输入"b"即可。
 
 实验现象
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
diff --git a/documentation/bare_metal/gpio_key.rst b/documentation/bare_metal/gpio_key.rst
index 1f7ba3ad7835612916556efe259999176ee31dde..c4f917d7eabda069619510b416b9d4a9d722d196 100644
--- a/documentation/bare_metal/gpio_key.rst
+++ b/documentation/bare_metal/gpio_key.rst
@@ -3,12 +3,16 @@
 GPIO输入—按键查询检测
 -----------------------------------------------------------------
 
-本章节内容处于开发笔记状态，还待整理至最终版的教程。
 
-本章节内容处于开发笔记状态，还待整理至最终版的教程。
 
 按键检测使用到GPIO外设的基本输入功能，本章中不再赘述GPIO外设的概念。
 
+配套源码以及下载工具:
+-  路径：~/embed_linux_tutorial/base_code/bare_metal/button
+-  野火裸机下载工具download_tool（路径：~/embed_linux_tutorial/base_code/bare_metal/download-tool/download-tool.tar.bz2）。
+
+
+
 硬件设计
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
@@ -99,7 +103,7 @@ MODE按键    SW4      BOOT_MODE[0]：           BOOT_MODE[0]：高电平 选择
 复制RGB灯程序
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 
-本程序在RGB等程序基础上修改，复制“/section4/led_rgb_c”灯程序到“/section4/button”目录下，如下图所示。
+本程序在RGB等程序基础上修改，复制"/section4/led_rgb_c"灯程序到"/section4/button"目录下，如下图所示。
 
 .. image:: media/gpioke008.png
    :align: center
@@ -107,12 +111,12 @@ MODE按键    SW4      BOOT_MODE[0]：           BOOT_MODE[0]：高电平 选择
 
 
 
-将文件“led.c”和“led.lds”分别修改为“button.c”和“button.lds”，添加按键代码我们只需要修改“makefile”文件以及“button.c”文件。
+将文件"led.c"和"led.lds"分别修改为"button.c"和"button.lds"，添加按键代码我们只需要修改"makefile"文件以及"button.c"文件。
 
 修改makefile
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 
-makefile文件主要是修改文件名，将“led”修改为button，其他内容并没有修改，修改过的makefile 如下所示。
+makefile文件主要是修改文件名，将"led"修改为button，其他内容并没有修改，修改过的makefile 如下所示。
 
 
 .. code-block:: c
@@ -129,7 +133,7 @@ makefile文件主要是修改文件名，将“led”修改为button，其他内
    
     .PHONY: clean
     clean:
-    rm \*.o \*.elf \*.bin
+    rm *.o *.elf *.bin
 
 
 为简化难度暂时这样修改，后面章节将会介绍更简单易用的修改方式。
@@ -224,18 +228,18 @@ makefile文件主要是修改文件名，将“led”修改为button，其他内
 下载验证
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
-程序编写完成后，在“/section4/button” 文件夹下执行make命令，makefile工具便会自动完成
+程序编写完成后，在“button” 文件夹下执行make命令，makefile工具便会自动完成
 程序的编译、链接、格式转换等工作。正常情况下我们可以在当前目录看到生成的一些中间文件以及我们期待的.bin文件。
 
-在46.2.5 烧写到SD卡章节我们详细讲解了如何将二进制文件烧写到SD卡（烧写工具自动实现为二进制文件添加头）。这里再次说明下载步骤。
+在编译下载官方SDK程序到开发板章节我们详细讲解了如何将二进制文件烧写到SD卡（烧写工具自动实现为二进制文件添加头）。这里再次说明下载步骤。
 
 -  将一张空SD卡（烧写一定会破坏SD卡中原有数据！！！烧写前请保存好SD卡中的数据），接入电脑后在虚拟机的右下角状态栏找到对应的SD卡。将其链接到虚拟机。
 
--  进入烧写工具目录，执行“./mkimage.sh <烧写文件路径>”命令,例如要
-   烧写的led.bin位于home目录下，则烧写命令为“./mkimage.sh /home/led.bin”。
+-  进入烧写工具目录，执行"./mkimage.sh <烧写文件路径>"命令,例如要
+   烧写的led.bin位于home目录下，则烧写命令为"./mkimage.sh /home/led.bin"。
 
 -  执行上一步后会列出linux下可烧写的磁盘，选择你插入的SD卡即可。这一步非常危险！！！一定要确定选择的是
-   你插入的SD卡！！，如果选错很可能破坏你电脑磁盘内容，造成数据损坏！！！。确定磁盘后SD卡以“sd”开头，选择“sd”后面的字符即可。例如要烧写的sd卡是“sdb”则输入“b”即可。
+   你插入的SD卡！！，如果选错很可能破坏你电脑磁盘内容，造成数据损坏！！！。确定磁盘后SD卡以"sd"开头，选择"sd"后面的字符即可。例如要烧写的sd卡是"sdb"则输入"b"即可。
 
 .. |gpioke002| image:: media/gpioke002.jpeg
    :width: 3.30764in
diff --git a/documentation/bare_metal/iar_led.rst b/documentation/bare_metal/iar_led.rst
index cca62a3414b6253e62adb3b3cdf5f83348caad7b..24a02758e28c479a8b2ef6f13ef85e9e272c2b03 100644
--- a/documentation/bare_metal/iar_led.rst
+++ b/documentation/bare_metal/iar_led.rst
@@ -3,12 +3,10 @@
 点亮LED灯
 ------------------------------------------------------------------------------------------------------------------
 
-本章节内容处于开发笔记状态，还待整理至最终版的教程。
 
-本章节内容处于开发笔记状态，还待整理至最终版的教程。
 
 通过上一节我们知道i.MX6ULL 拥有官方写好的windows以及linux下的SDK包，并
-且在SDK的“SDK_2.2_MCIM6ULL_EBF6ULL\boards\evkmcimx6ull\driver_examples”目录下存在
+且在SDK的"SDK_2.2_MCIM6ULL_EBF6ULL\boards\evkmcimx6ull\driver_examples"目录下存在
 大量的基于IAR集成开发环境的官方例程。看到这里是不是很兴奋
 ？很遗憾的告诉你，除本章以外的其他裸机章节将不会使用IAR集成开发环境，而是
 采用linux下的arm gcc 工具开发。为什么不使用IAR开发裸机？将会在下一章详细介绍。这里首先介绍为什么带领大家用IAR点灯。
@@ -17,7 +15,7 @@
    驱动开发的重要参考资料我们必须对它有一定的了解，需要能够快速找到我们需要的内容。
 
 -  IAR集成开发环境借助调试工具（jlink）能够实现强大的调试功
-   能，在开发阶段它能够帮助我们快速“调通”硬件，程序在IAR上调通后再移植到Linux 的arm gcc不会太难。
+   能，在开发阶段它能够帮助我们快速"调通"硬件，程序在IAR上调通后再移植到Linux 的arm gcc不会太难。
 
 本章目标：
 
@@ -25,6 +23,12 @@
 
 -  能够熟练查找外设对应的GPIO引脚。
 
+配套源码:
+-  路径：~/embed_linux_tutorial/base_code/bare_metal/IAR_project
+-  野火裸机下载工具download_tool（路径：~/embed_linux_tutorial/base_code/bare_metal/download-tool/download-tool.tar.bz2）。
+
+
+
 GPIO简介
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
@@ -191,7 +195,7 @@ IOMUXC_SW_MUX_CTL_PAD_XXXX引脚模式寄存器
 可以看到，该寄存器主要有两个配置域，分别是SION和MUX_MODE，其中SION用于设置引脚在输出模式下同时开启输入通道。重点是MUX_MODE的配置，它使用4个寄存器位表示可选的ALT0~ALT7这8个模式，如ALT2模式就是用于usb外设的USB_OTG1_PWR信号；若配置为ALT5则引脚会
 用作普通的GPIO功能，用于输出高、低电平。 这也是本章所需要的。
 
-IOMUXC_SW\_ PAD_CTL_PAD_XXXX引脚属性寄存器
+IOMUXC_SW_PAD_CTL_PAD_XXXX引脚属性寄存器
 
 
 类似地，以GPIO1_IO04引脚中PAD寄存器在参考手册中的描述见下图。
@@ -262,7 +266,7 @@ GPIO功能框中的第5项表示另一个引脚PAD2，它与PAD1有一根信号
 使用IAR点亮LED灯实验
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
-本教程假设你有一定的单片机基础，所以不再介绍IAR工程的建立。IAR工程名为“新建工程-固件库版本”，工程结构如下图所示。
+本教程假设你有一定的单片机基础，所以不再介绍IAR工程的建立。IAR工程名为"新建工程-固件库版本"，工程结构如下图所示。
 
 .. image:: media/iarled010.png
    :align: center
@@ -330,8 +334,8 @@ GPIO功能框中的第5项表示另一个引脚PAD2，它与PAD1有一根信号
 
 从中可以看出CSI_HSYNC对应的GPIO引脚为GPIO4_IO20。
 
-第二种，在官方写好的文件中查找，我们打开“fsl_iomuxc.h”文件（可以打开IAR工程找到该文件也可以在工程目录下直接搜索）。直
-接在“fsl_iomuxc.h”文件中搜索图 49‑12所搜得到的LED灯对
+第二种，在官方写好的文件中查找，我们打开"fsl_iomuxc.h"文件（可以打开IAR工程找到该文件也可以在工程目录下直接搜索）。直
+接在"fsl_iomuxc.h"文件中搜索图 49‑12所搜得到的LED灯对
 应的引脚CSI_HSYNC（或CSI_VSYNC）得到如下图所示的结果（以CSI_HSYNC为例）。
 
 .. image:: media/iarled015.png
@@ -340,7 +344,7 @@ GPIO功能框中的第5项表示另一个引脚PAD2，它与PAD1有一根信号
 
 
 
-从图中不难看出这就是我们要找的引脚，每个宏定义分“三段”，以宏IOMUXC_CSI_HSYNC_I2C2_SCL为例，IOMUXC代表这是一个引脚复用宏定义，CSI_HSYNC代表原理图上实际的芯片引脚名，I2C2_SCL代表引脚的复用功能。一个引脚有多个复用功能，本章要把CSI_HSYNC用作GP
+从图中不难看出这就是我们要找的引脚，每个宏定义分"三段"，以宏IOMUXC_CSI_HSYNC_I2C2_SCL为例，IOMUXC代表这是一个引脚复用宏定义，CSI_HSYNC代表原理图上实际的芯片引脚名，I2C2_SCL代表引脚的复用功能。一个引脚有多个复用功能，本章要把CSI_HSYNC用作GP
 IO控制LED灯，所以本实验要选择IOMUXC_CSI_HSYNC_GPIO4_IO20宏定义引脚CSI_HSYNC复用为GPIO4_IO20，具体怎么使用程序中再详细介绍。
 
 经查阅，我们把以上连接LED灯的各个i.MX 6U芯片引脚总结出如下表所示，它展示了各个LED灯的连接信息及相应引脚的GPIO端口和引脚号。
@@ -379,7 +383,7 @@ LED相关代码存储在bap_led.c/h，引脚复用功能定义在fsl_iomuxc.h文
 LED灯引脚宏定义
 ''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''
 
-在编写应用程序的过程中，要考虑更改硬件环境的情况，例如LED灯的控制引脚与当前的不一样，我们希望程序只需要做最小的修改即可在新的环境正常运行。这个时候一般把硬件相关的部分使用宏来封装，若更改了硬件环境，只修改这些硬件相关的宏即可，这些定义一般存储在头文件，即本例子中的“bsp_led.h”文件中，具
+在编写应用程序的过程中，要考虑更改硬件环境的情况，例如LED灯的控制引脚与当前的不一样，我们希望程序只需要做最小的修改即可在新的环境正常运行。这个时候一般把硬件相关的部分使用宏来封装，若更改了硬件环境，只修改这些硬件相关的宏即可，这些定义一般存储在头文件，即本例子中的"bsp_led.h"文件中，具
 体见代码清单 49‑1。
 
 
@@ -748,14 +752,14 @@ main文件
 
    在board.h文件中还包含了NXP固件库最
    基础的fsl_common.h文件，所以有了这个文件我们就不
-   用在main文件中再增加一个“#include “fsl_common.h””语句了。
+   用在main文件中再增加一个"#include "fsl_common.h""语句了。
 
 -  bsp_led.h文件，包含了我们控制LED灯相关的函数及宏。
 
 简单的延时函数
 
 
-代码的第2部分定义了一个delay函数用于简单的延时，它的实现非常简单，就是在一个for循环内调用CPU的空操作指令，调用形式是“__asm(“NOP”)”。对于这样的函数我们很难直接根据它的输入参数算出具体的延时时间，此处我们只是简单地凭感觉使用，也不要求它有精确的延时，在后面需要精确延时的地方，
+代码的第2部分定义了一个delay函数用于简单的延时，它的实现非常简单，就是在一个for循环内调用CPU的空操作指令，调用形式是"__asm("NOP")"。对于这样的函数我们很难直接根据它的输入参数算出具体的延时时间，此处我们只是简单地凭感觉使用，也不要求它有精确的延时，在后面需要精确延时的地方，
 会使用其它形式的延时操作代替。
 
 另外，由于这个函数会被编译器不同程度地优化，所以在我们不同版本的工程中其延时时间也是不一样的。例如按照我们的工程模板配置flexspi_nor_release版本的程序优化等级为3级，其余的均为1级，所以在使用同样的输入参数时，flexspi_nor_release版本的这个delay函数延时时间明
diff --git a/documentation/bare_metal/interrupt.rst b/documentation/bare_metal/interrupt.rst
index 85bed3fb80fb570c49b291a97b4e87dcefaa5d2d..cabfb079eb8bb3cf45e584df92e120b5e1168f0d 100644
--- a/documentation/bare_metal/interrupt.rst
+++ b/documentation/bare_metal/interrupt.rst
@@ -13,6 +13,12 @@
 
 -  编写i.MX 6U的中断向量表
 
+配套源码以及下载工具:
+-  路径：~/embed_linux_tutorial/base_code/bare_metal/interrupt_init
+-  野火裸机下载工具download_tool（路径：~/embed_linux_tutorial/base_code/bare_metal/download-tool/download-tool.tar.bz2）。
+
+
+
 GIC简介
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
@@ -62,12 +68,12 @@ interface）。下面重点讲解着两部分。
 
 (4) 指定中断发生时将中断请求发送到那些CPU（i.MX 6U是单核）。
 
-(5) 设置每个“外部中断”的触发方式（边缘触发或者电平触发）。
+(5) 设置每个"外部中断"的触发方式（边缘触发或者电平触发）。
 
 分发器相关寄存器介绍
 ''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''
 
-上一小节提到GIC分发器提供了一些编程接口，“编程接口”可以认为是寄存器，这里将简单介绍
+上一小节提到GIC分发器提供了一些编程接口，"编程接口"可以认为是寄存器，这里将简单介绍
 这些寄存器，因为我们程序中很少会去修改它。更详细的内容
 请参考《ARM® Generic Interrupt Controller》4.3 Distributor register descriptions
 。GIC分发器映射表如下所示。
@@ -97,9 +103,9 @@ interface）。下面重点讲解着两部分。
 =========== ================ ==== ========== ========================
 
 首先我们简单介绍上表，在表中只给出了寄存器相对于GIC分发器基地址的偏
-移地址，GIC基地址保存在另外的寄存器中，使用到是我们将详细介绍。“默认值”选项中有“待
-定”手册原文是“IMPLEMENTATION DEFINED”,原因是这张表格摘自《ARM® Generic Interrupt
-Controller》，它不针对具体的芯片，这些寄存器的默认值由芯片厂商决定。表格项“地址偏移”部分值是一个范围比如“中断使能寄存器”地址偏移为“0x100-0x17C”，原因是“中断使能寄存器”有很多，地址偏移范围是“0x100-0x17C”。
+移地址，GIC基地址保存在另外的寄存器中，使用到是我们将详细介绍。"默认值"选项中有"待
+定"手册原文是"IMPLEMENTATION DEFINED",原因是这张表格摘自《ARM® Generic Interrupt
+Controller》，它不针对具体的芯片，这些寄存器的默认值由芯片厂商决定。表格项"地址偏移"部分值是一个范围比如"中断使能寄存器"地址偏移为"0x100-0x17C"，原因是"中断使能寄存器"有很多，地址偏移范围是"0x100-0x17C"。
 
 部分寄存器简单介绍如下：
 
@@ -200,13 +206,13 @@ CPU接口为链接到GIC的处理器提供接口，与分发器类似它也提
 -  确定挂起的中断请求中优先级最高的中断请求。
 
 简单来说，CPU接口可以开启或关闭发往CPU的中断请求，CPU中断开启后只
-有优先级高于 “中断优先级掩码”的中断请求才能被发送到CPU。在任
+有优先级高于 "中断优先级掩码"的中断请求才能被发送到CPU。在任
 何时候CPU都可以从其GICC_Hppir(CPU接口寄存器)读取当前活动的最高优先级。
 
 CPU接口寄存器介绍
 ''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''
 
-同GIC分发器，GIC的CPU接口模块同样提供了一些编程接口，“编程接口”在这里就是一些寄存器，GPU接口寄存器有很多，我们只介绍几个常用的寄存器，其他寄存使用到时再详细介绍，CPU接口寄存器列表如下表所示。
+同GIC分发器，GIC的CPU接口模块同样提供了一些编程接口，"编程接口"在这里就是一些寄存器，GPU接口寄存器有很多，我们只介绍几个常用的寄存器，其他寄存使用到时再详细介绍，CPU接口寄存器列表如下表所示。
 
 表  CPU接口寄存器
 
@@ -245,7 +251,7 @@ CPU接口控制寄存器GICC_CTLR
    :align: center
    :alt: 未找到图片
 
-从上图可以看出GICC_PMR寄存器后8位（0~7）用于设置一个优先级，它的格式与GICD_IPRIORITYR寄存器相同。设置生效后高于此优先级的中断才能发送到CPU。需要注意的是8位寄存器只有高4位有效。与STM32一样，这四位还将分为“抢占优先级”和“子优先级”。讲解优先级分组时再详细介绍。
+从上图可以看出GICC_PMR寄存器后8位（0~7）用于设置一个优先级，它的格式与GICD_IPRIORITYR寄存器相同。设置生效后高于此优先级的中断才能发送到CPU。需要注意的是8位寄存器只有高4位有效。与STM32一样，这四位还将分为"抢占优先级"和"子优先级"。讲解优先级分组时再详细介绍。
 
 中断优先级分组寄存器GICC_BPR
 
@@ -301,7 +307,7 @@ i.MX 6U来说可以忽略该位。interrupt ID[0:9]用于记录
 CP15协处理器
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
-在上一小节的GIC接口寄存器讲解部分我们只给出了“偏移地址”，GIC的基地址保存在CP15协处理器中。我们修改系统控制寄存器以及设置中断向量表地址都会用到CP15协处理器。
+在上一小节的GIC接口寄存器讲解部分我们只给出了"偏移地址"，GIC的基地址保存在CP15协处理器中。我们修改系统控制寄存器以及设置中断向量表地址都会用到CP15协处理器。
 
 CP15协处理器简介
 ''''''''''''''''''''''''''''''''''''''''''''''''''
@@ -395,7 +401,7 @@ CP15读、写实例说明
    /****************以下代码省略***********************/
 
 
-结合以上代码，我们只看“mrc p15, 0, r0, c1, c0, 0”，不难看出，这里读取的CP15标号为c1的寄存器，该寄存器介绍如下图所示。
+结合以上代码，我们只看"mrc p15, 0, r0, c1, c0, 0"，不难看出，这里读取的CP15标号为c1的寄存器，该寄存器介绍如下图所示。
 
 
 
@@ -404,10 +410,10 @@ CP15读、写实例说明
    :alt: 未找到图片
 
 
-结合“mrc {cond} p15, <Opcode_1>, <Rd>, <CRn>, <CRm>, <Opcode_2> ”指令
+结合"mrc {cond} p15, <Opcode_1>, <Rd>, <CRn>, <CRm>, <Opcode_2> "指令
 不难看出这里就是读取的SCTLR(系统控制寄存器)。
 
- 第11行“mcr p15, 0, r0,c1,c0,0”将修改过的r0寄存器值写入到系统控制寄存器。
+ 第11行"mcr p15, 0, r0,c1,c0,0"将修改过的r0寄存器值写入到系统控制寄存器。
 
 (2) 在IRQ中断服务函数中获取GIC控制器基地址。
 
@@ -427,7 +433,7 @@ CP15读、写实例说明
 
 
 
-对比“mrc {cond} p15, <Opcode_1>, <Rd>, <CRn>, <CRm>, <Opcode_2> ”指令
+对比"mrc {cond} p15, <Opcode_1>, <Rd>, <CRn>, <CRm>, <Opcode_2> "指令
 格式可知 CRn、CRm、Opcode_1、Opcode_2分别为c15、c0、4、0。C15寄存器介绍如下图所示。
 
 
@@ -438,14 +444,14 @@ CP15读、写实例说明
 
 
 
-结合上图 可知“MRC P15, 4, r1, C15, C0, 0”读取的是CBAR寄存器。GIC基地址保存在CBAR寄存器中。
+结合上图 可知"MRC P15, 4, r1, C15, C0, 0"读取的是CBAR寄存器。GIC基地址保存在CBAR寄存器中。
 
 i.MX 6U中断分类
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
 查找一个芯片有哪些类型的中断最简单的方法是查看官方启动文件，我们打开第五部分配套程
-序的IAR工程模板的“\section5\IAR_project\libraries\iar”目
-录，文件“startup_MCIMX6Y2.s”是i.MX 6U启
+序的IAR工程模板的"\section5\IAR_project\libraries\iar"目
+录，文件"startup_MCIMX6Y2.s"是i.MX 6U启
 动文件。启动代码的中断向量表部分代码如下所示，其他部分省略。
 
 .. code-block:: asm
@@ -581,7 +587,7 @@ i.MX 6U中断分类
 
 我们不具体讲解汇编启动文件实现，仅仅从中提取我们需要的信息。
 
-第一部分代码，这是我们要找的中断向量表，从这部分可知这个“表”共有8项，除去一个保留项（RESIVED）剩余7个有效项。各项介绍如下：
+第一部分代码，这是我们要找的中断向量表，从这部分可知这个"表"共有8项，除去一个保留项（RESIVED）剩余7个有效项。各项介绍如下：
 
 (1) Res(reset)复位中断，即系统上电或者硬件复位，根据之前讲解系统复位后默认运行在SVC（特权模式）模式，我们裸机默认工作在该模式。
 
@@ -589,10 +595,10 @@ i.MX 6U中断分类
 指令时会进入未定义指令异常中断。这种情况下系统已经无法继续运行，只能通过硬件复位或者看门狗复位系统。
 
 (3) Supervisor
-Call（系统调用中断），这种中断用于带linux操作系统的情况，Linux内核（即驱动程序）运行在SVC（特权模式），而Linux应用程序运行在usr模式。应用程序中如果需要调用驱动程序，就需要首先通过系统调用中断切换到SVC(特权模式)，即我们常说的从“用户（应用）空间”切换到“内核空间”。
+Call（系统调用中断），这种中断用于带linux操作系统的情况，Linux内核（即驱动程序）运行在SVC（特权模式），而Linux应用程序运行在usr模式。应用程序中如果需要调用驱动程序，就需要首先通过系统调用中断切换到SVC(特权模式)，即我们常说的从"用户（应用）空间"切换到"内核空间"。
 
 (4) Prefetch abort（指令预取失败中断），这种中断的解释就是它的名字。在CPU执
-行当前指令时会“预取”下一个要执行的指令。如果“取指”失败就会进入该中断。CPU无法获取指令，所以这种情况下可以认为系统“挂了”。
+行当前指令时会"预取"下一个要执行的指令。如果"取指"失败就会进入该中断。CPU无法获取指令，所以这种情况下可以认为系统"挂了"。
 
 (5) Data abort（数据访问终止中断），同样这种中断的解释就是它的名字。CPU读取
 数据终止，就是说系统读数据错误、读不到数据，所以这种中断后系统也是不正常的。
@@ -602,13 +608,13 @@ Call（系统调用中断），这种中断用于带linux操作系统的情况
 
 第一部分列出了i.MX 6U的中断，下面简单认识一下对于裸机程序这些中断发生时CPU会做些啥。
 
-第二部分，设置中断向量表，以第15行为例，使用“DCD”伪指令将“Reset_Word”（复位中断）跳转地址设置为“__iar_program_start”即复位中断发生后将会跳转到“__iar_program_start”位置执行即第三部分。
+第二部分，设置中断向量表，以第15行为例，使用"DCD"伪指令将"Reset_Word"（复位中断）跳转地址设置为"__iar_program_start"即复位中断发生后将会跳转到"__iar_program_start"位置执行即第三部分。
 
 第三部分，程序入口，复位中断发生后程序将会跳转到这里执行，这里是程序的入口。具体代码我们暂时不关心。
 
 第四部分，从上到下依次为Undefined_Word（未定义指令异常中断）、Supervisor Call（系统调用中断）
 、Prefetch abort（指令预取失败中断）、Data abort（数据访问终止中断）的中
-断跳转地址，可以看到他们都会跳转到“B .”即死循环，程序将会卡死在这里。
+断跳转地址，可以看到他们都会跳转到"B ."即死循环，程序将会卡死在这里。
 
 第五部分，IRQ（中断），IRQ中断发生后程序将会跳转到这里执行，这里是后面小节讲解的重点，本小节主要讲解i.MX 6U中断类型，所以这里暂时跳过。
 
@@ -694,41 +700,41 @@ i.MX 6U 共享中断实现
 
 结合代码讲解如下：
 
-同函数调用类似，进入中断函数之前要将程序当前的运行状态保存保存到“栈”中。中断执行完成后能够恢复进入中断之前的状态。
+同函数调用类似，进入中断函数之前要将程序当前的运行状态保存保存到"栈"中。中断执行完成后能够恢复进入中断之前的状态。
 
--  第一部分，保存当前状态，同函数调用类似，进入中断函数之前要将程序当前的运行状态保存保存到“栈”中。中断执行完成后能够恢复进入中断之前的状态。
-   指令“push {lr}”将lr寄存器“入栈”，根据之前讲解当进行函数调用或发生中断
+-  第一部分，保存当前状态，同函数调用类似，进入中断函数之前要将程序当前的运行状态保存保存到"栈"中。中断执行完成后能够恢复进入中断之前的状态。
+   指令"push {lr}"将lr寄存器"入栈"，根据之前讲解当进行函数调用或发生中断
    时sp(程序计数寄存器，保存当前程序执行位置（Thumb）加4)的值会自动保存到lr寄
    存器中。lr的值将做为函数会中断返回的地址。
 
-指令“push {r0-r3, r12}”将r0~r3寄存器以及r12寄存器“入栈”。r0~r3和r12是通用寄存器，在函数中
+指令"push {r0-r3, r12}"将r0~r3寄存器以及r12寄存器"入栈"。r0~r3和r12是通用寄存器，在函数中
 它们可以用于任何用途，但是在函数调用或函数返回时它们用于传入函数参数以及传出返回
 值等等。中断可能发生在程序的任意时刻，所以进入中断之前也要保存这些信息。
 
 -  第二部分，于保存spsr(备份程序状态寄存器)。SPRS是特殊功能寄存器不能
-   直接访问，指令“MRS r0, spsr”用于将spsr寄存器的值保存到r0寄存器，然后
-   使用“push {r0}”指令将spsr寄存器的值保存到“栈”中。
+   直接访问，指令"MRS r0, spsr"用于将spsr寄存器的值保存到r0寄存器，然后
+   使用"push {r0}"指令将spsr寄存器的值保存到"栈"中。
 
 -  第三部分，获取GIC基地址以及GICC_IAR寄存器的值。
    这部分代码使用到了CP15协处理器，在54.2 CP15协处理器章节已经介绍，这里不再赘述，简单说明各
-   指令的作用。指令“MRC P15, 4, r1, C15, C0, 0”将GIC基地址
-   保存到r1寄存器中。指令“ADD r1, r1,#0x2000”在GIC基地址
+   指令的作用。指令"MRC P15, 4, r1, C15, C0, 0"将GIC基地址
+   保存到r1寄存器中。指令"ADD r1, r1,#0x2000"在GIC基地址
    基础上增加0x2000，得到GICC(GIC的cpu接口寄存器基地址)基地
-   址。指令“LDR r0, [r1, #0xC]”读取GICC_IAR寄存器的值到r0寄存器。
+   址。指令"LDR r0, [r1, #0xC]"读取GICC_IAR寄存器的值到r0寄存器。
 
 -  第四部分，将GICC基地址和GICC_IAR寄存器值入栈。第三部分代码将GICC基地址保
-   存在了r1寄存器，将GICC_IAR寄存器的值保存在了r0寄存器，中断执行完成后我们还要用到这些内容，所以这里将他们“入栈”保存。
+   存在了r1寄存器，将GICC_IAR寄存器的值保存在了r0寄存器，中断执行完成后我们还要用到这些内容，所以这里将他们"入栈"保存。
 
 -  第五部分，切换到Supervisor模式。
 
--  第六部分，跳转到“SystemIrqHandler”函数执行共享中断对应的中断服务函数。
-   指令“push {lr}”保存当前的链接寄存器，即保存程序的
-   返回地址。指令“LDR r2, =SystemIrqHandler”用于将函数“SystemIrqHandler”地址保
-   存到r2寄存器中。指令“BLX r2”是有返回的跳转，程序将会跳转到“SystemIrqHandler”函数执行。
-   函数“SystemIrqHandler”保存
-   在“~\base_code\section5\IAR_project\libraries\\ system_MCIMX6Y2.c”
+-  第六部分，跳转到"SystemIrqHandler"函数执行共享中断对应的中断服务函数。
+   指令"push {lr}"保存当前的链接寄存器，即保存程序的
+   返回地址。指令"LDR r2, =SystemIrqHandler"用于将函数"SystemIrqHandler"地址保
+   存到r2寄存器中。指令"BLX r2"是有返回的跳转，程序将会跳转到"SystemIrqHandler"函数执行。
+   函数"SystemIrqHandler"保存
+   在"~\base_code\section5\IAR_project\libraries\\ system_MCIMX6Y2.c"
    文件内。我们可以用VS code
-   或者直接打开“~\base_code\section5\”目录下的IAR工程。去掉不必要的条件编译后如下所示。
+   或者直接打开"~\base_code\section5\"目录下的IAR工程。去掉不必要的条件编译后如下所示。
 
 
 
@@ -769,7 +775,7 @@ i.MX 6U 共享中断实现
 
 结合代码，各部分讲解如下:
 
-(1) 第一部分，SystemIrqHandler函数有一个入口参数“giccIar”，它是GICC_IAR寄存
+(1) 第一部分，SystemIrqHandler函数有一个入口参数"giccIar"，它是GICC_IAR寄存
 器的值。在代码清单 54‑4的第四部分代码中，我们将GICC_IAR寄存器的值保存到了R0寄存
 器，跳转到SystemIrqHandler函数之后R0寄存器的值作为函数参数。
 
@@ -781,10 +787,10 @@ i.MX 6U 共享中断实现
 
 
 (3) 第三部分，判断中断标号是否有效。根据之前讲解如果中
-断无效，则读取得到的中断号为1023。“NUMBER_OF_INT_VECTORS”是i.MX 6U支持
+断无效，则读取得到的中断号为1023。"NUMBER_OF_INT_VECTORS"是i.MX 6U支持
 的最大中断号加一，大于等于这个值的中断编号也被认为无效。
 
-(4) 如果中断编号有效，这部分根据中断编号在“irqTable”中找到对应的
+(4) 如果中断编号有效，这部分根据中断编号在"irqTable"中找到对应的
 中断服务函数。我们简单了解一下这个表。表定义在system_MCIMX6Y2.h文件，如下所示。
 
 
@@ -800,7 +806,7 @@ i.MX 6U 共享中断实现
 
 
 
-这里把“irqTable”叫做“本地中断向量表”，我们所熟知的那个中断向量表在启动文件中实现，并且位于程序的开始处（0x80002000）。“本地中断向量表”的作用是当IRQ中断发生后找到对应的处理函数。从上方代码不难看出，本地中断向量表是一个“sys_irq_handle_t”结构体类型的数组。“sys_irq_handle_t”结构体如下所示。
+这里把"irqTable"叫做"本地中断向量表"，我们所熟知的那个中断向量表在启动文件中实现，并且位于程序的开始处（0x80002000）。"本地中断向量表"的作用是当IRQ中断发生后找到对应的处理函数。从上方代码不难看出，本地中断向量表是一个"sys_irq_handle_t"结构体类型的数组。"sys_irq_handle_t"结构体如下所示。
 
 .. code-block:: c
    :caption: sys_irq_handle_t结构体
@@ -844,7 +850,7 @@ i.MX 6U 共享中断实现
 添加SDK官方中断相关代码
 '''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''
 
-如下图所示，在“/interrupt_init/include”目录下共添加了5个中断相关的头文件。
+如下图所示，在"/interrupt_init/include"目录下共添加了5个中断相关的头文件。
 
 .. image:: media/interr016.png
    :align: center
@@ -853,13 +859,13 @@ i.MX 6U 共享中断实现
 
 标号①处是内核相关头文件以及符合CMSIS标准的头文件，没有对应的.c文件，这些头文件提供了系统控制函数以及特殊寄存器操作函数，我们直接添加到我们工程即可，几乎不用修改。
 
-标号②处是系统初始化头文件与它对应的.c文件位于本章源码的“/interrupt_init/device”目录下，这里包含我们需要的中断初始化代码以及MMU、时钟等等初始化代码。这里我们只关心中断相关内容，稍后将会结合修改后的代码详细介绍。
+标号②处是系统初始化头文件与它对应的.c文件位于本章源码的"/interrupt_init/device"目录下，这里包含我们需要的中断初始化代码以及MMU、时钟等等初始化代码。这里我们只关心中断相关内容，稍后将会结合修改后的代码详细介绍。
 
 修改启动文件
 ''''''''''''''''''''''''''''''''''''''''''''''''''''''
 
-启动文件参照官方GCC版本启动文件修改，官方文件位于“i.MX6ULL系列\1-野火开源
-图书合集\书籍配套代码\\ base_code_2019_11_09\section5\IAR_project\libraries\gcc”
+启动文件参照官方GCC版本启动文件修改，官方文件位于"i.MX6ULL系列\1-野火开源
+图书合集\书籍配套代码\\ base_code_2019_11_09\section5\IAR_project\libraries\gcc"
 目录下，修改后的源码如下所示。
 
 
@@ -960,14 +966,14 @@ i.MX 6U 共享中断实现
 -  第二部分，定义中断向量表。在讲解中断类型时介绍了这些中断，这些代码与官方启动文件完全相同。
 
 -  第三部分，复位中断服务函数。复位中断服务函数中要完成系统初始化并
-   为进入C环境设置栈空间。代码第三部分到第六部分都是复位中断服务函数的内容。这部分做了两件事，第一，使用“cpsidi”指令
+   为进入C环境设置栈空间。代码第三部分到第六部分都是复位中断服务函数的内容。这部分做了两件事，第一，使用"cpsidi"指令
    关闭全局中断，防止中断干扰初始化过程。第二，剩余代码修改修改系统控制寄存器关闭我们暂时用不到的功能，例如cache、mmu等等。
 
 -  第四部分，设置栈地址。本程序将栈地址设置在DDR的末尾处。IRQ工作模
    式的栈位于0x9FF00000地址处（DDR最后1M地址空间）。User模式和Supervisor模式使用
    相同的栈空间，位于0x9FE00000起始地址处，大小为1M。
 
--  第五部分，调用“SystemInit”执行系统初始化。上一步设置了“栈”所以这里就可以直接调用C函数了。SystemInit函数如下所示。
+-  第五部分，调用"SystemInit"执行系统初始化。上一步设置了"栈"所以这里就可以直接调用C函数了。SystemInit函数如下所示。
 
 
 
@@ -1037,7 +1043,7 @@ SystemInit函数执行完成后，系统已经可以接受中断了，我们回
 添加按键中断初始化代码
 ''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''
 
-与STM32中断初始化不同，我们将详细介绍这部分内容。此外，为了简化程序，我们并没有使用GIC接口寄存器配置每个中断的中断优先级、中断分组等等。中断优先级和中断优先级分组保持函数“SystemInit”设定的默认值。
+与STM32中断初始化不同，我们将详细介绍这部分内容。此外，为了简化程序，我们并没有使用GIC接口寄存器配置每个中断的中断优先级、中断分组等等。中断优先级和中断优先级分组保持函数"SystemInit"设定的默认值。
 
 GPIO引脚中断初始化函数如代码如下所示。
 
@@ -1104,9 +1110,9 @@ GPIO引脚中断初始化函数如代码如下所示。
 
 -  第一部分，这部分内容定义在button.h文件夹下，定义本次使用的GPIO引脚。
 
--  第二部分，添加中断服务函数到“本地中断向量表”，在STM32程序中，中断服务函
+-  第二部分，添加中断服务函数到"本地中断向量表"，在STM32程序中，中断服务函
    数在启动文件中已经定义好了，我们只需要实现即可。但这里需要手动添加中断服务函
-   数到“本地向量表中” SystemInstallIrqHandler函数原型如下所示。
+   数到"本地向量表中" SystemInstallIrqHandler函数原型如下所示。
 
 
 
@@ -1124,7 +1130,7 @@ GPIO引脚中断初始化函数如代码如下所示。
 
 
 
-从以上代码不难看出，该函数就是根据中断号填充全局结构体数组“irqTable”。SystemInstallIrqHandler函数共有三个参数，irq指定中断对应的中断号，handler指定中断服务函数，userParam指定中断服务函数的用户参数，如果不同设置为“NULL”即可。
+从以上代码不难看出，该函数就是根据中断号填充全局结构体数组"irqTable"。SystemInstallIrqHandler函数共有三个参数，irq指定中断对应的中断号，handler指定中断服务函数，userParam指定中断服务函数的用户参数，如果不同设置为"NULL"即可。
 
 -  第三部分，开启中断。GIC相关操作函数定义在core_ca.h文件。感兴趣可以使用这些函数实现更完善的中断。
 
@@ -1195,21 +1201,21 @@ GPIO引脚中断初始化完成后，验证代码就比较简单了。我们定
 下载验证
 ''''''''''''''''''''''''''''''''''''''''''''
 
-程序编写完成后，在“/section5/interrupt_init” 文件夹下执行make命令，makefile工具便
+程序编写完成后，在“interrupt_init” 文件夹下执行make命令，makefile工具便
 会自动完成程序的编译、链接、格式转换等工作。正常情况下我们可以在当前目录看到生成的一些
 中间文件以及我们期待的.bin文件。
 
-在46.2.5 烧写到SD卡章节我们详细讲解了如何将二进制文件烧写到SD卡（烧写工具自动实现为二进制文件添加头）。这里再次说明下载步骤。
+在编译下载官方SDK程序到开发板章节我们详细讲解了如何将二进制文件烧写到SD卡（烧写工具自动实现为二进制文件添加头）。这里再次说明下载步骤。
 
 -  将一张空SD卡（烧写一定会破坏SD卡中原有数据！！！烧写前请保存好SD卡中的数据），接入电脑后在虚拟机的右下角状态栏找到对应的SD卡。将其链接到虚拟机。
 
--  进入烧写工具目录，执行“./mkimage.sh <烧写文件路径>”命令,例如要
-   烧写的led.bin位于home目录下，则烧写命令为“./mkimage.sh /home/led.bin”。
+-  进入烧写工具目录，执行"./mkimage.sh <烧写文件路径>"命令,例如要
+   烧写的led.bin位于home目录下，则烧写命令为"./mkimage.sh /home/led.bin"。
 
 -  执行上一步后会列出linux下可烧写的磁盘，选择你插入的SD卡即可。这一步
    非常危险！！！一定要确定选择的是你插入的SD卡！！，如果选错很可能破坏你电脑
-   磁盘内容，造成数据损坏！！！。确定磁盘后SD卡以“sd”开头，选择“sd”后面的字
-   符即可。例如要烧写的sd卡是“sdb”则输入“b”即可。
+   磁盘内容，造成数据损坏！！！。确定磁盘后SD卡以"sd"开头，选择"sd"后面的字
+   符即可。例如要烧写的sd卡是"sdb"则输入"b"即可。
 
 烧写完成，首先将开发板启动方式设置为SD卡启动，将SD卡插入开发板卡槽。接通电源后循环按下sw2(KEY)按键，正常情况下可以看到RGB灯交替亮红、绿色。
 
diff --git a/documentation/bare_metal/sdk.rst b/documentation/bare_metal/sdk.rst
index db872ccd20c83e50ad020c7fc0d7accdec2b7a86..97236af221cc84a63c8ae6160a942e526184d214 100644
--- a/documentation/bare_metal/sdk.rst
+++ b/documentation/bare_metal/sdk.rst
@@ -3,14 +3,20 @@
 熟悉sdk
 ----------------------------------------
 
-本章节内容处于开发笔记状态，还待整理至最终版的教程。
 
-本章节内容处于开发笔记状态，还待整理至最终版的教程。
 
 SDK（Software Development Kit）是NXP针对其官方评估
-版的软件开发包，可以在NXP的官网下载得到。SDK中包含了各种程序范例，我们心心念念的固件库也包含在它里边。
+版的软件开发包，可以在NXP的官网下载得到。SDK中包含了
+各种程序范例，我们心心念念的固件库也包含在它里边。
+
+
+SDK的下载提供很多选择，下载步骤比较复杂，在本章的配套例程
+文件夹中包含了SDK的原件（路径：~/embed_linux_tutorial/base_code/bare_metal/sdk_nxp），可
+直接使用。若想亲自到官网下载，请按
+如下步骤操作，不感兴趣可直接跳过该步骤：
+
+
 
-SDK的下载提供很多选择，下载步骤比较复杂，在本章的配套例程文件夹中包含了SDK的原件，可直接使用。若想亲自到官网下载，请按如下步骤操作，不感兴趣可直接跳过该步骤：
 
 (1) 访问NXP官网下载链接：https://mcuxpresso.nxp.com/en/dashboardhttps://www.nxp.com/products/processors-and-microcontrollers/arm-processors/i.mx-applications-
 processors/i.mx-6-processors/i.mx-6ull-single-core-processor-with-arm-cortex-a7-core:i.MX6ULL?tab=Design_Tools_Tab
@@ -25,7 +31,7 @@ processors/i.mx-6-processors/i.mx-6ull-single-core-processor-with-arm-cortex-a7-
    :alt: 未找到图片
 
 
-(3) 打开链接之后选择“TOOLS&SOFTWATE”如下所示。
+(3) 打开链接之后选择"TOOLS&SOFTWATE"如下所示。
 
 
 .. image:: media/sdk003.png
@@ -34,7 +40,7 @@ processors/i.mx-6-processors/i.mx-6ull-single-core-processor-with-arm-cortex-a7-
 
 
 
-(4) 网页上可以看到多个下载选项我们选择“SDK2.2_iXMX6ULL_WIN”下载项目点击下载即可，如下所示。
+(4) 网页上可以看到多个下载选项我们选择"SDK2.2_iXMX6ULL_WIN"下载项目点击下载即可，如下所示。
 
 .. image:: media/sdk004.png
    :align: center
@@ -45,7 +51,7 @@ processors/i.mx-6-processors/i.mx-6ull-single-core-processor-with-arm-cortex-a7-
 SDK目录、文件简介
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
-本书讲解的例程全部采用2.2版本SDK的库文件，以下内容请大家打开“SDK_2.2_MCIM6ULL_EBF6ULL”的SDK包配合阅读，如下所示。
+本书讲解的例程全部采用2.2版本SDK的库文件，以下内容请大家打开"SDK_2.2_MCIM6ULL_EBF6ULL"的SDK包配合阅读，如下所示。
 
 .. image:: media/sdk005.png
    :align: center
@@ -58,7 +64,7 @@ boards：示例程序
 
 SDK的boards目录包含了NXP官方评估版MCIMX6ULL-EVK的各种示例程序，非常有参考价值。
 
-例如，下图是“boards\evkmcimx6ull”目录。
+例如，下图是"boards\evkmcimx6ull"目录。
 
 
 .. image:: media/sdk006.png
@@ -69,7 +75,7 @@ SDK的boards目录包含了NXP官方评估版MCIMX6ULL-EVK的各种示例程序
 
 这些文件夹的说明如下：
 
--  demo_apps包含了一些应用范例，如串口打印“hello world”、使用lwip协议栈进行网络通讯等内容，具体如下图所示。
+-  demo_apps包含了一些应用范例，如串口打印"hello world"、使用lwip协议栈进行网络通讯等内容，具体如下图所示。
 
 ..
 
@@ -82,7 +88,7 @@ SDK的boards目录包含了NXP官方评估版MCIMX6ULL-EVK的各种示例程序
 
 
 -  driver_example包含了i.mx6主要片上外设的使用范例，非常详细。例】
-   如在“boards\evkmcimx6ull\driver_examples”目录下包含各个外设的程序如下图所示。
+   如在"boards\evkmcimx6ull\driver_examples"目录下包含各个外设的程序如下图所示。
 
 .. image:: media/sdk008.png
    :align: center
@@ -268,7 +274,7 @@ gcc、iar目录
 
 
 在iar文件夹下startup_MCIMX6Y2.s文件，主要用于配置存储器分配和提供芯片启动时运行的代码指令，其他几个.icf文件根据芯片型号以及芯片所接的存储器类型选择，
-“MCIMX6Y2xxxxx”指定芯片型号，_ram适配nandFlash和eMMC，本教程配套开发板应当选择这种.icf文件。_flash适配norFlash。.icf是程序的分散加载文件，使用到时再详细介绍。
+"MCIMX6Y2xxxxx"指定芯片型号，_ram适配nandFlash和eMMC，本教程配套开发板应当选择这种.icf文件。_flash适配norFlash。.icf是程序的分散加载文件，使用到时再详细介绍。
 
 MCIMX6Y2\drivers目录
 ''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''
@@ -285,10 +291,10 @@ drivers目录是固件库的主体，有时我们把这些文件称为外设驱
    外设名字，如ADC、GPIO、UART、I2C等外设，大部分外设包含一个C源文件和头文件。
 
 -  当使用到某个外设时，我们会把此处对应的外设驱动源文
-   件添加到工程中，加入编译，对于没有源文件的IOMUXC外设，则直接使用“#include”包含其头文件fsl_iomuxc.h。
+   件添加到工程中，加入编译，对于没有源文件的IOMUXC外设，则直接使用"#include"包含其头文件fsl_iomuxc.h。
 
 -  特别地，其中的fsl_common.c和fsl_common.h中的common不是i.MX6芯片
-   的某个外设名字，它表示绝大多数工程都会需要这些“共同”的内容，所以一般工程都
+   的某个外设名字，它表示绝大多数工程都会需要这些"共同"的内容，所以一般工程都
    会添加这个fsl_common.c文件，并且可以通过fsl_common.h文件包含前面介绍的fsl_device_regi
    sters.h头文件，达到最终包含具有大量寄存器定义的MCIMX6Y2.h核心头文件的目的。
 
@@ -345,7 +351,7 @@ SDK中的middleware文件夹主要包含一些中间层软件，即这些软件
 rtos：实时操作系统
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 
-SDK目录下的rtos文件夹包含了FreeRTOS实时操作系统的源代码，位于“boards\evkmcimx6ull\rtos_examples”目录的FreeRTOS例程会使用到这里的源码，我们只需要知道源码再这里就可以了。见下图。
+SDK目录下的rtos文件夹包含了FreeRTOS实时操作系统的源代码，位于"boards\evkmcimx6ull\rtos_examples"目录的FreeRTOS例程会使用到这里的源码，我们只需要知道源码再这里就可以了。见下图。
 
 
 .. image:: media/sdk019.png
diff --git a/documentation/bare_metal/sorting_project.rst b/documentation/bare_metal/sorting_project.rst
index 6b5c95f9f69fd6cf31fc00020c75a4f20bfff813..6c8160c162e9650c0f13eb9bd02a041d1a14b0ff 100644
--- a/documentation/bare_metal/sorting_project.rst
+++ b/documentation/bare_metal/sorting_project.rst
@@ -3,9 +3,7 @@
 整理工程文件
 ------------------------------
 
-本章节内容处于开发笔记状态，还待整理至最终版的教程。
 
-本章节内容处于开发笔记状态，还待整理至最终版的教程。
 
 为降低难度，在之前章节我们把程序所有内容放在一个文件夹下。这样做存在两个主要问题，第一，代码存放混乱不易阅读。第二，程序可移植性差。本章将对代码进行简单的整理，让程序存放更有条理。
 
@@ -15,6 +13,11 @@
 
 -  修改makefile
 
+配套源码以及下载工具:
+-  路径：~/embed_linux_tutorial/base_code/bare_metal/button_adj
+
+
+
 分类存储代码
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
@@ -34,17 +37,17 @@
 
 -  include文件夹，保存程序中使用的头文件。
 
--  makefile，主makefile 。在主makefile中会调用“device”文件夹下的子makefile.
+-  makefile，主makefile 。在主makefile中会调用"device"文件夹下的子makefile.
 
 修改makefile
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
-修改makefile主要包括两部分，第一部分，在“device”文件夹下添加并编写子makefile，第二部分，修改主makefile。
+修改makefile主要包括两部分，第一部分，在"device"文件夹下添加并编写子makefile，第二部分，修改主makefile。
 
 编写子makefile
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 
-子makefile用于将“device”文件夹下的驱动源文件编译为一个“.o”文件，完整内容如下所示。
+子makefile用于将"device"文件夹下的驱动源文件编译为一个".o"文件，完整内容如下所示。
 
 
 .. code-block:: c
@@ -75,13 +78,13 @@
 
 结合代码，各部分简单说明如下：
 
--  第一部分，链接生成最终目标“device.o”。如果程序中新增了某个外设驱动程序，只需要将对应的“.o”文件填入“依赖”处即可。
+-  第一部分，链接生成最终目标"device.o"。如果程序中新增了某个外设驱动程序，只需要将对应的".o"文件填入"依赖"处即可。
 
--  第二部分，编译“device”文件夹下的所有“.c”文件并生成对应的“.o”文件。
+-  第二部分，编译"device"文件夹下的所有".c"文件并生成对应的".o"文件。
 
--  第三部分，编译“device”文件夹下的所有“.S”文件并生成对应的“.o”文件。
+-  第三部分，编译"device"文件夹下的所有".S"文件并生成对应的".o"文件。
 
--  第四部分，它是定义在主makefile中的变量，用“export”声明后可以在其他makefile中调用。
+-  第四部分，它是定义在主makefile中的变量，用"export"声明后可以在其他makefile中调用。
 
 修改主makefile
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
@@ -125,15 +128,15 @@
 
 结合代码，各部分简单说明如下：
 
--  第一部分，定义变量 “CFLAGS”。在makefile中“变量”更
-   像C原因中的宏定义。“-fno-builtin”是一个编译选项，用于解
-   决库函数与自己编写函数同名问题。“-I$(shell pwd)/include”用于指定头文件路径。
+-  第一部分，定义变量 "CFLAGS"。在makefile中"变量"更
+   像C原因中的宏定义。"-fno-builtin"是一个编译选项，用于解
+   决库函数与自己编写函数同名问题。"-I$(shell pwd)/include"用于指定头文件路径。
 
 -  第二部分，makefile最终目标，与原文件相比，这里只是修改了文件的名字。
 
--  第三部分，定义生成“.o”文件的相关内容
+-  第三部分，定义生成".o"文件的相关内容
 
--  第四部分，定义生成“device/device.o”的命令，“device.o”文件由子makefile生成，所以这里只需要调用子makefile即可。
+-  第四部分，定义生成"device/device.o"的命令，"device.o"文件由子makefile生成，所以这里只需要调用子makefile即可。
 
 -  第五部分，定义清理伪目标。在清理命令中不但要
    清理主makefile所在文件夹的内容还要调用子makefile的清理
diff --git a/documentation/bare_metal/uart.rst b/documentation/bare_metal/uart.rst
index d54e20e88b420c324b707cbae0a754354dd42b2e..ed5ce1fdc5c0b5b7efd59fd5c36ce49796f87d31 100644
--- a/documentation/bare_metal/uart.rst
+++ b/documentation/bare_metal/uart.rst
@@ -11,6 +11,9 @@ UART—串口通讯
 
 特别说明，本书内容是以i.MX 6U系列控制器资源讲解。
 
+配套源码以及下载工具:
+-  路径：~/embed_linux_tutorial/base_code/bare_metal/uart
+
 串口通讯协议简介
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
@@ -35,7 +38,7 @@ UART—串口通讯
    :alt: 未找到图片
 
 
-在上面的通讯方式中，两个通讯设备的“DB9接口”之间通过串口信号线建立起连接，串口信号线中使用“RS-232标准”传输数据信号。由于RS-232电平标准的信号不能直接被控制器直接识别，所以这些信号会经过一个“电平转换芯片”转换成控制器能识别的“TTL校准”的电平信号，才能实现通讯。
+在上面的通讯方式中，两个通讯设备的"DB9接口"之间通过串口信号线建立起连接，串口信号线中使用"RS-232标准"传输数据信号。由于RS-232电平标准的信号不能直接被控制器直接识别，所以这些信号会经过一个"电平转换芯片"转换成控制器能识别的"TTL校准"的电平信号，才能实现通讯。
 
 电平标准
 ''''''''''''''''''''''''''''
@@ -68,7 +71,7 @@ RS-232信号线
 ''''''''''''''''''''''''''''''''''''''''''''''''''''''
 
 在最初的应用中，RS-232串口标准常用于计算机、路由
-与调制调解器(MODEN，俗称“猫”)之间的通讯 ，在这种通讯系统中，设备被
+与调制调解器(MODEN，俗称"猫")之间的通讯 ，在这种通讯系统中，设备被
 分为数据终端设备DTE(计算机、路由)和数据通讯设备DCE(调制调解器)。我们以这
 种通讯模型讲解它们的信号线连接方式及各个信号线的作用。
 
@@ -106,7 +109,7 @@ RS-232信号线
 9    响铃指示            RI   DTEDCE   Ring Indicator，响铃指示，表示DCE端与线路已接通
 ==== =================== ==== ======== ======================================================================================================================
 
-上表中的是计算机端的DB9公头标准接法，由于两个通讯设备之间的收发信号(RXD与TXD)应交叉相连，所以调制调解器端的DB9母头的收发信号接法一般与公头的相反，两个设备之间连接时，只要使用“直通型”的串口线连接起来即可，见下图。
+上表中的是计算机端的DB9公头标准接法，由于两个通讯设备之间的收发信号(RXD与TXD)应交叉相连，所以调制调解器端的DB9母头的收发信号接法一般与公头的相反，两个设备之间连接时，只要使用"直通型"的串口线连接起来即可，见下图。
 
 .. image:: media/uart006.jpg
    :align: center
@@ -150,13 +153,13 @@ RS-232信号线
 
 在有效数据之后，有一个可选的数据校验位。由于数据通信相对更容易受到外部干扰导致传输数据出现偏差，可以在传输过程加上校验位来解决这个问题。校验方法有奇校验(odd)、偶校验(even)、0校验(space)、1校验(mark)以及无校验(noparity)，它们介绍如下：
 
--  奇校验要求有效数据和校验位中“1”的个数为奇数，比如一个8位长的
-   有效数据为：01101001，此时总共有4个“1”，为达到奇校验效果，校
-   验位为“1”，最后传输的数据将是8位的有效数据加上1位的校验位总共9位。
+-  奇校验要求有效数据和校验位中"1"的个数为奇数，比如一个8位长的
+   有效数据为：01101001，此时总共有4个"1"，为达到奇校验效果，校
+   验位为"1"，最后传输的数据将是8位的有效数据加上1位的校验位总共9位。
 
--  偶校验与奇校验要求刚好相反，要求帧数据和校验位中“1”的个数为偶数，比如数据帧：11001010，此时数据帧“1”的个数为4个，所以偶校验位为“0”。
+-  偶校验与奇校验要求刚好相反，要求帧数据和校验位中"1"的个数为偶数，比如数据帧：11001010，此时数据帧"1"的个数为4个，所以偶校验位为"0"。
 
--  0校验是不管有效数据中的内容是什么，校验位总为“0”，1校验是校验位总为“1”。
+-  0校验是不管有效数据中的内容是什么，校验位总为"0"，1校验是校验位总为"1"。
 
 -  在无校验的情况下，数据包中不包含校验位。
 
@@ -353,7 +356,7 @@ TxFIFO与RxFIFO大小均为32字节，以发送为例，数据通过UTXD寄存
 UART1收发实验
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
-UART只需两根信号线即可完成双向通信，对硬件要求低，使得很多模块都预留UART接口来实现与其他模块或者控制器进行数据传输，比如GSM模块，WIFI模块、蓝牙模块等等。在硬件设计时，注意还需要一根“共地线”。
+UART只需两根信号线即可完成双向通信，对硬件要求低，使得很多模块都预留UART接口来实现与其他模块或者控制器进行数据传输，比如GSM模块，WIFI模块、蓝牙模块等等。在硬件设计时，注意还需要一根"共地线"。
 
 我们经常使用UART来实现控制器与电脑之间的数据传输。这使得我们调试程序非常方便，比如我们可以把一些变量的值、函数的返回值、寄存器标志位等等通过UART发送到串口调试助手，这样我们可以非常清楚程序的运行状态，当我们正式发布程序时再把这些调试信息去除即可。
 
@@ -387,12 +390,12 @@ UART只需两根信号线即可完成双向通信，对硬件要求低，使得
 添加源文件并修改makefile
 ''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''
 
-首先复制“~\section5\clock_init”代码并更名为“~\section5\uart”。在“~\section5\uart\device”文件夹下添加uart.c文件，在“~\section5\uart\include”文件夹下添加uart.h文件。串口相关代码将会放到uart.c和u
+首先复制"~\section5\clock_init"代码并更名为"~\section5\uart"。在"~\section5\uart\device"文件夹下添加uart.c文件，在"~\section5\uart\include"文件夹下添加uart.h文件。串口相关代码将会放到uart.c和u
 art.h文件内。
 
 添加了源文件，所以要修改makefile ，将源文件编译
-进程序。打开“~\section5\uart\device”目录
-下的makefile文件，在最终目标依赖项中添加“uart.o”如下所示。
+进程序。打开"~\section5\uart\device"目录
+下的makefile文件，在最终目标依赖项中添加"uart.o"如下所示。
 
 
 .. code-block:: c
@@ -413,7 +416,7 @@ art.h文件内。
 
 
 
-在后面的程序中如果使用官方设置波特率函数或者如果用到了除法、取余等算数运算就需要在链接时指定链接库。打开“~\section5\uart”目录下的makefile，在链接指令中指定链接库，如下所示。
+在后面的程序中如果使用官方设置波特率函数或者如果用到了除法、取余等算数运算就需要在链接时指定链接库。打开"~\section5\uart"目录下的makefile，在链接指令中指定链接库，如下所示。
 
 
 .. code-block:: c
@@ -435,8 +438,8 @@ art.h文件内。
    /*****************以下代码省略******************/
 
 
-在makefile中增加了两部分内容。第一部分，代码第5行定义“libgcc_address”变量用于保存“arm-none-eabi”编译工具的安装位置，我们需要的libgcc.a位于该目录下。如果使用教程中介绍的“sudo apt-get install gcc-arm-none-
-eabi”安装则默认位于程序中所指目录，如果使用其他方式安装，找到对应的路径填入该变量即可。第二部分，代码第11行，在链接指令中静态链接libgcc.a库文件。
+在makefile中增加了两部分内容。第一部分，代码第5行定义"libgcc_address"变量用于保存"arm-none-eabi"编译工具的安装位置，我们需要的libgcc.a位于该目录下。如果使用教程中介绍的"sudo apt-get install gcc-arm-none-
+eabi"安装则默认位于程序中所指目录，如果使用其他方式安装，找到对应的路径填入该变量即可。第二部分，代码第11行，在链接指令中静态链接libgcc.a库文件。
 
 定义串口引脚以及引脚PAD属性
 '''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''
@@ -608,7 +611,7 @@ eabi”安装则默认位于程序中所指目录，如果使用其他方式安
 -  第一部分，设置UART根时钟。这部分内容在时钟初
    始化章节以及56.3 UART功能框图章节的56.3 2②串口时钟与波特率小节有过详细介绍，这里不再介绍。
 
--  第二部分，开启UART1的时钟并复位串口。“CCM_CCGR5_CG12”是一个帮
+-  第二部分，开启UART1的时钟并复位串口。"CCM_CCGR5_CG12"是一个帮
    助宏，设置CCM(时钟控制模块)的CCGR5寄存器的CG12位 ，开启UART1的时钟。这点与stm32很相似。
 
 -  第三部分，将UART配置寄存器设置为默认值。这部分内容是参考官方SDK相关代码编写的，笔者认为这部分代码可有可无，暂时把它放在这里。
@@ -668,9 +671,9 @@ eabi”安装则默认位于程序中所指目录，如果使用其他方式安
 
 -  第一部分，定义接收字符函数，函数仅仅返回URXD寄存器的内容。
 
--  第二部分，定义接收字符串函数，参数“base”指定用于接收的串
-   口，参数“data”指定用于保存数据的地址。参数“length”指定读取的字符串
-   长度。函数实现也很简单，循环调用第一部分的“UART_ReadByte”函数，并在读取之前等待接收完成标志。
+-  第二部分，定义接收字符串函数，参数"base"指定用于接收的串
+   口，参数"data"指定用于保存数据的地址。参数"length"指定读取的字符串
+   长度。函数实现也很简单，循环调用第一部分的"UART_ReadByte"函数，并在读取之前等待接收完成标志。
 
 串口发送函数
 ''''''''''''''''''''''''''''''''''''''''''
@@ -712,15 +715,15 @@ eabi”安装则默认位于程序中所指目录，如果使用其他方式安
 
 -  第一部分，定义字节发送函数。函数实现将字节数据写入到UTXD寄存器。
 
--  第二部分，定义字符串发送函数。函数有三个参数“base”指定用于发送的
-   串口，参数“data”指定用于要发送数据的地址。参数“length”指定发送
-   长度。在函数中循环调用第一部分的“UART_WriteByte”字节发送函数。第19行
-   等待发送FIFO可写入，只要FIFO可写入（不关心FIFO中的数据是否发送完成）就立即执行“UART_WriteByte”字节发送函数，通过字节发送函数发送的数据实际是写入FIFO,FIFO中的数据会自动依次执行发送。
+-  第二部分，定义字符串发送函数。函数有三个参数"base"指定用于发送的
+   串口，参数"data"指定用于要发送数据的地址。参数"length"指定发送
+   长度。在函数中循环调用第一部分的"UART_WriteByte"字节发送函数。第19行
+   等待发送FIFO可写入，只要FIFO可写入（不关心FIFO中的数据是否发送完成）就立即执行"UART_WriteByte"字节发送函数，通过字节发送函数发送的数据实际是写入FIFO,FIFO中的数据会自动依次执行发送。
 
 main函数中添加验证代码
 '''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''
 
-main函数中实现“发送接收到的数据”功能，代码实现很简单如下所示。
+main函数中实现"发送接收到的数据"功能，代码实现很简单如下所示。
 
 
 .. code-block:: c
@@ -754,20 +757,20 @@ king循环接收并立即发送接收到的数据。
 下载验证
 ''''''''''''''''''''''''''''''''''''''''''''
 
-程序编写完成后，在“/section5/ uart” 文件夹下执行make命令，makefile工具
+程序编写完成后，在“uart” 文件夹下执行make命令，makefile工具
 便会自动完成程序的编译、链接、格式转换等工作。正常情况下我们可以在当前目
 录看到生成的一些中间文件以及我们期待的.bin文件。
 
-在46.2.5 烧写到SD卡章节我们详细讲解了如何将二进制文件烧写到SD卡（烧写工具自动实现为二进制文件添加头）。这里再次说明下载步骤。
+在编译下载官方SDK程序到开发板章节我们详细讲解了如何将二进制文件烧写到SD卡（烧写工具自动实现为二进制文件添加头）。这里再次说明下载步骤。
 
 -  将一张空SD卡（烧写一定会破坏SD卡中原有数据！！！烧写前请保存好SD卡中的数据），接入电
    脑后在虚拟机的右下角状态栏找到对应的SD卡。将其链接到    虚拟机。
 
--  进入烧写工具目录，执行“./mkimage.sh <烧写文件路径>”命令,例如
-   要烧写的led.bin位于home目录下，则烧写命令为“./mkimage.sh /home/led.bin”。
+-  进入烧写工具目录，执行"./mkimage.sh <烧写文件路径>"命令,例如
+   要烧写的led.bin位于home目录下，则烧写命令为"./mkimage.sh /home/led.bin"。
 
 -  执行上一步后会列出linux下可烧写的磁盘，选择你插入的SD卡即可。这一步非
-   常危险！！！一定要确定选择的是你插入的SD卡！！，如果选错很可能破坏你电脑磁盘内容，造成数据损坏！！！。确定磁盘后SD卡以“sd”开头，选择“sd”后面的字符即可。例如要烧写的sd卡是“sdb”则输入“b”即可。
+   常危险！！！一定要确定选择的是你插入的SD卡！！，如果选错很可能破坏你电脑磁盘内容，造成数据损坏！！！。确定磁盘后SD卡以"sd"开头，选择"sd"后面的字符即可。例如要烧写的sd卡是"sdb"则输入"b"即可。
 
 烧写完成，首先将开发板启动方式设置为SD卡启动，将SD卡插入开发板卡槽。使用USB数据线连接电脑和开发板的USB转串口接口，接通电源，打开串口调试助手，正常情况下可以串口调试助手可以收到来自开发板的提示信息，通过串口调试助手发送字符会立即收到发送的字符，串口调试助手的配置信息如下所示。
 
diff --git a/documentation/building_image/building_NXP_firmware.rst b/documentation/building_image/building_NXP_firmware.rst
new file mode 100644
index 0000000000000000000000000000000000000000..c7f1b7e331edef6ca3a0d38c1e8e98dd064605ff
--- /dev/null
+++ b/documentation/building_image/building_NXP_firmware.rst
@@ -0,0 +1,1576 @@
+.. vim: syntax=rst
+
+制作NXP官方固件
+-----------------
+
+在构建linux系统中，一般的产品倾向选择原厂的固件。因为原厂的固件一般都比较稳定可靠、资料充足，一般的产品要求都能满足，尤其是对稳定性要求苛刻的工业产品。
+这一章就是介绍如何制作NXP官方固件。
+
+
+uboot
+=====
+
+在前面《了解Linux系统组件》章节中，我们简单介绍过uboot相关的概念，此处再回顾一下，总的来说uboot的目的是为了正确引导内核的启动，它分为两个阶段，即boot
++
+loader，boot阶段启动系统，初始化硬件设备，建立内存空间映射图，将系统的软硬件带到一个合适的状态，loader阶段将操作系统内核文件加载至内存，之后跳转到内核所在地址运行。
+
+那么我们今天来编译uboot，并教大家简单修改uboot的内容，因为在真正的生产环境中，uboot是使用芯片原厂做好的，只是根据需要修改一下uboot，而不会去大改uboot的源码，这样子没有必要也没有意义，因为uboot就是为了引导内核启动的，启动后uboot就没有什么作用了，与其将uboot改得乱七八糟还不如花时间去维护内核的稳定性。
+
+下载uboot源码
+~~~~~~~~~~~~~~~
+
+想要编译uboot，首先我们要下载到uboot的源码，野火官方已经在NXP提供的uboot之上做了修改，并且提交到github与gitee上，大家可以从github与gitee上下载uboot的源码:
+
+**github：**
+
+.. code:: bash
+
+    git clone https://github.com/Embedfire/ebf_6ull_uboot.git
+
+**gitee：**
+
+.. code:: bash
+
+    git clone https://gitee.com/wildfireteam/ebf_6ull_uboot.git
+
+当然啦，如果你想下载NXP原厂的uboot怎么办呢？很简单，直接去NXP官方网站下载就好了，打开
+http://git.freescale.com/git/
+网页，可以看到很多nxp官方提供的镜像，有内核镜像也有uboot镜像，我们下载官方提供的uboot镜像，名字为 ``uboot-imx`` ，我们点击 ``uboot-imx.git`` 链接，跳转到下载页面，可以发现该下载页面中有很多uboot相关的信息，如它的分支，标签等，当然我们要注意的是uboot下载界面中的下载信息，我们可以通过 ``git clone`` 命令去拉取 ``uboot-imx`` 源码，他们的地址就是在下载页面信息的最下方：
+
+.. code:: bash
+
+    Clone 
+    git://git.freescale.com/imx/uboot-imx.git
+    http://git.freescale.com/git/cgit.cgi/imx/uboot-imx.git
+
+.. figure:: media/building_uboot002.png
+   :alt: building_uboot
+
+   building_uboot
+.. figure:: media/building_uboot003.png
+   :alt: building_uboot
+
+   building_uboot
+
+**很重要的提醒，我们建议大家使用野火提供的仓库进行编译，而不需要去修改官方的uboot源码。**
+
+在下载完源码后，可以查看一下野官方在NXP的源码之上做了什么样的修改，其实改动的次数只有4次，非常简单，因此我们在日常使用的时候，对uboot的修改是非常微小的，完全不必去分析uboot源码的内容，当然如果你有兴趣，那当我没说。
+
+野火修改uboot的次数如下，它主要是是支持一些硬件，比如LCD触摸屏、HDMI，然后删除NXP官方的logo，修改uboot的延时、bootargs参数等，所以说绝大部分的内容是不需要用户去修改的。
+
+.. code:: bash
+
+    ➜  ebf_6ull_uboot git:(master) git log
+
+    commit d48487689c49f2c29013374689decbbb5bf1459d (HEAD -> master, origin/master)
+    Author: jiejie <1161959934@qq.com>
+    Date:   Wed Feb 26 08:39:48 2020 +0000
+
+        fix bootargs include rw
+
+    commit a3f25a41fda5ee76b0279dba79b396ae6968993c
+    Author: pengjie <jiejie.128@163.com>
+    Date:   Tue Oct 8 02:55:05 2019 +0800
+
+        1.delete logo 2.bootdelay==0
+        
+        Signed-off-by: pengjie <jiejie.128@163.com>
+
+    commit 444f285430aa186cff2ff490c6e4ac2e06cf1c13
+    Author: pengjie <jiejie.128@163.com>
+    Date:   Tue Sep 17 22:43:26 2019 +0800
+
+        1.修改设备树,适配个别的HDMI显示器,使其能够正常的显示
+        
+        Signed-off-by: pengjie <jiejie.128@163.com>
+
+    commit 1e738ade76db905670555a5e32dd63a1c6362382
+    Author: pengjie <jiejie.128@163.com>
+    Date:   Mon Aug 5 21:31:59 2019 +0800
+
+        add for 4.3 & 5.0 & 7.0 LCD
+        
+        Signed-off-by: pengjie <jiejie.128@163.com>
+
+编译前的准备
+~~~~~~~~~~~~~~~~~~~~
+
+开发环境选择 **ubuntu18.04**
+
+**安装独立编译工具链**
+
+arm-none-eabi-gcc：v6.3.1
+
+可以通过以下命令进行安装：
+
+.. code:: bash
+
+     sudo apt-get install gcc-arm-none-eabi
+
+**测试arm-none-eabi-gcc安装是否成功**
+
+.. code:: bash
+
+    arm-none-eabi-gcc -v
+
+    # 输出
+    gcc version 6.3.1 20170620 (15:6.3.1+svn253039-1build1) 
+
+安装一些必要的库，以确保编译能正常通过：
+
+.. code:: bash
+
+    sudo apt-get install lib32ncurses5 lib32tinfo5 libc6-i386
+
+开始编译
+~~~~~~~~~
+
+**清除编译信息**
+
+.. code:: bash
+
+    make ARCH=arm clean
+
+在编译uboot的时候需要我们自定义配置，而nxp官方会提供一些默认配置，这些配置在uboot
+/configs/目录下，如：
+
+-  mx6ull_14x14_evk_defconfig
+-  mx6ull_14x14_evk_emmc_defconfig
+-  mx6ull_14x14_evk_nand_defconfig
+
+就是nxp官方为imx6ull提供的配置文件，可以编译生成从SD卡启动的uboot、从emmc启动的uboot以及从nand启动的uboot，我们可以根据需求选择不同的配置文件从而编译不同的uboot。
+
+进入uboot源码目录下，如果想要编译从SD卡启动的uboot，则可以运行以下命令选择SD卡版本的uboot配置（3个版本的uboot任选其一即可）：
+
+.. code:: bash
+
+    命令（编译sd卡版本uboot）
+    make ARCH=arm mx6ull_14x14_evk_defconfig
+
+而如果想编译从emmc启动的uboot，则运行：
+
+.. code:: bash
+
+    命令（编译emmc卡版本uboot）
+    make ARCH=arm mx6ull_14x14_evk_ emmc _defconfig
+
+想编译从emmc启动的uboot，则运行：
+
+.. code:: bash
+
+    命令（编译nand卡版本uboot）
+    make ARCH=arm mx6ull_14x14_evk_ nand _defconfig
+
+在运行以上命令后，Makefile会根据对应的配置文件的内容将配置更新到当前目录下的
+``.config`` 文件中，如果读者感兴趣可以查看一下该文件的内容，接下来的编译则是根据 ``.config`` 文件的配置进行编译的。
+
+开始编译，运行以下命令：
+
+.. code:: bash
+
+    make -j4 ARCH=arm CROSS_COMPILE=arm-none-eabi-
+
+    ···
+      LD      u-boot
+      OBJCOPY u-boot-nodtb.bin
+      OBJCOPY u-boot.srec
+      SYM     u-boot.sym
+      COPY    u-boot.bin
+      CFGS    board/freescale/mx6ullevk/imximage.cfg.cfgtmp
+      MKIMAGE u-boot.imx
+
+命令中带有jN
+参数，表示最大使用N个线程编译，如j4则表示最大使用4个线程编译，根据自己电脑配置决定即可，当然线程数量越多，编译越快。在输出信息的最下方，可以看到已经生成对应的uboot（名字是u-boot.imx），可以直接烧录到开发板中。
+
+当编译完成后会在当前目录下生成 ``u-boot.imx`` 文件
+
+.. code:: bash
+
+    ebf_6ull_uboot/u-boot.imx
+
+把它与内核、设备树、文件系统烧录到开发板即可。
+
+尝试在uboot中添加自己的修改
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+有时候官方的uboot总是不能满足我们的需求，我们得学会修改对应的uboot配置，比如开机的logo，比如显示屏配置，HDMI配置等，我们就简单修改一下我们的配置，让他能在我们的屏幕上运行，也把开机logo替换为我们的logo。
+
+首先我们要知道这些配置写在什么地方，然后才能去修改它，比如我们先改开机logo，找到uboot
+/tools/目录下的Makefile文件，大约在200行，就有关于开机logo的配置，具体如下：
+
+.. code:: makefile
+
+    # Generic logo
+    ifeq ($(LOGO_BMP),)
+    LOGO_BMP= $(srctree)/$(src)/logos/denx.bmp
+
+    # Use board logo and fallback to vendor
+    ifneq ($(wildcard $(srctree)/$(src)/logos/$(BOARD).bmp),)
+    LOGO_BMP= $(srctree)/$(src)/logos/$(BOARD).bmp
+    else
+    ifneq ($(wildcard $(srctree)/$(src)/logos/$(VENDOR).bmp),)
+    LOGO_BMP= $(srctree)/$(src)/logos/$(VENDOR).bmp
+    endif
+    endif
+
+    endif # !LOGO_BMP
+
+解释一下Makefile文件的描述：
+
+-  使用ifeq 判断是否指定了LOGO_BMP变量（该变量表示开机logo图片），如果不指定则使用默认logo图片denx.bmp，该图片在logos目录下。
+
+-  然后判断一下是否存在使用开发板名字命名的图片（如 :math:(BOARD)，它是一个变量的引用，表示开发板的名字），如果是则使用(BOARD).bmp。
+
+-  最后判断一下是否存在以供应商名字命名的图片（如$(VENDOR).bmp），那么很显然，nxp官方提供的uboot必然是以它们的名字命名logo，那么uboot就会使用它们的logo图片，我们可以到uboot/tools/logos目录下查看一番，就会发现存在freescale.bmp文件，如图所示。
+
+注意：开机logo必须是bmp类型的图片，否则可能出现错误。
+
+.. figure:: media/building_uboot004.png
+   :alt: building_uboot
+
+   building_uboot
+
+既然要修改logo，我们把自己的开机logo图片放进去替换原本的logo即可，我们的开机logo如图所示（注意：logo图片格式必须为bmp格式）。
+
+.. figure:: media/building_uboot005.png
+   :alt: building_uboot
+
+   building_uboot
+
+这些logo在uboot启动时就会被显示在屏幕上，具体的显示logo的函数在uboot
+/board/esd/common/目录下的lcd.c文件中，大约在81行左右，感兴趣的读者可以去看看源码，在这里就不深入分析。
+
+接着我们可以修改显示屏，让我们的开发板支持显示屏的其他尺寸，那么此时就要去配置源码中修改了，nxp官方支持的imx6ull开发板相关的配置源码文件在/uboot/board/freescale/mx6ullevk/目录下的mx6ullevk.c文件中，我们简单修改一下displays这个数组，它是记录了与显示屏相关信息的数组，具体修改如下：
+
+.. code:: c
+
+    struct display_info_t const displays[] = {{
+            .bus = MX6UL_LCDIF1_BASE_ADDR,
+            .addr = 0,
+            .pixfmt = 24,
+            .detect = NULL,
+            .enable = do_enable_parallel_lcd,
+            .mode   = {
+                    .name           = "TFT43AB",
+                    .xres           = 480,
+                    .yres           = 272,
+                    .pixclock       = 108695,
+                    .left_margin    = 8,
+                    .right_margin   = 4,
+                    .upper_margin   = 2,
+                    .lower_margin   = 4,
+                    .hsync_len      = 41,
+                    .vsync_len      = 10,
+                    .sync           = 0,
+                    .vmode          = FB_VMODE_NONINTERLACED
+                       }
+            },
+
+            {
+            .bus = MX6UL_LCDIF1_BASE_ADDR,
+            .addr = 0,
+            .pixfmt = 24,
+            .detect = NULL,
+            .enable = do_enable_parallel_lcd,
+            .mode   = {
+                    .name           = "TFT50AB",
+                    .xres           = 800,
+                    .yres           = 480,
+                    .pixclock       = 108695,
+                    .left_margin    = 46,
+                    .right_margin   = 22,
+                    .upper_margin   = 23,
+                    .lower_margin   = 22,
+                    .hsync_len      = 1,
+                    .vsync_len      = 1,
+                    .sync           = 0,
+                    .vmode          = FB_VMODE_NONINTERLACED
+                       }
+            },
+
+            {
+            .bus = MX6UL_LCDIF1_BASE_ADDR,
+            .addr = 0,
+            .pixfmt = 24,
+            .detect = NULL,
+            .enable = do_enable_parallel_lcd,
+            .mode   = {
+                    .name           = "TFT70AB",
+                    .xres           = 800,
+                    .yres           = 480,
+                    .pixclock       = 108695,
+                    .left_margin    = 46,
+                    .right_margin   = 22,
+                    .upper_margin   = 23,
+                    .lower_margin   = 22,
+                    .hsync_len      = 1,
+                    .vsync_len      = 1,
+                    .sync           = 0,
+                    .vmode          = FB_VMODE_NONINTERLACED
+                       }
+            }
+
+    };
+
+这里的配置是支持3个野火显示屏尺寸的，4.3寸、5寸、7寸、HDMI的适配等，不同的屏幕尺寸稍微不一样，具体阅读以上配置即可，此处不深入研究，都是比较简单的语法，主要是配置硬件相关的信息。
+
+又比如我们在开机时不想让uboot有延时，我们都可以去修改：
+
+在 ``ebf_6ull_uboot/include/configs/mx6_common.h`` 文件中将宏定义改为0：
+
+.. code:: c
+
+    #ifndef CONFIG_BOOTDELAY
+    #define CONFIG_BOOTDELAY    0
+    #endif
+
+在 ``ebf_6ull_uboot/include/configs/mx6ullevk.h`` 文件中设置uboot传给内核的参数，比如设置console、bootargs、bootcmd等：
+
+**nand 版本的参数：**
+
+.. code:: c
+
+    #define CONFIG_EXTRA_ENV_SETTINGS \
+        CONFIG_MFG_ENV_SETTINGS \
+        "panel=TFT50AB\0" \
+        "splashimage=0x82000000\0" \
+        "fdt_addr=0x83000000\0" \
+        "fdt_high=0xffffffff\0"   \
+        "console=ttymxc0\0" \
+        "bootargs=console=ttymxc0,115200 ubi.mtd=3 "  \
+            "root=ubi0:rootfs rw rootfstype=ubifs "          \
+            CONFIG_BOOTARGS_CMA_SIZE \
+            "mtdparts=gpmi-nand:64m(boot),16m(kernel),16m(dtb),-(rootfs)\0"\
+        "bootcmd=nand read ${loadaddr} 0x4000000 0x800000;"\
+            "nand read ${fdt_addr} 0x5000000 0x100000;"\
+            "bootz ${loadaddr} - ${fdt_addr}\0"
+
+**emmc版本的参数太长了，就不贴代码了，感兴趣的可以自己看源码。**
+
+
+编译内核
+=========================
+
+下载野火官方提供的内核镜像
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+在编译内核前我们首先要下载到官方提供的内核镜像，目前野火官方镜像已经托管在github上，可以随时去下载，打开 https://github.com/Embedfire/ebf_6ull_linux 网页，可以看到野火官方提供的内核镜像，并且携带了很详细的操作说明文档，这个仓库是来源于NXP官方提供的内核镜像 http://git.freescale.com/git/cgit.cgi/imx/linux-imx.git/ ，由 ``imx_4.1.15_2.0.0_ga`` 分支开发而来，主要是满足野火开发板的需求。
+
+我们只需要野火官方提供的内核镜像即可，首先我们克隆一下这个内核镜像仓库，在克隆内核镜像的时候最好是在虚拟机中（或linux环境），而不是在Windows环境下，我们将使用 ``git clone`` 命令去克隆官方提供的内核镜像，这样子就能保留镜像中的所有git信息与标签，在开发过程中能方便切换到合适的分支进行开发，因为不同的分支内核镜像的源代码修改的地方是不一样的，可能会发生未知的问题，我们目前就使用 ``master`` 分支进行开发。
+
+使用 ``git clone`` 命令克隆内核镜像，然后等待克隆完成即可：
+
+.. code:: bash
+
+    git clone https://github.com/Embedfire/ebf_6ull_linux.git
+
+由于github网站是国外的，可能会非常慢，甚至出现下载失败现象，建议使用gitee中的仓库，我们已经将源码提交到gitee平台，直接使用 ``git clone`` 命令克隆内核镜像即可：
+
+.. code:: bash
+
+    git clone https://gitee.com/wildfireteam/ebf_6ull_linux.git
+
+    Cloning into 'ebf_6ull_linux'...
+    remote: Enumerating objects: 54412, done.
+    remote: Counting objects: 100% (54412/54412), done.
+    remote: Compressing objects: 100% (47905/47905), done.
+    remote: Total 54412 (delta 5331), reused 54348 (delta 5281)
+    Receiving objects: 100% (54412/54412), 148.94 MiB | 3.49 MiB/s, done.
+    Resolving deltas: 100% (5331/5331), done.
+    Checking out files: 100% (51413/51413), done.
+
+内核源码目录
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+在运行 ``git clone`` 命令命令后，大约等待一分钟，我们可以看到输出的信息，已然提示克隆完成，我们会发现克隆的目录下多出了一个文件夹 ``ebf_6ull_linux`` ，我们可以进入到 ``ebf_6ull_linux`` 目录下，可以使用git
+log查看仓库的日志信息，看看更改了什么地方。在 ``ebf_6ull_linux`` 目录下看到当前目录下多了很多文件夹，它就是我们克隆的内核镜像，里面是官方提供的内核源码，我们可以进入imx-linux目录下中查看主要有哪些文件夹组成，具体见：
+
+.. code:: bash
+
+    ➜  ebf_6ull_linux git:(master) ls
+
+    arch      CREDITS        fs       Kconfig      mm               REPORTING-BUGS  tools
+    block     crypto         include  kernel       Module.symvers   samples         usr
+    build.sh  Documentation  init     lib          net              scripts         virt
+    COPYING   drivers        ipc      MAINTAINERS  OFFICIAL-README  security
+    copy.sh   firmware       Kbuild   Makefile     README.md        sound
+
+.. figure:: media/building_kernel001.png
+   :alt: building_kernel001
+
+   building_kernel001
+
+
+从图中我们可以看到Linux内核源码目录下是有非常多的文件夹，且文件夹下也有非常多的文件，下面我们简单分析一下这些文件夹的主要作用。
+
+-  arch：主要包含和硬件体系结构相关的代码，如arm、x86、MIPS，PPC，每种CPU平台占一个相应的目录，例如我们使用的imx系列CPU就在 ``arch/arm/mach-imx`` 目录下，Linux内核目前已经支持30种左右的CPU体系结构。arch中的目录下存放的是各个平台以及各个平台的芯片对Linux内核进程调度、
+   内存管理、 中断等的支持，以及每个具体的SoC和电路板的板级支持代码。
+
+-  block：在Linux中block表示块设备（以块（多个字节组成的整体，类似于扇区）为单位来整体访问），譬如说SD卡、Nand、硬盘等都是块设备，block目录下放的是一些Linux存储体系中关于块设备管理的代码。
+
+-  crypto：这个文件夹下存放的是常用加密和散列算法（如md5、AES、 SHA等）
+   ，还有一些压缩和CRC校验算法。
+
+-  Documentation：内核各部分的文档描述。
+
+-  drivers：设备驱动程序，里面列出了linux内核支持的所有硬件设备的驱动源代码，每个不同的驱动占用一个子目录，如char、
+   block、 net、 mtd、 i2c等。
+
+-  fs：fs就是file system，里面包含Linux所支持的各种文件系统，如EXT、
+   FAT、 NTFS、 JFFS2等。
+
+-  include：目录包括编译核心所需要的大部分头文件，例如与平台无关的头文件在 ``include/linux`` 子目录下，与cpu架构相关的头文件在include目录下对应的子目录中。
+
+-  init：内核初始化代码，这个目录下的代码就是linux内核启动时初始化内核的代码。
+
+-  ipc：ipc就是 ``inter process commuication`` ，进程间通信，该文件夹下都是linux进程间通信的代码。
+
+-  kernel：kernel就是Linux内核，是Linux中最核心的部分，包括进程调度、定时器等，而和平台相关的一部分代码放在 ``arch/*/kernel`` 目录下。
+
+-  lib：lib是库的意思，lib目录下存放的都是一些公用的有用的库函数，注意这里的库函数和C语言的库函数不一样的，因为在内核编程中是不能用C语言标准库函数的，所以需要使用lib中的库函数，除此之外与处理器结构相关的库函数代码被放在 ``arch/*/lib/`` 目录下。
+
+-  mm： 目录包含了所有独立于 cpu
+   体系结构的内存管理代码，如页式存储管理内存的分配和释放等，而与具体硬件体系结构相关的内存管理代码位于 ``arch/*/mm`` 目录下，例如 ``arch/arm/mm/fault.c`` 。
+
+-  net： 网络协议栈相关代码，net目录下实现各种常见的网络协议。
+
+-  scripts：这个目录下全部是脚本文件，这些脚本文件不是linux内核工作时使用的，而是用了配置编译linux内核的。
+
+-  security：内核安全模型相关的代码，例如最有名的SELINUX。
+
+-  sound： ALSA、 OSS音频设备的驱动核心代码和常用设备驱动。
+
+-  usr： 实现用于打包和压缩的cpio等。
+
+提示：对于其他的未列出来的目录，暂时不用去理会。
+
+进行编译
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+简单了解内核源码的目录结构后，我们可以开始尝试编译内核，本小节主要是以编译我们配套的开发板源代码为主。
+
+我们提供的源码包是经过修改的，首先进入 ``ebf_6ull_linux/arch/arm/configs`` 目录下，可以看到很多默认的deconfig文件，这些是linux源码中的配置文件，其中我们主要关注 ``imx_v6_v7_defconfig、imx_v7_defconfig 、imx6_v7_ebf_defconfig`` 这3个文件即可， ``imx_v6_v7_defconfig、imx_v7_defconfig`` 这两个文件是nxp官方提供的默认配置文件，而 ``imx6_v7_ebf_defconfig`` 文件则是我们野火提供的配置文件，这些文件是与编译内核息息相关的，而不同的开发板这些配置是不一样的，前面两个是用于编译官方的imx6ull开发板，而后面两个则是根据我们的imx6ull开发板硬件而定制的配置。
+由于整个内核镜像都已经打上我们的补丁，那么也无需再做过多的修改即可直接编译，我们可以通过git
+log命令查看补丁信息：
+
+.. code:: bash
+
+    ➜  ebf_6ull_linux git:(master) ✗ git log
+
+    commit fe1b9b8fe423aa41ff53757b94adddea8973662d (HEAD -> master, origin/master)
+    Author: jiejie <1161959934@qq.com>
+    Date:   Tue Jan 14 08:06:54 2020 +0000
+
+        update config
+
+    commit 3594c804dafc37dae86a89520273b87c35488ce9
+    Author: jiejie <1161959934@qq.com>
+    Date:   Tue Jan 14 07:33:57 2020 +0000
+
+        update config
+
+    commit 342f29e8f7813917c945c3fde1bf2767b61110f6
+    Author: jiejie <1161959934@qq.com>
+    Date:   Tue Jan 7 02:44:46 2020 +0000
+
+        update README.md
+
+    commit 7c24a3c05257373d30dd698398b9bb798e814cec
+    Author: jiejie <1161959934@qq.com>
+    Date:   Wed Nov 27 02:45:14 2019 +0000
+
+        compatible with 5-inch and 4.3-inch LCD
+
+    commit 1b9f4f2252477d8eb41eb3f53f0e2232de7af576
+    Author: jiejie <1161959934@qq.com>
+    Date:   Tue Nov 19 06:44:02 2019 +0000
+
+        add 7' HDMI support
+
+搭建编译环境
+~~~~~~~~~~~~
+
+开发环境： **ubuntu18.04**
+
+**安装必要的库**
+
+.. code:: bash
+
+    sudo apt-get install lzop libncurses5-dev
+
+**安装独立编译工具链**
+
+1. 命令安装方式（推荐新手使用这种方法）：
+
+arm-linux-gnueabihf-gcc： ``v7.4.0``
+
+.. code:: bash
+
+    sudo apt-get install gcc-arm-linux-gnueabihf
+
+2. 安装包安装方式(推荐老手使用这种方法)
+
+从百度云盘下载 ``arm-linux-gnueabihf-gcc`` 编译器的压缩包，版本是
+``v4.9.3``
+
+链接： https://github.com/Embedfire/products/wiki
+
+在 **Linux系列产品** 中找到的网盘链接，在 ``i.MX6ULL系列\5-编译工具链\arm-gcc`` 目录下找到``arm-gcc.tar.gz``压缩包并且下载，然后解压到 ``/opt/arm-gcc/`` 目录下，如果没有创建即可，解压后就可以在 ``/opt/arm-gcc/bin/`` 目录下找到我们的编译器 ``arm-linux-gnueabihf-gcc`` ，它的版本是 ``gcc version 4.9.3 20141031 (prerelease) (Linaro GCC 2014.11)`` ，然后可以将编译器所在的路径添加到环境变量中，只修改当前用户的配置文件，通常是 ``"~/.bashrc"`` 或者 ``"~/.bash_profile"`` ，直接
+vi 打开即可，在文件末尾增加编译器所在的路径：
+
+.. code:: bash
+
+    export PATH=$PATH:/opt/arm-gcc/bin/
+
+立即使新的环境变量生效，不用重启电脑：
+
+.. code:: bash
+
+    ➜  ebf_6ull_linux git:(master) ✗ source ~/.bashrc
+
+然后检查是否将路径加入到PATH：
+
+.. code:: bash
+
+    ➜  ebf_6ull_linux git:(master) ✗ echo $PATH
+
+显示的内容中有 ``/opt/arm-gcc/bin`` ，说明已经将交叉编译器的路径加入PATH。至此，交叉编译环境安装完成。
+
+测试是否安装成功
+
+.. code:: bash
+
+    ➜  ebf_6ull_linux git:(master) ✗ arm-linux-gnueabihf-gcc -v
+    Using built-in specs.
+    COLLECT_GCC=arm-linux-gnueabihf-gcc
+    COLLECT_LTO_WRAPPER=/opt/arm-gcc/bin/../libexec/gcc/arm-linux-gnueabihf/4.9.3/lto-wrapper
+    ···
+    gcc version 4.9.3 20141031 (prerelease) (Linaro GCC 2014.11) 
+
+上面的命令会显示arm-linux-gcc信息和版本，说明成功。
+
+更多安装方法参考： https://blog.csdn.net/u013485792/article/details/50958253
+
+作者备注：为什么推荐更低版本的编译器呢？因为作者亲测新版本的编译器并不能完全兼容，在测试比如新版本编译的内核镜像无法识别到4G模块。但是在绝大部分情况下 ``v7.4.0`` 版本的编译器都是没有任何问题的！！！请放心使用！！！
+
+编译前准备
+~~~~~~~~~~
+
+在开始编译内核前，可以把环境变量设置一下，以防编译时找不到环境变量：
+
+.. code:: bash
+
+    export PATH=/opt/arm-gcc/bin:$PATH 
+    export ARCH=arm 
+    export CROSS_COMPILE=arm-linux-gnueabihf- 
+
+**清除编译信息**
+
+.. code:: bash
+
+    make ARCH=arm clean
+
+设置配置选项，使用野火开发板配置
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+首先进入imx-linux目录下，然后开始编译内核，运行 ``make ARCH=arm imx6_v7_ebf_defconfig`` 命令将imx6_v7_ebf_defconfig配置文件的信息写入当前路径下的
+``.config`` 文件中，在linux中以 ``"."`` 开头的文件都是隐藏文件，我们可以使用ls
+–la命令查看这些文件。
+
+.. code:: bash
+
+    make ARCH=arm imx6_v7_ebf_defconfig
+
+
+    输出
+      HOSTCC  scripts/basic/fixdep   
+      HOSTCC  scripts/kconfig/conf.o   
+      SHIPPED scripts/kconfig/zconf.tab.c   
+      SHIPPED scripts/kconfig/zconf.lex.c   
+      SHIPPED scripts/kconfig/zconf.hash.c   
+      HOSTCC  scripts/kconfig/zconf.tab.o   
+      HOSTLD  scripts/kconfig/conf 
+      # 
+      # configuration written to .config 
+      #
+
+Linux内核的配置系统由三个部分组成，分别是： 
+-  Makefile：分布在 Linux内核源代码根目录及各层目录中，定义 Linux 内核的编译规则； 
+
+-  配置文件：给用户提供配置选择的功能，如Kconfig文件定义了配置项，.config文件对配置项进行赋值；
+
+-  配置工具：包括配置命令解释器（对配置脚本中使用的配置命令进行解释）和配置用户界面（linux提供基于字符界面、
+基于Ncurses 图形界面以及基于 Xwindows 图形界面的用户配置界面，各自对应于make config、make menuconfig 和 make xconfig）。
+读者如果想看我们提供的配置文件imx6_v7_ebf_defconfig中修改了什么地方，可以通过makemenuconfig命令来查看我们的配置，
+makemenuconfig是一个基于文本选择的配置界面，推荐在字符终端下使用，make menuconfig运行的时候会从当前目录下
+导入 .config文件的配置（如果没有找到.config文件则会生成默认配置的 .config文件），
+而这个配置则是我们运行make ARCH=arm imx6_v7_ebf_defconfig命令生成的，这就直接可以看到我们在imx6_v7_ebf_defconfig的配置选择，
+可以通过键盘的"上"、"下"、"左"、"右"、"回车"、"空格"、"?"、"ESC"等按键进行选择配置，具体见：
+
+.. figure:: media/building_kernel002.png
+   :alt: building_kernel002
+
+   building_kernel002
+
+比如我们选择配置我们开发板的触摸屏驱动： ``Goodix I2C touchscreen`` ，如果读者炸不到这个配置选项在哪里，可以利用 ``make menuconfig`` 中的搜索功能，在英文输入法状态下按下"/"则可以进行搜索，输入"Goodix"找到改配置选项的位置，具体见：
+
+.. figure:: media/building_kernel003.png
+   :alt: building_kernel003
+
+   building_kernel003
+
+从图中可以很明显看出 ``Goodix I2C touchscreen`` 配置选项位于 ``-> Device Drivers`` 选项下的 ``-> Input device support`` 下的 ``-> Generic input layer (needed for keyboard, mouse, ...) (INPUT [=y])`` 选项下的 ``-> Touchscreens`` 选项中，其实也可以按下 ``"1"`` 直接可以定位到对应的选项，然后选中以下内容即可，具体见图：
+
+.. code:: bash
+
+    [*]Goodix touchpanel GT9xx series 
+    <*> Goodix GT9xx touch controller auto update support 
+    <*> Goodix GT9xx Tools for debuging 
+    <*>Goodix I2C touchscreen
+
+.. figure:: media/building_kernel004.png
+   :alt: building_kernel004
+
+   building_kernel004
+再举个例子，如果想要在我们的开发板上使用 ``DHT11`` 测量温湿度（单总线协议），那么需要在内核中配置支持单总线协议： ``Dallas's 1-wire support`` ，我们也照葫芦画瓢，先搜索到这个配置在哪个位置（时候搜索不到就直接找即可），它位于 ``->Device Drivers``
+选项下的 ``<*> Dallas's 1-wire suppor`` 选项中，然后进入它的选项下进行选择即可，当配置完成后保存退出，就可以进行编译了，具体见:
+
+.. figure:: media/building_kernel005.png
+   :alt: building_kernel005
+
+   building_kernel005
+
+开始编译
+~~~~~~~~
+
+如果不需要修改配置，则可以直接编译，运行 ``make ARCH=arm -j10 CROSS_COMPILE=arm-linux-gnueabihf-`` 命令直接编译， ``-j10`` 是代表使用10个线程进行编译，如果不选则默认使用一个线程编译，而线程的多少决定了编译的时间，根据自身情况决定即可，在运行这个命令后，可以看到中断输出一系列编译信息，而在编译的最后会告诉我们编译成功，镜像存在 ``arch/arm/boot/`` 目录下，具体见：（已删减绝大部分编译输出的信息）。
+
+.. code:: bash
+
+    make ARCH=arm -j10 CROSS_COMPILE=arm-linux-gnueabihf- 
+
+    # 输出内容（已删减绝大部分编译输出的信息）
+    ···
+    OBJCOPY arch/arm/boot/zImage   
+    Kernel: arch/arm/boot/zImage is ready
+    ···
+
+编译生成的镜像输出路径
+~~~~~~~~~~~~~~~~~~~~~~
+
+**内核镜像路径**
+
+.. code:: bash
+
+    ebf_6ull_linux/arch/arm/boot
+
+**设备树输出路径**
+
+.. code:: bash
+
+    ebf_6ull_linux/arch/arm/boot/dts
+
+因为这个 ``make ARCH=arm -j10 CROSS_COMPILE=arm-linux-gnueabihf-`` 命令编译的不仅仅是内核，还会编译设备树，设备树编译后产生的.dtb文件存在 ``arch/arm/boot/dts/`` 目录下，我们可以通过 ``ls arch/arm/boot/dts/ | grep .dtb`` 命令查看该目录下的所有设备树：
+
+.. code:: bash
+
+    ➜  ebf_6ull_linux git:(master) ✗ ls arch/arm/boot/dts/ | grep .dtb
+
+    imx6ull-14x14-evk-btwifi.dtb
+    imx6ull-14x14-evk.dtb
+    imx6ull-14x14-evk-emmc-43.dtb
+    imx6ull-14x14-evk-emmc-cam-dht11.dtb
+    imx6ull-14x14-evk-emmc.dtb
+    imx6ull-14x14-evk-emmc-hdmi.dtb
+    imx6ull-14x14-evk-emmc-wifi.dtb
+    imx6ull-14x14-evk-gpmi-weim-43.dtb
+    imx6ull-14x14-evk-gpmi-weim-cam-dht11.dtb
+    imx6ull-14x14-evk-gpmi-weim-hdmi.dtb
+    imx6ull-14x14-evk-gpmi-weim-wifi.dtb
+
+**拷贝zImage与dtb**
+
+然后我们可以直接运行脚本 ``copy.sh`` 将内核镜像与设备树拷贝到 ``image`` 目录下
+
+.. code:: bash
+
+    ➜  ebf_6ull_linux git:(master) ✗ ./copy.sh
+
+    all kernel and DTB are copied to /home/jiejie/ebf_6ull_linux/image/
+
+只编译设备树
+~~~~~~~~~~~~
+
+当然，如果你不想编译内核的话，只想编译设备树，那么可以在 ``make ARCH=arm -j10 CROSS_COMPILE=arm-linux-gnueabihf-`` 命令后面添加
+``dtbs`` 即可
+
+.. code:: bash
+
+    make ARCH=arm -j10 CROSS_COMPILE=arm-linux-gnueabihf- dtbs
+
+编译的设备树：
+
+-  imx6ull-14x14-evk.dts
+-  imx6ull-14x14-evk-btwifi.dts
+-  imx6ull-14x14-evk-emmc.dts
+-  imx6ull-14x14-evk-gpmi-weim-43.dts
+-  imx6ull-14x14-evk-emmc-43.dts
+-  imx6ull-14x14-evk-gpmi-weim-hdmi.dts
+-  imx6ull-14x14-evk-emmc-hdmi.dts
+-  imx6ull-14x14-evk-gpmi-weim-wifi.dts
+-  imx6ull-14x14-evk-emmc-wifi.dts
+-  imx6ull-14x14-evk-gpmi-weim-cam-dht11.dts
+-  imx6ull-14x14-evk-emmc-cam-dht11.dts
+
+一键编译
+~~~~~~~~
+
+如果你什么都不想理会，那么这个一键编译内核与设备树就更适合你了，直接运行以下命令
+
+::
+
+    ./build.sh
+
+或者...
+
+::
+
+    ./build.sh 5.0
+
+生成的内核镜像与设备树均被拷贝到 ``image`` 目录下。
+内核模块相关均被安装到 ``my_lib/lib/``
+目录下的 ``modules`` 文件夹下，可以直接替换掉 ``rootfs(根文件系统)`` 中的 ``/lib/modules/`` 。
+
+``build.sh`` 脚本默认编译5.0寸屏幕的内核镜像，如果需要4.3寸屏幕的内核镜像，则可以使用以下命令去编译:
+
+::
+
+    ./build.sh 4.3
+
+修改LOGO
+~~~~~~~~~~~~~~~~~
+
+其实在野火开发板的固件中，uboot是没有logo的，因为将uboot的logo删掉了，因为在内核有logo，而uboot到内核的时间非常短（已经将uboot等待
+3S
+时间去掉了），所以直接使用内核的logo会更好，那么如果想要使用内核的logo，就得自己去修改内核的logo，下面就教大家如何去做。
+
+准备一张图片
+^^^^^^^^^^^^^^
+
+我们可以随便准备一张图片，比如我们就选择ubuntu的logo吧，将它制作成适合显示屏大小的图片，比如5寸屏幕的分辨率是800*480：
+
+.. figure:: media/building_kernel006.png
+   :alt: building_kernel006
+
+   building_kernel006
+
+然后将其保存为 **256色（即8位色）的bpm格式的图片** ，可以在Windows下或者Linux虚拟机下编辑：
+
+.. figure:: media/building_kernel007.png
+   :alt: building_kernel007
+
+   building_kernel007
+
+转换为ppm格式的图片
+^^^^^^^^^^^^^^^^^^^^^
+
+然后在Linux下使用以下脚本将其转换为ppm格式的文件，为什么是ppm格式呢？因为这是编译Linux内核必要的文件格式，想要修改logo，就要这种格式的文件，它必须是 **256色（即8位色）的bpm格式的图片** 转换而成的。
+
+.. code:: bash
+
+    #!/bin/bash
+    if [ " $1" == " " ];
+    then
+        echo "usage:$0 bmp_file"
+        exit 0
+    fi
+
+    if [ -f "$1" ]
+    then
+        echo $1
+    else
+        echo "no find file [$1]"
+        exit 0
+    fi
+
+    name=${1%%.*}
+    bmptopnm $1 > $name.pnm
+    pnmquant 224 $name.pnm > $name.clut224.pnm
+    pnmtoplainpnm $name.clut224.pnm > $name.ppm
+    rm $name.pnm $name.clut224.pnm 
+
+这是bmp文件转换ppm格式文件的脚本，可以将其写入一个叫 ``bmp2ppm.sh`` 脚本文件中，并且赋予其可执行的权限（使用
+``chmod +x bmp2ppm.sh``
+命令即可），它主要是使用linux系统中的工具转换，如果系统中没有相关工具，则根据提示使用 ``apt install`` 命令进行安装即可。
+
+然后将准备好的bmp文件拷贝到制作ppm的工作目录下，使用 ``bmp2ppm.sh`` 脚本将其转化为ppm文件，具体操作如下：
+
+.. code:: bash
+
+    ➜  bmp2ppm git:(master) ✗ ls
+    bmp2ppm.sh  README.md  ubuntu.bmp
+
+    ➜  bmp2ppm git:(master) ✗ ./bmp2ppm.sh ubuntu.bmp 
+    ubuntu.bmp
+    bmptopnm: Windows BMP, 800x480x8
+    bmptopnm: WRITING PPM IMAGE
+    pnmcolormap: making histogram...
+    pnmcolormap: 29 colors found
+    pnmcolormap: Image already has few enough colors (<=224).  Keeping same colors.
+    pnmremap: 29 colors found in colormap
+
+    ➜  bmp2ppm git:(master) ✗ ls
+    bmp2ppm.sh  README.md  ubuntu.bmp  ubuntu.ppm
+
+替换原本的logo文件
+^^^^^^^^^^^^^^^^^^^^^
+
+在转换完成后，当前目录将出现对应的ppm文件，我们将其拷贝到linux内核源码的 ``ebf_6ull_linux/drivers/video/logo`` 目录下，因为我们的logo是存放在此处的，野火提供的logo：
+
+-  默认编译的logo：logo_linux_clut224.ppm
+-  5寸触摸屏logo：logo_linux_clut224_5.0.ppm
+-  4.3寸触摸屏logo：logo_linux_clut224_4.3.ppm
+
+然后将其重命名为你想替换的logo即可， **注意** ，5寸触摸屏logo与4.3寸触摸屏logo是一键编译使用的，它在一键编译过程中会替换掉默认的logo，如果你只替换了默认编译的logo，但是使用了一键编译脚本，那么你替换的logo将被一键编译脚本修改，编译产生的内核将不会存在你的logo。
+
+修改启动脚本
+^^^^^^^^^^^^^^
+
+替换完成后，重新编译内核，并且烧录到开发板上，不过此时会出现一个现象，logo一闪而过，这是因为内核启动后，会执行文件系统的启动脚本，而此时文件系统的启动脚本中 ``/etc/init.d/psplash.sh`` 会去执行相应的应用程序 ``/usr/bin/psplash`` ，这就是绘制开机的进度条与背景，那么你的开机logo将被刷掉，而只要不让这个启动脚本运行这个 ``/usr/bin/psplash`` 应用程序就可以解决问题了，那么我们在开发板中修改启动脚本 ``/etc/init.d/psplash.sh`` ：
+
+.. code:: bash
+
+    #!/bin/sh 
+    ### BEGIN INIT INFO
+    # Provides:             psplash
+    # Required-Start:
+    # Required-Stop:
+    # Default-Start:        S
+    # Default-Stop:
+    ### END INIT INFO
+
+    read CMDLINE < /proc/cmdline
+    for x in $CMDLINE; do
+            case $x in
+            psplash=false)
+                    echo "Boot splashscreen disabled" 
+                    exit 0;
+                    ;;
+            esac
+    done
+
+    export TMPDIR=/mnt/.psplash
+    mount tmpfs -t tmpfs $TMPDIR -o,size=40k
+
+    rotation=0
+    if [ -e /etc/rotation ]; then
+            read rotation < /etc/rotation
+    fi
+
+    /usr/bin/psplash --angle $rotation &
+
+将其最后一行屏蔽掉：
+
+.. code:: bash
+
+    # /usr/bin/psplash --angle $rotation &
+
+或者直接禁止启动该脚本，在终端执行以下命令：
+
+.. code:: bash
+
+    /usr/bin/psplash stop
+
+然后重启开发板，就可以看见你的logo了。
+
+
+烧录自己编译的内核到开发板
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+那么经过编译得到的 ``zImage`` 与设备树都可以烧录到我们的开发板中，比如我们选择 ``zImage`` 与 ``imx6ull-14x14-evk-emmc-cam-dht11.dts`` 文件替换掉前面小节中的烧录镜像与设备树，完成烧录后即可看到内核启动完成。
+
+当内核启动后，我们登陆root用户，就可以通过 ``cat /proc/version`` 命令查看内核版本：
+
+.. code:: bash
+
+    imx6ull14x14evk login: root 
+    root@imx6ull14x14evk:~# cat /proc/version 
+    Linux version 4.1.15-2.1.0-00162-gd815328d0504-dirty (embedfire @embedfire_dev) (gcc version 7.4.0 (Ubuntu/Linaro 7.4.0-1ubuntu1~18.04.1) ) #2 SMP PREEMPT Tue Aug 27 07:46:06 UTC 2019
+
+内核配置选项（部分）
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+运行 ``make ARCH=arm menuconfig``
+命令打开配置界面，根据自身需求配置即可！
+
+**触摸屏驱动：**
+
+.. code:: bash
+
+     Prompt: Goodix I2C touchscreen   
+      Location:            
+       -> Device Drivers         
+          -> Input device support  
+           -> Generic input layer (needed for keyboard, mouse, ...) (INPUT [=y]) 
+     (1)       -> Touchscreens (INPUT_TOUCHSCREEN [=y])  
+     #这个也要使能
+        [*]   Goodix touchpanel GT9xx series 
+        <*>     Goodix GT9xx touch controller auto update support  
+        <*>     Goodix GT9xx Tools for debuging     
+
+**单总线驱动：**
+
+.. code:: bash
+
+     Prompt: Dallas's 1-wire support     
+     Location:                         
+      (1) -> Device Drivers          
+      [*]   Userspace communication over connector (NEW)    
+
+**添加MPU6050的支持：**
+
+.. code:: bash
+
+    Prompt: Invensense MPU6050 devices      
+    Location:  
+      -> Device Drivers               
+        -> Industrial I/O support (IIO [=y])               
+    (1)     -> Inertial measurement units   
+              <*> Invensense MPU6050 devices   
+
+**WIFI蓝牙**
+
+.. code:: bash
+
+    Location:  
+      -> Device Drivers               
+        -> Network device support                                         
+           -> Wireless LAN
+              ->
+
+     <*>   Broadcom FullMAC wireless cards support                        
+            (/lib/firmware/bcm/AP6236/Wi-Fi/fw_bcm43436b0.bin) Firmware path     
+             (/lib/firmware/bcm/AP6236/Wi-Fi/nvram_ap6236.txt) NVRAM path    
+
+    #HCI串口配置也要选择
+        -> Device Drivers               
+        -> Network device support                                         
+           -> Wireless LAN
+              ->Bluetooth subsystem support   
+                  ->Bluetooth device drivers   
+                      <*> HCI USB driver     
+                      [*]   Broadcom protocol support  
+
+      -> Networking support (NET [=y])     
+        -> Bluetooth subsystem support (BT [=y]) 
+          -> Bluetooth device drivers    
+            <*> HCI USB driver    
+            [*]   Broadcom protocol support  
+
+**PPP点对点拨号：**
+
+所有PPP相关的都选中
+
+.. code:: bash
+
+     Prompt: PPP (point-to-point protocol) support              
+      Location:          
+      -> Device Drivers 
+        (1)   -> Network device support (NETDEVICES [=y])       
+
+**蓝牙和HCI子系统**
+
+.. code:: bash
+
+        -> Networking support (NET [=y])              
+         -> Bluetooth subsystem support (BT [=y])   
+          (1)     -> Bluetooth device drivers   
+      --- RF switch subsystem support                                         
+              [*]   RF switch input support  
+              <*>   Generic rfkill regulator driver
+              <*>   GPIO RFKILL driver 
+
+
+
+Buildroot简介
+==============
+
+Buildroot是一个简单，高效且易于使用的工具，可通过交叉编译生成嵌入式Linux系统。你可以很容易为你的目标系统构建交叉编译工具链、根文件系统、uboot以及Linux内核镜像，Buildroot可以独立的实现其中的一个或几个功能。Buildroot对于嵌入式开发人员来说是一个非常好用的工具，因为嵌入式不像x86平台（PC）一样硬件基本是统一的，嵌入式平台的硬件是根据需求进行裁剪，而不同的硬件对应的程序必然是不同，所以使用Buildroot来配置是一个非常好的选择。
+
+整个Buildroot是由 ``Makefile脚本和Kconfig配置文件`` 构成的，用户可以和编译Linux内核一样，通过config文件进行配置要编译的参数，也可以通过 ``make menuconfig`` 等界面进行修改，然后通过make命令编译出一个完整的，可以直接烧写到开发板上运行的Linux系统软件（如 ``uboot、zimage、dtb`` 已及文件系统）。
+
+更重要的是Buildroot可以很方便添加第三方的编译源码并且编译，很多工具链、源码都可以从Buildroot社区下载，用户也可以让Buildroot从本地导入源码并，这就为我们的开发带来极大的便利，当需要从网上下载时，Buildroot自动可以帮我们下载，当在本地修改后，又可以直接使用Buildroot编译，它实现了工具链下载、解压、依赖包下载编译等一系列机械化的流程，对开发者非常友好。
+
+Buildroot的官方网站是： https://buildroot.org/ ，我们可以打开官网然后下载我们需要的Buildroot工具，我们可以选择 ``buildroot-2019.02.4.tar.gz`` 这个版本的Buildroot作为我们的编译工具即可，虽然Buildroot一直在更新，但是无论是哪个版本基本都是差不多的，大家可以随意下载使用，具体见
+
+.. figure:: media/usingb002.png
+   :alt: buildroot
+
+   buildroot
+
+.. figure:: media/usingb003.png
+   :alt: buildroot
+
+   buildroot
+
+除此之外Buildroot还有非常详细的文档说明，大家可以在Documentation页面下浏览与下载，当然野火提供的资料中也会存在Buildroot的文档说明buildroot-manual.pdf文件，具体见：
+
+.. figure:: media/usingb004.png
+   :alt: buildroot
+
+   buildroot
+
+在官网下载的Buildroot是官方的，里面并没有适配野火开发板的配置文件，因此，我还是建议大家在github或者gitee平台下载我们野火适配好的Buildroot源码，然后使用它来编译文件系统即可，如果你是高手，那么请随意玩耍~
+
+github仓库地址： https://github.com/Embedfire/ebf_6ull_buildroot
+
+下载
+
+.. code:: bash
+
+    git clone https://github.com/Embedfire/ebf_6ull_buildroot.git
+
+gitee仓库地址： https://gitee.com/wildfireteam/ebf_6ull_buildroot
+
+下载
+
+.. code:: bash
+
+    git clone https://gitee.com/wildfireteam/ebf_6ull_buildroot.git
+
+Buildroot目录简介
+~~~~~~~~~~~~~~~~~~~~~~
+
+将下载好的Buildroot在虚拟机中解压后，就可以看到Buildroot的目录下存在很多文件夹如图所示，下面就简单介绍一下这些文件夹的作用。
+
+.. figure:: media/usingb005.png
+   :alt: buildroot
+
+   buildroot
+
+
+-  arch：存放CPU架构相关的配置脚本，如arm、mips、x86等，这些与CPU相关的脚本在Buildroot制作编译工具链、编译uboot时起关键作用。
+
+-  board：针对不同硬件平台的特有配置文件、脚本与补丁。
+
+-  boot：存放的是引导系统相关的配置文件。
+
+-  configs：这里存放的是一些针对不同硬件平台的特有配置文件合集（xxxx_deconfig），我们在开发过程中为自己开发板配置的文件也可以放入该目录下，比如野火提供的imx6ull开发板的配置文件ebf6ull_s1_pro_defconfig就可以放入该目录下。
+
+-  docs：存放相关的参考文档。
+
+-  fs：存放各种文件系统的配置相关的文件，比如ext2、yassf2等。
+
+-  linux：存放着Linux 内核的自动构建脚本。
+
+-  package：该目录下存放着应用软件包的配置文件，每个应用软件包的配置文件有Config.in和xxxx.mk以及一些补丁文件，其中xxxx.mk文件可以去下载对应名字的应用软件包，这个文件其实就是Makefile脚本的自动构建脚本，根据文件中的描述去下载。
+
+-  support：一些Buildroot支持相关的配置文件，比如docker、kconfig、下载辅助工具、补丁等。
+
+-  system：这里就是根目录的主要骨架，以及启动的初始化配置文件，当制作根目录时就是将此处的文件拷贝到output目录下，然后再下载安装工具链的动态库和用户勾选的package。
+
+-  toolchain：该目录主要存放编译交叉工具的配置文件。
+
+-  utils：存放Buildroot一些通用工具。
+
+-  dl：虽然一开始并没有dl（download）目录，但是在开始使用Buildroot后，会自动生成一个dl目录，它主要用于存放Buildroot工具下载的内容，因为Buildroot是一系列工具的管理集合，它本身并不存在这些编译工具，所以在使用时它自动会下载需要的工具，比如交叉编译器、依赖的库、以及一些软件源码包等（以压缩包的形式存放，Buildroot在使用时会自动解压），都会放在dl目录下。
+
+-  output：虽然一开始Buildroot也并没有output目录，但是在开始使用Buildroot后，就会自动生成output目录，它是编译出来的输出文件夹，里面存放着解压后的各种软件包编译完后的现场。同时output目录下还有各种文件夹，如host文件夹是由各类源码编译后在主机上运行工具的安装目录，如arm-linux-gcc就是安装在这里；build文件夹是所有源码包解压出来的文件存放地和编译的发生地；images文件夹则是在我们编译完成后存放uboot、内核镜像、设备树以及文件系统等结果的。
+
+    提示：对于其他的未列出来的目录，暂时不用去理会。
+
+编译前的准备
+~~~~~~~~~~~~~~~~~~~~~~
+
+Buildroot的使用是需要依赖源码包的，它会去寻找要编译的源码包，我们可以选择网络上的的源码包也可以选择本地的源码包，那么在这一章中我们就只选择本地的kernel与uboot源码包，从前面的章节我们也编译了kernel与uboot，此处对这些源码包就不再重复赘述，但是有一点读者必须要注意，更新了本地的源码包要用git记录，否则Buildroot不知道你已经更新过的。
+
+根据Buildroot官方文档说明，Buildroot会强制性使用一些工具包，如所示，这是为了Buildroot能正常编译，因此我们在使用前尽量查看一下当前系统的环境下是否存在这些软件包，或者可以直接通过sudo
+apt-get install命令去下载它们：
+
+.. code:: bash
+
+    sudo apt-get install -y sed make binutils build-essential gcc g++ bash patch gzip bzip2 perl tar cpio python unzip rsync file bc wget g++-multilib
+
+.. figure:: media/usingb006.png
+   :alt: buildroot
+
+   buildroot
+
+    提示：此处使用ubuntu18.04作为测试。
+
+选择配置文件
+~~~~~~~~~~~~~~~~~~~~~~
+
+Buildroot为了方便用户使用，在configs目录下提前配置好了很多平台的配置，我们可以在这里找一个与我们开发板最符合的配置文件，然后根据文件中的配置来修改出我们开发板的配置文件即可。当然野火是有提供默认的配置文件：
+
+**1.带Qt Demo的配置：**
+
+.. code:: bash
+
+    imx6ull_ebf_pro_defconfig
+
+**2.最小的完整镜像配置（文件系统6M左右）：**
+
+.. code:: bash
+
+    imx6ull_ebf_minimal_defconfig
+
+**3.pico文件系统配置（不编译uboot与内核，文件系统5M左右）：**
+
+.. code:: bash
+
+    imx6ull_ebf_pico_defconfig
+
+    ps: 以上配置选择其中之一即可
+
+这些配置文件就是根据configs目录下的 ``imx6ulevk_defconfig`` 修改，适配我们野火的imx6ull开发板。
+
+比如我们直接选择 ``imx6ull_ebf_pro_defconfig`` 作为我们编译的配置文件，那么可以运行以下命令将其写入到 ``.config`` 文件：
+
+.. code:: bash
+
+    make imx6ull_ebf_pro_defconfig
+
+    # 输出
+    #
+    # configuration written to /home/jiejie/ebf_6ull_buildroot/.config
+    #
+
+很显然这操作过程与我们编译内核的过程是一样的，都是将配置文件的信息写入当前目录下的
+.config文件中，然后通过make menuconfig命令进行配置：
+
+.. figure:: media/usingb007.png
+   :alt: buildroot
+
+   buildroot
+
+通过配置界面就可以很容易找的自己要配置的选项，我们可以来看看这些配置的主要功能：
+-
+``Target options  --->`` ：目标单板架构配置，在这里主要是选择要编译的平台架构，如cortex-A7；选择CPU的大小端模式，选择支持浮点等等，具体配置如下：
+
+.. figure:: media/usingb008.png
+   :alt: buildroot
+
+   buildroot
+
+-  ``Build options  --->`` ：编译相关的配置，主要是一些编译时用到的选项，比如设置当前配置的保存位置（Location
+   to save buildroot
+   config），根据自己的路径设置即可，设置dl的路径（下载代码包使用的路径：$(TOPDIR)/dl），多个线程编译的线程数量（如果设置为0则自动选择多个线程编译），是否使能编译器缓冲区；设置下载镜像Mirrors
+   and Download
+   locations：一般来说Buildroot会默认从国外的网站下载镜像，而在国内下载则很慢，我们可以修改镜像源：
+
+.. code:: bash
+
+    #设置下载镜像Mirrors and Download locations：
+    内核镜像源：https://mirror.bjtu.edu.cn/kernel 
+    GNU镜像源：https://mirrors.tuna.tsinghua.edu.cn/gnu/ 
+    清华镜像站汇总：https://mirrors.tuna.tsinghua.edu.cn/
+
+    # 提示：用清华镜像站会找不到内核。 
+    北京交通大学镜像站：https://mirror.bjtu.edu.cn/ 
+    中国科学技术大学镜像站：http://mirrors.ustc.edu.cn/
+
+Build options具体配置如下:
+
+.. figure:: media/usingb009.png
+   :alt: buildroot
+
+   buildroot
+
+.. figure:: media/usingb010.png
+   :alt: buildroot
+
+   buildroot
+
+    如后期有改变则以配置文件为主，建议尽量不改动已发布的配置文件。
+
+-  ``Toolchain  --->`` ：工具链选项主要是让用户选择合适自己的交叉编译工具链，可以选择Buildroot提供的工具链（内部工具链 ``Buildroot toolchain`` ），也可以指定其他非Buildroot提供的工具链（外部工具链 ``External toolchain`` ），我们默认选择外部提供的工具链： ``gcc-linaro-5.3.1-2016.05-x86_64_arm-linux-gnueabihf`` ，C库可以选择uClibc-ng,、glibc
+   和musl，我们选择glibc，还有选择内核头文件版本（要求比目标内核版本新）、是否使能宽字符（WCHAR）支持（如果需要支持Python则需要使能）、选择gcc编译器版本、是否使能c++等，具体配置如下：
+
+.. figure:: media/usingb011.png
+   :alt: buildroot
+
+   buildroot
+
+-  ``System configuration  --->`` ：系统相关的配置，比如配置系统主机名，它的主要作用是：在一个局域网中，每台机器都有一个主机名，用于主机与主机之间的便于区分，就可以为每台机器设置主机名，以便于以容易记忆的方法来相互访问；设置登陆界面的欢迎信息。选择密码的加密方式，我们可以选择SHA256加密算法（sha-25），设置root登陆的密码、设置默认的命令行终端（我们默认选择bash）、设置默认的登陆串口（开发板连接到电脑的输入/输出）、设置系统默认的环境变量（PATH）、以及选择构建系统镜像版本，根文件系统覆盖（野火的配置中就将一些脚本与相关内容放到 ``board/embedfire/ebf-imx6ull-pro/rootfs-overlay`` 目录下，在制作成文件系统时将这些文件添加到文件系统中）、以及一些运行的脚本（buildroot官方为imx6ull制作的打包脚本： ``board/freescale/common/imx/post-image.sh`` ）等，具体配置如下：
+
+.. figure:: media/usingb012.png
+   :alt: buildroot
+
+   buildroot
+
+-  ``Kernel  --->`` ：linux内核相关的配置，用户可以选择要编译的内核版本及源码，可以从网上下载（比如野火的配置文件就是从gitee仓库下载最新的内核源码），除此之外也可以从本地导入（其实对Buildroot来说也算是下载，因为这些文件都会被下载到dl目录下），还可以指定编译内核的默认配置文件（ ``imx6_v7_ebf，即imx6_v7_ebf_defconfig`` ，但此处的配置文件不需要后缀名defconfig）、内核二进制文件格式、选择是否编译设备树与指定编译的设备树（DTB）、以及其他的一些扩展。具体配置如下：
+
+指定内核源码编译的设备树如下：
+
+-  imx6ull-14x14-evk-btwifi.dtb
+-  imx6ull-14x14-evk.dtb
+-  imx6ull-14x14-evk-emmc-43.dtb
+-  imx6ull-14x14-evk-emmc-cam-dht11.dtb
+-  imx6ull-14x14-evk-emmc.dtb
+-  imx6ull-14x14-evk-emmc-hdmi.dtb
+-  imx6ull-14x14-evk-emmc-wifi.dtb
+-  imx6ull-14x14-evk-gpmi-weim-43.dtb
+-  imx6ull-14x14-evk-gpmi-weim-cam-dht11.dtb
+-  imx6ull-14x14-evk-gpmi-weim-hdmi.dtb
+-  imx6ull-14x14-evk-gpmi-weim-wifi.dtb
+
+.. figure:: media/usingb013.png
+   :alt: buildroot
+
+   buildroot
+
+-  ``Target packages  --->`` ：这个是Buildroot的包管理相关的配置选项，读者可以从这里选择自己需要的软件包，Buildroot
+   提供了海量软件包可选，只需在配置界面选中所需要的软件包，交叉编译后即可使用。比如添加音视频应用相关的软件包、添加压缩和解压缩相关的软件包、添加字体、游戏、图形库（QT）、语言和脚本（Python、PHP等）、网络（蓝牙、wifi、http工具包）等软件包，在我们开发板就添加了支持QT与Python的软件包，因此可以在开发板中使用QT与Python，由于配置较多，就不再截图，根据配置文件查看即可。注意：Busybox是必选的。
+
+    假设我们系统中缺失一些库，那么可以在这里选择有没有对应的软件包，如果没有则需要自己手动制作了。
+
+-  ``Filesystem images  --->`` ：文件系统镜像配置。可以选择生成的文件系统镜像类型
+   ，如 ``tar、cpio、ext2/3/4、 jffs2、 yaffs2 和 ubifs``
+   等。文件系统镜像可能会非常大，具体取决于你选择的文件系统类型、软件包的数量以及是否配置的可用空间等，具体配置如下：
+
+.. figure:: media/usingb014.png
+   :alt: buildroot
+
+   buildroot
+
+-  ``Bootloaders  --->`` ：Bootloaders相关的配置，在这个配置选项中，读者可以选择要编译的Bootloaders
+   引导程序（如 ``grub2、ts4800-mbrboot、uboot`` 等，我们默认选择uboot），指定uboot的名字、下载的位置（可以是从网上下载，写入正确的URL即可；也可以从本地导入，写入本地路径即可），指定uboot的版本，我们默认使用野火的uboot仓库，使用最新发布的uboot版本，具体配置如下：
+
+.. figure:: media/usingb015.png
+   :alt: buildroot
+
+   buildroot
+
+-  ``Host utilities  --->`` ：主机通用配置，使用默认配置即可。
+
+-  ``Legacy config options  --->`` ：使用默认配置即可。
+
+当配置完成，退出后会发现所有的配置都被写入当前目录下的 .config文件：
+
+.. code:: bash
+
+    configuration written to /home/jiejie/ebf_6ull_buildroot/.config
+
+    *** End of the configuration.
+    *** Execute 'make' to start the build or try 'make help'.
+
+如果你想将这次配置的文件保存起来，那么可以通过以下命令保存：
+
+::
+
+     make savedefconfig 
+
+然后我们可以执行 ``make`` 命令进行编译操作， ``make`` 命令通常会执行以下步骤：
+
+1. 根据配置需要下载源文件
+
+2. 配置、构建和安装交叉编译工具链，或者只是导入外部工具链
+
+3. 配置、构建和安装选定的目标软件包
+
+4. 则构建内核镜像
+
+5. 构建引导加载程序镜像
+
+6. 以所选格式创建根文件系统
+
+执行 ``make`` 命令后就等待它编译完成即可，在编译完成后可以在 ``output/images`` 目录下找到编译产生的镜像，具体见
+
+.. figure:: media/usingb016.png
+   :alt: buildroot
+
+   buildroot
+
+编译生成的设备树、内核、文件系统等都可以烧录到野火imx6ull开发板上，具体的烧录过程在烧录测试小节中已经讲解，此处就不再重复赘述。
+
+Buildroot其他分析
+~~~~~~~~~~~~~~~~~~~~~~
+
+正如前面所说的Buildroot是一个非常强大的工具，它可以随意依赖第三方的库以及工具，能快速构建我们需要的内容，如果你想了解一下Buildroot编译生成的内容的一些时间、依赖、大小等情况，通过代码肯定是不方便，Buildroot还提供可视化分析的工具，我们只需一句命令即可使用它们。
+
+当然，按照官方文档的说明，需要在主机上安装必须的软件包python-matplotlib
+和python-numpy，我们可以通过以下命令进行安装：
+
+.. code:: bash
+
+    sudo apt-get install -y python-matplotlib python-numpy
+
+Buildroot的工作之一是了解包之间的依赖关系，并确保它们以正确的顺序构建。
+这些依赖关系有时可能非常复杂，对于给定的系统，通常不容易理解为什么这样或那样的包被Buildroot引入并且成功构建。为了帮助理用户解依赖关系，从而更好地理解嵌入式Linux系统中不同组件的作用，Buildroot能够生成依赖关系图，通过make
+graph-depends命令即可生成对应的依赖文件（默认是PDF格式），具体情况如下：
+
+.. code:: bash
+
+    命令
+    make graph-depends
+
+    最后输出提示：
+    -o /home/ embedfire /buildroot/buildroot-2019.02.4/output/graphs/graph-depends.pdf  /home/embedfire/buildroot/buildroot-2019.02.4/output/graphs/graph-depends.dot
+
+当然，Buildroot还能生成关于编译时间与编译占用资源大小的分析图，只需要通过make
+graph-build与make graph-size命令生成即可，具体见（已删减输出信息）：
+
+.. code:: bash
+
+    命令
+    make graph-build
+
+    make graph-size
+
+然后可以看到在output/graphs目录下多了一些pdf文件，这些就是Buildroot生成的可视化分析文件，可以直接打开他们，具体见：
+
+.. figure:: media/usingb017.png
+   :alt: buildroot
+
+   buildroot
+.. figure:: media/usingb018.png
+   :alt: buildroot
+
+   buildroot
+.. figure:: media/usingb019.png
+   :alt: buildroot
+
+   buildroot
+
+其他的一些问题
+~~~~~~~~~~~~~~~~~~~~~~
+
+由于buildroot会在国外的网站下载很多东西，所以在下载时会很慢很慢，有可能出现下载失败的情况，那么可以根据日志信息手动去下载对应的软件包。
+
+如果在生成镜像时失败，可以尝试清除一下install状态，然后重新编译。
+
+.. code:: bash
+
+    ./clear.sh 
+
+还有需要注意的是：由于本项目是 ``Buildroot`` 使用
+``arm-linux-gnueabihf-5.3.1``
+编译工具链编译的，与单独编译的内核镜像使用的编译器版本不一致，可能会导致某些内核模块无法加载，因此如果有必要的话，将 ``output/images/`` 目录下的内核镜像
+``zImage`` 替换掉原本的内核镜像！同理，设备树亦是如此！
+
+
+制作根文件系统
+====================
+
+在介绍制作文件系统之前，我们先来看一下Linux是如何存储数据的。一般情况下，字符设备以串行方式存储和获取数据，串口是最典型的字符设备；而块设备会一次存取或者获取大小相同的一块区域内的数据。例如，一个硬
+盘控制器可以向物理存储介质上指定可寻址地址，一次传送或接收512字节的数据，文件系统正是建立在块设备之上的。
+
+文件系统是存在于一个物理设备的逻辑分区之上的。分区就是对一个物理介质（磁盘、闪存）的逻辑划分，该物理介质上的数据在给定分区类型上按照特定的规则进行组织，物理设备可以只有一个独立分区包含所有可用空间，也可以被划分为多个分区以满足特定需要，就好比我们电脑的磁盘，划分为多个分区以用于不同的需求。
+
+简单了解了文件系统的概念，那么我们就动手制作一个文件系统。
+
+buildroot构建根文件系统
+~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+文件系统通常要包含很多第三方软件，比如busybox，tslib，qt，vim，交叉编译工具等，为了避免繁杂的移植工作，buildroot应运而生。用户可以直接通过make
+menuconfig配置自己需要的功能，把不需要的功能去掉，再执行make指令编译，buildroot就会自动从指定的服务器上下载源码包，自动编译，自动搭建成我们所需要的嵌入式根文件系统。
+
+buildroot的文件系统（rootfs）构建流程有一个框架，有些部分是buildroot本身就集成的，但还是有些细节需要自己来实现，我们需要按照格式写脚本，提供必要的构建细节，并且配置整个系统，总之，rootfs是Buildroot中最为复杂的部分。
+
+一般来说，buildroot构建文件系统的运作过程如下：
+
+1. buildroot将system/skeleton/目录下的内容拷贝到output/target目录下下作为rootfs的模板。
+
+2. 将output/staging/目录下的工具链中动态库拷贝到output/target/对应的目录下。
+
+3. 分别编译每一个应用的package，并将生成的动态库和bin文件install到output/target/对应的目录下。
+
+4. 将package/initscripts/目录下的系统启动脚本install到output/target/对应的目录下。
+
+5. 构建fakeroot环境，在fakeroot环境下修改output/target/中对应的目录文件权限，制作dev节点，并根据用户的配置制作出rootfs 镜像。
+
+fakeroot是一个主机上使用的软件包，它会被buildroot下载编译，用于为构建rootfs提供一个虚拟的root权限环境，只有在root权限下，才能把output/target/中的目录和文件变成root用户，并创建dev节点。有了fakeroot环境，系统构建者无需获取主机的root权限，
+也能在fakeroot下把文件改为root用户，并制作root方式。
+
+uClibc与glibc的差异
+~~~~~~~~~~~~~~~~~~~~~~~
+
+glibc和libc都是Linux下的C函数库，libc是Linux下的ANSI C的函数库；glibc是Linux下的GUN C的函数库；GNU C是一种ANSI C的扩展实现。ANSI
+C是基本的C语言函数库，包含了C语言最基本的库函数。在写程序时，需要用到很多c语言的库函数，这些所有的库函数整合起来，就是对应的C语言（标准）函数库。
+
+目前在普通GNU/Linux系统中所用的C语言标准库，叫做glibc。它的功能很全，函数很多，但是就是因为代码太多，编译出来的函数库的大小也很大，占用的资源也很多，可以简单地认为glibc就是为了实现完整功能设计的。
+
+由于在嵌入式系统中，也需要C语言写代码实现特定功能，因此需要用到C语言函数库，但是由于嵌入式系统中，一般资源比较有限，所以不适合直接使用太占用资源的glibc。uClibc
+是一个面向嵌入式Linux系统的小型的C标准库，最初uClibc是为了支持uClinux而开发，这是一个不需要内存管理单元（MMU）的Linux版本。uClibc比一般用于Linux发行版的C库GNU C Library (glibc)要小得多，
+因此uClibc专注于嵌入式Linux，除此之外uClibc比glibc更可配置，这意味着开发人员可以根据功能与空间需求进行裁剪。
+
+简单总结以下几点：
+
+1. uClibc比glibc占用的资源小，虽然uClibc和glibc在已有的接口上是兼容的，而且采用uClibc编译应用程序比采用glibc编译应用程序要更方便，但是uClibc并没有包括glibc中的所有接口实现，因此有些应用可能在uClibc中不能编译。
+
+2. uClibc在可配置性上比glibc要好。
+
+提示：关于uClibc与glibc更多的差异比较信息请看 http://www.etalabs.net/compare_libcs.html 。
+
+使用buildroot制作自己需要的文件系统
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+关于buildroot的简单实用也在第32章 讲解过了，此处就讲解一下关于文件系统的内容即可。（注意：必须先按照第32章 的内容配置好内核及uboot的编译内容，否则无法从SD卡启动系统）。
+
+首先运行以下命令进入配置选项：
+
+命令
+
+make menuconfig
+
+找到System configuration(系统配置)选项，进入该选项中，如图 33‑1所示。
+
+|buildi002|
+
+图 33‑1 System configuration(系统配置)
+
+我们可以简单介绍一下这个选项的中的部分参数及其意义（ []内容为设置的值）：
+
+-  Root FS skeleton (default target skeleton) ： 根文件系统框架 [默认目标框架]
+
+-  (buildroot) System hostname ：系统主机名字(自取任意) [buildroot]
+
+-  (Welcome to ixm6ull Buildroot!) System banner：系统开机提示 [Welcome to ixm6ull Buildroot!]
+
+-  Passwords encoding (sha-256)：密码编码 [sha-256格式编码]
+
+-  Init system (busybox) --->：初始化系统方案 [busybox]
+
+-  /dev management (Dynamic using devtmpfs only) ：dev管理方案 [Dynamic using devtmpfs only]
+
+-  (system/device_table.txt) Path to the permission tables ：权限表路径
+
+-  [ ] support extended attributes in device tables：支持设备表中的扩展属性
+
+-  [ ] Use symlinks to /usr for /bin, /sbin and /lib：是否将/bin,/sbin,/lib链接到/usr
+
+-  [*] Enable root login with password：使能root登陆密码
+
+-  () Root password：设置root密码
+
+-  /bin/sh (bash) ：选择shell类型 [bash]
+
+-  [*] Run a getty (login prompt) after boot：启动后运行getty(登录提示)
+
+-  [*] remount root filesystem read-write during boot ：在引导期间安装根文件系统支持读和写
+
+-  (eth0) Network interface to configure through DHCP：设置DHCP配置的网络接口 [eth0]
+
+-  (/bin:/sbin:/usr/bin:/usr/sbin) Set the system's default PATH：设置系统的默认路径
+
+-  [*] Purge unwanted locales：清除不需要的区域设置
+
+-  (C en_US) Locales to keep：要保留的语言环境
+
+-  () Generate locale data：生成区域设置数据
+
+-  [ ] Enable Native Language Support (NLS) ：启用本地语言支持（NLS）
+
+-  -*- Install timezone info ：安装时区信息
+
+-  (default) timezone list：时区清单 [典型]
+
+-  (Etc/UTC) default local time ：用户表的路径
+
+-  () Path to the users tables
+
+-  () Root filesystem overlay directories：根文件系统覆盖目录
+
+-  () Custom scripts to run before creating filesystem images：在创建文件系统映像之前运行的自定义脚本
+
+-  () Custom scripts to run inside the fakeroot environment：自定义脚本在fakeroot(模拟root权限)环境中运行
+
+-  (board/……) Custom scripts to run after creating filesystem images ：创建文件系统映像后运行的自定义脚本
+
+-  () Extra arguments passed to custom scripts：传递给自定义脚本的额外参数
+
+在这里就重点提一下几点配置：
+
+1. Root FS skeleton：我们建议选择默认的根文件系统框架，因为默认的框架是非常小的，可以适应绝大部分的场合，当然，占用资源小也代表功能仅有一点点，读者可以自己往文件系统添加需要的功能，这是可以的。除此之外读者也可以选择自己的根文件系统框架（custom target skeleton）。
+
+2. Init system：初始化系统方案，目前buildroot中提供2种方案，一种是BusyBox：系统的init程序将在启动时读取/etc/inittab文件，以了解该做什么，默认inittab存储在./package/busybox/inittab中；inittab除了安装几个重要的文件系统之外
+   ，还要启动/etc/init.d/rcS中的shell脚本，并启动一个getty程序(提供一个登录提示)。另一种是systemV，使用传统sysvinit程序，之前大多数台式机Linux发行版都使用该方案，现在有些变为了Upstart或Systemd，在构建文件系统的时候会在/ect目录下会生成in
+   it.d、rc0.d、rc1.d、rc2.d、rc3.d、rc4.d、rc5.d、rc6.d、rc.loacl等目录和脚本文件，init.d目录下包含的是真正的脚本。
+
+3. /dev management ：/dev设备文件的管理方式，可选选项有四个：
+
+Static using device table: 使用静态的设备表，/dev将根据system/device_table _dev.txt的内容创建设备，进入系统添加或删除设备时，无法自动更新；
+
+Dynamic using devtmpfs only:在系统启动过程中，会动态生成/dev文件，进入系统添加或删除设备时，无法自动更新；
+
+Dynamic using devtmpfs + mdev:在前面devtmpfs的基础上加入mdev用户空间实用程序，进入系统添加或删除设备时，可以自动更新，自动创建规则在/etc/mdev.conf;
+
+Dynamic using devtmpfs + eudev:在前面devtmpfs的基础上加入eudev用户空间守护程序，eudev是udev的独立版本，是Systemd的一部分，提供更多的功能也更占用资源；
+
+4. /bin/sh (bash)：选择shell类型，一般选择bash即可，用户的体验会很好。除了bash外，还有很多shell工具，比如这里可选busybox自带的shell、小巧但功能很少的dash、高效紧凑的mksh、功能强大体积也稍大的zsh。
+
+5. Root filesystem overlay directories：根文件覆盖目录，如果你想将某些文件添加到文件系统中，那么可以按照根文件的目录框架进行添加到对应的路径中，在文件系统构建的时候，会将对应的文件添加到文件系统中，如果出现相同的文件则覆盖。
+
+我们还需要配置一下Filesystem images(文件系统)选项，具体见图 33‑2 。
+
+|buildi003|
+
+图 33‑2 Filesystem images(文件系统)
+
+这些配置的含义如下：
+
+-  [ ] axfs root filesystem：XFS格式根文件系统
+
+-  [ ] btrfs root filesystem ：btrfs格式根文件系统
+
+-  [ ] cloop root filesystem for the target device：clop方式压缩根文件系统
+
+-  [ ] cpio the root filesystem (for use as an initial RAM filesystem) ：cpio方式压缩根文件系统(用作初始RAM文件系统)
+
+-  [ ] cramfs root filesystem：cramf格式根文件系统
+
+-  [*] ext2/3/4 root filesystem ：ext2/3/4格式根文件系统
+
+-  ext2/3/4 variant (ext4) ：ext4格式根文件系统
+
+-  () filesystem label ：文件系统标签
+
+-  (200M) exact size ：根文件系统空间大小[200M]
+
+-  (0) exact number of inodes (leave at 0 for auto calculation) ：确切的inode数(从0开始自动计算)
+
+-  (5) reserved blocks percentage：保留块百分比 (保留的供root使用,默认5%)
+
+-  (-O ^64bit) additional mke2fs options ：额外的mke2fs选项 [禁用64位文件系统]
+
+-  Compression method (no compression) ：压缩方式 [无压缩]
+
+-  [ ] f2fs root filesystem ：f2fs格式根文件系统
+
+-  [ ] initial RAM filesystem linked into linux kernel：初始RAM文件系统链接到Linux内核
+
+-  [ ] jffs2 root filesystem：jffs2格式根文件系统
+
+-  [ ] romfs root filesystem：romfs格式根文件系统
+
+-  [ ] squashfs root filesystem ：squashfs格式根文件系统
+
+-  [*] tar the root filesystem：tar压缩格式根文件系统
+
+-  Compression method (no compression) ：压缩方式 [无压缩]
+
+-  () other random options to pass to tar：传递给tar的其他选项
+
+-  [ ] ubi image containing an ubifs root filesystem：ubifs格式根文件系统包含ubi镜像
+
+-  [ ] ubifs root filesystem ：ubifs格式根文件系统
+
+-  [ ] yaffs2 root filesystem：yaffs2格式根文件系统
+
+我们就简单设置一下文件系统的大小（256M），以及根文件系统的格式（tar压缩格式）即可。
+
+当配置完毕后，我们可以选择对应的软件包添加到我们的系统中，比如Python3等，这里就不再重复赘述。然后使用make命令进行编译，就会生成对应的文件系统了，生成的镜像文件在output/images/目录下。
+
+.. |buildi002| image:: media/building_rootfs002.png
+   :width: 5.76806in
+   :height: 4.2879in
+.. |buildi003| image:: media/building_rootfs003.png
+   :width: 4.76155in
+   :height: 5.05224in
+.. |buildi004| image:: media/building_rootfs004.png
+   :width: 5.76806in
+   :height: 4.62276in
+.. |buildi005| image:: media/building_rootfs005.png
+   :width: 5.76806in
+   :height: 3.46306in
diff --git a/documentation/building_image/building_debian.rst b/documentation/building_image/building_debian.rst
new file mode 100644
index 0000000000000000000000000000000000000000..471d08329b5542b8ea201769dbd8ccb187d307fb
--- /dev/null
+++ b/documentation/building_image/building_debian.rst
@@ -0,0 +1,365 @@
+.. vim: syntax=rst
+
+构建野火Debian系统固件
+------------------------
+
+为什么要构建Debian系统固件
+============================
+
+前面介绍了NXP官方的固件有稳定可靠的优点，适合大部分的产品使用，但这是从产品角度来看的。
+对于Linux学习者来说，原厂固件因为使用的是较老版本的linux内核、Uboot版本，
+它与目前的代码的架构和系统特性已经发生了一些变化。再去学习研究时，就显得比较脱节。
+毕竟学习时间有限，不可能把所有新旧版本的内核、uboot重新学习一遍。
+
+目前野火移植了较新版本的uboot(2019_04) ,kernel(4.19.71)，为的就是减少重复学习成本，
+也更加锻炼学习者的能力。而且出于对初学者好学易用的目的，
+根文件系统将会使用Debian，它的第三方软件包繁多，安装简单，
+大家熟悉的Ubuntu就是基于Debian发展而来。
+
+
+编译2019.04版本uboot
+============================
+
+野火移植2019.04版本uboot，在其中完善了对内核设备树插件的支持，提高了系统的扩展性和可维护性。
+
+1、下载野火2019版本uboot，代码已经托管在github以及gitee上，直接执行以下命令进行下载即可:
+
+.. code-block:: sh
+   :emphasize-lines: 1
+   :linenos:
+
+   git clone https://github.com/Embedfire/ebf-buster-uboot.git
+   或者
+   git clone https://gitee.com/wildfireteam/ebf-buster-uboot.git
+
+2、先在系统执行以下命令，安装必要的环境工具，再进行uboot的编译。
+
+.. code-block:: sh
+   :emphasize-lines: 1
+   :linenos:
+
+   sudo apt install make gcc-arm-linux-gnueabihf gcc bison flex libssl-dev dpkg-dev lzop
+
+
+3、在项目文件夹目录下使用root权限执行编译脚本compile_uboot.sh
+
+.. code-block:: sh
+   :emphasize-lines: 1
+   :linenos:
+
+   sudo ./compile_uboot.sh
+
+编译结束后，会在当前文件夹路径下生成u-boot-dtb.imx文件，这就是我们需要的uboot镜像,
+该uboot镜像需要存放到下面介绍的ebf-image-builder项目的uboot目录中，来进行系统固件的生成。
+
+编译4.19.71版本内核
+=========================
+
+1、下载野火4.19.71版本内核，代码已经托管在github以及gitee上，直接执行以下命令进行下载即可:
+
+.. code-block:: sh
+   :emphasize-lines: 1
+   :linenos:
+
+   git clone https://github.com/Embedfire/ebf-buster-linux.git
+   或者
+   git clone https://gitee.com/wildfireteam/ebf-buster-linux.git
+
+2、先在系统执行以下命令，安装必要的环境工具，再进行内核的编译。
+
+.. code-block:: sh
+   :emphasize-lines: 1
+   :linenos:
+
+   sudo apt install make gcc-arm-linux-gnueabihf gcc bison flex libssl-dev dpkg-dev lzop
+
+3、在项目文件夹目录下使用root权限执行编译脚本make_deb.sh
+
+.. code-block:: sh
+   :emphasize-lines: 1
+   :linenos:
+
+   sudo ./make_deb.sh
+
+编译结束后，会在/home/pi路径下生成linux-image-4.19.71-imx-r1_1stable_armhf.deb，这就是4.19.71版本linux内核的安装包。
+该内核安装包需要存放到下面介绍的ebf-image-builder项目的Kernel目录中，来进行系统固件的生成。
+
+制作Debian系统镜像
+=============================
+
+ebf-image-builder简介
+~~~~~~~~~~~~~~~~~~~~~~~
+
+该项目移植自BeagleBone公司的image-builder项目，主要用于构建debian系统镜像。它的源码开放，
+主要由shell脚本和配置文件构成，用户可以灵活高效地修改debian文件系统的配置，
+还能根据实际项目需要在文件系统中预装某些应用软件。
+
+源码地址: https://github.com/Embedfire/ebf-image-builder
+
+关于Debian系统
+~~~~~~~~~~~~~~
+
+Linux有非常多的发行版本，Debian就是最早的Linux发行版本之一。大家比较熟悉的Ubuntu就是基于Debian发展而来，
+相比其他Linux发型版本，Debian主要有以下几个方面的优点:
+
+1.  稳定
+
+Debian的发布版本通常测试完善，发行周期较长，它通常维护着三个版本:"稳定版(stable)"、"测试版(testing)"、
+"不稳定版(unstable)"，对每个稳定发行版本，用户可以得到三年的完整支持以及额外两年的长期支持。
+debian目前在很多企业用户中使用，它的稳定性和可靠性是经过市场长期验证的。
+
+2.  软件包管理程序简单易用
+
+熟悉Ubuntu的人应该知道，Ubuntu是用dpkg工具来进行软件包的管理，关于软件的安装、卸载、升级都可以用dpkg指令完成，
+dpkg指令功能非常强大，但是也比较复杂。因而后来基于dpkg衍生出来了apt工具，可以通过apt install、apt remove、
+等指令就能轻松安装、卸载软件。在这方面，Debian与Ubuntu的机制是完全一样的。
+
+3.  软件包丰富
+
+Debian经过这么多年的发展，开源社区已经积累了数以万计的应用程序，从文档编辑、到电子商务、到游戏娱乐、到软件开发，
+全面提供即安装即使用的体验。免去自己编译源代码的诸多麻烦，而且用apt upgrade就能轻松升级到最新版本的软件。
+
+4.  良好的系统安全
+
+Debian自由软件社区非常注重在软件发布中快速地修复安全问题。通常没几天就会有修复过的软件被上传。因为开放源代码
+所以 Debian 的安全性是可以被用户和开发者客观评估的。这有利于防止潜在的安全问题被引入到Debian系统中。
+
+
+
+关于image-builder项目
+~~~~~~~~~~~~~~~~~~~~~
+
+项目起源
+""""""""
+
+BeagleBoard.org是一家非盈利公司，致力于在嵌入式计算 领域提供开源硬件和软件，并且重点关注教育行业,
+BeagleBoneBlack是该公司最受欢迎的主板。image-builder项目就是为BeagleBoneBlack之类的开发板构建debian系统镜像的开源项目。
+
+源码地址: https://github.com/beagleboard/image-builder。
+
+项目原理
+"""""""""
+
+image-builder项目基于qemu和debootstrap等工具来生成和定制arm架构的debian文件系统。其中，qemu是一个开源的模拟器项目，
+在GNU/Linux平台上使用广泛，可用于模拟各种不同架构的处理器。而debootstrap是Debian官方提供的，
+适用于生成不同架构、不同版本的debian文件系统。
+
+.. image:: media/image-builder_analyze.png
+   :align: center
+   :alt: image-builder项目分析
+
+如上图所示:
+在使用debootstrap工具生成debian文件系统后，然后qemu使用新构建的debian文件系统作为文件系统，
+在qemu模拟arm架构的处理器并启动后，就可以用apt install命令预装各种应用软件，
+linux内核和设备树都是在这个阶段中安装更新的。安装完毕后，使用dd命令把得到的文件系统和u-boot一起打包到img文件中，
+即可生成用于sd卡烧录的debian系统镜像。
+
+ebf-image-builde目录分析
+~~~~~~~~~~~~~~~~~~~~~
+
+1.  使用git克隆项目镜像
+
+.. code-block:: sh
+   :emphasize-lines: 1
+   :linenos:
+
+    git clone https://github.com/Embedfire/ebf-image-builder.git
+    或者
+    git clone https://gitee.com/wildfireteam/ebf-image-builder.git
+
+出现下图提示表示克隆完成
+
+.. image:: media/git_clone_finish.png
+   :align: center
+   :alt: git克隆完成
+
+2.  进入下载好的文件目录，使用tree命令查看文件夹目录
+
+.. code-block:: sh
+   :emphasize-lines: 2
+   :linenos:
+
+   cd ebf-image-builder
+   tree -L 1
+
+可以看到ebf-image-builde项目的目录结构，如下图所示:
+
+.. image:: media/ebf-image-builder_list.png
+   :align: center
+   :alt: ebf-image-builde目录
+
+其中:
+
+- configs目录:主要是Debian文件系统的一些配置项，主要有:预安装软件列表、镜像源地址等。
+- docs目录:主要是代理使用说明和debootstrap使用说明。
+- publish目录:这个目录下存放着编译debian固件的起始脚本，是整个项目的编译入口。
+- scripts目录:存放了一些执行特殊功能的脚本，在编译过程中会被调用。
+- target目录:这里面放置的内容比较杂散，有启动参数的说明文档、systemd的启动服务和deb镜像源的密钥等等。
+- tools目录:主要是打包脚本，完成把文件系统和uboot打包成img镜像的功能。
+- Kernel目录:存放的是前面编译出来的内核安装包(linux-image-4.19.71-imx-r1_1stable_armhf.deb)。
+- uboot目录:存放前面编译出来的uboot固件(u-boot-dtb.imx)。
+
+ebf-image-builde编译Debian固件
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+进入ebf-image-builde项目源码目录下，直接执行编译脚本
+
+.. code-block:: sh
+   :emphasize-lines: 2
+   :linenos:
+
+   cd ebf-image-builder
+   sudo ./publish/seeed-imx-stable.sh
+
+注意：如果执行过程提示:
+
+.. code-block:: sh
+   :emphasize-lines: 2
+   :linenos:
+
+    m4: 未找到命令
+
+那么先用apt工具安装m4工具，再重新执行编译命令
+
+.. code-block:: sh
+   :emphasize-lines: 2
+   :linenos:
+
+   sudo apt install m4 -y
+   sudo ./publish/seeed-imx-stable.sh
+
+正常编译时，打印信息如下图所示:
+
+.. image:: media/building_debian_start.png
+   :align: center
+   :alt: 开始编译debian
+
+编译时间较长(大概三十分钟到一个小时不等，主要跟网速有关)，请耐心等待。如果后面客户需要频繁进行编译工作，
+我们会提供使用代理下载的方法，可大幅减小编译时间。
+
+编译完成后，下图中红框部分即为新编译的Debian系统镜像
+
+.. image:: media/building_debian_end.png
+   :align: center
+   :alt: 编译debian结束
+
+Debian系统镜像存放下面目录中
+
+.. code-block:: sh
+   :emphasize-lines: 2
+   :linenos:
+
+    ebf-image-builder/deploy/debian-buster-console-armhf##日期 
+    
+可以参考《SD卡烧录Debian镜像》章节把该镜像烧录到sd卡中，以SD卡方式启动开发板。
+
+烧录完成后，开发板第一次用sd卡方式启动时，系统会自动进行扩容重启，
+以保证充分利用sd卡存储空间。扩容完毕后，系统重启生效。
+
+修改启动logo步骤
+~~~~~~~~~~~~~~~~~~~~~
+
+其实在野火开发板的固件中，uboot是没有logo的，因为将uboot的logo删掉了，因为在内核有logo，而uboot到内核的时间非常短（已经将uboot等待
+3S时间去掉了），所以直接使用内核的logo会更好，那么如果想要使用内核的logo，就得自己去修改内核的logo，下面就教大家如何去做。
+
+准备一张图片
+""""""""
+
+我们可以随便准备一张图片，比如我们就选择ubuntu的logo吧，将它制作成适合显示屏大小的图片，比如5寸屏幕的分辨率是800*480：
+
+.. figure:: media/building_kernel006.png
+   :alt: building_kernel006
+
+   building_kernel006
+
+然后将其保存为 **256色（即8位色）的bpm格式的图片** ，可以在Windows下或者Linux虚拟机下编辑：
+
+.. figure:: media/building_kernel007.png
+   :alt: building_kernel007
+
+   building_kernel007
+
+转换为ppm格式的图片
+""""""""
+
+1、安装格式转换工具
+
+   sudo apt install netpbm -y
+
+2、在Linux下使用以下脚本将其转换为ppm格式的文件，为什么是ppm格式呢？
+因为这是编译Linux内核必要的文件格式，想要修改logo，就要这种格式的文件，
+它必须是 **256色（即8位色）的bpm格式的图片** 转换而成的。
+
+.. code:: bash
+
+    #!/bin/bash
+    if [ " $1" == " " ];
+    then
+        echo "usage:$0 bmp_file"
+        exit 0
+    fi
+
+    if [ -f "$1" ]
+    then
+        echo $1
+    else
+        echo "no find file [$1]"
+        exit 0
+    fi
+
+    name=${1%%.*}
+    bmptopnm $1 > $name.pnm
+    pnmquant 224 $name.pnm > $name.clut224.pnm
+    pnmtoplainpnm $name.clut224.pnm > $name.ppm
+    rm $name.pnm $name.clut224.pnm 
+
+这是bmp文件转换ppm格式文件的脚本，可以将其写入一个叫 ``bmp2ppm.sh`` 脚本文件中，并且赋予其可执行的权限（使用
+``chmod +x bmp2ppm.sh``
+命令即可），它主要是使用linux系统中的工具转换，如果系统中没有相关工具，则根据提示使用 ``apt install`` 命令进行安装即可。
+
+然后将准备好的bmp文件拷贝到制作ppm文件的目录下，使用 ``bmp2ppm.sh`` 脚本将其转化为ppm文件，具体操作如下：
+
+.. code:: bash
+
+    ➜  bmp2ppm git:(master) ✗ ls
+    bmp2ppm.sh  README.md  ubuntu.bmp
+
+    ➜  bmp2ppm git:(master) ✗ ./bmp2ppm.sh ubuntu.bmp 
+    ubuntu.bmp
+    bmptopnm: Windows BMP, 800x480x8
+    bmptopnm: WRITING PPM IMAGE
+    pnmcolormap: making histogram...
+    pnmcolormap: 29 colors found
+    pnmcolormap: Image already has few enough colors (<=224).  Keeping same colors.
+    pnmremap: 29 colors found in colormap
+
+    ➜  bmp2ppm git:(master) ✗ ls
+    bmp2ppm.sh  README.md  ubuntu.bmp  ubuntu.ppm
+
+替换原本的logo文件
+""""""""
+
+1、在转换完成后，当前目录将出现对应的ppm文件，我们将其拷贝到linux内核源码的 ``ebf-buster-linux/drivers/video/logo`` 目录下，因为我们的logo是存放在此处的，野火提供的logo：
+
+-  默认编译的logo：logo_linux_clut224.ppm
+
+2、将你编译的ppm文件重命名为logo_linux_clut224.ppm，替换掉内核中旧的logo_linux_clut224.ppm文件。
+
+3、按照上面的编译步骤，重新编译内核，把编译得到的内核安装包(linux-image-4.19.71-imx-r1_1stable_armhf.deb)，
+复制粘贴到ebf-image-builder项目中的Kernel文件夹下，重新在ebf-image-builder项目中编译得到新的.img格式系统镜像。
+
+修改启动脚本
+""""""""
+
+把新的.img格式系统镜像烧录到sd卡中，启动开发板。此时会出现一个现象，logo一闪而过，这是因为内核启动后，
+会执行文件系统的启动脚本，而此时文件系统的启动脚本中 ``/opt/scripts/boot/psplash.sh``\
+会去执行相应的应用程序 ``/usr/bin/psplash`` ，这就是绘制开机的进度条与背景。那么你的开机logo将被刷掉，
+而只要不让这个启动脚本运行这个 ``/usr/bin/psplash`` 应用程序就可以解决问题了，
+那么我们在开发板中使用vi编辑器修改脚本 ``/opt/scripts/boot/psplash.sh`` 。
+
+如下图:
+
+.. figure:: media/stop_psplash.png
+   :alt: 停止进度条
+
+将其最后一行屏蔽掉，然后重启开发板，就可以看见你的logo了并且没有了进度条程序。
\ No newline at end of file
diff --git a/documentation/building_image/building_kernel.rst b/documentation/building_image/building_kernel.rst
index fe6391e1e995e04ed5ac961e2d7aef9afd964fef..2a9854644b35d9c1648f9fc28a746705700b0f5e 100644
--- a/documentation/building_image/building_kernel.rst
+++ b/documentation/building_image/building_kernel.rst
@@ -1,318 +1,643 @@
-.. vim: syntax=rst
-
 编译内核
-----
+========
 
-本章节内容处于开发笔记状态，还待整理至最终版的教程。
+下载野火官方提供的内核镜像
+--------------------------
 
-本章节内容处于开发笔记状态，还待整理至最终版的教程。
+在编译内核前我们首先要下载到官方提供的内核镜像，目前野火官方镜像已经托管在github上，可以随时去下载，打开 https://github.com/Embedfire/ebf_6ull_linux 网页，可以看到野火官方提供的内核镜像，并且携带了很详细的操作说明文档，这个仓库是来源于NXP官方提供的内核镜像 http://git.freescale.com/git/cgit.cgi/imx/linux-imx.git/ ，由 ``imx_4.1.15_2.0.0_ga`` 分支开发而来，主要是满足野火开发板的需求。
 
-下载nxp官方提供的内核镜像
-~~~~~~~~~~~~~~
+我们只需要野火官方提供的内核镜像即可，首先我们克隆一下这个内核镜像仓库，在克隆内核镜像的时候最好是在虚拟机中（或linux环境），而不是在Windows环境下，我们将使用 ``git clone`` 命令去克隆官方提供的内核镜像，这样子就能保留镜像中的所有git信息与标签，在开发过程中能方便切换到合适的分支进行开发，因为不同的分支内核镜像的源代码修改的地方是不一样的，可能会发生未知的问题，我们目前就使用 ``master`` 分支进行开发。
 
-在编译内核前我们首先要下载到官方提供的内核镜像，打开\ http://git.freescale.com/git/\
-网页，可以看到很多nxp官方提供的内核镜像，这个网站是飞思卡尔（freescale）公司的，在2015年的是nxp巨资收购了飞思卡尔，所以可以直接从飞思卡尔的网站下载nxp官方提供的内核镜像。
+使用 ``git clone`` 命令克隆内核镜像，然后等待克隆完成即可：
 
-打开网页后可以看到nxp官方有非常多的镜像在这里，我们需要选择要下载的内核镜像linux-imx，然后页面会跳转到linux-imx内核镜像的详细说明页面，该页面有很多分支、标签等信息，具体见图 30‑1、图 30‑2。
+.. code:: bash
 
-|buildi010|
+    git clone https://github.com/Embedfire/ebf_6ull_linux.git
 
-图 30‑1 选择linux-imx镜像
+由于github网站是国外的，可能会非常慢，甚至出现下载失败现象，建议使用gitee中的仓库，我们已经将源码提交到gitee平台，直接使用 ``git clone`` 命令克隆内核镜像即可：
 
-|buildi003|
+.. code:: bash
 
-图 30‑2 linux-imx信息说明
+    git clone https://gitee.com/wildfireteam/ebf_6ull_linux.git
 
-我们注意图 30‑2最下面的两句话，它就是告诉我们克隆（即下载）镜像的路径：
+    Cloning into 'ebf_6ull_linux'...
+    remote: Enumerating objects: 54412, done.
+    remote: Counting objects: 100% (54412/54412), done.
+    remote: Compressing objects: 100% (47905/47905), done.
+    remote: Total 54412 (delta 5331), reused 54348 (delta 5281)
+    Receiving objects: 100% (54412/54412), 148.94 MiB | 3.49 MiB/s, done.
+    Resolving deltas: 100% (5331/5331), done.
+    Checking out files: 100% (51413/51413), done.
 
-Clonegit://git.freescale.com/imx/linux-imx.git http://git.freescale.com/git/cgit.cgi/imx/linux-imx.git
+内核源码目录
+------------
 
-在克隆内核镜像的时候最好是在虚拟机中（或linux环境），而不是在Windows环境下载，然后下载的环境必须支持git，因为我们将使用git
-clone命令去克隆nxp官方提供的内核镜像，这样子就能保留镜像中的所有git信息与标签，在开发过程中能方便切换到合适的分支进行开发，因为不同的分支内核镜像的源代码是不一样的，可能会发生未知的问题，我们目前就使用\ `imx_4.1.15_2.0.0_ga
-<http://git.freescale.com/git/cgit.cgi/imx/linux-imx.git/log/?h=imx_4.1.15_2.0.0_ga>`__\ 分支进行开发。
+在运行 ``git clone`` 命令命令后，大约等待一分钟，我们可以看到输出的信息，已然提示克隆完成，我们会发现克隆的目录下多出了一个文件夹 ``ebf_6ull_linux`` ，我们可以进入到 ``ebf_6ull_linux`` 目录下，可以使用git
+log查看仓库的日志信息，看看更改了什么地方。在 ``ebf_6ull_linux`` 目录下看到当前目录下多了很多文件夹，它就是我们克隆的内核镜像，里面是官方提供的内核源码，我们可以进入imx-linux目录下中查看主要有哪些文件夹组成，具体见：
 
-使用git clone命令克隆内核镜像，然后等待克隆完成即可：
+.. code:: bash
 
-git clone git://git.freescale.com/imx/linux-imx.git
+    ➜  ebf_6ull_linux git:(master) ls
 
-由于网站是国外的，可能会非常慢，甚至出现下载失败现象，建议使用野火资料包中的源码进行开发，我们已经将源码提交到腾讯云开发者平台，直接使用git clone命令克隆内核镜像即可：
+    arch      CREDITS        fs       Kconfig      mm               REPORTING-BUGS  tools
+    block     crypto         include  kernel       Module.symvers   samples         usr
+    build.sh  Documentation  init     lib          net              scripts         virt
+    COPYING   drivers        ipc      MAINTAINERS  OFFICIAL-README  security
+    copy.sh   firmware       Kbuild   Makefile     README.md        sound
 
-注意：我们修改的镜像名字是imx-linux，与官方命名刚好相反以便于区分。
+.. figure:: media/building_kernel001.png
+   :alt: building_kernel001
 
-命令
+   building_kernel001
 
-git clone https://git.dev.tencent.com/flyleaf91/imx-linux.git
 
-运行结果
+从图中我们可以看到Linux内核源码目录下是有非常多的文件夹，且文件夹下也有非常多的文件，下面我们简单分析一下这些文件夹的主要作用。
 
-embedfire@embedfire_dev:~$ git clone https://git.dev.tencent.com/flyleaf91/imx-linux.gitCloning into 'imx-linux'...remote: Enumerating objects:
-8225151, done.remote: Counting objects: 100% (8225151/8225151), done.remote: Compressing objects: 100% (1240846/1240846), done.remote: Total 8225151
-(delta 6957086), reused 8201579 (delta 6933694) Receiving objects: 100% (8225151/8225151), 1.37 GiB \| 4.79 MiB/s, done.Resolving deltas: 100%
-(6957086/6957086), done.warning: remote HEAD refers to nonexistent ref, unable to checkout.
+-  arch：主要包含和硬件体系结构相关的代码，如arm、x86、MIPS，PPC，每种CPU平台占一个相应的目录，例如我们使用的imx系列CPU就在 ``arch/arm/mach-imx`` 目录下，Linux内核目前已经支持30种左右的CPU体系结构。arch中的目录下存放的是各个平台以及各个平台的芯片对Linux内核进程调度、
+   内存管理、 中断等的支持，以及每个具体的SoC和电路板的板级支持代码。
 
-我们可以看到输出的信息，虽然是提示克隆完成，但是没法切换到（checkout）合适的分支，此时就需要进行手动切换分支。首先进入imx-linux目录下，可以看到imx-linux目录下是没有文件的，这是因为没有切换到正确的分支，我们可以使用git branch
-–a命令查看当前下载的源码包的分支情况，可以看到存在两个分支，分别是remotes/origin/imx_4.1.15_2.0.0_ga与remotes/origin/show，我们可以使用git
-checkout命令手动切换到imx_4.1.15_2.0.0_ga分支，然后就可以看到当前目录下多了很多文件夹，具体见：
+-  block：在Linux中block表示块设备（以块（多个字节组成的整体，类似于扇区）为单位来整体访问），譬如说SD卡、Nand、硬盘等都是块设备，block目录下放的是一些Linux存储体系中关于块设备管理的代码。
 
-进入imx-linux目录
+-  crypto：这个文件夹下存放的是常用加密和散列算法（如md5、AES、 SHA等）
+   ，还有一些压缩和CRC校验算法。
 
-embedfire @embedfire_dev:~$ cd imx-linux/embedfire @embedfire_dev:~/imx-linux$ ls
+-  Documentation：内核各部分的文档描述。
 
-命令
+-  drivers：设备驱动程序，里面列出了linux内核支持的所有硬件设备的驱动源代码，每个不同的驱动占用一个子目录，如char、
+   block、 net、 mtd、 i2c等。
 
-embedfire @embedfire_dev:~/imx-linux$ git branch –a
+-  fs：fs就是file system，里面包含Linux所支持的各种文件系统，如EXT、
+   FAT、 NTFS、 JFFS2等。
 
-输出
+-  include：目录包括编译核心所需要的大部分头文件，例如与平台无关的头文件在 ``include/linux`` 子目录下，与cpu架构相关的头文件在include目录下对应的子目录中。
 
-remotes/origin/imx_4.1.15_2.0.0_ga remotes/origin/show
+-  init：内核初始化代码，这个目录下的代码就是linux内核启动时初始化内核的代码。
 
-手动切换分支
+-  ipc：ipc就是 ``inter process commuication`` ，进程间通信，该文件夹下都是linux进程间通信的代码。
 
-embedfire @embedfire_dev:~/imx-linux$ git checkout imx_4.1.15_2.0.0_ga
+-  kernel：kernel就是Linux内核，是Linux中最核心的部分，包括进程调度、定时器等，而和平台相关的一部分代码放在arch/*/kernel目录下。
 
-输出
+-  lib：lib是库的意思，lib目录下存放的都是一些公用的有用的库函数，注意这里的库函数和C语言的库函数不一样的，因为在内核编程中是不能用C语言标准库函数的，所以需要使用lib中的库函数，除此之外与处理器结构相关的库函数代码被放在 ``arch/*/lib/`` 目录下。
 
-Checking out files: 100% (50159/50159), done.Branch 'imx_4.1.15_2.0.0_ga' set up to track remote branch 'imx_4.1.15_2.0.0_ga' from 'origin'.Switched
-to a new branch 'imx_4.1.15_2.0.0_ga'
+-  mm： 目录包含了所有独立于 cpu
+   体系结构的内存管理代码，如页式存储管理内存的分配和释放等，而与具体硬件体系结构相关的内存管理代码位于 ``arch/*/mm`` 目录下，例如 ``arch/arm/mm/fault.c`` 。
 
-命令
+-  net： 网络协议栈相关代码，net目录下实现各种常见的网络协议。
 
-embedfire @embedfire_dev:~/imx-linux$ ls
+-  scripts：这个目录下全部是脚本文件，这些脚本文件不是linux内核工作时使用的，而是用了配置编译linux内核的。
 
-输出
+-  security：内核安全模型相关的代码，例如最有名的SELINUX。
 
-arch COPYING CREDITS Documentation firmware include ipc Kconfig lib Makefile net REPORTING-BUGS scripts sound usrblock copy.sh crypto drivers fs init
-Kbuild kernel MAINTAINERS mm README samples security tools virt
+-  sound： ALSA、 OSS音频设备的驱动核心代码和常用设备驱动。
 
-内核源码目录
-~~~~~~
+-  usr： 实现用于打包和压缩的cpio等。
 
-在克隆完内核镜像之后，我们会发现克隆的目录下多出了一个文件夹imx-linux，它就是我们克隆的内核镜像，里面是官方提供的内核源码，我们可以进入imx-linux目录下中查看主要有哪些文件夹组成，具体见图 30‑3。
+提示：对于其他的未列出来的目录，暂时不用去理会。
 
-|buildi004|
+编译内核
+--------
 
-图 30‑3内核源码目录
+简单了解内核源码的目录结构后，我们可以开始尝试编译内核，本小节主要是以编译我们配套的开发板源代码为主。
 
-从图中我们可以看到Linux内核源码目录下是有非常多的文件夹，且文件夹下也有非常多的文件，下面我们简单分析一下这些文件夹的主要作用。
+我们提供的源码包是经过修改的，首先进入 ``ebf_6ull_linux/arch/arm/configs`` 目录下，可以看到很多默认的deconfig文件，这些是linux源码中的配置文件，其中我们主要关注 ``imx_v6_v7_defconfig、imx_v7_defconfig 、imx6_v7_ebf_defconfig`` 这3个文件即可， ``imx_v6_v7_defconfig、imx_v7_defconfig`` 这两个文件是nxp官方提供的默认配置文件，而 ``imx6_v7_ebf_defconfig`` 文件则是我们野火提供的配置文件，这些文件是与编译内核息息相关的，而不同的开发板这些配置是不一样的，前面两个是用于编译官方的imx6ull开发板，而后面两个则是根据我们的imx6ull开发板硬件而定制的配置。
+由于整个内核镜像都已经打上我们的补丁，那么也无需再做过多的修改即可直接编译，我们可以通过git
+log命令查看补丁信息：
 
--  arch：主要包含和硬件体系结构相关的代码，如arm、x86、MIPS，PPC，每种CPU平台占一个相应的目录，例如我们使用的imx系列CPU就在arch/arm/mach-
-  imx目录下，Linux内核目前已经支持30种左右的CPU体系结构。arch中的目录下存放的是各个平台以及各个平台的芯片对Linux内核进程调度、 内存管理、 中断等的支持，以及每个具体的SoC和电路板的板级支持代码。
+.. code:: bash
 
--  block：在Linux中block表示块设备（以块（多个字节组成的整体，类似于扇区）为单位来整体访问），譬如说SD卡、Nand、硬盘等都是块设备，block目录下放的是一些Linux存储体系中关于块设备管理的代码。
+    ➜  ebf_6ull_linux git:(master) ✗ git log
 
--  crypto：这个文件夹下存放的是常用加密和散列算法（如md5、AES、 SHA等） ，还有一些压缩和CRC校验算法。
+    commit fe1b9b8fe423aa41ff53757b94adddea8973662d (HEAD -> master, origin/master)
+    Author: jiejie <1161959934@qq.com>
+    Date:   Tue Jan 14 08:06:54 2020 +0000
 
--  Documentation：内核各部分的文档描述。
+        update config
 
--  drivers： 设备驱动程序，里面列出了linux内核支持的所有硬件设备的驱动源代码，每个不同的驱动占用一个子目录，如char、 block、 net、 mtd、 i2c等。
+    commit 3594c804dafc37dae86a89520273b87c35488ce9
+    Author: jiejie <1161959934@qq.com>
+    Date:   Tue Jan 14 07:33:57 2020 +0000
 
--  fs：fs就是file system，里面包含Linux所支持的各种文件系统，如EXT、 FAT、 NTFS、 JFFS2等。
+        update config
 
--  include：目录包括编译核心所需要的大部分头文件，例如与平台无关的头文件在include/linux子目录下，与cpu架构相关的头文件在include目录下对应的子目录中。
+    commit 342f29e8f7813917c945c3fde1bf2767b61110f6
+    Author: jiejie <1161959934@qq.com>
+    Date:   Tue Jan 7 02:44:46 2020 +0000
 
--  init： 内核初始化代码，这个目录下的代码就是linux内核启动时初始化内核的代码。
+        update README.md
 
--  ipc： ipc就是inter process commuication，进程间通信，该文件夹下都是linux进程间通信的代码。
+    commit 7c24a3c05257373d30dd698398b9bb798e814cec
+    Author: jiejie <1161959934@qq.com>
+    Date:   Wed Nov 27 02:45:14 2019 +0000
 
--  kernel： kernel就是Linux内核，是Linux中最核心的部分，包括进程调度、定时器等，而和平台相关的一部分代码放在arch/*/kernel目录下。
+        compatible with 5-inch and 4.3-inch LCD
 
--  lib：lib是库的意思，lib目录下存放的都是一些公用的有用的库函数，注意这里的库函数和C语言的库函数不一样的，因为在内核编程中是不能用C语言标准库函数的，所以需要使用lib中的库函数，除此之外与处理器结构相关的库函数代码被放在arch/*/lib/目录下。
+    commit 1b9f4f2252477d8eb41eb3f53f0e2232de7af576
+    Author: jiejie <1161959934@qq.com>
+    Date:   Tue Nov 19 06:44:02 2019 +0000
 
--  mm： 目录包含了所有独立于 cpu 体系结构的内存管理代码，如页式存储管理内存的分配和释放等，而与具体硬件体系结构相关的内存管理代码位于arch/*/mm目录下，例如arch/arm/mm/fault.c。
+        add 7' HDMI support
 
--  net： 网络协议栈相关代码，net目录下实现各种常见的网络协议。
+搭建编译环境
+~~~~~~~~~~~~
 
--  scripts：这个目录下全部是脚本文件，这些脚本文件不是linux内核工作时使用的，而是用了配置编译linux内核的。
+开发环境： **ubuntu18.04**
 
--  security：内核安全模型相关的代码，例如最有名的SELINUX。
+**安装必要的库**
 
--  sound： ALSA、 OSS音频设备的驱动核心代码和常用设备驱动。
+.. code:: bash
 
--  usr： 实现用于打包和压缩的cpio等。
+    sudo apt-get install lzop libncurses5-dev
 
-提示：对于其他的未列出来的目录，暂时不用去理会。
+**安装独立编译工具链**
 
-.. _编译内核-1:
+1. 命令安装方式（推荐新手使用这种方法）：
 
-编译内核
-~~~~
+arm-linux-gnueabihf-gcc： ``v7.4.0``
+
+.. code:: bash
+
+    sudo apt-get install gcc-arm-linux-gnueabihf
+
+2. 安装包安装方式(推荐老手使用这种方法)
+
+从百度云盘下载 ``arm-linux-gnueabihf-gcc`` 编译器的压缩包，版本是
+``v4.9.3``
+
+链接： https://github.com/Embedfire/products/wiki
+
+在 **Linux系列产品**中找到的网盘链接，在 ``i.MX6ULL系列\5-编译工具链\arm-gcc`` 目录下找到``arm-gcc.tar.gz``压缩包并且下载，然后解压到 ``/opt/arm-gcc/`` 目录下，如果没有创建即可，解压后就可以在 ``/opt/arm-gcc/bin/`` 目录下找到我们的编译器 ``arm-linux-gnueabihf-gcc`` ，它的版本是 ``gcc version 4.9.3 20141031 (prerelease) (Linaro GCC 2014.11)`` ，然后可以将编译器所在的路径添加到环境变量中，只修改当前用户的配置文件，通常是 ``"~/.bashrc"`` 或者 ``"~/.bash_profile"`` ，直接
+vi 打开即可，在文件末尾增加编译器所在的路径：
+
+.. code:: bash
+
+    export PATH=$PATH:/opt/arm-gcc/bin/
+
+立即使新的环境变量生效，不用重启电脑：
+
+.. code:: bash
 
-简单了解内核源码的目录结构后，我们可以开始尝试编译内核，本小节主要是以编译我们配套的开发板源代码为主，在后续也会提到编译官方开发板源代码的方法（官方的比较简单）。
+    ➜  ebf_6ull_linux git:(master) ✗ source ~/.bashrc
 
-我们提供的源码包是经过修改的，首先进入imx-linux/arch/arm/configs目录下，可以看到很多默认的deconfig文件，这些是linux源码中的配置文件，其中我们主要关注imx_v6_v7_defconfig、imx_v7_defconfig
-、imx_v7_ebf_defconfig 、imx_v7_mfg_defconfig这4个文件即可，如图 30‑4所示。
+然后检查是否将路径加入到PATH：
 
-|buildi005|
+.. code:: bash
 
-图 30‑4 默认配置文件
+    ➜  ebf_6ull_linux git:(master) ✗ echo $PATH
 
-imx_v6_v7_defconfig、imx_v7_defconfig这两个文件是nxp官方提供的默认配置文件，而imx_v7_ebf_defconfig
-、imx_v7_mfg_defconfig这两个文件则是我们野火提供的配置文件，这些文件是与边缘内核息息相关的，而不同的开发板这些配置是不一样的，前面两个是用于编译官方的imx6ull开发板，而后面两个则是根据我们的imx6ull开发板硬件而定制的配置。
+显示的内容中有 ``/opt/arm-gcc/bin`` ，说明已经将交叉编译器的路径加入PATH。至此，交叉编译环境安装完成。
 
-由于整个内核镜像都已经打上我们的补丁，那么也无需再做过多的修改即可直接编译，我们可以通过git log命令查看补丁信息：
+测试是否安装成功
 
-命令
+.. code:: bash
 
-embedfire @embedfire_dev:~/imx-linux$ git log
+    ➜  ebf_6ull_linux git:(master) ✗ arm-linux-gnueabihf-gcc -v
+    Using built-in specs.
+    COLLECT_GCC=arm-linux-gnueabihf-gcc
+    COLLECT_LTO_WRAPPER=/opt/arm-gcc/bin/../libexec/gcc/arm-linux-gnueabihf/4.9.3/lto-wrapper
+    ···
+    gcc version 4.9.3 20141031 (prerelease) (Linaro GCC 2014.11) 
 
-输出
+上面的命令会显示arm-linux-gcc信息和版本，说明成功。
 
-commit 00ce0881a15f0a140f6a684cafea06e114e0c6c7 (HEAD -> imx_4.1.15_2.0.0_ga, origin/imx_4.1.15_2.0.0_ga)Author: flyleaf91 <flyleaf91@163.com>Date:
-Tue Aug 27 02:31:51 2019 +0000 添加ebf config文件commit 2d1ca998ace53ee6f9f053b99296166e80321b6aAuthor: pengjie <jiejie.128@163.com>Date: Mon Aug 26
-21:29:18 2019 +0800 Modified 1.pwm_core 2.led_pwm 3.mmc led Signed-off-by: pengjie <jiejie.128@163.com>commit
-deefdc004090ada48b79e9db54142c4a2df497ffAuthor: pengjie <jiejie.128@163.com>Date: Fri Aug 23 21:34:41 2019 +0800 Modified dht.c.
-Signed-off-by: pengjie <jiejie.128@163.com>commit cd898b5d5afb7fa6f2fc1cfee6bfbdc71ddf4ec1Author: pengjie <jiejie.128@163.com>Date: Mon Aug 12
-23:24:28 2019 +0800 添加ADC&18B20&DHT11 Signed-off-by: pengjie <jiejie.128@163.com>commit 6bb47fefdc503793fd0b0876a6a81c81c339efec (origin/show)Author:
-pengjie <jiejie.128@163.com>Date: Mon Aug 5 21:25:11 2019 +0800 适配4.3寸，5寸，7寸LCD以及触摸屏 Signed-off-by: pengjie <jiejie.128@163.com>commit
-30278abfe0977b1d2f065271ce1ea23c0e2d1b6e (tag: rel_imx_4.1.15_2.1.0_ga)Author: Robby Cai <robby.cai@nxp.com>Date: Thu May 4 14:52:24 2017 +0800
-MLK-14762 ARM: dts: imx6sll-evk: correct gpio pin for lcd power control
+更多安装方法参考： https://blog.csdn.net/u013485792/article/details/50958253
 
-在编译内核前需要安装编译内核的工具链：arm-linux-gnueabihf-gcc，我们使用的是v7.4.0版本，大家可以通过命令安装：
+    作者备注：为什么推荐更低版本的编译器呢？因为作者亲测新版本的编译器并不能完全兼容，在测试比如新版本编译的内核镜像无法识别到4G模块。但是在绝大部分情况下 ``v7.4.0`` 版本的编译器都是没有任何问题的！！！请放心使用！！！
 
-sudo apt-get install gcc-arm-linux-gnueabihf
+编译前准备
+~~~~~~~~~~
 
-然后可以通过arm-linux-gnueabihf-gcc –v命令查看交叉编译器的版本号（我的虚拟机上是7.4.0版本，即使是不一样的版本有也是没有问题的，都是可以编译通过的）：
+在开始编译内核前，可以把环境变量设置一下，以防编译时找不到环境变量：
 
-命令
+.. code:: bash
 
-embedfire @embedfire_dev:~/imx-linux$ arm-linux-gnueabihf-gcc -v
+    export PATH=/opt/arm-gcc/bin:$PATH 
+    export ARCH=arm 
+    export CROSS_COMPILE=arm-linux-gnueabihf- 
 
-输出
+**清除编译信息**
 
-Using built-in specs.COLLECT_GCC=arm-linux-gnueabihf-gccCOLLECT_LTO_WRAPPER=/usr/lib/gcc-cross/arm-linux-gnueabihf/7/lto-wrapperTarget: arm-linux-
-gnueabihfConfigured with: ../src/configure -v --with-pkgversion='Ubuntu/Linaro 7.4.0-1ubuntu1~18.04.1' --with-
-bugurl=file:///usr/share/doc/gcc-7/README.Bugs --enable-languages=c,ada,c++,go,d,fortran,objc,obj-c++ --prefix=/usr --with-gcc-major-version-only
---program-suffix=-7 --enable-shared --enable-linker-build-id --libexecdir=/usr/lib --without-included-gettext --enable-threads=posix --libdir=/usr/lib
---enable-nls --with-sysroot=/ --enable-clocale=gnu --enable-libstdcxx-debug --enable-libstdcxx-time=yes --with-default-libstdcxx-abi=new --enable-gnu-
-unique-object --disable-libitm --disable-libquadmath --disable-libquadmath-support --enable-plugin --enable-default-pie --with-system-zlib --with-
-target-system-zlib --enable-multiarch --enable-multilib --disable-sjlj-exceptions --with-arch=armv7-a --with-fpu=vfpv3-d16 --with-float=hard --with-
-mode=thumb --disable-werror --enable-multilib --enable-checking=release --build=x86_64-linux-gnu --host=x86_64-linux-gnu --target=arm-linux-gnueabihf
---program-prefix=arm-linux-gnueabihf- --includedir=/usr/arm-linux-gnueabihf/includeThread model: posixgcc version 7.4.0 (Ubuntu/Linaro
-7.4.0-1ubuntu1~18.04.1)
+.. code:: bash
 
+    make ARCH=arm clean
 
-export PATH=/opt/arm-gcc/bin:$PATHexport ARCH=arm export CROSS_COMPILE=arm-linux-gnueabihf-
+设置配置选项，使用野火开发板配置
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
-首先进入imx-linux目录下，然后开始编译内核，运行make ARCH=arm imx_v7_ebf_defconfig命令将imx_v7_ebf_defconfig配置文件的信息写入当前路径下的 .config文件中，在linux中与“.”开头的文件都是隐藏文件，我们可以使用ls
+首先进入imx-linux目录下，然后开始编译内核，运行 ``make ARCH=arm imx6_v7_ebf_defconfig`` 命令将imx6_v7_ebf_defconfig配置文件的信息写入当前路径下的
+``.config`` 文件中，在linux中以 ``"."`` 开头的文件都是隐藏文件，我们可以使用ls
 –la命令查看这些文件。
 
-命令
+.. code:: bash
+
+    make ARCH=arm imx6_v7_ebf_defconfig
+
+
+    输出
+      HOSTCC  scripts/basic/fixdep   
+      HOSTCC  scripts/kconfig/conf.o   
+      SHIPPED scripts/kconfig/zconf.tab.c   
+      SHIPPED scripts/kconfig/zconf.lex.c   
+      SHIPPED scripts/kconfig/zconf.hash.c   
+      HOSTCC  scripts/kconfig/zconf.tab.o   
+      HOSTLD  scripts/kconfig/conf 
+      # 
+      # configuration written to .config 
+      #
+
+Linux内核的配置系统由三个部分组成，分别是： 
+-  Makefile：分布在 Linux内核源代码根目录及各层目录中，定义 Linux 内核的编译规则； 
+
+-  配置文件：给用户提供配置选择的功能，如Kconfig文件定义了配置项，.config文件对配置项进行赋值；
+
+-  配置工具：包括配置命令解释器（对配置脚本中使用的配置命令进行解释）和配置用户界面（linux提供基于字符界面、基于Ncurses 图形界面以及基于 Xwindows 图形界面的用户配置界面，各自对应于make config、make menuconfig 和 make xconfig）。
+
+
+读者如果想看我们提供的配置文件imx6_v7_ebf_defconfig中修改了什么地方，可以通过makemenuconfig命令来查看我们的配置，
+makemenuconfig是一个基于文本选择的配置界面，推荐在字符终端下使用，make menuconfig运行的时候会从当前目录下
+导入 .config文件的配置（如果没有找到.config文件则会生成默认配置的 .config文件），
+而这个配置则是我们运行make ARCH=arm imx6_v7_ebf_defconfig命令生成的，这就直接可以看到我们在imx6_v7_ebf_defconfig的配置选择，
+可以通过键盘的"上"、"下"、"左"、"右"、"回车"、"空格"、"?"、"ESC"等按键进行选择配置，具体见：
+
+.. figure:: media/building_kernel002.png
+   :alt: building_kernel002
+
+   building_kernel002
+
+比如我们选择配置我们开发板的触摸屏驱动： ``Goodix I2C touchscreen`` ，如果读者炸不到这个配置选项在哪里，可以利用 ``make menuconfig`` 中的搜索功能，在英文输入法状态下按下"/"则可以进行搜索，输入"Goodix"找到改配置选项的位置，具体见：
+
+.. figure:: media/building_kernel003.png
+   :alt: building_kernel003
+
+   building_kernel003
+
+从图中可以很明显看出 ``Goodix I2C touchscreen`` 配置选项位于 ``-> Device Drivers`` 选项下的 ``-> Input device support`` 下的 ``-> Generic input layer (needed for keyboard, mouse, ...) (INPUT [=y])`` 选项下的 ``-> Touchscreens`` 选项中，其实也可以按下 ``"1"`` 直接可以定位到对应的选项，然后选中以下内容即可，具体见图：
+
+.. code:: bash
+
+    [*]Goodix touchpanel GT9xx series 
+    <*> Goodix GT9xx touch controller auto update support 
+    <*> Goodix GT9xx Tools for debuging 
+    <*>Goodix I2C touchscreen
+
+.. figure:: media/building_kernel004.png
+   :alt: building_kernel004
+
+   building_kernel004
+
+再举个例子，如果想要在我们的开发板上使用 ``DHT11`` 测量温湿度（单总线协议），那么需要在内核中配置支持单总线协议： ``Dallas's 1-wire support`` ，我们也照葫芦画瓢，先搜索到这个配置在哪个位置（时候搜索不到就直接找即可），它位于 ``->Device Drivers``
+选项下的 ``<*> Dallas's 1-wire suppor`` 选项中，然后进入它的选项下进行选择即可，当配置完成后保存退出，就可以进行编译了，具体见:
+
+.. figure:: media/building_kernel005.png
+   :alt: building_kernel005
+
+   building_kernel005
+
+开始编译
+~~~~~~~~
+
+如果不需要修改配置，则可以直接编译，运行 ``make ARCH=arm -j10 CROSS_COMPILE=arm-linux-gnueabihf-`` 命令直接编译， ``-j10`` 是代表使用10个线程进行编译，如果不选则默认使用一个线程编译，而线程的多少决定了编译的时间，根据自身情况决定即可，在运行这个命令后，可以看到中断输出一系列编译信息，而在编译的最后会告诉我们编译成功，镜像存在 ``arch/arm/boot/`` 目录下，具体见：（已删减绝大部分编译输出的信息）。
+
+.. code:: bash
+
+    make ARCH=arm -j10 CROSS_COMPILE=arm-linux-gnueabihf- 
+
+    # 输出内容（已删减绝大部分编译输出的信息）
+    ···
+    OBJCOPY arch/arm/boot/zImage   
+    Kernel: arch/arm/boot/zImage is ready
+    ···
+
+编译生成的镜像输出路径
+~~~~~~~~~~~~~~~~~~~~~~
+
+**内核镜像路径**
+
+.. code:: bash
+
+    ebf_6ull_linux/arch/arm/boot
+
+**设备树输出路径**
+
+.. code:: bash
+
+    ebf_6ull_linux/arch/arm/boot/dts
 
-embedfire @embedfire_dev:~/imx-linux$ make ARCH=arm imx_v7_ebf_defconfig
+因为这个 ``make ARCH=arm -j10 CROSS_COMPILE=arm-linux-gnueabihf-`` 命令编译的不仅仅是内核，还会编译设备树，设备树编译后产生的.dtb文件存在 ``arch/arm/boot/dts/`` 目录下，我们可以通过 ``ls arch/arm/boot/dts/ | grep .dtb`` 命令查看该目录下的所有设备树：
 
-输出
+.. code:: bash
 
-HOSTCC scripts/basic/fixdep HOSTCC scripts/kconfig/conf.o SHIPPED scripts/kconfig/zconf.tab.c SHIPPED scripts/kconfig/zconf.lex.c SHIPPED
-scripts/kconfig/zconf.hash.c HOSTCC scripts/kconfig/zconf.tab.o HOSTLD scripts/kconfig/conf## configuration written to .config#
+    ➜  ebf_6ull_linux git:(master) ✗ ls arch/arm/boot/dts/ | grep .dtb
 
-Linux内核的配置系统由三个部分组成，分别是：
+    imx6ull-14x14-evk-btwifi.dtb
+    imx6ull-14x14-evk.dtb
+    imx6ull-14x14-evk-emmc-43.dtb
+    imx6ull-14x14-evk-emmc-cam-dht11.dtb
+    imx6ull-14x14-evk-emmc.dtb
+    imx6ull-14x14-evk-emmc-hdmi.dtb
+    imx6ull-14x14-evk-emmc-wifi.dtb
+    imx6ull-14x14-evk-gpmi-weim-43.dtb
+    imx6ull-14x14-evk-gpmi-weim-cam-dht11.dtb
+    imx6ull-14x14-evk-gpmi-weim-hdmi.dtb
+    imx6ull-14x14-evk-gpmi-weim-wifi.dtb
 
-1. Makefile：分布在 Linux 内核源代码根目录及各层目录中，定义 Linux 内核的编译规则；
+**拷贝zImage与dtb**
 
-2. 配置文件：给用户提供配置选择的功能，如Kconfig文件定义了配置项，.config文件对配置项进行赋值；
+然后我们可以直接运行脚本 ``copy.sh`` 将内核镜像与设备树拷贝到 ``image`` 目录下
 
-3. 配置工具：包括配置命令解释器（对配置脚本中使用的配置命令进行解释）和配置用户界面（linux提供基于字符界面、基于 Ncurses 图形界面以及基于 Xwindows 图形界面的用户配置界面，各自对应于 make config、make menuconfig 和 make xconfig）。
+.. code:: bash
 
-读者如果想看我们提供的配置文件imx_v7_ebf_defconfig中修改了什么地方，可以通过make menuconfig命令来查看我们的配置，make menuconfig是一个基于文本选择的配置界面，推荐在字符终端下使用，make menuconfig运行的时候会从当前目录下导入
-.config文件的配置（如果没有找到 .config文件则会生成默认配置的 .config文件），而这个配置则是我们运行make ARCH=arm
-imx_v7_ebf_defconfig命令生成的，这就直接可以看到我们在imx_v7_ebf_defconfig的配置选择，可以通过键盘的“上”、“下”、“左”、“右”、“回车”、“空格”、“?”、“ESC”等按键进行选择配置，具体见图 30‑5。
+    ➜  ebf_6ull_linux git:(master) ✗ ./copy.sh
 
-|buildi006|
+    all kernel and DTB are copied to /home/jiejie/ebf_6ull_linux/image/
 
-图 30‑5 make menuconfig界面
+只编译设备树
+~~~~~~~~~~~~
 
-比如我们选择配置我们开发板的触摸屏驱动：Goodix I2C touchscreen，如果读者炸不到这个配置选项在哪里，可以利用make menuconfig中的搜索功能，在英文输入法状态下按下“/”则可以进行搜索，输入“Goodix”找到改配置选项的位置，具体见图
-30‑6。从图中可以很明显看出Goodix I2C touchscreen配置选项位于-> Device Drivers选项下的-> Input device support下的-> Generic input layer (needed for keyboard, mouse, ...)
-(INPUT [=y])选项下的-> Touchscreens 选项中，其实也可以按下“1”直接可以定位到对应的选项，然后选中[*]Goodix touchpanel GT9xx series 、<*> Goodix GT9xx touch controller auto update
-support 、<*> Goodix GT9xx Tools for debuging 、<*>Goodix I2C touchscreen即可，具体见图 30‑7。
+当然，如果你不想编译内核的话，只想编译设备树，那么可以在 ``make ARCH=arm -j10 CROSS_COMPILE=arm-linux-gnueabihf-`` 命令后面添加
+``dtbs`` 即可
 
-|buildi007|
+.. code:: bash
 
-图 30‑6 搜索功能
+    make ARCH=arm -j10 CROSS_COMPILE=arm-linux-gnueabihf- dtbs
 
-|buildi008|
+编译的设备树：
 
-图 30‑7 使能触摸屏配置
+-  imx6ull-14x14-evk.dts
+-  imx6ull-14x14-evk-btwifi.dts
+-  imx6ull-14x14-evk-emmc.dts
+-  imx6ull-14x14-evk-gpmi-weim-43.dts
+-  imx6ull-14x14-evk-emmc-43.dts
+-  imx6ull-14x14-evk-gpmi-weim-hdmi.dts
+-  imx6ull-14x14-evk-emmc-hdmi.dts
+-  imx6ull-14x14-evk-gpmi-weim-wifi.dts
+-  imx6ull-14x14-evk-emmc-wifi.dts
+-  imx6ull-14x14-evk-gpmi-weim-cam-dht11.dts
+-  imx6ull-14x14-evk-emmc-cam-dht11.dts
 
-再举个例子，如果想要在我们的开发板上使用DHT11测量温湿度（单总线协议），那么需要在内核中配置支持单总线协议：Dallas's 1-wire support，我们也照葫芦画瓢，先搜索到这个配置在哪个位置（时候搜索不到就直接找即可），它位于->Device Drivers 选项下的<*>
-Dallas's 1-wire suppor选项中，然后进入它的选项下进行选择即可，当配置完成后保存退出，就可以进行编译了，具体见图 30‑8。
+一键编译
+~~~~~~~~
 
-|buildi009|
+如果你什么都不想理会，那么这个一键编译内核与设备树就更适合你了，直接运行以下命令
 
-图 30‑8 选择单总线驱动
+::
 
-如果不需要修改配置，则可以直接编译，运行make ARCH=arm -j4 CROSS_COMPILE=arm-linux-gnueabihf- 命令直接编译，-j4是代表使用4个CPU进行编译，如果不选则默认使用一个CPU编译，而CPU的多少决定了编译的时间，根据自身情况决定即可，在运行这个命令后
-，可以看到中断输出一系列编译信息，而在编译的最后会告诉我们编译成功，镜像存在arch/arm/boot/目录下，具体见：（已删减绝大部分编译输出的信息）。
+    ./build.sh
 
-命令
+或者...
 
-embedfire @embedfire_dev:~/imx-linux$ make ARCH=arm -j4 CROSS_COMPILE=arm-linux-gnueabihf-
+::
 
-输出
+    ./build.sh 5.0
 
-···
+生成的内核镜像与设备树均被拷贝到 ``image`` 目录下。
+内核模块相关均被安装到 ``my_lib/lib/``
+目录下的 ``modules`` 文件夹下，可以直接替换掉 ``rootfs(根文件系统)`` 中的 ``/lib/modules/`` 。
 
-OBJCOPY arch/arm/boot/zImage Kernel: arch/arm/boot/zImage is ready
+``build.sh`` 脚本默认编译5.0寸屏幕的内核镜像，如果需要4.3寸屏幕的内核镜像，则可以使用以下命令去编译:
 
-···
+::
 
-这个命令编译的不仅仅是内核，还会编译设备树，设备树编译后产生的.dtb文件存在arch/arm/boot/dts/目录下，我们可以通过ls arch/arm/boot/dts/ \| grep .dtb命令查看该目录下的所有设备树：（已删减，仅显示imx6ull相关的设备树）。
+    ./build.sh 4.3
 
-命令
+修改LOGO
+--------
 
-embedfire @embedfire_dev:~/imx-linux$ ls arch/arm/boot/dts/ \| grep .dtb
+其实在野火开发板的固件中，uboot是没有logo的，因为将uboot的logo删掉了，因为在内核有logo，而uboot到内核的时间非常短（已经将uboot等待
+3S
+时间去掉了），所以直接使用内核的logo会更好，那么如果想要使用内核的logo，就得自己去修改内核的logo，下面就教大家如何去做。
 
-输出
+准备一张图片
+~~~~~~~~~~~~
 
-imx6ull-14x14-ddr3-arm2-adc.dtbimx6ull-14x14-ddr3-arm2-cs42888.dtbimx6ull-14x14-ddr3-arm2.dtbimx6ull-14x14-ddr3-arm2-ecspi.dtbimx6ull-14x14-ddr3-arm2-
-emmc.dtbimx6ull-14x14-ddr3-arm2-epdc.dtbimx6ull-14x14-ddr3-arm2-flexcan2.dtbimx6ull-14x14-ddr3-arm2-gpmi-
-weim.dtbimx6ull-14x14-ddr3-arm2-lcdif.dtbimx6ull-14x14-ddr3-arm2-ldo.dtbimx6ull-14x14-ddr3-arm2-qspi-all.dtbimx6ull-14x14-ddr3-arm2-qspi.dtbimx6ull-14
-x14-ddr3-arm2-tsc.dtbimx6ull-14x14-ddr3-arm2-uart2.dtbimx6ull-14x14-ddr3-arm2-usb.dtbimx6ull-14x14-ddr3-arm2-wm8958.dtbimx6ull-14x14-evk-
-btwifi.dtbimx6ull-14x14-evk.dtbimx6ull-14x14-evk-emmc-43.dtbimx6ull-14x14-evk-emmc-50-70-dht11.dtbimx6ull-14x14-evk-
-emmc-50-70-dht11-leds.dtbimx6ull-14x14-evk-emmc-50-70-dht11-update.dtbimx6ull-14x14-evk-emmc-50-70.dtbimx6ull-14x14-evk-emmc.dtbimx6ull-14x14-evk-
-gpmi-weim-43.dtbimx6ull-14x14-evk-gpmi-weim-50-70-dht11.dtbimx6ull-14x14-evk-gpmi-weim-50-70-dht11-leds.dtbimx6ull-14x14-evk-gpmi-
-weim-50-70-dht11-update.dtbimx6ull-14x14-evk-gpmi-weim-50-70.dtbimx6ull-14x14-evk-gpmi-weim.dtbimx6ull-14x14-evk-usb-certi.dtb
+我们可以随便准备一张图片，比如我们就选择ubuntu的logo吧，将它制作成适合显示屏大小的图片，比如5寸屏幕的分辨率是800*480：
+
+.. figure:: media/building_kernel006.png
+   :alt: building_kernel006
+
+   building_kernel006
+
+然后将其保存为 **256色（即8位色）的bpm格式的图片** ，可以在Windows下或者Linux虚拟机下编辑：
+
+.. figure:: media/building_kernel007.png
+   :alt: building_kernel007
+
+   building_kernel007
+
+转换为ppm格式的图片
+~~~~~~~~~~~~~~~~~~~
+
+然后在Linux下使用以下脚本将其转换为ppm格式的文件，为什么是ppm格式呢？因为这是编译Linux内核必要的文件格式，想要修改logo，就要这种格式的文件，它必须是 **256色（即8位色）的bpm格式的图片** 转换而成的。
+
+.. code:: bash
+
+    #!/bin/bash
+    if [ " $1" == " " ];
+    then
+        echo "usage:$0 bmp_file"
+        exit 0
+    fi
+
+    if [ -f "$1" ]
+    then
+        echo $1
+    else
+        echo "no find file [$1]"
+        exit 0
+    fi
+
+    name=${1%%.*}
+    bmptopnm $1 > $name.pnm
+    pnmquant 224 $name.pnm > $name.clut224.pnm
+    pnmtoplainpnm $name.clut224.pnm > $name.ppm
+    rm $name.pnm $name.clut224.pnm 
+
+这是bmp文件转换ppm格式文件的脚本，可以将其写入一个叫 ``bmp2ppm.sh`` 脚本文件中，并且赋予其可执行的权限（使用
+``chmod +x bmp2ppm.sh``
+命令即可），它主要是使用linux系统中的工具转换，如果系统中没有相关工具，则根据提示使用 ``apt install`` 命令进行安装即可。
+
+然后将准备好的bmp文件拷贝到制作ppm的工作目录下，使用 ``bmp2ppm.sh`` 脚本将其转化为ppm文件，具体操作如下：
+
+.. code:: bash
+
+    ➜  bmp2ppm git:(master) ✗ ls
+    bmp2ppm.sh  README.md  ubuntu.bmp
+
+    ➜  bmp2ppm git:(master) ✗ ./bmp2ppm.sh ubuntu.bmp 
+    ubuntu.bmp
+    bmptopnm: Windows BMP, 800x480x8
+    bmptopnm: WRITING PPM IMAGE
+    pnmcolormap: making histogram...
+    pnmcolormap: 29 colors found
+    pnmcolormap: Image already has few enough colors (<=224).  Keeping same colors.
+    pnmremap: 29 colors found in colormap
+
+    ➜  bmp2ppm git:(master) ✗ ls
+    bmp2ppm.sh  README.md  ubuntu.bmp  ubuntu.ppm
+
+替换原本的logo文件
+~~~~~~~~~~~~~~~~~~
+
+在转换完成后，当前目录将出现对应的ppm文件，我们将其拷贝到linux内核源码的 ``ebf_6ull_linux/drivers/video/logo`` 目录下，因为我们的logo是存放在此处的，野火提供的logo：
+
+-  默认编译的logo：logo_dec_clut224.ppm
+-  5寸触摸屏logo：logo_dec_clut224_5.0.ppm
+-  4.3寸触摸屏logo：logo_dec_clut224_4.3.ppm
+
+然后将其重命名为你想替换的logo即可， **注意** ，5寸触摸屏logo与4.3寸触摸屏logo是一键编译使用的，它在一键编译过程中会替换掉默认的logo，如果你只替换了默认编译的logo，但是使用了一键编译脚本，那么你替换的logo将被一键编译脚本修改，编译产生的内核将不会存在你的logo。
+
+修改启动脚本
+~~~~~~~~~~~~
+
+替换完成后，重新编译内核，并且烧录到开发板上，不过此时会出现一个现象，logo一闪而过，这是因为内核启动后，会执行文件系统的启动脚本，而此时文件系统的启动脚本中 ``/etc/init.d/psplash.sh`` 会去执行相应的应用程序 ``/usr/bin/psplash`` ，这就是绘制开机的进度条与背景，那么你的开机logo将被刷掉，而只要不让这个启动脚本运行这个 ``/usr/bin/psplash`` 应用程序就可以解决问题了，那么我们在开发板中修改启动脚本 ``/etc/init.d/psplash.sh`` ：
+
+.. code:: bash
+
+    #!/bin/sh 
+    ### BEGIN INIT INFO
+    # Provides:             psplash
+    # Required-Start:
+    # Required-Stop:
+    # Default-Start:        S
+    # Default-Stop:
+    ### END INIT INFO
+
+    read CMDLINE < /proc/cmdline
+    for x in $CMDLINE; do
+            case $x in
+            psplash=false)
+                    echo "Boot splashscreen disabled" 
+                    exit 0;
+                    ;;
+            esac
+    done
+
+    export TMPDIR=/mnt/.psplash
+    mount tmpfs -t tmpfs $TMPDIR -o,size=40k
+
+    rotation=0
+    if [ -e /etc/rotation ]; then
+            read rotation < /etc/rotation
+    fi
+
+    /usr/bin/psplash --angle $rotation &
+
+将其最后一行屏蔽掉：
+
+.. code:: bash
+
+    # /usr/bin/psplash --angle $rotation &
+
+或者直接禁止启动该脚本，在终端执行以下命令：
+
+.. code:: bash
+
+    /usr/bin/psplash stop
+
+然后重启开发板，就可以看见你的logo了。
 
 烧录自己编译的内核到开发板
-~~~~~~~~~~~~~
-
-那么经过编译得到的zImage与设备树都可以烧录到我们的开发板中，比如我们选择zImage与imx6ull-14x14-evk-gpmi-weim-50-70-dht11-leds.dtb文件替换掉28.3 小节中的烧录镜像与设备树，完成烧录后即可看到内核启动完成，具体见图 30‑9。
-
-|buildi010|
-
-图 30‑9 替换镜像与设备树
-
-当内核启动后，我们登陆root用户，就可以通过cat /proc/version命令查看内核版本：
-
-imx6ull14x14evk login: rootroot@imx6ull14x14evk:~# cat /proc/versionLinux version 4.1.15-2.1.0-00162-gd815328d0504-dirty (embedfire @embedfire_dev)
-(gcc version 7.4.0 (Ubuntu/Linaro 7.4.0-1ubuntu1~18.04.1) ) #2 SMP PREEMPT Tue Aug 27 07:46:06 UTC 2019
-
-可能会增加个编译官方内核的
-
-.. |buildi010| image:: media/building_kernel002.png
-   :width: 5.76806in
-   :height: 4.17052in
-.. |buildi003| image:: media/building_kernel003.png
-   :width: 5.76806in
-   :height: 3.6958in
-.. |buildi004| image:: media/building_kernel004.png
-   :width: 5.76806in
-   :height: 3.71095in
-.. |buildi005| image:: media/building_kernel005.png
-   :width: 5.76806in
-   :height: 4.16798in
-.. |buildi006| image:: media/building_kernel006.png
-   :width: 6.06111in
-   :height: 4.32in
-.. |buildi007| image:: media/building_kernel007.png
-   :width: 5.76806in
-   :height: 3.6284in
-.. |buildi008| image:: media/building_kernel008.png
-   :width: 5.744in
-   :height: 4.57996in
-.. |buildi009| image:: media/building_kernel009.png
-   :width: 5.76806in
-   :height: 4.59066in
-.. |buildi010| image:: media/building_kernel010.png
-   :width: 5.76806in
-   :height: 3.51994in
+--------------------------
+
+那么经过编译得到的 ``zImage`` 与设备树都可以烧录到我们的开发板中，比如我们选择 ``zImage`` 与 ``imx6ull-14x14-evk-emmc-cam-dht11.dts`` 文件替换掉前面小节中的烧录镜像与设备树，完成烧录后即可看到内核启动完成。
+
+当内核启动后，我们登陆root用户，就可以通过 ``cat /proc/version`` 命令查看内核版本：
+
+.. code:: bash
+
+    imx6ull14x14evk login: root 
+    root@imx6ull14x14evk:~# cat /proc/version 
+    Linux version 4.1.15-2.1.0-00162-gd815328d0504-dirty (embedfire @embedfire_dev) (gcc version 7.4.0 (Ubuntu/Linaro 7.4.0-1ubuntu1~18.04.1) ) #2 SMP PREEMPT Tue Aug 27 07:46:06 UTC 2019
+
+内核配置选项（部分）
+--------------------
+
+运行 ``make ARCH=arm menuconfig``
+命令打开配置界面，根据自身需求配置即可！
+
+**触摸屏驱动：**
+
+.. code:: bash
+
+     Prompt: Goodix I2C touchscreen   
+      Location:            
+       -> Device Drivers         
+          -> Input device support  
+           -> Generic input layer (needed for keyboard, mouse, ...) (INPUT [=y]) 
+     (1)       -> Touchscreens (INPUT_TOUCHSCREEN [=y])  
+     #这个也要使能
+        [*]   Goodix touchpanel GT9xx series 
+        <*>     Goodix GT9xx touch controller auto update support  
+        <*>     Goodix GT9xx Tools for debuging     
+
+**单总线驱动：**
+
+.. code:: bash
+
+     Prompt: Dallas's 1-wire support     
+     Location:                         
+      (1) -> Device Drivers          
+      [*]   Userspace communication over connector (NEW)    
+
+**添加MPU6050的支持：**
+
+.. code:: bash
+
+    Prompt: Invensense MPU6050 devices      
+    Location:  
+      -> Device Drivers               
+        -> Industrial I/O support (IIO [=y])               
+    (1)     -> Inertial measurement units   
+              <*> Invensense MPU6050 devices   
+
+**WIFI蓝牙**
+
+.. code:: bash
+
+    Location:  
+      -> Device Drivers               
+        -> Network device support                                         
+           -> Wireless LAN
+              ->
+
+     <*>   Broadcom FullMAC wireless cards support                        
+            (/lib/firmware/bcm/AP6236/Wi-Fi/fw_bcm43436b0.bin) Firmware path     
+             (/lib/firmware/bcm/AP6236/Wi-Fi/nvram_ap6236.txt) NVRAM path    
+
+    #HCI串口配置也要选择
+        -> Device Drivers               
+        -> Network device support                                         
+           -> Wireless LAN
+              ->Bluetooth subsystem support   
+                  ->Bluetooth device drivers   
+                      <*> HCI USB driver     
+                      [*]   Broadcom protocol support  
+
+      -> Networking support (NET [=y])     
+        -> Bluetooth subsystem support (BT [=y]) 
+          -> Bluetooth device drivers    
+            <*> HCI USB driver    
+            [*]   Broadcom protocol support  
+
+**PPP点对点拨号：**
+
+所有PPP相关的都选中
+
+.. code:: bash
+
+     Prompt: PPP (point-to-point protocol) support              
+      Location:          
+      -> Device Drivers 
+        (1)   -> Network device support (NETDEVICES [=y])       
+
+**蓝牙和HCI子系统**
+
+.. code:: bash
+
+        -> Networking support (NET [=y])              
+         -> Bluetooth subsystem support (BT [=y])   
+          (1)     -> Bluetooth device drivers   
+      --- RF switch subsystem support                                         
+              [*]   RF switch input support  
+              <*>   Generic rfkill regulator driver
+              <*>   GPIO RFKILL driver            
+
diff --git a/documentation/building_image/building_rootfs.rst b/documentation/building_image/building_rootfs.rst
index 140d84292d90f2752de2bf9775988d31ab00dcd0..05eb7d8d8f7a3e0bbb35ccda7393b8dfbf505c96 100644
--- a/documentation/building_image/building_rootfs.rst
+++ b/documentation/building_image/building_rootfs.rst
@@ -1,262 +1,255 @@
-.. vim: syntax=rst
-
-制作根文件系统
--------
-
-本章节内容处于开发笔记状态，还待整理至最终版的教程。
-
-本章节内容处于开发笔记状态，还待整理至最终版的教程。
-
-文件系统知识回顾
-~~~~~~~~
-
-在介绍制作文件系统之前，我们先来看一下Linux是如何存储数据的。其实在第18章 也介绍了文件系统相关的知识，如果还未理解的读者可以回过头来去看一下文件系统的知识。一般情况下，字符设备以串行方式存储和获取数据，串口是最典型的字符设备；而块设备会一次存取或者获取大小相同的一块区域内的数据。例如，一个硬
-盘控制器可以向物理存储介质上指定可寻址地址，一次传送或接收512字节的数据，文件系统正是建立在块设备之上的。
-
-文件系统是存在于一个物理设备的逻辑分区之上的。分区就是对一个物理介质（磁盘、闪存）的逻辑划分，该物理介质上的数据在给定分区类型上按照特定的规则进行组织，物理设备可以只有一个独立分区包含所有可用空间，也可以被划分为多个分区以满足特定需要，就好比我们电脑的磁盘，划分为多个分区以用于不同的需求。
-
-简单了解了文件系统的概念，那么我们就动手制作一个文件系统。
-
-讲解buildroot构建根文件系统的原理
-~~~~~~~~~~~~~~~~~~~~~
-
-文件系统通常要包含很多第三方软件，比如busybox，tslib，qt，vim，交叉编译工具等，为了避免繁杂的移植工作，buildroot应运而生。用户可以直接通过make
-menuconfig配置自己需要的功能，把不需要的功能去掉，再执行make指令编译，buildroot就会自动从指定的服务器上下载源码包，自动编译，自动搭建成我们所需要的嵌入式根文件系统。
-
-buildroot的文件系统（rootfs）构建流程有一个框架，有些部分是buildroot本身就集成的，但还是有些细节需要自己来实现，我们需要按照格式写脚本，提供必要的构建细节，并且配置整个系统，总之，rootfs是Buildroot中最为复杂的部分。
-
-一般来说，buildroot构建文件系统的运作过程如下：
-
-1. buildroot将system/skeleton/目录下的内容拷贝到output/target目录下下作为rootfs的模板。
-
-2. 将output/staging/目录下的工具链中动态库拷贝到output/target/对应的目录下。
-
-3. 分别编译每一个应用的package，并将生成的动态库和bin文件install到output/target/对应的目录下。
-
-4. 将package/initscripts/目录下的系统启动脚本install到output/target/对应的目录下。
-
-5. 构建fakeroot环境，在fakeroot环境下修改output/target/中对应的目录文件权限，制作dev节点，并根据用户的配置制作出rootfs 镜像。
-
-fakeroot是一个主机上使用的软件包，它会被buildroot下载编译，用于为构建rootfs提供一个虚拟的root权限环境，只有在root权限下，才能把output/target/中的目录和文件变成root用户，并创建dev节点。有了fakeroot环境，系统构建者无需获取主机的root权限，
-也能在fakeroot下把文件改为root用户，并制作root方式。
-
-讲解uClibc与glibc的差异
-~~~~~~~~~~~~~~~~~
-
-glibc和libc都是Linux下的C函数库，libc是Linux下的ANSI C的函数库；glibc是Linux下的GUN C的函数库；GNU C是一种ANSI C的扩展实现。ANSI
-C是基本的C语言函数库，包含了C语言最基本的库函数。在写程序时，需要用到很多c语言的库函数，这些所有的库函数整合起来，就是对应的C语言（标准）函数库。
-
-目前在普通GNU/Linux系统中所用的C语言标准库，叫做glibc。它的功能很全，函数很多，但是就是因为代码太多，编译出来的函数库的大小也很大，占用的资源也很多，可以简单地认为glibc就是为了实现完整功能设计的。
-
-由于在嵌入式系统中，也需要C语言写代码实现特定功能，因此需要用到C语言函数库，但是由于嵌入式系统中，一般资源比较有限，所以不适合直接使用太占用资源的glibc。uClibc
-是一个面向嵌入式Linux系统的小型的C标准库，最初uClibc是为了支持uClinux而开发，这是一个不需要内存管理单元（MMU）的Linux版本。uClibc比一般用于Linux发行版的C库GNU C Library (glibc)要小得多，
-因此uClibc专注于嵌入式Linux，除此之外uClibc比glibc更可配置，这意味着开发人员可以根据功能与空间需求进行裁剪。
-
-简单总结以下几点：
-
-1. uClibc比glibc占用的资源小，虽然uClibc和glibc在已有的接口上是兼容的，而且采用uClibc编译应用程序比采用glibc编译应用程序要更方便，但是uClibc并没有包括glibc中的所有接口实现，因此有些应用可能在uClibc中不能编译。
-
-2. uClibc在可配置性上比glibc要好。
-
-提示：关于uClibc与glibc更多的差异比较信息请看\ http://www.etalabs.net/compare_libcs.html\ 。
-
-使用buildroot制作自己需要的文件系统
-~~~~~~~~~~~~~~~~~~~~~~
-
-关于buildroot的简单实用也在第32章 讲解过了，此处就讲解一下关于文件系统的内容即可。（注意：必须先按照第32章 的内容配置好内核及uboot的编译内容，否则无法从SD卡启动系统）。
-
-首先运行以下命令进入配置选项：
-
-命令
-
-make menuconfig
-
-找到System configuration(系统配置)选项，进入该选项中，如图 33‑1所示。
-
-|buildi002|
-
-图 33‑1 System configuration(系统配置)
-
-我们可以简单介绍一下这个选项的中的部分参数及其意义（ []内容为设置的值）：
-
--  Root FS skeleton (default target skeleton) ： 根文件系统框架 [默认目标框架]
-
--  (buildroot) System hostname ：系统主机名字(自取任意) [buildroot]
-
--  (Welcome to ixm6ull Buildroot!) System banner：系统开机提示 [Welcome to ixm6ull Buildroot!]
-
--  Passwords encoding (sha-256)：密码编码 [sha-256格式编码]
-
--  Init system (busybox) --->：初始化系统方案 [busybox]
-
--  /dev management (Dynamic using devtmpfs only) ：dev管理方案 [Dynamic using devtmpfs only]
-
--  (system/device_table.txt) Path to the permission tables ：权限表路径
-
--  [ ] support extended attributes in device tables：支持设备表中的扩展属性
-
--  [ ] Use symlinks to /usr for /bin, /sbin and /lib：是否将/bin,/sbin,/lib链接到/usr
-
--  [*] Enable root login with password：使能root登陆密码
-
--  () Root password：设置root密码
-
--  /bin/sh (bash) ：选择shell类型 [bash]
-
--  [*] Run a getty (login prompt) after boot：启动后运行getty(登录提示)
-
--  [*] remount root filesystem read-write during boot ：在引导期间安装根文件系统支持读和写
-
--  (eth0) Network interface to configure through DHCP：设置DHCP配置的网络接口 [eth0]
-
--  (/bin:/sbin:/usr/bin:/usr/sbin) Set the system's default PATH：设置系统的默认路径
-
--  [*] Purge unwanted locales：清除不需要的区域设置
-
--  (C en_US) Locales to keep：要保留的语言环境
-
--  () Generate locale data：生成区域设置数据
-
--  [ ] Enable Native Language Support (NLS) ：启用本地语言支持（NLS）
-
--  -*- Install timezone info ：安装时区信息
-
--  (default) timezone list：时区清单 [典型]
-
--  (Etc/UTC) default local time ：用户表的路径
-
--  () Path to the users tables
-
--  () Root filesystem overlay directories：根文件系统覆盖目录
-
--  () Custom scripts to run before creating filesystem images：在创建文件系统映像之前运行的自定义脚本
-
--  () Custom scripts to run inside the fakeroot environment：自定义脚本在fakeroot(模拟root权限)环境中运行
-
--  (board/……) Custom scripts to run after creating filesystem images ：创建文件系统映像后运行的自定义脚本
-
--  () Extra arguments passed to custom scripts：传递给自定义脚本的额外参数
-
-在这里就重点提一下几点配置：
-
-1. Root FS skeleton：我们建议选择默认的根文件系统框架，因为默认的框架是非常小的，可以适应绝大部分的场合，当然，占用资源小也代表功能仅有一点点，读者可以自己往文件系统添加需要的功能，这是可以的。除此之外读者也可以选择自己的根文件系统框架（custom target skeleton）。
-
-2. Init system：初始化系统方案，目前buildroot中提供2种方案，一种是BusyBox：系统的init程序将在启动时读取/etc/inittab文件，以了解该做什么，默认inittab存储在./package/busybox/inittab中；inittab除了安装几个重要的文件系统之外
-   ，还要启动/etc/init.d/rcS中的shell脚本，并启动一个getty程序(提供一个登录提示)。另一种是systemV，使用传统sysvinit程序，之前大多数台式机Linux发行版都使用该方案，现在有些变为了Upstart或Systemd，在构建文件系统的时候会在/ect目录下会生成in
-   it.d、rc0.d、rc1.d、rc2.d、rc3.d、rc4.d、rc5.d、rc6.d、rc.loacl等目录和脚本文件，init.d目录下包含的是真正的脚本。
-
-3. /dev management ：/dev设备文件的管理方式，可选选项有四个：
-
-Static using device table: 使用静态的设备表，/dev将根据system/device_table \_dev.txt的内容创建设备，进入系统添加或删除设备时，无法自动更新；
-
-Dynamic using devtmpfs only:在系统启动过程中，会动态生成/dev文件，进入系统添加或删除设备时，无法自动更新；
-
-Dynamic using devtmpfs + mdev:在前面devtmpfs的基础上加入mdev用户空间实用程序，进入系统添加或删除设备时，可以自动更新，自动创建规则在/etc/mdev.conf;
-
-Dynamic using devtmpfs + eudev:在前面devtmpfs的基础上加入eudev用户空间守护程序，eudev是udev的独立版本，是Systemd的一部分，提供更多的功能也更占用资源；
-
-4. /bin/sh (bash)：选择shell类型，一般选择bash即可，用户的体验会很好。除了bash外，还有很多shell工具，比如这里可选busybox自带的shell、小巧但功能很少的dash、高效紧凑的mksh、功能强大体积也稍大的zsh。
-
-5. Root filesystem overlay directories：根文件覆盖目录，如果你想将某些文件添加到文件系统中，那么可以按照根文件的目录框架进行添加到对应的路径中，在文件系统构建的时候，会将对应的文件添加到文件系统中，如果出现相同的文件则覆盖。
-
-我们还需要配置一下Filesystem images(文件系统)选项，具体见图 33‑2 。
-
-|buildi003|
-
-图 33‑2 Filesystem images(文件系统)
-
-这些配置的含义如下：
-
--  [ ] axfs root filesystem：XFS格式根文件系统
-
--  [ ] btrfs root filesystem ：btrfs格式根文件系统
-
--  [ ] cloop root filesystem for the target device：clop方式压缩根文件系统
-
--  [ ] cpio the root filesystem (for use as an initial RAM filesystem) ：cpio方式压缩根文件系统(用作初始RAM文件系统)
-
--  [ ] cramfs root filesystem：cramf格式根文件系统
-
--  [*] ext2/3/4 root filesystem ：ext2/3/4格式根文件系统
-
--  ext2/3/4 variant (ext4) ：ext4格式根文件系统
-
--  () filesystem label ：文件系统标签
-
--  (200M) exact size ：根文件系统空间大小[200M]
-
--  (0) exact number of inodes (leave at 0 for auto calculation) ：确切的inode数(从0开始自动计算)
-
--  (5) reserved blocks percentage：保留块百分比 (保留的供root使用,默认5%)
-
--  (-O ^64bit) additional mke2fs options ：额外的mke2fs选项 [禁用64位文件系统]
-
--  Compression method (no compression) ：压缩方式 [无压缩]
-
--  [ ] f2fs root filesystem ：f2fs格式根文件系统
-
--  [ ] initial RAM filesystem linked into linux kernel：初始RAM文件系统链接到Linux内核
-
--  [ ] jffs2 root filesystem：jffs2格式根文件系统
-
--  [ ] romfs root filesystem：romfs格式根文件系统
-
--  [ ] squashfs root filesystem ：squashfs格式根文件系统
-
--  [*] tar the root filesystem：tar压缩格式根文件系统
-
--  Compression method (no compression) ：压缩方式 [无压缩]
-
--  () other random options to pass to tar：传递给tar的其他选项
-
--  [ ] ubi image containing an ubifs root filesystem：ubifs格式根文件系统包含ubi镜像
-
--  [ ] ubifs root filesystem ：ubifs格式根文件系统
-
--  [ ] yaffs2 root filesystem：yaffs2格式根文件系统
-
-我们就简单设置一下文件系统的大小（256M），以及根文件系统的格式（tar压缩格式）即可。
-
-当配置完毕后，我们可以选择对应的软件包添加到我们的系统中，比如Python3等，这里就不再重复赘述。然后使用make命令进行编译，就会生成对应的文件系统了，生成的镜像文件在output/images/目录下。
-
-命令
-
-make
-
-烧录自己制作的根文件系统
-~~~~~~~~~~~~
-
-将生成的文件系统烧录到我们的开发板上，我们可以直接通过制作SD卡镜像的方式将文件系统烧录到SD卡，然后让开发板从SD卡启动。
-
-首先得到SD卡的文件系统镜像，如图 33‑3所示。
-
-|buildi004|
-
-图 33‑3 SD卡镜像
-
-然后通过SD卡镜像制作软件Etcher将该镜像烧写到SD卡中，如图 33‑4所示，Etcher软件可以从Etcher官网下载：\ https://www.balena.io/etcher/\ 。该软件的使用方式非常简单，此处就不做讲解。
-
-|buildi005|
-
-图 33‑4 SD卡镜像制作软件Etcher
-
-当制作成功后，将SD卡插入开发板中，并且将拨码开关的2/5/8打到ON档，然后给开发板上电就可以看到开发板正常启动。
-
-给开发板移植debian发行版
----------------
-
-制作ubuntu core版本镜像
------------------
-
-.. |buildi002| image:: media/building_rootfs002.png
-   :width: 5.76806in
-   :height: 4.2879in
-.. |buildi003| image:: media/building_rootfs003.png
-   :width: 4.76155in
-   :height: 5.05224in
-.. |buildi004| image:: media/building_rootfs004.png
-   :width: 5.76806in
-   :height: 4.62276in
-.. |buildi005| image:: media/building_rootfs005.png
-   :width: 5.76806in
-   :height: 3.46306in
+.. vim: syntax=rst
+
+制作根文件系统
+--------------
+
+在介绍制作文件系统之前，我们先来看一下Linux是如何存储数据的。其实在第18章 也介绍了文件系统相关的知识，如果还未理解的读者可以回过头来去看一下文件系统的知识。一般情况下，字符设备以串行方式存储和获取数据，串口是最典型的字符设备；而块设备会一次存取或者获取大小相同的一块区域内的数据。例如，一个硬
+盘控制器可以向物理存储介质上指定可寻址地址，一次传送或接收512字节的数据，文件系统正是建立在块设备之上的。
+
+文件系统是存在于一个物理设备的逻辑分区之上的。分区就是对一个物理介质（磁盘、闪存）的逻辑划分，该物理介质上的数据在给定分区类型上按照特定的规则进行组织，物理设备可以只有一个独立分区包含所有可用空间，也可以被划分为多个分区以满足特定需要，就好比我们电脑的磁盘，划分为多个分区以用于不同的需求。
+
+简单了解了文件系统的概念，那么我们就动手制作一个文件系统。
+
+讲解buildroot构建根文件系统的原理
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+文件系统通常要包含很多第三方软件，比如busybox，tslib，qt，vim，交叉编译工具等，为了避免繁杂的移植工作，buildroot应运而生。用户可以直接通过make
+menuconfig配置自己需要的功能，把不需要的功能去掉，再执行make指令编译，buildroot就会自动从指定的服务器上下载源码包，自动编译，自动搭建成我们所需要的嵌入式根文件系统。
+
+buildroot的文件系统（rootfs）构建流程有一个框架，有些部分是buildroot本身就集成的，但还是有些细节需要自己来实现，我们需要按照格式写脚本，提供必要的构建细节，并且配置整个系统，总之，rootfs是Buildroot中最为复杂的部分。
+
+一般来说，buildroot构建文件系统的运作过程如下：
+
+1. buildroot将system/skeleton/目录下的内容拷贝到output/target目录下下作为rootfs的模板。
+
+2. 将output/staging/目录下的工具链中动态库拷贝到output/target/对应的目录下。
+
+3. 分别编译每一个应用的package，并将生成的动态库和bin文件install到output/target/对应的目录下。
+
+4. 将package/initscripts/目录下的系统启动脚本install到output/target/对应的目录下。
+
+5. 构建fakeroot环境，在fakeroot环境下修改output/target/中对应的目录文件权限，制作dev节点，并根据用户的配置制作出rootfs 镜像。
+
+fakeroot是一个主机上使用的软件包，它会被buildroot下载编译，用于为构建rootfs提供一个虚拟的root权限环境，只有在root权限下，才能把output/target/中的目录和文件变成root用户，并创建dev节点。有了fakeroot环境，系统构建者无需获取主机的root权限，
+也能在fakeroot下把文件改为root用户，并制作root方式。
+
+讲解uClibc与glibc的差异
+~~~~~~~~~~~~~~~~~~~~~~~~~
+
+glibc和libc都是Linux下的C函数库，libc是Linux下的ANSI C的函数库；glibc是Linux下的GUN C的函数库；GNU C是一种ANSI C的扩展实现。ANSI
+C是基本的C语言函数库，包含了C语言最基本的库函数。在写程序时，需要用到很多c语言的库函数，这些所有的库函数整合起来，就是对应的C语言（标准）函数库。
+
+目前在普通GNU/Linux系统中所用的C语言标准库，叫做glibc。它的功能很全，函数很多，但是就是因为代码太多，编译出来的函数库的大小也很大，占用的资源也很多，可以简单地认为glibc就是为了实现完整功能设计的。
+
+由于在嵌入式系统中，也需要C语言写代码实现特定功能，因此需要用到C语言函数库，但是由于嵌入式系统中，一般资源比较有限，所以不适合直接使用太占用资源的glibc。uClibc
+是一个面向嵌入式Linux系统的小型的C标准库，最初uClibc是为了支持uClinux而开发，这是一个不需要内存管理单元（MMU）的Linux版本。uClibc比一般用于Linux发行版的C库GNU C Library (glibc)要小得多，
+因此uClibc专注于嵌入式Linux，除此之外uClibc比glibc更可配置，这意味着开发人员可以根据功能与空间需求进行裁剪。
+
+简单总结以下几点：
+
+1. uClibc比glibc占用的资源小，虽然uClibc和glibc在已有的接口上是兼容的，而且采用uClibc编译应用程序比采用glibc编译应用程序要更方便，但是uClibc并没有包括glibc中的所有接口实现，因此有些应用可能在uClibc中不能编译。
+
+2. uClibc在可配置性上比glibc要好。
+
+提示：关于uClibc与glibc更多的差异比较信息请看 http://www.etalabs.net/compare_libcs.html 。
+
+使用buildroot制作自己需要的文件系统
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+关于buildroot的简单实用也在第32章 讲解过了，此处就讲解一下关于文件系统的内容即可。（注意：必须先按照第32章 的内容配置好内核及uboot的编译内容，否则无法从SD卡启动系统）。
+
+首先运行以下命令进入配置选项：
+
+命令
+
+make menuconfig
+
+找到System configuration(系统配置)选项，进入该选项中，如图 33‑1所示。
+
+|buildi002|
+
+图 33‑1 System configuration(系统配置)
+
+我们可以简单介绍一下这个选项的中的部分参数及其意义（ []内容为设置的值）：
+
+-  Root FS skeleton (default target skeleton) ： 根文件系统框架 [默认目标框架]
+
+-  (buildroot) System hostname ：系统主机名字(自取任意) [buildroot]
+
+-  (Welcome to ixm6ull Buildroot!) System banner：系统开机提示 [Welcome to ixm6ull Buildroot!]
+
+-  Passwords encoding (sha-256)：密码编码 [sha-256格式编码]
+
+-  Init system (busybox) --->：初始化系统方案 [busybox]
+
+-  /dev management (Dynamic using devtmpfs only) ：dev管理方案 [Dynamic using devtmpfs only]
+
+-  (system/device_table.txt) Path to the permission tables ：权限表路径
+
+-  [ ] support extended attributes in device tables：支持设备表中的扩展属性
+
+-  [ ] Use symlinks to /usr for /bin, /sbin and /lib：是否将/bin,/sbin,/lib链接到/usr
+
+-  [*] Enable root login with password：使能root登陆密码
+
+-  () Root password：设置root密码
+
+-  /bin/sh (bash) ：选择shell类型 [bash]
+
+-  [*] Run a getty (login prompt) after boot：启动后运行getty(登录提示)
+
+-  [*] remount root filesystem read-write during boot ：在引导期间安装根文件系统支持读和写
+
+-  (eth0) Network interface to configure through DHCP：设置DHCP配置的网络接口 [eth0]
+
+-  (/bin:/sbin:/usr/bin:/usr/sbin) Set the system's default PATH：设置系统的默认路径
+
+-  [*] Purge unwanted locales：清除不需要的区域设置
+
+-  (C en_US) Locales to keep：要保留的语言环境
+
+-  () Generate locale data：生成区域设置数据
+
+-  [ ] Enable Native Language Support (NLS) ：启用本地语言支持（NLS）
+
+-  -*- Install timezone info ：安装时区信息
+
+-  (default) timezone list：时区清单 [典型]
+
+-  (Etc/UTC) default local time ：用户表的路径
+
+-  () Path to the users tables
+
+-  () Root filesystem overlay directories：根文件系统覆盖目录
+
+-  () Custom scripts to run before creating filesystem images：在创建文件系统映像之前运行的自定义脚本
+
+-  () Custom scripts to run inside the fakeroot environment：自定义脚本在fakeroot(模拟root权限)环境中运行
+
+-  (board/……) Custom scripts to run after creating filesystem images ：创建文件系统映像后运行的自定义脚本
+
+-  () Extra arguments passed to custom scripts：传递给自定义脚本的额外参数
+
+在这里就重点提一下几点配置：
+
+1. Root FS skeleton：我们建议选择默认的根文件系统框架，因为默认的框架是非常小的，可以适应绝大部分的场合，当然，占用资源小也代表功能仅有一点点，读者可以自己往文件系统添加需要的功能，这是可以的。除此之外读者也可以选择自己的根文件系统框架（custom target skeleton）。
+
+2. Init system：初始化系统方案，目前buildroot中提供2种方案，一种是BusyBox：系统的init程序将在启动时读取/etc/inittab文件，以了解该做什么，默认inittab存储在./package/busybox/inittab中；inittab除了安装几个重要的文件系统之外
+   ，还要启动/etc/init.d/rcS中的shell脚本，并启动一个getty程序(提供一个登录提示)。另一种是systemV，使用传统sysvinit程序，之前大多数台式机Linux发行版都使用该方案，现在有些变为了Upstart或Systemd，在构建文件系统的时候会在/ect目录下会生成in
+   it.d、rc0.d、rc1.d、rc2.d、rc3.d、rc4.d、rc5.d、rc6.d、rc.loacl等目录和脚本文件，init.d目录下包含的是真正的脚本。
+
+3. /dev management ：/dev设备文件的管理方式，可选选项有四个：
+
+Static using device table: 使用静态的设备表，/dev将根据system/device_table _dev.txt的内容创建设备，进入系统添加或删除设备时，无法自动更新；
+
+Dynamic using devtmpfs only:在系统启动过程中，会动态生成/dev文件，进入系统添加或删除设备时，无法自动更新；
+
+Dynamic using devtmpfs + mdev:在前面devtmpfs的基础上加入mdev用户空间实用程序，进入系统添加或删除设备时，可以自动更新，自动创建规则在/etc/mdev.conf;
+
+Dynamic using devtmpfs + eudev:在前面devtmpfs的基础上加入eudev用户空间守护程序，eudev是udev的独立版本，是Systemd的一部分，提供更多的功能也更占用资源；
+
+4. /bin/sh (bash)：选择shell类型，一般选择bash即可，用户的体验会很好。除了bash外，还有很多shell工具，比如这里可选busybox自带的shell、小巧但功能很少的dash、高效紧凑的mksh、功能强大体积也稍大的zsh。
+
+5. Root filesystem overlay directories：根文件覆盖目录，如果你想将某些文件添加到文件系统中，那么可以按照根文件的目录框架进行添加到对应的路径中，在文件系统构建的时候，会将对应的文件添加到文件系统中，如果出现相同的文件则覆盖。
+
+我们还需要配置一下Filesystem images(文件系统)选项，具体见图 33‑2 。
+
+|buildi003|
+
+图 33‑2 Filesystem images(文件系统)
+
+这些配置的含义如下：
+
+-  [ ] axfs root filesystem：XFS格式根文件系统
+
+-  [ ] btrfs root filesystem ：btrfs格式根文件系统
+
+-  [ ] cloop root filesystem for the target device：clop方式压缩根文件系统
+
+-  [ ] cpio the root filesystem (for use as an initial RAM filesystem) ：cpio方式压缩根文件系统(用作初始RAM文件系统)
+
+-  [ ] cramfs root filesystem：cramf格式根文件系统
+
+-  [*] ext2/3/4 root filesystem ：ext2/3/4格式根文件系统
+
+-  ext2/3/4 variant (ext4) ：ext4格式根文件系统
+
+-  () filesystem label ：文件系统标签
+
+-  (200M) exact size ：根文件系统空间大小[200M]
+
+-  (0) exact number of inodes (leave at 0 for auto calculation) ：确切的inode数(从0开始自动计算)
+
+-  (5) reserved blocks percentage：保留块百分比 (保留的供root使用,默认5%)
+
+-  (-O ^64bit) additional mke2fs options ：额外的mke2fs选项 [禁用64位文件系统]
+
+-  Compression method (no compression) ：压缩方式 [无压缩]
+
+-  [ ] f2fs root filesystem ：f2fs格式根文件系统
+
+-  [ ] initial RAM filesystem linked into linux kernel：初始RAM文件系统链接到Linux内核
+
+-  [ ] jffs2 root filesystem：jffs2格式根文件系统
+
+-  [ ] romfs root filesystem：romfs格式根文件系统
+
+-  [ ] squashfs root filesystem ：squashfs格式根文件系统
+
+-  [*] tar the root filesystem：tar压缩格式根文件系统
+
+-  Compression method (no compression) ：压缩方式 [无压缩]
+
+-  () other random options to pass to tar：传递给tar的其他选项
+
+-  [ ] ubi image containing an ubifs root filesystem：ubifs格式根文件系统包含ubi镜像
+
+-  [ ] ubifs root filesystem ：ubifs格式根文件系统
+
+-  [ ] yaffs2 root filesystem：yaffs2格式根文件系统
+
+我们就简单设置一下文件系统的大小（256M），以及根文件系统的格式（tar压缩格式）即可。
+
+当配置完毕后，我们可以选择对应的软件包添加到我们的系统中，比如Python3等，这里就不再重复赘述。然后使用make命令进行编译，就会生成对应的文件系统了，生成的镜像文件在output/images/目录下。
+
+命令
+
+make
+
+烧录自己制作的根文件系统
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+将生成的文件系统烧录到我们的开发板上，我们可以直接通过制作SD卡镜像的方式将文件系统烧录到SD卡，然后让开发板从SD卡启动。
+
+首先得到SD卡的文件系统镜像，如图 33‑3所示。
+
+|buildi004|
+
+图 33‑3 SD卡镜像
+
+然后通过SD卡镜像制作软件Etcher将该镜像烧写到SD卡中，如图 33‑4所示，Etcher软件可以从Etcher官网下载： https://www.balena.io/etcher/ 。该软件的使用方式非常简单，此处就不做讲解。
+
+|buildi005|
+
+图 33‑4 SD卡镜像制作软件Etcher
+
+当制作成功后，将SD卡插入开发板中，并且将拨码开关的2/5/8打到ON档，然后给开发板上电就可以看到开发板正常启动。
+
+给开发板移植debian发行版
+------------------------
+
+制作ubuntu core版本镜像
+--------------------------
+
+.. |buildi002| image:: media/building_rootfs002.png
+   :width: 5.76806in
+   :height: 4.2879in
+.. |buildi003| image:: media/building_rootfs003.png
+   :width: 4.76155in
+   :height: 5.05224in
+.. |buildi004| image:: media/building_rootfs004.png
+   :width: 5.76806in
+   :height: 4.62276in
+.. |buildi005| image:: media/building_rootfs005.png
+   :width: 5.76806in
+   :height: 3.46306in
diff --git a/documentation/building_image/building_uboot.rst b/documentation/building_image/building_uboot.rst
index ea0f95cd8ce89e0047afb1dd3c19e5d8b570b49c..bb2af465937ef29b90fd9798f2ea4af3d4396e9f 100644
--- a/documentation/building_image/building_uboot.rst
+++ b/documentation/building_image/building_uboot.rst
@@ -1,342 +1,340 @@
-.. vim: syntax=rst
+uboot
+=====
 
-编译uboot
--------
+在前面的文章我们简单了解过uboot相关的概念，此处再回顾一下，总的来说uboot的目的是为了正确引导内核的启动，它分为两个阶段，即boot
++
+loader，boot阶段启动系统，初始化硬件设备，建立内存空间映射图，将系统的软硬件带到一个合适的状态，loader阶段将操作系统内核文件加载至内存，之后跳转到内核所在地址运行。
 
-本章节内容处于开发笔记状态，还待整理至最终版的教程。
+那么我们今天来编译uboot，并教大家简单修改uboot的内容，因为在真正的生产环境中，uboot是使用芯片原厂做好的，只是根据需要修改一下uboot，而不会去大改uboot的源码，这样子没有必要也没有意义，因为uboot就是为了引导内核启动的，启动后uboot就没有什么作用了，与其将uboot改得乱七八糟还不如花时间去维护内核的稳定性。
 
-本章节内容处于开发笔记状态，还待整理至最终版的教程。
+下载uboot源码
+-------------
 
-uboot下载
-~~~~~~~
+想要编译uboot，首先我们要下载到uboot的源码，野火官方已经在NXP提供的uboot之上做了修改，并且提交到github与gitee上，大家可以从github与gitee上下载uboot的源码:
 
-在编译内核前我们首先要下载到官方提供的uboot镜像，打开\ http://git.freescale.com/git/\ 网页，可以看到很多nxp官方提供的镜像，有内核镜像也有uboot镜像，我们下载官方提供的uboot镜像，名字为uboot-imx，我们点击uboot-
-imx.git链接，跳转到下载页面，可以发现该下载页面中有很多uboot相关的信息，如它的分支，标签等，当然我们要注意的是uboot下载界面中的下载信息，我们可以通过git clone命令去拉取uboot-imx源码，他们的地址就是在下载页面信息的最下方：
+**github：**
 
-Clone
+.. code:: bash
 
-git://git.freescale.com/imx/uboot-imx.git http://git.freescale.com/git/cgit.cgi/imx/uboot-imx.git
+    git clone https://github.com/Embedfire/ebf_6ull_uboot.git
 
-具体如图 31‑1、图 31‑2所示。
+**gitee：**
 
-|buildi002|
+.. code:: bash
 
-图 31‑1 uboot下载
+    git clone https://gitee.com/wildfireteam/ebf_6ull_uboot.git
 
-|buildi003|
+当然啦，如果你想下载NXP原厂的uboot怎么办呢？很简单，直接去NXP官方网站下载就好了，打开
+http://git.freescale.com/git/
+网页，可以看到很多nxp官方提供的镜像，有内核镜像也有uboot镜像，我们下载官方提供的uboot镜像，名字为 ``uboot-imx`` ，我们点击 ``uboot-imx.git`` 链接，跳转到下载页面，可以发现该下载页面中有很多uboot相关的信息，如它的分支，标签等，当然我们要注意的是uboot下载界面中的下载信息，我们可以通过 ``git clone`` 命令去拉取 ``uboot-imx`` 源码，他们的地址就是在下载页面信息的最下方：
 
-图 31‑2 下载uboot-imx
+.. code:: bash
 
-编译我们提供的uboot
-~~~~~~~~~~~~
+    Clone 
+    git://git.freescale.com/imx/uboot-imx.git
+    http://git.freescale.com/git/cgit.cgi/imx/uboot-imx.git
 
-除了下载官方的uboo以外，我们还会提供我们的uboot，当然，我们的uboot跟官方uboot是一样的，只不过多了我们的配置文件，仅此而已。
+.. figure:: media/building_uboot002.png
+   :alt: building_uboot
 
-我们把uboot源码解压到linux虚拟机中，然后准备开始编译。
+   building_uboot
+.. figure:: media/building_uboot003.png
+   :alt: building_uboot
 
-首先使用git branch命令检查一下我们当前源码的分支是属于哪个分支，我们在编译uboot的时候，要切换到imx_v2016.03_4.1.15_2.0.0_ga分支中，如果当前分支不是imx_v2016.03_4.1.15_2.0.0_ga则使用git checkout命令切换分支。
+   building_uboot
 
-命令（检查并列出所有分支）
+**很重要的提醒，我们建议大家使用野火提供的仓库进行编译，而不需要去修改官方的uboot源码。**
 
-git branch -a
+在下载完源码后，可以查看一下野官方在NXP的源码之上做了什么样的修改，其实改动的次数只有4次，非常简单，因此我们在日常使用的时候，对uboot的修改是非常微小的，完全不必去分析uboot源码的内容，当然如果你有兴趣，那当我没说。
 
-输出
+野火修改uboot的次数如下，它主要是是支持一些硬件，比如LCD触摸屏、HDMI，然后删除NXP官方的logo，修改uboot的延时、bootargs参数等，所以说绝大部分的内容是不需要用户去修改的。
 
-\* master remotes/origin/HEAD -> origin/master remotes/origin/imx_3.14.38_6ul_engr
+.. code:: bash
 
-….（此处省略其他分支）
+    ➜  ebf_6ull_uboot git:(master) git log
 
-命令（切换分支）
+    commit d48487689c49f2c29013374689decbbb5bf1459d (HEAD -> master, origin/master)
+    Author: jiejie <1161959934@qq.com>
+    Date:   Wed Feb 26 08:39:48 2020 +0000
 
-git checkout imx_v2016.03_4.1.15_2.0.0_ga
+        fix bootargs include rw
 
-输出
+    commit a3f25a41fda5ee76b0279dba79b396ae6968993c
+    Author: pengjie <jiejie.128@163.com>
+    Date:   Tue Oct 8 02:55:05 2019 +0800
 
-Checking out files: 100% (14231/14231), done.Branch 'imx_v2016.03_4.1.15_2.0.0_ga' set up to track remote branch 'imx_v2016.03_4.1.15_2.0.0_ga' from
-'origin'.Switched to a new branch 'imx_v2016.03_4.1.15_2.0.0_ga'
+        1.delete logo 2.bootdelay==0
+        
+        Signed-off-by: pengjie <jiejie.128@163.com>
 
-切换分支后，由于我们的源码已经打上补丁的，所以不需要修改就可直接编译，我们可以通过git log命令查看一下是否已经打上补丁，如果存在以下代码则表示打上了补丁：
+    commit 444f285430aa186cff2ff490c6e4ac2e06cf1c13
+    Author: pengjie <jiejie.128@163.com>
+    Date:   Tue Sep 17 22:43:26 2019 +0800
 
-命令
+        1.修改设备树,适配个别的HDMI显示器,使其能够正常的显示
+        
+        Signed-off-by: pengjie <jiejie.128@163.com>
 
-git log
+    commit 1e738ade76db905670555a5e32dd63a1c6362382
+    Author: pengjie <jiejie.128@163.com>
+    Date:   Mon Aug 5 21:31:59 2019 +0800
 
-输出
+        add for 4.3 & 5.0 & 7.0 LCD
+        
+        Signed-off-by: pengjie <jiejie.128@163.com>
 
-commit d23b9c3540a14e03d78279e378220143adde7096 (HEAD -> imx_v2016.03_4.1.15_2.0.0_ga)Author: pengjie <jiejie.128@163.com>Date: Tue Sep 17 22:43:26
-2019 +0800 1.修改设备树,适配个别的HDMI显示器,使其能够正常的显示 Signed-off-by: pengjie <jiejie.128@163.com>
+编译前的准备
+------------
 
-commit b107e6ba6f0648c36af5e4ef146e8757041d4825Author: pengjie <jiejie.128@163.com>Date: Mon Aug 5 21:31:59 2019 +0800 add for 4.3 & 5.0 & 7.0 LCD
-Signed-off-by: pengjie <jiejie.128@163.com>
+开发环境选择 **ubuntu18.04**
 
-在编译之前，需要装交叉编译器arm-linux-gnueabihf-gcc，版本是v7.4.0，当然，如果虚拟机中已经装有交叉编译器的话则可以略过此步骤。
+**安装独立编译工具链**
 
-sudo apt-get install gcc-arm-linux-gnueabihf
+arm-none-eabi-gcc：v6.3.1
 
-编译的时候需要我们自定义配置，而nxp官方会提供一些默认配置，这些配置在uboot /configs/目录下，如mx6ull_14x14_evk_defconfig、mx6ull_14x14_evk_emmc_defconfig、mx6ull_14x14_evk_nand_defconfig等就是n
-xp官方为imx6ull提供的配置文件，可以编译生成从SD卡启动的uboot、从emmc启动的uboot以及从nand启动的uboot，我们可以根据需求选择不同的配置文件从而编译不同的uboot。
+可以通过以下命令进行安装：
 
-进入uboot源码目录下，如果想要编译从SD卡启动的uboot，则可以运行以下命令选择SD卡版本的uboot配置：
+.. code:: bash
 
-命令（编译sd卡版本uboot）
+     sudo apt-get install gcc-arm-none-eabi
 
-make ARCH=arm mx6ull_14x14_evk_defconfig
+**测试arm-none-eabi-gcc安装是否成功**
 
-而如果想编译从emmc启动的uboot，则运行：
-
-命令（编译emmc卡版本uboot）
-
-make ARCH=arm mx6ull_14x14_evk\_ emmc \_defconfig
-
-想编译从emmc启动的uboot，则运行：
-
-命令（编译nand卡版本uboot）
-
-make ARCH=arm mx6ull_14x14_evk\_ nand \_defconfig
-
-在运行以上命令后，Makefile会根据对应的配置文件的内容将配置更新到当前目录下的 .config文件中，如果读者感兴趣可以查看一下该文件的内容，接下来的编译则是根据.config文件的配置进行编译的。
-
-开始编译，运行以下命令：
-
-命令（编译uboot）
-
-make -j4 ARCH=arm CROSS_COMPILE=arm-linux-gnueabihf-
-
-输出
-
-scripts/kconfig/conf --silentoldconfig Kconfig CHK include/config.h UPD include/config.h GEN include/autoconf.mk GEN include/autoconf.mk.dep
-
-….(省略输出)
-
-LD u-boot OBJCOPY u-boot-nodtb.bin OBJCOPY u-boot.srec SYM u-boot.sym COPY u-boot.bin CFGS board/freescale/mx6ullevk/imximage.cfg.cfgtmp MKIMAGE
-u-boot.imx
-
-命令中带有jN 参数，表示最大使用N个线程编译，如j4则表示最大使用4个线程编译，根据自己电脑配置决定即可，当然线程数量越多，编译越快。在输出信息的最下方，可以看到已经生成对应的uboot（名字是u-boot.imx），可以直接烧录到开发板中。
-
-尝试在uboot中添加自己的修改
-~~~~~~~~~~~~~~~~
-
-有时候官方的uboot总是不能满足我们的需求，我们得学会修改对应的uboot配置，比如开机的logo，比如显示屏配置，HDMI配置等，我们就简单修改一下我们的配置，让他能在我们的屏幕上运行，也把开机logo替换为我们的logo。
-
-首先我们要知道这些配置写在什么地方，然后才能去修改它，比如我们先改开机logo，找到uboot /tools/目录下的Makefile文件，大约在200行，就有关于开机logo的配置，具体如下：
-
-# Generic logoifeq ($(LOGO_BMP),)LOGO_BMP= $(srctree)/$(src)/logos/denx.bmp# Use board logo and fallback to vendorifneq ($(wildcard $(srctree)/$(src)/
-logos/$(BOARD).bmp),)LOGO_BMP= $(srctree)/$(src)/logos/$(BOARD).bmpelseifneq ($(wildcard $(srctree)/$(src)/logos/$(VENDOR).bmp),)LOGO_BMP= $(srctree)/
-$(src)/logos/$(VENDOR).bmpendifendifendif # !LOGO_BMP
-
-解释一下Makefile文件的描述：
-
-使用ifeq 判断是否指定了LOGO_BMP变量（该变量表示开机logo图片），如果不指定则使用默认logo图片denx.bmp，该图片在logos目录下。
-
-然后判断一下是否存在使用开发板名字命名的图片（如$(BOARD)，它是一个变量的引用，表示开发板的名字），如果是则使用$(BOARD).bmp。
-
-最后判断一下是否存在以供应商名字命名的图片（如$(VENDOR).bmp），那么很显然，nxp官方提供的uboot必然是以它们的名字命名logo，那么uboot就会使用它们的logo图片，我们可以到uboot /tools/logos目录下查看一番，就会发现存在freescale.bmp文件，如图
-31‑3所示。
-
-注意：开机logo必须是bmp类型的图片，否则可能出现错误。
-
-|buildi004|
-
-图 31‑3 默认logo
-
-既然要修改logo，我们把自己的开机logo图片放进去替换原本的logo即可，我们的开机logo如图 31‑4所示（注意：logo图片格式必须为bmp格式）。
-
-|buildi005|
-
-图 31‑4 修改后的logo
-
-这些logo在uboot启动时就会被显示在屏幕上，具体的显示logo的函数在uboot /board/esd/common/目录下的lcd.c文件中，大约在81行左右，感兴趣的读者可以去看看源码，在这里就不深入分析。
-
-接着我们可以修改显示屏，让我们的开发板支持显示屏的其他尺寸，那么此时就要去配置源码中修改了，nxp官方支持的imx6ull开发板相关的配置源码文件在/uboot/board/freescale/mx6ullevk/目录下的mx6ullevk.c文件中，我们简单修改一下displays这个数组，它是记
-录了与显示屏相关信息的数组，具体修改如下：
-
-struct display_info_t const displays[] = {{
-
-.bus = MX6UL_LCDIF1_BASE_ADDR,
-
-.addr = 0,
-
-.pixfmt = 24,
-
-.detect = NULL,
-
-.enable = do_enable_parallel_lcd,
-
-.mode = {
-
-.name = "TFT43AB",
-
-.xres = 480,
-
-.yres = 272,
+.. code:: bash
 
-.pixclock = 108695,
+    arm-none-eabi-gcc -v
 
-.left_margin = 8,
+    # 输出
+    gcc version 6.3.1 20170620 (15:6.3.1+svn253039-1build1) 
 
-.right_margin = 4,
+安装一些必要的库，以确保编译能正常通过：
 
-.upper_margin = 2,
+.. code:: bash
 
-.lower_margin = 4,
+    sudo apt-get install lib32ncurses5 lib32tinfo5 libc6-i386
 
-.hsync_len = 41,
+开始编译
+--------
 
-.vsync_len = 10,
+**清除编译信息**
 
-.sync = 0,
+.. code:: bash
 
-.vmode = FB_VMODE_NONINTERLACED
+    make ARCH=arm clean
 
-}
+在编译uboot的时候需要我们自定义配置，而nxp官方会提供一些默认配置，这些配置在uboot
+/configs/目录下，如：
 
-},
+-  mx6ull_14x14_evk_defconfig
+-  mx6ull_14x14_evk_emmc_defconfig
+-  mx6ull_14x14_evk_nand_defconfig
 
-{
+就是nxp官方为imx6ull提供的配置文件，可以编译生成从SD卡启动的uboot、从emmc启动的uboot以及从nand启动的uboot，我们可以根据需求选择不同的配置文件从而编译不同的uboot。
 
-.bus = MX6UL_LCDIF1_BASE_ADDR,
+进入uboot源码目录下，如果想要编译从SD卡启动的uboot，则可以运行以下命令选择SD卡版本的uboot配置（3个版本的uboot任选其一即可）：
 
-.addr = 0,
+.. code:: bash
 
-.pixfmt = 24,
+    命令（编译sd卡版本uboot）
+    make ARCH=arm mx6ull_14x14_evk_defconfig
 
-.detect = NULL,
-
-.enable = do_enable_parallel_lcd,
-
-.mode = {
-
-.name = "TFT50AB",
-
-.xres = 800,
-
-.yres = 480,
-
-.pixclock = 108695,
-
-.left_margin = 46,
-
-.right_margin = 22,
-
-.upper_margin = 23,
-
-.lower_margin = 22,
-
-.hsync_len = 1,
-
-.vsync_len = 1,
-
-.sync = 0,
-
-.vmode = FB_VMODE_NONINTERLACED
-
-}
-
-},
-
-{
-
-.bus = MX6UL_LCDIF1_BASE_ADDR,
-
-.addr = 0,
-
-.pixfmt = 24,
-
-.detect = NULL,
-
-.enable = do_enable_parallel_lcd,
-
-.mode = {
-
-.name = "TFT70AB",
-
-.xres = 800,
-
-.yres = 480,
-
-.pixclock = 108695,
-
-.left_margin = 46,
-
-.right_margin = 22,
-
-.upper_margin = 23,
-
-.lower_margin = 22,
-
-.hsync_len = 1,
-
-.vsync_len = 1,
-
-.sync = 0,
-
-.vmode = FB_VMODE_NONINTERLACED
-
-}
-
-}
-
-};
-
-这里的配置是支持3个野火显示屏尺寸的，4.3寸、5寸、7寸，不同的屏幕尺寸稍微不一样，具体阅读以上配置即可，此处不深入研究。
+而如果想编译从emmc启动的uboot，则运行：
 
-当然除此之外还会修改一些其他地方（此处就不细说），如果是初学者，建议使用我们提供的补丁，把内核源码打上补丁，这种方式是最简单的方式，当然，如果是已经入门的读者，可以直接阅读补丁文件的内容，下面就介绍打补丁去过程。
+.. code:: bash
 
-首先将补丁文件拷贝到uboot源码目录下，然后可以通过git am命令给uboot源码打补丁，具体操作如下：
+    命令（编译emmc卡版本uboot）
+    make ARCH=arm mx6ull_14x14_evk_ emmc _defconfig
 
-命令（在打补丁前确认分支是imx_v2016.03_4.1.15_2.0.0_ga）
+想编译从nand启动的uboot，则运行：
 
-git branch
+.. code:: bash
 
-输出
+    命令（编译nand卡版本uboot）
+    make ARCH=arm mx6ull_14x14_evk_ nand _defconfig
 
-\* imx_v2016.03_4.1.15_2.0.0_ga master
+在运行以上命令后，Makefile会根据对应的配置文件的内容将配置更新到当前目录下的
+``.config`` 文件中，如果读者感兴趣可以查看一下该文件的内容，接下来的编译则是根据 ``.config`` 文件的配置进行编译的。
 
-命令（打第一个补丁）
+开始编译，运行以下命令：
 
-git am 0001-add-for-4.3-5.0-7.0-LCD.patch
+.. code:: bash
 
-输出
+    make -j4 ARCH=arm CROSS_COMPILE=arm-none-eabi-
 
-Applying: add for 4.3 & 5.0 & 7.0 LCD
+    ···
+      LD      u-boot
+      OBJCOPY u-boot-nodtb.bin
+      OBJCOPY u-boot.srec
+      SYM     u-boot.sym
+      COPY    u-boot.bin
+      CFGS    board/freescale/mx6ullevk/imximage.cfg.cfgtmp
+      MKIMAGE u-boot.imx
 
-命令（打第二个补丁）
+命令中带有jN
+参数，表示最大使用N个线程编译，如j4则表示最大使用4个线程编译，根据自己电脑配置决定即可，当然线程数量越多，编译越快。在输出信息的最下方，可以看到已经生成对应的uboot（名字是u-boot.imx），可以直接烧录到开发板中。
 
-git am 0002-1.-HDMI.patch
+当编译完成后会在当前目录下生成 ``u-boot.imx`` 文件
 
-输出
+.. code:: bash
 
-Applying: 1.修改设备树,适配个别的HDMI显示器,使其能够正常的显示
+    ebf_6ull_uboot/u-boot.imx
 
-注意：需要在打补丁前确认分支是imx_v2016.03_4.1.15_2.0.0_ga，当然，也必须确认uboot源码没有被修改过，可以通过git status命令查看，如果修改过则通过git reset --hard [commit]
-命令欢迎到imx_v2016.03_4.1.15_2.0.0_ga分支。
+把它与内核、设备树、文件系统烧录到开发板即可。
 
-当源码打完补丁后，可以通过 git log 查看日志信息，然后可以跟句需要进行编译，具体编译过程在上一小节中已讲解，此处不再重复赘述。
+尝试在uboot中添加自己的修改
+---------------------------
 
-烧录uboot并测试
-~~~~~~~~~~
+有时候官方的uboot总是不能满足我们的需求，我们得学会修改对应的uboot配置，比如开机的logo，比如显示屏配置，HDMI配置等，我们就简单修改一下我们的配置，让他能在我们的屏幕上运行，也把开机logo替换为我们的logo。
 
-我们编译一个emmc的uboot，具体过程如下：
+首先我们要知道这些配置写在什么地方，然后才能去修改它，比如我们先改开机logo，找到uboot
+/tools/目录下的Makefile文件，大约在200行，就有关于开机logo的配置，具体如下：
 
-#emmc版本make ARCH=arm mx6ull_14x14_evk_emmc_defconfig
+.. code:: makefile
 
-#编译make -j4 ARCH=arm CROSS_COMPILE=arm-linux-gnueabihf-
+    # Generic logo
+    ifeq ($(LOGO_BMP),)
+    LOGO_BMP= $(srctree)/$(src)/logos/denx.bmp
 
-并且将uboot烧录到开发板中可以看到启动时图片已经变为我们的logo了，具体见
+    # Use board logo and fallback to vendor
+    ifneq ($(wildcard $(srctree)/$(src)/logos/$(BOARD).bmp),)
+    LOGO_BMP= $(srctree)/$(src)/logos/$(BOARD).bmp
+    else
+    ifneq ($(wildcard $(srctree)/$(src)/logos/$(VENDOR).bmp),)
+    LOGO_BMP= $(srctree)/$(src)/logos/$(VENDOR).bmp
+    endif
+    endif
 
-（此处要加一张开机logo）
+    endif # !LOGO_BMP
 
-Clone
+解释一下Makefile文件的描述：
 
-.. |buildi002| image:: media/building_uboot002.png
-   :width: 5.76806in
-   :height: 3.62709in
-.. |buildi003| image:: media/building_uboot003.png
-   :width: 5.76806in
-   :height: 3.13519in
-.. |buildi004| image:: media/building_uboot004.png
-   :width: 3.37313in
-   :height: 1.20801in
-.. |buildi005| image:: media/building_uboot005.png
-   :width: 3.43284in
-   :height: 1.2483in
+-  使用ifeq
+   判断是否指定了LOGO_BMP变量（该变量表示开机logo图片），如果不指定则使用默认logo图片denx.bmp，该图片在logos目录下。
+
+-  然后判断一下是否存在使用开发板名字命名的图片（如 :math:(BOARD)，它是一个变量的引用，表示开发板的名字），如果是则使用(BOARD).bmp。
+
+-  最后判断一下是否存在以供应商名字命名的图片（如$(VENDOR).bmp），那么很显然，nxp官方提供的uboot必然是以它们的名字命名logo，那么uboot就会使用它们的logo图片，我们可以到uboot/tools/logos目录下查看一番，就会发现存在freescale.bmp文件，如图所示。
+
+    注意：开机logo必须是bmp类型的图片，否则可能出现错误。
+
+.. figure:: media/building_uboot004.png
+   :alt: building_uboot
+
+   building_uboot
+
+既然要修改logo，我们把自己的开机logo图片放进去替换原本的logo即可，我们的开机logo如图所示（注意：logo图片格式必须为bmp格式）。
+
+.. figure:: media/building_uboot005.png
+   :alt: building_uboot
+
+   building_uboot
+
+这些logo在uboot启动时就会被显示在屏幕上，具体的显示logo的函数在uboot
+/board/esd/common/目录下的lcd.c文件中，大约在81行左右，感兴趣的读者可以去看看源码，在这里就不深入分析。
+
+接着我们可以修改显示屏，让我们的开发板支持显示屏的其他尺寸，那么此时就要去配置源码中修改了，nxp官方支持的imx6ull开发板相关的配置源码文件在/uboot/board/freescale/mx6ullevk/目录下的mx6ullevk.c文件中，我们简单修改一下displays这个数组，它是记录了与显示屏相关信息的数组，具体修改如下：
+
+.. code:: c
+
+    struct display_info_t const displays[] = {{
+            .bus = MX6UL_LCDIF1_BASE_ADDR,
+            .addr = 0,
+            .pixfmt = 24,
+            .detect = NULL,
+            .enable = do_enable_parallel_lcd,
+            .mode   = {
+                    .name           = "TFT43AB",
+                    .xres           = 480,
+                    .yres           = 272,
+                    .pixclock       = 108695,
+                    .left_margin    = 8,
+                    .right_margin   = 4,
+                    .upper_margin   = 2,
+                    .lower_margin   = 4,
+                    .hsync_len      = 41,
+                    .vsync_len      = 10,
+                    .sync           = 0,
+                    .vmode          = FB_VMODE_NONINTERLACED
+                       }
+            },
+
+            {
+            .bus = MX6UL_LCDIF1_BASE_ADDR,
+            .addr = 0,
+            .pixfmt = 24,
+            .detect = NULL,
+            .enable = do_enable_parallel_lcd,
+            .mode   = {
+                    .name           = "TFT50AB",
+                    .xres           = 800,
+                    .yres           = 480,
+                    .pixclock       = 108695,
+                    .left_margin    = 46,
+                    .right_margin   = 22,
+                    .upper_margin   = 23,
+                    .lower_margin   = 22,
+                    .hsync_len      = 1,
+                    .vsync_len      = 1,
+                    .sync           = 0,
+                    .vmode          = FB_VMODE_NONINTERLACED
+                       }
+            },
+
+            {
+            .bus = MX6UL_LCDIF1_BASE_ADDR,
+            .addr = 0,
+            .pixfmt = 24,
+            .detect = NULL,
+            .enable = do_enable_parallel_lcd,
+            .mode   = {
+                    .name           = "TFT70AB",
+                    .xres           = 800,
+                    .yres           = 480,
+                    .pixclock       = 108695,
+                    .left_margin    = 46,
+                    .right_margin   = 22,
+                    .upper_margin   = 23,
+                    .lower_margin   = 22,
+                    .hsync_len      = 1,
+                    .vsync_len      = 1,
+                    .sync           = 0,
+                    .vmode          = FB_VMODE_NONINTERLACED
+                       }
+            }
+
+    };
+
+这里的配置是支持3个野火显示屏尺寸的，4.3寸、5寸、7寸、HDMI的适配等，不同的屏幕尺寸稍微不一样，具体阅读以上配置即可，此处不深入研究，都是比较简单的语法，主要是配置硬件相关的信息。
+
+又比如我们在开机时不想让uboot有延时，我们都可以去修改：
+
+在 ``ebf_6ull_uboot/include/configs/mx6_common.h`` 文件中将宏定义改为0：
+
+.. code:: c
+
+    #ifndef CONFIG_BOOTDELAY
+    #define CONFIG_BOOTDELAY    0
+    #endif
+
+在 ``ebf_6ull_uboot/include/configs/mx6ullevk.h`` 文件中设置uboot传给内核的参数，比如设置console、bootargs、bootcmd等：
+
+**nand 版本的参数：**
+
+.. code:: c
+
+    #define CONFIG_EXTRA_ENV_SETTINGS \
+        CONFIG_MFG_ENV_SETTINGS \
+        "panel=TFT50AB\0" \
+        "splashimage=0x82000000\0" \
+        "fdt_addr=0x83000000\0" \
+        "fdt_high=0xffffffff\0"   \
+        "console=ttymxc0\0" \
+        "bootargs=console=ttymxc0,115200 ubi.mtd=3 "  \
+            "root=ubi0:rootfs rw rootfstype=ubifs "          \
+            CONFIG_BOOTARGS_CMA_SIZE \
+            "mtdparts=gpmi-nand:64m(boot),16m(kernel),16m(dtb),-(rootfs)\0"\
+        "bootcmd=nand read ${loadaddr} 0x4000000 0x800000;"\
+            "nand read ${fdt_addr} 0x5000000 0x100000;"\
+            "bootz ${loadaddr} - ${fdt_addr}\0"
+
+**emmc版本的参数太长了，就不贴代码了，感兴趣的可以自己看源码。**
diff --git a/documentation/building_image/burning_NXP_firmware.rst b/documentation/building_image/burning_NXP_firmware.rst
new file mode 100644
index 0000000000000000000000000000000000000000..ce5ca73e0715184e19e42a61bdd5dee7f3cf06a1
--- /dev/null
+++ b/documentation/building_image/burning_NXP_firmware.rst
@@ -0,0 +1,706 @@
+.. vim: syntax=rst
+
+烧录NXP官方固件
+-----------------
+
+上一个章节介绍了如何编译NXP官方的uboot、内核、设备树以及使用buildroot编译根文件系统。
+接下来介绍烧录这些系统组件到开发板的一些常用工具和方法步骤。
+
+
+MFGtool工具
+===================
+
+MFGTool工具是NXP官方推荐的一个使用USB OTG来升级镜像的软
+件工具，它是NXP针对i.MX系列处理器专门使用的烧
+录工具，可以用来升级linux，单独烧录某一系统分区，独立
+地烧录spi flash、 nor flash、sd card、nand
+flash，emmc等，只需简单的配置，就可以使用该工具将编译好
+的文件系统和镜像文件烧录到开发板上，使用起来非常方便。而
+且MFGtool工具作为一个可量产性的工具，它支持多通道的烧录，在实
+际量产中，可以直接使用MFGtool工具同时将文件系统与镜像文件烧录
+到多个开发板上。
+
+MFGtool工具目录主要有以下内容，具体见下图。
+
+.. image:: media/mfgtoo002.png
+   :align: center
+   :alt: 未找到图片2|
+
+
+
+该目录其实是已省略很多内容的，其中主要的文件夹是Profile，里面存放着的
+是镜像文件，这里面镜像文件分为两种：第一种是作为媒介用途的
+镜像，包括uboot、dtb与uImage；第二种是真正烧录到emmc、sdcard或者nand
+flash的镜像文件。之所以存在这两种镜像，是因为MFGTools的烧录
+原理是先烧录媒介镜像到ram里面，然后启动，再通过这个启动了的媒介镜像
+把目标镜像烧录到emmc、sdcard或者nand flash里面。
+
+除此之外还有配置文件也是非常重要的，如cfg.ini、UICfg.ini以
+及ucl2.xml（该文
+件位于Profiles\Linux\OS Firmware目录下，此处就不再截图说明）。
+
+MfgTool2.exe则是MFGtool工具的可执行程序文件，在Windows系统下可
+以双击运行，在运行后就可以进行烧录操作（前提是将配置文件配置完成）。
+
+Document文件夹中存放了与该工具相关的文档。
+
+Driver目录为Windows 32位和64位操作系统的驱动，驱动一般
+都不会出现问题，也就无需理会。
+
+More_scripts目录主要存放一些脚本文件，如果只是单纯使用MFGtool工具
+也无需修这些脚本文件，此处暂时无需理会。
+
+对于MFGtool工具目录下的其他文件以及文件夹，就暂时无需理会。
+
+MFGtool工具的工作原理
+~~~~~~~~~~~~~~
+
+简单来说MFGtool工具的烧录步骤分为两个阶段：BurnStarp和Updater。第一阶段是
+烧录前的准备工作，配置设备USB的vid和pid，来选择烧录的设备。第二阶段是MFGtools开
+始烧录到结束烧录的过程，这个阶段的烧录过程是严格根据ucl2.xml文件来处理的，实际上是将bootload
+er加载到ram，然后在运行时将编译好的文件系统和镜像文件烧录到开发板上，烧录的
+位置由用户指定，可以是sd card、nand flash，emmc等。
+
+使用mfg工具直接烧录所有内容
+~~~~~~~~~~~~~~~
+
+UICfg.ini文件
+^^^^^^^^^^^
+
+UICfg.ini文件是用来配置同时烧录多少个开发板，即配置其多通道的烧录。我们此处并不量产，默认配置为1，具体见
+
+
+
+.. code-block:: c
+   :caption: UICfg.ini文件内容
+   :linenos:
+
+   [UICfg]
+   PortMgrDlg=1
+
+cfg.ini文件
+^^^^^^^^^
+
+cfg.ini文件主要是用来配置目标芯片类型和板子信息及存储器的方式等内容的，其主要文件内容
+包括四部分内容，分别是profiles、platform、list、variable。
+
+profiles
+''''''''
+
+.. code-block:: sh
+   :linenos:
+
+   [profiles]
+   chip = Linux
+
+表示要使用Profiles目录下哪个文件夹的内容进行烧录。
+
+如以上配置使用"/profiles/Linux/OS Firmware/ucl2.xml"目录
+下的ucl2.xml配置烧录。
+
+platform
+''''''''
+
+.. code-block:: sh
+   :linenos:
+
+   [platform]
+   board = embedfire_board
+
+开发板名字，目前没有作用，可以忽略
+
+list
+''''
+
+.. code-block:: sh
+   :linenos:
+
+   [list]
+   name = NAND Flash
+
+表示使用"/profiles/CHIP_PROFILE/OS Firmware/ucl2.xml"文件中
+的哪个list配置进行烧录，如将name 设置为 NAND Flash，则使用 ucl2.xml文
+件中NAND
+Flash一栏的配置进行烧录（ucl2.xml文件内容在后续讲解，此处只
+简单列出部分配置）。
+
+.. code-block:: sh
+   :linenos:
+
+   <LIST name="SDCard"
+   ….
+   <LIST name="eMMC"
+   ….
+   <LIST name="NAND Flash"
+   ….
+
+variable
+''''''''
+
+variable中是一些环境变量，在list列表配置中会引用的环境
+变量，如initramfs=fsl-image-mfgtool-initramfs-imx_mfgtools.cpio.gz.u-boot，在"/profiles/CHIP_PROFILE/OS
+Firmware/ucl2.xml"文件中会被<CMD state="BootStrap" type="load" file="firmware/%initramfs%"
+address="0x83800000"…引用，其引用的方式为"%...%"，在两
+个百分号（%）之间，通过变量initramfs进行传递。
+
+.. code-block:: sh
+   :linenos:
+
+   [variable]
+   board = sabresd
+   mmc = 1
+   sxuboot=sabresd
+   sxdtb=sdb
+   7duboot=sabresd
+   7ddtb=sdb
+   6uluboot=14x14evk
+   6uldtb=14x14-evk
+   ldo=
+   plus=
+   lite=l
+   initramfs=fsl-image-mfgtool-initramfs-imx_mfgtools.cpio.gz.u-boot
+   nand=nand
+   nanddtb=gpmi-weim
+   part_uboot=0
+   part_kernel=1
+   part_dtb=2
+   part_rootfs=3
+
+ucl2.xml文件
+^^^^^^^^^^
+
+首先我们看一下ucl2.xml文件中的文件内容（已删减）：
+
+.. code-block:: sh
+   :linenos:
+
+   <UCL>
+   
+   <CFG>
+   
+   <STATE name="BootStrap" dev="MX6ULL" vid="15A2" pid="0080"/>
+   
+   <STATE name="Updater" dev="MSC" vid="066F" pid="37FF"/>
+   
+   </CFG>
+   
+   <LIST name="NAND Flash" desc="Choose NAND as media">
+   
+   <CMD state="BootStrap" type="load" file="firmware/%initramfs%" address="0x83800000"loadSection="OTH" setSection="OTH" asFlashHeader="FALSE"
+   ifdev="MX6SL MX6SX MX7D MX6UL MX6ULL">Loading Initramfs.</CMD>
+   
+   <CMD state="BootStrap" type="jump" > Jumping to OS image.
+   </CMD>
+   
+   <CMD state="Updater" type="push" body="send" file="files1/zImage"> Sending kernel zImage</CMD>
+   
+   <CMD state="Updater" type="push" body="$ ubiformat /dev/mtd%part_rootfs%"/>
+   
+   <CMD state="Updater" type="push" body="$ ubimkvol /dev/ubi0 -Nrootfs -m"/>
+   
+   <CMD state="Updater" type="push" body="$ mkdir -p /mnt/mtd%part_rootfs%"/>
+   
+   <CMD state="Updater" type="push" body="frf">Finishing rootfs write</CMD>
+   
+   <CMD state="Updater" type="push" body="$ echo Update Complete!">Done</CMD>
+   
+   </LIST>
+   
+   </UCL>
+
+整个文件由三部分组成，首先看最外层标签<UCL> <UCL/>，它表示更新
+命令列表（Update Command List，UCL），会被MFGtool工具中的脚本解析，所有的配置都包含在该标签之下。
+
+在文件的开始会有 <CFG> </CFG>标签，它是MFGtool工具的一些全局
+配置，如在第一阶段（BootStrap）设备枚举，dev的值可以
+为MX6SL、MX6D、MX6Q、MX6SX、MX6UL、MX6ULL、MX7D其中的一个或
+多个（因为MFGtool工具可以同时烧录多个开发板），如果USB
+的vid为15A2，pid为0080，那么MFGtool工具会将dev识别为MX6ULL，这USB中
+的vid与pid是由芯片本身决定的，当dev为MX6ULL时，在后续的烧录任务中会通过ifdev
+MX6ULL进行选择执行哪些语句，然后将name设置为BootStrap，标识当前处于第
+一阶段，不同的阶段执行的处理是不一样的。这个阶段简单来说就是将开发板的USB OTG接口
+连接电脑，并且被MFGtool工具识别，才能有接下来的烧录操作。
+
+如果USB中的vid为066F，pid为37FF，则表示进入第二阶段，将dev标识为MSG，而name则被设置为Updater。
+
+简单来说，烧录分为两个阶段，BurnStarp和Updater，通过全局配置设备的vid和pid，来选择操作的设备（开发板）。
+
+接下来，可以看到该文件内有多个< LIST > </LIST>标签，这就是前面说的
+列表配置，list后面有name、desc等参数，name则表示选择cfg.ini文件中
+的list内容中的配置，可以为SDCard、eMMC、NAND
+Flash等。而desc参数用来说明目的，选择烧录
+的位置，如Choose SD Cardas media、Choose eMMC as media、Choose NAND as media等。
+
+在< LIST > </LIST>标签下有多个<CMD> </CMD>标签，这是命令标签，在不同的
+阶段命令是不一样的，MFGtool工具的命令分为主机特定命令（Host Specific Commands）与固
+件特定命令（Firmware Specific
+Commands），其中主机特定命令是由MFGtool工具解析和执行，而固件特定命令由
+目标设备上的固件运行解析和执行。
+
+命令标签下有多个熟悉，如state用于表示该命令在哪个阶段被执行，type表示执行
+命令的类型，body表示命令的参数，flie则是其他参数，如需要烧录哪个文件，最后
+的Loading Kernel、Loading U-boot则是命令描述。
+
+主机特定命令（Host Specific Commands）的命令类型有多种，其他参数也有多种，具体见
+
+下表（空余处表示无参数）。
+
+表   主机特定命令说明
+
+======== ======== ============== =================================================================================================
+命令类型 命令参数 其他参数       说明
+======== ======== ============== =================================================================================================
+load              file           烧录的镜像文件的路径和文件名
+\                 Address        镜像存放的RAM地址
+\                 loadSection    ROM代码使用的参数，应设置为"OTH"
+\                 setSection     设置为OTH，如果还有其他镜像，设置为APP
+\                 HasFlashHeader 镜像如果包含flash header，设为TRUE，否则设置为FALSE
+\                 CodeOffset     第一次执行的指令的地址偏移量。注意：该命令仅适用于除i.MX50 HID模式设备之外的Bulk-IO模式i.MX设备。
+jump                             通知ROM代码跳转到RAM映像运行
+boot     保留     flie           加载映像到RAM
+\                 if             执行判断
+======== ======== ============== =================================================================================================
+
+固件特定命令（Firmware Specific Commands）的命令类型有多种，其他参数也有多种，具体见
+
+（固件特定命令已删减，且空余处表示无参数）。如果命令被命名为"push"即type="push"，这意味着
+命令由目标设备而不是主机解析和执行，主机唯一要做的就是将命令发送到目标设备，通过body进行发
+送命令。（固件特定命令已删减，且空余处表示无参数）。如果命令被命名为"push"即type="push"，这意
+味着命令由目标设备而不是主机解析和执行，主机唯一要做的就是将命令发送到目标设备，通过body进行发送命令。
+
+表  固件特定命令说明
+
+======== ======= ===========================================================================
+命令     参数    说明
+======== ======= ===========================================================================
+?                请求以XML格式发送设备标识信息
+!        integer 根据参数进行重启操作
+$        string  执行shell命令，这是最常用的命令类型
+flush            等待所有数据传输完成并处理
+ffs              对SD卡进行分区并将引导流闪存到它
+read     string  读取参数指定的文件并将其发送给主机。如果没有这样的文件，将返回相应的状态
+send             从主机接收文件
+selftest         进行自我诊断， 返回通过或适当状态。在当前版本中未实现
+save     string  将命令"send"接收的文件保存到指定为参数的文件中。
+pipe     string  执行shell命令并从管道的输入端读取数据。 MFGtool工具会将文件发送到管道输出端
+wff              准备将固件写入flash
+wfs              准备将固件写入SD Card
+ffs              将固件写入SD Card
+======== ======= ===========================================================================
+
+MFGtool工具的烧录文件
+^^^^^^^^^^^^^^
+
+MFGtool烧录分为两个阶段，第一部分就是将firmware文件夹
+下的Uboot、Kernel、device tree、Initramfs加载到内存中，然后在第二阶段，将你要烧录的文件夹下的Uboot、Kernel、device tree、rootfs写入NAND Flash、SD
+Card或者emmc，然后完成烧录。
+
+野火开发板第1阶段烧录的文件（以烧录到nand为例）：
+
+.. code-block:: sh
+   :linenos:
+
+   Uboot：u-boot-imx6ull14x14evk_nand.imx
+   Kernel：zImage
+   device tree：zImage-imx6ull-14x14-evk-gpmi-weim.dtb
+   Initramfs：fsl-image-mfgtool-initramfs-imx_mfgtools.cpio.gz.u-boot
+
+野火开发板第2阶段烧录的文件以烧录到nand为例）：
+
+.. code-block:: sh
+   :linenos:
+
+   Uboot：u-boot-emmc-2016.03-r0.imx
+   Kernel：zImage
+   device tree：zImage-imx6ull-14x14-evk-emmc-50-70-dht11-leds.dtb
+   rootfs：my_qt_core_fs.tar.bz2
+
+烧录测试
+^^^^
+
+本次使用野火imx6ull开发板进行烧录测试，固件使用我们配套的固件即可，首先
+将表 11‑1中开发板启动方式的MODE0配置为1，MODE1配置为0，将开发板的USB OTG与
+电脑相接；然后双击打开MfgTool2.exe烧录工具，如果出现"符合 HID
+标准的供应商定义设备"则表示识别成功，而如果出现"No Device Connected"则表
+示未识别成功，识别成功时其界面如下图所示。
+
+.. image:: media/mfgtoo003.png
+   :align: center
+   :alt: 未找到图片3|
+
+
+
+最后点击"Start"按钮开始烧录到开发板上，而烧录的位置由cfg.Init文件
+指定，本次我们烧录到nand flash 中，在烧录完成后，将开发板启动
+方式的MODE0配置为0，MODE1配置为1，打开xShell终端软件，然后复位开发板即
+可看到系统启动过程，具体见下图。
+
+.. image:: media/mfgtoo004.png
+   :align: center
+   :alt: 未找到图片4|
+
+
+
+
+
+
+.. |mfgtoo002| image:: media/mfgtoo002.png
+   :width: 1.87222in
+   :height: 4.89583in
+.. |mfgtoo003| image:: media/mfgtoo003.png
+   :width: 4.49583in
+   :height: 1.87222in
+.. |mfgtoo004| image:: media/mfgtoo004.png
+   :width: 5.76806in
+   :height: 3.95426in
+
+
+SD卡刷机
+==================
+
+和MFG工具的原理类似，我们可以先将一个媒介镜像烧写到SD卡上，系统在SD卡启动后，再将保
+存在SD卡的系统组件烧写到NAND Flash或emmc中。烧写成功后再将系统配置为从NAND/emmc启动，从
+而更新系统。
+
+
+SD卡创建分区
+~~~~~~~
+
+首先需要准备一张SD卡与一个读卡器，开发环境为VM Virtual安装虚拟机ubunt18.04，使用读
+卡器将SD卡连接到电脑USB中，然后在虚拟机中将SD卡格式化，再将系统文件拷贝
+到SD卡中，具体操作如下。
+
+首先通过sudo fdisk /dev/sdb命令对SD卡进行分区，然后通过对应的命令对SD卡
+进行操作，如p：打印分区表，d：删除分区，n：添加新分区等等，具体命令如下：
+
+提示：fdisk命令产生的更改将停留在内存中，直到您决定将更改写入磁盘。
+
+::
+
+    embedfire@ embedfire:~$ sudo fdisk /dev/sdb
+
+    欢迎使用 fdisk (util-linux 2.31.1)。
+
+    更改将停留在内存中，直到您决定将更改写入磁盘。
+
+    使用写入命令前请三思。
+
+    DOS (MBR)
+
+    a 开关 可启动 标志
+
+    b 编辑嵌套的 BSD 磁盘标签
+
+    c 开关 dos 兼容性标志
+
+    常规
+
+    d 删除分区
+
+    F 列出未分区的空闲区
+
+    l 列出已知分区类型
+
+    n 添加新分区
+
+    p 打印分区表
+
+    t 更改分区类型
+
+    v 检查分区表
+
+    i 打印某个分区的相关信息
+
+    杂项
+
+    m 打印此菜单
+
+    u 更改 显示/记录 单位
+
+    x 更多功能(仅限专业人员)
+
+    脚本
+
+    I 从 sfdisk 脚本文件加载磁盘布局
+
+    O 将磁盘布局转储为 sfdisk 脚本文件
+
+    保存并退出
+
+    w 将分区表写入磁盘并退出
+
+    q 退出而不保存更改
+
+    新建空磁盘标签
+
+    g 新建一份 GPT 分区表
+
+    G 新建一份空 GPT (IRIX) 分区表
+
+    o 新建一份的空 DOS 分区表
+
+    s 新建一份空 Sun 分区表
+
+在执行sudo fdisk /dev/sdb命令后，我们需要输入p命令操作SD卡，列出SD卡中已存在的分区（不同的SD卡分区表是不一样的，根据实际情况来处理即可）：
+
+p 打印分区表
+
+输出：
+
+::
+
+    Disk /dev/sdb：7.5 GiB，8053063680 字节，15728640 个扇区单元：扇区 / 1 * 512 = 512 字节扇区大小(逻辑/物理)：512 字节 / 512 字节I/O 大小(最小/最佳)：512 字节 / 512
+    字节磁盘标签类型：dos磁盘标识符：0x4357e4a3 设备       启动    起点 末尾     扇区  大小 Id 类型/dev/sdb1         20480  1024000  1003521 490M 83 Linux/dev/sdb2       1228800
+    15728639 14499840  6.9G 83 Linux
+
+如果此时SD卡本身已存在分区（大多数情况都是为一个分区，少数情况会存在多个分区），那么就需要将SD卡本身的分区进行删除操作（如果有多少个分区就要删除多少次）。如我的SD卡就已存在两个分区，那么我需要删除两次，即输入两次d命令，再输入p命令列出分区表，此时SD卡已经没有分区表了，过程如下：
+
+d 删除分区
+
+输出：
+
+::
+
+    命令(输入 m 获取帮助)： d分区号 (1,2, 默认 2): 分区 2 已删除。命令(输入 m 获取帮助)： d已选择分区 1分区 1 已删除。
+
+    命令(输入 m 获取帮助)： pDisk /dev/sdb：7.5 GiB，8053063680 字节，15728640 个扇区单元：扇区 / 1 * 512 = 512 字节扇区大小(逻辑/物理)：512 字节 / 512 字节I/O 大小(最小/最佳)：512 字节 / 512
+    字节磁盘标签类型：dos磁盘标识符：0x4357e4a3
+
+SD卡制作新分区，且需要制作两个分区，一个是SD卡烧录本身使用的分区，剩下的SD卡容量作为第二个分区（暂时未使用到），可以输入n命令操作，输入n命令后还需要根据提示输入创建的分区类型、分区号（使用默认值即可）以及分区的大小，我们在输入n命令之后再输入p命令（创建主分区），然后输入分区的大小（分区起始
+位置~分区的结束位置，单位为扇区），同理创建第二个分区也是如此，过程如下：
+
+n 添加新分区
+
+输出：
+
+::
+
+    命令(输入 m 获取帮助)： n分区类型 p 主分区 (0个主分区，0个扩展分区，4空闲) e 扩展分区 (逻辑分区容器)选择 (默认 p)： p分区号 (1-4, 默认 1): 1第一个扇区 (2048-15728639, 默认 2048): 20480上个扇区，+sectors 或
+    +size{K,M,G,T,P} (20480-15728639, 默认 15728639): 1024000创建了一个新分区 1，类型为"Linux"，大小为 490 MiB。
+
+# 创建第二个分区
+
+::
+
+    命令(输入 m 获取帮助)： n分区类型 p 主分区 (1个主分区，0个扩展分区，3空闲) e 扩展分区 (逻辑分区容器)选择 (默认 p)： p分区号 (2-4, 默认 2): 2第一个扇区 (2048-15728639, 默认 2048): 1228800上个扇区，+sectors 或
+    +size{K,M,G,T,P} (1228800-15728639, 默认 15728639): （默认）创建了一个新分区 2，类型为"Linux"，大小为 6.9 GiB。
+
+在结束后，我们输入p命令查看一下SD卡当前分区情况，确认无误后，就输入w进行同步保存到SD卡中，因为目前的这些更改是暂时存储在内存上的，只有通过w命令保存后才能保存到SD卡中。
+
+p 打印分区表
+
+输出：
+
+::
+
+    命令(输入 m 获取帮助)： pDisk /dev/sdb：7.5 GiB，8053063680 字节，15728640 个扇区单元：扇区 / 1 * 512 = 512 字节扇区大小(逻辑/物理)：512 字节 / 512 字节I/O 大小(最小/最佳)：512 字节 / 512
+    字节磁盘标签类型：dos磁盘标识符：0x4357e4a3设备 启动 起点 末尾 扇区 大小 Id 类型/dev/sdb1 20480 1024000 1003521 490M 83 Linux/dev/sdb2 1228800 15728639 14499840 6.9G 83 Linux
+
+w 将分区表写入磁盘并退出
+
+输出：
+
+::
+
+    命令(输入 m 获取帮助)： w分区表已调整。正在同步磁盘。
+
+我们可以在终端中使用以下命令确认SD卡分区更改完成，当输出有sdb1与sdb2则表示完成，可以进行后续操作。
+
+uuu uboot.imx
+
+命令：
+
+.. code-block:: sh
+   :linenos:
+
+   ls /dev/ \| grep sdb
+
+输出：
+
+sdbsdb1sdb2
+
+烧写SD卡启动的Uboot
+~~~~~~~~~~~~~
+
+首先将野火提供的SD卡启动的资料包放入虚拟机，放入的目录可以随意选择，如我是直接放到家目录下，u-boot/sd_update/root存在以下内容：
+
+.. code-block:: sh
+   :linenos:
+
+
+   embedfire@ embedfire:~/u-boot/sd_update/root$ lsmfg-images-emmc update_nand_boot.scrmfg-images-nand zImagerelease.txt zImage-imx6ull-14x14-evk-emmc-
+   update.dtbrootfs.cpio.gz zImage-imx6ull-14x14-evk-gpmi-weim-update.dtbu-boot-sd-2016.03-r0.imx update_emmc_boot.scr
+
+u-boot-sd-2016.03-r0.imx是我们需要烧写到SD卡的Uboot，我们可以使用以下命令将进行烧录：
+
+输入命令：
+
+.. code-block:: sh
+   :linenos:
+
+   sudo dd if=~/u-boot/sd_update/root/u-boot-sd-2016.03-r0.imx of=/dev/sdb bs=512 seek=2 conv=fsync
+
+输出：
+
+[sudo] embedfire 的密码： 记录了830+0 的读入记录了830+0 的写出424960 bytes (425 kB, 415 KiB) copied, 0.176929 s, 2.4 MB/s
+
+提示：if=<Uboot镜像的位置>，位置根据你自己存放的资料路径修改即可。
+
+放入要烧写的文件到SD卡
+~~~~~~~~~~~~
+
+因为是从SD卡烧录到NAND Flash或者emmc，因此SD卡要保存烧录到NAND Flash或者emmc的文件，首先要将SD卡的分区进行格式化，用于保存这些文件，具体操作过程如下：
+
+输入命令：
+
+.. code-block:: sh
+   :linenos:
+
+   sudo mkfs.vfat /dev/sdb1
+
+
+输出：
+
+.. code-block:: sh
+   :linenos:
+
+   ~$ mkfs.fat 4.1 (2017-01-24)mkfs.vfat: /dev/sdb1 contains a mounted filesystem.
+
+输入命令：
+
+.. code-block:: sh
+   :linenos:
+
+   sudo mkfs.ext4 /dev/sdb2
+
+输出：
+
+.. code-block:: sh
+   :linenos:
+
+   mke2fs 1.44.1 (24-Mar-2018)
+
+首先挂载SD卡，本次试验创建一个挂载目录mountpoint，将SD卡挂
+载到该目录下，然后将野火提供的SD卡启动的资料包中root目录下所
+有文件拷贝到fat格式分区（即sdb1）目录下，具体操作如下：
+
+挂载SD卡：
+
+.. code-block:: sh
+   :linenos:
+
+   mkdir mountpointsudo mount /dev/sdb1 mountpoint/
+
+拷贝root目录下所有文件到SD卡：
+
+.. code-block:: sh
+   :linenos:
+
+   sudo cp -r ~/u-boot/sd_update/root/* ~/mountpoint/
+
+查看拷贝后的内容：ls
+
+mfg-images-emmc update_nand_boot.scrmfg-images-nand zImagerelease.txt zImage-imx6ull-14x14-evk-emmc-update.dtbrootfs.cpio.gz zImage-imx6ull-14x14-evk-
+gpmi-weim-update.dtbu-boot-sd-2016.03-r0.imx
+
+update_emmc_boot.scr
+
+配置SD卡烧录信息
+~~~~~~~~~
+
+如果需要从SD卡烧录到NAND Flash，则将mfg-images-nand改名为mfg-images；如果
+需要从SD卡烧录到emmc，则将mfg-images-emmc改名为mfg-images；并且将update_nand_boot.scr改名为boot.scr，mfg-
+images文件夹中的文件相应的替换，并在Manifest中填写欲烧写文件的文
+件名即可。然后将sd卡插入开发板，将开发板的WiFi的跳帽取下，同时
+将boot的拨码开关 2/5/8 拨到 ON档，表示从SD卡启动，在SD卡烧写的时
+候红灯闪烁，烧写完毕，红灯常亮，烧写失败，红灯熄灭。
+
+修改文件名字可以使用mv命令，具体如下：
+
+进入mountpoint目录：
+
+.. code-block:: sh
+   :linenos:
+
+   cd mountpoint/
+
+修改mfg-images-nand文件名字为mfg-images：
+
+.. code-block:: sh
+   :linenos:
+
+   sudo mv mfg-images-nand/ mfg-images/
+
+修改update_nand_boot.scr文件为boot.scr：
+
+.. code-block:: sh
+   :linenos:
+
+   sudo mv update_nand_boot.scr boot.scr
+
+在烧录工程可以打开串口终端，查看开发板输出的信息，具体见下图。
+
+.. image:: media/sdcard002.png
+   :align: center
+   :alt: 未找到图片
+
+
+
+在烧录完成后，将boot的拨码开关 2/3/6 拨到 ON档，就可以从NAND Flash启动了。
+
+
+
+.. |sdcard002| image:: media/sdcard002.png
+   :width: 5.12508in
+   :height: 5.008in
+
+制作SD卡启动介质
+====================
+
+SD卡作为一种灵活高效的存储介质，不仅可以利用它烧录系统组件到emmc/nand，还可以把它当成制作成启动介质，
+让开发板直接通过sd卡启动系统。
+
+野火已经提过 boot2sdcard.sh 脚本工具，路径为 https://github.com/Embedfire/embed_linux_tutorial/blob/master/shell_tools/boot2sdcard.sh 。
+
+1、使用读卡器把SD卡连接到Ubuntu上，执行fdisk -l查看所有系统设备，可以看到SD卡已经被为/dev/sd*设备，
+后面的*具体表示SD卡的驱动编号。
+
+如下图:
+
+.. image:: media/burn_sd.png
+   :align: center
+   :alt: 未找到图片
+
+
+2、把系统组件和烧录脚本放在同一个文件夹下，在Ubuntu中运行SD卡镜像制作脚本：
+
+.. code-block:: sh
+   :linenos:
+
+    #./boot2sdcard.sh uboot kernel devicetree rootfs
+    #这里的uboot、kernel、devicetree、rootfs分别泛指具体组件的文件名，示例:
+    ./boot2sdcard.sh u-boot-nand-2016.03-r0.imx \
+				zImage\
+				imx6ull-14x14-evk.dtb \
+				core-image-sato-imx6ull14x14evk-20190906004421.rootfs.tar.bz2
+
+3、脚本执行后，系统提示输入SD卡编号。比如上面示例识别sd卡设备为/dev/sdb1、/dev/sdb2，直接输入编号"b"即可。
+注意:sd卡编号一定不要输错，要通过系统盘的容量大小和反复拔插来确定sd卡的编号。
+如果不小心输入了电脑硬盘的编号，会导致系统本身被删除，造成死机奔溃！
+
+::
+
+    Disk /dev/sdb：14.9 GiB，15931539456 字节，31116288 个扇区
+    单元：扇区 / 1 * 512 = 512 字节
+    扇区大小(逻辑/物理)：512 字节 / 512 字节
+    I/O 大小(最小/最佳)：512 字节 / 512 字节
+    磁盘标签类型：dos
+    磁盘标识符：0x0070085a
+
+    请确保输入的sd卡编号正确！！！
+
+    Please Input the card ID [a~z] (Input 'exit' for quit): 
+
+
+
+4、等待系统烧录完毕后，调整开发板启动方式为SD卡启动，插入SD卡，上电即可启动开发板。
diff --git a/documentation/building_image/image_composition.rst b/documentation/building_image/image_composition.rst
index dbd5f11d07fa29ae87b45f4a39252f861af59c20..0c2c81a91f8d8c67f0dfb88fee9883793a5654e1 100644
--- a/documentation/building_image/image_composition.rst
+++ b/documentation/building_image/image_composition.rst
@@ -1,41 +1,63 @@
 .. vim: syntax=rst
 
-系统运行所需要的组件
+了解Linux系统组件
 ----------
 
-本章节内容处于开发笔记状态，还待整理至最终版的教程。
 
-本章节内容处于开发笔记状态，还待整理至最终版的教程。
-
-上一章节中我们制作的SD卡镜像里，包含了Uboot、kernel、**.dtb以及根文件系统，它们是系统运行需要的4个基础组件。
+一个完整的linux系统，通常包含了Uboot、kernel、**.dtb以及根文件系统，
+它们是系统运行需要的4个基础组件。
 
 Uboot
 ~~~~~
 
-U-Boot，全称 Universal Boot Loader，是遵循GPL条款的开源项目，U-Boot是从FADSROM、8xxROM、PPCBOOT逐步发展演化而来的。U-Boot发展至今，已经可以实现非常多的功能，在操作系统方面，它不仅支持嵌入式Linux系统的引导，还支持NetBSD,
+U-Boot，全称 Universal Boot Loader，是遵循GPL条款的开源项目，U-Boot是
+从FADSROM、8xxROM、PPCBOOT逐步发展演化而来的。U-Boot发展至今，已经可以
+实现非常多的功能，在操作系统方面，它不仅支持嵌入式Linux系统的引导，还支持NetBSD,
 VxWorks, QNX, RTEMS, ARTOS, LynxOS, Android等嵌入式操作系统的引导。在CPU架构方面
-，U-Boot支持PowerPC、MIPS、x86、ARM、NIOS、XScale等诸多常用系列的处理器。U-Boot的主要作用是用来启动操作系统内核，它分为两个阶段，即boot +
-loader，boot阶段启动系统，初始化硬件设备，建立内存空间映射图，将系统的软硬件带到一个合适的状态，loader阶段将操作系统内核文件加载至内存，之后跳转到内核所在地址运行。
+，U-Boot支持PowerPC、MIPS、x86、ARM、NIOS、XScale等诸多常用系列的处
+理器。U-Boot的主要作用是用来启动操作系统内核，它分为两个阶段，即boot +
+loader，boot阶段启动系统，初始化硬件设备，建立内存空间映射图，将系统的
+软硬件带到一个合适的状态，loader阶段将操作系统内核文件加载至内存，之后跳转到内核所在地址运行。
+
+当一个开发板上电的时候，即使是执行非常简单的程序，都需要进行很多初始化的
+操作，如初始化时钟、初始化存储控制器、将代码拷贝到运行内存中等操作，大多数
+处理器在上电的时候都会有默认的指令执行位置，如ARM架构的处理器会从0x00000000地址开始读取第一条指令。
+
+一般来说BootLoader必须提供系统上电时的初始化代码，在系统上电时初始化相关
+环境后，BootLoader需要引导完整的操作系统，然后将控制器交给操作系统。
+简单来说BootLoader是一段小程序，它在系统上电时执行，通过这段小程序可以将硬件
+设备进行初始化，如CPU、SDRAM、Flash、串口、网络等，初始化完毕后调用操作系统内核。
+另外，某些BootLoader可能含有一些高级特性，如校验操作系统镜像，从多个操作系统镜像中选择引导合适的操作系统，
+甚至可以添加网络功能，让系统自主从网上寻找合适的镜像并且进行引导等等。
 
-当一个开发板上电的时候，即使是执行非常简单的程序，都需要进行很多初始化的操作，如初始化时钟、初始化存储控制器、将代码拷贝到运行内存中等操作，大多数处理器在上电的时候都会有默认的指令执行位置，如ARM架构的处理器会从0x00000000地址开始读取第一条指令。
+在开发的时候，我们可能需要利用一些命令去操作BootLoader，让BootLoader完成一
+些事情，我们可以称这种模式为下载模式，比如从内存中的ELF镜像启动，从内存启动
+应用程序镜像，使用BOOTP/TFTP协议通过网络启动镜像，打印控制台设备和信息，打印
+有关文件系统的信息，列出目录中的文件等等。
+当然，下载模式是对于开发人员才有意义，而对于用户则不需要这些操作，直接可以启动
+操作系统运行，这种直接启动操作系统的模式可以称之为启动模式。正如我们所说， U-Boot的
+功能十分强大，它可以同时支持下载模式与启动模式，并且可以切换模式，它可以在系统上电
+时默认等待N秒（N可以随意设置），在这N秒内没有命
+令（如按下任意按键、串口发送任意数据等）去操作BootLoader时，U-Boot将启动默认
+的操作系统内核（如Linux）。当有命令操作BootLoader时，系统将进入下载模式，在这
+个模式下，BootLoader将不会继续启动操作系统内核，而是由开发者去指定BootLoader的工作，如通过串口下
+载操作系统镜像，通过网络启动镜像等操作，如下图所示。
 
-一般来说BootLoader必须提供系统上电时的初始化代码，在系统上电时初始化相关环境后，BootLoader需要引导完整的操作系统，然后将控制器交给操作系统。简单来说BootLoader是一段小程序，它在系统上电时执行，通过这段小程序可以将硬件设备进行初始化，如CPU、SDRAM、Flash、串口
-、网络等，初始化完毕后调用操作系统内核。另外，某些BootLoader可能含有一些高级特性，如校验操作系统镜像，从多个操作系统镜像中选择引导合适的操作系统，甚至可以添加网络功能，让系统自主从网上寻找合适的镜像并且进行引导等等。
+.. image:: media/imagec002.png
+   :align: center
+   :alt: 未找到图片02|
 
-在开发的时候，我们可能需要利用一些命令去操作BootLoader，让BootLoader完成一些事情，我们可以称这种模式为下载模式，比如从内存中的ELF镜像启动，从内存启动应用程序镜像，使用BOOTP/TFTP协议通过网络启动镜像，打印控制台设备和信息，打印有关文件系统的信息，列出目录中的文件等等。
-当然，下载模式是对于开发人员才有意义，而对于用户则不需要这些操作，直接可以启动操作系统运行，这种直接启动操作系统的模式可以称之为启动模式。正如我们所说， U-Boot的功能十分强大，它可以同时支持下载模式与启动模式，并且可以切换模式，它可以在系统上电时默认等待N秒（N可以随意设置），在这N秒内没有命
-令（如按下任意按键、串口发送任意数据等）去操作BootLoader时，U-Boot将启动默认的操作系统内核（如Linux）。当有命令操作BootLoader时，系统将进入下载模式，在这个模式下，BootLoader将不会继续启动操作系统内核，而是由开发者去指定BootLoader的工作，如通过串口下
-载操作系统镜像，通过网络启动镜像等操作，如图 27‑1所示。
 
-|imagec002|
 
-图 27‑1下载模式
+而当N秒内没有命令去操作BootLoader时，BootLoader将启动默认的操作系统，并将
+控制块交给操作系统，显然，在产品发布时BootLoader是工作在启动模式下的，这种模
+式是不需要用户通过BootLoader的命令去控制BootLoader，而是直接启动操作系统即可，具体见下图。
 
-而当N秒内没有命令去操作BootLoader时，BootLoader将启动默认的操作系统，并将控制块交给操作系统，显然，在产品发布时BootLoader是工作在启动模式下的，这种模式是不需要用户通过BootLoader的命令去控制BootLoader，而是直接启动操作系统即可，具体见图 27‑2。
+.. image:: media/imagec003.png
+   :align: center
+   :alt: 未找到图片03|
 
-|imagec003|
 
-图 27‑2启动模式
 
 U-Boot启动内核的过程可以分为两个阶段，两个阶段的功能如下：
 
@@ -69,26 +91,48 @@ Kernel
 Linux内核
 ^^^^^^^
 
-Kernel即是Linux内核，Linux内核采用宏内核架构，即Linux大部分功能都会在内核中实现，如进程管理、内存管理、设备管理、文件管理以及网络管理等功能，它们是运行在内核空间中（也可以称之为特权模式下运行）；除此之外还有一种与宏内核相反的内核架构——微内核，它仅仅是将内核的基本功能放入内核中
-，如进程管理、进程调度等，而其他的设备管理、文件管理等功能都放在内核空间之外（即运行在非特权模式下），这种微内核的架构有很优越的扩展性，它将系统分为各个小的功能模块，把设计难度大大降低。而宏内核的设计架构则没有非常好的扩展性，但Linux在发展的过程中，很早就引入了内核模块（Loadable
-Kernel Module，LKM）这一机制，弥补了这一不足之处，内核模块全称为动态可加载内核模块，就是在内核运行时可以动态加载一组目标代码来实现某些特定的功能，在这过程中不需要重新编译内核就可以实现动态扩展。模块是具有独立功能的程序，它可以被单独编译，但不能独立运行。它在运行时被链接到内核作为内核
-的一部分在内核空间运行，这与运行在用户空间的进程是不同的。模块通常由一组函数和数据结构组成，用来实现一种文件系统、一个驱动程序或其他内核上层的功能，关于内核模块我们后续会讲解。
-
-Linux\ **系统组成**
-^^^^^^^^^^^^^^^
-
-Linux内核主要由5部分组成，分别为：进程管理子系统，内存管理子系统，文件子系统，网络子系统，设备子系统，如图 27‑3所示（图片来源网络）。
-
-|imagec004|
-
-图 27‑3 Linux内核组成
-
-从图 27‑3科员看出，整个内核是由5部分组成，并且由系统调用层（系统调用子系统）进行统一管理，应用层通过系统调用层的函数接口与内核进行交互，用户应用程序执行的地方是用户空间，用户空间之下则是内核空间，Linux 内核正是位于内核空间中，下面分别了解一下内核的5个组成部分。
+Kernel即是Linux内核，Linux内核采用宏内核架构，即Linux大部分功能都
+会在内核中实现，如进程管理、内存管理、设备管理、文件管理以及网络管
+理等功能，它们是运行在内核空间中（也可以称之为特权模式下运行）；除
+此之外还有一种与宏内核相反的内核架构——微内核，它仅仅是将内核的基本功
+能放入内核中
+，如进程管理、进程调度等，而其他的设备管理、文件管理等功能都放在内核
+空间之外（即运行在非特权模式下），这种微内核的架构有很优越的扩展性，它
+将系统分为各个小的功能模块，把设计难度大大降低。而宏内核的设计架构则没有
+非常好的扩展性，但Linux在发展的过程中，很早就引入了内核模块（Loadable
+Kernel Module，LKM）这一机制，弥补了这一不足之处，内核模块全称为动态可
+加载内核模块，就是在内核运行时可以动态加载一组目标代码来实现某些特定的
+功能，在这过程中不需要重新编译内核就可以实现动态扩展。模块是具有独立功能
+的程序，它可以被单独编译，但不能独立运行。它在运行时被链接到内核作为内核
+的一部分在内核空间运行，这与运行在用户空间的进程是不同的。模块通常由一组
+函数和数据结构组成，用来实现一种文件系统、一个驱动程序或其他内核上层的功
+能，关于内核模块我们后续会讲解。
+
+Linux **系统组成**
+^^^^^^^^^^^^^^^^^^^^^^
+
+Linux内核主要由5部分组成，分别为：进程管理子系统，内存管理子系统，文件
+子系统，网络子系统，设备子系统，如下图所示（图片来源网络）。
+
+.. image:: media/imagec004.jpeg
+   :align: center
+   :alt: 未找到图片04|
+
+
+
+从上图可以看出，整个内核是由5部分组
+成，并且由系统调用层（系统调用子系统）进
+行统一管理，应用层通过系统调用层的函数接口与内核进
+行交互，用户应用程序执行的地方是用户空间，用户空间之下则是
+内核空间，Linux 内核正是位于内核空间中，下面分别了解一下内核的5个组成部分。
 
 进程管理子系统
 '''''''
 
-进程管理的核心就是进程的调度。在Linux内核中，进程调度的单元是进程，进程调度控制系统中的多个进程对CPU的访问，从宏观上看，系统中的进程在CPU中是并发执行的。此外内核通过系统调用提供了应用程序编程接口，例如：创建新进程（fork，exec），结束进程（kill，
+进程管理的核心就是进程的调度。在Linux内核中，进程调
+度的单元是进程，进程调度控制系统中的多个进程对CPU的访问，从宏观上看，系统
+中的进程在CPU中是并发执行的。此外内核通过系统调用提供了应用程序
+编程接口，例如：创建新进程（fork，exec），结束进程（kill，
 exit），并且提供了控制进程，同步进程和进程间通信的接口。
 
 进程与程序的区别：
@@ -103,111 +147,196 @@ exit），并且提供了控制进程，同步进程和进程间通信的接口
 
 2. 有进程专有的系统堆栈空间（也可以称之为内核堆栈空间）。
 
-3. 在内核中有一个task_struct数据结构，即进程控制块。有了这个数据结构，进程才能被内核调度器识别并参与内核调度，除此之外它还记录着进程所占有的各项资源。
+3. 在内核中有一个task_struct数据结构，即进程控制块。有了这个数
+据结构，进程才能被内核调度器识别并参与内核调度，除此之外它还记录着
+进程所占有的各项资源。
 
-4. 除上述的专有的系统堆栈空间外，进程还需要有独立的用户堆栈空间，这就是mm_struct数据结构，该数据结构位于task_struct结构中，字段名称为mm。
+4. 除上述的专有的系统堆栈空间外，进程还需要有独立的用户堆栈空间，这
+就是mm_struct数据结构，该数据结构位于task_struct结构中，字段名称为mm。
 
-每个进程都有自己的堆栈，内核在创建一个新的进程时，在创建进程控制块task_struct的同时，也为进程创建自己堆栈。一个进程有2个堆栈，即用户堆栈和系统堆栈；用户堆栈的空间指向用户地址空间，内核堆栈的空间指向内核地址空间。当进程在用户态运行时，CPU堆栈指针寄存器指向用户堆栈地址，使用用户堆栈，当
+每个进程都有自己的堆栈，内核在创建一个新的进程时，在创建进程控
+制块task_struct的同时，也为进程创建自己堆栈。一个进程有2个堆栈，即用
+户堆栈和系统堆栈；用户堆栈的空间指向用户地址空间，内核堆栈的空间指
+向内核地址空间。当进程在用户态运行时，CPU堆栈指针寄存器指向用户堆栈地址，使用用户堆栈，当
 进程运行在内核态时，CPU堆栈指针寄存器指向的是内核栈空间地址，使用的是内核栈。
 
-在Linux中进程与线程的区分也不是十分严格，一般在讲到进程时常常也包括了线程，以上的进程四个要素是必要条件，缺了其中任何一条都不能称其为“进程”，如果完全没有用户空间，即mm_struct为NULL，那么可以称它为内核线程，如果有共享的用户空间，那么可以称之为用户线程，具体如图 27‑4所示。
+在Linux中进程与线程的区分也不是十分严格，一般在讲到进程时常常也包括
+了线程，以上的进程四个要素是必要条件，缺了其中任何一条都不能称其为"进
+程"，如果完全没有用户空间，即mm_struct为NULL，那么可以称它为内核
+线程，如果有共享的用户空间，那么可以称之为用户线程，具体如下图所示。
 
-|imagec005|
+.. image:: media/imagec005.png
+   :align: center
+   :alt: 未找到图片05|
 
-图 27‑4 进程与线程
 
-进程调度：
 
-进程调度是进程管理子系统中最重要的一个功能，它决定了哪个进程可以运行，什么时候运行，什么时候停止，它实际上就是一个管理进程之间使用CPU资源的管理程序，因此Linux内核必须提供一种方法方法，让各个进程之间尽可能公平地共享CPU资源，并且还需要考虑各个进程的优先级。因此进程调度器的设计就要解决如何有
-效地为各个进程分配其使用 的CPU资源 时间，同时又要达到良好的用户体验效果，此外调度器还需要解决一些互相冲突的情况，例如既要实现实时任务的最小化响应时间, 又要最大限度地提高 CPU 的总体利用率等。
+进程调度：
 
-其实在Linux2.6版本之后，进程调度器使用新的进程调度算法——Completely Fair Scheduler，简称CFS，即完全公平调度算法，该算法会按所需分配的计算能力，向系统中每个进程提供最大的公正性，或者从另外一个角度上说，它试图确保没有进程被亏待。经过多年来的测试，完全公平调度算法在
-高负载情况下依然有极其出色的性能，它负责将CPU资源，分配给正在执行的进程，目标在于最大化程式互动效能，最小化整体CPU的运用，这个算法使用红黑树来实现，算法效率为O(log(n))。
+进程调度是进程管理子系统中最重要的一个功能，它决定了哪个进程
+可以运行，什么时候运行，什么时候停止，它实际上就是一个管理进程
+之间使用CPU资源的管理程序，因此Linux内核必须提供一种方法方法，让各个
+进程之间尽可能公平地共享CPU资源，并且还需要考虑各个进程的优先级。因此进程
+调度器的设计就要解决如何有
+效地为各个进程分配其使用 的CPU资源 时间，同时又要达到良好的用户体验效果，此外
+调度器还需要解决一些互相冲突的情况，例如既要实现实时任务的最小化响应时间, 又
+要最大限度地提高 CPU 的总体利用率等。
+
+其实在Linux2.6版本之后，进程调度器使用新的进程调
+度算法——Completely Fair Scheduler，简称CFS，即完全公平调度算法，该算
+法会按所需分配的计算能力，向系统中每个进程提供最大的公正性，或者从另
+外一个角度上说，它试图确保没有进程被亏待。经过多年来的测试，完全公平调度算法在
+高负载情况下依然有极其出色的性能，它负责将CPU资源，分配给正在执行的进
+程，目标在于最大化程式互动效能，最小化整体CPU的运用，这个算法使用红黑树
+来实现，算法效率为O(log(n))。
 
 进程状态：
 
-每个进程都有状态属性，在整个Linux中运行着多个进程，某些进程可能处于运行态，某些进程可能处于就绪态，某些进程可能处于睡眠态或者是深度睡眠态，还有一些进程可能处于暂停态或者僵死态等，这些进程的状态都是动态变化的并且是由进程调度器决定的，具体见图 27‑5。
+每个进程都有状态属性，在整个Linux中运行着多个进程，某些进程可能
+处于运行态，某些进程可能处于就绪态，某些进程可能处于睡眠态或者是深度
+睡眠态，还有一些进程可能处于暂停态或者僵死态等，这些进程的状态都是
+动态变化的并且是由进程调度器决定的，具体见下图。
+
+.. image:: media/imagec006.png
+   :align: center
+   :alt: 未找到图片06|
 
-|imagec006|
 
-图 27‑5 进程状态转换
 
--  就绪态R (TASK_RUNNING)：就绪态也被称作可执行状态，只有在该状态的进程才能被允许参与调度器调度并且使用CPU资源，而同一时刻可能有多个进程处于就绪态，这些进程的task_struct结构（进程控制块）被放入对应CPU的可执行队列中（一个进程最多只能出现在一个CPU的可执行队列中）。进
+-  就绪态R (TASK_RUNNING)：就绪态也被称作可执行状态，只有
+在该状态的进程才能被允许参与调度器调度并且使用CPU资源，而同一时
+刻可能有多个进程处于就绪态，这些进程的task_struct结构（进程控制块）被放入
+对应CPU的可执行队列中（一个进程最多只能出现在一个CPU的可执行队列中）。进
   程调度器的任务就是从各个CPU的可执行队列中分别选择一个进程在该CPU上运行。
 
 -  运行态R (TASK_RUNNING)：此时进程正在使用CPU资源。
 
-提示：很多操作系统的书将正在CPU上执行的进程定义为RUNNING状态、而将可执行但是尚未被调度执行的进程定义为READY状态，这两种状态在linux下统一为TASK_RUNNING状态
-
--  暂停态T (TASK_STOPPED or TASK_TRACED)：向进程发送一个SIGSTOP信号，它就会因响应该信号而进入TASK_STOPPED状态，向进程发送一个SIGCONT信号，可以让其从TASK_STOPPED状态恢复到TASK_RUNNING状态，当进程正在被跟踪时，它处于TAS
-  K_TRACED这个特殊的状态。“正在被跟踪”指的是进程暂停下来，等待跟踪它的进程对它进行操作。比如在gdb中对被跟踪的进程下一个断点，进程在断点处停下来的时候就处于TASK_TRACED状态。
-
--  可中断睡眠态S (TASK_INTERRUPTIBLE)：（对应图 27‑5的睡眠态）处于这个状态的进程因为等待某些事件的发生而进入睡眠状态（比如等待socket连接、等待信号量等）。当这些事件发生的时候进程将被唤醒，如产生一个硬件中断、释放进程正在等待的系统资源或是传递一个信号都可以是唤醒进程的
-  条件。一般情况下系统的大多数进程都是处于这个状态的，在终端可以通过ps命令查看系统进程状态。
-
--  不可中断睡眠状态D (TASK_UNINTERRUPTIBLE)：不可中断睡眠状态又被称作深度睡眠态，它与可中断睡眠状态类似，但是它有一个例外，那就是把信号传递到这种睡眠状态的进程不能改变它的状态，也就是说它不响应信号的唤醒，这种状态一般由IO引起，同步IO在做读或写操作时（比如进程对某些硬件设备
-  进行操作，等待磁盘IO，等待网络IO），此时CPU不能做其它事情，只能处于这种状态进行等待，这样一来就能保证进程执行期间不被外部信号打断，但这种状态时间非常短，很难在终端中将它捕获到。
+提示：很多操作系统的书将正在CPU上执行的进程定义为RUNNING状态、而将
+可执行但是尚未被调度执行的进程定义为READY状态，这两种状态在linux下统一为TASK_RUNNING状态
+
+-  暂停态T (TASK_STOPPED or TASK_TRACED)：向进程发送一个SIGSTOP信号，它就
+  会因响应该信号而进入TASK_STOPPED状态，向进程发送一个SIGCONT信号，可以让
+  其从TASK_STOPPED状态恢复到TASK_RUNNING状态，当进程正在被跟踪时，它处于TAS
+  K_TRACED这个特殊的状态。"正在被跟踪"指的是进程暂停下来，等待跟踪它的进
+  程对它进行操作。比如在gdb中对被跟踪的进程下一个断点，进程在断点处停下来的时
+  候就处于TASK_TRACED状态。
+
+-  可中断睡眠态S (TASK_INTERRUPTIBLE)：（对应上图的睡眠态）处于这个状
+   态的进程因为等待某些事件的发生而进入睡眠状态（比如等待socket连接、等待信号量等）。当
+   这些事件发生的时候进程将被唤醒，如产生一个硬件中断、释放进程正在等待的系统资源或是传
+   递一个信号都可以是唤醒进程的
+   条件。一般情况下系统的大多数进程都是处于这个状态的，在终端可以通过ps命令查看系统进程状态。
+
+-  不可中断睡眠状态D (TASK_UNINTERRUPTIBLE)：不可中断睡眠状态又被称作深度睡眠态，它与
+   可中断睡眠状态类似，但是它有一个例外，那就是把信号传递到这种睡眠状态的进程不能改变它
+   的状态，也就是说它不响应信号的唤醒，这种状态一般由IO引起，同步IO在做读或写操作
+   时（比如进程对某些硬件设备
+   进行操作，等待磁盘IO，等待网络IO），此时CPU不能做其它事情，只能处于这种状态
+   进行等待，这样一来就能保证进程执行期间不被外部信号打断，但这种状态时间非常
+   短，很难在终端中将它捕获到。
 
 -  僵死态Z (TASK_DEAD - EXIT_ZOMBIE)：僵死态又被称之为僵尸态或者退出态，进程在退出的过程中，除了task_struct数据结构（以及少数资源）以外，进程所占有的资源将被系统回收，此时进程没法继续运行了，但它还有task_struct数据结构，所以被称为僵死态。之所以保留ta
   sk_struct数据结构，是因为task_struct中保存了进程的退出码、以及一些其他的信息，而其父进程很可能会关心这些信息，因此会暂时被保留下来。
 
 可以使用ps –aux命令查看当前系统中进程的状态，因为当前系统觉得大部分进程是处于可中断睡眠态的，如运行态、不可中断睡眠态、僵死态等进程状态是很难被终端捕获到的，因此下面的图我是经过处理的，能更直观显示一些任务状态，具体见图 27‑6。
 
-|imagec007|
+.. image:: media/imagec007.png
+   :align: center
+   :alt: 未找到图片07|
+
 
-图 27‑6进程状态
 
 内存管理子系统
 '''''''
 
-内存管理的主要作用是保证系统安全访问内存区域，且绝大部分CPU都是支持内存管理单元的（Memory Management Unit，MMU），那么在
-Linux中，内存管理子系统就负责管理每个进程完成从虚拟内存到物理内存的转换，以及系统可用内存空间，此外还顺便提一点，Linux的2.6版本后引入了对无MMU CPU的支持。
-
-内存管理的硬件按照分页方式管理内存，分页就是把系统的物理内存按照相同大小等分，每个内存分片称作内存页，通常内存页大小是4KB。内存管理子系统要管理的不仅是4KB缓冲区，它提供了对4KB缓冲区的抽象，例如slab分配器。这种内存管理模式使用4KB缓冲区为基数，然后从中分配管理结构，并跟踪内存页使用情况
-，系统中哪些内存页是满的，哪些内存页面为空，哪些内存页没有完全使用。这样一来，系统就支持动态调整内存使用情况。除此之外，Linux还支持内存交换，因为Linux中使用的是虚拟内存，当物理内存不足时，内存管理子系统会将内存暂时移到磁盘中，在物理内存充裕时又将内存页从磁盘移到物理内存中，这就是内存交换。
-
-一般而言，在32位的系统上，每个进程都最大享有4GB的内存空间，因为由于32位的系统寻址空间只有4G，当然这是虚拟内存，0~3GB是属于用户内存空间，3~4GB是属于系统内存空间，实际上用户的程序几乎使用不完那么大的用户空间，一旦超出将无法正常运行，当然系统内存空间与用户内存空间是可以调整的。
+内存管理的主要作用是保证系统安全访问内存区域，且绝大部
+分CPU都是支持内存管理单元的（Memory Management Unit，MMU），那么在
+Linux中，内存管理子系统就负责管理每个进程完成从虚拟
+内存到物理内存的转换，以及系统可用内存空间，此外还顺便
+提一点，Linux的2.6版本后引入了对无MMU CPU的支持。
+
+内存管理的硬件按照分页方式管理内存，分页就是把系统的物
+理内存按照相同大小等分，每个内存分片称作内存页，通常内存页大小
+是4KB。内存管理子系统要管理的不仅是4KB缓冲区，它提供了对4KB缓冲区
+的抽象，例如slab分配器。这种内存管理模式使用4KB缓冲区为基数，然
+后从中分配管理结构，并跟踪内存页使用情况
+，系统中哪些内存页是满的，哪些内存页面为空，哪些内存页没有完全
+使用。这样一来，系统就支持动态调整内存使用情况。除此之外，Linux还
+支持内存交换，因为Linux中使用的是虚拟内存，当物理内存不足时，内存管理子系
+统会将内存暂时移到磁盘中，在物理内存充裕时又将内存页从磁盘移到物理内存中，这就是内存交换。
+
+一般而言，在32位的系统上，每个进程都最大享有4GB的内存空间，因为由于32位的
+系统寻址空间只有4G，当然这是虚拟内存，0~3GB是属于用户内存空间，3~4GB是属于
+系统内存空间，实际上用户的程序几乎使用不完那么大的用户空间，一旦超出将无法正
+常运行，当然系统内存空间与用户内存空间是可以调整的。
 
 文件管理子系统
 '''''''
 
-在Linux系统中有一个重要的概念：一切皆文件，它把一切资源都看作是文件，包括硬件设备，通常称为设备文件。Linux的文件管理子系统主要实现了虚拟文件系统（Virtual File
-System，VFS），虚拟文件系统屏蔽了各种硬件上的差异以及具体实现的细节，为所有的硬件设备提供统一的接口，这样子也就实现了设备无关性，同时文件管理系统还为应用层提供统一的API接口。
+在Linux系统中有一个重要的概念：一切皆文件，它把一切资源都看
+作是文件，包括硬件设备，通常称为设备文件。Linux的文件管理子系
+统主要实现了虚拟文件系统（Virtual File
+System，VFS），虚拟文件系统屏蔽了各种硬件上的差异以及具体实现的细
+节，为所有的硬件设备提供统一的接口，这样子也就实现了设备无关性，同时文
+件管理系统还为应用层提供统一的API接口。
+
+总的来说，Linux 的文件系统体系结构是对一个对复杂系统进行了抽象化，通
+过使用一组通用的 API 函数，Linux 可以在许多种存储设备上支持多种文件系
+统，如NTFS、EXT2、EXT3、EXT4 、FAT等等；而用户空间包含一些应用程序和 GNU C
+库（glibc），它们使用的API接口是由系统调用层提供（如打开、读、写和关闭等），其框
+架如下图所示。
 
-总的来说，Linux 的文件系统体系结构是对一个对复杂系统进行了抽象化，通过使用一组通用的 API 函数，Linux 可以在许多种存储设备上支持多种文件系统，如NTFS、EXT2、EXT3、EXT4 、FAT等等；而用户空间包含一些应用程序和 GNU C
-库（glibc），它们使用的API接口是由系统调用层提供（如打开、读、写和关闭等），其框架如图 27‑7所示。
+.. image:: media/imagec008.png
+   :align: center
+   :alt: 未找到图片08|
 
-|imagec008|
 
-图 27‑7 文件系统
 
 网络子系统
 '''''
 
-在Linux 内核中，与网络相关的代码被Linux独立开，形成一个相对独立的子系统，称为网络子系统，网络子系统是一个层次化的结构，可分为以下几个层次：
+在Linux 内核中，与网络相关的代码被Linux独立开，形成一个相对独
+立的子系统，称为网络子系统，网络子系统是一个层次化的结构，可分为以下几个层次：
 
-1. Socket 层（也可以称之为协议无关层）：Linux 在发展过程中，采用 BSD Socket API 作为自己的网络相关的 API 接口。同时， Linux 的目标又要能支持各种不同的协议族，而且这些协议族都可以使用 BSD Socket API
-   作为应用层的编程接口，这样一来将Socket层抽象出来就能屏蔽不同协议族之间的差异，不会对应用层的使用产生影响。
+1. Socket 层（也可以称之为协议无关层）：Linux 在发展过程中，采
+   用 BSD Socket API 作为自己的网络相关的 API 接口。同时， Linux 的目标又要能
+   支持各种不同的协议族，而且这些协议族都可以使用 BSD Socket API
+   作为应用层的编程接口，这样一来将Socket层抽象出来就能屏蔽不同协议族之间的
+   差异，不会对应用层的使用产生影响。
 
-2. 协议层：Linux 网络子系统功能上相当完备，它不仅支持 INET 协议族（也就是通常所说的 TCP/IP 协议族），而且还支持其它很多种协议族，如 INET6、DECnet，ROSE，NETBEUI 等，对于 INET 、 INET6
-   协议族来说，又会进一步将协议族划分为传输层和网络层以及链路层等，此处就不深入分析。
+2. 协议层：Linux 网络子系统功能上相当完备，它不仅支持 INET 协议
+   族（也就是通常所说的 TCP/IP 协议族），而且还支持其它很多种协
+   议族，如 INET6、DECnet，ROSE，NETBEUI 等，对于 INET 、 INET6
+   协议族来说，又会进一步将协议族划分为传输层和网络层以及
+   链路层等，此处就不深入分析。
 
-3. 网络设备层：网络设备其实是设备驱动层的内容了，它抽象了网卡数据结构，在一个系统中可能存在多种网卡，屏蔽了不同硬件上的差异，这一层提供了一组通用函数供底层网络设备驱动程序使用。
+3. 网络设备层：网络设备其实是设备驱动层的内容了，它抽象了网卡
+   数据结构，在一个系统中可能存在多种网卡，屏蔽了不同硬件上的差
+   异，这一层提供了一组通用函数供底层网络设备驱动程序使用。
 
 ..
 
-   网络子系统框架如图 27‑8所示。
+   网络子系统框架如下图所示。
+
+.. image:: media/imagec009.png
+   :align: center
+   :alt: 未找到图片09|
 
-|imagec009|
 
-图 27‑8 网络子系统
 
 设备子系统
 '''''
 
-设备子系统又被称之为设备驱动，在日常生活中，嵌入式中使用的设备多种多样，如LCD、摄像头、USB、音频等都是属于设备，且设备的厂商不同其驱动程序也是不同的，但是对于Linux来说，不可能去将每个设备都包含到内核，它只能抽象去描述某种设备。
+设备子系统又被称之为设备驱动，在日常生活中，嵌入式中使用的设
+备多种多样，如LCD、摄像头、USB、音频等都是属于设备，且设备的厂
+商不同其驱动程序也是不同的，但是对于Linux来说，不可能去将每个设备
+都包含到内核，它只能抽象去描述某种设备。
 
-从前面的章节中可以了解到，系统调用层是Linux内核与应用程序之间的接口，而设备驱动则是Linux内核与硬件之间的接口，设备驱动程序为应用程序屏蔽了硬件的细节，这样在应用程序看来，硬件设备只是一个设备文件，应用程序可以象操作普通文件一样对硬件设备进行操作（打开、读、写和关闭）。设备驱动程序是内核的一
+从前面的章节中可以了解到，系统调用层是Linux内核与应用程序
+之间的接口，而设备驱动则是Linux内核与硬件之间的接口，设备驱动程
+序为应用程序屏蔽了硬件的细节，这样在应用程序看来，硬件设备只是一个
+设备文件，应用程序可以象操作普通文件一样对硬件设备进行操作（打开、读、写和关闭）。设备驱动程
+序是内核的一
 部分，它主要完成以下的功能：
 
 1. 对设备初始化和释放
@@ -226,18 +355,28 @@ System，VFS），虚拟文件系统屏蔽了各种硬件上的差异以及具
 
 -  网络设备
 
-先说说网络设备，它其实就是我们上一章网络子系统中描述的网络设备层，它其实也是一个抽象，统一描述了不同的网卡设备，如WIFI、以太网等。因为网络设备存在协议栈（协议族），它涉及了网络层协议，所以Linux将网络设备单独分层一类设备，网络设备的传输速率通常是很高的。
+先说说网络设备，它其实就是我们上一章网络子系统中描述的网络
+设备层，它其实也是一个抽象，统一描述了不同的网卡设备，如WIFI、以
+太网等。因为网络设备存在协议栈（协议族），它涉及了网络层协议，所
+以Linux将网络设备单独分层一类设备，网络设备的传输速率通常是很高的。
 
-字符设备是以字节为单位传输的IO设备，可以提供连续的数据流，应用程序可以顺序读取，通常不支持随机存取。这种字符传输的效率通常是比较低的，如鼠标、键盘、串口等都是字符设备，也是一种比较常见的设备。
+字符设备是以字节为单位传输的IO设备，可以提供连续的数据流，应用程
+序可以顺序读取，通常不支持随机存取。这种字符传输的效率通常是比较低
+的，如鼠标、键盘、串口等都是字符设备，也是一种比较常见的设备。
 
-块设备是以块为单位进行传输的设备，应用程序可以随机访问块设备中的数据，程序可以指定读取数据的位置。我们的磁盘就是一种常见的块设备，应用程序可以寻址磁盘上的任何位置，并在这个位置读取数据。不过需要注意的是，块设备读取的数据只能以块为单位的倍数进行（通常是512Byte的整数倍），而不能与字符设备一样以
+块设备是以块为单位进行传输的设备，应用程序可以随机访问块设备中的
+数据，程序可以指定读取数据的位置。我们的磁盘就是一种常见的块设备，应用
+程序可以寻址磁盘上的任何位置，并在这个位置读取数据。不过需要注意的是，块设
+备读取的数据只能以块为单位的倍数进行（通常是512Byte的整数倍），而不能与字符设备一样以
 字节为单位读取，因此通常来说块设备的传输速度是比较高的。
 
-设备驱动框架如图 27‑9所示。
+设备驱动框架如下图所示。
+
+.. image:: media/imagec010.png
+   :align: center
+   :alt: 未找到图片10|
 
-|imagec010|
 
-图 27‑9设备驱动
 
 dtb
 ~~~
@@ -245,12 +384,24 @@ dtb
 设备树简介
 ^^^^^
 
-在2011年之前，ARM Linux中存在大量描述芯片平台以及板级差异的垃圾代码，它们位于kernel/arch/arm/plat-xxx目录和kernel/arch/arm/mach-
-xxx目录下，用代码描述硬件，如注册platform设备，声明设备的resource等，但这些代码对于Linux内核来说都是垃圾，因此Linux创始人Linus
-Torvalds在2011年3月份向Linux社区发送一封邮件，他提出ARM架构平台应该参考其他平台如PowerPC的设备树机（Device Tree）制描述硬件，这样子在Linux内核中就不再需要进行大量的冗余编码，许多硬件及芯片平台的细节可以通过设备树传递给Linux内核。
-
-其实设备树是一种描述硬件的数据结构，它把这些硬件设备的信息，用一个非C语言的脚本语言来描述，而这个脚本文件，就是传说中的Device Tree（设备树），设备树包括设备树源码（Device Tree Source，DTS）文件、设备树编译工具（Device Tree
-Compiler，DTC）与二进制格式设备树（Device Tree Blob，DTB）。DTS包含的头文件格式为DTSI，DTS文件是一种人类可以看懂的编码格式，由节点（Node）和属性（Property）组成，节点中又可能会包含子节点，而属性则是可以简单理解为成对出现的名称与值，如下面的示例。
+在2011年之前，ARM Linux中存在大量描述芯片平台以及板级差
+异的垃圾代码，它们位于kernel/arch/arm/plat-xxx目录
+和kernel/arch/arm/mach-
+xxx目录下，用代码描述硬件，如注册platform设备，声明设
+备的resource等，但这些代码对于Linux内核来说都是垃圾，因此Linux创始人Linus
+Torvalds在2011年3月份向Linux社区发送一封邮件，他提出
+ARM架构平台应该参考其他平台如PowerPC的设备树机（Device Tree）制
+描述硬件，这样子在Linux内核中就不再需要进行大量的冗余编码，许多
+硬件及芯片平台的细节可以通过设备树传递给Linux内核。
+
+其实设备树是一种描述硬件的数据结构，它把这些硬件设备的信
+息，用一个非C语言的脚本语言来描述，而这个脚本文件，就是传
+说中的Device Tree（设备树），设备树包括设备树源码（Device Tree Source，DTS）文件、设
+备树编译工具（Device Tree
+Compiler，DTC）与二进制格式设备树（Device Tree Blob，DTB）。DTS包含的头
+文件格式为DTSI，DTS文件是一种人类可以看懂的编码格式，由节点（Node）和属
+性（Property）组成，节点中又可能会包含子节点，而属性则是可以简单理解为
+成对出现的名称与值，如下面的示例。
 
 node1 {
 
@@ -270,10 +421,16 @@ a-string-property = "Hello, world";
 
 };
 
-因为Uboot和Linux不能直接识别DTS文件，它们只能识别二进制文件，所以需要把DTS文件编译成DTB文件，而DTC就是将设备树源码文件（.dts /
-.dtsi）编译成二进制格式设备树文件（.dtb）的编译工具，它位于Linux内核源码的scripts/dtc目录下，在Linux配置中使能了设备树情况下，内核会自动编译对应的设备树，当然用户也可以单独编译设备树。
+因为Uboot和Linux不能直接识别DTS文件，它们只能识别二进制
+文件，所以需要把DTS文件编译成DTB文件，而DTC就是将设备树源
+码文件（.dts /
+.dtsi）编译成二进制格式设备树文件（.dtb）的编译工具，它位于Linux内
+核源码的scripts/dtc目录下，在Linux配置中使能了设备树情况下，内核会
+自动编译对应的设备树，当然用户也可以单独编译设备树。
 
-DTB可以被内核与BootLoader识别解析，通常在制作NAND Flash、SD Card启动镜像时，通常会为DTB文件留下一部分存储区域以存储DTB，在BootLoader启动内核时，会先读取DTB到内存。
+DTB可以被内核与BootLoader识别解析，通常在制作NAND Flash、SD Card启动
+镜像时，通常会为DTB文件留下一部分存储区域以存储DTB，在BootLoader启
+动内核时，会先读取DTB到内存。
 
 Linux的设备树中，可描述的硬件信息包括以下几类：
 
@@ -294,32 +451,58 @@ Linux的设备树中，可描述的硬件信息包括以下几类：
 DTS的加载过程
 ^^^^^^^^
 
-使用DTS描述了硬件的信息，那么怎么让内核识别这些信息呢？这就涉及到DTS的加载过程：当我们要使用Device Tree时，我们首先要了解自己的硬件配置和系统运行参数，并把这些信息组织成Device Tree Source 文件，然后通过DTC将这些适合人类阅读的DTS/DTSI
+使用DTS描述了硬件的信息，那么怎么让内核识别这些信息呢？这就涉及
+到DTS的加载过程：当我们要使用Device Tree时，我们
+首先要了解自己的硬件配置和系统运行参数，并把这些信息
+组织成Device Tree Source 文件，然后通过DTC将这些适合人类阅读的DTS/DTSI
 文件编译变成适合机器处理的DTB文件。
 
-在编译生成DTB文件后，还需要将它加载到Linux内核中，让内核来识别这些信息。在系统启动时，BootLoader会将保存在flash中的DTB拷贝到内存，并把DTB在内存中的起始地址传递给内核，其过程如图 27‑10所示。
+在编译生成DTB文件后，还需要将它加载到Linux内核中，让内核来识
+别这些信息。在系统启动时，BootLoader会将保存在flash中的DTB
+拷贝到内存，并把DTB在内存中的起始地址传递给内核，其过程如下图所示。
+
+.. image:: media/imagec002.png
+   :align: center
+   :alt: 未找到图片11|
 
-|imagec011|
 
-图 27‑10 DTS加载过程
 
 根文件系统
 ~~~~~
 
-此处讲解的文件系统是根文件系统（rootfs），它是linux在初始化时加载的第一个文件系统，而非我们在27.2.2 3文件管理子系统小节所说的文件系统，这两个是不同的概念。根文件系统包括根目录和真实文件系统，根文件系统之所以在前面加一个“根”，说明它是加载其它文件系统的“根”，如果没有这个“根”的
-话，其它的文件系统也就没有办法进行加载的。因为它包含系统引导和使其他文件系统得以挂载（mount）所必要的文件。根文件系统包函Linux启动时所必须的目录和关键性的文件，例如Linux启动时必要的初始化文件，它在init目录下，此外根文件系统中还包括了许多的应用程序bin目录等，任何包括这些Linu
+此处讲解的文件系统是根文件系统（rootfs），它是linux在初始化时
+加载的第一个文件系统，而非我们在27.2.2 3文件管理子系统小节所说
+的文件系统，这两个是不同的概念。根文件系统包括根目录和真实文件系统，根文
+件系统之所以在前面加一个"根"，说明它是加载其它文件系统的"根"，如果没有这个"根"的
+话，其它的文件系统也就没有办法进行加载的。因为它包含系统引导和使
+其他文件系统得以挂载（mount）所必要的文件。根文件系统包函Linux启动时
+所必须的目录和关键性的文件，例如Linux启动时必要的初始化文件，它在init目录下，此
+外根文件系统中还包括了许多的应用程序bin目录等，任何包括这些Linu
 x 系统启动所必须的文件都可以成为根文件系统。
 
-在Linux内核启动的初始阶段，首先内核会初始化一个基于内存的文件系统，如initramfs，initrd等，然后以只读的方式去加载根文件系统（load rootfs），读取并且运行/sbin/init初始化文件，根据/etc/inittab配置文件完成系统的初始化工作（提示：/sbin/init是
-一个二进制可执行文件，为系统的初始化程序，而/etc/inittab是它的配置文件），在初始化的过程中，还会以读写的方式重新挂载根文件系统，在系统启动后，根文件系统就可用于存储数据了，存在根文件系统是Linux启动时的必要条件。
+在Linux内核启动的初始阶段，首先内核会初始化一个基于内存的文件系
+统，如initramfs，initrd等，然后以只读的方式去加载根文件系统（load rootfs），读取并
+且运行/sbin/init初始化文件，根据/etc/inittab配置文件完成系统的初始化工作（提示：/sbin/init是
+一个二进制可执行文件，为系统的初始化程序，而/etc/inittab是它的配置文件），在初
+始化的过程中，还会以读写的方式重新挂载根文件系统，在系统启动后，根文件系统就可用于
+存储数据了，存在根文件系统是Linux启动时的必要条件。
 
-在Windows的目录结构中，可能会包括C:或者D:盘，它们一般就被称之为特定逻辑磁盘的根目录。从文件系统的层面来说，每一个分区都包含了一个根目录，即Windows系统中可以存在多个根目录。
+在Windows的目录结构中，可能会包括C:或者D:盘，它们一般就被称之为特定逻辑磁
+盘的根目录。从文件系统的层面来说，每一个分区都包含了一个根目录，即Windows系统中可
+以存在多个根目录。
 
-但是，在Linux系统中的文件系统目录结构与Windows上有较大的不同。系统中只有一个根目录，路径是“/”，而其它的分区只是挂载在根目录中的一个文件夹，如“/home”和“/sys”等，这里的“/”就是Linux中的根目录，因此Linux中只存在一个根目录，在Linux启动后，根目录就位于真实的文
+但是，在Linux系统中的文件系统目录结构与Windows上有较大的不同。系统中只有
+一个根目录，路径是"/"，而其它的分区只是挂载在根目录中的一个文件夹，如"/home"和"/sys"等，这
+里的"/"就是Linux中的根目录，因此Linux中只存在一个根目录，在Linux启动后，根目录就位于真实的文
 件系统中。
 
-Linux中的文件系统多种多样，同时在Linux中一切皆是文件，普通文件、目录、字符设备、块设备、套接字等都以文件方式被抽象化；且它们需要向上层提供统一的操作接口。虚拟文件系统VFS就是Linux内核中的一个软件层，向上给用户空间程序提供文件系统操作接口；向下允许不同的文件系统共存，所以，所有实际文
-件系统都必须实现VFS的结构封装。因为无论是访问设备还是需要通过文件系统来访问它的挂载点。
+Linux中的文件系统多种多样，同时在Linux中一切皆是文件，普通文件、目录、字符
+设备、块设备、套接字等都以文件方式被抽象化；且它们需要向上层提供统一的操作接口。虚拟文
+件系统VFS就是Linux内核中的一个软件层，向上给用户空间程序提供文件系统操作接口；向下
+允许不同的文件系统共存，所以，所有实际文件系统都必须实现VFS的结构封装。
+因为无论是访问设备还是需要通过文件系统来访问它的挂载点。
+
+
 
 .. |imagec002| image:: media/imagec002.png
    :width: 5.76806in
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diff --git a/documentation/building_image/using_buildroot.rst b/documentation/building_image/using_buildroot.rst
index 5a960688c9cb0f2e328c3ada11d45ebfc8032f04..6b3df217b8b99d6e395e686e831a1c8a359f980a 100644
--- a/documentation/building_image/using_buildroot.rst
+++ b/documentation/building_image/using_buildroot.rst
@@ -1,50 +1,58 @@
-.. vim: syntax=rst
+使用buildroot编译文件系统
+=========================
 
-使用Buildroot编译
+Buildroot简介
 -------------
 
-本章节内容处于开发笔记状态，还待整理至最终版的教程。
+Buildroot是一个简单，高效且易于使用的工具，可通过交叉编译生成嵌入式Linux系统。你可以很容易为你的目标系统构建交叉编译工具链、根文件系统、uboot以及Linux内核镜像，Buildroot可以独立的实现其中的一个或几个功能。Buildroot对于嵌入式开发人员来说是一个非常好用的工具，因为嵌入式不像x86平台（PC）一样硬件基本是统一的，嵌入式平台的硬件是根据需求进行裁剪，而不同的硬件对应的程序必然是不同，所以使用Buildroot来配置是一个非常好的选择。
 
-本章节内容处于开发笔记状态，还待整理至最终版的教程。
+整个Buildroot是由 ``Makefile脚本和Kconfig配置文件`` 构成的，用户可以和编译Linux内核一样，通过config文件进行配置要编译的参数，也可以通过 ``make menuconfig`` 等界面进行修改，然后通过make命令编译出一个完整的，可以直接烧写到开发板上运行的Linux系统软件（如 ``uboot、zimage、dtb`` 已及文件系统）。
 
-Buildroot简介
-~~~~~~~~~~~
+更重要的是Buildroot可以很方便添加第三方的编译源码并且编译，很多工具链、源码都可以从Buildroot社区下载，用户也可以让Buildroot从本地导入源码并，这就为我们的开发带来极大的便利，当需要从网上下载时，Buildroot自动可以帮我们下载，当在本地修改后，又可以直接使用Buildroot编译，它实现了工具链下载、解压、依赖包下载编译等一系列机械化的流程，对开发者非常友好。
 
-Buildroot是一个简单，高效且易于使用的工具，可通过交叉编译生成嵌入式Linux系统。你可以很容易为你的目标系统构建交叉编译工具链、根文件系统、uboot以及Linux内核镜像，Buildroot可以独立的实现其中的一个或几个功能。Buildroot对于嵌入式开发人员来说是一个非常好用的工具，
-因为嵌入式不像x86平台（PC）一样硬件基本是统一的，嵌入式平台的硬件是根据需求进行裁剪，而不同的硬件对应的程序必然是不同，所以使用Buildroot来配置是一个非常好的选择。
+Buildroot的官方网站是： https://buildroot.org/ ，我们可以打开官网然后下载我们需要的Buildroot工具，我们可以选择 ``buildroot-2019.02.4.tar.gz`` 这个版本的Buildroot作为我们的编译工具即可，虽然Buildroot一直在更新，但是无论是哪个版本基本都是差不多的，大家可以随意下载使用，具体见
 
-整个Buildroot是由Makefile脚本和Kconfig配置文件构成的，用户可以和编译Linux内核一样，通过config文件进行配置要编译的参数，也可以通过make
-menuconfig等界面进行修改，然后通过make命令编译出一个完整的，可以直接烧写到开发板上运行的Linux系统软件（如uboot、zimage、dtb已及文件系统）。
+.. figure:: media/usingb002.png
+   :alt: buildroot
 
-更重要的是Buildroot可以很方便添加第三方的编译源码并且编译，很多工具链、源码都可以从Buildroot社区下载，用户也可以让Buildroot从本地导入源码并，这就为我们的开发带来极大的便利，当需要从网上下载时，Buildroot自动可以帮我们下载，当在本地修改后，又可以直接使用Buildr
-oot编译，它实现了工具链下载、解压、依赖包下载编译等一系列机械化的流程，对开发者非常友好。
+   buildroot
+.. figure:: media/usingb003.png
+   :alt: buildroot
 
-Buildroot的官方网站是：\ https://buildroot.org/\
-，我们可以打开官网然后下载我们需要的Buildroot工具，我们可以选择buildroot-2019.02.4.tar.gz这个版本的Buildroot作为我们的编译工具即可，虽然Buildroot一直在更新，但是无论是哪个版本基本都是差不多的，大家可以随意下载使用，具体见图 32‑1、图
-32‑2。
+   buildroot
+除此之外Buildroot还有非常详细的文档说明，大家可以在Documentation页面下浏览与下载，当然野火提供的资料中也会存在Buildroot的文档说明buildroot-manual.pdf文件，具体见：
 
-|usingb002|
+.. figure:: media/usingb004.png
+   :alt: buildroot
 
-图 32‑1 Buildroot官网
+   buildroot
+在官网下载的Buildroot是官方的，里面并没有适配野火开发板的配置文件，因此，我还是建议大家在github或者gitee平台下载我们野火适配好的Buildroot源码，然后使用它来编译文件系统即可，如果你是高手，那么请随意玩耍~
 
-|usingb003|
+github仓库地址： https://github.com/Embedfire/ebf_6ull_buildroot
 
-图 32‑2 Buildroot工具版本
+下载
 
-除此之外Buildroot还有非常详细的文档说明，大家可以在Documentation页面下浏览与下载，当然野火提供的资料中也会存在Buildroot的文档说明buildroot-manual.pdf文件，具体见：
+.. code:: bash
+
+    git clone https://github.com/Embedfire/ebf_6ull_buildroot.git
 
-|usingb004|
+gitee仓库地址： https://gitee.com/wildfireteam/ebf_6ull_buildroot
 
-图 32‑3 Buildroot文档说明
+下载
+
+.. code:: bash
+
+    git clone https://gitee.com/wildfireteam/ebf_6ull_buildroot.git
 
 Buildroot目录简介
-~~~~~~~~~~~~~
+-----------------
 
-将下载好的Buildroot在虚拟机中解压后，就可以看到Buildroot的目录下存在很多文件夹如图 32‑4所示，下面就简单介绍一下这些文件夹的作用。
+将下载好的Buildroot在虚拟机中解压后，就可以看到Buildroot的目录下存在很多文件夹如图所示，下面就简单介绍一下这些文件夹的作用。
 
-|usingb005|
+.. figure:: media/usingb005.png
+   :alt: buildroot
 
-图 32‑4 Buildroot目录
+   buildroot
 
 -  arch：存放CPU架构相关的配置脚本，如arm、mips、x86等，这些与CPU相关的脚本在Buildroot制作编译工具链、编译uboot时起关键作用。
 
@@ -70,140 +78,191 @@ Buildroot目录简介
 
 -  utils：存放Buildroot一些通用工具。
 
--  dl：虽然一开始并没有dl（download）目录，但是在开始使用Buildroot后，会自动生成一个dl目录，它主要用于存放Buildroot工具下载的内容，因为Buildroot是一系列工具的管理集合，它本身并不存在这些编译工具，所以在使用时它自动会下载需要的工具，比如交叉编译器、依赖的库、以
-  及一些软件源码包等（以压缩包的形式存放，Buildroot在使用时会自动解压），都会放在dl目录下。
+-  dl：虽然一开始并没有dl（download）目录，但是在开始使用Buildroot后，会自动生成一个dl目录，它主要用于存放Buildroot工具下载的内容，因为Buildroot是一系列工具的管理集合，它本身并不存在这些编译工具，所以在使用时它自动会下载需要的工具，比如交叉编译器、依赖的库、以及一些软件源码包等（以压缩包的形式存放，Buildroot在使用时会自动解压），都会放在dl目录下。
+
+-  output：虽然一开始Buildroot也并没有output目录，但是在开始使用Buildroot后，就会自动生成output目录，它是编译出来的输出文件夹，里面存放着解压后的各种软件包编译完后的现场。同时output目录下还有各种文件夹，如host文件夹是由各类源码编译后在主机上运行工具的安装目录，如arm-linux-gcc就是安装在这里；build文件夹是所有源码包解压出来的文件存放地和编译的发生地；images文件夹则是在我们编译完成后存放uboot、内核镜像、设备树以及文件系统等结果的。
+
+    提示：对于其他的未列出来的目录，暂时不用去理会。
 
--  output：虽然一开始Buildroot也并没有output目录，但是在开始使用Buildroot后，就会自动生成output目录，它是编译出来的输出文件夹，里面存放着解压后的各种软件包编译完后的现场。同时output目录下还有各种文件夹，如host文件夹是由各类源码编译后在主机上运行工具的安装
-  目录，如arm-linux-gcc就是安装在这里；build文件夹是所有源码包解压出来的文件存放地和编译的发生地；images文件夹则是在我们编译完成后存放uboot、内核镜像、设备树以及文件系统等结果的。
+编译前的准备
+------------
 
-提示：对于其他的未列出来的目录，暂时不用去理会。
+Buildroot的使用是需要依赖源码包的，它会去寻找要编译的源码包，我们可以选择网络上的的源码包也可以选择本地的源码包，那么在这一章中我们就只选择本地的kernel与uboot源码包，从前面的章节我们也编译了kernel与uboot，此处对这些源码包就不再重复赘述，但是有一点读者必须要注意，更新了本地的源码包要用git记录，否则Buildroot不知道你已经更新过的。
 
-.. _使用buildroot编译-1:
+根据Buildroot官方文档说明，Buildroot会强制性使用一些工具包，如所示，这是为了Buildroot能正常编译，因此我们在使用前尽量查看一下当前系统的环境下是否存在这些软件包，或者可以直接通过sudo
+apt-get install命令去下载它们：
 
-使用Buildroot编译
-~~~~~~~~~~~~~
+.. code:: bash
 
-Buildroot的使用是需要依赖源码包的，它会去寻找要编译的源码包，我们可以选择网络上的的源码包也可以选择本地的源码包，那么在这一章中我们就只选择本地的kernel与uboot源码包，从前面的章节我们也编译了kernel与uboot，此处对这些源码包就不再重复赘述，但是有一点读者必须要注意，更新了
-本地的源码包要用git记录，否则Buildroot不知道你已经更新过的。
+    sudo apt-get install -y sed make binutils build-essential gcc g++ bash patch gzip bzip2 perl tar cpio python unzip rsync file bc wget g++-multilib
 
-根据Buildroot官方文档说明，Buildroot会强制性使用一些工具包，如所示，这是为了Buildroot能正常编译，因此我们在使用前尽量查看一下当前系统的环境下是否存在这些软件包，或者可以直接通过sudo apt-get install命令去下载它们：
+.. figure:: media/usingb006.png
+   :alt: buildroot
 
-命令
+   buildroot
+    提示：此处使用ubuntu18.04作为测试。
 
-sudo apt-get install which sed make binutils build-essential gcc g++ bash patch gzip bzip2 perl tar cpio python unzip rsync file bc wget
+选择配置文件
+------------
 
-|usingb006|
+Buildroot为了方便用户使用，在configs目录下提前配置好了很多平台的配置，我们可以在这里找一个与我们开发板最符合的配置文件，然后根据文件中的配置来修改出我们开发板的配置文件即可。当然野火是有提供默认的配置文件：
 
-图 32‑5 Buildroot文档中强制使用的软件包
+**1.带Qt Demo的配置：**
 
-Buildroot为了方便用户使用，在configs目录下提前配置好了很多平台的配置，我们可以在这里找一个与我们开发板最符合的配置文件，然后根据文件中的配置来修改出我们开发板的配置文件即可。当然野火是有提供默认的配置文件imx6ull_ebf_defconfig，它就是根据configs目录下的im
-x6ulevk_defconfig修改的，适配我们的imx6ull开发板。
+.. code:: bash
 
-首先将野火提供的imx6ull_ebf_defconfig文件拷贝到Buildroot的configs目录下，进入buildroot-2019.02.4目录下，输入以下命令查看configs目录下是否存在imx6ull_ebf_defconfig配置文件：
+    imx6ull_ebf_pro_defconfig
 
-命令
+**2.最小的完整镜像配置（文件系统6M左右）：**
 
-embedfire @embedfire_dev:~/buildroot/buildroot-2019.02.4$ ls configs/ \| grep imx6ull_ebf_defconfig
+.. code:: bash
 
-输出
+    imx6ull_ebf_minimal_defconfig
 
-imx6ull_ebf_defconfig
+**3.pico文件系统配置（不编译uboot与内核，文件系统5M左右）：**
 
-然后通过make imx6ull_ebf_defconfig命令将配置文件写入 .config文件：
+.. code:: bash
 
-命令
+    imx6ull_ebf_pico_defconfig
 
-embedfire @embedfire_dev:~/buildroot/buildroot-2019.02.4$ make imx6ull_ebf_defconfig
+    ps: 以上配置选择其中之一即可
 
-输出
+这些配置文件就是根据configs目录下的 ``imx6ulevk_defconfig`` 修改，适配我们野火的imx6ull开发板。
 
-## configuration written to /home/ embedfire /buildroot/buildroot-2019.02.4/.config#
+比如我们直接选择 ``imx6ull_ebf_pro_defconfig`` 作为我们编译的配置文件，那么可以运行以下命令将其写入到 ``.config`` 文件：
 
-很显然这操作过程与我们编译内核的过程是一样的，都是将配置文件的信息写入当前目录下的 .config文件中，然后通过make menuconfig命令进行配置，如图 32‑6所示：
+.. code:: bash
 
-|usingb007|
+    make imx6ull_ebf_pro_defconfig
 
-图 32‑6 make menuconfig配置界面
+    # 输出
+    #
+    # configuration written to /home/jiejie/ebf_6ull_buildroot/.config
+    #
 
+很显然这操作过程与我们编译内核的过程是一样的，都是将配置文件的信息写入当前目录下的
+.config文件中，然后通过make menuconfig命令进行配置：
+
+.. figure:: media/usingb007.png
+   :alt: buildroot
+
+   buildroot
 通过配置界面就可以很容易找的自己要配置的选项，我们可以来看看这些配置的主要功能：
+-
+``Target options  --->`` ：目标单板架构配置，在这里主要是选择要编译的平台架构，如cortex-A7；选择CPU的大小端模式，选择支持浮点等等，具体配置如下：
 
--  Target options --->：目标单板架构配置，在这里主要是选择要编译的平台架构，如cortex-A7；选择CPU的大小端模式，选择支持浮点等等，具体配置如下：
+.. figure:: media/usingb008.png
+   :alt: buildroot
 
-|usingb008|
+   buildroot
 
--  Build options --->：编译相关的配置，主要是一些编译时用到的选项，比如设置当前配置的保存位置（Location to save buildroot
-  config），根据自己的路径设置即可，设置dl的路径（下载代码包使用的路径：$(TOPDIR)/dl），多个线程编译的线程数量（如果设置为0则自动选择多个线程编译），是否使能编译器缓冲区；设置下载镜像Mirrors and Download
-  locations：一般来说Buildroot会默认从国外的网站下载镜像，而在国内下载则很慢，我们可以修改镜像源：
+-  ``Build options  --->`` ：编译相关的配置，主要是一些编译时用到的选项，比如设置当前配置的保存位置（Location
+   to save buildroot
+   config），根据自己的路径设置即可，设置dl的路径（下载代码包使用的路径：$(TOPDIR)/dl），多个线程编译的线程数量（如果设置为0则自动选择多个线程编译），是否使能编译器缓冲区；设置下载镜像Mirrors
+   and Download
+   locations：一般来说Buildroot会默认从国外的网站下载镜像，而在国内下载则很慢，我们可以修改镜像源：
 
-设置下载镜像Mirrors and Download locations：
+.. code:: bash
 
-内核镜像源：https://mirror.bjtu.edu.cn/kernelGNU镜像源：https://mirrors.tuna.tsinghua.edu.cn/gnu/清华镜像站汇总：https://mirrors.tuna.tsinghua.edu.cn/
+    #设置下载镜像Mirrors and Download locations：
+    内核镜像源：https://mirror.bjtu.edu.cn/kernel 
+    GNU镜像源：https://mirrors.tuna.tsinghua.edu.cn/gnu/ 
+    清华镜像站汇总：https://mirrors.tuna.tsinghua.edu.cn/
 
-提示：用清华镜像站会找不到内核。北京交通大学镜像站：https://mirror.bjtu.edu.cn/中国科学技术大学镜像站：http://mirrors.ustc.edu.cn/
+    # 提示：用清华镜像站会找不到内核。 
+    北京交通大学镜像站：https://mirror.bjtu.edu.cn/ 
+    中国科学技术大学镜像站：http://mirrors.ustc.edu.cn/
 
-   Build options具体配置如下：
+Build options具体配置如下:
 
-|usingb009|
+.. figure:: media/usingb009.png
+   :alt: buildroot
 
-图 32‑7 Build options配置
+   buildroot
+.. figure:: media/usingb010.png
+   :alt: buildroot
 
-|usingb010|
+   buildroot
+    如后期有改变则以配置文件为主，建议尽量不改动已发布的配置文件。
 
-图 32‑8设置下载镜像
+-  ``Toolchain  --->`` ：工具链选项主要是让用户选择合适自己的交叉编译工具链，可以选择Buildroot提供的工具链（内部工具链 ``Buildroot toolchain`` ），也可以指定其他非Buildroot提供的工具链（外部工具链 ``External toolchain`` ），我们默认选择外部提供的工具链： ``gcc-linaro-5.3.1-2016.05-x86_64_arm-linux-gnueabihf`` ，C库可以选择uClibc-ng,、glibc
+   和musl，我们选择glibc，还有选择内核头文件版本（要求比目标内核版本新）、是否使能宽字符（WCHAR）支持（如果需要支持Python则需要使能）、选择gcc编译器版本、是否使能c++等，具体配置如下：
 
--  Toolchain --->：工具链选项主要是让用户选择合适自己的交叉编译工具链，可以选择Buildroot提供的工具链（内部工具链Buildroot toolchain），也可以指定其他非Buildroot提供的工具链（外部工具链External
-  toolchain），我们默认使用Buildroot提供的工具链即可，C库可以选择uClibc-ng,、glibc 和musl，我们默认选择uClibc-
-  ng，还有选择内核头文件版本（要求比目标内核版本新）、是否使能宽字符（WCHAR）支持（如果需要支持Python则需要使能）、选择gcc编译器版本、是否使能c++等，具体配置如下：
+.. figure:: media/usingb011.png
+   :alt: buildroot
 
-|usingb011|
+   buildroot
 
-图 32‑9 Toolchain配置
+-  ``System configuration  --->`` ：系统相关的配置，比如配置系统主机名，它的主要作用是：在一个局域网中，每台机器都有一个主机名，用于主机与主机之间的便于区分，就可以为每台机器设置主机名，以便于以容易记忆的方法来相互访问；设置登陆界面的欢迎信息。选择密码的加密方式，我们可以选择SHA256加密算法（sha-25），设置root登陆的密码、设置默认的命令行终端（我们默认选择bash）、设置默认的登陆串口（开发板连接到电脑的输入/输出）、设置系统默认的环境变量（PATH）、以及选择构建系统镜像版本，根文件系统覆盖（野火的配置中就将一些脚本与相关内容放到 ``board/embedfire/ebf-imx6ull-pro/rootfs-overlay`` 目录下，在制作成文件系统时将这些文件添加到文件系统中）、以及一些运行的脚本（buildroot官方为imx6ull制作的打包脚本： ``board/freescale/common/imx/post-image.sh`` ）等，具体配置如下：
 
--  System configuration --->：系统相关的配置，比如配置系统主机名，它的主要作用是：在一个局域网中，每台机器都有一个主机名，用于主机与主机之间的便于区分，就可以为每台机器设置主机名，以便于以容易记忆的方法来相互访问；设置登陆界面的欢迎信息。选择密码的加密方式，我们可以选择SHA
-  256加密算法（sha-25），设置root登陆的密码、设置默认的命令行终端（我们默认选择bash）、设置默认的登陆串口（开发板连接到电脑的输入/输出）、设置系统默认的环境变量（PATH）、以及选择构建系统镜像版本，根文件系统覆盖、以及一些运行的脚本等，具体配置如下：
+.. figure:: media/usingb012.png
+   :alt: buildroot
 
-|usingb012|
+   buildroot
 
-图 32‑10 System配置
+-  ``Kernel  --->`` ：linux内核相关的配置，用户可以选择要编译的内核版本及源码，可以从网上下载（比如野火的配置文件就是从gitee仓库下载最新的内核源码），除此之外也可以从本地导入（其实对Buildroot来说也算是下载，因为这些文件都会被下载到dl目录下），还可以指定编译内核的默认配置文件（ ``imx6_v7_ebf，即imx6_v7_ebf_defconfig`` ，但此处的配置文件不需要后缀名defconfig）、内核二进制文件格式、选择是否编译设备树与指定编译的设备树（DTB）、以及其他的一些扩展。具体配置如下：
 
--  Kernel --->：linux内核相关的配置，用户可以选择要编译的内核版本及源码，可以从网上下载，也可以从本地导入（其实对Buildroot来说也算是下载，因为这些文件都会被下载到dl目录下），还可以指定编译内核的默认配置文件、内核二进制文件格式、选择是否编译设备树与指定编译的设备树（DTB）
-  、以及其他的一些扩展。具体配置如下：
+指定内核源码编译的设备树如下：
 
-要编译的设备树文件-Build a Device Tree Blob(DTB)：
+-  imx6ull-14x14-evk-btwifi.dtb
+-  imx6ull-14x14-evk.dtb
+-  imx6ull-14x14-evk-emmc-43.dtb
+-  imx6ull-14x14-evk-emmc-cam-dht11.dtb
+-  imx6ull-14x14-evk-emmc.dtb
+-  imx6ull-14x14-evk-emmc-hdmi.dtb
+-  imx6ull-14x14-evk-emmc-wifi.dtb
+-  imx6ull-14x14-evk-gpmi-weim-43.dtb
+-  imx6ull-14x14-evk-gpmi-weim-cam-dht11.dtb
+-  imx6ull-14x14-evk-gpmi-weim-hdmi.dtb
+-  imx6ull-14x14-evk-gpmi-weim-wifi.dtb
 
-imx6ull-14x14-evk-emmc-43 imx6ull-14x14-evk-emmc-50-70 imx6ull-14x14-evk imx6ull-14x14-evk-gpmi-weim imx6ull-14x14-evk-gpmi-weim-50-70
-imx6ull-14x14-evk-gpmi-weim-43 imx6ull-14x14-evk-emmc
+.. figure:: media/usingb013.png
+   :alt: buildroot
 
-|usingb013|
+   buildroot
 
-图 32‑11 Kernel 配置
+-  ``Target packages  --->`` ：这个是Buildroot的包管理相关的配置选项，读者可以从这里选择自己需要的软件包，Buildroot
+   提供了海量软件包可选，只需在配置界面选中所需要的软件包，交叉编译后即可使用。比如添加音视频应用相关的软件包、添加压缩和解压缩相关的软件包、添加字体、游戏、图形库（QT）、语言和脚本（Python、PHP等）、网络（蓝牙、wifi、http工具包）等软件包，在我们开发板就添加了支持QT与Python的软件包，因此可以在开发板中使用QT与Python，由于配置较多，就不再截图，根据配置文件查看即可。注意：Busybox是必选的。
 
--  Target packages --->：这个是Buildroot的包管理相关的配置选项，读者可以从这里选择自己需要的软件包，Buildroot 提供了海量软件包可选，只需在配置界面选中所需要的软件包，交叉编译后即可使用。比如添加音视频应用相关的软件包、添加压缩和解压缩相关的软件包、添加字体、游戏
-  、图形库（QT）、语言和脚本（Python、PHP等）、网络（蓝牙、wifi、http工具包）等软件包，在我们开发板就添加了支持QT与Python的软件包，因此可以在开发板中使用QT与Python，由于配置较多，就不再截图，根据配置文件查看即可。注意：Busybox是必选的。
+    假设我们系统中缺失一些库，那么可以在这里选择有没有对应的软件包，如果没有则需要自己手动制作了。
 
--  Filesystem images --->：文件系统镜像配置。可以选择生成的文件系统镜像类型 ，如tar、cpio、ext2/3/4、 jffs2、 yaffs2 和 ubifs 等。文件系统镜像可能会非常大，具体取决于你选择的文件系统类型、软件包的数量以及是否配置的可用空间等，具体配置如下：
+-  ``Filesystem images  --->`` ：文件系统镜像配置。可以选择生成的文件系统镜像类型
+   ，如 ``tar、cpio、ext2/3/4、 jffs2、 yaffs2 和 ubifs``
+   等。文件系统镜像可能会非常大，具体取决于你选择的文件系统类型、软件包的数量以及是否配置的可用空间等，具体配置如下：
 
-|usingb014|
+.. figure:: media/usingb014.png
+   :alt: buildroot
 
-图 32‑12 Filesystem配置
+   buildroot
 
--  Bootloaders --->：Bootloaders 相关的配置，在这个配置选项中，读者可以选择要编译的Bootloaders 引导程序（如grub2、ts4800-mbrboot、uboot等，我们默认选择uboot），指定uboot的名字、下载的位置（可以是从网上下载，写入正确的URL即可
-  ；也可以从本地导入，写入本地路径即可），指定uboot的版本，我们默认使用imx_v2016.03_4.1.15_2.0.0_ga标签的版本，具体配置如下：
+-  ``Bootloaders  --->`` ：Bootloaders相关的配置，在这个配置选项中，读者可以选择要编译的Bootloaders
+   引导程序（如 ``grub2、ts4800-mbrboot、uboot`` 等，我们默认选择uboot），指定uboot的名字、下载的位置（可以是从网上下载，写入正确的URL即可；也可以从本地导入，写入本地路径即可），指定uboot的版本，我们默认使用野火的uboot仓库，使用最新发布的uboot版本，具体配置如下：
 
-|usingb015|
+.. figure:: media/usingb015.png
+   :alt: buildroot
 
-图 32‑13 Bootloaders 配置
+   buildroot
 
--  Host utilities --->：主机通用配置，使用默认配置即可。
+-  ``Host utilities  --->`` ：主机通用配置，使用默认配置即可。
 
--  Legacy config options --->：使用默认配置即可。
+-  ``Legacy config options  --->`` ：使用默认配置即可。
 
 当配置完成，退出后会发现所有的配置都被写入当前目录下的 .config文件：
 
-configuration written to /home/ embedfire /buildroot/buildroot-2019.02.4/.config**\* End of the configuration.**\* Execute 'make' to start the build
-or try 'make help'.
+.. code:: bash
+
+    configuration written to /home/jiejie/ebf_6ull_buildroot/.config
+
+    *** End of the configuration.
+    *** Execute 'make' to start the build or try 'make help'.
 
-然后我们可以执行make命令，make命令通常会执行以下步骤：
+如果你想将这次配置的文件保存起来，那么可以通过以下命令保存：
+
+::
+
+     make savedefconfig 
+
+然后我们可以执行 ``make`` 命令进行编译操作， ``make`` 命令通常会执行以下步骤：
 
 1. 根据配置需要下载源文件
 
@@ -217,115 +276,74 @@ or try 'make help'.
 
 6. 以所选格式创建根文件系统
 
-执行make命令后就等待它编译完成即可，在编译完成后可以在output/images目录下找到编译产生的镜像，具体见图 32‑14。
-
-|usingb016|
+执行 ``make`` 命令后就等待它编译完成即可，在编译完成后可以在 ``output/images`` 目录下找到编译产生的镜像，具体见
 
-图 32‑14 output/images目录
+.. figure:: media/usingb016.png
+   :alt: buildroot
 
-编译生成的设备树、内核、文件系统等都可以烧录到野火imx6ull开发板上，具体的烧录过程在28.3.5 烧录测试小节中已经讲解，此处就不再重复赘述。
+   buildroot
+编译生成的设备树、内核、文件系统等都可以烧录到野火imx6ull开发板上，具体的烧录过程在烧录测试小节中已经讲解，此处就不再重复赘述。
 
 Buildroot其他分析
-~~~~~~~~~~~~~
+-----------------
 
 正如前面所说的Buildroot是一个非常强大的工具，它可以随意依赖第三方的库以及工具，能快速构建我们需要的内容，如果你想了解一下Buildroot编译生成的内容的一些时间、依赖、大小等情况，通过代码肯定是不方便，Buildroot还提供可视化分析的工具，我们只需一句命令即可使用它们。
 
-当然，按照官方文档的说明，需要在主机上安装必须的软件包python-matplotlib 和python-numpy，我们可以通过以下命令进行安装：
+当然，按照官方文档的说明，需要在主机上安装必须的软件包python-matplotlib
+和python-numpy，我们可以通过以下命令进行安装：
 
-命令
+.. code:: bash
 
-sudo apt-get install -y python-matplotlib python-numpy
+    sudo apt-get install -y python-matplotlib python-numpy
 
 Buildroot的工作之一是了解包之间的依赖关系，并确保它们以正确的顺序构建。
-这些依赖关系有时可能非常复杂，对于给定的系统，通常不容易理解为什么这样或那样的包被Buildroot引入并且成功构建。为了帮助理用户解依赖关系，从而更好地理解嵌入式Linux系统中不同组件的作用，Buildroot能够生成依赖关系图，通过make graph-
-depends命令即可生成对应的依赖文件（默认是PDF格式），具体情况如下：
-
-命令
-
-make graph-depends
-
-最后输出提示：
-
--o /home/ embedfire /buildroot/buildroot-2019.02.4/output/graphs/graph-depends.pdf
-\\/home/embedfire/buildroot/buildroot-2019.02.4/output/graphs/graph-depends.dot
-
-当然，Buildroot还能生成关于编译时间与编译占用资源大小的分析图，只需要通过make graph-build与make graph-size命令生成即可，具体见（已删减输出信息）：
-
-命令
-
-make graph-build
-
-make graph-size
-
-然后可以看到在output/graphs目录下多了一些pdf文件，这些就是Buildroot生成的可视化分析文件，可以直接打开他们，具体见图 32‑15、图 32‑16和图 32‑17。
-
-|usingb017|
-
-图 32‑15生成的可视化分析文件
-
-|usingb018|
-
-图 32‑16 依赖关系
-
-|usingb019|
-
-图 32‑17 占用资源大小分析
-
-命令
-
-embedfire @embedfire_dev:~/imx-linux$ git log
-
-.. |usingb002| image:: media/usingb002.png
-   :width: 5.76806in
-   :height: 2.85583in
-.. |usingb003| image:: media/usingb003.png
-   :width: 5.76806in
-   :height: 2.76841in
-.. |usingb004| image:: media/usingb004.png
-   :width: 5.76806in
-   :height: 3.16556in
-.. |usingb005| image:: media/usingb005.png
-   :width: 2.13067in
-   :height: 4.432in
-.. |usingb006| image:: media/usingb006.png
-   :width: 3.368in
-   :height: 4.97743in
-.. |usingb007| image:: media/usingb007.png
-   :width: 5.76806in
-   :height: 3.38371in
-.. |usingb008| image:: media/usingb008.png
-   :width: 3.99167in
-   :height: 1.24028in
-.. |usingb009| image:: media/usingb009.png
-   :width: 5.76806in
-   :height: 2.45178in
-.. |usingb010| image:: media/usingb010.png
-   :width: 5.76806in
-   :height: 2.35666in
-.. |usingb011| image:: media/usingb011.png
-   :width: 4.14179in
-   :height: 4.68741in
-.. |usingb012| image:: media/usingb012.png
-   :width: 5.69403in
-   :height: 3.714in
-.. |usingb013| image:: media/usingb013.png
-   :width: 5.68657in
-   :height: 2.79197in
-.. |usingb014| image:: media/usingb014.png
-   :width: 4.68161in
-   :height: 4.02239in
-.. |usingb015| image:: media/usingb015.png
-   :width: 5.52807in
-   :height: 3.51493in
-.. |usingb016| image:: media/usingb016.png
-   :width: 3.48986in
-   :height: 5.60448in
-.. |usingb017| image:: media/usingb017.png
-   :width: 5.76806in
-   :height: 2.74714in
-.. |usingb018| image:: media/usingb018.png
-   :width: 5.76806in
-   :height: 2.47858in
-.. |usingb019| image:: media/usingb019.png
-   :width: 5.76806in
-   :height: 3.73585in
+这些依赖关系有时可能非常复杂，对于给定的系统，通常不容易理解为什么这样或那样的包被Buildroot引入并且成功构建。为了帮助理用户解依赖关系，从而更好地理解嵌入式Linux系统中不同组件的作用，Buildroot能够生成依赖关系图，通过make
+graph-depends命令即可生成对应的依赖文件（默认是PDF格式），具体情况如下：
+
+.. code:: bash
+
+    命令
+    make graph-depends
+
+    最后输出提示：
+    -o /home/ embedfire /buildroot/buildroot-2019.02.4/output/graphs/graph-depends.pdf  /home/embedfire/buildroot/buildroot-2019.02.4/output/graphs/graph-depends.dot
+
+当然，Buildroot还能生成关于编译时间与编译占用资源大小的分析图，只需要通过make
+graph-build与make graph-size命令生成即可，具体见（已删减输出信息）：
+
+.. code:: bash
+
+    命令
+    make graph-build
+
+    make graph-size
+
+然后可以看到在output/graphs目录下多了一些pdf文件，这些就是Buildroot生成的可视化分析文件，可以直接打开他们，具体见：
+
+.. figure:: media/usingb017.png
+   :alt: buildroot
+
+   buildroot
+.. figure:: media/usingb018.png
+   :alt: buildroot
+
+   buildroot
+.. figure:: media/usingb019.png
+   :alt: buildroot
+
+   buildroot
+其他的一些问题
+--------------
+
+由于buildroot会在国外的网站下载很多东西，所以在下载时会很慢很慢，有可能出现下载失败的情况，那么可以根据日志信息手动去下载对应的软件包。
+
+如果在生成镜像时失败，可以尝试清除一下install状态，然后重新编译。
+
+.. code:: bash
+
+    ./clear.sh 
+
+还有需要注意的是：由于本项目是 ``Buildroot`` 使用
+``arm-linux-gnueabihf-5.3.1``
+编译工具链编译的，与单独编译的内核镜像使用的编译器版本不一致，可能会导致某些内核模块无法加载，因此如果有必要的话，将 ``output/images/`` 目录下的内核镜像
+``zImage`` 替换掉原本的内核镜像！同理，设备树亦是如此！
diff --git a/documentation/index.rst b/documentation/index.rst
index 7e4ca0a9a7ae2528d1a7eb80694bdd753155b0bc..29a31e5c1cc8955f4fc1c7fac00a92fc4fc37d45 100644
--- a/documentation/index.rst
+++ b/documentation/index.rst
@@ -16,10 +16,11 @@
 
 .. toctree::
    :maxdepth: 1
-   :caption: 搭建并熟悉开发环境
+   :caption: 熟悉linux操作系统
    :numbered:
 
    linux_basis/why_learning_linux
+   linux_basis/how_to_learn_linux
    linux_basis/i_mx_series
    linux_basis/linux_brief
    linux_basis/installing_linux
@@ -28,20 +29,35 @@
    linux_basis/command_line
    linux_basis/software_package
    linux_basis/editor
+   #linux_basis/git_tutorial
+   
+
+.. toctree::
+   :maxdepth: 1
+   :caption: 熟悉EBF_6ULL开发板
+   :numbered:
+
    linux_basis/ebf6ull_hardware
+   install_image/install_debian_to_sd
    linux_basis/board_startup
    linux_basis/system_information
+   linux_basis/fire-config_brief
    linux_basis/led_key_command_line_testing
    linux_basis/script_hardware_testing
-
+   linux_basis/ec20_4g_module
 
 .. toctree::
    :maxdepth: 1
    :caption: 在Linux下开发应用程序
    :numbered:
 
+   linux_app/git_use
    linux_app/mount_nfs
    linux_app/gcc_hello_world
+   linux_app/arm_gcc_hello_world.rst
+   linux_app/hello_in_linux.rst
+   linux_app/Makefile_brife.rst
+   linux_app/makefile
    linux_app/filesystem_system_call
    linux_app/led_subsystem
    linux_app/gpio_subsystem
@@ -52,24 +68,37 @@
 
 .. toctree::
    :maxdepth: 1
-   :caption: 安装系统镜像
+   :caption: 制作系统镜像
    :numbered:
 
-   install_image/install_sd_image
-   install_image/sdcard_production
-   install_image/mfgtool_production
+
+   building_image/image_composition
+   building_image/building_NXP_firmware
+   building_image/burning_NXP_firmware
+   building_image/building_debian
+
+
+   #building_image/building_kernel
+   #building_image/building_uboot
+   #building_image/building_rootfs
+   #building_image/using_buildroot
+   #building_image/using_yocto
+   #building_image/building_debian
 
 .. toctree::
    :maxdepth: 1
-   :caption: 制作系统镜像
+   :caption: 环境搭建
    :numbered:
 
-   building_image/image_composition
-   building_image/building_kernel
-   building_image/building_uboot
-   building_image/building_rootfs
-   building_image/using_buildroot
-   building_image/using_yocto
+   linux_env/qt_cross_compiling
+   linux_env/python37_env
+   linux_env/pyqt5_env
+   linux_env/python_ssd1306
+   linux_env/python_gpio
+   linux_env/python_serial
+   linux_env/using_sqlite
+   linux_env/using_qtsqlite
+   linux_env/using_php
 
 .. toctree::
    :maxdepth: 1
@@ -79,6 +108,40 @@
    system_programing/process
    system_programing/pipe
    system_programing/signal
+   system_programing/msg_queuq
+   system_programing/systemV_sem
+   system_programing/shm
+   system_programing/thread
+   system_programing/posix_sem
+   system_programing/posix_mutex
+   system_programing/tcp_ip
+   system_programing/socket
+
+.. toctree::
+   :maxdepth: 1
+   :caption: Linuxn内核调试
+   :numbered:
+
+   linux_debug/gdb_use
+   linux_debug/core_dump
+   linux_debug/backtrace
+   linux_debug/strace
+
+.. toctree::
+   :maxdepth: 1
+   :caption: Linux物联网编程
+   :numbered:
+
+   linux_iot/linux_http
+   linux_iot/linux_http_client
+   linux_iot/linux_http_server
+   linux_iot/canopen
+   linux_iot/modbus
+   linux_iot/ATGM332D
+   linux_iot/mqtt
+   linux_iot/mqtt-client
+   linux_iot/mqtt-baidu
+   linux_iot/mqtt-onenet
 
 
 .. toctree::
@@ -101,15 +164,24 @@
    bare_metal/ddr
    bare_metal/elcdif
 
-
 .. toctree::
    :maxdepth: 1
    :caption: Linux驱动开发
    :numbered:
 
-   linux_driver/character_device
    linux_driver/module
-
+   linux_driver/character_device
+   linux_driver/led_character_device
+   linux_driver/linux_device_model
+   linux_driver/platform_driver
+   linux_driver/driver_tree
+   linux_driver/device_tree_rgb_led
+   linux_driver/dynamic_device_tree
+   linux_driver/gpio_subsystem
+   linux_driver/concurrency
+   linux_driver/i2c_mpu6050.rst
+   
+   
 .. toctree::
    :maxdepth: 1
    :caption: 附录
@@ -126,6 +198,10 @@
    submission/ubuntu16-rootfs
    submission/debian9-rootfs
    submission/野火IMX6UL开发板SDK使用说明
+   submission/buildroot2017-1
+   submission/buildroot2017-2
+   submission/buildroot2017-3
+
 
 .. toctree::
    :maxdepth: 1
diff --git a/documentation/install_image/install_debian_to_sd.rst b/documentation/install_image/install_debian_to_sd.rst
new file mode 100644
index 0000000000000000000000000000000000000000..3c6c98916aed964c1583d0d4ba2e961a3f604843
--- /dev/null
+++ b/documentation/install_image/install_debian_to_sd.rst
@@ -0,0 +1,131 @@
+.. vim: syntax=rst
+
+SD卡烧录Debian镜像
+---------------------
+本章节讲解如何把Debian镜像烧录到SD卡，如果想把镜像烧录至板载eMMC或NAND FLASH，也要先制作这个SD卡镜像，从SD卡启动开发板。然后再参考下一章节，使用SD卡镜像系统中的fire-config工具刷机到eMMC或NAND FLASH。
+
+Etcher工具简介
+~~~~~~~~~~~~~~~~~
+
+Etcher是一款简易好用的镜像烧录工具，主要用于刻录镜像到USB设备，包括SD卡和U盘，
+支持ios、img、zip、raw、sdcard等多种镜像格式。它的用户界面清爽美观，操作简单，
+在软件自动识别到USB设备后，点击几次鼠标就能完成镜像的烧录。
+
+同时Etcher是一个跨平台工具，支持 Mac、Windows 和 Linux ，
+国内外开发者常用它将树莓派SD卡启动镜像烧录到SD卡中。
+
+下载安装Etcher工具
+~~~~~~~~~~~~~~~~~~~~~~
+
+打开Etcher官网地址:  https://www.balena.io/etcher/\,
+在官网首页有Etcher工具的下载链接，用户可以根据自己的操作系统类型，来下载对应版本的软件安装包。
+
+..  image:: media/instal002.png
+    :align: center
+    :alt: Etcher工具
+
+下载完成后，直接安装软件即可。
+
+烧录Debian镜像
+~~~~~~~~~~~~~~~~~~~~~
+
+1、下载野火最新发布的Debian系统镜像：
+
+百度云网盘:
+
+.. code-block:: sh
+   :linenos:
+
+    http://products.embedfire.com/zh_CN/latest/linux/ebf_i.mx6ull.html#debian
+
+SOURCEFORGE:
+
+.. code-block:: sh
+   :linenos:
+
+   https://sourceforge.net/projects/ebf-debian-firmware/files/
+
+2、打开安装好的Etcher工具，软件界面如下图所示:
+
+..  image:: media/instal003.png
+    :align: center
+    :alt: Etcher工具
+
+
+
+3、选择要烧录的镜像，野火提供的Debian镜像三个不同版本，如下图所示:
+
+..  image:: media/install_debian3.png
+    :align: center
+    :alt: Debian镜像
+
+
+镜像标注的解压后容量为SD、eMMC、NAND等目标存储器需要的最小空间:
+
+- imx6ull-debian-buster-console-armhf-2020-04-09.img.xz:
+
+    Debian的纯净版固件，没有带桌面环境和野火的QT App。（解压后约340M）
+
+- imx6ull-debian-buster-desktop-armhf-2020-04-09.img.xz: 
+    
+    带有桌面环境的Debian固件，系统启动后会进入桌面环境。（解压后约1.1G）
+
+- imx6ull-debian-buster-full-qt-app-armhf-2020-04-09.img.xz: 
+    
+    具有完整QT App功能的Debian固件,系统启动后会进入QT App的界面。
+    
+    但是该固件体积超过了Nandflash 512M的容量，因此不能烧录到Nandflash中。只可烧录于eMMC。（解压后约900M）
+
+- imx6ull-debian-buster-part-qt-app-armhf-2020-04-09.img.xz: 
+
+    该固件移除了音视频播放功能的QT App，系统启动后会进入QT App的界面。
+    
+    该固件体积小于Nandflash 512M的容量，可以分别烧录到Nandflash和eMMC中。(解压后约420M)
+
+- README.txt:文件有固件的使用说明以及版本改动的记录。
+
+- SHA256SUMS.txt:记录各个固件的sha256校验值。
+
+
+4、选择好Debian镜像后，继续选择要烧录的SD卡，然后点击"flash"按钮开始进行烧录。
+
+..  image:: media/instal005.png
+    :align: center
+    :alt: Debian镜像
+
+烧录过程会显示镜像的烧录进度，如下图
+
+..  image:: media/instal006.png
+    :align: center
+    :alt: Debian镜像
+
+5、等到软件出现出现如下界面时，表示镜像已经成功烧录完毕。
+
+..  image:: media/install_debian7.png
+    :align: center
+    :alt: Debian镜像
+
+6、开发板插入烧录好Debian镜像的SD卡，调整拨码开关为SD卡启动方式，上电后开发板就能正常启动。
+
+注意:开发板第一次从SD卡启动时，系统会自动进行SD卡扩容，
+以保证充分利用SD卡存储空间。扩容完毕后，系统自动重启生效。
+
+系统启动以后，输入用户密码登录即可：
+
+普通用户:
+
+.. code-block:: sh
+   :emphasize-lines: 2
+   :linenos:
+
+   账户:debian
+   密码:temppwd
+
+ROOT用户:
+
+.. code-block:: sh
+   :emphasize-lines: 2
+   :linenos:
+
+   账户:root
+   密码:root
diff --git a/documentation/install_image/install_sd_image.rst b/documentation/install_image/install_sd_image.rst
index 4c656f49cf907bf17bb78d3e8ef8221ee25d65ee..f0da5102f8c58e293be0e624655435fe44b61658 100644
--- a/documentation/install_image/install_sd_image.rst
+++ b/documentation/install_image/install_sd_image.rst
@@ -3,9 +3,6 @@
 使用Etcher烧录镜像到SD卡
 ----------------
 
-本章节内容处于开发笔记状态，还待整理至最终版的教程。
-
-本章节内容处于开发笔记状态，还待整理至最终版的教程。
 
 Etcher工具简介
 ~~~~~~~~~~
@@ -23,38 +20,58 @@ Etcher 是一个快速将镜像文件烧录到 USB 设备或 SD 卡中的工具
 下载Etcher
 ~~~~~~~~
 
-首先打开官网：\ https://www.balena.io/etcher/\ ，在首页就可以看到Etcher工具的下载位置，如图 26‑1所示，下载完毕直接安装即可。
+首先打开官网：\ https://www.balena.io/etcher/\ ，在首页就可以看到Etcher工具的下载位置，如下图所示，下载完毕直接安装即可。
+
+
+
+
+.. image:: media/instal002.png
+   :align: center
+   :alt: 未找到图片2|
 
-|instal002|
 
-图 26‑1下载Etcher
 
 使用Etcher工具烧录
 ~~~~~~~~~~~~
 
-首先打开已经安装完成的Etcher，启动界面如图 26‑2所示。
+首先打开已经安装完成的Etcher，启动界面如下图所示。
+
+.. image:: media/instal003.png
+   :align: center
+   :alt: 未找到图片3|
+
+
+
+然后选择要烧录的SD卡镜像，野火提供的SD卡镜像是.sdcard格式的，如
+下图所示，可以直接烧录到SD卡中，我们可以选择core-image-sato-imx6ull14x14evk.sdcard镜像烧录即可。
+
+.. image:: media/instal004.png
+   :align: center
+   :alt: 未找到图片4|
+
+
 
-|instal003|
+接着选择要烧录的SD卡，如果你的电脑只是插入一个SD卡，那么Etcher会自动识
+别你的SD卡，在烧录的过程中，SD卡会被分区并且格式化，选择完毕后直
+接点击"Flash"进行烧录操作，具体见下图。
 
-图 26‑2 Etcher启动界面
+.. image:: media/instal005.png
+   :align: center
+   :alt: 未找到图片5|
 
-然后选择要烧录的SD卡镜像，野火提供的SD卡镜像是.sdcard格式的，如图 26‑3所示，可以直接烧录到SD卡中，我们可以选择core-image-sato-imx6ull14x14evk.sdcard镜像烧录即可。
 
-|instal004|
 
-图 26‑3 SD卡镜像
+.. image:: media/instal006.png
+   :align: center
+   :alt: 未找到图片6|
 
-接着选择要烧录的SD卡，如果你的电脑只是插入一个SD卡，那么Etcher会自动识别你的SD卡，在烧录的过程中，SD卡会被分区并且格式化，选择完毕后直接点击“Flash”进行烧录操作，具体见图 26‑4与图 26‑5。
 
-|instal005|
 
-图 26‑4 选择SD卡与烧录
+当制作成功后，将SD卡插入开发板中，并且将拨码开关
+的2/5/8打到ON档（SD启动方式），然后给开发板上电就可以看到开发板正常启动。
 
-|instal006|
 
-图 26‑5 烧录界面
 
-当制作成功后，将SD卡插入开发板中，并且将拨码开关的2/5/8打到ON档（SD启动方式），然后给开发板上电就可以看到开发板正常启动。
 
 .. |instal002| image:: media/instal002.png
    :width: 5.31343in
diff --git a/documentation/install_image/media/install_debian3.png b/documentation/install_image/media/install_debian3.png
new file mode 100644
index 0000000000000000000000000000000000000000..671fc9a7b5ae5a608450cb93b32b086ab338fd27
Binary files /dev/null and b/documentation/install_image/media/install_debian3.png differ
diff --git a/documentation/install_image/media/install_debian4.png b/documentation/install_image/media/install_debian4.png
new file mode 100644
index 0000000000000000000000000000000000000000..faa47c508251f66424b915ef88dca9ce67344224
Binary files /dev/null and b/documentation/install_image/media/install_debian4.png differ
diff --git a/documentation/install_image/media/install_debian7.png b/documentation/install_image/media/install_debian7.png
new file mode 100644
index 0000000000000000000000000000000000000000..b6de57a46b6279d01e06e4f08c0173655c1c99fa
Binary files /dev/null and b/documentation/install_image/media/install_debian7.png differ
diff --git a/documentation/install_image/mfgtool_production.rst b/documentation/install_image/mfgtool_production.rst
index b4d20e7236ad15e0dfcbdccb9e53f2b23649e28e..92fb4b78ef85c4f2b60ea1ca5eb3c7b7fcfc3423 100644
--- a/documentation/install_image/mfgtool_production.rst
+++ b/documentation/install_image/mfgtool_production.rst
@@ -12,35 +12,56 @@ MFGtool工具
 MFGtool工具的作用
 ~~~~~~~~~~~~
 
-MFGTool工具是freescale官方推荐的一个使用OTG来升级镜像的软件工具，它是freescale针对i.MX系列处理器专门使用的烧录工具，可以用来升级linux，单独烧录某一系统分区，独立地烧录spi flash、 nor flash、sd card、nand
-flash，emmc等，只需简单的配置，就可以使用该工具将编译好的文件系统和镜像文件烧录到开发板上，使用起来非常方便。而且MFGtool工具作为一个可量产性的工具，它支持多通道的烧录，在实际量产中，可以直接使用MFGtool工具同时将文件系统与镜像文件烧录到多个开发板上。
+MFGTool工具是freescale官方推荐的一个使用OTG来升级镜像的软
+件工具，它是freescale针对i.MX系列处理器专门使用的烧
+录工具，可以用来升级linux，单独烧录某一系统分区，独立
+地烧录spi flash、 nor flash、sd card、nand
+flash，emmc等，只需简单的配置，就可以使用该工具将编译好
+的文件系统和镜像文件烧录到开发板上，使用起来非常方便。而
+且MFGtool工具作为一个可量产性的工具，它支持多通道的烧录，在实
+际量产中，可以直接使用MFGtool工具同时将文件系统与镜像文件烧录
+到多个开发板上。
 
-MFGtool工具目录主要有以下内容，具体见图 28‑1。
+MFGtool工具目录主要有以下内容，具体见下图。
 
-|mfgtoo002|
+.. image:: media/mfgtoo002.png
+   :align: center
+   :alt: 未找到图片2|
 
-图 28‑1MFGtool工具目录
 
-该目录其实是已省略很多内容的，其中主要的文件夹是Profile，里面存放着的是镜像文件，这里面镜像文件分为两种：第一种是作为媒介用途的镜像，包括uboot、dtb与uImage；第二种是真正烧录到emmc、sdcard或者nand
-flash的镜像文件。之所以存在这两种镜像，是因为MFGTools的烧录原理是先烧录媒介镜像到ram里面，然后启动，再通过这个启动了的媒介镜像把目标镜像烧录到emmc、sdcard或者nand flash里面。
 
-除此之外还有配置文件也是非常重要的，如cfg.ini、UICfg.ini以及ucl2.xml（该文件位于Profiles\Linux\OS Firmware目录下，此处就不再截图说明）。
+该目录其实是已省略很多内容的，其中主要的文件夹是Profile，里面存放着的
+是镜像文件，这里面镜像文件分为两种：第一种是作为媒介用途的
+镜像，包括uboot、dtb与uImage；第二种是真正烧录到emmc、sdcard或者nand
+flash的镜像文件。之所以存在这两种镜像，是因为MFGTools的烧录
+原理是先烧录媒介镜像到ram里面，然后启动，再通过这个启动了的媒介镜像
+把目标镜像烧录到emmc、sdcard或者nand flash里面。
 
-MfgTool2.exe则是MFGtool工具的可执行程序文件，在Windows系统下可以双击运行，在运行后就可以进行烧录操作（前提是将配置文件配置完成）。
+除此之外还有配置文件也是非常重要的，如cfg.ini、UICfg.ini以
+及ucl2.xml（该文
+件位于Profiles\Linux\OS Firmware目录下，此处就不再截图说明）。
+
+MfgTool2.exe则是MFGtool工具的可执行程序文件，在Windows系统下可
+以双击运行，在运行后就可以进行烧录操作（前提是将配置文件配置完成）。
 
 Document文件夹中存放了与该工具相关的文档。
 
-Driver目录为Windows 32位和64位操作系统的驱动，驱动一般都不会出现问题，也就无需理会。
+Driver目录为Windows 32位和64位操作系统的驱动，驱动一般
+都不会出现问题，也就无需理会。
 
-More_scripts目录主要存放一些脚本文件，如果只是单纯使用MFGtool工具也无需修这些脚本文件，此处暂时无需理会。
+More_scripts目录主要存放一些脚本文件，如果只是单纯使用MFGtool工具
+也无需修这些脚本文件，此处暂时无需理会。
 
 对于MFGtool工具目录下的其他文件以及文件夹，就暂时无需理会。
 
 MFGtool工具的工作原理
 ~~~~~~~~~~~~~~
 
-简单来说MFGtool工具的烧录步骤分为两个阶段：BurnStarp和Updater。第一阶段是烧录前的准备工作，配置设备USB的vid和pid，来选择烧录的设备。第二阶段是MFGtools开始烧录到结束烧录的过程，这个阶段的烧录过程是严格根据ucl2.xml文件来处理的，实际上是将bootload
-er加载到ram，然后在运行时将编译好的文件系统和镜像文件烧录到开发板上，烧录的位置由用户指定，可以是sd card、nand flash，emmc等。
+简单来说MFGtool工具的烧录步骤分为两个阶段：BurnStarp和Updater。第一阶段是
+烧录前的准备工作，配置设备USB的vid和pid，来选择烧录的设备。第二阶段是MFGtools开
+始烧录到结束烧录的过程，这个阶段的烧录过程是严格根据ucl2.xml文件来处理的，实际上是将bootload
+er加载到ram，然后在运行时将编译好的文件系统和镜像文件烧录到开发板上，烧录的
+位置由用户指定，可以是sd card、nand flash，emmc等。
 
 使用mfg工具直接烧录所有内容
 ~~~~~~~~~~~~~~~
@@ -50,173 +71,190 @@ UICfg.ini文件
 
 UICfg.ini文件是用来配置同时烧录多少个开发板，即配置其多通道的烧录。我们此处并不量产，默认配置为1，具体见
 
-代码清单 28‑1 UICfg.ini文件内容
 
-1 [UICfg]
 
-2 PortMgrDlg=1
+.. code-block:: c
+   :caption: UICfg.ini文件内容
+   :linenos:
+
+   [UICfg]
+   PortMgrDlg=1
 
 cfg.ini文件
 ^^^^^^^^^
 
-cfg.ini文件主要是用来配置目标芯片类型和板子信息及存储器的方式等内容的，其主要文件内容包括四部分内容，分别是profiles、platform、list、variable。
+cfg.ini文件主要是用来配置目标芯片类型和板子信息及存储器的方式等内容的，其主要文件内容
+包括四部分内容，分别是profiles、platform、list、variable。
 
 profiles
 ''''''''
 
-[profiles]
+.. code-block:: sh
+   :linenos:
 
-chip = Linux
+   [profiles]
+   chip = Linux
 
 表示要使用Profiles目录下哪个文件夹的内容进行烧录。
 
-如以上配置使用“/profiles/Linux/OS Firmware/ucl2.xml”目录下的ucl2.xml配置烧录。
+如以上配置使用"/profiles/Linux/OS Firmware/ucl2.xml"目录
+下的ucl2.xml配置烧录。
 
 platform
 ''''''''
 
-[platform]
+.. code-block:: sh
+   :linenos:
 
-board = embedfire_board
+   [platform]
+   board = embedfire_board
 
 开发板名字，目前没有作用，可以忽略
 
 list
 ''''
 
-[list]
-
-name = NAND Flash
-
-表示使用“/profiles/CHIP_PROFILE/OS Firmware/ucl2.xml”文件中的哪个list配置进行烧录，如将name 设置为 NAND Flash，则使用 ucl2.xml文件中NAND
-Flash一栏的配置进行烧录（ucl2.xml文件内容在后续讲解，此处只简单列出部分配置）。
+.. code-block:: sh
+   :linenos:
 
-<LIST name="SDCard"
+   [list]
+   name = NAND Flash
 
-….
+表示使用"/profiles/CHIP_PROFILE/OS Firmware/ucl2.xml"文件中
+的哪个list配置进行烧录，如将name 设置为 NAND Flash，则使用 ucl2.xml文
+件中NAND
+Flash一栏的配置进行烧录（ucl2.xml文件内容在后续讲解，此处只
+简单列出部分配置）。
 
-<LIST name="eMMC"
+.. code-block:: sh
+   :linenos:
 
-….
-
-<LIST name="NAND Flash"
-
-….
+   <LIST name="SDCard"
+   ….
+   <LIST name="eMMC"
+   ….
+   <LIST name="NAND Flash"
+   ….
 
 variable
 ''''''''
 
-variable中是一些环境变量，在list列表配置中会引用的环境变量，如initramfs=fsl-image-mfgtool-initramfs-imx_mfgtools.cpio.gz.u-boot，在“/profiles/CHIP_PROFILE/OS
-Firmware/ucl2.xml”文件中会被<CMD state="BootStrap" type="load" file="firmware/%initramfs%"
-address="0x83800000"…引用，其引用的方式为“%...%”，在两个百分号（%）之间，通过变量initramfs进行传递。
-
-[variable]
-
-board = sabresd
-
-mmc = 1
-
-sxuboot=sabresd
-
-sxdtb=sdb
-
-7duboot=sabresd
-
-7ddtb=sdb
-
-6uluboot=14x14evk
-
-6uldtb=14x14-evk
-
-ldo=
-
-plus=
-
-lite=l
-
-initramfs=fsl-image-mfgtool-initramfs-imx_mfgtools.cpio.gz.u-boot
-
-nand=nand
-
-nanddtb=gpmi-weim
-
-part_uboot=0
-
-part_kernel=1
-
-part_dtb=2
-
-part_rootfs=3
+variable中是一些环境变量，在list列表配置中会引用的环境
+变量，如initramfs=fsl-image-mfgtool-initramfs-imx_mfgtools.cpio.gz.u-boot，在"/profiles/CHIP_PROFILE/OS
+Firmware/ucl2.xml"文件中会被<CMD state="BootStrap" type="load" file="firmware/%initramfs%"
+address="0x83800000"…引用，其引用的方式为"%...%"，在两
+个百分号（%）之间，通过变量initramfs进行传递。
+
+.. code-block:: sh
+   :linenos:
+
+   [variable]
+   board = sabresd
+   mmc = 1
+   sxuboot=sabresd
+   sxdtb=sdb
+   7duboot=sabresd
+   7ddtb=sdb
+   6uluboot=14x14evk
+   6uldtb=14x14-evk
+   ldo=
+   plus=
+   lite=l
+   initramfs=fsl-image-mfgtool-initramfs-imx_mfgtools.cpio.gz.u-boot
+   nand=nand
+   nanddtb=gpmi-weim
+   part_uboot=0
+   part_kernel=1
+   part_dtb=2
+   part_rootfs=3
 
 ucl2.xml文件
 ^^^^^^^^^^
 
 首先我们看一下ucl2.xml文件中的文件内容（已删减）：
 
-<UCL>
-
-<CFG>
-
-<STATE name="BootStrap" dev="MX6ULL" vid="15A2" pid="0080"/>
-
-<STATE name="Updater" dev="MSC" vid="066F" pid="37FF"/>
-
-</CFG>
-
-<LIST name="NAND Flash" desc="Choose NAND as media">
-
-<CMD state="BootStrap" type="load" file="firmware/%initramfs%" address="0x83800000"loadSection="OTH" setSection="OTH" asFlashHeader="FALSE"
-ifdev="MX6SL MX6SX MX7D MX6UL MX6ULL">Loading Initramfs.</CMD>
-
-<CMD state="BootStrap" type="jump" > Jumping to OS image.
-</CMD>
-
-<CMD state="Updater" type="push" body="send" file="files1/zImage"> Sending kernel zImage</CMD>
-
-<CMD state="Updater" type="push" body="$ ubiformat /dev/mtd%part_rootfs%"/>
-
-<CMD state="Updater" type="push" body="$ ubimkvol /dev/ubi0 -Nrootfs -m"/>
-
-<CMD state="Updater" type="push" body="$ mkdir -p /mnt/mtd%part_rootfs%"/>
-
-<CMD state="Updater" type="push" body="frf">Finishing rootfs write</CMD>
-
-<CMD state="Updater" type="push" body="$ echo Update Complete!">Done</CMD>
-
-</LIST>
-
-</UCL>
-
-整个文件由三部分组成，首先看最外层标签<UCL> <UCL/>，它表示更新命令列表（Update Command List，UCL），会被MFGtool工具中的脚本解析，所有的配置都包含在该标签之下。
-
-在文件的开始会有 <CFG> </CFG>标签，它是MFGtool工具的一些全局配置，如在第一阶段（BootStrap）设备枚举，dev的值可以为MX6SL、MX6D、MX6Q、MX6SX、MX6UL、MX6ULL、MX7D其中的一个或多个（因为MFGtool工具可以同时烧录多个开发板），如果USB
-的vid为15A2，pid为0080，那么MFGtool工具会将dev识别为MX6ULL，这USB中的vid与pid是由芯片本身决定的，当dev为MX6ULL时，在后续的烧录任务中会通过ifdev
-MX6ULL进行选择执行哪些语句，然后将name设置为BootStrap，标识当前处于第一阶段，不同的阶段执行的处理是不一样的。这个阶段简单来说就是将开发板的USB OTG接口连接电脑，并且被MFGtool工具识别，才能有接下来的烧录操作。
+.. code-block:: sh
+   :linenos:
+
+   <UCL>
+   
+   <CFG>
+   
+   <STATE name="BootStrap" dev="MX6ULL" vid="15A2" pid="0080"/>
+   
+   <STATE name="Updater" dev="MSC" vid="066F" pid="37FF"/>
+   
+   </CFG>
+   
+   <LIST name="NAND Flash" desc="Choose NAND as media">
+   
+   <CMD state="BootStrap" type="load" file="firmware/%initramfs%" address="0x83800000"loadSection="OTH" setSection="OTH" asFlashHeader="FALSE"
+   ifdev="MX6SL MX6SX MX7D MX6UL MX6ULL">Loading Initramfs.</CMD>
+   
+   <CMD state="BootStrap" type="jump" > Jumping to OS image.
+   </CMD>
+   
+   <CMD state="Updater" type="push" body="send" file="files1/zImage"> Sending kernel zImage</CMD>
+   
+   <CMD state="Updater" type="push" body="$ ubiformat /dev/mtd%part_rootfs%"/>
+   
+   <CMD state="Updater" type="push" body="$ ubimkvol /dev/ubi0 -Nrootfs -m"/>
+   
+   <CMD state="Updater" type="push" body="$ mkdir -p /mnt/mtd%part_rootfs%"/>
+   
+   <CMD state="Updater" type="push" body="frf">Finishing rootfs write</CMD>
+   
+   <CMD state="Updater" type="push" body="$ echo Update Complete!">Done</CMD>
+   
+   </LIST>
+   
+   </UCL>
+
+整个文件由三部分组成，首先看最外层标签<UCL> <UCL/>，它表示更新
+命令列表（Update Command List，UCL），会被MFGtool工具中的脚本解析，所有的配置都包含在该标签之下。
+
+在文件的开始会有 <CFG> </CFG>标签，它是MFGtool工具的一些全局
+配置，如在第一阶段（BootStrap）设备枚举，dev的值可以
+为MX6SL、MX6D、MX6Q、MX6SX、MX6UL、MX6ULL、MX7D其中的一个或
+多个（因为MFGtool工具可以同时烧录多个开发板），如果USB
+的vid为15A2，pid为0080，那么MFGtool工具会将dev识别为MX6ULL，这USB中
+的vid与pid是由芯片本身决定的，当dev为MX6ULL时，在后续的烧录任务中会通过ifdev
+MX6ULL进行选择执行哪些语句，然后将name设置为BootStrap，标识当前处于第
+一阶段，不同的阶段执行的处理是不一样的。这个阶段简单来说就是将开发板的USB OTG接口
+连接电脑，并且被MFGtool工具识别，才能有接下来的烧录操作。
 
 如果USB中的vid为066F，pid为37FF，则表示进入第二阶段，将dev标识为MSG，而name则被设置为Updater。
 
 简单来说，烧录分为两个阶段，BurnStarp和Updater，通过全局配置设备的vid和pid，来选择操作的设备（开发板）。
 
-接下来，可以看到该文件内有多个< LIST > </LIST>标签，这就是前面说的列表配置，list后面有name、desc等参数，name则表示选择cfg.ini文件中的list内容中的配置，可以为SDCard、eMMC、NAND
-Flash等。而desc参数用来说明目的，选择烧录的位置，如Choose SD Cardas media、Choose eMMC as media、Choose NAND as media等。
+接下来，可以看到该文件内有多个< LIST > </LIST>标签，这就是前面说的
+列表配置，list后面有name、desc等参数，name则表示选择cfg.ini文件中
+的list内容中的配置，可以为SDCard、eMMC、NAND
+Flash等。而desc参数用来说明目的，选择烧录
+的位置，如Choose SD Cardas media、Choose eMMC as media、Choose NAND as media等。
 
-在< LIST > </LIST>标签下有多个<CMD> </CMD>标签，这是命令标签，在不同的阶段命令是不一样的，MFGtool工具的命令分为主机特定命令（Host Specific Commands）与固件特定命令（Firmware Specific
-Commands），其中主机特定命令是由MFGtool工具解析和执行，而固件特定命令由目标设备上的固件运行解析和执行。
+在< LIST > </LIST>标签下有多个<CMD> </CMD>标签，这是命令标签，在不同的
+阶段命令是不一样的，MFGtool工具的命令分为主机特定命令（Host Specific Commands）与固
+件特定命令（Firmware Specific
+Commands），其中主机特定命令是由MFGtool工具解析和执行，而固件特定命令由
+目标设备上的固件运行解析和执行。
 
-命令标签下有多个熟悉，如state用于表示该命令在哪个阶段被执行，type表示执行命令的类型，body表示命令的参数，flie则是其他参数，如需要烧录哪个文件，最后的Loading Kernel、Loading U-boot则是命令描述。
+命令标签下有多个熟悉，如state用于表示该命令在哪个阶段被执行，type表示执行
+命令的类型，body表示命令的参数，flie则是其他参数，如需要烧录哪个文件，最后
+的Loading Kernel、Loading U-boot则是命令描述。
 
 主机特定命令（Host Specific Commands）的命令类型有多种，其他参数也有多种，具体见
 
-表格 28‑1（空余处表示无参数）。
+下表（空余处表示无参数）。
 
-表格 28‑1主机特定命令说明
+表   主机特定命令说明
 
 ======== ======== ============== =================================================================================================
 命令类型 命令参数 其他参数       说明
 ======== ======== ============== =================================================================================================
 load              file           烧录的镜像文件的路径和文件名
 \                 Address        镜像存放的RAM地址
-\                 loadSection    ROM代码使用的参数，应设置为“OTH”
+\                 loadSection    ROM代码使用的参数，应设置为"OTH"
 \                 setSection     设置为OTH，如果还有其他镜像，设置为APP
 \                 HasFlashHeader 镜像如果包含flash header，设为TRUE，否则设置为FALSE
 \                 CodeOffset     第一次执行的指令的地址偏移量。注意：该命令仅适用于除i.MX50 HID模式设备之外的Bulk-IO模式i.MX设备。
@@ -227,10 +265,12 @@ boot     保留     flie           加载映像到RAM
 
 固件特定命令（Firmware Specific Commands）的命令类型有多种，其他参数也有多种，具体见
 
-（固件特定命令已删减，且空余处表示无参数）。如果命令被命名为“push”即type="push"，这意味着命令由目标设备而不是主机解析和执行，主机唯一要做的就是将命令发送到目标设备，通过body进行发送命令。表格
-28‑2（固件特定命令已删减，且空余处表示无参数）。如果命令被命名为“push”即type="push"，这意味着命令由目标设备而不是主机解析和执行，主机唯一要做的就是将命令发送到目标设备，通过body进行发送命令。
+（固件特定命令已删减，且空余处表示无参数）。如果命令被命名为"push"即type="push"，这意味着
+命令由目标设备而不是主机解析和执行，主机唯一要做的就是将命令发送到目标设备，通过body进行发
+送命令。（固件特定命令已删减，且空余处表示无参数）。如果命令被命名为"push"即type="push"，这意
+味着命令由目标设备而不是主机解析和执行，主机唯一要做的就是将命令发送到目标设备，通过body进行发送命令。
 
-表格 28‑2固件特定命令说明
+表  固件特定命令说明
 
 ======== ======= ===========================================================================
 命令     参数    说明
@@ -243,7 +283,7 @@ ffs              对SD卡进行分区并将引导流闪存到它
 read     string  读取参数指定的文件并将其发送给主机。如果没有这样的文件，将返回相应的状态
 send             从主机接收文件
 selftest         进行自我诊断， 返回通过或适当状态。在当前版本中未实现
-save     string  将命令“send”接收的文件保存到指定为参数的文件中。
+save     string  将命令"send"接收的文件保存到指定为参数的文件中。
 pipe     string  执行shell命令并从管道的输入端读取数据。 MFGtool工具会将文件发送到管道输出端
 wff              准备将固件写入flash
 wfs              准备将固件写入SD Card
@@ -253,44 +293,58 @@ ffs              将固件写入SD Card
 MFGtool工具的烧录文件
 ^^^^^^^^^^^^^^
 
-MFGtool烧录分为两个阶段，第一部分就是将firmware文件夹下的Uboot、Kernel、device tree、Initramfs加载到内存中，然后在第二阶段，将你要烧录的文件夹下的Uboot、Kernel、device tree、rootfs写入NAND Flash、SD
+MFGtool烧录分为两个阶段，第一部分就是将firmware文件夹
+下的Uboot、Kernel、device tree、Initramfs加载到内存中，然后在第二阶段，将你要烧录的文件夹下的Uboot、Kernel、device tree、rootfs写入NAND Flash、SD
 Card或者emmc，然后完成烧录。
 
 野火开发板第1阶段烧录的文件（以烧录到nand为例）：
 
-Uboot：u-boot-imx6ull14x14evk_nand.imx
+.. code-block:: sh
+   :linenos:
+
+   Uboot：u-boot-imx6ull14x14evk_nand.imx
+   Kernel：zImage
+   device tree：zImage-imx6ull-14x14-evk-gpmi-weim.dtb
+   Initramfs：fsl-image-mfgtool-initramfs-imx_mfgtools.cpio.gz.u-boot
 
-Kernel：zImage
+野火开发板第2阶段烧录的文件以烧录到nand为例）：
 
-device tree：zImage-imx6ull-14x14-evk-gpmi-weim.dtb
+.. code-block:: sh
+   :linenos:
 
-Initramfs：fsl-image-mfgtool-initramfs-imx_mfgtools.cpio.gz.u-boot
+   Uboot：u-boot-emmc-2016.03-r0.imx
+   Kernel：zImage
+   device tree：zImage-imx6ull-14x14-evk-emmc-50-70-dht11-leds.dtb
+   rootfs：my_qt_core_fs.tar.bz2
 
-野火开发板第2阶段烧录的文件以烧录到nand为例）：
+烧录测试
+^^^^
 
-Uboot：u-boot-emmc-2016.03-r0.imx
+本次使用野火imx6ull开发板进行烧录测试，固件使用我们配套的固件即可，首先
+将表 11‑1中开发板启动方式的MODE0配置为1，MODE1配置为0，将开发板的USB OTG与
+电脑相接；然后双击打开MfgTool2.exe烧录工具，如果出现"符合 HID
+标准的供应商定义设备"则表示识别成功，而如果出现"No Device Connected"则表
+示未识别成功，识别成功时其界面如下图所示。
 
-Kernel：zImage
+.. image:: media/mfgtoo003.png
+   :align: center
+   :alt: 未找到图片3|
 
-device tree：zImage-imx6ull-14x14-evk-emmc-50-70-dht11-leds.dtb
 
-rootfs：my_qt_core_fs.tar.bz2
 
-烧录测试
-^^^^
+最后点击"Start"按钮开始烧录到开发板上，而烧录的位置由cfg.Init文件
+指定，本次我们烧录到nand flash 中，在烧录完成后，将开发板启动
+方式的MODE0配置为0，MODE1配置为1，打开xShell终端软件，然后复位开发板即
+可看到系统启动过程，具体见下图。
 
-本次使用野火imx6ull开发板进行烧录测试，固件使用我们配套的固件即可，首先将表 11‑1中开发板启动方式的MODE0配置为1，MODE1配置为0，将开发板的USB OTG与电脑相接；然后双击打开MfgTool2.exe烧录工具，如果出现“符合 HID
-标准的供应商定义设备”则表示识别成功，而如果出现“No Device Connected”则表示未识别成功，识别成功时其界面如图 28‑2所示。
+.. image:: media/mfgtoo004.png
+   :align: center
+   :alt: 未找到图片4|
 
-|mfgtoo003|
 
-图 28‑2 MFGtool工具界面
 
-最后点击“Start”按钮开始烧录到开发板上，而烧录的位置由cfg.Init文件指定，本次我们烧录到nand flash 中，在烧录完成后，将开发板启动方式的MODE0配置为0，MODE1配置为1，打开xShell终端软件，然后复位开发板即可看到系统启动过程，具体见图 28‑3。
 
-|mfgtoo004|
 
-图 28‑3系统启动过程
 
 .. |mfgtoo002| image:: media/mfgtoo002.png
    :width: 1.87222in
diff --git a/documentation/install_image/sdcard_production.rst b/documentation/install_image/sdcard_production.rst
index c8ce5170deccec81225d1fd5720c504bdfb166f7..987d5e04d855d1351e7971e5ab8bde83118d0a57 100644
--- a/documentation/install_image/sdcard_production.rst
+++ b/documentation/install_image/sdcard_production.rst
@@ -10,13 +10,18 @@
 SD卡创建分区
 ~~~~~~~
 
-和前面的原理类似，即先将一个媒介镜像烧写到SD卡上，系统在SD卡启动后，再将保存在SD卡的系统烧写到NAND Flash或emmc中，然后再将系统配置为从NAND启动，从而更新系统。
+和前面的原理类似，即先将一个媒介镜像烧写到SD卡上，系统在SD卡启动后，再将保
+存在SD卡的系统烧写到NAND Flash或emmc中，然后再将系统配置为从NAND启动，从
+而更新系统。
 
 提示：整个实验使用野火提供的资料源码与镜像即可。
 
-首先需要准备一张SD卡与一个读卡器，开发环境为ubuntu14.04虚拟机，使用读卡器将SD卡连接到电脑USB中，然后在虚拟机中将SD卡格式化，再将系统文件拷贝到SD卡中，具体操作如下。
+首先需要准备一张SD卡与一个读卡器，开发环境为ubuntu14.04虚拟机，使用读
+卡器将SD卡连接到电脑USB中，然后在虚拟机中将SD卡格式化，再将系统文件拷贝
+到SD卡中，具体操作如下。
 
-首先通过sudo fdisk /dev/sdb命令对SD卡进行分区，然后通过对应的命令对SD卡进行操作，如p：打印分区表，d：删除分区，n：添加新分区等等，具体命令如下：
+首先通过sudo fdisk /dev/sdb命令对SD卡进行分区，然后通过对应的命令对SD卡
+进行操作，如p：打印分区表，d：删除分区，n：添加新分区等等，具体命令如下：
 
 提示：fdisk命令产生的更改将停留在内存中，直到您决定将更改写入磁盘。
 
@@ -90,7 +95,7 @@ p 打印分区表
 
 输出：
 
-Disk /dev/sdb：7.5 GiB，8053063680 字节，15728640 个扇区单元：扇区 / 1 \* 512 = 512 字节扇区大小(逻辑/物理)：512 字节 / 512 字节I/O 大小(最小/最佳)：512 字节 / 512
+Disk /dev/sdb：7.5 GiB，8053063680 字节，15728640 个扇区单元：扇区 / 1 * 512 = 512 字节扇区大小(逻辑/物理)：512 字节 / 512 字节I/O 大小(最小/最佳)：512 字节 / 512
 字节磁盘标签类型：dos磁盘标识符：0x4357e4a3 设备       启动    起点 末尾     扇区  大小 Id 类型/dev/sdb1         20480  1024000  1003521 490M 83 Linux/dev/sdb2       1228800
 15728639 14499840  6.9G 83 Linux
 
@@ -102,7 +107,7 @@ d 删除分区
 
 命令(输入 m 获取帮助)： d分区号 (1,2, 默认 2): 分区 2 已删除。命令(输入 m 获取帮助)： d已选择分区 1分区 1 已删除。
 
-命令(输入 m 获取帮助)： pDisk /dev/sdb：7.5 GiB，8053063680 字节，15728640 个扇区单元：扇区 / 1 \* 512 = 512 字节扇区大小(逻辑/物理)：512 字节 / 512 字节I/O 大小(最小/最佳)：512 字节 / 512
+命令(输入 m 获取帮助)： pDisk /dev/sdb：7.5 GiB，8053063680 字节，15728640 个扇区单元：扇区 / 1 * 512 = 512 字节扇区大小(逻辑/物理)：512 字节 / 512 字节I/O 大小(最小/最佳)：512 字节 / 512
 字节磁盘标签类型：dos磁盘标识符：0x4357e4a3
 
 SD卡制作新分区，且需要制作两个分区，一个是SD卡烧录本身使用的分区，剩下的SD卡容量作为第二个分区（暂时未使用到），可以输入n命令操作，输入n命令后还需要根据提示输入创建的分区类型、分区号（使用默认值即可）以及分区的大小，我们在输入n命令之后再输入p命令（创建主分区），然后输入分区的大小（分区起始
@@ -113,12 +118,12 @@ n 添加新分区
 输出：
 
 命令(输入 m 获取帮助)： n分区类型 p 主分区 (0个主分区，0个扩展分区，4空闲) e 扩展分区 (逻辑分区容器)选择 (默认 p)： p分区号 (1-4, 默认 1): 1第一个扇区 (2048-15728639, 默认 2048): 20480上个扇区，+sectors 或
-+size{K,M,G,T,P} (20480-15728639, 默认 15728639): 1024000创建了一个新分区 1，类型为“Linux”，大小为 490 MiB。
++size{K,M,G,T,P} (20480-15728639, 默认 15728639): 1024000创建了一个新分区 1，类型为"Linux"，大小为 490 MiB。
 
 # 创建第二个分区
 
 命令(输入 m 获取帮助)： n分区类型 p 主分区 (1个主分区，0个扩展分区，3空闲) e 扩展分区 (逻辑分区容器)选择 (默认 p)： p分区号 (2-4, 默认 2): 2第一个扇区 (2048-15728639, 默认 2048): 1228800上个扇区，+sectors 或
-+size{K,M,G,T,P} (1228800-15728639, 默认 15728639): （默认）创建了一个新分区 2，类型为“Linux”，大小为 6.9 GiB。
++size{K,M,G,T,P} (1228800-15728639, 默认 15728639): （默认）创建了一个新分区 2，类型为"Linux"，大小为 6.9 GiB。
 
 在结束后，我们输入p命令查看一下SD卡当前分区情况，确认无误后，就输入w进行同步保存到SD卡中，因为目前的这些更改是暂时存储在内存上的，只有通过w命令保存后才能保存到SD卡中。
 
@@ -126,7 +131,7 @@ p 打印分区表
 
 输出：
 
-命令(输入 m 获取帮助)： pDisk /dev/sdb：7.5 GiB，8053063680 字节，15728640 个扇区单元：扇区 / 1 \* 512 = 512 字节扇区大小(逻辑/物理)：512 字节 / 512 字节I/O 大小(最小/最佳)：512 字节 / 512
+命令(输入 m 获取帮助)： pDisk /dev/sdb：7.5 GiB，8053063680 字节，15728640 个扇区单元：扇区 / 1 * 512 = 512 字节扇区大小(逻辑/物理)：512 字节 / 512 字节I/O 大小(最小/最佳)：512 字节 / 512
 字节磁盘标签类型：dos磁盘标识符：0x4357e4a3设备 启动 起点 末尾 扇区 大小 Id 类型/dev/sdb1 20480 1024000 1003521 490M 83 Linux/dev/sdb2 1228800 15728639 14499840 6.9G 83 Linux
 
 w 将分区表写入磁盘并退出
@@ -139,7 +144,12 @@ w 将分区表写入磁盘并退出
 
 uuu uboot.imx
 
-命令：ls /dev/ \| grep sdb
+命令：
+
+.. code-block:: sh
+   :linenos:
+
+   ls /dev/ \| grep sdb
 
 输出：
 
@@ -150,14 +160,21 @@ sdbsdb1sdb2
 
 首先将野火提供的SD卡启动的资料包放入虚拟机，放入的目录可以随意选择，如我是直接放到家目录下，u-boot/sd_update/root存在以下内容：
 
-embedfire@ embedfire:~/u-boot/sd_update/root$ lsmfg-images-emmc update_nand_boot.scrmfg-images-nand zImagerelease.txt zImage-imx6ull-14x14-evk-emmc-
-update.dtbrootfs.cpio.gz zImage-imx6ull-14x14-evk-gpmi-weim-update.dtbu-boot-sd-2016.03-r0.imx update_emmc_boot.scr
+.. code-block:: sh
+   :linenos:
+
+
+   embedfire@ embedfire:~/u-boot/sd_update/root$ lsmfg-images-emmc update_nand_boot.scrmfg-images-nand zImagerelease.txt zImage-imx6ull-14x14-evk-emmc-
+   update.dtbrootfs.cpio.gz zImage-imx6ull-14x14-evk-gpmi-weim-update.dtbu-boot-sd-2016.03-r0.imx update_emmc_boot.scr
 
 u-boot-sd-2016.03-r0.imx是我们需要烧写到SD卡的Uboot，我们可以使用以下命令将进行烧录：
 
 输入命令：
 
-sudo dd if=~/u-boot/sd_update/root/u-boot-sd-2016.03-r0.imx of=/dev/sdb bs=512 seek=2 conv=fsync
+.. code-block:: sh
+   :linenos:
+
+   sudo dd if=~/u-boot/sd_update/root/u-boot-sd-2016.03-r0.imx of=/dev/sdb bs=512 seek=2 conv=fsync
 
 输出：
 
@@ -170,25 +187,52 @@ sudo dd if=~/u-boot/sd_update/root/u-boot-sd-2016.03-r0.imx of=/dev/sdb bs=512 s
 
 因为是从SD卡烧录到NAND Flash或者emmc，因此SD卡要保存烧录到NAND Flash或者emmc的文件，首先要将SD卡的分区进行格式化，用于保存这些文件，具体操作过程如下：
 
-输入命令：sudo mkfs.vfat /dev/sdb1
+输入命令：
+
+.. code-block:: sh
+   :linenos:
+
+   sudo mkfs.vfat /dev/sdb1
+
 
 输出：
 
-~$ mkfs.fat 4.1 (2017-01-24)mkfs.vfat: /dev/sdb1 contains a mounted filesystem.
+.. code-block:: sh
+   :linenos:
+
+   ~$ mkfs.fat 4.1 (2017-01-24)mkfs.vfat: /dev/sdb1 contains a mounted filesystem.
+
+输入命令：
+
+.. code-block:: sh
+   :linenos:
+
+   sudo mkfs.ext4 /dev/sdb2
+
+输出：
 
-输入命令：sudo mkfs.ext4 /dev/sdb2
+.. code-block:: sh
+   :linenos:
 
-输出：mke2fs 1.44.1 (24-Mar-2018)
+   mke2fs 1.44.1 (24-Mar-2018)
 
-首先挂载SD卡，本次试验创建一个挂载目录mountpoint，将SD卡挂载到该目录下，然后将野火提供的SD卡启动的资料包中root目录下所有文件拷贝到fat格式分区（即sdb1）目录下，具体操作如下：
+首先挂载SD卡，本次试验创建一个挂载目录mountpoint，将SD卡挂
+载到该目录下，然后将野火提供的SD卡启动的资料包中root目录下所
+有文件拷贝到fat格式分区（即sdb1）目录下，具体操作如下：
 
 挂载SD卡：
 
-mkdir mountpointsudo mount /dev/sdb1 mountpoint/
+.. code-block:: sh
+   :linenos:
+
+   mkdir mountpointsudo mount /dev/sdb1 mountpoint/
 
 拷贝root目录下所有文件到SD卡：
 
-sudo cp -r ~/u-boot/sd_update/root/\* ~/mountpoint/
+.. code-block:: sh
+   :linenos:
+
+   sudo cp -r ~/u-boot/sd_update/root/* ~/mountpoint/
 
 查看拷贝后的内容：ls
 
@@ -200,31 +244,48 @@ update_emmc_boot.scr
 配置SD卡烧录信息
 ~~~~~~~~~
 
-如果需要从SD卡烧录到NAND Flash，则将mfg-images-nand改名为mfg-images；如果需要从SD卡烧录到emmc，则将mfg-images-emmc改名为mfg-images；并且将update_nand_boot.scr改名为boot.scr，mfg-
-images文件夹中的文件相应的替换，并在Manifest中填写欲烧写文件的文件名即可。然后将sd卡插入开发板，将开发板的WiFi的跳帽取下，同时将boot的拨码开关 2/5/8 拨到 ON档，表示从SD卡启动，在SD卡烧写的时候红灯闪烁，烧写完毕，红灯常亮，烧写失败，红灯熄灭。
+如果需要从SD卡烧录到NAND Flash，则将mfg-images-nand改名为mfg-images；如果
+需要从SD卡烧录到emmc，则将mfg-images-emmc改名为mfg-images；并且将update_nand_boot.scr改名为boot.scr，mfg-
+images文件夹中的文件相应的替换，并在Manifest中填写欲烧写文件的文
+件名即可。然后将sd卡插入开发板，将开发板的WiFi的跳帽取下，同时
+将boot的拨码开关 2/5/8 拨到 ON档，表示从SD卡启动，在SD卡烧写的时
+候红灯闪烁，烧写完毕，红灯常亮，烧写失败，红灯熄灭。
 
 修改文件名字可以使用mv命令，具体如下：
 
 进入mountpoint目录：
 
-cd mountpoint/
+.. code-block:: sh
+   :linenos:
+
+   cd mountpoint/
 
 修改mfg-images-nand文件名字为mfg-images：
 
-sudo mv mfg-images-nand/ mfg-images/
+.. code-block:: sh
+   :linenos:
+
+   sudo mv mfg-images-nand/ mfg-images/
 
 修改update_nand_boot.scr文件为boot.scr：
 
-sudo mv update_nand_boot.scr boot.scr
+.. code-block:: sh
+   :linenos:
+
+   sudo mv update_nand_boot.scr boot.scr
 
-在烧录工程可以打开串口终端，查看开发板输出的信息，具体见图 29‑1。
+在烧录工程可以打开串口终端，查看开发板输出的信息，具体见下图。
+
+.. image:: media/sdcard002.png
+   :align: center
+   :alt: 未找到图片
 
-|sdcard002|
 
-图 29‑1 从SD卡烧录
 
 在烧录完成后，将boot的拨码开关 2/3/6 拨到 ON档，就可以从NAND Flash启动了。
 
+
+
 .. |sdcard002| image:: media/sdcard002.png
    :width: 5.12508in
    :height: 5.008in
diff --git a/documentation/linux_app/Makefile_brife.rst b/documentation/linux_app/Makefile_brife.rst
new file mode 100644
index 0000000000000000000000000000000000000000..731636bd698c7318a10aeed820075ba442b7a752
--- /dev/null
+++ b/documentation/linux_app/Makefile_brife.rst
@@ -0,0 +1,110 @@
+.. vim: syntax=rst
+
+Makefile简介
+----------------------------
+
+Makefile是什么
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+回顾一下我们前面几个章节，我们使用到的示例代码只有一个hello.c文件，非常简单，所以直接执行下面的指令进行编译也非常方便。
+
+**编译一个文件**
+
+.. code-block:: sh
+   :linenos:
+
+   gcc hello.c -o hello 
+
+但是随着我们课程逐渐深入，以后在我们的项目工程中，势必会有越来越多的C文件和H头文件。
+当一个工程中有很多C源文件和H头文件时，再直接使用编译器指令就非常麻烦了，光输入文件名都会影响心情，
+比如下面的例子:
+
+**编译多个文件**
+
+.. code-block:: sh
+   :linenos:
+
+   gcc hello.c aaa.c bbb.c -o hello 
+
+
+而且哪怕你只是修改一个文件，也需要重新编译所有的文件，白白浪费了很多开发时间。
+要解决这个问题，最好的方式就是把工程的编译规则写下来，让编译器自动加载该规则进行编译。
+解决方法就是使用make和Makefile，这两个工具是搭配使用的，下面给大家介绍一下:
+
+- **make工具**：它可以帮助我们找出项目里面修改变更过的文件，并根据依赖关系，找出受修改影响的其他相关文件，然后对这些文件按照规则进行单独的编译，这样一来，就能避免重新编译项目的所有的文件。
+
+- **Makefile文件**：上面提到的规则、依赖关系主要是定义在这个Makefile文件中的，我们在其中合理地定义好文件的依赖关系之后，make工具就能精准地进行编译工作。
+
+它们的关系如下图所示:
+
+.. image:: media/make001.png
+   :align: center
+   :alt: 未找到图片
+
+
+从我们上面的介绍，大家可以知道，我们管理一个项目工程，实质上就是管理项目文件间的依赖关系。
+所以我们在学习和使用Makefile的时候，一定要牢牢抓住它这种面向依赖的思想，
+心里一定要谨记，**Makefile中所有的复杂、晦涩的语法都是更好地为解决依赖问题而存在的**。
+理解了它的本质目的之后，我们以后在学习它的过程中就不用死记硬背各种语法了，
+**只要想想这个本质目的，你会觉得一切都是那么地顺理成章**。
+
+是否真正驾驭Makefile的标志，就在于脑海中是否清晰地知道目标和依赖的关系。当你的大脑能够像make工具一样，
+准确无误地解释执行Makefile的时候，就是一个Makefile高手了。我们就是要奔着这个目标去的。
+
+这里再多介绍一下，当工程复杂度再上一个台阶的时候，会觉得手写Makefile也很麻烦，
+那个时候可以用CMake、autotools等工具来帮忙生成Makefile。实际上Windows系统下很多IDE工具内部也是使用类似Makefile的方式组织工程文件的，
+只不过被封装成图形界面，对用户不可见而已。
+
+Makefile概览
+~~~~~~~~~~~~~~~
+
+Makefile对于一个嵌入式Linux开发人员来说，怎么强调它的重要性都不为过。虽然它跟程序员的编程能力并不直接挂钩，
+但是它所体现出来的是一种工程能力，**这种工程能力恰恰就是专业程序员和业余程序员的一个分水岭**。因为在Linux开发环境下，
+我们并没有太多的集成开发环境IDE，也就是说程序的所有控制权全部在于开发者，你势必要对底层软件的编译、链接、
+装载有着相当深入的了解，才能说真正地驾驭了你的程序。虽然前面的章节已经简单介绍了部分底层相关内容，但是还不够深入，
+我们以后的课程还要更加深入。
+
+而且我们以后的课程也会陆续讲解Uboot移植开发、Linux内核移植开发和其他的一些开源项目，倘若我们Makefile基础不够扎实，
+那么很可能怎么着手分析项目都不知道。程序的架构组织都梳理不清楚，就更别谈修改程序功能了。如下图:
+
+.. image:: media/make002.png
+   :align: center
+   :alt: 未找到图片
+
+接下来我们先整体了解Makefile的相关语法，这里要提前跟大家说清楚一点，Makefile经过多年发展，虽然功能非常强大，
+但是也留下了沉重的历史包袱，我们没有办法详细介绍make的每一个详细知识点(也没有必要)，借鉴于以往的开发经验，
+我们总结了80%常用的Makefile知识点，定位在为以后研究Uboot、Linux kernel和其他开源项目打下结实的基础。
+虽然这个目标难度还是比较大的，要学习的知识点也不少，不过我们会通过一系列难度逐步迭代的小实验，
+来帮助大家无痛学会Makefile。
+
+我一直提倡：学习知识之前，要现在脑海中初步建立知识点的整体框架，以此来指导进一步的学习。
+接下来我们先整体看一下要学习Mkaefile的知识点，如下图所示:
+
+.. image:: media/make003.png
+   :align: center
+   :alt: 未找到图片
+
+图里面的知识点不少，我们在这里先不深入学习具体语法，而是告诉大家每一个语法的出现是为了解决什么问题，
+我们从左上角开始讲起:
+
+1、 基础语法-- 描述目标和依赖的特定格式，Makefile的核心。
+
+2、 变量-- 记录特定的信息，避免重复输入原始信息。尤其是手动输入原始信息很长时，特别好用。
+
+3、 分支判断-- 灵活控制多个不同的编译过程，方便兼容不同属性。
+
+4、 头文件依赖-- 监控头文件的变化，头文件也是程序的关键内容。
+
+5、 隐含规则-- 利用Makefile的一些默认规则，可以减少编写Makefile的工作量。
+
+6、 自动化变量-- 利用Makefile的默认的自动化变量，可以减少编写Makefile的工作量。
+
+7、 模式规则-- 灵活使用正则表达式，可以减少编写Makefile的工作量。
+
+8、 函数-- 使用Makefile的各种函数，可以更方便地实现Makefile的功能。
+
+了解完Makefile的知识点，从上面的分析可以知道，Makefile的核心在于基础语法，用来描述目标和依赖的关系。
+其他语法的目的，是为了减少我们编写Makefile工作量，让我们能够以更加优雅、更加简洁、更好维护的方式来实现Makefile的功能。
+这跟我们程序开发是很相似的，不止要实现功能，还要兼顾程序的可读性、拓展性、可维护性等等。
+
+下一章，将会通过小实验来进一步学习Makefile。
\ No newline at end of file
diff --git a/documentation/linux_app/arm_gcc_hello_world.rst b/documentation/linux_app/arm_gcc_hello_world.rst
new file mode 100644
index 0000000000000000000000000000000000000000..42b571731440d3baa9c1193c732f2e91cecbe404
--- /dev/null
+++ b/documentation/linux_app/arm_gcc_hello_world.rst
@@ -0,0 +1,478 @@
+.. vim: syntax=rst
+
+ARM-GCC和开发板的HelloWorld
+-----------------------
+
+为了加深对GCC编译工具链的了解，本章尝试在ARM开发板上运行x86_64平台、Ubuntu系统用各种不同方法编译的HelloWorld。
+
+由于需要在Ubuntu主机及开发板之间共享文件，请按《挂载NFS网络文件系统》章节搭建好NFS网络文件系统环境。
+
+本章的示例代码目录为：base_code/linux_app/hello_crosscompile。
+
+在ARM板上运行x86_64平台的程序
+~~~~~~~~~~~~~~
+
+上一章Ubantu编译生成了X86_64平台的Hello World程序，我们尝试ARM开发板上直接运行它。
+
+在开发板的终端上，切换至主机共享目录下的hello_c文件夹，可以直接执行如下命令测试：
+
+::
+
+         #以下命令在开发板上的终端上执行
+
+         #进入共享的NFS目录，下面的目录根据自己的实际配置情况修改
+
+         cd /mnt/example/hello_c
+
+         #查看是否有存在前面编译生成的文件
+
+         ls
+
+         #执行主机编译的x86架构程序
+
+         ./hello
+
+
+如下图:
+
+.. image:: media/armgcc002.png
+   :align: center
+   :alt: 未找到图片2|
+
+
+如图所示，程序无法正常运行，终端提示ARM开发板在执行x86架构（Intel或AMD）的hello程序时提示格式错误，原因是x86_64和ARM架构的程序不兼容，本质是由于这些CPU使用的指令集不同。这就是为什么需要针对芯片架构定制文件系统、软件工具，apt使用的源也针对不同架构提供不同的软件包。前
+面说Debian系统有支持多种架构的优势，本质上就是说它的文件系统针对不同芯片架构提供了适配的软件包。
+
+当然，对于由Python等跨平台语言编写的源程序，它们不需要编译，只需要使用匹配的解释器即可运行，与芯片架构甚至操作系统无关。
+
+安装并使用交叉编译工具链
+~~~~~~~~~~~~
+
+在前面《GCC和Hello World》章节中，我们编译了两个程序，分别是:
+
+- 编译器运行在X86_64架构平台上，编译生成X86_64架构的可执行程序
+
+- 编译器运行在ARM架构平台上，编译生成ARM架构的可执行程序
+
+这种编译器和目标程序都是相同架构的编译过程，被称为 **本地编译** 。
+
+而当前我们希望的是编译器运行在x86架构平台上，编译生成ARM架构的可执行程序，这种编译器和目标程序运行在不同架构的编译过程，被称为 **交叉编译**。
+
+既然已经有本地编译，为什么需要交叉编译？这是因为通常编译工具链对编译环境有较高的要求，编译复杂的程序时，可能需要巨大的存储空间以及强大的CPU运算能力加快编译速度。常见的ARM
+架构平台资源有限，无论是存储空间还是CPU运算能力，都与X86平台相去甚远，特别是对于MCU平台，安装编译器根本无从谈起。有了交叉编译，我们就可以在PC上快速编译出针对其他架构的可执行程序。
+
+相对的，能进行架构"交叉"编译过程的编译器，就被称为 **交叉编译器（Cross compiler）**。
+交叉编译器听起来是个新概念，但在MCU开发中一直使用的就是交叉编译器，
+例如开发STM32、RT1052所使用的IDE软件Keil（MDK）或IAR，就是在Windows x86架构编译，生成MCU平台的应用程序，最后下载到板子执行。
+
+
+
+使用APT安装ARM-GCC
+^^^^^^^^^^^^^^
+
+安装交叉编译工具链有如下三种方式：
+
+-  直接在Ubuntu下使用APT包管理工具下载安装，操作简单，在本章节我们直接使用该方式安装即可。
+
+-  自行下载第三方制作好的工具链，如Linaro，好处是选择丰富，能找到很多不同的版本。
+
+-  使用crosstool-ng根据需要自己制作，过程复杂，不推荐。
+
+本书中提供的示例程序对编译器版本没什么要求，为简便起见，此处直接在Ubuntu系统下使用APT包管理工具安装。
+
+本书使用的编译器主要有两种类型：
+
+-  arm-linux-gnueabihf-gcc：名称中的Linux表示目标应用程序是运行在Linux操作系统之上的，例如前面的hello.c程序。
+
+-  arm-none-eabi-gcc，名称中的none表示无操作系统，目标应用程序的运行环境是不带操作系统的，例如裸机代码、uboot、内核代码本身。
+
+不过在开发中比较多的开发者对所有程序都直接用arm-linux-gnueabihf-gcc来编译，包括裸机代码和uboot，虽然可能因为代码本身没有调用到Linux相关的内容而不会出错，但这样做不够严谨，条件允许的话，我们还是严格区分开来。
+
+本章节示例代码只需要使用arm-linux-gnueabihf-gcc编译器，可通过APT包管理工具可直接执行以下命令安装：
+
+::
+
+
+         #在主机上执行如下命令
+
+         sudo apt install gcc-arm-linux-gnueabihf
+
+         #安装完成后使用如下命令查看版本
+
+         arm-linux-gnueabihf-gcc –v
+
+可以看到下图的内容，它表明交叉编译工具链安装成功了，输出信息表明了它是7.4.0版本的编译器，其中的 "Target:arm-linux-gnueabihf"也表明了它的目标架构。
+
+.. image:: media/armgcc003.png
+   :align: center
+   :alt: 未找到图片3|
+
+ arm-linux-gnueabi-gcc版本信息
+
+安装完成后输入"arm-linux-gnueabihf-"，再按两下TAB键，终端会提示可用的相关命令，如下图包含了ARM-GCC工具链Binutils的各种工具。
+
+.. image:: media/armgcc004.png
+   :align: center
+   :alt: 未找到图片4|
+
+安装后包含的Binutils工具集
+
+交叉编译Hello World程序
+^^^^^^^^^^^^^^^^^
+
+安装好交叉编译器后，直接使用它对Hello World程序进行交叉编译即可。
+
+交叉编译器与本地编译器使用起来并没有多大区别。对于源文件的编译过程，都是四个阶段：预处理，编译，汇编以及链接，区别只在于编译工具。因此，我们可以依葫芦画瓢，修改一下前面GCC编译章节的命令，就可以完成这个过程。
+
+在主机上执行如下命令对Hello World程序进行交叉编译：
+
+::
+
+
+         #以下命令在主机上运行
+
+         #在hello.c程序所在的目录执行如下命令
+
+         arm-linux-gnueabihf-gcc hello.c –o hello
+
+同样的C代码文件，使用交叉编译器编译后，生成的hello已经变成了ARM平台的可执行文件，可以通过readelf工具来查看具体的程序信息。
+
+readelf工具在系统安装GCC编译工具链时一起被安装了，我们可以直接使用。在主机上执行以下命令：
+
+::
+
+
+         #以下命令在主机上运行
+
+         readelf -a hello
+
+.. image:: media/armgcc005.png
+   :align: center
+   :alt: 未找到图片5|
+
+使有readelf查看交叉编译器生成的hello程序
+
+可看到hello程序的系统架构为ARM平台，标志中表明了它是hard-float类型的EABI接口。
+
+编译好后，即可尝试在开发板上运行，在开发板的终端执行以下命令，执行结果如下图所示。
+
+::
+
+
+         #以下命令在开发板上的终端上执行
+
+         #切换至共享的NFS目录，下面的目录根据自己的配置修改
+
+         cd /mnt/example/hello_c
+
+         #查看是否有存在前面编译生成的文件
+
+         ls
+
+         #执行主机编译的ARM平台程序
+
+         ./hello
+
+.. image:: media/armgcc006.png
+   :align: center
+   :alt: 未找到图片6|
+
+
+如何选择编译器
+~~~~~~~
+
+除了我们安装的arm-linux-gnueabihf-gcc外，编译器还有很多版本，如arm-linux-gnueabi-gcc，《GCC和Hello World》章节中使用的本地编译器gcc全名为x86_64-linux-gnu-gcc。
+
+目前大部分ARM开发者使用的都是由Linaro组织提供的交叉编译器，包括前面使用APT安装的ARM-GCC工具链，它的来源也是Linaro。Linaro是由ARM发起，与其它ARM SOC公司共同投资的非盈利组织。我们可以在它官网的如下地址找到它提供的ARM交叉编译器：\
+https://releases.linaro.org/components/toolchain/binaries/ ，如下图所示，在它提供的编译器列表中首先选择版本号，然后可选择ARM架构类型，最后是具体的编译器平台。
+
+.. image:: media/armgcc007.jpg
+   :align: center
+   :alt: 未找到图片7|
+
+
+编译器的命名没有严格的规则，但它们的名字中一般包含我们最关心的内容，可根据它们的名字选择要使用的编译器：
+
+arch [-os] [-(gnu)eabi(hf)] -gcc
+
+其中的各字段如下表所示。
+
+ GCC编译器命名格式
+
+==== ==============
+字段 含义
+==== ==============
+arch 目标芯片架构
+os   操作系统
+gnu  C标准库类型
+eabi 应用二进制接口
+hf   浮点模式
+==== ==============
+
+以我们安装的arm-linux-gnueabihf-gcc编译器为例，表示它的目标芯片架构为ARM，目标操作系统为Linux，使用GNU的C标准库即glibc，使用嵌入式应用二进制接口（eabi），编译器的浮点模式为硬浮点hard-float。而另一种名为arm-linux-gnueabi-
+gcc的编译器与它的差别就在于是否带"hf"，不带"hf"表示它使用soft-float模式。
+
+关于编译器的各个字段详细说明如下：
+
+目标芯片架构
+^^^^^^^^^^^^^
+
+目标芯片架构就是指交叉编译器生成的程序运行的平台，如ARM、MIPS，其中ARM交叉编译器又分为ARMv7、ARMv8及aarch64架构。本书使用的i.MX 6ULL的内核为Cortex-A7，它使用的是ARMv7架构。
+arm-linux-gnueabihf-gcc直接以arm表示ARMv7架构。
+
+大小端
+^^^^^^^^
+
+指目标芯片的大小端模式，i.MX 6ULL使用的是小端模式。若是大端模式（big edian），编译器名字中会带"be"或"eb"字段进行标标注。
+
+目标操作系统
+^^^^^^^^^^^^^^^
+
+目标操作系统表示编译后的程序运行的系统，主要有Linux或bare-metal（无操作系统）两种，arm-linux-gnueabi-gcc 表示它目标程序的运行环境为Linux系统，程序可以使用Linux下的C标准库或Linux内核提供的API，如fork等进程函数。而arm-
+eabi-gcc或arm-none-eabi-gcc表示它们的目标程序运行在无操作系统的环境中。
+
+所以严格来说，我们编译Linux应用程序时应该使用带"linux"的编译器，而编译uboot、裸机程序时，应该使用"bare-metal"类型的裸机编译器，但很多开发者常常把它们混用也没有出现问题，这一般是因为开发者编写的裸机程序本身就没有使用到Linux系统提供的API，所以才不会出错。
+
+C标准库类型
+^^^^^^^^^^^^^^
+
+C标准库类型通常有gnu、uclibc等，分别表示GNU的glibc库和uclibc库，这取决于目标操作系统提供的C库类型，不过由于glibc和uclibc库是兼容的，所以开发者在编通常直接使用GNU类型的编译器而不管目标系统中的C库类型。
+除了裸机编译器不带C库之外，其它编译器的C库类型都是glibc库的，如arm-linux-gnueabihf-gcc。
+
+应用二进制接口
+^^^^^^^^^^^^^^^
+
+应用二进制接口（Application Binary Interface），描述了应用程序和操作系统之间或其他应用程序的低级接口。在编译器选项中主要有"abi"和"eabi"两种类型，abi通常用在x86架构上，而eabi表示embed abi，即嵌入式架构，如ARM、MIPS等。
+
+浮点模式
+^^^^^^^^^^^
+
+部分ARM处理器带浮点运算单元，代码需要进行浮点运算时若交给fpu处理，可以加快运算速度。编译器针对浮点运算的不同处理情况提供了以下几种模式：
+
+- hard： 硬浮点类型（hard-float），采用fpu参与浮点运算。 arm-linux-gnueabihf-gcc、armeb-linux-gnueabihf-gcc都是硬浮点类型，即名字中带"hf"。
+
+- soft：软浮点类型（soft-float），即使有fpu浮点运算单元也不用，而是使用软件模式，arm-linux-gnueabi-gcc、armeb-linux-gnueabi-gcc都是软浮点类型，即名字中不带"hf"。
+
+- softfp：允许使用浮点指令，但保持与软浮点ABI的兼容性。
+
+i.MX6ULL带有fpu，对于soft-float和hard-float模式都支持，不过本开发板中提供Linux文件系统中的库都是使用hard模式编译的，所以编写应用程序时也需要使用相同类型的编译器，否则会应用程序运行时会提示找不到库文件。
+
+编译器版本号
+^^^^^^^^^^^
+
+通常来说高版本的编译器是向后兼容的，但开发特定程序时会使用固定的某个版本编译器，所以程序可能会依赖该版本的编译器，根据自己要编译的程序的要求选择即可。
+
+编译器类型对程序的影响
+~~~~~~~~~~~
+
+讲解编译器类型时提到，编译器名字中带hf和不带hf的差异为硬浮点和软浮点模式，此处通过小实验来进行讲解，对比两种编译器对同样程序的影响。
+
+安装软浮点编译器
+^^^^^^^^
+
+首先安装浮点模式为soft-float类型的编译器，即arm-linux-gnueabi-gcc，它与前面使用的arm-linux-gnueabihf-gcc差异为编译器名字不带"hf"：
+
+::
+
+
+         #在主机上执行如下命令
+
+         sudo apt install gcc-arm-linux-gnueabi
+
+         #安装完成后使用如下命令查看版本
+
+         arm-linux-gnueabi-gcc -v
+
+.. image:: media/armgcc008.png
+   :align: center
+   :alt: 未找到图片8|
+
+
+
+运行软浮点动态编译的程序
+^^^^^^^^^^^^
+
+安装好arm-linux-gnueabi-gcc软浮点编译器后，继续使用hello.c程序进行实验。
+
+切换至前面hello.c的目录，使用不带"hf"的软浮点编译器重新编译：
+
+::
+
+
+
+         #以下命令在主机上运行
+
+         #在hello.c程序所在的目录执行如下命令，注意编译器名字不带hf
+
+         sudo arm-linux-gnueabi-gcc hello.c –o hello
+
+此处我们使用的是同样的hello.c代码文件，只是编译器的类型不同，再次通过readelf工具来查看具体的程序头信息，在主机上执行以下命令：
+
+::
+
+
+         #以下命令在主机上运行
+
+         readelf -h hello
+
+.. image:: media/armgcc009.png
+   :align: center
+   :alt: 未找到图片9|
+
+
+
+可以看到结果与前面的差异在于此处的是soft-float类型，而前面的是hard-float类型，这正是编译器类型不同导致的。
+
+编译好后，尝试在开发板上运行该程序，在开发板的终端执行以下命令。
+
+::
+
+         #以下命令在开发板上的终端上执行
+
+         #切换至共享的NFS目录，下面的目录根据自己的配置修改
+
+         cd /mnt/example/hello_c
+
+         #查看是否有存在前面编译生成的文件
+
+         ls
+
+         #执行主机编译的ARM平台程序，soft-float类型
+
+         ./hello
+
+.. image:: media/armgcc010.png
+   :align: center
+   :alt: 未找到图片10|
+
+
+很遗憾，使用arm-linux-gnueabi-gcc软浮点编译的程序无法正常执行，它提示找不到文件或目录，这是因为程序内部调用了软浮点的类库（如glibc库文件libc.so.6），而开发板配套的库文件是硬浮点类型的。
+
+开发板的glibc库类型
+^^^^^^^^^^^^
+
+关于库文件的类型，同样可以使用readelf工具查看，在开发板中执行以下命令
+
+::
+
+
+         #使用readelf查看开发板的libc.so.6类型
+
+         readelf -h libc.so.6
+
+.. image:: media/armgcc012.png
+   :align: center
+   :alt: 未找到图片2|
+
+
+表示开发板的glibc库文件libc.so.6为ARM架构的hard-float类型库，所以不带hf编译器生成的hello程序与它不兼容，无法正常运行。
+
+运行软浮点静态编译的程序
+^^^^^^^^^^^^
+
+既然hello程序是因为库不兼容，那如果程序使用静态编译，即程序自带相关库的内容，是不是就可以正常运行呢？答案是可以的。我们继续进行如下测试：
+
+在主机执行如下命令，对hello.c进行静态编译生成hello_static程序：
+
+::
+
+
+         #以下命令在主机上运行
+
+         #使用不带hf的编译器对hello.c进行静态编译，生成的程序名为hello_static
+
+         sudo arm-linux-gnueabi-gcc hello.c -o hello_static --static
+
+         #查看生成的程序大小
+
+         ls -lh
+
+         #查看hello_static文件头
+
+         readelf -h hello_static
+
+.. image:: media/armgcc013.png
+   :align: center
+   :alt: 未找到图片2|
+
+可看到使用静态编译得到的hello_static程序比动态编译的hello大，这是因为它自身包含了库文件，使用readelf也可以看到hello_static程序依然是soft-float类型的。
+
+接着尝试在开发板中执行生成的hello_static静态程序：
+
+::
+
+
+      #以下命令在开发板上的终端上执行
+
+      #切换至共享的NFS目录，下面的目录根据自己的配置修改
+
+      cd /mnt/example/hello_c
+
+      #查看是否有存在前面编译生成的文件
+
+      ls
+
+      #执行主机编译的ARM平台程序，soft-float类型，静态可执行文件
+
+      ./hello_static
+
+如下图:
+
+.. image:: media/armgcc014.png
+   :align: center
+   :alt: 未找到图片2|
+
+hello_static程序正常运行，这就是编译器及系统库文件对程序运行的影响。
+
+.. |armgcc002| image:: media\armgcc002.png
+   :align: center
+   :alt: 未找到图片
+
+.. |armgcc003| image:: media\armgcc003.png
+   :width: 5.76806in
+   :height: 3.18445in
+
+.. |armgcc004| image:: media\armgcc004.png
+   :width: 5.69444in
+   :height: 2.85577in
+
+.. |armgcc005| image:: media\armgcc005.png
+   :width: 5.71528in
+   :height: 2.61855in
+
+.. |armgcc006| image:: media\armgcc006.png
+   :width: 4.625in
+   :height: 2.00549in
+
+.. |armgcc007| image:: media\armgcc007.jpg
+   :width: 5.20833in
+   :height: 4.99429in
+
+.. |armgcc008| image:: media\armgcc008.png
+   :width: 5.76806in
+   :height: 3.90812in
+
+.. |armgcc009| image:: media\armgcc009.png
+   :width: 5.76806in
+   :height: 2.72848in
+
+.. |armgcc010| image:: media\armgcc010.png
+   :width: 5.7505in
+   :height: 1.19177in
+
+.. |armgcc011| image:: media\armgcc011.png
+   :width: 5.77083in
+   :height: 0.47222in
+
+.. |armgcc012| image:: media\armgcc012.png
+   :width: 5.76159in
+   :height: 3.3125in
+
+.. |armgcc013| image:: media\armgcc013.png
+   :width: 5.76806in
+   :height: 3.89544in
+
+.. |armgcc014| image:: media\armgcc014.png
+   :width: 5.76806in
+   :height: 1.912in
+
diff --git a/documentation/linux_app/filesystem_system_call.rst b/documentation/linux_app/filesystem_system_call.rst
index 85fd57d19e967d2a011966b25b8bf8aadd922416..c6a20233d87b804389817937688cba3d7640abab 100644
--- a/documentation/linux_app/filesystem_system_call.rst
+++ b/documentation/linux_app/filesystem_system_call.rst
@@ -1,144 +1,193 @@
 .. vim: syntax=rst
 
 文件操作与系统调用
----------
+---------------------------
 
 在Linux系统中有一个重要的概念：一切皆文件，它把一切资源都看作是文件，包括硬件设备，通常称为设备文件。前面我们也尝试过通过脚本读写文件的方式，实现了对硬件的访问。所以如果不了解Linux的文件操作，那想要点亮开发板的LED灯都费劲！
 
 本章通过C标准库及系统调用的方式操作文件，揭示用户应用程序、C标准库与系统调用之间的关系。
 
-本章的示例代码目录为：base_code/section2/file_io。
+本章的示例代码目录为：base_code/linux_app/file_io。
 
 存储设备文件系统
-~~~~~~~~
+~~~~~~~~~~~~~~~~~~~~~~~~
 
 提到文件系统时，我们首先想到的通常是Windows下的FAT32、NTFS、exFAT以及Linux下常用的ext2、ext3和ext4的类型格式。这些文件系统都是为了解决如何高效管理存储器空间的问题而诞生的。
 
-从EEPROM、Nor FLASH、NAND FLASH、eMMC到机械硬盘，各种各样的存储器本质就是具有多个能够存储0和1数据单元的设备，存储内容时，程序需要直接访问这些存储单元的物理地址来保存内容。这样直接存储数据会带来极大的不便，如难以记录有效数据的位置，难以确定存储介质的剩余空间，以及应以何
+从EEPROM、Nor FLASH、NAND FLASH、eMMC到机械硬盘，各种各样的存储器本质就是具有多个能够
+存储0和1数据单元的设备，存储内容时，程序需要直接访问这些存储单元的物理地址来保存内容。这样直接
+存储数据会带来极大的不便，如难以记录有效数据的位置，难以确定存储介质的剩余空间，以及应以何
 种格式来解读数据。就如同一个巨大的图书馆无人管理，杂乱无章地堆放着各种书籍，难以查找。
 
-为了高效地存储和管理数据，文件系统在存储介质上建立了一种组织结构，这些结构包括操作系统引导区、目录和文件，就如同图书馆给不同类的书籍进行分类、编号，放在不同的书架上。不同的管理理念引出了不同的文件系统标准，上述的 FAT32、 NTFS、
-exFAT、ext2/3/4就是指不同类型的标准，除此之外，还有专门针对NAND类型设备的文件系统jffs2、yaffs2等等。
+为了高效地存储和管理数据，文件系统在存储介质上建立了一种组织结构，这些结构包括操作系
+统引导区、目录和文件，就如同图书馆给不同类的书籍进行分类、编号，放在不同的书架上。不同的管理
+理念引出了不同的文件系统标准，上述的 FAT32、 NTFS、 exFAT、ext2/3/4就是指不同类型的
+标准，除此之外，还有专门针对NAND类型设备
+的文件系统jffs2、yaffs2等等。
 
-正是有了文件系统，计算机上的数据才能以文件的形式呈现给用户。关于文件系统的基本概念，学习野火《STM32库开发实战指南》或《i.MX RT库开发实战指南》中Fatfs文件系统章节的相关内容，可以非常清楚地了解使用MCU直接记录数据与通过文件系统记录文件时的差异。
+正是有了文件系统，计算机上的数据才能以文件的形式呈现给用户。关于文件系统的基本概
+念，学习野火《STM32库开发实战指南》或《i.MX RT库开发实战指南》中Fatfs文件系统章节
+的相关内容，可以非常清楚地了解使用MCU直接记录数据与通过文件系统记录文件时的差异。
 
 下面简单介绍一下各种不同标准文件系统的特性：
 
--  FAT32格式：兼容性好， STM32等MCU也可以通过Fatfs支持FAT32文件系统，大部分SD卡或U盘出厂默认使用的就是FAT32文件系统。它的主要缺点是技术老旧，单个文件不能超过4GB，非日志型文件系统。
+-  FAT32格式：兼容性好， STM32等MCU也可以通过Fatfs支持FAT32文件系统，大部分SD卡或U盘出厂
+   默认使用的就是FAT32文件系统。它的主要缺点是技术老旧，单个文件不能超过4GB，非日志型文件系统。
 
--  NTFS格式：单个文件最大支持256TB、支持长文件名、服务器文件管理权限等，而且NTFS是日志型文件系统。但由于是日志型文件系统，会记录详细的读写操作，相对来说会加快FLASH存储器的损耗。文件系统的日志功能是指，它会把文件系统的操作记录在磁盘的某个分区，当系统发生故障时，能够尽最大的努力保证数
-  据的完整性。
+-  NTFS格式：单个文件最大支持256TB、支持长文件名、服务器文件管理权限等，而且NTFS是日志型
+   文件系统。但由于是日志型文件系统，会记录详细的读写操作，相对来说会加快FLASH存储器的损
+   耗。文件系统的日志功能是指，它会把文件系统的操作记录在磁盘的某个分区，当系统发生故障时，能够
+   尽最大的努力保证数据的完整性。
 
--  exFAT格式：基于FAT32改进而来，专为FLASH介质的存储器设计（如SD卡、U盘），空间浪费少。单个文件最大支持16EB，非日志文件系统。
+-  exFAT格式：基于FAT32改进而来，专为FLASH介质的存储器
+   设计（如SD卡、U盘），空间浪费少。单个文件最大支持16EB，非日志文件系统。
 
 -  ext2格式：简单，文件少时性能较好，单个文件不能超过2TB。非日志文件系统。
 
 -  ext3格式：相对于ext2主要增加了支持日志功能。
 
--  ext4格式：从ext3改进而来，ext3实际是ext4的子集。它支持1EB的分区，单个文件最大支持16TB，支持无限的子目录数量，使用延迟分配策略优化了文件的数据块分配，允许自主控制是否使用日志的功能。
+-  ext4格式：从ext3改进而来，ext3实际是ext4的子集。它支持1EB的分区，单个文件最大支
+   持16TB，支持无限的子目录数量，使用延迟分配策略优化了文件的数据块分配，允许自主控制是否使用日志的功能。
 
--  jffs2和yaffs2格式： jffs2和yaffs2是专为FLASH类型存储器设计的文件系统，它们针对FLASH存储器的特性加入了擦写平衡和掉电保护等特性。由于Nor、NAND FLASH类型存储器的存储块的擦写次数是有限的（通常为10万次），使用这些类型的文件系统可以减少对存储器的损耗。
+-  jffs2和yaffs2格式： jffs2和yaffs2是专为FLASH类型存储器设计的文件
+   系统，它们针对FLASH存储器的特性加入了擦写平衡和掉电保护等特性。由于Nor、NAND FLASH类
+   型存储器的存储块的擦写次数是有限的（通常为10万次），使用这些类型的文件系统可以减少对存储器的损耗。
 
-总的来说，在Linux下，ext2适用于U盘（但为了兼容，使用得比较多的还是FAT32或exFAT），日常应用推荐使用ext4，而ext3使用的场景大概就只剩下对ext4格式的稳定性还有疑虑的用户了，但ext4从2008年就已结束实验期，进入稳定版了，可以放心使用。
+总的来说，在Linux下，ext2适用于U盘（但为了兼容，使用得比较多的还是FAT32或exFAT），日常应用推
+荐使用ext4，而ext3使用的场景大概就只剩下对ext4格式的稳定性还有疑虑的用户了，但ext4从2008年就已结束
+实验期，进入稳定版了，可以放心使用。
 
-Linux内核本身也支持FAT32文件系统，而使用NTFS格式则需要安装额外的工具如ntfs-3g。所以使用开发板出厂的默认Linux系统时，把FAT32格式的U盘直接插入到开发板是可以自动挂载的，而NTFS格式的则不支持。主机上的Ubuntu对于NTFS或FAT32的U盘都能自动识别并挂载，因为U
-buntu发行版安装了相应的支持。目前微软已公开exFAT文件系统的标准，且已把它开源至Linux，未来Linux可能也默认支持exFAT。
+Linux内核本身也支持FAT32文件系统，而使用NTFS格式则需要安装额外的工具如ntfs-3g。所以使用开发板出厂的
+默认Linux系统时，把FAT32格式的U盘直接插入到开发板是可以自动挂载的，而NTFS格式的则不支持。主机上
+的Ubuntu对于NTFS或FAT32的U盘都能自动识别并挂载，因为U
+buntu发行版安装了相应的支持。目前微软已公开exFAT文件系统的标准，且已把它开源至Linux，未来Linux可能
+也默认支持exFAT。
 
 对于非常在意FLASH存储器损耗的场合，则可以考虑使用jffs2或yaffs2等文件系统。
 
 在Linux下，可以通过如下命令查看系统当前存储设备使用的文件系统：
 
-#在主机或开发板上执行如下命令
+.. code-block:: sh
+   :linenos:
+
+   #在主机或开发板上执行如下命令
+   df -T
+
+如下图:
 
-df -T
+.. image:: media/filesy002.png
+   :align: center
+   :alt: 未找到图片02|
 
-|filesy002|
 
-图 19‑1 主机上存储设备使用的文件系统
 
-从图 19‑1中，主机的硬盘设备为“/dev/sda1”，它使用的文件系统类型为ext4，挂载点是根目录“/”。
+从上图可以看出，主机的硬盘设备为"/dev/sda1"，它使用的文件系统
+类型为ext4，挂载点是根目录"/"。
 
 伪文件系统
-~~~~~
+~~~~~~~~~~~~~~~~
 
-除了前面介绍的专门用于存储设备记录文件的文件系统外，Linux内核还提供了procfs、sysfs和devfs等伪文件系统。
+除了前面介绍的专门用于存储设备记录文件的文
+件系统外，Linux内核还提供了procfs、sysfs和devfs等伪文件系统。
 
-伪文件系统存在于内存中，通常不占用硬盘空间，它以文件的形式，向用户提供了访问系统内核数据的接口。用户和应用程序可以通过访问这些数据接口，得到系统的信息，而且内核允许用户修改内核的某些参数。
+伪文件系统存在于内存中，通常不占用硬盘空间，它以文
+件的形式，向用户提供了访问系统内核数据的接口。用户和应用程序
+可以通过访问这些数据接口，得到系统的信息，而且内核允许用户修改内核的某些参数。
 
 procfs文件系统
-^^^^^^^^^^
+^^^^^^^^^^^^^^^^^^^^
 
-procfs是“process filesystem”的缩写，所以它也被称为进程文件系统，procfs通常会自动挂载在根目录下的/proc文件夹。procfs为用户提供内核状态和进程信息的接口，功能相当于Windows的任务管理器。在《第12章
-查看系统信息》章节我们也尝试过/proc目录查看一些系统信息。
+procfs是"process filesystem"的缩写，所以它
+也被称为进程文件系统，procfs通常会自动挂载在根
+目录下的/proc文件夹。procfs为用户提供内核状态和进程信息的接口，功能相
+当于Windows的任务管理器。
+在《查看系统信息》章节我们也尝试过/proc目录查看一些系统信息。
 
 使用如下命令可以查看proc文件系统的内容：
 
 #在主机或开发板上执行如下命令
 
-#查看CPU信息
+.. code-block:: sh
+   :linenos:
 
-cat /proc/cpuinfo
+   #查看CPU信息
+   cat /proc/cpuinfo
+   #查看proc目录
+   ls /proc
 
-#查看proc目录
+如下图:
 
-ls /proc
+.. image:: media/filesy003.png
+   :align: center
+   :alt: 未找到图片03|
 
-|filesy003|
 
-图 19‑2 查看CPU信息
 
-|filesy004|
 
-图 19‑3 proc目录下的内容
+.. image:: media/filesy004.png
+   :align: center
+   :alt: 未找到图片04
 
-图 19‑1查看了CPU的信息，而图 19‑3表示/proc包含了非常多以数字命名的目录，这些数字就是进程的PID号，其它文件或目录的一些说明见表 19‑1。
 
-表 19‑1 /proc各个文件的作用
+
+刚才我们查看了CPU的信息，而上图表示/proc包含了非常多以数字命
+名的目录，这些数字就是进程的PID号，其它文件或目录的一些说明见下表。
+
+表   /proc各个文件的作用
 
 =========== ================================================================================================================================================================================
 文件名      作用
 =========== ================================================================================================================================================================================
 pid\*       \*表示的是进程的 PID 号，系统中当前运行的每一个进程都有对应的一个目录，用于记录进程所有相关信息。对于操作系统来说，一个应用程序就是一个进程
 self        该文件是一个软链接，指向了当前进程的目录，通过访问/proc/self/目录来获取当前进程的信息，就不用每次都获取pid
-thread-self 该文件也是一个软链接，指向了当前线程，访问该文件，等价于访问“当前进程pid/task/当前线程tid”的内容。。一个进程，可以包含多个线程，但至少需要一个进程，这些线程共同支撑进程的运行。
-version     记录了当前运行的内核版本，通常可以使用命令”uname –r”
+thread-self 该文件也是一个软链接，指向了当前线程，访问该文件，等价于访问"当前进程pid/task/当前线程tid"的内容。。一个进程，可以包含多个线程，但至少需要一个进程，这些线程共同支撑进程的运行。
+version     记录了当前运行的内核版本，通常可以使用命令"uname –r"
 cpuinfo     记录系统中CPU的提供商和相关配置信息
 modules     记录了目前系统加载的模块信息
 meminfo     记录系统中内存的使用情况，free命令会访问该文件，来获取系统内存的空闲和已使用的数量
-filesystems 记录内核支持的文件系统类型，通常mount一个设备时，如果没有指定文件系统并且它无法确定文件系统类型时，mount会尝试包含在该文件中的文件系统，除了那些标有“nodev”的文件系统。
+filesystems 记录内核支持的文件系统类型，通常mount一个设备时，如果没有指定文件系统并且它无法确定文件系统类型时，mount会尝试包含在该文件中的文件系统，除了那些标有"nodev"的文件系统。
 =========== ================================================================================================================================================================================
 
 下面我们以当前bash的进程pid目录，来了解proc文件系统的一些功能。
 
 使用如下命令来查看当前bash进程的PID号。
 
-#在主机上执行如下命令
+.. code-block:: sh
+   :linenos:
 
-ps
+   #在主机上执行如下命令
+   ps
 
-每个人的计算机运行运行状况不一样，所以得到的进程号也是不一样，如图 19‑4所示，当前得到bash进程的pid是3042。
+每个人的计算机运行运行状况不一样，所以得到的进程号也是不一样，如下图所示，当前得
+到bash进程的pid是3042。
 
-|filesy005|
+.. image:: media/filesy005.png
+   :align: center
+   :alt: 未找到图片05|
 
-图 19‑4 当前进程号
 
 根据这个pid号，查看proc/3042目录的内容，它记录了进程运行过程的相关信息。
 
 执行如下命令：
 
-#在主机上执行如下命令
+.. code-block:: sh
+   :linenos:
+
+   #在主机上执行如下命令
+   #把目录中的数字改成自己bash进程的pid号
+   ls /proc/3042
 
-#把目录中的数字改成自己bash进程的pid号
+如下图:
 
-ls /proc/3042
+.. image:: media/filesy006.png
+   :align: center
+   :alt: 未找到图片06|
 
-|filesy006|
 
-图 19‑5 3042进程目录
 
-该目录下的一些文件夹和文件的意义如表 19‑2。
+该目录下的一些文件夹和文件的意义如下表。
 
-表 19‑2 文件夹及文件内容
+表    文件夹及文件内容
 
 ========= ========================================================================
 文件名    文件内容
@@ -161,31 +210,45 @@ wchan     记录当前进程处于睡眠状态，内核调用的相关函数
 
 如果是文件，可以直接使用cat命令输出对应文件的内容可查看，如查看进程名：
 
-#在主机上执行如下命令
+.. code-block:: sh
+   :linenos:
 
-#把目录中的数字改成自己bash进程的pid号
+   #在主机上执行如下命令
+   #把目录中的数字改成自己bash进程的pid号 
+   cat /proc/3042/comm
 
-cat /proc/3042/comm
+.. image:: media/filesy007.png
+   :align: center
+   :alt: 未找到图片07|
 
-|filesy007|
 
-图 19‑6查看进程名
 
-可看到进程名为“bash”，实际上前面的“ps”命令也是通过“proc”文件系统获取到相关进程信息的。
+可看到进程名为"bash"，实际上前面的"ps"命令也
+是通过"proc"文件系统获取到相关进程信息的。
 
 sysfs文件系统
-^^^^^^^^^
+^^^^^^^^^^^^^^^^^^
+
+上一节我们提及到的procfs是"任务管理器"，那sysfs同procfs一样，也是一
+个伪文件系统，那么它的作用是什么呢？
+
+Linux内核在2.6版本中引入了sysfs文件系统，sysfs通常会自动挂载在根目录下的sys文件夹。sys目录下的文
+件/文件夹向用户提供了一些关于设备、内核模块、文件系统以及其他内核组件的信息，如子目录block中存放了所
+有的块设备，而bus中存放了系统中所有的总线类型，有i2c，usb，sdi
+o，pci等。下图中的虚线表示软连接，可以看到所有跟设备
+有关的文件或文件夹都链接到了device目录下，类似于将一个大类，根
+据某个特征分为了无数个种类，这样使得/sys文件夹的结构层次清晰明了。
 
-上一节我们提及到的procfs是“任务管理器”，那sysfs同procfs一样，也是一个伪文件系统，那么它的作用是什么呢？
+如下图:
 
-Linux内核在2.6版本中引入了sysfs文件系统，sysfs通常会自动挂载在根目录下的sys文件夹。sys目录下的文件/文件夹向用户提供了一些关于设备、内核模块、文件系统以及其他内核组件的信息，如子目录block中存放了所有的块设备，而bus中存放了系统中所有的总线类型，有i2c，usb，sdi
-o，pci等。图 19‑7中的虚线表示软连接，可以看到所有跟设备有关的文件或文件夹都链接到了device目录下，类似于将一个大类，根据某个特征分为了无数个种类，这样使得/sys文件夹的结构层次清晰明了。
+.. image:: media/filesy008.jpg
+   :align: center
+   :alt: 未找到图片08|
 
-|filesy008|
 
-图 19‑7 sysfs结构
 
-表格 19‑1 /sys各个文件的作用
+
+表   /sys各个文件的作用
 
 ======= ======================================================================================================================
 文件名  作用
@@ -198,52 +261,77 @@ module  该目录记录了系统加载的所有内核模块，每个文件夹名
 fs      包含了系统中注册文件系统
 ======= ======================================================================================================================
 
-概括来说，sysfs文件系统是内核加载驱动时，根据系统上的设备和总线构成导出的分级目录，它是系统上设备的直观反应，每个设备在sysfs下都有唯一的对应目录，用户可以通过具体设备目录下的文件访问设备。
+概括来说，sysfs文件系统是内核加载驱动时，根据系统上的设备和总
+线构成导出的分级目录，它是系统上设备的直观反应，每个设备在sysfs下都有
+唯一的对应目录，用户可以通过具体设备目录下的文件访问设备。
 
-在《第13章 使用命令点灯和检测按键第13章 》的示例中，我们就是通过访问sysfs文件系统达到了控制LED灯的目的。
+在《使用命令点灯和检测按键》章节的示例中，我们就是
+通过访问sysfs文件系统达到了控制LED灯的目的。
 
 devfs文件系统
-^^^^^^^^^
+^^^^^^^^^^^^^^^^^^^^^^^^^^^
 
-在Linux 2.6内核之前一直使用的是devfs文件系统管理设备，它通常挂载于/dev目录下。devfs中的每个文件都对应一个设备，用户也可以通过/dev目录下的文件访问硬件。在sysfs出现之前，devfs是在制作根文件系统的时候就已经固定的，这不太方便使用，而当代的devfs通常会在系统运行时
-使用名为udev的工具根据sysfs目录生成devfs目录。在后面学习制作根文件系统时，就会接触到静态devfs以及使用udev动态生成devfs的选项。
+在Linux 2.6内核之前一直使用的是devfs文件系统管理设备，它通
+常挂载于/dev目录下。devfs中的每个文件都对应一个设备，用户也可以通过/dev目录下的文件访
+问硬件。在sysfs出现之前，devfs是在制作根文件系统的时候就已经固定的，这不太方便使用，而当
+代的devfs通常会在系统运行时
+使用名为udev的工具根据sysfs目录生成devfs目录。在后面学习制作根文件系统时，就会接触到
+静态devfs以及使用udev动态生成devfs的选项。
 
 在接下来的几个章节我们会通过具体的硬件设备讲解sysfs、devfs的使用，为大家建立起设备文件的概念。
 
 虚拟文件系统
-~~~~~~
+~~~~~~~~~~~~~~~~~~
 
-除了前面提到的存储器文件系统FAT32、ext4，伪文件系统/proc、/sys、/dev外，还有内存文件系统ramfs，网络文件系统nfs等等，不同的文件系统标准，需要使用不同的程序逻辑实现访问，对外提供的访问接口可能也稍有差异。但是我们在编写应用程序时，大都可以通过类似fopen、fread、f
-write等C标准库函数访问文件，这都是虚拟文件系统的功劳。
+除了前面提到的存储器文件系统FAT32、ext4，伪文件系统/proc、/sys、/dev外，还有内
+存文件系统ramfs，网络文件系统nfs等等，不同的文件系统标准，需要使用不同的程序逻辑实
+现访问，对外提供的访问接口可能也稍有差异。但是我们在编写应用程序时，大都可以通
+过类似fopen、fread、fwrite等C标准库函数
+访问文件，这都是虚拟文件系统的功劳。
 
-Linux内核包含了文件管理子系统组件，它主要实现了虚拟文件系统（Virtual File System，VFS），虚拟文件系统屏蔽了各种硬件上的差异以及具体实现的细节，为所有的硬件设备提供统一的接口，从而达到设备无关性的目的，同时文件管理系统还为应用层提供统一的API接口。
+Linux内核包含了文件管理子系统组件，它主要实现了虚
+拟文件系统（Virtual File System，VFS），虚拟文件系统屏蔽了各种硬件上的差
+异以及具体实现的细节，为所有的硬件设备提供统一的接口，从而达到设备无关性的
+目的，同时文件管理系统还为应用层提供统一的API接口。
 
-在Linux下，一个与文件操作相关的应用程序结构如图 19‑8。
+在Linux下，一个与文件操作相关的应用程序结构如下图所示。
 
-|filesy009|
+.. image:: media/filesy009.png
+   :align: center
+   :alt: 未找到图片09|
 
-图 19‑8 虚拟文件系统
 
-图 19‑8解构如下：
+
+上图解构如下：
 
 -  应用层指用户编写的程序，如我们的hello.c。
 
--  GNU C库（glibc）即C语言标准库，例如在编译器章节介绍的libc.so.6文件，它包含了printf、malloc，以及本章使用的fopen、fread、fwrite等文件操作函数。
+-  GNU C库（glibc）即C语言标准库，例如在编译器章节介绍的libc.so.6文件，它
+   包含了printf、malloc，以及本章使用的fopen、fread、fwrite等文件操作函数。
 
 -  用户程序和glibc库都是属于用户空间的，本质都是用户程序。
 
--  应用层的程序和glibc可能会调用到“系统调用层（SCI）”的函数，这些函数是Linux内核对外提供的函数接口，用户通过这些函数向系统申请操作。例如，C库的printf函数使用了系统的vsprintf和write函数，C库的fopen、fread、fwrite分别调用了系统的open、read、w
-  rite函数，具体可以阅读glibc的源码了解。
+-  应用层的程序和glibc可能会调用到"系统调用层（SCI）"的函数，这些函数
+   是Linux内核对外提供的函数接口，用户通过这些函数向系统申请操作。例如，C库
+   的printf函数使用了系统的vsprintf和write函数，C库的fopen、fread、fwrite分别
+   调用了系统的open、read、w
+   rite函数，具体可以阅读glibc的源码了解。
 
--  由于文件系统种类非常多，跟文件操作相关的open、read、write等函数经过虚拟文件系统层，再访问具体的文件系统。
+-  由于文件系统种类非常多，跟文件操作相关的open、read、write等函数经过虚
+   拟文件系统层，再访问具体的文件系统。
 
-总的来说，为了使不同的文件系统共存， Linux内核在用户层与具体文件系统之前增加了虚拟文件系统中间层，它对复杂的系统进行抽象化，对用户提供了统一的文件操作接口。无论是ext2/3/4、FAT32、NTFS存储的文件，还是/proc、/sys提供的信息还是硬件设备，无论内容是在本地还是网络上，都使用
-一样的open、read、write来访问，使得“一切皆文件”的理念被实现，这也正是软件中间层的魅力。
+总的来说，为了使不同的文件系统共存， Linux内核在用户层与具体文件
+系统之前增加了虚拟文件系统中间层，它对复杂的系统进行抽象化，对用户提供了统
+一的文件操作接口。无论是ext2/3/4、FAT32、NTFS存储的文件，还是/proc、/sys提供
+的信息还是硬件设备，无论内容是在本地还是网络上，都使用
+一样的open、read、write来访问，使得"一切皆文件"的理念被实现，这也正是软件中间层的魅力。
 
 Linux系统调用
-~~~~~~~~~
+~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
-从图 19‑8可了解到，系统调用（System Call）是操作系统提供给用户程序调用的一组“特殊”函数接口API，文件操作就是其中一种类型。实际上，Linux提供的系统调用包含以下内容：
+从上图可了解到，系统调用（System Call）是操作系统提供给用
+户程序调用的一组"特殊"函数接口API，文件操作就是其中一种类型。实际
+上，Linux提供的系统调用包含以下内容：
 
 -  进程控制：如fork、clone、exit 、setpriority等创建、中止、设置进程优先级的操作。
 
@@ -261,14 +349,18 @@ Linux系统调用
 
 -  进程间通信：包含信号量、管道、共享内存等操作。
 
-从逻辑上来说，系统调用可被看成是一个Linux内核与用户空间程序交互的中间人，它把用户进程的请求传达给内核，待内核把请求处理完毕后再将处理结果送回给用户空间。它的存在就是为了对用户空间与内核空间进行隔离，要求用户通过给定的方式访问系统资源，从而达到保护系统的目的。
+从逻辑上来说，系统调用可被看成是一个Linux内核与用户空间程序交互的中间人，它把用户
+进程的请求传达给内核，待内核把请求处理完毕后再将处理结果送回给用户空间。它的
+存在就是为了对用户空间与内核空间进行隔离，要求用户通过给定的方式访问系统资源，从
+而达到保护系统的目的。
 
-也就是说，我们心心念念的Linux应用程序与硬件驱动程序之间，就是各种各样的系统调用，所以无论出于何种目的，系统调用是学习Linux开发绕不开的话题。
+也就是说，我们心心念念的Linux应用程序与硬件驱动程序之间，就是各种各样的系统
+调用，所以无论出于何种目的，系统调用是学习Linux开发绕不开的话题。
 
 本章通过文件操作的两个实验，来演示使用C标准库与系统调用方式的差异。
 
 文件操作（C标准库）
-~~~~~~~~~~
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
 本小节讲解使用通用的C标准库接口访问文件，标准库实际是对系统调用再次进行了封装。使用C标准库编写的代码，能方便地在不同的系统上移植。
 
@@ -276,85 +368,101 @@ Linux系统调用
 新编译程序即可，而不需要修改对应的代码。
 
 常用文件操作（C标准库）
-^^^^^^^^^^^^
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 
 在开发时，遇到不熟悉的库函数或系统调用，要善用man手册，而不要老是从网上查找。C标准库提供的常用文件操作简介如下：
 
 fopen函数
-'''''''
+""""""""""""""""""""""""""""
 
 fopen库函数用于打开或创建文件，返回相应的文件流。它的函数原型如下：
 
-#include <stdio.h>
+.. code-block:: sh
+   :linenos:
 
-FILE \*fopen(const char \*pathname, const char \*mode);
+   #include <stdio.h>
+   FILE *fopen(const char *pathname, const char *mode);
 
 -  pathname参数用于指定要打开或创建的文件名。
 
 -  mode参数用于指定文件的打开方式，注意该参数是一个字符串，输入时需要带双引号：
 
--  “r”：以只读方式打开，文件指针位于文件的开头。
+-  "r"：以只读方式打开，文件指针位于文件的开头。
 
--  “r+”：以读和写的方式打开，文件指针位于文件的开头。
+-  "r+"：以读和写的方式打开，文件指针位于文件的开头。
 
--  “w”：以写的方式打开，不管原文件是否有内容都把原内容清空掉，文件指针位于文件的开头。
+-  "w"：以写的方式打开，不管原文件是否有内容都把原内容清空掉，文件指针位于文件的开头。
 
--  “w+”： 同上，不过当文件不存在时，前面的“w”模式会返回错误，而此处的“w+”则会创建新文件。
+-  "w+"： 同上，不过当文件不存在时，前面的"w"模式会返回错误，而此处的"w+"则会创建新文件。
 
--  “a”：以追加内容的方式打开，若文件不存在会创建新文件，文件指针位于文件的末尾。与“w+”的区别是它不会清空原文件的内容而是追加。
+-  "a"：以追加内容的方式打开，若文件不存在会创建新文件，文件指针位于文件的末尾。与"w+"的区别是它不会清空原文件的内容而是追加。
 
--  “a+”：以读和追加的方式打开，其它同上。
+-  "a+"：以读和追加的方式打开，其它同上。
 
 -  fopen的返回值是FILE类型的文件文件流，当它的值不为NULL时表示正常，后续的fread、fwrite等函数可通过文件流访问对应的文件。
 
 fread函数
-'''''''
+""""""""""""""""""""""""""""
 
 fread库函数用于从文件流中读取数据。它的函数原型如下：
 
-#include <stdio.h>
+.. code-block:: sh
+   :linenos:
 
-size_t fread(void \*ptr, size_t size, size_t nmemb, FILE \*stream);
+   #include <stdio.h>
+   size_t fread(void *ptr, size_t size, size_t nmemb, FILE *stream);
 
-stream是使用fopen打开的文件流，fread通过它指定要访问的文件，它从该文件中读取nmemb项数据，每项的大小为size，读取到的数据会被存储在ptr指向的数组中。fread的返回值为成功读取的项数（项的单位为size）。
+stream是使用fopen打开的文件流，fread通过它指定要访问的文件，它从该文件中读取nmemb项
+数据，每项的大小为size，读取到的数据会被存储在ptr指向的数组中。fread的返回值为成功读取的项数（项的单位为size）。
 
 fwrite函数
-''''''''
+""""""""""""""""""""""""""""""""
 
 fwrite库函数用于把数据写入到文件流。它的函数原型如下：
 
-#include <stdio.h>
+.. code-block:: sh
+   :linenos:
 
-size_t fwrite(void \*ptr, size_t size, size_t nmemb, FILE \*stream);
+   #include <stdio.h>
+   size_t fwrite(void *ptr, size_t size, size_t nmemb, FILE *stream);
 
-它的操作与fread相反，把ptr数组中的内容写入到stream文件流，写入的项数为nmemb，每项大小为size，返回值为成功写入的项数（项的单位为size）。
+它的操作与fread相反，把ptr数组中的内容写入到stream文件流，写入的项数为nmemb，每项
+大小为size，返回值为成功写入的项数（项的单位为size）。
 
 fclose函数
-''''''''
+""""""""""""""""""""""""""""""""
 
-fclose库函数用于关闭指定的文件流，关闭时它会把尚未写到文件的内容都写出。因为标准库会对数据进行缓冲，所以需要使用fclose来确保数据被写出。它的函数原型如下：
+fclose库函数用于关闭指定的文件流，关闭时它会把尚未写到文件的内容都写出。因为标准
+库会对数据进行缓冲，所以需要使用fclose来确保数据被写出。它的函数原型如下：
 
-#include <unistd.h>
+.. code-block:: sh
+   :linenos:
 
-int close(int fd);
+   #include <unistd.h>
+   int close(int fd);
 
 fflush函数
-''''''''
+""""""""""""""""""""""""""""""""
 
-fflush函数用于把尚未写到文件的内容立即写出。常用于确保前面操作的数据被写入到磁盘上。fclose函数本身也包含了fflush的操作。fflush的函数原型如下：
+fflush函数用于把尚未写到文件的内容立即写出。常用于确保前面操作的数据被写
+入到磁盘上。fclose函数本身也包含了fflush的操作。fflush的函数原型如下：
 
-#include <stdio.h>
+.. code-block:: sh
+   :linenos:
 
-int fflush(FILE \*stream);
+   #include <stdio.h>
+   int fflush(FILE *stream);
 
 fseek函数
-'''''''
+"""""""""""""""""""""""""""""""""""""
 
 fseek函数用于设置下一次读写函数操作的位置。它的函数原型如下：
 
-#include <stdio.h>
+.. code-block:: sh
+   :linenos:
 
-int fseek(FILE \*stream, long offset, int whence);
+   #include <stdio.h>
+   int fseek(FILE *stream, long offset, int whence);
 
 其中的offset参数用于指定位置，whence参数则定义了offset的意义，whence的可取值如下：
 
@@ -365,320 +473,246 @@ int fseek(FILE \*stream, long offset, int whence);
 -  SEEK_CUR：offset是以当前位置为参考点的相对位置。
 
 实验代码分析
-^^^^^^
-
-下面我们使用C标准库进行文件操作实验，见代码清单 19‑1。
-
-代码清单 19‑1 文件操作实验-C标准库（file_io/stdio/main.c文件）
-
-1
-
-2 #include <stdio.h>
-
-3 #include <string.h>
-
-4
-
-5 //要写入的字符串
-
-6 const char buf[] = "filesystem_test:Hello World!\n";
-
-7 //文件描述符
-
-8 FILE \*fp;
-
-9 char str[100];
-
-10 int len;
-
-11
-
-12
-
-13 int main(void)
-
-14 {
-
-15 //创建一个文件
-
-16 fp = fopen("filesystem_test.txt", "w+");
-
-17 //正常返回文件指针
-
-18 //异常返回NULL
-
-19 if (NULL == fp) {
-
-20 printf("Fail to Open File\n");
-
-21 return 0;
-
-22 }
-
-23 //将buf的内容写入文件
-
-24 //每次写入1个字节，总长度由strlen给出
-
-25 fwrite(buf, 1, strlen(buf), fp);
-
-26
-
-27 //写入Embedfire
+^^^^^^^^^^^^^^^^^^
 
-28 //每次写入1个字节，总长度由strlen给出
 
-29 fwrite("Embedfire\n", 1, strlen("Embedfire\n"),fp);
+下面我们使用C标准库进行文件操作实验，如下所示。
 
-30
 
-31 //把缓冲区的数据立即写入文件
+.. code-block:: c
+   :caption: 文件操作实验-C标准库（base_code/linux_app/file_io/stdio/main.c文件）
+   :linenos:
+   
+   #include <stdio.h>
+   #include <string.h>
 
-32 fflush(fp);
+   //要写入的字符串
+   const char buf[] = "filesystem_test:Hello World!\n";
+   //文件描述符
+   FILE *fp;
+   char str[100];
 
-33
 
-34 //此时的文件位置指针位于文件的结尾处，使用fseek函数使文件指针回到文件头
+   int main(void)
+   {
+      //创建一个文件
+      fp = fopen("filesystem_test.txt", "w+");
+      //正常返回文件指针
+      //异常返回NULL
+      if(NULL == fp){
+         printf("Fail to Open File\n");
+         return 0;
+      }
+      //将buf的内容写入文件
+      //每次写入1个字节，总长度由strlen给出
+      fwrite(buf, 1, strlen(buf), fp);
 
-35 fseek(fp, 0, SEEK_SET);
+      //写入Embedfire
+      //每次写入1个字节，总长度由strlen给出
+      fwrite("Embedfire\n", 1, strlen("Embedfire\n"),fp);
 
-36
+      //把缓冲区的数据立即写入文件 
+      fflush(fp);
 
-37 //从文件中读取内容到str中
+      //此时的文件位置指针位于文件的结尾处，使用fseek函数使文件指针回到文件头
+      fseek(fp, 0, SEEK_SET);
 
-38 //每次读取100个字节，读取1次
+      //从文件中读取内容到str中
+      //每次读取100个字节，读取1次
+      fread(str, 100, 1, fp);
 
-39 //返回读取了多少次，若返回值为0表示到达了文件尾
+      printf("File content:\n%s \n", str);
 
-40 len = fread(str, 100, 1, fp);
+      fclose(fp);
 
-41
-
-42 printf("File content: %s \\nread len=%d\n", str, len);
-
-43
-
-44 fclose(fp);
-
-45
-
-46 return 0;
-
-47 }
+      return 0;
+   }
+  
 
 如果之前有学习过C语言的文件操作，本实验代码非常容易理解，它的流程就是使用fopen创建文件、使用fwrite写入内容，使用fflush确保缓冲区的内容写到文件，然后使用fseek重置文件位置指针，使用fread把文件的内容读出，最后调用fclose关闭文件。
 
-其中的fopen函数调用时使用了参数“w+”，表示每次都创建新的空文件，且带上读权限打开，函数调用后得到文件描述符fp，在它后面的fwrite、fread、fflush等函数都是通过这个fp文件描述符访问该文件的。
+其中的fopen函数调用时使用了参数"w+"，表示每次都创建新的空文件，且带上读权限打开，函数调用后得到文件描述符fp，在它后面的fwrite、fread、fflush等函数都是通过这个fp文件描述符访问该文件的。
 
-与下一小节中差异最大的就是此处fwrite和fread之间的fflush函数，C标准库的文件系统带缓冲区，而系统调用的文件操作不带缓冲区，所以没有相应的flush函数。
+与下一小节中差异最大的就是此处fwrite和fread之间
+的fflush函数，C标准库的文
+件系统带缓冲区，而系统调用的文件操作不带缓冲区，所以没有相应的flush函数。
 
 Makefile说明
-^^^^^^^^^^
-
-Makefile是跟工程目录匹配的，本实验仅有一个main.c文件，且与Makefile处于同级目录。它的工程文件结构如图 19‑9。
-
-|filesy010|
-
-图 19‑9 工程的目录结构
-
-此处编写的Makefile与《18.7.2 多级结构工程的Makefile》章节的基本一致，见代码清单 19‑2。
-
-代码清单 19‑2 文件操作-C标准库的Makefile（file_io/stdio/Makefile文件）
-
-1 #生成可执行文件的名称
-
-2 Target = file_demo
-
-3 ARCH ?= x86
-
-4 #编译器CC
-
-5 #根据传入的参数ARCH，确定使用的编译器
-
-6 #默认使用gcc编译器
-
-7 #make ARCH=arm 时使用ARM-GCC编译器
-
-8 ifeq ($(ARCH), x86)
-
-9 CC = gcc
-
-10 else
-
-11 CC = arm-linux-gnueabihf-gcc
-
-12 endif
-
-13 #存放中间文件的路径
-
-14 build_dir = build_$(ARCH)
-
-15 #存放源文件的文件夹
-
-16 src_dir = .
-
-17 #存放头文件的文件夹
-
-18 inc_dir = includes .
-
-19
-
-20 #源文件
-
-21 sources = $(foreach dir,$(src_dir),$(wildcard $(dir)/*.c))
-
-22 #目标文件（*.o）
-
-23 objects = $(patsubst %.c,$(build_dir)/%.o,$(notdir $(sources)))
-
-24 #头文件
-
-25 includes = $(foreach dir,$(inc_dir),$(wildcard $(dir)/*.h))
-
-26 #编译参数
-
-27 #指定头文件的路径
-
-28 CFLAGS = $(patsubst %, -I%, $(inc_dir))
-
-29
-
-30 #链接过程
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+Makefile是跟工程目录匹配的，本实验仅有一个main.c文件，且与Makefile处
+于同级目录。它的工程文件结构如下图所示。
+
+.. image:: media/filesy010.png
+   :align: center
+   :alt: 未找到图片10|
+
+
+
+此处编写的Makefile与前面《多级结构工程的Makefile》章节的基本一致，如下所示。
+
+
+
+.. code-block:: c
+   :caption: 文件操作-C标准库的Makefile（base_code/linux_app/file_io/stdio/Makefile文件）
+   :linenos:
+
+   #生成可执行文件的名称
+   Target = file_demo
+   ARCH ?= x86
+   #编译器CC
+   #根据传入的参数ARCH，确定使用的编译器
+   #默认使用gcc编译器
+   #make ARCH=arm 时使用ARM-GCC编译器
+   ifeq ($(ARCH), x86)
+      CC = gcc
+   else
+      CC = arm-linux-gnueabihf-gcc
+   endif
+   #存放中间文件的路径
+   build_dir = build_$(ARCH)
+   #存放源文件的文件夹
+   src_dir =  .
+   #存放头文件的文件夹
+   inc_dir = includes .
+
+   #源文件
+   sources = $(foreach dir,$(src_dir),$(wildcard $(dir)/*.c))
+   #目标文件（*.o）
+   objects = $(patsubst %.c,$(build_dir)/%.o,$(notdir $(sources)))
+   #头文件
+   includes = $(foreach dir,$(inc_dir),$(wildcard $(dir)/*.h))
+   #编译参数
+   #指定头文件的路径
+   CFLAGS = $(patsubst %, -I%, $(inc_dir))
+
+   #链接过程
+   #开发板上无法使用动态库，因此使用静态链接的方式
+   $(build_dir)/$(Target) : $(objects)  | create_build
+      $(CC) $^ -o $@ 
+
+   #编译工程
+   #编译src文件夹中的源文件，并将生成的目标文件放在objs文件夹中
+   $(build_dir)/%.o : $(src_dir)/%.c $(includes) | create_build
+      $(CC) -c $(CFLAGS) $< -o $@ 
+
+
+   #以下为伪目标，调用方式：make 伪目标
+   #clean：用于Clean Project
+   #check：用于检查某个变量的值
+   .PHONY:clean cleanall check create_build
+   #按架构删除
+   clean:
+      rm -rf $(build_dir)
+
+   #全部删除
+   cleanall:
+      rm -rf build_x86 build_arm
+
+   #命令前带"@",表示不在终端上输出执行的命令
+   #这个目标主要是用来调试Makefile时输出一些内容
+   check:
+      @echo $(CFLAGS)
+      @echo $(CURDIR)
+      @echo $(src_dir)
+      @echo $(sources)
+      @echo $(objects)
+      
+   #创建一个新目录create，用于存放过程文件
+   create_build:
+      @mkdir -p $(build_dir)
 
-31 #开发板上无法使用动态库，因此使用静态链接的方式
 
-32 $(build_dir)/$(Target) : $(objects) \| create_build
-
-33 $(CC) $^ -o $@
-
-34
-
-35 #编译工程
-
-36 #编译src文件夹中的源文件，并将生成的目标文件放在objs文件夹中
-
-37 $(build_dir)/%.o : $(src_dir)/%.c $(includes) \| create_build
-
-38 $(CC) -c $(CFLAGS) $^ -o $@
-
-39
-
-40
-
-41 #以下为伪目标，调用方式：make 伪目标
-
-42 #clean：用于Clean Project
-
-43 #check：用于检查某个变量的值
-
-44 .PHONY:clean cleanall check create_build
-
-45 #按架构删除
-
-46 clean:
-
-47 rm -rf $(build_dir)
-
-48
-
-49 #全部删除
-
-50 cleanall:
-
-51 rm -rf build_x86 build_arm
-
-52
-
-53 #创建一个新目录create，用于存放过程文件
-
-54 create_build:
-
-55 @mkdir -p $(build_dir)
 
 与前面讲解的Makefile的差异主要如下：
 
--  第2行：本工程编译后的可执行文件名为file_demo，以后我们的Makefile都在此处定义可执行文件名，配合第14行的build_dir变量的值可找到编译后生成的应用程序的目录。
+-  第2行：本工程编译后的可执行文件名为file_demo，以后我们的Makefile都
+   在此处定义可执行文件名，配合第14行的build_dir变量的值可找到编译后生成的应用程序的目录。
 
--  第16行：本工程的源文件跟Makefile在相同的目录，所以表示源文件的src_dir变量赋值为“.”，表示当前目录。
+-  第16行：本工程的源文件跟Makefile在相同的目录，所以表示源文件的src_dir变量赋值为"."，表示当前目录。
 
 -  54~55行：定义了一个名为create_build的伪目标，它执行的Shell命令为创建编译目录，在下面说明的代码中会被用到。
 
--  第32行和第37行：分别是生成最终目标文件和*.o文件的依赖，与之前不同的时它们的末尾都新增了“\| create_build”的内容，其中“ \|
-  ”在此处的意义为前置依赖，create_build为上面说明的伪目标，合起来的意义是create_build这个伪目标要先被执行，即要先创建编译目录。
+-  第32行和第37行：分别是生成最终目标文件和*.o文件的依赖，与之前不同的
+   时它们的末尾都新增了"\| create_build"的内容，其中" \|"在此处的
+   意义为前置依赖，create_build为上面说明的伪目标，合起来的
+   意义是create_build这个伪目标要先被执行，即要先创建编译目录。
 
 编译及测试
-^^^^^
+^^^^^^^^^^^^^^^^^^^^
 
 x86架构
-'''''
+""""""""""""""""""""""""""
 
 本实验支持x86和ARM架构，在x86上的编译及测试命令如下：
 
-#在主机的实验代码Makefile目录下编译
-
-#默认编译x86平台的程序
-
-make
-
-tree
+.. code-block:: sh
+   :linenos:
 
-#运行
+   #在主机的实验代码Makefile目录下编译
+   #默认编译x86平台的程序
+   make
+   tree
+   #运行
+   ./build_x86/file_demo
+   #程序运行后本身有输出，并且创建了一个文件
+   ls
+   #查看文件的内容
+   cat filesystem_test.txt
 
-./build_x86/file_demo
+如下图:
 
-#程序运行后本身有输出，并且创建了一个文件
+.. image:: media/filesy011.png
+   :align: center
+   :alt: 未找到图片11|
 
-ls
 
-#查看文件的内容
-
-cat filesystem_test.txt
-
-|filesy011|
-
-图 19‑10 文件操作实验（C标准库）
 
 ARM架构
-'''''
+""""""""""""""""""""""""""
 
 对于ARM架构的程序，可使用如下步骤进行编译：
 
-#在主机的实验代码Makefile目录下编译
+.. code-block:: sh
+   :linenos:
 
-#编译arm平台的程序
+   #在主机的实验代码Makefile目录下编译
+   #编译arm平台的程序
+   make ARCH=arm
 
-make ARCH=arm
+编译后生成的ARM平台程序为build_arm/file_demo，使用网络文件系统共
+享至开发板，在开发板的终端上运行即可，如下图所示。
 
-编译后生成的ARM平台程序为build_arm/file_demo，使用网络文件系统共享至开发板，在开发板的终端上运行即可，如图 19‑11。
+.. image:: media/filesy012.png
+   :align: center
+   :alt: 未找到图片12|
 
-|filesy012|
 
-图 19‑11 在开发板上的执行现象
 
 文件操作（系统调用）
-~~~~~~~~~~
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
 Linux提供的文件操作系统调用常用的有open、write、read、lseek、close等。
 
 open函数
-''''''
-
-#include <sys/types.h>
-
-#include <sys/stat.h>
-
-#include <fcntl.h>
+^^^^^^^^^
 
-int open(const char \*pathname, int flags);
+.. code-block:: sh
+   :linenos:
 
-int open(const char \*pathname, int flags, mode_t mode);
+   #include <sys/types.h>
+   #include <sys/stat.h>
+   #include <fcntl.h>
+   int open(const char *pathname, int flags);
+   int open(const char *pathname, int flags, mode_t mode);
 
 Linux使用open函数来打开文件，并返回该文件对应的文件描述符。函数参数的具体说明如下：
 
 -  pathname：要打开或创建的文件名；
 
--  flag：指定文件的打开方式，具体有以下参数，见表 19‑3 flag参数值。
+-  flag：指定文件的打开方式，具体有以下参数，见下表 flag参数值。
 
-表 19‑3 flag参数值
+表   flag参数值
 
 ======== ========================================================
 标志位   含义
@@ -691,9 +725,9 @@ O_APPEND 将数据写入到当前文件的结尾处
 O_TRUNC  如果pathname文件存在，则清除文件内容
 ======== ========================================================
 
-C库函数fopen的mode参数与系统调用open的flags参数有如表 19‑4中的等价关系。
+C库函数fopen的mode参数与系统调用open的flags参数有如下表中的等价关系。
 
-表 19‑4 fopen的mode与open的flags参数关系
+表   fopen的mode与open的flags参数关系
 
 =============== ===============================
 fopen的mode参数 open的flags参数
@@ -706,45 +740,58 @@ w+              O_RDWR \| O_CREAT \| O_TRUNC
 a+              O_RDWR \| O_CREAT \| O_APPEND
 =============== ===============================
 
--  mode：当open函数的flag值设置为O_CREAT时，必须使用mode参数来设置文件与用户相关的权限。mode可用的权限如表 19‑5所示，表中各个参数可使用“\| ”来组合。
+-  mode：当open函数的flag值设置为O_CREAT时，必须使用mode参数来设置文件
+   与用户相关的权限。mode可用的权限如下表所示，表中各个参数可使用"\| "来组
+   合。
 
-表 19‑5 文件权限
+表  文件权限
 
-======== ======= ========================================
-标志位   含义
-======== ======= ========================================
-当前用户 S_IRUSR 用户拥有读权限
-\        S_IWUSR 用户拥有写权限
-\        S_IXUSR 用户拥有执行权限
-\        S_IRWXU 用户拥有读、写、执行权限
-当前     S_IRGRP 当前用户组的其他用户拥有读权限
+========== ======= ========================================
+\\         标志位   含义
+========== ======= ========================================
+当前用户   S_IRUSR 用户拥有读权限
+\\         S_IWUSR 用户拥有写权限
+\\         S_IXUSR 用户拥有执行权限
+\\         S_IRWXU 用户拥有读、写、执行权限
+当前用户组 S_IRGRP 当前用户组的其他用户拥有读权限
+\\         S_IWGRP 当前用户组的其他用户拥有写权限 
+\\         S_IXGRP 当前用户组的其他用户拥有执行权限 
+\\         S_IRWXG 当前用户组的其他用户拥有读、写、执行权限 
+其他用户   S_IROTH 其他用户拥有读权限 
+\\         S_IWOTH 其他用户拥有写权限 
+\\         S_IXOTH 其他用户拥有执行权限 
+\\         S_IROTH 其他用户拥有读、写、执行权限 
+========== ======= ========================================
 
-用户组           \        S_IWGRP 当前用户组的其他用户拥有写权限 \        S_IXGRP 当前用户组的其他用户拥有执行权限 \        S_IRWXG 当前用户组的其他用户拥有读、写、执行权限 其他用户 S_IROTH 其他用户拥有读权限 \
-S_IWOTH 其他用户拥有写权限 \        S_IXOTH 其他用户拥有执行权限 \        S_IROTH 其他用户拥有读、写、执行权限 其它     S_ISUID 设置文件所属的用户（UID）
 
-标志位           \        S_ISGID 设置文件所属的分组（GID） ======== ======= ========================================
 
 read函数
-''''''
+^^^^^^^^^
 
-#include <unistd.h>
+.. code-block:: sh
+   :linenos:
 
-ssize_t read(int fd, void \*buf, size_t count);
+   #include <unistd.h>
+   ssize_t read(int fd, void *buf, size_t count);
 
-read函数用于从文件中读取若干个字节的数据，保存到数据缓冲区buf中，并返回实际读取的字节数，具体函数参数如下：
+read函数用于从文件中读取若干个字节的数据，保存到数据缓冲区buf中，并返
+回实际读取的字节数，具体函数参数如下：
 
--  fd：文件对应的文件描述符，可以通过fopen函数获得。另外，当一个程序运行时，Linux默认有0、1、2这三个已经打开的文件描述符，分别对应了标准输入、标准输出、标准错误输出，即可以直接访问这三种文件描述符；
+-  fd：文件对应的文件描述符，可以通过fopen函数获得。另外，当一个程序
+   运行时，Linux默认有0、1、2这三个已经打开的文件描述符，分别对应了标准输入、标准输出、标准错误输出，即可以直接访问这三种文件描述符；
 
 -  buf：指向数据缓冲区的指针；
 
 -  count：读取多少个字节的数据。
 
 write函数
-'''''''
+^^^^^^^^^
 
-#include <unistd.h>
+.. code-block:: sh
+   :linenos:
 
-ssize_t write(int fd, const void \*buf, size_t count);
+   #include <unistd.h>
+   ssize_t write(int fd, const void *buf, size_t count);
 
 write函数用于往文件写入内容，并返回实际写入的字节长度，具体函数参数如下：
 
@@ -755,18 +802,25 @@ write函数用于往文件写入内容，并返回实际写入的字节长度，
 -  count：往文件中写入多少个字节。
 
 close函数
-'''''''
+^^^^^^^^^
+
+.. code-block:: sh
+   :linenos:
 
-int close(int fd);
+   int close(int fd);
 
 当我们完成对文件的操作之后，想要关闭该文件，可以调用close函数，来关闭该fd文件描述符对应的文件。
 
 lseek函数
-'''''''
+^^^^^^^^^
 
-lseek函数可以用与设置文件指针的位置，并返回文件指针相对于文件头的位置。其函数原型如下：
+lseek函数可以用与设置文件指针的位置，并返回文件指针相对于文件头
+的位置。其函数原型如下：
 
-off_t lseek(int fd, off_t offset, int whence);
+.. code-block:: sh
+   :linenos:
+
+   off_t lseek(int fd, off_t offset, int whence);
 
 它的用法与flseek一样，其中的offset参数用于指定位置，whence参数则定义了offset的意义，whence的可取值如下：
 
@@ -779,133 +833,112 @@ off_t lseek(int fd, off_t offset, int whence);
 .. _实验代码分析-1:
 
 实验代码分析
-^^^^^^
+~~~~~~~~~~~~~~~
 
 本节我们通过一个实验，来讲解如何使用对文件进行操作。
 
-代码清单 19‑3文件操作实验-系统调用（file_io/systemcall/main.c文件）
-
-1 #include <sys/stat.h>
 
-2 #include <unistd.h>
+.. code-block:: c
+   :caption: 文件操作实验-系统调用（base_code/linux_app/file_io/systemcall/main.c文件）
+   :linenos:
 
-3 #include <fcntl.h>
+   #include <sys/stat.h>
+   #include <unistd.h>
+   #include <fcntl.h>
+   #include <stdio.h>
+   #include <string.h>
 
-4 #include <stdio.h>
+   //文件描述符
+   int fd;
+   char str[100];
 
-5 #include <string.h>
 
-6
+   int main(void)
+   {
+      //创建一个文件
+      fd = open("testscript.sh", O_RDWR|O_CREAT|O_TRUNC, S_IRWXU);
+      //文件描述符fd为非负整数
+      if(fd < 0){
+         printf("Fail to Open File\n");
+         return 0;
+      }
+      //写入字符串pwd
+      write(fd, "pwd\n", strlen("pwd\n"));
 
-7 //文件描述符
+      //写入字符串ls
+      write(fd, "ls\n", strlen("ls\n"));
 
-8 int fd;
+      //此时的文件指针位于文件的结尾处，使用lseek函数使文件指针回到文件头
+      lseek(fd, 0, SEEK_SET);
 
-9 char str[100];
+      //从文件中读取100个字节的内容到str中，该函数会返回实际读到的字节数
+      read(fd, str, 100);
 
-10
+      printf("File content:\n%s \n", str);
 
-11
+      close(fd);
 
-12 int main(void)
-
-13 {
-
-14 //创建一个文件
-
-15 fd = open("testscript.sh", O_RDWR|O_CREAT|O_TRUNC, S_IRWXU);
-
-16 //文件描述符fd为非负整数
-
-17 if (fd < 0) {
-
-18 printf("Fail to Open File\n");
-
-19 return 0;
-
-20 }
-
-21 //写入字符串pwd
-
-22 write(fd, "pwd\n", strlen("pwd\n"));
-
-23
-
-24 //写入字符串ls
-
-25 write(fd, "ls\n", strlen("ls\n"));
-
-26
-
-27 //此时的文件指针位于文件的结尾处，使用lseek函数使文件指针回到文件头
-
-28 lseek(fd, 0, SEEK_SET);
-
-29
-
-30
-
-31 //从文件中读取100个字节的内容到str中，该函数会返回实际读到的字节数
-
-32 read(fd, str, 100);
-
-33
-
-34 printf("File content:\n%s \\n", str);
-
-35
-
-36 close(fd);
-
-37
-
-38 return 0;
-
-39 }
-
-40
+      return 0;
+   }
 
 执行流程
-''''
+^^^^^^^^^
 
-本实验与C库文件操作类似，也是创建文件、写入内容然后读出，不过此处使用的都是系统调用函数如open、write、lseek、read、close，具体说明如下：
+本实验与C库文件操作类似，也是创建文件、写入内容然后读出，不过此处使用
+的都是系统调用函数如open、write、lseek、read、close，具体说明如下：
 
--  代码中先调用了open函数以可读写的方式打开一个文本文件，并且O_CREAT指定如果文件不存在，则创建一个新的文件，文件的权限为S_IRWXU，即当前用户可读可写可执行，当前用户组和其他用户没有任何权限。
+-  代码中先调用了open函数以可读写的方式打开一个文本文件，并且O_CREAT指定
+   如果文件不存在，则创建一个新的文件，文件的权限为S_IRWXU，即当前用户可读
+   可写可执行，当前用户组和其他用户没有任何权限。
 
--  open与fopen的返回值功能类似，都是文件描述符，不过open使用非负整数来表示正常，失败时返回-1，而fopen失败时返回NULL。
+-  open与fopen的返回值功能类似，都是文件描述符，不过open使用非负整数
+   来表示正常，失败时返回-1，而fopen失败时返回NULL。
 
--  创建文件后调用write函数写入了“pwd\n”、“ls\n”这样的字符串，实际上就是简单的Shell命令。
+-  创建文件后调用write函数写入了"pwd\n"、"ls\n"这样的字符串，实际上就是简单的Shell命令。
 
--  使用read函数读取内容前，先调用lseek函数重置了文件指针至文件开头处读取。与C库文件操作的区别write和read之间不需要使用fflush确保缓冲区的内容并写入，因为系统调用的文件操作是没有缓冲区的。
+-  使用read函数读取内容前，先调用lseek函数重置了文件指针至文件开头处读取。与C库文件
+   操作的区别write和read之间不需要使用fflush确保缓冲区的内容并写入，因为系统调用的文件操作是没有缓冲区的。
 
 -  最后关闭文件，释放文件描述符。
 
 头文件目录
-'''''
+^^^^^^^^^^^
 
-示例代码中的开头包含了一系列Linux系统常用的头文件。今后学习Linux的过程中，我们可能会接触各种各样的头文件，因此了解一下Linux中头文件的用法十分有必要。
+示例代码中的开头包含了一系列Linux系统常用的头文件。今后学习Linux的过程中，我们可能会接触各种
+各样的头文件，因此了解一下Linux中头文件的用法十分有必要。
 
-在linux中，大部分的头文件在系统的“/usr/include”目录下可以找到，它是系统自带的GCC编译器默认的头文件目录，如图 19‑12，如果把该目录下的stdio.h文件删除掉或更改名字（想尝试请备份，我不负责），那么使用GCC编译hello
+在linux中，大部分的头文件在系统的"/usr/include"目录下可以找到，它是
+系统自带的GCC编译器默认的头文件目录，如下图所示，如果把该目录下的stdio.h文件删除
+掉或更改名字（想尝试请备份），那么使用GCC编译hello
 world的程序会因为找不到stdio.h文件而报错。
 
-|filesy013|
+.. image:: media/filesy013.png
+   :align: center
+   :alt: 未找到图片13|
+
+
+代码中一些头文件前包含了某个目录，比如sys/stat.h，这些头文件
+可以在编译器文件夹中的目录下找到。我们通常可以使用locate命令来搜索，如：
 
-图 19‑12 系统中的头文件源码
+.. code-block:: sh
+   :linenos:
 
-代码中一些头文件前包含了某个目录，比如sys/stat.h，这些头文件可以在编译器文件夹中的目录下找到。我们通常可以使用locate命令来搜索，如：
+   #在Ubuntu主机下执行如下命令：
+   locate sys/stat.h
 
-#在Ubuntu主机下执行如下命令：
+如下图:
 
-locate sys/stat.h
+.. image:: media/filesy014.png
+   :align: center
+   :alt: 未找到图片14|
 
-|filesy014|
 
-图 19‑13 查看sys/stat.h的位置
 
-在图 19‑13中我们查找出sys/stat.h存在三个位置，这是因为示例的主机安装了三个版本的编译器，每个编译器都有自己的头文件，编译器运行时默认是采用自己目录下的头文件编译的。
+在上图中我们查找出sys/stat.h存在三个位置，这是因为示例的主机安装
+了三个版本的编译器，每个编译器都有自己的头文件，编译器运行时默认是采用自己目录下的头文件编译的。
 
 常用头文件
-'''''
+^^^^^^^^^^^
 
 在后面的学习中我们常常会用到以下头文件，此处进行简单说明，若想查看具体的头文件内容，使用locate命令找到该文件目录后打开即可：
 
@@ -913,9 +946,11 @@ locate sys/stat.h
 
 -  头文件stdlib.h：C标准库（standard library）头文件，该文件包含了常用的malloc函数、free函数。
 
--  头文件sys/stat.h：包含了关于文件权限定义，如S_IRWXU、S_IWUSR，以及函数fstat用于查询文件状态。涉及系统调用文件相关的操作，通常都需要用到sys/stat.h文件。
+-  头文件sys/stat.h：包含了关于文件权限定义，如S_IRWXU、S_IWUSR，以
+   及函数fstat用于查询文件状态。涉及系统调用文件相关的操作，通常都需要用到sys/stat.h文件。
 
--  头文件unistd.h：UNIX C标准库头文件，unix，linux系列的操作系统相关的C库，定义了unix类系统POSIX标准的符号常量头文件，比如Linux标准的输入文件描述符（STDIN），标准输出文件描述符（STDOUT），还有read、write等系统调用的声明。
+-  头文件unistd.h：UNIX C标准库头文件，unix，linux系列的操
+   作系统相关的C库，定义了unix类系统POSIX标准的符号常量头文件，比如Linux标准的输入文件描述符（STDIN），标准输出文件描述符（STDOUT），还有read、write等系统调用的声明。
 
 -  头文件fcntl.h：unix标准中通用的头文件，其中包含的相关函数有 open，fcntl，close等操作。
 
@@ -924,80 +959,90 @@ locate sys/stat.h
 .. _编译及测试-1:
 
 编译及测试
-^^^^^
+~~~~~~~~~~~~
 
 本实验使用的Makefile与上一小节的完全一样，不再分析。
 
 .. _x86架构-1:
 
 x86架构
-'''''
+^^^^^^^^^^^
 
 本实验支持x86和ARM架构，在x86上的编译及测试命令如下：
 
-#在主机的实验代码Makefile目录下编译
+.. code-block:: sh
+   :linenos:
 
-#默认编译x86平台的程序
+   #在主机的实验代码Makefile目录下编译
+   #默认编译x86平台的程序
+   make
+   tree
+   #运行
+   ./build_x86/file_demo
+   #程序运行后本身有输出，并且创建了一个文件
+   ls
+   #查看文件的内容
+   cat testsript.sh
+   #执行生成的testscript.sh文件
+   ./testscript.sh
 
-make
+如下图:
 
-tree
+.. image:: media/filesy015.png
+   :align: center
+   :alt: 未找到图片15|
 
-#运行
 
-./build_x86/file_demo
 
-#程序运行后本身有输出，并且创建了一个文件
-
-ls
-
-#查看文件的内容
-
-cat testsript.sh
-
-#执行生成的testscript.sh文件
-
-./testscript.sh
-
-|filesy015|
-
-图 19‑14 文件操作实验-系统调用
-
-从图 19‑14可看到，file_demo程序执行后，它创建的testscript.sh文件带有可执行权限，这是使用C库函数fopen无法直接做到的。运行testscript.h可执行该文件内记录的Shell指令。
+从上图可看到，file_demo程序执行后，它创建的testscript.sh文件带有
+可执行权限，运行./testscript.sh可执行该脚本。
 
 .. _arm架构-1:
 
 ARM架构
-'''''
+^^^^^^^^^^^
 
 对于ARM架构的程序，可使用如下步骤进行编译：
 
-#在主机的实验代码Makefile目录下编译
+.. code-block:: sh
+   :linenos:
 
-#编译arm平台的程序
+   #在主机的实验代码Makefile目录下编译
+   #编译arm平台的程序
+   make ARCH=arm
 
-make ARCH=arm
+编译后生成的ARM平台程序为build_arm/file_demo，使用网络文件系统共享
+至开发板，在开发板的终端上测试即可。
 
-编译后生成的ARM平台程序为build_arm/file_demo，使用网络文件系统共享至开发板，在开发板的终端上测试即可。
+如下图:
+
+.. image:: media/filesy016.png
+   :align: center
+   :alt: 未找到图片16|
 
-|filesy016|
 
-图 19‑15 在开发板上的执行现象
 
 如何决择
-~~~~
+~~~~~~~~~~~~
 
 既然C标准库和系统调用都能够操作文件，那么应该选择哪种操作呢？考虑的因素如下：
 
--  使用系统调用会影响系统的性能。执行系统调用时，Linux需要从用户态切换至内核态，执行完毕再返回用户代码，所以减少系统调用能减少这方面的开销。如库函数写入数据的文件操作fwrite最后也是执行了write系统调用，如果是写少量数据的话，直接执行write可能会更高效，但如果是频繁的写入操作，由于f
-  write的缓冲区可以减少调用write的次数，这种情况下使用fwrite能更节省时间。
+-  使用系统调用会影响系统的性能。执行系统调用时，Linux需要从用
+   户态切换至内核态，执行完毕再返回用户代码，所以减少系统调用能减
+   少这方面的开销。如库函数写入数据的文件操作fwrite最后也是执行了write系统
+   调用，如果是写少量数据的话，直接执行write可能会更高效，但如果是频繁的写入操作，由于f
+   write的缓冲区可以减少调用write的次数，这种情况下使用fwrite能更节省时间。
 
--  硬件本身会限制系统调用本身每次读写数据块的大小。如针对某种存储设备的write函数每次可能必须写4kB的数据，那么当要写入的实际数据小于4kB时，write也只能按4kB写入，浪费了部分空间，而带缓冲区的fwrite函数面对这种情况，会尽量在满足数据长度要求时才执行系统调用，减少空间开销。
+-  硬件本身会限制系统调用本身每次读写数据块的大小。如针对某种存
+   储设备的write函数每次可能必须写4kB的数据，那么当要写入的实际数据小于4kB时，write也只能
+   按4kB写入，浪费了部分空间，而带缓冲区的fwrite函数面对这种情况，会尽量在满足数据长度要求时才执行系统调用，减少空间开销。
 
--  也正是由于库函数带缓冲区，使得我们无法清楚地知道它何时才会真正地把内容写入到硬件上，所以在需要对硬件进行确定的控制时，我们更倾向于执行系统调用。
+-  也正是由于库函数带缓冲区，使得我们无法清楚地知道它何时才会真正地把内容写入到硬件上，所以在需
+   要对硬件进行确定的控制时，我们更倾向于执行系统调用。
 
 下一小节我们将使用库函数和系统调用的文件操作方式控制LED灯，演示这两种方式的差异。
 
+
 .. |filesy002| image:: media/filesy002.png
    :width: 5.76806in
    :height: 0.86988in
diff --git a/documentation/linux_app/gcc_hello_world.rst b/documentation/linux_app/gcc_hello_world.rst
index 5ade2b392f01b6e2ecf32de6113cd872cd35543f..d21ff1e914db7ef754f5b8185f23930a1634bba7 100644
--- a/documentation/linux_app/gcc_hello_world.rst
+++ b/documentation/linux_app/gcc_hello_world.rst
@@ -21,7 +21,7 @@ IDE的一个特点是它把各种常用操作封装成图形界面供用户使
 了解程序的链接过程有利于明白为什么某些程序需要
 依赖特定的文件，从而方便专门定制Linux文件系统。
 
-本章的示例代码目录为：base_code/section2/hello_c。
+本章的示例代码目录为：base_code/linux_app/hello_c。
 
 GCC编译工具链
 ~~~~~~~~~~~~~~~~~~~~~~~~
@@ -40,12 +40,12 @@ GCC编译器
 ^^^^^^^^^^^^^^^^^^^^^^^^
 
 GCC（GNU Compiler Collection）是由 GNU 开发的编程语言编译器。
-GCC最初代表“GNU C Compiler”，当时只支持C语言。
+GCC最初代表"GNU C Compiler"，当时只支持C语言。
 后来又扩展能够支持更多编程语言，包括 C++、Fortran 和 Java 等。
-因此，GCC也被重新定义为“GNU Compiler Collection”，成为历史上最优秀的编译器，
+因此，GCC也被重新定义为"GNU Compiler Collection"，成为历史上最优秀的编译器，
 其执行效率与一般的编译器相比平均效率要高 20%~30%。
 
-GCC的官网地址为：https://gcc.gnu.org/，在Ubuntu系统下系统默认已经安装好GCC编译器，可以通过如下命令查看GCC编译器的版本及安装路径：
+GCC的官网地址为：https://gcc.gnu.org/，在Ubuntu系统下系统默认已经安装好GCC编译器，可以通过如下命令查看Ubuntu系统中GCC编译器的版本及安装路径：
 
 ::
 
@@ -53,28 +53,23 @@ GCC的官网地址为：https://gcc.gnu.org/，在Ubuntu系统下系统默认已
       gcc -v          #查看gcc编译器版本
       which gcc       #查看gcc的安装路径
 
-      #若系统没有gcc编译器，可以直接通过如下命令安装
-      #该指令执行后通常会直接安装包含gcc、binutils工具
-      sudo apt install gcc
-
-
 .. image:: media/gcchel002.png
    :align: center
    :alt: 系统自带的GCC编译器
 
 图中的两处信息说明如下：
 
-- “Target:x86_64-linux-gnu”表示该GCC的目标平台为x86_64架构（Intel、AMD的CPU），
+- "Target:x86_64-linux-gnu"表示该GCC的目标平台为x86_64架构（Intel、AMD的CPU），
   表示它编译生成的应用程序只适用于x86架构，不适用于ARM开发板平台。
 
-- “gcc version 7.4.0”表明该GCC的版本为7.4.0，部分程序可能会对编译器版本有要求，
+- "gcc version 7.4.0"表明该GCC的版本为7.4.0，部分程序可能会对编译器版本有要求，
   不过我们演示使用的应用程序比较简单，兼容性好，一开始可以不用在乎这个，
   而编译指定版本的uboot、Linux内核的时候可能会对GCC有版本要求。
 
 Binutils工具集
 ^^^^^^^^^^^^^^^^^^^^^^
 
-Binutils（bin utility），是GNU二进制工具集，通常跟GCC编译器一起打包安装到系统，它的官方说明网站地址为：\ https://www.gnu.org/software/binutils/\ 。
+Binutils（bin utility），是GNU二进制工具集，通常跟GCC编译器一起打包安装到系统，它的官方说明网站地址为： https://www.gnu.org/software/binutils/ 。
 
 在进行程序开发的时候通常不会直接调用这些工具，而是在使用GCC编译指令的时候由GCC编译器间接调用。下面是其中一些常用的工具：
 
@@ -96,7 +91,7 @@ Binutils（bin utility），是GNU二进制工具集，通常跟GCC编译器一
 
 ::
 
-      #在主机上执行如下命令
+      #在Ubantu上执行如下命令
       ls /usr/bin/ | grep linux-gnu-
 
 .. image:: media/gcchel003.png
@@ -115,7 +110,7 @@ glibc库是GNU组织为GNU系统以及Linux系统编写的C语言标准库，因
 
 ::
 
-      #在主机上执行如下命令
+      #在Ubantu上执行如下命令
       #以下是Ubuntu 64位机的glibc库文件路径，可直接执行
       /lib/x86_64-linux-gnu/libc.so.6
 
@@ -130,11 +125,12 @@ glibc库是GNU组织为GNU系统以及Linux系统编写的C语言标准库，因
 则可以直接研究glibc的源代码，甚至加入开发社区贡献自己的代码，glibc的官网地址为：
 https://www.gnu.org/software/libc/ ，可在该网站中下载源代码来学习。
 
-Linux下的Hello World程序
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
 为了更直观地感受GCC编译工具，请跟着以下的步骤来打开新世界的大门吧。
 
+X86_64平台、Ubuntu系统下的HelloWorld
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
 创建工作目录
 ^^^^^^^^^^^^^^^^^^^^^^^^
 
@@ -143,7 +139,7 @@ Linux下的Hello World程序
 
 ::
 
-      #在主机上执行如下命令
+      #在Ubantu上执行如下命令
       mkdir -p ~/workdir/example/hello_c #创建hello_c目录
 
 编写代码文件
@@ -162,12 +158,12 @@ Linux下的Hello World程序
 编译并执行
 ^^^^^^^^^^^^^^^^^^^^
 
-编写好程序后，立马进行编译体验一下，请尝试执行以下命令：
+Ubuntu默认安装GCC编译工具链，写好程序后可以直接进行编译，请尝试执行以下命令：
 
 
 ::
 
-      #在主机的hello_c目录下执行如下命令
+      #在Ubantu的hello_c目录下执行如下命令
       gcc hello.c –o hello #使用gcc把hello.c编译成hello程序
 
       ls        #查看目录下的文件
@@ -176,17 +172,97 @@ Linux下的Hello World程序
       #若提示权限不够或不是可执行文件，执行如下命令再运行hello程序
       chmod u+x hello #给hello文件添加可执行权限
 
+如下图:
+
 .. image:: media/gcchel005.png
    :align: center
    :alt: GCC编译结果
 
 如图所示，执行gcc编译命令后看到目录下生成了一个可执行文件hello，
-然后通过“./”符号加上程序的名字即可运行，此处的“.”表示当前目录，
+然后通过"./"符号加上程序的名字即可运行，此处的"."表示当前目录，
 所以当我们想运行一个可执行程序的时候，输出它的路径名即可执行。
 hello程序运行时代码中printf的内容直接输出到了终端。
 
-这就是在Linux下使用GCC开发简单C应用程序并运行的基本流程，
-下面我们针对GCC编译过程进行讲解。
+
+ARM平台、Debian系统下的HelloWorld
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+安装GCC编译工具链
+^^^^^^^^^^^^^^^^^^^^^^^^
+
+野火提供的Debian系统镜像默认不带gcc编译器，开发板启动以后，执行以下命令安装GCC编译工具链
+
+::
+
+      sudo apt install gcc -y
+
+如下图:
+
+.. image:: media/gcchel011.png
+   :align: center
+   :alt: GCC安装编译工具链
+
+GCC工具链包括了binutils、readelf工具,因此GCC安装完成后，binutils、readelf等工具也可以直接使用。
+
+运行以下指令查看GCC版本与安装路径。
+
+::
+
+
+      gcc -v          #查看gcc编译器版本
+      which gcc       #查看gcc的安装路径
+
+如下图:
+
+.. image:: media/gcchel012.png
+   :align: center
+   :alt: Debian GCC
+
+与前面介绍的Ubuntu中GCC不一样的是，开发板中gcc编译工具链的目标平台是arm架构的，表示它生成的应用程序只能运行于ARM平台的开发板，
+而不适合用于X86平台。
+
+创建工作目录
+^^^^^^^^^^^^^^^^^^^^^^^^
+
+先在当前用户下创建一个本章节使用的工作目录workdir/example/hello_c。
+
+::
+
+      #在Debian上执行如下命令
+      mkdir -p ~/workdir/example/hello_c #创建hello_c目录
+
+编写代码文件
+^^^^^^^^^^^^^^^^^^
+
+使用编辑器新建一个名为hello.c的文件，输入如下面的示例代码并保存至hello_c目录下。
+
+.. literalinclude:: ../../base_code/linux_app/hello_c/hello.c
+   :caption: ../../base_code/linux_app/hello_c/hello.c
+   :language: c
+   :linenos:
+
+编译并执行
+^^^^^^^^^^^^^^^^^^^^
+::
+
+      #在Debian的hello_c目录下执行如下命令
+      gcc hello.c –o hello #使用gcc把hello.c编译成hello程序
+
+      ls        #查看目录下的文件
+      ./hello   #执行生成的hello程序
+
+      #若提示权限不够或不是可执行文件，执行如下命令再运行hello程序
+      chmod u+x hello #给hello文件添加可执行权限
+
+如下图:
+
+.. image:: media/gcchel013.png
+   :align: center
+   :alt: GCC编译结果
+
+运行结果与前面X86_64、Ubantu系统的HelloWorld执行结果一致。
+
+**这就是在Linux下使用GCC开发简单C应用程序并运行的基本流程，下面我们针对GCC编译过程进行讲解。**
 
 GCC编译过程
 ~~~~~~~~~~~~~~~~~~~~~
@@ -200,7 +276,7 @@ gcc [选项] 输入的文件名
 
 常用选项：
 
--  -o：小写字母“o”，指定生成的可执行文件的名字，不指定的话生成的可执行文件名为a.out。
+-  -o：小写字母"o"，指定生成的可执行文件的名字，不指定的话生成的可执行文件名为a.out。
 
 -  -E：只进行预处理，既不编译，也不汇编。
 
@@ -210,21 +286,20 @@ gcc [选项] 输入的文件名
 
 -  -g：生成的可执行文件带调试信息，方便使用gdb进行调试。
 
--  -Ox：大写字母“O”加数字，设置程序的优化等级，如“-O0”“-O1” “-O2” “-O3”，
+-  -Ox：大写字母"O"加数字，设置程序的优化等级，如"-O0""-O1" "-O2" "-O3"，
    数字越大代码的优化等级越高，编译出来的程序一般会越小，但有可能会导致程序不正常运行。
 
 编译过程
 """""""""""""""""
+若不了解程序的编译过程，那么GCC的编译选项会让人一头雾水。下面以X86_64平台下Ubuntu的编译过程为例进行初步讲解，
+ARM平台下Debian的编译过程也是类似的，不再进行分析。
 
-若不了解程序的编译过程，那么GCC的编译选项会让人一头雾水，
-除了-g和-Ox选项，其它选项实际上都是编译的分步骤，即只进行某些编译过程。
-
-也就是说，前面演示编译hello.c程序的过程，跟以下内容是等价的：
+GCC编译选项除了-g和-Ox选项，其它选项实际上都是编译的分步骤，即只进行某些编译过程。
 
 ::
 
       #直接编译成可执行文件
-      gcc -o hello
+      gcc hello.c -o hello
 
       #以上命令等价于执行以下全部操作
       #预处理，可理解为把头文件的代码汇总成C代码，把*.c转换得到*.i文件
@@ -265,7 +340,7 @@ GCC 编译工具链在编译一个C源文件时需要经过以下 4 步：
 预处理阶段
 ^^^^^^^^^^^^^^^^^^^^
 
-使用GCC的参数“-E”，可以让编译器生成.i文件，参数“-o”，可以指定输出文件的名字。
+使用GCC的参数"-E"，可以让编译器生成.i文件，参数"-o"，可以指定输出文件的名字。
 
 具体执行命令如下：
 
@@ -317,8 +392,8 @@ GCC 编译工具链在编译一个C源文件时需要经过以下 4 步：
    # 27 "/usr/include/x86_64-linux-gnu/bits/types.h" 3 4
    # 1 "/usr/include/x86_64-linux-gnu/bits/wordsize.h" 1 3 4
    # 28 "/usr/include/x86_64-linux-gnu/bits/types.h" 2 3 4
-   typedef unsigned char \__u_char;
-   typedef unsigned short int \__u_short;
+   typedef unsigned char __u_char;
+   typedef unsigned short int __u_short;
 
    ...中间省略部分内容...
 
@@ -332,7 +407,7 @@ GCC 编译工具链在编译一个C源文件时需要经过以下 4 步：
    return 0;
    }
 
-文件中以“#”开头的是注释，可看到有非常多的类型定义、函数声明被加入到文件中，
+文件中以"#"开头的是注释，可看到有非常多的类型定义、函数声明被加入到文件中，
 这些就是预处理阶段完成的工作，相当于它把原C代码中包含的头文件中引用的内容汇总到一处。
 如果原C代码有宏定义，还可以更直观地看到它把宏定义展开成具体的内容（如宏定义代表的数字）。
 
@@ -389,7 +464,7 @@ GCC可以使用-S选项，让编译程序生成汇编语言的代码文件（.s
 汇编阶段
 ^^^^^^^^^^^^^^^^
 
-GCC的参数“c”表示只编译(compile)源文件但不链接，会将源程序编译成目标文件（.o后缀）。计算机只认识0或者1，不懂得C语言，也不懂得汇编语言，经过编译汇编之后，生成的目标文件包含着机器代码，这部分代码就可以直接被计算机执行。一般情况下，可以直接使用参数“c”，跳过上述的两个过程，具体命令
+GCC的参数"c"表示只编译(compile)源文件但不链接，会将源程序编译成目标文件（.o后缀）。计算机只认识0或者1，不懂得C语言，也不懂得汇编语言，经过编译汇编之后，生成的目标文件包含着机器代码，这部分代码就可以直接被计算机执行。一般情况下，可以直接使用参数"c"，跳过上述的两个过程，具体命令
 如下：
 
 ::
@@ -400,7 +475,7 @@ GCC的参数“c”表示只编译(compile)源文件但不链接，会将源程
       #也可以直接以C文件作为输入进行汇编，与上面的命令是等价的
       gcc –c hello.c –o hello.o
 
-\*.o是为了让计算机阅读的，所以不像前面生成的\*.i和\*.s文件直接使用字符串来记录，
+*.o是为了让计算机阅读的，所以不像前面生成的*.i和*.s文件直接使用字符串来记录，
 如果直接使用编辑器打开，只会看到乱码，如下图。
 
 .. image:: media/gcchel007.png
@@ -408,8 +483,8 @@ GCC的参数“c”表示只编译(compile)源文件但不链接，会将源程
    :alt: 直接使用VS Code打开*.o文件的提示
 
 
-Linux下生成的\*.o目标文件、\*.so动态库文件以及下一小节链接阶段生成最终的可执行文件都是elf格式的，
-可以使用“readelf”工具来查看它们的内容。
+Linux下生成的*.o目标文件、*.so动态库文件以及下一小节链接阶段生成最终的可执行文件都是elf格式的，
+可以使用"readelf"工具来查看它们的内容。
 
 请亲自尝试执行如下命令：
 
@@ -448,7 +523,7 @@ Linux下生成的\*.o目标文件、\*.so动态库文件以及下一小节链接
    hello程序执行时调用库文件*.so中的内容，不同的程序可以共用代码库。
    所以动态链接生成的程序比较小，占用较少的内存。
 
--  静态链接，链接时使用选项“--static”，它在编译阶段就会把所有用到的库打包到自己的可执行程序中。
+-  静态链接，链接时使用选项"--static"，它在编译阶段就会把所有用到的库打包到自己的可执行程序中。
    所以静态链接的优点是具有较好的兼容性，不依赖外部环境，但是生成的程序比较大。
 
 请尝试执行如下命令体验静态链接与动态链接的区别：
diff --git a/documentation/linux_app/git_use.rst b/documentation/linux_app/git_use.rst
new file mode 100644
index 0000000000000000000000000000000000000000..284ccbe5200e9a9131511d6387368d68c87210e9
--- /dev/null
+++ b/documentation/linux_app/git_use.rst
@@ -0,0 +1,115 @@
+.. vim: syntax=rst
+
+
+项目资料下载
+------------------
+
+本项目通过Git开源，用户可以在GitHub和Gitee下载本项目相关源码：
+
+- GitHub仓库地址：https://github.com/Embdefire/embed_linux_tutorial
+- Gitee 仓库地址：https://gitee.com/wildfireteam/embed_linux_tutorial
+
+Git是什么
+~~~~~~~~~~~~~~~~~~
+
+Git是一个功能十分强大的分布式版本控制系统，主要用于高效地对各种各样的项目进行版本管理。
+
+Git的诞生，起源于linux社区的一位大牛Andrew(samba之父)写了可连接BitKeeper仓库的外挂，
+这引起了BitMover 公司的震怒，收回了对linux社区免费使用BitKeeper的授权。于是Linux之父，
+Torvalds，花了十天时间为Linux社区开发了新的版本工具--Git。
+
+Git的特点
+~~~~~~~~~~~~~~~~~~
+
+相较于其他版本管理工具，Git有以下几个优点:
+
+- 快照记录。git和其他版本管理工具重要差别在于存储数据的方式。
+  其他版本工具通常将它们保存的信息看作是一种原始数据+文件修改的记录。
+  而Git在储存时是生成快照来记录全部文件（快照不是所有文件的单纯拷贝，而是一种对全体文件的索引）。
+
+- 分布式。每一位项目开发人员的电脑里，都有项目的完成备份，避免造成资料受损无法挽回的后果。
+  同时，本地的项目备份使得所有的版本管理操作都在毫秒级别内完成。
+  这与SVN、CVS等集中式版本工具时常要等待中央服务器响应相比,用户体验显得非常好。
+
+- 开源。这与linux内核一样，开放源码保证了Git的可靠性和安全性，也有利于Git的功能越来越强大。
+
+
+Git与GitHub、Gitee
+~~~~~~~~~~~~~~~~~
+
+GitHub和Gitee是一个基于Git的在线项目托管平台,它提供了web界面,用户可以在上面创建远程仓库来存放自己的项目。
+所有的开发者可以基于这个远程仓库共同协作，不断地维护和完善该项目。
+
+使用Git下载项目资料
+~~~~~~~~~~~~~~~~~
+
+安装Git
+^^^^^^^^^^^^
+
+**Windows系统**
+
+到Git官网下载安装包,直接安装即可。
+
+https://gitforwindows.org
+
+
+**Linux系统**
+
+根据不同发行版，使用相关包管理工具安装即可。
+
+比如Ubantu：在终端执行"sudo apt-get install git -y"即可。
+
+获取项目仓库地址
+^^^^^^^^^^^^^^^^^^^^^
+
+1、在GitHub或者Gitee网站上，找到需要下载的项目，复制该项目的克隆链接。
+如下图:
+
+GitHub仓库地址
+
+.. image:: media/github_url.png
+   :align: center
+   :alt: 未找到图片
+
+Gitee仓库地址
+
+.. image:: media/gitee_url.png
+   :align: center
+   :alt: 未找到图片
+
+下载项目
+^^^^^^^^^^^^^^^^^^^^^
+
+下面以Windows系统为例，linux系统的操作是类似的。
+
+1、windows安装完Git后，.在将要下载项目的目录中，右键选择"Git Bash Here"项，
+打开git bash命令工具。
+
+如下图:
+
+.. image:: media/git_bash.png
+   :align: center
+   :alt: 未找到图片
+
+2、在git bash命令工具运行:"git clone +"仓库地址""命令，进行项目下载。
+本项目在GitHub的仓库地址为:https://github.com/Embdefire/embed_linux_tutorial。
+因此要运行的命令为:
+
+.. code-block:: sh
+   :linenos:
+
+    git clone https://github.com/Embdefire/embed_linux_tutorial
+
+如下图:
+
+.. image:: media/git_clone.png
+   :align: center
+   :alt: 未找到图片
+
+
+3、等待项目下载完毕,注意:GitHub网速在国内受限，可能会出现多次下载失败的现象。
+
+
+
+4、项目下载完毕后，在项目目录下的base_code文件夹存放了所有实验的相关代码，用户可根据实际需要进行查阅使用。
+
diff --git a/documentation/linux_app/gpio_subsystem.rst b/documentation/linux_app/gpio_subsystem.rst
index 8653e1b35b5d614e3d5c773dba97c0e39f1cde6d..056af835df206201eac2e3b8e68139341815a5a5 100644
--- a/documentation/linux_app/gpio_subsystem.rst
+++ b/documentation/linux_app/gpio_subsystem.rst
@@ -5,14 +5,14 @@
 
 本章讲解Linux GPIO子系统驱动相关应用层程序的控制原理。
 
-本章的示例代码目录为：base_code/section2/beep。
+本章的示例代码目录为：base_code/linux_app/beep。
 
 GPIO子系统
 ~~~~~~~
 
 GPIO是General Purpose I/O的缩写，即通用输入输出端口，简单来说就是MCU/CPU可控制的引脚，这些引脚通常有多种功能，最基本的是高低电平输入检测和输出，部分引脚还会与主控器的片上外设绑定，如作为串口、I2C、网络、电压检测的通讯引脚。
 
-与LED子系统类似，Linux提供了GPIO子系统驱动框架，使用该驱动框架可以把CPU的GPIO引脚导出到用户空间，用户通过访问/sys文件系统进行控制，GPIO子系统支持把引脚用于基本的输入输出功能，其中输入功能还支持中断检测。在Linux内核源码的“Documentation/gpio”目录可找
+与LED子系统类似，Linux提供了GPIO子系统驱动框架，使用该驱动框架可以把CPU的GPIO引脚导出到用户空间，用户通过访问/sys文件系统进行控制，GPIO子系统支持把引脚用于基本的输入输出功能，其中输入功能还支持中断检测。在Linux内核源码的"Documentation/gpio"目录可找
 到关于GPIO子系统的说明。
 
 通过GPIO子系统可以控制LED、蜂鸣器以及按键检测这类硬件设备，不过由于本开发板出厂的默认镜像中，LED灯使用了LED子系统驱动控制，按键使用了input输入子系统驱动控制，不方便在用户空间使用GPIO的方式进行实验，而蜂鸣器在驱动层中我们是使用GPIO子系统的，本章选择蜂鸣器作为示例讲解。
@@ -22,72 +22,76 @@ GPIO是General Purpose I/O的缩写，即通用输入输出端口，简单来说
 GPIO设备目录
 ^^^^^^^^
 
-GPIO驱动子系统导出到用户空间的目录是“/sys/class/gpio”。
+GPIO驱动子系统导出到用户空间的目录是"/sys/class/gpio"。
 
 可使用如下命令查看：
 
-#在主机或开发板的终端使用以下命令查看
+.. code-block:: sh
+   :linenos:
 
-ls -lh /sys/class/gpio
+   #在主机或开发板的终端使用以下命令查看
+   ls -lh /sys/class/gpio
 
-#以下命令不支持在Ubuntu主机上运行
+   #以下命令不支持在Ubuntu主机上运行
+   #导出GPIO到用户空间
+   echo 19 > /sys/class/gpio/export
+   #查看目录的变化，增加了gpio19目录
+   ls /sys/class/gpio/
+   #把gpio19从用户空间中取消导出
+   echo 19 > /sys/class/gpio/unexport
+   #查看目录变化，gpio19目录消失了
+   ls /sys/class/gpio/
 
-#请在开发板的终端上执行如下命令：
+如下图:
 
-#请在开发板的终端上执行如下命令：
+.. image:: media/gpiosu002.png
+   :align: center
+   :alt: 未找到图片2|
 
-#导出GPIO到用户空间
 
-echo 19 > /sys/class/gpio/export
 
-#查看目录的变化，增加了gpio19目录
+.. image:: media/gpiosu003.png
+   :align: center
+   :alt: 未找到图片3|
 
-ls /sys/class/gpio/
 
-#把gpio19从用户空间中取消导出
-
-echo 19 > /sys/class/gpio/unexport
-
-#查看目录变化，gpio19目录消失了
-
-ls /sys/class/gpio/
-
-|gpiosu002|
-
-图 21‑1 Ubuntu主机上的/sys/class/gpio目录内容
-
-|gpiosu003|
-
-图 21‑2在开发板上的/sys/class/gpio目录
 
 该目录下的主要内容说明如下：
 
--  export文件：导出GPIO，该文件只能写不能读，用户向该文件写入GPIO的编号N可以向内核申请将该编号的GPIO导出到用户空间，若内核本身没有把该GPIO用于其它功能，那么在/sys/class/gpio目录下会新增一个对应编号的gpioN目录，如图 21‑2导出了gpio19。
+-  export文件：导出GPIO，该文件只能写不能读，用户向该文件写
+   入GPIO的编号N可以向内核申请将该编号的GPIO导出到用户空间，若内核本
+   身没有把该GPIO用于其它功能，那么在/sys/class/gpio目录下会新增一
+   个对应编号的gpioN目录，如上图一导出了gpio19。
 
--  unexport文件：export的相反操作，取消导出GPIO，该文件同样只能写不能读。图 21‑2演示了往unexport写入19后，gpio19目录消失了。
+-  unexport文件：export的相反操作，取消导出GPIO，该文件同样只能
+   写不能读。上图演示了往unexport写入19后，gpio19目录消失了。
 
 -  gpiochipX目录：该目录是指GPIO控制器外设，Ubuntu主机上默认没有这样的功能。
 
--  gpioN目录：通过export导出的具体GPIO引脚的控制目录，如图 21‑2中的gpio19目录下会包含有控制该引脚的相应文件。
+-  gpioN目录：通过export导出的具体GPIO引脚的控制目录，如上图中的gpio19目录下会包含有
+   控制该引脚的相应文件。
 
 GPIO设备属性
-^^^^^^^^
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 
 gpioN目录下相关的设备文件，可以使用以下命令查看：
 
-#在开发板的终端使用以下命令
-
-#导出编号为19的GPIO
+.. code-block:: sh
+   :linenos:
 
-echo 19 > /sys/class/gpio/export
+   #在开发板的终端使用以下命令
+   #导出编号为19的GPIO
+   echo 19 > /sys/class/gpio/export
+   #查看gpio19目录下的内容
+   ls -lh /sys/class/gpio/gpio19
 
-#查看gpio19目录下的内容
+如下图:
 
-ls -lh /sys/class/gpio/gpio19
+.. image:: media/gpiosu004.png
+   :align: center
+   :alt: 未找到图片4|
 
-|gpiosu004|
 
-图 21‑3 gpioN目录下的内容
 
 常用的属性文件介绍如下：
 
@@ -101,9 +105,11 @@ ls -lh /sys/class/gpio/gpio19
 
 -  high：引脚为输出模式，且默认输出电平为高。
 
--  value文件：表示GPIO的电平，1表示高电平，0表示低电平。GPIO被配置为输出模式， 那么修改该文件的内容可以改变引脚的电平。
+-  value文件：表示GPIO的电平，1表示高电平，0表示低电平。GPIO被配置为输出
+   模式， 那么修改该文件的内容可以改变引脚的电平。
 
--  edge文件：用于配置GPIO的中断触发方式，当GPIO被配置为中断时，可以通过系统的poll函数监听。edge文件可取如下的属性值：
+-  edge文件：用于配置GPIO的中断触发方式，当GPIO被配置为中断时，可以通过系统
+   的poll函数监听。edge文件可取如下的属性值：
 
 -  none：没有使用中断模式。
 
@@ -113,25 +119,37 @@ ls -lh /sys/class/gpio/gpio19
 
 -  both：表示引脚为中断输入模式，边沿触发。
 
-与LED子系统不同，当某个引脚被用于具体的LED设备时，该引脚会被设备占用，它的功能在用户空间是无法再被修改的，而使用GPIO子系统的设备则可以在用户空间灵活配置作为输入、输出或中断模式。
+与LED子系统不同，当某个引脚被用于具体的LED设备时，该引脚会被设备占用，它的
+功能在用户空间是无法再被修改的，而使用GPIO子系统的设备则可以在用户空间灵活配置作为输入、输出或中断模式。
 
-只要我们知道蜂鸣器的GPIO引脚编号，就可以就可以通过它导出的direction、value文件控制引脚输出高低电平，从而控制它发声了。当然，如果硬件上临时把该引脚修改为按键高低电平检测，此时也可以通过这些文件把引脚改为输入模式使用，而不需要修改Linux内核驱动。
+只要我们知道蜂鸣器的GPIO引脚编号，就可以就可以通过它导出的direction、value文件
+控制引脚输出高低电平，从而控制它发声了。当然，如果硬件上临时把该引脚修改为按键
+高低电平检测，此时也可以通过这些文件把引脚改为输入模式使用，而不需要修改Linux内核驱动。
 
 引脚编号转换
-~~~~~~
+~~~~~~~~~~~~~~~~~~
 
-与LED驱动设备不一样，它们已经在内核驱动（设备树）绑定了具体引脚的端口号，最终直接以设备名字导出到用户空间，所以控制时只要通过设备文件即可控制，而不需要知道具体的硬件连接。使用GPIO子系统时，需要用户自主控制导出使用哪个引脚，所以我们要根据蜂鸣器的硬件连接来进行实验。
+与LED驱动设备不一样，它们已经在内核驱动（设备树）绑定了具体引脚的端
+口号，最终直接以设备名字导出到用户空间，所以控制时只要通过设备文件即可
+控制，而不需要知道具体的硬件连接。使用GPIO子系统时，需要用户自主控制导出
+使用哪个引脚，所以我们要根据蜂鸣器的硬件连接来进行实验。
 
-Mini开发板不带蜂鸣器，实验时可以在引出的排针处找到该引脚，使用电压表测量它的输出电压即可。
+Mini开发板不带蜂鸣器，实验时可以在引出的排针处找到该引脚，使用
+电压表测量它的输出电压即可。
 
-|gpiosu005|
+如下图:
 
-图 21‑4 蜂鸣器硬件原理图
+.. image:: media/gpiosu005.png
+   :align: center
+   :alt: 未找到图片5|
 
-从图 21‑4可了解到，蜂鸣器的控制引脚名为“GPIO1_19”，该引脚输出高电平时，三极管导通，蜂鸣器响，引脚输出低电平时，电路断开，蜂鸣器不响。
 
-i.MX6ULL芯片GPIO引脚名格式通常为GPIOn_IOx，如此处的GPIO1_19或GPIO4_IO20等等，其中n是端口号，x为该组端口的引脚号，本开发板采用的芯片有1~5组端口，每组端口包含的引脚从0~31不等。
 
+从上图可了解到，蜂鸣器的控制引脚名为"GPIO1_19"，该引脚输出高电平时，三极
+管导通，蜂鸣器响，引脚输出低电平时，电路断开，蜂鸣器不响。
+
+i.MX6ULL芯片GPIO引脚名格式通常为GPIOn_IOx，如此处的GPIO1_19或GPIO4_IO20等等，其
+中n是端口号，x为该组端口的引脚号，本开发板采用的芯片有1~5组端口，每组端口包含的引脚从0~31不等。
 本开发板中export文件使用的编号index与GPIO引脚名的转换关系如下：
 
 index = GPIOn_IOx = (n-1)*32 + x
@@ -140,40 +158,38 @@ index = GPIOn_IOx = (n-1)*32 + x
 
 又例如GPIO4_IO20的编号为：index = GPIO4_IO20 = (4-1)*32+20=116。
 
-要注意并不是所有的引脚都能通过export文件导出到用户空间的，例如GPIO4_IO20引脚已经被用在了LED设备上。
+要注意并不是所有的引脚都能通过export文件导出到用户空间的，例
+如GPIO4_IO20引脚已经被用在了LED设备上。
 
 控制蜂鸣器（Shell）
-~~~~~~~~~~~~
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
 下面使用命令行控制蜂鸣器，讲解GPIO子系统设备属性的应用。
 
-由于在Ubuntu主机通常无法导出GPIO，请在开发板上执行以下命令测试：
-
-#以下命令在开发板上执行
-
-#导出蜂鸣器使用的GPIO到用户空间
-
-echo 19 > /sys/class/gpio/export
-
-#确认出现了gpio19设备目录
-
-ls /sys/class/gpio/
-
-#控制gpio19方向为输出
-
-echo out > /sys/class/gpio/gpio19/direction
+由于在Ubuntu主机通常无法导出GPIO，请在开发板上执行以下命令测试,测试前需确保当前用户为root用户：
 
-#控制gpio19输出高电平
+.. code-block:: sh
+   :linenos:
 
-echo 1 > /sys/class/gpio/gpio19/value
+   #以下命令在开发板上执行
+   #导出蜂鸣器使用的GPIO到用户空间
+   echo 19 > /sys/class/gpio/export
+   #确认出现了gpio19设备目录
+   ls /sys/class/gpio/
+   #控制gpio19方向为输出
+   echo out > /sys/class/gpio/gpio19/direction
+   #控制gpio19输出高电平
+   echo 1 > /sys/class/gpio/gpio19/value
+   #控制gpio19输出低电平
+   echo 0 > /sys/class/gpio/gpio19/value
 
-#控制gpio19输出低电平
+如下图:
 
-echo 0 > /sys/class/gpio/gpio19/value
+.. image:: media/gpiosu006.png
+   :align: center
+   :alt: 未找到图片6|
 
-|gpiosu006|
 
-图 21‑5 使用GPIO子系统控制蜂鸣器
 
 命令执行的原理非常简单：
 
@@ -188,278 +204,157 @@ echo 0 > /sys/class/gpio/gpio19/value
 
 类似地，也可以通过系统调用的文件操作方式控制蜂鸣器。
 
-本实验的代码目录为：base_code/section2/beep/c，工程的目录结构如图 21‑6所示。
-
-|gpiosu007|
-
-图 21‑6 工程目录结构
-
-蜂鸣器控制
-^^^^^
-
-工程中的beep_bsp.c文件包含了控制蜂鸣器相关的函数，见代码清单 21‑1。
-
-代码清单 21‑1 蜂鸣器驱动文件（beep/c/sources/beep_bsp.c文件）
-
-1 #include <string.h>
-
-2 #include <sys/stat.h>
-
-3 #include <unistd.h>
-
-4 #include <fcntl.h>
-
-5 #include "includes/bsp_beep.h"
-
-6
-
-7 //蜂鸣器的GPIO引脚号
-
-8 //imx6的计算方式，GPIOn_IOx = (n-1)*32 + x
-
-9 //如GPIO1_IO19 = (1-1)*32 + 19 = 19
-
-10 #define BEEP_GPIO_INDEX "19"
-
-11
-
-12 int beep_init(void)
-
-13 {
-
-14 int fd;
-
-15 //index config
-
-16 fd = open("/sys/class/gpio/export", O_WRONLY);
-
-17 if (fd < 0)
-
-18 return 1 ;
-
-19
-
-20 write(fd, BEEP_GPIO_INDEX, strlen(BEEP_GPIO_INDEX));
-
-21 close(fd);
-
-22
-
-23 //direction config
-
-24 fd = open("/sys/class/gpio/gpio" BEEP_GPIO_INDEX "/direction", O_WRONLY);
-
-25 if (fd < 0)
-
-26 return 2;
-
-27
-
-28 write(fd, "out", strlen("out"));
-
-29 close(fd);
-
-30
-
-31 return 0;
-
-32 }
-
-33
-
-34 int beep_deinit(void)
-
-35 {
-
-36 int fd;
-
-37 fd = open("/sys/class/gpio/unexport", O_WRONLY);
-
-38 if (fd < 0)
-
-39 return 1;
-
-40
-
-41 write(fd, BEEP_GPIO_INDEX, strlen(BEEP_GPIO_INDEX));
-
-42 close(fd);
-
-43
+工程中的beep_bsp.c文件包含了控制蜂鸣器相关的函数，见如下所示。
 
-44 return 0;
 
-45 }
+.. code-block:: c
+   :caption: 蜂鸣器驱动文件（base_code/linux_app/beep/c/sources/bsp_beep.c文件）
+   :linenos:
 
-46
+   #include <string.h>
+   #include <sys/stat.h>
+   #include <unistd.h>
+   #include <fcntl.h>
+   #include "includes/bsp_beep.h"
 
-47
 
-48 int beep_on(void)
+   int beep_init(void)
+   {
+      int fd;
+      //index config
+      fd = open("/sys/class/gpio/export", O_WRONLY);
+      if(fd < 0)
+         return 1 ;
 
-49 {
+      write(fd, BEEP_GPIO_INDEX, strlen(BEEP_GPIO_INDEX));
+      close(fd);
 
-50 int fd;
+      //direction config
+      fd = open("/sys/class/gpio/gpio" BEEP_GPIO_INDEX "/direction", O_WRONLY);
+      if(fd < 0)
+         return 2;
 
-51
+      write(fd, "out", strlen("out"));
+      close(fd);	
+      
+      return 0;
+   }
 
-52 fd = open("/sys/class/gpio/gpio" BEEP_GPIO_INDEX "/value", O_WRONLY);
+   int beep_deinit(void)
+   {
+      int fd;
+      fd = open("/sys/class/gpio/unexport", O_WRONLY);
+      if(fd < 0)
+         return 1;
 
-53 if (fd < 0)
+      write(fd, BEEP_GPIO_INDEX, strlen(BEEP_GPIO_INDEX));
+      close(fd);
+      
+      return 0;
+   }
 
-54 return 1;
 
-55
+   int beep_on(void)
+   {
+      int fd;
 
-56 write(fd, "1", 1);
+      fd = open("/sys/class/gpio/gpio" BEEP_GPIO_INDEX "/value", O_WRONLY);
+      if(fd < 0)
+         return 1;
 
-57 close(fd);
+      write(fd, "1", 1);
+      close(fd);
 
-58
+      return 0;
+   }
 
-59 return 0;
+   int beep_off(void)
+   {
+      int fd;
 
-60 }
+      fd = open("/sys/class/gpio/gpio" BEEP_GPIO_INDEX "/value", O_WRONLY);
+      if(fd < 0)
+         return 1;
 
-61
+      write(fd, "0", 1);
+      close(fd);
 
-62 int beep_off(void)
+      return 0;
+   }
 
-63 {
-
-64 int fd;
-
-65
-
-66 fd = open("/sys/class/gpio/gpio" BEEP_GPIO_INDEX "/value", O_WRONLY);
-
-67 if (fd < 0)
-
-68 return 1;
-
-69
-
-70 write(fd, "0", 1);
-
-71 close(fd);
-
-72
-
-73 return 0;
-
-74 }
 
 该代码说明如下：
 
--  第10行 ：根据蜂鸣器使用的GPIO定义要使用的编号。
-
--  beep_init函数：它使用了open、write、close等函数修改export和gpioN/direction文件，初始化蜂鸣器使用的引脚为输出模式。
-
+-  beep_init函数：它使用了open、write、close等函数修改export和gpioN/direction文件，初始
+   化蜂鸣器使用的引脚为输出模式。
 -  beep_deinit函数：向unexport文件写入编号，取消导出。
 
 -  beep_on和beep_off函数：往gpioN/value文件写入1和0，控制引脚输出高低电平。
 
-本代码要特别注意的是export和unexport文件是只有写权限的，所以通过open打开时要使用“O_WRONLY”标志以写入方式打开，不能使用“O_RDWR”等带读模式的标志。
+本代码要特别注意的是export和unexport文件是只有写权限的，所以通过open打开时要
+使用"O_WRONLY"标志以写入方式打开，不能使用"O_RDWR"等带读模式的标志。
 
 主文件
-^^^
-
-编写完 蜂鸣器的控制函数后，就可以在 main 函数中测试了，见代码清单 21‑2。
-
-代码清单 21‑2 主函数（beep/c/sources/main.c文件）
-
-1 #include <stdio.h>
-
-2 #include <unistd.h>
-
-3 #include "includes/bsp_beep.h"
-
-4
-
-5 /*\*
-
-6 \* @brief 主函数
-
-7 \* @param 无
-
-8 \* @retval 无
-
-9 \*/
-
-10 int main(int argc, char \*argv[])
-
-11 {
-
-12 char buf[10];
-
-13 int res;
-
-14 printf("This is the beep demo\n");
-
-15
-
-16 res = beep_init();
-
-17 if (res) {
-
-18 printf("beep init error,code = %d",res);
-
-19 return 0;
-
-20 }
-
-21
-
-22 while (1) {
-
-23 printf("Please input the value : 0--off 1--on q--exit\n");
-
-24 scanf("%10s", buf);
-
-25
-
-26 switch (buf[0]) {
-
-27 case '0':
-
-28 beep_off();
-
-29 break;
-
-30
-
-31 case '1':
-
-32 beep_on();
-
-33 break;
-
-34
-
-35 case 'q':
-
-36 beep_deinit();
-
-37 printf("Exit\n");
-
-38 return 0;
-
-39
-
-40 default:
-
-41 break;
-
-42 }
-
-43 }
-
-44 }
-
-在 main 函数中，调用我们前面定义的beep_init初始化蜂鸣器使用的GPIO，然后使用scanf检测用户输入，根据用户输入调用对应的函数控制蜂鸣器。
+^^^^^^^^^^^^^^^
+
+编写完 蜂鸣器的控制函数后，就可以在 main 函数中测试了，如下所示。
+
+
+.. code-block:: c
+   :caption: 主函数（base_code/linux_app/beep/c/sources/main.c文件）
+   :linenos:
+
+   #include <stdio.h>
+   #include <unistd.h>
+   #include "includes/bsp_beep.h"
+
+   /**
+      * @brief  主函数
+      * @param  无
+      * @retval 无
+      */
+   int main(int argc, char *argv[])
+   {
+      char buf[10];
+      int res;
+      printf("This is the beep demo\n");
+      
+      res = beep_init();
+      if(res){
+         printf("beep init error,code = %d",res);
+         return 0;
+      }
+
+      while(1){
+         printf("Please input the value : 0--off 1--on q--exit\n");
+         scanf("%10s", buf);
+
+         switch (buf[0]){
+            case '0':
+               beep_off();
+               break;
+
+            case '1':
+               beep_on();
+               break;
+
+            case 'q':
+               beep_deinit();
+               printf("Exit\n");
+               return 0;
+
+            default:
+               break;
+         }
+      }
+   }
+
+
+在 main 函数中，调用我们前面定义的beep_init初始化蜂鸣器使用的GPIO，然后使用scanf检测用
+户输入，根据用户输入调用对应的函数控制蜂鸣器。
 
 编译及测试
-^^^^^
+^^^^^^^^^^^^^^^^^^^^
 
 本实验使用的Makefile相对于前面的章节仅修改了最终的可执行文件名为beep_demo。
 
@@ -467,20 +362,29 @@ echo 0 > /sys/class/gpio/gpio19/value
 
 对于ARM架构的程序，可使用如下步骤进行编译：
 
-#在主机的实验代码Makefile目录下编译
+.. code-block:: sh
+   :linenos:
 
-#编译arm平台的程序
+   #在主机的实验代码Makefile目录下编译
+   #编译arm平台的程序
+   make ARCH=arm
 
-make ARCH=arm
+编译后生成的ARM平台程序为build_arm/beep_demo，使用网络文件系统共
+享至开发板，在开发板的终端上运行该程序测试即可。
 
-编译后生成的ARM平台程序为build_arm/beep_demo，使用网络文件系统共享至开发板，在开发板的终端上运行该程序测试即可。
+如下图:
+
+.. image:: media/gpiosu008.png
+   :align: center
+   :alt: 未找到图片8|
 
-|gpiosu008|
 
-图 21‑7 在开发板上的执行现象
 
 程序执行后会提示输入，在终端输入1并回车后蜂鸣器会响，输入0并回车后蜂鸣器不响。
 
+
+
+
 .. |gpiosu002| image:: media/gpiosu002.png
    :width: 5.76806in
    :height: 0.81981in
diff --git a/documentation/linux_app/hello_in_linux.rst b/documentation/linux_app/hello_in_linux.rst
new file mode 100644
index 0000000000000000000000000000000000000000..70d40212512a176d9c97653299c3c13fb9a8728e
--- /dev/null
+++ b/documentation/linux_app/hello_in_linux.rst
@@ -0,0 +1,108 @@
+.. vim: syntax=rst
+
+Linux系统下的Hello World
+-----------------------
+
+大家如果认真看前面文档的的话，会发现，算上我们这一章，已经是连续第三个章节都有讨论Hello World程序了。
+只不过前面两章主要是借助它来给大家介绍GCC编译工具链，并没有涉及太多Hello World程序的核心。
+这里可能你会疑惑:Hello World程序有啥核心？但是如果你对Hello World程序掉以轻心，那你就错了。
+
+如此简单的一个程序，却带领了无数的人进入了编程的世界。只不过越简单的事物背后往往蕴含着复杂的机制。
+如果我们深入思考一个简单的"Hello World程序"，就会发现很多问题看似简单，
+但是实质上我们并没有一个非常清晰的思路，准确来说，应该大部分人脑海中都有一些模糊的印象，
+但是真正深入到细节中去的时候，可能又模糊不清了。
+
+尤其是单片机转过来学习Linux开发的学员，因为对单片机下的"Hello World程序"有了非常底层的认识，
+所以在学习Linux系统开发的时候，经常不自觉地套用单片机下的"Hello World程序"的知识，来理解Linux
+系统的"Hello World程序"，却不知两个程序之间的运行机制已经截然不同。
+
+**"Hello World程序"是一个典型的案例，我们搞懂它在Linux系统下的运行机制，对我们以后开发其他程序，
+有非常好的借鉴意义。尤其是当你的程序编译链接出错的时候，可以清晰地判断问题出现在哪个环节。
+而不用再一脸懵逼地复制各种报错的信息，到谷歌百度中苦苦寻找解决方法。**
+
+下面以"裸机下的Hello World"为比较对象，给大家扒一扒"Linux系统下的Hello World"。
+**在接下来的分析内容里面，大家重点把握整个执行流程。在没有对Linux系统有深入研究之前，
+千万不要陷进去其中的大部分细节。在学习初期，掌握宏观思想已经很不错了，
+足以指导我们以后进一步学习其他内容**。
+
+裸机下的Hello World
+~~~~~~~~~~~~~~~~~~
+
+在单片机中，实现Hello World程序的步骤并不复杂，下面的这张图片基本上涵括了全部的开发过程，非常清晰:
+
+.. image:: media/helloworld1.png
+   :align: center
+   :alt: 未找到图片
+
+- 第一步；进行源代码的编写，其中关键的点在于printf函数的实现，它需要依赖单片机的串口驱动程序。
+- 第二步: 借助一些集成开发环境进行程序的编译。一键编译，无需学习编译链接相关知识。
+- 第三步: 借助烧录工具烧录到具体芯片上。一键烧录，无需学习芯片的flash和各种各样启动方式。
+- 第四步: 上电启动开发板，串口输出"Hello World"字符串。
+
+Linux系统下的Hello World
+~~~~~~~~~~~~~~~~~~~~~~~~~
+
+上面谈到了裸机开发Hello World，其实它也涉及到很多编译链接和烧录的知识，但是因为裸机程序不是本章节的重点，
+在这里不适合展开来讲。而我们Linux系统下的Hello World，则是因为它的借鉴意义非常强，
+对我们以后进一步学习其他课程起到很好的指导作用，所以在这里会尽可能详细剖析它整体的工作原理。
+
+我们先来看Linux系统下，Hello World程序的流程图，如下所示:
+
+.. image:: media/helloworld2.png
+   :align: center
+   :alt: 未找到图片
+
+总体上整个程序的编译执行过程，可以按图片从上到下的顺序，分为四大部分的内容：
+
+- 第一部分，上面浅绿色外框部分为程序的编译。
+- 第二部分，浅黄色外框部分为Linux内核提供的服务。
+- 第三部分，橘色外框部分为glibc库提供的服务。
+- 第四部分，浅灰色外框部分，为用户程序。
+
+下面针对每个子步骤做进一步的讲解:
+
+1. 预处理hello.c,主要是处理程序里面的文件包含、处理宏定义、条件编译。
+
+2. 把c文件编译成为汇编文件(.s)，其中进行了词法分析，语法分析，语义分析、生成中间代码、对代码进行优化等工作。
+
+3. 把汇编文件(.s)编译成可重定位文件(.o)。
+
+4. 把可重定位文件(.o)链接成为可执行文件，其中链接可分为静态链接和动态链接
+
+- 静态链接:在编译阶段就会把所有用到的库打包到自己的可执行程序中,其优点是具有较好的兼容性，不依赖外部环境，但是生成的程序比较大。
+- 动态链接:在应用程序运行时，链接器去加载外部的共享库，并完成共享库和动态编译程序之间的链接。不同的程序可以共用代码库，节省内存空间。
+
+5. 控制台输入./hello命令后，Shell会创建一个新的进程来执行该程序。fork()函数就是用于创建一个新的进程的。这里的进程可以先简单理解为程序的容器。
+
+6. exeve()函数可以理解为向上一步新建的进程，填充一个可执行程序(hello)。
+
+7. sys_execve()函数为linux系统调用,被exeve()函数调用，这里的系统调用可以理解为是操作系统系统开放给用户的最底层接口。
+
+8. do_exeve()函数是sys_execve()函数的核心。
+
+9. load_elf_binary()函数会去文件系统中读取hello程序到内存，然后判断它是否是动态链接的可执行程序，如果不是，则进一步判断是否是静态链接的文件。
+
+10. ld-linux-xx.so是glibc库中的动态连接器。如果hello程序是动态链接程序，该动态链接器会去加载共享库，并完成共享库和程序的链接工作，
+然后准备真正开始执行hell程序。
+
+11. 相反，如果hello程序是静态编译的程序，则无需再加载链接共享库，直接开始准备执行hello程序。
+
+    - 第10和11步分别执行之后.都会开始执行hello程序，_start是程序的真正入口，而该符号在glibc中。也就是说程序的真正入口在glibc。
+
+12. __libc_start_main()也是glibc中的函数，用于在执行用户程序前进行一些初始化工作。
+
+13. 调用用户程序中的mian()函数，开始执行printf打印函数。
+
+14. 程序执行完了之后，调用glibc库中的_exit()函数，来结束当前进程。
+
+整个过程粗略分析完了，对比裸机和linux系统下的"Hello World",很明显可以看到操作系统为我们做了大量的工作，
+甚至为了节省内存空间，还把程序的链接这种非常基础性的工作，交给了glibc中的动态连接器来完成。
+避免静态链接的那种低效的开发方式，这是裸机开发难以做到的。
+
+大家可能会对里面的内容有很多陌生的地方，也可能有很多疑惑的地方，
+但是这里面的内容实在没有办法展开来讲，每个子步骤的后面都是一个庞然大物。如果在这个地方耗费过多精力，
+势必会大大耽误学习的进度。对于深入高阶的内容，还是需要循序渐进的。
+
+但是另一方面，脑海中有了程序执行的整体轮廓之后，我们以后的学习和编程，
+就有了指导和前进的方向。我们对程序开发过程中，进行的每个步骤就了然于胸。这才是我们这个章节的意义所在。
+
diff --git a/documentation/linux_app/i2c_bus.rst b/documentation/linux_app/i2c_bus.rst
index 3f47a6e8db51aa815303b5287b25c5608d3c7743..8e4e579082d98817e6875e444965d53d8a4ce8a8 100644
--- a/documentation/linux_app/i2c_bus.rst
+++ b/documentation/linux_app/i2c_bus.rst
@@ -3,11 +3,12 @@
 I2C通讯
 -----------------
 
-本章通过讲解在应用层中使用I2C总线与外部设备的通讯，讲解Linux系统总线类型设备驱动架构的应用。
+本章介绍在应用层中使用I2C总线与外部设备的通讯，讲解Linux系
+统总线类型设备驱动架构的应用。
 
 在Linux内核文档的Documentation/i2c目录下有关于I2C驱动非常详细的说明。
 
-本章节的示例代码目录为：base_code/section2/i2c
+本章节的示例代码目录为：base_code/linux_app/i2c
 
 I2C通讯协议简介
 ^^^^^^^^^^^^^^^^^^^^^
@@ -30,7 +31,7 @@ I2C通讯设备之间的常用连接方式如下图。
 
 它的物理层有如下特点：
 
-- 它是一个支持多设备的总线。“总线”指多个设备共用的信号线。
+- 它是一个支持多设备的总线。"总线"指多个设备共用的信号线。
   在一个I2C通讯总线中，可连接多个I2C通讯设备，支持多个通讯主机及多个通讯从机。
 - 一个I2C总线只使用两条总线线路，一条双向串行数据线(SDA) ，一条串行时钟线 (SCL)。
   数据线即用来表示数据，时钟线用于数据收发同步。
@@ -89,28 +90,31 @@ I2C基本读写过程
    在I2C总线上，每个设备的地址都是唯一的，当主机广播的地址与某个设备地址相同时，这个设备就被选中了，没被选中的设备将会忽略之后的数据信号。
    根据I2C协议，这个从机地址可以是7位或10位。
 
-#. 在地址位之后，是传输方向的选择位，该位为0时，表示后面的数据传输方向是由主机传输至从机，即主机向从机写数据。该位为1时，则相反，即主机由从机读数据。
+#. 在地址位之后，是传输方向的选择位，该位为0，表示后面的数据传输方向是由主机传输至从机，即主机向从机写数据。该位为1，则相反，即主机由从机读数据。
 
 #. 从机接收到匹配的地址后，主机或从机会返回一个应答(ACK)或非应答(NACK)信号，只有接收到应答信号后，主机才能继续发送或接收数据。
 
 
 写数据方向:
-  若配置的方向传输位为 **“写数据”** 方向，即第一幅图的情况，广播完地址，接收到应答信号后，
-  主机开始正式向从机 **传输数据(DATA)** ，数据包的大小为8位，主机每发送完一个字节数据，
-  都要等待从机的应答信号(ACK)，重复这个过程，可以向从机传输N个数据，这个N没有大小限制。
-  当数据传输结束时，主机向从机发送一个停止传输信号(P)，表示不再传输数据。
+
+若配置的方向传输位为 **"写数据"** 方向，即第一幅图的情况，广播完地址，接收到应答信号后，
+主机开始正式向从机 **传输数据(DATA)** ，数据包的大小为8位，主机每发送完一个字节数据，
+都要等待从机的应答信号(ACK)，重复这个过程，可以向从机传输N个数据，这个N没有大小限制。
+当数据传输结束时，主机向从机发送一个停止传输信号(P)，表示不再传输数据。
 
 读数据方向:
-  若配置的方向传输位为 **“读数据”** 方向，即第二幅图的情况，广播完地址，接收到应答信号后，
-  从机开始向主机 **返回数据(DATA)** ，数据包大小也为8位，从机每发送完一个数据，
-  都会等待主机的应答信号(ACK)，重复这个过程，可以返回N个数据，这个N也没有大小限制。
-  当主机希望停止接收数据时，就向从机返回一个非应答信号(NACK)，则从机自动停止数据传输。
+
+若配置的方向传输位为 **"读数据"** 方向，即第二幅图的情况，广播完地址，接收到应答信号后，
+从机开始向主机 **返回数据(DATA)** ，数据包大小也为8位，从机每发送完一个数据，
+都会等待主机的应答信号(ACK)，重复这个过程，可以返回N个数据，这个N也没有大小限制。
+当主机希望停止接收数据时，就向从机返回一个非应答信号(NACK)，则从机自动停止数据传输。
 
 复合格式:
-  除了基本的读写，I2C通讯更常用的是 **复合格式** ，即第三幅图的情况，该传输过程有 **两次起始信号(S)** 。
-  一般在第一次传输中，主机通过SLAVE_ADDRESS寻找到从设备后，发送一段“数据”，
-  这段数据通常用于表示从设备内部的寄存器或存储器地址(注意区分它与SLAVE_ADDRESS的区别)；
-  在第二次的传输中，对该地址的内容进行读或写。也就是说，第一次通讯是告诉从机读写地址，第二次则是读写的实际内容。
+
+除了基本的读写，I2C通讯更常用的是 **复合格式** ，即第三幅图的情况，该传输过程有 **两次起始信号(S)** 。
+一般在第一次传输中，主机通过SLAVE_ADDRESS寻找到从设备后，发送一段"数据"，
+这段数据通常用于表示从设备内部的寄存器或存储器地址(注意区分它与SLAVE_ADDRESS的区别)；
+在第二次的传输中，对该地址的内容进行读或写。也就是说，第一次通讯是告诉从机读写地址，第二次则是读写的实际内容。
 
 以上通讯流程中包含的起始、停止、数据有效性、地址和数据方向以及响应的说明按小节如下。
 
@@ -123,6 +127,8 @@ I2C基本读写过程
 - 当 SCL 线是高电平时 SDA 线从高电平向低电平切换，这个情况表示通讯的起始。
 - 当 SCL 是高电平时 SDA 线由低电平向高电平切换，表示通讯的停止。
 
+如下图:
+
 .. image:: media/i2c/i2cbus008.jpg
    :align: center
    :alt: 起始和停止信号
@@ -134,9 +140,11 @@ I2C基本读写过程
 I2C使用SDA信号线来传输数据，使用SCL信号线进行数据同步，如下图。
 SDA数据线在SCL的每个时钟周期传输一位数据。
 
-- 传输时，SCL为高电平的时候SDA表示的数据有效，即此时的SDA为高电平时表示数据“1”，为低电平时表示数据“0”。
+- 传输时，SCL为高电平的时候SDA表示的数据有效，即此时的SDA为高电平时表示数据"1"，为低电平时表示数据"0"。
 - 当SCL为低电平时，SDA的数据无效，一般在这个时候SDA进行电平切换，为下一次表示数据做好准备。
 
+如下图:
+
 .. image:: media/i2c/i2cbus009.jpg
    :align: center
    :alt: 数据有效性
@@ -150,7 +158,9 @@ I2C总线上的每个设备都有自己的独立地址，主机发起通讯时
 I2C协议规定设备地址可以是7位或10位，实际中7位的地址应用比较广泛。
 
 紧跟设备地址的一个数据位用来表示数据传输方向，它是数据方向位(R/)，第8位或第11位。
-数据方向位为“1”时表示主机由从机读数据，该位为“0”时表示主机向从机写数据，如下图。
+数据方向位为"1"时表示主机由从机读数据，该位为"0"时表示主机向从机写数据。
+
+如下图：
 
 .. image:: media/i2c/i2cbus010.jpg
    :align: center
@@ -163,11 +173,13 @@ I2C协议规定设备地址可以是7位或10位，实际中7位的地址应用
 响应
 """"""""""""""""""""
 
-I2C的数据和地址传输都带响应。响应包括“应答(ACK)”和“非应答(NACK)”两种信号。
+I2C的数据和地址传输都带响应。响应包括"应答(ACK)"和"非应答(NACK)"两种信号。
 作为数据接收端时，当设备(无论主从机)接收到I2C传输的一个字节数据或地址后：
 
-- 若希望对方 **继续发送数据** ，则需要向对方发送 **“应答(ACK)”** 信号，发送方会继续发送下一个数据；
-- 若接收端希望 **结束数据传输** ，则向对方发送 **“非应答(NACK)”** 信号，发送方接收到该信号后会产生一个停止信号，结束信号传输。如下图。
+- 若希望对方 **继续发送数据** ，则需要向对方发送 **"应答(ACK)"** 信号，发送方会继续发送下一个数据；
+- 若接收端希望 **结束数据传输** ，则向对方发送 **"非应答(NACK)"** 信号，发送方接收到该信号后会产生一个停止信号，结束信号传输。如下图。
+
+如下图:
 
 .. image:: media/i2c/i2cbus011.jpg
    :align: center
@@ -177,171 +189,743 @@ I2C的数据和地址传输都带响应。响应包括“应答(ACK)”和“非
 传输时主机产生时钟，在第9个时钟时，数据发送端会释放SDA的控制权，由数据接收端控制SDA，若SDA为高电平，表示非应答信号(NACK)，低电平表示应答信号(ACK)。
 
 
-Linux的I2C及总线设备
+
+
+
+使能IIC通信接口
 ^^^^^^^^^^^^^^^^^^^^^^^^^
-由于一个I2C总线上可以挂载多个设备，
 
+I.MX6ULL有4个I2C外设，MPU6050连接到了它的IIC 1接口，参考前面《fire-config工具简介》章节，使能IIC_1通信接口。
+
+如下图:
 
-/sys/bus/i2c
+.. image:: media/i2c/i2cbus019.png
+   :align: center
+   :alt: 未找到图片
 
-::
 
-    #以下命令在开发板上的终端上运行
-    #查看系统存在的I2C总线
-    ls  /sys/bus/i2c/devices
+检查IIC 设备
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 
-    #根据具体的输出查看存在的I2C设备和总线
+使能IIC_1通信接口后，我们可以通过系统中的IIC设备文件来检查设备的一些基本信息，下面简单介绍几个查看命令。
 
-    #查看I2C总线的属性
-    ls /sys/bus/i2c/devices/i2c-0
-    #查看I2C总线的名字
-    cat /sys/bus/i2c/devices/i2c-0/name
 
-    #查看I2C设备的属性
-    ls /sys/bus/i2c/deivces/0-005d
-    #查看I2C设备的名字
-    cat /sys/bus/i2c/devices/0-005d/name
+.. code-block:: sh
+   :linenos:
 
+   #查看系统存在的I2C总线
+   ls  /sys/bus/i2c/devices
 
 
+如下图，不同版本的Debian系统输出内容可能有差别。
 
-在用户态添加一个I2C设备
+.. image:: media/i2c/i2cbus020.png
+   :align: center
+   :alt: 未找到图片
 
-::
 
-  #未测试，参数为设备名及设备地址
-  echo eeprom 0x50 > /sys/bus/i2c/devices/i2c-3/new_device
+IIC 1接口对应的驱动设备文件为上图中的i2c-0，这是因为驱动是从0开始编号的。 
+因此应用程序一般通过操作设备文件i2c-0实现对MPU6050的操作。不止MPU6050，
+理论上任何连接到 IIC 1 接口上的设备（触摸、摄像头、oled）都可以通过 i2c-0 设备文件来实现具体的功能。
 
 
-在用户态删除一个I2C设备
+IIC 第三方工具- i2c-detect
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 
-::
+使用i2c-tools工具包提供了一些非常方便的工具来对系统的I2C总线进行调试。使用之前要使用apt 命令安装i2c-tools。下面介绍i2c-tools的安装步骤并使用i2c-tools提供的命令查看系统IIC 设备。
 
-  #未测试,参数为要删除设备的设备地址
-  echo 0x50  > /sys/bus/i2c/devices/i2c-3/delete_device
 
+i2c-detect工具安装
+~~~~~~~~~~~~~~~~~~~~~~~~
 
-/dev/i2c-0
+在开发板的控制台执行命令：
 
 
+.. code-block:: sh
+   :linenos:
 
-i2c-detect工具
-^^^^^^^^^^^^^^^^^^^^^
-使用i2c-tools工具包提供了一些非常方便的工具来对系统的I2C总线进行调试。
+   sudo apt install i2c-tools -y
 
-可以通过如下指令安装
-::
+安装后可使用的命令有i2cdetect、i2cdump、i2cset以及i2cget,它们分别用于扫描I2C总线上的设备、读写指定设备的寄存器内容。
+命令介绍如下：
 
-  #以下命令在主机上运行
-  sudo apt install i2c-tools
 
+i2cdetect命令
+~~~~~~~~~~~~~~~~~~~~~~~~
 
-安装后可使用的命令有i2cdetect、i2cdump、i2cset以及i2cget,
-它们分别用于扫描I2C总线上的设备、读写指定设备的寄存器内容
 
+i2cdetect ：用于扫描I2C总线上的设备。它会打印一个表，其中包含了总线上检测到的设备。
 
 
-+ i2cdetect ：用于扫描I2C总线上的设备。它会打印一个表，其中包含了总线上检测到的设备。
-~~~
-    相关命令语法：
-       i2cdetect [-y] [-a] [-q|-r] i2cbus [first last]：
-       参数说明：
-       >参数y：关闭交互模式，使用该参数时，不会提示警告信息。
-       >参数a：扫描总线上的所有设备。
-       >参数q：使用SMBus的“quick write”命令进行检测，不建议使用该参数。
-       >参数r：使用SMBus的“receive byte”命令进行检测，不建议使用该参数。
-       >参数i2cbus：指定i2c总线的编号
-       >参数first、last：扫描的地址范围
+相关命令语法：
 
-       返回值说明：
-       >'--'：表示该地址被检测，但没有芯片应答；
-       >'UU'：表示该地址当前由内核驱动程序使用。
-       >'**'：**表示以十六进制表示的设备地址编号，如 “2d”或“4e”。
+i2cdetect [-y] [-a] [-q|-r] i2cbus [first last]：
 
-       i2cdetect -F i2cbus：查询i2c总线的功能，参数i2cbus表示i2c总线编号
+参数说明：
 
-       i2cdetect -V：打印软件的版本号
+- 参数y：关闭交互模式，使用该参数时，不会提示警告信息。
+- 参数a：扫描总线上的所有设备。
+- 参数q：使用SMBus的"quick write"命令进行检测，不建议使用该参数。
+- 参数r：使用SMBus的"receive byte"命令进行检测，不建议使用该参数。
+- 参数i2cbus：指定i2c总线的编号
+- 参数first、last：扫描的地址范围
 
-       i2cdetect -l：检测当前系统有几组i2c总线
-~~~
+返回值说明：
 
-+ i2cget 
-~~~
-    相关命令语法：
-        i2cget [-f] [-y] i2cbus chip-address [data-address [mode]]
-        参数说明：
-        >参数f：强制访问设备。
-        >参数y：关闭交互模式，使用该参数时，不会提示警告信息。
-        >参数i2cbus：指定i2c总线的编号
-        >参数chip-address：i2c设备地址
-        >参数data-address：设备的寄存器的地址
-        >参数mode：参考i2cdump命令。
-~~~
+- '--'：表示该地址被检测，但没有芯片应答；
+- 'UU'：表示该地址当前由内核驱动程序使用。
+- '**'：**表示以十六进制表示的设备地址编号，如 "2d"或"4e"。
 
-+ i2cset 
-~~~
-    相关命令语法：
-       i2cset  [-f]  [-y]  [-m  mask]  [-r]  i2cbus  chip-address data-address [value] ...  [mode]
-       参数说明：
-       >参数f：强制访问设备。
-       >参数y：关闭交互模式，使用该参数时，不会提示警告信息。
-       >参数m：
-       >参数r：写入后立即回读寄存器值，并将结果与写入的值进行比较。
-       >参数i2cbus：指定i2c总线的编号
-       >参数chip-address：i2c设备地址
-       >参数data-address：设备的寄存器的地址
-       >参数value：要写入寄存器的值
-       >参数mode：参考i2cdump命令。
-~~~
 
-+ i2cdump：读取I2C总线上某个设备的寄存器值。
-~~~
-    相关命令语法：
-       i2cdump   [-f]   [-r first-last]  [-y]  i2cbus  address  [mode [bank [bankreg]]]
-       >参数r：指定寄存器范围，只扫描从first到last区域；
-       >参数f：强制访问设备。
-       >参数y：关闭人机交互模式；
-       >参数i2cbus：指定i2c总线的编号
-       >参数address：指定设备的地址
-       >参数mode：指定读取的大小， 可以是b, w, s或i，分别对应了字节，字，SMBus块, I2C块
-       i2cdump -V：打印软件的版本号
-~~~
+i2cdetect 使用示例
+~~~~~~~~~~~~~~~~~~~~~~~~
 
+i2cdetect主要用于查看当前总线上的设备，我们这里查看IIC 1接口上的设备，重点关注MPU6050、显示屏触摸芯片、oled显示屏（需要使用杜邦线外接）
 
 
-## MPU6050实验
+首先不连接显示屏和oled 执行如下命令：
 
-i2cset -f -y -r 0 0x68 0x6B 0
+.. code-block:: sh
+   :linenos:
 
-i2cset -f -y -r 0 0x68 0x19 7
+   i2cdetect -a 0
 
-i2cset -f -y -r 0 0x68 0x1A 6
+参数 "-a" 扫描总线上的所有设备。 参数"0" 表示标号为0的IIC 总线，既 IIC 1 。
 
-i2cset -f -y -r 0 0x68 0x1C 1
+输出内容如下所示：
 
-i2cdump -f -y -r 0x3B-0x48 0 0x68
+.. image:: media/i2c/i2cbus017.png
+   :align: center
+   :alt: 未找到图片
+
+
+上图中 "68" 是MPU6050的设备地址。
 
+连接显示屏（显示屏40pin 的排线中包含了触摸的IIC ，所以接上显示屏也就将触摸芯片接入 IIC 1 总线），再次执行查看设备命令，如下所示：
 
-读取陀螺仪的ID
+.. code-block:: sh
+   :linenos:
 
-::
+   i2cdetect -a 0
 
-  i2cget 0 0x68  0x75
+如下图:
+
+.. image:: media/i2c/i2cbus018.png
+   :align: center
+   :alt: 未找到图片
+
+新增加的IIC 地址5d，就是我们新接入的触摸芯片IIC 地址。
+
+
+i2cdetect其他命令
+""""""""""""""""""""""
+
+- i2cdetect -F i2cbus：查询i2c总线的功能，参数i2cbus表示i2c总线
+- i2cdetect -V：打印软件的 - 
+- i2cdetect -l：检测当前系统有几组i2c总线
+
+
+
+i2cget命令
+~~~~~~~~~~~~~~~~~~~~~~~~
+
+i2cget:读取指定IIC设备的某个寄存器的值
+
+相关命令语法：
+        
+i2cget [-f] [-y] i2cbus chip-address [data-address [mode]]
+        
+参数说明：
+
+- 参数f：强制访问设备。
+- 参数y：关闭交互模式，使用该参数时，不会提示警告信息。
+- 参数i2cbus：指定i2c总线的编号
+- 参数chip-address：i2c设备地址
+- 参数data-address：设备的寄存器的地址
+- 参数mode：参考i2cdump命令。
+
+
+i2cset命令
+~~~~~~~~~~~~~~~~~~~~~~~~
+
+i2cget:写入指定IIC设备的某个寄存器的值
+
+相关命令语法：
+       
+i2cset  [-f]  [-y]  [-m  mask]  [-r]  i2cbus  chip-address data-address [value] ...  [mode]
+       
+参数说明：
+
+- 参数f：强制访问设备。
+- 参数y：关闭交互模式，使用该参数时，不会提示警告信息。
+- 参数m：
+- 参数r：写入后立即回读寄存器值，并将结果与写入的值进行比较。
+- 参数i2cbus：指定i2c总线的编号
+- 参数chip-address：i2c设备地址
+- 参数data-address：设备的寄存器的地址
+- 参数value：要写入寄存器的值
+- 参数mode：参考i2cdump命令
+
+
+
+i2cdump命令
+~~~~~~~~~~~~~~~~~~~~~~~~
 
-其中0x68是陀螺仪设备的7位I2C地址，0x75是陀螺仪的WHO_AM_I寄存器，
+i2cdump：读取指定设备的全部寄存器的值。
 
-数据地址支持的范围为0x00~0xFF,所以对于触摸屏使用16位表示寄存器地址的设备不适用。
+相关命令语法：
+       
+i2cdump   [-f]   [-r first-last]  [-y]  i2cbus  address  [mode [bank [bankreg]]]
 
-读取陀螺仪传感器数据
+参数说明：
+
+- 参数r：指定寄存器范围，只扫描从first到last区域；
+- 参数f：强制访问设备。
+- 参数y：关闭人机交互模式；
+- 参数i2cbus：指定i2c总线的编号
+- 参数address：指定设备的地址
+- 参数mode：指定读取的大小， 可以是b, w, s或i，分别对应了字节，字，SMBus块, I2C块
+ 
+i2cdump -V：打印软件的版本号
+
+
+
+读取陀螺仪传感器数据实验
 ^^^^^^^^^^^^^^^^^^^^^
 
+实验说明
+~~~~~~~~~~~~~~~~~~~~~~~~
+
+本教程将通过IIC接口读取板载陀螺仪(MPU6050)的原始数据(MINI开发板没有板载陀螺仪，想要完成本实验需要参照Pro开发板外接MPU6050传感器)。
+在测试程序中大约每一秒读取并显示一次MPU6050的原始数据。读取得到的原始数据并没有进行处理，所以不要误以为读取得到的是角度值。
+
+
+查看IIC设备文件，确保IIC 1接口已经使能
+
+.. code-block:: sh
+   :linenos:
+
+   ls  /sys/bus/i2c/devices
+
+如下图:
 
-控制OLED显示
+.. image:: media/i2c/i2cbus020.png
+   :align: center
+   :alt: 未找到图片
+
+"i2c-0" 就是MPU6050使用到的 IIC 1接口总线。
+
+
+程序分析
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+陀螺仪传感器数据读取程序完整源码，请参考本小节配套源码（位于 base_code/linux_app/i2c/mpu6050/sources 目录下）。
+
+.. code-block:: sh
+   :caption: MPU6050示例（base_code\linux_app\i2c\mpu6050\sources\main.c文件）
+   :linenos:
+
+   /************************第一部分***********************/
+   //MPU6050初始化
+   static uint8 MPU6050_Init(void)
+   {
+       fd  = open("/dev/i2c-0", O_RDWR);               // 以读写权限打开IIC 1设备文件
+   
+       if (fd < 0)
+       {
+           perror("Can't open /dev/MPU6050 \n");       
+           exit(1);
+       }
+   
+       printf("open /dev/i2c-0 success !\n");          
+   
+       if (ioctl(fd, I2C_SLAVE, Address) < 0)         //设置IIC设备地址
+       { 
+           printf("fail to set i2c device slave address!\n");
+           close(fd);
+           return - 1;
+       }
+   
+       printf("set slave address to 0x%x success!\n", Address);
+       i2c_write(fd, PWR_MGMT_1, 0X00);               //配置电源管理，0x00,正常启动
+       i2c_write(fd, SMPLRT_DIV, 0X07);               //设置MPU6050的输出分频既设置采样频率
+       i2c_write(fd, CONFIG, 0X06);                   //配置数字低通滤波器和帧同步引脚采样
+       i2c_write(fd, ACCEL_CONFIG, 0X01);             //设置量程和 X、Y、Z 轴加速度自检
+       return (1);
+   }
+   
+   /************************第二部分***********************/
+   //MPU6050 wirte byte
+   static uint8 i2c_write(int fd, uint8 reg, uint8 val)
+   {
+       int retries;
+       uint8 data[2];
+   
+       data[0] = reg;
+       data[1] = val;
+   
+       for (retries = 5; retries; retries--)
+       {
+           if (write(fd, data, 2) == 2)
+           {
+               return 0;
+   
+           }
+   
+           usleep(1000 * 10);
+       }
+   
+       return - 1;
+   }
+   
+   /************************第三部分***********************/
+   //MPU6050 read byte
+   static uint8 i2c_read(int fd, uint8 reg, uint8 * val)
+   {
+       int retries;
+   
+       for (retries = 5; retries; retries--)
+       {
+           if (write(fd, &reg, 1) == 1)
+           {
+               if (read(fd, val, 1) == 1)
+               {
+                   return 0;
+               }
+   
+           }
+   
+       }
+   
+       return - 1;
+   }
+   
+   /************************第四部分***********************/
+   //get data
+   short GetData(unsigned char REG_Address)
+   {
+       char H, L;
+   
+       i2c_read(fd, REG_Address, &H);
+       usleep(1000);
+       i2c_read(fd, REG_Address + 1, &L);
+       return (H << 8) +L;
+   }
+
+这部分代码由四个函数组成，它们都是由系统接口API（ioctl、read、write）函数实现的，结合代码简单说明如下：
+
+
+
+---------------------------------------------------------------------------------
+
+1. 第一部分，MPU6050初始化函数。初始化的过程实际就是打开设备然后写入配置参数。代码第5行使用可读可写方式打开IIC 设备文件。
+代码第14行，设置MPU6050的IIC 从地址。代码22到26行设置MPU6050采样精度和量程等等。
+
+2. 第二部分，MPU6050写函数。写入成功，返回0，失败返回 -1。函数参数共有三个，fd,文件描述符。reg，要写入的MPU6050寄存器地址。
+val, 要写入的值。在函数内部实际是使用 write 函数依次写入MPU6050寄存器地址和要写入的值。
+
+3. 第三部分，MPU6050读函数。返回值与MPU6050写函数相同。在函数中使用 write 函数写入要读取的MPU6050寄存器地址，
+然后使用read 函数读取即可得到MPU6050寄存器值。
+
+4. 第四部分，获取MPU6050数据函数。返回值为读取得到的MPU6050数据，函数实现很简单，
+使用 i2c_read 函数读取MPU6050数据寄存器即可。
+
+
+.. code-block:: c
+   :caption: 读取MPU6050原始数据
+   :linenos:  
+
+   /************************第一部分*********************/
+   #define ACCEL_XOUT_H                                0x3B
+   #define ACCEL_XOUT_L                                0x3C
+   #define ACCEL_YOUT_H                                0x3D
+   #define ACCEL_YOUT_L                                0x3E
+   #define ACCEL_ZOUT_H                                0x3F
+   #define ACCEL_ZOUT_L                                0x40
+   
+   
+   #define GYRO_XOUT_H                                 0x43
+   #define GYRO_XOUT_L                                 0x44
+   #define GYRO_YOUT_H                                 0x45
+   #define GYRO_YOUT_L                                 0x46
+   #define GYRO_ZOUT_H                                 0x47
+   #define GYRO_ZOUT_L                                 0x48
+   
+   /************************第二部分*********************/
+   // main
+   int main(int argc, char * argv[])
+   {
+       MPU6050_Init();
+       usleep(1000 * 100);
+   
+       while (1)
+       {
+           //printf("\033[2J");
+           usleep(1000 * 200);
+           printf("ACCE_X:%6d\n ", GetData(ACCEL_XOUT_H));
+           usleep(1000 * 200);
+           printf("ACCE_Y:%6d\n ", GetData(ACCEL_YOUT_H));
+           usleep(1000 * 200);
+           printf("ACCE_Z:%6d\n ", GetData(ACCEL_ZOUT_H));
+           usleep(1000 * 200);
+           printf("GYRO_X:%6d\n ", GetData(GYRO_XOUT_H));
+           usleep(1000 * 200);
+           printf("GYRO_Y:%6d\n ", GetData(GYRO_YOUT_H));
+           usleep(1000 * 200);
+           printf("GYRO_Z:%6d\n\n ", GetData(GYRO_ZOUT_H));
+           sleep(1);
+       }
+   
+       close(fd);
+   }
+
+代码实现非常简单，第一部分是MPU6050数据寄存器，通过读取这些寄存器可以获得MPU6050的三轴加速度和三轴陀螺仪数据。
+第二部分是在main函数中通过GetData函数读取数据并使用printf函数进行打印，读取间隔大约为1秒。
+
+
+
+
+
+下载验证
+~~~~~~~~~~~
+
+ARM架构
+'''''''''''''''
+
+对于ARM架构的程序，可使用如下步骤进行编译：
+
+.. code-block:: sh
+   :linenos:
+
+   #在主机的实验代码Makefile目录下编译
+   #编译arm平台的程序
+   make ARCH=arm
+
+编译后生成的ARM平台程序为build_arm/mpu6050_demo，使用网络文件系统共享至开
+发板，在开发板的终端上测试即可。
+
+
+如下图:
+
+.. image:: media/i2c/i2cbus021.png
+   :align: center
+   :alt: 未找到图片
+
+OLED显示屏显示实验
 ^^^^^^^^^^^^^^^^^^^^^
 
+本实验使用OLED显示屏如下所示
+
+.. image:: media/i2c/i2cbus012.jpg
+   :align: center
+   :alt: 未找到图片
+
+
+本实验的配套程序适配 IIC_1通信接口的 OLED 显示屏，分辨率128*64 。如果使用的是其他OLED显示屏必须保证支持IIC接口。
+
+
+硬件连接
+~~~~~~~~~~
 
 
+开发板自身不带OLED显示屏，本实验需要用杜邦线将OLED显示屏连接到 IIC_1接口。
+如果使用的是野火OLED 显示屏，OLED供电电压为3.3V（特别注意，OLED不兼容5V，接错电压可能烧坏OLED显示屏），
+OLED显示屏与Pro开发板的连接方法为:OLED显示屏的SDA、SCL引脚分别连接到开发板的IO1.29、IO1.28引脚，
+其VCC、GND连接到开发板的3.3V、GND引脚。
 
+如下图：
+
+.. image:: media/i2c/i2cbus013.jpg
+   :align: center
+   :alt: 未找到图片
+
+使能IIC通信接口
+^^^^^^^^^^^^^^^^^^^^^^^^^
+
+I.MX6ULL有4个I2C外设，OLED显示屏连接到了它的IIC_1接口，参考前面《fire-config工具简介》章节，使能IIC_1通信接口。
+
+
+代码分析
+~~~~~~~~~~
+
+oled程序完整源码，请参考本小节配套源码（位于 base_code/linux_app/i2c/oled/sources 目录下）。
+
+
+oled 写函数 oled_i2c_write ，oled 写函数用于向oled发送命令（配置参数）和要显示的数据，函数原型如下所示：
+
+
+.. code-block:: sh
+   :caption: oled（base_code\linux_app\i2c\oled\sources\main.c文件）
+   :linenos: 
+
+   static uint8 oled_i2c_write(int fd, uint8 reg, uint8 val)
+   {   
+       /*******************第一部分************************/
+       int retries;
+       uint8 data[2];
+       int write_error = 0;
+   
+       data[0] = reg;
+       data[1] = val;
+       
+       ioctl(fd, I2C_SLAVE, OLED_ADDRESS);
+       /*******************第二部分************************/
+       for (retries = 5; retries; retries--)
+       {
+           if (write(fd, data, 2) == 2)
+           {
+               return 0;
+           }
+           usleep(1000);
+       }
+       return -1;
+   }
+
+函数oled_i2c_write共有三个参数。fd， 打开的设备文件描述符，成功打开IIC设备文件后得到。reg，指定发送到的类型，这里分为命令和数据，在本程序中
+只有两个值可选，并且在程序中已经通过宏定义设置了，具体如下：
+
+
+.. code-block:: sh
+   :caption: oled（base_code\linux_app\i2c\oled\sources\main.c文件）
+   :linenos:
+
+   #define OLED_COMMEND_ADDR 0x00
+   #define OLED_DATA_ADDR 0x40
+
+reg = 0x00， 表示发送的是命令，更准确的说是OLED配置参数、控制参数。reg = 0x40, 表示发送的是数据。
+val , 指定要发送的内容。
+
+函数实现分为两部分。第一部分，将函数入口参数保存到局部变量 data[] 数组中，便于后面执行发送，调用ioctl 函数设置 IIC 从地址既oled 的地址，当oled检测到与自己对应的
+地址时就会响应，这时就可通信了。 oled 地址定义如下所示：
+
+.. code-block:: sh
+   :caption: oled（base_code\linux_app\i2c\oled\sources\main.c文件）
+   :linenos:
+
+   #define OLED_ADDRESS 0x3C   //通过调整0R电阻,屏可以0x78和0x7A两个地址 -- 默认0x78 
+
+野火 oled 显示屏默认的IIC从地址为0X78,通过调整电阻可以设置为0X7A,需要注意的是，这里的地址是8位地址，最后一位表示的是读或者写。而我们这里要发送的是IIC设备的
+7位地址，如上代码所示，我们在宏定义中设置的IIC 地址是由0x78 左移一位得到的。
+
+第二部分，执行发送，如果一次发送不成功则循环发送5次，都失败的情况下返回-1，有一次成功则返回 0 。如果使用的是其他OLED显示屏必须保证支持IIC接口。
+
+
+oled 初始化函数OLED_Init。oled初始化函数实现很简单。只需要使用open 打开IIC_1接口的设备文件后，使用上面所讲的oled_i2c_write函数写入配置参数即可，部分代码如下所示
+完整代码请参考本实验源码。
+
+
+.. code-block:: c
+   :caption: oled初始化（base_code\linux_app\i2c\oled\sources\main.c文件）
+   :linenos: 
+
+   void OLED_Init(void)
+   {
+     /*---------------------第一部分---------------------*/
+       fd = open("/dev/i2c-0", O_RDWR); // open file and enable read and  write
+   
+       if (fd < 0)
+       {
+           perror("Can't open /dev/i2c-0 \n"); // open i2c dev file fail
+           exit(1);
+       }
+       
+       /*发送 从设备地址， 这里就是 oled的地址*/
+       if (ioctl(fd, I2C_SLAVE, OLED_ADDRESS) < 0)
+       { //set i2c address
+           printf("fail to set i2c device slave address!\n");
+           close(fd);
+       }
+      
+     /*---------------------第一部分---------------------*/
+       oled_i2c_write(fd, OLED_COMMEND_ADDR, 0xAE); //display off
+       oled_i2c_write(fd, OLED_COMMEND_ADDR, 0x20); //
+       oled_i2c_write(fd, OLED_COMMEND_ADDR, 0x10); //00,Horizontal Addressing Mode;
+       oled_i2c_write(fd, OLED_COMMEND_ADDR, 0xb0); //Set Page Start Address for Page Addressing Mode,0-7
+       oled_i2c_write(fd, OLED_COMMEND_ADDR, 0xc8); //Set COM Output Scan Direction
+   }
+
+结合以上代码讲解如下，
+
+第一部分, 打开IIC 设备文件，使用ioctl函数发送 oled 设备地址。正常情况下 oled 设备会有响应。
+第二部分，使用oled_i2c_write向 oled 发送配置信息和控制信息，这部分内容完成了oled的初始化。配置参数非常多这里只列出了部分初始化代码，完整内容请
+参考源码。
+
+
+
+全屏填充函数OLED_Fill，全屏填充函数和清屏函数相似，全屏填充函数点亮每一个像素点而清屏函数熄灭每一个像素点，在程序中前者是写入0xff，后者写入0x00,
+函数实现如下所示：
+
+.. code-block:: c
+   :caption: oled填充（base_code\linux_app\i2c\oled\sources\main.c文件）
+   :linenos: 
+
+   void OLED_Fill(unsigned char fill_Data) //全屏填充
+   {
+       unsigned char m, n;
+       /*---------------------第一部分---------------------*/
+       for (m = 0; m < 8; m++)
+       {
+           oled_i2c_write(fd, OLED_COMMEND_ADDR, 0xb0 + m); //page0-page1
+           oled_i2c_write(fd, OLED_COMMEND_ADDR, 0x00);     //low column start address
+           oled_i2c_write(fd, OLED_COMMEND_ADDR, 0x10);     //high column start address
+          /*---------------------第二部分---------------------*/
+           for (n = 0; n < 128; n++)
+           {
+               // WriteDat(fill_Data);
+               oled_i2c_write(fd, OLED_DATA_ADDR, fill_Data); //high column start address
+           }
+       }
+   }
+
+全屏填充函数由两个嵌套的for 循环组成，默认情况下没每8行像素组成"一行"，oled显示屏一列有64个
+像素点，所以外层循环可取0到7。内层循环用于设置"一行"，oled一行有
+128个像素点，内层循环要执行128次，oled_i2c_write函数每次写入一个8位的数据代表8个像素点的状
+态，准确的说，内层循环执行完成（循环128次）实际写入8行像素点。
+
+
+
+oled 字符串显示函数OLED_ShowStr，oled字符串显示函数只能显示F6x8和F8X16两种字体，F6x8既每个
+字符宽度为6个像素高度为8个像素，F6x8和F8X16都是通过字库生成软件手动生成的，有兴趣可以自己制作其他字库。
+字符串显示函数如下所示：
+
+.. code-block:: c
+   :caption: oled显示（base_code\linux_app\i2c\oled\sources\main.c文件）
+   :linenos: 
+
+   void OLED_ShowStr(unsigned char x, unsigned char y, unsigned char ch[], unsigned char TextSize)
+   {
+   	unsigned char c = 0,i = 0,j = 0;
+   	switch(TextSize)
+   	{
+   
+       /*---------------------第一部分---------------------*/
+   		case 1:
+   		{
+   			while(ch[j] != '\0')
+   			{
+   				c = ch[j] - 32;
+   				if(x > 126)
+   				{
+   					x = 0;
+   					y++;
+   				}
+   				oled_set_Pos(x,y);
+   				for(i=0;i<6;i++)
+   					oled_i2c_write(fd, OLED_DATA_ADDR,F6x8[c][i]);
+   				x += 6;
+   				j++;
+   			}
+   		}break;
+       /*---------------------第二部分---------------------*/
+   		case 2:
+   		{
+   			while(ch[j] != '\0')
+   			{
+   				c = ch[j] - 32;
+   				if(x > 120)
+   				{
+   					x = 0;
+   					y++;
+   				}  
+   				oled_set_Pos(x,y);
+   				for(i=0;i<8;i++)
+   					oled_i2c_write(fd, OLED_DATA_ADDR,F8X16[c*16+i]);
+   				oled_set_Pos(x,y+1);
+   				for(i=0;i<8;i++)
+   					oled_i2c_write(fd, OLED_DATA_ADDR,F8X16[c*16+i+8]);
+   				x += 8;
+   				j++;
+   			}
+   		}break;
+   	}
+   }
+
+函数共有四个参数, x, y 用于设置字符显示的位置，因字符编码的不同，x和y的取值
+范围不是固定的，以F8X16为例，每写入一个字符 x需要自加8，根据oled分辨率可知
+x最大可取128-8-1（像素点从零开始），每写入一个字符 Y 需要自增 16个像素。我们知
+道8行像素组成"一行"，实际 y 可取 0到7,由于每写入一个字符 y 需要自增16个
+像素，所以y可取 0到6。ch[]，指定要写入的字符串。TextSize 指定字体大小，当前该函数只支持两
+种字体，TextSize = 1 使用F6x8字体格式，TextSize = 2使用F8X16字体格式。
+
+
+
+其他显示函数类似，这里不再一一介绍。
+
+
+
+
+.. code-block:: c
+   :caption: 主函数（base_code\linux_app\i2c\oled\sources\main.c文件）
+   :linenos: 
+
+   int main(int argc, char *argv[])
+   {
+       int i = 0; //用于循环
+   
+       OLED_Init(); //初始化oled
+       usleep(1000 * 100);
+       OLED_Fill(0xff); //全屏填充
+   
+       while (1)
+       {
+           OLED_Fill(0xff); //全屏填充
+           sleep(1);
+   
+           OLED_CLS(); //清屏
+           sleep(1);
+   
+           OLED_ShowStr(0, 3, (unsigned char *)"Wildfire Tech", 1);  //测试6*8字符
+           OLED_ShowStr(0, 4, (unsigned char *)"Hello wildfire", 2); //测试8*16字符
+           sleep(1);
+           OLED_CLS(); //清屏
+   
+           for (i = 0; i < 4; i++)
+           {
+               OLED_ShowCN(22 + i * 16, 0, i); //测试显示中文
+           }
+           sleep(1);
+           OLED_CLS(); //清屏
+   
+           OLED_DrawBMP(0, 0, 128, 8, (unsigned char *)BMP1); //测试BMP位图显示
+           sleep(1);
+           OLED_CLS(); //清屏
+       }
+   
+       close(fd);
+   }
+
+主函数的实现比较简单，直接调用前面讲解的函数即可。在while(1)死循环中依次执行全屏填充、清屏、显示英文字符、显示汉字、显示图片测试函数。
+
+
+下载验证
+~~~~~~~~~~
+
+ARM架构
+'''''''''''''''
+
+对于ARM架构的程序，可使用如下步骤进行编译：
+
+.. code-block:: sh
+   :linenos:
+
+   #在主机的实验代码Makefile目录下编译
+   #编译arm平台的程序
+   make ARCH=arm
+
+编译后生成的ARM平台程序为build_arm/oled_demo，使用网络文件系统共享至开
+发板，在开发板的终端上测试即可。
+
+如下图:
+
+.. image:: media/i2c/i2cbus022.png
+   :align: center
+   :alt: 未找到图片
+
+实物图:
+
+.. image:: media/i2c/i2cbus023.png
+   :align: center
+   :alt: 未找到图片
 
 
 .. |i2cbus002| image:: media/i2c/i2cbus002.png
@@ -374,3 +958,11 @@ i2cdump -f -y -r 0x3B-0x48 0 0x68
 .. |i2cbus011| image:: media/i2c/i2cbus011.jpg
    :width: 5.78538in
    :height: 2.74747in
+.. |i2cbus012| image:: media/i2c/i2cbus012.jpg
+
+.. |i2cbus013| image:: media/i2c/i2cbus013.jpg
+
+.. |i2cbus013| image:: media/i2c/i2cbus014.png
+.. |i2cbus013| image:: media/i2c/i2cbus015.png
+.. |i2cbus013| image:: media/i2c/i2cbus016.png
+
diff --git a/documentation/linux_app/input_subsystem.rst b/documentation/linux_app/input_subsystem.rst
index f2e5b97d5d8242810e9f4b905db31641f01d10b5..03af8e0f46aa898052b3764db5596373b4fb5827 100644
--- a/documentation/linux_app/input_subsystem.rst
+++ b/documentation/linux_app/input_subsystem.rst
@@ -1,381 +1,384 @@
 .. vim: syntax=rst
 
 检测按键输入（input子系统）
-----------------
+------------------------------------------------
 
 本章讲解Linux input输入子系统驱动相关应用层程序的控制原理。
 
-本章的示例代码目录为：base_code/section2/input。
+本章的示例代码目录为：base_code/linux_app/input。
 
 input子系统
-~~~~~~~~
+~~~~~~~~~~~~~~~~~~~~~~~~
 
 input子系统是Linux对输入设备提供的统一驱动框架。如按键、键盘、触摸屏和鼠标等输入设备的驱动方式是类似的，当出现按键、触摸等操作时，硬件产生中断，然后CPU直接读取引脚电平，或通过SPI、I2C等通讯方式从设备的寄存器读取具体的按键值或触摸坐标，然后把这些信息提交给内核。使用input子系统
 驱动的输入设备可以通过统一的数据结构提交给内核，该数据结构包括输入的时间、类型、代号以及具体的键值或坐标，而内则通过/dev/input目录下的文件接口传递给用户空间。
 
-在Linux内核源码的“Documentation/input”目录包含了input子系统相关的说明。
+在Linux内核源码的"Documentation/input"目录包含了input子系统相关的说明。
 
 本开发板默认的出厂镜像中，按键、触摸屏、鼠标、键盘都使用了input子系统驱动，本章使用按键进行讲解。
 
 input事件目录
-~~~~~~~~~
+~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
 使用evtest工具测试
-^^^^^^^^^^^^
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 
 在开发input子系统驱动时，常常会使用evtest工具进行测试，此处我们通过该工具来了解Ubuntu主机或开发板上的输入设备。
 
 在Ubuntu主机下使用如下命令测试：
 
-#在主机下执行如下命令
+.. code-block:: sh
+   :linenos:
 
-#安装evtest工具
+   #在主机下执行如下命令
+   #安装evtest工具
+   sudo apt install evtest -y
+   #使用sudo权限运行evtest工具
+   sudo evtest
+   #根据自己主机的输出来选择某个设备测试，下图选择的是"6"，鼠标
+   #根据选择的设备测试，如选择的键盘就按键盘，选择鼠标就移植鼠标
 
-sudo apt install evtest
+如下图:
 
-#使用sudo权限运行evtest工具
+.. image:: media/inputs002.png
+   :align: center
+   :alt: 未找到图片02|
 
-sudo evtest
 
-#根据自己主机的输出来选择某个设备测试，下图选择的是“6”，鼠标
 
-#根据选择的设备测试，如选择的键盘就按键盘，选择鼠标就移植鼠标
+上图的执行过程说明如下：
 
-|inputs002|
+-  运行evtest工具，它列出了系统当前可用的/dev/input/event0~6输入事件
+   文件，并且列出了这些事件对应的设备名。
 
-图 22‑1 在主机上的evtest
+-  我们根据设备名的"VirtualBox mouse intergration"推猜它就是接入到电脑
+   的鼠标，所以输入了它对应的event6事件编号6，实验时请根据自己电脑的输出来选择。
 
-图 22‑1的执行过程说明如下：
+-  输入编号后它列出了event6的一些设备信息，包括驱动版本、设备ID、设备
+   名、支持的事件类型、事件代号以及输入值的取值范围。
 
--  运行evtest工具，它列出了系统当前可用的/dev/input/event0~6输入事件文件，并且列出了这些事件对应的设备名。
-
--  我们根据设备名的“VirtualBox mouse intergration”推猜它就是接入到电脑的鼠标，所以输入了它对应的event6事件编号6，实验时请根据自己电脑的输出来选择。
-
--  输入编号后它列出了event6的一些设备信息，包括驱动版本、设备ID、设备名、支持的事件类型、事件代号以及输入值的取值范围。
-
--  此时移动鼠标，可以看到它输出了详细的事件信息，如果移动后没有输出，说明你选择的不是鼠标设备，请退出重新选择。输出信息中每一行包含了鼠标上报事件的具体时间time、事件类型type 3（EV_ABS）、事件代号code
-  1或code0（ABS_Y或ABS_X）和具体的值value，该值就是鼠标X/Y的坐标。
+-  此时移动鼠标，可以看到它输出了详细的事件信息，如果移动后没有输出，说明
+   你选择的不是鼠标设备，请退出重新选择。输出信息中每一行包含了鼠标上报事件的具
+   体时间time、事件类型type 3（EV_ABS）、事件代号code
+   1或code0（ABS_Y或ABS_X）和具体的值value，该值就是鼠标X/Y的坐标。
 
 input事件结构
-^^^^^^^^^
-
-evtest工具的原理并不神秘，学习本章节后也可以尝试自己使用代码实现它的部分功能。列出可用事件时，它就是通过查看目录“/dev/input/”实现的。本示例中主机的“/dev/input”目录的内容如图 22‑2。
-
-|inputs003|
-
-图 22‑2 /dev/input目录的内容
+^^^^^^^^^^^^^^^^^^^^^^^^^^^
 
-可看到“/dev/input”目录下，有event*、js*、mouse*及mice文件，它们分别是驱动层evdev（通用输入事件）、joydev（游戏杆）及遗留的mousedev（鼠标）设备暴露到用户空间的访问接口文件，读取这些文件的内容可获取到设备上报的信息。
+evtest工具的原理并不神秘，学习本章节后也可以尝试自己
+使用代码实现它的部分功能。列出可用事件时，它就是通过查
+看目录"/dev/input/"实现的。本示例中主机的"/dev/input"目录的内
+容如下图所示。
 
-在前面LED、GPIO子系统中，brightness、direction等设备文件直接使用字符串来记录具体的信息，所以使用cat命令输出文件的内容时，字符串的形式非常方便我们阅读。但是event文件包含的信息较多，使用字符串不方便其它程序处理，它采用了纯粹的内核事件数据结构来记录内容，其它程序使用时
-应把读取到的内容按数据的结构进行格式化转换，该数据结构定义见代码清单 22‑1。
+.. image:: media/inputs003.png
+   :align: center
+   :alt: 未找到图片03|
 
-代码清单 22‑1 input_event结构体（内核源码的/include/uapi/linux/input.h文件）
 
-1 struct input_event {
+可看到"/dev/input"目录下，有event*、js*、mouse*及mice文件，它们分别是
+驱动层evdev（通用输入事件）、joydev（游戏杆）及遗留的mousedev（鼠标）设备暴露
+到用户空间的访问接口文件，读取这些文件的内容可获取到设备上报的信息。
 
-2 struct timeval time;
+在前面LED、GPIO子系统中，brightness、direction等设备文件直接使用字符串来记
+录具体的信息，所以使用cat命令输出文件的内容时，字符串的形式非常方便我们阅读。但是event文件包
+含的信息较多，使用字符串不方便其它程序处理，它采用了纯粹的内核事件数据结构来记录内容，其它
+程序使用时
+应把读取到的内容按数据的结构进行格式化转换，该数据结构定义如下所示。
 
-3 \__u16 type;
+.. code-block:: c
+   :caption: input_event结构体（内核源码的/include/uapi/linux/input.h文件）
+   :linenos:
 
-4 \__u16 code;
+   struct input_event {
+   struct timeval time;
+   __u16 type;
+   __u16 code;
+   __s32 value;
+   };
 
-5 \__s32 value;
+-  time：该变量用于记录事件产生的时间戳，既evtest输出的time值。
 
-6 };
+-  type：输入设备的事件类型。系统常用的默认类型有EV_KEY、 EV_REL和EV_ABS，分别用
+   于表示按键状态改变事件、相对坐标改变事件及绝对坐标改变事件，特别地，EV_SYN用于分隔事件，无特别意义。如果选择鼠标（本章第一个图）
+   evtest输出的type类型为EV_ABS。相关的枚举值可以参考内核文件include/uapi/linux/input-event-codes.h。
 
--  time：该变量用于记录事件产生的时间戳，如图 22‑1中evtest输出的time值。
+-  code：事件代号，它以更精确的方式表示事件。例如
+   在EV_KEY事件类型中，code的值常用于表
+   示键盘上具体的按键，其取值范围在0~127之间，例如按键Q对应的是KEY_Q，该枚举变量的
+   值为16。如果选择鼠标， evtest输出内容的code分别有ABS_X/ABS_Y，表示上报的是X或Y坐标。
 
--  type：输入设备的事件类型。系统常用的默认类型有EV_KEY、 EV_REL和EV_ABS，分别用于表示按键状态改变事件、相对坐标改变事件及绝对坐标改变事件，特别地，EV_SYN用于分隔事件，无特别意义。在图 22‑1
-  中evtest输出的type类型为EV_ABS。相关的枚举值可以参考内核文件include/uapi/linux/input-event-codes.h。
+-  value：事件的值。对于EV_KEY事件类型，当按键按下时，该值为1；按键松开时，该值为0。如果选择
+   鼠标，中evtest输出的内容里，ABS_X事件类型中的value值表示X坐标，ABS_Y类型中的value值表示Y坐标。
 
--  code：事件代号，它以更精确的方式表示事件。例如在EV_KEY事件类型中，code的值常用于表示键盘上具体的按键，其取值范围在0~127之间，例如按键Q对应的是KEY_Q，该枚举变量的值为16。在图 22‑1中 evtest输出内容的code分别有ABS_X/ABS_Y，表示上报的是X或Y坐标。
-
--  value：事件的值。对于EV_KEY事件类型，当按键按下时，该值为1；按键松开时，该值为0。在图 22‑1 中evtest输出的内容里，ABS_X事件类型中的value值表示X坐标，ABS_Y类型中的value值表示Y坐标。
-
-如果同样使用cat命令查看事件文件，当事件出现时，cat把内容转化成字符串，会看到乱码，使用这样的方式可以简单地查看设备是否上报了事件。
+如果同样使用cat命令查看事件文件，当事件出现时，cat把内容转化成字
+符串，会看到乱码，使用这样的方式可以简单地查看设备是否上报了事件。
 
 可使用以下方式可进行测试：
 
-#根据自己主机上的事件号修改要查看的具体事件文件
+.. code-block:: sh
+   :linenos:
 
-#此处使用的event6是本主机的鼠标设备，注意要使用sudo权限
+   #根据自己主机上的事件号修改要查看的具体事件文件
+   #此处使用的event6是本主机的鼠标设备，注意要使用sudo权限
+   sudo cat /dev/input/event6
+   #输入命令后移动鼠标，会看到字符
 
-sudo cat /dev/input/event6
+如下图；
 
-#输入命令后移动鼠标，会看到字符
+.. image:: media/inputs004.jpg
+   :align: center
+   :alt: 未找到图片04|
 
-|inputs004|
 
-图 22‑3 移动鼠标时会出现乱码字符
 
-与其它文件不同，通常cat命令读取文件内容后就会返回，而此处读取event文件时，命令会持续地等待输入。
+与其它文件不同，通常cat命令读取文件内容后就会返回，而此处读取event文件时，命
+令会持续地等待输入。
 
 input事件设备名
-^^^^^^^^^^
-
-“/dev/input/event*”的事件编号与设备的联系不是固定的，它通常按系统检测到设备的先号顺序安排event文件的编号，这对编写应用程序控制不太方便，我们可以通过“/dev/input/by-id”或“/dev/input/by-path”目录查看具体的硬件设备，如图 22‑4。
-
-|inputs005|
-
-图 22‑4 by-path目录
-
-图中列出了by-path目录下的内容，该目录下的文件实际上都是链接，如第一行的“pci-0000:00:04.0-event-mouse -> ../event6”表示“pci-0000:00:04.0-event-
-mouse”文件就是event6的快捷方式，它就是本主机中使用的鼠标，也就是说访问该文件就是访问该鼠标的事件设备，而且该文件名与硬件的关系是固定的，后面我们的实验就是采用这样的方式。
-
-由于/dev下的设备都是通过/sys导出的，所以也可以通过“/sys/class/input”目录查看，如图 22‑5。
-
-|inputs006|
-
-图 22‑5 event*/device/name
-
-“/sys/class/input”下包含了各个以事件命名的目录，其对应目录下的device/name文件包含了事件对应的设备名，如本示例中的“/sys/class/input/event6/device/name”文件的内容为“VirtualBox mouse
-integration”，evtest工具列出的事件与设备名的关系，就是从这里读取的。
-
-按键检测实验
-~~~~~~
-
-本开发板出厂的镜像中默认包含evtest工具，可以在开发板的终端上重现前面在Ubuntu主机上进行的操作。
-
-下面以简单的操作对开发板上的设备进行说明：
-
-#在开发板的终端执行如下命令：
-
-#查看存在的输入设备，截图中是板子接了屏幕和鼠标的情况
-
-evtest
-
-#查看按键在by-path目录下的文件
-
-ls -lh /dev/input/by-path
-
-#查看按键在/sys文件系统中的名字,以下命令中的“event3”根据自己的实验环境修改
-
-cat /sys/class/input/event3/device/name
-
-|inputs007|
-
-图 22‑6 开发板上的gpio-keys设备
-
-此处主要针对开发板上的按键设备进行说明，在图 22‑6中，event0和event3分别对应了开发板的“ON/OFF”和“KEY”按键，注意如果开发板上连接了触摸屏或鼠标键盘等其它输入设备时，按键使用的event*编号可能会发生变化，所以我们查看了“by-
-path”目录下的链接文件，这两个按键的文件链接名分别为“platform-20cc000.snvs:snvs-powerkey-event”和“platform-gpio-keys-event”，下面我们使用这两个文件名编写按键检测的应用程序。
-
-实验代码分析
-^^^^^^
-
-在输入事件检测的应用中，通常使用主线程直接循环读取“/dev/input/event*”设备文件获取事件的数据结构，然后通过消息队列通知其它子线程，从而响应输入操作。
-
-本实验的代码目录为：base_code/section2/input/c。
-
-本实验仅使用了一个main.c文件，见代码清单 22‑2。
-
-代码清单 22‑2 输入设备检测（base_code/section2/input/c/main.c文件）
-
-1 #include <stdio.h>
-
-2 #include <unistd.h>
-
-3 #include <stdlib.h>
-
-4 #include <sys/types.h>
-
-5 #include <sys/stat.h>
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 
-6 #include <fcntl.h>
+"/dev/input/event*"的事件编号与设备的联系不是固定的，它通常按系统检测
+到设备的先号顺序安排event文件的编号，这对编写应用程序控制不太方便，我们
+可以通过"/dev/input/by-id"或"/dev/input/by-path"目录查看具体的硬件设备，如
+下图所示。
 
-7 #include <linux/input.h>
+.. image:: media/inputs005.png
+   :align: center
+   :alt: 未找到图片05|
 
-8 #include <linux/input-event-codes.h>
 
-9
 
-10
+图中列出了by-path目录下的内容，该目录下的文件实际上都是链接，如第
+一行的"pci-0000:00:04.0-event-mouse -> ../event6"表示"pci-0000:00:04.0-event-
+mouse"文件就是event6的快捷方式，它就是本主机中使用的鼠标，也就是说访问该
+文件就是访问该鼠标的事件设备，而且该文件名与硬件的关系是固定的，后面我们的实验就是采用这样的方式。
 
-11 //开发板上的KEY按键，请根据实际情况修改
+由于/dev下的设备都是通过/sys导出的，所以也可以通过"/sys/class/input"目
+录查看，如下图所示。
 
-12 const char default_path[] = "/dev/input/by-path/platform-gpio-keys-event";
+.. image:: media/inputs006.png
+   :align: center
+   :alt: 未找到图片06|
 
-13
 
-14 //开发板上的ON_OFF按键，请根据实际情况修改
 
-15 //const char default_path[] = "/dev/input/by-path/platform-20cc000.snvs:snvs-powerkey-event";
+"/sys/class/input"下包含了各个以事件命名的目录，其对应目录
+下的device/name文件包含了事件对应的设备名，如本示例中
+的"/sys/class/input/event6/device/name"文件的内容为"VirtualBox mouse
+integration"，evtest工具列出的事件与设备名的关系，就是从这里读取的。
 
-16
+开发板按键检测实验
+~~~~~~~~~~~~~~~~~~
 
-17
+开发板执行以下命令，安装evtest工具:
 
-18 int main(int argc, char \*argv[])
+.. code-block:: sh
+   :linenos:
 
-19 {
+   sudo apt install evtest -y
 
-20 int fd;
-
-21 struct input_event event;
-
-22 char \*path;
-
-23
-
-24 printf("This is a input device demo.\n");
-
-25
-
-26 //若无输入参数则使用默认事件设备
-
-27 if (argc > 1)
-
-28 path = argv[1];
-
-29 else
-
-30 path = (char \*)default_path;
-
-31
-
-32 fd = open(path, O_RDONLY);
-
-33 if (fd < 0) {
-
-34 printf("Fail to open device:%s.\n"
-
-35 "Please confirm the path or you have permission to do this.\n", path);
-
-36 exit(1);
-
-37 }
-
-38
-
-39 printf("Test device: %s.\nWaiting for input...\n", path);
-
-40
-
-41 while (1) {
-
-42 if (read(fd, &event, sizeof(event)) == sizeof(event)) {
-
-43
-
-44 //EV_SYN是事件分隔标志，不打印
-
-45 if (event.type != EV_SYN)
-
-46 printf("Event: time %ld.%ld, type %d, code %d,value %d\n",
-
-47 event.time.tv_sec,event.time.tv_usec,
-
-48 event.type,
-
-49 event.code,
-
-50 event.value);
+下面以简单的操作对开发板上的设备进行说明：
 
-51 }
+.. code-block:: sh
+   :linenos:
 
-52 // printf("Read end\n");
+   #在开发板的终端执行如下命令：
+   #查看存在的输入设备，截图中是板子接了鼠标的情况
+   evtest
+   #查看按键在by-path目录下的文件
+   ls -lh /dev/input/by-path
+   #查看按键在/sys文件系统中的名字,以下命令中的"event0"根据自己的实验环境修改
+   cat /sys/class/input/event0/device/name
 
-53 }
+如下图：
 
-54 close(fd);
+.. image:: media/inputs007.png
+   :align: center
+   :alt: 未找到图片07|
 
-55
 
-56 return 0;
 
-57 }
+此处主要针对开发板上的按键设备进行说明，在上图中，event0和event1分别对应
+了开发板的"KEY"按键和USB鼠标按键，注意如果开发板上设备树使用了其他按键，按键使用的event*编号可能会发生变化，
+所以我们查看了"by-path"目录下的链接文件，
+这两个按键的文件链接名分别为"platform-gpio-keys-event"和"platform-ci_hdrc.1-usb-0:1.1:1.0-event-mouse".
+下面我们使用这两个文件名编写按键检测的应用程序。
 
-58
+实验代码分析
+^^^^^^^^^^^^^^^^^^^^^^^^
+
+在输入事件检测的应用中，通常使用主线程直接
+循环读取"/dev/input/event*"设备文件获取事件的数据结构，然后通过消
+息队列通知其它子线程，从而响应输入操作。
+
+本实验的代码目录为：base_code/linux_app/input/c。
+
+本实验仅使用了一个main.c文件，如下所示。
+
+.. code-block:: c
+   :caption:  输入设备检测（base_code/linux_app/input/c/main.c文件）
+   :linenos:
+
+   #include <stdio.h>
+   #include <unistd.h>
+   #include <stdlib.h>
+   #include <sys/types.h>
+   #include <sys/stat.h>
+   #include <fcntl.h>
+   #include <linux/input.h>
+   #include <linux/input-event-codes.h>
+   
+
+   //开发板上的KEY按键，请根据实际情况修改 
+   const char default_path[] = "/dev/input/by-path/platform-gpio-keys-event";
+
+   //开发板上的ON_OFF按键，请根据实际情况修改
+   //const char default_path[] = "/dev/input/by-path/platform-ci_hdrc.1-usb-0:1.1:1.0-event-mouse";
+
+
+   int main(int argc, char *argv[])
+   {
+      int fd;
+      struct input_event event;
+      char *path;
+      
+      printf("This is a input device demo.\n");
+
+      //若无输入参数则使用默认事件设备
+      if(argc > 1)
+         path = argv[1];
+      else
+         path = (char *)default_path;
+
+      fd = open(path, O_RDONLY);
+      if(fd < 0){
+         printf("Fail to open device:%s.\n"
+               "Please confirm the path or you have permission to do this.\n", path);
+         exit(1);
+      }	
+      
+      printf("Test device: %s.\nWaiting for input...\n", path);
+      
+      while(1){
+         if(read(fd, &event, sizeof(event)) == sizeof(event)){
+            
+            //EV_SYN是事件分隔标志，不打印
+            if(event.type != EV_SYN)
+               printf("Event: time %ld.%ld, type %d, code %d,value %d\n",			
+                     event.time.tv_sec,event.time.tv_usec,
+                     event.type,
+                     event.code,
+                     event.value);
+         }
+      }
+      close(fd);
+
+      return 0;
+   }
 
 本代码的说明如下：
 
--  第12行：定义默认设备路径，此处使用的是开发板KEY按键在“/dev/input/by-path”下的链接文件名，此处不使用“/dev/input/event*”只是为了让程序不受其它输入设备而影响了事件编号。
+-  第12行：定义默认设备路径，此处使用的是开发板KEY按键
+   在"/dev/input/by-path"下的链接文件名，此处不使用"/dev/input/event*"只是
+   为了让程序不受其它输入设备而影响了事件编号。
 
--  第26~30行：检查main函数的输入参数，若程序执行时带输入参数，把第1个输入参数作为要打开的事件设备文件路径，若程序不带参数，则使用上面的默认设备KEY按键的事件设备文件。
+-  第25~29行：检查main函数的输入参数，若程序执行时带输入参数，把第1个输入
+   参数作为要打开的事件设备文件路径，若程序不带参数，则使用上面的默认设备KEY按键的事件设备文件。
 
--  第32~37行：使用O_RDONLY模式打开事件设备文件，O_RDONLY模式默认是阻塞型的，而且事件设备文件支持阻塞操作，也就是说，若后面使用read函数读取时，它会等待事件上报，一直等待至读取成功或失败才会返回。
+-  第31~36行：使用O_RDONLY模式打开事件设备文件，O_RDONLY模式默认是阻塞
+   型的，而且事件设备文件支持阻塞操作，也就是说，若后面使用read函数读取时，它会
+   等待事件上报，一直等待至读取成功或失败才会返回。
 
--  第42行：在while循环里通过read系统调用读取事件文件，读取到的内容存储在 “struct input_event”类型的event变量中，“struct
-  input_event”类型就是前面介绍的内核事件数据结构。若成功读取，我们就可以通过该变量的结构体成员访问到事件的时间戳、类型、代号和值。
+-  第41行：在while循环里通过read系统调用读取事件文件，读取到的内容存储在 "struct input_event"类型
+   的event变量中，"struct input_event"类型就是前面介绍的内核事件数据结构。
+   若成功读取，我们就可以通过该变量的结构体成员访问到事件的时间戳、类型、代号和值。
 
--  第46~50行：输出读取到的event变量的各个成员值，在上报的事件中，通常会有很多类型为EV_SYN的事件，这种事件是用于分隔的，无特别意义，所以代码中不输出这类型事件的内容。
+-  第45~49行：输出读取到的event变量的各个成员值，在上报
+   的事件中，通常会有很多类型为EV_SYN的事件，这种事件是用于分隔的，无特别
+   意义，所以代码中不输出这类型事件的内容。
 
 值得思考的是，若没有上报事件，第42行的read读取事件设备文件操作会被阻塞，简单来说就是即使第52行的printf代码不注释掉，它也不会在持续地在循环里输出，而只有当出现了事件，触发read退出，后面的printf函数才有机会被执行一次，然后重新read事件再次阻塞。在这种阻塞的过程中，进程会休眠
 ，释放它对CPU的占用。
 
-假如我们使用的是GPIO子系统框架来编写按键驱动程序，在应用层的操作中，需要使用“/sys/class/gpio/gpio*/direction”文件配置为输入方向，然后使用循环读取“/sys/class/gpio/gpio*/value”文件的值来获得按键的状态，但由于对value文件的read读
+假如我们使用的是GPIO子系统框架来编写按键驱动程序，在应用层的操作中，需要使用"/sys/class/gpio/gpio*/direction"文件配置为输入方向，然后使用循环读取"/sys/class/gpio/gpio*/value"文件的值来获得按键的状态，但由于对value文件的read读
 取操作不会阻塞，所以进程会不停地读取文件内容来判断按键值，占用CPU宝贵的运算资源。
 
 由于read事件文件操作会阻塞，那么采用这种方式就无法同时检测两个输入设备了，这种时候可以通过select或poll等IO多路复用的操作达成目的，这在后续的章节再进行讲解。
 
 编译及测试
-^^^^^
+^^^^^^^^^^^^^^^
 
 本实验使用的Makefile相对于前面的章节仅修改了最终的可执行文件名为input_demo。
 
 x86架构
-'''''
-
-本实验的main.c实验代码使用的事件设备文件默认是开发板上的KEY按键，在Ubuntu主机上并没有这样的设备，如果想尝试在主机上使用，可以根据自己Ubuntu主机上存在的事件作为程序的输入参数输入运行，在x86平台的编译测试过程如下：
-
-#在主机的实验代码Makefile目录下编译
-
-#默认编译x86平台的程序
+''''''''''''''''''''
 
-make
+本实验的main.c实验代码使用的事件设备文件默认是开发板上的KEY按键，在Ubuntu主机上
+并没有这样的设备，如果想尝试在主机上使用，可以根据自己Ubuntu主机上存在的事件作为
+程序的输入参数输入运行，在x86平台的编译测试过程如下：
 
-#运行需要root权限，要使用sudo运行
+.. code-block:: sh
+   :linenos:
 
-#运行需要root权限，要使用sudo运行
+   #在主机的实验代码Makefile目录下编译
+   #默认编译x86平台的程序
+   make
+   #运行需要root权限，要使用sudo运行
+   #使用evtest查看可用的设备文件
+   sudo evtest
+   #请根据自己主机上的输出修改设备文件参数
+   #程序需要使用sudo运行
+   sudo ./build_x86/input_demo /dev/input/event6
+   #使用对应的设备输入，终端会打印出事件的信息
 
-#使用evtest查看可用的设备文件
+如下图:
 
-sudo evtest
+.. image:: media/inputs008.jpg
+   :align: center
+   :alt: 未找到图片08|
 
-#请根据自己主机上的输出修改设备文件参数
 
-#程序需要使用sudo运行
-
-sudo ./build_x86/input_demo /dev/input/event6
-
-#使用对应的设备输入，终端会打印出事件的信息
-
-|inputs008|
-
-图 22‑7在Ubuntu主机上的运行输出（注意要使用sudo执行）
 
 ARM架构
-'''''
+'''''''''''''''
 
 对于ARM架构的程序，可使用如下步骤进行编译：
 
-#在主机的实验代码Makefile目录下编译
-
-#编译arm平台的程序
+.. code-block:: sh
+   :linenos:
 
-make ARCH=arm
+   #在主机的实验代码Makefile目录下编译
+   #编译arm平台的程序
+   make ARCH=arm
 
-编译后生成的ARM平台程序为build_arm/input_demo，使用网络文件系统共享至开发板，程序默认使用KEY按键检测，也可以自行指定输入设备路径。
+编译后生成的ARM平台程序为build_arm/input_demo，使用网络文
+件系统共享至开发板，程序默认使用KEY按键检测，也可以自行指定输入设备路径。
 
-#以下命令在开发板上的终端执行
+.. code-block:: sh
+   :linenos:
 
-#在NFS共享的工程目录路径执行
+   #以下命令在开发板上的终端执行
+   #在NFS共享的工程目录路径执行
+   #使用默认的KEY按键运行
+   #运行需要root权限，要使用sudo运行
+   sudo ./build_arm/input_demo
+   #按下开发板的KEY按键会有输出
+   #也可以指定要测试的事件文件路径
+   sudo ./build_arm/input_demp [事件文件路径]
 
-#使用默认的KEY按键运行
+如下图:
 
-./build_arm/input_demo
+.. image:: media/inputs009.jpg
+   :align: center
+   :alt: 未找到图片09|
 
-#按下开发板的KEY按键会有输出
 
-#也可以指定要测试的事件文件路径
 
-./build_arm/input_demp [事件文件路径]
+使用默认的KEY事件路径，程序执行后，按下开发板的KEY键时，终端输出
+的事件值value为1，释放按键时，输出的事件值value为0。
 
-|inputs009|
 
-图 22‑8 在开发板上的执行现象
 
-使用默认的KEY事件路径，程序执行后，按下开发板的KEY键时，终端输出的事件值value为1，释放按键时，输出的事件值value为0。
 
 .. |inputs002| image:: media/inputs002.png
    :width: 5.76801in
diff --git a/documentation/linux_app/led_subsystem.rst b/documentation/linux_app/led_subsystem.rst
index e8bebcc2c484df3834b1804653972db938a6a1c5..218638d1c8480b4b4f2009be1377d56c0feb82e2 100644
--- a/documentation/linux_app/led_subsystem.rst
+++ b/documentation/linux_app/led_subsystem.rst
@@ -1,49 +1,57 @@
 .. vim: syntax=rst
 
 控制LED灯设备（LED子系统）
-----------------
+------------------------------------------------
 
 本章分别使用C库和系统调用的文件操作方式控制开发板的LED灯，展示如何在应用层通过系统提供的设备文件控制相关硬件。
 
-本章的示例代码目录为：base_code/section2/led/sys_class_leds。
+本章的示例代码目录为：base_code/linux_app/led/sys_class_leds。
 
 LED子系统
-~~~~~~
+~~~~~~~~~~~~
 
 在Linux系统中，绝大多数硬件设备都有非常成熟的驱动框架，驱动工程师使用这些框架添加与板子相关的硬件支持，建立硬件与Linux内核的联系，内核再通过统一文件系统接口呈现给用户，用户通过对应的设备文件控制硬件。
 
-对于LED设备，Linux提供了LED子系统驱动框架，在Linux内核源码中的“Documentation/leds/leds-class.txt”有相关的描述，它实现了一个leds类，用户层通过sysfs文件系统对LED进行控制。
+对于LED设备，Linux提供了LED子系统驱动框架，在Linux内核源码中的"Documentation/leds/leds-class.txt"有相关的描述，它实现了一个leds类，用户层通过sysfs文件系统对LED进行控制。
 
 LED设备目录
-^^^^^^^
+^^^^^^^^^^^^^^
 
 使用了LED子系统驱动的设备，会被展现在/sys/class/leds目录下，可在主机和开发板使用如下命令查看，命令的输出可能会因为硬件环境不同而不一样：
 
-#在主机或ARM板的终端上执行如下命令：
+.. code-block:: sh
+   :linenos:
 
-ls /sys/class/leds/
+   #在主机或ARM板的终端上执行如下命令：
+   ls /sys/class/leds/
 
-#根据具体的目录内容继续查看：
+   #根据具体的目录内容继续查看：
 
-#在主机上有input2::capslock目录，可在主机执行如下命令查看
+   #在主机上有input2::capslock目录，可在主机执行如下命令查看
+   ls /sys/class/leds/input2::capslock
 
-ls /sys/class/leds/input2::capslock
+   #在开发板上有cpu目录，可在开发板上执行如下命令查看
 
-#在开发板上有cpu目录，可在开发板上执行如下命令查看
+   ls /sys/class/leds/cpu
 
-ls /sys/class/leds/cpu
+如下图
 
-|ledsub002|
+.. image:: media/ledsub002.png
+   :align: center
+   :alt: 未找到图片02|
 
-图 20‑1 虚拟机上的LED灯设备
 
-|ledsub003|
+.. image:: media/ledsub003.png
+   :align: center
+   :alt: 未找到图片03|
 
-图 20‑2开发板上的LED灯设备
 
-从图 20‑1和图 20‑2可看到，示例中的Ubuntu主机和开发板/sys/class/leds下包含了以LED设备名字命名的目录，如“input2::capslock”、“input2::numlock”和“blue”、“cpu”等LED灯，这些目录对应的具体LED灯如表 20‑1所示。
 
-表 20‑1 /sys/class/leds下目录对应的设备
+上图可看到，示例中的Ubuntu主机和开发板/sys/class/leds下包含了以LED设备名
+字命名的目录，如"input2::capslock"、"input2::numlock"和"blue"、"cpu"等LED灯，这
+些目录对应的具体LED灯如下表所示。
+
+表 /sys/class/leds下目录对应的设备
 
 ======================= =================================================
 /sys/class/leds下的目录 对应的LED灯设备
@@ -60,17 +68,21 @@ mmc0::                  SD卡指示灯（出厂镜像默认没有启用）
 ======================= =================================================
 
 LED设备属性
-^^^^^^^
+^^^^^^^^^^^^^^^^^^^^^
 
-图 20‑1和图 20‑2中，在具体的LED目录下又包含brightness、max_brightness、trigger等文件，这些文件包含了LED设备的属性和控制接口。
+上图中，在具体的LED目录下又包含brightness、max_brightness、trigger等文件，这些文件包含了LED设备的属性和控制接口。
 
 -  max_brightness文件：表示LED灯的最大亮度值。
 
--  brightness文件：表示当前LED灯的亮度值，它的可取值范围为[0~max_brightness]，一些LED设备不支持多级亮度，直接以非0值来表示LED为点亮状态，0值表示灭状态。
+-  brightness文件：表示当前LED灯的亮度值，它的可取
+   值范围为[0~max_brightness]，一些LED设备不支持多级亮度，直接以非0值来
+   表示LED为点亮状态，0值表示灭状态。
 
--  trigger文件：则指示了LED灯的触发方式，查看该文件的内容时，该文件会列出它的所有可用触方式，而当前使用的触发方式会以“[]”符号括起。常见的触发方式如表 20‑2。
+-  trigger文件：则指示了LED灯的触发方式，查看该文件的内容时，该文件会
+   列出它的所有可用触方式，而当前使用的触发方式会以"[]"符号括起。常见的触
+   发方式如下表所示。
 
-表 20‑2 trigger常见的触发方式
+表 trigger常见的触发方式
 
 ============= ==============
 触发方式      说明
@@ -83,503 +95,277 @@ timer         定时器
 heartbeat     系统心跳
 ============= ==============
 
-控制LED实验（Shell）
-~~~~~~~~~~~~~~
-
-下面通过命令行控制LED来讲解LED设备属性文件的应用。
-
-首先以主机Ubuntu上的“input2::capslock”大写锁定指示灯的文件状态为例，按以下流程进行操作：
-
-#以下命令在主机上执行
-
-#请把“input2::capslock”替换为自己主机上的大写锁定指示灯的设备名字
-
-#查看max_brightness文件内容
-
-cat /sys/class/leds/input2\:\:capslock/max_brightness
-
-#查看trigger文件内容
-
-cat /sys/class/leds/input2\:\:capslock/trigger
-
-#查看brightness文件内容
-
-cat /sys/class/leds/input2\:\:capslock/brightness
-
-#按下键盘的CapsLock大写锁定键（Shift键的上面），再次查看brightness文件的内容
-
-cat /sys/class/leds/input2\:\:capslock/brightness
-
-|ledsub004|
-
-图 20‑3 键盘CapsLock指示灯的控制文件
-
-实验结果如图 20‑3，该指示灯的max_brightness文件表示它的最大亮度值为1，trigger文件中的“[]”括起了“none”，表示当前无触发方式，接着查看brightness文件的内容，第一次查看时为“0”，然后按一下大写锁定键“CapsLock”后，键盘该指示灯亮起，再次查看brig
-htness文件的内容，可发现它的内容已变为“1”，也就是说它与键盘上大写锁定指示灯的状态是一致的。 “NumLock”或“ScrollLock”指示灯也是类似的。
-
-特别地，brightness和trigger文件都是可写的，当trigger文件的内容为none时，直接修改brightness的内容即可控制LED设备的亮度。
-
-在主机上执行以下命令：
-
-#在主机执行以下命令：
-
-#请把“input2::capslock”替换为自己主机上的大写锁定指示灯的设备名字
-
-#点亮大写锁定指示灯
-
-sudo sh -c 'echo 1 > /sys/class/leds/input2\:\:capslock/brightness'
-
-#关闭大写锁定指示灯
-
-sudo sh -c 'echo 0 > /sys/class/leds/input2\:\:capslock/brightness'
-
-|ledsub005|
-
-图 20‑4 通过修改brightness 控制CapsLock指示灯
-
-由于修改sys目录的文件需要root权限，所以我们执行命令时添加了“sudo sh -c”前缀，要求它以root权限执行echo命令，而echo命令的具体内容就是往brightness文件写1和写0，执行命令后观察键盘的CapsLock指示灯，它会呈现出brightness文件对应的状态。
-
-类似地，我们也可以使用同样的方式控制开发板的LED设备：
-
-#以下命令在开发板的终端上执行
-
-#查看red灯的最大亮度值
-
-cat /sys/class/leds/red/max_brightness
-
-#查看red灯的触发方式
-
-cat /sys/class/leds/red/trigger
-
-#查看red灯当前的亮度值
-
-cat /sys/class/leds/red/brightness
-
-#开发板上LED灯默认可能处于亮的状态，我们先把它们全部关闭再一点亮
-
-echo 0 > /sys/class/leds/red/brightness #关闭red灯
-
-echo 0 > /sys/class/leds/blue/brightness #关闭blue灯
-
-echo 0 > /sys/class/leds/green/brightness #关闭green灯
-
-echo 255 > /sys/class/leds/red/brightness #设置red灯亮度值255
-
-echo 127 > /sys/class/leds/red/brightness #设置red灯亮度值127
-
-echo 10 > /sys/class/leds/red/brightness #设置red灯亮度值10
-
-|ledsub006|
-
-图 20‑5 开发板的RGB灯控制
-
-由于开发板上RGB灯的硬件设计和驱动上支持了PWM功能，这几个LED是可以控制亮度值的，并且把亮度值分为了256个等级，对brightness文件赋予[0~255]的值可控制LED灯的亮度，Pro开发板的RGB灯是一体的，可以通过控制三盏灯的亮度值进行混色。
-
-特别地，开发板上的cpu灯默认使用的是“heartbeat”系统心跳的触发方式，所以开发板在上电后它就一直闪烁，在heartbeat方式下LED的亮度是不受brightness文件控制的，要使用的话需要把trigger文件的触发方式改为none。
-
-通过如下命令可查看及修改触发方式：
-
-#以下命令在开发板上的终端上执行
-
-#查看触发方式
-
-cat /sys/class/leds/cpu/trigger
-
-#修改触发方式为none
-
-echo none > /sys/class/leds/cpu/trigger
-
-#修改触发方式为heartbeat
-
-echo heartbeat > /sys/class/leds/cpu/trigger
-
-|ledsub007|
-
-图 20‑6 cpu灯的触发方式
 
 控制LED实验（C库函数）
-~~~~~~~~~~~~~
+~~~~~~~~~~~~~~~~~~~~~~~~~~
 
-前面演示时使用echo命令修改设备文件，实际上也可以使用gedit、Vim等编辑器进行修改，修改时注意用户权限即可。既然设备是以文件形式提供的，那么自然也可以使用C库函数或系统调用的方式读写文件，达到控制设备的目的。
+在《命令行点灯和检测按键》章节中，我们演示了使用echo命令修改设备文件，实际上也可以使用gedit、Vim等编辑器进
+行修改，修改时注意用户权限即可。既然设备是以文件形式提供的，那么自然也可以使用C库函数
+或系统调用的方式读写文件，达到控制设备的目的。
 
 实验代码分析
-^^^^^^
+^^^^^^^^^^^^^^^^^^
 
 本小节的示例代码目录为：led/sys_class_leds/c_stdio。
 
-本小节先演示使用C库函数控制LED，具体见代码清单 20‑1。
-
-代码清单 20‑1通过C库函数控制LED（led/sys_class_leds/c_stdio/sources/main.c文件）
-
-1 #include <stdio.h>
-
-2 #include <stdlib.h>
-
-3 #include <unistd.h>
-
-4
-
-5 //ARM 开发板LED设备的路径
-
-6 #define RLED_DEV_PATH "/sys/class/leds/red/brightness"
-
-7 #define GLED_DEV_PATH "/sys/class/leds/green/brightness"
-
-8 #define BLED_DEV_PATH "/sys/class/leds/blue/brightness"
-
-9
-
-10 //Ubuntu主机LED设备的路径，具体请根据自己的主机LED设备修改
-
-11 // #define RLED_DEV_PATH "/sys/class/leds/input2::capslock/brightness"
-
-12 // #define GLED_DEV_PATH "/sys/class/leds/input2::numlock/brightness"
-
-13 // #define BLED_DEV_PATH "/sys/class/leds/input2::scrolllock/brightness"
-
-14
-
-15
-
-16 int main(int argc, char \*argv[])
-
-17 {
-
-18
-
-19 FILE \*r_fd, \*g_fd, \*b_fd;
-
-20
-
-21 printf("This is the led demo\n");
-
-22 //获取红灯的设备文件描述符
-
-23 r_fd = fopen(RLED_DEV_PATH, "w");
-
-24 if (r_fd < 0) {
-
-25 printf("Fail to Open %s device\n", RLED_DEV_PATH);
-
-26 exit(1);
-
-27 }
-
-28
-
-29 //获取绿灯的设备文件描述符
-
-30 g_fd = fopen(GLED_DEV_PATH, "w");
-
-31 if (g_fd < 0) {
-
-32 printf("Fail to Open %s device\n", GLED_DEV_PATH);
-
-33 exit(1);
-
-34 }
-
-35
-
-36 //获取蓝灯的设备文件描述符
-
-37 b_fd = fopen(BLED_DEV_PATH, "w");
-
-38 if (b_fd < 0) {
-
-39 printf("Fail to Open %s device\n", BLED_DEV_PATH);
-
-40 exit(1);
-
-41 }
-
-42
-
-43 while (1) {
-
-44 //红灯亮
-
-45 fwrite("255",3,1,r_fd);
-
-46 fflush(r_fd);
-
-47 //延时1s
-
-48 sleep(1);
-
-49 //红灯灭
-
-50 fwrite("0",1,1,r_fd);
-
-51 fflush(r_fd);
-
-52
-
-53 //绿灯亮
-
-54 fwrite("255",3,1,g_fd);
-
-55 fflush(g_fd);
-
-56 //延时1s
-
-57 sleep(1);
-
-58 //绿灯灭
-
-59 fwrite("0",1,1,g_fd);
-
-60 fflush(g_fd);
-
-61
-
-62 //蓝灯亮
-
-63 fwrite("255",3,1,b_fd);
-
-64 fflush(b_fd);
-
-65 //延时1s
-
-66 sleep(1);
-
-67 //蓝灯亮
-
-68 fwrite("0",1,1,b_fd);
-
-69 fflush(b_fd);
-
-70 }
-
-71 }
+本小节先演示使用C库函数控制LED，具体如下所示。
+
+.. code-block:: c
+   :caption: 通过C库函数控制LED（base_code/linux_app/led/sys_class_leds/c_stdio/sources/main.c文件）
+   :linenos:
+
+   #include <stdio.h>
+   #include <stdlib.h>
+   #include <unistd.h>
+
+   //ARM 开发板LED设备的路径
+   #define RLED_DEV_PATH "/sys/class/leds/red/brightness"
+   #define GLED_DEV_PATH "/sys/class/leds/green/brightness"
+   #define BLED_DEV_PATH "/sys/class/leds/blue/brightness"
+
+   //Ubuntu主机LED设备的路径，具体请根据自己的主机LED设备修改
+   // #define RLED_DEV_PATH "/sys/class/leds/input2::capslock/brightness"
+   // #define GLED_DEV_PATH "/sys/class/leds/input2::numlock/brightness"
+   // #define BLED_DEV_PATH "/sys/class/leds/input2::scrolllock/brightness"
+
+
+   int main(int argc, char *argv[])
+   {
+      FILE *r_fd, *g_fd, *b_fd;
+
+      printf("This is the led demo\n");
+      //获取红灯的设备文件描述符
+      r_fd = fopen(RLED_DEV_PATH, "w");
+      if(r_fd < 0){
+         printf("Fail to Open %s device\n", RLED_DEV_PATH);
+         exit(1);
+      }
+
+      //获取绿灯的设备文件描述符
+      g_fd = fopen(GLED_DEV_PATH, "w");
+      if(g_fd < 0){
+         printf("Fail to Open %s device\n", GLED_DEV_PATH);
+         exit(1);
+      }
+
+      //获取蓝灯的设备文件描述符
+      b_fd = fopen(BLED_DEV_PATH, "w");
+      if(b_fd < 0){
+         printf("Fail to Open %s device\n", BLED_DEV_PATH);
+         exit(1);
+      }   
+
+      while(1){
+         //红灯亮
+         fwrite("255",3,1,r_fd);
+         fflush(r_fd);
+         //延时1s
+         sleep(1);
+         //红灯灭
+         fwrite("0",1,1,r_fd);
+         fflush(r_fd);
+         
+         //绿灯亮
+         fwrite("255",3,1,g_fd);
+         fflush(g_fd);
+         //延时1s
+         sleep(1);
+         //绿灯灭
+         fwrite("0",1,1,g_fd);
+         fflush(g_fd);
+
+         //蓝灯亮
+         fwrite("255",3,1,b_fd);
+         fflush(b_fd);
+         //延时1s
+         sleep(1);
+         //蓝灯亮
+         fwrite("0",1,1,b_fd);
+         fflush(b_fd);
+      }
+   }
 
 可以发现，这个控制LED灯的过程就是一个普通的文件写入流程：
 
--  第5~13行：定义了三盏LED灯的brightness文件路径。配套的程序默认使用开发板RGB灯的路径，如果要在Ubuntu主机上测试请根据自己主机上的设备文件修改10~13行的内容。
+-  第5~13行：定义了三盏LED灯的brightness文件路径。配套的程序默认使用
+   开发板RGB灯的路径，如果要在Ubuntu主机上测试请根据自己主机上的设备文件修改10~13行的内容。
 
--  第18~41行：使用fopen库函数，以“w”的写模式打开了三盏LED的brightness文件，并获得文件描述符。
+-  第18~41行：使用fopen库函数，以"w"的写模式打开了三盏LED的brightness文件，并获得文件描述符。
 
--  第43~70行：在循环中分别对三盏灯写入"255"和"0"的字符串来控制LED灯的亮度，写入后调用了fflush库函数要求立刻把缓冲区的内容写入到文件上。
+-  第43~70行：在循环中分别对三盏灯写入"255"和"0"的字符串来控制LED灯的亮
+   度，写入后调用了fflush库函数要求立刻把缓冲区的内容写入到文件上。
 
 本代码有两处值得注意的地方：
 
-如果是普通文件，按代码while循环的执行流程，运行一段时间后，由于多次写入，文件中的内容应该为“255025502550255”这样的字符串，但对于此处的brightness设备文件，它的最终内容只是“255”或“0”，而不是像普通文件那样记录了一连串前面输入的字符。这是因为在LED的设备驱动层中
-，brightness文件就相当于一个函数的参数接口，每次对文件执行写入操作时，会触发驱动代码以这次写入的内容作为参数，修改LED灯的亮度；而每次读取操作时，则触发驱动代码更新当前LED灯亮度值到brightness文件，所以brightness始终是一个0~255的亮度值，而不是“25502550
-2550255”这样的字符串。特别地，如果在一次写入操作中，直接写入“0255025502550”这样的字符串，驱动层会把它当成数字255025502550，而该数字大于最大亮度值，所以它最终会以255的亮度控制LED灯，若此时读取brightness文件，也会发现它的值确实是255。关于这些细节，
+如果是普通文件，按代码while循环的执行流程，运行一段时间后，由于多次
+写入，文件中的内容应该为"255025502550255"这样的字符串，但对于此
+处的brightness设备文件，它的最终内容只是"255"或"0"，而不是像普通
+文件那样记录了一连串前面输入的字符。这是因为在LED的设备驱动层中
+，brightness文件就相当于一个函数的参数接口，每次对文件执行写入操
+作时，会触发驱动代码以这次写入的内容作为参数，修改LED灯的亮度；而每次读
+取操作时，则触发驱动代码更新当前LED灯亮度值到brightness文件，所以brightness始终
+是一个0~255的亮度值，而不是"255025502550255"这样的字符串。特别地，
+如果在一次写入操作中，直接写入"0255025502550"这样的
+字符串，驱动层会把它当成数字255025502550，而该数字大于最大亮度值，所以它最终会以255的
+亮度控制LED灯，若此时读取brightness文件，也会发现它的值确实是255。关于这些细节，
 在学习了LED子系统框架后查看驱动源码可更好地了解。
 
-另一处要注意的是代码中调用fwrite函数写入内容时，它可能只是把内容保存到了C库的缓冲区，并没有执行真正的系统调用write函数把内容写入到设备文件，这种情况下LED灯的状态是不会被改变的，代码中在fwrite函数后调用了fflush要求立刻把缓冲区的内容写入到文件，确保执行了相应的操作。在实验时
-可以尝试把代码中的fflush都注释掉，这种情况下有极大的几率是无法正常改变LED灯状态的。
+另一处要注意的是代码中调用fwrite函数写入内容时，它可能只是把内容保存
+到了C库的缓冲区，并没有执行真正的系统调用write函数把内容写入到设备文件，这种情况下LED灯
+的状态是不会被改变的，代码中在fwrite函数后调用了fflush要求立刻把缓冲区的内容写入到文件，确保
+执行了相应的操作。在实验时可以尝试把代码中的fflush都注释掉，
+这种情况下有极大的几率是无法正常改变LED灯状态的。
 
-如果不考虑操作的时间开销，其实控制硬件更推荐的做法是，每次控制LED灯都使用fopen—fwrite—fclose的流程，这样就不需要考虑flseek、fflush的问题了。当然，我们最推崇的还是下一小节直接通过系统调用来控制硬件的方式。
+如果不考虑操作的时间开销，其实控制硬件更推荐的做法是，每次控制LED灯都使用fopen—fwrite—fclose的
+流程，这样就不需要考虑flseek、fflush的问题了。当然，我们最推崇的还是下一小节直接通过
+系统调用来控制硬件的方式。
 
 编译及测试
-^^^^^
+^^^^^^^^^^^^^^^
 
-本实验使用的Makefile由上一章节修改而来，修改了最终的可执行文件名为led_demo，以及C源文件目录改为了main.c文件所在的sources，其它方面没有差异。
+本实验使用的Makefile由上一章节修改而来，修改了最终的可执行文件名为led_demo，以及C源
+文件目录改为了main.c文件所在的sources，其它方面没有差异。
 
 x86架构
-'''''
-
-本工程的main.c实验代码使用的设备文件默认是开发板上的RGB灯，在Ubuntu主机上并没有这样的设备，如果想尝试在主机上使用，可以根据自己Ubuntu主机上存在的LED设备修改代码中的LED路径，然后使用make直接编译测试。
-
-#在主机测试请先修改main.c代码中的LED灯路径
-
-#在主机测试请先修改main.c代码中的LED灯路径
-
-#在主机的实验代码Makefile目录下编译
+'''''''''''''''
 
-#默认编译x86平台的程序
+本工程的main.c实验代码使用的设备文件默认是开发板
+上的RGB灯，在Ubuntu主机上并没有这样的设备，如果想尝试在主机上使用，
+可以根据自己Ubuntu主机上存的LED设备修改代码中的LED路径，然后使用make直接编译测试。
 
-make
+.. code-block:: sh
+   :linenos:
 
-#运行需要root权限，要使用sudo运行
+   #在主机的实验代码Makefile目录下编译
+   #默认编译x86平台的程序
+   make
+   #运行需要root权限，要使用sudo运行
+   #运行需要root权限，要使用sudo运行
+   sudo ./build_x86/led_demo
+   #程序运行后终端会输出提示，相应的LED灯设备状态会改变
 
-#运行需要root权限，要使用sudo运行
-
-sudo ./build_x86/led_demo
-
-#程序运行后终端会输出提示，相应的LED灯设备状态会改变
-
-|ledsub008|
-
-图 20‑7在Ubuntu主机上的运行输出（注意要使用sudo执行）
 
 ARM架构
-'''''
+'''''''''''''''
 
 对于ARM架构的程序，可使用如下步骤进行编译：
 
-#在主机的实验代码Makefile目录下编译
+.. code-block:: sh
+   :linenos:
 
-#编译arm平台的程序
+   #在主机的实验代码Makefile目录下编译
+   #编译arm平台的程序
+   make ARCH=arm
 
-make ARCH=arm
+编译后生成的ARM平台程序为build_arm/led_demo，使用网络文件系统共享至开
+发板，在开发板的终端上测试即可。
 
-编译后生成的ARM平台程序为build_arm/led_demo，使用网络文件系统共享至开发板，在开发板的终端上测试即可。
+如下图:
 
-|ledsub009|
-
-图 20‑8 在开发板上的执行现象
+.. image:: media/ledsub009.png
+   :align: center
+   :alt: 未找到图片09|
 
 程序执行后终端会有输出，开发板上的三盏用户LED灯也会轮流闪烁。
 
 控制LED实验（系统调用）
-~~~~~~~~~~~~~
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
-由于使用C库的文件操作函数存在缓冲机制，使用它来控制硬件时存在不确定性，所以我们更喜欢直接以系统调用来控制硬件设备。
+由于使用C库的文件操作函数存在缓冲机制，使用它来控制硬件时存在不
+确定性，所以我们更喜欢直接以系统调用来控制硬件设备。
 
 .. _实验代码分析-1:
 
 实验代码分析
-^^^^^^
+^^^^^^^^^^^^^^^^^^
 
 本小节的示例代码目录为：led/sys_class_leds/c_systemcall。
 
-本小节通过系统调用的文件操作方式控制LED，具体见代码清单 20‑2。
-
-代码清单 20‑2 通过系统调用控制LED（led/sys_class_leds/c_systemcall/sources/main.c文件）
-
-1 #include <stdio.h>
-
-2 #include <stdlib.h>
-
-3 #include <unistd.h>
-
-4 #include <sys/stat.h>
-
-5 #include <sys/types.h>
-
-6 #include <fcntl.h>
-
-7
-
-8 //ARM 开发板LED设备的路径
-
-9 #define RLED_DEV_PATH "/sys/class/leds/red/brightness"
-
-10 #define GLED_DEV_PATH "/sys/class/leds/green/brightness"
-
-11 #define BLED_DEV_PATH "/sys/class/leds/blue/brightness"
-
-12
-
-13 //Ubuntu主机LED设备的路径，具体请根据自己的主机LED设备修改
-
-14 // #define RLED_DEV_PATH "/sys/class/leds/input2::capslock/brightness"
-
-15 // #define GLED_DEV_PATH "/sys/class/leds/input2::numlock/brightness"
-
-16 // #define BLED_DEV_PATH "/sys/class/leds/input2::scrolllock/brightness"
-
-17
-
-18
-
-19 int main(int argc, char \*argv[])
-
-20 {
-
-21 int res = 0;
-
-22 int r_fd, g_fd, b_fd;
-
-23
-
-24 printf("This is the led demo\n");
-
-25 //获取红灯的设备文件描述符
-
-26 r_fd = open(RLED_DEV_PATH, O_WRONLY);
-
-27 if (r_fd < 0) {
-
-28 printf("Fail to Open %s device\n", RLED_DEV_PATH);
-
-29 exit(1);
-
-30 }
-
-31 //获取绿灯的设备文件描述符
-
-32 g_fd = open(GLED_DEV_PATH, O_WRONLY);
-
-33 if (g_fd < 0) {
-
-34 printf("Fail to Open %s device\n", GLED_DEV_PATH);
-
-35 exit(1);
-
-36 }
-
-37 //获取蓝灯的设备文件描述符
-
-38 b_fd = open(BLED_DEV_PATH, O_WRONLY);
-
-39 if (b_fd < 0) {
-
-40 printf("Fail to Open %s device\n", BLED_DEV_PATH);
-
-41 exit(1);
-
-42 }
-
-43
-
-44 while (1) {
-
-45 //红灯亮
-
-46 write(r_fd, "255", 3);
-
-47 //延时1s
-
-48 sleep(1);
-
-49 //红灯灭
-
-50 write(r_fd, "0", 1);
-
-51
-
-52 //绿灯亮
-
-53 write(g_fd, "255", 3);
-
-54 //延时1s
-
-55 sleep(1);
-
-56 //绿灯灭
-
-57 write(g_fd, "0", 1);
-
-58
-
-59 //蓝灯亮
-
-60 write(b_fd, "255", 3);
-
-61 //延时1s
-
-62 sleep(1);
-
-63 //蓝灯亮
-
-64 write(b_fd, "0", 1);
-
-65 }
-
-66 }
-
-本实验代码与上一小节使用C库函数操作的控制流程完全一样，只是把C库的文件操作替换成了系统调用的文件操作方式，特别之处在于这种方式不需要调用fflush之类的函数确保缓冲区的内容被写出，而且系统调用也不存在类似这样操作的函数。
-
-相对C库函数的操作方式，通过系统调用更加简单直接，而且这种与设备文件联系比较紧密的应用，C库函数兼容性好的优点也没有用武之地，所以在编写这类应用通常直接使用系统调用的方式。
+本小节通过系统调用的文件操作方式控制LED，具体如下所示。
+
+
+.. code-block:: c
+   :caption: 通过系统调用控制LED（base_code/linux_app/led/sys_class_leds/c_systemcall/sources/main.c文件）
+   :linenos:
+
+   #include <stdio.h>
+   #include <stdlib.h>
+   #include <unistd.h>
+   #include <sys/stat.h>
+   #include <sys/types.h>
+   #include <fcntl.h>
+
+   //ARM 开发板LED设备的路径
+   #define RLED_DEV_PATH "/sys/class/leds/red/brightness"
+   #define GLED_DEV_PATH "/sys/class/leds/green/brightness"
+   #define BLED_DEV_PATH "/sys/class/leds/blue/brightness"
+
+   //Ubuntu主机LED设备的路径，具体请根据自己的主机LED设备修改
+   // #define RLED_DEV_PATH "/sys/class/leds/input2::capslock/brightness"
+   // #define GLED_DEV_PATH "/sys/class/leds/input2::numlock/brightness"
+   // #define BLED_DEV_PATH "/sys/class/leds/input2::scrolllock/brightness"
+
+
+   int main(int argc, char *argv[])
+   {
+      int res = 0;
+      int r_fd, g_fd, b_fd;
+      
+      printf("This is the led demo\n");
+      //获取红灯的设备文件描述符
+      r_fd = open(RLED_DEV_PATH, O_WRONLY);
+      if(r_fd < 0){
+         printf("Fail to Open %s device\n", RLED_DEV_PATH);
+         exit(1);
+      }
+      //获取绿灯的设备文件描述符
+      g_fd = open(GLED_DEV_PATH, O_WRONLY);
+      if(g_fd < 0){
+         printf("Fail to Open %s device\n", GLED_DEV_PATH);
+         exit(1);
+      }
+      //获取蓝灯的设备文件描述符
+      b_fd = open(BLED_DEV_PATH, O_WRONLY);
+      if(b_fd < 0){
+         printf("Fail to Open %s device\n", BLED_DEV_PATH);
+         exit(1);
+      }
+
+      while(1){
+         //红灯亮
+         write(r_fd, "255", 3);
+         //延时1s
+         sleep(1);
+         //红灯灭
+         write(r_fd, "0", 1);
+
+         //绿灯亮
+         write(g_fd, "255", 3);
+         //延时1s
+         sleep(1);
+         //绿灯灭
+         write(g_fd, "0", 1);
+
+         //蓝灯亮
+         write(b_fd, "255", 3);
+         //延时1s
+         sleep(1);
+         //蓝灯亮
+         write(b_fd, "0", 1);
+      }
+   }
+
+本实验代码与上一小节使用C库函数操作的控制流程完全一样，只是把C库的文件操作
+替换成了系统调用的文件操作方式，特别之处在于这种方式不需要调用fflush之类的
+函数确保缓冲区的内容被写出，而且系统调用也不存在类似这样操作的函数。
+
+相对C库函数的操作方式，通过系统调用更加简单直接，而且这种与设备文件联系比较
+紧密的应用，C库函数兼容性好的优点也没有用武之地，所以在编写这类应用通常直接使用系统调用的方式。
 
 .. _编译及测试-1:
 
 编译及测试
-^^^^^
+^^^^^^^^^^^^^^^
 
 本实验使用的Makefile与上一小节的完全一样，不再分析。
 
@@ -587,19 +373,29 @@ make ARCH=arm
 
 对于ARM架构的程序，可使用如下步骤进行编译：
 
-#在主机的实验代码Makefile目录下编译
+.. code-block:: sh
+   :linenos:
+
+   #在主机的实验代码Makefile目录下编译
+   #编译arm平台的程序
+   make ARCH=arm
+
+编译后生成的ARM平台程序为build_arm/led_demo，使用网络文件系统共享至开发
+板，在开发板的终端上测试即可。
+
+如下图:
+
+.. image:: media/ledsub010.png
+   :align: center
+   :alt: 未找到图片10|
 
-#编译arm平台的程序
 
-make ARCH=arm
 
-编译后生成的ARM平台程序为build_arm/led_demo，使用网络文件系统共享至开发板，在开发板的终端上测试即可。
+程序执行后终端会有输出，开发板上的三盏用户LED灯也会轮流闪烁，实验现象
+与使用C库函数操作方式是一样的。
 
-|ledsub010|
 
-图 20‑9 在开发板上的执行现象
 
-程序执行后终端会有输出，开发板上的三盏用户LED灯也会轮流闪烁，实验现象与使用C库函数操作方式是一样的。
 
 .. |ledsub002| image:: media/ledsub002.png
    :width: 5.74216in
diff --git a/documentation/linux_app/makefile.rst b/documentation/linux_app/makefile.rst
new file mode 100644
index 0000000000000000000000000000000000000000..b2e5c0a794ba772186bc28f8dafdb30b3a87baf4
--- /dev/null
+++ b/documentation/linux_app/makefile.rst
@@ -0,0 +1,941 @@
+.. vim: syntax=rst
+
+使用Makefile控制编译
+----------------------------
+
+关于Makefile的详细使用可参考《跟我一起写Makefile》一书或GNU官方的make说
+明文档：\ https://www.gnu.org/software/make/manual\ ，本章仅以示例对Makefile的基础语法进行讲解。
+
+本章的示例代码目录为：base_code/linux_app/makefile_step。
+
+Makefile小实验
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+为了直观地演示Makefile的作用，我们使用一个示例进行讲解，首
+先使用编辑器创建一个名为"Makefile"的文件，输入如下代码并保存，其中使用"#"开头的
+行是注释，自己做实验时可以不输入，另外要注意在"ls -lh"、"touch
+test.txt"等命令前要使用Tab键，不能使用空格代替。
+
+该示例代码step0目录下的Makefile文件中找到。
+
+
+
+.. code-block:: c
+   :caption: Makefile小实验（base_code/linux_app/makefile_step/step0/Makefile）
+   :linenos:
+
+   #Makefile格式
+   #目标:依赖的文件或其它目标
+   #Tab 命令1
+   #Tab 命令2
+   #第一个目标，是最终目标及make的默认目标
+   #目标a，依赖于目标targetc和targetb
+   #目标要执行的shell命令 ls -lh，列出目录下的内容
+   targeta: targetc targetb
+    ls -lh
+   
+    #目标b，无依赖
+    #目标要执行的shell命令，使用touch创建test.txt文件
+    targetb:
+    touch test.txt
+   
+    #目标c，无依赖
+    #目标要执行的shell命令，pwd显示当前路径
+    targetc:
+    pwd
+   
+    #目标d，无依赖
+    #由于abc目标都不依赖于目标d，所以直接make时目标d不会被执行
+    #可以使用make targetd命令执行
+    targetd:
+    rm -f test.txt
+   
+   
+
+这个Makefile文件主要是定义了四个目标
+操作，先大致了解它们的关系：
+
+-  targeta：这是Makefile中的第一个目标代号，在符号":"后
+   面的内容表示它依赖于targetc和targetb目标，它自身的命令为"ls -lh"，列出当前目录下的内容。
+
+-  targetb：这个目标没有依赖其它内容，它要执行的命令为"touch test.txt"，即创建一个test.txt文件。
+
+-  targetc：这个目标同样也没有依赖其它内容，它要执行的命令为"pwd"，就是简单地显示当前的路径。
+
+-  targetd：这个目标无依赖其它内容，它要执行的命令为"rm -f test.txt"，删除
+   目录下的test.txt文件。与targetb、c不同的是，没有任何其它目标依赖于targetd，而且
+   它不是默认目标。
+
+下面使用这个Makefile执行各种make命令，对比不同make命令的输出，可以清楚地了解Makefile的机制。
+在主机Makefile所在的目录执行如下命令：
+
+::
+
+         #在主机上Makefile所在的目录执行如下命令
+         #查看当前目录的内容
+         ls
+
+         #执行make命令，make会在当前目录下搜索"Makefile"或"makefile"，并执行
+         make
+
+         #可看到make命令后的输出，它执行了Makefile中编写的命令
+
+         #查看执行make命令后的目录内容，多了test.txt文件
+         ls
+
+         #执行Makefile的targetd目标，并查看，少了test.txt文件
+         make targetd
+         ls
+
+         #执行Makefile的targetb目标，并查看，又生成了test.txt文件
+         make targetb
+         ls
+
+         #执行Makefile的targetc目标
+         make targetc
+
+.. image:: media/makefi002.jpg
+   :align: center
+   :alt: 未找到图片02|
+
+
+
+上图中包含的原理说明如下：
+
+make命令：
+
+-  在终端上执行make命令时，make会在当前目录下搜索名为"Makefile"或"makefile"的文件，然后
+   根据该文件的规则解析执行。如果要指定其它文件作为输入规则，可以通过"-f"参数指定输
+   入文件，如"make -f 文件名"。
+
+-  此处make命令读取我们的Makefile文件后，发现targeta是Makefile的第一个目标，它会被当成默认目标执行。
+
+-  又由于targeta依赖于targetc和targetb目标，所以在执行targeta自身的命令之前，会先去完成targetc和targetb。
+
+-  targetc的命令为pwd，显示了当前的路径。
+
+-  targetb的命令为touch test.txt ，创建了test.txt文件。
+
+-  最后执行targeta自身的命令ls -lh ，列出当前目录的内容，可看到多了一个test.txt文件。
+
+make targetd 、make targetb、make targetc命令：
+
+-  由于targetd不是默认目标，且不被其它任何目标依赖，所以直接make的时
+   候targetd并没有被执行，想要单独执行Makefile中的某个目标，可以使用"make 目标
+   名"的语法，例如上图中分别执行了"make targetd" 、"make targetb" 和"make
+   targetc"指令，在执行"make targetd"目标时，可看到它的命令rm -f test.txt被执行，test.txt文件被删除。
+
+从这个过程，可了解到make程序会根据Makefile中描述的目标与依赖关系，执行达成目标需要的shell命令。简单来说，Makefile就是用来指导make程序如何干某些事情的清单。
+
+使用Makefile编译程序
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+使用GCC编译多个文件
+^^^^^^^^^^^^^^^^^^^^^^
+
+接着我们使用Makefile来控制程序的编译，为方便说明，先把前面章节
+的hello.c程序分开成三个文件来写，分别为hello_main.c主文件，hello_func.c函数文
+件，hello_func.h头文件，其内容如下代码所示，这些文件可在示例的step1目录下找到。
+
+.. code-block:: c
+   :caption: hello_main.c文件（base_code/linux_app/makefile_step/step1目录）
+   :linenos:
+
+   #include "hello_func.h"
+   int main()
+   {
+   hello_func();
+   return 0;
+   }
+
+.. code-block:: c
+   :caption: hello_func.c文件（base_code/linux_app/makefile_step/step1目录）
+   :linenos:
+
+   #include <stdio.h>
+   #include "hello_func.h"
+   void hello_func(void)
+   {
+   printf("hello, world! This is a C program.\n");
+   for (int i=0; i<10; i++ ) {
+   printf("output i=%d\n",i);
+   }
+    }
+
+.. code-block:: c
+   :caption: hello_func.h文件（base_code/linux_app/makefile_step/step1目录）
+   :linenos:
+
+   void hello_func(void);
+
+也就是说hello_main.c的main主函数调用了hello_func.c文件的打
+印函数，而打印函数在hello_func.h文件中声明，在复杂的工程中这是常见的程序结构。
+
+如果我们直接使用GCC进行编译，需要使用如下命令：
+
+::
+
+
+         #在主机上示例代码目录执行如下命令
+         #注意最后的"-I ."包含名点"."
+         gcc -o hello_main hello_main.c hello_func.c -I .
+
+         #运行生成的hello_main程序
+         ./hello_main
+
+.. image:: media/makefi003.png
+   :align: center
+   :alt: 未找到图片03|
+
+
+
+相对于基础的hello.c编译命令，此处主要是增加了输入的文件
+数量，如"hello_main.c"、"hello_func.c"，另外新增的"-I ."是告诉编
+译器头文件路径，让它在编译时可以在"."（当前目录）寻找头文件，其实不加"-I
+."选项也是能正常编译通过的，此处只是为了后面演示Makefile的相关变量。
+
+使用Makefile编译
+^^^^^^^^^^^^
+
+可以想像到，只要把gcc的编译命令按格式写入到Makefile，就能直接
+使用make编译，而不需要每次手动直接敲gcc编译命令。
+
+操作如下使用编辑器在hello_main.c所在的目录新建一个名为"Makefile"的文件，并
+输入如下内容并保存。
+
+.. code-block:: c
+   :caption:  Makefile示例文件1
+   :linenos:
+
+   #Makefile格式
+   #目标:依赖
+   #Tab 命令1
+   #Tab 命令2
+   #默认目标
+   #hello_main依赖于hello_main.c和hello_func.c文件
+   hello_main: hello_main.c hello_func.c
+   gcc -o hello_main hello_main.c hello_func.c -I .
+   
+   
+    #clean目标，用来删除编译生成的文件
+    clean:
+    rm -f *.o hello_main
+
+该文件定义了默认目标hello_main用于编译程序，clean目标用于删除
+编译生成的文件。特别地，其中hello_main目标名与gcc编译生成的文件名"gcc -o
+hello_main"设置成一致了，也就是说，此处的目标hello_main在Makefile看来，已经是
+一个目标文件hello_main。
+
+这样的好处是make每次执行的时候，会检查hello_main文件和依赖
+文件hello_main.c、hello_func.c的修改日期，如果依赖文件的修改日期比hello_main文件的
+日期新，那么make会执行目标其下的Shell命令更新hello_main文件，否则不会执行。
+
+请运行如下命令进行实验：
+
+.. code-block:: sh
+   :linenos:
+
+   #在主机上Makefile所在的目录执行如下命令   
+   #若之前有编译生成hello_main程序，先删除
+
+   rm hello_main
+   ls
+
+   #使用make根据Makefile编译程序
+   make
+   ls
+
+   #执行生成的hello_main程序
+   ./hello_main
+
+   #再次make，会提示hello_main文件已是最新
+   make
+
+   #使用touch命令更新一下hello_func.c的时间
+   touch hello_func.c
+
+   #再次make，由于hello_func.c比hello_main新，所以会再编译
+   make
+   ls
+
+.. image:: media/makefi004.png
+   :align: center
+   :alt: 未找到图片04|
+
+
+
+如上图所示，有了Makefile后，我们实际上只需要执行一下make命令就可以完成
+整个编译流程。
+
+图中还演示了make会对目标文件和依赖进行更新检查，当依赖文件
+有改动时，才会再
+次执行命令更新目标文件。
+
+目标与依赖
+~~~~~~~~~~~~~~~
+
+下面我们再总结一下Makefile中跟目标相关的语法：
+
+[目标1]：[依赖]
+
+[命令1]
+
+[命令2]
+
+[目标2]：[依赖]
+
+[命令1]
+
+[命令2]
+
+-  目标：指make要做的事情，可以是一个简单的代号，也可以是目标文件，需要顶格
+   书写，前面不能有空格或Tab。一个Makefile可以有多个目标，写在最前面的第一
+   个目标，会被Make程序确立为 "默认目标"，例如前面的targeta、hello_main。
+
+-  依赖：要达成目标需要依赖的某些文件或其它目标。例如前面的targeta依赖
+   于targetb和targetc，又如在编译的例子中，hello_main依赖于hello_main.c、hello_func.c源文
+   件，若这些文件更新了会重新进行编译。
+
+-  命令1，命令2…命令n：make达成目标所需要的命令。只有当目标不存在或依赖
+   文件的修改时间比目标文件还要新时，才会执行命令。要特别注意命令的开头要用"Tab"键，不能
+   使用空格代替，有的编辑器会把Tab键自动转换成空格导致出错，若出现这种情况请检查自己的编辑器配置。
+
+伪目标
+~~~~~~~~~
+
+前面我们在Makefile中编写的目标，在make看来其实都是目标文件，例如make在执行
+的时候由于在目录找不到targeta文件，所以每次make
+targeta的时候，它都会去执行targeta的命令，期待执行后能得到名为targeta的
+同名文件。如果目录下真的有targeta、targetb、targetc的文件，即假如目标文件和依
+赖文件都存在且是最新的，那么make targeta就不会被正常执行了，这会引起误会。
+
+为了避免这种情况，Makefile使用".PHONY"前缀来区分目标代号和目标文件，并且这种目
+标代号被称为"伪目标"，phony单词翻译过来本身就是假的意思。
+
+也就是说，只要我们不期待生成目标文件，就应该把它定义成伪目标，前面的演示代码
+修改如下。
+
+.. code-block:: c
+   :caption: 使用.PHONY定义伪目标
+   :linenos:
+
+   #使用.PHONY表示targeta是个伪目标
+   .PHONY:targeta
+   #目标a，依赖于目标targetc和targetb
+   #目标要执行的shell命令 ls -lh，列出目录下的内容
+   targeta: targetc targetb
+   ls -lh
+   #使用.PHONY表示targetb是个伪目标
+   .PHONY:targetb
+   
+   #目标b，无依赖
+   #目标要执行的shell命令，使用touch创建test.txt文件
+   targetb:
+   touch test.txt
+   
+   #使用.PHONY表示targetc是个伪目标
+   .PHONY:targetc
+   
+   #目标c，无依赖
+   #目标要执行的shell命令，pwd显示当前路径
+   targetc:
+   pwd
+   
+   #使用.PHONY表示targetd是个伪目标
+   .PHONY:targetd
+   
+   #目标d，无依赖
+   #由于abc目标都不依赖于目标d，所以直接make时目标d不会被执行
+   #可以使用make targetd命令执行
+   targetd:
+   rm -f test.txt
+   
+   
+
+.. code-block:: c
+   :caption: 使用.PHONY定义伪目标
+   :linenos:
+
+   #默认目标
+   #hello_main依赖于hello_main.c和hello_func.c文件
+   hello_main: hello_main.c hello_func.c
+   gcc -o hello_main hello_main.c hello_func.c -I .
+   #clean伪目标，用来删除编译生成的文件
+   .PHONY:clean
+   clean:
+   rm -f *.o hello_main
+
+GNU组织发布的软件工程代码的Makefile，常常会有类似以上代码中定义的clean伪目标，用于清
+除编译的输出文件。常见
+的还有"all"、"install"、"print"、"tar"等分别用于编译所有内容、安装已
+编译好的程序、列出被修改的文件及打包成tar文件。虽然并没有固定的要求伪目标必须用这些
+名字，但可以参考这些习惯来编写自己的Makefile。
+
+如果以上代码中不写".PHONY:clean"语句，并且在目录下创建一个名为clean的文件，那么当
+执行"make clean"时，clean的命令并不会被执行，感兴趣的可以亲自尝试一下。
+
+默认规则
+~~~~~~~~~~~~
+
+在前面《GCC编译过程》章节中提到整个编译过程包含如下图中的步骤，make在执行时也是
+使用同样的流程，不过在Makefile的实际应用中，通常会把编译和最终的链接过程分开。
+
+.. image:: media/makefi005.png
+   :align: center
+   :alt: 未找到图片05|
+
+
+
+也就是说，我们的hello_main目标文件本质上并不是依赖hello_main.c和hello_func.c文件，而是依
+赖于hello_main.o和hello_func.o，把这两个文件链接起来就能得到我们最终想要的hello_main目
+标文件。另外，由于make有一条默认规则，当找不到xxx.
+o文件时，会查找目录下的同名xxx.c文件进行编译。根据这样
+的规则，我们可把Makefile改修改如下。
+
+.. code-block:: c
+   :caption: Makefile文件（base_code/linux_app/makefile_step/step2）
+   :linenos:
+
+   #Makefile格式
+   #目标文件:依赖的文件
+   #Tab 命令1
+   #Tab 命令2
+   hello_main: hello_main.o hello_func.o
+   gcc -o hello_main hello_main.o hello_func.o
+   #以下是make的默认规则，下面两行可以不写
+   #hello_main.o: hello_main.c
+   # gcc -c hello_main.c
+   
+   #以下是make的默认规则，下面两行可以不写
+   #hello_func.o: hello_func.c
+   # gcc -c hello_func.c
+
+以上代码的第5~6行把依赖文件由C文件改成了.o文件，gcc编译命令也做
+了相应的修改。第8~14行分别是hello_main.o文件和hello_func.o文件的依赖和
+编译命令，不过由于C编译成同名的.o文件是make的默认规则，所以这部分内容通常不会写上去。
+
+使用修改后的Makefile编译结果如下图所示。
+
+.. image:: media/makefi006.png
+   :align: center
+   :alt: 未找到图片06|
+
+
+
+从make的输出可看到，它先执行了两条额外的"cc"编译命令，这是由make默认规则执
+行的，它们把C代码编译生成了同名的.o文件，然后make根据Makefile的命令链接这两
+个文件得到最终目标文件hello_main。
+
+使用变量
+~~~~~~~~~~~~
+
+使用C自动编译成*.o的默认规则有个缺陷，由于没有显式地表示*.o依赖于.h头文
+件，假如我们修改了头文件的内容，那么*.o并不会更新，这是不可接受的。并且默认
+规则使用固定的"cc"进行编译，假如我们想使用ARM-GCC进行交叉编译，那么系统默
+认的"cc"会导致编译错误。
+
+要解决这些问题并且让Makefile变得更加通用，需要引入变量和分支进行处理。
+
+基本语法
+^^^^^^^^^^^^
+
+在Makefile中的变量，有点像 C语言的宏定义，在引用变量的地方使用变量
+值进行替换。变量的命名可以包含字符、数字、下划线，区分大小写，定义变量的方式有以下四种：
+
+-  "=" ：延时赋值，该变量只有在调用的时候，才会被赋值
+
+-  ":=" ：直接赋值，与延时赋值相反，使用直接赋值的话，变量的值定义时就已经确定了。
+
+-  "?=" ：若变量的值为空，则进行赋值，通常用于设置默认值。
+
+-  "+=" ：追加赋值，可以往变量后面增加新的内容。
+
+当我们想使用变量时，其语法如下：
+
+.. code-block:: sh
+   :linenos:
+
+   $(变量名)
+
+下面通过一个实验来讲解这四种定义方式，对于后两种赋值方式
+比较简单，主要思考延时赋值和直接赋值的差异，实验代码如下所示。
+
+.. code-block:: c
+   :caption: Makefile_test变量实验（base_code/linux_app/makefile_step/step3/Makefile_test）
+   :linenos:
+
+   VAR_A = FILEA
+   VAR_B = $(VAR_A)
+   VAR_C := $(VAR_A)
+   VAR_A += FILEB
+   VAR_D ?= FILED
+   .PHONY:check
+   check:
+   @echo "VAR_A:"$(VAR_A)
+   @echo "VAR_B:"$(VAR_B)
+   @echo "VAR_C:"$(VAR_C)
+   @echo "VAR_D:"$(VAR_D)
+
+这里主要关心VAR_B和VAR_C的赋值方式，实验结果如下图所示。执行完make命令
+后，只有VAR_C是FILEA。这是因为VAR_B采用的延时赋值，只有当调用时，才会进行
+赋值。当调用VAR_B时，VAR_A的值已经被修改为FILEA FILEB，因此VAR_B的变量值也就等于FILEA
+FILEB。
+
+.. image:: media/makefi007.png
+   :align: center
+   :alt: 未找到图片07|
+
+
+
+改造默认规则
+^^^^^^^^^^^^^^^^^^
+
+接下来使用变量对前面hello_main的Makefile进行大改造，如下所示。
+
+.. code-block:: c
+   :caption: 使用变量修改默认规则（base_code/linux_app/makefile_step/step3/Makefile）
+   :linenos:
+
+   #定义变量
+   CC=gcc
+   CFLAGS=-I.
+   DEPS = hello_func.h
+
+   #目标文件
+   hello_main: hello_main.o hello_func.o
+   $(CC) -o hello_main hello_main.o hello_func.o
+
+   #*.o文件的生成规则
+   %.o: %.c $(DEPS)
+   $(CC) -c -o $@ $< $(CFLAGS)
+   
+   #伪目标
+   .PHONY: clean
+   clean:
+   rm -f *.o hello_main
+
+-  代码的1~4行：分别定义了CC、CFLAGS、DEPS变量，变量的值就是等号右
+   侧的内容，定义好的变量可通过"$(变量名)"的形式引用，如后面
+   的"$(CC)"、"$( CFLAGS)"、"$(DEPS)"等价于定义时赋予的变量值"gcc"、"-I."和"hello_func.h"。
+
+-  代码的第8行：使用$(CC)替代了gcc，这样编写的Makefile非常容易更换
+   不同的编译器，如要进行交叉编译，只要把开头的编译器名字修改掉即可。
+
+-  代码的第11行："%"是一个通配符，功能类似"*"，如"%.o"表示所
+   有以".o"结尾的文件。所以"%.o:%.c"在本例子中等价
+   于"hello_main.o: hello_main.c"、"hello_func.o:
+   hello_func.c"，即等价于o文件依赖于c文件的默认规则。不过这行代码后面的"$(DEPS)"表示它除了
+   依赖c文件，还依赖于变量"$(DEPS)"表示的头文件，所以当头文件修改的话，o文件也会被重新编译。
+
+-  代码的第12行：这行代码出现了特殊的变量"$@"，"$<"，可理解为Makefile文件保
+   留的关键字，是系统保留的自动化变量，"$@"代表了目标文件，"$<"代表了第一个依赖
+   文件。即"$@"表示"%.o"，"$<"表示"%.c"，所以，当第11行的"%"匹配的字符为"hello_func"的话，第1
+   2行代码等价于：
+
+.. code-block:: sh
+   :linenos:
+
+   #当"%"匹配的字符为"hello_func"的话：
+   $(CC) -c -o $@ $< $(CFLAGS)
+   #等价于：
+   gcc -c -o hello_func.o func_func.c -I .
+
+也就是说makefile可以利用变量及自动化变量，来重写.o文件的默认生成
+规则，以及增加头文件的依赖。
+
+改造链接规则
+^^^^^^^^^^^^^^^^^^
+
+与*.o文件的默认规则类似，我们也可以使用变量来修改生成最终目标
+文件的链接规则，具体参考如下代码。
+
+.. code-block:: c
+   :caption: 使用变量修改链接规则（base_code/linux_app/makefile_step/step4/Makefile）
+   :linenos:
+
+   #定义变量
+   TARGET = hello_main
+   CC = gcc
+   CFLAGS = -I.
+   DEPS = hello_func.h
+   OBJS = hello_main.o hello_func.o
+
+   #目标文件
+   $(TARGET): $(OBJS)
+    $(CC) -o $@ $^ $(CFLAGS)
+   
+   #*.o文件的生成规则
+   %.o: %.c $(DEPS)
+   $(CC) -c -o $@ $< $(CFLAGS)
+   
+   #伪目标
+   .PHONY: clean
+   clean:
+   rm -f *.o hello_main
+
+这部分说明如下：
+
+-  代码的第2行：定义了TARGET变量，它的值为目标文件名hello_main。
+
+-  代码的第6行：定义了OBJS变量，它的值为依赖的各个o文件，如hello_main.o、hello_func.o文件。
+
+-  代码的第9行：使用TARGET和OBJS变量替换原来固定的内容。
+
+-  代码的第10行：使用自动化变量"$@"表示目标文件"$(TARGET)"，使用自动化变量"$^"表示所有的依赖文件即"$(OBJS)"。
+
+也就是说以上代码中的Makefile把编译及链接的过程都通过变量表示出来了，非常通用。
+使用这样的Makefile可以针对不同的工程直接修改变量的内容就可以使用。
+
+其它自动化变量
+^^^^^^^^^^^^^^^^^^^^^
+
+Makefile中还有其它自动化变量，此处仅列出方便以后使用到的时候进行查阅，见下表。
+
+表    自动化变量
+
+==== ==============================================
+符号 意义
+==== ==============================================
+$@   匹配目标文件
+$%   与$@类似，但$%仅匹配"库"类型的目标文件
+$<   依赖中的第一个目标文件
+$^   所有的依赖目标，如果依赖中有重复的，只保留一份
+$+   所有的依赖目标，即使依赖中有重复的也原样保留
+$?   所有比目标要新的依赖目标
+==== ==============================================
+
+使用分支
+~~~~~~~~~~~~
+
+为方便直接切换GCC编译器，我们还可以使用条件分支增加切换编译器
+的功能。在Makefile中的条件分支语法如下：
+
+.. code-block:: sh
+   :linenos:
+
+   ifeq(arg1, arg2)
+   分支1
+   else
+   分支2
+   endif
+
+分支会比较括号内的参数"arg1"和"arg2"的值是否相
+同，如果相同，则为真，执行分支1的内容，否则的话，执行分支2 的内容，参
+数arg1和arg2可以是变量或者是常量。
+
+使用分支切换GCC编译器的Makefile如下所示。
+
+.. code-block:: c
+   :caption: 给Makefile增加编译器的选择切换（base_code/linux_app/makefile_step/step4/Makefile）
+   :linenos:
+
+   #定义变量
+   #ARCH默认为x86，使用gcc编译器，
+   #否则使用arm编译器
+   ARCH ?= x86
+   TARGET = hello_main
+   CFLAGS = -I.
+   DEPS = hello_func.h
+   OBJS = hello_main.o hello_func.o
+   
+   #根据输入的ARCH变量来选择编译器
+   #ARCH=x86，使用gcc
+   #ARCH=arm，使用arm-gcc
+   ifeq ($(ARCH),x86)
+   CC = gcc
+   else
+   CC = arm-linux-gnueabihf-gcc
+   endif
+   
+   #目标文件
+   $(TARGET): $(OBJS)
+   $(CC) -o $@ $^ $(CFLAGS)
+   
+   #*.o文件的生成规则
+   %.o: %.c $(DEPS)
+   $(CC) -c -o $@ $< $(CFLAGS)
+   
+   #伪目标
+   .PHONY: clean
+   clean:
+   rm -f *.o hello_main
+
+Makefile主要是增加了ARCH变量用于选择目标平台，第4行代
+码中使用"?="给ARCH赋予默认值x86，然后在代码11~18行增加了根据ARCH
+变量值的内容对CC变量赋予不同的编译器名。
+
+在执行make命令的时候，通过给ARCH赋予不同的变量值切换不同的编译器平台：
+
+.. code-block:: sh
+   :linenos:
+
+   #清除编译输出，确保不受之前的编译输出影响
+   make clean
+   #使用ARM平台
+   make ARCH=arm
+   #清除编译输出
+   make clean
+   #默认是x86平台
+   make
+
+.. image:: media/makefi008.png
+   :align: center
+   :alt: 未找到图片08|
+
+
+
+使用函数
+~~~~
+
+在更复杂的工程中，头文件、源文件可能会放在二级目录，编译生成的*.o或
+可执行文件也放到专门的编译输出目录方便整理，如下图所示。示例中*.h头文件
+放在includes目录下，*.c文件放在sources目录下，不同平台的编译输出分别存
+放在build_x86和build_arm中。
+
+实现这些复杂的操作通常需要使用Makefile的函数。
+
+.. image:: media/makefi009.png
+   :align: center
+   :alt: 未找到图片09|
+
+
+
+函数格式及示例
+^^^^^^^^^^^^^^
+
+在Makefile中调用函数的方法跟变量的使用
+类似，以"$()"或"${}"符号包含函数名和参数，具体语法如下：
+
+.. code-block:: sh
+   :linenos:
+
+   $(函数名 参数)
+   #或者使用花括号
+   ${函数名 参数}
+
+下面以常用的notdir、patsubst、wildcard函数为例
+进行讲解，并且示例中都是我们后面Makefile中使用到的内容。
+
+notdir函数
+''''''''''''''''''''''''
+
+notdir函数用于去除文件路径中的目录部分。它的格式如下：
+
+.. code-block:: sh
+   :linenos:
+
+   $(notdir 文件名)
+
+例如输入参数"./sources/hello_func.c"，函数执行后
+的输出为"hell_func.c"，也就是说它会把输入中的"./sources/"路径部分去掉，保留
+文件名。使用范例如下：
+
+.. code-block:: sh
+   :linenos:
+
+   #以下是范例
+   $(notdir ./sources/hello_func.c)
+
+#上面的函数执行后会把路径中的"./sources/"部分去掉，输出为：
+hello_func.c
+
+wildcard函数
+''''''''''''''''''''
+
+wildcard函数用于获取文件列表，并使用空格分隔开。它的格式如下：
+
+$(wildcard 匹配规则)
+
+例如函数调用"$(wildcard *.c)"，函数执行后会把当前目录的所
+有c文件列出。假设我们在上图中的Makefile目录下执行该函数，使用范例如下：
+
+.. code-block:: sh
+   :linenos:
+
+   #在sources目录下有hello_func.c、hello_main.c、test.c文件
+   #执行如下函数
+   $(wildcard sources/*.c)
+   #函数的输出为：
+   sources/hello_func.c sources/hello_main.c sources/test.c
+
+
+
+patsubst函数
+''''''''''''''''''''''''''''''
+
+patsubst函数功能为模式字符串替换。它的格式如下：
+
+.. code-block:: sh
+   :linenos:
+
+   $(patsubst 匹配规则, 替换规则, 输入的字符串)
+
+当输入的字符串符合匹配规则，那么使用替换规则来替换字符串，当匹配规则中有"%"号时，替换规
+则也可以例程"%"号来提取"%"匹配的内容加入到最后替换的字符串中。有点抽象，请直接阅读以下示例：
+
+#执行如下函数
+
+.. code-block:: sh
+   :linenos:
+
+   $(patsubst %.c, build_dir/%.o, hello_main.c )
+   #函数的输出为：
+   build_dir/hello_main.o
+   #执行如下函数
+   $(patsubst %.c, build_dir/%.o, hello_main.xxx )
+   #由于hello_main.xxx不符合匹配规则"%.c"，所以函数没有输出
+
+第一个函数调用中，由于"hello_main.c"符合"%.c"的匹配规则（%在Makefile中的类似于*通配符），而且"%"从"hello_main.c"中提取出了"hello_main"字符，把这部分内容放到替换规则"build_dir/%.o"的"%"号中，所以最终的输出为"build_di
+r/hello_main.o"。
+
+第二个函数调用中，由于由于"hello_main.xxx"不符合"%.c"的匹配规则，".xxx"与".c"对不上，所以不会进行替换，函数直接返回空的内容。
+
+多级结构工程的Makefile
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+接下来我们使用上面三个函数修改我们的Makefile，以适应包含多级目录的工程，修改后的内容如下所示。
+
+.. code-block:: c
+   :caption: 使用函数处理多级结构的工程（base_code/linux_app/makefile_step/step5/Makefile）
+   :linenos:
+
+   #定义变量
+   #ARCH默认为x86，使用gcc编译器，
+   #否则使用arm编译器
+   ARCH ?= x86
+   TARGET = hello_main
+
+
+   #存放中间文件的路径
+   BUILD_DIR = build_$(ARCH)
+   #存放源文件的文件夹
+   SRC_DIR = sources
+   #存放头文件的文件夹
+   INC_DIR = includes .
+   
+   #源文件
+   SRCS = $(wildcard $(SRC_DIR)/*.c)
+   #目标文件（*.o）
+   OBJS = $(patsubst %.c, $(BUILD_DIR)/%.o, $(notdir $(SRCS)))
+   #头文件
+   DEPS = $(wildcard $(INC_DIR)/*.h)
+   
+   #指定头文件的路径
+   CFLAGS = $(patsubst %, -I%, $(INC_DIR))
+   
+   #根据输入的ARCH变量来选择编译器
+   #ARCH=x86，使用gcc
+   #ARCH=arm，使用arm-gcc
+   ifeq ($(ARCH),x86)
+   CC = gcc
+   else
+   CC = arm-linux-gnueabihf-gcc
+   endif
+   
+   #目标文件
+   $(BUILD_DIR)/$(TARGET): $(OBJS)
+   $(CC) -o $@ $^ $(CFLAGS)
+   
+   #*.o文件的生成规则
+   $(BUILD_DIR)/%.o: $(SRC_DIR)/%.c $(DEPS)
+   #创建一个编译目录，用于存放过程文件
+   #命令前带"@",表示不在终端上输出
+   @mkdir -p $(BUILD_DIR)
+   $(CC) -c -o $@ $< $(CFLAGS)
+   
+   #伪目标
+   .PHONY: clean cleanall
+   #按架构删除
+   clean:
+   rm -rf $(BUILD_DIR)
+   
+   #全部删除
+   cleanall:
+   rm -rf build_x86 build_arm
+
+注意这个Makefile文件需要配合前面上图中的工程结构，否则即使Makefile写对了编译也会错误，因为
+目录对不上。具体可以直接参考我们示例代码"step5"中的内容。修改后的Makefile文件分析如下：
+
+-  代码的8~12行：定义了变量BULID_DIR、SRC_DIR、INC_DIR分别赋值为工程的编译输出路径build_$(ARCH)、源文
+   件路径sources以及头文件路径includes和当前目录"."。其中编译输出路径包含了架构$(ARCH)的内容，ARCH=x86时编译输出路径为build
+   _x86，ARCH=arm时编译输出路径为build_arm，方便区分不同的编译输出。
+
+-  代码的第15行：定义了变量SRCS用于存储所有需要编译的源文件，它的值为wildcard函
+   数的输出，本例子中该函数的输出为"sources/hello_func.c sources/hello_main.c sources/test.c"。
+
+-  代码的第17行：定义了OBJS变量用于存储所有要生成的的.o文件，它的值为patsubst函数
+   的输出，本例子中该函数是把所有c文件名替换为同名的.o文件，并添加build目录，即函数的输
+   出为"build/hello_func.o build /hello_main.o build
+   /test.o"。
+
+-  代码的第19行：与SRCS变量类似，定义一个DEPS变量存储所有依赖的头文件，它的值为wildcard函
+   数的输出，本例子中该函数的输出为"includes/hello_func.h "。
+
+-  代码的第22行：定义了CFLAGS变量，用于存储包含的头文件路径，它的值为patsubst函数的
+   输出，本例子中该函数是把includes目录添加到"-I"后面，函数的输出为"-Iincludes"。
+
+-  代码的第34行：相对于之前的Makefile，我们在$(TARGET)前增加了$(BUILD_DIR)路径，使得最终的可执行程序放在build目录下。
+
+-  代码的第38行：与上面类似，给.o目标文件添加$(BUILD_DIR)路径。
+
+-  代码的第41行：在执行编译前先创建build目录，以存放后面的.o文件，命令前的"@"表示执行该命令时不在终端上输出。
+
+-  代码的第48行：rm删除命令也被修改成直接删除编译目录$(BUILD_DIR)。
+
+-  代码的51~52行：增加了删除所有架构编译目录的伪目标cleanall。
+
+使用该Makefile时，直接在Makefile的目录执行make即可：
+
+.. code-block:: sh
+   :linenos:
+
+   #使用tree命令查看目录结构
+   #若提示找不到命令，使用 sudo apt install tree安装
+   tree
+
+   #编译
+   make
+
+如下图:
+
+.. image:: media/makefi010.png
+   :align: center
+   :alt: 未找到图片10|
+
+
+
+本示例中的Makefile目前只支持使用一个源文件目录，如果有多个源文
+件目录还需要改进，关于这些，我们在以后的学习中继续积累。
+
+
+
+
+
+
+.. |makefi002| image:: media\makefi002.jpg
+   :width: 6.04497in
+   :height: 2.94441in
+.. |makefi003| image:: media\makefi003.png
+   :width: 5.76806in
+   :height: 2.16302in
+.. |makefi004| image:: media\makefi004.png
+   :width: 5.76806in
+   :height: 3.17043in
+.. |makefi005| image:: media\makefi005.png
+   :width: 5.76806in
+   :height: 1.72937in
+.. |makefi006| image:: media\makefi006.png
+   :width: 5.75in
+   :height: 0.97917in
+.. |makefi007| image:: media\makefi007.png
+   :width: 5.76806in
+   :height: 0.8572in
+.. |makefi008| image:: media\makefi008.png
+   :width: 5.76806in
+   :height: 1.37125in
+.. |makefi009| image:: media\makefi009.png
+   :width: 5.76806in
+   :height: 2.49749in
+.. |makefi010| image:: media\makefi010.png
+   :width: 5.76806in
+   :height: 5.27403in
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diff --git a/documentation/linux_app/mount_nfs.rst b/documentation/linux_app/mount_nfs.rst
index 68804b08b2477cea4b7325fd75f6d7dae0062f28..bca2b6ff92e481b926dd415d722b779e0e0a17d2 100644
--- a/documentation/linux_app/mount_nfs.rst
+++ b/documentation/linux_app/mount_nfs.rst
@@ -2,160 +2,209 @@
 
 
 挂载NFS网络文件系统
------------
+---------------------------------
 
 本章将介绍如何挂载NFS网络文件系统，为后面的主机编译生成的ARM Linux应用传输到开发板做准备。
 
-本章的示例exports文件目录为：base_code/section2/nfs_config/exports。
+用户可先根据前面《项目资料下载》章节进行资料下载，本章的示例exports文件位于项目资料的embed_linux_tutorial文件夹下，具体路径为
+"base_code/linux_app/nfs_config/exports"。
 
 网络文件系统简介
-~~~~~~~~
+~~~~~~~~~~~~~~~~~~~~~~~~
 
-网络文件系统，常被称为NFS（Network File System），它是一种非常便捷的在服务器与客户端通过网络共享文件的方式，具体见图 15‑1。
+网络文件系统，常被称为NFS（Network File System），它是一种非常便
+捷的在服务器与客户端通过网络共享文件的方式，具体见下图。
 
-|mountn002|
+.. image:: media/mountn002.png
+   :align: center
+   :alt: 未找到图片02|
 
-图 15‑1 NFS服务器与客户端连接
 
-开启了NFS服务后，客户端访问服务器共享的文件时如同访问本地存储器（磁盘/SD卡/NAND FLASH等）上的文件一样，对于上层应用来说没有任何差别，在嵌入式开发时，我们常常利用这个特性在主机上共享文件，主要应用场景如下：
+
+开启了NFS服务后，客户端访问服务器共享的文件时如同访问本
+地存储器（磁盘/SD卡/NAND FLASH等）上的文件一样，对于上层应用来说没有
+任何差别，在嵌入式开发时，我们常常利用这个特性在主机上共享文件，主要应用场景如下：
 
 -  在NFS服务器上编译应用软件，客户端（开发板）通过NFS访问并运行应用程序进行测试。
 
 -  把NFS作为根文件系统来启动
 
 使用NFS的实验环境架构
-~~~~~~~~~~~~
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+在后面章节的实验中，我们常常通过NFS给开发板共享开发主机编写的应
+用程序，在本节内容将介绍如何在开发板和开发主机之间共享目录。我们要构
+建的使用NFS文件系统的实验环境架构如下图所示。
 
-在后面章节的实验中，我们常常通过NFS给开发板共享开发主机编写的应用程序，在本节内容将介绍如何在开发板和开发主机之间共享目录。我们要构建的使用NFS文件系统的实验环境架构如图 15‑2。
+.. image:: media/mountn003.png
+   :align: center
+   :alt: 未找到图片03|
 
-|mountn003|
 
-图 15‑2 使用NFS的实验环境架构
 
-在这样的环境中，开发板与开发主机接入到同一个局域网中，然后开发主机提供NFS服务，开发板通过NFS与开发主机连接共享文件。开发主机生成的目标板应用程序放在NFS的共享文件夹内，开发板访问该文件夹执行应用程序进行测试。
+在这样的环境中，开发板与开发主机接入到同一个局域网中，然后开发主机
+提供NFS服务，开发板通过NFS与开发主机连接共享文件。开发主机生成的目标板应
+用程序放在NFS的共享文件夹内，开发板访问该文件夹执行应用程序进行测试。
 
-在另一方面，开发主机与开发板还有串口连接，使用串口终端控制开发板。
+在另一方面，开发主机与开发板通过串口连接，使用串口终端控制开发板。
 
 搭建NFS环境
-~~~~~~~
+~~~~~~~~~~~~~~~~~~~~~
 
-接下来介绍如何利用NFS搭建上述实验环境。主要包含连接网络、主机开启NFS服务以及开发板挂载文件系统三个步骤。
+接下来介绍如何利用NFS搭建上述实验环境。主要包含连接网络、主机开启NFS服务
+以及开发板挂载文件系统三个步骤。
 
 我们的目标是使开发主机与开发板的以下目录映射起来：
 
 开发主机共享目录：/home/embedfire/workdir
 
-开发板的共享目录：/home/root/workdir
+开发板的挂载目录：/mnt
 
 连接到局域网络
-^^^^^^^
+^^^^^^^^^^^^^^^^^^^^^
 
 连接到局域网
-''''''
+''''''''''''''''''
+
+在本应用场景中开发主机和开发板需要通过网络互相访问，另外由于NFS文件系统
+暴露到公网需要处理很多安全问题，为简化操作，我们把开发主机和开发板连接到
+局域网络，即都使用网线把它们连接到同一个交换机（路由器）上，如上图所示。
 
-在本应用场景中开发主机和开发板需要通过网络互相访问，另外由于NFS文件系统暴露到公网需要处理很多安全问题，为简化操作，我们把开发主机和开发板连接到局域网络，即都使用网线把它们连接到同一个交换机（路由器）上，如前面的图 15‑2所示。
+如果开发主机是安装在虚拟机上，注意要在VirtualBox把虚拟机的网络配置
+改成"桥接网卡"模式，见 下图，若修改了该配置，需要重启虚拟机才生效。
 
-如果开发主机是安装在虚拟机上，注意要在VirtualBox把虚拟机的网络配置改成“桥接网卡”模式，见 图 15‑3，若修改了该配置，需要重启虚拟机才生效。
+.. image:: media/mountn004.png
+   :align: center
+   :alt: 未找到图片04|
 
-|mountn004|
 
-图 15‑3虚拟机的网络配置为“桥接网卡”模式
 
 互ping测试
-'''''''
+'''''''''''''''''''''
 
-连接好网络后在开发主机和开发板之间进行互ping测试，以保证网络互通。
+连接好网络后在开发主机和开发板之间进行互ping测试，以保证网络互通。ping命令格式为：
 
-ping时可以直接使用主机名，各自的主机名可以在终端上查看，见图 15‑4。
+.. code-block:: sh
+   :linenos:
 
-|mountn005|
+   ping [目标主机名或目标ip地址]
 
-图 15‑4 查看主机名
+这里以ping主机名为例，见下图:
 
-在终端输入提示符的“@”与“:”之间的就是主机名。例如本示例中的开发主机名为“dev”，开发板主机名为“imx6ull14x14evk”，互ping测试成功的结果如图 15‑5，ping命令格式为：
+开发主机ping开发板
 
-ping [目标主机名或目标ip地址]
+.. image:: media/mountn005.jpg
+   :align: center
+   :alt: 未找到图片05|
 
-若测试成功，会返回ttl域和时间，使用Ctrl+c可退出命令。
+开发板ping主机
 
-|mountn006|
+.. image:: media/mountn006.jpg
+   :align: center
+   :alt: 未找到图片06|
 
-图 15‑5 互ping测试
+若测试成功，会返回ttl域和时间，使用Ctrl+c可退出命令。
 
-在图 15‑5中我们还可以了解到本示例中开发主机的IP为192.168.0.219，开发板的IP为192.168.0.215，它们处于192.168.0.*的网段，即在同一个局域网内。
+在ping命令的打印信息中，我们还可以了解到本示例中开发主机的IP为192.168.100.4，开发
+板的IP为192.168.100.3，我们也可以使用ifconfig命令来查看它们的ip地址和子网掩码，如下图:
 
-如果使用主机名无法ping通，请使用ifconfig命令查看各自的IP并直接用IP地址进行ping测试，见图 15‑6。
+.. image:: media/mountn015.jpg
+   :align: center
+   :alt: 未找到图片15|
 
-|mountn007|
 
-图 15‑6 查看开发板IP并进行ping测试
+在上图中开发板使用ifconfig命令可查看到开发板有两个网卡，分别是其两
+个网络接口的信息，其中eth1没有接网线，所以不能正常使用，而eth2可看到其IP地
+址为192.168.100.3，在开发主机的终端上可使用该IP进行ping测试。
 
-注：若在开发主机上使用ifconfig提示找不到命令，请使用如下命令进行安装：
+**注意**：若在开发主机上使用ifconfig提示找不到命令，请使用如下命令进行安装：
 
-#以下命令在主机上运行
+.. code-block:: sh
+   :linenos:
 
-sudo apt-get install net-tools
+   #以下命令在主机上运行
+   sudo apt install net-tools
 
-在图 15‑6中开发板使用ifconfig命令可查看到开发板有两个网卡，分别是其两个网络接口的信息，其中eth0没有接网线，所以不能正常使用，而eth1可看到其IP地址为192.168.0.215，在开发主机的终端上可使用该IP进行ping测试。
+根据开发主机的ip和子网掩码，我们可以判断开发主板处于192.168.100.*的网段中，
+我们只要保证开发主机网络也在同一个局域网网段中，就能让它们通信。
 
 若使用ifconfig命令查看不到IP地址，或IP地址与开发主机的IP不在同一个网段，请检查网络连接。
 
+如果使用主机名无法ping通，请直接用IP地址进行ping测试，见下图。
+
+开发主机ping开发板
+
+.. image:: media/mountn007.jpg
+   :align: center
+   :alt: 未找到图片07|
+
+开发板ping开发主机
+
+.. image:: media/mountn016.jpg
+   :align: center
+   :alt: 未找到图片07|
+
 在开发主机开启NFS服务
-^^^^^^^^^^^^
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 
 确认网络并了解局域网IP地址信息后，可配置开发主机的NFS服务，以下步骤说明均在开发主机上进行操作。
 
 安装NFS服务
-'''''''
+'''''''''''''''''''''
 
 Ubuntu系统默认没有安装NFS服务，需要使用如下命令安装NFS服务端软件：
 
-#以下命令在主机上运行
+.. code-block:: sh
+   :linenos:
 
-sudo apt-get install nfs-kernel-server
+   #以下命令在主机上运行
+   sudo apt install nfs-kernel-server
 
 查看用户id
-''''''
+''''''''''''''''''
 
 在配置NFS时需要使用到用户uid和组gid，可使用id命令查看，在开发主机上的终端输入如下命令：
 
-#以下命令在主机上运行
+.. code-block:: sh
+   :linenos:
 
-id
+   #以下命令在主机上运行
+   id
 
-具体见图 15‑7。
+具体见下图。
 
-|mountn008|
+.. image:: media/mountn008.jpg
+   :align: center
+   :alt: 未找到图片08|
 
-图 15‑7 使用id命令用户id和组id
+上图使用id命令用户id和组id
 
-从图 15‑7可知本开发主机的用户uid和组gid均为998，请使用该命令查看自己的开发主机相关id，在下面的配置文件中将会使用到。
+从上图可知本开发主机的用户uid和组gid均为998，请使用该命令查看自己的开发主机相
+关id，在下面的配置文件中将会使用到。
 
 配置NFS
-'''''
-
-安装NFS服务后，会新增一个/etc/exports文件（即/etc目录下名字为exports的文件），NFS服务根据它的配置来运行，其默认内容可通过命令cat /etc/exports查看，它默认包含了一些配置的范例，内容如图 15‑8。
-
-图 15‑8 文件/etc/exports的默认内容（/etc/exports文件）
-
-1 # /etc/exports: the access control list for filesystems which may be exported
-
-2 # to NFS clients.
-See exports(5).
+'''''''''''''''
 
-3 #
+安装NFS服务后，会新增一个/etc/exports文件（即/etc目录下名字为exports的文件），NFS服务根
+据它的配置来运行，其默认内容可通过命令cat /etc/exports查看，它默认包含了一些配置
+的范例，内容如所示。
 
-4 # Example for NFSv2 and NFSv3:
 
-5 # /srv/homes hostname1(rw,sync,no_subtree_check) hostname2(ro,sync,no_subtree_check)
 
-6 #
+.. code-block:: c
+   :caption: 文件/etc/exports的默认内容（/etc/exports文件）
+   :linenos:
 
-7 # Example for NFSv4:
-
-8 # /srv/nfs4 gss/krb5i(rw,sync,fsid=0,crossmnt,no_subtree_check)
-
-9 # /srv/nfs4/homes gss/krb5i(rw,sync,no_subtree_check)
+   # /etc/exports: the access control list for filesystems which may be exported
+   # to NFS clients.
+   See exports(5).
+   #
+   # Example for NFSv2 and NFSv3:
+   # /srv/homes hostname1(rw,sync,no_subtree_check) hostname2(ro,sync,no_subtree_check)
+   #
+   # Example for NFSv4:
+   # /srv/nfs4 gss/krb5i(rw,sync,fsid=0,crossmnt,no_subtree_check)
+   # /srv/nfs4/homes gss/krb5i(rw,sync,no_subtree_check)
 
 详细的帮助说明可以使用 命令man nfs查看，此处直接以我们配置的范例进行讲解。
 
@@ -163,61 +212,78 @@ See exports(5).
 
 使用vim打开/etc/exports文件命令如下：
 
-#以下命令在主机上运行，可用gedit替换vim
+.. code-block:: sh
+   :linenos:
 
-sudo vim /etc/exports
+   #以下命令在主机上运行，可用gedit替换vim
+   sudo vim /etc/exports
 
-在/etc/exports文件末尾添加如下语句并保存，注意如下语句写到/etc/exports文件是在同一行，此处由于排版问题分行了。
+在/etc/exports文件末尾添加如下语句并保存，**注意如下语句写到/etc/exports文件是在同一行**。
 
-#把以下内容添加至/etc/exports文件末尾，注意以下内容处于同一行
+.. code-block:: sh
+   :linenos:
 
-#以下内容的IP地址和uid，gid需要根据自己的环境进行修改
-
-/home/embedfire/workdir 192.168.0.0/24(rw,sync,all_squash,anonuid=998,anongid=998,no_subtree_check)
+   #把以下内容添加至/etc/exports文件末尾，注意以下内容处于同一行
+   #以下内容的IP地址和uid，gid需要根据自己的环境进行修改
+   /home/embedfire/workdir 192.168.0.0/24(rw,sync,all_squash,anonuid=998,anongid=998,no_subtree_check)
 
 注意具体的配置需要根据自己的实验环境进行配置，请理解如下说明根据自己的实验环境进行修改：
 
 -  /home/embedfire/workdir：要共享的开发主机目录，注意使用空格与后面的配置隔开。
 
--  192.168.0.0/24：配置谁可以访问，其中的/24是掩码，此处表示24个1，即11111111.11111111.11111111.00000000，即掩码是255.255.255.0。结合前面192.168.0.0表示此处配置IP为 192.168.0.\*
-  的主机均可以访问该目录，即局域网上的所有主机。
+-  192.168.0.0/24：配置谁可以访问，其中的/24是掩码，此处表示24个1，即11111111.11111111.11111111.00000000，
+   即掩码是255.255.255.0。结合前面192.168.0.0表示此处配置IP为 192.168.0.*的主机均可以访问该目录，即局域网上的所有主机。
 
--  若局域网是其它网段，请参考此处的配置，不能直接用星号表示，如欲配置192.168.1.\* 的局域网下所有机器都可以访问，则配置为 192.168.1.0/24。
+-  若局域网是其它网段，请参考此处的配置，不能直接用星号表示，如欲配
+   置192.168.1.* 的局域网下所有机器都可以访问，则配置为 192.168.1.0/24。
 
--  这个配置域也可以直接写可访问的主机名，如把“192.168.0.0/24”替换为开发板主机名“imx6ull14x14evk”，则仅该开发板能访问共享的目录。
+-  这个配置域也可以直接写可访问的主机名，如把"192.168.0.0/24"替换为开
+   发板主机名"imx6ull14x14evk"，则仅该开发板能访问共享的目录。
 
 -  rw: 表示客户机的权限，rw表示可读写，具体的权限还受文件系统的rwx及用户身份影响。
 
 -  sync：资料同步写入到内存与硬盘中。
 
--  anonuid=998：将客户机上的用户映射成指定的本地用户ID的用户，此处998是开发主机embedfire用户的uid，此处请根据具体的主机用户uid进行配置。
+-  anonuid=998：将客户机上的用户映射成指定的本地用户ID的用户，此处998是开
+   发主机embedfire用户的uid，此处请根据具体的主机用户uid进行配置。
 
--  anongid=998： 将客户机上的用户映射成属于指定的本地用户组ID，此处998是开发主机embedfire用户组gid，此处请根据具体的主机用户组gid进行配置。
+-  anongid=998： 将客户机上的用户映射成属于指定的本地用户
+   组ID，此处998是开发主机embedfire用户组gid，此处请根据具体的主机用户组gid进行配置。
 
 -  no_subtree_check：不检查子目录权限，默认配置。
 
-本配置中的anonuid和anongid把客户机的用户映射成本地uid/gid为998的用户，即开发主机的embedfire，那么当在开发板上使用与开发主机不同的用户访问NFS共享目录时，都会具有embedfire的权限，方便互相访问。如开发板上的root用户创建文件，在开发主机上会被认为是embe
-dfire创建的；在开发主机上仅embedfire能读写的文件，在开发板上的root或其它用户也能对该文件进行读写（被当成了embedfire）。当然这并不是一种安全的访问设置方式，不过这用在我们的开发中是非常方便的配置。
+本配置中的anonuid和anongid把客户机的用户映射成本地uid/gid为998的用户，即开发
+主机的embedfire，那么当在开发板上使用与开发主机不同的用户访问NFS共享目录时，都会
+具有embedfire的权限，方便互相访问。如开发板上的root用户创建文件，在开发主机上会被认为是embe
+dfire创建的；在开发主机上仅embedfire能读写的文件，在开发板上的root或其它用户也
+能对该文件进行读写（被当成了embedfire）。当然这并不是一种安全的访问设置方式，不过
+这用在我们的开发中是非常方便的配置。
 
 创建共享目录
-''''''
+''''''''''''''''''
 
 为了确保共享的配置有效，我们还需要创建共享的目录，在本例子中共享的目录为/home/embedfire/workdir。
 
 本例子中创建的目录命令如下，请根据自己的实验环境设置要共享的目录：
 
-#以下命令在主机上运行
 
-mkdir /home/embedfire/workdir
+
+.. code-block:: sh
+   :linenos:
+
+   #以下命令在主机上运行
+   mkdir /home/embedfire/workdir
 
 更新exports配置
-'''''''''''
+'''''''''''''''''''''''''''''''''
 
 修改完/etc/exports文件并保存后，可使用exportfs命令更新配置：
 
-#以下命令在主机上运行
+.. code-block:: sh
+   :linenos:
 
-sudo exportfs -arv
+   #以下命令在主机上运行
+   sudo exportfs -arv
 
 该命令的参数说明如下：
 
@@ -231,83 +297,130 @@ sudo exportfs -arv
 
 ..
 
-   若配置正常，该命令执行后会列出共享的目录项，本示例的执行结果见图 15‑9。
+若配置正常，该命令执行后会列出共享的目录项，本示例的执行结果见下图。
+
+.. image:: media/mountn009.jpg
+   :align: center
+   :alt: 未找到图片09|
 
-   |mountn009|
 
-图 15‑9 exportfs 更新配置
 
 查看NFS共享情况
-'''''''''
+'''''''''''''''''''''''''''
+
+使用showmount –e 可查看当前NFS服务器的加载情况，具体见下图。
+
+
+
+.. code-block:: sh
+   :linenos:
+
+   #以下命令在主机上运行
+   showmount -e
+
+.. image:: media/mountn010.jpg
+   :align: center
+   :alt: 未找到图片10|
+
 
-使用showmount –e 可查看当前NFS服务器的加载情况，具体见图 15‑10。
 
-#以下命令在主机上运行
+安装NFS客户端
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 
-showmount -e
+开发主机开启NFS服务后，我们还需要在开发板安装NFS客户端，来让开发板使用NFS服务。
 
-|mountn010|
+执行安装NFS客户端命令:
 
-图 15‑10 显示当前的NFS加载情况
+.. code-block:: sh
+   :linenos:
 
-在开发板上挂载NFS目录
-^^^^^^^^^^^^
+   sudo apt install nfs-common -y
 
-开发主机共享目录后，我们还需要在开发板端挂载该共享目录。
 
-所谓挂载，就是把Linux系统本地的某个目录与存储设备建立连接，以使系统能通过目录访问存储设备上的资源，这个存储设备可以是磁盘、光盘、SD卡以及此处使用的网络共享的目录。在Linux系统下，可使用mount命令挂载目录。
+查看NFS服务器共享目录
 
-下面以实例进行说明，以下操作均在开发板的终端上进行，默认用户为root。
+在开发板上执行"showmount -e +"NFS服务器IP""命令。**注意在不同网络环境下，NFS服务器IP可能不一样，以实际情况为准。**
 
-创建挂载点
-'''''
+.. code-block:: sh
+   :linenos:
 
-挂载时需要本地存在该目录，本例子把开发板挂载在/home/root/mountnfs目录下，首先需要创建该目录：
+   showmount -e 192.168.0.219
 
-#以下命令在开发板上运行
+如下图：
+
+.. image:: media/mountn011.jpg
+   :align: center
+   :alt: 未找到图片
 
-mkdir /home/root/mountnfs
 
 临时挂载NFS文件系统
-'''''''''''
+'''''''''''''''''''''''''''''''''
 
-接下来使用mount命令进行挂载：
+使用mount命令挂载NFS服务器的共享目录到开发板/mnt目录下：
 
-#以下命令在开发板上运行
+注意:需要把下面的192.168.0.219设置为用户实际网络环境下的NFS服务器IP
 
-#需要把下面的dev设置为前面自己的主机名
+.. code-block:: sh
+   :linenos:
 
-mount -o vers=4 dev:/home/embedfire/workdir /home/root/mountnfs
+   #以下命令在开发板上运行
+   sudo mount -t nfs 192.168.0.219:/home/embedfire/workdir /mnt
 
 以上命令使用的各个参数如下：
 
--  -o vers=4：表示使用NFS文件系统第4版本，若不注明版本可能会提示参数错误。
+-  -t nfs：指定挂载的文件系统格式为nfs。
+
+-  192.168.0.219：指定NFS服务器的IP地址。
+
+-  /home/embedfire/workdir：指定NFS服务器的共享目录。
 
--  dev：目标主机的名字，此处也可以直接使用目标主机的IP地址，如本例子的目标机器IP为192.168.0.219。
+-  /mnt：本地挂载目录，即要把NFS服务器的共享目录映射到开发板的/mnt目录下。
 
--  /home/embedfire/workdir：远端的主机共享目录。
+若挂载成功，终端不会有输出，Linux的哲学思想是"没有消息便是好消息"。
 
--  /home/root/mountnfs：本地挂载点，即要把远端共享的目录映射到本地的哪个目录。
+如下图:
+
+.. image:: media/mountn012.jpg
+   :align: center
+   :alt: 未找到图片
 
-若挂载成功，终端不会有输出，Linux下执行命令后若没有输出通常就是表示执行成功。
 
 使用这种方式挂载目录只是临时的，开发板在重启后需要重新挂载该NFS目录才能访问。
 
-使用脚本进行测试
-''''''''
+测试NFS共享目录
+''''''''''''''''''''''''
+
+挂载成功后，在NFS服务器的共享目录下，输入"sudo touch hello_world.txt"命令，
+则在共享目录下创建一个hello_world.txt文件，如下图:
 
-挂载成功后，可以在开发机上把前面编写的hello world脚本复制至共享目录，然后在开发板上的终端直接访问该脚本文件并执行。在后面我们都会采用这样的形式进行开发，即在开发主机编写代码，复制至共享目录，然后在开发板上测试。
+.. image:: media/mountn013.jpg
+   :align: center
+   :alt: 未找到图片
+
+进入开发板的/mnt目录下，可以查看到NFS服务器的共享目录中的hello_world.txt文件。
+如下图:
+
+.. image:: media/mountn014.jpg
+   :align: center
+   :alt: 未找到图片
 
 取消挂载
-''''
+''''''''''''
+
+当客户机在网络上无法找到NFS共享的目录时，如开发主机关机时，在NFS的客户机
+的终端常常会输出一些提示，或在使用ls命令查看共享目录会导致长时间等待，这时可以对目录使用umount命令取消挂载，示例如下：
+
+.. code-block:: sh
+   :linenos:
 
-当客户机在网络上无法找到NFS共享的目录时，如开发主机关机时，在NFS的客户机的终端常常会输出一些提示，或在使用ls命令查看共享目录会导致长时间等待，这时可以对目录使用umount命令取消挂载，示例如下：
+   #以下命令在开发板上运行
+   sudo umount /mnt
 
-#以下命令在开发板上运行
+使用该命令时以要取消挂载的目录作为参数即可，没有输出表示执行正常。如果
+在当前挂载的目录进行umount操作，会提示"device is busy"。建议取消挂
+载时，先切换到家目录"~"，在进行umount操作。
 
-umount /home/root/mountnfs
 
-使用该命令时以要取消挂载的目录作为参数即可，没有输出表示执行正常。如果在当前挂载的目录进行umount操作，会提示“device is busy”。建议取消挂载时，先切换到家目录”~”，在进行umount操作。
 
 .. |mountn002| image:: media/mountn002.png
    :width: 3.00117in
diff --git a/documentation/linux_app/spi_bus.rst b/documentation/linux_app/spi_bus.rst
index b055430e5773912ec4ad30cb28ab12da4d107726..8f3dedca6bd16e899c5e7ae39b84909d1695a61f 100644
--- a/documentation/linux_app/spi_bus.rst
+++ b/documentation/linux_app/spi_bus.rst
@@ -1,4 +1,784 @@
 .. vim: syntax=rst
 
-SPI通讯
------------------
+SPI通信
+------------------------------
+
+本章通过讲解在应用层中使用SPI总线与外部设备的通讯，讲解Linux系统总线类型设备驱动架构的应用,它与上一章的I2C 总线操作方法非常相似，可以对比学习。
+
+在Linux内核文档的Documentation/SPI目录下有关于SPI驱动非常详细的说明。
+
+本章节的示例代码目录为：base_code/linux_app/spi
+
+SPI通讯协议简介
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+SPI 协议是由摩托罗拉公司提出的通讯协议(Serial Peripheral Interface)，即串行外围设
+备接口，是一种高速全双工的通信总线。它被广泛地使用在 ADC、 LCD 等设备与 MCU 间，要求通讯速率较高的场合
+学习本章时，可与 I2C 章节对比阅读，体会两种通讯总线的差异。下面我们分别对 SPI 协议的物理层及协议层进行讲解。
+
+SPI物理层
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+SPI通讯设备之间的常用连接方式见下图。
+
+.. image:: media/spi001.png
+   :align: center
+   :alt: 未找到图片
+
+
+
+SPI通讯使用3条总线及片选线，3条总线分别为SCK、MOSI、MISO，片选线为 ，它们的作用介绍如下：
+
+(1) ( Slave Select)：从设备选择信号线，常称为片选信号
+线，也称为NSS、CS，以下用NSS表示。当有多个SPI从设备与SPI主机相连时，设备的其它信
+号线SCK、MOSI及MISO同时并联到相同的SPI总线上，即无论有多少个从设备，都共同只使用这3条总线；而每个从设备都有独立的这一条
+NSS信号线，本信号线独占主机的一个引脚，即有多少个从设备，就有多少条片选信号线。I2C协议中通过设备地址来寻址、选中总线上的某个设备并与其进行通讯；而SPI协议中没有设备地址，它使用NSS信号线来寻址，当主机要选择从设备时，把该从设备的NSS信号线设置为低电平，该从设备即被选中，即片选有效，接着主
+机开始与被选中的从设备进行SPI通讯。所以SPI通讯以NSS线置低电平为开始信号，以NSS线被拉高作为结束信号。
+
+(2) SCK (Serial Clock)：时钟信号线，用于通讯数据同步。它由通讯主机产生，决定了通讯的速率，不同的
+设备支持的最高时钟频率不一样，如RT1052的SPI时钟频率最大为f\ :sub:`pclk`/2，两个设备之
+间通讯时，通讯速率受限于低速设备。
+
+(3) MOSI (Master Output， Slave Input)：主设备输出/从设备输入引脚。主机的
+数据从这条信号线输出，从机由这条信号线读入主机发送的数据，即这条线上数据的方向为主机到从机。
+
+(4) MISO(Master Input,，Slave Output)：主设备输入/从设备输出引脚。主机从这条信号线读
+入数据，从机的数据由这条信号线输出到主机，即在这条线上数据的方向为从机到主机。
+
+
+协议层
+^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+与I2C的类似，SPI协议定义了通讯的起始和停止信号、数据有效性、时钟同步等环节。
+
+SPI基本通讯过程
+'''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''
+
+先看看SPI通讯的通讯时序，如下图所示。
+
+
+.. image:: media/spi003.png
+   :align: center
+   :alt: 未找到图片
+
+
+
+这是一个主机的通讯时序。NSS、SCK、MOSI信号都由主机控制产生，而MISO的信号由从机产生，主机通过该信号线读取从机的数据。MOSI与MISO的信号只在NSS为低电平的时候才有效，在SCK的每个时钟周期MOSI和MISO传输一位数据。
+
+以上通讯流程中包含的各个信号分解如下：
+
+通讯的起始和停止信号
+''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''
+
+在上图中的标号处，NSS信号线由高变低，是SPI通讯的起始信号。NSS是每个从机各自独
+占的信号线，当从机检在自己的NSS线检测到起始信号后，就知道自己被主机选中了，开始准备与主机
+通讯。在图中的标号处，NSS信号由低变高，是SPI通讯的停止信号，表示本次通讯结束，从机的选中状态被取消。
+
+数据有效性
+''''''''''''''''''''''''''''''
+
+SPI使用MOSI及MISO信号线来传输数据，使用SCK信号线进行数据同步。MOSI及MISO数据线在SCK的每个时钟周期传输一位数据，且数据输入输出是同时进行的。数据传输时，MSB
+先行或LSB先行并没有作硬性规定，但要保证两个SPI通讯设备之间使用同样的协定，一般都会采用上图中的MSB先行模式。
+
+观察图中的标号处，MOSI及MISO的数据在SCK的上升沿期间变化输出，在SCK的下降沿时被采样。即在SCK的下降沿时刻，MOSI及MISO的数据有效，高电平时表示数据"1"，为低电
+平时表示数据"0"。在其它时刻，数据无效，MOSI及MISO为下一次表示数据做准备。
+
+SPI每次数据传输可以8位或16位为单位，每次传输的单位数不受限制。
+
+CPOL/CPHA及通讯模式
+''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''
+
+上面讲述的图中的时序只是SPI中的其中一种通讯模式，SPI一共有四种通讯
+模式，它们的主要区别是总线空闲时SCK的时钟状态以及数据采样时刻。为方便说明，在此
+引入"时钟极性CPOL"和"时钟相位CPHA"的概念。
+
+时钟极性CPOL是指SPI通讯设备处于空闲状态时，SCK信号线的电平
+信号(即SPI通讯开始前、 NSS线为高电平时SCK的状态)。CPOL=0时， SCK在空闲状态时
+为低电平，CPOL=1时，则相反。
+
+时钟相位CPHA是指数据的采样的时刻，当CPHA=0时，MOSI或MISO数据线上的信号
+将会在SCK时钟线的"奇数边沿"被采样。当CPHA=1时，数据线在SCK的"偶数边沿"采样。
+
+如下图:
+
+.. image:: media/spi004.png
+   :align: center
+   :alt: 未找到图片
+
+
+
+
+
+我们来分析这个CPHA=0的时序图。首先，根据SCK在空闲状态时的电平，分为两种情况。SCK信号线在空闲状态为低电平时，CPOL=0；空闲状态为高电平时，CPOL=1。
+
+无论CPOL=0还是=1，因为我们配置的时钟相位CPHA=0，在图中可以看到，采样时刻都是在SCK的奇数边沿。注意当CPOL=0的时候，时钟的奇数边沿是上升沿，而CPOL=1的时候，时钟的奇数边沿是下降沿。所以SPI的采样时刻不是由上升/下降沿决定的。MOSI和MISO数据线的有效信号在SCK的奇数
+边沿保持不变，数据信号将在SCK奇数边沿时被采样，在非采样时刻，MOSI和MISO的有效信号才发生切换。
+
+类似地，当CPHA=1时，不受CPOL的影响，数据信号在SCK的偶数边沿被采样。
+
+如下图:
+
+.. image:: media/spiapp005.jpeg
+   :align: center
+   :alt: 未找到图片
+
+
+
+由CPOL及CPHA的不同状态，SPI分成了四种模式，见下表，主机与
+从机需要工作在相同的模式下才可以正常通讯，实际中采用较多的是"模式0"与"模式3"。
+
+表  SPI的四种模式
+
+======= ==== ==== ============= ========
+SPI模式 CPOL CPHA 空闲时SCK时钟 采样时刻
+======= ==== ==== ============= ========
+0       0    0    低电平        奇数边沿
+1       0    1    低电平        偶数边沿
+2       1    0    高电平        奇数边沿
+3       1    1    高电平        偶数边沿
+======= ==== ==== ============= ========
+
+扩展SPI协议（Single/Dual/Quad/Octal SPI）
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+以上介绍的是经典SPI协议的内容，这种也被称为标准SPI协议（Standard SPI）或单
+线SPI协议（Single SPI），其中的单线是指该SPI协议中使用单根数据线MOSI进行发送数据，单根数据线MISO进行接收数据。
+
+为了适应更高速率的通讯需求，半导体厂商扩展SPI协议，主要发展出了Dual/Quad/Octal SPI协议，加上
+标准SPI协议（Single SPI），这四种协议的主要区别是数据线的数量及通讯方式，具体见下表。
+
+表 四种SPI协议的区别
+
+===================== ================= ========
+协议                  数据线数量及功能  通讯方式
+===================== ================= ========
+Single SPI（标准SPI） 1根发送，1根接收  全双工
+Dual SPI（双线SPI）   收发共用2根数据线 半双工
+Quad SPI（四线SPI）   收发共用4根数据线 半双工
+Octal SPI（八线SPI）  收发共用8根数据线 半双工
+===================== ================= ========
+
+扩展的三种SPI协议都是半双工的通讯方式，也就是说它们的数据线是分时进行收发
+数据的。例如，标准SPI（Single SPI）与双线SPI（Dual SPI）都是两根数据线，但
+标准SPI（Single SPI）的其中一根数据线只用来发送，另一根数据线只用来接收，即全双工；而双线SPI（Dual
+SPI）的两根线都具有收发功能，但在同一时刻只能是发送或者是接收，即半
+双工，四线SPI（Quad SPI）和 八线SPI（Octal SPI）与双线SPI（Dual SPI）类似，只是数据线量的区别。
+
+SDR和DDR模式
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+扩展的SPI协议还增加了SDR模式（单倍速率Single Data Rate）和DDR模式（双倍速率Double Data
+Rate）。例如在标准SPI协议的SDR模式下，只在SCK的单边沿进行数据传输，即一个SCK时钟只传输一位数据；而在它的DDR模式下，会在SCK的上升沿和下降沿都进行数据传输，即一个SCK时钟能传输两位数据，传输速率提高一倍。
+
+使能ECSPI_3驱动
+^^^^^^^^^^^^^^^^
+
+IMX6ULL的spi接口称为"ECSPI",它在普通spi接口新加入来一些特性。
+但是我们不必过分深入，把它当作普通spi接口使用即可。
+IMX6ULL有四个ECSPI接口，本实验主要使用它的第三个。
+参考前面《fire-config工具简介》章节，使能exspi_3驱动。
+
+**注意**:打开spi3时需要关闭串口3，两者存在io复用冲突，不能同时使用。
+
+如下图:
+
+.. image:: media/spiapp012.png
+   :align: center
+   :alt: 未找到图片
+
+
+检查SPI 设备
+''''''''''''''''''''''''''''''''''''''''''''''''''''''''
+
+使能exspi_3接口驱动后，我们可以通过SPI设备文件来判断spi驱动是否加载成功。
+SPI_3对应的设备文件是spidev2.0，这是因为驱动是从0开始编号的。
+
+.. code-block:: sh
+   :linenos:
+
+   #查看命令 
+   ls /dev/spidev2.0
+
+如果ECSPI_3驱动使能了，系统输出如下图所示:
+
+.. image:: media/spiapp013.png
+   :align: center
+   :alt: 未找到图片
+
+
+不同版本的Debian镜像输出的内容可能有差别。
+
+使能LED设备
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+本实验中将使用到SPI_OLED 显示屏，它的 D/C 引脚用于控制SPI写入的是命令还是数据，因此需要一个普通IO，连接到SPI_OLED的 D/C引脚。
+为简化程序设计，我们直接使用RGB灯的"绿灯"控制引脚，使用前需要使能LED设备。系统默认使能LED设备，如果用户自己禁止了，请重新使能。
+
+参考前面《fire-config工具简介》章节，使能LED设备。
+
+如下图:
+
+.. image:: media/spiapp014.png
+   :align: center
+   :alt: 未找到图片
+
+
+检查LED设备
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+.. code-block:: sh
+   :linenos:
+
+   ls /sys/class/leds/green
+
+如果LED设备使能了，系统输出如下图所示
+
+.. image:: media/spiapp015.png
+   :align: center
+   :alt: 未找到图片
+
+其中brightness就是我们所需IO引脚的设备文件。
+
+
+
+SPI回环通讯测试实验
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+本章节的示例代码目录为：base_code/linux_app/spi/spi_test
+
+硬件说明：
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+上一小节我们添加了SPI 3 的设备驱动，当然这里要操作的是SPI 3。既然是回环测试实
+验，我们只需要将SPI 3的 MIOS与MOSI引脚使用跳线帽短接即可。SPI 3 引脚说明以及在开发板上的位置如下所示。
+
+========== ============== ====================
+SPI引脚    原理图网络标号 引脚引出位置（排针）
+========== ============== ====================
+SPI3_MOSI  UART2_CTS      CN4排针 IO1.22 脚
+SPI3_MISO  UART2_RTS      CN4排针 IO1.23 脚
+SPI3_CLOCK UART2_RXD      CN4排针 IO1.21 脚
+========== ============== ====================
+
+代码分析
+^^^^^^^^^^^^^^^^^^^^^^^^
+
+SPI代码与上一章的IIC 非常类似。首先打开SPI对应的设备文件，然后写
+入配置参数，这样就完成了SPI的初始化，后面的具体功能实现只需要调用对应的API函数即可。SPI初始化代码如下：
+
+SPI 初始化代码
+'''''''''''''''''
+
+.. code-block:: c
+   :caption: SPI 初始化代码
+   :linenos:  
+
+   static  uint32_t mode = SPI_MODE_2;    //用于保存 SPI 工作模式
+   static  uint8_t bits = 8;        // 接收、发送数据位数
+   static  uint32_t speed = 500000; // 发送速度
+   
+   /*
+   * 初始化SPI
+   */
+   void spi_init(void)
+   {
+     int ret = 0;
+     /*-------------------第一部分-------------------------*/
+     /*打开 SPI 设备*/
+     fd = open("/dev/spidev2.0", O_RDWR);
+     if (fd < 0)
+     {
+       pabort("can't open /dev/spidev2.0 ");
+     }
+   
+     /*-------------------第二部分-------------------------*/
+     /*
+   	 * spi mode 设置SPI 工作模式
+   	 */
+     ret = ioctl(fd, SPI_IOC_WR_MODE32, &mode);
+     if (ret == -1)
+       pabort("can't set spi mode");
+   
+     ret = ioctl(fd, SPI_IOC_RD_MODE32, &mode);
+     if (ret == -1)
+       pabort("can't get spi mode");
+   
+     /*-------------------第三部分-------------------------*/
+     /*
+   	 * bits per word  设置一个字节的位数
+   	 */
+     ret = ioctl(fd, SPI_IOC_WR_BITS_PER_WORD, &bits);
+     if (ret == -1)
+       pabort("can't set bits per word");
+   
+     ret = ioctl(fd, SPI_IOC_RD_BITS_PER_WORD, &bits);
+     if (ret == -1)
+       pabort("can't get bits per word");
+     
+     /*-------------------第四部分-------------------------*/
+     /*
+   	 * max speed hz  设置SPI 最高工作频率
+   	 */
+     ret = ioctl(fd, SPI_IOC_WR_MAX_SPEED_HZ, &speed);
+     if (ret == -1)
+       pabort("can't set max speed hz");
+   
+     ret = ioctl(fd, SPI_IOC_RD_MAX_SPEED_HZ, &speed);
+     if (ret == -1)
+       pabort("can't get max speed hz");
+   
+     printf("spi mode: 0x%x\n", mode);
+     printf("bits per word: %d\n", bits);
+     printf("max speed: %d Hz (%d KHz)\n", speed, speed / 1000);
+   }
+
+
+
+
+
+结合代码，简单说明如下：
+
+第一部分，打开SPI 总线的设备文件。设备文件路径"/dev/spidev2.0"，如果打开失败首先要
+查看路径是否正确以及设备文件是否存在。打开方式"O_RDWR"，我们要做SPI回环通信测试，所以要以读、写方式打开。
+
+第二部分，设置SPI 工作模式。根据之前讲解,SPI根据相位和极性的不同分为四
+种工作模式，在这里四种工作模式为SPI_MODE_x (x = 0、1、2、3)。这里是回环
+测试所以设置为任意一种工作模式都可以。需要注意的是我们可以分开设置SPI的读、写工作模式。
+
+第三部分，设置SPI通信过程中一个字节所占的
+位数。默认情况下设置为8即可。同样，这里的读、写是分开设置的。
+
+第四部分，设置SPI通信的波特率，这里设置为500K。
+
+
+经过以上四部分的初始化，SPI已经可以通信了。
+
+spi发送函数
+'''''''''''''
+
+SPI借助SPI发送结构体spi_ioc_transfer 实现发送，程序中我们只需要将要发送的数据以及必要
+的配置参数填入结构体，然后调用ioctl函数执行发送即可。发送函数如下所示：
+
+.. code-block:: c
+   :caption: SPI 发送函数
+   :linenos:  
+
+   void transfer(int fd, uint8_t const *tx, uint8_t const *rx, size_t len)
+   {
+     int ret;
+     /*------------------第一部分--------------------*/
+     struct spi_ioc_transfer tr = {
+         .tx_buf = (unsigned long)tx,
+         .rx_buf = (unsigned long)rx,
+         .len = len,
+         .delay_usecs = delay,
+         .speed_hz = speed,
+         .bits_per_word = bits,
+         .tx_nbits = 1,
+         .rx_nbits = 1
+     };
+   
+     /*------------------第二部分--------------------*/
+     ret = ioctl(fd, SPI_IOC_MESSAGE(1), &tr);
+     if (ret < 1)
+     {
+       pabort("can't send spi message");
+     }
+   }
+
+
+函数共有四个参数，fd, 打开SPI设备文件时得到的SPI设备文件描述符，tx,要发送的数据地址，rx，如果是双向传输，rx 用于指定
+接收缓冲区的地址。len, 指定本次传输的数据长度，单位为字节。函数实现非常简单，结合代码介绍如下：
+
+第一部分，定义并初始化SPI传输结构体。SPI传输结构体的完整定义如下所示：
+
+结合注释很容易理解，简单说明如下，tx_buf和rx_buf分别为发送、接收缓冲区地址，数据类型为"__u64"，兼容64位系统，64位或32位
+由系统自动处理，我们不必关心。len,一次传输的数据长度。speed_hz,指定SPI通信的比特率。delay_usecs，如果不为零则用于设置两次传输之间
+的时间延迟。bits_per_word，指定字节长度，既一个字节占用多少比特。cs_change，取消
+选中，如果设置为真，则在下次传输之前会取消选中当前的SPI设备，更新片选。tx_nbits，指定"写"数据宽度，SPI 支持
+1、2、4位宽度，不过我们使用的SPI3只支持1位数据宽度，该值应当设置为1或0（设置为0表示使用默认的宽度既宽度为1）。pad参数我们没有用到，不用设置。
+
+第二部分，调用ioctl执行发送，参数fd,是SPI设备文件描述符，参数SPI_IOC_MESSAGE(1)用于指定执
+行传输次数，我们这里只定义并初始化了一个传输结构体tr,所以传输次数为1。tr 是第一部分设置的传输结构体变量。
+
+
+main函数
+'''''''''''''''
+
+有了初始化函数和发送函数，SPI回环测试就非常简单了。我们只需要初始化SPI然后调用发送函数，最后打印传输结果如下所示：
+
+
+.. code-block:: c
+   :caption: main函数
+   :linenos:  
+
+   /*-------------------第一部分---------------------*/
+   /*SPI 接收 、发送 缓冲区*/
+   unsigned char tx_buffer[100] = "hello the world !";
+   unsigned char rx_buffer[100];
+   
+   /*-------------------第二部分---------------------*/
+   int main(int argc, char *argv[])
+   {
+   	/*初始化SPI */
+   	spi_init();
+   
+   	/*执行发送*/
+   	transfer(fd, tx_buffer, rx_buffer, sizeof(tx_buffer));
+   
+   	/*打印 tx_buffer 和 rx_buffer*/
+   	printf("tx_buffer: \n %s\n ", tx_buffer);
+   	printf("rx_buffer: \n %s\n ", rx_buffer);
+   
+   	close(fd);
+   
+   	return 0;
+   }
+
+
+
+
+
+第一部分，tx_buffer是发送缓冲区，rx_buffer是接收缓冲区。第二部分，在main函数中依次调用函数spi_init初始化SPI、调用函数transfer执
+行发送。最后分别打印tx_buffer和rx_buffer的内容，正常情况下，程序运行后我们可以在控制终端发现tx_buffer和r
+x_buffer的内容一致。
+
+下载验证
+~~~~~~~~~~
+
+对于ARM架构的程序，可使用如下步骤进行编译：
+
+.. code-block:: sh
+   :linenos:
+
+   #在主机的实验代码Makefile目录下编译
+   #编译arm平台的程序
+   make ARCH=arm
+
+编译后生成的ARM平台程序为build_arm/spi_test_demo，使用网络文件系统共享至开
+发板，在开发板的终端上测试即可。
+
+如下图:
+
+.. image:: media/spiapp016.png
+   :align: center
+   :alt: 未找到图片
+
+
+
+SPI_OLED 显示实验
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+上一小节我们实现了SPI 回环通信，这一小节实现SPI驱动SPI_OLED显示屏。本小节与上一章的IIC驱动IIC_OLED非常相似，仅仅是发送函数不同。
+
+本章节的示例代码目录为：base_code/linux_app/spi/spi_oled
+
+.. _硬件说明-1:
+
+硬件说明：
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+本实验我们仍然使用SPI 3，OLED使用的是SPI接口0.96寸单色显示屏，详细资料可以在野火电子官网找到。实物如下所示：
+
+
+.. image:: media/spiapp011.png
+   :align: center
+   :alt: 未找到图片
+
+
+SPI_OLED显示屏与开发板连接关系如下表所示
+
+============== ========== ============== ====================
+SPI_OLED显示屏 SPI引脚    原理图网络标号 引脚引出位置（排针）
+============== ========== ============== ====================
+MOSI           SPI3_MOSI  UART2_CTS      CN4排针 IO1.22 脚
+未使用         SPI3_MISO  UART2_RTS      CN4排针 IO1.23 脚
+CLK            SPI3_CLOCK UART2_RXD      CN4排针 IO1.21 脚
+D/C            非SPI3引脚 CSI_HSYNC      CN5排针 IO4.20脚
+CS             非SPI3引脚                GND
+GND            非SPI3引脚                GND
+VCC            非SPI3引脚                3.3V
+============== ========== ============== ====================
+
+
+代码分析
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+SPI_OLED显示实验由SPI回环测试程序修改得到。其中OLED显示相关代码参照IIC驱动OLED显示屏程序。完整
+的代码请参考本小节配套源码（位于 base_code/linux_app/spi/spi_oled 目录下）。
+
+
+spi初始化函数
+'''''''''''''''''
+
+这里的SPI初始化函数与上一小节有两点不同。第一，这里增加了一个GPIO设备，用于控制SPI_OLED的 D/C引脚，第
+二，这里要设置SPI工作模式为模式二，并且可以不设置读（SPI_OLED是只写的一个设备）。完整初始化代码如下所示。
+
+.. code-block:: c
+   :caption: spi初始化函数
+   :linenos:  
+
+   /*---------------第一部分------------------*/
+   static uint32_t mode = SPI_MODE_2;           //用于保存 SPI 工作模式
+   
+   void spi_and_gpio_init(void)
+   {
+     int ret = 0;
+   
+     /*打开 SPI 设备*/
+     fd = open("/dev/spidev2.0", O_RDWR);
+     if (fd < 0)
+     {
+       pabort("can't open /dev/spidev2.0 ");
+     }
+    
+    /*---------------第二部分------------------*/
+     /*打开 LED 设备*/
+     data_or_command = open(data_or_command_DEV_path, O_RDWR);
+     if (fd < 0)
+     {
+       pabort("can't open /sys/class/leds/green/brightness");
+     }
+   
+     /*---------------第三部分------------------*/
+     /*
+   	 * spi mode 设置SPI 工作模式
+   	 */
+     ret = ioctl(fd, SPI_IOC_WR_MODE32, &mode);
+     if (ret == -1)
+       pabort("can't set spi mode");
+   
+     ret = ioctl(fd, SPI_IOC_RD_MODE32, &mode);
+     if (ret == -1)
+       pabort("can't get spi mode");
+   
+     /*
+   	 * bits per word  设置一个字节的位数
+   	 */
+     ret = ioctl(fd, SPI_IOC_WR_BITS_PER_WORD, &bits);
+     if (ret == -1)
+       pabort("can't set bits per word");
+   
+     ret = ioctl(fd, SPI_IOC_RD_BITS_PER_WORD, &bits);
+     if (ret == -1)
+       pabort("can't get bits per word");
+   
+     /*
+   	 * max speed hz  设置SPI 最高工作频率
+   	 */
+     ret = ioctl(fd, SPI_IOC_WR_MAX_SPEED_HZ, &speed);
+     if (ret == -1)
+       pabort("can't set max speed hz");
+   
+     ret = ioctl(fd, SPI_IOC_RD_MAX_SPEED_HZ, &speed);
+     if (ret == -1)
+       pabort("can't get max speed hz");
+   
+     printf("spi mode: 0x%x\n", mode);
+     printf("bits per word: %d\n", bits);
+     printf("max speed: %d Hz (%d KHz)\n", speed, speed / 1000);
+   }
+
+
+
+
+对比上一小节我们只关心两部分内容。第一部分，将工作模式mode设置为SPI_MODE_2，在第三部分将会用该变量初始化SPI的读（读设置可省略）、写。第二部分，打开一个LED设备，LED设备实际是一个GPIO，我们程序中将会使用这个引脚控制SPI_OLED的D/C引脚。
+
+
+SPI_OLED命令发送和数据发送函数
+''''''''''''''''''''''''''''''
+
+根据之前讲解，SPI_OLED的D/C引脚用于表示显示屏接收到的是命令还是数据，D/C为低电平，发送的是命令，D/C为高电平发送的是数据。命令发送函数和数据发送函数仅仅是在执行发送之前设置D/C对应引脚的高、低电平。如下所示。
+
+
+.. code-block:: c
+   :caption: 命令发送和数据发送函数
+   :linenos:  
+
+   /*
+   * 向 SPI_OLED 发送控制命令
+   * cmd， 要发送的命令。 
+   */
+   void spi_oled_send_commend(unsigned char cmd)
+   {
+     uint8_t tx = cmd;
+     uint8_t rx;
+   
+     write(data_or_command, "255", 3); //设置 SPI_OLED 的 D/C 为低电平
+     transfer(fd, &tx, &rx, 1);        //发送控制命令
+   }
+   
+   /*
+   * 向 SPI_OLED 发送数据
+   * cmd， 要发送的数据。 
+   */
+   void spi_oled_send_data(unsigned char dat)
+   {
+     uint8_t tx = dat;
+     uint8_t rx;
+   
+     write(data_or_command, "0", 1); //设置 SPI_OLED 的 D/C 为高电平
+     transfer(fd, &tx, &rx, 1);      //发送数据
+   }
+
+
+SPI_OLED初始化代码
+'''''''''''''''''''''
+
+
+SPI_OLED初始化分为两部分，首先初始化SPI，然后通过SPI向OLED发送配置参数。部分初始化代码如下所示：
+
+
+
+.. code-block:: c
+   :caption: SPI_OLED初始化代码
+   :linenos:  
+
+   void oled_init(void)
+   {
+     /*---------------第一部分------------------*/
+     /*初始化SPI和D/C控制引脚*/
+     spi_and_gpio_init();
+   
+     /*---------------第二部分------------------*/
+     spi_oled_send_commend(0xae);
+     spi_oled_send_commend(0xae); //--turn off oled panel
+     spi_oled_send_commend(0x00); //---set low column address
+     /*---------------一下代码省略----------------*/
+     spi_oled_send_commend(0x8d); //--set Charge Pump enable/disable
+     spi_oled_send_commend(0x14); //--set(0x10) disable
+     spi_oled_send_commend(0xa4); // Disable Entire Display On (0xa4/0xa5)
+     spi_oled_send_commend(0xa6); // Disable Inverse Display On (0xa6/a7)
+     spi_oled_send_commend(0xaf); //--turn on oled panel
+     
+     /*---------------第三部分------------------*/
+     OLED_Fill(0x00);  //清屏
+     OLED_SetPos(0, 0); //设置光标到 （0,0）地址处。
+   }
+
+
+结合代码，简单说明如下：
+
+第一部分，调用spi_and_gpio_init初始化函数，根据之前讲解，该函数初始化了SPI和一个GPIO。初始化完成后我们就可以使用SPI与OLED通信同时也可以通过GPIO控制发送的是命令还是数据。
+
+第二部分，发送OLED初始化参数。第三部分，依次调用清屏函数（使屏幕不显示）和OLED光标设置函
+数（将光标设置到起始位置）。
+
+程序中OLED清屏函数、显示字符函数、显示汉字函数以及显示图片函数与IIC驱动IIC_OLED非常相似，只是函数的简单替换，这里不再赘述。
+
+main 函数实现
+''''''''''''''''''''
+
+
+main函数中调用OLED基本的显示函数测试OLED，完整代码如下所示：
+
+
+.. code-block:: c
+   :caption: main 函数实现
+   :linenos:  
+
+   int main(int argc, char *argv[])
+   {
+   	int i = 0; //用于循环
+   
+   	/*---------------第一部分------------------*/
+   	oled_init();
+   	OLED_Fill(0xFF);
+   	sleep(1);
+   
+   	while (1)
+   	{
+           /*---------------第二部分------------------*/
+   		OLED_Fill(0x00); //清屏
+   		sleep(1);
+   
+   		/*---------------第三部分------------------*/
+   		OLED_ShowStr(0, 3, (unsigned char *)"Wildfire Tech", 1);  //测试6*8字符
+   		OLED_ShowStr(0, 4, (unsigned char *)"Hello wildfire", 2); //测试8*16字符
+   		sleep(1);
+   		OLED_Fill(0x00); //清屏
+   
+   		/*---------------第四部分------------------*/
+   		for (i = 0; i < 4; i++)
+   		{
+   			OLED_ShowCN(22 + i * 16, 0, i); //测试显示中文
+   		}
+   		sleep(1);
+   		OLED_Fill(0x00); //清屏
+   
+   		/*---------------第五部分------------------*/
+   		OLED_DrawBMP(0, 0, 128, 8, (unsigned char *)BMP1); //测试BMP位图显示
+   		sleep(1);
+   		OLED_Fill(0x00); //清屏
+   	}
+   
+   	close(fd);
+   	return 0;
+   }
+
+结合代码各部分简单说明如下：
+
+第一部分，初始化oled并全屏显示，我们使用的oled分辨率是128*64（64行，128列）。每个像素点只有亮、灭两种状态（0或1）。
+
+第二部分，清屏。清屏与全屏填充只是函数参数不同，清屏将每个像素点都设置为0，屏幕不亮，全屏填充将所有像素点设置为1，屏幕全亮。
+
+第三部分，设置显示字符串。字符串显示函数在IIC驱动OLED章节已经详细介绍，这里再次简单说明，函数前两个参数分别用于设置字符串起始位置的x、y 坐标，根据选择的字体不同（第四个参数）x,y
+的取值范围也不同，以6*8字体为例，x可取0到（128-1-6），减1是因为从零开始计数，减6是因为一个字符宽度为6个像素点，一行剩余的像素点小于6则显示不全，y可取0到7，oled显示屏有64行，每8行像素点被分成一组，所以共有8组，字符的其实位置的y坐标只能取0到7。
+
+第四部分，显示中文。使用中文要有对应的点阵字库，字库制作工具以及制作方法请参考SPI_OLED模块资料，这里不再介绍。
+
+第五部分，显示图片。与显示中文相似，使用显示图片函数之前要将图片转化为点阵数据，制作工具以及制作方法请参考SPI_OLED模块资料。
+
+
+
+
+下载验证
+~~~~~~~~~~
+
+对于ARM架构的程序，可使用如下步骤进行编译：
+
+.. code-block:: sh
+   :linenos:
+
+   #在主机的实验代码Makefile目录下编译
+   #编译arm平台的程序
+   make ARCH=arm
+
+编译后生成的ARM平台程序为build_arm/spi_oled_demo，使用网络文件系统共享至开
+发板，在开发板的终端上测试即可。
+
+
+
+
+.. |spiapp002| image:: media\spiapp002.png
+   :width: 4.81944in
+   :height: 3.48611in
+.. |spiapp003| image:: media\spiapp003.jpeg
+   :width: 5.75694in
+   :height: 2.20833in
+.. |spiapp004| image:: media\spiapp004.jpeg
+   :width: 5.63889in
+   :height: 2.99306in
+.. |spiapp005| image:: media\spiapp005.jpeg
+   :width: 5.57639in
+   :height: 2.92361in
+.. |spiapp006| image:: media\spiapp006.png
+   :width: 5.76806in
+   :height: 2.53819in
+.. |spiapp007| image:: media\spiapp007.png
+   :width: 5.76806in
+   :height: 2.53472in
+.. |spiapp008| image:: media\spiapp008.png
+   :width: 5.76806in
+   :height: 3.03958in
+.. |spiapp009| image:: media\spiapp009.png
+   :width: 5.64513in
+   :height: 2.87464in
+.. |spiapp010| image:: media\spiapp010.png
+   :width: 5.76806in
+   :height: 2.38403in
+.. |spiapp011| image:: media\spiapp011.png
+   :width: 3.60372in
+   :height: 3.33292in
+
+
diff --git a/documentation/linux_app/uart_tty.rst b/documentation/linux_app/uart_tty.rst
index 5e2cf62c0a6a9693580426df67a84297ef176a49..48b7107cd86651ba66981e5dbb9a606111bf2d98 100644
--- a/documentation/linux_app/uart_tty.rst
+++ b/documentation/linux_app/uart_tty.rst
@@ -1,505 +1,536 @@
 .. vim: syntax=rst
 
 串口通讯与终端设备
----------
+---------------------------
 
-本章主要讲解串口和终端设备的基本使用，并且通过这个过程解构如何使用ioctl系统调用向设备文件写入特别的命令，控制硬件。我们需要熟悉ioctl的使用，是因为在后面编写驱动时，某些硬件需要向内核提供ioctl所需的操作方法。
+本章主要讲解串口和终端设备的基本使用，并且通过这个过程解构如何使用ioctl系统调用
+向设备文件写入特别的命令，控制硬件。我们需要熟悉ioctl的使用，是因为在后面编写驱
+动时，某些硬件需要向内核提供ioctl所需的操作方法。
 
-本章节的示例代码目录为：base_code/section2/tty
+本章节的示例代码目录为：base_code/linux_app/tty
 
 串口通讯简介
-~~~~~~
+~~~~~~~~~~~~~~~~~~~~~~~~
 
-串口通讯(Serial Communication)是一种设备间非常常用的串行通讯方式，因为它简单便捷，大部分电子设备都支持，电子工程师在调试设备时也经常使用串口来输出调试信息，在计算机的上古时代，键盘、鼠标、MODEM以及终端都是使用串口通讯的。本书配套的开发板默认也是使用串口终端，不过为了方便使
+串口通讯(Serial Communication)是一种设备间非常常用的串行
+通讯方式，因为它简单便捷，大部分电子设备都支持，电子工程师在调试设备
+时也经常使用串口来输出调试信息，在计算机的上古时代，键盘、鼠标、MODEM以及终
+端都是使用串口通讯的。本书配套的开发板默认也是使用串口终端，不过为了方便使
 用，开发板上添加了USB转串口芯片，使得我们可以直接用USB线连接主机和开发板的串口。
 
-串口在旧式的台式计算机中一般会以RS-232标准的COM口出现(也称DB9接口)，见图 23‑1。
+串口在旧式的台式计算机中一般会以RS-232标准的COM口出现(也称DB9接口)，见下图。
 
-|uarttt002|
+.. image:: media/uarttt002.jpg
+   :align: center
+   :alt: 未找到图片02|
 
-图 23‑1 电脑主板上的COM口及串口线
 
-对于没有COM口的电脑，可以使用类似图 23‑2的USB转串口线，把USB端接入电脑并安装对应的驱动程序即可。
 
-|uarttt003|
+对于没有COM口的电脑，可以使用类似下图的USB转串口线，把USB端接
+入电脑并安装对应的驱动程序即可。
 
-图 23‑2 USB转串口线
+.. image:: media/uarttt003.png
+   :align: center
+   :alt: 未找到图片03|
 
-Windows上有很多串口通讯工具，如野火串口调试助手，终端工具putty、xShell等，如图 23‑3。
 
-|uarttt004|
 
-图 23‑3 串口调试工具
+Windows上有很多串口通讯工具，如野火串口调试助手，终端
+工具putty、xShell等，如下图所示。
+
+.. image:: media/uarttt004.jpg
+   :align: center
+   :alt: 未找到图片04|
+
+
 
 使用这些工具时，我们通常需要配置端口号、波特率、校验位、数据位以及停止位的参数。
 
--  端口号：在Windows上通常以COM1、COM2等方式命名，用于区分同一台电脑上的不同串口设备。
+-  端口号：在Windows上通常以COM1、COM2等方式命名，用于区
+   分同一台电脑上的不同串口设备。
 
--  波特率：串口最常用的是异步通讯，它没有时钟信号同步数据，所以通讯双方需要约定好数据的传输速率，波特率就是指每秒传输的比特位数（bits per second）。常见的波特率为4800、9600、115200等，表示通讯双方传输时每秒传输4800、9600以及115200个二进制数据位。
+-  波特率：串口最常用的是异步通讯，它没有时钟信号同步数据，所以通讯双
+   方需要约定好数据的传输速率，波特率就是指每秒传输的比特位数（bits per second）。常
+   见的波特率为4800、9600、115200等，表示通讯双方传输时每秒传输4800、9600以及115200个二
+   进制数据位。
 
--  通讯的起始和停止信号：串口通讯的一个数据包从起始信号开始，直到停止信号结束。数据包的起始信号由一个逻辑0的数据位表示，而数据包的停止信号可以用0.5、1、1.5或2个逻辑1的数据位表示。
+-  通讯的起始和停止信号：串口通讯的一个数据包从起始信号开始，直到停止信号结束。数
+   据包的起始信号由一个逻辑0的数据位表示，而数据包的停止信号可以用0.5、1、1.5或2个逻辑1的数
+   据位表示。
 
--  有效数据：在数据包的起始位之后紧接着的就是要传输的主体数据内容，也称为有效数据，有效数据的长度常被约定为5、6、7或8位长。
+-  有效数据：在数据包的起始位之后紧接着的就是要传输的主体数据内容，也称
+   为有效数据，有效数据的长度常被约定为5、6、7或8位长。
 
--  数据校验：由于通信容易受到外部干扰导致传输出现偏差，在有效数据之后，有一个可选的数据校验位。校验方法有奇校验(odd)、偶校验(even)、0校验(space)、1校验(mark)以及无校验(noparity)。
+-  数据校验：由于通信容易受到外部干扰导致传输出现偏差，在有效数据之后，有一个
+   可选的数据校验位。校验方法有奇校验(odd)、偶校验(even)、0校验(space)、1校验(mark)以及无
+   校验(noparity)。
 
-在本章的学习中，对于上述概念的细节不了解也没有关系，只要知道串口通讯需要配置这些参数，而且通讯双方的这些配置都一致即可。本章节聚焦于如何使用串口通讯、使用终端设备文件，若想了解串口通讯协议的详细内容请参考裸机章节。
+在本章的学习中，对于上述概念的细节不了解也没有关系，只要知道串口通讯需要配置
+这些参数，而且通讯双方的这些配置都一致即可。本章节聚焦于如何使用串口通讯、使用终端设备
+文件，若想了解串口通讯协议的详细内容请参考裸机章节。
 
 终端设备
-~~~~
+~~~~~~~~~~~~
 
-最初的计算机价格比较昂贵，往往带有一块控制计算机的面板，可用于对计算机进行一些简单操作，这种被称为控制台（console）。每个用户通过终端（terminal）连接到主机，终端和主机之间采用通信电缆相连接，甚至可以通过电信网络连接到另一个城市的电脑。控制台与终端都是用于用户与系统进行交互的设备，区别
-在于主机对于控制台的信任度高于终端。随着物理元器件的变化，计算机主机经历了更新换代 ，“控制台终端”、“终端”这些名词都是表示的一个意思，基本没有什么区别了。
+最初的计算机价格比较昂贵，往往带有一块控制计算机的面板，可用于对计算机进行一些
+简单操作，这种被称为控制台（console）。每个用户通过终端（terminal）连接到主
+机，终端和主机之间采用通信电缆相连接，甚至可以通过电信网络连接到另一个城市的
+电脑。控制台与终端都是用于用户与系统进行交互的设备，区别
+在于主机对于控制台的信任度高于终端。随着物理元器件的变化，计算机主机经历了
+更新换代 ，"控制台终端"、"终端"这些名词都是表示的一个意思，基本没有什么区别了。
 
-Teletype是最早出现的一种终端设备，类似于电传打字机，tty是 Teletype的缩写。最初tty是指连接到Unix系统上的物理或者虚拟终端。但是随着时间的推移，tty也用于串口设备，如ttyn、ttySACn等，Linux系统对终端设备的支持非常强大。
+Teletype是最早出现的一种终端设备，类似于电传打字机，tty是 Teletype的缩写。最初tty是指
+连接到Unix系统上的物理或者虚拟终端。但是随着时间的推移，tty也用于串口设备，如ttyn、ttySACn等，Linux系统
+对终端设备的支持非常强大。
 
 本章通过Linux的终端设备文件进行串口通讯。
 
-|uarttt005|
+.. image:: media/uarttt005.jpg
+   :align: center
+   :alt: 未找到图片05|
+
 
-图 23‑4 终端与开发板
 
 终端设备文件
-^^^^^^
+^^^^^^^^^^^^^^^^^^
 
 在Linux下终端的设备文件都位于/dev/目录下，以tty*开头的字符命名，可使用如下命令查看：
 
-#查看/dev目录下的“tty”名字开头的设备，“*”表示匹配任意字符
 
-ls /dev/tty\*
+.. code-block:: sh
+   :linenos:
+
+   #查看/dev目录下的"tty"名字开头的设备，"*"表示匹配任意字符
+   ls /dev/tty*
 
-|uarttt006|
+.. image:: media/uarttt006.png
+   :align: center
+   :alt: 未找到图片06|
 
-图 23‑5 /dev目录下的tty设备
 
 虽然/dev目录下有很多这样的设备，但它们并不是都可用的，为便于讲解，我们使用开发板上的tty设备进行说明。
 
-在开发板的终端上执行同样的“ls /dev/tty*”命令，如图 23‑6。
+在开发板的终端上执行同样的"ls /dev/tty*"命令，如下图所示。
 
-|uarttt007|
+.. image:: media/uarttt007.png
+   :align: center
+   :alt: 未找到图片07|
 
-图 23‑6 开发板上的终端设备
 
-可以看到有两个分别名为“ttymxc0”和“ttymxc2”的设备，其中“ttymxc0”是开发板的串口1，它已被默认被用在命令行的终端上，“ttymxc2”是开发板的串口3。
+
+可以看到有个名为"ttymxc0"的设备，"ttymxc0"就是开发板的串口1，它已被默认被用在命令行的终端上。
 
 stty命令
-^^^^^^
+^^^^^^^^^^^^^^^^^^^^^^^^
 
 Linux下有一个专门的stty命令可以查看或设置终端的参数。
 
 在开发板的终端执行如下命令：
 
-#在开发板的终端执行如下命令
+.. code-block:: sh
+   :linenos:
 
-#它会输出当前终端的参数
+   #在开发板的终端执行如下命令
+   #它会输出当前终端的参数
+   stty
+   #查看ttymxc0设备参数
+   stty -F /dev/ttymxc0
 
-stty
+.. image:: media/uarttt008.png
+   :align: center
+   :alt: 未找到图片08|
 
-#查看ttymxc0设备参数
 
-stty -F /dev/ttymxc0
 
-#查看ttymxc2设备参数
+从上图中命令的执行结果可看到，ttymxc0的通讯速率"speed"为115200，
+这就是串口通讯的波特率，这些是在驱动中设置的默认值。若用户想修改tty设备的配置，可以使用如下命令：
 
-stty -F /dev/ttymxc2
+.. code-block:: sh
+   :linenos:
 
-|uarttt008|
+   #在开发板的终端执行如下命令
+   #查看设备参数
+   stty -F /dev/ttymxc0
+   #设置通讯速率，其中ispeed为输入速率，ospeed为输出速率
+   stty -F /dev/ttymxc0 ispeed 9600 ospeed 9600
 
-图 23‑7 输出当前终端的参数
+**注意:如果修改了串口1的波特率，相应的串口调试助手也要修改为对应波特率，否则开发板的串口终端将不能再使用**
 
-从图 23‑7中命令的执行结果可看到，ttymxc0的通讯速率“speed”为115200，ttymxc2的通讯速率为9600，这就是串口通讯的波特率，这些是在驱动中设置的默认值。若用户想修改tty设备的配置，可以使用如下命令：
+命令中的ispeed和ospeed分别表示要设置的输入速率和输出速率，并不是所有设备
+都支持不同的输入输出速率，所以最好把它们设置成一样。
 
-#在开发板的终端执行如下命令
+串口通讯实验（Shell）
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
-#查看设备参数
+本实验使用开发板上的串口3进行实验，对应的设备文件为/dev/ttymxc2，这是因为驱动是从0开始编号的。
+对tty的设备文件直接读写就可以控制设备通过串口接收或发送数据，下面我们使用开发板配合Windows下的串口调试助手或Linux下的minicom进行测试。
 
-stty -F /dev/ttymxc2
+使能串口3
+^^^^^^^^^^^
 
-#设置通讯速率，其中ispeed为输入速率，ospeed为输出速率
+开发板串口3默认没有使能，参考前面《fire-config工具简介》章节，使能开发板的串口3外设。
 
-stty -F /dev/ttymxc2 ispeed 115200 ospeed 115200
+如下图:
 
-#查看设备参数
+.. image:: media/uarttt029.png
+   :align: center
+   :alt: 未找到图片
 
-stty -F /dev/ttymxc2
+查询串口3的通信参数
+^^^^^^^^^^^^^^^^^^^
 
-|uarttt009|
+串口3外设使能后，在/dev目录下生成ttymxc2设备文件，用stty工具查询其通信参数
 
-图 23‑8 使用stty修改终端参数
+.. code-block:: sh
+   :linenos:
 
-命令中的ispeed和ospeed分别表示要设置的输入速率和输出速率，并不是所有设备都支持不同的输入输出速率，所以最好把它们设置成一样。可以看到命令执行后ttymxc2设备的速率变为了115200。
+   #在开发板的终端执行如下命令
+   stty -F /dev/ttymxc2
 
-串口通讯实验（Shell）
-~~~~~~~~~~~~~
+如下图:
 
-对tty的设备文件直接读写就可以控制设备通过串口接收或发送数据，下面我们使用开发板配合Windows下的串口调试助手或Linux下的minicom进行测试
+.. image:: media/uarttt030.png
+   :align: center
+   :alt: 未找到图片
 
 连接串口线及跳线帽
-^^^^^^^^^
+^^^^^^^^^^^^^^^^^^^^^^^^^^^
 
-本实验使用/dev/ttymxc2设备文件进行实验，也就是开发板上的串口3，实验前需要使用串口线或USB转串口线把它与开发板与电脑连接起来，并且使用跳线帽连接排针“UART3_TXD<---->T2IN”、“UART3_RXD<---->R2OUT”，如图 23‑9。
+实验前需要使用串口线或USB转串口线把它与开发板与电脑连接起来，并且使用跳线帽连接
+排针"UART3_TXD<---->T2IN"、"UART3_RXD<---->R2OUT"，如下图所示。
+
+.. image:: media/uarttt010.png
+   :align: center
+   :alt: 未找到图片10|
 
-|uarttt010|
 
-图 23‑9 连接串口线和跳帽
 
 与Windows主机通讯
-^^^^^^^^^^^^
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 
 配置串口调试助手
-''''''''
+''''''''''''''''''''''''
+
+在Windows的电脑端，打开串口调试助手，如下图所示。
 
-在Windows的电脑端，打开串口调试助手，如图 23‑10。
+.. image:: media/uarttt011.jpg
+   :align: center
+   :alt: 未找到图片11|
 
-|uarttt011|
 
-图 23‑10 Windows的串口调试助手配置
 
-使用串口调试助手时，要注意端口号，如果是使用USB转串口线的话，可以在Windows系统的设备管理器中查找到，把线从电脑上拔掉或插入可以看到设备列表的更新，从图 23‑11中可以看到本电脑有两个CH340 USB转串口设备，其中COM4
+使用串口调试助手时，要注意端口号，如果是使用USB转串口线的话，可以在Windows系
+统的设备管理器中查找到，把线从电脑上拔掉或插入可以看到设备列表的更新，从下图中可以
+看到本电脑有两个CH340 USB转串口设备，其中COM4
 是连接到开发板串口3的设备，COM5是连接到开发板的串口1终端的设备，请根据自己电脑的实际情况选择。
 
-|uarttt012|
+.. image:: media/uarttt012.png
+   :align: center
+   :alt: 未找到图片12|
+
 
-图 23‑11 设备管理器下的COM设备
 
 另外还要注意串口的波特率，串口调试助手的波特率要与开发板串口的设置一致。
 
 串口通讯实验
-''''''
+''''''''''''''''''
 
 配置好串口调试助手后，尝试使用如下命令测试发送数据：
 
-#在开发板上的终端执行如下指令
-
-#查看设备参数，确认波特率与串口调试助手的一致
-
-stty -F /dev/ttymxc2
+.. code-block:: sh
+   :linenos:
 
-#使用echo命令向终端设备文件写入字符串“board”
+   #在开发板上的终端执行如下指令
+   #使用echo命令向终端设备文件写入字符串"board"、"embedfire"
+   echo board > /dev/ttymxc2
+   echo embedfire > /dev/ttymxc2
+   #Windows上的串口调试助手会接收到内容
 
-echo board > /dev/ttymxc2
+如下图:
 
-#Windows上的串口调试助手会接收到内容
+.. image:: media/uarttt013.jpg
+   :align: center
+   :alt: 未找到图片13|
 
-|uarttt013|
 
-图 23‑12 使用串口从开发板向Windows主机发送内容
 
-从图 23‑12可看到，往/dev/ttymxc2设备文件写入的内容会直接通过串口线发送至Winodws的主机。
+可以看到，往/dev/ttymxc2设备文件写入的内容会直接通过串口线发送至Winodws的主机。
 
 而读取设备文件则可接收Winodws主机发往开发板的内容，可以使用cat命令来读取：
 
-#在开发板上的终端执行如下指令
+.. code-block:: sh
+   :linenos:
 
-#使用cat命令读取终端设备文件
+   #在开发板上的终端执行如下指令
+   #使用cat命令读取终端设备文件
+   cat /dev/ttymxc2
+   #cat命令会等待
+   #使用串口调试助手发送字符串
+   #字符串最后必须加回车！
+   #开发板的终端会输出接收到的内容
 
-cat /dev/ttymxc2
+如下图:
 
-#cat命令会等待
+.. image:: media/uarttt014.jpg
+   :align: center
+   :alt: 未找到图片14|
 
-#使用串口调试助手发送字符串
 
-#字符串最后必须加回车！
-
-#开发板的终端会输出接收到的内容
-
-|uarttt014|
-
-图 23‑13 从串口接收Windows主机发送到板子的内容
 
 与Ubuntu主机通讯
-^^^^^^^^^^^
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 
 分配USB转串口设备
-''''''''''
+''''''''''''''''''''''''''''''
 
 在Linux下串口调试的过程也是类似的，不过要注意虚拟机的配置。
 
-实验前同样要先接上前面图 23‑2中的USB转串口线到电脑上，并且在虚拟机界面的右下方设置把该USB设备分配到虚拟机上。
+实验前同样要先接上USB转串口线到电脑上，并且在虚拟机界面的右下方设置把该USB设备分配到虚拟机上。
+
+如下图:
+
+.. image:: media/uarttt015.png
+   :align: center
+   :alt: 未找到图片15|
+
 
-|uarttt015|
 
-图 23‑14分配USB转串口设备到虚拟机上
+通过对比分配设备前后/dev/ 目录下的tty*文件，可以了解到插入的USB转串口线对应
+的是哪个设备文件。在本主机中，新增的设备文件是"/dev/ttyUSB0"，如下图，请根据自己主机的情
+况确认具体的设备文件，在后面配置串口参数时需要用到。
 
-通过对比分配设备前后/dev/ 目录下的tty*文件，可以了解到插入的USB转串口线对应的是哪个设备文件。在本主机中，新增的设备文件是“/dev/ttyUSB0”，如图 23‑15，请根据自己主机的情况确认具体的设备文件，在后面配置串口参数时需要用到。
+.. image:: media/uarttt016.png
+   :align: center
+   :alt: 未找到图片16|
 
-|uarttt016|
 
-图 23‑15 插入USB转串口线后新增的设备
 
 安装和配置minicom
-''''''''''''
+''''''''''''''''''''''''''''''''''''
 
-Linux下也有类似Windows的图形界面串口调试助手，不过此处想推荐大家学习一款在Linux终端下的工具minicom，使用该工具可以在无界面的系统上调试串口。
+Linux下也有类似Windows的图形界面串口调试助手，不过此处想推荐大家
+学习一款在Linux终端下的工具minicom，使用该工具可以在无界面的系统上调试串口。
 
 在Ubuntu主机上可以直接用以下命令安装和配置minicom：
 
-#以下命令在主机上执行
+.. code-block:: sh
+   :linenos:
 
-sudo apt install minicom
+   #以下命令在主机上执行
+   sudo apt install minicom
+   #安装成功后使用如下命令运行配置
+   #需要使用sudo权限运行
+   sudo minicom -s
 
-#安装成功后使用如下命令运行配置
+.. image:: media/uarttt017.png
+   :align: center
+   :alt: 未找到图片17|
 
-#需要使用sudo权限运行
 
-sudo minicom -s
 
-|uarttt017|
+上图是minicom运行时的配置界面，注意执行minicom命令时需要使用sudo获取权限，否则无法
+修改设备的参数。在该界面中使用键盘的上下方向键和回车键可以进入菜单进行配置，此处我
+们选择"Serial port setup"菜单配置串口参数，如下图所示。
 
-图 23‑16 minicom运行配置界面
+.. image:: media/uarttt018.png
+   :align: center
+   :alt: 未找到图片18|
 
-图 23‑16是minicom运行时的配置界面，注意执行minicom命令时需要使用sudo获取权限，否则无法修改设备的参数。在该界面中使用键盘的上下方向键和回车键可以进入菜单进行配置，此处我们选择“Serial port setup”菜单配置串口参数，如图 23‑17。
 
-|uarttt018|
 
-图 23‑17 minicom修改串口配置
+在配置串口参数页面中根据提示的按键"A"、"E"、"F"配置串口设备为"/dev/ttyUSB0"（根据自己的电
+脑设备选择）、波特率为"9600"、以及不使用硬件流控"No"，配置完成后按回车键退出当前菜
+单。然后再选择"Save setup as dfl"菜单保存配置，见下图（若提示无法保
+存，请确保前面是使用"sudo"权限运行minicom的），保存完成后选
+择"Exit"菜单或按键盘的"Esc"键即可进入终端界面。
 
-在配置串口参数页面中根据提示的按键“A”、“E”、“F”配置串口设备为“/dev/ttyUSB0”（根据自己的电脑设备选择）、波特率为“9600”、以及不使用硬件流控“No”，配置完成后按回车键退出当前菜单。然后再选择“Save setup as dfl”菜单保存配置，见图
-23‑18（若提示无法保存，请确保前面是使用“sudo”权限运行minicom的），保存完成后选择“Exit”菜单或按键盘的“Esc”键即可进入终端界面。
+如下图:
 
-|uarttt019|
+.. image:: media/uarttt019.png
+   :align: center
+   :alt: 未找到图片19|
 
-图 23‑18 minicom保存配置
 
-从配置菜单退出后可进入minicom的终端界面，也可以在保存配置完全退出minicom后，重新执行命令打开它的终端：
+
+从配置菜单退出后可进入minicom的终端界面，也可以在保存
+配置完全退出minicom后，重新执行命令打开它的终端：
 
 #以下命令在Ubuntu主机上执行
 
-minicom
+.. code-block:: sh
+   :linenos:
+
+   sudo minicom
+
+下图是minicom打开的终端界面，默认包含了当前打开的串口
+设备信息，当该设备接收到内容时，会在终端上显示出来，而在终端输入的内容则会通过串口发送出去。
+
+如下图:
 
-图 23‑19是minicom打开的终端界面，默认包含了当前打开的串口设备信息，当该设备接收到内容时，会在终端上显示出来，而在终端输入的内容则会通过串口发送出去。
+.. image:: media/uarttt020.png
+   :align: center
+   :alt: 未找到图片20|
 
-|uarttt020|
 
-图 23‑19 minicom终端运行界面
 
-在minicom的终端界面中，按下Ctrl+A键再按下Z键可以查看帮助，按下Ctrl+A键再按下X键可以退出。
+在minicom的终端界面中，按下Ctrl+A键再按下Z
+键可以查看帮助，按下Ctrl+A键再按下X键可以退出。
 
 .. _串口通讯实验-1:
 
 串口通讯实验
-''''''
+''''''''''''''''''
 
-配置好minicom后，就可以使用它与开发板进行串口通讯实验了，操作方式与Windows下是类似的，在开发板使用echo和cat命令对终端设备文件进行读写，实现串口通讯。
+配置好minicom后，就可以使用它与开发板进行串口通讯
+实验了，操作方式与Windows下是类似的，在开发板使用echo和cat命令
+对终端设备文件进行读写，实现串口通讯。
 
 使用如下命令测试收发数据：
 
-#在开发板上的终端执行如下指令
+.. code-block:: sh
+   :linenos:
 
-#查看设备参数，确认波特率与串口调试助手的一致
+   #在开发板上的终端执行如下指令
+   #使用echo命令向终端设备文件写入字符串"board"、"embedfire"
+   echo board > /dev/ttymxc2
+   echo embedfire > /dev/ttymxc2
 
-stty -F /dev/ttymxc2
+Ubuntu主机上的minicom会显示接收到内容
 
-#使用echo命令向终端设备文件写入字符串“board”
+如下图:
 
-echo board > /dev/ttymxc2
+.. image:: media/uarttt021.jpg
+   :align: center
+   :alt: 未找到图片21|
 
-#Ubuntu主机上的minicom会显示接收到内容
 
-|uarttt021|
-
-图 23‑20 使用minicom接收开发板的数据
 
 开发板接收串口内容的实验步骤如下：
 
-#在开发板上的终端执行如下指令
-
-#使用cat命令读取终端设备文件
-
-cat /dev/ttymxc2
+.. code-block:: sh
+   :linenos:
 
-#cat命令会等待
+   #在开发板上的终端执行如下指令
+   #使用cat命令读取终端设备文件
+   cat /dev/ttymxc2
+   #cat命令会等待
+   #在Ubuntu主机的minicom界面输入内容
+   #字符串最后必须加回车！
+   #开发板的终端会输出接收到的内容
 
-#在Ubuntu主机的minicom界面输入内容
+如下图:
 
-#字符串最后必须加回车！
+.. image:: media/uarttt022.jpg
+   :align: center
+   :alt: 未找到图片22|
 
-#开发板的终端会输出接收到的内容
 
-|uarttt022|
-
-图 23‑21 使用minicom发送数据到开发板
 
 串口通讯实验（系统调用）
-~~~~~~~~~~~~
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
-如果只是想通过串口终端设备收发数据，那么使用open、read、write等系统调用能轻易实现，操作的原理和前面的led、gpio、input设备并无区别，都是读写设备文件。但是led、gpio和input除了主设备文件，还有众多的属性文件配合用于设置设备的运行参数，如led的trigger文件，g
-pio的direction文件，而终端设备却没有其它的属性文件，那么stty命令和minicom工具是如何配置终端设备参数的呢？
+如果只是想通过串口终端设备收发数据，那么使用open、read、write等系统调
+用能轻易实现，操作的原理和前面的led、gpio、input设备并无区别，都是读写设备
+文件。但是led、gpio和input除了主设备文件，还有众多的属性文件配合用于设置设备的运
+行参数，如led的trigger文件，g
+pio的direction文件，而终端设备却没有其它的属性文件，那
+么stty命令和minicom工具是如何配置终端设备参数的呢？
 
 实验代码分析
-^^^^^^
-
-我们直接通过修改串口终端参数的示例代码来解答这个疑惑，见代码清单 23‑1。
-
-代码清单 23‑1 串口通讯示例（base_code/section2/tty/c/source/main.c文件）
-
-1 #include <stdio.h>
-
-2 #include <stdlib.h>
-
-3 #include <unistd.h>
-
-4 #include <fcntl.h>
-
-5 #include <sys/stat.h>
-
-6 #include <sys/types.h>
-
-7 #include <termios.h>
-
-8 #include <string.h>
-
-9 #include <sys/ioctl.h>
-
-10
-
-11 /第一部分代码/
-
-12 //根据具体的设备修改
-
-13 const char default_path[] = "/dev/ttymxc2";
-
-14 // const char default_path[] = "/dev/ttymxc2";
-
-15
-
-16
-
-17 int main(int argc, char \*argv[])
-
-18 {
-
-19 int fd;
-
-20 int res;
-
-21 char \*path;
-
-22 char buf[1024] = "Embedfire tty send test.\n";
-
-23
-
-24 /第二部分代码/
-
-25
-
-26 //若无输入参数则使用默认终端设备
-
-27 if (argc > 1)
-
-28 path = argv[1];
-
-29 else
-
-30 path = (char \*)default_path;
-
-31
-
-32 //获取串口设备描述符
-
-33 printf("This is tty/usart demo.\n");
-
-34 fd = open(path, O_RDWR);
-
-35 if (fd < 0) {
-
-36 printf("Fail to Open %s device\n", path);
-
-37 return 0;
-
-38 }
-
-39
-
-40 /第三部分代码/
-
-41 struct termios opt;
-
-42
-
-43 //清空串口接收缓冲区
-
-44 tcflush(fd, TCIOFLUSH);
-
-45 // 获取串口参数opt
-
-46 tcgetattr(fd, &opt);
-
-47
-
-48 //设置串口输出波特率
-
-49 cfsetospeed(&opt, B9600);
-
-50 //设置串口输入波特率
-
-51 cfsetispeed(&opt, B9600);
-
-52 //设置数据位数
-
-53 opt.c_cflag &= ~CSIZE;
-
-54 opt.c_cflag \|= CS8;
-
-55 //校验位
-
-56 opt.c_cflag &= ~PARENB;
-
-57 opt.c_iflag &= ~INPCK;
-
-58 //设置停止位
-
-59 opt.c_cflag &= ~CSTOPB;
-
-60
-
-61 //更新配置
-
-62 tcsetattr(fd, TCSANOW, &opt);
-
-63
-
-64 printf("Device %s is set to 9600bps,8N1\n",path);
-
-65
-
-66 /第四部分代码/
-
-67
-
-68 do {
-
-69 //发送字符串
-
-70 write(fd, buf, strlen(buf));
-
-71 //接收字符串
-
-72 res = read(fd, buf, 1024);
-
-73 if (res >0 ) {
-
-74 //给接收到的字符串加结束符
-
-75 buf[res] = '\0';
-
-76 printf("Receive res = %d bytes data: %s\n",res, buf);
-
-77 }
-
-78 } while (res >= 0);
-
-79
-
-80 printf("read error,res = %d",res);
-
-81
-
-82 close(fd);
-
-83 return 0;
-
-84 }
+^^^^^^^^^^^^^^^^^^
+
+我们直接通过修改串口终端参数的示例代码来解答这个疑惑，源码如下所示。
+
+
+
+.. code-block:: c
+   :caption: 串口通讯示例（base_code/linux_app/tty/c/source/main.c文件）
+   :linenos: 
+
+   #include <stdio.h>
+   #include <stdlib.h>
+   #include <unistd.h>
+   #include <fcntl.h>
+   #include <sys/stat.h>
+   #include <sys/types.h>
+   #include <termios.h>
+   #include <string.h>
+   #include <sys/ioctl.h>
+   
+   /第一部分代码/
+   //根据具体的设备修改
+   const char default_path[] = "/dev/ttymxc2";
+   // const char default_path[] = "/dev/ttymxc2";
+   
+   
+   int main(int argc, char *argv[])
+   {
+   int fd;
+   int res;
+   char *path;
+   char buf[1024] = "Embedfire tty send test.\n";
+   
+   /第二部分代码/
+   
+   //若无输入参数则使用默认终端设备
+   if (argc > 1)
+   path = argv[1];
+   else
+   path = (char *)default_path;
+   
+   //获取串口设备描述符
+   printf("This is tty/usart demo.\n");
+   fd = open(path, O_RDWR);
+   if (fd < 0) {
+   printf("Fail to Open %s device\n", path);
+   return 0;
+   }
+   
+   /第三部分代码/
+   struct termios opt;
+   
+   //清空串口接收缓冲区
+   tcflush(fd, TCIOFLUSH);
+   // 获取串口参数opt
+   tcgetattr(fd, &opt);
+   
+   //设置串口输出波特率
+   cfsetospeed(&opt, B9600);
+   //设置串口输入波特率
+   cfsetispeed(&opt, B9600);
+   //设置数据位数
+   opt.c_cflag &= ~CSIZE;
+   opt.c_cflag \|= CS8;
+   //校验位
+   opt.c_cflag &= ~PARENB;
+   opt.c_iflag &= ~INPCK;
+   //设置停止位
+   opt.c_cflag &= ~CSTOPB;
+   
+   //更新配置
+   tcsetattr(fd, TCSANOW, &opt);
+   
+   printf("Device %s is set to 9600bps,8N1\n",path);
+   
+   /第四部分代码/
+   
+   do {
+   //发送字符串
+   write(fd, buf, strlen(buf));
+   //接收字符串
+   res = read(fd, buf, 1024);
+   if (res >0 ) {
+   //给接收到的字符串加结束符
+   buf[res] = '\0';
+   printf("Receive res = %d bytes data: %s\n",res, buf);
+   }
+   } while (res >= 0);
+   
+   printf("read error,res = %d",res);
+   
+   close(fd);
+   return 0;
+   }
 
 为便于讲解，我们把代码分成四个部分：
 
@@ -507,47 +538,46 @@ pio的direction文件，而终端设备却没有其它的属性文件，那么st
 
 -  第二部分：根据main是否有输入参数确认使用哪个设备路径，并通过open的O_RDWR读写模式打开该设备。
 
--  第三部分：定义了一个结构体termios用于获取、设置终端设备的参数，包括波特率、数据位数、校验位等，这是本章的重点，在下一小节详细说明。
+-  第三部分：定义了一个结构体termios用于获取、设置终端设备的参数，包括波特率、数据位数、校验位等，这是
+   本章的重点，在下一小节详细说明。
 
--  第四部分：在while循环中对终端设备使用read和write进行读写，从而控制串口收发数据。代码中在接收到的内容末尾加了’\0’结束符，主要是为了方便使用字符串的方式处理内容。
+-  第四部分：在while循环中对终端设备使用read和write进行读写，从而
+   控制串口收发数据。代码中在接收到的内容末尾加了’\0’结束符，主要是为了方便使用字符串的方式处理内容。
 
 termios结构体
-^^^^^^^^^^
-
-示例代码中的第三部分，使用了termios结构体，它是在POSIX规范中定义的标准接口。Linux系统利用termios来设置串口的参数，它是在头文件<termios.h>包含的<bits/termios.h>中定义的，该文件中还包含了各个结构体成员可使用的宏值，请自己使用locate命令查找该文件
-打开来阅读，关于termios结构体的定义摘录如代码清单 23‑2。
-
-代码清单 23‑2 termios结构体（位于主机/usr/include/bits/termios.h文件）
-
-1 struct termios {
-
-2 tcflag_t c_iflag; /\* input mode flags \*/
-
-3 tcflag_t c_oflag; /\* output mode flags \*/
-
-4 tcflag_t c_cflag; /\* control mode flags \*/
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 
-5 tcflag_t c_lflag; /\* local mode flags \*/
+示例代码中的第三部分，使用了termios结构体，它是在POSIX规范中定义的标准接口。Linux系统利
+用termios来设置串口的参数，它是在头文件<termios.h>包含的<bits/termios.h>中定义的，该文
+件中还包含了各个结构体成员可使用的宏值，请自己使用locate命令查找该文件
+打开来阅读，关于termios结构体的定义摘录如下所示。
 
-6 cc_t c_line; /\* line discipline \*/
 
-7 cc_t c_cc[NCCS]; /\* control characters \*/
 
-8 speed_t c_ispeed; /\* input speed \*/
 
-9 speed_t c_ospeed; /\* output speed \*/
 
-10 #define \_HAVE_STRUCT_TERMIOS_C_ISPEED 1
+.. code-block:: c
+   :caption: termios结构体（位于主机/usr/include/bits/termios.h文件）
+   :linenos:  
 
-11 #define \_HAVE_STRUCT_TERMIOS_C_OSPEED 1
-
-12 };
+   struct termios {
+   tcflag_t c_iflag; /* input mode flags */
+   tcflag_t c_oflag; /* output mode flags */
+   tcflag_t c_cflag; /* control mode flags */
+   tcflag_t c_lflag; /* local mode flags */
+   cc_t c_line; /* line discipline */
+   cc_t c_cc[NCCS]; /* control characters */
+   speed_t c_ispeed; /* input speed */
+   speed_t c_ospeed; /* output speed */
+    #define _HAVE_STRUCT_TERMIOS_C_ISPEED 1
+    #define _HAVE_STRUCT_TERMIOS_C_OSPEED 1
+    };
 
 下面我们介绍一下各个结构体成员，主要是关注c_iflag、c_cflag以及c_ispeed、c_ospeed即可：
 
--  c_iflag：输入（input）模式标志，用于控制如何对串口输入的字符进行处理，常用的选项值见表 23‑1。
+-  c_iflag：输入（input）模式标志，用于控制如何对串口输入的字符进行处理，常用的选项值见下表。
 
-表 23‑1 c_iflag选项值
+表    c_iflag选项值
 
 ====== ========================
 选项值 作用
@@ -559,9 +589,9 @@ IXON   开启XON/XOFF流控制
 IXOFF  关闭XON/XOFF流控制
 ====== ========================
 
--  c_oflag：输出（output）模式标志，用于控制串口的输出模式，常用的选项值见表 23‑2。
+-  c_oflag：输出（output）模式标志，用于控制串口的输出模式，常用的选项值见下表。
 
-表 23‑2 c_oflag选项值
+表    c_oflag选项值
 
 ====== ===================================
 选项值 作用
@@ -572,9 +602,10 @@ ONLRET 不输出回车
 OFILL  发送填充字符串
 ====== ===================================
 
--  c_cflag：控制（control）模式标志，用于控制串口的基本参数，如数据位、停止位等，常用配置见表 23‑3，特别地，c_cflag结构体成员还包含了波特率的参数。
+-  c_cflag：控制（control）模式标志，用于控制串口的基本参数，如数据位、停止位等，常
+用配置见下表，特别地，c_cflag结构体成员还包含了波特率的参数。
 
-表 23‑3 c_cflag选项值
+表   c_cflag选项值
 
 ====== ==============================================
 选项值 作用
@@ -596,9 +627,10 @@ ICANON 若设置了 ICANON 标志，则表示终端处于规范式输入状态
 ECHONL 若该标志位和ICANON标志位同时被设置，则回显换行符NL
 ====== ===============================================================================
 
--  c_cc[NCCS]：该数组包含了终端的所有特殊字符，可以修改特殊字符对应的键值（Ctrl+C产生的^C，ASCII码为0x03），部分内容如表 23‑4。
+-  c_cc[NCCS]：该数组包含了终端的所有特殊字符，可以修改特殊字符对应
+的键值（Ctrl+C产生的^C，ASCII码为0x03），部分内容如下表。
 
-表 23‑4 c_cc中各成员对应的下标值
+表   c_cc中各成员对应的下标值
 
 ============ =====================================================================================================
 数组的下标值 作用
@@ -609,78 +641,73 @@ VIM          设置非标准模式读取的最小字节数
 VTIM         设置非标准模式读取时的延时值，单位为十分之一秒。
 ============ =====================================================================================================
 
--  c_ispeed和c_ospeed：记录串口的输入和输出波特率（input speed和output speed），部分可取值如代码清单 23‑3所示，宏定义中的数字以“0”开头，在C语言中这是表示8进制数字的方式。
-
-代码清单 23‑3 波特率定义（位于/usr/include/bits/termios.h）
-
-1 //注意以0开头的数字在是C语言的8进制数字形式
-
-2 #define B1200 0000011
+-  c_ispeed和c_ospeed：记录串口的输入和输出波特率（input speed和output speed），部分可
+   取值如下代码所示，宏定义中的数字以"0"开头，在C语言中这是表示8进制数字的方式。
 
-3 #define B1800 0000012
 
-4 #define B2400 0000013
 
-5 #define B4800 0000014
+.. code-block:: c
+   :caption: 波特率定义（位于/usr/include/bits/termios.h）
+   :linenos:  
 
-6 #define B9600 0000015
+   //注意以0开头的数字在是C语言的8进制数字形式
+   #define B1200 0000011
+   #define B1800 0000012
+   #define B2400 0000013
+   #define B4800 0000014
+   #define B9600 0000015
+   #define B19200 0000016
+   #define B38400 0000017
 
-7 #define B19200 0000016
+-  宏定义：termios结构体内部有_HAVE_STRUCT_TERMIOS_C_ISPEED和_HAVE_STRUCT_TERMIOS_C_OSPEED两个
+   宏定义，它们的宏值都为1，表示它
+   支持c_ispeed和c_ospeed表示方式，部分标准中不支持使用这两个结构体成员表示波特率，而只使用c_cflag来表示。
 
-8 #define B38400 0000017
-
--  宏定义：termios结构体内部有_HAVE_STRUCT_TERMIOS_C_ISPEED
-  和_HAVE_STRUCT_TERMIOS_C_OSPEED两个宏定义，它们的宏值都为1，表示它支持c_ispeed和c_ospeed表示方式，部分标准中不支持使用这两个结构体成员表示波特率，而只使用c_cflag来表示。
-
-直接看结构体的定义比较抽象，下面我们以修改串口波特率、数据位、校验位和停止位的示例代码进行讲解。接下来几个小节的代码，是我们从base_code/section2/tty/c_full/sources/bsp_uart.c文件截取的，该文件以比较完善的方式封装了串口的配置，而本书提取出了代码中的重点
+直接看结构体的定义比较抽象，下面我们以修改串口波特率、数据位、校验位和停止位的示例代码进行讲解。接下来几个小节的代码，是我们从base_code/linux_app/tty/c_full/sources/bsp_uart.c文件截取的，该文件以比较完善的方式封装了串口的配置，而本书提取出了代码中的重点
 进行分析，感兴趣的读者可以打开配套的工程文件阅读。
 
 配置串口波特率
-'''''''
-
-修改终端串口波特率的示例代码如代码清单 23‑4。
+'''''''''''''''''''''
 
-代码清单 23‑4 示例代码-修改串口波特率
+修改终端串口波特率的示例代码如下所示。
 
-1 //定义termios型变量opt
 
-2 struct termios opt;
 
-3
+.. code-block:: c
+   :caption: 示例代码-修改串口波特率
+   :linenos: 
 
-4 //fd是使用open打开设备文件得到的文件句柄
-
-5 // 获取串口参数opt
-
-6 tcgetattr(fd, &opt);
-
-7 //设置串口输出波特率
-
-8 cfsetospeed(&opt, B9600);
-
-9 //设置串口输入波特率
-
-10 cfsetispeed(&opt, B9600);
-
-11 //更新配置
-
-12 tcsetattr(fd, TCSANOW, &opt);
+   //定义termios型变量opt
+   struct termios opt;
+   //fd是使用open打开设备文件得到的文件句柄
+   // 获取串口参数opt
+   tcgetattr(fd, &opt);
+   //设置串口输出波特率
+   cfsetospeed(&opt, B9600);
+   //设置串口输入波特率
+    cfsetispeed(&opt, B9600);
+    //更新配置
+    tcsetattr(fd, TCSANOW, &opt);
 
 代码中使用到了头文件termios.h的库函数tcgetattr、cfsetispeed、cfsetospeed和tcsetattr。
 
 其中tcgetattr和tcsetattr函数分别用于读取和设置串口的参数，原型如下：
 
-#include <termios.h>
-
-#include <unistd.h>
+.. code-block:: sh
+   :linenos:
 
-int tcgetattr(int fd, struct termios \*termios_p);
-
-int tcsetattr(int fd, int optional_actions, const struct termios \*termios_p);
+   #include <termios.h>
+   
+   #include <unistd.h>
+   
+   int tcgetattr(int fd, struct termios *termios_p);
+   
+   int tcsetattr(int fd, int optional_actions, const struct termios *termios_p);
 
 -  形参fd：指定串口设备文件的文件描述符。
 
--  形参termios_p：指向串口参数的结构体termios，tcgetattr读取到的参数会保存在该结构体中，而tcsetattr则根据该结构体配置设备参数。
+-  形参termios_p：指向串口参数的结构体termios，tcgetattr读取到的参数会
+   保存在该结构体中，而tcsetattr则根据该结构体配置设备参数。
 
 -  形参optional_actions：仅tcsetattr函数有这个参数，它用于指示配置什么时候生效，它支持的配置参数如下：
 
@@ -692,826 +719,630 @@ int tcsetattr(int fd, int optional_actions, const struct termios \*termios_p);
 
 跟示例代码中的一样，通常都使用选项TCSANOW，让写入的参数配置立马生效。
 
-代码中的cfsetispeed和cfsetospeed函数分别用于设置termios结构体的输入和输出波特率，另外还有cfsetspeed函数可以同时设置输入和输出波特率参数为相同的值，原型如下：
-
-int cfsetispeed(struct termios \*termios_p, speed_t speed);
+代码中的cfsetispeed和cfsetospeed函数分别用于设置termios结构体的输入和输出波
+特率，另外还有cfsetspeed函数可以同时设置输入和输出波特率参数为相
+同的值，原型如下：
 
-int cfsetospeed(struct termios \*termios_p, speed_t speed);
+.. code-block:: sh
+   :linenos:
 
-int cfsetspeed(struct termios \*termios_p, speed_t speed);
+   int cfsetispeed(struct termios *termios_p, speed_t speed);
+   
+   int cfsetospeed(struct termios *termios_p, speed_t speed);
+   
+   int cfsetspeed(struct termios *termios_p, speed_t speed);
 
 使用这些函数要注意两点：
 
--  speed参数需要使用类似前面代码清单 23‑3定义的宏值。
+-  speed参数需要使用类似前面代码定义的宏值。
 
--  这三个函数只是修改了termios的opt变量的内容，并没有写入到设备文件，因此在修改完它的内容后，还需要调用tcsetattr函数，把opt变量中的配置写入到设备，使它生效。
+-  这三个函数只是修改了termios的opt变量的内容，并没有写入到设备文件，因此在修改完
+   它的内容后，还需要调用tcsetattr函数，把opt变量中的配置写入到设备，使它生效。
 
 这就是修改终端设备参数的过程，读取原配置、修改termios参数、写入termios参数。
 
 配置串口停止位
-'''''''
-
-c_cflag中的标志位CSTOPB，用于设置串口通信停止位的长度。若该值为0，则停止位的长度为1位；若设置该位为1，则停止位的长度为两位，具体实现见代码清单 23‑5。
-
-代码清单 23‑5 示例代码-配置停止位
-
-1 //在bits/termios.h文件中关于CSTOPB的定义
-
-2 //注意以0开头的数字在是C语言的8进制数字形式
-
-3 #define CSTOPB 0000100
-
-4 //
-
-5 //设置停止位示例
-
-6 //定义termios型变量opt
-
-7 struct termios opt;
-
-8
-
-9 // 获取串口参数opt
-
-10 tcgetattr(fd, &opt);
-
-11
-
-12 /\* 设置停止位*/
-
-13 switch (stopbits)
-
-14 {
-
-15 //设置停止位为1位
-
-16 case 1:
-
-17 opt.c_cflag &= ~CSTOPB;
-
-18 break;
-
-19 //设置停止位为2位
-
-20 case 2:
-
-21 opt.c_cflag \|= CSTOPB;
-
-22 break;
-
-23 }
-
-24
-
-25 //更新配置
-
-26 tcsetattr(fd, TCSANOW, &opt);
+'''''''''''''''''''''
+
+c_cflag中的标志位CSTOPB，用于设置串口通信停止位的长度。若该值为0，则停止位的长
+度为1位；若设置该位为1，则停止位的长度为两位，具体实现如下所示。
+
+
+
+.. code-block:: c
+   :caption: 示例代码-配置停止位
+   :linenos:  
+
+   //在bits/termios.h文件中关于CSTOPB的定义
+   //注意以0开头的数字在是C语言的8进制数字形式
+   #define CSTOPB 0000100
+   //
+   //设置停止位示例
+   //定义termios型变量opt
+   struct termios opt;
+   // 获取串口参数opt
+    tcgetattr(fd, &opt);
+   
+    /* 设置停止位*/
+    switch (stopbits)
+    {
+    //设置停止位为1位
+    case 1:
+    opt.c_cflag &= ~CSTOPB;
+    break;
+    //设置停止位为2位
+    case 2:
+    opt.c_cflag \|= CSTOPB;
+    break;
+    }
+   
+    //更新配置
+    tcsetattr(fd, TCSANOW, &opt);
 
 示例代码依然是采取了获取当前参数、修改配置、更新配置的套路。
 
-修改配置的代码中使用了“&=~”、“|=”这种位操作方法，主要是为了避免影响到变量中的其它位，因为在c_cflag的其它位还包含了校验位、数据位和波特率相关的配置，如果直接使用“=”赋值，那其它配置都会受到影响，而且操作不方便。在后面学习裸机开发，对寄存器操作时会经常用到这种方式。若没接触过这些位操
+修改配置的代码中使用了"&=~"、"|="这种位操作
+方法，主要是为了避免影响到变量
+中的其它位，因为在c_cflag的其它位还包含了校验位、数据位和波特率相关的配置，如果直
+接使用"="赋值，那其它配置都会受到影响，而且操作不方便。在后面学习裸机开发，对寄存器操作
+时会经常用到这种方式。若没接触过这些位操
 作方式，可参考本书附录中《第65章 位操作方法》的说明。
 
-简单来说，示例中的“&=~”把c_cflag变量中CSTOPB对应的数据位清0，而“|=”则把c_cflag变量中CSTOPB对应的数据位置1，达到在不影响其它配置的情况下把停止位配置为1位或两位。
+简单来说，示例中的"&=~"把c_cflag变量中CSTOPB对应的数
+据位清0，而"|="则把c_cflag变量中CSTOPB对应的
+数据位置1，达到在不影响其它配置的情况下把停止位配置为1位或两位。
 
 配置串口校验位
-'''''''
-
-配置串口的校验位涉及到termios成员c_cflag的标志位PARENB、PARODD 以及c_iflag的标志位INPCK，其中PARENB和INPCK共同决定是否使能奇偶校验，而PARODD 决定使用奇校验还是偶校验，配置的示例代码清单 23‑6。
-
-代码清单 23‑6 示例代码-配置奇偶校验
-
-1 //bits/termios.h的位定义
-
-2 //注意以0开头的数字在是C语言的8进制数字形式
-
-3 /\* c_cflag bit meaning \*/
-
-4 #define PARENB 0000400
-
-5 #define PARODD 0001000
-
-6 /\* c_iflag bits \*/
-
-7 #define INPCK 0000020
-
-8
-
-9 //
-
-10 //定义termios型变量opt
-
-11 struct termios opt;
-
-12 // 获取串口参数opt
-
-13 tcgetattr(fd, &opt);
-
-14
-
-15 switch (parity)
-
-16 {
-
-17 case 'n':
-
-18 case 'N':
-
-19 options.c_cflag &= ~PARENB; /\* 不使用奇偶校验 \*/
-
-20 options.c_iflag &= ~INPCK; /\* 禁止输入奇偶检测 \*/
-
-21 break;
-
-22 case 'o':
-
-23 case 'O':
-
-24 options.c_cflag \|= PARENB; /\* 启用奇偶效验 \*/
-
-25 options.c_iflag \|= INPCK; /\* 启用输入奇偶检测 \*/
-
-26 options.c_cflag \|= PARODD ; /\* 设置为奇效验 \*/
-
-27 break;
-
-28 case 'e':
-
-29 case 'E':
-
-30 options.c_cflag \|= PARENB; /\* 启用奇偶效验 \*/
-
-31 options.c_iflag \|= INPCK; /\* 启用输入奇偶检测 \*/
-
-32 options.c_cflag &= ~PARODD; /\* 设置为偶效验*/
-
-33 break;
-
-34 }
-
-35
-
-36 //更新配置
-
-37 tcsetattr(fd, TCSANOW, &opt);
+''''''''''''''''''''''''''''
+
+配置串口的校验位涉及到termios成员c_cflag的标志位PARENB、PARODD 以及c_iflag的标志
+位INPCK，其中PARENB和INPCK共同决定是否使能奇偶校验，而PARODD 决定使用奇校验还是偶校验，配置的示例代码如下所示。
+
+
+
+.. code-block:: c
+   :caption: 示例代码-配置奇偶校验
+   :linenos:  
+
+   //bits/termios.h的位定义
+   //注意以0开头的数字在是C语言的8进制数字形式
+   /* c_cflag bit meaning */
+   #define PARENB 0000400
+   #define PARODD 0001000
+   /* c_iflag bits */
+   #define INPCK 0000020
+   //
+    //定义termios型变量opt
+    struct termios opt;
+    // 获取串口参数opt
+    tcgetattr(fd, &opt);
+   
+    switch (parity)
+    {
+    case 'n':
+    case 'N':
+    options.c_cflag &= ~PARENB; /* 不使用奇偶校验 */
+    options.c_iflag &= ~INPCK; /* 禁止输入奇偶检测 */
+    break;
+    case 'o':
+    case 'O':
+    options.c_cflag \|= PARENB; /* 启用奇偶效验 */
+    options.c_iflag \|= INPCK; /* 启用输入奇偶检测 */
+    options.c_cflag \|= PARODD ; /* 设置为奇效验 */
+    break;
+    case 'e':
+    case 'E':
+    options.c_cflag \|= PARENB; /* 启用奇偶效验 */
+    options.c_iflag \|= INPCK; /* 启用输入奇偶检测 */
+    options.c_cflag &= ~PARODD; /* 设置为偶效验*/
+    break;
+    }
+   
+    //更新配置
+    tcsetattr(fd, TCSANOW, &opt);
 
 配置非常简单，不校验时同时把PARENB和INPCK位清零，启用校验时把PARENB和INPCK同时置1，而PARODD为1时指定为奇校验，为0时是偶校验。
 
 配置串口数据位
-'''''''
-
-串口的数据位是由c_cflag中的CSIZE配置的，由于串口支持5、6、7、8位的配置，一共有四种，所以在c_cflag中使用了两个数据位进行配置，在配置前我们需要先对CSIZE数据位清零，然后再赋予5、6、7、8的宏配置值，见代码清单 23‑7。
-
-代码清单 23‑7 示例代码-设置数据位长度位
-
-1 //bits/termios.h的位定义
-
-2 //注意以0开头的数字在是C语言的8进制数字形式
-
-3 #define CSIZE 0000060
-
-4 #define CS5 0000000
-
-5 #define CS6 0000020
-
-6 #define CS7 0000040
-
-7 #define CS8 0000060
-
-8
-
-9 //
-
-10 //定义termios型变量opt
-
-11 struct termios opt;
-
-12 // 获取串口参数opt
-
-13 tcgetattr(fd, &opt);
-
-14
-
-15 //先清除CSIZE数据位的内容
-
-16 opt.c_cflag &= ~CSIZE;
-
-17
-
-18 switch (databits) /*设置数据位数*/
-
-19 {
-
-20 case 5:
-
-21 opt.c_cflag \|= CS5;
-
-22 break;
-
-23 case 6:
-
-24 opt.c_cflag \|= CS6;
-
-25 break;
-
-26 case 7:
-
-27 opt.c_cflag \|= CS7;
-
-28 break;
-
-29 case 8:
-
-30 opt.c_cflag \|= CS8;
-
-31 break;
-
-32 }
-
-33 //更新配置
-
-34 tcsetattr(fd, TCSANOW, &opt);
-
-学习了使用termios结构体配置串口参数的各种方式后，请再回过头看看前面的代码清单 23‑1 main.c示例文件代码，相信已经不用再介绍了。
+'''''''''''''''''''''
+
+串口的数据位是由c_cflag中的CSIZE配置的，由于串
+口支持5、6、7、8位的配置，一共有四种，所以在c_cflag中使用了两个数据
+位进行配置，在配置前我们需要先对CSIZE数据位清零，然后再赋予5、6、7、8的宏配置值，具体代码如下所示。
+
+
+
+.. code-block:: c
+   :caption: 示例代码-设置数据位长度位
+   :linenos:  
+
+   //bits/termios.h的位定义
+   //注意以0开头的数字在是C语言的8进制数字形式
+   #define CSIZE 0000060
+   #define CS5 0000000
+   #define CS6 0000020
+   #define CS7 0000040
+   #define CS8 0000060
+   //
+    //定义termios型变量opt
+    struct termios opt;
+    // 获取串口参数opt
+    tcgetattr(fd, &opt);
+   
+    //先清除CSIZE数据位的内容
+    opt.c_cflag &= ~CSIZE;
+   
+    switch (databits) /*设置数据位数*/
+    {
+    case 5:
+    opt.c_cflag \|= CS5;
+    break;
+    case 6:
+    opt.c_cflag \|= CS6;
+    break;
+    case 7:
+    opt.c_cflag \|= CS7;
+    break;
+    case 8:
+    opt.c_cflag \|= CS8;
+    break;
+    }
+    //更新配置
+    tcsetattr(fd, TCSANOW, &opt);
+
+学习了使用termios结构体配置串口参数的各种方式后，请再回过头看看前面的main.c示例文件代码，相信已经不用再介绍了。
 
 编译及测试
-^^^^^
+^^^^^^^^^^^^^^^^^^^^
 
 本实验使用的Makefile相对于前面的章节仅修改了最终的可执行文件名为tty_demo。
 
 x86架构
-'''''
+''''''''''''''''''''
 
-本实验的main.c实验代码使用的终端设备文件默认是开发板上的ttymxc2按键，在Ubuntu主机上并没有这样的设备，如果想尝试在主机上使用，可以根据自己Ubuntu主机上可用的串口设备作为程序的输入参数输入运行，如本书示例的“/dev/ttyUSB0”，它使用USB转串口线连接至了开发板的串口3
+本实验的main.c实验代码使用的终端设备文件默认是开发板上的ttymxc2按键，在Ubuntu主机上并没
+有这样的设备，如果想尝试在主机上使用，可以根据自己Ubuntu主机上可用的串口设备作为程
+序的输入参数输入运行，如本书示例的"/dev/ttyUSB0"，它使用USB转串口线连接至了开发板的串口3
 ，并且连接了跳线帽。
 
-实验的硬件连接和minicom的配置请参考前面《23.3 串口通讯实验（Shell）》小节的内容，通讯时注意串口波特率要匹配。
+实验的硬件连接和minicom的配置,请参考前面小节的内容，通讯时注意串口波特率要匹配。
 
 在x86平台的编译测试过程如下：
 
-#在主机的实验代码Makefile目录下编译
-
-#默认编译x86平台的程序
-
-make
-
-#查看可用的tty设备文件
-
-ls /dev/tty\*
-
-#请根据自己主机上的输出修改设备文件参数
-
-#程序需要使用sudo运行
-
-sudo ./build_x86/tty_demo /dev/ttyUSB0
-
-----------------------------------------------------------------------
-
-#在另一个设备通过串口发送内容至Ubuntu主机
-
-#本示例中是开发板与电脑连接，此处在开发板中使用echo命令发送内容至串口3
-
-#以下命令在开发板的终端执行
-
-#以下命令在开发板的终端执行
-
-#确认串口波特率
+.. code-block:: sh
+   :linenos:
+
+   #在主机的实验代码Makefile目录下编译
+   #默认编译x86平台的程序
+   make
+   #查看可用的tty设备文件
+   ls /dev/tty*
+   #请根据自己主机上的输出修改设备文件参数
+   #程序需要使用sudo运行
+   sudo ./build_x86/tty_demo /dev/ttyUSB0
+   #在另一个设备通过串口发送内容至Ubuntu主机
+   #本示例中是开发板与电脑连接，此处在开发板中使用echo命令发送内容至串口3
+   #以下命令在开发板的终端执行
+   #以下命令在开发板的终端执行
+   #确认串口波特率
+   stty -F /dev/ttymxc2
+   #发送数据
+   echo board > /dev/ttymxc2
+   #Ubuntu主机端会收到数据并显示
+
+如下图:
+
+.. image:: media/uarttt023.jpg
+   :align: center
+   :alt: 未找到图片23|
 
-stty -F /dev/ttymxc2
-
-#发送数据
-
-echo board > /dev/ttymxc2
-
-#Ubuntu主机端会收到数据并显示
-
-|uarttt023|
-
-图 23‑22在Ubuntu主机上的运行程序与开发板端通讯
 
 ARM架构
-'''''
+'''''''''''''''
 
 对于ARM架构的程序，可使用如下步骤进行编译：
 
-#在主机的实验代码Makefile目录下编译
-
-#编译arm平台的程序
-
-make ARCH=arm
-
-编译后生成的ARM平台程序为build_arm/tty_demo，使用网络文件系统共享至开发板，程序默认使用ttymxc2通讯，也可以自行指定输入设备路径。
-
-#以下命令在Ubuntu主机执行
-
-#以下命令在Ubuntu主机执行
-
-#根据自己主机的设备配置minicom，注意波特率要匹配
-
-#关于minicom的配置请参考前面小节的内容
-
-sudo minicom /dev/ttyUSB0
-
-#配置完毕打开minicom终端
+.. code-block:: sh
+   :linenos:
+
+   #在主机的实验代码Makefile目录下编译
+   #编译arm平台的程序
+   make ARCH=arm
+   编译后生成的ARM平台程序为build_arm/tty_demo，使用网络文件系统
+   共享至开发板，程序默认使用ttymxc2通讯，也可以自行指定输入设备路径。
+   #以下命令在Ubuntu主机执行
+   #以下命令在Ubuntu主机执行
+   #根据自己主机的设备配置minicom，注意波特率要匹配
+   #关于minicom的配置请参考前面小节的内容
+   sudo minicom /dev/ttyUSB0
+   #配置完毕打开minicom终端
 
 ----------------------------------------------------------------------
 
-#以下命令在开发板上的终端执行
-
-#以下命令在开发板上的终端执行
+.. code-block:: sh
+   :linenos:
 
-#在NFS共享的工程目录路径执行
+   #以下命令在开发板上的终端执行
+   #在NFS共享的工程目录路径执行
+   #使用默认的ttymxc2设备通讯
+   ./build_arm/tty_demo
+   #程序会通过串口发送内容至主机
+   #主机使用minicom可发送内容至开发板
 
-#使用默认的ttymxc2设备通讯
+如下图:
 
-./build_arm/tty_demo
+.. image:: media/uarttt024.jpg
+   :align: center
+   :alt: 未找到图片24|
 
-#程序会通过串口发送内容至主机
 
-#主机使用minicom可发送内容至开发板
-
-|uarttt024|
-
-图 23‑23 实验现象
 
 ioctl系统调用
-~~~~~~~~~
-
-通过前面的学习我们已经掌握了配置串口参数的方法，就是对设备文件操作，前面代码中使用到的文件操作摘录如代码清单 23‑8。
-
-代码清单 23‑8 跟设备文件相关的函数操作
+~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
-1 //前面实验中对设备文件操作的函数
+通过前面的学习我们已经掌握了配置串口参数的方法，就是对设备文件操作，前面代码中使用
+到的文件操作摘录如下所示。
 
-2 fd = open(path, O_RDWR);
 
-3 write(fd, buf, strlen(buf));
 
-4 read(fd, buf, 1024);
+.. code-block:: c
+   :caption: 跟设备文件相关的函数操作
+   :linenos:  
 
-5 close(fd);
+   //前面实验中对设备文件操作的函数
+   fd = open(path, O_RDWR);
+   write(fd, buf, strlen(buf));
+   read(fd, buf, 1024);
+   close(fd);
+   tcgetattr(fd, &opt);
+   tcsetattr(fd, TCSANOW, &opt);
 
-6 tcgetattr(fd, &opt);
-
-7 tcsetattr(fd, TCSANOW, &opt);
-
-仔细分析这些操作，发现万里晴空出现了两朵乌云。open、write、read、close都是Linux的系统调用，而tcgetattr、tcsetattr则是库函数。而且按照传统的认知，文件操作大都是跟内容挂勾的，上一章节的input事件设备文件记录了上报的事件信息，而tty设备的文件却不是记录串口
-终端的配置参数，因为对文件的write操作是对外发送数据，而read则是读取接收到的数据，也就是说，“tty*”文件并没有记录串口终端的配置信息，那么tcgetattr、tcsetattr这两个函数究竟做了什么神仙操作？
+仔细分析这些操作，发现万里晴空出现了两朵乌云。open、write、read、close都是Linux的系统调
+用，而tcgetattr、tcsetattr则是库函数。而且按照传统的认知，文件操作大都是跟
+内容挂勾的，上一章节的input事件设备文件记录了上报的事件信息，而tty设备的文件却不是记录串口
+终端的配置参数，因为对文件的write操作是对外发送数据，而read则是读取接收
+到的数据，也就是说，"tty*"文件并没有记录串口终端的配置信息，那么tcgetattr、tcsetattr这两个函数究竟做了什么神仙操作？
 
 它们实际上都是对ioctl系统调用的封装。
 
 ioctl原型
-^^^^^^^
+^^^^^^^^^^^^^^^^^^^^^
 
 ioctl系统调用的功能是向设备文件发送命令，控制一些特殊操作，它的函数原型如下：
 
-#include <sys/ioctl.h>
+.. code-block:: sh
+   :linenos:
 
-int ioctl(int fd, unsigned long request, ...);
+   #include <sys/ioctl.h>
+   int ioctl(int fd, unsigned long request, ...);
 
 -  参数fd：与write、read类似，fd文件句柄指定要操作哪个文件。
 
 -  参数reques：操作请求的编码，它是跟硬件设备驱动相关的，不同驱动设备支持不同的编码，驱动程序通常会使用头文件提供可用的编码给上层用户。
 
--  参数“…”：这是一个没有定义类型的指针，它与printf函数定义中的“…”类似，不过ioctl此处只能传一个参数。部分驱动程序执行操作请求时可能需要配置参数，或者操作完成时需要返回数据，都是通过此处传的指针进行访问的。
+-  参数"…"：这是一个没有定义类型的指针，它与printf函数定义中的"…"类似，不过ioctl此处只能
+   传一个参数。部分驱动程序执行操作请求时可能需要配置参数，或者操作完成时需要返回数据，都是通过此处传的指针进行访问的。
 
 使用ioctl代替tcgetattr和tcsetattr
-^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-
-我们编写了工程文件来进行说明，本小节的工程目录：base_code/section2/tty/c_ioctl。
-
-工程示例文件见代码清单 23‑9。
-
-代码清单 23‑9 使用ioctl的示例（base_code/section2/tty/c_ioctl/source/main.c文件）
-
-1 #include <stdio.h>
-
-2 #include <stdlib.h>
-
-3 #include <unistd.h>
-
-4 #include <fcntl.h>
-
-5 #include <sys/stat.h>
-
-6 #include <sys/types.h>
-
-7 #include <termios.h>
-
-8 #include <string.h>
-
-9 #include <sys/ioctl.h>
-
-10
-
-11 //根据具体的设备修改
-
-12 const char default_path[] = "/dev/ttymxc2";
-
-13 // const char default_path[] = "/dev/ttymxc2";
-
-14
-
-15
-
-16 int main(int argc, char \*argv[])
-
-17 {
-
-18 int fd;
-
-19 int res;
-
-20 struct termios opt;
-
-21 char \*path;
-
-22 char buf[1024] = "Embedfire tty send test.\n";
-
-23
-
-24 //若无输入参数则使用默认终端设备
-
-25 if (argc > 1)
-
-26 path = argv[1];
-
-27 else
-
-28 path = (char \*)default_path;
-
-29
-
-30 //获取串口设备描述符
-
-31 printf("This is tty/usart demo.\n");
-
-32 fd = open(path, O_RDWR);
-
-33 if (fd < 0) {
-
-34 printf("Fail to Open %s device\n", path);
-
-35 return 0;
-
-36 }
-
-37 //清空串口接收缓冲区
-
-38 tcflush(fd, TCIOFLUSH);
-
-39 // 获取串口参数opt
-
-40 // tcgetattr(fd, &opt);
-
-41
-
-**42 res = ioctl(fd,TCGETS, &opt);**
-
-**43**
-
-**44 opt.c_ispeed = opt.c_cflag & (CBAUD \| CBAUDEX);**
-
-**45 opt.c_ospeed = opt.c_cflag & (CBAUD \| CBAUDEX);**
-
-46
-
-47 //输出宏定义的值，方便对比
-
-48 printf("Macro B9600 = %#o\n",B9600);
-
-49 printf("Macro B115200 = %#o\n",B115200);
-
-50 //输出读取到的值
-
-51 printf("ioctl TCGETS,opt.c_ospeed = %#o\n", opt.c_ospeed);
-
-52 printf("ioctl TCGETS,opt.c_ispeed = %#o\n", opt.c_ispeed);
-
-53 printf("ioctl TCGETS,opt.c_cflag = %#x\n", opt.c_cflag);
-
-54
-
-55 speed_t change_speed = B9600;
-
-56 if (opt.c_ospeed == B9600)
-
-57 change_speed = B115200;
-
-58
-
-59 //设置串口输出波特率
-
-60 cfsetospeed(&opt, change_speed);
-
-61 //设置串口输入波特率
-
-62 cfsetispeed(&opt, change_speed);
-
-63 //设置数据位数
-
-64 opt.c_cflag &= ~CSIZE;
-
-65 opt.c_cflag \|= CS8;
-
-66 //校验位
-
-67 opt.c_cflag &= ~PARENB;
-
-68 opt.c_iflag &= ~INPCK;
-
-69 //设置停止位
-
-70 opt.c_cflag &= ~CSTOPB;
-
-71
-
-72 //更新配置
-
-73 // tcsetattr(fd, TCSANOW, &opt);
-
-**74 res = ioctl(fd,TCSETS, &opt);**
-
-75
-
-76 //再次读取
-
-**77 res = ioctl(fd,TCGETS, &opt);**
-
-**78**
-
-**79 opt.c_ispeed = opt.c_cflag & (CBAUD \| CBAUDEX);**
-
-**80 opt.c_ospeed = opt.c_cflag & (CBAUD \| CBAUDEX);**
-
-81
-
-82 printf("ioctl TCGETS after TCSETS\n");
-
-83
-
-84 //输出读取到的值
-
-85 printf("ioctl TCGETS,opt.c_ospeed = %#o\n", opt.c_ospeed);
-
-86 printf("ioctl TCGETS,opt.c_ispeed = %#o\n", opt.c_ispeed);
-
-87 printf("ioctl TCGETS,opt.c_cflag = %#x\n", opt.c_cflag);
-
-88
-
-89 do {
-
-90 //发送字符串
-
-91 write(fd, buf, strlen(buf));
-
-92 //接收字符串
-
-93 res = read(fd, buf, 1024);
-
-94 if (res >0 ) {
-
-95 //给接收到的字符串加结束符
-
-96 buf[res] = '\0';
-
-97 printf("Receive res = %d bytes data: %s\n",res, buf);
-
-98 }
-
-99 } while (res >= 0);
-
-100
-
-101 printf("read error,res = %d",res);
-
-102
-
-103 close(fd);
-
-104 return 0;
-
-105 }
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+我们编写了工程文件来进行说明，本小节的工程目录：base_code/linux_app/tty/c_ioctl。
+
+工程示例文件如下所示。
+
+
+
+.. code-block:: c
+   :caption: 使用ioctl的示例（base_code/linux_app/tty/c_ioctl/source/main.c文件）
+   :linenos:  
+
+   #include <stdio.h>
+   #include <stdlib.h>
+   #include <unistd.h>
+   #include <fcntl.h>
+   #include <sys/stat.h>
+   #include <sys/types.h>
+   #include <termios.h>
+   #include <string.h>
+   #include <sys/ioctl.h>
+
+   //根据具体的设备修改
+   const char default_path[] = "/dev/ttymxc2";
+   // const char default_path[] = "/dev/ttymxc2";
+
+
+   int main(int argc, char *argv[])
+   {
+      int fd;
+      int res;
+      struct termios opt;
+      char *path;
+      char buf[1024] = "Embedfire tty send test.\n";
+
+      //若无输入参数则使用默认终端设备
+      if(argc > 1)
+         path = argv[1];
+      else
+         path = (char *)default_path;
+
+      //获取串口设备描述符
+      printf("This is tty/usart demo.\n");
+      fd = open(path, O_RDWR);
+      if(fd < 0){
+         printf("Fail to Open %s device\n", path);
+         return 0;
+      }
+      //清空串口接收缓冲区
+      tcflush(fd, TCIOFLUSH);
+      // 获取串口参数opt
+      // tcgetattr(fd, &opt);
+
+      res = ioctl(fd,TCGETS, &opt);
+
+      opt.c_ispeed = opt.c_cflag & (CBAUD | CBAUDEX);
+      opt.c_ospeed = opt.c_cflag & (CBAUD | CBAUDEX);
+
+      //输出宏定义的值，方便对比
+      printf("Macro B9600 = %#o\n",B9600);
+      printf("Macro B115200 = %#o\n",B115200);
+      //输出读取到的值
+      printf("ioctl TCGETS,opt.c_ospeed = %#o\n", opt.c_ospeed);
+      printf("ioctl TCGETS,opt.c_ispeed = %#o\n", opt.c_ispeed);
+      printf("ioctl TCGETS,opt.c_cflag = %#x\n", opt.c_cflag);
+
+      speed_t change_speed = B9600;
+      if(opt.c_ospeed == B9600)
+         change_speed = B115200;
+
+      //设置串口输出波特率
+      cfsetospeed(&opt, change_speed);
+      //设置串口输入波特率
+      cfsetispeed(&opt, change_speed);
+      //设置数据位数
+      opt.c_cflag &= ~CSIZE;
+      opt.c_cflag |= CS8;
+      //校验位
+      opt.c_cflag &= ~PARENB;
+      opt.c_iflag &= ~INPCK;
+      //设置停止位
+      opt.c_cflag &= ~CSTOPB;
+
+      //更新配置
+      // tcsetattr(fd, TCSANOW, &opt);   
+      res = ioctl(fd,TCSETS, &opt);
+
+      //再次读取
+      res = ioctl(fd,TCGETS, &opt);
+
+      opt.c_ispeed = opt.c_cflag & (CBAUD | CBAUDEX);
+      opt.c_ospeed = opt.c_cflag & (CBAUD | CBAUDEX);
+
+      printf("ioctl TCGETS after TCSETS\n");
+
+      //输出读取到的值
+      printf("ioctl TCGETS,opt.c_ospeed = %#o\n", opt.c_ospeed);
+      printf("ioctl TCGETS,opt.c_ispeed = %#o\n", opt.c_ispeed);
+      printf("ioctl TCGETS,opt.c_cflag = %#x\n", opt.c_cflag);
+
+      do{
+         //发送字符串
+         write(fd, buf, strlen(buf));
+         //接收字符串
+         res = read(fd, buf, 1024);		
+         if(res >0 ){
+            //给接收到的字符串加结束符
+            buf[res] = '\0';
+            printf("Receive res = %d bytes data: %s\n",res, buf);
+         }
+      }while(res >= 0);
+
+      printf("read error,res = %d",res);
+
+      close(fd);
+      return 0;
+   }
 
 本实验代码就是直接通过ioctl系统调用代替了tcgetattr和tcsetattr这两个库函数。
 
--  在示例代码中的第42行和77行，使用ioctl向设备文件发送了“TCGETS”请求，在tty设备的驱动层，会根据这个请求返回配置参数，并通过传入的&opt指针传出。
+-  在示例代码中的第41行和76行，使用ioctl向设备文件发送了"TCGETS"请求，在tty设备
+   的驱动层，会根据这个请求返回配置参数，并通过传入的&opt指针传出。
 
--  类似地，示例代码中的第74行，使用ioctl向设备文件发送了“TCSETS”请求，在tty设备的驱动层，会根据这个请求设置由指针&opt传入的配置参数，修改设备的属性。
+-  类似地，示例代码中的第73行，使用ioctl向设备文件发送了"TCSETS"请求，在tty设备
+   的驱动层，会根据这个请求设置由指针&opt传入的配置参数，修改设备的属性。
 
--  特别地，由于使用ioctl获取配置参数时，波特率的值不会直接写入到termios结构体的c_ispeed和c_ospeed成员，需要通过c_cflag的值运算得出，所以第44、45行和79、80行加入了运算转换，运算出来的值是B9600或B115200之类的值。如果不进行这样的运算操作，c_isp
-  eed和c_ospeed得到的值可能是不对的。
+-  特别地，由于使用ioctl获取配置参数时，波特率的值不会直接写入到termios结构体
+   的c_ispeed和c_ospeed成员，需要通过c_cflag的值运算得出，所以第43、44行和78、79行加入了运算转
+   换，运算出来的值是B9600或B115200之类的值。如果不进行这样的运算操作，c_ispeed和c_ospeed得到的值可能是不对的。
 
 -  代码的其它部分是输出的一些调试信息，方便在实验时验证获取到的信息是否正确。
 
 关于ioctl的TCGETS和TCSETS参数，可以在man手册中查看，使用如下命令：
 
-man ioctl_tty
+.. code-block:: sh
+   :linenos:
 
-|uarttt025|
+   man ioctl_tty
 
-图 23‑24 man ioctl_tty的说明
+如下图:
 
-ioctl系统调用应用非常广泛，因为并不是所有设备都仅有读写操作，例如控制CD-ROM的弹出和收回，特殊设备的机械操作，又或者我们自己编写LED驱动程序也可以对上层提供指令实现花式点灯，在以后编写驱动程序时，我们再来学习与ioctl系统调用相关的接口。
+.. image:: media/uarttt025.png
+   :align: center
+   :alt: 未找到图片25|
+
+
+
+ioctl系统调用应用非常广泛，因为并不是所有设备都仅有读写操作，例如控制CD-ROM的
+弹出和收回，特殊设备的机械操作，又或者我们自己编写LED驱动程序也可以对
+上层提供指令
+实现花式点灯，在以后编写驱动程序时，我们再来学习与ioctl系统调用相关的接口。
 
 .. _编译及测试-1:
 
 编译及测试
-^^^^^
+^^^^^^^^^^^^^^^
 
 本实验使用的Makefile相对于前面的章节仅修改了最终的可执行文件名为tty_demo。
 
 .. _x86架构-1:
 
 x86架构
-'''''
+'''''''''''''''
 
-本实验主要是为了验证ioctl是否能获取或设置串口终端设备的参数，如果想进行通讯测试请参照上一小节的说明，操作是类似的，匹配波特率即可。
+本实验主要是为了验证ioctl是否能获取或设置串口终端设备的参数，如果想进行通
+讯测试请参照上一小节的说明，操作是类似的，匹配波特率即可。
 
 在x86平台的编译测试过程如下：
 
-#在主机的实验代码Makefile目录下编译
-
-#默认编译x86平台的程序
-
-make
-
-#查看可用的tty设备文件
-
-ls /dev/tty\*
+.. code-block:: sh
+   :linenos:
 
-#请根据自己主机上的输出修改设备文件参数
+   #在主机的实验代码Makefile目录下编译
+   #默认编译x86平台的程序
+   make
+   #查看可用的tty设备文件
+   ls /dev/tty*
+   #请根据自己主机上的输出修改设备文件参数
+   #可以使用stty命令查看当前设备参数
+   sudo stty -F /dev/ttyUSB0
+   #程序需要使用sudo运行
+   sudo ./build_x86/tty_demo /dev/ttyUSB0
+   #程序运行时会输出获取到的波特率及c_cflag配置，并把波特率设置为B9600或B115200
 
-#可以使用stty命令查看当前设备参数
+如下图:
 
-sudo stty -F /dev/ttyUSB0
+.. image:: media/uarttt026.png
+   :align: center
+   :alt: 未找到图片26|
 
-#程序需要使用sudo运行
-
-sudo ./build_x86/tty_demo /dev/ttyUSB0
-
-#程序运行时会输出获取到的波特率及c_cflag配置，并把波特率设置为B9600或B115200
-
-|uarttt026|
-
-图 23‑25在Ubuntu主机上的运行程序
 
 .. _arm架构-1:
 
 ARM架构
-'''''
+'''''''''''''''
 
 对于ARM架构的程序，可使用如下步骤进行编译：
 
-#在主机的实验代码Makefile目录下编译
-
-#编译arm平台的程序
-
-make ARCH=arm
-
-编译后生成的ARM平台程序为build_arm/tty_demo，使用网络文件系统共享至开发板，程序默认使用ttymxc2设备，也可以自行指定输入设备路径。
+.. code-block:: sh
+   :linenos:
 
-#以下命令在开发板上的终端执行
+   #在主机的实验代码Makefile目录下编译
+   #编译arm平台的程序
+   make ARCH=arm
 
-#以下命令在开发板上的终端执行
+编译后生成的ARM平台程序为build_arm/tty_demo，使用网络文件系
+统共享至开发板，程序默认使用ttymxc2设备，也可以自行指定输入设备路径。
 
-#请根据自己主机上的输出修改设备文件参数
+.. code-block:: sh
+   :linenos:
 
-#可以使用stty命令查看当前设备参数
+   #以下命令在开发板上的终端执行
+   #以下命令在开发板上的终端执行
+   
+   #请根据自己主机上的输出修改设备文件参数
+   
+   #可以使用stty命令查看当前设备参数
+   
+   stty -F /dev/ ttymxc2
+   
+   #程序需要使用sudo运行
+   
+   ./build_arm/tty_demo /dev/ttymxc2
+   
+   #程序运行时会输出获取到的波特率及c_cflag配置，并把波特率设置为B9600或B115200
 
-stty -F /dev/ ttymxc2
+如下图:
 
-#程序需要使用sudo运行
+.. image:: media/uarttt027.png
+   :align: center
+   :alt: 未找到图片27|
 
-./build_arm/tty_demo /dev/ttymxc2
 
-#程序运行时会输出获取到的波特率及c_cflag配置，并把波特率设置为B9600或B115200
-
-|uarttt027|
-
-图 23‑26 实验现象
 
 查看glibc源码
-~~~~~~~~~
-
-如果你问我，是怎么知道这些的tcgetattr.c和tcsetattr.c是通过ioctl系统调用实现的，又是如何知道c_ispeed和c_ospeed需要通过c_cflag成员运算得出的？答案是查看源码，我们一直在强调Linux是开放的，就看我们如何挖掘这些宝藏了。
-
-既然它们是库函数，那我们就到glibc的源码中找找，glibc的源码可以到其官网下载：\ http://www.gnu.org/software/libc/\ ，下载到源码后，使用VS Code编辑器的搜索功能，就可以搜到相关的内容，如图 23‑27。
-
-|uarttt028|
-
-图 23‑27 在glibc源码目录下搜索tcgetattr
-
-这两个函数的定义位于glibc源码的如下目录： glibc/sysdeps/unix/sysv/linux/，该目录中的tcgetattr.c和tcsetattr.c文件分别定义了这两个函数。这两个文件我们也拷贝了一份到工程的如下目录，方便查看：
-base_code/section2/tty/c_ioctl/glibc_file。
-
-tcgetattr.c文件的内容见代码清单 23‑10。
-
-代码清单 23‑10 tcgetattr的glibc源码（glibc/sysdeps/unix/sysv/linux/tcgetattr.c文件）
-
-1 int
-
-2 \__tcgetattr (int fd, struct termios \*termios_p)
-
-3 {
-
-4 struct \__kernel_termios k_termios;
-
-5 int retval;
-
-6
-
-**7 retval = INLINE_SYSCALL (ioctl, 3, fd, TCGETS, &k_termios);**
-
-8
-
-9 if (__glibc_likely (retval == 0)) {
-
-10 termios_p->c_iflag = k_termios.c_iflag;
-
-11 termios_p->c_oflag = k_termios.c_oflag;
-
-12 termios_p->c_cflag = k_termios.c_cflag;
-
-13 termios_p->c_lflag = k_termios.c_lflag;
-
-14 termios_p->c_line = k_termios.c_line;
-
-15 #if \_HAVE_STRUCT_TERMIOS_C_ISPEED
-
-16 # if \_HAVE_C_ISPEED
-
-17 termios_p->c_ispeed = k_termios.c_ispeed;
-
-18 # else
-
-**19 termios_p->c_ispeed = k_termios.c_cflag & (CBAUD \| CBAUDEX);**
-
-20 # endif
+~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+如果你问我，是怎么知道这些的tcgetattr.c和tcsetattr.c是通过ioctl系统调
+用实现的，又是如何知道c_ispeed和c_ospeed需要通过c_cflag成员运算得出的？答案
+是查看源码，我们一直在强调Linux是开放的，就看我们如何挖掘这些宝藏了。
+
+既然它们是库函数，那我们就到glibc的源码中找找，glibc的源码可以到其
+官网下载：\ http://www.gnu.org/software/libc/\ ，下载到源码后，使用VS Code编辑
+器的搜索功能，就可以搜到相关的内容，如下图所示。
+
+.. image:: media/uarttt028.png
+   :align: center
+   :alt: 未找到图片28|
+
+
+
+这两个函数的定义位于glibc源码的如下目录： glibc/sysdeps/unix/sysv/linux/，该
+目录中的tcgetattr.c和tcsetattr.c文件分别定义了这两个函数。这两个文件
+我们也拷贝了一份到工程的如下目录，方便查看：
+base_code/linux_app/tty/c_ioctl/glibc_file。
+
+tcgetattr.c文件的内容如下。
+
+
+
+.. code-block:: c
+   :caption: tcgetattr的glibc源码（glibc/sysdeps/unix/sysv/linux/tcgetattr.c文件）
+   :linenos:  
+
+   int
+   __tcsetattr (int fd, int optional_actions, const struct termios *termios_p)
+   {
+   struct __kernel_termios k_termios;
+   unsigned long int cmd;
+
+   switch (optional_actions)
+      {
+      case TCSANOW:
+         cmd = TCSETS;
+         break;
+      case TCSADRAIN:
+         cmd = TCSETSW;
+         break;
+      case TCSAFLUSH:
+         cmd = TCSETSF;
+         break;
+      default:
+         return INLINE_SYSCALL_ERROR_RETURN_VALUE (EINVAL);
+      }
+
+   k_termios.c_iflag = termios_p->c_iflag & ~IBAUD0;
+   k_termios.c_oflag = termios_p->c_oflag;
+   k_termios.c_cflag = termios_p->c_cflag;
+   k_termios.c_lflag = termios_p->c_lflag;
+   k_termios.c_line = termios_p->c_line;
+   #if _HAVE_C_ISPEED && _HAVE_STRUCT_TERMIOS_C_ISPEED
+   k_termios.c_ispeed = termios_p->c_ispeed;
+   #endif
+   #if _HAVE_C_OSPEED && _HAVE_STRUCT_TERMIOS_C_OSPEED
+   k_termios.c_ospeed = termios_p->c_ospeed;
+   #endif
+   memcpy (&k_termios.c_cc[0], &termios_p->c_cc[0],
+      __KERNEL_NCCS * sizeof (cc_t));
+
+   return INLINE_SYSCALL (ioctl, 3, fd, cmd, &k_termios);
+   }
+   
+   libc_hidden_def (__tcgetattr)
+   weak_alias (__tcgetattr, tcgetattr)
 
-21 #endif
-
-22 #if \_HAVE_STRUCT_TERMIOS_C_OSPEED
-
-23 # if \_HAVE_C_OSPEED
-
-24 termios_p->c_ospeed = k_termios.c_ospeed;
-
-25 # else
-
-**26 termios_p->c_ospeed = k_termios.c_cflag & (CBAUD \| CBAUDEX);**
-
-27 # endif
-
-28 #endif
-
-29 if (sizeof (cc_t) == 1 \|\| \_POSIX_VDISABLE == 0
-
-30 \|\| (unsigned char) \_POSIX_VDISABLE == (unsigned char) -1)
-
-31 memset (__mempcpy (&termios_p->c_cc[0], &k_termios.c_cc[0],
-
-32 \__KERNEL_NCCS \* sizeof (cc_t)),
-
-33 \_POSIX_VDISABLE, (NCCS - \__KERNEL_NCCS) \* sizeof (cc_t));
-
-34 else {
-
-35 memcpy (&termios_p->c_cc[0], &k_termios.c_cc[0],
-
-36 \__KERNEL_NCCS \* sizeof (cc_t));
-
-37
-
-38 for (size_t cnt = \__KERNEL_NCCS; cnt < NCCS; ++cnt)
-
-39 termios_p->c_cc[cnt] = \_POSIX_VDISABLE;
-
-40 }
-
-41 }
-
-42
-
-43 return retval;
-
-44 }
-
-45
+代码看起来有点复杂，但刚接触的时候我们不需要完全弄清楚它的所有细节：
 
-46 libc_hidden_def (__tcgetattr)
+-  第7行：它使用ioctl发送了TCGETS请求，并传入了&k_termios指针记录参数。
 
-47 weak_alias (__tcgetattr, tcgetattr)
+-  第10行开始，都是把读取到的k_termios内容复制到__tcgetattr传入的termios_p中指针指向的
+   变量中，而c_ispeed和c_ospeed就是在第19、26行通过c_cflag运算得到的，所以我们使用tcgetattr库函
+   数的时候，不需要自己再运算赋值，而自己通过ioctl读取
+   配置时则要加上运算转换。
 
-代码看起来有点复杂，但刚接触的时候我们不需要完全弄清楚它的所有细节：
+glibc源码中使用了很多特别的宏或封装，如INLINE_SYSCALL、__glibc_likely、weak_alias等，感兴趣
+的读者可以查阅glibc官方的相关文档学习。
 
--  第7行：它使用ioctl发送了TCGETS请求，并传入了&k_termios指针记录参数。
 
--  第10行开始，都是把读取到的k_termios内容复制到__tcgetattr传入的termios_p中指针指向的变量中，而c_ispeed和c_ospeed就是在第19、26行通过c_cflag运算得到的，所以我们使用tcgetattr库函数的时候，不需要自己再运算赋值，而自己通过ioctl读取
-  配置时则要加上运算转换。
 
-glibc源码中使用了很多特别的宏或封装，如INLINE_SYSCALL、__glibc_likely、weak_alias等，感兴趣的读者可以查阅glibc官方的相关文档学习。
 
 .. |uarttt002| image:: media/uarttt002.jpg
    :width: 4.07996in
diff --git a/documentation/linux_basis/board_startup.rst b/documentation/linux_basis/board_startup.rst
index fe45aa5520113e298c40cf7b2dbf546377c66cbf..08e68995d232e02d6495ff9a0f8d85be9999569f 100644
--- a/documentation/linux_basis/board_startup.rst
+++ b/documentation/linux_basis/board_startup.rst
@@ -1,22 +1,24 @@
 .. vim: syntax=rst
 
 让开发板跑起来
--------
+------------------------------------------
 
 本章主要讲解如何使用配套的开发板，让开发板的系统运行起来！
 
 了解开发板的启动方式
-~~~~~~~~~~
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
 i.MX系列芯片支持多种启动方式，在我们配套的开发板上主要使用其中的Nand-FLASH、eMMC、SD卡及USB启动方式。
 
-|boards002|
 
-图 11‑1 boot拨码开关（请根据具体启动方式进行配置）
+.. image:: media/boards002.png
+   :align: center
+   :alt: 未找到图片
 
-拨码开关的一侧会写着ON字样，把拨码调至该侧表示对应的选项为高电平1，调至另一侧为0，不同启动方式的见表 11‑1，也可以直接查看开发板上的丝印说明（一般印在板子背面），表中的X表示任意电平均可。
+拨码开关的一侧会写着ON字样，把拨码调至该侧表示对应的选项为高电平1，调至另一侧为0，不
+同启动方式的见下表，也可以直接查看开发板上的丝印说明（一般印在板子背面），表中的X表示任意电平均可。
 
-表 11‑1 拨码开关配置的启动方式
+下表为拨码开关配置的启动方式:
 
 ==== ====== ========== ==== == ===
 编号 名称   Nand FLASH eMMC SD USB
@@ -31,12 +33,13 @@ i.MX系列芯片支持多种启动方式，在我们配套的开发板上主要
 8    CFG2-5 0          0    1  X
 ==== ====== ========== ==== == ===
 
-开发板上电后会根据拨码开关的状态从不同的存储器加载代码运行，故上电前需要根据自己开发板使用的存储器进行配置，如Nand FLASH核心板就配置为0-1-1-0-0-1-0-0，其它依次类推。
+开发板上电后会根据拨码开关的状态从不同的存储器加载代码运行，故上电前需要根据自
+己开发板使用的存储器进行配置，如Nand FLASH核心板就配置为0-1-1-0-0-1-0-0，其它依次类推。
 
 其中的USB启动模式主要用来配合NXP官方的mfgtool工具烧录镜像。
 
 硬件准备
-~~~~
+~~~~~~~~~~~~~~~~~~~~~~~~
 
 要进行本章的实验操作，需要准备如下硬件：
 
@@ -51,7 +54,7 @@ i.MX系列芯片支持多种启动方式，在我们配套的开发板上主要
 -  配套的屏幕（可选）
 
 启动步骤
-~~~~
+~~~~~~~~~~~~~~~~~~~~~~~~
 
 开发板出厂时默认都烧录了Linux系统，确认设置了正确的boot启动方式，只要上电就会自动运行。
 
@@ -71,58 +74,101 @@ i.MX系列芯片支持多种启动方式，在我们配套的开发板上主要
 
 (7) 对于不带屏幕的开发板，可以通过串口终端控制开发板。关于串口终端的使用请参考下一小节的内容。
 
-设置Putty连接终端
-~~~~~~~~~~~
+设置MobaXterm连接终端
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
 开发板支持使用串口终端进行控制，并且为方便使用，开发板上的串口通过CH340转换成USB通讯，使得开发板与电脑连接时直接用USB线即可。使用时需要在电脑先安装CH340芯片的USB转串口驱动。
 
-连接串口终端时可以使用普通的串口调试工具收发字符串，不过这样控制起来非常不方便，此处我们推荐使用Putty终端软件。如果使用的不是Putty软件，以下连接开发板串口终端的操作步骤也大体相似，可以参考它来操作。
+连接串口终端时可以使用普通的串口调试工具收发字符串，不过这样控制起来非常不方便，此处我们推荐使用MobaXterm终端软件。如果使用的不是MobaXterm软件，以下连接开发板串口终端的操作步骤也大体相似，可以参考它来操作。
 
 以下操作步骤在Windows系统的开发主机进行：
 
-(1) 安装CH340芯片的USB转串口驱动，该驱动安装程序可在开发板配套的资料里找到。
+(1) 安装CH340芯片的USB转串口驱动，
+该驱动安装程序可在开发板配套的资料里找到。
 
-(2) 使用Mini USB线连接电脑与开发板，注意在开发板端要接入到板子上的“USB转串口”接口，并通过DC电源供电，不能只使用USB线供电。
+(2) 使用Mini USB线连接电脑与开发板，注意在开发板端要接入到板子上的"USB转串口"接口，
+并通过DC电源供电，不能只使用USB线供电。
 
-(3) 连接并供电后，在“我的电脑”设备管理器的“端口”设备下会新增一个“USB-SERIAL CH340”设备，请查看自己电脑上该COM口的编号，这在不同的电脑上编号是不同的，见图 11‑2。
+(3) 连接并供电后，在"我的电脑"设备管理器的"端口"设备下会新增一个"USB-SERIAL CH340"设备，请查看自
+己电脑上该COM口的编号，这在不同的电脑上编号是不同的，如下图所示。
 
-|boards003|
+.. image:: media/boards003.jpg
+   :align: center
+   :alt: 未找到图片
 
-图 11‑2 查看COM口
 
-(4) 安装并打开Putty软件，新建会话，在连接的协议处选择使用“Serial”，表示通过串口连接终端，把Putty的串口的通讯速率配置成开发板默认值，即“115200”，本例子使用的端口号为“COM4”，注意该端口号要根据自己的实验环境进行选择，即在步骤（3）中查看的端口号。具体见图 11‑3。
+(4) 安装MobaXterm软件：https://mobaxterm.mobatek.net/download.html，
+在软件官网选择免费版安装即可。如下图:
 
-|boards004|
+.. image:: media/boards015.png
+   :align: center
+   :alt: 未找到图片
 
-图 11‑3 使用SERIAL协议连接终端
 
-登录到终端
-~~~~~
+(5) 打开MobaXterm软件，
+软件界面如下图所示:
+
+.. image:: media/boards011.png
+   :align: center
+   :alt: 未找到图片
+
+**注意:第一次安装时，左边会话的标签栏是没有任何session的。**
+
+(6) 点击菜单栏 「sessions」 --> 「new session」，即可弹出 「session setting」 对话框。
+从会话对话框中可以看到，MobaXterm支持非常多的连接方式，我们在本章节中，主要是关注串口连接方式，
+如下图所示:
+
+.. image:: media/boards012.png
+   :align: center
+   :alt: 未找到图片
+
+(7) 把MobaXterm的串口的通讯速率配置成开发板默认值，即”115200”，
+本例子使用的 端口号为”COM8”，注意该端口号要根据自己的实验环境进行选择，
+即在步骤（3）中查看的端口号。如下图:
+
+.. image:: media/boards013.png
+   :align: center
+   :alt: 未找到图片
+
+(8) 选好串口号及波特率后，点击OK就完成连接了。左边标签栏会记录这次的session，以后可以直接从标签栏打开会话窗口。
+如下图:
 
-设置好连接软件后，打开终端软件的连接即可连接至开发板的串口终端。
+.. image:: media/boards014.png
+   :align: center
+   :alt: 未找到图片
 
-(1) 如果是在开发板开机前就建立了串口终端连接，那么在开机时会看到开发板在启动时的信息输出，见图 11‑4。
+登录到终端
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
-|boards005|
+(1) 如果是在开发板开机前就建立了串口终端连接，
+那么在开机时会看到开发板在启动时的信息输出，见下图。
 
-图 11‑4 开发板启动时的终端输出（部分）
+.. image:: media/boards005.png
+   :align: center
+   :alt: 未找到图片
 
-(2) 如果是在开发板开机后才建立的连接，开发板没有输出，这时直接按几下回车即可，见图 11‑5。
 
-|boards006|
+(2) 如果是在开发板开机后才建立的连接，开发板没有输出，
+这时直接按几下回车即可，见下图。
 
-图 11‑5 按回车后终端的输出
+.. image:: media/boards006.png
+   :align: center
+   :alt: 未找到图片
 
-(3) 无论是以上哪种情况，开发板的启动流程执行完毕时，只要按回车后终端都会提示login，此时终端在等待用户的输入，它需要知道我们希望以哪个用户名登录终端。我们的开发板默认用户为：root，不带密码。所以在该提示界面中输入root并回车即可，见图 11‑6。
+(3) 无论是以上哪种情况，开发板的启动流程执行完毕时，只要按回车后终端都会提示login，此时终
+端在等待用户的输入，它需要知道我们希望以哪个用户名登录终端。我们的开发板默认
+用户为：debian，密码：temppwd。所以在提示界面中输入用户密码并回车登录即可，见下图。
 
-|boards007|
+.. image:: media/boards007.png
+   :align: center
+   :alt: 未找到图片
 
-图 11‑6 在login提示中输入root并回车
 
-(4) 至此，我们就成功通过串口登录到开发板的终端了，接下来我们就可以使用各种命令来控制开发板。
+(4) 至此，我们就成功通过串口登录到开发板的终端了，
+接下来我们就可以使用各种命令来控制开发板。
 
 连接网络
-~~~~
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
 在前面的基础上，需要的额外硬件准备：
 
@@ -133,45 +179,101 @@ i.MX系列芯片支持多种启动方式，在我们配套的开发板上主要
 使用网线通过开发板的任意一个以太网接口与路由器连接起来，即可把开发板连接至网络。
 
 连接外网测试
-^^^^^^
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 
 若开发板连接的路由器支持连接到公网，直接在终端输入如下命令即可进行连接测试：
 
-#在开发板的终端执行以下命令
 
-ping www.firebbs.cn
 
-|boards008|
+.. code-block:: sh
+   :linenos:
+
+   #在开发板的终端执行以下命令
+   ping www.firebbs.cn
+
+
+.. image:: media/boards008.png
+   :align: center
+   :alt: 未找到图片
 
-图 11‑7 ping外网测试
 
-出现类似图 11‑7的输出表示网络连接成功，使用“Ctrl + C”可退出命令。
+
+
+出现类似上图的输出表示网络连接成功，使用"Ctrl + C"可退出命令。
 
 ping路由测试
-^^^^^^^^
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 
-若连接的路由不支持连接到公网，可以直接ping路由的IP地址，如本例子中的路由IP地址为192.168.0.1。请把以下命令中的IP地址换成自己实验环境的路由IP：
+若连接的路由不支持连接到公网，可以直接ping路由的IP地址，如本例子中的路由IP地址为192.168.0.1。请把以
+下命令中的IP地址换成自己实验环境的路由IP：
 
-ping 192.168.0.1
+.. code-block:: sh
+   :linenos:
+
+   ping 192.168.0.1
 
 查看开发板的IP地址
-^^^^^^^^^^
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+如果使用无法ping通，请使用ifconfig命令查看开发板的IP地址，见下图。
+
+.. image:: media/boards009.png
+   :align: center
+   :alt: 未找到图片
+
+
+
+
+在上图中开发板使用ifconfig命令可查看到开发板eth0网口的IP地址，为192.168.0.177。若
+使用ifconfig命令查看不到IP地址，请检查网络连接，或尝试使用以下命令申请IP：
+
+.. code-block:: sh
+   :linenos:
+
+   #eth1表示第一路以太网口，eth2表示第二路以太网口
+   sudo udhcpc  -b  -i  eth1  
+
+若命令执行正常，会出现图 11‑9中的输出，并且再次输入ifconfig命令会查看到eth1具有正常的IP地址。
+
+.. image:: media/boards010.png
+   :align: center
+   :alt: 未找到图片
+
+
+修改启动脚本
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+系统在启动时会在显示屏中绘制进度条，这就是 ``/opt/scripts/boot/psplash.sh`` 启动脚本要干的事情，当成功加载完系统后，接着会执行 ``/opt/scripts/boot/psplash_quit.sh`` 启动脚本，那么可以在这个启动脚本中处理一些自己的事情。
+
+比如野火在绘制完进度条后启动qt
+app，在 ``/opt/scripts/boot/psplash_quit.sh`` 启动脚本就是这样子写的：
+
+.. code:: bash
+
+    if [ -f /home/debian/qt-app-static/run.sh ] ; then
+        sudo /home/debian/qt-app-static/run.sh &
+    else
+        sudo /home/debian/qt-app/run.sh &
+    fi
+
+如果你不想启动qt
+app，则可以把上述代码注释掉即可，如果你想在启动后有一个固定的IP地址，那么也可以这样子做， ``xxx`` 改为你自己需要设置的IP地址即可：
 
-如果使用无法ping通，请使用ifconfig命令查看开发板的IP地址，见图 11‑8。
+.. code:: bash
 
-|boards009|
+    sudo ifconfig eth1 down
+    sudo ifconfig eth1 192.168.xxx.xxx up
 
-图 11‑8 查看开发板IP地址
+如果你想执行其他操作，就在这里修改即可，此处仅是做个提示。
 
-在图 11‑8中开发板使用ifconfig命令可查看到开发板eth0网口的IP地址，为192.168.0.177。若使用ifconfig命令查看不到IP地址，请检查网络连接，或尝试使用以下命令申请IP：
+那么如果我不想等待系统加载完成就运行我的脚本，如何做到呢，其实还是只需要修改 ``/opt/scripts/boot/psplash.sh`` 启动脚本即可，在这个启动脚本中有执行绘制进度条的操作，在改脚本的最后一行，具体如下:
 
-udhcpc  -b  -i  eth0
+.. code:: bash
 
-若命令执行正常，会出现图 11‑9中的输出，并且再次输入ifconfig命令会查看到eth0具有正常的IP地址。
+    /usr/bin/psplash
 
-|boards010|
+那么你也可以在这个启动脚本中添加你需要执行的脚本即可， **请注意：需要脚本所在的绝对路径** 。
 
-图 11‑9 开启udhcpc申请IP
 
 .. |boards002| image:: media/boards002.png
    :width: 3.98415in
diff --git a/documentation/linux_basis/command_line.rst b/documentation/linux_basis/command_line.rst
index e01b925d65b53caf8991204081d160f60b6db6ee..aac4b6b17d4671b68d8e05d5368471bd838bcc32 100644
--- a/documentation/linux_basis/command_line.rst
+++ b/documentation/linux_basis/command_line.rst
@@ -3,18 +3,32 @@
 使用Linux命令行
 ----------
 
-使用桌面Ubuntu的一大好处是它的对用户很友好，日常的基础应用都可以通过它的图形界面完成，但界面做得再完善，还是有很多操作无法通过界面完成的，因为绝大部分程序本身根本就不提供界面，或者界面只提供一小部分常用操作。但是几乎所有的程序都能通过命令行来调用运行，并且通过命令行提供丰富的操作选项。尤其是做
+使用桌面Ubuntu的一大好处是它的对用户很友好，日常的基础应用都可以通过它
+的图形界面完成，但界面做得再完善，还是有很多操作无法通过界面完成的，因为
+绝大部分程序本身根本就不提供界面，或者界面只提供一小部分常用操作。但是几乎所有的程
+序都能通过命令行来调用运行，并且通过命令行提供丰富的操作选项。尤其是做
 开发时，不要总想着有IDE，有当然好，但我们要接受只能使用命令行的处境，实际上，用多了就习惯了。
 
-Linus Torvalds（林纳斯）在其自传中提到，他在编写Linux操作系统内核的时候，首要目标就是让Linux系统能兼容正常运行Unix下的Shell程序。因为Shell是命令行解释器，它的Linux系统若能兼容Shell，那么大部分类Unix的程序也很容易做到兼容了。
+Linus Torvalds（林纳斯）在其自传中提到，他在编写Linux操作系统内核的
+时候，首要目标就是让Linux系统能兼容正常运行Unix下的Shell程序。因为Shell是命令
+行解释器，它的Linux系统若能兼容Shell，那么大部分类Unix的程序也很容易做到兼容了。
 
-在早期的Unix系统与用户就是通过Shell进行交互的，如图 7‑1，Shell对外接受用户输入的命令，对内通过系统调用传递给内核，内核执行操作后把输出通过Shell呈现给用户，也就是说，Shell就是一个中间人。而Shell的英文原意“壳”，也是为了把它与内核区分开来。
+在早期的Unix系统与用户就是通过Shell进行交互的，如下图所示，Shell对外接
+受用户输入的命令，对内通过系统调用传递给内核，内核执
+行操作后把输出通过Shell呈现给用户，也就是说，Shell就是
+一个中间人。而Shell的英文原意"壳"，也是为了把它与内核区分开来。
 
-|command002|
+.. image:: media/comman002.png
+   :align: center
+   :alt: 未找到图片
 
-图 7‑1 Shell与内核
 
-在平时的交流中，有时我们会说打开Shell、终端（Terminal）或控制台（Console），严格来说它们实际上不是同样的东西，但只要明白，当我们说打开Shell、终端或控制台的时候，通常就是为了使用命令行控制系统。它们的严格区分如下，了解下即可：
+
+
+
+在平时的交流中，有时我们会说打开Shell、终端（Terminal）或控制台（Console），严格来
+说它们实际上不是同样的东西，但只要明白，当我们说打开Shell、终端或
+控制台的时候，通常就是为了使用命令行控制系统。它们的严格区分如下，了解下即可：
 
 -  Shell：指命令行解释器，常见的解释器有bash，sh，在Ubuntu系统默认用的是bash解释器，所以有时说bash也是指命令行。
 
@@ -23,402 +37,515 @@ Linus Torvalds（林纳斯）在其自传中提到，他在编写Linux操作系
 -  控制台（Console）：特指某些终端，通常是指它的物理形态，如带键盘和显示器的物理设备。
 
 打开终端
-~~~~
+~~~~~~~~~~~~~~~~~~~~
+
+实际上，在Windows也有终端，下图是类似于Windows操作系统的cmd程序，而在Ubuntu的命令行终端如下图所示。
+
+
+.. image:: media/comman003.jpg
+   :align: center
+   :alt: 未找到图片
+
 
-实际上，在Windows也有终端，如图 7‑2是类似于Windows操作系统的cmd程序，而在Ubuntu的命令行终端如图 7‑3所示。
 
-|comman003|
+.. image:: media/comman004.jpg
+   :align: center
+   :alt: 未找到图片
+
 
-图 7‑2 cmd窗口（Windows）
 
-|comman004|
 
-图 7‑3 terminal窗口（Ubuntu）
 
    在Ubuntu下，可通过如下方式启动终端：
 
 -  第一种方式是最简便最快捷的，通过快捷键Ctrl+Alt+T，可以快速打开一个命令行终端；
 
--  第二种方式是搜索功能，如图 7‑4所示，点击处显示全部的应用程序，然后在处输入“terminal”，就可以找到我们想要的命令行终端。
+-  第二种方式是搜索功能，如下图所示，点击处显示全部的
+   应用程序，然后在处输入"terminal"，就可以找到我们想要的命令行终端。
+
+
+.. image:: media/comman005.jpeg
+   :align: center
+   :alt: 未找到图片
+
 
-|comman005|
 
-图 7‑4 打开terminal窗口
+-  第三种，在桌面点击鼠标右键，选择"打开终端"，如下图所示。
+
+.. image:: media/comman006.jpg
+   :align: center
+   :alt: 未找到图片
 
--  第三种，在桌面点击鼠标右键，选择“打开终端”，如图 7‑5所示。
 
-|comman006|
 
-图 7‑5 使用鼠标打开终端
 
 命令提示符
-~~~~~
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+
+.. image:: media/comman007.png
+   :align: center
+   :alt: 未找到图片
 
-|comman007|
 
-图 7‑6 命令提示符
 
-如图 7‑6，打开终端后，我们可以看到终端本身显示了一行字符，而且按回车后会重复出现：
+
+如上图，打开终端后，我们可以看到终端本身显示了一行字符，而且按回车后会重复出现：
 
 embedfire@dev:~$
 
 实际上这行提示符分成以下几个部分：
 
--  embedfire：显示的是当前的登录用户，图 7‑6现在使用的是 embedfire用户登录。
+-  embedfire：显示的是当前的登录用户，上图使用的是 embedfire用户登录。
 
 -  @：分隔符号，可理解为at，表示embedfire用户at主机dev上。
 
 -  dev：当前系统的主机名。
 
--  “:” ：分隔符号。
+-  ":" ：分隔符号。
 
--  ~：冒号后表示用户当前所在的目录，此处的波浪线表示当前用户的家目录，即“~”的含义为/home/embedfire目录。
+-  ~：冒号后表示用户当前所在的目录，此处的波浪线表示当前用户的家目录，即"~"的含义为/home/embedfire目录。
 
 -  $：命令提示符，Linux 用这个符号标识登录的用户权限等级。如果是超级用户，提示符就是 #，如果是普通用户，提示符就是 $。
 
 小试牛刀
-~~~~
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
-废话少说，请亲自尝试在终端中输入如下命令，注意如果使用了中文输入法的话，要记得把它切换回英文模式，另外，在以下命令中的波浪号“~”也是英文符号，还要注意终端中所有的内容都是区分大小写的：
+废话少说，请亲自尝试在终端中输入如下命令，注意如果使用了中文输入法的话，要记得把它切换回英文模式，另
+外，在以下命令中的波浪号"~"也是英文符号，还要注意终端中所有的内容都是区分大小写的：
 
 # 在后面的说明中，#号表示注释，它后面的内容不要输入到终端中
 
 # 在后面的说明中，#号表示注释，它后面的内容不要输入到终端中
 
-# 从下面开始是你要在终端中输入的命令（不包括#号后的内容）：
-
-cd /home # 切换到/home目录
-
-pwd # 显示当前目录
-
-cd ~ # 切换至~目录
+从下面开始是你要在终端中输入的命令（不包括#号后的内容）：
 
-pwd # 显示当前目录
+.. code-block:: sh
+   :linenos:
 
-ls # l是字母L的小写，不要把l输入成数字1或字母i的大写
+   cd /home # 切换到/home目录
+   pwd # 显示当前目录
+   cd ~ # 切换至~目录
+   pwd # 显示当前目录
+   ls # l是字母L的小写，不要把l输入成数字1或字母i的大写
+   ls -l # 同上，两个l都是字母L的小写
 
-ls -l # 同上，两个l都是字母L的小写
+每行命令输入后按回车，Shell就会对输入的命令进行解释，执行后输出，运行结果如下所示。
 
-每行命令输入后按回车，Shell就会对输入的命令进行解释，执行后输出，运行结果如图 7‑7所示。
+.. image:: media/comman008.png
+   :align: center
+   :alt: 未找到图片
 
-|comman008|
 
-图 7‑7 切换目录后的命令行提示
 
    以上各行命令的意义如下：
 
--  cd /home ：执行 “cd”命令，并以“/home”作为参数，表示切换至/home目录，命令执行后，我们可以看到命令提示符已变为 ：
+-  cd /home ：执行 "cd"命令，并以"/home"作为参数，表示切换至/home目录，命令执行后，我们
+   可以看到命令提示符已从 **embedfire@dev:~$变为embedfire@dev:/home$**
+   即其中的波浪符号"~"已变成"/home"。
 
-从 embedfire@dev:~$
+-  pwd：执行"pwd"命令，表示输出当前所在目录，可看到它的输出为"/home"，与命令提示符中的是一致的。
 
-变为 embedfire@dev:/home$
+-  cd ~ ：再次执行 "cd"命令，并以"~"作为参数，表示切换至"~"目录，命令执行后，我们可以看到命令提示符中的路径已由"/home"变回"~"。
 
-   即其中的波浪符号“~”已变成“/home”。
+-  pwd：再次执行"pwd"命令，输出当前所在目录，可看到它的输出为/home/embedfire，是当前用户的家目录，与命令提示符中的"~"表示的意思是一致的。
 
--  pwd：执行“pwd”命令，表示输出当前所在目录，可看到它的输出为“/home”，与命令提示符中的是一致的。
+-  ls ：执行"ls"命令，（注意这是字母L的小写，不是数字1也
+   不是字母i的大写），该命令表示列出当前目录下的内容，可以看到它的
+   输出与图形界面看到的是一致的，如下图所示，而且在终端中还以不同的字符颜色对文件夹与文件进行了区分。
 
--  cd ~ ：再次执行 “cd”命令，并以“~”作为参数，表示切换至“~”目录，命令执行后，我们可以看到命令提示符中的路径已由“/home”变回“~”。
-
--  pwd：再次执行“pwd”命令，输出当前所在目录，可看到它的输出为/home/embedfire，是当前用户的家目录，与命令提示符中的“~”表示的意思是一致的。
+..
 
--  ls ：执行“ls”命令，（注意这是字母L的小写，不是数字1也不是字母i的大写），该命令表示列出当前目录下的内容，可以看到它的输出与图形界面看到的是一致的，如图 7‑8，而且在终端中还以不同的字符颜色对文件夹与文件进行了区分。
+.. image:: media/comman009.png
+   :align: center
+   :alt: 未找到图片   
 
-..
 
-   |comman009|
 
-图 7‑8图形界面下的家目录内容
 
--  ls -l ：执行“ls”命令，并带“ -l ”（同样地，注意这是L的小写，不是数字1也不是字母i的大写）选项，该选项表示以列表的形式列出目录下的详细内容，可看到它比普通的ls命令多了很多内容，具体我们后面再分析。
+-  ls -l ：执行"ls"命令，并带" -l "（同样地，注意这是L的小写，不是数字1也不是字母i的大写）选
+   项，该选项表示以列表的形式列出目录下的详细内容，可看到它比普通的ls命令多了很多内容，具体我们后面再分析。
 
 命令的格式与帮助
-~~~~~~~~
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
 命令的格式
-^^^^^
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 
 通过以上的一些命令示例，我们大致可以归纳一下命令的格式：
 
-command [-options] [argument]
+.. code-block:: sh
+   :linenos:
+
+   command [-options] [argument]
 
 命令的组成一般分三部分，每部分之间使用空格隔开，说明如下：
 
 -  command：命令名，如前面的cd命令，pwd命令，ls命令。
 
--  -options：命令的选项，使用“-”开头的或“--”开头，如前面示例“ls -l”中的-l选项，命令会根据具体的选项执行不同的操作。使用“-”时一般是选项的简写，一些选项可以同时使用，“ls -la”等价于“ls -l
-  -a”，即同时使用“l”和“a”选项。而“--”一般后面带选项的全名，如“ls -a”等价于“ls --all”。
+-  -options：命令的选项，使用"-"开头的或"--"开头，如前
+   面示例"ls -l"中的-l选项，命令会根据具体的选项执行不同的
+   操作。使用"-"时一般是选项的简写，一些选项可以同时使
+   用，"ls -la"等价于"ls -l -a"，即同时
+   使用"l"和"a"选项。而"--"一般后面带选项的全
+   名，如"ls -a"等价于"ls --all"。
 
--  argument：命令参数，如前面cd命令中以“/home”可“~”参数作为路径名。
+-  argument：命令参数，如前面cd命令中以"/home"可"~"参数作为路径名。
 
-在命令格式中，使用“[ ]”括起来的内容表示它不是要求必需的，例如前面使用时cd命令时没有带选项，使用pwd命令不带选项及参数。
+在命令格式中，使用"[ ]"括起来的内容表示它不是要求必需的，例如前面使
+用时cd命令时没有带选项，使用pwd命令不带选项及参数。
 
 命令的帮助
-^^^^^
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+Linux下系统本身就支持数不清的命令，不同的命令又带不同的选
+项，输入的参数往往又有不同的意义，除了丢下一句"用多了就会记住"这不
+负责任的说法外，使用命令其实还是有一些门道的。
+
+每个命令都会带有一个"-h" 或者"--help"的参数，可以用来打印一些帮
+助说明。比如，现在不知道ls的选项a有什么用法，那么就可以执行下面的命令：
+
+.. code-block:: sh
+   :linenos:
 
-Linux下系统本身就支持数不清的命令，不同的命令又带不同的选项，输入的参数往往又有不同的意义，除了丢下一句“用多了就会记住”这不负责任的说法外，使用命令其实还是有一些门道的。
+   ls --help
 
-每个命令都会带有一个“-h” 或者“--help”的参数，可以用来打印一些帮助说明。比如，现在不知道ls的选项a有什么用法，那么就可以执行下面的命令：
+.. image:: media/comman010.png
+   :align: center
+   :alt: 未找到图片 
 
-ls --help
 
-|comman010|
 
-图 7‑9 --help参数
+从上图中圈出来的地方，可以知道参数a可以只列出隐藏的内容。现在执行命令：
 
-从图 7‑9圈出来的地方，可以知道参数a可以只列出隐藏的内容。现在执行命令：
+.. code-block:: sh
+   :linenos:
 
-ls –a
+   ls –a
 
-|comman011|
 
-图 7‑10 列出隐藏文件
+.. image:: media/comman011.png
+   :align: center
+   :alt: 未找到图片
 
-如图 7‑10，可看到该执行后比直接用“ls”命令多列出了很多以“.”开头的内容，在Linux下以“.”开头命名的文件或目录默认为隐藏文件，而ls的“-a”选项可以把它们显示出来。
 
-补充说明一下，帮助信息中的“-a”后面还有“--all”参数，这两个参数是等价的，只不过“--all”会比“-a”好记。
+
+从上图中可看到该执行后比直接用"ls"命令多列出了很多以"."开头
+的内容，在Linux下以"."开头命名的文件或目录默认为隐藏文件，而ls的"-a"选项可以把它们显示出来。
+
+补充说明一下，帮助信息中的"-a"后面还有"--all"参数，这两个参数是等价的，只不过"--all"会比"-a"好记。
 
 自动补全
-^^^^
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+有些时候我们甚至连命令的全称都想不起来，这时可以用到命令行的自动补全功能。就是键盘上神奇的"Tab"键。
 
-有些时候我们甚至连命令的全称都想不起来，这时可以用到命令行的自动补全功能。就是键盘上神奇的“Tab”键。
+假如我们知道有个命令是以"whic"开头，但想不起全称，那么我们可以在
+终端输入"whic"然后按一下"Tab"键（键盘上字母Q的左边），它会自动补全命令为"which"。
 
-假如我们知道有个命令是以“whic”开头，但想不起全称，那么我们可以在终端输入“whic”然后按一下“Tab”键（键盘上字母Q的左边），它会自动补全命令为“which”。
 
-|comman012|
+.. image:: media/comman012.jpg
+   :align: center
+   :alt: 未找到图片
 
-图 7‑11 按下Tab键的自动补全
 
-如果我们只记得命令是以“wh”开头的话，按一下“Tab”键发现它没反应（如果接入了耳机可以听到一下提示音），这时我们尝试按两下“Tab”键，如图 7‑12。
 
-|comman013|
 
-图 7‑12按两下Tab的提示
+如果我们只记得命令是以"wh"开头的话，按一下"Tab"键发现它
+没反应（如果接入了耳机可以听到一下提示音），这时我们
+尝试按两下"Tab"键，如下图所示。
 
-终端输出了好多以“wh”开头的命令，如which，who，whoami等。
+.. image:: media/comman013.jpg
+   :align: center
+   :alt: 未找到图片
 
-所以按一下“Tab”键时如果只有一个匹配的内容时它会自动补全，按两下“Tab”键则会列出所有的匹配项。
 
-“Tab”键除了用来补全命令名，还可以自动补全路径，如我们使用cd命令输入“/home”参数时，先输入“/ho”然后按下“Tab”键，它会把“/ho”自动补全为“/home”路径名，如图 7‑13。这在使用命令行时是频繁使用的技巧，能减少我们的输入，而且不容易出错。
 
-|comman014|
+终端输出了好多以"wh"开头的命令，如which，who，whoami等。
 
-图 7‑13 自动补全路径
+所以按一下"Tab"键时如果只有一个匹配的内容时它会自动补全，按两下"Tab"键则会列出所有的匹配项。
+
+"Tab"键除了用来补全命令名，还可以自动补全路径，如
+我们使用cd命令输入"/home"参数时，先输入"/ho"然后
+按下"Tab"键，它会把"/ho"自动补全为"/home"路径
+名，如下图所示。这在使用命令行时是频繁使用的技巧，能减少我们的输入，而且不容易出错。
+
+
+.. image:: media/comman014.jpg
+   :align: center
+   :alt: 未找到图片
+
+
+
+如果对命令只记得大概，也可以大致地乱敲一通，如果运气好，按下回车后如果终端
+找不到这个命令时它会输出类似命令的提示，我们可以根据提示来
+了解。我们输入"whihc"回车后如下图所示，它提示我们
+找不到"whihc"命令，并询问我们想输入的是不是"which"。
+
+
+.. image:: media/comman015.png
+   :align: center
+   :alt: 未找到图片
 
-如果对命令只记得大概，也可以大致地乱敲一通，如果运气好，按下回车后如果终端找不到这个命令时它会输出类似命令的提示，我们可以根据提示来了解。我们输入“whihc”回车后如图 7‑14，它提示我们找不到“whihc”命令，并询问我们想输入的是不是“which”。
 
-|comman015|
 
-图 7‑14 whihc的提示
 
 命令的退出与取消
-^^^^^^^^
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 
-在应用中我们有时会想要中止命令的执行，或者命令输入到一半的时候觉得输错了不想继续，这时我们都可以通过“Ctrl”+“c”的组合键来结束。
+在应用中我们有时会想要中止命令的执行，或者命令输入到一半的时候觉得输错
+了不想继续，这时我们都可以通过"Ctrl"+"c"的组合键来结束。
 
 如在终端输入：
 
-# 在后面的说明中，#号表示注释，它后面的内容不要输入到终端中
+**# 在后面的说明中，#号表示注释，它后面的内容不要输入到终端中**
 
-# 在后面的说明中，#号表示注释，它后面的内容不要输入到终端中
+.. code-block:: sh
+   :linenos:
 
-ping 127.0.0.1 #尝试ping测试自己的网络地址127.0.0.1
+   ping 127.0.0.1 #尝试ping测试自己的网络地址127.0.0.1
 
-#以上ping命令会持续输出，按下“Ctrl”+“c”组合键来结束
+**以上ping命令会持续输出，按下"Ctrl"+"c"组合键来结束**
 
-|comman016|
 
-图 7‑15 让命令停止执行
+.. image:: media/comman016.jpg
+   :align: center
+   :alt: 未找到图片
 
-又例如，我们在终端输入了以下内容，然后又不想让它执行，使用删除键一个个字符删除很麻烦，也可以通过“Ctrl”+“c”的组合键来取消：
 
-# 在后面的说明中，#号表示注释，它后面的内容不要输入到终端中
 
-# 在后面的说明中，#号表示注释，它后面的内容不要输入到终端中
 
-ls adfadfadsfadsfa
+又例如，我们在终端输入了以下内容，然后又不想让它执行，使用删除键一个
+个字符删除很麻烦，也可以通过"Ctrl"+"c"的组合键来取消：
+
+
+.. code-block:: sh
+   :linenos:
 
-#输入后不想运行以上命令，按下“Ctrl”+“c”组合键来结束
+   ls adfadfadsfadsfa
+
+输入以上命令后不想运行以上命令，按下"Ctrl"+"c"组合键来结束
+
+.. image:: media/comman017.jpg
+   :align: center
+   :alt: 未找到图片
 
-|comman017|
 
-图 7‑16 取消命令输入
 
 命令究竟是什么
-^^^^^^^
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+命令究竟是什么，当我们敲下命令"ls"后，Shell究竟做了什么事情。在《5.3.1 /bin目录》小节
+中提到，/bin目录下包含了很多命令，如下图所示，可看到ls、lsblk、lsmod、mkdir等命令程序。
+
+.. image:: media/comman018.png
+   :align: center
+   :alt: 未找到图片
+
 
-命令究竟是什么，当我们敲下命令“ls”后，Shell究竟做了什么事情。在《5.3.1 /bin目录》小节中提到，/bin目录下包含了很多命令，如图 7‑17，可看到ls、lsblk、lsmod、mkdir等命令程序。
 
-|comman018|
 
-图 7‑17 /bin下的内容
 
 在终端中，我们使用which命令可以查看指定命令的路径，如查看ls、pwd、cd命令：
 
 # 在后面的说明中，#号表示注释，它后面的内容不要输入到终端中
 
-which ls # 查看使用的是哪个ls命令
 
-which pwd # 查看使用的是哪个pwd命令
+.. code-block:: sh
+   :linenos:
 
-which cd # 查看使用的是哪个cd命令
+   which ls # 查看使用的是哪个ls命令
+   which pwd # 查看使用的是哪个pwd命令
+   which cd # 查看使用的是哪个cd命令
 
-|comman019|
+.. image:: media/comman019.png
+   :align: center
+   :alt: 未找到图片
 
-图 7‑18 查看命令的路径
 
-如图 7‑18可了解到ls命令实际是/bin/ls程序，pwd命令实际是/bin/pwd程序，而which cd命令没有输出，因为cd命令是Shell自己内部的程序。
 
-我们在Shell中输入ls命令与输入/bin/ls的作用是一样的，当我们输入Shell时，它会到预定的目录下查找有没有该程序，如果有就使用命令选项及参数调用该程序执行，并把程序的输出再呈现出来。而这个预定的目录我们可以通过如下命令来查看：
+从上图中可了解到ls命令实际是/bin/ls程序，pwd命令实际是/bin/pwd程序，而which cd命令没
+有输出，因为cd命令是Shell自己内部的程序。
+
+我们在Shell中输入ls命令与输入/bin/ls的作用是一样的，当我们输入Shell时，它会到预定
+的目录下查找有没有该程序，如果有就使用命令选项及参数调用该程序执行，并把程序
+的输出再呈现出来。而这个预定的目录我们可以通过如下命令来查看：
 
-# 在后面的说明中，#号表示注释，它后面的内容不要输入到终端中
 
-echo $PATH # echo是输出命令，而“$PATH”是一个变量，表示输出变量内容
+echo $PATH # echo是输出命令，而"$PATH"是一个变量，表示输出变量内容
 
-|comman020|
+.. image:: media/comman020.png
+   :align: center
+   :alt: 未找到图片
 
-图 7‑19 打印PATH环境变量
 
-“$PATH”是终端使用的路径环境变量，它使用“: ”进行分隔，表示Shell将会在这些路径下寻找命令程序，在其中我们可以看到/bin路径。也就是说，“$PATH” 路径环境变量让我们输入命令时省去了输入完整路径的麻烦，而命令的本质大都是在文件系统中的一些应用程序。
+
+"$PATH"是终端使用的路径环境变量，它使用": "进行分隔，表示Shell将会在这些路
+径下寻找命令程序，在其中我们可以看到/bin路径。也就是说，"$PATH" 路径环境变
+量让我们输入命令时省去了输入完整路径的麻烦，而命令的本质大都是在文件系统中的一些应用程序。
 
 常用命令
-~~~~
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
 下面我们列出一些常用命令的讲解，请都亲自在终端里尝试运行一下。
 
 cd命令
-^^^^
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 
 cd命令是change dir的简写，它可以把终端当前所在的路径切换至目标路径。该命令的格式如下：
 
-cd [目录名]
+.. code-block:: sh
+   :linenos:
+
+   cd [目录名]
 
-格式说明中 “目录名”就是要切换至的路径，若目录名称省略，则切换至当前用户的 home 目录 。
+格式说明中 "目录名"就是要切换至的路径，若目录名称省略，则切换至当前用户的 home 目录 。
 
-除某些有特殊要求的应用程序，Linux自带的所有命令在终端运行时，“目录名”都可以使用绝对路径或相对路径。
+除某些有特殊要求的应用程序，Linux自带的所有命令在终端运行时，"目录名"都可以使用绝对路径或相对路径。
 
-例如当前终端所在的路径为“/home/embedfire”，那么以下两个命令是等价的：
+例如当前终端所在的路径为"/home/embedfire"，那么以下两个命令是等价的：
 
 # 在后面的说明中，#号表示注释，它后面的内容不要输入到终端中
 
-# 假如当前目录为/home/embedfire
+假如当前目录为/home/embedfire
 
-cd test
 
-cd /home/embedfire/test
+.. code-block:: sh
+   :linenos:
 
-它们都表示切换至“/home/embedfire/test”目录，这其中的“test”就是相对路径，而“/home/embedfire/test”是绝对路径。
+   cd test
+   cd /home/embedfire/test
+
+它们都表示切换至"/home/embedfire/test"目录，这其中的"test"就是相对路径，而"/home/embedfire/test"是绝对路径。
 
 特别地，我们需要知道目录的如下表示：
 
--  “~”：波浪号，表示为当前用户的 home 目录
+-  "~"：波浪号，表示为当前用户的 home 目录
 
--  “.”：一个英文句号，表示当前目录
+-  "."：一个英文句号，表示当前目录
 
--  “..” ：两个英文句号，表示当前目录的上一层目录
+-  ".." ：两个英文句号，表示当前目录的上一层目录
 
--  “/” ：斜杠符号，表示为根目录
+-  "/" ：斜杠符号，表示为根目录
 
--  “-”：减号，不是目录，但作为cd命令的参数时可以返回上一次cd切换前的目录。
+-  "-"：减号，不是目录，但作为cd命令的参数时可以返回上一次cd切换前的目录。
 
 我们尝试执行以下命令，进行目录切换实验，注意其中的embedfire是当前的用户名，具体请根据自己的用户名进行修改。
 
 #在后面的说明中，#号表示注释，它后面的内容不要输入到终端中
 
-cd / # 切换至根目录
-
-ls # 列出当前目录的内容（根目录）
+.. code-block:: sh
+   :linenos:
 
-cd - # 返回至上一次的目录（家目录）
+   cd / # 切换至根目录
+   ls  # 列出当前目录的内容（根目录）
+   cd - # 返回至上一次的目录（家目录）
+   cd .. # 切换至上一级目录
+   ls # 列出当前目录的内容（home目录）
+   cd embedfire # 切换至embedfire目录（请把embedfire换成自己的用户名）
 
-cd ..
-# 切换至上一级目录
+注意以上命令中，命令名cd与路径名之间是有空格的，实际上包括以后使
+用的所有命令中，命令名，命令选项以及命令参数之间都是要有空
+格分隔开的。
 
-ls # 列出当前目录的内容（home目录）
+.. image:: media/comman021.png
+   :align: center
+   :alt: 未找到图片
 
-cd embedfire # 切换至embedfire目录（请把embedfire换成自己的用户名）
 
-注意以上命令中，命令名cd与路径名之间是有空格的，实际上包括以后使用的所有命令中，命令名，命令选项以及命令参数之间都是要有空格分隔开的。
 
-|comman021|
 
-图 7‑20 cd命令实验
-
-图 7‑20中执行切换至根目录的命令后，命令行提示符中的目录就变成“/”，且可以用直接用ls列出了当前的文件，最后再通过“-”参数切换回了用户的家目录。
+上图中执行切换至根目录的命令后，命令行提示符中的目录就变成"/"，且可以用
+直接用ls列出了当前的文件，最后再通过"-"参数切换回了用户的家目录。
 
 mkdir命令
-^^^^^^^
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 
 mkdir命令是make directory的简写，它可以在文件系统中创建一个新的目录。其命令格式如下：
 
-mkdir [-p] 目录名
+.. code-block:: sh
+   :linenos:
+
+   mkdir [-p] 目录名
 
-命令格式中的“目录名”就是要创建的目录路径，“-p”选项可以不输入，若使用了“-p”选项，当创建的目录名包含的上级目录不存在时，它会自动创建所有不存在的目录。
+命令格式中的"目录名"就是要创建的目录路径，"-p"选项可以不输入，若使用了"-p"选项，当创建
+的目录名包含的上级目录不存在时，它会自动创建所有不存在的目录。
 
 我们尝试执行以下命令：
 
 #在后面的说明中，#号表示注释，它后面的内容不要输入到终端中
 
-ls # 列出当前目录的内容，此时没有testdir目录
-
-mkdir testdir # 创建目录testdir
+.. code-block:: sh
+   :linenos:
 
-ls # 列出当前目录的内容，发现多了testdir
+   ls # 列出当前目录的内容，此时没有testdir目录
+   mkdir testdir # 创建目录testdir
+   ls # 列出当前目录的内容，发现多了testdir
+   mkdir other/test # 创建目录other/test，因为other不存在，报错
+   mkdir -p other/test # 使用 -p 选项创建目录other/test
+   ls # 列出当前目录的内容，发现other目录
+   ls other # 列出other目录的内容，发现test目录
 
-mkdir other/test # 创建目录other/test，因为other不存在，报错
+.. image:: media/comman022.png
+   :align: center
+   :alt: 未找到图片
 
-mkdir -p other/test # 使用 -p 选项创建目录other/test
 
-ls # 列出当前目录的内容，发现other目录
-
-ls other # 列出other目录的内容，发现test目录
-
-|comman022|
-
-图 7‑21 mkdir命令实验
 
 touch命令
-^^^^^^^
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 
 touch命令可以创建不存在的文件，或者touch通过参数修改目录或文件的日期时间，就是摸一下，更新它的时间。
 
 它的命令格式如下：
 
-touch 文件名
+.. code-block:: sh
+   :linenos:
+
+   touch 文件名
 
 尝试执行如下命令：
 
 #在后面的说明中，#号表示注释，它后面的内容不要输入到终端中
 
-touch helloworld # 在当前目录下创建一个名为helloworld的文件
+.. code-block:: sh
+   :linenos:
 
-ls # 显示当前目录下的内容
+   touch helloworld # 在当前目录下创建一个名为helloworld的文件
+   ls # 显示当前目录下的内容
 
-使用touch命令，新建一个helloworld的文件，然后使用ls命令来查看文件是否被创建，执行结果如图 7‑22所示。
+使用touch命令，新建一个helloworld的文件，然后使用ls命令来查看文件是否被创建，执行结果如下图所示。
+
+.. image:: media/comman023.png
+   :align: center
+   :alt: 未找到图片
 
-|comman023|
 
-图 7‑22 touch指令
 
 ls命令
-^^^^
+^^^^^^^^^^^^^^^^^^^^^^^^
 
-ls命令是list的简写，在前面我们已经频繁使用，它是Linux下最常用的指令，功能为显示指定目录下的内容（文件及子目录) ，还可以查看文件大小，修改日期等等信息。
+ls命令是list的简写，在前面我们已经频繁使用，它是Linux下最常用的指令，功能
+为显示指定目录下的内容（文件及子目录) ，还可以查看文件大小，修改日期等等信息。
 
 ls命令格式如下：
 
-ls [选项] [目录]
+.. code-block:: sh
+   :linenos:
+
+   ls [选项] [目录]
 
-当“目录”参数省略时，它会列出当前目录的内容。
+当"目录"参数省略时，它会列出当前目录的内容。
 
 除了基本的显示，ls命令还有以下常用选项：
 
--  -a： 显示所有文件及目录 (ls内定将文件名或目录名称开头为“.”的视为隐藏档，不会列出)
+-  -a： 显示所有文件及目录 (ls内定将文件名或目录名称开头为"."的视为隐藏档，不会列出)
 
 -  -l ：注意这是字母L的小写，除文件名称外，将文件型态、权限、拥有者、文件大小等信息详细列出
 
 -  -t ：将文件依建立时间之先后次序列出
 
--  -A： 同 -a ，但不列出 “.”(当前目录) 及 “..”(父目录)
+-  -A： 同 -a ，但不列出 "."(当前目录) 及 ".."(父目录)
 
 -  -R ：若目录下有文件，则该目录下的文件也会列出，即递归显示
 
@@ -426,61 +553,85 @@ ls [选项] [目录]
 
 #在后面的说明中，#号表示注释，它后面的内容不要输入到终端中
 
-ls # 列出当前目录的内容
+.. code-block:: sh
+   :linenos:
 
-ls -a # 显示当前目录下的所有内容
+   ls # 列出当前目录的内容
+   ls -a # 显示当前目录下的所有内容
+   ls -A # 显示当前目录下除"." 及 ".."外的所有内容
 
-ls -A # 显示当前目录下除“.” 及 “..”外的所有内容
+.. image:: media/comman024.jpg
+   :align: center
+   :alt: 未找到图片
 
-|comman024|
 
-图 7‑23 ls命令带参数a和A
 
-从图 7‑23可以看到，缺省参数下的ls命令只能列出非隐藏的文件或者文件夹，而ls –a或者ls –A这两条命令会把所有文件，包括隐藏文件在内都罗列出来。在linux中，以点“.”开头命名的文件在系统中被视为隐藏文件。不过ls –a 和 ls
-–A这两个命令的执行结果，区别在于是否列出“.”和“..”。
+从上图可以看到，缺省参数下的ls命令只能列出非隐藏的文件或者文件夹，而ls –a或者ls –A这两条命令会把所有文件，包括隐藏文件在内都罗列出来。在linux中，以点"."开头命名的文件在系统中被视为隐藏文件。不过ls –a 和 ls
+–A这两个命令的执行结果，区别在于是否列出"."和".."。
 
 除此之外，在终端上罗列出来的文件是白色的字体，而文件夹是淡蓝色的字体，以此来区分文件和文件夹。
 
-特别地，有时我们需要查看文件的详细信息，可以使用“-l”参数，我们尝试执行以下命令：
+特别地，有时我们需要查看文件的详细信息，可以使用"-l"参数，我们尝
+试执行以下命令：
+
+.. code-block:: sh
+   :linenos:
 
-ls -l
+   ls -l
 
-可以看到图 7‑24 参数l的执行结果的结果，得到当前目录下所有文件所占用的空间总和以及一个7个字段的列表。
+可以看到如下图的结果 参数l的执行结果的结果，得到当前目
+录下所有文件所占用的空间总和以及一个7个字段的列表。
 
-   |comman025|
+.. image:: media/comman025.jpg
+   :align: center
+   :alt: 未找到图片
 
-图 7‑24 参数l的执行结果
 
 各个字段的说明如下：
 
 第一字段：文件属性
 
-文件属性共有十个字符，第一个字符代表文件的类型，字符“-” 表示该文件是一个普通文件；字符“d”是dirtectory(目录)的首字符，表示该文件是一个目录。
+文件属性共有十个字符，第一个字符代表文件的类型，字符"-" 表示该文件是一个普通文件；字
+符"d"是dirtectory(目录)的首字符，表示该文件是一个目录。
 
-后面的九个字符，每三个为一组，分别表示文件拥有者的权限、文件所属组拥有的权限以及其他用户拥有的权限。字符“r”代表的是读（read）权限，字符“w”代表的是写（write）权限，字符“x”代表的是执行（execute）权限。
+后面的九个字符，每三个为一组，分别表示文件拥有者
+的权限、文件所属组拥有的权限以及其他用户拥有的
+权限。字符"r"代表的是读（read）权限，字符"w"代表的
+是写（write）权限，字符"x"代表的是执行（execute）权限。
 
 第二字段：链接占用的节点/子目录的个数
 
-第二字段的含义，主要取决该文件的类型，如果是文件的话，则表示该文件所具有的硬连接数。某个文件的第二字段如果等于1的话，代表没有其他指向该文件的硬连接。
+第二字段的含义，主要取决该文件的类型，如果是文件的话，则表示该文件所具
+有的硬连接数。某个文件的第二字段如果等于1的话，代表没有其他指向该文件的硬连接。
 
-根据 Linux 系统存储文件的特点，链接的方式可以分为两种，分别是硬链接和软连接（符号连接）。软链接，类似于Windows操作系统的快捷方式。而硬链接，则是相当于把该文件复制一份，同时加上自动更新。当我们修改了硬链接文件的内容，源文件也会被修改。当为某个文件创建硬链接时，该字段的值便会加1。可以使
+根据 Linux 系统存储文件的特点，链接的方式可以分为两种，分别是硬链接
+和软连接（符号连接）。软链接，类似于Windows操作系统的快捷方式。而硬链
+接，则是相当于把该文件复制一份，同时加上自动更新。当我们修改了硬链接文
+件的内容，源文件也会被修改。当为某个文件创建硬链接时，该字段的值便会加1。可以使
 用ln命令创建软链接和硬链接，当前只要知道有这回事即可，先不要纠结软链接和硬链接的概念。
 
-对于文件夹来说，第二字段则表示该文件夹下有多少个子目录。空文件夹的话，该值默认等于2，这是因为包含了“.”和“..”子目录。
+对于文件夹来说，第二字段则表示该文件夹下有多少个子目录。空文件夹
+的话，该值默认等于2，这是因为包含了"."和".."子目录。
 
 第三字段和第四字段：文件拥有者和文件所在的组
 
-Linux系统属于多用户系统，每个文件都有它的拥有者。结合第一字段的后九个字符，一般只有文件拥有者有权利去修改文件。当然，对于root用户有权利去修改任何文件。以“视频”文件夹为例：
+Linux系统属于多用户系统，每个文件都有它的拥有者。结合第一字段的后九个字
+符，一般只有文件拥有者有权利去修改文件。当然，对于root用户有权利
+去修改任何文件。以"视频"文件夹为例：
 
-|comman026|
+.. image:: media/comman026.jpg
+   :align: center
+   :alt: 未找到图片
 
-图 7‑25 视频文件夹
 
-结合图 7‑26，进行理解：对于文件拥有者embedfire，它拥有对该文件夹的读、写、执行的权限，对于在embedfire分组的其他成员xiaoming，就只可以进行读、执行的权限。还有位于Other分组的用户xiaohong，也是只有读、执行的权限。
 
-|comman027|
+结合下图，进行理解：对于文件拥有者embedfire，它拥有对该文件夹的读、写、执行的权限，对于在embedfire分组的其他成员xiaoming，就只可以进行读、执行的权限。还有位于Other分组的用户xiaohong，也是只有读、执行的权限。
+
+.. image:: media/comman027.jpg
+   :align: center
+   :alt: 未找到图片
+
 
-图 7‑26 Linux分组
 
 第五字段：文件所占用的空间(以字节为单位)
 
@@ -493,63 +644,85 @@ Linux系统属于多用户系统，每个文件都有它的拥有者。结合第
 第七字段：文件/文件夹名称
 
 cat命令
-^^^^^
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 
-cat命令是concatenate的简写，译为串联，即它可以把两个内容串联起来，我们通常使用它在终端下输出文件的内容进行查看。
+cat命令是concatenate的简写，译为串联，即它可以把两个内容串联起来，我们通
+常使用它在终端下输出文件的内容进行查看。
 
 命令格式为：
 
-cat 文件名
+.. code-block:: sh
+   :linenos:
+
+   cat 文件名
+
+前面我们使用gedit编辑器保存了一些内容到test123.txt文件上，此处
+可以使用如下命令把它的内容输出到终端：
 
-前面我们使用gedit编辑器保存了一些内容到test123.txt文件上，此处可以使用如下命令把它的内容输出到终端：
+.. code-block:: sh
+   :linenos:
 
-cat test123.txt
+   cat test123.txt
 
-|comman028|
 
-图 7‑27查看文件内容
+.. image:: media/comman028.png
+   :align: center
+   :alt: 未找到图片
+
 
 echo命令
-^^^^^^
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 
-echo命令的功能是在终端上打印一段文字，也可以把终端的变量内容打印出来。
+echo命令的功能是在终端上打印一段文字，也可以把终端
+的变量内容打印出来。
 
 其命令格式如下：
 
-echo “字符串”
-
-echo 字符串
+.. code-block:: sh
+   :linenos:
 
-echo $变量名
+   echo "字符串"
+   echo 字符串
+   echo $变量名
 
-使用echo命令时，带双引号和不带双引号的效果是一样的，使用引号时，要注意用英文符号。
+使用echo命令时，带双引号和不带双引号的效果是一样
+的，使用引号时，要注意用英文符号。
 
 我们尝试执行如下命令：
 
 #在后面的说明中，#号表示注释，它后面的内容不要输入到终端中
 
-echo “test” # 打印字符串test
+.. code-block:: sh
+   :linenos:
+
+   echo "test" # 打印字符串test
+   echo test # 打印字符串test
+   echo $PATH # 打印环境变量PATH
+   echo "$PATH" # 打印环境变量PATH
 
-echo test # 打印字符串test
 
-echo $PATH # 打印环境变量PATH
+.. image:: media/comman029.png
+   :align: center
+   :alt: 未找到图片
 
-echo “$PATH” # 打印环境变量PATH
 
-|comman029|
 
-图 7‑28 使用echo打印字符串或变量
 
 输出重定向到文件
-^^^^^^^^
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 
-在上面看到命令执行后都是输入到终端显示，有时我们希望把命令执行的结果保存到文件进行分析，这时我们可以使用输出重定向到文件的控制符“>”或“>>”，其中“>”会直接用输出覆盖原文件，而“>>”则把输出追加到原文件的末尾。
+在上面看到命令执行后都是输入到终端显示，有时我
+们希望把命令执行的结果保存到文件进行分析，这时我们可以使用
+输出重定向到文件的控制符">"或">>"，其中">"会直接用输出
+覆盖原文件，而">>"则把输出追加到原文件的末尾。
 
 使用格式如下：
 
-命令 > 文件名
+.. code-block:: sh
+   :linenos:
 
-命令 >> 文件名
+   命令 > 文件名
+   命令 >> 文件名
 
 重定向时文件不存在会自动创建。
 
@@ -557,65 +730,88 @@ echo “$PATH” # 打印环境变量PATH
 
 #在后面的说明中，#号表示注释，它后面的内容不要输入到终端中
 
-echo test > file.txt # 把echo test的输出重定向至file.txt文件
+.. code-block:: sh
+   :linenos:
 
-cat file.txt # 查看file.txt文件的内容
+   echo test > file.txt # 把echo test的输出重定向至file.txt文件
+   cat file.txt # 查看file.txt文件的内容
+   echo abc > file.txt # 把echo abc 的输出重定向至file.txt文件
+   cat file.txt # 查看file.txt文件的内容
+   echo 123456 >> file.txt # 把echo 123456的输出重定向追加至file.txt文件
+   cat file.txt # 查看file.txt文件的内容
+   ls > file.txt # 把ls命令的输出重定向至file.txt文件
+   cat file.txt # 查看file.txt文件的内容
 
-echo abc > file.txt # 把echo abc 的输出重定向至file.txt文件
 
-cat file.txt # 查看file.txt文件的内容
+.. image:: media/comman030.png
+   :align: center
+   :alt: 未找到图片
 
-echo 123456 >> file.txt # 把echo 123456的输出重定向追加至file.txt文件
 
-cat file.txt # 查看file.txt文件的内容
 
-ls > file.txt # 把ls命令的输出重定向至file.txt文件
 
-cat file.txt # 查看file.txt文件的内容
-
-|comman030|
-
-图 7‑29 输出重定向到文件
-
-如图 7‑29演示了echo命令和ls命令的输出重定向至文件file.txt中，重定向执行命令后输出不会显示在终端上。
+上图演示了echo命令和ls命令的输出重定向至
+文件file.txt中，重定向执行命令后输出不会显示在终端上。
 
 rmdir命令
-^^^^^^^
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 
 rmdir命令是remove directory的简写，它的功能是删除空的目录。
 
 命令格式如下：
 
-rmdir [-p] 目录名
+.. code-block:: sh
+   :linenos:
+
+   rmdir [-p] 目录名
 
-与mkdir的选项类似，-p可以用来递归删除目录，如果子目录删除后其父目录为空时，也一同被删除。
+与mkdir的选项类似，-p可以用来递归删除目录，如果子目
+录删除后其父目录为空时，也一同被删除。
 
-特别地，rmdir命令只能够用来删除空目录，当删除一个非空目录时，会提示“删除“某某某”目录失败：目录非空”，所以实际上这个命令用得并不多。
+特别地，rmdir命令只能够用来删除空目录，当删除一个非空
+目录时，会提示"删除"某某某"目录失
+败：目录非空"，所以实际上这个命令用得并不多。
 
-下面我们执行以下命令，来删除我们上面创建testdir目录和其other/test及其子目录。
+下面我们执行以下命令，来删除我们上面创建testdir目录
+和其other/test及其子目录。
 
 #在后面的说明中，#号表示注释，它后面的内容不要输入到终端中
 
-rmdir testdir # 删除testdir目录
+.. code-block:: sh
+   :linenos:
 
-rmdir -p other/test # 删除other/test目录，若删除后other为空，把other目录也删除掉
+   rmdir testdir # 删除testdir目录
+   rmdir -p other/test # 删除other/test目录，若删除后other为空，把other目录也删除掉
 
-|comman031|
+.. image:: media/comman031.png
+   :align: center
+   :alt: 未找到图片
 
-图 7‑30 rmdir命令实验
 
-命令rmdir –p other/test/是删除空子目录test，但由于参数p的作用下，删除了test目录之后，目录other也为空目录，因此other目录也会被一起删除。假如没有参数p的话，那么other目录依然会存在，读者可以自己尝试一下。
+
+
+命令rmdir –p other/test/是删除空子目录test，但由于参数p的作用下，删除了test目录
+之后，目录other也为空目录，因此other目录也会被一起删除。假如没有
+参数p的话，那么other目录依然会存在，读者可以自己尝试一下。
 
 rm命令
-^^^^
+^^^^^^^^^^^^^^^^^^^^^^^^
 
 rm命令是remove的简写，它的功能是删除一个或多个文件或目录。
 
 其命令格式如下：
 
-rm [选项] 一个或多个文件/文件夹名
+.. code-block:: sh
+   :linenos:
+
+   rm [选项] 一个或多个文件/文件夹名
 
-使用rm命令删除内容时，文件是会被直接永久删除的，它并不会放到回收站中再确认。所以在使用rm命令前，一定要考虑清楚。特别时如果你使用的是系统管理员账户或者通过后面介绍的sudo命令获取了系统权限，那么只需要一句命令就可以实现删库跑路，酿成大祸！
+使用rm命令删除内容时，文件是会被直接永久删除的，它并
+不会放到回收站
+中再确认。所以在使用rm命令前，一定要考虑清楚。特别
+时如果你使用的是系
+统管理员账户或者通过后面介绍的sudo命令获取了系统
+权限，那么只需要一句命令就可以实现删库跑路，酿成大祸！
 
 它支持的选项如下：
 
@@ -625,80 +821,128 @@ rm [选项] 一个或多个文件/文件夹名
 
 -  -f：忽略不存在的文件，无需逐一确认
 
-虽然rm命令使用不当很容易造成严重后果，但不能因噎废食，而且趁我们现在的系统是刚安装的，没有什么重要内容，在家目录进行操作通常也不会影响到系统的正常运行，所以大可以放心去运行以下命令进行实验：
+虽然rm命令使用不当很容易造成严重后果，但不能因噎废食，而且趁我们现
+在的系统是刚安装的，没有什么重要内容，在家目录进行操作通常也
+不会影响到系统的正常运行，所以大可以放心去运行以下命令进行实验：
 
 #在后面的说明中，#号表示注释，它后面的内容不要输入到终端中
 
 #先创建一些试验文件给后面删除
 
-mkdir -p ABC/test #创建ABC/test目录
+.. code-block:: sh
+   :linenos:
 
-ls #列出内容
+   mkdir -p ABC/test #创建ABC/test目录
+   ls #列出内容
 
-touch a.txt b.txt c.txt d.txt #创建 几个测试文件
+.. code-block:: sh
+   :linenos:
 
-ls #列出内容
+   touch a.txt b.txt c.txt d.txt #创建 几个测试文件
+   ls #列出内容
+
+先结合前面学习的mkdir和touch命令，在当前目录创建
+一个ABC目录，里面包含了一
+个子目录test还有a.txt，b.txt， c.txt，d.txt，执行结果
+如下图所示。
+
+
+.. image:: media/comman032.png
+   :align: center
+   :alt: 未找到图片
 
-先结合前面学习的mkdir和touch命令，在当前目录创建一个ABC目录，里面包含了一个子目录test还有a.txt，b.txt， c.txt，d.txt，执行结果如图 7‑31所示。
 
-|comman032|
 
-图 7‑31 创建文件
 
 删除文件测试
-''''''
+''''''''''''''''''''''''''''''
 
 #在后面的说明中，#号表示注释，它后面的内容不要输入到终端中
 
-rm a.txt b.txt #直接删除a.txt b.txt
+.. code-block:: sh
+   :linenos:
+
+   rm a.txt b.txt #直接删除a.txt b.txt
+   rm –i c.txt d.txt #询问式删除c.txt d.txt
 
-rm –i c.txt d.txt #询问式删除c.txt d.txt
+执行上面两条命令的其中一条都可以完成删除任务。当带有参
+数i时，则会有询问是否删除文件，如果是，输入y；反之，则输
+入n。如下图所示，直接
+删除了a.txt，b.txt。使用询问式删除时，删除了c.txt，保留
+了d.txt文件。
+
+
+.. image:: media/comman033.png
+   :align: center
+   :alt: 未找到图片
 
-执行上面两条命令的其中一条都可以完成删除任务。当带有参数i时，则会有询问是否删除文件，如果是，输入y；反之，则输入n。如图 7‑32所示，直接删除了a.txt，b.txt。使用询问式删除时，删除了c.txt，保留了d.txt文件。
 
-|comman033|
 
-图 7‑32 删除文件测试
 
 删除非空目录
-''''''
+''''''''''''''''''''''''''''''''''''
+
+前面提到rmdir命令不能删除非空的目录，我们可以使用rm命令
+配合"-r"选项来完成：
 
-前面提到rmdir命令不能删除非空的目录，我们可以使用rm命令配合“-r”选项来完成：
+.. code-block:: sh
+   :linenos:
 
-rm –r ABC/
+   rm –r ABC/
 
-|comman034|
+.. image:: media/comman034.png
+   :align: center
+   :alt: 未找到图片
 
-图 7‑33删除非空目录
 
-执行以上命令之后，就会把目录ABC以及子目录test，即ABC下的内容统统都删除掉。因此，为了防止误删文件，使用rm命令时尽可能加上参数i。
+
+
+执行以上命令之后，就会把目录ABC以及
+子目录test，即ABC下的内容统统都删除掉。因此，为了防止误
+删文件，使用rm命令时尽可能加上参数i。
 
 选项-f的作用
-'''''''
+'''''''''''''''''''''''''''''''''''
 
 执行以下两条命令，比较执行结果的差异：
 
-rm a.txt
+.. code-block:: sh
+   :linenos:
 
-rm –f a.txt
+   rm a.txt
+   rm –f a.txt
 
-|comman035|
+.. image:: media/comman035.png
+   :align: center
+   :alt: 未找到图片
 
-图 7‑34 使用-f选项的差异
 
-当使用第一条命令时，会提示“删除失败，找不到该文件”，但是当我们使用参数-f时，就忽略该提示。这里只是简单介绍一下该参数，日常使用中还是尽量不要使用该参数，以免造成无法挽回的损失。
+当使用第一条命令时，会提示"删除失败，找不到该文件"，但是当我们
+使用参数-f时，就忽略该提示。这里只是简单介绍一下该参数，日常使用中
+还是尽量不要使用该参数，以免造成无法挽回的损失。
 
 sudo命令
-^^^^^^
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 
 sudo命令是switch user do的简写，意思是切换用户去做某件事情。
 
-在Linux中，有一个名为root的超级用户。它可以做任何事情，权力越大，责任越大因此在日常工作中，若一时没注意输入了错误的命令，可能会导致系统崩溃，所以在Ubuntu下默认是不能用root用户登录的。但是在很多情况下我们又需要用到root的权限，如安装某个软件，若使用普通的用户会提示“权限不够”。
-这时候我们可以在需要root权限的命令前添加sudo命令，从而使当前用户获得root权限，并执行其后的命令。所以Ubuntu需要用sudo实际上是提醒我们接下来执行的命令有可能会影响到系统的关键内容，要小心操作。
+在Linux中，有一个名为root的超级用户。它可以做任何事情，权力越
+大，责任越大
+因此在日常工作中，若一时没注意输入了错误的命令，可能会
+导致系统崩溃，所以在Ubuntu下默认是
+不能用root用户登录的。但是在很多情况下我们又需要用到root的
+权限，如安装某个软件，若使用
+普通的用户会提示"权限不够"。
+这时候我们可以在需要root权限的命令前添加sudo命令，从而使当前用户获得root权限，并执
+行其后的命令。所以Ubuntu需要用sudo实际上是提醒我们接下来执行的命令有可能会影响
+到系统的关键内容，要小心操作。
 
 sudo命令格式如下：
 
-sudo 命令
+.. code-block:: sh
+   :linenos:
+
+   sudo 命令
 
 使用sudo命令时会提示输入你当前的用户密码，而不是root用户的密码。请注意，你输入的密码不会显示在终端上，而且终端也不会随着你的输入而显示星号（*）！自信地在键盘上敲入密码，然后按回车即可。
 
@@ -706,50 +950,64 @@ sudo 命令
 
 #在后面的说明中，#号表示注释，它后面的内容不要输入到终端中
 
-cd /home # 切换至/home目录
-
-touch test.txt # 尝试在当前目录创建test.txt文件
+.. code-block:: sh
+   :linenos:
 
-sudo touch test.txt # 使用sudo增加权限，创建test.txt文件
+   cd /home # 切换至/home目录
+   touch test.txt # 尝试在当前目录创建test.txt文件
+   sudo touch test.txt # 使用sudo增加权限，创建test.txt文件
 
-# 输入密码时终端也不会随着输入而显示星号（*），输入完回车即可！
+   # 输入密码时终端也不会随着输入而显示星号（*），输入完回车即可！
+   # 输入密码时终端也不会随着输入而显示星号（*），输入完回车即可！
+   # 输入密码时终端也不会随着输入而显示星号（*），输入完回车即可！
+   rm test.txt # 尝试删除test.txt文件
+   sudo rm test.txt # 使用sudo增加权限，删除test.txt文件
 
-# 输入密码时终端也不会随着输入而显示星号（*），输入完回车即可！
+.. image:: media/comman036.jpg
+   :align: center
+   :alt: 未找到图片
 
-# 输入密码时终端也不会随着输入而显示星号（*），输入完回车即可！
 
-rm test.txt # 尝试删除test.txt文件
 
-sudo rm test.txt # 使用sudo增加权限，删除test.txt文件
 
-|comman036|
 
-图 7‑35 使用sudo执行需要权限的操作
-
-如图 7‑35，当前用户是embedfire用户，切换至/home目录后，它没有往该目录写入文件的权限，所以直接用touch命令尝试创建文件时提示权限不够。当我们在touch命令前增加sudo命令，并输入正确的用户密码后获得了权限，所以文件被成功创建。类似地，当我们直接尝试用rm命令删除文件时，也会
-提示权限不足，再增加sudo后即可删除。而且可以发现这时不需要再次输入密码了，也就是说认证成功后能维持一段时间，但是使用命令时，还是要添加sudo操作。
+如上图所示，当前用户是embedfire用户，切换至/home目录后，它
+没有往该目录写入文件的权限，所以直接用touch命令尝试创建文件
+时提示权限不够。当我们在touch命令前增加sudo命令，并输入正确的用户
+密码后获得了权限，所以文件被成功创建。类似地，当我们直接尝试用rm命令删除文件时，也会
+提示权限不足，再增加sudo后即可删除。而且可以发现这时不需要再次输入
+密码了，也就是说认证成功后能维持一段时间，但是使用命令时，还是要添加sudo操作。
 
 部分用户在使用系统时，会觉得使用sudo命令很麻烦，有时干脆直接切换到root用户去进行开发，这常常会导致各种问题。例如部分构建工具直接不支持root用户运行，有时我们用了root用户去解压或拷贝工程文件，一不注意又使用普通用户去运行，这时会因为普通用户没有权限而出错，但找起原因却很浪费时间。所以，
 我们强烈建议在开发及日常使用时，不要使用root用户。
 
 clear命令
-^^^^^^^
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 
 终端执行各种命令后会保留之前的内容在屏幕上，如果觉得碍眼，可以直接运行clear命令清除：
 
-clear
+.. code-block:: sh
+   :linenos:
+
+   clear
 
 reboot/poweroff命令
-^^^^^^^^^^^^^^^^^
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 
 在终端上，reboot/poweroff命令来控制系统的重启与关机。直接使用如下命令即可：
 
-reboot
+.. code-block:: sh
+   :linenos:
+
+   reboot
+   poweroff
 
-poweroff
+注意:IMX6ULL开发板在使用poweroff命令关机后，需要长按ON/OFF键1~2秒才能正常开机。
+这是因为执行poweroff后，芯片的SNVS(电源管理)寄存器进入关机状态。纽扣电池只要持续供电，
+那么芯片会一直保持关机状态，直到触发ON/OFF键后才能改变关机状态。
 
 man命令
-~~~~~
+~~~~~~~~~~~~~~~~~~~~~~~~~
 
 man命令值得我们为它独立一小节来进行说明。
 
@@ -757,95 +1015,153 @@ man命令值得我们为它独立一小节来进行说明。
 help选项外，Linux还提供了一个man命令，可用于查看Linux系统自带的参考手册，该手册包含非常丰富的内容，甚至在我们进行编程开发时还可以使用它来查看函数的接口。
 
 man基本用法
-'''''''
+'''''''''''''''''''''''''''''''''''''''''''''''''
 
 man命令格式：
 
-man [要查询的内容]
+.. code-block:: sh
+   :linenos:
+
+   man [要查询的内容]
+
+使用起来非常简单，如我们想查看ls命令的说明，直接输
+入如下命令即可：
+
+
+.. code-block:: sh
+   :linenos:
+
+   man ls
+
+.. image:: media/comman037.png
+   :align: center
+   :alt: 未找到图片
+
 
-使用起来非常简单，如我们想查看ls命令的说明，直接输入如下命令即可：
 
-man ls
 
-|comman037|
 
-图 7‑36 man中的帮助说明
 
-按键盘方向键的“↑”“↓”键可以实现上下切页。按“q”键可以退出手册。
+按键盘方向键的"↑""↓"键可以实现上下切页。按"q"键可以退出手册。
 
 man手册的章节
-''''''''
+''''''''''''''''''''''''''''''''''''''''
 
 关于man手册本身的使用，可以使用如下命令查看：
 
-man man
+.. code-block:: sh
+   :linenos:
 
-|comman038|
+   man man
 
-图 7‑37 man man指令
+.. image:: media/comman038.png
+   :align: center
+   :alt: 未找到图片
 
-从图 7‑37可了解到，除了Shell命令外，还可以看到man手册支持共9种类型的内容，如第一章是关于Shell命令，第二章是系统调用（内核提供的函数）、第三章是库调用（程序库中的函数），如我们可以查看内核函数fork及C标准库函数printf的说明：
 
-man fork
 
-man printf
+从上图可了解到，除了Shell命令外，还可以看到man手册支持共9种类型
+的内容，如第一章是关于Shell命令，第二章是系统调用（内核提供的函数）、第三章
+是库调用（程序库中的函数），如我们可以查看内核函数fork及C标准库函数printf的说明：
 
-|comman039|
+.. code-block:: sh
+   :linenos:
 
-图 7‑38 fork函数的帮助说明
+   man fork
+   man printf
 
-|comman040|
+.. image:: media/comman039.png
+   :align: center
+   :alt: 未找到图片
 
-图 7‑39 printf函数的帮助说明
 
-说明页开头的 “FORK(2)”、 “PRINTF(1)”括号内的数字表明了它在man手册中的章节号。即此处的FORK页的说明是第二章的内容，正是我们要查询的内核函数说明（系统调用）。而此处PRINTF页面实际是第一章的内容，man手册的第一章是关于Shell命令的，在Shell中刚好有一个命令也是
-名为“printf”，所以它出现了这样的搜索结果，该页的说明不是我们想要的C库函数内容，C库函数的说明应位于man手册的第三章。
+
+.. image:: media/comman040.png
+   :align: center
+   :alt: 未找到图片
+
+
+
+说明页开头的 "FORK(2)"、 "PRINTF(1)"括号内的数字表明了它
+在man手册中的章节号。即此处的FORK页的说明是
+第二章的内容，正是我们要查询的内核函数说明（系统调用）。而
+此处PRINTF页面实际是第一章的内容，man手册的第
+一章是关于Shell命令的，在Shell中刚好有一个命令也是
+名为"printf"，所以它出现了这样的搜索结果，该页的说明不是我
+们想要的C库函数内容，C库函数的说明应位于man手册的第三章。
 
 查询指定章节的内容
-'''''''''
+'''''''''''''''''''''''''''''''''''''''''
+
+man是按默认顺序来查找的，有时我们要查阅的内容可能在前面的手
+册出现，而它不是我们需要的内容，例如前面的C库函数printf ，或者
+查阅open系统调用函数时，出现的却是Shell的printf和openvt程序说明：
+
+#直接man open，它会按默认顺序搜索，结果搜索出了openvt的Shell命
+令说明
+
+.. code-block:: sh
+   :linenos:
+
+   man open
+
+.. image:: media/comman041.png
+   :align: center
+   :alt: 未找到图片
+
+
+
+在上图中可以看到OPENVT(1)说明页是在第一章节的，与PRINTF(1)类似。
+
+解决这个问题可以通过指定章节号来查询，因为我们要查询的printf是C库函
+数、open是Linux的"系统调用"API，所以我们可指定它就在该章节查找，前
+面的man命令输出中可看到"库调用"属于第3章，而"系统调用"是属
+于第2章，所以使用man命令时，我们通过"-s"选项指定它搜索的章节号：
 
-man是按默认顺序来查找的，有时我们要查阅的内容可能在前面的手册出现，而它不是我们需要的内容，例如前面的C库函数printf ，或者查阅open系统调用函数时，出现的却是Shell的printf和openvt程序说明：
+通过-s指定搜索章节的内容
 
-#直接man open，它会按默认顺序搜索，结果搜索出了openvt的Shell命令说明
+man手册的章节3是"库调用"相关的函数说明
 
-man open
+.. code-block:: sh
+   :linenos:
 
-|comman041|
+   man -s 3 printf
 
-图 7‑40 man手册章节1的openvt程序说明
+可以省略-s，使用以下命令是等价的
 
-在图 7‑40中可以看到OPENVT(1)说明页是在第一章节的，与PRINTF(1)类似。
+.. code-block:: sh
+   :linenos:
 
-解决这个问题可以通过指定章节号来查询，因为我们要查询的printf是C库函数、open是Linux的“系统调用”API，所以我们可指定它就在该章节查找，前面图 7‑37中的man
-man命令输出中可看到“库调用”属于第3章，而“系统调用”是属于第2章，所以使用man命令时，我们通过“-s”选项指定它搜索的章节号：
+   man 3 printf
 
-#通过-s指定搜索章节的内容
+man手册的章节2是"系统调用"相关的函数说明
 
-#man手册的章节3是“库调用”相关的函数说明
+.. code-block:: sh
+   :linenos:
 
-man -s 3 printf
+   man -s 2 open
 
-#可以省略-s，使用以下命令是等价的
+可以省略-s，使用以下命令是等价的
 
-man 3 printf
+.. code-block:: sh
+   :linenos:
 
-#man手册的章节2是“系统调用”相关的函数说明
+   man 2 open
 
-man -s 2 open
+.. image:: media/comman042.png
+   :align: center
+   :alt: 未找到图片
 
-#可以省略-s，使用以下命令是等价的
 
-man 2 open
 
-|comman042|
 
-图 7‑41 指定章节号查询出的printf函数说明
+.. image:: media/comman043.jpg
+   :align: center
+   :alt: 未找到图片
 
-|comman043|
 
-图 7‑42 指定章节号查找出的open说明
 
-图 7‑42是man手册中关于open函数的用法，分为以下三个部分：
+上图是man手册中关于open函数的用法，分为以下三个部分：
 
 -  第一部分，通常是该函数的概述，介绍该函数的功能。open、openat、creat函数可用于打开文件，某些情况下也可用于创建新文件。
 
diff --git a/documentation/linux_basis/ebf6ull_hardware.rst b/documentation/linux_basis/ebf6ull_hardware.rst
index db3a7ecafb773fcd4498bd01d0399d3b13b141b9..8a4fffdb05d540508096d8783973854e133f40a9 100644
--- a/documentation/linux_basis/ebf6ull_hardware.rst
+++ b/documentation/linux_basis/ebf6ull_hardware.rst
@@ -8,34 +8,46 @@
 EBF6ULL Mini及Pro开发板
 ~~~~~~~~~~~~~~~~~~~
 
-EBF6ULL 系列开发板是野火电子基于NXP i.MX 6ULL系列处理器设计的一款低功耗单板电脑，工业级主频最高可达 792MHz，按底板功能主要分为Mini和Pro两个版本，具体见图 10‑1及图 10‑2。
+EBF6ULL 系列开发板是野火电子基于NXP i.MX 6ULL系列处理器设计的一款低功耗单板电
+脑，工业级主频最高可达 792MHz，按底板功能主要分为Mini和Pro两个版本，具体见下图。
 
-|ebf6ul002|
 
-图 10‑1 EBF6ULL S1 Mini开发板
 
-|ebf6ul003|
 
-图 10‑2 EBF6ULL S1 Pro开发板
+.. image:: media/ebf6ul002.jpeg
+   :align: center
+   :alt: 未找到图片2|
 
-EBF6ULL开发板提供完整的SDK驱动开发包、核心板封装库，底板应用参考设计原理图，可帮助客户大大缩减产品的开发时间，加快产品上市。目前提供Linux 4.1.15版本的内核，配套的系统自带python、Qt等组件。
 
-开发板整板由EBF6ULL S1核心板模组和底板组成，具体见图 10‑3，元件采用工业级选料，其中核心板板载主控芯片512MB DDR3L内存，256/512MB Nand-FLASH（或8GB eMMC）。
 
-|ebf6ul004|
+.. image:: media/ebf6ul003.jpeg
+   :align: center
+   :alt: 未找到图片3|
+
+
+
+EBF6ULL开发板提供完整的SDK驱动开发包、核心板封装库，底板应用参考设计原理图，可帮助客户大大缩减产品的开发时间，加快产品上市。目前提供Linux 4.19.71版本的内核，配套的系统镜像有纯净版、Qt_demo、桌面系统三个版本。
+
+开发板整板由EBF6ULL S1核心板模组和底板组成，具体见下图，元件采用工业级选料，其中核心板板载主控芯片512MB DDR3L内存，256/512MB Nand-FLASH（或8GB eMMC）。
+
+.. image:: media/ebf6ul004.jpeg
+   :align: center
+   :alt: 未找到图片4|
+
 
-图 10‑3核心板外观
 
 核心板PCB采用8层黑色沉金设计，单面放元件，整体尺寸39x39mm，共140个引脚，引脚间距1.0mm，除了SEMC总线引脚外，芯片其余IO均引出。该核心板适用于工业控制、手持扫码、喷墨打印机、轨道交通、无人机控制和音频输出等领域。
 
 EBF6ULL核心板硬件资源
 ~~~~~~~~~~~~~~
 
-野火EBF6ULL核心板包含多种配置版本，它按照核心板上FLASH存储器类型进行区分，具体见图 10‑4。
+野火EBF6ULL核心板包含多种配置版本，它按照核心板上FLASH存储器类型进行区分，具体见下图。
+
+.. image:: media/ebf6ul005.jpeg
+   :align: center
+   :alt: 未找到图片5|
 
-|ebf6ul005|
 
-图 10‑4 EBF6ULL S1邮票孔核心板内部
 
    EBF6ULL S1核心板模组参数如下：
 
@@ -47,9 +59,9 @@ EBF6ULL核心板硬件资源
 
 -  FLASH存储器示不同型号的板子，使用以下其中一种配置：
 
-   -  板载256MB或512MB的 Nand-FALSH
+-  板载256MB或512MB的 Nand-FALSH
 
-   -  板载8GB 的eMMC
+-  板载8GB 的eMMC
 
 -  PCB：8层黑色沉金，尺寸为39 x39mm
 
@@ -60,15 +72,19 @@ EBF6ULL核心板硬件资源
 EBF6ULL Mini底板硬件资源
 ~~~~~~~~~~~~~~~~~~
 
-EBF6ULL Mini底板硬件资源见图 10‑5。
+EBF6ULL Mini底板硬件资源见下图。
 
-|ebf6ul006|
+.. image:: media/ebf6ul006.jpg
+   :align: center
+   :alt: 未找到图片6|
 
-图 10‑5 EBF6ULL S1 Mini开发板硬件资源图（正面）
 
-|ebf6ul007|
 
-图 10‑6 EBF6ULL S1 Mini开发板硬件资源图（背面）
+.. image:: media/ebf6ul007.jpeg
+   :align: center
+   :alt: 未找到图片7|
+
+
 
    EBF6ULL S1 Mini底板参数如下：
 
@@ -107,13 +123,15 @@ EBF6ULL Mini底板硬件资源见图 10‑5。
 EBF6ULL Pro底板硬件资源
 ~~~~~~~~~~~~~~~~~
 
-野火EBF6ULL Pro底板硬件资源见图 10‑5。
+野火EBF6ULL Pro底板硬件资源见下图。
+
+.. image:: media/ebf6ul008.jpeg
+   :align: center
+   :alt: 未找到图片8|
 
-|ebf6ul008|
 
-图 10‑7 EBF6ULL S1 Pro开发板硬件资源图
 
-表 10‑1 EBF6ULL S1 Pro底板硬件资源表
+表   EBF6ULL S1 Pro底板硬件资源表
 
 ============ ============================================================================================
 尺寸         200*13.5MM
@@ -153,6 +171,9 @@ LCD接口      FPC接口，RGB888及I2C触摸信号，支持直接连接野火
 GPIO         通过两排2*40P的2.54间距排针引出，可自主连接各种外部设备
 ============ ============================================================================================
 
+
+
+
 .. |ebf6ul002| image:: media/ebf6ul002.jpeg
    :width: 5.76806in
    :height: 4.13704in
diff --git a/documentation/linux_basis/ec20_4g_module.rst b/documentation/linux_basis/ec20_4g_module.rst
new file mode 100644
index 0000000000000000000000000000000000000000..0f51fbe1f70bc235c7c9ff2d7e0fd97e855f378f
--- /dev/null
+++ b/documentation/linux_basis/ec20_4g_module.rst
@@ -0,0 +1,454 @@
+在Debian使用4G模块
+==================
+
+-  平台：野火imx6ull开发板
+-  系统：Debian
+-  Debian版本：需要使用最新的Debian镜像，必须是2020年5月1日以后的镜像，否则无法ppp拨号成功。
+-  需要使用野火4G模块
+
+野火4G模块
+----------
+
+野火EC20 4G模块是由EC20
+Pcie接口模组加一个USB转接板构成，可方便插接到带有USB接口的Linux主板上。EC20型号众多，我们选用的型号是CEHCLG，全网通，7模，纯数据、单天线版本。
+
+.. figure:: media/EC20_4G_module001.png
+   :alt: EC20_4G_module001.png
+
+   EC20_4G_module001.png
+
+EC20是移远的一款4G模组，有Mini PCle和LCC两种封装，与处理器通信的协议为USB。即你们在市面上看到的那些通过板载的PCle接口与EC20连接的开发板，他们通信时也是通过USB通信，并不是一些初学用户说的通过PCle通信，PCle只是一种封装而已，最终通信都是通过USB。
+
+.. figure:: media/EC20_4G_module002.png
+   :alt: EC20_4G_module002.png
+
+   EC20_4G_module002.png
+
+.. figure:: media/EC20_4G_module003.png
+   :alt: EC20_4G_module003.png
+
+   EC20_4G_module003.png
+
+野火开发板使用4G模块
+--------------------
+
+野火开发板出厂固件已经支持4G模块的，所以在收到开发板后可以直接使用，使用方式也非常简单，首先插入4G的电话卡到SIM卡座上，这张电话卡必须是可以上网的，然后接上IPX天线（4G模块在发货的时候就已经接好天线的了），最终连接到开发板上，Pro或者mini开发板都可以使用野火4G模块。
+
+.. figure:: media/EC20_4G_module004.png
+   :alt: EC20_4G_module004.png
+
+   EC20_4G_module004.png
+.. figure:: media/EC20_4G_module005.png
+   :alt: EC20_4G_module005.png
+
+   EC20_4G_module005.png
+
+等待大约6S，可以看到4G模块的蓝色LED灯在闪烁，然后可以在终端输入dmesg命令，能看到以下内容，就代表模块启动成功：
+
+.. code:: bash
+
+    dmesg
+
+    ···
+    [83577.336314] usb 1-1.1: new high-speed USB device number 13 using ci_hdrc
+    [83577.607805] option 1-1.1:1.0: GSM modem (1-port) converter detected
+    [83577.617195] usb 1-1.1: GSM modem (1-port) converter now attached to ttyUSB0
+    [83577.619058] option 1-1.1:1.1: GSM modem (1-port) converter detected
+    [83577.646781] usb 1-1.1: GSM modem (1-port) converter now attached to ttyUSB1
+    [83577.648866] option 1-1.1:1.2: GSM modem (1-port) converter detected
+    [83577.654863] usb 1-1.1: GSM modem (1-port) converter now attached to ttyUSB2
+    [83577.659113] option 1-1.1:1.3: GSM modem (1-port) converter detected
+    [83577.660546] usb 1-1.1: GSM modem (1-port) converter now attached to ttyUSB3
+    [83577.662514] option 1-1.1:1.4: GSM modem (1-port) converter detected
+    [83577.686784] usb 1-1.1: GSM modem (1-port) converter now attached to ttyUSB4
+
+更新
+----
+
+为了确保我们的软件包版本是最新版本，让我们使用apt命令更新本地apt包索引和升级系统：
+
+.. code:: bash
+
+    sudo apt-get update
+
+安装必要的依赖
+--------------
+
+首先安装ppp拨号相关的依赖，安装过程中出现任何输入的内容，直接按 **回车** 即可：
+
+.. code:: bash
+
+    sudo apt-get -y install ipppd
+
+安装野火提供的4g模块拨号脚本，在安装完成后在 ``/home/debian`` 目录下出现 ``peripheral`` 文件夹：
+
+.. code:: bash
+
+    sudo apt-get -y install peripheral
+
+拨号上网
+--------
+
+模块想要上网则需要拨号，进入 ``~/peripheral/ec20-4g``
+目录下，可以看到该目录存在以下文件（部分）：
+
+-  ec20_options
+-  ec20_ppp_dialer
+-  ppp-on.sh
+
+ppp-on.sh就是拨号脚本，直接运行它可以进行拨号，ec20_options是拨号的配置文件，而ec20_ppp_dialer
+则是拨号的一些指令。
+
+三个文件的内容如下：
+
+**ec20_options：**
+
+.. code:: bash
+
+    /dev/ttyUSB2
+    115200
+    crtscts
+    modem
+    persist
+    lock
+    noauth
+    noipdefault
+    debug
+    nodetach
+    user Anyname
+    password Anypassword
+    ipcp-accept-local
+    ipcp-accept-remote
+    #replacedefaultroute
+    defaultroute
+    usepeerdns
+    noccp
+    nobsdcomp
+    novj
+    #Dump
+
+**ec20_ppp_dialer：**
+
+.. code:: bash
+
+    ABORT "NO CARRIER"
+    ABORT "ERROR"
+    TIMEOUT 120
+    "" ATE
+    SAY "ATE"
+    ECHO ON
+    OK ATH
+    OK ATP
+    OK AT+CGDCONT=1,\"IP\",\"CMNET\"
+    #OK AT+ZSNT=0,0,0
+    OK ATD*98*1#
+    CONNECT
+
+**ppp-on.sh：**
+
+.. code:: bash
+
+    #!/bin/sh
+    #clear
+    #ppp-on.sh
+    OPTION_FILE="ec20_options"
+    DIALER_SCRIPT="ec20_ppp_dialer"
+    pppd file $OPTION_FILE connect '/usr/sbin/chat -v -f ec20_ppp_dialer' &
+
+那么我们直接运行ppp-on.sh即可，注意：需要sudo权限运行。
+
+.. code:: bash
+
+    sudo ./ppp-on.sh
+
+    Removed stale lock on ttyUSB2 (pid 4125)
+    ➜  ec20-4g ATE
+    +CMTI: "ME",2
+
+    +CMTI: "ME",3
+
+    +CMTI: "ME",4
+    ATE
+    OK
+    ATH
+    OK
+    ATP
+    OK
+    AT+CGDCONT=1,"IP","CMNET"
+    OK
+    ATD*98*1#
+    CONNECT
+    Script /usr/sbin/chat -v -f ec20_ppp_dialer finished (pid 5776), status = 0x0
+    Serial connection established.
+    using channel 9
+    Using interface ppp0
+    Connect: ppp0 <--> /dev/ttyUSB2
+    sent [LCP ConfReq id=0x1 <asyncmap 0x0> <magic 0x64c762f8> <pcomp> <accomp>]
+    rcvd [LCP ConfReq id=0x0 <asyncmap 0x0> <auth chap MD5> <magic 0xa326b19> <pcomp> <accomp>]
+    sent [LCP ConfAck id=0x0 <asyncmap 0x0> <auth chap MD5> <magic 0xa326b19> <pcomp> <accomp>]
+    rcvd [LCP ConfAck id=0x1 <asyncmap 0x0> <magic 0x64c762f8> <pcomp> <accomp>]
+    sent [LCP EchoReq id=0x0 magic=0x64c762f8]
+    rcvd [LCP DiscReq id=0x1 magic=0xa326b19]
+    rcvd [CHAP Challenge id=0x1 <163eafbf8714ed417edfd556ca784e60>, name = "UMTS_CHAP_SRVR"]
+    sent [CHAP Response id=0x1 <d2f3e94b688d9898ea55893da7cfd10e>, name = "Anyname"]
+    rcvd [LCP EchoRep id=0x0 magic=0xa326b19 64 c7 62 f8]
+    rcvd [CHAP Success id=0x1 ""]
+    CHAP authentication succeeded
+    CHAP authentication succeeded
+    sent [IPCP ConfReq id=0x1 <addr 0.0.0.0> <ms-dns1 0.0.0.0> <ms-dns2 0.0.0.0>]
+    rcvd [IPCP ConfReq id=0x0]
+    sent [IPCP ConfNak id=0x0 <addr 0.0.0.0>]
+    rcvd [IPCP ConfNak id=0x1 <addr 10.17.241.161> <ms-dns1 202.96.134.33> <ms-dns2 202.96.128.166>]
+    sent [IPCP ConfReq id=0x2 <addr 10.17.241.161> <ms-dns1 202.96.134.33> <ms-dns2 202.96.128.166>]
+    rcvd [IPCP ConfReq id=0x1]
+    sent [IPCP ConfAck id=0x1]
+    rcvd [IPCP ConfAck id=0x2 <addr 10.17.241.161> <ms-dns1 202.96.134.33> <ms-dns2 202.96.128.166>]
+    Could not determine remote IP address: defaulting to 10.64.64.64
+    not replacing default route to eth1 [192.168.0.1]
+    local  IP address 10.17.241.161
+    remote IP address 10.64.64.64
+    primary   DNS address 202.96.134.33
+    secondary DNS address 202.96.128.166
+    Script /etc/ppp/ip-up started (pid 5783)
+    Script /etc/ppp/ip-up finished (pid 5783), status = 0x0
+
+当你看到拨号返回的内容后有IP地址时，就证明拨号成功，当然你也可以通过 ``ifconfig`` 命令去查看4g模块的IP地址。
+
+.. code:: bash
+
+    rcvd [IPCP ConfNak id=0x1 <addr 10.17.241.161> <ms-dns1 202.96.134.33> <ms-dns2 202.96.128.166>]
+    sent [IPCP ConfReq id=0x2 <addr 10.17.241.161> <ms-dns1 202.96.134.33> <ms-dns2 202.96.128.166>]
+
+验证4G网卡
+----------
+
+一旦拨号成功，可以使用 ``ifconfig`` 命令验证4G网卡是否存在，如果成功此时会多出来一个ppp0的网卡，并且已经获取到IP地址了。可以很明显看到，我们目前有了一个4g模块的网卡ppp0，存在IP地址，那么说明我们可以使用ppp0进行网络通信：
+
+.. code:: bash
+
+    ifconfig
+
+    ppp0: flags=4305<UP,POINTOPOINT,RUNNING,NOARP,MULTICAST>  mtu 1500
+            inet 10.17.241.161  netmask 255.255.255.255  destination 10.64.64.64
+            ppp  txqueuelen 3  (Point-to-Point Protocol)
+            RX packets 4  bytes 52 (52.0 B)
+            RX errors 0  dropped 0  overruns 0  frame 0
+            TX packets 4  bytes 58 (58.0 B)
+            TX errors 0  dropped 0 overruns 0  carrier 0  collisions 0
+
+然后我们可以验证一下ping功能，是否可以访问互联网（此处以ping
+baidu.com为示例）：
+
+.. code:: bash
+
+    ping baidu.com
+
+    PING baidu.com (39.156.69.79): 56 data bytes
+    64 bytes from 39.156.69.79: seq=0 ttl=48 time=60.056 ms
+    64 bytes from 39.156.69.79: seq=1 ttl=48 time=62.634 ms
+    64 bytes from 39.156.69.79: seq=2 ttl=48 time=50.397 ms
+
+可能你是接了网线的（假设使用了eth1接口），而默认路由表却不是4G模块，如果想使用网卡上网，则需要更新路由表，解决办法如下：
+
+.. code:: bash
+
+    route del-net 0.0.0.0 eth1
+    route add-net 0.0.0.0 ppp0
+
+网速测试
+--------
+
+本次测试使用阿里云服务器4M带宽主机，经测试，4G模块已经将4M带宽跑满了，但是还未到模块上限，由于测试主机带宽有限，暂不能做更高速度的测试，但足以证明本模块的性能。
+
+测试结果：
+
+**接收模式：**
+
+.. figure:: media/EC20_4G_module006.png
+   :alt: EC20_4G_module006.png
+
+   EC20_4G_module006.png
+
+**发送模式：**
+
+.. figure:: media/EC20_4G_module007.png
+   :alt: EC20_4G_module007.png
+
+   EC20_4G_module007.png
+
+可能出现的问题
+--------------
+
+经过实测，目前的脚本是可以连接到移动、联通、电信的，如果出现一些其他的问题，可以参考以下内容：
+
+APN设置:
+
+.. code:: bash
+
+    移动：at+cgdcont=1，"ip"，"cmnet"
+    联通：at+cgdcont=1，"ip"，"3gnet"
+    电信：at+cgdcont=1，"ip"，"ctnet"
+
+拨号：
+
+.. code:: bash
+
+    移动：*99***1#或*98*1#
+    联通：*99#电信：#777
+
+使用GPS功能（需要4G模块支持GPS功能）
+------------------------------------
+
+野火在售的4G模块有两个版本，一个是带GPS功能的，一个是不带GPS功能的，具体型号与说明如下：
+
+-  EC20CEHCLG：不带GPS功能的。
+-  EC20CEFILG：带GPS功能的。
+
+.. figure:: media/EC20_4G_module008.png
+   :alt: EC20_4G_module008.png
+
+   EC20_4G_module008.png
+
+**注意，以下的操作必须是带GPS功能版本的4G模块才能使用，请悉知。更重要的是模块需要使用GPS天线，并且天线需要放置在户外，才能正常接收到卫星信号**
+
+本文主要讲解EC20莫块的GPS功能的基本使用方法，更多详细的指令操作细节、参数、示例可参考官网提供的手册：Quectel_EC20_GNSS_AT_Commands_Manual，可以从野火官方git仓库下载： https://github.com/Embedfire/ebf_gsm_ec20 。
+
+EC20挂载系统成功后，在Windows环境下会有四个/dev/ttyUSBx设备文件，也就是我们一开始看到的识别成功4G模块的设备信息，其中ttyUSB2用于AT指令收发，ttyUSB1用于GPS
+NMEA的接收。
+
+主要的指令有以下：
+
++--------------+-------------------------+
+| 指令         | 功能                    |
++==============+=========================+
+| AT+QGPSCFG   | 用于进行GPS功能的配置   |
++--------------+-------------------------+
+| AT+QGPS      | 启动GPS会话             |
++--------------+-------------------------+
+| AT+QGPSEND   | 结束GPS会话             |
++--------------+-------------------------+
+
+以上只列举了简单启用EC20模块GPS功能并获取到NMEA数据所需的AT指令说明，其他功能诸如节能模式、其他定位系统模式、频次控制等操作可通过官网GNSS
+AT指令手册了解。
+
+实现验证:
+
+1. 从 ``/dev/ttyUSB1`` 读取GPS数据，并将其存储到自定义的文件中 ``ec20_gps_data.txt`` ，下面这一行命令就是在后台读取 ``/dev/ttyUSB1`` 设备的数据并存储到 ``ec20_gps_data.txt`` 文件中， ``&``
+   表示后台运行。
+
+.. code:: bash
+
+    cat /dev/ttyUSB1 > ~/ec20_gps_data.txt &
+
+2. 启动GPS会话
+
+.. code:: bash
+
+    echo -e "AT+QGPS=1\r\n" > /dev/ttyUSB2
+
+在启动的时候，可能不会立即收到所有卫星的信号，可以等待一段时间，注意，必须使用GPS天线并且放置在户外，户内可能搜不到信号。
+
+3. 查看GPS信息，直接cat这个 ``ec20_gps_data.txt`` 文件即可。
+
+.. code:: bash
+
+    cat ~/ec20_gps_data.txt
+
+
+    $GPGSV,5,1,18,03,18,246,29,04,41,313,34,08,29,195,34,09,07,320,23*75
+
+    $GPGSV,5,2,18,11,02,194,21,14,28,149,30,21,04,071,30,23,,,23*48
+
+    $GPGSV,5,3,18,27,57,170,49,31,34,077,23,32,05,149,29,16,60,336,*7A
+
+    $GPGSV,5,4,18,18,,,,22,14,222,,26,41,025,,38,,,34*75
+
+    $GPGSV,5,5,18,41,,,34,50,,,48*7B
+
+    $GPGGA,011113.00,2253.723057,N,11350.704943,E,1,07,0.6,46.6,M,-2.0,M,,*4C
+
+    $GPVTG,296.2,T,298.5,M,0.0,N,0.0,K,A*2A
+
+    $GPRMC,011113.00,A,2253.723057,N,11350.704943,E,0.0,296.2,040520,2.4,W,A*27
+
+    $GPGSA,A,2,03,04,08,14,22,27,32,,,,,,0.9,0.6,0.7*35
+
+4. 当数据正常以后，可以关闭GPS会话
+
+.. code:: bash
+
+    echo -e "AT+QGPSEND\r\n" > /dev/ttyUSB2
+
+5. 结束从ttyUSB1读取数据的后台进程
+
+.. code:: bash
+
+    ps -aux | grep ttyUSB1 | awk '{print $2}' | sudo xargs kill -9
+
+6. 使用野火多功能调试助手查看GPS数据信息，首先将数据复制到Windows平台下，放入一个txt文件，比如我就放在桌面的log.txt文件中，然后打开野火多功能调试助手，选择GPS定位功能->解码GPS日志文件->选择你的GPS数据文件，注意，这个GPS数据不要太多，因为定位信息的数据本来就是差不多的，只需要几组即可，否则软件可能卡死。
+
+.. figure:: media/EC20_4G_module009.png
+   :alt: EC20_4G_module009.png
+
+   EC20_4G_module009.png
+
+得到的位置信息如下（地图可以放大缩小）：
+
+.. figure:: media/EC20_4G_module010.png
+   :alt: EC20_4G_module010.png
+
+   EC20_4G_module010.png
+
+获取GPS数据的同时使用4G上网
+---------------------------
+
+由于所有的数据指令都是通过 ``ttyUSB2`` 去控制的，如果你先进行4G拨号上网后，这个 ``ttyUSB2`` 就已经被占用了，无法通过命令去设置企业GPS功能，那么必须按以下步骤才能获取GPS数据的同时使用4G上网。
+
+1. 启动GPS会话。
+2. 进行ppp拨号上网。
+3. 关闭ppp拨号上网。
+4. 关闭GPS会话。
+
+测试：
+
+-  启动GPS会话。
+
+   .. code:: bash
+
+       echo -e "AT+QGPS=1\r\n" > /dev/ttyUSB2
+
+-  查看GPS信息是否正常。
+
+.. code:: bash
+
+    cat /dev/ttyUSB1 
+
+-  进入 ``~/peripheral/ec20-4g`` 目录下，进行ppp拨号上网。
+
+.. code:: bash
+
+    sudo ./ppp-on.sh 
+
+-  查看IP信息是否正常，并且 ``ping`` 一下 ``baidu.com`` ，如果都能成功表示此时可以通过4G模块上网了。
+
+.. code:: bash
+
+    ifconfig
+
+.. code:: bash
+
+    ping baidu.com -I ppp0
+
+-  关闭ppp拨号上网，可以在关闭后再看看IP信息，下面这句命令返回什么信息都不用管。
+
+.. code:: bash
+
+    ps -aux | grep ppp | awk '{print $2}' | sudo xargs kill -9
+
+-  关闭GPS会话。
+
+.. code:: bash
+
+    echo -e "AT+QGPSEND\r\n" > /dev/ttyUSB2
+
+按着以上的步骤操作即可在获取GPS数据的同时使用4G上网。
diff --git a/documentation/linux_basis/editor.rst b/documentation/linux_basis/editor.rst
index db95ac38578f89942fbb960dbfe69b8cb6253736..d9aa6a73968a24386830b4da8ed3b58afd5dbbda 100644
--- a/documentation/linux_basis/editor.rst
+++ b/documentation/linux_basis/editor.rst
@@ -17,51 +17,61 @@ gedit编辑器
 
 gedit是在Ubuntu系统下的地位就如同Windows系统下的记事本软件，它的功能不算强大，但因为是系统自带的，说不上什么时候我们就会图方便使用它用来轻度编辑和记录一些内容。
 
-在图形界面下使用gedit编辑器在前面已经介绍过，此处我们演示下在终端打开该编辑器。在前面的《7.4.5 命令究竟是什么》中提到，命令的本质就是一些应用程序，Ubuntu系统自带的gedit编辑器，我们也可以通过终端来打开：
+在图形界面下使用gedit编辑器在前面已经介绍过，此处我们演示下在终端打开该编辑器。在前面的《8.4.5 命令究竟是什么》中提到，命令的本质就是一些应用程序，Ubuntu系统自带的gedit编辑器，我们也可以通过终端来打开：
 
 gedit 要打开或新建的文件名
 
-|editor002|
 
-图 9‑1 使用命令行打开gedit编辑器
+
+
+.. image:: media/editor002.png
+   :align: center
+   :alt: 未找到图片2|
+
+
 
 为什么要用终端打开gedit？因为在修改系统配置文件时，通常需要管理员权限，而在图形界面下通过gedit打开文件，只能使用当前用户的身份，这种情况下是无法对这些文件进行修改的。但是，如果我们在终端下，使用sudo命令为gedit增加权限来打开这些文件，则可以对它进行修改，在《8.2.2
 修改软件源（命令行）》小节就介绍了这样的方式对/etc/apt/sources.list 文件进行了修改。
 
-执行以下命令可进行对比，使用普通用户权限与sudo权限打开配置文件的差异如图 9‑2和图 9‑3。
+执行以下命令可进行对比，使用普通用户权限与sudo权限打开配置文件的差异如下图所示。
 
 #在后面的说明中，#号表示注释，它后面的内容不要输入到终端中
 
-gedit /etc/apt/sources.list #以普通用户身份打开配置文件
+.. code-block:: sh
+   :linenos:
 
-sudo gedit /etc/apt/sources.list #使用sudo增加权限打开配置文件
+   gedit /etc/apt/sources.list #以普通用户身份打开配置文件
+   sudo gedit /etc/apt/sources.list #使用sudo增加权限打开配置文件
 
-|editor003|
+.. image:: media/editor003.png
+   :align: center
+   :alt: 未找到图片3|
 
-图 9‑2 使用普通用户打开apt配置文件（只读）
 
-|editor004|
+.. image:: media/editor004.png
+   :align: center
+   :alt: 未找到图片4|
+
 
-图 9‑3使用sudo权限通过gedit打开apt配置文件（可读写）
 
 总而言之，当我们使用有图形界面的Ubuntu桌面版进行开发时，使用sudo gedit的方式修改配置文件是一个非常好的选择。
 
 Linux新手在配置开发环境时，对Linux本来就不熟悉，刚学习配置开发环境时一般又一头雾水，再加上网上的教程一般是使用Vim来修改配置文件，新手照着敲命令使用Vim编辑器来改内容，经过Vim的一番操作后，直接就劝退了，我们从此损失了一位未来的技术大牛。
 
-在网上以及我们后面的各种修改配置文件的命令中，默认都是使用Vi/Vim来修改，因为系统一般自带Vi，而且不需要区分系统是否需要使用图形界面。但是对于刚学习Linux的用户，能不用Vim就不去用，在使用带图形界面的Ubuntu时，看到命令中的vim时心里就默认把命令中的“vim”替换成“gedit”即
+在网上以及我们后面的各种修改配置文件的命令中，默认都是使用Vi/Vim来修改，因为系统一般自带Vi，而且不需要区分系统是否需要使用图形界面。但是对于刚学习Linux的用户，能不用Vim就不去用，在使用带图形界面的Ubuntu时，看到命令中的vim时心里就默认把命令中的"vim"替换成"gedit"即
 可。
 
 例如：
 
-#使用sudo权限通过vim打开文件
-
-sudo vim /etc/apt/sources.list
+.. code-block:: sh
+   :linenos:
 
-#使用sudo权限通过gedit打开文件
+   #使用sudo权限通过vim打开文件
+   sudo vim /etc/apt/sources.list
+   #使用sudo权限通过gedit打开文件
+   sudo gedit /etc/apt/sources.list
 
-sudo gedit /etc/apt/sources.list
-
-以上命令区别仅为“vim”和“gedit”，即使是Vim编辑器同样也是需要sudo权限才能对文件进行编辑的，如果不使用sudo，以普通用户的身份使用Vim编辑器打开配置文件，同样也是只有“只读”权限。所以，千万不要把Vi/Vim编辑器神圣化了。
+以上命令区别仅为"vim"和"gedit"，即使是Vim编辑器同样也是需要sudo权限才能对文件进行编辑的，如果不使用sudo，以普通用户的身份使用Vim编辑器打开配置文件，同样也是只有"只读"权限。所以，千万不要把Vi/Vim编辑器神圣化了。
 
 VS Code编辑器
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
@@ -71,7 +81,7 @@ VS Code是微软制作的开源编辑器，跨Windows、Linux及iOS平台都有
 下载安装
 ^^^^^^^^^^^^^^^^^^^^^^^^
 
-在Ubuntu自带的软件中心可以找到VS Code软件，通过搜索“vscode”即可安装，但目前Ubunut采用Snap软件市场来安装软件，暂时还没有国内的镜像下载源，所以下载可能需要花比较长的时间。
+在Ubuntu自带的软件中心可以找到VS Code软件，通过搜索"vscode"即可安装，但目前Ubunut采用Snap软件市场来安装软件，暂时还没有国内的镜像下载源，所以下载可能需要花比较长的时间。
 
 我们推荐直接在Ubuntu下使用浏览器在VS Code官网下载deb包进行安装，顺便学习deb包的安装方法。
 
@@ -79,65 +89,85 @@ VS Code官网地址：\ https://code.visualstudio.com/
 
 VS Code 的安装步骤如下：
 
-(1) 到官网找到下载的选项，可看到Linux平台下分deb和rpm安装包，Debian和Ubuntu系统都是用deb包，如图 9‑4。
+(1) 到官网找到下载的选项，可看到Linux平台下分deb和rpm安装包，Debian和Ubuntu系统都是用deb包，如下图所示。
+
+.. image:: media/editor005.png
+   :align: center
+   :alt: 未找到图片5|
 
-|editor005|
 
-图 9‑4 下载deb安装包
 
-(2) 下载后可以在浏览器中打开下载目录，默认的目录一般为用户家目录下的“/home/下载”。
+(2) 下载后可以在浏览器中打开下载目录，默认的目录一般为用户家目录下的"/home/下载"。
+
+.. image:: media/editor006.png
+   :align: center
+   :alt: 未找到图片6|
 
-|editor006|
 
-   图 9‑5 下载目录
 
    找到下载好的deb包，直接双击即可安装。
 
-|editor007|
+.. image:: media/editor007.png
+   :align: center
+   :alt: 未找到图片7|
+
 
-图 9‑6 打开下载目录直接双击安装
 
-|editor008|
+.. image:: media/editor008.png
+   :align: center
+   :alt: 未找到图片8|
+
 
-图 9‑7 直接安装
 
 (3) 如果想体验命令行安装deb包，可以使用以下命令：
 
-sudo dpkg -i 安装包的名字
+.. code-block:: sh
+   :linenos:
+
+   sudo dpkg -i 安装包的名字
 
-使用命令行安装过程如图 9‑8。
+使用命令行安装过程如下图所示。
 
-|editor009|
+.. image:: media/editor009.png
+   :align: center
+   :alt: 未找到图片9|
 
-图 9‑8 使用命令行安装deb包
 
-(4) 安装完成后，可以通过“显示应用程序“中打开，如图 9‑9。
 
-..
+(4) 安装完成后，可以通过"显示应用程序"中打开，如下图所示。
 
-   |editor010|
 
-图 9‑9 显示应用程序中的VS Code
+.. image:: media/editor010.png
+   :align: center
+   :alt: 未找到图片10|
 
-也可以通过终端打开，在终端下VS Code的打开命令为“code”：
+
+
+也可以通过终端打开，在终端下VS Code的打开命令为"code"：
 
 code
 
 输入命令回车后稍等一会即可。
 
-|editor011|
+.. image:: media/editor011.png
+   :align: center
+   :alt: 未找到图片11|
 
-图 9‑10 打开VS Code
 
 (5) 类似地，如果希望用VS Code修改配置文件，使用sudo命令增加权限即可：
 
-sudo code 文件名 --user-data-dir
+.. code-block:: sh
+   :linenos:
+
+   sudo code 文件名 --user-data-dir
+
+其中的"--user-data-dir"参数是VS Code提示要输入的，如下图所示。
 
-其中的“--user-data-dir”参数是VS Code提示要输入的，如图 9‑11。
+.. image:: media/editor012.png
+   :align: center
+   :alt: 未找到图片12|
 
-|editor012|
 
-图 9‑11 VS Code使用sudo权限打开文件
 
 添加插件
 ^^^^^^^^^^^^^^^^^^^^^^^^
@@ -147,29 +177,36 @@ VS Code的强大之处在于它的插件，刚开始的时候我们安装中文
 中文支持
 ''''''''''''''''''''''''''''
 
-点击VS Code界面左侧的“插件图标”，在输入框中输入“chinese”后搜索，可以找到插件“Language pack extension for Chinese (Simplified)”，点击插件下的install按钮即可安装。
+点击VS Code界面左侧的"插件图标"，在输入框中输入"chinese"后搜索，可以找到插件"Language pack extension for Chinese (Simplified)"，点击插件下的install按钮即可安装。
 
-|editor013|
+.. image:: media/editor013.png
+   :align: center
+   :alt: 未找到图片13|
 
-图 9‑12 中文插件
 
-安装插件后一般需要重启VS Code才能生效，平时界面的右下角通常也会有各种提示，如图 9‑13。
 
-|editor014|
+安装插件后一般需要重启VS Code才能生效，平时界面的右下角通常也会有各种提示，如下图所示。
+
+.. image:: media/editor014.png
+   :align: center
+   :alt: 未找到图片14|
+
 
-图 9‑13 重启VS Code以使插件生效
 
 C/C++插件
 '''''''''''''''''''''''''''''''''''
 
-VS Code本身就支持C/C++的语法高亮，但并不支持编译、运行、调试等功能，通过安装“C/C++”插件可扩展相应的功能。在插件安装栏中输入“c”即可搜索到“C/C++”插件，直接安装，如图 9‑14。
+VS Code本身就支持C/C++的语法高亮，但并不支持编译、运行、调试等功能，通过安装"C/C++"插件可扩展相应
+的功能。在插件安装栏中输入"c"即可搜索到"C/C++"插件，直接安装，如下图所示。
+
+.. image:: media/editor015.png
+   :align: center
+   :alt: 未找到图片15|
 
-|editor015|
 
-图 9‑14 C/C++插件
 
 Vi/Vim编辑器
-~~~~~~~~~
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
 前面已多次提到Vi/Vim编辑器，大部分Linux系统中都会自带Vi编辑器已方便用户在终端上编辑文件，而Vim是Vi的升级版本，它在Vi的基础上改进和增加了很多特性，是一个功能更强大、高度可定制的文本编辑器。如支持代码折叠、插件、多国语言支持、垂直分割视窗、拼字检查、上下文相关补完，标签页编辑等功能
 。热爱Vim编辑器的用户，能把它玩出花来，甚至直接把它打造成IDE。
@@ -177,80 +214,91 @@ Vi/Vim编辑器
 在对Linux服务器进行运维或控制嵌入式开发板的时候，绝大部分情况下我们只能使用终端，而在终端编辑文件时使用Vi/Vim编辑器几乎是最好的选择，所以即使它上手不易，但我们也绝不能逃避学习。对新手来说，要求能熟练使用Vi/Vim编辑器对文件进行基本的读写修改。
 
 Vim使用演示
-^^^^^^^
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 
 安装Vim
-'''''
+''''''''''''''''''''''''''''''
 
 在Ubuntu下，使用apt可安装Vim编辑器，执行如下命令安装：
 
-sudo apt install vim
+.. code-block:: sh
+   :linenos:
+
+   sudo apt install vim
 
 打开Vi/Vim
-''''''''
+''''''''''''''''''''''''''''''''
 
 安装后使用vi或vim命令都可以打开，它们的基础使用方法是一样的：
 
-vi #若系统安装了vim，该命令会自动打开vim软件
+.. code-block:: sh
+   :linenos:
 
-vim #打开vim软件
+   vi #若系统安装了vim，该命令会自动打开vim软件
+   vim #打开vim软件
 
 也可以使用如下命令创建或打开文件：
 
-vi 文件名 #若文件存在则打开，文件不存在则创建
+.. code-block:: sh
+   :linenos:
 
-vim 文件名
+   vi 文件名 #若文件存在则打开，文件不存在则创建
+   vim 文件名
 
 退出Vim
-'''''
+'''''''''''''''''''''''''
 
 由于Vim是在终端下使用，没有图形界面的，所以对它的所有控制都只能通过命令来实现，包括退出。对于新手来说如何退出Vim都是个问题。
 
-我们通过退出Vim的步骤来体验Vim的“一般模式”和“命令行模式”。
+我们通过退出Vim的步骤来体验Vim的"一般模式"和"命令行模式"。
 
 打开Vim后，请按如下步骤进行操作，注意若开启了输入法，要先把输入法设置成英文：
 
-(1) 按下退出键“Esc”，Vim会进入到“一般模式”。
+(1) 按下退出键"Esc"，Vim会进入到"一般模式"。
 
-(2) 输入英文冒号“:”，Vim会进入到“命令行模式”。
+(2) 输入英文冒号":"，Vim会进入到"命令行模式"。
 
-(3) 输入强制退出命令“q!”，即字母“q”及英文叹号“!”。
+(3) 输入强制退出命令"q!"，即字母"q"及英文叹号"!"。
 
 (4) 按回车执行命令，会退出Vim，返回到终端。
 
-执行时终端显示的内容如图 9‑15。
+执行时终端显示的内容如下图所示。
+
+.. image:: media/editor016.jpg
+   :align: center
+   :alt: 未找到图片16|
 
-|editor016|
 
-图 9‑15 退出Vim的步骤
 
 输入内容
-''''
+''''''''''''''''''''
 
-初次使用Vim时，想要在编辑器输入内容也并非易事， Vim打开后默认是在“一般模式”的，键盘的输入都会被当成一般命令而不是文本的内容，即在该模式下的所有输入就如同在其它常用编辑器中按了快捷键。运气好按了进入“插入模式”的快捷键，后续的输入才会被当成文本内容。
+初次使用Vim时，想要在编辑器输入内容也并非易事， Vim打开后默认是在"一般模式"的，键盘的输入都会被当成一般命令而不是文本的内容，即在该模式下的所有输入就如同在其它常用编辑器中按了快捷键。运气好按了进入"插入模式"的快捷键，后续的输入才会被当成文本内容。
 
-可通过以下步骤进入到“插入模式”输入内容并保存文件：
+可通过以下步骤进入到"插入模式"输入内容并保存文件：
 
-(1) 按下退出键“Esc”进入“一般模式”。
+(1) 按下退出键"Esc"进入"一般模式"。
 
-(2) 输入一般命令“i”，即直接按字母“i”，进入“插入模式”，如图 9‑16。
+(2) 输入一般命令"i"，即直接按字母"i"，进入"插入模式"，如下图所示。
 
 (3) 随意输入一些内容。
 
-(4) 按下退出键“Esc”再次进入“一般模式”。
+(4) 按下退出键"Esc"再次进入"一般模式"。
 
-(5) 输入英文冒号“:”，Vim会进入到“命令行”模式。
+(5) 输入英文冒号":"，Vim会进入到"命令行"模式。
 
-(6) 输入保存退出命令“wq”。
+(6) 输入保存退出命令"wq"。
 
 (7) 按回车执行命令，会退出Vim，返回到终端。
 
-|editor017|
+.. image:: media/editor017.jpg
+   :align: center
+   :alt: 未找到图片17|
+
 
-图 9‑16 Vim的插入模式
 
 Vim的三种模式
-^^^^^^^^
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 
 经过以上的使用演示，我们体验到了Vim编辑器的三种工作模式：
 
@@ -260,26 +308,28 @@ Vim的三种模式
 
 -  命令行模式（command-line mode）：命令行模式支持保存、退出、替换等命令，以及Vim的高级功能。
 
-我们在使用Vim时，常常会在这三种模式之间进行切换，切换方式可以参考图 9‑17。
+我们在使用Vim时，常常会在这三种模式之间进行切换，切换方式可以参考下图。
 
-|editor018|
+.. image:: media/editor018.png
+   :align: center
+   :alt: 未找到图片18|
 
-图 9‑17 Vim模式切换
 
-图 9‑17的意义就是：
 
--  在任意模式下，我们可以通过按键“Esc”进入到一般模式。
+上图的意义就是：
 
--  在一般模式下，通过按键“a” “i” “o” “O” “r” “R”等可进入到插入模式。
+-  在任意模式下，我们可以通过按键"Esc"进入到一般模式。
 
--  在一般模式下，通过按键“:”可进入到命令行模式。
+-  在一般模式下，通过按键"a" "i" "o" "O" "r" "R"等可进入到插入模式。
+
+-  在一般模式下，通过按键":"可进入到命令行模式。
 
 插入模式
-^^^^
+^^^^^^^^^^^^^^^^^^^^
 
-Vim提供多个快捷键来从一般模式进入插入模式，见表格 9‑1。进入插入模式之后，就可以正常地编辑文本了，使用方向键来移动光标，回车键进行换行，操作方式与Windows记事本没有什么区别。
+Vim提供多个快捷键来从一般模式进入插入模式，见下表。进入插入模式之后，就可以正常地编辑文本了，使用方向键来移动光标，回车键进行换行，操作方式与Windows记事本没有什么区别。
 
-表格 9‑1 进入/退出插入模式的快捷键
+表 进入/退出插入模式的快捷键
 
 ====== ===================================================
 快捷键 功能描述
@@ -288,16 +338,16 @@ i      在当前光标所在位置插入文本
 a      在当前光标所在位置的下一个字符插入文本
 o      在光标所在位置后插入新行
 r      替换当前光标所在位置的字符
-R      可以替换当前光标所在位置之后的字符，按下“Esc”则退出
+R      可以替换当前光标所在位置之后的字符，按下"Esc"则退出
 ESC    退出插入模式
 ====== ===================================================
 
 一般模式
-^^^^
+^^^^^^^^^^^^^^^^^^^^
 
-在任意模式下按按键“Esc”可进入到一般模式。表格 9‑2列出了一般模式下常用的快捷键。在一般模式下，可以进行复制，粘贴，删除，查找替换某个关键字等。
+在任意模式下按按键"Esc"可进入到一般模式。下表列出了一般模式下常用的快捷键。在一般模式下，可以进行复制，粘贴，删除，查找替换某个关键字等。
 
-表格 9‑2 一般模式快捷键
+表  一般模式快捷键
 
 ====================== ==================== ===============================================================================================================================
 \                      快捷键               功能描述
@@ -330,11 +380,11 @@ ESC    退出插入模式
 ====================== ==================== ===============================================================================================================================
 
 命令行模式
-^^^^^
+^^^^^^^^^^^^^^^^^^^^^^^^^
 
-在一般命令模式下，按下键盘的冒号键“:”，就可以进入命令行模式，继续输入要执行的命令按回车即可执行。
+在一般命令模式下，按下键盘的冒号键":"，就可以进入命令行模式，继续输入要执行的命令按回车即可执行。
 
-表格 9‑3 命令行模式快捷键
+表  命令行模式快捷键
 
 ============ ==================================================
 快捷键       功能描述
@@ -352,33 +402,52 @@ set hlsearch 搜索结果高亮显示
 ============ ==================================================
 
 用Vi/Vim软件编写简单的sh脚本
-^^^^^^^^^^^^^^^^^^
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 
 到此为止，Vim的基本操作就介绍完了，最后我们尝试用Vim编写一个输出hello world的脚本，熟悉Vim的操作。
 
 在终端中执行行下列命令：
 
-vim hello_world.sh
+.. code-block:: sh
+   :linenos:
+
+   vim hello_world.sh
 
-然后进入插入模式（在一般模式下按“i”键），输入下列代码后，保存文件并退出（退出插入模式，进入命令行模式后，输入wq并回车），注意以下内容全为英文符号。
+然后进入插入模式（在一般模式下按"i"键），输入下列代码后，保存文
+件并退出（退出插入模式，进入命令行模式后，输入wq并回车），注意以下内
+容全为英文符号。
 
-echo "helloworld,this is a script test!"
+.. code-block:: sh
+   :linenos:
+
+   echo "helloworld,this is a script test!"
 
 此脚本文件中的echo命令的作用是将其后面的文本内容直接输出到终端上。
 
-|editor019|
+.. image:: media/editor019.png
+   :align: center
+   :alt: 未找到图片19|
+
 
-图 9‑18 输入脚本内容并保存退出
 
 Vim退出后回到终端，通过source命令运行刚刚编写的脚本文件：
 
-source hello_world.sh
+.. code-block:: sh
+   :linenos:
+
+   source hello_world.sh
+
+可以看到终端会输出"helloworld,this is a script test!"字样。
+
+.. image:: media/editor020.png
+   :align: center
+   :alt: 未找到图片20|
+
+
+
 
-可以看到终端会输出“helloworld,this is a script test!”字样。
 
-|editor020|
 
-图 9‑19执行脚本
 
 .. |editor002| image:: media/editor002.png
    :width: 5.67949in
diff --git a/documentation/linux_basis/fire-config_brief.rst b/documentation/linux_basis/fire-config_brief.rst
new file mode 100644
index 0000000000000000000000000000000000000000..09cf70e3256dae9af223f01c8050ffd56b7a0f26
--- /dev/null
+++ b/documentation/linux_basis/fire-config_brief.rst
@@ -0,0 +1,528 @@
+.. vim: syntax=rst
+
+fire-config工具简介
+-------------------
+
+**注意:该工具专用于野火新发布的Debian系统镜像,不适合用于野火旧版本镜像和其他任何的Linux系统上，望知悉!**  
+（新版Debian镜像的下载和烧录方法详见《SD卡烧录Debian镜像》章节）。
+
+fire-config是野火IMX-6ULL开发板自带的一个系统配置工具，
+通过串口终端或远程终端可以方便地使用它来进行系统功能的使能或禁止。
+
+
+使用方法
+~~~~~~~~~~~~~~~~~~~~~
+
+在登录系统以后，如果要使用fire-config工具，只需要运行以下命令
+
+.. code-block:: sh
+   :emphasize-lines: 2
+   :linenos:
+
+   sudo fire-config
+
+   注意:由于该工具会改变一系列不属于当前用户的文件，sudo是必须要加的。
+
+执行指令后，在终端的显示界面如下:
+
+.. image:: media/fire-config.png
+   :align: center
+   :alt: fire-config工具
+
+串口终端界面
+
+
+.. image:: media/fire-config1.png
+   :align: center
+   :alt: fire-config工具
+
+ssh远程终端界面
+
+
+菜单选择和移动
+~~~~~~~~~~~~~~~~~~~~~
+
+在该菜单中，使用up和down箭头键可以在不同的选项中切换，被选中的一项将会高亮显示，
+使用right箭头键将跳出"选项"，并跳转到<Select>和<Finish>按钮。按下left将使您返回选项。
+<Select>按钮表示该项被选中，<Finish>按钮表示已完成全部配置项。
+
+
+fire-config机制
+~~~~~~~~~~~~~~~~~~~~~
+一般而言，fire-config旨在提供一些常见的系统功能配置服务，在进行配置过程中，
+这可能会导致/boot/uEnv.txt或者是其他各种标准的linux配置文件被自动更改了，
+某些选项需要重启才能生效，如果您修改了其中一个，fire-config 会在<Finish>
+按钮被选择时，询问您是否要立即重启，如果您希望配置马上生效，确定重启系统即可。
+
+Device Tree Overlays
+~~~~~~~~~~~~~~~~~~~~~
+
+fire-config工具集成了Device Tree Overlays机制，用来管理一些硬件资源的分配和模块的加载，
+从而缓解多个驱动程序争用系统资源的问题。
+
+在传统开发模式中，这个机制通常是由设备树来完成的：在开发之前根据项目需求，
+提前确定系统中所有用到的硬件设备。在设备树中把所有的外围设备信息以设备树特定的语法进行描述，
+在设备树被编译为dtb文件后，被linux内核加载使用。
+
+可以看到，在传统开发过程，一旦硬件资源发生变化，就要重新修改、编译、下载设备树。比较极端的情况是:
+当项目中要支持多种的硬件模块，而不同模块间往往会共用某些系统资源(如IO引脚)。
+一旦系统要兼容模块任意组合使用，那么随着模块数量增加，需要编译的设备树数量将爆炸增长。
+
+因此，使用传统设备树是不利于项目的维护和扩展的。内核为了解决这个提出了一套新的解决方案，
+那就是Device Tree Overlays，中文上可理解为"设备树插件"。
+它的核心原理是，通过扩展传统的设备树语法，使得各个硬件模块的信息可以独立地用新的设备树语法来描述。
+这样一来，传统的主设备树中只需要保留最基础的硬件信息(主要是cpu和内存)，其他模块单独编译成"设备树插件"。
+在系统实际使用时，根据实际应用情景，需要用到哪些硬件模块就把对应的设备树插件加入到主设备树即可。
+
+如下为实际内存中设备树的示意图:
+
+.. image:: media/device_tree_overlays.png
+   :align: center
+   :alt: 设备树示意图
+
+"设备树插件"无疑提高了系统的可维护性和减少了大量的重复工作，目前，
+我们已经把常见的硬件模块都编译成了"设备树插件",比如LCD、HDMI、WiFi等等。
+用户可以通过fire-config工具轻松地实现对硬件模块的便捷管理。
+
+
+
+fire-config功能项
+~~~~~~~~~~~~~~
+
+IIC_1
+^^^^
+
+使能或者禁止IIC 1接口
+
+IIC_2
+^^^^
+
+使能或者禁止IIC 2接口
+
+74HC595
+^^^^
+
+使能或者禁止74HC595位移缓存器接口
+
+LED
+^^^^
+
+使能或者禁止LED灯
+
+KEY
+^^^^
+
+使能或者禁止独立按键
+
+18b20
+^^^^^^^^
+
+使能或者禁止18b20温度传感器
+
+HDMI
+^^^^^^^^
+
+使能或者禁止HDMI显示器
+
+CAMERA
+^^^^^^^^
+
+使能或者禁止摄像头模块
+
+SOUND
+^^^^^^^^
+
+使能或者禁止声卡模块
+
+LCD5
+^^^^^^^^
+
+使能或者禁止5寸触摸屏
+
+LCD4.3
+^^^^^^^^
+
+使能或者禁止4.3寸触摸屏
+
+485r1
+^^^^^^^^
+
+使能或者禁止第一路485串口
+
+485r2
+^^^^^^^^
+
+使能或者禁止第二路485串口
+
+ADC1
+^^^^^^^^
+
+使能或者禁止第一路ADC采样
+
+CAN1
+^^^^^^^^
+
+使能或者禁止第一路CAN通信
+
+CAN2
+^^^^^^^^
+
+使能或者禁止第二路CAN通信
+
+dht11
+^^^^^^^^
+
+使能或者禁止dht11温湿度传感器
+
+ecspi3
+^^^^^^^^
+
+使能或者禁止spi通信
+
+uart3
+^^^^^^^^
+
+使能或者禁止第三路串口通信
+
+wifi
+^^^^^^
+
+使能wifi接口。wifi与sd卡共用一个sdio接口，两者不能同时使用
+
+wifi_scan
+^^^^^^^^^^^^
+
+扫描并显示当前存在的wifi网络
+
+wifi_setting
+^^^^^^^^^^^^^^^
+
+设置目标wifi的账号与密码
+
+SSH_connect
+^^^^^^^^^^^^^^^^
+
+远程登录会话
+
+
+flasher
+^^^^^^^^^^^^^^^^^^
+
+使能或者禁止SD卡刷机，用于将SD卡的系统固件烧录到eMMC或者nandflash
+
+Expand Filesystem
+^^^^^^^^^^^^^^^^^^
+
+扩展SD卡容量，解决SD卡镜像烧录完毕后，出现储存容量大幅减小的问题
+
+
+fire-config设置ssh
+~~~~~~~~~~~~~~~~~~~~~~
+
+1、上电启动开发板，开发板默认开启ssh服务。系统正常登录后，输入以下命令查看ssh服务是否已经运行：
+
+.. code-block:: sh
+   :emphasize-lines: 2
+   :linenos:
+
+   sudo systemctl status ssh
+
+如下图所示:active状态说明ssh服务正常运行
+
+.. image:: media/fire-config_ssh.png
+   :align: center
+   :alt: 查看ssh服务是否运行
+
+2、确保网络连接正常(注意wifi要先正确配置后才能使用)。输入以下命令查看当前主机的ip地址:
+
+.. code-block:: sh
+   :emphasize-lines: 2
+   :linenos:
+
+   ifconfig
+
+以太网ip地址如下图所示:
+
+.. image:: media/fire-config_ssh1.png
+   :align: center
+   :alt: 查看以太网ip地址
+
+正确配置wifi后，wifi的ip地址如下图所示:
+
+.. image:: media/fire-config_ssh2.png
+   :align: center
+   :alt: 查看wifi ip地址
+
+3、使用ssh客户端登录，这里使用vscode的Remote-SSH插件为例。
+vscode安装完Remote-SSH插件后，使用"ctrl+shift+P"快捷键打开命令面板，
+输入"Remote-SSH"迅速找到"Remote-ssh: connect to host"选项，
+如下图所示:
+
+.. image:: media/fire-config_ssh3.png
+   :align: center
+   :alt: Remote-SSH插件
+
+4、进一步选择"Add New SSH Host"选项，如下图
+
+.. image:: media/fire-config_ssh4.png
+   :align: center
+   :alt: Remote-SSH插件
+
+5、根据开发板的ip地址，在ssh登录框中输入登录命令，
+这里以本人实际开发环境中的以太网IP地址为例。
+
+.. image:: media/fire-config_ssh5.png
+   :align: center
+   :alt: Remote-SSH插件
+
+6、选择配置文件来保存主机ip和用户名，一般选择用户名下的config进行配置即可，
+如下图所示:
+
+.. image:: media/fire-config_ssh6.png
+   :align: center
+   :alt: Remote-SSH插件
+
+7、提示检查主机公钥指纹，选择"continue",如下图:
+
+.. image:: media/fire-config_ssh7.png
+   :align: center
+   :alt: Remote-SSH插件
+
+8、输入主机用户的密码，debian用户默认密码为"temppwd"。
+如果弹出登录失败串口，点击"retry"选项，重复登录2~3次。
+
+.. image:: media/fire-config_ssh8.png
+   :align: center
+   :alt: Remote-SSH插件
+
+9、登录成功后，在菜单栏打开"Terminal"选项，新建一个终端。
+如下图:
+
+.. image:: media/fire-config_ssh9.png
+   :align: center
+   :alt: Remote-SSH插件
+
+10、输入"sudo fire-config"命令，选择"SSH-connect"项。
+如下图:
+
+.. image:: media/fire-config_ssh10.png
+   :align: center
+   :alt: Remote-SSH插件
+
+11、系统提示: "Would you like the SSH server to be enabled?"。选择<Yes>或<No>来
+分别对ssh进行使能和禁止即可。
+如下图:
+
+.. image:: media/fire-config_ssh11.png
+   :align: center
+   :alt: Remote-SSH插件
+
+
+fire-config使能硬件模块
+~~~~~~~~~~~~~~~~~~~~~~
+
+1、开发板正常启动后，执行sudo fire-config，这里以"LED"外设为例，选择"LED"项。
+其他硬件模块的使能方法与"LED"类似。
+
+如下图:
+
+.. image:: media/fire-config_led.png
+   :align: center
+   :alt: 使能LED
+
+2、系统提示: "Would you like the led to be enabled?"，选择<Yes>项。
+
+如下图:
+
+.. image:: media/fire-config_led.png
+   :align: center
+   :alt: 使能LED
+
+3、系统提示: "The flasher is enabled"，选择<OK>项，返回主界面。
+
+如下图:
+
+.. image:: media/fire-config_led.png
+   :align: center
+   :alt: 使能LED
+
+4、在初始界面,选择<Finish>项。系统默认使能"LED"外设，因此不会提示重启。
+
+注意:**如果系统的外设本来已经是使能状态，那么此时会直接退出fire-config工具；
+如果系统的外设原本是禁止状态，在设置为使能状态后，系统会提示重启:"Would you like to reboot now?",
+选择<Yes>项，等系统重启后，相关外设已经被使能**。
+
+
+
+fire-config刷机
+~~~~~~~~~~~~~~
+
+注意:
+**刷机不建议用ssh远程登录来操作，避免开发板重启后，
+ssh断开连接而不能及时看到相关的刷机信息提示**。
+
+1、开发板正常启动后，在串口终端登录debian系统。
+
+.. code-block:: sh
+   :emphasize-lines: 2
+   :linenos:
+
+   账户:debian
+   密码:temppwd
+
+系统正常登录界面如下所示:
+
+.. image:: media/debian_login.png
+   :align: center
+   :alt: 登录debian系统
+
+
+2、执行sudo fire-config，选择"flasher"项。
+
+如下图所示:
+
+.. image:: media/fire-config_flasher.png
+   :align: center
+   :alt: fire-config刷机
+
+
+3、系统提示: "Would you like the flasher to be enabled?"，选择<Yes>。
+
+如下图所示:
+
+.. image:: media/fire-config_flasher1.png
+   :align: center
+   :alt: fire-config刷机
+
+3、系统提示: "The flasher is enabled"，选择<OK>。
+
+如下图所示:
+
+.. image:: media/fire-config_flasher2.png
+   :align: center
+   :alt: fire-config刷机
+
+4、返回fire-config初始界面,选择<Finish>。
+
+如下图所示:
+
+.. image:: media/fire-config_flasher3.png
+   :align: center
+   :alt: fire-config刷机
+
+5、系统提示:"Would you like to reboot now?"，选择<Yes>。
+
+如下图所示:
+
+.. image:: media/fire-config_flasher4.png
+   :align: center
+   :alt: fire-config刷机
+
+6、系统自动重启。
+
+如下图所示:
+
+.. image:: media/fire-config_flasher5.png
+   :align: center
+   :alt: fire-config刷机
+
+7、重启后的系统将自动进行eMMC或者nandflash刷机。
+
+如下图所示(以eMMC刷机为例):
+
+.. image:: media/fire-config_flasher6.png
+   :align: center
+   :alt: fire-config刷机
+
+8、耐心等待刷机结束，刷机过程大约持续2分30秒左右。刷机完成后，控制台会重新进入串口登录页面，
+此时观察开发板的LED灯，如果LED在持续闪烁，说明刷机成功。
+
+如下图所示
+
+.. image:: media/fire-config_flasher7.png
+   :align: center
+   :alt: fire-config刷机
+
+9、无论是eMMC，还是nandflash，刷机成功后，调整拨码开关为相应启动方式，重新上电启动系统即可。
+
+**注意**:sd卡配置一次之后，将不需要再重复配置，可以持续给内部flash烧录，非常适合给产线的工人使用，专门为产线工人量产而生。
+
+
+fire-config连接wifi
+~~~~~~~~~~~~~~
+
+wifi配置前提
+^^^^^^^^^^^^^
+
+- wifi与sd卡共用同一个sdio接口，进行配置wifi之前，要先通过fire-config工具来刷机。
+  确认开发板可以正常从nandflash或者eMMC启动后，才能进行wifi的配置连接。
+
+- 刷机步骤完成后，修改跳线帽为下图中连接方式，确保wifi模块连接在该sdio接口上。
+
+.. image:: media/fire-config_wifi.png
+   :align: center
+   :alt: fire-config刷机
+
+wifi连接步骤
+^^^^^^^^^^^^^
+
+1、在终端执行sudo fire-config命令，选择"wifi"项。
+如下图:
+
+.. image:: media/fire-config_wifi1.png
+   :align: center
+   :alt: fire-config配置wifi
+
+2、系统提示:"Would you like the wifi interface to be enabled?",选择<yes>项，表示使能wifi模块。
+
+.. image:: media/fire-config_wifi2.png
+   :align: center
+   :alt: fire-config配置wifi
+
+3、系统提示:"The wifi interface is enabled"，选择<ok>项返回主菜单。
+
+.. image:: media/fire-config_wifi3.png
+   :align: center
+   :alt: fire-config配置wifi
+
+4、在主菜单选择<Finish>项，系统会提示重启：
+"Would you like to reboot now?",选择<Yes>项，等待系统重启。
+此时wifi模块驱动和wifi自动连接服务已经配置完成。
+
+.. image:: media/fire-config_wifi4.png
+   :align: center
+   :alt: fire-config配置wifi
+
+5、系统重启后，继续在系统中执行sudo fire-config命令，选择"wifi_scan"项，
+系统会扫描搜索所有周围的无线网络，并在界面显示wifi的名字和信号强弱.如果暂时没有识别到wifi，多尝试几次扫描。
+如下图:
+
+.. image:: media/fire-config_wifi5.png
+   :align: center
+   :alt: fire-config配置wifi
+
+6、确保系统搜索到目标wifi后，选择<ok>项返回主菜单，选择"wifi_setting"项。
+如下图:
+
+.. image:: media/fire-config_wifi6.png
+   :align: center
+   :alt: fire-config配置wifi
+
+7、输入目标wifi的账号，输入完成后选择<oK>项。
+
+.. image:: media/fire-config_wifi7.png
+   :align: center
+   :alt: fire-config配置wifi
+
+8、继续输入目标wifi的密码，输入完成后选择<ok>项返回主菜单。
+
+.. image:: media/fire-config_wifi8.png
+   :align: center
+   :alt: fire-config配置wifi
+
+9、选择主菜单<Finsh>项，退出fire-config工具。
+执行ifconfig命令，可以看到开发板wifi的ip地址已经分配成功。
+
+.. image:: media/fire-config_wifi9.png
+   :align: center
+   :alt: fire-config配置wifi
\ No newline at end of file
diff --git a/documentation/linux_basis/git_tutorial.rst b/documentation/linux_basis/git_tutorial.rst
new file mode 100644
index 0000000000000000000000000000000000000000..6e5115c7d0b683146c0878329a70073c4bcb93f5
--- /dev/null
+++ b/documentation/linux_basis/git_tutorial.rst
@@ -0,0 +1,500 @@
+.. vim: syntax=rst
+
+Git教程
+------------------
+
+Git是一个功能十分强大的分布式版本控制系统，主要用于有效、高速地对各种各样的项目进行版本管理。
+
+Git的诞生，起源于linux社区的一位大牛Andrew(samba之父)写了可连接BitKeeper仓库的外挂，
+这引起了BitMover 公司的震怒，收回了对linux社区免费使用BitKeeper的授权。于是Linux之父，
+Torvalds，花了十天时间为Linux社区开发了新的版本工具--Git。
+
+Git的特点
+~~~~~~~~~~~~~~~~~~
+
+相较于其他版本管理工具，Git有以下几个优点:
+
+- 快照记录。git和其他版本管理工具重要差别在于存储数据的方式。
+  其他版本工具通常将它们保存的信息看作是一种原始数据+文件修改的记录。
+  而Git在储存时是生成快照来记录全部文件（快照不是所有文件的单纯拷贝，而是一种对全体文件的索引）。
+
+- 分布式。每一位项目开发人员的电脑里，都有项目的完成备份，避免造成资料受损无法挽回的后果。
+  同时，本地的项目备份使得所有的版本管理操作都在毫秒级别内完成。
+  这与SVN、CVS等集中式版本工具时常要等待中央服务器响应相比,用户体验显得非常好。
+
+- 开源。这与linux内核一样，开放源码保证了Git的可靠性和安全性，也有利于Git的功能越来越强大。
+
+
+Git的学习层次
+~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+每一个Git的学习者，在遇上Git复杂繁多的命令时，都难免心里发怵。客观来说，Git确实不及SVN那么简单好用，
+新手要用Git好不容易。但是换个角度看，若是我们能熟练掌握Git，体验到其中的奥妙，
+会发现自己再也不愿意回到SVN的怀抱了。
+
+王国维在<<人间词话>>里说:欢古今之成大事业、大学问者，必经过三种之境界:"昨夜西风凋碧树。
+独上高楼，望尽天涯路。"此第一境也。"衣带渐宽终不悔，为伊消得人憔悴。"此第二镜也。
+"众里寻他千百度，那人却在灯火阑珊处。"此第三镜也。
+
+Git的学习同样也可以分为三个层次，用户可以根据自己实际情况进行学习。
+
+- 第一层，Git的基础使用，这一阶段适合小白用户学习，主要是学习利用Git来下载一些开源项目，学会对项目进行增删改查。
+
+- 第二层，Git的分支、标签、版本管理等相关用法，这一阶段适合在工作中频繁使用Git来进行开发的用户，学会进行版本追溯和各种冲突解决。
+
+- 第三次，Git的版本库分析，这一阶段适合对Git原理感兴趣的开发者学习，深入了解Git在命令行的背后，对版本库进行了什么样的操作。
+
+可能很多人觉得对于Git，学习基本使用就够了。但是实际上，随着项目开发越来越复杂，会遇到很多需要使用Git复杂指令的场合。
+靠死记硬背很容易忘记它，也很难用好。这个时候去了解它的一些背后原理，对加深Git的理解大有脾益，复杂命令将不再复杂。
+
+Git的安装
+~~~~~~~~~~~~~~~~~
+
+Windows系统
+
+到Git官网下载安装包,直接安装即可。
+
+https://gitforwindows.org
+
+
+Linux系统
+
+根据不同发行版，使用相关包管理工具安装即可。
+
+比如Ubantu：在终端执行"sudo apt-get install git -y"即可。
+
+
+Git的基础使用
+~~~~~~~~~~~~~~~~~~~~
+
+Git里面有很多比较晦涩的专业术语，如果不熟悉这一套术语，常常会在Git出现各种提示信息的时候摸不着头脑。
+这里中文翻译了Git中比较重要的部分术语。先对这些专业术语有初步的印象，后面的教程再逐步讲解它的含义。
+
+.. csv-table:: Frozen Delights!
+    :widths: 10, 10, 10 ,10 ,10 ,10
+
+    "respository","仓库/版本库","commit","提交","snapshot","快照"
+    "SSH","安全传输协议","fetch","获取代码","SHA1","哈希值"
+    "HEAD","当前分支","checkout","检出分支","Gerrit","代码审核"
+    "pull","拉取代码","rebase","分支衍合","stash","储存" 
+    "push","推送代码","tag","标签","index","索引" 
+    "merge","分支合并","master","主分支","cherry-pick","条件分支"
+    "add","添加改动","origin","远程分支","revert","反转提交"
+
+
+Git本地仓库操作
+^^^^^^^^^^^^^^^^^^^^^
+
+1、Git安装完成后，新建一个文件夹"Git_demo"。右键点击，选择"Git Bash Here"选项打开,
+输入"git init"命令。该指令会在当前目录下生成一个隐藏文件".git"，这个".git"文件就是术语中本地仓库/版本库。
+如下图
+
+.. image:: media/git_init.png
+   :align: center
+   :alt: git_init
+
+2、添加一个newadd.txt文件，使用"git status"命令查看状态。
+
+.. image:: media/git_status1.png
+   :align: center
+   :alt: git_status
+
+此时新添加的文件处于"Untracked"未跟踪状态，提示使用"git add"命令添加文件到暂存区。
+
+3、执行"git add newadd.txt"命令，重新查看状态。
+
+.. image:: media/git_add.png
+   :align: center
+   :alt: git_add
+
+ 提示:new file：newadd.txt，说明文件已经添加到了暂存区。
+
+ 4、输入"git commit -m "add a new",把暂存区新修改的文件提交到仓库里面去保存，
+并在仓库中用"add a new"这条语句来记录这一次的提交。
+
+.. image:: media/git_commit.png
+   :align: center
+   :alt: git_commit
+
+5、查看当前状态，git提示没有新的可提交文件，说明文件已经提交到仓库中去了。
+
+.. image:: media/git_status2.png
+   :align: center
+   :alt: git_status
+
+6、在newadd.txt文件中加入一句"change test/\r/\n",保存退出后，查看状态。
+
+.. image:: media/git_status3.png
+   :align: center
+   :alt: git_status
+
+此时git不再提示这是一个新文件，而是一个已经修改(modified)的文件。
+
+7、重复前面提到添加到暂存区、提交到仓库的步骤，那这个改动的文件就已经保存下来了。
+使用"git log"命令可以查看到这两次提交的记录。如下图:
+
+.. image:: media/git_log.png
+   :align: center
+   :alt: git_log
+
+在输出的历史记录中，commit后面跟着的一串数字，是该文件的SHA-1 校验和，
+这个校验和在git中称为commit-id。"git show"命令可以通过commit-id，
+找到文件对应的修改记录。
+
+8、执行"git show + commit-id"命令，可以看到非常详细的修改记录，包括作者、
+时间以及详细的修改内容。+号就代表新加的内容，-号代表删减的内容。
+
+.. image:: media/git_show.png
+   :align: center
+   :alt: git_show
+
+9、如果是特别关注某个文件，还有一个"git blame"命令可以迅速地找到这个文件的改动。
+输入"git blame newadd.txt",该文件每次被提交仓库的commit-id、作者、时间、内容都显示出来了。
+如下图:
+
+.. image:: media/git_blame.png
+   :align: center
+   :alt: git_blame
+
+Git远程仓库操作
+^^^^^^^^^^^^^^^^^^^^^
+
+远程仓库是指托管在Internet或局域网中的项目版本库。现在较为流行的远程仓库是GitHub和Gitee。
+这里以GitHub为例来说明远程仓库的项目创建和下载。
+
+1、登录`GitHub官网 <https://github.com>`_ ，按提示注册一个用户后。打开右上角的'+'号，
+选择"New repository"项，创建一个新的远程仓库。
+如下图:
+
+.. image:: media/github_new_repository.png
+   :align: center
+   :alt: github_new_repository
+
+2、设置该远程仓库的名字、概述，选择该远程仓库是公开的还是私有的。
+这里把它设为公开的，并设置它的名字为"git_pratice"。如下图：
+
+.. image:: media/github_create_repository.png
+   :align: center
+   :alt: github_create_repository
+
+可以看到GitHub生成了两种远程连接方式，SSH和HTTPS。
+
+.. image:: media/github_https.png
+   :align: center
+   :alt: github_https
+
+3、输入"git remote add origin + "https地址" "命令，就能把我们本地仓库的项目与该远程仓库相关联，
+如下图:
+
+.. image:: media/github_https.png
+   :align: center
+   :alt: github_https
+
+4、这时候就可以把"Git_demo"文件夹中的仓库内容推送到远程仓库了，使用"git push -u origin master"命令进行推送，
+
+.. image:: media/github_push.png
+   :align: center
+   :alt: github_push
+
+到这里，"Git_demo"文件夹中的本地仓库就成功推送到远程仓库了。以后只要遵循"添加到暂存区"->"提交到本地仓库"->"推送到远程仓库"的步骤，
+就能初步完成远程仓库的开发工作了。
+
+5、如果在GitHup上面发现了一些自己感兴趣的项目，可以用"git clone + "https地址" "命令进行克隆。克隆完成后，
+会自动在当前目录下创建一个本地仓库，这个本地仓库可以看作是该远程仓库的备份，而且已经与该远程仓库相关联了的。
+如下图:
+
+.. image:: media/github_clone.png
+   :align: center
+   :alt: github_clone
+
+一些成熟稳定的远程仓库往往是多人合作、共同开发的，通常比我们自己创建的项目复杂很多。
+这时候如果你想参与到这种规模的项目开发，那上面的介绍的基本命令就不够用了，需要进一步的深入学习。
+
+Git的分支、标签、版本回溯
+~~~~~~~~~~~~~~~~~~~~~~~~~
+
+分支
+^^^^^^^^
+
+Git的分支管理功能是多人协同开发的利器，在大型项目的开发中，开发者通常会先切出远程仓库的一个分支，
+等到在分支上完开发完功能后，再把分支合并到主支中去。
+
+在分支上开发有两个好处，一是避免所有开发者杂糅在主支上开发，导致频繁的提交代码冲突。在新开发的功能未经过严格测试之前，
+提交代码到主支上是风险很大的。不能轻易地因为代码冲突就修改其他开发者的代码，这必须是经过慎重考虑的。
+二是分支的提交记录不会影响到主支，我们可以随时提交自己的代码到远程仓库的分支中作备份，避免自己因为电脑的硬盘故障而导致本地仓库的资料丢失。
+
+下面模拟两个开发者(A、B)协同工作的流程，帮助大家更好地理解分支的使用、分支冲突解决和版本回溯等功能。
+
+A和B此时分别使用git clone命令，把前面创建的git_pratice远程仓库克隆下来。
+如下图:
+
+.. image:: media/github_clone1.png
+   :align: center
+   :alt: github_clone1
+
+开发者A
+"""""""""""""""""
+
+1、现在模拟开发者A工作，使用git branch命令，创建一个本地分支，命名为"test_branch1"。
+使用"git branch -a"命令查看所有分支。。
+如下图:
+
+.. image:: media/git_branch.png
+   :align: center
+   :alt: git_branch
+
+可以看到现在本地仓库中有两个本地分支，其中master默认为主分支，已经和远程仓库关联，
+而test_branch1分支为新创建的本地分支。*表示当前本地分支指向master分支。
+
+再看远端仓库，"remote"表示远程分支，但是HEAD不是指一个独立分支，
+它表示的是当前分支。所以现在远端仓库只有一个master分支，远端仓库的当前分支指向master。
+
+
+2、输入"git checkout test_branch1"命令检出test_branch1分支，修改newadd.txt文件内容分为"this is branch1"
+如下图:
+
+.. image:: media/git_checkout.png
+   :align: center
+   :alt: git_checkout
+
+3、把改动添加到缓存区（git add）、提交到本地仓库(git commit)。
+如下图:
+
+.. image:: media/git_commit1.png
+   :align: center
+   :alt: git_commit
+
+4、执行"git push origin +"分支名""命令（origin是GitHub的默认主机名)，在远程仓库建立test_branch1分支，
+并把当前本地分支(test_branch1分支)的内容推送到上去。如下图:
+
+.. image:: media/git_push.png
+   :align: center
+   :alt: git_push
+
+在GitHub远程仓库上，可以看到新创建了分支，如下图：
+
+.. image:: media/git_push1.png
+   :align: center
+   :alt: git_push
+
+5、假设现在开发者A工作结束了，那么它需要将本地test_branch1合并到mster分支上，再推送到远端仓库的master分支。
+需要执行的步骤是:切回到master分支，再使用"git merge +分支名"就能把test_branch1分支合并到master分支。如下图:
+
+.. image:: media/git_merge.png
+   :align: center
+   :alt: git_merge
+
+6、使用"git push origin master"命令，把当前本地分支（新合并的本地master分支）推送到远端的master分支。
+git显示已经成功推送。
+如下图:
+
+.. image:: media/git_push2.png
+   :align: center
+   :alt: git_push2
+
+
+开发者B
+"""""""""""""""""
+
+1、现在轮到开发者B来开始工作，前面创建、捡出、修改和推送分支的步骤与开发者A是一致的。
+但是分支名称改为test_branch2，修改的内容为:"this is branch2"。
+如下图:
+
+.. image:: media/git_checkout1.png
+   :align: center
+   :alt: git_check
+
+2、同开发者A一样，开发者B的test_branch2分支也提交到远端仓库了。现在远端仓库有三个分支，
+如下图：
+
+.. image:: media/git_push3.png
+   :align: center
+   :alt: git_push
+
+3、假设此时开发者B也完成工作了，需要把test_branch2合并到master主支，然后提交到远程仓库master分支
+需要执行的步骤是:切回到master分支，再执行"git merge +分支名"就能把test_branch2分支合并到master分支。
+
+如下图:
+
+.. image:: media/git_merge1.png
+   :align: center
+   :alt: git_merge1
+
+4、使用"git push origin master"命令，把当前本地分支（新合并的本地master分支）推送到远端的master分支。
+出乎意料的是，这一次推送失败了。
+
+.. image:: media/git_push4.png
+   :align: center
+   :alt: git_push
+
+这是因为之前开发者A已经修改了远程仓库的文件，但是现在开发者B的本地仓库中并不知道开发者A修改了什么内容，
+所以远端仓库不允许再次推送，否则开发者A修改的内容就被覆盖了。
+
+因此，需要先使用git pull命令把开发者A修改的内容同步到开发者B的本地仓库中，
+此时如果开发者A和开发者B修改了相同的文件，那么git会识别出来并且提示你去解决冲突。
+如下图:
+
+.. image:: media/git_pull.png
+   :align: center
+   :alt: git_pull
+
+5、打开git提示冲突的文件，解决冲突。
+如下图:
+
+.. image:: media/git_error.png
+   :align: center
+   :alt: git_error
+
+上面"<<<<<<< HEAD"部分代表的是本地仓库的修改内容，"======="表示内容分割线，">>>>>>>"表示目前远端仓库的内容。
+
+6、开发者B经过认真思考，觉得应该以自己的内容为准。于是删除了远程仓库的内容和冲突符号，只保留自己的改动。
+
+.. image:: media/git_save.png
+   :align: center
+   :alt: git_save
+
+7、把解决冲突后的内容，重新添加到暂存区、提交到本地仓库。
+如下图:
+
+.. image:: media/git_commit2.png
+   :align: center
+   :alt: git_commit
+
+8、此时再次使用"git push origin master"命令，把当前本地分支（新合并的本地master分支）推送到远端的master分支。
+如下图:
+
+.. image:: media/git_push5.png
+   :align: center
+   :alt: git_push5
+
+此时，修改的内容就成功推送到远端仓库了。
+
+9、如果确认功能完成开发后，输入"git branch -d +分支名"命令可以删除本地分支，
+输入"git push --delete origin +分支名"命令可以删除远程分支。
+
+如下图:
+
+.. image:: media/git_delete.png
+   :align: center
+   :alt: git_delete
+
+远程分支已经删除成功。
+
+标签
+^^^^^^
+
+上面介绍了如何通过"git show + commit-id"命令来查看某次历史提交的详细记录。但是commit-id是一串冰冷、
+无规律的数字，十分难以记忆。有时候开发者完成了一个大版本的功能开发，此时新功能未经市场验证，
+，可能后面需要频繁review代码、解决bug。那么每次追溯都要重复地查询commit-id，效率就会很低。
+
+在这种场景下，git的标签功能就很重要了。它可以对某一时间点上的版本打上指定标签，
+利用该标签可以方便快速地进行查看历史提交信息。可以把标签理解为给commit-id起一个别名。
+
+1、用"git log"命令可以查询到历史提交的commit-id。输入"git tag +标签名 +commit-id"命令，
+给commit-id对应的历史版本打上一个标签。
+如下图:
+
+.. image:: media/git_tag.png
+   :align: center
+   :alt: git_tag
+
+找到分支test_branch的提交，并给这个版本的提交打上"v1.0"的标签。
+
+2、执行"git show v1.0"命令，可以查看到该次提交的详细信息，包括作者、日期、文件改动内容等等。
+如下图:
+
+.. image:: media/git_show1.png
+   :align: center
+   :alt: git_show1
+
+3、使用"git push origin +标签名"命令，可以把该标签推送到远端分支。加 --tags 选项表示推送全部标签。
+如下图:
+
+.. image:: media/git_push6.png
+   :align: center
+   :alt: git_push6
+
+git提示标签推送成功。
+
+4、使用"git tag -d +标签名"命令删除本地仓库的标签，使用"git push origin :refs/tags/+标签名"来移除远端仓库的标签。
+
+.. image:: media/git_push6.png
+   :align: center
+   :alt: git_push6
+
+git提示本地标签已经删除，远端仓库相应的标签也已经删除。
+
+版本回溯
+^^^^^^^^
+
+一旦开发者仓库中提交了错误的修改内容，就需要进行版本回溯。版本回溯的意思是把仓库里面的内容还原到某一次历史提交的状态中。
+通常在新产品出了bug时，就可以通过版本回溯来定位bug。
+
+1、用"git log"命令查询到历史提交的commit-id。输入"git reset --hard +commit-id"命令，
+就能把仓库还原到commit-id对应的历史提交的状态中。
+如下图:
+
+.. image:: media/git_reset.png
+   :align: center
+   :alt: git_reset
+
+看到newadd.txt已经还原到test_branch1提交的状态。
+
+2、使用"git push -f origin master"，强制推送到远端仓库，远端仓库也将被还原到test_branch1提交状态。
+
+.. image:: media/git_push7.png
+   :align: center
+   :alt: git_push7
+
+3、版本回溯还有其他更优雅的方法，比如使用标签替代commit-id，使用git revert等，
+考虑到篇幅，无法一一详述。大家感兴趣可以自行查阅git说明文档。
+
+Git的版本库分析
+~~~~~~~~~~~~~~~~~~~~~~~~~
+
+本地仓库存储在.git文件夹中，.git文件夹目录如下图所示:
+
+.. image:: media/git_store.png
+   :align: center
+   :alt: git_store
+
+其中，
+
+- hooks目录下是存放一些shell脚本，可以指定某些shell脚本在git指令执行时运行。
+
+- info 目录存放包含仓库的部分信息，里面的exclude文件可以排除管理的文件，不同的地方是它不会被共享。
+
+- logs目录保存所有的历史引用记录(commit-id)。
+
+- objects目录中存放所有的git对象(commit、tree、tag、blob)。
+
+- refs目录存放具体的引用信息。三个子目录heads、remote、tags分别记录本地仓库、远端仓库和标签最后一次的commit-id。
+
+- config目录里面记录了远程仓库的名字(默认为origin)、url、本地仓库主支(默认为master)等。
+
+- COMMIT_EDITMSG文件记录最后的一次commit message
+
+- description文件是仓库的描述信息
+
+- index 是一个二进制文件，实际上就是暂存区。
+
+- HEAD文件记录当前分支。
+
+- FETCH_HEAD文件记录远端仓库的数据获取过程，指向远端仓库的最新版本。
+
+- ORIG_HEAD:HEAD指针的前一个状态。
+
+- packed-refs：clone仓库时所有的引用信息。
+
+git对象
+^^^^^^^^^^^^^^^
+
+待后续补充
+
+git add/commit底层机制
+^^^^^^^^^^^^^^^
+
+待后续补充
+
+常用git命令汇总
+
diff --git a/documentation/linux_basis/how_to_learn_linux.rst b/documentation/linux_basis/how_to_learn_linux.rst
new file mode 100644
index 0000000000000000000000000000000000000000..0a2ae84fea01bc0044b1be25c61054b8e6f26789
--- /dev/null
+++ b/documentation/linux_basis/how_to_learn_linux.rst
@@ -0,0 +1,77 @@
+.. vim: syntax=rst
+
+如何学习linux开发
+----------------
+
+
+嵌入式linux学习路线
+~~~~~~~~~~~~~~~~~~~~
+
+我们立足于树莓派的开发方式，借鉴其一系列先进的设计理念和软件架构，力求为电子爱好者提供强大、好用的DIY平台，
+方便实现各种天马行空的想法。与此同时，所有的软件和芯片手册将全部开源，为有志于从事嵌入式linux行业者后续深入学习各种软件架构和驱动程序扫清障碍。
+
+适合哪些用户群体
+^^^^^^^^^^^^^^^^^^^^^^^^^^^
+嵌入式linux学习者大体可以分为两类，一类是进阶用户，主要指已经有大量mcu工作经验的开发者，
+他们希望进阶到更有难度，薪资更高的mpu开发中去。另一类则是学生用户，主要是刚开始接触嵌入式开发的大学生群体。
+
+对于前者而言，出于工作的压力和升职加薪的需求，通常会比较关注课程学习的深度，关注学习完成后，能不能顺利地利用学习的知识来跳槽升职加薪。
+但是对于后者，他们没有行业经验，没有工作压力，更加注重的是课程的有趣性，功能性，想知道通过这个课程我有能力做出什么东西来。
+
+本教程兼顾两种用户的需求，首先，最大程度上降低入门门槛，这主要指两个方面，一方面简化开发环境的搭建，尽可能避免各种各样的软件版本问题，
+以及各种电脑系统的兼容性问题。另一方面是先学习嵌入式linux的高频技能，所谓高频技能，就是指在大部分实际开发工作中都较为频繁地使用的技能。
+其次，是尝试使用这些高频技能去开发一些炫酷、自己感兴趣的产品，进一步去了解嵌入式linux各式各样的产业，体验嵌入式linux在人类实际生活中的影响。
+最后，在对嵌入式linux有整体了解后，根据自己的个人兴趣和实际工作需求，选择嵌入式linux的某一个方面深入研究。
+
+通常，国内传统的嵌入式linux学习路线大体为:
+
+1.  linux基本操作+c语言进阶
+#.  ARM裸机开发
+#.  linux系统移植(u-boot移植、kernel移植、构建根文件系统)
+#.  linux驱动开发
+#.  linux应用编程
+#.  项目实战
+
+按照上面的学习路线走下来，一方面，需要耗费巨大的学习精力，哪怕全天学习，一般也要4个月以上的时间。这对于还没有确定职业方向的学生用户，
+想玩嵌入式linux的门槛太高。
+
+另一方面，不贴合进阶用户实际工作需求，因为大部分课程在设计的时候充斥了许多低频技能，这些技能在大部分嵌入式linux工作中很少用上(比如ARM裸机开发)。
+而当工作中真正遇到系统性能问题的时候，往往又没有能力去实际解决问题，因为你所学习的linux系统移植，不过是用芯片公司团队做好的系统镜像，
+自己复制张贴一些文件，修改一些配置，然后重新编译安装到系统里面去，真正高阶的技能其实没学到多少。
+
+为什么选择树莓派教育理念
+^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+树莓派（Raspberry Pi）是尺寸仅有信用卡大小的一个小型电脑，您可以将树莓派连接电视、显示器、键盘鼠标等设备使用，
+它的设计目标是用较为低廉的价格和大量开源软件，为青少年提供一个计算机教育平台，用于培养计算机程序设计的兴趣和能力。
+
+现在树莓派已经拥有全球100万用户的作品展示社区，这意味着树莓派有海量的应用可以参考和模仿。
+下面是它们的一些DIY案例:
+
+.. image:: media/raspi_demo1.png
+   :align: center
+   :alt: 树莓派案例
+
+.. image:: media/raspi_demo2.png
+   :align: center
+   :alt: 树莓派案例
+
+.. image:: media/raspi_demo3.png
+   :align: center
+   :alt: 树莓派案例
+
+.. image:: media/raspi_demo4.png
+   :align: center
+   :alt: 树莓派案例
+
+树莓派的成功给了国内linux教育一些深刻的启发，那就是编程教育应该是强调探究性、项目式学习，以此激发探索的好奇心和享受实现自己目标的成就感。
+从这个角度而言，掌握一些必备的计算机编程技能只是完成了基本的知识获取过程，重点是站在巨人肩膀上的各种创新。
+
+考虑到开发者技术水平参差不齐，树莓派做了很多软件架构上的优化和开发了很多方便好用工具。
+这是树莓派广受好评和便于在社区推广的一大原因，非常值得我们去借鉴学习。
+
+但是树莓派也有它的不足之处，那就是它的底层的bootloader和核心数据手册是闭源的，普通用户无法获取。
+所以树莓派往往更被学生群体或者其他一些创客群体所青睐，而不太适合嵌入式linux从业者的进阶学习。
+
+
+
diff --git a/documentation/linux_basis/i_mx_series.rst b/documentation/linux_basis/i_mx_series.rst
index cedb4549b74dc9c38258da0cc13217506de45dc3..f48fa0eb0839f499a2de03389d2be8cc255b73dc 100644
--- a/documentation/linux_basis/i_mx_series.rst
+++ b/documentation/linux_basis/i_mx_series.rst
@@ -20,9 +20,14 @@ reescale的一些标签时不要奇怪。NXP承诺对这些产品供货周期持
 本书讲解主要采用的是i.MX6ULL系列处理器，它包含一个Cortex-A7内核，主频有528MHz、792MHz和900Mhz，具体芯片的特性可参考图
 2‑1的命名规则说明进行区分。如型号为MCIMX6Y2CVM08AB的芯片，它属于i.MX6ULL系列，是主频为792MHz、芯片封装为BGA，尺寸为14x14mm，焊盘间距为0.8pitch的工业级芯片。
 
-|imxser002|
+.. image:: media/imxser002.png
+   :align: center
+   :alt: 未找到图片
 
-图 2‑1 i.MX6 ULL芯片命名规则
+
+
+
+ULL芯片命名规则
 
 Cortex A7内核简介
 ~~~~~~~~~~~~~~~~~~~~~~~~~~
@@ -36,7 +41,7 @@ Cortex-A7处理器是ARM开发的一种高能效处理器架构，它的架构
 i.MX RT系列
 ~~~~~~~~~~~~~~~~~~
 
-NXP针对MCU（微控制器）的应用场景，推出了i.MX RT系列跨界处理器，该系列下又包括i.MX RT1020、i.MX RT1050及i.MX RT1060等子系列芯片。所谓“跨界”，是指它自身的定位既非传统的应用处理器也非传统的微控制器。
+NXP针对MCU（微控制器）的应用场景，推出了i.MX RT系列跨界处理器，该系列下又包括i.MX RT1020、i.MX RT1050及i.MX RT1060等子系列芯片。所谓"跨界"，是指它自身的定位既非传统的应用处理器也非传统的微控制器。
 
 它在i.MX6的MPU（应用处理器）平台之上把其Cortex-A内核换成Cortex-M内核，使得它具备了应用处理器的高性能及丰富的功能，又具备传统微控制器的易用、实时及低功耗的特性。
 
@@ -57,13 +62,23 @@ NXP针对MCU（微控制器）的应用场景，推出了i.MX RT系列跨界处
 
 对于学习Linux依然心怀忐忑，希望学习MCU过渡的读者，这些是非常适合的教材。具体资料下载地址请参见链接：\ https://github.com/Embdefire/products/wiki\ 。
 
-|imxser003|
 
-图 2‑2 我这有本秘笈（图片来源：周星驰 电影《功夫》）
+.. image:: media/imxser003.jpg
+   :align: center
+   :alt: 未找到图片
+
+
+（图片来源：周星驰 电影《功夫》）
+
+.. image:: media/imxser004.jpg
+   :align: center
+   :alt: 未找到图片
+
+
+（图片来源：周星驰 电影《功夫》）
+
 
-|imxser004|
 
-图 2‑3 老乡别跑（图片来源：周星驰 电影《功夫》）
 
 .. |imxser002| image:: media/imxser002.png
    :width: 5.23333in
diff --git a/documentation/linux_basis/index.rst b/documentation/linux_basis/index.rst
index 46e361d8fd3dfb1b35e5bdce3f0ff8de3001b1ec..5ca2a2a3f44c51472c21300e5383182c2a34e592 100644
--- a/documentation/linux_basis/index.rst
+++ b/documentation/linux_basis/index.rst
@@ -20,4 +20,4 @@
 ..    linux_directory
 ..    user_group
 ..    command_line
-
+..    ec20_4g_module
diff --git a/documentation/linux_basis/installing_linux.rst b/documentation/linux_basis/installing_linux.rst
index 2dd797a8040ba2fd5d77a7aaf9839f3ce87c086d..e011a475bc33af55d8fba330d9574f48a9e09d15 100644
--- a/documentation/linux_basis/installing_linux.rst
+++ b/documentation/linux_basis/installing_linux.rst
@@ -16,68 +16,93 @@
 流行的虚拟机软件有VMware、Virtual Box和Virtual PC，它们都能在Windows系统上虚拟出多个计算机，本书使用的是免费的虚拟机软件Virtual Box，我们可以去\ https://www.virtualbox.org/wiki/Downloads\
 官网中下载VirtualBox软件，也可以使用我们提供的资料光盘中的软件，进行安装。
 
-|instal002|
 
-图 4‑1 官网下载地址
+
+.. image:: media/instal002.jpeg
+   :align: center
+   :alt: 未找到图片02|
+
+
 
 下面介绍一下，安装虚拟机软件VirtualBox的全过程：
 
-(1) 运行VirtualBox-6.0.2-128162-Win.exe，可以看到的界面，点击“下一步”，见图 4‑2。
+(1) 运行VirtualBox-6.0.2-128162-Win.exe，可以看到的界面，点击"下一步"，见下图。
+
+.. image:: media/instal003.jpg
+   :align: center
+   :alt: 未找到图片03|
+
+
+
+(2) 需要安装的功能，选择默认即可。软件的安装路径，用户可以根据实际情况自由选择，本书选择安装
+在E盘，点击"下一步"，见下图。
+
+.. image:: media/instal004.jpg
+   :align: center
+   :alt: 未找到图片04|
 
-|instal003|
 
-图 4‑2 安装向导
 
-(2) 需要安装的功能，选择默认即可。软件的安装路径，用户可以根据实际情况自由选择，本书选择安装在E盘，点击“下一步”，见图 4‑3。
+(3) 安装过程，选择软件自定义的功能，这里选择默认即可，点击"下一步"，见下图。
 
-|instal004|
+.. image:: media/instal005.jpg
+   :align: center
+   :alt: 未找到图片05|
 
-图 4‑3 选择安装路径
 
-(3) 安装过程，选择软件自定义的功能，这里选择默认即可，点击“下一步”，见图 4‑4。
 
-|instal005|
+(4) 在安装过程中，会提示一个警告，我们可以忽略该警告，点击"是"，继续安装，见下图。
 
-图 4‑4 自定义安装
+.. image:: media/instal006.jpg
+   :align: center
+   :alt: 未找到图片06|
 
-(4) 在安装过程中，会提示一个警告，我们可以忽略该警告，点击“是”，继续安装，见图 4‑5。
 
-|instal006|
 
-图 4‑5 安装警告
+(5) 下图中，点击"安装"按钮，开始安装软件。
 
-(5) 图 4‑6，点击“安装”按钮，开始安装软件。
+.. image:: media/instal007.jpg
+   :align: center
+   :alt: 未找到图片07|
 
-|instal007|
 
-图 4‑6 开始安装
 
 (6) 这样之后，便开始安装VirtualBox软件，静静地等待，软件安装完成。
 
-|instal008|
+.. image:: media/instal008.jpg
+   :align: center
+   :alt: 未找到图片08|
 
-图 4‑7 安装过程
 
-(7) 软件安装成功，点击“完成”，运行VirtualBox，见图 4‑8。
 
-|instal009|
+(7) 软件安装成功，点击"完成"，运行VirtualBox，见下图。
 
-图 4‑8 安装成功
+.. image:: media/instal009.jpg
+   :align: center
+   :alt: 未找到图片09|
+
+
+
+.. image:: media/instal010.jpeg
+   :align: center
+   :alt: 未找到图片10|
 
-|instal010|
 
-图 4‑9 软件VirtualBox
 
 获取Ubuntu系统
 ~~~~~~~~~~~~~~~~~~~~~~~~~~
 
-本书以Ubuntu 18.04桌面发行版本作为开发主机的主体系统环境，对于后期编译内核等依赖不同版本系统环境的情况，我们会采用Docker技术创建其它运行环境。
+本书以Ubuntu 18.04桌面发行版本作为开发主机的主体系统环境，对于后期编
+译内核等依赖不同版本系统环境的情况，我们会采用Docker技术创建其它运行环境。
+
+在安装前需要先到Ubuntu的官网下载桌面版的系统镜像，可在如下
+址下载得到：\ https://ubuntu.com/download/desktop\ ，具体见下图。
 
-在安装前需要先到Ubuntu的官网下载桌面版的系统镜像，可在如下网址下载得到：\ https://ubuntu.com/download/desktop\ ，具体见图 4‑10。
+.. image:: media/instal011.png
+   :align: center
+   :alt: 未找到图片11|
 
-|instal011|
 
-图 4‑10 Ubuntu下载页面
 
 使用VirtualBox安装Ubuntu系统
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
@@ -86,121 +111,171 @@
 
 (1) 可从以下地址获取VirtualBox软件：\ https://www.virtualbox.org/wiki/Downloads\ ，下载后直接安装即可。
 
-(2) 运行VirtualBox软件，点击“新建”按钮，来创建一个新的虚拟机，如图 4‑11所示。点击“下一步”。
+(2) 运行VirtualBox软件，点击"新建"按钮，来创建一个新的虚拟机，如下图所示。点击"下一步"。
+
+.. image:: media/instal012.jpg
+   :align: center
+   :alt: 未找到图片12|
+
+
+
+(3) 选择内存大小，默认为1024MB，可以根据自己电脑
+    的配置选择，这里选择4096MB，即4GB的内存大小，点击"下一步"按钮。
 
-|instal012|
+.. image:: media/instal013.jpg
+   :align: center
+   :alt: 未找到图片13|
 
-图 4‑11 创建虚拟机
 
-(3) 选择内存大小，默认为1024MB，可以根据自己电脑的配置选择，这里选择4096MB，即4GB的内存大小，点击“下一步”按钮。
 
-|instal013|
+(4) 选择虚拟硬盘，如下图所示，选择"现在创建虚拟硬盘"，点击"创建"。出现如下所示的窗口，选择
+    虚拟硬盘的类型，一般情况都选择VDI，单击"下一步"。虚拟硬盘的分配方
+    式有两种：一种是动态分配，需要多少用多少，一开始占用小，随着空间需要而增长；另一种是固定大小，它
+    会直接占用所分配的物理硬盘空间，但是访问速度快。这里我们选择"动态
+    分配"，点击"下一步"之后，就需要我们选择虚拟硬盘大小，默认是10GB，用户可
+    以根据自己电脑配置和需要进行分配，这里选择100GB（它不会立即占用这么多的空间，根据自
+    己需求设置即可）。最后点击"创建"按钮，这样就创建好了。
 
-图 4‑12 分配内存大小
+.. image:: media/instal014.jpg
+   :align: center
+   :alt: 未找到图片14|
 
-(4) 选择虚拟硬盘，如图 4‑13所示，选择“现在创建虚拟硬盘”，点击“创建”。出现图 4‑14所示的窗口，选择虚拟硬盘的类型，一般情况都选择VDI，单击“下一步”。如图 4‑15所示，虚拟硬盘的分配方式有两种：一种是动态分配，需要多少用多少，一开始占用小，随着空间需要而增长；另一种是固定大小，它
-会直接占用所分配的物理硬盘空间，但是访问速度快。这里我们选择“动态分配”，点击“下一步”之后，就需要我们选择虚拟硬盘大小，默认是10GB，用户可以根据自己电脑配置和需要进行分配，这里选择100GB（它不会立即占用这么多的空间，根据自己需求设置即可）。如图
-4‑16所示，最后点击“创建”按钮，这样就创建好了，如图 4‑17所示。
 
-|instal014|
 
-图 4‑13 创建虚拟硬盘
+.. image:: media/instal015.jpg
+   :align: center
+   :alt: 未找到图片15|
 
-|instal015|
 
-图 4‑14 选择虚拟硬盘类型
 
-|instal016|
+.. image:: media/instal016.jpg
+   :align: center
+   :alt: 未找到图片16|
 
-图 4‑15 虚拟硬盘的分配方式
 
-|instal017|
 
-图 4‑16 指定虚拟硬盘的大小
+.. image:: media/instal017.jpg
+   :align: center
+   :alt: 未找到图片17|
 
-|instal018|
 
-图 4‑17 创建成功
+.. image:: media/instal018.jpg
+   :align: center
+   :alt: 未找到图片18|
 
-(5) 点击右侧的“设置”按钮，如图 4‑18所示，选择“存储”栏目，然后选择处来设置系统镜像文件，通过点击处的按钮来选择我们Ubuntu镜像文件（*.iso）的路径，设置成功之后，如图 4‑19所示，点击“OK”，进入下一步。
 
-|instal019|
 
-图 4‑18 设置镜像文件
+(5) 点击右侧的"设置"按钮，如下图所示，选择"存储"栏
+    目，然后选择处来设置系统镜像文件，通过点击处的按钮来选择我们Ubuntu镜像
+    文件（*.iso）的路径，设置成功之后，如下图所示，点击"OK"，进入下一步。
 
-|instal020|
+.. image:: media/instal019.jpg
+   :align: center
+   :alt: 未找到图片19|
 
-图 4‑19 镜像文件设置成功
 
-(6) 选择“网络”栏目，将网卡连接方式配置为桥接网卡，如图 4‑20所示。
 
-|instal021|
+.. image:: media/instal020.jpg
+   :align: center
+   :alt: 未找到图片20|
 
-图 4‑20 设置网卡连接方式
 
-(7) 安装Ubuntu18.04系统，点击启动“启动”按钮，启动虚拟机，如图 4‑21所示。进入安装程序，如图 4‑22所示。
 
-|instal022|
+(6) 选择"网络"栏目，将网卡连接方式配置为桥接网卡，如下图所示。
 
-图 4‑21 启动虚拟机
+.. image:: media/instal021.jpg
+   :align: center
+   :alt: 未找到图片21|
 
-|instal023|
 
-图 4‑22 安装程序
 
-(8) 选择语言，处可以选择英文，中文等语言，这里我们选择 “简体中文”，然后点击处的“install Ubuntu”按钮，进入下一步。
+(7) 安装Ubuntu18.04系统，点击启动"启动"按钮，启动虚拟机，如下图所示。进入安装程序，如下图所示。
 
-..
+.. image:: media/instal022.jpg
+   :align: center
+   :alt: 未找到图片22|
 
-   |instal024|
 
-(9) 选择键盘布局，如图 4‑23，点击“继续”。
 
-|instal025|
+.. image:: media/instal023.jpg
+   :align: center
+   :alt: 未找到图片23|
 
-图 4‑23 键盘布局
 
-(10) 选择一些软件安装，如图 4‑24所示，点击“继续”，进入下一步。
 
-|instal026|
+(8) 选择语言，处可以选择英文，中文等语言，这里我们选择 "简体中文"，然后点击处
+    的"install Ubuntu"按钮，进入下一步。
 
-图 4‑24 软件更新
+.. image:: media/instal024.jpg
+   :align: center
+   :alt: 未找到图片24|
 
-(11) 进入如图 4‑25所示的界面，由于虚拟机的虚拟硬盘是独占的，我们选择默认的“清除整个磁盘并安装Ubuntu”即可。
 
-|instal027|
+(9) 选择键盘布局，如下图所示，点击"继续"。
+
+.. image:: media/instal025.jpg
+   :align: center
+   :alt: 未找到图片25|
+
+
+
+(10) 选择一些软件安装，如下图所示，点击"继续"，进入下一步。
+
+.. image:: media/instal026.jpg
+   :align: center
+   :alt: 未找到图片26|
+
+
+
+(11) 进入如下图所示的界面，由于虚拟机的虚拟硬盘是独占的，我们选择默认的"清除整个磁盘并安装Ubuntu"即可。
+
+.. image:: media/instal027.jpg
+   :align: center
+   :alt: 未找到图片27|
+
 
-图 4‑25 选择安装类型
 
 (12) 点击继续后会弹出提示确认磁盘的分区修改，点击继续即可。
 
-|instal028|
+.. image:: media/instal028.jpg
+   :align: center
+   :alt: 未找到图片28|
+
+
 
-图 4‑26 确认磁盘分区
+(13) 选择时区，在下图的提示界面区域点击我国东侧位置，其下的文本会出现"Shanghai"字
+     样，选择后系统使用的就是北京时间。
 
-(13) 选择时区，在图 4‑27提示界面区域点击我国东侧位置，其下的文本会出现“Shanghai”字样，选择后系统使用的就是北京时间。
 
-..
+.. image:: media/instal029.jpg
+   :align: center
+   :alt: 未找到图片29|
 
-   |instal029|
 
-图 4‑27选择默认时区
 
-(14) 进入如图 4‑28所示的界面，在这个界面中输入用户名和密码，设置计算机名称，用户可以根据自己的喜好来设置。此处设置的用户会默认具有系统管理员的权限，使用Linux系统时，常常需要使用该密码进行认证，请牢记该密码。
+(14) 进入如下图所示的界面，在这个界面中输入用户名和密码，设置计算机名称，用户
+     可以根据自己的喜好来设置。此处设置的用户会默认具有系统管理员的权限，使
+     用Linux系统时，常常需要使用该密码进行认证，请牢记该密码。
 
-|instal030|
+.. image:: media/instal030.jpg
+   :align: center
+   :alt: 未找到图片30|
 
-图 4‑28 配置用户名和密码
 
-(15) 如图 4‑29所示，等待安装完成，然后重启虚拟机，输入密码，就可以看到Linux的桌面了，如图 4‑30所示。
 
-|instal031|
+(15) 如下图所示，等待安装完成，然后重启虚拟机，输入密码，就可以看到Linux的桌面了，如下所示。
 
-图 4‑29 正在安装系统
+.. image:: media/instal031.jpg
+   :align: center
+   :alt: 未找到图片31|
+
+
+
+.. image:: media/instal032.jpeg
+   :align: center
+   :alt: 未找到图片32|
 
-|instal032|
 
-图 4‑30 安装成功
 
 给虚拟机安装增强功能
 ~~~~~~~~~~~~~~~~~~~~~~~~~~
@@ -209,184 +284,268 @@
 
 安装过程如下：
 
-(1) 在虚拟机界面点击“设备/安装增强功能”即可，见图 4‑31。
+(1) 在虚拟机界面点击"设备/安装增强功能"即可，见下图。
+
+.. image:: media/instal033.png
+   :align: center
+   :alt: 未找到图片33|
 
-|instal033|
 
-图 4‑31 点击安装增强功能
 
-(2) 点击安装增强功能后，虚拟机中会插入一个光盘，并会自动启动安装程序，见图 4‑32，在弹出的界面点击运行。若没有自动启动，可手动双击该光盘进行安装。
 
-|instal034|
 
-图 4‑32 运行安装程序
+(2) 点击安装增强功能后，虚拟机中会插入一个光盘，并会自动启动安装程序，见下图，在弹出的
+    界面点击运行。若没有自动启动，可手动双击该光盘进行安装。
 
-(3) 点击运行后会出现终端界面输出运行提示，最后提示“press return to close this window”时，按回车键退出即可。
+.. image:: media/instal034.png
+   :align: center
+   :alt: 未找到图片34|
+
+
+
+(3) 点击运行后会出现终端界面输出运行提示，最后提示"press return to close this window"时，按回车键退出即可。
+
+.. image:: media/instal035.png
+   :align: center
+   :alt: 未找到图片35|
 
-|instal035|
 
-图 4‑33 安装完成
 
 (4) 重启虚拟机，进入系统后尝试调整虚拟机控制界面的窗口大小，看到虚拟机内桌面根据窗口大小调整分辨率表明安装成功。
 
-(5) 设置虚拟机控制选项中的“设备/共享粘贴板”和“设备/拖放”一栏可以设置虚拟机与主机之间的粘贴板和拖放功能。
+(5) 设置虚拟机控制选项中的"设备/共享粘贴板"和"设备/拖放"一栏可以设置虚拟机与主机之间的粘贴板和拖放功能。
 
 设置共享文件夹
 ~~~~~~~~~~~~~~~
 
-在未来的学习过程中，我们有时候需要把下载的资料文件放到虚拟机中，或者是需要把虚拟机的资料挪到Windows主机中，常用的解决方法有很多，如winscp，FileZilla等软件。不过，上述的软件虽然在使用的过程十分快捷方便，但是在安装过程中，都相当地麻烦，一会需要在虚拟机上操作，一会又要到主机上操作
-。我们的虚拟机实际上提供了一个强大的功能：共享文件夹。我们可以通过这个功能，实现主机与虚拟机的文件传输，安装方式以及使用方法也都十分简单。下面，介绍一下如何开启虚拟机VirtualBox的共享文件夹功能（执行以下步骤时，确保Linux虚拟机处于关机状态）。
+在未来的学习过程中，我们有时候需要把下载的资料文件放到虚拟机中，或者是需要把虚拟机的
+资料挪到Windows主机中，常用的解决方法有很多，如winscp，FileZilla等软件。不过，上述
+的软件虽然在使用的过程十分快捷方便，但是在安装过程中，都相当地麻烦，一会需要在虚拟机
+上操作，一会又要到主机上操作
+。我们的虚拟机实际上提供了一个强大的功能：共享文件夹。我们可以通过这个功能，实现主
+机与虚拟机的文件传输，安装方式以及使用方法也都十分简单。下面，介绍一下如何开启虚
+拟机VirtualBox的共享文件夹功能（执行以下步骤时，确保Linux虚拟机处于关机状态）。
+
+(1) 新建文件夹，用于Windows主机和Linux虚拟机共享文件夹。用户可以根据实际情况，创建共享文件夹，见下图。
+
+.. image:: media/instal036.jpg
+   :align: center
+   :alt: 未找到图片36|
+
+
+
+(2) 设置虚拟机的共享文件夹，点击下图的标记处，弹出设置窗口，选择"共享文件夹"选项卡（下图的处），最后点
+    击的按钮，添加共享文件夹，进入下一步。
+
+.. image:: media/instal037.jpg
+   :align: center
+   :alt: 未找到图片37|
+
+
+
+(3) 下图中，点击处按钮，新增共享文件夹，在弹出的"添加共享文
+    件夹"窗口，我们可以看到处有一个下拉箭头，我们选中处，来选择
+    我们刚刚新建的文件夹。到这里之后，我们就完成了文件夹路径的
+    设置。我们仍然需要让虚拟机启动的时候，自动挂载共享文件夹，见下
+    图。选中"自动挂载"选项，在处填入共享文件夹的挂载点，这里我
+    们建议初学者使用我们提供的路径：**/home/用户名/ebf_dir**  
+
+    用户名需要根据用户安装系统时，输入的用户名。本书使用的embedfire，因此，我们
+    输入的路径为"/home/embedfire/ebf_dir"，最后点击"OK"按钮即可完成设置，见下图。
+
+.. image:: media/instal038.jpg
+   :align: center
+   :alt: 未找到图片38|
+
 
-(1) 新建文件夹，用于Windows主机和Linux虚拟机共享文件夹。用户可以根据实际情况，创建共享文件夹，见图 4‑34。
 
-|instal036|
+.. image:: media/instal039.jpg
+   :align: center
+   :alt: 未找到图片39|
 
-图 4‑34 新建文件夹
 
-(2) 设置虚拟机的共享文件夹，点击图 4‑35的处，弹出设置窗口，选择“共享文件夹”选项卡（图 4‑35的处），最后点击的按钮，添加共享文件夹，进入下一步。
+.. image:: media/instal040.jpg
+   :align: center
+   :alt: 未找到图片40|
 
-|instal037|
 
-图 4‑35 设置共享文件夹
 
-(3) 图 4‑36中，点击处按钮，新增共享文件夹，在弹出的“添加共享文件夹”窗口，我们可以看到处有一个下拉箭头，我们选中处，来选择我们刚刚新建的文件夹。到这里之后，我们就完成了文件夹路径的设置。我们仍然需要让虚拟机启动的时候，自动挂载共享文件夹，见图
-4‑37。选中“自动挂载”选项，在处填入共享文件夹的挂载点，这里我们建议初学者使用我们提供的路径：
+(4) 启动虚拟机，我们就可以看到我们的共享文件夹了，见下图。
 
-/home/用户名/ebf_dir
 
-   用户名需要根据用户安装系统时，输入的用户名。本书使用的embedfire，因此，我们输入的路径为“/home/embedfire/ebf_dir”，最后点击“OK”按钮即可完成设置，见图 4‑37。
+.. image:: media/instal041.jpg
+   :align: center
+   :alt: 未找到图片41|
 
-|instal038|
 
-图 4‑36 设置共享文件夹
 
-|instal039|
 
-图 4‑37 设置自动挂载
+(5) 单击鼠标右键，左键点击"打开终端"，见下图。
 
-|instal040|
+.. image:: media/instal042.jpg
+   :align: center
+   :alt: 未找到图片42|
 
-图 4‑38 设置成功
 
-(4) 启动虚拟机，我们就可以看到我们的共享文件夹了，见图 4‑39。
 
-..
+出现如下图所示的窗口，输入命令：
 
-   |instal041|
+.. code-block:: sh
+   :emphasize-lines: 1
+   :linenos:
 
-图 4‑39共享文件夹
+   sudo usermod -a -G vboxsf 用户名
 
-(5) 单击鼠标右键，左键点击“打开终端”，见图 4‑40。
 
-|instal042|
 
-图 4‑40 打开终端
+本机的用户名是embedfire，因此，输入命令"sudo usermod –a –G vboxsf embedfire"，见下图。
 
-出现图 4‑41的窗口，输入命令：
+.. image:: media/instal043.jpg
+   :align: center
+   :alt: 未找到图片43|
 
-sudo usermod -a -G vboxsf 用户名
 
-本机的用户名是embedfire，因此，输入命令“sudo usermod –a –G vboxsf embedfire”，见图 4‑42。
 
-|instal043|
+.. image:: media/instal044.jpg
+   :align: center
+   :alt: 未找到图片44|
 
-图 4‑41 终端terminal窗口
 
-|instal044|
 
-图 4‑42 添加用户到某个用户组
+(6) 打开之后，这里为了更好地说明，因此在Windows下新建一个普通的txt文档，我们可
+    以看到Linux也可以对该文档进行操作。
+
+
+.. image:: media/instal045.jpg
+   :align: center
+   :alt: 未找到图片45|
 
-(6) 打开之后，这里为了更好地说明，因此在Windows下新建一个普通的txt文档，我们可以看到Linux也可以对该文档进行操作。
 
-..
 
-   |instal045|
 
-图 4‑43 共享文件
 
 熟悉系统
 ~~~~~~~~~~~~
 
 Ubuntu系统安装好后，请随意体验一下Ubuntu系统，看看能用它做些什么日常操作。
 
-它自带有浏览器，音乐播放器以及一些与Office功能类似的办公软件，如果安装的是中文版，中文输入法也会默认被配置好。建议使用打开浏览器看看自己的常用网站，打开系统的文件夹新建文件随便记录一些内容，甚至安装一下Steam游戏平台，看看能玩什么游戏。对于与Windows系统的差异，如不能使用MCU的开发
-软件Keil等，不能用Adobe的PS等软件，在这些方面就不要去强求和折腾。现在国产软件开始对Linux重新重视了起来，腾讯QQ也于2019-10-24回归Linux了。
+它自带有浏览器，音乐播放器以及一些与Office功能类似的办公软件，如果安装的是
+中文版，中文输入法也会默认被配置好。建议使用打开浏览器看看自己的常用网站，打开
+系统的文件夹新建文件随便记录一些内容，甚至安装一下Steam游戏平台，看看能玩什么游
+戏。对于与Windows系统的差异，如不能使用MCU的开发
+软件Keil等，不能用Adobe的PS等软件，在这些方面就不要去强求和折腾。现在
+国产软件开始对Linux重新重视了起来，腾讯QQ也于2019-10-24回归Linux了。
 
 应用列表
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 
-下面我们以Ubuntu下使用gedit编辑器编写文件为例，让大家去熟悉操作系统。在Ubuntu桌面的左下角有个应用软件列表按钮，点开后可看到系统中包含的应用，如图 4‑44。
+下面我们以Ubuntu下使用gedit编辑器编写文件为例，让大家去熟悉操作系统。在Ubuntu桌
+面的左下角有个应用软件列表按钮，点开后可看到系统中包含的应用，如下图所示。
 
-|instal046|
+.. image:: media/instal046.png
+   :align: center
+   :alt: 未找到图片46|
 
-图 4‑44 应用软件列表
 
-图 4‑44中的“文本编辑器”即是Ubuntu系统自带的gedit编辑器，直接点击后打开可以输入文字，它的使用就类似Windows系统自带的记事本软件一样。
+
+上图中的"文本编辑器"即是Ubuntu系统自带的gedit编辑器，直接点击
+后打开可以输入文字，它的使用就类似Windows系统自带的记事本软件一样。
 
 使用拼音输入法
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 
-如果安装Ubuntu系统时选择了中文支持，那么系统安装后就自带拼音输入法，其设置位置在桌面状态栏的“zh”图标中，点击后可选择汉语拼音输入法，如图 4‑45。
+如果安装Ubuntu系统时选择了中文支持，那么系统安装后就自带拼音
+输入法，其设置位置在桌面状态栏的"zh"图标中，点击后可
+选择汉语拼音输入法，如下图所示。
+
+.. image:: media/instal047.png
+   :align: center
+   :alt: 未找到图片47|
 
-|instal047|
 
-图 4‑45 使用拼音输入法
 
-|instal048|
+.. image:: media/instal048.png
+   :align: center
+   :alt: 未找到图片48|
 
-图 4‑46 文字输入
 
-该输入法使用效果如图 4‑46，使用输入法时可以通过“Shift”键快速切换中英文输入。
 
-在后面我们使用命令行的时候，建议直接把输入法关闭掉，即重新点击输入法设置的图标，把它选择回“zh”即可。
+该输入法使用效果如上图所示，使用输入法时可以通过"Shift"键快速切换中英文输入。
+
+在后面我们使用命令行的时候，建议直接把输入法关闭掉，即重新点击输入法设置的图标，把它选择回"zh"即可。
 
 文件浏览器
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 
-输入完内容后点击编辑器右侧的保存按钮，它会弹出选择文件保存位置的弹框，如图 4‑47。
+输入完内容后点击编辑器右侧的保存按钮，它会弹出选择文件保存位置的弹框，如下图所示。
+
+.. image:: media/instal049.png
+   :align: center
+   :alt: 未找到图片49|
 
-|instal049|
 
-图 4‑47 保存文件
 
-可以看到它默认的保存位置是“主目录embedfire”，这个是用户自己的目录，如果你选择其它位置，有可能会因为没有权限而无法保存。选定好存储位置并输入文件名称后，通过保存按钮可保存文件。
+可以看到它默认的保存位置是"主目录embedfire"，这个是用户自己的目
+录，如果你选择其它位置，有可能会因为没有权限而无法保存。选定好存储位
+置并输入文件名称后，通过保存按钮可保存文件。
 
-保存关闭文件后，点击桌面任务栏的文件浏览器图标，可以打开到刚刚文件存放的目录，查找到该文件，如图 4‑48。
+保存关闭文件后，点击桌面任务栏的文件浏览器图标，可以打开到刚刚
+文件存放的目录，查找到该文件，如下图所示。
+
+.. image:: media/instal050.png
+   :align: center
+   :alt: 未找到图片50|
 
-|instal050|
 
-图 4‑48文件浏览器
 
 安装软件及权限
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
-不同的Linux发行版安装应用软件的方式不尽相同，Ubuntu系统自带了软件中心，使用它可以非常方便地安装和卸载各种软件。
+不同的Linux发行版安装应用软件的方式不尽相同，Ubuntu系统自
+带了软件中心，使用它可以非常方便地安装和卸载各种软件。
+
+在桌面的任务栏有"Ubuntu软件"图标，如下图所示，点击后可以打开软件中心。
+
+.. image:: media/instal051.jpg
+   :align: center
+   :alt: 未找到图片51|
+
+
+
+我们尝试安装"2048"小游戏。打开软件之后，点击搜索
+的按钮（下图中的框框处），输入"2048"，如下图所示，点击安装框框处的"2048"游戏。
+
+.. image:: media/instal052.jpg
+   :align: center
+   :alt: 未找到图片52|
+
+
+
+.. image:: media/instal053.png
+   :align: center
+   :alt: 未找到图片53|
 
-在桌面的任务栏有“Ubuntu软件”图标，图 4‑49所示，点击后可以打开软件中心。
 
-|instal051|
 
-图 4‑49 Ubuntu软件
+安装软件时，可能会弹出如下图所示的提示，由于需要系统管理员的权限，所以要
+输入密码进行认证，该密码为安装系统时设置的用户密码。
 
-我们尝试安装“2048”小游戏。打开软件之后，点击搜索的按钮（图 4‑50中的框框处），输入“2048”，如图 4‑51所示，点击安装框框处的“2048”游戏。
+.. image:: media/instal054.png
+   :align: center
+   :alt: 未找到图片54|
 
-|instal052|
 
-图 4‑50 Ubuntu软件中心全貌
 
-|instal053|
+在Linux系统下，所有的操作都有明确的权限要求。如安装软
+件需要系统管理员权限；普通用户在自己所属的目录下才能创建文件等。
 
-图 4‑51小游戏2048
+目前Ubuntu软件中心采用Snap软件市场来安装软件，暂时还
+没有国内的镜像下载源，所以下载可能需要花比较长的时间。如果不想体验可以直接点击取消安装。
 
-安装软件时，可能会弹出如图 4‑52的提示，由于需要系统管理员的权限，所以要输入密码进行认证，该密码为安装系统时，图 4‑28中设置的用户密码。
 
-|instal054|
 
-图 4‑52 认证提示
 
-在Linux系统下，所有的操作都有明确的权限要求。如安装软件需要系统管理员权限；普通用户在自己所属的目录下才能创建文件等。
 
-目前Ubuntu软件中心采用Snap软件市场来安装软件，暂时还没有国内的镜像下载源，所以下载可能需要花比较长的时间。如果不想体验可以直接点击取消安装。
 
 .. |instal002| image:: media/instal002.jpeg
    :width: 2.77273in
diff --git a/documentation/linux_basis/led_key_command_line_testing.rst b/documentation/linux_basis/led_key_command_line_testing.rst
index 5c6624e0b69b3a3a51b6f59bc781e7c9591a9187..bf8106b5732ebcd7551bd3d4b14a233e6ded9458 100644
--- a/documentation/linux_basis/led_key_command_line_testing.rst
+++ b/documentation/linux_basis/led_key_command_line_testing.rst
@@ -1,181 +1,246 @@
 .. vim: syntax=rst
 
-使用命令点灯和检测按键
+命令行点灯和检测按键
 -----------
+**注意:目前发布的Debian镜像只使能了LED灯，没有使能呼吸灯，本章节中的呼吸灯相关操作需要在下一个版本的Debian镜像中操作**
 
-前面讲了那么多的内容，终于迎来了重头戏——使用开发板的各种硬件外设，如入门必备的点灯，按键，蜂鸣器，串口等等。本章先带领大家使用命令行来控制LED灯和检测按键。
+前面讲了那么多的内容，终于迎来了重头戏——使用开发板的各种硬
+件外设，如入门必备的点灯，按键，蜂鸣器，串口等等。本章先带领大家使用命令行来控制LED灯和检测按键。
 
 初探/sys目录
 ~~~~~~~~
 
-与/proc目录类似，/sys目录下的文件/文件夹向用户提供了一些关于设备、内核模块、文件系统以及其他内核组件的信息，如子目录block中存放了所有的块设备；子目录bus中存放了系统中所有的总线类型，有i2c、usb、sdio、pci等；子目录class按类型归类设备，如leds、lcd、mtd、p
+与/proc目录类似，/sys目录下的文件/文件夹向用户提供了一些关
+于设备、内核模块、文件系统以及其他内核组件的信息，如子目录block中存
+放了所有的块设备；子目录bus中存放了系统中所有的总线类型，有i2c、usb、sdio、pci等；子
+目录class按类型归类设备，如leds、lcd、mtd、p
 wm等。
 
-尝试在开发板的终端执行以下命令查看sys各层级的目录内容：
-
-#在开发板上的终端执行以下命令查看
 
-ls /sys
+尝试在开发板的终端执行以下命令查看sys各层级的目录内容：
 
-ls /sys/class
+.. code-block:: sh
+   :linenos:
 
-ls /sys/class/leds
+   #在开发板上的终端执行以下命令查看
+   ls /sys
+   ls /sys/class
+   ls /sys/class/leds
+   ls /sys/class/leds/cpu
 
-ls /sys/class/leds/cpu
 
-|ledkey002|
+.. image:: media/ledkey002.png
+   :align: center
+   :alt: 未找到图片02|
 
-图 13‑1 /sys各目录的内容（内容可能会小有差异）
 
-可以看到，本开发板的/sys/class/leds目录下分别有：blue、cpu、green、red等目录（出厂的），它们代表着开发板上不同的LED灯，是由Linux内核驱动提供给用户的控制接口。
+可以看到，本开发板的/sys/class/leds目录下分别
+有：blue、cpu、green、red等目录（出厂的），它们代表着开
+发板上不同的LED灯，是由Linux内核驱动提供给用户的控制接口。
 
-以其中的/sys/class/leds/cpu目录为例，它下面又包含brightness、device、max_brightness、power、subsystem、trigger、uevent等文件。其中brightness表示LED灯的亮度，trigger表示LED灯的触发方式，我们可以通过ec
-ho、cat等命令来修改或查看这些文件，从而达到控制LED灯的目的。下面以实例进行讲解。
+以其中的/sys/class/leds/cpu目录为例，它下面又
+包含brightness、device、max_brightness、power、subsystem、trigger、uevent等文
+件。其中brightness表示LED灯的亮度，trigger表示LED灯的触发方式，我们可以通过echo、
+cat等命令来修改或查看这些文件，从而达到控制LED灯的目的。下面以实例进行讲解。
 
 控制LED灯
 ~~~~~~
 
-在野火的i.MX 6ULL Pro及Mini开发板上，有如下几个LED灯可以通过主控芯片的引脚进行控制，硬件的具体位置见《第10章 野火EBF 6ULL 开发板硬件资源介绍》章节的资源图：
+在野火的i.MX 6ULL Pro及Mini开发板上，有如下几个LED灯
+可以通过主控芯片的引脚进行控制，硬件的具体位
+置见《野火EBF 6ULL 开发板硬件资源介绍》章节的资源图：
 
--  心跳灯：默认用来指示系统运行状态，系统正在运行时就会持续闪烁。开发板文件系统上的/sys/class/leds/cpu目录表示的就是该心跳灯。
+-  心跳灯：默认用来指示系统运行状态，系统正在运行时
+   就会持续闪烁。开发板文件系统上的/sys/class/leds/cpu目录表示的就是该心跳灯。
 
--  三盏普通LED灯：在Pro开发板上，它们共同组成一盏RGB彩灯，可以进行色彩混合。在Mini开发板上是三盏独立的小灯。开发板文件系统上的/sys/class/leds/red、/sys/class/leds/blue、/sys/class/leds/green目录表示的就是这三盏灯。
+-  三盏普通LED灯：在Pro开发板上，它们共同组成一盏RGB彩
+   灯，可以进行色彩混合。在Mini开发板上是三盏独立的小灯。开发板文件系
+   统上的/sys/class/leds/red、/sys/class/leds/blue、/sys/class/leds/green目录表示的就是这三盏灯。
 
 brightness文件
 ^^^^^^^^^^^^
 
-各LED灯设备下的brightness文件表示了它的亮度值。本开发板提供的内核驱动中，心跳灯是直接IO控制的，它的亮度范围为1和0表示亮灭；而其它三盏普通LED灯是使用pwm控制的，支持的亮度范围为0~255。
-
-我们先尝试控制三盏普通LED灯，在开发板的终端上执行如下命令，执行前请确认当前为root用户：
-
-#在后面的说明中，#号表示注释，它后面的内容不要输入到终端中
-
-#LED灯默认可能处于亮的状态，我们先把它们全部关闭再一盏盏点亮
+各LED灯设备下的brightness文件表示了它的亮
+度值。本开发板提供的内核驱动中，心跳灯是直接IO控制的，它的亮度
+范围为1和0表示亮灭；而其它三盏普通LED灯是使用pwm控制的，支持的亮度范围为0~255。
 
-echo 0 > /sys/class/leds/red/brightness #关闭red灯
+我们先尝试控制三盏普通LED灯，在开发板的终端上执行如下
+命令，执行前请确认当前为root用户：
 
-echo 0 > /sys/class/leds/blue/brightness #关闭blue灯
+.. code-block:: sh
+   :linenos:
 
-echo 0 > /sys/class/leds/green/brightness #关闭green灯
+   #LED灯默认可能处于亮的状态，我们先把它们全部关闭再一盏盏点亮
+   echo 0 > /sys/class/leds/red/brightness #关闭red灯
+   echo 0 > /sys/class/leds/blue/brightness #关闭blue灯
+   echo 0 > /sys/class/leds/green/brightness #关闭green灯
+   echo 255 > /sys/class/leds/red/brightness #点亮red灯
+   echo 255 > /sys/class/leds/blue/brightness #点亮blue灯
+   echo 255 > /sys/class/leds/green/brightness #点亮green灯
 
-echo 255 > /sys/class/leds/red/brightness #点亮red灯
+.. image:: media/ledkey003.png
+   :align: center
+   :alt: 未找到图片03|
 
-echo 255 > /sys/class/leds/blue/brightness #点亮blue灯
 
-echo 255 > /sys/class/leds/green/brightness #点亮green灯
 
-|ledkey003|
-
-图 13‑2 完全关闭RGB灯后，点亮GREEN灯
-
-在Pro开发板中，由于三盏灯会进行硬件RGB混色，所以随着每条指令的执行，彩灯的颜色不一定呈红蓝绿的变化，而是三盏灯状态的共同结果，可以自行尝试使用不同的亮度值对RGB灯进行混色。
+在Pro开发板中，由于三盏灯会进行硬件RGB混色，所以随着每条指
+令的执行，彩灯的颜色不一定呈红蓝绿的变化，而是三盏灯状态的
+共同结果，可以自行尝试使用不同的亮度值对RGB灯进行混色。
 
 在Mini开发板上三盏LED是硬件独立的，可以更明显地看出执行不同指令时硬件的运行情况。
 
 trigger文件
 ^^^^^^^^^
 
-如果我们直接使用上面的方式去控制/sys/class/leds/cpu心跳灯的brightness文件，发现并没有生效，心跳灯依然是按自己的节奏在闪烁，这是因为我们的驱动中心跳灯与上述普通LED灯使用了不同的默认触发条件。LED灯的触发条件可以通过其目录下的trigger文件控制。
+如果我们直接使用上面的方式去控制/sys/class/leds/cpu心跳灯
+的brightness文件，发现并没有生效，心跳灯依然是按自己的节奏在
+闪烁，这是因为我们的驱动中心跳灯与上述普通LED灯使用了不同的默
+认触发条件。LED灯的触发条件可以通过其目录下的trigger文件控制。
 
 我们先来查看各LED设备trigger文件的原内容：
 
-#在后面的说明中，#号表示注释，它后面的内容不要输入到终端中
+.. code-block:: sh
+   :linenos:
+
+   cat /sys/class/leds/red/trigger #查看red灯的trigger文件内容
+   cat /sys/class/leds/cpu/trigger #查看cpu灯的trigger文件内容
 
-cat /sys/class/leds/red/trigger #查看red灯的trigger文件内容
+.. image:: media/ledkey004.png
+   :align: center
+   :alt: 未找到图片04|
 
-cat /sys/class/leds/cpu/trigger #查看cpu灯的trigger文件内容
 
-|ledkey004|
 
-图 13‑3 各LED灯的默认trigger配置
+仔细对比上图中red及cpu灯的trigger文件内容，发现两个文
+件中有类似的内容，这些内容表示触发条件，其中"[]"括号括起来的表示当前使
+用的触发方式。可看到red灯中的触发条件为"none"，表示无触发条件，所以直接
+修改brightness文件来控制；而cpu灯的触发条件为"heartb
+eat"，表示系统心跳指示触发，这时用户不能再直接修改brightness文件来
+控制。
 
-仔细对比图 13‑3中red及cpu灯的trigger文件内容，发现两个文件中有类似的内容，这些内容表示触发条件，其中“[]”括号括起来的表示当前使用的触发方式。可看到red灯中的触发条件为“none”，表示无触发条件，所以直接修改brightness文件来控制；而cpu灯的触发条件为“heartb
-eat”，表示系统心跳指示触发，这时用户不能再直接修改brightness文件来控制。其它的触发条件如nand-disk表示nand读写指示灯，timer表示通过定时器控制等。
+了解触发条件后，我们可以先把cpu灯的触发条件改为none，再
+修改brightness文件即可以手动控制cpu灯，尝试执行如下命令：
 
-了解触发条件后，我们可以先把cpu灯的触发条件改为none，再修改brightness文件即可以手动控制cpu灯，尝试执行如下命令：
+.. code-block:: sh
+   :linenos:
 
-#在后面的说明中，#号表示注释，它后面的内容不要输入到终端中
+   echo none > /sys/class/leds/cpu/trigger #修改cpu灯触发条件为none
+   cat /sys/class/leds/cpu/trigger #查看cpu灯的trigger文件内容
+   echo 1 > /sys/class/leds/cpu/brightness # 点亮cpu灯
+   echo 0 > /sys/class/leds/cpu/brightness #关闭cpu灯
 
-echo none > /sys/class/leds/cpu/trigger #修改cpu灯触发条件为none
+.. image:: media/ledkey005.png
+   :align: center
+   :alt: 未找到图片05|
 
-cat /sys/class/leds/cpu/trigger #查看cpu灯的trigger文件内容
 
-echo 1 > /sys/class/leds/cpu/brightness # 点亮cpu灯
 
-echo 0 > /sys/class/leds/cpu/brightness #关闭cpu灯
+类似地，我们可以把red灯的触发条件改为heartbeat，此时red灯就会以心跳指示的方式进行闪烁：
 
-|ledkey005|
 
-图 13‑4 修改cpu灯的触发条件并控制
+.. code-block:: sh
+   :linenos:
 
-类似地，我们可以把red灯的触发条件改为heartbeat，此时red灯就会以心跳指示的方式进行闪烁：
+   echo heartbeat > /sys/class/leds/red/trigger
 
-echo heartbeat > /sys/class/leds/red/trigger
+.. image:: media/ledkey006.png
+   :align: center
+   :alt: 未找到图片06|
 
-|ledkey006|
 
-图 13‑5 把red灯改为heartbeat触发
 
-在示例中我们一直是用echo命令修改文件内容来达到控制的目的，但我们要清楚地知道，并不是echo命令能控制硬件，而是文件的内容影响了硬件的工作状态。可以尝试使用Vi编辑器来修改各个LED灯的brightness文件的内容，完全可以达到同样的控制目的。不过使用Vi时可能会提示权限问题，忽略即可。
+在示例中我们一直是用echo命令修改文件内容来达到控制的目的，但我
+们要清楚地知道，并不是echo命令能控制硬件，而是文件的内容影响了硬
+件的工作状态。可以尝试使用Vi编辑器来修改各个LED灯的brightness文件
+的内容，完全可以达到同样的控制目的。不过使用Vi时可能会提示权限问题，忽略即可。
 
 初探/dev目录
 ~~~~~~~~
 
-除了/proc和/sys目录外，/dev目录也包含了非常丰富的设备信息，该目录下包含了Linux系统中使用的所有外部设备，如/dev/tty为串口设备、/dev/ram为内存、通过这些设备文件，我们也可以访问到对应的硬件设备。
+除了/proc和/sys目录外，/dev目录也包含了非常丰富的设备信息，该目
+录下包含了Linux系统中使用的所有外部设备，如/dev/tty为串口
+设备、/dev/ram为内存、通过这些设备文件，我们也可以访问到对应的硬件设备。
 
 尝试使用以下命令查看dev目录的内容：
 
-ls /dev
+.. code-block:: c
+   :caption: 看dev目录的内容
+   :linenos:
 
-ls /dev/input
+   ls /dev
+   
+   ls /dev/input
 
-|ledkey007|
+.. image:: media/ledkey007.png
+   :align: center
+   :alt: 未找到图片07|
 
-图 13‑6 /dev目录的部分内容
 
-以图 13‑6中/dev/input目录下的内容为例，上面包含了event0/1/2/3等内容，它们是输入设备的事件文件接口，通过它们可以获知设备上报的输入事件。event后带的数字并不是跟设备绑定的，可以查看文件/proc/bus/input/devices了解它们分别代表什么。
 
-在开发板的终端执行以下命令：
+以上图中/dev/input目录下的内容为例，上面的event0是输入设备的事件文件接口，
+通过它们可以获知设备上报的输入事件。event后带的数字并不是跟设备绑定的，
+可以查看文件/proc/bus/input/devices了解它们分别代表什么。
 
-cat /proc/bus/input/devices
+在开发板的终端执行以下命令：
 
-|ledkey008|
+.. code-block:: sh
+   :linenos:
 
-图 13‑7 查看输入设备（具体内容可能有差异）
+   cat /proc/bus/input/devices
 
-如图 13‑7，可看到当前开发板的包含了四个输入设备，在具体的开发板上可能会有差异：
+.. image:: media/ledkey008.png
+   :align: center
+   :alt: 未找到图片08|
 
--  event0：名称为20cc000.snvs:snvs-powerkey，它对应的硬件是开发板上的ON/OFF按键。
 
--  event1：名称为goodix-ts，它对应的是触摸屏设备，若没接入触摸屏可能会见不到该设备
 
--  event2：名称为gpio_ir_recv，它对应的是红外接收器，我们提供的部分内核驱动可能不包含红外接收器，该设备可能不存在。
+如上图所示，可看到当前开发板的只包含了一个输入设备，在具体的开发板上可能会有差异：
 
--  event3：名称为gpio_keys，它对应的是KEY按键。
+-  event0：名称为gpio_keys，它对应的是KEY按键。
 
 检测按键
 ~~~~
 
-在开发板的文件系统中我们提供了evtest工具，使用它可以更方便地查看硬件当前接入的输入设备，并且对其进行检测。
+在开发板中，我们可以使用evtest工具更方便地查看硬件当前接入的输入设备，
+并且对其进行实时检测。
+
+apt安装evtest工具
+
+.. code-block:: sh
+   :linenos:
+
+   sudo apt install evtest
+
+**注意**:第一次使用apt install命令前，需要先执行以下执行刷新镜像源
+
+.. code-block:: sh
+   :linenos:
 
-在开发板的终端上输入如下命令：
+   sudo apt update
 
-evtest
+使用evtest工具：
 
-|ledkey009|
+.. code-block:: sh
+   :linenos:
 
-图 13‑8 evtest查看可用的输入设备（视具体的接入设备有差异）
+   evtest
 
-执行命令后，它会扫描/dev/input目录下的event设备输入事件文件，并列出到终端，它提示我们可以通过数字选择对应的设备进行测试，具体请根据自己开发板上的输出进行选择。此处我们以snvs-powerkey和gpio-keys为例，测试结果如图 13‑9和图
-13‑10所示。测试时可执行“Ctrl”+“c”退出。
+.. image:: media/ledkey009.png
+   :align: center
+   :alt: 未找到图片09|
 
-|ledkey010|
 
-图 13‑9 ON/OFF按键的测试
 
-|ledkey011|
+执行命令后，它会扫描/dev/input目录下的event设备输入事件文件，并列
+出到终端，它提示我们可以通过数字选择对应的设备进行测试，具体请根据自己
+开发板上的输出进行选择。此处我们以gpio-keys为例，测试结果如下图所示。测试
+时可执行"Ctrl"+"c"退出。
+
+.. image:: media/ledkey011.png
+   :align: center
+   :alt: 未找到图片11|
 
-图 13‑10 KEY按键的测试
 
 设备、文件与驱动
 ~~~~~~~~
@@ -188,6 +253,11 @@ evtest
 
 所以说，驱动工程师所做的工作就是把硬件的控制方式抽象、封装成为函数API或者文件，只不过Linux驱动工程师在封装时需要按照Linux的规范去编写，而且在编写时需要了解Linux内核的一些机制，所以相对裸机驱动来说，提出了更高的要求。
 
+
+
+
+
+
 .. |ledkey002| image:: media/ledkey002.png
    :width: 5.76806in
    :height: 1.22371in
diff --git a/documentation/linux_basis/linux_brief.rst b/documentation/linux_basis/linux_brief.rst
index bd5355d4c6889d704052bc3580237a80079724af..1182e1d572faae3b50790d06de224c7b83600ce5 100644
--- a/documentation/linux_basis/linux_brief.rst
+++ b/documentation/linux_basis/linux_brief.rst
@@ -18,32 +18,49 @@ Linux系统由Linus Torvalds （林纳斯·托瓦兹）于1991年发布在新闻
 
 当我们说Linux系统时，其含义往往是指采用Linux内核的操作系统。Linux内核负责控制硬件、管理文件系统、进程管理、网络通讯等，但它本身并没有给用户提供必要的工具和应用软件。
 
-由于Linux内核本身是开源的，所以一些人和厂商在其规则之下，基于Linux内核搭配各种各样系统管理软件或应用工具软件，从而组成一套完整可用的操作系统，见图
-3‑1。我们称这样的系统为Linux发行版（distribution）。完整的Linux系统就如同汽车，Linux内核构成了最为关键的引擎，不同的发行版就类似使用相同引擎的不同车型。
+由于Linux内核本身是开源的，所以一些人和厂商在其规则之下，基于Linux内核搭配各种各样系统管理软件或
+应用工具软件，从而组成一套完整可用的操作系统，见下图。我们称这样的系
+统为Linux发行版（distribution）。完整的Linux系统就如同
+汽车，Linux内核构成了最为关键的引擎，不同的发行版就类似使用相同引擎的不同车型。
 
-|linuxb002|
+.. image:: media/linuxb002.bmp
+   :align: center
+   :alt: 未找到图片
 
 图 3‑1 Linux系统的完整构成
 
-人们制作发行版通常用于特定的用途，构建哲学不一，侧重点有所不同，因而Linux发行版可谓百花齐放。其中以Debian、Suse及Fedora派系的发行版最为常见。对于基础用户来说，常常会困惑于安装某些软件时，软件的安装帮助会针对不同派系的Linux给出不同的安装指令，这实际是由于不同Linux派系之
-间使用不同的包管理软件（可理解为使用不同的软件商店），这无伤大雅。常见的Linux发行版关系见图 3‑2。
+人们制作发行版通常用于特定的用途，构建哲学不一，侧重点有所不同，因
+而Linux发行版可谓百花齐放。其中以Debian、Suse及Fedora派系的发行版最
+为常见。对于基础用户来说，常常会困惑于安装某些软件时，软件的安装帮助会针
+对不同派系的Linux给出不同的安装指令，这实际是由于不同Linux派系之
+间使用不同的包管理软件（可理解为使用不同的软件商店），这无伤大雅。常见的Linux发行版关系见下图。
+
+.. image:: media/linuxb003.bmp
+   :align: center
+   :alt: 未找到图片
+
 
-|linuxb003|
 
 图 3‑2 常见的Linux发行版关系图
 
-对于初次接触Linux的用户，建议只要了解到这些都是Linux系统，而且目前我们的开发主机要用的是Ubuntu即可。至于在开发板上运行的Linux系统，也可以理解为这是我们针对特定板子而定制的Linux发行版。
+对于初次接触Linux的用户，建议只要了解到这些都是Linux系统，而且目前我们
+的开发主机要用的是Ubuntu即可。至于在开发板上运行的Linux系统，也可以理
+解为这是我们针对特定板子而定制的Linux发行版。
 
 Debian派系
 ^^^^^^^^^^^^^^^^
 
 Debian派系下主要包含Debian、Ubuntu等发行版。
 
-Debian的特色在于其海量的软件支持和apt-get软件包管理系统，而且其支持的硬件平台非常全面，包括x86、AMD、MIPS、ARM、POWERPC等。
+Debian的特色在于其海量的软件支持和apt-get软件包管理系统，而且其支持的硬件
+平台非常全面，包括x86、AMD、MIPS、ARM、POWERPC等。
 
-Ubuntu衍生自Debian，由于其易用性，可以说是最成功的Linux桌面版，且它的成功已经开始漫延至其服务器版本，目前还推出了Ubuntu Core版本针对物联网等小型设备领域，非常有发展前景。本书将采用Ubuntu作为开发主机的系统环境。
+Ubuntu衍生自Debian，由于其易用性，可以说是最成功的Linux桌
+面版，且它的成功已经开始漫延至其服务器版本，目前还推出了Ubuntu Core版本
+针对物联网等小型设备领域，非常有发展前景。本书将采用Ubuntu作为开发主机的系统环境。
 
-Debian和Ubuntu官网有非常丰富的使用教程，而且中文支持也很好，推荐初学者多多浏览其中的内容，尤其是Debian。
+Debian和Ubuntu官网有非常丰富的使用教程，而且中文支持也很好，推
+荐初学者多多浏览其中的内容，尤其是Debian。
 
 Debian官网：https://www.debian.org
 
@@ -54,24 +71,36 @@ Fedora派系
 
 Fedora派系下包含Fedora、Red Hat Linux、Red Hat Enterprise（RHEL）、CentOS等发行版。
 
-Red Hat Linux是由Red Hat（红帽）发行的个人版本Linux，现已停止开发，他们转而开发主要应用于服务器领域的Red Hat Enterprise
-Linux（RHEL），即红帽企业版Linux。使用RHEL的好处是获得安全稳定的技术支持以及企业级的保证，这正是众多服务器应用场景的核心需求，红帽公司也正是依靠提供这些服务成为了最赚钱的Linux公司。现红帽公司已被IBM收购。
+Red Hat Linux是由Red Hat（红帽）发行的个人版本Linux，现已停止开发，他们转而
+开发主要应用于服务器领域的Red Hat Enterprise
+Linux（RHEL），即红帽企业版Linux。使用RHEL的好处是获得安全稳定的技术支持以
+及企业级的保证，这正是众多服务器应用场景的核心需求，红帽公司也正是依靠提供这
+些服务成为了最赚钱的Linux公司。现红帽公司已被IBM收购。
 
-Fedora发行版是由社区基于RHEL构建的，由Red Hat公司赞助，它大胆采用和验证最新的技术，部分经验证的技术会被加入至RHEL。因而Fedora与RHEL是被互惠互利关系。从另一个角度看，Fedora也被认为是RHEL的小白鼠版本。
+Fedora发行版是由社区基于RHEL构建的，由Red Hat公司赞助，它大胆采用和验证最
+新的技术，部分经验证的技术会被加入至RHEL。因而Fedora与RHEL是被互惠互利关系。从另
+一个角度看，Fedora也被认为是RHEL的小白鼠版本。
 
 CentOS全名为Community Enterprise Operation
-System，即社区企业操作系统，它由红帽遵循开源协议公开的RHEL源代码构建而成，它们的区别在于CentOS提供免费的长期升级和更新服务，使用CentOS相当于使用RHEL而不寻求红帽的技术支持，CentOS在我国的小型服务器领域应用非常广泛。
+System，即社区企业操作系统，它由红帽遵循开源协议公开的RHEL源代码构建而
+成，它们的区别在于CentOS提供免费的长期升级和更新服务，使用CentOS相当于
+使用RHEL而不寻求红帽的技术支持，CentOS在我国的小型服务器领域应用非常广泛。
 
 Open SUSE派系
 ^^^^^^^^^^^^^^^^^^^
 
-SUSE派系下包含SUSE、SUSE Linux Enterprise Server（SLES）、openSUSE等发行版，它们的关系类似于Fedora， Red Hat Enterprise Linux（RHEL） 和CentOS的关系。相对Red
+SUSE派系下包含SUSE、SUSE Linux Enterprise Server（SLES）、openSUSE等发行版，
+它们的关系类似于Fedora， Red Hat Enterprise Linux（RHEL） 和CentOS的关系。相对Red
 Hat专长x86架构的计算机来说，SUSE在诞生之初就瞄准大型机，所以SUSE在大型服务器领域占有一席之地。
 
 麒麟
 ^^^^^^^^^^^^^^^^^^
 
-由于军政系统对信息安全要求严格，我国基于Linux内核构建了中标麒麟、优麒麟、银河麒麟等发行版，其特色主要在于自主、风险可控。
+由于军政系统对信息安全要求严格，我国基于Linux内核构建了中标
+麒麟、优麒麟、银河麒麟等发行版，其特色主要在于自主、风险可控。
+
+
+
 
 .. |linuxb002| image:: media/linuxb002.bmp
    :width: 3.78333in
diff --git a/documentation/linux_basis/linux_directory.rst b/documentation/linux_basis/linux_directory.rst
index fa1c7c68e2994fe55c6872f5b1eda9535f0f63a3..2e6c13b82dcda13eecb28b8d5eaae3c3e9b1d59b 100644
--- a/documentation/linux_basis/linux_directory.rst
+++ b/documentation/linux_basis/linux_directory.rst
@@ -8,23 +8,32 @@ Linux文件目录
 家目录
 ~~~~~~~~~~~~
 
-当尝试使用gedit等编辑器保存文件时，系统默认通常会先打开个人用户的“家”目录，建议在通常情况下个人相关的内容也是保存在该目录中，因为其它目录大都是系统相关的，使用时容易导致混乱，而且需要相关权限。
+当尝试使用gedit等编辑器保存文件时，系统默认通常会先打开个人用户的"家"目录，建议在通常情况下个人相关的内容也是保存在该目录中，因为其它目录大都是系统相关的，使用时容易导致混乱，而且需要相关权限。
 
-点击Ubuntu系统侧栏的文件图标，如图 5‑1，可以打开系统的文件资源管理器。
+点击Ubuntu系统侧栏的文件图标，如下图所示，可以打开系统的文件资源管理器。
 
-|linuxd002|
 
-图 5‑1 文件图标
 
-打开后可以看到当前用户的主文件夹目录，也称为个人的“家”目录，“home”目录，它与Win10系统的个人目录非常相似，具体见图 5‑2和图 5‑3。
 
-|linuxd003|
+.. image:: media/linuxd002.png
+   :align: center
+   :alt: 未找到图片02|
 
-图 5‑2 Ubuntu个人目录
 
-|linuxd004|
 
-图 5‑3 Win10个人目录
+打开后可以看到当前用户的主文件夹目录，也称为个人的"家"目录，"home"目录，它与Win10系统的个人目录非常相似，具体见下图。
+
+.. image:: media/linuxd003.jpg
+   :align: center
+   :alt: 未找到图片03|
+
+
+
+.. image:: media/linuxd004.jpg
+   :align: center
+   :alt: 未找到图片04|
+
+
 
 Ubuntu和Win10希望用户使用时个人的内容都存放在个人目录，主要是为了与系统核心文件区分开来，因为通常不希望普通用户修改系统相关的内容，而且人个目录分开也便于系统升级。
 
@@ -33,26 +42,36 @@ Ubuntu和Win10希望用户使用时个人的内容都存放在个人目录，主
 根目录
 ~~~~~~~~~~~~
 
-根目录是Linux下所有文件和目录的起点，它的路径用斜杠符号“/”来表示。如图 5‑4，通过点击文件浏览器的“/其他位置/计算机”可以查看到整个Ubuntu系统的根目录内容。
+根目录是Linux下所有文件和目录的起点，它的路径用斜杠符号"/"来表示。如下图所示，通过点击文件浏览器的"/其他位置/计算机"可以查看到整个Ubuntu系统的根目录内容。
+
+.. image:: media/linuxd005.jpg
+   :align: center
+   :alt: 未找到图片05|
+
+
 
-|linuxd005|
+打开目录后，可以查看到Ubuntu系统根目录的内容，如下图。
 
-图 5‑4 点击查看计算机的其它文件
+.. image:: media/linuxd006.jpg
+   :align: center
+   :alt: 未找到图片06|
 
-打开目录后，可以查看到Ubuntu系统根目录的内容，如图 5‑5。
 
-|linuxd006|
 
-图 5‑5 Ubuntu根目录的内容
+也就是说，上图中这些文件或文件夹都位于"/"目录下，而它们的路径分别为"/bin"、"/boot"、"/cdrom"、"/initrd.img"等。
 
-也就是说，图 5‑5中这些文件或文件夹都位于“/”目录下，而它们的路径分别为“/bin”、“/boot”、“/cdrom”、“/initrd.img”等。
+特别地，前面说明的家目录（个人目录）路径为“/home/用户名/”，见下图，图中
+的例子目录是**/home/embedfire**。也就是说，在Ubuntu系统下，用户的个人目
+录都在“/home”下，并且按照用户名命名，如果系统下有
+多个用户A、B、C并且它们都有个人目录的话，那么它们的个人目录路径默认
+就是/home/A，/home/B，/home/C。在这方面，跟Windows系统是
+类似的，在Windows系统下，个人目录默认是“C:/Users”或“C:/用户”。
 
-特别地，前面说明的家目录（个人目录）路径为“/home/用户名/”，见图 5‑6，图中的例子目录是/home/embedfire。也就是说，在Ubuntu系统下，用户的个人目录都在“/home”下，并且按照用户名命名，如果系统下有多个用户A、B、C并且它们都有个人目录的话，那么它们的个人目录路径默认
-就是/home/A，/home/B，/home/C。在这方面，跟Windows系统是类似的，在Windows系统下，个人目录默认是“C:/Users”或“C:/用户”。
+.. image:: media/linuxd007.jpg
+   :align: center
+   :alt: 未找到图片07|
 
-|linuxd007|
 
-图 5‑6 家目录的完整路径
 
 对于Linux开发者来说，必须要了解根目录的内容，这也是大部分人觉得Linux的不友好之处。如果我们把/home的个人目录排除掉，实质上Linux的根目录与Windows系统C:/Windows目录的功能类似，都是系统核心的文件，只是对于Windows用户通常不需要了解系统文件目录罢了。如果把Lin
 ux系统用于普通的桌面应用，实际上也不需要多么了解它的根目录内容。
@@ -63,34 +82,42 @@ ws有独立的盘符可以访问，而是默认挂载在/media目录下。
 根目录结构
 ~~~~~~~~~~~~~~
 
-整个Linux系统有且只有一棵从根目录开始的目录树，如图 5‑7。
+整个Linux系统有且只有一棵从根目录开始的目录树，如下图所示。
 
-|linuxd008|
+.. image:: media/linuxd008.png
+   :align: center
+   :alt: 未找到图片08|
 
-图 5‑7 根目录结构图
 
-所以如果一个计算机中如果有多个硬盘，也不会呈现出Windows下的C、D、E盘的结构，强行复制Windows下习惯的话，可以在根目录下创建C、D、E目录，然后把磁盘C、D、E挂载在/C、/D或/E目录下，即它们仍然从属于“/”根目录，不过在Linux下通常不会这么用。
 
-目录树只是一个管理上的概念，它本身并不跟硬件挂钩的，例如这些文件之所以是存储在磁盘中，是因为在安装系统时，已经把整个根目录“挂载”在了磁盘上。所谓挂载就是把存储器的分区与某个目录对应起来，当对访问该目录时，相应的操作会被映射到其挂载的存储器分区，而这些存储器包括磁盘、光盘、U盘、NAND
+所以如果一个计算机中如果有多个硬盘，也不会呈现出Windows下的C、D、E盘的结构，强行复制Windows下习惯的话，可以在根目录下创建C、D、E目录，然后把磁盘C、D、E挂载在/C、/D或/E目录下，即它们仍然从属于"/"根目录，不过在Linux下通常不会这么用。
+
+目录树只是一个管理上的概念，它本身并不跟硬件挂钩的，例如这些文件之所以是存储在磁盘中，是因为在安装系统时，已经把整个根目录"挂载"在了磁盘上。所谓挂载就是把存储器的分区与某个目录对应起来，当对访问该目录时，相应的操作会被映射到其挂载的存储器分区，而这些存储器包括磁盘、光盘、U盘、NAND
 FLASH等。
 
-给电脑插入U盘，系统会自动把U盘挂载在“/media/用户名/”目录下，打开该目录即可访问U盘进行读写，另外，在桌面也会看到一个U盘的快捷方式，通过该快捷方式访问的也是同样的目录。使用VirtualBox虚拟机时，要注意把U盘分配到虚拟机，见图 5‑8、图 5‑9和图 5‑10。
+给电脑插入U盘，系统会自动把U盘挂载在"/media/用户名/"目录下，打开该目录即可访问U盘进行读写，另外，在桌面也会看到一个U盘的快捷方式，通过该快捷方式访问的也是同样的目录。使用VirtualBox虚拟机时，要注意把U盘分配到虚拟机，见图 5‑8、图 5‑9和图 5‑10。
+
+.. image:: media/linuxd009.jpg
+   :align: center
+   :alt: 未找到图片09|
+
 
-|linuxd009|
 
-图 5‑8 把U盘分配到虚拟机
+.. image:: media/linuxd010.png
+   :align: center
+   :alt: 未找到图片10|
 
-|linuxd010|
 
-图 5‑9 /media/embedfire目录下的U盘
 
-|linuxd011|
+.. image:: media/linuxd011.png
+   :align: center
+   :alt: 未找到图片11|
 
-图 5‑10 桌面下的U盘快捷方式
 
-不同的发行版对根目录的理解不同，但它们大都遵守文件层次标准（FHS， Filesystem Hierarchy Standard），所以根目录下的各个子目录内容和功能大致如表 5‑1所示。
+不同的发行版对根目录的理解不同，但它们大都遵守文件层次标准（FHS， Filesystem Hierarchy Standard），所以根
+目录下的各个子目录内容和功能大致如下表所示。
 
-表 5‑1 根目录的内容
+表    根目录的内容
 
 =========== ==================================================================================================================================
 目录        目录放置的内容
@@ -124,18 +151,22 @@ var         存放内容常变动的文件目录，如系统日志文件
 
 /bin目录是/binary的缩写，它包含众多普通用户可用的命令。而命令的本质就是可执行程序，二进制bin文件。熟悉Linux命令后，回头再来本目录看看，会发现ls、cp、cat等命令，都可以在此处找到，具体见图 5‑11。
 
-|linuxd012|
+.. image:: media/linuxd012.jpg
+   :align: center
+   :alt: 未找到图片12|
+
 
-图 5‑11 /bin目录的部分内容
 
 /sbin目录
 ^^^^^^^^^^^^^^^
 
 /sbin目录是/system bin的缩写，它的功能类似/bin ，不过它存储的一般是系统程序，一般需要使用管理员权限才能使用。如显示系统已加载的模块命令lsmod、对存储器分区进行格式化的mkfs等，具体见图 5‑12。
 
-|linuxd013|
+.. image:: media/linuxd013.png
+   :align: center
+   :alt: 未找到图片13|
+
 
-图 5‑12 /sbin目录的部分内容
 
 /etc目录
 ^^^^^^^^^^^^^^
@@ -162,43 +193,54 @@ alloc函数，那么它们就可以共用文件系统上的C库内容，代码A
 /dev目录
 ^^^^^^^^^^^^^^
 
-/dev目录存放了设备文件，即设备驱动程序，用户通过这些文件访问外部设备。比如，用户可 以通过访问/dev/mouse来访问鼠标的输入，就像访问其他文件一样。
+/dev目录存放了设备文件，即设备驱动程序，用户通过这些文件访问外部设备。比如，用户可 
+以通过访问/dev/mouse来访问鼠标的输入，就像访问其他文件一样。
 
 /proc目录
 ^^^^^^^^^^^^^^^
 
-/proc目录通常包含了内核导出到用户空间的内核信息，通过访问该目录下的文件可以查看这些信息。
+/proc目录通常包含了内核导出到用户空间的内核信息，通过访问该目录下的
+文件可以查看这些信息。
 
 /sys目录
 ^^^^^^^^^^^^^^
 
-与/proc目录类似，/sys目录用于把内核的设备驱动导出到用户空间，可通过访问sys目录及其下的文件，来查看甚至控制内核的一些驱动设备。
+与/proc目录类似，/sys目录用于把内核的设备驱动导出到用户空间，可通过访问sys目录
+及其下的文件，来查看甚至控制内核的一些驱动设备。
 
 /tmp目录
 ^^^^^^^^^^^^^^
 
-/tmp目录存放程序在运行时产生的信息和数据。但在引导启动后，运行的程序最好使用/var/tmp来 代替/tmp，因为前者可能拥有一个更大的磁盘空间。
+/tmp目录存放程序在运行时产生的信息和数据。但在引导启动后，运行的程序最好
+使用/var/tmp来 代替/tmp，因为前者可能拥有一个更大的磁盘空间。
 
 /boot目录
 ^^^^^^^^^^^^^^^
 
-/boot目录存放引导加载器(bootstrap loader)使用的文件，如lilo，核心映像也经常放在这里，而不是放在根目录中。但是如果有许多核心映像，这个目录就可能变得很大，这时使用单独的 文件系统会更好一些。
+/boot目录存放引导加载器(bootstrap loader)使用的文件，如lilo，核心映像也经常放
+在这里，而不是放在根目录中。但是如果有许多核心映像，这个目录就可能变得很大，这时使用单独的 文件系统会更好一些。
 
 /mnt目录
 ^^^^^^^^^^^^^^
 
-/mnt目录是系统管理员临时挂载(mount)文件系统的安装点。/mnt下面可以分为许多子目录，例如/mnt/dosa可能是使用 msdos文件系统的软驱，而/mnt/exta可能是使用ext2文件系统的软驱，/mnt/cdrom光 驱等等。
+/mnt目录是系统管理员临时挂载(mount)文件系统的安装点。/mnt下面可以分为许多子目录，例
+如/mnt/dosa可能是使用 msdos文件系统的软驱，而/mnt/exta可能是使用ext2文件系统的软驱，/mnt/cdrom光 驱等等。
 
 /media目录
 ^^^^^^^^^^^^^^^^^^^^^^^^
 
-/media目录通常是一些自动挂载的设备目录，如光盘和U盘，部分系统会自动挂载到这个目录下，然后通过自动挂载的目录可以访问对应的设备。
+/media目录通常是一些自动挂载的设备目录，如光盘和U盘，部分系统会自动挂载到这个目
+录下，然后通过自动挂载的目录可以访问对应的设备。
 
 /usr目录
 ^^^^^^^^^^^^^^
 
-曾经的 /usr 还是用户的家目录，存放着各种用户文件 —— 现在已经被 /home 取代了（例如 /usr/someone 已经改为 /home/someone）。现代的 /usr 只专门存放各种程序和数据，用户目录已经转移。虽然 /usr 名称未改，不过其含义已经从“用户目录”变成了“unix
-system resource”(Unix 系统资源)。值得注意的是，在一些 unix 系统上，仍然把 /usr/someone 当做用户家目录，如 Minix。
+曾经的 /usr 还是用户的家目录，存放着各种用户文件 —— 现在已经被 /home 取代
+了（例如 /usr/someone 已经改为 /home/someone）。现代的 /usr 只专门存放各
+种程序和数据，用户目录已经转移。虽然 /usr 名称未改，不过其含义已经从"用户目
+录"变成了"unix
+system resource"(Unix 系统资源)。值得注意的是，在一些 unix 系统上，仍然
+把 /usr/someone 当做用户家目录，如 Minix。
 
 -  /usr/bin : 所有可执行文件，如 gcc，firefox 等（指不包含在 /sbin 和 /bin 内的）；
 
@@ -232,7 +274,8 @@ system resource”(Unix 系统资源)。值得注意的是，在一些 unix 系
 
 -  硬链接是指同一个文件的不同别名。
 
--  软链接文件有类似于Windows的快捷方式。它实际上是一个特殊的文件。在符号连接中，文件实际上是一个文本文件，其中包含的有另一文件的位置信息。
+-  软链接文件有类似于Windows的快捷方式。它实际上是一个特殊的文件。在符号
+连接中，文件实际上是一个文本文件，其中包含的有另一文件的位置信息。
 
 目录文件
 ^^^^^^^^^^^^
@@ -247,9 +290,11 @@ system resource”(Unix 系统资源)。值得注意的是，在一些 unix 系
 文件扩展名
 ~~~~~~~~~~~~~~
 
-在Windows下习惯通过文件的后缀名来判断可以使用什么软件打开对应的文件，而Linux下没有这样的要求，便Linux下为了容易区分和兼容用户使用Windows的习惯，我们还是会用扩展名来表示文件类型。举例如下：
+在Windows下习惯通过文件的后缀名来判断可以使用什么软件打开对应的文件，而Linux下没
+有这样的要求，便Linux下为了容易区分和兼容用户使用Windows的习惯，我们还是会用扩展名来表示文件类型。举例如下：
 
--  后缀.tar、.tar.gz、.tgz、.zip、.tar.bz表示压缩文件，创建命令一般为tar，gzip，zip等。在压缩文件中的后缀名来通常表示自身由什么压缩格式打包的，以便解压时方便选择要使用的命令。
+-  后缀.tar、.tar.gz、.tgz、.zip、.tar.bz表示压缩文件，创建命令一般为tar，gzip，zip等。在压缩文件
+   中的后缀名来通常表示自身由什么压缩格式打包的，以便解压时方便选择要使用的命令。
 
 -  .sh表示shell脚本文件，通过shell语言开发的程序。
 
@@ -263,6 +308,10 @@ system resource”(Unix 系统资源)。值得注意的是，在一些 unix 系
 
 -  .rpm表示rpm安装包文件。
 
+
+
+
+
 .. |linuxd002| image:: media/linuxd002.png
    :width: 1.02865in
    :height: 1.7197in
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new file mode 100644
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diff --git a/documentation/linux_basis/script_hardware_testing.rst b/documentation/linux_basis/script_hardware_testing.rst
index 33f7558abd604cc9c7b04cfd4673e4264826e341..217c4401e77a72e2706cb379faac1d85f710ffc3 100644
--- a/documentation/linux_basis/script_hardware_testing.rst
+++ b/documentation/linux_basis/script_hardware_testing.rst
@@ -3,60 +3,120 @@
 使用脚本测试硬件
 --------
 
-为方便对开发板的硬件进行测试，我们在开发板出厂配套的系统镜像中提供了一些脚本演示如何控制板载外设。使用这些脚本可以方便地体验开发板的强大之处，小则可以花样点灯，大则可以播视频音乐。
+为方便对开发板的硬件进行测试，我们在开发板出厂配套的系统镜像中提供了一些脚
+本来演示如何控制嵌入式行业常见的板载外设。使用这些脚本可以方便地体验开发板的强大之处。
 
-作为一个合格的程序员，可能在阅读本节的时候，会思考这部分的代码是如何实现的呢？不过本章我们先进行体验，建立概念，在后面章节再对其中的原理进行详细讲解。只要耐心地看完本书，精彩都是在后头的。
+作为一个合格的程序员，可能在阅读本节的时候，会思考这部分的代码是如何实现的
+呢？不过本章我们先进行体验，建立概念，在后面章节再对其中的原理进行详细讲解。只要耐心地
+看完本书，精彩都是在后头的。
+
+
+fire-config使能外设
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+本节测试实验，主要涉及LED、按键、蜂鸣器、ADC、陀螺仪等硬件外设，需要初始化化相关模块。
+参考《fire-config工具简介》章节的相关介绍，确保使能LED、key、IIC、ADC等模块。
+
+.. image:: media/script000.png
+   :align: center
+   :alt: 未找到图片2|
+
+.. image:: media/script001.png
+   :align: center
+   :alt: 未找到图片2|
+
+
+安装脚本文件
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+执行安装命令
+
+.. code-block:: sh
+   :linenos:
+
+   sudo apt install peripheral
+
+注意:如果开发板是第一次使用下载软件，请先使用以下命令进行软件源的刷新
+
+.. code-block:: sh
+   :linenos:
+
+   sudo apt update
 
 测试脚本目录
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
-测试脚本都被存放在开发板的“/home/root/peripheral”目录，为方便讲解，本章后面默认是在该目录下进行，先使用如下命令切换至该目录：
+安装完成后，测试脚本都被存放在开发板的"/home/debian/peripheral"目录。
+为方便讲解，本章后面默认是在该目录下进行，先使用如下命令切换至该目录：
+
+.. code-block:: sh
+   :linenos:
+
+   cd ~/peripheral
+
 
-cd ~/peripheral
+.. image:: media/script002.png
+   :align: center
+   :alt: 未找到图片2|
 
-|script002|
 
-图 14‑1 脚本目录
 
-如图 14‑1是开发板提供的外设示例脚本，不同的开发板提供的内容可能会不同。
+如上图是开发板提供的外设示例脚本，不同的开发板提供的内容可能会不同。
 
 LED灯测试
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
-led.sh脚本可以控制开发板上的LED灯，对于EBF6ULL Pro开发板的RGB彩灯会进行混色，对于EBF6ULL Mini开发板三盏用户LED会以不同形式进行闪烁。
+led.sh脚本可以控制开发板上的LED灯，对于EBF6ULL Pro开发板的RGB彩灯会进行
+混色，对于EBF6ULL Mini开发板三盏用户LED会以不同形式进行闪烁。
 
-在脚本目录下，使用如下命令可直接运行：
+在脚本目录下，使用如下命令可直接运行。
+
+执行前请确认当前用户为 ``root`` 用户，或者使用 ``sudo`` 权限执行。
 
 #在脚本目录下运行
 
-./led.sh
+.. code-block:: sh
+   :linenos:
+
+   ./led.sh
+
+对脚本内容感兴趣的用户可以使用cat命令来查看脚本的内容，如下图所示。
 
-对脚本内容感兴趣的用户可以使用cat命令来查看脚本的内容，如图 14‑2。
+.. image:: media/script003.png
+   :align: center
+   :alt: 未找到图片3|
 
-|script003|
 
-图 14‑2 led.sh脚本的部分内容
 
-脚本的内容看似复杂，其本质就是相当于手动在终端中执行echo命令修改LED灯的设备文件。其余脚本大都是使用类似原理对硬件外设进行控制的。
+脚本的内容看似复杂，其本质就是相当于手动在终端中执行echo命令修改LED灯的设备文件。其余脚本大都是使
+用类似原理对硬件外设进行控制的。
 
 输入设备测试
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
-input.sh脚本可用于对输入设备进行测试，包括按键、触摸屏、鼠标和键盘等。运行脚本可以看到如图 14‑3 按键测试所示的终端信息，若想要退出测试时，请按键盘上的“Ctrl”+“c”结束当前进程。
+input.sh脚本可用于对输入设备进行测试，包括按键、触摸屏、鼠标和键盘等。运行脚本可以看到如下图所示 按键
+测试所示的终端信息，若想要退出测试时，请按键盘上的"Ctrl"+"c"结束当前进程。
 
 #在脚本目录下运行
 
-./input.sh
+.. code-block:: sh
+   :linenos:
 
-|script004|
+   ./input.sh
 
-图 14‑3 按键测试（视接入的设备会有不同的输出）
+.. image:: media/script004.png
+   :align: center
+   :alt: 未找到图片4|
 
-该脚本其实是直接调用了《13.4 检测按键》章节提到的evtest命令，若已了解则使用相同的方式测试即可。
 
-执行脚本后，它会列出可用的输入设备，其中右侧说明带“powerkey”或“gpio-keys”字样的分别对应开发板的“ON/OFF”键及“KEY”键，输设备对应的数字，就可以进行测试。
 
-图 14‑3示例中数字3表示的是KEY按键，若开发板接入了不同的输入设备，对应的数字可能不同，请按照自己开发板的提示输出进行选择。
+该脚本其实是直接调用了《检测按键》章节提到的evtest命令，若已了解则使用相同的方式测试即可。
+
+执行脚本后，它会列出可用的输入设备，其中右侧说明带"powerkey"或"gpio-keys"字样的
+分别对应开发板的"ON/OFF"键及"KEY"键，输设备对应的数字，就可以进行测试。
+
+上图的示例中数字0表示的是KEY按键，若开发板接入了不同的输入设备，对应的数字可能
+不同，请按照自己开发板的提示输出进行选择。
 
 选择了KEY键进行测试后，按下开发板对应的KEY键，终端会有相应的事件检测输出。
 
@@ -69,13 +129,18 @@ EBF6ULL Pro开发板带有蜂鸣器，可进行蜂鸣器测试。
 
 #在脚本目录下运行
 
-./beep.sh
+.. code-block:: sh
+   :linenos:
+
+   ./beep.sh
 
 执行脚本后，按提示输入1，蜂鸣器则会发出响声，输入0，则会关闭蜂鸣器。
 
-|script005|
+.. image:: media/script005.jpg
+   :align: center
+   :alt: 未找到图片5|
+
 
-图 14‑4 蜂鸣器测试
 
 ADC数据采集
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
@@ -88,11 +153,16 @@ EBF6ULL Pro开发板带有电位器，可进行ADC电压采集测试。
 
 #在脚本目录下运行
 
-./adc.sh
+.. code-block:: sh
+   :linenos:
+
+   ./adc.sh
+
+.. image:: media/script006.jpg
+   :align: center
+   :alt: 未找到图片6|
 
-|script006|
 
-图 14‑5 AD数据采集
 
 陀螺仪
 ~~~~~~~~~~~~~
@@ -103,56 +173,26 @@ EBF6ULL Pro开发板带有陀螺仪，可进行陀螺仪测试。
 
 #在脚本目录下运行
 
-./mpu_demo
-
-|script007|
-
-图 14‑6 陀螺仪测试
-
-与前面的sh脚本不同，mpu_demo是一个C程序生成的可执行文件，在后面的章节我们会进行源码讲解。
-
-音频播放
-~~~~~~~~~~~~~~~~~~~~~~~~
-
-EBF6ULL Pro开发板带有耳机接口，可进行音乐播放测试。
-
-测试前使用耳机连接至开发板。
-
-使用./ music_player.sh脚本进行测试。
-
-#在脚本目录下运行
+.. code-block:: sh
+   :linenos:
 
-./music_player.sh
+   ./mpu_demo
 
-|script008|
+.. image:: media/script007.png
+   :align: center
+   :alt: 未找到图片7|
 
-图 14‑7 音频播放测试
-
-脚本执行时，可在耳机中听到播放的音乐。
-
-视频播放
-~~~~~~~~~~~~~~~~~~~~~~~~
-
-EBF6ULL Pro开发板带有耳机及液晶接口，可进行视频播放测试。
-
-测试前给开发板连接好耳机及液晶屏。
-
-使用./ video_player.sh脚本可进行视频播放测试。
-
-#在脚本目录下运行
+其它
+~~~~~~~~~~~~
 
-./video_player.sh
+EBF6ULL Pro开发板上还有DHT11、摄像头、WiFi等硬件接口，不过由于开
+发板存在硬件引脚的复用，控制某些硬件时需要使用非出厂自带
+的Linux系统设备树，控制这些硬件的方式我们将在学习切换系统设备树后再进行操作。
 
-|script009|
 
-图 14‑8视频播放测试
 
-脚本执行时，可在屏幕看到播放的视频，耳机会有视频的声音。
 
-其它
-~~~~~~~~~~~~
 
-EBF6ULL Pro开发板上还有DHT11、摄像头、WiFi等硬件接口，不过由于开发板存在硬件引脚的复用，控制某些硬件时需要使用非出厂自带的Linux系统设备树，控制这些硬件的方式我们将在学习切换系统设备树后再进行操作。
 
 .. |script002| image:: media/script002.png
    :width: 4.45833in
diff --git a/documentation/linux_basis/software_package.rst b/documentation/linux_basis/software_package.rst
index 35def5e871adbf99130e9a0e2f4818a50ae1523b..581949ceb91523517b959f1cf950bb9139e5dfff 100644
--- a/documentation/linux_basis/software_package.rst
+++ b/documentation/linux_basis/software_package.rst
@@ -3,7 +3,7 @@
 包管理工具
 -------------------------
 
-在windows操作系统中，我们要想安装某个软件的时候，只要点开相应的exe文件，一直按“下一步”，最后点“完成”，这样就可以在我们电脑上使用这个软件了。前面我们也提到过，Ubuntu提供了一个软件商店，虽然它也可以提供软件的下载，并且能够自动安装，但是有些软件并不一定能够在里面搜索得到，那只能以源
+在windows操作系统中，我们要想安装某个软件的时候，只要点开相应的exe文件，一直按"下一步"，最后点"完成"，这样就可以在我们电脑上使用这个软件了。前面我们也提到过，Ubuntu提供了一个软件商店，虽然它也可以提供软件的下载，并且能够自动安装，但是有些软件并不一定能够在里面搜索得到，那只能以源
 码的方式来安装软件。采用这种安装方式，都需要检测当前的系统环境，设置编译的参数，如加入/剔除某个模块等，这样的安装方式就显得非常的繁琐。
 
 软件包与包管理工具
@@ -19,46 +19,71 @@ deb包、dpkg及apt
 
 在Debian、Ubuntu等Linux发行版中，通常使用deb（debian）形式的软件包，如图 8‑1是Vim软件的deb安装包。
 
-|softwa002|
 
-图 8‑1 deb包
+
+.. image:: media/softwa002.jpg
+   :align: center
+   :alt: 未找到图片02|
+
+
 
 若下载了deb软件包，可使用如下命令进行安装，其中xxxx.deb为要安装的软件包的名字：
 
-sudo dpkg -i xxxx.deb
+.. code-block:: sh
+   :linenos:
 
-命令中的dpkg（Debian Packager）是Debian专门开发的包管理工具，它可以用来安装、更新和移除软件，安装时它需要使用deb软件包。
+   sudo dpkg -i xxxx.deb
 
-dpkg是一个底层的包管理工具，主要用于对已下载到本地和已经安装的软件包进行管理。在它之上的apt（Advanced Package Tool）包管理工具，其功能则更加丰富和方便使用，使用apt能够自动从互联网的软件仓库中搜索、安装、升级、卸载软件，它会咨询软件仓库，并能安装软件时的模块及依赖问题。
+命令中的dpkg（Debian Packager）是Debian专门开发的包管理工具，它可以用
+来安装、更新和移除软件，安装时它需要使用deb软件包。
+
+dpkg是一个底层的包管理工具，主要用于对已下载到本地和已经安装的软件
+包进行管理。在它之上的apt（Advanced Package Tool）包管理工具，其功能
+则更加丰富和方便使用，使用apt能够自动从互联网的软件仓库中搜索、安装、升级、卸载
+软件，它会咨询软件仓库，并能安装软件时的模块及依赖问题。
 
 如果是使用apt工具安装某个软件，直接使用如下命令即可，它会自动下载并安装软件：
 
-sudo apt-get install 软件名
+.. code-block:: sh
+   :linenos:
+
+   sudo apt-get install 软件名
 
 概括起来可以这么理解，deb是软件包，dpkg是手动安装工具，apt是自动安装工具。
 
 rpm包、rpm及yum
 ^^^^^^^^^^^^
 
-类似地，在RedHat，Fedora，Centos等派系的Linux发行版中，通常使用rpm（RedHat Package Manager)形式的软件包，如图 8‑2是Vim软件的rpm安装包。
+类似地，在RedHat，Fedora，Centos等派系的Linux发行版中，通常
+使用rpm（RedHat Package Manager)形式的软件包，下图是Vim软件的rpm安装包。
+
+.. image:: media/softwa003.jpg
+   :align: center
+   :alt: 未找到图片03|
 
-|softwa003|
 
-图 8‑2 rpm包
 
 若下载了rpm软件包，可使用如下命令进行安装，其中xxxx.rpm为要安装的软件包的名字：
 
-rpm -ivh xxxx.rpm
+.. code-block:: sh
+   :linenos:
 
-命令中的rpm与dpkg的功能类似，同样是主要用于对已下载到本地和已经安装的软件包进行管理。在它之上yum（Yellow dog Updater, Modified）包管理工具，功能与apt类似，它会咨询软件仓库，并能安装软件时的模块及依赖问题。
+   rpm -ivh xxxx.rpm
+
+命令中的rpm与dpkg的功能类似，同样是主要用于对已下载到本地和已经安装
+的软件包进行管理。在它之上yum（Yellow dog Updater, Modified）包管理
+工具，功能与apt类似，它会咨询软件仓库，并能安装软件时的模块及依赖问题。
 
 使用yum安装软件的命令如下，同样地，它会自动下载并完成安装：
 
-yum install 软件名
+.. code-block:: sh
+   :linenos:
+
+   yum install 软件名
 
-关于这些软件包和工具，总结如表 8‑1：
+关于这些软件包和工具，总结如下表：
 
-表 8‑1 软件包和工具
+表  软件包和工具
 
 ============== ================ ================
 \              Debian派系发行版 Redhat派系发行版
@@ -71,63 +96,94 @@ yum install 软件名
 apt工具使用
 ~~~~~~~
 
-本书使用的Linux发行版是Ubuntu，对应的包管理工具就是apt工具，apt包管理工具包含了apt-get工具，主要负责软件包的的安装、卸载以及更新等事务，除此之外，还有apt-cache，用于查询软件包的相关信息，apt-config，用于配置所有apt工具。
+本书使用的Linux发行版是Ubuntu，对应的包管理工具就是apt工具，apt包管
+理工具包含了apt-get工具，主要负责软件包的的安装、卸载以及更新等事务，除
+此之外，还有apt-cache，用于查询软件包的相关信息，apt-config，用于配
+置所有apt工具。
 
 安装与删除软件包
 ^^^^^^^^
 
-apt-get install
+.. code-block:: sh
+   :linenos:
+
+   apt-get install
 '''''''''''''''
 
 使用apt-get工具安装程序的时候，需要你知道应用程序的名字。具体的命令语法：
 
-sudo apt-get install 软件包名
+.. code-block:: sh
+   :linenos:
+
+   sudo apt-get install 软件包名
+
+apt-get install会扫描本地存放的软件包更新列表/var/lib/apt/lists/，找
+到最新版本的软件包，然后检查软件包依赖关系，找到支持该软件正常运行的
+所有软件包，并从镜像源地址中下载所需的软件包，最后解压软件包，自动完
+成应用程序的安装和配置。
 
-apt-get install会扫描本地存放的软件包更新列表/var/lib/apt/lists/，找到最新版本的软件包，然后检查软件包依赖关系，找到支持该软件正常运行的所有软件包，并从镜像源地址中下载所需的软件包，最后解压软件包，自动完成应用程序的安装和配置。
+下面带大家来安装一个有趣的命令：sl。运行该命令之后，你的终端里会出
+现一辆火车在跑，执行以下命令：
 
-下面带大家来安装一个有趣的命令：sl。运行该命令之后，你的终端里会出现一辆火车在跑，执行以下命令：
+.. image:: media/softwa004.jpg
+   :align: center
+   :alt: 未找到图片04|
 
-|softwa004|
 
-图 8‑3 安装sl软件
 
 可以看到终端会输出很多信息，下面我们把输出信息拆分成三块进行讲解：
 
-|softwa005|
+.. image:: media/softwa005.jpg
+   :align: center
+   :alt: 未找到图片05|
 
-图 8‑4 安装软件第一部分
 
-图 8‑4中的输出信息，apt-get install正读取软件包列表，并且检查软件包的依赖关系，并且列出了所有的依赖文件。
 
-|softwa006|
+上图中的输出信息，apt-get install正读取软件包列表，并且检查软件包的依赖关系，并且列出了所有的依赖文件。
 
-图 8‑5 安装软件的第二部分
+.. image:: media/softwa006.jpg
+   :align: center
+   :alt: 未找到图片06|
 
-图 8‑5则是apt-get install从镜像源http://cn.archive.ubuntu.com/ubuntu中下载所需要的软件，并且自动解压，完成安装的整个过程。
 
-运行刚刚安装的软件，在终端输入命令：sl，就可以看到图 8‑6的画面。
 
-|softwa007|
+上图则是apt-get install从镜
+像源http://cn.archive.ubuntu.com/ubuntu中下载所需要的软件，并且
+自动解压，完成安装的整个过程。
+
+运行刚刚安装的软件，在终端输入命令：sl，就可以看到下图的画面。
+
+.. image:: media/softwa007.jpg
+   :align: center
+   :alt: 未找到图片07|
+
 
-图 8‑6 运行画面
 
 apt-get remove
 ''''''''''''''
 
 讲了如何安装软件，自然也要知道如何卸载一个软件，具体的命令语法如下：
 
-sudo apt-get remove 软件包名
+.. code-block:: sh
+   :linenos:
+
+   sudo apt-get remove 软件包名
+
+.. image:: media/softwa008.jpg
+   :align: center
+   :alt: 未找到图片08|
 
-|softwa008|
 
-图 8‑7 删除软件
 
-在执行命令之后，终端会提示是否继续执行删除操作，输入“Y”的话，该软件就和你彻底说拜拜了，输入“n”的话，则会终止当前的删除操作。
+在执行命令之后，终端会提示是否继续执行删除操作，输入"Y"的话，该软件
+就和你彻底说拜拜了，输入"n"的话，则会终止当前的删除操作。
 
 常用镜像站
 ^^^^^
 
-使用apt-get install安装软件时，可注意到它是从Ubuntu官方源地址下载的，但Ubuntu默认官方的软件仓库都设置在国外，经常出现软件包安装更新缓慢甚至下载超时等异常情况。实际上，国内有许多第三方软件仓库镜像源，可以从这些国内仓库安装软件工具。
+使用apt-get install安装软件时，可注意到它是从Ubuntu官方源地址下载的，但Ubuntu默认官
+方的软件仓库都设置在国外，经常出现软件包安装更新缓慢甚至下载超时等异常情况。实
+际上，国内有许多第三方软件仓库镜像源，可以从这些国内仓库安装软件工具。
 
 常用的国内镜像源有：
 
@@ -137,29 +193,39 @@ sudo apt-get remove 软件包名
 
 -  阿里云镜像源：\ https://opsx.alibaba.com/mirror
 
-这些镜像站通常包含非常丰富的软件，以清华大学镜像源的网站为例，见图 8‑8，在其镜像列表中可以找到ubuntu的软件源，点击ubuntu右侧的“？”，还可以查看到如图 8‑9的帮助说明。
+这些镜像站通常包含非常丰富的软件，以清华大学镜像源的网站为例，见下图，在其镜
+像列表中可以找到ubuntu的软件源，点击ubuntu右侧的"？"，还可以查看到如下的帮助说明。
 
-   |softwa009|
 
-图 8‑8清华大学镜像源网站
+.. image:: media/softwa009.png
+   :align: center
+   :alt: 未找到图片09|
 
-|softwa010|
 
-图 8‑9 清华大学Ubuntu镜像的使用帮助
 
-点击镜像站中的ubuntu链接，可以看到如图 8‑10的界面。
+.. image:: media/softwa010.png
+   :align: center
+   :alt: 未找到图片10|
 
-|softwa011|
 
-图 8‑10 ubuntu镜像源目录
+点击镜像站中的ubuntu链接，可以看到如下所示的界面。
 
-该页面下的目录pool就是各种Ubuntu软件存放的位置，点击该地址，可以看到图 8‑11的内容。
+.. image:: media/softwa011.png
+   :align: center
+   :alt: 未找到图片11|
 
-|softwa012|
 
-图 8‑11 目录pool
 
-其中有四个目录，分别是main，multiverse，restricted以及universe四个“仓库”，它们主要是依据软件包是否开源来进行划分的：
+该页面下的目录pool就是各种Ubuntu软件存放的位置，点击该地址，可以看到如下所示的内容。
+
+.. image:: media/softwa012.png
+   :align: center
+   :alt: 未找到图片12|
+
+
+
+其中有四个目录，分别是main，multiverse，restricted以及universe四个"仓库"，它们
+主要是依据软件包是否开源来进行划分的：
 
 -  main表示完全开源软件，可以被Ubuntu官方完全支持的软件。
 
@@ -169,62 +235,81 @@ sudo apt-get remove 软件包名
 
 -  universe表示Ubuntu官方不提供支持与补丁，全靠社区支持。
 
-这四个目录中的软件都是按照软件名称的首字母进行分类，极大地方便了我们搜索某个软件，如图 8‑12。不过，当我们使用时，是直接通过apt工具下载的，而不需要自己来到开源镜像站中查找。
+这四个目录中的软件都是按照软件名称的首字母进行分类，极大地方便了我们搜索某个
+软件，如下所示。不过，当我们使用时，是直接通过apt工具下载的，而不需要自己来到开源镜像站中查找。
+
+.. image:: media/softwa013.jpg
+   :align: center
+   :alt: 未找到图片13|
 
-|softwa013|
 
-图 8‑12 gcc编译器
 
 修改软件源（图形）
 ^^^^^^^^^
 
-在Ubuntu下可直接在“软件和更新”的配置中修改软件源，见图 8‑13。
+在Ubuntu下可直接在"软件和更新"的配置中修改软件源，见下图。
 
-|softwa014|
+.. image:: media/softwa014.png
+   :align: center
+   :alt: 未找到图片14|
 
-图 8‑13 软件和更新
 
-在弹出的界面选择“其他站点”->“mirrors.tuna.tsinghua.edu.cn”（清华大学镜像源）或“mirrors.aliyun.com”（阿里云镜像源）网址，如图 8‑15和图 8‑16。
 
-|softwa015|
+在弹出的界面选择"其他站点"->"mirrors.tuna.tsinghua.edu.cn"（清华大学
+镜像源）或"mirrors.aliyun.com"（阿里云镜像源）网址，如下图所示。
 
-图 8‑14 在其他站点
+.. image:: media/softwa015.png
+   :align: center
+   :alt: 未找到图片15|
 
-|softwa016|
 
-图 8‑15 使用清华大学镜像源
 
-选择后关闭该窗口它会提示更新源，点击“重新载入”即可，见图 8‑16。
+.. image:: media/softwa016.png
+   :align: center
+   :alt: 未找到图片16|
+
+
+
+选择后关闭该窗口它会提示更新源，点击"重新载入"即可，见下图。
+
+.. image:: media/softwa017.png
+   :align: center
+   :alt: 未找到图片17|
 
-|softwa017|
 
-图 8‑16 更新软件源列表
 
 软件源格式
 ^^^^^
 
-在后面我们的开发板会提供Debian及Ubuntu的镜像，但在开发板中修改软件源并没有上述的图形界面这么方便，我们通常是使用终端去修改软件源配置文件实现的，而且在后期搭建开发环境的时候，也常常需要修改各种配置文件。在本例子中如果改得不对，还可以通过上面的图形界面修改回来，所以我们就趁这个机会先熟悉一
+在后面我们的开发板会提供Debian及Ubuntu的镜像，但在开发板中修改软件源
+并没有上述的图形界面这么方便，我们通常是使用终端去修改软件源配置文件
+实现的，而且在后期搭建开发环境的时候，也常常需要修改各种配置文件。在本例
+子中如果改得不对，还可以通过上面的图形界面修改回来，所以我们就趁这个机会先熟悉一
 下修改配置文件的过程吧。修改配置文件的步骤为：熟悉配置文件的格式->修改配置文件->更新配置。
 
-我们先来了解软件源配置文件的格式，在Ubunut下，软件源的配置是记录在文件/etc/apt/sources.list中的，我们可以通过cat命令输出该文件的内容，查看自己电脑上的源配置：
+我们先来了解软件源配置文件的格式，在Ubunut下，软件源的配置是记录
+在文件/etc/apt/sources.list中的，我们可以通过cat命令输出该文件的内容，查
+看自己电脑上的源配置：
 
-cat /etc/apt/sources.list
+.. code-block:: sh
+   :linenos:
 
-|softwa018|
+   at /etc/apt/sources.list
 
-图 8‑17 使用cat查看/etc/apt/sources.list的内容
+.. image:: media/softwa018.png
+   :align: center
+   :alt: 未找到图片18|
 
-/etc/apt/sources.list文件具有一定的格式， **错误!书签自引用无效。**\ 和
 
-图 8‑19分别是符合要求的官方软件源和清华大学镜像源的例子。
+/etc/apt/sources.list文件具有一定的格式如下所示。
 
-图 8‑18 官方软件源（/etc/apt/sources.list节选）
+官方软件源（/etc/apt/sources.list节选）
 
 1 deb http://cn.archive.ubuntu.com/ubuntu/ bionic main restricted
 
 2 deb-src http://cn.archive.ubuntu.com/ubuntu/ bionic main restricted
 
-图 8‑19 第三方镜像源（以清华大学镜像源为例）
+第三方镜像源（以清华大学镜像源为例）
 
 1 deb https://mirrors.tuna.tsinghua.edu.cn/ubuntu/ bionic main restricted universe multiverse
 
@@ -232,9 +317,9 @@ cat /etc/apt/sources.list
 
 我们以清华大学提供的镜像源为例，讲解一下Ubuntu软件源的格式。
 
-/etc/apt/sources.list中每一行都代表了一个软件源，每行的软件源描述又可以分为四个部分，见表格 8‑1。
+/etc/apt/sources.list中每一行都代表了一个软件源，每行的软件源描述又可以分为四个部分，见下表。
 
-表格 8‑1 软件源格式
+表  软件源格式
 
 =========== ============================================ ==================== ===================================
 软件包格式  镜像源地址                                   Ubuntu发行版版本代号 要下载软件包的类型
@@ -244,14 +329,21 @@ deb/deb-src https://mirrors.tuna.tsinghua.edu.cn/ubuntu/ bionic               ma
 
 这四部分的说明如下：
 
--  第一部分，软件包格式。apt工具下载某个格式的软件包，有deb和deb-src两种格式。deb格式就是所要的软件安装包，而deb-src则是对应软件的源代码。因为开源协议，我们在下载某个软件的同时，也可以下载到某个软件的源代码。
+-  第一部分，软件包格式。apt工具下载某个格式的软件包，有deb和deb-src两种格
+   式。deb格式就是所要的软件安装包，而deb-src则是对应软件的源代码。因为
+   开源协议，我们在下载某个软件的同时，也可以下载到某个软件的源代码。
 
--  第二部分，镜像源地址， apt工具去什么地方可以下载到我们所需要的软件包。这个地址可不是什么普通的地址，关于这部分内容后面还会继续介绍。
+-  第二部分，镜像源地址， apt工具去什么地方可以下载到我们所
+   需要的软件包。这个地址可不是什么普通的地址，关于这部分内容后面还会继续介绍。
 
--  第三部分，Ubuntu发行版本的版本代号。在本章开篇处，曾提到了包管理工具中的软件都是经过Linux开发者在特定的硬件平台上编译成功之后，发布出来的。因此，同一个软件，在不同的平台上不一定适用，因此，在下载的时候，千万不能搞错版本，张冠李戴。Ubuntu中的每个版本都是由一个形容词和一个动物名称组
-  成，并且形容词和名词的首字母都是一致的。如果当前版本的首字母是 D ，下个版本就要以 E 来起头。
+-  第三部分，Ubuntu发行版本的版本代号。在本章开篇处，曾提到
+   了包管理工具中的软件都是经过Linux开发者在特定的硬件平台上编译成功
+   之后，发布出来的。因此，同一个软件，在不同的平台上不一定适用，因此，在
+   下载的时候，千万不能搞错版本，张冠李戴。Ubuntu中的每个版本都是由一个形容词和一个动物名称组
+   成，并且形容词和名词的首字母都是一致的。如果当前版本的首字母是 D ，下个
+   版本就要以 E 来起头。
 
-表格 8‑2 Ubuntu发行版版本代号
+表  Ubuntu发行版版本代号
 
 ===== ================
 版本  版本代号
@@ -264,9 +356,11 @@ deb/deb-src https://mirrors.tuna.tsinghua.edu.cn/ubuntu/ bionic               ma
 
 ..
 
-   表格 8‑2只列出了Ubuntu的LTS版本。LTS，是长期支持（Long Term Support）的缩写。Ubuntu桌面版通常每两年发布一个新的LTS版本，本书使用的Ubuntu18.04，对应的版本代号为Bionic Beaver。
+   上表只列出了Ubuntu的LTS版本。LTS，是长期支持（Long Term Support）的缩写。Ubuntu
+   桌面版通常每两年发布一个新的LTS版本，本书使用的Ubuntu18.04，对应的版本代号为Bionic Beaver。
 
--  第四部分，选择要下载的软件包的类型，即图 8‑11介绍的main完全开源软件， restricted不完全开源的软件，universe Ubuntu官方不提供支持与补丁的软件，全靠社区支持。muitiverse非开源软件。
+-  第四部分，选择要下载的软件包的类型，前面介绍的main完全开源软件， restricted不完全开源
+   的软件，universe Ubuntu官方不提供支持与补丁的软件，全靠社区支持。muitiverse非开源软件。
 
 修改软件源（命令行）
 ^^^^^^^^^^
@@ -275,67 +369,95 @@ deb/deb-src https://mirrors.tuna.tsinghua.edu.cn/ubuntu/ bionic               ma
 
 建议在修改软件源前，使用如下复制命令对原文件进行备份：
 
-cp /etc/apt/sources.list /etc/apt/sources_bk.list
+.. code-block:: sh
+   :linenos:
+
+   cp /etc/apt/sources.list /etc/apt/sources_bk.list
 
 若修改后使用有问题，使用备份的/etc/apt/sources_bk.list覆盖原文件后更新即可。
 
 由于修改/etc/apt/sources.list配置文件通常需要管理员权限，
 普通用户在图形界面直接双击打开该文件时，Ubuntu系统自带的编辑器gedit只有只读权限，无法修改。可以在终端中使用sudo以管理员的身份运行gedit，并打开/etc/apt/sources.list文件进行修改，命令如下：
 
-sudo gedit /etc/apt/sources.list
+.. code-block:: sh
+   :linenos:
+
+   sudo gedit /etc/apt/sources.list
 
-在后面的系统应用中，我们常常需要修改某些系统配置文件，都可以通过这种方式使用gedit进行修改，把命令中的文件名改成目标文件即可。
+在后面的系统应用中，我们常常需要修改某些系统配置文件，都可以通过这
+种方式使用gedit进行修改，把命令中的文件名改成目标文件即可。
 
-如果系统没有gedit或者没有图形界面，一般直接在终端下使用Vi/Vim编辑器进行修改，不会使用Vi/Vim的话，请在学习《使用Vim编辑器》的章节后再进行修改。
+如果系统没有gedit或者没有图形界面，一般直接在终端下使
+用Vi/Vim编辑器进行修改，不会使用Vi/Vim的话，请在学习《使用Vim编辑器》的章
+节后再进行修改。
 
-把前面图 8‑9中镜像源使用帮助的sources.list文件内容复制替换文件/etc/apt/sources.list的原内容，保存后退出即可。
+把前面镜像源使用帮助的sources.list文件内容复制替换文件/etc/apt/sources.list的原内容，保存后退出即可。
+
+.. image:: media/softwa019.jpg
+   :align: center
+   :alt: 未找到图片19|
 
-|softwa019|
 
-图 8‑20 使用gedit在sources.list中添加软件源
 
 更新软件源
 ^^^^^
 
 用户一旦修改了软件源配置文件/etc/apt/sources.list，需要运行apt-get update命令来更新软件源中的所有软件列表。
 
-sudo apt-get update
+.. code-block:: sh
+   :linenos:
+
+   sudo apt-get update
+
+.. image:: media/softwa020.png
+   :align: center
+   :alt: 未找到图片20|
+
+
 
-|softwa020|
+apt-get update命令会扫描每一个软件源地址，并为该软件源地址所具有软
+件包资源建立索引文件，存放在本地的/var/lib/apt/lists/目录下。
 
-图 8‑21 apt-get update命令
+我们从上图中，可以看到我们上面添加的中国科技大学的镜
+像源地址，在sources.list文件中选择只下载main类型的软件，因此在apt-get
+update的过程中，也只会去获取main类型的软件包。此外，图中
+的amd64是一种64位的电脑处理器架构，又称"x86-64"或"x64"；i386则是
+作为对Intel（英特尔）32位微处理器的统称。
 
-apt-get update命令会扫描每一个软件源地址，并为该软件源地址所具有软件包资源建立索引文件，存放在本地的/var/lib/apt/lists/目录下。
+.. image:: media/softwa021.png
+   :align: center
+   :alt: 未找到图片21|
 
-我们从图 8‑21中，可以看到我们上面添加的中国科技大学的镜像源地址，在sources.list文件中选择只下载main类型的软件，因此在apt-get
-update的过程中，也只会去获取main类型的软件包。此外，图中的amd64是一种64位的电脑处理器架构，又称“x86-64”或“x64”；i386则是作为对Intel（英特尔）32位微处理器的统称。
 
-|softwa021|
 
-图 8‑22 本地索引文件
+本书的虚拟机使用的64位机器，我们打开上图选中的文件，该文件主要
+记录了所有适用于am64架构处理器的软件包。
 
-本书的虚拟机使用的64位机器，我们打开图 8‑22选中的文件，该文件主要记录了所有适用于am64架构处理器的软件包。
+.. image:: media/softwa022.jpeg
+   :align: center
+   :alt: 未找到图片22|
 
-|softwa022|
 
-图 8‑23 gcc软件包
 
-图 8‑23中记录了gcc-7软件包的相关信息：
+上图中记录了gcc-7软件包的相关信息：
 
 -  Package：记录了关于软件的具体名称；
 
--  Architecture：该软件包可以运行的平台架构，常见的有amd64，i386。Debian和Ubuntu的Linux发行版也支持armhf架构的处理器。
+-  Architecture：该软件包可以运行的平台架构，常见的
+   有amd64，i386。Debian和Ubuntu的Linux发行版也支持armhf架构的处理器。
 
--  Depends：记录了该软件的需要依赖文件，而且还有相应的版本要求。安装gcc-7编译器，需要依赖zlib1g，版本要求高于1:1.1.4。
+-  Depends：记录了该软件的需要依赖文件，而且还有相应的
+   版本要求。安装gcc-7编译器，需要依赖zlib1g，版本要求高于1:1.1.4。
 
 -  Filename：记录了该软件包位于镜像源的位置，是不是和我们上一节分析的内容一致。
 
    1. ..
       rubric:: apt-cache工具 :name: apt-cache工具
 
-apt-cache是Ubuntu的另一个APT软件包管理工具。通过apt-cache工具配合对应的子命令，可以实现查找，显示软件包信息及包依赖关系等功能，见表格 8‑3。
+apt-cache是Ubuntu的另一个APT软件包管理工具。通过apt-cache工具
+配合对应的子命令，可以实现查找，显示软件包信息及包依赖关系等功能，见下表。
 
-表格 8‑3 apt-cache工具
+表  apt-cache工具
 
 ========================== ============================================
 命令                       作用
@@ -351,33 +473,56 @@ apt-cache policy 软件包名  显示软件包的安装状态
 
 例如，可通过如下命令搜索支持ifconfig命令的软件包：
 
-apt-cache search ifconfig
+.. code-block:: sh
+   :linenos:
 
-|softwa023|
+   apt-cache search ifconfig
 
-图 8‑24 搜索ifconfig软件包
+.. image:: media/softwa023.png
+   :align: center
+   :alt: 未找到图片23|
 
-APT包管理工具还包括apt-config工具，用于配置所有的APT工具，但是我们基本上接触不到。因此，我们只需要重点掌握apt-get工具的用法，对于apt-
-cache的话，我们只需要大概了解即可。实际上，Ubuntu开发团队也发现了这个问题，并且给出了有效的解决方法：apt命令。这里的apt命令和APT包管理工具是完全不同的两个东西，请不要混淆了。
+
+
+APT包管理工具还包括apt-config工具，用于配置所有的APT工具，但是我们
+基本上接触不到。因此，我们只需要重点掌握apt-get工具的用法，对于apt-
+cache的话，我们只需要大概了解即可。实际上，Ubuntu开发团队也发现了这
+个问题，并且给出了有效的解决方法：apt命令。这里的apt命令和APT包管理
+工具是完全不同的两个东西，请不要混淆了。
 
 apt与apt-get
 ~~~~~~~~~~~
 
-前面介绍命令“apt-get install”时，已经为大家演示了如何安装软件。下面的实验是大多数初学者经常会遇到的情况。现在我们执行下面的命令：
+前面介绍命令"apt-get install"时，已经为大家演示了如何安装软件。下面的实验
+是大多数初学者经常会遇到的情况。现在我们执行下面的命令：
+
+.. code-block:: sh
+   :linenos:
 
-vim
+   vim
 
-终端会告诉你，找不到这个vim命令，并告诉你可以用下面提供命令来安装软件，如 图8‑25所示。Linux的终端往往会输出一些有利于我们解决问题的信息。而Windows偶尔会弹出一个对话框来提醒用户。因此，在今后的学习中，遇到问题，应该多关注终端的输出信息，说不定里面暗含着解决之道。
+终端会告诉你，找不到这个vim命令，并告诉你可以用下面提供命令来安
+装软件，如下图所示。Linux的终端往往会输出一些有利于我们
+解决问题的信息。而Windows偶尔会弹出一个对话框来提醒用户。因
+此，在今后的学习中，遇到问题，应该多关注终端的输出信息，说不定里面暗含着解决之道。
 
-|softwa024|
+.. image:: media/softwa024.jpg
+   :align: center
+   :alt: 未找到图片24|
 
-图 8‑25 安装提示
 
-不知道有没有细心的读者发现，此处Linux给出的解决方案是“apt install vim”而不是“apt-get install vim”。实际上，在Ubuntu 16.04中就引入了 apt 命令，并且越来越多Linux发行版也开始鼓励用户使用apt而不是apt-get。前面我们提到，apt-
-cache、apt-config 等命令包含众多了功能，但对于 Linux 用户来说可能永远都不会使用到。apt 命令出现就是为了解决上述的问题，它包括了 apt-get 命令使用最广泛的功能选项，以及 apt-cache 和 apt-config 命令中很少用到的功能，也就是说apt是集apt-
-get、apt-cache 和 apt-config 各工具之所长的工具。不仅如此，使用 apt 命令安装或删除程序时，会有进度条显示当前的进度。
 
-表格 8‑4 apt命令
+不知道有没有细心的读者发现，此处Linux给出的解决方案是"apt install vim"而
+不是"apt-get install vim"。实际上，在Ubuntu 16.04中就引入了 apt 命
+令，并且越来越多Linux发行版也开始鼓励用户使用apt而不是apt-get。前面
+我们提到，apt-
+cache、apt-config 等命令包含众多了功能，但对于 Linux 用户来说可能永
+远都不会使用到。apt 命令出现就是为了解决上述的问题，它包括了 apt-get 命
+令使用最广泛的功能选项，以及 apt-cache 和 apt-config 命令中很少用到的功能，也就是说apt是集apt-
+get、apt-cache 和 apt-config 各工具之所长的工具。不仅如此，使用 apt 命
+令安装或删除程序时，会有进度条显示当前的进度。
+
+表  apt命令
 
 ==================== ==========================
 命令                 作用
@@ -390,23 +535,40 @@ apt show 软件包名    显示软件包的相关信息
 apt list             根据名称列出所有的软件包
 ==================== ==========================
 
-表格 8‑4中列出了部分常用的apt命令，可以看到apt命令比APT包管理工具更加精简，更能满足用户的需求。用通俗一点的话讲，就是别人需要三个工具才能搞定的事情，我只需要一个apt命令，如原来的apt-get install 命令改成apt install同样也可以完成软件的安装。
+上表中列出了部分常用的apt命令，可以看到apt命令比APT包管理
+工具更加精简，更能满足用户的需求。用通俗一点的话讲，就是别人需要三个
+工具才能搞定的事情，我只需要一个apt命令，如原来的apt-get install 命令
+改成apt install同样也可以完成软件的安装。
 
 我们输入命令：
 
-sudo apt install vim
+.. code-block:: sh
+   :linenos:
+
+   sudo apt install vim
+
+之后，会提示你输入密码，接着便开始下载，安装软件
+了。软件安装完成之后，再执行命令vim，终端就不会再报
+错了，这时候就可以使用我们的Vim编辑软件，软件界面如 下图所示。
+
+.. image:: media/softwa025.jpg
+   :align: center
+   :alt: 未找到图片25|
+
+
+
+对于没有用过Vim的用户，如果你在Vim上尝试折腾一翻后， 可能会出现各种情
+况，如进入到了Vim的编辑模式，输入了些内容，但不知道如何保存或退出，这些
+我们将在《第10章 使用编辑器》章节中介绍，现在我们直接点击终端右上角的关闭按钮强制退出即可。
 
-之后，会提示你输入密码，接着便开始下载，安装软件了。软件安装完成之后，再执行命令vim，终端就不会再报错了，这时候就可以使用我们的Vim编辑软件，软件界面如 图8‑26所示。
+.. image:: media/softwa026.png
+   :align: center
+   :alt: 未找到图片26|
 
-|softwa025|
 
-图 8‑26 vim界面
 
-对于没有用过Vim的用户，如果你在Vim上尝试折腾一翻后， 可能会出现各种情况，如进入到了Vim的编辑模式，输入了些内容，但不知道如何保存或退出，这些我们将在《第9章 使用编辑器》章节中介绍，现在我们直接点击终端右上角的关闭按钮强制退出即可。
 
-|softwa026|
 
-图 8‑27 强制退出
 
 .. |softwa002| image:: media/softwa002.jpg
    :width: 4.55833in
diff --git a/documentation/linux_basis/system_information.rst b/documentation/linux_basis/system_information.rst
index 61dc51f22a87184951ff9f1f901fa008a93be203..a28d1f0cecc03555b2abf11f397fc84afc74be30 100644
--- a/documentation/linux_basis/system_information.rst
+++ b/documentation/linux_basis/system_information.rst
@@ -16,27 +16,33 @@ Linux没有提供类似Windows的任务管理器，但是它将系统运行的
 
 #在开发板的终端执行以下命令
 
-ls /proc
+.. code-block:: sh
+   :linenos:
 
-|system002|
+   ls /proc
 
-图 12‑1 开发板上的/proc目录内容（内容可能会小有差异，影响不大）
 
-该目录下各文件包含的信息如表 12‑1所示。
+.. image:: media/system002.png
+   :align: center
+   :alt: 未找到图片02|
 
-表 12‑1 /proc文件结构
+
+
+该目录下各文件包含的信息如下表所示。
+
+表   /proc文件结构
 
 =========== ================================================================================================================================================================================
 文件名      作用
 =========== ================================================================================================================================================================================
-pid\*       “pid*”通常就是一个数字，该数字表示的是进程的 PID 号，系统中当前运行的每一个进程都有对应的一个目录，用于记录进程所有相关信息。对于操作系统来说，一个应用程序就是一个进程
+pid*       "pid*"通常就是一个数字，该数字表示的是进程的 PID 号，系统中当前运行的每一个进程都有对应的一个目录，用于记录进程所有相关信息。对于操作系统来说，一个应用程序就是一个进程
 self        该文件是一个软链接，指向了当前进程的目录，通过访问/proc/self/目录来获取当前进程的信息，就不用每次都获取pid
-thread-self 该文件也是一个软链接，指向了当前线程，访问该文件，等价于访问“当前进程pid/task/当前线程tid”的内容。。一个进程，可以包含多个线程，但至少需要一个进程，这些线程共同支撑进程的运行。
-version     记录了当前运行的内核版本，通常可以使用“uname –r”命令查看
+thread-self 该文件也是一个软链接，指向了当前线程，访问该文件，等价于访问"当前进程pid/task/当前线程tid"的内容。。一个进程，可以包含多个线程，但至少需要一个进程，这些线程共同支撑进程的运行。
+version     记录了当前运行的内核版本，通常可以使用"uname –r"命令查看
 cpuinfo     记录系统中CPU的提供商和相关配置信息
 modules     记录了目前系统加载的模块信息
 meminfo     记录系统中内存的使用情况，free命令会访问该文件，来获取系统内存的空闲和已使用的数量
-filesystems 记录内核支持的文件系统类型，通常mount一个设备时，如果没有指定文件系统并且它无法确定文件系统类型时，mount会尝试包含在该文件中的文件系统，除了那些标有“nodev”的文件系统。
+filesystems 记录内核支持的文件系统类型，通常mount一个设备时，如果没有指定文件系统并且它无法确定文件系统类型时，mount会尝试包含在该文件中的文件系统，除了那些标有"nodev"的文件系统。
 =========== ================================================================================================================================================================================
 
 通过访问/proc文件夹的内容，就可以得到我们想要的系统信息。
@@ -46,58 +52,86 @@ filesystems 记录内核支持的文件系统类型，通常mount一个设备时
 
 /proc/cpuinfo文件存储了CPU的信息，可通过如下命令查看：
 
-cat /proc/cpuinfo
+.. code-block:: sh
+   :linenos:
+
+   cat /proc/cpuinfo
 
-|system003|
+.. image:: media/system003.jpg
+   :align: center
+   :alt: 未找到图片03|
 
-图 12‑2 CPU信息
 
-从图 12‑2可以看到，我们使用的硬件平台是飞思卡尔i.MX6 Ultralite，是一款ARMv7架构的处理器（Cortex-A7内核是ARMv7架构的）。
+
+从上图可以看到，我们使用的硬件平台是飞思卡尔i.MX6 Ultralite，是一
+款ARMv7架构的处理器（Cortex-A7内核是ARMv7架构的）。
 
 查看内核版本
 ~~~~~~
 
 /proc/version文件保存了内核的版本信息，我们可以通过如下命令来获取。
 
-cat /proc/version
+.. code-block:: sh
+   :linenos:
+
+   cat /proc/version
+
+.. image:: media/system004.png
+   :align: center
+   :alt: 未找到图片04|
 
-|system004|
 
-图 12‑3 内核版本信息
 
-从图 12‑3中，我们可以看到当前使用的内核版本是4.1.15。
+从上图中我们可以看到当前使用的内核版本是4.19.71。
 
 也可以通过如下命令获取：
 
-uname –a
+.. code-block:: sh
+   :linenos:
+
+   uname –a
+
+.. image:: media/system005.png
+   :align: center
+   :alt: 未找到图片05|
 
-|system005|
 
-图 12‑4 uname –a命令获取的信息
 
 查看内存信息
 ~~~~~~
 
 内核将内存的使用情况记录在/proc/meminfo文件中，我们可以通过读取该文件的内容，来了解我们内存的使用情况：
 
-cat /proc/meminfo
+.. code-block:: sh
+   :linenos:
+
+   cat /proc/meminfo
 
-|system006|
+.. image:: media/system006.png
+   :align: center
+   :alt: 未找到图片06|
 
-图 12‑5 /proc/meminfo的内容
 
 在实际应用中，我们一般都不会直接去读取该文件的内容，而是使用下面的命令来获取内存的相关信息。
 
 通过free命令查看系统的内存大小：
 
-free
+.. code-block:: sh
+   :linenos:
 
-如图 12‑6所示，输出信息共有三行，六列。其中第一行记录了我们的内存使用情况，可以看到我们内存容量为494M（506268/1024），当前已使用了93M，还剩下400M可用。shared表示表示的是多个进程共享的内存总量，这里只占有了580个字节；Buffers/cached表示当前磁盘缓存的大
+   free
+
+如下图所示，输出信息共有三行，六列。其中第一行记录了我们的内
+存使用情况，可以看到我们内存容量为491M（503508/1024），当前已
+使用了99M，还剩下380M可用。shared表示表示的是多个进程共享的内存总
+量，这里只占有了27668个字节；Buffers/cached表示当前磁盘缓存的大
 小为31476个字节。
 
-|system007|
+.. image:: media/system007.jpg
+   :align: center
+   :alt: 未找到图片07|
+
 
-图 12‑6 内存使用情况
 
 查看FLASH存储器容量
 ~~~~~~~~~~~~
@@ -106,39 +140,50 @@ free
 
 可使用如下命令查看：
 
-cat /proc/partitions
+.. code-block:: sh
+   :linenos:
+
+   cat /proc/partitions
 
 其单位为blocks的数量，对于本示例的开发板，Nand-FLASH的每个Block大小为1024Byte，eMMC则为512Byte。
 
 Nand-Flash存储器
 ^^^^^^^^^^^^^
 
-图 12‑7是使用256MB Nand-FLASH开发板的命令输出信息。
+下图是使用512MB Nand-FLASH开发板的命令输出信息。
 
-|system008|
+.. image:: media/system008.png
+   :align: center
+   :alt: 未找到图片08|
 
-图 12‑7 256MB Nand-FLASH开发板的分区信息
 
-其中的mtdblock开头的都是属于Nand-FLASH存储器的数据块，把它们所有的blocks加起来就可以算出容量(每个block大小为1024Byte)：
 
-65536+16384+16384+163840 （Block）
+其中的mtdblock开头的都是属于Nand-FLASH存储器的数
+据块，把它们所有的blocks加起来就可以
+算出容量(每个block大小为1024Byte)：
 
-= 262144*1024（Byte）
+516096+8192 （Block）
 
-=262144*1024/1024/1024 （MByte）
+= 524288*1024（Byte）
 
-=256 MByte
+=524288*1024/1024/1024 （MByte）
+
+=512 MByte
 
 eMMC存储器
 ^^^^^^^
 
-图 12‑8是使用8GB eMMC开发板的命令输出信息。
+下图是使用8GB eMMC开发板的命令输出信息。
+
+.. image:: media/system009.png
+   :align: center
+   :alt: 未找到图片09|
 
-|system009|
 
-图 12‑8 8GB eMMC开发板的分区信息
 
-其中的mmcblk开头的都是属于eMMC存储器的数据块，把它们所有的blocks加起来就可以算出容量（每个block大小为512Byte）：
+其中的mmcblk开头的都是属于eMMC存储器的数
+据块，把它们所有的blocks加起来就可以算出
+容量（每个block大小为512Byte）：
 
 7634944+512000+7020544+512+4096+4096 （Block）
 
@@ -148,49 +193,81 @@ eMMC存储器
 
 =7.2 GByte
 
-算出的最终结果比8G小一点，这跟SD卡标称值比实际值小的原因一样，不要纠结。
+算出的最终结果比8G小一点，这跟SD卡标称值
+比实际值小的原因一样，不要纠结。
 
 查看任务进程
 ~~~~~~
 
-在/proc文件夹下，有很多以数字命名的文件夹，这些文件夹是用来记录当前正在运行的进程状态，文件名则是他们的pid号，每一个进程都对应一个pid号，用于辨识。这些进程文件夹中包含的内容，基本上是大同小异的。使用ls命令，来查看pid为1的文件夹内容，如图
-12‑9所示。其中，fd记录里当前进程使用的文件描述，mountinfo记录了挂载信息，mem则记录了该进程的内存使用情况等。
+在/proc文件夹下，有很多以数字命名的文件夹，这些文件
+夹是用来记录当前正在运行的进程状态，文件名则是他们
+的pid号，每一个进程都对应一个pid号，用于辨识。这些
+进程文件夹中包含的内容，基本上是大同小异的。使
+用ls命令，来查看pid为1的文件夹内容，如下图所示。其中，fd记
+录里当前进程使用的文件描述，mountinfo记录了挂载信息，mem则记录了该进程的内存使用情况等。
+
+.. image:: media/system010.jpg
+   :align: center
+   :alt: 未找到图片10|
 
-|system010|
 
-图 12‑9 文件夹1的内容
 
-除了上面使用的这种方式，常用的还有top命令。该命令的功能类似于windows的任务管理器，执行效果如图 12‑10所示，该命令可以会实时地更新每个进程的使用情况，按下“q”键或“Ctrl + C”，就可以退出该命令。
+除了上面使用的这种方式，常用的还有top命令。该命令的功
+能类似于windows的任务管理器，执行效果
+如上图所示，该命令可以会实时地更新每个进程的使用
+情况，按下"q"键或"Ctrl + C"，就可以退出该命令。
 
-top
+.. code-block:: sh
+   :linenos:
+
+   top
+
+.. image:: media/system011.jpg
+   :align: center
+   :alt: 未找到图片11|
 
-|system011|
 
-图 12‑10 top命令
 
 查看支持的文件系统
 ~~~~~~~~~
 
 cat /proc/filesystems
 
-/proc/filesystems可以用来查看内核支持的文件系统类型，如图 12‑10所示。图中有部分文件系统前带有“nodev”标志，表示这些文件系统不需要挂载块设备，如网络文件系统nfs/nfs4，伪文件系统sysfs等。
+/proc/filesystems可以用来查看内核支持的文件系
+统类型，如上图所示。图中有部分文件系统前
+带有"nodev"标志，表示
+这些文件系统不需要挂载块设备，如网络文
+件系统nfs/nfs4，伪文件系统sysfs等。
+
+.. image:: media/system012.jpg
+   :align: center
+   :alt: 未找到图片12|
 
-|system012|
 
-图 12‑11 内核支持的文件系统
 
 查看CPU当前主频
 ~~~~~~~~~
 
-除了/proc目录外，在/sys目录也可以查看一些系统相关的信息，如文件/sys/devices/system/cpu/cpu0/cpufreq/cpuinfo_cur_freq包含了CPU当前的主频信息，若系统存在该文件，可以把它的内容输出来查看：
+除了/proc目录外，在/sys目录也可以查看一些系统相关的信
+息，如文件/sys/devices/system/cpu/cpu0/cpufreq/cpuinfo_cur_freq包含了CPU当
+前的主频信息，若系统存在该文件，可以把它的内容输出来查看：
+
+.. code-block:: sh
+   :linenos:
+
+   cat /sys/devices/system/cpu/cpu0/cpufreq/cpuinfo_cur_freq
+
+.. image:: media/system013.png
+   :align: center
+   :alt: 未找到图片13|
+
+
+
+如上图中的输出，表示当前CPU主频为792MHz。
 
-cat /sys/devices/system/cpu/cpu0/cpufreq/cpuinfo_cur_freq
 
-|system013|
 
-图 12‑12 当前CPU主频
 
-如图 12‑12中的输出，表示当前CPU主频为792MHz。
 
 .. |system002| image:: media/system002.png
    :width: 5.82381in
diff --git a/documentation/linux_basis/user_group.rst b/documentation/linux_basis/user_group.rst
index e9feea28cd006af6e3f9e5d04a30cb106a683a68..58686a2a2675ac31b911a5f11fdc78872d42c3d0 100644
--- a/documentation/linux_basis/user_group.rst
+++ b/documentation/linux_basis/user_group.rst
@@ -2,71 +2,115 @@
 
 用户组与文件权限
 --------------------------------
-
 用户及用户组
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
 在早期的Windows操作系统，如Windows 95 和 Windows
-XP，都是单用户操作系统。所谓的单用户操作系统，就是说在同一时间，只能由一个用户独自享用系统的全部硬件和软件资源。我们现在所使用的win7、win8以及win10都是多用户操作系统，与单用户操作系统恰恰相反，它支持多个用户能够同时访问和使用同一台计算机的全部硬件和软件资源，
+XP，都是单用户操作系统。所谓的单用户操作系统，就是说在同一时间，只能由
+一个用户独自享用系统的全部硬件和软件资源。我们现在所使用的win7、win8以
+及win10都是多用户操作系统，与单用户操作系统恰恰相反，它支持多个用户能够同时访
+问和使用同一台计算机的全部硬件和软件资源，
+
+在众多用户中，其中的一个用户administrator具有管理其他用户账号和计算机的全
+部资源的权限。我们在安装软件的时候，经常会看到"要以管理员身份运行该软件"，又
+或者是下图，实际上就是要求我们给予程序一些管理员的权限。
+
 
-在众多用户中，其中的一个用户administrator具有管理其他用户账号和计算机的全部资源的权限。我们在安装软件的时候，经常会看到“要以管理员身份运行该软件”，又或者是图 6‑1，实际上就是要求我们给予程序一些管理员的权限。
+.. image:: media/usergr002.jpg
+   :align: center
+   :alt: 未找到图片2|
 
-|usergr002|
 
-图 6‑1 以管理员身份运行
 
-Linux操作系统，同样也是多用户操作系统，其中具有管理其他用户和计算机的全部资源的用户，称为root。前面提及过安卓系统，实质上也是基于Linux，安卓手机上常常提到的root权限，也就是获取最高的权限，就跟电脑获取超级管理员的权限是一样的。
+Linux操作系统，同样也是多用户操作系统，其中具有管理
+其他用户和计算机的全部资源的用户，称为root。前面提及过安卓系统，实质
+上也是基于Linux，安卓手机上常常提到的root权限，也就是获取最高的权限，就跟电
+脑获取超级管理员的权限是一样的。
 
-在Linux中，每个用户都有一个特定的编号——UID，用于标识一个系统用户。Linux将标号0分配给root用户的uid，它可以分配给每个用户不同的权限，因此每个用户可进行的操作也不同。
+在Linux中，每个用户都有一个特定的编号——UID，用于标识一个系统用户。Linux将
+标号0分配给root用户的uid，它可以分配给每个用户不同的权限，因此每个用户可进
+行的操作也不同。
 
 我们可以通过id命令来查看当前用户的UID值（关于如何使用命令在下一章介绍，此处先了解）：
 
-id
+.. code-block:: sh
+   :linenos:
 
-|usergr003|
+   id
 
-图 6‑2 当前用户的uid
+.. image:: media/usergr003.jpg
+   :align: center
+   :alt: 未找到图片3|
 
-图 6‑2中的gid用于标识当前用户所在的分组（Group），每个用户可以对应多个分组。就好像学校里面有音乐社，动漫社，文学社等社团，每个学生可以去参加多个社团，这样才能够接触到各种各样有趣的东西。Linux系统拥有多个分组，每个用户分组就相当社团，用户如果是多个用户组的成员，就可以访问其他分组对应
+
+
+上图中的gid用于标识当前用户所在的
+分组（Group），每个用户可以对应多个分组。就好像学校里面
+有音乐社，动漫社，文学社等社团，每个学生可以去参加多个社团，这样才
+能够接触到各种各样有趣的东西。Linux系统拥有多个分组，每个用户分组就相当社
+团，用户如果是多个用户组的成员，就可以访问其他分组对应
 的文件，前提是该分组的文件允许其他用户访问，这就需要了解大标题的另一个知识点：文件权限。
 
-|usergr004|
+.. image:: media/usergr004.jpg
+   :align: center
+   :alt: 未找到图片4|
+
 
-图 6‑3 Linux中分组情况
 
 文件权限
 ~~~~~~~~~~~~~~~~
 
 在Windows系统中我们经常接触的文件属性，无非就是以下两种属性：只读、隐藏。
 
-从字面上的意思，我们也很好理解。具有只读属性的文件，我们不能对文件的内容进行修改。而具有隐藏属性的文件，我们一般情况下是看不到的。
+从字面上的意思，我们也很好理解。具有只读属性的文件，我们
+不能对文件的内容进行修改。而具有隐藏属性的文件，我们一般情况下是看不到的。
 
-|usergr005|
+.. image:: media/usergr005.jpg
+   :align: center
+   :alt: 未找到图片5|
 
-图 6‑4 Windows文件属性
 
-在windows上，通过选中文件，然后右键调出菜单，就可以看到“属性”选项，那如何在Linux查看一个文件的属性？其实，查看方法和Windows相差无几，同样也是先选中一个文件，右键可以看到图 6‑5右侧的菜单。我们通过最下面的“属性”选项来查看某个文件的具体情况， 如图 6‑6所示。
 
-|usergr006|
+在windows上，通过选中文件，然后右键调出菜单，就可以看到"属性"选
+项，那如何在Linux查看一个文件的属性？其实，查看方法和Windows相差
+无几，同样也是先选中一个文件，右键可以看到下图右侧的菜单。我们通过最
+下面的"属性"选项来查看某个文件的具体情况， 如下图所示。
 
-图 6‑5 wins和linux右键菜单
+.. image:: media/usergr006.jpg
+   :align: center
+   :alt: 未找到图片6|
 
-|usergr007|
 
-图 6‑6 文件属性
 
-Linux的文件属性，可以分为读权限、写权限、执行权限。读权限以及写权限，基本上和Windows操作系统是一样的。关于执行权限，是指可以加载到内存中，并由操作系统加载程序执行的文件。在Windows操作系统中，我们接触最多的应该是后缀为.exe的文件。但是对于Linux来说，它并不是通过后缀名来识别
-文件类型的，如果我们想要执行某个可执行文件，则需要为其添加执行权限，如图 6‑7 分配执行权限所示。
+.. image:: media/usergr007.jpg
+   :align: center
+   :alt: 未找到图片7|
 
-|usergr008|
 
-图 6‑7 分配执行权限
 
-除此之外，关于Linux文件权限，还需要分三种情况：文件拥有者，分组成员以及其他分组成员，分别对应图 6‑6
-文件属性的、、部分。该文件允许文件拥有者embedfire和位于embedfire分组的其他成员，对该文件的内容进行读写操作，而其他分组的用户则只能阅读该文件，并不能对该文件进行修改。如果我们想修改其他分组的文件，我们可以修改该文件的其他分组所拥有的权限。
+Linux的文件属性，可以分为读权限、写权限、执行权限。读权限以
+及写权限，基本上和Windows操作系统是一样的。关于执行权限，是指
+可以加载到内存中，并由操作系统加载程序执行的文件。在Windows操作系统中，我们接触最多的应该是后缀为.exe的文件。但是对于Linux来说，它并不是通过后缀名来识别
+文件类型的，如果我们想要执行某个可执行文件，则需要为其添加执
+行权限，如下图所示 分配执行权限所示。
+
+.. image:: media/usergr008.png
+   :align: center
+   :alt: 未找到图片8|
+
+
+
+除此之外，关于Linux文件权限，还需要分三种情况：文件
+拥有者，分组成员以及其他分组成员，分别对应
+文件属性的、、部分。该文件允许文件拥有者embedfire和位于embedfire
+分组的其他成员，对该文件的内容进行读写操作，而其他分组的用户则只能
+阅读该文件，并不能对该文件进行修改。如果我们想修改其他分组的文件，我们可以
+修改该文件的其他分组所拥有的权限。
 
 在后面学会使用命令行后，我们可以通过chmod命令在终端快速地修改文件的权限。
 
+
+
 .. |usergr002| image:: media/usergr002.jpg
    :width: 3.33333in
    :height: 0.29167in
diff --git a/documentation/linux_basis/why_learning_linux.rst b/documentation/linux_basis/why_learning_linux.rst
index 4621132cebb0e74e27765ad2aa473e43466ec498..392d5e0e07897cc4d401afbaf777abb418b57761 100644
--- a/documentation/linux_basis/why_learning_linux.rst
+++ b/documentation/linux_basis/why_learning_linux.rst
@@ -4,7 +4,8 @@
 ------------------------
 
 
-本章主要从Linux的应用场景，程序员的技能学习，职业方向来讨论为什么需要学习Linux开发并对如何学好Linux开发提出了一些建议。
+本章主要从Linux的应用场景，程序员的技能学习，职业方向来
+讨论为什么需要学习Linux开发并对如何学好Linux开发提出了一些建议。
 
 Linux的应用场景
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
@@ -17,36 +18,59 @@ Linux的应用场景主要是由其特点决定的，其特点主要有：开源
 服务器
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^
 
-服务器是指提供计算服务的设备，如网页服务器、文件服务器、数据库服务器、邮件服务器、域名服务器和代理服务器等。可以说我们在互联网上的所有操作，背后都是在跟服务器打交道。例如我们访问网页、网上购物、微信聊天、运行网络游戏、观看在线视频等一切需要联网才能正常进行的应用，其背后都由服务器作为支撑。
+服务器是指提供计算服务的设备，如网页服务器、文件
+服务器、数据库服务器、邮件服务器、域名服务器和代理服务
+器等。可以说我们在互联网上的所有操作，背后都是在跟服务
+器打交道。例如我们访问网页、网上购物、微信聊天、运行网络
+游戏、观看在线视频等一切需要联网才能正常进行的应用，其背
+后都由服务器作为支撑。
 
-服务器的实体各种各样，小到单板电脑，大至计算机集群，实际上你正在使用的个人电脑，安装上对应的服务软件，通过网络给其它计算机提供资源，它也就变身成了一个服务器。服务器的本质也是计算机，只是通常来说它们没有显示器，不需要鼠标键盘。
+服务器的实体各种各样，小到单板电脑，大至计算机集群，实际上你
+正在使用的个人电脑，安装上对应的服务软件，通过网络给其它计算机提
+供资源，它也就变身成了一个服务器。服务器的本质也是计算机，只是通
+常来说它们没有显示器，不需要鼠标键盘。
 
-在商业应用中，在服务器运行的操作系统主要有Linux、Windows和UNIX，其中由于Linux系统开源、使用成本低而且安全稳定，所以Linux在服务器使用的系统中占据了绝大多数。
+在商业应用中，在服务器运行的操作系统主要有Linux、Windows和UNIX，其中
+由于Linux系统开源、使用成本低而且安全稳定，所以Linux在服务器使用的系统中占据了绝大多数。
 
-感兴趣的读者可以访问Netcraft 网站 http://www.netcraft.com，可以查询到其它网站是运行在什么操作系统上的，具体见图 1‑1和图 1‑2。
+感兴趣的读者可以访问Netcraft 网站 http://www.netcraft.com，可以查询
+到其它网站是运行在什么操作系统上的，具体见下图。
 
 .. image:: media/whylea002.png
    :align: center
-   :alt: Netcraft网站输入要查询的网址
+   :alt: 未找到图片
 
-图 1‑1 Netcraft网站输入要查询的网址
 
-|whylea003|
 
-图 1‑2 查询的网站使用的操作系统
+.. image:: media/whylea003.png
+   :align: center
+   :alt: 未找到图片
+
+
 
-可以查询到绝大部分知名网站都运行在Linux系统之上，包括微软官网：www.microsoft.com。而国内的一些银行官网则通常使用Windows Server系统。
+
+
+可以查询到绝大部分知名网站都运行在Linux系统之上，包括微
+软官网：www.microsoft.com。而国内的一些银行官网则通常使用Windows Server系统。
 
 特别地，超级计算机也是特殊的服务器，目前全球TOP500的计算机运行的操作系统都是Linux。
 
 嵌入式设备
 ^^^^^^^^^^^^^^^^^
 
-嵌入式设备是Linux系统的另一个主战场，这也是本书主要讲解的Linux应用方向。嵌入式设备的定义比较模糊，不过基本上把PC、集群服务器、超级计算机排除后，具有处理器（包括微控制器等）的，按设定程序运行的电子设备大都可以归类为嵌入式设备。
+嵌入式设备是Linux系统的另一个主战场，这也是本书主
+要讲解的Linux应用方向。嵌入式设备的定义比较模糊，不过基本上把PC、集群
+服务器、超级计算机排除后，具有处理器（包括微控制器等）的，按设定程序运行
+的电子设备大都可以归类为嵌入式设备。
 
-嵌入式设备种类非常丰富，包括日常生活中的手机、智能手表、各种家电、玩具、路由器、车载电子系统，工业应用中包括电力系统监控、环境监测、工业机器人、智能快递柜、手持POS机、地铁闸机系统、停车场管理、卫星、月球车等。
+嵌入式设备种类非常丰富，包括日常生活中的手机、智能手表、各
+种家电、玩具、路由器、车载电子系统，工业应用中包括电力系统监控、环境
+监测、工业机器人、智能快递柜、手持POS机、地铁闸机系统、停车场管理、卫星、月球车等。
 
-从嵌入式设备的种类就可以知道它们的应用场景是碎片化的，它们内部的电子系统一般会针对设备的功能做专用的控制。部分嵌入式设备不使用操作系统；部分使用freeRTOS等实时操作系统；而另一些高性能的嵌入式设备使用Linux系统。使用Linux系统的的嵌入式设备，往往是看中Linux系统的如下特性：
+从嵌入式设备的种类就可以知道它们的应用场景是碎片化的，它们内
+部的电子系统一般会针对设备的功能做专用的控制。部分嵌入式设备不使用
+操作系统；部分使用freeRTOS等实时操作系统；而另一些高性能的嵌入式设备
+使用Linux系统。使用Linux系统的的嵌入式设备，往往是看中Linux系统的如下特性：
 
 -  嵌入式设备使用的处理器多种多样，而Linux系统支持运行在x86、ARM、PowerPC、MIPS等不同平台的处理器上。
 
@@ -78,59 +102,50 @@ Linux应用软件开发就是开发基于Linux系统的应用程序。具体而
 设备驱动开发
 ^^^^^^^^^^^^^^^^^^^^^^^^
 
-设备驱动，它的本质也是软件程序，不过它介于硬件与操作系统之间的层级，是硬件和操作系统之间的桥梁，具体见图 1‑3。
+设备驱动，它的本质也是软件程序，不过它介于硬件与操作系统之间的层级，是硬件和操作系统之间的桥梁，具体见下图。
 
-|whylea004|
+.. image:: media/whylea004.png
+   :align: center
+   :alt: 未找到图片
 
-图 1‑3 驱动程序在Linux系统中的位置
 
-对于不使用操作系统或使用小型实时操作系统（如freeRTOS）的设备来说，与硬件相关的驱动程序与应用程序往往混合在一起，因此常常不会对驱动与应用进行严格的区分，这也导致更换硬件平台时，应用程序移植困难。
 
-使用了Linux系统的设备，硬件会由操作系统接管。Linux系统的一个重要设计哲学是一切皆文件。包括硬件设备，对于系统来说也是一个文件，所以系统向上层应用程序提供open、write、read、close等统一的文件操作接口，应用程序可以利用这些接口对设备文件进行访问，从而实现对硬件设备的初始化、写
+对于不使用操作系统或使用小型实时操作系统（如freeRTOS）的设备来说，与硬件相关的驱动
+程序与应用程序往往混合在一起，因此常常不会对驱动与应用进行严格的区分，这也导
+致更换硬件平台时，应用程序移植困难。
+
+使用了Linux系统的设备，硬件会由操作系统接管。Linux系统的一个重要设计哲
+学是一切皆文件。包括硬件设备，对于系统来说也是一个文件，所以系统向上层应用程
+序提供open、write、read、close等统一的文件操作接口，应用程序可以利用这些接口对
+设备文件进行访问，从而实现对硬件设备的初始化、写
 入、读取以及关闭等操作。
 
-当系统接收到应用程序的这些访问请求时，它会向下查询对应设备具体的操作函数，然后调用相应的函数处理请求，而这些针对不同设备具体的操作函数就是设备驱动程序。因此，设备驱动就是这样一种把硬件与操作系统连接在一起的程序，Linux系统会提供统一的格式，设备驱动开发工程师根据具体的设备按照系统格式要求实现相应
+当系统接收到应用程序的这些访问请求时，它会向下查询对应设备具体的操作函数，然后调
+用相应的函数处理请求，而这些针对不同设备具体的操作函数就是设备驱动程序。因此，设备驱
+动就是这样一种把硬件与操作系统连接在一起的程序，Linux系统会提供统一的格式，设备驱动开
+发工程师根据具体的设备按照系统格式要求实现相应
 的设备操作函数。
 
-本书主要针对嵌入式设备驱动开发的讲解，对于志在应用软件开发的工程师，也可通过本书的内容掌握Linux底层的相关知识，这对应用开发也是大有裨益。
+本书主要针对嵌入式设备驱动开发的讲解，对于志在应用软件开发的工程师，也可通过本书的
+内容掌握Linux底层的相关知识，这对应用开发也是大有裨益。
 
 程序员的宝库
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
-Linux可谓是公开的宝库，它是开源世界的代表作，它的内核源代码是完全公开的，只要你愿意沉浸其中，必定收获丰富。通过学习Linux开发，会熟悉命令行的使用；可以了解到操作系统原理；学习常用数据结构，如链表、红黑树、哈希表等；了解开源社区的文化，学习各自优秀的代码实现，如常用的C语言库libc等；熟悉
+Linux可谓是公开的宝库，它是开源世界的代表作，它的内核源代码是完全公开的，只要你
+愿意沉浸其中，必定收获丰富。通过学习Linux开发，会熟悉命令行的使用；可以了解到操作
+系统原理；学习常用数据结构，如链表、红黑树、哈希表等；了解开源社区的文化，学习各自优
+秀的代码实现，如常用的C语言库libc等；熟悉
 各种常用开发工具，如Git版本管理系统、GCC编译器。
 
-并不是说从事传统MCU开发或Windows开发时不能学习到这些，只是这些内容往往被包装起来，要么直接无法追根溯源，要么隐藏起来了。但在进行Linux开发时，相关的内容是直接暴露给用户的，只要钻得够深，永远有惊喜等待着我们。例如，使用Keil或IAR开发时，我们不知道调用C语言库的printf函数后，
+并不是说从事传统MCU开发或Windows开发时不能学习到这些，只是这些内容往往被包装起
+来，要么直接无法追根溯源，要么隐藏起来了。但在进行Linux开发时，相关的内容是直
+接暴露给用户的，只要钻得够深，永远有惊喜等待着我们。例如，使用Keil或IAR开发时，
+我们不知道调用C语言库的printf函数后，
 具体究竟执行了什么；点击编译按钮时，集成的工具又为我们处理了一些什么内容，这些我们都很难了解到。
 
 对于长期从事MCU开发的程序员来说，学习Linux开发会让人感叹，原来代码的世界一直在这里等着我！
 
-如何学习Linux设备驱动开发
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-
-希望经过前面介绍Linux的应用场景、职业方向以及学习Linux对编程技能提升的好处，能让你更加坚定地开始学习Linux开发。那么该如何学习呢？对于Linux设备驱动开发工程师，会有如下基本要求：
-
--  学好英语
-
--  打磨C语言基础，要求熟练运用指针、结构体及各种C库的使用
-
--  熟悉Linux下编写基本的应用程序，如文件操作、在应用层控制硬件设备等
-
--  熟悉各种常用设备通讯协议，如UART、I2C及SPI等
-
--  熟悉不同的存储设备及其读写特性，如SDRAM、NAND FLASH、Nor FLASH等
-
--  熟悉Linux内核机制和各种驱动框架
-
--  对多任务和并发控制等应用自如
-
-总而言之，Linux开发涉及非常庞大的知识体系，只有通过大量的动手实践和阅读才能深入掌握，同时，也不要局限自己，多了解一下Linux运维和应用开发相关的知识也很有帮助。在学习时，也多进行类比，如在熟悉Linux系统时，类比Windows下的习惯，编写程序时，多类比它与MCU开发时的异同。
-
-学习设备驱动开发，建议要使用开发板。虽然使用QEMU软件可以模拟电路板，但对于初学者来说没有办法建立切实的概念，一切全凭想像，这样的学习如同架构在幻境之上，没法落地。也不要使用树莓派等设备，使用树莓派的爱好者很多，有活跃的社区，因而有非常多的资源可以参考，但这些都是利用树莓派制作应用。虽然在制作应用
-时可以参考，但因为树莓派使用的主控芯片公开的硬件资料比较少，而编写设备驱动时又必须了解芯片具体的各项特性和外设，对于设备驱动工程师来说，目标是制作一个树莓派，而不仅仅是把它当一个单板Linux设备来应用。
-
-学习是一个螺旋上升的过程，学习到后面的章节，再回过头来再看一遍本书，会发现刚开始学习时以为自己了解的东西又深入了一遍。
-
 推荐书单
 ~~~~~~~~~~~~~~~~~~~~
 
@@ -146,6 +161,9 @@ Linux可谓是公开的宝库，它是开源世界的代表作，它的内核源
 
 -  野火《RT-Thread内核实现与应用开发实战指南》和《FreeRTOS内核实现与应用开发实战指南》，针对嵌入式实时操作系统讲解，通过它们可掌握操作系统相关的概念。
 
+
+
+
 .. |whylea002| image:: media/whylea002.png
    :width: 2.34076in
    :height: 0.97619in
diff --git a/documentation/linux_debug/backtrace.rst b/documentation/linux_debug/backtrace.rst
new file mode 100644
index 0000000000000000000000000000000000000000..48031c8affe2931ec182bf5b485d19c5bcceae38
--- /dev/null
+++ b/documentation/linux_debug/backtrace.rst
@@ -0,0 +1,379 @@
+gdb调试之函数调用栈——backtrace
+==============================
+
+什么是函数调用栈
+----------------
+
+在写代码的时候，我们会封装很多函数，而这些函数之中又会调用其他的函数，当程序每次调用函数的时候，就会跳转到函数的地方去执行，那么这期间就有很多信息产生了，比如：调用函数的地方，函数的参数，被调用函数的变量等，这些信息其实是存储在栈中的，其实更确切地说，这些信息是存储在函数调用信息帧中的，每个函数及其变量都被分配了一个帧（frame），这些函数信息帧就组成了函数调用栈。我们使用
+gdb
+调试工具就可以查看函数调用栈的内容信息，可以清晰地看到各个函数的调用顺序以及各函数的输入形参值，是分析程序的执行流程和输入依赖的重要手段。
+
+gdb提供了一些指令可以查看这些帧中的信息，当查询函数变量的信息时，gdb就是从这个被选中的帧内获取信息，但是查看被选中帧外的变量信息是非法的，当程序运行停止的时候，gdb会自动选择当前被调用的函数帧，并且打印简单帧信息。
+
+gdb中函数调用栈的指令
+---------------------
+
+查看栈信息
+~~~~~~~~~~
+
+-  ``bt`` ：bt是 ``backtrace`` 指令的缩写，显示所有的函数调用栈的信息，栈中的每个函数都被分配了一个编号，最近被调用的函数在
+   0 号帧中（栈顶），并且每个帧占用一行。
+
+-  ``bt n`` ：显示函数调用栈从栈顶算起的n帧信息（n 表示一个正整数）。
+
+-  ``bt -n`` ：显示函数调用栈从栈底算起的n帧信息。
+
+-  ``bt full`` ：显示栈中所有信息如：函数参数，本地变量等。
+
+-  ``bt full n`` ：显示函数调用栈从栈顶算起的n帧的所有信息。
+
+-  ``bt full -n`` ：显示函数调用栈从栈底算起的n帧的所有信息。
+
+查看帧信息
+~~~~~~~~~~
+
+上面的bt指令主要是查看栈的信息，而每一帧都会有详细的信息，这些函数调用信息帧包括：调用函数的地方，函数的参数等。如果想查看栈中某一帧的信息，首先要做的是切换当前栈。这时候需用用到
+frame 指令（缩写形式为 f）。
+
+-  ``f n``: 它的功能是切换到编号为 n 的栈帧（n
+   表示一个正整数），并显示相关信息。
+
+up/down 指令
+~~~~~~~~~~~~
+
+除了使用 frame 指令切换栈帧外，还可以使用 up 和 down 指令。
+
+-  ``down n`` ：表示往栈顶方向下移 n 层（n 表示一个正整数，默认值为
+   1）。
+-  ``up n`` ：表示往栈底方向上移 n 层。
+
+查看更详细的帧信息
+~~~~~~~~~~~~~~~~~~
+
+info
+指令是一个很强大的指令，使用它可以查看各种变量的值，如果我们希望看到详细的函数调用信息帧的信息，如：函数地址、调用函数的地址、被调用函数的地址、当前函数由哪种编程语言编写、函数参数地址及形参值、局部变量的地址、当前桢中存储的寄存器等，可以使用以下指令：
+
+-  ``info frame`` ：
+   指令的缩写形式为 ``i f`` ，查看函数调用帧的所有信息。
+
+-  ``info args`` ：查看函数变量的值。
+
+-  ``info locals`` ：查看本地变量的信息。
+
+除此之外 info 指令还可以查看当前寄存器的值：
+
+-  ``info registers`` ：查看寄存器的情况（除了浮点寄存器）。
+
+-  ``info all-registers`` ：查看所有寄存器的情况（包括浮点寄存器）。
+
+gdb调试实战
+-----------
+
+调试源码
+~~~~~~~~
+
+首先我们得写一份可以调试函数调用栈的代码，也就是说一个函数要调用其他函数，层层调用，这样子才能在调试中看得出来调用栈相关的信息，代码如下：
+
+.. code:: c
+
+    #include <sys/types.h>
+    #include <unistd.h>
+    #include <stdio.h>
+    #include <stdlib.h>
+
+    void test1(int arg)
+    {
+        int num;
+        num = arg;
+        
+        printf("\t\t---我是 test%d 函数\n", num);
+    }
+
+    void test2(int arg)
+    {
+        int num;
+        num = arg;
+
+        printf("\t--我是 test%d 函数\n", num);
+
+        printf("\t-- test%d 开始调用 test1 \n", num);
+        test1(1);
+        printf("\t-- test%d 结束调用 test1 \n", num);
+
+        printf("\t--结束调用 test%d \n", num);
+    }
+
+    void test3(int arg)
+    {
+        int num;
+        num = arg;
+
+        printf("-我是 test%d 函数\n", num);
+
+        printf("- test%d 开始调用 test2 \n", num);
+        test2(2);
+        printf("- test%d 结束调用 test1 \n", num);
+
+        printf("-结束调用 test%d \n", num);
+    }
+
+    int main(void)
+    {
+        test3(3);
+
+        sleep(1);       // 防止进程过快退出
+
+        return 0;
+    }
+
+代码呢非常简单，函数的调用关系如下:
+
+.. code:: bash
+
+    main()
+        ->test3()
+            ->test2()
+                ->test1()
+
+然后我们将源码编译，然后使用gdb调试器进行调试，我们在实际调试的时候，先去到最底层的地方，即test1()函数中，查看它被调用的关系，具体操作如下：
+
+1. 编译源码，并尝试运行它，可以很明显看到函数的调用关系信息：
+
+.. code:: bash
+
+    ➜  backtrace git:(master) ✗ make
+    gcc -o backtrace.o -c -g -Werror -I. -Iinclude -static backtrace.c -g -MD -MF .backtrace.o.d
+    gcc -o targets backtrace.o -g -Werror -I. -Iinclude -static
+
+    # 运行
+    ➜  backtrace git:(master) ✗ ./targets 
+    -我是 test3 函数
+    - test3 开始调用 test2 
+            --我是 test2 函数
+            -- test2 开始调用 test1 
+                    ---我是 test1 函数
+            -- test2 结束调用 test1 
+            --结束调用 test2 
+    - test3 结束调用 test1 
+    -结束调用 test3 
+
+2. 使用gdb调试器进行调试：
+
+.. code:: bash
+
+    ➜  backtrace git:(master) ✗ gdb ./targets 
+
+    ···
+    Reading symbols from ./targets...done.
+    (gdb) 
+
+3. 在test1()函数中打上断点，并运行到断点处，代码运行期间会打印出相关的信息：
+
+.. code:: bash
+
+    # 打断点
+    (gdb) b test1
+    Breakpoint 1 at 0x400b58: file backtrace.c, line 9.
+
+    # 运行到断点处
+    (gdb) r
+    Starting program: /home/jiejie/embed_linux_tutorial/base_code/linux_debug/backtrace/targets 
+
+    # 这些就是代码运行时打印的信息
+    -我是 test3 函数
+    - test3 开始调用 test2 
+            --我是 test2 函数
+            -- test2 开始调用 test1 
+
+    Breakpoint 1, test1 (arg=1) at backtrace.c:9
+    9           num = arg;
+
+4. bt指令查看函数调用栈：
+
+可以看到一些基本的信息，如函数调用信息帧的地址，传递的参数arg的值，以及代码的位置等信息。
+
+.. code:: bash
+
+    (gdb) bt
+    #0  test1 (arg=1) at backtrace.c:9
+    #1  0x0000000000400bbe in test2 (arg=2) at backtrace.c:22
+    #2  0x0000000000400c34 in test3 (arg=3) at backtrace.c:36
+    #3  0x0000000000400c71 in main () at backtrace.c:44
+
+    (gdb) bt 2
+    #0  test1 (arg=1) at backtrace.c:9
+    #1  0x0000000000400bbe in test2 (arg=2) at backtrace.c:22
+    (More stack frames follow...)
+
+    (gdb) bt -2
+    #2  0x0000000000400c34 in test3 (arg=3) at backtrace.c:36
+    #3  0x0000000000400c71 in main () at backtrace.c:44
+
+5. f指令切换帧：
+
+.. code:: bash
+
+    (gdb) f 2
+    #2  0x0000000000400c34 in test3 (arg=3) at backtrace.c:36
+    36          test2(2);
+
+    (gdb) f 3
+    #3  0x0000000000400c71 in main () at backtrace.c:44
+    44          test3(3);
+
+6. ``info frame`` 指令查看函数调用帧的所有信息，在这步操作前我们切换回到test1函数中（切换帧）。
+
+.. code:: bash
+
+    # 切换帧 0
+    (gdb) f 0
+    #0  test1 (arg=1) at backtrace.c:9
+    9           num = arg;
+
+    # 查看信息
+    (gdb) i f
+    Stack level 0, frame at 0x7fffffffe030:
+     rip = 0x400b58 in test1 (backtrace.c:9); saved rip = 0x400bbe
+     called by frame at 0x7fffffffe060
+     source language c.
+     Arglist at 0x7fffffffe020, args: arg=1
+     Locals at 0x7fffffffe020, Previous frame's sp is 0x7fffffffe030
+     Saved registers:
+      rbp at 0x7fffffffe020, rip at 0x7fffffffe028
+
+这里面有很多信息：
+
+-  当前桢的地址：0x7fffffffe030。
+
+-  rip的值：0x400b58，此处引申介绍一下rip是什么：它是指令地址寄存器，用来存储
+   CPU 即将要执行的指令地址。每次 CPU 执行完相应的汇编指令之后，rip
+   寄存器的值就会自行累加，rip 无法直接赋值。
+
+-  当前桢函数：test1 (backtrace.c:9)。
+
+-  调用者的rip值：saved rip = 0x400bbe。
+
+-  调用者的帧地址：0x7fffffffe060。
+
+-  源代码所用的程序的语言: source language c。
+
+-  当前桢的参数的地址及值：Arglist at 0x7fffffffe020, args: arg=1。
+
+-  当前帧中局部变量的地址：Locals at 0x7fffffffe020, Previous frame's sp
+   is 0x7fffffffe030。
+
+-  当前桢中存储的寄存器：rbp at 0x7fffffffe020, rip at 0x7fffffffe028。
+
+7. ``info args`` 指令查看函数变量的值。
+
+.. code:: bash
+
+    (gdb) info args 
+    arg = 1
+
+8. ``info locals`` 指令查看本地变量的信息，如果此时还未运行变量赋值语句，则变量不会有值。
+
+.. code:: bash
+
+    Breakpoint 1, test1 (arg=1) at backtrace.c:9
+    9           num = arg;
+    (gdb) s
+    11          printf("\t\t---我是 test%d 函数\n", num);
+    (gdb) info locals
+    num = 1
+
+1. 查看当前寄存器的值（不包括浮点寄存器）：
+
+.. code:: bash
+
+    (gdb) info registers
+    rax            0x1      1
+    rbx            0x400400 4195328
+    rcx            0x0      0
+    rdx            0x6bbd30 7060784
+    rsi            0x0      0
+    rdi            0x1      1
+    rbp            0x7fffffffe020   0x7fffffffe020
+    rsp            0x7fffffffe000   0x7fffffffe000
+    r8             0x0      0
+    r9             0x1e     30
+    r10            0x0      0
+    r11            0x246    582
+    r12            0x401a00 4200960
+    r13            0x0      0
+    r14            0x6b9018 7049240
+    r15            0x0      0
+    rip            0x400b5e 0x400b5e <test1+17>
+    eflags         0x206    [ PF IF ]
+    cs             0x33     51
+    ss             0x2b     43
+    ds             0x0      0
+    es             0x0      0
+    fs             0x0      0
+    gs             0x0      0
+
+gdb调试递归函数
+---------------
+
+本小节的主题是教大家用gdb去调试递归函数，因为一步步去调试太麻烦了，也没法打断点，因为打断点每次递归时都会停下来，实在是难以调试，那么强大如gdb调试工具，对这种递归函数的调试也是轻而易举的。
+
+我们用递归算法计算斐波拉契数列，这是在大学C语言课本中的非常有名的递归算法——计算斐波拉契数列，我们回顾一下是什么是斐波拉契数列：斐波那契数列由
+0 和 1 开始，之后的斐波那契数就是由之前的两数相加而得出。
+
+递归算法计算就非常简单啦，代码如下：
+
+.. code:: c
+
+    int fibonacci(int n)
+    {       
+        if (n == 1 || n == 2) {   
+            return 1;
+        }   
+
+        return fibonacci(n - 1) + fibonacci(n - 2);                                                                                                            
+    }       
+            
+    int main()
+    {       
+        int n = 10; 
+        int ret = 0;
+
+        ret = fibonacci(n);
+
+        printf("fibonacci(%d)=%d\n", n, ret);
+
+        return 0;
+    }
+
+编译后使用gdb调试，比如我打算当递归函数fibonacci()中 n
+的值为5时，停下来，然后查看函数的调用栈：
+
+.. code:: bash
+
+    # 启动gdb调试
+    ➜  backtrace git:(master) ✗ gdb ./targets 
+
+    # 打断点，当n等于5时在断点处停下
+    (gdb) b fibonacci if n==5
+    Breakpoint 1 at 0x400b59: file backtrace.c, line 54.
+
+    # 运行，停下来时n已经等于5了
+    (gdb) r
+    Starting program: /home/jiejie/embed_linux_tutorial/base_code/linux_debug/backtrace/targets 
+
+    Breakpoint 1, fibonacci (n=5) at backtrace.c:54
+    54          if (n == 1 || n == 2) { 
+
+    # 查看函数调用栈
+    (gdb) bt
+    #0  fibonacci (n=5) at backtrace.c:54
+    #1  0x0000000000400b79 in fibonacci (n=6) at backtrace.c:58
+    #2  0x0000000000400b79 in fibonacci (n=7) at backtrace.c:58
+    #3  0x0000000000400b79 in fibonacci (n=8) at backtrace.c:58
+    #4  0x0000000000400b79 in fibonacci (n=9) at backtrace.c:58
+    #5  0x0000000000400b79 in fibonacci (n=10) at backtrace.c:58
+    #6  0x0000000000400bb1 in main () at backtrace.c:66
+
+    # 其他的一些操作...
+
+至此，本章内容讲解完毕，更多的gdb调试信息大家可以亲身去体验。
diff --git a/documentation/linux_debug/core_dump.rst b/documentation/linux_debug/core_dump.rst
new file mode 100644
index 0000000000000000000000000000000000000000..9117794ac9c0a95ae918ee9450a32b0644942205
--- /dev/null
+++ b/documentation/linux_debug/core_dump.rst
@@ -0,0 +1,298 @@
+核心转储调试
+=============
+
+核心转储——core文件简介
+----------------------
+
+核心转储文件（core文件，也被称之为core
+dump文件，可能某些书籍上称之为“内核转储文件”，都是一样的，不必纠结名称）
+是操作系统在进程收到某些信号而终止运行时，将此时进程地址空间的内容以及有关进程状态的其他信息写入一个磁盘文件，
+这个文件就是核心转储文件，它里面包含了进程崩溃时的所有信息，比如包含终止时进程内存的映像、寄存器状态，堆栈指针，
+内存管理信息等，而这种信息往往用于调试，比如在gdb调试器使用，导致进程终止运行的信号可以在系统的signal列表中找到。
+
+为什么要学这个东西呢，因为是程序员总会写bug的，我们的程序一旦运行，一开始可能没什么问题，但是谁能保证一个
+很大的工程没有一点问题呢，那么如果我们使用了核心转储，在程序运行崩溃时我们就能找到程序出现问题的地方，对于
+调试还是解bug都是非常好的，虽然程序崩溃了，但是它留下来现场的数据啊，就跟开车撞了别人一样，被监控拍到了，
+就能知道当时发生了什么事情。
+
+简单的说，在一个程序崩溃时，系统会在指定目录下生成一个core文件，core文件主要是用来调试的。
+
+打开或关闭core文件的生成
+------------------------
+
+在默认情况下，系统是没有打开core文件生成的，比如我的服务器ubuntu18.04就是没有打开core文件生成的功能，
+当程序崩溃了我也不知道它哪里出现问题，那么我们可以通过以下命令打开core文件的生成：
+
+.. code:: bash
+
+    # 改为无限制大小
+    ulimit -c unlimited     
+
+如果想检验你们的系统是否打开了core文件的生成，那么可以通过以下命令判断，如果终端打印的值是0，则代表系统并未开启
+生成core文件的功能，而如果是其他数值：比如1024，这代表系统最大可以产生1024字节的core文件，而如果是unlimited则
+代表系统不限制core文件的大小，只要有足够的磁盘空间，可以产生10G、100G、甚至是10000G的core文件，当然啦，你的程序
+有足够大才行。
+
+.. code:: bash
+
+    # 检验是否打开core文件生成
+    ulimit -c  
+
+    # core文件的大小
+    unlimited
+
+限制系统产生core文件的大小为1024000字节：
+
+.. code:: bash
+
+    # 改为限制大小1024000字节
+    ulimit -c 1024000     
+
+    ps：限制其他大小字节就在命令中修改对应的数值即可
+
+设置永久生效
+------------
+
+上面所述的方法只是在当前终端生效，当你打开了一个新的终端，它是无效的，也就是说你在其他终端运行程序时，
+即使程序崩溃了，系统也不会产生core文件，那么如果我想要设置使设置让它永久生效的办法怎么办呢？
+
+很简单，设置永久生效的办法是在 ``profile`` 文件中添加一句代码 ``ulimit -c xxxx`` 即可：
+
+.. code:: bash
+
+    # 命令，打开profile文件
+    vi /etc/profile
+
+    # 添加以下代码，数值可以是其他值
+    ulimit -c 1024000 
+
+    # 或者是
+    ulimit -c unlimited
+
+这样重启机器后就生效了。也可以使用 ``source`` 命令使之马上生效。
+
+.. code:: bash
+
+    source /etc/profile
+
+不生成核心转储文件的情况
+------------------------
+
+linux系统在多种情况下不会生成核心转储文件：
+
+-  该进程无权写入核心转储文件。在默认情况下，产生的核心转储文件名称为core或core.pid，其中pid是转储核心转储的进程的ID，并在当前进程的工作目录中创建，而如果核心转储文件创建失败或者该目录不可写，或者存在相同名称的文件且该文件是不可写的（它是目录或符号链接），那么在进程奔溃时将无法产生核心转储文件。
+
+-  已经存在一个与可用于核心转储的名称相同的（可写的，常规的）文件，但是该文件有多个硬链接。
+
+-  用于创建核心转储文件的文件系统已满，存放不下心产生的core文件
+
+-  文件系统是只读形式的。
+
+-  要在其中创建核心转储文件的目录不存在。
+
+-  系统中核心转储文件大小资源限制设置为0，或者核心转储文件大小已经超过core文件限制的上限。
+
+指定核心转储的文件名和目录
+~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+在默认情况下，系统在进程崩溃时产生的core文件是存在与该进程的程序文件相同的目录下的，并且固定命名为core，
+如此此时系统中有多个程序文件都存放在同一个目录下，而恰巧有多个进程崩溃，那么产生的core文件就会相互覆盖，
+而如果我们想要分析他们，那就没法去分析了，因此我们可以通过修改配置，让产生的核心转储文件命名包含相应的信息，
+而不会导致覆盖，也可以指定核心转储文件的路径，如何做到呢？
+
+只需在 ``/etc/sysctl.conf`` 文件中，设置kernel.core_pattern的值即可，具体操作如下：
+
+1. 使用vi编辑器打开 ``/etc/sysctl.conf`` 文件：
+
+.. code:: bash
+
+    vi /etc/sysctl.conf
+
+2. 在文件末尾添加以下代码：
+
+.. code:: bash
+
+    kernel.core_pattern = core_%e_%p 
+    kernel.core_uses_pid = 0
+
+这代表着在当前目录下产生core文件，而如果想在其他目录下产生core文件，也是可以指定对应的目录的，如：
+
+.. code:: bash
+
+    # 在/var/core目录下产生core文件
+    kernel.core_pattern = /var/core/core_%e_%p 
+    kernel.core_uses_pid = 0
+
+其中core_pattern的配置中%e, %p分别代表以下参数：
+
+-  %e：所dump的文件名
+-  %p：所dump的进程PID
+-  %c：转储文件的大小上限
+-  %g：所dump的进程的实际组ID
+-  %h：主机名
+-  %s：导致本次coredump的信号
+-  %t：转储时刻(由1970年1月1日起计的秒数)
+-  %u：所dump进程的实际用户ID
+
+需要注意的是，如果 ``/proc/sys/kernel/core_uses_pid`` 文件的内容被设置为1，即使 ``kernel.core_pattern`` 中没
+有设置%p，最后生成的core文件名仍会加上进程ID。
+
+然后可以使用以下命令，使修改结果马上生效。
+
+.. code:: bash
+
+    sudo /sbin/sysctl -p
+
+    注意，当你指定了 ``kernel.core_pattern`` 路径的时候，如果没有足够的权限，那么是不能生成core文件的。
+    可能就需要sudo权限来运行程序了。
+
+强制某个进程产生core dump
+-------------------------
+
+在日常写代码的时候，我们写了一些bug不一定会导致进程崩溃，而是可能会让进程卡在某个地方，比如发生看死锁，此时程序已经
+是不正常运行了，而我们还不知道进程的错误在哪里，如果开发的环境又没有gdb调试，那么我们可以尝试在外部让进程崩溃，
+从而产生core文件，根据linux的信号默认的处理行为， ``SIGQUIT，SIGABRT, SIGFPE和SIGSEGV`` 都可以让该进程产生core文件，
+那么我们可以手动发送这些信号让进程终止并且产生core文件，前提是进程没有处理这些信号。
+
+还有一种方法，在你认为程序可能出现卡死的地方主动调用 ``abort()`` 函数产生core文件，这个函数首先取消阻止SIGABRT信号，
+然后为调用进程引发该信号（就像调用了 ``raise()`` 函数一样），除此之外还有可以使用gdb调试工具来产生core文件。
+
+使用gdb调试core文件
+-------------------
+
+学习了那么多，现在来进行一波实战操作，让大家熟悉一下流程，在产生core文件的时候就可以自己去调试了。
+
+首先我们需要产生一个core文件对吧，那就写一个bug咯，写代码我不会，难道写bug我还不会吗，是吧，看以下代码：
+
+.. code:: c
+
+    #include <sys/types.h>
+    #include <unistd.h>
+    #include <stdio.h>
+    #include <stdlib.h>
+
+    int main(void)
+    {
+        int *a = NULL;
+
+        printf("这是一个错误\n");
+
+        // abort();
+        *a = 0x1;
+
+        printf("看看我是否能打印出来\n");
+
+        sleep(1);       // 防止进程过快退出
+
+        return 0;
+    }
+
+代码定义了一个指向NULL的指针，然后对指针操作，那肯定是内存越界了，进程崩溃后会产生一个core文件，
+这不就可以调试了吗!
+
+代码的路径是在： ``embed_linux_tutorial/documentation/linux_debug`` ，先make编译代码，然后直接运行：
+
+.. code:: bash
+
+    ➜  core_dump git: ✗ make 
+    gcc -o core_dump.o -c -g -Werror -I. -Iinclude -static core_dump.c -g -MD -MF .core_dump.o.d
+    gcc -o targets core_dump.o -g -Werror -I. -Iinclude -static
+
+    ➜  core_dump git: ✗ ls
+    core_dump.c  core_dump.o  Makefile  targets
+
+    ➜  core_dump git: ✗ ./targets 
+    这是一个错误
+    [1]    19176 segmentation fault (core dumped)  ./targets
+
+    ➜  core_dump git: ✗ ls
+    core_dump.c  core_dump.o  core_targets_19176  Makefile  targets
+
+在运行时可以看到输出了一个错误， ``[1]    19176 segmentation fault (core dumped)  ./targets`` ，告诉我们
+产生了一个core文件，那么在当前目录下就产生了 ``core_targets_19176`` 文件，那么怎么来调试呢，通过以下命令即可：
+
+.. code:: bash
+
+    ➜  core_dump git:(dev_jie) ✗ gdb targets core_targets_19176 
+
+    GNU gdb (Ubuntu 8.1-0ubuntu3.2) 8.1.0.20180409-git
+    Copyright (C) 2018 Free Software Foundation, Inc.
+    License GPLv3+: GNU GPL version 3 or later <http://gnu.org/licenses/gpl.html>
+    This is free software: you are free to change and redistribute it.
+    There is NO WARRANTY, to the extent permitted by law.  Type "show copying"
+    and "show warranty" for details.
+    This GDB was configured as "x86_64-linux-gnu".
+    Type "show configuration" for configuration details.
+    For bug reporting instructions, please see:
+    <http://www.gnu.org/software/gdb/bugs/>.
+    Find the GDB manual and other documentation resources online at:
+    <http://www.gnu.org/software/gdb/documentation/>.
+    For help, type "help".
+    Type "apropos word" to search for commands related to "word"...
+    Reading symbols from targets...done.
+    [New LWP 19176]
+    Core was generated by `./targets'.
+    Program terminated with signal SIGSEGV, Segmentation fault.
+    #0  0x0000000000400b6d in main () at core_dump.c:13
+    ---Type <return> to continue, or q <return> to quit---
+    13          *a = 0x1;
+    (gdb) 
+
+命令格式如下：
+
+.. code:: bash
+
+    gdb [程序文件] [core文件]
+
+在gdb调试的底部，我们可以看到错误的位置就是第13行，对空指针操作的位置，gdb工具直接
+定位出来错误在哪，还不需要我们一步步调试。
+
+.. code:: bash
+
+    Program terminated with signal SIGSEGV, Segmentation fault.
+    #0  0x0000000000400b6d in main () at core_dump.c:13
+    13          *a = 0x1;
+
+如果我们想一步步调试，那么可以在gdb中打断点(b)，然后运行(r)，或者一步步(s)调试，具体见：
+
+.. code:: bash
+
+    Program terminated with signal SIGSEGV, Segmentation fault.
+    #0  0x0000000000400b6d in main () at core_dump.c:13
+    13          *a = 0x1;
+
+    # 下面是gdb调试的步骤：
+    # 首先在main函数中打一个断点
+    (gdb) b main
+    Breakpoint 1 at 0x400b55: file core_dump.c, line 8.
+
+    # 运行到断点处
+    (gdb) r
+    Starting program: /home/jiejie/embed_linux_tutorial/base_code/linux_debug/core_dump/targets 
+
+    Breakpoint 1, main () at core_dump.c:8
+    8           int *a = NULL;
+
+    # 接下来单步运行
+    (gdb) s
+    10          printf("这是一个错误\n");
+    (gdb) s
+    这是一个错误
+    13          *a = 0x1;
+
+    # 运行到第13行这里就出现错误了
+    (gdb) s
+
+    Program received signal SIGSEGV, Segmentation fault.
+    0x0000000000400b6d in main () at core_dump.c:13
+    13          *a = 0x1;
+
+    # 退出gdb调试
+    (gdb) quit
+    A debugging session is active.
+
+            Inferior 1 [process 19261] will be killed.
+
+    Quit anyway? (y or n) y
+
+    本章完，大家在本章练习中可以随意写bug然后调试，都是可以的~
diff --git a/documentation/linux_debug/gdb_use.rst b/documentation/linux_debug/gdb_use.rst
new file mode 100644
index 0000000000000000000000000000000000000000..8bf4c2131dc0092c125224a1d9c24bd3e13dbe69
--- /dev/null
+++ b/documentation/linux_debug/gdb_use.rst
@@ -0,0 +1,234 @@
+.. vim: syntax=rst
+
+GDB调试利器
+--------------
+
+GDB简介
+===============
+
+在单片机开发中，KEIL、IAR、ADS1.2等集成开发环境下的调试工具对程序开发有很大的帮助，
+尤其是出现各种疑难杂症的bug时，往往只能通过单步调试、堆栈查询、CPU寄存器查询、
+甚至是反汇编来定位问题。同样的，在嵌入式Linux的开发环境下，也有能够实现类似功能的调试器，那就是GDB（GNU debugger）。
+它是一个由GNU开源组织发布的，UNIX/LINUX操作系统下的、基于命令行的、功能强大的调试工具，
+是嵌入式linux开发人员必不可少的工具。
+
+GDB的使用
+===============
+
+安装gdb工具
+~~~~~~~~~~~~~~~~~
+
+在开发板中执行gdb安装命令:
+
+.. code-block:: sh
+   :linenos:
+
+   sudo apt install gdb -y
+
+如下图:
+
+.. image:: media/gdb_install.png
+   :align: center
+   :alt: 未找到图片
+
+添加程序调试信息
+~~~~~~~~~~~~~~~~
+
+本章节示例代码在:embed_linux_tutorial/base_code/linux_debug/gdb_use/hello.c
+
+把代码源文件通过NFS网络文件系统拷贝到开发板后，使用gcc进行编译，-g参数表示添加调试信息。
+
+.. code-block:: sh
+   :linenos:
+
+   gcc -g hello.c -o hello
+
+如下图:
+
+.. image:: media/gdb-g.png
+   :align: center
+   :alt: 未找到图片
+
+gdb启动应用程序
+~~~~~~~~~~~~~~~~~~
+
+开发板输入运行gdb开始调试命令：
+
+.. code-block:: sh
+   :linenos:
+
+   gdb hello
+
+如下图:
+
+.. image:: media/gdb_hello.png
+   :align: center
+   :alt: 未找到图片
+
+加-q参数，启动时不会打印gdb的默认信息，界面清爽干净些。
+
+如下图:
+
+.. image:: media/gdb_q.png
+   :align: center
+   :alt: 未找到图片
+
+查看源码
+~~~~~~~~~~
+
+输入list(简写l)命令可以查看程序源代码，默认显示10行，通过回车键不断查看剩余代码。
+
+如下图:
+
+.. image:: media/gdb_list.png
+   :align: center
+   :alt: 未找到图片
+
+运行程序
+~~~~~~~~~~
+
+执行run(简写r)命令用于运行代码，在程序结束或者遇到断点处停下。
+
+如下图:
+
+.. image:: media/gdb_run.png
+   :align: center
+   :alt: 未找到图片
+
+设置断点
+~~~~~~~~~
+
+运行break(简写b)命令可以在指定行设置一个断点，断点调试是程序调试里面使用频率最高的技巧，务必熟练掌握。
+
+设置方法为"b"命令后加上相应的行号，在这里以在第6、7行设置断点为例：
+
+.. image:: media/gdb_b.png
+   :align: center
+   :alt: 未找到图片
+
+查看断点信息
+~~~~~~~~~~~~~~~
+
+设置好断点后，执行以下命令查看断点信息：
+
+.. code-block:: sh
+   :linenos:
+
+   info b
+
+如下图:
+
+.. image:: media/gdb_info.png
+   :align: center
+   :alt: 未找到图片
+
+含义解释:
+
+- NUM:断点编号  
+- Disp：断点执行一次之后是否还有效（keep:有效 dis:无效）
+- Enb:当前断点是否有效（y:有效 n:无效）     
+- Address：内存地址
+
+单步调试
+~~~~~~~~~
+
+- continue(简写c):继续执行，到下一个断点处(或运行结束)。
+- next(简写n):单步执行，跳过子函数。
+- strp(简写s)：单步执行，进入子函数。
+
+示例:在第6行设置来断点后，先输入r指令让程序运行到断点处，然后执行n指令进行单步调试，
+可以看到第6行的打印信息在单步执行后，输出"hello,world"打印信息。
+如下图:
+
+.. image:: media/gdb_next.png
+   :align: center
+   :alt: 未找到图片
+
+示例:在第6行设置来断点后，先输入r指令让程序运行到断点处，然后执行s指令进行单步调试，
+可以看到程序已经进入到printf函数的内部中。继续执行c指令，可以让程序继续运行。
+
+如下图:
+
+.. image:: media/gdb_step.png
+   :align: center
+   :alt: 未找到图片
+
+查看变量
+~~~~~~~~~
+
+使用print(简写p)指令可以查看变量的值，用法为print+变量名。
+
+示例:在程序的第8行处设置断点，看i的值在for循环两次执行过程中的变化。
+
+如下图:
+
+.. image:: media/gdb_print.png
+   :align: center
+   :alt: 未找到图片
+
+清除断点
+~~~~~~~~~
+
+使用clear指令可以删除某一行对应的断点，用法为clear+行号。
+
+运行至函数结束
+~~~~~~~~~
+
+使用finish指令可以让程序运行到函数结束位置。
+
+显示源代码窗口
+~~~~~~~~~~~~~~~~~
+
+程序运行以后，使用"layout src"命令可以显示源代码窗口,当前执行代码会高亮标志，单步调试非常方便。
+
+如下图:
+
+.. image:: media/gdb_layout.png
+   :align: center
+   :alt: 未找到图片
+
+退出gdb
+~~~~~~~~~~~~~~~
+
+执行quit(简写q)会退出gdb调试，返回到控制台终端。
+
+CGDB的使用
+===============
+
+cgbd是gdb的终端界面增强版，相比windows下的visual studio而言，
+它的功能显得十分轻量级而没有太多繁杂，它有上下两栏窗口，上栏的窗口支持vi编辑器的语法，
+可以方便的使用它来进行字符串定位等功能。在gdb下使用"layout src"时，界面往往容易花屏，
+而cgbd更加的稳定可靠。
+
+安装cgdb工具
+~~~~~~~~~~~~~~~~~
+
+在开发板中执行cgdb安装命令:
+
+.. code-block:: sh
+   :linenos:
+
+   sudo apt install cgdb -y
+
+如下图:
+
+.. image:: media/cgdb_install.png
+   :align: center
+   :alt: 未找到图片
+
+cgdb启动应用程序
+~~~~~~~~~~~~~~~~~~
+
+开发板输入运行gdb开始调试命令：
+
+.. code-block:: sh
+   :linenos:
+
+   gdb hello
+
+.. image:: media/cgdb_hello.png
+   :align: center
+   :alt: 未找到图片
+
+可以看到，cgbd默认启动显示源文件界面，而且颜色区分关键字和变量类型，十分美观。
+它下面一栏是gdb窗口，可以直接使用上面介绍的gdb各种指令进行调试。
diff --git a/documentation/linux_debug/index.rst b/documentation/linux_debug/index.rst
new file mode 100644
index 0000000000000000000000000000000000000000..34897c2883bb4c758d22112148a7ab4eb6d1fa4b
--- /dev/null
+++ b/documentation/linux_debug/index.rst
@@ -0,0 +1,13 @@
+.. vim: syntax=rst
+
+第六部分 Linux内核调试
+==================================
+
+
+.. .. toctree::
+..    :maxdepth: 1
+..    :numbered:
+
+..    core_dump
+..    backtrace
+..    strace
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diff --git a/documentation/linux_debug/strace.rst b/documentation/linux_debug/strace.rst
new file mode 100644
index 0000000000000000000000000000000000000000..e87d0514644a04c835e441d59b90aed2600753d4
--- /dev/null
+++ b/documentation/linux_debug/strace.rst
@@ -0,0 +1,266 @@
+跟踪系统调用——strace
+====================
+
+在前面的文章我们了解了gdb调试工具，今天我们来了解一下新的调试工具，它虽然不能与
+gdb一样跟踪程序的运行，调试程序运行时的环境，如查看栈的内容与函数内部的变量等信
+息，但它依旧是一个非常强大的工具，我们一般用来跟踪任何程序的系统调用，没错，是任何
+程序，比如Linux系统中自带的命令，或者是其他不开源的可执行文件，strace都可以跟踪他
+们的系统调用，下面我们就来简单了解一下strace这个工具。
+
+strace简介
+----------
+
+strace命令是一个集诊断、调试、统计与一体的工具，我们用它来监控用户空间进程和内核
+的交互，比如对应用程序的系统调用、信号传递与进程状态变更等进行跟踪与分析，以达到解
+决问题或者是了解应用工作过程的目的。这个简单而又强大的工具几乎在所有的Linux操作系
+统上都可用，足以见证其强大之处。
+
+我们知道Linux的前身是Unix，Unix的设计由大量的函数调用组成，比如包括一些简单的操
+作，打开一个文件，读写文件，关闭文件等，这写就是系统调用，而Linux也是如此，拥有大
+量系统提供的函数接口。在Linux世界，进程不能直接访问硬件设备，当进程需要访问硬件设
+备（比如读取磁盘文件，接收网络数据等等）时，必须由用户态模式切换至内核态模式，通过
+系统调用访问硬件设备。所有的Linux应用程序都是通过调用操作系统提供的函数来完成它们
+的任务，这也是我们常说的应用编程，我们不需要去了解操作系统到底在干嘛，我们只需要知
+道通过这些系统调用就可以完成我们的操作，比如向串口写入数据，那么就将串口设备打开，
+然后写入数据，最后关闭串口设备等。
+
+那么如果程序出现问题，我们不知道问题出现在哪里，而strace工具就派上用场了，使用
+strace工具，我们可以清楚地看到这些系统调用的过程、使用的参数、返回值与执行消耗的
+时间等，还可以了解它们与操作系统之间的底层交互。
+
+    ps：strace底层使用内核的ptrace特性来实现其功能，有兴趣的同学可以去了解一下ptrace。
+
+strace命令
+----------
+
+strace是系统自带的命令，在绝大部分的linux系统中可以用它来调试应用程序，只需我们运
+行一下strace命令就可以跟踪某个应用程序，在应用程序运行结束后它也会自动结束跟踪，
+在命令执行的过程中，strace会记录和解析命令进程的所有系统调用以及这个进程所接收到
+的所有的信号值，通过这些跟踪到的信息，你可以知道程序执行了那些系统调用，以何种顺序
+执行，收到了什么信号等。
+
+在linux下运行 ``strace -h`` 命令就可以看到strace命令用法的介绍，还有很多参数，由于太
+多就不一一列举出来。
+
+.. code:: bash
+
+    ➜  ~ strace -h
+
+    usage: strace [-CdffhiqrtttTvVwxxy] [-I n] [-e expr]...
+                  [-a column] [-o file] [-s strsize] [-P path]...
+                  -p pid... / [-D] [-E var=val]... [-u username] PROG [ARGS]
+       or: strace -c[dfw] [-I n] [-e expr]... [-O overhead] [-S sortby]
+                  -p pid... / [-D] [-E var=val]... [-u username] PROG [ARGS]
+
+**strace命令输出的格式参数：**
+
+    ps：这些参数挑一些常用的记就好了，因为如果不记得运行 ``strace -h`` 命令就知道这些
+    参数的作用了，而以下的参数描述都是根据strace帮助文档整理的。
+
+-  [-o file]：将strace的输出写入指定的文件。
+-  [-s strsize]：将打印字符串的长度限制为strsize个字符（默认值为32）。
+-  -d：输出strace关于标准错误的调试信息。
+-  -r：打印出相对时间关于每一个系统调用。
+-  -f：跟踪由fork()调用所产生的子进程。
+-  -t：在输出中的每一行前加上时间信息。
+-  -tt：在输出中的每一行前加上时间信息（微秒级）。
+-  -T：打印在每个系统调用中花费的时间。
+-  -r：打印相对时间戳。
+-  -x：以十六进制打印非ascii字符串。
+-  -xx：以十六进制打印所有字符串。
+-  -y：打印与文件描述符参数关联的路径。
+-  -yy：打印与套接字文件描述符关联的协议特定信息。
+
+**strace命令统计参数**
+
+-  -c：统计每一系统调用的所执行的时间，次数和出错的次数等。
+-  -C：像-c一样，也可以打印常规输出。
+-  -w：汇总系统调用延迟（默认为系统时间）
+-  [-O overhead]：设置将系统调用跟踪到OVERUSE的开销
+-  [-S sortby]：按以下顺序对系统调用计数：时间，调用，名称等
+
+**strace命令过滤参数**
+
+-  [-e
+   expr]...：指定一个表达式，用来控制如何跟踪。格式如下： ``[qualifier=][!]value1[,value2]...`` 。
+
+    描述说明： ``qualifier`` 只能是
+    ``trace、abbrev、verbose、raw、signal、read、write`` 其中之一，value是用来限定的符号或数字，默认的
+    qualifier是trace。感叹号是否定符号，例如: ``-e open`` 等价于
+    ``-e trace=open`` ，表示只跟踪 ``open`` 调用；而 ``-etrace!=open``
+    表示跟踪除了open以外的其他调用，还有两个特殊的符号 ``all`` 和
+    ``none`` ，它们分别代表所有选项与没有选项。
+
+**strace命令过滤的例子：**
+
+-  ``-e trace=set``
+   只跟踪指定的系统调用，例如: ``-e trace=open,close,rean,write`` 表示只跟踪这四个系统调用，默认的为 ``set=all`` 。
+-  ``-e trace=file`` 只跟踪有关文件操作的系统调用。
+-  ``-e trace=process`` 只跟踪有关进程控制的系统调用。
+-  ``-e trace=network`` 跟踪与网络有关的所有系统调用。
+-  ``-e strace=signal`` 跟踪所有与信号有关的系统调用。
+-  ``-e trace=ipc`` 跟踪所有与进程通讯有关的系统调用。
+-  ``-e raw=set`` 将指定的系统调用的参数以十六进制显示。
+-  ``-e signal=se`` t
+   指定跟踪的系统信号。默认为all（所有信号）。如 ``signal=!SIGIO`` 或者 ``signal=!io`` ，表示不跟踪 ``SIGIO`` 信号。
+-  ``-e read=set`` 输出从指定文件中读出的数据。
+-  ``-e write=set`` 输出写入到指定文件中的数据。
+
+strace实战
+----------
+
+跟踪ls命令
+~~~~~~~~~~
+
+学习了那么多基本的知识，大家是不是迫不及待想试一下了？我们就跟踪一下基本的ls命令吧，它在我们linux系统
+中应该是用得最多的命令了，我们可以看看在敲下ls命令的时候，系统做了什么东西：
+
+    友情提示一下，因为ls命令是列出当前路径下的所有文件，而strace命令会默认跟踪所有的系统调用，如果当前路径下有很多文件的话，可能会输出非常非常多的内容，不利于观察，我们可以新建一个测试的空目录，在空目录下跟踪ls命令到底做了什么事情。
+
+.. code:: bash
+
+    # 创建空的测试目录并进入
+    ➜  ~ mkdir mytest
+    ➜  ~ cd mytest 
+
+    # 跟踪ls命令
+    ➜  mytest strace ls   
+
+    # 输出内容
+    execve("/bin/ls", ["ls"], 0x7fffe987f830 /* 34 vars */) = 0
+    brk(NULL)                               = 0x55769774d000
+    access("/etc/ld.so.nohwcap", F_OK)      = -1 ENOENT (No such file or directory)
+    access("/etc/ld.so.preload", R_OK)      = -1 ENOENT (No such file or directory)
+    openat(AT_FDCWD, "/etc/ld.so.cache", O_RDONLY|O_CLOEXEC) = 3
+    fstat(3, {st_mode=S_IFREG|0644, st_size=95106, ...}) = 0
+    mmap(NULL, 95106, PROT_READ, MAP_PRIVATE, 3, 0) = 0x7efd08f12000
+    close(3)                                = 0
+    access("/etc/ld.so.nohwcap", F_OK)      = -1 ENOENT (No such file or directory)
+    openat(AT_FDCWD, "/lib/x86_64-linux-gnu/libselinux.so.1", O_RDONLY|O_CLOEXEC) = 3
+    read(3, "\177ELF\2\1\1\0\0\0\0\0\0\0\0\0\3\0>\0\1\0\0\0\20b\0\0\0\0\0\0"..., 832) = 832
+    fstat(3, {st_mode=S_IFREG|0644, st_size=154832, ...}) = 0
+    mmap(NULL, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_ANONYMOUS, -1, 0) = 0x7efd08f10000
+    mmap(NULL, 2259152, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3, 0) = 0x7efd08adb000
+    mprotect(0x7efd08b00000, 2093056, PROT_NONE) = 0
+    mmap(0x7efd08cff000, 8192, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x24000) = 0x7efd08cff000
+    mmap(0x7efd08d01000, 6352, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_FIXED|MAP_ANONYMOUS, -1, 0) = 0x7efd08d01000
+
+    # 省略n行
+
+    close(3)                                = 0
+    close(1)                                = 0
+    close(2)                                = 0
+    exit_group(0)                           = ?
+    +++ exited with 0 +++
+
+是不是没想到，这么简单的一个ls命令，内核居然敢了这么多事情，这还是省略了绝大部分的输出，大家可以自己参考终端的输出内容。
+
+跟踪并统计ls命令
+~~~~~~~~~~~~~~~~
+
+或者我们可以统计一下ls命令调用了什么函数，可以使用以下命令：
+
+.. code:: bash
+
+    ➜  mytest strace -c ls           
+
+    % time     seconds  usecs/call     calls    errors syscall
+    ------ ----------- ----------- --------- --------- ----------------
+      0.00    0.000000           0         7           read
+      0.00    0.000000           0        11           close
+      0.00    0.000000           0         9           fstat
+      0.00    0.000000           0        17           mmap
+      0.00    0.000000           0        12           mprotect
+      0.00    0.000000           0         1           munmap
+      0.00    0.000000           0         3           brk
+      0.00    0.000000           0         2           rt_sigaction
+      0.00    0.000000           0         1           rt_sigprocmask
+      0.00    0.000000           0         2           ioctl
+      0.00    0.000000           0         8         8 access
+      0.00    0.000000           0         1           execve
+      0.00    0.000000           0         2           getdents
+      0.00    0.000000           0         2         2 statfs
+      0.00    0.000000           0         1           arch_prctl
+      0.00    0.000000           0         1           set_tid_address
+      0.00    0.000000           0         9           openat
+      0.00    0.000000           0         1           set_robust_list
+      0.00    0.000000           0         1           prlimit64
+    ------ ----------- ----------- --------- --------- ----------------
+    100.00    0.000000                    91        10 total
+
+这里的输出很清楚的告诉我们调用了那些系统函数，调用次数多少，消耗了多少时间等等，这些信息对我们分析一个程序来说是非常有用的。
+
+重定向输出信息
+~~~~~~~~~~~~~~
+
+strace命令在终端输出的信息太多了，我们想要将它重定向输出某个文件中（使用 ``[-o filename]`` 参数），
+然后对文件进行分析，这样子的操作就比在终端上分析要好得多，但是需要注意的是，因为输出的信息很多，
+生成的日志文件可能会很大，所以在日常使用中要注意设置过滤，不需要完全跟踪所有的内容。
+
+重定向输出信息命令如下：
+
+.. code:: bash
+
+    ➜  mytest strace -o ls.log ls 
+    ls.log
+
+    ➜  mytest strace -c -o ls.log ls      
+    ls.log
+
+生成ls.log文件位于当前路径下，可以使用cat命令打开。
+
+    ps：-o filename
+    参数中的文件名filename可以随意命名，无需后缀也是可以的，毕竟Linux一切皆文件。
+
+跟踪自己的代码
+~~~~~~~~~~~~~~
+
+我们可以使用核心转储章节的代码，代码位置： ``embed_linux_tutorial/base_code/linux_debug/core_dump`` ，
+编译后使用strace命令去跟踪它，看看遇到错误是怎么样的情况。
+
+操作如下：
+
+.. code:: bash
+
+    # 编译
+    ➜  core_dump git:(dev_jie) ✗ make 
+    gcc -o core_dump.o -c -g -Werror -I. -Iinclude -static core_dump.c -g -MD -MF .core_dump.o.d
+    gcc -o targets core_dump.o -g -Werror -I. -Iinclude -static
+
+    # 跟踪
+    ➜  core_dump git:(dev_jie) ✗ strace ./targets 
+    execve("./targets", ["./targets"], 0x7ffe4c007260 /* 34 vars */) = 0
+    brk(NULL)                               = 0x1d57000
+    brk(0x1d581c0)                          = 0x1d581c0
+    arch_prctl(ARCH_SET_FS, 0x1d57880)      = 0
+    uname({sysname="Linux", nodename="embedfire_dev", ...}) = 0
+    readlink("/proc/self/exe", "/home/xxxxx/embed_linux_tutoria"..., 4096) = 73
+    brk(0x1d791c0)                          = 0x1d791c0
+    brk(0x1d7a000)                          = 0x1d7a000
+    access("/etc/ld.so.nohwcap", F_OK)      = -1 ENOENT (No such file or directory)
+    fstat(1, {st_mode=S_IFCHR|0620, st_rdev=makedev(136, 0), ...}) = 0
+    write(1, "\350\277\231\346\230\257\344\270\200\344\270\252\351\224\231\350\257\257\n", 19这是一个错误
+    ) = 19
+    --- SIGSEGV {si_signo=SIGSEGV, si_code=SEGV_MAPERR, si_addr=NULL} ---
+    +++ killed by SIGSEGV +++
+    [1]    12576 segmentation fault  strace ./targets
+
+从日志信息可以看出，它是被SIGSEGV终止的，并且产生了段错误 ``segmentation fault`` 。除此之外，
+代码的运行调用了一些系统调用，比如调用execve()函数创建了一个新的进程 ``./targets`` 、查看了当前系统的信息，
+系统名，主机名、打开文件描述符编号为1的输出文件，并且向该文件描述符中写入打印的内容等。
+
+我们也能使用 ``-T`` 参数查看每个系统调用的时间（在输出的最右边 ``<>`` 的内容就是时间），当然大家可以用 ``-t -tt`` 等参数来测试一下：
+
+.. code:: bash
+
+    ➜  core_dump git:(dev_jie) ✗ strace -T ./targets
+
+    execve("./targets", ["./targets"], 0x7ffc6c9cda78 /* 34 vars */) = 0 <0.000119>
+    brk(NULL)                               = 0x1d65000 <0.000006>
+    brk(0x1d661c0)                          = 0x1d661c0 <0.000007>
+    arch_prctl(ARCH_SET_FS, 0x1d65880)      = 0 <0.000005>
+    uname({sysname="Linux", nodename="embedfire_dev", ...}) = 0 <0.000005>
+    readlink("/proc/self/exe", "/home/jiejie/embed_linux_tutoria"..., 4096) = 73 <0.000023>
+    # 省略后续输出
+
+本章跟踪进程的讲解就到此结束，更多实战的内容大家可以自行去尝试。
diff --git a/documentation/linux_driver/character_device.rst b/documentation/linux_driver/character_device.rst
index 6b3f7cdeb0c582a53a421597be0c2a58a8e50495..3dabb831587135ad38cfa60c71afc3bd2cd2afb7 100644
--- a/documentation/linux_driver/character_device.rst
+++ b/documentation/linux_driver/character_device.rst
@@ -1,17 +1,22 @@
 .. vim: syntax=rst
 
+
 字符设备驱动
-------
+------------------------------------
 
 本章节内容处于开发笔记状态，还待整理至最终版的教程。
 
+
 本章节内容处于开发笔记状态，还待整理至最终版的教程。
 
 本章，我们将学习如何编写一个字符设备驱动：
 
 1. 介绍Linux设备分类，了解什么是字符设备、块设备以及网络设备；
 
-2. 我们经常说“一切皆文件”，对于硬件设备，也是如此。那当我们打开设备文件时，到底做了什么东西。为什么我们对该文件进行读写可以操作我们的硬件呢。刚开始学习本节，可能会很懵圈。但是，当你学习完整章的内容之后，再回过头来看本节的内容，可以加深你对字符设备驱动的理解。
+2. 我们经常说"一切皆文件"，对于硬件设备，也是如此。那当我们打开
+   设备文件时，到底做了什么东西。为什么我们对该文件进行读写可以操作
+   我们的硬件呢。刚开始学习本节，可能会很懵圈。但是，当你学习完整章的
+   内容之后，再回过头来看本节的内容，可以加深你对字符设备驱动的理解。
 
 3. 介绍字符设备驱动相关的数据结构
 
@@ -20,318 +25,284 @@
 5. 自己写一个字符设备驱动
 
 Linux设备
-~~~~~~~
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
 Linux中，根据设备的类型可以分为三类：字符设备、块设备和网络设备。
 
 字符设备：应用程序按字节/字符来读写数据，通常不支持随机存取。我们常用的键盘、串口都是字符设备。
 
-块设备：应用程序可以随机访问设备数据。典型的块设备有硬盘、SD卡、闪存等，应用程序可以寻址磁盘上的任何位置，并由此读取数据。此外，数据的读写只能以块的倍数进行。
+块设备：应用程序可以随机访问设备数据。典型的块设备有硬盘、SD卡、闪存等，应用程序
+可以寻址磁盘上的任何位置，并由此读取数据。此外，数据的读写只能以块的倍数进行。
 
 网络设备是一种特殊设备，它并不存在于/dev下面，主要用于网络数据的收发。
 
 open函数到底做了什么
-~~~~~~~~~~~~
-
-在学习字符设备驱动之前，我们一起了解一下，使用open函数打开设备文件，到底做了些什么工作？图 57‑1中列出了open函数执行的大致过程。
-
-|charac002|
-
-图 57‑1执行流程
-
-设备文件通常在开机启动时自动创建的，不过，我们仍然可以使用命令mknod来创建一个新的设备文件，命令的基本语法如下：
-
-mknod 设备名 设备类型 主设备号 次设备号
-
-当我们使用上述命令，创建了一个字符设备文件时，实际上就是创建了一个设备节点inode结构体，并且将该设备的设备编号记录在成员i_rdev，将成员f_op指针指向了def_chr_fops结构体。这就是mknod负责的工作内容，具体代码见代码清单 57‑1。
-
-代码清单 57‑1mknod调用关系
-
-1 static struct inode \*shmem_get_inode(struct super_block \*sb, const struct inode \*dir,
-
-2 umode_t mode, dev_t dev, unsigned long flags)
-
-3 {
-
-4 inode = new_inode(sb);
-
-5 if (inode) {
-
-6 ......
-
-7 switch (mode & S_IFMT) {
-
-8 default:
-
-9 inode->i_op = &shmem_special_inode_operations;
-
-10 init_special_inode(inode, mode, dev);
-
-11 break;
-
-12 ......
-
-13 }
-
-14 } else
-
-15 shmem_free_inode(sb);
-
-16 return inode;
-
-17 }
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
-18 void init_special_inode(struct inode \*inode, umode_t mode, dev_t rdev)
+在学习字符设备驱动之前，我们一起了解一下，使用open函数打开设备文件，到底做
+了些什么工作？下图中列出了open函数执行的大致过程。
 
-19 {
+.. image:: media/charac002.jpg
+   :align: center
+   :alt: 未找到图片02
 
-20 inode->i_mode = mode;
 
-21 if (S_ISCHR(mode)) {
 
-22 inode->i_fop = &def_chr_fops;
+设备文件通常在开机启动时自动创建的，不过，我们仍然
+可以使用命令mknod来创建一个新的设备文件，命令的基本语法如下：
 
-23 inode->i_rdev = rdev;
-
-24 }
-
-25 ....
-
-26 }
-
-命令mknod最终会调用init_special_inode函数，由于我们创建的是字符设备，因此，会执行第22~23行的代码。这样就完成了图 57‑1处的内容。
-
-我们使用的open函数在内核中对应的是sys_open函数，sys_open函数又会调用do_sys_open函数。在do_sys_open函数中，首先调用函数get_unused_fd_flags来获取一个未被使用的文件描述符fd，该文件描述符就是我们最终通过open函数得到的值。紧接着，又调用了
-do_filp_open函数，该函数通过调用函数get_empty_filp得到一个新的file结构体，之后的代码做了许多复杂的工作，如解析文件路径，查找该文件的文件节点inode等，直接来到了函数do_dentry_open函数，见代码清单 57‑2。
-
-代码清单 57‑2 do_dentry_open函数（位于内核源码/fs/open.c文件）
-
-1 static int do_dentry_open(struct file \*f,
-
-2 struct inode \*inode,
-
-3 int (*open)(struct inode \*, struct file \*),
-
-4 const struct cred \*cred)
-
-5 {
-
-6 ……
-
-7 f->f_op = fops_get(inode->i_fop);
-
-8 ……
-
-9
-
-10 if (!open)
-
-11 open = f->f_op->open;
-
-12 if (open) {
-
-13 error = open(inode, f);
-
-14 if (error)
-
-15 goto cleanup_all;
-
-16 }
-
-17 ……
-
-18 }
+mknod 设备名 设备类型 主设备号 次设备号
 
-代码清单 57‑2中的第7行使用fops_get函数来获取该文件节点inode的成员变量i_fop，还记得图 57‑1中的处吗？我们使用mknod创建字符设备文件时，将def_chr_fops结构体赋值给了该设备文件inode的i_fop成员。到了这里，我们新建的file结构体的成员f_op就指向了
+当我们使用上述命令，创建了一个字符设备文件时，实际上
+就是创建了一个设备节点inode结构体，并且将该设备的设备编号记录在
+成员i_rdev，将成员f_op指针指向了def_chr_fops结构体。这就是mknod负责
+的工作内容，具体代码见如下。
+
+
+
+
+
+.. code-block:: c
+   :caption: mknod调用关系
+   :linenos:
+
+   static struct inode *shmem_get_inode(struct super_block *sb, const struct inode *dir,
+   umode_t mode, dev_t dev, unsigned long flags)
+   {
+   inode = new_inode(sb);
+   if (inode) {
+   ......
+   switch (mode & S_IFMT) {
+   default:
+   inode->i_op = &shmem_special_inode_operations;
+    init_special_inode(inode, mode, dev);
+    break;
+    ......
+    }
+    } else
+    shmem_free_inode(sb);
+    return inode;
+    }
+    void init_special_inode(struct inode *inode, umode_t mode, dev_t rdev)
+    {
+    inode->i_mode = mode;
+    if (S_ISCHR(mode)) {
+    inode->i_fop = &def_chr_fops;
+    inode->i_rdev = rdev;
+    }
+    ....
+    }
+
+命令mknod最终会调用init_special_inode函数，由于我们创建的是
+字符设备，因此，会执行第22~23行的代码。这样就完成了上图的内容。
+
+我们使用的open函数在内核中对应的是sys_open函数，sys_open函数
+又会调用do_sys_open函数。在do_sys_open函数中，首先调用函
+数get_unused_fd_flags来获取一个未被使用的文件描述符fd，该文件描述
+符就是我们最终通过open函数得到的值。紧接着，又调用了
+do_filp_open函数，该函数通过调用函数get_empty_filp得到一个新
+的file结构体，之后的代码做了许多复杂的工作，如解析文件路径，查找该文
+件的文件节点inode等，直接来到了函数do_dentry_open函数，如下所示。
+
+
+
+
+.. code-block:: c
+   :caption: do_dentry_open函数（位于内核源码/fs/open.c文件）
+   :linenos:
+
+   static int do_dentry_open(struct file *f,
+   struct inode *inode,
+   int (*open)(struct inode *, struct file *),
+   const struct cred *cred)
+   {
+   ……
+   f->f_op = fops_get(inode->i_fop);
+   ……
+    if (!open)
+    open = f->f_op->open;
+    if (open) {
+    error = open(inode, f);
+    if (error)
+    goto cleanup_all;
+    }
+    ……
+    }
+
+以上代码中的第7行使用fops_get函数来获取该文件节点inode的成
+员变量i_fop，在上图中我们使用mknod创建字符设备
+文件时，将def_chr_fops结构体赋值给了该设备文件inode的i_fop成员。到
+了这里，我们新建的file结构体的成员f_op就指向了
 def_chr_fops。
 
-代码清单 57‑3 def_chr_fops结构体（位于内核源码/fs/char_dev.c文件）
-
-1 const struct file_operations def_chr_fops = {
-
-2 .open = chrdev_open,
-
-3 .llseek = noop_llseek,
-
-4 };
-
-最终，会执行def_chr_fops中的open函数，也就是chrdev_open函数，可以理解为一个字符设备的通用初始化函数，根据字符设备的设备号，找到相应的字符设备，从而得到操作该设备的方法，代码实现见代码清单 57‑5。
-
-|charac003|
-
-代码清单 57‑4 图解chrdev_open函数
-
-代码清单 57‑5 chrdev_open函数（位于内核源码/fs/char_dev.c文件）
-
-1 static int chrdev_open(struct inode \*inode, struct file \*filp)
-
-2 {
-
-3 const struct file_operations \*fops;
-
-4 struct cdev \*p;
-
-5 struct cdev \*new = NULL;
-
-6 int ret = 0;
-
-7
-
-8 spin_lock(&cdev_lock);
-
-9 p = inode->i_cdev;
-
-10 if (!p) {
-
-11 struct kobject \*kobj;
-
-12 int idx;
-
-13 spin_unlock(&cdev_lock);
-
-14 kobj = kobj_lookup(cdev_map, inode->i_rdev, &idx);
-
-15 if (!kobj)
-
-16 return -ENXIO;
-
-17 new = container_of(kobj, struct cdev, kobj);
-
-18 spin_lock(&cdev_lock);
-
-19 /\* Check i_cdev again in case somebody beat us to it while
-
-20 we dropped the lock.
-\*/
-
-21 p = inode->i_cdev;
-
-22 if (!p) {
-
-23 inode->i_cdev = p = new;
-
-24 list_add(&inode->i_devices, &p->list);
-
-25 new = NULL;
-
-26 } else if (!cdev_get(p))
-
-27 ret = -ENXIO;
-
-28 } else if (!cdev_get(p))
-
-29 ret = -ENXIO;
-
-30 spin_unlock(&cdev_lock);
-
-31 cdev_put(new);
-
-32 if (ret)
-
-33 return ret;
-
-34
-
-35 ret = -ENXIO;
-
-36 fops = fops_get(p->ops);
-
-37 if (!fops)
-
-38 goto out_cdev_put;
-
-39
-
-40 replace_fops(filp, fops);
-
-41 if (filp->f_op->open) {
-
-42 ret = filp->f_op->open(inode, filp);
-
-43 if (ret)
-
-44 goto out_cdev_put;
-
-45 }
-
-46
 
-47 return 0;
 
-48
 
-49 out_cdev_put:
 
-50 cdev_put(p);
-
-51 return ret;
-
-52 }
-
-在Linux内核中，使用结构体cdev来描述一个字符设备。代码清单 57‑5中的第14行，inode->i_rdev中保存了字符设备的设备编号，通过函数kobj_lookup函数便可以找到该设备文件cdev结构体的kobj成员，再通过函数container_of便可以得到该字符设备对应的结构体cde
-v。函数container_of的作用就是通过一个结构变量中一个成员的地址找到这个结构体变量的首地址。同时，将cdev结构体记录到文件节点inode中的i_cdev，便于下次打开该文件。继续阅读第36~45行代码，我们可以发现，函数chrdev_open最终将该文件结构体file的成员f_op替换成
+.. code-block:: c
+   :caption: def_chr_fops结构体（位于内核源码/fs/char_dev.c文件）
+   :linenos:
+
+   const struct file_operations def_chr_fops = {
+   .open = chrdev_open,
+   .llseek = noop_llseek,
+   };
+
+最终，会执行def_chr_fops中的open函数，也就是chrdev_open函数，可以理解为
+一个字符设备的通用初始化函数，根据字符设备的设备号，找到相应的
+字符设备，从而得到操作该设备的方法，代码实现如下。
+
+.. image:: media/charac003.jpg
+   :align: center
+   :alt: 未找到图片03|
+
+
+
+
+
+
+
+
+.. code-block:: c
+   :caption: chrdev_open函数（位于内核源码/fs/char_dev.c文件）
+   :linenos:
+
+   static int chrdev_open(struct inode *inode, struct file *filp)
+   {
+   const struct file_operations *fops;
+   struct cdev *p;
+   struct cdev *new = NULL;
+   int ret = 0;
+   spin_lock(&cdev_lock);
+   p = inode->i_cdev;
+    if (!p) {
+    struct kobject *kobj;
+    int idx;
+    spin_unlock(&cdev_lock);
+    kobj = kobj_lookup(cdev_map, inode->i_rdev, &idx);
+    if (!kobj)
+    return -ENXIO;
+    new = container_of(kobj, struct cdev, kobj);
+    spin_lock(&cdev_lock);
+    /* Check i_cdev again in case somebody beat us to it while
+    we dropped the lock.
+   */
+    p = inode->i_cdev;
+    if (!p) {
+    inode->i_cdev = p = new;
+    list_add(&inode->i_devices, &p->list);
+    new = NULL;
+    } else if (!cdev_get(p))
+    ret = -ENXIO;
+    } else if (!cdev_get(p))
+    ret = -ENXIO;
+    spin_unlock(&cdev_lock);
+    cdev_put(new);
+    if (ret)
+    return ret;
+   
+    ret = -ENXIO;
+    fops = fops_get(p->ops);
+    if (!fops)
+    goto out_cdev_put;
+   
+    replace_fops(filp, fops);
+    if (filp->f_op->open) {
+    ret = filp->f_op->open(inode, filp);
+    if (ret)
+    goto out_cdev_put;
+    }
+   
+    return 0;
+   
+    out_cdev_put:
+    cdev_put(p);
+    return ret;
+    }
+
+在Linux内核中，使用结构体cdev来描述一个字符设备。在以上代码中
+的第14行，inode->i_rdev中保存了字符设备的设备编号，通过函数kobj_lookup函数便
+可以找到该设备文件cdev结构体的kobj成员，再通过函数container_of便可以得到
+该字符设备对应的结构体cde
+v。函数container_of的作用就是通过一个结构变量中一个成员的地址找到这个结
+构体变量的首地址。同时，将cdev结构体记录到文件节点inode中的i_cdev，便于下次
+打开该文件。继续阅读第36~45行代码，我们可以发现，函数chrdev_open最终将该文件
+结构体file的成员f_op替换成
 了cdev对应的ops成员，并执行ops结构体中的open函数。
 
-最后，调用图 57‑1的fd_install函数，完成文件描述符和文件结构体file的关联，之后我们使用对该文件描述符fd调用read、write函数，最终都会调用file结构体对应的函数，实际上也就是调用cdev结构体中ops结构体内的相关函数。
+最后，调用上图的fd_install函数，完成文件描述符和文件
+结构体file的关联，之后我们使用对该文件描述符fd调用read、write函数，最终都
+会调用file结构体对应的函数，实际上也就是调用cdev结构体中ops结构体内的相关函数。
 
-总结一下整个过程，当我们使用open函数，打开设备文件时，会根据该设备的文件的设备号找到相应的设备结构体，从而得到了操作该设备的方法。也就是说如果我们要添加一个新设备的话，我们需要提供一个设备号，一个设备结构体以及操作该设备的方法（file_operations结构体）
+总结一下整个过程，当我们使用open函数，打开设备文件时，会根据该设
+备的文件的设备号找到相应的设备结构体，从而得到了操作该设备的方法。也就是
+说如果我们要添加一个新设备的话，我们需要提供一个设备号，一个设备结构体以
+及操作该设备的方法（file_operations结构体）
 。接下来，我们将介绍以上的三个内容。
 
 数据结构
 ~~~~
 
-本节，我们讲解编写设备驱动需要了解到的数据结构体，包括了文件操作方式（file_operations），字符设备结构体（struct cdev）以及文件描述结构体（struct file）。
+本节，我们讲解编写设备驱动需要了解到的数据结
+构体，包括了文件操作方式（file_operations），字符设备
+结构体（struct cdev）以及文件描述结构体（struct file）。
 
 file_operations结构体
 ^^^^^^^^^^^^^^^^^^
 
-上一节，我们提及到的文件结构体file以及字符设备结构体cdev，他们都有一个struct file_operations类型的成员变量。file_operations结构体中包含了操作文件的一系列函数指针，代码清单 57‑6中只列出本章使用到的部分函数。
-
-代码清单 57‑6 file_operations结构体（位于内核源码/include/linux/fs.h文件）
-
-1 struct file_operations {
-
-2
-
-3 loff_t (*llseek) (struct file \*, loff_t, int);
+上一节，我们提及到的文件结构体file以及字符设备
+结构体cdev，他们都有一个struct file_operations类型的
+成员变量。file_operations结构体中包含了操作文件的一系列函数
+指针，一下代码中只列出本章使用到的部分函数。
 
-4 ssize_t (*read) (struct file \*, char \__user \*, size_t, loff_t \*);
 
-5 ssize_t (*write) (struct file \*, const char \__user \*, size_t, loff_t \*);
+.. code-block:: c
+   :caption: file_operations结构体（位于内核源码/include/linux/fs.h文件）
+   :linenos:
 
-6 long (*unlocked_ioctl) (struct file \*, unsigned int, unsigned long);
+   struct file_operations {
+   loff_t (*llseek) (struct file *, loff_t, int);
+   ssize_t (*read) (struct file *, char __user *, size_t, loff_t *);
+   ssize_t (*write) (struct file *, const char __user *, size_t, loff_t *);
+   long (*unlocked_ioctl) (struct file *, unsigned int, unsigned long);
+   int (*open) (struct inode *, struct file *)
+   int (*release) (struct inode *, struct file *);
+   };
 
-7 int (*open) (struct inode \*, struct file \*)
+-  llseek：用于修改文件的当前读写位置，并返回偏移后的位置。参数file传入了对应的文
+   件指针，我们可以看到以上代码中所有的函数都有该形参，通常用于读取文件的信息，如文件
+   类型、读写权限；参数loff_t指定偏移量的大小；参数int是用于指定新位置
+   指定成从文件的某个位置进行偏移，SEEK_SET表示从文件起始处开始偏移；SEEK_CUR表示
+   从当前位置开始偏移；SEEK_END表示从文件结尾开始偏移。
 
-8 int (*release) (struct inode \*, struct file \*);
+-  read：用于读取设备中的数据，并返回成功读取的字节数。该函数指针被
+   设置为NULL时，会导致系统调用read函数报错，提示"非法参数"。该函数有三个参数：file类型指针变量，char
+  __user*类型的数据缓冲区，__user用于修饰变量，表明该变量所在的地址空间是用户空间的。内核模块不能直接使用该数
+  据，需要使用copy_to_user函数来进行操作。size_t类型变量指定读取的数据大小。
 
-9 };
+-  write：用于向设备写入数据，并返回成功写入的字节数，write函数的参数用法与read函数类似，不过在访问__user修饰的数
+据缓冲区，需要使用copy_from_user函数。
 
--  llseek：用于修改文件的当前读写位置，并返回偏移后的位置。参数file传入了对应的文件指针，我们可以看到代码清单
-  57‑6中所有的函数都有该形参，通常用于读取文件的信息，如文件类型、读写权限；参数loff_t指定偏移量的大小；参数int是用于指定新位置指定成从文件的某个位置进行偏移，SEEK_SET表示从文件起始处开始偏移；SEEK_CUR表示从当前位置开始偏移；SEEK_END表示从文件结尾开始偏移。
-
--  read：用于读取设备中的数据，并返回成功读取的字节数。该函数指针被设置为NULL时，会导致系统调用read函数报错，提示“非法参数”。该函数有三个参数：file类型指针变量，char
-  \__user*类型的数据缓冲区，__user用于修饰变量，表明该变量所在的地址空间是用户空间的。内核模块不能直接使用该数据，需要使用copy_to_user函数来进行操作。size_t类型变量指定读取的数据大小。
-
--  write：用于向设备写入数据，并返回成功写入的字节数，write函数的参数用法与read函数类似，不过在访问__user修饰的数据缓冲区，需要使用copy_from_user函数。
-
--  unlocked_ioctl：提供设备执行相关控制命令的实现方法，它对应于应用程序的fcntl函数以及ioctl函数。在 kernel 3.0 中已经完全删除了 struct file_operations 中的 ioctl 函数指针。
+-  unlocked_ioctl：提供设备执行相关控制命令的实现方法，它对应于应用程序的fcntl函数以及ioctl函数。在 kernel 3.0 中已
+经完全删除了 struct file_operations 中的 ioctl 函数指针。
 
 -  open：设备驱动第一个被执行的函数，一般用于硬件的初始化。如果该成员被设置为NULL，则表示这个设备的打开操作永远成功。
 
 -  release：当file结构体被释放时，将会调用该函数。与open函数相反，该函数可以用于释放
 
-上面，我们提到read和write函数时，需要使用copy_to_user函数以及copy_from_user函数来进行数据访问，写入/读取成功函数返回0，失败则会返回未被拷贝的字节数。
-
-代码清单 57‑7copy_to_user和copy_from_user函数（位于内核源码/include/asm-generic/uaccess.h文件）
+上面，我们提到read和write函数时，需要使用copy_to_user函数以及copy_from_user函数来进行数据访问，写入/读取成
+功函数返回0，失败则会返回未被拷贝的字节数。
 
-1 static inline long copy_from_user(void \*to,
 
-2 const void \__user \* from, unsigned long n)
 
-3 static inline long copy_to_user(void \__user \*to,
+.. code-block:: c
+   :caption: copy_to_user和copy_from_user函数（位于内核源码/include/asm-generic/uaccess.h文件）
+   :linenos:
 
-4 const void \*from, unsigned long n)
+   static inline long copy_from_user(void *to,
+   const void __user * from, unsigned long n)
+   static inline long copy_to_user(void __user *to,
+   const void *from, unsigned long n)
 
 -  to：指定目标地址，也就是数据存放的地址，
 
@@ -342,52 +313,54 @@ file_operations结构体
 file结构体
 ^^^^^^^
 
-内核中用file结构体来表示每个打开的文件，每打开一个文件，内核会创建一个结构体，并将对该文件上的操作函数传递给该结构体的成员变量f_op。代码清单 57‑8中，只列出了我们本章需要了解的成员变量。
+内核中用file结构体来表示每个打开的文件，每打开一个文件，内核会创建一个结构体，并将对该文件上的操作函数传递给
+该结构体的成员变量f_op。如下代码中，只列出了我们本章需要了解的成员变量。
 
-代码清单 57‑8 file结构体（位于内核源码/include/fs.h文件）
 
-1 struct file {
 
-2 const struct file_operations \*f_op;
+.. code-block:: c
+   :caption: file结构体（位于内核源码/include/fs.h文件）
+   :linenos:
 
-3 /\* needed for tty driver, and maybe others \*/
-
-4 void \*private_data;
-
-5 };
+   struct file {
+   const struct file_operations *f_op;
+   /* needed for tty driver, and maybe others */
+   void *private_data;
+   };
 
 -  f_op：存放与文件操作相关的一系列函数指针，如open、read、wirte等函数。
 
--  private_data：该指针变量只会用于设备驱动程序中，内核并不会对该成员进行操作。因此，在驱动程序中，通常用于指向描述设备的结构体。
+-  private_data：该指针变量只会用于设备驱动程序中，内核并不会对该成员进行操作。因此，在驱动
+   程序中，通常用于指向描述设备的结构体。
 
 cdev结构体
 ^^^^^^^
 
-如图 57‑2所示，内核用struct cdev结构体来描述一个字符设备，并通过struct kobj_map类型的散列表cdev_map来管理当前系统中的所有字符设备。
-
-|charac004|
+如下图所示，内核用struct cdev结构体来描述一个字符设备，并通过struct kobj_map类型的
+散列表cdev_map来管理当前系统中的所有字符设备。
 
-图 57‑2 cdev_map与cdev的关系
+.. image:: media/charac004.jpg
+   :align: center
+   :alt: 未找到图片04|
 
-代码清单 57‑9 cdev结构体（位于内核源码/include/linux/cdev.h文件）
 
-1 struct cdev {
 
-2 struct kobject kobj;
 
-3 struct module \*owner;
+.. code-block:: c
+   :caption: cdev结构体（位于内核源码/include/linux/cdev.h文件）
+   :linenos:
 
-4 const struct file_operations \*ops;
+   struct cdev {
+   struct kobject kobj;
+   struct module *owner;
+   const struct file_operations *ops;
+   struct list_head list;
+   dev_t dev;
+   unsigned int count;
+   };
 
-5 struct list_head list;
-
-6 dev_t dev;
-
-7 unsigned int count;
-
-8 };
-
--  kobj：内核数据对象，用于管理该结构体。代码清单 57‑5中通过kobj_lookup函数中从cdev_map中得到该成员，由该成员便可以得到相应的字符设备结构体。
+-  kobj：内核数据对象，用于管理该结构体。obj_lookup函
+   数中从cdev_map中得到该成员，由该成员便可以得到相应的字符设备结构体。
 
 -  owner：指向了关联该设备的内核模块，实际上就是关联了驱动程序，通常设置为THIS_MODULE。
 
@@ -402,55 +375,72 @@ cdev结构体
 字符设备驱动程序框架
 ~~~~~~~~~~
 
-前面我们已经讲解了一些相关的数据结构，但是各个结构体要如何进行联系？答案肯定是通过函数。因此，本节我们开始讲解关于字符设备的驱动程序框架。关于框架，我们在内核模块那张也讲了一个内核模块的框架，实际上，在Linux上写驱动程序，都是做一些“填空题”。因为Linux给我们提供了一个基本的框架，如果你不按
+前面我们已经讲解了一些相关的数据结构，但是各个结构体要如何进行联系？答案肯定
+是通过函数。因此，本节我们开始讲解关于字符设备的驱动程序框架。关于框架，我们
+在内核模块那张也讲了一个内核模块的框架，实际上，在Linux上写驱动程序，都是做
+一些"填空题"。因为Linux给我们提供了一个基本的框架，如果你不按
 照这个框架写驱动，那么你写的驱动程序是不能被内核所接纳的。
 
 初始化/移除字符设备
 ^^^^^^^^^^
 
-Linux内核提供了两种方式来定义字符设备，见代码清单 57‑10。
+Linux内核提供了两种方式来定义字符设备，如下所示。
 
-代码清单 57‑10 定义字符设备
 
-1 //第一种方式
 
-2 static struct cdev chrdev;
+.. code-block:: c
+   :caption: 定义字符设备
+   :linenos:
 
-3 //第二种方式
+   //第一种方式
+   static struct cdev chrdev;
+   //第二种方式
+   struct cdev *cdev_alloc(void);
 
-4 struct cdev \*cdev_alloc(void);
+第一种方式，就是我们常见的变量定义；第二种方式，是内核提供的动态分配方式，调用该函数之
+后，会返回一个struct cdev类型的指针，用于描述字符设备。
 
-第一种方式，就是我们常见的变量定义；第二种方式，是内核提供的动态分配方式，调用该函数之后，会返回一个struct cdev类型的指针，用于描述字符设备。
+从内核中移除某个字符设备，则需要调用cdev_del函数，如下所示。
 
-从内核中移除某个字符设备，则需要调用cdev_del函数，见代码清单 57‑11。
 
-代码清单 57‑11 cdev_del函数
+.. code-block:: c
+   :caption: cdev_del函数
+   :linenos:
 
-1 void cdev_del(struct cdev \*p)
+   void cdev_del(struct cdev *p)
 
 该函数需要将我们的字符设备结构体的地址作为实参传递进去，就可以从内核中移除该字符设备了。
 
 分配/注销设备号
 ^^^^^^^^
 
-Linux的各种设备都以文件的形式存放在/dev目录下，为了管理这些设备，系统为各个设备进行编号，每个设备号又分为主设备号和次设备号。主设备号用来区分不同种类的设备，如USB，tty等，次设备号用来区分同一类型的多个设备，如tty0，tty1……图
-57‑3列出了部分tty设备，他们的主设备号都是4，而不同的次设备号分别对应一个tty设备。
+Linux的各种设备都以文件的形式存放在/dev目录下，为了管理这些设备，系
+统为各个设备进行编号，每个设备号又分为主设备号和次设备号。主设备号用来
+区分不同种类的设备，如USB，tty等，次设备号用来区分同一类型的多个设备，如tty0，tty1……下图
+列出了部分tty设备，他们的主设备号都是4，而不同的次设备号分别对应一个tty设备。
 
-|charac005|
+.. image:: media/charac005.jpg
+   :align: center
+   :alt: 未找到图片05|
 
-图 57‑3 tty设备
 
-内核提供了一种数据类型：dev_t，用于记录设备编号，该数据类型实际上是一个无符号32位整型，其中的12位用于表示主设备号，剩余的20位则用于表示次设备号。
 
-实际上，内核将一部分主设备号分配给了一些常见的设备。在内核源码的Documentation/devices.txt文件中可以找到这些设备以及这部分设备占据的主设备号。
+内核提供了一种数据类型：dev_t，用于记录设备编号，该数据类
+型实际上是一个无符号32位整型，其中的12位用于表示主设备号，剩余的20位则用于表示次设备号。
 
-|charac006|
+实际上，内核将一部分主设备号分配给了一些常见的设备。在内核源码
+的Documentation/devices.txt文件中可以找到这些设备以及这部分设备占据的主设备号。
 
-图 57‑4 devices文件
+.. image:: media/charac006.jpg
+   :align: center
+   :alt: 未找到图片06|
 
-devices文件大致上分成了图 57‑4的四个部分：
 
-1. 这一部分的内容，主要记录了当前内核所占据的所有字符设备的主设备号，我们通过检查这一列的内容，便可以知道当前的主设备号是否被内核占用。
+
+devices文件大致上分成了上图的四个部分：
+
+1. 这一部分的内容，主要记录了当前内核所占据的所有字符设备的主设备号，我们通过检查这一列
+   的内容，便可以知道当前的主设备号是否被内核占用。
 
 2. 第二部分的内容，主要记录了设备的类型，主要分为块设备（block）以及字符设备（char），我们这里只关心字符设备即可。
 
@@ -458,16 +448,22 @@ devices文件大致上分成了图 57‑4的四个部分：
 
 4. 第四部分的内容，则是对每个设备的概述。
 
-根据上一节提到的，创建一个新的字符设备之前，我们需要为新的字符设备注册一个新的设备号，就好像每个人都有一个身份证号，用来标识自己。内核提供了三种方式，来完成这项工作。
+根据上一节提到的，创建一个新的字符设备之前，我们需要为新的字符设备注册一个新的设备号，就好像
+每个人都有一个身份证号，用来标识自己。内核提供了三种方式，来完成这项工作。
 
 register_chrdev_region函数
 ''''''''''''''''''''''''
 
-register_chrdev_region函数用于静态地为一个字符设备申请一个或多个设备编号。该函数在分配成功时，会返回0；失败则会返回相应的错误码，函数原型见代码清单 57‑12。
+register_chrdev_region函数用于静态地为一个字符设备申请一个或多个设备编号。该函数在分配
+成功时，会返回0；失败则会返回相应的错误码，函数原型如下所示。
+
 
-代码清单 57‑12 register_chrdev_region函数原型
 
-1 int register_chrdev_region(dev_t from, unsigned count, const char \*name)
+.. code-block:: c
+   :caption: register_chrdev_region函数原型
+   :linenos:
+
+   int register_chrdev_region(dev_t from, unsigned count, const char *name)
 
 参数说明：
 
@@ -477,33 +473,39 @@ register_chrdev_region函数用于静态地为一个字符设备申请一个或
 
 -  name：用于指定该设备的名称，我们可以在/proc/devices中看到该设备。
 
-register_chrdev_region函数使用时需要指定一个设备编号， Linux内核为我们提供了生成设备号的宏定义MKDEV，用于将主设备号和次设备号合成一个设备号，主设备可以通过查阅内核源码的Documentation/devices.txt文件，而次设备号通常是从编号0开始。除此之外，内
+register_chrdev_region函数使用时需要指定一个设备编号， Linux内核为我们提供了生成设备号的
+宏定义MKDEV，用于将主设备号和次设备号合成一个设备号，主设备可以通过查阅内核
+源码的Documentation/devices.txt文件，而次设备号通常是从编号0开始。除此之外，内
 核还提供了另外两个宏定义MAJOR和MINOR，可以根据设备的设备号来获取设备的主设备号和次设备号。
 
-代码清单 57‑13 合成设备号MKDEV（位于内核源码/include/linux/kdev_t.h）
-
-1 #define MINORBITS 20
-
-2 #define MINORMASK ((1U << MINORBITS) - 1)
 
-3
+.. code-block:: c
+   :caption: 合成设备号MKDEV（位于内核源码/include/linux/kdev_t.h）
+   :linenos:
 
-4 #define MAJOR(dev) ((unsigned int) ((dev) >> MINORBITS))
-
-5 #define MINOR(dev) ((unsigned int) ((dev) & MINORMASK))
-
-6 #define MKDEV(ma,mi) (((ma) << MINORBITS) \| (mi))
+   #define MINORBITS 20
+   #define MINORMASK ((1U << MINORBITS) - 1)
+   #define MAJOR(dev) ((unsigned int) ((dev) >> MINORBITS))
+   #define MINOR(dev) ((unsigned int) ((dev) & MINORMASK))
+   #define MKDEV(ma,mi) (((ma) << MINORBITS) \| (mi))
 
 alloc_chrdev_region函数
 '''''''''''''''''''''
 
-使用register_chrdev_region函数时，都需要去查阅内核源码的Documentation/devices.txt文件，这就十分不方便。因此，内核又为我们提供了一种能够动态分配设备编号的方式：alloc_chrdev_region。
+使用register_chrdev_region函数时，都需要去查阅内核
+源码的Documentation/devices.txt文件，这就十分不方便。因此，内核又
+为我们提供了一种能够动态分配设备编号的方式：alloc_chrdev_region。
+
+调用alloc_chrdev_region函数，内核会自动分配给我们一个尚未使用的主设备号。我
+们可以通过命令"cat /proc/devices"查询内核分配的主设备号。
 
-调用alloc_chrdev_region函数，内核会自动分配给我们一个尚未使用的主设备号。我们可以通过命令“cat /proc/devices”查询内核分配的主设备号。
 
-代码清单 57‑14 alloc_chrdev_region函数原型
 
-1 int alloc_chrdev_region(dev_t \*dev, unsigned baseminor, unsigned count, const char \*name)
+.. code-block:: c
+   :caption: alloc_chrdev_region函数原型
+   :linenos:
+
+   int alloc_chrdev_region(dev_t *dev, unsigned baseminor, unsigned count, const char *name)
 
 参数说明如下：
 
@@ -516,11 +518,16 @@ alloc_chrdev_region函数
 unregister_chrdev_region函数
 ''''''''''''''''''''''''''
 
-当我们删除字符设备时候，我们需要把分配的设备编号交还给内核，对于使用register_chrdev_region函数以及alloc_chrdev_region函数分配得到的设备编号，可以使用unregister_chrdev_region函数实现该功能。
+当我们删除字符设备时候，我们需要把分配的设备编号交还给内核，对于使用register_chrdev_region函数
+以及alloc_chrdev_region函数分配得到的设备编号，可以使用unregister_chrdev_region函数实现该功能。
+
 
-代码清单 57‑15 unregister_chrdev_region函数（位于内核源码/fs/char_dev.c）
 
-1 void unregister_chrdev_region(dev_t from, unsigned count)
+.. code-block:: c
+   :caption: unregister_chrdev_region函数（位于内核源码/fs/char_dev.c）
+   :linenos:
+
+   void unregister_chrdev_region(dev_t from, unsigned count)
 
 -  from：指定需要注销的字符设备的设备编号起始值，我们一般将定义的dev_t变量作为实参。
 
@@ -529,19 +536,20 @@ unregister_chrdev_region函数
 register_chrdev函数
 '''''''''''''''''
 
-除了上述的两种，内核还提供了register_chrdev函数用于分配设备号。该函数是一个内联函数，它不仅支持静态申请设备号，也支持动态申请设备号，并将主设备号返回，函数原型见代码清单 57‑16。
-
-代码清单 57‑16 register_chrdev函数原型（位于内核源码/include/linux/fs.h文件）
+除了上述的两种，内核还提供了register_chrdev函数用于分配设备号。该函数是一个内联函数，它不
+仅支持静态申请设备号，也支持动态申请设备号，并将主设备号返回，函数原型如下所示。
 
-1 static inline int register_chrdev(unsigned int major, const char \*name,
 
-2 const struct file_operations \*fops)
 
-3 {
+.. code-block:: c
+   :caption: register_chrdev函数原型（位于内核源码/include/linux/fs.h文件）
+   :linenos:
 
-4 return \__register_chrdev(major, 0, 256, name, fops);
-
-5 }
+   static inline int register_chrdev(unsigned int major, const char *name,
+   const struct file_operations *fops)
+   {
+   return __register_chrdev(major, 0, 256, name, fops);
+   }
 
 参数说明：
 
@@ -551,22 +559,24 @@ register_chrdev函数
 
 -  fops：用于操作该设备的函数接口指针。
 
-我们从代码清单 57‑16中可以看到，使用register_chrdev函数向内核申请设备号，同一类字符设备（即主设备号相同），会在内核中申请了256个，通常情况下，我们不需要用到这么多个设备，这就造成了极大的资源浪费。
+我们从以上代码中可以看到，使用register_chrdev函数向内核申请设备号，同一类字
+符设备（即主设备号相同），会在内核中申请了256个，通常情况下，我们不需要用到这么多个设备，这就造成了极大的资源浪费。
 
 unregister_chrdev函数
 '''''''''''''''''''
 
 使用register函数申请的设备号，则应该使用unregister_chrdev函数进行注销。
 
-代码清单 57‑17 unregister_chrdev函数（位于内核源码/include/linux/fs.h文件）
-
-1 static inline void unregister_chrdev(unsigned int major, const char \*name)
 
-2 {
 
-3 \__unregister_chrdev(major, 0, 256, name);
+.. code-block:: c
+   :caption: unregister_chrdev函数（位于内核源码/include/linux/fs.h文件）
+   :linenos:
 
-4 }
+   static inline void unregister_chrdev(unsigned int major, const char *name)
+   {
+   __unregister_chrdev(major, 0, 256, name);
+   }
 
 -  major：指定需要释放的字符设备的主设备号，一般使用register_chrdev函数的返回值作为实参。
 
@@ -575,11 +585,16 @@ unregister_chrdev函数
 关联设备的操作方式
 ^^^^^^^^^
 
-前面我们已经提到过了，编写一个字符设备最重要的事情，就是要实现file_operations这个结构体中的函数。实现之后，如何将该结构体与我们的字符设备结构相关联呢？内核提供了cdev_init函数，来实现这个工程。
+前面我们已经提到过了，编写一个字符设备最重要的事情，就是要实现file_operations这个结
+构体中的函数。实现之后，如何将该结构体与我们的字符设备结构相关联呢？内核提供了cdev_init函数，来实现这个工程。
+
 
-代码清单 57‑18 cdev_init函数（位于内核源码/fs/char_dev.c）
 
-1 void cdev_init(struct cdev \*cdev, const struct file_operations \*fops)
+.. code-block:: c
+   :caption: cdev_init函数（位于内核源码/fs/char_dev.c）
+   :linenos:
+
+   void cdev_init(struct cdev *cdev, const struct file_operations *fops)
 
 -  cdev：struct cdev类型的指针变量，指向需要关联的字符设备结构体；
 
@@ -588,11 +603,15 @@ unregister_chrdev函数
 注册设备
 ^^^^
 
-cdev_add函数用于向内核的cdev_map散列表添加一个新的字符设备，见代码清单 57‑19。
+cdev_add函数用于向内核的cdev_map散列表添加一个新的字符设备，如下所示。
+
+
 
-代码清单 57‑19 cdev_add函数（位于内核源码/fs/char_dev.c文件）
+.. code-block:: c
+   :caption: cdev_add函数（位于内核源码/fs/char_dev.c文件）
+   :linenos:
 
-1 int cdev_add(struct cdev \*p, dev_t dev, unsigned count)
+   int cdev_add(struct cdev *p, dev_t dev, unsigned count)
 
 -  p：struct cdev类型的指针，用于指定需要添加的字符设备；
 
@@ -603,344 +622,262 @@ cdev_add函数用于向内核的cdev_map散列表添加一个新的字符设备
 字符设备驱动程序实验
 ~~~~~~~~~~
 
-结合前面所有的知识点，首先，字符设备驱动程序是以内核模块的形式存在的，因此，使用内核模块的程序框架是毫无疑问的。紧接着，我们要向系统注册一个新的字符设备，需要这几样东西：字符设备结构体cdev，设备编号devno，以及最最最重要的操作方式结构体file_operations。
+结合前面所有的知识点，首先，字符设备驱动程序是以内核模块的形式存在的，因此，使用内核
+模块的程序框架是毫无疑问的。紧接着，我们要向系统注册一个新的字符设备，需要这几样东西：字符
+设备结构体cdev，设备编号devno，以及最最最重要的操作方式结构体file_operations。
 
 下面，我们开始编写我们自己的字符设备驱动程序。
 
+**本章的示例代码目录为：base_code/linux_driver/EmbedCharDev/chrdev.c**
+
 内核模块框架
 ^^^^^^
 
-既然我们的设备程序是以内核模块的方式存在的，那么就需要先写出一个基本的内核框架，见代码清单 57‑20。
-
-代码清单 57‑20 内核模块加载函数（位于文件chrdev.c）
-
-1 #define DEV_NAME "EmbedCharDev"
-
-2 #define DEV_CNT (1)
-
-3 #define BUFF_SIZE 128
-
-4 //定义字符设备的设备号
-
-5 static dev_t devno;
-
-6 //定义字符设备结构体chr_dev
-
-7 static struct cdev chr_dev;
-
-8 static int \__init chrdev_init(void)
-
-9 {
-
-10 int ret = 0;
-
-11 printk("chrdev init\n");
-
-12 //第一步
-
-13 //采用动态分配的方式，获取设备编号，次设备号为0，
-
-14 //设备名称为EmbedCharDev，可通过命令cat /proc/devices查看
-
-15 //DEV_CNT为1，当前只申请一个设备编号
-
-16 ret = alloc_chrdev_region(&devno, 0, DEV_CNT, DEV_NAME);
-
-17 if (ret < 0) {
-
-18 printk("fail to alloc devno\n");
-
-19 goto alloc_err;
-
-20 }
-
-21 //第二步
-
-22 //关联字符设备结构体cdev与文件操作结构体file_operations
-
-23 cdev_init(&chr_dev, &chr_dev_fops);
-
-24 //第三步
-
-25 //添加设备至cdev_map散列表中
-
-26 ret = cdev_add(&chr_dev, devno, DEV_CNT);
-
-27 if (ret < 0) {
-
-28 printk("fail to add cdev\n");
-
-29 goto add_err;
-
-30 }
-
-31 return 0;
-
-32
-
-33 add_err:
-
-34 //添加设备失败时，需要注销设备号
-
-35 unregister_chrdev_region(devno, DEV_CNT);
-
-36 alloc_err:
-
-37 return ret;
-
-38 }
-
-39 module_init(chrdev_init);
-
-在模块的加载函数中，代码清单
-57‑20的第16~20行使用动态分配的方式来获取设备号，指定设备的名称为“EmbedCharDev”，只申请一个设备号，并且次设备号为0。这里使用C语言的goto语法，当获取失败时，直接返回对应的错误码。成功获取到设备号之后，我们还缺字符设备结构体以及文件的操作方式。代码清单 57‑20中使用定义
-变量的方式定义了一个字符设备结构体chr_dev，调用cdev_init函数将chr_dev结构体和文件操作结构体相关联，该结构体的具体实现下节见分晓。到这里，我们的字符设备就已经编写完毕。最后我们只需要调用cdev_add函数将我们的字符设备添加到字符设备管理列表cdev_map即可。此处也使用了
-goto语法，当添加设备失败的话，需要将申请的设备号注销掉，要养成一个好习惯，不要“占着茅坑不拉屎”。
-
-模块的卸载函数就相对简单一下，只需要完成注销设备号，以及移除字符设备，见代码清单 57‑21。
-
-代码清单 57‑21 内核模块卸载函数（位于文件chrdev.c）
-
-1 static void \__exit chrdev_exit(void)
-
-2 {
-
-3 printk("chrdev exit\n");
-
-4 unregister_chrdev_region(devno, DEV_CNT);
-
-5
-
-6 cdev_del(&chr_dev);
-
-7 }
-
-8 module_exit(chrdev_exit);
+既然我们的设备程序是以内核模块的方式存在的，那么就需要先写出一个基本的内核框架，见如下所示。
+
+
+
+.. code-block:: c
+   :caption: 内核模块加载函数（位于../base_code/linux_driver/EmbedCharDev/chrdev.c）
+   :linenos:
+
+   #define DEV_NAME "EmbedCharDev"
+   #define DEV_CNT (1)
+   #define BUFF_SIZE 128
+   //定义字符设备的设备号
+   static dev_t devno;
+   //定义字符设备结构体chr_dev
+   static struct cdev chr_dev;
+   static int __init chrdev_init(void)
+   {
+    int ret = 0;
+    printk("chrdev init\n");
+    //第一步
+    //采用动态分配的方式，获取设备编号，次设备号为0，
+    //设备名称为EmbedCharDev，可通过命令cat /proc/devices查看
+    //DEV_CNT为1，当前只申请一个设备编号
+    ret = alloc_chrdev_region(&devno, 0, DEV_CNT, DEV_NAME);
+    if (ret < 0) {
+    printk("fail to alloc devno\n");
+    goto alloc_err;
+    }
+    //第二步
+    //关联字符设备结构体cdev与文件操作结构体file_operations
+    cdev_init(&chr_dev, &chr_dev_fops);
+    //第三步
+    //添加设备至cdev_map散列表中
+    ret = cdev_add(&chr_dev, devno, DEV_CNT);
+    if (ret < 0) {
+    printk("fail to add cdev\n");
+    goto add_err;
+    }
+    return 0;
+   
+    add_err:
+    //添加设备失败时，需要注销设备号
+    unregister_chrdev_region(devno, DEV_CNT);
+    alloc_err:
+    return ret;
+    }
+    module_init(chrdev_init);
+
+在模块的加载函数中，以上代码的第16~20行使用动态分配的方式来获取设备号，指定设备的名称为"EmbedCharDev"，只申请
+一个设备号，并且次设备号为0。这里使用C语言的goto语法，当获取失败时，直接返回对应的错
+误码。成功获取到设备号之后，我们还缺字符设备结构体以及文件的操作方式。以上代码中使用定义
+变量的方式定义了一个字符设备结构体chr_dev，调用cdev_init函数将chr_dev结构体和文件操
+作结构体相关联，该结构体的具体实现下节见分晓。到这里，我们的字符设备就已经编写完毕。最后
+我们只需要调用cdev_add函数将我们的字符设备添加到字符设备管理列表cdev_map即可。此处也使用了
+goto语法，当添加设备失败的话，需要将申请的设备号注销掉，要养成一个好习惯，不要"占着茅坑不拉屎"。
+
+模块的卸载函数就相对简单一下，只需要完成注销设备号，以及移除字符设备，如下所示。
+
+
+
+.. code-block:: c
+   :caption: 内核模块卸载函数（位于../base_code/linux_driver/EmbedCharDev/chrdev.c）
+   :linenos:
+
+   static void __exit chrdev_exit(void)
+   {
+   printk("chrdev exit\n");
+   unregister_chrdev_region(devno, DEV_CNT);
+   cdev_del(&chr_dev);
+   }
+   module_exit(chrdev_exit);
 
 文件操作方式的实现
 ^^^^^^^^^
 
-下面，我们开始实现字符设备最重要的部分：文件操作方式结构体file_operations，见代码清单 57‑22。
-
-代码清单 57‑22 file_operations结构体（位于文件chrdev.c）
-
-1 #define BUFF_SIZE 128
-
-2 //数据缓冲区
-
-3 static char vbuf[BUFF_SIZE];
-
-4 static struct file_operations chr_dev_fops = {
-
-5 .owner = THIS_MODULE,
-
-6 .open = chr_dev_open,
-
-7 .release = chr_dev_release,
-
-8 .write = chr_dev_write,
-
-9 .read = chr_dev_read,
-
-10 };
-
-由于这个字符设备是一个虚拟的设备，与硬件并没有什么关联，因此，open函数与release直接返回0即可，我们重点关注write以及read函数的实现。
-
-代码清单 57‑23 chr_dev_open函数与chr_dev_release函数（位于文件chrdev.c）
-
-1 static int chr_dev_open(struct inode \*inode, struct file \*filp)
-
-2 {
-
-3 printk("\nopen\n");
+下面，我们开始实现字符设备最重要的部分：文件操作方式结构体file_operations，见如下所示。
 
-4 return 0;
 
-5 }
 
-6
+.. code-block:: c
+   :caption: file_operations结构体（位于../base_code/linux_driver/EmbedCharDev/chrdev.c）
+   :linenos:
 
-7 static int chr_dev_release(struct inode \*inode, struct file \*filp)
+   #define BUFF_SIZE 128
+   //数据缓冲区
+   static char vbuf[BUFF_SIZE];
+   static struct file_operations chr_dev_fops = {
+   .owner = THIS_MODULE,
+   .open = chr_dev_open,
+   .release = chr_dev_release,
+   .write = chr_dev_write,
+   .read = chr_dev_read,
+    };
 
-8 {
+由于这个字符设备是一个虚拟的设备，与硬件并没有什么关联，因此，open函数与release直接返回0即可，我们重点
+关注write以及read函数的实现。
 
-9 printk("\nrelease\n");
 
-10 return 0;
 
-11 }
+.. code-block:: c
+   :caption: chr_dev_open函数与chr_dev_release函数（位于../base_code/linux_driver/EmbedCharDev/chrdev.c）
+   :linenos:
 
-我们在open函数与release函数中打印相关的调试信息，见代码清单 57‑23。
+   static int chr_dev_open(struct inode *inode, struct file *filp)
+   {
+   printk("\nopen\n");
+   return 0;
+   }
+   static int chr_dev_release(struct inode *inode, struct file *filp)
+   {
+   printk("\nrelease\n");
+    return 0;
+    }
 
-代码清单 57‑24 chr_dev_write函数（位于文件chrdev.c）
+我们在open函数与release函数中打印相关的调试信息，如上方代码所示。
 
-1 static ssize_t chr_dev_write(struct file \*filp, const char \__user \* buf, size_t count, loff_t \*ppos)
 
-2 {
 
-3 unsigned long p = \*ppos;
+.. code-block:: c
+   :caption: chr_dev_write函数（位于../base_code/linux_driver/EmbedCharDev/chrdev.c）
+   :linenos:
 
-4 int ret;
+   static ssize_t chr_dev_write(struct file *filp, const char __user * buf, size_t count, loff_t *ppos)
+   {
+   unsigned long p = *ppos;
+   int ret;
+   int tmp = count ;
+   if (p > BUFF_SIZE)
+   return 0;
+   if (tmp > BUFF_SIZE - p)
+   tmp = BUFF_SIZE - p;
+    ret = copy_from_user(vbuf, buf, tmp);
+    *ppos += tmp;
+    return tmp;
+    }
 
-5 int tmp = count ;
-
-6 if (p > BUFF_SIZE)
-
-7 return 0;
-
-8 if (tmp > BUFF_SIZE - p)
-
-9 tmp = BUFF_SIZE - p;
-
-10 ret = copy_from_user(vbuf, buf, tmp);
-
-11 \*ppos += tmp;
-
-12 return tmp;
-
-13 }
-
-当我们的应用程序调用write函数，最终就调用我们的chr_dev_write函数。在该函数中，变量p记录了当前文件的读写位置，如果超过了数据缓冲区的大小（128字节）的话，直接返回0。并且如果要读写的数据个数超过了数据缓冲区剩余的内容的话，则只读取剩余的内容。使用copy_from_user从用户
+当我们的应用程序调用write函数，最终就调用我们的chr_dev_write函数。在该函数中，变量p记录
+了当前文件的读写位置，如果超过了数据缓冲区的大小（128字节）的话，直接返回0。并且如果要读
+写的数据个数超过了数据缓冲区剩余的内容的话，则只读取剩余的内容。使用copy_from_user从用户
 空间拷贝tmp个字节的数据到数据缓冲区中，同时让文件的读写位置偏移同样的字节数。
 
-代码清单 57‑25 chr_dev_read函数（位于文件chrdev.c）
-
-1 static ssize_t chr_dev_read(struct file \*filp, char \__user \* buf, size_t count, loff_t \*ppos)
-
-2 {
-
-3 unsigned long p = \*ppos;
-
-4 int ret;
-
-5 int tmp = count ;
 
-6
+.. code-block:: c
+   :caption: chr_dev_read函数（位于../base_code/linux_driver/EmbedCharDev/chrdev.c）
+   :linenos:
 
-7
+   static ssize_t chr_dev_read(struct file *filp, char __user * buf, size_t count, loff_t *ppos)
+   {
+   unsigned long p = *ppos;
+   int ret;
+   int tmp = count ;
+   if (p >= BUFF_SIZE)
+   return 0;
+    if (tmp > BUFF_SIZE - p)
+    tmp = BUFF_SIZE - p;
+    ret = copy_to_user(buf, vbuf+p, tmp);
+    *ppos +=tmp;
+    return tmp;
+    }
 
-8 if (p >= BUFF_SIZE)
-
-9 return 0;
-
-10 if (tmp > BUFF_SIZE - p)
-
-11 tmp = BUFF_SIZE - p;
-
-12 ret = copy_to_user(buf, vbuf+p, tmp);
-
-13 \*ppos +=tmp;
-
-14 return tmp;
-
-15 }
-
-同样的，当我们应用程序调用read函数，则会执行chr_dev_read函数的内容。该函数的实现与chr_dev_write函数类似，区别在于，使用copy_to_user从数据缓冲区拷贝tmp个字节的数据到用户空间中。
+同样的，当我们应用程序调用read函数，则会执行chr_dev_read函数的内容。该函数的
+实现与chr_dev_write函数类似，区别在于，使用copy_to_user从数据缓冲区拷贝tmp个字节的数据到用户空间中。
 
 应用程序验证
 ^^^^^^
 
-代码清单 57‑26 Makefile
-
-1 KERNEL_DIR=/home/embedfire/module/linux-imx
-
-2
-
-3 obj-m := chrdev.o
-
-4
-
-5 all:
-
-6 $(MAKE) -C $(KERNEL_DIR) M=$(CURDIR) modules
-
-7
-
-8 .PHONY:clean
-
-9 clean:
-
-10 $(MAKE) -C $(KERNEL_DIR) M=$(CURDIR) clean
-
-编写Makefile，执行make，生成的chrdev.ko文件通过nfs网络文件系统，让开发板能够访问该文件。执行以下命令：
+   :caption: Makefile(位于../base_code/linux_driver/EmbedCharDev/Makefile)
+   :language: makefile
+   :linenos:   
+   
+   KERNEL_DIR=/home/embedfire/module/linux-imx
+   obj-m := chrdev.o
+   all:
+   $(MAKE) -C $(KERNEL_DIR) M=$(CURDIR) modules
+   .PHONY:clean
+   clean:
+    $(MAKE) -C $(KERNEL_DIR) M=$(CURDIR) clean
+
+编写Makefile，执行make，生成的chrdev.ko文件通过nfs网络文件系统，让
+开发板能够访问该文件。执行以下命令：
 
 insmod chrdev.ko
 
 cat /proc/devices
 
-|charac007|
+.. image:: media/charac007.jpg
+   :align: center
+   :alt: 未找到图片07|
+
 
-图 57‑5 EmbedCharDev设备
 
 我们从/proc/devices文件中，可以看到我们注册的字符设备EmbedCharDev的主设备号为248。
 
 mknod /dev/chrdev c 248 0
 
-使用mknod命令来创建一个新的设备chrdev，见图 57‑6。
-
-|charac008|
-
-图 57‑6 chrdev设备
-
-下面，我们开始编写应用程序，来读写我们的字符设备，见代码清单 57‑27。
-
-代码清单 57‑27 main.c函数（位于文件main.c）
-
-1 #include <stdio.h>
-
-2 #include <unistd.h>
-
-3 #include <fcntl.h>
-
-4 #include <string.h>
-
-5 char \*wbuf = "Hello World\n";
-
-6 char rbuf[128];
-
-7 int main(void)
-
-8 {
-
-9 printf("EmbedCharDev test\n");
-
-10 //打开文件
-
-11 int fd = open("/dev/chrdev", O_RDWR);
-
-12 //写入数据
-
-13 write(fd, wbuf, strlen(wbuf));
-
-14 //写入完毕，关闭文件
-
-15 close(fd);
+使用mknod命令来创建一个新的设备chrdev，见下图。
 
-16 //打开文件
+.. image:: media/charac008.jpg
+   :align: center
+   :alt: 未找到图片08|
 
-17 fd = open("/dev/chrdev", O_RDWR);
 
-18 //读取文件内容
 
-19 read(fd, rbuf, 128);
+下面，我们开始编写应用程序，来读写我们的字符设备，如下所示。
 
-20 //打印读取的内容
 
-21 printf("The content : %s", rbuf);
 
-22 //读取完毕，关闭文件
+.. code-block:: c
+   :caption: main.c函数（位于../base_code/linux_driver/EmbedCharDev/main.c）
+   :linenos:
 
-23 close(fd);
+   #include <stdio.h>
+   #include <unistd.h>
+   #include <fcntl.h>
+   #include <string.h>
+   char *wbuf = "Hello World\n";
+   char rbuf[128];
+   int main(void)
+   {
+   printf("EmbedCharDev test\n");
+    //打开文件
+    int fd = open("/dev/chrdev", O_RDWR);
+    //写入数据
+    write(fd, wbuf, strlen(wbuf));
+    //写入完毕，关闭文件
+    close(fd);
+    //打开文件
+    fd = open("/dev/chrdev", O_RDWR);
+    //读取文件内容
+    read(fd, rbuf, 128);
+    //打印读取的内容
+    printf("The content : %s", rbuf);
+    //读取完毕，关闭文件
+    close(fd);
+    return 0;
+    }
 
-24 return 0;
+main函数中，打开文件/dev/chrdev，这里只是进行简单的读写测试。最后，我们可以看
+到终端的输出信息，见下图。
 
-25 }
+.. image:: media/charac009.jpg
+   :align: center
+   :alt: 未找到图片09|
 
-main函数中，打开文件/dev/chrdev，这里只是进行简单的读写测试。最后，我们可以看到终端的输出信息，见图 57‑7。
 
-|charac009|
-
-图 57‑7 实验结果
 
 实际上，我们也可以通过echo或者cat命令，来测试我们的设备驱动程序。
 
@@ -948,9 +885,11 @@ echo "EmbedCharDev test" > /dev/chrdev
 
 cat /dev/chrdev
 
-|charac010|
+.. image:: media/charac010.jpg
+   :align: center
+   :alt: 未找到图片10|
+
 
-图 57‑8 echo、cat命令测试结果
 
 当我们不需要该内核模块的时候，我们可以执行以下命令：
 
@@ -963,135 +902,115 @@ rm /dev/chrdev
 一个驱动支持多个设备
 ~~~~~~~~~~
 
-在Linux内核中，主设备号用于标识设备对应的驱动程序，告诉Linux内核使用哪一个驱动程序为该设备服务。但是，次设备号表示了同类设备的各个设备。图 57‑4中列出了所有主设备号为1的设备，每个设备的功能都是不一样的。如何能够用一个驱动程序去控制各种设备呢？很明显，首先，我们可以根据次设备号，来区分
-各种设备；其次，就是前文提到过的file结构体的私有数据成员private_data。我们可以通过该成员来做文章，不难想到为什么只有open函数和close函数的形参才有file结构体，因为驱动程序第一个执行的是操作就是open，通过open函数就可以控制我们想要驱动的底层硬件。
+在Linux内核中，主设备号用于标识设备对应的驱动程序，告诉Linux内核使用哪一个驱动
+程序为该设备服务。但是，次设备号表示了同类设备的
+各个设备。每个设备
+的功能都是不一样的。如何能够用一个驱动程序去控制各种设备呢？很
+明显，首先，我们可以根据次设备号，来区分
+各种设备；其次，就是前文提到过的file结构体的私有数据成员private_data。我们可以通
+过该成员来做文章，不难想到为什么只有open函数和close函数的形参才有file结构体，因为驱
+动程序第一个执行的是操作就是open，通过open函数就可以控制我们想要驱动的底层硬件。
 
 下面介绍第一种实现方式，将我们的上一节程序改善一下，生成了两个设备，各自管理各自的数据缓冲区。
 
-代码清单 57‑28 chrdev.c修改部分（位于文件chrdev.c）
-
-1 #define DEV_NAME "EmbedCharDev"
-
-2 #define DEV_CNT (2) (1)
-
-3 #define BUFF_SIZE 128
-
-4 //定义字符设备的设备号
-
-5 static dev_t devno;
-
-6 //定义字符设备结构体chr_dev
-
-7 static struct cdev chr_dev;
-
-8 //数据缓冲区
-
-9 static char vbuf1[BUFF_SIZE]; (2)
-
-10 static char vbuf2[BUFF_SIZE]; (3)
-
-代码清单 57‑28中，（1）处修改了宏定义DEV_CNT，将原本的个数1改为2，这样的话，我们的驱动程序便可以管理两个设备。（2）~（3）处修改为两个数据缓冲区。
-
-代码清单 57‑29 chr_dev_open函数修改（位于文件chrdev.c）
-
-1 static int chr_dev_open(struct inode \*inode, struct file \*filp)
-
-2 {
-
-3 printk("\nopen\n ");
-
-4 switch (MINOR(inode->i_rdev)) {
-
-5 case 0 : {
-
-6 filp->private_data = vbuf1;
-
-7 break;
-
-8 }
-
-9 case 1 : {
-
-10 filp->private_data = vbuf2;
-
-11 break;
-
-12 }
-
-13 }
-
-14 return 0;
-
-15 }
-
-我们知道inode结构体中，对于设备文件的设备号会被保存到其成员i_rdev中。在chr_dev_open函数中，我们使用宏定义MINOR来获取该设备文件的次设备号，使用private_data指向各自的数据缓冲区。对于次设备号为0的设备，负责管理vbuf1的数据，对于次设备号为1的设备，则用于管理
-vbuf2的数据，这样就实现了同一个设备驱动，管理多个设备了。接下来，我们的驱动只需要对private_data进行读写即可。
-
-代码清单 57‑30 chr_dev_write函数（位于文件chrdev.c）
-
-1 static ssize_t chr_dev_write(struct file \*filp, const char \__user \* buf, size_t count, loff_t \*ppos)
-
-2 {
-
-3 unsigned long p = \*ppos;
-
-4 int ret;
-
-5 char \*vbuf = filp->private_data;
-
-6 int tmp = count ;
-
-7 if (p > BUFF_SIZE)
-
-8 return 0;
-
-9 if (tmp > BUFF_SIZE - p)
-
-10 tmp = BUFF_SIZE - p;
-
-11 ret = copy_from_user(vbuf, buf, tmp);
-
-12 \*ppos += tmp;
-
-13 return tmp;
-
-14 }
-
-可以看到，我们的chr_dev_write函数改动很小，只是增加了第5行的代码，将原先vbuf数据指向了private_data，这样的话，当我们往次设备号为0的设备写数据时，就会往vbuf1中写入数据。次设备号为1的设备写数据，也是同样的道理。
-
-代码清单 57‑31 chr_dev_read函数（位于文件chrdev.c）
-
-1 static ssize_t chr_dev_read(struct file \*filp, char \__user \* buf, size_t count, loff_t \*ppos)
-
-2 {
-
-3 unsigned long p = \*ppos;
-
-4 int ret;
-
-5 int tmp = count ;
-
-6 char \*vbuf = filp->private_data;
-
-7 if (p >= BUFF_SIZE)
-
-8 return 0;
-
-9 if (tmp > BUFF_SIZE - p)
-
-10 tmp = BUFF_SIZE - p;
-
-11 ret = copy_to_user(buf, vbuf+p, tmp);
-
-12 \*ppos +=tmp;
-
-13 return tmp;
-
-14 }
+**本章的示例代码目录为：base_code/linux_driver/1_SupportMoreDev/chrdev.c**
+
+.. code-block:: c
+   :caption: chrdev.c修改部分（位于../base_code/linux_driver/1_SupportMoreDev/chrdev.c）
+   :linenos:
+
+   #define DEV_NAME "EmbedCharDev"
+   #define DEV_CNT (2) (1)
+   #define BUFF_SIZE 128
+   //定义字符设备的设备号
+   static dev_t devno;
+   //定义字符设备结构体chr_dev
+   static struct cdev chr_dev;
+   //数据缓冲区
+   static char vbuf1[BUFF_SIZE]; (2)
+    static char vbuf2[BUFF_SIZE]; (3)
+
+以上代码中，（1）处修改了宏定义DEV_CNT，将原本的个数1改为2，这样的话，我们的驱动程序便可以管
+理两个设备。（2）~（3）处修改为两个数据缓冲区。
+
+
+
+.. code-block:: c
+   :caption: chr_dev_open函数修改（位于../base_code/linux_driver/1_SupportMoreDev/chrdev.c）
+   :linenos:
+
+   static int chr_dev_open(struct inode *inode, struct file *filp)
+   {
+   printk("\nopen\n ");
+   switch (MINOR(inode->i_rdev)) {
+   case 0 : {
+   filp->private_data = vbuf1;
+   break;
+   }
+   case 1 : {
+    filp->private_data = vbuf2;
+    break;
+    }
+    }
+    return 0;
+    }
+
+我们知道inode结构体中，对于设备文件的设备号会被保存到
+其成员i_rdev中。在chr_dev_open函数中，我们使用宏定义MINOR来获
+取该设备文件的次设备号，使用private_data指向各自的数据缓冲区。对于
+次设备号为0的设备，负责管理vbuf1的数据，对于次设备号为1的设备，则用于管理
+vbuf2的数据，这样就实现了同一个设备驱动，管理多个设备了。接下来，我们
+的驱动只需要对private_data进行读写即可。
+
+
+.. code-block:: c
+   :caption: chr_dev_write函数（位于../base_code/linux_driver/1_SupportMoreDev/chrdev.c）
+   :linenos:
+
+   static ssize_t chr_dev_write(struct file *filp, const char __user * buf, size_t count, loff_t *ppos)
+   {
+   unsigned long p = *ppos;
+   int ret;
+   char *vbuf = filp->private_data;
+   int tmp = count ;
+   if (p > BUFF_SIZE)
+   return 0;
+   if (tmp > BUFF_SIZE - p)
+    tmp = BUFF_SIZE - p;
+    ret = copy_from_user(vbuf, buf, tmp);
+    *ppos += tmp;
+    return tmp;
+    }
+
+可以看到，我们的chr_dev_write函数改动很小，只是增加了第5行的代码，将原
+先vbuf数据指向了private_data，这样的话，当我们往次设备号为0的设备写数据
+时，就会往vbuf1中写入数据。次设备号为1的设备写数据，也是同样的道理。
+
+
+
+.. code-block:: c
+   :caption: chr_dev_read函数（位于../base_code/linux_driver/1_SupportMoreDev/chrdev.c）
+   :linenos:
+
+   static ssize_t chr_dev_read(struct file *filp, char __user * buf, size_t count, loff_t *ppos)
+   {
+   unsigned long p = *ppos;
+   int ret;
+   int tmp = count ;
+   char *vbuf = filp->private_data;
+   if (p >= BUFF_SIZE)
+   return 0;
+   if (tmp > BUFF_SIZE - p)
+    tmp = BUFF_SIZE - p;
+    ret = copy_to_user(buf, vbuf+p, tmp);
+    *ppos +=tmp;
+    return tmp;
+    }
 
 同样的，chr_dev_read函数也只是增加了第6行的代码，将原先的vbuf指向了private_data成员。
 
-至于Makefile文件，与上一小节的相同，这里便不再罗列出来了。下面我们使用cat以及echo命令，对我们的驱动程序进行测试。
+至于Makefile文件，与上一小节的相同，这里便不再罗列出来了。下面我们
+使用cat以及echo命令，对我们的驱动程序进行测试。
 
 insmod chrdev.ko
 
@@ -1099,244 +1018,209 @@ mknod /dev/chrdev1 c 248 0
 
 mknod /dev/chrdev2 c 248 1
 
-通过以上命令，加载了新的内核模块，同时创建了两个新的字符设备，分别是/dev/chrdev1和/dev/chrdev2，开始进行读写测试：
+通过以上命令，加载了新的内核模块，同时创建了两个新的字符设备，分
+别是/dev/chrdev1和/dev/chrdev2，开始进行读写测试：
 
-echo “hello world” > /dev/chrdev1
+echo "hello world" > /dev/chrdev1
 
-echo “123456” > /dev/chrdev2
+echo "123456" > /dev/chrdev2
 
 cat /dev/chrdev1
 
 cat /dev/chrdev2
 
-|charac011|
-
-图 57‑9 实验结果
-
-可以看到设备chrdev1中保存了字符串“hello world”，而设备chrdev2中保存了字符串“123456”。只需要几行代码，就可以实现一个驱动程序，控制多个设备。
-
-我们回忆一下，我们前面讲到的文件节点inode中的成员i_cdev，为了方便访问设备文件，在打开文件过程中，将对应的字符设备结构体cdev保存到该变量中，那么我们也可以通过该变量来做文章。
-
-代码清单 57‑32 定义设备（文件main.c）
-
-1 //虚拟字符设备
-
-2 struct chr_dev {
-
-3 struct cdev dev;
-
-4 char vbuf[BUFF_SIZE];
-
-5 };
-
-6 //字符设备1
-
-7 static struct chr_dev vcdev1;
-
-8 //字符设备2
-
-9 static struct chr_dev vcdev2;
-
-代码清单 57‑32中定义了一个新的结构体struct chr_dev，它有两个结构体成员：字符设备结构体dev以及设备对应的数据缓冲区。使用新的结构体类型struct chr_dev定义两个虚拟设备vcdev1以及vcdev2。
-
-代码清单 57‑33 chrdev_init函数（文件main.c）
-
-1 static int \__init chrdev_init(void)
-
-2 {
-
-3 int ret;
-
-4 printk("4 chrdev init\n");
-
-5 ret = alloc_chrdev_region(&devno, 0, DEV_CNT, DEV_NAME);
-
-6 if (ret < 0)
-
-7 goto alloc_err;
-
-8
-
-9 //关联第一个设备：vdev1
-
-10 cdev_init(&vcdev1.dev, &chr_dev_fops);
-
-11 ret = cdev_add(&vcdev1.dev, devno+0, 1);
-
-12 if (ret < 0) {
-
-13 printk("fail to add vcdev1 ");
-
-14 goto add_err1;
-
-15 }
-
-16 //关联第二个设备：vdev2
-
-17 cdev_init(&vcdev2.dev, &chr_dev_fops);
-
-18 ret = cdev_add(&vcdev2.dev, devno+1, 1);
-
-19 if (ret < 0) {
-
-20 printk("fail to add vcdev2 ");
-
-21 goto add_err2;
-
-22 }
-
-23 return 0;
-
-24 add_err2:
-
-25 cdev_del(&(vcdev1.dev));
-
-26 add_err1:
-
-27 unregister_chrdev_region(devno, DEV_CNT);
-
-28 alloc_err:
-
-29 return ret;
-
-30
-
-31 }
-
-chrdev_init函数的框架仍然没有什么变化。只不过，在添加字符设备时，使用cdev_add依次添加。注意，当虚拟设备1添加失败时，直接返回的时候，只需要注销申请到的设备号即可。若虚拟设备2添加失败，则需要把虚拟设备1移动，再将申请的设备号注销。
-
-代码清单 57‑34 chrdev_exit函数（文件main.c）
-
-1 static void \__exit chrdev_exit(void)
-
-2 {
-
-3 printk("chrdev exit\n");
-
-4 unregister_chrdev_region(devno, DEV_CNT);
-
-5 cdev_del(&(vcdev1.dev));
-
-6 cdev_del(&(vcdev2.dev));
-
-7 }
+.. image:: media/charac011.jpg
+   :align: center
+   :alt: 未找到图片11|
+
+
+
+可以看到设备chrdev1中保存了字符串"hello world"，而设
+备chrdev2中保存了字符串"123456"。只需要几行代码，就可以实现一个驱动程序，控制多个设备。
+
+我们回忆一下，我们前面讲到的文件节点inode中的成员i_cdev，为了
+方便访问设备文件，在打开文件过程中，将对应的字符设备结构体cdev保
+存到该变量中，那么我们也可以通过该变量来做文章。
+
+**本章的示例代码目录为：base_code/linux_driver/2_SupportMoreDev/chrdev.c**
+
+.. code-block:: c
+   :caption: 定义设备（位于../base_code/linux_driver/2_SupportMoreDev/chrdev.c）
+   :linenos:
+
+   /*虚拟字符设备*/
+   struct chr_dev {
+   struct cdev dev;
+   char vbuf[BUFF_SIZE];
+   };
+   //字符设备1
+   static struct chr_dev vcdev1;
+   //字符设备2
+   static struct chr_dev vcdev2;
+
+以上代码中定义了一个新的结构体struct chr_dev，它有两个结
+构体成员：字符设备结构体dev以及设备对应的数据缓冲区。使用新的结构
+体类型struct chr_dev定义两个虚拟设备vcdev1以及vcdev2。
+
+
+
+.. code-block:: c
+   :caption: chrdev_init函数（位于../base_code/linux_driver/2_SupportMoreDev/chrdev.c）
+   :linenos:
+
+   static int __init chrdev_init(void)
+   {
+   int ret;
+   printk("4 chrdev init\n");
+   ret = alloc_chrdev_region(&devno, 0, DEV_CNT, DEV_NAME);
+   if (ret < 0)
+   goto alloc_err;
+   //关联第一个设备：vdev1
+    cdev_init(&vcdev1.dev, &chr_dev_fops);
+    ret = cdev_add(&vcdev1.dev, devno+0, 1);
+    if (ret < 0) {
+    printk("fail to add vcdev1 ");
+    goto add_err1;
+    }
+    //关联第二个设备：vdev2
+    cdev_init(&vcdev2.dev, &chr_dev_fops);
+    ret = cdev_add(&vcdev2.dev, devno+1, 1);
+    if (ret < 0) {
+    printk("fail to add vcdev2 ");
+    goto add_err2;
+    }
+    return 0;
+    add_err2:
+    cdev_del(&(vcdev1.dev));
+    add_err1:
+    unregister_chrdev_region(devno, DEV_CNT);
+    alloc_err:
+    return ret;
+   
+    }
+
+chrdev_init函数的框架仍然没有什么变化。只不过，在添加字符设备时，使
+用cdev_add依次添加。注意，当虚拟设备1添加失败时，直接返回的时候，只需要
+注销申请到的设备号即可。若虚拟设备2添加失败，则需要把虚拟设备1移动，再将申请的设备号注销。
+
+
+
+.. code-block:: c
+   :caption: chrdev_exit函数（位于../base_code/linux_driver/2_SupportMoreDev/chrdev.c）
+   :linenos:
+
+   static void __exit chrdev_exit(void)
+   {
+   printk("chrdev exit\n");
+   unregister_chrdev_region(devno, DEV_CNT);
+   cdev_del(&(vcdev1.dev));
+   cdev_del(&(vcdev2.dev));
+   }
 
 chrdev_exit函数注销了申请到的设备号，使用cdev_del移动两个虚拟设备。
 
-代码清单 57‑35 chr_dev_open以及chr_dev_release函数（文件main.c）
-
-1 static int chr_dev_open(struct inode \*inode, struct file \*filp)
-
-2 {
-
-3 printk("open\n");
 
-4 filp->private_data = container_of(inode->i_cdev, struct chr_dev, dev);
 
-5 return 0;
-
-6 }
-
-7
-
-8 static int chr_dev_release(struct inode \*inode, struct file \*filp)
-
-9 {
-
-10 printk("release\n");
-
-11 return 0;
-
-12 }
-
-我们知道inode中的i_cdev成员保存了对应字符设备结构体的地址，但是我们的虚拟设备是把cdev封装起来的一个结构体，我们要如何能够得到虚拟设备的数据缓冲区呢？为此，Linux提供了一个宏定义container_of，该宏可以根据结构体的某个成员的地址，来得到该结构体的地址。该宏需要三个参数，分
-别是代表结构体成员的真实地址，结构体的类型以及结构体成员的名字。在chr_dev_open函数中，我们需要通过inode的i_cdev成员，来得到对应的虚拟设备结构体，并保存到文件指针filp的私有数据成员中。假如，我们打开虚拟设备1，那么inode->i_cdev便指向了vcdev1的成员dev，
+.. code-block:: c
+   :caption: chr_dev_open以及chr_dev_release函数（位于../base_code/linux_driver/2_SupportMoreDev/chrdev.c）
+   :linenos:
+
+   static int chr_dev_open(struct inode *inode, struct file *filp)
+   {
+   printk("open\n");
+   filp->private_data = container_of(inode->i_cdev, struct chr_dev, dev);
+   return 0;
+   }
+   static int chr_dev_release(struct inode *inode, struct file *filp)
+   {
+    printk("release\n");
+    return 0;
+    }
+
+我们知道inode中的i_cdev成员保存了对应字符设备结构体的地址，但是我们的虚
+拟设备是把cdev封装起来的一个结构体，我们要如何能够得到虚拟设备的数
+据缓冲区呢？为此，Linux提供了一个宏定义container_of，该宏可以根
+据结构体的某个成员的地址，来得到该结构体的地址。该宏需要三个参数，分
+别是代表结构体成员的真实地址，结构体的类型以及结构体成员的名
+字。在chr_dev_open函数中，我们需要通过inode的i_cdev成员，来得
+到对应的虚拟设备结构体，并保存到文件指针filp的私有数据成员中。假如，我
+们打开虚拟设备1，那么inode->i_cdev便指向了vcdev1的成员dev，
 利用container_of宏，我们就可以得到vcdev1结构体的地址，也就可以操作对应的数据缓冲区了。
 
-代码清单 57‑36 chr_dev_write函数（文件main.c）
-
-1 static ssize_t chr_dev_write(struct file \*filp, const char \__user \* buf, size_t count, loff_t \*ppos)
-
-2 {
-
-3 unsigned long p = \*ppos;
-
-4 int ret;
-
-5 //获取文件的私有数据
 
-6 struct chr_dev \*dev = filp->private_data;
 
-7 char \*vbuf = dev->vbuf;
+.. code-block:: c
+   :caption: chr_dev_write函数（位于../base_code/linux_driver/2_SupportMoreDev/chrdev.c）
+   :linenos:
+
+   static ssize_t chr_dev_write(struct file *filp, const char __user * buf, size_t count, loff_t *ppos)
+   {
+   unsigned long p = *ppos;
+   int ret;
+   //获取文件的私有数据
+   struct chr_dev *dev = filp->private_data;
+   char *vbuf = dev->vbuf;
+   int tmp = count ;
+    if (p > BUFF_SIZE)
+    return 0;
+    if (tmp > BUFF_SIZE - p)
+    tmp = BUFF_SIZE - p;
+    ret = copy_from_user(vbuf, buf, tmp);
+    *ppos += tmp;
+    return tmp;
+    }
+
+对比第一种方法，实际上只是新增了第6行代码，通过文件指针filp的成
+员private_data得到相应的虚拟设备。修改第7行的代码，定义了char类型的指
+针变量，指向对应设备的数据缓冲区。
+
+
+
+.. code-block:: c
+   :caption: chr_dev_read函数（位于../base_code/linux_driver/2_SupportMoreDev/chrdev.c）
+   :linenos:
+
+   static ssize_t chr_dev_read(struct file *filp, char __user * buf, size_t count, loff_t *ppos)
+   {
+   unsigned long p = *ppos;
+   int ret;
+   int tmp = count ;
+   //获取文件的私有数据
+   struct chr_dev *dev = filp->private_data;
+   char *vbuf = dev->vbuf;
+   if (p >= BUFF_SIZE)
+    return 0;
+    if (tmp > BUFF_SIZE - p)
+    tmp = BUFF_SIZE - p;
+    ret = copy_to_user(buf, vbuf+p, tmp);
+    *ppos +=tmp;
+    return tmp;
+    }
 
-8
-
-9 int tmp = count ;
-
-10 if (p > BUFF_SIZE)
-
-11 return 0;
-
-12 if (tmp > BUFF_SIZE - p)
-
-13 tmp = BUFF_SIZE - p;
-
-14 ret = copy_from_user(vbuf, buf, tmp);
-
-15 \*ppos += tmp;
-
-16 return tmp;
-
-17 }
-
-对比第一种方法，实际上只是新增了第6行代码，通过文件指针filp的成员private_data得到相应的虚拟设备。修改第7行的代码，定义了char类型的指针变量，指向对应设备的数据缓冲区。
-
-代码清单 57‑37 chr_dev_read函数（文件main.c）
-
-1 static ssize_t chr_dev_read(struct file \*filp, char \__user \* buf, size_t count, loff_t \*ppos)
-
-2 {
-
-3 unsigned long p = \*ppos;
-
-4 int ret;
-
-5 int tmp = count ;
-
-6 //获取文件的私有数据
-
-7 struct chr_dev \*dev = filp->private_data;
-
-8 char \*vbuf = dev->vbuf;
-
-9 if (p >= BUFF_SIZE)
-
-10 return 0;
-
-11 if (tmp > BUFF_SIZE - p)
-
-12 tmp = BUFF_SIZE - p;
-
-13 ret = copy_to_user(buf, vbuf+p, tmp);
+读函数，与写函数的改动部分基本一致，这里就只贴出代码，不进行讲解。
 
-14 \*ppos +=tmp;
+.. image:: media/charac012.jpg
+   :align: center
+   :alt: 未找到图片12|
 
-15 return tmp;
 
-16 }
 
-读函数，与写函数的改动部分基本一致，这里就只贴出代码，不进行讲解。
+我们往两个数据缓冲区分别写入"HelloWorld"以及"DemoTest"字符串，然
+后使用cat命令来读取设备，实验结果见上图。
 
-|charac012|
+总结一下，一个驱动支持多个设备的具体实现方式的重点在于如
+何运用file的私有数据成员。第一种方法是通过将各自的数据缓冲区放
+到该成员中，在读写函数的时候，直接就可以对相应的数据缓冲区进行
+操作；第二种方法则是通过将我们的数据缓冲区和字符设备结构体封装到一
+起，由于文件结构体inode的成员i_cdev保存
+了对应字符设备结构体，使用container_of宏便可以获得封装后的结构
+体的地址，进而得到相应的数据缓冲区。
 
-图 57‑10 实验结果
+到这里，字符设备驱动就已经讲解完毕了。如果你发现自己有
+好多不理解的地方，学完本章之后，建议重新梳理一下整个过程，有助于加深对整个字符设备驱动框架的理解。
 
-我们往两个数据缓冲区分别写入“HelloWorld”以及“DemoTest”字符串，然后使用cat命令来读取设备，实验结果见图 57‑10。
 
-总结一下，一个驱动支持多个设备的具体实现方式的重点在于如何运用file的私有数据成员。第一种方法是通过将各自的数据缓冲区放到该成员中，在读写函数的时候，直接就可以对相应的数据缓冲区进行操作；第二种方法则是通过将我们的数据缓冲区和字符设备结构体封装到一起，由于文件结构体inode的成员i_cdev保存
-了对应字符设备结构体，使用container_of宏便可以获得封装后的结构体的地址，进而得到相应的数据缓冲区。
 
-到这里，字符设备驱动就已经讲解完毕了。如果你在阅读57.2 时，发现自己有好多不理解的地方，学完本章之后，建议重新梳理一下整个过程，有助于加深对整个字符设备驱动框架的理解。
 
 .. |charac002| image:: media/charac002.jpg
    :width: 5.6482in
diff --git a/documentation/linux_driver/concurrency.rst b/documentation/linux_driver/concurrency.rst
new file mode 100644
index 0000000000000000000000000000000000000000..e15ae0250adac2e9e375716784adc2671e5440cf
--- /dev/null
+++ b/documentation/linux_driver/concurrency.rst
@@ -0,0 +1,1087 @@
+.. vim: syntax=rst
+
+linux驱动并发与竞态
+------------
+
+并发是指多个执行单元同时并行执行，这些并行执行单元访问共享资源容易造成竞态。对于多核系统，很容理解，由于多个CPU同时执行，多个CPU同时读、写共享资源时很容易造成竞态。对于单核系统（例如我们的i.mx6ull）虽然没有真正的“并行”执行，但是linux系统是多任务系统，linux2.6以及更高版本
+的内核是抢占式内核，高优先级的任务可以打断低优先级的任务，再加上中断的存在在单核系统中同样存在竞态的问题。
+
+竞态的产生
+~~~~~
+
+竞态的定义是在某种情况下各个执行单元以一种没有逻辑的顺序执行动作，从而导致意想不到的结果。对应到我们的linux系统就是多个线程对共享资源以一种没有逻辑的顺序访问，从而造成未知错误。
+
+从竞态的定义可知，竞态产生需要两个条件，第一，共享资源，第二，没有逻辑的顺序访问。
+
+什么是共享资源。在linux系统中可被多个线程访问的内容都可被称为共享资源，比如一个文件、一块内存、全局变量。在linux系统中一切皆文件，我们编写的驱动在系统中对应一个设备节点文件，从应用程序角度看，驱动也是共享资源。
+
+什么是没有逻辑的顺序访问。对于单核linux系统主要表现为抢占式内核以及中断。linux2.6及更高版本引入了抢占式内核，高优先级的任务可以打断低优先级的任务。大多数ARM处理器支持中断。
+
+以文件读写为例简单理解竞态的产生过程，如下图所示
+
+.. image:: ./media/concur002.png
+   :align: center
+   :alt: 竞态02|
+
+假设进程A和进程B不断的读取、转换同一传感器传回的数据，并将结果记录到test.txt文件，B进程优先级高于A进程。假设A进程得到的是“601”，B进程得到的是“602”。正常情况下test.txt文件新增两条记录“601”和“602”。但是在A进程写入“602”过程中B进程准备就绪将A进程打断，然
+后在test.txt文件中写入“601”B进程退出后A进程继续写入，最终test.txt文件中增加的两条数据可能是“60602”“1”。
+
+竞态的解决方法
+~~~~~~~
+
+解决“竞态”的最终目的是保护共享资源不被无序访问。根据共享资源的种类以及实际应用场景我们有多种解决方法可选，常用的几种方式介绍如下，后面章节将会结合实际代码详细介绍其使用方法。
+
+1. 原子操作
+
+..
+
+   “原子”的定义是“化学反应不可再分的基本微粒”，“原子操作”可以理解为“不可拆分的操作”。原子操作用于保护对一个整型数据的修改是不可分割的。它的实现与CPU架构相关，不再介绍。原子操作进一步细分为“整型原子操作”和“位原子操作”，两者都只能保护“整型”数据。
+
+2. 自旋锁
+
+..
+
+   自旋锁是实现互斥访问的常用手段，在一些实时操作系统中也经常用到。自旋锁主要操作分为定义自旋锁、初始化自旋锁、获取自旋锁、释放自旋锁。 “自旋锁”的作用是给一段代码“加锁”。获取自旋锁成功后才能运行被保护的代码，运行结束后释放自旋锁。“自旋”是指获取自旋锁失败后轮询检测锁的状态，直到自旋锁被释放。
+
+   自旋锁的缺点是自旋锁失败后会循环检测自旋锁的状态，占用系统资源。优点是实现简单、不需要休眠、可以在中断中使用。
+
+3. 信号量
+
+..
+
+   信号量的使用一般分为定义信号量、初始化信号量、尝试获取信号量、获取信号量和释放信号量。对比“自旋锁”使用方法差异不大，两者差异主要表现在申请失败后的处理方式，自旋锁申请失败后会轮询检测锁的状态，而信号量申请失败后进程可引入休眠，当信号量可用时由系统通知进程退出休眠。
+
+   由于信号量无需轮询检测信号量状态所以它不会造成系统资源的浪费，缺点是会引起进程的休眠所以不能在中断中使用。信号量的“量值”可以是多个所以它可以同时保护多个资源。例如有5个缓冲区，使用信号量时将“量值”设置为5每获取一次“量值”减一，释放一次“量值”加一。
+
+4. 互斥体
+
+..
+
+   互斥体可以说是“量值”为1的信号量。把信号量的“量值”设置为1就行了为什么还要引入互斥体呢？，很简单，虽然两者功能相同但是具体实现不同，互斥体效率更高。在使用信号量时，如果“量值”为1，考虑到效率，我们一般将其改为使用互斥体实现。
+
+原子操作函数（宏定义）以及测试实验
+~~~~~~~~~~~~~~~~~
+
+原子操作分为整型原子操作和位原子操作。使用方法非常类似，本小节介绍分别
+介绍整型原子操作和位原子操作的函数（确切的说某些是宏定义）。测试实验仅
+用整型原子操作，读者可自行使用位原子操作实现,实验源码位于“~/base_code/linux_driver/concurrency/atomic”。
+
+整型原子操作函数（宏定义）介绍
+^^^^^^^^^^^^^^^
+
+1. 定义整型原子变量并设置初始值
+
+.. code-block:: c
+
+   atomic_t data = ATOMIC_INIT(int i)
+
+**说明**：
+
+**atomic_t**：暂且称为“整型原子类型”，我们用它定义整型原子变量。
+
+**ATOMIC_INIT**：这是一个宏定义，用于定义整型原子变量并设置它的初始值。
+
+2. 设置整型原子变量的值
+
+.. code-block:: c
+
+   atomic_set(atomic_t\* v,int i)
+
+**说明**：
+
+**atomic_set**：这是一个宏定义，用于设置整型原子变量的值。
+
+**v**：要设置的整型原子变量的指针（地址）。
+
+**i**: 设置的值。
+
+3. 获取原子变量的值
+
+.. code-block:: c
+
+   #define atomic_read(v) ACCESS_ONCE((v)->counter)
+
+忽略宏定义的具体实现，获取原子变量的宏定义如下所示：
+
+.. code-block:: c
+
+   atomic_read(atomic_t\* v)
+
+**说明**：
+
+**v**：要获取的整型原子变量的指针。
+
+4. 整型原子变量的加/减
+
+.. code-block:: c
+
+   static inline void atomic_add(int i, atomic_t \*v) //整型原子变量加i
+   static inline void atomic_sub(int i, atomic_t \*v) //整型原子变量减i
+
+5. 整型原子变量自增/自减
+
+.. code-block:: c
+
+   static inline void atomic_inc(atomic_t \*v) //整型原子变量自增1
+   static inline void atomic_dec(atomic_t \*v)//整型原子变量自减1
+
+6. 整型原子变量操作返回函数（宏定义）
+
+.. code-block:: c
+
+   int atomic_sub_return(int i, atomic_t \*v) //返回增加后的结果
+   int atomic_sub_return(int i, atomic_t \*v) //返回减少后的结果
+   #define atomic_dec_return(v) atomic_sub_return(1, (v)) //返回自减1的结
+   #define atomic_inc_return(v) atomic_add_return(1, (v))//返回自增1的结果
+
+7. 整型原子变量测试函数（宏定义）
+
+.. code-block:: c
+
+   /*整型原子变量减i后是否为0*/
+   #define atomic_sub_and_test(i, v) (atomic_sub_return((i), (v)) == 0)
+   /*整型原子变量自减1后是否为0*/
+   #define atomic_dec_and_test(v) (atomic_dec_return(v) == 0)
+   /*整型原子变量自加1后是否为0*/
+   #define atomic_inc_and_test(v) (atomic_inc_return(v) == 0)
+
+位原子操作函数（宏定义）介绍。
+^^^^^^^^^^^^^^^
+
+1. 设置位
+
+.. code-block:: c
+
+   set_bit(int nr, unsigned long \*addr)
+
+**说明**：
+
+**addr**：指定要设置的地址。
+
+**nr**：指定设置哪一位 ，如果地址指定的数据是32位的，那么nr可取0~31。
+
+设置位的含义是将某一位置1，对比清除位。
+
+2. 清除位
+
+.. code-block:: c
+
+   clear_bit(int nr, unsigned long \*addr)
+
+**说明**：
+
+与set_bit函数类似。
+
+3. 改变位
+
+.. code-block:: c
+
+   change_bit(int nr, unsigned long \*addr)
+
+改变位就是反转某一位的值，是0就变为1，是1就变为0。
+
+4. 测试位
+
+.. code-block:: c
+
+   int test_bit(int nr, unsigned long \*addr)
+
+返回nr 位的值
+
+5. 测试并操作位
+
+.. code-block:: c
+
+   /*测试并设置位*/
+
+   int test_and_set_bit(int nr, volatile unsigned long \*addr)
+   /*测试并清除位*/
+   int test_and_clear_bit(int nr, volatile unsigned long \*addr)
+   /*测试并反转位*/
+   int test_and_change_bit(int nr, volatile unsigned long \*addr)
+
+上述函数等同于先执行test_bit函数然后再执行xxx_bit函数（xxx,指 set、clear、change）
+
+原子操作函数（宏定义）很多，但是非常简单，特别注意的是在程序中要使用以上提供的函数实现想要的工功能，切记不能自行使用“+”、“-”等等操作原子操作数。
+
+整型原子操作实验
+^^^^^^^^
+
+本实验使用整型原子变量保护驱动程序不被多次打开，既驱动打开一次之后，在退
+出之前其他进程无法再次打开驱动。实验在“~/base_code/linux_driver/led_cdev”字符设备驱动基础上修改得到，修改的主要的内容
+包括在在驱动中添加整型原子操作、添加测试应用程序。修改完成后的源码位于“~/base_code/linux_driver/concurrency/atomic”
+
+修改驱动程序
+''''''
+
+只需要在驱动程序的.open和.release函数中添加整型原子相关操作即可，修改之后的源码如下所示（省略了大量未修改的代码）。
+
+
+.. code-block:: c
+   :caption: 驱动程序修改内容
+   :linenos:  
+
+   /*---------------以下代码省略-----------------*/
+   
+   /*---------------第一部分-----------------*/
+   static atomic_t test_atomic = ATOMIC_INIT(1);
+   
+   static int led_chrdev_open(struct inode *inode, struct file *filp)
+   {
+   
+       /*---------------以下代码省略-----------------*/
+   
+       /*---------------第二部分-----------------*/
+   
+   	if(atomic_read(&test_atomic))
+   	{
+   		atomic_set(&test_atomic,0);
+   	}
+       else
+       {
+   		printk("\n driver on using!  open failed !!!\n");
+   		return - EBUSY;
+       }
+       
+       
+   	printk("open \n");
+       /*---------------以下代码省略-----------------*/
+   
+   	return 0;
+   }
+   
+   static int led_chrdev_release(struct inode *inode, struct file *filp)
+   {
+       /*---------------以下代码省略-----------------*/
+   
+       /*---------------第三部分-----------------*/
+       atomic_set(&test_atomic,1);
+   	printk("\n finished  !!!\n");
+   
+   	return 0;
+   }
+   
+   
+   static struct file_operations led_chrdev_fops = {
+   	.owner = THIS_MODULE,
+   	.open = led_chrdev_open,
+   	.release = led_chrdev_release,
+   	.write = led_chrdev_write,
+   };
+
+
+相比原驱动，修改内容很少。结合代码介绍如下：
+
+第一部分，定义并初始化整型原子变量。初始值设置为1，表示驱动还未被占用。
+
+第二部分，在.open函数的开始处添加多整型原子变量值的检测，如果为1则将其设置为0（表示驱动已经被占用）并继续正常运行。否则输出提示信息“driver on using! open failed !!!”并返回 “- EBUSY”错误码表示驱动已经被打开并且没有退出。
+
+第三部分，在.release函数的末尾使用atomic_set将整型原子变量的值重新设置为1，表示已经退出。
+
+编译驱动程序：
+
+编译命令：
+
+.. code-block:: c
+
+   make ARCH=arm CROSS_COMPILE=arm-linux-gnueabihf-
+
+编写测试应用程序
+''''''''
+
+测试应用程序的目的是验证整型原子变量能否保护驱动程序不被多次打开。测试程序源码如下所示，完整内容请参考本小节配套例程。
+
+
+.. code-block:: c
+   :caption: 整型原子变量测试应用程序
+   :linenos:  
+
+   int main(int argc, char *argv[])
+   {
+   
+       /*--------------第一部分---------------*/
+       /*判断输入的命令是否合法*/
+       if(argc != 2)
+       {
+           printf(" commend error ! \n");
+           return -1;
+       }
+   
+       /*--------------第二部分---------------*/
+       /*打开文件*/
+       int fd = open("/dev/led_chrdev0", O_RDWR);
+       if(fd < 0)
+       {
+   		printf("open file : %s failed !\n", argv[0]);
+   		return -1;
+   	}
+       
+       /*--------------第三部分---------------*/
+       /*判断命令的有效性*/
+       /*写入命令*/
+       int error = write(fd,argv[1],sizeof(argv[1]));
+       if(error < 0)
+       {
+           printf("write file error! \n");
+           close(fd);
+           /*判断是否关闭成功*/
+       }
+   
+       /*--------------第四部分---------------*/
+       sleep(15);  //休眠5秒
+   
+       /*关闭文件*/
+       error = close(fd);
+       if(error < 0)
+       {
+           printf("close file error! \n");
+       }
+       return 0;
+   }
+
+代码大致分为四部分，介绍如下：
+
+第一部分，检测输入的命令是否合法，在运行应用程序时需要传递一个参数，格式是“./<应用程序路径> <参数>”。为简化代码这里只是检测输入的命令长度是否为2。
+
+第二部分，打开led灯的设备节点文件。在驱动中我们使用一个主设备号和三个次设备号三个LED灯的设备节点文件是独立的，我们这里只使用红灯的设备节点文件“led_chrdev0”
+
+第三部分，使用“write”函数写入命令。
+
+第四部分，休眠15秒。休眠的目的是模拟驱动程序正在被使用，休眠时间可根据需要自己设定。
+
+编译应用程序：
+
+编译命令：
+
+.. code-block:: c
+
+   arm-linux-gnueabihf-gcc <源文件路径> -o <输出文件名>
+
+以本实验为例，源文件名“main.c”则在源码目录下的编译命令为：
+
+.. code-block:: c
+
+   arm-linux-gnueabihf-gcc ./main.c -o main
+
+下载验证
+''''
+
+将前两小节编译得到的驱动程序和应用程序拷贝到开发板中。（推荐使用NFS共享文件夹，如果无法连接开发板和电脑可以先将程序拷贝到U盘或者SD卡，然后再将它们挂载到开发板）。
+
+加载驱动程序
+
+
+以本章配套源码为例，加载命令：
+
+.. code-block:: c
+
+   insmod ./led_cdev.ko
+
+运行应用程序开始测试
+
+
+我们的目的是测试驱动程序能否被打开两次，首先在后台运行应用程序“./main 0 &”，这个程序将会运行15秒，在十五秒之内再次运行“./main 1 &”，正常情况下由于第一次程序还没有退出第二次会打开失败。实际实现现象如下所示。
+
+1. 在后台运行测试应用程序并点亮led灯
+
+命令：
+
+.. code-block:: c
+
+   ./main 0 &
+
+执行结果如下所示：
+
+.. image:: ./media/concur003.png
+   :align: center
+   :alt: 竞态03|
+
+2. 在上一个应用程序退出之前再次运行应用程序
+
+命令：
+
+.. code-block:: c
+
+   ./main 1
+
+执行结果如下所示：
+
+.. image:: ./media/concur004.png
+   :align: center
+   :alt: 竞态04|
+
+3. 等待应用程序运行结束。
+
+.. image:: ./media/concur005.png
+   :align: center
+   :alt: 竞态05|
+
+4. 等待结束后再次运行应用程序
+
+命令：
+
+.. image:: ./media/concur006.png
+   :align: center
+   :alt: 竞态06|
+
+从上面实验可以看出，第一次运行的应用程序释放驱动之前其他
+线程是无法打开驱动的。实现了我们的预定目标。
+
+自旋锁操作函数（宏定义）及实验
+~~~~~~~~~~~~~~~
+
+和整型原子变量类似，linux提供了一系列函数（宏定义）来操作自
+旋锁。我们先介绍自旋锁相关的函数然后在整型原子变量实验基础上完成实验。实验源码位于“~/base_code/linux_driver/concurrency/spinlock”
+
+自旋锁相关函数
+^^^^^^^
+
+定义自旋锁
+
+
+变量：
+
+.. code-block:: c
+
+   spinlock_t s_lock ;
+
+**说明：**
+
+spinlock_t，是一个结构体，具体内容我们不必关心，使用自旋锁时定义一个spinlock_t类型的变量即可。
+
+初始化自旋锁
+
+
+函数（宏定义）：
+
+.. code-block:: c
+
+   spin_lock_init(_lock)
+
+**参数：**
+
+\_lock ，spinlock_t类型变量，既我们要初始化的自旋锁。定义自旋锁只用之前首先要使用该函数（宏定义）初始化自旋锁。
+
+获取自旋锁
+
+
+linux提供了两种获得自旋锁的方法，介绍如下：
+
+获取自旋锁函数：
+
+.. code-block:: c
+
+   void spin_lock(spinlock_t \*lock)
+
+获取自旋锁成功则继续向下执行，否则进行将会一直轮询检测直到获取成功。
+
+尝试获取自旋锁函数：
+
+.. code-block:: c
+
+   int spin_trylock(spinlock_t \*lock)
+
+相比获取自旋锁函数，尝试获取自旋锁函数拥有返回值，获取成功返回“true”,获取失败返回“false”。无论结果如何程序都会继续向下执行。
+
+释放自旋锁
+
+
+.. code-block:: c
+
+   void spin_unlock(spinlock_t \*lock)
+
+释放自旋锁函数和获取自旋锁函数一般成对存在。
+
+以上自旋锁操作函数（宏定义）只能解决来自别的CPU和进程间的抢占（抢占式内核），CPU不受控制。简单来说，函数spin_lock只是关闭了linux 内核的抢占调度，并没有关闭中断，如果想要把中断关掉，需要使如下函数。
+
+获取自旋锁并关中断
+
+
+.. code-block:: c
+
+   void spin_lock_irq(spinlock_t \*lock)
+
+此函数相当于同时执行获取自旋锁函数“spin_lock”和关中断函数“local_irq_disable”。
+
+释放自旋锁并开中断
+
+
+.. code-block:: c
+
+   void spin_unlock_irq(spinlock_t \*lock)
+
+此函数与上一个函数“spin_lock_irq”成对存在，用法相似。
+
+获取自旋锁并保存中断状态字
+
+
+.. code-block:: c
+
+   spin_lock_irqsave(lock, flags)
+
+**参数：**
+
+**lock** ,指定自旋锁。
+
+**flags**, 指定中断状态字。
+
+我们还没有介绍中断，该函数不过多介绍，使用到时我们再详细介绍。与它成对使用的函数还有“spin_unlock_irqrestore”释放自旋锁并恢复中断状态字。
+
+自旋锁测试实验
+^^^^^^^
+
+与原子操作实验类似，我们在字符设备驱动基础上完成该实验。修改之前的字符设备
+驱动源码“~/base_code/linux_driver/led_cdev”。修改的主要的内
+容包括在在驱动中添加自旋锁、添加测试应用程序。修改完成后的源
+码位于“~/base_code/linux_driver/concurrency/spinlock”。
+
+修改Makefile文件
+''''''''''''
+
+将源文件名对应的.o文件添加到Makefile中，如下所示。
+
+
+
+.. code-block:: c
+   :caption: Makefile文件
+   :linenos: 
+
+   KERNEL_DIR = /home/fire2/ebf-buster-linux
+   
+   obj-m := spinlock.o
+   
+   all:
+   	$(MAKE) -C $(KERNEL_DIR) M=$(CURDIR) modules
+   	
+   .PHONY:clean
+   clean:
+   	$(MAKE) -C $(KERNEL_DIR) M=$(CURDIR) clean
+   
+   	echo 1 >/dev/led_chrdev0
+
+
+.. _修改驱动程序-1:
+
+修改驱动程序
+''''''
+
+驱动程序修改内容较少，主要包括添加自旋锁、初始化自旋锁以及使用“上锁”、“释放锁”函数
+保护一段代码。源码如下所示（只列出了修改内容，完整源码请参考配套历程）。
+
+
+
+.. code-block:: c
+   :caption: 自旋锁驱动程序修改内容
+   :linenos:  
+
+   #include <linux/init.h>
+   #include <linux/module.h>
+   #include <linux/cdev.h>
+   #include <linux/fs.h>
+   #include <linux/uaccess.h>
+   #include <linux/io.h>
+   #include <linux/delay.h>
+   
+   /*-------------以下代码省略-------------*/
+   
+   /*------------------第一部分修改，定义自旋锁---------------*/
+   /*定义一个自旋锁*/
+   spinlock_t s_lock;
+   
+   static ssize_t led_chrdev_write(struct file *filp, const char __user *buf,
+   								size_t count, loff_t *ppos)
+   {
+   	unsigned long val = 0;
+   	unsigned long ret = 0;
+   	unsigned long i;
+   
+   	int tmp = count;
+   
+   	kstrtoul_from_user(buf, tmp, 10, &ret);
+   	struct led_chrdev *led_cdev = (struct led_chrdev *)filp->private_data;
+   
+   /*------------------第二部分修改，保护“临界”资源 ---------------*/
+   	spin_lock(&s_lock);
+   	for (i = ret; i > 0; i--)
+   	{
+   		printk("the data is %ld \n", i);
+   
+   		/*点亮led 灯*/
+   		val &= ~(0x01 << led_cdev->led_pin);
+   		iowrite32(val, led_cdev->va_dr);
+   		mdelay(100);
+   
+   		/*熄灭led 灯*/
+   		val |= (0x01 << led_cdev->led_pin); 
+   		iowrite32(val, led_cdev->va_dr);
+   		mdelay(100);
+   	}
+   	spin_unlock(&s_lock);
+   
+   
+   	*ppos += tmp;
+   	return tmp;
+   }
+   
+   static struct file_operations led_chrdev_fops = {
+   	.owner = THIS_MODULE,
+   	.open = led_chrdev_open,
+   	.release = led_chrdev_release,
+   	.write = led_chrdev_write,
+   };
+   
+   
+   
+   /*驱动入口*/
+   static __init int led_chrdev_init(void)
+   {
+   	int i = 0;
+   	dev_t cur_dev;
+       /*-------------以下代码省略-------------*/
+   
+   /*------------------第三部分修改，初始化自旋锁 ---------------*/
+   	spin_lock_init(&s_lock);
+   	return 0;
+   }
+
+
+程序中我们修改了三个地方，结合代码介绍如下：
+
+第一部分，定义一个自旋锁。由于自旋锁要被两个进程调用，所有这里使用全局变量定义它。
+
+第三部分，初始化自旋锁。自旋锁初始化放到了驱动程序的进入函数，防止被多次初始化。
+
+第二部分，使用spin_lock函数和spin_unlock函数保护一段代码。根据自旋锁的特性，自旋锁不适合保护哪些耗时的操作，但是为更好的观察实现现象这里使用for循环和延时函数模拟一个耗时的过程，实际程序中不会这么做。这段代码会循环执行“ret”次，ret
+是我们运行应用程序时传入的一个参数，每次循环LED闪烁一次，间隔100ms。
+
+.. _编写测试应用程序-1:
+
+编写测试应用程序
+''''''''
+
+测试应用程序的工作是启动两个线程，然后分别打开led灯设备节点文件“led_chrdev0”和led灯设备节点文件“led_chrdev1”。“led_chrdev0”对应RGB灯的红灯，“led_chrdev1”对应RGB灯的绿灯，它们拥有相同的主设备号，在驱动中共用“.write”函数。在上一小
+节我们在“.write”函数中添加了自旋锁，所以两个线程会“依次”通过“受保护的代码片段”。测试代码如下所示。
+
+
+.. code-block:: c
+   :caption: 自旋锁测试应用程序
+   :linenos:  
+
+   #include <stdio.h>
+   #include <unistd.h>
+   #include <fcntl.h>
+   #include <string.h>
+   
+   /*多线程需要用到的头文件*/
+   #include <sys/types.h>
+   #include <unistd.h>
+   
+   int main(int argc, char *argv[])
+   {
+   
+       pid_t pid; //用于保存 fork 函数返回的父、子线程的PID
+       int fd;  //文件描述符
+       
+   /*---------------第一部分------------------*/
+       /*判断输入的命令是否合法*/
+       if (argc != 2)
+       {
+           printf(" commend error ! \n");
+           return -1;
+       }
+   
+   /*---------------第二部分------------------*/
+       pid = fork();
+       if (pid < 0)
+       {
+           /*fork 函数执行错误*/
+           printf("\n fork error ！！\n");
+           return -1;
+       }
+   
+   /*---------------第三部分------------------*/
+       if (0 == pid)
+       {
+           printf("\n child! \n");
+           /*这里是子线程*/
+           fd = open("/dev/led_chrdev0", O_RDWR); //打开设 "led_chrdev0"
+           if (fd < 0)
+           {
+               printf("\n open file : /dev/led_chrdev0 failed !!!\n");
+               return -1;
+           }
+   
+           /*写入命令*/
+           int error = write(fd, argv[1], sizeof(argv[1]));
+           if (error < 0)
+           {
+               printf("write file error! \n");
+               close(fd);
+               /*判断是否关闭成功*/
+           }
+   
+           /*关闭文件*/
+           error = close(fd);
+           if (error < 0)
+           {
+               printf("close file error! \n");
+           }
+       }
+   /*---------------第四部分------------------*/
+       else
+       {
+           printf("\n parent! \n");
+           /*这里是父进程*/
+           fd = open("/dev/led_chrdev1", O_RDWR); //打开设 "led_chrdev1"
+           if (fd < 0)
+           {
+               printf("\n open file : /dev/led_chrdev1 failed !!!\n");
+               return -1;
+           }
+   
+           /*写入命令*/
+           int error = write(fd, argv[1], sizeof(argv[1]));
+           if (error < 0)
+           {
+               printf("write file error! \n");
+               close(fd);
+               /*判断是否关闭成功*/
+           }
+   
+           /*关闭文件*/
+           error = close(fd);
+           if (error < 0)
+           {
+               printf("close file error! \n");
+           }
+       }
+   
+       return 0;
+   }
+
+
+
+
+代码大致分为四部分，结合代码介绍如下：
+
+第一部分，判断命令长度是否符合要求。执行应用程序时要加一个参数指定循环次数，命令格式为“./<应用程序> <循环次数>”。
+
+第二部分，使用函数fork创建子线程并检测创建是否成功。
+
+第三部分，在子线程中依次打开、写入、关闭 “/dev/led_chrdev0”设备节点。
+
+第四部分，在父线程中依次打开、写入、关闭“/dev/led_chrdev1”设别节点。
+
+父进程与子进程都会调用“.write”函数，并且在.write函数中使用自旋锁保护了一段耗时的代码。
+
+实验现象。
+'''''
+
+在驱动所在目录下执行如下命令编译驱动：
+
+编译命令：
+
+.. code-block:: c
+
+   make ARCH=arm CROSS_COMPILE=arm-linux-gnueabihf-
+
+以本章配套源码为例，编译成功后会在源码目录下生成“spinlock.ko”文件，将其拷贝到开发板即可。
+
+在应用程序所在目录下执行如下命令编译测试应用程序：
+
+编译命令：
+
+.. code-block:: c
+
+   arm-linux-gnueabihf-gcc <源文件路径> -o <输出文件名>
+
+以本实验为例，源文件名“test_app.c”则在源码目录下的编译命令为：
+
+.. code-block:: c
+
+   arm-linux-gnueabihf-gcc ./ test_app.c -o test_app
+
+编译成功后将生成的“test_app”拷贝到开发板中。
+
+测试步骤如下所示：
+
+1. 加载驱动
+
+..
+
+   执行“mount <驱动所在路径>”加载驱动，
+
+2. 运行应用程序
+
+..
+
+   执行 “./test_app 10”命令，执行结果如下所示：
+
+信号量试验
+
+.. image:: ./media/concur007.png
+   :align: center
+   :alt: 竞态07|
+
+控制台输出内容上图所示，输出的数字是连续的。开发板的现象是绿灯闪烁10次之后红灯闪烁。
+
+3. 屏蔽掉自旋锁相关代码再次编译驱动，下载运行试验现象如下。
+
+.. image:: ./media/concur008.png
+   :align: center
+   :alt: 竞态08|
+
+控制台输出内容上图所示，输出的数字是不连续的，父进程与子进程交替输出。开发板的现象是绿灯闪烁一次之后闪烁黄灯（红色+绿色显示黄色），由于不同情况下子、父进程执行情况不同实现现象可能稍有差异。
+
+信号量操作函数（宏定义）及试验
+~~~~~~~~~~~~~~~
+
+信号量与自旋锁的使用方法非常类似，包括定义信号量、初始化信号量、获取信号量、释放信号量。我们
+先介绍信号量操作函数，然后编写程序测试程序深入理解信号量。实验源码位于“~/base_code/linux_driver/concurrency/semaphore”
+
+信号量操作函数（宏定义）介绍
+^^^^^^^^^^^^^^
+
+1. 定义信号量。
+
+结构体
+
+.. code-block:: c
+
+   struct semaphore 
+
+用于定义信号量。
+
+2. 初始化信号量。
+
+.. code-block:: c
+
+   static inline void sema_init(struct semaphore \*sem, int val)
+
+说明：
+
+参数sem，指定要初始化的信号量。
+
+参数val，信号量的初始值。
+
+3. 获取信号量
+
+.. code-block:: c
+
+   void down(struct semaphore \*sem);
+   int down_interruptible(struct semaphore \*sem)
+
+**说明：**
+
+参数sem，指定要获取的额信号量，该函数每执行一次，信号量的值就会减1.。函数down如果申请时信号量已经为0则获取失败，进程将会休眠并且不能被信号打断，该函数不能用在中断的上下文中。函数down_interruptible获取信号量失败同样会进入休眠，但是休眠可以被信号打断，并且函数会返回非0值，
+该函数可以用在中断的上下文中而函数down不可以。
+
+4. 尝试获取信号量
+
+.. code-block:: c
+
+   int down_trylock(struct semaphore \*sem)
+
+与获取信号量相比，它有返回值。如果获取成功则返回0，否则会返回非零值。该函数不会导致进程休眠，可以用在中断的上下文中。
+
+5. 释放信号量
+
+.. code-block:: c
+
+   void up(struct semaphore \*sem)
+
+释放信号量，信号量加一。
+
+信号量测试实验
+^^^^^^^
+
+信号量测试实验在自旋锁实验基础上修改得到。我们只需要修改驱动程序和Makefile文件，在驱动程序中使用信号量操作函
+数替换自旋锁操作函数，在Makefiel中只需要修改目标文件名即可。实验源码位于“~/base_code/linux_driver/concurrency/semaphore”
+
+.. _修改驱动程序-2:
+
+修改驱动程序
+''''''
+
+修改之后驱动代码如下所示。（这里只列出了部分代码，完整内容请参考本章配套历程）。
+
+
+
+.. code-block:: c
+   :caption: 信号量试验驱动部分代码
+   :linenos:  
+
+   #include <linux/init.h>
+   #include <linux/module.h>
+   #include <linux/cdev.h>
+   #include <linux/fs.h>
+   #include <linux/uaccess.h>
+   #include <linux/io.h>
+   #include <linux/delay.h>
+   
+   #define DEV_NAME "led_chrdev"
+   #define DEV_CNT (3)
+   
+   static dev_t devno;
+   struct class *led_chrdev_class;
+   
+   
+   /*---------------第一部分------------------*/
+   /*定义一个自旋锁*/
+   // spinlock_t s_lock;
+   struct semaphore sema_lock;
+   
+   static ssize_t led_chrdev_write(struct file *filp, const char __user *buf,
+   								size_t count, loff_t *ppos)
+   {
+   
+   /*----------------以下代码省略----------------*/
+   
+   /*---------------第二部分------------------*/
+   	// spin_lock(&s_lock);
+   	down(&sema_lock);
+   	for (i = ret; i > 0; i--)
+   	{
+   		printk("the data is %ld \n", i);
+   
+   		/*点亮led 灯*/
+   		val &= ~(0x01 << led_cdev->led_pin);
+   		iowrite32(val, led_cdev->va_dr);
+   		mdelay(100);
+   
+   		/*熄灭led 灯*/
+   		val |= (0x01 << led_cdev->led_pin); 
+   		iowrite32(val, led_cdev->va_dr);
+   		mdelay(100);
+   	}
+   	// spin_unlock(&s_lock);
+   	up(&sema_lock);
+   
+   	*ppos += tmp;
+   	return tmp;
+   }
+   
+   static struct file_operations led_chrdev_fops = {
+   	.owner = THIS_MODULE,
+   	.open = led_chrdev_open,
+   	.release = led_chrdev_release,
+   	.write = led_chrdev_write,
+   };
+   
+   /*---------------第三部分------------------*/
+   /*驱动入口*/
+   static __init int led_chrdev_init(void)
+   {
+   /*----------------以下代码省略----------------*/
+   	// spin_lock_init(&s_lock);
+   	sema_init(&sema_lock, 1);
+   	return 0;
+   }
+
+在驱动中修改了三部分内容，只需要只用信号量操作函数替换掉自旋锁操作函数即可。
+
+.. _修改makefile文件-1:
+
+修改Makefile文件
+''''''''''''
+
+Makefile文件只需要修改目标文件名，和源文件（.c文件）名对应即可。这里就不列出具体代码。
+
+.. _实验现象-1:
+
+实验现象
+''''
+
+程序的编译方法与上一小节相同，这里不再赘述。编译完成后拷贝到开发板即可。以本章配套源码为例，驱动为“semaphore.ko”,应用程序为“test_app”。
+
+执行“insmod <驱动所在路径>”加载驱动，加载成功执行“./test_app 10”运行应用程序，正常情况下控制台输出内容如下所示。
+
+.. image:: ./media/concur009.png
+   :align: center
+   :alt: 竞态09|
+
+开发板上的实验现象与自旋锁相同，RGB灯先闪烁绿灯，然后闪烁红灯。不会出现红灯、绿灯同时量（显示黄灯）。
+
+互斥体操作函数（宏定义）及实验
+~~~~~~~~~~~~~~~
+
+上一小节我们讲解了信号量的用法，将信号量设置为1则可以实现互斥体的功能，为什么还要
+讲解互斥体呢？前面也说过，互斥体比信号量的效率要高。实验源码位于“~/base_code/linux_driver/concurrency/mutex”
+
+互斥体操作函数
+^^^^^^^
+
+互斥体的操作函数用法和信号量操作函数使用方法非常相似，可对比学习。互斥体操作函数介绍如下所示。
+
+6. 定义信号量。
+
+结构体struct mutex 用于定义信号量。
+
+7. 初始化互斥体。
+
+.. code-block:: c
+
+   mutex_init(struct mutex \*lock)
+
+说明：
+
+参数lock，指定要初始化的互斥体。
+
+8. 获取互斥体
+
+.. code-block:: c
+
+   void \__sched mutex_lock(struct mutex \*lock)。
+   int \__sched mutex_lock_interruptible(struct mutex \*lock)。
+
+参数lock，指定要获取的互斥体，执行该函数相当于“上锁”，释放之前其他线程无法再次获取。获取失败进程将会休眠并且不能被信号打断，该函数不能用在中断的上下文中。函数mutex_lock_interruptible获取信号量失败同样会进入休眠，但是休眠可以被信号打断，并且函数会返回非0值，该函数可以用
+在中断的上下文中而函数mutex_lock不可以。
+
+9. 尝试获取互斥体
+
+.. code-block:: c
+
+   int \__sched mutex_trylock(struct mutex \*lock)。
+
+与获取互斥体相比，它有返回值。如果获取成功则返回0，否则会返回非零值。该函数不会导致进程休眠，可以用在中断的上下文中。
+
+10.
+释放互斥体
+
+.. code-block:: c
+
+   void mutex_unlock (struct semaphore \*sem)
+
+互斥体测试实验
+^^^^^^^
+
+互斥体的使用方法与信号量几乎完全相同，在信号量测试实验的基础上使用互斥体操作
+函数替换信号量操作函数即可。
+
+这里只提供测试源码位于“~/base_code/linux_driver/concurrency/mutex”，这里不再对代码
+进行讲解，详细可参考信号量测试实验。
+
+.. |concur002| image:: media\concur002.png
+   :width: 4.03075in
+   :height: 4.30155in
+.. |concur003| image:: media\concur003.png
+   :width: 5.76806in
+   :height: 1.32917in
+.. |concur004| image:: media\concur004.png
+   :width: 5.76806in
+   :height: 2.18889in
+.. |concur005| image:: media\concur005.png
+   :width: 5.34308in
+   :height: 1.98934in
+.. |concur006| image:: media\concur006.png
+   :width: 5.76806in
+   :height: 2.05833in
+.. |concur007| image:: media\concur007.png
+   :width: 5.46807in
+   :height: 4.4057in
+.. |concur008| image:: media\concur008.png
+   :width: 5.76806in
+   :height: 4.02014in
+.. |concur009| image:: media\concur009.png
+   :width: 5.76806in
+   :height: 4.69931in
diff --git a/documentation/linux_driver/device_tree_rgb_led.rst b/documentation/linux_driver/device_tree_rgb_led.rst
new file mode 100644
index 0000000000000000000000000000000000000000..8b2591b9124b4e0faa730cccac5191d231f44109
--- /dev/null
+++ b/documentation/linux_driver/device_tree_rgb_led.rst
@@ -0,0 +1,660 @@
+.. vim: syntax=rst
+
+使用设备树实现RGB 灯驱动
+---------------
+
+通过上一小节的学习，我们已经能够编写简单的设备树节点，并且使用常用的of函数从设备树中获取我们想要的节点资源。这一小节我们带领大家使用设备树编写一个简单的RGB灯驱动程序，加深对设备树的理解。
+
+程序编写的主要内容为添加RGB灯的设备树节点、在驱动程序中使用of函数获取设备节点中的属性，编写测试应用程序。完整代码位于“补充”
+
+添加RGB设备节点
+~~~~~~~~~
+
+RGB灯实际使用的是一个IO口，控制它所需要的资源几个控制寄存器，所以它的设备树节点也非常简单如下所示。
+
+.. code-block:: c 
+    :caption: 添加设备节点
+    :linenos:
+
+    /*------------第一部分---------------*/
+    /*
+    *CCM_CCGR1                         0x020C406C
+    *IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO04  0x020E006C
+    *IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO04  0x020E02F8
+    *GPIO1_GD                          0x0209C000
+    *GPIO1_GDIR                        0x0209C004
+    */
+    
+    
+    /*
+    *CCM_CCGR3                         0x020C4074
+    *IOMUXC_SW_MUX_CTL_PAD_CSI_HSYNC   0x020E01E0
+    *IOMUXC_SW_PAD_CTL_PAD_CSI_HSYNC   0x020E046C
+    *GPIO4_GD                          0x020A8000
+    *GPIO4_GDIR                        0x020A8004
+    */
+    
+    
+    /*
+    *CCM_CCGR3                         0x020C4074
+    *IOMUXC_SW_MUX_CTL_PAD_CSI_VSYNC   0x020E01DC
+    *IOMUXC_SW_PAD_CTL_PAD_CSI_VSYNC   0x020E0468
+    *GPIO4_GD                          0x020A8000
+    *GPIO4_GDIR                        0x020A8004
+    */
+    /*添加led节点*/
+    
+    /*------------第二部分---------------*/
+    rgb_led{
+    	#address-cells = <1>;
+    	#size-cells = <1>;
+    	compatible = "fire,rgb_led";
+    	/*------------第三部分---------------*/
+    	/*红灯节点*/
+    	ranges;
+    	rgb_led_red@0x020C406C{
+    		compatible = "fire,rgb_led_red";
+    		reg = <0x020C406C 0x00000004
+    		       0x020E006C 0x00000004
+    		       0x020E02F8 0x00000004
+    			   0x0209C000 0x00000004
+    		       0x0209C004 0x00000004>;
+    		status = "okay";
+    	};
+    	/*------------第四部分---------------*/
+    	/*绿灯节点*/
+    	rgb_led_green@0x020C4074{
+    		compatible = "fire,rgb_led_green";
+    		reg = <0x020C4074 0x00000004
+    		       0x020E01E0 0x00000004
+    		       0x020E046C 0x00000004
+    			   0x020A8000 0x00000004
+    		       0x020A8004 0x00000004>;
+    		status = "okay";
+    	};
+    	/*------------第五部分---------------*/
+    	/*蓝灯节点*/
+    	rgb_led_blue@0x020C4074{
+    		compatible = "fire,rgb_led_blue";
+    		reg = <0x020C4074 0x00000004
+    		       0x020E01DC 0x00000004
+    		       0x020E0468 0x00000004
+    			   0x020A8000 0x00000004
+    		       0x020A8004 0x00000004>;
+    		status = "okay";
+    	};
+    };
+
+
+RGB灯的设备节点添加到了根节点的末尾，完整内容请参考本章配套代码。结合设备树介绍如下：
+
+第一 部分，这部分列出了控制RGB灯的三个引脚所使用的的寄存器，这些寄存器的作用以及用法已经在裸机部分详细介绍，这里不再赘述，如有疑问可以参考裸机的LED相关章节。
+
+第二部分，这里就是RGB灯的设备树节点，节点名“rgb_led”由于在根节点下，很明显它的设备树路径为“/rgb_led”,在驱动程序中我们会用到这个路径。这里共定义了三个属性，“#address-cells”和“#size-
+cells”定义了它的子节点的reg属性样式。“compatible”属性用于匹配驱动，在驱动我们会配置一个和“compatible”一样的参数，这样加载驱动是就可以自动和这个设备树节点匹配了。
+
+第三部分，rgb_led节点的子节点。RGB灯使用了三个引脚，如上所示，它会用到15个寄存器，为方便管理，我们为每个引脚创建了一个子节点，从上到下依次为红灯控制引脚、绿灯控制引脚、蓝灯控制引脚。它们三个非常相似，我们这里只以第一个红灯控制引脚为例讲解。在红灯子节点中只定义了三个属性，“compati
+ble = "fire,rgb_led_red"”表示这是一个红灯子节点，对于本实验来说可有可无。“reg = < ...>”定义红灯引脚使用到寄存器。一共有五个，排列顺序与注释中的一致。“status = "okay"”定义子节点的状态，我们要用这个子节点所以设置为“okay”。
+
+编写驱动程序
+~~~~~~
+
+基于设备树的驱动程序与平台总线驱动非常相似，差别是平台总线驱动中的平台驱动要和平台设备进行匹配，使用设备树后设备树取代“平台设备”的作用，平台驱动只需要和与之对应的设备树节点匹配即可。
+
+驱动程序主要内容包括编写平台设备驱动框架、编写.prob函数、实现字符设备操作函数集、驱动注销四部分内容。结合源码介绍如下。
+
+编写平台设备驱动框架
+^^^^^^^^^^
+
+平台设备驱动框架主要包驱动入口函数、驱动注销函数、平台设备结构体定义三部分内容。其中驱动注销函数会用到后面的内容，这里暂不介绍，放在最后面介绍。
+
+驱动入口函数
+''''''
+
+驱动入口函数仅仅注册一个平台驱动，如下所示
+
+
+
+
+
+.. code-block:: c 
+    :caption: 驱动初始化函数
+    :linenos:
+
+    /*
+    *驱动初始化函数
+    */
+    static int __init led_platform_driver_init(void)
+    {
+    	int DriverState;
+    	DriverState = platform_driver_register(&led_platform_driver);
+    	printk(KERN_EMERG "\tDriverState is %d\n", DriverState);
+    	return 0;
+    }
+
+
+
+在整个入口函数中仅仅调用了“platform_driver_register”函数注册了一个平台驱动。参数是一个平台设备结构体。介绍如下。
+
+定义平台设备结构体
+'''''''''
+
+注册平台驱动时会用到平台设备结构体，在平台设备结构体主要作用是指定平台驱动的.probe函数、指定与平台驱动匹配的平台设备，使用了设备树后就是指定与平台驱动匹配的设备树节点。源码如下所示。
+
+
+
+
+
+
+.. code-block:: c 
+    :caption: 平台设备结构体
+    :linenos:
+
+    /*------------第一部分---------------*/
+    static const struct of_device_id rgb_led[] = {
+    	{.compatible = "fire,rgb_led"},
+    	{/* sentinel */}};
+    /*------------第二部分---------------*/
+    /*定义平台设备结构体*/
+    struct platform_driver led_platform_driver = {
+    	.probe = led_probe,
+    	.driver = {
+    		.name = "rgb-leds-platform",
+    		.owner = THIS_MODULE,
+    		.of_match_table = rgb_led,
+    	}};
+
+
+以上代码中第二部分就是我们定义的平台设备结构体。其中“.probe =
+led_probe,”指定.probe函数。.probe函数比较特殊，当平台驱动和设备树节点匹配后会自动执行.probe函数，后面的RGB灯的初始化以及字符设备的注册都在这个函数中实现（当然也可以在其他函数中实现）。“.driver = { …
+}”定义driver的一些属性，包括名字、所有者等等，其中最需要注意的是“.of_match_table ”属性，它指定这个驱动的匹配表。匹配表的定义如第一部分代码所示。这里只定义了一个匹配值“.compatible = "fire,rgb_led”，这个驱动将会和设备树中“compatible =
+"fire,rgb_led"的节点匹配”，准确的说是和““compatible = "fire,rgb_led"”的相对根节点的子节点匹配。我们在根节点下定义了rgb_led子节点，并且设置“compatible = "fire,rgb_led";”所以正常情况下，驱动会和这个子节点匹配。
+
+实现.probe函数
+^^^^^^^^^^
+
+之前说过，当驱动和设备树节点匹配成功后会自动执行.probe函数，所以我们可以在.probe函数中实现
+一些初始化工作。本实验将RGB初始化以及字符设备的初始化全部放到.probe函数中实现，.probe函数较长，但包含大
+量的简单、重复性的初始化代码，非常容易理解。源码如下所示。
+
+
+.. code-block:: c 
+    :caption: .probe函数
+    :linenos:
+
+    /*------------------------第一部分--------------------------*/
+    
+    /*定义 led 资源结构体，保存获取得到的节点信息以及转换后的虚拟寄存器地址*/
+    struct led_resource
+    {
+    	struct device_node *device_node; //rgb_led_red的设备树节点
+    	void __iomem *virtual_CCM_CCGR;
+    	void __iomem *virtual_IOMUXC_SW_MUX_CTL_PAD;
+    	void __iomem *virtual_IOMUXC_SW_PAD_CTL_PAD;
+    	void __iomem *virtual_DR;
+    	void __iomem *virtual_GDIR;
+    };
+    
+    /*定义 R G B 三个灯的led_resource 结构体，保存获取得到的节点信息*/
+    struct led_resource led_red;
+    struct led_resource led_green;
+    struct led_resource led_blue;
+    
+    
+    
+    static int led_probe(struct platform_device *pdv)
+    {
+    
+    	int ret = -1; //保存错误状态码
+    	unsigned int register_data = 0;
+    
+    	printk(KERN_EMERG "\t  match successed  \n");
+    
+    
+    /*------------------------第二部分--------------------------*/
+    	/*获取rgb_led的设备树节点*/
+    	rgb_led_device_node = of_find_node_by_path("/rgb_led");
+    	if (rgb_led_device_node == NULL)
+    	{
+    		printk(KERN_ERR "\t  get rgb_led failed!  \n");
+    		return -1;
+    	}
+    
+    /*------------------------第三部分--------------------------*/
+    	/*获取rgb_led节点的红灯子节点*/
+    	led_red.device_node = of_find_node_by_name(rgb_led_device_node,"rgb_led_red");
+    	if (led_red.device_node == NULL)
+    	{
+    		printk(KERN_ERR "\n get rgb_led_red_device_node failed ! \n");
+    		return -1;
+    	}
+    
+    	/*获取 reg 属性并转化为虚拟地址*/
+    	led_red.virtual_CCM_CCGR = of_iomap(led_red.device_node, 0);
+    	led_red.virtual_IOMUXC_SW_MUX_CTL_PAD = of_iomap(led_red.device_node, 1);
+    	led_red.virtual_IOMUXC_SW_PAD_CTL_PAD = of_iomap(led_red.device_node, 2);
+    	led_red.virtual_DR = of_iomap(led_red.device_node, 3);
+    	led_red.virtual_GDIR = of_iomap(led_red.device_node, 4);
+    
+    	/*初始化红灯*/
+    	register_data = readl(led_red.virtual_CCM_CCGR);
+    	register_data |= (0x03 << 26);
+    	writel(register_data, led_red.virtual_CCM_CCGR); //开启时钟
+    
+    	register_data = readl(led_red.virtual_IOMUXC_SW_MUX_CTL_PAD);
+    	register_data &= ~(0xff << 0);
+    	register_data |= (0x05 << 0);
+    	writel(register_data, led_red.virtual_IOMUXC_SW_MUX_CTL_PAD); //设置复用功能
+    
+    	register_data = readl(led_red.virtual_IOMUXC_SW_PAD_CTL_PAD);
+    	register_data = (0x10B0);
+    	writel(register_data, led_red.virtual_IOMUXC_SW_PAD_CTL_PAD); //设置PAD 属性
+    
+    	register_data = readl(led_red.virtual_GDIR);
+    	register_data |= (0x01 << 4);
+    	writel(register_data, led_red.virtual_GDIR); //设置GPIO1_04 为输出模式
+    
+    	register_data = readl(led_red.virtual_DR);
+    	register_data |= (0x01 << 4);
+    	writel(register_data, led_red.virtual_DR); //设置 GPIO1_04 默认输出高电平
+    
+    
+    
+    /*------------------------第四部分--------------------------*/
+    	/*获取rgb_led节点的绿灯子节点*/
+    	led_green.device_node = of_find_node_by_name(rgb_led_device_node,"rgb_led_green");
+    	if (led_green.device_node == NULL)
+    	{
+    		printk(KERN_ERR "\n get rgb_led_green_device_node failed ! \n");
+    		return -1;
+    	}
+    
+    	/*获取 reg 属性并转化为虚拟地址*/
+    	led_green.virtual_CCM_CCGR = of_iomap(led_green.device_node, 0);
+    	led_green.virtual_IOMUXC_SW_MUX_CTL_PAD = of_iomap(led_green.device_node, 1);
+    	led_green.virtual_IOMUXC_SW_PAD_CTL_PAD = of_iomap(led_green.device_node, 2);
+    	led_green.virtual_DR = of_iomap(led_green.device_node, 3);
+    	led_green.virtual_GDIR = of_iomap(led_green.device_node, 4);
+    
+    	/*初始化绿灯*/
+    	register_data = readl(led_green.virtual_CCM_CCGR);
+    	register_data |= (0x03 << 12);
+    	writel(register_data, led_green.virtual_CCM_CCGR); //开启时钟
+    
+    	register_data = readl(led_green.virtual_IOMUXC_SW_MUX_CTL_PAD);
+    	register_data &= ~(0xff << 0);
+    	register_data |= (0x05 << 0);
+    	writel(register_data, led_green.virtual_IOMUXC_SW_MUX_CTL_PAD); //设置复用功能
+    
+    	register_data = readl(led_green.virtual_IOMUXC_SW_PAD_CTL_PAD);
+    	register_data = (0x10B0);
+    	writel(register_data, led_green.virtual_IOMUXC_SW_PAD_CTL_PAD); //设置PAD 属性
+    
+    	register_data = readl(led_green.virtual_GDIR);
+    	register_data |= (0x01 << 20);
+    	writel(register_data, led_green.virtual_GDIR); //设置GPIO4_IO20 为输出模式
+    
+    	register_data = readl(led_green.virtual_DR);
+    	register_data |= (0x01 << 20);
+    	writel(register_data, led_green.virtual_DR); //设置 GPIO4_IO20 默认输出高电平
+    
+    
+    /*------------------------第五部分--------------------------*/
+    
+    	/*获取rgb_led节点的蓝灯子节点*/
+    	led_blue.device_node = of_find_node_by_name(rgb_led_device_node,"rgb_led_blue");
+    	if (led_blue.device_node == NULL)
+    	{
+    		printk(KERN_ERR "\n get rgb_led_blue_device_node failed ! \n");
+    		return -1;
+    	}
+    
+    	/*获取 reg 属性并转化为虚拟地址*/
+    	led_blue.virtual_CCM_CCGR = of_iomap(led_blue.device_node, 0);
+    	led_blue.virtual_IOMUXC_SW_MUX_CTL_PAD = of_iomap(led_blue.device_node, 1);
+    	led_blue.virtual_IOMUXC_SW_PAD_CTL_PAD = of_iomap(led_blue.device_node, 2);
+    	led_blue.virtual_DR = of_iomap(led_blue.device_node, 3);
+    	led_blue.virtual_GDIR = of_iomap(led_blue.device_node, 4);
+    
+    	/*初始化绿灯*/
+    	register_data = readl(led_blue.virtual_CCM_CCGR);
+    	register_data |= (0x03 << 12);
+    	writel(register_data, led_blue.virtual_CCM_CCGR); //开启时钟
+    
+    	register_data = readl(led_blue.virtual_IOMUXC_SW_MUX_CTL_PAD);
+    	register_data &= ~(0xff << 0);
+    	register_data |= (0x05 << 0);
+    	writel(register_data, led_blue.virtual_IOMUXC_SW_MUX_CTL_PAD); //设置复用功能
+    
+    	register_data = readl(led_blue.virtual_IOMUXC_SW_PAD_CTL_PAD);
+    	register_data = (0x10B0);
+    	writel(register_data, led_blue.virtual_IOMUXC_SW_PAD_CTL_PAD); //设置PAD 属性
+    
+    	register_data = readl(led_blue.virtual_GDIR);
+    	register_data |= (0x01 << 19);
+    	writel(register_data, led_blue.virtual_GDIR); //设置GPIO4_IO19 为输出模式
+    
+    	register_data = readl(led_blue.virtual_DR);
+    	register_data |= (0x01 << 19);
+    	writel(register_data, led_blue.virtual_DR); //设置 GPIO4_IO19 默认输出高电平
+    
+    
+    
+        /*------------------------第六部分--------------------------*/
+    	/*---------------------注册 字符设备部分-----------------*/
+    
+    	//第一步
+    	//采用动态分配的方式，获取设备编号，次设备号为0，
+    	//设备名称为rgb-leds，可通过命令cat  /proc/devices查看
+    	//DEV_CNT为1，当前只申请一个设备编号
+    	ret = alloc_chrdev_region(&led_devno, 0, DEV_CNT, DEV_NAME);
+    	if (ret < 0)
+    	{
+    		printk("fail to alloc led_devno\n");
+    		goto alloc_err;
+    	}
+    	//第二步
+    	//关联字符设备结构体cdev与文件操作结构体file_operations
+    	led_chr_dev.owner = THIS_MODULE;
+    	cdev_init(&led_chr_dev, &led_chr_dev_fops);
+    	//第三步
+    	//添加设备至cdev_map散列表中
+    	ret = cdev_add(&led_chr_dev, led_devno, DEV_CNT);
+    	if (ret < 0)
+    	{
+    		printk("fail to add cdev\n");
+    		goto add_err;
+    	}
+    
+    	//第四步
+    	/*创建类 */
+    	class_led = class_create(THIS_MODULE, DEV_NAME);
+    
+    	/*创建设备*/
+    	device = device_create(class_led, NULL, led_devno, NULL, DEV_NAME);
+    
+    	return 0;
+    
+    add_err:
+    	//添加设备失败时，需要注销设备号
+    	unregister_chrdev_region(led_devno, DEV_CNT);
+    	printk("\n error! \n");
+    alloc_err:
+    
+    	return -1;
+    }
+
+
+代码共分为六部分，结合代码介绍如下：
+
+第一部分，自定义一个结构体，用于保存读取得到的引脚相关寄存器，以及设备节点结构体。
+
+第二部分，使用of_find_node_by_path函数获取设备树节点“/rgb_led”，获取成功后会返回“/rgb_led”节点的“设备节点结构体”后面的代码我们就可以根据这个“设备节点结构体”访问它的子节点。
+
+第三部分，第三部分到第五部分依次初始化 红、绿、蓝灯，这三部分非常
+相似，这里仅介绍第三部分红灯初始化部分。初始化过程大致分三步。第一步，获取红
+灯子节点，这里使用函数“of_find_node_by_name”，参数rgb_led_device_node指定从
+rgb_led节点开始搜索，参数"rgb_led_red"指定要获取那个节点，这里是rgb_led节点下的rgb_led_red子节点。第二步，获取并转换re
+g属性，我们知道reg属性保存的是就寄存器地址（物理地址），这里使用“of_iomap”函数，获
+取并完成物理地址到虚拟地址的转换。第三步，初始化寄存器，至于如何将初始化GPIO在裸机章节
+已经详细介绍这里不再赘述，需要注意的是这里只能用系统提供的API(例如这里读写的是32位数据，使用writel和r
+eadl)，不能像裸机那样直接使用“=”、“&=”、“|=”等等那样直接修改寄存器。
+
+第六部分，注册一个字符设备。字符设备的注册过程与之前讲解的字符设备驱动非常相似，这部分代码就是从字符涉笔驱动拷贝得到的。这里不再过多介绍，注册流程简单介绍如下。
+
+本章配套源码使用到了如下结构体：
+
+
+
+.. code-block:: c 
+    :caption: 注册字符设备使用到的结构体
+    :linenos:
+
+    static dev_t led_devno;					 //定义字符设备的设备号
+    static struct cdev led_chr_dev;			 //定义字符设备结构体chr_dev
+    struct class *class_led;				 //保存创建的类
+    struct device *device;					 // 保存创建的设备
+    
+    static struct file_operations led_chr_dev_fops =
+    	{
+    		.owner = THIS_MODULE,
+    		.open = led_chr_dev_open,
+    		.write = led_chr_dev_write,
+    };
+
+
+第一步，使用“alloc_chrdev_region”动态申请主设备号，并保存到led_devno结构体中。第二步，使用“cdev_init”初始化字符设别。第三步，使用“cdev_add”将字符设备添加到系统。如果需要驱动自动创建设备节点，则还要创建类和设备。第四部，使用“class_create
+”函数创建类。第五步，使用“device_create”创建设备，其中参数“DEV_NAME”用于指定设备节点名，这个名字在应用程序中会用到。
+
+如果驱动和设备树节点完成匹配，系统会自动执行.probe函数，从上方代码可知，.probe函数完成了RGB灯的初始化和字符设备的创建。下一步我们只需要在字符设备的操作函数集中控制RGB灯即可。
+
+实现字符设备操作函数集
+^^^^^^^^^^^
+
+为简化程序设计这里仅仅实现了字符设备操作函数集中的.write函数，.write函数根据收到的信息控制RGB灯的亮、灭，结合代码介绍如下：
+
+
+
+
+.. code-block:: c 
+    :caption: .write函数实现
+    :linenos:
+
+    /*字符设备操作函数集，open函数*/
+    static int led_chr_dev_open(struct inode *inode, struct file *filp)
+    {
+    	printk("\n open form driver \n");
+    	return 0;
+    }
+    
+    /*字符设备操作函数集，write函数*/
+    static ssize_t led_chr_dev_write(struct file *filp, const char __user *buf, size_t cnt, loff_t *offt)
+    {
+    
+    	unsigned int register_data = 0; //暂存读取得到的寄存器数据
+    	unsigned char write_data; //用于保存接收到的数据
+    
+    /*----------------------第一部分-------------------------*/
+    	int error = copy_from_user(&write_data, buf, cnt);
+    	if (error < 0)
+    	{
+    		return -1;
+    	}
+    
+    /*----------------------第二部分-------------------------*/
+    	/*设置 GPIO1_04 输出电平*/
+    	if (write_data & 0x04)
+    	{
+    		register_data = readl(led_red.virtual_DR);
+    		register_data &= ~(0x01 << 4);
+    		writel(register_data, led_red.virtual_DR); // GPIO1_04引脚输出低电平，红灯亮
+    	}
+    	else
+    	{
+    		register_data = readl(led_red.virtual_DR);
+    		register_data |= (0x01 << 4);
+    		writel(register_data, led_red.virtual_DR); // GPIO1_04引脚输出高电平，红灯灭
+    	}
+    
+    /*----------------------第三部分-------------------------*/
+    	/*设置 GPIO4_20 输出电平*/
+    	if (write_data & 0x02)
+    	{
+    		register_data = readl(led_green.virtual_DR);
+    		register_data &= ~(0x01 << 20);
+    		writel(register_data, led_green.virtual_DR); // GPIO4_20引脚输出低电平，绿灯亮
+    	}
+    	else
+    	{
+    		register_data = readl(led_green.virtual_DR);
+    		register_data |= (0x01 << 20);
+    		writel(register_data, led_green.virtual_DR); // GPIO4_20引脚输出高电平，绿灯灭
+    	}
+    
+    /*----------------------第四部分-------------------------*/
+    	/*设置 GPIO4_19 输出电平*/
+    	if (write_data & 0x01)
+    	{
+    		register_data = readl(led_blue.virtual_DR);
+    		register_data &= ~(0x01 << 19);
+    		writel(register_data, led_blue.virtual_DR); //GPIO4_19引脚输出低电平，蓝灯亮
+    	}
+    	else
+    	{
+    		register_data = readl(led_blue.virtual_DR);
+    		register_data |= (0x01 << 19);
+    		writel(register_data, led_blue.virtual_DR); //GPIO4_19引脚输出高电平，蓝灯灭
+    	}
+    
+    	return 0;
+    }
+    
+    
+    /*----------------------第五部分-------------------------*/
+    /*字符设备操作函数集*/
+    static struct file_operations led_chr_dev_fops =
+    	{
+    		.owner = THIS_MODULE,
+    		.open = led_chr_dev_open,
+    		.write = led_chr_dev_write,
+    };
+
+
+我们仅实现了两个字符设备操作函数，从第五部分可知.open 对应led_chr_dev_open函数这是一个空函数。.write对应led_chr_dev_write函数，这个函数接收应用程序传回的命令，根据命令控制RGB三个灯的亮、灭，结合代码介绍如下。
+
+第一部分，使用copy_from_user函数将用户空间的数据拷贝到内核空间。这里传递的数据是一个无符号整型数据。
+
+第二部分，第二部分到第四部分都是解析命令，如何解析由我们自己决定。本例中使用数字的后三位从高到低依次对应红灯、绿灯、蓝灯，对应位是1则亮灯否则熄灭。例如0x03表示红灯灭，绿灯和蓝灯亮。0x07 表示全亮。具体实现过程很简单这里不再赘述。
+
+编写测试应用程序
+~~~~~~~~
+
+在驱动程序中我采用自动创建设备节点的方式创建了字符设备的设备节点文件，文件名可自定义，写测试应用程序时记得文件名即可。本例程设备节点名为“rgb_led”。测试程序很简单，源码如下所示。
+
+
+
+.. code-block:: c 
+    :caption: 测试应用程序
+    :linenos:
+
+    #include <stdio.h>
+    #include <unistd.h>
+    #include <fcntl.h>
+    #include <string.h>
+    int main(int argc, char *argv[])
+    {
+    
+    
+    /*-----------------第一部分----------------------*/
+        printf("led_tiny test\n");
+        /*判断输入的命令是否合法*/
+        if(argc != 2)
+        {
+            printf(" commend error ! \n");
+            return -1;
+        }
+    
+    /*-----------------第二部分----------------------*/
+        /*打开文件*/
+        int fd = open("/dev/rgb_led", O_RDWR);
+        if(fd < 0)
+        {
+    		printf("open file : %s failed !\n", argv[0]);
+    		return -1;
+    	}
+    
+    /*-----------------第三部分----------------------*/
+        unsigned char commend = atoi(argv[1]);  //将受到的命令值转化为数字;
+    
+        /*判断命令的有效性*/
+    
+        /*写入命令*/
+        int error = write(fd,&commend,sizeof(commend));
+        if(error < 0)
+        {
+            printf("write file error! \n");
+            close(fd);
+            /*判断是否关闭成功*/
+        }
+    
+        /*关闭文件*/
+        error = close(fd);
+        if(error < 0)
+        {
+            printf("close file error! \n");
+        }
+        
+        return 0;
+    }
+
+
+第一部分，简单判断输入是否合法，运行本测试应用程序时argc应该为2。它由应用程序文件名和命令组成例如“/test_app <命令值>”。
+
+第二部分，打开设备文件。
+
+第三部分，将终端输入的命令值转化为数字最终使用write函数
+
+下载验证
+~~~~
+
+如何编译、下载设备树在上一章已经介绍这里不再赘述。驱动程序和应用程序编译命令如下所示：
+
+驱动编译命令：
+
+make ARCH=arm CROSS_COMPILE=arm-linux-gnueabihf-
+
+应用程序编译命令：
+
+arm-linux-gnueabihf-gcc <源文件名> –o <输出文件名>
+
+将驱动程序和应用程序添加到开发板中（推荐使用之前讲解的NFS共享文件夹），驱动程序和应用程序在开发板中的存放位置没有限制。我们将驱动和应用都放到开发板的“/home/nfs_share”目录下，如下所示。
+
+
+.. image:: ./media/device_tree_rgb_led002.png
+   :align: center
+   :alt: 找不到图片02|
+
+执行如下命令加载驱动：
+
+命令：
+
+insmod ./rgb-leds.ko
+
+正常情况下输出结果如下所示。
+
+.. image:: ./media/device_tree_rgb_led003.png
+   :align: center
+   :alt: 找不到图片03|
+
+在驱动程序中，我们在.probe函数中注册字符设备并创建了设备文件，设备和驱动匹配成功后.probe函数已经执行，所以正常情况下在“/dev/”目录下已经生成了“rgb-leds”设备节点，如下所示。
+
+.. image:: ./media/device_tree_rgb_led004.png
+   :align: center
+   :alt: 找不到图片04|
+
+驱动加载成功后直接运行应用程序如下所示。
+
+命令：
+
+./test_app <命令>
+
+执行结果如下：
+
+.. image:: ./media/device_tree_rgb_led005.png
+   :align: center
+   :alt: 找不到图片05|
+
+命令是一个“unsigned char”型数据，只有后三位有效，每一位代表一个灯，从高到低依次代表红、绿、蓝，1表示亮，0表示灭。例如命令=4 则亮红灯，命令=7则三个灯全亮。
+
+.. |device002| image:: media\device002.png
+   :width: 5.76806in
+   :height: 1.425in
+.. |device003| image:: media\device003.png
+   :width: 5.76806in
+   :height: 1.33958in
+.. |device004| image:: media\device004.png
+   :width: 5.28059in
+   :height: 0.52077in
+.. |device005| image:: media\device005.png
+   :width: 4.63484in
+   :height: 1.78103in
diff --git a/documentation/linux_driver/driver_tree.rst b/documentation/linux_driver/driver_tree.rst
new file mode 100644
index 0000000000000000000000000000000000000000..4d40139ad27f5abe8d7aecf1ea077c4dc7283201
--- /dev/null
+++ b/documentation/linux_driver/driver_tree.rst
@@ -0,0 +1,1154 @@
+.. vim: syntax=rst
+
+Linux设备树
+--------------------------------
+
+Linux3.x以后的版本才引入了设备树，设备树用于描述一个硬件平台的板级细节。在早些的linux内核，这些“硬件平台的板级细节”保存在linux内核目录“/arch”，以ARM平台为例“硬件平台的板级细节”保存在“/arch/arm/plat-xxx”和“/arch/arm/mach-
+xxx”目录下。随着处理器数量的增多用于描述“硬件平台板级细节”的文件越来越多导致Linux内核非常臃肿，Linux之父发现这个问题之后决定使用设备树解决这个问题。设备树简单、易用、可重用性强，linux3.x之后大多采用设备树编写驱动。
+
+设备树简介
+~~~~~~~~~~~~~~~~~~~~
+
+设备树的作用就是描述一个硬件平台的硬件资源。这个“设备树”可以被bootloader(uboot)传递到内核，内核可以从设备树中获取硬件信息。
+
+设备树描述硬件资源时有两个特点。第一，以“树状”结构描述硬件资源，例如本地总线为树的“主干”在设备树里面称为“根节点”，挂载到本地总线的IIC总线、SPI总线、UART总线为树的“枝干”在设备树里称为“根节点的子节点”，IIC 总线下的IIC设备不止一个，这些“枝干”又可以再分。第二，设备树可以像头
+文件（.h文件）那样，一个设备树文件引用另外一个设备树文件，这样可以实现“代码”的重用，例如多个硬件平台都使用i.MX6ULL作为主控芯片，那么我们可以将i.MX6ULL芯片的硬件资源写到一个单独的设备树文件里面一般使用“.dtsi”后缀，其他设备树文件直接使用“# include
+xxx”引用即可。
+
+DTS、DTC和DTB它们是文档中常见的几个缩写。DTS是指.dts格式的文件，是一种ASII 文本格式的设备树描述，也是我们要编写的设备树源码，一般一个.dts文件对应一个硬件平台，位于Linux源码的“/arch/arm/boot/dts”目录下。DTC是指编译设备树源码的工具，一般情况下我们需
+要手动安装这个编译工具。DTB是设备树源码编译生成的文件，类似于我们C语言中“.C”文件编译生成“.bin”文件。
+
+设备树语法讲解及源码分析
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+上一小节我们简单了解了设备树的作用，到现在为止我们还不知道“设备树”是什么样子。考虑到直接讲解设备树语法可能会让人摸不着头脑，下面内容将以我们现在使用的设备树源码为例逐步分析设备树，在分析过程中讲解设备树基本语法。
+
+本教程使用的设备树位于“~/ebf-buster-linux/arch/arm/boot/dts/imx6ull-seeed-npi.dts”
+
+打开设备树文件“imx6ull-seeed-npi.dts”如下所示。
+
+
+
+.. code-block:: c 
+    :caption: 设备树
+     :linenos:
+ 
+    /*--------------------第一部分----------------*/
+    #include <dt-bindings/input/input.h>  
+    #include "imx6ull.dtsi"            ---------------①
+    
+    
+    /*--------------------第二部分----------------*/
+    / {  --------------------②
+    	model = "Seeed i.MX6 ULL NPi Board";
+    	compatible = "fsl,imx6ull-14x14-evk", "fsl,imx6ull";
+    
+    	aliases {
+    		pwm0 = &pwm1;
+    		pwm1 = &pwm2;
+    		pwm2 = &pwm3;
+    		pwm3 = &pwm4;
+    	};
+        chosen {
+    		stdout-path = &uart1;
+    	};
+    
+    	memory {
+    		reg = <0x80000000 0x20000000>;
+    	};
+    
+    	reserved-memory {
+    		#address-cells = <1>;
+    		#size-cells = <1>;
+    		ranges;
+    
+    		linux,cma {
+    			compatible = "shared-dma-pool";
+    			reusable;
+    			size = <0x14000000>;
+    			linux,cma-default;
+    		};
+    	};
+        /*-------------以下内容省略=-------------*/
+    };
+    
+    /*--------------------第三部分----------------*/
+    &cpu0 {  --------------------③
+    	dc-supply = <&reg_gpio_dvfs>;
+    	clock-frequency = <800000000>;
+    };
+    
+    &clks {  --------------------④
+    	assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
+    	assigned-clock-rates = <786432000>;
+    };
+    
+    
+    &fec1 {  --------------------⑤
+    	pinctrl-names = "default";
+    	pinctrl-0 = <&pinctrl_enet1>;
+    	phy-mode = "rmii";
+    	phy-handle = <&ethphy0>;
+    	status = "okay";
+    };
+    /*-------------以下内容省略=-------------*/
+
+设备树源码分为三部分，介绍如下：
+
+第一部分，头文件。根据之前讲解设备树是可以像C语言那样使用“#include”引用头文件。标号①处并不是我们常见的“.h”头文件，它也是一个imx6ull平台“共用”的设备树文件，它由NXP官方提供，稍后我们会以imx6ull.dtsi文件为例分析设备树。
+
+第二部分，添加设备树节点。设备树给我们最直观的感受是它由一些嵌套的大括号“{}”组成，每一个“{}”都是一个“节点”标号② “/ {…};”表示它是一个“根节点”每一个设备树只有一个根节点。如果打开“imx6ull.dtsi”文件可以发现它也有一个根节点，“imx6ull-seeed-
+npi.dts”引用了“imx6ull.dtsi”文件，那么“imx6ull-seeed-npi.dts”设备树是否有两个根节点？其实不同文件的根节点会合并为一个。
+
+在根节点内部的“aliases {…}”、“chosen {…}”、“memory {…}”等等，是他的子节点。节点格式我们稍后会详细介绍。
+
+第三部分，对已经存在的设备树节点追加内容。第三部分的子节点比根节点下的子节点多了一个“&”，他表示在已经存在的子节点
+追加加数据。这些“已经存在的节点”可能定义在“imx6ull-seeed-npi.dts”文件也可能定义在“imx6ull-seeed-
+npi.dts”文件所包含的设备树文件里。本例程中的“&cpu0 {…}”、“&clks {…}”、“&fec1 {…}”等等，就是定义在“imx6ull.dtsi”。
+
+到目前为止我们知道设备树由一个根节点和众多子节点组成，子节点也可以包含其他节点，也就是子节点的子节点。设备树的组成很简单，下面我们重点介绍如何书写一个子节点，以及在驱动中如何从节点中获取数据。
+
+
+节点基本格式
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+
+设备树中的每个节点都按照以下约定命名：
+
+
+.. code-block:: c 
+    :caption: 节点基本格式
+    :linenos:
+
+    node-name@unit-address{
+    
+    属性1 = …
+    
+    属性2 = …
+    
+    属性13= …
+    
+    子节点…
+    
+    }
+
+
+node-name 节点名
+'''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''
+
+用于指定节点的名称。 它的长度为1至31个字符，只能由如下字符组成
+
+==== ========
+字符 描述
+==== ========
+0-9  数字
+a-z  小写字母
+A-Z  大写字母
+,    英文逗号
+.    英文句号
+\_   下划线
++    加号
+-    减号 
+==== ========
+
+另外，节点名应当使用大写或小写字母开头，并且能够描述设备类别。
+
+@unit-address
+''''''''''''''''''''''''''''''''''''''''''''''''''''
+
+符号“@”可以理解为是一个分割符，“unit-address”用于指定“单元地址”，它的值要和节点“reg”属性的第一个地址（节点属性我们稍后介绍）。如果节点
+没有“reg”属性值，直接省略“@unit-address”，注意，这时要求同级别的设备树下（相同级别的子节点）节点名要唯一,也就是同级别的子节点的节点名可以相同，但是要求
+“单元地址”不同。
+
+节点属性
+''''''''''''''''''''''''
+
+通常情况下一个节点包含多个属性信息，这些属性信息就是要传递到内核的“板级硬件描述信息”驱动中会通过一些API函数获取这些信息（后面会详细介绍）。一个节点中也可以包含自己的子节点。
+
+注意，根节点没有节点名和单元地址用“/”指代这是一个根节点。
+
+
+
+设备树中的一些基本概念
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+打开设备树，可以发现有些设备树节点并不是我们上一小节讲的那样。初学者可能感到疑惑，这一小节就学习一下这些“不同之处”。
+
+节点标签
+^^^^^^^^^^^^^^^^
+
+
+
+如下所示。
+
+
+
+.. code-block:: c 
+    :caption: 节点标签
+    :linenos:
+
+    cpu0: cpu@0 {
+    	compatible = "arm,cortex-a7";
+    	device_type = "cpu";
+    	reg = <0>;
+    }
+
+
+在节点名“cpu”前面多了个“cpu0”,“cpu0”就是我们所说的节点标签。节点标签的作用是便于向节点中追加内容。
+
+向已存在的节点追加内容
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+在我们编写的设备树源码“~/ebf-buster-linux/arch/arm/boot/dts/imx6ull-seeed-npi.dts”中存在如下所示的内容（大约120行的位置）。
+
+
+
+.. code-block:: c 
+    :caption: 向节点追加内容
+    :linenos:
+
+    &cpu0 {
+    	dc-supply = <&reg_gpio_dvfs>;
+    	clock-frequency = <800000000>;
+    };
+
+这些源码并不包含在根节点“/{…}”内，它们不是一个新的节点，而是向原有节点追
+加内容。以上方源码为例，“&cpu0”表示向“节点标签”为“cpu0”的节点追加数据，这个节点可能
+定义在本文件也可能定义在本文件所包含的设备树文件中，上方源码的“cpu0”定义在“imx6ull.dtsi”文件夹下。
+
+
+
+节点路径
+^^^^^^^^^^^^^^^^^^^^
+
+
+通过指定从根节点到所需节点的完整路径，可以唯一地标识设备树中的节点，“不同层次的
+设备树节点名字可以相同”。这有点类似于我们windows上的文件，一个路径唯一标识
+一个文件或文件夹，不同目录下的文件文件名可以相同。例如在“imx6ull.dtsi”文件内的cpu节点的路径标识为“/cpus/cpu”，
+如果在驱动中要获取CPU属性我们就会用到这个路径，当然我们也可以为cpu节点定义一个别名（稍后会介绍），直接通过这个别名访问它。
+
+别名子节点
+^^^^^
+
+别名子节点的作用就是为其他节点起一个别名，如下所示。
+
+
+.. code-block:: c 
+    :caption: 别名子节点
+    :linenos:
+
+    aliases {
+    	can0 = &flexcan1;
+    	can1 = &flexcan2;
+    	ethernet0 = &fec1;
+    	ethernet1 = &fec2;
+    	gpio0 = &gpio1;
+    	gpio1 = &gpio2;
+    	gpio2 = &gpio3;
+    	gpio3 = &gpio4;
+    	gpio4 = &gpio5;
+    	i2c0 = &i2c1;
+    	i2c1 = &i2c2;
+    	/*----------- 以下省略------------*/
+    }
+
+
+
+以“can0 = &flexcan1;”为例。“flexcan1”是一个节点的名字，设置别名后我么可以使用“can0”来指代flexcan1节点。在设备树中更多的是为节点添加标签，没有使用节点别名，别名的作用是“快速找到设备树节点”。在驱动中如果要查找一个节点，通常情况下我们可以使用“节点路径”一步
+步找到节点。也可以使用别名“一步到位”找到节点。
+
+chosen自节点
+^^^^^^^^^
+
+chosen子节点位于根节点下，如下所示
+
+.. code-block:: c 
+    :caption: chosen子节点
+    :linenos:
+
+    chosen {
+    	stdout-path = &uart1;
+    };
+
+
+chosen子节点不代表实际硬件，它主要用于给内核传递参数。这里只设置了“stdout-path =
+&uart1;”一条属性，表示系统输出使用uart1。此外这个节点还用作uboot向linux内核传递配置参数的“通道”，我们在Uboot中设置的参数就是通过这个节点传递到内核的，这部分内容是uboot和内核自动完成的，作为初学者我们不必深究。
+
+.. _节点属性-1:
+
+节点属性
+~~~~
+
+我们编写设备树最主要的内容是编写节点的节点属性，通常情况下一个节点代表一个设备，设备有哪些属性、怎么编写这些属性、在驱动中怎么引用这些属性是我们后面讲解的重点，这一小节只讲解设备节点有哪些可设置属性。节点属性有一些节点属性是所有节点共有的，一些作用于特定的节点，我们这里介绍那些共有的节点属性，其他节
+点属性使用到时再详细介绍。
+
+节点属性分为标准属性和自定义属性，也就是说我们在设备树中可以根据自己的实际需要定义、添加设备属性。标准属性的属性名是固定的，自定义属性名可按照要求自行定义。
+
+compatible属性
+''''''''''''
+
+属性值类型：字符串
+
+.. code-block:: c 
+    :caption: compatible属性
+    :linenos:
+
+    intc: interrupt-controller@a01000 {
+    	compatible = "arm,cortex-a7-gic";
+    	#interrupt-cells = <3>;
+    	interrupt-controller;
+    	reg = <0xa01000 0x1000>,
+    	      <0xa02000 0x100>;
+    };
+
+
+compatible属性值由一个或多个字符串组成，这些字符串定义了设备的特定编程模型。 此字符串列表用于设备和驱动的匹配，类似于平台总线的设备和驱动的匹配。
+
+model
+'''''
+
+属性值类型：字符串
+
+示例：
+
+.. code-block:: c 
+    :caption: model属性
+    :linenos:
+
+    model = "Seeed i.MX6 ULL NPi Board";
+
+
+
+compatible属性用于指定设备的制造商和型号，推荐使用“执照商, 型号”的格式，当然也可以自定义，本例子就没有使用这种格式。
+
+应由客户端程序用于设备驱动程序的选择。 属性值由空终止字符串的级联列表组成，从最特定到最一般。 它们允许设备表示其与一系列类似设备的兼容性，可能允许单个设备驱动程序与多个设备匹配。
+
+status
+''''''
+
+属性值类型：字符串
+
+示例：
+
+.. code-block:: c 
+    :caption: status属性
+    :linenos:
+
+    /* External sound card */
+    sound: sound {
+        status = "disabled";
+    };
+   
+
+
+状态属性用于指示设备的操作状态。 “操作状态”如下所示。
+
+========== ===========================================================================================================
+状态值     描述
+========== ===========================================================================================================
+"okay"     设备正常运行
+"disabled" 表明该设备目前尚未运行，但它可能在未来开始运行（例如，某些东西没有插入或关闭）。
+"fail"     表示设备不可操作。
+"fail-sss" 设备不可操作，原因是设备中检测到一个严重的错误，如果没有修复，它就不太可能运行。“sss”的值与具体的设备相关。
+========== ===========================================================================================================
+
+#address-cells 和 #size-cells
+''''''''''''''''''''''''''''
+
+属性值类型：u32
+
+示例：
+
+.. code-block:: c 
+    :caption: #address-cells和 #size-cells
+    :linenos:
+
+    soc {
+    	#address-cells = <1>;
+    	#size-cells = <1>;
+    	compatible = "simple-bus";
+    	interrupt-parent = <&gpc>;
+    	ranges;
+    	ocrams: sram@900000 {
+    		compatible = "fsl,lpm-sram";
+    		reg = <0x900000 0x4000>;
+    	};
+    };
+
+
+#address-cells和 #size-cells属性同时存在，在设备树测城西结构中，它们用在有子节点的设备节点（节点），用于设置子节点的“reg”属性的“书写格式”。
+
+补充：reg属性值由一串数字组成，如上图中的reg = <0x900000 0x4000>，ret属性的书写格式为reg = < cells cells cells cells cells cells…>，长度根据实际情况而定，这些数据分为地址数据（地址字段），长度数据（大小字段）。
+
+#address-cells，用于指定子节点reg属性“地址字段”所占的长度（单元格数量）。# size-cells，用于指定子节点reg属性“大小字段”所占的长度（单元格数量）。例如#address-cells=2，#address-cells=1，则reg内的数据含义为reg = <
+address address size address address size…>，#address-cells=1，#address-cells=1，则reg内的数据含义为reg = < address size address size address size…>。总之# size-
+cells和#address-cells决定了子节点的reg属性中哪些数据是“地址”，哪些数据是“长度”信息。
+
+reg属性
+'''''
+
+属性值类型：地址、长度数据对
+
+示例：
+
+与 #address-cells和 #size-cells示例相同。
+
+reg属性描述设备资源在其父总线定义的地址空间内的地址。通常情况下用于表示一块寄存器的起始地址（偏移地址）和长度，在特定情况下也有不同的含义。例如上例中#address-cells = <1>，#address-cells = <1>，reg = <0x900000
+0x4000>，0x900000表示的是地址，0x4000表示的是地址长度，这里的reg属性指定了起始地址为0x900000，长度为0x4000的一块地址空间。
+
+ranges
+''''''
+
+属性值类型：任意数量的 <子地址、父地址、地址长度>编码
+
+示例：
+
+
+.. code-block:: c 
+    :caption: ranges属性
+    :linenos:
+
+    soc {
+    		#address-cells = <1>;
+    		#size-cells = <1>;
+    		compatible = "simple-bus";
+    		interrupt-parent = <&gpc>;
+    		ranges;
+    
+    		busfreq {
+    			/*以下内容省略*/
+    
+    		};
+    }
+
+
+该属性提供了子节点地址空间和父地址空间的映射（转换）方法，常见格式是ranges = (字地址, 父地址, 转换长度)。如果父地址空间和字地址空间相同则无需转换，如示例中所示，只写了renges,内容为空，我们也可以直接省略renges属性。
+
+name和device_type
+''''''''''''''''
+
+属性值类型：字符串。
+
+示例：
+
+name和device_type
+
+
+.. code-block:: c 
+    :caption: name属性
+    :linenos:
+
+    example{
+    	name = "name"
+    }
+
+
+.. code-block:: c 
+    :caption: device_type属性
+    :linenos:
+
+    cpus {
+    		#address-cells = <1>;
+    		#size-cells = <0>;
+    
+    		cpu0: cpu@0 {
+    			compatible = "arm,cortex-a7";
+    			device_type = "cpu";
+    			reg = <0>;
+
+
+
+这两个属性很少用（已经被废弃），不推荐使用。name用于指定节点名，在旧的设备树中它用于确定节点名，现在我们使用的设备树已经弃用。device_type属性也是一个很少用的属性，只用在CPU和内存的节点上。如上例中所示，device_type用在了CPU节点。
+
+在中断、时钟部分也有自己的节点标准属性，随着深入的学习我们会详细介绍这些节点标准属性。
+
+在设备树中添加设备节点实验
+~~~~~~~~~~~~~
+
+通常情况下我们几乎不会从零开始写一个设备树，因为一个功能完善的设备树通常比较庞大，例如本教程引用的NXP官方编写的设备树“imx6ull.dtsi”就多达1000行，另外官方已经写好了一部分呢我们只需要引用官方写好的设备树，然后根据自己的实际情况修改即可。在实际应用中我们最常见的操作是向设备节点中增
+加一个节点、向现有设备节点追加数据、和编写设备树插件。
+
+这一小节不需要编写驱动程序，开发板上的系统保持不变。
+
+ 添加节点
+ ^^^^
+
+根据之前讲解，我们的系统默认使用的是“~/ebf-buster-linux/arch/arm/boot/dts/imx6ull-seeed-npi.dts”设备树，我们就在这个设备树里尝试增加一个设备节点，如下所示。
+
+
+
+.. code-block:: c 
+    :caption: 添加子节点
+    :linenos:
+
+    / {
+    	model = "Seeed i.MX6 ULL NPi Board";
+    	compatible = "fsl,imx6ull-14x14-evk", "fsl,imx6ull";
+    
+    	aliases {
+    		pwm0 = &pwm1;
+    		pwm1 = &pwm2;
+    		pwm2 = &pwm3;
+    		pwm3 = &pwm4;
+    	};
+    	/*-----------一下代码省略-------------*/
+    
+    	/*添加led节点*/
+    	led{
+    		/*-------------第一部分-----------*/
+    		#address-cells = <1>;
+    		#size-cells = <1>; 
+    
+    		/*-------------第二部分-----------*/
+    		rgb_led_red@0x0209C000{
+    			compatible = "fire,rgb_led_red";
+    			reg = <0x0209C000 0x00000020>;
+    			status = "okay";
+    		};
+    	};
+    };
+
+
+
+
+
+在我们在imx6ull-seeed-npi.dts设备树文件的根节点末尾新增了一个节点名为“led”的节点，里面只添加了几个基本属性，我们这里只是学习添加一个设备节点。
+
+在以上代码中，led节点的#address-cells = <1>，#size-cells = <1>，意味着它的子节点的reg属性里的数据是“地址”、“长度”交替的。
+
+第二部分是led 节点的子节点，它定义了三个属性分别为compatible、reg、status，这三个属性在 “节点属性”章节已经介绍。需要注意的是rgb属性，在父节点设置了#address-cells = <1>，#size-cells =
+<1>，所以这里0x0209C000表示的是地址（这里填写的是GPIO1控制寄存器的首地址），0x00000020表示的是地址长度。“rgb_led_red@0x0209C000”中的单元的地址0x0209C000要和reg属性的第一个地址一致。
+
+编译下载设备树
+^^^^^^^
+
+编译设备树
+'''''
+
+编译内核时会自动编译设备树，但是编译内核很耗时，所以我们推荐使用如下命令只编译设备树。
+
+命令：
+
+make ARCH=arm CROSS_COMPILE=arm-linux-gnueabihf- npi_v7_defconfig
+
+make ARCH=arm -j4 CROSS_COMPILE=arm-linux-gnueabihf- dtbs
+
+如果在内核源码中执行了make distclean 则必须执行第一条命令，它用于生成默认配置文件，如果执行过一次就没有必要再次执行，当然再次执行也没有什么问题。第二条命令开始编译设备树，参数“-j4”指定多少个线程编译，根据自己电脑实际情况设置，越大编译越快，当然也可以不设置，设备树编译本来就很快。
+
+编译成功后生成的设备树文件（.dtb）位于源码目录下的“./arch/arm/boot/dts”文件名为“imx6ull-seeed-npi.dtb”
+
+下载设备树
+'''''
+
+设备树“下载”有两种方法。第一种，像刷系统那样使用MFG工具将设备树烧写到开发板，这种方法比较繁琐但适用于SD卡、emmc、nand。第二种，将设备树使用nfs共享文件夹拷贝到开发板（其他工具也可以），挂载设备树和内核所在的磁盘，然后用新的设备树替换掉旧的。这种方法我们只测试了emmc，SD卡和na
+nd暂不支持使用这种方式。
+
+使用MFG工具烧录
+
+
+将编译生成的设备树imx6ull-seeed-npi.dtb拷贝得到MFG工具的相应目录（如果文件已存在则替换掉旧的），注意修改mfg工具的“cfg.ini”文件，具体烧录过程和使用MFG工具烧系统完全一致，这里不再介绍。
+
+在开发板中更新设备树文件
+
+
+如果使用emmc，推荐使用这种方式，将生成的设备树imx6ull-seeed-npi.dtb拷贝到开发板，然后执行如下命令挂载设备树所在磁盘。
+
+命令：
+
+mount /dev/mmcblk1p1 /mnt
+
+以上命令将mmcblk1p1磁盘挂载到“/mnt”目录下，mmcblk1p1磁盘保存的是内核和设备树，挂载成功后打开“/mnt”目录。如下所示。
+
+
+
+
+.. image:: ./media/driver002.png
+   :align: center
+   :alt: 找不到图片02|
+
+将我们编译生成的设备树重命名为“imx6ull-14x14-evk.dtb”替换掉“/mnt”目录下设备树文件即可。替换之后记得取消挂载，或者重新打开、关闭 “/mnt”目录，这样更改之后的内容会立即写入磁盘，重新启动即可。取消挂载命令如下：
+
+命令
+
+umount /dev/mmcblk1p1
+
+实验结果
+
+
+设备树中的设备树节点在文件系统中有与之对应的文件，位于“/proc/device-tree”目录。进入“/proc/device-tree”目录如下所示。
+
+.. image:: ./media/driver003.png
+   :align: center
+   :alt: 找不到图片03|
+
+接着进入led 文件夹，可以发现led节点中定义的属性以及它的子节点，如下所示。
+
+.. image:: ./media/driver004.png
+   :align: center
+   :alt: 找不到图片04|
+
+在节点属性中多了一个name，我们在led节点中并没有定义name属性，这是自从生成的，保存节点名。
+
+这里的属性是一个文件，而子节点是一个文件夹，我们再次进入“rgb_led_red@0x0209C000”文件夹，如下所示。
+
+.. image:: ./media/driver005.png
+   :align: center
+   :alt: 找不到图片05|
+
+同样这些属性是一个文件，我们可以使用“vi”命令查看这些属性文件，如下所示。
+
+.. image:: ./media/driver006.png
+   :align: center
+   :alt: 找不到图片06|
+
+.. image:: ./media/driver007.png
+   :align: center
+   :alt: 找不到图片07|
+
+至此，我们已经成功的在设备树中添加了一个名为“led”的节点。
+
+在驱动中获取设备树节点的属性
+~~~~~~~~~~~~~~
+
+在设备树中“节点”对应实际硬件中的设备，我们在设备树中添加了一个“led”节点，
+
+正常情况下我们可以从这个节点获取编写led驱动所用到的所有信息，例如led相关控制寄存器地址、led时钟控制寄存器地址等等。这一小节我们就开始学习如何从设备树的设备节点获取我们想要的数据。
+
+常用获取资源函数
+^^^^^^^^
+
+内核提供了一组函数用于从设备节点获取资源（设备节点中定义的属性）的函数，这些函数以of_开头，称为OF操作函数。常用的OF函数介绍如下：
+
+查找节点函数
+''''''
+
+根据节点路径寻找节点函数
+
+
+函数原型：
+
+struct device_node \*of_find_node_by_path(const char \*path)
+
+参数“path”，指定节点在设备树中的路径。
+
+返回值“device_node”结构体指针，如果查找失败则返回NULL，否则返回device_node类型的结构体指针，它保存着设备节点的信息。
+
+device_node机构体如下所示。
+
+
+
+.. code-block:: c 
+    :caption: device_node结构体
+    :linenos:
+
+    struct device_node {
+    	const char *name;  //节点名
+    	const char *type;  //设备类型
+    	phandle phandle;
+    	const char *full_name; //完整名字
+    	struct fwnode_handle fwnode;
+    
+    	struct	property *properties; //属性
+    	struct	property *deadprops;	/* removed properties */
+    	struct	device_node *parent; //父节点
+    	struct	device_node *child;  //子节点
+    	struct	device_node *sibling;
+    #if defined(CONFIG_OF_KOBJ)
+    	struct	kobject kobj;
+    #endif
+    	unsigned long _flags;
+    	void	*data;
+    #if defined(CONFIG_SPARC)
+    	const char *path_component_name;
+    	unsigned int unique_id;
+    	struct of_irq_controller *irq_trans;
+    #endif
+    };
+
+
+
+得到device_node结构体之后我们就可以使用其他of 函数获取节点的详细信息。
+
+根据节点名字寻找节点函数
+
+
+函数原型：
+
+struct device_node \*of_find_node_by_name(struct device_node \*from,const char \*name);
+
+参数from，指定从哪个节点开始查找，它本身并不在查找行列中，只查找它后面的节点，如果设置为NULL表示从根节点开始查找。
+
+参数name，要寻找的节点名。
+
+返回值：device_node类型的结构体指针，保存获取得到的节点。同样，如果失败返回NULL。
+
+根据节点类型寻找节点函数
+
+
+函数原型：
+
+struct device_node \*of_find_node_by_type(struct device_node \*from,const char \*type)
+
+类似of_find_node_by_name函数。
+
+参数from，指定从哪个节点开始查找，它本身并不在查找行列中，只查找它后面的节点，如果设置为NULL表示从根节点开始查找。
+
+参数type，要查找节点的类型，这个类型就是device_node-> type。
+
+返回值：device_node类型的结构体指针，保存获取得到的节点。同样，如果失败返回NULL。
+
+根据节点类型和compatible属性寻找节点函数
+
+
+函数原型：
+
+struct device_node \*of_find_compatible_node(struct device_node \*from,const char \*type, const char \*compatible)
+
+相比of_find_node_by_name函数增加了一个compatible属性作为筛选条件。
+
+参数from，指定从哪个节点开始查找，它本身并不在查找行列中，只查找它后面的节点，如果设置为NULL表示从根节点开始查找。
+
+参数type，要查找节点的类型，这个类型就是device_node-> type。
+
+参数compatible，要查找节点的compatible属性。
+
+返回值：device_node类型的结构体指针，保存获取得到的节点。同样，如果失败返回NULL。
+
+根据匹配表寻找节点函数
+
+
+函数原型：
+
+static inline struct device_node \*of_find_matching_node_and_match(
+
+struct device_node \*from,
+
+const struct of_device_id \*matches,
+
+const struct of_device_id \*\*match)
+
+参数from，指定从哪个节点开始查找，它本身并不在查找行列中，只查找它后面的节点，如果设置为NULL表示从根节点开始查找。
+
+参数matches，源匹配表，查找与该匹配表想匹配的设备节点。
+
+结构体struct of_device_id如下所示。
+
+
+.. code-block:: c 
+    :caption: of_device_id结构体
+    :linenos:
+
+   /*
+    * Struct used for matching a device
+    */
+   struct of_device_id {
+   	char	name[32];
+   	char	type[32];
+   	char	compatible[128];
+   	const void *data;
+   };
+
+
+
+
+可以看到，该结构体包含了更多的匹配参数，也就是说相比前三个寻找节点函数，这个函数匹配的参数更多，对节点的筛选更细。
+
+参数match，查找得到的结果。
+
+返回值：device_node类型的结构体指针，保存获取得到的节点。同样，如果失败返回NULL。
+
+寻找父节点函数
+
+
+函数原型
+
+struct device_node \*of_get_parent(const struct device_node \*node)
+
+参数node，指定谁（节点）要查找父节点。
+
+返回值：device_node类型的结构体指针，保存获取得到的节点。同样，如果失败返回NULL。
+
+寻找子节点函数
+
+
+函数原型
+
+struct device_node \*of_get_next_child(const struct device_node \*node,
+
+struct device_node \*prev)
+
+参数node，指定谁（节点）要查找它的子节点。
+
+参数prev，前一个子节点，寻找的是prev节点之后的节点。这是一个迭代寻找过程，例如寻找第二个子节点，这里就要填第一个子节点。参数为NULL 表示寻找第一个子节点。
+
+返回值：device_node类型的结构体指针，保存获取得到的节点。同样，如果失败返回NULL。
+
+这里介绍了7个寻找节点函数，这7个函数有一个共同特点——返回值类型相同。只要找到了节点就会返回节点对应的device_node结构体，在驱动程序中我们就是通过这个device_node获取设备节点的属性信息、顺藤摸瓜查找它的父、子节点等等。第一函数of_find_node_by_path与后面六个不
+同，它是通过节点路径寻找节点的，“节点路径”是从设备树源文件(.dts)中的到的。而中间四个函数是根据节点属性在某一个节点之后查找符合要求的设备节点，这个“某一个节点”是设备节点结构体（device_node），也就是说这个节点是已经找到的。最后两个函数与中间四个类似，只不过最后两个没有使用节点属性
+而是根据父、子关系查找。
+
+提取属性值的of函数
+''''''''''
+
+上一小节我们讲解了7个查找节点的函数，它们有一个共同特点，找到一个设备节点就会返回这个设备节点对应的结构体指针（device_node*）。这个过程可以理解为把设备树中的设备节点“获取”到驱动中。“获取”成功后我们再通过一组of函数从设备节点结构体（device_node）中获取我们想要的设备节点属
+性信息。
+
+查找节点属性函数
+
+
+函数原型
+
+struct property \*of_find_property(const struct device_node \*np,const char \*name,int \*lenp)
+
+参数np，指定要获取那个设备节点的属性信息。
+
+参数name，属性名。
+
+参数lenp，获取得到的属性值的大小，这个指针作为输出参数，这个参数“带回”的值是实际获取得到的属性大小。
+
+返回值：获取得到的属性。这是一个结构体，我们把它称为节点属性结构体，如下所示。失败返回NULL。
+
+
+
+.. code-block:: c 
+    :caption: property属性结构体
+    :linenos:
+
+    struct property {
+    	char	*name;  //属性名
+    	int	length;     //属性长度
+    	void	*value; //属性值
+    	struct property *next; //下一个属性
+    #if defined(CONFIG_OF_DYNAMIC) || defined(CONFIG_SPARC)
+    	unsigned long _flags;
+    #endif
+    #if defined(CONFIG_OF_PROMTREE)
+    	unsigned int unique_id;
+    #endif
+    #if defined(CONFIG_OF_KOBJ)
+    	struct bin_attribute attr;
+    #endif
+    };
+
+
+从这个结构体中我们就可以得到想要的属性值了。
+
+读取整型属性函数
+
+
+读取属性函数是一组函数，分别为读取8、16、32、64位数据。
+
+函数原型：
+
+//8位整数读取函数
+
+int of_property_read_u8_array(const struct device_node \*np, const char \*propname,
+
+u8 \*out_values, size_t sz)
+
+//16位整数读取函数
+
+int of_property_read_u16_array(const struct device_node \*np, const char \*propname,
+
+u16 \*out_values, size_t sz)
+
+//32位整数读取函数
+
+int of_property_read_u32_array(const struct device_node \*np, const char \*propname,
+
+u32 \*out_values, size_t sz)
+
+//64位整数读取函数
+
+int of_property_read_u64_array(const struct device_node \*np, const char \*propname,
+
+u64 \*out_values, size_t sz)
+
+这几个函数结构和用法是相同的，以8位读取为例介绍如下：
+
+参数np，指定要读取那个设备节点结构体，也就是说读取那个设备节点的数据。
+
+参数propname，指定要获取设备节点的哪个属性。
+
+参数out_values，这是一个输出参数，是函数的“返回值”，保存读取得到的数据。
+
+参数sz，这是一个输入参数，它用于设置读取的长度。
+
+返回值，成功返回0，错误返回错误状态码（非零值），-EINVAL（属性不存在），-ENODATA（没有要读取的数据），-EOVERFLOW（属性值列表太小）。
+
+简化后的读取整型属性函数
+
+
+这里的函数是对读取整型属性函数的简单封装，将读取长度设置为1。用法与读取属性函数完全一致，这里不再赘述。
+
+函数原型：
+
+//8位整数读取函数
+
+int of_property_read_u8 (const struct device_node \*np, const char \*propname,
+
+u8 \*out_values)
+
+//16位整数读取函数
+
+int of_property_read_u16 (const struct device_node \*np, const char \*propname,
+
+u16 \*out_values)
+
+//32位整数读取函数
+
+int of_property_read_u32 (const struct device_node \*np, const char \*propname,
+
+u32 \*out_values)
+
+//64位整数读取函数
+
+int of_property_read_u64 (const struct device_node \*np, const char \*propname,
+
+u64 \*out_values)
+
+读取字符串属性函数
+
+
+在设备节点中存在很多字符串属性，例如compatible、status、type等等，这些属性可以使用查找节点属性函数of_find_property来获取，但是这样比较繁琐。内核提供了一组用于读取字符串属性的函数，介绍如下：
+
+int of_property_read_string(const struct device_node \*np,const char \*propname,
+
+const char \*\*out_string)
+
+int of_property_read_string_index(const struct device_node \*np,const char \*propname,
+
+int index,const char \**out_string)
+
+第一个函数，介绍如下：
+
+参数np，指定要获取那个设备节点的属性信息。
+
+参数propname，属性名。
+
+参数out_string，获取得到字符串指针，这是一个“输出”参数，带回一个字符串指针。也就是字符串属性值的首地址。这个地址是“属性值”在内存中的真实位置，也就是说我们可以通过对地址操作获取整个字符串属性（一个字符串属性可能包含多个字符串，这些字符串在内存中连续存储，使用’\0’分隔），这个函数使用
+相对繁琐，推荐使用第二个。
+
+返回值：成功返回0，失败返回错误状态码。
+
+第二个函数介绍如下：
+
+相比第一函数增加了参数index，它用于指定读取属性值中第几个字符串，index从零开始计数。第一个函数只能得到属性值所在地址，也就是第一个字符串的地址，其他字符串需要我们手动修改移动地址，非常麻烦，推荐使用第二个函数。
+
+读取布尔型属性函数
+
+
+在设备节点中一些属性是BOOL型，当然内核会提供读取BOOL型属性的函数，介绍如下：
+
+static inline bool of_property_read_bool(const struct device_node \*np,
+
+const char \*propname)：
+
+参数np，指定要获取那个设备节点的属性信息。
+
+参数propname，属性名。
+
+返回值：true ,属性存在。false,其他。
+
+这个函数不按套路出牌，它不是读取某个布尔型属性的值，仅仅是读取这个属性存在或者不存在。如果想要或取值，可以使用之前讲解的“全能”函数查找节点属性函数of_find_property。
+
+内存映射相关of函数
+''''''''''
+
+在设备树的设备节点中大多会包含一些内存相关的属性，比如常用的reg属性。通常情况下，得到寄存器地址之后我们还要通过ioremap函数将物理地址转化为虚拟地址。现在内核提供了of函数，自动完成物理地址到虚拟地址的转换。介绍如下：
+
+void \__iomem \*of_iomap(struct device_node \*np, int index)
+
+参数np，指定要获取那个设备节点的属性信息。
+
+参数index，通常情况下reg属性包含多段，index 用于指定映射那一段，标号从0开始。；
+
+返回值：成功，得到转换得到的地址。失败返回NULL。
+
+内核也提供了常规获取地址的of函数，这些函数得到的值就是我们在设备树中设置的地址值。介绍如下：
+
+int of_address_to_resource(struct device_node \*dev, int index, struct resource \*r)
+
+参数np，指定要获取那个设备节点的属性信息。
+
+参数index，通常情况下reg属性包含多段，index 用于指定映射那一段，标号从0开始。
+
+参数r，这是一个resource结构体，是“输出参数”用于返回得到的地址信息。resource结构体如下所示：
+
+
+
+.. code-block:: c 
+    :caption: resource属性结构体
+    :linenos:
+
+    struct resource {
+    	resource_size_t start; //起始地址
+    	resource_size_t end;  //结束地址
+    	const char *name;    //属性名字
+    	unsigned long flags;
+    	unsigned long desc;
+    	struct resource *parent, *sibling, *child;
+    };
+
+
+从这个结构体比较简单，很容从中得到获取得到的具体信息。这里不再赘述。
+
+返回值，成功返回0，失败返回错误状态码。
+
+这里介绍了三类常用的of函数，这些基本满足我们的需求，其他of函数后续如果使用到我们在详细介绍。
+
+在驱动中获取节点属性实验
+~~~~~~~~~~~~
+
+本实验目的是演示如何使用上一小节讲解的of函数，进行本实验之前要先完成“在设备树中添加设备节点实验”，因为本实验就是从我们添加的节点中获取设备节点属性。
+
+本实验是一个简化的字符设备驱动，在驱动中没有实际操作硬件，仅在.open 函数中调用of函数获取设备树节点中的属性，获取成功后打印获取得到的内容。
+
+源码讲解
+^^^^
+
+程序源码如下所示，这里只列出了.open函数中的内容，其他与字符设备驱动类似，完整内容请参考本章配套源码“补充”。
+
+
+
+.. code-block:: c 
+    :caption: 获取节点属性实验
+    :linenos:
+
+   /*-------------------第一部分------------------*/
+   struct device_node	*led_device_node; //led的设备树节点
+   struct device_node  *rgb_led_red_device_node; //rgb_led_red 红灯节点
+   struct property     *rgb_led_red_property;    //定义属性结构体指针
+   int size = 0 ;
+   unsigned int out_values[18];  //保存读取得到的REG 属性值
+   
+   
+   
+   /*.open 函数*/
+   static int led_chr_dev_open(struct inode *inode, struct file *filp)
+   {
+       int error_status = -1;
+   
+       printk("\n open form device \n");
+   
+   
+   /*-------------------第二部分------------------*/
+       /*of 测试函数*/
+       led_device_node = of_find_node_by_path("/led");
+       if(led_device_node == NULL)
+       {
+           printk(KERN_EMERG "\n get led_device_node failed ! \n");
+           return -1;
+       }
+       /*根据 led_device_node 设备节点结构体输出节点的基本信息*/
+       printk(KERN_EMERG "name: %s",led_device_node->name); //输出节点名
+       printk(KERN_EMERG "child name: %s",led_device_node->child->name);  //输出子节点的节点名
+   
+   
+   /*-------------------第三部分------------------*/
+       /*获取 rgb_led_red_device_node 的子节点*/ 
+       rgb_led_red_device_node = of_get_next_child(led_device_node,NULL); 
+       if(rgb_led_red_device_node == NULL)
+       {
+           printk(KERN_EMERG "\n get rgb_led_red_device_node failed ! \n");
+           return -1;
+       }
+       printk(KERN_EMERG "name: %s",rgb_led_red_device_node->name); //输出节点名
+       printk(KERN_EMERG "parent name: %s",rgb_led_red_device_node->parent->name);  //输出父节点的节点名
+   
+   
+   /*-------------------第四部分------------------*/
+       /*获取 rgb_led_red_device_node 节点  的"compatible" 属性 */ 
+       rgb_led_red_property = of_find_property(rgb_led_red_device_node,"compatible",&size);
+       if(rgb_led_red_property == NULL)
+       {
+           printk(KERN_EMERG "\n get rgb_led_red_property failed ! \n");
+           return -1;
+       }
+       printk(KERN_EMERG "size = : %d",size);                      //实际读取得到的长度
+       printk(KERN_EMERG "name: %s",rgb_led_red_property->name);   //输出属性名
+       printk(KERN_EMERG "length: %d",rgb_led_red_property->length);        //输出属性长度
+       printk(KERN_EMERG "value : %s",(char*)rgb_led_red_property->value);  //属性值
+   
+   
+   /*-------------------第五部分------------------*/
+       /*获取 reg 地址属性*/
+       error_status = of_property_read_u32_array(rgb_led_red_device_node,"reg",out_values, 2);
+       if(error_status != 0)
+       {
+           printk(KERN_EMERG "\n get out_values failed ! \n");
+           return -1;
+       }
+       printk(KERN_EMERG"0x%08X ", out_values[0]);
+       printk(KERN_EMERG"0x%08X ", out_values[1]);
+   
+       return 0;
+   }
+
+
+
+测试代码大致分为5部分，介绍如下。
+
+第一部分，定义一些变量，用于保存读取得到的数据，在讲解of 函数时已经介绍了这些结构体这不再赘述。
+
+第二部分，使用“of_find_node_by_path”函数寻找“led”设备节点。参数是“led”的设备节点路径。获取成功后得到的是一个device_node类型的结构体指针，然后我们就可以从这个结构体中获得我们想要的数据。获取完整的属性信息可能还需要使用其他of函数。
+
+第三部分，获取 “led”节点的子节点。在第二部分我们得到了“led”节点的“设备节点结构体”这里就可以使用“of_get_next_child”函数获取它的子节点。当然我们也可以从“led”节点的“设备节点结构体”中直接读取得到它的第一个子节点。
+
+第四部分，使用“of_find_property”函数获取“rgb_led_red”节点的“compatible”属性。
+
+第五部分，使用“of_property_read_u32_array”函数获取reg属性，
+
+下载验证
+^^^^
+
+本小节配套源码位于“补充”，使用如下命令编译驱动程序。
+
+命令：
+
+make ARCH=arm CROSS_COMPILE=arm-linux-gnueabihf-
+
+使用如下命名编译测试应用程序：
+
+命令：
+
+arm-linux-gnueabihf-gcc <源文件路径> -o <目标文件路径>
+
+编译成功后将驱动.ko和应用程序拷贝到开发板，以例程为例如下所示。
+
+.. image:: ./media/driver008.png
+   :align: center
+   :alt: 找不到图片08|
+
+首先使用insmod 加载驱动，然后直接运行应用程序，如下所示。
+
+.. image:: ./media/driver009.png
+   :align: center
+   :alt: 找不到图片09|
+
+从上图中可以看到，驱动程序中得到了设备树中设置的属性值。
+
+.. |driver002| image:: media\driver002.png
+   :width: 5.76806in
+   :height: 0.83056in
+.. |driver003| image:: media\driver003.png
+   :width: 4.41611in
+   :height: 1.73937in
+.. |driver004| image:: media\driver004.png
+   :width: 4.48902in
+   :height: 2.5101in
+.. |driver005| image:: media\driver005.png
+   :width: 5.76806in
+   :height: 1.62639in
+.. |driver006| image:: media\driver006.png
+   :width: 5.76806in
+   :height: 0.90903in
+.. |driver007| image:: media\driver007.png
+   :width: 4.47861in
+   :height: 1.43732in
+.. |driver008| image:: media\driver008.png
+   :width: 5.76806in
+   :height: 1.08125in
+.. |driver009| image:: media\driver009.png
+   :width: 5.76806in
+   :height: 3.20278in
diff --git a/documentation/linux_driver/dynamic_device_tree.rst b/documentation/linux_driver/dynamic_device_tree.rst
new file mode 100644
index 0000000000000000000000000000000000000000..d23d06348fa500949caad0505e3339772aae5503
--- /dev/null
+++ b/documentation/linux_driver/dynamic_device_tree.rst
@@ -0,0 +1,210 @@
+.. vim: syntax=rst
+
+使用设备树插件实现RGB灯驱动
+---------------
+
+Linux4.4以后引入了动态设备树（Dynamic Device
+Tree），我们这里翻译为“设备树插件”。设备树插件可以理解为主设备树的“补丁”它动态的加载到系统中，并被内核识别。例如我们要在系统中增加RGB驱动，那么我们可以针对RGB这个硬件设备写一个设备树插件，然后编译、加载到系统即可，无需从新编译整个设备树。
+
+设备树插件是在设备树基础上增加的内容，我们之前讲解的设备树语法完全适用，甚至我们可以直接将之前编
+写的设备树节点复制到设备树插件里。具体使用方法介绍如下。
+本章配套源码和工具位于“~/linux_driver/dynamic_device_tree”目录下
+
+设备树插件格式
+~~~~~~~
+
+设备树插件拥有相对固定的格式，甚至可以认为它只是把设备节点加了一个“壳”编译后内核能够动态加载它。格式如下，具体节点省略。
+
+.. code-block:: c 
+    :caption: 设备树插件基本格式
+    :linenos:
+
+    /dts-v1/; ①
+    /plugin/; ②
+    
+     / {
+            fragment@0 {
+                target-path = "/"; ③
+                __overlay__ {
+                    /*在此添加要插入的节点*/
+    
+                };
+            };
+     };
+
+
+
+标号①处用于指定dts的版本。标号②表示允许使用未定义的引用并记录它们，设备树插件中可以引用主设备树中的节点，而这些“引用的节点”对于设备树插件来说就是未定义的，所以设备树插件应该加上“/plugin/”。标号③指定设备树插件的加载位置，默认我们加载到根节点下，既“target-path =
+"/"”。
+
+我们要插入的设备及节点或者要引用（追加）的设备树节点放在__overlay_\_ {…}；内。下面我们尝试将上一节编写的RGB灯节点使用设备 树的方式添加到系统中。
+
+创建RGB灯的设备树插件
+~~~~~~~~~~~~
+
+实现方法很简单，直接复制上一小节RGB灯的设备节点到设备树插件模板中，如下所示。
+
+.. code-block:: c 
+    :caption: rgb_led 设备树插件
+    :linenos:
+
+    /dts-v1/;
+    /plugin/;
+    
+    /*---------------第一部分--------------------*/
+    
+    #include "imx6ul-pinfunc.h"
+    
+    #include "dt-bindings/gpio/gpio.h"
+    
+    / {
+       fragment@0 {
+           target-path = "/";
+           __overlay__ {
+               /*-----------------第二部分----------------*/
+               rgb_led2{
+                   #address-cells = <1>;
+                   #size-cells = <1>;
+                   compatible = "fire,rgb_led21";
+                   /*红灯节点*/
+                   ranges;
+                   rgb_led_red@0x020C406C{
+                       compatible = "fire,rgb_led_red";
+                       reg = <0x020C406C 0x00000004
+                              0x020E006C 0x00000004
+                              0x020E02F8 0x00000004
+                              0x0209C000 0x00000004
+                              0x0209C004 0x00000004>;
+                       status = "okay";
+                   };
+                   /*绿灯节点*/
+                   rgb_led_green@0x020C4074{
+                       compatible = "fire,rgb_led_green";
+                       reg = <0x020C4074 0x00000004
+                              0x020E01E0 0x00000004
+                              0x020E046C 0x00000004
+                              0x020A8000 0x00000004
+                              0x020A8004 0x00000004>;
+                       status = "okay";
+                   };
+                   /*蓝灯节点*/
+                   rgb_led_blue@0x020C4074{
+                       compatible = "fire,rgb_led_blue";
+                       reg = <0x020C4074 0x00000004
+                              0x020E01DC 0x00000004
+                              0x020E0468 0x00000004
+                              0x020A8000 0x00000004
+                              0x020A8004 0x00000004>;
+                       status = "okay";
+                   };
+               };
+           };
+       };
+    };
+
+从以上代码可以看出，代码第一部分是RGB灯设备节点使用到的头文件，第二部分是我们复制、粘贴过来的RGB灯设备节点。简单两步，RGB灯的设备树插件已经做好了，下面重点是编译设备树插件并把设备树插件添加到系统。
+
+编译设备树插件
+~~~~~~~
+
+设备树插件与设备树一样都是使用DTC工具编译，只不过设备树编译为.dtb。而设备树插
+件需要编译为.dtbo。我们可以使用DTC编译命令编译生成.dtbot，但是这样比较繁琐、容
+易出错。我们提供一个编译工具，帮助完成这些繁琐  
+的工作，实现“一键式”编译。编译工具位于“~/linux_driver/dynamic_device_tree/ebf-linux-dtoverlays-master”。将ebf
+-linux-dtoverlays-master文件夹复制到linux主机的任意文件夹。使用之前要安装编译工具，执行如下命令安装。
+
+.. code-block:: sh
+   :linenos:
+
+   sudo apt-get install device-tree-compiler
+
+要编译的设备树插件源文件放在“~/ebf-linux-dtoverlays-master/overlays/ebf”目录下，然后回
+到编译工具的根目录“~/ebf-linux-
+dtoverlays-master/”执行“make”即可。生成的.dtbo位于“~/ebf-linux-dtoverlays-master/output”目录
+下。例如本章的RGB设备树插件为“imx-fire-rgb-led-overlay.dts”将其拷贝到“~/ebf-linux-
+dtoverlays-master/overlays/ebf”目录下，编译之后就会在“~/ebf-linux-dtoverlays-master/output”目录
+下生成同名的.dtbo文件。得到.dtbo后，下一步就是将其加载到系统中。
+
+将设备树插件加入系统
+~~~~~~~~~~
+
+上一小节我们编译生成了.dtbo。.dtbo 可以被动态的加载到系统，这一小节介绍两种将设备树插件加入系统的方法。
+
+使用echo命令加载
+^^^^^^^^^^
+
+linux内核从4.4开始支持设备号树插件，支持并不代表默认开启。所以我们使用之前要配置内核开启这个功能。如果使用的是我们提供的debian镜像（无论哪个版本）都是开启过了，无需再配置内核并重新编译。假设使用的是debina镜像，下面介绍具体的加载步骤。
+
+首先将.dtbo复制到开发板的“/lib/firmware”目录下，执行如下命令，创建一个文件夹。
+
+命令：
+
+.. code-block:: sh
+   :linenos:
+
+   mkdir /sys/kernel/config/device-tree/overlays/<文件夹名>
+
+该命令的作用很明显，只是在“/sys/kernel/config/device-tree/overlays/”目录下创建了一个文件夹，这个文件夹的名字可以任意定义，最好能反应对应的设备，例如本例中要插入RGB灯的设备树插件，则文件夹命名为rgb_led。
+
+文件夹创建成功后使用“echo”命令将设备树插件“放入”刚刚创建的文件夹。命令如下。
+
+命令：
+
+.. code-block:: sh
+   :linenos:
+
+   echo <.dtbo位置 > >/sys/kernel/config/device-tree/overlays/<刚刚创建的文件夹>/path
+
+例如我们的.dtbo放在文件名为“imx-fire-rgb-led-overlay.dtbo”，并且刚刚创建的文件夹为rgb_led.则命令应当为“echo /lib/firmware/imx-fire-rgb-led-overlay.dtbo >/sys/kernel/config/device-
+tree/overlays/rgb_led/path”（排版原因，命令在同一行imx-fire-rgb-led-overlay.dtbo之间没有空格）。
+
+执行该命令可能会出现一个警告，直接忽略即可。加载过程中如果不出错不会输出提示信息。
+
+和设备树相同，加载成功后就可以在“/proc/device-tree”目录下找到与插入的设备树节点同名的文件夹，进入该文件夹还可以看到该节点拥有的属性以及它的子节点，如下所示。
+
+
+.. image:: ./media/dynami002.png
+   :align: center
+   :alt: 02|
+
+
+进入rgb_led 目录，如下所示。
+
+
+.. image:: ./media/dynami003.png
+   :align: center
+   :alt: 02|
+
+
+看到这些文件，证明已经加载成功了。
+
+将设备树插件写入uEnv.txt配置文件
+^^^^^^^^^^^^^^^^^^^^
+
+上一小节我们使用echo命令加载设备树插件到系统，采用这种方式每次重启后都要重新加载设备树插件。将设备树插件写入uEnv.txt配置文件系统启动过程中自动从uEnv.txt读取要加载的设备树插件，我们也不用创建文件夹。使用方法介绍如下：
+
+与使用 echo命令加载相同，需要将要加载的.dtbo放入“/lib/firmware”，然后打开位于“/boot”目录下的uEnv.txt文件，如下所示。
+
+.. image:: ./media/dynami004.png
+   :align: center
+   :alt: 02|
+
+
+
+从上图可以看出在uEnv.txt文件夹下有很多被屏蔽的设备树插件，这些设备树插件是烧写系统时自带的插件，为避免它们干扰我们的实验，这里把它们全部屏蔽掉。如果要将RGB的设备树插件写入uEnv.txt也很简单，参照着写即可。书写格式为“dtoverlay=<设备树插件路径>”。修改完成后保存、退出。执
+行reboot命令重启系统。正常情况下我们可以在“/proc/device-tree”找与插入的设备节点同名的文件夹。
+
+加载RGB灯驱动
+~~~~~~~~
+
+驱动程序和应用程序的使用方法与上一章完全相同，可直接使用上一章的驱动和测试应用程序完成实验，实验现象完全相同。
+
+.. |dynami002| image:: media\dynami002.png
+   :width: 5.76806in
+   :height: 1.55903in
+.. |dynami003| image:: media\dynami003.png
+   :width: 5.76806in
+   :height: 1.07431in
+.. |dynami004| image:: media\dynami004.png
+   :width: 5.76806in
+   :height: 2.73333in
diff --git a/documentation/linux_driver/gpio_subsystem.rst b/documentation/linux_driver/gpio_subsystem.rst
new file mode 100644
index 0000000000000000000000000000000000000000..4780eac2057609b73aa0b025d88d5b267256db59
--- /dev/null
+++ b/documentation/linux_driver/gpio_subsystem.rst
@@ -0,0 +1,971 @@
+.. vim: syntax=rst
+
+pinctrl子系统和gpio子系统
+------------------
+
+本章将会使用GPIO子系统实现LED驱动，GPIO子系统要用到pinctrl子系统所以本章将pinctrl子系统和GPIO子系统放在一块讲解。
+
+pinctrl子系统
+~~~~~~~~~~
+
+从名字不难看出pinctrl子系统主要用于管理芯片（以下简称SOC）的引脚（pin）。imx6ull芯片拥有众多的片上外设，而大多数外设需要通过芯片的PIN（引脚）与外部设备（器件）相连进而实现特定的功能。例如我们熟悉的IIC、SPI、LCD、USDHC、等等。imx6ull芯片的可用引脚（除去电源
+引脚和特定功能引脚）数量是有限的，为充分发挥芯片性能，提高硬件设计的灵活性，通常情况下每个外设的功能引脚有多个外部引脚可选，以IIC1为例，如下图所示。
+
+
+
+
+.. image:: ./media/gpiosu002.png
+   :align: center
+   :alt: 总线结构02|
+
+IIC的SCL和SDA都有三个引脚可选，在设计硬件时我们可以根据需要灵活的选择其中的一个。硬件设计完成后片上外设使用的引脚就已经确定了，假设在硬件设计中IIC1的SCL和SDA分别连接到UART4_TX_DATA和UART4_RX_DATA，从引脚名字可以看出这两个引脚是UART4的接收、发送引脚并
+不是用作IIC1的SCL和SDA，无论是裸机还是驱动，一般首先要设置引脚的复用功能并且设置引脚的PAD属性（驱动能力、上下拉等等）。
+
+在pinctrl子系统出现之前，在驱动程序中我们需要手动设置每个引脚的复用功能，这样不仅增加了工作量而且编写的驱动程序不方便移植，可重用性差。更糟糕的是由于缺乏对引脚的统一管理，容易出现引脚的重复定义。还以I2C1为例，假设我们在I2C1的驱动中将UART4_RX_DATA引脚和UART4_TX_D
+ATA引脚复用为SCL和 SDA，恰好在编写UART4驱动驱动时没有注意到UART4_RX_DATA引脚和UART4_TX_DATA引脚已经被使用，在驱动中又将其初始化为UART4_RX和UART4_TX，这样IIC1驱动将不能正常工作，并且这种错误很难被发现。
+
+简单来说pinctrl子系统用于帮助我们管理芯片引脚并自动完成引脚的初始化，而我们要做的只是在设备树中按照规定的格式写出想要的配置参数。
+
+pinctrl子系统编写格式以及引脚属性详解
+^^^^^^^^^^^^^^^^^^^^^^
+
+本章使用的内核以及设备树与上一章相同，首先我们会介绍如何将RGB灯的三个引脚添加到pinctrl子系统中，以及各个参数的含义，修改完成后编译并下载到开发板验证修改是否成功。
+
+本小节使用的设备树位于“~/ebf-buster-linux/arch/arm/boot/dts/imx6ull-seeed-npi.dts”。打开imx6ull-seeed-npi.dts，在文件中搜索“&iomuxc”找到设备树中引用“iomuxc”节点的位置如下所示。
+
+
+
+.. code-block:: c 
+    :caption: imx6ull-seeed-npi.dts中iomuxc部分
+    :linenos:
+
+    &iomuxc {
+    	pinctrl-names = "default";
+    	pinctrl-0 = <&pinctrl_hog_1>;
+    
+    
+    
+    	pinctrl_gpmi_nand: gpmi-nand {
+    			fsl,pins = <
+    				MX6UL_PAD_NAND_CLE__RAWNAND_CLE         0xb0b1
+    				MX6UL_PAD_NAND_ALE__RAWNAND_ALE         0xb0b1
+    				MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B       0xb0b1
+    				/*------------以下省略-----------------*/
+    			>;
+    		};
+    
+    	pinctrl_hog_1: hoggrp-1 {
+    		fsl,pins = <
+    			MX6UL_PAD_UART1_RTS_B__GPIO1_IO19	0x17059 /* SD1 CD */
+    			MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT	0x17059 /* SD1 VSELECT */
+    			MX6UL_PAD_GPIO1_IO09__GPIO1_IO09        0x17059 /* SD1 RESET */
+    		>;
+    	};
+    
+    	pinctrl_enet1: enet1grp {
+    		fsl,pins = <
+    			MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN	0x1b0b0
+    			MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER	0x1b0b0
+    			MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00	0x1b0b0
+    			/*------------以下省略-----------------*/
+    		>;
+    	};
+    
+    	pinctrl_enet2: enet2grp {
+    		fsl,pins = <
+    			MX6UL_PAD_GPIO1_IO07__ENET2_MDC		0x1b0b0
+    			MX6UL_PAD_GPIO1_IO06__ENET2_MDIO	0x1b0b0
+                /*------------以下省略-----------------*/
+    		>;
+    	};
+    
+    	pinctrl_uart1: uart1grp {
+    		fsl,pins = <
+    			MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
+    			MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
+    		>;
+    	};
+
+
+iomuxc节点定义在imx6ull.dtsi设备树内，在这里通过“&iomuxc”在“iomuxc”节点下追加内容。结合设备树源码介绍如下：
+
+“pinctrl-names”标识，指定PIN的状态列表，默认设置为“default”。“pinctrl-0 = <&pinctrl_hog_1>”是支持热插拔相关我们暂时不用理会。其余源码就是pinctrl子节点，它们都是按照一定的格式规范编写，以源码最后“pinctrl_uart1”节点为例介绍如下：
+
+.. image:: ./media/gpiosu003.png
+   :align: center
+   :alt: 总线结构03|
+
+和其他子节点一样，“pinctrl_uart1”子节点按照固定的格式编写，提取格式框架如下所示。
+
+
+.. code-block:: c 
+    :caption: pinctrl子节点格式
+    :linenos:
+
+    pinctrl_自定义名字: 自定义名字 {
+    	fsl,pins = <
+    		引脚复用宏定义   PAD（引脚）属性
+    		引脚复用宏定义   PAD（引脚）属性
+    	>;
+    };    
+    
+
+
+如果我们添加自己的子节点按照上面的格式框架编写即可。我们重点讲解上图的标号3处的内容，它是我们编写的主要内容-添加PIN配
+置信息。
+
+每个引脚使用一条配置信息，每条配置信息分为两部分，直观上看第一部分是一个宏定义，暂且称为引脚
+复用宏定义，第二部分是一个16进制数，用于设置PAD属性值。以上图的第一条配置信息为例说明如下所示。
+
+.. code-block:: c 
+    :caption: 引脚配置信息
+    :linenos:
+
+    MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
+
+**MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX宏定义**
+
+
+MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX是定义在“~/ebf-buster-linux/arch/arm/boot/dts/imx6ul-pinfunc.h”文件内的一个宏定义，如下图所示。
+
+.. image:: ./media/gpiosu004.png
+   :align: center
+   :alt: 总线结构04|
+
+从上图可以看出以“MX6UL_PAD_UART1_TX_DATA__xxx”命名的宏定义共有8个，结合我们之前讲解的引脚复用选择寄存器很容易联想到这就是“UART1_TX_DATA”引脚的8个复用功能，而宏定义“MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX”将“UART
+1_TX_DATA”引脚复用为UART1的TX引脚。每个宏定义后面有5个参数，名字依次为mux_reg、conf_reg、input_reg、mux_mode、input_val。如果将宏定义展开则在设备树中每条配置信息实际是6个参数，由于第6个参数需要根据实际需要设置所以并没有把它放到宏定义里
+面。以MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX为例，宏定义中5个参数参数介绍如下：
+
+1. mux_reg和mux_mode，mux_reg是引脚复用选择寄存器偏移地址，mux_mode是引脚复用选择寄存器模式选择位的值。UART1_TX引脚复用选择寄存器IOMUXC_SW_MUX_CTL_PAD_UART1_TX_DATA定义如下所示。
+
+.. image:: ./media/gpiosu005.png
+   :align: center
+   :alt: 总线结构05|
+
+mux_reg = 0x0084与IM6ULL用户手册偏移地址一致, mux_mode = 0。设置复用选择寄存器IOMUXC_SW_MUX_CTL_PAD_UART1_TX_DATA[MUX_MODE] = 0，将其复用为UART1_TX功能。
+
+2. conf_reg，引脚（PAD）属性控制寄存器偏移地址。与引脚复用选择寄存器不同，引脚属性寄存器应当根据实际需要灵活的配置，所以它的值并不包含在宏定义中，它的值是我们上面所说的“第六个”参数。UART1_TX引脚属性控制寄存器IOMUXC_SW_PAD_CTL_PAD_UART1_TX
+   _DATA如下所示。
+
+.. image:: ./media/gpiosu006.png
+   :align: center
+   :alt: 总线结构06|
+
+从上图可以看到conf_reg = 0x0310对应UART1_TX引脚的引脚属性寄存器的偏移地址。而这个寄存器包含很多配置项（上图中是部分配置项），这些配置项在裸机部分有详细介绍，寄存器的值就是上面所说的“第六个”参数。
+
+3. input_reg和input_val，input_reg暂且称为输入选择寄存器偏移地址。input_val是输入选择寄存器的值。这个寄存器只有某些用作输入的引脚才有，正如本例所示，UART1_TX用作输出，所以这两个参数都是零。“输入选择寄存器”理解稍微有点复杂，结合下图介绍如下。
+
+.. image:: ./media/gpiosu007.png
+   :align: center
+   :alt: 总线结构07|
+
+从上图可以看出，如果引脚用作输出，我们我们只需要配置引脚复用选择寄存器和引脚PAD属性设置寄存器。如果用作输入时还增加了引脚输入选择寄存器，输入选择寄存器的作用也很明显，在多个可选输入中选择一个连接到片上外设。
+
+**引脚（PAD）属性值**
+
+
+在pinctrl子系统中一条配置信息由一个宏定义和一个参数组成，将宏定义展开就是六个参数。结合上图不难发现这6个参数就是IOMUX相关的三个寄存器偏移地址和寄存器的值(引脚用作输出时实际只有四个有效，输入选择寄存器偏移地址和它的值全为0)，至于为什么要将pad属性寄存器的值单独列出，前面也说过了，pad属性配置选项非常多，配置灵活。在pinctrl子系统中添加的PAD属
+性值就是引脚（PAD）属性设置寄存器的值（16进制）。有关PAD属性设置内容已经在裸机部分GPIO章节详细介绍这里不再赘述。
+
+将RGB灯引脚添加到pinctrl子系统
+^^^^^^^^^^^^^^^^^^^^
+
+本小节假设没有看过裸机部分RGB灯章节，我们从看原理图开始，一步步将RGB灯用到的三个引脚添加到pinctrl子系统中。
+
+查找RGB灯使用的引脚
+'''''''''''
+
+RGB灯对应的原理图如下所示。
+
+.. image:: ./media/gpiosu008.png
+   :align: center
+   :alt: 总线结构08|
+
+根据网络名在核心板上找到对应的引脚，如下。
+
+rgb_led_red: GPIO1_IO04
+
+rgb_led_green: CSI\_HSYNC
+
+rgb_led_blue: CSI_VSYNC
+
+找到引脚配置宏定义
+'''''''''
+
+这些引脚都将被复用为GPIO，用作驱动LED灯。首先要在“~/ebf-buster-linux/arch/arm/boot/dts/imx6ul-pinfunc.h”文件内找到对应的宏定义，以CSI_HSYNC引脚为例，在imx6ul-pinfunc.h中直接搜索“CSI_HSYNC”找到如下结果，
+
+.. image:: ./media/gpiosu009.png
+   :align: center
+   :alt: 总线结构09|
+
+同一个引脚的可选复用功能是连续排布的，我们要将其复用为GPIO，所以选择“MX6UL_PAD_CSI_HSYNC__GPIO4_IO20”即可。
+
+其他的两个引脚最终得到的结果如下：
+
+
+
+CSI_HSYNC：MX6UL_PAD_CSI_HSYNC__GPIO4_IO20
+
+CSI_VSYNC：MX6UL_PAD_CSI_VSYNC__GPIO4_IO19
+
+设置引脚属性
+''''''
+
+我们要写入到设备树中的引脚属性实际就是引脚属性设置寄存器的值。引脚属性配置项很多，以GPIO1_IO04为例如下所示。
+
+.. image:: ./media/gpiosu010.png
+   :align: center
+   :alt: 总线结构10|
+
+.. image:: ./media/gpiosu011.png
+   :align: center
+   :alt: 总线结构11|
+
+实际编程中我们几乎不会手动设置每一个配置项然后再将其组合成一个16进制数，通常情况下我们直接参照官方的设置，如果有需要在对个别参数进行修改。通常情况下用作GPIO的引脚PAD属性设置为“0x000010B1”
+
+在iomuxc节点中添加pinctrl子节点
+''''''''''''''''''''''
+
+添加子节点很简单，我们只需要将前面选择好的配置信息按照之前讲解的格式写入到设备树中即可，添加完成后如下所示。
+
+
+
+.. code-block:: c 
+    :caption: 新增pinctrl子节点
+    :linenos:
+
+    &iomuxc {
+    	pinctrl-names = "default";
+    	pinctrl-0 = <&pinctrl_hog_1>;
+    
+    	/*----------新添加的内容--------------*/
+    	pinctrl_rgb_led:rgb_led{
+    			fsl,pins = <
+    				MX6UL_PAD_GPIO1_IO04__GPIO1_IO04	0x000010B1 
+    				MX6UL_PAD_CSI_HSYNC__GPIO4_IO20	    0x000010B1 
+    				MX6UL_PAD_CSI_VSYNC__GPIO4_IO19	    0x000010B1 
+    			>;
+    		};
+
+
+
+新增的节点名为“rgb_led”，名字任意选取，长度不要超过32个字符，最好能表达出节点的
+作用。"pinctrl_rgb_led"节点标签，“pinctrl_”是固定的格式，后面的内容自定义的，我们将通过这个标签引用这个节点。  
+
+
+GPIO子系统
+~~~~~~~
+
+上一小节我们将RGB灯使用的三个引脚添加到了pinctrl子系统中，正常情况下系统会根据
+我们添加的配置信息将引脚初始化GPIO，初始化完成后就该GPIO子系统登场了。
+
+会想一下，如果没有使用GPIO子系统我们是怎样控制led灯的。首先要获取RGB灯用到
+的GPIO配置寄存器的地址（如果是物理地址还要转化为虚拟地址），然后手动的读、改、写这些寄存器实现控制RGB灯的目的。有了GPIO子系统之后这部分工作
+由GPIO子系统帮我们完成，我们只需要调用GPIO子系统提供的API函数即可。
+
+要使用GPIO子系统首先按照要求在设备树中添加设备节点，然后在程序中使用GPIO子系统提供的API实现特定的GPIO功能。
+
+在设备树中添加RGB灯的设备树节点
+^^^^^^^^^^^^^^^^^
+
+
+相比之前led灯的设备树节点(没有使用GPIO子系统)，这里只需要增加GPIO属性定义。基于GPIO子系统的rgb_led设备树节点
+添加到“~/ebf-buster-linux/arch/arm/boot/dts/imx6ull-seeed-npi.dts”设备树的根节点内。
+添加完成后的设备树如下所示。
+
+
+
+.. code-block:: c 
+    :caption: 设备树中添加rgb_led节点
+    :linenos:
+
+    /*添加rgb_led节点*/
+    rgb_led{
+    	#address-cells = <1>;
+    	#size-cells = <1>;
+    	pinctrl-names = "default";
+    	compatible = "fire,rgb-led";
+    	pinctrl-0 = <&pinctrl_rgb_led>;
+    	rgb_led_red = <&gpio1 4 GPIO_ACTIVE_LOW>;
+    	rgb_led_green = <&gpio4 20 GPIO_ACTIVE_LOW>;
+    	rgb_led_blue = <&gpio4 19 GPIO_ACTIVE_LOW>;
+    	status = "okay";
+    };
+
+以上代码第6行，设置“compatible”属性值，根据之前讲解这个属性值要和驱动程序中设置的一致，这样才能和驱动匹配。第7行，指定RGB灯的引脚pinctrl信息，上一小节我们定义了pinctrl节点，并且标签设置为“pinctrl_rgb_led”，在这里我们引用了这个pinctrl信息。代码
+第8到12行指定引脚使用的哪个GPIO,编写格式如下所示。
+
+.. image:: ./media/gpiosu012.png
+   :align: center
+   :alt: 总线结构12|
+
+标号①，设置引脚名字，如果使用GPIO子系统提供的API操作GPIO,在驱动程序中会
+用到这个名字，名字是自定义的。标号②，指定GPIO组，标号③指定GPIO编号。编号④，这是一个宏定义，指定有效电平，低电平有效选择“GPIO_ACTIVE_LOW”高电平有效选择“GPIO_ACTIVE_HIGH”
+。
+
+编译、下载设备树验证修改结果
+^^^^^^^^^^^^^^
+
+前两小节我们分别在设备树中将RGB灯使用的引脚添加到pinctrl子系统，然
+后又在设备树中添加了rgb_led设备树节点。这一小节将会编译、下载修改后的设备树，用新的设备树启动系统，然后检查是否有rgb_led设备树节点产生。
+
+编译内核时会自动编译设备树，我们可以直接重新编译内核，这样做的缺点是编译时间会很长。如果内核已经成功编译过一次并且没有执行“make distclean”命令清理内核，我们可以
+直接在内核目录下（~/ebf-buster-linux）执行如下命令，只编译设备树：
+
+命令：
+
+.. code-block:: sh
+   :emphasize-lines: 1
+   :linenos:
+
+   make ARCH=arm CROSS_COMPILE=arm-linux-gnueabihf- dtbs
+
+如果执行了“make distclean”清理了内核，那么就需要在内核目录下执行如下命令重新配置内核（如果编译设备树出错也可以先清理内核然后执行如下命令尝试重新编译）。
+
+命令：
+
+
+.. code-block:: sh
+   :emphasize-lines: 1
+   :linenos:
+
+   make ARCH=arm CROSS_COMPILE=arm-linux-gnueabihf- npi_v7_defconfig
+   make ARCH=arm CROSS_COMPILE=arm-linux-gnueabihf- dtbs
+
+
+编译成功后会在“/ebf-buster-linux/arch/arm/boot/dts”目录下生成“imx6ull-seeed-npi.dtb”将其烧录到开发板，使用新的设备树启动之后正常情况下会在开发板的“/proc/driver-tree”目录下生成“rgb_led”设备树节点。如下所示。
+
+.. image:: ./media/gpiosu013.png
+   :align: center
+   :alt: 总线结构13|
+
+GPIO子系统常用API函数讲解
+^^^^^^^^^^^^^^^^
+
+之前两小节我们修改设备树并编译、下载到开开发板。设备树部分已经完成了，这里介绍GPIO子系统常用的几个API函数，然后就可以使用GPIO子系统编写RGB驱动了。
+
+**1. 获取GPIO编号函数of_get_named_gpio**
+
+
+GPIO子系统大多数API函数会用到GPIO编号。GPIO编号是of_get_named_gpio函数从设备树中获取的。
+
+**函数原型：**
+
+.. code-block:: sh
+   :emphasize-lines: 1
+   :linenos:
+
+   int of_get_named_gpio(struct device_node \*np, const char \*propname, int index)
+
+**函数参数：**
+
+np：指定设备节点。
+
+propname：GPIO属性名，与设备树中定义的属性名对应。
+
+index：引脚索引值，在设备树中一条引脚属性可以包含多个引脚，该参数用于指定获取那个引脚。
+
+**返回值：**
+
+成功，返回获取的GPIO编号（这里的GPIO编号是根据引脚属性生成的一个非负整数），失败返回负数。
+
+**2. GPIO申请函数gpio_request**
+
+**函数原型：**
+
+.. code-block:: c
+   :emphasize-lines: 1
+   :linenos:
+
+   static inline int gpio_request(unsigned gpio, const char \*label);
+
+**函数参数：**
+
+gpio，要申请的GPIO编号，该值是函数of_get_named_gpio的返回值。
+
+label，引脚名字，相当于为申请得到的引脚取了个别名。
+
+**返回值：**
+
+成功，返回0，失败返回负数。
+
+**3. GPIO释放函数**
+
+**函数原型：**
+
+.. code-block:: c
+   :emphasize-lines: 1
+   :linenos:
+
+   static inline void gpio_free(unsigned gpio);
+
+该函数与gpio_request是一对，一个申请，一个释放。一个GPIO只能被申请一次，所以不再使用某一个引脚时一定要调用gpio_request函数将其释放掉。
+
+**函数参数：**
+
+gpio：要释放的GPIO编号。
+
+**4. GPIO输出设置函数gpio_direction_output**
+
+函数用于将引脚设置为输出模式。
+
+**函数原型：**
+
+.. code-block:: c 
+   :emphasize-lines: 1
+   :linenos:
+
+   static inline int gpio_direction_output(unsigned gpio , int value)；
+
+**函数参数：**
+
+gpio，要设置的GPIO的编号。
+
+value，输出值，1，表示高电平。0表示低电平。
+
+**返回值：**
+
+成功，返回0，失败返回负数。
+
+**5. GPIO输入设置函数gpio_direction_input**
+
+gpio_direction_output与gpio_direction_input是一对，前者将引脚设置为输出，后者用于将引脚设置为输入。
+
+**函数原型：**
+
+
+.. code-block:: c
+   :emphasize-lines: 1
+   :linenos:
+
+   static inline int gpio_direction_input(unsigned gpio)
+
+**函数参数：**
+
+gpio，要设置的GPIO的编号。
+
+**返回值：**
+
+成功，返回0，失败返回负数。
+
+**6. 获取GPIO引脚值函数gpio_get_value**
+
+无论引脚被设置为输出或者输入都可以用该函数获取引脚的当前状态。
+
+**函数原型：**
+
+.. code-block:: c
+   :emphasize-lines: 1
+   :linenos:
+
+   static inline int gpio_get_value(unsigned gpio);
+
+**函数参数：**
+
+gpio，要获取的GPIO的编号。
+
+**返回值：**
+
+大于等于零，表示获取得到的引脚状态。小于零，获取失败。
+
+**7. 设置GPIO输出值gpio_set_value**
+
+该函数只用于哪些设置为输出模式的GPIO.
+
+**函数原型：**
+
+.. code-block:: c
+   :emphasize-lines: 1
+   :linenos:
+
+   static inline int gpio_direction_output(unsigned gpio , int value)；
+
+**函数参数**
+
+gpio，设置的GPIO的编号。
+
+value，设置的输出值，为1输出高电平，为0输出低电平。
+
+**返回值：**
+
+成功，返回0，失败返回负数。
+
+我们使用以上函数就可以在驱动程序中控制IO口了。
+
+基于GPIO子系统的RGB程序编写
+~~~~~~~~~~~~~~~~~
+
+程序包含两部分，第一部分是驱动程序，驱动程序在平台总线基础上编写。第二部分是一个简单的测试程序，用于测试驱动是否正常。
+
+驱动程序编写
+^^^^^^
+
+驱动程序大致分为三个部分，第一部分，编写平台设备驱动的入口和出口函数。第二部分，编写平台设备的.probe函数,在probe函数中实现字符设备的注册和RGB灯的初始化。第三部分，编写字符设备函数集，实现open和write函数。
+
+**平台驱动入口和出口函数实现**
+
+
+程序与平台驱动章节相同，源码如下：
+
+
+.. code-block:: c 
+    :caption: 平台驱动框架
+    :linenos:
+
+    /*------------------第一部分----------------*/
+    static const struct of_device_id rgb_led[] = {
+    { .compatible = "fire,rgb-led"},
+      { /* sentinel */ }
+    };
+    
+    /*定义平台驱动结构体*/
+    struct platform_driver led_platform_driver = {
+    	.probe = led_probe,
+    	.driver = {
+    		.name = "rgb-leds-platform",
+    		.owner = THIS_MODULE,
+    		.of_match_table = rgb_led,
+    	}
+    };
+    
+    /*------------------第二部分----------------*/
+    /*驱动初始化函数*/
+    static int __init led_platform_driver_init(void)
+    {
+    	int error;
+    	
+    	error = platform_driver_register(&led_platform_driver);
+    	
+    	printk(KERN_EMERG "\tDriverState = %d\n",error);
+    	return 0;
+    }
+    
+    /*------------------第三部分----------------*/
+    /*驱动注销函数*/
+    static void __exit led_platform_driver_exit(void)
+    {
+    	printk(KERN_EMERG "platform_driver_exit!\n");
+    	
+    	platform_driver_unregister(&led_platform_driver);	
+    }
+    
+    
+    module_init(led_platform_driver_init);
+    module_exit(led_platform_driver_exit);
+    
+    MODULE_LICENSE("GPL");
+
+
+以上代码分为三部分，第二、三部分是平台设备的入口和出口函数，函数实现很简单，在入口函数中注册平台驱动，在出口函数中注销平台驱动。我们重点介绍第一部分，平台驱动结构体。
+
+在平台驱动结构体中我们仅实现.probe函数和.driver，当驱动和设备匹配成功后会执行该函数，这个函数的函数实现我们在后面介绍。.driver描述这个驱动的属性，包括.name驱动的名字，.owner驱动的所有者,.of_match_table
+驱动匹配表，用于匹配驱动和设备。驱动设备匹配表定义为“rgb_led”在这个表里只有一个匹配值“.compatible = "fire,rgb-led"”这个值要与我
+们在设备树中rgb_led设备树节点的“compatible”属性相同。
+
+**平台驱动.probe函数实现**
+
+
+当驱动和设备匹配后首先会probe函数，我们在probe函数中实现RGB的初始化、注册一个字符设备。后面将会在字符设备操作函数（open、write）中实现对RGB等的控制。函数源码如下所示。
+
+
+
+.. code-block:: c 
+    :caption: probe函数实现
+    :linenos:
+
+    static int led_probe(struct platform_device *pdv)
+    {
+        unsigned int  register_data = 0;  //用于保存读取得到的寄存器值
+    	int ret = 0;  //用于保存申请设备号的结果
+        
+    	printk(KERN_EMERG "\t  match successed  \n");
+    
+    	/*------------------第一部分---------------*/
+        /*获取RGB的设备树节点*/
+        rgb_led_device_node = of_find_node_by_path("/rgb_led");
+        if(rgb_led_device_node == NULL)
+        {
+            printk(KERN_EMERG "\t  get rgb_led failed!  \n");
+        }
+    
+    	/*------------------第二部分---------------*/
+        rgb_led_red = of_get_named_gpio(rgb_led_device_node, "rgb_led_red", 0);
+        rgb_led_green = of_get_named_gpio(rgb_led_device_node, "rgb_led_green", 0);
+        rgb_led_blue = of_get_named_gpio(rgb_led_device_node, "rgb_led_blue", 0);
+    
+        printk("rgb_led_red = %d,\n rgb_led_green = %d,\n rgb_led_blue = %d,\n", rgb_led_red,\
+        rgb_led_green,rgb_led_blue);
+    
+    	/*------------------第三部分---------------*/
+        gpio_direction_output(rgb_led_red, 1);
+        gpio_direction_output(rgb_led_green, 1);
+        gpio_direction_output(rgb_led_blue, 1);
+    
+    	/*------------------第四部分---------------*/
+    	/*---------------------注册 字符设备部分-----------------*/
+    	//第一步
+        //采用动态分配的方式，获取设备编号，次设备号为0，
+        //设备名称为rgb-leds，可通过命令cat  /proc/devices查看
+        //DEV_CNT为1，当前只申请一个设备编号
+        ret = alloc_chrdev_region(&led_devno, 0, DEV_CNT, DEV_NAME);
+        if(ret < 0){
+            printk("fail to alloc led_devno\n");
+            goto alloc_err;
+        }
+        //第二步
+        //关联字符设备结构体cdev与文件操作结构体file_operations
+    	led_chr_dev.owner = THIS_MODULE;
+        cdev_init(&led_chr_dev, &led_chr_dev_fops);
+        //第三步
+        //添加设备至cdev_map散列表中
+        ret = cdev_add(&led_chr_dev, led_devno, DEV_CNT);
+        if(ret < 0)
+        {
+            printk("fail to add cdev\n");
+            goto add_err;
+        }
+    
+    	//第四步
+    	/*创建类 */
+    	class_led = class_create(THIS_MODULE, DEV_NAME);
+    
+    	/*创建设备*/
+    	device = device_create(class_led, NULL, led_devno, NULL, DEV_NAME);
+    
+    	return 0;
+    
+    add_err:
+        //添加设备失败时，需要注销设备号
+        unregister_chrdev_region(led_devno, DEV_CNT);
+    	printk("\n error! \n");
+    alloc_err:
+    
+    	return -1;
+    }
+
+
+
+
+前三部分是RGB灯初始化部分，第四部分是字符设备相关内容，这部分内容在字符设备章节已经详细介绍这里不再赘述。
+
+第一部分，使用of_find_node_by_path函数找到并获取rgb_led在设备树中的设备节点。参数“/rgb_led”是要获取的设备树节点在设备树中的路径，由于rgb_led设备树节点在根节点下，所以路径为“/rgb_led”，如果要获取的节点嵌套在其他子节点中需要写出节点所在的完整路径。
+
+第二部分，使用函数of_get_named_gpio函数获取GPIO号，以“rgb_led_red = of_get_named_gpio(rgb_led_device_node, "rgb_led_red",
+0);”为例，读取成功则返回读取得到的GPIO号。“rgb_led_device_node”是我们使用函数“of_find_node_by_path”得到
+的设备节点。“rgb_led_red”指定GPIO的名字，这个参数要与rgb_led设备树节点中GPIO属性名对应，如下所示
+
+
+
+.. code-block:: c 
+    :caption: 设备树中GPIO属性定义部分
+    :linenos:
+
+    rgb_led_red = <&gpio1 4 GPIO_ACTIVE_LOW>;
+    rgb_led_green = <&gpio4 20 GPIO_ACTIVE_LOW>;
+    rgb_led_blue = <&gpio4 19 GPIO_ACTIVE_LOW>;
+
+参数“0”指定引脚索引，我们的设备树中一条属性中只定义了一个引脚，当然也可以定义多个，如果定义多个则该参数就用于指定获取的哪一个（从零开始），我们只有一个所以设置为0.
+
+第三部分，将GPIO设置为输出模式，默认输出电平为高电平。上一步我们已经获取了引脚编号，这里直接使用GPIO子系统提供的API函数操作GPIO即可。
+
+**实现字符设备函数**
+
+
+字符设备函数我们只需要实现open函数和write函数。函数源码如下。
+
+
+
+
+
+.. code-block:: c 
+    :caption: open函数和write函数实现
+    :linenos:
+
+    /*------------------第一部分---------------*/
+    /*字符设备操作函数集*/
+    static struct file_operations  led_chr_dev_fops = 
+    {
+    	.owner = THIS_MODULE,
+       .open = led_chr_dev_open,
+    	.write = led_chr_dev_write,
+    };
+    
+    /*------------------第二部分---------------*/
+    /*字符设备操作函数集，open函数*/
+    static int led_chr_dev_open(struct inode *inode, struct file *filp)
+    {
+    	printk("\n open form driver \n");
+        return 0;
+    }
+    
+    /*------------------第三部分---------------*/
+    /*字符设备操作函数集，write函数*/
+    static ssize_t led_chr_dev_write(struct file *filp, const char __user *buf, size_t cnt, loff_t *offt)
+    {
+    	unsigned char write_data; //用于保存接收到的数据
+    
+    	int error = copy_from_user(&write_data, buf, cnt);
+    	if(error < 0) {
+    		return -1;
+    	}
+    
+        /*设置 GPIO1_04 输出电平*/
+    	if(write_data & 0x04)
+    	{
+    		gpio_direction_output(rgb_led_red, 0);  // GPIO1_04引脚输出低电平，红灯亮
+    	}
+    	else
+    	{
+    		gpio_direction_output(rgb_led_red, 1);    // GPIO1_04引脚输出高电平，红灯灭
+    	}
+    
+        /*设置 GPIO4_20 输出电平*/
+    	if(write_data & 0x02)
+    	{
+    		gpio_direction_output(rgb_led_green, 0);  // GPIO4_20引脚输出低电平，绿灯亮
+    	}
+    	else
+    	{
+    		gpio_direction_output(rgb_led_green, 1);    // GPIO4_20引脚输出高电平，绿灯灭
+    	}
+    
+        /*设置 GPIO4_19 输出电平*/
+    	if(write_data & 0x01)
+    	{
+    		gpio_direction_output(rgb_led_blue, 0);  // GPIO4_19引脚输出低电平，蓝灯亮
+    	}
+    	else
+    	{
+    		gpio_direction_output(rgb_led_blue, 1);    // GPIO4_19引脚输出高电平，蓝灯灭
+    	}
+    
+    	return 0;
+    }
+
+
+代码共分为三部分，结合代码介绍如下：
+
+第一部分，定义字符设备操作函数集，这里我们只实现open和write函数即可。
+
+第二部分，实现open函数，在平台驱动的prob函数中已经初始化了GPIO,这里不用做任何操作，当然我们也可以将GPIO初始化部分代码移动到这里。
+
+第三部分，实现write函数。write函数的主要任务是根据应用程序传递来的命令控制RGB三个灯的亮、灭。这里存在一个问题，我们怎么解析命令？ 在程序中规定“命令”是一个“unsigned char”类型的数据，数据的后三位从高到低分别代表红、绿、蓝。为“1”表示亮为“0”表示灭。
+
+write函数实现也很简单，首先使用“copy_from_user”函数将来自应用层的数据“拷贝”内核层。得到命令后就依次检查
+后三位，根据命令值使用“gpio_direction_output”函数控制RGB灯的亮灭。
+
+**修改Makefile并编译生成驱动程序**
+
+
+Makefile程序并没有大的变化，修改后的Makefile如下所示。
+
+
+
+.. code-block:: c 
+    :caption: Makefile文件
+    :linenos:
+
+    KERNEL_DIR = /home/fire2/ebf-buster-linux
+    
+    obj-m := rgb-leds.o
+    
+    all:
+    	$(MAKE) -C $(KERNEL_DIR) M=$(CURDIR) modules
+    	
+    .PHONY:clean
+    clean:
+    	$(MAKE) -C $(KERNEL_DIR) M=$(CURDIR) clean
+
+
+需要注意的是第二行，变量“KERNEL_DIR”保存的是内核所在路径，这个需要根据自己内核所在位置设定。第四行“obj-m := rgb-leds.o”中的“rgb-leds.o”要与驱动源码名对应。Makefiel 修改完成后执行如下命令编译驱动。
+
+命令：
+
+.. code-block:: sh
+   :emphasize-lines: 1
+   :linenos:
+
+   make ARCH=arm CROSS_COMPILE=arm-linux-gnueabihf-
+
+正常情况下会在当前目录生成.ko驱动文件。
+
+应用程序编写
+^^^^^^
+
+应用程序实现
+
+
+应用程序编写比较简单，我们只需要打开设备节点文件，写入命令然后关闭设备节点文件即可。源码如下所示。
+
+
+
+.. code-block:: c 
+    :caption: Makefile文件
+    :linenos:
+
+    int main(int argc, char *argv[])
+    {
+        /*判断输入的命令是否合法*/
+        if(argc != 2)
+        {
+            printf(" commend error ! \n");
+            return -1;
+        }
+    
+        /*打开文件*/
+        int fd = open("/dev/rgb-leds", O_RDWR);
+        if(fd < 0)
+        {
+    		printf("open file : %s failed !\n", argv[0]);
+    		return -1;
+    	}
+    
+        unsigned char commend = atoi(argv[1]);  //将受到的命令值转化为数字;
+    
+        /*判断命令的有效性*/
+        /*写入命令*/
+        int error = write(fd,&commend,sizeof(commend));
+        if(error < 0)
+        {
+            printf("write file error! \n");
+            close(fd);
+            /*判断是否关闭成功*/
+        }
+        /*关闭文件*/
+        error = close(fd);
+        if(error < 0)
+        {
+            printf("close file error! \n");
+        }
+        return 0;
+    }
+
+
+结合代码各部分说明如下：
+
+第一部分，判断命令是否有效。再运行应用程序时我们要传递一个控制命令，所以参数长度是2。
+
+第二部分，打开设备文件。参数“/dev/rgb-leds”用于指定设备节点文件，设备节点文件名是在驱动程序中设置的，这里保证与驱动一致即可。
+
+第三部分，由于从main函数中获取的参数是字符串，这里首先要将其转化为数字。最后条用write函数写入命令然后关闭文件即可。
+
+编译应用程序
+
+
+进入应用程序所在目录“~/gpio_subsystem_rgb_led/”执行如下命令：
+
+命令：
+
+.. code-block:: sh
+   :emphasize-lines: 1
+   :linenos:
+
+   arm-linux-gnueabihf-gcc <源文件名> –o <输出文件名>
+
+以本章配套历程为例执行如下命令编译应用程序：
+
+命令：
+
+.. code-block:: sh
+   :emphasize-lines: 1
+   :linenos:
+
+   arm-linux-gnueabihf-gcc rgb_leds_app.c –o rgb_leds_app
+
+下载验证
+^^^^
+
+前两小节我们已经编译出了.ko驱动和应用程序，将驱动程序和应用程序添加到开发板中（推荐使用之前讲解的NFS共享文件夹），驱动程序和应用程序在开发板中的存放位置没有限制。我们将驱动和应用都放到开发板的“/home/nfs_share”目录下，如下所示。
+
+.. image:: ./media/gpiosu014.png
+   :align: center
+   :alt: 总线结构14|
+
+执行如下命令加载驱动：
+
+命令：
+
+.. code-block:: sh
+   :emphasize-lines: 1
+   :linenos:
+
+   insmod ./rgb-leds.ko
+
+正常情况下输出结果如下所示。
+
+.. image:: ./media/gpiosu015.png
+   :align: center
+   :alt: 总线结构15|
+
+在驱动程序中，我们在.probe函数中注册字符设备并创建了设备文件，设备和驱动匹配成功后.probe函数已经执行，所以正常情况下在“/dev/”目录下已经生成了“rgb-leds”设备节点，如下所示。
+
+.. image:: ./media/gpiosu016.png
+   :align: center
+   :alt: 总线结构16|
+
+驱动加载成功后直接运行应用程序如下所示。
+
+命令：
+
+.. code-block:: sh
+   :emphasize-lines: 1
+   :linenos:
+
+   ./rgb_leds_app <命令>
+
+执行结果如下：
+
+.. image:: ./media/gpiosu017.png
+   :align: center
+   :alt: 总线结构17|
+
+命令是一个“unsigned char”型数据，只有后三位有效，每一位代表一个灯，从高到低依次代表红、绿、蓝，1表示亮，0表示灭。例如命令=4 则亮红灯，命令=7则三个灯全亮。
+
+.. |gpiosu002| image:: media\gpiosu002.png
+   :width: 5.76806in
+   :height: 1.09722in
+.. |gpiosu003| image:: media\gpiosu003.png
+   :width: 5.76806in
+   :height: 1.55208in
+.. |gpiosu004| image:: media\gpiosu004.png
+   :width: 5.76806in
+   :height: 2.01806in
+.. |gpiosu005| image:: media\gpiosu005.png
+   :width: 5.76806in
+   :height: 4.35903in
+.. |gpiosu006| image:: media\gpiosu006.png
+   :width: 5.76806in
+   :height: 5.6125in
+.. |gpiosu007| image:: media\gpiosu007.png
+   :width: 5.76806in
+   :height: 3.31111in
+.. |gpiosu008| image:: media\gpiosu008.png
+   :width: 5.76806in
+   :height: 1.98056in
+.. |gpiosu009| image:: media\gpiosu009.png
+   :width: 5.76806in
+   :height: 1.78681in
+.. |gpiosu010| image:: media\gpiosu010.png
+   :width: 5.76806in
+   :height: 6.06111in
+.. |gpiosu011| image:: media\gpiosu011.png
+   :width: 5.76806in
+   :height: 4.81389in
+.. |gpiosu012| image:: media\gpiosu012.png
+   :width: 5.76806in
+   :height: 1.21319in
+.. |gpiosu013| image:: media\gpiosu013.png
+   :width: 5.76806in
+   :height: 1.31319in
+.. |gpiosu014| image:: media\gpiosu014.png
+   :width: 5.76806in
+   :height: 1.27708in
+.. |gpiosu015| image:: media\gpiosu015.png
+   :width: 5.76806in
+   :height: 1.48264in
+.. |gpiosu016| image:: media\gpiosu016.png
+   :width: 5.76806in
+   :height: 0.83194in
+.. |gpiosu017| image:: media\gpiosu017.png
+   :width: 5.76806in
+   :height: 1.94583in
diff --git a/documentation/linux_driver/i2c_mpu6050.rst b/documentation/linux_driver/i2c_mpu6050.rst
new file mode 100644
index 0000000000000000000000000000000000000000..b09e8d37333bb0905eec27a22a2f66d6da3bcaf9
--- /dev/null
+++ b/documentation/linux_driver/i2c_mpu6050.rst
@@ -0,0 +1,1147 @@
+.. vim: syntax=rst
+
+i2c_mpu6050驱动实验
+---------------
+
+本章我们以板载MPU6050为例讲解i2c驱动程序的编写，本章主要分为四
+部分内容。第一部分，i2c驱动基本知识，包括i2c驱动的一些函数和结构
+体讲解。第二部分，编写i2c_mpu6050的设备树插件。第三部分，编写mpu6050驱动。第四部分，编写
+简单测试应用程序。
+
+本章配套源码和设备树插件源码位于“~/embed_linux_tutorial/base_code/linux_driver/I2c_MPU6050”。
+
+i2c驱动基本知识
+~~~~~~~~~
+
+学过单片机的用户对i2c协议并不陌生，如果忘记可参考野火单片机相关教程，这里不再赘述。
+
+在编写单片机裸机i2c驱动时我们需要根据i2c协议手动配置i2c控制寄存器使其能够输出起始信号、停止信号、数据信息等等。在Linux系统中采用了总线、设备驱动模型。我们之前讲解的平台设备也是采用了这种总线、设备驱动模型，只不过平台总线是一个虚拟的总线。
+
+我们知道一个i2c(例如i2c1)上可以挂在多个i2c设备，例如mpu6050、i2c接口的OLED显示屏、摄像头（摄像头通过i2c接口发送控制信息）等等，这些设备共用一个i2c，这个i2c的驱动我们称为i2c总线驱动。而对应具体的设备,例如mpu6050的驱动就是设备驱动。这样我们要使用mpu60
+50就需要拥有“两个驱动”一个是i2c总线驱动和mpu6050设备驱动。i2c总线驱动由芯片厂商提供（驱动复杂，官方提供了经过测试的驱动，我们直接用），mpu6050设备驱动可以从mpu6050芯片厂家那里获得（不确定有），也可以我们手动编写。
+
+NXP官方i2c总线驱动介绍
+~~~~~~~~~~~~~~
+
+为方便用户使用NXP官方已经写好了i2c总线驱动，如果我们使用NXP官方提供的Linux内核i2c总线驱动已经保存在内核中，并且默认情况下已经编译进内核。下面结合源码简单介绍i2c总线驱动实现。
+
+查找i2c总线驱动的入口在设备树，我们可以根据i2c设备节点中的compatible属性来定位i2c总线驱动源码。i2c是IMX6ull平台共用的资源所以它的设备树节点保存在“imx6ull.dtsi”文件内，该文件位于内核源码的“~/arch/arm/boot/dts”目录下。打开该文件，在文件中
+直接搜索i2c1，找到i2c1对应的设备树节点如下所示。
+
+
+
+.. code-block:: c 
+    :caption: i2c1设别树节点
+    :linenos:
+
+    i2c1: i2c@021a0000 {
+    	#address-cells = <1>;
+    	#size-cells = <0>;
+    	compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
+    	reg = <0x021a0000 0x4000>;
+    	interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+    	clocks = <&clks IMX6UL_CLK_I2C1>;
+    	status = "disabled";
+    };
+
+
+我么先不关心i2c1设备树节点的详细内容，重点关注compatible属性，我们复制“fsl,imx6ul-i2c”或“fsl,imx21-i2c”在内核驱动源码中全局搜索（例如进入内核源码使用VScode打开drivers文件夹使用vscode搜索）。如下所示。
+
+.. image:: ./media/i2cmpu002.png
+   :align: center
+   :alt: 2|
+
+
+
+进入i2c驱动源文件“~/drivers/i2c/busses/i2c-imx.c”，i2c总线驱动代码较长，我们只简单介绍重要的几个点，如果感兴趣可自行阅读完整的i2c驱动源码。通常情况下，看驱动程序首先要找到驱动的入口和出口函数，驱动入口和出口位于驱动的末尾，如下所示。
+
+
+
+
+.. code-block:: c 
+    :caption: 驱动入口和出口函数
+    :linenos:
+
+    static int __init i2c_adap_imx_init(void)
+    {
+    	return platform_driver_register(&i2c_imx_driver);
+    }
+    subsys_initcall(i2c_adap_imx_init);
+    
+    static void __exit i2c_adap_imx_exit(void)
+    {
+    	platform_driver_unregister(&i2c_imx_driver);
+    }
+    module_exit(i2c_adap_imx_exit);
+
+
+
+驱动入口和出口函数很简单，我们可以从中得到i2c驱动是一个平台驱动，并且我们知道平台驱动结构体是“i2c_imx_driver”，平台驱动结构体如下所示。
+
+
+
+.. code-block:: c 
+    :caption: 平台设备驱动结构体
+    :linenos:
+
+    /*----------------第一部分-----------------*/
+    static const struct of_device_id i2c_imx_dt_ids[] = {
+    	{ .compatible = "fsl,imx1-i2c", .data = &imx1_i2c_hwdata, },
+    	{ .compatible = "fsl,imx21-i2c", .data = &imx21_i2c_hwdata, },
+    	{ .compatible = "fsl,vf610-i2c", .data = &vf610_i2c_hwdata, },
+    	{ /* sentinel */ }
+    };
+    
+    /*----------------第二部分-----------------*/
+    static struct platform_driver i2c_imx_driver = {
+    	.probe = i2c_imx_probe,
+    	.remove = i2c_imx_remove,
+    	.driver	= {
+    		.name = DRIVER_NAME,
+    		.owner = THIS_MODULE,
+    		.of_match_table = i2c_imx_dt_ids,
+    		.pm = IMX_I2C_PM,
+    	},
+    	.id_table	= imx_i2c_devtype,
+    };
+
+第一部分是i2c驱动的匹配表，用于和设备树节点匹配，第二部分就是初始化的平台设备结构体，从这个结构体我们可以找到.prob函数，.prob函数的作用我们都很清楚，通常情况下该函数实现设备的基本初始化，下面重点介绍.porb函数的内容。（.prob函数较长，推荐配合源码阅读这部分内容）。
+
+
+.. code-block:: c 
+    :caption: i2c 驱动 .prob函数
+    :linenos:
+
+    static int i2c_imx_probe(struct platform_device *pdev)
+    {
+    	const struct of_device_id *of_id = of_match_device(i2c_imx_dt_ids,
+    							   &pdev->dev);
+    	struct imx_i2c_struct *i2c_imx;
+    	struct resource *res;
+    	struct imxi2c_platform_data *pdata = dev_get_platdata(&pdev->dev);
+    	void __iomem *base;
+    	int irq, ret;
+    	dma_addr_t phy_addr;
+    
+    	dev_dbg(&pdev->dev, "<%s>\n", __func__);
+    
+    /*----------------第一部分-----------------*/
+    	irq = platform_get_irq(pdev, 0);
+    	if (irq < 0) {
+    		dev_err(&pdev->dev, "can't get irq number\n");
+    		return irq;
+    	}
+    
+    /*----------------第二部分-----------------*/
+    	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+    	base = devm_ioremap_resource(&pdev->dev, res);
+    	if (IS_ERR(base))
+    		return PTR_ERR(base);
+    
+    	phy_addr = (dma_addr_t)res->start;
+    
+        /*----------------第三部分-----------------*/
+    	i2c_imx = devm_kzalloc(&pdev->dev, sizeof(*i2c_imx), GFP_KERNEL);
+    	if (!i2c_imx)
+    		return -ENOMEM;
+    
+    	if (of_id)
+    		i2c_imx->hwdata = of_id->data;
+    	else
+    		i2c_imx->hwdata = (struct imx_i2c_hwdata *)
+    				platform_get_device_id(pdev)->driver_data;
+    
+    /*----------------第四部分-----------------*/
+    	/* Setup i2c_imx driver structure */
+    	strlcpy(i2c_imx->adapter.name, pdev->name, sizeof(i2c_imx->adapter.name));
+    	i2c_imx->adapter.owner		= THIS_MODULE;
+    	i2c_imx->adapter.algo		= &i2c_imx_algo;
+    	i2c_imx->adapter.dev.parent	= &pdev->dev;
+    	i2c_imx->adapter.nr		= pdev->id;
+    	i2c_imx->adapter.dev.of_node	= pdev->dev.of_node;
+    	i2c_imx->base			= base;
+    
+    /*----------------第五部分-----------------*/
+    	/* Get I2C clock */
+    	i2c_imx->clk = devm_clk_get(&pdev->dev, NULL);
+    	if (IS_ERR(i2c_imx->clk)) {
+    		dev_err(&pdev->dev, "can't get I2C clock\n");
+    		return PTR_ERR(i2c_imx->clk);
+    	}
+    
+    /*----------------第六部分-----------------*/
+    	ret = clk_prepare_enable(i2c_imx->clk);
+    	if (ret) {
+    		dev_err(&pdev->dev, "can't enable I2C clock\n");
+    		return ret;
+    	}
+    
+    /*----------------第七部分-----------------*/
+    	/* Request IRQ */
+    	ret = devm_request_irq(&pdev->dev, irq, i2c_imx_isr,
+    			       IRQF_NO_SUSPEND, pdev->name, i2c_imx);
+    	if (ret) {
+    		dev_err(&pdev->dev, "can't claim irq %d\n", irq);
+    		goto clk_disable;
+    	}
+    
+    	/* Init queue */
+    	init_waitqueue_head(&i2c_imx->queue);
+    
+    	/* Set up adapter data */
+    	i2c_set_adapdata(&i2c_imx->adapter, i2c_imx);
+    
+    	/* Set up clock divider */
+    	i2c_imx->bitrate = IMX_I2C_BIT_RATE;
+    	ret = of_property_read_u32(pdev->dev.of_node,
+    				   "clock-frequency", &i2c_imx->bitrate);
+    	if (ret < 0 && pdata && pdata->bitrate)
+    		i2c_imx->bitrate = pdata->bitrate;
+    
+    	/* Set up chip registers to defaults */
+    	imx_i2c_write_reg(i2c_imx->hwdata->i2cr_ien_opcode ^ I2CR_IEN,
+    			i2c_imx, IMX_I2C_I2CR);
+    	imx_i2c_write_reg(i2c_imx->hwdata->i2sr_clr_opcode, i2c_imx, IMX_I2C_I2SR);
+    
+    	/* Add I2C adapter */
+    	ret = i2c_add_numbered_adapter(&i2c_imx->adapter);
+    	if (ret < 0) {
+    		dev_err(&pdev->dev, "registration failed\n");
+    		goto clk_disable;
+    	}
+    
+    	/* Set up platform driver data */
+    	platform_set_drvdata(pdev, i2c_imx);
+    	clk_disable_unprepare(i2c_imx->clk);
+    
+    	dev_dbg(&i2c_imx->adapter.dev, "claimed irq %d\n", irq);
+    	dev_dbg(&i2c_imx->adapter.dev, "device resources: %pR\n", res);
+    	dev_dbg(&i2c_imx->adapter.dev, "adapter name: \"%s\"\n",
+    		i2c_imx->adapter.name);
+    	dev_info(&i2c_imx->adapter.dev, "IMX I2C adapter registered\n");
+    
+    	/* Init DMA config if supported */
+    	i2c_imx_dma_request(i2c_imx, phy_addr);
+    
+    	return 0;   /* Return OK */
+    
+    clk_disable:
+    	clk_disable_unprepare(i2c_imx->clk);
+    	return ret;
+    }
+
+
+这里简单介绍.prob函数的实现过程，很多详细的内容我们还没有讲解到，这里先不具体介绍。
+
+第一部分， 获取中断号，在i2c1的设备树节点中定义了中断，这里获取得到的中断号申请中断时会用到，获取函数使用的是内核提供的函数“platform_get_irq”。
+
+第二部分，获取reg属性，这里同样使用的是内核提供的“platform_get_resource”它实现的功能和我们使用of函数获取reg属性相同。这里的代码获取得到了i2c1的基地址，并且使用“devm_ioremap_resource”将其转化为虚拟地址。
+
+第三部分，为i2c_imx申请内存空间，我们先不关心申请函数，重点是结构体i2c_imx下面我们将重点介绍这个结构体。
+
+
+
+.. code-block:: c 
+    :caption: imx_i2c_struct结构体
+    :linenos:
+
+    struct imx_i2c_struct {
+    	struct i2c_adapter	adapter;
+    	struct clk		*clk;
+    	void __iomem		*base;
+    	wait_queue_head_t	queue;
+    	unsigned long		i2csr;
+    	unsigned int		disable_delay;
+    	int			stopped;
+    	unsigned int		ifdr; /* IMX_I2C_IFDR */
+    	unsigned int		cur_clk;
+    	unsigned int		bitrate;
+    	const struct imx_i2c_hwdata	*hwdata;
+    
+    	struct imx_i2c_dma	*dma;
+    };
+
+imx_i2c_struct结构体成员较多，其中大多数是用于保存i2c硬件信息例如clk结构体保存时钟相关信息、bitrate保存iic的波特率、dma保存dam相关信息等等。我们重点关心的是第一个成员“i2c_adapter”结构体。
+
+在Linux内核i2c_adapte结构体用于表示一个实际的i2c总线（例如i2c1）。i2c_adapter结构体如下所示。
+
+
+
+
+.. code-block:: c 
+    :caption: i2c_adapter结构体
+    :linenos:
+
+    /*
+     * i2c_adapter is the structure used to identify a physical i2c bus along
+     * with the access algorithms necessary to access it.
+     */
+    struct i2c_adapter {
+    	struct module *owner;
+    	unsigned int class;		  /* classes to allow probing for */
+    	const struct i2c_algorithm *algo; /* the algorithm to access the bus */
+    	void *algo_data;
+    
+    	/* data fields that are valid for all devices	*/
+    	struct rt_mutex bus_lock;
+    
+    	int timeout;			/* in jiffies */
+    	int retries;
+    	struct device dev;		/* the adapter device */
+    
+    	int nr;
+    	char name[48];
+    	struct completion dev_released;
+    
+    	struct mutex userspace_clients_lock;
+    	struct list_head userspace_clients;
+    
+    	struct i2c_bus_recovery_info *bus_recovery_info;
+    	const struct i2c_adapter_quirks *quirks;
+    };
+
+i2c_adapte结构体的一些参数较多。在.prob函数中会初始化部分参数，这里重点介绍“struct
+i2c_algorithm”结构体，它用于指定“访问总线（i2c）的算法”，在这里就是用于指定外部访问i2c总线的接口，这个“接口”体现到代码就是一些接口函数，i2c_algorithm结构体如下所示。
+
+
+
+.. code-block:: c 
+    :caption: i2c_algorithm结构体
+    :linenos:
+
+    struct i2c_algorithm {
+    	/* If an adapter algorithm can't do I2C-level access, set master_xfer
+    	   to NULL. If an adapter algorithm can do SMBus access, set
+    	   smbus_xfer. If set to NULL, the SMBus protocol is simulated
+    	   using common I2C messages */
+    	/* master_xfer should return the number of messages successfully
+    	   processed, or a negative value on error */
+    	int (*master_xfer)(struct i2c_adapter *adap, struct i2c_msg *msgs,
+    			   int num);
+    	int (*smbus_xfer) (struct i2c_adapter *adap, u16 addr,
+    			   unsigned short flags, char read_write,
+    			   u8 command, int size, union i2c_smbus_data *data);
+    
+    	/* To determine what the adapter supports */
+    	u32 (*functionality) (struct i2c_adapter *);
+    
+    #if IS_ENABLED(CONFIG_I2C_SLAVE)
+    	int (*reg_slave)(struct i2c_client *client);
+    	int (*unreg_slave)(struct i2c_client *client);
+    #endif
+    };
+
+从以上代码不难看出i2c_algorithm结构体实际提供了一些函数指针，这些函数就是外部访问i2c总线的接口，更直白的说，i2c设备例如mpu6050、i2c接口的oled屏等等就是通过这些函数接口使用i2c总线实现收、发数据的。在i2c1的总线驱动中会实现这些函数（部分函数）。
+
+回到 i2c1的.prob函数的第四部分代码。
+
+第四部分，初始化i2c_imx结构体，根据前面讲解，i2c_imx结构体内有一个imx_i2c_struct类型的结构体，在程序中它代表一个实际的i2c总线。这部分初始化代码大多数用于初始化imx_i2c_struct结构体的成员。其中我们需要特别关心“i2c_imx->adapter.algo =
+&i2c_imx_algo;”，它就是用于初始化“访问总线（i2c）的算法”。“i2c_imx_algo”定义如下。
+
+
+
+.. code-block:: c 
+    :caption: i2c_algorithm结构体实例i2c_imx_algo
+    :linenos:
+
+    static struct i2c_algorithm i2c_imx_algo = {
+    	.master_xfer	= i2c_imx_xfer,
+    	.functionality	= i2c_imx_func,
+    };
+
+
+i2c_imx_algo结构体内指定了两个函数，它们就是外部访问i2c总线的接口，函数i2c_imx_func只是用于返回当前所处状态，真正实现外部访问i2c总线的是函数i2c_imx_xfer。函数定义如下。（省略了具体的函数实现）。
+
+
+
+.. code-block:: c 
+    :caption: i2c_imx_xfer函数
+    :linenos:
+
+    static int i2c_imx_xfer(struct i2c_adapter *adapter,
+    						struct i2c_msg *msgs, int num)
+
+在编写设备驱动时我们会使用“i2c_transfer”函数执行数据的传输，i2c_transfer函数最终就是调用i2c_imx_xfer函数实现具体的收发工作。在编写设备驱动时我们会详细介绍i2c_transfer函数的用法。
+
+第五部分，第五部分完成一些基本的初始化，从上到下依次为 获取i2c的时钟、使能i2c时钟、请求中断、初始化队列、设置i2c_adapter结构体的data参数、设置i2c1的时钟分频、设置寄存器为默认值。
+
+第六部分，添加i2c adapter 。根据之前讲解，在系统中一个i2c adapter（一个i2c_adapter结构体）对应一个i2c设备，这一步就是将i2c添加到系统中。参数就是我们前面部分初始化的i2c_imx->adapter结构体。
+
+整个.prob函数完成了两个主要工作 。第一，初始化i2c1硬件，第二，初始化一个“代表i2c1”的i2c_adapter结构体，并将其添加到系统中。
+
+.prob函数完成了i2c的基本初始化并将其添加到了系统中。i2c总线驱动的另外一个重要工作就是实现i2c对外接口函数。我们在初始化i2c_adapter结构体时已经初始化了“访问总线算法结构体”
+i2c_adapter->i2c_algorithm.具体代码为“i2c_imx->adapter.algo = &i2c_imx_algo;”。在i2c_imx_algo结构体源码如下所示。
+
+
+
+.. code-block:: c 
+    :caption: i2c_imx_algo
+    :linenos:
+
+    static struct i2c_algorithm i2c_imx_algo = {
+    	.master_xfer	= i2c_imx_xfer,
+    	.functionality	= i2c_imx_func,
+    };
+
+
+在i2c设备驱动程序中“i2c_transfer”函数的读、写工工作实际由i2c_imx_xfer函数完成，i2c_imx_xfer函数就是i2c总线驱动中实现具体收发工作的函数。i2c_imx_xfer部分代码如下所示。
+
+
+
+.. code-block:: c 
+    :caption: i2c_imx_xfer函数
+    :linenos:
+
+    static int i2c_imx_xfer(struct i2c_adapter *adapter,
+    						struct i2c_msg *msgs, int num)
+    {
+    /*---------------一下内容省略-------------------*/
+    	/* read/write data */
+    	for (i = 0; i < num; i++) {
+    		if (i == num - 1)
+    			is_lastmsg = true;
+    
+    		if (i) {
+    			dev_dbg(&i2c_imx->adapter.dev,
+    				"<%s> repeated start\n", __func__);
+    			temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
+    			temp |= I2CR_RSTA;
+    			imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
+    			result =  i2c_imx_bus_busy(i2c_imx, 1);
+    			if (result)
+    				goto fail0;
+    		}
+    		dev_dbg(&i2c_imx->adapter.dev,
+    			"<%s> transfer message: %d\n", __func__, i);
+    		/* write/read data */
+    /*---------------以下下内容省略-------------------*/
+    		if (msgs[i].flags & I2C_M_RD)
+    			result = i2c_imx_read(i2c_imx, &msgs[i], is_lastmsg);
+    		else {
+    			if (i2c_imx->dma && msgs[i].len >= DMA_THRESHOLD)
+    				result = i2c_imx_dma_write(i2c_imx, &msgs[i]);
+    			else
+    				result = i2c_imx_write(i2c_imx, &msgs[i]);
+    		}
+    		if (result)
+    			goto fail0;
+    	}
+    /*---------------以下下内容省略-------------------*/
+    }
+
+从以上代码中可以看到i2c_imx_xfer函数会调用i2c_imx_dma_write、i2c_imx_read、imx_i2c_write_reg等等基本收发函数实现数据的收发工作，这些基本的收发函数由i2c总线驱动实现。
+
+至此，我们知道i2c总线驱动完成了i2c的硬件初始化、将i2c总线添加到系统、并提外界访问i2c总线的接口函数。我们的i2c设备驱动只需要根据特定设备使用这些接口函数即可。下面以mpu6050为例讲解如何编写i2c设备驱动。
+
+mpu6050驱动介绍
+~~~~~~~~~~~
+
+mpu6050驱动使用设备树插件方式开发,驱动的主要工作包四部分内容。第一，编写mpu6050的设备树插件，第二，编写mpu6050驱动程序，第三，编写简单测试应用程序。结合代码，这三部分内容介绍如下。
+
+mpu6050设备树插件编写
+^^^^^^^^^^^^^^
+
+mpu6050使用的是i2c1，我们需要在i2c1设备节点下追加mpu6050这个设备。如果之前没有用到i2c1(还没有将i2c1的两个引脚)，还需要将i2c1使用的引脚添加到pinctrl子系统对应的节点。设备树插件完整代码如下所示。
+
+
+
+
+.. code-block:: c 
+    :caption: mpu6050设备树插件
+    :linenos:
+
+    /dts-v1/;
+    /plugin/;
+    #include "imx6ul-pinfunc.h"
+    
+     / {
+         fragment@0 {
+    /*-------------第一部分-----------*/
+             target = <&i2c1>;  -------------------------①
+             __overlay__ { 
+                clock-frequency = <100000>;
+    	        pinctrl-names = "default";
+    	        pinctrl-0 = <&pinctrl_i2c1>; ------------②
+    	        status = "okay";
+    
+    	        i2c_mpu6050@68 {  -----------------------③
+    	        	compatible = "fire,i2c_mpu6050";  ---④
+    	        	reg = <0x68>;  ----------------------⑤            
+    	        	status = "okay";
+    	        };        
+             };
+         };
+    /*-------------第二部分-----------*/
+         fragment@1 {
+             target = <&iomuxc>;------------------------⑥
+             __overlay__ { 
+            pinctrl_i2c1: i2c1grp {
+            		fsl,pins = <
+            			MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0
+            			MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0
+            		>;
+            	};     
+             };
+         };
+    
+     };
+
+设别树插件分为两部分内容，第一部分是在i2c1节点追加mpu6050子节点，第二部分是在pinctrl子系统对应节点内追加i2c1所使用的两个引脚。如果其他i2c1设备已经追加过了，则第二部分可以省略。
+
+第一部分，标号①，指定设备树插件“插入”位置。标号②，指定i2c1使用的引脚，“pinctrl_i2c1”定义在设备树插件的第二部分。标号③，指定mpu6050节点名，注意@符号后面是mpu6050在i2c1总线中地址。这个地址是七位地址，我们原理途中给出了mpu6050的8位地址，右移一位得到7位
+地址，如下所示。
+
+.. image:: ./media/i2cmpu003.png
+   :align: center
+   :alt: 3|
+
+标号④用于指定compatible 属性，和驱动保持一致即可。标号⑤，设置reg属性，reg属性只需要指定mpu6050在i2c1总线上的地址即可，注意这里要和标号③处的地址保持一致。
+
+设备树插件的编译、添加到系统请参考“设备树插件实现RGB灯章节”。
+
+mpu6050驱动实现
+^^^^^^^^^^^
+
+由于NXP官方已经写好了i2c的总线驱动，mpu6050这个设备驱动就变得很简单，下面结合代码介绍mpu6050设别驱动实现。
+
+和平台设备驱动类似，驱动框架如下：
+
+
+
+.. code-block:: c 
+    :caption: mpu6050驱动程序结构
+    :linenos:
+
+    /*--------------第四部分----------------*/
+    static int i2c_write_mpu6050(struct i2c_client *mpu6050_client, u8 address, u8 data)
+    {
+    	return 0;
+    }
+    static int i2c_read_mpu6050(struct i2c_client *mpu6050_client, u8 address, void *data, u32 length)
+    {
+    	return 0;
+    }
+    static int mpu6050_init(void)
+    {
+    	return 0;
+    }
+    
+    /*--------------第三部分----------------*/
+    /*字符设备操作函数集，open函数实现*/
+    static int mpu6050_open(struct inode *inode, struct file *filp)
+    {
+    	return 0;
+    }
+    /*字符设备操作函数集，.read函数实现*/
+    static ssize_t mpu6050_read(struct file *filp, char __user *buf, size_t cnt, loff_t *off)
+    {
+    	return 0;
+    }
+    /*字符设备操作函数集，.release函数实现*/
+    static int mpu6050_release(struct inode *inode, struct file *filp)
+    {
+    	return 0;
+    }
+    /*字符设备操作函数集*/
+    static struct file_operations mpu6050_chr_dev_fops =
+    	{
+    		.owner = THIS_MODULE,
+    		.open = mpu6050_open,
+    		.read = mpu6050_read,
+    		.release = mpu6050_release,
+    };
+    /*--------------第二部分--------------------*/
+    /*i2c总线设备函数集*/
+    static int mpu6050_probe(struct i2c_client *client, const struct i2c_device_id *id)
+    {
+    	/*---------------------添加、注册字符设备-----------------*/
+    	return 0
+    }
+    static int mpu6050_remove(struct i2c_client *client)
+    {
+    	/*删除设备*/
+    	return 0;
+    }
+    
+    
+    /*--------------第一部分--------------------*/
+    /*定义i2c总线设备结构体*/
+    struct i2c_driver mpu6050_driver = {
+    	.probe = mpu6050_probe,
+    	.remove = mpu6050_remove,
+    	.id_table = gtp_device_id,
+    };
+    
+    /*
+    *驱动初始化函数
+    */
+    static int __init mpu6050_driver_init(void)
+    {
+    	return 0;
+    }
+    
+    /*
+    *驱动注销函数
+    */
+    static void __exit mpu6050_driver_exit(void)
+    {
+    
+    }
+    
+    module_init(mpu6050_driver_init);
+    module_exit(mpu6050_driver_exit);
+    
+    MODULE_LICENSE("GPL");
+
+
+从下往上看，驱动程序分为四部分内容。结合以上代码介绍如下：
+
+第一部分，定义i2c总线设备结构体并实现i2c总线设备的注册和注销函数，在这里就是程驱动程序的入口和出口函数。
+
+第二部分，实现i2c总线设备结构体中定义的操作函数，主要是.prob匹配函数，在.prob函数中添加、注册一个字符设备，这个字符设备用于实现mpu6050的具体功能。
+
+第三部分，定义并实现字符设备操作函数集。在应用程序中的open、read操作传到内核后就是执行这些函数，所以他们要真正实现对mpu6050的初始化以及读取转换结果。
+
+第四部分，具体的读、写mpu6050的函数，它们被第三部分的函数调用，用户自行定义。
+
+下面我们将按照这四部分内容介绍mpu6050设备驱动程序实现。
+
+驱动入口和出口函数实现
+'''''''''''
+
+驱动入口和出口函数仅仅用于注册、注销i2c设备驱动，代码如下：
+
+
+
+
+.. code-block:: c 
+    :caption: mpu6050驱动入口和出口函数实现
+    :linenos:
+
+    /*---------------第一部分-----------------*/
+    /*定义ID 匹配表*/
+    static const struct i2c_device_id gtp_device_id[] = {
+    	{"fire,i2c_mpu6050", 0},
+    	{}};
+    
+    /*---------------第二部分-----------------*/
+    /*定义设备树匹配表*/
+    static const struct of_device_id mpu6050_of_match_table[] = {
+    	{.compatible = "fire,i2c_mpu6050"},
+    	{/* sentinel */}};
+    
+    /*---------------第三部分-----------------*/
+    /*定义i2c设备结构体*/
+    struct i2c_driver mpu6050_driver = {
+    	.probe = mpu6050_probe,
+    	.remove = mpu6050_remove,
+    	.id_table = gtp_device_id,
+    	.driver = {
+    		.name = "fire,i2c_mpu6050",
+    		.owner = THIS_MODULE,
+    		.of_match_table = mpu6050_of_match_table,
+    	},
+    };
+    
+    /*---------------第四部分-----------------*/
+    /*
+    *驱动初始化函数
+    */
+    static int __init mpu6050_driver_init(void)
+    {
+    	int ret;
+    	pr_info("mpu6050_driver_init\n");
+    	ret = i2c_add_driver(&mpu6050_driver);
+    	return ret;
+    }
+    
+    /*
+    *驱动注销函数
+    */
+    static void __exit mpu6050_driver_exit(void)
+    {
+    	pr_info("mpu6050_driver_exit\n");
+    	i2c_del_driver(&mpu6050_driver);
+    }
+    
+    module_init(mpu6050_driver_init);
+    module_exit(mpu6050_driver_exit);
+    
+    MODULE_LICENSE("GPL");
+
+
+
+
+以上代码中，第三部分是我们定义的i2c设备驱动结构体mpu6050_driver，和我们之前学习的平台设备驱动类似，一个“结构体”代表了一个设备。结构体内主要成员介绍如下， “.id_table”和“.of_match_table”，它们用于和匹配设备树节点
+，具体实现如代码第一、第二部分所示。第二部分是“.probe”和“.remove”，它们是i2c设备的操作函数，.prob函数在匹配成功后会执行,设备注销之前.remove函数会执行，稍后我们会实现这两个函数。
+
+第四部分，这部分就是我们常说的驱动入口和出口函数。在入口函数内我们调用“i2c_add_driver”函数添加一个i2c设备驱动。在出口函数内调用“i2c_del_driver”函数删除一个i2c设备驱动。它们的参数都只有一个i2c设备驱动结构体，在这里就是我们第三部分定义的哪个结构体。
+
+.prob函数和.remove函数实现
+'''''''''''''''''''
+
+通常情况下.prob用于实现一些初始化工作，.remove用于实现退出之前的清理工作。mpu6050需要初始化的内容很少，我们放到了字符设备的.open函数中实现.prob函数只需要添加、注册一个字符设备即可。程序源码如下所示：（为节省篇幅，这里只列出了部分代码）。
+
+
+
+
+.. code-block:: c 
+    :caption: mpu6050驱动.prob和.remove函数实现
+    :linenos:
+
+    /*----------------平台驱动函数集-----------------*/
+    static int mpu6050_probe(struct i2c_client *client, const struct i2c_device_id *id)
+    {
+    
+    	int ret = -1; //保存错误状态码
+    
+    	printk(KERN_EMERG "\t  match successed  \n");
+    	/*---------------------注册 字符设备部分-----------------*/
+    	//采用动态分配的方式，获取设备编号，次设备号为0，
+    	ret = alloc_chrdev_region(&mpu6050_devno, 0, DEV_CNT, DEV_NAME);
+    	if (ret < 0)
+    	{
+    		printk("fail to alloc mpu6050_devno\n");
+    		goto alloc_err;
+    	}
+    	/*-------------以下代码省略----------------*/
+    }
+    
+    
+    static int mpu6050_remove(struct i2c_client *client)
+    {
+    	/*删除设备*/
+    	device_destroy(class_mpu6050, mpu6050_devno);	  //清除设备
+    	class_destroy(class_mpu6050);					  //清除类
+    	cdev_del(&mpu6050_chr_dev);						  //清除设备号
+    	unregister_chrdev_region(mpu6050_devno, DEV_CNT); //取消注册字符设备
+    	return 0;
+    }
+
+
+.prob函数和.remove函数实现很简单。在.prob函数仅仅注册了一个字符设备，注册字符设备已经在之前的驱动程序中多次使用，这里不再赘述。.remove函数工作是注销字符设备。
+
+实现字符设备操作函数集
+'''''''''''
+
+在.prob函数中我么添加了一个字符设备，mpu6050的初始化以及转换结果的读取都在这个字符设备的操作函数中实现，其中最主要是.open 和.read函数。下面结合源码介绍这两个函数实现。
+
+.open函数实现
+
+
+我们在.open函数中配置mpu6050，具体代码如下：
+
+.. code-block:: c 
+    :caption: open函数实现
+    :linenos:
+
+    /*字符设备操作函数集，open函数实现*/
+    static int mpu6050_open(struct inode *inode, struct file *filp)
+    {
+    	// printk("\n mpu6050_open \n");
+    
+    	/*向 mpu6050 发送配置数据，让mpu6050处于正常工作状态*/
+    	mpu6050_init();
+    	return 0;
+    }
+    
+    
+    /*初始化i2c
+    *返回值，成功，返回0。失败，返回 -1
+    */
+    static int mpu6050_init(void)
+    {
+    	int error = 0;
+    	/*配置mpu6050*/
+    	error += i2c_write_mpu6050(mpu6050_client, PWR_MGMT_1, 0X00);
+    	error += i2c_write_mpu6050(mpu6050_client, SMPLRT_DIV, 0X07);
+    	error += i2c_write_mpu6050(mpu6050_client, CONFIG, 0X06);
+    	error += i2c_write_mpu6050(mpu6050_client, ACCEL_CONFIG, 0X01);
+    
+    	if (error < 0)
+    	{
+    		/*初始化错误*/
+    		printk(KERN_DEBUG "\n mpu6050_init error \n");
+    		return -1;
+    	}
+    	return 0;
+    }
+    
+    
+    /*通过i2c 向mpu6050写入数据
+    *mpu6050_client：mpu6050的i2c_client结构体。
+    *address, 数据要写入的地址，
+    *data, 要写入的数据
+    *返回值，错误，-1。成功，0  
+    */
+    static int i2c_write_mpu6050(struct i2c_client *mpu6050_client, u8 address, u8 data)
+    {
+    	int error = 0;
+    	u8 write_data[2];
+    	struct i2c_msg send_msg; //要发送的数据结构体
+    
+    	/*设置要发送的数据*/
+    	write_data[0] = address;
+    	write_data[1] = data;
+    
+    	/*发送 iic要写入的地址 reg*/
+    	send_msg.addr = mpu6050_client->addr; //mpu6050在 iic 总线上的地址
+    	send_msg.flags = 0;					  //标记为发送数据
+    	send_msg.buf = write_data;			  //写入的首地址
+    	send_msg.len = 2;					  //reg长度
+    
+    	/*执行发送*/
+    	error = i2c_transfer(mpu6050_client->adapter, &send_msg, 1);
+    	if (error != 1)
+    	{
+    		printk(KERN_DEBUG "\n i2c_transfer error \n");
+    		return -1;
+    	}
+    	return 0;
+    }
+
+
+在.open函数中仅仅调用了我们自己编写的mpu6050_init函数。跳转到mpu6050_init函数，mpu6050初始化函数调用i2c_write_mpu6050函数向mpu6050发送控制参数，这些控制参数的含义可以参考单片机MPU6050相关章节，这里不再介绍，我们重点讲解函数i2c_w
+rite_mpu6050实现。跳转到i2c_write_mpu6050函数，该函数是对i2c_transfer函数的封装，而i2c_transfer是系统提供的i2c设备驱动发送函数，根据之前讲解这个函数最终会调用i2c总线驱动里的函数，最终由i2c总线驱动执行收、发工作。我们这里要做的就是按照规定
+的格式编写要发送的数据。这里用到了两个结构体struct i2c_client和struct i2c_msg介绍如下：
+
+
+
+.. code-block:: c 
+    :caption:  i2c从设备结构体
+    :linenos:
+
+    struct i2c_client {
+    	unsigned short flags;		/* div., see below		*/
+    	unsigned short addr;		/* chip address - NOTE: 7bit	*/
+    					/* addresses are stored in the	*/
+    					/* _LOWER_ 7 bits		*/
+    	char name[I2C_NAME_SIZE];
+    	struct i2c_adapter *adapter;	/* the adapter we sit on	*/
+    	struct device dev;		/* the device structure		*/
+    	int irq;			/* irq issued by device		*/
+    	struct list_head detected;
+    #if IS_ENABLED(CONFIG_I2C_SLAVE)
+    	i2c_slave_cb_t slave_cb;	/* callback for slave mode	*/
+    #endif
+    };
+
+
+
+
+i2c_client结构体用于代表一个i2c从设备，mpu6050挂载到i2c1总线上的从设备。当驱动匹配成功后会通过.prob函数返回i2c从设备（这里就是mpu6050）对应的i2c_client结构体，回到.prob函数“static int mpu6050_probe(struct
+i2c_client \*client, const struct i2c_device_id
+\*id)”。我们在.prob函数中保存返回得到的“i2c_client”结构体即可。在驱动源码中使用全局变量mpu6050_client保存.prob函数返回的i2c从设备结构体，在这里它就代表了mpu6050这个从设备。
+
+既然i2c_client代表一个i2c从设备，那么它应该保存有一个i2c从设备的必要信息，i2c_client结构体参数介绍如下：
+
+1. flags，标志位，用于表示是否使用包错误检查，片上地址位数。
+
+2. addr，芯片地址，也就是我们设置的七位从机地址，对于mpu6050来说，地址是0x68.
+
+3. name，设备名字，名字没有太多要求，最好能够表达设备信息，长度不要超过I2C_NAME_SIZE宏定义指定的长度。
+
+4. adapter, 这是一个i2c_adapter类型的结构体，我么之前说过一个i2c_adapter代表一个i2c总线，这个参数就是用于指定i2c设备（i2c_client）挂载到了那个总线上。
+
+5. dev，这是一个device类型的结构体，device是一个驱动结构体，该参数用于指定i2c设备（从机）驱动的驱动结构体。
+
+6. irq，如果i2c设备驱动（从机）使用了中断，这个参数用于保存设备生成的IRQ。
+
+7. slave_cb，如果开启了从机模式（6ull作为从机）该参数才有用，我们没有开启，该参数不存在。
+
+这些参数由.prob函数带回，其中最主要的是addr、adapter以及dev，这三个参数我们发送数据时会用到。
+
+
+
+.. code-block:: c 
+    :caption:  i2c_msg结构体
+    :linenos:
+
+    struct i2c_msg {
+    	__u16 addr;	/* slave address			*/
+    	__u16 flags;
+    #define I2C_M_TEN		0x0010	/* this is a ten bit chip address */
+    #define I2C_M_RD		0x0001	/* read data, from slave to master */
+    #define I2C_M_STOP		0x8000	/* if I2C_FUNC_PROTOCOL_MANGLING */
+    #define I2C_M_NOSTART		0x4000	/* if I2C_FUNC_NOSTART */
+    #define I2C_M_REV_DIR_ADDR	0x2000	/* if I2C_FUNC_PROTOCOL_MANGLING */
+    #define I2C_M_IGNORE_NAK	0x1000	/* if I2C_FUNC_PROTOCOL_MANGLING */
+    #define I2C_M_NO_RD_ACK		0x0800	/* if I2C_FUNC_PROTOCOL_MANGLING */
+    #define I2C_M_RECV_LEN		0x0400	/* length will be first received byte */
+    	__u16 len;		/* msg length				*/
+    	__u8 *buf;		/* pointer to msg data			*/
+    };
+
+
+
+
+在i2c设备驱动中，数据是基于i2c_msg结构体来发送的。i2c_msg结构体介绍如下：
+
+1. addr，i2c设备地址，这个地址就是i2c设备在i2c总线上的地址。这个地址可以从i2c_client结构体的addr成员得到。
+
+2. flags，发送标志，这个参数的值由一些宏定义组成，为方便使用，这些宏定义添加到了结构体中（根据宏定义的特性，预编译已经处理掉这些宏定义，它们不会影响结构体，更不会多占空间）。下面我们简单常用的几个宏定义。I2C_M_TEN，表示器件是10位地址，根据之前讲解我们使用的是7为地址，linux内核只区
+   分10位地址和其他位数地址，所以我们不选该选项即可。I2C_M_RD，表示这是一个读操作。I2C_M_REV_DIR_ADDR，反转读、写标志位。例如I2C_M_RD \| I2C_M_REV_DIR_ADDR就是一个写操作。通常情况下如果是读，则flags = I2C_M_RD =
+   1。如果为写则flags = I2C_M_RD \| I2C_M_REV_DIR_ADDR =0。其他宏定义的作用使用暂不介绍，如果读者感兴趣可自行阅读代码注释。
+
+3. buf和len，buf保存要发送数据的地址，len设置要发送数据的长度。
+
+知道了struct i2c_client和struct i2c_msg结构体，i2c_write_mpu6050函数就很容易理解了（为方便阅读，这里再次列出i2c_write_mpu6050函数）
+
+
+
+.. code-block:: c 
+    :caption:  i2c_write_mpu6050函数
+    :linenos:
+
+    /*-------------第一部分----------------*/
+    static int i2c_write_mpu6050(struct i2c_client *mpu6050_client, u8 address, u8 data)
+    {
+    	/*-------------第二部分----------------*/
+    	int error = 0;   -------------------①
+    	u8 write_data[2];-------------------②
+    	struct i2c_msg send_msg; //要发送的数据结构体 --------------③
+    
+    	/*设置要发送的数据*/
+    	write_data[0] = address;
+    	write_data[1] = data;
+    
+    	/*发送 iic要写入的地址 reg*/
+    	send_msg.addr = mpu6050_client->addr; //mpu6050在 iic 总线上的地址
+    	send_msg.flags = 0;					  //标记为发送数据
+    	send_msg.buf = write_data;			  //写入的首地址
+    	send_msg.len = 2;					  //reg长度
+    
+    	/*-------------第三部分----------------*/
+    	/*执行发送*/
+    	error = i2c_transfer(mpu6050_client->adapter, &send_msg, 1);
+    	if (error != 1)
+    	{
+    		printk(KERN_DEBUG "\n i2c_transfer error \n");
+    		return -1;
+    	}
+    	return 0;
+    }
+
+
+
+
+第一部分，函数共有三个参数，参数mpu6050_client是i2c_client类型的结构体，填入mpu6050设备对应的i2c_client结构体即可。参数address，用于设置要写入的地址这个地址是要写入mpu6050的内部地址。参数data, 指定要写入的数据。
+
+第二部分，标号①，保存错误状态。标号②要发送的数据，写入数据时要先发送写入的地址然后发送要写入的数据，这里用长度为二的数组保存地址和数据。标号③定义要发送的i2c_msg，前面已经介绍了 i2c_msg结构体，这里只需要填充这个结构体即可。
+
+第三部分，调用i2c_transfer执行发送。这个函数最终会调用i2c总线驱动里的发送函数最终执行数据的收发。函数原型如下：
+
+
+
+.. code-block:: c 
+    :caption:  i2c_transfer函数原型
+    :linenos:
+
+    int i2c_transfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
+
+
+函数共有三个参数，参数adap用于指i2c总线句柄，i2c_client-> adapter保存着i2c设备所使用的i2c总线句柄。参数msgs指定要发送的i2c_msg。参数num用于指定发送的i2c_msg的个数。
+
+.read函数实现
+
+
+mpu6050_read函数源码如下所示。
+
+
+
+.. code-block:: c 
+    :caption:  .read函数原型
+    :linenos:
+
+    /*字符设备操作函数集，.read函数实现*/
+    static ssize_t mpu6050_read(struct file *filp, char __user *buf, size_t cnt, loff_t *off)
+    {
+    
+    	char data_H;
+    	char data_L;
+    	int error;
+    	short mpu6050_result[6]; //保存mpu6050转换得到的原始数据
+    	
+    	/*-------------------第一部分------------------*/
+    	i2c_read_mpu6050(mpu6050_client, ACCEL_XOUT_H, &data_H, 1);
+    	i2c_read_mpu6050(mpu6050_client, ACCEL_XOUT_L, &data_L, 1);
+    	mpu6050_result[0] = data_H << 8;
+    	mpu6050_result[0] += data_L;
+    
+    	i2c_read_mpu6050(mpu6050_client, ACCEL_YOUT_H, &data_H, 1);
+    	i2c_read_mpu6050(mpu6050_client, ACCEL_YOUT_L, &data_L, 1);
+    	mpu6050_result[1] = data_H << 8;
+        mpu6050_result[1] += data_L;
+    
+    	i2c_read_mpu6050(mpu6050_client, ACCEL_ZOUT_H, &data_H, 1);
+    	i2c_read_mpu6050(mpu6050_client, ACCEL_ZOUT_L, &data_L, 1);
+    	mpu6050_result[2] = data_H << 8;
+    	mpu6050_result[2] += data_L;
+    
+    	i2c_read_mpu6050(mpu6050_client, GYRO_XOUT_H, &data_H, 1);
+    	i2c_read_mpu6050(mpu6050_client, GYRO_XOUT_L, &data_L, 1);
+    	mpu6050_result[3] = data_H << 8;
+    	mpu6050_result[3] += data_L;
+    
+    	i2c_read_mpu6050(mpu6050_client, GYRO_YOUT_H, &data_H, 1);
+    	i2c_read_mpu6050(mpu6050_client, GYRO_YOUT_L, &data_L, 1);
+    	mpu6050_result[4] = data_H << 8;
+    	mpu6050_result[4] += data_L;
+    
+    	i2c_read_mpu6050(mpu6050_client, GYRO_ZOUT_H, &data_H, 1);
+    	i2c_read_mpu6050(mpu6050_client, GYRO_ZOUT_L, &data_L, 1);
+    	mpu6050_result[5] = data_H << 8;
+    	mpu6050_result[5] += data_L;
+    
+       /*-------------------第二部分------------------*/
+    	/*将读取得到的数据拷贝到用户空间*/
+    	error = copy_to_user(buf, mpu6050_result, cnt);
+    
+    	if(error != 0)
+    	{
+    		printk("copy_to_user error!");
+    		return -1;
+    	}
+    	return 0;
+    }
+
+
+
+.read函数很简单，大致分为两部分，第一部分，调用i2c_read_mpu6050函数读取mpu6050转换结果。第二部分，调用copy_to_user函数将转换得到的数据拷贝到用户空间。重点是i2c_read_mpu6050函数的实现，该函数实现从mpu6050寄存器中读取转换结果，源码如下：
+
+
+
+.. code-block:: c 
+    :caption:  i2c_read_mpu6050函数实现
+    :linenos:
+
+    /*---------------第一部分-----------------*/
+    static int i2c_read_mpu6050(struct i2c_client *mpu6050_client, u8 address, void *data, u32 length)
+    {
+    	/*---------------第二部分-----------------*/
+    	int error = 0;
+    	u8 address_data = address;  --------①
+    	struct i2c_msg mpu6050_msg[2];------②
+    
+    	/*---------------第三部分-----------------*/
+    	/*设置读取位置i2c_msg*/
+    	mpu6050_msg[0].addr = mpu6050_client->addr; //mpu6050在 iic 总线上的地址
+    	mpu6050_msg[0].flags = 0;					//标记为发送数据
+    	mpu6050_msg[0].buf = &address_data;			//写入的首地址
+    	mpu6050_msg[0].len = 1;						//写入长度
+    
+    	/*读取i2c_msg*/
+    	mpu6050_msg[1].addr = mpu6050_client->addr; //mpu6050在 iic 总线上的地址
+    	mpu6050_msg[1].flags = I2C_M_RD;			//标记为读取数据
+    	mpu6050_msg[1].buf = data;					//读取得到的数据保存位置
+    	mpu6050_msg[1].len = length;				//读取长度
+    
+    	/*---------------第四部分-----------------*/
+    	error = i2c_transfer(mpu6050_client->adapter, mpu6050_msg, 2);
+    
+    	if (error != 2)
+    	{
+    		printk(KERN_DEBUG "\n i2c_read_mpu6050 error \n");
+    		return -1;
+    	}
+    	return 0;
+    }
+
+
+
+它与我们之前讲解的i2c_write_mpu6050函数很相似，结合源码介绍如下：
+
+第一部部分，参数mpu6050_client是i2c_client类型的结构体，填入mpu6050设备对应的i2c_client结构体即可。参数address，用于设置要读取的地址这个地址是要读取的mpu6050的内部地址。参数data,
+保存读取得到的数据。参数length，指定去取长度，单位字节。
+
+第二部分，定义的一些变量，其中标号②是要用到的i2c_msg结构体，读取工作与写入不同，读取时需要先写入要读取的地址然后再执行读取。第三部分将会填充这两个结构体。
+
+第三部分，初始化i2c_msg结构体。这里初始化了两个，第一个是写入要读取的地址，第二个执行读取，特别注意的是第一个i2c_msg结构体的flags设置为0（或者I2C_M_RD \| I2C_M_REV_DIR_ADDR），第二个i2c_msg结构体的flags设置为1（或者I2C_M_RD）。
+
+mpu6050测试应用程序实现
+^^^^^^^^^^^^^^^
+
+这里编写一个简单地测试应用程序测试驱动是否正常，很简单，只需要打开、读取、打印即可。测试代码如下所示。
+
+
+
+
+.. code-block:: c 
+    :caption:  mpu6050测试程序
+    :linenos:
+
+    #include <stdio.h>
+    #include <unistd.h>
+    #include <fcntl.h>
+    #include <string.h>
+    #include <stdlib.h>
+    int main(int argc, char *argv[])
+    {
+    	/*----------------第一部分-----------------*/
+        short resive_data[6];  //保存收到的 mpu6050转换结果数据，依次为 AX(x轴角度), AY, AZ 。GX(x轴加速度), GY ,GZ
+        printf("led_tiny test\n");
+    
+    	/*----------------第二部分-----------------*/
+        /*打开文件*/
+        int fd = open("/dev/I2C1_mpu6050", O_RDWR);
+        if(fd < 0)
+        {
+    		printf("open file : %s failed !\n", argv[0]);
+    		return -1;
+    	}
+    
+    	/*----------------第三部分-----------------*/
+        /*写入命令*/
+        int error = read(fd,resive_data,12);
+        if(error < 0)
+        {
+            printf("write file error! \n");
+            close(fd);
+            /*判断是否关闭成功*/
+        }
+        printf("AX=%d, AY=%d, AZ=%d ",(int)resive_data[0],(int)resive_data[1],(int)resive_data[2]);
+    	printf("    GX=%d, GY=%d, GZ=%d \n \n",(int)resive_data[3],(int)resive_data[4],(int)resive_data[5]);
+    
+        /*关闭文件*/
+        error = close(fd);
+        if(error < 0)
+        {
+            printf("close file error! \n");
+        }
+        
+        return 0;
+    }
+
+
+
+测试应用程序很简单，我们不过多介绍，只说明一点，在驱动的.read函数中我们每次读取了6050的AX, AY, AZ ，GX, GY ,GZ共六个short类型数据，在应用程序中每次读取也要读这么多。
+
+下载验证
+^^^^
+
+首先我么要将编译好的设备树插件添加到系统中，具体方法参照“使用设备树插件实现RGB灯”章节。将编译好的驱动和测试应用程序拷贝到系统。使用imsmod命令加载驱动，正常情况下会输出“匹配成功”提示，并且在“/dev”目录下生成设备节点。如下所示。
+
+.. image:: ./media/i2cmpu004.png
+   :align: center
+   :alt: 4|
+
+接着运行测试应用程序，运行结果如下所示。
+
+.. image:: ./media/i2cmpu005.png
+   :align: center
+   :alt: 5|
+
+注意：这里采集的是原始数据，所以波动较大是正常的。
+
+.. |i2cmpu002| image:: media\i2cmpu002.png
+   :width: 4.6765in
+   :height: 4.78065in
+.. |i2cmpu003| image:: media\i2cmpu003.png
+   :width: 4.62442in
+   :height: 4.33279in
+.. |i2cmpu004| image:: media\i2cmpu004.png
+   :width: 5.76806in
+   :height: 0.53681in
+.. |i2cmpu005| image:: media\i2cmpu005.png
+   :width: 5.76806in
+   :height: 0.81736in
diff --git a/documentation/linux_driver/led_character_device.rst b/documentation/linux_driver/led_character_device.rst
new file mode 100644
index 0000000000000000000000000000000000000000..b17c515e25b1c0f7f39c3e08d55f881ed56504ef
--- /dev/null
+++ b/documentation/linux_driver/led_character_device.rst
@@ -0,0 +1,8 @@
+.. vim: syntax=rst
+
+字符设备驱动——点亮LED灯
+------------------------------------
+
+
+
+
diff --git a/documentation/linux_driver/linux_device_model.rst b/documentation/linux_driver/linux_device_model.rst
new file mode 100644
index 0000000000000000000000000000000000000000..1531ff0e7f7fde3a18f2d0b7cabb96131d1b59d8
--- /dev/null
+++ b/documentation/linux_driver/linux_device_model.rst
@@ -0,0 +1,656 @@
+.. vim: syntax=rst
+
+
+Linux的设备模型
+==================
+到目前为止，我们已经接触了如何编写内核模块以及简单的字符设备驱动了，算是半只脚踏进Linux的大门了。
+但着这会这些内容，还远远不够。通过前面两章的学习，我们发现，Linux的驱动代码不能够让我们随心所欲地写，它都具有一定的“套路”，
+比如某个函数负责初始化，某个函数负责注册设备等等。虽然如此，但是却也给我们带来了极大的便利。我们可以不需要关心内核是如何工作的，
+只需要编写好我们的驱动文件，然后加载进内核，这样就可以使我们的设备开始工作，当然啦，前提肯定是驱动是正确无误。因此，在Linux开发驱动，
+只要能够掌握了这些“套路”，开发一个驱动便不是难事。当然，我们不提倡自己从零开始写一个设备驱动，在内核源码的drivers中存放了大量的设备驱动代码，
+说不定可以在这些目录找到想要的驱动代码，如图所示：
+
+.. image:: ./media/code_drivers.jpg
+   :align: center
+   :alt: 内核提供的驱动代码
+
+
+本章节，我们主要讲解Linux的设备模型，在旧版本的Linux代码中，内核无法知道：当前系统中存在什么设备、各个设备的电源管理方式、设备挂载在哪个总线上等信息。
+为此，Linux2.6版本开始提出了Linux设备模型（Linux device model），该设备模型通过几个数据结构来反映当前系统中总线、设备以及驱动的工作状况，提出了以下几个重要概念：
+
+- 设备(device)：挂载在某个总线的物理设备；
+- 驱动(driver)：与特定设备相关的软件，负责初始化该设备以及提供一些操作该设备的操作方式；
+- 总线（bus)：负责管理挂载对应总线的设备以及驱动；
+- 类(class)：对于具有相同功能的设备，归结到一种类别，进行分类管理；
+
+
+无论以后学习平台设备驱动、块设备驱动或者是其他总线设备，都跟Linux设备模型息息相关。此外，关于Linux设备模型与sysfs的关系，在讲解Linux文件目录结构时，提到过sysfs文件系统，该文件系统用于把内核的设备驱动导出到用户空间，用户便可通过访问sys目录及其下的文件，来查看甚至控制内核的一些驱动设备。
+学完本章的内容，我们也可以将我们驱动的某个控制变量，导出到用户空间。
+
+
+
+
+
+总线
+~~~~
+总线是连接处理器和设备之间的桥梁，我们接触到的设备大部分是依靠总线来进行通信的，它们之间的物理连接如图所示，对于野火开发板而言，触摸芯片是依赖于I2C，鼠标、键盘等HID设备，
+则是依赖于USB。从功能上讲，这些设备都是将文字、字符、控制命令或采集的数据等信息输入到计算机。
+
+.. image:: ./media/LDM.jpg
+   :align: center
+   :alt: Linux设备模型
+
+总线驱动则负责实现总线的各种行为，其管理着两个链表，分别是添加到该总线的设备链表以及注册到该总线的驱动链表。当你向总线添加（移除）一个设备（驱动）时，便会在对应的列表上添加新的节点，
+同时对挂载在该总线的驱动以及设备进行匹配，在匹配过程中会忽略掉那些已经有驱动匹配的设备。
+
+.. image:: ./media/bus_model.jpg
+   :align: center
+   :alt: 总线结构
+
+在内核中使用结构体bus_type来表示总线，如下所示：
+
+.. code-block:: c 
+    :caption: bus_type结构体（内核源码/include/linux/device.h）
+    :linenos:
+
+    struct bus_type {
+	const char		*name;
+	const struct attribute_group **bus_groups;
+	const struct attribute_group **dev_groups;
+	const struct attribute_group **drv_groups;
+
+	int (*match)(struct device *dev, struct device_driver *drv);
+	int (*uevent)(struct device *dev, struct kobj_uevent_env *env);
+	int (*probe)(struct device *dev);
+	int (*remove)(struct device *dev);
+
+	int (*suspend)(struct device *dev, pm_message_t state);
+	int (*resume)(struct device *dev);
+
+	const struct dev_pm_ops *pm;
+
+	struct subsys_private *p;
+
+    };
+
+- name : 指定总线的名称，当新注册一种总线类型时，会在/sys/bus目录创建一个新的目录，目录名就是该参数的值；
+- drv_groups 、dev_groups 、bus_groups: 分别表示驱动、设备以及总线的属性。这些属性可以是内部变量、字符串等等。通常会对应的/sys目录下在以文件的形式存在，对于驱动而言，在目录/sys/bus/<bus-name>/driver/<driver-name>存放了设备的默认属性；设备则在目录/sys/bus/<bus-name>/devices/<driver-name>中。这些文件一般是可读写的，用户可以通过读写操作来获取和设置这些attribute的值。
+- match : 当向总线注册一个新的设备或者是新的驱动时，会调用该回调函数。该回调函数主要负责判断是否有注册了的驱动适合新的设备，或者新的驱动能否驱动总线上已注册但没有驱动匹配的设备；
+- uevent：总线上的设备发生添加、移除或者其它动作时，就会调用该函数，来通知驱动做出相应的对策。
+- probe : 当总线将设备以及驱动相匹配之后，执行该回调函数,最终会调用驱动提供的probe函数。
+- remove : 当设备从总线移除时，调用该回调函数；
+- suspend、resume : 电源管理的相关函数，当总线进入睡眠模式时，会调用suspend回调函数；而resume回调函数则是在唤醒总线的状态下执行；
+- pm : 电源管理的结构体，存放了一系列跟总线电源管理有关的函数，与device_driver结构体中的pm_ops有关；
+- p：该结构体用于存放特定的私有数据，其成员klist_devices和klist_drivers记录了挂载在该总线的设备和驱动；
+
+Linux内核已经为我们写好了大部分总线驱动，我们一般不会去注册一个新的总线，内核中提供了bus_register函数来注册总线，以及bus_unregister函数来注销总线，其函数原型如下：
+
+.. code-block:: c 
+    :caption: 注册/注销总线API（内核源码/drivers/base/bus.c）
+    :linenos: 
+
+    int bus_register(struct bus_type *bus);
+    void bus_unregister(struct bus_type *bus);
+
+当我们成功注册总线时，会在/sys/bus/目录下创建一个新目录，目录名为我们新注册的总线名。bus目录中包含了当前系统中已经注册了的所有总线，例如i2c，spi，platform等。我们看到每个总线目录都拥有两个子目录devices和drivers，
+分别记录着挂载在该总线的所有设备以及驱动。
+
+.. image:: ./media/bus.jpg
+   :align: center
+   :alt: /sys/bus目录
+
+设备
+~~~~
+驱动开发的过程中，我们最关心的莫过于设备以及对应的驱动了。我们编写驱动的目的，最终就是为了使设备可以正常工作。在Linux中，一切都是以文件的形式存在，
+设备也不例外。/sys/devices目录记录了系统中所有设备，实际上在sys目录下所有设备文件最终都会指向该目录对应的设备文件；此外还有另一个目录/sys/dev记录所有的设备节点，
+但实际上都是些链接文件，同样指向了devices目录下的文件。
+
+.. image:: ./media/dev.jpg
+   :align: center
+   :alt: /sys/dev目录
+
+
+在内核使用device结构体来描述我们的物理设备，如下所示，
+
+.. code-block:: c 
+	:caption: device结构体(内核源码/include/linux/device.h）
+	:linenos:
+
+	struct device {
+        const char *init_name;
+		struct device		*parent;
+		struct bus_type	*bus;		
+		struct device_driver *driver;	
+		void		*platform_data;	
+		void		*driver_data;	
+		struct device_node	*of_node; 
+		dev_t			devt;	
+		struct class		*class;
+        void (*release)(struct device *dev);
+		const struct attribute_group **groups;	/* optional groups */
+	};	
+
+- init_name：指定该设备的名称，总线匹配时，一般会根据比较名字，来进行配对；
+- parent：表示该设备的父对象，前面提到过，旧版本的设备之间没有任何关联，引入Linux设备模型之后，设备之间呈树状结构，便于管理各种设备；
+- bus：表示该设备依赖于哪个总线，当我们注册设备时，内核便会将该设备注册到对应的总线。
+- of_node：存放设备树中匹配的设备节点。当内核使能设备树，总线负责将驱动的of_match_table以及设备树的compatible属性进行比较之后，将匹配的节点保存到该变量。
+- platform_data：特定设备的私有数据，通常定义在板级文件中；
+- driver_data：同上，驱动层可通过dev_set/get_drvdata函数来获取该成员；
+- class：指向了该设备对应类，开篇我们提到的触摸，鼠标以及键盘等设备，对于计算机而言，他们都具有相同的功能，都归属于输入设备。我们可以在/sys/class目录下对应的类找到该设备，如input、leds、pwm等目录;
+- dev：dev_t类型变量，字符设备章节提及过，它是用于标识设备的设备号，该变量主要用于向/sys目录中导出对应的设备。
+- release：回调函数，当设备被注销时，会调用该函数。如果我们没定义该函数时，移除设备时，会提示“Device 'xxxx' does not have a release() function, it is broken and must be fixed”的错误。
+- group：指向struct attribute_group类型的指针，指定该设备的属性；
+
+内核也提供相关的API来注册和注销设备，如下所示：
+
+.. code-block:: c 
+    :caption: 内核注册/注销设备(内核源码/driver/base/core.c）
+    :linenos: 
+
+    int device_register(struct device *dev);
+    void device_unregister(struct device *dev);
+
+在讲解总线的时候，我们说过，当成功注册总线时，会在/sys/bus目录下创建对应总线的目录，该目录下有两个子目录，分别是drivers和devices，
+我们使用device_register注册的设备从属于某个总线时，该总线的devices目录下便会存在该设备文件。
+
+驱动
+~~~~
+前面两小节，已经大致介绍完总线以及设备。设备能否正常工作，取决于驱动。驱动需要告诉内核，
+自己可以驱动哪些设备，如何初始化设备。在内核中，使用device_driver结构体来描述我们的驱动，如下所示：
+
+.. code-block:: c 
+	:caption: device_driver结构体(内核源码/include/linux/device.h）
+	:linenos:
+
+	struct device_driver {
+		const char		*name;
+		struct bus_type		*bus;
+
+		struct module		*owner;
+		const char		*mod_name;	/* used for built-in modules */
+
+		bool suppress_bind_attrs;	/* disables bind/unbind via sysfs */
+
+		const struct of_device_id	*of_match_table;
+		const struct acpi_device_id	*acpi_match_table;
+
+		int (*probe) (struct device *dev);
+		int (*remove) (struct device *dev);
+
+		const struct attribute_group **groups;
+	};	
+
+- name：指定驱动名称，总线进行匹配时，利用该成员与设备名进行比较；
+- bus：表示该驱动依赖于哪个总线，内核需要保证在驱动执行之前，对应的总线能够正常工作；
+- suppress_bind_attrs：布尔量，用于指定是否通过sysfs导出bind与unbind文件，bind与unbind文件是驱动用于绑定/解绑关联的设备。
+- owner：表示该驱动的拥有者，一般设置为THIS_MODULE；
+- of_match_table：指定该驱动支持的设备类型。当内核使能设备树时，会利用该成员与设备树中的compatible属性进行比较。
+- remove：当设备从操作系统中拔出或者是系统重启时，会调用该回调函数；
+- probe：当驱动以及设备匹配后，会执行该回调函数，对设备进行初始化。通常的代码，都是以main函数开始执行的，但是在内核的驱动代码，都是从probe函数开始的。
+- group：指向struct attribute_group类型的指针，指定该驱动的属性；
+
+内核提供了driver_register函数以及driver_unregister函数来注册/注销驱动，成功注册的驱动会记录在/sys/bus/<bus>/drivers目录，
+函数原型如下所示：
+
+.. code-block:: c 
+    :caption: device_driver结构体(内核源码/include/linux/device.h）
+    :linenos: 
+
+    int driver_register(struct device_driver *drv);
+    void driver_unregister(struct device_driver *drv);
+
+attribute属性文件
+~~~~~~~~~~~~
+/sys目录有各种子目录以及文件，前面讲过当我们注册新的总线、设备或驱动时，内核会在对应的地方创建一个新的目录，目录名为各自结构体的name成员，
+每个子目录下的文件，都是内核导出到用户空间，用于控制我们的设备的。内核中以attribute结构体来描述/sys目录下的文件，如下所示：
+
+.. code-block:: c 
+    :caption: struct attribute结构体（内核源码/include/linux/sysfs.h)
+    :linenos:
+
+    struct attribute {
+        const char		*name;
+        umode_t			mode;        
+    };
+
+- name：指定文件的文件名；
+- mode：指定文件的权限，
+
+bus_type、device、device_driver结构体中都包含了一种数据类型struct attribute_group，如下所示，它是多个attribute文件的集合，
+利用它进行初始化，可以避免一个个注册attribute。
+
+.. code-block:: c 
+    :caption: struct attribute_group结构体（内核源码/include/linux/sysfs.h)
+    :linenos:
+
+    struct attribute_group {
+        const char		*name;
+        umode_t			(*is_visible)(struct kobject *,
+                            struct attribute *, int);
+        struct attribute	**attrs;
+        struct bin_attribute	**bin_attrs;
+    };
+
+
+设备属性文件
+------------
+在开发单片机的时候，如果想要读取某个寄存器的值，你可能需要加入一些新的代码，并重新编译。但对于Linux内核来讲，每次都需要编译一遍源码，
+实在太浪费时间和精力了。为此，Linux提供以下接口，来注册和注销一个设备属性文件。我们可以通过这些接口直接在用户层进行查询/修改，避免了重新编译内核的麻烦。
+
+.. code-block:: c 
+    :caption: 设备属性文件接口（内核源码/include/linux/device.h)
+    :linenos:
+
+    struct device_attribute {
+        struct attribute	attr;
+        ssize_t (*show)(struct device *dev, struct device_attribute *attr,
+                char *buf);
+        ssize_t (*store)(struct device *dev, struct device_attribute *attr,
+                const char *buf, size_t count);
+    };
+
+    #define DEVICE_ATTR(_name, _mode, _show, _store) \
+	    struct device_attribute dev_attr_##_name = __ATTR(_name, _mode, _show, _store)
+    extern int device_create_file(struct device *device,
+                    const struct device_attribute *entry);
+    extern void device_remove_file(struct device *dev,
+                    const struct device_attribute *attr);   
+
+DEVICE_ATTR宏定义用于定义一个device_attribute类型的变量，##表示将##左右两边的标签拼接在一起，因此，我们得到变量的名称应该是带有dev_attr_前缀的。
+该宏定义需要传入四个参数_name，_mode，_show，_store，分别代表了文件名，文件权限，show回调函数，store回调函数。show回调函数以及store回调函数分别对应着用户层的cat和echo命令，
+当我们使用cat命令，来获取/sys目录下某个文件时，最终会执行show回调函数；使用echo命令，则会执行store回调函数。
+参数_mode的值，可以使用S_IRUSR、S_IWUSR、S_IXUSR等宏定义，更多选项可以查看读写文件章节关于文件权限的内容。
+
+device_create_file函数用于创建文件，它有两个参数成员，第一个参数表示的是设备，前面讲解device结构体时，其成员中有个bus_type变量，
+用于指定设备挂载在某个总线上，并且会在总线的devices子目录创建一个属于该设备的目录，device参数可以理解为在哪个设备目录下，创建设备文件。
+第二个参数则是我们自己定义的device_attribute类型变量。
+
+device_remove_file函数用于删除文件，当我们的驱动注销时，对应目录以及文件都需要被移除。
+其参数和device_create_file函数的参数是一样，这里就不进行解释。
+
+
+驱动属性文件
+------------
+驱动属性文件，和设备属性文件的作用是一样，唯一的区别在于函数参数的不同，函数接口如下：
+
+.. code-block:: c 
+    :caption: 驱动属性文件接口（内核源码/include/linux/device.h)
+    :linenos:
+
+    struct driver_attribute {
+        struct attribute attr;
+        ssize_t (*show)(struct device_driver *driver, char *buf);
+        ssize_t (*store)(struct device_driver *driver, const char *buf,
+                size_t count);
+    };
+
+    #define DRIVER_ATTR_RW(_name) \
+        struct driver_attribute driver_attr_##_name = __ATTR_RW(_name)
+    #define DRIVER_ATTR_RO(_name) \
+        struct driver_attribute driver_attr_##_name = __ATTR_RO(_name)
+    #define DRIVER_ATTR_WO(_name) \
+        struct driver_attribute driver_attr_##_name = __ATTR_WO(_name)
+        
+    extern int __must_check driver_create_file(struct device_driver *driver,
+					const struct driver_attribute *attr);
+    extern void driver_remove_file(struct device_driver *driver,
+                    const struct driver_attribute *attr);
+
+DRIVER_ATTR_RW、DRIVER_ATTR_RO以及DRIVER_ATTR_WO宏定义用于定义一个driver_attribute类型的变量，带有driver_attr_的前缀，区别在于文件权限不同，RW后缀表示文件可读写，RO后缀表示文件仅可读，
+WO后缀表示文件仅可写。而且你会发现，DRIVER_ATTR类型的宏定义没有参数来设置show和store回调函数，那如何设置这两个参数呢？在写驱动代码时，只需要你提供xxx_store以及xxx_show这两个函数，
+并确保两个函数的xxx和DRIVER_ATTR类型的宏定义中名字是一致的即可。
+
+driver_create_file和driver_remove_file函数用于创建和移除文件，使用driver_create_file函数，会在/sys/bus/<bus-name>/drivers/<driver-name>/目录下创建文件。
+
+
+总线属性文件
+-----------
+同样的，Linux也为总线通过了相应的函数接口，如下所示：
+
+.. code-block:: c 
+    :caption: 总线属性文件接口（内核源码/include/linux/device.h)
+    :linenos:
+
+    struct bus_attribute {
+        struct attribute	attr;
+        ssize_t (*show)(struct bus_type *bus, char *buf);
+        ssize_t (*store)(struct bus_type *bus, const char *buf, size_t count);
+    };
+    #define BUS_ATTR(_name, _mode, _show, _store)	\
+	    struct bus_attribute bus_attr_##_name = __ATTR(_name, _mode, _show, _store)
+    extern int __must_check bus_create_file(struct bus_type *,
+                        struct bus_attribute *);
+    extern void bus_remove_file(struct bus_type *, struct bus_attribute *);
+
+BUS_ATTR宏定义用于定义一个bus_attribute变量，使用bus_create_file函数，会在/sys/bus/<bus-name>下创建对应的文件。
+bus_remove_file则用于移除该文件。
+
+实验
+~~~~~~~~
+下面，我们利用前面学到的理论知识，来创建一个虚拟的总线xbus，分别挂载了驱动xdrv以及设备xdev。
+
+**本章的示例代码目录为：base_code/linux_driver/linux_device_model**
+
+Makefile
+------
+工欲善其事必先利其器，在开始写程序之前，我们需要先准备好我们的Makefile。针对当前开发板使用的是debian的镜像，那么我们便可以直接在开发板上进行编译，
+前提是板子上已经安装了gcc以及make工具。
+
+
+   :caption: Makefile(位于../base_code/linux_driver/linux_device_model/Makefile)
+   :language: makefile
+   :linenos: 	
+	
+	NATIVE ?= true
+
+
+	ifeq ($(NATIVE), false)
+		KERNEL_DIR = /home/embedfire/linux4.19
+	else
+		KERNEL_DIR = /lib/modules/$(shell uname -r)/build
+	endif
+
+
+
+
+	obj-m := xdev.o xbus.o xdrv.o
+
+	all:modules
+	modules clean:
+		$(MAKE) -C $(KERNEL_DIR) M=$(shell pwd) $@
+
+我们通过变量NATIVE来控制我们的编译环境，该Makefile默认设置是在开发板进行编译，对于想要在PC机进行交叉编译的读者，需要指定变量KERNEL_DIR为自己内核源码的路径，
+再执行命令“make NATIVE=false”，完成编译。
+
+总线
+--------
+
+定义新的总线
+^^^^^^^^^^^^^^^^^^^^^
+
+.. code-block:: c 
+    :caption: 定义bus_type结构体（位于../base_code/linux_driver/linux_device_model/xbus.c)
+    :linenos:
+
+    int xbus_match(struct device *dev, struct device_driver *drv)
+    {
+        printk("%s-%s\n",__FILE__, __func__);
+        if(!strncmp(dev_name(dev), drv->name, strlen(drv->name))){
+            printk("dev & drv match\n");
+            return 1;	
+        }
+        return 0;
+    }
+
+    static struct bus_type xbus = {
+        .name = "xbus",
+        .match = xbus_match,
+    };
+    EXPORT_SYMBOL(xbus);
+
+代码中定义了一种新的总线，名为xbus，总线结构体中最重要的一个成员，便是match回调函数，这个函数负责总线下的设备以及驱动匹配，
+没有这个函数，设备与驱动便不可以进行匹配。这里，我们使用字符串比较的方式，通过对比驱动以及设备的名字来确定是否匹配，如果相同，
+则说明匹配成功，返回1；反之，则返回0。
+
+导出总线属性文件
+^^^^^^^^^^^^^^^^^^^^^
+我们通过BUS_ATTR宏，将我们自定义的变量导出到/sys目录，方便用户查询。
+
+.. code-block:: c 
+    :caption: 定义bus_type结构体（位于../base_code/linux_driver/linux_device_model/xbus.c)
+    :linenos:
+
+    static char *bus_name = "xbus";
+
+    ssize_t xbus_test_show(struct bus_type *bus, char *buf)
+    {
+        return sprintf(buf, "%s\n", bus_name);
+    }
+
+    BUS_ATTR(xbus_test, S_IRUSR, xbus_test_show, NULL);
+
+代码中，定义了一个bus_name变量，存放了该总线的名字，并且提供show回调函数，这样用户便可以通过cat命令，
+来查询总线的名称，并且设置该文件的文件权限为文件拥有者可读，组内成员以及其他成员不可操作。
+
+注册总线
+^^^^^^^^^^^^^^^^^^^^^
+内核的驱动代码，都是基于内核模块，我们在模块初始化的函数中注册总线，在模块注销的函数中注销该总线。
+
+.. code-block:: c 
+    :caption: 模块初始化以及注销函数（位于../base_code/linux_driver/linux_device_model/xbus.c)
+    :linenos:
+
+    static __init int xbus_init(void)
+    {
+        printk("xbus init\n");
+        
+        bus_register(&xbus);
+        bus_create_file(&xbus, &bus_attr_xbus_test);
+        return 0;
+    }
+    module_init(xbus_init);
+
+
+    static __exit void xbus_exit(void)
+    {
+        printk("xbus exit\n");
+        bus_remove_file(&xbus, &bus_attr_xbus_test);
+        bus_unregister(&xbus);
+    }
+    module_exit(xbus_exit);
+
+    MODULE_AUTHOR("embedfire");
+    MODULE_LICENSE("GPL");
+
+这样的代码，就完成了总线的注册，当我们成功加载该内核模块时，内核便会出现一种新的总线xbus,如图所示：
+
+.. image:: ./media/xbus.jpg
+   :align: center
+   :alt: xbus目录
+
+我们可以看到，总线的devices和drivers目录都是空的，并没有什么设备和驱动挂载在该总线下。红框处便是我们自定义的总线属性文件，当我们执行命令"cat    xbus_test"时，可以看到终端上会打印一行字符串：xbus。
+
+设备
+--------
+Linux设备模型中，总线已经注册好了，还缺少设备和驱动。注册一个新的设备，主要完成这两个工作：一个是名字，
+这是总相匹配的依据；另一个就是总线，该设备挂载在哪个总线上，不能张冠李戴。
+
+这里，我们注册一个设备xdev，并且定义一个变量id，将该变量导出到用户空间，使得用户可以通过sysfs文件系统来修改该变量的值。
+
+定义新的设备
+^^^^^^^^^^^^^^^^^^^^^
+
+.. code-block:: c 
+    :caption: 定义device结构体（位于../base_code/linux_driver/linux_device_model/xdev.c)
+    :linenos:
+
+    extern struct bus_type xbus;
+
+    void xdev_release(struct device *dev)
+    {
+        printk("%s-%s\n", __FILE__, __func__);
+    }
+
+
+    static struct device xdev = {
+        .init_name = "xdev",
+        .bus = &xbus,
+        .release = xdev_release,
+    };
+
+代码中，定义了一个名为xdev的设备，其挂载在xbus上，这里写了一个release函数，防止卸载模块时会报错。相对于注册总线来说，
+还是相对比较简单。
+
+导出设备属性文件
+^^^^^^^^^^^^^^^^^^^^^
+
+.. code-block:: c 
+    :caption: 定义设备属性文件（位于../base_code/linux_driver/linux_device_model/xdev.c)
+    :linenos:
+
+    unsigned long id = 0;
+    ssize_t xdev_id_show(struct device *dev, struct device_attribute *attr,
+                    char *buf)
+    {
+        return sprintf(buf, "%d\n", id);
+    }
+
+    ssize_t xdev_id_store(struct device *dev, struct device_attribute *attr,
+                    const char *buf, size_t count)
+    {
+        kstrtoul(buf, 10, &id);
+        return count;  	
+    }
+
+
+    DEVICE_ATTR(xdev_id, S_IRUSR|S_IWUSR, xdev_id_show, xdev_id_store);
+
+
+使用DEVICE_ATTR宏定义定义了xdev_id，并且设置该文件的文件权限是文件拥有者可读可写，组内成员以及其他成员不可操作。
+show回调函数中，直接将id的值通过sprintf函数拷贝至buf中。store回调函数则是利用kstrtoul函数，该函数有三个参数，其中第二个参数是采用几进制的方式，
+这里我们传入的是10，意味着buf中的内容将转换为10进制的数传递给id，实现了通过sysfs修改驱动的目的。
+
+注册设备
+^^^^^^^^^^^^^^^^^^^^^
+最后，只需要调用device_register函数以及device_create_file函数，将上面的设备结构体以及属性文件结构体注册到内核即可。
+
+.. code-block:: c 
+    :caption: 注册/注销设备（位于../base_code/linux_driver/linux_device_model/xdev.c)
+    :linenos:
+
+    static __init int xdev_init(void)
+    {
+        printk("xdev init\n");
+        device_register(&xdev);
+        device_create_file(&xdev, &dev_attr_xdev_id);
+        return 0;
+    }
+    module_init(xdev_init);
+
+
+    static __exit void xdev_exit(void)
+    {
+        printk("xdev exit\n");
+        device_remove_file(&xdev, &dev_attr_xdev_id);
+        device_unregister(&xdev);
+    }
+    module_exit(xdev_exit);
+
+    MODULE_AUTHOR("embedfire");
+    MODULE_LICENSE("GPL");
+
+加载内核模块后，我们可以看到在/sys/bus/xbus/devices/中多了个设备xdev，它是个链接文件，最终指向了/sys/devices中的设备。
+
+.. image:: ./media/xdev.jpg
+   :align: center
+   :alt: xdev目录
+
+我们直接切换到xdev的目录下，可以看到，我们自定义的属性文件xdev_id。
+
+.. image:: ./media/xdevid.jpg
+   :align: center
+   :alt: xdevid文件
+
+通过echo以及cat命令，可以进行修改和查询，如下所示：
+
+.. image:: ./media/exec.jpg
+   :align: center
+   :alt: 修改xdev_id文件
+
+驱动
+-------
+关于驱动的部分，由于本章实验没有具体的物理设备，因此，没有涉及到设备初始化、设备的函数接口等内容。
+
+定义新的驱动
+^^^^^^^^^^^^^^^^^^^^^
+
+.. code-block:: c 
+    :caption: 定义device_driver结构体（位于../base_code/linux_driver/linux_device_model/xdrv.c)
+    :linenos:
+
+    extern struct bus_type xbus;
+
+    int xdrv_probe(struct device *dev)
+    {
+        printk("%s-%s\n", __FILE__, __func__);
+        return 0;
+    }
+
+    int xdrv_remove(struct device *dev)
+    {
+        printk("%s-%s\n", __FILE__, __func__);
+        return 0;
+    }
+
+    static struct device_driver xdrv = {
+        .name = "xdev",
+        .bus = &xbus,
+        .probe = xdrv_probe,
+        .remove = xdrv_remove,
+    };
+
+代码中定义了一个驱动结构体xdrv，名字需要和设备的名字相同，否则就不能成功匹配。该驱动挂载在已经注册好的总线xbus下。
+当驱动和设备匹配成功之后，便会执行驱动的probe函数，这里只是在终端上打印当前的文件以及函数名。
+xdrv_remove函数，当注销驱动时，需要关闭物理设备的某些功能等，这里也只是打印出当前的文件名以及函数名。
+
+导出驱动属性文件
+^^^^^^^^^^^^^^^^^^^^^
+
+.. code-block:: c 
+    :caption: 定义device_driver结构体（位于../base_code/linux_driver/linux_device_model/xdrv.c)
+    :linenos:
+
+    char *name = "xdrv";
+    ssize_t drvname_show(struct device_driver *drv, char *buf)
+    {
+        return sprintf(buf, "%s\n", name);
+    }
+
+    DRIVER_ATTR_RO(drvname);
+
+在讲驱动属性文件时，我们讲到DRIVER_ATTR_RO定义驱动属性文件时，没有参数可以设置show和store回调函数，我们只要保证store和show函数的前缀与驱动属性文件一致即可。
+如代码所示，定义了一个drvname属性文件，show回调函数的函数名则为drvname_show，这样便可以完成两者之间的关联。
+
+注册驱动
+^^^^^^^^^^^^^^^^^^^^^
+最后，调用driver_register函数以及driver_create_file函数进行注册我们的驱动以及驱动属性文件。
+
+.. code-block:: c 
+    :caption: 模块注册/注销函数（位于../base_code/linux_driver/linux_device_model/xdrv.c)
+    :linenos:
+
+    static __init int xdrv_init(void)
+    {
+        printk("xdrv init\n");
+        driver_register(&xdrv);
+        driver_create_file(&xdrv, &driver_attr_drvname);
+        return 0;
+    }
+    module_init(xdrv_init);
+
+    static __exit void xdrv_exit(void)
+    {
+        printk("xdrv exit\n");
+        driver_remove_file(&xdrv, &driver_attr_drvname);
+        driver_unregister(&xdrv);
+    }
+    module_exit(xdrv_exit);
+
+    MODULE_AUTHOR("embedfire");
+    MODULE_LICENSE("GPL");
+
+成功加载驱动后，可以看到/sys/bus/xbus/driver多了个驱动xdev目录，如图所示：在该目录下存在一个我们自定义的属性文件，
+使用cat命令读该文件的内容，终端会打印字符串"xdrv"。
+
+.. image:: ./media/xdrv.jpg
+   :align: center
+   :alt: drivers目录
+
+使用命令“demsg | tail”来查看模块加载过程的打印信息，当我们加载完设备和驱动之后，总线开始进行匹配，执行match函数，
+发现这两个设备的名字是一致的，就将设备和驱动关联到一起，最后会执行驱动的probe函数。
+
+.. image:: ./media/dmesg.jpg
+   :align: center
+   :alt: drivers目录
+   
+
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diff --git a/documentation/linux_driver/media/xdrv.jpg b/documentation/linux_driver/media/xdrv.jpg
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diff --git a/documentation/linux_driver/module.rst b/documentation/linux_driver/module.rst
index 2b91bf49f5f8f8ddae66efbec0803ffe0139d5c9..a26c289c76dab67990c6cc4e577e69c8a54b4f45 100644
--- a/documentation/linux_driver/module.rst
+++ b/documentation/linux_driver/module.rst
@@ -7,7 +7,8 @@
 
 本章节内容处于开发笔记状态，还待整理至最终版的教程。
 
-从本章开始，我们就要真真正正地步入Linux设备驱动的殿堂了。了解一样新事物，无非就是围绕这“这东西是什么”，“这东西怎么用”，“能不能给我整一个”这三个问题。
+从本章开始，我们就要真真正正地步入Linux设备驱动的殿堂了。了解一样新事物，无非就
+是围绕这"这东西是什么"，"这东西怎么用"，"能不能给我整一个"这三个问题。
 
 本章大致分为三个部分：
 
@@ -17,23 +18,30 @@
 
 3. 如何自己写一个简单的模块，学完本节内容就可以给自己整一个简单的内核模块。
 
+
+
 为什么需要内核模块
 ~~~~~~~~~
 
 内核按照体系结构分为两类：微内核（microkernel）和宏内核（macrokernel）。
 
-Windows操作系统、华为的鸿蒙操作系统就属于微内核结构。微内核是提供操作系统核心功能的内核的精简版，实现进程管理、存储器管理、进程间通信、I/O设备管理等基本功能，其他功能模块则需要单独进行编译，具有动态扩展性的优点。
+Windows操作系统、华为的鸿蒙操作系统就属于微内核结构。微内核是提供操作系统核心功能的内核
+的精简版，实现进程管理、存储器管理、进程间通信、I/O设备管理等基本功能，其他功能模块则需要单独进行编译，具有动态扩展性的优点。
 
-而Linux操作系统则是采用了宏内核结构。宏内核是将内核所有的功能都编译成一个整体，其优点是执行效率非常高，缺点也是十分明显的，一旦我们想要修改、增加内核某个功能时，都需要重新编译一遍内核。
+而Linux操作系统则是采用了宏内核结构。宏内核是将内核所有的功能都编译成一个整体，其优点是执行
+效率非常高，缺点也是十分明显的，一旦我们想要修改、增加内核某个功能时，都需要重新编译一遍内核。
 
-为了解决这个问题，Linux引入了内核模块这一机制。内核模块就是实现了某个功能的一段内核代码，在内核运行过程，可以加载这部分代码到内核中， 从而动态地增加了内核的功能。基于这种特性，我们进行设备驱动开发时，以内核模块的形式编写设备驱动，只需要编译相关的驱动代码即可，无需对整个内核进行编译。
+为了解决这个问题，Linux引入了内核模块这一机制。内核模块就是实现了某个功能的一段内核代
+码，在内核运行过程，可以加载这部分代码到内核中， 从而动态地增加了内核的功能。基于这种特性，我们进行
+设备驱动开发时，以内核模块的形式编写设备驱动，只需要编译相关的驱动代码即可，无需对整个内核进行编译。
 
 内核模块相关命令
 ~~~~~~~~
 
-通过上一节的学习，我们知道了内核模块是什么东西，那么学完本小节的内容，我们就知道内核模块该如何使用。Linux提供了关于内核模块的一系列命令，见表格 56‑1 内核模块相关命令。
+通过上一节的学习，我们知道了内核模块是什么东西，那么学完本小节的内容，我们就知道内核模块该
+如何使用。Linux提供了关于内核模块的一系列命令，见下表 内核模块相关命令。
 
-表格 56‑1 内核模块相关命令
+表  内核模块相关命令
 
 ======== ==============================================================================================
 命令     作用
@@ -46,13 +54,19 @@ depmod   用于分析检测内核模块之间的依赖关系。
 modprobe 同样用于加载内核模块，与insmod不同，modprobe会根据depmod产生的依赖关系，加载依赖的的其他模块。
 ======== ==============================================================================================
 
-在本章的例程文件中，提供了一个hello_world.ko的内核模块。我们可以使用命令modinfo，来查看该模块的相关信息。
+在本章的例程文件中，提供了一个hello_world.ko的内核模块。我们可以使
+用命令modinfo，来查看该模块的相关信息。
+
+.. image:: media/module002.jpg
+   :align: center
+   :alt: 未找到图片02|
 
-|module002|
 
-图 56‑1 hello_world模块信息
 
-我们从打印的输出信息中，可以得到该模块的相关说明，如该模块遵循的是GPL协议，该模块的作者是embedfire，该模块的vermagic等等。出于对安全的考虑，Linux内核会对加载的内核模块进行严格的版本检查，在加载模块时，模块加载器会比较所保存的内核vermagic与此模块的vermagic信息
+我们从打印的输出信息中，可以得到该模块的相关说明，如该模块遵循
+的是GPL协议，该模块的作者是embedfire，该模块的vermagic等等。出于对安
+全的考虑，Linux内核会对加载的内核模块进行严格的版本检查，在加载模块时，模块加
+载器会比较所保存的内核vermagic与此模块的vermagic信息
 是否一致，只有两者完全一致时，模块才能被成功加载，即便小版本号不一致也会导致加载失败。
 
 内核模块程序结构
@@ -74,253 +88,230 @@ modprobe 同样用于加载内核模块，与insmod不同，modprobe会根据dep
 
 本章将围绕上述的六个部分的内容，一步一步带大家写一个helloworld的内核模块。
 
-代码清单 56‑1 内核模块的基本框架（伪代码）
-
-1 头文件
-
-2
-
-3 内核模块参数
-
-4
-
-5 内核模块加载/卸载函数
-
-6
+.. code-block:: c
+   :caption: 内核模块的基本框架（伪代码）
+   :linenos:
 
-7 内核模块许可证
-
-8
-
-9 内核模块导出符号
-
-10
-
-11内核模块的其他信息
+   头文件
+   内核模块参数
+   内核模块加载/卸载函数
+   内核模块许可证
+   内核模块导出符号
+   
+   内核模块的其他信息
 
 头文件
-^^^
-
-前面我们已经接触过了Linux的应用编程，了解到Linux的头文件都存放在/usr/include中。编写内核模块所需要的头文件，并不在上述说到的目录，而是在Linux内核源码（资料位置——待补充）中的include文件夹。
-
-|module003|
-
-图 56‑2 头文件存放位置
-
-编写内核模块中经常要使用到的头文件有以下两个：<linux/init.h>和<linux/module.h>。我们可以看到在头文件前面也带有一个文件夹的名字linux，对应了include下的linux文件夹，我们到该文件夹下，查看这两个头文件都有什么内容。
-
-代码清单 56‑2 init.h文件（位于内核源码 /include/linux）
-
-1 /\* These are for everybody (although not all archs will actually
-
-2 discard it in modules) \*/
-
-3 #define \__init \__section(.init.text) \__cold notrace
-
-4 #define \__initdata \__section(.init.data)
-
-5 #define \__initconst \__constsection(.init.rodata)
-
-6 #define \__exitdata \__section(.exit.data)
-
-7 #define \__exit_call \__used \__section(.exitcall.exit)
-
-8 /*\*
-
-9 \* module_init() - driver initialization entry point
-
-10 \* @x: function to be run at kernel boot time or module insertion
-
-11 \*
-
-12 \* module_init() will either be called during do_initcalls() (if
-
-13 \* builtin) or at module insertion time (if a module).
-There can only
-
-14 \* be one per module.
-
-15 \*/
-
-16 #define module_init(x) \__initcall(x);
-
-17
-
-18 /*\*
-
-19 \* module_exit() - driver exit entry point
-
-20 \* @x: function to be run when driver is removed
-
-21 \*
-
-22 \* module_exit() will wrap the driver clean-up code
-
-23 \* with cleanup_module() when used with rmmod when
-
-24 \* the driver is a module.
-If the driver is statically
-
-25 \* compiled into the kernel, module_exit() has no effect.
-
-26 \* There can only be one per module.
-
-27 \*/
+^^^^^^
 
-28 #define module_exit(x) \__exitcall(x);
+前面我们已经接触过了Linux的应用编程，了解到Linux的头文件都
+存放在/usr/include中。编写内核模块所需要的头文件，并不在上述说到的
+目录，而是在Linux内核源码（资料位置——待补充）中的include文件夹。
+
+.. image:: media/module003.jpg
+   :align: center
+   :alt: 未找到图片03|
+
+
+
+编写内核模块中经常要使用到的头文件有以下两个：<linux/init.h>和<linux/module.h>。我们可
+以看到在头文件前面也带有一个文件夹的名字linux，对应了include下的linux文件夹，我们到
+该文件夹下，查看这两个头文件都有什么内容。
+
+.. code-block:: c
+   :caption: init.h文件（位于内核源码 /include/linux）
+   :linenos:
+
+   /* These are for everybody (although not all archs will actually
+   discard it in modules) */
+   #define __init __section(.init.text) __cold notrace
+   #define __initdata __section(.init.data)
+   #define __initconst __constsection(.init.rodata)
+   #define __exitdata __section(.exit.data)
+   #define __exit_call __used __section(.exitcall.exit)
+   /**
+   * module_init() - driver initialization entry point
+    * @x: function to be run at kernel boot time or module insertion
+    *
+    * module_init() will either be called during do_initcalls() (if
+    * builtin) or at module insertion time (if a module).
+    There can only
+    * be one per module.
+    */
+    #define module_init(x) __initcall(x);
+   
+    /**
+    * module_exit() - driver exit entry point
+    * @x: function to be run when driver is removed
+    *
+    * module_exit() will wrap the driver clean-up code
+    * with cleanup_module() when used with rmmod when
+    * the driver is a module.
+    the driver is statically
+    * compiled into the kernel, module_exit() has no effect.
+    * There can only be one per module.
+    */
+    #define module_exit(x) __exitcall(x);
 
 Init.h头文件主要包含了内核模块的加载、卸载函数的声明，还有一些宏定义，因此，只要我们涉及内核模块的编程，就需要加上该头文件。
 
-代码清单 56‑3 module.h（位于内核源码/include/linux）
-
-1 /\* Generic info of form tag = "info" \*/
-
-2 #define MODULE_INFO(tag, info) \__MODULE_INFO(tag, tag, info)
-
-3
-
-4 /\* For userspace: you can also call me...
-\*/
-
-5 #define MODULE_ALIAS(_alias) MODULE_INFO(alias, \_alias)
-
-6
-
-7 #define MODULE_LICENSE(_license) MODULE_INFO(license, \_license)
-
-8
-
-9 /\*
-
-10 \* Author(s), use "Name <email>" or just "Name", for multiple
-
-11 \* authors use multiple MODULE_AUTHOR() statements/lines.
-
-12 \*/
-
-13 #define MODULE_AUTHOR(_author) MODULE_INFO(author, \_author)
-
-代码清单 56‑3中，列举了module.h文件中的部分宏定义，这部分宏定义，有的是可有可无的，但是MODULE_LICENSE这个是指定该内核模块的许可证，是必须要有的。
+.. code-block:: c
+   :caption: module.h（位于内核源码/include/linux）
+   :linenos:
+
+   /* Generic info of form tag = "info" */
+   #define MODULE_INFO(tag, info) __MODULE_INFO(tag, tag, info)
+   /* For userspace: you can also call me...
+   */
+   #define MODULE_ALIAS(_alias) MODULE_INFO(alias, _alias)
+   #define MODULE_LICENSE(_license) MODULE_INFO(license, _license)
+   /*
+    * Author(s), use "Name <email>" or just "Name", for multiple
+    * authors use multiple MODULE_AUTHOR() statements/lines.
+    */
+    #define MODULE_AUTHOR(_author) MODULE_INFO(author, _author)
+
+以上代码中，列举了module.h文件中的部分宏定义，这部分宏定义，有的是可有可无
+的，但是MODULE_LICENSE这个是指定该内核模块的许可证，是必须要有的。
 
 加载和卸载内核
-^^^^^^^
+^^^^^^^^^^^^^^
 
 内核模块加载函数
 ''''''''
 
-回忆我们学过的STM32，假设我们要使用串口，是不是有一个BSP_USART_INIT函数，在这个函数里面，我们初始化了串口的GPIO，配置了串口的相关参，如波特率，数据位，停止位等等参数。func_init函数通常也是负责这部分内容的。
-
-代码清单 56‑4 内核模块卸载函数
-
-1 static int \__init func_init(void)
-
-2 {
+回忆我们学过的STM32，假设我们要使用串口，是不是有一个BSP_USART_INIT函数，在这个函
+数里面，我们初始化了串口的GPIO，配置了串口的相关参，如波特率，数据位，停止位
+等等参数。func_init函数通常也是负责这部分内容的。
 
-3 }
+.. code-block:: c
+   :caption: 内核模块卸载函数
+   :linenos:
 
-4 module_init(func_init);
+   static int __init func_init(void)
+   {
+   }
+   module_init(func_init);
 
-我们可以看到func_init函数类型为int，该函数返回0，表示模块初始化成功，并会在/sys/module下新建一个以模块名为名的目录，如图 56‑3中的红框处；返回非0值，表示模块初始化失败。
+我们可以看到func_init函数类型为int，该函数返回0，表示模块初始化成功，并会在/sys/module下新
+建一个以模块名为名的目录，如下图中的红框处；返回非0值，表示模块初始化失败。
 
-|module004|
+.. image:: media/module004.jpg
+   :align: center
+   :alt: 未找到图片04|
 
-图 56‑3 sys目录下module文件夹
 
-在C语言中，static关键字的作用如下：1、static修饰的静态局部变量直到程序运行结束以后才释放，延长了局部变量的生命周期；2、static的修饰全局变量只能在本文件中访问，不能在其它文件中访问；3、static修饰的函数只能在本文件中调用，不能被其他文件调用。内核模块的代码，实际上是内核代码
-的一部分，假如内核模块定义的函数和内核源代码中的某个函数重复了，编译器就会报错，导致编译失败，因此我们给内核模块的代码加上static修饰符的话，那么就可以避免这种错误。
+在C语言中，static关键字的作用如下：1、static修饰的静态局部变量直到程
+序运行结束以后才释放，延长了局部变量的生命周期；2、static的修饰全局变量只
+能在本文件中访问，不能在其它文件中访问；3、static修饰的函数只能在本文件中
+调用，不能被其他文件调用。内核模块的代码，实际上是内核代码
+的一部分，假如内核模块定义的函数和内核源代码中的某个函数重复了，编译器就会
+报错，导致编译失败，因此我们给内核模块的代码加上static修饰符的话，那么就可以避免这种错误。
 
-代码清单 56‑5 \__init、__initdata宏定义（位于内核源码/linux/init.h）
+.. code-block:: c
+   :caption: __init、__initdata宏定义（位于内核源码/linux/init.h）
+   :linenos:
 
-1 #define \__init \__section(.init.text) \__cold notrace
+   #define __init __section(.init.text) __cold notrace
+   #define __initdata __section(.init.data)
 
-2 #define \__initdata \__section(.init.data)
+Linux内核的栈资源十分有限，可能只有一个4096字节大小的页，我们编写的函数与Linux内核
+共享同一个栈资源。可想而知，如果在我们的模块程序中定义了一个大的局部数组变量，那么有
+可能大致导致堆栈溢出，因此，如果需要很大的空间的变量，应该使用动态分配。
 
-Linux内核的栈资源十分有限，可能只有一个4096字节大小的页，我们编写的函数与Linux内核共享同一个栈资源。可想而知，如果在我们的模块程序中定义了一个大的局部数组变量，那么有可能大致导致堆栈溢出，因此，如果需要很大的空间的变量，应该使用动态分配。
+以上代码 __init、__initdata宏定义（位于内核源码/linux/init.h）中的__init用于修
+饰函数，__initdata用于修饰变量。带有__init的修饰符，表示将该函数放到可执行文件的__init节
+区中，该节区的内容只能用于模块的初始化阶段，初始化阶段执行完毕之
+后，这部分的内容就会被释放掉，真可谓是"针尖也要削点铁"。
 
-代码清单 56‑5 \__init、__initdata宏定义（位于内核源码/linux/init.h）中的__init用于修饰函数，__initdata用于修饰变量。带有__init的修饰符，表示将该函数放到可执行文件的__init节区中，该节区的内容只能用于模块的初始化阶段，初始化阶段执行完毕之
-后，这部分的内容就会被释放掉，真可谓是“针尖也要削点铁”。
+.. code-block:: c
+   :caption: module_init宏定义
+   :linenos:
 
-代码清单 56‑6 module_init宏定义
+   #define module_init(x) __initcall(x);
 
-1 #define module_init(x) \__initcall(x);
-
-宏定义module_init用于通知内核初始化模块的时候，要使用哪个函数进行初始化。它会将函数地址加入到相应的节区section中，这样的话，开机的时候就可以自动加载模块了。
+宏定义module_init用于通知内核初始化模块的时候，要使用哪个函数进行初
+始化。它会将函数地址加入到相应的节区section中，这样的话，开机的时候就可以自动加载模块了。
 
 内核模块卸载函数
 ''''''''
 
-理解了模块加载的内容之后，来学习模块卸载函数应该会比较简单。与内核加载函数相反，内核模块卸载函数func_exit主要是用于释放初始化阶段分配的内存，分配的设备号等，是初始化过程的逆过程。
-
-代码清单 56‑7 内核模块卸载函数
-
-1 static void \__exit func_exit(void)
-
-2 {
+理解了模块加载的内容之后，来学习模块卸载函数应该会比较简单。与内核加载
+函数相反，内核模块卸载函数func_exit主要是用于释放初始化阶段分配的内存，分配的设
+备号等，是初始化过程的逆过程。
 
-3 }
+.. code-block:: c
+   :caption: 内核模块卸载函数
+   :linenos:
 
-4 module_exit(func_exit);
+   static void __exit func_exit(void)
+   {
+   }
+   module_exit(func_exit);
 
-与函数func_init区别在于，该函数的返回值是void类型，且修饰符也不一样，这里使用的使用__exit，表示将该函数放在可执行文件的__exit节区，当执行完模块卸载阶段之后，就会自动释放该区域的空间。
+与函数func_init区别在于，该函数的返回值是void类型，且修饰符也不一样，这里
+使用的使用__exit，表示将该函数放在可执行文件的__exit节区，当执行完模块卸载阶
+段之后，就会自动释放该区域的空间。
 
-代码清单 56‑8 \__exit、__exitdata宏定义
+.. code-block:: c
+   :caption: __exit、__exitdata宏定义
+   :linenos:
 
-1 #define \__exit \__section(.exit.text) \__exitused \__cold notrace
+   #define __exit __section(.exit.text) __exitused __cold notrace
+   #define __exitdata __section(.exit.data)
 
-2 #define \__exitdata \__section(.exit.data)
-
-类比于模块加载函数，__exit用于修饰函数，__exitdata用于修饰变量。宏定义module_exit用于告诉内核，当卸载模块时，需要调用哪个函数。
+类比于模块加载函数，__exit用于修饰函数，__exitdata用于修饰变量。宏定义module_exit用于
+告诉内核，当卸载模块时，需要调用哪个函数。
 
 内核模块参数
 ^^^^^^
 
-我们调试代码时，偶尔会需要串口来输出一些调试信息，方便我们找到问题的所在。但在正常运行的时候，我们是不需要串口输出信息的。为此，我们使用一个宏定义，来控制串口调试信息的输出，见代码清单 56‑9。
-
-代码清单 56‑9 示例程序
-
-1 #define GTP_DEBUG_ON 1
-
-2 #define GTP_DEBUG_ARRAY_ON 1
-
-3 #define GTP_DEBUG_FUNC_ON 0
-
-4 // Log define
-
-5 #define GTP_INFO(fmt,arg...) printf("<<-GTP-INFO->> "fmt"\n",##arg)
-
-6 #define GTP_ERROR(fmt,arg...) printf("<<-GTP-ERROR->> "fmt"\n",##arg)
-
-7 #define GTP_DEBUG(fmt,arg...) do{\\
-
-8 if(GTP_DEBUG_ON)\\
-
-9 printf("<<-GTP-DEBUG->> [%d]"fmt"\n",__LINE__, ##arg);\\
-
-10 }while(0)
+我们调试代码时，偶尔会需要串口来输出一些调试信息，方便我们找到问题的所在。但在正常运
+行的时候，我们是不需要串口输出信息的。为此，我们使用一个宏定义，来控制串口调试信
+息的输出，如下所示。
+
+.. code-block:: c
+   :caption: 示例程序
+   :linenos:
+
+   #define GTP_DEBUG_ON 1
+   #define GTP_DEBUG_ARRAY_ON 1
+   #define GTP_DEBUG_FUNC_ON 0
+   // Log define
+   #define GTP_INFO(fmt,arg...) printf("<<-GTP-INFO->> "fmt"\n",##arg)
+   #define GTP_ERROR(fmt,arg...) printf("<<-GTP-ERROR->> "fmt"\n",##arg)
+   #define GTP_DEBUG(fmt,arg...) do{\\
+   if(GTP_DEBUG_ON)\\
+   printf("<<-GTP-DEBUG->> [%d]"fmt"\n",__LINE__, ##arg);\\
+    }while(0)
 
 在调试内核模块的时候，我们可以使用module_param函数来定义一个变量，控制调试信息的输出。
 
-代码清单 56‑10 内核模块参数宏定义（位于内核源码/linux/moduleparam.h）
-
-1 #define module_param(name, type, perm) \\
+.. code-block:: c
+   :caption: 内核模块参数宏定义（位于内核源码/linux/moduleparam.h）
+   :linenos:
 
-2 module_param_named(name, name, type, perm)
+   #define module_param(name, type, perm) \\
+   module_param_named(name, name, type, perm)
+   #define module_param_array(name, type, nump, perm) \\
+   module_param_array_named(name, name, type, nump, perm)
 
-3 #define module_param_array(name, type, nump, perm) \\
+以上代码中的module_param函数需要传入三个参数：参数name——我们定义的变量名；参数type——参数
+的类型，目前内核支持的参数类型有byte，short， ushort，
+int，uint，long，ulong，charp，bool，invbool。其中charp表示的是字符指针，bool是布尔
+类型，其值只能为0或者是1；invbool是反布尔类型，其值也是只能取0或者是1，但是true值表示0，false表示1。
 
-4 module_param_array_named(name, name, type, nump, perm)
+.. image:: media/module005.jpg
+   :align: center
+   :alt: 未找到图片05|
 
-代码清单 56‑10中的module_param函数需要传入三个参数：参数name——我们定义的变量名；参数type——参数的类型，目前内核支持的参数类型有byte，short， ushort，
-int，uint，long，ulong，charp，bool，invbool。其中charp表示的是字符指针，bool是布尔类型，其值只能为0或者是1；invbool是反布尔类型，其值也是只能取0或者是1，但是true值表示0，false表示1。
 
-|module005|
 
-图 56‑4 模块参数对应的文件
+如果我们定义了一个模块参数，则会在/sys/module/模块名/ parameters下会存在以模块
+参数为名的文件，上图中的debug_on是本章实验编写的内核模块hello_world中定义
+的模块参数，加载内核模块，可以通过"insmod
+debug_on=1"来输出调试信息。参数perm表示的是该文件的权限，具体参数值见下表。
 
-如果我们定义了一个模块参数，则会在/sys/module/模块名/ parameters下会存在以模块参数为名的文件，图 56‑4中的debug_on是本章实验编写的内核模块hello_world中定义的模块参数，加载内核模块，可以通过“insmod
-debug_on=1”来输出调试信息。参数perm表示的是该文件的权限，具体参数值见表格 56‑2。
-
-表格 56‑2 文件权限
+表  文件权限
 
 ======== ======= ==============================
 标志位   含义
@@ -331,239 +322,246 @@ debug_on=1”来输出调试信息。参数perm表示的是该文件的权限，
 
 用户组           \        S_IWGRP 当前用户组的其他用户拥有写权限 其他用户 S_IROTH 其他用户拥有读权限 \        S_IWOTH 其他用户拥有写权限 ======== ======= ==============================
 
-上述文件权限唯独没有关于可执行权限的设置，请注意，该文件不允许该文件具有可执行权限，如开发板使用的内核版本为4.1.15，设置该权限参数值为S_IXUGO，加载内核模块时会提示错误，见图 56‑5。
+上述文件权限唯独没有关于可执行权限的设置，请注意，该文件不允许
+该文件具有可执行权限，如开发板使用的内核版本为4.1.15，设置该权限参
+数值为S_IXUGO，加载内核模块时会提示错误，见下图。
 
-|module006|
+.. image:: media/module006.jpg
+   :align: center
+   :alt: 未找到图片06|
 
-图 56‑5 错误提示
 
 内核模块导出符号
 ^^^^^^^^
 
-内核模块导出符号，符号是什么东西？实际上，符号指的就是函数和变量。当模块被装入内核后，它所导出的符号都会记录在内核符号表中。在使用命令insmod加载模块后，模块就被连接到了内核，因此可以访问内核的共用符号。
-
-代码清单 56‑11 导出符号
-
-1 #define EXPORT_SYMBOL(sym) \\
-
-2 \__EXPORT_SYMBOL(sym, "")
+内核模块导出符号，符号是什么东西？实际上，符号指的就是函数和变量。当模
+块被装入内核后，它所导出的符号都会记录在内核符号表中。在使用命令insmod加
+载模块后，模块就被连接到了内核，因此可以访问内核的共用符号。
 
-EXPORT_SYMBOL宏用于向内核导出符号，这样的话，其他模块也可以使用我们导出的符号了。下面通过一段代码，介绍如何使用某个模块导出符号。
+.. code-block:: c
+   :caption: 导出符号
+   :linenos:
 
-代码清单 56‑12 file1.c
+   #define EXPORT_SYMBOL(sym) \\
+   __EXPORT_SYMBOL(sym, "")
 
-1 ...省略代码...
+EXPORT_SYMBOL宏用于向内核导出符号，这样的话，其他模块也可以使用我们导
+出的符号了。下面通过一段代码，介绍如何使用某个模块导出符号。
 
-2 void func(void)
+.. code-block:: c
+   :caption: file1.c
+   :linenos:
 
-3 {
+   ...省略代码...
+   void func(void)
+   {
+   }
+   EXPORT_SYMBOL(func);
+   ...省略代码...
 
-4
+我们file1中定义了一个func函数，并通过EXPORT_SYMBOL宏将该函数导出。以上代码中，省略了内
+核模块程序的其他内容，如头文件，加载/卸载函数等。
 
-5 }
+.. code-block:: c
+   :caption: file2.c
+   :linenos:
 
-6 EXPORT_SYMBOL(func);
+   ...省略代码...
+   extern void func1(void);
+   void func2(void)
+   {
+   func1();
+   }
+   ...省略代码...
 
-7 ...省略代码...
-
-我们file1中定义了一个func函数，并通过EXPORT_SYMBOL宏将该函数导出。代码清单 56‑12中，省略了内核模块程序的其他内容，如头文件，加载/卸载函数等。
-
-代码清单 56‑13 file2.c
-
-1 ...省略代码...
-
-2 extern void func1(void);
-
-3 void func2(void)
-
-4 {
-
-5 func1();
-
-6 }
-
-7 ...省略代码...
-
-file2.c中使用extern关键字声明函数func1，这样我们就可以使用file1.c文件中的func1了。
+file2.c中使用extern关键字声明函数func1，这样我们就
+可以使用file1.c文件中的func1了。
 
 内核模块许可证
 ^^^^^^^
 
-Linux是一款免费的操作系统，采用了GPL协议，允许用户可以任意修改其源代码。GPL协议的主要内容是软件产品中即使使用了某个GPL协议产品提供的库，衍生出一个新产品，该软件产品都必须采用GPL协议，即必须是开源和免费使用的，可见GPL协议具有传染性。因此，我们可以在Linux使用各种各样的免费软件
-。在以后学习Linux的过程中，可能会发现我们安装任何一款软件，从来没有30天试用期或者是要求输入激活码的。
+Linux是一款免费的操作系统，采用了GPL协议，允许用户可以任意修改其源
+代码。GPL协议的主要内容是软件产品中即使使用了某个GPL协议产品提供的
+库，衍生出一个新产品，该软件产品都必须采用GPL协议，即必须是开源和免费使
+用的，可见GPL协议具有传染性。因此，我们可以在Linux使用各种各样的免费软件
+。在以后学习Linux的过程中，可能会发现我们安装任何一款软件，从来没有30天试
+用期或者是要求输入激活码的。
+
+在Linux内核版本2.4.10之后，模块必须通过MODULE_LICENSE宏声明此模块的许
+可证，否则在加载此模块时，会提示内核被污染，见下图。
 
-在Linux内核版本2.4.10之后，模块必须通过MODULE_LICENSE宏声明此模块的许可证，否则在加载此模块时，会提示内核被污染，见图 56‑6。
+.. code-block:: c
+   :caption: 许可证
+   :linenos:
 
-代码清单 56‑14 许可证
+   #define MODULE_LICENSE(_license) MODULE_INFO(license, _license)
 
-1 #define MODULE_LICENSE(_license) MODULE_INFO(license, \_license)
+.. image:: media/module007.jpg
+   :align: center
+   :alt: 未找到图片07|
 
-|module007|
 
-图 56‑6 内核被污染
 
-内核模块许可证有 “GPL”，“GPL v2”，“GPL and additional rights”，“Dual SD/GPL”，“Dual MPL/GPL”，“Proprietary”。
+内核模块许可证有 "GPL"，"GPL v2"，"GPL and additional rights"，"Dual SD/GPL"，"Dual MPL/GPL"，"Proprietary"。
 
 内核模块的其他信息
 ^^^^^^^^^
 
-下面，我们介绍一下关于内核模块程序结构的最后一部分内容。这部分内容只是为了给使用该模块的读者一本“说明书”，属于可有可无的部分，有则锦上添花，无则也无伤大雅。
+下面，我们介绍一下关于内核模块程序结构的最后一部分内容。这部分内容只
+是为了给使用该模块的读者一本"说明书"，属于可有可无的部分，有则锦上添花，无则也无伤大雅。
 
 作者
 ''
 
-代码清单 56‑15 内核模块作者宏定义（位于内核源码/linux/module.h）
+.. code-block:: c
+   :caption: 内核模块作者宏定义（位于内核源码/linux/module.h）
+   :linenos:
 
-1 #define MODULE_AUTHOR(_author) MODULE_INFO(author, \_author)
+   #define MODULE_AUTHOR(_author) MODULE_INFO(author, _author)
 
-我们前面使用modinfo中打印出的模块信息中“author”信息便是来自于宏定义MODULE_AUTHOR。该宏定义用于声明该模块的作者。
+我们前面使用modinfo中打印出的模块信息中"author"信息便是来自于
+宏定义MODULE_AUTHOR。该宏定义用于声明该模块的作者。
 
 模块描述信息
 ^^^^^^
 
-代码清单 56‑16模块描述信息（位于内核源码/linux/module.h）
+.. code-block:: c
+   :caption: 模块描述信息（位于内核源码/linux/module.h）
+   :linenos:
 
-1 #define MODULE_DESCRIPTION(_description) MODULE_INFO(description, \_description)
+   #define MODULE_DESCRIPTION(_description) MODULE_INFO(description, _description)
 
-模块信息中“description”信息则来自宏MODULE_DESCRIPTION，该宏用于描述该模块的功能作用。
+模块信息中"description"信息则来自宏MODULE_DESCRIPTION，该宏用于描述该模块的功能作用。
 
 模块别名
 ''''
 
-代码清单 56‑17 内核模块别名宏定义（位于内核源码/linux/module.h）
+.. code-block:: c
+   :caption: 内核模块别名宏定义（位于内核源码/linux/module.h）
+   :linenos:
 
-1 #define MODULE_ALIAS(_alias) MODULE_INFO(alias, \_alias)
+   #define MODULE_ALIAS(_alias) MODULE_INFO(alias, _alias)
 
-模块信息中“alias”信息来自于宏定义MODULE_ALIAS。该宏定义用于给内核模块起别名。注意，在使用该模块的别名时，需要将该模块复制到/lib/modules/内核源码/下，使用命令depmod更新模块的依赖关系，否则的话，Linux内核怎么知道这个模块还有另一个名字。
+模块信息中"alias"信息来自于宏定义MODULE_ALIAS。该宏定义用于给内核
+模块起别名。注意，在使用该模块的别名时，需要将该模块复制到/lib/modules/内核
+源码/下，使用命令depmod更新模块的依赖关系，否则的话，Linux内核怎么知道这个模块还有另一个名字。
 
 在开发主机上编译内核模块
 ~~~~~~~~~~~~
 
 结合我们56.3 节的内容，我们便可以写出一个简单的内核模块程序。
 
+**本章的示例代码目录为：base_code/linux_driver/hello_world/hello_world.c**
+
 源码分析
 ^^^^
 
-代码清单 56‑18 hello_world.c文件
-
-1 #include <linux/init.h>
-
-2 #include <linux/module.h>
-
-3
-
-4 //默认不输出调试信息
-
-5 //权限有限制
-
-6 bool debug_on = 0;
-
-7 module_param(debug_on, bool, S_IRWXU);
-
-8
-
-9
-
-10
-
-11 static int \__init hello_init(void)
-
-12 {
-
-13 if (debug)
-
-14 printk("[ DEBUG ] debug info output\n");
-
-15 printk("Hello World Module Init\n");
-
-16 return 0;
-
-17 }
-
-18 module_init(hello_init);
-
-19
-
-20
-
-21 static void \__exit hello_exit(void)
-
-22 {
-
-23 printk("Hello World Module Exit\n");
-
-24 }
-
-25 module_exit(hello_exit);
-
-26
-
-27
-
-28 MODULE_LICENSE("GPL");
-
-29 MODULE_AUTHOR("embedfire");
-
-30 MODULE_DESCRIPTION("hello world module");
-
-31 MODULE_ALIAS("test_module");
-
-代码清单 56‑18包含了头文件<linux/init.h>和<linux/module.h>，这两个头文件是写内核模块必须要包含的。这里是我们定义了一个布尔类型的模块参数debug_on，用来打开debug消息的输出。
-
-模块初始化函数hello_init调用了printk函数，在内核模块运行的过程中，他不能依赖于C库函数，因此用不了printf函数，需要使用单独的打印输出函数printk。该函数的用户与printf函数类似。完成模块初始化函数之后，还需要调用宏module_init来告诉内核，使用hello_ini
-t函数来进行初始化。模块卸载函数也用printk函数打印字符串，并用宏module_exit在内核注册该模块的卸载函数。
+.. code-block:: c
+   :caption: ../base_code/linux_driver/hello_world/hello_world.c文件
+   :linenos:
+
+   #include <linux/init.h>
+   #include <linux/module.h>
+   //默认不输出调试信息
+   //权限有限制
+   bool debug_on = 0;
+   module_param(debug_on, bool, S_IRUSR);
+   
+    static int __init hello_init(void)
+    {
+    if (debug_on)
+    printk("[ DEBUG ] debug info output\n");
+    printk("Hello World Module Init\n");
+    return 0;
+    }
+    module_init(hello_init);
+   
+   
+    static void __exit hello_exit(void)
+    {
+    printk("Hello World Module Exit\n");
+    }
+    module_exit(hello_exit);
+   
+   
+    MODULE_LICENSE("GPL");
+    MODULE_AUTHOR("embedfire");
+    MODULE_DESCRIPTION("hello world module");
+    MODULE_ALIAS("test_module");
+
+以上代码中包含了头文件<linux/init.h>和<linux/module.h>，这两个头文件是写内核模块必须要
+包含的。这里是我们定义了一个布尔类型的模块参数debug_on，用来打开debug消息的输出。
+
+模块初始化函数hello_init调用了printk函数，在内核模块运行的过程中，他不能依赖于C库函
+数，因此用不了printf函数，需要使用单独的打印输出函数printk。该函数的用户与printf函数类
+似。完成模块初始化函数之后，还需要调用宏module_init来告诉内核，使用hello_ini
+t函数来进行初始化。模块卸载函数也用printk函数打印字符串，并用宏module_exit在内核
+注册该模块的卸载函数。
 
 最后，必须声明该模块使用遵循的许可证，这里我们设置为GPL协议。
 
 Makefile分析
 ^^^^^^^^^^
 
-对于内核模块而言，它是属于内核的一段代码，只不过它并不在内核源码中。为此，我们在编译时需要到内核源码目录下，进行编译。编译内核模块使用的Makefile文件，和我们前面编译C代码使用的Makefile大相径庭，这得益于编译Linux内核所采用的Kbuild系统。
-
-代码清单 56‑19 Makefile
+对于内核模块而言，它是属于内核的一段代码，只不过它并不在内核源码中。为此，我们在编译时需
+要到内核源码目录下，进行编译。编译内核模块使用的Makefile文件，和我们前面编译C代码使
+用的Makefile大相径庭，这得益于编译Linux内核所采用的Kbuild系统，因此在编译内核模块时，我们需要指定环境变量ARCH和CROSS_COMPILE的值。
 
-1 KERNEL_DIR=/home/embedfire/module/linux-imx
+.. code-block:: makefile
+   :caption: ../base_code/linux_driver/hello_world/Makefile
+   :linenos:
+   
+   KERNEL_DIR=/home/embedfire/module/linux-imx
+   obj-m := hello_world.o
+   all:
+   $(MAKE) -C $(KERNEL_DIR) M=$(CURDIR) modules
+   clean:
+   $(MAKE) -C $(KERNEL_DIR) M=$(CURDIR) clean
 
-2 obj-m := hello_world.o
+以上代码中提供了一个关于编译内核模块的Makefile。该Makefile定义了
+变量KERNEL_DIR，来保存内核源码的目录。变量obj-m保存着需要编译成模块的目标文件名。 "$(MAKE)
+modules"实际上是执行Linux顶层Makefile的伪目标modules。通过选项"-C"，可以让make工具跳
+转到源码目录下读取顶层Makefile。M=$(CURDIR)
+表明然后返回到当前目录，读取并执行当前目录的Makefile，开始编译内核模块。CURDIR是make的
+内嵌变量，自动设置为当前目录。
 
-3 all:
+执行"make ARCH=arm CROSS_COMPILE=arm-linux-gnueabihf-"命令，可以看到下图的输出信息，最后
+生成内核模块hello_world.ko。
 
-4 $(MAKE) -C $(KERNEL_DIR) M=$(CURDIR) modules
+.. image:: media/module008.jpg
+   :align: center
+   :alt: 未找到图片08|
 
-5 clean:
 
-6 $(MAKE) -C $(KERNEL_DIR) M=$(CURDIR) clean
 
-7
+.. image:: media/module009.jpg
+   :align: center
+   :alt: 未找到图片09|
 
-代码清单 56‑19中提供了一个关于编译内核模块的Makefile。该Makefile定义了变量KERNEL_DIR，来保存内核源码的目录。变量obj-m保存着需要编译成模块的目标文件名。 “$(MAKE)
-modules”实际上是执行Linux顶层Makefile的伪目标modules。通过选项“-C”，可以让make工具跳转到源码目录下读取顶层Makefile。M=$(CURDIR)
-表明然后返回到当前目录，读取并执行当前目录的Makefile，开始编译内核模块。CURDIR是make的内嵌变量，自动设置为当前目录。
 
-执行“make ARCH=arm CROSS_COMPILE=arm-linux-gnueabihf-”命令，可以看到图 56‑7的输出信息，最后生成内核模块hello_world.ko。
 
-|module008|
+实验结果
+^^^^
 
-图 56‑7 make过程
+将生成的内核模块拷贝至开发板执行命令"insmod hello_world.ko"，可以看到终
+端会输出字符串"Hello World Module Init"，执行命令"rmmod hello_world"，终端会输出
+字符串"Hello World Module Exit"。
 
-|module009|
+.. image:: media/module010.jpg
+   :align: center
+   :alt: 未找到图片10|
 
-图 56‑8 生成的内核模块
 
-实验结果
-^^^^
 
-将生成的内核模块拷贝至开发板执行命令“insmod hello_world.ko”，可以看到终端会输出字符串“Hello World Module Init”，执行命令“rmmod hello_world”，终端会输出字符串“Hello World Module Exit”。
+执行"insmod hello_world.ko debug_on=1"，可以看到终端会输出调试信息。s
 
-|module010|
+.. image:: media/module011.jpg
+   :align: center
+   :alt: 未找到图片11|
 
-图 56‑9 实验结果（不带debug信息）
 
-执行“insmod hello_world.ko debug_on=1”，可以看到终端会输出调试信息。
 
-|module011|
 
-图 56‑10 实验结果（带debug信息）
 
 .. |module002| image:: media/module002.jpg
    :width: 5.24618in
diff --git a/documentation/linux_driver/platform_driver.rst b/documentation/linux_driver/platform_driver.rst
new file mode 100644
index 0000000000000000000000000000000000000000..7086052b620fb03392c15f414340b02a11b76a62
--- /dev/null
+++ b/documentation/linux_driver/platform_driver.rst
@@ -0,0 +1,1571 @@
+.. vim: syntax=rst
+
+
+
+平台设备驱动
+-----------------------
+
+
+在Linux设备模型章节中，我们了解到Linux中采用“总线——设备——驱动”的方式，来管理系统中的设备以及驱动。
+
+但是，在实际应用中，并不是所有的设备都能需要通过对应的物理总线进行通信，如LED灯，蜂鸣器，按键等设备。
+
+为了使这些设备也能够采用“总线——设备——驱动”方式进行管理，内核引入了一种虚拟的总线——平台总线（platform bus)，专门用于连接那些没有物理总线的设备，这些设备被称为平台设备，
+
+对应的设备驱动则被称为平台驱动。对于从事Linux驱动的开发工作者来说，平台设备极为重要。
+
+
+
+我们都知道，常见的物理总线有I2C、SPI、UART......在嵌入式开发中，我们经常使用的i2c、spi、uart，并不是真正的物理总线，
+
+它们都是集成在SOC上面的控制器，如i2c控制器，spi控制器等等，它们都可以通过CPU的总线直接寻址，也就是我们常说的操作寄存器。
+
+对于这些控制器而言，同样地，没有对应的物理总线可以进行连接，那么这些控制器也会以平台设备的身份注册到内核中去。尽管这样，
+
+但我们所注册的I2C设备、SPI设备最终还是会连接到I2C总线、SPI总线，并不会连接到平台总线。
+
+
+
+平台设备驱动是在Linux设备模型的基础上，对device和device_driver结构体进一步封装，得到platform device和platform driver这两个结构体，
+
+分别对应平台设备以及平台驱动。驱动开发者，只需要利用这两个结构体以及内核提供的API，便可以依葫芦画瓢，编写出平台设备驱动了。
+
+
+
+
+
+前面，我们已经尝试过以字符设备的方式，来点亮板子上的LED灯。但是这个驱动还是有些不足之处，比如设备和驱动并没有分离，我们将设备的硬件信息统统都定义在了驱动代码中，
+
+这样的代码通用性差，一旦硬件有所变更，势必需要修改驱动代码。我们知道Linux中采用“总线——设备——驱动”的方式，能够有效地解决这个问题。对于没有物理总线连接的LED灯，可以使用虚构的平台总线进行连接。
+
+
+
+
+
+
+
+平台设备
+
+~~~~~~
+
+平台设备只需要尽可能地告诉驱动，自己需要什么资源，至于如何使用这些资源，那就是驱动的事情了。
+
+内核使用platform_device结构体来描述一个设备平台设备，如下所示：
+
+
+
+.. code-block:: c
+
+    :caption: platform_device结构体(内核源码/include/linux/platform_device.h)
+
+    :linenos:
+
+
+
+    struct platform_device {
+
+        const char	*name;
+
+        int		id;
+
+        struct device	dev;
+
+        u32		num_resources;
+
+        struct resource	*resource;
+
+
+
+        const struct platform_device_id	*id_entry;        
+
+    };
+
+
+
+- name：设备名称，总线进行匹配时，会比较设备和驱动的名称是否一致；
+
+- id：指定设备的编号，Linux支持同名的设备，而同名设备之间则是通过该编号进行区分；
+
+- dev：Linux设备模型中的device结构体，platform_device中嵌入了该结构体，方便内核管理平台设备；
+
+- num_resources：记录资源的个数，当结构体成员resource存放的是数组时，需要记录resource数组的个数，内核提供了宏定义ARRAY_SIZE用于计算数组的个数；
+
+- resource：平台设备提供给驱动的资源，如irq，dma，内存等等。该结构体会在接下来的内容进行讲解；
+
+- id_entry：平台总线提供的另一种匹配方式，原理依然是通过比较字符串，这部分内容会在平台总线小节中讲，这里的id_entry用于保存匹配的结果；
+
+
+
+对于不支持热插拔的设备而言，内核并不知道如何能够使该设备正常工作。为此，在平台设备结构体中，嵌入了一个结构体struct resource,
+
+用于保存设备所需要的资源，比如这个设备使用的中断编号，寄存器的内存地址等等，结构体原型如下：
+
+
+
+.. code-block:: c
+
+    :caption: resource结构体(内核源码/include/linux/ioport.h)
+
+    :linenos:
+
+
+
+    /*
+
+    * Resources are tree-like, allowing
+
+    * nesting etc..
+
+    */
+
+    struct resource {
+
+        resource_size_t start;
+
+        resource_size_t end;
+
+        const char *name;
+
+        unsigned long flags;
+
+    };
+
+
+
+- flags：用于指定该资源的类型，在Linux中，资源包括I/O、Memory、Register、IRQ、DMA、Bus等多种类型，最常见的有以下几种：
+
+
+
+.. code-block:: c
+
+    :caption: 资源宏定义(内核源码/include/linux/ioport.h)
+
+    :linenos:
+
+
+
+    #define IORESOURCE_IO		0x00000100	
+
+    #define IORESOURCE_MEM		0x00000200
+
+    #define IORESOURCE_IRQ		0x00000400
+
+    #define IORESOURCE_DMA		0x00000800
+
+
+
+设备驱动程序的主要目的是操作设备的寄存器。不同架构的计算机提供不同的操作接口，主要有IO端口映射和IO內存映射两种方式。
+
+IORESOURCE_IO指的是IO地址空间，对应于IO端口映射方式，只能通过专门的接口函数（如inb、outb）才能访问；IORESOURCE_MEM指的是属于外设的可直接寻址的地址空间，也就是我们常说的某个寄存器地址，
+
+采用IO内存映射的方式，可以像访问内存一样，去读写寄存器。在嵌入式中，基本上没有IO地址空间，所以通常使用IORESOURCE_MEM。
+
+IORESOURCE_IRQ可以指定该设备使用某个中断，而IORESOURCE_DMA则是用于指定使用的DMA通道。
+
+
+
+- name：指定资源的名字，可以设置为NULL；
+
+- start、end：指定资源的起始地址以及结束地址，对于IORESOURCE_IO或者是IORESOURCE_MEM，他们表示要使用的内存的起始位置以及结束位置；而对于IORESOURCE_IRQ、IORESOURCE_DMA，若是只用一个中断引脚或者是一个通道，则start和end成员的值必须是相等的。
+
+
+
+
+
+
+
+
+
+Linux虽然提供了很多种资源类型供我们选择，但是不一定能够囊括所有的数据，如某个GPIO的引脚号。尽管如此，我们依然有办法可以解决这个问题。我们说过“设备只需要尽可能多地提供相关信息，
+
+怎么样用是由驱动说了算的”，以上述问题为例，我们可以使用IORESOURCE_IRQ资源，把该引脚编号赋给start和end成员，驱动只需要调用对应的API，便可以得到我们的引脚号。这只是其中的一种方式，
+
+常见的方式是以下这种使用方式。我们注意到platform_device结构体中，有个device结构体类型的成员dev。上一章，我们提到过Linux设备模型使用device结构体来抽象物理设备，该结构体的成员platform_data可用于保存设备的私有数据，于是，
+
+我们便可以利用该成员做文章，这样的话，无论你想要提供的是什么内容，只需要把数据的地址赋值给platform_data即可，还是以GPIO引脚号为例，示例代码如下：
+
+
+
+
+
+.. code-block:: c
+
+    :caption: 示例代码
+
+    :linenos: 
+
+
+
+    unsigned int pin = 10;
+
+    struct platform_device pdev = {
+
+        .dev = {
+
+            .platform_data = &pin;
+
+
+
+        }
+
+
+
+    }
+
+
+
+将保存了GPIO引脚号的变量地址赋值给platform_data成员，这样，驱动调用特定的API，即可获取到我们的引脚号。
+
+
+
+当我们完成了上述结构体的初始化时，需要告诉内核，我们定义了一个平台设备。为此，需要使用下面的API，来注册平台设备。
+
+
+
+
+
+.. code-block:: c
+
+    :caption: platform_device_register函数(内核源码/drivers/base/platform.c)
+
+    :linenos:
+
+
+
+    int platform_device_register(struct platform_device *pdev)
+
+
+
+同样，当我们想要移除我们的平台设备时，我们需要使用platform_device_unregister函数，来通知内核去移除该设备。
+
+
+
+.. code-block:: c 
+
+    :caption: platform_device_unregister函数(内核源码/drivers/base/platform.c)
+
+    :linenos:
+
+
+
+    void platform_device_unregister(struct platform_device *pdev)
+
+
+
+到这里，平台设备的知识就全部讲解完毕了。虽然我们还没有学习平台驱动，但是我们大致上了解了平台设备驱动是如何实现硬件与软件分离的。
+
+首先他将硬件部分的代码与驱动部分的代码分开，然后在他们之间搭建了一座桥——统一的数据结构以及函数接口，
+
+两者间的数据交互直接在“这座桥”上进行，从而很好地实现了驱动和硬件相分离。
+
+
+
+平台驱动
+
+~~~~
+
+学完平台设备之后，在学平台驱动之前，想象一下，我们现在内核已经注册了一个平台设备，它提供了什么样的资源，
+
+我的驱动要如何提取这些资源，提取这些资源之后，又该如何使设备正常工作呢？这便是平台驱动的重点。
+
+内核中使用platform_driver结构体来描述平台驱动，结构体原型如下所示：
+
+
+
+.. code-block:: c
+
+    :caption: platform_driver结构体(内核源码/include/platform_device.h)
+
+    :linenos:
+
+
+
+    struct platform_driver {
+
+        int (*probe)(struct platform_device *);
+
+        int (*remove)(struct platform_device *);
+
+        struct device_driver driver;
+
+        const struct platform_device_id *id_table;
+
+    };
+
+
+
+- probe：函数指针类型，指向驱动的probe函数，当总线为设备和驱动匹配上之后，会执行驱动的probe函数。我们通常在该函数中，对设备进行一系列的初始化。
+
+- remove：函数指针类型，指向驱动的remove函数，当我们移除我们的平台设备时，会调用该函数，该函数实现的操作，通常是probe函数的逆过程。
+
+- driver：Linux设备模型中用于抽象驱动的device_driver结构体，platform_driver嵌入该结构体，方便内核管理平台驱动；
+
+- id_table：表示该驱动能够兼容的设备类型。
+
+
+
+.. code-block:: c
+
+    :caption: id_table结构体(内核源码/include/linux/mod_devicetable.h)
+
+    :linenos:
+
+
+
+    struct platform_device_id {
+
+        char name[PLATFORM_NAME_SIZE];
+
+        kernel_ulong_t driver_data;
+
+    };
+
+
+
+我们可以看到，platform_device_id中有两个成员，一个是数组，用于指定驱动的名称，总线进行匹配时，
+
+会依据该结构体的name成员进行对比。在platform_device中也存在该类型的变量id_entry，当平台设备与平台驱动匹配成功时，
+
+平台设备的id_entry会保存对应的条目。我们知道同系列的设备中，往往只是某些寄存器的配置发生了改变，为了减少代码的冗余，
+
+尽量做到一个驱动可以匹配多个设备的目的，在platform_device_id中提供了另一个成员变量driver_data，Linux用kernel_ulong_t类型来表示无符号长整形（unsigned long），
+
+使用该变量来保存设备的配置。以imx的串口为例，具体代码如下：
+
+
+
+.. code-block:: c
+
+    :caption: 示例代码(内核源码/drivers/tty/serial/imx.c)
+
+    :linenos:
+
+
+
+    static struct imx_uart_data imx_uart_devdata[] = {
+
+        [IMX1_UART] = {
+
+            .uts_reg = IMX1_UTS,
+
+            .devtype = IMX1_UART,
+
+        },
+
+        [IMX21_UART] = {
+
+            .uts_reg = IMX21_UTS,
+
+            .devtype = IMX21_UART,
+
+        },
+
+        [IMX6Q_UART] = {
+
+            .uts_reg = IMX21_UTS,
+
+            .devtype = IMX6Q_UART,
+
+        },
+
+    };
+
+
+
+    static struct platform_device_id imx_uart_devtype[] = {
+
+        {
+
+            .name = "imx1-uart",
+
+            .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX1_UART],
+
+        }, {
+
+            .name = "imx21-uart",
+
+            .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX21_UART],
+
+        }, {
+
+            .name = "imx6q-uart",
+
+            .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX6Q_UART],
+
+        }, {
+
+            /* sentinel */
+
+        }
+
+    };
+
+
+
+上述驱动代码中，支持三种设备的串口，分别是imx1、imx21、imx6q，他们之间区别在于串口的test寄存器地址。前面提到过，
+
+当总线成功配对平台驱动以及平台设备时，会将对应的id_table条目赋值给平台设备的id_entry成员，而平台驱动的probe函数是以平台设备为参数，
+
+这样的话，就可以拿到当前设备串口的test寄存器地址了。
+
+
+
+当我们初始化了平台驱动结构体之后，通过以下函数来注册我们的平台驱动，由于platform_driver中嵌入了driver结构体，结合Linux设备模型的知识，
+
+那么当我们成功注册了一个平台驱动时，就会在/sys/bus/platform/driver目录生成一个新的子目录。
+
+
+
+.. code-block:: c 
+
+    :caption: platform_driver_register函数
+
+    :linenos:
+
+
+
+    int platform_driver_register(struct platform_driver *drv);
+
+
+
+当我们移除我们的模块时，需要注销掉已注册的平台驱动，Linux提供以下函数，用于注销我们的平台驱动。
+
+
+
+.. code-block:: c 
+
+    :caption: platform_driver_unregister函数(内核源码/drivers/base/platform.c)
+
+    :linenos:
+
+
+
+    void platform_driver_unregister(struct platform_driver *drv);
+
+
+
+上面所讲的内容是最基本的平台驱动框架，只需要实现probe函数、remove函数，初始化platform_driver结构体，并调用platform_driver_register进行注册即可。
+
+这只是完成了本小节的一个重点，另一个重点便是如何获取平台设备提供的资源。在学习平台设备的时候，我们知道Linux使用结构体resource来抽象我们的资源，
+
+以及可以利用设备结构体device中的成员platform_data来保存私有数据。下面，先看一下，如何获取平台设备中结构体resource提供的资源。
+
+函数platform_get_resource通常会在驱动的probe函数中执行，用于获取平台设备提供的资源结构体，最终会返回一个struct resource类型的指针，
+
+函数原型如下：
+
+
+
+.. code-block:: c
+
+    :caption: platform_get_resource函数
+
+    :linenos:
+
+
+
+    struct resource *platform_get_resource(struct platform_device *dev, unsigned int type, unsigned int num);
+
+
+
+- dev：指定要获取哪个平台设备的资源；
+
+- type：指定获取资源的类型，如IORESOURCE_MEM、IORESOURCE_IO等；
+
+- num：指定要获取的资源编号。每个设备所需要资源的个数是不一定的，为此内核对这些资源进行了编号，对于不同的资源，编号之间是相互独立的。
+
+
+
+假若资源类型为IORESOURCE_IRQ，内核还提供以下函数接口，来获取中断引脚，
+
+
+
+.. code-block:: c 
+
+    :caption: platform_get_irq函数
+
+    :linenos:
+
+
+
+    int platform_get_irq(struct platform_device *pdev, unsigned int num)
+
+
+
+- pdev：指定要获取哪个平台设备的资源；
+
+- num：指定要获取的资源编号。
+
+
+
+对于存放在device结构体中成员platform_data的数据，我们可以使用dev_get_platdata函数来获取，函数原型如下所示：
+
+
+
+.. code-block:: c 
+
+    :caption: dev_get_platdata函数
+
+    :linenos:
+
+
+
+    static inline void *dev_get_platdata(const struct device *dev)
+
+    {
+
+        return dev->platform_data;
+
+    }
+
+
+
+dev_get_platdata函数的实现十分简单，直接返回device结构体中成员platform_data的值。
+
+
+
+平台驱动需要实现probe函数，当平台总线成功匹配驱动和设备时，则会调用驱动的probe函数，在该函数中使用上述的函数接口来获取资源，
+
+以初始化设备，最后填充结构体platform_driver，调用platform_driver_register进行注册。
+
+
+
+平台总线
+
+~~~~~
+
+在Linux的设备驱动模型中，总线是最重要的一环。上一节中，我们提到过总线是负责匹配设备和驱动，
+
+它维护了一个链表，里面记录着各个已经注册的平台设备和平台驱动。每当有新的设备或者是新的驱动加入到总线时，
+
+总线便会调用platform_match函数对新增的设备或驱动，进行配对。内核中使用bus_type来抽象描述系统中的总线，平台总线结构体原型如下所示：
+
+
+
+.. code-block:: c
+
+    :caption: platform_bus_type结构体(内核源码/driver/base/platform.c)
+
+    :linenos:
+
+
+
+    struct bus_type platform_bus_type = {
+
+        .name		= "platform",
+
+        .dev_groups	= platform_dev_groups,
+
+        .match		= platform_match,
+
+        .uevent		= platform_uevent,
+
+        .pm		= &platform_dev_pm_ops,
+
+    };
+
+    EXPORT_SYMBOL_GPL(platform_bus_type);
+
+
+
+platform_bus_type来描述平台总线，由于内核已经替我们实现了平台总线，我们只需要了解platform总线的match函数，
+
+清楚platform总线是如何将平台设备以及平台驱动联系到一起，其函数原型如下：
+
+
+
+.. code-block:: c
+
+    :caption: platform_match函数(内核源码/driver/base/platform.c)
+
+    :linenos:
+
+
+
+    static int platform_match(struct device *dev, struct device_driver *drv)
+
+    {
+
+        struct platform_device *pdev = to_platform_device(dev);
+
+        struct platform_driver *pdrv = to_platform_driver(drv);
+
+
+
+        /* When driver_override is set, only bind to the matching driver */
+
+        if (pdev->driver_override)
+
+            return !strcmp(pdev->driver_override, drv->name);
+
+
+
+        /* Attempt an OF style match first */
+
+        if (of_driver_match_device(dev, drv))
+
+            return 1;
+
+
+
+        /* Then try ACPI style match */
+
+        if (acpi_driver_match_device(dev, drv))
+
+            return 1;
+
+
+
+        /* Then try to match against the id table */
+
+        if (pdrv->id_table)
+
+            return platform_match_id(pdrv->id_table, pdev) != NULL;
+
+
+
+        /* fall-back to driver name match */
+
+        return (strcmp(pdev->name, drv->name) == 0);
+
+    }
+
+
+
+platform_match函数只传入两个参数：dev和drv。回想前面所学的知识，我们知道在platform_device和platform_driver中也有对应的成员，
+
+在platform_match开头，调用了两个宏定义to_platform_device和to_platform_driver，原型如下所示：
+
+
+
+.. code-block:: c
+
+    :caption: to_platform_xxx宏定义(内核源码/include/linux/platform_device.h)
+
+    :linenos:
+
+
+
+    #define to_platform_device(x) container_of((x), struct platform_device, dev)
+
+    #define to_platform_driver(drv)	(container_of((drv), struct platform_driver, driver))
+
+
+
+宏定义to_platform_device和to_platform_driver实现了对container_of的封装，利用该这两个宏便可以得到进行匹配的platform_driver和platform_device。
+
+platform总线提供了四种匹配方式，并且这四种方式存在着优先级：设备树机制>ACPI匹配模式>id_table方式>字符串比较。虽然匹配方式五花八门，但是并没有涉及到任何复杂的算法，
+
+都只是在匹配的过程中，比较一下设备和驱动提供的某个成员的字符串是否相同。设备树是一种描述硬件的数据结构，它用一个非C语言的脚本来描述这些硬件设备的信息。
+
+驱动和设备之间的匹配时通过比较compatible的值。acpi主要是用于电源管理，基本上用不到，这里就并不进行讲解了。关于设备树的匹配机制，会在设备树章节进行详细分析。
+
+
+
+我们在定义结构体platform_driver时，我们需要提供一个id_table的数组，该数组说明了当前的驱动能够支持的设备。当加载该驱动时，总线的match函数发现id_table非空，
+
+则会比较id_table中的name成员和平台设备的name成员，若相同，则会返回匹配的条目，具体的实现过程如下：
+
+
+
+.. code-block:: c
+
+    :caption: platform_match_id函数(内核源码/drivers/base/platform.c)
+
+    :linenos:
+
+
+
+    static const struct platform_device_id *platform_match_id(
+
+                const struct platform_device_id *id,
+
+                struct platform_device *pdev)
+
+    {
+
+        while (id->name[0]) {
+
+            if (strcmp(pdev->name, id->name) == 0) {
+
+                pdev->id_entry = id;
+
+                return id;
+
+            }
+
+            id++;
+
+        }
+
+        return NULL;
+
+    }
+
+
+
+每当有新的驱动或者设备添加到总线时，总线便会调用match函数对新的设备或者驱动进行配对。platform_match_id函数中第一个参数为驱动提供的id_table，
+
+第二个参数则是待匹配的平台设备。当待匹配的平台设备的name字段的值等于驱动提供的id_table中的值时，会将当前匹配的项赋值给platform_device中的id_entry，
+
+返回一个非空指针。若没有成功匹配，则返回空指针。
+
+
+
+.. image:: ./media/id_table_match.jpg
+
+   :align: center
+
+   :alt: 驱动和设备匹配过程
+
+
+
+倘若我们的驱动没有提供前三种方式的其中一种，那么总线进行匹配时，只能比较platform_device中的name字段以及嵌在platform_driver中的device_driver的name字段。
+
+
+
+
+
+.. image:: ./media/name_match.jpg
+
+   :align: center
+
+   :alt: 名称匹配方式
+
+
+
+
+
+实验
+
+~~~~~~~~~~~~~
+
+前面的小节，学习了平台设备驱动的相关理论知识。回到我们最初的问题，本节将会将平台设备驱动，应用到LED字符设备驱动的代码中，实现硬件与软件代码相分离，巩固平台设备驱动的学习。
+
+**本章的示例代码目录为：base_code/linux_driver/platform_driver**
+
+定义平台设备
+
+---------------
+
+我们需要将字符设备中的硬件信息提取出来，独立成一份代码，将其作为平台设备，注册到内核中。
+
+点亮LED灯，需要与LED灯相关的寄存器，包括GPIO时钟寄存器，IO配置寄存器，IO数据寄存器等，这些资源，实际上就是寄存器地址，可以使用IORESOURCE_MEM进行处理；
+
+除了这些之外，还需要提供一些寄存器的偏移量，我们可以利用平台设备的私有数据进行管理。
+
+
+
+.. code-block:: c
+
+    :caption: 寄存器宏定义(位于../base_code/linux_driver/platform_driver/led_pdev.c)
+
+    :linenos:
+
+
+
+    #define CCM_CCGR1 										0x20C406C	//时钟控制寄存器
+
+    #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO04 				0x20E006C	//GPIO1_04复用功能选择寄存器
+
+    #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO04 				0x20E02F8	//PAD属性设置寄存器
+
+    #define GPIO1_GDIR 										0x0209C004	//GPIO方向设置寄存器（输入或输出）
+
+    #define GPIO1_DR 										0x0209C000	//GPIO输出状态寄存器
+
+
+
+    #define CCM_CCGR3 										0x020C4074
+
+    #define GPIO4_GDIR 										0x020A8004
+
+    #define GPIO4_DR 										0x020A8000
+
+
+
+    #define IOMUXC_SW_MUX_CTL_PAD_GPIO4_IO020 			    0x020E01E0
+
+    #define IOMUXC_SW_PAD_CTL_PAD_GPIO4_IO020 			    0x020E046C
+
+
+
+    #define IOMUXC_SW_MUX_CTL_PAD_GPIO4_IO019 			    0x020E01DC
+
+    #define IOMUXC_SW_PAD_CTL_PAD_GPIO4_IO019 			    0x020E0468
+
+
+
+关于LED灯的寄存器，我们采用宏定义进行封装，具体每个寄存器的作用，可以参考《IMX6ULRM》。定义一个resource结构体，用于存放上述的寄存器地址，提供给驱动使用，如下所示：
+
+
+
+.. code-block:: c
+
+    :caption: 定义资源数组(位于../base_code/linux_driver/platform_driver/led_pdev.c)
+
+    :linenos: 
+
+
+
+    static struct resource rled_resource[] = {
+
+        [0] = DEFINE_RES_MEM(GPIO1_DR, 4),
+
+        [1] = DEFINE_RES_MEM(GPIO1_GDIR, 4),
+
+        [2] = DEFINE_RES_MEM(IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO04, 4),
+
+        [3] = DEFINE_RES_MEM(CCM_CCGR1, 4),
+
+        [4] = DEFINE_RES_MEM(IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO04, 4),
+
+    };
+
+
+
+在内核源码/include/linux/ioport.h中，提供了宏定义DEFINE_RES_MEM、DEFINE_RES_IO、DEFINE_RES_IRQ和DEFINE_RES_DMA，用来定义所需要的资源类型。
+
+DEFINE_RES_MEM用于定义IORESOURCE_MEM类型的资源，我们只需要传入两个参数，一个是寄存器地址，另一个是大小。从手册上看，可以得知一个寄存器都是32位的，因此，
+
+这里我们选择需要4个字节大小的空间。rled_resource资源数组中，我们将所有的MEM资源进行了编号，0对应了GPIO1_DR，1对应了GPIO1_GDIR，驱动到时候就可以根据这些编号获得对应的寄存器地址。
+
+我们使用一个数组rled_hwinfo，来记录这些偏移量，填充平台私有数据时，只需要把数组的首地址赋给platform_data即可。
+
+
+
+.. code-block:: c
+
+    :caption: 定义平台设备的私有数据(位于../base_code/linux_driver/platform_driver/led_pdev.c)
+
+    :linenos: 
+
+
+
+    unsigned int rled_hwinfo[2] = { 4, 26 };
+
+
+
+关于设备的硬件信息，我们已经全部完成了，接下来只需要定义一个platform_device类型的变量，填充相关信息。
+
+
+
+.. code-block:: c
+
+    :caption: 定义平台设备(位于../base_code/linux_driver/platform_driver/led_pdev.c)
+
+    :linenos: 
+
+
+
+    static int led_cdev_release(struct inode *inode, struct file *filp)
+
+    {
+
+        return 0;
+
+    }
+
+
+
+    /* red led device */ 
+
+    static struct platform_device rled_pdev = {
+
+        .name = "led_pdev",
+
+        .id = 0,
+
+        .num_resources = ARRAY_SIZE(rled_resource),
+
+        .resource = rled_resource,
+
+        .dev = {
+
+            .release = led_release,
+
+            .platform_data = rled_hwinfo,
+
+            },
+
+    };
+
+
+
+这里我们定义了一个设备名为“led_pdev”的设备，这里的名字确保要和驱动的名称保持一致，否则就会导致匹配失败。id编号设置为0，驱动会利用该编号来注册设备。
+
+对于设备资源，我们将上面实现好的rled_resource数组赋值给resource成员，同时，我们还需要指定资源的数量，内核同样也提供了宏定义ARRAY_SIZE，用于计算数组长度，
+
+因此，num_resources直接赋值为ARRAY_SIZE(rled_resource)。这里的led_release函数为空，目的为了防止卸载模块，内核提示报错。
+
+
+
+最后，只需要在模块加载的函数中调用platform_device_register函数，这样，当加载该内核模块时，新的平台设备就会被注册到内核中去，实现方式如下：
+
+
+
+
+
+.. code-block:: c
+
+    :caption: 模块初始化(位于../base_code/linux_driver/platform_driver/led_pdev.c)
+
+    :linenos:
+
+
+
+    static __init int led_pdev_init(void)
+
+    {
+
+        printk("pdev init\n");
+
+        platform_device_register(&rled_pdev);
+
+        return 0;
+
+    }
+
+
+
+    module_init(led_pdev_init);
+
+
+
+    static __exit void led_pdev_exit(void)
+
+    {
+
+        printk("pdev exit\n");
+
+        platform_device_unregister(&rled_pdev);
+
+    }
+
+
+
+    module_exit(led_pdev_exit);
+
+
+
+    MODULE_AUTHOR("Embedfire");
+
+    MODULE_LICENSE("GPL");
+
+    MODULE_DESCRIPTION("the example for platform driver");
+
+
+
+这样，我们就实现了一个新的设备，只需要在开发板上加载该模块，平台总线下就会挂载我们LED灯的平台设备。
+
+
+
+定义平台驱动
+
+-------------------
+
+我们已经注册了一个新的平台设备，驱动只需要提取该设备提供的资源，并提供相应的操作方式即可。这里我们仍然采用字符设备来控制我们的LED灯，关于这部分的内容，LED灯字符设备已经详细讲解过了，
+
+后面只会贴出相应的代码，不做详细介绍了。
+
+
+
+我们驱动提供id_table的方式，来匹配设备。我们定义一个platform_device_id类型的变量led_pdev_ids，说明驱动支持哪些设备，
+
+这里我们只支持一个设备，名称为led_pdev，要与平台设备提供的名称保持一致。
+
+
+
+.. code-block:: c
+
+    :caption: id_table(位于../base_code/linux_driver/platform_driver/led_pdrv.c)
+
+    :linenos: 
+
+
+
+
+
+    static struct platform_device_id led_pdev_ids[] = {
+
+        {.name = "led_pdev"},
+
+        {}
+
+    };
+
+
+
+    MODULE_DEVICE_TABLE(platform, led_pdev_ids);
+
+
+
+代码提供了驱动支持哪些设备，这仅仅完成了第一个内容，这是总线进行匹配时所需要的内容。匹配成功之后，驱动需要去提取设备的资源，
+
+这部分工作都是在probe函数中完成。由于我们采用字符设备的框架，因此，在probe过程，还需要完成字符设备的注册等工作，具体实现的代码如下：
+
+
+
+.. code-block:: c
+
+    :caption: led_pdrv_probe函数(位于../base_code/linux_driver/platform_driver/led_pdrv.c)
+
+    :linenos: 
+
+
+
+    struct led_data {
+
+        unsigned int led_pin;
+
+        unsigned int clk_regshift;
+
+
+
+        unsigned int __iomem *va_dr;
+
+        unsigned int __iomem *va_gdir;
+
+        unsigned int __iomem *va_iomuxc_mux;
+
+        unsigned int __iomem *va_ccm_ccgrx;
+
+        unsigned int __iomem *va_iomux_pad;	
+
+
+
+        struct cdev led_cdev;
+
+
+
+    };    
+
+
+
+
+
+    static int led_pdrv_probe(struct platform_device *pdev)
+
+    {
+
+        struct led_data *cur_led;
+
+        unsigned int *led_hwinfo;
+
+        
+
+        struct resource *mem_dr;
+
+        struct resource *mem_gdir;
+
+        struct resource *mem_iomuxc_mux;
+
+        struct resource *mem_ccm_ccgrx;
+
+        struct resource *mem_iomux_pad; 	
+
+
+
+        dev_t cur_dev;
+
+
+
+        int ret = 0;
+
+        
+
+        printk("led platform driver probe\n");
+
+        //第一步：提取平台设备提供的资源
+
+        cur_led = devm_kzalloc(&pdev->dev, sizeof(struct led_data), GFP_KERNEL);
+
+        if(!cur_led)
+
+            return -ENOMEM;
+
+        led_hwinfo = devm_kzalloc(&pdev->dev, sizeof(unsigned int)*2, GFP_KERNEL);
+
+        if(!led_hwinfo)
+
+            return -ENOMEM;
+
+
+
+        /* get the pin for led and the reg's shift */
+
+        led_hwinfo = dev_get_platdata(&pdev->dev);
+
+
+
+        cur_led->led_pin = led_hwinfo[0];
+
+        cur_led->clk_regshift = led_hwinfo[1];
+
+        /* get platform resource */
+
+        mem_dr = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+
+        mem_gdir = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+
+        mem_iomuxc_mux = platform_get_resource(pdev, IORESOURCE_MEM, 2);
+
+        mem_ccm_ccgrx = platform_get_resource(pdev, IORESOURCE_MEM, 3);
+
+        mem_iomux_pad = platform_get_resource(pdev, IORESOURCE_MEM, 4);
+
+
+
+        cur_led->va_dr =
+
+            devm_ioremap(&pdev->dev, mem_dr->start, resource_size(mem_dr));
+
+        cur_led->va_gdir =
+
+            devm_ioremap(&pdev->dev, mem_gdir->start, resource_size(mem_gdir));
+
+        cur_led->va_iomuxc_mux =
+
+            devm_ioremap(&pdev->dev, mem_iomuxc_mux->start,
+
+                resource_size(mem_iomuxc_mux));
+
+        cur_led->va_ccm_ccgrx =
+
+            devm_ioremap(&pdev->dev, mem_ccm_ccgrx->start,
+
+                resource_size(mem_ccm_ccgrx));
+
+        cur_led->va_iomux_pad =
+
+            devm_ioremap(&pdev->dev, mem_iomux_pad->start,
+
+                resource_size(mem_iomux_pad));
+
+        //第二步：注册字符设备
+
+        cur_dev = MKDEV(DEV_MAJOR, pdev->id);
+
+
+
+        register_chrdev_region(cur_dev, 1, "led_cdev");
+
+
+
+        cdev_init(&cur_led->led_cdev, &led_cdev_fops);
+
+
+
+        ret = cdev_add(&cur_led->led_cdev, cur_dev, 1);
+
+        if(ret < 0)
+
+        {
+
+            printk("fail to add cdev\n");
+
+            goto add_err;
+
+        }
+
+        
+
+        device_create(my_led_class, NULL, cur_dev, NULL, DEV_NAME "%d", pdev->id);
+
+
+
+        /* save as drvdata */ 
+
+        platform_set_drvdata(pdev, cur_led);
+
+
+
+        return 0;
+
+
+
+    add_err:
+
+        unregister_chrdev_region(cur_dev, 1);
+
+        return ret;
+
+    }
+
+
+
+
+
+代码中仍然使用结构体led_data来管理我们LED灯的硬件信息，首先，我们需要获取平台设备中提供的资源，使用dev_get_platdata函数获取私有数据，得到LED灯的寄存器偏移量，
+
+并赋值给cur_led->led_pin和cur_led->clk_regshift。同样的，利用函数platform_get_resource可以获取到各个寄存器的地址，在内核中，这些地址并不能够直接使用，
+
+必须使用devm_ioremap函数将这些地址转换为虚拟地址。这样的话，我们就完成提取资源的工作了。
+
+
+
+接下来，就需要注册一个LED字符设备了。开发板上板载了三个LED灯，在rled_pdev结构体中，我们指定了红灯的ID号为0，我们可以利用该id号，来作为字符设备的次设备号，用于区分不同的LED灯。
+
+使用MKDEV宏定义来创建一个设备编号，再调用register_chrdev_region、cdev_init、cdev_add等函数来注册字符设备。在probe函数的最后，我们使用platform_set_drvdata函数，保存了当前的LED数据信息。
+
+
+
+当驱动的内核模块被卸载时，我们需要将注册的驱动注销，相应的字符设备也同样需要注销，具体的实现代码如下：
+
+
+
+.. code-block:: c
+
+    :caption: led_pdrv_remove函数(位于../base_code/linux_driver/platform_driver/led_pdrv.c)
+
+    :linenos: 
+
+
+
+    static int led_pdrv_remove(struct platform_device *pdev)
+
+    {
+
+        dev_t cur_dev; 
+
+        struct led_data *cur_data = platform_get_drvdata(pdev);
+
+
+
+
+
+        printk("led platform driver remove\n");
+
+
+
+        cur_dev = MKDEV(DEV_MAJOR, pdev->id);
+
+
+
+        cdev_del(&cur_data->led_cdev);
+
+
+
+        device_destroy(my_led_class, cur_dev);
+
+
+
+        unregister_chrdev_region(cur_dev, 1);
+
+
+
+        return 0;
+
+    }
+
+
+
+我们在probe函数中调用了platform_set_drvdata，将当前的LED灯数据结构体保存到pdev的driver_data成员中，
+
+我们只需要调用platform_get_drvdata，即可获取当前LED灯对应的结构体，该结构体中包含了字符设备，调用cdev_del删除对应的字符设备，
+
+删除/dev目录下的设备，则调用函数device_destroy，最后使用函数unregister_chrdev_region，注销掉当前的字符设备编号
+
+
+
+关于操作LED灯字符设备的方式，实现方式如下，具体介绍可以参阅LED灯字符设备章节的内容。
+
+
+
+
+
+.. code-block:: c
+
+    :caption: led灯的字符设备框架(位于../base_code/linux_driver/platform_driver/led_pdrv.c)
+
+    :linenos: 
+
+
+
+    static int led_cdev_open(struct inode *inode, struct file *filp)
+
+    {
+
+        printk("%s\n", __func__);
+
+        
+
+        struct led_data *cur_led = container_of(inode->i_cdev, struct led_data, led_cdev);
+
+        unsigned int val = 0;
+
+
+
+        val = readl(cur_led->va_ccm_ccgrx);
+
+        val &= ~(3 << cur_led->clk_regshift);
+
+        val |= (3 << cur_led->clk_regshift);
+
+        writel(val, cur_led->va_ccm_ccgrx);
+
+
+
+        writel(5, cur_led->va_iomuxc_mux);
+
+
+
+        writel(0x1F838, cur_led->va_iomux_pad);
+
+
+
+        val = readl(cur_led->va_gdir);
+
+        val &= ~(1 << cur_led->led_pin);
+
+        val |= (1 << cur_led->led_pin);
+
+        writel(val, cur_led->va_gdir);
+
+
+
+        val = readl(cur_led->va_dr);
+
+        val |= (0x01 << cur_led->led_pin);
+
+        writel(val, cur_led->va_dr);
+
+
+
+        filp->private_data = cur_led;
+
+
+
+        return 0;
+
+    }
+
+
+
+
+
+    static int led_cdev_release(struct inode *inode, struct file *filp)
+
+    {
+
+        return 0;
+
+    }
+
+
+
+    static ssize_t led_cdev_write(struct file *filp, const char __user * buf,
+
+                    size_t count, loff_t * ppos)
+
+    {
+
+        unsigned long val = 0;
+
+        unsigned long ret = 0;
+
+
+
+        int tmp = count;
+
+
+
+        struct led_data *cur_led = (struct led_data *)filp->private_data;
+
+
+
+        kstrtoul_from_user(buf, tmp, 10, &ret);
+
+
+
+        val = readl(cur_led->va_dr);
+
+        if (ret == 0)
+
+            val &= ~(0x01 << cur_led->led_pin);
+
+        else
+
+            val |= (0x01 << cur_led->led_pin);
+
+
+
+        writel(val, cur_led->va_dr);
+
+        *ppos += tmp;
+
+
+
+        return tmp;
+
+    }
+
+
+
+    static struct file_operations led_cdev_fops = {
+
+        .open = led_cdev_open,
+
+        .release = led_cdev_release,
+
+        .write = led_cdev_write,
+
+    };
+
+
+
+最后，我们只需要将我们实现好的内容，填充到platform_driver类型的结构体，并使用platform_driver_register函数注册即可。
+
+
+
+.. code-block:: c
+
+    :caption: 注册平台驱动(位于../base_code/linux_driver/platform_driver/led_pdrv.c)
+
+    :linenos: 
+
+
+
+    static struct platform_driver led_pdrv = {    
+
+        .probe = led_pdrv_probe,
+
+        .remove = led_pdrv_remove,
+
+        .driver.name = "led_pdev",
+
+        .id_table = led_pdev_ids,
+
+    };
+
+
+
+    static __init int led_pdrv_init(void)
+
+    {
+
+        printk("led platform driver init\n");
+
+
+
+        my_led_class = class_create(THIS_MODULE, "my_leds");
+
+        
+
+        platform_driver_register(&led_pdrv);
+
+
+
+        return 0;
+
+    }
+
+    module_init(led_pdrv_init);
+
+
+
+
+
+    static __exit void led_pdrv_exit(void)
+
+    {
+
+        printk("led platform driver exit\n");	
+
+
+
+        platform_driver_unregister(&led_pdrv);
+
+
+
+        class_destroy(my_led_class);
+
+
+
+    }
+
+    module_exit(led_pdrv_exit);
+
+
+
+    MODULE_AUTHOR("Embedfire");
+
+    MODULE_LICENSE("GPL");
+
+    MODULE_DESCRIPTION("the example for platform driver");
+
+
+
+我们在led_pdrv中定义了两种匹配模式，在平台总线匹配过程中，只会根据id_table中的name值进行匹配，若和平台设备的name值相等，则表示匹配成功；
+
+反之，则匹配不成功，表明当前内核没有该驱动能够支持的设备。在模块的初始化函数led_pdrv_init中，我们调用函数class_create，来创建一个led类，并且调用函数platform_driver_register，
+
+注册我们的平台驱动结构体，这样当加载该内核模块时，就会有新的平台驱动加入到内核中。模块的注销函数led_pdrv_exit，则是初始化函数的逆过程。
+
+
+
+编译led_pdrv.c和led_pdev.c的Makefile如下所示，编写该Makefile时，只需要根据实际情况修改变量KERNEL_DIR和obj-m即可。
+
+
+
+   :caption: Makefile(位于../base_code/linux_driver/platform_driver/Makefile)
+   :language: makefile
+   :linenos:  
+
+    KERNEL_DIR = /home/embedfire/linux4.19
+
+
+
+    obj-m := led_pdev.o led_pdrv.o
+
+
+
+    all:modules
+
+    modules clean:
+
+        $(MAKE) -C $(KERNEL_DIR) M=$(shell pwd) $@
+
+
+
+
+
+
+
+
+
+实验结果
+
+-------------------
+
+教程中为了节省篇幅，只列举了一个led灯，配套的例程中提供了三个LED的代码。当我们运行命令"insmod led_pdev.ko"后，
+
+可以在/sys/bus/platform/devices下看到我们注册的LED灯设备，共有三个，后面的数字0、1、2对应了平台设备结构体的id编号。
+
+
+
+.. image:: ./media/led_devices.jpg
+
+   :align: center
+
+   :alt: led灯设备
+
+
+
+
+
+执行命令“insmod led_pdrv.ko”，加载LED的平台驱动。在运行命令“dmesg|tail"来查看内核打印信息，可以看到打印了三次probe，分别对应了三个LED灯设备。
+
+
+
+.. image:: ./media/result.jpg
+
+   :align: center
+
+   :alt: led灯设备
+
+
+
+通过驱动代码，最后会在/dev下创建三个LED灯设备，分别为led0、led1、led2，可以使用echo命令来测试我们的LED驱动是否正常。
+
+以红灯（/dev/led0）为例，我们使用命令“echo 0 > /dev/led0”可控制红灯亮，命令“echo 1 > /dev/led0”可控制红灯亮，
\ No newline at end of file
diff --git a/documentation/linux_env/index.rst b/documentation/linux_env/index.rst
new file mode 100644
index 0000000000000000000000000000000000000000..0277ec85ff065886abc9949fd3037232ee7419d6
--- /dev/null
+++ b/documentation/linux_env/index.rst
@@ -0,0 +1,24 @@
+.. vim: syntax=rst
+
+搭建并熟悉Debian的各种开发环境
+==================================
+
+这一部分主要是为用户熟悉野火Debian系统，并搭建相关的开发环境。对于已经熟悉Debian开发环境的用户，可以略读本章节的内容，并直接使用配套资料提供的搭建环境脚本直接安装所有环境依赖。
+
+对于不熟悉Debian系统的用户，这是一个破冰过程。请紧跟书中的步骤亲自搭建开发环境，在这搭建的过程中会建立起对Debian开发环境的亲切感，并且了解到为什么需要安装这些依赖环境，这对后期的学习是非常有必要掌握的基础。
+
+
+
+.. .. toctree::
+..    :maxdepth: 1
+..    :numbered:
+
+..    qt_cross_compiling
+..    python37_env
+..    pyqt5_env
+..    python_ssd1306
+..    python_gpio
+..    python_serial
+..    using_sqlite
+..    using_qtsqlite
+..    using_php
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+Debian搭建PyQt5环境
+===================
+
+-  平台：野火imx6ull开发板
+-  系统：Debian
+-  Python版本：Python3.7
+-  PyQt版本：PyQt5
+
+PyQt是Qt应用框架与Python的结合，同时支持Python2.x和Python3.x版本，本教程使用的是Python3.7版本，PyQt5版本。
+
+PyQt5是由一系列Python模块组成，超过620个类，6000函数和方法。能在诸如Unix、Windows和Mac
+OS等主流操作系统上运行，而且由于Python语言的开发方便性，在编写代码时比C++更为方便，美中不足的是Python语言的执行效率会比C++慢。
+
+首先烧录好Debian镜像，为了确保我们的版本是最新版本，让我们使用apt命令更新本地apt包索引和升级系统：
+
+.. code:: bash
+
+        sudo apt-get update && sudo apt-get -y upgrade
+        
+
+手动安装Python3，强烈建议参考上一章的Python环境搭建:
+
+.. code:: bash
+
+        sudo apt-get -y install python3-pip python3
+
+然后安装PyQt5：
+
+.. code:: bash
+
+        sudo apt-get -y install python3-pyqt5
+
+最后安装一些依赖的deb包，它主要是用于提供tslib触摸、中文字库等功能：
+
+.. code:: bash
+
+        sudo apt-get -y install libts-bin 
+
+.. code:: bash
+
+        sudo apt-get -y install devscan 
+
+.. code:: bash
+
+        sudo apt-get -y install ebf-tslibplugin
+    
+.. code:: bash
+
+        sudo apt-get -y install ebf-fonts
+    
+
+然后运行：
+
+.. code:: bash
+
+    sudo depmod -a
+
+最后重启开发板：
+
+::
+
+        sudo reboot
+
+这样子环境就搭建完成。
+
+接下来我们测试一下PyQt5在开发板上的运行：
+
+首先编写一个名字为pyqt5_demo.py的PyQt5应用程序，它主要是用于测试显示、触摸、信号、槽函数、以及PyQt5的部分组件如：QWidget、QLCDNumber、QSlider、QVBoxLayout等的简单使用，虽然是很简单的程序，但足以满足我们的测试，这样子就能说明野火开发板的Debian系统是可以运行PyQt5的，并且可以通过它看出PyQt5的执行效率，目前我的测试还是可以非常快响应的。
+
+pyqt5_demo.py代码如下:
+
+.. code:: py
+
+    import sys
+    from PyQt5.QtWidgets import QWidget,QLCDNumber,QSlider,QVBoxLayout,QApplication
+    from PyQt5.QtCore import Qt
+
+    class WinForm(QWidget):
+        def __init__(self):
+            super().__init__()   
+            self.initUI()
+
+        def initUI(self):
+            #1 先创建滑块和 LCD 部件
+            lcd = QLCDNumber(self)
+            slider = QSlider(Qt.Horizontal, self)
+            
+            slider.setMaximum(1000)
+            lcd.display(666)
+            slider.setValue(666)
+
+            #2 通过QVboxLayout来设置布局
+            vBox = QVBoxLayout()
+            vBox.addWidget(lcd)
+            vBox.addWidget(slider)
+
+            self.setLayout(vBox)
+            #3 valueChanged()是Qslider的一个信号函数，只要slider的值发生改变，它就会发射一个信号，然后通过connect连接信号的接收部件，也就是lcd。
+            slider.valueChanged.connect(lcd.display)
+           
+            slider.setMinimumWidth(200) 
+            slider.setFixedHeight(60)
+            
+            style = "QSlider::groove:horizontal {border:1px solid #999999;height:10px;" \
+                    "background-color:#666666;margin:2px 0;}" \
+                    "QSlider::handle:horizontal {background-color:#ff0000;border:1px solid #797979;" \
+                    "width:50px;margin:-20px;border-radius:25px;}" \
+                                
+            slider.setStyleSheet(style);
+            
+            #self.setGeometry(0,0,800,480)
+            self.setWindowTitle("拖动滑块LCD显示")
+
+    if __name__ == '__main__':
+        app = QApplication(sys.argv)
+        form = WinForm()
+        form.resize(800, 480)
+        form.show()                      
+        sys.exit(app.exec_())
+
+然后创建一个run.sh脚本，通过它来运行我们的pyqt5_demo.py，为什么需要一个脚本呢，是因为我们需要导出相关的环境变量，比如显示、触摸等环境变量，这个脚本需要使用sudo权限运行。
+
+run.sh脚本内容如下:
+
+.. code:: bash
+
+    #! /bin/sh
+
+    type devscan
+
+    if [ $? -eq 0 ]; then
+        eventx=$(devscan "goodix-ts")
+        echo "eventx=$eventx"
+        if [ "$eventx " != " " ]; then
+            if [ ! -f "/etc/pointercal" ]; then
+                type ts_calibrate
+                if [ $? -eq 0 ]; then
+                    ts_calibrate
+                fi
+            fi
+        else 
+            echo "eventx is null"
+        fi
+    else
+        echo "please install devscan"
+        echo
+        echo "sudo apt-get install devscan"
+        exit
+    fi
+
+    export TSLIB_TSDEVICE=/dev/input/$eventx
+    export QT_QPA_PLATFORM=linuxfb:fb=/dev/fb0
+    export TSLIB_CONFFILE=/etc/ts.conf
+    export TSLIB_CALIBFILE=/etc/pointercal
+    export QT_QPA_GENERIC_PLUGINS=tslib:/dev/input/$eventx
+    export QT_QPA_EVDEV_TOUCHSCREEN_PARAMETERS=/dev/input/$eventx
+
+    echo "start pyqt pyqt5_demo..."
+    python3 pyqt5_demo.py
+
+赋予脚本可执行权限：
+
+.. code:: bash
+
+    chmod +x run.sh
+
+运行：
+
+.. code:: bash
+
+    sudo ./run.sh
+
+效果：
+
+.. figure:: media/pyqt5_001.png
+   :alt: pyqt5_001
+
+   pyqt5_001
+
diff --git a/documentation/linux_env/python37_env.rst b/documentation/linux_env/python37_env.rst
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+++ b/documentation/linux_env/python37_env.rst
@@ -0,0 +1,333 @@
+在Debian系统中部署Python3.7运行环境
+===================================
+
+-  平台：野火imx6ull开发板
+-  系统：Debian
+-  目标Python版本：Python3.7
+
+    注意：此处的操作是在野火imx6ull开发板上（运行的是Debian系统），而非虚拟机。
+
+介绍
+----
+
+Python是一种灵活的多功能编程语言，适用于许多用例，包括脚本，自动化，数据分析，机器学习和后端开发。
+1991年首次出版，其名称灵感来自英国喜剧组织Monty Python，开发团队希望让Python成为一种有趣的语言。
+快速设置即时反馈错误，Python是一个有用的语言，可供初学者和经验丰富的开发人员学习。
+Python3是该语言的最新版本，而Python2则逐渐被停止维护，并且Python3与Python2之间的差别还是很大的，
+Python2的程序不一定能在Python3上运行，因此我们只使用Python3即可。
+
+本教程将在Debian系统中搭建Python3开发环境，并且简单使用。
+
+更新
+----
+
+其实在很多Debian系统中都预装了Python3或者Python2，但是野火提供的镜像是并未预装Python3的，
+我们可以手动安装，为了确保我们的版本是最新版本，让我们使用apt命令更新本地apt包索引和升级系统：
+
+.. code:: bash
+
+    sudo apt-get update
+    sudo apt-get -y upgrade
+
+-y 标志将确认我们同意所有要安装的项目。
+
+手动安装Python3
+---------------
+
+.. code:: bash
+
+    sudo apt-get -y install python3
+
+可以看到Python3有很多依赖的deb包：
+
+.. code:: bash
+
+    Reading package lists... Done
+    Building dependency tree
+    Reading state information... Done
+    The following additional packages will be installed:
+      libmpdec2 libpython3-stdlib libpython3.7-minimal libpython3.7-stdlib
+      python3-minimal python3.7 python3.7-minimal
+    Suggested packages:
+      python3-doc python3-tk python3-venv python3.7-venv python3.7-doc binutils
+      binfmt-support
+    The following NEW packages will be installed:
+      libmpdec2 libpython3-stdlib libpython3.7-minimal libpython3.7-stdlib python3
+      python3-minimal python3.7 python3.7-minimal
+    0 upgraded, 8 newly installed, 0 to remove and 0 not upgraded.
+    Need to get 4224 kB of archives.
+    After this operation, 19.6 MB of additional disk space will be used.
+
+当然啦，这些依赖的deb包是不需要我们手动安装的，Debian会自动安装。
+
+在安装完成后，校验是否安装成功：
+
+.. code:: bash
+
+     python3 -V
+
+当出现以下内容时表示Python3安装成功：
+
+.. code:: bash
+
+    Python 3.7.3
+
+设置Debian系统的默认Python版本
+------------------------------
+
+如果你是运行以下命令校验Python的版本：
+
+.. code:: bash
+
+    python -V
+
+并且当你的系统存在Python2的话，那么版本可能就是 ``Python 2.7.16`` ，那么与我们想要安装的Python3版本并不符合，因此我们要设置Python3位默认版本：
+
+.. code:: bash
+
+    cd /usr/bin
+    sudo rm python
+    sudo ln -s python3.7 python
+    cd ~
+
+再次校验Python版本时，发现系统默认的Python版本就是python3.7了：
+
+.. code:: bash
+
+    python3 -V
+
+    # 版本
+    Python 3.7.3
+
+简单使用Python
+--------------
+
+我们可以直接运行python命令进入Python的交互式编程，交互式编程不需要创建脚本文件，是通过
+Python
+解释器的交互模式进来编写代码。在这里可以做一些简单的操作，比如在中断打印"hello
+world!"，做一些算术运算等，最后通过 ``exit()`` 退出：
+
+.. code:: bash
+
+    debian@npi:~$ python
+    Python 3.7.3 (default, Dec 20 2019, 18:57:59)
+    [GCC 8.3.0] on linux
+    Type "help", "copyright", "credits" or "license" for more information.
+    >>> 
+    >>> print("hello world!")
+    hello world!
+    >>>
+    >>> 8+2
+    10
+    >>> exit()
+
+我们也可以编写一个简单的Python代码，保存为 ``hello.py`` ，注意要是.py格式的文件。
+
+代码如下：
+
+.. code:: py
+
+    print("Hello, Python!")
+
+然后运行：
+
+.. code:: bash
+
+    # 编写hello.py
+    debian@npi:~$ ls
+    hello.py 
+
+    # 运行
+    debian@npi:~$ python hello.py
+    Hello, Python!
+
+当然也可以运行一些比较复杂的Python代码，此处示例是获取某地（比如北京）的天气：
+
+我们新建一个 ``weather.py`` ，写入以下代码：
+
+.. code:: py
+
+    # 导入json、requests包
+    import json, requests
+
+    #输入地点
+    weather_place = "东莞"
+
+    #日期
+    date = []
+    #最高温与最低温
+    high_temp = []
+    low_temp = []
+    #天气
+    weather = []
+
+    # 请求天气信息
+    weather_url = "http://wthrcdn.etouch.cn/weather_mini?city=%s" % (weather_place)
+
+    response = requests.get(weather_url)
+    try:
+        response.raise_for_status()
+    except:
+        print("请求信息出错")
+        
+    #将json文件格式导入成python的格式
+    weather_data = json.loads(response.text)
+
+    # 打印原始数据
+    # print(weather_data)
+     
+    w = weather_data['data']
+
+    print("地点：%s" % w['city'])
+
+    #进行五天的天气遍历，并格式化输出
+    for i in range(len(w['forecast'])):
+        date.append(w['forecast'][i]['date'])
+        high_temp.append(w['forecast'][i]['high'])
+        low_temp.append(w['forecast'][i]['low'])
+        weather.append(w['forecast'][i]['type'])
+        
+        #输出
+        print("日期：" + date[i])
+        print("\t温度：最" + low_temp[i] + "\t最" + high_temp[i])
+        print("\t天气：" + weather[i] + "\n")
+        
+    print("\n今日着装：" + w['ganmao'])
+    print("当前温度：" + w['wendu'])
+
+然后尝试运行：
+
+.. code:: bash
+
+    python weather.py
+
+    # 输出
+    Traceback (most recent call last):
+      File "weather.py", line 1, in <module>
+        import json, requests
+    ModuleNotFoundError: No module named 'requests'
+
+它会提示说没有 ``requests`` 模块（一般是被称之为包），那么怎么办呢，我们需要安装对应的包，才可以在python程序中正常使用。
+
+安装pip包管理工具
+-----------------
+
+接下来我们就讲解怎么去安装对应的包。
+
+pip是一个Python的包管理系统，允许用户安装Python包。使用pip，您可以从Python包索引（PyPI）和其他存储库安装对应的包。
+
+我们首先还是更新一下apt的索引：
+
+.. code:: bash
+
+    sudo apt-get update
+
+然后安装python3-pip：
+
+.. code:: bash
+
+    sudo apt-get -y install python3-pip
+
+在安装完成后验证一下：
+
+.. code:: bash
+
+    pip3 --version
+
+    # 出现以下内容表示安装成功
+    pip 18.1 from /usr/lib/python3/dist-packages/pip (python 3.7)
+
+使用pip包管理工具
+-----------------
+
+接下来我们就讲解怎么使用pip包管理工具去安装对应的包。用户可以从PyPI，版本控制，本地项目和分发文件安装软件包，但在大多数情况下，我们一般都是从PyPI安装软件包。
+
+以为从上面的示例报错中发现，我是缺少一个名为 ``requests`` 的软件包，那么我们就可以通过以下命令去安装 ``requests`` 软件包：
+
+.. code:: bash
+
+    pip3 install requests
+
+    # 输出内容：
+
+    Collecting requests
+    Downloading https://files.pythonhosted.org/packages/1a/70/1935c770cb3be6e3a8b78ced23d7e0f3b187f5cbfab4749523ed65d7c9b1/requests-2.23.0-py2.py3-none-any.whl (58kB)
+        100% |████████████████████████████████| 61kB 16kB/s
+    Collecting chardet<4,>=3.0.2 (from requests)
+    Downloading https://files.pythonhosted.org/packages/bc/a9/01ffebfb562e4274b6487b4bb1ddec7ca55ec7510b22e4c51f14098443b8/chardet-3.0.4-py2.py3-none-any.whl (133kB)
+        100% |████████████████████████████████| 143kB 16kB/s
+    Collecting certifi>=2017.4.17 (from requests)
+    Downloading https://files.pythonhosted.org/packages/b9/63/df50cac98ea0d5b006c55a399c3bf1db9da7b5a24de7890bc9cfd5dd9e99/certifi-2019.11.28-py2.py3-none-any.whl (156kB)
+        100% |████████████████████████████████| 163kB 11kB/s
+    Collecting urllib3!=1.25.0,!=1.25.1,<1.26,>=1.21.1 (from requests)
+    Downloading https://files.pythonhosted.org/packages/e8/74/6e4f91745020f967d09332bb2b8b9b10090957334692eb88ea4afe91b77f/urllib3-1.25.8-py2.py3-none-any.whl (125kB)
+        100% |████████████████████████████████| 133kB 11kB/s
+    Collecting idna<3,>=2.5 (from requests)
+    Downloading https://files.pythonhosted.org/packages/89/e3/afebe61c546d18fb1709a61bee788254b40e736cff7271c7de5de2dc4128/idna-2.9-py2.py3-none-any.whl (58kB)
+        100% |████████████████████████████████| 61kB 12kB/s
+    Installing collected packages: chardet, certifi, urllib3, idna, requests
+    The script chardetect is installed in '/home/debian/.local/bin' which is not on PATH.
+    Consider adding this directory to PATH or, if you prefer to suppress this warning, use --no-warn-script-location.
+    Successfully installed certifi-2019.11.28 chardet-3.0.4 idna-2.9 requests-2.23.0 urllib3-1.25.8
+
+
+然后重新运行weather.py程序
+
+.. code:: bash
+
+    python weather.py
+
+    # 输出
+    地点：东莞
+    日期：27日星期五
+            温度：最低温 21℃        最高温 28℃
+            天气：阵雨
+
+    日期：28日星期六
+            温度：最低温 18℃        最高温 23℃
+            天气：中到大雨
+
+    日期：29日星期天
+            温度：最低温 17℃        最高温 24℃
+            天气：阴
+
+    日期：30日星期一
+            温度：最低温 21℃        最高温 26℃
+            天气：阴
+
+    日期：31日星期二
+            温度：最低温 20℃        最高温 28℃
+            天气：阵雨
+
+
+    今日着装：天气转凉，空气湿度较大，较易发生感冒，体质较弱的朋友请注意适当防护。
+    当前温度：27
+
+pip的其他操作
+-------------
+
+卸载包：
+
+.. code:: bash
+
+    pip3 uninstall "package_name"
+
+从PyPI搜索包：
+
+.. code:: bash
+
+    pip3 search "package_name"
+
+列出已安装的包：
+
+.. code:: bash
+
+    pip3 list
+
+列出过时的包：
+
+.. code:: bash
+
+    pip3 list --outdated
+
+至此，Python3的环境搭建基本完成，更多内容大家可以自行探索。
diff --git a/documentation/linux_env/python_gpio.rst b/documentation/linux_env/python_gpio.rst
new file mode 100644
index 0000000000000000000000000000000000000000..cad4f16191e9eaa28849d868d2500d1e112a7c0f
--- /dev/null
+++ b/documentation/linux_env/python_gpio.rst
@@ -0,0 +1,214 @@
+Debian搭建Python控制GPIO开发环境
+================================
+
+说明
+----
+
+-  平台：野火imx6ull开发板
+-  系统：Debian
+-  目标Python版本：Python3.7
+
+**注意：此处的操作是在野火imx6ull开发板上（运行的是Debian系统），而非虚拟机。**
+
+在上一章的教程中，我们通过Python控制OLED显示了一些东西，但是如果我们想要通过python控制某个io口怎么办呢，其实很简单，就是一样的操作。
+
+如果你能通过python控制OLED
+屏幕了，那么接下来的应用层代码是非常简单的，写就对了。
+
+如果你还没有安装Python的环境，请参考: `在Debian系统中部署Python3.7运行环境 <https://tutorial.linux.doc.embedfire.com/zh_CN/latest/linux_env/python37_env.html>`__
+
+如果你还没下载并安装 ``Adafruit_Blinka、Adafruit_CircuitPython_SSD1306、Adafruit_Python_PlatformDetect`` 这些库，请参考: `Debian搭建Python控制OLED开发环境 <https://tutorial.linux.doc.embedfire.com/zh_CN/latest/linux_env/python_ssd1306.html>`__ 。
+
+修改pin引脚
+-----------
+
+首先进入 ``Adafruit_Blinka/src/adafruit_blinka/microcontroller/nxp_imx6ull/`` 目录下，打开 ``pin.py`` 文件，它里面是定义了底层接口的引脚：
+
+定义引脚的方式如下：
+
+.. code:: bash
+
+    Pin(([GPIO组号 - 1], [GPIO引脚号]))
+
+比如RGB
+LED的引脚分别为GPIO1_IO4、GPIO4_IO20、GPIO4_IO19，蜂鸣器的引脚是GPIO1_IO19，按键的引脚是GPIO5_IO1，那么他们的定义就如下面的代码所示：
+
+.. code:: py
+
+    R_LED_PIN = Pin((0, 4))    # GPIO1_IO4
+    G_LED_PIN = Pin((3, 20))    # GPIO4_IO20
+    B_LED_PIN = Pin((3, 19))    # GPIO4_IO19
+
+    BEEP_PIN = Pin((0, 19))    # GPIO1_IO19
+
+    BUTTON_PIN = Pin((4, 1))    # GPIO5_IO1
+
+定义好引脚的gpio后，我们可以把它写到board模块中，然后就可以从board模块导入这些引脚，直接编辑 ``Adafruit_Blinka/src/adafruit_blinka/board/embedfire_imx6ull.py`` 文件即可，在里面添加以下代码：
+
+.. code:: py
+
+    R_LED = pin.R_LED_PIN
+    G_LED = pin.G_LED_PIN
+    B_LED = pin.B_LED_PIN
+
+    BEEP = pin.BEEP_PIN
+
+    BUTTON = pin.BUTTON_PIN
+
+如此一来在使用的时候就可以这样使用：
+
+.. code:: py
+
+    from board import R_LED, G_LED, B_LED
+
+    from board import BEEP
+
+    from board import BUTTON
+
+就可以导入对应的GPIO，非常方便
+
+如果你想要修改其他GPIO的话，一样是这样子操作，定义底层的pin，然后直接导入使用即可。
+
+**补充说明：野火已经提供控制蜂鸣器、RGB
+LED灯以及按键的GPIO接口，所以大家不需要去修改**
+
+安装库
+------
+
+如果你修改了GPIO的pin引脚，那么需要重新安装这些库，安装的步骤如下：
+
+-  进入Adafruit_CircuitPython_SSD1306目录下，安装对应的库：
+
+.. code:: bash
+
+    cd Adafruit_CircuitPython_SSD1306 
+
+    sudo python setup.py install
+
+-  然后进入Adafruit_Blinka目录下安装对应的库：
+
+.. code:: bash
+
+    cd Adafruit_Blinka
+
+    sudo python setup.py install
+
+-  最后进入Adafruit_Python_PlatformDetect目录下安装对应的库：
+
+.. code:: bash
+
+    cd Adafruit_Python_PlatformDetect
+
+    sudo python setup.py install
+
+编写控制GPIO的代码
+------------------
+
+野火提供的GPIO应用代码有3个，分别控制RGB
+LED、蜂鸣器、按键，核心的依赖库是digitalio，它里面提供了GPIO初始化的方法、控制GPIO方向（如配置为输入方向、配置为输出方向）、设置GPIO的电平、读取GPIO的电平等。
+
+注意：这里控制RGB LED需要将设备树插件的LED关闭（通过fire-config修改即可），否则会出现LED设备被内核占用导致设备正忙的错误。
+
+python控制RGB LED
+~~~~~~~~~~~~~~~~~
+
+控制RGB LED的代码可以从
+https://github.com/Embedfire-pythonlib/Adafruit_CircuitPython_SSD1306/blob/master/examples/rgb_led.py
+得到。
+
+代码如下：
+
+.. code:: py
+
+    import time
+    import digitalio
+    from board import R_LED, G_LED, B_LED
+
+    rled = digitalio.DigitalInOut(R_LED)
+    gled = digitalio.DigitalInOut(G_LED)
+    bled = digitalio.DigitalInOut(B_LED)
+
+    rled.switch_to_output()     
+    gled.switch_to_output()
+    bled.switch_to_output()
+
+    while True:
+        rled.value = 0
+        time.sleep(1)
+        rled.value = 1
+        gled.value = 0
+        time.sleep(1)
+        gled.value = 1
+        bled.value = 0
+        time.sleep(1)
+        bled.value = 1
+        time.sleep(1)
+
+代码简单解析：
+
+-  通过 ``digitalio.DigitalInOut`` 初始化一个pin对象
+
+-  使用 ``switch_to_output`` 方法选择为输出方向，如果是输入方向则使用 ``switch_to_input`` 方法。
+
+-  直接设置 ``value`` ，输出高低电平。
+
+python控制蜂鸣器
+~~~~~~~~~~~~~~~~
+
+控制蜂鸣器的代码可以从
+https://github.com/Embedfire-pythonlib/Adafruit_CircuitPython_SSD1306/blob/master/examples/beep_onoff.py
+得到。
+
+代码如下：
+
+.. code:: py
+
+    import time
+    import digitalio
+    from board import BEEP
+
+    beep = digitalio.DigitalInOut(BEEP)
+    beep.switch_to_output()
+
+    while True:
+        beep.value = 0
+        time.sleep(1)
+        beep.value = 1
+        time.sleep(1)
+
+python控制按键
+~~~~~~~~~~~~~~
+
+控制按键的代码可以从
+https://github.com/Embedfire-pythonlib/Adafruit_CircuitPython_SSD1306/blob/master/examples/button.py
+得到。
+
+按键是作为输入的方向，在应用层读取gpio的电平，当按键被按下是，终端打印对应的信息。
+
+代码如下：
+
+.. code:: py
+
+    import time
+    import digitalio
+    from board import BUTTON
+
+    button = digitalio.DigitalInOut(BUTTON)
+    button.switch_to_input()
+
+    print("please touch the button!")
+
+    while True:
+        if (button.value):
+            print("the button is pressed...")
+            time.sleep(1)
+
+实验现象
+--------
+
+代码的实验现象比较简单，直接运行测试即可，运行的方式如下（必须有python环境）:
+
+.. code:: bash
+
+    python [xxx.py]
+
diff --git a/documentation/linux_env/python_serial.rst b/documentation/linux_env/python_serial.rst
new file mode 100644
index 0000000000000000000000000000000000000000..ed2ae2a86d1d5a0b86728ab2b178f1568b7d5f7f
--- /dev/null
+++ b/documentation/linux_env/python_serial.rst
@@ -0,0 +1,263 @@
+在Debian中通过Python控制串口
+============================
+
+-  平台：野火imx6ull开发板
+-  系统：Debian
+-  目标Python版本：Python3.7
+
+    注意：此处的操作是在野火imx6ull开发板上（运行的是Debian系统），而非虚拟机。
+
+更新
+----
+
+其实在很多Debian系统中都预装了Python3或者Python2，但是野火提供的镜像是并未预装Python3的，我们可以手动安装，为了确保我们的版本是最新版本，让我们使用apt命令更新本地apt包索引和升级系统：
+
+.. code:: bash
+
+    sudo apt-get update
+    sudo apt-get -y upgrade
+
+-y 标志将确认我们同意所有要安装的项目。
+
+手动安装Python3
+---------------
+
+.. code:: bash
+
+    sudo apt-get -y install python3
+
+可以看到Python3有很多依赖的deb包：
+
+::
+
+    Reading package lists... Done
+    Building dependency tree
+    Reading state information... Done
+    The following additional packages will be installed:
+      libmpdec2 libpython3-stdlib libpython3.7-minimal libpython3.7-stdlib
+      python3-minimal python3.7 python3.7-minimal
+    Suggested packages:
+      python3-doc python3-tk python3-venv python3.7-venv python3.7-doc binutils
+      binfmt-support
+    The following NEW packages will be installed:
+      libmpdec2 libpython3-stdlib libpython3.7-minimal libpython3.7-stdlib python3
+      python3-minimal python3.7 python3.7-minimal
+    0 upgraded, 8 newly installed, 0 to remove and 0 not upgraded.
+    Need to get 4224 kB of archives.
+    After this operation, 19.6 MB of additional disk space will be used.
+
+当然啦，这些依赖的deb包是不需要我们手动安装的，Debian会自动安装。
+
+在安装完成后，校验是否安装成功：
+
+.. code:: bash
+
+     python3 -V
+
+当出现以下内容时表示Python3安装成功：
+
+.. code:: bash
+
+    Python 3.7.3
+
+设置Debian系统的默认Python版本
+------------------------------
+
+如果你是运行以下命令校验Python的版本：
+
+.. code:: bash
+
+    python -V
+
+并且当你的系统存在Python2的话，那么版本可能就是 ``Python 2.7.16`` ，那么与我们想要安装的Python3版本并不符合，因此我们要设置Python3位默认版本：
+
+.. code:: bash
+
+    cd /usr/bin
+    sudo rm python
+    sudo ln -s python3.7 python
+    cd ~
+
+再次校验Python版本时，发现系统默认的Python版本就是python3.7了：
+
+.. code:: bash
+
+    python3 -V
+
+    # 版本
+    Python 3.7.3
+
+安装pip包管理工具
+-----------------
+
+接下来我们就讲解怎么去安装对应的包。
+
+pip是一个Python的包管理系统，允许用户安装Python包。使用pip可以从Python包索引（PyPI）和其他存储库安装对应的包。
+
+我们首先还是更新一下apt的索引：
+
+.. code:: bash
+
+    sudo apt-get update
+
+然后安装python3-pip：
+
+.. code:: bash
+
+    sudo apt-get -y install python3-pip
+
+在安装完成后验证一下：
+
+.. code:: bash
+
+    pip3 --version
+
+    # 出现以下内容表示安装成功
+    pip 18.1 from /usr/lib/python3/dist-packages/pip (python 3.7)
+
+安装pyserial模块
+----------------
+
+使用pip3安装 ``pyserial模块`` ，它封装了对串口的访问，提供了在Windows，OSX，Linux，BSD（任何POSIX兼容系统）上运行的Python的后端模块，它会选择合适的串口进行数据的输入输出操作，使得我们通过Python操作串口变得非常简单。
+
+.. code:: bash
+
+    pip3 install -i https://pypi.tuna.tsinghua.edu.cn/simple pyserial
+
+pyserial模块介绍
+----------------
+
+本章仅简单介绍一下模块的类，更多信息大家可以去看官方的介绍： https://pythonhosted.org/pyserial/
+
+本章仅简单介绍一下pyserial模块的类 ``class serial.Serial`` ，这是我们写代码要用到的。
+
+初始化参数：
+~~~~~~~~~~~~
+
+.. code:: py
+
+    __init__(port=None, baudrate=9600, bytesize=EIGHTBITS, parity=PARITY_NONE, stopbits=STOPBITS_ONE, timeout=None, xonxoff=False, rtscts=False, write_timeout=None, dsrdtr=False, inter_byte_timeout=None)
+
+参数说明： 
+
+- port：指定端口设备名称，取决于操作系统，例如在Linux上为/dev/ttyXXX，在Windows上为COMXXX。
+
+- baudrate：波特率，可以是以下标准值之一：50、75、110、134、150、200、300、600、1200、1800、2400、4800、9600、19200、38400、57600、115200等等。
+
+- bytesize：数据位数。可取的值：5位，6位，7位，8位。 
+
+- parity：启用奇偶校验。可取的值：PARITY_NONE，PARITY_EVEN，PARITY_ODD，PARITY_MARK，PARITY_SPACE。
+
+- stopbits：停止位数。可取的值：STOPBITS_ONE，STOPBITS_ONE_POINT_FIVE，STOPBITS_TWO。
+
+- timeout：设置读取超时值，是浮点类型，表示当没有数据时读取阻塞的时间；如果设置为None，则永远等待，直到接收到请求的字节数；如果设置为0，则表不阻塞，在任何情况下立即返回读取到的数据内容。
+
+- xonxoff：启用软件流控制。 - rtscts：启用硬件（RTS / CTS）流控制。 
+
+- dsrdtr：启用硬件（DSR / DTR）流控制。 
+
+- write_timeout：设置写超时值，默认情况下write()处于阻塞状态。 
+
+- inter_byte_timeout：字符间超时，无则禁用（默认）。
+
+
+    ps：这些参数基本都有默认值，但port是必须填写的。
+
+
+读数据
+~~~~~~
+
+从串口读取指定长度的字节数据，读取数据时根据初始化参数中指定的超时时间进行判断是否超时。
+
+.. code:: py
+
+    read(size=1)
+
+参数： - size：要读取的字节数。 - 返回：从端口读取到的数据
+
+写数据
+~~~~~~
+
+将指定的数据写入串口，但Unicode字符串必须经过编码，例如 ``'hello'.encode('utf-8')`` 。
+
+参数： - data：要写入的数据。 -
+返回：写入的字节数，如果为端口配置了写超时并且超过了时间，则抛出异常SerialTimeoutException。
+
+编写例程代码
+------------
+
+简单了解之后可以直接使用它，比如我们创建一个 ``serial_demo.py`` 文件，并编写相关的代码，代码文件可以在 https://github.com/Embedfire/embed_linux_tutorial/blob/master/base_code/linux_env/serial_demo.py 路径下得到，具体代码如下：
+
+.. code:: py
+
+    import serial
+    from time import sleep
+
+    def recv(serial):
+        while True:
+            data = serial.read_all()
+            if data != b'' :
+                break
+            
+        return data.decode()
+
+
+    if __name__ == '__main__':
+        serial = serial.Serial('/dev/ttymxc2', 115200)  # /dev/ttymxc2
+        if serial.isOpen() :
+            print("open success")
+        else :
+            print("open failed")
+
+        while True:
+            data =recv(serial)
+            if data != '' :
+                print("receive:",data)
+                serial.write(data.encode()) # 数据回显
+
+实验
+----
+
+1. 首先使用USB转串口接上开发板的USART3，如果没有USB转串口可以在野火官方淘宝店上购买: `野火
+   USB转TTL
+   CH340模块 <https://detail.tmall.com/item.htm?spm=a230r.1.14.6.bc3e6fffIjse95&id=600554874281&cm_id=140105335569ed55e27b&abbucket=9>`__ 。
+
+.. figure:: media/python_serial001.png
+   :alt: python_serial001.png
+
+   python_serial001.png
+
+2. 然后在 ``fire-config`` 中打开串口3：
+
+.. code:: bash
+
+    sudo fire-config
+
+.. figure:: media/python_serial002.png
+   :alt: python_serial002.png
+
+   python_serial002.png
+
+3. 重启开发板。
+
+4. 查看 ``/dev`` 目录下是否存在串口3设备 ``ttymxc2``
+
+.. code:: bash
+
+    ls /dev | grep ttymxc2
+
+5. 打开野火串口调试助手。
+
+6. 在Debian系统中运行 ``serial_demo.py`` 文件
+
+.. code:: bash
+
+    python serial_demo.py
+
+7. 程序运行的现象如下：
+
+.. figure:: media/python_serial003.png
+   :alt: python_serial003.png
+
+   python_serial003.png
+
diff --git a/documentation/linux_env/python_ssd1306.rst b/documentation/linux_env/python_ssd1306.rst
new file mode 100644
index 0000000000000000000000000000000000000000..83eccacc6253d6ecce093d62427762fd294c98f3
--- /dev/null
+++ b/documentation/linux_env/python_ssd1306.rst
@@ -0,0 +1,526 @@
+Debian搭建Python控制OLED开发环境
+================================
+
+-  平台：野火imx6ull开发板
+-  系统：Debian
+-  Python版本：Python3.7
+
+更新
+----
+
+其实在很多Debian系统中都预装了Python3或者Python2，但是野火提供的镜像是并未预装Python3的，我们可以手动安装，为了确保我们的版本是最新版本，让我们使用apt命令更新本地apt包索引和升级系统：
+
+.. code:: bash
+
+    sudo apt-get update
+    sudo apt-get -y upgrade
+
+-y 标志将确认我们同意所有要安装的项目。
+
+手动安装Python3
+---------------
+
+.. code:: bash
+
+    sudo apt-get -y install python3
+
+在安装完成后，校验是否安装成功：
+
+.. code:: bash
+
+     python3 -V
+
+当出现以下内容或更高版本时表示Python3安装成功：
+
+.. code:: bash
+
+    Python 3.7.3
+
+设置Debian系统的默认Python版本
+------------------------------
+
+如果你是运行以下命令校验Python的版本：
+
+.. code:: bash
+
+    python -V
+
+并且当你的系统存在Python2的话，那么版本可能就是 ``Python 2.7.16`` ，那么与我们想要安装的Python3版本并不符合，因此我们要设置Python3位默认版本：
+
+.. code:: bash
+
+    #先删除原有的软链接
+    sudo rm /usr/bin/python
+    sudo ln -s /usr/bin/python3 /usr/bin/python
+
+再次校验Python版本时，发现系统默认的Python版本就是python3了：
+
+.. code:: bash
+
+    python3 -V
+
+    # 版本
+    Python 3.7.3
+
+
+手动安装pip
+---------------
+使用python时常常需要用到pip工具，可以使用如下命令安装：
+
+.. code:: bash
+
+    sudo apt install python3-pip
+
+    #安装完成后使用如下命令查看版本
+    python3 -m pip -V
+
+
+安装Python相关的依赖库
+----------------------
+
+-  python3-smbus：主要是是读写i2c总线相关操作的依赖库
+-  python3-setuptools：Python的setupt工具。
+-  libjpeg-dev、zlib1g-dev：图片相关的依赖库，因为本章的例程中需要依赖图片相关的内容。
+-  Pillow：Pillow 是一个对 PIL 友好的分支，作者是 Alex Clark。而 PIL
+   是一个 Python 图像处理库。
+
+.. code:: bash
+
+    sudo apt-get install -y python3-smbus
+
+    sudo apt-get install -y python3-setuptools
+
+    sudo apt-get install -y libjpeg-dev zlib1g-dev
+
+安装 Pillow：
+
+.. code:: bash
+
+    python3 -m pip install -i https://pypi.tuna.tsinghua.edu.cn/simple Pillow
+
+安装野火提供的gpiod库
+---------------------
+
+因为本教程中的python代码会依赖gpiod模块，但是由于直接通过pip安装会导致很多问题，因此野火特地制作了ebf-gpiod软件包，解决了很多依赖及各种，我们直接安装即可。
+
+.. code:: bash
+
+    sudo apt-get install -y ebf-gpiod
+
+安装git
+-------
+
+我们需要从github或者gitee拉取对应的代码，所以必须使用git去拉取，当然啦，这些代码体积非常小，拉取是非常快的。
+
+.. code:: bash
+
+    sudo apt-get install -y git
+
+安装i2c-tools
+-------------
+
+因为我们用到了OLED中的i2c作为通信接口，因此安装一个i2c工具，以便检查校验i2c是否正常工作。
+
+.. code:: bash
+
+    sudo apt-get install -y i2c-tools
+
+拉取代码
+--------
+
+**说明：无论从github还是gitee拉取代码，都是一样的，选择其中一处拉取即可。**
+
+Adafruit_CircuitPython_SSD1306是一个开源的库代码，里面含有SSD1306（野火的OLED
+屏幕所使用的型号）的Python例子。
+
+-  从gitee拉取：
+
+.. code:: bash
+
+    git clone https://gitee.com/Embedfire-pythonlib/Adafruit_CircuitPython_SSD1306.git
+
+Adafruit_Blinka是与硬件打交道的，根据硬件信息选择对应的库。
+
+.. code:: bash
+
+    git clone https://gitee.com/Embedfire-pythonlib/Adafruit_Blinka.git
+
+Adafruit_Python_PlatformDetect是平台层依赖，它主要是配置芯片及开发板接口的。
+
+.. code:: bash
+
+    git clone https://gitee.com/Embedfire-pythonlib/Adafruit_Python_PlatformDetect.git
+
+-  从github拉取：
+
+.. code:: bash
+
+    git clone https://github.com/Embedfire-pythonlib/Adafruit_CircuitPython_SSD1306.git
+
+.. code:: bash
+
+    git clone https://github.com/Embedfire-pythonlib/Adafruit_Blinka.git
+
+.. code:: bash
+
+    git clone https://github.com/Embedfire-pythonlib/Adafruit_Python_PlatformDetect.git
+
+拉取完成后可以看到当前文件夹存在3个文件夹：
+
+.. code:: bash
+
+    ➜ ls
+    Adafruit_Blinka  Adafruit_CircuitPython_SSD1306  Adafruit_Python_PlatformDetect
+
+进入Adafruit_CircuitPython_SSD1306目录下，安装对应的库：
+
+.. code:: bash
+
+    cd Adafruit_CircuitPython_SSD1306 
+
+    sudo python setup.py install
+
+然后进入Adafruit_Blinka目录下安装对应的库：
+
+.. code:: bash
+
+    cd Adafruit_Blinka
+
+    sudo python setup.py install
+
+最后进入Adafruit_Python_PlatformDetect目录下安装对应的库：
+
+.. code:: bash
+
+    cd Adafruit_Python_PlatformDetect
+
+    sudo python setup.py install
+
+**注意，一定要按照顺序去执行这些安装的操作。**
+
+开发板接线
+----------
+
+将野火OLED模块与开发板接好，接线IO如表所示：
+
++-------------+-----------------+
+| OLED 屏幕   | imx6ull开发板   |
++=============+=================+
+| VCC         | 3.3V            |
++-------------+-----------------+
+| GND         | GND             |
++-------------+-----------------+
+| SCL         | IO1_28          |
++-------------+-----------------+
+| SDA         | IO1_29          |
++-------------+-----------------+
+
+可以参考野火硬件原理图进行接线： https://ebf-6ull-hardware.readthedocs.io/zh/latest/
+
+打开I2C总线
+-----------
+
+在fire-config打开I2C_1总线，目前作者使用的是最新的fire-config工具，如果你的不是最新的，也是无所谓的，因为该总线是默认打开的。
+
+.. figure:: media/python_ssd1306_001.png
+   :alt: python_ssd1306_001.png
+
+   python_ssd1306_001.png
+
+使用I2C工具
+-----------
+
+在打开总线后，会提示需要重启，那么在重启后，使用i2c工具查看系统是否可以找到OLED
+屏幕的地址，命令如下：
+
+.. code:: bash
+
+    i2cdetect -y 0
+
+如果出现以下结果，说明开发板与OLED 屏幕的i2c总线通信是正常的。
+
+.. figure:: media/python_ssd1306_002.png
+   :alt: python_ssd1306_002.png
+
+   python_ssd1306_002.png
+
+使用示例
+--------
+
+我们可以进入刚刚从github、gitee拉取的代码中运行它本身的demo，进入 ``Adafruit_CircuitPython_SSD1306/examples`` 目录下：
+
+::
+
+    cd Adafruit_CircuitPython_SSD1306/examples
+
+运行ssd1306_stats.py这个demo，它会将系统的IP地址，CPU的使用情况、内存信息、磁盘信息等显示到OLED
+屏幕中。
+
+.. code:: bash
+
+    python ssd1306_stats.py
+
+可以看到此时的OLED 屏幕已经出现了一些与系统状态相关的信息：
+
+.. figure:: media/python_ssd1306_003.png
+   :alt: python_ssd1306_003.png
+
+   python_ssd1306_003.png
+
+源代码也是比较简单的：
+
+.. code:: python
+
+    import time
+    import subprocess
+
+    from board import SCL, SDA, DC, RST, SS0
+    import busio
+    import board
+    import digitalio
+    from PIL import Image, ImageDraw, ImageFont
+    import adafruit_ssd1306
+
+
+    # Create the SSD1306 OLED class.
+    # The first two parameters are the pixel width and pixel height.  Change these
+    # to the right size for your display!
+
+    # Create the I2C interface.
+    i2c = busio.I2C(SCL, SDA)
+    disp = adafruit_ssd1306.SSD1306_I2C(128, 32, i2c)
+
+    # Create the SPI interface.
+    # spi = board.SPI()
+    # oled_cs = digitalio.DigitalInOut(SS0)
+    # oled_dc = digitalio.DigitalInOut(DC)
+    # oled_reset = None
+    # disp = adafruit_ssd1306.SSD1306_SPI(128, 64, spi, oled_dc, oled_reset, oled_cs)
+
+    # Clear display.
+    disp.fill(0)
+    disp.show()
+
+    # Create blank image for drawing.
+    # Make sure to create image with mode '1' for 1-bit color.
+    width = disp.width
+    height = disp.height
+    image = Image.new('1', (width, height))
+
+    # Get drawing object to draw on image.
+    draw = ImageDraw.Draw(image)
+
+    # Draw a black filled box to clear the image.
+    draw.rectangle((0, 0, width, height), outline=0, fill=0)
+
+    # Draw some shapes.
+    # First define some constants to allow easy resizing of shapes.
+    padding = -2
+    top = padding
+    bottom = height-padding
+    # Move left to right keeping track of the current x position for drawing shapes.
+    x = 0
+
+
+    # Load default font.
+    font = ImageFont.load_default()
+
+    # Alternatively load a TTF font.  Make sure the .ttf font file is in the
+    # same directory as the python script!
+    # Some other nice fonts to try: http://www.dafont.com/bitmap.php
+    #font = ImageFont.truetype('/usr/share/fonts/truetype/dejavu/DejaVuSans.ttf', 9)
+
+    while True:
+
+        # Draw a black filled box to clear the image.
+        draw.rectangle((0, 0, width, height), outline=0, fill=0)
+
+        # Shell scripts for system monitoring from here:
+        # https://unix.stackexchange.com/questions/119126/command-to-display-memory-usage-disk-usage-and-cpu-load
+        cmd = "hostname -I | cut -d\' \' -f1"
+        IP = subprocess.check_output(cmd, shell=True).decode("utf-8")
+        cmd = "top -bn1 | grep load | awk '{printf \"CPU Load: %.2f\", $(NF-2)}'"
+        CPU = subprocess.check_output(cmd, shell=True).decode("utf-8")
+        cmd = "free -m | awk 'NR==2{printf \"Mem: %s/%s MB  %.2f%%\", $3,$2,$3*100/$2 }'"
+        MemUsage = subprocess.check_output(cmd, shell=True).decode("utf-8")
+        cmd = "df -h | awk '$NF==\"/\"{printf \"Disk: %d/%d GB  %s\", $3,$2,$5}'"
+        Disk = subprocess.check_output(cmd, shell=True).decode("utf-8")
+
+        # Write four lines of text.
+
+        draw.text((x, top+0), "IP: "+IP, font=font, fill=255)
+        draw.text((x, top+8), CPU, font=font, fill=255)
+        draw.text((x, top+16), MemUsage, font=font, fill=255)
+        draw.text((x, top+25), Disk, font=font, fill=255)
+
+        # Display image.
+        disp.image(image)
+        disp.show()
+        time.sleep(.1)
+
+我们也可以显示一个很好看的图案：
+
+.. code:: bash
+
+    python ssd1306_pillow_images.py 
+
+效果如下：
+
+.. figure:: media/python_ssd1306_004.png
+   :alt: python_ssd1306_004.png
+
+   python_ssd1306_004.png
+
+修改平台层
+----------
+
+如果我想用其他IO怎么办呢，其实非常简单，直接在 ``Adafruit_Blinka/src/adafruit_blinka/microcontroller/nxp_imx6ull/`` 路径下的 ``pin.py`` 文件修改对应的引脚，并且打开对应的I2C总线即可，当然我们不建议修改其他引脚。
+
+可以支持以下两种方式：
+
+-  方式1：
+
+.. code:: python
+
+    I2C1_SCL = Pin((0, 28)) # GPIO1_IO28
+    I2C1_SDA = Pin((0, 29)) # GPIO1_IO29
+
+-  方式2：
+
+.. code:: python
+
+    I2C2_SCL = Pin(0) # GPIO1_IO0
+    I2C2_SDA = Pin(1) # GPIO1_IO1
+
+那么这种引脚是怎么计算的呢？公式如下：
+
+.. code:: bash
+
+    数字 = (IO组号 - 1)  * 32 + 8
+
+比如假设需要打开 ``IO4_15`` 这个IO，那么通过计算可以知道数字是 104：
+
+.. code:: bash
+
+    数字 = (4 - 1) * 32 + 8
+
+那么在 ``pin.py`` 文件就可以这样子配置：
+
+.. code:: py
+
+    I2C1_SCL = Pin((3, 15)) # IO4_15
+
+    # 或者：
+
+    I2C1_SCL = Pin(104) # IO4_15
+
+使用SPI方式控制OLED屏幕
+-----------------------
+
+如果你没有i2c接口的屏幕，那么也可以在这个库中使用SPI的方式去控制OLED屏幕，修改也是非常简单的，步骤如下：
+
+1. 将野火OLED屏幕与开发板连接，接线表如下：
+
++----------------------------+-----------------+
+| OLED 屏幕                  | imx6ull开发板   |
++============================+=================+
+| VCC                        | 3.3V            |
++----------------------------+-----------------+
+| GND                        | GND             |
++----------------------------+-----------------+
+| CLK                        | IO1_21          |
++----------------------------+-----------------+
+| MISO（如果没有则不用接）   | IO1_23          |
++----------------------------+-----------------+
+| MOSI                       | IO1_22          |
++----------------------------+-----------------+
+| CS                         | IO1_20          |
++----------------------------+-----------------+
+| DC                         | IO1_18          |
++----------------------------+-----------------+
+
+可以参考野火硬件原理图进行接线： https://ebf-6ull-hardware.readthedocs.io/zh/latest/
+
+1. 打开SPI总线与SPI设备，比如我们的开发板引出了SPI3接口，那么就打开它：
+
+.. figure:: media/python_ssd1306_005.png
+   :alt: python_ssd1306_005.png
+
+   python_ssd1306_005.png
+
+3. 然后修改 ``/boot/uEnv.txt`` 文件，将 ``dtoverlay=/lib/firmware/imx-fire-spidev-overlay.dtbo`` 设备树插件打开（将前面的“#”去掉），其他插件打不打开无所谓，但是 ``dtoverlay=/lib/firmware/imx-fire-uart2-overlay.dtbo`` 串口2设备树插件不能打开。
+
+.. code:: bash
+
+
+    #overlay_start
+
+    # dtoverlay=/lib/firmware/imx-fire-i2c1-overlay.dtbo
+    #dtoverlay=/lib/firmware/imx-fire-i2c2-overlay.dtbo
+    #dtoverlay=/lib/firmware/imx-fire-74hc595-overlay.dtbo
+    #dtoverlay=/lib/firmware/imx-fire-485r1-overlay.dtbo
+    #dtoverlay=/lib/firmware/imx-fire-485r2-overlay.dtbo
+    #dtoverlay=/lib/firmware/imx-fire-adc1-overlay.dtbo
+    #dtoverlay=/lib/firmware/imx-fire-btwifi-overlay.dtbo
+    #dtoverlay=/lib/firmware/imx-fire-cam-overlay.dtbo
+    #dtoverlay=/lib/firmware/imx-fire-can1-overlay.dtbo
+    #dtoverlay=/lib/firmware/imx-fire-can2-overlay.dtbo
+    #dtoverlay=/lib/firmware/imx-fire-dht11-overlay.dtbo
+    dtoverlay=/lib/firmware/imx-fire-ecspi3-overlay.dtbo
+    #dtoverlay=/lib/firmware/imx-fire-hdmi-overlay.dtbo
+    #dtoverlay=/lib/firmware/imx-fire-key-overlay.dtbo
+    #dtoverlay=/lib/firmware/imx-fire-lcd5-overlay.dtbo
+    #dtoverlay=/lib/firmware/imx-fire-lcd43-overlay.dtbo
+    #dtoverlay=/lib/firmware/imx-fire-led-overlay.dtbo
+    #dtoverlay=/lib/firmware/imx-fire-sound-overlay.dtbo
+    dtoverlay=/lib/firmware/imx-fire-spidev-overlay.dtbo
+    #dtoverlay=/lib/firmware/imx-fire-uart2-overlay.dtbo
+    #dtoverlay=/lib/firmware/imx-fire-uart3-overlay.dtbo
+
+    #overlay_end
+
+3. 重启开发板即可。
+
+4. 通过 ``ls /dev`` 命令可以看到已经有了spi3设备了，名字叫 ``spidev2.0`` ，此时我们可以使用SPI3总线了。
+
+5. 修改例程中的接口对象，打开具体的某个例程，比如 ``Adafruit_CircuitPython_SSD1306/examples/ssd1306_stats.py`` ，将该文件的i2c接口对象注释掉，打开spi接口对象，具体代码如下：
+
+.. code:: python
+
+    # Create the I2C interface.    注释掉这两行
+    # i2c = busio.I2C(SCL, SDA)
+    # disp = adafruit_ssd1306.SSD1306_I2C(128, 32, i2c)
+
+    # Create the SPI interface.     打开spi设备对象
+    spi = board.SPI()
+    oled_cs = digitalio.DigitalInOut(SS0)
+    oled_dc = digitalio.DigitalInOut(DC)
+    oled_reset = None
+    disp = adafruit_ssd1306.SSD1306_SPI(128, 64, spi, oled_dc, oled_reset, oled_cs)
+
+同理其他例程也是这样子操作。
+
+6. 运行例程：运行ssd1306_stats.py这个demo，它会将系统的IP地址，CPU的使用情况、内存信息、磁盘信息等显示到OLED
+   屏幕中。
+
+.. code:: bash
+
+    python ssd1306_stats.py
+
+可以看到此时的OLED 屏幕已经出现了一些与系统状态相关的信息：
+
+7. 如果你是其他接口，可以在 ``Adafruit_Blinka/src/adafruit_blinka/microcontroller/nxp_imx6ull/`` 路径下的 ``pin.py`` 文件修改对应的引脚，野火不保证你修改的引脚是正确的，如非特别需要，请直接使用野火的配置:
+
+.. code:: python
+
+    ECSPI3_MISO = Pin(23) # IO1_23
+    ECSPI3_MOSI = Pin(22) # IO1_22 
+    ECSPI3_SCLK = Pin(21) # IO1_21
+    ECSPI3_SS0 = Pin(20)  # IO1_20 
+    ECSPI3_DC = Pin(18) # IO1_18
+    ECSPI3_RST = Pin(17)  # IO1_17
+
+    # ordered as spiId, sckId, mosiId, misoId
+    spiPorts = ( (2, ECSPI3_SCLK, ECSPI3_MOSI, ECSPI3_MISO), )
+
+至此，本章的教程也完结了，因为是开源库，大家可以自行去深入研究，本章的目的是告诉大家可以通过Python控制硬件。
diff --git a/documentation/linux_env/qt_cross_compiling.rst b/documentation/linux_env/qt_cross_compiling.rst
new file mode 100644
index 0000000000000000000000000000000000000000..9e4414fd44b51bae94aeb378b28c058d7af06a93
--- /dev/null
+++ b/documentation/linux_env/qt_cross_compiling.rst
@@ -0,0 +1,1325 @@
+Qt交叉编译环境搭建
+==================
+
+主机：Ubuntu18.04
+
+    本交叉编译环境使用5.14.1版本的Qt源码，编译出来的Qt
+    App可以直接运行在野火发布的 Debian 系统上。
+
+安装arm-linux-gnueabihf-gcc 8.3.0
+---------------------------------
+
+首先安装教程编译器：arm-linux-gnueabihf-gcc 8.3.0
+版本，为什么要选择那么高的版本呢，因为作者测试时使用4.9.3版本编译器编译出来的Qt
+App在Debian系统上运行时会报一个错误：
+
+.. code:: bash
+
+    relocation error: /home/debian/qt-app/abc: symbol _ZTVN10__cxxabiv120__si_class_type_infoE version Qt_5 not defined in file libQt5Core.so.5 with link time reference
+
+经过Google搜索答案，大致是说编译器版本不同导致的错误，我查看了Debian
+系统中的 libQt5Core.so.5.11.3
+库的信息，发现它的编译器版本是比较高的，所以为了一致性，我也使用了
+arm-linux-gnueabihf-gcc 8.3.0 版本的编译器。
+
+.. code:: bash
+
+    # strings libQt5Core.so.5.11.3 |grep GCC
+
+    GCC_3.4
+    GCC_3.5
+    Qt 5.11.3 (arm-little_endian-ilp32-eabi-hardfloat shared (dynamic) release build; by GCC 8.3.0)
+    This is the QtCore library version Qt 5.11.3 (arm-little_endian-ilp32-eabi-hardfloat shared (dynamic) release build; by GCC 8.3.0)
+
+**野火提供 build-gcc.sh 脚本一键安装 arm-linux-gnueabihf-gcc 8.3.0
+版本编译器** ：
+
+build-gcc.sh 脚本内容如下：
+
+.. code:: bash
+
+    #!/bin/sh
+
+    HOST=arm-linux-gnueabihf
+    SCRIPT_PATH=$(pwd)
+
+    #修改源码包解压后的名称
+    MAJOR_NAME=arm-linux-gnueabihf
+
+    #修改需要下载的源码版本前缀和后缀
+    OPENSRC_VER_PREFIX=8.3
+    OPENSRC_VER_SUFFIX=.0
+
+    PACKAGE_NAME=${MAJOR_NAME}-${OPENSRC_VER_PREFIX}${OPENSRC_VER_SUFFIX}
+
+    #定义压缩包名称
+    COMPRESS_PACKAGE=gcc-arm-8.3-2019.03-x86_64-arm-linux-gnueabihf.tar.xz
+
+    #定义编译后安装--生成的文件,文件夹位置路径
+    INSTALL_PATH=/opt/${PACKAGE_NAME}
+
+    #无需修改--下载地址
+    DOWNLOAD_LINK=https://developer.arm.com/-/media/Files/downloads/gnu-a/8.3-2019.03/binrel/${COMPRESS_PACKAGE}
+
+    #下载源码包
+    do_download_src () {
+       echo "\033[1;33mstart download ${COMPRESS_PACKAGE}...\033[0m"
+       if [ ! -d "${COMPRESS_PACKAGE}" ];then
+          wget -c ${DOWNLOAD_LINK}
+       fi
+       echo "\033[1;33mdone...\033[0m"
+    }
+
+    #解压源码包
+    do_tar_package () {
+       echo "\033[1;33mstart unpacking the ${PACKAGE_NAME} package ...\033[0m"
+       
+       mkdir -p ${INSTALL_PATH}
+
+       if [ ! -d "${PACKAGE_NAME}" ];then
+          tar -xf ${COMPRESS_PACKAGE} -C ${INSTALL_PATH}
+       fi
+       echo "\033[1;33mdone...\033[0m"
+    }
+
+    #删除下载的文件
+    do_delete_file () {
+       cd ${SCRIPT_PATH}
+       if [ -f "${PACKAGE_NAME}" ];then
+          sudo rm -f ${PACKAGE_NAME}
+       fi
+    }
+
+    do_download_src
+    do_tar_package
+    # do_delete_file
+
+    exit $?
+
+
+整个脚本的核心就是使用wget命令将arm-linux-gnueabihf-gcc
+v8.3.0的文件下载到本地，然后通过tar解压到指定的安装目录（/opt/${PACKAGE_NAME}，实际上就是/opt/gcc-arm-linux-gnueabihf-8.3.0目录下）。
+
+我们直接运行脚本即可下载并安装arm-linux-gnueabihf-gcc 8.3.0
+版本的交叉编译器，后续的编译都是要该编译器进行。
+
+**执行脚本的过程：**
+
+.. code:: bash
+
+    # sudo ./build-gcc.sh
+
+    start download gcc-arm-8.3-2019.03-x86_64-arm-linux-gnueabihf.tar.xz...
+    --2020-03-18 11:04:11--  https://developer.arm.com/-/media/Files/downloads/gnu-a/8.3-2019.03/binrel/gcc-arm-8.3-2019.03-x86_64-arm-linux-gnueabihf.tar.xz
+    正在解析主机 developer.arm.com (developer.arm.com)... 23.41.45.203
+    正在连接 developer.arm.com (developer.arm.com)|23.41.45.203|:443... 已连接。
+    已发出 HTTP 请求，正在等待回应... 302 Moved Temporarily
+    位置：https://armkeil.blob.core.windows.net/developer/Files/downloads/gnu-a/8.3-2019.03/binrel/gcc-arm-8.3-2019.03-x86_64-arm-linux-gnueabihf.tar.xz [跟随至新的 URL]
+    --2020-03-18 11:04:12--  https://armkeil.blob.core.windows.net/developer/Files/downloads/gnu-a/8.3-2019.03/binrel/gcc-arm-8.3-2019.03-x86_64-arm-linux-gnueabihf.tar.xz
+    正在解析主机 armkeil.blob.core.windows.net (armkeil.blob.core.windows.net)... 52.239.137.100
+    正在连接 armkeil.blob.core.windows.net (armkeil.blob.core.windows.net)|52.239.137.100|:443... 已连接。
+    已发出 HTTP 请求，正在等待回应... 200 OK
+    长度： 256094408 (244M) [application/octet-stream]
+    正在保存至: “gcc-arm-8.3-2019.03-x86_64-arm-linux-gnueabihf.tar.xz”
+
+    gcc-arm-8.3-2019.0   0%[                    ] 167.51K  22.5KB/s    剩余 3h 5m ^C
+
+    start unpacking the arm-linux-gnueabihf-8.3.0 package ...
+    done...
+
+    # ls /opt
+    gcc-arm-linux-gnueabihf-8.3.0
+
+
+如果你的系统本身存在多个gcc-arm-linux-gnueabihf编译器的话，也不用管它，因为gcc-arm-linux-gnueabihf-8.3.0只是用来编译Qt，
+如果想要使用gcc-arm-linux-gnueabihf-8.3.0，可以导出环境变量，具体操作如下：
+
+
+导出gcc-arm-linux-gnueabihf-8.3.0交叉编译的环境变量
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+.. code:: bash
+
+    export PATH=/opt/gcc-arm-linux-gnueabihf-8.3.0/bin:$PATH
+
+输入命令验证版本
+~~~~~~~~~~~~~~~~~
+
+.. code:: bash
+
+    arm-linux-gnueabihf-gcc -v 
+
+若环境变量设置正确，则会出现以下信息
+
+.. code:: bash
+
+    ➜  ~ arm-linux-gnueabihf-gcc -v                              
+    使用内建 specs。
+    COLLECT_GCC=arm-linux-gnueabihf-gcc
+    COLLECT_LTO_WRAPPER=/opt/gcc-arm-linux-gnueabihf-8.3.0/bin/../libexec/gcc/arm-linux-gnueabihf/8.3.0/lto-wrapper
+    目标：arm-linux-gnueabihf
+    配置为：/tmp/dgboter/bbs/rhev-vm8--rhe6x86_64/buildbot/rhe6x86_64--arm-linux-gnueabihf/build/src/gcc/configure --target=arm-linux-gnueabihf --prefix= --with-sysroot=/arm-linux-gnueabihf/libc --with-build-sysroot=/tmp/dgboter/bbs/rhev-vm8--rhe6x86_64/buildbot/rhe6x86_64--arm-linux-gnueabihf/build/build-arm-linux-gnueabihf/install//arm-linux-gnueabihf/libc --with-bugurl=https://bugs.linaro.org/ --enable-gnu-indirect-function --enable-shared --disable-libssp --disable-libmudflap --enable-checking=release --enable-languages=c,c++,fortran --with-gmp=/tmp/dgboter/bbs/rhev-vm8--rhe6x86_64/buildbot/rhe6x86_64--arm-linux-gnueabihf/build/build-arm-linux-gnueabihf/host-tools --with-mpfr=/tmp/dgboter/bbs/rhev-vm8--rhe6x86_64/buildbot/rhe6x86_64--arm-linux-gnueabihf/build/build-arm-linux-gnueabihf/host-tools --with-mpc=/tmp/dgboter/bbs/rhev-vm8--rhe6x86_64/buildbot/rhe6x86_64--arm-linux-gnueabihf/build/build-arm-linux-gnueabihf/host-tools --with-isl=/tmp/dgboter/bbs/rhev-vm8--rhe6x86_64/buildbot/rhe6x86_64--arm-linux-gnueabihf/build/build-arm-linux-gnueabihf/host-tools --with-arch=armv7-a --with-fpu=neon --with-float=hard --with-arch=armv7-a --with-pkgversion='GNU Toolchain for the A-profile Architecture 8.3-2019.03 (arm-rel-8.36)'
+    线程模型：posix
+    gcc 版本 8.3.0 (GNU Toolchain for the A-profile Architecture 8.3-2019.03 (arm-rel-8.36)) 
+
+
+以上是验证SDK安装是否成功！！
+
+
+交叉编译tslib
+-------------
+
+tslib
+是一个用于触摸屏设备的开源函数库，能够为触摸屏驱动获得的采样提供诸如滤波、去抖、校准等功能，通常作为触摸屏驱动的适配层，为上层的应用提供了一个统一的接口，比如Qt就是上层应用，数据通过tslib传入Qt应用程序，Qt应用程序就知道哪里被触摸了，然后进行正确的响应。而且通过这样一个函数库，可以将编程者从繁琐的数据处理中解脱出来，因为触摸屏的坐标和液晶显示屏
+之间的坐标并不是一一对应的，所以，要让从触摸屏上得到的坐标正确转换为液晶显示屏上的坐标，需要经过一个转换过程，而tslib就是完成这个功能的。因此在这里预先编译安装tslib，这样在后面编译Qt的时候才能将tslib打包编译进去。
+
+**野火提供 build-tslib.sh 脚本一键下载、配置、编译及安装 tslib** ：
+
+build-tslib.sh 脚本内容如下：
+
+.. code:: bash
+
+    #!/bin/sh
+
+    # set -v 
+
+    HOST=arm-linux-gnueabihf
+    SCRIPT_PATH=$(pwd)
+
+    #添加交叉编译工具链路径
+    # CROSS_CHAIN_PREFIX=/opt/arm-gcc/bin/arm-linux-gnueabihf
+    CROSS_CHAIN_PREFIX=/opt/gcc-arm-linux-gnueabihf-8.3.0/bin/arm-linux-gnueabihf
+
+    #修改源码包解压后的名称
+    MAJOR_NAME=tslib
+
+    #修改需要下载的源码前缀和后缀
+    OPENSRC_VER_PREFIX=1
+    OPENSRC_VER_SUFFIX=.21
+
+    PACKAGE_NAME=${MAJOR_NAME}-${OPENSRC_VER_PREFIX}${OPENSRC_VER_SUFFIX}
+
+    #定义压缩包名称
+    COMPRESS_PACKAGE=${PACKAGE_NAME}.tar.bz2
+
+    #定义编译后安装--生成的文件,文件夹位置路径
+    INSTALL_PATH=/opt/${PACKAGE_NAME}
+
+    #无需修改--下载地址
+    DOWNLOAD_LINK=https://github.com/libts/${MAJOR_NAME}/releases/download/${OPENSRC_VER_PREFIX}${OPENSRC_VER_SUFFIX}/${COMPRESS_PACKAGE}
+
+    #下载源码包
+    do_download_src () {
+       echo "\033[1;33mstart download ${PACKAGE_NAME}...\033[0m"
+
+       if [ ! -f "${COMPRESS_PACKAGE}" ];then
+          if [ ! -d "${PACKAGE_NAME}" ];then
+             wget -c ${DOWNLOAD_LINK}
+          fi
+       fi
+
+       echo "\033[1;33mdone...\033[0m"
+    }
+
+    #解压源码包
+    do_tar_package () {
+       echo "\033[1;33mstart unpacking the ${PACKAGE_NAME} package ...\033[0m"
+       if [ ! -d "${PACKAGE_NAME}" ];then
+          tar -xf ${COMPRESS_PACKAGE}
+       fi
+       echo "\033[1;33mdone...\033[0m"
+       cd ${PACKAGE_NAME}
+    }
+
+    #配置选项
+    do_configure () {
+       echo "\033[1;33mstart configure ${PACKAGE_NAME}...\033[0m"
+
+       export CC=${CROSS_CHAIN_PREFIX}-gcc 
+       
+       ./configure \
+       --prefix=${INSTALL_PATH} \
+       --host=${HOST} \
+
+       echo "\033[1;33mdone...\033[0m"
+    }
+
+
+    #编译并且安装
+    do_make_install () {
+       echo "\033[1;33mstart make and install ${PACKAGE_NAME} ...\033[0m"
+       make && make install
+       echo "\033[1;33mdone...\033[0m"
+    }
+
+    #删除下载的文件
+    do_delete_file () {
+       cd ${SCRIPT_PATH}
+       if [ -f "${PACKAGE_NAME}" ];then
+          sudo rm -f ${PACKAGE_NAME}
+       fi
+    }
+
+    do_download_src
+    do_tar_package
+    do_configure
+    do_make_install
+    # do_delete_file
+
+    exit $?
+
+-  野火此处选用的tslib版本也是比较新的，是2019年发布的版本tslib-1.21，更多版本大家可以在官方发布的github网站上选择： https://github.com/libts/tslib/releases ，然后只需要修改版本对应的前缀
+   OPENSRC_VER_PREFIX 与后缀 OPENSRC_VER_SUFFIX 即可。
+
+.. figure:: media/qt_cross_compiling001.png
+   :alt: qt_cross_compiling001.png
+
+   qt_cross_compiling001.png
+
+-  交叉编译器选择刚刚安装的编译器：CROSS_CHAIN_PREFIX=/opt/gcc-arm-linux-gnueabihf-8.3.0/bin/arm-linux-gnueabihf。
+
+-  安装的路径是：INSTALL_PATH=/opt/${PACKAGE_NAME}，即 /opt/tslib-1.21
+
+整个脚本的执行顺序如下：
+
+1. 下载tslib源码
+2. 解压tslib源码文件
+3. 配置tslib源码，配置的内容主要是指定编译器： ``export CC=${CROSS_CHAIN_PREFIX}-gcc``
+   ；指定安装路径 ``--prefix=${INSTALL_PATH}`` ，即/opt/tslib-1.21
+   ；指定平台： ``--host=${HOST}`` 。
+4. 编译并且安装： ``make && make install`` 。
+
+**需要使用 sudo
+权限执行脚本** ，因为在/opt/目录下必须要有超级用户权限才可以正常安装。
+
+.. code:: bash
+
+    sudo ./build-tslib.sh
+
+交叉编译alsa
+------------
+
+高级Linux声音体系（英语：Advanced Linux Sound
+Architecture，缩写为ALSA），在Linux内核中，ALSA为声卡提供的驱动组件。ALSA支持声卡的自动配置，以及可以完美的处理系统中的多个声卡设备，所以可能会使用到ALSA，此时就预先将ALSA交叉编译完成，以便在交叉编译Qt时将ALSA包含编译进去。
+
+**野火提供 build-alsa.sh 脚本一键下载、配置、编译及安装 alsa** ：
+
+.. code:: bash
+
+    #!/bin/sh
+
+    HOST=arm-linux-gnueabihf
+    SCRIPT_PATH=$(pwd)
+
+    #修改源码包解压后的名称
+    MAJOR_NAME=alsa-lib
+
+    #修改需要下载的源码前缀和后缀
+    OPENSRC_VER_PREFIX=1.2
+    OPENSRC_VER_SUFFIX=.2
+
+    PACKAGE_NAME=${MAJOR_NAME}-${OPENSRC_VER_PREFIX}${OPENSRC_VER_SUFFIX}
+
+    #定义压缩包名称
+    COMPRESS_PACKAGE=${PACKAGE_NAME}.tar.bz2
+
+    #定义编译后安装--生成的文件,文件夹位置路径
+    INSTALL_PATH=/opt/${PACKAGE_NAME}
+
+    #添加交叉编译工具链路径
+    # CROSS_CHAIN_PREFIX=/opt/arm-gcc/bin/arm-linux-gnueabihf
+    CROSS_CHAIN_PREFIX=/opt/gcc-arm-linux-gnueabihf-8.3.0/bin/arm-linux-gnueabihf
+
+    #无需修改--下载地址
+    DOWNLOAD_LINK=ftp://ftp.alsa-project.org/pub/lib/${COMPRESS_PACKAGE}
+
+    #下载源码包
+    do_download_src () {
+       echo "\033[1;33mstart download ${PACKAGE_NAME}...\033[0m"
+       
+       if [ ! -f "${COMPRESS_PACKAGE}" ];then
+          if [ ! -d "${PACKAGE_NAME}" ];then
+             wget -c ${DOWNLOAD_LINK}
+          fi
+       fi
+
+       echo "\033[1;33mdone...\033[0m"
+    }
+
+    #解压源码包
+    do_tar_package () {
+       echo "\033[1;33mstart unpacking the ${PACKAGE_NAME} package ...\033[0m"
+       if [ ! -d "${PACKAGE_NAME}" ];then
+          tar -xf ${COMPRESS_PACKAGE}
+       fi
+       echo "\033[1;33mdone...\033[0m"
+       cd ${PACKAGE_NAME}
+    }
+
+    #配置选项
+    do_configure () {
+       echo "\033[1;33mstart configure ${PACKAGE_NAME}...\033[0m"
+
+       mkdir -p ${INSTALL_PATH}/config
+       mkdir -p ${INSTALL_PATH}/plugin
+
+       export CC=${CROSS_CHAIN_PREFIX}-gcc 
+       
+       ./configure \
+       --prefix=${INSTALL_PATH} \
+       --host=${HOST} \
+       # --enable-static \
+       --enable-shared \
+       --disable-python \
+       --with-configdir=${INSTALL_PATH}/config \
+       --with-plugindir=${INSTALL_PATH}/plugin
+
+       echo "\033[1;33mdone...\033[0m"
+    }
+
+
+    #编译并且安装
+    do_make_install () {
+       echo "\033[1;33mstart make and install ${PACKAGE_NAME} ...\033[0m"
+       make && make install
+       echo "\033[1;33mdone...\033[0m"
+    }
+
+    #删除下载的文件
+    do_delete_file () {
+       cd ${SCRIPT_PATH}
+       if [ -f "${PACKAGE_NAME}" ];then
+          sudo rm -f ${PACKAGE_NAME}
+       fi
+    }
+
+    do_download_src
+    do_tar_package
+    do_configure
+    do_make_install
+    # do_delete_file
+
+    exit $?
+
+-  野火此处选用的alsa版本也是比较新的，是2020年发布的版本alsa-1.2.2，更多版本大家可以在官方发布源码的网站上选择： ftp://ftp.alsa-project.org/pub/lib ，只需要修改版本对应的前缀
+   OPENSRC_VER_PREFIX 与后缀 OPENSRC_VER_SUFFIX 即可。
+
+.. figure:: media/qt_cross_compiling002.png
+   :alt: qt_cross_compiling002.png
+
+   qt_cross_compiling002.png
+
+-  交叉编译器选择刚刚安装的编译器：CROSS_CHAIN_PREFIX=/opt/gcc-arm-linux-gnueabihf-8.3.0/bin/arm-linux-gnueabihf。
+
+-  安装的路径是：INSTALL_PATH=/opt/${PACKAGE_NAME}，即 /opt/alsa-1.2.2
+
+整个脚本的执行顺序如下：
+
+1. 下载 alsa 源码
+2. 解压 alsa 源码文件
+3. 配置 alsa
+   源码，配置的内容主要是指定编译器： ``export CC=${CROSS_CHAIN_PREFIX}-gcc``
+   ；指定安装路径 ``--prefix=${INSTALL_PATH}`` ，即/opt/alsa-1.2.2
+   ；指定平台： ``--host=${HOST}`` ，除此之外还是要动态库的方式连接： ``--enable-shared``
+   ；不使能Python： ``--disable-python`` ；
+   然后指定配置文件的路径： ``--with-configdir=${INSTALL_PATH}/config`` ；指定插件的路径： ``--with-plugindir=${INSTALL_PATH}/plugin`` 。
+4. 编译并且安装： ``make && make install`` 。
+
+**需要使用 sudo
+权限执行脚本** ，因为在/opt/目录下必须要有超级用户权限才可以正常安装。
+
+.. code:: bash
+
+    sudo ./build-alsa.sh
+
+如果大家想要自己去配置alsa的内容，可以进入到源码目录下，运行以下命令进行查看支持的配置：
+
+.. code:: bash
+
+    #  ./configure -h
+
+    [....省略大部分的配置内容]
+
+    Optional Features:
+      --disable-option-checking  ignore unrecognized --enable/--with options
+      --disable-FEATURE       do not include FEATURE (same as --enable-FEATURE=no)
+      --enable-FEATURE[=ARG]  include FEATURE [ARG=yes]
+      --enable-silent-rules   less verbose build output (undo: "make V=1")
+      --disable-silent-rules  verbose build output (undo: "make V=0")
+      --disable-maintainer-mode
+                              disable make rules and dependencies not useful (and
+                              sometimes confusing) to the casual installer
+      --enable-dependency-tracking
+                              do not reject slow dependency extractors
+      --disable-dependency-tracking
+                              speeds up one-time build
+      --enable-static[=PKGS]  build static libraries [default=no]
+      --enable-shared[=PKGS]  build shared libraries [default=yes]
+      --enable-fast-install[=PKGS]
+                              optimize for fast installation [default=yes]
+      --disable-libtool-lock  avoid locking (might break parallel builds)
+      --enable-symbolic-functions
+                              use -Bsymbolic-functions option if available
+                              (optmization for size and speed)
+      --enable-debug          enable assert call at the default error message
+                              handler
+      --enable-resmgr         support resmgr (optional)
+      --disable-aload         disable reading /dev/aload*
+      --disable-mixer         disable the mixer component
+
+    [....省略大部分的配置内容]
+
+交叉编译Qt
+----------
+
+本次交叉编译Qt源码的版本选择5.14.1版本，我们可以在Qt官网可以看到对应的源码是最新的版本：
+
+.. figure:: media/qt_cross_compiling003.png
+   :alt: qt_cross_compiling003.png
+
+   qt_cross_compiling003.png
+
+**野火提供 build-qt.sh 脚本一键下载、配置、安装依赖、编译及安装 qt** ：
+
+build-qt.sh 脚本内容如下：
+
+.. code:: bash
+
+    #!/bin/sh
+
+    PLATFORM=my-linux-arm-qt
+    SCRIPT_PATH=$(pwd)
+
+    #修改源码包解压后的名称
+    MAJOR_NAME=qt-everywhere-src
+
+    #修改需要下载的源码前缀和后缀
+    OPENSRC_VER_PREFIX=5.14
+    OPENSRC_VER_SUFFIX=.1
+
+    #添加tslib交叉编译的动态库文件和头文件路径
+    TSLIB_LIB=/opt/tslib-1.21/lib
+    TSLIB_INC=/opt/tslib-1.21/include
+
+    #添加alsa交叉编译的动态库文件和头文件路径
+    ALSA_LIB=/opt/alsa-lib-1.2.2/lib
+    ALSA_INC=/opt/alsa-lib-1.2.2/include
+
+    #修改源码包解压后的名称
+    PACKAGE_NAME=${MAJOR_NAME}-${OPENSRC_VER_PREFIX}${OPENSRC_VER_SUFFIX}
+
+    #定义编译后安装--生成的文件,文件夹位置路径
+    INSTALL_PATH=/opt/${PACKAGE_NAME}
+
+    #添加交叉编译工具链路径
+    # CROSS_CHAIN_PREFIX=/opt/arm-gcc/bin/arm-linux-gnueabihf
+    CROSS_CHAIN_PREFIX=/opt/gcc-arm-linux-gnueabihf-8.3.0/bin/arm-linux-gnueabihf
+
+    #定义压缩包名称
+    COMPRESS_PACKAGE=${PACKAGE_NAME}.tar.xz
+
+    #无需修改--自动组合下载地址
+    OPENSRC_VER=${OPENSRC_VER_PREFIX}${OPENSRC_VER_SUFFIX}
+    # DOWNLOAD_LINK=http://download.qt.io/new_archive/qt/${OPENSRC_VER_PREFIX}/${OPENSRC_VER}/single/${COMPRESS_PACKAGE}
+    DOWNLOAD_LINK=http://download.qt.io/official_releases/qt/${OPENSRC_VER_PREFIX}/${OPENSRC_VER}/single/${COMPRESS_PACKAGE}
+
+    #无需修改--自动组合平台路径
+    CONFIG_PATH=${SCRIPT_PATH}/${PACKAGE_NAME}/qtbase/mkspecs/${PLATFORM}
+
+    #无需修改--自动组合配置平台路径文件
+    CONFIG_FILE=${CONFIG_PATH}/qmake.conf
+
+    #下载源码包
+    do_download_src () {
+       echo "\033[1;33mstart download ${PACKAGE_NAME}...\033[0m"
+
+       if [ ! -f "${COMPRESS_PACKAGE}" ];then
+          if [ ! -d "${PACKAGE_NAME}" ];then
+             wget -c ${DOWNLOAD_LINK}
+          fi
+       fi
+
+       echo "\033[1;33mdone...\033[0m"
+    }
+
+    #解压源码包
+    do_tar_package () {
+       echo "\033[1;33mstart unpacking the ${PACKAGE_NAME} package ...\033[0m"
+       if [ ! -d "${PACKAGE_NAME}" ];then
+          tar -xf ${COMPRESS_PACKAGE}
+       fi
+       echo "\033[1;33mdone...\033[0m"
+       cd ${PACKAGE_NAME}
+    }
+
+    #安装依赖项
+    do_install_config_dependent () {
+       sudo apt install g++ make qt3d5-dev-tools -y
+       sudo apt install qml-module-qtquick-xmllistmodel -y
+       sudo apt install qml-module-qtquick-virtualkeyboard qml-module-qtquick-shapes qml-module-qtquick-privatewidgets qml-module-qtquick-dialogs qml-module- qt-labs-calendar qml -y
+       sudo apt install libqt53dquickscene2d5 libqt53dquickrender5 libqt53dquickinput5 libqt53dquickextras5 libqt53dquickanimation5 libqt53dquick5 -y
+       sudo apt install qtdeclarative5-dev qml-module-qtwebengine qml-module-qtwebchannel qml-module-qtmultimedia qml-module-qtaudioengine -y
+    }
+
+    #修改配置平台
+    do_config_before () {
+       echo "\033[1;33mstart configure platform...\033[0m"
+
+    if [ ! -d "${CONFIG_PATH}" ];then
+       cp -a ${SCRIPT_PATH}/${PACKAGE_NAME}/qtbase/mkspecs/linux-arm-gnueabi-g++ ${CONFIG_PATH}
+    fi
+
+       echo "#" > ${CONFIG_FILE}
+       echo "# qmake configuration for building with arm-linux-gnueabi-g++" >> ${CONFIG_FILE}
+       echo "#" >> ${CONFIG_FILE}
+       echo "" >> ${CONFIG_FILE}
+       echo "MAKEFILE_GENERATOR      = UNIX" >> ${CONFIG_FILE}
+       echo "CONFIG                 += incremental" >> ${CONFIG_FILE}
+       echo "QMAKE_INCREMENTAL_STYLE = sublib" >> ${CONFIG_FILE}
+       echo "" >> ${CONFIG_FILE}
+       echo "include(../common/linux.conf)" >> ${CONFIG_FILE}
+       echo "include(../common/gcc-base-unix.conf)" >> ${CONFIG_FILE}
+       echo "include(../common/g++-unix.conf)" >> ${CONFIG_FILE}
+       echo "" >> ${CONFIG_FILE}
+       echo "# modifications to g++.conf" >> ${CONFIG_FILE}
+       echo "QMAKE_CC                = ${CROSS_CHAIN_PREFIX}-gcc -lts" >> ${CONFIG_FILE}
+       echo "QMAKE_CXX               = ${CROSS_CHAIN_PREFIX}-g++ -lts" >> ${CONFIG_FILE}
+       echo "QMAKE_LINK              = ${CROSS_CHAIN_PREFIX}-g++ -lts" >> ${CONFIG_FILE}
+       echo "QMAKE_LINK_SHLIB        = ${CROSS_CHAIN_PREFIX}-g++ -lts" >> ${CONFIG_FILE}
+       echo "" >> ${CONFIG_FILE}
+       echo "# modifications to linux.conf" >> ${CONFIG_FILE}
+       echo "QMAKE_AR                = ${CROSS_CHAIN_PREFIX}-ar cqs" >> ${CONFIG_FILE}
+       echo "QMAKE_OBJCOPY           = ${CROSS_CHAIN_PREFIX}-objcopy" >> ${CONFIG_FILE}
+       echo "QMAKE_NM                = ${CROSS_CHAIN_PREFIX}-nm -P" >> ${CONFIG_FILE}
+       echo "QMAKE_STRIP             = ${CROSS_CHAIN_PREFIX}-strip" >> ${CONFIG_FILE}
+       echo "load(qt_config)" >> ${CONFIG_FILE}
+       echo "" >> ${CONFIG_FILE}
+       echo "QMAKE_INCDIR=${TSLIB_INC}" >> ${CONFIG_FILE}
+       echo "QMAKE_LIBDIR=${TSLIB_LIB}" >> ${CONFIG_FILE}
+
+       cat ${CONFIG_FILE}
+       echo "\033[1;33mdone...\033[0m"
+    }
+
+    #配置选项
+    do_configure () {
+       echo "\033[1;33mstart configure ${PACKAGE_NAME}...\033[0m"
+
+       export CC="${CROSS_CHAIN_PREFIX}-gcc"
+       export CXX="${CROSS_CHAIN_PREFIX}-g++" 
+
+       ./configure \
+       -prefix ${INSTALL_PATH} \
+       -xplatform ${PLATFORM} \
+       -release \
+       -opensource \
+       -confirm-license \
+       -no-openssl \
+       -no-opengl \
+       -no-xcb \
+       -no-eglfs \
+       -no-compile-examples \
+       -no-pkg-config \
+       -skip qtquickcontrols \
+       -skip qtquickcontrols2 \
+       -skip qtsensors \
+       -skip qtdoc \
+       -skip qtwayland \
+       -skip qt3d \
+       -skip qtcanvas3d \
+       -skip qtpurchasing \
+       -skip qtcharts \
+       -skip qtdeclarative \
+       -no-iconv \
+       -no-glib \
+       -tslib \
+       -I"${TSLIB_INC}" \
+       -L"${TSLIB_LIB}" \
+       -alsa \
+       -I"${ALSA_INC}" \
+       -L"${ALSA_LIB}" \
+
+       echo "\033[1;33mdone...\033[0m"
+    }
+
+
+    #编译并且安装
+    do_make_install () {
+       echo "\033[1;33mstart make and install ${PACKAGE_NAME} ...\033[0m"
+       make && make install
+       echo "\033[1;33mdone...\033[0m"
+    }
+
+    #删除下载的文件
+    do_delete_file () {
+       cd ${SCRIPT_PATH}
+       if [ -f "${COMPRESS_PACKAGE}" ];then
+          sudo rm -f ${COMPRESS_PACKAGE}
+       fi
+    }
+
+    do_download_src
+    do_tar_package
+    do_install_config_dependent
+    do_config_before
+    do_configure
+    do_make_install
+    # do_delete_file
+
+    exit $?
+
+简单介绍一下脚本的内容：
+
+1. 使用wget命令下载qt源码，源码的路径是： http://download.qt.io/official_releases/qt/5.14/5.14.1/single/qt-everywhere-src-5.14.1.tar.xz
+2. 解压下载完的源码包。
+3. 进入源码目录中，进行配置，为了不污染源码本身，重新拷贝一份 ``qtbase/mkspecs/linux-arm-gnueabi-g++`` 中的配置，并且命名为 ``my-linux-arm-qt`` ，然后修改qmake.conf文件的内容，主要是指定编译Qt的编译器： ``/opt/gcc-arm-linux-gnueabihf-8.3.0/bin/arm-linux-gnueabihf-gcc``
+   。当然，这部分操作均在脚本中完成的。
+
+.. figure:: media/qt_cross_compiling004.png
+   :alt: qt_cross_compiling004.png
+
+   qt_cross_compiling004.png
+.. figure:: media/qt_cross_compiling005.png
+   :alt: qt_cross_compiling005.png
+
+   qt_cross_compiling005.png
+
+4. 安装一些对应的依赖。
+5. 编译Qt并安装到指定目录下： ``/opt/qt-everywhere-src-5.14.1`` 。
+
+安装Qt Creator
+--------------
+
+在官网下载Qt Creator，大家可以仅安装Qt Creator IDE，也可以安装Qt Creator
+IDE与 PC上的Qt
+5.14.1版本的编译环境，前者没有Qt编译环境，而后者可以在PC上编译Qt应用程序并且可以在PC上运行与调试。独立的Qt
+Creator
+IDE可以在官网中下载： http://download.qt.io/official_releases/qtcreator/4.11/4.11.1/ 。
+
+为了方便起见，我们既安装IDE也安装PC上的Qt编译环境，注意此处的编译环境是PC上的而非交叉编译环境。我们在Qt官网下载IED与编译环境集成的可执行文件： http://download.qt.io/official_releases/qt/5.14/5.14.1/ ，如下图所示：
+
+.. figure:: media/install_qt_creator000.png
+   :alt: install_qt_creator000
+
+   install_qt_creator000
+
+当然我们也能在终端通过wget命令下载：
+
+.. code:: bash
+
+    ➜  ~ wget http://download.qt.io/official_releases/qt/5.14/5.14.1/qt-opensource-linux-x64-5.14.1.run
+    --2020-03-19 11:10:45--  http://download.qt.io/official_releases/qt/5.14/5.14.1/qt-opensource-linux-x64-5.14.1.run
+    正在解析主机 download.qt.io (download.qt.io)... 77.86.229.90
+    正在连接 download.qt.io (download.qt.io)|77.86.229.90|:80... 已连接。
+    已发出 HTTP 请求，正在等待回应... 302 Found
+    位置：http://mirrors.ustc.edu.cn/qtproject/archive/qt/5.14/5.14.1/qt-opensource-linux-x64-5.14.1.run [跟随至新的 URL]
+    --2020-03-19 11:11:24--  http://mirrors.ustc.edu.cn/qtproject/archive/qt/5.14/5.14.1/qt-opensource-linux-x64-5.14.1.run
+    正在解析主机 mirrors.ustc.edu.cn (mirrors.ustc.edu.cn)... 202.38.95.110, 202.141.176.110, 2001:da8:d800:95::110
+    正在连接 mirrors.ustc.edu.cn (mirrors.ustc.edu.cn)|202.38.95.110|:80... 已连接。
+    已发出 HTTP 请求，正在等待回应... 200 OK
+    长度： 1320027012 (1.2G) [application/x-makeself]
+    正在保存至: “qt-opensource-linux-x64-5.14.1.run”
+
+    qt-opensource-linux-x64-5 100%[==================================>]   1.23G  4.82MB/s    用时 2m 7s 
+
+    2020-03-19 11:13:31 (9.90 MB/s) - 已保存 “qt-opensource-linux-x64-5.14.1.run” [1320027012/1320027012])
+
+在下载完毕后赋予它可执行权限：
+
+.. code:: bash
+
+    sudo chmod +x qt-opensource-linux-x64-5.14.1.run
+
+然后运行即可安装：
+
+.. code:: bash
+
+    ./qt-opensource-linux-x64-5.14.1.run
+
+安装过程如下，基本上一路Next下去即可：
+
+.. figure:: media/install_qt_creator001.png
+   :alt: install_qt_creator001
+
+   install_qt_creator001
+
+因为安装的时候要登陆Qt的账号密码，如果还没有账号密码的同学可以去Qt官网进行注册一个：
+
+.. figure:: media/install_qt_creator002.png
+   :alt: install_qt_creator002
+
+   install_qt_creator002
+
+同意Qt的开源协议。
+
+.. figure:: media/install_qt_creator003.png
+   :alt: install_qt_creator003
+
+   install_qt_creator003
+
+选择安装的目录，默认情况下会在当前目录下安装，有需要的可以选择其他目录。
+
+.. figure:: media/install_qt_creator004.png
+   :alt: install_qt_creator004
+
+   install_qt_creator004
+
+选择安装的PC上的Qt编译环境，为了避免缺失，全选就行了。
+
+.. figure:: media/install_qt_creator005.png
+   :alt: install_qt_creator005
+
+   install_qt_creator005
+
+同意Qt的协议，因为不同意的话是无法安装的，对于商用的同学就要认真看看协议的内容了，而仅是学习的话，基本不用理会它。
+
+.. figure:: media/install_qt_creator006.png
+   :alt: install_qt_creator006
+
+   install_qt_creator006
+
+正在安装中。
+
+.. figure:: media/install_qt_creator007.png
+   :alt: install_qt_creator007
+
+   install_qt_creator007
+
+安装完成。
+
+.. figure:: media/install_qt_creator008.png
+   :alt: install_qt_creator008
+
+   install_qt_creator008
+
+开始使用Qt Creator
+------------------
+
+在ubuntu打开Qt Creator：
+
+.. figure:: media/install_qt_creator009.png
+   :alt: install_qt_creator009
+
+   install_qt_creator009
+
+进入Qt Creator后，可以在示例中看到很多自带的例程我们可以选择一个时钟的例程，名字是analogclock，它所在的目录是 ``Qt5.14.1/Examples/Qt-5.14.1/widgets/widgets/`` 。
+
+.. figure:: media/install_qt_creator010.png
+   :alt: install_qt_creator010
+
+   install_qt_creator010
+
+我们打开这个例程后，点击构建，将这个例程编译完成，然后我们可以点击运行：
+
+.. figure:: media/install_qt_creator011.png
+   :alt: install_qt_creator011
+
+   install_qt_creator011
+
+此时PC上已经显示出这个例程的运行效果，如图所示：
+
+.. figure:: media/install_qt_creator012.png
+   :alt: install_qt_creator012
+
+   install_qt_creator012
+
+除此之外还有非常多的教程，这些教程对初学者都是非常友好的，大家可以去学习一下。
+
+.. figure:: media/install_qt_creator013.png
+   :alt: install_qt_creator013
+
+   install_qt_creator013
+
+在Qt Creator使用交叉编译环境
+----------------------------
+
+至此，上面所讲的都是在PC环境下使用的，它编译出来的应用程序并不能在开发板上运行，因此我们需要在Qt
+Creator使用交叉编译环境，然后进行交叉编译，再将程序放到开发板上运行。
+首先选择 【工具】 -> 【选项】
+
+.. figure:: media/install_qt_creator014.png
+   :alt: install_qt_creator014
+
+   install_qt_creator014
+
+在弹出来的选项配置界面中选择【Kits】->【编译器】，点击【添加】按钮选择添加【GCC】 ->【C++】类型，
+自己定义一个名字，然后将我们之前安装的``arm-linux-gnueabihf-gcc 8.3.0`` 版本的交叉编译器添加进来，
+注意要选择 ``/opt/gcc-arm-linux-gnueabihf-8.3.0/bin/arm-linux-gnueabihf-g++`` ，点击【Apply】完成应用。
+
+.. figure:: media/install_qt_creator015.png
+   :alt: install_qt_creator015
+
+   install_qt_creator015
+
+同理将 ``/opt/gcc-arm-linux-gnueabihf-8.3.0/bin/arm-linux-gnueabihf-gcc`` 编译器添加进来。
+
+.. figure:: media/install_qt_creator016.png
+   :alt: install_qt_creator016
+
+   install_qt_creator016
+
+然后选择Qt的版本，我们在前面已经交叉编译并安装了Qt5.14.1版本，那么在这里只需要将qmake添加进来即可，
+具体操作如下：在选项配置界面中选择【Kits】->【Qt Versions】，然后点击【添加】按钮，在Qt的安装目录
+下选择qmake： ``/opt/qt-everywhere-src-5.14.1/bin`` ，然后添加完成后点击【Apply】完成应用。
+
+.. figure:: media/install_qt_creator017.png
+   :alt: install_qt_creator017
+
+   install_qt_creator017
+
+.. figure:: media/install_qt_creator018.png
+   :alt: install_qt_creator018
+
+   install_qt_creator018
+
+最后要添加构建套件，在选项配置界面中选择【Kits】->
+【构建套件(Kit)】，点击【添加】，然后设置名称，此处我的名称设置为“ebf_imx6ull”，接着选择设备的类型，我选择了通用的Linux设备（Generic
+Linux
+Device），因为这是为开发板构建的环境，然后选择编译器，此处使用我们刚刚添加的交叉编译器即可，最后选择Qt的版本，此处也是选择我们刚刚添加的交叉编译安装的版本，最后点击【Apply】完成应用。
+
+.. figure:: media/install_qt_creator019.png
+   :alt: install_qt_creator019
+
+   install_qt_creator019
+
+交叉编译Qt自带的例程
+--------------------
+
+首先点击例程的项目配置，选择使用交叉编译环境编译，选择构建套件为刚刚添加的交叉编译套件 ``ebf_imx6ull`` ，在编译时可以根据自己需求决定选择Debug或者Release版本：
+
+.. figure:: media/install_qt_creator020.png
+   :alt: install_qt_creator020
+
+   install_qt_creator020
+
+.. figure:: media/install_qt_creator021.png
+   :alt: install_qt_creator021
+
+   install_qt_creator021
+
+点击“锤子”构建应用程序：
+
+.. figure:: media/install_qt_creator022.png
+   :alt: install_qt_creator022
+
+   install_qt_creator022
+
+在构建完成后，可以在 ``Qt5.14.1/Examples/Qt-5.14.1/widgets/widgets/build-analogclock-ebf_imx6ull-Release`` 目录下看到对应的可执行文件analogclock：
+
+.. figure:: media/install_qt_creator023.png
+   :alt: install_qt_creator023
+
+   install_qt_creator023
+
+我们可以使用file查看文件的类型，可以发现它确实是32位的程序，是ARM类型的可执行文件。
+
+.. figure:: media/install_qt_creator024.png
+   :alt: install_qt_creator024
+
+   install_qt_creator024
+
+开发板的环境处理
+----------------
+
+首先要使用已经发布的Debian系统，可以选择纯净版的Debian镜像 ``Debian Buster Lite`` ，也可以选择动态版本的Qt镜像 ``Full Feature QT_App`` ，但是注意 **不要选择其他版本** 。
+
+Debian Buster Lite版本
+~~~~~~~~~~~~~~~~~~~~~~
+
+如果你选择的是纯净版的Debian镜像 ``Debian Buster Lite`` ，我们要安装动态版本的qt-app，直接使用以下指令安装即可：
+
+.. code:: bash
+
+    sudo apt-get install qt-app
+
+如果没有发现 ``qt-app`` 安装包，可以使用以下命令更新一下apt命令的软件包缓存再安装：
+
+.. code:: bash
+
+    sudo apt-get update
+
+在安装完成后，可以发现 ``/home/debian`` 目录下多了qt-app文件夹，这里就是我们出厂提供的Qt应用程序，可以直接使用以下命令运行它，野火提供了run.sh运行Qt应用程序的脚本，这样子就不需要我们配置环境变量：
+
+.. code:: bash
+
+    # 进入qt-app目录
+    cd qt-app
+
+    # 运行
+    sudo ./run.sh
+
+如果能成功运行，则可以 **将我们编译例程的可执行文件analogclock放到qt-app目录下** ，然后编辑run.sh脚本，主要是修改脚本中的最后一行，将运行官方的App改为自己的Qt例程analogclock。（编辑可以使用nano编辑器进行编辑）
+
+.. code:: bash
+
+    #! /bin/sh
+
+    type devscan
+
+    if [ $? -eq 0 ]; then
+        eventx=$(devscan "goodix-ts")
+        echo "eventx=$eventx"
+        if [ ! -f "/etc/pointercal" ]; then
+            type devscan
+            if [ $? -eq 0 ]; then
+                ts_calibrate
+            fi
+        fi
+    else
+        echo "please install devscan"
+        echo
+        echo "sudo apt-get install devscan"
+        exit
+    fi
+
+    export APP_DIR=/home/debian/qt-app
+    export QT_QPA_PLATFORM_PLUGIN_PATH=/usr/lib/arm-linux-gnueabihf/qt5/plugins/
+    export LD_LIBRARY_PATH=$LD_LIBRARY_PATH:$APP_DIR/libskin:$APP_DIR/libqui:$APP_DIR/libffmpeg:/usr/lib:/lib
+    export QT_QPA_FONTDIR=/usr/share/fonts/SourceHanSans
+    export PATH=$PATH:$QT_DIR/libexec
+    export QT_QPA_PLATFORM=linuxfb:fb=/dev/fb0
+    export TSLIB_CONFFILE=/etc/ts.conf
+    export TSLIB_CALIBFILE=/etc/pointercal
+    export QT_QPA_GENERIC_PLUGINS=tslib:/dev/input/$eventx
+    export QWS_MOUSE_PROTO=tslib
+    export QT_QPA_EVDEV_TOUCHSCREEN_PARAMETERS=/dev/input/$eventx:rotate=180:invertx
+
+    # start app...
+    # $APP_DIR/App
+
+    # 这里是要运行的Qt程序
+    $APP_DIR/analogclock
+
+保存并且运行：
+
+.. code:: bash
+
+    # 运行
+    sudo ./run.sh
+
+此时我们的开发板上运行的就是Qt的例程，效果如下：
+
+.. figure:: media/install_qt_creator025.png
+   :alt: install_qt_creator025
+
+   install_qt_creator025
+
+Full Feature QT_App版本
+~~~~~~~~~~~~~~~~~~~~~~~~
+
+而如果你选择的是动态版本的Qt镜像 ``Full Feature QT_App`` ，则无需安装qt-app，因为在系统中就已经存在了qt相关的环境，并且在 ``/home/debian`` 路径下就也存在了qt-app应用程序。
+
+**将我们编译例程的可执行文件analogclock放到qt-app目录下** ，然后编辑run.sh脚本，主要是修改脚本中的最后一行，将运行官方的App改为自己的Qt例程analogclock。（编辑可以使用nano编辑器进行编辑）
+
+.. code:: bash
+
+    #! /bin/sh
+
+    type devscan
+
+    if [ $? -eq 0 ]; then
+        eventx=$(devscan "goodix-ts")
+        echo "eventx=$eventx"
+        if [ ! -f "/etc/pointercal" ]; then
+            type devscan
+            if [ $? -eq 0 ]; then
+                ts_calibrate
+            fi
+        fi
+    else
+        echo "please install devscan"
+        echo
+        echo "sudo apt-get install devscan"
+        exit
+    fi
+
+    export APP_DIR=/home/debian/qt-app
+    export QT_QPA_PLATFORM_PLUGIN_PATH=/usr/lib/arm-linux-gnueabihf/qt5/plugins/
+    export LD_LIBRARY_PATH=$LD_LIBRARY_PATH:$APP_DIR/libskin:$APP_DIR/libqui:$APP_DIR/libffmpeg:/usr/lib:/lib
+    export QT_QPA_FONTDIR=/usr/share/fonts/SourceHanSans
+    export PATH=$PATH:$QT_DIR/libexec
+    export QT_QPA_PLATFORM=linuxfb:fb=/dev/fb0
+    export TSLIB_CONFFILE=/etc/ts.conf
+    export TSLIB_CALIBFILE=/etc/pointercal
+    export QT_QPA_GENERIC_PLUGINS=tslib:/dev/input/$eventx
+    export QWS_MOUSE_PROTO=tslib
+    export QT_QPA_EVDEV_TOUCHSCREEN_PARAMETERS=/dev/input/$eventx:rotate=180:invertx
+
+    # start app...
+    # $APP_DIR/App
+
+    # 这里是要运行的Qt程序
+    $APP_DIR/analogclock
+
+保存并且运行：
+
+.. code:: bash
+
+    # 运行
+    sudo ./run.sh
+
+效果也是一样的。
+
+.. figure:: media/install_qt_creator025.png
+   :alt: install_qt_creator025
+
+   install_qt_creator025
+
+编译野火提供的Debian Qt Demo
+----------------------------
+
+因为本次实验是使用Qt
+5.14.1去编译demo，demo略微有改动，我们可以从github或者gitee上拉取对应的仓库到本地，然后使用Qt
+Creator去编译：
+
+从github拉取：
+
+.. code:: bash
+
+    git clone https://github.com/Embedfire/ebf_debian_qt_demo.git
+
+从gitee拉取：
+
+.. code:: bash
+
+    git clone https://gitee.com/wildfireteam/ebf_debian_qt_demo.git
+
+打开Qt Creator，添加QtUi进行单独的编译，通过Qt Creator界面的【文件】 ->
+【添加文件或项目】，选择 ``ebf_debian_qt_demo/QtUi`` 目录下的QtUi.pro工程添加到Qt
+Creator中。
+
+.. figure:: media/install_qt_creator026.png
+   :alt: install_qt_creator026
+
+   install_qt_creator026
+
+在添加工程的时候会让你选择构建套件，我们全选就好了，这取决于你系统中有多少中构建套件，而交叉编译套件则是我们之前安装的 ``ebf_imx6ull`` ，这个套件必须存在，否则无法交叉编译。
+
+.. figure:: media/install_qt_creator027.png
+   :alt: install_qt_creator027
+
+   install_qt_creator027
+
+最后选择对应的构建套件并且进行构建。
+
+.. figure:: media/install_qt_creator028.png
+   :alt: install_qt_creator028
+
+   install_qt_creator028
+
+同理我们将Skin工程添加到Qt Creator中，然后进行构建：
+
+.. figure:: media/install_qt_creator029.png
+   :alt: install_qt_creator029
+
+   install_qt_creator029
+
+.. figure:: media/install_qt_creator030.png
+   :alt: install_qt_creator030
+
+   install_qt_creator030
+
+最后将我们要编译的Demo工程添加到Qt Creator中，并且进行构建：
+
+.. figure:: media/install_qt_creator031.png
+   :alt: install_qt_creator031
+
+   install_qt_creator031
+
+.. figure:: media/install_qt_creator032.png
+   :alt: install_qt_creator032
+
+   install_qt_creator032
+
+在构建完成后，可以看到 ``ebf_debian_qt_demo/app_bin`` 目录下存在App可执行程序，我们使用file查看该可执行程序会发现它是32位的，可以在ARM开发板上运行，如图所示：
+
+.. figure:: media/install_qt_creator033.png
+   :alt: install_qt_creator033
+
+   install_qt_creator033
+
+我们将它放到野火提供的Debian系统qt-app目录下，然后编辑run.sh脚本，主要是修改脚本中的最后一行，将运行官方的App改为自己的Qt应用程序xxx（最好是重命名一下我们编译的App，比如我重命名为mydemo）。
+
+.. code:: bash
+
+    #! /bin/sh
+
+    type devscan
+
+    if [ $? -eq 0 ]; then
+        eventx=$(devscan "goodix-ts")
+        echo "eventx=$eventx"
+        if [ ! -f "/etc/pointercal" ]; then
+            type devscan
+            if [ $? -eq 0 ]; then
+                ts_calibrate
+            fi
+        fi
+    else
+        echo "please install devscan"
+        echo
+        echo "sudo apt-get install devscan"
+        exit
+    fi
+
+    export APP_DIR=/home/debian/qt-app
+    export QT_QPA_PLATFORM_PLUGIN_PATH=/usr/lib/arm-linux-gnueabihf/qt5/plugins/
+    export LD_LIBRARY_PATH=$LD_LIBRARY_PATH:$APP_DIR/libskin:$APP_DIR/libqui:$APP_DIR/libffmpeg:/usr/lib:/lib
+    export QT_QPA_FONTDIR=/usr/share/fonts/SourceHanSans
+    export PATH=$PATH:$QT_DIR/libexec
+    export QT_QPA_PLATFORM=linuxfb:fb=/dev/fb0
+    export TSLIB_CONFFILE=/etc/ts.conf
+    export TSLIB_CALIBFILE=/etc/pointercal
+    export QT_QPA_GENERIC_PLUGINS=tslib:/dev/input/$eventx
+    export QWS_MOUSE_PROTO=tslib
+    export QT_QPA_EVDEV_TOUCHSCREEN_PARAMETERS=/dev/input/$eventx:rotate=180:invertx
+
+    # start app...
+    # $APP_DIR/App
+
+    # 这里是要运行的Qt程序
+    $APP_DIR/mydemo
+
+然后运行：
+
+.. code:: bash
+
+    sudo ./run.sh
+
+运行的效果如下：
+
+.. figure:: media/install_qt_creator034.png
+   :alt: install_qt_creator034
+
+   install_qt_creator034
+
+在PC上运行野火提供的Debian Qt Demo
+----------------------------------
+
+有同学又想在PC上运行野火提供的Debian Qt
+Demo，其实非常简单，我们只需要选择不同的构建套件即可，比如我们将QtUi、Skin、FireApp等工程的构建套件选择为 ``Desktop Qt 5.14.1 GCC 64bit`` 即可，这个构建套件是我们在安装的时候自动选择的，具体见：
+
+.. figure:: media/install_qt_creator035.png
+   :alt: install_qt_creator035
+
+   install_qt_creator035
+
+然后我们将所有工程都选择为 ``Desktop Qt 5.14.1 GCC 64bit`` 套件构建：
+
+Skin工程构建：
+
+.. figure:: media/install_qt_creator036.png
+   :alt: install_qt_creator036
+
+   install_qt_creator036
+
+QtUi工程构建：
+
+.. figure:: media/install_qt_creator037.png
+   :alt: install_qt_creator037
+
+   install_qt_creator037
+
+FireApp工程构建后运行：
+
+.. figure:: media/install_qt_creator038.png
+   :alt: install_qt_creator038
+
+   install_qt_creator038
+
+运行的效果：
+
+.. figure:: media/install_qt_creator039.png
+   :alt: install_qt_creator039
+
+   install_qt_creator039
+
+错误处理
+~~~~~~~~
+
+1. 如果因为之前交叉编译产生不能链接的32位的文件，那么我们可以清除，然后再重新构建即可：
+
+.. figure:: media/install_qt_creator040.png
+   :alt: install_qt_creator040
+
+   install_qt_creator040
+
+如果出现无法找到App应用程序的错误，我们可以重新设置一下项目运行的选项，运行配置选择App即可。
+
+.. figure:: media/install_qt_creator041.png
+   :alt: install_qt_creator041
+
+   install_qt_creator041
+
+.. figure:: media/install_qt_creator042.png
+   :alt: install_qt_creator042
+
+   install_qt_creator042
+
+使用命令行编译
+--------------
+
+导出Qt交叉编译的环境变量
+~~~~~~~~~~~~~~~~~~~~~~~~
+
+.. code:: bash
+
+    export PATH=/opt/qt-everywhere-src-5.14.1/bin:$PATH
+
+输入命令验证Qt版本
+~~~~~~~~~~~~~~~~~~
+
+.. code:: bash
+
+    qmake -v 
+
+若环境变量设置正确，则会出现以下信息
+
+.. code:: bash
+
+    QMake version 3.1
+    Using Qt version 5.14.1 in /opt/qt-everywhere-src-5.14.1/lib
+
+    以上是验证SDK安装是否成功！！
+
+下载qt源码
+~~~~~~~~~~
+
+**github**
+
+.. code:: bash
+
+    git clone https://github.com/Embdefire/ebf_debian_qt_demo.git
+
+**gitee**
+
+.. code:: bash
+
+    git clone https://gitee.com/wildfireteam/ebf_debian_qt_demo.git
+
+编译
+~~~~
+
+.. code:: bash
+
+    ./build.sh
+
+如果 ``build.sh`` 不是可执行文件，可以使用以下命令添加可执行权限
+
+.. code:: bash
+
+    chmod +x build.sh
+
+输出
+~~~~
+
+在当前目录下会创建一个 ``run_dir`` 目录，存在 ``App  libqui  libskin`` 文件，App是可以直接在开发板上运行的！
+与此同时，还会打包一个 ``fire-app-xxxx.tar.bz2`` 文件，大家可以拷贝到对应的目录下解压替换掉旧的 ``App`` 。
+
+清除相关内容
+~~~~~~~~~~~~
+
+.. code:: bash
+
+    make distclean
+
diff --git a/documentation/linux_env/using_php.rst b/documentation/linux_env/using_php.rst
new file mode 100644
index 0000000000000000000000000000000000000000..8e88995161ced053048362d76ec1f8827f92048d
--- /dev/null
+++ b/documentation/linux_env/using_php.rst
@@ -0,0 +1,176 @@
+在Debian上部署web服务器
+=======================
+
+-  平台：野火imx6ull开发板
+-  系统：Debian
+-  使用工具：Nginx、PHP
+
+实现在Debian上通过Nginx与PHP搭建Web服务器，验证Nginx与PHP可以在开发板上使用。
+
+Nginx
+-----
+
+Nginx是一个高性能的HTTP和反向代理web服务器，同时也提供了IMAP/POP3/SMTP服务。它具有非常好的稳定性，拥有丰富的功能集，以及对系统资源的消耗极低。
+
+PHP
+---
+
+PHP即
+“超文本预处理器”，是一种通用开源脚本语言。PHP是在服务器端执行的脚本语言，与C语言类似，是常用的网站编程语言。PHP独特的语法混合了C、Java、Perl以及
+PHP 自创的语法，利于学习，使用广泛，主要适用于Web开发领域。
+
+安装
+----
+
+更新软件源
+~~~~~~~~~~
+
+此步骤不一定是要做的，如果你是新刷的系统，那么就需要更新一下，如果你在之前的操作都更新过了，那么这也不需要去更新它。
+
+.. code:: bash
+
+    sudo apt-get update
+    sudo apt-get upgrade
+
+安装Nginx
+~~~~~~~~~
+
+.. code:: bash
+
+    sudo apt-get -y install nginx
+
+安装PHP
+~~~~~~~
+
+此处安装的版本是7.3版本。
+
+.. code:: bash
+
+    sudo apt-get -y install php7.3-fpm
+
+启动Nginx
+---------
+
+在安装完成后可以去启动它。
+
+.. code:: bash
+
+    sudo systemctl start nginx
+
+配置Nginx使用PHP
+----------------
+
+``/etc/nginx/sites-enabled/default`` 文件是Nginx的配置文件，在安装完成后就已经存在的，并且有默认的配置，而且PHP相关的配置也是默认在里面的，只不过被注释了，只需要打开即可：
+
+.. code:: bash
+
+    sudo nano /etc/nginx/sites-enabled/default
+
+配置完成的代码如下，如果不知道改哪一句，就直接复制粘贴过去替换掉就好了：
+
+.. code:: bash
+
+    server {
+        listen 80 default_server;
+        listen [::]:80 default_server;
+
+        # SSL configuration
+        #
+        # listen 443 ssl default_server;
+        # listen [::]:443 ssl default_server;
+        #
+        # Note: You should disable gzip for SSL traffic.
+        # See: https://bugs.debian.org/773332
+        #
+        # Read up on ssl_ciphers to ensure a secure configuration.
+        # See: https://bugs.debian.org/765782
+        #
+        # Self signed certs generated by the ssl-cert package
+        # Don't use them in a production server!
+        #
+        # include snippets/snakeoil.conf;
+
+        root /var/www/html;
+
+        # Add index.php to the list if you are using PHP
+        index index.html index.htm index.nginx-debian.html;
+
+        server_name _;
+
+        location / {
+            # First attempt to serve request as file, then
+            # as directory, then fall back to displaying a 404.
+            #try_files $uri $uri/ =404;
+            try_files $uri /index.php$is_args$args;
+        }
+
+        # pass PHP scripts to FastCGI server
+        # 主要修改这下面的代码
+        #
+        location ~ \.php$ {
+            include snippets/fastcgi-php.conf;
+        #
+        #   # With php-fpm (or other unix sockets):
+            fastcgi_pass unix:/run/php/php7.3-fpm.sock;
+        #   # With php-cgi (or other tcp sockets):
+        #   fastcgi_pass 127.0.0.1:9000;
+        }
+
+        # deny access to .htaccess files, if Apache's document root
+        # concurs with nginx's one
+        #
+        location ~ /\.ht {
+            deny all;
+        }
+    }
+
+创建index.php
+-------------
+
+简单编写一个PHP文件，放在 ``/var/www/html/`` 目录下，这个目录是Nginx部署的的网站默认路径，通过Nginx的配置文件可以修改成其他目录，但每次修改配置后都要重新加载Nginx。
+
+index.php文件内容如下：
+
+.. code:: php
+
+    <?php
+        phpinfo();
+    ?>
+
+它主要是调用了 ``phpinfo()`` 这个函数，它会列举出来很多有关自己系统的有用信息，例如系统相关的属性、名称、预定义变量、已经加载的
+PHP 模块和配置信息。
+
+重新加载Nginx
+-------------
+
+每次修改配置后都要重新加载Nginx，才能生效，如果配置文件的配置不正确，或者语法出现错误，则会加载失败，就需要去检查配置文件的代码是否正确。
+
+.. code:: bash
+
+    sudo systemctl reload nginx
+
+访问web服务器
+-------------
+
+首先开发板要插入网线或者连接到wifi，使用 ``ifconfig`` 命令查看开发板当前的IP地址，比如我的IP地址就是 ``192.168.0.231`` 。
+
+.. code:: bash
+
+    ifconfig
+
+    eth1: flags=4163<UP,BROADCAST,RUNNING,MULTICAST>  mtu 1500
+            inet 192.168.0.231  netmask 255.255.255.0  broadcast 192.168.0.255
+            inet6 fe80::8813:d1ff:fec4:d5b6  prefixlen 64  scopeid 0x20<link>
+            ether 8a:13:d1:c4:d5:b6  txqueuelen 1000  (Ethernet)
+            RX packets 2820772  bytes 271315620 (258.7 MiB)
+            RX errors 1  dropped 0  overruns 0  frame 1
+            TX packets 372530  bytes 75563693 (72.0 MiB)
+            TX errors 0  dropped 0 overruns 0  carrier 0  collisions 0
+
+打开浏览器，输入你自己的IP地址 ``192.168.0.231`` ，然后回车，就可以看到一个网页了，这里面显示的就是我们的web服务器的内容，比如开发板的系统、名字、PHP相关的信息等：
+
+.. figure:: media/using_php001.png
+   :alt: using_php001
+
+   using_php001
+
diff --git a/documentation/linux_env/using_qtsqlite.rst b/documentation/linux_env/using_qtsqlite.rst
new file mode 100644
index 0000000000000000000000000000000000000000..c88452efe30066e2261024c504622b6b86ea6e61
--- /dev/null
+++ b/documentation/linux_env/using_qtsqlite.rst
@@ -0,0 +1,228 @@
+Qt使用SQLite
+============
+
+-  平台：野火imx6ull开发板
+-  系统：Debian
+-  Qt的SQLite插件：libqt5sql5
+
+在上一章节的时候我们简单说了Debian开发板使用SQLite相关的内容，而且Qt中还是会使用到SQLite作为数据库的，在qt里面称之为sql。
+
+我们简单说说在Debian开发板上，Qt使用SQLite。
+
+在虚拟机上运行demo
+------------------
+
+如果你没有搭建好Qt的交叉编译环境，那么请参考
+`Qt交叉编译环境搭建 <https://tutorial.linux.doc.embedfire.com/zh_CN/latest/linux_env/qt_cross_compiling.html>`__
+
+搭建好Qt的交叉编译环境后，打开qt
+creator，选择一个sql相关的demo，这里面的demo有很多，我们选择books这个demo，
+
+这个Books示例展示了如何将Qt的SQL类与模型/视图框架一起使用，以创建丰富的用户界面来存储数据库中的信息。
+
+.. figure:: media/using_qtsql001.png
+   :alt: using_qtsql001
+
+   using_qtsql001
+首先我们先在虚拟机上测试能否正常运行，选择对应的构建套件：
+
+.. figure:: media/using_qtsql002.png
+   :alt: using_qtsql002
+
+   using_qtsql002
+在选择完毕后，点击构建，编译是不会出错的，因为这是qt官方的demo，接着点击运行按钮，此时在虚拟机上出现了books这个应用程序的界面，它的上半部分是数据的显示区域，它主要是从数据库中读取数据并显示出来，下半部分则是数据修改的区域。
+
+有关书籍集合的信息保存在数据库中，这些书按作者、标题、体裁和出版年份分类，所有的书籍使用系统分配评级，每本系统都被分配星级。
+一本书的星星越多，它的评级越好。完美可以通过手动去修改这些数据，然后显示出来。
+
+.. figure:: media/using_qtsql003.png
+   :alt: using_qtsql003
+
+   using_qtsql003
+编译开发板上运行的demo
+----------------------
+
+既然在虚拟机上运行这个demo通过了，我们可以在开发板上运行它，首先选择在开发板上的构建套件，然后编译：
+
+.. figure:: media/using_qtsql004.png
+   :alt: using_qtsql004
+
+   using_qtsql004
+在编译完成后，可以打开这个demo对应的目录，可以看到一个books可执行文件：
+
+.. figure:: media/using_qtsql005.png
+   :alt: using_qtsql005
+
+   using_qtsql005
+通过file命令去查看它的文件类型，它是32位的：
+
+.. code:: bash
+
+    file books
+
+    books: ELF 32-bit LSB executable, ARM, EABI5 version 1 (SYSV), dynamically linked, interpreter /lib/ld-, for GNU/Linux 3.2.0, with debug_info, not stripped
+
+开发板的环境处理
+----------------
+
+首先要使用已经发布的Debian系统，可以选择纯净版的Debian镜像 ``Debian Buster Lite`` ，也可以选择动态版本的Qt镜像 ``Full Feature QT_App`` ，但是注意 **不要选择其他版本** 。
+
+Debian Buster Lite版本
+~~~~~~~~~~~~~~~~~~~~~~
+
+如果你选择的是纯净版的Debian镜像 ``Debian Buster Lite`` ，我们要安装动态版本的qt-app，直接使用以下指令安装即可：
+
+.. code:: bash
+
+    sudo apt-get install qt-app
+
+安装Qt的sql插件：
+
+.. code:: bash
+
+    sudo apt-get -y install libqt5sql5
+
+如果没有发现 ``qt-app`` 安装包，可以使用以下命令更新一下apt命令的软件包缓存再安装：
+
+.. code:: bash
+
+    sudo apt-get update
+
+在安装完成后，可以发现 ``/home/debian`` 目录下多了qt-app文件夹，这里就是我们出厂提供的Qt应用程序，可以直接使用以下命令运行它，野火提供了run.sh运行Qt应用程序的脚本，这样子就不需要我们配置环境变量：
+
+.. code:: bash
+
+    # 进入qt-app目录
+    cd qt-app
+
+    # 运行
+    sudo ./run.sh
+
+如果能成功运行，则可以 **将我们编译例程的可执行文件books放到qt-app目录下** ，然后编辑run.sh脚本，主要是修改脚本中的最后一行，将运行官方的App改为自己的Qt例程books。（编辑可以使用nano编辑器进行编辑）
+
+.. code:: bash
+
+    #! /bin/sh
+
+    type devscan
+
+    if [ $? -eq 0 ]; then
+        eventx=$(devscan "goodix-ts")
+        echo "eventx=$eventx"
+        if [ ! -f "/etc/pointercal" ]; then
+            type devscan
+            if [ $? -eq 0 ]; then
+                ts_calibrate
+            fi
+        fi
+    else
+        echo "please install devscan"
+        echo
+        echo "sudo apt-get install devscan"
+        exit
+    fi
+
+    export APP_DIR=/home/debian/qt-app
+    export QT_QPA_PLATFORM_PLUGIN_PATH=/usr/lib/arm-linux-gnueabihf/qt5/plugins/
+    export LD_LIBRARY_PATH=$LD_LIBRARY_PATH:$APP_DIR/libskin:$APP_DIR/libqui:$APP_DIR/libffmpeg:/usr/lib:/lib
+    export QT_QPA_FONTDIR=/usr/share/fonts/SourceHanSans
+    export PATH=$PATH:$QT_DIR/libexec
+    export QT_QPA_PLATFORM=linuxfb:fb=/dev/fb0
+    export TSLIB_CONFFILE=/etc/ts.conf
+    export TSLIB_CALIBFILE=/etc/pointercal
+    export QT_QPA_GENERIC_PLUGINS=tslib:/dev/input/$eventx
+    export QWS_MOUSE_PROTO=tslib
+    export QT_QPA_EVDEV_TOUCHSCREEN_PARAMETERS=/dev/input/$eventx:rotate=180:invertx
+
+    # start app...
+    # $APP_DIR/App
+
+    # 这里是要运行的Qt程序
+    $APP_DIR/books
+
+保存并且运行：
+
+.. code:: bash
+
+    # 运行
+    sudo ./run.sh
+
+此时我们的开发板上运行的就是Qt的例程，效果如下：
+
+.. figure:: media/using_qtsql006.png
+   :alt: using_qtsql006
+
+   using_qtsql006
+Full Feature QT_App版本
+~~~~~~~~~~~~~~~~~~~~~~~~
+
+而如果你选择的是动态版本的Qt镜像 ``Full Feature QT_App`` ，则无需安装qt-app，因为在系统中就已经存在了qt相关的环境，并且在 ``/home/debian`` 路径下就也存在了qt-app应用程序。
+
+需要安装Qt的sql插件：
+
+.. code:: bash
+
+    sudo apt-get -y install libqt5sql5
+
+如果不能安装成功，可以使用以下命令更新一下apt命令的软件包缓存再安装：
+
+.. code:: bash
+
+    sudo apt-get update
+
+**将我们编译例程的可执行文件books放到qt-app目录下** ，然后编辑run.sh脚本，主要是修改脚本中的最后一行，将运行官方的App改为自己的Qt例程books。（编辑可以使用nano编辑器进行编辑）
+
+.. code:: bash
+
+    #! /bin/sh
+
+    type devscan
+
+    if [ $? -eq 0 ]; then
+        eventx=$(devscan "goodix-ts")
+        echo "eventx=$eventx"
+        if [ ! -f "/etc/pointercal" ]; then
+            type devscan
+            if [ $? -eq 0 ]; then
+                ts_calibrate
+            fi
+        fi
+    else
+        echo "please install devscan"
+        echo
+        echo "sudo apt-get install devscan"
+        exit
+    fi
+
+    export APP_DIR=/home/debian/qt-app
+    export QT_QPA_PLATFORM_PLUGIN_PATH=/usr/lib/arm-linux-gnueabihf/qt5/plugins/
+    export LD_LIBRARY_PATH=$LD_LIBRARY_PATH:$APP_DIR/libskin:$APP_DIR/libqui:$APP_DIR/libffmpeg:/usr/lib:/lib
+    export QT_QPA_FONTDIR=/usr/share/fonts/SourceHanSans
+    export PATH=$PATH:$QT_DIR/libexec
+    export QT_QPA_PLATFORM=linuxfb:fb=/dev/fb0
+    export TSLIB_CONFFILE=/etc/ts.conf
+    export TSLIB_CALIBFILE=/etc/pointercal
+    export QT_QPA_GENERIC_PLUGINS=tslib:/dev/input/$eventx
+    export QWS_MOUSE_PROTO=tslib
+    export QT_QPA_EVDEV_TOUCHSCREEN_PARAMETERS=/dev/input/$eventx:rotate=180:invertx
+
+    # start app...
+    # $APP_DIR/App
+
+    # 这里是要运行的Qt程序
+    $APP_DIR/books
+
+保存并且运行：
+
+.. code:: bash
+
+    # 运行
+    sudo ./run.sh
+
+效果也是一样的。
+
+.. figure:: media/using_qtsql006.png
+   :alt: using_qtsql006
+
+   using_qtsql006
+
diff --git a/documentation/linux_env/using_sqlite.rst b/documentation/linux_env/using_sqlite.rst
new file mode 100644
index 0000000000000000000000000000000000000000..81195d598915455e0306efdaafdd9eabe0a91daa
--- /dev/null
+++ b/documentation/linux_env/using_sqlite.rst
@@ -0,0 +1,506 @@
+在Debian使用SQLite
+==================
+
+-  平台：野火imx6ull开发板
+-  系统：Debian
+-  SQLite版本：SQLite3
+
+**注意：此处的操作是在野火imx6ull开发板上（运行的是Debian系统），而非虚拟机。**
+
+SQLite 简介
+-----------
+
+SQLite是一款轻量级数据库，是一个关系型数据库（RDBMS）管理系统，它包含在一个相对小的C库中，实现了自给自足的、无服务器的、零配置的、事务性的
+SQL
+数据库引擎。在很多嵌入式产品中使用了它，它占用资源非常的低，在嵌入式设备中，可能只需要几百K的内存就够了。它能够支持Windows/Linux/Unix/Android/IOS等等主流的操作系统，同时能够跟很多程序语言相结合，比如
+C#、PHP、Java等，更重要的是 SQLite
+文件格式稳定，跨平台且向后兼容，开发人员保证至少在2050年之前保持这种格式。而且速度极快，目前是在世界上最广泛部署的
+SQL 数据库，据官网统计活跃使用的SQLite数据库超过1万亿，更重要的是SQLite
+源代码不受版权限制，任何人都可以免费使用于任何目的。
+
+大家可以参考官网的介绍： https://www.sqlite.org/index.html
+
+安装SQLite
+----------
+
+我们要在Debian开发板上安装SQLite，使用的版本是SQLite3。
+
+SQLite
+的一个重要的特性是零配置的，这意味着不需要复杂的安装或管理，直接一条命令安装即可。
+
+为了确保我们的版本是最新版本，让我们使用apt命令更新本地apt包索引和升级系统：
+
+.. code:: bash
+
+    sudo apt-get update
+    sudo apt-get -y upgrade
+
+``-y`` 标志将确认我们同意所有要安装的项目。
+
+.. code:: bash
+
+    sudo apt-get -y install sqlite3
+
+因为SQLite非常小，很快就安装完了，可以看到安装完成的最后输出了SQLite的版本信息，所以安装的版本是 ``3.27.2-3`` ：
+
+.. code:: bash
+
+    ···
+    Preparing to unpack .../sqlite3_3.27.2-3_armhf.deb ...
+    Unpacking sqlite3 (3.27.2-3) ...
+    Setting up sqlite3 (3.27.2-3) ...
+
+SQLite命令
+----------
+
+我们简单讲解 SQLite 编程所使用的简单却有用的命令，这些命令被称为 SQLite
+的点命令。
+
+在终端运行 ``sqlite3`` 命令，可以发现进入了 SQLite
+命令终端，并且显示了SQLite版本相关的信息
+
+在 SQLite 命令提示符下，我们可以使用各种 SQLite
+的点命令，比如我们输入一个 ``.help`` 命令，这是一个帮助命令，可以帮助开发者查看
+SQLite
+支持所有的点命令，注意，这个help命令前有一个 **点** 的，这也是为什么这些命令被称之为点命令的原因。
+
+当输入 ``.help`` 命令后，可以看到非常多的点命令：
+
+.. code:: bash
+
+    ➜  ~ sqlite3
+    SQLite version 3.27.2 2019-02-25 16:06:06
+    Enter ".help" for usage hints.
+    Connected to a transient in-memory database.
+    Use ".open FILE name" to reopen on a persistent database.
+    sqlite> .help
+    .archive ...             Manage SQL archives
+    .auth ON|OFF             Show authorizer callbacks
+    .backup ?DB? FILE        Backup DB (default "main") to FILE
+    .bail on|off             Stop after hitting an error.  Default OFF
+    .binary on|off           Turn binary output on or off.  Default OFF
+    .cd DIRECTORY            Change the working directory to DIRECTORY
+    .changes on|off          Show number of rows changed by SQL
+    .check GLOB              Fail if output since .testcase does not match
+    .clone NEWDB             Clone data into NEWDB from the existing database
+    .databases               List names and files of attached databases
+    .dbconfig ?op? ?val?     List or change sqlite3_db_config() options
+    .dbinfo ?DB?             Show status information about the database
+    .dump ?TABLE? ...        Render all database content as SQL
+    .echo on|off             Turn command echo on or off
+    ···
+    ···
+
+其实这里的命令非常多，我只截取了一部分，以下是部分点命令的功能介绍，其实没必要全部记住，在需要的时候通过 ``.help`` 命令查询一下即可：
+
++--------------------------+-------------------------------------------------------------------------------------------+
+| 命令                     | 功能                                                                                      |
++==========================+===========================================================================================+
+| .archive ...             | 管理SQL存档                                                                               |
++--------------------------+-------------------------------------------------------------------------------------------+
+| .auth ON \| OFF          | 显示授权者回调                                                                            |
++--------------------------+-------------------------------------------------------------------------------------------+
+| .backup ?DB? FILE        | 备份 DB 数据库（默认是 "main"）到 FILE 文件                                               |
++--------------------------+-------------------------------------------------------------------------------------------+
+| .restore ?DB? FILE       | 从FILE文件恢复DB的内容（默认为“ main”）                                                   |
++--------------------------+-------------------------------------------------------------------------------------------+
+| .databases               | 列出数据库的名称及其所依附的文件                                                          |
++--------------------------+-------------------------------------------------------------------------------------------+
+| .dump ?TABLE?            | 以 SQL 文本格式转储数据库。如果指定了 TABLE 表，则只转储匹配 LIKE 模式的 TABLE 表。       |
++--------------------------+-------------------------------------------------------------------------------------------+
+| .echo ON\|OFF            | 开启或关闭 echo 命令。                                                                    |
++--------------------------+-------------------------------------------------------------------------------------------+
+| .import FILE TABLE       | 导入来自 FILE 文件的数据到 TABLE 表中。                                                   |
++--------------------------+-------------------------------------------------------------------------------------------+
+| .indices ?TABLE?         | 显示所有索引的名称。如果指定了 TABLE 表，则只显示匹配 LIKE 模式的 TABLE 表的索引。        |
++--------------------------+-------------------------------------------------------------------------------------------+
+| .log FILE\|off           | 开启或关闭日志。FILE 文件可以是 stderr（标准错误）/stdout（标准输出）。                   |
++--------------------------+-------------------------------------------------------------------------------------------+
+| .mode MODE ?TABLE?       | 设置输出模式，可选泽的模式：csv 、column 、html、insert、line 、list、list 、tabs 、tcl   |
++--------------------------+-------------------------------------------------------------------------------------------+
+| .open ?OPTIONS? ?FILE?   | 关闭现有的数据库并重新打开文件                                                            |
++--------------------------+-------------------------------------------------------------------------------------------+
+| .output FILE name        | 发送输出到 FILE name 文件。                                                               |
++--------------------------+-------------------------------------------------------------------------------------------+
+| .output stdout           | 发送输出到屏幕。                                                                          |
++--------------------------+-------------------------------------------------------------------------------------------+
+| .print STRING...         | 逐字地输出 STRING 字符串。                                                                |
++--------------------------+-------------------------------------------------------------------------------------------+
+| .quit                    | 退出 SQLite 提示符终端。                                                                  |
++--------------------------+-------------------------------------------------------------------------------------------+
+| .read FILE name          | 从FILE读取输入                                                                            |
++--------------------------+-------------------------------------------------------------------------------------------+
+| .schema ?PATTERN?        | 显示与PATTERN匹配的CREATE语句                                                             |
++--------------------------+-------------------------------------------------------------------------------------------+
+| .show                    | 显示各种设置的当前值                                                                      |
++--------------------------+-------------------------------------------------------------------------------------------+
+| .stats ON\|OFF           | 开启或关闭统计。                                                                          |
++--------------------------+-------------------------------------------------------------------------------------------+
+| .tables ?TABLE?          | 列出与LIKE模式TABLE匹配的表的名称                                                         |
++--------------------------+-------------------------------------------------------------------------------------------+
+
+创建数据库
+----------
+
+首先我们创建一个数据库，SQLite 的 sqlite3 命令被用来创建新的 SQLite
+数据库，我们不需要任何特殊的权限即可创建一个数据，如果路径下存在相同名字的数据库则直接打开该数据库而不是重新创建。
+
+-  创建test.db数据库
+
+.. code:: bash
+
+    ➜  ~ sqlite3 test.db  
+
+    SQLite version 3.27.2 2019-02-25 16:06:06
+    Enter ".help" for usage hints.
+    sqlite>
+
+创建表
+------
+
+SQLite 的 ``CREATE TABLE``
+语句用于在任何给定的数据库创建一个新表。创建基本表，涉及到命名表、定义列及每一列的数据类型。
+
+``CREATE TABLE`` 语句的基本语法如下：
+
+.. code:: bash
+
+    CREATE TABLE database_name.table_name(
+       column1 datatype  PRIMARY KEY(one or more columns),
+       column2 datatype,
+       column3 datatype,
+       .....
+       columnN datatype,
+    );
+
+-  ``database_name.table_name`` 在数据库中是唯一的。
+-  ``column1, column2, ... columnN`` ：表示的是数据库中的列。
+-  ``datatype`` ：每列的数据类型，可选INT、TEXT、CHAR、REAL等类型。
+-  ``PRIMARY`` ：表示第1列作为主键。
+-  ``KEY`` ：关键字，一个或者多个。
+
+比如下面的语句就创建一个班级，班级中有学生的id，名字、年龄、总分数等列，id
+作为主键， ``NOT NULL`` 的约束表示在表中创建纪录时这些字段不能为
+NULL，此处使用小写字母表示用户可以修改的内容。
+
+.. code:: bash
+
+    CREATE TABLE class(
+       id INT PRIMARY KEY     NOT NULL,
+       name           TEXT    NOT NULL,
+       age            INT     NOT NULL,
+       score          INT
+    );
+
+这样子创建的数据库就类似一个Excel表格，差不多是这样子的类型：
+
+.. code:: bash
+
+    id          name        age         score     
+    ----------  ----------  ----------  ----------
+
+在创建完成后，可以使用 SQLIte 命令中的 ``.tables``
+命令来验证表是否已成功创建，该命令用于列出附加数据库中的所有表。
+
+.. code:: bash
+
+    sqlite> .tables
+    class
+
+插入数据
+--------
+
+SQLite 的 ``INSERT INTO`` 语句用于向数据库的某个表中添加新的数据行。
+
+``INSERT INTO`` 语句有两种基本语法。
+
+为表中部分列添加对应的值，可以通过以下方法：
+
+.. code:: bash
+
+    INSERT INTO TABLE_NAME (column1, column2, column3,...columnN)  
+    VALUES (value1, value2, value3,...valueN);
+
+-  ``TABLE_NAME`` ：表示表的名字，是数据库中唯一的。
+
+-  ``column1, column2, ... columnN`` ：表示要插入数据的表中的列的 **名称** ，注意这里是列的名称。
+
+-  ``value1, value2, value3, ... valueN`` ：表示要插入数据的表中的列的值。
+
+如果要为表中的所有列添加值，我们也可以不需要在 SQLite
+查询中指定列名称，但要确保值的顺序与列在表中的顺序一致，SQLite 的 INSERT
+INTO 语法如下：
+
+.. code:: bash
+
+    INSERT INTO TABLE_NAME VALUES (value1,value2,value3,...valueN);
+
+-  TABLE_NAME：表示表的名字，是数据库中唯一的。
+
+-  value1, value2, value3,...valueN：表示要插入数据的表中的列的值。
+
+**注意，插入值的类型要与表中列指定的类型要匹配的。**
+
+我们来给class表添加对应的值：
+
+-  语法1格式：
+
+.. code:: bash
+
+    INSERT INTO class (id, name, age, score)
+    VALUES (1, 'liuyi', 22, 610);
+
+    INSERT INTO class (id, name, age, score)
+    VALUES (2, 'chener', 19, 621);
+
+    INSERT INTO class (id, name, age, score)
+    VALUES (3, 'zhangsan', 23, 601);
+
+    INSERT INTO class (id, name, age, score)
+    VALUES (4, 'lisi', 21, 666);
+
+    INSERT INTO class (id, name, age, score)
+    VALUES (5, 'wangwu', 20, 629);
+
+    INSERT INTO class (id, name, age, score)
+    VALUES (6, 'zhaoliu', 22, 621);
+
+    INSERT INTO class (id, name, age, score)
+    VALUES (7, 'sunqi', 20, 611);
+
+    INSERT INTO class (id, name, age, score)
+    VALUES (8, 'zhouba', 22, 591);
+
+    INSERT INTO class (id, name, age, score)
+    VALUES (9, 'wujiu', 23, 625);
+
+    INSERT INTO class (id, name, age, score)
+    VALUES (10, 'zhengshi', 21, 621);
+
+-  语法2格式：
+
+.. code:: bash
+
+    INSERT INTO class VALUES (1, 'liuyi', 22, 610);
+
+    INSERT INTO class VALUES (2, 'chener', 19, 621);
+
+    INSERT INTO class VALUES (3, 'zhangsan', 23, 601);
+
+    INSERT INTO class VALUES (4, 'lisi', 21, 666);
+
+    INSERT INTO class VALUES (5, 'wangwu', 20, 629);
+
+    INSERT INTO class VALUES (6, 'zhaoliu', 22, 621);
+
+    INSERT INTO class VALUES (7, 'sunqi', 20, 611);
+
+    INSERT INTO class VALUES (8, 'zhouba', 22, 591);
+
+    INSERT INTO class VALUES (9, 'wujiu', 23, 625);
+
+    INSERT INTO class VALUES (10, 'zhengshi', 21, 621);
+
+这两个语法得出的结果是一样的，随便选择一个即可。
+
+查找数据
+--------
+
+SQLite 的 ``SELECT`` 语句用于从 SQLite
+数据库表中获取数据，并且以结果表的形式返回数据。
+
+SQLite 的 ``SELECT`` 语句的基本语法如下：
+
+.. code:: bash
+
+    SELECT column1, column2, ... columnN FROM table_name;
+
+-  ``column1, column2, ... columnN`` ：表示要查找数据的表中的列的 **名称** ，注意这里是列的名称，当然可以使用
+   ``*`` 符号表示要查找所有的列。
+
+-  ``table_name`` ：表示要查找数据库中的表名称，它在数据库中是唯一的。
+
+查找刚刚创建的class表操作如下：
+
+.. code:: bash
+
+    sqlite> SELECT * FROM class;
+
+    1|liuyi|22|610
+    2|chener|19|621
+    3|zhangsan|23|601
+    4|lisi|21|666
+    5|wangwu|20|629
+    6|zhaoliu|22|621
+    7|sunqi|20|611
+    8|zhouba|22|591
+    9|wujiu|23|625
+    10|zhengshi|21|621
+
+你会发现这些表的格式是很乱，不直观，那么你可以通过 ``.header`` 命令显示表头，通过 ``.mode`` 设置显示的模式：
+
+.. code:: bash
+
+    .header on
+    .mode column
+
+然后再次查找所有的内容：
+
+.. code:: bash
+
+    sqlite> SELECT * FROM class;
+
+    id          name        age         score     
+    ----------  ----------  ----------  ----------
+    1           liuyi       22          610       
+    2           chener      19          621       
+    3           zhangsan    23          601       
+    4           lisi        21          666       
+    5           wangwu      20          629       
+    6           zhaoliu     22          621       
+    7           sunqi       20          611       
+    8           zhouba      22          591       
+    9           wujiu       23          625       
+    10          zhengshi    21          621   
+
+这一次就好看多了，当然你还可以进行排序。
+
+数据排序
+--------
+
+SQLite 的 ``ORDER BY``
+语句是用来基于一个或多个列按升序或降序顺序排列数据。
+
+``ORDER BY`` 语句的基本语法如下：
+
+.. code:: bash
+
+    SELECT column-list 
+    FROM table_name 
+    [WHERE condition] 
+    [ORDER BY column1, column2, .. columnN] [ASC | DESC];
+
+比如按照某一列进行排序，此处选择 ``score`` 列，ASC表示升序，DESC表示降序：
+
+.. code:: bash
+
+    sqlite> SELECT * FROM class ORDER BY score ASC;
+
+    id          name        age         score     
+    ----------  ----------  ----------  ----------
+    8           zhouba      22          591       
+    3           zhangsan    23          601       
+    1           liuyi       22          610       
+    7           sunqi       20          611       
+    2           chener      19          621       
+    6           zhaoliu     22          621       
+    10          zhengshi    21          621       
+    9           wujiu       23          625       
+    5           wangwu      20          629       
+    4           lisi        21          666 
+
+.. code:: bash
+
+    sqlite> SELECT * FROM class ORDER BY score DESC;
+
+    id          name        age         score     
+    ----------  ----------  ----------  ----------
+    4           lisi        21          666       
+    5           wangwu      20          629       
+    9           wujiu       23          625       
+    2           chener      19          621       
+    6           zhaoliu     22          621       
+    10          zhengshi    21          621       
+    7           sunqi       20          611       
+    1           liuyi       22          610       
+    3           zhangsan    23          601       
+    8           zhouba      22          591   
+
+导出数据库为SQL脚本
+-------------------
+
+我们可以通过 ``.dump`` 命令导出数据库为一个sql脚本，也可以通过这个脚本还原一个数据库，具体操作如下：
+
+在shell终端中（注意不是在sqlite提示符终端）通过以下命令即可导出数据库为sql脚本：
+
+.. code:: bash
+
+    sqlite3 test.db .dump > test.sql 
+
+.. code:: bash
+
+    # 当前路径下存在test.db数据库
+    ➜  ~ ls
+    bin  mountnfs  qt-app  test.db
+
+    # 导出数据库为sql脚本
+    ➜  ~ sqlite3 test.db .dump > test.sql 
+
+    # 生成test.sql脚本
+    ➜  ~ ls
+    bin  mountnfs  qt-app  test.db  test.sql
+
+    # 查看脚本的内容
+    ➜  ~ cat test.sql 
+    PRAGMA foreign_keys=OFF;
+    BEGIN TRANSACTION;
+    CREATE TABLE class(
+       id INT PRIMARY KEY     NOT NULL,
+       name           TEXT    NOT NULL,
+       age            INT     NOT NULL,
+       score          INT
+    );
+    INSERT INTO class VALUES(1,'liuyi',22,610);
+    INSERT INTO class VALUES(2,'chener',19,621);
+    INSERT INTO class VALUES(3,'zhangsan',23,601);
+    INSERT INTO class VALUES(4,'lisi',21,666);
+    INSERT INTO class VALUES(5,'wangwu',20,629);
+    INSERT INTO class VALUES(6,'zhaoliu',22,621);
+    INSERT INTO class VALUES(7,'sunqi',20,611);
+    INSERT INTO class VALUES(8,'zhouba',22,591);
+    INSERT INTO class VALUES(9,'wujiu',23,625);
+    INSERT INTO class VALUES(10,'zhengshi',21,621);
+    COMMIT;
+
+从SQL脚本导入数据库
+-------------------
+
+这一步的操作与上一步操作是相反的，可以通过以下命令导入SQL脚本生成一个新的数据库：
+
+.. code:: bash
+
+    sqlite3 new.db < test.sql
+
+注意，这里的new.db
+是通过test.sql生成的，它里面的内容与test.db是完全一致的。
+
+.. code:: bash
+
+    # 从SQL脚本导入数据库
+    ➜  ~ sqlite3 new.db < test.sql
+
+    # 生成新的数据库new.db
+    ➜  ~ ls
+    bin  mountnfs  new.db  qt-app  test.db  test.sql
+
+    # 进入新的数据库中并查询数据表
+    ➜  ~ sqlite3 new.db 
+    SQLite version 3.27.2 2019-02-25 16:06:06
+    Enter ".help" for usage hints.
+    sqlite> .header on
+    sqlite> .mode column
+    sqlite> SELECT * FROM class;
+    id          name        age         score     
+    ----------  ----------  ----------  ----------
+    1           liuyi       22          610       
+    2           chener      19          621       
+    3           zhangsan    23          601       
+    4           lisi        21          666       
+    5           wangwu      20          629       
+    6           zhaoliu     22          621       
+    7           sunqi       20          611       
+    8           zhouba      22          591       
+    9           wujiu       23          625       
+    10          zhengshi    21          621     
+
+至此，数据库的讲解完成，更多知识大家可以自行学习，此处仅告诉大家野火开发板上可以使用数据库。
diff --git a/documentation/linux_iot/ATGM332D.rst b/documentation/linux_iot/ATGM332D.rst
new file mode 100644
index 0000000000000000000000000000000000000000..cb37a63b0614c820c5a526882d326824586fa3e1
--- /dev/null
+++ b/documentation/linux_iot/ATGM332D.rst
@@ -0,0 +1,503 @@
+Debian使用BH-ATGM332D
+=====================
+
+本章旨在帮助用户正确构建 BH-ATGM332D
+模块的使用环境，引导用户快速使用该模块。
+
+BH-ATGM332D 简介
+----------------
+
+BH-ATGM332D 是野火设计的高性能、低功耗 GPS、
+北斗双模定位模块。它采用中科微电子公司的 ATGM332D-5N-31
+模组方案，可以通过串口向单片机系统和电脑输出 GPS
+及北斗定位信息，使用简单方便，其外观见图。
+
+.. figure:: ./media/ATGM332D001.png
+   :alt: ATGM332D001
+
+   ATGM332D001
+
+BH-ATGM332D 模块引脚说明如下：
+
+.. figure:: ./media/ATGM332D002.png
+   :alt: ATGM332D002
+
+   ATGM332D002
+
+BH-ATGM332D 模块的资源如下：
+
+.. figure:: ./media/ATGM332D003.png
+   :alt: ATGM332D003
+
+   ATGM332D003
+
+BH-ATGM332D 模块及其配套的有源天线如下：
+
+.. figure:: ./media/ATGM332D004.png
+   :alt: ATGM332D004
+
+   ATGM332D004
+
+测试 BH-ATGM332D
+----------------
+
+硬件接线
+~~~~~~~~
+
+BH-ATGM332D
+模块的硬件资源介绍完毕了，可以在Debian上使用它，我们开发板的左上角有预留了EBF
+Module 模块接口，直接将 BH-ATGM332D
+插在模块接口上即可（需要注意引脚位置）。
+
+如图所示：
+
+.. figure:: ./media/ATGM332D005.png
+   :alt: ATGM332D005
+
+   ATGM332D005
+
+fire-config打开USART3
+~~~~~~~~~~~~~~~~~~~~~
+
+1. 我们要验证一下我们板子上的串口3是可以正常工作的，运行以下命令，在fire-config工具打开串口3设备。
+
+.. code:: bash
+
+    sudo fire-config
+
+.. figure:: ./media/ATGM332D006.png
+   :alt: ATGM332D006
+
+   ATGM332D006
+
+2. 重启开发板。
+
+3. 重启之后查看dev目录下是否存在串口3设备：
+
+.. code:: bash
+
+    ls /dev/ttymxc2
+
+当存在/dev/ttymxc2的时候表示已经打开串口3设备。
+
+验证模块是否工作
+~~~~~~~~~~~~~~~~
+
+实现要验证模块是否工作了，我们在将模块插入开发板的 EBF Module
+模块接口后，BH-ATGM332D
+模块的LED灯会闪烁，如果没有则检查是否正常供电了。
+
+然后在linux的终端中运行以下命令：
+
+.. code:: bash
+
+    cat /dev/ttymxc2
+
+输出了以下内容则表示模块正常工作：
+
+.. code:: bash
+
+
+    $GPTXT,01,01,01,ANTENNA OK*35
+
+    $GNGGA,034101.000,2253.72536,N,11350.70190,E,1,22,0.7,48.8,M,0.0,M,,*4C
+
+    $GNGLL,2253.72536,N,11350.70190,E,034101.000,A,A*4A
+
+    $GPGSA,A,3,01,04,07,08,09,11,16,22,27,30,33,34,1.1,0.7,0.8*38
+
+    $BDGSA,A,3,03,06,08,10,11,12,13,16,,,,,1.1,0.7,0.8*26
+
+    $GPGSV,4,1,16,01,60,154,43,04,12,190,23,07,63,308,21,08,41,026,20*74
+
+    $GPGSV,4,2,16,09,21,224,15,11,75,044,31,16,12,089,21,17,09,242,*7F
+
+    $GPGSV,4,3,16,22,12,139,16,23,,,16,27,13,044,24,28,09,300,*41
+
+    $GPGSV,4,4,16,30,30,318,23,33,12,150,13,34,64,095,39,35,63,049,35*7B
+
+    $BDGSV,2,1,08,03,62,188,37,06,19,189,20,08,55,161,37,10,52,337,21*65
+
+    $BDGSV,2,2,08,11,70,264,18,12,46,028,21,13,35,187,38,16,21,195,39*64
+
+    $GNRMC,034101.000,A,2253.72536,N,11350.70190,E,0.00,315.42,220520,,,A*7B
+
+    $GNVTG,315.42,T,,M,0.00,N,0.00,K,A*22
+
+    $GNZDA,034101.000,22,05,2020,00,00*4A
+
+注意看输入的内容 “$GPTXT,01,01,01,ANTENNA OK\*35”
+，它表示模块正常运行，当然也可能是其他情况，比如：
+
+.. figure:: ./media/ATGM332D007.png
+   :alt: ATGM332D007
+
+   ATGM332D007
+
+图中的三种状态分别为开路（OPEN） 、 SHORT（短路） 及 OK（正常） ，
+测试时请确保天线处于 OK 状态
+
+注意：如果模块上电后输出的数据长期处于第一种状态（天线开路或者没连接天线），则应考虑转移一下定位模块天线的位置，一般在室内卫星信号会比较差，可到室外空旷的地方测试(如楼顶、阳台、窗边)。
+
+NMEA-0183
+---------
+
+NMEA-0183 协议简介
+~~~~~~~~~~~~~~~~~~
+
+BH-ATGM332D 模块通过 TTL 串口输出定位数据信息，这些信息默认采用
+NMEA-0183 4.0 协议， 输出的信息如前面的日志所示。
+
+NMEA 是美国国家海洋电子协会（National Marine Electronics Association
+）为海用电子设备制定的标准格式，目前已经成为了 GPS 导航设备统一的 RTCM
+标准协议， 本模块使用的 NMEA 4.0 版本协议支持
+GPS、北斗、海格纳斯等定位系统。NMEA-0183
+是一套定义接收机输出的标准信息，有几种不同的格式，每种都是独立相关的
+ASCII 格式， 使用逗号隔开数据，数据流长度从 30-100
+字符不等，通常以每秒间隔选择输出，最常用的格式为"GGA"，它包含了定位时间，纬度，经度，高度，定位所用的卫星数，
+DOP 值， 差分状态和校正时段等，其他的有速度，跟踪，日期等。 NMEA
+实际上已成为所有的定位接收机中最通用的数据输出格式。
+
+NMEA 解码库
+~~~~~~~~~~~
+
+了解了 NMEA 格式有之后，我们就可以编写相应的解码程序了，而程序员
+Tim(xtimor@gmail.com)提供了一个非常完善的 NMEA
+解码库，在以下网址可以下载到：http://nmea.sourceforge.net/
+，直接使用该解码库，可以避免重复发明轮子的工作。 在野火提供的 GPS
+模块资料的“NMEA0183 解码库源码”文件夹中也包含了该解码库的源码，
+野火提供的 STM32 程序就是使用该库来解码 NMEA 语句的。
+
+该解码库目前最新为 0.5.3 版本，它使用纯 C 语言编写，支持 windows、 winCE
+、UNIX 平台，支持解析 GPGGA， GPGSA,GPGSV,GPRMC,GPVTG
+这五种语句(这五种语句已经提供足够多的 GPS 信息)，解析得的 GPS
+数据信息以结构体存储，附加了地理学相关功能，可支持导航等数据工作，除了解析
+NMEA 语句，它还可以根据随机数产生 NMEA语句，方便模拟。 在该解码库之上，
+野火扩展了其对 NMEA-0183 4.0 版本的支持。
+
+在 Debian 上使用 BH-ATGM332D 模块
+---------------------------------
+
+更新软件源
+~~~~~~~~~~
+
+为了确保我们的软件包版本是最新版本，让我们使用apt命令更新本地apt包索引和升级系统：
+
+.. code:: bahs
+
+    sudo apt-get update
+
+手动安装相关的依赖包
+~~~~~~~~~~~~~~~~~~~~
+
+首先安装git make相关的依赖
+
+.. code:: bash
+
+    sudo apt-get -y install git make
+
+.. code:: bash
+
+    sudo apt-get -y install make
+
+拉取 nmealib 仓库
+~~~~~~~~~~~~~~~~~
+
+nmealib 仓库已经发布在github与gitee上，野火对改库进行了修改，以支持解析
+NMEA-0183 4.0 协议，
+
+在github拉取 nmealib 仓库
+
+.. code:: bash
+
+    git clone https://github.com/Embedfire/nmealib.git
+
+当然也可以从野火的gitee仓库拉取。
+
+.. code:: bash
+
+    git clone https://gitee.com/Embedfire/nmealib.git
+
+示例
+~~~~
+
+野火发布的 nmealib
+仓库已经提供了相关的demo例程，在samples目录下有5个文件夹，分别是：generate
+、 generator 、 math 、parse 、
+parse_ebf_module。他们都对应不同的例程：
+
+-  generate/generator ：这两个demo是产生随机 NMEA-0183
+   标准信息的，可以用来做调试使用。
+
+-  math：数学库，用来将这些 NMEA-0183
+   标准信息转换为数学相关的数据，比如经纬度、方位角等。
+
+-  parse：解析 NMEA-0183 标准信息的demo，这些 NMEA-0183
+   标准信息信息写在一个数组中。
+
+-  parse_ebf_module ：解析野火北斗定位模块的 NMEA-0183
+   标准信息的demo，它通过读取串口3设备得到 BH-ATGM332D
+   的数据，然后调用nmealib库去解析它。
+
+编译 & 运行
+~~~~~~~~~~~
+
+我们进入nmealib目录下，直接运行make命令去编译：
+
+.. code:: bash
+
+    ➜  nmealib git:(master) ✗ make
+
+    mkdir -p build/nmea_gcc
+    gcc  -I include  -c src/generate.c -o build/nmea_gcc/generate.o
+    gcc  -I include  -c src/generator.c -o build/nmea_gcc/generator.o
+    gcc  -I include  -c src/parse.c -o build/nmea_gcc/parse.o
+    gcc  -I include  -c src/parser.c -o build/nmea_gcc/parser.o
+    gcc  -I include  -c src/tok.c -o build/nmea_gcc/tok.o
+    gcc  -I include  -c src/context.c -o build/nmea_gcc/context.o
+    gcc  -I include  -c src/time.c -o build/nmea_gcc/time.o
+    gcc  -I include  -c src/info.c -o build/nmea_gcc/info.o
+    gcc  -I include  -c src/gmath.c -o build/nmea_gcc/gmath.o
+    gcc  -I include  -c src/sentence.c -o build/nmea_gcc/sentence.o
+    ar rsc lib/libnmea.a build/nmea_gcc/generate.o build/nmea_gcc/generator.o build/nmea_gcc/parse.o build/nmea_gcc/parser.o build/nmea_gcc/tok.o build/nmea_gcc/context.o build/nmea_gcc/time.o build/nmea_gcc/info.o build/nmea_gcc/gmath.o build/nmea_gcc/sentence.o
+    ranlib lib/libnmea.a
+    gcc  -I include  -c samples/generate/main.c -o samples/generate/main.o
+    gcc  samples/generate/main.o -lm -Llib -lnmea -o build/samples_generate
+    gcc  -I include  -c samples/generator/main.c -o samples/generator/main.o
+    gcc  samples/generator/main.o -lm -Llib -lnmea -o build/samples_generator
+    gcc  -I include  -c samples/parse/main.c -o samples/parse/main.o
+    gcc  samples/parse/main.o -lm -Llib -lnmea -o build/samples_parse
+    gcc  -I include  -c samples/parse_ebf_module/main.c -o samples/parse_ebf_module/main.o
+    gcc  samples/parse_ebf_module/main.o -lm -Llib -lnmea -o build/samples_parse_ebf_module
+    gcc  -I include  -c samples/math/main.c -o samples/math/main.o
+    gcc  samples/math/main.o -lm -Llib -lnmea -o build/samples_math
+    rm samples/math/main.o samples/parse_ebf_module/main.o samples/generator/main.o samples/parse/main.o samples/generate/main.o
+
+可以看到编译生成了libnmea.a库文件，并且将所有的samples都编译了，输出的结果在
+build/ 目录下，生成了对应的可执行文件，我们直接运行
+build/samples_parse_ebf_module 试一试：
+
+.. code:: bash
+
+    ➜  nmealib git:(master) ✗ ./build/samples_parse_ebf_module
+
+    时间：2020-05-22，14:50:31
+
+    纬度：22.895420,经度113.845100
+
+    海拔高度：49.200000 米 
+    速度：0.000000 km/h 
+    航向：315.420000 度
+    正在使用的GPS卫星：11,可见GPS卫星：15
+    正在使用的北斗卫星：11,可见北斗卫星：15
+    PDOP：1.400000,HDOP：0.700000，VDOP：1.200000
+
+可以看到已经输出了北斗定位相关的信息。
+
+示例代码
+~~~~~~~~
+
+实例的代码比较简单，主要流程是从 串口3
+设备读取数据，读取数据的流程基本如下：open打开设备，配置读取信息的参数，如波特率、停止位、校验位等，然后read读取数据，缓存到一个buff中；然后调用
+nmea_parse() 函数去解析数据，并将其打印出来。
+
+.. code:: c
+
+    #include <nmea/nmea.h>
+
+    #include <string.h>
+    #include <stdio.h>
+    #include <unistd.h>
+    #include <sys/types.h>
+    #include <sys/stat.h>
+    #include <fcntl.h>
+    #include <stdlib.h>
+    #include <stdint.h>
+    #include <termios.h>
+    #include <sys/ioctl.h>
+
+    void GMTconvert(nmeaTIME *SourceTime, nmeaTIME *ConvertTime, uint8_t GMT,uint8_t AREA);
+
+    void error(const char *str, int str_size)
+    {
+        printf("Error: ");
+        write(1, str, str_size);
+        printf("\n");
+    }
+
+    int main()
+    {
+        int fd;
+        int len;
+
+        nmeaINFO info;
+        nmeaPARSER parser;
+        nmeaTIME beiJingTime;    //北京时间
+        double deg_lat;//转换成[degree].[degree]格式的纬度
+        double deg_lon;//转换成[degree].[degree]格式的经度
+
+        char tmp_buf[200];
+        char buff[4096];
+
+        int size, it = 0;
+        nmeaPOS dpos;
+
+        fd = open("/dev/ttymxc2", O_RDONLY);
+
+        printf("fopen %d\n", fd);
+
+        if(!fd)
+            return -1;
+
+        // nmea_property()->trace_func = &trace;
+        nmea_property()->error_func = &error;
+
+        nmea_zero_INFO(&info);
+        nmea_parser_init(&parser);
+
+        struct termios opt;
+
+        //清空串口接收缓冲区
+        tcflush(fd, TCIOFLUSH);
+        // 获取串口参数opt
+        tcgetattr(fd, &opt);
+
+        //设置串口输出波特率
+        cfsetospeed(&opt, B9600);
+        //设置串口输入波特率
+        cfsetispeed(&opt, B9600);
+        //设置数据位数
+        opt.c_cflag &= ~CSIZE;
+        opt.c_cflag |= CS8;
+        //校验位
+        opt.c_cflag &= ~PARENB;
+        opt.c_iflag &= ~INPCK;
+        //设置停止位
+        opt.c_cflag &= ~CSTOPB;
+
+        //更新配置
+        tcsetattr(fd, TCSANOW, &opt);
+
+        while(1)
+        {
+            memset(buff, 0, 4096);
+            size = 0;
+            len = 0;
+            nmea_zero_INFO(&info);
+            nmea_parser_init(&parser);
+            for(it = 0; it < 32; it++) {
+                memset(tmp_buf, 0, 100);
+                size = (int)read(fd, tmp_buf, 100);
+                if (size > 1) {
+                    memcpy(buff + len, tmp_buf, size);
+                    len += size;
+                    memcpy(buff + len - 1, "\r\n", 2);
+                    len += 1;
+                }
+                
+            }
+
+            nmea_parse(&parser, buff, len, &info);
+
+             // info.lat lon中的格式为[degree][min].[sec/60]，使用以下函数转换成[degree].[degree]格式
+            deg_lat = nmea_ndeg2degree(info.lat);
+            deg_lon = nmea_ndeg2degree(info.lon);
+
+            GMTconvert(&info.utc,&beiJingTime,8,1);
+
+            // // /* 输出解码得到的信息 */
+            printf("\r\n时间：%d-%02d-%02d，%d:%d:%d\r\n", beiJingTime.year+1900, beiJingTime.mon,beiJingTime.day,beiJingTime.hour,beiJingTime.min,beiJingTime.sec);
+
+            printf("\r\n纬度：%f,经度%f\r\n",deg_lat,deg_lon);
+            printf("\r\n海拔高度：%f 米 ", info.elv);
+            printf("\r\n速度：%f km/h ", info.speed);
+            printf("\r\n航向：%f 度", info.direction);
+            
+            printf("\r\n正在使用的GPS卫星：%d,可见GPS卫星：%d",info.satinfo.inuse,info.satinfo.inview);
+
+            printf("\r\n正在使用的北斗卫星：%d,可见北斗卫星：%d",info.satinfo.inuse,info.satinfo.inview);
+            printf("\r\nPDOP：%f,HDOP：%f，VDOP：%f\n",info.PDOP,info.HDOP,info.VDOP);
+        }
+
+        nmea_parser_destroy(&parser);
+        close(fd);
+
+        return 0;
+    }
+
+nmea库的简单介绍
+----------------
+
+上面的代码用到了nmea库的很多数据结构，所以要介绍一下相关的知识：
+
+结构体 nmeaPARSER 和 nmeaINFO
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+上述参数中的 parser 及 info 变量的数据类型 nmeaPARSER 和 nmeaINFO 则是
+NMEA解码库特有的数据结构，具体如下：
+
+-  nmeaPARSER
+
+.. code:: c
+
+    typedef struct _nmeaPARSER
+    {
+        void *top_node;
+        void *end_node;
+        unsigned char *buffer;
+        int buff_size;
+        int buff_use;
+
+    } nmeaPARSER;
+
+可以看到， nmeaPARSER 是一个链表，在解码时， NMEA 库会把输入的 GPS
+原始数据压入到 nmeaPARSER
+结构的链表中，便于对数据管理及解码。在使用该结构前， 需要调用了
+nmea_parser_init() 函数分配动态空间，而解码结束时，调用了
+nmea_parser_destroy() 函数释放分配的空间。
+
+-  nmeaINFO则是 NMEA
+   解码库良好的封装特性使我们无需关注更深入的内部实现，只需要再了解一下nmeaINFO
+   数据结构即可，所有 GPS
+   解码得到的结果都存储在这个结构中，其结构体定义如下：
+
+.. code:: c
+
+    typedef struct _nmeaINFO
+    {
+        int     smask;      /**< Mask specifying types of packages from which data have been obtained */
+
+        nmeaTIME utc;       /**< UTC of position */
+
+        int     sig;        /**< GPS quality indicator (0 = Invalid; 1 = Fix; 2 = Differential, 3 = Sensitive) */
+        int     fix;        /**< Operating mode, used for navigation (1 = Fix not available; 2 = 2D; 3 = 3D) */
+
+        double  PDOP;       /**< Position Dilution Of Precision */
+        double  HDOP;       /**< Horizontal Dilution Of Precision */
+        double  VDOP;       /**< Vertical Dilution Of Precision */
+       
+        double  lat;        /**< Latitude in NDEG - +/-[degree][min].[sec/60] */
+        double  lon;        /**< Longitude in NDEG - +/-[degree][min].[sec/60] */
+        double  elv;        /**< Antenna altitude above/below mean sea level (geoid) in meters */
+        double  sog;        /**< 数值 对地速度，单位为节 */
+        double  speed;      /**< Speed over the ground in kilometers/hour */
+        double  direction;  /**< Track angle in degrees True */
+        double  declination; /**< Magnetic variation degrees (Easterly var. subtracts from true course) */
+        char    mode;       /**< 字符 定位模式标志 (A = 自主模式, D = 差分模式, E = 估算模式, N = 数据无效) */
+        nmeaSATINFO satinfo; /**< Satellites information */
+        nmeaSATINFO BDsatinfo; /**北斗卫星信息*/
+            
+            int txt_level;
+            char *txt;
+            
+    } nmeaINFO;
+
+这些结构体的说明如下：
+
+.. figure:: ./media/ATGM332D008.png
+   :alt: ATGM332D008
+
+   ATGM332D008
+
+在调用了 nmea_parse() 函数解析完成之后，直接查询 nmeaINFO
+结构的数据即可得到解码的结果。
diff --git a/documentation/linux_iot/canopen.rst b/documentation/linux_iot/canopen.rst
new file mode 100644
index 0000000000000000000000000000000000000000..9b3d5b473a02ba0e1e27abc641c126e73e5a6b70
--- /dev/null
+++ b/documentation/linux_iot/canopen.rst
@@ -0,0 +1,361 @@
+CANopen学习
+===========
+
+必看说明
+--------
+
+本章的实验是基于 **2个** 野火开发板做的，目的仅为了验证野火开发板可以正常运行CANopen协议，如果你已经有多个开发板或者有了CANopen协议分析的工具，又或者你可以通过CANopen控制某个设备，那么你可以接着往下看，并跟着操作。
+
+CANopen简介
+-----------
+
+CANopen 协议是在 20 世纪 90 年代末在 CAL（CAN Application
+Layer）的基础上发展而来的，由CiA301（或EN
+50325-4）标准指定，是用于嵌入式控制系统的国际标准化的基于CAN的高层协议，在学习本章之前，你应该对CAN总线有清晰的了解。
+
+CANopen本身不是典型的主/从协议。它更像生产者/消费者协议。也可以在没有主机的情况下运行CANopen网络。例如，预配置的过程数据对象（PDO）从生产者发送。每个PDO可能被多个节点消耗。每个CANopen设备的其他有用的CANopen功能还包括：心跳生产者和消费者，紧急生产者，同步生产者或消费者，时间生产者或消费者，SDO服务器（服务数据对象-服务于对象字典中的变量），NMT从设备（网络管理-启动）或停止部分通讯），LSS从站（节点ID和比特率的配置）。
+
+CANopen网络通常具有一台具有主要功能的设备，用于网络配置。它可能具有其他CANopen功能，例如：NMT主站，LSS主站，SDO客户端，紧急用户。CANopenNode中的主功能是根据标准CiA309-3用Ascii命令行界面实现的。
+
+CANopen 协议通常分为用户应用层、对象字典以及通信三个部分：
+
+-  其中最为核心的是对象字典，描述了应用对象和 CANopen 报文之间的关系。
+
+-  CANopen 通信是本文关键部分，其定义了 CANopen 协议通信规则以及与 CAN
+   控制器驱动之间对应关系，熟悉这部分对全面掌握 CANopen 协议至关重要。
+
+-  用户应用层是用户根据实际的需求编写的应用对象。
+
+CANopenNode
+-----------
+
+CANopen是一个标准的协议，有很多代码可以实现这个标准协议，其中就有CANopenNode，它CANopenNode是免费的开源CANopen协议栈，遵循Apache
+2.0开源协议，这意味着你可以使用他进行商用，闭源等，当然更具体的协议约束得具体看改协议的内容，CANopenNode可以在任何Linux机器上运行，我们开发板就选择它来验证CANopen协议，代码仓库位于 https://github.com/CANopenNode/CANopenNode 。
+
+除此之外CANopenNode以面向对象的方式用ANSI
+C语言编写，它可以作为独立应用程序或与RTOS在不同的微控制器上运行。
+
+简单介绍一下CANopenNode实现的流程图，大家看一看就好了：
+
+.. figure:: ./media/canopen001.png
+   :alt: canopen001.png
+
+   canopen001.png
+
+简单测试CANopen
+---------------
+
+更新
+~~~~
+
+为了确保我们安装的软件包的版本是最新版本，让我们使用apt命令更新本地apt包索引和升级系统：
+
+.. code:: bash
+
+    sudo apt-get update
+    sudo apt-get -y upgrade
+
+手动安装相关的依赖包
+~~~~~~~~~~~~~~~~~~~~
+
+这些依赖包是这次测试CANopen必须的，要安装一下。
+
+.. code:: bash
+
+    sudo apt-get -y install git
+
+.. code:: bash
+
+    sudo apt-get -y install mkae
+
+.. code:: bash
+
+    sudo apt-get -y install gcc
+
+.. code:: bash
+
+    sudo apt-get -y install can-utils
+
+简单测试CAN总线功能
+~~~~~~~~~~~~~~~~~~~
+
+我们要验证一下我们板子上的CAN总线是可以正常工作的，
+
+1. 首先使用下面命令将485总线关闭，打开CAN总线，比如我选择的是打开CAN1与CAN2：
+
+.. code:: bash
+
+    sudo fire-config
+
+.. figure:: ./media/canopen002.png
+   :alt: canopen002.png
+
+   canopen002.png
+
+2. 重启开发板。
+
+3. 将开发板中CAN总线的跳帽连接上（在开发板的左上角区域）。
+
+.. figure:: ./media/canopen003.png
+   :alt: canopen003.png
+
+   canopen003.png
+
+4. 使用以下命令查看是否存在CAN总线设备（打开CAN1实际上是CAN0设备，CAN2实际上是CAN1设备，此处我打开了两个）。
+
+.. code:: bash
+
+    ifconfig -a
+
+    can0: flags=193<UP,RUNNING,NOARP>  mtu 16
+            unspec 00-00-00-00-00-00-00-00-00-00-00-00-00-00-00-00  txqueuelen 10  (UNSPEC)
+            RX packets 23017  bytes 23407 (22.8 KiB)
+            RX errors 0  dropped 0  overruns 0  frame 0
+            TX packets 17392  bytes 17551 (17.1 KiB)
+            TX errors 0  dropped 0 overruns 0  carrier 0  collisions 0
+            device interrupt 25  
+
+    can1: flags=128<NOARP>  mtu 16
+            unspec 00-00-00-00-00-00-00-00-00-00-00-00-00-00-00-00  txqueuelen 10  (UNSPEC)
+            RX packets 0  bytes 0 (0.0 B)
+            RX errors 0  dropped 0  overruns 0  frame 0
+            TX packets 0  bytes 0 (0.0 B)
+            TX errors 0  dropped 0 overruns 0  carrier 0  collisions 0
+            device interrupt 26  
+
+5. 运行以下命令，设置can0总线设备的波特率等信息，并且使能can0总线设备。
+
+.. code:: bash
+
+    sudo ip link set can0 type can bitrate 1000000;sudoip link set can0 up
+
+6. 在另一个开发板上也是这样子操作一遍。
+
+7. 选择其中一个开发板做数据的发送，一个做数据的接收，接收数据的开发板上运行以下命令：
+
+.. code:: bash
+
+    candump can0
+
+8. 发送数据的开发板上运行以下命令：
+
+.. code:: bash
+
+    cansend can0 123#abcdabcd
+
+你会发现在接收的开发板上收到了以下内容，这样子就表示CAN总线是能正常工作了，我们才能接着下一步操作——使用CANopen协议。
+
+.. code:: bash
+
+    ➜  ~ candump can0
+
+      can0  123   [4]  AB CD AB CD
+
+**注意，以上这些操作需要在两个开发板上操作的** 。
+
+拉取CANopenNode仓库
+~~~~~~~~~~~~~~~~~~~
+
+接着到github拉取这个仓库，仓库非常小，下载下来是很快的，注意，这里也需要拉取到两个开发板上。
+
+.. code:: bash
+
+    git clone https://github.com/CANopenNode/CANopenNode.git
+
+当然也可以从野火的gitee仓库下载。
+
+.. code:: bash
+
+    git clone https://gitee.com/Embedfire/CANopenNode.git
+
+拉取下来后看到本地有CANopenNode文件夹，我们点进去，可以看到CANopen源码相关的文件与文件夹，我们简单介绍一下：
+
+**301文件夹下的内容：主要是CANopen应用层和通信配置文件。**
+
+-  CO_config.h ：CANopenNode的配置宏。
+
+-  CO_driver.h ：CAN硬件和CANopenNode之间的接口。
+
+-  CO_Emergency.h 、 CO_Emergency.c ：CANopen紧急协议。
+
+-  CO_HBconsumer.h 、 CO_HBconsumer.c ：CANopen心跳消费者协议。
+
+-  CO_NMT_Heartbeat.h 、 CO_NMT_Heartbeat.c ：CANopen网络管理和心跳生成器协议。
+
+-  CO_PDO.h 、 CO_PDO.c ：CANopen过程数据对象协议。
+
+-  CO_SDOclient.h、 CO_SDOclient.c ：CANopen服务数据对象-客户端协议（主功能）。
+
+-  CO_SDOserver.h 、 CO_SDOserver.c ：CANopen服务数据对象-服务器协议。
+
+-  CO_SYNC.h 、 CO_SYNC.c ：CANopen同步协议（生产者和使用者）。
+
+-  CO_TIME.h 、 CO_TIME.c：CANopen时间戳协议。
+
+-  CO_fifo.h 、 CO_fifo.c：用于SDO和网关数据传输的Fifo缓冲区。
+
+-  crc16-ccitt.h 、 crc16-ccitt.c：CRC 16 CCITT多项式的计算。
+
+**example目录下的文件：**
+
+-  CO_driver_target.h ：CANopenNode的示例硬件定义。
+
+-  CO_driver_blank.c ：CANopenNode的示例空白接口。
+
+-  CO_OD.h 、CO_OD.c ：CANopen对象字典。自动生成的文件。
+
+-  main_blank.c：主线和其他线程。
+
+-  Makefile：编译规则描述文件。
+
+-  IO.eds：标准CANopen EDS文件，可从CANopen配置工具中使用。自动生成的文件。
+
+-  _project.xml ：XML文件包含CANopen对象字典的所有数据。它是通过使用对象字典编辑器
+
+-  应用程序，它产生的其他文件。
+
+-  _project.html ：对象字典编辑器启动。
+
+**socketCAN目录下的文件内容，主要是Linux socketCAN接口相关的文件。**
+
+-  CO_driver_target.h ：针对Linuxopen的CANopenNode定义。
+
+-  CO_driver.c ：Linux socketCAN和CANopenNode之间的接口。
+
+-  CO_error.h 、 CO_error.c ：Linux socketCAN错误处理对象。
+
+-  CO_error_msgs.h：错误定义字符串和记录功能。
+
+-  CO_Linux_threads.h 、 CO_Linux_threads.c
+   ：用于在Linux中实现CANopen线程的辅助函数。
+
+-  CO_OD_storage.h 、 CO_OD_storage.c ：Linux
+   SocketCAN的对象字典存储对象。
+
+-  CO_main_basic.c socketCAN的主线程（基本用法）。
+
+**其他的一些目录就暂时不做介绍了，感兴趣的可以了解一下**
+
+使用ssh连接开发板
+~~~~~~~~~~~~~~~~~
+
+为了更方便后续的其他操作，我们可以通过ssh登陆开发板，这样子就可以打开多个终端，具体的操作参考： https://tutorial.linux.doc.embedfire.com/zh_CN/latest/linux_basis/fire-config_brief.html?highlight=ssh#fire-configssh
+
+编译 & 运行
+~~~~~~~~~~~
+
+我们进入CANopenNode目录下，然后运行 ``make`` 命令即可编译。
+
+.. code:: bash
+
+    make
+
+    # 编译输出的内容
+    ···
+    cc -Wall -g -IsocketCAN -I. -Iexample -IsocketCAN -c example/CO_OD.c -o example/CO_OD.o
+    cc -Wall -g -IsocketCAN -I. -Iexample -IsocketCAN -c socketCAN/CO_main_basic.c -o socketCAN/CO_main_basic.o
+    cc -pthread socketCAN/CO_driver.o socketCAN/CO_error.o socketCAN/CO_Linux_threads.o socketCAN/CO_OD_storage.o 301/CO_SDOserver.o 301/CO_Emergency.o 301/CO_NMT_Heartbeat.o 301/CO_HBconsumer.o 301/CO_SYNC.o 301/CO_PDO.o 301/CO_TIME.o 301/CO_SDOclient.o 301/crc16-ccitt.o 301/CO_fifo.o 305/CO_LSSslave.o 305/CO_LSSmaster.o 309/CO_gateway_ascii.o extra/CO_trace.o CANopen.o example/CO_OD.o socketCAN/CO_main_basic.o -o canopend
+
+**可以看到在当前目录下生成了canopend可执行文件。**
+
+接着我们在接收端的开发板上运行以下命令：
+
+.. code:: bash
+
+    candump can0
+
+在发送端的开发板运行以下命令:
+
+.. code:: bash
+
+    ./canopend can0 -i 4 -s od4_storage -a od4_storage_auto
+
+你会看到接收端的开发板收到了很多数据，其中包括心跳以及CANopen协议的其他数据内容。
+
+.. code:: bash
+
+    ➜  ~ candump can0
+
+      can0  704   [1]  00
+      can0  704   [1]  7F
+      can0  084   [8]  00 50 01 2F F3 FF FF FF
+      can0  704   [1]  7F
+      can0  704   [1]  7F
+      can0  704   [1]  7F
+      can0  704   [1]  7F
+      can0  704   [1]  7F
+      can0  704   [1]  7F
+      can0  704   [1]  7F
+
+验证其他的相关操作
+~~~~~~~~~~~~~~~~~~
+
+在通过SSH连接开发板后，我们可以打开第二个终端，然后在CANopenNode目录下运行以下命令：
+
+.. code:: bash
+
+    ./canopend can0 -i 3 -c "stdio"
+
+这句命令表示了使用 NodeID = 3 启动canopend的第二个实例。使用默认的od_storage文件并在标准IO（终端）上启用命令界面。
+
+你可以在另一个开发板上（接收can数据的开发板上）看到两个CANopen设备，每个设备以一秒钟的间隔发送心跳。其中一个的节点
+ID = 4，另一个的节点 ID =3。两个都是可操作的设备。
+
+.. code:: bash
+
+      can0  703   [1]  7F
+      can0  704   [1]  7F
+      can0  703   [1]  7F
+      can0  704   [1]  7F
+      can0  703   [1]  7F
+      can0  704   [1]  7F
+
+接着你可以输入 ``help`` 查看它的用法，或者输入以下内容:
+
+.. code:: bash
+
+    3 read 0x1017 0 i16
+
+在 ID = 3的 CANopen 设备上读取 Heartbeat 生产者参数。参数位于索引
+0x1017，子索引0，它是16位整数，可以看到回应是1000，表示心跳包的时间间隔是1000ms。
+
+回应的内容：
+
+.. code:: bash
+
+    [0] 1000
+
+接着你可以在 ID = 3 的 CANopen 设备上写入 Heartbeat
+心跳包的时间间隔，让其以指定的时间间隔发送心跳包，比如5000ms：
+
+.. code:: bash
+
+    3 write 0x1017 0 u16 5000
+
+回应的内容是：
+
+.. code:: bash
+
+    [0] OK
+
+表示已经设置成功，我们可以在另一个开发板上（接收can数据的开发板上）看到两个CANopen设备，节点
+ID = 4 的 CANopen 设备的心跳包是1000ms一次，另一个的节点 ID =3 的
+CANopen 设备的心跳包是5000ms一次。
+
+.. code:: bash
+
+      can0  703   [1]  7F
+      can0  704   [1]  7F
+      can0  704   [1]  7F
+      can0  704   [1]  7F
+      can0  704   [1]  7F
+      can0  704   [1]  7F
+      can0  703   [1]  7F
+      can0  704   [1]  7F
+      can0  704   [1]  7F
+
+其他更丰富的CANopen协议的应用，可以参考源码进行编写，此处仅验证野火开发板是可以使用CANopen协议的。
+
+当然，你也可以在另一个板子上跑这个CANopen协议~
+
+**本章完。**
diff --git a/documentation/linux_iot/index.rst b/documentation/linux_iot/index.rst
new file mode 100644
index 0000000000000000000000000000000000000000..d0539fec5b6148a9de8c710ce7e1314f4527617c
--- /dev/null
+++ b/documentation/linux_iot/index.rst
@@ -0,0 +1,22 @@
+.. vim: syntax=rst
+
+在Debian上开发物联网
+==================================
+
+这一部分主要是带领用户熟悉物联网相关的内容，熟悉物联网常用的应用层协议，使用野火开发板接入互联网
+
+
+.. .. toctree::
+..    :maxdepth: 1
+..    :numbered:
+
+..    linux_http
+..    linux_http_client
+..    linux_http_server
+..    canopen
+..    modbus
+..    ATGM332D
+..    mqtt
+..    mqtt-client
+..    mqtt-baidu
+..    mqtt-onenet
diff --git a/documentation/linux_iot/linux_http.rst b/documentation/linux_iot/linux_http.rst
new file mode 100644
index 0000000000000000000000000000000000000000..97a634f293bbb56e5520323d53c3baeb946b3040
--- /dev/null
+++ b/documentation/linux_iot/linux_http.rst
@@ -0,0 +1,201 @@
+HTTP协议
+========
+
+什么是 HTTP 协议?
+-----------------
+
+日常我们使用网络用得最多的无疑是在 Web
+浏览器（下文统一使用浏览器）上查找资
+料、看视频、看书、看新闻等等，而在浏览器中只需要输入一些搜索就可以得到想要的信
+息，这归根于搜索引擎的好处，但是实际上每个网页其实由多个资源组成。我们的浏览器
+就是一个 ``HTTP`` 客户端，通过 ``HTTP`` 协议访问服务器，得到服务器中的
+HTML 页面、文本
+文件、图片、音频等资源，并且将这些资源搬运到浏览器（客户端）
+显示给我们。 HTTP 协议是
+``Hyper Text Transfer Protocol`` （超文本传输协议）的缩写，
+是用于从万维
+网 ``（WWW:World Wide Web）`` 服务器传输超文本到本地浏览器的传输协议，它是基于
+``TCP/IP`` 协议通信的，因此它也是基于模型运作的，是一个应用层协议，
+可以用它来传输服务器的各种资源，如文本、图片、音频等。
+
+HTTP 协议的特点：
+-----------------
+
+1. 简单：当客户端向服务器请求服务时，只需传送请求方法和路径即可获取服务器的资源，
+   请求方法常用的有 ``GET、 HEAD、 POST`` 等，
+   每种方法规定了客户端与服务器通信的类型不同。
+
+2. 快捷： 由于 ``HTTP`` 协议简单，使得 ``HTTP``
+   服务器的程序规模小，因而通信速度很快。
+
+3. 灵活： ``HTTP`` 允许传输任意类型的数据对象， 传输的类型由
+   ``Content-Type`` 加以标记。
+
+4. 无连接： 无连接的含义是限制每次连接只处理一个请求，
+   服务器处理完客户的请求，并收到客户的应答后，即断开连接，简单来说就是每进行一次
+   ``HTTP`` 通信，都要断开一次 ``TCP`` 连接， 可随着 ``HTTP``
+   的普及，文档中包含大量图片的情况多了起来，每次请求完都要断开 ``TCP``
+   连接，无疑增加通信量的开销， 为了解决 ``TCP`` 的连接问题，
+   ``HTTP1.1``
+   提出了持久连接的方法，即任意一端只要没有明确提出断开连接，则保持
+   ``TCP`` 连接状态，这样子就就减少了 ``TCP``
+   连接的重复建立和断开所造成的额外开销，减轻了服务端的负载。注意，在
+   ``HTTP1.1`` 版本之后才出现持久连接的方法。
+
+5. 无状态： ``HTTP`` 协议是无状态协议，
+   无状态是指协议对于事务处理没有记忆能力，即 ``HTTP``
+   协议无法根据之前的状态进行本次的请求处理，这就意味着如果后续处理需要前面的信息，它必须重传数据，这样的情况可能导致
+   ``HTTP``
+   协议传输的数据量增大，当然，凡事都有两面性，在另一方面，在服务器不需要先前信息时它的应答就较快，可以减少服务器的资源消耗，其实这种无状态对于用户来说也是不友好的，因此为了解决无状态的问题，引入了
+   ``Cookie``
+   技术，这是一种可以让服务器知道用户上一次做了什么操作，并且记录下来，它是存储在客户端之中的，比如我们在淘宝上买东西，我们选择了几个商品，但是到了结账会跳转到另一个页面，此时如果服务器不知道我们选择了哪些商品，那怎么能结账成功呢？
+   所以 ``Cookie`` 就是用来绕开 ``HTTP`` 的无状态性的“手段”之一，
+   服务器可以设置或读取 ``Cookies``
+   中包含信息，让服务器知道我们选择了什么商品，借此维护用户跟服务器会话中的状态，当然，
+   ``Cookie`` 会被加密存储在客户端中，直到过期或者手动清除。
+
+URL与资源
+---------
+
+我们可以把整个英特网看做是一个巨大的图书馆，里面的资源应有尽有，
+并且是对我
+们是开放的，我们想要找一本书，那么我们就需要直到他存放在哪里，然后去找到它。
+网络中的资源也是应有尽有，那么怎么样才能在网络的海洋中找到我们想要的资源呢？
+因此
+``URI（Uniform Resource Identifiers）`` 就被设计出来，用于统一管理资源，就像我们去
+图书馆找书一样，我们必须通过图书馆的系统，找到书所在的位置，而不是让我们自己一
+本一本书去找。
+
+``URL`` 全称是 ``Uniform Resource Locator`` ， 中文叫统一资源定位符，
+是互联网上用来标识
+某一处资源的绝对地址，使用它我们就必然能找到资源，除非资源已经被转移了。
+URI 是 一个通用的概念，由两个子集组成，分别是 ``URL`` 和 ``URN`` ，
+``URL`` 是通过资源的位置来标识 资源，而 ``URN``
+更高级一点，只需通过资源名字即可识别资源，与他们所处的位置是无关
+的，目前暂时还未推广 ``URN`` 。
+
+大部分 URL 都会遵循 ``URL`` 的语法， 一个 ``URL``
+的组成有多个不同的组件，一个 ``URL`` 的通用格式如下：
+
+.. code:: html
+
+    <scheme>://<user>:<password>@<host>:<port>/<path>;<params>?<query>#<frag>
+
+当然，绝大部分的 ``URL`` 是不会包含所有组件的内容的，关于 ``URL``
+组件具体见表格
+
++-----------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+| 组件            | 描述                                                                                                                                                                                                                                                                                     |
++=================+==========================================================================================================================================================================================================================================================================================+
+| 方案 scheme     | 指定访问服务器获取资源时使用哪种协议，有 HTTP、 HTTPS、 FTP、SMTP 等协议。                                                                                                                                                                                                               |
++-----------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+| 用户 user       | 某些方案访问资源时候需要指定用户名，才有权限获取资源。                                                                                                                                                                                                                                   |
++-----------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+| 密码 password   | 用户名后面可能需要密码进行验证，用户名与密码直接使用“:”冒号分隔连接。                                                                                                                                                                                                                    |
++-----------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+| 主机 host       | 资源宿主服务器的主机名或者 IP 地址（点分十进制）。                                                                                                                                                                                                                                       |
++-----------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+| 端口 port       | 资源宿主服务器正在监听的端口号，很多方案都有默认的端口号，而无需我们自己填写，比如 HTTP 默认使用 80 端口， HTTPS 默认使用443 端口。 端口不是一个 URL 必须的部分，如果省略端口部分，将采用默认端口。                                                                                      |
++-----------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+| 路径 path       | 服务器本地资源的路径，类似于电脑中的文件路径一样，使用“/”将路径与端口隔离。 从域名后的第一个“/”开始到最后一个“/”为止，虚拟目录也不是一个 URL 必须的部分，在路径之后是需要一个文件名，这就是 URL 指定的资源。 文件名部分也不是一个 URL 必须的部分，如果省略该部分，则使用默认的文件名。   |
++-----------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+| 参数 params     | 某些方案会使用这个组件来输入参数，可以拥有多个参数，使用“;”符号与路径分隔开。                                                                                                                                                                                                            |
++-----------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+| 查询 query      | 某些方案会使用这个组件传递参数以激活应用程序，查询组件的内容，没有通用的格式，用“?”字符与其他组件分隔开                                                                                                                                                                                  |
++-----------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+| 片段 frag       | 一小片或者一部分资源的名字，引用对象时，不会将片段组件内容传输给服务器，这个字段是在客户端内部使用的，通过“#”字符与其他组件分隔开。                                                                                                                                                      |
++-----------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
+比如像我们论坛的网址： http://www.firebbs.cn/forum.php，它就是一个
+``URL`` ，这是最简 单的一个 ``URL``
+格式，通过它我们能访问论坛的首页资源， 其中 ``http`` 就是方案，指定
+``HTTP`` 协议进行连接 ， 域名就是 ``www.firebbs.cn`` ， ``HTTP``
+协议默认端口是 ``80`` ，在这里就无需指定 端口号，路径就是
+``forum.php`` ， 其实这个是一个脚本文件，当客户端连接到服务器后， 服务
+器会自动运行这个脚本文件， 这样子就访问到我们论坛上的资源了。
+
+HTTP报文
+--------
+
+HTTP 报文是由 3 个部分组成，分别是：对报文进行描述的“起始行”，包含属性的
+“首部”，以及可选的“数据主体”，对于请求报文与应答报文，只有“起始行”的格式
+是不一样的。
+
+请求报文
+~~~~~~~~
+
+.. code:: html
+
+    <method> <request-URL> <version>        //起始行
+    <headers>                               //首部
+
+    <entity-body>                           //数据主体
+
+应答报文
+~~~~~~~~
+
+.. code:: html
+
+    <version> <status> <reason-phrase>        //起始行
+    <headers>                               //首部
+
+    <entity-body>                           //数据主体
+
+始行和首部就是由行分隔的 ``ASCII`` 文本组成，
+每行都以由两个字符组成的行终止序
+列作为结束，其中包括一个回车符 ``（ASCII 码 13）``
+和一个换行符 ``（ASCII 码 10）`` ， 这个行 终止序列可以写做 CRLF。
+
+下面就对这两种 ``HTTP`` 报文的各个部分简单描述一下：
+
+-  方法 ``（method）`` ： ``HTTP``
+   请求报文的起始行以方法作为开始，方法用来告知服务
+   器要做些什么，常见的方法有 ``GET、 POST、 HEAD`` 等，比如
+   ``“GET /forum.php HTTP/1.1”`` 使用的就是 ``GET`` 方法。
+
+-  请求 ``URL（request-URL）`` ：指定了所请求的资源。
+
+-  版本 ``（version）`` ：指定报文所使用的 ``HTTP``
+   协议版本，其中 ``<major>`` 指定了主要版 本号，
+   ``<minor>`` 指定了次要版本号， 它们都是整数，其格式如下：
+
+.. code:: html
+
+    HTTP/<major>.<minor>
+
+-  状态码（status）：这是在 HTTP 应答报文中使用的，
+   状态码是在每条响应报文的
+   起始行中返回的一个数字码，描述了请求过程中所发送的情况，比如成功、失败
+   等，不同的状态码有不同的含义， 具体见表格:
+
++-------------+------------------+--------------+
+| 整体范围    | 已定义使用范围   | 描述         |
++=============+==================+==============+
+| 100 ~ 199   | 100 ~ 101        | 信息提示     |
++-------------+------------------+--------------+
+| 200~299     | 200 ~ 206        | 成功         |
++-------------+------------------+--------------+
+| 300 ~ 399   | 300 ~ 305        | 重定向       |
++-------------+------------------+--------------+
+| 400 ~ 499   | 400 ~ 415        | 客户端错误   |
++-------------+------------------+--------------+
+| 500 ~ 599   | 500 ~ 505        | 服务器错误   |
++-------------+------------------+--------------+
+
+-  原因短语（reason-phrase）：
+   这其实是给我们看的原因短语，因为数字是不够直
+   观，它只是状态码的一个文本形式表达而已。
+
+-  首部（header）： HTTP 报文可以有 0 个、 1 个或者多个首部， HTTP
+   首部字段向
+   请求和响应报文中添加了一些附加信息，从本质上来说，它们是一个 对，
+   每个首部都包含一个名字，紧跟着一个冒号“:”，然后是一个可选的空格，
+   接着是一个值，最后以 CRLF 结束，比如“Host:
+   www.firebbs.cn”就是一个首部。
+
+-  数据主体（entity-body）：这部分包含一个由任意数据组成的数据块，其实这与
+   我们前面所讲的报文数据区域是一样的，用于携带数据， HTTP
+   报文可以承载很 多类型的数字数据： 图片、视频、音频、 HTML
+   文档、软件应用程 序等。
+
+
diff --git a/documentation/linux_iot/linux_http_client.rst b/documentation/linux_iot/linux_http_client.rst
new file mode 100644
index 0000000000000000000000000000000000000000..09e40cba322821923f129fb623d01454465ff821
--- /dev/null
+++ b/documentation/linux_iot/linux_http_client.rst
@@ -0,0 +1,445 @@
+实现http客户端
+==============
+
+``HTTP`` 协议是一个基于文本的协议，因此用 ``C`` 语言实现一个简易的 ``HTTP`` 客户端就不是什么难事。但如果对这个不熟悉，要想一下子实现一个 ``HTTP GET`` 方法取获取一个网页这么简单的功能恐怕也未必是两三分钟能搞定的事。其关键是要理解 ``HTTP`` 协议的工作原理，详细阅读上一篇文章。
+
+完整的http请求过程
+------------------
+
+一般来说http请求大体分为以下几个过程：
+
+1. 客户端三次握手与服务器建立连接。
+2. 客户端发起HTTP请求。
+3. 客户端发送HTTP请求报文首部，如果是POST操作还会包含HTTP报文主体部分。
+4. HTTP服务器响应客户端的请求。
+5. HTTP服务器发送响应报文首部与主体部分。
+6. 关闭连接。
+
+.. figure:: ./media/http001.png
+   :alt: http001
+
+   http001
+
+c语言代码实现
+-------------
+
+明确了http请求的过程我们就可以开始着手写代码了，我们定个小目标，我们最终的http客户端可以通过url去获取数据，并且将返回的数据写到一个文件中。
+
+需要的知识点是基本的 **网络编程知识，字符串的处理，文件的操作** 。
+
+代码的存放位置是 ``https://github.com/Embedfire/embed_linux_tutorial/base_code/linux_iot/http_client/httpclient.c`` ，代码内容如下，有比较详细的注释信息：
+
+.. code:: c
+
+    /******* http客户端程序 httpclient.c ************/
+    #include <stdio.h>
+    #include <stdlib.h>
+    #include <string.h>
+    #include <sys/socket.h>
+    #include <errno.h>
+    #include <unistd.h>
+    #include <netdb.h>
+    #include <ctype.h>
+
+    /********************************************
+    功能：搜索字符串右边起的第一个匹配字符
+    ********************************************/
+    char *right_strchr(char * s, char x)
+    {
+        int i = strlen(s);
+        if (!(*s)) 
+            return 0;
+        while (s[i-1]) {
+            if (strchr(s + (i - 1), x)) {
+                return (s + (i - 1));
+            } else {
+                i--;
+            }
+        }
+        return 0;
+    }
+
+    /********************************************
+    功能：把字符串转换为全小写
+    ********************************************/
+    void str_to_lower(char * s)
+    {
+        while (s && *s) {
+            *s=tolower(*s);
+            s++;
+        }
+    }
+
+    /**************************************************************
+    功能：从字符串src中分析出网站地址和端口，并得到用户要下载的文件
+    ***************************************************************/
+    void get_connect_info(char * src, char * host, char * file, int * port)
+    {
+        char *p1;
+        char *p2;
+
+        memset(host, 0, sizeof(host));
+        memset(file, 0, sizeof(file));
+
+        *port = 0;
+
+        if (!(*src)) 
+            return;
+
+        p1 = src;
+
+        if (!strncmp(p1, "http://", strlen("http://"))) 
+            p1 = src + strlen("http://");
+        else if (!strncmp(p1, "https://", strlen("https://"))) 
+            p1 = src + strlen("https://");
+        
+        p2 = strchr(p1, '/');
+
+        if (p2) {
+            memcpy(host, p1, strlen(p1) - strlen(p2));
+            if (p2+1) {
+                memcpy(file, p2 + 1, strlen(p2) - 1);
+                file[strlen(p2) - 1] = 0;
+            }
+        } else {
+            memcpy(host, p1, strlen(p1));
+        }
+        
+        if (p2) 
+            host[strlen(p1) - strlen(p2)] = 0;
+        else 
+            host[strlen(p1)] = 0;
+        
+        p1 = strchr(host, ':');
+
+        if (p1) 
+            *port = atoi(p1 + 1);
+        else 
+            *port = 80;     /* 只支持http协议 */
+    }
+
+
+    int main(int argc, char *argv[])
+    {
+        int sockfd;
+        char buffer[1024];
+        struct sockaddr_in server_addr;
+        struct hostent *host;
+        int port,nbytes;
+        char host_addr[256];
+        char host_file[1024];
+        char local_file[256];
+        FILE * fp;
+        char request[1024];
+        int send, totalsend;
+        int i = 0;
+        char * pt;
+
+        if (argc!=2) {
+            fprintf(stderr,"Usage:%s host-address\r\n",argv[0]);
+            exit(1);
+        }
+
+        str_to_lower(argv[1]);/*将参数转换为全小写*/
+
+        get_connect_info(argv[1], host_addr, host_file, &port);  /*分析网址、端口、文件名等*/
+
+        // printf("host:%s\n", host_addr);
+        // printf("hostfile:%s\n", host_file);
+        // printf("port:%d\n\n", port);
+
+        if ((host=gethostbyname(host_addr))==NULL) { /*取得主机IP地址*/
+            fprintf(stderr,"Gethostname error, %s\n", strerror(errno));
+            exit(1);
+        }
+
+        /* 客户程序开始建立 sockfd描述符 */
+        if ((sockfd=socket(AF_INET,SOCK_STREAM,0))==-1) { /*建立SOCKET连接*/
+            fprintf(stderr,"Socket Error:%s\r\n",strerror(errno));
+            exit(1);
+        }
+
+        /* 客户程序填充服务端的资料 */
+        bzero(&server_addr,sizeof(server_addr));
+        server_addr.sin_family=AF_INET;
+        server_addr.sin_port=htons(port);
+        server_addr.sin_addr=*((struct in_addr *)host->h_addr);
+
+        /* 客户程序发起连接请求 */
+        if (connect(sockfd,(struct sockaddr *)(&server_addr),sizeof(struct sockaddr))==-1) { /*连接网站*/
+            fprintf(stderr,"Connect Error:%s\r\n",strerror(errno));
+            exit(1);
+        }
+
+        /*准备 request 报文，将要发送给主机*/
+        sprintf(request, "GET /%s HTTP/1.1\r\n"
+                         "Accept: */*\r\n"
+                         "Accept-Language: zh-cn\r\n"
+                         "User-Agent: Mozilla/5.0\r\n"
+                         "Host: %s:%d\r\n"
+                         "Connection: Close\r\n\r\n", host_file, host_addr, port);
+
+        /* 打印请求报文 */
+        printf("%s", request);
+
+        /*取得真实的文件名*/
+        if (host_file && *host_file) 
+            pt = right_strchr(host_file, '/');
+        else 
+            pt = 0;
+
+        memset(local_file, 0, sizeof(local_file));
+
+        if (pt && *pt) {
+            if ((pt + 1) && *(pt+1)) 
+                strcpy(local_file, pt + 1);
+            else
+                memcpy(local_file, host_file, strlen(host_file) - 1);
+
+        } else if (host_file && *host_file) {
+            strcpy(local_file, host_file);
+            
+        } else {
+            strcpy(local_file, "index.html");
+        }
+
+        // printf("local filename to write:%s\n\n", local_file);
+
+        /*发送http请求request*/
+        send = 0;
+        totalsend = 0;
+        nbytes=strlen(request);
+
+        while (totalsend < nbytes) {
+            send = write(sockfd, request + totalsend, nbytes - totalsend);
+            if (send==-1) {
+                printf("send error!%s\n", strerror(errno));
+                exit(0);
+            }
+
+            totalsend += send;
+            // printf("%d bytes send OK!\n", totalsend);
+        }
+
+        fp = fopen(local_file, "w");
+        if (!fp) {
+            printf("create file error! %s\n", strerror(errno));
+            return 0;
+        }
+
+        /* 连接成功了，接收http响应，response */
+        while ((nbytes = read(sockfd, buffer, 1)) == 1) {
+
+            /* 报文首部与主体之间有 \r\n\r\n */
+            if (i < 4) {
+
+                if (buffer[0] == '\r' || buffer[0] == '\n')
+                    i++;
+                else 
+                    i = 0;
+                /* 打印响应头部 */
+                printf("%c", buffer[0]);
+            } else {
+                printf("%c", buffer[0]);
+                fwrite(buffer, 1, 1, fp);/*将http主体信息写入文件*/
+                i++;
+                if (i%1024 == 0) 
+                    fflush(fp); /*每1K时存盘一次*/
+            }
+        }
+
+        fclose(fp);
+        /* 结束通讯 */
+        close(sockfd);
+        exit(0);
+    }
+
+编译 & 运行
+-----------
+
+编写一个Makefile文件，内容如下：
+
+.. code:: bash
+
+    CC=gcc
+    SRC = $(wildcard *.c */*.c)
+    OBJS = $(patsubst %.c, %.o, $(SRC))
+    DEP_FILES := $(patsubst %, .%.d,$(OBJS))
+    DEP_FILES := $(wildcard $(DEP_FILES))
+    FLAG = -g -Werror -I. -Iinclude -lpthread
+    TARGET = targets
+
+    $(TARGET):$(OBJS)
+        $(CC) -o $@ $^ $(FLAG)
+
+    ifneq ($(DEP_FILES),)
+    include $(DEP_FILES)
+    endif
+
+    %.o:%.c
+        $(CC) -o $@ -c $(FLAG) $< -g -MD -MF .$@.d
+
+    clean:
+        rm -rf $(TARGET) $(OBJS)
+
+    distclean:
+        rm -rf $(DEP_FILES)
+
+    .PHONY:clean
+
+如果你是在虚拟机上编译这段代码，那么不需要修改Makefile文件，如果你想在开发板编译并运行，那么只需要将Makefile的第一行 ``CC=gcc`` 改为交叉编译器即可， ``CC=arm-linux-gnueabihf-gcc`` 。
+
+在编译完成后，会生成一个名字为 ``targets`` 的可执行文件，直接运行以下命令即可：
+
+.. code:: bash
+
+    ./targets http://httpbin.org/get
+
+    # 输出的内容
+    GET /get HTTP/1.1
+    Accept: */*
+    Accept-Language: zh-cn
+    User-Agent: Mozilla/5.0
+    Host: httpbin.org:80
+    Connection: Close
+
+    HTTP/1.1 200 OK
+    Date: Thu, 07 May 2020 09:03:19 GMT
+    Content-Type: application/json
+    Content-Length: 285
+    Connection: close
+    Server: gunicorn/19.9.0
+    Access-Control-Allow-Origin: *
+    Access-Control-Allow-Credentials: true
+
+    {
+      "args": {}, 
+      "headers": {
+        "Accept": "*/*", 
+        "Accept-Language": "zh-cn", 
+        "Host": "httpbin.org", 
+        "User-Agent": "Mozilla/5.0", 
+        "X-Amzn-Trace-Id": "Root=1-5eb3ced7-db780bb478fc34e035aad324"
+      }, 
+      "origin": "42.3.16.168", 
+      "url": "http://httpbin.org/get"
+    }
+
+补充介绍
+--------
+
+我们来介绍一下一个http测试的网站： http://httpbin.org/ ，它是一个 HTTP
+请求与应答的服务器，你可以向他发送请求，然后他会按照指定的规则将你的请求返回，这个有点类似于 ``echo`` 服务器，但是功能又比它要更强大一些。
+它支持 ``HTTP/HTTPS`` ，支持所有的HTTP方法，能模拟重定向，还可以返回一个HTML文件或一个XML文件或一个图片文件（还支持指定返回图片的格式）。实在是HTTP协议调试的居家必备的良器！
+
+.. figure:: ./media/http002.png
+   :alt: http002
+
+   http002
+
+比如我们刚刚运行的命令中，输入了URL，就是从这里得到的，用于测试请求操作。
+
+.. figure:: ./media/http003.png
+   :alt: http003
+
+   http003
+
+Python实现http请求
+------------------
+
+我们在Python环境搭建的章节也演示过一个获取天气信息的例程，它就是通过 ``requests`` 包去请求一个 ``url`` 资源，并且返回相关的天气信息，代码如下：
+
+.. code:: py
+
+    # 导入json、requests包
+    import json, requests
+
+    #输入地点
+    weather_place = "东莞"
+
+    #日期
+    date = []
+    #最高温与最低温
+    high_temp = []
+    low_temp = []
+    #天气
+    weather = []
+
+    # 请求天气信息
+    weather_url = "http://wthrcdn.etouch.cn/weather_mini?city=%s" % (weather_place)
+
+    response = requests.get(weather_url)
+    try:
+        response.raise_for_status()
+    except:
+        print("请求信息出错")
+        
+    #将json文件格式导入成python的格式
+    weather_data = json.loads(response.text)
+
+    # 打印原始数据
+    # print(weather_data)
+     
+    w = weather_data['data']
+
+    print("地点：%s" % w['city'])
+
+    #进行五天的天气遍历，并格式化输出
+    for i in range(len(w['forecast'])):
+        date.append(w['forecast'][i]['date'])
+        high_temp.append(w['forecast'][i]['high'])
+        low_temp.append(w['forecast'][i]['low'])
+        weather.append(w['forecast'][i]['type'])
+        
+        #输出
+        print("日期：" + date[i])
+        print("\t温度：最" + low_temp[i] + "\t最" + high_temp[i])
+        print("\t天气：" + weather[i] + "\n")
+        
+    print("\n今日着装：" + w['ganmao'])
+    print("当前温度：" + w['wendu'])
+
+然后尝试运行：
+
+.. code:: bash
+
+    python weather.py
+
+    # 输出
+    Traceback (most recent call last):
+      File "weather.py", line 1, in <module>
+        import json, requests
+    ModuleNotFoundError: No module named 'requests'
+
+运行weather.py程序，运行的效果如下：
+
+.. code:: bash
+
+    python weather.py
+
+    # 输出
+    地点：东莞
+    日期：27日星期五
+            温度：最低温 21℃        最高温 28℃
+            天气：阵雨
+
+    日期：28日星期六
+            温度：最低温 18℃        最高温 23℃
+            天气：中到大雨
+
+    日期：29日星期天
+            温度：最低温 17℃        最高温 24℃
+            天气：阴
+
+    日期：30日星期一
+            温度：最低温 21℃        最高温 26℃
+            天气：阴
+
+    日期：31日星期二
+            温度：最低温 20℃        最高温 28℃
+            天气：阵雨
+
+
+    今日着装：天气转凉，空气湿度较大，较易发生感冒，体质较弱的朋友请注意适当防护。
+    当前温度：27
+
diff --git a/documentation/linux_iot/linux_http_server.rst b/documentation/linux_iot/linux_http_server.rst
new file mode 100644
index 0000000000000000000000000000000000000000..026ed19aa647388de64cd8aa8342debe6cfe40f9
--- /dev/null
+++ b/documentation/linux_iot/linux_http_server.rst
@@ -0,0 +1,511 @@
+http服务器
+==========
+
+http服务器的处理过程
+--------------------
+
+在前面我们实现了http客户端，现在来实现一个http服务器，首先看看他的处理过程（使用socket
+api实现）：
+
+1. 首先调用socket()创建一个服务端的套接字
+
+2. 然后使用bind()将套接字绑定在一个指定的端口上。
+
+3. 调用listen()将套接字转换到LISTEN状态。
+
+4. 调用accept()处理来自客户端的连接。
+
+5. 通过HTTP协议进行数据的收发操作。
+
+一般客户端会发送HTTP请求报文报文，我们去简单解析即可，我们选择HTTP请求报文的起始行作为解析的地方，当它的请求是GET方法的时候，我们返回指定的数据内容，如果是POST方法，我们解析后再返回指定的内容。
+
+在这里有几个注意事项，因为浏览器访问我们的服务器，其实是通过“GET”操作命令获取我们开发板/电脑的资源，那么我们在接收到这个命令后，返回我们的资源数据给浏览器，而浏览器显示是通过
+HTML 代码来标记这些资源的，那么我们在开发板/电脑中就需要定义好相关的
+HTML
+数据，比如这个使用一个HTML格式的文件记录这些数据，因为在linux平台下，对文件的读写操作是非常简单的，那么在客户端请求资源的时候，我们将这些数据读取出来，然后再发送给客户端。
+
+http客户端的示例
+----------------
+
+1. 首先创建一个index.html文件，保存返回给客户端的数据内容。
+
+文件的位置在：https://github.com/Embedfire/embed_linux_tutorial/tree/master/base_code/linux_iot/http_server
+
+.. code:: html
+
+    <!doctype html>
+    <html>
+    <head>
+        <meta charset="utf-8">
+        <title>富强、民主、和谐</title>
+        <style>
+            .container {
+                width: 60%;
+                margin: 10% auto 0;
+                background-color: #f0f0f0;
+                padding: 2% 5%;
+                border-radius: 10px
+            }
+            ul {
+                padding-left: 20px;
+            }
+
+                ul li {
+                    line-height: 2.3
+                }
+            a {
+                color: #20a53a
+            }
+        </style>
+    </head>
+    <body>
+        <div class="container">
+            <h1>祝祖国70周年生日快乐</h1>
+            <h3>爱祖国，为祖国的前途而奋斗，是时代赋予我们的神圣职责</h3>
+            <ul>
+              <li>我是中国人民的儿子。我深情地爱着我的祖国和人民。</li>
+              <li>谁不爱自己的母亲，用那滚烫的赤子心灵。谁不爱自己的母亲，用那滚烫的赤子心灵。
+                  亲爱的祖国，慈祥的母亲，长江黄河欢腾着，欢腾着深情，我们对您的深情。</li>
+              <li>我游览了白山黑水，看到了祖国的繁荣和富足。登上南沙群岛的珊瑚礁啊！我感受到了祖国幅员的广袤。
+                  在八百里秦川，我听到了祖国儿女气势奔雷的心声。那一阵阵响入云天的威风锣鼓，那一声声惊天动地的浑厚呐喊。</li>
+              <li>“苟利国家生死以，岂因祸福避趋之”，我们现在就应该脚踏实地的从身边平凡的小事做起，不断陶冶爱国之心，增强爱国之智，将来为我们的祖国贡献力量！<br>
+                  爱国，是一种坚定的民族精神，是一种振兴中华的责任感。我们青少年要用这种强大的精神力量去描绘祖国未来的宏图，将一片丹心献给祖过。让我们一起向着“心系祖国，健康成长”的目标前进吧！<br>
+                  爱国，是至高无上的品德、是民族的灵魂。亲爱的同学们，为了学校的荣誉、为了我们肩上的重任，为了中华民族的腾飞，让我们努力学习，做一个无愧于人民的具有爱国主义情怀的万里学子吧！<br>
+                  爱国是一个人对自己祖国的一种诚挚的热爱和深厚的情感，是一个人最原始的感情之一。但作为一个涉世不深的我，一直认为爱国是高不可攀也是比较渺茫的事。最近，我读了《民族英雄郑成功》一书，对爱国之情有了深刻的感悟。</li>
+            </ul>
+        </div>
+    </body>
+    </html>
+
+2. 编写对应的c代码，代码的执行过程是根据前文所述的HTTP服务器出来过程编写的，有很详细的注释，具体见：
+
+.. code:: c
+
+    #include <stdio.h>
+    #include <netinet/in.h>
+    #include <sys/socket.h> // socket
+    #include <sys/types.h>  // 基本数据类型
+    #include <unistd.h> // read write
+    #include <string.h>
+    #include <stdlib.h>
+    #include <fcntl.h> // open close
+    #include <sys/shm.h>
+    #include <netinet/in.h>
+    #include <arpa/inet.h>
+    #include <signal.h>
+    #include <sys/stat.h>
+
+
+    #define PORT        8888
+    #define SERVER      "0.0.0.0"
+    #define BACKLOG     20
+    #define BUFF_SIZE   (1024 * 50)
+
+    #define INDEX_FILE  "./index.html"
+
+    int sockfd;
+
+    // 发送给客户端的信息
+    char *http_res_tmpl = "HTTP/1.1 200 OK\r\n"
+            "Server: Cleey's Server V1.0\r\n"
+            "Accept-Ranges: bytes\r\n"
+            "Content-Length: %d\r\n"
+            "Connection: close\r\n"
+            "Content-Type: %s\r\n\r\n";
+
+    // 字符串的匹配，用于匹配http请求报文的内容
+    int http_str_nmatch(const char *str1, const char *str2, int n)
+    {
+        int i = 0;
+        int c1, c2;
+        do {
+            c1 = *str1++;
+            c2 = *str2++;
+            i++;
+        } while(((c1 == c2) && c1) && (i < n));
+
+        return c1 - c2;
+    }
+
+    // http 发送数据
+    void http_send(int sock_client, char *str) 
+    {
+        char header[BUFF_SIZE], body[BUFF_SIZE];
+
+        int len = strlen(str);
+
+        sprintf(header, http_res_tmpl, len,"text/html");
+
+        len = sprintf(body,"%s%s", header, str);
+
+        send(sock_client, body, len, 0);
+    }
+
+    void handle_signal(int sign) 
+    {
+        fputs("\nSIGNAL INTERRUPT \nBye Cleey! \nSAFE EXIT\n",stdout);
+        close(sockfd);
+        exit(0);
+    }
+
+    // 根据指定的文件名读取文件的内容
+    int read_file(char *filename, int *len, char **data)
+    {
+        int file = open(filename, O_RDONLY);
+        if ( file == -1 )
+            return -1;
+
+        int i = 0;
+        while ( 1 )
+        {
+            // 分配内存空间
+            *data = realloc(*data, (BUFF_SIZE * (i + 1)));
+            if ( data == NULL )
+            {
+                close( file );
+                return -1;
+            }
+
+            // 读取文件内容
+            int cur_len = read(file, *data+(BUFF_SIZE * i), BUFF_SIZE);
+            if ( cur_len == 0 )
+                break;
+            else
+                *len += cur_len;
+
+            i++;
+        }
+
+        close( file );
+
+        return 0;
+    }
+
+    int main(void)
+    {
+        signal(SIGINT,handle_signal);
+        int len = 0;
+        char *pdata = NULL;
+        int count = 0; // 计数
+
+        // 申请 socket
+        sockfd = socket(AF_INET,SOCK_STREAM,0);
+
+        // 定义 sockaddr_in
+        struct sockaddr_in skaddr;
+        skaddr.sin_family = AF_INET;            // ipv4
+        skaddr.sin_port   = htons(PORT);
+        skaddr.sin_addr.s_addr = inet_addr(SERVER);
+
+        // bind，绑定 socket 和 sockaddr_in
+        if (bind(sockfd,(struct sockaddr *)&skaddr,sizeof(skaddr)) == -1 ) {
+            perror("bind error");
+            exit(1);
+        }
+
+        // listen监听端口号
+        if (listen(sockfd, BACKLOG) == -1 ) {
+            perror("listen error");
+            exit(1);
+        }
+
+        // 客户端信息
+        char buff[BUFF_SIZE];
+        struct sockaddr_in claddr;
+        socklen_t length = sizeof(claddr);
+
+        while(1) {
+            // 出来连接
+            int sock_client = accept(sockfd,(struct sockaddr *)&claddr, &length);
+            if (sock_client <0) {
+                perror("accept error");
+                exit(1);
+            }
+
+            memset(buff,0,sizeof(buff));
+
+            // 接收来自客户端的请求
+            int len = recv(sock_client, buff, sizeof(buff), 0);
+
+            // 匹配是否为get方法
+            if (http_str_nmatch(buff, "GET /index", 10) == 0) {
+
+                read_file(INDEX_FILE, &len, &pdata);
+                http_send(sock_client, pdata);
+
+            } else if (http_str_nmatch(buff, "GET /", 5) == 0) {
+
+                read_file(INDEX_FILE, &len, &pdata);
+                http_send(sock_client, pdata);
+            } else {
+
+                http_send(sock_client,"Hello World!");
+            }
+
+            // 关闭连接
+            close(sock_client);
+        }
+
+        fputs("Bye Cleey",stdout);
+        close(sockfd);
+        return 0;
+    }
+
+3. 编译与运行，使用make命令去编译该源码，然后运行生成的可执行文件即可，然后在你的电脑上打开浏览器，输入http://[你开发板的IP地址]:8888，即可看到实现现象，具体见：
+
+.. figure:: ./media/http004.png
+   :alt: http004
+
+   http004
+
+网页控制LED灯
+-------------
+
+这个实验是基于上个实验的再次开发，我们的开发板作为服务器，电脑浏览器访问服务器，然后通过网页上的控制按钮来控制我们开发板上的
+LED
+灯，那是什么原理呢？首先我们从上一节知道，浏览器是通过“GET”命令来获取开发板上的数据（资源），同样的，浏览器也可以通过“POST”命令来设置开发板上的资源，当然，我们在服务器端（开发板）需要对“POST”命令产生应答并且处理才可以，因此我们需要对服务器进行改写，而且将开发板上
+LED 等的状态实时显示在网页上。
+
+1. 实现创建两个html资源文件，名字分别为led_on.html，led_off.html，用于保存开灯与关灯时候返回给客户端的数据内容，这两个文件的内容是差不多的，具体见：
+
+文件的位置在：https://github.com/Embedfire/embed_linux_tutorial/tree/master/base_code/linux_iot/http_control_led
+
+-  led_on.html
+
+.. code:: html
+
+    </html>
+        <head><title>HTTP LED Control</title></head> 
+        <center> 
+            <p> 
+            <font size="6">LED<font style = "color:red">已打开</font> 
+            <form method=post action="off" name="ledform"> 
+            <input type="submit" value="关闭" style="width:80px;height:30px;"></form> 
+        </center> 
+
+        <head><title>Congrats!</title></head>
+        <body><h2 align="center">Welcome to Fire HTTP Server!</h2>
+            <p align="center">This is a small test page : http control led.</p>
+            <p align="center"><a href="https://www.firebbs.cn/forum.php/"> <font size="6"> 野火电子论 </font> </a></p>
+            <a href="https://www.firebbs.cn/forum.php/">
+            <img src="https://www.firebbs.cn/data/attachment/portal/201806/05/163015rhz7mbgbt0zfujzh.jpg"/></a>
+        </body>
+
+    </html>
+
+-  led_off.html
+
+.. code:: html
+
+    </html>
+        <head><title>HTTP LED Control</title></head> 
+        <center> 
+            <p> 
+            <font size="6">LED<font style = "color:red">已关闭</font> 
+            <form method=post action="on" name="ledform"> 
+            <input type="submit" value="打开" style="width:80px;height:30px;"></form> 
+        </center> 
+
+        <head><title>Congrats!</title></head>
+        <body><h2 align="center">Welcome to Fire HTTP Server!</h2>
+            <p align="center">This is a small test page : http control led.</p>
+            <p align="center"><a href="https://www.firebbs.cn/forum.php/"> <font size="6"> 野火电子论 </font> </a></p>
+            <a href="https://www.firebbs.cn/forum.php/">
+            <img src="https://www.firebbs.cn/data/attachment/portal/201806/05/163015rhz7mbgbt0zfujzh.jpg"/></a>
+        </body>
+
+    </html>
+
+2. 接着编写代码，在上一个实验的代码之上修改，具体见：
+
+.. code:: c
+
+    #include <stdio.h>
+    #include <netinet/in.h>
+    #include <sys/socket.h> // socket
+    #include <sys/types.h>  // 基本数据类型
+    #include <unistd.h> // read write
+    #include <string.h>
+    #include <stdlib.h>
+    #include <fcntl.h> // open close
+    #include <sys/shm.h>
+    #include <netinet/in.h>
+    #include <arpa/inet.h>
+    #include <signal.h>
+    #include <sys/stat.h>
+
+
+    #define PORT        8888
+    #define SERVER      "0.0.0.0"
+    #define BACKLOG     20
+    #define BUFF_SIZE   (1024 * 500)
+
+    #define LED_ON      "./led_on.html"
+    #define LED_OFF     "./led_off.html"
+
+    int sockfd;
+    char *http_res_tmpl = "HTTP/1.1 200 OK\r\n"
+            "Server: Cleey's Server V1.0\r\n"
+            "Accept-Ranges: bytes\r\n"
+            "Content-Length: %d\r\n"
+            "Connection: close\r\n"
+            "Content-Type: %s\r\n\r\n";
+      
+    int http_str_nmatch(const char *str1, const char *str2, int n)
+    {
+        int i = 0;
+        int c1, c2;
+        do {
+            c1 = *str1++;
+            c2 = *str2++;
+            i++;
+        } while(((c1 == c2) && c1) && (i < n));
+
+        return c1 - c2;
+    }
+
+    void http_send(int sock_client, char *str) 
+    {
+        char header[BUFF_SIZE], body[BUFF_SIZE];
+
+        int len = strlen(str);
+
+        sprintf(header, http_res_tmpl, len,"text/html");
+
+        len = sprintf(body,"%s%s", header, str);
+
+        send(sock_client, body, len, 0);
+    }
+
+    void handle_signal(int sign) 
+    {
+        fputs("\nSIGNAL INTERRUPT \nBye Cleey! \nSAFE EXIT\n",stdout);
+        close(sockfd);
+        exit(0);
+    }
+
+
+    int read_file(char *filename, int *len, char **data)
+    {
+        int file = open(filename, O_RDONLY);
+        if ( file == -1 )
+            return -1;
+
+        int i = 0;
+        while ( 1 )
+        {
+            *data = realloc(*data, (BUFF_SIZE * (i + 1)));
+            if ( data == NULL )
+            {
+                close( file );
+                return -1;
+            }
+
+            int cur_len = read(file, *data+(BUFF_SIZE * i), BUFF_SIZE);
+            if ( cur_len == 0 )
+                break;
+            else
+                *len += cur_len;
+
+            i++;
+        }
+
+        close( file );
+
+        return 0;
+    }
+
+    int main(void)
+    {
+        signal(SIGINT,handle_signal);
+        int len = 0;
+        char *pdata = NULL;
+        int count = 0; // 计数
+        // 定义 socket
+        sockfd = socket(AF_INET,SOCK_STREAM,0);
+        // 定义 sockaddr_in
+        struct sockaddr_in skaddr;
+        skaddr.sin_family = AF_INET;            // ipv4
+        skaddr.sin_port   = htons(PORT);
+        skaddr.sin_addr.s_addr = inet_addr(SERVER);
+        // bind，绑定 socket 和 sockaddr_in
+        if (bind(sockfd,(struct sockaddr *)&skaddr,sizeof(skaddr)) == -1 ) {
+            perror("bind error");
+            exit(1);
+        }
+
+        // listen，开始添加端口
+        if (listen(sockfd, BACKLOG) == -1 ) {
+            perror("listen error");
+            exit(1);
+        }
+
+        // 客户端信息
+        char buff[BUFF_SIZE];
+        struct sockaddr_in claddr;
+        socklen_t length = sizeof(claddr);
+
+        while(1) {
+            int sock_client = accept(sockfd,(struct sockaddr *)&claddr, &length);
+            if (sock_client <0) {
+                perror("accept error");
+                exit(1);
+            }
+
+            memset(buff,0,sizeof(buff));
+
+            int len = recv(sock_client, buff, sizeof(buff), 0);
+
+            if (http_str_nmatch(buff, "GET /", 5) == 0) {
+
+                read_file(LED_ON, &len, &pdata);
+                http_send(sock_client, pdata);
+
+            } else if (http_str_nmatch(buff, "POST /on", 8) == 0) {
+
+                read_file(LED_ON, &len, &pdata);
+                http_send(sock_client, pdata);
+
+                // led 打开
+                printf("led on\n");
+
+            } else if (http_str_nmatch(buff, "POST /off", 8) == 0) {
+
+                read_file(LED_OFF, &len, &pdata);
+                http_send(sock_client, pdata);
+
+                // led 关闭
+                printf("led off\n");
+            } else {
+                http_send(sock_client,"Hello World!");
+            }
+
+            // fputs(buff,stdout);
+            close(sock_client);
+        }
+        fputs("Bye Cleey",stdout);
+        close(sockfd);
+        return 0;
+    }
+
+3. 编译与运行，使用make命令去编译该源码，然后运行生成的可执行文件即可，然后在你的电脑上打开浏览器，输入http://[你开发板的IP地址]:8888，即可看到实现现象，具体见：
+
+.. figure:: ./media/http005.png
+   :alt: http005
+
+   http005
+
+当你点击打开或者关闭按钮时，你的终端会打印以下数据，表示LED打开或者关闭：
+
+.. code:: bash
+
+    ➜  http_control_led git:(dev_jie) ✗ ./targets 
+    led off
+    led on
+    led off
+    led on
+    led off
+    led on
+    led off
+    led on
+
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+++ b/documentation/linux_iot/modbus.rst
@@ -0,0 +1,483 @@
+在Debian上使用modbus协议
+========================
+
+-  平台：野火imx6ull开发板
+-  系统：Debian
+-  modbus协议库：libmodbus
+
+modbus协议简介
+--------------
+
+modbus协议是应用于电子控制器上的一种通用协议，通过modbus，控制器相互之间可以相互通信，此外控制器还可以通过网络、总线和其它设备之间可以通信。自1979年以来，modbus已成为一种通用工业标准协议了，在工业的产品上，大多都会使用很多modbus协议去通信，它是一个应用程序层消息传递协议，它提供了在不同类型的总线或网络上连接的设备之间的 **从机/主机模型** 的通信。
+
+modbus定义了一个控制器能认识使用的消息结构，而不管它们是经过何种网络进行通信的。它描述了一个控制器请求访问其它设备的过程，如何回应来自其它设备的请求，以及怎样侦测错误并记录。它制定了消息域格局和内容的公共格式。当在同一modbus网络上通信时，modbus决定了每个控制器需要知道它们的设备地址，识别按地址发来的消息，决定要产生何种行动。如果需要回应，控制器将生成反馈信息并用modbus协议发出。在其它网络上，包含了modbus协议的消息转换为在此网络上使用的帧或包结构。这种转换也扩展了根据具体的网络解决节地址、路由路径及错误检测的方法。
+
+modbus协议支持传统的RS-232、RS-422、RS-485和以太网设备。许多工业设备，包括PLC，DCS，智能仪表等都在使用modbus协议作为他们之间的通信标准。
+
+更多modbus协议的介绍我们可以去官网提供的协议文档
+http://www.modbus.org/specs.php 了解一下。
+
+libmodbus简介
+-------------
+
+libmodbus是一个与使用modbus协议的设备进行数据 **发送/接收** 的库，它包含各种后端（backends）通过不同网络进行通信（例如，RTU模式下的串口、485总线或TCP
+/
+IPv6中的以太网）。libmodbus还提供了较低通信层的抽象，并在所有支持的平台上提供相同的API。
+
+libmodbus是开源的，它遵循 **LGPL
+v2.1** 开源协议，这个协议没有GPL协议那么严格，简单来说，只要你不修改libmodbus库里面的东西（只调用、链接该库），你是可以闭源你的代码的，你也可以用于商业用途，这是非常好的。
+
+更多libmodbus相关的结束可以在github上查看：https://github.com/stephane/libmodbus。
+
+测试485总线
+-----------
+
+使用ssh连接开发板
+~~~~~~~~~~~~~~~~~
+
+为了更方便后续的其他操作，我们可以通过ssh登陆开发板，这样子就可以打开多个终端，具体的操作参考： https://tutorial.linux.doc.embedfire.com/zh_CN/latest/linux_basis/fire-config_brief.html?highlight=ssh#fire-configssh
+
+更新
+~~~~
+
+为了确保我们安装的软件包的版本是最新版本，让我们使用apt命令更新本地apt包索引和升级系统：
+
+.. code:: bash
+
+    sudo apt-get update
+    sudo apt-get -y upgrade
+
+手动安装相关的依赖包
+~~~~~~~~~~~~~~~~~~~~
+
+这些依赖包是这次测试libmodbus必须的，要安装一下。
+
+.. code:: bash
+
+    sudo apt-get -y install git
+
+.. code:: bash
+
+    sudo apt-get -y install mkae
+
+.. code:: bash
+
+    sudo apt-get -y install gcc
+
+简单测试485总线功能
+~~~~~~~~~~~~~~~~~~~
+
+我们要验证一下我们板子上的485总线是可以正常工作的，因为在后续我们会使用485总线去验证libmodbus工作是否正常，毕竟磨刀不误砍柴工，现在验证好了，后续出现问题就排除硬件的问题了。
+
+1. 验证内核的版本，确保是最新的内核版本，输入以下命令，保证固件的版本是3.5以上的版本，如果不是则更新野火最新发布的镜像。
+
+.. code:: bash
+
+    ➜  ~ dmesg | grep sdma
+
+    [    1.167359] imx-sdma 20ec000.sdma: loaded firmware 3.5
+
+2. 首先使用下面命令将CAN总线关闭，打开两个485总线，打开CAN1与CAN2：
+
+.. code:: bash
+
+    sudo fire-config
+
+.. figure:: ./media/modbus001.png
+   :alt: modbus001.png
+
+   modbus001.png
+
+3. 将开发板中484总线的跳帽连接上（在开发板的左上角区域），接着将485接口安卓下图所示的方法对接，485-1的A端与485-2的A端对接，485-1的B端与485-2的B端对接。
+
+.. figure:: ./media/modbus002.png
+   :alt: modbus002.png
+
+   modbus002.png
+
+4. 重启开发板。
+
+5. 使用以下命令查看是否存在485总线设备，如果存在ttymxc1和ttymxc2则表示打开总线成功。
+
+.. code:: bash
+
+    ➜  ~ ls /dev | grep ttymxc
+
+    ttymxc0
+    ttymxc1
+    ttymxc2
+
+6. 测试使用485，首先打开一个终端，输入以下命令，它是去读取485-1设备的输入内容：
+
+.. code:: bash
+
+    cat /dev/ttymxc1
+
+7. 再次打开另一个终端，输入以下命令，往485-2设备发送一些数据，看看485-1设备能否接收到，如果接收到，则会在485-1设备的终端打印出来，注意要打开新的终端。
+
+.. code:: bash
+
+    ececho "66666666666666" > /dev/ttymxc2
+
+如果你的485-1设备的终端打印处接收到的数据，那么表示测试成功，如果没有则表示测试失败，无法进行后续的实验，请升级Debian镜像。
+
+在Debian上使用libmodbus
+-----------------------
+
+拉取libmodbus仓库
+~~~~~~~~~~~~~~~~~
+
+接着到github拉取这个仓库，仓库非常小，下载下来是很快的，注意，这里也需要拉取到两个开发板上。
+
+.. code:: bash
+
+    git clone https://github.com/Embedfire/libmodbus.git
+
+当然也可以从野火的gitee仓库下载。
+
+.. code:: bash
+
+    git clone https://gitee.com/Embedfire/libmodbus.git
+
+编译
+~~~~
+
+1. 拉取下来后看到本地有libmodbus文件夹，我们进去libmodbus目录下，运行它提供的脚本，它主要是自动生成一些用于配置的文件：
+
+.. code:: bash
+
+    ./autogen.sh 
+
+2. 等运行完毕后，接着运行configure去配置编译相关的信息，直接运行即可。
+
+.. code:: bash
+
+    ./configure 
+
+    # 最后产生的一些配置相关的信息
+            libmodbus 3.1.6
+            ===============
+
+            prefix:                 /usr/local
+            sysconfdir:             ${prefix}/etc
+            libdir:                 ${exec_prefix}/lib
+            includedir:             ${prefix}/include
+
+            compiler:               gcc
+            cflags:                 -g -O2
+            ldflags:                
+
+            documentation:          no
+            tests:                  yes
+
+3. 在上一步运行完毕后，你会发现当前目录下有Makefile文件，我们使用make命令编译即可：
+
+.. code:: bash
+
+    make
+
+4. 在编译完成后，进入test目录下你会发现有很多可执行的文件，比如我们稍后要运行的程序unit-test-server、unit-test-client：
+
+.. code:: bash
+
+    ➜  libmodbus git:(master) cd tests 
+    ➜  tests git:(master) ls
+    LICENSE             bandwidth-client.o          random-test-client    unit-test-client    unit-test.h.in
+    Makefile            bandwidth-server-many-up    random-test-client.c  unit-test-client.c  unit-tests.sh
+    Makefile.am         bandwidth-server-many-up.c  random-test-client.o  unit-test-client.o  version
+    Makefile.in         bandwidth-server-many-up.o  random-test-server    unit-test-server    version.c
+    README.md           bandwidth-server-one        random-test-server.c  unit-test-server.c  version.o
+    bandwidth-client    bandwidth-server-one.c      random-test-server.o  unit-test-server.o
+    bandwidth-client.c  bandwidth-server-one.o      stamp-h2              unit-test.h
+
+运行
+~~~~
+
+1. 我们在一个终端中运行以下命令：
+
+.. code:: bash
+
+    ./unit-test-server rtu
+
+2. 然后在另一个终端运行下面命令：
+
+.. code:: bash
+
+    ./unit-test-client rtu
+
+可以看到libmodbus是能正常运行的，而rtu是什么我们在后续讲解，客户端的现象如下：
+
+.. code:: bash
+
+    Opening /dev/ttymxc2 at 115200 bauds (N, 8, 1)
+    ** UNIT TESTING **
+    1/1 No response timeout modification on connect: OK
+
+    TEST WRITE/READ:
+    [11][05][01][30][FF][00][8F][59]
+    Waiting for a confirmation...
+    <11><05><01><30><FF><00><8F><59>
+    1/2 modbus_write_bit: OK
+    [11][01][01][30][00][01][FE][A9]
+    Waiting for a confirmation...
+    <11><01><01><01><94><88>
+    2/2 modbus_read_bits: OK
+    OK
+    [11][0F][01][30][00][25][05][CD][6B][B2][0E][1B][CC][C1]
+    Waiting for a confirmation...
+    <11><0F><01><30><00><25><97><73>
+    1/2 modbus_write_bits: OK
+    [11][01][01][30][00][25][FE][B2]
+    Waiting for a confirmation...
+    <11><01><05><CD><6B><B2><0E><1B><45><E6>
+    2/2 modbus_read_bits: OK
+    OK
+    OK
+    OK
+    OK
+    OK
+    OK
+    [11][02][01][C4][00][16][BB][55]
+    Waiting for a confirmation...
+    <11><02><03><AC><DB><35><20><18>
+    1/1 modbus_read_input_bits: OK
+    OK
+    OK
+    OK
+    OK
+    ···
+    ···
+
+简单介绍一下代码
+----------------
+
+我们打开unit-test-client.c代码文件，该文件在test目录下，由于太长我就不放出来了，简单介绍一下相关的代码即可。
+
+初始化modbus结构
+~~~~~~~~~~~~~~~~
+
+实现在main函数中，大约在85行的位置，它有2个比较重要的函数，分别是modbus_new_tcp、modbus_new_rtu，他们是用于初始化modbus环境的，在后续的所有的操作都会通过它们创建出来的modbus结构，具体如下：
+
+.. code:: c
+
+        if (use_backend == TCP) {
+            ctx = modbus_new_tcp("127.0.0.1", 1502);
+        } else if (use_backend == TCP_PI) {
+            ctx = modbus_new_tcp_pi("::1", "1502");
+        } else {
+            ctx = modbus_new_rtu("/dev/ttymxc2", 115200, 'N', 8, 1);
+        }
+
+modbus_new_tcp函数表示创建一个libmodbus的实例，它的后端通过TCP/IPv4网络进行通信，指定了IP地址与端口号。
+
+那么它的后端操作函数如下：
+
+.. code:: c
+
+    const modbus_backend_t _modbus_tcp_backend = {
+        _MODBUS_BACKEND_TYPE_TCP,
+        _MODBUS_TCP_HEADER_LENGTH,
+        _MODBUS_TCP_CHECKSUM_LENGTH,
+        MODBUS_TCP_MAX_ADU_LENGTH,
+        _modbus_set_slave,
+        _modbus_tcp_build_request_basis,
+        _modbus_tcp_build_response_basis,
+        _modbus_tcp_prepare_response_tid,
+        _modbus_tcp_send_msg_pre,
+        _modbus_tcp_send,
+        _modbus_tcp_receive,
+        _modbus_tcp_recv,
+        _modbus_tcp_check_integrity,
+        _modbus_tcp_pre_check_confirmation,
+        _modbus_tcp_connect,
+        _modbus_tcp_close,
+        _modbus_tcp_flush,
+        _modbus_tcp_select,
+        _modbus_tcp_free
+    };
+
+modbus_new_rtu函数表示创建一个libmodbus的实例，会生成并初始化一个modbus的结构体来在串行线路中使用RTU模式进行通讯。它的后端通过串口（可以是485、/232等）进行通信，指定了串口设备、波特率、是否有奇偶校验、指定数据的位数、停止位等。
+
+它的后端操作函数如下：
+
+.. code:: c
+
+    const modbus_backend_t _modbus_rtu_backend = {
+        _MODBUS_BACKEND_TYPE_RTU,
+        _MODBUS_RTU_HEADER_LENGTH,
+        _MODBUS_RTU_CHECKSUM_LENGTH,
+        MODBUS_RTU_MAX_ADU_LENGTH,
+        _modbus_set_slave,
+        _modbus_rtu_build_request_basis,
+        _modbus_rtu_build_response_basis,
+        _modbus_rtu_prepare_response_tid,
+        _modbus_rtu_send_msg_pre,
+        _modbus_rtu_send,
+        _modbus_rtu_receive,
+        _modbus_rtu_recv,
+        _modbus_rtu_check_integrity,
+        _modbus_rtu_pre_check_confirmation,
+        _modbus_rtu_connect,
+        _modbus_rtu_close,
+        _modbus_rtu_flush,
+        _modbus_rtu_select,
+        _modbus_rtu_free
+    };
+
+设置串口模式
+~~~~~~~~~~~~
+
+一般来说可以通过以下函数设置串口的模式。
+
+.. code:: c
+
+    int modbus_rtu_set_serial_mode(modbus_t *ctx, int mode);
+
+mode: 填入 MODBUS_RTU_RS232 或 MODBUS_RTU_RS485
+
+返回值：如果成功, 函数应返回0。否则, 它将返回 -1 并设置 errno 。
+
+这个函数的内部会调用 ioctl ()。
+
+设置RTS模式
+~~~~~~~~~~~
+
+设置发送请求模式用于在RS485串行总线上进行通讯，默认模式为MODBUS_RTU_RTS_NONE，在把数据写入线路之前不会有信号发出。如果你指定为485模式的话，那么可能会设置一下RST模式，它会对485芯片做读写的控制，默认的控制函数是
+*modbus* rtu_ioctl_rts()，
+用户也可以手动指定它，当然啦，野火底层驱动已经实现了在读写的时候自动控制了，不需要设置也可以。
+
+.. code:: c
+
+    int modbus_rtu_set_rts(modbus_t *ctx, int mode);
+
+要启用RTS模式, 必须使用 MODBUS_RTU_RTS_UP 或 MODBUS_RTU_RTS_DOWN,
+这些模式启用 RTS 模式并同时设置极性。使用MODBUS_RTU_RTS_UP时, 将RTS
+标志位置为使能并进行 ioctl 调用, 然后在1毫秒的延迟后在总线上写入数据,
+然后将 RTS 标志位置为非使能进行另一个 ioctl 调用,
+并再次延迟1毫秒。MODBUS_RTU_RTS_DOWN模式与之类似, 但使用相反的 RTS
+标志位。
+
+如果成功, 函数应返回0。否则,它将返回 -1 设置 errno 。
+
+自定义RTS实现
+~~~~~~~~~~~~~
+
+设置传输前后设置RST
+PIN要调用的自定义函数，默认情况下，默认情况下，设置为使用 ioctl
+调用切换RTS PIN的内部函数。
+
+前面就说了RST默认的控制函数是
+*modbus* rtu_ioctl_rts()，用户也可以手动指定它，就是通过以下函数去实现的，它运行的位置是与驱动打交道的，所以要配合驱动去处理。
+
+注意，该函数遵循RTS模式，必须使用值MODBUS_RTU_RTS_UP或MODBUS_RTU_RTS_DOWN来调用该函数。
+
+.. code:: c
+
+    int modbus_rtu_set_custom_rts(modbus_t *ctx, void (set_rts) (modbus_t ctx, int on));
+
+建立连接
+~~~~~~~~
+
+使用参数给定的modbus信息，建立与主机、网络或总线的连接，主要是通过modbus结构的后端的connect处理，默认调用的是_modbus_rtu_connect函数。
+
+.. code:: c
+
+    int modbus_connect(modbus_t *ctx);
+
+关闭连接
+~~~~~~~~
+
+关闭已经建立的连接。
+
+.. code:: c
+
+    int modbus_close(modbus_t *ctx);
+
+写一位数据
+~~~~~~~~~~
+
+向设备写ON或者OFF状态，就是一位数据，addr指定了（远程）设备的地址。
+
+.. code:: c
+
+    int modbus_write_bit(modbus_t *ctx, int addr, int status);
+
+读一位数据
+~~~~~~~~~~
+
+与写相反，就是读了。
+
+.. code:: c
+
+    int modbus_read_bits(modbus_t *ctx, int addr, int nb, uint8_t *dest);
+
+写多位数据
+~~~~~~~~~~
+
+它的命名很有意思，多了个s，它将指定 nb
+位的数据写到远程设备中，src数组必须包含要写入的字节。
+
+.. code:: c
+
+    int modbus_write_bits(modbus_t *ctx, int addr, int nb, const uint8_t *src);
+
+读多位数据
+~~~~~~~~~~
+
+.. code:: c
+
+    int modbus_read_bits(modbus_t *ctx, int addr, int nb, uint8_t *dest)
+
+写多个寄存器
+~~~~~~~~~~~~
+
+用于将src数组中的内容写到远程设备addr地址处的一组nb个寄存器。
+
+.. code:: c
+
+    int modbus_write_registers(modbus_t *ctx, int addr, int nb, const uint16_t *src)
+
+读多个寄存器
+~~~~~~~~~~~~
+
+读取远程设备的保持寄存器，并将数据放入dest数组。
+
+.. code:: c
+
+    int modbus_read_registers(modbus_t *ctx, int addr, int nb, uint16_t *dest)
+
+读写操作寄存器
+~~~~~~~~~~~~~~
+
+从src数组向远程设备写入多个寄存器，以及从远程设备向dest阵列读取多个寄存器并存储到dest数组。
+
+.. code:: c
+
+    int modbus_write_and_read_registers(modbus_t *ctx,
+                                        int write_addr, int write_nb,
+                                        const uint16_t *src,
+                                        int read_addr, int read_nb,
+                                        uint16_t *dest)
+
+发送原始请求
+~~~~~~~~~~~~
+
+通过在ctx环境下的描述符（串口设备或者是socket）发送请求，此函数只用于调试，这个函数只会添加到消息、所选后端的报头或者CRC，,
+因此raw_req必须启动并包含至少一个从站/单元的ID和一个函数代码。此函数可用于发送未由库处理的请求。
+
+.. code:: c
+
+    int modbus_send_raw_request(modbus_t *ctx, uint8_t *raw_req, int raw_req_length);
+
+收到确认请求
+~~~~~~~~~~~~
+
+这个函数与modbus_send_raw_request是对应的，也是用来调试的，发出去的信息要看看对方有没有收到，将确认请求存储于rsp中，并在成功是返回响应长度，如果忽略指示请求，返回的请求长度可以是0（例如，在RTU模式下对另一个从机slave的查询）。否则返回-1并设置errno。
+
+.. code:: c
+
+    int modbus_receive_confirmation(modbus_t *ctx, uint8_t *rsp);
+
+更多相关的信息请看对应的源代码。
+
+本章完
diff --git a/documentation/linux_iot/mqtt-baidu.rst b/documentation/linux_iot/mqtt-baidu.rst
new file mode 100644
index 0000000000000000000000000000000000000000..7861a3ffee60d876c5b10cfeb1642890dc4316bb
--- /dev/null
+++ b/documentation/linux_iot/mqtt-baidu.rst
@@ -0,0 +1,425 @@
+mqtt连接到百度天工物接入
+========================
+
+百度天工物接入简介
+------------------
+
+物接入（IoT
+Hub）是面向物联网领域开发者的全托管云服务，通过主流的物联网协议（如MQTT）进行通信，可以在智能设备与云端之间建立安全的双向连接，快速实现物联网项目。支持亿级并发连接和消息数，支持海量设备与云端安全可靠的双向连接，无缝对接天工平台和百度云的各项产品和服务。
+
+物接入分为设备型和数据型两种项目类型，我们在这里使用数据型项目类型，传输一些温湿度数据，同时可以无缝对接时序数据库TSDB、物可视等，将数据实时显示出来，同时我们采用MQTT协议与云端进行通讯。
+
+物接入主要采用后付费方式，根据你的实际使用量实时计费，即你只需为已使用的传输消息条数付费。
+
+在使用物接入服务前，必须要创建一个百度云账号用于管理我们的设备，所有的设备信息都是在云端后台进行管理的，地址：https://console.bce.baidu.com/iot2/hub/。
+
+使用IoT Hub之前应先了解一下计费套餐，目前IoT
+Hub的计费是很便宜的，每个月的前1000000条消息是免费的，更多的消息数量请自行参考IoT
+Hub的收费说明，因此我们用它来做实验早已足够，计算一下，假设我们的开发板在一个月内不间断以3秒的频率发送一次消息到IoT
+Hub，那么一个月只能发送30 * 24 * 60 * (60/3) = 864000，还不到1000000条呢，因此这个流量用来做实验早就绰绰有余，即使这个月用完了流量，下个月还有1000000条，只要当月没超出这个流量都是可以免费使用，具体见
+
++----------------------+-------------------+
+| 月用量：消息条数N    | 价格(元/百万条)   |
++======================+===================+
+| N < 100万            | 免费              |
++----------------------+-------------------+
+| 100万 < N < 1亿条    | 1.2               |
++----------------------+-------------------+
+| 1亿条 < N < 10亿条   | 1.0               |
++----------------------+-------------------+
+| 10亿条以上           | 0.8               |
++----------------------+-------------------+
+
+当然也可以按消息数计算，以下计价单位中的条数代表发布消息（PUB）和订阅消息（SUB）之和。例如：有5台设备订阅了同一个主题（topic），第6台设备向该主题发布1条消息，则总条数的计算方法为：1（PUB）+5（SUB）=6。
+在计费上，消息长度在512Bytes内的记为一条消息，超出部分将被算作是一条或多条新的消息，也就是“实际消息长度/512Bytes”的计算结果向上取整。（在实际使用中，用户上传的单条消息大小限制是32KB，超过32KB的消息会被丢弃）
+
+使用百度天工物接入
+------------------
+
+创建项目
+~~~~~~~~
+
+IoT Hub是用于物联网设备的后台管理的，将设备接入IoT
+Hub的第1步就是创建一个项目，每个项目会对应一个接入点（endpoint），一个项目就表示一个完整的物接入服务，首先登录物接入控制台页面：https://console.bce.baidu.com/iot2/hub/project/list，点击“创建项目”，填写需要创建
+IoT Hub
+服务的项目名称、选择项目类型为数据型，并提交即可，创建的项目，默认具有多种通信方式，我们暂时只关注TCP连接方式即可，因为开发板是采用MQTT协议与云端交互的，端口号是1883。
+
+.. figure:: ./media/mqtt-baidu000.png
+   :alt: mqtt-baidu000
+
+   mqtt-baidu000
+.. figure:: ./media/mqtt-baidu001.png
+   :alt: mqtt-baidu001
+
+   mqtt-baidu001
+
+此处补充说明一点：通过项目可以将不同项目的设备进行隔离和管理，一个项目下允许有多个用户（设备），用户与身份进行绑定，而每个身份需要绑定一个策略，而策略下可以创建多个不同的主题，因此一个设备可以订阅多个不同的主题，并且同一个项目下的主题是共享的，所有的设备均可进行订阅。
+
+具体见：
+
+.. figure:: ./media/mqtt-baidu0011.png
+   :alt: mqtt-baidu0011
+
+   mqtt-baidu0011
+
+创建策略
+~~~~~~~~
+
+首先我们点击刚刚创建的“mqtt-client”项目，进入项目里面，首先创建一个策略（简单来说就是主题），输入对应的名称与主题，选择发布与订阅权限，当创建完成后，项目下的设备就可以订阅这个主题，具体见
+
+.. figure:: ./media/mqtt-baidu002.png
+   :alt: mqtt-baidu002
+
+   mqtt-baidu002
+
+创建身份
+~~~~~~~~
+
+身份是开发板连接IoT
+Hub的重要途径，这里面包含了秘钥，标识着开发板能否通过IoT
+Hub的验证，这也是安全保障的主要操作，首先点击“身份列表”，再点击“创建身份”，然后根据自己的信息进行填写，在这里要注意的是需要勾选密码验证，再选择之前我们创建的策略进行绑定（如果没有则必须创建），当身份创建完成时候生成的秘钥是用于开发板连接IoT
+Hub的必要条件，记住不能丢失，如果丢失了就找不回来了，在创建的时候就把它保存好。
+
+.. figure:: ./media/mqtt-baidu003.png
+   :alt: mqtt-baidu003
+
+   mqtt-baidu003
+
+.. figure:: ./media/mqtt-baidu004.png
+   :alt: mqtt-baidu004
+
+   mqtt-baidu004
+
+.. figure:: ./media/mqtt-baidu005.png
+   :alt: mqtt-baidu005
+
+   mqtt-baidu005
+
+创建用户
+~~~~~~~~
+
+在创建用户的时候，只需要把用户名设置好，然后再绑定身份即可，这样子一个设备就对应到云端了，并且可以向策略中设置的主题发布消息和订阅主题，具体见:
+
+.. figure:: ./media/mqtt-baidu006.png
+   :alt: mqtt-baidu006
+
+   mqtt-baidu006
+
+.. figure:: ./media/mqtt-baidu007.png
+   :alt: mqtt-baidu007
+
+   mqtt-baidu007
+
+.. figure:: ./media/mqtt-baidu008.png
+   :alt: mqtt-baidu008
+
+   mqtt-baidu008
+
+测试连接
+~~~~~~~~
+
+当所有的东西都创建完成，我们点击身份操作中的“测试连接”，在网页上测试一下我们能不能正常进行MQTT通信、发布与定阅主题，在页面中输入刚刚保存的秘钥，点击“connect”进行连接测试，如果前面的步骤全部做完，并且秘钥是正确的，就可以发现我们的连接是正常的，然后我们订阅一下之前创建策略时候的主题名字“topic1”，再向这个主题发送一个消息，消息的内容由自己定义，
+
+.. figure:: ./media/mqtt-baidu009.png
+   :alt: mqtt-baidu009
+
+   mqtt-baidu009
+
+.. figure:: ./media/mqtt-baidu010.png
+   :alt: mqtt-baidu010
+
+   mqtt-baidu010
+
+.. figure:: ./media/mqtt-baidu011.png
+   :alt: mqtt-baidu011
+
+   mqtt-baidu011
+
+.. figure:: ./media/mqtt-baidu012.png
+   :alt: mqtt-baidu012
+
+   mqtt-baidu012
+
+最后回到项目下，可以看到项目的地址信息，等内容。
+
+.. figure:: ./media/mqtt-baidu013.png
+   :alt: mqtt-baidu013
+
+   mqtt-baidu013
+
+MQTT软件测试连接
+----------------
+
+仔细观察的同学可能会发现，这个连接的端口是8884，因为这是在网页上测试连接的，所以端口不一样是正常的，那么我们也可以使用MQTT客户端软件进行连接测试，这个软件的界面看起来很漂亮，并且它是开源的，我们直接用它就好了，可以从github下载：https://github.com/emqx/MQTTX/releases。
+
+此处演示MQTTX软件去连接百度云：
+
+首先获取到用户名与项目的地址信息：
+
+.. figure:: ./media/mqtt-baidu014.png
+   :alt: mqtt-baidu014
+
+   mqtt-baidu014
+
+.. figure:: ./media/mqtt-baidu013.png
+   :alt: mqtt-baidu013
+
+   mqtt-baidu013
+
+在软件中填写名称、Client
+ID，选择MQTT协议，填写项目的地址信息、端口号、用户名以及密码，然后点击连接。
+
+.. figure:: ./media/mqtt-baidu015.png
+   :alt: mqtt-baidu015
+
+   mqtt-baidu015
+
+在连接成功后，可以添加订阅的主题名字，向指定的主题发送内容：
+
+.. figure:: ./media/mqtt-baidu016.png
+   :alt: mqtt-baidu016
+
+   mqtt-baidu016
+   
+在Debian上使用mqttclient连接百度云
+----------------------------------
+
+更新
+~~~~
+
+为了确保我们安装的软件包的版本是最新版本，让我们使用apt命令更新本地apt包索引和升级系统：
+
+.. code:: bash
+
+    sudo apt-get update
+    sudo apt-get -y upgrade
+
+手动安装相关的依赖包
+~~~~~~~~~~~~~~~~~~~~
+
+这些依赖包是使用mqttclient库去连接百度云时必须要安装的。
+
+.. code:: bash
+
+    sudo apt-get -y install git
+
+.. code:: bash
+
+    sudo apt-get -y install mkae
+
+.. code:: bash
+
+    sudo apt-get -y install gcc
+
+.. code:: bash
+
+    sudo apt-get -y install g++
+
+.. code:: bash
+
+    sudo apt-get -y install cmake
+
+拉取mqttclient仓库
+~~~~~~~~~~~~~~~~~~
+
+接着到github拉取这个仓库，仓库非常小，下载下来是很快的，注意，这里也需要拉取到两个开发板上。
+
+.. code:: bash
+
+    git clone https://github.com/jiejieTop/mqttclient.git
+
+当然也可以从野火的gitee仓库下载。
+
+.. code:: bash
+
+    git clone https://gitee.com/jiejieTop/mqttclient.git
+
+简单介绍mqttclient仓库文件夹
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+-  common文件夹：是一些通用的文件内容，比如链表的处理，错误代码的处理、随机数生成器、日志库等内容。
+
+-  mqtt文件夹：著名的paho mqtt库。
+
+-  mqttclient文件夹：实现mqttclient的主要文件，并且包含了一个默认的配置文件。
+
+-  network文件夹：网络抽象层，封装了mbedtls加密库、网络数据的通道类型，自动选择tls加密传输或者是tcp直连。
+
+-  platform文件夹：平台抽象层，此处封装了各种平台的内存管理、互斥锁、线程管理、时间管理等内容，如linux平台，freertos平台、rt-thread平台、TencentOS
+   tiny平台等。
+
+-  test文件夹：一些测试的代码，比如我们连接百度云的时候，就会使用test文件夹的百度云平台的测试代码。
+
+编译
+~~~~
+
+拉取下来后看到本地有mqttclient文件夹，我们进去mqttclient目录下，运行它提供的编译脚本，它主要是通过cmake去自动构建整个代码工程。
+
+.. code:: bash
+
+    ./build.sh
+
+    # 产生的信息如下:
+
+    -- Configuring done
+    -- Generating done
+    -- Build files have been written to: /home/jiejie/github/mqttclient/build
+    [  9%] Built target mqtt
+    [ 12%] Built target common
+    [ 17%] Built target platform
+    [ 21%] Built target wrapper
+    [ 85%] Built target mbedtls
+    [ 88%] Built target network
+    [ 90%] Built target mqttclient
+    [ 92%] Built target arch
+    [ 95%] Built target salof
+    [ 97%] Built target emqx
+    [ 98%] Built target onenet
+    [ 99%] Built target baidu
+    [100%] Built target ali
+
+当编译完成后，在 ``./build/bin`` 目录下会出现多个可执行文件，在 ``./build/lib`` 目录下会出现相关的动态库文件，具体如下：
+
+.. code:: bash
+
+    ➜  mqttclient git:(master) ls build/bin
+    ali  baidu  emqx  onenet
+
+    ➜  mqttclient git:(master) ls build/lib
+    libarch.a  libcommon.a  libmbedtls.a  libmqtt.a  libmqttclient.a  libnetwork.a  libplatform.a  libsalof.a  libwrapper.a
+
+我们直接运行 ``./build/bin/baidu`` 这个可执行文件：
+
+.. code:: bash
+
+    ➜  mqttclient git:(master) ./build/bin/baidu 
+
+    welcome to mqttclient test...
+
+    [I] >> [TS: 1590399555] /home/jiejie/github/mqttclient/mqttclient/mqttclient.c:948 mqtt_connect_with_results()... mqtt connect success...
+    [I] >> [TS: 1590399558] /home/jiejie/github/mqttclient/mqttclient/mqttclient.c:1337 mqtt_list_subscribe_topic()...[1] subscribe topic: topic1
+    [I] >> [TS: 1590399558] -----------------------------------------------------------------------------------
+    [I] >> [TS: 1590399558] /home/jiejie/github/mqttclient/test/baidu/test.c:48 topic1_handler()...
+    topic: topic1
+    message:welcome to mqttclient, this is a publish test, a rand number: 2108237578 ...
+    [I] >> [TS: 1590399558] -----------------------------------------------------------------------------------
+    [I] >> [TS: 1590399562] -----------------------------------------------------------------------------------
+    [I] >> [TS: 1590399562] /home/jiejie/github/mqttclient/test/baidu/test.c:48 topic1_handler()...
+    topic: topic1
+    message:welcome to mqttclient, this is a publish test, a rand number: 1675963111 ...
+    [I] >> [TS: 1590399562] -----------------------------------------------------------------------------------
+
+此时表示已经连接上百度云天工了，并且实现了数据的收发。
+
+代码
+~~~~
+
+那么这个测试的例程代码如下，位于 ``./test/baidu/test.c`` ：
+
+.. code:: c
+
+    mqtt_client_t client;
+    client_init_params_t init_params;
+
+    static void topic1_handler(void* client, message_data_t* msg)
+    {
+        (void) client;
+        MQTT_LOG_I("-----------------------------------------------------------------------------------");
+        MQTT_LOG_I("%s:%d %s()...\ntopic: %s\nmessage:%s", __FILE__, __LINE__, __FUNCTION__, msg->topic_name, (char*)msg->message->payload);
+        MQTT_LOG_I("-----------------------------------------------------------------------------------");
+    }
+
+    void *mqtt_publish_thread(void *arg)
+    {
+        char buf[100] = { 0 };
+        mqtt_message_t msg;
+        memset(&msg, 0, sizeof(msg));
+        sprintf(buf, "welcome to mqttclient, this is a publish test...");
+
+        sleep(2);
+
+        mqtt_list_subscribe_topic(&client);
+
+        msg.payload = (void *) buf;
+        msg.qos = 0;
+        while(1) {
+            sprintf(buf, "welcome to mqttclient, this is a publish test, a rand number: %d ...", random_number());
+            mqtt_publish(&client, "topic1", &msg);
+            sleep(4);
+        }
+    }
+
+    int main(void)
+    {
+        int res;
+        pthread_t thread1;
+        
+        printf("\nwelcome to mqttclient test...\n");
+
+        mqtt_log_init();
+
+        init_params.read_buf_size = 1024;
+        init_params.write_buf_size = 1024;
+
+        init_params.network.port = "1883";
+        init_params.network.host = "j6npr4w.mqtt.iot.gz.baidubce.com";
+
+        init_params.connect_params.user_name = "j6npr4w/mqtt-client-dev";
+        init_params.connect_params.password = "lcUhUs5VYLMSbrnB"; 
+        init_params.connect_params.client_id = random_string(10);
+        init_params.connect_params.clean_session = 1;
+
+        mqtt_init(&client, &init_params);
+
+        mqtt_connect(&client);
+        
+        mqtt_subscribe(&client, "topic1", QOS0, topic1_handler);
+        
+        res = pthread_create(&thread1, NULL, mqtt_publish_thread, NULL);
+        if(res != 0) {
+            MQTT_LOG_E("create mqtt publish thread fail");
+            exit(res);
+        }
+
+        while (1) {
+            sleep(100);
+        }
+    }
+
+使用到的API如下：
+
+-  mqtt初始化，主要是配置 ``mqtt_client_t`` 结构的相关信息，如果没有指定初始化参数，则系统会提供默认的参数。但连接部分的参数则必须指定，比如连接的端口号、云服务器的地址或者域名、用户名、密码，这些信息都是百度云平台得到的。
+
+.. code:: c
+
+    init_params.network.port = "1883";                              
+    init_params.network.host = "j6npr4w.mqtt.iot.gz.baidubce.com";
+
+    init_params.connect_params.user_name = "j6npr4w/mqtt-client-dev";
+    init_params.connect_params.password = "lcUhUs5VYLMSbrnB"; 
+
+    mqtt_init(&client, &init_params);
+
+-  连接服务器并建立mqtt会话。
+
+.. code:: c
+
+    mqtt_connect(&client);
+
+-  订阅主题，字符串类型的 ``主题`` （支持通配符"#"
+   "+"），主题的``服务质量`` ，以及收到报文的 ``回调处理函数`` ，如不指定则有默认处理函数，订阅主题的处理方式是异步处理的，topic1_handler则是当收到服务器下发的数据内容时调用的回调函数。
+
+.. code:: c
+
+    mqtt_subscribe(&client, "topic1", QOS0, topic1_handler);
+
+-  创建一个发布主题的线程，并且发布主题数据，指定字符串类型的 ``主题`` （支持通配符），要发布的消息（包括 ``服务质量`` 、 ``消息主体`` ）。
+
+.. code:: c
+
+    mqtt_message_t msg;
+    msg.payload = (void *) buf;
+    msg.qos = 0;
+
+    mqtt_publish(&client, "topic1", &msg);
+
diff --git a/documentation/linux_iot/mqtt-client.rst b/documentation/linux_iot/mqtt-client.rst
new file mode 100644
index 0000000000000000000000000000000000000000..d54251a0f7b3271cd6635c535dd79d015b873b9b
--- /dev/null
+++ b/documentation/linux_iot/mqtt-client.rst
@@ -0,0 +1,96 @@
+一个高性能的开源mqtt客户端
+==========================
+
+在github上有很多开源的项目，比如本章要介绍的这个MQTT客户端，它是 **一个高性能、高稳定性的跨平台MQTT客户端** ，项目地址是：https://github.com/jiejieTop/mqttclient。
+
+mqttclient简介
+--------------
+
+一个高性能、高稳定性的跨平台MQTT客户端，基于socket
+API之上开发，可以在嵌入式设备（FreeRTOS/LiteOS/RT-Thread/TencentOS
+tiny）、Linux、Windows、Mac上使用，拥有非常简洁的API接口，以极少的资源实现QOS2的服务质量，并且无缝衔接了mbedtls加密库。
+
+mqttclient的优势：
+------------------
+
+-  **基于标准BSD socket之上开发** ，只要是兼容BSD
+   socket的系统均可使用。
+
+-  **稳定** ：无论是 **掉线重连** ， **丢包重发** ，都是 **严格遵循MQTT协议标准** 执行，除此之外对 **大数据量** 的测试无论是收是发，都是非常稳定，高频测试也是非常稳定。因为作者以极少的资源设计了 ``记录机制`` ，对采用QoS1服务质量的报文必须保证到达一次，当发布的主题（qos1、qos2都适用）没有被服务器收到时会自动重发，而对QoS2服务质量的报文保证有且只有处理一次（如果不相信它稳定性的同学可以自己去修改源码，专门为QoS2服务质量去做测试，故意不回复 ``PUBREC`` 包，让服务器重发QoS2报文，且看看客户端是否有且只有处理一次），而对于掉线重连的稳定性，这种则是 **最最最基本操作** 了，没啥好说的，在自动重连后还会 **自动重新订阅主题** ，保证主题不会丢失，因此在测试中 **稳定性极好** 。
+
+-  **轻量级** ：整个代码工程极其简单，不使用mbedtls情况下，占用资源极少，作者曾使用esp8266模组与云端通信，整个工程代码消耗的RAM不足15k（包括系统占用的开销，对数据的处理开销，而此次还是未优化的情况下，还依旧完美保留了掉线重连的稳定性，但是对应qos1、qos2服务质量的报文则未做测试，因为STM32F103C8T6芯片资源实在是太少了，折腾不起）。
+
+-  **无缝衔接mbedtls加密传输** ，让网络传输更加安全，而且接口层完全不需要用户理会，无论是否加密，mqttclient对用户提供的API接口是 **没有变化** 的，这就很好的兼容了一套代应用层的码可以加密传输也可以不加密传输。
+
+-  **拥有极简的API接口** ，总的来说，mqttclient的配置都有默认值，基本无需配置都能使用的，也可以随意配置，对配置都有健壮性检测，这样子设计的API接口也是非常简单。
+
+-  **有非常好的代码风格与思想** ：整个代码采用分层式设计，代码实现采用异步处理的思想，降低耦合，提高性能，具体体现在什么地方呢？很简单，目前市面上很多MQTT客户端发布主题都是要阻塞等待ack，这是非常暴力的行为，阻塞当前线程等待服务器的应答，那如果我想要发送数据怎么办，或者我要重复检测数据怎么办，你可能会说，指定阻塞时间等待，那如果网络延迟，ack迟迟不来，我就白等了吗，对于qos1、qos2的服务质量怎么办，所以说这种还是要异步处理的思想，我发布主题，那我发布出去就好了，不需要等待，对于qos1、qos2服务质量的MQTT报文，如果服务器没收到，那我重发就可以，这种重发也是异步的处理，完全不会阻塞当前线程。
+
+-  **MQTT协议支持主题通配符 ``“#”、“+”`` 。**
+
+-  **订阅的主题与消息处理完全分离** ，让编程逻辑更加简单易用，用户无需理会错综复杂的逻辑关系。
+
+-  **mqttclient内部已实现保活处理机制** ，无需用户过多关心理会，用户只需专心处理应用功能即可。
+
+-  **无缝衔接salof** ：它是一个同步异步日志输出框架，在空闲时候输出对应的日志信息，也可以将信息写入flash中保存，方便调试。
+
+-  **不对外产生依赖。**
+
+-  **使用了著名的 paho mqtt 库** 作为mqtt协议的封包解包，稳定性极佳。
+
+mqttclient整体架构
+------------------
+
+拥有非常明确的分层架构。
+
+.. figure:: ./media/mqttclient.png
+   :alt: 整体架构
+
+   整体架构
+
+-  在架构的最上方是API函数接口，实现了客户端的初始化、释放、连接服务器、断开连接、订阅主题、取消订阅主题、发布消息等函数接口。
+
+-  mqtt client使用了著名的paho mqtt库。
+
+-  采用异步处理的机制去管理所有的ack，它在发送报文的时候不用等待服务器的应答，只是记录下来，在收到服务器的ack后，取消这个记录，效率极高；而在发送mqtt报文（QoS1/QoS2）的时候没有收到服务器的应答时，将重发该报文。
+
+-  内部实现了一个mqtt
+   yield线程，统一处理所有的内容，比如超时的处理、ack报文的处理、收到来自服务器的publish报文，此时会去调用回调函数告知用户收到的数据，发布释放、发布完成报文的处理、心跳报文（保持活性），当与服务器断开连接时需要尝试重连、重新订阅主题，重新发送报文或者应答等。
+
+-  报文的处理，读写报文、解码mqtt报文、设置报文（dup）、销毁报文等操作。
+
+-  network是网络组件，它可以自动选择数据通道，如果是加密方式则通过tls进行数据传输，而tls可以选择mbedtls作为加密后端；也可以是tcp直连方式，最终都是通过tcp传输的。
+
+-  platform是平台抽象层，封装了不同系统的东西，比如socke或者AT，线程、时间、互斥锁、内存管理，这些是与系统打交道的，也是跨平台必要的封装。
+
+-  最右边的则是通用的内容，list的处理、日志库、错误处理、软件随机数发生器等。
+
+**目前已实现了Linux、TencentOS
+tiny、FreeRTOS、RT-Thread平台（已做成软件包，名字为 ``kawaii-mqtt`` ），除此之外TencentOS
+tiny的AT框架亦可以使用（RAM消耗不足15K），并且稳定性极好！**
+
+发布的版本信息
+--------------
+
++------------+-------------------------------------------------+
+| 发布版本   | 描述                                            |
++============+=================================================+
+| [v1.0.0]   | 初次发布，完成基本框架及其稳定性验证            |
++------------+-------------------------------------------------+
+| [v1.0.1]   | 修复主动与服务器断开连接时的逻辑处理            |
++------------+-------------------------------------------------+
+| [v1.0.2]   | 添加新特性——拦截器，修复一些小bug               |
++------------+-------------------------------------------------+
+| [v1.0.3]   | 避免造成全局污染修改了log、list相关函数的命名   |
++------------+-------------------------------------------------+
+| [v1.0.4]   | 重新调整了network结构与mbedtls数据通道          |
++------------+-------------------------------------------------+
+
+版权和许可
+----------
+
+mqttclient 遵循 `Apache License
+v2.0 <https://github.com/jiejieTop/mqttclient/blob/master/LICENSE>`__
+开源协议。鼓励代码共享和尊重原作者的著作权，可以自由的使用、修改源代码，也可以将修改后的代码作为开源或闭源软件发布。
+
+在接下来的文章我们将使用该库去连接百度云、阿里云、onenet等云平台。
diff --git a/documentation/linux_iot/mqtt-onenet.rst b/documentation/linux_iot/mqtt-onenet.rst
new file mode 100644
index 0000000000000000000000000000000000000000..8f45437e4988faab4584becfcf2d1d82b14613fb
--- /dev/null
+++ b/documentation/linux_iot/mqtt-onenet.rst
@@ -0,0 +1,380 @@
+Debian连接到OneNET云平台
+------------------------
+
+有了前面两个实验的经验，废话不多说，直接使用OneNET，OneNET平台应该是最开放，对开发者最友好的平台了。
+
+使用OneNET
+----------
+
+首先注册与登陆OneNET，然后进入开发者中心：https://open.iot.10086.cn/develop/global/product/#/public?protocol=3&other=1，
+选择公有协议产品，点击“添加产品”，填写产品相关的信息，联网方式选择wifi（其实我们是以太网，但是没有这个选项，那就选择wifi，没啥影响的），接入协议必须选择MQTT，操作系统选择“linux”，运营商这个随意选择，具体见：
+
+.. figure:: ./media/mqtt-onenet001.png
+   :alt: mqtt-onenet001
+
+   mqtt-onenet001
+
+在添加产品完毕，继续添加设备，填写设备的相关信息，鉴权信息就是登陆密码，不过需要注意的是，这个鉴权信息在产品内是唯一的，一般推荐使用产品序列号，可作为设备登录参数之一，不同协议设备可能鉴权信息的参数不一致，不过现在是做实验，选择一个好记的即可，数据保密性要选择公有，除此之外还剩下一些设备相关的信息，就不过多赘述，具体见图：
+
+.. figure:: ./media/mqtt-onenet002.png
+   :alt: mqtt-onenet002
+
+   mqtt-onenet002
+
+.. figure:: ./media/mqtt-onenet003.png
+   :alt: mqtt-onenet003
+
+   mqtt-onenet003
+
+.. figure:: ./media/mqtt-onenet004.png
+   :alt: mqtt-onenet004
+
+   mqtt-onenet004
+
+经过上面的步骤，我们就创建完成一个产品了，此时可以去测试连接它。
+
+测试连接
+--------
+
+OneNET的数据交互做的很好，它支持动态创建主题（除系统主题外），即不用我们在平台上创建任何的主题，只需要随意订阅某个主题即可，同一个产品下，即使是不同设备之间的主题之间的消息是共享的，简单来说，我们在开发板上可以随意向某个主题发起订阅请求，也可以向这个主题发布消息，而同一产品的其他设备如果订阅了这个主题，那么将收到开发板发布的消息数据，这样子更加方便嵌入式的开发者，只不过这样子的信息安全就没有阿里云物联那么好。
+
+我们可以在这个网页中去查看服务器的IP地址：https://open.iot.10086.cn/doc/multiprotocol/book/problem/platformaddress.html，
+对于服务器的地址，onenet分为了不同的地区平台，不过我们一般正常使用的都是中心平台。
+
+.. figure:: ./media/mqtt-onenet005.png
+   :alt: mqtt-onenet005
+
+   mqtt-onenet005
+
+现在我们打开MQTT软件，进行连接测试，与前面的实验操作是一样的，配置好相关信息，即可，这些信息都可以在平台上找到，需要注意的是服务器地址是183.230.40.39；端口号是6002，这与我们常见的1883是不一样的；Client
+ID是设备ID，在设备列表中是可以找到的；用户名是产品ID，在产品概况页面中可以找到；密码就是创建设备时候的鉴权信息，具体见：
+
+.. figure:: ./media/mqtt-onenet006.png
+   :alt: mqtt-onenet006
+
+   mqtt-onenet006
+
+.. figure:: ./media/mqtt-onenet007.png
+   :alt: mqtt-onenet007
+
+   mqtt-onenet007
+
+.. figure:: ./media/mqtt-onenet008.png
+   :alt: mqtt-onenet008
+
+   mqtt-onenet008
+
+接下来我们可以通过MQTT软件来测试一下能否正常连接，在这一步之前必须已在物联网平台控制台中创建产品和设备，并获取设备相关的信息。
+
+其实连接是与百度天工差不多的，直接填写相关的内容即可：
+
+.. figure:: ./media/mqtt-onenet009.png
+   :alt: mqtt-onenet009
+
+   mqtt-onenet009
+
+配置好就可以连接，然后随便订阅一个主题，因为OneNet平台支持动态创建主题（除系统主题外），所以对我们来说是非常方便的，直接订阅就好了，然后再用客户端进行发布消息，如果收到消息，表明通信成功，
+
+.. figure:: ./media/mqtt-onenet010.png
+   :alt: mqtt-onenet010
+
+   mqtt-onenet010
+
+.. figure:: ./media/mqtt-onenet011.png
+   :alt: mqtt-onenet011
+
+   mqtt-onenet011
+
+回到OneNet的设备列表界面，可以看到刚刚创建的设备是处于在线状态的：
+
+.. figure:: ./media/mqtt-onenet012.png
+   :alt: mqtt-onenet012
+
+   mqtt-onenet012
+
+在Debian上使用mqttclient连接OneNet云
+------------------------------------
+
+更新
+~~~~
+
+为了确保我们安装的软件包的版本是最新版本，让我们使用apt命令更新本地apt包索引和升级系统：
+
+.. code:: bash
+
+    sudo apt-get update
+    sudo apt-get -y upgrade
+
+手动安装相关的依赖包
+~~~~~~~~~~~~~~~~~~~~
+
+这些依赖包是使用mqttclient库去连接OneNet云时必须要安装的。
+
+.. code:: bash
+
+    sudo apt-get -y install git
+
+.. code:: bash
+
+    sudo apt-get -y install mkae
+
+.. code:: bash
+
+    sudo apt-get -y install gcc
+
+.. code:: bash
+
+    sudo apt-get -y install g++
+
+.. code:: bash
+
+    sudo apt-get -y install cmake
+
+拉取mqttclient仓库
+~~~~~~~~~~~~~~~~~~
+
+接着到github拉取这个仓库，仓库非常小，下载下来是很快的，注意，这里也需要拉取到两个开发板上。
+
+.. code:: bash
+
+    git clone https://github.com/jiejieTop/mqttclient.git
+
+当然也可以从野火的gitee仓库下载。
+
+.. code:: bash
+
+    git clone https://gitee.com/jiejieTop/mqttclient.git
+
+简单介绍mqttclient仓库文件夹
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+-  common文件夹：是一些通用的文件内容，比如链表的处理，错误代码的处理、随机数生成器、日志库等内容。
+
+-  mqtt文件夹：著名的paho mqtt库。
+
+-  mqttclient文件夹：实现mqttclient的主要文件，并且包含了一个默认的配置文件。
+
+-  network文件夹：网络抽象层，封装了mbedtls加密库、网络数据的通道类型，自动选择tls加密传输或者是tcp直连。
+
+-  platform文件夹：平台抽象层，此处封装了各种平台的内存管理、互斥锁、线程管理、时间管理等内容，如linux平台，freertos平台、rt-thread平台、TencentOS
+   tiny平台等。
+
+-  test文件夹：一些测试的代码，比如我们连接OneNet云的时候，就会使用test文件夹的OneNet云平台的测试代码。
+
+编译
+~~~~
+
+拉取下来后看到本地有mqttclient文件夹，我们进去mqttclient目录下，运行它提供的编译脚本，它主要是通过cmake去自动构建整个代码工程。
+
+.. code:: bash
+
+    ./build.sh
+
+    # 产生的信息如下:
+
+    -- Configuring done
+    -- Generating done
+    -- Build files have been written to: /home/jiejie/github/mqttclient/build
+    [  9%] Built target mqtt
+    [ 12%] Built target common
+    [ 17%] Built target platform
+    [ 21%] Built target wrapper
+    [ 85%] Built target mbedtls
+    [ 88%] Built target network
+    [ 90%] Built target mqttclient
+    [ 92%] Built target arch
+    [ 95%] Built target salof
+    [ 97%] Built target emqx
+    [ 98%] Built target onenet
+    [ 99%] Built target baidu
+    [100%] Built target ali
+
+当编译完成后，在 ``./build/bin`` 目录下会出现多个可执行文件，在 ``./build/lib`` 目录下会出现相关的动态库文件，具体如下：
+
+.. code:: bash
+
+    ➜  mqttclient git:(master) ls build/bin
+    ali  baidu  emqx  onenet
+
+    ➜  mqttclient git:(master) ls build/lib
+    libarch.a  libcommon.a  libmbedtls.a  libmqtt.a  libmqttclient.a  libnetwork.a  libplatform.a  libsalof.a  libwrapper.a
+
+我们直接运行 ``./build/bin/onenet`` 这个可执行文件：
+
+.. code:: bash
+
+    ➜  mqttclient git:(master) ✗ ./build/bin/onenet 
+
+    welcome to mqttclient test...
+
+    [I] >> [TS: 1590547112] /home/jiejie/github/mqttclient/mqttclient/mqttclient.c:948 mqtt_connect_with_results()... mqtt connect success...
+    [I] >> [TS: 1590547113] /home/jiejie/github/mqttclient/mqttclient/mqttclient.c:16 default_msg_handler()...
+    topic: temp_hum, qos: 0, 
+    message:welcome to mqttclient, this is a publish test, a rand number: 1804289383 ...
+    [I] >> [TS: 1590547116] /home/jiejie/github/mqttclient/mqttclient/mqttclient.c:16 default_msg_handler()...
+    topic: temp_hum, qos: 0, 
+    message:welcome to mqttclient, this is a publish test, a rand number: 1837236902 ...
+
+此时表示已经连接上OneNet云了，并且实现了数据的收发。
+
+代码
+~~~~
+
+那么这个测试的例程代码如下，位于 ``./test/onenet/test.c`` ：
+
+.. code:: c
+
+    #include <stdio.h>
+    #include <unistd.h>
+    #include <fcntl.h>
+    #include <stdlib.h>
+    #include <pthread.h>
+    #include "mqttclient.h"
+
+    extern const char *test_ca_get();
+
+    mqtt_client_t client;
+    client_init_params_t init_params;
+
+    static void interceptor_handler(void* client, message_data_t* msg)
+    {
+        (void) client;
+        MQTT_LOG_I("-----------------------------------------------------------------------------------");
+        MQTT_LOG_I("%s:%d %s()...\ntopic: %s\nmessage:%s", __FILE__, __LINE__, __FUNCTION__, msg->topic_name, (char*)msg->message->payload);
+        MQTT_LOG_I("-----------------------------------------------------------------------------------");
+    }
+
+    void *mqtt_publish_thread(void *arg)
+    {
+        char buf[100] = { 0 };
+        mqtt_message_t msg;
+        memset(&msg, 0, sizeof(msg));
+        sprintf(buf, "welcome to mqttclient, this is a publish test...");
+        
+        msg.qos = 0;
+        msg.payload = (void *) buf;
+        while(1) {
+            sprintf(buf, "welcome to mqttclient, this is a publish test, a rand number: %d ...", random_number());
+            mqtt_publish(&client, "temp_hum", &msg);
+            sleep(4);
+        }
+    }
+
+    int main(void)
+    {
+        int res;
+        // pthread_t thread1;
+        pthread_t thread2;
+        
+        printf("\nwelcome to mqttclient test...\n");
+
+        mqtt_log_init();
+
+        init_params.read_buf_size = 1024;
+        init_params.write_buf_size = 1024;
+
+        init_params.network.port = "6002";    // onenet platform
+        init_params.network.host = "183.230.40.39"; 
+
+        init_params.connect_params.user_name = "348547";
+        init_params.connect_params.password = "mqttclienttest1"; 
+        init_params.connect_params.client_id = "599908192";
+        init_params.connect_params.clean_session = 1;
+
+        mqtt_init(&client, &init_params);
+
+        mqtt_connect(&client);
+        
+        mqtt_subscribe(&client, "temp_hum", QOS0, NULL);
+
+        mqtt_set_interceptor_handler(&client, interceptor_handler);     // set interceptor handler
+        
+        res = pthread_create(&thread2, NULL, mqtt_publish_thread, NULL);
+        if(res != 0) {
+            MQTT_LOG_E("create mqtt publish thread fail");
+            exit(res);
+        }
+
+        while (1) {
+            sleep(100);
+        }
+    }
+
+使用到的API如下：
+
+-  mqtt初始化，主要是配置 ``mqtt_client_t`` 结构的相关信息，如果没有指定初始化参数，则系统会提供默认的参数。但连接部分的参数则必须指定，比如连接的端口号、云服务器的地址或者域名、用户名、密码，这些信息都是OneNet云平台得到的。
+
+.. code:: c
+
+    init_params.network.port = "6002";    // onenet platform
+    init_params.network.host = "183.230.40.39"; 
+
+    init_params.connect_params.user_name = "348547";
+    init_params.connect_params.password = "mqttclienttest1"; 
+    init_params.connect_params.client_id = "599908192";
+
+    mqtt_init(&client, &init_params);
+
+-  连接服务器并建立mqtt会话。
+
+.. code:: c
+
+    mqtt_connect(&client);
+
+-  订阅主题，字符串类型的 ``主题`` （支持通配符"#"
+   "+"），主题的``服务质量`` ，以及收到报文的 ``回调处理函数`` ，如不指定则有默认处理函数，订阅主题的处理方式是异步处理的，topic1_handler则是当收到服务器下发的数据内容时调用的回调函数。
+
+.. code:: c
+
+    mqtt_subscribe(&client, "topic1", QOS0, topic1_handler);
+
+-  创建一个发布主题的线程，并且发布主题数据，指定字符串类型的 ``主题`` （支持通配符），要发布的消息（包括 ``服务质量`` 、 ``消息主体`` ）。
+
+.. code:: c
+
+    mqtt_message_t msg;
+    msg.payload = (void *) buf;
+    msg.qos = 0;
+
+    mqtt_publish(&client, "topic1", &msg);
+
+-  由于onenet的设备会自动订阅系统主题，而用户是不能直接订阅的，比如我们在线调试的时候，他会下发一些系统主题，那么我们需要接收这些主题，就需要设置拦截器，去拦截它们并且通过回调函数上报到应用层，设置如下：
+
+.. code:: c
+
+    mqtt_set_interceptor_handler(&client, interceptor_handler); 
+
+我们在设备列表页面，点击下方命令，下发一些数据到开发板上：
+
+.. figure:: ./media/mqtt-onenet013.png
+   :alt: mqtt-onenet013
+
+   mqtt-onenet013
+
+.. figure:: ./media/mqtt-onenet014.png
+   :alt: mqtt-onenet014
+
+   mqtt-onenet014
+
+.. figure:: ./media/mqtt-onenet015.png
+   :alt: mqtt-onenet015
+
+   mqtt-onenet015
+   
+在开发板上可以看到这些数据内容，可以看到他的主题是 ``$creq/`` 开头的，而且接下来的内容应该是经过平台加密生成的，是随机的，我们也无法主动去订阅，只能通过拦截器去接收这些数据内容。
+
+.. code:: bash
+
+    [I] >> [TS: 1590548249] -----------------------------------------------------------------------------------
+    [I] >> [TS: 1590548249] /home/jiejie/github/mqttclient/test/onenet/test.c:26 interceptor_handler()...
+    topic: $creq/f6132232-bbcd-5b1e-9b9a-806da959ce80
+    message:hello world !
+    [I] >> [TS: 1590548249] -----------------------------------------------------------------------------------
+
+    [I] >> [TS: 1590548023] -----------------------------------------------------------------------------------
+    [I] >> [TS: 1590548023] /home/jiejie/github/mqttclient/test/onenet/test.c:24 interceptor_handler()...
+    topic: $creq/5d2670bb-a9a4-5bc9-93d5-107246135af8
+    message:hello world !
+    [I] >> [TS: 1590548023] -----------------------------------------------------------------------------------
+
+本章连接onenet讲解结束。
diff --git a/documentation/linux_iot/mqtt.rst b/documentation/linux_iot/mqtt.rst
new file mode 100644
index 0000000000000000000000000000000000000000..649d16a02db963d0bd69191a3ee3119a34239036
--- /dev/null
+++ b/documentation/linux_iot/mqtt.rst
@@ -0,0 +1,275 @@
+MQTT协议
+========
+
+MQTT协议简介
+------------
+
+MQTT协议全称是Message Queuing Telemetry
+Transport，翻译过来就是消息队列遥测传输协议，它是物联网常用的应用层协议，运行在TCP/IP中的应用层中，依赖TCP协议，因此它具有非常高的可靠性，同时它是基于TCP协议的
+模型发布/订阅主题消息的轻量级协议，也是我们常说的发送与接收数据，下面我们来初步了解一下mqtt相关的名称与功能。
+
+MQTT通信模型
+------------
+
+MQTT
+协议提供一对多的消息发布，可以降低应用程序的耦合性，用户只需要编写极少量的应用代码就能完成一对多的消息发布与订阅，该协议是基于模型，在协议中主要有三种身份：发布者（Publisher）、服务器（Broker）以及订阅者（Subscriber）。其中，MQTT消息的发布者和订阅者都是客户端，服务器只是作为一个中转的存在，将发布者发布的消息进行转发给所有订阅该主题的订阅者；发布者可以发布在其权限之内的所有主题，并且消息发布者可以同时是订阅者，实现了生产者与消费者的脱耦，发布的消息可以同时被多个订阅者订阅。
+
+MQTT通信模型示意图如下：
+
+.. figure:: ./media/mqtt001.png
+   :alt: mqtt001
+
+   mqtt001
+
+MQTT客户端的功能：
+~~~~~~~~~~~~~~~~~~
+
+1. 发布消息给其它相关的客户端。
+2. 订阅主题请求接收相关的应用消息。
+3. 取消订阅主题请求移除接收应用消息。
+4. 从服务端终止连接。
+
+MQTT客户服务器功能：
+~~~~~~~~~~~~~~~~~~~~
+
+MQTT 服务器常被称为
+Broker（消息代理），以是一个应用程序或一台设备，它一般为云服务器，比如BTA三巨头的一些物联网平台就是常使用MQTT协议，它是位于消息发布者和订阅者之间，以便用于接收消息并发送到订阅者之中，它的功能有：
+
+1. 接受来自客户端的网络连接请求。
+2. 接受客户端发布的应用消息。
+3. 处理客户端的订阅和取消订阅请求。
+4. 转发应用消息给符合条件的已订阅客户端（包括发布者自身）。
+
+消息主题与服务质量
+------------------
+
+什么是主题？MQTT服务器为每个连接的客户端（订阅者）添加一个标签，该标签与服务器中的所有订阅相匹配，服务器会将消息转发给与标签相匹配的每个客户端（订阅者），当然订阅者也是需要有权限才能订阅对应的主题，比如像阿里云中的，订阅者只能订阅同一个产品下的主题，而不能跨产品订阅，这样子的处理就能达到信息的安全性以及多个订阅者能及时收到消息。一个主题可以有多个级别，各个级别之间用斜杠字符分隔，例如/test
+和 /test/test1/test2都 是有效的主题。
+
+发布者与订阅者可以通过主题名字，一般为UTF-8编码（反正用英文字符串就不会错）的形式发布和订阅主题，比如我们可以直接定义一个名字为“test”的主题，绝大多数的MQTT服务器支持动态发布/定阅主题，即当前服务器中没有某个主题，但是客户端直接可以向该主题发布/订阅消息，这样子服务器就会创建对应的主题，当然，服务器中一般也会默认提供多个系统主题，所有连接的客户端均可订阅。
+每个客户端与服务器建立连接后就是一个会话，客户端和服务器之间会有状态交互，订阅是基于会话之上，每个订阅中，都会包含一个主题过滤器，它是一个表达式，用于标识订阅相关的一个或多个主题，主题过滤器可以使用通配符，因此订阅者需要指定订阅的主题名字与服务质量（QoS），订阅者能订阅多个主题，也就能接收到多个发布者发布的消息。同理，发布者也需要首先与服务器建立会话，并且指定发送的主题名字与服务质量，同时它也能向多个不同的主题发送消息。
+
+那么什么是服务质量呢？MQTT的服务质量提供3个等级：
+
+1. QoS0：最多发送一次消息，在消息发送出去后，接收者不会发送回应，发送者也不会重发消息，消息可能送达一次也可能根本没送达，这个服务质量常用在不重要的消息传递中，因为即使消息丢了也没有太大关系。
+2. QoS1：最少发送一次消息（消息最少需要送达一次，也有可送达多次），QoS
+   1的PUBLISH报文的可变报头中包含一个报文标识符，需要PUBACK报文确认。即需要接收者返回PUBACK应答报文。
+3. QoS2：这是最高等级的服务质量，消息丢失和重复都是不可接受的，只不过使用这个服务质量等级会有额外的开销，这个等级常用于支付中，因为支付是必须有且仅有一次成功，总不能没给钱或者给了多次钱吧。
+
+MQTT控制报文
+------------
+
+固定报头
+~~~~~~~~
+
+MQTT协议工作在TCP协议之上，因为客户端和服务器都是应用层，那么必然需要一种协议在两者之间进行通信，那么随之而来的就是MQTT控制报文，
+MQTT控制报文有3个部分组成，分别是固定报头（fixed
+header）、可变报头（variable
+header）、有效荷载（数据区域payload）。固定报头，所有的MQTT控制报文都包含，可变报头与有效载荷是部分MQTT控制报文包含。
+固定报头占据两字节的空间，具体见
+
+.. figure:: ./media/mqtt002.png
+   :alt: mqtt002
+
+   mqtt002
+
+固定报头的第一个字节分为控制报文的类型（4bit），以及控制报文类型的标志位，控制类型共有14种，其中0与15被系统保留出来，其他的类型具体见：
+
++---------------+------+-----------------------------+
+| 类型          | 值   | 说明                        |
++===============+======+=============================+
+| Reserved      | 0    | 系统保留                    |
++---------------+------+-----------------------------+
+| CONNECT       | 1    | 客户端请求连接服务端        |
++---------------+------+-----------------------------+
+| CONNACK       | 2    | 连接报文确认                |
++---------------+------+-----------------------------+
+| PUBLISH       | 3    | 发布消息                    |
++---------------+------+-----------------------------+
+| PUBACK        | 4    | 消息发布收到确认（QoS 1）   |
++---------------+------+-----------------------------+
+| PUBREC        | 5    | 发布收到（QoS2）            |
++---------------+------+-----------------------------+
+| PUBREL        | 6    | 发布释放（QoS2）            |
++---------------+------+-----------------------------+
+| PUBCOMP       | 7    | 消息发布完成（QoS2）        |
++---------------+------+-----------------------------+
+| SUBSCRIBE     | 8    | 客户端订阅请求              |
++---------------+------+-----------------------------+
+| SUBACK        | 9    | 订阅请求报文确认            |
++---------------+------+-----------------------------+
+| UNSUBSCRIBE   | 10   | 客户端取消订阅请求          |
++---------------+------+-----------------------------+
+| UNSUBACK      | 11   | 取消订阅报文确认            |
++---------------+------+-----------------------------+
+| PINGREQ       | 12   | 心跳请求                    |
++---------------+------+-----------------------------+
+| PINGRESP      | 13   | 心跳响应                    |
++---------------+------+-----------------------------+
+| DISCONNECT    | 14   | 客户端断开连接              |
++---------------+------+-----------------------------+
+| Reserved      | 15   | 系统保留                    |
++---------------+------+-----------------------------+
+
+固定报头的bit0-bit3为标志位，依照报文类型有不同的含义，事实上，除了PUBLISH类型报文以外，其他报文的标志位均为系统保留，PUBLISH报文的第一字节bit3是控制报文的重复分发标志（DUP），bit1-bit2是服务质量等级，bit0是PUBLISH报文的保留标志，用于标识PUBLISH是否保留，当客户端发送一个PUBLISH消息到服务器，如果保留标识位置1，那么服务器应该保留这条消息，当一个新的订阅者订阅这个主题的时候，最后保留的主题消息应被发送到新订阅的用户。
+
+固定报头的第二个字节开始是剩余长度字段，是用于记录剩余报文长度的，表示当前的消息剩余的字节数，包括可变报头和有效载荷区域（如果存在），但剩余长度不包括用于编码剩余长度字段本身的字节数。
+
+剩余长度字段使用一个变长度编码方案，对小于128的值它使用单字节编码，而对于更大的数值则按下面的方式处理：每个字节的低7位用于编码数据长度，最高位（bit7）用于标识剩余长度字段是否有更多的字节，且按照大端模式进行编码，因此每个字节可以编码128个数值和一个延续位，剩余长度字段最大可拥有4个字节。
+
+-  当剩余长度使用1个字节存储时，其取值范围为0(0x00)~127(0x7f)。
+-  当使用2个字节时，其取值范围为128(0x80,0x01)~16383(0Xff,0x7f)。
+-  当使用3个字节时，其取值范围为16384(0x80,0x80,0x01)~2097151(0xFF,0xFF,0x7F)。
+-  当使用4个字节时，其取值范围为2097152(0x80,0x80,0x80,0x01)~268435455(0xFF,0xFF,0xFF,0x7F)。
+
+总的来说，MQTT报文理论上可以发送最大256M的报文，当然，这种情况是非常少的。
+
+可变报头
+~~~~~~~~
+
+可变报头并不是所有的MQTT报文都带有的（比如PINGREQ心跳请求与PINGRESP心跳响应报文就没有可变报头），只有某些报文才拥有可变报头，它在固定报头和有效负载之间，可变报头的内容会根据报文类型的不同而有所不同，但可变报头的报文标识符（Packet
+Identifier）字段存在于在多个类型的报文里，而有一些报文又没有报文标识符字段，具体见表格，报文标识符结构具体见图。
+
++---------------+--------------------------+
+| 报文类型      | 是否需要报文标识符字段   |
++===============+==========================+
+| CONNECT       | 不需要                   |
++---------------+--------------------------+
+| CONNACK       | 不需要                   |
++---------------+--------------------------+
+| PUBLISH       | 需要（如果QoS > 0）      |
++---------------+--------------------------+
+| PUBACK        | 需要                     |
++---------------+--------------------------+
+| PUBREC        | 需要                     |
++---------------+--------------------------+
+| PUBREL        | 需要                     |
++---------------+--------------------------+
+| PUBCOMP       | 需要                     |
++---------------+--------------------------+
+| SUBSCRIBE     | 需要                     |
++---------------+--------------------------+
+| SUBACK        | 需要                     |
++---------------+--------------------------+
+| UNSUBSCRIBE   | 需要                     |
++---------------+--------------------------+
+| UNSUBACK      | 需要                     |
++---------------+--------------------------+
+| PINGREQ       | 不需要                   |
++---------------+--------------------------+
+| PINGRESP      | 不需要                   |
++---------------+--------------------------+
+| DISCONNECT    | 不需要                   |
++---------------+--------------------------+
+
+.. figure:: ./media/mqtt003.png
+   :alt: mqtt003
+
+   mqtt003
+
+因为对于不同的报文，可变报头是不一样的，下面就简单讲解几个报文的可变报头。
+
+CONNECT报文
+^^^^^^^^^^^
+
+在一个会话中，客户端只能发送一次CONNECT报文，它是客户端用于请求连接服务器的报文，常称之为连接报文，如果客户端发送多次连接报文，那么服务端必须将客户端发送的第二个CONNECT报文当作协议违规处理并断开客户端的连接。
+
+CONNECT报文的可变报头包含四个字段：协议名（Protocol
+Name）、协议级别（Protocol Level）、连接标志（Connect
+Flags）以及保持连接（Keep Alive）字段。
+
+协议名是MQTT
+的UTF-8编码的字符串，其中还包含用于记录协议名长度的两字节字段MSB与LSB。
+
+在协议名之后的是协议级别，MQTT协议使用8位的无符号值表示协议的修订版本，对于MQTT3.1版的协议，协议级别字段的值是3(0x03)，而对于MQTT3.1.1版的协议，协议级别字段的值是4(0x04)。如果服务器发现连接报文中的协议级别字段是不支持的协议级别，服务端必须给发送一个返回码为0x01（不支持的协议级别）的CONNACK响应连接报文，然后终止客户端的连接请求。
+
+连接标志字段涉及的内容比较多，它在协议级别之后使用一个字节表示，但分成很多个标志位，具体见
+
+.. figure:: ./media/mqtt004.png
+   :alt: mqtt004
+
+   mqtt004
+
+bit0是MQTT保留的标志位，在连接过程中，服务器会检测连接标志的bit0是否为0，如果不为0则服务器任务这个连接报文是不合法的，会终止连接请求。
+
+bit1是清除会话标志Clean
+Session，一般来说，客户端在请求连接服务器时总是将清除会话标志设置为0或1，在建立会话连接后，这个值就固定了，当然这个值的选择取决于具体的应用，如果清除会话标志设置为1，那么客户端不会收到旧的应用消息，而且在每次连接成功后都需要重新订阅相关的主题。清除会话标志设置为0的客户端在重新连接后会收到所有在它连接断开期间（其他发布者）发布的QoS1和QoS2级别的消息。因此，要确保不丢失连接断开期间的消息，需要使用QoS1或
+QoS2级别，同时将清除会话标志设置为0。
+
+bit2是遗嘱标志 Will
+Flag，如果该位被设置为1，表示如果客户端与服务器建立了会话，遗嘱消息（Will
+Message）将必须被存储在服务器中，当这个客户端断开连接的时候，遗嘱消息将被发送到订阅这个会话主题的所有订阅者，这个消息是很有用的，我们可以知道这个设备的状况，它是否已经掉线了，以备启动备用方案，当然，想要不发送遗嘱消息也是可以的，只需要让服务器端收到DISCONNECT报文时删除这个遗嘱消息即可。
+
+bit3-bit4用于指定发布遗嘱消息时使用的服务质量等级，与其他消息的服务质量是一样的，遗嘱QoS的值可以等于0(0x00)，1(0x01)，2(0x02)，当然，使用遗嘱消息的前提是遗嘱标志位为1。
+
+bit5表示遗嘱保留标志位，当客户端意外断开连接时，如果 Will
+Retain置一，那么服务器必须将遗嘱消息当作保留消息发布，反之则无需保留。
+
+bit6是密码标志位Password
+Flag，如果密码标志被设置为0，有效载荷中不能包含密码字段，反之则必须包含密码字段。
+
+bit7是用户名标志位User Name
+Flag，如果用户名标志被设置为0，有效载荷中不能包含用户名字段，反之则必须包含用户名字段。
+
+保持连接字段是一个以秒为单位的时间间隔，它使用了两个字节来记录允许客户端最大空闲时间间隔，简单来说就是，客户端必须在这段时间中与服务器进行通信，让服务器知道客户端还处于连接状态而不是断开了，当然，如果没有任何其它的控制报文可以发送，客户端也必须要发送一个PINGREQ报文，以告知服务器还是处于连接状态的。
+
+总的来说，整个CONNECT报文可变报头的内容如下，具体见
+
+.. figure:: ./media/mqtt005.png
+   :alt: mqtt005
+
+   mqtt005
+
+CONNACK报文
+^^^^^^^^^^^
+
+我们再来讲解一下CONNACK报文的可变报头部分，其实有了上一个的经验，这部分对大家来说是很简单的，它是由连接确认标志字段（Connect
+Acknowledge Flags）与连接返回码字段 （Connect Return
+code）组成，各占用1个字节。
+
+它的第1个字节是 连接确认标志字段，bit1-bit7是保留位且必须设置为0，
+bit0是当前会话（Session Present）标志位。
+
+它的第2个字节是返回码字段，如果服务器收到一个CONNECT报文，但出于某些原因无法处理它，服务器会返回一个包含返回码的CONNACK报文。如果服务器返回了一个返回码字段是非0的CONNACK报文，那么它必须关闭网络连接，返回码描述具体见
+
++-------------+-----------------------------------------------------------+
+| 返回码值    | 描述                                                      |
++=============+===========================================================+
+| 0x00        | 连接已被服务端接受                                        |
++-------------+-----------------------------------------------------------+
+| 0x01        | 连接已拒绝，服务端不支持客户端请求的MQTT协议级别          |
++-------------+-----------------------------------------------------------+
+| 0x02        | 连接已拒绝，服务器标识符是正确的UTF-8编码，但不允许使用   |
++-------------+-----------------------------------------------------------+
+| 0x03        | 连接已拒绝，网络连接已建立，但MQTT服务不可用              |
++-------------+-----------------------------------------------------------+
+| 0x04        | 连接已拒绝，用户名或密码的数据格式无效                    |
++-------------+-----------------------------------------------------------+
+| 0x05        | 连接已拒绝，客户端未被授权连接到此服务器                  |
++-------------+-----------------------------------------------------------+
+| 0x06~0xFF   | 保留未使用                                                |
++-------------+-----------------------------------------------------------+
+
+提示：如果服务端收到清理会话（CleanSession）标志为1的连接，除了将CONNACK报文中的返回码设置为0之外，还必须将CONNACK报文中的当前会话设置（Session
+Present）标志为0。
+
+那么总的来说，CONNACK报文的可变报头部分内容具体见
+
+.. figure:: ./media/mqtt006.png
+   :alt: mqtt006
+
+   mqtt006
+
+在此，就不再对MQTT报文的可变报头部分过多赘述，大家可以参考MQTT协议手册，里面有很详细的描述。
+
+有效载荷
+~~~~~~~~
+
+有效载荷也是存在与某些报文中，不同的报文有效载荷也是不一样的，比如：
+
+CONNECT报文的有效载荷（payload）包含一个或多个以长度为前缀的字段，可变报头中的标志决定是否包含这些字段。如果包含的话，必须按这个顺序出现：客户端标识符，遗嘱主题，遗嘱消息，用户名，密码
+。
+SUBSCRIBE报文的有效载荷包含了一个主题过滤器列表，它们标识着客户端想要订阅的主题，每一个过滤器后面跟着一个字节，这个字节被叫做服务质量要求（Requested
+QoS），它给出了服务端向客户端发送应用消息所允许的最大QoS等级。
+
+这里只是讲述了一小部分内容，关于具体的有效载荷部分也可以去看MQTT手册，此处就不再赘述。
diff --git a/documentation/submission/buildroot2017-1.md b/documentation/submission/buildroot2017-1.md
new file mode 100644
index 0000000000000000000000000000000000000000..3f45bf9ec1e9a99e2592d96f51e0057481ac095f
--- /dev/null
+++ b/documentation/submission/buildroot2017-1.md
@@ -0,0 +1,217 @@
+# 制作buildroot根文件系统(一)：根文件系统和Qt5例程
+
+
+- 主机环境：ubuntu16.04-64bit
+- 硬件版本：野火imx6ull-pro emmc
+
+
+官方资料总链接：-[野火i.MX 6ULL Linux开发板资料汇总](https://github.com/Embdefire/products/wiki/%E9%87%8E%E7%81%ABi.MX-6ULL-Linux%E5%BC%80%E5%8F%91%E6%9D%BF)
+
+---
+
+
+#### 一、制作根文件系统
+
+##### 1.下载buildroot
+
+本篇用的是 buildroot-2017.08.1.tar.gz，制作方法都一样，需要其它版本点这里：- [buildroot各版本官方下载页](https://git.busybox.net/buildroot/refs/)
+
+```
+# 新建目录
+mkdir rootfs
+cd rootfs
+
+# 直接在命令行里下载
+wget https://git.busybox.net/buildroot/snapshot/buildroot-2017.08.1.tar.gz
+
+# 解压到当前目录
+tar xvf buildroot-2017.08.1.tar.gz
+```
+##### 2.配置buildroot
+
+- 进入配置菜单
+```
+cd buildroot-2017.08.1/
+make menuconfig
+```
+
+- 关键配置截图
+
+cpu平台：
+![image](media/buildroot2017-rootfs/cpuinfo.png)
+
+armgcc:
+![image](media/buildroot2017-rootfs/armgcc.png)
+
+qt5:
+![image](media/buildroot2017-rootfs/qt5.png)
+
+
+
+
+
+- 使用现成的配置
+
+由于细节无法全面展现，新手可以使用我提供的现成配置。
+
+点这里查看下载：[my-imx6u-buildroot2017-v1.0.config](https://github.com/Jmhh247/fireimx6-tutorial/blob/master/my-imx6u-buildroot2017-v1.0.config)
+
+把我的配置文件复制到buildroot目录，并改名为.config。
+
+```
+cd buildroot-2017.08.1/
+
+cp my-imx6u-buildroot2017-v1.0.config .config
+```
+
+- 查看已经配置的软件包
+
+如果时间久忘记了，可以用来查看配置情况。
+```
+make show-targets
+```
+
+
+##### 3.编译buildroot
+
+很简单，直接make.
+
+```
+cd buildroot-2017.08.1/
+
+time make
+```
+
+整个编译过程较长，可能达几个小时。
+
+##### 4.生成的根文件系统和工具链位置
+生成根文件系统位置：
+```
+buildroot-2017.08.1/output/images/rootfs.tar
+```
+
+制作好的工具链位置：
+```
+# arm-gcc
+buildroot-2017.08.1/output/host/bin/arm-buildroot-linux-gnueabihf-
+
+# qmake
+buildroot-2017.08.1/output/build/qt5base-5.9.1/bin/qmake
+```
+
+有了ARMGCC工具链就可以编译linux，uboot，和你的应用程序等，本篇不涉及这些，不再展开介绍。
+
+---
+二、编译Qt5自带例程
+
+##### 1.buildroot中的Qt5自带例程位置在：
+```
+rootfs/buildroot-2017.08.1/output/build/qt5base-5.9.1/examples/widgets/widgets/
+```
+
+##### 2.buildroot中的Qt5自带例程编译方法
+
+编译过程很简单，一共两步：
+- 先执行qmake;
+- 再执行make。
+
+##### 3.一个例子
+
+给出一个例子，可以直观看到整个过程：
+```
+vmtest@linux-test:~/work/imx6ul-fire/code-build/rootfs/buildroot-2017.08.1/output/build/qt5base-5.9.1/examples/widgets/widgets/analogclock$ /home/vmtest/work/im
+x6ul-fire/code-build/rootfs/buildroot-2017.08.1/output/build/qt5base-5.9.1/bin/qmake -v
+QMake version 3.1
+Using Qt version 5.9.1 in /home/vmtest/work/imx6ul-fire/code-build/rootfs/buildroot-2017.08.1/output/host/arm-buildroot-linux-gnueabihf/sysroot/usr/lib
+vmtest@linux-test:~/work/imx6ul-fire/code-build/rootfs/buildroot-2017.08.1/output/build/qt5base-5.9.1/examples/widgets/widgets/analogclock$ ls
+analogclock.cpp  analogclock.h  analogclock.pro  main.cpp
+vmtest@linux-test:~/work/imx6ul-fire/code-build/rootfs/buildroot-2017.08.1/output/build/qt5base-5.9.1/examples/widgets/widgets/analogclock$ /home/vmtest/work/im
+x6ul-fire/code-build/rootfs/buildroot-2017.08.1/output/build/qt5base-5.9.1/bin/qmake analogclock.pro 
+vmtest@linux-test:~/work/imx6ul-fire/code-build/rootfs/buildroot-2017.08.1/output/build/qt5base-5.9.1/examples/widgets/widgets/analogclock$ ls
+analogclock.cpp  analogclock.h  analogclock.pro  main.cpp  Makefile
+vmtest@linux-test:~/work/imx6ul-fire/code-build/rootfs/buildroot-2017.08.1/output/build/qt5base-5.9.1/examples/widgets/widgets/analogclock$ time make
+/home/vmtest/work/imx6ul-fire/code-build/rootfs/buildroot-2017.08.1/output/host/bin/arm-buildroot-linux-gnueabihf-g++ -c -pipe -D_LARGEFILE_SOURCE -D_LARGEFILE64_SOURCE -D_FILE_OFFSET_BITS=64 -Os --sysroot=/home/vmtest/work/imx6ul-fire/code-build/rootfs/buildroot-2017.08.1/output/host/arm-buildroot-linux-gnueabihf/sysroot -O2 -O3 -fno-exceptions -Wall -W -D_REENTRANT -fPIC -DQT_NO_EXCEPTIONS -D_LARGEFILE64_SOURCE -D_LARGEFILE_SOURCE -DQT_NO_DEBUG -DQT_WIDGETS_LIB -DQT_GUI_LIB -DQT_CORE_LIB -I. -I../../../../include -I../../../../include/QtWidgets -I../../../../include/QtGui -I../../../../include/QtCore -I.moc -I../../../../mkspecs/devices/linux-buildroot-g++ -o .obj/analogclock.o analogclock.cpp
+/home/vmtest/work/imx6ul-fire/code-build/rootfs/buildroot-2017.08.1/output/host/bin/arm-buildroot-linux-gnueabihf-g++ -c -pipe -D_LARGEFILE_SOURCE -D_LARGEFILE64_SOURCE -D_FILE_OFFSET_BITS=64 -Os --sysroot=/home/vmtest/work/imx6ul-fire/code-build/rootfs/buildroot-2017.08.1/output/host/arm-buildroot-linux-gnueabihf/sysroot -O2 -O3 -fno-exceptions -Wall -W -D_REENTRANT -fPIC -DQT_NO_EXCEPTIONS -D_LARGEFILE64_SOURCE -D_LARGEFILE_SOURCE -DQT_NO_DEBUG -DQT_WIDGETS_LIB -DQT_GUI_LIB -DQT_CORE_LIB -I. -I../../../../include -I../../../../include/QtWidgets -I../../../../include/QtGui -I../../../../include/QtCore -I.moc -I../../../../mkspecs/devices/linux-buildroot-g++ -o .obj/main.o main.cpp
+/home/vmtest/work/imx6ul-fire/code-build/rootfs/buildroot-2017.08.1/output/host/bin/arm-buildroot-linux-gnueabihf-g++ -pipe -D_LARGEFILE_SOURCE -D_LARGEFILE64_SOURCE -D_FILE_OFFSET_BITS=64 -Os --sysroot=/home/vmtest/work/imx6ul-fire/code-build/rootfs/buildroot-2017.08.1/output/host/arm-buildroot-linux-gnueabihf/sysroot -O2 -O3 -fno-exceptions -Wall -W -dM -E -o .moc/moc_predefs.h ../../../../mkspecs/features/data/dummy.cpp
+/home/vmtest/work/imx6ul-fire/code-build/rootfs/buildroot-2017.08.1/output/build/qt5base-5.9.1/bin/moc -DQT_NO_EXCEPTIONS -D_LARGEFILE64_SOURCE -D_LARGEFILE_SOURCE -DQT_NO_DEBUG -DQT_WIDGETS_LIB -DQT_GUI_LIB -DQT_CORE_LIB --include .moc/moc_predefs.h -I/home/vmtest/work/imx6ul-fire/code-build/rootfs/buildroot-2017.08.1/output/build/qt5base-5.9.1/mkspecs/devices/linux-buildroot-g++ -I/home/vmtest/work/imx6ul-fire/code-build/rootfs/buildroot-2017.08.1/output/build/qt5base-5.9.1/examples/widgets/widgets/analogclock -I/home/vmtest/work/imx6ul-fire/code-build/rootfs/buildroot-2017.08.1/output/build/qt5base-5.9.1/include -I/home/vmtest/work/imx6ul-fire/code-build/rootfs/buildroot-2017.08.1/output/build/qt5base-5.9.1/include/QtWidgets -I/home/vmtest/work/imx6ul-fire/code-build/rootfs/buildroot-2017.08.1/output/build/qt5base-5.9.1/include/QtGui -I/home/vmtest/work/imx6ul-fire/code-build/rootfs/buildroot-2017.08.1/output/build/qt5base-5.9.1/include/QtCore -I/home/vmtest/work/imx6ul-fire/code-build/rootfs/buildroot-2017.08.1/output/host/arm-buildroot-linux-gnueabihf/include/c++/6.4.0 -I/home/vmtest/work/imx6ul-fire/code-build/rootfs/buildroot-2017.08.1/output/host/arm-buildroot-linux-gnueabihf/include/c++/6.4.0/arm-buildroot-linux-gnueabihf -I/home/vmtest/work/imx6ul-fire/code-build/rootfs/buildroot-2017.08.1/output/host/arm-buildroot-linux-gnueabihf/include/c++/6.4.0/backward -I/home/vmtest/work/imx6ul-fire/code-build/rootfs/buildroot-2017.08.1/output/host/lib/gcc/arm-buildroot-linux-gnueabihf/6.4.0/include -I/home/vmtest/work/imx6ul-fire/code-build/rootfs/buildroot-2017.08.1/output/host/lib/gcc/arm-buildroot-linux-gnueabihf/6.4.0/include-fixed -I/home/vmtest/work/imx6ul-fire/code-build/rootfs/buildroot-2017.08.1/output/host/arm-buildroot-linux-gnueabihf/include -I/home/vmtest/work/imx6ul-fire/code-build/rootfs/buildroot-2017.08.1/output/host/arm-buildroot-linux-gnueabihf/sysroot/usr/include analogclock.h -o .moc/moc_analogclock.cpp
+/home/vmtest/work/imx6ul-fire/code-build/rootfs/buildroot-2017.08.1/output/host/bin/arm-buildroot-linux-gnueabihf-g++ -c -pipe -D_LARGEFILE_SOURCE -D_LARGEFILE64_SOURCE -D_FILE_OFFSET_BITS=64 -Os --sysroot=/home/vmtest/work/imx6ul-fire/code-build/rootfs/buildroot-2017.08.1/output/host/arm-buildroot-linux-gnueabihf/sysroot -O2 -O3 -fno-exceptions -Wall -W -D_REENTRANT -fPIC -DQT_NO_EXCEPTIONS -D_LARGEFILE64_SOURCE -D_LARGEFILE_SOURCE -DQT_NO_DEBUG -DQT_WIDGETS_LIB -DQT_GUI_LIB -DQT_CORE_LIB -I. -I../../../../include -I../../../../include/QtWidgets -I../../../../include/QtGui -I../../../../include/QtCore -I.moc -I../../../../mkspecs/devices/linux-buildroot-g++ -o .obj/moc_analogclock.o .moc/moc_analogclock.cpp
+/home/vmtest/work/imx6ul-fire/code-build/rootfs/buildroot-2017.08.1/output/host/bin/arm-buildroot-linux-gnueabihf-g++ --sysroot=/home/vmtest/work/imx6ul-fire/code-build/rootfs/buildroot-2017.08.1/output/host/arm-buildroot-linux-gnueabihf/sysroot -Wl,-O1 -Wl,--enable-new-dtags -o analogclock .obj/analogclock.o .obj/main.o .obj/moc_analogclock.o   -L/home/vmtest/work/imx6ul-fire/code-build/rootfs/buildroot-2017.08.1/output/build/qt5base-5.9.1/lib -lQt5Widgets -lQt5Gui -lQt5Core -lrt -ldl -latomic -lpthread 
+ 
+real  0m3.491s
+user  0m2.031s
+sys 0m1.433s
+vmtest@linux-test:~/work/imx6ul-fire/code-build/rootfs/buildroot-2017.08.1/output/build/qt5base-5.9.1/examples/widgets/widgets/analogclock$ ls
+analogclock      analogclock.h    main.cpp
+analogclock.cpp  analogclock.pro  Makefile
+vmtest@linux-test:~/work/imx6ul-fire/code-build/rootfs/buildroot-2017.08.1/output/build/qt5base-5.9.1/examples/widgets/widgets/analogclock$ file analogclock
+analogclock: ELF 32-bit LSB executable, ARM, EABI5 version 1 (SYSV), dynamically linked, interpreter /lib/ld-, for GNU/Linux 4.1.0, not stripped
+vmtest@linux-test:~/work/imx6ul-fire/code-build/rootfs/buildroot-2017.08.1/output/build/qt5base-5.9.1/examples/widgets/widgets/analogclock$
+```
+
+
+---
+#### 三、测试根文件系统
+
+
+开发板用的野火出厂固件，这里只替换根文件系统。
+
+使用NFS挂载buildroot根文件系统来测试，操作方法如下 (里面用到的IP和相关目录，需要改成你的~)：
+
+##### 1.解压根文件系统到NFS目录内
+
+```
+cd buildroot-2017.08.1/output/images/
+
+sudo tar xvf rootfs.tar -C /nfsroot/imx6ull-nfs/buildroot2017-v1/
+
+sync
+```
+
+##### 2.开发板从NFS启动根文件系统
+
+进入uboot命令行设置启动参数：
+
+- 设置bootargs
+```
+setenv bootargs "console=${console},${baudrate} root=/dev/nfs ip=192.168.2.102:192.168.2.119:192.168.2.1:255.255.255.0:imx6ull:eth0:off rootwait rw nfsroot=192.168.2.119:/nfsroot/imx6ull-nfs/buildroot2017-v1 consoleblank=0 init=/sbin/init";saveenv
+```
+- 设置bootcmd，设置后开发板自动从NFS启动
+```
+setenv bootcmd "mmc dev 1;mmc dev 1; mmc rescan;fatload mmc 1 0x80800000 zImage;fatload mmc 1 0x83000000 imx6ull-14x14-evk.dtb;bootz 0x80800000 - 0x83000000"
+```
+
+到这里，一切正常的话，系统就启动了！
+
+
+```
+Welcome to Buildroot
+buildroot login: root
+# cd /
+# ls
+bin      lib      media    proc     sbin     usr
+dev      lib32    mnt      root     sys      var
+etc      linuxrc  opt      run      tmp
+#
+
+```
+
+##### 3.运行Qt5例程
+
+- 配置环境变量
+```
+export  QT_QPA_PLATFORM=linuxfb:fb=/dev/fb0
+export  QT_QPA_EVDEV_TOUCHSCREEN_PARAMETERS=/dev/input/event1:inverty
+```
+- 运行例程
+
+```
+# export  QT_QPA_PLATFORM=linuxfb:fb=/dev/fb0
+# export  QT_QPA_EVDEV_TOUCHSCREEN_PARAMETERS=/dev/input/event1:inverty
+# ./analogclock
+
+```
+
+![image](media/buildroot2017-rootfs/qt5clock.png)
+
+---
+ *本篇完。*
\ No newline at end of file
diff --git a/documentation/submission/buildroot2017-2.md b/documentation/submission/buildroot2017-2.md
new file mode 100644
index 0000000000000000000000000000000000000000..b2cac17ea206cd7bd8ddff8f9504f479f1dcd555
--- /dev/null
+++ b/documentation/submission/buildroot2017-2.md
@@ -0,0 +1,271 @@
+## 制作buildroot根文件系统(二)：使用tinyalsa播放音频
+
+
+- 主机环境：ubuntu16.04-64bit
+- 硬件版本：野火imx6ull-pro emmc
+
+
+
+---
+
+
+
+
+#### 一、制作根文件系统
+
+详细的制作方法请参考：[制作buildroot根文件系统(一)：根文件系统和Qt5例程](buildroot2017-1.md)
+
+本篇只介绍 buildroot 中关于 tinyalsa 的配置。
+
+##### 1.关于 tinyalsa
+目前 linux 中主流的音频体系结构是ALSA（Advanced Linux Sound Architecture），ALSA在内核驱动层提供了alsa-driver，在应用层提供了alsa-lib，应用程序只需要调用alsa-lib提供的API就可以完成对底层硬件的操作。
+
+但是 ALSA 较为庞大，对于资源有限，可以满足需求的前提下，ALSA 的 简化版 tinyalsa 是个不错的选择。
+
+tinyalsa 编译后会生成四个小工具：
+
+- tinypcminfo
+```
+用于查看pcm通道的相关信息。
+```
+- tinymix
+```
+用于查看设置各项配置参数。
+```
+- tinycap
+```
+简易的录音软件，用于录音测试。
+```
+- tinyplay
+```
+用于播放测试，只能播放wav原始格式的音乐。
+```
+
+##### 2.配置buildroot
+
+- 进入配置菜单
+```
+cd buildroot-2017.08.1/
+make menuconfig
+```
+
+- 关键配置截图
+
+选中 tinyalsa:
+![image](media/buildroot2017-rootfs/tinyalsa.png)
+
+
+- 使用现成的配置
+
+由于细节无法全面展现，新手可以使用我提供的现成配置。
+
+点这里查看下载：[my-imx6u-buildroot2017-v1.0.config](https://github.com/Jmhh247/fireimx6-tutorial/blob/master/my-imx6u-buildroot2017-v1.0.config)
+
+把我的配置文件复制到buildroot目录，并改名为.config。
+
+```
+cd buildroot-2017.08.1/
+
+cp my-imx6u-buildroot2017-v1.0.config .config
+```
+
+
+##### 3.编译buildroot
+
+很简单，直接make.
+
+```
+cd buildroot-2017.08.1/
+
+time make
+```
+
+整个编译过程较长，可能达几个小时。
+
+##### 4.生成的根文件系统和工具链位置
+生成根文件系统位置：
+```
+buildroot-2017.08.1/output/images/rootfs.tar
+```
+
+制作好的工具链位置：
+```
+# arm-gcc
+buildroot-2017.08.1/output/host/bin/arm-buildroot-linux-gnueabihf-
+
+# qmake
+buildroot-2017.08.1/output/build/qt5base-5.9.1/bin/qmake
+```
+
+有了ARMGCC工具链就可以编译linux，uboot，和你的应用程序等，本篇不涉及这些，不再展开介绍。
+
+---
+#### 二、测试根文件系统
+
+
+开发板用的野火出厂固件，这里只替换根文件系统。
+
+使用NFS挂载buildroot根文件系统来测试，操作方法如下 (里面用到的IP和相关目录，需要改成你的~)：
+
+##### 1.解压根文件系统到NFS目录内
+
+```
+cd buildroot-2017.08.1/output/images/
+
+sudo tar xvf rootfs.tar -C /nfsroot/imx6ull-nfs/buildroot2017-v1/
+
+sync
+```
+
+##### 2.开发板从NFS启动根文件系统
+
+进入uboot命令行设置启动参数：
+
+- 设置bootargs
+```
+setenv bootargs "console=${console},${baudrate} root=/dev/nfs ip=192.168.2.102:192.168.2.119:192.168.2.1:255.255.255.0:imx6ull:eth0:off rootwait rw nfsroot=192.168.2.119:/nfsroot/imx6ull-nfs/buildroot2017-v1 consoleblank=0 init=/sbin/init";saveenv
+```
+- 设置bootcmd，设置后开发板自动从NFS启动
+```
+setenv bootcmd "mmc dev 1;mmc dev 1; mmc rescan;fatload mmc 1 0x80800000 zImage;fatload mmc 1 0x83000000 imx6ull-14x14-evk.dtb;bootz 0x80800000 - 0x83000000"
+```
+
+到这里，一切正常的话，系统就启动了！
+
+
+```
+Welcome to Buildroot
+buildroot login: root
+# cd /
+# ls
+bin      lib      media    proc     sbin     usr
+dev      lib32    mnt      root     sys      var
+etc      linuxrc  opt      run      tmp
+#
+
+# tiny
+tinycap      tinymix      tinypcminfo  tinyplay
+#
+
+```
+
+---
+#### 三、测试 tinyalsa 播放音频
+
+##### 1.使用 tinymix 配置声卡
+
+系统启动后，声卡默认是关闭的，需要配置一下通道开关、音量等。
+
+
+- 查询声卡参数
+
+首先查询下当前状态，使用命令：
+
+```
+tinymix contents
+```
+
+查询到的结果如下：
+```
+# tinymix contents
+Number of controls: 57
+ctl     type    num     name                                    value
+0       INT     2       Capture Volume                          39, 39 (range 0->63)
+1       INT     2       Capture Volume ZC Switch                0, 0 (range 0->1)
+2       BOOL    2       Capture Switch                          Off, Off
+3       INT     1       Right Input Boost Mixer RINPUT3 Volume  0 (range 0->7)
+4       INT     1       Right Input Boost Mixer RINPUT2 Volume  0 (range 0->7)
+5       INT     1       Left Input Boost Mixer LINPUT3 Volume   0 (range 0->7)
+6       INT     1       Left Input Boost Mixer LINPUT2 Volume   0 (range 0->7)
+7       INT     1       Right Input Boost Mixer RINPUT1 Volume  0 (range 0->3)
+8       INT     1       Left Input Boost Mixer LINPUT1 Volume   0 (range 0->3)
+9       INT     2       Playback Volume                         255, 255 (range 0->255)
+10      INT     2       Headphone Playback Volume               0, 0 (range 0->127)
+11      BOOL    2       Headphone Playback ZC Switch            Off, Off
+12      INT     2       Speaker Playback Volume                 0, 0 (range 0->127)
+13      BOOL    2       Speaker Playback ZC Switch              Off, Off
+14      INT     1       Speaker DC Volume                       0 (range 0->5)
+15      INT     1       Speaker AC Volume                       0 (range 0->5)
+16      BOOL    1       PCM Playback -6dB Switch                Off
+17      ENUM    1       ADC Polarity                            , No InversionLeft InvertedRight InvertedStereo Inversion
+18      BOOL    1       ADC High Pass Filter Switch             Off
+19      ENUM    1       DAC Polarity                            , No InversionLeft InvertedRight InvertedStereo Inversion
+20      BOOL    1       DAC Deemphasis Switch                   Off
+21      ENUM    1       3D Filter Upper Cut-Off                 0 (range 0->7)
+22      ENUM    1       3D Filter Lower Cut-Off                 0 (range 0->7)
+23      INT     1       3D Volume                               0 (range 0->7)
+24      BOOL    1       3D Switch                               0 (range 0->7)
+25      ENUM    1       ALC Function                            , OffRightLeftStereo
+26      INT     1       ALC Max Gain                            7 (range 0->7)
+27      INT     1       ALC Target                              4 (range 0->15)
+28      INT     1       ALC Min Gain                            0 (range 0->7)
+29      INT     1       ALC Hold Time                           0 (range 0->15)
+30      ENUM    1       ALC Mode                                , ALCLimiter
+31      INT     1       ALC Decay                               3 (range 0->15)
+32      INT     1       ALC Attack                              2 (range 0->15)
+33      INT     1       Noise Gate Threshold                    0 (range 0->31)
+34      BOOL    1       Noise Gate Switch                       Off
+35      INT     2       ADC PCM Capture Volume                  195, 195 (range 0->255)
+36      INT     1       Left Output Mixer Boost Bypass Volume   2 (range 0->7)
+37      INT     1       Left Output Mixer LINPUT3 Volume        2 (range 0->7)
+38      INT     1       Right Output Mixer Boost Bypass Volume  2 (range 0->7)
+39      INT     1       Right Output Mixer RINPUT3 Volume       2 (range 0->7)
+40      ENUM    1       ADC Data Output Select                  , Left Data = Left ADC;  Right Data = Right ADCLeft Data = Left ADC;  Right Data = Left ADCLeft Data = Right ADC; Right Data = Right ADCLeft Data = Right ADC; Right Data = Left ADC
+41      BOOL    1       Mono Output Mixer Left Switch           Off
+42      BOOL    1       Mono Output Mixer Right Switch          Off
+43      BOOL    1       Right Output Mixer PCM Playback Switch  Off
+44      BOOL    1       Right Output Mixer RINPUT3 Switch       Off
+45      BOOL    1       Right Output Mixer Boost Bypass Switch  Off
+46      BOOL    1       Left Output Mixer PCM Playback Switch   Off
+47      BOOL    1       Left Output Mixer LINPUT3 Switch        Off
+48      BOOL    1       Left Output Mixer Boost Bypass Switch   Off
+49      BOOL    1       Right Input Mixer Boost Switch          Off
+50      BOOL    1       Left Input Mixer Boost Switch           Off
+51      BOOL    1       Right Boost Mixer RINPUT2 Switch        Off
+52      BOOL    1       Right Boost Mixer RINPUT3 Switch        Off
+53      BOOL    1       Right Boost Mixer RINPUT1 Switch        On
+54      BOOL    1       Left Boost Mixer LINPUT2 Switch         Off
+55      BOOL    1       Left Boost Mixer LINPUT3 Switch         Off
+56      BOOL    1       Left Boost Mixer LINPUT1 Switch         On
+#
+
+```
+
+- 经过测试，至少设置下面三项：
+
+```
+设置耳机音量
+tinymix set 10 75
+
+右声道
+tinymix set 43 1
+
+左声道
+tinymix set 46 1
+```
+
+##### 2.使用 tinyplay 播放 wav 音频
+准备一段wav格式的音乐，复制到根文件系统。
+
+开始播放：
+```
+# ls
+bin       lib       media     proc      sbin      usr
+dev       lib32     mnt       root      sys       var
+etc       linuxrc   opt       run       tmp       yzxd.wav
+# tinymix set 10 75
+# tinymix set 43 1
+# tinymix set 46 1
+# tinyplay yzxd.wav
+playing 'yzxd.wav': 2 ch, 48000 hz, 16 bit
+#
+```
+
+
+插上耳机欣赏音乐吧，耳机位置在这里：
+
+![image](media/buildroot2017-rootfs/audio.png)
+
+
+---
+*本篇完。*
\ No newline at end of file
diff --git a/documentation/submission/buildroot2017-3.md b/documentation/submission/buildroot2017-3.md
new file mode 100644
index 0000000000000000000000000000000000000000..fbc1c6713716bb8d2545f10b1e7a48c555b1a9b3
--- /dev/null
+++ b/documentation/submission/buildroot2017-3.md
@@ -0,0 +1,304 @@
+## 制作buildroot根文件系统(三)：使用mplayer播放视频
+
+
+- 主机环境：ubuntu16.04-64bit
+- 硬件版本：野火imx6ull-pro emmc
+
+
+
+---
+
+
+
+
+#### 一、制作根文件系统
+
+详细的制作方法请参考：[制作buildroot根文件系统(一)：根文件系统和Qt5例程](buildroot2017-1.md)
+
+本篇只介绍 buildroot 中关于 mplayer 的配置。
+
+##### 1.关于 mplayer
+mplayer 是一款开源多媒体播放器，基于命令行界面，以GNU通用公共许可证发布。可在各主流作业系统使用，例如Linux和其他类Unix系统、Windows及Mac OS X系统。
+
+##### 2.配置buildroot
+
+- 进入配置菜单
+```
+cd buildroot-2017.08.1/
+make menuconfig
+```
+
+- 关键配置截图
+
+选中 mplayer:
+![image](media/buildroot2017-rootfs/mplayer.png)
+
+选中 alsa-lib，否则没声音：
+![image](media/buildroot2017-rootfs/alsa-lib.png)
+
+
+- 使用现成的配置
+
+由于细节无法全面展现，新手可以使用我提供的基础配置，在基础配置增加选项。
+
+点这里查看下载：[my-imx6u-buildroot2017-v1.0.config](https://github.com/Jmhh247/fireimx6-tutorial/blob/master/my-imx6u-buildroot2017-v1.0.config)
+
+把我的配置文件复制到buildroot目录，并改名为.config。
+
+```
+cd buildroot-2017.08.1/
+
+cp my-imx6u-buildroot2017-v1.0.config .config
+```
+
+
+##### 3.编译buildroot
+
+很简单，直接make.
+
+```
+cd buildroot-2017.08.1/
+
+time make
+```
+
+整个编译过程较长，可能达几个小时。
+
+##### 4.生成的根文件系统和工具链位置
+生成根文件系统位置：
+```
+buildroot-2017.08.1/output/images/rootfs.tar
+```
+
+制作好的工具链位置：
+```
+# arm-gcc
+buildroot-2017.08.1/output/host/bin/arm-buildroot-linux-gnueabihf-
+
+# qmake
+buildroot-2017.08.1/output/build/qt5base-5.9.1/bin/qmake
+```
+
+有了ARMGCC工具链就可以编译linux，uboot，和你的应用程序等，本篇不涉及这些，不再展开介绍。
+
+---
+#### 二、测试根文件系统
+
+
+开发板用的野火出厂固件，这里只替换根文件系统。
+
+使用NFS挂载buildroot根文件系统来测试，操作方法如下 (里面用到的IP和相关目录，需要改成你的~)：
+
+##### 1.解压根文件系统到NFS目录内
+
+```
+cd buildroot-2017.08.1/output/images/
+
+sudo tar xvf rootfs.tar -C /nfsroot/imx6ull-nfs/buildroot2017-v1/
+
+sync
+```
+
+##### 2.开发板从NFS启动根文件系统
+
+进入uboot命令行设置启动参数：
+
+- 设置bootargs
+```
+setenv bootargs "console=${console},${baudrate} root=/dev/nfs ip=192.168.2.102:192.168.2.119:192.168.2.1:255.255.255.0:imx6ull:eth0:off rootwait rw nfsroot=192.168.2.119:/nfsroot/imx6ull-nfs/buildroot2017-v1 consoleblank=0 init=/sbin/init";saveenv
+```
+- 设置bootcmd，设置后开发板自动从NFS启动
+```
+setenv bootcmd "mmc dev 1;mmc dev 1; mmc rescan;fatload mmc 1 0x80800000 zImage;fatload mmc 1 0x83000000 imx6ull-14x14-evk.dtb;bootz 0x80800000 - 0x83000000"
+```
+
+到这里，一切正常的话，系统就启动了！
+
+
+```
+Welcome to Buildroot
+buildroot login: root
+# cd /
+# ls
+audiodump.wav  lib32          proc           test.mp4       ym.mp4
+bin            linuxrc        root           testvideo.avi  yzxd.wav
+dev            media          run            tmp
+etc            mnt            sbin           usr
+lib            opt            sys            var
+#
+# mplayer
+MPlayer 1.3.0-6.4.0 (C) 2000-2016 MPlayer Team
+Usage:   mplayer [options] [url|path/]filename
+
+Basic options: (complete list in the man page)
+ -vo <drv>        select video output driver ('-vo help' for a list)
+ -ao <drv>        select audio output driver ('-ao help' for a list)
+ -alang/-slang    select DVD audio/subtitle language (by 2-char country code)
+ -ss <position>   seek to given (seconds or hh:mm:ss) position
+ -nosound         do not play sound
+ -fs              fullscreen playback (or -vm, -zoom, details in the man page)
+ -x <x> -y <y>    set display resolution (for use with -vm or -zoom)
+ -sub <file>      specify subtitle file to use (also see -subfps, -subdelay)
+ -playlist <file> specify playlist file
+ -vid x -aid y    select video (x) and audio (y) stream to play
+ -fps x -srate y  change video (x fps) and audio (y Hz) rate
+ -pp <quality>    enable postprocessing filter (details in the man page)
+ -framedrop       enable frame dropping (for slow machines)
+
+Basic keys: (complete list in the man page, also check input.conf)
+ <-  or  ->       seek backward/forward 10 seconds
+ down or up       seek backward/forward  1 minute
+ pgdown or pgup   seek backward/forward 10 minutes
+ < or >           step backward/forward in playlist
+ p or SPACE       pause movie (press any key to continue)
+ q or ESC         stop playing and quit program
+ + or -           adjust audio delay by +/- 0.1 second
+ o                cycle OSD mode:  none / seekbar / seekbar + timer
+ * or /           increase or decrease PCM volume
+ x or z           adjust subtitle delay by +/- 0.1 second
+ r or t           adjust subtitle position up/down, also see -vf expand
+
+ * * * SEE THE MAN PAGE FOR DETAILS, FURTHER (ADVANCED) OPTIONS AND KEYS * * *
+
+#
+
+```
+
+---
+#### 三、测试 mplayer 播放视频
+
+##### 1.查看 mplayer 的音频输出
+
+查看到alsa，说明音频输出是正常的，否则播放时可能没声音。
+```
+# mplayer -ao help
+MPlayer 1.3.0-6.4.0 (C) 2000-2016 MPlayer Team
+Available audio output drivers:
+        oss     OSS/ioctl audio output
+        alsa    ALSA-0.9.x-1.x audio output
+        mpegpes DVB audio output
+        v4l2    V4L2 MPEG Audio Decoder output
+        null    Null audio output
+        pcm     RAW PCM/WAVE file writer audio output
+
+#
+```
+
+##### 2.使用 tinymix 配置声卡
+
+系统启动后，声卡默认是关闭的，需要配置一下通道开关、音量等。
+
+关于 tinyalsa 的相关介绍在这里：[制作buildroot根文件系统(二)：使用tinyalsa播放音频](buildroot2017-2.md)
+
+- 经过测试，至少设置下面三项：
+```
+设置耳机音量
+tinymix set 10 75
+
+右声道
+tinymix set 43 1
+
+左声道
+tinymix set 46 1
+```
+
+##### 3.使用 mplayer 播放视频
+准备一段mp4或avi格式的视频，复制到根文件系统。
+
+- 播放指令
+```
+mplayer -x 800 -y 480 -zoom -framedrop xxx.mp4
+```
+
+- 播放测试：
+```
+# ls
+audiodump.wav  lib32          proc           test.mp4       ym.mp4
+bin            linuxrc        root           testvideo.avi  yzxd.wav
+dev            media          run            tmp
+etc            mnt            sbin           usr
+lib            opt            sys            var
+#
+# tinymix set 10 75
+# tinymix set 43 1
+# tinymix set 46 1
+#
+# mplayer -x 800 -y 480 -zoom -framedrop test.mp4
+MPlayer 1.3.0-6.4.0 (C) 2000-2016 MPlayer Team
+
+Playing test.mp4.
+libavformat version 57.25.100 (internal)
+libavformat file format detected.
+[mov,mp4,m4a,3gp,3g2,mj2 @ 0x750618]Protocol name not provided, cannot determine if input is local or a network protocol, buffers and access patterns cannot be configured optimally without knowing the protocol
+[lavf] stream 0: video (h264), -vid 0
+[lavf] stream 1: audio (aac), -aid 0, -alang und
+VIDEO:  [H264]  480x272  24bpp  30.000 fps  186.1 kbps (22.7 kbyte/s)
+==========================================================================
+Opening video decoder: [ffmpeg] FFmpeg's libavcodec codec family
+libavcodec version 57.24.102 (internal)
+Selected video codec: [ffh264] vfm: ffmpeg (FFmpeg H.264)
+==========================================================================
+Clip info:
+ major_brand: isom
+ minor_version: 512
+ compatible_brands: isomiso2avc1mp41
+ encoder: Lavf56.25.101
+ copyright: jid:17043011
+Load subtitles in ./
+==========================================================================
+Opening audio decoder: [ffmpeg] FFmpeg/libavcodec audio decoders
+AUDIO: 44100 Hz, 1 ch, floatle, 16.0 kbit/1.13% (ratio: 2000->176400)
+Selected audio codec: [ffaac] afm: ffmpeg (FFmpeg AAC (MPEG-2/MPEG-4 Audio))
+==========================================================================
+[AO OSS] audio_setup: Can't open audio device /dev/dsp: No such file or directory
+AO: [alsa] 44100Hz 1ch floatle (4 bytes per sample)
+Starting playback...
+Could not find matching colorspace - retrying with -vf scale...
+Opening video filter: [scale]
+[swscaler @ 0x9945d8]bicubic scaler, from yuv420p to rgb565le using C
+VO: [fbdev] 800x480 => 800x480 BGR 16-bit  [zoom]
+A:   4.5 V:   3.0 A-V:  1.515 ct:  0.303   0/  0 14% 80%  1.8% 50 0 $<50>
+
+
+           ************************************************
+           **** Your system is too SLOW to play this!  ****
+           ************************************************
+
+Possible reasons, problems, workarounds:
+- Most common: broken/buggy _audio_ driver
+  - Try -ao sdl or use the OSS emulation of ALSA.
+  - Experiment with different values for -autosync, 30 is a good start.
+- Slow video output
+  - Try a different -vo driver (-vo help for a list) or try -framedrop!
+- Slow CPU
+  - Don't try to play a big DVD/DivX on a slow CPU! Try some of the lavdopts,
+    e.g. -vfm ffmpeg -lavdopts lowres=1:fast:skiploopfilter=all.
+- Broken file
+  - Try various combinations of -nobps -ni -forceidx -mc 0.
+- Slow media (NFS/SMB mounts, DVD, VCD etc)
+  - Try -cache 8192.
+- Are you using -cache to play a non-interleaved AVI file?
+  - Try -nocache.
+Read DOCS/HTML/en/video.html for tuning/speedup tips.
+If none of this helps you, read DOCS/HTML/en/bugreports.html.
+
+A:  48.1 V:  33.4 A-V: 14.709 ct:  3.340   0/  0 11% 80%  1.5% 538 0 $<50>
+
+
+MPlayer interrupted by signal 2 in module: filter video
+A:  48.2 V:  33.4 A-V: 14.735 ct:  3.343   0/  0 11% 80%  1.5% 538 0 $<50>
+
+Exiting... (Quit)
+# 
+```
+
+
+
+
+插上耳机欣赏视频吧：
+
+![image](media/buildroot2017-rootfs/mplayer-play.png)
+
+
+---
+*本篇完。*
\ No newline at end of file
diff --git a/documentation/submission/debian9-rootfs.md b/documentation/submission/debian9-rootfs.md
index 96d6532897356a8bf315dc227ae5093bc216b7e8..8a05f9497ad217a85db7c6104d06e6624fd5163b 100644
--- a/documentation/submission/debian9-rootfs.md
+++ b/documentation/submission/debian9-rootfs.md
@@ -269,7 +269,7 @@ setenv bootargs "console=${console},${baudrate} root=/dev/nfs ip=192.168.2.102:1
 ```
 2. 设置bootcmd，设置后开发板自动从NFS启动
 ```
-setenv bootcmd “mmc dev 1;mmc dev 1; mmc rescan;fatload mmc 1 0x80800000 zImage;fatload mmc 1 0x83000000 imx6ull-14x14-evk.dtb;bootz 0x80800000 - 0x83000000”;saveenv
+setenv bootcmd "mmc dev 1;mmc dev 1; mmc rescan;fatload mmc 1 0x80800000 zImage;fatload mmc 1 0x83000000 imx6ull-14x14-evk.dtb;bootz 0x80800000 - 0x83000000";saveenv
 ```
 
 到这里，一切正常的话，就可以看到debian启动了！
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diff --git a/documentation/submission/media/buildroot2017-rootfs/tinyalsa.png b/documentation/submission/media/buildroot2017-rootfs/tinyalsa.png
new file mode 100644
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diff --git a/documentation/submission/ubuntu16-rootfs.md b/documentation/submission/ubuntu16-rootfs.md
index 181c2dae4827752dc11de6b5cd55d346abf48fd3..1d2f1e362d6ce34b0905b969da226fa48e0f3365 100644
--- a/documentation/submission/ubuntu16-rootfs.md
+++ b/documentation/submission/ubuntu16-rootfs.md
@@ -241,7 +241,7 @@ setenv bootargs "console=${console},${baudrate} root=/dev/nfs ip=192.168.2.102:1
 ```
 - 设置bootcmd，设置后开发板自动从NFS启动
 ```
-setenv bootcmd “mmc dev 1;mmc dev 1; mmc rescan;fatload mmc 1 0x80800000 zImage;fatload mmc 1 0x83000000 imx6ull-14x14-evk.dtb;bootz 0x80800000 - 0x83000000”
+setenv bootcmd "mmc dev 1;mmc dev 1; mmc rescan;fatload mmc 1 0x80800000 zImage;fatload mmc 1 0x83000000 imx6ull-14x14-evk.dtb;bootz 0x80800000 - 0x83000000"
 ```
 
 到这里，一切正常的话，就可以看到ubuntu启动了！
diff --git a/documentation/system_programing/index.rst b/documentation/system_programing/index.rst
new file mode 100644
index 0000000000000000000000000000000000000000..658c7e077e96f295c2dfb119e2f3ad789d01d424
--- /dev/null
+++ b/documentation/system_programing/index.rst
@@ -0,0 +1,21 @@
+.. vim: syntax=rst
+
+第五部分 系统编程
+==================================
+
+
+.. .. toctree::
+..    :maxdepth: 1
+..    :numbered:
+
+..    process
+..    signal
+..    pipe
+..    msg_queuq
+..    systemV_sem
+..    shm
+..    thread
+..    posix_sem
+..    posix_mutex
+..    tcp_ip
+..    socket
diff --git a/documentation/system_programing/media/shm001.png b/documentation/system_programing/media/shm001.png
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diff --git a/documentation/system_programing/media/thread001.png b/documentation/system_programing/media/thread001.png
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diff --git a/documentation/system_programing/msg_queuq.rst b/documentation/system_programing/msg_queuq.rst
new file mode 100644
index 0000000000000000000000000000000000000000..29845e1490b20b7f66ff0136f9f2eedb4e437aac
--- /dev/null
+++ b/documentation/system_programing/msg_queuq.rst
@@ -0,0 +1,433 @@
+消息队列
+========
+
+Linux下的进程通信手段基本上是从Unix平台上的进程通信手段继承而来的。而对Unix发展做出重大贡献的两大主力AT&T的贝尔实验室及BSD（加州大学伯克利分校的伯克利软件发布中心）在进程间通信方面的侧重点有所不同；前者对Unix早期的进程间通信手段进行了系统的改进和扩充，形成了"system
+V
+IPC"，通信进程局限在单个计算机内（同一个设备的不同进程间通讯）；而后者则跳过了该限制，形成了基于套接字（socket）的进程间通信机制（多用于不同设备的进程间通讯）。Linux则把两者继承了下来，所以说Linux才是最成功的，既有"system
+V IPC"，又支持socket。
+
+**消息队列、共享内存 和 信号量** 被统称为 system-V IPC，V 是罗马数字
+5，是 Unix 的AT&T 分支的其中一个版本，一般习惯称呼他们为 IPC
+对象，这些对象的操作接口都比较类似，在系统中他们都使用一种叫做 key
+的键值来唯一标识，而且他们都是"持续性"资源——即他们被创建之后，不会因为进程的退出而消失，而会持续地存在，除非调用特殊的函数或者命令删除他们。
+
+消息队列的基本概念
+------------------
+
+Linux的消息队列（queue）实质上是一个内核地址空间中的内部链表，它有消息队列标识符（queue
+ID）。通过Linux内核在各个进程直接传递内容，消息顺序地发送到消息队列中，并以几种不同的方式从队列中获得，每个消息队列可以用消息队列标识符唯一地进行识别。内核中是通过IPC的标识符来区别不同的消息队列，不同的消息队列之间是相互独立的，每个消息队列中的消息，又构成一个独立的链表，这样子就是在内涵中维护多个消息队列，每个消息队列的内部又通过链表维护了不同的消息，举个不太恰当的比喻：假设你的房子就是内核，那么每个房间就是消息队列，一个房子有多个房间，而每个房间睡觉的人就是不同的消息，有一些房间可以睡很多个人，有一些房间没有人。在Linux系统中，只要有足够权限的进程都可以向某个消息队列中发送消息，被赋予读权限的进程则可以读走这个消息队列中的消息，
+
+当然也可能有同学对消息队列的标识符感兴趣，那我就简单介绍一下：每个内核中的
+IPC
+结构（消息队列、信号量或共享存储段）都用一个非负整数的标识符（identifier）加以引用。例如，为了对一个消息队列发送或取消息，只需知道其消息队列标识符。这个消息队列标识符是在内部使用，因此这样的标识方法不能支持进程间通信的，那怎么办呢？别急，且听我慢慢道来!
+
+而我们用户接触到的只是IPC关键字，并非IPC标识符，这是因为IPC标识符是IPC结构的内部名。为使多个合作进程能够在同一IPC对象上会合，需要提供一个外部名方案，即关键字（key）每一个IPC对象都与一个IPC关键字相关联，于是关键字就作为该IPC结构的外部名。要想获得一个唯一标识符，必须使用一个IPC关键字，这样子只要不同进程间使用的关键字是相同的，就可以得到相同的IPC标识符，这样子就能保证访问到相同的消息队列。因此无论何时创建IPC结构，都应指定一个关键字（key），关键字的数据类型由系统规定为
+key_t，是一个长整型的数据类型，关键字由内核变换成标识符。
+
+**消息队列与信号的对比：**
+
+-  信号承载的信息量少，而消息队列可以承载大量的数据
+
+**消息队列与管道的对比：**
+
+-  消息队列跟命名管道有不少的相同之处，通过与命名管道一样，消息队列进行通信的进程可以是不相关的进程，同时它们都是通过发送和接收的方式来传递数据的。在命名管道中，发送数据用write()，接收数据用read()，则在消息队列中，发送数据用msgsnd()，接收数据用msgrcv()。它们对每个数据都有一个最大长度的限制。
+
+-  消息队列也可以独立于发送和接收进程而存在，在进程终止时，消息队列及其内容并不会被删除。
+
+-  管道只能承载无格式字节流，消息队列提供有格式的字节流，可以减少了开发人员的工作量。
+
+-  消息队列是面向记录的，其中的消息具有特定的格式以及特定的优先级，接收程序可以通过消息类型有选择地接收数据，而不是像命名管道中那样，只能默认地接收。
+
+-  消息队列可以实现消息的随机查询，消息不一定要以先进先出的顺序接收，也可以按消息的类型接收。
+
+消息队列的实现包括创建或打开消息队列、发送消息、接收消息和控制消息队列这
+4 种操作。其中创建或打开消息队列使用的函数是
+msgget()，这里创建的消息队列的数量会受到系统可支持的消息队列数量的限制；发送消息使用的函数是
+msgsnd()函数，它把消息发送到已打开的消息队列末尾;接收消息使用的函数是msgrcv()，它把消息从消息队列中取走，与
+FIFO 不同的是，这里可以指定取走某一条消息;最后控制消息队列使用的函数是
+msgctl()，它可以完成多项功能。
+
+想要使用消息队列还需要包含以下头文件：
+
+.. code:: c
+
+        #include <sys/types.h>
+        #include <sys/ipc.h>
+        #include <sys/msg.h>
+
+创建或获取消息队列ID
+--------------------
+
+**msgget()函数**
+
+.. code:: c
+
+       int msgget(key_t key, int msgflg);
+
+该函数的作用是得到消息队列标识符或创建一个消息队列对象并返回消息队列标识符：成功返回队列ID，失败返回-1。为什么说这个函数是创建或者获取消息队列ID呢？在以下两种情况下，msgget()函数将创建一个新的消息队列：
+
+1. 如果没有与键值key相对应的消息队列，并且flag中包含了IPC_CREAT标志位。
+2. key参数为IPC_PRIVATE。
+
+-  key:消息队列的关键字值，多个进程可以通过它访问同一个消息队列，其中有个特殊值
+   IPC_PRIVATE，它用于创建当前进程的私有消息队列。
+
+-  msgflg表示创建的消息队列的模式标志参数，在真正使用时需要与IPC对象存取权限（如0600）进行"｜"运算来确定消息队列的存取权限。msgflg有多种情况：如果为0则表示取消息队列标识符，若该消息队列不存在则函数会报错；如果是 ``IPC_CREAT & msgflg``
+   为真则表示：如果内核中不存在关键字与key相等的消息队列，则新建一个消息队列；如果存在这样的消息队列，返回此消息队列的标识符，而如果为 ``IPC_CREAT | IPC_EXCL`` 为真则表示：如果内核中不存在键值与key相等的消息队列，则新建一个消息队列；如果存在这样的消息队列则报错，这些参数是可以通过"｜"运算符联合起来的，因为它始终是int类型的参数。
+
+该函数可能返回以下错误代码：
+
+-  EACCES：指定的消息队列已存在，但调用进程没有权限访问它
+
+-  EEXIST：key指定的消息队列已存在，而msgflg中同时指定IPC_CREAT和IPC_EXCL标志
+
+-  ENOENT：key指定的消息队列不存在同时msgflg中没有指定IPC_CREAT标志
+
+-  ENOMEM：需要建立消息队列，但内存不足
+
+-  ENOSPC：需要建立消息队列，但已达到系统的限制
+
+**使用该函数需要注意的以下几点:**
+
+1. 选项 msgflg 是一个位屏蔽字，因此 IPC_CREAT、IPC_EXCL 和权限 mode
+   可以用位或的方式叠加起来，比如: ``msgget(key, IPC_CREAT | 0666);`` 表示如果
+   key 对应的消息队列不存在就创建，且权限指定为
+   0666，若已存在则直接获取消息队列ID。
+2. 权限只有读和写，执行权限是无效的，例如 0777 跟 0666 是等价的。
+3. 当 key 被指定为 IPC_PRIVATE 时，系统会自动产生一个未用的 key
+   来对应一个新的消息队列对象，这个消息队列一般用于进程内部间的通信。
+
+发送消息与接收消息
+------------------
+
+**msgsnd()函数**
+
+这个函数的主要作用就是将消息写入到消息队列，俗称发送一个消息。
+
+**函数原型：**
+
+.. code:: c
+
+        int msgsnd(int msqid, const void *msgp, size_t msgsz, int msgflg);
+
+**函数传入值：**
+
+-  msqid：消息队列标识符。
+
+-  msgp：发送给队列的消息。msgp可以是任何类型的结构体，但第一个字段必须为long类型，即表明此发送消息的类型，msgrcv()函数则根据此接收消息。msgp定义的参照格式如下：
+
+   .. code:: c
+
+           /*msgp定义的参照格式*/
+           struct s_msg{ 
+               long type;  /* 必须大于0,消息类型 */
+               char mtext[１];  /* 消息正文，可以是其他任何类型 */
+           } msgp;
+
+-  msgsz：要发送消息的大小，不包含消息类型占用的4个字节，即mtext的长度。
+
+-  msgflg：如果为0则表示：当消息队列满时，msgsnd()函数将会阻塞，直到消息能写进消息队列；如果为IPC_NOWAIT则表示：当消息队列已满的时候，msgsnd()函数不等待立即返回；如果为IPC_NOERROR：若发送的消息大于size字节，则把该消息截断，截断部分将被丢弃，且不通知发送进程。
+
+如果成功则返回0，如果失败则返回-1，并且错误原因存于error中。
+
+**错误代码：**
+
+-  EAGAIN：参数msgflg设为IPC_NOWAIT，而消息队列已满。
+
+-  EIDRM：标识符为msqid的消息队列已被删除。
+
+-  EACCESS：无权限写入消息队列。
+
+-  EFAULT：参数msgp指向无效的内存地址。
+
+-  EINTR：队列已满而处于等待情况下被信号中断。
+
+-  EINVAL：无效的参数msqid、msgsz或参数消息类型type小于0。
+
+msgsnd()为阻塞函数，当消息队列容量满或消息个数满会阻塞。消息队列已被删除，则返回EIDRM错误；被信号中断返回E_INTR错误。
+
+如果设置IPC_NOWAIT消息队列满或个数满时会返回-1，并且置EAGAIN错误。
+
+msgsnd()解除阻塞的条件有以下三个条件：
+
+1. 消息队列中有容纳该消息的空间。
+2. msqid代表的消息队列被删除。
+3. 调用msgsnd函数的进程被信号中断。
+
+**msgrcv()函数**
+
+函数原型：
+
+.. code:: c
+
+        ssize_t msgrcv(int msqid, void *msgp, size_t msgsz, long msgtyp, int msgflg);
+
+msgrcv()函数是从标识符为msqid的消息队列读取消息并将消息存储到msgp中，读取后把此消息从消息队列中删除，也就是俗话说的接收消息。
+
+**函数传入值：**
+
+-  msqid：消息队列标识符。
+
+-  msgp：存放消息的结构体，结构体类型要与msgsnd()函数发送的类型相同。
+
+-  msgsz：要接收消息的大小，不包含消息类型占用的4个字节。
+
+-  msgtyp有多个可选的值：如果为0则表示接收第一个消息，如果大于0则表示接收类型等于msgtyp的第一个消息，而如果小于0则表示接收类型等于或者小于msgtyp绝对值的第一个消息。
+
+**msgflg取值情况如下：**
+
+-  0: 阻塞式接收消息，没有该类型的消息msgrcv函数一直阻塞等待
+
+-  IPC_NOWAIT：若在消息队列中并没有相应类型的消息可以接收，则函数立即返回，此时错误码为ENOMSG
+
+-  IPC_EXCEPT：与msgtype配合使用返回队列中第一个类型不为msgtype的消息
+
+-  IPC_NOERROR：如果队列中满足条件的消息内容大于所请求的size字节，则把该消息截断，截断部分将被丢弃
+
+msgrcv()函数如果接收消息成功则返回实际读取到的消息数据长度，否则返回-1，错误原因存于error中。
+
+**错误代码**
+
+-  E2BIG：消息数据长度大于msgsz而msgflag没有设置IPC_NOERROR
+
+-  EIDRM：标识符为msqid的消息队列已被删除
+
+-  EACCESS：无权限读取该消息队列
+
+-  EFAULT：参数msgp指向无效的内存地址
+
+-  ENOMSG：参数msgflg设为IPC_NOWAIT，而消息队列中无消息可读
+
+-  EINTR：等待读取队列内的消息情况下被信号中断
+
+msgrcv()函数解除阻塞的条件也有三个：
+
+1. 消息队列中有了满足条件的消息。
+2. msqid代表的消息队列被删除。
+3. 调用msgrcv()函数的进程被信号中断。
+
+操作消息队列
+------------
+
+消息队列是可以被用户操作的，比如设置或者获取消息队列的相关属性，那么可以通过msgctl()函数去处理它。
+
+**函数原型：**
+
+.. code:: c
+
+    int msgctl(int msqid, int cmd, struct msqid_ds *buf);
+
+**函数传入值：**
+
+-  msqid：消息队列标识符。
+
+**cmd的取值有多个：**
+
+-  IPC_STAT 获取该 MSG 的信息，获取到的信息会储存在结构体 msqid_ds
+   类型的buf中。
+
+-  IPC_SET 设置消息队列的属性，要设置的属性需先存储在结构体
+   msqid_ds类型的buf中，可设置的属性包括：msg_perm.uid、msg_perm.gid、msg_perm.mode以及msg_qbytes，储存在结构体
+   msqid_ds。
+
+-  IPC_RMID 立即删除该 MSG，并且唤醒所有阻塞在该 MSG
+   上的进程，同时忽略第三个参数。
+
+-  IPC_INFO 获得关于当前系统中 MSG 的限制值信息。
+
+-  MSG_INFO 获得关于当前系统中 MSG 的相关资源消耗信息。
+
+-  MSG_STAT 同 IPC_STAT，但 msgid
+   为该消息队列在内核中记录所有消息队列信息的数组的下标，因此通过迭代所有的下标可以获得系统中所有消息队列的相关信息。
+
+-  buf：相关信息结构体缓冲区。
+
+**函数返回值：**
+
+-  成功：0
+
+-  出错：-1，错误原因存于error中
+
+**错误代码：**
+
+-  EACCESS：参数cmd为IPC_STAT，确无权限读取该消息队列。
+
+-  EFAULT：参数buf指向无效的内存地址。
+
+-  EIDRM：标识符为msqid的消息队列已被删除。
+
+-  EINVAL：无效的参数cmd或msqid。
+
+-  EPERM：参数cmd为IPC_SET或IPC_RMID，却无足够的权限执行。
+
+消息队列实例
+------------
+
+消息队列的使用方法一般是:
+
+**发送者:**
+
+1. 获取消息队列的 ID
+2. 将数据放入一个附带有标识的特殊的结构体，发送给消息队列。
+
+**接收者:**
+
+1. 获取消息队列的 ID
+2. 将指定标识的消息读出。
+
+当发送者和接收者都不再使用消息队列时，及时删除它以释放系统资源。
+
+本次实验主要是两个进程（无血缘关系的进程）通过消息队列进行消息的传递，一个进程发送消息，一个进程接收消息，并将其打印出来。
+
+**发送进程源码**
+
+.. code:: c
+
+    #include <sys/types.h>
+    #include <sys/ipc.h>
+    #include <sys/msg.h>
+    #include <stdio.h>
+    #include <stdlib.h>
+    #include <unistd.h>
+    #include <string.h>
+
+
+    #define BUFFER_SIZE 512
+
+    struct message
+    {
+        long msg_type;
+        char msg_text[BUFFER_SIZE];
+    };
+    int main()
+    {
+        int qid;
+        struct message msg;
+
+        /*创建消息队列*/
+        if ((qid = msgget((key_t)1234, IPC_CREAT|0666)) == -1)
+        {
+            perror("msgget");
+            exit(1);
+        }
+
+        printf("Open queue %d\n",qid);
+
+        while(1)
+        {
+            printf("Enter some message to the queue:");
+            if ((fgets(msg.msg_text, BUFFER_SIZE, stdin)) == NULL)
+            {
+                puts("no message");
+                exit(1);
+            }
+            
+            msg.msg_type = getpid();
+
+            /*添加消息到消息队列*/
+            if ((msgsnd(qid, &msg, strlen(msg.msg_text), 0)) < 0)
+            {
+                perror("message posted");
+                exit(1);
+            }
+
+            if (strncmp(msg.msg_text, "quit", 4) == 0)
+            {
+                break;
+            }
+        }
+
+        exit(0);
+    }
+
+**接收进程源码：**
+
+.. code:: c
+
+    #include <sys/types.h>
+    #include <sys/ipc.h>
+    #include <sys/msg.h>
+    #include <stdio.h>
+    #include <stdlib.h>
+    #include <unistd.h>
+    #include <string.h>
+
+    #define BUFFER_SIZE 512
+
+    struct message
+    {
+        long msg_type;
+        char msg_text[BUFFER_SIZE];
+    };
+
+    int main()
+    {
+        int qid;
+        struct message msg;
+
+        /*创建消息队列*/
+        if ((qid = msgget((key_t)1234, IPC_CREAT|0666)) == -1)
+        {
+            perror("msgget");
+            exit(1);
+        }
+
+        printf("Open queue %d\n", qid);
+
+        do
+        {
+            /*读取消息队列*/
+            memset(msg.msg_text, 0, BUFFER_SIZE);
+
+            if (msgrcv(qid, (void*)&msg, BUFFER_SIZE, 0, 0) < 0)
+            {
+                perror("msgrcv");
+                exit(1);
+            }
+
+            printf("The message from process %ld : %s", msg.msg_type, msg.msg_text);
+
+        } while(strncmp(msg.msg_text, "quit", 4));
+
+        /*从系统内核中移走消息队列 */
+        if ((msgctl(qid, IPC_RMID, NULL)) < 0)
+        {
+            perror("msgctl");
+            exit(1);
+        }
+
+        exit(0);
+
+    }
+
+将两个进程编译出来，分别运行即可，实验现象如下：
+
+**发送消息：**
+
+在发送消息进程运行的时候，会提示让你输入要发送的消息，随便什么消息都可以的
+
+.. code:: bash
+
+    ➜  msg_send ./targets
+
+    Open queue 0
+    Enter some message to the queue:123
+    Enter some message to the queue:1111111 
+    Enter some message to the queue:666666666666666
+    Enter some message to the queue:abcdef
+    Enter some message to the queue:
+
+**接收消息：**
+
+在新的终端运行接收消息进程，当你从发送消息进程输入消息时（按下回车键发送），接收消息进程会打印出你输入的消息，这是因为进程从消息队列中读取到发送进程发送的消息。
+
+.. code:: bash
+
+    ➜  msg_recv ./targets
+
+    Open queue 0
+    The message from process 12822 : 123
+    The message from process 12822 : 1111111
+    The message from process 12822 : 666666666666666
+    The message from process 12822 : abcdef
+
diff --git a/documentation/system_programing/pipe.rest b/documentation/system_programing/pipe.rest
deleted file mode 100644
index 5ef043bdaca55d87bde1a857f52d7dad94772402..0000000000000000000000000000000000000000
--- a/documentation/system_programing/pipe.rest
+++ /dev/null
@@ -1,354 +0,0 @@
-.. vim: syntax=rst
-
-管道
---
-
-本章节内容处于开发笔记状态，还待整理至最终版的教程。
-
-本章节内容处于开发笔记状态，还待整理至最终版的教程。
-
-管道的基本概念
-~~~~~~~
-
-在进入正式的学习之前，想一想管道为什么叫管道，也想一想生活中有什么跟管道相关的？比如水管，水通过水管从一端流向另一端，那么进程间通信是不是可以模仿这种“流向”的关系呢，很显然是可以的，数据可以从一个进程流向另一个进程，那么一个进程产生数据，然后通过管道发送给另一个进程，另一个进程读取到数据，这样一来
-就实现了进程间的通信了。
-
-在上一章中，我们学过信号，一个信号从进程中产生，发送给另一个进程，这其实也是信号类型的通信，只传递信号值，而没有数据传递，就会在很多时候无法满足我们的需求，因此管道的传输数据功能就会在某些场合非常适用。
-
-我们可以首先做个试验，在终端中使用以下命：
-
-命令
-
-ps -aux \| grep root
-
-输出
-
-root 1 0.0 0.0 225376 6376 ? Ss 10月18 0:31 /sbin/init
-
-root 2 0.0 0.0 0 0 ? S 10月18 0:00 [kthreadd]root 4 0.0 0.0 0 0 ? I< 10月18 0:00 [kworker/0:0H]root 6 0.0 0.0 0 0 ? I< 10月18 0:00 [mm_percpu_wq]root 7
-0.0 0.0 0 0 ? S 10月18 0:02 [ksoftirqd/0]root 8 0.0 0.0 0 0 ? I 10月18 5:35 [rcu_sched]root 9 0.0 0.0 0 0 ? I 10月18 0:00 [rcu_bh]root 10 0.0 0.0 0 0 ? S
-10月18 0:00 [migration/0]root 11 0.0 0.0 0 0 ? S 10月18 0:01 [watchdog/0]root 12 0.0 0.0 0 0 ? S 10月18 0:00 [cpuhp/0]root 13 0.0 0.0 0 0 ? S 10月18 0:00
-[cpuhp/1]
-
-首先ps命令我们是非常熟悉的了，就是列出当前的进程，grep命令我们也使用过，它是一种强大的文本搜索工具，它能使用正则表达式搜索文本，那么ps与grep命令之间的“|”符号是什么呢？它其实是一个管道，将ps命令输出的数据通过管道流向grep，其实在这里就打开了两个进程，ps命令本应该在终端输出信息的
-，但是它通过管道将输出的信息作为grep命令的输入信息，然后通过搜索之后将合适的信息显示出来，这样子就形成了我们在终端看到的信息。
-
-读者可以验证是否打开了两个进程，使用以下命令查看当前的进程情况，一定会在输出的最后打印两个进程相关的信息（ps、grep）：
-
-命令
-
-ps -ux \| grep $USER
-
-输出（在输出的最后）
-
-xxx 29663 0.0 0.0 29580 1460 pts/0 R+ 07:12 0:00 ps -ux
-
-xxx 29664 0.0 0.0 14888 1016 pts/0 S+ 07:12 0:00 grep --color=auto xxx
-
-什么是管道呢？当从一个进程连接数据流到另一个进程时，这就是一个管道（pipe）。我们通常是把一个进程的输出通过管道连接到另一个进程的输入。对于shell命令来说，命令的连接是通过管道字符来完成的，正如“ps -aux \| grep root”命令一样，只需要使用“|”字符进行连接即可。
-
-那么我们对这个“ps -aux \| grep root”命令进行详细的分析，它实际上就是执行以下过程：
-
--  shell负责安排两个命令的标准输入和标准输出。
-
--  ps的标准输入来自终端鼠标、键盘等。
-
--  ps的标准输出传递给grep，作为它的标准输入。
-
--  grep的标准输出连接到终端显示器屏幕时。
-
-shell所做的工作实际上是对标准输入和标准输出流进行了重新连接，使数据流从键盘输入通过两个命令最终输出到屏幕上，示意图具体见图 39‑1。
-
-|pipe002|
-
-图 39‑1 管道连接示意图
-
-其实，管道本质上是一个文件，图 39‑1过程可以看做是ps进程将输出的内容写入管道中，grep进程从管道中读取数据，这样子就是一个可读可写的文件，这其实也遵循了linux中“一切皆文件”的设计思想，因此linux系统直接把管道实现成了一种文件系统，借助VFS给应用程序提供操作接口。不过还是要注意的是
-：虽然管道的实现形态上是文件，但是管道本身并不占用磁盘或者其他外部存储的空间，它占用的是内存空间，因此linux上的管道就是一个操作方式为文件的内存缓冲区。
-
-管道的分类
-~~~~~
-
-Linux系统上的管道分两种类型：
-
--  匿名管道
-
--  命名管道
-
-这两种管道也叫做无名或有名管道，为了统一，作者还是使用匿名管道和有名管道。匿名管道最常见的形态就是我们在shell操作中最常用的”|”。它的特点是只能在父子进程中使用，父进程在产生子进程前必须打开一个管道文件，然后fork产生子进程，这样子进程通过拷贝父进程的进程地址空间获得同一个管道文件的描述符，
-以达到使用同一个管道通信的目的。此时除了父子进程外，没人知道这个管道文件的描述符，所以通过这个管道中的信息无法传递给其他进程。这保证了传输数据的安全性，当然也降低了管道了通用性，于是系统还提供了命名管道，它本质是一个文件，位于文件系统中，命名管道可以让多个无相关的进程进行通讯。
-
-匿名管道PIPE
-^^^^^^^^
-
-匿名管道（PIPE）是一种特殊的文件，但虽然它是一种文件，却没有名字，因此一般进程无法使用open()来获取他的描述符，它只能在一个进程中被创建出来，然后通过继承的方式将他的文件描述符传递给子进程，这就是为什么匿名管道只能用于亲缘关系进程间通信的原因。另外，
-匿名管道不同于一般文件的显著之处是：它有两个文件描述符，而不是一个，一个只能用来读，另一个只能用来写，这就是所谓的“半双工”通信方式。而且它对写操作不做任何保护，即：假如有多个进程或线程同时对 匿名管道进行写操作，那么这些 数据很有可能会相互践踏，因此一个简单的结论是：
-匿名管道只能用于一对一的亲缘进程通信。最后， 匿名管道不能使用 lseek()来进行所谓的定位，因为他们的数据不像普通文件那样按块的方式存放在诸如硬盘、 flash 等块设备上。
-
-总结来说，匿名管道有以下的特征：
-
-1. 没有名字，因此不能使用open()函数打开，但可以使用close()函数关闭。
-
-2. 只提供单向通信（半双工），也就是说，两个进程都能访问这个文件，假设进程1往文件内写东西，那么进程2 就只能读取文件的内容。
-
-3. 只能用于具有血缘关系的进程间通信，通常用于父子进程建通信 。
-
-4. 管道是基于字节流来通信的 。
-
-5. 依赖于文件系统，它的生命周期随进程的结束而结束。
-
-6. 写入操作不具有原子性，因此只能用于一对一的简单通信情形。
-
-7. 管道也可以看成是一种特殊的文件，对于它的读写也可以使用普通的 read()和 write()等函数。但是它又不是普通的文件，并不属于其他任何文件系统，并且只存在于内核的内存空间中，因此不能使用 lseek()来定位。
-
-命名管道FIFO
-^^^^^^^^
-
-命名管道（FIFO）与匿名管道（PIPE）是不同的，命名管道可以在多个无关的进程中交换数据（通信）。我们知道，匿名管道的通信方式通常都由一个共同的祖先进程启动，只能在“有血缘关系”的进程中交互数据，这给我们在不相关的的进程之间交换数据带来了不方便，因此产生了命名管道，来解决不相关进程间的通信问题。
-
-命名管道不同于无名管道之处在于它提供了一个路径名与之关联，以一个文件形式存在于文件系统中，这样，即使与命名管道的创建进程不存在“血缘关系”的进程，只要可以访问该命名管道文件的路径，就能够彼此通过
-命名管道相互通信，因为可以通过文件的形式，那么就可以调用系统中对文件的操作，如打开（open）、读（read）、写（write）、关闭（close）等函数，虽然命名管道文件存储在文件系统中，但数据却是存在于内存中的，这点要区分开。
-
-总结来说，命名管道有以下的特征：
-
-1. 有名字，存储于普通文件系统之中。
-
-2. 任何具有相应权限的进程都可以使用 open()来获取命名管道的文件描述符。
-
-3. 跟普通文件一样：使用统一的 read()/write()来读写。
-
-4. 跟普通文件不同：不能使用 lseek()来定位，原因是数据存储于内存中。
-
-5. 具有写入原子性，支持多写者同时进行写操作而数据不会互相践踏。
-
-6. 遵循先进先出（First In First Out）原则，最先被写入 FIFO 的数据，最先被读出来。
-
-pipe()函数
-~~~~~~~~
-
-pipe()函数用于创建一个匿名管道，一个可用于进程间通信的单向数据通道。我们可以通过man命令查看pipe函数的相关介绍：
-
-命令
-
-man pipe
-
-输出（已删减）
-
-头文件
-
-#include <unistd.h>
-
-函数原型
-
-int pipe(int pipefd[2]);
-
-函数原型非常简单，没有任何的传入参数，注意：数组pipefd是用于返回两个引用管道末端的文件描述符，它是一个由两个整数类型的文件描述符组成的数组的指针。 pipefd [0] 指管道的读取端， pipefd
-[1]指向管道的写端。向管道的写入端写入数据将会由内核缓冲，即写入内存中，直到从管道的读取端读取数据为止，而且数据遵循先进先出原则。pipe()函数还会返回一个int类型的变量，如果为0则表示创建匿名管道成功，如果为-1则表示创建失败，并且设置errno。
-
-匿名管道创建成功以后，创建该匿名管道的进程（父进程）同时掌握着管道的读取端和写入端，但是想要父子进程间有数据交互，则需要以下操作：
-
-1. 父进程调用pipe()函数创建匿名管道，得到两个文件描述符pipefd [0]、pipefd [1]，分别指向管道的读取端和写入端。
-
-2. 父进程调用fork()函数启动（创建）一个子进程，那么子进程将从父进程中继承这两个文件描述符pipefd [0]、pipefd [1]，它们指向同一匿名管道的读取端与写入端。
-
-3. 由于匿名管道是利用环形队列实现的，数据将从写入端流入管道，从读取端流出，这样子就实现了进程间通信，但是这个匿名管道此时有两个读取端与两个写入端，示意图如图 39‑2所示，因此需要进行接下来的操作。
-
-4. 如果想要从父进程将数据传递给子进程，则父进程需要关闭读取端，子进程关闭写入端，示意图如图 39‑3所示。
-
-5. 如果想要从子进程将数据传递给父进程，则父进程需要关闭写入端，子进程关闭读取端，示意图如图 39‑4所示。
-
-6. 当不需要管道的时候，就在进程中将未关闭的一端关闭即可。
-
-|pipe003|
-
-图 39‑2 fork()后子进程继承父进程文件描述符
-
-|pipe004|
-
-图 39‑3 数据从父进程流向子进程
-
-|pipe005|
-
-图 39‑4 数据从子进程流向父进程
-
-我们可以使用pipe()函数做一个测试实验，野火资料提供了对应的实验代码，在application/pipe目录下存在pipe.c文件，该文件内容如代码清单 39‑1所示。
-
-代码清单 39‑1 pipe.c源码文件内容
-
-1 #include <unistd.h>
-
-2 #include <sys/types.h>
-
-3 #include <sys/wait.h>
-
-4 #include <errno.h>
-
-5 #include <stdio.h>
-
-6 #include <stdlib.h>
-
-7 #include <string.h>
-
-8
-
-9 #define MAX_DATA_LEN 256
-
-10 #define DELAY_TIME 1
-
-11
-
-12 int main()
-
-13 {
-
-14 pid_t pid;
-
-15 int pipe_fd[2]; **(1)**
-
-16 char buf[MAX_DATA_LEN];
-
-17 const char data[] = "Pipe Test Program";
-
-18 int real_read, real_write;
-
-19
-
-20 memset((void*)buf, 0, sizeof(buf));
-
-21
-
-22 /\* 创建管道 \*/
-
-23 if (pipe(pipe_fd) < 0) { **(2)**
-
-24 printf("pipe create error\n");
-
-25 exit(1);
-
-26 }
-
-27
-
-28 /\* 创建一子进程 \*/
-
-29 if ((pid = fork()) == 0) { **(3)**
-
-30 /\* 子进程关闭写描述符，并使子进程暂停 3s 等待父进程已关闭相应的读描述符 \*/
-
-31 close(pipe_fd[1]);
-
-32 sleep(DELAY_TIME \* 3);
-
-33
-
-34 /\* 子进程读取管道内容 \*/ **(4)**
-
-35 if ((real_read = read(pipe_fd[0], buf, MAX_DATA_LEN)) > 0) {
-
-36 printf("%d bytes read from the pipe is '%s'\n", real_read, buf);
-
-37 }
-
-38
-
-39 /\* 关闭子进程读描述符 \*/
-
-40 close(pipe_fd[0]); **(5)**
-
-41
-
-42 exit(0);
-
-43 }
-
-44
-
-45 else if (pid > 0) {
-
-46 /\* 父进程关闭读描述符，并通过使父进程暂停 1s 等待子进程已关闭相应的写描述符 \*/
-
-47 close(pipe_fd[0]); **(6)**
-
-48
-
-49 sleep(DELAY_TIME);
-
-50 **(7)**
-
-51 if ((real_write = write(pipe_fd[1], data, strlen(data))) != -1) {
-
-52 printf("Parent write %d bytes : '%s'\n", real_write, data);
-
-53 }
-
-54
-
-55 /*关闭父进程写描述符*/
-
-56 close(pipe_fd[1]); **(8)**
-
-57
-
-58 /*收集子进程退出信息*/
-
-59 waitpid(pid, NULL, 0); **(9)**
-
-60
-
-61 exit(0);
-
-62 }
-
-63 }
-
-代码清单 39‑1\ **(1)**\ ：定义一个数组pipe_fd，在创建匿名管道后通过数组返回管道的文件描述符。
-
-代码清单 39‑1\ **(2)**\ ：调用pipe()创建一个匿名管道，创建成功则得到两个文件描述符pipe_fd[0]、pipe_fd[1]，否则返回-1。
-
-代码清单 39‑1\ **(3)**\ ：调用fork()创建一个子进程，如果返回值是0则表示此时运行的是子进程，那么在子进程中调用close()函数关闭写描述符，并使子进程睡眠 3s 等待父进程已关闭相应的读描述符。
-
-代码清单 39‑1\ **(4)**\ ：子进程调用read()函数读取管道内容，如果管道没有数据则子进程将被阻塞，读取到数据就将数据打印出来。
-
-代码清单 39‑1\ **(5)**\ ：调用close()函数关闭子进程读描述符。
-
-代码清单 39‑1\ **(6)**\ ：如果fork()函数的返回值大于0，则表示此时运行的是父进程，那么在父进程中先调用close()关闭管道的读描述符，并且等待1s，因为此时可能子进程先于父进程运行，暂且等待一会。
-
-代码清单 39‑1\ **(7)**\ ：父进程调用write()函数将数据写入管道。
-
-代码清单 39‑1\ **(8)**\ ：关闭父进程写描述符。
-
-代码清单 39‑1\ **(9)**\ ：调用waitpid()函数收集子进程退出信息并退出进程。
-
-我们使用make命令编译，然后运行“targets”程序，其运行结果如图 39‑5所示：
-
-|pipe006|
-
-图 39‑5 pipe()函数测试结果
-
-我们再深入学习一下pipe管道的一些知识吧，比如：当没有数据可读时，调用read()函数读取数据时通常会阻塞，即它将暂停进程来等待直到有数据到达为止。但如果管道的另一端已被关闭，也就是说，已经没有进程打开这个管道并向它写数据了，这时调用read()函数如果会阻塞的话，就没有意义，因为这个进程永远不会
-等待到数据，这也是匿名管道的一个特性，它只能在创建时返回对应的文件描述符，而无法在关闭文件描述符后后再通过open()这类函数打开，因此对一个已关闭写数据的管道做read()调用将返回0而不是阻塞。这就使读进程能够像检测文件结束一样，对管道进行检测并作出相应的动作。注意，这与read()函数读取一个
-无效的文件描述符不同， read()函数会把无效的文件描述符看作一个错误并返回-1。
-
-fifo()函数
-~~~~~~~~
-
-至此，我们还只能在有“血缘关系”的程序之间传递数据，即这些程序是由一个共同的祖先进程启动的。但如果我们想在不相关的进程之间交换数据，这还不是很方便，我们可以用FIFO文件来完成这项工作，或者称之为命名管道。命名管道是一种特殊类型的文件，它在文件系统中以文件名的形式存在，但它的的数据却是存储在内存中的
-。我们可以在终端（命令行）上创建命名管道，也可以在程序中创建它。
-
-比如使用
-
-.. |pipe002| image:: media/pipe002.png
-   :width: 5.76806in
-   :height: 1.89043in
-.. |pipe003| image:: media/pipe003.png
-   :width: 5.76806in
-   :height: 3.97056in
-.. |pipe004| image:: media/pipe004.png
-   :width: 5.76806in
-   :height: 4.00706in
-.. |pipe005| image:: media/pipe005.png
-   :width: 5.76806in
-   :height: 4.24902in
-.. |pipe006| image:: media/pipe006.png
-   :width: 5.76806in
-   :height: 2.49682in
diff --git a/documentation/system_programing/pipe.rst b/documentation/system_programing/pipe.rst
new file mode 100644
index 0000000000000000000000000000000000000000..5f6f6c3fd40aef43c314551244ffe61af8f7caf1
--- /dev/null
+++ b/documentation/system_programing/pipe.rst
@@ -0,0 +1,533 @@
+.. vim: syntax=rst
+
+管道
+====
+
+管道的基本概念
+--------------
+
+在进入正式的学习之前，想一想管道为什么叫管道，也想一想生活中有什么跟管道相关的？比如水管，水通过水管从一端流向另一端，那么进程间通信是不是可以模仿这种"流向"的关系呢，很显然是可以的，数据可以从一个进程流向另一个进程，那么一个进程产生数据，然后通过管道发送给另一个进程，另一个进程读取到数据，这样一来就实现了进程间的通信了。
+
+在上一章中，我们学过信号，一个信号从进程中产生，发送给另一个进程，这其实也是信号类型的通信，只传递信号值，而没有数据传递，就会在很多时候无法满足我们的需求，因此管道的传输数据功能就会在某些场合非常适用。
+
+我们可以首先做个试验，在终端中使用以下命：
+
+**命令**
+
+.. code:: bash
+
+    ps -aux | grep root
+
+
+    # 输出
+
+    root         1  0.0  0.0 225376  6376 ?  Ss   10月18   0:31 /sbin/init
+    root         2  0.0  0.0      0     0 ?         S    10月18   0:00 [kthreadd]
+    root         4  0.0  0.0      0     0 ?         I<   10月18   0:00 [kworker/0:0H]
+    root         6  0.0  0.0      0     0 ?         I<   10月18   0:00 [mm_percpu_wq]
+    root         7  0.0  0.0      0     0 ?         S    10月18   0:02 [ksoftirqd/0]
+    root         8  0.0  0.0      0     0 ?         I    10月18    5:35 [rcu_sched]
+    root         9  0.0  0.0      0     0 ?         I    10月18    0:00 [rcu_bh]
+    root        10  0.0  0.0      0     0 ?         S    10月18   0:00 [migration/0]
+    root        11  0.0  0.0      0     0 ?         S    10月18   0:01 [watchdog/0]
+    root        12  0.0  0.0      0     0 ?         S    10月18   0:00 [cpuhp/0]
+    root        13  0.0  0.0      0     0 ?         S    10月18   0:00 [cpuhp/1]
+
+首先ps命令我们是非常熟悉的了，就是列出当前的进程，grep命令我们也使用过，它是一种强大的文本搜索工具，它能使用正则表达式搜索文本，那么ps与grep命令之间的"\|"符号是什么呢？它其实是一个管道，将ps命令输出的数据通过管道流向grep，其实在这里就打开了两个进程，ps命令本应该在终端输出信息的，但是它通过管道将输出的信息作为grep命令的输入信息，然后通过搜索之后将合适的信息显示出来，这样子就形成了我们在终端看到的信息。
+
+读者可以验证是否打开了两个进程，使用以下命令查看当前的进程情况，一定会在输出的最后打印两个进程相关的信息（ps、grep）：
+
+命令
+
+.. code:: bash
+
+    ps -ux | grep $USER
+
+
+    # 输出（在输出的最后）
+
+    xxx 29663 0.0 0.0 29580 1460 pts/0 R+ 07:12 0:00 ps -ux
+
+    xxx 29664 0.0 0.0 14888 1016 pts/0 S+ 07:12 0:00 grep --color=auto xxx
+
+什么是管道呢？当从一个进程连接数据流到另一个进程时，这就是一个管道（pipe）。我们通常是把一个进程的输出通过管道连接到另一个进程的输入。对于shell命令来说，命令的连接是通过管道字符来完成的，正如" ``ps -aux | grep root`` "命令一样，只需要使用"\|"字符进行连接即可。
+
+那么我们对这个"ps -aux \| grep
+root"命令进行详细的分析，它实际上就是执行以下过程：
+
+-  shell负责安排两个命令的标准输入和标准输出。
+-  ps的标准输入来自终端鼠标、键盘等。
+-  ps的标准输出传递给grep，作为它的标准输入。
+-  grep的标准输出连接到终端显示器屏幕时。
+
+shell所做的工作实际上是对标准输入和标准输出流进行了重新连接，使数据流从键盘输入通过两个命令最终输出到屏幕上，示意图具体见图
+39‑1。
+
+.. figure:: media/pipe002.png
+   :alt: pipe002
+
+   pipe002
+
+图 39‑1 管道连接示意图
+
+其实，管道本质上是一个文件，图39‑1过程可以看做是ps进程将输出的内容写入管道中，grep进程从管道中读取数据，这样子就是一个可读可写的文件，这其实也遵循了Linux中"一切皆文件"的设计思想，因此Linux系统直接把管道实现成了一种文件系统，借助VFS给应用程序提供操作接口。不过还是要注意的是：虽然管道的实现形态上是文件，但是管道本身并不占用磁盘或者其他外部存储的空间，它占用的是内存空间，因此Linux上的管道就是一个操作方式为文件的内存缓冲区。
+
+管道的分类
+----------
+
+Linux系统上的管道分两种类型：
+
+-  匿名管道
+-  命名管道
+
+这两种管道也叫做无名或有名管道，为了统一，作者还是使用匿名管道和命名管道。匿名管道最常见的形态就是我们在shell操作中最常用的"\|"。它的特点是只能在父子进程中使用，父进程在产生子进程前必须打开一个管道文件，然后fork产生子进程，这样子进程通过拷贝父进程的进程地址空间获得同一个管道文件的描述符，以达到使用同一个管道通信的目的。此时除了父子进程外，没人知道这个管道文件的描述符，所以通过这个管道中的信息无法传递给其他进程。这保证了传输数据的安全性，当然也降低了管道了通用性，于是系统还提供了命名管道，它本质是一个文件，位于文件系统中，命名管道可以让多个无相关的进程进行通讯。
+
+匿名管道PIPE
+~~~~~~~~~~~~
+
+匿名管道（PIPE）是一种特殊的文件，但虽然它是一种文件，却没有名字，因此一般进程无法使用open()来获取他的描述符，它只能在一个进程中被创建出来，然后通过继承的方式将他的文件描述符传递给子进程，这就是为什么匿名管道只能用于亲缘关系进程间通信的原因。另外，匿名管道不同于一般文件的显著之处是：它有两个文件描述符，而不是一个，一个只能用来读，另一个只能用来写，这就是所谓的"半双工"通信方式。而且它对写操作不做任何保护，即：假如有多个进程或线程同时对匿名管道进行写操作，那么这些数据很有可能会相互践踏，因此一个简单的结论是：匿名管道只能用于一对一的亲缘进程通信。最后，
+匿名管道不能使用lseek()来进行所谓的定位，因为他们的数据不像普通文件那样按块的方式存放在诸如硬盘、flash
+等块设备上。
+
+总结来说，匿名管道有以下的特征：
+
+1. 没有名字，因此不能使用open()函数打开，但可以使用close()函数关闭。
+2. 只提供单向通信（半双工），也就是说，两个进程都能访问这个文件，假设进程1往文件内写东西，那么进程2
+   就只能读取文件的内容。
+3. 只能用于具有血缘关系的进程间通信，通常用于父子进程建通信 。
+4. 管道是基于字节流来通信的 。
+5. 依赖于文件系统，它的生命周期随进程的结束而结束。
+6. 写入操作不具有原子性，因此只能用于一对一的简单通信情形。
+7. 管道也可以看成是一种特殊的文件，对于它的读写也可以使用普通的read()和write()等函数。但是它又不是普通的文件，并不属于其他任何文件系统，并且只存在于内核的内存空间中，因此不能使用lseek()来定位。
+
+命名管道FIFO
+~~~~~~~~~~~~
+
+命名管道（FIFO）与匿名管道（PIPE）是不同的，命名管道可以在多个无关的进程中交换数据（通信）。我们知道，匿名管道的通信方式通常都由一个共同的祖先进程启动，只能在"有血缘关系"的进程中交互数据，这给我们在不相关的的进程之间交换数据带来了不方便，因此产生了命名管道，来解决不相关进程间的通信问题。
+
+命名管道不同于无名管道之处在于它提供了一个路径名与之关联，以一个文件形式存在于文件系统中，这样，即使与命名管道的创建进程不存在"血缘关系"的进程，只要可以访问该命名管道文件的路径，就能够彼此通过命名管道相互通信，因为可以通过文件的形式，那么就可以调用系统中对文件的操作，如打开（open）、读（read）、写（write）、关闭（close）等函数，虽然命名管道文件存储在文件系统中，但数据却是存在于内存中的，这点要区分开。
+
+总结来说，命名管道有以下的特征：
+
+1. 有名字，存储于普通文件系统之中。
+2. 任何具有相应权限的进程都可以使用 open()来获取命名管道的文件描述符。
+3. 跟普通文件一样：使用统一的 read()/write()来读写。
+4. 跟普通文件不同：不能使用 lseek()来定位，原因是数据存储于内存中。
+5. 具有写入原子性，支持多写者同时进行写操作而数据不会互相践踏。
+6. 遵循先进先出（First In First Out）原则，最先被写入 FIFO
+   的数据，最先被读出来。
+
+pipe()函数
+----------
+
+pipe()函数用于创建一个匿名管道，一个可用于进程间通信的单向数据通道。我们可以通过man命令查看pipe函数的相关介绍：
+
+**命令**
+
+.. code:: bash
+
+    man pipe
+
+**头文件**
+
+.. code:: c
+
+    #include <unistd.h>
+
+**函数原型**
+
+.. code:: c
+
+    int pipe(int pipefd[2]);
+
+函数原型非常简单，没有任何的传入参数，注意：数组pipefd是用于返回两个引用管道末端的文件描述符，它是一个由两个整数类型的文件描述符组成的数组的指针。pipefd
+[0] 指管道的读取端，
+pipefd[1]指向管道的写端。向管道的写入端写入数据将会由内核缓冲，即写入内存中，直到从管道的读取端读取数据为止，而且数据遵循先进先出原则。pipe()函数还会返回一个int类型的变量，如果为0则表示创建匿名管道成功，如果为-1则表示创建失败，并且设置errno。
+
+匿名管道创建成功以后，创建该匿名管道的进程（父进程）同时掌握着管道的读取端和写入端，但是想要父子进程间有数据交互，则需要以下操作：
+
+1. 父进程调用pipe()函数创建匿名管道，得到两个文件描述符pipefd[0]、pipefd
+   [1]，分别指向管道的读取端和写入端。
+2. 父进程调用fork()函数启动（创建）一个子进程，那么子进程将从父进程中继承这两个文件描述符pipefd[0]、pipefd
+   [1]，它们指向同一匿名管道的读取端与写入端。
+3. 由于匿名管道是利用环形队列实现的，数据将从写入端流入管道，从读取端流出，这样子就实现了进程间通信，但是这个匿名管道此时有两个读取端与两个写入端，示意图如图39‑2所示，因此需要进行接下来的操作。
+4. 如果想要从父进程将数据传递给子进程，则父进程需要关闭读取端，子进程关闭写入端，示意图如图39‑3所示。
+5. 如果想要从子进程将数据传递给父进程，则父进程需要关闭写入端，子进程关闭读取端，示意图如图39‑4所示。
+6. 当不需要管道的时候，就在进程中将未关闭的一端关闭即可。
+
+.. figure:: media/pipe003.png
+   :alt: pipe003
+
+   pipe003
+
+图 39‑2 fork()后子进程继承父进程文件描述符
+
+.. figure:: media/pipe004.png
+   :alt: pipe004
+
+   pipe004
+
+图 39‑3 数据从父进程流向子进程
+
+.. figure:: media/pipe005.png
+   :alt: pipe005
+
+   pipe005
+
+图 39‑4 数据从子进程流向父进程
+
+我们可以使用pipe()函数做一个测试实验，野火资料提供了对应的实验代码，在system_programing/pipe目录下存在pipe.c文件，该文件内容如代码清单39‑1所示。
+
+代码清单 39‑1 pipe.c源码文件内容
+
+.. code:: c
+
+    #include <unistd.h>
+    #include <sys/types.h>
+    #include <sys/wait.h>
+    #include <errno.h>
+    #include <stdio.h>
+    #include <stdlib.h>
+    #include <string.h>
+
+    #define MAX_DATA_LEN 256
+    #define DELAY_TIME 1
+
+    int main()
+    {
+        pid_t pid;
+        int pipe_fd[2];                             //(1)
+        char buf[MAX_DATA_LEN];
+        const char data[] = "Pipe Test Program";
+        int real_read, real_write;
+
+        memset((void*)buf, 0, sizeof(buf));
+
+        /* 创建管道 */
+        if (pipe(pipe_fd) < 0)                  //(2)
+        {
+            printf("pipe create error\n");
+            exit(1);
+        }
+
+        /* 创建一子进程 */
+        if ((pid = fork()) == 0)                //(3)
+        {
+            /* 子进程关闭写描述符，并通过使子进程暂停 3s 等待父进程已关闭相应的读描述符 */
+            close(pipe_fd[1]);
+            sleep(DELAY_TIME * 3);
+
+            /* 子进程读取管道内容 */            //(4)
+            if ((real_read = read(pipe_fd[0], buf, MAX_DATA_LEN)) > 0)
+            {
+                printf("%d bytes read from the pipe is '%s'\n", real_read, buf);
+            }
+
+            /* 关闭子进程读描述符 */
+            close(pipe_fd[0]);                  //(5)
+
+            exit(0);
+        }
+        
+        else if (pid > 0)                      
+        {
+            /* 父进程关闭读描述符，并通过使父进程暂停 1s 等待子进程已关闭相应的写描述符 */
+            close(pipe_fd[0]);                  //(6)
+
+            sleep(DELAY_TIME);
+
+            if((real_write = write(pipe_fd[1], data, strlen(data))) != -1)  //(7)
+            {
+                printf("Parent write %d bytes : '%s'\n", real_write, data);
+            }
+            
+            /*关闭父进程写描述符*/
+            close(pipe_fd[1]);                  //(8)
+
+            /*收集子进程退出信息*/
+            waitpid(pid, NULL, 0);              //(9)
+
+            exit(0);
+        }
+    }
+
+代码清单39‑1
+**(1)** ：定义一个数组pipe_fd，在创建匿名管道后通过数组返回管道的文件描述符。
+
+代码清单39‑1
+**(2)** ：调用pipe()创建一个匿名管道，创建成功则得到两个文件描述符pipe_fd[0]、pipe_fd[1]，否则返回-1。
+
+代码清单39‑1
+**(3)** ：调用fork()创建一个子进程，如果返回值是0则表示此时运行的是子进程，那么在子进程中调用close()函数关闭写描述符，并使子进程睡眠
+3s 等待父进程已关闭相应的读描述符。
+
+代码清单39‑1
+**(4)** ：子进程调用read()函数读取管道内容，如果管道没有数据则子进程将被阻塞，读取到数据就将数据打印出来。
+
+代码清单39‑1 **(5)** ：调用close()函数关闭子进程读描述符。
+
+代码清单39‑1
+**(6)** ：如果fork()函数的返回值大于0，则表示此时运行的是父进程，那么在父进程中先调用close()关闭管道的读描述符，并且等待1s，因为此时可能子进程先于父进程运行，暂且等待一会。
+
+代码清单 39‑1 **(7)** ：父进程调用write()函数将数据写入管道。
+
+代码清单 39‑1 **(8)** ：关闭父进程写描述符。
+
+代码清单 39‑1 **(9)** ：调用waitpid()函数收集子进程退出信息并退出进程。
+
+我们使用make命令编译，然后运行"targets"程序，其运行结果如图 39‑5所示：
+
+.. figure:: media/pipe006.png
+   :alt: pipe006
+
+   pipe006
+
+图 39‑5 pipe()函数测试结果
+
+我们再深入学习一下pipe管道的一些知识吧，比如：当没有数据可读时，调用read()函数读取数据时通常会阻塞，即它将暂停进程来等待直到有数据到达为止。但如果管道的另一端已被关闭，也就是说，已经没有进程打开这个管道并向它写数据了，这时调用read()函数如果会阻塞的话，就没有意义，因为这个进程永远不会等待到数据，这也是匿名管道的一个特性，它只能在创建时返回对应的文件描述符，而无法在关闭文件描述符后后再通过open()这类函数打开，因此对一个已关闭写数据的管道做read()调用将返回0而不是阻塞。这就使读进程能够像检测文件结束一样，对管道进行检测并作出相应的动作。注意，这与read()函数读取一个无效的文件描述符不同，read()函数会把无效的文件描述符看作一个错误并返回-1。
+
+fifo()函数
+----------
+
+至此，我们还只能在有"血缘关系"的程序之间传递数据，即这些程序是由一个共同的祖先进程启动的。但如果我们想在不相关的进程之间交换数据，这还不是很方便，我们可以用FIFO文件来完成这项工作，或者称之为命名管道。命名管道是一种特殊类型的文件，它在文件系统中以文件名的形式存在，但它的的数据却是存储在内存中的。我们可以在终端（命令行）上创建命名管道，也可以在程序中创建它。
+
+比如使用mkfifo命令去创建一个命名管道，此时会创建一个命名管道文件test（Linux一切皆文件）：
+
+.. code:: bash
+
+    mkfifo test
+
+关于mkfifo命令，我们可以使用man命令查看一下它的描述：
+
+.. code:: bash
+
+    man mkfifo
+
+    # 输出
+    名称
+           mkfifo - 创建 FIFO（命名管道）
+
+    概述
+           mkfifo [选项]... 名称...
+
+    描述
+           使用给定的名称创建命名管道（FIFO）。
+
+           必选参数对长短选项同时适用。
+
+           -m, --mode=模式
+                  将文件权限位设置为给定的模式（类似 chmod），而不是类似 a=rw 这样
+
+           -Z     将 SELinux 安全上下文设置为默认类型
+
+           --context[=CTX]
+                  类似 -Z，或者如果指定了上下文，则将 SELinux 或者 SMACK 安全上下文设置为指定类型
+
+           --help 显示此帮助信息并退出
+
+我们创建了一个命名管道，也可以通过file命令去看一下这个test文件的类型：
+
+.. code:: bash
+
+    file test
+
+    test: fifo (named pipe)
+
+    # 可以看出它是一个命名管道类型的文件
+
+当然了，上面说说的都是终端的命令——mkfifo，当然还有系统调用函数，很巧的是，这个函数也叫这个名字——mkfifo，这个函数的作用就是创建一个命名管道，其实就类似于创建一个文件，只不过这个文件的类型是命名管道的类型。
+
+mkfifo()会根据参数pathname建立特殊的FIFO文件，而参数mode为该文件的模式与权限。mkfifo()创建的FIFO文件其他进程都可以进行读写操作，可以使用读写一般文件的方式操作它，如open，read，write，close等。
+
+一个进程对管道进行读操作时： - 若该管道是阻塞打开，且当前 FIFO
+内没有数据，则对读进程而言将一直阻塞到有数据写入。 -
+若该管道是非阻塞打开，则不论 FIFO
+内是否有数据，读进程都会立即执行读操作。即如果
+FIFO内没有数据，则读函数将立刻返回 0。
+
+一个进程对管道进行写操作时： -
+若该管道是阻塞打开，则写操作将一直阻塞到数据可以被写入。 -
+若该管道是非阻塞打开而不能写入全部数据，则读操作进行部分写入或者调用失败
+
+**函数原型**
+
+.. code:: c
+
+    int mkfifo(const char * pathname,mode_t mode);
+
+**函数传入值 mode：** - O_RDONLY：读管道。 - O_WRONLY：写管道。 -
+O_RDWR：读写管道。 - O_NONBLOCK：非阻塞。 -
+O_CREAT：如果该文件不存在，那么就创建一个新的文件，并用第三个参数为其设置权限。
+- O_EXCL：如果使用 O_CREAT
+时文件存在，那么可返回错误消息。这一参数可测试文件是否存在。
+
+**函数返回值：** - 0：成功 - EACCESS：参数 filename
+所指定的目录路径无可执行的权限。 - EEXIST：参数 filename
+所指定的文件已存在。 - ENAMETOOLONG：参数 filename 的路径名称太长。 -
+ENOENT：参数 filename 包含的目录不存在。 -
+ENOSPC：文件系统的剩余空间不足。 - ENOTDIR：参数 filename
+路径中的目录存在但却非真正的目录。 - EROFS：参数 filename
+指定的文件存在于只读文件系统内。
+
+下面我们来看看具体的实例：
+
+.. code:: c
+
+    #include <sys/wait.h>
+    #include <sys/types.h>
+    #include <sys/stat.h>
+    #include <unistd.h>
+    #include <errno.h>
+    #include <fcntl.h>
+    #include <stdio.h>
+    #include <stdlib.h>
+    #include <limits.h>
+    #include <string.h>
+
+
+    #define MYFIFO "myfifo"    /* 命名管道文件名*/
+
+    #define MAX_BUFFER_SIZE PIPE_BUF /* 4096 定义在于 limits.h 中*/
+
+
+    void fifo_read(void)
+    {
+        char buff[MAX_BUFFER_SIZE];
+        int fd;
+        int nread;
+
+        printf("***************** read fifo ************************\n");
+        /* 判断命名管道是否已存在，若尚未创建，则以相应的权限创建*/
+        if (access(MYFIFO, F_OK) == -1)                 //(4)
+        {
+            if ((mkfifo(MYFIFO, 0666) < 0) && (errno != EEXIST))    //(5)
+            {
+                printf("Cannot create fifo file\n");
+                exit(1);
+            }
+        }
+
+        /* 以只读阻塞方式打开命名管道 */
+        fd = open(MYFIFO, O_RDONLY);                //(6)
+        if (fd == -1)
+        {
+            printf("Open fifo file error\n");
+            exit(1);
+        }
+
+        memset(buff, 0, sizeof(buff));
+
+        if ((nread = read(fd, buff, MAX_BUFFER_SIZE)) > 0)      // (7)
+        {
+            printf("Read '%s' from FIFO\n", buff);
+        }
+
+       printf("***************** close fifo ************************\n");
+
+        close(fd);                              //(8)
+
+        exit(0);
+    }
+
+
+    void fifo_write(void)
+    {
+        int fd;
+        char buff[] = "this is a fifo test demo";
+        int nwrite;
+
+        sleep(2);   //等待子进程先运行              //(9)
+
+        /* 以只写阻塞方式打开 FIFO 管道 */
+        fd = open(MYFIFO, O_WRONLY | O_CREAT, 0644);        //(10)
+        if (fd == -1)
+        {
+            printf("Open fifo file error\n");
+            exit(1);
+        }
+
+        printf("Write '%s' to FIFO\n", buff);
+
+        /*向管道中写入字符串*/
+        nwrite = write(fd, buff, MAX_BUFFER_SIZE);          //(11)
+
+        if(wait(NULL))  //等待子进程退出
+        {
+            close(fd);                          //(12)
+            exit(0);
+        }
+
+    }
+
+
+    int main()
+    {
+        pid_t result;
+        /*调用 fork()函数*/
+        result = fork();                //(1)
+
+        /*通过 result 的值来判断 fork()函数的返回情况，首先进行出错处理*/
+        if(result == -1)
+        {
+            printf("Fork error\n");
+        }
+
+
+        else if (result == 0) /*返回值为 0 代表子进程*/
+        {
+            fifo_read();            //(2)
+        }
+
+        else /*返回值大于 0 代表父进程*/
+        {
+            fifo_write();       //(3)
+        }
+
+        return result;
+    }
+
+下面介绍这个例子的流程，我们先从main函数开始：
+
+**(1):** 首先使用fork函数创建一个子进程。 **(2):** 返回值为 0
+代表子进程，就运行fifo_read()函数。 **(3):** 返回值大于 0
+代表父进程，就运行fifo_write()函数。 **(4):**
+在子进程中先通过access()函数判断命名管道是否已存在，若尚未创建，则以相应的权限创建
+**(5):** 调用mkfifo()函数创建一个命名管道。 **(6):**
+使用open()函数以只读阻塞方式打开命名管道。 **(7):**
+使用read()函数读取管道的内容，由于打开的管道是阻塞的，而此时管道中没有存在任何数据，因此子进程会阻塞在这里，等待到管道中有数据时才恢复运行，并打印从管道中读取到的数据。
+**(8):** 读取完毕，使用close()函数关闭管道。 **(9):**
+父进程休眠2秒，等待子进程先运行，因为是需要在子进程中创建管道的。
+**(10):** 以只写阻塞方式打开 FIFO 管道。 **(11):**
+向管道中写入字符串数据，当写入后管道中就存在数据了，此时处于阻塞的子进程将恢复运行，并将字符串数据打印出来。
+**(12):** 等待子进程退出，并且关闭管道。
+
+这个例子在 ``system_programing/fifo`` 目录下，我们直接make编译后即可得到一个可执行文件，然后运行该文件即可。
+
+.. code:: bash
+
+    ➜  application cd fifo 
+
+    ➜  fifo make
+
+    gcc -o fifo.o -c -g -Werror -I. -Iinclude -static fifo.c -g -MD -MF .fifo.o.d
+    gcc -o targets fifo.o -g -Werror -I. -Iinclude -static
+
+    ➜  fifo ./targets 
+    ***************** read fifo ************************
+    Write 'this is a fifo test demo' to FIFO
+    Read 'this is a fifo test demo' from FIFO
+    ***************** close fifo ************************
+
+前面的例子是两个进程之间的通信问题（例子中使用了父子进程，但即使是没有"血缘关系"的进程也是一样的操作），也就是说，一个进程向FIFO文件写数据，而另一个进程则在FIFO文件中读取数据。大家可以试想这样一个问题，只使用一个FIFO文件，如果有多个进程同时向同一个FIFO文件写数据，而只有一个读FIFO进程在同一个FIFO文件中读取数据时，会发生怎么样的情况呢？大家是不是会觉得数据相互交错混乱？如果不做任何处理，的确会这样子，但FIFO
+跟 PIPE 区别的还有一个最大的不同点在于: FIFO
+是具有写原子特性的，就是让写操作的原子化，怎样才能使写操作原子化呢？答案很简单，系统规定：在一个以O_WRONLY（即阻塞方式）打开的FIFO中，
+如果写入的数据长度小于等待PIPE_BUF，那么或者写入全部字节，或者一个字节都不写入。如果所有的写请求都是发往一个阻塞的FIFO的，并且每个写记请求的数据长度小于等于PIPE_BUF字节，系统就可以确保数据决不会交错在一起。这种特性使得我们可以同时对
+FIFO 进行写操作而不怕数据遭受破坏。
+
+说了那么多，FIFO的应用场景是什么呢？一个典型应用是Linux
+的日志系统。系统的日志信息被统一安排存放在/var/log目录下，这些日志文件都是一些普通的文本文件，在Linux系统中普通的文件可以被一个或多个进程重读多次打开，每次打开都有一个独立的位置偏移量，如果多个进程或线程同时写文件，那么除非他们之间能相互协调好，否则必然导致混乱。可惜需要写日志的进程根本不可能"协调好"，由于写日志的进程是毫无关联的，因此常用的互斥手段(比如什么互斥锁、信号量等)是无法起作用的，就像你无法试图通过交通法规来杜绝有人乱闯红灯一样，因为总有人可以故意无视规则，肆意践踏规则，如何使得毫不相干的不同进程的日志信息都能完整地输送到日志文件中而不相互破坏，是一个必须要解决的问题，一个简单高效的方案是：使用
+FIFO 来接收各个不相干进程的日志信息，然后让一个进程专门将 FIFO
+中的数据写到相应的日志文件当中。这样做的好处是，任何进程无需对日志信息的互斥编写出任何额外的代码，只管往
+FIFO
+里面写入即可。后台默默耕耘的日志系统服务例程会将这些信息一一地拿出来再写入日志文件，FIFO
+的写入原子性保证了数据的完整无缺。
diff --git a/documentation/system_programing/posix_mutex.rst b/documentation/system_programing/posix_mutex.rst
new file mode 100644
index 0000000000000000000000000000000000000000..21a9e5c6e36cfce1badb7b235585f639f9e7f9af
--- /dev/null
+++ b/documentation/system_programing/posix_mutex.rst
@@ -0,0 +1,324 @@
+POSIX 互斥锁
+============
+
+互斥锁的基本概念
+----------------
+
+在前面的信号量章节，我们也了解过互斥这个概念，就是当不同进程/线程去访问某个临界资源的时候，就需要进行互斥保护，这种互斥保护可以看做是一种锁机制，就好比当你去上厕所的时候，你会锁住门，不让别人进来。在Linux系统中的锁机制是一个比较广泛的概念，而且锁的种类很多，包括互斥锁，文件锁，读写锁等等。。。其实信号量也是一种锁，可以使用锁的目的是达到互斥的作用，使共享资源在同一时间内，只有能有一个进程或者线程对他进行操作。整个系统拥有很多临界资源，比如某些全局性的文件，硬件接口等，但整个Linux系统可以完美运行，这无不依赖锁机制，可以说锁机制是Linux整个系统的精髓所在，Linux内核都是围绕着同步在运转，它决定了进程/线程什么时候可以访问这个临界资源，在多进程和多线程编程中，锁起着极其重要的作用，当然啦，信号量可以作为锁所以，但是我今天讲解的内容是另一个锁机制，属于POSIX标准中的机制——互斥锁（mutex）。
+
+    ps：可能某些资料中会将互斥锁称为互斥量，其实也是一样的。
+
+互斥锁和信号量不同的是，它具有互斥锁所有权、递归访问等特性，常用于实现对临界资源的独占式处理，任意时刻互斥锁的状态只有两种，开锁或闭锁。当互斥锁被线程持有时，该互斥锁处于闭锁状态，线程获得互斥锁的所有权。当该线程释放互斥锁时，该互斥锁处于开锁状态，线程失去该互斥锁的所有权。当一个线程持有互斥锁时，其他线程将不能再对该互斥锁进行开锁或持有。持有该互斥锁的线程能够再次获得这个锁而不被阻塞，这就是互斥锁的递归访问，这个特性与一般的信号量有很大的不同，在信号量中，由于已经不存在可用的信号量，线程递归获取信号量时会发生阻塞，最终形成死锁。
+
+    ps：死锁就自己把自己阻塞了，就相当于自己把自己锁在门外，钥匙在屋里，还有一种死锁的的情况是，两个线程相互阻塞，就好比你家的钥匙在你朋友家，你朋友家的钥匙在你家，然后你们都进不去。
+
+想要避免死锁，最好遵循以下的规则：
+
+-  对共享资源操作前一定要获得锁。
+-  完成操作以后一定要释放锁。
+-  尽量短时间地占用锁。
+-  如果有多锁, 如获得顺序是ABC连环扣, 释放顺序也应该是ABC。
+
+如果想要实现同步功能（线程与线程间同步），信号量或许是更好的选择，虽然互斥锁也可以用于线程与线程间的同步，但互斥锁更多的是用于保护资源的互斥。互斥锁可以充当保护资源的令牌，当一个线程希望访问某个资源时，它必须先获取令牌；当线程使用资源后，必须归还令牌，以便其他线程可以访问该资源。在信号量中也可以用于保护临界资源，当线程获取信号量后才能开始使用该资源，当不需要使用时就释放信号量，如此一来其他线程也能获取到信号量从而可用使用资源。但信号量会导致的另一个潜在问题：当其他线程释放这个信号量的时候，这就不能保证信号量能实现互斥操作了。
+
+互斥锁的使用比较单一，并且它是以锁的形式存在，在初始化的时候，互斥锁处于开锁的状态，而当被线程持有的时候则立刻转为闭锁的状态。互斥锁更适合于以下场景：
+
+1. 保护临界资源。
+2. 线程可能会多次获取互斥锁的情况下。这样可以避免同一线程多次递归持有而造成死锁的问题。
+
+多线程环境下往往存在多个线程竞争同一临界资源的应用场景，互斥锁可被用于对临界资源的保护从而实现独占式访问。另外，互斥锁可以降低信号量存在的优先级翻转问题带来的影响。
+
+例如，有两个线程需要用串口进行发送数据，假设其硬件资源只有一个，那么两个线程肯定不能同时发送数据，不然将导致数据错误，那么，就可以用互斥锁对串口资源进行保护，当一个线程正在使用串口的时候，另一个线程则无法使用串口，等到线程使用串口完毕之后，另外一个线程才能获得串口的使用权。
+
+多线程环境下会存在多个线程访问同一临界资源的场景，该资源会被线程独占处理。其他线程在资源被占用的情况下不允许对该临界资源进行访问，这个时候就需要用到的互斥锁来进行资源保护，那么互斥锁是怎样来避免这种冲突？
+
+使用互斥锁处理不同线程对临界资源的同步访问时，线程想要获得互斥锁才能访问资源，如果一旦有线程成功获得了互斥锁，则互斥锁立即变为闭锁状态，此时其他线程会因为获取不到互斥锁而不能访问该资源，那么此时线程有2个选择：扭头就走，不进行等待操作；或者一直阻塞在这里等待，直到互斥锁被持有线程释放后，线程才能获取互斥锁从而得以访问该临界资源，此时互斥锁再次上锁，如此一来就可以确保同一时刻只有一个线程正在访问这个临界资源，保证了临界资源操作的安全性。
+
+初始化互斥锁
+------------
+
+使用互斥锁需要包含头文件：
+
+.. code:: c
+
+        #include <pthread.h>
+
+在使用互斥锁前需要初始化一个互斥锁，而在POSIX标准中支持互斥锁静态初始化也可以支持互斥锁动态初始化，如果是静态初始化的可以通过以下代码初始化（选择其中一句即可）：
+
+.. code:: c
+
+        pthread_mutex_t fastmutex = PTHREAD_MUTEX_INITIALIZER;
+
+        pthread_mutex_t recmutex = PTHREAD_RECURSIVE_MUTEX_INITIALIZER_NP;
+
+        pthread_mutex_t errchkmutex = PTHREAD_ERRORCHECK_MUTEX_INITIALIZER_NP;
+
+pthread_mutex_t是互斥锁的结构体，其实就是定义一个互斥锁结构，并且将其赋值，代表不同的互斥锁。PTHREAD_MUTEX_INITIALIZER表示默认的互斥锁，即快速互斥锁；PTHREAD_RECURSIVE_MUTEX_INITIALIZER_NP则是递归互斥锁；PTHREAD_ERRORCHECK_MUTEX_INITIALIZER_NP则是检错互斥锁。
+
+互斥锁可以分为快速互斥锁、递归互斥锁和检错互斥锁，这 3
+种锁的区别主要在于其他未占有互斥锁的线程在获取互斥锁时是否需要阻塞等待：（以下讨论的情况是假设线程1已经持有互斥锁）
+
+-  快速互斥锁：当线程2尝试获取互斥锁，此时互斥锁处于闭锁状态（互斥锁被线程1持有），那么线程2将会阻塞直至持有互斥锁的线程1解锁为止。
+-  递归互斥锁：线程2尝试获取互斥锁时，将无法获取成功，并且阻塞等待，而如果是线程1尝试获取互斥锁时，将获取成功，并且持有互斥锁的次数加1。
+-  检错互斥锁则为快速互斥锁的非阻塞版本，它会立即返回一个错误代码（线程不会阻塞）。
+
+互斥锁动态初始化可以调用pthread_mutex_init()函数，该函数原型如下：
+
+.. code:: c
+
+        int pthread_mutex_init(pthread_mutex_t *mutex, const pthread_mutexattr_t *mutexattr);
+
+pthread_mutex_init()函数是以动态方式初始化互斥锁的，mutex则是初始化互斥锁结构的指针，mutexattr是属性参数，它允许我们设置互斥锁的属性，而属性控制着互斥锁的行为，如果参数mutexattr为NULL，则使用默认的互斥锁属性，默认属性为快速互斥锁。
+
+获取互斥锁与释放互斥锁
+----------------------
+
+从前文我们也知道，想要访问一个临界资源需要获取互斥锁，获取互斥锁就相当于获得访问资源权限，就好比你有钥匙才能开你家的门。当互斥锁处于开锁状态时，线程才能够获取互斥锁，当线程持有了某个互斥锁的时候，其他线程就无法获取这个互斥锁，需要等到持有互斥锁的线程进行释放后，其他线程才能获取成功，线程通过互斥锁获取函数来获取互斥锁的所有权。线程对互斥锁的所有权是独占的，任意时刻互斥锁只能被一个线程持有，如果互斥锁处于开锁状态，那么获取该互斥锁的线程将成功获得该互斥锁，并拥有互斥锁的所有权；而如果互斥锁处于闭锁状态，则根据互斥锁的类型做对应的处理，默认情况下是快速互斥锁，获取该互斥锁的线程将无法获得互斥锁，线程将被阻塞，直到互斥锁被释放，当然，如果是同一个线程重复获取互斥锁，也会导致死锁结果。
+
+获取互斥锁有2个函数，mutex参数指定了要操作的互斥锁：
+
+.. code:: c
+
+        int pthread_mutex_lock(pthread_mutex_t *mutex);
+
+        int pthread_mutex_trylock(pthread_mutex_t *mutex);
+
+        int pthread_mutex_unlock(pthread_mutex_t *mutex);
+
+通过pthread_mutex_lock()函数获得访问临界资源的权限，如果已经有其他线程锁住互斥锁，那么该函数会是线程阻塞指定该互斥锁解锁为止。pthread_mutex_trylock()是pthread_mutex_lock()函数的非阻塞版本，使用它不会阻塞当前线程，如果互斥锁已被占用，它会理解返回一个EBUSY错误。访问完共享资源后，一定要通过pthread_mutex_unlock()函数释放占用的互斥锁，这样子系统其他线程就有机会获取互斥锁，访问该资源。
+
+简单说就是，互斥锁的使用流程应该是：
+
+1. 线程获取互斥锁。
+2. 然后访问共享资源。
+3. 最后释放互斥锁。
+
+销毁互斥锁
+----------
+
+函数原型：
+
+.. code:: c
+
+        int pthread_mutex_destroy(pthread_mutex_t *mutex);
+
+pthread_mutex_destroy()函数用于销毁一个互斥锁，当互斥锁不再使用时，可以用它来销毁，mutex参数指定了要销毁的互斥锁。
+
+互斥锁实验
+----------
+
+这个实验主要是验证互斥锁的互斥情况，系统创建3个线程，假设这3个线程中有临界资源被访问，那么我肯定是希望这3个线程按顺序去访问这个临界资源（假设临界资源是调用sleep()函数），而不是3个线程全部一起去执行对吧，所以我们可以使用互斥锁去限制能访问的线程，获取到互斥锁的线程可以访问临界资源。
+
+代码如下：
+
+.. code:: c
+
+    #include <unistd.h>
+    #include <fcntl.h>
+    #include <stdio.h>
+    #include <stdlib.h>
+    #include <pthread.h>
+
+    #define THREAD_NUMBER 3 /* 线程数 */
+    #define sleep_TIME_LEVELS 4.0 /*小任务之间的最大时间间隔*/
+
+    pthread_mutex_t mutex;
+
+    void *thrd_func(void *arg)
+    {
+        int num = (unsigned long long)arg; /** sizeof(void*) == 8 and sizeof(int) == 4 (64 bits) */
+        int sleep_time = 0;
+        int res;
+
+        /* 互斥锁上锁 */
+        res = pthread_mutex_lock(&mutex);
+        if (res)
+        {
+            printf("Thread %d lock failed\n", num);
+
+            /* 互斥锁解锁 */
+            pthread_mutex_unlock(&mutex);
+
+            pthread_exit(NULL);
+        }
+
+        printf("Thread %d is hold mutex\n", num);
+
+        sleep_time = (int)(rand() * sleep_TIME_LEVELS/(RAND_MAX)) + 1;
+        printf("\tThread %d: sleep %d S\n",num, sleep_time);
+        sleep(sleep_time);
+
+        printf("Thread %d freed mutex\n\n", num);
+
+        /* 互斥锁解锁 */
+        pthread_mutex_unlock(&mutex);
+
+        pthread_exit(NULL);
+    }
+
+
+    int main(void)
+    {
+        pthread_t thread[THREAD_NUMBER];
+        int num = 0, res;
+
+        srand(time(NULL));
+
+        /* 互斥锁初始化 */
+        pthread_mutex_init(&mutex, NULL);
+        for (num = 0; num < THREAD_NUMBER; num++)
+        {
+            res = pthread_create(&thread[num], NULL, thrd_func, (void*)(unsigned long long)num);
+            if (res != 0)
+            {
+                printf("Create thread %d failed\n", num);
+                exit(res);
+            }
+        }
+
+
+        for (num = 0; num < THREAD_NUMBER; num++)
+        {
+            pthread_join(thread[num], NULL);
+        }
+
+        pthread_mutex_destroy(&mutex);
+        
+        return 0;
+    }
+
+该代码在/embed_Linux_tutorial/base_code/system_programing/mutex/mutex.c路径下，我们直接make编译，然后运行，可以看到线程按照顺序执行了，那个线程获取到互斥锁，就能访问临界资源（假设临界资源是调用sleep()函数）。
+
+现象如下：
+
+.. code:: bash
+
+    ➜  mutex git:(master) ✗ ./targets
+
+    Thread 0 is hold mutex
+            Thread 0: sleep 4 S
+    Thread 0 freed mutex
+
+    Thread 2 is hold mutex
+            Thread 2: sleep 2 S
+    Thread 2 freed mutex
+
+    Thread 1 is hold mutex
+            Thread 1: sleep 1 S
+    Thread 1 freed mutex
+
+如果觉得不太明确的话，可以将互斥锁的相关代码注释掉，看看如果没有互斥操作的话线程会怎样访问临界资源，再重新编译运行，注释后的代码如下：
+
+.. code:: c
+
+    #include <unistd.h>
+    #include <fcntl.h>
+    #include <stdio.h>
+    #include <stdlib.h>
+    #include <pthread.h>
+
+    #define THREAD_NUMBER 3 /* 线程数 */
+    #define sleep_TIME_LEVELS 4.0 /*小任务之间的最大时间间隔*/
+
+    pthread_mutex_t mutex;
+
+    void *thrd_func(void *arg)
+    {
+        int num = (unsigned long long)arg; /** sizeof(void*) == 8 and sizeof(int) == 4 (64 bits) */
+        int sleep_time = 0;
+        int res;
+
+        // /* 互斥锁上锁 */
+        // res = pthread_mutex_lock(&mutex);
+        // if (res)
+        // {
+        //     printf("Thread %d lock failed\n", num);
+
+        //     /* 互斥锁解锁 */
+        //     pthread_mutex_unlock(&mutex);
+
+        //     pthread_exit(NULL);
+        // }
+
+        // printf("Thread %d is hold mutex\n", num);
+
+        sleep_time = (int)(rand() * sleep_TIME_LEVELS/(RAND_MAX)) + 1;
+        printf("\tThread %d: sleep %d S\n",num, sleep_time);
+        sleep(sleep_time);
+
+        // printf("Thread %d freed mutex\n\n", num);
+
+        /* 互斥锁解锁 */
+        // pthread_mutex_unlock(&mutex);
+
+        pthread_exit(NULL);
+    }
+
+
+    int main(void)
+    {
+        pthread_t thread[THREAD_NUMBER];
+        int num = 0, res;
+
+        srand(time(NULL));
+
+        /* 互斥锁初始化 */
+        // pthread_mutex_init(&mutex, NULL);
+
+        for (num = 0; num < THREAD_NUMBER; num++)
+        {
+            res = pthread_create(&thread[num], NULL, thrd_func, (void*)(unsigned long long)num);
+            if (res != 0)
+            {
+                printf("Create thread %d failed\n", num);
+                exit(res);
+            }
+        }
+
+
+        for (num = 0; num < THREAD_NUMBER; num++)
+        {
+            pthread_join(thread[num], NULL);
+        }
+
+        // pthread_mutex_destroy(&mutex);
+        
+        return 0;
+    }
+
+实验现象：
+
+.. code:: bash
+
+    ➜  mutex git:(master) ✗ ./targets
+
+            Thread 2: sleep 3 S
+            Thread 1: sleep 3 S
+            Thread 0: sleep 1 S
+
+其实这个实验现象是终端同时打印出这3行代码，这说明了线程在同时访问临界资源，这怎么可以呢，这样岂不是乱套了吗，为了让实验更明确，不要注释这两句代码：
+
+.. code:: c
+
+    printf("Thread %d is hold mutex\n", num);
+
+    printf("Thread %d freed mutex\n\n", num);
+
+实验现象，可以很明显看出如果没有互斥锁进行保护临界资源，3个线程都会同时去访问这个临界资源：
+
+.. code:: bash
+
+    ➜  mutex git:(master) ✗ ./targets
+
+    Thread 0 is hold mutex
+            Thread 0: sleep 1 S
+    Thread 2 is hold mutex
+            Thread 2: sleep 3 S
+    Thread 1 is hold mutex
+            Thread 1: sleep 4 S
+    Thread 0 freed mutex
+
+    Thread 2 freed mutex
+
+    Thread 1 freed mutex
+
diff --git a/documentation/system_programing/posix_sem.rst b/documentation/system_programing/posix_sem.rst
new file mode 100644
index 0000000000000000000000000000000000000000..298dcdb05f13fbf0c175dc483e1a2208c3882ace
--- /dev/null
+++ b/documentation/system_programing/posix_sem.rst
@@ -0,0 +1,343 @@
+POSIX信号量
+===========
+
+这篇文章将讲述别一种进程/线程间通信的机制——POSIX信号量，为了明确与system
+V信号量间的区别，若非特别说明，本章出现的信号量均为POSIX信号量。也要注意请不要把它与之前所说的信号混淆了，信号与信号量是不同的两种机制。
+
+POSIX信号量基本概念
+-------------------
+
+信号量（Semaphore）是一种实现进程/线程间通信的机制，可以实现进程/线程之间同步或临界资源的互斥访问，常用于协助一组相互竞争的进程/线程来访问临界资源。在多进程/线程系统中，各进程/线程之间需要同步或互斥实现临界资源的保护，信号量功能可以为用户提供这方面的支持。
+
+在 POSIX
+标准中，信号量分两种，一种是无名信号量，一种是有名信号量。无名信号量一般用于进程/线程间同步或互斥，而有名信号量一般用于进程间同步或互斥。有名信号量和无名信号量的差异在于创建和销毁的形式上，但是其他工作一样，无名信号量则直接保存在内存中，而有名信号量要求创建一个文件。
+
+正如其名，无名信号量没有名字，它只能存在于内存中，这就要求使用信号量的进程/线程必须能访问无名信号量所在的这一块内存，所以无名信号量只能应用在同一进程内的线程之间同步或者互斥。相反，有名信号量可以通过名字访问，因此可以被任何知道它们名字的进程或者进程/线程使用。单个进程中使用
+POSIX 信号量时，无名信号量更简单，多个进程间使用 POSIX
+信号量时，有名信号量更简单。
+
+在多进程/多进程/线程操作系统环境下，多个进程/线程会同时运行，并且一些进程/线程之间可能存在一定的关联。多个进程/线程可能为了完成同一个进程/线程会相互协作，这样形成进程/线程之间的同步关系，因此可以使用信号量进行同步。
+
+而且在不同进程/线程之间，为了争夺有限的系统资源（硬件或软件资源）会进入竞争状态，这就是进程/线程之间的互斥关系。为了防止出现因多个程序同时访问一个共享资源而引发的一系列问题，我们需要一种方法，它可以通过生成并使用令牌来授权，在任一时刻只能有一个执行进程/线程访问代码的临界区域。临界区域是指执行数据更新的代码需要独占式地执行。而信号量就可以提供这样的一种访问机制，让一个临界区同一时间只有一个进程/线程在访问它，因此信号量是可以用来调协进程/线程对共享资源的访问的。进程/线程之间的互斥与同步关系存在的根源在于临界资源。临界资源是在同一个时刻只允许有限个（通常只有一个）进程/线程可以访问（读）或修改（写）的资源，通常包括硬件资源（处理器、内存、存储器以及其他外围设备等）和软件资源（共享代码段，共享结构和变量等）。
+
+抽象的来讲，信号量中存在一个非负整数，所有获取它的进程/线程都会将该整数减一（获取它当然是为了使用资源），当该整数值为零时，所有试图获取它的进程/线程都将处于阻塞状态。通常一个信号量的计数值用于对应有效的资源数，表示剩下的可被占用的互斥资源数。其值的含义分两种情况：
+
+-  0：表示没有可用的信号量，进程/线程进入睡眠状态，直至信号量值大于 0。
+
+-  正值：表示有一个或多个可用的信号量，进程/线程可以使用该资源。进程/线程将信号量值减
+   1，表示它使用了一个资源单位。
+
+对信号量的操作可以分为两个：
+
+-  P
+   操作：如果有可用的资源（信号量值大于0），则占用一个资源（给信号量值减去一，进入临界区代码）;如果没有可用的资源（信号量值等于
+   0），则被阻塞到，直到系统将资源分配给该进程/线程（进入等待队列，一直等到资源轮到该进程/线程）。这就像你要把车开进停车场之前，先要向保安申请一张停车卡一样，P
+   操作就是申请资源，如果申请成功，资源数（空闲的停车位）将会减少一个，如果申请失败，要不在门口等，要不就走人。
+
+-  V
+   操作：如果在该信号量的等待队列中有进程/线程在等待资源，则唤醒一个阻塞的进程/线程。如果没有进程/线程等待它，则释放一个资源（给信号量值加一），就跟你从停车场出去的时候一样，空闲的停车位就会增加一个。
+
+举个例子，就是两个进程/线程共享信号量sem，sem可用信号量的数值为1，一旦其中一个进程/线程执行了P（sem）操作，它将得到信号量，并可以进入临界区，使sem减1。而第二个进程/线程将被阻止进入临界区，因为当它试图执行P（sem）操作时，sem为0，它会被挂起以等待第一个进程/线程离开临界区域并执行V（sem）操作释放了信号量，这时第二个进程/线程就可以恢复执行。
+
+POSIX有名信号量
+---------------
+
+如果要在Linux中使用信号量同步，需要包含头文件 ``semaphore.h`` 。
+
+有名信号量其实是一个文件，它的名字由类似 ``"sem.[信号量名字]"`` 这样的字符串组成，注意看文件名前面有 ``"sem."`` ，它是一个特殊的信号量文件，在创建成功之后，系统会将其放置在 ``/dev/shm`` 路径下，不同的进程间只要约定好一个相同的信号量文件名字，就可以访问到对应的有名信号量，并且借助信号量来进行同步或者互斥操作，需要注意的是，有名信号量是一个文件，在进程退出之后它们并不会自动消失，而需要手工删除并释放资源。
+
+**主要用到的函数：**
+
+.. code:: c
+
+        sem_t *sem_open(const char *name, int oflag, mode_t mode, unsigned int value);
+        int sem_wait(sem_t *sem);
+        int sem_trywait(sem_t *sem);
+        int sem_post(sem_t *sem);
+        int sem_close(sem_t *sem);
+        int sem_unlink(const char *name);
+
+sem_open()函数用于打开/创建一个有名信号量
+
+**参数：**
+
+-  name：打开或者创建信号量的名字。
+-  oflag：当指定的文件不存在时，可以指定 O_CREATE 或者 O_EXEL
+   进行创建操作，如果指定为0，后两个参数可省略，否则后面两个参数需要带上。
+-  mode：八进制的文件读写权限。
+-  value：信号量初始的值，这这个参数只有在新创建的时候才需要设置，如果是打开已有的，不需要在去指定，否则会报错。该值不允许大于系统指定值SEM_VALUE_MAX。
+-  sem_open()函数的返回值是一个sem_t类型的指针，它指向已经创建/打开的信号量，后续的函数都通过改信号量指针去访问对应的信号量。
+
+sem_wait()函数是等待（获取）信号量，如果信号量的值大于0，将信号量的值减1，立即返回。如果信号量的值为0，则进程/线程阻塞。相当于P操作。成功返回0，失败返回-1。
+
+sem_trywait()函数也是等待信号量，如果指定信号量的计数器为0，那么直接返回EAGAIN错误，而不是阻塞等待。
+
+sem_post()函数是释放信号量，让信号量的值加1，相当于V操作。成功返回0，失败返回-1。
+
+sem_close()函数用于关闭一个信号量，这表示当前进程/线程取消对信号量的使用，它的作用仅在当前进程/线程，其他进程/线程依然可以使用该信号量，同时当进程结束的时候，无论是正常退出还是信号中断退出的进程，内核都会主动调用该函数去关闭进程使用的信号量，即使从此以后都没有其他进程/线程在使用这个信号量了，内核也会维持这个信号量。
+
+sem_unlink()函数就是主动删除一个信号量，直接删除指定名字的信号量文件。
+
+POSIX无名信号量
+---------------
+
+无名信号量的操作与有名信号量差不多的，但它不使用文件系统标识，直接存在程序运行的内存中，不同进程之间不能访问，不能用于不同进程之间相互访问。同样的一个父进程初始化一个信号量，然后fork其副本得到的是该信号量的副本，这两个信号量之间并不存在关系。
+
+**主要用到的函数：**
+
+.. code:: c
+
+        int sem_init(sem_t *sem， int pshared， unsigned int value);
+        int sem_destroy(sem_t *sem);
+        int sem_wait(sem_t *sem);
+        int sem_trywait(sem_t *sem);
+        int sem_post(sem_t *sem);
+
+-  sem_init()：初始化信号量，其中sem是要初始化的信号量，pshared表示此信号量是在进程间共享还是线程间共享，由于目前
+   Linux 还没有实现进程间共享信号量，所以这个值只能够取
+   0，就表示这个信号量是当前进程的局部信号量，value是信号量的初始值。成功返回0，失败返回-1。
+
+-  sem_destroy()：销毁信号量，其中sem是要销毁的信号量。只有用sem_init初始化的信号量才能用sem_destroy()函数销毁。成功返回0，失败返回-1。
+
+sem_wait()、sem_trywait()、sem_post()等函数与有名信号量的使用是一样的。
+
+POSIX信号量的使用实例
+---------------------
+
+有名信号量
+~~~~~~~~~~
+
+有名信号量中创建了两个进程，然后进程之间通有名信号量进行同步操作。
+
+有名信号量的使用操作步骤如下： 
+
+1.通过sem_open()函数打开或者创建一个信号量。 
+
+2.调用sem_wait()函数获取到信号量，然后打印信息到终端。 
+
+3.使用sem_post()函数释放信号量。 
+
+4.使用完毕后将信号量关闭并且删除：sem_close()、sem_unlink()。
+
+.. code:: c
+
+    #include <unistd.h>
+    #include <stdio.h>
+    #include <pthread.h>
+    #include <semaphore.h>
+    #include <stdlib.h>
+    #include <stdio.h>
+    #include <sys/types.h>
+    #include <fcntl.h>
+    #include <sys/wait.h>
+
+    int main(int argc, char **argv)
+    {
+        int pid;
+        sem_t *sem;
+        const char sem_name[] = "my_sem_test";
+
+        pid = fork();
+
+        if (pid < 0) {
+            printf("error in the fork!\n");
+        } else if (pid == 0) {
+            
+            sem = sem_open(sem_name, O_CREAT, 0644, 1);
+
+            if (sem == SEM_FAILED) {
+                printf("unable to create semaphore...\n");
+
+                sem_unlink(sem_name);
+
+                exit(-1);
+            }
+
+            sem_wait(sem);
+
+            for (int i = 0; i < 3; ++i) {
+
+                printf("childe process run: %d\n", i);
+                sleep(1);
+            }
+
+        sem_post(sem);
+
+        } else {
+
+            sem = sem_open(sem_name, O_CREAT, 0644, 1);
+            
+            if (sem == SEM_FAILED) {
+                printf("unable to create semaphore...\n");
+
+                sem_unlink(sem_name);
+
+                exit(-1);
+            }
+
+            sem_wait(sem);
+
+            for (int i = 0; i < 3; ++i) {
+
+                printf("parent process run: %d\n", i);
+                sleep(1);
+            }
+
+            sem_post(sem);
+
+            wait(NULL);
+        }
+
+        sem_close(sem);
+        sem_unlink(sem_name);
+
+        return 0;
+    }
+
+编译并且运行后，实验现象如下：
+
+.. code:: bash
+
+     parent process run: 0
+     parent process run: 1
+     parent process run: 2
+     childe process run: 0
+     childe process run: 1
+     childe process run: 2
+
+在代码的运行过程中，如果你打开一个新的终端，并且输入以下命令：
+
+.. code:: bash
+
+    ls -l /dev/shm
+
+    -rw-r--r--  1 root  root    32 2月  14 13:31 sem.my_sem_test
+
+那么你可以发现在 ``/dev/shm`` 目录下存在一个 ``sem.my_sem_test`` 文件，这就是我们实验中创建的一个信号量，当进程运行完毕，这个信号量将会被删除。
+
+无名信号量
+~~~~~~~~~~
+
+下面的例子是用无名信号量同步机制实现 3
+个线程之间的有序执行，首先创建3个线程，然后在线程中首先使用sem_wait()获取信号量，然后随机睡眠3次，然后再通过sem_post()函数释放信号量，再退出进线程，这个实验的目的是为了使用信号量在多线程间进行同步。
+
+**代码如下：**
+
+.. code:: c
+
+    #include <unistd.h>
+    #include <stdio.h>
+    #include <stdlib.h>
+    #include <pthread.h>
+    #include <semaphore.h>
+
+    #define THREAD_NUMBER 3 /* 进程/线程数 */
+    #define REPEAT_NUMBER 3 /* 每个进程/线程中的小任务数 */
+    #define DELAY_TIME_LEVELS 3.0 /*小任务之间的最大时间间隔*/
+
+    sem_t sem[THREAD_NUMBER];
+
+    void *thread_func(void *arg)
+    {
+        int num = (unsigned long long)arg;
+        int delay_time = 0;
+        int count = 0;
+
+        /* 进行 P 操作 */
+        sem_wait(&sem[num]);
+
+        printf("Thread %d is starting\n", num);
+        for (count = 0; count < REPEAT_NUMBER; count++)
+        {
+            delay_time = (int)(rand() * DELAY_TIME_LEVELS/(RAND_MAX)) + 1;
+            sleep(delay_time);
+            printf("\tThread %d: job %d delay = %d\n",num, count, delay_time);
+        }
+
+        printf("Thread %d finished\n", num);
+        pthread_exit(NULL);
+    }
+
+
+
+    int main(void)
+    {
+        pthread_t thread[THREAD_NUMBER];
+        int no = 0, res;
+        void * thread_ret;
+        srand(time(NULL));
+
+        for (no = 0; no < THREAD_NUMBER; no++)
+        {
+            sem_init(&sem[no], 0, 0);
+            res = pthread_create(&thread[no], NULL, thread_func, (void*)(unsigned long long)no);
+
+            if (res != 0)
+            {
+                printf("Create thread %d failed\n", no);
+                exit(res);
+            }
+        }
+
+        printf("Create treads success\n Waiting for threads to finish...\n");
+
+        /* 对最后创建的进程/线程的信号量进行 V 操作 */
+        sem_post(&sem[THREAD_NUMBER - 1]);
+        for (no = THREAD_NUMBER - 1; no >= 0; no--)
+        {
+            res = pthread_join(thread[no], &thread_ret);
+            if (!res)
+            {
+                printf("Thread %d joined\n", no);
+            }
+            else
+            {
+                printf("Thread %d join failed\n", no);
+            }
+
+            /* 进行 V 操作 */
+            sem_post(&sem[(no + THREAD_NUMBER - 1) % THREAD_NUMBER]);
+        }
+
+        for (no = 0; no < THREAD_NUMBER; no++)
+        {
+            /* 删除信号量 */
+            sem_destroy(&sem[no]);
+        }
+
+        return 0;
+    }
+
+**实验结果如下：**
+
+.. code:: bash
+
+    ➜  thread_sem make     
+
+    gcc -o thread_sem.o -c -g -Werror -I. -Iinclude -lpthread -static  thread_sem.c -g -MD -MF .thread_sem.o.d
+    gcc -o targets thread_sem.o -g -Werror -I. -Iinclude -lpthread -static 
+
+
+    ➜  thread_sem ./targets
+
+    Create treads success
+     Waiting for threads to finish...
+    Thread 2 is starting
+            Thread 2: job 0 delay = 1
+            Thread 2: job 1 delay = 3
+            Thread 2: job 2 delay = 3
+    Thread 2 finished
+    Thread 2 joined
+    Thread 1 is starting
+            Thread 1: job 0 delay = 3
+            Thread 1: job 1 delay = 1
+            Thread 1: job 2 delay = 1
+    Thread 1 finished
+    Thread 1 joined
+    Thread 0 is starting
+            Thread 0: job 0 delay = 3
+            Thread 0: job 1 delay = 2
+            Thread 0: job 2 delay = 1
+    Thread 0 finished
+    Thread 0 joined
+
diff --git a/documentation/system_programing/process.rest b/documentation/system_programing/process.rest
deleted file mode 100644
index e9e2433a52c9d89f320a6d9f1c0a8cc3d970aee0..0000000000000000000000000000000000000000
--- a/documentation/system_programing/process.rest
+++ /dev/null
@@ -1,1314 +0,0 @@
-.. vim: syntax=rst
-
-进程
---
-
-本章节内容处于开发笔记状态，还待整理至最终版的教程。
-
-本章节内容处于开发笔记状态，还待整理至最终版的教程。
-
-简单了解进程
-~~~~~~
-
-在进入正题之前，我们不打算像其他书籍一样，讲一大堆原理，而是希望想通过实验现象来引导读者了解进程相关的知识，紧接着再来补充进程相关的知识点。
-
-首先在虚拟机中打开一个终端（相信读者能阅读到此处，就已经了解什么是终端了，而由于作者用是的公司的服务器，使用ssh方式连接的，所以下文的截图有可能与读者的显示界面不是一样的，但这不会对本章的阅读造成任何影响），一般来说ubuntu中有很多shell终端，而这个终端就是一个进程，或许读者很可能打开多个
-终端，那么这些所有被打开的终端就一个个进程，这些进程是不一样的，独立运行在系统中，作者打开三个shell终端，这些终端各自有输入输出，互不干扰，如图 37‑1所示。
-
-|proces002|
-
-图 37‑1 三个shell终端
-
-每个运行中的 shell 都是一个单独的进程，假如读者从一个 shell 里面调用一个程序的时候，对应的程序在一个新进程中运行，运行结束后 shell
-继续工作，高级的程序员经常在一个应用程序中同时启用多个协作的进程以使程序可以并行更多任务、使程序更健壮，或者可以直接利用已有的其它程序，这样子整个系统中运行的进程就可以相互配合，而不是独立运行，这就涉及到进程间的通信，这部分内容我们在后续讲解。
-
-查看进程
-~~~~
-
-即使读者刚打开linux电脑，没有运行任何程序，电脑中也会有进程存在，因为系统中必须要有进程在处理一些必要的程序，以保证系统能正常运行。其实在Linux中是通过检查表记录与进程相关的信息的，进程表就像一个数据结构，它把当前加载在内存中的所有进程的有关信息保存在一个表中，其中包括进程的PID、进程的状
-态、命令字符串和其他一些ps命令输出的各类信息。操作系统通过进程的ID对它们进行管理，这些PID是进程表的索引，就目前的linux系统而言，系统支持可以同时运行的进程数可能只与用于建立进程表项的内存容量有关，而没有具体的数量的限制，也就是说系统有足够的内存的话，那么理论上就可以运行无数个进程。
-
-进程ID
-^^^^
-
-Linux 系统中的每个进程都都会被分配一个唯一的数字编号，我们称之为进程ID（Process ID，通常也被简称为 PID）。进程ID 是一个 16 位的正整数，默认取值范围是从2到32768（可以修改），由 Linux
-在启动新进程的时候自动依次分配，当进程被启动时，系统将按顺序选择下一个未被使用的数字作为它的PID，当PID的数值达到最大时，系统将重新选择下一个未使用的数值，新的PID重新从2开始，这是因为PID数字为1的值一般是为特殊进程init保留，即系统在运行时就存在的第一个进程，
-init进程负责管理其他进程。
-
-父进程ID
-^^^^^
-
-任何进程（除init进程）都是由另一个进程启动，该进程称为被启动进程的父进程，被启动的进程称为子进程，父进程号无法在用户层修改。父进程的进程号（PID）即为子进程的父进程号（PPID）。用户可以通过调用getppid()函数来获得当前进程的父进程号。
-
-为了更直观看到这些进程，作者就使用ps命令去查看系统中的进程情况，ps命令可以显示我们正在运行的进程、其他用户正在运行的进程或者目前在系统上运行的所有进程。输出结果如图
-37‑2所示，可以很明显看到，编号为1的进程是init进程。它位于/sbin/init目录中。当然，整个系统的进程可不止这一些，由于太多没法截图，就只展示这小部分的进程，读者可以自己使用下面命令去尝试一下， ps 命令可以显示当前系统中运行的进程， 其实在linux中， ps
-命令有很多选项，因为它试图与很多不同 UNIX 版本的 ps 命令兼容，这些选项决定显示哪些进程以及要显示的信息。
-
-命令
-
-ps –aux
-
-|proces003|
-
-图 37‑2 ps –aux输出结果
-
-父进程与子进程
-^^^^^^^
-
-进程启动时，启动进程为新进程的父进程，新进程是启动进程的子进程。
-
-每个进程都有一个父进程（除了 系统中如“僵尸进程”这种特殊进程外），因此，读者可以把 Linux 中的进程结构想象成一个树状结构，其中 init
-进程就是树的“根”；或者可以把init进程看作为操作系统的进程管理器，它是其他所有进程的祖先进程。我们将要看到的其他系统进程要么是由init进程启动的，要么是由被init进程启动的其他进程启动的。
-
-总的来说init进程下有很多子进程，这些子进程又可能存在子进程，就像家族一样。系统中所有的父进程 ID被称为PPID，不同进程的父进程是不同的，这个值只是当前进程的父进程的
-ID，系统中的父进程与子进程是相对而言的，就好比爷爷<->爸爸<->儿子直接的关系，爸爸相对于爷爷而言是儿子，相对于儿子而言则是爸爸。
-
-为了更加直观看出系统中父进程与子进程，作者决定使用pstree命令将进程以树状关系列出来，具体见图 37‑3。
-
-命令
-
-pstree
-
-|proces004|
-
-图 37‑3 pstree命令结果
-
-程序与进程
-~~~~~
-
-进程相关信息也简单了解过了，可能很多读者还是有疑问，我们写的代码，它是程序，怎么变成进程了呢？那么在本小节作者就讲解一下程序与进程的关系。
-
-程序
-^^
-
-程序（program） 是一个普通文件，是为了完成特定任务而准备好的指令序列与数据的集合，这些指令和数据以“可执行映像”的格式保存在磁盘中。正如我们所写的一些代码，经过编译器编译后，就会生成对应的可执行文件，那么这个就是程序，或者称之为可执行程序。
-
-.. _进程-1:
-
-进程
-^^
-
-进程（process）则是程序执行的具体实例，比如一个可执行文件，在执行的时候，它就是一个进程，直到该程序执行完毕。那么在程序执行的过程中，它享有系统的资源，至少包括进程的运行环境、CPU、外设、内存、进程ID等资源与信息，同样的一个程序，可以实例化为多个进程，在Linux 系统下使用 ps
-命令可以查看到当前正在执行的进程，当这个可执行程序运行完毕后，进程也会随之被销毁（可能不是立即销毁，但是总会被销毁）。
-
-程序并不能单独执行，只有将程序加载到内存中，系统为他分配资源后才能够执行，这种执行的程序称之为进程，也就是说进程是系统进行资源分配和调度的一个独立单位，每个进程都有自己单独的地址空间。
-
-举个例子，我们可以看到/bin目录下有很多可执行文件，如图 37‑4所示，我们在系统中打开一个终端就是一个进程，这个进程由bash可执行文件（程序）实例化而来，而一个linux系统可用打开多个终端，并且这些终端是独立运行在系统中的。
-
-|proces005|
-
-图 37‑4 /bin目录下的可执行文件
-
-程序变成进程
-^^^^^^
-
-在linux系统中，程序只是个静态的文件，而进程是一个动态的实体，进程的状态（后续讲解进程状态）会在运行过程中改变，那么问题来了，程序到底是如何变成一个进程的呢？
-
-其实正如我们运行一个程序（可执行文件），通常在 Shell 中输入命令运行就可以了，在这运行的过程中包含了程序到进程转换的过程，整个转换过程主要包含以下 3 个步骤：
-
-1. 查找命令对应程序文件的位置。
-
-2. 使用 fork()函数为启动一个新进程。
-
-3. 在新进程中调用 exec 族函数装载程序文件，并执行程序文件中的 main()函数。
-
-补充：关于具体的函数介绍将在后续讲解。
-
-总结
-^^
-
-总的来说，程序与进程有以下的关系：
-
-1. 程序只是一系列指令序列与数据的集合，它本身没有任何运行的含义，它只是一个静态的实体。而进程则不同，它是程序在某个数据集上的执行过程，它是一个动态运行的实体，有自己的生命周期，它因启动而产生，因调度而运行，因等待资源或事件而被处于等待状态，因完成任务而被销毁。
-
-2. 进程和程序并不是一一对应的，一个程序执行在不同的数据集上运行就会成 为不同的进程，可以用进程控制块来唯一地标识系统中的每个进程。而这一点正是程序无法做到的，由于程序没有和数据产生直接的联系，既使是 执行不同的数据的程序，他们的指令的集合依然是一样的，所以无法
-   唯一地标识出这些运行于不同数据集上的程序。一般来说，一个进程 肯定有一个与之对应的程序，而且有且只有一个。而一个程序有可能没有与之对应的进程（因为这个程序没有被运行），也有可能有多个进程与之对应（这个程序可能运 行在多个不同的数据集上）。
-
-3. 进程具有并发性而程序没有。
-
-4. 进程是竞争计算机资源的基本单位，而程序不是。
-
-   4. ..
-      rubric:: 进程状态 :name: 进程状态
-
-在学习进程状态之前，作者决定还是先让读者看看系统中常见的进程状态，可以通过ps命令将系统中运行的进程信息打印出来，我们只需要关注STAT那一列的信息即可，进程的状态非常多种，具体见图 37‑5：
-
-命令
-
-ps –ux
-
-输出(已删减)：
-
-USER PID %CPU %MEM VSZ RSS TTY STAT START TIME COMMAND
-
-xxx 11132 0.0 0.0 15492 5568 pts/1 Ss 00:45 0:00 /bin/bashxxx 11340 0.0 0.0 15508 5636 pts/2 Ss+ 00:50 0:01 /bin/bashxxx 11807 0.0 0.0 14916 4572
-pts/3 Ss 01:05 0:00 /bin/bashxxx 18319 0.0 0.0 18260 588 pts/1 Ss+ 10月09 0:00 bashxxx 21862 0.0 0.0 7928 824 ? S 07:57 0:00 sleep 180xxx 26124 0.0 0.0
-29580 1540 pts/1 R+ 07:58 0:00 ps -ux
-
-由于作者用的是公司服务器，所以只将作者用户当前的进程信息输出，而不是将系统所有进程信息输出，因此ps命令不需要 –a 选项。
-
-|proces006|
-
-图 37‑5 进程状态
-
-从图 37‑5中可以看到进程的状态有比较多种，有些是S，有些是Ss，还有些是Sl、Rl、R+等状态，具体是什么含义呢？其实是这些状态只是linux系统进程的一部分，还有一些状态是没有显示出来的，因为作者当前用户下的所有进程并没有处于那些状态，所以就没显示出来，下面作者就简单介绍一下linux系统中所
-有的进程状态，如表格 37‑1所示。
-
-表格 37‑1 linux系统中进程状态说明
-
-==== ===========================================================================================================================================================================
-状态 说明
-==== ===========================================================================================================================================================================
-R    运行状态。严格来说，应该是“可运行状态”，即表示进程在运行队列中，处于正在执行或即将运行状态，只有在该状态的进程才可能在 CPU 上运行，而同一时刻可能有多个进程处于可运行状态。
-S    可中断的睡眠状态。处于这个状态的进程因为等待某种事件的发生而被挂起，比如进程在等待信号。
-D    不可中断的睡眠状态。通常是在等待输入或输出（I/O）完成，处于这种状态的进程不能响应异步信号。
-T    停止状态。通常是被shell的工作信号控制，或因为它被追踪，进程正处于调试器的控制之下。
-Z    退出状态。进程成为僵尸进程。
-X    退出状态。进程即将被回收。
-s    进程是会话其首进程。
-l    进程是多线程的。
-+    进程属于前台进程组。
-<    高优先级任务。
-==== ===========================================================================================================================================================================
-
-进程状态转换
-~~~~~~
-
-从前文的介绍我们也知道，进程是动态的活动的实例，这其实指的是进程会有很多种运行状态，一会儿睡眠、一会儿暂停、一会儿又继续执行。虽然Linux操作系统是一个多用户多任务的操作系统，但对于单核的CPU系统来说，在某一时刻，只能有一个进程处于运行状态（此处的运行状态指的是占用CPU），其他进程都处于其他状
-态，等待系统资源，各任务根据调度算法在这些状态之间不停地切换。但由于CPU处理速率较快，使用户感觉每个进程都是同时运行。
-
-图 37‑6 展示了Linux 进程从被启动到退出的全部状态，以及这些状态发生转换时的条件。\ |proces007|
-
-图 37‑6 进程状态转换
-
-1. 一般来说，一个进程的开始都是从其父进程调用fork()开始的，所以在系统一上电运行的时候，init进程就开始工作，在系统运行过程中，会不断启动新的进程，这些进程要么是由init进程启动的，要么是由被init进程启动的其他进程所启动的。
-
-2. 一个进程被启动后，都是处于可运行状态（但是此时进程并未占用CPU运行）。处于该状态的进程可以是正在进程等待队列中排队，也可以占用 CPU 正在运行，我们习惯上称前者为“就绪态”，称后者为“运行态”（占用CPU运行）。
-
-3. 当系统产生进程调度的时候，处于就绪态的进程可以占用CPU的使用权，此时进程就是处于运行态。但每个进程运行时间都是有限的，比如 10毫秒，这段时间被称为
-   “时间片”。当进程的时间片已经耗光了的情况下，如果进程还没有结束运行，那么会被系统重新放入等待队列中等待，此时进程又转变为就绪状态，等待下一次进程的调度。另外，正处于“运行态”的进程即使时间片没有耗光，也可能被别的更高优先级的进程“抢占”，被迫重新回到等到队列中等待。
-
-4. 处于“运行态”的进程可能会等待某些事件、信号或者资源而进入“可中断睡眠态”，比如进程要读取一个管道文件数据而管道为空，或者进程要获得一个锁资源而当前锁不可获取，甚至是进程自己调用
-   sleep()来强制将自己进入睡眠，这些情况下进程的状态都会变成“可中断睡眠态”。顾名思义，“可中断睡眠态”就是可以被中断的，能响应信号，在特定条件发生后，进程状态就会转变为“就绪态”，比如其他进程想管道文件写入数据后，或者锁资源可以被获取，或者是睡眠时间到达等情况。
-
-5. 当然，处于“运行态”的进程还可能会进入“不可中断睡眠态”，在这种状态下的进程不能响应信号，但是这种状态非常短暂，读者几乎无法通过ps命令将其显示出来，一般处于这种状态的进程都是在等待输入或输出（I/O）完成，在等待完成后自动进入“就绪态”。
-
-6. 当进程收到 SIGSTOP 或者 SIGTSTP 中的其中一个信号时，进程状态会被置为 “暂停态”，该状态下的进程不再参与调度，但系统资源不会被释放，直到收到 SIGCONT 信号后被重新置为就绪态。当进程被追踪时（典型情况是使用调试器调试应用程序的情况），收到任何信号状态都会被置为
-   TASK_TRACED状态，该状态跟暂停态是一样的，一直要等到 SIGCONT 信号后进程才会重新参与系统进程调度。
-
-7. 进程在完成任务后会退出，那么此时进程状态就变为退出状态，这是正常的退出，比如在main 函数内 return 或者调用 exit()函数或者线程调用
-   pthread_exit()都是属于正常退出。为什么作者要强调正常退出呢？因为进程也会有异常退出，比如进程收到kill信号就会被杀死，其实不管怎么死，最后内核都会调用do_exit()函数来使得进程的状态变成“僵尸态（僵尸进程）”，这里的“僵尸”指的是进程的 PCB（Process Control
-   Block，进程控制块）。为什么一个进程的死掉之后还要把尸体（PCB）留下呢？因为进程在退出的时候，系统会将其退出信息都保存在进程控制块中，比如如果他正常退出，那进程的退出值是多少呢？如果被信号杀死？那么是哪个信号将其杀死呢？这些“死亡信息”都被一一封存在该进程的 PCB
-   当中，好让别人可以清楚地知道：我是怎么死的。那谁会关心他是怎么死的呢？那就是它的父进程，它的父进程之所以要启动它，很大的原因是要让这个进程去干某一件事情，现在这个孩子已死，那事情办得如何，因此需要把这些信息保存在进程控制块中，等着父进程去查看这些信息。
-
-8. 当父进程去处理僵尸进程的时候，会将这个僵尸进程的状态设置为EXIT_DEAD，即死亡态（退出态）， 这样子系统才能去回收僵尸进程的内存空间，否则系统将存在 越来越多的僵尸进程，最后导致系统 内存不足而崩溃。那么还有两个问题，假如父进程由于太忙而没能及时去处理僵尸进程的时候，要怎么处理呢？又假如在子进
-   程变成“僵尸态”之前，它的父进程已经先它而去了（退出），那么这个子进程变成僵死态由谁处理呢？第一种情况可能不同的读者有不同的处理，父进程有别的事情要干，不能随时去处理僵尸进程。在这样的情形下，读者可以考虑使用信号异步通知机制，让一个孩子在变成僵尸的时候，给其父进程发一个信号，父进程接收到这个信号之后
-   ，再对其进行处理，在此之前父进程该干嘛就干嘛。而如果如果一个进程的父进程先退出，那么这个子进程将变成“孤儿进程”（没有父进程），那么这个进程将会被他的祖先进程收养（adopt），它的祖先进程是 init（该进程是系统第一个运行的进程，他的 PCB
-   是从内核的启动镜像文件中直接加载的，系统中的所有其他进程都是init进程的后代）。那么当子进程退出的时候，init进程将回收这些资源。
-
-   6. ..
-      rubric:: 启动新进程 :name: 启动新进程
-
-在linux中启动一个进程有多种方法，比如可以使用system()函数，也可以使用fork()函数去启动（在其他的一些linux书籍也称作创建进程，本书将全部称之为启动进程）一个新的进程，第一种方法相对简单，但是在使用之前应慎重考虑，因为它效率低下，而且具有不容忽视的安全风险。第二种方法相对复杂了很
-多，但是提供了更好的弹性、效率和安全性。
-
-system()
-^^^^^^^^
-
-这个system ()函数是C 标准库中提供的，它主要是提供了一种调用其它程序的简单方法。读者可以利用 system()函数调用一些应用程序，它产生的结果与从 shell 中执行这个程序基本相似。事实上， system()启动了一个运行着/bin/sh的子进程，然后将命令交由它执行。
-
-我们举个例子，在野火提供的application/system目录下，找到system.c文件，它里面的应用例程就是使用system()函数启动一个新进程ls，具体的代码如代码清单 37‑1所示：
-
-代码清单 37‑1 system.c文件源码
-
-1 #include <sys/types.h>
-
-2 #include <unistd.h>
-
-3 #include <stdio.h>
-
-4 #include <stdlib.h>
-
-5
-
-6 int main(void)
-
-7 {
-
-8 pid_t result;
-
-9
-
-10 printf("This is a system demo!\n\n");
-
-11
-
-12 /*调用 system()函数*/
-
-13 result = system("ls -l");
-
-14
-
-15 printf("Done!\n\n");
-
-16
-
-17 return result;
-
-18 }
-
-在代码的第13行，就调用了这个system()函数，并且传入了一个命令“ls -l”这个命令与在shell中运行的结果是一样的，调用 system() 函数的返回值就是被调用的 shell 命令的返回值。如果系统中 shell 自身无法运行，system() 函数返回 127；如果出现了其它错误，
-system ()函数将返回 -1，为了简单，作者在这个例子中并没有检查system调用是否能够真正的工作。因为 system() 函数使用 shell 调用命令，它受到系统 shell 自身的功能特性和安全缺陷的限制，因此， 作者并不推荐使用这种方法去启动一个进程。
-
-我们可以尝试编译它，在application/system目录下还会提供对应编译的Makefile文件，这是一个通用的Makefile文件，所有application的例程都使用这个Makefile文件编译，具体见代码清单 37‑2。
-
-代码清单 37‑2 Makefile源码
-
-1 # Makefile
-
-2
-
-3 CC = gcc
-
-4 SRC = $(wildcard \*.c \*/*.c)
-
-5 OBJS = $(patsubst %.c, %.o, $(SRC))
-
-6 DEP_FILES := $(patsubst %, .%.d,$(OBJS))
-
-7 DEP_FILES := $(wildcard $(DEP_FILES))
-
-8 FLAG = -g -Werror -I.
--Iinclude
-
-9 TARGET = targets
-
-10
-
-11 $(TARGET):$(OBJS)
-
-12 $(CC) -o $@ $^ $(FLAG)
-
-13
-
-14 ifneq ($(DEP_FILES),)
-
-15 include $(DEP_FILES)
-
-16 endif
-
-17
-
-18 %.o:%.c
-
-19 $(CC) -o $@ -c $(FLAG) $< -g -MD -MF .$@.d
-
-20
-
-21 clean:
-
-22 rm -rf $(TARGET) $(OBJS)
-
-23
-
-24 distclean:
-
-25 rm -rf $(DEP_FILES)
-
-26
-
-27 .PHONY:clean
-
-解释一下Makefile文件中的代码含义：
-
--  第3行指定编译器为 gcc，可以根据需要修改为 g++ 或者 arm-linux-gcc 等交叉编译工具链，使用CC变量保存。
-
--  第4行是为了获取匹配模式的文件名，*.c 表示当前工程目录的 c 文件，*/*.c 表示所有下一级目录的 .c 文件，这些文件名保存在SRC变量中。
-
--  第5行是将 $(SRC) 中的 .c 文件都替换成对应的目标 .o 文件，并且保存在OBJS变量中。
-
--  第6 - 7行将根据是有的目标文件替换成 .o.d 文件（隐藏的依赖文件），并且通过DEP_FILES变量保存。
-
--  第8行用于指定编译选项并且保存在FLAG变量中，读者根据需要添加，比如 -g、-ml、-Wall、-O2 等等，在这里作者提个小建议，编译选项最后选上-Werror，这个选项的含义是存在警告就会报错，它会使我们的代码更加严谨。
-
--  第9行指定最终生成的可执行文件名为targets。
-
--  第11行的$(TARGET):$(OBJS) 表示由 .o 文件链接成可执行文件。
-
--  注意第12行前面是一个 <tab> 键，而 $@ 表示目标，也就是 $(TARGET)，$^ 表示依赖目标，也就是 $(OBJS) ，编译选项则是$(FLAG)。
-
--  第14 - 16行则是判断，判断依赖文件是否存在，如果不存在则需要包含DEP_FILES变量。
-
--  第18行表示将所有的.c文件编译编译成.o文件 。
-
--  第19行的开头也是一个<tab> 键，$< 表示搜索到的第一个匹配的文件，而接下来的-g -MD -MF则是编译器的语法，-g表示以操作系统的本地格式产生调试信息，GDB能够使用这些调试信息进行调试； -MD
-  -MF则表示生成文件的依赖关系，同时也把一些标准库的头文件包含了进来。本质是告诉预处理器输出一个适合 make 的规则，用于描述各目标文件的依赖关系。
-
--  第21 – 25行表示清除相关的依赖文件，目标文件等。
-
--  “.PHONY”表示clean是个伪目标文件。
-
-进入application/system目录下，运行make命令将system.c编译，然后可以看到application/system目录下多了一个可执行文件——target，然后运行这个文件，可以看到调用system()函数启动一个进程输出的结果，它与我们在shell终端中执行ls
-–l命令产生的结果是一致的，具体见图 37‑7。
-
-命令
-
-make
-
-输出：
-
-gcc -o system.o -c -g -Werror -I.
--Iinclude system.c -g -MD -MF .system.o.dgcc -o targets system.o -g -Werror -I.
-–Iinclude
-
-生成target可执行文件
-
-|proces008|
-
-图 37‑7 system()函数运行结果与ls命令运行结果
-
-从程序运行的结果可以看到，只有当system()函数运行完毕之后，才会输出Done，这是因为程序从上往下执行，而无法直接返回结果。虽然system()函数很有用，但它也有局限性，因为程序必须等待由system()函数启动的进程结束之后才能继续，因此我们不能立刻执行其他任务。
-
-当然，你也可以让“ls -l”命令在后台运行，只需在命令结束位置加上“ &”即可，具体命令如下：
-
-命令
-
-ls –l &
-
-如果在system()函数中使用这个命令，它也是可以在后台中运行的，那么system()函数的调用将在shell命令结束后立刻返回。由于它是一个在后台运行程序的请求，所以ps程序一启动shell就返回了，代码如代码清单 37‑3所示。
-
-代码清单 37‑3 修改system.c源码
-
-1 #include <sys/types.h>
-
-2 #include <unistd.h>
-
-3 #include <stdio.h>
-
-4 #include <stdlib.h>
-
-5
-
-6 int main(void)
-
-7 {
-
-8 pid_t result;
-
-9
-
-10 printf("This is a system demo!\n\n");
-
-11
-
-12 /*调用 system()函数*/
-
-13 result = system("ls -l &");
-
-14
-
-15 printf("Done!\n\n");
-
-16
-
-17 return result;
-
-18 }
-
-重新make编译，然后运行程序，实验现象具体见图 37‑8。
-
-|proces009|
-
-图 37‑8 system后台运行
-
-从图 37‑8就可以看出来，在ls命令还未来得及打印出它的所有输出结果之前， system()函数就程序就打印出字符串Done然后退出了。在system()程序退出后，ls命令继续完成它的输出。这类的处理行为往往会给用户带来很大的困惑，也不一定如用户所预料的结果一致，因此如果读者想要让进程按照自己的
-意愿执行，就需要能够对它们的行为做更细致的控制，接下来作者就会讲解其他方式启动新的进程。
-
-fork()
-^^^^^^
-
-在前面的文章我们也了解到，init进程可以启动一个子进程，它通过fork()函数从原程序中创建一个完全分离的子进程，当然，这只是init进程启动子进程的第一步，后续还有其他操作的。不管怎么说，fork()函数就是可以启动一个子进程，其示意图具体见图 37‑9。
-
-在父进程中的fork()调用后返回的是新的子进程的PID。新进程将继续执行，就像原进程一样，不同之处在于，子进程中的fork()函数调用后返回的是0，父子进程可以通过返回的值来判断究竟谁是父进程，谁是子进程。
-
-|proces010|
-
-图 37‑9 fork()示意图
-
-fork()函数用于从一个已存在的进程中启动一个新进程，新进程称为子进程，而原进程称为父进程。使用
-fork()函数的本质是将父进程的内容复制一份，正如细胞分裂一样，得到的是几乎两个完全一样的细胞，因此这个启动的子进程基本上是父进程的一个复制品，但子进程与父进程有不一样的地方，作者就简单列举一下它们的联系与区别。
-
-与父进程一致的内容：
-
--  进程的地址空间。
-
--  进程上下文、代码段。
-
--  进程堆空间、栈空间，内存信息。
-
--  进程的环境变量。
-
--  标准 IO 的缓冲区。
-
--  打开的文件描述符。
-
--  信号响应函数。
-
--  当前工作路径。
-
-子进程独有的内容：
-
--  进程号 PID。 PID 是身份证号码，是进程的唯一标识符。
-
--  记录锁。父进程对某文件加了把锁，子进程不会继承这把锁。
-
--  挂起的信号。这些信号是已经响应但尚未处理的信号，也就是“悬挂”的信号，子进程也不会继承这些信号。
-
-因为子进程几乎是父进程的完全复制，所以父子两个进程会运行同一个程序，但是这种复制有一个很大的问题，那就是资源与时间都会消耗很大，当发出fork()系统调用时，内核原样复制父进程的整个地址空间并把复制的那一份分配给子进程。这种行为是非常耗时的，因为它需要做一些事情：
-
--  为子进程的页表分配页面。
-
--  为子进程的页分配页面。
-
--  初始化子进程的页表。
-
--  把父进程的页复制到子进程相应的页中
-
-创建一个地址空间的这种方法涉及许多内存访问，消耗许多CPU周期，并且完全破坏了高速缓存中的内容，因此直接复制物理内存对系统的开销会产生很大的影响，更重要的是在大多数情况下，这样直接拷贝通常是毫无意义的，因为许多子进程通过装入一个新的程序开始它们的执行，这样就完全丢弃了所继承的地址空间。因此在linu
-x中引入一种写时复制技术（Copy On Write，简称COW ），我们知道，linux系统中的进程都是使用虚拟内存地址，虚拟地址与真实物理地址之间是有一个对应关系的，每个进程都有自己的虚拟地址空间，而操作虚拟地址明显比直接操作物理内存更加简便快捷，那么显而易见的，写时复制是一种可以推迟甚至避免复
-制数据的技术。内核此时并不复制整个进程的地址空间，而是让父子进程共享同一个地址空间（页面）。
-
-那么写时复制的思想就是在于：父进程和子进程共享页面而不是复制页面。而共享页面就不能被修改，无论父进程和子进程何时试图向一个共享的页面写入内容时，都会产生一个错误，这时内核就把这个页复制到一个新的页面中并标记为可写。原来的页面仍然是写保护的，当还有进程试图写入时，内核检查写进程是否是这个页面的唯一属主
-，如果是则把这个页面标记为对这个进程是可写的。
-
-总的来说，写时复制只会用在需要写入的时候才会复制地址空间，从而使各个进行拥有各自的地址空间，资源的复制是在需要写入的时候才会进行，在此之前，父进程与子进程都是以只读方式共享页面，这种技术使地址空间上的页的拷贝被推迟到实际发生写入的时候。而在绝大多数的时候共享的页面根本不会被写入，例如，在调用fork
-()函数后立即执行exec()，地址空间就无需被复制了，这样一来fork()的实际开销就是复制父进程的页表以及给子进程创建一个进程描述符。
-
-理论相关的知识就讲解到这里就好了，作者也不打算再深入讲解，下面就看看fork()函数的使用，它的函数原型如下：
-
-pid_t fork(void);
-
-在fork()启动新的进程后，子进程与父进程开始并发执行，谁先执行由内核调度算法来决定。fork()函数如果成功启动了进程，会对父子进程各返回一次，其中对父进程返回子进程的 PID，对子进程返回
-0；如果fork()函数启动子进程失败，它将返回-1。失败通常是因为父进程所拥有的子进程数目超过了规定的限制（CHILD_MAX），此时errno将被设为EAGAIN。如果是因为进程表里没有足够的空间用于创建新的表单或虚拟内存不足， errno变量将被设为ENOMEM。
-
-在野火提供的application/fork目录下，找到fork.c文件，它里面的应用例程就是使用fork()函数启动一个新进程，并且在进程中打印相关的信息，如在父进程中打印出“In father process!!”等信息，例程源码具体见代码清单 37‑4。
-
-代码清单 37‑4 fork.c源码
-
-1 #include <sys/types.h>
-
-2 #include <unistd.h>
-
-3 #include <stdio.h>
-
-4 #include <stdlib.h>
-
-5 int main(void)
-
-6 {
-
-7 pid_t result;
-
-8
-
-9 printf("This is a fork demo!\n\n");
-
-10
-
-11 /*调用 fork()函数*/
-
-12 result = fork();
-
-13
-
-14 /*通过 result 的值来判断 fork()函数的返回情况，首先进行出错处理*/
-
-15 if (result == -1) {
-
-16 printf("Fork error\n");
-
-17 }
-
-18
-
-19 /*返回值为 0 代表子进程*/
-
-20 else if (result == 0) {
-
-21 printf("The returned value is %d, \\
-
-22 In child process!! \\
-
-23 My PID is %d\n\n", result, getpid());
-
-24
-
-25 }
-
-26
-
-27 /*返回值大于 0 代表父进程*/
-
-28 else {
-
-29 printf("The returned value is %d, \\
-
-30 In father process!! \\
-
-31 My PID is %d\n\n", result, getpid());
-
-32 }
-
-33
-
-34 return result;
-
-35 }
-
-我们来分析一下这段代码：
-
--  首先在第12行的时候调用了fork函数，调用fork函数后系统就会启动一个子进程，并且子进程与父进程执行的内容是一样的（代码段），读者可以通过返回值result判断fork()函数的执行结果。
-
--  如果result的值为-1，那代表着fork()函数执行出错，出错的原因在前文也提到，在此具体不细说。
-
--  如果返回的值为0，则表示此时执行的代码是子进程，那么就打印返回的结果、“In child process!!”与子进程的PID，进程的PID通过getpid()函数获取得到。
-
--  如果返回的值大于0，则表示此时执行的代码是父进程，同样也打印出返回的结果、“In father process!!”与父进程的PID。
-
-在application/fork目录下也提供了对应的Makefile文件，可以直接运行make进行编译，然后执行编译后生成的可执行文件“targets”，现象具体见图 37‑10。
-
-|proces011|
-
-图 37‑10 fork实验现象
-
-细心的同学就会发现，在这个实验现象中，父进程的返回值就是子进程的PID，而子进程的返回值则是0。
-
-exce系列函数
-^^^^^^^^
-
-事实上，使用fork()函数启动一个子进程是并没有太大作用的，因为子进程跟父进程都是一样的，子进程能干的活父进程也一样能干，因此世界各地的开发者就想方设法让子进程做不一样的事情，因此就诞生了exce系列函数，这个系列函数主要是用于替换进程的执行程序，它可以根据指定的文件名或目录名找到可执行文件，并用
-它来取代原调用进程的数据段、代码段和堆栈段，在执行完之后，原调用进程的内容除了进程号外，其他全部被新程序的内容替换。另外，这里的可执行文件既可以是二进制文件，也可以是Linux下任何可执行脚本文件。简单来说就是覆盖进程，举个例子，A进程调用exce系列函数启动一个进程B，此时进程B会替换进程A，进程
-A的内存空间、数据段、代码段等内容都将被进程B占用，进程A将不复存在。
-
-exec 族函数有 6 个不同的 exec 函数，函数原型分别如下：
-
- int execl(const char *path, const char *arg, ...)
-
-int execlp(const char *file, const char *arg, ...)
-
- int execle(const char *path, const char *arg, ..., char *const envp[])
-
- int execv(const char *path, char *const argv[])
-
- int execvp(const char *file, char *const argv[])
-
- int execve(const char *path, char *const argv[], char *const envp[])
-
-这些函数可以分为两大类， execl、 execlp和execle的参数个数是可变的。 execv、execvp和execve的第2个参数是一个字符串数组，参数以一个空指针NULL结束，无论何种函数，在调用的时候都会通过参数将这些内容传递进去，传入的参数一般都是要运行的程序（可执行文件）、脚本等。
-
-总结来说，可以通过它们的后缀来区分他们的作用：
-
--  名称包含 l 字母的函数（execl、 execlp 和 execle）接收参数列表“list”作为调用程序的参数。
-
--  名称包含 p 字母的函数（execvp 和 execlp）接受一个程序名作为参数，然后在当前的执行路径中搜索并执行这个程序；名字不包含 p 字母的函数在调用时必须指定程序的完整路径，其实就是在系统环境变量“PATH”搜索可执行文件。
-
--  名称包含 v 字母的函数（execv、execvp 和 execve）的命令参数通过一个数组“vector”传入。
-
--  名称包含 e 字母的函数（execve 和 execle）比其它函数多接收一个指明环境变量列表的参数，并且可以通过参数envp传递字符串数组作为新程序的环境变量，这个envp参数的格式应为一个以 NULL 指针作为结束标记的字符串数组，每个字符串应该表示为“environment =
-  virables”的形式。
-
-下面作者就具体某个函数做介绍：
-
- 函数
-
-int execl(const char *path, const char *arg, ...)
-
-execl()函数用于执行参数path字符串所代表的文件路径（必须指定路径），接下来是一系列可变参数，它们代表执行该文件时传递过去的argv[0]、argv[1] … argv[n]，最后一个参数必须用空指针NULL作为结束的标志。
-
-代码清单 37‑5 execl()函数实例
-
-1 int main(void)
-
-2 {
-
-3     int err;
-
-4
-
-5     printf("this is a execl function test demo!\n\n");
-
-6
-
-7     err = execl("/bin/ls", "ls", "-la", NULL);
-
-8
-
-9     if  (err < 0)  {
-
-10         printf("execl fail!\n\n");
-
-11
-
-12 }
-
-13 }
-
-如以上的execlp()函数实例代码，它其实就是与我们在终端上运行“ls -la”产生的结果是一样的。
-
-函数
-
-int execlp(const char *file, const char *arg, ...)
-
-execlp()函数会从PATH 环境变量所指的目录中查找符合参数file的文件名（不需要指定路径），找到后便执行该文件，然后将第二个以后的参数当做该文件的argv[0]、argv[1] … argv[n]， 最后一个参数必须用空指针NULL作为结束的标志。
-
-代码清单 37‑6 execlp()函数实例
-
-1 int main(void)
-
-2 {
-
-3 int err;
-
-4
-
-5 printf("this is a execlp function test demo!\n\n");
-
-6
-
-7 err = execlp("ls", "ls", "-la", NULL);
-
-8
-
-9 if (err < 0) {
-
-10 printf("execlp fail!\n\n");
-
-11 }
-
-12 }
-
-函数
-
-int execle(const char *path, const char *arg, ..., char *const envp[])
-
-execle()函数用于执行参数path字符串所代表的文件路径（必须指定路径），并为新程序复制最后一个参数所指示的环境变量（envp）。
-
-代码清单 37‑7 execle()函数实例
-
-1 int main(void)
-
-2 {
-
-3 int err;
-
-4
-
-5
-
-6
-
-7 char \*envp[] = {
-
-8 "/bin", NULL
-
-9 };
-
-10
-
-11 printf("this is a execle function test demo!\n\n");
-
-12
-
-13 err = execle("/bin/ls", "ls", "-la" , NULL, envp);
-
-14
-
-15 if (err < 0) {
-
-16 printf("execle fail!\n\n");
-
-17 }
-
-18 }
-
-函数
-
-int execv(const char *path, char *const argv[])
-
-execv()函数用于执行参数path字符串所代表的文件路径（必须指定路径），接着传入一个数组作为执行该文件时传递过去的参数argv[0]、argv[1] … argv[n]，以空指针NULL结束。
-
-代码清单 37‑8 execv()函数实例
-
-1 int main(void)
-
-2 {
-
-3 int err;
-
-4 char \*argv[] = {
-
-5 "ls", "-la", NULL
-
-6 };
-
-7
-
-8 printf("this is a execv function test demo!\n\n");
-
-9
-
-10 err = execv("/bin/ls", argv);
-
-11
-
-12 if (err < 0) {
-
-13 printf("execv fail!\n\n");
-
-14 }
-
-15 }
-
-函数
-
-int execvp(const char *path, char *const argv[])
-
-execvp()函数会从PATH 环境变量所指的目录中查找符合参数file的文件名（不需要指定路径），找到该文件后便执行该文件，接着传入一个数组作为执行该文件时传递过去的参数argv[0]、argv[1] … argv[n]，以空指针NULL结束。
-
-代码清单 37‑9 execvp()函数实例
-
-1 int main(void)
-
-2 {
-
-3 int err;
-
-4 char \*argv[] = {
-
-5 "ls", "-la", NULL
-
-6 };
-
-7
-
-8 printf("this is a execvp function test demo!\n\n");
-
-9
-
-10 err = execvp("ls", argv);
-
-11
-
-12 if (err < 0) {
-
-13 printf("execvp fail!\n\n");
-
-14 }
-
-15 }
-
-函数
-
-int execve(const char *path, char *const argv[], char *const envp[])
-
-execve ()函数用于执行参数path字符串所代表的文件路径（必须指定路径），执行该文件时会传入一个数组作为执行该文件时传递过去的参数argv[0]、argv[1] … argv[n]，除此之外该函数还会为新程序复制最后一个参数所指示的环境变量（envp）。
-
-代码清单 37‑10 execve ()函数实例
-
-1 int main(void)
-
-2 {
-
-3 int err;
-
-4 char \*argv[] = {
-
-5 "ls", "-la", NULL
-
-6 };
-
-7 char \*envp[] = {
-
-8 "/bin", NULL
-
-9 };
-
-10
-
-11 printf("this is a execve function test demo!\n\n");
-
-12
-
-13 err = execve("/bin/ls", argv, envp);
-
-14
-
-15 if (err < 0) {
-
-16 printf("execve fail!\n\n");
-
-17 }
-
-18 }
-
-以上函数实例代码均在application/exce目录下，选择对应的代码进行编译即可，该目录也提供了对应的Makefile文件，可以直接运行make进行编译，然后执行编译后生成的可执行文件“targets”，具体现象如图 37‑11所示。
-
-|proces012|
-
-图 37‑11 exce系列函数实验现象
-
-程序先打印出它的第一条消息“this is a execl function test demo!”，接着调用exec系列函数（实验中使用execl()函数），这个函数在/bin/ls目录中搜索程序ls，然后用这个程序替换targets程序，这与直接在终端中使用以下所示的shell命令一样，如图
-37‑12所示。
-
-命令
-
-ls -la
-
-|proces013|
-
-图 37‑12 ls –la命令
-
-注意，exce系列函数是直接将当前进程给替换掉的，当调用exce系列函数后，当前进程将不会再继续执行，我们可以测试一下，在调用exce系列函数后再打印一句话，具体代码如代码清单 37‑11加粗部分所示。
-
-代码清单 37‑11 exce系列函数测试代码
-
-1 int main(void)
-
-2 {
-
-3 int err;
-
-4
-
-5 printf("this is a execl function test demo!\n\n");
-
-6
-
-7 err = execl("/bin/ls", "ls", "-la", NULL);
-
-8
-
-9 if (err < 0) {
-
-10 printf("execl fail!\n\n");
-
-11 }
-
-12
-
-**13 printf("Done!\n\n");**
-
-14 }
-
-在程序运行后，“\ **Done!**\ ”将不被输出，因为当前进程已经被替换了，一般情况下， exec系列函数函数是不会返回的，除非发生了错误。出现错误时， exec系列函数将返回-1，并且会设置错误变量errno。
-
-因此我们可以通过调用fork()复制启动一个子进程，并且在子进程中调用exec系列函数替换子进程，这样子 fork()和exec系列函数结合在一起使用就是创建一个新进程所需要的一切了。
-
-终止进程
-~~~~
-
-在linux系统中，进程终止（或者称为进程退出，为了统一，下文均使用“终止”一词）的常见方式有5种，可以分为正常终止与异常终止：
-
-正常终止：
-
-1. 从main函数返回。
-
-2. 调用exit()函数终止。
-
-3. 调用_exit()函数终止。
-
-..
-
-   异常终止：
-
-4. 调用abort()函数异常终止。
-
-5. 由系统信号终止。
-
-在linux系统中，exit()函数定义在stdlib.h中，而_exit()定义在unistd.h中，exit()和_exit()函数都是用来终止进程的，当程序执行到 exit()或_exit()函数时，进程会无条件地停止剩下的所有操作，清除包括 PCB
-在内的各种数据结构，并终止当前进程的运行。不过这两个函数还是有区别的，具体如图 37‑13所示。
-
-|proces014|
-
-图 37‑13 exit()和_exit()函数的区别
-
-从图中可以看出， \_exit()函数的作用最为简单：直接通过系统调用使进程终止运行，当然，在终止进程的时候会清除这个进程使用的内存空间，并销毁它在内核中的各种数据结构；而exit()
-函数则在这些基础上做了一些包装，在执行退出之前加了若干道工序：比如exit()函数在调用exit系统调用之前要检查文件的打开情况，把文件缓冲区中的内容写回文件，这就是“清除I/O缓冲”。
-
-由于在 Linux 的标准函数库中，有一种被称作“缓冲 I/O（buffered I/O）”操作，其特征就是对应每一个打开的文件，在内存中都有一片缓冲区。每次读文件时，会连续读出若干条记录，这样在下次读文件时就可以直接从内存的缓冲区中读取；同样，每次写文件的时候，也仅仅是写入内存中的缓冲区，等满足了
-一定的条件（如达到一定数量或遇到特定字符等），再将缓冲区中的内容一次性写入文件。这种技术大大增加了文件读写的速度，但也为编程带来了一些麻烦。比如有些数据，认为已经被写入文件中，实际上因为没有满足特定的条件，它们还只是被保存在缓冲区内，这时用_exit()函数直接将进程关闭，缓冲区中的数据就会丢失。因
-此，若想保证数据的完整性，就一定要使用 exit()函数。
-
-不管 是那种 退出方式，系统最终都会执行内核中的同一代码，这段代码用来关闭进程所用已打开的文件描述符，释放它所占用的内存和其他资源。
-
-下面一起看看_exit()与exit()函数的使用方法：
-
-头文件
-
-#include <unistd.h>#include <stdlib.h>
-
-函数原型void \_exit(int status);void exit(int status);
-
-这两个函数都会传入一个参数status，这个参数表示的是进程终止时的状态码，0表示正常终止，其他非0值表示异常终止，一般都可以使用-1或者1表示，标准C里有EXIT_SUCCESS和EXIT_FAILURE两个宏，表示正常与异常终止。
-
-这些函数的使用都是非常简单的，只需要在需要终止的地方调用一下即可，此处就不深入讲解。
-
-等待进程
-~~~~
-
-在linux中，当我们使用fork()函数启动一个子进程时，子进程就有了它自己的生命周期并将独立运行，在某些时候，可能父进程希望知道一个子进程何时结束，或者想要知道子进程结束的状态，甚至是等待着子进程结束，那么我们可以通过在父进程中调用wait()或者waitpid()函数让父进程等待子进程的结束。
-
-从前面的文章我们也了解到，当一个进程调用了exit()之后，该进程并不会立刻完全消失，而是变成了一个僵尸进程。僵尸进程是一种非常特殊的进程，它已经放弃了几乎所有的内存空间，没有任何可执行代码，也不能被调度，仅仅在进程列表中保留一个位置，记载该进程的退出状态等信息供其他进程收集，除此之外，僵尸进程不再
-占有任何内存空间。那么无论如何，父进程都要回收这个僵尸进程，因此调用wait()或者waitpid()函数其实就是将这些僵尸进程回收，释放僵尸进程占有的内存空间，并且了解一下进程终止的状态信息。
-
-我们可以在终端中通过man命令查看关于wait相关的函数，具体命令如下：
-
-命令
-
-man 2 wait
-
-输出
-
-NAME wait, waitpid, waitid - wait for process to change stateSYNOPSIS #include <sys/types.h> #include <sys/wait.h> pid_t wait(int \*wstatus); pid_t
-waitpid(pid_t pid, int \*wstatus, int options);
-
-…….(省略其他)
-
-可能很多读者对man命令不了解，那我就简单说一下man命令相关的内容吧，其实在linux系统中是提供了丰富的帮助手册，当你需要查看某个命令的参数时不必到处上网查找，只要man一下即可，man命令是就是用于找出这些帮助手册的内容的，比如有什么shell命令，有什么可以调用的函数 等等。
-
-man 命令是按照章节存储的，linux的man手册共有8个章节，具体见表格 37‑2。
-
-表格 37‑2 man 命令说明
-
-======== ====================== =========================================
-章节编号 章节名称               章节主要内容
-======== ====================== =========================================
-1        General Commands       用户在shell中可以操作的指令或者可执行文档
-2        System Calls           系统调用的函数与工具等
-3        Sunroutines            C语言库函数
-4        Special Files          设备或者特殊文件
-5        File Formats           文件格式与规则
-6        Games                  游戏及其他
-7        Macros and Conventions 表示宏、包及其他杂项
-8        Maintenence Commands   表示系统管理员相关的命令
-======== ====================== =========================================
-
-例如我们想找与wait相关的函数，那么我们只需要输入以下命令即可：
-
-man 2 wait
-
-例如我们想要了解ls命令相关的内容，我们可以直接输入以下命令，就可以看到关于ls相关的用法等内容。
-
-命令
-
-man ls
-
-输出
-
-NAME ls - list directory contentsSYNOPSIS ls [OPTION]...
-[FILE]...DESCRIPTION List information about the FILEs (the current directory by default).
-Sort entries alphabetically if none of -cftuvSUX nor --sort is specified.
-Mandatory arguments to long options are mandatory for short options too.
--a, --all do not ignore entries starting with.
--A, --almost-all do not list implied.
-and ..
---author with -l, print the author of each file -b, --escape print C-style escapes for nongraphic characters
-
-…….(省略其他)
-
-当然啦，man手册是英文的，这是属于全世界通用的技术交流语言，因此读者还是需要对英文有一定熟悉程度。
-
-wait()
-^^^^^^
-
-我们通过man命令就知道了wait()、waitpid()函数原型，那么我们就首先了解下wait()函数。
-
-函数原型
-
-pid_t wait(int \*wstatus);
-
-wait()函数在被调用的时候，系统将暂停父进程的执行，直到有信号来到或子进程结束，如果在调用wait()函数时子进程已经结束，则会立即返回子进程结束状态值。子进程的结束状态信息会由参数wstatus返回，与此同时该函数会返子进程的PID，它通常是已经结束运行的子进程的PID。状态信息允许父进程了解
-子进程的退出状态，如果不在意子进程的结束状态信息，则参数wstatus可以设成NULL。
-
-wait()函数有几点需要注意的地方：
-
-1. wait()要与fork()配套出现，如果在使用fork()之前调用wait()，wait()的返回值则为-1，正常情况下wait()的返回值为子进程的PID。
-
-2. 参数wstatus用来保存被收集进程退出时的一些状态，它是一个指向int类型的指针，但如果我们对这个子进程是如何死掉毫不在意，只想把这个僵尸进程消灭掉，（事实上绝大多数情况下，我们都会这样做），我们就可以设定这个参数为NULL。
-
-当然，除此之外，linux系统中还提供关于等待子进程退出的一些宏定义，我们可以使用这些宏定义来直接判断子进程退出的状态：
-
-WIFEXITED(status) ：如果子进程正常结束，返回一个非零值
-
-WEXITSTATUS(status)： 如果WIFEXITED非零，返回子进程退出码
-
-WIFSIGNALED(status) ：子进程因为捕获信号而终止，返回非零值
-
-WTERMSIG(status) ：如果WIFSIGNALED非零，返回信号代码
-
-WIFSTOPPED(status)： 如果子进程被暂停，返回一个非零值
-
-WSTOPSIG(status)： 如果WIFSTOPPED非零，返回一个信号代码
-
-wait()函数使用实例如下：
-
-代码清单 37‑12 wait()函数使用实例
-
-1 int main()
-
-2 {
-
-3 pid_t pid, child_pid;
-
-4 int status;
-
-5
-
-6 pid = fork(); **(1)**
-
-7
-
-8 if (pid < 0) {
-
-9 printf("Error fork\n");
-
-10 }
-
-11 /*子进程*/
-
-12 else if (pid == 0) { **(2)**
-
-13
-
-14 printf("I am a child process!, my pid is %d!\n\n",getpid());
-
-15
-
-16 /*子进程暂停 3s*/
-
-17 sleep(3);
-
-18
-
-19 printf("I am about to quit the process!\n\n");
-
-20
-
-21 /*子进程正常退出*/
-
-22 exit(0); **(3)**
-
-23 }
-
-24 /*父进程*/
-
-25 else {
-
-26
-
-27 /*调用 wait，父进程阻塞*/
-
-28 child_pid = wait(&status); **(4)**
-
-29
-
-30 /*若发现子进程退出，打印出相应情况*/
-
-31 if (child_pid == pid) { **(5)**
-
-32 printf("Get exit child process id: %d\n",child_pid);
-
-33 printf("Get child exit status: %d\n\n",status);
-
-34 } else {
-
-35 printf("Some error occured.\n\n");
-
-36 }
-
-37
-
-38 exit(0);
-
-39 }
-
-40 }
-
-我们来分析一下这段代码：
-
-代码清单 37‑12\ **(1)**\ ：首先调用fork()函数启动一个子进程。
-
-代码清单 37‑12\ **(2)**\ ：如果fork()函数返回的值pid 为0，则表示此时运行的是子进程，那么就让子进程输出一段信息，并且休眠3s。
-
-代码清单 37‑12\ **(3)**\ ：休眠结束后调用exit()函数退出，退出状态为0，表示子进程正常退出。
-
-代码清单 37‑12\ **(4)**\ ：如果fork()函数返回的值pid 不为0，则表示此时运行的是父进程，那么在父进程中调用wait(&status)函数等待子进程的退出，子进程的退出状态将保存在status变量中。
-
-代码清单 37‑12\ **(5)**\ ：若发现子进程退出（通过wait()函数返回的子进程pid判断），则打印出相应信息，如子进程的pid与status。
-
-以上函数实例代码在application/wait目录下，选择对应的代码进行编译即可，该目录也提供了对应的Makefile文件，可以直接运行make进行编译，然后执行编译后生成的可执行文件“targets”，执行结果如图 37‑14所示。
-
-|proces015|
-
-图 37‑14 wait()函数现象
-
-waitpid()
-^^^^^^^^^
-
-waitpid()函数 的作用和 wait()函数一样，但它并不一定要等待第一个终止的子进程，它还有其他选项，比如指定等待某个pid的子进程、提供一个非阻塞版本的 wait()功能等。实际上 wait()函数只是 waitpid() 函数的一个特例，在 linux 内部实现 wait
-函数时直接调用的就是 waitpid 函数。
-
-函数原型
-
-pid_t waitpid(pid_t pid, int \*wstatus, int options);
-
-waitpid()函数的参数有3个，下面就简单介绍这些参数相关的选项：
-
--  pid：参数pid为要等待的子进程ID，其具体含义如下：
-
-1. pid < -1：等待进程组号为pid绝对值的任何子进程。
-
-2. pid = -1：等待任何子进程，此时的waitpid()函数就等同于wait()函数。
-
-3. pid = 0：等待进程组号与目前进程相同的任何子进程，即等待任何与调用waitpid()函数的进程在同一个进程组的进程。
-
-4. pid > 0：等待指定进程号为pid的子进程。
-
--  wstatus：与wait()函数一样。
-
--  options：参数options提供了一些另外的选项来控制waitpid()函数的行为。如果不想使用这些选项，则可以把这个参数设为0。
-
-1. WNOHANG：如果pid指定的子进程没有终止运行，则waitpid()函数立即返回0，而不是阻塞在这个函数上等待；如果子进程已经终止运行，则立即返回该子进程的进程号与状态信息。
-
-2. WUNTRACED：如果子进程进入了暂停状态（可能子进程正处于被追踪等情况），则马上返回。
-
-3. WCONTINUED：如果子进程恢复通过SIGCONT信号运行，也会立即返回（这个不常用，了解一下即可）。
-
-很显然，当waitpid()函数的参数为(-1, status, 0)时， waitpid()函数就完全退化成了wait()函数。
-
-下面看一下waitpid()函数使用实例，具体见代码清单 37‑13。
-
-代码清单 37‑13 waitpid()函数使用实例
-
-1 int main()
-
-2 {
-
-3 pid_t pid, child_pid;
-
-4 int status;
-
-5
-
-6 pid = fork();
-
-7
-
-8 if (pid < 0) {
-
-9 printf("Error fork\n");
-
-10 }
-
-11 /*子进程*/
-
-12 else if (pid == 0) {
-
-13
-
-14 printf("I am a child process!, my pid is %d!\n\n",getpid());
-
-15
-
-16 /*子进程暂停 3s*/
-
-17 sleep(3);
-
-18
-
-19 printf("I am about to quit the process!\n\n");
-
-20 /*子进程正常退出*/
-
-21 exit(0);
-
-22 }
-
-23 /*父进程*/
-
-24 else {
-
-25
-
-**26 /*调用 waitpid()等待指定子进程，父进程阻塞*/**
-
-**27 child_pid = waitpid(pid, &status,0);**
-
-28
-
-29 /*若发现子进程退出，打印出相应情况*/
-
-30 if (child_pid == pid) {
-
-31 printf("Get exit child process id: %d\n",child_pid);
-
-32 printf("Get child exit status: %d\n\n",status);
-
-33 } else {
-
-34 printf("Some error occured.\n");
-
-35 }
-
-36
-
-37 exit(0);
-
-38 }
-
-39 }
-
-编译后运行，它的实验现象与wait()函数的是一样的。
-
-.. |proces002| image:: media/proces002.png
-   :width: 5.95555in
-   :height: 2.88806in
-.. |proces003| image:: media/proces003.png
-   :width: 5.20441in
-   :height: 2.63433in
-.. |proces004| image:: media/proces004.png
-   :width: 5.68657in
-   :height: 5.34303in
-.. |proces005| image:: media/proces005.png
-   :width: 4.60448in
-   :height: 2.61388in
-.. |proces006| image:: media/proces006.png
-   :width: 5.76806in
-   :height: 3.29165in
-.. |proces007| image:: media/proces007.png
-   :width: 5.70283in
-   :height: 4.95806in
-.. |proces008| image:: media/proces008.png
-   :width: 5.42109in
-   :height: 4.17911in
-.. |proces009| image:: media/proces009.png
-   :width: 5.36597in
-   :height: 1.84306in
-.. |proces010| image:: media/proces010.png
-   :width: 3.88276in
-   :height: 4.05224in
-.. |proces011| image:: media/proces011.png
-   :width: 5.00289in
-   :height: 3.74627in
-.. |proces012| image:: media/proces012.png
-   :width: 5.76806in
-   :height: 2.90055in
-.. |proces013| image:: media/proces013.png
-   :width: 4.99236in
-   :height: 1.81319in
-.. |proces014| image:: media/proces014.png
-   :width: 3.83569in
-   :height: 4.88806in
-.. |proces015| image:: media/proces015.png
-   :width: 5.38806in
-   :height: 2.5551in
diff --git a/documentation/system_programing/process.rst b/documentation/system_programing/process.rst
new file mode 100644
index 0000000000000000000000000000000000000000..06e0d7c49d513ef7ebe0afc0b1c3e0d7d1a89b35
--- /dev/null
+++ b/documentation/system_programing/process.rst
@@ -0,0 +1,1149 @@
+.. vim: syntax=rst
+
+进程
+====
+
+简单了解进程
+------------
+
+在进入正题之前，我们不打算像其他书籍一样，讲一大堆原理，而是希望想通过实验现象来引导读者了解进程相关的知识，紧接着再来补充进程相关的知识点。
+
+首先在虚拟机中打开一个终端（相信读者能阅读到此处，就已经了解什么是终端了，而由于作者用是的公司的服务器，使用ssh方式连接的，所以下文的截图有可能与读者的显示界面不是一样的，但这不会对本章的阅读造成任何影响），一般来说ubuntu中有很多shell终端，而这个终端就是一个进程，或许读者很可能打开多个终端，那么这些所有被打开的终端就一个个进程，这些进程是不一样的，独立运行在系统中，作者打开三个shell终端，这些终端各自有输入输出，互不干扰，如图37‑1所示。
+
+.. figure:: media/proces002.png
+   :alt: proces002
+
+   proces002
+
+
+每个运行中的 shell 都是一个单独的进程，假如读者从一个
+shell里面调用一个程序的时候，对应的程序在一个新进程中运行，运行结束后
+shell继续工作，高级的程序员经常在一个应用程序中同时启用多个协作的进程以使程序可以并行更多任务、使程序更健壮，或者可以直接利用已有的其它程序，这样子整个系统中运行的进程就可以相互配合，而不是独立运行，这就涉及到进程间的通信，这部分内容我们在后续讲解。
+
+查看进程
+--------
+
+即使读者刚打开Linux电脑，没有运行任何程序，电脑中也会有进程存在，因为系统中必须要有进程在处理一些必要的程序，以保证系统能正常运行。其实在Linux中是通过检查表记录与进程相关的信息的，进程表就像一个数据结构，它把当前加载在内存中的所有进程的有关信息保存在一个表中，其中包括进程的PID、进程的状态、命令字符串和其他一些ps命令输出的各类信息。操作系统通过进程的ID对它们进行管理，这些PID是进程表的索引，就目前的Linux系统而言，系统支持可以同时运行的进程数可能只与用于建立进程表项的内存容量有关，而没有具体的数量的限制，也就是说系统有足够的内存的话，那么理论上就可以运行无数个进程。
+
+进程ID
+~~~~~~
+
+Linux系统中的每个进程都都会被分配一个唯一的数字编号，我们称之为进程ID（ProcessID，通常也被简称为
+PID）。进程ID 是一个
+16位的正整数，默认取值范围是从2到32768（可以修改），由
+Linux在启动新进程的时候自动依次分配，当进程被启动时，系统将按顺序选择下一个未被使用的数字作为它的PID，当PID的数值达到最大时，系统将重新选择下一个未使用的数值，新的PID重新从2开始，这是因为PID数字为1的值一般是为特殊进程init保留，即系统在运行时就存在的第一个进程，
+init进程负责管理其他进程。
+
+父进程ID
+~~~~~~~~
+
+任何进程（除init进程）都是由另一个进程启动，该进程称为被启动进程的父进程，被启动的进程称为子进程，父进程号无
+法在用户层修改。父进程的进程号（PID）即为子进程的父进程号（PPID）。用户可以通过调用getppid()函数来获得当前进程的父进程号。
+
+为了更直观看到这些进程，作者就使用ps命令去查看系统中的进程情况，ps命令可以显示我们正在运行的进程、其他
+用户正在运行的进程或者目前在系统上运行的所有进程。输出结果如图37‑2所示，可以很明显看到，编号为1的进程是ini
+t进程。它位于 ``/sbin/init`` 目录中。当然，整个系统的进程可不止这一些，由于太多没法截图，就只展示这小部分的进程，读者可以自己使用下面命令去尝试一下，ps
+命令可以显示当前系统中运行的进程， 其实在Linux中，
+ps命令有很多选项，因为它试图与很多不同 UNIX 版本的
+ps命令兼容，这些选项决定显示哪些进程以及要显示的信息。
+
+**命令:**
+
+.. code:: bash
+
+    ps –aux
+
+.. figure:: media/proces003.png
+   :alt: proces003
+
+   proces003
+
+
+父进程与子进程
+~~~~~~~~~~~~~~
+
+进程启动时，启动进程为新进程的父进程，新进程是启动进程的子进程。
+
+每个进程都有一个父进程（除了系统中如"僵尸进程"这种特殊进程外），因此，读者可以把
+Linux 中的进程结构想象成一个树状结构，其中
+init进程就是树的“根”；或者可以把init进程看作为操作系统的进程管理器，它是其他所有进程的祖先进程。我们将要看到的
+其他系统进程要么是由init进程启动的，要么是由被init进程启动的其他进程启动的。
+
+总的来说init进程下有很多子进程，这些子进程又可能存在子进程，就像家族一样。系统中所有的父进
+程ID被称为PPID，不同进程的父进程是不同的，这个值只是当前进程的父进程的ID，系统中的父进程与子进
+程是相对而言的，就好比 ``爷爷<->爸爸<->儿子`` 之间的关系，爸爸相对于爷爷而言是儿子，相对于儿子而言则是爸爸。
+
+为了更加直观看出系统中父进程与子进程，作者决定使用 ``pstree`` 命令将进程以树状关系列出来，具体见图
+37‑3。
+
+**命令：**
+
+.. code:: bash
+
+    pstree
+
+.. figure:: media/proces004.png
+   :alt: proces004
+
+   proces004
+
+
+程序与进程
+----------
+
+进程相关信息也简单了解过了，可能很多读者还是有疑问，我们写的代码，它是程序，怎么变成进程了呢？那么在本小节作者就讲解一下程序与进程的关系。
+
+程序
+~~~~
+
+程序（program）是一个普通文件，是为了完成特定任务而准备好的指令序列与数据的集合，这些指令和数据以"可执行映像"的格式保存在磁盘中。正如我们所写的一些代码，经过编译器编译后，就会生成对应的可执行文件，那么这个就是程序，或者称之为可执行程序。
+
+
+进程
+~~~~
+
+进程（process）则是程序执行的具体实例，比如一个可执行文件，在执行的时候，它就是一个进程，直到该程序执
+行完毕。那么在程序执行的过程中，它享有系统的资源，至少包括进程的运行环境、CPU、外设、内存、进程ID等资源与
+信息，同样的一个程序，可以实例化为多个进程，在Linux系统下使用
+ps命令可以查看到当前正在执行的进程，当这个可执行程序运行完毕后，进程也会随之被销毁（可能不是立即销毁，但是总
+会被销毁）。
+
+程序并不能单独执行，只有将程序加载到内存中，系统为他分配资源后才能够执行，这种执行的程序称之为进程，也就是说进程
+是系统进行资源分配和调度的一个独立单位，每个进程都有自己单独的地址空间。
+
+举个例子，我们可以看到/bin目录下有很多可执行文件，如图37‑4所示，我们在系统中打开一个终端就是一个进程，这个进
+程由bash可执行文件（程序）实例化而来，而一个Linux系统可用打开多个终端，并且这些终端是独立运行在系统中的。
+
+.. figure:: media/proces005.png
+   :alt: proces005
+
+   proces005
+
+
+程序变成进程
+~~~~~~~~~~~~
+
+在Linux系统中，程序只是个静态的文件，而进程是一个动态的实体，进程
+的状态（后续讲解进程状态）会在运行过程中改变，那么问题来了，程序到底是如何变成一个进程的呢？
+
+其实正如我们运行一个程序（可执行文件），通常在
+Shell中输入命令运行就可以了，在这运行的过程中包含了程序到进
+程转换的过程，整个转换过程主要包含以下
+3 个步骤：
+
+1. 查找命令对应程序文件的位置。
+2. 使用 fork()函数为启动一个新进程。
+3. 在新进程中调用 exec
+   族函数装载程序文件，并执行程序文件中的main()函数。
+
+    补充：关于具体的函数介绍将在后续讲解。
+
+总结
+~~~~
+
+总的来说，程序与进程有以下的关系：
+
+1. 程序只是一系列指令序列与数据的集合，它本身没有任何运行的含义，它只是一个静态
+   的实体。而进程则不同，它是程序在某个数据集上的执行过程，它是一个动态运行的实体，有自己的生命周期，它因启动而产生，因调度而运行，因等待资源或事件而被处于等待状态，因完成任务而被销毁。
+
+2. 进程和程序并不是一一对应的，一个程序执行在不同的数据集上运行就会成为不同的进程，可以用进程控制块来唯一地标识系统中的每个进程。而这一点正是程序无法做到的，由于程序没有和数据产生直接的联系，既使是执行不同的数据的程序，他们的指令的集合依然是一样的，所以无法唯一地标识出这些运行于不同数据集上的程序。一般来说，一个进程肯定有一个与之对应的程序，而且有且只有一个。而一个程序有可能没有与之对应的进程（因为这个程序没有被运行），也有可能有多个进程与之对应（这个程序可能运行在多个不同的数据集上）。
+
+3. 进程具有并发性而程序没有。
+
+4. 进程是竞争计算机资源的基本单位，而程序不是。
+
+进程状态
+--------
+
+在学习进程状态之前，作者决定还是先让读者看看系统中常见的进程状态，可以通过ps命令将系统中运行的进程信息打印出来，我们只需要关注STAT那一列的信息即可，进程的状态非常多种，具体见图37‑5：
+
+**命令：**
+
+.. code:: bash
+
+    ps –ux
+
+    # 输出(已删减)：
+    USER   PID  %CPU  %MEM    VSZ   RSS   TTY      STAT   START    TIME     COMMAND
+    xxx    11132   0.0      0.0     15492  5568  pts/1    Ss      00:45    0:00       /bin/bash
+    xxx    11340   0.0      0.0     15508  5636  pts/2    Ss+    00:50    0:01       /bin/bash
+    xxx    11807   0.0      0.0     14916  4572  pts/3    Ss      01:05    0:00        /bin/bash
+    xxx    18319   0.0      0.0     18260   588  pts/1     Ss+     10月09   0:00      bash
+    xxx    21862   0.0      0.0      7928   824     ?         S         07:57    0:00      sleep 180
+    xxx    26124   0.0      0.0     29580  1540  pts/1     R+      07:58    0:00         ps -ux
+
+由于作者用的是公司服务器，所以只将作者用户当前的进程信息输出，而不是将系统所有进程信息输出，因此ps命令不需要 ``–a`` 选项。
+
+.. figure:: media/proces006.png
+   :alt: proces006
+
+   proces006
+图 37‑5 进程状态
+
+从图37‑5中可以看到进程的状态有比较多种，有些是S，有些是Ss，还有些是Sl、Rl、R+等状态，具体是什么含义呢？其实是这些状态只是Linux系统进程的一部分，还有一些状态是没有显示出来的，因为作者当前用户下的所有进程并没有处于那些状态，所以就没显示出来，下面作者就简单介绍一下Linux系统中所有的进程状态，如表格
+37‑1所示。
+
+表格 37‑1 Linux系统中进程状态说明
+
++--------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+| 状态   | 说明                                                                                                                                                                          |
++========+===============================================================================================================================================================================+
+| R      | 运行状态。严格来说，应该是"可运行状态"，即表示进程在运行队列中，处于正在执行或即将运行状态，只有在该状态的进程才可能在 CPU 上运行，而同一时刻可能有多个进程处于可运行状态。   |
++--------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+| S      | 可中断的睡眠状态。处于这个状态的进程因为等待某种事件的发生而被挂起，比如进程在等待信号。                                                                                      |
++--------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+| D      | 不可中断的睡眠状态。通常是在等待输入或输出（I/O）完成，处于这种状态的进程不能响应异步信号。                                                                                   |
++--------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+| T      | 停止状态。通常是被shell的工作信号控制，或因为它被追踪，进程正处于调试器的控制之下。                                                                                           |
++--------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+| Z      | 退出状态。进程成为僵尸进程。                                                                                                                                                  |
++--------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+| X      | 退出状态。进程即将被回收。                                                                                                                                                    |
++--------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+| s      | 进程是会话其首进程。                                                                                                                                                          |
++--------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+| l      | 进程是多线程的。                                                                                                                                                              |
++--------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+| +      | 进程属于前台进程组。                                                                                                                                                          |
++--------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+| <      | 高优先级任务。                                                                                                                                                                |
++--------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
+进程状态转换
+------------
+
+从前文的介绍我们也知道，进程是动态的活动的实例，这其实指的是进程会有很多种运行状态，一会儿睡眠、一会儿暂停、一会儿又继续执行。虽然Linux操作系统是一个多用户多任务的操作系统，但对于单核的CPU系统来说，在某一时刻，只能有一个进程处于运行状态（此处的运行状态指的是占用CPU），其他进程都处于其他状态，等待系统资源，各任务根据调度算法在这些状态之间不停地切换。但由于CPU处理速率较快，使用户感觉每个进程都是同时运行。
+
+图 37‑6
+展示了Linux进程从被启动到退出的全部状态，以及这些状态发生转换时的条件。
+
+.. figure:: media/proces007.png
+   :alt: proces007
+
+   proces007
+图 37‑6 进程状态转换
+
+1. 一般来说，一个进程的开始都是从其父进程调用fork()开始的，所以在系统一上电运行的时候，init进程就开始工作，在系统运行过程中，会不断启动新的进程，这些进程要么是由init进程启动的，要么是由被init进程启动的其他进程所启动的。
+
+2. 一个进程被启动后，都是处于可运行状态（但是此时进程并未占用CPU运行）。处于该状态的进程可以是正在进程等待队列中排队，也可以占用CPU正在运行，我们习惯上称前者为"就绪态"，称后者为"运行态"（占用CPU运行）。
+
+3. 当系统产生进程调度的时候，处于就绪态的进程可以占用CPU的使用权，此时进程就是处于运行态。但每个进程运行时间都是有限的，比如10毫秒，这段时间被称为"时间片"。当进程的时间片已经耗光了的情况下，如果进程还没有结束运行，那么会被系统重新放入等待队列中等待，此时进程又转变为就绪状态，等待下一次进程的调度。另外，正处于"运行态"的进程即使时间片没有耗光，也可能被别的更高优先级的进程"抢占"，被迫重新回到等到队列中等待。
+
+4. 处于"运行态"的进程可能会等待某些事件、信号或者资源而进入"可中断睡眠态"，比如进程要读取一个管道文件数据而管道为空，或者进程要获得一个锁资源而当前锁不可获取，甚至是进程自己调用sleep()来强制将自己进入睡眠，这些情况下进程的状态都会变成"可中断睡眠态"。顾名思义，"可中断睡眠态"就是可以被中断的，能响应信号，在特定条件发生后，进程状态就会转变为"就绪态"，比如其他进程想管道文件写入数据后，或者锁资源可以被获取，或者是睡眠时间到达等情况。
+
+5. 当然，处于"运行态"的进程还可能会进入"不可中断睡眠态"，在这种状态下的进程不能响应信号，但是这种状态非常短暂，读者几乎无法通过ps命令将其显示出来，一般处于这种状态的进程都是在等待输入或输出（I/O）完成，在等待完成后自动进入"就绪态"。
+
+6. 当进程收到 SIGSTOP 或者 SIGTSTP
+   中的其中一个信号时，进程状态会被置为"暂停态"，该状态下的进程不再参与调度，但系统资源不会被释放，直到收到SIGCONT信号后被重新置为就绪态。当进程被追踪时（典型情况是使用调试器调试应用程序的情况），收到任何信号状态都会被置为
+   TASK_TRACED状态，该状态跟暂停态是一样的，一直要等到
+   SIGCONT信号后进程才会重新参与系统进程调度。
+
+7. 进程在完成任务后会退出，那么此时进程状态就变为退出状态，这是正常的退出，比如在main函数内
+   return 或者调用
+   exit()函数或者线程调用pthread_exit()都是属于正常退出。为什么作者要强调正常退出呢？因为进程也会有异常退出，比如进程收到kill信号就会被杀死，其实不管怎么死，最后内核都会调用do_exit()函数来使得进程的状态变成"僵尸态（僵尸进程）"，这里的"僵尸"指的是进程的PCB（Process
+   Control
+   Block，进程控制块）。为什么一个进程的死掉之后还要把尸体（PCB）留下呢？因为进程在退出的时候，系统会将其退出信息都保存在进程控制块中，比如如果他正常退出，那进程的退出值是多少呢？如果被信号杀死？那么是哪个信号将其杀死呢？这些"死亡信息"都被一一封存在该进程的PCB当中，好让别人可以清楚地知道：我是怎么死的。那谁会关心他是怎么死的呢？那就是它的父进程，它的父进程之所以要启动它，很大的原因是要让这个进程去干某一件事情，现在这个孩子已死，那事情办得如何，因此需要把这些信息保存在进程控制块中，等着父进程去查看这些信息。
+8. 当父进程去处理僵尸进程的时候，会将这个僵尸进程的状态设置为EXIT_DEAD，即死亡态（退出态），这样子系统才能去回收僵尸进程的内存空间，否则系统将存在越来越多的僵尸进程，最后导致系统内存不足而崩溃。那么还有两个问题，假如父进程由于太忙而没能及时去处理僵尸进程的时候，要怎么处理呢？又假如在子进程变成"僵尸态"之前，它的父进程已经先它而去了（退出），那么这个子进程变成僵死态由谁处理呢？第一种情况可能不同的读者有不同的处理，父进程有别的事情要干，不能随时去处理僵尸进程。在这样的情形下，读者可以考虑使用信号异步通知机制，让一个孩子在变成僵尸的时候，给其父进程发一个信号，父进程接收到这个信号之后，再对其进行处理，在此之前父进程该干嘛就干嘛。而如果如果一个进程的父进程先退出，那么这个子进程将变成"孤儿进程"（没有父进程），那么这个进程将会被他的祖先进程收养（adopt），它的祖先进程是init（该进程是系统第一个运行的进程，他的
+   PCB是从内核的启动镜像文件中直接加载的，系统中的所有其他进程都是init进程的后代）。那么当子进程退出的时候，init进程将回收这些资源。
+
+启动新进程
+----------
+
+在Linux中启动一个进程有多种方法，比如可以使用system()函数，也可以使用fork()函数去启动（在其他的一些Linux书籍也称作创建进程，本书将全部称之为启动进程）一个新的进程，第一种方法相对简单，但是在使用之前应慎重考虑，因为它效率低下，而且具有不容忽视的安全风险。第二种方法相对复杂了很多，但是提供了更好的弹性、效率和安全性。
+
+system()
+~~~~~~~~
+
+这个system
+()函数是C标准库中提供的，它主要是提供了一种调用其它程序的简单方法。读者可以利用system()函数调用一些应用程序，它产生的结果与从
+shell中执行这个程序基本相似。事实上，system()启动了一个运行着/bin/sh的子进程，然后将命令交由它执行。
+
+我们举个例子，在野火提供的system_programing/system目录下，找到system.c文件，它里面的应用例程就是使用system()函数启动一个新进程ls，具体的代码如代码清单37‑1所示：
+
+代码清单 37‑1 system.c文件源码
+
+.. code:: c
+
+    #include <sys/types.h>
+    #include <unistd.h>
+    #include <stdio.h>
+    #include <stdlib.h>
+
+    int main(void)
+    {
+        pid_t result;
+
+        printf("This is a system demo!\n\n");
+
+        /*调用 system()函数*/
+        result = system("ls -l");
+
+        printf("Done!\n\n");
+
+        return result;
+    }
+
+在代码的第13行，就调用了这个system()函数，并且传入了一个命令"ls
+-l"这个命令与在shell中运行的结果是一样的，调用
+system()函数的返回值就是被调用的 shell 命令的返回值。如果系统中
+shell自身无法运行，system() 函数返回 127；如果出现了其它错误，
+system()函数将返回-1，为了简单，作者在这个例子中并没有检查system调用是否能够真正的工作。因为system()
+函数使用 shell 调用命令，它受到系统
+shell自身的功能特性和安全缺陷的限制，因此，作者并不推荐使用这种方法去启动一个进程。
+
+我们可以尝试编译它，在system_programing/system目录下还会提供对应编译的Makefile文件，这是一个通用的Makefile文件，所有application的例程都使用这个Makefile文件编译，具体见代码清单
+37‑2。
+
+代码清单 37‑2 Makefile源码
+
+.. code:: makefile
+
+    CC = gcc
+    SRC = $(wildcard *.c */*.c)
+    OBJS = $(patsubst %.c, %.o, $(SRC))
+    DEP_FILES := $(patsubst %, .%.d,$(OBJS))
+    DEP_FILES := $(wildcard $(DEP_FILES))
+    FLAG = -g -Werror -I. -Iinclude 
+    TARGET = targets
+
+    $(TARGET):$(OBJS)
+        $(CC) -o $@ $^ $(FLAG)
+
+    ifneq ($(DEP_FILES),)
+    include $(DEP_FILES)
+    endif
+
+    %.o:%.c
+        $(CC) -o $@ -c $(FLAG) $< -g -MD -MF .$@.d
+
+    clean:
+        rm -rf $(TARGET) $(OBJS)
+
+    distclean:
+        rm -rf $(DEP_FILES)
+
+    .PHONY:clean
+
+解释一下Makefile文件中的代码含义：
+
+-  第3行指定编译器为 ``gcc`` ，可以根据需要修改为 ``g++`` 或者
+   ``arm-Linux-gcc`` 等交叉编译工具链，使用CC变量保存。
+-  第4行是为了获取匹配模式的文件名， ``*.c`` 表示当前工程目录的
+   c文件， ``*/*.c`` 表示所有下一级目录的
+   ``.c`` 文件，这些文件名保存在SRC变量中。
+-  第5行是将 ``$(SRC)`` 中的 ``.c`` 文件都替换成对应的目标
+   ``.o`` 文件，并且保存在OBJS变量中。
+-  第6 - 7行将根据是有的目标文件替换成
+   ``.o.d`` 文件（隐藏的依赖文件），并且通过DEP_FILES变量保存。
+-  第8行用于指定编译选项并且保存在 ``FLAG`` 变量中，读者根据需要添加，比如 ``-g、-ml、-Wall、-O2`` 等等，在这里作者提个小建议，编译选项最后选上 ``-Werror`` ，这个选项的含义是存在警告就会报错，它会使我们的代码更加严谨。
+-  第9行指定最终生成的可执行文件名为 ``targets`` 。
+-  第11行的 ``$(TARGET):$(OBJS)`` 表示由 ``.o`` 文件链接成可执行文件。
+-  注意第12行前面是一个 ``<tab>`` 键，而 ``$@``
+   表示目标，也就是 ``$(TARGET)，$^`` 表示依赖目标，也就是 ``$(OBJS)``
+   ，编译选项则是 ``$(FLAG)`` 。
+-  第14 -
+   16行则是判断，判断依赖文件是否存在，如果不存在则需要包含 ``DEP_FILES`` 变量。
+-  第18行表示将所有的 ``.c`` 文件编译编译成 ``.o`` 文件 。
+
+-  第19行的开头也是一个 ``<tab>`` 键， ``$<``
+   表示搜索到的第一个匹配的文件，而接下来的 ``-g -MD -MF`` 则是编译器的语法， ``-g`` 表示以操作系统的本地格式产生调试信息， ``GDB`` 能够使用这些调试信息进行调试；
+   ``-MD -MF`` 则表示生成文件的依赖关系，同时也把一些标准库的头文件包含了进来。本质是告诉预处理器输出一个适合
+   ``make`` 的规则，用于描述各目标文件的依赖关系。
+
+-  第21 – 25行表示清除相关的依赖文件，目标文件等。
+-  ``.PHONY`` 表示 ``clean`` 是个伪目标文件。
+
+进入 ``system_programing/system`` 目录下，运行make命令将system.c编译，然后可以看到system_programing/system目录下多了一个可执行文件—— ``target`` ，然后运行这个文件，可以看到调用system()函数启动一个进程输出的结果，它与我们在shell终端中执行 ``ls –l`` 命令产生的结果是一致的，具体见图
+37‑7。
+
+**命令:**
+
+.. code:: bash
+
+    make
+
+    # 输出：
+
+    gcc -o system.o -c -g -Werror -I. -Iinclude system.c -g -MD -MF
+    .system.o.dgcc -o targets system.o -g -Werror -I. –Iinclude
+
+    ps:此时已生成target可执行文件
+
+.. figure:: media/proces008.png
+   :alt: proces008
+
+   proces008
+图 37‑7 system()函数运行结果与ls命令运行结果
+
+从程序运行的结果可以看到，只有当system()函数运行完毕之后，才会输出Done，这是因为程序从上往下执行，而无法直接返回结果。虽然system()函数很有用，但它也有局限性，因为程序必须等待由system()函数启动的进程结束之后才能继续，因此我们不能立刻执行其他任务。
+
+当然，你也可以让"ls
+-l"命令在后台运行，只需在命令结束位置加上"&"即可，具体命令如下：
+
+**命令：**
+
+.. code:: bash
+
+    ls –l &
+
+如果在system()函数中使用这个命令，它也是可以在后台中运行的，那么system()函数的调用将在shell命令结束后立刻返回。由于它是一个在后台运行程序的请求，所以ps程序一启动shell就返回了，代码如代码清单37‑3所示。
+
+代码清单 37‑3 修改system.c源码:
+
+.. code:: c
+
+    #include <sys/types.h>
+    #include <unistd.h>
+    #include <stdio.h>
+    #include <stdlib.h>
+
+    int main(void)
+    {
+        pid_t result;
+
+        printf("This is a system demo!\n\n");
+
+        /*调用 system()函数*/
+        result = system("ls -l &");
+
+        printf("Done!\n\n");
+
+        return result;
+    }
+
+重新执行 ``make`` 编译，然后运行程序，实验现象具体见图 37‑8。
+
+.. figure:: media/proces009.png
+   :alt: proces009
+
+   proces009
+图 37‑8 system后台运行
+
+从图
+37‑8就可以看出来，在ls命令还未来得及打印出它的所有输出结果之前，system()函数就程序就打印出字符串Done然后退出了。在system()程序退出后，ls命令继续完成它的输出。这类的处理行为往往会给用户带来很大的困惑，也不一定如用户所预料的结果一致，因此如果读者想要让进程按照自己的意愿执行，就需要能够对它们的行为做更细致的控制，接下来作者就会讲解其他方式启动新的进程。
+
+fork()
+~~~~~~
+
+在前面的文章我们也了解到，init进程可以启动一个子进程，它通过fork()函数从原程序中创建一个完全分离的子进程，当然，这只是init进程启动子进程的第一步，后续还有其他操作的。不管怎么说，fork()函数就是可以启动一个子进程，其示意图具体见图37‑9。
+
+在父进程中的fork()调用后返回的是新的子进程的PID。新进程将继续执行，就像原进程一样，不同之处在于，子进程中的fork()函数调用后返回的是0，父子进程可以通过返回的值来判断究竟谁是父进程，谁是子进程。
+
+.. figure:: media/proces010.png
+   :alt: proces010
+
+   proces010
+图 37‑9 fork()示意图
+
+fork()函数用于从一个已存在的进程中启动一个新进程，新进程称为子进程，而原进程称为父进程。使用fork()函数的本质是将父进程的内容复制一份，正如细胞分裂一样，得到的是几乎两个完全一样的细胞，因此这个启动的子进程基本上是父进程的一个复制品，但子进程与父进程有不一样的地方，作者就简单列举一下它们的联系与区别。
+
+子进程与父进程一致的内容：
+
+-  进程的地址空间。
+-  进程上下文、代码段。
+-  进程堆空间、栈空间，内存信息。
+-  进程的环境变量。
+-  标准 IO 的缓冲区。
+-  打开的文件描述符。
+-  信号响应函数。
+-  当前工作路径。
+
+子进程独有的内容：
+
+-  进程号 PID。 PID 是身份证号码，是进程的唯一标识符。
+-  记录锁。父进程对某文件加了把锁，子进程不会继承这把锁。
+-  挂起的信号。这些信号是已经响应但尚未处理的信号，也就是"悬挂"的信号，子进程也不会继承这些信号。
+
+因为子进程几乎是父进程的完全复制，所以父子两个进程会运行同一个程序，但是这种复制有一个很大的问题，那就是资源与时间都会消耗很大，当发出fork()系统调用时，内核原样复制父进程的整个地址空间并把复制的那一份分配给子进程。这种行为是非常耗时的，因为它需要做一些事情：
+
+-  为子进程的页表分配页面。
+-  为子进程的页分配页面。
+-  初始化子进程的页表。
+-  把父进程的页复制到子进程相应的页中
+
+创建一个地址空间的这种方法涉及许多内存访问，消耗许多CPU周期，并且完全破坏了高速缓存中的内容，因此直接复制物理内存对系统的开销会产生很大的影响，更重要的是在大多数情况下，这样直接拷贝通常是毫无意义的，因为许多子进程通过装入一个新的程序开始它们的执行，这样就完全丢弃了所继承的地址空间。因此在Linux中引入一种写时复制技术（Copy
+On
+Write，简称COW），我们知道，Linux系统中的进程都是使用虚拟内存地址，虚拟地址与真实物理地址之间是有一个对应关系的，每个进程都有自己的虚拟地址空间，而操作虚拟地址明显比直接操作物理内存更加简便快捷，那么显而易见的，写时复制是一种可以推迟甚至避免复制数据的技术。内核此时并不复制整个进程的地址空间，而是让父子进程共享同一个地址空间（页面）。
+
+那么写时复制的思想就是在于：父进程和子进程共享页面而不是复制页面。而共享页面就不能被修改，无论父进程和子进程何时试图向一个共享的页面写入内容时，都会产生一个错误，这时内核就把这个页复制到一个新的页面中并标记为可写。原来的页面仍然是写保护的，当还有进程试图写入时，内核检查写进程是否是这个页面的唯一属主，如果是则把这个页面标记为对这个进程是可写的。
+
+总的来说，写时复制只会用在需要写入的时候才会复制地址空间，从而使各个进行拥有各自的地址空间，资源的复制是在需要写入的时候才会进行，在此之前，父进程与子进程都是以只读方式共享页面，这种技术使地址空间上的页的拷贝被推迟到实际发生写入的时候。而在绝大多数的时候共享的页面根本不会被写入，例如，在调用fork()函数后立即执行exec()，地址空间就无需被复制了，这样一来fork()的实际开销就是复制父进程的页表以及给子进程创建一个进程描述符。
+
+理论相关的知识就讲解到这里就好了，作者也不打算再深入讲解，下面就看看fork()函数的使用，它的函数原型如下：
+
+.. code:: c
+
+    pid_t fork(void);
+
+在fork()启动新的进程后，子进程与父进程开始并发执行，谁先执行由内核调度算法来决定。fork()函数如果成功启动了进程，会对父子进程各返回一次，其中对父进程返回子进程的
+PID，对子进程返回0；如果fork()函数启动子进程失败，它将返回-1。失败通常是因为父进程所拥有的子进程数目超过了规定的限制（CHILD_MAX），此时errno将被设为EAGAIN。如果是因为进程表里没有足够的空间用于创建新的表单或虚拟内存不足，errno变量将被设为ENOMEM。
+
+在野火提供的system_programing/fork目录下，找到fork.c文件，它里面的应用例程就是使用fork()函数启动一个新进程，并且在进程中打印相关的信息，如在父进程中打印出"In
+father process!!"等信息，例程源码具体见代码清单 37‑4。
+
+代码清单 37‑4 fork.c源码
+
+.. code:: c
+
+    #include <sys/types.h>
+    #include <unistd.h>
+    #include <stdio.h>
+    #include <stdlib.h>
+    int main(void)
+    {
+        pid_t result;
+
+        printf("This is a fork demo!\n\n");
+
+        /*调用 fork()函数*/
+        result = fork();
+
+        /*通过 result 的值来判断 fork()函数的返回情况，首先进行出错处理*/
+        if(result == -1) {
+            printf("Fork error\n");
+        }
+
+        /*返回值为 0 代表子进程*/
+        else if (result == 0) {
+            printf("The returned value is %d, In child process!! My PID is %d\n\n", result, getpid());
+
+        }
+
+        /*返回值大于 0 代表父进程*/
+        else {
+            printf("The returned value is %d, In father process!! My PID is %d\n\n", result, getpid());
+        }
+
+        return result;
+    }
+
+我们来分析一下这段代码：
+
+-  首先在第12行的时候调用了fork函数，调用fork函数后系统就会启动一个子进程，并且子进程与父进程执行的内容是一样的（代码段），读者可以通过返回值result判断fork()函数的执行结果。
+-  如果result的值为-1，那代表着fork()函数执行出错，出错的原因在前文也提到，在此具体不细说。
+-  如果返回的值为0，则表示此时执行的代码是子进程，那么就打印返回的结果、"In
+   child process!!"与子进程的PID，进程的PID通过getpid()函数获取得到。
+-  如果返回的值大于0，则表示此时执行的代码是父进程，同样也打印出返回的结果、"In
+   father process!!"与父进程的PID。
+
+在system_programing/fork目录下也提供了对应的Makefile文件，可以直接运行make进行编译，然后执行编译后生成的可执行文件"targets"，现象具体见图37‑10。
+
+.. figure:: media/proces011.png
+   :alt: proces011
+
+   proces011
+图 37‑10 fork实验现象
+
+细心的同学就会发现，在这个实验现象中，父进程的返回值就是子进程的PID，而子进程的返回值则是0。
+
+exce系列函数
+~~~~~~~~~~~~
+
+事实上，使用fork()函数启动一个子进程是并没有太大作用的，因为子进程跟父进程都是一样的，子进程能干的活父进程也一样能干，因此世界各地的开发者就想方设法让子进程做不一样的事情，因此就诞生了exce系列函数，这个系列函数主要是用于替换进程的执行程序，它可以根据指定的文件名或目录名找到可执行文件，并用它来取代原调用进程的数据段、代码段和堆栈段，在执行完之后，原调用进程的内容除了进程号外，其他全部被新程序的内容替换。另外，这里的可执行文件既可以是二进制文件，也可以是Linux下任何可执行脚本文件。简单来说就是覆盖进程，举个例子，A进程调用exce系列函数启动一个进程B，此时进程B会替换进程A，进程A的内存空间、数据段、代码段等内容都将被进程B占用，进程A将不复存在。
+
+exec 族函数有 6 个不同的 exec 函数，函数原型分别如下：
+
+.. code:: c
+
+     int execl(const char *path, const char *arg, ...)
+
+     int execlp(const char *file, const char *arg, ...)
+
+     int execle(const char *path, const char *arg, ..., char *const envp[])
+
+     int execv(const char *path, char *const argv[])
+
+     int execvp(const char *file, char *const argv[])
+
+     int execve(const char *path, char *const argv[], char *const envp[])
+
+这些函数可以分为两大类， execl、
+execlp和execle的参数个数是可变的。execv、execvp和execve的第2个参数是一个字符串数组，参数以一个空指针NULL结束，无论何种函数，在调用的时候都会通过参数将这些内容传递进去，传入的参数一般都是要运行的程序（可执行文件）、脚本等。
+
+总结来说，可以通过它们的后缀来区分他们的作用：
+
+-  名称包含 l 字母的函数（execl、 execlp
+   和execle）接收参数列表"list"作为调用程序的参数。
+-  名称包含 p 字母的函数（execvp
+   和execlp）接受一个程序名作为参数，然后在当前的执行路径中搜索并执行这个程序；名字不包含p字母的函数在调用时必须指定程序的完整路径，其实就是在系统环境变量"PATH"搜索可执行文件。
+-  名称包含 v 字母的函数（execv、execvp 和
+   execve）的命令参数通过一个数组"vector"传入。
+
+-  
+
+   名称包含 e 字母的函数（execve 和
+   execle）比其它函数多接收一个指明环境变量列表的参数，并且可以通过参数envp传递字符串数组作为新程序的环境变量，这个envp参数的格式应为一个以
+   NULL 指针作为结束标记的字符串数组，每个字符串应该表示为"environment =
+       virables"的形式。
+
+下面作者就具体某个函数做介绍：
+
+**函数:**
+
+.. code:: c
+
+    int execl(const char *path, const char *arg, ...)
+
+execl()函数用于执行参数path字符串所代表的文件路径（必须指定路径），接下来是一系列可变参数，它们代表执行该文件时传递过去的 ``argv[0]、argv[1]… argv[n]`` ，最后一个参数必须用空指针NULL作为结束的标志。
+
+代码清单 37‑5 execl()函数实例
+
+.. code:: c
+
+    int main(void)
+    {
+        int err;
+
+        printf("this is a execl function test demo!\n\n");
+
+        err = execl("/bin/ls", "ls", "-la", NULL);
+
+        if (err < 0) {
+            printf("execl fail!\n\n");
+        }
+        
+        printf("Done!\n\n");
+    }
+
+如以上的execlp()函数实例代码，它其实就是与我们在终端上运行"ls
+-la"产生的结果是一样的。
+
+**函数：**
+
+.. code:: c
+
+    int execlp(const char *file, const char *arg, ...)
+
+execlp()函数会从PATH环境变量所指的目录中查找符合参数file的文件名（不需要指定路径），找到后便执行该文件，然后将第二个以后的参数当做该文件的 ``argv[0]、argv[1]… argv[n]`` ，
+最后一个参数必须用空指针NULL作为结束的标志。
+
+代码清单 37‑6 execlp()函数实例
+
+.. code:: c
+
+    int main(void)
+    {
+        int err;
+
+        printf("this is a execlp function test demo!\n\n");
+
+        err = execlp("ls", "ls", "-la", NULL);
+
+        if (err < 0) {
+            printf("execlp fail!\n\n");
+        }
+    }
+
+**函数:**
+
+.. code:: c
+
+    int execle(const char *path, const char *arg, ..., char *const envp[])
+
+execle()函数用于执行参数path字符串所代表的文件路径（必须指定路径），并为新程序复制最后一个参数所指示的环境变量（envp）。
+
+代码清单 37‑7 execle()函数实例
+
+.. code:: c
+
+    int main(void)
+    {
+        int err;
+        char *envp[] = {
+            "/bin", NULL
+        };
+
+        printf("this is a execle function test demo!\n\n");
+
+        err = execle("/bin/ls", "ls", "-la", NULL, envp);
+
+        if (err < 0) {
+            printf("execle fail!\n\n");
+        }
+    }
+
+**函数：**
+
+.. code:: c
+
+    int execv(const char *path, char *const argv[])
+
+execv()函数用于执行参数path字符串所代表的文件路径（必须指定路径），接着传入一个数组作为执行该文件时传递过去的参数 ``argv[0]、argv[1]… argv[n]`` ，以空指针NULL结束。
+
+代码清单 37‑8 execv()函数实例
+
+.. code:: c
+
+    int main(void)
+    {
+        int err;
+        char *argv[] = {
+            "ls", "-la", NULL
+        };
+
+        printf("this is a execv function test demo!\n\n");
+
+        err = execv("/bin/ls", argv);
+
+        if (err < 0) {
+            printf("execv fail!\n\n");
+        }
+    }
+
+函数
+
+.. code:: c
+
+    int execvp(const char *path, char *const argv[])
+
+execvp()函数会从PATH环境变量所指的目录中查找符合参数file的文件名（不需要指定路径），找到该文件后便执行该文件，接着传入一个数组作为执行该文件时传递过去的参数 ``argv[0]、argv[1] … argv[n]`` ，以空指针NULL结束。
+
+代码清单 37‑9 execvp()函数实例
+
+.. code:: c
+
+    int main(void)
+    {
+        int err;
+        char *argv[] = {
+            "ls", "-la", NULL
+        };
+
+        printf("this is a execvp function test demo!\n\n");
+
+        err = execvp("ls", argv);
+
+        if (err < 0) {
+            printf("execvp fail!\n\n");
+        }
+    }
+
+**函数：**
+
+.. code:: c
+
+    int execve(const char *path, char *const argv[], char *const envp[])
+
+execve()函数用于执行参数path字符串所代表的文件路径（必须指定路径），执行该文件时会传入一个数组作为执行该文件时传递过去的参数 ``argv[0]、argv[1] … argv[n]`` ，除此之外该函数还会为新程序复制最后一个参数所指示的环境变量（envp）。
+
+代码清单 37‑10 execve ()函数实例
+
+.. code:: c
+
+    int main(void)
+    {
+        int err;
+        char *argv[] = {
+            "ls", "-la", NULL
+        };
+        char *envp[] = {
+            "/bin", NULL
+        };
+
+        printf("this is a execve function test demo!\n\n");
+
+        err = execve("/bin/ls", argv, envp);
+
+        if (err < 0) {
+            printf("execve fail!\n\n");
+        }
+    }
+
+以上函数实例代码均在system_programing/exce目录下，选择对应的代码进行编译即可，该目录也提供了对应的Makefile文件，可以直接运行make进行编译，然后执行编译后生成的可执行文件"targets"，具体现象如图
+37‑11所示。
+
+.. figure:: media/proces012.png
+   :alt: proces012
+
+   proces012
+图 37‑11 exce系列函数实验现象
+
+程序先打印出它的第一条消息"this is a execl function test
+demo!"，接着调用exec系列函数（实验中使用execl()函数），这个函数在/bin/ls目录中搜索程序ls，然后用这个程序替换targets程序，这与直接在终端中使用以下所示的shell命令一样，如图37‑12所示。
+
+**命令：**
+
+.. code:: bash
+
+    ls -la
+
+.. figure:: media/proces013.png
+   :alt: proces013
+
+   proces013
+图 37‑12 ls –la命令
+
+注意，exce系列函数是直接将当前进程给替换掉的，当调用exce系列函数后，当前进程将不会再继续执行，我们可以测试一下，在调用exce系列函数后再打印一句话，具体代码如代码清单37‑11加粗部分所示。
+
+代码清单 37‑11 exce系列函数测试代码
+
+.. code:: c
+
+    int main(void)
+    {
+        int err;
+
+        printf("this is a execl function test demo!\n\n");
+
+        err = execl("/bin/ls", "ls", "-la", NULL);
+
+        if (err < 0) {
+            printf("execl fail!\n\n");
+        }
+        
+        printf("Done!\n\n");
+    }
+
+在程序运行后，" **Done!** "将不被输出，因为当前进程已经被替换了，一般情况下，
+exec系列函数函数是不会返回的，除非发生了错误。出现错误时，
+exec系列函数将返回-1，并且会设置错误变量errno。
+
+因此我们可以通过调用fork()复制启动一个子进程，并且在子进程中调用exec系列函数替换子进程，这样子
+fork()和exec系列函数结合在一起使用就是创建一个新进程所需要的一切了。
+
+终止进程
+--------
+
+在Linux系统中，进程终止（或者称为进程退出，为了统一，下文均使用"终止"一词）的常见方式有5种，可以分为正常终止与异常终止：
+
+**正常终止：**
+
+-  从main函数返回。
+
+-  调用exit()函数终止。
+
+-  调用_exit()函数终止。
+
+**异常终止：**
+
+-  调用abort()函数异常终止。
+
+-  由系统信号终止。
+
+在Linux系统中，exit()函数定义在stdlib.h中，而_exit()定义在unistd.h中，exit()和_exit()函数都是用来终止进程的，当程序执行到exit()或_exit()函数时，进程会无条件地停止剩下的所有操作，清除包括
+PCB在内的各种数据结构，并终止当前进程的运行。不过这两个函数还是有区别的，具体如图37‑13所示。
+
+.. figure:: media/proces014.png
+   :alt: proces014
+
+   proces014
+图 37‑13 exit()和_exit()函数的区别
+
+从图中可以看出，_exit()函数的作用最为简单：直接通过系统调用使进程终止运行，当然，在终止进程的时候会清除这个进程使用的内存空间，并销毁它在内核中的各种数据结构；而exit()函数则在这些基础上做了一些包装，在执行退出之前加了若干道工序：比如exit()函数在调用exit系统调用之前要检查文件的打开情况，把文件缓冲区中的内容写回文件，这就是"清除I/O缓冲"。
+
+由于在 Linux 的标准函数库中，有一种被称作"缓冲 I/O（buffered
+I/O）"操作，其特征就是对应每一个打开的文件，在内存中都有一片缓冲区。每次读文件时，会连续读出若干条记录，这样在下次读文件时就可以直接从内存的缓冲区中读取；同样，每次写文件的时候，也仅仅是写入内存中的缓冲区，等满足了一定的条件（如达到一定数量或遇到特定字符等），再将缓冲区中的内容一次性写入文件。这种技术大大增加了文件读写的速度，但也为编程带来了一些麻烦。比如有些数据，认为已经被写入文件中，实际上因为没有满足特定的条件，它们还只是被保存在缓冲区内，这时用_exit()函数直接将进程关闭，缓冲区中的数据就会丢失。因此，若想保证数据的完整性，就一定要使用
+exit()函数。
+
+不管是那种退出方式，系统最终都会执行内核中的同一代码，这段代码用来关闭进程所用已打开的文件描述符，释放它所占用的内存和其他资源。
+
+下面一起看看_exit()与exit()函数的使用方法：
+
+**头文件：**
+
+.. code:: c
+
+    #include <unistd.h>
+    #include <stdlib.h>
+
+**函数原型：**
+
+.. code:: c
+
+    void _exit(int status);
+    void exit(int status);
+
+这两个函数都会传入一个参数status，这个参数表示的是进程终止时的状态码，0表示正常终止，其他非0值表示异常终止，一般都可以使用-1或者1表示，标准C里有EXIT_SUCCESS和EXIT_FAILURE两个宏，表示正常与异常终止。
+
+这些函数的使用都是非常简单的，只需要在需要终止的地方调用一下即可，此处就不深入讲解。
+
+等待进程
+--------
+
+在Linux中，当我们使用fork()函数启动一个子进程时，子进程就有了它自己的生命周期并将独立运行，在某些时候，可能父进程希望知道一个子进程何时结束，或者想要知道子进程结束的状态，甚至是等待着子进程结束，那么我们可以通过在父进程中调用wait()或者waitpid()函数让父进程等待子进程的结束。
+
+从前面的文章我们也了解到，当一个进程调用了exit()之后，该进程并不会立刻完全消失，而是变成了一个僵尸进程。僵尸进程是一种非常特殊的进程，它已经放弃了几乎所有的内存空间，没有任何可执行代码，也不能被调度，仅仅在进程列表中保留一个位置，记载该进程的退出状态等信息供其他进程收集，除此之外，僵尸进程不再占有任何内存空间。那么无论如何，父进程都要回收这个僵尸进程，因此调用wait()或者waitpid()函数其实就是将这些僵尸进程回收，释放僵尸进程占有的内存空间，并且了解一下进程终止的状态信息。
+
+我们可以在终端中通过man命令查看关于wait相关的函数，具体命令如下：
+
+**命令：**
+
+.. code:: bash
+
+    man 2 wait
+
+    # 输出
+
+    NAME
+           wait, waitpid, waitid - wait for process to change state
+
+    SYNOPSIS
+           #include <sys/types.h>
+           #include <sys/wait.h>
+
+           pid_t wait(int *wstatus);
+
+           pid_t waitpid(pid_t pid, int *wstatus, int options);
+
+           int waitid(idtype_t idtype, id_t id, siginfo_t *infop, int options);
+    # ……(省略其他)
+
+可能很多读者对man命令不了解，那我就简单说一下man命令相关的内容吧，其实在Linux系统中是提供了丰富的帮助手册，当你需要查看某个命令的参数时不必到处上网查找，只要man一下即可，man命令是就是用于找出这些帮助手册的内容的，比如有什么shell命令，有什么可以调用的函数
+等等。
+
+man 命令是按照章节存储的，Linux的man手册共有8个章节，具体见表格 37‑2。
+
+**表格 37‑2 man 命令说明:**
+
++------------+--------------------------+---------------------------------------------+
+| 章节编号   | 章节名称                 | 章节主要内容                                |
++============+==========================+=============================================+
+| 1          | General Commands         | 用户在shell中可以操作的指令或者可执行文档   |
++------------+--------------------------+---------------------------------------------+
+| 2          | System Calls             | 系统调用的函数与工具等                      |
++------------+--------------------------+---------------------------------------------+
+| 3          | Sunroutines              | C语言库函数                                 |
++------------+--------------------------+---------------------------------------------+
+| 4          | Special Files            | 设备或者特殊文件                            |
++------------+--------------------------+---------------------------------------------+
+| 5          | File Formats             | 文件格式与规则                              |
++------------+--------------------------+---------------------------------------------+
+| 6          | Games                    | 游戏及其他                                  |
++------------+--------------------------+---------------------------------------------+
+| 7          | Macros and Conventions   | 表示宏、包及其他杂项                        |
++------------+--------------------------+---------------------------------------------+
+| 8          | Maintenence Commands     | 表示系统管理员相关的命令                    |
++------------+--------------------------+---------------------------------------------+
+
+例如我们想找与wait相关的函数，那么我们只需要输入以下命令即可：
+
+.. code:: bash
+
+    man 2 wait
+
+例如我们想要了解ls命令相关的内容，我们可以直接输入以下命令，就可以看到关于ls相关的用法等内容。
+
+**命令:**
+
+.. code:: bash
+
+    man ls
+
+    # 输出
+
+    NAME
+           ls - list directory contents
+
+    SYNOPSIS
+           ls [OPTION]... [FILE]...
+
+    DESCRIPTION
+           List information about the FILEs (the current directory by default).  Sort entries alphabetically if none of -cftuvSUX nor --sort is specified.
+
+           Mandatory arguments to long options are mandatory for short options too.
+
+           -a, --all
+                  do not ignore entries starting with .
+
+    ……(省略其他)
+
+    当然啦，man手册是英文的，这是属于全世界通用的技术交流语言，因此读者还是需要对英文有一定熟悉程度。
+
+wait()
+~~~~~~
+
+我们通过man命令就知道了wait()、waitpid()函数原型，那么我们就首先了解下wait()函数。
+
+函数原型
+
+.. code:: bash
+
+    pid_t wait(int *wstatus);
+
+wait()函数在被调用的时候，系统将暂停父进程的执行，直到有信号来到或子进程结束，如果在调用wait()函数时子进程已经结束，则会立即返回子进程结束状态值。子进程的结束状态信息会由参数wstatus返回，与此同时该函数会返子进程的PID，它通常是已经结束运行的子进程的PID。状态信息允许父进程了解子进程的退出状态，如果不在意子进程的结束状态信息，则参数wstatus可以设成NULL。
+
+wait()函数有几点需要注意的地方：
+
+1. wait()要与fork()配套出现，如果在使用fork()之前调用wait()，wait()的返回值则为-1，正常情况下wait()的返回值为子进程的PID。
+2. 参数wstatus用来保存被收集进程退出时的一些状态，它是一个指向int类型的指针，但如果我们对这个子进程是如何死掉毫不在意，只想把这个僵尸进程消灭掉，（事实上绝大多数情况下，我们都会这样做），我们就可以设定这个参数为NULL。
+
+当然，除此之外，Linux系统中还提供关于等待子进程退出的一些宏定义，我们可以使用这些宏定义来直接判断子进程退出的状态：
+
+-  WIFEXITED(status) ：如果子进程正常结束，返回一个非零值
+
+-  WEXITSTATUS(status)： 如果WIFEXITED非零，返回子进程退出码
+
+-  WIFSIGNALED(status) ：子进程因为捕获信号而终止，返回非零值
+
+-  WTERMSIG(status) ：如果WIFSIGNALED非零，返回信号代码
+
+-  WIFSTOPPED(status)： 如果子进程被暂停，返回一个非零值
+
+-  WSTOPSIG(status)： 如果WIFSTOPPED非零，返回一个信号代码
+
+wait()函数使用实例如下：
+
+代码清单 37‑12 wait()函数使用实例
+
+.. code:: c
+
+    #include <sys/types.h>
+    #include <sys/wait.h>
+    #include <unistd.h>
+    #include <stdio.h>
+    #include <stdlib.h>
+
+    int main()
+    {
+        pid_t pid, child_pid;
+        int status;
+
+        pid = fork();                  //(1)
+
+        if (pid < 0) {
+            printf("Error fork\n");
+        }
+        /*子进程*/
+        else if (pid == 0) {                  //(2)
+
+            printf("I am a child process!, my pid is %d!\n\n",getpid());
+
+            /*子进程暂停 3s*/
+            sleep(3);
+
+            printf("I am about to quit the process!\n\n");
+
+            /*子进程正常退出*/
+            exit(0);                          //(3)
+        }
+        /*父进程*/
+        else {                                //(4)
+
+            /*调用 wait，父进程阻塞*/
+            child_pid = wait(&status);        //(5)
+
+            /*若发现子进程退出，打印出相应情况*/
+            if (child_pid == pid) {
+                printf("Get exit child process id: %d\n",child_pid);
+                printf("Get child exit status: %d\n\n",status);
+            } else {
+                printf("Some error occured.\n\n");
+            }
+
+            exit(0);
+        }
+    }
+
+我们来分析一下这段代码：
+
+代码清单 37‑12 **(1)** ：首先调用fork()函数启动一个子进程。
+
+代码清单 37‑12
+**(2)** ：如果fork()函数返回的值pid为0，则表示此时运行的是子进程，那么就让子进程输出一段信息，并且休眠3s。
+
+代码清单37‑12
+**(3)** ：休眠结束后调用exit()函数退出，退出状态为0，表示子进程正常退出。
+
+代码清单 37‑12
+**(4)** ：如果fork()函数返回的值pid不为0，则表示此时运行的是父进程，那么在父进程中调用wait(&status)函数等待子进程的退出，子进程的退出状态将保存在status变量中。
+
+代码清单37‑12
+**(5)** ：若发现子进程退出（通过wait()函数返回的子进程pid判断），则打印出相应信息，如子进程的pid与status。
+
+以上函数实例代码在system_programing/wait目录下，选择对应的代码进行编译即可，该目录也提供了对应的Makefile文件，可以直接运行make进行编译，然后执行编译后生成的可执行文件"targets"，执行结果如图
+37‑14所示。
+
+.. figure:: media/proces015.png
+   :alt: proces015
+
+   proces015
+图 37‑14 wait()函数现象
+
+waitpid()
+~~~~~~~~~
+
+waitpid()函数
+的作用和wait()函数一样，但它并不一定要等待第一个终止的子进程，它还有其他选项，比如指定等待某个pid的子进程、提供一个非阻塞版本的wait()功能等。实际上
+wait()函数只是 waitpid() 函数的一个特例，在 Linux内部实现 wait
+函数时直接调用的就是 waitpid 函数。
+
+函数原型
+
+.. code:: C
+
+    pid_t waitpid(pid_t pid, int *wstatus, int options);
+
+waitpid()函数的参数有3个，下面就简单介绍这些参数相关的选项：
+
+-  pid：参数pid为要等待的子进程ID，其具体含义如下：
+
+1. pid < -1：等待进程组号为pid绝对值的任何子进程。
+2. pid = -1：等待任何子进程，此时的waitpid()函数就等同于wait()函数。
+3. pid
+   =0：等待进程组号与目前进程相同的任何子进程，即等待任何与调用waitpid()函数的进程在同一个进程组的进程。
+4. pid > 0：等待指定进程号为pid的子进程。
+
+-  wstatus：与wait()函数一样。
+-  options：参数options提供了一些另外的选项来控制waitpid()函数的行为。如果不想使用这些选项，则可以把这个参数设为0。
+
+1. WNOHANG：如果pid指定的子进程没有终止运行，则waitpid()函数立即返回0，而不是阻塞在这个函数上等待；如果子进程已经终止运行，则立即返回该子进程的进程号与状态信息。
+2. WUNTRACED：如果子进程进入了暂停状态（可能子进程正处于被追踪等情况），则马上返回。
+3. WCONTINUED：如果子进程恢复通过SIGCONT信号运行，也会立即返回（这个不常用，了解一下即可）。
+
+很显然，当waitpid()函数的参数为(-1, status,
+0)时，waitpid()函数就完全退化成了wait()函数。
+
+下面看一下waitpid()函数使用实例，具体见代码清单 37‑13。
+
+代码清单 37‑13 waitpid()函数使用实例
+
+.. code:: C
+
+    #include <sys/types.h>
+    #include <sys/wait.h>
+    #include <unistd.h>
+    #include <stdio.h>
+    #include <stdlib.h>
+
+
+    int main()
+    {
+        pid_t pid, child_pid;
+        int status;
+
+        pid = fork();
+
+        if (pid < 0) {
+            printf("Error fork\n");
+        }
+        /*子进程*/
+        else if (pid == 0) {
+
+            printf("I am a child process!, my pid is %d!\n\n",getpid());
+
+            /*子进程暂停 3s*/
+            sleep(3);
+
+            printf("I am about to quit the process!\n\n");
+            /*子进程正常退出*/
+            exit(0);
+        }
+        /*父进程*/
+        else {
+
+            /*调用 waitpid，且父进程不阻塞*/
+            child_pid = waitpid(pid, &status, WUNTRACED);
+
+            /*若发现子进程退出，打印出相应情况*/
+            if (child_pid == pid) {
+                printf("Get exit child process id: %d\n",child_pid);
+                printf("Get child exit status: %d\n\n",status);
+            } else {
+                printf("Some error occured.\n");
+            }
+
+            exit(0);
+        }
+    }
+
+编译后运行，它的实验现象与wait()函数的是一样的。
diff --git a/documentation/system_programing/semaphore.rst b/documentation/system_programing/semaphore.rst
new file mode 100644
index 0000000000000000000000000000000000000000..8522afc6f856a4b9c8edb1a1995287f34e059ecd
--- /dev/null
+++ b/documentation/system_programing/semaphore.rst
@@ -0,0 +1,213 @@
+本章先别发布，应该是在讲解线程后才发布
+======================================
+
+线程信号量
+==========
+
+这篇文章将讲述别一种线程间通信的机制——线程信号量，为了明确进程与线程信号量间的区别，本章
+出现的信号量均为线程使用的信号量。注意请不要把它与之前所说的信号混淆了，信号与信号量是不同的两种机制。
+
+线程信号量基本概念
+------------------
+
+信号量（Semaphore）是一种实现线程间通信的机制，可以实现线程之间同步或
+临界资源的互斥访问，常用于协助一组相互竞争的线程来访问临界资源。在多线程
+系统中，各线程之间需要同步或互斥实现临界资源的保护，信号量功能可以为用户提供这方面的支持。
+
+在多线程操作系统环境下，多个线程会同时运行，并且一些线程之间可能存在一定
+的关联。多个线程可能为了完成同一个线程会相互协作，这样形成线程之间的同步关系，因此可以使用信号量进行同步。
+
+而且在不同线程之间，为了争夺有限的系统资源（硬件或软件资源）会进入竞争状
+态，这就是线程之间的互斥关系。为了防止出现因多个程序同时访问一个共享资源而引发的一系列问题，我们
+需要一种方法，它可以通过生成并使用令牌来授权，在任一时刻只能有一个执行线程访问代码的临界区域。临
+界区域是指执行数据更新的代码需要独占式地执行。而信号量就可以提供这样的一种访问机制，让一个临界区
+同一时间只有一个线程在访问它，因此信号量是可以用来调协线程对共享资源的访问的。线程之间的互斥与同
+步关系存在的根源在于临界资源。临界资源是在同一个时刻只允许有限个（通常只有一个）线程可以访问（读）或
+修改（写）的资源，通常包括硬件资源（处理器、内存、存储器以及其他外围设备等）和软件资源（共享代码段，共
+享结构和变量等）。
+
+抽象的来讲，信号量中存在一个非负整数，所有获取它的线程都会将该整数减
+一（获取它当然是为了使用资源），当该整数值为零时，所有试图获取它的线程
+都将处于阻塞状态。通常一个信号量的计数值用于对应有效的资源数，表示剩下的可
+被占用的互斥资源数。其值的含义分两种情况：
+
+-  0：表示没有可用的信号量，线程进入睡眠状态，直至信号量值大于 0。
+
+-  正值：表示有一个或多个可用的信号量，线程可以使用该资源。线程将信号量值减
+   1，表示它使用了一个资源单位。
+
+对信号量的操作可以分为两个：
+
+-  P
+   操作：如果有可用的资源（信号量值大于0），则占用一个资源（给信号量
+   值减去一，进入临界区代码）;如果没有可用的资源（信号量值等于
+   0），则被阻塞到，直到系统将资源分配给该线程（进入等待队列，一直等到
+   资源轮到该线程）。这就像你要把车开进停车场之前，先要向保安申请一张停车卡一样，P
+   操作就是申请资源，如果申请成功，资源数（空闲的停车位）将会减少一个，如果申
+   请失败，要不在门口等，要不就走人。
+
+-  V
+   操作：如果在该信号量的等待队列中有线程在等待资源，则唤醒一个阻塞的线程。如果
+   没有线程等待它，则释放一个资源（给信号量值加一），就跟你从停车场出去的时候一样，空闲的停车位就会增加一个。
+
+举个例子，就是两个线程共享信号量sem，sem可用信号量的数值为1，一旦其中一个线
+程执行了P（sem）操作，它将得到信号量，并可以进入临界区，使sem减1。而第二个线程将被阻
+止进入临界区，因为当它试图执行P（sem）操作时，sem为0，它会被挂起以等待第一个线程离开临界
+区域并执行V（sem）操作释放了信号量，这时第二个线程就可以恢复执行。
+
+线程信号量相关函数
+------------------
+
+如果要在Linux中使用信号量同步，需要包含头文件 ``semaphore.h`` 。
+
+**主要用到的函数：**
+
+.. code:: c
+
+    int sem_init(sem_t *sem， int pshared， unsigned int value);
+    int sem_destroy(sem_t *sem);
+    int sem_wait(sem_t *sem);
+    int sem_post(sem_t *sem);
+
+-  sem_init()：初始化信号量，其中sem是要初始化的信号量，pshared表示此信号量是在线
+   程间共享还是线程间共享，由于目前
+   Linux 还没有实现进程间共享信号量，所以这个值只能够取
+   0，就表示这个信号量是当前进程的局部信号量，value是信号量的初始值。成功返回0，失败返回-1。
+
+-  sem_destroy()：销毁信号量，其中sem是要销毁的信号量。只有用sem_init初
+   始化的信号量才能用sem_destroy()函数销毁。成功返回0，失败返回-1。
+
+-  sem_wait()：等待（获取）信号量，如果信号量的值大于0，将信号量的值减1，立即
+   返回。如果信号量的值为0，则线程阻塞。相当于P操作。成功返回0，失败返回-1。
+
+-  sem_post();
+   释放信号量，让信号量的值加1，相当于V操作。成功返回0，失败返回-1。
+
+线程信号量的使用实例
+--------------------
+
+下面的例子是用信号量同步机制实现 3
+个线程之间的有序执行，首先创建3个线程，然后在线程中首先使用sem_wait()获取
+信号量，然后随机睡眠3次，然后再通过sem_post()函数释放信号量，再退出线程，这个
+实验的目的是为了使用信号量在多线程间进行同步。
+
+**代码如下：**
+
+.. code:: c
+
+    #include <unistd.h>
+    #include <stdio.h>
+    #include <stdlib.h>
+    #include <pthread.h>
+    #include <semaphore.h>
+
+    #define THREAD_NUMBER 3 /* 线程数 */
+    #define REPEAT_NUMBER 3 /* 每个线程中的小任务数 */
+    #define DELAY_TIME_LEVELS 3.0 /*小任务之间的最大时间间隔*/
+
+    sem_t sem[THREAD_NUMBER];
+
+    void *thread_func(void *arg)
+    {
+        int num = (unsigned long long)arg;
+        int delay_time = 0;
+        int count = 0;
+
+        /* 进行 P 操作 */
+        sem_wait(&sem[num]);
+
+        printf("Thread %d is starting\n", num);
+        for (count = 0; count < REPEAT_NUMBER; count++)
+        {
+            delay_time = (int)(rand() * DELAY_TIME_LEVELS/(RAND_MAX)) + 1;
+            sleep(delay_time);
+            printf("\tThread %d: job %d delay = %d\n",num, count, delay_time);
+        }
+
+        printf("Thread %d finished\n", num);
+        pthread_exit(NULL);
+    }
+
+
+
+    int main(void)
+    {
+        pthread_t thread[THREAD_NUMBER];
+        int no = 0, res;
+        void * thread_ret;
+        srand(time(NULL));
+
+        for (no = 0; no < THREAD_NUMBER; no++)
+        {
+            sem_init(&sem[no], 0, 0);
+            res = pthread_create(&thread[no], NULL, thread_func, (void*)(unsigned long long)no);
+
+            if (res != 0)
+            {
+                printf("Create thread %d failed\n", no);
+                exit(res);
+            }
+        }
+
+        printf("Create treads success\n Waiting for threads to finish...\n");
+
+        /* 对最后创建的线程的信号量进行 V 操作 */
+        sem_post(&sem[THREAD_NUMBER - 1]);
+        for (no = THREAD_NUMBER - 1; no >= 0; no--)
+        {
+            res = pthread_join(thread[no], &thread_ret);
+            if (!res)
+            {
+                printf("Thread %d joined\n", no);
+            }
+            else
+            {
+                printf("Thread %d join failed\n", no);
+            }
+
+            /* 进行 V 操作 */
+            sem_post(&sem[(no + THREAD_NUMBER - 1) % THREAD_NUMBER]);
+        }
+
+        for (no = 0; no < THREAD_NUMBER; no++)
+        {
+            /* 删除信号量 */
+            sem_destroy(&sem[no]);
+        }
+
+        return 0;
+    }
+
+**实验结果如下：**
+
+.. code:: bash
+
+    ➜  thread_sem make     
+
+    gcc -o thread_sem.o -c -g -Werror -I. -Iinclude -lpthread -static  thread_sem.c -g -MD -MF .thread_sem.o.d
+    gcc -o targets thread_sem.o -g -Werror -I. -Iinclude -lpthread -static 
+
+
+    ➜  thread_sem ./targets
+
+    Create treads success
+     Waiting for threads to finish...
+    Thread 2 is starting
+            Thread 2: job 0 delay = 1
+            Thread 2: job 1 delay = 3
+            Thread 2: job 2 delay = 3
+    Thread 2 finished
+    Thread 2 joined
+    Thread 1 is starting
+            Thread 1: job 0 delay = 3
+            Thread 1: job 1 delay = 1
+            Thread 1: job 2 delay = 1
+    Thread 1 finished
+    Thread 1 joined
+    Thread 0 is starting
+            Thread 0: job 0 delay = 3
+            Thread 0: job 1 delay = 2
+            Thread 0: job 2 delay = 1
+    Thread 0 finished
+    Thread 0 joined
+
diff --git a/documentation/system_programing/shm.rst b/documentation/system_programing/shm.rst
new file mode 100644
index 0000000000000000000000000000000000000000..93a30dce2dbcd8912fdf3f66d61cb8c9499ff22d
--- /dev/null
+++ b/documentation/system_programing/shm.rst
@@ -0,0 +1,408 @@
+共享内存
+========
+
+共享内存基本概念
+----------------
+
+什么是共享内存？顾名思义，共享内存就是将内存进行共享，它允许多个不相关的进程访问同一个逻辑内存，直接将一块裸露的内存放在需要数据传输的进程面前，让它们自己使用。因此，共享内存是效率最高的一种IPC通信机制，它可以在多个进程之间共享和传递数据，进程间需要共享的数据被放在共享内存区域，所有需要访问该共享区域的进程都要把该共享区域映射到本进程的地址空间中去，因此所有进程都可以访问共享内存中的地址，就好像它们是由用C语言函数malloc分配的内存一样。
+
+但是，这种共享的内存需要进程自己去维护好，如同步、互斥等工作，比如当进程1在读取共享内存的数据时，进程2却修改了共享内存中的数据，那么必然会造成数据的混乱，进程1读取到的数据就是错误的，因此，共享内存是属于临界资源，在某一时刻最多只能有一个进程对其操作（读
+/
+写数据），所以共享内存一般不能单独使用，而要配合信号量、互斥锁等协调机制，让各个进程在高效交换数据的同时，不会发生数据践踏、破坏等意外。
+
+共享内存的思想非常简单，进程与进程之间虚拟内存空间本来相互独立，不能互相访问的，但是可以通过某些方式，使得相同的一块物理内存多次映射到不同的进程虚拟空间之中，这样的效果就相当于多个进程的虚拟内存空间部分重叠在一起，如图所示：
+
+.. figure:: media/shm001.png
+   :alt: 共享内存
+
+   共享内存
+当进程1向共享内存写入数据后，共享内存的数据就变化了，那么进程2就能立即读取到变化了的数据，而这中间并未经过内核的拷贝，因此效率极高。
+
+**总的来说共享内存有以下特点：**
+
+1. 共享内存是进程间通信中效率最高的方式之一。
+
+2. 共享内存是系统出于多个进程之间通讯的考虑，而预留的的一块内存区，因此共享内存是以传输数据为目的的。
+
+3. 共享内存允许两个或更多进程访问同一块内存，当一个进程改变了这块地址中的内容的时候，其它进程都会察觉到这个更改。
+
+4. 共享内存无同步无互斥。
+
+**共享内存的优缺点：**
+
+-  优点：使用共享内存进行进程间的通信非常方便，而且函数的接口也简单，数据的共享使进程间的数据不用传送，而是直接访问内存，加快了程序的效率。同时，它也不像匿名管道那样要求通信的进程有一定的"血缘"关系，只要是系统中的任意进程都可以对共享内存进行读写操作。
+
+-  缺点：共享内存没有提供同步的机制，这使得我们在使用共享内存进行进程间通信时，往往要借助其他的手段（如信号量、互斥量等）来进行进程间的同步工作。
+
+创建或获取共享内存ID
+--------------------
+
+**想要使用共享内存，必须包含以下头文件：**
+
+.. code:: c
+
+        #include <sys/ipc.h>
+        #include <sys/shm.h>
+
+**shmget()**
+
+shmget()函数的主要主要是得到一个共享内存标识符或创建一个共享内存对象并返回共享内存标识符。
+
+**函数原型：**
+
+.. code:: c
+
+        int shmget(key_t key, size_t size, int shmflg);
+
+**参数：**
+
+1. key：标识共享内存的键值，可以有以下取值：
+
+-  0 / IPC_PRIVATE。
+   当key的取值为IPC_PRIVATE，则函数shmget()将创建一块新的共享内存；如果key的取值为0，而参数shmflg中设置了IPC_PRIVATE这个标志，则同样将创建一块新的共享内存。
+-  大于0的32位整数：视参数shmflg来确定操作。
+
+2. size：要创建共享内存的大小，所有的内存分配操作都是以页为单位的，所以即使只申请只有一个字节的内存，内存也会分配整整一页。
+
+3. shmflg：表示创建的共享内存的模式标志参数，在真正使用时需要与IPC对象存取权限mode（如0600）进行"｜"运算来确定共享内存的存取权限。msgflg有多种情况：
+
+-  IPC_CREAT：如果内核中不存在关键字与key相等的共享内存，则新建一个共享内存；如果存在这样的共享内存，返回此共享内存的标识符。
+-  IPC_EXCL：如果内核中不存在键值与key相等的共享内存，则新建一个共享内存；如果存在这样的共享内存则报错。
+-  SHM_HUGETLB：使用"大页面"来分配共享内存，所谓的"大页面"指的是内核为了提高程序性能，对内存实行分页管理时，采用比默认尺寸（4KB）更大的分页，以减少缺页中断。Linux内核支持以2MB作为物理页面分页的基本单位。
+-  SHM_NORESERVE：不在交换分区中为这块共享内存保留空间。
+
+**错误代码：**
+
+当调用shmget()函数失败时将产生错误代码。
+
+-  EACCES：指定的消息队列已存在，但调用进程没有权限访问它
+-  EEXIST：key指定的消息队列已存在，而msgflg中同时指定IPC_CREAT和IPC_EXCL标志
+-  EINVAL：创建共享内存时参数size小于SHMMIN或大于SHMMAX。
+-  ENFILE：已达到系统范围内打开文件总数的限制。
+-  ENOENT：给定的key不存在任何共享内存，并且未指定IPC_CREAT。
+-  ENOMEM：内存不足，无法为共享内存分配内存。
+-  EACCES：没有权限。
+
+shmget()函数的返回值是共享内存的ID。
+
+映射共享内存
+------------
+
+**shmat()**
+
+从前文我们就知道了，如果一个进程想要访问这个共享内存，那么需要将其映射到进程的虚拟空间中，然后再去访问它，那么shmat()函数就是把共享内存区对象映射到调用进程的地址空间。
+
+**函数原型：**
+
+.. code:: c
+
+        void *shmat(int shmid, const void *shmaddr, int shmflg);
+
+**参数：**
+
+1. shmid：共享内存ID，通常是由shmget()函数返回的。
+2. shmaddr：如果不为NULL，则系统会根据shmaddr来选择一个合适的内存区域，如果为NULL，则系统会自动选择一个合适的虚拟内存空间地址去映射共享内存。
+3. shmflg：操作共享内存的方式：
+
+-  SHM_RDONLY：以只读方式映射共享内存。
+-  SHM_REMAP：重新映射，此时shmaddr不能为NULL。
+-  NULLSHM：自动选择比shmaddr小的最大页对齐地址。
+
+shmat()函数调用成功后返回共享内存的起始地址，这样子我们就能操作这个共享内存了。
+
+共享内存的映射有以下注意的要点：
+
+-  共享内存只能以只读或者可读写方式映射，无法以只写方式映射。
+-  shmat()第二个参数shmaddr一般都设为NULL，让系统自动找寻合适的地址。但当其确实不为空时，那么要求SHM_RND在shmflg必须被设置，这样的话系统将会选择比shmaddr小而又最大的页对齐地址（即为SHMLBA的整数倍）作为共享内存区域的起始地址。如果没有设置SHM_RND，那么shmaddr必须是严格的页对齐地址。
+
+解除共享内存的映射
+------------------
+
+**shmdt()**
+
+shmdt()函数与shmat()函数相反，是用来解除进程与共享内存之间的映射的，在解除映射后，该进程不能再访问这个共享内存。
+
+**函数原型：**
+
+.. code:: c
+
+        int shmdt(const void *shmaddr);
+
+**参数：**
+
+-  shmaddr：映射的共享内存的起始地址。
+
+shmdt()函数调用成功返回0，如果出错则返回-1，并且将错误原因存于error中。
+
+虽然shmdt()函数很简单，但是还是有注意的要点的，该函数并不删除所指定的共享内存区，而只是将先前用shmat()函数映射好的共享内存脱离当前进程，共享内存还是存在于物理内存中。
+
+获取或设置共享内存的相关属性
+----------------------------
+
+**shmctl()**
+
+shmctl()用于获取或者设置共享内存的相关属性的。
+
+**函数原型：**
+
+.. code:: c
+
+        int shmctl(int shmid, int cmd, struct shmid_ds *buf);
+
+**参数：**
+
+1. shmid：共享内存标识符。
+2. cmd：函数功能的控制命令，其取值如下：
+
+-  IPC_STAT：获取属性信息，放置到buf中。
+-  IPC_SET：设置属性信息为buf指向的内容。
+-  IPC_RMID：删除这该共享内存。
+-  IPC_INFO：获得关于共享内存的系统限制值信息。
+-  SHM_INFO：获得系统为共享内存消耗的资源信息。
+-  SHM_STAT：与IPC_STAT具有相同的功能，但shmid为该SHM在内核中记录所有SHM信息的数组的下标，因此通过迭代所有的下标可以获得系统中所有SHM的相关信息。
+-  SHM_LOCK：禁止系统将该SHM交换至swap分区。
+-  SHM_UNLOCK：允许系统将该SHM交换至swap分。
+
+-  buf：共享内存属性信息结构体指针，设置或者获取信息都通过该结构体，shmid_ds结构如下：
+
+注意：选项SHM_LOCK不是锁定读写权限，而是锁定SHM能否与swap分区发生交换。一个SHM被交换至swap分区后如果被设置了SHM_LOCK，那么任何访问这个SHM的进程都将会遇到页错误。进程可以通过IPC_STAT后得到的mode来检测SHM_LOCKED信息。
+
+.. code:: c
+
+        struct shmid_ds {
+            struct ipc_perm shm_perm;    /* 所有权和权限 */
+            size_t          shm_segsz;   /* 共享内存尺寸（字节） */
+            time_t          shm_atime;   /* 最后一次映射时间 */
+            time_t          shm_dtime;   /* 最后一个解除映射时间 */
+            time_t          shm_ctime;   /* 最后一次状态修改时间 */
+            pid_t           shm_cpid;    /* 创建者PID */
+            pid_t           shm_lpid;    /* 后一次映射或解除映射者PID */
+            shmatt_t        shm_nattch;  /* 映射该SHM的进程个数 */
+            ...
+        };
+
+其中权限信息结构体如下：
+
+::
+
+        struct ipc_perm {
+            key_t          __key;    /* 该共享内存的键值key */
+            uid_t          uid;      /* 所有者的有效UID */
+            gid_t          gid;      /* 所有者的有效GID */
+            uid_t          cuid;     /* 创建者的有效UID */
+            gid_t          cgid;     /* 创建者的有效GID */
+            unsigned short mode;     /* 读写权限 + SHM_DEST + SHM_LOCKED 标记 */
+            unsigned short __seq;    /* 序列号 */
+        };
+
+使用实例
+--------
+
+**使用共享内存的一般步骤是：**
+
+1. 创建或获取共享内存ID。
+2. 将共享内存映射至本进程虚拟内存空间的某个区域。
+3. 当不再使用时，解除映射关系。
+4. 当没有进程再需要这块共享内存时，删除它。
+
+共享内存由于其特性，与进程中的其他内存段在使用习惯上有些不同。一般进程对栈空间分配可以自动回收，而堆空间通过malloc申请，free回收，这些内存在回收之后就可以认为是不存在了。但是共享内存不同，用shmdt()函数解除映射后，实际上其占用的内存还在，并仍然可以使用shmat映射使用。如果不使用shmctl()函数删除这个共享内存的话，那么它将一直保留直到系统被关闭，除此之外，我们应该配合信号量去使用共享内存，避免多进程间的随意使用造成数据踩踏。
+
+首先我们需要使用到system V
+信号量，在上一章我们就封装了这个信号量，此处不再重复赘述，然后我们需要实现两个进程，分别为共享内存写进程，共享内存读进程，在写进程中实现写数据，在读进程中将数据读取，并且打印出来，代码如下：
+
+**读进程：**
+
+.. code:: c
+
+    #include <sys/types.h>
+    #include <sys/shm.h>
+    #include <sys/sem.h>
+    #include <sys/ipc.h>
+    #include <unistd.h>
+    #include <stdlib.h>
+    #include <stdio.h>
+    #include <string.h>
+    #include <sys/stat.h>
+    #include <fcntl.h>
+    #include <errno.h>
+
+    #include "sem.h"
+
+    int main(void)
+    {
+        int running = 1;//程序是否继续运行的标志
+        char *shm = NULL;//分配的共享内存的原始首地址
+        int shmid;//共享内存标识符
+        int semid;//信号量标识符
+
+        //创建共享内存
+        shmid = shmget((key_t)1234, 4096, 0666 | IPC_CREAT);
+        if(shmid == -1)
+        {
+            fprintf(stderr, "shmget failed\n");
+            exit(EXIT_FAILURE);
+        }
+
+        //将共享内存连接到当前进程的地址空间
+        shm = shmat(shmid, 0, 0);
+        if(shm == (void*)-1)
+        {
+            fprintf(stderr, "shmat failed\n");
+            exit(EXIT_FAILURE);
+        }
+        printf("\nMemory attached at %p\n", shm);
+
+        /** 打开信号量，不存在则创建 */
+        semid = semget((key_t)6666, 1, 0666|IPC_CREAT); /* 创建一个信号量*/
+
+        if(semid == -1)
+        {
+            printf("sem open fail\n");
+            exit(EXIT_FAILURE); 
+        }
+
+        init_sem(semid, 0);
+
+        while(running)//读取共享内存中的数据
+        {
+            /** 等待心信号量 */
+            if(sem_p(semid) == 0)
+            {
+                printf("You wrote: %s", shm);
+                sleep(rand() % 3);
+                
+                //输入了end，退出循环（程序）
+                if(strncmp(shm, "end", 3) == 0)
+                    running = 0;
+            }
+        }
+
+        del_sem(semid); /** 删除信号量 */
+
+        //把共享内存从当前进程中分离
+        if(shmdt(shm) == -1)
+        {
+            fprintf(stderr, "shmdt failed\n");
+            exit(EXIT_FAILURE);
+        }
+        
+        //删除共享内存
+        if(shmctl(shmid, IPC_RMID, 0) == -1)
+        {
+            fprintf(stderr, "shmctl(IPC_RMID) failed\n");
+            exit(EXIT_FAILURE);
+        }
+        exit(EXIT_SUCCESS);
+    }
+
+**写进程：**
+
+.. code:: c
+
+    #include <sys/types.h>
+    #include <sys/shm.h>
+    #include <sys/sem.h>
+    #include <sys/ipc.h>
+    #include <unistd.h>
+    #include <stdlib.h>
+    #include <stdio.h>
+    #include <string.h>
+    #include <sys/stat.h>
+    #include <fcntl.h>
+    #include <errno.h>
+
+    #include "sem.h"
+
+
+    int main()
+    {
+        int running = 1;
+        void *shm = NULL;
+        struct shared_use_st *shared = NULL;
+        char buffer[BUFSIZ + 1];//用于保存输入的文本
+        int shmid;
+        int semid;;//信号量标识符
+
+        //创建共享内存
+        shmid = shmget((key_t)1234, 4096, 0644 | IPC_CREAT);
+        if(shmid == -1)
+        {
+            fprintf(stderr, "shmget failed\n");
+            exit(EXIT_FAILURE);
+        }
+        //将共享内存连接到当前进程的地址空间
+        shm = shmat(shmid, (void*)0, 0);
+        if(shm == (void*)-1)
+        {
+            fprintf(stderr, "shmat failed\n");
+            exit(EXIT_FAILURE);
+        }
+        printf("Memory attached at %p\n", shm);
+
+        /** 打开信号量，不存在则创建 */
+        semid = semget((key_t)6666, 1, 0666|IPC_CREAT);
+
+        if(semid == -1)
+        {
+            printf("sem open fail\n");
+            exit(EXIT_FAILURE); 
+        }
+
+
+
+        while(running)//向共享内存中写数据
+        {
+            //向共享内存中写入数据
+            printf("Enter some text: ");
+            fgets(buffer, BUFSIZ, stdin);
+            strncpy(shm, buffer, 4096);
+
+            sem_v(semid);/* 释放信号量 */
+
+            //输入了end，退出循环（程序）
+            if(strncmp(buffer, "end", 3) == 0)
+                running = 0;
+        }
+
+        //把共享内存从当前进程中分离
+        if(shmdt(shm) == -1)
+        {
+            fprintf(stderr, "shmdt failed\n");
+            exit(EXIT_FAILURE);
+        }
+        sleep(2);
+        exit(EXIT_SUCCESS);
+    }
+
+该代码在system_programing/shm_read目录及system_programing/shm_write目录下，分别编译并且运行即可，现象如下：
+
+**读进程：**
+
+.. code:: bash
+
+    ➜  shm_read git:(master) ✗ ./targets
+
+    Memory attached at 0x7f2df8f9e000
+    You wrote: embedfire
+    You wrote: good
+    You wrote: nice
+    You wrote: 123456
+    You wrote: 6666666666666
+    You wrote: end
+
+**写进程：**
+
+在写进程中可以输入任何信息，当输入end表示结束，此时共享内存将被删除。
+
+.. code:: bash
+
+    ➜  shm_write git:(master) ✗ ./targets
+
+    Memory attached at 0x7f66e44e4000
+    Enter some text: embedfire
+    Enter some text: good
+    Enter some text: nice
+    Enter some text: 123456
+    Enter some text: 6666666666666
+    Enter some text: end 
+
diff --git a/documentation/system_programing/signal.rest b/documentation/system_programing/signal.rst
similarity index 32%
rename from documentation/system_programing/signal.rest
rename to documentation/system_programing/signal.rst
index 321611779a8b0d993fea0743637592ab1f055976..45065a90a1af622b475597c16e331fa33ecbf768 100644
--- a/documentation/system_programing/signal.rest
+++ b/documentation/system_programing/signal.rst
@@ -1,130 +1,156 @@
 .. vim: syntax=rst
 
 信号
---
-
-本章节内容处于开发笔记状态，还待整理至最终版的教程。
-
-本章节内容处于开发笔记状态，还待整理至最终版的教程。
+====
 
 信号的基本概念
-~~~~~~~
+--------------
 
 概述
-^^
+~~~~
 
-信号（signal），又称为软中断信号，用于通知进程发生了异步事件，它是linux系统响应某些条件而产生的一个事件，它是在软件层次上对中断机制的一种模拟，是一种异步通信方式，在原理上，一个进程收到一个信号与处理器收到一个中断请求可以说是一样的。
+信号（signal），又称为软中断信号，用于通知进程发生了异步事件，它是Linux系统响应某些条件而产生的一个事件，它是在软件层次上对中断机制的一种模拟，是一种异步通信方式，在原理上，一个进程收到一个信号与处理器收到一个中断请求可以说是一样的。
 
-信号是进程间通信机制中唯一的异步通信机制，一个进程不必通过任何操作来等待信号的到达，事实上，进程也不知道信号到底什么时候到达。正如我们所了解的中断服务函数一样，在中断发生的时候，就会进入中断服务函数中去处理，同样的，当进程接收到一个信号的时候，也会相应地采取一些行动。我们可以使用术语“生成（rais
-e）”表示一个信号的产生，使用术语“捕获（catch）”表示进程接收到一个信号。
+信号是进程间通信机制中唯一的异步通信机制，一个进程不必通过任何操作来等待信号的到达，事实上，进程也不知道信号到底什么时候到达。正如我们所了解的中断服务函数一样，在中断发生的时候，就会进入中断服务函数中去处理，同样的，当进程接收到一个信号的时候，也会相应地采取一些行动。我们可以使用术语"生成（raise）"表示一个信号的产生，使用术语"捕获（catch）"表示进程接收到一个信号。
 
-在linux系统中，信号可能是由于系统中某些错误而产生，也可以是摸个进程主动生成的一个信号。由于某些错误条件而生成的信号：如内存段冲突、浮点处理器错误或非法指令等，它们由shell和终端处理器生成并且引起中断。由进程主动生成的信号可以作为在进程间传递通知或修改行为的一种方式，它可以明确地由一个进程发
-送给另一个进程，当进程捕获了这个信号就会按照程序进行相应并且去处理它。无论何种情况，它们的编程接口都是相同的，信号可以被生成、捕获、响应或忽略。进程之间可以互相发送信号，内核也可以因为内部事件而给进程发送信号，通知进程发生了某个事件。
+在Linux系统中，信号可能是由于系统中某些错误而产生，也可以是摸个进程主动生成的一个信号。由于某些错误条件而生成的信号：如内存段冲突、浮点处理器错误或非法指令等，它们由shell和终端处理器生成并且引起中断。由进程主动生成的信号可以作为在进程间传递通知或修改行为的一种方式，它可以明确地由一个进程发送给另一个进程，当进程捕获了这个信号就会按照程序进行相应并且去处理它。无论何种情况，它们的编程接口都是相同的，信号可以被生成、捕获、响应或忽略。进程之间可以互相发送信号，内核也可以因为内部事件而给进程发送信号，通知进程发生了某个事件。
 
 系统支持的信号
-^^^^^^^
+~~~~~~~~~~~~~~
 
 我们可以使用kill 命令来查看系统中支持的信号种类：
 
-命令
-
-kill -l
-
-|signal002|
-
-图 38‑1 linux系统支持的信号
-
-从图中可以看出，linux系统支持信号62 种信号，每种信号名称都以SIG三个字符开头，注意，没有信号值为32和33的信号。
-
-可以将这62中信号分为2大类：信号值为1~31的信号属性非实时信号（也称为不可靠信号），它们是从 UNIX 系统中继承下来的信号，具体的作用见表格 38‑1，信号值为34~64的信号为实时信号（也被称为可靠信号）。
-
-表格 38‑1 linux信号种类与描述
-
-====== ========= ============================================================================================================================================================================================================================================================================================================================================ ==============================
-信号值 名称      描述                                                                                                                                                                                                                                                                                                                                         默认处理
-====== ========= ============================================================================================================================================================================================================================================================================================================================================ ==============================
-1      SIGHUP    控制终端被关闭时产生。                                                                                                                                                                                                                                                                                                                       终止
-2      SIGINT    程序终止(interrupt)信号，在用户键入INTR字符（通常是Ctrl + C）时发出，用于通知前台进程组终止进程。                                                                                                                                                                                                                                            终止
-3      SIGQUIT   和SIGINT类似，但由QUIT字符（通常是Ctrl + \\）来控制，进程在因收到SIGQUIT退出时会产生core文件，在这个意义上类似于一个程序错误信号。                                                                                                                                                                                                           终止并产生转储文件（core文件）
-4      SIGILL    CPU检测到某进程执行了非法指令时产生，通常是因为可执行文件本身出现错误， 或者试图执行数据段、堆栈溢出时也有可能产生这个信号。                                                                                                                                                                                                                 终止并产生转储文件
-5      SIGTRAP   由断点指令或其它trap指令产生，由debugger使用。                                                                                                                                                                                                                                                                                               终止并产生转储文件
-6      SIGABRT   调用系统函数 abort()时产生。                                                                                                                                                                                                                                                                                                                 终止并产生转储文件
-7      SIGBUS    总线错误时产生。一般是非法地址，包括内存地址对齐（alignment）出错。比如访问一个四个字长的整数，但其地址不是4的倍数。它与SIGSEGV的区别在于后者是由于对合法存储地址的非法访问触发的（如访问不属于自己存储空间或只读存储空间）。                                                                                                                终止并产生转储文件
-8      SIGFPE    处理器出现致命的算术运算错误时产生，不仅包括浮点运算错误，还包括溢出及除数为0等其它所有的算术的错误。                                                                                                                                                                                                                                        终止并产生转储文件
-9      SIGKILL   系统杀戮信号。用来立即结束程序的运行，本信号不能被阻塞、处理和忽略。如果管理员发现某个进程终止不了，可尝试发送这个信号将进程杀死。                                                                                                                                                                                                           终止
-10     SIGUSR1   用户自定义信号。                                                                                                                                                                                                                                                                                                                             终止
-11     SIGSEGV   访问非法内存时产生，进程试图访问未分配给自己的内存， 或试图往没有写权限的内存地址写数据。                                                                                                                                                                                                                                                    终止
-12     SIGUSR2   用户自定义信号。                                                                                                                                                                                                                                                                                                                             终止
-13     SIGPIPE   这个信号通常在进程间通信产生，比如采用FIFO（管道）通信的两个进程，读管道没打开或者意外终止就往管道写，写进程会收到SIGPIPE信号。此外用Socket通信的两个进程，写进程在写Socket的时候，读进程已经终止，也会产生这个信号。                                                                                                                        终止
-14     SIGALRM   定时器到期信号，计算的是实际的时间或时钟时间，alarm函数使用该信号。                                                                                                                                                                                                                                                                          终止
-15     SIGTERM   程序结束（terminate）信号，与SIGKILL不同的是该信号可以被阻塞和处理。通常用来要求程序自己正常退出，shell命令kill缺省产生这个信号，如果进程终止不了，才会尝试SIGKILL。                                                                                                                                                                         终止
-16     SIGSTKFLT 已废弃。                                                                                                                                                                                                                                                                                                                                     终止
-17     SIGCHLD   子进程暂停或终止时产生，父进程将收到这个信号，如果父进程没有处理这个信号，也没有等待（wait）子进程，子进程虽然终止，但是还会在内核进程表中占有表项，这时的子进程称为僵尸进程，这种情况我们应该避免。父进程默认是忽略SIGCHILD信号的，我们可以捕捉它，做成异步等待它派生的子进程终止，或者父进程先终止，这时子进程的终止自动由init进程来接管。 忽略
-18     SIGCONT   系统恢复运行信号，让一个停止（stopped）的进程继续执行，本信号不能被阻塞，可以用一个handler来让程序在由stopped状态变为继续执行时完成特定的工作 。                                                                                                                                                                                             恢复运行
-19     SIGSTOP   系统暂停信号，停止进程的执行. 注意它和terminate以及interrupt的区别：该进程还未结束，只是暂停执行，本信号不能被阻塞，处理或忽略。                                                                                                                                                                                                             暂停
-20     SIGTSTP   由控制终端发起的暂停信号，停止进程的运行，但该信号可以被处理和忽略，比如用户键入SUSP字符时（通常是Ctrl+Z）发出这个信号。                                                                                                                                                                                                                     暂停
-21     SIGTTIN   后台进程发起输入请求时控制终端产生该信号。                                                                                                                                                                                                                                                                                                   暂停
-22     SIGTTOU   后台进程发起输出请求时控制终端产生该信号。                                                                                                                                                                                                                                                                                                   暂停
-23     SIGURG    套接字上出现紧急数据时产生。                                                                                                                                                                                                                                                                                                                 忽略
-24     SIGXCPU   处理器占用时间超出限制值时产生。                                                                                                                                                                                                                                                                                                             终止并产生转储文件
-25     SIGXFSZ   文件尺寸超出限制值时产生。                                                                                                                                                                                                                                                                                                                   终止并产生转储文件
-26     SIGVTALRM 由虚拟定时器产生的虚拟时钟信号，类似于SIGALRM，但是计算的是该进程占用的CPU时间。                                                                                                                                                                                                                                                             终止
-27     SIGPROF   类似于SIGALRM / SIGVTALRM，但包括该进程用的CPU时间以及系统调用的时间。                                                                                                                                                                                                                                                                       终止
-28     SIGWINCH  窗口大小改变时发出。                                                                                                                                                                                                                                                                                                                         忽略
-29     SIGIO     文件描述符准备就绪, 可以开始进行输入/输出操作。                                                                                                                                                                                                                                                                                              终止
-30     SIGPWR    启动失败时产生。                                                                                                                                                                                                                                                                                                                             终止
-31     SIGUNUSED 非法的系统调用。                                                                                                                                                                                                                                                                                                                             终止并产生转储文件
-====== ========= ============================================================================================================================================================================================================================================================================================================================================ ==============================
+**命令**
+
+.. code:: bash
+
+    kill -l
+
+.. figure:: media/signal002.png
+   :alt: signal002
+
+   signal002
+图 38‑1 Linux系统支持的信号
+
+从图中可以看出，Linux系统支持信号62种信号，每种信号名称都以SIG三个字符开头，注意，没有信号值为32和33的信号。
+
+可以将这62中信号分为2大类：信号值为1~31的信号属性非实时信号（也称为不可靠信号），它们是从UNIX
+系统中继承下来的信号，具体的作用见表格
+38‑1，信号值为34~64的信号为实时信号（也被称为可靠信号）。
+
+表格 38‑1 Linux信号种类与描述
+
++----------+-------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------+
+| 信号值   | 名称        | 描述                                                                                                                                                                                                                                                                                                                                           | 默认处理                         |
++==========+=============+================================================================================================================================================================================================================================================================================================================================================+==================================+
+| 1        | SIGHUP      | 控制终端被关闭时产生。                                                                                                                                                                                                                                                                                                                         | 终止                             |
++----------+-------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------+
+| 2        | SIGINT      | 程序终止(interrupt)信号，在用户键入INTR字符（通常是Ctrl + C）时发出，用于通知前台进程组终止进程。                                                                                                                                                                                                                                              | 终止                             |
++----------+-------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------+
+| 3        | SIGQUIT     | SIGQUIT 和SIGINT类似，但由QUIT字符（通常是Ctrl + ）来控制，进程在因收到SIGQUIT退出时会产生core文件，在这个意义上类似于一个程序错误信号。                                                                                                                                                                                                       | 终止并产生转储文件（core文件）   |
++----------+-------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------+
+| 4        | SIGILL      | CPU检测到某进程执行了非法指令时产生，通常是因为可执行文件本身出现错误， 或者试图执行数据段、堆栈溢出时也有可能产生这个信号。                                                                                                                                                                                                                   | 终止并产生转储文件（core文件）   |
++----------+-------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------+
+| 5        | SIGTRAP     | 由断点指令或其它trap指令产生，由debugger使用。                                                                                                                                                                                                                                                                                                 | 终止并产生转储文件（core文件）   |
++----------+-------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------+
+| 6        | SIGABRT     | 调用系统函数 abort()时产生。                                                                                                                                                                                                                                                                                                                   | 终止并产生转储文件（core文件）   |
++----------+-------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------+
+| 7        | SIGBUS      | 总线错误时产生。一般是非法地址，包括内存地址对齐（alignment）出错。比如访问一个四个字长的整数，但其地址不是4的倍数。它与SIGSEGV的区别在于后者是由于对合法存储地址的非法访问触发的（如访问不属于自己存储空间或只读存储空间）。                                                                                                                  | 终止并产生转储文件（core文件）   |
++----------+-------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------+
+| 8        | SIGFPE      | 处理器出现致命的算术运算错误时产生，不仅包括浮点运算错误，还包括溢出及除数为0等其它所有的算术的错误。                                                                                                                                                                                                                                          | 终止并产生转储文件（core文件）   |
++----------+-------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------+
+| 9        | SIGKILL     | 系统杀戮信号。用来立即结束程序的运行，本信号不能被阻塞、处理和忽略。如果管理员发现某个进程终止不了，可尝试发送这个信号将进程杀死。                                                                                                                                                                                                             | 终止                             |
++----------+-------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------+
+| 10       | SIGUSR1     | 用户自定义信号。                                                                                                                                                                                                                                                                                                                               | 终止                             |
++----------+-------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------+
+| 11       | SIGSEGV     | 访问非法内存时产生，进程试图访问未分配给自己的内存，或试图往没有写权限的内存地址写数据。                                                                                                                                                                                                                                                       | 终止                             |
++----------+-------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------+
+| 12       | SIGUSR2     | 用户自定义信号。                                                                                                                                                                                                                                                                                                                               | 终止                             |
++----------+-------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------+
+| 13       | SIGPIPE     | 这个信号通常在进程间通信产生，比如采用FIFO（管道）通信的两个进程，读管道没打开或者意外终止就往管道写，写进程会收到SIGPIPE信号。此外用Socket通信的两个进程，写进程在写Socket的时候，读进程已经终止，也会产生这个信号。                                                                                                                          | 终止                             |
++----------+-------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------+
+| 14       | SIGALRM     | 定时器到期信号，计算的是实际的时间或时钟时间，alarm函数使用该信号。                                                                                                                                                                                                                                                                            | 终止                             |
++----------+-------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------+
+| 15       | SIGTERM     | 程序结束（terminate）信号，与SIGKILL不同的是该信号可以被阻塞和处理。通常用来要求程序自己正常退出，shell命令kill缺省产生这个信号，如果进程终止不了，才会尝试SIGKILL。                                                                                                                                                                           | 终止                             |
++----------+-------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------+
+| 16       | SIGSTKFLT   | 已废弃。                                                                                                                                                                                                                                                                                                                                       | 终止                             |
++----------+-------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------+
+| 17       | SIGCHLD     | 子进程暂停或终止时产生，父进程将收到这个信号，如果父进程没有处理这个信号，也没有等待（wait）子进程，子进程虽然终止，但是还会在内核进程表中占有表项，这时的子进程称为僵尸进程，这种情况我们应该避免。父进程默认是忽略SIGCHILD信号的，我们可以捕捉它，做成异步等待它派生的子进程终止，或者父进程先终止，这时子进程的终止自动由init进程来接管。   | 忽略                             |
++----------+-------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------+
+| 18       | SIGCONT     | 系统恢复运行信号，让一个停止（stopped）的进程继续执行，本信号不能被阻塞，可以用一个handler来让程序在由stopped状态变为继续执行时完成特定的工作                                                                                                                                                                                                  | 恢复运行                         |
++----------+-------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------+
+| 19       | SIGSTOP     | 系统暂停信号，停止进程的执行。注意它和terminate以及interrupt的区别：该进程还未结束，只是暂停执行，本信号不能被阻塞，处理或忽略。                                                                                                                                                                                                               | 暂停                             |
++----------+-------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------+
+| 20       | SIGTSTP     | 由控制终端发起的暂停信号，停止进程的运行，但该信号可以被处理和忽略，比如用户键入SUSP字符时（通常是Ctrl+Z）发出这个信号。                                                                                                                                                                                                                       | 暂停                             |
++----------+-------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------+
+| 21       | SIGTTIN     | 后台进程发起输入请求时控制终端产生该信号。                                                                                                                                                                                                                                                                                                     | 暂停                             |
++----------+-------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------+
+| 22       | SIGTTOU     | 后台进程发起输出请求时控制终端产生该信号。                                                                                                                                                                                                                                                                                                     | 暂停                             |
++----------+-------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------+
+| 23       | SIGURG      | 套接字上出现紧急数据时产生。                                                                                                                                                                                                                                                                                                                   | 忽略                             |
++----------+-------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------+
+| 24       | SIGXCPU     | 处理器占用时间超出限制值时产生。                                                                                                                                                                                                                                                                                                               | 终止并产生转储文件（core文件）   |
++----------+-------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------+
+| 25       | SIGXFSZ     | 文件尺寸超出限制值时产生。                                                                                                                                                                                                                                                                                                                     | 终止并产生转储文件（core文件）   |
++----------+-------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------+
+| 26       | SIGVTALRM   | 由虚拟定时器产生的虚拟时钟信号，类似于SIGALRM，但是计算的是该进程占用的CPU时间。                                                                                                                                                                                                                                                               | 终止                             |
++----------+-------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------+
+| 27       | SIGPROF     | 类似于SIGALRM / SIGVTALRM，但包括该进程用的CPU时间以及系统调用的时间。                                                                                                                                                                                                                                                                         | 终止                             |
++----------+-------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------+
+| 28       | SIGWINCH    | 窗口大小改变时发出。                                                                                                                                                                                                                                                                                                                           | 忽略                             |
++----------+-------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------+
+| 29       | SIGIO       | 文件描述符准备就绪, 可以开始进行输入/输出操作。                                                                                                                                                                                                                                                                                                | 终止                             |
++----------+-------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------+
+| 30       | SIGPWR      | 启动失败时产生。                                                                                                                                                                                                                                                                                                                               | 终止                             |
++----------+-------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------+
+| 31       | SIGUNUSED   | 非法的系统调用。                                                                                                                                                                                                                                                                                                                               | 终止并产生转储文件（core文件）   |
++----------+-------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------+
 
 对于表格 38‑1，有几点需要注意的地方：
 
-1. 信号的“值”在 x86、PowerPC 和 ARM 平台下是有效的，但是别的平台的信号值也许跟这个表的不一致。
-
-2. “描述”中注明的一些情况发生时会产生相应的信号，但并不是说该信号的产生就一定发生了这个事件。事实上，任何进程都可以使用 kill()函数来产生任何信号。
-
-3. 信号 SIGKILL 和 SIGSTOP 是两个特殊的信号，他们不能被忽略、阻塞或捕捉，只能按缺省动作来响应。
-
+1. 信号的"值"在 x86、PowerPC 和
+   ARM平台下是有效的，但是别的平台的信号值也许跟这个表的不一致。
+2. "描述"中注明的一些情况发生时会产生相应的信号，但并不是说该信号的产生就一定发生了这个事件。事实上，任何进程都可以使用kill()函数来产生任何信号。
+3. 信号 SIGKILL 和 SIGSTOP
+   是两个特殊的信号，他们不能被忽略、阻塞或捕捉，只能按缺省动作来响应。
 4. 一般而言，信号的响应处理过程如下：如果该信号被阻塞，那么将该信号挂起，不对其做任何处理，等到解除对其阻塞为止。如果该信号被捕获，那么进一步判断捕获的类型，如果设置了响应函数，那么执行该响应函数；如果设置为忽略，那么直接丢弃该信号。最后才执行信号的默认处理。
 
 非实时信号与实时信号
-^^^^^^^^^^
+~~~~~~~~~~~~~~~~~~~~
 
-linux 系统中有许多信号，其中前面 31 个信号都有一个特殊的名字，对应一个特殊的事件，比如 信号值为1的信号 SIGHUP（Signal Hang UP），这个信号就是通知系统关闭中断的，当系统中的一个控制终端被关闭（即挂断， hang up）时，都会产生这个信号。
+Linux 系统中有许多信号，其中前面 31
+个信号都有一个特殊的名字，对应一个特殊的事件，比如 信号值为1的信号
+SIGHUP（Signal Hang
+UP），这个信号就是通知系统关闭中断的，当系统中的一个控制终端被关闭（即挂断，
+hang up）时，都会产生这个信号。
 
-信号值为1~31的信号属性非实时信号，它主要是因为这类信号不支持排队，因此信号可能会丢失。比如发送多次相同的信号，进程只能收到一次，也只会处理一次，因此剩下的信号将被丢弃。而实时信号（信号值为34~64的信号）则不同，它是支持排队的，发送了多少个信号给进程，进程就会处理多少次。
+信号值为1 :sub:`31的信号属性非实时信号，它主要是因为这类信号不支持排队，因此信号可能会丢失。比如发送多次相同的信号，进程只能收到一次，也只会处理一次，因此剩下的信号将被丢弃。而实时信号（信号值为34` 64的信号）则不同，它是支持排队的，发送了多少个信号给进程，进程就会处理多少次。
 
-为什么说信号还有可靠与不可靠呢，这得从信号的处理过程来介绍了：一般来说，一个进程收到一个信号后不会被立即处理，而是在恰当时机进行处理！一般是在中断返回的时候，或者内核态返回用户态的时候 （这种情况是比较常见的处理方式）。
+为什么说信号还有可靠与不可靠呢，这得从信号的处理过程来介绍了：一般来说，一个进程收到一个信号后不会被立即处理，而是在恰当时机进行处理！一般是在中断返回的时候，或者内核态返回用户态的时候
+（这种情况是比较常见的处理方式）。
 
-也就是说，即使这些信号到来了，进程也不一定会立即去处理它，因为系统不会为了处理一个信号而把当前正在运行的进程挂起，这样的话系统的资源消耗太大了，如果不是紧急信号，是不会立即处理的，所以系统一般都会选择在内核态切换回用户态的时候处理信号。比如有时候进程处于休眠状态，但是又收到了一个信号，于是系统就得把
-信号储存在进程唯一的 PCB（进程控制块） 当中，而非实时信号则是不支持排队的，假如此时又有一个信号到来，那么它将被丢弃，这样进程就无法处理这个信号，所以它是不可靠的。对于实时信号则没有这种顾虑，因为它支持排队，信号是不会被丢弃的，这样子每个到来的信号都能得到有效处理。
+也就是说，即使这些信号到来了，进程也不一定会立即去处理它，因为系统不会为了处理一个信号而把当前正在运行的进程挂起，这样的话系统的资源消耗太大了，如果不是紧急信号，是不会立即处理的，所以系统一般都会选择在内核态切换回用户态的时候处理信号。比如有时候进程处于休眠状态，但是又收到了一个信号，于是系统就得把信号储存在进程唯一的
+PCB（进程控制块）当中，而非实时信号则是不支持排队的，假如此时又有一个信号到来，那么它将被丢弃，这样进程就无法处理这个信号，所以它是不可靠的。对于实时信号则没有这种顾虑，因为它支持排队，信号是不会被丢弃的，这样子每个到来的信号都能得到有效处理。
 
 信号的处理
-~~~~~
+----------
 
-生成信号的事件一般可以归为3大类：程序错误、外部事件以及显式请求。例如零作除数、非法存储访问等，这种情况通常是由硬件而不是由linux内核检测到的，但由内核向发生此错误的那个进程发送相应的信号；例如当用户在终端按下某些键时产生终端生成的信号，当进程超越了CPU或文件大小的限制时，内核会生成一个信号通
-知进程；例如使用kill()函数允许进程发送任何信号给其他进程或进程组。
+生成信号的事件一般可以归为3大类：程序错误、外部事件以及显式请求。例如零作除数、非法存储访问等，这种情况通常是由硬件而不是由Linux内核检测到的，但由内核向发生此错误的那个进程发送相应的信号；例如当用户在终端按下某些键时产生终端生成的信号，当进程超越了CPU或文件大小的限制时，内核会生成一个信号通知进程；例如使用kill()函数允许进程发送任何信号给其他进程或进程组。
 
 信号的生成既可以是同步的，也可以是异步的。同步信号大多数是程序执行过程中出现了某个错误而产生的，由进程显式请求生成的给自己的信号也是同步的。
 
-异步信号是接收进程可控制之外的事件所生成的信号，这类信号一般是进程无法控制的，只能被动接收，因为进程也不知道这个信号会何时发生，只能在发生的时候去处理它。一般外部事件总是异步地生成信号，异步信号可在进程运行中的任意时刻产生，进程无法预期信号到达的时刻，它所能做的只是告诉linux内核假如有信号生成时
-应当采取什么行动（这相当于注册信号对应的处理）。
+异步信号是接收进程可控制之外的事件所生成的信号，这类信号一般是进程无法控制的，只能被动接收，因为进程也不知道这个信号会何时发生，只能在发生的时候去处理它。一般外部事件总是异步地生成信号，异步信号可在进程运行中的任意时刻产生，进程无法预期信号到达的时刻，它所能做的只是告诉Linux内核假如有信号生成时应当采取什么行动（这相当于注册信号对应的处理）。
 
-无论是同步还是异步信号，当信号发生时，我们可以告诉linux内核采取如下3种动作中的任意一种：
+无论是同步还是异步信号，当信号发生时，我们可以告诉Linux内核采取如下3种动作中的任意一种：
 
 -  忽略信号。大部分信号都可以被忽略，但有两个除外：SIGSTOP和SIGKILL绝不会被忽略。不能忽略这两个信号的原因是为了给超级用户提供杀掉或停止任何进程的一种手段。此外，尽管其他信号都可以被忽略，但其中有一些却不宜忽略。例如，若忽略硬件例外（非法指令）信号，则会导致进程的行为不确定。
-
--  捕获信号。这种处理是要告诉linux内核，当信号出现时调用专门提供的一个函数。这个函数称为信号处理函数，它专门对产生信号的事件作出处理。
-
--  让信号默认动作起作用。系统为每种信号规定了一个默认动作，这个动作由linux内核来完成，有以下几种可能的默认动作：
+-  捕获信号。这种处理是要告诉Linux内核，当信号出现时调用专门提供的一个函数。这个函数称为信号处理函数，它专门对产生信号的事件作出处理。
+-  让信号默认动作起作用。系统为每种信号规定了一个默认动作，这个动作由Linux内核来完成，有以下几种可能的默认动作：
 
 1. 终止进程并且生成内存转储文件，即写出进程的地址空间内容和寄存器上下文至进程当前目录下名为cone的文件中；
-
 2. 终止终止进程但不生成core文件。
-
 3. 忽略信号。
-
 4. 暂停进程。
-
 5. 若进程是暂停暂停，恢复进程，否则将忽略信号。
 
 我们可以写个小程序验证一下一些控制信号，比如SIGINT 。
@@ -133,102 +159,111 @@ linux 系统中有许多信号，其中前面 31 个信号都有一个特殊的
 
 代码清单 38‑1 测试信号代码
 
-1 int main(void)
-
-2 {
-
-3 while (1) {
-
-4 printf("please input \\"Ctrl + C\" to terminate \\
-
-5 the test process!\n");
-
-6 sleep(1);
-
-7 }
+.. code:: c
 
-8 exit(0);
+    int main(void)
+    {
+        while (1) {
+            printf("please input \"Ctrl + C\" to terminate the test process!");
+            sleep(1);
+        }
+        exit(0);
+    }
 
-9 }
+编译后运行，可以看到终端中一直打印"please input "Ctrl + C" to terminate
+the test process!"这句话，我们按下Ctrl +
+C键，就能终止这个进程，这是因为在按下Ctrl+C组合键时会产生的SIGINT信号，将进程终止，具体见图38‑2。
 
-编译后运行，可以看到终端中一直打印“please input "Ctrl + C" to terminate the test process!”这句话，我们按下Ctrl + C键，就能终止这个进程，这是因为在按下Ctrl+C组合键时会产生的SIGINT信号，将进程终止，具体见图 38‑2。
-
-|signal003|
+.. figure:: media/signal003.png
+   :alt: signal003
 
+   signal003
 图 38‑2 测试结果
 
 发送信号相关API函数
-~~~~~~~~~~~
+-------------------
 
 发送信号的函数主要有 kill()、 raise()、alarm()，下面就依次对其进行介绍。
 
 kill()
-^^^^^^
+~~~~~~
 
 在讲解这个函数之前，我们先用kill命令去终止一个进程吧，具体操作如下：
 
-1. 先使用ps –ux命令查看当前有什么进程可以终止的，如果没有则可以打开一个终端，因为终端也是一个进程，我们把这个进程终止就好了。
-
-命令
-
-ps –ux
+1. 先使用 ``ps –ux`` 命令查看当前有什么进程可以终止的，如果没有则可以打开一个终端，因为终端也是一个进程，我们把这个进程终止就好了。
 
-输出
+**命令：**
 
-USER PID %CPU %MEM VSZ RSS TTY STAT START TIME COMMAND
+.. code:: bash
 
-xxx 22133 0.3 0.0 14916 4820 pts/5 Ss 07:49 0:00 /bin/bashxxx 22142 0.5 0.0 14916 4768 pts/6 Ss+ 07:49 0:00 /bin/bashxxx 22151 0.0 0.0 29580 1500
-pts/5 R+ 07:50 0:00 ps -uxxxx 24331 0.0 0.0 15156 5244 pts/3 Ss+ 03:12 0:00 /bin/bash
+    ps –ux
 
-2. 可能不同的电脑输出的内容是不一样的，但是我们可以看到最后一列的进程名字（bash）就是终端，那么我们可以关闭其中一个终端，目前我打开了3个终端。
+    # 输出
+    USER   PID   %CPU  %MEM    VSZ     RSS TTY     STAT  START   TIME COMMAND
+    xxx    22133   0.3     0.0        14916  4820 pts/5    Ss     07:49   0:00 /bin/bash
+    xxx    22142   0.5     0.0        14916  4768 pts/6    Ss+   07:49   0:00 /bin/bash
+    xxx    22151   0.0     0.0        29580  1500 pts/5    R+    07:50   0:00 ps -ux
+    xxx    24331   0.0     0.0        15156  5244 pts/3    Ss+   03:12   0:00 /bin/bash
 
-3. 输入kill 22142终止终端6进程，这样子就可以看到终端6被关闭了，kill命令的语法如下：
+1. 可能不同的电脑输出的内容是不一样的，但是我们可以看到最后一列的进程名字（bash）就是终端，那么我们可以关闭其中一个终端，目前我打开了3个终端。
+2. 输入 ``kill 22142`` （注意，此处的22142是PID）终止终端6进程，这样子就可以看到终端6被关闭了，kill命令的语法如下：
 
 命令语法：
 
-kill [信号或选项] PID(s)
+.. code:: bash
+
+    kill [信号或选项] PID(s)
 
-备注：
+**备注：**
 
 [信号或选项]是可选部分。
 
 PID(s)是目标进程的ID，可以是一个进程也可以是多个进程。
 
-如果想发送一个信号给进程，而该进程并不是当前的前台进程，就需要使用kill命令。该命令需要有一个可选的信号代码或信号名称和一个接收信号的目标进程的PID（这个PID一般需要用ps命令查出来），例如，如果要向运行在另一个终端上的PID为666的进程发送“挂断”信号（SIGHUP），可以使用如下命令：
+如果想发送一个信号给进程，而该进程并不是当前的前台进程，就需要使用kill命令。该命令需要有一个可选的信号代码或信号名称和一个接收信号的目标进程的PID（这个PID一般需要用ps命令查出来），例如，如果要向运行在另一个终端上的PID为666的进程发送"挂断"信号（SIGHUP），可以使用如下命令：
 
-命令
+**命令**
+
+.. code:: bash
 
-kill - SIGHUP 666
+    kill - SIGHUP 666
 
-或者
+    # 或者
 
-kill -1 666
+    kill -1 666
 
 备注：这里的-1是指信号值为1 的SIGHUP信号
 
-演示完kill命令，就来看看linux系统中信号操作相关的函数，kill()函数与kill 系统命令一样， 可以发送信号给进程或进程组，实际上， kill 系统命令只是 kill()函数的一个用户接口。这里需要注意的是，它不仅可以中止进程（实际上发出 SIGKILL
+演示完kill命令，就来看看Linux系统中信号操作相关的函数，kill()函数与kill系统命令一样，
+可以发送信号给进程或进程组，实际上， kill
+系统命令只是kill()函数的一个用户接口。这里需要注意的是，它不仅可以中止进程（实际上发出SIGKILL
 信号），也可以向进程发送其他信号。
 
 同样的，我们使用man命令去查看系统中关于kill()函数的描述：
 
 命令
 
-man 2 kill
+.. code:: bash
+
+    man 2 kill
+
 
-输出
+    输出
 
-NAME kill – 发送信号到一个进程SYNOPSIS #include <sys/types.h> #include <signal.h> int kill(pid_t pid, int sig);
+    NAME kill – 发送信号到一个进程SYNOPSIS
+
+    #include <sys/types.h>
+    #include <signal.h> 
+
+    int kill(pid_t pid, int sig);
 
 kill()函数的参数有两个，分别是pid与sig，还返回一个int类型的错误码。
 
 pid的取值如下：
 
 -  pid > 1：将信号sig发送到进程ID值为pid指定的进程。
-
 -  pid = 0：信号被发送到所有和当前进程在同一个进程组的进程。
-
 -  pid = -1：将sig发送到系统中所有的进程，但进程1（init）除外。
-
 -  pid < -1：将信号sig发送给进程组号为-pid （pid绝对值）的每一个进程。
 
 sig：信号值。
@@ -236,288 +271,241 @@ sig：信号值。
 函数返回值：
 
 -  0：发送成功。
-
 -  -1：发送失败。
 
-进程可以通过调用kill()函数向包括它本身在内的其他进程发送一个信号。如果程序没有发送该信号的权限，对kill函数的调用就将失败，失败的常见原因是目标进程由另一个用户所拥有。因此要想发送一个信号，发送进程必须拥有相应的权限，这通常意味着两个进程必须拥有相同的用户ID（即你只能发送信号给属于自己的进
-程，但超级用户可以发送信号给任何进程）。
+进程可以通过调用kill()函数向包括它本身在内的其他进程发送一个信号。如果程序没有发送该信号的权限，对kill函数的调用就将失败，失败的常见原因是目标进程由另一个用户所拥有。因此要想发送一个信号，发送进程必须拥有相应的权限，这通常意味着两个进程必须拥有相同的用户ID（即你只能发送信号给属于自己的进程，但超级用户可以发送信号给任何进程）。
 
-Kill()函数会在失败时返回-1并设置errno变量。失败的原因可能是：给定的信号无效（errno设置为EINVAL）、发送进程权限不够（errno设置为EPERM）、目标进程不存在（errno设置为ESRCH）等情况。
+Kill()函数会在失败时返回-1并设置errno变量。失败的原因可能是：给定的信号无效（errno设置为INVAL）、发送进程权限不够（errno设置为EPERM）、目标进程不存在（errno设置为ESRCH）等情况。
 
 作者注：现在暂时先不讲解这个函数的使用，待讲解完raise()函数后一起写代码做实验。
 
 raise()
-^^^^^^^
-
-raise()函数也是发送信号函数，不过与 kill()函数所不同的是， raise()函数只是进程向自身发送信号的，而没有向其他进程发送信号，可以说kill(getpid(),sig)等同于raise(sig)。下面使用man命令查看一下raise()函数的相关信息
-
-头文件
-
-#include <signal.h>
-
-函数原型
-
-int raise(int sig);
-
-raise()函数只有一个参数sig，它代表着发送的信号值，如果发送成功则返回0，发送失败则返回-1，发送失败的原因主要是信号无效，因为它只往自身发送信号，不存在权限问题，也不存在目标进程不存在的情况。
-
-我们来做个小实验，实验代码在野火提供资料的application/kill目录下，里面有一个kill.c源码文件，具体内容如代码清单 38‑2所示。
-
-代码清单 38‑2 kill.c实验源码文件内容
-
-1 #include <unistd.h>
-
-2 #include <stdio.h>
-
-3 #include <stdlib.h>
-
-4 #include <signal.h>
-
-5 #include <sys/types.h>
-
-6 #include <sys/wait.h>
-
-7
-
-8 int main(void)
-
-9 {
-
-10 pid_t pid;
-
-11
-
-12 int ret;
-
-13
-
-14 /\* fork启动一个子进程 \*/
-
-15 if ((pid = fork()) < 0) { **(1)**
-
-16 printf("Fork error\n");
-
-17 exit(1);
-
-18 }
-
-19
-
-20 if (pid == 0) { **(2)**
-
-21 /\* 在子进程中使用 raise()函数发出 SIGSTOP 信号,使子进程暂停 \*/
-
-22 printf("Child(pid : %d) is waiting for any signal\n", getpid());
-
-23
-
-24 /*\* 子进程停在这里 \*/
-
-25 raise(SIGSTOP); **(3)**
+~~~~~~~
 
-26
+raise()函数也是发送信号函数，不过与 kill()函数所不同的是，
+raise()函数只是进程向自身发送信号的，而没有向其他进程发送信号，可以说kill(getpid(),sig)等同于raise(sig)。下面使用man命令查看一下raise()函数的相关信息
 
-27 exit(0);
+**头文件**
 
-28 }
+.. code:: c
 
-29
+    #include <signal.h>
 
-30 else {
+**函数原型**
 
-31 /*\* 等待一下，等子进程先执行 \*/
+.. code:: c
 
-32 sleep(1); **(4)**
+    int raise(int sig);
 
-33
+raise()函数只有一个参数sig，它代表着发送的信号值，如果发送成功则返回0，发送失败则返回-1，发送失败的原因主要是信号无效，因为它只往自身发送信号，不存在权限问题，也不存在目标进程不存在的情况。
 
-34 /\* 在父进程中收集子进程发出的信号(不阻塞)，并调用 kill()函数进行相应的操作 \*/
+我们来做个小实验，实验代码在野火提供资料的system_programing/kill目录下，里面有一个kill.c源码文件，具体内容如代码清单38‑2所示。
 
-35 if ((waitpid(pid, NULL, WNOHANG)) == 0) { **(5)**
+代码清单 38‑2 kill.c实验源码文件内容
 
-36 /*\* 子进程还没退出，返回为0，就发送SIGKILL信号杀死子进程 \*/
+.. code:: c
 
-37 if ((ret = kill(pid, SIGKILL)) == 0) { **(6)**
+    #include <unistd.h>
+    #include <stdio.h>
+    #include <stdlib.h>
+    #include <signal.h>
+    #include <sys/types.h>
+    #include <sys/wait.h>
 
-38 printf("Parent kill %d\n",pid);
+    int main(void)
+    {
+        pid_t pid;
 
-39 }
+        int ret;
 
-40 }
+        /* 创建一子进程 */
+        if ((pid = fork()) < 0) {               // (1)
+            printf("Fork error\n");
+            exit(1);
+        }
 
-41
+        if (pid == 0) {                          // (2)
+            /* 在子进程中使用 raise()函数发出 SIGSTOP 信号,使子进程暂停 */
+            printf("Child(pid : %d) is waiting for any signal\n\n", getpid());
 
-42 /*\* 一直阻塞直到子进程退出（杀死） \*/
+            /** 子进程停在这里 */
+            raise(SIGSTOP);                     // (3)
 
-43 waitpid(pid, NULL, 0); **(7)**
+            exit(0);
+        }
 
-44
+        else {                                  // (4)
+            /** 等待一下，等子进程先执行 */
+            sleep(1);
 
-45 exit(0);
+            /* 在父进程中收集子进程发出的信号(不阻塞)，并调用 kill()函数进行相应的操作 */
+            if ((waitpid(pid, NULL, WNOHANG)) == 0) {       // (5)
+                /** 子进程还没退出，返回为0，就发送SIGKILL信号杀死子进程 */
+                if ((ret = kill(pid, SIGKILL)) == 0) {
+                    printf("Parent kill %d\n\n",pid);       // (6)
+                }
+            }
 
-46 }
+            /** 一直阻塞直到子进程退出（杀死） */
+            waitpid(pid, NULL, 0);              // (7)
 
-47 }
+            exit(0);
+        }
+    }
 
-代码清单 38‑2\ **(1)**\ ：fork启动一个子进程，如果返回值小于0（值为-1），则表示启动失败。
+代码清单 38‑2
+**(1)** ：fork启动一个子进程，如果返回值小于0（值为-1），则表示启动失败。
 
-代码清单 38‑2\ **(2)**\ ：如果返回值为0，则表示此时运行的是子进程，打印相关信息。
+代码清单 38‑2
+**(2)** ：如果返回值为0，则表示此时运行的是子进程，打印相关信息。
 
-代码清单 38‑2\ **(3)**\ ：在子进程中使用 raise()函数发出 SIGSTOP 信号，使子进程暂停。
+代码清单 38‑2 **(3)** ：在子进程中使用 raise()函数发出
+SIGSTOP信号，使子进程暂停。
 
-代码清单 38‑2\ **(4)**\ ：而如果运行的是父进程，则等待一下，让子进程先执行。
+代码清单 38‑2
+**(4)** ：而如果运行的是父进程，则等待一下，让子进程先执行。
 
-代码清单 38‑2\ **(5)**\ ：在父进程中使用waitpid()函数收集子进程发出的信号（不阻塞）。
+代码清单 38‑2
+**(5)** ：在父进程中使用waitpid()函数收集子进程发出的信号（不阻塞）。
 
-代码清单 38‑2\ **(6)**\ ：如果子进程还未退出，则调用kill()函数向子进程发送终止信号，子进程收到这个信号后会被杀死。
+代码清单 38‑2
+**(6)** ：如果子进程还未退出，则调用kill()函数向子进程发送终止信号，子进程收到这个信号后会被杀死。
 
-代码清单 38‑2\ **(7)**\ ：使用waitpid()函数回收子进程资源，如果子进程未终止，父进程则会一直阻塞等待，直到子进程终止。
+代码清单 38‑2
+**(7)** ：使用waitpid()函数回收子进程资源，如果子进程未终止，父进程则会一直阻塞等待，直到子进程终止。
 
-进入application/kill目录下，该目录下有编译使用的Makefile文件，我们直接运行make命令即可编译生成“targets”可执行文件，然后运行该文件即可，可以看到终端输出了对应的代码，且子进程也被终止了，父进程才会退出，现象如图 38‑3所示。
+进入 ``system_programing/kill`` 目录下，该目录下有编译使用的Makefile文件，我们直接运行make命令即可编译生成"targets"可执行文件，然后运行该文件即可，可以看到终端输出了对应的代码，且子进程也被终止了，父进程才会退出，现象如图
+38‑3所示。
 
-|signal004|
+.. figure:: media/signal004.png
+   :alt: signal004
 
+   signal004
 图 38‑3 kil()函数实验现象
 
 alarm()
-^^^^^^^
-
-alarm()也称为闹钟函数，它可以在进程中设置一个定时器，当定时器指定的时间到时，它就向进程发送SIGALARM 信号。如果在seconds秒内再次调用了alarm()函数设置了新的闹钟，则新的设置将覆盖前面的设置，即之前设置的秒数被新的闹钟时间取代，如果新的seconds
-为0，则之前设置的闹钟会被取消，并将剩下的时间返回。因此它的返回值是之前闹钟的剩余秒数，如果之前未设闹钟则返回0，以下是alarm()函数的函数原型与使用该函数需要的头文件。
-
-头文件
-
-#include <unistd.h>
+~~~~~~~
 
-函数原型
+alarm()也称为闹钟函数，它可以在进程中设置一个定时器，当定时器指定的时间到时，它就向进程发送SIGALARM信号。如果在seconds秒内再次调用了alarm()函数设置了新的闹钟，则新的设置将覆盖前面的设置，即之前设置的秒数被新的闹钟时间取代，如果新的seconds为0，则之前设置的闹钟会被取消，并将剩下的时间返回。因此它的返回值是之前闹钟的剩余秒数，如果之前未设闹钟则返回0，以下是alarm()函数的函数原型与使用该函数需要的头文件。
 
-unsigned int alarm(unsigned int seconds);
+**头文件**
 
-了解了alarm()函数的功能特性和返回值的特性后，我们就可以对其测试。测试方向有两个：其一，测试常规只单独存在一个闹钟函数alarm()的程序；其二，测试程序中包含多个alarm()闹钟函数。因此整理了下面几个程序，通过比较学习更有助于理解。
+.. code:: c
 
-代码清单 38‑3 alarm()函数测试1
+    #include <unistd.h>
 
-1 int main()
+**函数原型**
 
-2 {
+.. code:: c
 
-3 printf("\nthis is an alarm test function\n\n");
+    unsigned int alarm(unsigned int seconds);
 
-4 alarm(5);
-
-5 sleep(20);
+了解了alarm()函数的功能特性和返回值的特性后，我们就可以对其测试。测试方向有两个：其一，测试常规只单独存在一个闹钟函数alarm()的程序；其二，测试程序中包含多个alarm()闹钟函数。因此整理了下面几个程序，通过比较学习更有助于理解。
 
-6 printf("end!\n");
+代码清单 38‑3 alarm()函数测试1
 
-7 return 0;
+.. code:: c
 
-8 }
+    int main() 
+    { 
+        printf("\nthis is an alarm test function\n\n");
+        alarm(5);
+        sleep(20); 
+        printf("end!\n"); 
+        return 0; 
+    }
 
-这个测试是为了验证SIGALRM信号的默认处理，实际上这个程序是定义了一个时钟alarm(5)，它的作用是让SIGALRM信号在经过5秒后传送给目前main()所在进程；接着又定义了sleep(20)，它的作用是让进程睡眠20秒的时间。当main()程序挂起5秒钟时，产生了SIGALRM信号，并且执
-行了该信号的默认处理函数，即执行exit(0)函数直接终止进程，在终止的时候还打印出来“Alarm clock”，因此最后一句printf("end!\n")代码是不会被执行的，测试结果如图 38‑4所示。
+这个测试是为了验证SIGALRM信号的默认处理，实际上这个程序是定义了一个时钟alarm(5)，它的作用是让SIGALRM信号在经过5秒后传送给目前main()所在进程；接着又定义了sleep(20)，它的作用是让进程睡眠20秒的时间。当main()程序挂起5秒钟时，产生了SIGALRM信号，并且执行了该信号的默认处理函数，即执行exit(0)函数直接终止进程，在终止的时候还打印出来"Alarm
+clock"，因此最后一句printf("end!n")代码是不会被执行的，测试结果如图
+38‑4所示。
 
-|signal005|
+.. figure:: media/signal005.png
+   :alt: signal005
 
+   signal005
 图 38‑4 alarm()函数测试结果
 
 代码清单 38‑4 alarm()函数测试2
 
-1 int main()
-
-2 {
-
-3 unsigned int seconds;
-
-4
-
-5 printf("\nthis is an alarm test function\n\n");
-
-6
-
-7 seconds = alarm(20);
+.. code:: c
 
-8
+    int main() 
+    {
+        unsigned int seconds;
 
-9 printf("last alarm seconds remaining is %d! \\n\n", seconds);
+        printf("\nthis is an alarm test function\n\n");
 
-10
+        seconds = alarm(20);
 
-11 printf("process sleep 5 seconds\n\n");
+        printf("last alarm seconds remaining is %d! \n\n", seconds);
 
-12 sleep(5);
+        printf("process sleep 5 seconds\n\n");
+        sleep(5); 
 
-13
+        printf("sleep woke up, reset alarm!\n\n");
 
-14 printf("sleep woke up, reset alarm!\n\n");
+        seconds = alarm(5);
 
-15
+        printf("last alarm seconds remaining is %d! \n\n", seconds);
 
-16 seconds = alarm(5);
+        sleep(20); 
 
-17
+        printf("end!\n"); 
 
-18 printf("last alarm seconds remaining is %d! \\n\n", seconds);
+        return 0; 
+    }
 
-19
+这个alarm测试代码是为了验证多次设置alarm的时候，会不会覆盖前一次的设置值，事实证明确实是会覆盖的。代码的逻辑非常简单，首先调用alarm(20)函数设置在20秒后产生一个SIGALRM信号，进程睡眠5秒后唤醒，再次设置alarm(5)函数在5秒后产生SIGALRM信号终止进程，此时上一个alarm设置就被覆盖了，并且返回剩余的时间（15秒），此时进程还需要睡眠，等待SIGALRM信号的到来，具体的实验现象见图38‑5。
 
-20 sleep(20);
-
-21
-
-22 printf("end!\n");
-
-23
-
-24 return 0;
-
-25 }
-
-26
-
-这个alarm测试代码是为了验证多次设置alarm的时候，会不会覆盖前一次的设置值，事实证明确实是会覆盖的。代码的逻辑非常简单，首先调用alarm(20)函数设置在20秒后产生一个SIGALRM信号，进程睡眠5秒后唤醒，再次设置alarm(5)函数在5秒后产生SIGALRM信号终止进程，此时上一个a
-larm设置就被覆盖了，并且返回剩余的时间（15秒），此时进程还需要睡眠，等待SIGALRM信号的到来，具体的实验现象见图 38‑5。
-
-|signal006|
+.. figure:: media/signal006.png
+   :alt: signal006
 
+   signal006
 图 38‑5 alarm()函数测试结果
 
 捕获信号相关API函数
-~~~~~~~~~~~
+-------------------
 
-在前面的文章作者也简单介绍了一些信号的处理方式，有很多种，而且系统也会有默认的处理方式，很多时候我们使用信号只是通知进程而不是要杀死它，这个时候就是需要我们去捕获这个信号，然后去处理它。在linux中，捕获信号的函数有很多，比如signal()、sigaction()等函数 。
+在前面的文章作者也简单介绍了一些信号的处理方式，有很多种，而且系统也会有默认的处理方式，很多时候我们使用信号只是通知进程而不是要杀死它，这个时候就是需要我们去捕获这个信号，然后去处理它。在Linux中，捕获信号的函数有很多，比如signal()、sigaction()等函数。
 
 signal()
-^^^^^^^^
+~~~~~~~~
 
-signal()主要是用于捕获信号，可以改变进程中对信号的默认行为，我们在捕获这个信号后，也可以自定义对信号的处理行为，当收到这个信号后，应该如何去处理它，这也是我们在开发linux最长使用的方式。
+signal()主要是用于捕获信号，可以改变进程中对信号的默认行为，我们在捕获这个信号后，也可以自定义对信号的处理行为，当收到这个信号后，应该如何去处理它，这也是我们在开发Linux最长使用的方式。
 
-signal()这个函数一般是跟 kill()函数配套使用的，目标进程必须先使用 signal()来为某个信号设置一个响应函数，或者设置忽略某个信号，才能改变信号的默认行为，这个过程称为“信号的捕获”。对一个信号的“捕获”可以重复进行， 不过signal()函数将会返回前一次设置的信号响应函数指针。
+signal()这个函数一般是跟 kill()函数配套使用的，目标进程必须先使用
+signal()来为某个信号设置一个响应函数，或者设置忽略某个信号，才能改变信号的默认行为，这个过程称为"信号的捕获"。对一个信号的"捕获"可以重复进行，
+不过signal()函数将会返回前一次设置的信号响应函数指针。
 
 我们可以使用man命令去查看signal()相关介绍，具体如下：
 
-头文件
+**头文件**
 
-#include <signal.h>
+.. code:: c
 
-函数原型
+    #include <signal.h>
 
-typedef void (*sighandler_t)(int);
+**函数原型**
 
-sighandler_t signal(int signum, sighandler_t handler);
+.. code:: c
 
-这个相当复杂的函数定义说明， signal是一个带有signum和handler两个参数的函数。准备捕获或忽略的信号由参数signum指出，接收到指定的信号后将要调用的函数由参数handler指出。
+    typedef void (*sighandler_t)(int);
 
-signum是指定捕获的信号，如果指定的是一个无效的信号，或者尝试处理的信号是不可捕获或不可忽略的信号（如SIGKILL）， errno将被设置为EINVAL。
+    sighandler_t signal(int signum, sighandler_t handler);
 
-handler是一个函数指针，它的类型是void (*sighandler_t)(int)类型，拥有一个int类型的参数，这个参数的作用就是传递收到的信号值，返回类型为void。
+这个相当复杂的函数定义说明，signal是一个带有signum和handler两个参数的函数。准备捕获或忽略的信号由参数signum指出，接收到指定的信号后将要调用的函数由参数handler指出。
+
+signum是指定捕获的信号，如果指定的是一个无效的信号，或者尝试处理的信号是不可捕获或不可忽略的信号（如SIGKILL），errno将被设置为EINVAL。
+
+handler是一个函数指针，它的类型是 ``void(*sighandler_t)(int)`` 类型，拥有一个int类型的参数，这个参数的作用就是传递收到的信号值，返回类型为void。
 
 signal()函数会返回一个sighandler_t类型的函数指针，这是因为调用signal()函数修改了信号的行为，需要返回之前的信号处理行为是哪个，以便让应用层知悉，如果修改信号的默认行为识别则返回对应的错误代码SIG_ERR。
 
 handler需要用户自定义处理信号的方式，当然还可以使用以下宏定义：
 
-SIG_IGN：忽略该信号。
+-  SIG_IGN：忽略该信号。
 
-SIG_DFL：采用系统默认方式处理信号。
+-  SIG_DFL：采用系统默认方式处理信号。
 
 虽然这个函数是比较简单的，但是还是要注意一下：如果调用处理程序导致信号被阻塞，则从处理程序返回后，信号将被解除阻塞。无法捕获或忽略信号SIGKILL和SIGSTOP。
 
@@ -525,133 +513,116 @@ SIG_DFL：采用系统默认方式处理信号。
 
 代码清单 38‑5 signal()函数实验
 
-1 #include <unistd.h>
-
-2 #include <stdio.h>
+.. code:: c
 
-3 #include <stdlib.h>
+    #include <unistd.h>
+    #include <stdio.h>
+    #include <stdlib.h>
+    #include <signal.h>
+    #include <sys/types.h>
+    #include <sys/wait.h>
 
-4 #include <signal.h>
+    /** 信号处理函数 */
+    void signal_handler(int sig)            //(3)
+    {
+        printf("\nthis signal numble is %d \n",sig);
 
-5 #include <sys/types.h>
+        if (sig == SIGINT) {
+            printf("I have get SIGINT!\n\n");
+            printf("The signal has been restored to the default processing mode!\n\n");
+            /** 恢复信号为默认情况 */
+            signal(SIGINT, SIG_DFL);        //(4)
+        }
 
-6 #include <sys/wait.h>
+    }
 
-7
+    int main(void)
+    {
+        printf("\nthis is an alarm test function\n\n");
 
-8 /*\* 信号处理函数 \*/
+        /** 设置信号处理的回调函数 */
+        signal(SIGINT, signal_handler);         //(1)
 
-9 void signal_handler(int sig) **(3)**
+        while (1) {
+            printf("waiting for the SIGINT signal , please enter \"ctrl + c\"...\n");
+            sleep(1);                           //(2)
+        }
 
-10 {
-
-11 printf("\nthis signal numble is %d \\n",sig);
-
-12
-
-13 if (sig == SIGINT) { **(4)**
-
-14 printf("I have get SIGINT!\n\n");
-
-15 printf("The signal has been restored to \\
-
-16 the default processing mode!\n\n");
-
-17 /*\* 恢复信号为默认情况 \*/
-
-18 signal(SIGINT, SIG_DFL);
-
-19 }
-
-20
-
-21 }
-
-22
-
-23 int main(void)
-
-24 {
-
-25 printf("\nthis is an alarm test function\n\n");
-
-26
-
-27 /*\* 设置信号处理的回调函数 \*/
-
-28 signal(SIGINT, signal_handler); **(1)**
-
-29
-
-30 while (1) {
-
-31 printf("waiting for the SIGINT signal , \\
-
-32 please enter \\"ctrl + c\"...\n");
-
-33 sleep(1); **(2)**
-
-34 }
-
-35
-
-36 exit(0);
-
-37 }
+        exit(0);
+    }
 
 解析一下这段代码：（先从第23行的main函数开始）。
 
-代码清单 38‑5\ **(1)**\ ：使用signal()函数捕获SIGINT信号（这个信号可以通过按下ctrl + c产生），当产生信号的时候就调用signal_handler()函数去处理这个信号。
+代码清单38‑5
+**(1)** ：使用signal()函数捕获SIGINT信号（这个信号可以通过按下ctrl +
+c产生），当产生信号的时候就调用signal_handler()函数去处理这个信号。
 
-代码清单 38‑5\ **(2)**\ ：在信号没有到来的时候就打印信息并且休眠。
+代码清单 38‑5 **(2)** ：在信号没有到来的时候就打印信息并且休眠。
 
-代码清单 38‑5\ **(3)**\
-：signal_handler()是信号处理函数，它传入一个int类型的信号值，在信号传递进来的时候就将对应的信号值打印出来，在此例中我们可以看到，信号处理函数使用了一个单独的整数参数，它就是引起该函数被调用的信号值。如果需要在同一个函数中处理多个信号，这个参数就很有用。
+代码清单 38‑5
+**(3)** ：signal_handler()是信号处理函数，它传入一个int类型的信号值，在信号传递进来的时候就将对应的信号值打印出来，在此例中我们可以看到，信号处理函数使用了一个单独的整数参数，它就是引起该函数被调用的信号值。如果需要在同一个函数中处理多个信号，这个参数就很有用。
 
-代码清单 38‑5\ **(4)**\ ：如果信号是SIGINT，则打印对应的信息，并且调用signal()函数将SIGINT信号的处理恢复默认的处理（SIG_DFL），在下一次接收到SIGINT信号的时候就不会进入这个函数里了。
+代码清单38‑5
+**(4)** ：如果信号是SIGINT，则打印对应的信息，并且调用signal()函数将SIGINT信号的处理恢复默认的处理（SIG_DFL），在下一次接收到SIGINT信号的时候就不会进入这个函数里了。
 
-我们进入application/signal目录下，该目录存在代码清单 38‑5所示的实验代码，还有对应的Makefile文件，我们只需使用“make”命令编译生成“targets”可执行文件，并且运行即可，在运行过程中会不断打印出“waiting for the SIGINT signal ,
-please enter "ctrl + c"...”，当我们按下“ctrl + c”时，进入signal_handler()信号处理函数，打印对应的信息，并且将SIGINT信号的处理恢复默认，因此当下一次按下“ctrl + c”时进程将直接退出，该实验代码的现象具体见图 38‑6。
+我们进入 ``system_programing/signal`` 目录下，该目录存在代码清单38‑5所示的实验代码，还有对应的Makefile文件，我们只需使用"make"命令编译生成"targets"可执行文件，并且运行即可，在运行过程中会不断打印出"waiting
+for the SIGINT signal , please enter "ctrl + c"..."，当我们按下"ctrl +
+c"时，进入signal_handler()信号处理函数，打印对应的信息，并且将SIGINT信号的处理恢复默认，因此当下一次按下"ctrl
++ c"时进程将直接退出，该实验代码的现象具体见图 38‑6。
 
-|signal007|
+.. figure:: media/signal007.png
+   :alt: signal007
 
+   signal007
 图 38‑6 signal()函数实验现象
 
 sigaction()
-^^^^^^^^^^^
+~~~~~~~~~~~
 
-其实，我们不推荐读者使用signal()函数接口，之所以会在上一小节介绍它，是因为读者可能会在许多老程序中看到它的应用。稍后我们会介绍一个定义更清晰、执行更可靠的sigaction()函数，这个函数的功能与signal()函数是一样的，但是API接口稍微有点不同，作者建议，以后在所有的程序中都应该使
-用这个函数去操作信号。
+其实，我们不推荐读者使用signal()函数接口，之所以会在上一小节介绍它，是因为读者可能会在许多老程序中看到它的应用。稍后我们会介绍一个定义更清晰、执行更可靠的sigaction()函数，这个函数的功能与signal()函数是一样的，但是API接口稍微有点不同，作者建议，以后在所有的程序中都应该使用这个函数去操作信号。
 
 我们使用man命令来查看一下sigaction()函数的相关信息：
 
-命令
+**命令**
 
-man 2 sigaction
+.. code:: bash
 
-头文件
+    man 2 sigaction
 
-#include <signal.h>
+**头文件**
 
-函数原型
+.. code:: c
+
+    #include <signal.h>
+
+**函数原型**
+
+.. code:: c
 
-int sigaction(int signum, const struct sigaction \*act, struct sigaction \*oldact);
+    int sigaction(int signum, const struct sigaction *act, struct sigaction *oldact);
 
 这个函数的参数比signal()函数多了一些，下面就介绍一下这些参数的区别：
 
 -  signum：指定捕获的信号值。
-
 -  act：是一个结构体，该结构体的内容如下：
 
-struct sigaction { void (*sa_handler)(int); void (*sa_sigaction)(int, siginfo_t \*, void \*); sigset_t sa_mask; int sa_flags; void
-(*sa_restorer)(void); };
+.. code:: c
+
+      struct sigaction {
+                   void     (*sa_handler)(int);
+                   void     (*sa_sigaction)(int, siginfo_t *, void *);
+                   sigset_t   sa_mask;
+                   int        sa_flags;
+                   void     (*sa_restorer)(void);
+               };
 
 sa_handler是一个函数指针，是捕获信号后的处理函数，它也有一个int类型的参数，传入信号的值，这个函数是标准的信号处理函数。
 
-sa_sigaction则是扩展信号处理函数，它也是一个函数指针，但它比标准信号处理函数复杂的多，事实上如果选择扩展接口的话，信号的接收进程不仅可以接收到 int 型的信号值，还会接收到一个 siginfo_t类 型的结构体指针，还有一个 void
-型的指针，还有需要注意的就是，不要同时使用sa_handler和sa_sigaction，因为这两个处理函数是有联合的部分（联合体）。关于siginfo_t类 型的结构体我们在后续讲解。
+sa_sigaction则是扩展信号处理函数，它也是一个函数指针，但它比标准信号处理函数复杂的多，事实上如果选择扩展接口的话，信号的接收进程不仅可以接收到int
+型的信号值，还会接收到一个 siginfo_t类
+型的结构体指针，还有一个void类型的指针，还有需要注意的就是，不要同时使用sa_handler和sa_sigaction，因为这两个处理函数是有联合的部分（联合体）。关于siginfo_t类型的结构体我们在后续讲解。
 
-sa_mask 是信号掩码，它指定了在执行信号处理函数期间阻塞的信号的掩码，被设置在该掩码中的信号，在进程响应信号期间被临时阻塞。除非使用SA_NODEFER标志，否则即使是当前正在处理的响应的信号再次到来的时候也会被阻塞。
+sa_mask是信号掩码，它指定了在执行信号处理函数期间阻塞的信号的掩码，被设置在该掩码中的信号，在进程响应信号期间被临时阻塞。除非使用SA_NODEFER标志，否则即使是当前正在处理的响应的信号再次到来的时候也会被阻塞。
 
 re_restorer则是一个已经废弃的成员变量，不要使用。
 
@@ -659,251 +630,171 @@ oldact：返回原有的信号处理参数，一般设置为NULL即可。
 
 sa_flags是指定一系列用于修改信号处理过程行为的标志，由下面的0个或多个标志组合而成：
 
--  SA_NOCLDSTOP：如果signum是SIGCHLD，则在子进程停止或恢复时，不会传信号给调用sigaction()函数的进程。即当它们接收到SIGSTOP、SIGTSTP、SIGTTIN或SIGTTOU（停止）中的一种时或接收到SIGCONT（恢复）时，父进程不会收到通知。仅当为SIGCH
-  LD建立处理程序时，此标志才有意义
-
--  SA_NOCLDWAIT：从Linux 2.6开始就存在这个标志了，它表示父进程在它的子进程终止时不会收到 SIGCHLD 信号，这时子进程终止则不会成为僵尸进程。
+-  SA_NOCLDSTOP：如果signum是SIGCHLD，则在子进程停止或恢复时，不会传信号给调用sigaction()函数的进程。即当它们接收到SIGSTOP、SIGTSTP、SIGTTIN或SIGTTOU（停止）中的一种时或接收到SIGCONT（恢复）时，父进程不会收到通知。仅当为SIGCHLD建立处理程序时，此标志才有意义
 
+-  SA_NOCLDWAIT：从Linux
+   2.6开始就存在这个标志了，它表示父进程在它的子进程终止时不会收到
+   SIGCHLD 信号，这时子进程终止则不会成为僵尸进程。
 -  SA_NODEFER：不要阻止从其自身的信号处理程序中接收信号，使进程对信号的屏蔽无效，即在信号处理函数执行期间仍能接收这个信号，仅当建立信号处理程序时，此标志才有意义。
-
 -  SA_RESETHAND：信号处理之后重新设置为默认的处理方式。
-
--  SA_SIGINFO：从Linux 2.2开始就存在这个标志了，使用 sa_sigaction 成员而不是使用sa_handler 成员作为信号处理函数。
+-  SA_SIGINFO：从Linux 2.2开始就存在这个标志了，使用
+   sa_sigaction成员而不是使用sa_handler 成员作为信号处理函数。
 
 当在asa_flags中指定SA_SIGINFO标志时，信号处理程序地址将通过sa_sigaction字段传递。该处理程序采用三个参数，如下所示：
 
-void handler(int sig, siginfo_t \*info, void \*ucontext)
+.. code:: c
 
-{
+    void handler(int sig, siginfo_t *info, void *ucontext)
+    {
 
-...
+        ...
 
-}
+    }
 
 info指向siginfo_t的指针，它是一个包含有关信号的更多信息的结构，具体成员变量如下所示：
 
-siginfo_t {
-
-int si_signo; /\* 信号数值 \*/
-
-int si_errno; /\* 错误值 \*/
-
-int si_code; /\* 信号代码 \*/
-
-int si_trapno; /*导致硬件生成信号的陷阱号，在大多数体系结构中未使用*/
-
-pid_t si_pid; /\* 发送信号的进程ID \*/
-
-uid_t si_uid; /*发送信号的真实用户ID \*/
-
-int si_status; /\* 退出值或信号状态*/
-
-clock_t si_utime; /*消耗的用户时间*/
-
-clock_t si_stime; /*消耗的系统时间*/
-
-sigval_t si_value; /*信号值*/
-
-int si_int; /\* POSIX.1b 信号*/
-
-void \*si_ptr;
-
-int si_overrun; /*计时器溢出计数*/
-
-int si_timerid; /\* 计时器ID \*/
-
-void \*si_addr; /*导致故障的内存位置 \*/
-
-long si_band;
-
-int si_fd; /\* 文件描述符*/
-
-short si_addr_lsb; /*地址的最低有效位 (从Linux 2.6.32开始存在) \*/
-
-void \*si_lower; /*地址冲突时的下限*/
-
-void \*si_upper; /*地址冲突时的上限 (从Linux 3.19开始存在) \*/
-
-int si_pkey; /*导致的PTE上的保护密钥*/
-
-void \*si_call_addr; /*系统调用指令的地址*/
-
-int si_syscall; /*尝试的系统调用次数*/
-
-unsigned int si_arch; /\* 尝试的系统调用的体系结构*/
-
-}
+.. code:: c
+
+    siginfo_t {
+                   int      si_signo;     /* 信号数值 */
+                   int      si_errno;     /* 错误值 */
+                   int      si_code;      /* 信号代码 */
+                   int      si_trapno;   /*导致硬件生成信号的陷阱号，在大多数体系结构中未使用*/
+                   pid_t    si_pid;       /* 发送信号的进程ID */
+                   uid_t    si_uid;       /*发送信号的真实用户ID */
+                   int      si_status;    /* 退出值或信号状态*/
+                   clock_t  si_utime;     /*消耗的用户时间*/
+                   clock_t  si_stime;     /*消耗的系统时间*/
+                   sigval_t si_value;     /*信号值*/
+                   int      si_int;       /* POSIX.1b 信号*/
+                   void    *si_ptr;      
+                   int      si_overrun;   /*计时器溢出计数*/
+                   int      si_timerid;   /* 计时器ID */
+                   void    *si_addr;      /*导致故障的内存位置 */
+                   long     si_band;     
+                   int      si_fd;        /* 文件描述符*/
+                   short    si_addr_lsb;  /*地址的最低有效位 (从Linux 2.6.32开始存在) */
+                   void    *si_lower;     /*地址冲突时的下限*/
+                   void    *si_upper;     /*地址冲突时的上限 (从Linux 3.19开始存在) */
+                   int      si_pkey;      /*导致的PTE上的保护密钥*/
+                   void    *si_call_addr; /*系统调用指令的地址*/
+                   int      si_syscall;   /*尝试的系统调用次数*/
+                   unsigned int si_arch;  /* 尝试的系统调用的体系结构*/
+               }
 
 上面的成员变量绝大部分我们是几乎使用不到的，因为我们如果是对信号的简单处理，直接使用sa_handler处理即可，根本无需配置siginfo_t这些比较麻烦的信息。
 
-我们可以进入application/sigaction目录下，里面有一个sigaction.c文件与Makefile文件，sigaction.c就是我们的实验代码，具体见代码清单 38‑6。
+我们可以进入 ``system_programing/sigaction`` 目录下，里面有一个sigaction.c文件与Makefile文件，sigaction.c就是我们的实验代码，具体见代码清单38‑6。
 
 代码清单 38‑6 sigaction.c文件内容
 
-1 #include <unistd.h>
-
-2 #include <stdio.h>
-
-3 #include <stdlib.h>
-
-4 #include <signal.h>
-
-5 #include <sys/types.h>
-
-6 #include <sys/wait.h>
-
-7
-
-8
-
-9 /*\* 信号处理函数 \*/
-
-10 void signal_handler(int sig) **(1)**
-
-11 {
-
-12 printf("\nthis signal numble is %d \\n",sig);
-
-13
-
-14 if (sig == SIGINT) {
-
-15 printf("I have get SIGINT!\n\n");
-
-16 printf("The signal is automatically
+.. code:: c
 
-17 restored to the default handler!\n\n");
+    #include <unistd.h>
+    #include <stdio.h>
+    #include <stdlib.h>
+    #include <signal.h>
+    #include <sys/types.h>
+    #include <sys/wait.h>
 
-18 /*\* 信号自动恢复为默认处理函数 \*/
+    /** 信号处理函数 */
+    void signal_handler(int sig)                    //(1)
+    {
+        printf("\nthis signal numble is %d \n",sig);
 
-19 }
+        if (sig == SIGINT) {
+            printf("I have get SIGINT!\n\n");
+            printf("The signal is automatically restored to the default handler!\n\n");
+            /** 信号自动恢复为默认处理函数 */
+        }
 
-20
+    }
 
-21 }
+    int main(void)
+    {
+        struct sigaction act;
 
-22
+        printf("this is sigaction function test demo!\n\n");
 
-23 int main(void)
+        /** 设置信号处理的回调函数 */
+        act.sa_handler = signal_handler;            //(2)
+        
+        /* 清空屏蔽信号集 */
+        sigemptyset(&act.sa_mask);                  //(3)
 
-24 {
+        /** 在处理完信号后恢复默认信号处理 */
+        act.sa_flags = SA_RESETHAND;                //(4)
 
-25 struct sigaction act;
+        sigaction(SIGINT, &act, NULL);              //(5)
 
-26
+        while (1)
+        {
+            printf("waiting for the SIGINT signal , please enter \"ctrl + c\"...\n\n");
+            sleep(1);
+        }
+        
+        exit(0);
+    }
 
-27 printf("this is sigaction function test demo!\n\n");
+代码清单38‑6
+**(1)** ：信号处理函数signal_handler()与signal实验的信号处理函数几乎是一样的，但是这里并没有在函数中让信号恢复默认处理，这是因为设置了sa_flags成员变量，在处理完信号后自动恢复默认的处理。
 
-28
+代码清单38‑6
+**(2)** ：设置信号处理的回调函数，在这个实验使用sa_handler作为信号处理成员变量而不是sa_sigaction。
 
-29 /*\* 设置信号处理的回调函数 \*/
+代码清单38‑6
+**(3)** ：调用sigemptyset()函数清空进程屏蔽的信号集，即在信号处理的时候不会屏蔽任何信号。
 
-30 act.sa_handler = signal_handler; **(2)**
+代码清单38‑6
+**(4)** ：设置sa_flags成员变量为SA_RESETHAND，在处理完信号后恢复默认信号处理。
 
-31
+代码清单 38‑6 **(5)** ：调用sigaction()函数捕获SIGINT信号。
 
-32 /\* 清空屏蔽信号集 \*/
+进入system_programing/sigaction目录下，直接使用make命令编译代码，然后运行生成的targets可执行文件，根据终端输出的提示按下两次"ctrl
++ c"，就可以看到如图 38‑7所示的实验现象。
 
-33 sigemptyset(&act.sa_mask); **(3)**
-
-34
-
-35 /*\* 在处理完信号后恢复默认信号处理 \*/
-
-36 act.sa_flags = SA_RESETHAND; **(4)**
-
-37
-
-38 sigaction(SIGINT, &act, NULL); **(5)**
-
-39
-
-40 while (1) {
-
-41 printf("waiting for the SIGINT signal ,
-
-42 please enter \\"ctrl + c\"...\n\n");
-
-43 sleep(1);
-
-44 }
-
-45
-
-46 exit(0);
-
-47 }
-
-48
-
-代码清单 38‑6\ **(1)**\ ：信号处理函数signal_handler()与signal实验的信号处理函数几乎是一样的，但是这里并没有在函数中让信号恢复默认处理，这是因为设置了sa_flags成员变量，在处理完信号后自动恢复默认的处理。
-
-代码清单 38‑6\ **(2)**\ ：设置信号处理的回调函数，在这个实验使用sa_handler作为信号处理成员变量而不是sa_sigaction。
-
-代码清单 38‑6\ **(3)**\ ：调用sigemptyset()函数清空进程屏蔽的信号集，即在信号处理的时候不会屏蔽任何信号。
-
-代码清单 38‑6\ **(4)**\ ：设置sa_flags成员变量为SA_RESETHAND，在处理完信号后恢复默认信号处理。
-
-代码清单 38‑6\ **(5)**\ ：调用sigaction()函数捕获SIGINT信号。
-
-进入application/sigaction目录下，直接使用make命令编译代码，然后运行生成的targets可执行文件，根据终端输出的提示按下两次“ctrl + c”，就可以看到如图 38‑7所示的实验现象。
-
-|signal008|
+.. figure:: media/signal008.png
+   :alt: signal008
 
+   signal008
 图 38‑7 sigaction实验现象
 
-实验解说：第一次按下“ctrl + c”时产生SIGINT信号，被sigaction()函数捕获，并且进入信号处理函数signal_handler()，打印对应的信息“I have get SIGINT!”，在处理完毕后恢复SIGINT信号的默认处理（即终止进程），在第二次按下“ctrl +
-c”时，就会直接终止进程而不会有任何输出。
+实验解说：第一次按下"ctrl +
+c"时产生SIGINT信号，被sigaction()函数捕获，并且进入信号处理函数signal_handler()，打印对应的信息"I
+have get
+SIGINT!"，在处理完毕后恢复SIGINT信号的默认处理（即终止进程），在第二次按下"ctrl
++ c"时，就会直接终止进程而不会有任何输出。
 
 信号集
-~~~
+------
 
-在linux系统中有一个能表示多个信号集合的数据类型sigset_t——信号集（signal set），它在头文件signal.h中被定义，此外还定义了用来处理信号集的函数。这些函数中使用信号集这个数据类型，以告诉内核不允许发生该信号集中的信号。正如上一节所述的信号掩码就是这种数据类型，不过由于信号
-种类数目可能超过一个整型变量所包含的位数，所以一般而言，不能用整型量中的一位代表一种信号，所以POSIX.1定义数据类型sigset_t以包含一个信号集，并且定义了下列五个处理信号集的函数，以修改进程在接收到信号时的行为：
+在Linux系统中有一个能表示多个信号集合的数据类型sigset_t——信号集（signalset），它在头文件signal.h中被定义，此外还定义了用来处理信号集的函数。这些函数中使用信号集这个数据类型，以告诉内核不允许发生该信号集中的信号。正如上一节所述的信号掩码就是这种数据类型，不过由于信号种类数目可能超过一个整型变量所包含的位数，所以一般而言，不能用整型量中的一位代表一种信号，所以POSIX.1定义数据类型sigset_t以包含一个信号集，并且定义了下列五个处理信号集的函数，以修改进程在接收到信号时的行为：
 
-头文件
+**头文件**
 
-#include <signal.h>
+.. code:: c
+
+    #include <signal.h>
 
 函数原型
 
-int sigemptyset(sigset_t \*set);
+.. code:: c
 
-int sigfillset(sigset_t \*set);
+    int sigemptyset(sigset_t *set);
 
-int sigaddset(sigset_t \*set, int signum);
+    int sigfillset(sigset_t *set);
 
-int sigdelset(sigset_t \*set, int signum);
+    int sigaddset(sigset_t *set, int signum);
 
-int sigismember(const sigset_t \*set, int signum);
+    int sigdelset(sigset_t *set, int signum);
 
-见名知义，这些函数执行的操作如它们的名字一样， sigemptyset()函数是将信号集初始化为空，使进程不会屏蔽任何信号； sigfillset()函数将信号集初始化为包含所有已定义的信号，刚好与igemptyset()函数是相对立的。
+    int sigismember(const sigset_t *set, int signum);
 
-所有应用程序在使用信号集前，要对该信号集调用sigemptyset()函数或sigfillset()函数将信号初始化一次，这是因为 C编译器会将不赋初值的外部和静态度量都初始化为 0，而这是否与给定系统上信号集的实现相对应并不清楚。
+见名知义，这些函数执行的操作如它们的名字一样，sigemptyset()函数是将信号集初始化为空，使进程不会屏蔽任何信号；sigfillset()函数将信号集初始化为包含所有已定义的信号，刚好与igemptyset()函数是相对立的。
 
-一旦已经初始化了一个信号集，以后就可在该信号集中增、删特定的信号。sigaddset()函数会将一个信号添加到现有的信号集中，sigdelset()函数则是从现有的信号集中删除一个信号。在两个函数在操作信号集成功时返回0，失败时返回-1并设置errno。不过只有一个错误代码被定义了，即当给定的信号无
-效时， errno将设置为EINVAL。
+所有应用程序在使用信号集前，要对该信号集调用sigemptyset()函数或sigfillset()函数将信号初始化一次，这是因为C编译器会将不赋初值的外部和静态度量都初始化为0，而这是否与给定系统上信号集的实现相对应并不清楚。
 
-函数sigismember()用于判断一个给定的信号是否是一个信号集的成员。如果是就返回1；如果不是，它就返回0；如果给定的信号无效，它就返回-1并设置errno为EINVAL。
+一旦已经初始化了一个信号集，以后就可在该信号集中增、删特定的信号。sigaddset()函数会将一个信号添加到现有的信号集中，sigdelset()函数则是从现有的信号集中删除一个信号。在两个函数在操作信号集成功时返回0，失败时返回-1并设置errno。不过只有一个错误代码被定义了，即当给定的信号无效时，
+errno将设置为EINVAL。
 
-.. |signal002| image:: media/signal002.png
-   :width: 5.76371in
-   :height: 3.10448in
-.. |signal003| image:: media/signal003.png
-   :width: 5.11194in
-   :height: 2.55597in
-.. |signal004| image:: media/signal004.png
-   :width: 5.76806in
-   :height: 2.22154in
-.. |signal005| image:: media/signal005.png
-   :width: 5.76806in
-   :height: 2.73527in
-.. |signal006| image:: media/signal006.png
-   :width: 5.76806in
-   :height: 3.1817in
-.. |signal007| image:: media/signal007.png
-   :width: 5.76806in
-   :height: 3.33175in
-.. |signal008| image:: media/signal008.png
-   :width: 5.76806in
-   :height: 3.27263in
+函数sigismember()用于判断一个给定的信号是否是一个信号集的成员。如果是就返回1；如果不是，它就返回0；如果给定的信号无效，它就返回-1并设置errno为EINVAL。
diff --git a/documentation/system_programing/socket.rst b/documentation/system_programing/socket.rst
new file mode 100644
index 0000000000000000000000000000000000000000..f6a5c4870dd40380a07c6629f8330c368e79240b
--- /dev/null
+++ b/documentation/system_programing/socket.rst
@@ -0,0 +1,679 @@
+套接字
+======
+
+不知道大家还记不记得我在消息队列章节中提到的一段话：
+
+    Linux下的进程通信手段基本上是从Unix平台上的进程通信手段继承而来的。而对Unix发展做出重大贡献的两大主力AT&T的贝尔实验室及BSD（加州大学伯克利分校的伯克利软件发布中心）在进程间通信方面的侧重点有所不同；前者对Unix早期的进程间通信手段进行了系统的改进和扩充，形成了"system
+    V
+    IPC"，通信进程局限在单个计算机内（同一个设备的不同进程间通讯）；而后者则跳过了该限制，形成了基于套接字（Socket）的进程间通信机制（多用于不同设备的进程间通讯）。Linux则把两者继承了下来，所以说Linux才是最成功的，既有"system
+    V IPC"，又支持Socket。
+
+那么很显然，我们前面的文章讲解了单个计算机内的进程间通信，所有的机制都依靠一台计算机系统的共享资源实现，这里的资源可以是文件系统空间、共享的物理内存或消息队列，但只有运行在同一台机器上的进程才能使用它们，很显然这种方式并不满足我们想要的，我们可能会想让这个设备与另一个设备进行通讯，我接下来就要讲解用于不同设备的进程间通讯——基于套接字（Socket）的进程间通信机制，当然Socket也能支持在一个设备上的进程间通信，而不仅仅只是不同设备之间的。
+
+在上一节我们也简单了解了网络中的UDP与TCP协议，那么我们今天就是通过套接字进行通讯。
+
+Socket简介
+----------
+
+套接字（socket）是一种通信机制，凭借这种机制， ``客户端<->服务器``
+模型的通信方式既可以在本地设备上进行，也可以跨网络进行。套接字的创建和使用与管道是有区别的，因为套接字明确地将客户端、服务器区分开来，而且套接字机制可以实现将多个客户连接到一个服务器。
+
+Socket英文原意是"孔"或者"插座"的意思，在网络编程中，通常将其称之为"套接字"，当前网络中的主流程序设计都是使用Socket进行编程的，因为它简单易用，它还是一个标准（BSD
+Socket），能在不同平台很方便移植，比如你的一个应用程序是基于Socket编程的，那么它可以移植到任何实现BSD
+Socket标准的平台，比如LwIP，它兼容BSD
+Socket；又比如Windows，它也实现了一套基于Socket的套接字接口，更甚至在国产操作系统中，如RT-Thread，它也实现了BSD
+Socket标准的Socket接口。
+
+在Socket中，它使用一个套接字来记录网络的一个连接，套接字是一个整数，就像我们操作文件一样，利用一个文件描述符，可以对它打开、读、写、关闭等操作，类似的，在网络中，我们也可以对Socket套接字进行这样子的操作，比如开启一个网络的连接、读取连接主机发送来的数据、向连接的主机发送数据、终止连接等操作。
+
+我们来了解一下套接字描述符，它跟我们的文件描述符非常像，其实就是一个整数，套接字API最初是作为UNIX操作系统的一部分而开发的，所以套接字API与系统的其他I/O设备集成在一起。当应用程序要为网络通信而创建一个套接字（socket）时，操作系统就返回一个整数作为描述符（descriptor）来标识这个套接字。然后，应用程序以该描述符作为传递参数，通过调用Socket
+API接口的函数来完成某种操作（例如通过网络传送数据或接收输入的数据）。
+
+接下来讲解Linux系统中的套接字相关的函数，但注意要包含网络编程中常用的头文件：
+
+.. code:: c
+
+        #include <sys/types.h>
+        #include <sys/socket.h>
+
+socket()
+--------
+
+函数原型：
+
+.. code:: c
+
+        int socket(int domain, int type, int protocol);
+
+socket()函数用于创建一个socket描述符（socket
+descriptor），它唯一标识一个socket，这个socket描述字跟文件描述字一样，后续的操作都有用到它，把它作为参数，通过它来进行一些读写操作。
+
+创建socket的时候，也可以指定不同的参数创建不同的socket描述符，socket函数的三个参数分别为：
+1.
+domain：参数domain表示该套接字使用的协议族，在Linux系统中支持多种协议族，对于TCP/IP协议来说，选择AF_INET就足以，当然如果你的IP协议的版本支持IPv6，那么可以选择AF_INET6，可选的协议族具体见：
+
+-  AF_UNIX, AF_LOCAL： 本地通信
+-  AF_INET ： IPv4
+-  AF_INET6 ： IPv6
+-  AF_IPX ： IPX - Novell 协议
+-  AF_NETLINK ： 内核用户界面设备
+-  AF_X25 ： ITU-T X.25 / ISO-8208 协议
+-  AF_AX25 ： 业余无线电 AX.25 协议
+-  AF_ATMPVC ： 访问原始ATM PVC
+-  AF_APPLETALK ： AppleTalk
+-  AF_PACKET ： 底层数据包接口
+-  AF_ALG ： 内核加密API的AF_ALG接口
+
+    ps：其实我个人都只用过AF_INET以及AF_NETLINK，对于其他协议族，基本没用过。
+
+1. type：参数type指定了套接字使用的服务类型，可能的类型有以下几种：
+
+-  SOCK_STREAM：提供可靠的（即能保证数据正确传送到对方）面向连接的Socket服务，多用于资料（如文件）传输，如TCP协议。
+-  SOCK_DGRAM：是提供无保障的面向消息的Socket
+   服务，主要用于在网络上发广播信息，如UDP协议，提供无连接不可靠的数据报交付服务。
+-  SOCK_SEQPACKET：为固定最大长度的数据报提供有序的，可靠的，基于双向连接的数据传输路径。
+-  SOCK_RAW：表示原始套接字，它允许应用程序访问网络层的原始数据包，这个套接字用得比较少，暂时不用理会它。
+-  SOCK_RDM：提供不保证排序的可靠数据报层。
+
+2. protocol：参数protocol指定了套接字使用的协议，在IPv4中，只有TCP协议提供SOCK_STREAM这种可靠的服务，只有UDP协议提供SOCK_DGRAM服务，对于这两种协议，protocol的值均为0，因为当protocol为0时，会自动选择type类型对应的默认协议。。
+
+当创建套接字成功的时候，该函数返回一个int类型的值，也就是socket描述符，该值大于等于0；而如果创建套接字失败时则返回-1。
+
+bind()
+------
+
+函数原型：
+
+.. code:: c
+
+        int bind(int sockfd, struct sockaddr *my_addr, socklen_t addrlen);
+
+在套接口中，一个套接字只是用户程序与内核交互信息的枢纽，它自身没有太多的信息，也没有网络协议地址和端口号等信息，在进行网络通信的时候，必须把一个套接字与一个IP地址或端口号相关联，这个过程就是绑定的过程。
+
+bind()函数用于将一个 IP
+地址或端口号与一个套接字进行绑定，许多时候内核会帮我们自动绑定一个IP地址与端口号，然而有时用户可能需要自己来完成这个绑定的过程，以满足实际应用的需要，最典型的情况是一个服务器进程需要绑定一个众所周知的地址和端口以等待客户来连接，作为服务器端，这一步绑定的操作是必要的，而作为客户端，则不是必要的，因为内核会帮我们自动选择合适的IP地址与端口号。
+
+    ps：bind()函数并不是总是需要调用的，只有用户进程想与一个具体的地址或端口相关联的时候才需要调用这个函数。如果用户进程没有这个需要，那么程序可以依赖内核的自动的选址机制来完成自动地址选择。
+
+参数：
+
+-  sockfd：sockfd是由socket()函数返回的套接字描述符。
+-  my_addr：my_addr是一个指向套接字地址结构的指针。
+-  addrlen：addrlen指定了以addr所指向的地址结构体的字节长度。
+
+若bind()函数绑定成功则返回0，若出错则为-1。
+
+sockaddr 结构内容如下：
+
+sockaddr结构：
+
+.. code:: c
+
+    struct sockaddr {
+        sa_family_t     sa_family;
+        char            sa_data[14];
+    }
+
+咋一看这个结构体，好像没啥信息要我们填写的，确实也是这样子，我们需要填写的IP地址与端口号等信息，都在sa_data连续的14字节信息里面，但这个结构对用户操作不友好，一般我们在使用的时候都会使用sockaddr_in结构，sockaddr_in和sockaddr是并列的结构（占用的空间是一样的），指向sockaddr_in的结构体的指针也可以指向sockadd的结构体，并代替它，而且sockaddr_in结构对用户将更加友好，在使用的时候进行类型转换就可以了。
+
+sockaddr_in结构：
+
+.. code:: c
+
+    struct sockaddr_in {
+        short int sin_family;               /* 协议族 */
+        unsigned short int sin_port;        /* 端口号 */
+        struct in_addr sin_addr;            /* IP地址 */
+        unsigned char sin_zero[8];          /* sin_zero是为了让sockaddr与sockaddr_in两个数据结构保持大小相同而保留的空字节 */
+    };
+
+这个结构体的第一个字段是与sockaddr结构体是一致的，而剩下的字段就是sa_data连续的14字节信息里面的内容，只不过从新定义了成员变量而已，sin_port字段是我们需要填写的端口号信息，sin_addr字段是我们需要填写的IP地址信息，剩下sin_zero
+区域的8字节保留未用。
+
+举个简单的使用实例：
+
+.. code:: c
+
+        struct sockaddr_in server;
+
+        bzero(&server, sizeof(server));
+
+        // assign IP, PORT
+        server.sin_family = AF_INET;
+        server.sin_addr.s_addr = htonl(INADDR_ANY);
+        server.sin_port = htons(6666);
+
+        // binding newly created socket to given IP and verification
+        bind(sockfd, (struct sockaddr*)&server, sizeof(server));
+
+connect()
+---------
+
+函数原型：
+
+.. code:: c
+
+        int connect(int sockfd, const struct sockaddr *addr, socklen_t addrlen);
+
+这个connect()函数用于客户端中，将sockfd与远端IP地址、端口号进行绑定，在TCP客户端中调用这个函数将发生握手过程（会发送一个TCP连接请求），并最终建立一个TCP连接，而对于UDP协议来说，调用这个函数只是在sockfd中记录远端IP地址与端口号，而不发送任何数据，参数信息与bind()函数是一样的。
+
+函数调用成功则返回0，失败返回-1，错误原因存于errno中。
+
+connect()函数是套接字连接操作，对于TCP协议来说，connect()函数操作成功之后代表对应的套接字已与远端主机建立了连接，可以发送与接收数据。
+
+对于UDP协议来说，没有连接的概念，在这里我就将其描述为记录远端主机的IP地址与端口好，UDP协议经过connect()函数调用成功之后，在通过sendto()函数发送数据报时不需要指定目的地址、端口，因为此时已经记录到了远端主机的IP地址与端口号。UDP协议还可以给同一个套接字进行多次connect()操作，而TCP协议不可以，TCP只能指定一次connect操作。
+
+listen()
+--------
+
+listen()函数只能在TCP服务器进程中使用，让服务器进程进入监听状态，等待客户端的连接请求，listen()函数在一般在bind()函数之后调用，在accept()函数之前调用，它的函数原型是：
+
+.. code:: c
+
+        int listen(int s, int backlog);
+
+参数：
+
+-  sockfd：sockfd是由socket()函数返回的套接字描述符。
+-  backlog参数用来描述sockfd的等待连接队列能够达到的最大值。在服务器进程正处理客户端连接请求的时候，可能还存在其它的客户端请求建立连接，因为TCP连接是一个过程，由于同时尝试连接的用户过多，使得服务器进程无法快速地完成所有的连接请求，那怎么办呢？直接丢掉其他客户端的连接肯定不是一个很好的解决方法。因此内核会在自己的进程空间里维护一个队列，这些连接请求就会被放入一个队列中，服务器进程会按照先来后到的顺序去处理这些连接请求，这样的一个队列内核不可能让其任意大，所以必须有一个大小的上限，这个backlog告诉内核使用这个数值作为队列的上限。而当一个客户端的连接请求到达并且该队列为满时，客户端可能会收到一个表示连接失败的错误，本次请求会被丢弃不作处理。
+
+accept()函数
+------------
+
+函数原型：
+
+.. code:: c
+
+        int accept(int s, struct sockaddr *addr, socklen_t *addrlen);
+
+为了能够正常让TCP客户端能正常连接到服务器，服务器必须遵循以下流程处理：
+
+1. 调用socket()函数创建对应的套接字类型。
+
+2. 调用bind()函数将套接字绑定到本地的一个端口地址。
+
+3. 调用listen()函数让服务器进程进入监听状态，等待客户端的连接请求。
+
+4. 调用accept()函数处理到来的连接请求。
+
+accept()函数用于TCP服务器中，等待着远端主机的连接请求，并且建立一个新的TCP连接，在调用这个函数之前需要通过调用listen()函数让服务器进入监听状态，如果队列中没有未完成连接套接字，并且套接字没有标记为非阻塞模式，accept()函数的调用会阻塞应用程序直至与远程主机建立TCP连接；如果一个套接字被标记为非阻塞式而队列中没有未完成连接套接字,
+调用accept()函数将立即返回EAGAIN。
+
+所以，accept()函数就是用于处理连接请求的，它会从未完成连接队列中取出第一个连接请求，建一个和参数
+s 属性相同的连接套接字，并为这个套接字分配一个文件描述符,
+然后以这个描述符返回，新创建的描述符不再处于监听状态，原套接字 s
+不受此调用的影响，还是会处于监听状态，因为 s
+是由socket()函数创建的，而处理连接时accept()函数会创建另一个套接字。
+
+参数addr用来返回已连接的客户端的IP地址与端口号，参数addrlen用于返回addr所指向的地址结构体的字节长度，如果我们对客户端的IP地址与端口号不感兴趣，可以把arrd和addrlen均置为空指针。
+
+若连接成功则返回一个socket描述符（非负值），若出错则为-1。
+
+    ps:
+    如果accept()连接成功，那么其返回值是由内核自动生成的一个全新描述符，代表与客户端的TCP连接，一个服务器通常仅仅创建一个监听套接字，它在该服务器生命周期内一直存在，内核为每个由服务器进程接受的客户端连接创建一个已连接套接字。
+
+read()
+------
+
+一旦客户端与服务器建立好TCP连接之后，我们就可以通过sockfd套接字描述符来收发数据，这与我们读写文件是差不多的操作，接收网络中的数据函数可以是read()、recv()、recvfrom()等。
+
+函数原型：
+
+.. code:: c
+
+        ssize_t read(int fd, void *buf, size_t count);
+
+        ssize_t recv(int sockfd, void *buf, size_t len, int flags);
+
+        ssize_t recvfrom(int sockfd, void *buf, size_t len, int flags,
+                        struct sockaddr *src_addr, socklen_t *addrlen);
+
+    ps：ssize_t 它表示的是 signed size_t 类型。
+
+read() 从描述符 fd
+（描述符可以是文件描述符也可以是套接字描述符，本章主要讲解套接字，此处为套接字描述符）中读取
+count 字节的数据并放入从 buf
+开始的缓冲区中，read()函数调用成功返回读取到的字节数，此返回值受文件剩余字节数限制，当返回值小于指定的字节数时
+并不意味着错误；这可能是因为当前可读取的字节数小于指定的
+字节数（比如已经接近文件结尾，或者正在从管道或者终端读取数据，或者read()函数被信号中断等），出错返回-1并设置errno，如果在调read之前已到达文件末尾，则这次read返回0。
+
+参数： - fd：在socket编程中是指定套接字描述符。 -
+buf：指定存放数据的地址。 -
+count：是指定读取的字节数，将读取到的数据保存在缓冲区buf中。
+
+错误代码： - EINTR：在读取到数据前被信号所中断。 - EAGAIN：使用
+O_NONBLOCK 标志指定了非阻塞式输入输出，但当前没有数据可读。 -
+EIO：输入输出错误，可能是正处于后台进程组进程试图读取其控制终端，但读操作无效，或者被信号SIGTTIN所阻塞,
+或者其进程组是孤儿进程组，也可能执行的是读磁盘或者磁带机这样的底层输入输出错误。
+- EISDIR：fd 指向一个目录。 - EBADF：fd
+不是一个合法的套接字描述符，或者不是为读操作而打开。 - EINVAL：fd
+所连接的对象不可读。 - EFAULT：buf 超出用户可访问的地址空间。
+
+recv()
+------
+
+函数原型：
+
+.. code:: c
+
+        ssize_t recv(int sockfd, void *buf, size_t len, int flags);
+
+不论是客户还是服务器应用程序都可以用recv()函数从TCP连接的另一端接收数据，它与read()函数的功能是差不多的。
+
+recv()函数会先检查套接字 s 的接收缓冲区，如果 s
+接收缓冲区中没有数据或者协议正在接收数据，那么recv就一直等待，直到协议把数据接收完毕。当协议把数据接收完毕，recv()函数就把
+s 的接收缓冲中的数据拷贝到 buf
+中，但是要注意的是议接收到的数据可能大于buf的长度，所以在这种情况下要调用几次recv()函数才能把s的接收缓冲中的数据拷贝完。recv()函数仅仅是拷贝数据，真正的接收数据是由协议来完成的，recv函数返回其实际拷贝的字节数。如果recv()函数在拷贝时出错，那么它返回SOCKET_ERROR；如果recv()函数在等待协议接收数据时网络中断了，那么它返回0。
+
+参数：
+
+-  sockfd：指定接收端套接字描述符。
+-  buf：指定一个接收数据的缓冲区，该缓冲区用来存放recv()函数接收到的数据。
+-  len：指定recv()函数拷贝的数据长度。
+
+参数 flags 一般设置为0即可，其他数值定义如下: -
+MSG_OOB：接收以out-of-band送出的数据。 -
+MSG_PEEK：保持原有数据，就是说接收到的数据并不会被删除,
+如果再调用recv()函数还会拷贝相同的数据到buf中。 -
+MSG_WAITALL：强迫接收到指定len大小的数据后才能返回,
+除非有错误或信号产生。 -
+MSG_NOSIGNAL：recv()函数不会被SIGPIPE信号中断，返回值成功则返回接收到的字符数,
+失败返回-1，错误原因存于errno中。
+
+错误代码：
+
+-  EBADF：fd 不是一个合法的套接字描述符，或者不是为读操作而打开。
+-  EFAULT：buf 超出用户可访问的地址空间。
+-  ENOTSOCK：参数 s 为一文件描述词, 非socket.
+-  EINTR：在读取到数据前被信号所中断。
+-  EAGAIN：此动作会令进程阻塞, 但参数s的 socket 为不可阻塞。
+-  ENOBUFS：buf内存空间不足。
+-  ENOMEM：内存不足。
+-  EINVAL：传入的参数不正确。
+
+write()
+-------
+
+函数原型：
+
+.. code:: c
+
+        ssize_t write(int fd, const void *buf, size_t count);
+
+write()函数一般用于处于稳定的TCP连接中传输数据，当然也能用于UDP协议中，它向套接字描述符
+fd 中写入 count 字节的数据，数据起始地址由 buf
+指定，函数调用成功返回写的字节数，失败返回-1，并设置errno变量。
+
+在网络编程中，当我们向套接字描述符写数据时有两种可能：
+
+1. write()函数的返回值大于0，表示写了部分数据或者是全部的数据，这样我们可以使用一个while循环不断的写入数据，但是循环过程中的
+   buf 参数和 count
+   参数是我们自己来更新的，也就是说，网络编程中写函数是不负责将全部数据写完之后再返回的，说不定中途就返回了！
+
+2. 返回值小于0，此时出错了，需要根据错误类型进行相应的处理。
+
+所以一般我们处理写数据的时候都会自己封装一层，以保证数据的正确写入：
+
+.. code:: c
+
+    /* Write "n" bytes to a descriptor. */
+    ssize_t writen(int fd, const void *vptr, size_t n)
+    {
+        size_t      nleft;      //剩余要写的字节数
+        ssize_t     nwritten;   //已经写的字节数
+        const char  *ptr;       //write的缓冲区
+
+        ptr = vptr;             //把传参进来的write要写的缓冲区备份一份
+        nleft = n;              //还剩余需要写的字节数初始化为总共需要写的字节数
+
+        //检查传参进来的需要写的字节数的有效性
+        while (nleft > 0) {     
+            if ( (nwritten = write(fd, ptr, nleft)) <= 0) { //把ptr写入fd
+                if (nwritten < 0 && errno == EINTR) //当write返回值小于0且因为是被信号打断
+                    nwritten = 0;       /* and call write() again */
+                else
+                    return(-1);         /* error 其他小于0的情况为错误*/
+            }
+
+            nleft -= nwritten;          //还剩余需要写的字节数=现在还剩余需要写的字节数-这次已经写的字节数
+            ptr += nwritten;          //下次开始写的缓冲区位置=缓冲区现在的位置右移已经写了的字节数大小
+        }
+        return(n); //返回已经写了的字节数
+    }
+
+    ps：当然啦，如果是比较简单的数据（比如单行数据）倒是不需要那么麻烦，直接调用write()也是完全没有问题的，只是看情况写代码就行了，上面代码的封装只是保证程序的健壮性。
+
+    注意，这个函数在写入数据完成后并不是立即发送的，至于什么时候发送则由TCP/IP协议栈决定。
+
+send()
+------
+
+函数原型：
+
+.. code:: c
+
+        int send(int s, const void *msg, size_t len, int flags);
+
+无论是客户端还是服务器应用程序都可以用send()函数来向TCP连接的另一端发送数据。
+
+参数：
+
+-  s：指定发送端套接字描述符。
+-  msg：指定要发送数据的缓冲区。
+-  len：指明实际要发送的数据的字节数。
+-  flags：一般设置为0即可
+
+当调用该函数时，send()函数先比较待发送数据的长度len和套接字s的发送缓冲的长度，如果len大于s的发送缓冲区的长度，该函数返回SOCKET_ERROR；如果len小于或者等于s的发送缓冲区的长度，那么send()函数先检查协议是否正在发送s的发送缓冲中的数据，如果是就等待协议把数据发送完，如果协议还没有开始发送s的发送缓冲中的数据或者s的发送缓冲中没有数据，那么send()函数就比较s的发送缓冲区的剩余空间和len，如果len大于剩余空间大小send()函数就一直等待协议把s的发送缓冲中的数据发送完，如果len小于剩余空间大小send()函数就仅仅把buf中的数据拷贝到s的发送缓冲区的剩余空间里。
+
+如果send()函数拷贝数据成功，就返回实际copy的字节数，如果send()函数在拷贝数据时出现错误，那么send就返回SOCKET_ERROR；如果send在等待协议传送数据时网络断开的话，那么send函数也返回SOCKET_ERROR。
+
+    注意send()函数把buf中的数据成功拷贝到s的发送缓冲的剩余空间里后它就返回了，但是此时这些数据并不一定马上被传到连接的另一端。
+
+sendto
+------
+
+函数原型：
+
+.. code:: c
+
+    int sendto(int s, const void *msg, size_t len, int flags, const struct sockaddr *to, socklen_t tolen);
+
+sendto()函数与send函数非常像，但是它会通过 struct sockaddr 指向的 to
+结构体指定要发送给哪个远端主机，在to参数中需要指定远端主机的IP地址、端口号等，而tolen参数则是指定to
+结构体的字节长度。
+
+close()
+-------
+
+函数原型：
+
+.. code:: c
+
+    int close(int fd);
+
+close()函数是用于关闭一个指定的套接字，在关闭套接字后，将无法使用对应的套接字描述符，这个函数比较简单，当你不需要使用某个套接字描述符时，就将其关闭即可，在UDP协议中，close会释放一个套接字描述符的资源；而在TCP协议中，当调用close()函数后将发起"四次挥手"终止连接，当连接正式终止后，套接字描述符的资源才会被释放。
+
+ioctlsocket()
+-------------
+
+函数原型：
+
+.. code:: c
+
+        int ioctlsocket( int s, long cmd, u_long *argp);
+
+该函数用于获取与设置套接字相关的操作参数。
+
+参数：
+
+1. s：指定要操作的套接字描述符。
+2. cmd：对套接字s的操作命令。
+
+-  FIONBIO：命令用于允许或禁止套接字的非阻塞模式。在这个命令下，argp参数指向一个无符号长整型，如果该值为0则表示禁止非阻塞模式，而如果该值非0则表示允许非阻塞模式则。当创建一个套接字的时候，它就处于阻塞模式，也就是说非阻塞模式被禁止，这种情况下所有的发送、接收函数都会是阻塞的，直至发送、接收成功才得以继续运行；而如果是非阻塞模式下，所有的发送、接收函数都是不阻塞的，如果发送不出去或者接收不到数据，将直接返回错误代码给用户，这就需要用户对这些"意外"情况进行处理，保证代码的健壮性。
+-  FIONREAD：FIONREAD命令确定套接字s自动读入的数据量，这些数据已经被接收，但应用线程并未读取的，所以可以使用这个函数来获取这些数据的长度，在这个命令状态下，argp参数指向一个无符号长整型，用于保存函数的返回值（即未读数据的长度）。如果套接字是SOCK_STREAM类型，则FIONREAD命令会返回recv()函数中所接收的所有数据量，这通常与在套接字接收缓存队列中排队的数据总量相同；而如果套接字是SOCK_DGRAM类型的，则FIONREAD命令将返回在套接字接收缓存队列中排队的第一个数据包大小。
+-  SIOCATMARK：确认是否所有的带外数据都已被读入。
+
+3. argp：指向cmd命令所带参数的指针。
+
+其实这个函数，举个例子：
+
+.. code:: c
+
+    // 控制为阻塞模式。
+    u_long mode = 0;
+    ioctlsocket(s,FIONBIO,&mode);
+
+    // 控制为非阻塞模式。
+    u_long mode = 1;
+    ioctlsocket(s,FIONBIO,&mode); 
+
+getsockopt()、setsockopt()
+--------------------------
+
+.. code:: c
+
+        int getsockopt(int sockfd, int level, int optname,
+                        void *optval, socklen_t *optlen);
+
+        int setsockopt(int sockfd, int level, int optname,
+                        const void *optval, socklen_t optlen);
+
+看名字就知道，这个函数是用于获取/设置套接字的一些选项的，参数level有多个常见的选项，如：
+
+-  SOL_SOCKET：表示在Socket层。
+-  IPPROTO_TCP：表示在TCP层。
+-  IPPROTO_IP： 表示在IP层。
+
+参数optname表示该层的具体选项名称，比如：
+
+-  对于SOL_SOCKET选项，可以是SO_REUSEADDR（允许重用本地地址和端口）、SO_SNDTIMEO（设置发送数据超时时间）、SO_SNDTIMEO（设置接收数据超时时间）、SO_RCVBUF（设置发送数据缓冲区大小）等等。
+-  对于IPPROTO_TCP选项，可以是TCP_NODELAY（不使用Nagle算法）、TCP_KEEPALIVE（设置TCP保活时间）等等。
+-  对于IPPROTO_IP选项，可以是IP_TTL（设置生存时间）、IP_TOS（设置服务类型）等等。
+
+TCP客户端实验
+-------------
+
+我们本小节就通过socket
+API函数去实现一个TCP客户端，代码的步骤首先是与服务器建立连接，然后在客户端中输入一些数据并且将它发送到服务器，最后在数据发送完毕后就终止连接，由于TCP协议的模型是
+``客户端 <-> 服务器`` ，因此我们在下一小节还会实现一个TCP服务器，两个进程间相互通信。
+
+首先明确一下整个客户端的流程步骤： 1.
+调用socket()函数创建一个套接字描述符。 2.
+调用connect()函数连接到指定服务器中，端口号为服务器监听的端口号。 3.
+调用write()函数发送数据。 4. 调用close()函数终止连接。
+
+TCP客户端代码：
+
+.. code:: c
+
+    #include <stdio.h>
+    #include <stdlib.h>
+    #include <string.h>
+    #include <unistd.h>
+    #include <errno.h>
+    #include <sys/types.h>
+    #include <sys/socket.h>
+    #include <netinet/in.h>
+    #include <arpa/inet.h>
+    #include <netdb.h>
+
+    #define HOST "192.168.0.217"        // 根据你服务器的IP地址修改
+    #define PORT 6666                   // 根据你服务器进程绑定的端口号修改
+    #define BUFFER_SIZ (4 * 1024)           // 4k的数据区域
+
+
+    int main(void)
+    {
+        int sockfd, ret;
+        struct sockaddr_in server;
+        char buffer[BUFFER_SIZ];        //用于保存输入的文本
+
+        // 创建套接字描述符
+        if ((sockfd = socket(AF_INET, SOCK_STREAM, 0)) == -1) {
+            printf("create an endpoint for communication fail!\n");
+            exit(1);
+        } 
+
+        bzero(&server, sizeof(server));
+        server.sin_family = AF_INET;
+        server.sin_port = htons(PORT);
+        server.sin_addr.s_addr = inet_addr(HOST);
+
+        // 建立TCP连接
+        if (connect(sockfd, (struct sockaddr *)&server, sizeof(struct sockaddr)) == -1) {
+            printf("connect server fail...\n");
+            close(sockfd);
+            exit(1);
+        } 
+
+        printf("connect server success...\n");
+
+        while (1) {
+
+            printf("please enter some text: ");
+            fgets(buffer, BUFFER_SIZ, stdin);
+
+            //输入了end，退出循环（程序）
+            if(strncmp(buffer, "end", 3) == 0)
+                break;
+
+            write(sockfd, buffer, sizeof(buffer));
+        }
+
+        close(sockfd);
+        exit(0);
+    }
+
+TCP服务器实验
+-------------
+
+接着我们实现一个服务器代码，接受客户端的连接，并且将来自客户端的数据打印到终端中。
+
+服务器的代码流程如下：
+
+1. 调用socket()函数创建一个套接字描述符。
+2. 调用bind()函数绑定监听的端口号。
+3. 调用listen()函数让服务器进入监听状态。
+4. 调用accept()函数处理来自客户端的连接请求。
+5. 调用read()函数接收客户端发送的数据。
+6. 调用close()函数终止连接。
+
+服务器代码：
+
+.. code:: c
+
+    #include <stdio.h>
+    #include <netdb.h>
+    #include <unistd.h>
+    #include <netinet/in.h>
+    #include <stdlib.h>
+    #include <string.h>
+    #include <sys/socket.h>
+    #include <sys/types.h>
+
+    #define MAX 10*1024
+    #define PORT 6666
+
+    // Driver function
+    int main()
+    {
+        char buff[MAX];
+        int n;
+        int sockfd, connfd, len;
+        struct sockaddr_in server, client;
+
+        // socket create and verification
+        sockfd = socket(AF_INET, SOCK_STREAM, 0);
+        if (sockfd == -1) {
+            printf("socket creation failed...\n");
+            exit(0);
+        }
+
+        printf("socket successfully created..\n");
+        bzero(&server, sizeof(server));
+
+        // assign IP, PORT
+        server.sin_family = AF_INET;
+        server.sin_addr.s_addr = htonl(INADDR_ANY);
+        server.sin_port = htons(PORT);
+
+        // binding newly created socket to given IP and verification
+        if ((bind(sockfd, (struct sockaddr*)&server, sizeof(server))) != 0) {
+            printf("socket bind failed...\n");
+            exit(0);
+        }
+        
+        printf("socket successfully binded..\n");
+
+        // now server is ready to listen and verification
+        if ((listen(sockfd, 5)) != 0) {
+            printf("Listen failed...\n");
+            exit(0);
+        }
+
+        printf("server listening...\n");
+        
+        len = sizeof(client);
+
+        // accept the data packet from client and verification
+        connfd = accept(sockfd, (struct sockaddr*)&client, &len);
+        if (connfd < 0) {
+            printf("server acccept failed...\n");
+            exit(0);
+        }
+
+        printf("server acccept the client...\n");
+
+        // infinite loop for chat
+        while(1) {
+            bzero(buff, MAX);
+
+            // read the messtruct sockaddrge from client and copy it in buffer
+            if (read(connfd, buff, sizeof(buff)) <= 0) {
+                printf("client close...\n");
+                close(connfd);
+                break;
+            }
+
+            // print buffer which contains the client contents
+            printf("from client: %s\n", buff);
+
+            // if msg contains "Exit" then server exit and chat ended.
+            if (strncmp("exit", buff, 4) == 0) {
+                printf("server exit...\n");
+                close(connfd);
+                break;
+            }
+        }
+
+        // After chatting close the socket
+        close(sockfd);
+        exit(0);
+    }
+
+实验现象
+--------
+
+分别进入 ``embed_linux_tutorial/base_code/system_programing/tcp_client`` 与 ``embed_linux_tutorial/base_code/system_programing/tcp_server`` 目录下运行make命令将客户端与服务器的代码编译，打开两个终端，然后首先运行服务器的程序，接着运行客户端的程序，然后在客户端程序中输入想要发送的数据，然后发送出去，你就会看到在服务器进程中将数据打印出来，现象如下：
+
+客户端进程：
+
+.. code:: c
+
+    ➜  tcp_client git:(master)  ./targets 
+
+    connect server success...
+    please enter some text: abcdefg
+    please enter some text: aaaaaaaaaaaa
+    please enter some text: bbbbbbbbbbbbbbbbbbb
+    please enter some text: 6666666666666666666666666
+    please enter some text: embedfire socket api      
+    please enter some text: 野火
+    please enter some text: exit
+    ➜  tcp_client git:(master) 
+
+服务器进程：
+
+.. code:: c
+
+    ➜  tcp_server git:(master) ./targets     
+
+    socket successfully created..
+    socket successfully binded..
+    server listening...
+    server acccept the client...
+    from client: abcdefg
+
+    from client: aaaaaaaaaaaa
+
+    from client: bbbbbbbbbbbbbbbbbbb
+
+    from client: 6666666666666666666666666
+
+    from client: embedfire socket api
+
+    from client: 野火
+
+    client close...
+    ➜  tcp_server git:(master)
+
diff --git a/documentation/system_programing/systemV_sem.rst b/documentation/system_programing/systemV_sem.rst
new file mode 100644
index 0000000000000000000000000000000000000000..6fef0d11daf24b25e96b2066079ab3420790c3c1
--- /dev/null
+++ b/documentation/system_programing/systemV_sem.rst
@@ -0,0 +1,317 @@
+system-V IPC 信号量
+===================
+
+**提示：本章主要讲解进程信号量的内容，如非特别说明，"信号量"均表示system-V
+IPC信号量** ，这主要是为了区分后续章节的"POSIX信号量"。
+
+进程信号量基本概念
+------------------
+
+信号量与已经介绍过的
+管道、FIFO以及消息列队不同，它本质上是一个计数器，用于多进程间对共享数据对象的读取，它和管道有所不同，它不以传送数据为主要目的，它主要是用来保护共享资源（信号量也属于临界资源），使得该临界资源在一个时刻只有一个进程独享。可能会有同学问了，为什么不使用全局变量呢？那是因为全局变量并不能在进程间共同使用，因为进程间是相互独立的，而且也无法保证引用计数的原子操作，因此使用系统提供的信号量即可。
+
+信号量的工作原理
+----------------
+
+由于信号量只能进行两种操作等待和发送信号，即P操作和V操作，锁行为就是P操作，解锁就是V操作。PV操作是计算机操作系统需要提供的基本功能之一，它们的行为是这样的：
+
+-  P
+   操作：如果有可用的资源（信号量值大于0），则占用一个资源（给信号量值减去一，进入临界区代码）;如果没有可用的资源（信号量值等于
+   0），则被阻塞到，直到系统将资源分配给该进程（进入等待队列，一直等到资源轮到该进程）。这就像你要把车开进停车场之前，先要向保安申请一张停车卡一样，P
+   操作就是申请资源，如果申请成功，资源数（空闲的停车位）将会减少一个，如果申请失败，要不在门口等，要不就走人。
+
+-  V
+   操作：如果在该信号量的等待队列中有进程在等待资源，则唤醒一个阻塞的进程。如果没有进程等待它，则释放一个资源（给信号量值加一），就跟你从停车场出去的时候一样，空闲的停车位就会增加一个。
+
+举个例子，就是两个进程共享信号量sem，sem可用信号量的数值为1，一旦其中一个进程执行了P操作，它将得到信号量，并可以进入临界区，使sem减1。而第二个进程将被阻止进入临界区，因为当它试图执行P操作时，sem为0，它会被挂起以等待第一个进程离开临界区域并执行V操作释放了信号量，这时第二个进程就可以恢复执行。
+
+在信号量进行PV操作时都为原子操作（因为它需要保护临界资源）。
+
+    注：原子操作：单指令的操作称为原子的，单条指令的执行是不会被打断的
+
+简单来说就是内核可以对这个信号量（计数器）做加减操作，并且操作时遵守一些基本操作原则，即：对计数器做加操作立即返回，做减操作要检查计数器当前值是否可减？（这个计数器的值要大于1），如果是则进行减操作；否则将进程将阻塞等待，直到系统中有进程对该信号量进行P操作。
+
+创建或获取一个信号量
+--------------------
+
+**使用信号量包含的头文件**
+
+.. code:: C
+
+        #include <sys/types.h>
+        #include <sys/ipc.h>
+        #include <sys/sem.h>
+
+**semget函数原型**
+
+.. code:: c
+
+        int semget(key_t key, int nsems, int semflg);
+
+semget()函数的功能是创建或者获取一个已经创建的信号量，如果成功则返回对应的信号量标识符，失败则返回-1。
+
+与消息队列一样的是，我们应该已经知道第一个参数key用来标识系统内的信号量，同样的也可以使用IPC_PRIVATE创建一个没有key的信号量。如果指定的key已经存在，则意味着打开这个信号量，这时nsems参数指定为0，semflg参数也指定为0。nsems参数表示在创建信号量的时候，这个信号量中可用信号量的值。最后一个semflg参数用来指定标志位，主要有：IPC_CREAT，IPC_EXCL和权限mode，其中使用IPC_CREAT
+标志创建新的信号量，即使该信号量已经存在（具有同一个键值的信号量已在系统中存在），也不会出错。如果同时使用
+IPC_EXCL
+标志可以创建一个新的唯一的信号量，此时如果该信号量已经存在，该函数会返回出错。
+
+| 创建信号量时,还受到以下系统信息的影响:
+| - SEMMNI：系统中信号量的总数最大值。 -
+SEMMSL：每个信号量中信号量元素的个数最大值。 -
+SEMMNS：系统中所有信号量中的信号量元素的总数最大值。
+
+在Linux系统中，以上信息在/proc/sys/kernel/sem 中可查看
+
+信号量操作
+----------
+
+**semop()函数原型**
+
+.. code:: c
+
+        int semop(int semid, struct sembuf *sops, size_t nsops);
+
+semop()函数主要是对信号量进行PV操作。
+
+**参数** - semid：System V信号量的标识符，用来标识一个信号量。 -
+sops：是指向一个struct
+sembuf结构体数组的指针，该数组是一个信号量操作数组。 -
+nsops：指定对数组中的几个元素进行操作，如数组中只有一个信号量就指定为1。操作的所有参数都定义在一个sembuf结构体里，其内容如下：
+
+.. code:: c
+
+    struct sembuf
+    {
+        unsigned short int sem_num;   /* 信号量的序号从0 ~ nsems-1 */
+        short int sem_op;            /* 对信号量的操作，>0, 0, <0 */
+        short int sem_flg;            /* 操作标识：0， IPC_WAIT, SEM_UNDO */
+    };
+
+1. sem_num标识信号量中的第几个信号量，0表示第1个，1表示第2个，nsems -
+   1表示最后一个。
+
+2. sem_op标识对信号量的所进行的操作类型。对信号量的操作有三种类型：
+
+-  sem_op 大于 0，则表示要释放信号量，对该信号量执行V操作，信号量的值由sem_op决定，系统会把sem_op的值加到该信号量的信号量当前值semval上。如果sem_flag指定了SEM_UNDO（还原）标志，则从该进程的此信号量调整值中减去
+   sem_op。
+
+-  sem_op 小于 0，则表示要获取由该信号量控制的资源，对该信号量执行P操作，当信号量当前值semval 大于或者等于 -sem_op
+   时，semval减掉sem_op的绝对值，为该进程分配对应数目的资源。如果指定SEM_UNDO，则sem_op的绝对值也加到该进程的此信号量调整值上。当semval 小于 -sem_op时，相应信号量的等待进程数量就加1，调用进程被阻塞，直到semval 大于或者等于 -sem_op
+   时，调用进程被唤醒，执行相应的P操作。
+
+-  sem_op 等于 0，表示调用者希望信号量的当前值变为0。如果为0则立即返回，如果不为0，相应信号量的等待进程数量加1，调用调用进程被阻塞。
+
+3. sem_flg，信号量操作的属性标志，可以指定的参数包括IPC_NOWAIT和SEM_UNDO。如果为0，表示正常操作；当指定了SEM_UNDO，那么将维护进程对信号量的调整值，进程退出的时候会自动还原它对信号量的操作；当指定了IPC_WAIT，使对信号量的操作时非阻塞的。即指定了该标志，调用进程在信号量的值不满足条件的情况下不会被阻塞，而是直接返回-1，并将errno设置为EAGAIN。
+
+那么什么是信号量调整值呢？其实就是指定信号量针对某个特定进程的调整值。只有sembuf结构的sem_flag指定为SEM_UNDO后，信号量调整值才会随着sem_op而更新。讲简单一点：对某个进程，在指定SEM_UNDO后，对信号量的当前值的修改都会反应到信号量调整值上，当该进程终止的时候，内核会根据信号量调整值重新恢复信号量之前的值。
+
+**获取或者设置信号量的相关属性**
+
+**函数原型**
+
+.. code:: c
+
+        int semctl(int semid, int semnum, int cmd, ...);
+
+函数主要是对信号量集的一系列控制操作，根据操作命令cmd的不同，执行不同的操作，依赖于所请求的命令，第四个参数是可选的。
+
+-  semid：System V信号量的标识符；
+
+-  semnum：表示信号量集中的第semnum个信号量。它的取值范围： ``0 ~ nsems-1`` 。
+
+-  cmd：操作命令，主要有以下命令：
+
+-  IPC_STAT：获取此信号量集合的semid_ds结构，存放在第四个参数的buf中。
+-  IPC_SET：通过第四个参数的buf来设定信号量集相关联的semid_ds中信号量集合权限为sem_perm中的uid，gid，mode。
+-  IPC_RMID：从系统中删除该信号量集合。
+-  GETVAL：返回第semnum个信号量的值。
+-  SETVAL：设置第semnum个信号量的值，该值由第四个参数中的val指定。
+-  GETPID：返回第semnum个信号量的sempid，最后一个操作的pid。
+-  GETNCNT：返回第semnum个信号量的semncnt。等待semval变为大于当前值的线程数。
+-  GETZCNT：返回第semnum个信号量的semzcnt。等待semval变为0的线程数。
+-  GETALL：去信号量集合中所有信号量的值，将结果存放到的array所指向的数组。
+-  SETALL：按arg.array所指向的数组中的值，设置集合中所有信号量的值。
+
+-  第四个参数是可选的：如果使用该参数，该参数的类型为 union semun，它是多个特定命令的联合，具体如下：
+
+.. code:: c
+
+        union semun {
+            int              val;    /* Value for SETVAL */
+            struct semid_ds *buf;    /* Buffer for IPC_STAT, IPC_SET */
+            unsigned short  *array;  /* Array for GETALL, SETALL */
+            struct seminfo  *__buf;  /* Buffer for IPC_INFO
+                                        (Linux-specific) */
+        };
+
+信号量实例
+----------
+
+因为system V
+的信号量相关的函数调用接口比较复杂，作者将其封装成单个信号量的几个基本函数。它们分别为信号量初始化函数sem_init()、
+P 操作函数 sem_p()、 V 操作函数 sem_v()以及删除信号量的函数
+sem_del()等，具体实现如下所示:
+
+    这些函数的实现单独作为sem.c文件的内容，同时还实现一个sem.h作为外部调用的头文件。
+
+.. code:: c
+
+    #include <sys/sem.h>
+    #include <sys/ipc.h>
+    #include <unistd.h>
+    #include <stdlib.h>
+    #include <stdio.h>
+    #include <string.h>
+    #include <sys/shm.h>
+    #include <sys/stat.h>
+    #include <fcntl.h>
+    #include <errno.h>
+
+    #include "sem.h"
+
+
+    /* 信号量初始化（赋值）函数*/
+    int sem_init(int sem_id, int init_value)
+    {
+        union semun sem_union;
+        sem_union.val = init_value; /* init_value 为初始值 */
+
+        if (semctl(sem_id, 0, SETVAL, sem_union) == -1)
+        {
+            perror("Initialize semaphore");
+            return -1;
+        }
+
+        return 0;
+    }
+
+    /* 从系统中删除信号量的函数 */
+    int sem_del(int sem_id)
+    {
+        union semun sem_union;
+        if (semctl(sem_id, 0, IPC_RMID, sem_union) == -1)
+        {
+            perror("Delete semaphore");
+            return -1;
+        }
+    }
+
+    /* P 操作函数 */
+    int sem_p(int sem_id)
+    {
+        struct sembuf sops;
+        sops.sem_num = 0; /* 单个信号量的编号应该为 0 */
+        sops.sem_op = -1; /* 表示 P 操作 */
+        sops.sem_flg = SEM_UNDO; /* 系统自动释放将会在系统中残留的信号量*/
+
+        if (semop(sem_id, &sops, 1) == -1)
+        {
+            perror("P operation");
+            return -1;
+        }
+        return 0;
+    }
+
+    /* V 操作函数*/
+    int sem_v(int sem_id)
+    {
+        struct sembuf sops;
+        sops.sem_num = 0; /* 单个信号量的编号应该为 0 */
+        sops.sem_op = 1; /* 表示 V 操作 */
+        sops.sem_flg = SEM_UNDO; /* 系统自动释放将会在系统中残留的信号量*/
+
+        if (semop(sem_id, &sops, 1) == -1)
+        {
+            perror("V operation");
+            return -1;
+        }
+        return 0;
+    }
+
+.. code:: c
+
+    #ifndef _SEM_H_
+    #define _SEM_H_
+
+
+    union semun
+    {
+        int val;
+        struct semid_ds *buf;
+        unsigned short *array;
+    };
+
+    extern int init_sem(int sem_id, int init_value);
+    extern int del_sem(int sem_id);
+    extern int sem_p(int sem_id);
+    extern int sem_v(int sem_id);
+
+    #endif
+
+在实例程序中，首先创建一个子进程，接下来使用信号量来控制两个进程（父子进程）之间的执行顺序。
+
+.. code:: c
+
+    #include <sys/types.h>
+    #include <sys/shm.h>
+    #include <sys/sem.h>
+    #include <sys/ipc.h>
+    #include <unistd.h>
+    #include <stdlib.h>
+    #include <stdio.h>
+    #include <string.h>
+    #include <sys/stat.h>
+    #include <fcntl.h>
+    #include <errno.h>
+
+    #include "sem.h"
+
+    #define DELAY_TIME 3 /* 为了突出演示效果，等待几秒钟， */
+
+    int main(void)
+    {
+        pid_t result;
+        int sem_id;
+
+        sem_id = semget((key_t)6666, 1, 0666 | IPC_CREAT); /* 创建一个信号量*/
+
+        init_sem(sem_id, 0);
+
+        /*调用 fork()函数*/
+        result = fork();
+        if(result == -1)
+        {
+            perror("Fork\n");
+        }
+        else if (result == 0) /*返回值为 0 代表子进程*/
+        {
+            printf("Child process will wait for some seconds...\n");
+            sleep(DELAY_TIME);
+            printf("The returned value is %d in the child process(PID = %d)\n",result, getpid());
+
+            sem_v(sem_id);
+        }
+
+        else /*返回值大于 0 代表父进程*/
+        {
+            sem_p(sem_id);
+            printf("The returned value is %d in the father process(PID = %d)\n",result, getpid());
+
+            sem_v(sem_id);
+
+            del_sem(sem_id);
+        }
+
+        exit(0);
+    }
+
+**实验效果如下：**
+
+.. code:: bash
+
+    ➜  systemV_sem git:(master) ✗ ./targets 
+
+    Child process will wait for some seconds...
+    The returned value is 0 in the child process(PID = 10203)
+    The returned value is 10203 in the father process(PID = 10202)
+
diff --git a/documentation/system_programing/tcp_ip.rst b/documentation/system_programing/tcp_ip.rst
new file mode 100644
index 0000000000000000000000000000000000000000..e951c110936046383be962074257019236fe4bfb
--- /dev/null
+++ b/documentation/system_programing/tcp_ip.rst
@@ -0,0 +1,452 @@
+网络编程
+========
+
+互联网对人类社会产生的巨大变革，大家是有目共睹的，它几乎改变了人类生活的方方面面。互联网通信的本质是数字通信，任何数字通信都离不开通信协议的制定，通信设备只有按照约定的、统一的方式去封装和解析信息，才能实现通信。互联网通信所要遵守的众多协议，被统称为TCP/IP。
+
+网络相关知识简介
+----------------
+
+因为网络的知识太庞大了，想要介绍清除得写好几本书，在这里就简单提及一下就好了。
+
+TCP/IP是一个协议族，包含众多的协议。但对于网络应用开发人员，可能听到更多的是其中的应用层协议，比如HTTP、FTP、MQTT等。
+
+比如：
+
+HTTP协议是Hyper Text Transfer
+Protocol（超文本传输协议）的缩写，HTTP的应用最为广泛。比如大家日常使用电脑时的一个常规操作：打开电脑，打开浏览器，输入网址，最后按下回车，这一刻你就开启了HTTP通信。HTTP协议工作于架构之上，（服务端也称作为服务器端，除非特别说明，否则本书出现的"服务端"即为"服务器端"），浏览器作为HTTP客户端通过URL向HTTP服务端即WEB服务器发送所有请求。Web服务器根据接收到的请求后，向客户端发送响应信息。借助这种浏览器和服务器之间的HTTP通信，我们能够足不出户地获得来自世界各个角落的信息。另外，网页不仅仅是大型服务器的专利，
+在物联网风潮盛行的今天，许多随处可见的小型设备（空调、冰箱、插座、路由器等），都内嵌网页，在物理链路畅通的情况下，用户可以用手机、平板电脑上的浏览器随时随地监控这些设备。
+
+FTP（File Transfer
+Protocol）是文件传输协议的简称。FTP是工作在应用层的网络协议。FTP使得主机间可以共享文件，用于在两台设备之间传输文件（双向传输）。它也是一个客户端-服务端框架系统。用户可以通过一个支持FTP协议的客户端程序，连接到在远程主机上的FTP服务端程序，通过客户端程序向服务端程序发出命令，服务端程序执行用户所发出的命令，并将执行的结果返回到客户机。FTP除了基本的文件上传/下载功能外，还有目录操作、权限设置、身份验证机制，许多网盘的文件传输功能都是基于FTP实现的。
+
+在物联网发展的处期，物联网场景中的设备使用何种应用层协议进行通信一直是备受争议的话题。很多开发人员习惯了网页的开发模式，于是经常选择HTTP作为通信方式。使用HTTP有以下不利因素：HTTP是一种同步协议，设备需要等待服务器的响应才可以进行下一步的工作，然而在设备数量多、网络不可靠的场景下，实现同步通信很困难；HTTP是单向的，设备只能主动向服务器发出数据，无法被动的接收来自网络的数据，这不适用于实时控制的场合；HTTP是有许多帧头和规则的重量级协议，实现在设备中需要耗费大量的系统资源。基于上述的形势，MQTT和COAP等轻量级、异步的通信协议便得到了物联网设备开发商的宠爱，尤其是MQTT。MQTT（消息队列遥测传输）是IBM公司于1990年设计并推出的一款通信协议，于2014年正式成为了一个OASIS开放标准。近年来，MQTT的应用呈现出爆炸性的增长势头，大有一统物联网的趋势。另外，MQTT在物联网以外的其他领域也得到了广泛的应用，比如许多公司在制作手机APP时，会使用MQTT来实现消息推送、即时聊天等功能。
+
+嵌入式设备接入互联网的需求越来越大，有以下几点原因：
+
+1. 近些年，各种带网络接入功能的MCU、SoC层出不穷，开源轻量的TCP/IP协议栈日趋成熟和完善，云平台的市场越来越繁荣，这些因素大大降低了嵌入式设备的入网成本，也为许多资源受限的低端设备接入互联网提供了可能。
+2. "物联网+"的风潮日渐盛行，设备能够被远程监控，这一点已经成为许多产品的技术要求。
+3. 人们对于设备"智能性"的追求越来越高，当今热门的大数据、图像处理、语音识别、机器学习等功能都可以被集成在云端，成为云平台能提供的服务。终端设备大多是计算、存储能力有限的设备，这些设备如果想要获取"智能"，最便捷的办法就是接入云平台，利用各项云服务。
+
+互联网的基础就是TCP/IP。TCP/IP是一个非常复杂的协议族，即便我们能把它的设计思想和实现原理都解释得清清楚楚，你也不见得有时间和精力去学习它，所以本书的写作重点不在于对TCP/IP的解读，而在于对它的应用。另外，TCP/IP的复杂性也决定了它并不是那么简单就能用好的东西，即便我们只关注应用开发，也依然需要对它的许多概念和设计思想有所了解，才能编写出正确、高效、健壮性好的应用程序。
+
+互联网对人类社会产生的巨大变革，大家是有目共睹的，它几乎改变了人类生活的方方面面。互联网通信的本质是数字通信，任何数字通信都离不开通信协议的制定，通信设备只有按照约定的、统一的方式去封装和解析信息，才能实现通信。互联网通信所要遵守的众多协议，被统称为TCP/IP。
+
+网络协议的分层模型
+~~~~~~~~~~~~~~~~~~
+
+TCP/IP是一个庞大的协议族，它是众多网络协议的集合，包括：ARP、IP、ICMP、UDP、TCP、DNS、DHCP、HTTP、FTP、MQTT等等。这些协议按照功能，可以被划分为几个不同的层次，如图所示。比如HTTP、FTP、MQTT，它们隶属于应用层，。那么TCP/IP为什么需要分层，分层又是依靠什么依据呢？
+
+.. figure:: media/tcpip001.png
+   :alt: tcpip001
+
+   tcpip001
+TCP/IP协议栈中不同协议所完成的功能是不一样的，
+某些协议的实现要依赖于其它协议，依据这种依赖关系，可以将协议栈分层。在图中，低层协议为相邻的上层协议提供服务，是上层协议得以实现的基础。
+
+其中，物理层（PHY）规定了传输信号所需要的物理电平、介质特征；
+
+链路层（MAC）规定了数据帧能被网卡接收的条件，最常见的方式是利用网卡的MAC地址，发送方会在欲发送的数据帧的首部加上接收方网卡的MAC地址信息，接收方只有监听到属于自己的MAC地址信息后，才会去接收并处理该数据。
+
+每台网络设备都应该有自己的网络地址，网络层规定了主机的网络地址该如何定义，以及如何在网络地址和MAC地址之间进行映射，即ARP协议；网络层实现了数据包在主机之间的传递，而一台主机内部可能运行着多个网络程序。
+
+传输层可以区分数据包是属于哪一个应用程序的，可以说传输层实现了数据包端到端的传递。另外，数据包在传输过程中可能会出现丢包、乱序和重复的现象，网络层并没有提供应对这些错误的机制，而传输层可以解决这些问题，如TCP协议；
+
+应用层以下的工作完成了数据的传递工作，应用层则决定了你如何应用和处理这些数据，之所以会有许多的应用层协议，是因为互联网中传递的数据种类很多、差异很大、应用场景十分多样。
+
+协议层报文间的封装与拆封
+~~~~~~~~~~~~~~~~~~~~~~~~
+
+在这里，我们简单解释一下在数据的发送和接收过程中，TCP/IP都做了哪些事儿。
+
+当用户发送数据时，将数据向下交给传输层，这是处于应用层的操作，而应用层也有相关的协议，对用户的数据进行封装，比如MQTT、HTTP等协议，最后应用层通过调用传输层的接口来将数据递交到传输层中。传输层会在数据前面加上传输层首部（此处以TCP协议为例，图中的传输层首部为TCP首部，也可以是UDP首部），然后向下交给网络层。同样地，网络层会在数据前面加上网络层首部（IP首部），然后将数据向下交给链路层，链路层会对数据进行最后一次封装，即在数据前面加上链路层首部（此处使用以太网接口为例），然后将数据交给网卡。最后，网卡将数据转换成物理链路上的电平信号，数据就这样被发送到了网络中。数据的发送过程，可以概括为TCP/IP的各层协议对数据进行封装的过程，如图所示：
+
+.. figure:: media/tcpip002.png
+   :alt: tcpip002
+
+   tcpip002
+当设备的网卡接收到某个数据包后，它会将其放置在网卡的接收缓存中，并告知TCP/IP内核。然后TCP/IP内核就开始工作了，它会将数据包从接收缓存中取出，并逐层解析数据包中的协议首部信息，并最终将数据交给某个应用程序。数据的接收过程与发送过程正好相反，可以概括为TCP/IP的各层协议对数据进行解析的过程。
+
+IP协议
+------
+
+IP协议（Internet
+Protocol），又称之为网际协议，IP协议处于IP层工作，它是整个TCP/IP协议栈的核心协议，上层协议都要依赖IP协议提供的服务，IP协议负责将数据报从源主机发送到目标主机，通过IP地址作为唯一识别码，简单来说，不同主机之间的IP地址是不一样的，在发送数据报的过程中，IP协议还可能对数据报进行分片处理，同时在接收数据报的时候还可能需要对分片的数据报进行重装等等。
+
+IP协议是一种无连接的不可靠数据报交付协议，协议本身不提供任何的错误检查与恢复机制。
+
+IP地址简述
+~~~~~~~~~~
+
+在TCP/IP设计之初，为了标识互联网中的每台主机的身份，设计人员为每个接入网络中的主机都分配一个IP地址（Internet
+Protocol
+Address），是一个32位的整数地址，只有合法的IP地址才能接入互联网中并且与其他主机进行通信，IP地址是软件地址，不是硬件地址，硬件MAC地址是存储在网卡中的，应用于本地网络中寻找目标主机。而IP地址能让一个网络中的主机能够与另一个网络中的主机进行通信，无需理会这些主机之间的MAC地址。
+
+在学习IP地址之前，我们需要简述一下主机与路由器连入网络的通信的方法：一台主机通常只有一条链路连接到网络，一般只有一个网卡；当主机中想发送一个数据报时，它就在该链路上发送，一个网卡对应一个MAC地址与IP地址，当然，主机也可能有多个网卡，这样子主机就有多个MAC地址与IP地址。
+
+每个IP地址长度为32比特（4字节），因此总共有2^32个可能的IP地址，大约有40亿个IP地址能被使用的。这些地址一般按所谓点分十进制记法（dotted-decimal
+notation）书写，即地址中的每个字节用它的十进制形式书写，各字节间以点分隔开。例如，
+IP地址为192.168.0.122，192是该地址第一个8比特的十进制等价数，168是该地址第二个8比特的十进制等价数，依次类推。
+
+IP地址编址
+~~~~~~~~~~
+
+在全球的互联网中，每个主机都要唯一的一个IP地址作为身份识别，那么这么多IP地址是怎么样分配的呢？这不可能是随意自由选择IP地址的，实际上每个主机的IP地址的一部分都由其所在的子网决定的，所以又出现了IP地址分类编址的概念，网络的类型决定了IP
+地址将如何划分成网络部分和节点部分，在分类编址中，设计者把所有的IP地址划分为5大类，分别为A、B、C、D、E五类，每一类地址都觉定了其中IP地址的一部分组成，具体见：
+
+.. figure:: media/tcpip003.png
+   :alt: tcpip003
+
+   tcpip003
+A 类网络地址的第一个字节的第一位必须为0 ，因此， A
+类网络地址第一个字节的取值范围为0~127（注意：但0 和127 不是有效的A
+类网络地址号），A类地址总共有128个网络号，其中3个网络号用作特殊用途，因此可以在互联网上使用的还有125个，而每一个网络号后面的3字节主机号表示能用于A类网络地址不同网络号的的主机数量（多达2^24-2
+=
+16777214个），所以总的来说A类网络支持的主机数量为125*16777214=2097151750个，大约占据了40亿IP地址的半壁江山，这些IP地址通常被分配给世界上超大型的机构使用，但是通常没有任何一个机构能使用那么大量的IP地址，所以A类地址的很多IP地址都会被白白浪费掉。
+
+B 类网络地址的第一个字节的第一位必须为1 ，且第二位必须为0，因此， B
+类网络地址第一个字节的取值范围为128~191，前2字节剩余的14bit表示网络号，多达16384个网络号，其中16个网络号被保留使用，因此可以分配给企业使用的网络号有16368个，每一个网络号中可以拥有2^16-2
+=65534个主机，总的来说B类网络支持的主机个数为16368*65534=1072660512，大约占据了所有IP地址的四分之一。
+
+C类网络地址的第一个字节的第一位必须为1，第二位必须为1，第三位必须为0，因此C类网络第一个字节的取值范围为192~223，C类地址的前三个字节用于表示网络号（剩下的21bit），所以拥有2097152个网络号，但是其中的256个网络号被保留出来，因此C类地址的可用网络号为2096896个，每个网络号下的主机个数为254，因此C类网络支持的主机数量为532611584，大约占据了所有IP地址的八分之一。
+
+D类IP地址的第一个字节前四位为1110，那么它第一个字节的取值范围为224~239，约占据了所有IP地址的十六分之一，它是一个专门保留的地址，它并不指向特定的网络，目前这一类地址被用于多播。
+
+E类IP地址的第一个字节前四位必须为1111，那么它第一个字节的取值范围为240~255，约占据了所有IP地址的十六分之一，是为将来使用而保留的，其中32bit全为1的IP地址（255.255.255.255）用作广播地址。
+
++--------+--------------------+--------------------+--------------+--------------+------------+
+| 类别   | 第一字节(二进制)   | 第一字节取值范围   | 网络号个数   | 主机号个数   | 适用范围   |
++========+====================+====================+==============+==============+============+
+| A类    | 0XXX XXXX          | 0~127              | 125          | 16777214     | 大型网络   |
++--------+--------------------+--------------------+--------------+--------------+------------+
+| B类    | 10XX XXXX          | 128~191            | 16368        | 65534        | 中型网络   |
++--------+--------------------+--------------------+--------------+--------------+------------+
+| C类    | 110X XXXX          | 192~223            | 2097152      | 254          | 小型网络   |
++--------+--------------------+--------------------+--------------+--------------+------------+
+| D类    | 1110 XXXX          | 224~239            | —            | —            | 多播       |
++--------+--------------------+--------------------+--------------+--------------+------------+
+| E类    | 1111 XXXX          | 240~255            | —            | —            | 保留       |
++--------+--------------------+--------------------+--------------+--------------+------------+
+
+特殊IP地址
+~~~~~~~~~~
+
+除了上述的网络地址外，还有一些特殊用途的地址，这些地址是不允许分配给任何一个网络的主机使用的，下面简单介绍几个常见的特殊地址。
+
+受限广播地址
+^^^^^^^^^^^^
+
+广播通信是一对所有的通信方式，受限广播地址用于定义整个互联网，如果设备想使IP数据报被整个网络所接收，就发送这个目的地址全为1的广播包，但这样会给整个互联网带来灾难性的负担，所以在任何情况下，路由器都会禁止转发目的地址为255.255.255.255的广播数据包，因此这样的数据包仅会出现在本地网络中（局域网），255.255.255.255这个地址指本网段内的所有主机，
+相当于"房子里面的人都听着"通知所有主机。
+
+注意：此处不要与以太网的广播地址（255-255-255-255-255-255）混淆了。
+
+直接广播地址
+^^^^^^^^^^^^
+
+受限广播地址是网络号与主机号都为1的地址，但是直接广播地址是主机号全为1而得到的地址，广播地址代表本网络内的所有主机，使用该地址可以向网络内的所有主机发送数据，比如一个IP地址是192.168.0.181，这是C类地址，所以它的主机号只有一个字节，那么对主机号全取1得到一个广播地址192.168.0.255，向这个地址发送数据就能让同一网络下的所有主机接收到。
+
+A、B、C三类地址的广播地址结构如下：
+
+-  A类地址的广播地址为：XXX.255.255.255（XXX为A类地址的第一个字节取值范围）。
+-  A类地址的广播地址为：XXX.
+   XXX.255.255（XXX为B类地址的前两个字节取值范围）。
+-  A类地址的广播地址为：XXX. XXX.
+   XXX.255（XXX为C类地址的前三个字节取值范围）。
+
+注意：这个地址在IP数据报中只能作为目的地址。另外，直接广播地址使一个网段中可分配给设备的地址数减少了1个。
+
+多播地址
+^^^^^^^^
+
+多播地址用在一对多的通信中，即一个发送者，多个接收者，不论接受者员数量的多少，发送者只发送一次数据包。多播地址属于分类编址中的D类地址，
+D类地址只能用作目的地址，而不能作为主机中的源地址。
+
+环回地址
+^^^^^^^^
+
+127网段的所有地址都称为环回地址，主要用来测试网络协议是否工作正常的作用。比如在电脑中使用ping
+命令去ping
+127.1.1.1就可以测试本地TCP/IP协议是否正常。用通俗的话表示，就是"我自己"，不能以127网段中的IP地址作为主机地址，因此A类地址又少了一个可用网络号。
+
+本网络本主机
+^^^^^^^^^^^^
+
+IP地址32bit全为0的地址（0.0.0.0）表示的是本网络本主机，这个IP地址在IP数据报中只能用作源IP地址，这发生在当设备启动时但又不知道自己的IP地址情况下。在使用DHCP分配IP地址的网络环境中，这样的地址是很常见的，主机为了获得一个可用的IP地址，就给DHCP服务器发送IP数据报，并用这样的地址（0.0.0.0）作为源地址，目的地址为255.255.255.255（因为主机这时还不知道DHCP服务器的IP地址），然后DHCP服务器就会知道这个主机暂时没有IP地址，那么就会分配一个IP给这个主机。
+
+UDP协议
+-------
+
+UDP 是User Datagram Protocol的简称，
+中文名是用户数据报协议，是一种无连接、不可靠的协议，它只是简单地实现从一端主机到另一端主机的数据传输功能，这些数据通过IP层发送，在网络中传输，到达目标主机的顺序是无法预知的，因此需要应用程序对这些数据进行排序处理，这就带来了很大的不方便，此外，UDP协议更没有流量控制、拥塞控制等功能，在发送的一端，UDP只是把上层应用的数据封装到UDP报文中，在差错检测方面，仅仅是对数据进行了简单的校验，然后将其封装到IP数据报中发送出去。而在接收端，无论是否收到数据，它都不会产生一个应答发送给源主机，并且如果接收到数据发送校验错误，那么接收端就会丢弃该UDP报文，也不会告诉源主机，这样子传输的数据是无法保障其准确性的，如果想要其准确性，那么就需要应用程序来保障了。
+UDP协议的特点：
+
+1. 无连接、不可靠。
+2. 尽可能提供交付数据服务，出现差错直接丢弃，无反馈。
+3. 面向报文，发送方的UDP拿到上层数据直接添加个UDP首部，然后进行校验后就递交给IP层，而接收的一方在接收到UDP报文后简单进行校验，然后直接去除数据递交给上层应用。
+4. 支持一对一，一对多，多对一，多对多的交互通信。
+5. 速度快，UDP没有TCP的握手、确认、窗口、重传、拥塞控制等机制，UDP是一个无状态的传输协议，所以它在传递数据时非常快，即使在网络拥塞的时候UDP也不会降低发送的数据。
+
+UDP虽然有很多缺点，但是也不排除其能用于很多场合，因为在如今的网络环境下，UDP协议传输出现错误的概率是很小的，并且它的实时性是非常好，常用于实时视频的传输，比如直播、网络电话等，因为即使是出现了数据丢失的情况，导致视频卡帧，这也不是什么大不了的事情，所以，UDP协议还是会被应用与对传输速度有要求，并且可以容忍出现差错的数据传输中。
+
+TCP协议
+-------
+
+TCP协议简介
+~~~~~~~~~~~
+
+TCP与UDP一样，都是传输层的协议，但是提供的服务却大不相同，UDP为上层应用提供的是一种不可靠的，无连接的服务，而TCP则提供一种面向连接、可靠的字节流传输服务，TCP让两个主机建立连接的关系，应用数据以数据流的形式进行传输，这与UDP协议是不一样：
+
+-  UDP运载的数据是以报文的形式，各个报文在网络中互不相干传输，UDP每收到一个报文就递交给上层应用，因此如果对于大量数据来说，应用层的重装是非常麻烦的，因为UDP报文在网络中到达目标主机的顺序是不一样的；
+-  而TCP采用数据流的形式传输，先后发出的数据在网络中虽然也是互不相干的传输，但是这些数据本身携带的信息却是紧密联系的，TCP协议会给每个传输的字节进行编号，当然啦，两个主机方向上的数据编号是彼此独立的，在传输的过程中，发送方把数据的起始编号与长度放在TCP报文中，在接收方将所有数据按照编号组装起来，然后返回一个确认，当所有数据接收完成后才将数据递交到应用层中。
+
+TCP的特性
+~~~~~~~~~
+
+连接机制
+^^^^^^^^
+
+TCP是一个面向连接的协议，无论哪一方向另一方发送数据之前，都必须先在双方之间建立一个连接，否则将无法发送数据，一个TCP连接必须有双方IP地址与端口号，就像打电话一样，必须知道双方的电话号码才会打电话，关于具体的连接我们在后文讲解。
+
+确认与重传
+^^^^^^^^^^
+
+一个完整的TCP传输必须有数据的交互，接收方在接收到数据之后必须正面进行确认，向发送方报告接收的结果，而发送方在发送数据之后必须等待接收方的确认，同时发送的时候会启动一个定时器，在指定超时时间内没收到确认，发送方就会认为发送失败，然后进行重发操作，这就是重传报文。
+
+TCP提供可靠的运输层，但它依赖的是IP层的服务，IP数据报的传输是无连接、不可靠的，因此它要通过确认来知道接收方确实已经收到数据了。但数据和确认都有可能会丢失，因此TCP通过在发送时设置一个超时机制（定时器）来解决这种问题，如果当超时时间到达的时候还没有收到对方的确认，它就重传该数据。
+
+缓冲机制
+^^^^^^^^
+
+在发送方想要发送数据的时候，由于应用程序的数据大小、类型都是不可预估的，而TCP协议提供了缓冲机制来处理这些数据，如在数据量很小的时候，TCP会将数据存储在一个缓冲空间中，等到数据量足够大的时候在进行发送数据，这样子能提供传输的效率并且减少网络中的通信量，而且在数据发送出去的时候并不会立即删除数据，还是让数据保存在缓冲区中，因为发送出去的数据不一定能被接收方正确接收，它需要等待到接收方的确认再将数据删除。同样的，在接收方也需要有同样的缓冲机制，因为在网络中传输的数据报到达的时间是不一样的，而且TCP协议还需要把这些数据报组装成完整的数据，然后再递交到应用层中。
+
+全双工通信
+^^^^^^^^^^
+
+在TCP连接建立后，那么两个主机就是对等的，任何一个主机都可以向另一个主机发送数据，数据是双向流通的，所以TCP协议是一个全双工的协议，这种机制为TCP协议传输数据带来很大的方便，一般来说，TCP协议的确认是通过捎带的方式来实现，即接收方把确认信息放到反向传来的是数据报文中，不必单独为确认信息申请一个报文，捎带机制减少了网络中的通信流量。由于双方主机是对等的存在，那么容易一方都可以断开连接，此时这个方向上的数据流就断开了，但是另一个
+方向上的数据仍是连通的状态，这种情况就称之为半双工。
+
+流量控制
+^^^^^^^^
+
+在前面讲过，一条TCP连接每一侧的主机都设置了缓冲区域。当该接收方收到数据后，它就将数据放入接收缓冲区，当确认这段数据是正常的时候，就会向发送方返回一个确认。并且向相关的应用层递交该数据，但不一定是数据刚一到达就立即递交。事实上，接收方应用也许正忙于其他任务，甚至要过很长时间后才会去处理这些数据。这样子如果接收方处理这些数据时相对缓慢，而发送方发送得太多、太快，就会很容易地使接收方的接收缓冲区发生溢出。
+
+因此TCP提供了流量控制服务（flow-control
+service）以消除发送方使接收方缓冲区溢出的可能性。流量控制是一个速度匹配服务，即发送方的发送速率与接收方应用程序的读取速率相匹配，TCP通过让发送方维护一个称为接收窗口（receive
+window）的变量来提供流量控制，是的，你没看错，是接收窗口（rwnd），它用于给发送方一个指示：接收方还能接收多少数据，接收方会将此窗口值放在
+TCP
+报文的首部中的窗口字段，然后传递给发送方，这个窗口的大小是在发送数据的时候动态调整的。
+
+那可能有人问，这个窗口既然是动态调整的，那有没有可能是0，这样子发送方不就是没法继续发送数据到接收方了？为了解决这个问题，TCP协议的规范中有些要求，当接收方主机的接收窗口为0时，发送方继续发送只有一个字节的报文段，这些报文段将被接收方接收，直到缓存清空，并在确认报文中包含一个非0的接收窗口值。
+
+流量控制是双方通信之间的控制信息，这是很有必要的，比如两个新能不对等的主机，建立了TCP协议连接，但是其中一个主机一直发送数据，但是接收的主机来不及处理，这样子的处理就不是最佳的，因此，TCP协议中使用滑动窗口的流量控制方法，它允许接收方根据自身的处理能力来确定能接收数据的多少，因此会告诉发送方可以发送多少数据过来，即窗口的大小，而发送方尽可能将数据都多发到对方那里，所以发送方会根据这个窗口的大小发送对应的数据
+，通俗地来说就是接收方告诉发送方"我还有能力处理那么多的数据，你就发那么多数据给我就行了，不要发多了，否则我处理不了"。
+
+差错控制
+^^^^^^^^
+
+除了确认与重传之外，TCP协议也会采用校验和的方式来检验数据的有效性，主机在接收数据的时候，会将重复的报文丢弃，将乱序的报文重组，发现某段报文丢失了会请求发送方进行重发，因此在TCP往上层协议递交的数据是顺序的、无差错的完整数据。
+
+拥塞控制
+^^^^^^^^
+
+什么是拥塞？当数据从一个大的管道（如一个快速局域网）向一个较小的管道（如一个较慢的广域网）发送时便会发生拥塞。当多个输入流到达一个路由器，而路由器的输出流小于这些输入流的总和时也会发生拥塞，这种是网络状况的原因。
+如果一个主机还是以很大的流量给另一个主机发送数据，但是其中间的路由器通道很小，无法承受这样大的数据流量的时候，就会导致拥塞的发生，这样子就导致了接收方无法在超时时间内完成接收（接收方此时完全有能力处理大量数据），而发送方又进行重传，这样子就导致了链路上的更加拥塞，延迟发送方必须实现一直自适应的机制，在网络中拥塞的情况下调整自身的发送速度，这种形式对发送方的控制被称为拥塞控制（congestion
+control），与前面我们说的流量控制是非常相似的，而且TCP协议采取的措施也非常相似，均是限制发送方的发送速度。
+
+端口号的概念
+------------
+
+TCP协议的连接是包括上层应用间的连接，简单来说，TCP连接是两个不同主机的应用连接，而传输层与上层协议是通过端口号进行识别的，如IP协议中以IP地址作为识别一样，端口号的取值范围是0~65535，这些端口标识着上层应用的不同线程，一个主机内可能只有一个IP地址，但是可能有多个端口号，每个端口号表示不同的应用线程。一台拥有IP地址的主机可以提供许多服务，比如Web服务、FTP服务、SMTP服务等，这些服务完全可以通过1个IP地址来实现，主机是怎样区分不同的网络服务呢？显然不能只靠IP地址，因为IP
+地址只能识别一台主机而非主机提供的服务，这些服务就是主机上的应用线程，因此是通过"IP地址+端口号"来区分主机不同的线程。
+
+常见的TCP协议端口号有21、53、80等等，更多端口描述具体见表格，其中80端口号是我们日常生活中最常见的一个端口号，它也是HTTP服务器默认开放的端口。
+
++----------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+| 端口号   | 协议     | 说明                                                                                                                                                                                                     |
++==========+==========+==========================================================================================================================================================================================================+
+| 20/21    | FTP      | 文件传输协议，使得主机间可以共享文件。                                                                                                                                                                   |
++----------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+| 23       | Telnet   | 终端远程登录，它为用户提供了在本地计算机上完成远程主机工作的能力。                                                                                                                                       |
++----------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+| 25       | SMTP     | 简单邮件传输协议，它帮助每台计算机在发送或中转信件时找到下一个目的地。                                                                                                                                   |
++----------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+| 69       | TFTP     | 普通文件传输协议。                                                                                                                                                                                       |
++----------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+| 80       | HTTP     | 超文本传输协议，通过使用网页浏览器、网络爬虫或者其它的工具，客户端发起一个HTTP请求到服务器上指定端口（默认端口为80），应答的服务器上存储着一些资源，比如HTML文件和图像，那么就会返回这些数据到客户端。   |
++----------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+| 110      | POP3     | 邮局协议版本3，本协议主要用于支持使用客户端远程管理在服务器上的电子邮件。                                                                                                                                |
++----------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
+举个例子，我们访问 http://www.firebbs.cn 这个网站，如果我们在浏览器中输入 http://www.firebbs.cn:80 ，访问这个服务器的80端口，我们还是会进入一样的页面，但是如果我们输入 http://www.firebbs.cn:90 去访问这个服务器的90端口，这是不允许访问的。
+
+TCP报文段
+---------
+
+TCP报文段由 ``首部 + 数据区域`` 组成，TCP报文段的首部我们称之为TCP首部，其首部内容很丰富，各个字段都有不一样的含义，如果不计算选项字段，一般来说TCP首部只有20个字节，具体见图：
+
+.. figure:: media/tcpip004.png
+   :alt: tcpip004
+
+   tcpip004
+每个TCP报文段都包含源主机和目标主机的端口号，用于寻找发送端和接收端应用线程，这两个值加上IP首部中的源IP地址和目标IP地址就能确定唯一一个TCP连接。
+
+序号字段用来标识从TCP发送端向TCP接收端发送的数据字节流，它的值表示在这个报文段中的第一个数据字节所处位置吗，根据接收到的数据区域长度，就能计算出报文最后一个数据所处的序号，因为TCP协议会对发送或者接收的数据进行编号（按字节的形式），那么使用序号对每个字节进行计数，就能很轻易管理这些数据。序号是32
+bit的无符号整数。
+
+当建立一个新的连接时，TCP报文段首部的
+SYN标志变1，序号字段包含由这个主机随机选择的初始序号ISN（Initial
+Sequence Number）。该主机要发送数据的第一个字节序号为
+ISN+1，因为SYN标志会占用一个序号，在这里我们只需要了解一下即可，后面会讲解的。
+
+既然TCP协议给每个传输的字节都了编号，那么确认序号就包含接收端所期望收到的下一个序号，因此，确认序号应当是上次已成功收到数据的最后一个字节序号加
+1。当然，只有ACK标志为
+1时确认序号字段才有效，TCP为应用层提供全双工服务，这意味数据能在两个方向上独立地进行传输，因此确认序号通常会与反向数据（即接收端传输给发送端的数据）封装在同一个报文中（即捎带），所以连接的每一端都必须保持每个方向上的传输数据序号准确性。
+
+首部长度字段占据4bit空间，它指出了TCP报文段首部长度，以字节为单位，最大能记录15*4=60字节的首部长度，因此，TCP报文段首部最大长度为60字节。在字段后接下来有6bit空间是保留未用的。
+
+此外还有6bit空间，是TCP报文段首部的标志字段，用于标志一些信息： -
+URG：首部中的紧急指针字段标志，如果是1表示紧急指针字段有效。 -
+ACK：首部中的确认序号字段标志，如果是1表示确认序号字段有效。 -
+PSH：该字段置一表示接收方应该尽快将这个报文段交给应用层。 -
+RST：重新建立TCP连接。 - SYN：用同步序号发起连接。 - FIN：中止连接。
+
+TCP的流量控制由连接的每一端通过声明的窗口大小来提供，窗口大小为字节数，起始于确认序号字段指明的值，这个值是接收端正期望接收的数据序号，发送方根据窗口大小调整发送数据，以实现流量控制。窗口大小是一个占据16
+bit空间的字段，因而窗口最大为
+65535字节，当接收方告诉发送方一个大小为0的窗口时，将完全阻止发送方的数据发送。
+
+检验和覆盖了整个的
+TCP报文段：TCP首部和TCP数据区域，由发送端计算和填写，并由接收端进行验证。
+
+只有当URG标志置1时紧急指针才有效，紧急指针是一个正的偏移量，和序号字段中的值相加表示紧急数据最后一个字节的序号。简单来说，本TCP报文段的紧急数据在报文段数据区域中，从序号字段开始，偏移紧急指针的值结束。
+
+选项字段我们暂时就无需理会了。
+
+TCP建立连接
+-----------
+
+TCP是一个面向连接的协议，无论哪一方向另一方发送数据之前，都必须先在双方之间建立一条连接，俗称"握手"，可能在学习网络之前，大家或多或少都听过"三次握手"、"四次挥手"这两个词汇，那么"三次握手"、"四次挥手"是怎么样的呢？本小节将详细讨论一个
+TCP连接是如何建立的以及通信结束后是如何终止的。
+
+**"三次握手"建立连接：**
+
+首先建立连接的过程是由客户端发起，而服务器无时无刻都在等待着客户端的连接，其示意图具体见图，TCP连接一般来说会经历以下过程：
+
+.. figure:: media/tcpip005.png
+   :alt: tcpip005
+
+   tcpip005
+第一步：客户端的TCP首先向服务器端的TCP发送一个特殊的TCP报文段。该报文段中不包含应用层数据，但是在报文段的首部中的SYN标志位会被置为1。因此，这个特殊报文段被称为SYN报文段（我们暂且称之为握手请求报文）。另外，客户会随机地选择一个初始序号（ISN，假设为A），并将此序号放置于该SYN报文段的序号字段中；但SYN报文段中的ACK标志位0，此时它的确认序号段是无效的。该报文段会被封装在一个IP数据报中，然后发送给目标服务器。
+
+第二步：一旦服务器收到了客户端发出的SYN报文段，知道客户端要请求握手了，服务器便会从SYN报文段中提取对应的信息，为该TCP连接分配TCP缓存和变量，并向该客户TCP发送允许连接的报文段（握手应答报文）。这个报文段同样也不包含任何应用层数据，但是，在报文段的首部却包含3个重要的信息。
+
+1. SYN与ACK标志都被置为1。
+2. 将TCP报文段首部的确认序号字段设置为A+1（这个A（ISN）是从握手请求报文中得到）。
+3. 服务器随机选择自己的初始序号（ISN，注意此ISN是服务器端的ISN，假设为B），并将其放置到TCP报文段首部的序号字段中。
+
+这个允许连接的报文段实际上表明了："我收到了你发起建立连接的请求，初始序号为A，我同意建立该TCP连接，我自己的初始序号是B。"该允许连接的报文段有时被称为SYN
+ACK报文段（SYN ACK
+segment），同时由于ACK标志位1，所以TCP报文段首部的窗口大小字段是有效的。
+
+第三步：当客户端收到服务器的握手应答报文后，会将ACK标志置位，此时客户端的TCP报文段的
+ACK标志被设置为1，而对于SYN标志，因为连接已经建立了，所以该标志会被置为0，同时客户端也要给该TCP连接分配缓存和变量，并且客户端还需要返回一个应答报文段，这个报文对服务器的应答报文段作出应答，将TCP报文段首部的确认序号字段设置为B+1，同时也会告知服务器的窗口大小。
+
+    补充提示：在三次握手的第三个阶段可以在报文段数据区域中携带客户到服务器的数据。
+
+在完成握手后，客户端与服务器就建立了连接，同时双方都得到了彼此的窗口大小，序列号等信息，在传输TCP报文段的时候，每个TCP报文段首部的SYN标志都会被置0，因为它只用于发起连接，同步序号。
+
+TCP终止连接
+-----------
+
+建立一个连接需要三次握手，而终止一个连接要经过
+四次挥手（有一些书上也会称为"四次握手"），这由 TCP的特性造成的，因为
+TCP连接是全双工连接的服务，因此每个方向上的连接必须单独关闭。当一端完成它的数据发送任务后就能发送一个
+FIN报文段（可以称之为终止连接请求，其实就是FIN标志位被设置为1）来终止这个方向上的连接。另一端收到一个
+FIN报文段，它必须通知应用层对方几经终止了那个方向的连接，发送FIN报文段通常是应用层进行关闭的结果。
+
+注意了：客户端发送一个FIN报文段只意味着在这一方向上没有数据流动，一个
+TCP连接在发送一个 FIN后仍能接收数据，但是在实际应用中只有很少的
+TCP应用程序这样做。
+
+"四次挥手"终止连接具体过程如下：
+
+.. figure:: media/tcpip006.png
+   :alt: tcpip006
+
+   tcpip006
+第一步：客户端发出一个FIN报文段主动进行关闭连接，此时报文段的FIN标志位为1，假设序号为C，一般来说ACK标志也会被置一，但确认序号字段是无效的。
+
+第二步：当服务器收到这个
+FIN报文段，它发回一个ACK报文段（此报文段是终止连接应答），确认序号为收到的序号加
+1（C+1），和SYN一样，一个FIN将占用一个序号，此时断开客户端->服务器的方向连接。
+
+第三步：服务器会向应用程序请求关闭与这个客户端的连接，接着服务器就会发送一个FIN报文段（这个报文段是服务器向客户端发出，请求终止连接），此时假设序号为D，ACK标志虽然也为1，但是确认序号字段是无效的。
+
+第四步：客户端返回一个ACK报文段来确认终止连接的请求，ACK标志置一，并将确认序号设置为收到序号加1（D+1），此时断开服务器->客户端的方向连接。
+
+TCP状态
+-------
+
+TCP协议根据连接时接收到报文的不同类型，采取相应动作也不同，还要处理各个状态的关系，如当收到握手报文时候、超时的时候、用户主动关闭的时候等都需要不一样的状态去采取不一样的处理。
+
+TCP协议的状态如下：
+
+-  LISTENING状态：提供某种服务，侦听远方TCP端口的连接请求，当提供的服务没有被连接时，处于LISTENING状态，端口是开放的，等待被连接。
+
+-  SYN_SENT
+   (客户端状态)：客户端调用connect()函数，将会发送一个SYN请求建立一个连接，在发送连接请求后等待匹配的连接请求，此时状态为SYN_SENT.
+
+-  SYN_RECEIVED
+   (服务端状态)：在收到和发送一个连接请求后，等待对方对连接请求的确认，当服务器收到客户端发送的同步信号时，将标志位ACK和SYN置1发送给客户端，此时服务器端处于SYN_RCVD状态，如果连接成功了就变为ESTABLISHED，正常情况下SYN_RCVD状态非常短暂。
+
+-  ESTABLISHED状态：这个状态是处于稳定连接状态，建立连接的TCP协议两端的主机都是处于这个状态，它们相互知道彼此的窗口大小、序列号、最大报文段等信息。
+
+-  FIN_WAIT_1与FIN_WAIT_2状态：处于这个状态一般都是单向请求终止连接，然后主机等待对方的回应，而如果对方产生应答，则主机状态转移为FIN_WAIT_2，此时{主机->对方}方向上的TCP连接就断开，但是{对方->主机}方向上的连接还是存在的。此处有一个注意的地方：如果主机处于FIN_WAIT_2状态，说明主机已经发出了FIN报文段，并且对方也已对它进行确认，除非主机是在实行半关闭状态，否则将等待对方主机的应用层处理关闭连接，因为对方已经意识到它已收到FIN报文段，它需要主机发一个
+   FIN
+   来关闭{对方->主机}方向上的连接。只有当另一端的进程完成这个关闭，主机这端才会从FIN_WAIT_2状态进入TIME_WAIT状态。否则这意味着主机这端可能永远保持这个FIN_WAIT_2状态，另一端的主机也将处于
+   CLOSE_WAIT状态，并一直保持这个状态直到应用层决定进行关闭。
+
+-  CLOSE-WAIT状态：等待从本地用户发来的连接中断请求
+   ，被动关闭端TCP接到FIN后，就发出ACK以回应FIN请求(它的接收也作为文件结束符传递给上层应用程序),并进入CLOSE_WAIT.
+
+-  TIME_WAIT状态：TIME_WAIT状态也称为
+   2MSL等待状态。每个具体TCP连接的实现必须选择一个TCP报文段最大生存时间MSL（Maximum
+   Segment
+   Lifetime），如IP数据报中的TTL字段，表示报文在网络中生存的时间，它是任何报文段被丢弃前在网络内的最长时间，这个时间是有限的，为什么需要等待呢？我们知道IP数据报是不可靠的，而TCP报文段是封装在IP数据报中，TCP协议必须保证发出的ACK报文段是正确被对方接收，
+   因此处于该状态的主机必须在这个状态停留最长时间为2倍的MSL，以防最后这个ACK丢失，因为TCP协议必须保证数据能准确送达目的地。
+
+讲了那么多理论，下面就结合图文来详解一下TCP协议在建立连接与终止连接的时候所有的状态转移处理是怎么样的，具体见：
+
+.. figure:: media/tcpip007.png
+   :alt: tcpip007
+
+   tcpip007
+对图中的补充说明（很重要，要牢牢记住）：
+
+-  虚线：表示服务器的状态转移。
+-  实线：表示客户端的状态转移。
+-  图中所有"关闭"、"打开"都是应用程序主动处理。
+-  图中所有的"超时"都是内核超时处理。
+
+**三次握手过程：**
+
+-  图中(7)：服务器的应用程序主动使服务器进入监听状态，等待客户端的连接请求。
+-  图中(1)：首先客户端的应用程序会主动发起连接，发送SNY报文段给服务器，在发送之后就进入SYN_SENT状态等待服务器的SNY
+   ACK报文段进行确认，如果在指定超时时间内服务器不进行应答确认，那么客户端将关闭连接。
+-  图中(8)：处于监听状态的服务器收到客户端的连接请求（SNY报文段），那么服务器就返回一个SNY
+   ACK报文段应答客户端的响应，并且服务器进入SYN_RCVD状态。
+-  图中(1)：如果客户端收到了服务器的SNY
+   ACK报文段，那么就进入ESTABLISHED稳定连接状态，并向服务器发送一个ACK报文段。
+-  图中(9)：同时，服务器收到来自客户端的ACK报文段，表示连接成功，进入ESTABLISHED稳定连接状态，这正是我们建立连接的三次握手过程。
+
+**四次挥手过程：**
+
+-  图中(3)：一般来说，都是客户端主动发送一个FIN报文段来终止连接，此时客户端从ESTABLISHED稳定连接状态转移为FIN_WAIT_1状态，并且等待来自服务器的应答确认。
+-  图中(10)：服务器收到FIN报文段，知道客户端请求终止连接，那么将返回一个ACK报文段到客户端确认终止连接，并且服务器状态由稳定状态转移为CLOSE_WAIT等待终止连接状态。
+-  图中(4)：客户端收到确认报文段后，进入FIN_WAIT_2状态，等待来自服务器的主动请求终止连接，此时 ``{客户端->服务器}`` 方向上的连接已经断开。
+-  图中(11)：一般来说，当客户端终止了连接之后，服务器也会终止 ``{客户端->服务器}`` 方向上的连接，因此服务器的原因程序会主动关闭该方向上的连接，发送一个FIN报文段给客户端。
+-  图中(5)：处于FIN_WAIT_2的客户端收到FIN报文段后，发送一个ACK报文段给服务器。
+-  图中(12)：服务器收到ACK报文段，就直接关闭，此时 ``{客户端->服务器}`` 方向上的连接已经终止，进入CLOSED状态。
+-  图中(6)：客户端还会等待2MSL，以防ACK报文段没被服务器收到，这就是四次挥手的全部过程。
+   注意：对于图中(13)(14)(15)的这些状态都是一些比较特殊的状态，我们暂时就不讲解了，总的来说都是一样的。
+
+    对TCP协议的简单讲解就到这里，上面讲解了那么多内容，其实是非常非常简单非常非常基础的，具体还有更多TCP协议的特点就去看对应的专业书籍。
diff --git a/documentation/system_programing/thread.rst b/documentation/system_programing/thread.rst
new file mode 100644
index 0000000000000000000000000000000000000000..0a63bac6d318c2b1799dd738d1c45e38e66ab5df
--- /dev/null
+++ b/documentation/system_programing/thread.rst
@@ -0,0 +1,390 @@
+线程
+====
+
+线程和进程
+----------
+
+从很多Linux的书籍我们都可以这样子描述进程和线程的：进程是资源管理的最小单位，线程是程序执行的最小单位。
+
+没错，这些确实是线程与进程之间的区别，这个描述非常言简意赅，在操作系统设计上，从进程演化出线程，最主要的目的就是减小进程上下文切换开销，这又是怎么一回事呢？在前面的文章已经提到，进程是资源管理的最小单位，那么每个进程都拥有自己的数据段、代码段和堆栈段，这必然就造成了进程在进行切换时都需要有比较复杂的上下文切换等动作，因为要保存当前进程上下文的内容，还要恢复另一个进程的上下文，如果是经常切换进程的话，这样子的开销就过于庞大，因为在进程切换上下文时，需要重新映射虚拟地址空间、进出OS内核、寄存器切换，还会干扰处理器的缓存机制，因此为了进一步减少CPU在进程切换时的额外开销，因此Linux进程演化出了另一个概念——线程。
+
+线程是操作系统能够调度和执行的基本单位，在Linux中也被称之为轻量级进程。在Linux系统中，一个进程至少需要一个线程作为它的指令执行体，进程管理着资源（比如cpu、内存、文件等等），而将线程分配到某个cpu上执行。一个进程可以拥有多个线程，它还可以同时使用多个cpu来执行各个线程，以达到最大程度的并行，提高工作的效率；同时，即使是在单cpu的机器上，也依然可以采用多线程模型来设计程序，使设计更简洁、功能更完备，程序的执行效率也更高。
+
+从上面的这些概念我们不难得出一个非常重要的结论：线程的本质是一个进程内部的一个控制序列，它是进程里面的东西，一个进程可以拥有一个进程或者多个进程，那么它们的关系就如图所示：
+
+.. figure:: media/thread001.png
+   :alt: 进程与线程
+
+   进程与线程
+回顾一下进程相关的知识：当进程执行fork()函数创建一个进程时，将创建出该进程的一份新副本。这个新进程拥有自己的变量和自己的PID，它的执行几乎完全独立于父进程，这样子得到一个新的进程开销是非常大的。而当在进程中创建一个新线程时，新的执行线程将拥有自己的栈，但与它的创建者共享全局变量、文件描述符、信号处理函数和当前目录状态，也就是说，它只使用当前进程的资源，而不是产生当前进程的副本。
+
+Linux系统中的每个进程都有独立的地址空间，一个进程崩溃后，在系统的保护模式下并不会对系统中其它进程产生影响，而线程只是一个进程内部的一个控制序列，当进程崩溃后，线程也随之崩溃，所以一个多进程的程序要比多线程的程序健壮，但在进程切换时，耗费资源较大，效率要差一些。但在某些场合下对于一些要求同时进行并且又要共享某些变量的并发操作，只能用线程，不能用进程。
+
+**总的来说：**
+
+-  一个程序至少有一个进程,一个进程至少有一个线程。
+-  线程使用的资源是进程的资源，进程崩溃线程也随之崩溃。
+-  线程的上下文切换，要比进程更加快速，因为本质上，线程很多资源都是共享进程的，所以切换时，需要保存和切换的项是很少的。
+
+创建线程
+--------
+
+在讲解线程编程之前，先了解一个标准：可移植操作系统接口（英语：Portable
+Operating System
+Interface，缩写为POSIX），POSIX是IEEE为要在各种UNIX操作系统上运行软件，而定义API的一系列互相关联的标准的总称，其正式称呼为IEEE
+Std 1003，而国际标准名称为ISO/IEC
+9945。此标准源于一个大约开始于1985年的项目。POSIX这个名称是由理查德·斯托曼（RMS）应IEEE的要求而提议的一个易于记忆的名称。它基本上是Portable
+Operating System
+Interface（可移植操作系统接口）的缩写，而X则表明其对Unix API的传承。
+
+    注：以上介绍来自维基百科：https://zh.wikipedia.org/wiki/POSIX
+
+在Linux系统下的多线程遵循POSIX标准，而其中的一套常用的线程库是 pthread
+，它是一套通用的线程库，是由 POSIX
+提出的，因此具有很好的可移植性，我们学习多线程编程，就是使用它，必须包含以下头文件：
+
+.. code:: c
+
+        #include <pthread.h>
+
+除此之外在链接时需要使用库libpthread.a。因为pthread的库不是Linux系统的库，所以在编译时要加上
+-lpthread 选项。
+
+**pthread_create()**
+
+pthread_create()函数是用于创建一个线程的，创建线程实际上就是确定调用该线程函数的入口点，在线程创建后，就开始运行相关的线程函数。若线程创建成功，则返回0。若线程创建失败，则返回对应的错误代码。
+
+**函数原型：**
+
+.. code:: c
+
+        int pthread_create(pthread_t *thread, const pthread_attr_t *attr,
+                            void *(*start_routine) (void *), void *arg);
+
+**参数：**
+
+-  thread：指向线程标识符的指针。
+-  attr：设置线程属性。
+-  start_routine：start_routine是一个函数指针，指向要运行的线程入口。
+-  运行线程时传入的参数。
+
+线程属性
+--------
+
+Linux中线程属性结构如下:
+
+.. code:: c
+
+    typedef struct
+    {
+        int                   etachstate;      //线程的分离状态
+        int                   schedpolicy;     //线程调度策略
+        structsched_param     schedparam;      //线程的调度参数
+        int                   inheritsched;    //线程的继承性
+        int                   scope;           //线程的作用域
+        size_t                guardsize;       //线程栈末尾的警戒缓冲区大小
+        int                   stackaddr_set;   //线程的栈设置
+        void*                 stackaddr;       //线程栈的位置
+        size_t                stacksize;       //线程栈的大小
+    }pthread_attr_t;
+
+注意：因为pthread并非Linux系统的默认库，而是POSIX线程库。在Linux中将其作为一个库来使用，因此加上
+-lpthread（或-pthread）以显式指定链接该库。函数在执行错误时的错误信息将作为返回值返回，并不修改系统全局变量errno，当然也无法使用perror()打印错误信息。
+
+线程的属性非常多，而且其属性值不能直接设置，须使用相关函数进行操作，线程属性主要包括如下属性：作用域（scope）、栈大小（stack
+size）、栈地址（stack
+address）、优先级（priority）、分离的状态（detached
+state）、调度策略和参数（scheduling policy and
+parameters）。默认的属性为非绑定、非分离、1M的堆栈大小、与父进程同样级别的优先级。下面简单讲解一下与线程属性相关的API接口：
+
++------------------------------------+----------------------------------------+
+| API                                | 描述                                   |
++====================================+========================================+
+| pthread_attr_init()                | 初始化一个线程对象的属性               |
++------------------------------------+----------------------------------------+
+| pthread_attr_destroy()             | 销毁一个线程属性对象                   |
++------------------------------------+----------------------------------------+
+| pthread_attr_getaffinity_np()      | 获取线程间的CPU亲缘性                  |
++------------------------------------+----------------------------------------+
+| pthread_attr_setaffinity_np()      | 设置线程的CPU亲缘性                    |
++------------------------------------+----------------------------------------+
+| pthread_attr_getdetachstate()      | 获取线程分离状态属性                   |
++------------------------------------+----------------------------------------+
+| pthread_attr_setdetachstate()      | 修改线程分离状态属性                   |
++------------------------------------+----------------------------------------+
+| pthread_attr_getguardsize()        | 获取线程的栈保护区大小                 |
++------------------------------------+----------------------------------------+
+| pthread_attr_setguardsize()        | 设置线程的栈保护区大小                 |
++------------------------------------+----------------------------------------+
+| pthread_attr_getscope()            | 获取线程的作用域                       |
++------------------------------------+----------------------------------------+
+| pthread_attr_setscope()            | 设置线程的作用域                       |
++------------------------------------+----------------------------------------+
+| pthread_attr_getstack()            | 获取线程的堆栈信息（栈地址和栈大小）   |
++------------------------------------+----------------------------------------+
+| pthread_attr_setstack()            | 设置线程堆栈区                         |
++------------------------------------+----------------------------------------+
+| pthread_attr_getstacksize()        | 获取线程堆栈大小                       |
++------------------------------------+----------------------------------------+
+| pthread_attr_setstacksize()        | 设置线程堆栈大小                       |
++------------------------------------+----------------------------------------+
+| pthread_attr_getschedpolicy()      | 获取线程的调度策略                     |
++------------------------------------+----------------------------------------+
+| pthread_attr_setschedpolicy()      | 设置线程的调度策略                     |
++------------------------------------+----------------------------------------+
+| pthread_attr_setschedparam()       | 获取线程的调度优先级                   |
++------------------------------------+----------------------------------------+
+| pthread_attr_getschedparam()       | 设置线程的调度优先级                   |
++------------------------------------+----------------------------------------+
+| pthread_attr_getinheritsched()     | 获取线程是否继承调度属性               |
++------------------------------------+----------------------------------------+
+| pthread_attr_getinheritsched()     | 设置线程是否继承调度属性               |
++------------------------------------+----------------------------------------+
+
+    当然啦，如果不是特别需要的话，可以不需要考虑线程相关属性的，使用默认的属性即可。
+
+初始化一个线程对象的属性
+~~~~~~~~~~~~~~~~~~~~~~~~
+
+**函数原型：**
+
+.. code:: c
+
+        int pthread_attr_init(pthread_attr_t *attr);
+
+若函数调用成功返回0，否则返回对应的错误代码。
+
+-  attr：指向一个线程属性的指针
+
+销毁一个线程属性对象
+~~~~~~~~~~~~~~~~~~~~
+
+销毁一个线程属性对象，经过pthread_attr_destroy()函数销毁初始化之后的pthread_attr_t结构被pthread_create()函数调用时将会返回错误。
+
+**函数原型：**
+
+.. code:: c
+
+        int pthread_attr_destroy(pthread_attr_t *attr);
+
+若函数调用成功返回0，否则返回对应的错误代码。
+
+-  attr：指向一个线程属性的指针
+
+线程的分离状态
+--------------
+
+什么是线程的分离状态呢？在任何一个时间点上，线程是可结合的（joinable），或者是分离的（detached）。一个可结合的线程能够被其他线程收回其资源和杀死；在被其他线程回收之前，它的存储器资源（如栈）是不释放的。相反，一个分离的线程是不能被其他线程回收或杀死的，它的存储器资源在它终止时由系统自动释放。
+
+总而言之：线程的分离状态决定一个线程以什么样的方式来终止自己。
+
+进程中的线程可以调用以下函数来等待某个线程的终止，获得该线程的终止状态，并收回所占的资源，如果对线程的返回状态不感兴趣，可以将rval_ptr设置为NULL。
+
+.. code:: c
+
+        int pthread_join(pthread_t tid, void **rval_ptr)；
+
+除此之外线程也可以调用以下函数将此线程设置为分离状态，设置为分离状态的线程在线程结束时，操作系统会自动收回它所占的资源。设置为分离状态的线程，不能再调用pthread_join()等待其结束。
+
+.. code:: c
+
+        int pthread_detach(pthread_t tid)；
+
+如果一个线程是可结合的，意味着这条线程在退出时不会自动释放自身资源，而会成为僵尸线程，同时意味着该线程的退出值可以被其他线程获取。因此，如果不需要某条线程的退出值的话，那么最好将线程设置为分离状态，以保证该线程不会成为僵尸线程。
+
+如果在创建线程时就知道不需要了解线程的终止状态，那么可以通过修改pthread_attr_t结构中的detachstate属性，让线程以分离状态启动，调用函数如下：
+
+.. code:: c
+
+        int pthread_attr_setdetachstate(pthread_attr_t *attr, int detachstate)；
+
+如果想要获取某个线程的分离状态，那么可以通过以下函数：
+
+.. code:: c
+
+        int pthread_attr_getdetachstate(const pthread_attr_t *attr, int *detachstate);
+
+若函数调用成功返回0，否则返回对应的错误代码。
+
+**参数：**
+
+-  attr：指向一个线程属性的指针。
+-  detachstate：如果值为PTHREAD_CREATE_DETACHED，则表示线程是分离状态，如果值为PTHREAD_CREATE_JOINABLE则表示线程是结合状态。
+
+线程的调度策略
+--------------
+
+POSIX 标准指定了三种调度策略：
+
+-  分时调度策略 (SCHED_OTHER)。
+-  实时调度策略，先进先出方式调度(SCHED_FIFO)。
+-  实时调度策略 ，时间片轮转方式调度(SCHED_RR)。
+
+这个属性的默认值为SCHED_OTHER。另外两种调度方式只能用于以超级用户权限运行的进程，因为它们都具备实时调度的功能，但在行为上略有区别。
+
+SCHED_FIFO
+是基于队列的调度程序，对于每个优先级都会使用不同的队列，先进入队列的线程能优先得到运行，线程会一直占用CPU，直到有更高优先级任务到达或自己主动放弃CPU使用权。SCHED_RR
+与 FIFO
+相似，不同的是前者的每个线程都有一个执行时间配额，当采用SHCED_RR策略的线程的时间片用完，系统将重新分配时间片，并将该线程置于就绪队列尾，并且切换线程，放在队列尾保证了所有具有相同优先级的RR线程的调度公平。
+
+与调度相关的API接口如下：
+
+.. code:: c
+
+        int pthread_attr_setinheritsched(pthread_attr_t *attr, int inheritsched);
+        int pthread_attr_getinheritsched(const pthread_attr_t *attr, int *inheritsched);
+
+        int pthread_attr_setschedpolicy(pthread_attr_t *attr, int policy);
+        int pthread_attr_getschedpolicy(const pthread_attr_t *attr, int *policy);
+
+若函数调用成功返回0，否则返回对应的错误代码。
+
+**参数：**
+
+-  attr：指向一个线程属性的指针。
+-  inheritsched：线程是否继承调度属性，可选值分别为
+
+-  PTHREAD_INHERIT_SCHED：调度属性将继承于创建的线程，attr中设置的调度属性将被忽略。
+-  PTHREAD_EXPLICIT_SCHED：调度属性将被设置为attr中指定的属性值。
+
+-  policy：可选值为线程的三种调度策略，SCHED_OTHER、SCHED_FIFO、SCHED_RR。
+
+线程的优先级
+------------
+
+顾名思义，线程优先级就是这个线程得到运行的优先顺序，在Linux系统中，优先级数值越小，线程优先级越高，Linux根据线程的优先级对线程进行调度，遵循线程属性中指定的调度策略。
+
+获取、设置线程静态优先级（staticpriority）可以使用以下函数，注意，是静态优先级，当线程的调度策略为SCHED_OTHER时，其静态优先级必须设置为0。该调度策略是Linux系统调度的默认策略，处于0优先级别的这些线程按照动态优先级被调度，之所以被称为"动态"，是因为它会随着线程的运行，根据线程的表现而发生改变，而动态优先级起始于线程的nice值，且每当一个线程已处于就绪态但被调度器调度无视时，其动态优先级会自动增加一个单位，这样能保证这些线程竞争CPU的公平性。
+
+线程的静态优先级之所以被称为"静态"，是因为只要你不强行使用相关函数修改它，它是不会随着线程的执行而发生改变，静态优先级决定了实时线程的基本调度次序，它们是在实时调度策略中使用的。
+
+.. code:: c
+
+        int pthread_attr_setschedparam(pthread_attr_t *attr, const struct sched_param *param);
+        int pthread_attr_getschedparam(const pthread_attr_t *attr, struct sched_param *param);
+
+**参数：**
+
+-  attr：指向一个线程属性的指针。
+-  param：静态优先级数值。
+
+线程优先级有以下特点：
+
+-  新线程的优先级为默认为0。
+-  新线程不继承父线程调度优先级(PTHREAD_EXPLICIT_SCHED)
+-  当线程的调度策略为SCHED_OTHER时，不允许修改线程优先级，仅当调度策略为实时（即SCHED_RR或SCHED_FIFO）时才有效，并可以在运行时通过pthread_setschedparam()函数来改变，默认为0。
+
+线程栈
+------
+
+线程栈是非常重要的资源，它可以存放函数形参、局部变量、线程切换现场寄存器等数据，在前文我们也说过了，线程使用的是进程的内存空间，那么一个进程有n个线程，默认的线程栈大小是1M，那么就有可能导致进程的内存空间是不够的，因此在有多线程的情况下，我们可以适当减小某些线程栈的大小，防止进程的内存空间不足，而某些线程可能需要完成很大量的工作，或者线程调用的函数会分配很大的局部变量，亦或是函数调用层次很深时，需要的栈空间可能会很大，那么也可以增大线程栈的大小。
+
+获取、设置线程栈大小可以使用以下函数：
+
+.. code:: c
+
+        int pthread_attr_setstacksize(pthread_attr_t *attr, size_t stacksize);
+        int pthread_attr_getstacksize(const pthread_attr_t *attr, size_t *stacksize);
+
+**参数：**
+
+-  attr：指向一个线程属性的指针。
+-  stacksize：线程栈的大小。
+
+线程退出
+--------
+
+在线程创建后，系统就开始运行相关的线程函数，在该函数运行完之后，该线程也就退出了，这是线程的一种隐式退出的方法，这与我们进程的退出差不多，进程完成工作后就会退出。而另一种退出线程的方法是使用pthread_exit()函数，让线程显式退出，这是线程的主动行为。这里要注意的是，在使用线程函数时，不能随意使用exit()退出函数来进行出错处理，这是因为exit()函数的作用是使调用进程终止，而一个进程往往包含多个线程，因此，在使用exit()之后，该进程中的所有线程都会被退出，因此在线程中只能调用线程退出函数pthread_exit()而不是调用进程退出函数exit()。
+
+函数原型：
+
+.. code:: c
+
+    void pthread_exit(void *retval);
+
+**参数：**
+
+-  retval：如果retval不为空，则会将线程的退出值保存到retval中，如果不关心线程的退出值，形参为NULL即可。
+
+一般情况下，进程中各个线程的运行是相互独立的，线程的终止并不会相互通知，也不会影响其他的线程，终止的线程所占用的资源不会随着线程的终止而归还系统，而是仍为线程所在的进程持有，这是因为一个进程中的多个线程是共享数据段的。从前面的文章我们知道进程之间可以使用wait()系统调用来等待其他进程结束一样，线程也有类似的函数：
+
+.. code:: c
+
+        int pthread_join(pthread_t tid, void **rval_ptr)；
+
+如果某个线程想要等待另一个线程退出，并且获取它的退出值，那么就可以使用pthread_join()函数完成，以阻塞的方式等待thread指定的线程结束，当函数返回时，被等待线程的资源将被收回，如果进程已经结束，那么该函数会立即返回。并且thread指定的线程必须是可结合状态的，该函数执行成功返回0，否则返回对应的错误代码。
+
+**参数：**
+
+-  thread: 线程标识符，即线程ID，标识唯一线程。
+-  retval: 用户定义的指针，用来存储被等待线程的返回值。
+
+需要注意的是一个可结合状态的线程所占用的内存仅当有线程对其执行立pthread_join()后才会释放，因此为了避免内存泄漏，所有线程的终止时，要么已被设为DETACHED，要么使用pthread_join()来回收资源。
+
+线程实验
+--------
+
+我们在日常使用的情况下，若非特别需要，几乎不需要修改线程的属性的，我们今天做一个线程的实验，实验中创建一个进程，线程的属性是默认属性，在线程执行完毕后就退出，代码如下：
+
+.. code:: c
+
+    #include <unistd.h>
+    #include <fcntl.h>
+    #include <stdio.h>
+    #include <stdlib.h>
+    #include <pthread.h>
+
+    void *test_thread(void *arg)
+    {
+        int num = (unsigned long long)arg; /** sizeof(void*) == 8 and sizeof(int) == 4 (64 bits) */
+
+        printf("arg is %d\n", num);
+
+        pthread_exit(NULL);
+    }
+
+
+    int main(void)
+    {
+        pthread_t thread;
+        void *thread_return;
+        int arg = 520;
+        int res;
+
+        printf("start create thread\n");
+
+        res = pthread_create(&thread, NULL, test_thread, (void*)(unsigned long long)(arg));
+        if(res != 0)
+        {
+            printf("create thread fail\n");
+            exit(res);
+        }
+
+        printf("create treads success\n");
+        printf("waiting for threads to finish...\n");
+
+
+        res = pthread_join(thread, &thread_return);
+        if(res != 0)
+        {
+            printf("thread exit fail\n");
+            exit(res);
+        }
+
+        printf("thread exit ok\n");
+
+        return 0;
+    }
+
+进入 ``system_programing/thread`` 目录下执行make编译源码，然后运行，实验现象如下：
+
+.. code:: bash
+
+    ➜  thread git:(master) ✗ ./targets 
+
+    start create thread
+    create treads success
+    waiting for threads to finish...
+    arg is 520
+    thread exit ok
+
diff --git a/shell_tools/build-alsa.sh b/shell_tools/build-alsa.sh
new file mode 100755
index 0000000000000000000000000000000000000000..36fb3b138c288d7c24bdb03ee913b4641cbeca26
--- /dev/null
+++ b/shell_tools/build-alsa.sh
@@ -0,0 +1,96 @@
+#!/bin/sh
+
+# set -v 
+
+HOST=arm-linux-gnueabihf
+SCRIPT_PATH=$(pwd)
+
+#修改源码包解压后的名称
+MAJOR_NAME=alsa-lib
+
+#修改需要下载的源码前缀和后缀
+OPENSRC_VER_PREFIX=1.2
+OPENSRC_VER_SUFFIX=.2
+
+PACKAGE_NAME=${MAJOR_NAME}-${OPENSRC_VER_PREFIX}${OPENSRC_VER_SUFFIX}
+
+#定义压缩包名称
+COMPRESS_PACKAGE=${PACKAGE_NAME}.tar.bz2
+
+#定义编译后安装--生成的文件,文件夹位置路径
+INSTALL_PATH=/opt/${PACKAGE_NAME}
+
+#添加交叉编译工具链路径
+# CROSS_CHAIN_PREFIX=/opt/arm-gcc/bin/arm-linux-gnueabihf
+CROSS_CHAIN_PREFIX=/opt/gcc-arm-linux-gnueabihf-8.3.0/bin/arm-linux-gnueabihf
+
+#无需修改--下载地址
+DOWNLOAD_LINK=ftp://ftp.alsa-project.org/pub/lib/${COMPRESS_PACKAGE}
+
+#下载源码包
+do_download_src () {
+   echo "\033[1;33mstart download ${PACKAGE_NAME}...\033[0m"
+   
+   if [ ! -f "${COMPRESS_PACKAGE}" ];then
+      if [ ! -d "${PACKAGE_NAME}" ];then
+         wget -c ${DOWNLOAD_LINK}
+      fi
+   fi
+
+   echo "\033[1;33mdone...\033[0m"
+}
+
+#解压源码包
+do_tar_package () {
+   echo "\033[1;33mstart unpacking the ${PACKAGE_NAME} package ...\033[0m"
+   if [ ! -d "${PACKAGE_NAME}" ];then
+      tar -xf ${COMPRESS_PACKAGE}
+   fi
+   echo "\033[1;33mdone...\033[0m"
+   cd ${PACKAGE_NAME}
+}
+
+#配置选项
+do_configure () {
+   echo "\033[1;33mstart configure ${PACKAGE_NAME}...\033[0m"
+
+   mkdir -p ${INSTALL_PATH}/config
+   mkdir -p ${INSTALL_PATH}/plugin
+
+   export CC=${CROSS_CHAIN_PREFIX}-gcc 
+   
+   ./configure \
+   --prefix=${INSTALL_PATH} \
+   --host=${HOST} \
+   # --enable-static \
+   --enable-shared \
+   --disable-python \
+   --with-configdir=${INSTALL_PATH}/config \
+   --with-plugindir=${INSTALL_PATH}/plugin
+
+   echo "\033[1;33mdone...\033[0m"
+}
+
+
+#编译并且安装
+do_make_install () {
+   echo "\033[1;33mstart make and install ${PACKAGE_NAME} ...\033[0m"
+   make && make install
+   echo "\033[1;33mdone...\033[0m"
+}
+
+#删除下载的文件
+do_delete_file () {
+   cd ${SCRIPT_PATH}
+   if [ -f "${PACKAGE_NAME}" ];then
+      sudo rm -f ${PACKAGE_NAME}
+   fi
+}
+
+do_download_src
+do_tar_package
+do_configure
+do_make_install
+# do_delete_file
+
+exit $?
diff --git a/shell_tools/build-gcc.sh b/shell_tools/build-gcc.sh
new file mode 100755
index 0000000000000000000000000000000000000000..95298be89ff759216913e4063d4c809f40800b3c
--- /dev/null
+++ b/shell_tools/build-gcc.sh
@@ -0,0 +1,64 @@
+#!/bin/sh
+
+# set -v 
+
+HOST=arm-linux-gnueabihf
+SCRIPT_PATH=$(pwd)
+
+#修改源码包解压后的名称
+MAJOR_NAME=gcc-arm-linux-gnueabihf
+
+#修改需要下载的源码前缀和后缀
+OPENSRC_VER_PREFIX=8.3
+OPENSRC_VER_SUFFIX=.0
+
+PACKAGE_NAME=${MAJOR_NAME}-${OPENSRC_VER_PREFIX}${OPENSRC_VER_SUFFIX}
+
+#定义压缩包名称
+COMPRESS_PACKAGE=gcc-arm-8.3-2019.03-x86_64-arm-linux-gnueabihf.tar.xz
+
+#定义编译后安装--生成的文件,文件夹位置路径
+INSTALL_PATH=/opt/${PACKAGE_NAME}
+
+#无需修改--下载地址
+DOWNLOAD_LINK=https://developer.arm.com/-/media/Files/downloads/gnu-a/8.3-2019.03/binrel/${COMPRESS_PACKAGE}
+
+#下载源码包
+do_download_src () {
+   echo "\033[1;33mstart download ${COMPRESS_PACKAGE}...\033[0m"
+
+   if [ ! -f "${COMPRESS_PACKAGE}" ];then
+      if [ ! -d "${PACKAGE_NAME}" ];then
+         wget -c ${DOWNLOAD_LINK}
+      fi
+   fi
+   
+   echo "\033[1;33mdone...\033[0m"
+}
+
+#解压源码包
+do_tar_package () {
+   echo "\033[1;33mstart unpacking the ${PACKAGE_NAME} package ...\033[0m"
+
+   mkdir -p ${INSTALL_PATH}
+
+   if [ ! -d "${PACKAGE_NAME}" ];then
+      tar -xf ${COMPRESS_PACKAGE} -C ${INSTALL_PATH} --strip-components=1 
+   fi
+
+   echo "\033[1;33mdone...\033[0m"
+}
+
+#删除下载的文件
+do_delete_file () {
+   cd ${SCRIPT_PATH}
+   if [ -f "${PACKAGE_NAME}" ];then
+      sudo rm -f ${PACKAGE_NAME}
+   fi
+}
+
+do_download_src
+do_tar_package
+# do_delete_file
+
+exit $?
diff --git a/shell_tools/build-qt.sh b/shell_tools/build-qt.sh
new file mode 100755
index 0000000000000000000000000000000000000000..a24cef1f2e37afa74893f529b137e7f68a88c427
--- /dev/null
+++ b/shell_tools/build-qt.sh
@@ -0,0 +1,184 @@
+#!/bin/sh
+
+# set -v 
+
+PLATFORM=my-linux-arm-qt
+SCRIPT_PATH=$(pwd)
+
+#修改源码包解压后的名称
+MAJOR_NAME=qt-everywhere-src
+
+#修改需要下载的源码前缀和后缀
+OPENSRC_VER_PREFIX=5.14
+OPENSRC_VER_SUFFIX=.1
+
+#添加tslib交叉编译的动态库文件和头文件路径
+TSLIB_LIB=/opt/tslib-1.21/lib
+TSLIB_INC=/opt/tslib-1.21/include
+
+#添加alsa交叉编译的动态库文件和头文件路径
+ALSA_LIB=/opt/alsa-lib-1.2.2/lib
+ALSA_INC=/opt/alsa-lib-1.2.2/include
+
+#修改源码包解压后的名称
+PACKAGE_NAME=${MAJOR_NAME}-${OPENSRC_VER_PREFIX}${OPENSRC_VER_SUFFIX}
+
+#定义编译后安装--生成的文件,文件夹位置路径
+INSTALL_PATH=/opt/${PACKAGE_NAME}
+
+#添加交叉编译工具链路径
+# CROSS_CHAIN_PREFIX=/opt/arm-gcc/bin/arm-linux-gnueabihf
+CROSS_CHAIN_PREFIX=/opt/gcc-arm-linux-gnueabihf-8.3.0/bin/arm-linux-gnueabihf
+
+#定义压缩包名称
+COMPRESS_PACKAGE=${PACKAGE_NAME}.tar.xz
+
+#无需修改--自动组合下载地址
+OPENSRC_VER=${OPENSRC_VER_PREFIX}${OPENSRC_VER_SUFFIX}
+# DOWNLOAD_LINK=http://download.qt.io/new_archive/qt/${OPENSRC_VER_PREFIX}/${OPENSRC_VER}/single/${COMPRESS_PACKAGE}
+DOWNLOAD_LINK=http://download.qt.io/official_releases/qt/${OPENSRC_VER_PREFIX}/${OPENSRC_VER}/single/${COMPRESS_PACKAGE}
+
+#无需修改--自动组合平台路径
+CONFIG_PATH=${SCRIPT_PATH}/${PACKAGE_NAME}/qtbase/mkspecs/${PLATFORM}
+
+#无需修改--自动组合配置平台路径文件
+CONFIG_FILE=${CONFIG_PATH}/qmake.conf
+
+#下载源码包
+do_download_src () {
+   echo "\033[1;33mstart download ${PACKAGE_NAME}...\033[0m"
+
+   if [ ! -f "${COMPRESS_PACKAGE}" ];then
+      if [ ! -d "${PACKAGE_NAME}" ];then
+         wget -c ${DOWNLOAD_LINK}
+      fi
+   fi
+
+   echo "\033[1;33mdone...\033[0m"
+}
+
+#解压源码包
+do_tar_package () {
+   echo "\033[1;33mstart unpacking the ${PACKAGE_NAME} package ...\033[0m"
+   if [ ! -d "${PACKAGE_NAME}" ];then
+      tar -xf ${COMPRESS_PACKAGE}
+   fi
+   echo "\033[1;33mdone...\033[0m"
+   cd ${PACKAGE_NAME}
+}
+
+#安装依赖项
+do_install_config_dependent () {
+   sudo apt install g++ make qt3d5-dev-tools -y
+   sudo apt install qml-module-qtquick-xmllistmodel -y
+   sudo apt install qml-module-qtquick-virtualkeyboard qml-module-qtquick-shapes qml-module-qtquick-privatewidgets qml-module-qtquick-dialogs qml-module- qt-labs-calendar qml -y
+   sudo apt install libqt53dquickscene2d5 libqt53dquickrender5 libqt53dquickinput5 libqt53dquickextras5 libqt53dquickanimation5 libqt53dquick5 -y
+   sudo apt install qtdeclarative5-dev qml-module-qtwebengine qml-module-qtwebchannel qml-module-qtmultimedia qml-module-qtaudioengine -y
+}
+
+#修改配置平台
+do_config_before () {
+   echo "\033[1;33mstart configure platform...\033[0m"
+
+if [ ! -d "${CONFIG_PATH}" ];then
+   cp -a ${SCRIPT_PATH}/${PACKAGE_NAME}/qtbase/mkspecs/linux-arm-gnueabi-g++ ${CONFIG_PATH}
+fi
+
+   echo "#" > ${CONFIG_FILE}
+   echo "# qmake configuration for building with arm-linux-gnueabi-g++" >> ${CONFIG_FILE}
+   echo "#" >> ${CONFIG_FILE}
+   echo "" >> ${CONFIG_FILE}
+   echo "MAKEFILE_GENERATOR      = UNIX" >> ${CONFIG_FILE}
+   echo "CONFIG                 += incremental" >> ${CONFIG_FILE}
+   echo "QMAKE_INCREMENTAL_STYLE = sublib" >> ${CONFIG_FILE}
+   echo "" >> ${CONFIG_FILE}
+   echo "include(../common/linux.conf)" >> ${CONFIG_FILE}
+   echo "include(../common/gcc-base-unix.conf)" >> ${CONFIG_FILE}
+   echo "include(../common/g++-unix.conf)" >> ${CONFIG_FILE}
+   echo "" >> ${CONFIG_FILE}
+   echo "# modifications to g++.conf" >> ${CONFIG_FILE}
+   echo "QMAKE_CC                = ${CROSS_CHAIN_PREFIX}-gcc -lts" >> ${CONFIG_FILE}
+   echo "QMAKE_CXX               = ${CROSS_CHAIN_PREFIX}-g++ -lts" >> ${CONFIG_FILE}
+   echo "QMAKE_LINK              = ${CROSS_CHAIN_PREFIX}-g++ -lts" >> ${CONFIG_FILE}
+   echo "QMAKE_LINK_SHLIB        = ${CROSS_CHAIN_PREFIX}-g++ -lts" >> ${CONFIG_FILE}
+   echo "" >> ${CONFIG_FILE}
+   echo "# modifications to linux.conf" >> ${CONFIG_FILE}
+   echo "QMAKE_AR                = ${CROSS_CHAIN_PREFIX}-ar cqs" >> ${CONFIG_FILE}
+   echo "QMAKE_OBJCOPY           = ${CROSS_CHAIN_PREFIX}-objcopy" >> ${CONFIG_FILE}
+   echo "QMAKE_NM                = ${CROSS_CHAIN_PREFIX}-nm -P" >> ${CONFIG_FILE}
+   echo "QMAKE_STRIP             = ${CROSS_CHAIN_PREFIX}-strip" >> ${CONFIG_FILE}
+   echo "load(qt_config)" >> ${CONFIG_FILE}
+   echo "" >> ${CONFIG_FILE}
+   echo "QMAKE_INCDIR=${TSLIB_INC}" >> ${CONFIG_FILE}
+   echo "QMAKE_LIBDIR=${TSLIB_LIB}" >> ${CONFIG_FILE}
+
+   cat ${CONFIG_FILE}
+   echo "\033[1;33mdone...\033[0m"
+}
+
+#配置选项
+do_configure () {
+   echo "\033[1;33mstart configure ${PACKAGE_NAME}...\033[0m"
+
+   export CC="${CROSS_CHAIN_PREFIX}-gcc"
+   export CXX="${CROSS_CHAIN_PREFIX}-g++" 
+
+   ./configure \
+   -prefix ${INSTALL_PATH} \
+   -xplatform ${PLATFORM} \
+   -release \
+   -opensource \
+   -confirm-license \
+   -no-openssl \
+   -no-opengl \
+   -no-xcb \
+   -no-eglfs \
+   -no-compile-examples \
+   -no-pkg-config \
+   -skip qtquickcontrols \
+   -skip qtquickcontrols2 \
+   -skip qtsensors \
+   -skip qtdoc \
+   -skip qtwayland \
+   -skip qt3d \
+   -skip qtcanvas3d \
+   -skip qtpurchasing \
+   -skip qtcharts \
+   -skip qtdeclarative \
+   -no-iconv \
+   -no-glib \
+   -tslib \
+   -I"${TSLIB_INC}" \
+   -L"${TSLIB_LIB}" \
+   -alsa \
+   -I"${ALSA_INC}" \
+   -L"${ALSA_LIB}" \
+
+   echo "\033[1;33mdone...\033[0m"
+}
+
+
+#编译并且安装
+do_make_install () {
+   echo "\033[1;33mstart make and install ${PACKAGE_NAME} ...\033[0m"
+   make && make install
+   echo "\033[1;33mdone...\033[0m"
+}
+
+#删除下载的文件
+do_delete_file () {
+   cd ${SCRIPT_PATH}
+   if [ -f "${COMPRESS_PACKAGE}" ];then
+      sudo rm -f ${COMPRESS_PACKAGE}
+   fi
+}
+
+do_download_src
+do_tar_package
+do_install_config_dependent
+do_config_before
+do_configure
+do_make_install
+# do_delete_file
+
+exit $?
diff --git a/shell_tools/build-tslib.sh b/shell_tools/build-tslib.sh
new file mode 100755
index 0000000000000000000000000000000000000000..e236aef4789d9f502cfd6c9bd91442623a2824b3
--- /dev/null
+++ b/shell_tools/build-tslib.sh
@@ -0,0 +1,88 @@
+#!/bin/sh
+
+# set -v 
+
+HOST=arm-linux-gnueabihf
+SCRIPT_PATH=$(pwd)
+
+#添加交叉编译工具链路径
+# CROSS_CHAIN_PREFIX=/opt/arm-gcc/bin/arm-linux-gnueabihf
+CROSS_CHAIN_PREFIX=/opt/gcc-arm-linux-gnueabihf-8.3.0/bin/arm-linux-gnueabihf
+
+#修改源码包解压后的名称
+MAJOR_NAME=tslib
+
+#修改需要下载的源码前缀和后缀
+OPENSRC_VER_PREFIX=1
+OPENSRC_VER_SUFFIX=.21
+
+PACKAGE_NAME=${MAJOR_NAME}-${OPENSRC_VER_PREFIX}${OPENSRC_VER_SUFFIX}
+
+#定义压缩包名称
+COMPRESS_PACKAGE=${PACKAGE_NAME}.tar.bz2
+
+#定义编译后安装--生成的文件,文件夹位置路径
+INSTALL_PATH=/opt/${PACKAGE_NAME}
+
+#无需修改--下载地址
+DOWNLOAD_LINK=https://github.com/libts/${MAJOR_NAME}/releases/download/${OPENSRC_VER_PREFIX}${OPENSRC_VER_SUFFIX}/${COMPRESS_PACKAGE}
+
+#下载源码包
+do_download_src () {
+   echo "\033[1;33mstart download ${PACKAGE_NAME}...\033[0m"
+
+   if [ ! -f "${COMPRESS_PACKAGE}" ];then
+      if [ ! -d "${PACKAGE_NAME}" ];then
+         wget -c ${DOWNLOAD_LINK}
+      fi
+   fi
+
+   echo "\033[1;33mdone...\033[0m"
+}
+
+#解压源码包
+do_tar_package () {
+   echo "\033[1;33mstart unpacking the ${PACKAGE_NAME} package ...\033[0m"
+   if [ ! -d "${PACKAGE_NAME}" ];then
+      tar -xf ${COMPRESS_PACKAGE}
+   fi
+   echo "\033[1;33mdone...\033[0m"
+   cd ${PACKAGE_NAME}
+}
+
+#配置选项
+do_configure () {
+   echo "\033[1;33mstart configure ${PACKAGE_NAME}...\033[0m"
+
+   export CC=${CROSS_CHAIN_PREFIX}-gcc 
+   
+   ./configure \
+   --prefix=${INSTALL_PATH} \
+   --host=${HOST} \
+
+   echo "\033[1;33mdone...\033[0m"
+}
+
+
+#编译并且安装
+do_make_install () {
+   echo "\033[1;33mstart make and install ${PACKAGE_NAME} ...\033[0m"
+   make && make install
+   echo "\033[1;33mdone...\033[0m"
+}
+
+#删除下载的文件
+do_delete_file () {
+   cd ${SCRIPT_PATH}
+   if [ -f "${PACKAGE_NAME}" ];then
+      sudo rm -f ${PACKAGE_NAME}
+   fi
+}
+
+do_download_src
+do_tar_package
+do_configure
+do_make_install
+# do_delete_file
+
+exit $?