# Tee_dual_core_soc **Repository Path**: wzycool/tee_dual_core_soc ## Basic Information - **Project Name**: Tee_dual_core_soc - **Description**: 基于无剑100 SOC扩展安全核，构建TEE最小系统 - **Primary Language**: Unknown - **License**: MIT - **Default Branch**: master - **Homepage**: None - **GVP Project**: No ## Statistics - **Stars**: 7 - **Forks**: 3 - **Created**: 2023-08-29 - **Last Updated**: 2025-02-03 ## Categories & Tags **Categories**: Uncategorized **Tags**: None ## README # wujian100_dualcore_TEE 基于无剑100SoC开源平台，构建双核安全 SoC，系统架构如图所示。本安全系统主要包含两部分隔离：安全核与非安全核的隔离，非安全核与外设、部分内存等资源的隔离。其中安全核与非安全核的隔离采用物理隔离的方式，即安全核有独立的总线、内存及IO资源，由此构成TEE，非安全核及其相关资源构成非安全区域 REE。安全核与非安全核只通过二级总线上挂载的 Mailbox 模块实现通信，由共享的内存实现数据交互。外设资源、部分内存资源的隔离是采用IOPMP构建资源访问的“防火墙”，防止REE对受保护内存、 MMIO及外设的访问和控制。同时实现了ASCON密码学算法引擎，能为安全启动、安全存储等提供密码学服务。 ![Image text](https://gitee.com/wzycool/tee_dual_core_soc/raw/master/doc/dual_core_tee.png) # 目录结构 |--Project //open source project work directory |--riscv_toolchain //tool chain install directory download from t-head.cn |--wujian100_open //wujian100_open project get from github |--case //test case example for simulation |--doc //wujian100_open user guide |--fpga //FPGA script |--lib //compile script for simulation |--regress //regression result |--sdk //software design kit |--soc //Soc RTL source code |--tb //test bench |--tools //simulation script and setup file |--workdir //simulation directory |--LICENSE |--README.md # Get Started 1. prepare a project work directory just like 'Project' 2. cd Project 3. git clone https://gitee.com/wzycool/tee_dual_core_soc.git or git clone git@gitee.com:wzycool/tee_dual_core_soc.git # Download C/C++ Compiler 1. prepare a tool chain install directory named 'riscv_toolchain' // use the c shell command like 'mkdir riscv_toolchain' 2. download the tool chain from the url https://occ.t-head.cn/community/download?id=3913221581316624384 3. install the tool chain to the riscv_toolchain dirctory # Get open source EDA tools centos7/rhel7: sudo yum install iverilog verilator gtkwave ubuntu/debian: sudo apt-get install iverilog verilator gtkwave # Get ready for simulation 1. cd wujian100_open/tools 2. vim setup.csh then add the vcs path and license 3. source setup.csh //if not success you can touch a new file named setup.csh and copy the content to the new file. then source the new file 4. cd wujian100_open/workdir 5. if you want to use iverilog as simulation tool please execute the command '../tools/run_case -sim_tool iverilog ../case/timer/timer_test.c' or if you want to use vcs as simulation tool please execute the command '../tools/run_case -sim_tool vcs ../case/timer/timer_test.c' # Get ready for FPGA bit generation 1. make sure you have the synplify and license 2. cd wujian100_open/fpga/synplify 3. execute the synplify and load the wujian100_open_200t_3b.prj file 4. input the command 'sdc2fdc' in synplify 5. start the synplify 6. after synplify generated the netlist we will use vivado for P&R and generated the bit file 7. make sure you have the vivado and licese 8. cd wujian100_open/fpga/vivado 9. run tcl use file 'wujian100_open_200t_3b_prj.tcl' 10. program the bit file to the fpga board 11. enjoy the application development # How to get the debug tool download from the url https://occ.t-head.cn/community/download?id=616215132330000384 # How to get the IDE for development download from the url https://occ.t-head.cn/community/download?id=575997419775328256 # How to use the sdk wujian100_open SDK is wujian100_open software development kit, the software follows the CSI interface specification. Through the SDK users can quickly wujian100_open test and evaluation. At the same time users can refer to the SDK integration of various commonly used components and sample procedures for application development quickly form a product solution. ``` SDK directory structure: |--sdk |--csi_core //CSI-Core related interface definition, and interface implementation on //E902. |--csi_dirver //CSI-Driver related interface definition, and peripheral Driver //implementation. |--csi_kernel //CSI-Kernel related interface definition, and Rhino, FreeRTOSv8.2.3 //ucos-iii and other real-time operating system docking example code |--libs //Store common library implementations |--projicet //Store a variety of reference examples including benchmark test //program, driver example program, rtos example program. The relevant //project documents are also included. |--utilites //Store project config files. |--VERSION ``` 1. Download and install the CDK 2. Open a project using CDK, for example open the hello project: projects/examples/hello_world/CDK/wj100-open-hello_world.cdkproj 3. Build the project: Click "project" on the toolbar,and select "build all". After successful compilation, you will see the following: ``` Build target ' wujian100_open-hello_world BuildSet ' ----------Building project:[ wujian100_open-hello_world - BuildSet ]---------- make[1]: Entering directory 'D:/release/Wujian100_open-V1.0.0/Wujian100_open-V1.0.0/projects/examples/hello_world/CDK' make[1]: Leaving directory 'D:/release/Wujian100_open-V1.0.0/Wujian100_open-V1.0.0/projects/examples/hello_world/CDK' make[1]: Entering directory 'D:/release/Wujian100_open-V1.0.0/Wujian100_open-V1.0.0/projects/examples/hello_world/CDK' linking... size of target: text data bss dec hex filename 22680 1628 6660 30968 78f8 D:/release/Wujian100_open-V1.0.0/Wujian100_open-V1.0.0/projects/examples/hello_world/CDK/Obj/wujian100_open-hello_world.elf checksum value of target: 0xE2B2C769 (491,388) make[1]: Leaving directory 'D:/release/Wujian100_open-V1.0.0/Wujian100_open-V1.0.0/projects/examples/hello_world/CDK' Executing Post Build commands ... Done ====0 errors, 0 warnings, total time : 20s263ms==== ``` 4. Run the project: Click "Debug" on the toolbar,and select "Start/Stop Debugger". # Reference and Thanks The program model of GPIO refer to the DesignWare of Synopsys The program model of Timer refer to the DesignWare of Synopsys The program model of WDT refer to the DesignWare of Synopsys The Wujian100 soc refer to https://github.com/T-head-Semi/wujian100_open