# bp_decoder

**Repository Path**: xusun000/bp_decoder

## Basic Information

- **Project Name**: bp_decoder
- **Description**: No description available
- **Primary Language**: Unknown
- **License**: Not specified
- **Default Branch**: master
- **Homepage**: None
- **GVP Project**: No

## Statistics

- **Stars**: 0
- **Forks**: 0
- **Created**: 2026-08-10
- **Last Updated**: 2026-09-10

## Categories & Tags

**Categories**: Uncategorized

**Tags**: None

## README

# Bank-Conflict-Aware QLDPC BP Research Prototype

• 已完成整个项目的注释与入门文档：

- Python 核心模块补充了职责、数据结构、BP 更新、依赖生成、bank mapping、调度和逐周期仿真注释。
- 所有脚本、RTL、Verilator wrapper、C++ testbench 和测试文件都有文件级说明。
- 新增 224 行中文指南：docs/getting_started_zh.md:1。
- README 已加入指南入口：README.md:13。
- 未对结果文件和生成报告添加无意义的源码注释。

建议按这个顺序入门：

1. gf2.py、codes.py：理解 CSS code 和 bitset 表示。
2. src/bp_decoder_demo/decoder.py:1：理解 min-sum BP。
3. mapping.py、schedule.py、clusters.py：理解编译优化。
4. src/bp_decoder_demo/simulator.py:1：理解 read -> compute -> write -> commit 周期模型。
5. multiframe.py、tail_latency.py：理解多帧调度。
6. docs/rtl_architecture.md 和 rtl/runtime_issue_unit.sv:1：进入 RTL。

验证结果：

- 211 项 Python 测试与 11 个子测试通过；覆盖 learned N-NMS、publication-scale flooding Python reference contract、matched-weight/circuit-level noise、物理板卡证据和 provenance audit 相关路径。
- Python 语法检查和 git diff --check 通过。
- KCU116 programmable UART 路径的 Vivado xsim 与 Python cycle-trace match 均通过；这不是板级 USB-UART 实测。
- 当前环境没有 Verilator/Yosys，因此未重新运行 Verilator/Yosys RTL 门禁；已有 Vivado xsim/OOC 产物仍按各自 scope 记录。

这个仓库实现 `Roadmap.md` 中 bank-aware QLDPC BP accelerator 的软件/RTL 研究原型，当前覆盖：

- **H1**：sequential/layered BP 的 bank/dependency stalls 会显著限制目标加速器利用率。
- **H3**：小窗口 bank-aware 重排不会显著损害 logical error rate（LER）。
- **M1 oracle**：静态 bank objective 的 MILP 最优解与真实 dependency-constrained cycle 并不等价。
- **M3 tail**：只在稳定平均负载下的周期性 microburst 场景激活多帧 bank-aware runtime。
- **RTL evidence**：控制器、Q6 min-sum PE、同步 message bank 与 8-lane MVP 的严格 lint、随机等价和 UltraScale+ technology mapping。

软件模型覆盖 Toric、HGP 和 bivariate-bicycle CSS code、layered/grouped normalized min-sum、mapping portfolio、因果多帧 runtime 和逐周期 banked-memory simulator。RTL 是实现可信度 MVP，不等同于完成 place-and-route、功耗或 tapeout 级验证。

第一次阅读建议从 **[项目阅读与入门指南](docs/getting_started_zh.md)** 开始。指南给出了目录地图、十五分钟运行路径、推荐源码阅读顺序、核心数据流和常见语义误区。

## 快速运行

无需第三方 Python 包：

```bash
python -m unittest discover -s tests -v
python scripts/run_demo.py --samples 2000
```

跨 BB/HGP 码族并扫描更多硬件参数：

```bash
python scripts/run_extended_validation.py --samples 2000
```

验证 Gate B 的 M1/M2/M3 消融、8-bit 定点 LER 和投稿门槛：

```bash
python scripts/run_gate_b_validation.py --samples 2000
```

验证 M1 静态目标的双 MILP oracle（需要可选 `scipy`）：

```bash
python -m pip install -e '.[oracle]'
python scripts/run_mapping_oracle_validation.py
```

验证因果多帧 M3 的 microburst P99/deadline 收益：

```bash
python scripts/run_tail_latency_validation.py \
  --frames 256 \
  --offered-loads 0.85 \
  --reference-offered-load 0.85 \
  --arrival-pattern microburst \
  --microburst-size 8
```

生成显式的 QEC controller-level arrival trace（仍是 synthetic model，uniform arrival 仍需作为 negative control）：

```bash
python scripts/run_controller_trace_validation.py
```

运行 causal dynamic scheduling software proxy（不是 BP-SF）：

```bash
python scripts/run_dynamic_schedule_baseline.py
```

运行 matched software-only BP-SF baseline（不代表 BP-SF FPGA 实现，也不与 FPGA 资源/能耗合并排名）：

```bash
python scripts/run_bp_sf_baseline.py \
  --workloads bb12x6 hgp12x6 toric7 \
  --physical-error-rates 0.02 0.04 0.06 \
  --samples 256 --candidate-count 8 --max-flip-weight 1
```

运行 matched learned N-NMS baseline（训练集与评测集分离；仍是 software-only，不代表 FPGA 资源/时序/能耗）：

```bash
python scripts/run_learned_baseline.py \
  --workloads bb12x6 hgp12x6 toric7 \
  --physical-error-rates 0.02 0.04 0.06 \
  --training-samples 128 --evaluation-samples 256
```

运行 true RTL dynamic scheduler 的 matched static-vs-dynamic ablation：

```bash
python scripts/run_dynamic_schedule_runtime_sim.py
python scripts/run_dynamic_schedule_runtime_vivado_ooc.py \
  --part xcku5p-ffvb676-2-i --clock-period-ns 8.0
```

扫描 physical-error-rate × controller-derived burst size，并输出 paired bootstrap 区间：

```bash
python scripts/run_robustness_sweep.py --frames 128
```

对已生成的 KCU116 200 MHz bitstream 做 JTAG programming（需要真实连接的 KCU116；这一步只记录编程身份，不替代 UART readback）：

```bash
/home/user/Xilinx/2026.1/Vivado/bin/vivado -mode batch \
  -source board/scripts/program_kcu116_bitstream.tcl \
  -tclargs board/bitstreams/bp_kc116_flooding_programmable_200mhz.bit \
  board/reports/kcu116_flooding_programmable_200mhz_program.log
```

把 Vivado programming log 转成可审计 manifest：

```bash
python3 scripts/summarize_kcu116_programming.py \
  --log board/reports/kcu116_flooding_programmable_200mhz_program.log \
  --bitstream board/bitstreams/bp_kc116_flooding_programmable_200mhz.bit \
  --output results/kcu116_flooding_programmable_200mhz_program.json \
  --report docs/kcu116_flooding_programmable_200mhz_program.md
```

运行 matched-weight spatially correlated-noise robustness audit（软件 scoped evidence）：

```bash
python3 scripts/run_correlated_noise_robustness.py \
  --samples 1000 --workers 8
```

该实验固定每帧 iid/correlated 的 Binomial error weight，并额外报告 adjacency separation 与 schedule negative results；它不替代 circuit-level noise、真实 controller trace 或板级测量。

运行 BB-12x6 scoped circuit-level detector audit：

```bash
python3 scripts/run_bb12x6_circuit_level_detector_audit.py
```

该审计覆盖 3 个物理错误率 × 3 个测量轮数、每点 1,000 个 paired primitive-fault streams，显式建模 ancilla reset/CNOT hook、15 种非平凡双比特 Pauli、重复 noisy measurement、detector-event history 与 perfect-boundary closure，并用 exact fixed-point flooding 和 serial BP-SF 按 logical success 计分。它仍只覆盖 CSS X 分量和 synthetic rates；当前解码器消费 collapsed final spatial syndrome，而不是完整 space-time detector graph，也不代表 QPU calibration、FPGA 功耗或板级能耗。

归一化 RTL/Vivado 资源、吞吐 proxy 与 vectorless energy accounting：

```bash
python scripts/normalize_hardware_evidence.py --clock-mhz 200 --iterations 6
```

验证有限 ingress/resident frame admission queue 的 Vivado xsim RTL primitive：

```bash
python scripts/run_frame_queue_sim.py
```

运行 publication-scale KCU116 直连 UART 的 4/16/32 帧序列化 burst 回归（仍是 xsim，不是板级 readback）：

```bash
python3 scripts/run_kcu116_flooding_burst_stress.py
```

该回归检查有序 tag、刻意 pass/fail 语义、每帧及 status CRC/EOF、精确 commit 数，以及 parser/service 丢包计数为零；它不等同于物理 CP2105 overflow stress。

对 admission queue primitive 做独立 Vivado OOC P&R（仅 primitive 资源/时序，不代表完整 decoder closure）：

```bash
python scripts/run_queue_vivado_ooc.py \
  --part xcku5p-ffvb676-2-i \
  --clock-period-ns 5.0
```

验证 queue 到固定 decoder service slot 的 admission/commit 顺序（仍不代表 programmable LLR front-end）：

```bash
python scripts/run_decoder_service_sim.py
```

对 queue→固定 C=8/V=12 decoder service shell 运行独立 Vivado OOC P&R（仍不代表 production front-end closure）：

```bash
python scripts/run_decoder_service_vivado_ooc.py \
  --part xcku5p-ffvb676-2-i \
  --clock-period-ns 5.0
```

验证 programmable frame payload（packed signed LLR + expected codeword/syndrome）经过有限 queue→decoder service→commit：

```bash
python scripts/run_decoder_programmable_service_sim.py
```

对 programmable C=8/V=12 service shell 做独立 Vivado OOC P&R（仅小码 service shell，不代表板级或 production-scale closure）：

```bash
python scripts/run_decoder_programmable_service_vivado_ooc.py \
  --part xcku5p-ffvb676-2-i \
  --clock-period-ns 5.0
```

验证 BB-12x6 publication-scale（C=72/V=144/degree=6）多帧 queue→decoder service→commit：

```bash
python scripts/run_publication_scale_service_sim.py
python scripts/run_publication_scale_service_vivado_ooc.py \
  --part xcku5p-ffvb676-2-i \
  --clock-period-ns 10.0
```

该 service top 已包含 2-entry ingress、2-entry resident queue、packed signed
LLR/codeword/syndrome payload、per-frame restart 和 FIFO commit；当前仍是
single-PE scoped closure，不包含 NoC、banked multi-lane message memory、物理
板级 programmable readback 或实测能耗。

验证 publication-scale BB-12x6 四 lane layered datapath 及其软件拓扑/ROM 一致性：

```bash
python scripts/validate_parallel_schedule.py
python scripts/run_publication_scale_parallel_sim.py
python scripts/run_publication_scale_parallel_service_sim.py
python scripts/run_publication_scale_banked_sim.py
python scripts/run_publication_scale_banked_service_sim.py
```

四 lane OOC P&R 的 5 ns（200 MHz）点也会严格执行并保留 timing miss；当前
artifact 为 WNS -1.368 ns、估计 Fmax 157.0 MHz，不能写成 200 MHz closure：

```bash
python scripts/run_publication_scale_parallel_vivado_ooc.py \
  --part xcku5p-ffvb676-2-i \
  --clock-period-ns 5.0
```

对应证据见 `docs/parallel_schedule_validation.md`、
`docs/publication_scale_parallel_sim.md` 和 `docs/paper_bar_audit.md`。

新增 banked-memory prototype（四 bank、check % 4、固定优先级冲突 replay）：

```bash
python scripts/run_publication_scale_banked_sim.py
python scripts/run_publication_scale_banked_service_sim.py
# BRAM-calibrated synchronous-read core (four explicit RAMB36E2 banks)
python scripts/run_publication_scale_banked_bram_sim.py
python scripts/run_publication_scale_banked_bram_vivado_ooc.py \
  --part xcku5p-ffvb676-2-i --clock-period-ns 8.0
python scripts/run_publication_scale_banked_bram_vivado_ooc.py \
  --part xcku5p-ffvb676-2-i --clock-period-ns 5.0 \
  --build-dir build/publication_scale_banked_bram_5ns \
  --output results/publication_scale_banked_bram_5ns.json \
  --report docs/publication_scale_banked_bram_5ns.md
# BRAM-backed queue-integrated service
python scripts/run_publication_scale_banked_bram_service_sim.py
python scripts/run_publication_scale_banked_bram_service_vivado_ooc.py \
  --part xcku5p-ffvb676-2-i --clock-period-ns 8.0
python scripts/run_publication_scale_banked_vivado_ooc.py \
  --part xcku5p-ffvb676-2-i --clock-period-ns 8.0
python scripts/run_banked_packet_router_sim.py
python scripts/run_banked_packet_router_fairness.py
python scripts/run_banked_packet_router_fairness_sweep.py
python scripts/run_banked_packet_router_vivado_ooc.py \
  --part xcku5p-ffvb676-2-i --clock-period-ns 8.0
python scripts/run_banked_packet_router_vivado_ooc.py --fair-arbitration \
  --part xcku5p-ffvb676-2-i --clock-period-ns 8.0
python scripts/run_banked_packet_router_vivado_ooc.py --fair-arbitration \
  --part xcku5p-ffvb676-2-i --clock-period-ns 5.0 \
  --build-dir build/banked_packet_router_fair_vivado_ooc_5ns \
  --output results/banked_packet_router_fair_vivado_ooc_5ns.json \
  --report docs/banked_packet_router_fair_vivado_ooc_5ns.md
python scripts/compare_banked_packet_router_arbitration.py
python scripts/run_publication_scale_banked_packet_service_sim.py
python scripts/run_publication_scale_banked_packet_service_vivado_ooc.py \
  --part xcku5p-ffvb676-2-i --clock-period-ns 8.0
# BRAM-backed packet-to-decoder service
python scripts/run_publication_scale_banked_bram_packet_service_sim.py
python scripts/run_publication_scale_banked_bram_packet_service_vivado_ooc.py \
  --part xcku5p-ffvb676-2-i --clock-period-ns 8.0
# Scoped deterministic two-hop fabric only
python scripts/run_multihop_packet_fabric_sim.py
```

验证 credit-based multi-node ring NoC primitive（FIFO depth 1、bubble flow control、exactly-once packet contract）：

```bash
python3 scripts/run_credit_multinode_noc_sim.py
python3 scripts/run_credit_multinode_noc_sweep.py
python3 scripts/run_credit_multinode_noc_vivado_ooc.py --clock-period-ns 8.0
python3 scripts/run_credit_multinode_noc_vivado_ooc.py --clock-period-ns 5.0 \
  --build-dir build/credit_multinode_noc_vivado_ooc_5ns \
  --output results/credit_multinode_noc_vivado_ooc_5ns.json \
  --report docs/credit_multinode_noc_vivado_ooc_5ns.md
```

该 primitive 仍不等于 general adaptive mesh NoC，也不等于 KCU116 板级 decoder integration。

对当前 VC mesh 的 dedicated escape VC 运行维度参数化 rank theorem：

```bash
python3 scripts/prove_credit_mesh_escape_rank.py
```

该构造性证书对所有正整数有限矩形 `W×H` 给出严格 lexicographic channel rank，证明 deterministic X-then-Y escape route 每跳恰好减少 1 个 Manhattan distance、每条 channel dependency 严格升 rank，因此 route 最多 `W+H-2` 跳终止且 escape-VC dependency graph 无环。脚本同时绑定当前 `rtl/credit_mesh_noc_vc.sv` SHA-256，并以 `1x1` 到 `12x12` 的 422,500 条 route 做实现回归。该 rank theorem 本身不是完整 RTL 的 temporal liveness proof，也不证明 unrestricted multi-packet traffic、promotion/endpoint fairness 或 backpressure 下有限时延。

production output arbiter 另有独立的 source-bound formal theorem：对 2 VC × 5 input ports 的 10 个 requester slots，在 requester 持续 eligible、且目标 output availability/credit 已存在的前提下，BMC、temporal induction 和 cover 全部通过，并证明任一 requester 最迟在 10 次成功 grant opportunity 内得到服务。这个结论只闭合**本地、条件式 bounded wait**；它不保证下游最终返还 credit、endpoint 最终 ready，也不等于端到端 promotion/starvation freedom 或整个 decoder 的 liveness。

对固定的 4x2 adaptive-minimal credit mesh → explicit packet reassembly → BRAM-backed BB-12x6 full-flooding service boundary，还保留了一组 matched integrated OOC 对照：default-flow 的 5 ns 结果 fully routed 但为 WNS -0.063 ns（197.51 MHz estimated），因此是明确的 near-miss；独立的 `Explore / AggressiveExplore / Explore` implementation-directive run 为 WNS +0.033 ns、WHS +0.042 ns（201.33 MHz estimated），但仍只是 scoped OOC implementation datapoint。它不替代 default-flow negative evidence，也不代表完整 front-end、KCU116 board I/O、unbounded NoC liveness 或 board-measured energy closure。复现成功的归档结果：

```bash
python3 scripts/run_publication_scale_flooding_credit_mesh_packet_service_vivado_ooc.py \
  --clock-period-ns 5.0 \
  --place-directive Explore \
  --phys-opt-directive AggressiveExplore \
  --route-directive Explore \
  --build-dir build/publication_scale_flooding_credit_mesh_packet_service_vivado_ooc_5ns_directive_explore \
  --output results/publication_scale_flooding_credit_mesh_packet_service_vivado_ooc_5ns_directive_explore.json \
  --report docs/publication_scale_flooding_credit_mesh_packet_service_vivado_ooc_5ns_directive_explore.md
```

# Two-hop fabric -> BRAM-backed packet-to-decoder service

```bash
python scripts/run_publication_scale_banked_multihop_packet_service_sim.py
python scripts/run_publication_scale_banked_multihop_packet_service_vivado_ooc.py \
  --part xcku5p-ffvb676-2-i --clock-period-ns 8.0
# Explicit packet-store variant: four RAMB36 packet banks in the two-hop path
python scripts/run_publication_scale_flooding_multihop_packet_service_sim.py \
  --explicit-packet-storage
python scripts/run_publication_scale_flooding_multihop_packet_service_vivado_ooc.py \
  --explicit-packet-storage --clock-period-ns 5.0 \
  --build-dir build/publication_scale_flooding_multihop_packet_service_bram_ooc_5ns \
  --output results/publication_scale_flooding_multihop_packet_service_bram_ooc_5ns.json \
  --report docs/publication_scale_flooding_multihop_packet_service_bram_ooc_5ns.md
# Preserve the 200 MHz/timing boundary as an explicit negative result
python scripts/run_publication_scale_banked_multihop_packet_service_vivado_ooc.py \
  --part xcku5p-ffvb676-2-i --clock-period-ns 5.0 \
  --build-dir build/publication_scale_banked_multihop_packet_service_vivado_ooc_5ns \
  --output results/publication_scale_banked_multihop_packet_service_vivado_ooc_5ns.json \
  --report docs/publication_scale_banked_multihop_packet_service_vivado_ooc_5ns.md
```

banked core 的 BB-12x6 每迭代软件/xsim 对齐结果为 72 lane issues、19 group commits、
46 issue batches、27 conflict batches、37 denied lane operations、231 control cycles。
此外，未加输入寄存器的 BRAM-calibrated xsim 基线每迭代 277 control cycles；当前源码的 direct
decode→PE input-pipelined top 每迭代 369 cycles。Vivado 在 `xcku5p-ffvb676-2-i`、8 ns 点对该
input-pipelined top 观察到 4 个显式 RAMB36E2、WNS +0.880 ns、WHS +0.044 ns、估计 Fmax
140.45 MHz、29,581 LUT/4,542 FF/8 DSP、0 unrouted nets、0.976 W vectorless。
vectorless。现在 queue-integrated 与 packet-to-decoder scoped service 也已提供 BRAM-backed
参数化版本，并有独立 xsim/OOC 产物；旧 packet integration artifact 的 packet FIFO/reassembly
仍是 inferred storage，但最新的 explicit-BRAM packet-reassembly artifact 已将 packet persistence
映射到 4 个 RAMB36E2 bank，并保留同步读回边界，
现在新增了 scoped deterministic two-hop fabric：4 source lanes → 2 intermediate nodes → 4 destination banks，
并已接入 BRAM-backed BB-12x6 packet service。xsim 验证 180/180/0 packet、360 forwarded hops、
bit-exact reassembly 和 FIFO commit；8 ns OOC 为 WNS +0.782 ns、4 BRAM、39,848 LUT、
12,363 FF、1.019 W vectorless。这里的 `dest % 2` 路由只是 bounded two-hop evidence，
不应写成 general adaptive/credit-based multi-hop NoC；hop-1 同目的冲突在该拓扑中结构性为 0，
但 hop-1 backpressure/congestion 已被测到。对应 5 ns sweep 为 WNS -0.476 ns、估计 Fmax 182.62 MHz，
因此 200 MHz 仍明确未闭合。另有 `EXPLICIT_PACKET_STORAGE=1` 的 two-hop variant：xsim 通过 180/180/0、360 forwarded hops、0 snapshot mismatch；5 ns routed OOC 通过 WNS +0.268 ns、WHS +0.042 ns，packet-store 观察到 4 个 RAMB36（总计 95 个）。该显式 variant 仍是 scoped deterministic two-hop 集成，不是完整 production-scale NoC、板级 readback 或实测 energy closure。

验证 publication-scale BB-12x6 **真正的 full flooding snapshot** RTL（`l_snapshot` 跨 19 个 group 保持不变，每轮只 commit 一次）：

```bash
python scripts/run_publication_scale_flooding_sim.py
python scripts/run_publication_scale_flooding_reference_match.py
python scripts/run_publication_scale_flooding_vivado_ooc.py \
  --part xcku5p-ffvb676-2-i --clock-period-ns 5.0
python scripts/run_publication_scale_flooding_vivado_ooc.py \
  --part xcku5p-ffvb676-2-i --clock-period-ns 8.0 \
  --build-dir build/publication_scale_flooding_vivado_ooc_8ns \
  --output results/publication_scale_flooding_vivado_ooc_8ns.json \
  --report docs/publication_scale_flooding_vivado_ooc_8ns.md
```

5 ns OOC datapath 结果为 WNS +0.021 ns、估计 200.84 MHz；8 ns 对照点为 WNS +0.513 ns、估计 133.56 MHz。这里的 flooding message store 是 explicit registers，不等同于 BRAM-backed grouped/layered 行，更不等同于完整 service/front-end、NoC、板级 readback 或实测能耗。

`python scripts/run_publication_scale_flooding_reference_match.py` 还会用固定 seed
`20260820` 生成 16 个 BB-12x6 frame，并将固定点 Python reference 与 Vivado xsim
进行 output/convergence/counter contract match。覆盖 zero-error、两个 directed
single-error、12 个 randomized frame，以及一个 incompatible expected-codeword
negative control；比较 pass/fail、iteration count、hard decision/syndrome result
contract、group/lane/snapshot counters 和 frame cycles。对应产物为
`results/publication_scale_flooding_reference_match.json` 与
`results/publication_scale_flooding_reference_match.log`。这不是 message-level
waveform match；该 flooding core 仍是 explicit-register storage，不是
BRAM/SRAM flooding，也不构成完整 service/front-end、board-I/O 或 measured-energy
closure。

验证强 schedule baseline 矩阵（flooding、clustered、layered，统一 grouped-update 语义）：

```bash
python scripts/run_schedule_baseline_validation.py \
  --physical-error-rates 0.02 0.04 0.06 \
  --samples 500 \
  --group-sizes 1 2 4 8
```

对同一 publication-scale BB-12x6 BRAM-backed datapath 运行可实现的 layered/clustered2/grouped4 matched hardware baseline（相同 xcku5p、4 lanes、4 个 RAMB36E2、同步读延迟和 I/O timing boundary）：

```bash
python scripts/run_publication_scale_banked_hardware_baselines.py --only all
python scripts/run_publication_scale_banked_hardware_baseline_vivado_ooc.py \
  --baseline layered --clock-period-ns 8.0
python scripts/run_publication_scale_banked_hardware_baseline_vivado_ooc.py \
  --baseline clustered2 --clock-period-ns 8.0
python scripts/run_publication_scale_banked_hardware_baseline_vivado_ooc.py \
  --baseline grouped4 --clock-period-ns 8.0
# 额外保留 5 ns / 200 MHz 边界结果
python scripts/run_publication_scale_banked_hardware_baseline_vivado_ooc.py \
  --baseline layered --clock-period-ns 5.0
python scripts/run_publication_scale_banked_hardware_baseline_vivado_ooc.py \
  --baseline clustered2 --clock-period-ns 5.0
python scripts/summarize_publication_scale_banked_hardware_baselines.py
```

该矩阵是冲突自由 grouped/layered 硬件证据，不是 full flooding snapshot 实现。5 ns schedule-core 结果为 layered WNS +0.080 ns（估算 203.25 MHz）、clustered2 WNS -0.516 ns、grouped4 WNS -0.269 ns；即使 layered 行闭合，也不等于完整 decoder/service/front-end 的 200 MHz production closure。

验证冻结策略在 unseen code size 上的 held-out generalization：

```bash
python scripts/run_heldout_generalization.py \
  --frames 1000 \
  --seeds 20260813 20260814 20260815 \
  --output results/heldout_generalization_1000.json \
  --csv results/heldout_generalization_1000.csv \
  --report docs/heldout_generalization_1000.md
```

运行完整 RTL/Verilator/Yosys 证据门禁：

```bash
python scripts/run_rtl_validation.py
```

在安装 Vivado 的远程主机运行严格 OOC place-and-route 门禁：

> 默认 target 是 KCU116-compatible `xcku5p-ffvb676-2-i`。`--input-min-delay-ns 0.2` 是用于 hold 分析的 OOC boundary assumption，不是板级实测 I/O 延迟；因此 100 MHz closure 不能直接表述为 board-level timing closure。

```bash
python scripts/run_vivado_ooc.py \
  --part xcku5p-ffvb676-2-i \
  --clock-period-ns 10.0 \
  --input-delay-ns 1.0 \
  --input-min-delay-ns 0.2 \
  --output-delay-ns 1.0
```

对完整当前 MVP 做 200/125/100 MHz 多周期 OOC sweep（失败点也会被保留）：

```bash
python scripts/run_vivado_ooc_sweep.py
```

结果写入 `results/vivado_ooc_timing_sweep.json` 和 `docs/vivado_ooc_timing_sweep.md`；当前 canonical evidence 是 200 MHz/125 MHz FAIL、100 MHz scoped PASS。

较快的 smoke test：

```bash
python scripts/run_demo.py \
  --distances 5 \
  --physical-error-rates 0.05 0.08 \
  --samples 200
```

输出：

- `results/demo_summary.json`：完整机器可读指标；
- `docs/h1_h3_demo_report.md`：H1/H3 判定、表格和边界说明。
- `results/extended_summary.json`：BB/HGP 扩展实验完整结果；
- `results/h1_hardware_sweep.csv`：`PE × bank × port` 的逐配置结果；
- `docs/h1_h3_extended_report.md`：跨码族验证报告。
- `results/gate_b_summary.json`：Gate B 完整消融和统计结果；
- `results/gate_b_ablation.csv`：逐 workload 架构收益；
- `docs/gate_b_report.md`：Software Gate B 与投稿门槛判断。
- 可用 `--fixed-bits 12 --fixed-fractional-bits 6` 复核高精度定点敏感性，结果见 `docs/gate_b_12bit_report.md`。
- `results/mapping_oracle_summary.json` / `docs/mapping_oracle_report.md`：M1 双 MILP oracle 与 proxy–cycle gap。
- `results/tail_latency_summary.json` / `docs/tail_latency_report.md`：256-frame microburst Gate C。
- `results/tail_latency_sensitivity_summary.json`：四个 offered-load 点的 64-frame sensitivity。
- `results/tail_latency_uniform_summary.json`：uniform arrival 的负面结果，Gate C 保持 FAIL。
- `results/qec_controller_trace.json` / `results/qec_controller_trace.csv` / `docs/qec_controller_trace.md`：显式 QEC controller-level synthetic arrival trace 与 provenance。
- `results/dynamic_schedule_baseline.json` / `docs/dynamic_schedule_baseline.md`：causal dynamic scheduling software proxy；不是 BP-SF。
- `results/dynamic_schedule_runtime_sim.json` / `docs/dynamic_schedule_runtime_sim.md`：registered causal RTL scheduler 的 bounded admission、bank conflict、per-frame restart 和 matched static-vs-dynamic ablation。
- `results/bp_sf_baseline.json` / `results/bp_sf_baseline.csv` / `docs/bp_sf_baseline.md`：matched software-only BP-SF syndrome-flip baseline；报告 paired LER、convergence、Wilson intervals、serial BP work 和 trial-level parallel-latency proxy，不包含 FPGA 资源、时序或板级能耗。
- `results/bp_sf_rtl_reference_match.json` / `docs/bp_sf_rtl_reference_match.md` 与 `results/bp_sf_serial_vivado_ooc.json` / `docs/bp_sf_serial_vivado_ooc.md`：production-scale BB-12x6 syndrome-only fixed-point weight-one BP-SF RTL baseline；单个 four-lane flooding kernel 串行复用，5-case xsim bit-exact match，并从 xsim 原始 case record 解析得到 `98–11,538` RTL latency cycles 与 `96–10,368` scheduled kernel cycles（固定为 `96 × serial BP iterations`）。XCKU5P 5 ns OOC 以 WNS +0.044 ns / WHS +0.037 ns fully routed。由于候选试验数和收敛迭代数依输入变化，不宣称单一 cycles/frame；功耗仍是 routed vectorless estimate，不是板级实测，也不宣称 8-kernel replicated-parallel BP-SF。
- `results/learned_baseline.json` / `results/learned_baseline.csv` / `docs/learned_baseline.md`：matched software-only learned N-NMS baseline；128-frame disjoint training + 256-frame held-out evaluation，报告 learned parameters、paired LER/convergence、Wilson intervals 和 exact tests，不包含 FPGA 资源、时序或板级能耗。
- `results/dynamic_schedule_runtime_vivado_ooc.json` / `docs/dynamic_schedule_runtime_vivado_ooc.md`：scheduler-only 的 routed Vivado OOC 资源/时序/功耗估计；8 ns 点 WNS 为负，不能据此宣称 200 MHz。
- `results/dynamic_schedule_runtime_vivado_ooc_12ns.json` / `docs/dynamic_schedule_runtime_vivado_ooc_12ns.md`：scheduler-only 的 12 ns scoped closure；不是完整 decoder、BP-SF 或板级能耗。
- `results/publication_scale_flooding_reference_match.json` / `results/publication_scale_flooding_reference_match.log`：16-frame fixed-point Python↔Vivado xsim output/convergence/counter contract match；不是 message-level waveform、BRAM/SRAM flooding、service/front-end、board-I/O 或 measured-energy closure。
- `results/robustness_sweep.json` / `docs/robustness_sweep.md`：physical-error-rate × burst-size 的 scoped robustness sweep；脚本支持 `--include-uniform-negative-control` 生成显式 uniform 负控制。
- `results/robustness_sweep_uniform_128.json` / `docs/robustness_sweep_uniform_128.md`：128-frame uniform-arrival negative control，保留 family-specific CI，不作为 microburst 正面结果。
- `results/robustness_sweep_1000.json` / `docs/robustness_sweep_1000.md`：publication-scale software robustness sweep（1,000 frames/point，45 workload points）。
- `results/correlated_noise_robustness.json` / `docs/correlated_noise_robustness.md`：matched-weight spatially correlated X-noise audit（30 points，5 workloads/3 code families，3 rates，rho=0.5/0.9，1,000 samples/point）；保留 flooding 与 clustered4 的显著负结果，不宣称普适 correlated-noise 增益，也不代表 circuit-level、板级或 FPGA 结果。
- `results/bb12x6_circuit_level_detector_audit.json` / `results/bb12x6_circuit_level_detector_samples.jsonl` / `docs/bb12x6_circuit_level_detector_audit.md`：BB-12x6 scoped circuit-level detector evidence（9 points、9,000 paired samples、144 个 raw records）；detector closure、sample seed、primitive-fault accounting 与 paired McNemar accounting 均由严格 gate audit 检查。仅覆盖 synthetic CSS-X direct-ancilla model 与 collapsed spatial decoding，不宣称 calibrated QPU 或完整 space-time decoder。
- `results/credit_mesh_escape_rank_theorem.json` / `docs/credit_mesh_escape_rank_theorem.md`：source-bound arbitrary-positive-dimension XY escape-route rank theorem；8 类合法 dependency 的 affine obligations 全部严格升 rank，四个 route case 均恰好将 Manhattan distance 减 1，补充回归覆盖 144 个矩形尺寸和 422,500 条 route。仅证明 dedicated escape routing/CDG，不宣称完整 RTL 或 unrestricted traffic liveness。
- `results/publication_scale_evidence_audit.json` / `docs/publication_scale_evidence_audit.md`：publication-scale xsim/OOC provenance audit；当前 181/181 checks 通过；新增 `scripts/audit_ccfa_gates.py` / `results/ccfa_gate_status.json` / `docs/ccfa_gate_status.md` 维护 14 个 CCF-A gate 的 PASS/PARTIAL/PENDING/BLOCKED_EXTERNAL_HARDWARE 状态；claim-aligned submission core 为 9/9 PASS，完整保守 register 仍为 9/14 full PASS（其余是可选的功耗、ASIC、memory-calibration 和 external-trace extensions），0 个 stale cycle-metadata artifact；这是内部一致性检查，不是录用保证。
- `results/external_qec_controller_raw_trace_audit.json` / `docs/external_qec_controller_raw_trace_audit.md`：对 Caune et al. Zenodo 15364358 的 CC-BY-4.0 原始 `decoder_timings_each_repetition.csv` 做全量独立审计；300,000 rows（9/17/25 rounds 各 100,000）均满足 156.25 MHz cycle conversion，并重现 source mean。它是真实 FPGA decoder execution-time trace，不是 syndrome-arrival timestamp trace，也不允许与本地 BB-12x6 直接排名。
- `results/external_qec_feedback_trace_audit.json` / `docs/external_qec_feedback_trace_audit.md`：进一步对同一 Zenodo 记录的原始 `fast_feedback_raw_data.h5` 做确定性提取与独立审计；8,000 条 per-shot control/decoder-register rows（2--9 rounds 各 1,000）精确重建 Fig. 4b 的全部 control/decoder mean 与 population std，并共同推出 250 MHz control 路径的 395-cycle fixed offset。它强化了真实闭环 timing 证据，但仍不是 syndrome-arrival timestamps、不匹配本地 BB-12x6，也不允许 direct ranking。
- `scripts/generate_axku5_board_power_templates.py` / `scripts/analyze_axku5_board_power.py`：生成完整五重复 12 V 采集骨架并分析真实 meter samples；Gate 3/4 promotion 现在绑定 canonical raw/metadata/build/analyzer/report hashes，并有临时仓库 tamper regression。尚无真实 meter capture，因此功耗/能耗 gate 仍 PENDING。
- `results/hardware_normalized.json` / `docs/hardware_normalized.md`：资源、吞吐和 vectorless energy 的 accounting-only normalization。
- `results/publication_scale_baselines_normalized.json` / `docs/publication_scale_baselines_normalized.md`：同一 xcku5p、BB-12x6、四 lane、四 RAMB36E2 schedule-core 的 matched per-update/per-frame normalization；仍是 vectorless proxy，不是板级能耗或外部 FPGA baseline。
- `results/external_fpga_decoder_baselines.json` / `docs/external_fpga_decoder_baselines.md`：三条主来源 FPGA QEC 文献行的 source-located audit（Valls 2021 QLDPC SB-MS、Bascones 2025 `[144,12,12]` BB BP+OSD、Liyanage 2024 surface-code Helios）；保存 DOI、PDF SHA-256、页/表定位和 comparability flags，三行均排除 direct ranking。该证据只把 Gate 10 提升为 PARTIAL，不允许生成跨 workload speedup/energy ratio。
- `results/banked_packet_router_invariant_sweep.json` / `docs/banked_packet_router_invariant_sweep.md`：四组参数化 packet-router bounded invariant xsim；检查 occupancy/conservation/no-drop/FIFO order，不是 formal liveness proof。
- `results/banked_packet_router_fairness.json` / `docs/banked_packet_router_fairness.md`：`FAIR_ARBITRATION=1` 的两 lane/单 bank round-robin bounded xsim；40 个连续竞争包全部无丢失，per-lane accepted 为 20/20，最大等待为 1/1 cycle；这是 selected finite configuration 的 fairness/liveness evidence，不是 unbounded formal proof。
- `results/banked_packet_router_fairness_sweep.json` / `docs/banked_packet_router_fairness_sweep.md`：六组有限参数 sweep，覆盖 2/3/4 lanes 与 1/2/4 banks；所有 case accepted=delivered、0 drop、per-lane service 相等，且 observed wait 不超过 active-bank contention group 的 `lanes_per_active_bank - 1`；仍是 bounded xsim，不是 formal proof 或 general adaptive NoC。
- `results/banked_packet_router_formal.json` / `docs/banked_packet_router_formal.md`：新增 Yosys/Z3 可复现 formal runner。对 selected `LANES=2/BANKS=1/FIFO_DEPTH=2` safety harness 与 two-lane/one-bank continuous-request round-robin fairness harness，BMC、temporal induction、cover 均通过；这是 named finite harness 的 inductive evidence，不是 arbitrary-parameter、full credit-mesh、general production NoC 或 CCF-A closure。
- `results/kcu116_200mhz_storage_boundary.json` / `docs/kcu116_200mhz_storage_boundary.md`：KCU116 200 MHz direct-top 的非重复计数 storage/area boundary artifact；以 top-level routed utilization 为总面积，子层级仅作 ownership view，并显式列出 parser/admission/decoder/response 的 RAMB36/LUTRAM 边界。
- `results/kcu116_flooding_programmable_200mhz_program.json` / `docs/kcu116_flooding_programmable_200mhz_program.md`：真实 Digilent/KCU116 JTAG target `210512180081` 上的 200 MHz bitstream programming manifest；SHA/size/device checks 通过，但不包含 UART readback、decoder correctness、板级功耗或 energy。
- `results/credit_multinode_noc_sim.json` / `docs/credit_multinode_noc_sim.md`：4-node credit-based shortest-ring RTL/xsim contract；96/96 exactly-once bit-exact delivery，显式 credit stall/retry 计数，以及 FIFO depth 1 bubble-flow-control stress。`results/credit_multinode_noc_sweep.json` / `docs/credit_multinode_noc_sweep.md` 进一步覆盖 N=3/4/8、FIFO depth 1/2，并在每周期检查 capacity/credit bound、accepted-minus-delivered conservation 和 no-drop invariants。对应 8 ns/5 ns routed OOC 产物分别为 `results/credit_multinode_noc_vivado_ooc.json` 和 `results/credit_multinode_noc_vivado_ooc_5ns.json`；仍不是 general adaptive NoC 或板级集成。
- `results/credit_mesh_noc_sim.json` / `docs/credit_mesh_noc_sim.md`：scoped 2x2 credit mesh 的 adaptive-minimal xsim contract；64/64 exactly-once bit-exact delivery，88 forwarded hops，282 retries，301 credit stalls。`results/credit_mesh_noc_sweep.json` / `docs/credit_mesh_noc_sweep.md` 覆盖 2x2 adaptive/XY、FIFO depth 1/2 与 3x2 XY，并逐周期检查 capacity/credit/conservation/no-drop invariants；`results/credit_mesh_noc_vivado_ooc.json` / `docs/credit_mesh_noc_vivado_ooc.md` 为同一 xcku5p 的 8 ns routed OOC（WNS +4.998 ns、1745/1745 nets、863 LUT/1249 FF、0 BRAM、0.466 W vectorless）。
- `results/credit_mesh_noc_vc_sim.json` / `results/credit_mesh_noc_vc_sim_d2d.json` 与 `docs/credit_mesh_noc_vc_sim*.md`：scoped 2x2 adaptive VC0 + deterministic XY escape VC1 bounded xsim；FIFO depth 1/2 均 lossless，默认 24/24、12 promotions、16 escape deliveries、0 bounded-monitor violations。`rtl/credit_mesh_noc_vc.sv` 已补上 `link_push_packet` 的显式组合默认赋值，消除此前 Vivado 报告的 inferred-latch 根因；修复后的默认 xsim 数字保持不变。仍无 unbounded deadlock/liveness proof、board traffic/power 或 general production NoC closure。
- `results/credit_mesh_vc_formal.json` / `docs/credit_mesh_vc_formal.md` / `formal/credit_mesh_noc_vc_safety.sv`：fixed 2x1、FIFO1、two-VC、three-packet harness 的 Yosys/Z3 20-step BMC 与 cover；cover 在 step 13 到达，并非空洞地观察到 VC0→VC1 promotion、escape delivery、conservation、per-VC bounds、metadata preservation 与 unique delivery。该 harness 是 one-hop bounded evidence，没有 temporal induction、multi-hop RTL theorem、deadlock freedom、unrestricted liveness、arbitrary-topology 或 integrated-decoder formal claim。
- `results/credit_mesh_vc_multihop_formal.json` / `docs/credit_mesh_vc_multihop_formal.md` / `formal/credit_mesh_noc_vc_multihop_safety.sv`：fixed 2x2、FIFO1、two-VC、source 0→destination 3 的 three-packet harness 通过 24-step BMC 和 lightweight non-vacuity cover；cycle 15 的 bounded assertions 要求三包全部唯一送达、aggregate 至少 6 个 forwarded hops、至少一次 VC0→VC1 promotion，并同时出现 adaptive/escape endpoint delivery。该证据只覆盖固定 topology/workload；没有 temporal induction、unbounded deadlock/liveness、arbitrary-topology 或 integrated-decoder formal claim。
- `results/credit_mesh_vc_anypair_formal.json` / `docs/credit_mesh_vc_anypair_formal.md` / `formal/credit_mesh_noc_vc_anypair_safety.sv`：在 2x2、3x2、2x3、3x3 四种固定 mesh 上穷举全部 144 个有序不同 source/destination 对。前三种形状各用一个双符号端点查询；3x3 不删减任何 pair 或 assertion，而是拆成 9 个固定 source、符号 destination 的分区查询以避免单查询超时。全部 BMC 与 non-vacuity cover PASS，并检查单包唯一接收/送达、conservation、zero-drop、metadata、FIFO/credit bounds、exact Manhattan hops 和 bounded completion。它仍是 all-ready、single-packet、finite-shape bounded evidence，不是 arbitrary-dimension、multi-source contention、temporal induction、unbounded deadlock/liveness 或 full-decoder proof。
- `results/credit_mesh_vc_multisource_formal.json` / `docs/credit_mesh_vc_multisource_formal.md` / `formal/credit_mesh_noc_vc_multisource_contention_safety.sv`：production two-VC RTL 的 fixed 2x2/FIFO1 三源汇聚争用 BMC。nodes 0/1/2 各注入两包到 node 3；sink 在 cycle 8 起永久 ready。16-state BMC 证明 conservation、source/tag/sequence/payload preservation、无重复送达、每源恰好两包完成、retry/endpoint-stall 被观察到，并在 cycle 14 零占用排空；全部六包 accepted 的 cover 在 step 4 到达。该证据只覆盖确定性的有限六包 workload 和 eventually-ready sink，不是 arbitrary injection/backpressure、unbounded fairness、fixed-priority starvation freedom、完整 RTL temporal liveness 或 full-decoder proof。
- `results/credit_mesh_output_arbiter_formal.json` / `docs/credit_mesh_output_arbiter_formal.md` / `formal/credit_mesh_output_arbiter_fairness.sv`：直接绑定 production `rtl/credit_mesh_output_arbiter.sv` 的 2-VC × 5-port round-robin theorem。BMC、temporal induction、cover 均 PASS；在 requester 连续 eligible 且 output availability/credit 已存在时，10 个 requester slots 中任一个均在 10 次 successful grant opportunities 内被服务。该 theorem 是 local conditional bounded-wait，不证明 eventual downstream credit/readiness、end-to-end promotion/starvation freedom、unrestricted network liveness 或 complete-decoder progress。
- `results/credit_mesh_output_arbiter_pulsed_credit_formal.json` / `docs/credit_mesh_output_arbiter_pulsed_credit_formal.md` 与 `results/credit_mesh_escape_qos_theorem.json` / `docs/credit_mesh_escape_qos_theorem.md`：将 production arbiter 的 rank 保持扩展到任意长 credit gap，并给出 source-bound continuing-traffic escape-VC QoS theorem。对于直接接受到 deterministic escape VC1 的 packet，允许其他 source 持续并发注入；若每个 endpoint 至少每 `E` 个 cycle ready 一次，则任意正整数有限矩形 mesh 上存在构造性 delivery bound。4x2、FIFO depth 2、`E=4` 的保守上界为 1,135,788 cycles（200 MHz 下 5,678.940 us）。该结论不覆盖 adaptive VC0、adaptive-to-escape promotion 的 boundedness、永久 backpressure、任意图拓扑、完整 flattened mesh RTL temporal induction 或当前默认注入 VC0 的 integrated decoder service。
- `results/credit_mesh_escape_acyclic.json` / `docs/credit_mesh_escape_acyclic.md`：对 2x2、3x2、4x2、4x4 矩形 mesh 和 FIFO depth 1/2 共 8 个 case 的 deterministic X-then-Y escape-channel dependency 审计；所有路径终止、route rank 单调、dependency DAG 无环、无 reverse dependency、无 vertical-to-horizontal dependency。该结果是有限 channel-dependency architectural evidence，不是 RTL formal/unbounded liveness proof、adaptive VC0 theorem 或 general production NoC closure。
- `results/publication_scale_flooding_credit_mesh_vc_packet_service_sim.json` / `docs/publication_scale_flooding_credit_mesh_vc_packet_service_sim.md`：scoped 4x2 FIFO2 VC integrated endpoint，4 个 source packet lane 显式注入 VC0，VC0 adaptive-minimal / VC1 deterministic XY escape；xsim 通过 4 frames、180/180 lossless packets、364 forwarded hops、51 promotions、129 adaptive deliveries、51 escape deliveries、0 bounded-monitor violations、0 reassembly grant mismatches、12 flooding snapshot commits。原 default-flow 5 ns OOC fully routed 但 WNS -0.573 ns，关键路径为 `accum_lane_index` 动态选择后驱动全 `eval_belief` 写网络。`rtl/bp_publication_scale_flooding_bram_core.sv` 现用窄的一-lane `accum_*_q` 寄存边界将 selector 与宽写网络分离；重跑 integrated xsim 保持上述数字，matched default-flow OOC 在 5 ns/8 ns 均 fully routed/timing met：WNS +0.036/+1.450 ns，5 ns 为 44,232 LUT / 22,125 FF / 95 BRAM / 8 DSP。旧 -0.573 ns artifact 保留为 pre-fix negative evidence；新结果仍只是 OOC core closure，不是 retry stress、general production NoC、unbounded formal proof、完整 front-end 或 board closure。
- `results/frame_queue_validation.json` / `docs/rtl_frame_admission_queue.md`：有限 admission queue 的 Vivado xsim RTL primitive 证据，不能替代 production-scale front-end closure。
- `results/queue_vivado_ooc.json` / `docs/queue_vivado_ooc.md`：admission queue primitive 的独立 Vivado OOC P&R 资源/时序/功耗估计，不能替代完整 decoder OOC 或 board measurement。
- `results/decoder_service_validation.json` / `docs/rtl_decoder_service.md`：queue→固定 decoder service slot→commit 的 FIFO/重启/结果传播 RTL 证据；这是兼容性/控制路径结果，输入仍是固定 decoder 的 tag token。
- `results/decoder_service_vivado_ooc.json` / `docs/decoder_service_vivado_ooc.md`：queue→固定 decoder service shell 的独立 Vivado OOC P&R 资源/时序/功耗估计；不包含 programmable LLR front-end。
- `results/decoder_programmable_service_validation.json` / `docs/rtl_decoder_programmable_service.md`：packed signed LLR、目标 codeword/syndrome、FIFO/backpressure、per-frame restart 和 pass/fail commit 的 xsim 证据；仅 C=8/V=12 小码 scoped result。
- `results/decoder_programmable_service_vivado_ooc.json` / `docs/decoder_programmable_service_vivado_ooc.md`：programmable C=8/V=12 service shell 的独立 Vivado OOC 资源/时序/功耗估计；不是板级 multi-frame 或 production-scale closure。
- `results/publication_scale_service_sim.json` / `docs/publication_scale_service_sim.md`：BB-12x6 publication-scale 多帧 queue/service xsim 证据；包含 FIFO commit、payload/result propagation 和 backpressure。
- `results/publication_scale_service_vivado_ooc.json` / `docs/publication_scale_service_vivado_ooc.md`：BB-12x6 多帧 service top 的 100 MHz OOC P&R；`results/publication_scale_service_vivado_ooc_5ns.json` / `docs/publication_scale_service_vivado_ooc_5ns.md` 是 200 MHz 点；两者均为 scoped PASS，仍不等于 NoC/parallel production closure。
- `results/parallel_schedule_validation.json` / `docs/parallel_schedule_validation.md`：BB-12x6 四 lane schedule 的软件拓扑、ROM literal、check coverage、variable-disjoint 和 cycle-contract 校验。
- `results/publication_scale_parallel_sim.json` / `results/publication_scale_parallel_service_sim.json` / `docs/publication_scale_parallel_sim.md`：四 lane datapath 及 queue-integrated service 的 xsim 证据。
- `results/publication_scale_parallel_vivado_ooc_5ns.json`：200 MHz 目标的明确 timing miss（WNS −1.368 ns）；`results/publication_scale_parallel_vivado_ooc_8ns.json` 与 `results/publication_scale_parallel_service_vivado_ooc_8ns.json`：125 MHz scoped closure，后者纳入 queue/service 资源。
- `results/publication_scale_banked_bram_sim.json` / `docs/publication_scale_banked_bram_sim.md`：四个显式 RAMB36E2 bank、同步一周期 row read 的 BB-12x6 core xsim；四帧功能与 bank-pressure counters 通过，277 cycles/iteration。
- `results/publication_scale_banked_bram_vivado_ooc.json` / `docs/publication_scale_banked_bram_vivado_ooc.md`：当前源码 direct input-pipelined BRAM-calibrated core 的 8 ns routed OOC；WNS +0.880 ns、WHS +0.044 ns、估计 Fmax 140.45 MHz、29,581 LUT/4,542 FF/8 DSP/4 BRAM36/0 BRAM18、0 unrouted nets、0.976 W vectorless。 `results/publication_scale_banked_bram_5ns.json` / `docs/publication_scale_banked_bram_5ns.md` 记录同一当前源码 top 的 5 ns sweep，并明确保留 timing miss。这是 standalone core 的 BRAM 校准点；queue/packet service 的 BRAM 结果见后续独立产物，也不是板级测量。
- `results/publication_scale_banked_bram_inputpipe_5ns.json` / `docs/publication_scale_banked_bram_inputpipe_5ns.md`：在 BRAM top 中加入显式 group/check decode→PE input register 后的 matched 5 ns OOC；当前源码重跑 WNS −0.524 ns、WHS +0.045 ns、估计 Fmax 181.03 MHz、31,429 LUT/4,565 FF/8 DSP/4 BRAM36，仍未达到 200 MHz。xsim 四帧通过，direct input-pipelined top 每迭代为 369 个控制周期；该结果仍是 core-only timing experiment，不是完整 service/front-end closure。
- `results/publication_scale_banked_bram_service_sim.json` / `docs/publication_scale_banked_bram_service_sim.md`：BRAM-backed queue-integrated service xsim；四帧 FIFO commit 通过，277 cycles/iteration，含 3,324-cycle max-iteration failure。
- `results/publication_scale_banked_bram_service_vivado_ooc.json` / `docs/publication_scale_banked_bram_service_vivado_ooc.md`：BRAM-backed queue service 的当前源码 8 ns routed OOC；WNS +0.799 ns、WHS +0.046 ns、估计 Fmax 138.87 MHz、28,515 LUT/7,592 FF/8 DSP/83 BRAM36、0 top-level LUTRAM、1.162 W vectorless；service 层宽队列使总 BRAM 数高于 standalone core，仍不是板级测量。
- `results/publication_scale_banked_bram_packet_service_sim.json` / `docs/publication_scale_banked_bram_packet_service_sim.md`：packet router→reassembly→BRAM-backed decoder service 的 xsim；180 accepted/180 delivered/0 dropped，bit-exact，四帧 FIFO commit 通过。
- `results/publication_scale_banked_bram_packet_service_vivado_ooc.json` / `docs/publication_scale_banked_bram_packet_service_vivado_ooc.md`：历史 BRAM-backed packet integration 的 8 ns routed OOC；WNS +0.707 ns、WHS +0.034 ns、39,028 LUT/11,719 FF/8 DSP/4 BRAM、1.023 W vectorless；该历史 artifact 的 packet FIFO/reassembly 仍为 inferred storage，最新 explicit packet-persistence 结果见下一行。
- `results/bp_packet_reassembly_bram_sim.json` / `docs/bp_packet_reassembly_bram_sim.md`：explicit packet-store same-bank collision/retry xsim regression
- `results/publication_scale_banked_bram_packet_reassembly_vivado_ooc.json` / `docs/publication_scale_banked_bram_packet_reassembly_vivado_ooc.md`：最新 explicit-BRAM packet-reassembly 8 ns routed OOC；5 ns negative boundary 见 `results/publication_scale_banked_bram_packet_reassembly_vivado_ooc_5ns.json` / `docs/publication_scale_banked_bram_packet_reassembly_vivado_ooc_5ns.md`（WNS −0.582 ns，估计 179.15 MHz）；`u_packet_reassembly_bram` 观察到 4 RAMB36，WNS +0.707 ns、WHS +0.044 ns、30,975 LUT/10,177 FF/8 DSP、87 total RAMB36、41,721 fully routed nets、1.119 W vectorless；frame assembly 是 bounded interface register，功耗仍是 vectorless estimate。
- `results/publication_scale_banked_sim.json` / `docs/publication_scale_banked_sim.md`：四-lane/four-bank bank-conflict-aware core 的 xsim 与软件 reference 对齐证据；每迭代 46 issue batches、27 conflict batches、37 denied lane operations。
- `results/publication_scale_banked_vivado_ooc_5ns.json` / `results/publication_scale_banked_vivado_ooc_8ns.json` / `results/publication_scale_banked_vivado_ooc_10ns.json`：banked core 的 routed OOC timing sweep；5 ns 明确 miss，8 ns 为 scoped 125 MHz closure。Vivado 观察到 0 BRAM/0 LUTRAM，故只能称 register/logic banked-memory prototype。
- `results/publication_scale_banked_service_sim.json` / `docs/publication_scale_banked_service_sim.md`：queue-integrated banked service 的四帧 FIFO/backpressure/commit xsim 证据。
- `results/publication_scale_banked_service_vivado_ooc.json` / `docs/publication_scale_banked_service_vivado_ooc.md`：8 ns queue-integrated banked service OOC P&R；WNS +0.367 ns、WHS +0.043 ns、51,630 LUT/12,812 FF/8 DSP、0 BRAM/3,248 LUTRAM、1.171 W vectorless。该功耗是 vectorless estimate，不是板级实测 energy。
- `results/banked_packet_router_sim.json` / `docs/banked_packet_router_sim.md`：四-lane packetized crossbar→四个 depth-2 bank FIFO 的 xsim 证据；48 accepted/48 delivered/0 dropped，14 bank conflicts、62 congestion stalls、76 retries，并检查 per-bank FIFO order。
- `results/banked_packet_router_arbitration_comparison.json` / `docs/banked_packet_router_arbitration_comparison.md`：同一 xcku5p、4-lane/4-bank/FIFO-depth-2 和 I/O-delay boundary 下的 fixed-priority / round-robin matched OOC。两者均 fully routed 并闭合 5 ns：fixed WNS +1.043 ns、1,132 LUT/692 FF；round-robin WNS +0.339 ns、1,129 LUT/700 FF。8 ns 对应 WNS 为 +3.623 / +2.449 ns。功耗仍是 vectorless，且这是 standalone traffic primitive，不是完整 multi-hop NoC、decoder integration 或板级结果。
- `results/publication_scale_banked_packet_service_sim.json` / `docs/publication_scale_banked_packet_service_sim.md`：packet router→45×64-bit packet reassembly→真实 BB-12x6 banked decoder service 的四帧 xsim 端到端证据；180 accepted/180 delivered/0 dropped，bit-exact reassembly，FIFO commit，conflict/congestion/retry 计数和 1/1/1/12 迭代结果。
- `results/publication_scale_banked_packet_service_vivado_ooc.json` / `docs/publication_scale_banked_packet_service_vivado_ooc.md`：上述 packet-to-decoder scoped integration 的 8 ns routed OOC；WNS +0.400 ns、WHS +0.033 ns、59,244 LUT/16,862 FF/8 DSP/0 BRAM、66,657 fully routed nets、1.320 W vectorless。该结果不是完整 multi-hop NoC、BRAM/SRAM closure、板级 readback 或实测 energy。
- `results/kcu116_e2e_jtag_verify.json` / `board/reports/hardware_kc116_e2e_result.txt`：2026-08-19 重新执行的 KCU116 JTAG USER1 固定帧验证；仅证明一个 deterministic C=8/V=12 noisy frame，不等于 programmable multi-frame 或 production-scale closure。
- `results/schedule_baselines.json` / `docs/schedule_baselines.md`：统一硬件与 grouped-update 语义下的 flooding/clustered/layered baseline matrix。
- `results/publication_scale_banked_hardware_baselines.json` / `docs/publication_scale_banked_hardware_baselines.md`：同一 xcku5p BRAM-backed publication-scale datapath 的 layered/clustered2/grouped4 matched hardware matrix；三行均 xsim 通过并在 8 ns routed OOC 闭合，功耗仍为 vectorless estimate。
- `results/publication_scale_flooding_bram_sim.json` / `docs/publication_scale_flooding_bram_sim.md`：storage-normalized full-flooding snapshot 的 16-frame Python↔Vivado xsim contract；使用 4 个 message RAMB36E2 + 8 个 snapshot RAMB36E2，检查收敛、失败控制、snapshot freeze/commit、bank conflict/replay 与 frame cycles。
- `results/publication_scale_flooding_bram_service_vivado_ooc_5ns_sharedaccum_convreg_current.json` / `docs/publication_scale_flooding_bram_service_vivado_ooc_5ns_sharedaccum_convreg_current.md`：当前源码的 BRAM-backed full-flooding queue-integrated service 在 5 ns 下 fully routed/timing met，WNS +0.134 ns、WHS +0.041 ns、33,995 LUT/11,684 FF/92 RAMB36/8 DSP、1.469 W Vivado vectorless。完整 92-BRAM service 为两个 2,840-bit-wide depth-2 full-frame FIFO 的 80 个 width-banked RAMB36，加 4 message 与 8 snapshot RAMB36；早期文档中的“12 BRAM”只覆盖 decoder store，不是完整 service。该结果是 FPGA OOC allocation，不是 ASIC SRAM 或板级能耗。
- `results/sky130_packet_reassembly_sram_calibration.json` / `docs/sky130_packet_reassembly_sram_calibration.md`：packet-reassembly-only 的公开 OpenRAM/SKY130 macro mapping；固定源 commit 和输入 SHA-256，从 LEF/Liberty/HTML/config/log 交叉解析 `32x256 1rw1r`、TT/1.8 V/25 C、面积/漏电/Fmax/active power，并把生产 RTL 的四个 `12x72` bank 映射为 12 macros。结果为 `2.2885506 mm^2` macro-only area、`0.114192 mW` nominal leakage 和 `2.397350 nJ/frame` datasheet-power/Fmax proxy；不是 measured energy，且源 datasheet 报告 analytical model 与 10 DRC errors，不能称为 tapeout-clean ASIC SRAM。
- `results/sky130_axku5_storage_system_calibration.json` / `docs/sky130_axku5_storage_system_calibration.md`：把 canonical AXKU5 image 的全部 151 RAMB36 ownership 扩展为 whole-image SRAM mapping/activity proxy，覆盖 parser、reassembly、两级 admission FIFO、decoder message/snapshot 与 response queue。架构保持映射需要 438 个 `32x256 1rw1r` macros，macro-only area `83.5320969 mm^2`、nominal leakage `4.168008 mW`；普通 UART 1/12-iteration access proxy 为 `20.373179/115.648508 nJ/frame`。这些仍是 datasheet-power/Fmax proxy，不是 post-layout、SPICE、silicon 或 board-measured energy。
- `results/publication_scale_flooding_bram_service_sim.json` / `docs/publication_scale_flooding_bram_service_sim.md`：BRAM-backed full-flooding queue/service xsim；四帧 FIFO commit 通过，三帧收敛、一帧最大迭代失败，835 cycles/frame（收敛）与 9228 cycles/frame（12-iteration 负控制）；artifact 记录每帧 snapshot grants/mismatches/write cycles/write commits/flooding commits，使用 4 message + 8 snapshot RAMB36E2。
- `results/publication_scale_flooding_multihop_packet_service_sim.json` / `docs/publication_scale_flooding_multihop_packet_service_sim.md`：BRAM-backed full-flooding packet→two-hop fabric→bit-exact reassembly→queue/service 的端到端 xsim；4 frames/180 packets lossless，FIFO commit order，360 forwarded hops，snapshot grant mismatch=0。
- `results/publication_scale_flooding_multihop_packet_service_vivado_ooc_8ns.json` / `docs/publication_scale_flooding_multihop_packet_service_vivado_ooc_8ns.md`：上述 scoped flooding packet integration 的 8 ns routed OOC；WNS +1.024 ns / 143.35 MHz，12 BRAM36，0 unrouted nets，0.864 W vectorless；5 ns secondary point WNS +0.104 ns / 204.25 MHz。它仍不是 general adaptive NoC、完整 front-end、板级 readback 或实测 energy。
- `results/publication_scale_flooding_bram_service_vivado_ooc_8ns_sharedaccum.json` / `docs/publication_scale_flooding_bram_service_vivado_ooc_8ns_sharedaccum.md`：fixed-lane/shared-accumulation queue-integrated full-flooding service routed OOC；8 ns WNS +0.920 ns / 141.24 MHz，12 BRAM36，0 unrouted nets，33,558 LUT/11,550 FF/8 DSP，0.931 W vectorless；hierarchy evidence 为 4 message + 8 snapshot RAMB36，timing endpoint evidence 为 12 个 unique RAMB36 primitive。
- `results/publication_scale_flooding_bram_service_vivado_ooc_5ns_sharedaccum_convreg.json` / `docs/publication_scale_flooding_bram_service_vivado_ooc_5ns_sharedaccum_convreg.md`：历史 5 ns pre-current-source artifact（WNS +0.184 ns、33,921 LUT/11,673 FF）。其中 12 RAMB36 是 decoder message/snapshot store 的局部计数；完整 queue-integrated service 的权威当前结果为上一条的 92 RAMB36。该历史行不用于当前资源主张。
- `docs/finite_buffer_validation.md`：有限 resident/ingress queue、source backpressure、tail-drop 与 loss-inclusive SLO 的 1,000-frame 压力验证。
- `docs/latest_baseline_audit_2026.md`：2026 年 baseline 可执行状态、匹配条件与公平比较 gate。
- `results/heldout_generalization_1000.json` / `docs/heldout_generalization_1000.md`：1,000-frame、3-seed held-out generalization 与 P99.9 统计。
- `results/rtl_validation.json` / `docs/rtl_validation.md`：控制、Q6 PE、同步 message bank 和 full MVP 的 RTL evidence gate。
- `docs/rtl_architecture.md`：RTL 模块边界、算术语义、资源映射和证据限制。
- `docs/vivado_ooc_flow.md`：严格 I/O 约束、setup/hold、routing、methodology 与 power 的远程 Vivado 执行契约。
- `docs/paper_bar_audit.md`：当前 CCF-A 投稿成熟度与下一步硬门槛。
- `paper/main.tex` / `paper/generated/evidence_manifest.json`：聚焦 cycle-guided mapping、burst-tail runtime、XCKU5P physical execution 与 scoped BP-SF/circuit evidence 的可编译两栏论文主稿；12 个权威 JSON 自动绑定 headline 数字与表格，`python3 paper/generate_evidence.py --check` 检查 stale claim，`cd paper && make` 生成当前 4 页 evidence-bound PDF。它不改变严格 gate 状态，仍不允许把 Vivado vectorless power 写成板级能耗。

## 判定标准

H1 直接复用 Roadmap Gate A 的两个条件：

1. baseline bank-conflict stall cycles 占总周期超过 25%；
2. 理想无冲突 memory 比 baseline 至少快 30%。

满足至少两项 H1 条件即 PASS。Demo 还额外检查不同 banking 的 stall 差异是否达到 1.5×。

架构模型把每条 Tanner-edge message 视为独立记录，并支持多种 qubit-to-bank layout、每帧 bank rotation 与多帧 ready-cluster issue。完整逐周期语义见 `docs/simulator_spec.md`。

H3 对原 schedule 与 `W=4` bounded bank-aware schedule 使用完全相同的错误样本，并报告：

- LER 与 Wilson 95% confidence interval；
- paired exact test；
- 相对 LER 变化；
- correction mismatch 与平均迭代次数。

没有显著变差，且置信区间重叠或相对退化不超过 5%，判为 PASS。

## 模型边界

- 主体软件基线仍以 code-capacity X errors 为主；另有独立、scoped 的 BB-12x6 circuit-level CSS-X detector audit，但尚无完整 space-time decoder、CSS-Z 联合评测或 calibrated QPU noise。
- 周期数来自 architecture model，不是 Python wall-clock 或真实 ASIC 测量。
- 当前覆盖 HGP、BB 和 Toric 三个 family，但 M3 的显著收益只在 HGP/BB microburst 上成立，Toric 使用安全回退。
- M1 oracle 优化两个可解释静态目标，不是完整 cycle-optimal mapping oracle。
- M3 不允许访问 frame 的最终迭代数；deadline 是固定 workload SLO，不按单帧实际难度设置。
- uniform arrival 下 M3 没有稳定收益，因此 runtime 必须由 burst/frame-pressure 激活。
- H3 PASS 只代表窗口重排的 LER 安全性；该最小启发式是否加速不参与 H3 判定。

## AXKU5/ACKU5 physical UART evidence (2026-08-21)

The physically connected board is an ALINX AXKU5 carrier with an ACKU5
`xcku5p-ffvb676-2-e` target. The confidential ACKU5 schematic is kept outside
publication artifacts; its reviewed net mapping and the checked-in constraints
bind AC13/AC14 to the 200 MHz differential clock and AE15/AD15 to FPGA UART
RX/TX. The current promotion-stress-capable RAMB36E2 image closes at WNS
+0.029 ns / WHS +0.010 ns with zero unrouted nets and zero DRC errors, using
58,963 LUT, 35,774 FF, 151 RAMB36, and 8 DSP48E2. Its bitstream SHA-256 is
`c764d56b0db158b6697ffdcd5125cf295e0c3f4701d946d87e2fa58071d549c6`. It was
programmed through Digilent JTAG target `210512180081`, then exercised through
the enumerated CP2102N at 115200 baud.

```bash
python3 scripts/summarize_axku5_flooding_credit_mesh_vc_programmable_200mhz_build.py
python3 scripts/summarize_axku5_programming.py \
  --log results/axku5_acku5_programming_c764d56b_20260821.log \
  --bitstream board/bitstreams/bp_axku5_flooding_credit_mesh_vc_programmable_200mhz.bit \
  --output results/axku5_acku5_programming_c764d56b_20260821.json \
  --report docs/axku5_acku5_programming_c764d56b_20260821.md
python3 scripts/run_axku5_uart_overflow_recovery.py
# Reprogram the same bitstream to reset cumulative counters before each clean suite.
python3 scripts/run_axku5_uart_burst_suite.py \
  --program-log results/axku5_acku5_programming_burst.log \
  --program-json results/axku5_acku5_programming_burst.json
PYTHONPATH=. python3 scripts/run_axku5_uart_sustained_workload.py \
  --promotion-stress --active-seconds 10 --min-frames 100 \
  --build-artifact results/axku5_flooding_credit_mesh_vc_programmable_200mhz_build.json \
  --program-log results/axku5_acku5_programming_c764d56b_20260821.log \
  --output results/axku5_acku5_uart_promotion_stress_c764d56b_20260821.json \
  --report docs/axku5_acku5_uart_promotion_stress_c764d56b_20260821.md
python3 scripts/audit_ccfa_gates.py
```

The physical 4/16/32-frame suite passes ordered non-zero tag readback, CRC and
geometry checks, exact accepted/admitted/committed deltas, and zero
parser/CRC/service loss. A separate physical CP2102N command triggers a bounded
64-candidate stream on chip at 200 MHz: the observed result is exactly `64 = 7
accepted + 57 parser drops`; all accepted candidates commit in order, the FIFOs
drain, and a fresh recovery frame completes. Canonical artifacts are
`results/axku5_acku5_uart_burst_suite.json` and
`results/axku5_acku5_uart_overflow_recovery.json`. The same SHA-bound physical
image also passes a promotion-stress session with 2,387,109
requested/accepted/committed frames over 2,000,392,406 active FPGA cycles
(10.00196203 s), 238,664.073 frames/s, and 837.997932 active cycles/frame. It
conserves exactly 107,419,905 accepted/delivered packets, records 54,903,507 VC
promotion events, observes escape-VC delivery and promotion stalls, and ends
quiescent with zero parser/service drops or monitor violations. The canonical
artifact is `results/axku5_acku5_uart_promotion_stress_c764d56b_20260821.json`. These are
physical throughput/integration measurements for the implemented 4x2
configuration, not unrestricted-traffic liveness or board-power measurements;
the current 2.029 W value remains a routed Vivado vectorless estimate and must
not be reported as measured energy.

## FPGA programmable end-to-end status

### AXKU5/ACKU5 external 12 V power capture workflow

Board power and energy/frame remain unmeasured. A strict five-repeat capture
workflow is now ready in `scripts/analyze_axku5_board_power.py`, with editable
metadata/sample templates under `docs/templates/`, a beginner wiring card in
`docs/axku5_power_measurement_quickstart_zh.md`, and the claim boundary in
`docs/axku5_power_measurement_path.md`. It integrates raw `V(t) * I(t)`, binds
each active window to the canonical bitstream SHA and hardware-counted FPGA
cycles/commits, and rejects missing calibration metadata, multiple supply paths,
loss, monitor violations, insufficient repeats, or meter/FPGA timing mismatch.
The workflow alone is not measurement evidence: Gates 3/4 stay PENDING until a
calibrated external 12 V trace is captured. The current `2.029 W` Vivado value is
still a routed vectorless estimate only.

```bash
python3 scripts/analyze_axku5_board_power.py \
  --samples results/axku5_acku5_board_power_samples.csv \
  --metadata results/axku5_acku5_board_power_metadata.json
python3 scripts/audit_ccfa_gates.py
```

The KCU116 path now includes a packetized programmable C=8/V=12 decoder demo:
UART RX, CRC-checked finite packet FIFO, decoder service, response FIFO, and
UART TX. Reproduce the RTL transport test with:

```bash
python scripts/run_board_programmable_sim.py
python scripts/run_rtl_cycle_trace_match.py
python scripts/summarize_kcu116_programmable_build.py
```

The routed bitstream is `board/bitstreams/bp_kc116_programmable.bit`; details
are in `docs/kcu116_programmable_multiframe.md`. This closes the small-code RTL
transport and routed-board-top build, but **does not** yet prove physical
KCU116 USB-UART multi-frame readback, production-scale decoder closure, or
measured energy. Those distinctions are intentional in the CCF-A audit.

- Historical direct KCU116 UART -> BRAM-backed flooding service path: four-frame xsim pass and routed bitstream build. Physical publication-scale readback is now supplied by the separate AXKU5/ACKU5 CP2102N integrated suite above; board-measured energy remains open.

### Publication-scale KCU116 flooding UART boundary (2026-08-20)

The direct publication-scale board target is now reproducible at `C=72,
V=144`:

```text
USB UART RX -> 355-byte CRC parser -> finite frame FIFO
            -> 4-message/8-snapshot RAMB36 flooding service
            -> 39-byte result response + 70-byte BPFS counter response
            -> USB UART TX
```

Run the checks from the repository root:

```bash
source /home/user/Xilinx/2026.1/Vivado/settings64.sh
python3 scripts/run_kcu116_flooding_programmable_sim.py
python3 scripts/summarize_kcu116_flooding_programmable_build.py
python3 -m unittest discover -s tests -p 'test_*.py'
```

The latest routed artifact is `results/kcu116_flooding_programmable_build.json`:
Vivado 2026.1 / `xcku5p-ffvb676-2-e`, 300.03 MHz board input and 100.01 MHz
decoder clock, WNS +2.258 ns, WHS +0.002 ns, zero unrouted nets, 44,038 LUT,
22,848 FF, 140 RAMB36, 8 DSP. The bitstream SHA-256 is
`2caf42d70d38f6474a7d9d438618e5f8a2c728b6994228bca0e28ab2f5bbcfcc`.
The reported 1.079 W is a routed Vivado vectorless estimate, not a board
measurement. The parser frame FIFO and both admission queues now have
explicit routed RAMB36E2 evidence, but synchronous-read alignment creates
substantial FF/LUT overhead; the UART top does not exercise the separate
deterministic multi-hop packet/NoC fabric, and physical CP2105 readback is
still pending.

A separate current-source direct-top 200 MHz implementation image is also
available. It uses an MMCM-generated 200.02 MHz decoder/UART clock and the
current-source implementation closes with zero unrouted nets, zero DRC errors,
WNS +0.265 ns / WHS +0.007 ns, and a provenance-matched bitstream. This is a
scoped implementation PASS for Gate 5; it is not physical UART readback,
board-measured energy, packet/NoC board-boundary closure, or CCF-A readiness.
Reproduce it with:

```bash
source /home/user/Xilinx/2026.1/Vivado/settings64.sh
vivado -mode batch \
  -source board/scripts/build_bp_kc116_flooding_programmable_200mhz.tcl
python3 scripts/summarize_kcu116_flooding_programmable_200mhz_build.py
python3 scripts/audit_kcu116_storage_boundary.py
```

`audit_kcu116_storage_boundary.py` 生成非重复计数的 top-level/子层级资源边界与
835-cycle synchronous-BRAM convergent frame normalization；它不会把 Vivado hierarchy rows 重新相加，
也不会把 vectorless power 写成板级实测能耗。

The artifact is `results/kcu116_flooding_programmable_200mhz_build.json` and
the bitstream is `board/bitstreams/bp_kc116_flooding_programmable_200mhz.bit`.
Its current 1.527 W value is still a routed Vivado vectorless estimate, not measured
board energy; physical UART readback and the scoped packet/NoC boundary are now closed, a clean-room Valls same-contract published-architecture baseline is available, and the directly admitted escape-VC class now has a continuing-traffic QoS bound; adaptive-VC/promotion guarantees and energy-normalized comparison remain outside the proved scope.