diff --git a/components/controller/rf_phy_driver.h b/components/controller/rf_phy_driver.h index f2c3d8850ab96bba7ef5acd342520a158c218170..b09f10eceb36d06f7879a4a8bec38710856a9d67 100755 --- a/components/controller/rf_phy_driver.h +++ b/components/controller/rf_phy_driver.h @@ -120,7 +120,7 @@ extern volatile uint32_t g_dtmAccessCode ; /******************************************************************************* * MACRO */ - +#define RF_PHY_EXT_PREAMBLE_US (8) // ext ble preamble length #define PHY_REG_RD(x) *(volatile uint32_t *)(x) #define PHY_REG_WT(x,y) *(volatile uint32_t *)(x) = (y) @@ -208,6 +208,7 @@ extern volatile uint32_t g_dtmAccessCode ; #define PKT_FMT_BLR500K 3 #define PKT_FMT_BLR125K 4 +#ifdef CONFIG_CHIP_PACKAGE_QFN32 #define RF_PHY_TX_POWER_EXTRA_MAX 0x3f #define RF_PHY_TX_POWER_MAX 0x1f #define RF_PHY_TX_POWER_MIN 0x00 @@ -218,6 +219,27 @@ extern volatile uint32_t g_dtmAccessCode ; #define RF_PHY_TX_POWER_N5DBM 0x0a #define RF_PHY_TX_POWER_N20DBM 0x01 +#elif defined(CONFIG_CHIP_PACKAGE_SOP16) || defined(CONFIG_CHIP_PACKAGE_SOP24) + +#define RF_PHY_TX_POWER_EXTRA_MAX 0x3f +#define RF_PHY_TX_POWER_MAX 0x1f +#define RF_PHY_TX_POWER_MIN 0x00 + +#define RF_PHY_TX_POWER_5DBM 0x1d +#define RF_PHY_TX_POWER_4DBM 0x17 +#define RF_PHY_TX_POWER_3DBM 0x15 +#define RF_PHY_TX_POWER_0DBM 0x0d + +#define RF_PHY_TX_POWER_N2DBM 0x0a +#define RF_PHY_TX_POWER_N5DBM 0x06 +#define RF_PHY_TX_POWER_N6DBM 0x05 +#define RF_PHY_TX_POWER_N10DBM 0x03 +#define RF_PHY_TX_POWER_N15DBM 0x02 +#define RF_PHY_TX_POWER_N20DBM 0x01 +#else + #error "Please check chip package type" +#endif + #define RF_PHY_FREQ_FOFF_00KHZ 0 #define RF_PHY_FREQ_FOFF_20KHZ 5 #define RF_PHY_FREQ_FOFF_40KHZ 10 diff --git a/components/driver/inc/gpio.h b/components/driver/inc/gpio.h index 31764281bdde7d18d4687aaae8877a798d297fe7..d23a22db9b71663ab1507d06a259117eca977041 100755 --- a/components/driver/inc/gpio.h +++ b/components/driver/inc/gpio.h @@ -204,5 +204,6 @@ int phy_gpioretention_unregister(gpio_pin_e pin); int phy_gpioretention_register(gpio_pin_e pin); void phy_gpioretention_prepare_sleep_action(void); void phy_gpioretention_prepare_wakeup_action(void); +__attribute__((section(".__sram.code"))) void phy_gpioretention_disable(void); #endif diff --git a/components/driver/src/clock.c b/components/driver/src/clock.c index f8a0d5558664138c4cba6a24827d2587f8eed8ee..8d7b0f3fe733261c3bfcc07cd86473a9162d224f 100755 --- a/components/driver/src/clock.c +++ b/components/driver/src/clock.c @@ -254,9 +254,11 @@ void hal_rtc_clock_config(CLK32K_e clk32Mode) subWriteReg(&(AP_AON->PMCTL0), 31, 27, 0x16); //pGlobal_config[LL_SWITCH]&=0xffffffee; } +#if !(defined(CONFIG_SYS_CLK_XTAL_16M) && CONFIG_SYS_CLK_XTAL_16M > 0) //ZQ 20200812 for rc32k wakeup subWriteReg(&(AP_AON->PMCTL0),28,28,0x1);//turn on 32kxtal subWriteReg(&(AP_AON->PMCTL1),18,17,0x0);// reduce 32kxtal bias current +#endif } uint32_t hal_systick(void) diff --git a/components/driver/src/gpio.c b/components/driver/src/gpio.c index d170f4c886c48e88a52173a6b90cc9a315d0d639..99e0f11c17911d4453043d2e9fa76311d42f81ed 100755 --- a/components/driver/src/gpio.c +++ b/components/driver/src/gpio.c @@ -553,6 +553,20 @@ __attribute__((section(".__sram.code"))) void phy_gpioretention_prepare_sleep_ac } } +__attribute__((section(".__sram.code"))) void phy_gpioretention_disable(void) +{ + gpio_pin_e pin=0; + + for(pin=0;pinPMCTL0 &= ~BIT(retention_reg[pin][1]); + } else { + AP_AON->IOCTL[retention_reg[pin][0]] &= ~BIT(retention_reg[pin][1]); + } + } +} + __attribute__((section(".__sram.code"))) void phy_gpioretention_prepare_wakeup_action(void) { gpio_pin_e pin=0; diff --git a/components/driver/src/phy_adc.c b/components/driver/src/phy_adc.c index b843d37d69bf6b6e5cf4f8e12dafb62d7fca664c..a15dccbf409f95d900d0da99f55b5598429a9187 100755 --- a/components/driver/src/phy_adc.c +++ b/components/driver/src/phy_adc.c @@ -1,46 +1,4 @@ -/************************************************************************************************** - - Phyplus Microelectronics Limited confidential and proprietary. - All rights reserved. - - IMPORTANT: All rights of this software belong to Phyplus Microelectronics - Limited ("Phyplus"). Your use of this Software is limited to those - specific rights granted under the terms of the business contract, the - confidential agreement, the non-disclosure agreement and any other forms - of agreements as a customer or a partner of Phyplus. You may not use this - Software unless you agree to abide by the terms of these agreements. - You acknowledge that the Software may not be modified, copied, - distributed or disclosed unless embedded on a Phyplus Bluetooth Low Energy - (BLE) integrated circuit, either as a product or is integrated into your - products. Other than for the aforementioned purposes, you may not use, - reproduce, copy, prepare derivative works of, modify, distribute, perform, - display or sell this Software and/or its documentation for any purposes. - - YOU FURTHER ACKNOWLEDGE AND AGREE THAT THE SOFTWARE AND DOCUMENTATION ARE - PROVIDED AS IS WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESS OR IMPLIED, - INCLUDING WITHOUT LIMITATION, ANY WARRANTY OF MERCHANTABILITY, TITLE, - NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL - PHYPLUS OR ITS SUBSIDIARIES BE LIABLE OR OBLIGATED UNDER CONTRACT, - NEGLIGENCE, STRICT LIABILITY, CONTRIBUTION, BREACH OF WARRANTY, OR OTHER - LEGAL EQUITABLE THEORY ANY DIRECT OR INDIRECT DAMAGES OR EXPENSES - INCLUDING BUT NOT LIMITED TO ANY INCIDENTAL, SPECIAL, INDIRECT, PUNITIVE - OR CONSEQUENTIAL DAMAGES, LOST PROFITS OR LOST DATA, COST OF PROCUREMENT - OF SUBSTITUTE GOODS, TECHNOLOGY, SERVICES, OR ANY CLAIMS BY THIRD PARTIES - (INCLUDING BUT NOT LIMITED TO ANY DEFENSE THEREOF), OR OTHER SIMILAR COSTS. - -**************************************************************************************************/ - -/******************************************************************************* -* @file adc.c -* @brief Contains all functions support for adc driver -* @version 0.0 -* @date 18. Oct. 2017 -* @author qing.han -* -* Copyright(C) 2016, PhyPlus Semiconductor -* All rights reserved. -* -*******************************************************************************/ + #include #include "error.h" #include "gpio.h" @@ -264,7 +222,7 @@ int phy_adc_start_int_dis(void) //hal_pwrmgr_lock(MOD_ADCC); //JUMP_FUNCTION(V29_IRQ_HANDLER) = (uint32_t)&hal_ADC_IRQHandler; - MASK_ADC_INT; + AP_ADCC->intr_mask = 0x1ff; drv_irq_disable(ADCC_IRQn); drv_irq_unregister(ADCC_IRQn); @@ -384,7 +342,7 @@ int phy_adc_config_channel(adc_Cfg_t cfg, adc_event_cb_t evt_handler) for (i = 2; i < 8; i++) { if (cfg.channel & BIT(i)) { gpio_pin_e pin = s_pinmap[i]; - phy_gpio_pull_set(pin,GPIO_FLOATING); + phy_gpio_pull_set(pin,GPIO_FLOATING); phy_gpio_ds_control(pin, Bit_ENABLE); phy_gpio_cfg_analog_io(pin, Bit_ENABLE); @@ -470,7 +428,7 @@ int phy_adc_config_channel(adc_Cfg_t cfg, adc_event_cb_t evt_handler) //LOG("%d %d %x\n",pin,pin_neg,*(volatile int*)0x40003800); phy_gpio_pull_set(pin,GPIO_FLOATING); - phy_gpio_pull_set(pin_neg,GPIO_FLOATING); + phy_gpio_pull_set(pin_neg,GPIO_FLOATING); phy_gpio_cfg_analog_io(pin, Bit_ENABLE); phy_gpio_cfg_analog_io(pin_neg, Bit_ENABLE); //LOG("%d %d %x\n",pin,pin_neg,*(volatile int*)0x40003800); @@ -537,13 +495,16 @@ int phy_adc_stop(void) **************************************************************************************/ static void phy_adc_load_calibration_value(void) { - if (adc_cal_read_flag == FALSE) { - adc_cal_read_flag = TRUE; - adc_cal_negtive = read_reg(0x11001000) & 0x0fff; - adc_cal_postive = (read_reg(0x11001000) >> 16) & 0x0fff; - //printf("->adc_cal_negtive:%x\n",adc_cal_negtive); - //printf("->adc_cal_postive:%x\n",adc_cal_postive); - } + if (adc_cal_read_flag == FALSE) { + adc_cal_read_flag = TRUE; + adc_cal_negtive = read_reg(0x11001000) & 0x0fff; + adc_cal_postive = (read_reg(0x11001000) >> 16) & 0x0fff; + + if((adc_cal_negtive < 0x733)||(adc_cal_negtive > 0x8cc) ||(adc_cal_postive < 0x733)||(adc_cal_postive > 0x8cc)){ + adc_cal_negtive = 0xfff; + adc_cal_postive = 0xfff; + } + } } @@ -561,6 +522,7 @@ const unsigned int adc_Lambda[ADC_CH_NUM] = 4047198,//P20, 0,//GPIO_DUMMY, //ADC_CH_VOICE =8, + }; //#elif(SDK_VER_CHIP == __DEF_CHIP_TSOP16__) @@ -579,6 +541,7 @@ const unsigned short adc_Lambda[ADC_CH_NUM] = }; */ //#endif + int phy_adc_value_cal(adc_CH_t ch, uint16_t *buf, uint32_t size, bool high_resol, bool diff_mode) { volatile float result = 0.0; @@ -586,7 +549,7 @@ int phy_adc_value_cal(adc_CH_t ch, uint16_t *buf, uint32_t size, bool high_resol phy_adc_load_calibration_value(); result = (float)buf[0]; //printf("\n->%d %d %d %d\n",ch,adc_Lambda[ch],(int)result,size); - //printf("\n->%d\n",(int)result); + //printf("[%d]",(int)result); if((adc_cal_postive!=0xfff)&&(adc_cal_negtive!=0xfff)){ float delta = ((int)(adc_cal_postive-adc_cal_negtive))/2.0; if(ch&0x01) @@ -617,6 +580,8 @@ int phy_adc_value_cal(adc_CH_t ch, uint16_t *buf, uint32_t size, bool high_resol } + + /* */ #include @@ -666,7 +631,7 @@ int32_t drv_adc_uninitialize(adc_handle_t handle) //hal_pwrmgr_register(MOD_ADCC,NULL,NULL); phy_clear_adcc_cfg(); //hal_adc_init(); - AP_AON->PMCTL2_1 = 0x00; + AP_AON->PMCTL2_1 =0x00; hal_clk_gate_disable(MOD_ADCC); return 0; @@ -920,10 +885,13 @@ static int read_multiple_channel_n(adc_handle_t handle, uint32_t *data, uint32_t break; ch_cur=(ch%2)?(ch-1):(ch+1); + + while(!(read_reg(0x4005003c)&BIT(ch_cur))); + + subWriteReg(0x40050038,ch_cur,ch_cur,1); - ++i; - i=i%8; - + ++i; + i&=0x07; adc_sum = 0; for (n = 0; n < 29; n++) { adc_sum += (uint16_t)(read_reg(ADC_CH_BASE + (ch_cur * 0x80) + ((n+2) * 4))&0xfff); @@ -938,6 +906,7 @@ static int read_multiple_channel_n(adc_handle_t handle, uint32_t *data, uint32_t //printf("[%x %x ]",s_adc_cfg.is_high_resolution,s_adc_cfg.is_differential_mode); //printf("[%d %d %d]",i,high_resol,diff_mode); data[i] = phy_adc_value_cal(ch,adc_avg,1,high_resol,diff_mode); + //printf("[%d %d %d ] ",i,data[i],ch_cur); ch++; diff --git a/components/inc/mcu.h b/components/inc/mcu.h index cb00fde109925026908680f41a64dc83279a32fd..cb5a4a9f13d9cb8ca9c7e07b3692d2b8cd844fbb 100755 --- a/components/inc/mcu.h +++ b/components/inc/mcu.h @@ -96,9 +96,11 @@ #define HAL_ICER *((volatile uint32_t *)(0xe000e180)) //subWriteReg: write value to register zone: bit[high:low] -#define subWriteReg(addr,high,low,value) write_reg(addr,(read_reg(addr)&\ +#define subWriteReg(addr,high,low,value) {write_reg(addr,(read_reg(addr)&\ (~((((unsigned int)1<<((high)-(low)+1))-1)<<(low))))|\ - ((unsigned int)(value)<<(low))) +((unsigned int)(value)<<(low)));__asm volatile("nop");} + + #define TIME_BASE (0x003fffff) // 24bit count shift 2 bit as 1us/bit #define TIME_DELTA(x,y) ( (x>=y) ? x-y : TIME_BASE-y+x ) diff --git a/components/inc/types.h b/components/inc/types.h index d1c404bc2c1cb85fc489599dafd7fca46463d5a4..147692285c519207bd6dbbc7b697eff5a3099455 100755 --- a/components/inc/types.h +++ b/components/inc/types.h @@ -169,7 +169,7 @@ typedef struct _comm_evt_t { typedef void (*comm_cb_t)(comm_evt_t *pev); - +#define __ATTR_FUNC_XIP__(fn) __attribute__(( section("__xip_function__."#fn))) fn #endif diff --git a/csi_drivers/dw_usart.c b/csi_drivers/dw_usart.c index 33f29dc69b809194199c7462ff98b0ec7d6903e1..ac8b0327264798075f6080c7903e9d41df762867 100755 --- a/csi_drivers/dw_usart.c +++ b/csi_drivers/dw_usart.c @@ -756,37 +756,44 @@ __attribute__((section(".__sram.code"))) void csi_usart_prepare_sleep_action(vo uint32_t addr = 0x40004000; uint32_t set_fcr_value; while (!(*(volatile uint32_t *)(addr + 0x7c) & 0x4)); - for(int i = 0; i < 4 ; i++) { - if(uart_tx_rx_pin[i] != 0xff) { - phy_gpio_fmux(uart_tx_rx_pin[i], Bit_DISABLE); - } - } +// for(int i = 0; i < 4 ; i++) { +// if(uart_tx_rx_pin[i] != 0xff) { +// phy_gpio_fmux(uart_tx_rx_pin[i], Bit_DISABLE); +// } +// } +// while ((*(volatile uint32_t *)(addr + 0x7c) & 0x1)); set_fcr_value = (*(volatile uint32_t *)(addr + 0x98) & 0x01) | ((*(volatile uint32_t *)(addr + 0x94) & 0x01)<<3) | ((*(volatile uint32_t *)(addr + 0x9c) & 0x03)<<6) | ((*(volatile uint32_t *)(addr + 0xa0) & 0x03)<<4) | DW_FCR_RFIFOR | DW_FCR_XFIFOR; + + registers_save(&usart_regs_saved[3], (uint32_t *)addr + 3, 1); + + do{ - *(volatile uint32_t *)(addr + 0x8) = set_fcr_value; - }while (*(volatile uint32_t *)(addr + 0x7c) & 0x1); - *(volatile uint32_t *)(addr + 0xc) |= 0x80; + *(volatile uint32_t *)(addr + 0xc) = 0x80; + }while(*(volatile uint32_t *)(addr + 0xc) != 0x80); registers_save((uint32_t *)usart_regs_saved, (uint32_t *)addr, 2); - *(volatile uint32_t *)(addr + 0xc) &= ~0x80; + do{ + *(volatile uint32_t *)(addr + 0xc) = usart_regs_saved[3]; + }while(*(volatile uint32_t *)(addr + 0xc) != usart_regs_saved[3]); registers_save(&usart_regs_saved[2], (uint32_t *)addr + 1, 1); - registers_save(&usart_regs_saved[3], (uint32_t *)addr + 3, 2); - usart_regs_saved[4] = set_fcr_value; + usart_regs_saved[4] = set_fcr_value; } __attribute__((section(".__sram.code"))) void csi_usart_wakeup_sleep_action(void) { uint32_t addr = 0x40004000; - //while (*(volatile uint32_t *)(addr + 0x7c) & 0x1); - *(volatile uint32_t *)(addr + 0xc) |= 0x80; + do{ + *(volatile uint32_t *)(addr + 0xc) = 0x80; + }while(*(volatile uint32_t *)(addr + 0xc) != 0x80); registers_save((uint32_t *)addr, usart_regs_saved, 2); - *(volatile uint32_t *)(addr + 0xc) &= ~0x80; + do{ + *(volatile uint32_t *)(addr + 0xc) = usart_regs_saved[3]; + }while(*(volatile uint32_t *)(addr + 0xc) != usart_regs_saved[3]); registers_save((uint32_t *)addr + 1, &usart_regs_saved[2], 1); - registers_save((uint32_t *)addr + 3, &usart_regs_saved[3], 2); registers_save((uint32_t *)addr + 2, &usart_regs_saved[4], 1); } diff --git a/csi_drivers/dw_wdt.c b/csi_drivers/dw_wdt.c index 0fcf3fdbbc17c6de1fb96b577b4beeb3ff15de84..fcfc5b0ebb35bcb994a5473c12540462ee4516d5 100755 --- a/csi_drivers/dw_wdt.c +++ b/csi_drivers/dw_wdt.c @@ -34,7 +34,8 @@ //#define SYSTEM_CLOCK_MS (30000 / 1000) //uint32_t timeout_ms[16]; -const uint32_t timeout_ms[8] = {2000, 4000, 8000, 16000, 32000, 64000, 128000, 256000}; +//const uint32_t timeout_ms[8] = {2000, 4000, 8000, 16000, 32000, 64000, 128000, 256000}; +uint32_t timeout_ms[8] = {2000, 4000, 8000, 16000, 32000, 64000, 128000, 256000}; typedef struct { #ifdef CONFIG_LPM uint8_t wdt_power_status; @@ -52,7 +53,7 @@ static dw_wdt_priv_t wdt_instance[CONFIG_WDT_NUM]; static inline void dw_wdt_enable(dw_wdt_reg_t *addr) { - addr->WDT_CR = 0x1F; + addr->WDT_CR = 0x1D; } static inline void dw_wdt_disable(dw_wdt_reg_t *addr) @@ -197,7 +198,7 @@ int32_t csi_wdt_power_control(wdt_handle_t handle, csi_power_stat_e state) \param[in] value the timeout value(ms) \ref:timeout_ms[] \return \ref execution_status */ -int32_t csi_wdt_set_timeout(wdt_handle_t handle, uint32_t value) +__attribute__((section(".__sram.code"))) int32_t csi_wdt_set_timeout(wdt_handle_t handle, uint32_t value) { WDT_NULL_PARAM_CHK(handle); uint32_t i = 0u; @@ -275,7 +276,7 @@ int32_t csi_wdt_stop(wdt_handle_t handle) \param[in] handle wdt handle to operate. \return \ref execution_status */ -int32_t csi_wdt_restart(wdt_handle_t handle) +__attribute__((section(".__sram.code"))) int32_t csi_wdt_restart(wdt_handle_t handle) { WDT_NULL_PARAM_CHK(handle); diff --git a/csi_drivers/spif.c b/csi_drivers/spif.c index c908237718c4486fcf5aef2915554a83e6a3497c..f737ee992b63431f6048b3f7207845636a43ec57 100755 --- a/csi_drivers/spif.c +++ b/csi_drivers/spif.c @@ -55,6 +55,11 @@ extern void spif_set_deep_sleep(void); extern void spif_release_deep_sleep(void); extern void spif_cmd(uint8_t op, uint8_t addrlen, uint8_t rdlen, uint8_t wrlen, uint8_t mbit, uint8_t dummy); extern void spif_rddata(uint8_t *data, uint8_t len); +extern void WaitRTCCount(uint32_t rtcDelyCnt); +extern uint8_t spif_flash_status_reg_0(void); +extern uint8_t spif_flash_status_reg_1(void); +extern void spif_wrdata(uint8_t* data, uint8_t len); +extern void ll_patch_restore(uint8_t flg); #define SPIF_TIMEOUT 1000000 @@ -98,6 +103,7 @@ __attribute__((section(".__sram.code"))) static inline uint32_t spif_lock() VIC->ICER[0] = 0xFFFFFFFF; //enable ll irq and tim1 irq VIC->ISER[0] = 0x100010; + ll_patch_restore(0); HAL_EXIT_CRITICAL_SECTION(); return vic_iser; } @@ -107,6 +113,7 @@ __attribute__((section(".__sram.code"))) static inline void spif_unlock(uint32_ _HAL_CS_ALLOC_(); HAL_ENTER_CRITICAL_SECTION(); VIC->ISER[0] = vic_iser; + ll_patch_restore(1); HAL_EXIT_CRITICAL_SECTION(); } @@ -131,7 +138,7 @@ __attribute__((section(".__sram.code"))) static inline void spif_unlock(uint32_ #define spif_wait_nobusy(flg, tout_ns, return_val) {if(_spif_wait_nobusy_x(flg, tout_ns)){if(return_val){ return return_val;}}} -__attribute__((section(".__sram.code"))) static void hal_cache_tag_flush(void) +__attribute__((section(".__sram.code"))) void hal_cache_tag_flush(void) { _HAL_CS_ALLOC_(); HAL_ENTER_CRITICAL_SECTION(); @@ -139,10 +146,10 @@ __attribute__((section(".__sram.code"))) static void hal_cache_tag_flush(void) volatile int dly = 8; if (cb == 0) { - AP_CACHE->CTRL0 = 0x02; + AP_PCR->CACHE_BYPASS = 1; } - + AP_CACHE->CTRL0 = 0x02; while (dly--) { ; }; @@ -154,10 +161,10 @@ __attribute__((section(".__sram.code"))) static void hal_cache_tag_flush(void) while (dly--) { ; }; - + AP_CACHE->CTRL0 = 0; if (cb == 0) { AP_PCR->CACHE_BYPASS = 0; - AP_CACHE->CTRL0 = 0; + } HAL_EXIT_CRITICAL_SECTION(); @@ -178,6 +185,7 @@ __attribute__((section(".__sram.code"))) static int _spif_wait_nobusy_x(uint8_t volatile int tout = (int)(tout_ns); for (; tout ; tout --) { + WaitRTCCount(1);//increase polling interval status = _spif_read_status_reg_x(); if ((status & flg) == 0) { @@ -188,6 +196,89 @@ __attribute__((section(".__sram.code"))) static int _spif_wait_nobusy_x(uint8_t return PPlus_ERR_BUSY; } +__attribute__((section(".__sram.code"))) uint16_t hal_flash_lock_status() +{ + uint16_t status = _spif_read_status_reg_x(); + if(s_spif_ctx.mid == FLASH_TH_ID) + return status&(FCMD_DATAPRO_AREA_512_TH | FCMD_SRP_REG_TH); + return status&(FCMD_DATAPRO_AREA_512 | FCMD_SRP_REG); +} + +__attribute__((section(".__sram.code"))) uint8_t hal_flash_write_disable(void) +{ + uint32_t cs = spif_lock(); + uint8_t status; + status = _spif_read_status_reg_x(); + if(status & SFLG_WEL) + { + AP_SPIF->fcmd = XFRD_FCMD_WRDI; + SPIF_STATUS_WAIT_IDLE(SPIF_WAIT_IDLE_CYC); + spif_wait_nobusy(SFLG_WIP, SPIF_TIMEOUT, PPlus_ERR_BUSY); + } + spif_unlock(cs); + return 0; +} + +__attribute__((section(".__sram.code"))) int hal_flash_lock(uint16_t area) +{ + uint32_t cs = spif_lock(); + if(s_spif_ctx.mid == FLASH_TH_ID) + { + area |= FCMD_DATAPRO_AREA_512_TH; + area |= FCMD_SRP_REG_TH; + } + else + { + area &= FCMD_DATAPRO_AREA_512; + area |= FCMD_SRP_REG; + } + if(area != hal_flash_lock_status()) + { + if(s_spif_ctx.mid == FLASH_TH_ID) + { + area |= FCMD_SRP_REG_TH; + hal_flash_wr_status_reg((uint8 *)&area,2); + + } + else + { + SPIF_STATUS_WAIT_IDLE(SPIF_WAIT_IDLE_CYC); + spif_wait_nobusy(SFLG_WIP, SPIF_TIMEOUT, PPlus_ERR_BUSY); + AP_SPIF->fcmd = XFRD_FCMD_WREN; + SPIF_STATUS_WAIT_IDLE(SPIF_WAIT_IDLE_CYC); + spif_wait_nobusy(SFLG_WIP, SPIF_TIMEOUT, PPlus_ERR_BUSY); + AP_SPIF->fcmd_wrdata[0] = area | FCMD_SRP_REG; + AP_SPIF->fcmd = XFRD_FCMD_WRST; + SPIF_STATUS_WAIT_IDLE(SPIF_WAIT_IDLE_CYC); + spif_wait_nobusy(SFLG_WIP, SPIF_TIMEOUT, PPlus_ERR_BUSY); + } + } + spif_unlock(cs); + return 0; +} +__attribute__((section(".__sram.code"))) int hal_flash_unlock() +{ + + uint32_t cs = spif_lock(); + + if(FCMD_DATAPRO_AREA_NONE != hal_flash_lock_status()) + { + subWriteReg(&AP_SPIF->config, 14, 14, 0); //disable wp bit(14) + SPIF_STATUS_WAIT_IDLE(SPIF_WAIT_IDLE_CYC); + spif_wait_nobusy(SFLG_WIP, SPIF_TIMEOUT, PPlus_ERR_BUSY); + AP_SPIF->fcmd = XFRD_FCMD_WREN; + SPIF_STATUS_WAIT_IDLE(SPIF_WAIT_IDLE_CYC); + spif_wait_nobusy(SFLG_WIP, SPIF_TIMEOUT, PPlus_ERR_BUSY); + AP_SPIF->fcmd_wrdata[0] = FCMD_DATAPRO_AREA_NONE; + AP_SPIF->fcmd = XFRD_FCMD_WRST; + SPIF_STATUS_WAIT_IDLE(SPIF_WAIT_IDLE_CYC); + spif_wait_nobusy(SFLG_WIP, SPIF_TIMEOUT, PPlus_ERR_BUSY); + } + spif_unlock(cs); + return 0; +} + + __attribute__((section(".__sram.code"))) static int hal_flash_write(uint32_t addr, uint8_t *data, uint32_t size) { uint8_t retval; @@ -275,8 +366,9 @@ __attribute__((section(".__sram.code"))) int hal_flash_erase_sector(unsigned in __attribute__((section(".__sram.code"))) int hal_flash_erase_block64(unsigned int addr) { - uint32_t cs = spif_lock(); uint8_t retval; + uint32_t cs = spif_lock(); + uint32_t cb = AP_PCR->CACHE_BYPASS; SPIF_STATUS_WAIT_IDLE(SPIF_WAIT_IDLE_CYC); spif_wait_nobusy(SFLG_WIP, SPIF_TIMEOUT, PPlus_ERR_BUSY); @@ -294,8 +386,9 @@ __attribute__((section(".__sram.code"))) int hal_flash_erase_block64(unsigned i __attribute__((section(".__sram.code"))) int hal_flash_erase_all(void) { - uint32_t cs = spif_lock(); uint8_t retval; + uint32_t cs = spif_lock(); + uint32_t cb = AP_PCR->CACHE_BYPASS; SPIF_STATUS_WAIT_IDLE(SPIF_WAIT_IDLE_CYC); spif_wait_nobusy(SFLG_WIP, SPIF_TIMEOUT, PPlus_ERR_BUSY); @@ -311,6 +404,14 @@ __attribute__((section(".__sram.code"))) int hal_flash_erase_all(void) return retval; } +__attribute__((section(".__sram.code")))uint16_t hal_flash_area_choose() +{ + uint16_t area = FCMD_DATAPRO_AREA_384; + if(s_spif_ctx.mid == FLASH_TH_ID) + area = FCMD_DATAPRO_AREA_384_TH | FCMD_DATAPRO_AREA_384_TH_CMP; + return area; +} + /* basic spif driver */ @@ -376,6 +477,101 @@ uint32_t phy_flash_block64_erase(unsigned int addr) return hal_flash_erase_block64(addr); } +__attribute__((section(".__sram.code"))) int hal_flash_rd_status_reg(uint8* buf,bool low_8bit) +{ + uint8_t retval = PPlus_SUCCESS; + uint32_t cs = spif_lock(); + + SPIF_STATUS_WAIT_IDLE(SPIF_WAIT_IDLE_CYC); + spif_wait_nobusy(SFLG_WIP, SPIF_TIMEOUT, PPlus_ERR_BUSY); + + if(low_8bit == TRUE) + { + *buf = spif_flash_status_reg_0(); + } + else + { + *buf = spif_flash_status_reg_1(); + } + SPIF_STATUS_WAIT_IDLE(SPIF_WAIT_IDLE_CYC); + spif_wait_nobusy(SFLG_WIP, SPIF_TIMEOUT, PPlus_ERR_BUSY); + spif_unlock(cs); + return retval; +} + + +__attribute__((section(".__sram.code"))) int hal_flash_wr_status_reg(uint8* buf,int len) +{ + uint8_t retval = PPlus_SUCCESS; + //uint32_t result; + + if((len != 1) && (len != 2)) + { + return PPlus_ERR_INVALID_PARAM; + } + + uint32_t cs = spif_lock(); + SPIF_STATUS_WAIT_IDLE(SPIF_WAIT_IDLE_CYC); + spif_wait_nobusy(SFLG_WIP, SPIF_TIMEOUT, PPlus_ERR_BUSY); + + AP_SPIF->fcmd = XFRD_FCMD_WREN; + SPIF_STATUS_WAIT_IDLE(SPIF_WAIT_IDLE_CYC); + spif_wait_nobusy(SFLG_WIP, SPIF_TIMEOUT, PPlus_ERR_BUSY); + + spif_wrdata(buf, len); + spif_cmd(FCMD_WRST, 0,0,len,0,0); + + spif_wait_nobusy(SFLG_WIP, SPIF_TIMEOUT, PPlus_ERR_BUSY); + SPIF_STATUS_WAIT_IDLE(SPIF_WAIT_IDLE_CYC); + + spif_unlock(cs); + return retval; +} + + + +__attribute__((section(".__sram.code"))) static int hal_flash_config_srp(void) +{ + uint8_t retval; + uint8_t status_reg[2]; + uint8_t status_reg_len = 1; + + FLASH_WP_HIGH_LEVEL; + retval = hal_flash_rd_status_reg(&status_reg[0],TRUE); + +#if (FLASH_STATUS_REGISTER_LEN == 1) + if((status_reg[0] & 0x80) != 0x80) //SRP=1 +#elif (FLASH_STATUS_REGISTER_LEN == 2) + retval = hal_flash_rd_status_reg(&status_reg[1],FALSE); + if(((status_reg[1] & 0x01) != 0x00) || ((status_reg[0] & 0x80) != 0x80)) //SRP1=0&& SRP0=1 +#endif + { +#if (FLASH_STATUS_REGISTER_LEN == 2) + status_reg_len = 2; + status_reg[1] &= ~(1<<0); +#endif + status_reg[0] |= (1<<7); + hal_flash_wr_status_reg(status_reg,status_reg_len); + } + + return retval; +} + +__attribute__((section(".__sram.code"))) int hal_flash_switch_hardware_protect_mode(void) +{ + uint8_t retval = hal_flash_config_srp(); + FLASH_WP_LOW_LEVEL; + return retval; +} + +__attribute__((section(".__sram.code"))) int hal_flash_switch_hardware_unprotect_mode(void) +{ + uint8_t retval = hal_flash_config_srp(); + FLASH_WP_HIGH_LEVEL; + return retval; +} + + /* cpi api */ @@ -738,3 +934,4 @@ int32_t csi_spiflash_power_control(spiflash_handle_t handle, /*csi_power_stat_e* return state; } + diff --git a/flash/PHY6220_Flash.elf b/flash/PHY6220_Flash.elf index d6b5a6f5058ca7c42189bf9144dbd348f68ae0a4..c9ff7b2eaffb340f85bdb3bb1d0c7eec46999e4c 100755 Binary files a/flash/PHY6220_Flash.elf and b/flash/PHY6220_Flash.elf differ diff --git a/include/spif.h b/include/spif.h index f9f4313d5b8e499b4f362a87f41f034aa0e5b0cf..5cff3a61baa05278a9da77451cc61a89d97716c6 100755 --- a/include/spif.h +++ b/include/spif.h @@ -25,6 +25,7 @@ //#include "drv_spiflash.h" //#include "soc.h" #include "types.h" +#include "rom_sym_def.h" #ifdef __cplusplus extern "C" { @@ -35,6 +36,27 @@ extern "C" { #define __IOM volatile /*! Defines 'read / write' structure member permissions */ #endif +typedef struct{ + uint8_t state; + uint32_t size; + + bool w_protect; + + uint8_t clk_div; + + uint32_t qspi_en; + uint32_t rd_instr; + uint32_t wr_instr; + uint32_t remap; + + /*device id*/ + uint8_t mid; + uint8_t mtype; //mempry type + uint8_t mcapc; //memory capcity +}spif_ctx_t; + +extern spif_ctx_t s_spif_ctx; + #define CONFIG_SPIFLASH_NUM 1 #define DEBUG_EN 1 //#define SPIF_ADDR_START 0x11005000 @@ -52,6 +74,12 @@ extern "C" { #define XFRD_FCMD_READ 0x801000B #define XFRD_FCMD_READ_DUAL 0x801003B #define XFRD_FCMD_READ_QUAD 0x801006B +#define XFRD_FCMD_WREN 0x6000001 +#define XFRD_FCMD_WRDI 0x4000001 //flash write disable +#define XFRD_FCMD_WRST 0x1008001 + + + #define FCMD_RESET 0x99 //reset @@ -81,6 +109,66 @@ extern "C" { #define FCMD_READQIO 0xeB //quad I/O fast read #define FCMD_READQIOW 0xe7 //quad I/O fast read word +#define FCMD_CMD_EXCUTE 0x01 +#define FCMD_SRP_REG 0x80 +#define FCMD_SRP_REG_TH 0x0080 + +#define FCMD_DATAPRO_AREA_NONE 0x00 +#define FCMD_DATAPRO_AREA_504 0x04 +#define FCMD_DATAPRO_AREA_496 0x08 +#define FCMD_DATAPRO_AREA_480 0x0c +#define FCMD_DATAPRO_AREA_448 0x10 +#define FCMD_DATAPRO_AREA_384 0x14 +#define FCMD_DATAPRO_AREA_384_TH 0x0008 +#define FCMD_DATAPRO_AREA_384_TH_CMP 0x4000 +#define FCMD_DATAPRO_AREA_256 0x18 +#define FCMD_DATAPRO_AREA_512 0x1c +#define FCMD_DATAPRO_AREA_512_TH 0x0000 + + + +#define FCMD_DATAPRO_NONE_BIT 0x00 +#define FCMD_DATAPRO_504_BIT 0x04 +#define FCMD_DATAPRO_496_BIT 0x08 +#define FCMD_DATAPRO_480_BIT 0x0c +#define FCMD_DATAPRO_448_BIT 0x10 +#define FCMD_DATAPRO_384_BIT 0x14 +#define FCMD_DATAPRO_256_BIT 0x18 +#define FCMD_DATAPRO_512_BIT 0x1c + + + + +#define FLASH_STATUS_REGISTER_LEN 1 + +#define XFRD_FCMD_WREN 0x6000001 +#define XFRD_FCMD_WRST 0x1008001 + +#define FLASH_WP_HIGH_LEVEL (AP_SPIF->config &= ~(1<<14)) +#define FLASH_WP_LOW_LEVEL (AP_SPIF->config |= (1<<14)) +#define FLASH_WP_LEVEL_GET (0x4000-(AP_SPIF->config & (1<<14))) + +#define FLASH_GD_ID 0xc8 +#define FLASH_XTX_ID 0x0b +#define FLASH_TH_ID 0xcd + + + +extern uint8_t spif_flash_status_reg_1(void); +extern int spif_read_id(uint32_t* pid); +extern void spif_wrdata(uint8_t* data, uint8_t len); + +__attribute__((section(".__sram.code"))) void hal_cache_tag_flush(void); + + +__attribute__((section(".__sram.code"))) int hal_flash_rd_status_reg(uint8* buf,bool low_8bit); +__attribute__((section(".__sram.code"))) int hal_flash_wr_status_reg(uint8* buf,int len); + +__attribute__((section(".__sram.code"))) int hal_flash_switch_hardware_protect_mode(void); +__attribute__((section(".__sram.code"))) int hal_flash_switch_hardware_unprotect_mode(void); +__attribute__((section(".__sram.code"))) uint8_t hal_flash_write_disable(void); + + #ifdef __cplusplus } #endif diff --git a/misc/rom_sym_def.h b/misc/rom_sym_def.h index 7ed7555bc1b8a06d2c68a16c937e7b6d8ca249df..0e106ac316b0bac9616aa0a06be074968366210b 100755 --- a/misc/rom_sym_def.h +++ b/misc/rom_sym_def.h @@ -4,6 +4,8 @@ #define __ROM_SYM_H__ #ifdef USE_ROMSYM_ALIAS +#define g_system_reset_cause _symrom_g_system_reset_cause +#define SystemResetCause _symrom_SystemResetCause #define WaitMs _symrom_WaitMs #define WaitRTCCount _symrom_WaitRTCCount #define WaitUs _symrom_WaitUs @@ -40,6 +42,7 @@ #define conn_param _symrom_conn_param #define connUpdateTimer _symrom_connUpdateTimer #define counter_tracking _symrom_counter_tracking +#define g_llScanMode _symrom_g_llScanMode #define crc16_rom _symrom_crc16 #define ctrlToHostEnable _symrom_ctrlToHostEnable #define dataPkt _symrom_dataPkt @@ -569,7 +572,7 @@ #define LL_SetPeriodicAdvEnable _symrom_LL_SetPeriodicAdvEnable #define LL_SetPeriodicAdvParameter _symrom_LL_SetPeriodicAdvParameter #define LL_SetPhyMode _symrom_LL_SetPhyMode -#define LL_SetRandomAddress _symrom_LL_SetRandomAddress +//#define LL_SetRandomAddress _symrom_LL_SetRandomAddress #define LL_SetResolvablePrivateAddressTimeout _symrom_LL_SetResolvablePrivateAddressTimeout #define LL_SetScanControl _symrom_LL_SetScanControl #define LL_SetScanParam _symrom_LL_SetScanParam @@ -873,6 +876,7 @@ #define spif_set_deep_sleep _symrom_spif_set_deep_sleep #define spif_wrdata _symrom_spif_wrdata #define spif_write _symrom_spif_write +#define spif_read_id _symrom_spif_read_id #define spif_write_protect _symrom_spif_write_protect #define sram_ret_patch _symrom_sram_ret_patch #define supportedCmdsTable _symrom_supportedCmdsTable @@ -909,6 +913,15 @@ #define rom_hal_uart_send_buff _symrom_hal_uart_send_buff #define rom_hal_uart_tx _symrom_hal_uart_tx #define move_to_slave_function0 _symrom_move_to_slave_function0 +#define ll_scheduler0 _symrom_ll_scheduler0 +#define g_llAdvMode _symrom_g_llAdvMode +#define LL_AdvSetTerminatedCback _symrom_LL_AdvSetTerminatedCback +#define g_timer4_irq_pending_time _symrom_g_timer4_irq_pending_time +#define llSetupNextSlaveEvent0 _symrom_llSetupNextSlaveEvent0 +#define llProcessSlaveControlPacket0 _symrom_llProcessSlaveControlPacket0 +#define llProcessMasterControlPacket0 _symrom_llProcessMasterControlPacket0 +#define LL_slave_conn_event0 _symrom_LL_slave_conn_event0 +#define LL_SetScanParam0 _symrom_LL_SetScanParam0 #endif #endif diff --git a/phy_pmu.c b/phy_pmu.c index bcc3385dcfe6bf68379f4059644747dc53801613..fa1d8029878dc94c6f90ab587c83c92353be0ad7 100755 --- a/phy_pmu.c +++ b/phy_pmu.c @@ -25,7 +25,7 @@ #include #include - +#include "global_config.h" #define ERR_PMU(errno) (CSI_DRV_ERRNO_PMU_BASE | errno) #define PMU_NULL_PARAM_CHK(para) HANDLE_PARAM_CHK(para, ERR_PMU(DRV_ERROR_PARAMETER)) @@ -36,6 +36,7 @@ typedef struct { extern int32_t arch_do_cpu_save(void); extern int32_t arch_do_cpu_resume(void); +extern uint32_t rtc_get_counter(void); static uint8_t pmu_power_status; static phy_pmu_priv_t pmu_handle[CONFIG_PMU_NUM]; @@ -73,6 +74,9 @@ static void do_prepare_sleep_action(int32_t idx) static void do_wakeup_sleep_action(int32_t idx) { int i = 0; + + subWriteReg(&AP_SPIF->config, 14, 14, 1); //enable wp bit(14) + /* resume vic register */ VIC->ISER[0U] = vic_regs_saved[0]; VIC->ISPR[0U] = vic_regs_saved[1]; @@ -106,7 +110,10 @@ pmu_handle_t csi_pmu_initialize(int32_t idx, pmu_event_cb_t cb_event) pmu_priv->idx = idx; pmu_priv->cb = cb_event; - JUMP_FUNCTION(WAKEUP_PROCESS) = (uint32_t)arch_do_cpu_resume; + /* + WAKEUP_PROCESS jump func will be registed as arch_do_cpu_resume in enter_sleep_process + */ + //JUMP_FUNCTION(WAKEUP_PROCESS) = (uint32_t)arch_do_cpu_resume; return (pmu_handle_t)pmu_priv; } @@ -188,6 +195,18 @@ int32_t csi_pmu_enter_sleep(pmu_handle_t handle, pmu_mode_e mode) do_prepare_sleep_action(0); if (arch_do_cpu_save() == 0) { + subWriteReg(0x4000f03c, 2, 0, 0); //switch hclk to RC32M + uint32_t rtc_current; + extern uint32 *pGlobal_config; + rtc_current = rtc_get_counter(); + if(((AP_AON->RTCCC0 - rtc_current)>(pGlobal_config[MAX_SLEEP_TIME]>>4)) || + ((AP_AON->RTCCC0 - rtc_current)<(pGlobal_config[MIN_SLEEP_TIME]>>6))) + { + extern void just_enter_sleep(uint32 time); + just_enter_sleep(33000); + } + extern int32_t arch_do_cpu_resume(void); + JUMP_FUNCTION(WAKEUP_PROCESS) = (uint32_t)arch_do_cpu_resume; enter_sleep_off_mode(SYSTEM_SLEEP_MODE); } @@ -203,6 +222,7 @@ int32_t csi_pmu_enter_sleep(pmu_handle_t handle, pmu_mode_e mode) if (pmu_priv->cb) { pmu_priv->cb(pmu_priv->idx, PMU_EVENT_PREPARE_SLEEP, mode); } + set_sleep_flag(0); *((unsigned int *)0x4000f0c0) = 0x2; subWriteReg(0x4000f01c, 6, 6, 0x00); //disable software control enter_sleep_off_mode(SYSTEM_OFF_MODE); diff --git a/pm.c b/pm.c index 816dc77a02441d4e194533c92218aa123b73eedd..fdfe7dcd87a86476e127e4e3f98ddc39d12fd112 100755 --- a/pm.c +++ b/pm.c @@ -22,6 +22,7 @@ #include "pwrmgr.h" #include "pin.h" #include "pm.h" +#include "spif.h" #define DBGIO_LL_TRIG P14 #define DBGIO_LL_IRQ P15 @@ -33,6 +34,7 @@ #define MIN_TIME_TO_SLEEP 50 //ms #define MIN_TIME_TO_SUSPEND 10000 //ms + extern int g_spif_ref_clk; //pwrmgr_attribute_t pwrmgr_attribute; extern uint32_t ll_remain_time; @@ -40,7 +42,7 @@ extern uint32_t g_wakeup_rtc_tick;// = 0; extern uint32_t sleep_flag;// = 0; // when sleep, set this value to SLEEP_MAGIC. when wakeup, set this value to 0 extern uint32_t osal_sys_tick; -extern uint32_t g_counter_traking_avg ;// = 3906; +extern uint32_t g_counter_traking_avg ;// = 3906;7812(bug fix 2021/11/15) extern volatile uint32_t llWaitingIrq; //used for sleep timer sync @@ -65,6 +67,11 @@ extern uint32 read_LL_remainder_time(void); extern uint32_t read_current_fine_time(void); extern int clk_spif_ref_clk(sysclk_t spif_ref_sel); extern void hal_mpu_config(void); +extern void drv_reboot(int cmd); +extern void *osal_memcpy( void *dst, const void GENERIC *src, unsigned int len ); +extern void *osal_memset( void *dest, uint8 value, int len ); +extern __attribute__((section(".__sram.code"))) void config_reset_handler(int rstMod); +extern void jump_area_init(void); static uint32_t irq_flags; @@ -99,7 +106,11 @@ pm_wakeup_by_io_cb g_wakeup_cb = NULL; #define PMU_ADDROFF (0x1F0) #ifndef CONFIG_WDT -#define CONFIG_WDT 0 +#define CONFIG_WDT 1 +#endif + +#ifndef CONFIG_LOW_POWER_WAKE_DEBUG +#define CONFIG_LOW_POWER_WAKE_DEBUG 0 #endif #if (CONFIG_WDT > 0) @@ -200,7 +211,7 @@ void wdt_wakeup_action() while (delay-- > 0); - AP_WDT->CR = 0x1F; + AP_WDT->CR = 0x1D; csi_wdt_set_timeout(wdt_handle, WDT_TIMEOUT); #endif @@ -335,6 +346,22 @@ void set_sleep_flag(int flag) // *(volatile uint32_t *) 0x4000f024 |= 1 << 15; //enable comparator0 inerrupt //*(volatile uint32_t *) 0x4000f024 |= 0x148000; // combine above 3 statement to save MCU time +void rc32k_cap_cal(uint32_t temp) +{ + uint32_t rccap; + if((temp > CRY32_16_CYCLE_16MHZ_CYCLE_MAX) && ((*(volatile uint32_t *) 0x4000f018 & 0x7e) > 0)) + { + rccap = ((read_reg(0x4000f018)>>1) & 0x3f) - 1; + subWriteReg(0x4000f018,6,1,rccap); + WaitRTCCount(3); + } + else if((temp < CRY32_16_CYCLE_16MHZ_CYCLE_MIN) && ((*(volatile uint32_t *) 0x4000f018 & 0x7e) < 0x7e)) + { + rccap = ((read_reg(0x4000f018)>>1) & 0x3f) + 1; + subWriteReg(0x4000f018,6,1,rccap); + WaitRTCCount(3); + } +} void enterSleepProcess1(uint32_t time) { @@ -345,7 +372,7 @@ void enterSleepProcess1(uint32_t time) if (pGlobal_config[LL_SWITCH] & RC32_TRACKINK_ALLOW) { // 1. read RC 32KHz tracking counter, calculate 16MHz ticks number per RC32KHz cycle - temp = *(volatile uint32_t *)0x4000f064 & 0x1ffff; + temp = AP_PCRM->cal_ro1 & 0x1ffff; //====== assume the error cnt is (n+1/2) cycle,for this case, it should be 9 or 10 // error_delt = (temp>STD_CRY32_8_CYCLE_16MHZ_CYCLE) @@ -368,7 +395,8 @@ void enterSleepProcess1(uint32_t time) counter_tracking = (temp > CRY32_16_CYCLE_16MHZ_CYCLE_MAX) ? counter_tracking : temp; //20181204 filter the counter_tracking spur, due to the N+1 issue - + rc32k_cap_cal(temp); + if (g_counter_traking_cnt < 1000) { //before traking converage use hard limitation counter_tracking = (counter_tracking > CRY32_16_CYCLE_16MHZ_CYCLE_MAX || counter_tracking < CRY32_16_CYCLE_16MHZ_CYCLE_MIN) @@ -378,8 +406,8 @@ void enterSleepProcess1(uint32_t time) } else { //after tracking converage use soft limitation - counter_tracking = (counter_tracking > g_counter_traking_avg + (g_counter_traking_avg >> 8) - || counter_tracking < g_counter_traking_avg - (g_counter_traking_avg >> 8)) + counter_tracking = (counter_tracking > g_counter_traking_avg + (g_counter_traking_avg >> 3) + || counter_tracking < g_counter_traking_avg - (g_counter_traking_avg >> 3)) ? g_counter_traking_avg : counter_tracking; } @@ -437,7 +465,6 @@ void enterSleepProcess1(uint32_t time) // 5. set sleep flag(AON reg & retention SRAM variable) set_sleep_flag(1); - // 6. trigger system sleep csi_pmu_enter_sleep(pmu_handle, PMU_MODE_DORMANT); } @@ -447,7 +474,11 @@ void osal_pwrmgr_powerconserve_dummy(void) //do nothing return; } - +void sram_HardFault_Handler(void) +{ + subWriteReg(&(AP_PCRM->CLKSEL),2,0,SYS_CLK_RC_32M); + drv_reboot(1); +} /****************************************** // SOC interfaces ******************************************/ @@ -469,6 +500,9 @@ int sys_soc_suspend(uint32_t suspend_tick) RHINO_CPU_INTRPT_DISABLE(); irq_flags = psr; + extern void check_hclk_by_rc32k_rtc(void); + check_hclk_by_rc32k_rtc(); + if (!isSleepAllowInPM()) { RHINO_CPU_INTRPT_ENABLE(); __WFI(); @@ -636,57 +670,154 @@ int sys_soc_suspend(uint32_t suspend_tick) #ifndef BASE_TIME_UINTS #define BASE_TIME_UNITS (0x3fffff) #endif -extern uint8 rc32k_calibration(void); + #define CRY32_2_CYCLE_16MHZ_CYCLE_MAX (976 + 98) // tracking value range std +/- 20% #define CRY32_2_CYCLE_16MHZ_CYCLE_MIN (976 - 98) #define CRY32_2_CYCLE_DELTA_LMT (19) #define TRACKING_96M_16M_MULTI6_DELTA_LIMIT (10*6) //96M:16M*6 +- 1% #define DLL_ENABLE_MAX (5) +#define TRACKING_16M_TICK_MAX (3300) +#define TRACKING_MAX_SLEEPTIME (1980000) //MAX sleep time is 60 seconds. -volatile uint8_t g_rc32kCalRes = 0xFF; +//volatile uint8_t g_rc32kCalRes = 0xff; uint32_t g_xtal16M_tmp=0; uint32_t g_xtal96M_temp=0; uint32_t DLL_enable_num=1; +uint32_t tracking_16M_num = 0; +extern void Reset_Handler(); +extern int SystemResetCause(void); +extern uint32_t g_system_reset_cause; +void _rom_data_init(void) +{ + //copy rom data section + osal_memcpy((void *)0x1fff0800,(const void GENERIC *)0x17c7c,(0x1fff0924-0x1fff0800)); + //clr rom bss section skip g_top_trapstack + osal_memset((void *)0x1fff0924,0,(0x1fff0988-0x1fff0924)); + osal_memset((void *)0x1fff0b8c,0,(0x1fff1a3c-0x1fff0b8c)); +} -void rf_calibrate2(void) +void sram_reset_handler(void) { - //========== do rf tp cal for tx and rx dcoffset cal - rf_phy_ana_cfg(); - rf_tpCal_gen_cap_arrary(); //generate the tpCal cap arrary - //rf_tpCal_cfg(/*rfChn*/2); - rf_rxDcoc_cfg(/*rfChn*/88,/*bwSet*/1,&g_rfPhyRxDcIQ); //set the rfChn as 2488 for BW=1MHz - g_rc32kCalRes = rc32k_calibration(); + subWriteReg(&AP_SPIF->config, 14, 14, 1); //enable wp bit(14) + + AP_PCR->CACHE_BYPASS = 1;//disable cache + AP_SPIF->fcmd_wrdata[0] = 0x94; + clk_init(SYS_CLK_RC_32M); + config_reset_handler(1); + + + + g_spif_ref_clk = SYS_CLK_RC_32M; + hal_cache_init(); + hal_flash_write_disable(); + hal_mpu_config(); + + _rom_data_init(); + + + + /* + update reset cause, add 0x80 to mark the reset path from sram_reset_handler + */ + SystemResetCause(); + g_system_reset_cause |=0x80; + + //check just_sleep_reset flg + if(((AP_AON->SLEEP_R[1] & 0x0f)>>2)) + g_system_reset_cause |=0x40; + + Reset_Handler(); +} +void just_enter_sleep(uint32 time) +{ + if (time < MIN_TIME_TO_SLEEP) + time = MIN_TIME_TO_SLEEP; + + jump_area_init(); + JUMP_FUNCTION(WAKEUP_PROCESS) = (uint32_t)sram_reset_handler; + + /* set sleep flag , rom boot will check the flag and + set reset path from WAKEUP_PROCESS */ + phy_gpioretention_disable(); + set_sleep_flag(1); + + subWriteReg(&(AP_AON->PMCTL2_0),6,6,0x00); //disable software control + // config wakeup timer + uint32_t sleep_tick_now = AP_AON->RTCCNT; + WaitRTCCount(1); + AP_AON->RTCCC0 = sleep_tick_now + time; + AP_AON->RTCCTL |= BIT(15)|BIT(18)|BIT(20); + + // clear sram retention + // hal_pwrmgr_RAM_retention_clr(); + + /** + config reset casue as RSTC_WARM_NDWC + reset path walkaround dwc + */ + if (((AP_AON->SLEEP_R[1] & 0xFF00) >>8) > 100) + AP_AON->SLEEP_R[1]=0; + + AP_AON->SLEEP_R[0]=4; + + // trigger system sleep + enter_sleep_off_mode(SYSTEM_SLEEP_MODE); } -static void check_16MXtal_by_rcTracking(void) + +#define RTC_32KRC_3_CYCLE_LIMIT_LOW (60) //3*30.5 normal pclk +#define RTC_32KRC_3_CYCLE_LIMIT_HIGH (120) //3*30.5 normal pclk + +void check_hclk_by_rc32k_rtc(void) +{ + WaitRTCCount(1); + uint32_t t0 = read_current_fine_time(); + WaitRTCCount(3); + uint32_t t1 = read_current_fine_time(); + if((TIME_DELTA(t1,t0)RTC_32KRC_3_CYCLE_LIMIT_HIGH)) + { + subWriteReg(&(AP_PCRM->CLKSEL), 2, 0, 0); //switch hclk to RC32M + just_enter_sleep(33000); + + } + + +} + + +void check_16MXtal_by_rcTracking(void) { /* + for fiset wakeupini, not do rcCal, just skip the rcTacking */ - if(g_rc32kCalRes==0xFF) + + if((AP_AON->SLEEP_R[1] & 0x80) == 0) { WaitRTCCount(60); return; } + uint32_t tracking_start = rtc_get_counter(); + uint32_t temp,temp1; uint32_t temp31,temp32,temp33; uint32_t temp_min,temp_max; // ======== enable tracking 32KHz RC timer with 16MHz crystal clock - temp = *(volatile uint32_t *)0x4000f040; - *(volatile uint32_t *)0x4000f040 = temp | BIT(18); - temp = *(volatile uint32_t *)0x4000f05C; - *(volatile uint32_t *)0x4000f05C = (temp & 0xfffefe00) | 0x0028; + temp = AP_PCRM->CLKHF_CTL0; + AP_PCRM->CLKHF_CTL0 = temp | BIT(18); + temp = AP_PCRM->cal_rw; + AP_PCRM->cal_rw = (temp & 0xfffefe00) | 0x0028; WaitRTCCount(3); - temp31 = (*(volatile uint32_t *)0x4000f064 & 0x1ffff); + temp31 = (AP_PCRM->cal_ro1 & 0x1ffff); WaitRTCCount(3); - temp32 = (*(volatile uint32_t *)0x4000f064 & 0x1ffff); + temp32 = (AP_PCRM->cal_ro1 & 0x1ffff); WaitRTCCount(3); - temp33 = (*(volatile uint32_t *)0x4000f064 & 0x1ffff); + temp33 = (AP_PCRM->cal_ro1 & 0x1ffff); while(1) { @@ -704,100 +835,125 @@ static void check_16MXtal_by_rcTracking(void) (temp_max-temp_min)SLEEP_R[1]),3,2,0); + + //reset tracking sleep num + subWriteReg(&(AP_AON->SLEEP_R[1]),15,8,0); break; } temp31= temp32; temp32 = temp33; WaitRTCCount(3); - temp33 = (*(volatile uint32_t *)0x4000f064 & 0x1ffff); + temp33 = (AP_PCRM->cal_ro1 & 0x1ffff); + + //check tracking cost + uint32_t tracking_end = rtc_get_counter(); + uint32_t tracking_16M_tick = (tracking_end>=tracking_start) ? (tracking_end-tracking_start) : (0xffffffff-tracking_start+tracking_end); + if(tracking_16M_tick >= TRACKING_16M_TICK_MAX) + { + uint32_t tracking_sleep_num = (AP_AON->SLEEP_R[1] & 0xFF00) >>8; + subWriteReg(&(AP_AON->SLEEP_R[1]),15,8,tracking_sleep_num+1); + subWriteReg(&(AP_AON->SLEEP_R[1]),3,2,1); + if ((uint32_t)((uint32_t)1 << tracking_sleep_num)*33000 < TRACKING_MAX_SLEEPTIME) + { + just_enter_sleep((1 << tracking_sleep_num)*33000); + } + else + { + just_enter_sleep(TRACKING_MAX_SLEEPTIME); + } + } + } - WaitRTCCount(20); - temp1 = (*(volatile uint32_t *)0x4000f064 & 0x1ffff); + temp1 = (AP_PCRM->cal_ro1 & 0x1ffff); - subWriteReg(0x4000f05C,3,3,0); + subWriteReg(&(AP_PCRM->cal_rw),3,3,0); g_xtal16M_tmp = temp1; } -static void check_96MXtal_by_rcTracking(void) +void check_96MXtal_by_rcTracking(void) { uint32_t temp,temp1; //for first wakeupinit - if(g_rc32kCalRes==0xFF) + if((AP_AON->SLEEP_R[1] & 0x80) == 0) { //enable DLL - temp = *(volatile uint32_t *)0x4000f044; - *(volatile uint32_t *)0x4000f044 = temp | BIT(7); + temp = AP_PCRM->CLKHF_CTL1; + AP_PCRM->CLKHF_CTL1 = temp | BIT(7); WaitRTCCount(3); return; } - + DLL_enable_num=0; // ======== enable tracking 32KHz RC timer with 16MHz crystal clock - temp = *(volatile uint32_t *)0x4000f040; - *(volatile uint32_t *)0x4000f040 = temp | BIT(18); + temp = AP_PCRM->CLKHF_CTL0; + AP_PCRM->CLKHF_CTL0 = temp | BIT(18); while(1) { //enable DLL - temp = *(volatile uint32_t *)0x4000f044; - *(volatile uint32_t *)0x4000f044 = temp | BIT(7); + temp = AP_PCRM->CLKHF_CTL1; + AP_PCRM->CLKHF_CTL1 = temp | BIT(7); WaitRTCCount(3); DLL_enable_num++; // //enable digclk 96M - temp = *(volatile uint32_t *)0x4000f044; - *(volatile uint32_t *)0x4000f044 = temp | BIT(16); + temp = AP_PCRM->CLKHF_CTL1; + AP_PCRM->CLKHF_CTL1 = temp | BIT(16); for(uint8 index=0;index<5;index++) { - temp = *(volatile uint32_t *)0x4000f05C; - *(volatile uint32_t *)0x4000f05C = (temp & 0xfffefe00) | 0x0028 | BIT(16); + temp = AP_PCRM->cal_rw; + AP_PCRM->cal_rw = (temp & 0xfffefe00) | 0x0028 | BIT(16); WaitRTCCount(3); - temp1 = (*(volatile uint32_t *)0x4000f064 & 0x1ffff); - subWriteReg(0x4000f05C,3,3,0); + temp1 = (AP_PCRM->cal_ro1 & 0x1ffff); + subWriteReg(&(AP_PCRM->cal_rw),3,3,0); if( (g_xtal16M_tmp*6 >=temp1 ? (g_xtal16M_tmp*6 -temp1):(temp1-g_xtal16M_tmp*6))cal_rw),16,16,0); + subWriteReg(&(AP_PCRM->CLKHF_CTL1),16,16,0); g_xtal96M_temp = temp1; + subWriteReg(&(AP_AON->SLEEP_R[1]),5,4,0); return; } - } + } //disable 96M - subWriteReg(0x4000f05C,16,16,0); - subWriteReg(0x4000f044,16,16,0); + subWriteReg(&(AP_PCRM->cal_rw),16,16,0); + subWriteReg(&(AP_PCRM->CLKHF_CTL1),16,16,0); //should not be here if(DLL_enable_num>= DLL_ENABLE_MAX) { - NVIC_SystemReset(); + subWriteReg(&(AP_AON->SLEEP_R[1]),5,4,1); + just_enter_sleep(60); } //disable DLL - subWriteReg(0x4000f044,7,7,0); + subWriteReg(&(AP_PCRM->CLKHF_CTL1),7,7,0); WaitRTCCount(3); - + //update g_xtal16M_tmp - temp = *(volatile uint32_t *)0x4000f05C; - *(volatile uint32_t *)0x4000f05C = (temp & 0xfffefe00) | 0x0028 ; + temp = AP_PCRM->cal_rw; + AP_PCRM->cal_rw = (temp & 0xfffefe00) | 0x0028 ; WaitRTCCount(3); - g_xtal16M_tmp = (*(volatile uint32_t *)0x4000f064 & 0x1ffff); + g_xtal16M_tmp = (AP_PCRM->cal_ro1 & 0x1ffff); - subWriteReg(0x4000f05C,3,3,0); + subWriteReg(&(AP_PCRM->cal_rw),3,3,0); } } +uint32_t tracking_cnt=0; void wakeup_init1() { uint8_t pktFmt = 1; // packet format 1: BLE 1M uint32_t temp; @@ -811,36 +967,33 @@ void wakeup_init1() { //WaitRTCCount(pGlobal_config[WAKEUP_DELAY]); if(g_system_clk == SYS_CLK_XTAL_16M) { - WaitRTCCount(pGlobal_config[WAKEUP_DELAY]); + //WaitRTCCount(pGlobal_config[WAKEUP_DELAY]); + WaitRTCCount(10); + check_16MXtal_by_rcTracking(); } else { uint32_t tracking_c1,tracking_c2; - uint32_t tracking_cnt=0; - tracking_c1 = rtc_get_counter(); + WaitRTCCount(30); + subWriteReg(&(AP_AON->SLEEP_R[1]),1,0,0); check_16MXtal_by_rcTracking(); + WaitRTCCount(6); + subWriteReg(&(AP_AON->SLEEP_R[1]),1,0,1); check_96MXtal_by_rcTracking(); - + subWriteReg(&(AP_AON->SLEEP_R[1]),1,0,2); tracking_c2 = rtc_get_counter(); - tracking_cnt = (tracking_c2>=tracking_c1) ? (tracking_c2-tracking_c1) : (0xffffffff-tracking_c1+tracking_c2); - pGlobal_config[WAKEUP_ADVANCE] =1500+30*tracking_cnt; - - //enable DLL - uint32 temp0; - temp0 = *(volatile uint32_t *)0x4000f044; - *(volatile uint32_t *)0x4000f044 = temp0 | BIT(7); - WaitRTCCount(3); } + // ============ config BB Top *(volatile uint32_t *) 0x40030000 = 0x3d068001; // set tx pkt =2 *(volatile uint32_t *) 0x400300bc = 0x834; //[7:0] pll_tm [11:8] rxafe settle *(volatile uint32_t *) 0x400300a4 = 0x140; //[6] for tpm_en clk_init(g_system_clk); - + subWriteReg(&(AP_AON->SLEEP_R[1]),1,0,3); hal_wakeup_irq_config(); // ========== init timers @@ -864,8 +1017,8 @@ void wakeup_init1() { ll_hw_ign_rfifo(LL_HW_IGN_SSN | LL_HW_IGN_CRC | LL_HW_IGN_EMP); // ======== enable tracking 32KHz RC timer with 16MHz crystal clock - temp = *(volatile uint32_t *)0x4000f05C; - *(volatile uint32_t *)0x4000f05C = (temp & 0xfffefe00) | 0x0108; //[16] 16M [8:4] cnt [3] track_en_rc32k + temp = AP_PCRM->cal_rw; + AP_PCRM->cal_rw = (temp & 0xfffefe00) | 0x0108; //[16] 16M [8:4] cnt [3] track_en_rc32k } static void hw_spif_cache_config(void) { @@ -874,15 +1027,26 @@ static void hw_spif_cache_config(void) { hal_cache_init(); } -uint64_t sys_soc_resume(int pm_state) { +extern void efuse_init(void); + +int sys_soc_resume(int pm_state) { uint32_t current_RTC_tick; uint32_t wakeup_time, wakeup_time0, next_time; - uint64_t sleep_total; + uint32_t sleep_total; uint32_t dlt_tick; if (pm_state == SYS_POWER_STATE_RUN) { return 0; } + + AP_PCR->CACHE_BYPASS = 1;//disable cache + AP_SPIF->fcmd_wrdata[0] = 0x94; + + config_reset_handler(1); + + efuse_init(); + + wdt_wakeup_action(); DBG_GPIO_WRITE(DBGIO_APP_WAKEUP, 1); // restore HW registers @@ -908,14 +1072,14 @@ uint64_t sys_soc_resume(int pm_state) { //config the tx2rx timing according to the g_rfPhyPktFmt ll_hw_tx2rx_timing_config(g_rfPhyPktFmt); - if (pGlobal_config[LL_SWITCH] & LL_RC32K_SEL) { - subWriteReg(0x4000f01c, 16, 7, 0x3fb); //software control 32k_clk - subWriteReg(0x4000f01c, 6, 6 , 0x01); //enable software control + // if (pGlobal_config[LL_SWITCH] & LL_RC32K_SEL) { + // subWriteReg(0x4000f01c, 16, 7, 0x3fb); //software control 32k_clk + // subWriteReg(0x4000f01c, 6, 6 , 0x01); //enable software control - } else { - subWriteReg(0x4000f01c, 9, 8, 0x03); //software control 32k_clk - subWriteReg(0x4000f01c, 6, 6, 0x00); //disable software control - } + // } else { + // subWriteReg(0x4000f01c, 9, 8, 0x03); //software control 32k_clk + // subWriteReg(0x4000f01c, 6, 6, 0x00); //disable software control + // } //20181201 by ZQ //restart the TIM2 to align the RTC @@ -1043,7 +1207,7 @@ uint64_t sys_soc_resume(int pm_state) { ll_debug_output(DEBUG_WAKEUP); - set_sleep_flag(0); +// set_sleep_flag(0); DBG_GPIO_WRITE(DBGIO_APP_WAKEUP, 1); @@ -1051,7 +1215,7 @@ uint64_t sys_soc_resume(int pm_state) { hal_mpu_config(); //clk_spif_ref_clk(g_spif_ref_clk); - + /* clear tick irq state by reading reg */ int count; unsigned int v = *((volatile unsigned int *) (0xE000E010)); while((v & 0x10000) > 0) @@ -1059,11 +1223,19 @@ uint64_t sys_soc_resume(int pm_state) { v = *((volatile unsigned int *) (0xE000E010)); count++; } + #if (CONFIG_LOW_POWER_WAKE_DEBUG == 1) + gpio_write(P25,1); + gpio_write(P25,0); + #endif CPSR_ALLOC(); psr = irq_flags; RHINO_CPU_INTRPT_ENABLE(); - wdt_wakeup_action(); +// wdt_wakeup_action(); + #if(CONFIG_LOW_POWER_WAKE_DEBUG == 1) + gpio_write(P33,1); + gpio_write(P33,0); + #endif //usart_wakeup_action(); pm_after_sleep_action(); @@ -1075,7 +1247,7 @@ uint64_t sys_soc_resume(int pm_state) { // ==== measure value, from RTC counter meet comparator 0 -> here : 260us ~ 270us // start task loop // osal_start_system(); - uint64_t sleep_total_us = sleep_total + g_osal_tick_trim; + uint32_t sleep_total_us = sleep_total + g_osal_tick_trim; sleep_total_us = ((sleep_total_us << 7) + (sleep_total_us << 1) + sleep_total_us) >> 17; //sleep_total_us/1000 return sleep_total_us; } diff --git a/reboot.c b/reboot.c index b64b5013655046e0d5ffdff16e64d0273b403468..3c2a4bb0f959add686419ef21429b49c63db9547 100755 --- a/reboot.c +++ b/reboot.c @@ -14,27 +14,49 @@ #include #include #include +#include "jump_function.h" + +#define RST_FROM_ROM_BOOT 0 +#define RST_FROM_APP_RST_HANDLER 1 + extern size_t cpu_intrpt_save(void); +extern void sram_reset_handler(void); +extern void set_sleep_flag(int flag); + +__attribute__((section(".__sram.code"))) void config_reset_handler(int rstMod) +{ + if(rstMod==RST_FROM_ROM_BOOT) + { + set_sleep_flag(0); + } + else + { + JUMP_FUNCTION(WAKEUP_PROCESS) = (uint32_t)sram_reset_handler; + extern void trap_c(uint32_t *regs); + extern void sram_HardFault_Handler(void); + JUMP_FUNCTION(CK802_TRAP_C) = (uint32_t)&sram_HardFault_Handler; //register trap irq handler + set_sleep_flag(1); + } +} __attribute__((section(".__sram.code"))) void drv_reboot(int cmd) { csi_irq_save(); - - volatile int dly = 100; - - //cache rst + AP_PCR->CACHE_BYPASS = 1; +// hal_flash_write_disable(); +// AP_SPIF->config = 0; AP_PCR->CACHE_RST = 0; - while (dly--) {}; - - AP_PCR->CACHE_RST = 0x03; - - //cache flush tag - AP_CACHE->CTRL0 = 0x03; - - //cache enable - AP_PCR->CACHE_BYPASS = 1; + // config reset path , from rom or app + config_reset_handler(cmd); + /** + config reset casue as RSTC_WARM_NDWC + reset path walkaround dwc + */ + AP_AON->SLEEP_R[0]=4; + + AP_AON->SLEEP_R[1]=0; *(volatile uint32_t *) 0x40000004 = 0x00; diff --git a/system.c b/system.c index 3928e3e35156bc7c64c60996831ddb56fa4261c6..8deb93570589613fe7952703593fb846dcad68de 100755 --- a/system.c +++ b/system.c @@ -35,18 +35,20 @@ #include "sys_freq.h" #include #include "pm.h" +#include "spif.h" #ifndef CONFIG_SYSTICK_HZ #define CONFIG_SYSTICK_HZ 100 #endif extern volatile sysclk_t g_system_clk; -int g_spif_ref_clk = SYS_CLK_DLL_64M; +int g_spif_ref_clk = SYS_CLK_RC_32M; extern void trap_c(uint32_t *regs); extern uint32_t g_system_clk; volatile uint8 g_clk32K_config; + extern int32_t g_top_irqstack; extern void irq_vectors_init(void); extern void init_config(void); @@ -75,7 +77,7 @@ __attribute__((section(".__sram.code"))) void hal_cache_init(void) hal_clk_gate_enable(MOD_PCLK_CACHE); //cache rst - AP_PCR->CACHE_RST = 0x00; + AP_PCR->CACHE_RST = 0x02; while (dly--) {}; @@ -83,13 +85,16 @@ __attribute__((section(".__sram.code"))) void hal_cache_init(void) AP_PCR->CACHE_RST = 0x03; //cache flush tag - AP_CACHE->CTRL0 = 0x01; + //AP_CACHE->CTRL0 = 0x01; + hal_cache_tag_flush(); //cache enable AP_PCR->CACHE_BYPASS = 0; spif_config(g_spif_ref_clk, 0x1, 0x801003b, 0, 0); + subWriteReg(&AP_SPIF->config, 14, 14, 1); //enable wp bit(14) + AP_SPIF->low_wr_protection = 0; AP_SPIF->up_wr_protection = 0x10; @@ -198,7 +203,9 @@ static void hal_low_power_io_init(void) drv_pm_ram_retention(RET_SRAM0 | RET_SRAM1 | RET_SRAM2); //hal_pwrmgr_RAM_retention(RET_SRAM0); hal_pwrmgr_RAM_retention_set(); - //hal_pwrmgr_LowCurrentLdo_enable(); +#if (defined(CONFIG_SYS_CLK_XTAL_16M) && CONFIG_SYS_CLK_XTAL_16M > 0) + hal_pwrmgr_LowCurrentLdo_enable(); +#endif //========= low power module clk gate #if(PHY_MCU_TYPE==MCU_BUMBEE_CK802) *(volatile uint32_t *)0x40000008 = 0x001961f1; // @@ -233,9 +240,12 @@ __attribute__((section(".__data_copy_first__"))) void check_before_startup() { //check_data = -1; } - void SystemInit(void) { + // /* USE CONFIG_WDT=1 to enable wdt */ + extern void wdt_init(void); + wdt_init(); + subWriteReg(&AP_SPIF->config, 14, 14, 1); //enable wp bit(14) /* Clear active and pending IRQ */ VIC->IABR[0] = 0x0; VIC->ICPR[0] = 0xFFFFFFFF; @@ -243,7 +253,7 @@ void SystemInit(void) __disable_irq(); - g_system_clk = SYS_CLK_DLL_48M; + g_system_clk = SYS_CLK_XTAL_16M; #ifdef CONFIG_USE_XTAL_CLK g_clk32K_config = CLK_32K_XTAL;//CLK_32K_XTAL,CLK_32K_RCOSC @@ -251,11 +261,11 @@ void SystemInit(void) g_clk32K_config = CLK_32K_RCOSC;//CLK_32K_XTAL,CLK_32K_RCOSC #endif - g_spif_ref_clk = SYS_CLK_DLL_64M; + g_spif_ref_clk = SYS_CLK_RC_32M; - - - JUMP_FUNCTION(CK802_TRAP_C) = (uint32_t)&trap_c; //register trap irq handler + + extern void sram_HardFault_Handler(void); + JUMP_FUNCTION(CK802_TRAP_C) = (uint32_t)&sram_HardFault_Handler; //register trap irq handler #ifdef CONFIG_KERNEL_NONE _system_init_for_baremetal(); @@ -267,12 +277,13 @@ void SystemInit(void) hal_rfphy_init(); + int i = 0; PHY6220_Vectors[0] = (uint32_t)Reset_Handler; for (i = 1; i < 32; i++) { - PHY6220_Vectors[i] = (uint32_t)Default_Handler; + PHY6220_Vectors[i] = (uint32_t)sram_HardFault_Handler; } PHY6220_Vectors[32] = (uint32_t)tspend_handler; @@ -290,7 +301,8 @@ void SystemInit(void) //replace TS_PEND IRQ with IRQ0 drv_irq_enable(0); - csi_vic_set_prio(0, 3); + csi_vic_set_prio(0, 3); + spif_read_id(NULL); hal_cache_init(); hal_mpu_config(); diff --git a/trap_c.c b/trap_c.c index 0a764a7c30bb7189151a1632b9a2df5e76146b3f..2d1e126da92c3c302c64aed2b6888770d5a1f031 100755 --- a/trap_c.c +++ b/trap_c.c @@ -27,6 +27,16 @@ #include void (*trap_c_callback)(void); +extern char * strerror(int errnum); +extern void drv_reboot(int cmd); + + +static void except_process_function(int errno, const char *file, int line, const char *func_name, void *caller) +{ + printf("Except! errno is %s, caller: %p\n", strerror(errno), caller); + drv_reboot(1); +} + void trap_c(uint32_t *regs) { @@ -47,9 +57,11 @@ void trap_c(uint32_t *regs) printf("epsr: %8x\n", regs[16]); printf("epc : %8x\n", regs[17]); - if (trap_c_callback) { - trap_c_callback(); - } + except_process_function(1, __FILE__, __LINE__, __func__, NULL); + +// if (trap_c_callback) { +// trap_c_callback(); +// } while (1); }