# 16QAM

**Repository Path**: zdevt/16QAM

## Basic Information

- **Project Name**: 16QAM
- **Description**: https://github.com/qxdn/16QAM.git
- **Primary Language**: Verilog
- **License**: Not specified
- **Default Branch**: master
- **Homepage**: None
- **GVP Project**: No

## Statistics

- **Stars**: 0
- **Forks**: 0
- **Created**: 2024-04-29
- **Last Updated**: 2024-04-29

## Categories & Tags

**Categories**: Uncategorized

**Tags**: None

## README

## 16QAM
使用FPGA完成16QAM的调制解调


设置FIR的IP核的时候不小心存错地方了，懒得改了

[other](./other)里面是matlab进行正余弦采样和滤波器设计的代码

[报告](https://github.com/qxdn/16QAM/releases/download/1.0.0/default.pdf)

## TODO
- [x] 上传报告