# Vitis_Model_Composer **Repository Path**: zdevt/Vitis_Model_Composer ## Basic Information - **Project Name**: Vitis_Model_Composer - **Description**: https://github.com/Xilinx/Vitis_Model_Composer.git - **Primary Language**: Verilog - **License**: Not specified - **Default Branch**: 2024.1 - **Homepage**: None - **GVP Project**: No ## Statistics - **Stars**: 0 - **Forks**: 0 - **Created**: 2024-06-07 - **Last Updated**: 2024-12-17 ## Categories & Tags **Categories**: Uncategorized **Tags**: None ## README

Rapid design exploration using Vitis Model Composer

Within the Simulink environment, Vitis Model Composer offers a range of performance-optimized blocks that facilitate the design and implementation of DSP algorithms on AMD devices. The inclusion of the Vitis Model Composer AI Engine, HLS, and HDL libraries enables efficient algorithm exploration and greatly expedites the path towards production.

To learn more, visit the Vitis Model Composer website.

Where should you start?

Are you interested in accelerating your development effort using Vitis Model Composer? Here is where to start:

What's new in 2024.1?

Examples

Tutorials

Quick Guides


Copyright 2024 Advanced Micro Devices, Inc.

Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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